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Configuration registers (Spartan 3, 3E)

TODO: document

COR.S3

This is the Spartan 3 version of COR.

spartan3 REG.COR.S3 rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 STARTUP:LCK_CYCLE[0]
B7 STARTUP:LCK_CYCLE[1]
B8 STARTUP:LCK_CYCLE[2]
B9 STARTUP:MATCH_CYCLE[0]
B10 STARTUP:MATCH_CYCLE[1]
B11 STARTUP:MATCH_CYCLE[2]
B12 STARTUP:DONE_CYCLE[0]
B13 STARTUP:DONE_CYCLE[1]
B14 STARTUP:DONE_CYCLE[2]
B15 STARTUP:STARTUPCLK[0]
B16 STARTUP:STARTUPCLK[1]
B17 STARTUP:BUSCLK_FREQ[0]
B18 STARTUP:BUSCLK_FREQ[1]
B19 STARTUP:CONFIG_RATE[0]
B20 STARTUP:CONFIG_RATE[1]
B21 STARTUP:CONFIG_RATE[2]
B22 -
B23 CAPTURE:ONESHOT
B24 STARTUP:DRIVE_DONE
B25 STARTUP:DONE_PIPE
B26 STARTUP:DCM_SHUTDOWN
B27 -
B28 -
B29 ~STARTUP:CRC
B30 STARTUP:VRDSEL[0]
B31 STARTUP:VRDSEL[1]
CAPTURE:ONESHOT 0.F0.B23
STARTUP:DCM_SHUTDOWN 0.F0.B26
STARTUP:DONE_PIPE 0.F0.B25
STARTUP:DRIVE_DONE 0.F0.B24
non-inverted [0]
STARTUP:BUSCLK_FREQ 0.F0.B18 0.F0.B17
100 0 0
25 0 1
50 1 0
200 1 1
STARTUP:CONFIG_RATE 0.F0.B21 0.F0.B20 0.F0.B19
6 0 0 0
12 0 0 1
25 0 1 0
50 0 1 1
3 1 0 0
100 1 1 0
STARTUP:CRC 0.F0.B29
inverted ~[0]
STARTUP:DONE_CYCLE 0.F0.B14 0.F0.B13 0.F0.B12
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
KEEP 1 1 1
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
DONE 1 1 0
KEEP 1 1 1
STARTUP:LCK_CYCLE 0.F0.B8 0.F0.B7 0.F0.B6
STARTUP:MATCH_CYCLE 0.F0.B11 0.F0.B10 0.F0.B9
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1
STARTUP:STARTUPCLK 0.F0.B16 0.F0.B15
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.F0.B31 0.F0.B30
100 0 0
95 0 1
90 1 0
80 1 1

COR.FC

This is the FPGAcore version of COR.

spartan3 REG.COR.FC rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 -
B7 -
B8 -
B9 -
B10 -
B11 -
B12 STARTUP:DONE_CYCLE[0]
B13 STARTUP:DONE_CYCLE[1]
B14 STARTUP:DONE_CYCLE[2]
B15 STARTUP:STARTUPCLK[0]
B16 STARTUP:STARTUPCLK[1]
B17 STARTUP:BUSCLK_FREQ[0]
B18 STARTUP:BUSCLK_FREQ[1]
B19 STARTUP:CONFIG_RATE[0]
B20 STARTUP:CONFIG_RATE[1]
B21 STARTUP:CONFIG_RATE[2]
B22 -
B23 CAPTURE:ONESHOT
B24 STARTUP:DRIVE_DONE
B25 STARTUP:DONE_PIPE
B26 -
B27 -
B28 -
B29 ~STARTUP:CRC
B30 STARTUP:VRDSEL[0]
B31 STARTUP:VRDSEL[1]
CAPTURE:ONESHOT 0.F0.B23
STARTUP:DONE_PIPE 0.F0.B25
STARTUP:DRIVE_DONE 0.F0.B24
non-inverted [0]
STARTUP:BUSCLK_FREQ 0.F0.B18 0.F0.B17
100 0 0
25 0 1
50 1 0
200 1 1
STARTUP:CONFIG_RATE 0.F0.B21 0.F0.B20 0.F0.B19
6 0 0 0
12 0 0 1
25 0 1 0
50 0 1 1
3 1 0 0
100 1 1 0
STARTUP:CRC 0.F0.B29
inverted ~[0]
STARTUP:DONE_CYCLE 0.F0.B14 0.F0.B13 0.F0.B12
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
KEEP 1 1 1
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
DONE 1 1 0
KEEP 1 1 1
STARTUP:STARTUPCLK 0.F0.B16 0.F0.B15
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.F0.B31 0.F0.B30
100 0 0
95 0 1
90 1 0
80 1 1

COR.S3E

This is the Spartan 3E version of COR.

spartan3 REG.COR.S3E rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 STARTUP:LCK_CYCLE[0]
B7 STARTUP:LCK_CYCLE[1]
B8 STARTUP:LCK_CYCLE[2]
B9 -
B10 -
B11 -
B12 STARTUP:DONE_CYCLE[0]
B13 STARTUP:DONE_CYCLE[1]
B14 STARTUP:DONE_CYCLE[2]
B15 STARTUP:STARTUPCLK[0]
B16 STARTUP:STARTUPCLK[1]
B17 STARTUP:BUSCLK_FREQ[0]
B18 STARTUP:BUSCLK_FREQ[1]
B19 STARTUP:CONFIG_RATE[0]
B20 STARTUP:CONFIG_RATE[1]
B21 STARTUP:CONFIG_RATE[2]
B22 -
B23 CAPTURE:ONESHOT
B24 STARTUP:DRIVE_DONE
B25 STARTUP:DONE_PIPE
B26 STARTUP:DCM_SHUTDOWN
B27 -
B28 STARTUP:MULTIBOOT_ENABLE
B29 ~STARTUP:CRC
B30 STARTUP:VRDSEL[0]
B31 STARTUP:VRDSEL[1]
CAPTURE:ONESHOT 0.F0.B23
STARTUP:DCM_SHUTDOWN 0.F0.B26
STARTUP:DONE_PIPE 0.F0.B25
STARTUP:DRIVE_DONE 0.F0.B24
STARTUP:MULTIBOOT_ENABLE 0.F0.B28
non-inverted [0]
STARTUP:BUSCLK_FREQ 0.F0.B18 0.F0.B17
100 0 0
25 0 1
50 1 0
200 1 1
STARTUP:CONFIG_RATE 0.F0.B21 0.F0.B20 0.F0.B19
1 0 0 0
3 0 0 1
6 0 1 0
12 0 1 1
50 1 0 0
25 1 1 0
STARTUP:CRC 0.F0.B29
inverted ~[0]
STARTUP:DONE_CYCLE 0.F0.B14 0.F0.B13 0.F0.B12
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
KEEP 1 1 1
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
DONE 1 1 0
KEEP 1 1 1
STARTUP:LCK_CYCLE 0.F0.B8 0.F0.B7 0.F0.B6
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1
STARTUP:STARTUPCLK 0.F0.B16 0.F0.B15
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.F0.B31 0.F0.B30
70_75 0 0
90 1 0
80 1 1

CTL.S3

This is the Spartan 3 and Spartan 3E version of CTL.

spartan3 REG.CTL.S3 rect R0
BitFrame
F0
B0 MISC:GTS_USR_B
B1 MISC:VGG_TEST
B2 MISC:BCLK_TEST
B3 MISC:PERSIST
B4 MISC:SECURITY[0]
B5 MISC:SECURITY[1]
MISC:BCLK_TEST 0.F0.B2
MISC:GTS_USR_B 0.F0.B0
MISC:PERSIST 0.F0.B3
MISC:VGG_TEST 0.F0.B1
non-inverted [0]
MISC:SECURITY 0.F0.B5 0.F0.B4
NONE 0 0
LEVEL1 0 1
LEVEL2 1 0

Device data

Device MISC:SEND_VGG_DEFAULT MISC:VGG_SENDMAX_DEFAULT
[3] [2] [1] [0] [0]
xc3s50 1 0 0 0 1
xa3s50 1 0 0 0 1
xc3s200 1 0 0 0 1
xa3s200 1 0 0 0 1
xc3s400 1 0 0 0 1
xa3s400 1 0 0 0 1
xc3s1000 1 0 0 0 1
xa3s1000 1 0 0 0 1
xc3s1000l 1 0 0 0 1
xc3s1500 1 0 0 0 1
xa3s1500 1 0 0 0 1
xc3s1500l 1 0 0 0 1
xc3s2000 1 0 0 0 1
xc3s4000 1 0 0 0 1
xc3s4000l 1 0 0 0 1
xc3s5000 1 0 0 0 1
xcexf10 0 0 0 0 1
xcexf20 0 0 0 0 1
xcexf40 0 0 0 0 1
xc3s100e 1 0 0 0 1
xa3s100e 1 0 0 0 1
xc3s250e 1 0 0 0 1
xa3s250e 1 0 0 0 1
xc3s500e 1 0 0 0 1
xa3s500e 1 0 0 0 1
xc3s1200e 1 0 0 0 1
xa3s1200e 1 0 0 0 1
xc3s1600e 1 0 0 0 1
xa3s1600e 1 0 0 0 1
xc3s50a 1 1 1 1 1
xc3s50an 1 1 1 1 1
xc3s200a 1 1 1 1 1
xa3s200a 1 1 1 1 1
xc3s200an 1 1 1 1 1
xc3s400a 1 1 1 1 1
xa3s400a 1 1 1 1 1
xc3s400an 1 1 1 1 1
xc3s700a 1 1 1 1 1
xa3s700a 1 1 1 1 1
xc3s700an 1 1 1 1 1
xc3s1400a 1 1 1 1 1
xa3s1400a 1 1 1 1 1
xc3s1400an 1 1 1 1 1
xc3sd1800a 1 1 1 1 1
xa3sd1800a 1 1 1 1 1
xc3sd3400a 1 1 1 1 1
xa3sd3400a 1 1 1 1 1