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TODO: document

CNR_SW_S3

This tile is used on Spartan 3.

Tile CNR_SW_S3

Cells: 1

Bel DCI[0]

spartan3 CNR_SW_S3 bel DCI[0]
PinDirectionWires
ADDRESS0outputOUT_SEC[0]
ADDRESS1outputOUT_SEC[1]
ADDRESS2outputOUT_SEC[2]
DATAoutputOUT_SEC[3]
DCI_CLKinputIMUX_DATA[23]
DCI_DONEoutputOUT_SEC[4]
DCI_RESETinputIMUX_DATA[22]
HI_LO_NinputIMUX_DATA[21]
HI_LO_PinputIMUX_DATA[20]
IOUPDATEoutputOUT_SEC[8]
N_OR_PoutputOUT_SEC[5]
SCLKoutputOUT_SEC[6]
UPDATEoutputOUT_SEC[7]

Bel DCI[1]

spartan3 CNR_SW_S3 bel DCI[1]
PinDirectionWires
ADDRESS0outputOUT_SEC[0]
ADDRESS1outputOUT_SEC[1]
ADDRESS2outputOUT_SEC[2]
DATAoutputOUT_SEC[3]
DCI_CLKinputIMUX_DATA[15]
DCI_DONEoutputOUT_SEC[4]
DCI_RESETinputIMUX_DATA[14]
HI_LO_NinputIMUX_DATA[13]
HI_LO_PinputIMUX_DATA[12]
IOUPDATEoutputOUT_SEC[8]
N_OR_PoutputOUT_SEC[5]
SCLKoutputOUT_SEC[6]
UPDATEoutputOUT_SEC[7]

Bel DCIRESET[0]

spartan3 CNR_SW_S3 bel DCIRESET[0]
PinDirectionWires
RSTinputIMUX_DATA[19]

Bel DCIRESET[1]

spartan3 CNR_SW_S3 bel DCIRESET[1]
PinDirectionWires
RSTinputIMUX_DATA[11]

Bel wires

spartan3 CNR_SW_S3 bel wires
WirePins
IMUX_DATA[11]DCIRESET[1].RST
IMUX_DATA[12]DCI[1].HI_LO_P
IMUX_DATA[13]DCI[1].HI_LO_N
IMUX_DATA[14]DCI[1].DCI_RESET
IMUX_DATA[15]DCI[1].DCI_CLK
IMUX_DATA[19]DCIRESET[0].RST
IMUX_DATA[20]DCI[0].HI_LO_P
IMUX_DATA[21]DCI[0].HI_LO_N
IMUX_DATA[22]DCI[0].DCI_RESET
IMUX_DATA[23]DCI[0].DCI_CLK
OUT_SEC[0]DCI[0].ADDRESS0, DCI[1].ADDRESS0
OUT_SEC[1]DCI[0].ADDRESS1, DCI[1].ADDRESS1
OUT_SEC[2]DCI[0].ADDRESS2, DCI[1].ADDRESS2
OUT_SEC[3]DCI[0].DATA, DCI[1].DATA
OUT_SEC[4]DCI[0].DCI_DONE, DCI[1].DCI_DONE
OUT_SEC[5]DCI[0].N_OR_P, DCI[1].N_OR_P
OUT_SEC[6]DCI[0].SCLK, DCI[1].SCLK
OUT_SEC[7]DCI[0].UPDATE, DCI[1].UPDATE
OUT_SEC[8]DCI[0].IOUPDATE, DCI[1].IOUPDATE

Bitstream

spartan3 CNR_SW_S3 rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SW_S3 rect R0
BitFrame
F0 F1
B63 DCIRESET[1]:ENABLE DCIRESET[0]:ENABLE
B62 DCI[1]:TEST_ENABLE DCI[0]:TEST_ENABLE
B61 DCI[1]:FORCE_DONE_HIGH DCI[0]:FORCE_DONE_HIGH
B60 - -
B59 DCI[1]:PMASK_TERM_SPLIT[3] DCI[0]:PMASK_TERM_SPLIT[3]
B58 DCI[1]:PMASK_TERM_SPLIT[2] DCI[0]:PMASK_TERM_SPLIT[2]
B57 DCI[1]:PMASK_TERM_SPLIT[1] DCI[0]:PMASK_TERM_SPLIT[1]
B56 DCI[1]:PMASK_TERM_SPLIT[0] DCI[0]:PMASK_TERM_SPLIT[0]
B55 - -
B54 DCI[1]:PMASK_TERM_VCC[3] DCI[0]:PMASK_TERM_VCC[3]
B53 DCI[1]:PMASK_TERM_VCC[2] DCI[0]:PMASK_TERM_VCC[2]
B52 DCI[1]:PMASK_TERM_VCC[1] DCI[0]:PMASK_TERM_VCC[1]
B51 DCI[1]:PMASK_TERM_VCC[0] DCI[0]:PMASK_TERM_VCC[0]
B50 - MISC:DCI_TEST_MUX[0]
B49 DCI[1]:NMASK_TERM_SPLIT[3] DCI[0]:NMASK_TERM_SPLIT[3]
B48 DCI[1]:NMASK_TERM_SPLIT[2] DCI[0]:NMASK_TERM_SPLIT[2]
B47 DCI[1]:NMASK_TERM_SPLIT[1] DCI[0]:NMASK_TERM_SPLIT[1]
B46 DCI[1]:NMASK_TERM_SPLIT[0] DCI[0]:NMASK_TERM_SPLIT[0]
B45 DCI[1]:QUIET DCI[0]:QUIET
B44 DCI[1]:ENABLE DCI[0]:ENABLE
B43 DCI[0]:LVDSBIAS[2] DCI[1]:LVDSBIAS[2]
B42 DCI[0]:LVDSBIAS[3] DCI[1]:LVDSBIAS[3]
B41 DCI[0]:LVDSBIAS[4] DCI[1]:LVDSBIAS[4]
B40 DCI[0]:LVDSBIAS[5] DCI[1]:LVDSBIAS[5]
B39 DCI[0]:LVDSBIAS[6] DCI[1]:LVDSBIAS[6]
B38 DCI[0]:LVDSBIAS[7] DCI[1]:LVDSBIAS[7]
B37 DCI[0]:LVDSBIAS[8] DCI[1]:LVDSBIAS[8]
B36 DCI[0]:LVDSBIAS[9] DCI[1]:LVDSBIAS[9]
B35 DCI[0]:LVDSBIAS[10] DCI[1]:LVDSBIAS[10]
B34 DCI[0]:LVDSBIAS[11] DCI[1]:LVDSBIAS[11]
B33 DCI[0]:LVDSBIAS[12] DCI[1]:LVDSBIAS[12]
B32 - DCI[1]:LVDSBIAS[0]
B31 - DCI[1]:LVDSBIAS[1]
B30 MISC:M2PIN[0] -
B29 MISC:M2PIN[1] -
B28 MISC:M0PIN[0] -
B27 MISC:M0PIN[1] -
B26 MISC:M1PIN[0] -
B25 MISC:M1PIN[1] -
B24 DCI[0]:LVDSBIAS[0] -
B23 DCI[0]:LVDSBIAS[1] -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - MISC:VGG_ENABLE_OFFCHIP
B12 - MISC:VGG_SENDMAX
B11 - MISC:SEND_VGG[3]
B10 - MISC:SEND_VGG[2]
B9 - MISC:SEND_VGG[1]
B8 - MISC:SEND_VGG[0]
B7 - -
B6 - -
B5 - MISC:DCM_ENABLE
B4 - MISC:DCI_OSC_SEL[2]
B3 - MISC:DCI_OSC_SEL[1]
B2 - MISC:DCI_OSC_SEL[0]
B1 - MISC:GATE_GHIGH
B0 - MISC:DCI_CLK_ENABLE
DCIRESET[0]:ENABLE 0.F1.B63
DCIRESET[1]:ENABLE 0.F0.B63
DCI[0]:ENABLE 0.F1.B44
DCI[0]:FORCE_DONE_HIGH 0.F1.B61
DCI[0]:QUIET 0.F1.B45
DCI[0]:TEST_ENABLE 0.F1.B62
DCI[1]:ENABLE 0.F0.B44
DCI[1]:FORCE_DONE_HIGH 0.F0.B61
DCI[1]:QUIET 0.F0.B45
DCI[1]:TEST_ENABLE 0.F0.B62
MISC:DCI_CLK_ENABLE 0.F1.B0
MISC:DCM_ENABLE 0.F1.B5
MISC:GATE_GHIGH 0.F1.B1
MISC:VGG_ENABLE_OFFCHIP 0.F1.B13
MISC:VGG_SENDMAX 0.F1.B12
non-inverted [0]
DCI[0]:LVDSBIAS 0.F0.B33 0.F0.B34 0.F0.B35 0.F0.B36 0.F0.B37 0.F0.B38 0.F0.B39 0.F0.B40 0.F0.B41 0.F0.B42 0.F0.B43 0.F0.B23 0.F0.B24
DCI[1]:LVDSBIAS 0.F1.B33 0.F1.B34 0.F1.B35 0.F1.B36 0.F1.B37 0.F1.B38 0.F1.B39 0.F1.B40 0.F1.B41 0.F1.B42 0.F1.B43 0.F1.B31 0.F1.B32
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI[0]:NMASK_TERM_SPLIT 0.F1.B49 0.F1.B48 0.F1.B47 0.F1.B46
DCI[0]:PMASK_TERM_SPLIT 0.F1.B59 0.F1.B58 0.F1.B57 0.F1.B56
DCI[0]:PMASK_TERM_VCC 0.F1.B54 0.F1.B53 0.F1.B52 0.F1.B51
DCI[1]:NMASK_TERM_SPLIT 0.F0.B49 0.F0.B48 0.F0.B47 0.F0.B46
DCI[1]:PMASK_TERM_SPLIT 0.F0.B59 0.F0.B58 0.F0.B57 0.F0.B56
DCI[1]:PMASK_TERM_VCC 0.F0.B54 0.F0.B53 0.F0.B52 0.F0.B51
MISC:SEND_VGG 0.F1.B11 0.F1.B10 0.F1.B9 0.F1.B8
non-inverted [3] [2] [1] [0]
MISC:DCI_OSC_SEL 0.F1.B4 0.F1.B3 0.F1.B2
non-inverted [2] [1] [0]
MISC:DCI_TEST_MUX 0.F1.B50
DCI0 0
DCI1 1
MISC:M0PIN 0.F0.B27 0.F0.B28
MISC:M1PIN 0.F0.B25 0.F0.B26
MISC:M2PIN 0.F0.B29 0.F0.B30
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1

CNR_SW_FC

This tile is used on FPGAcore.

Tile CNR_SW_FC

Cells: 1

Bel MISR

spartan3 CNR_SW_FC bel MISR
PinDirectionWires
CLKinputIMUX_CLK[3]

Bel wires

spartan3 CNR_SW_FC bel wires
WirePins
IMUX_CLK[3]MISR.CLK

Bitstream

spartan3 CNR_SW_FC rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SW_FC rect R0
BitFrame
F0 F1
B13 - MISC:VGG_ENABLE_OFFCHIP
B12 - MISC:VGG_SENDMAX
B11 - MISC:SEND_VGG[3]
B10 - MISC:SEND_VGG[2]
B9 - MISC:SEND_VGG[1]
B8 - MISC:SEND_VGG[0]
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 MISC:MISR_CLOCK -
B0 MISC:MISR_RESET -
MISC:MISR_CLOCK 0.F0.B1
MISC:MISR_RESET 0.F0.B0
MISC:VGG_ENABLE_OFFCHIP 0.F1.B13
MISC:VGG_SENDMAX 0.F1.B12
non-inverted [0]
MISC:SEND_VGG 0.F1.B11 0.F1.B10 0.F1.B9 0.F1.B8
non-inverted [3] [2] [1] [0]

CNR_SW_S3E

This tile is used on Spartan 3E.

Tile CNR_SW_S3E

Cells: 1

Bitstream

spartan3 CNR_SW_S3E rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SW_S3E rect R0
BitFrame
F0 F1
B43 - BANK:LVDSBIAS_1[6]
B42 - BANK:LVDSBIAS_1[7]
B41 - BANK:LVDSBIAS_1[8]
B40 - BANK:LVDSBIAS_1[9]
B39 - BANK:LVDSBIAS_1[10]
B38 - BANK:LVDSBIAS_0[5]
B37 - BANK:LVDSBIAS_0[6]
B36 - BANK:LVDSBIAS_0[7]
B35 - BANK:LVDSBIAS_0[8]
B34 - BANK:LVDSBIAS_0[9]
B33 - BANK:LVDSBIAS_0[10]
B32 - BANK:LVDSBIAS_1[0]
B31 - BANK:LVDSBIAS_0[0]
B30 - BANK:LVDSBIAS_1[1]
B29 - BANK:LVDSBIAS_1[2]
B28 - BANK:LVDSBIAS_1[3]
B27 - BANK:LVDSBIAS_1[4]
B26 - BANK:LVDSBIAS_0[1]
B25 - BANK:LVDSBIAS_0[2]
B24 - BANK:LVDSBIAS_0[3]
B23 - BANK:LVDSBIAS_0[4]
B22 - BANK:LVDSBIAS_1[5]
B21 - MISC:TEMPSENSOR[0]
B20 - -
B19 - -
B18 - MISC:TEMPSENSOR[1]
B17 - MISC:TEMPSENSOR[2]
B16 - -
B15 - -
B14 - -
B13 - MISC:VGG_ENABLE_OFFCHIP
B12 - MISC:VGG_SENDMAX
B11 - MISC:SEND_VGG[3]
B10 - MISC:SEND_VGG[2]
B9 - MISC:SEND_VGG[1]
B8 - MISC:SEND_VGG[0]
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
BANK:LVDSBIAS_0 0.F1.B33 0.F1.B34 0.F1.B35 0.F1.B36 0.F1.B37 0.F1.B38 0.F1.B23 0.F1.B24 0.F1.B25 0.F1.B26 0.F1.B31
BANK:LVDSBIAS_1 0.F1.B39 0.F1.B40 0.F1.B41 0.F1.B42 0.F1.B43 0.F1.B22 0.F1.B27 0.F1.B28 0.F1.B29 0.F1.B30 0.F1.B32
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:SEND_VGG 0.F1.B11 0.F1.B10 0.F1.B9 0.F1.B8
non-inverted [3] [2] [1] [0]
MISC:TEMPSENSOR 0.F1.B17 0.F1.B18 0.F1.B21
NONE 0 0 0
THERM 0 0 1
PGATE 0 1 1
BG 1 0 1
CGATE 1 1 1
MISC:VGG_ENABLE_OFFCHIP 0.F1.B13
MISC:VGG_SENDMAX 0.F1.B12
non-inverted [0]

CNR_SW_S3A

This tile is used on Spartan 3A.

Tile CNR_SW_S3A

Cells: 1

Bitstream

spartan3 CNR_SW_S3A rect TERM_H
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 CNR_SW_S3A rect R0
BitFrame
F0 F1
B63 - BANK:LVDSBIAS_1[5]
B62 BANK:LVDSBIAS_1[10] BANK:LVDSBIAS_1[4]
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - BANK:LVDSBIAS_0[4]
B35 - BANK:LVDSBIAS_1[8]
B34 - BANK:LVDSBIAS_0[8]
B33 - BANK:LVDSBIAS_0[9]
B32 - BANK:LVDSBIAS_0[0]
B31 BANK:LVDSBIAS_0[2] -
B30 BANK:LVDSBIAS_1[6] BANK:LVDSBIAS_0[3]
B29 BANK:LVDSBIAS_1[9] -
B28 BANK:LVDSBIAS_1[1] BANK:LVDSBIAS_0[5]
B27 BANK:LVDSBIAS_0[1] BANK:LVDSBIAS_1[0]
B26 BANK:LVDSBIAS_1[2] BANK:LVDSBIAS_1[3]
B25 - -
B24 MISC:MOSI2PIN[1] MISC:MOSI2PIN[0]
B23 - MISC:VGG_ENABLE_OFFCHIP
B22 - MISC:VGG_SENDMAX
B21 - MISC:SEND_VGG[3]
B20 - MISC:SEND_VGG[2]
B19 - MISC:SEND_VGG[1]
B18 - MISC:SEND_VGG[0]
B17 - -
B16 - -
B15 MISC:CCLK2PIN[0] MISC:CCLK2PIN[1]
B14 - MISC:UNK_ALWAYS_SET[3]
B13 MISC:UNK_ALWAYS_SET[1] -
B12 MISC:UNK_ALWAYS_SET[0] MISC:UNK_ALWAYS_SET[2]
B11 - BANK:LVDSBIAS_0[7]
B10 BANK:LVDSBIAS_0[6] BANK:LVDSBIAS_0[10]
B9 BANK:LVDSBIAS_0[11] BANK:LVDSBIAS_1[7]
B8 - -
B7 MISC:TEMPSENSOR[0] MISC:TEMPSENSOR[1]
B6 BANK:LVDSBIAS_1[11] -
B5 - -
B4 - MISC:TEMPSENSOR[3]
B3 - MISC:TEMPSENSOR[2]
B2 - -
B1 - -
B0 - -
BANK:LVDSBIAS_0 0.F0.B9 0.F1.B10 0.F1.B33 0.F1.B34 0.F1.B11 0.F0.B10 0.F1.B28 0.F1.B36 0.F1.B30 0.F0.B31 0.F0.B27 0.F1.B32
BANK:LVDSBIAS_1 0.F0.B6 0.F0.B62 0.F0.B29 0.F1.B35 0.F1.B9 0.F0.B30 0.F1.B63 0.F1.B62 0.F1.B26 0.F0.B26 0.F0.B28 0.F1.B27
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:CCLK2PIN 0.F1.B15 0.F0.B15
MISC:MOSI2PIN 0.F0.B24 0.F1.B24
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1
MISC:SEND_VGG 0.F1.B21 0.F1.B20 0.F1.B19 0.F1.B18
MISC:UNK_ALWAYS_SET 0.F1.B14 0.F1.B12 0.F0.B13 0.F0.B12
non-inverted [3] [2] [1] [0]
MISC:TEMPSENSOR 0.F1.B4 0.F1.B3 0.F1.B7 0.F0.B7
NONE 0 0 0 0
THERM 0 0 1 1
PGATE 0 1 1 1
BG 1 0 1 1
CGATE 1 1 1 1
MISC:VGG_ENABLE_OFFCHIP 0.F1.B23
MISC:VGG_SENDMAX 0.F1.B22
non-inverted [0]