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South-west

TODO: document

LL.S3

This tile is used on Spartan 3.

Tile LL.S3

Cells: 1 IRIs: 0

Bel DCI0

spartan3 LL.S3 bel DCI0
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA23
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA22
HI_LO_NinputIMUX.DATA21
HI_LO_PinputIMUX.DATA20
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCI1

spartan3 LL.S3 bel DCI1
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA15
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA14
HI_LO_NinputIMUX.DATA13
HI_LO_PinputIMUX.DATA12
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCIRESET0

spartan3 LL.S3 bel DCIRESET0
PinDirectionWires
RSTinputIMUX.DATA19

Bel DCIRESET1

spartan3 LL.S3 bel DCIRESET1
PinDirectionWires
RSTinputIMUX.DATA11

Bel wires

spartan3 LL.S3 bel wires
WirePins
IMUX.DATA11DCIRESET1.RST
IMUX.DATA12DCI1.HI_LO_P
IMUX.DATA13DCI1.HI_LO_N
IMUX.DATA14DCI1.DCI_RESET
IMUX.DATA15DCI1.DCI_CLK
IMUX.DATA19DCIRESET0.RST
IMUX.DATA20DCI0.HI_LO_P
IMUX.DATA21DCI0.HI_LO_N
IMUX.DATA22DCI0.DCI_RESET
IMUX.DATA23DCI0.DCI_CLK
OUT.SEC0DCI0.ADDRESS0, DCI1.ADDRESS0
OUT.SEC1DCI0.ADDRESS1, DCI1.ADDRESS1
OUT.SEC2DCI0.ADDRESS2, DCI1.ADDRESS2
OUT.SEC3DCI0.DATA, DCI1.DATA
OUT.SEC4DCI0.DCI_DONE, DCI1.DCI_DONE
OUT.SEC5DCI0.N_OR_P, DCI1.N_OR_P
OUT.SEC6DCI0.SCLK, DCI1.SCLK
OUT.SEC7DCI0.UPDATE, DCI1.UPDATE
OUT.SEC8DCI0.IOUPDATE, DCI1.IOUPDATE

Bitstream

spartan3 LL.S3 bittile 0
BitFrame
0 1
63 DCIRESET1:ENABLE DCIRESET0:ENABLE
62 DCI1:TEST_ENABLE DCI0:TEST_ENABLE
61 DCI1:FORCE_DONE_HIGH DCI0:FORCE_DONE_HIGH
60 - -
59 DCI1:PMASK_TERM_SPLIT[3] DCI0:PMASK_TERM_SPLIT[3]
58 DCI1:PMASK_TERM_SPLIT[2] DCI0:PMASK_TERM_SPLIT[2]
57 DCI1:PMASK_TERM_SPLIT[1] DCI0:PMASK_TERM_SPLIT[1]
56 DCI1:PMASK_TERM_SPLIT[0] DCI0:PMASK_TERM_SPLIT[0]
55 - -
54 DCI1:PMASK_TERM_VCC[3] DCI0:PMASK_TERM_VCC[3]
53 DCI1:PMASK_TERM_VCC[2] DCI0:PMASK_TERM_VCC[2]
52 DCI1:PMASK_TERM_VCC[1] DCI0:PMASK_TERM_VCC[1]
51 DCI1:PMASK_TERM_VCC[0] DCI0:PMASK_TERM_VCC[0]
50 - MISC:DCI_TEST_MUX[0]
49 DCI1:NMASK_TERM_SPLIT[3] DCI0:NMASK_TERM_SPLIT[3]
48 DCI1:NMASK_TERM_SPLIT[2] DCI0:NMASK_TERM_SPLIT[2]
47 DCI1:NMASK_TERM_SPLIT[1] DCI0:NMASK_TERM_SPLIT[1]
46 DCI1:NMASK_TERM_SPLIT[0] DCI0:NMASK_TERM_SPLIT[0]
45 DCI1:QUIET DCI0:QUIET
44 DCI1:ENABLE DCI0:ENABLE
43 DCI0:LVDSBIAS[2] DCI1:LVDSBIAS[2]
42 DCI0:LVDSBIAS[3] DCI1:LVDSBIAS[3]
41 DCI0:LVDSBIAS[4] DCI1:LVDSBIAS[4]
40 DCI0:LVDSBIAS[5] DCI1:LVDSBIAS[5]
39 DCI0:LVDSBIAS[6] DCI1:LVDSBIAS[6]
38 DCI0:LVDSBIAS[7] DCI1:LVDSBIAS[7]
37 DCI0:LVDSBIAS[8] DCI1:LVDSBIAS[8]
36 DCI0:LVDSBIAS[9] DCI1:LVDSBIAS[9]
35 DCI0:LVDSBIAS[10] DCI1:LVDSBIAS[10]
34 DCI0:LVDSBIAS[11] DCI1:LVDSBIAS[11]
33 DCI0:LVDSBIAS[12] DCI1:LVDSBIAS[12]
32 - DCI1:LVDSBIAS[0]
31 - DCI1:LVDSBIAS[1]
30 MISC:M2PIN[0] -
29 MISC:M2PIN[1] -
28 MISC:M0PIN[0] -
27 MISC:M0PIN[1] -
26 MISC:M1PIN[0] -
25 MISC:M1PIN[1] -
24 DCI0:LVDSBIAS[0] -
23 DCI0:LVDSBIAS[1] -
22 - -
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - -
14 - -
13 - MISC:VGG_ENABLE_OFFCHIP
12 - MISC:VGG_SENDMAX
11 - MISC:SEND_VGG[3]
10 - MISC:SEND_VGG[2]
9 - MISC:SEND_VGG[1]
8 - MISC:SEND_VGG[0]
7 - -
6 - -
5 - MISC:DCM_ENABLE
4 - MISC:DCI_OSC_SEL[2]
3 - MISC:DCI_OSC_SEL[1]
2 - MISC:DCI_OSC_SEL[0]
1 - MISC:GATE_GHIGH
0 - MISC:DCI_CLK_ENABLE
DCI0:ENABLE 0.1.44
DCI0:FORCE_DONE_HIGH 0.1.61
DCI0:QUIET 0.1.45
DCI0:TEST_ENABLE 0.1.62
DCI1:ENABLE 0.0.44
DCI1:FORCE_DONE_HIGH 0.0.61
DCI1:QUIET 0.0.45
DCI1:TEST_ENABLE 0.0.62
DCIRESET0:ENABLE 0.1.63
DCIRESET1:ENABLE 0.0.63
MISC:DCI_CLK_ENABLE 0.1.0
MISC:DCM_ENABLE 0.1.5
MISC:GATE_GHIGH 0.1.1
MISC:VGG_ENABLE_OFFCHIP 0.1.13
MISC:VGG_SENDMAX 0.1.12
non-inverted [0]
DCI0:LVDSBIAS 0.0.33 0.0.34 0.0.35 0.0.36 0.0.37 0.0.38 0.0.39 0.0.40 0.0.41 0.0.42 0.0.43 0.0.23 0.0.24
DCI1:LVDSBIAS 0.1.33 0.1.34 0.1.35 0.1.36 0.1.37 0.1.38 0.1.39 0.1.40 0.1.41 0.1.42 0.1.43 0.1.31 0.1.32
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.1.49 0.1.48 0.1.47 0.1.46
DCI0:PMASK_TERM_SPLIT 0.1.59 0.1.58 0.1.57 0.1.56
DCI0:PMASK_TERM_VCC 0.1.54 0.1.53 0.1.52 0.1.51
DCI1:NMASK_TERM_SPLIT 0.0.49 0.0.48 0.0.47 0.0.46
DCI1:PMASK_TERM_SPLIT 0.0.59 0.0.58 0.0.57 0.0.56
DCI1:PMASK_TERM_VCC 0.0.54 0.0.53 0.0.52 0.0.51
MISC:SEND_VGG 0.1.11 0.1.10 0.1.9 0.1.8
non-inverted [3] [2] [1] [0]
MISC:DCI_OSC_SEL 0.1.4 0.1.3 0.1.2
non-inverted [2] [1] [0]
MISC:DCI_TEST_MUX 0.1.50
DCI0 0
DCI1 1
MISC:M0PIN 0.0.27 0.0.28
MISC:M1PIN 0.0.25 0.0.26
MISC:M2PIN 0.0.29 0.0.30
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1

LL.S3E

This tile is used on Spartan 3E.

Tile LL.S3E

Cells: 1 IRIs: 0

Bitstream

spartan3 LL.S3E bittile 0
BitFrame
0 1
43 - BANK:LVDSBIAS_1[6]
42 - BANK:LVDSBIAS_1[7]
41 - BANK:LVDSBIAS_1[8]
40 - BANK:LVDSBIAS_1[9]
39 - BANK:LVDSBIAS_1[10]
38 - BANK:LVDSBIAS_0[5]
37 - BANK:LVDSBIAS_0[6]
36 - BANK:LVDSBIAS_0[7]
35 - BANK:LVDSBIAS_0[8]
34 - BANK:LVDSBIAS_0[9]
33 - BANK:LVDSBIAS_0[10]
32 - BANK:LVDSBIAS_1[0]
31 - BANK:LVDSBIAS_0[0]
30 - BANK:LVDSBIAS_1[1]
29 - BANK:LVDSBIAS_1[2]
28 - BANK:LVDSBIAS_1[3]
27 - BANK:LVDSBIAS_1[4]
26 - BANK:LVDSBIAS_0[1]
25 - BANK:LVDSBIAS_0[2]
24 - BANK:LVDSBIAS_0[3]
23 - BANK:LVDSBIAS_0[4]
22 - BANK:LVDSBIAS_1[5]
21 - MISC:TEMPSENSOR[0]
20 - -
19 - -
18 - MISC:TEMPSENSOR[1]
17 - MISC:TEMPSENSOR[2]
16 - -
15 - -
14 - -
13 - MISC:VGG_ENABLE_OFFCHIP
12 - MISC:VGG_SENDMAX
11 - MISC:SEND_VGG[3]
10 - MISC:SEND_VGG[2]
9 - MISC:SEND_VGG[1]
8 - MISC:SEND_VGG[0]
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 - -
BANK:LVDSBIAS_0 0.1.33 0.1.34 0.1.35 0.1.36 0.1.37 0.1.38 0.1.23 0.1.24 0.1.25 0.1.26 0.1.31
BANK:LVDSBIAS_1 0.1.39 0.1.40 0.1.41 0.1.42 0.1.43 0.1.22 0.1.27 0.1.28 0.1.29 0.1.30 0.1.32
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:SEND_VGG 0.1.11 0.1.10 0.1.9 0.1.8
non-inverted [3] [2] [1] [0]
MISC:TEMPSENSOR 0.1.17 0.1.18 0.1.21
NONE 0 0 0
THERM 0 0 1
PGATE 0 1 1
BG 1 0 1
CGATE 1 1 1
MISC:VGG_ENABLE_OFFCHIP 0.1.13
MISC:VGG_SENDMAX 0.1.12
non-inverted [0]

LL.S3A

This tile is used on Spartan 3A.

Tile LL.S3A

Cells: 1 IRIs: 0

Bitstream

spartan3 LL.S3A bittile 0
BitFrame
0 1
63 - BANK:LVDSBIAS_1[5]
62 BANK:LVDSBIAS_1[10] BANK:LVDSBIAS_1[4]
61 - -
60 - -
59 - -
58 - -
57 - -
56 - -
55 - -
54 - -
53 - -
52 - -
51 - -
50 - -
49 - -
48 - -
47 - -
46 - -
45 - -
44 - -
43 - -
42 - -
41 - -
40 - -
39 - -
38 - -
37 - -
36 - BANK:LVDSBIAS_0[4]
35 - BANK:LVDSBIAS_1[8]
34 - BANK:LVDSBIAS_0[8]
33 - BANK:LVDSBIAS_0[9]
32 - BANK:LVDSBIAS_0[0]
31 BANK:LVDSBIAS_0[2] -
30 BANK:LVDSBIAS_1[6] BANK:LVDSBIAS_0[3]
29 BANK:LVDSBIAS_1[9] -
28 BANK:LVDSBIAS_1[1] BANK:LVDSBIAS_0[5]
27 BANK:LVDSBIAS_0[1] BANK:LVDSBIAS_1[0]
26 BANK:LVDSBIAS_1[2] BANK:LVDSBIAS_1[3]
25 - -
24 MISC:MOSI2PIN[1] MISC:MOSI2PIN[0]
23 - MISC:VGG_ENABLE_OFFCHIP
22 - MISC:VGG_SENDMAX
21 - MISC:SEND_VGG[3]
20 - MISC:SEND_VGG[2]
19 - MISC:SEND_VGG[1]
18 - MISC:SEND_VGG[0]
17 - -
16 - -
15 MISC:CCLK2PIN[0] MISC:CCLK2PIN[1]
14 - MISC:UNK_ALWAYS_SET[3]
13 MISC:UNK_ALWAYS_SET[1] -
12 MISC:UNK_ALWAYS_SET[0] MISC:UNK_ALWAYS_SET[2]
11 - BANK:LVDSBIAS_0[7]
10 BANK:LVDSBIAS_0[6] BANK:LVDSBIAS_0[10]
9 BANK:LVDSBIAS_0[11] BANK:LVDSBIAS_1[7]
8 - -
7 MISC:TEMPSENSOR[0] MISC:TEMPSENSOR[1]
6 BANK:LVDSBIAS_1[11] -
5 - -
4 - MISC:TEMPSENSOR[3]
3 - MISC:TEMPSENSOR[2]
2 - -
1 - -
0 - -
BANK:LVDSBIAS_0 0.0.9 0.1.10 0.1.33 0.1.34 0.1.11 0.0.10 0.1.28 0.1.36 0.1.30 0.0.31 0.0.27 0.1.32
BANK:LVDSBIAS_1 0.0.6 0.0.62 0.0.29 0.1.35 0.1.9 0.0.30 0.1.63 0.1.62 0.1.26 0.0.26 0.0.28 0.1.27
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:CCLK2PIN 0.1.15 0.0.15
MISC:MOSI2PIN 0.0.24 0.1.24
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1
MISC:SEND_VGG 0.1.21 0.1.20 0.1.19 0.1.18
MISC:UNK_ALWAYS_SET 0.1.14 0.1.12 0.0.13 0.0.12
non-inverted [3] [2] [1] [0]
MISC:TEMPSENSOR 0.1.4 0.1.3 0.1.7 0.0.7
NONE 0 0 0 0
THERM 0 0 1 1
PGATE 0 1 1 1
BG 1 0 1 1
CGATE 1 1 1 1
MISC:VGG_ENABLE_OFFCHIP 0.1.23
MISC:VGG_SENDMAX 0.1.22
non-inverted [0]