Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

South-west

TODO: document

CNR_SW_S3

This tile is used on Spartan 3.

Tile CNR_SW_S3

Cells: 1

Bels DCI

spartan3 CNR_SW_S3 bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_DATA[23]IMUX_DATA[15]
DCI_RESETinIMUX_DATA[22]IMUX_DATA[14]
HI_LO_PinIMUX_DATA[20]IMUX_DATA[12]
HI_LO_NinIMUX_DATA[21]IMUX_DATA[13]
SCLKoutOUT_SEC[6]OUT_SEC[6]
ADDRESS[0]outOUT_SEC[0]OUT_SEC[0]
ADDRESS[1]outOUT_SEC[1]OUT_SEC[1]
ADDRESS[2]outOUT_SEC[2]OUT_SEC[2]
DATAoutOUT_SEC[3]OUT_SEC[3]
N_OR_PoutOUT_SEC[5]OUT_SEC[5]
UPDATEoutOUT_SEC[7]OUT_SEC[7]
IOUPDATEoutOUT_SEC[8]OUT_SEC[8]
DCI_DONEoutOUT_SEC[4]OUT_SEC[4]
spartan3 CNR_SW_S3 bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[1][44]TERM_H[0][44]
TEST_ENABLETERM_H[1][62]TERM_H[0][62]
FORCE_DONE_HIGHTERM_H[1][61]TERM_H[0][61]
S3_PMASK_TERM_SPLIT bit 0TERM_H[1][56]TERM_H[0][56]
S3_PMASK_TERM_SPLIT bit 1TERM_H[1][57]TERM_H[0][57]
S3_PMASK_TERM_SPLIT bit 2TERM_H[1][58]TERM_H[0][58]
S3_PMASK_TERM_SPLIT bit 3TERM_H[1][59]TERM_H[0][59]
S3_NMASK_TERM_SPLIT bit 0TERM_H[1][46]TERM_H[0][46]
S3_NMASK_TERM_SPLIT bit 1TERM_H[1][47]TERM_H[0][47]
S3_NMASK_TERM_SPLIT bit 2TERM_H[1][48]TERM_H[0][48]
S3_NMASK_TERM_SPLIT bit 3TERM_H[1][49]TERM_H[0][49]
S3_PMASK_TERM_VCC bit 0TERM_H[1][51]TERM_H[0][51]
S3_PMASK_TERM_VCC bit 1TERM_H[1][52]TERM_H[0][52]
S3_PMASK_TERM_VCC bit 2TERM_H[1][53]TERM_H[0][53]
S3_PMASK_TERM_VCC bit 3TERM_H[1][54]TERM_H[0][54]
S3_LVDSBIAS bit 0TERM_H[0][33]TERM_H[1][33]
S3_LVDSBIAS bit 1TERM_H[0][34]TERM_H[1][34]
S3_LVDSBIAS bit 2TERM_H[0][35]TERM_H[1][35]
S3_LVDSBIAS bit 3TERM_H[0][36]TERM_H[1][36]
S3_LVDSBIAS bit 4TERM_H[0][37]TERM_H[1][37]
S3_LVDSBIAS bit 5TERM_H[0][38]TERM_H[1][38]
S3_LVDSBIAS bit 6TERM_H[0][39]TERM_H[1][39]
S3_LVDSBIAS bit 7TERM_H[0][40]TERM_H[1][40]
S3_LVDSBIAS bit 8TERM_H[0][41]TERM_H[1][41]
S3_LVDSBIAS bit 9TERM_H[0][42]TERM_H[1][42]
S3_LVDSBIAS bit 10TERM_H[0][43]TERM_H[1][43]
S3_LVDSBIAS bit 11TERM_H[0][23]TERM_H[1][31]
S3_LVDSBIAS bit 12TERM_H[0][24]TERM_H[1][32]
QUIETTERM_H[1][45]TERM_H[0][45]

Bels DCIRESET

spartan3 CNR_SW_S3 bel DCIRESET pins
PinDirectionDCIRESET[0]DCIRESET[1]
RSTinIMUX_DATA[19]IMUX_DATA[11]
spartan3 CNR_SW_S3 bel DCIRESET attribute bits
AttributeDCIRESET[0]DCIRESET[1]
ENABLETERM_H[1][63]TERM_H[0][63]

Bels MISC_CNR_S3

spartan3 CNR_SW_S3 bel MISC_CNR_S3 pins
PinDirectionMISC_CNR_S3
spartan3 CNR_SW_S3 bel MISC_CNR_S3 attribute bits
AttributeMISC_CNR_S3
MUX_DCI_TEST bit 0TERM_H[1][50]
DCM_ENABLETERM_H[1][5]

Bels MISC_SW

spartan3 CNR_SW_S3 bel MISC_SW pins
PinDirectionMISC_SW
spartan3 CNR_SW_S3 bel MISC_SW attribute bits
AttributeMISC_SW
M0_PULL[enum: IOB_PULL]
M1_PULL[enum: IOB_PULL]
M2_PULL[enum: IOB_PULL]
DCI_CLK_ENABLETERM_H[1][0]
DCI_OSC_SEL bit 0TERM_H[1][2]
DCI_OSC_SEL bit 1TERM_H[1][3]
DCI_OSC_SEL bit 2TERM_H[1][4]
GATE_GHIGHTERM_H[1][1]
SEND_VGG bit 0TERM_H[1][8]
SEND_VGG bit 1TERM_H[1][9]
SEND_VGG bit 2TERM_H[1][10]
SEND_VGG bit 3TERM_H[1][11]
VGG_ENABLE_OFFCHIPTERM_H[1][13]
VGG_SENDMAXTERM_H[1][12]
spartan3 CNR_SW_S3 enum IOB_PULL
MISC_SW.M0_PULLTERM_H[0][27]TERM_H[0][28]
MISC_SW.M1_PULLTERM_H[0][25]TERM_H[0][26]
MISC_SW.M2_PULLTERM_H[0][29]TERM_H[0][30]
NONE01
PULLUP00
PULLDOWN11

Bel wires

spartan3 CNR_SW_S3 bel wires
WirePins
IMUX_DATA[11]DCIRESET[1].RST
IMUX_DATA[12]DCI[1].HI_LO_P
IMUX_DATA[13]DCI[1].HI_LO_N
IMUX_DATA[14]DCI[1].DCI_RESET
IMUX_DATA[15]DCI[1].DCI_CLK
IMUX_DATA[19]DCIRESET[0].RST
IMUX_DATA[20]DCI[0].HI_LO_P
IMUX_DATA[21]DCI[0].HI_LO_N
IMUX_DATA[22]DCI[0].DCI_RESET
IMUX_DATA[23]DCI[0].DCI_CLK
OUT_SEC[0]DCI[0].ADDRESS[0], DCI[1].ADDRESS[0]
OUT_SEC[1]DCI[0].ADDRESS[1], DCI[1].ADDRESS[1]
OUT_SEC[2]DCI[0].ADDRESS[2], DCI[1].ADDRESS[2]
OUT_SEC[3]DCI[0].DATA, DCI[1].DATA
OUT_SEC[4]DCI[0].DCI_DONE, DCI[1].DCI_DONE
OUT_SEC[5]DCI[0].N_OR_P, DCI[1].N_OR_P
OUT_SEC[6]DCI[0].SCLK, DCI[1].SCLK
OUT_SEC[7]DCI[0].UPDATE, DCI[1].UPDATE
OUT_SEC[8]DCI[0].IOUPDATE, DCI[1].IOUPDATE

Bitstream

spartan3 CNR_SW_S3 rect TERM_H
BitFrame
F1 F0
B63 DCIRESET[0]: ENABLE DCIRESET[1]: ENABLE
B62 DCI[0]: TEST_ENABLE DCI[1]: TEST_ENABLE
B61 DCI[0]: FORCE_DONE_HIGH DCI[1]: FORCE_DONE_HIGH
B60 - -
B59 DCI[0]: S3_PMASK_TERM_SPLIT bit 3 DCI[1]: S3_PMASK_TERM_SPLIT bit 3
B58 DCI[0]: S3_PMASK_TERM_SPLIT bit 2 DCI[1]: S3_PMASK_TERM_SPLIT bit 2
B57 DCI[0]: S3_PMASK_TERM_SPLIT bit 1 DCI[1]: S3_PMASK_TERM_SPLIT bit 1
B56 DCI[0]: S3_PMASK_TERM_SPLIT bit 0 DCI[1]: S3_PMASK_TERM_SPLIT bit 0
B55 - -
B54 DCI[0]: S3_PMASK_TERM_VCC bit 3 DCI[1]: S3_PMASK_TERM_VCC bit 3
B53 DCI[0]: S3_PMASK_TERM_VCC bit 2 DCI[1]: S3_PMASK_TERM_VCC bit 2
B52 DCI[0]: S3_PMASK_TERM_VCC bit 1 DCI[1]: S3_PMASK_TERM_VCC bit 1
B51 DCI[0]: S3_PMASK_TERM_VCC bit 0 DCI[1]: S3_PMASK_TERM_VCC bit 0
B50 MISC_CNR_S3: MUX_DCI_TEST bit 0 -
B49 DCI[0]: S3_NMASK_TERM_SPLIT bit 3 DCI[1]: S3_NMASK_TERM_SPLIT bit 3
B48 DCI[0]: S3_NMASK_TERM_SPLIT bit 2 DCI[1]: S3_NMASK_TERM_SPLIT bit 2
B47 DCI[0]: S3_NMASK_TERM_SPLIT bit 1 DCI[1]: S3_NMASK_TERM_SPLIT bit 1
B46 DCI[0]: S3_NMASK_TERM_SPLIT bit 0 DCI[1]: S3_NMASK_TERM_SPLIT bit 0
B45 DCI[0]: QUIET DCI[1]: QUIET
B44 DCI[0]: ENABLE DCI[1]: ENABLE
B43 DCI[1]: S3_LVDSBIAS bit 10 DCI[0]: S3_LVDSBIAS bit 10
B42 DCI[1]: S3_LVDSBIAS bit 9 DCI[0]: S3_LVDSBIAS bit 9
B41 DCI[1]: S3_LVDSBIAS bit 8 DCI[0]: S3_LVDSBIAS bit 8
B40 DCI[1]: S3_LVDSBIAS bit 7 DCI[0]: S3_LVDSBIAS bit 7
B39 DCI[1]: S3_LVDSBIAS bit 6 DCI[0]: S3_LVDSBIAS bit 6
B38 DCI[1]: S3_LVDSBIAS bit 5 DCI[0]: S3_LVDSBIAS bit 5
B37 DCI[1]: S3_LVDSBIAS bit 4 DCI[0]: S3_LVDSBIAS bit 4
B36 DCI[1]: S3_LVDSBIAS bit 3 DCI[0]: S3_LVDSBIAS bit 3
B35 DCI[1]: S3_LVDSBIAS bit 2 DCI[0]: S3_LVDSBIAS bit 2
B34 DCI[1]: S3_LVDSBIAS bit 1 DCI[0]: S3_LVDSBIAS bit 1
B33 DCI[1]: S3_LVDSBIAS bit 0 DCI[0]: S3_LVDSBIAS bit 0
B32 DCI[1]: S3_LVDSBIAS bit 12 -
B31 DCI[1]: S3_LVDSBIAS bit 11 -
B30 - MISC_SW: M2_PULL bit 0
B29 - MISC_SW: M2_PULL bit 1
B28 - MISC_SW: M0_PULL bit 0
B27 - MISC_SW: M0_PULL bit 1
B26 - MISC_SW: M1_PULL bit 0
B25 - MISC_SW: M1_PULL bit 1
B24 - DCI[0]: S3_LVDSBIAS bit 12
B23 - DCI[0]: S3_LVDSBIAS bit 11
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 MISC_SW: VGG_ENABLE_OFFCHIP -
B12 MISC_SW: VGG_SENDMAX -
B11 MISC_SW: SEND_VGG bit 3 -
B10 MISC_SW: SEND_VGG bit 2 -
B9 MISC_SW: SEND_VGG bit 1 -
B8 MISC_SW: SEND_VGG bit 0 -
B7 - -
B6 - -
B5 MISC_CNR_S3: DCM_ENABLE -
B4 MISC_SW: DCI_OSC_SEL bit 2 -
B3 MISC_SW: DCI_OSC_SEL bit 1 -
B2 MISC_SW: DCI_OSC_SEL bit 0 -
B1 MISC_SW: GATE_GHIGH -
B0 MISC_SW: DCI_CLK_ENABLE -

CNR_SW_FC

This tile is used on FPGAcore.

Tile CNR_SW_FC

Cells: 1

Bels MISR_FC

spartan3 CNR_SW_FC bel MISR_FC pins
PinDirectionMISR_FC
CLKinIMUX_CLK_OPTINV[3]
spartan3 CNR_SW_FC bel MISR_FC attribute bits
AttributeMISR_FC
MISR_CLOCKTERM_H[0][1]
MISR_RESETTERM_H[0][0]

Bels MISC_SW

spartan3 CNR_SW_FC bel MISC_SW pins
PinDirectionMISC_SW
spartan3 CNR_SW_FC bel MISC_SW attribute bits
AttributeMISC_SW
SEND_VGG bit 0TERM_H[1][8]
SEND_VGG bit 1TERM_H[1][9]
SEND_VGG bit 2TERM_H[1][10]
SEND_VGG bit 3TERM_H[1][11]
VGG_ENABLE_OFFCHIPTERM_H[1][13]
VGG_SENDMAXTERM_H[1][12]

Bel wires

spartan3 CNR_SW_FC bel wires
WirePins
IMUX_CLK_OPTINV[3]MISR_FC.CLK

Bitstream

spartan3 CNR_SW_FC rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 MISC_SW: VGG_ENABLE_OFFCHIP -
B12 MISC_SW: VGG_SENDMAX -
B11 MISC_SW: SEND_VGG bit 3 -
B10 MISC_SW: SEND_VGG bit 2 -
B9 MISC_SW: SEND_VGG bit 1 -
B8 MISC_SW: SEND_VGG bit 0 -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - MISR_FC: MISR_CLOCK
B0 - MISR_FC: MISR_RESET

CNR_SW_S3E

This tile is used on Spartan 3E.

Tile CNR_SW_S3E

Cells: 1

Bels MISC_SW

spartan3 CNR_SW_S3E bel MISC_SW pins
PinDirectionMISC_SW
spartan3 CNR_SW_S3E bel MISC_SW attribute bits
AttributeMISC_SW
SEND_VGG bit 0TERM_H[1][8]
SEND_VGG bit 1TERM_H[1][9]
SEND_VGG bit 2TERM_H[1][10]
SEND_VGG bit 3TERM_H[1][11]
VGG_ENABLE_OFFCHIPTERM_H[1][13]
VGG_SENDMAXTERM_H[1][12]
TEMP_SENSOR[enum: MISC_TEMP_SENSOR]
spartan3 CNR_SW_S3E enum MISC_TEMP_SENSOR
MISC_SW.TEMP_SENSORTERM_H[1][17]TERM_H[1][18]TERM_H[1][21]
NONE000
THERM001
PGATE011
BG101
CGATE111

Bels BANK

spartan3 CNR_SW_S3E bel BANK pins
PinDirectionBANK
spartan3 CNR_SW_S3E bel BANK attribute bits
AttributeBANK
S3E_LVDSBIAS[0] bit 0TERM_H[1][31]
S3E_LVDSBIAS[0] bit 1TERM_H[1][26]
S3E_LVDSBIAS[0] bit 2TERM_H[1][25]
S3E_LVDSBIAS[0] bit 3TERM_H[1][24]
S3E_LVDSBIAS[0] bit 4TERM_H[1][23]
S3E_LVDSBIAS[0] bit 5TERM_H[1][38]
S3E_LVDSBIAS[0] bit 6TERM_H[1][37]
S3E_LVDSBIAS[0] bit 7TERM_H[1][36]
S3E_LVDSBIAS[0] bit 8TERM_H[1][35]
S3E_LVDSBIAS[0] bit 9TERM_H[1][34]
S3E_LVDSBIAS[0] bit 10TERM_H[1][33]
S3E_LVDSBIAS[1] bit 0TERM_H[1][32]
S3E_LVDSBIAS[1] bit 1TERM_H[1][30]
S3E_LVDSBIAS[1] bit 2TERM_H[1][29]
S3E_LVDSBIAS[1] bit 3TERM_H[1][28]
S3E_LVDSBIAS[1] bit 4TERM_H[1][27]
S3E_LVDSBIAS[1] bit 5TERM_H[1][22]
S3E_LVDSBIAS[1] bit 6TERM_H[1][43]
S3E_LVDSBIAS[1] bit 7TERM_H[1][42]
S3E_LVDSBIAS[1] bit 8TERM_H[1][41]
S3E_LVDSBIAS[1] bit 9TERM_H[1][40]
S3E_LVDSBIAS[1] bit 10TERM_H[1][39]

Bitstream

spartan3 CNR_SW_S3E rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 BANK: S3E_LVDSBIAS[1] bit 6 -
B42 BANK: S3E_LVDSBIAS[1] bit 7 -
B41 BANK: S3E_LVDSBIAS[1] bit 8 -
B40 BANK: S3E_LVDSBIAS[1] bit 9 -
B39 BANK: S3E_LVDSBIAS[1] bit 10 -
B38 BANK: S3E_LVDSBIAS[0] bit 5 -
B37 BANK: S3E_LVDSBIAS[0] bit 6 -
B36 BANK: S3E_LVDSBIAS[0] bit 7 -
B35 BANK: S3E_LVDSBIAS[0] bit 8 -
B34 BANK: S3E_LVDSBIAS[0] bit 9 -
B33 BANK: S3E_LVDSBIAS[0] bit 10 -
B32 BANK: S3E_LVDSBIAS[1] bit 0 -
B31 BANK: S3E_LVDSBIAS[0] bit 0 -
B30 BANK: S3E_LVDSBIAS[1] bit 1 -
B29 BANK: S3E_LVDSBIAS[1] bit 2 -
B28 BANK: S3E_LVDSBIAS[1] bit 3 -
B27 BANK: S3E_LVDSBIAS[1] bit 4 -
B26 BANK: S3E_LVDSBIAS[0] bit 1 -
B25 BANK: S3E_LVDSBIAS[0] bit 2 -
B24 BANK: S3E_LVDSBIAS[0] bit 3 -
B23 BANK: S3E_LVDSBIAS[0] bit 4 -
B22 BANK: S3E_LVDSBIAS[1] bit 5 -
B21 MISC_SW: TEMP_SENSOR bit 0 -
B20 - -
B19 - -
B18 MISC_SW: TEMP_SENSOR bit 1 -
B17 MISC_SW: TEMP_SENSOR bit 2 -
B16 - -
B15 - -
B14 - -
B13 MISC_SW: VGG_ENABLE_OFFCHIP -
B12 MISC_SW: VGG_SENDMAX -
B11 MISC_SW: SEND_VGG bit 3 -
B10 MISC_SW: SEND_VGG bit 2 -
B9 MISC_SW: SEND_VGG bit 1 -
B8 MISC_SW: SEND_VGG bit 0 -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -

CNR_SW_S3A

This tile is used on Spartan 3A.

Tile CNR_SW_S3A

Cells: 1

Bels MISC_SW

spartan3 CNR_SW_S3A bel MISC_SW pins
PinDirectionMISC_SW
spartan3 CNR_SW_S3A bel MISC_SW attribute bits
AttributeMISC_SW
CCLK2_PULL[enum: IOB_PULL]
MOSI2_PULL[enum: IOB_PULL]
SEND_VGG bit 0TERM_H[1][18]
SEND_VGG bit 1TERM_H[1][19]
SEND_VGG bit 2TERM_H[1][20]
SEND_VGG bit 3TERM_H[1][21]
VGG_ENABLE_OFFCHIPTERM_H[1][23]
VGG_SENDMAXTERM_H[1][22]
TEMP_SENSOR[enum: MISC_TEMP_SENSOR]
UNK_ALWAYS_SET bit 0TERM_H[0][12]
UNK_ALWAYS_SET bit 1TERM_H[0][13]
UNK_ALWAYS_SET bit 2TERM_H[1][12]
UNK_ALWAYS_SET bit 3TERM_H[1][14]
spartan3 CNR_SW_S3A enum IOB_PULL
MISC_SW.CCLK2_PULLTERM_H[1][15]TERM_H[0][15]
MISC_SW.MOSI2_PULLTERM_H[0][24]TERM_H[1][24]
NONE01
PULLUP00
PULLDOWN11
spartan3 CNR_SW_S3A enum MISC_TEMP_SENSOR
MISC_SW.TEMP_SENSORTERM_H[1][4]TERM_H[1][3]TERM_H[1][7]TERM_H[0][7]
NONE0000
THERM0011
PGATE0111
BG1011
CGATE1111

Bels BANK

spartan3 CNR_SW_S3A bel BANK pins
PinDirectionBANK
spartan3 CNR_SW_S3A bel BANK attribute bits
AttributeBANK
S3A_LVDSBIAS[0] bit 0TERM_H[1][32]
S3A_LVDSBIAS[0] bit 1TERM_H[0][27]
S3A_LVDSBIAS[0] bit 2TERM_H[0][31]
S3A_LVDSBIAS[0] bit 3TERM_H[1][30]
S3A_LVDSBIAS[0] bit 4TERM_H[1][36]
S3A_LVDSBIAS[0] bit 5TERM_H[1][28]
S3A_LVDSBIAS[0] bit 6TERM_H[0][10]
S3A_LVDSBIAS[0] bit 7TERM_H[1][11]
S3A_LVDSBIAS[0] bit 8TERM_H[1][34]
S3A_LVDSBIAS[0] bit 9TERM_H[1][33]
S3A_LVDSBIAS[0] bit 10TERM_H[1][10]
S3A_LVDSBIAS[0] bit 11TERM_H[0][9]
S3A_LVDSBIAS[1] bit 0TERM_H[1][27]
S3A_LVDSBIAS[1] bit 1TERM_H[0][28]
S3A_LVDSBIAS[1] bit 2TERM_H[0][26]
S3A_LVDSBIAS[1] bit 3TERM_H[1][26]
S3A_LVDSBIAS[1] bit 4TERM_H[1][62]
S3A_LVDSBIAS[1] bit 5TERM_H[1][63]
S3A_LVDSBIAS[1] bit 6TERM_H[0][30]
S3A_LVDSBIAS[1] bit 7TERM_H[1][9]
S3A_LVDSBIAS[1] bit 8TERM_H[1][35]
S3A_LVDSBIAS[1] bit 9TERM_H[0][29]
S3A_LVDSBIAS[1] bit 10TERM_H[0][62]
S3A_LVDSBIAS[1] bit 11TERM_H[0][6]

Bitstream

spartan3 CNR_SW_S3A rect TERM_H
BitFrame
F1 F0
B63 BANK: S3A_LVDSBIAS[1] bit 5 -
B62 BANK: S3A_LVDSBIAS[1] bit 4 BANK: S3A_LVDSBIAS[1] bit 10
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 BANK: S3A_LVDSBIAS[0] bit 4 -
B35 BANK: S3A_LVDSBIAS[1] bit 8 -
B34 BANK: S3A_LVDSBIAS[0] bit 8 -
B33 BANK: S3A_LVDSBIAS[0] bit 9 -
B32 BANK: S3A_LVDSBIAS[0] bit 0 -
B31 - BANK: S3A_LVDSBIAS[0] bit 2
B30 BANK: S3A_LVDSBIAS[0] bit 3 BANK: S3A_LVDSBIAS[1] bit 6
B29 - BANK: S3A_LVDSBIAS[1] bit 9
B28 BANK: S3A_LVDSBIAS[0] bit 5 BANK: S3A_LVDSBIAS[1] bit 1
B27 BANK: S3A_LVDSBIAS[1] bit 0 BANK: S3A_LVDSBIAS[0] bit 1
B26 BANK: S3A_LVDSBIAS[1] bit 3 BANK: S3A_LVDSBIAS[1] bit 2
B25 - -
B24 MISC_SW: MOSI2_PULL bit 0 MISC_SW: MOSI2_PULL bit 1
B23 MISC_SW: VGG_ENABLE_OFFCHIP -
B22 MISC_SW: VGG_SENDMAX -
B21 MISC_SW: SEND_VGG bit 3 -
B20 MISC_SW: SEND_VGG bit 2 -
B19 MISC_SW: SEND_VGG bit 1 -
B18 MISC_SW: SEND_VGG bit 0 -
B17 - -
B16 - -
B15 MISC_SW: CCLK2_PULL bit 1 MISC_SW: CCLK2_PULL bit 0
B14 MISC_SW: UNK_ALWAYS_SET bit 3 -
B13 - MISC_SW: UNK_ALWAYS_SET bit 1
B12 MISC_SW: UNK_ALWAYS_SET bit 2 MISC_SW: UNK_ALWAYS_SET bit 0
B11 BANK: S3A_LVDSBIAS[0] bit 7 -
B10 BANK: S3A_LVDSBIAS[0] bit 10 BANK: S3A_LVDSBIAS[0] bit 6
B9 BANK: S3A_LVDSBIAS[1] bit 7 BANK: S3A_LVDSBIAS[0] bit 11
B8 - -
B7 MISC_SW: TEMP_SENSOR bit 1 MISC_SW: TEMP_SENSOR bit 0
B6 - BANK: S3A_LVDSBIAS[1] bit 11
B5 - -
B4 MISC_SW: TEMP_SENSOR bit 3 -
B3 MISC_SW: TEMP_SENSOR bit 2 -
B2 - -
B1 - -
B0 - -