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TODO: document

`UL.S3`

This tile is used on Spartan 3.

spartan3 UL.S3 bittile 0
Bit	Frame
Bit	0	1
63	DCIRESET0:ENABLE	DCIRESET1:ENABLE
62	DCI0:TEST_ENABLE	DCI1:TEST_ENABLE
61	DCI0:FORCE_DONE_HIGH	DCI1:FORCE_DONE_HIGH
60	-	-
59	DCI0:PMASK_TERM_SPLIT[3]	DCI1:PMASK_TERM_SPLIT[3]
58	DCI0:PMASK_TERM_SPLIT[2]	DCI1:PMASK_TERM_SPLIT[2]
57	DCI0:PMASK_TERM_SPLIT[1]	DCI1:PMASK_TERM_SPLIT[1]
56	DCI0:PMASK_TERM_SPLIT[0]	DCI1:PMASK_TERM_SPLIT[0]
55	-	-
54	DCI0:PMASK_TERM_VCC[3]	DCI1:PMASK_TERM_VCC[3]
53	DCI0:PMASK_TERM_VCC[2]	DCI1:PMASK_TERM_VCC[2]
52	DCI0:PMASK_TERM_VCC[1]	DCI1:PMASK_TERM_VCC[1]
51	DCI0:PMASK_TERM_VCC[0]	DCI1:PMASK_TERM_VCC[0]
50	MISC:DCI_TEST_MUX[0]	-
49	DCI0:NMASK_TERM_SPLIT[3]	DCI1:NMASK_TERM_SPLIT[3]
48	DCI0:NMASK_TERM_SPLIT[2]	DCI1:NMASK_TERM_SPLIT[2]
47	DCI0:NMASK_TERM_SPLIT[1]	DCI1:NMASK_TERM_SPLIT[1]
46	DCI0:NMASK_TERM_SPLIT[0]	DCI1:NMASK_TERM_SPLIT[0]
45	DCI0:QUIET	DCI1:QUIET
44	DCI0:ENABLE	DCI1:ENABLE
43	DCI1:LVDSBIAS[2]	DCI0:LVDSBIAS[2]
42	DCI1:LVDSBIAS[3]	DCI0:LVDSBIAS[3]
41	DCI1:LVDSBIAS[4]	DCI0:LVDSBIAS[4]
40	DCI1:LVDSBIAS[5]	DCI0:LVDSBIAS[5]
39	DCI1:LVDSBIAS[6]	DCI0:LVDSBIAS[6]
38	DCI1:LVDSBIAS[7]	DCI0:LVDSBIAS[7]
37	DCI1:LVDSBIAS[8]	DCI0:LVDSBIAS[8]
36	DCI1:LVDSBIAS[9]	DCI0:LVDSBIAS[9]
35	DCI1:LVDSBIAS[10]	DCI0:LVDSBIAS[10]
34	DCI1:LVDSBIAS[11]	DCI0:LVDSBIAS[11]
33	DCI1:LVDSBIAS[12]	DCI0:LVDSBIAS[12]
32	DCI1:LVDSBIAS[0]	MISC:TEST_LL
31	-	DCI0:LVDSBIAS[0]
30	-	DCI0:LVDSBIAS[1]
29	DCI1:LVDSBIAS[1]	MISC:TDIPIN[1]
28	-	MISC:TDIPIN[0]
27	-	MISC:HSWAPENPIN[0]
26	-	MISC:HSWAPENPIN[1]
25	-	MISC:PROGPIN[0]
24	-	-
23	-	-
22	-	-
21	-	-
20	-	-
19	-	-
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	MISC:DCM_ENABLE	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

DCI0:ENABLE	0.0.44
DCI0:FORCE_DONE_HIGH	0.0.61
DCI0:QUIET	0.0.45
DCI0:TEST_ENABLE	0.0.62
DCI1:ENABLE	0.1.44
DCI1:FORCE_DONE_HIGH	0.1.61
DCI1:QUIET	0.1.45
DCI1:TEST_ENABLE	0.1.62
DCIRESET0:ENABLE	0.0.63
DCIRESET1:ENABLE	0.1.63
MISC:DCM_ENABLE	0.0.8
MISC:TEST_LL	0.1.32
non-inverted	[0]

DCI0:LVDSBIAS	0.1.33	0.1.34	0.1.35	0.1.36	0.1.37	0.1.38	0.1.39	0.1.40	0.1.41	0.1.42	0.1.43	0.1.30	0.1.31
DCI1:LVDSBIAS	0.0.33	0.0.34	0.0.35	0.0.36	0.0.37	0.0.38	0.0.39	0.0.40	0.0.41	0.0.42	0.0.43	0.0.29	0.0.32
non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

DCI0:NMASK_TERM_SPLIT	0.0.49	0.0.48	0.0.47	0.0.46
DCI0:PMASK_TERM_SPLIT	0.0.59	0.0.58	0.0.57	0.0.56
DCI0:PMASK_TERM_VCC	0.0.54	0.0.53	0.0.52	0.0.51
DCI1:NMASK_TERM_SPLIT	0.1.49	0.1.48	0.1.47	0.1.46
DCI1:PMASK_TERM_SPLIT	0.1.59	0.1.58	0.1.57	0.1.56
DCI1:PMASK_TERM_VCC	0.1.54	0.1.53	0.1.52	0.1.51
non-inverted	[3]	[2]	[1]	[0]

MISC:DCI_TEST_MUX	0.0.50
DCI0	0
DCI1	1

MISC:HSWAPENPIN	0.1.26	0.1.27
MISC:TDIPIN	0.1.29	0.1.28
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:PROGPIN	0.1.25
PULLUP	0
PULLNONE	1

`UL.S3E`

This tile is used on Spartan 3E.

spartan3 UL.S3E bittile 0
Bit	Frame
Bit	0	1
45	BANK:LVDSBIAS_1[0]	-
44	BANK:LVDSBIAS_0[0]	-
43	BANK:LVDSBIAS_1[1]	-
42	BANK:LVDSBIAS_1[2]	-
41	BANK:LVDSBIAS_1[3]	-
40	BANK:LVDSBIAS_1[4]	-
39	BANK:LVDSBIAS_0[1]	-
38	BANK:LVDSBIAS_0[2]	-
37	BANK:LVDSBIAS_0[3]	-
36	BANK:LVDSBIAS_0[4]	-
35	BANK:LVDSBIAS_1[5]	-
34	BANK:LVDSBIAS_1[6]	-
33	BANK:LVDSBIAS_1[7]	-
32	BANK:LVDSBIAS_1[8]	MISC:TEST_LL
31	-	-
30	-	-
29	BANK:LVDSBIAS_1[9]	MISC:TDIPIN[1]
28	BANK:LVDSBIAS_1[10]	MISC:TDIPIN[0]
27	BANK:LVDSBIAS_0[5]	-
26	BANK:LVDSBIAS_0[6]	-
25	BANK:LVDSBIAS_0[7]	MISC:PROGPIN[0]
24	BANK:LVDSBIAS_0[8]	-
23	BANK:LVDSBIAS_0[9]	-
22	BANK:LVDSBIAS_0[10]	-
21	-	-
20	-	-
19	-	-
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

BANK:LVDSBIAS_0	0.0.22	0.0.23	0.0.24	0.0.25	0.0.26	0.0.27	0.0.36	0.0.37	0.0.38	0.0.39	0.0.44
BANK:LVDSBIAS_1	0.0.28	0.0.29	0.0.32	0.0.33	0.0.34	0.0.35	0.0.40	0.0.41	0.0.42	0.0.43	0.0.45
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:PROGPIN	0.1.25
PULLUP	0
PULLNONE	1

MISC:TDIPIN	0.1.29	0.1.28
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:TEST_LL	0.1.32
non-inverted	[0]

`UL.S3A`

This tile is used on Spartan 3A.

spartan3 UL.S3A bittile 0
Bit	Frame
Bit	0	1
63	-	BANK:LVDSBIAS_1[0]
62	-	BANK:LVDSBIAS_0[0]
61	-	BANK:LVDSBIAS_1[1]
60	-	BANK:LVDSBIAS_0[1]
59	-	BANK:LVDSBIAS_1[2]
58	-	BANK:LVDSBIAS_1[3]
57	-	BANK:LVDSBIAS_1[4]
56	-	BANK:LVDSBIAS_1[5]
55	-	BANK:LVDSBIAS_0[2]
54	-	BANK:LVDSBIAS_0[3]
53	-	BANK:LVDSBIAS_0[4]
52	-	BANK:LVDSBIAS_0[5]
51	-	BANK:LVDSBIAS_1[6]
50	-	BANK:LVDSBIAS_1[7]
49	-	BANK:LVDSBIAS_1[8]
48	-	BANK:LVDSBIAS_1[9]
47	-	BANK:LVDSBIAS_1[10]
46	-	BANK:LVDSBIAS_1[11]
45	-	BANK:LVDSBIAS_0[6]
44	-	BANK:LVDSBIAS_0[7]
43	-	BANK:LVDSBIAS_0[8]
42	-	BANK:LVDSBIAS_0[9]
41	-	BANK:LVDSBIAS_0[10]
40	-	BANK:LVDSBIAS_0[11]
39	-	-
38	-	-
37	-	-
36	-	-
35	-	-
34	-	-
33	-	-
32	-	MISC:TEST_LL
31	MISC:TMSPIN[1]	-
30	MISC:TMSPIN[0]	-
29	-	MISC:TDIPIN[1]
28	-	MISC:TDIPIN[0]
27	-	-
26	-	-
25	-	MISC:PROGPIN[0]
24	-	-
23	-	-
22	-	-
21	-	-
20	-	-
19	-	-
18	-	-
17	-	-
16	-	-
15	-	-
14	-	-
13	-	-
12	-	-
11	-	-
10	-	-
9	-	-
8	-	-
7	-	-
6	-	-
5	-	-
4	-	-
3	-	-
2	-	-
1	-	-
0	-	-

BANK:LVDSBIAS_0	0.1.40	0.1.41	0.1.42	0.1.43	0.1.44	0.1.45	0.1.52	0.1.53	0.1.54	0.1.55	0.1.60	0.1.62
BANK:LVDSBIAS_1	0.1.46	0.1.47	0.1.48	0.1.49	0.1.50	0.1.51	0.1.56	0.1.57	0.1.58	0.1.59	0.1.61	0.1.63
non-inverted	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

MISC:PROGPIN	0.1.25
PULLUP	0
PULLNONE	1

MISC:TDIPIN	0.1.29	0.1.28
MISC:TMSPIN	0.0.31	0.0.30
PULLUP	0	0
PULLNONE	0	1
PULLDOWN	1	1

MISC:TEST_LL	0.1.32
non-inverted	[0]