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North-west

TODO: document

CNR_NW_S3

This tile is used on Spartan 3.

Tile CNR_NW_S3

Cells: 1

Bels DCI

spartan3 CNR_NW_S3 bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_DATA[23]IMUX_DATA[15]
DCI_RESETinIMUX_DATA[22]IMUX_DATA[14]
HI_LO_PinIMUX_DATA[20]IMUX_DATA[12]
HI_LO_NinIMUX_DATA[21]IMUX_DATA[13]
SCLKoutOUT_SEC[6]OUT_SEC[6]
ADDRESS[0]outOUT_SEC[0]OUT_SEC[0]
ADDRESS[1]outOUT_SEC[1]OUT_SEC[1]
ADDRESS[2]outOUT_SEC[2]OUT_SEC[2]
DATAoutOUT_SEC[3]OUT_SEC[3]
N_OR_PoutOUT_SEC[5]OUT_SEC[5]
UPDATEoutOUT_SEC[7]OUT_SEC[7]
IOUPDATEoutOUT_SEC[8]OUT_SEC[8]
DCI_DONEoutOUT_SEC[4]OUT_SEC[4]
spartan3 CNR_NW_S3 bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[0][44]TERM_H[1][44]
TEST_ENABLETERM_H[0][62]TERM_H[1][62]
FORCE_DONE_HIGHTERM_H[0][61]TERM_H[1][61]
S3_PMASK_TERM_SPLIT bit 0TERM_H[0][56]TERM_H[1][56]
S3_PMASK_TERM_SPLIT bit 1TERM_H[0][57]TERM_H[1][57]
S3_PMASK_TERM_SPLIT bit 2TERM_H[0][58]TERM_H[1][58]
S3_PMASK_TERM_SPLIT bit 3TERM_H[0][59]TERM_H[1][59]
S3_NMASK_TERM_SPLIT bit 0TERM_H[0][46]TERM_H[1][46]
S3_NMASK_TERM_SPLIT bit 1TERM_H[0][47]TERM_H[1][47]
S3_NMASK_TERM_SPLIT bit 2TERM_H[0][48]TERM_H[1][48]
S3_NMASK_TERM_SPLIT bit 3TERM_H[0][49]TERM_H[1][49]
S3_PMASK_TERM_VCC bit 0TERM_H[0][51]TERM_H[1][51]
S3_PMASK_TERM_VCC bit 1TERM_H[0][52]TERM_H[1][52]
S3_PMASK_TERM_VCC bit 2TERM_H[0][53]TERM_H[1][53]
S3_PMASK_TERM_VCC bit 3TERM_H[0][54]TERM_H[1][54]
S3_LVDSBIAS bit 0TERM_H[1][33]TERM_H[0][33]
S3_LVDSBIAS bit 1TERM_H[1][34]TERM_H[0][34]
S3_LVDSBIAS bit 2TERM_H[1][35]TERM_H[0][35]
S3_LVDSBIAS bit 3TERM_H[1][36]TERM_H[0][36]
S3_LVDSBIAS bit 4TERM_H[1][37]TERM_H[0][37]
S3_LVDSBIAS bit 5TERM_H[1][38]TERM_H[0][38]
S3_LVDSBIAS bit 6TERM_H[1][39]TERM_H[0][39]
S3_LVDSBIAS bit 7TERM_H[1][40]TERM_H[0][40]
S3_LVDSBIAS bit 8TERM_H[1][41]TERM_H[0][41]
S3_LVDSBIAS bit 9TERM_H[1][42]TERM_H[0][42]
S3_LVDSBIAS bit 10TERM_H[1][43]TERM_H[0][43]
S3_LVDSBIAS bit 11TERM_H[1][30]TERM_H[0][29]
S3_LVDSBIAS bit 12TERM_H[1][31]TERM_H[0][32]
QUIETTERM_H[0][45]TERM_H[1][45]

Bels DCIRESET

spartan3 CNR_NW_S3 bel DCIRESET pins
PinDirectionDCIRESET[0]DCIRESET[1]
RSTinIMUX_DATA[19]IMUX_DATA[11]
spartan3 CNR_NW_S3 bel DCIRESET attribute bits
AttributeDCIRESET[0]DCIRESET[1]
ENABLETERM_H[0][63]TERM_H[1][63]

Bels PMV

spartan3 CNR_NW_S3 bel PMV pins
PinDirectionPMV
A[0]inIMUX_DATA[0]
A[1]inIMUX_DATA[1]
A[2]inIMUX_DATA[2]
A[3]inIMUX_DATA[3]
A[4]inIMUX_DATA[4]
A[5]inIMUX_DATA[5]
ENinIMUX_DATA[6]
OoutOUT_FAN[0]

Bels MISC_CNR_S3

spartan3 CNR_NW_S3 bel MISC_CNR_S3 pins
PinDirectionMISC_CNR_S3
spartan3 CNR_NW_S3 bel MISC_CNR_S3 attribute bits
AttributeMISC_CNR_S3
MUX_DCI_TEST bit 0TERM_H[0][50]
DCM_ENABLETERM_H[0][8]

Bels MISC_NW

spartan3 CNR_NW_S3 bel MISC_NW pins
PinDirectionMISC_NW
spartan3 CNR_NW_S3 bel MISC_NW attribute bits
AttributeMISC_NW
HSWAPEN_PULL[enum: IOB_PULL]
PROG_PULL[enum: IOB_PULL]
TDI_PULL[enum: IOB_PULL]
TEST_LLTERM_H[1][32]
spartan3 CNR_NW_S3 enum IOB_PULL
MISC_NW.HSWAPEN_PULLTERM_H[1][26]TERM_H[1][27]
MISC_NW.TDI_PULLTERM_H[1][29]TERM_H[1][28]
NONE01
PULLUP00
PULLDOWN11
spartan3 CNR_NW_S3 enum IOB_PULL
MISC_NW.PROG_PULLTERM_H[1][25]
NONE1
PULLUP0

Bel wires

spartan3 CNR_NW_S3 bel wires
WirePins
IMUX_DATA[0]PMV.A[0]
IMUX_DATA[1]PMV.A[1]
IMUX_DATA[2]PMV.A[2]
IMUX_DATA[3]PMV.A[3]
IMUX_DATA[4]PMV.A[4]
IMUX_DATA[5]PMV.A[5]
IMUX_DATA[6]PMV.EN
IMUX_DATA[11]DCIRESET[1].RST
IMUX_DATA[12]DCI[1].HI_LO_P
IMUX_DATA[13]DCI[1].HI_LO_N
IMUX_DATA[14]DCI[1].DCI_RESET
IMUX_DATA[15]DCI[1].DCI_CLK
IMUX_DATA[19]DCIRESET[0].RST
IMUX_DATA[20]DCI[0].HI_LO_P
IMUX_DATA[21]DCI[0].HI_LO_N
IMUX_DATA[22]DCI[0].DCI_RESET
IMUX_DATA[23]DCI[0].DCI_CLK
OUT_FAN[0]PMV.O
OUT_SEC[0]DCI[0].ADDRESS[0], DCI[1].ADDRESS[0]
OUT_SEC[1]DCI[0].ADDRESS[1], DCI[1].ADDRESS[1]
OUT_SEC[2]DCI[0].ADDRESS[2], DCI[1].ADDRESS[2]
OUT_SEC[3]DCI[0].DATA, DCI[1].DATA
OUT_SEC[4]DCI[0].DCI_DONE, DCI[1].DCI_DONE
OUT_SEC[5]DCI[0].N_OR_P, DCI[1].N_OR_P
OUT_SEC[6]DCI[0].SCLK, DCI[1].SCLK
OUT_SEC[7]DCI[0].UPDATE, DCI[1].UPDATE
OUT_SEC[8]DCI[0].IOUPDATE, DCI[1].IOUPDATE

Bitstream

spartan3 CNR_NW_S3 rect TERM_H
BitFrame
F1 F0
B63 DCIRESET[1]: ENABLE DCIRESET[0]: ENABLE
B62 DCI[1]: TEST_ENABLE DCI[0]: TEST_ENABLE
B61 DCI[1]: FORCE_DONE_HIGH DCI[0]: FORCE_DONE_HIGH
B60 - -
B59 DCI[1]: S3_PMASK_TERM_SPLIT bit 3 DCI[0]: S3_PMASK_TERM_SPLIT bit 3
B58 DCI[1]: S3_PMASK_TERM_SPLIT bit 2 DCI[0]: S3_PMASK_TERM_SPLIT bit 2
B57 DCI[1]: S3_PMASK_TERM_SPLIT bit 1 DCI[0]: S3_PMASK_TERM_SPLIT bit 1
B56 DCI[1]: S3_PMASK_TERM_SPLIT bit 0 DCI[0]: S3_PMASK_TERM_SPLIT bit 0
B55 - -
B54 DCI[1]: S3_PMASK_TERM_VCC bit 3 DCI[0]: S3_PMASK_TERM_VCC bit 3
B53 DCI[1]: S3_PMASK_TERM_VCC bit 2 DCI[0]: S3_PMASK_TERM_VCC bit 2
B52 DCI[1]: S3_PMASK_TERM_VCC bit 1 DCI[0]: S3_PMASK_TERM_VCC bit 1
B51 DCI[1]: S3_PMASK_TERM_VCC bit 0 DCI[0]: S3_PMASK_TERM_VCC bit 0
B50 - MISC_CNR_S3: MUX_DCI_TEST bit 0
B49 DCI[1]: S3_NMASK_TERM_SPLIT bit 3 DCI[0]: S3_NMASK_TERM_SPLIT bit 3
B48 DCI[1]: S3_NMASK_TERM_SPLIT bit 2 DCI[0]: S3_NMASK_TERM_SPLIT bit 2
B47 DCI[1]: S3_NMASK_TERM_SPLIT bit 1 DCI[0]: S3_NMASK_TERM_SPLIT bit 1
B46 DCI[1]: S3_NMASK_TERM_SPLIT bit 0 DCI[0]: S3_NMASK_TERM_SPLIT bit 0
B45 DCI[1]: QUIET DCI[0]: QUIET
B44 DCI[1]: ENABLE DCI[0]: ENABLE
B43 DCI[0]: S3_LVDSBIAS bit 10 DCI[1]: S3_LVDSBIAS bit 10
B42 DCI[0]: S3_LVDSBIAS bit 9 DCI[1]: S3_LVDSBIAS bit 9
B41 DCI[0]: S3_LVDSBIAS bit 8 DCI[1]: S3_LVDSBIAS bit 8
B40 DCI[0]: S3_LVDSBIAS bit 7 DCI[1]: S3_LVDSBIAS bit 7
B39 DCI[0]: S3_LVDSBIAS bit 6 DCI[1]: S3_LVDSBIAS bit 6
B38 DCI[0]: S3_LVDSBIAS bit 5 DCI[1]: S3_LVDSBIAS bit 5
B37 DCI[0]: S3_LVDSBIAS bit 4 DCI[1]: S3_LVDSBIAS bit 4
B36 DCI[0]: S3_LVDSBIAS bit 3 DCI[1]: S3_LVDSBIAS bit 3
B35 DCI[0]: S3_LVDSBIAS bit 2 DCI[1]: S3_LVDSBIAS bit 2
B34 DCI[0]: S3_LVDSBIAS bit 1 DCI[1]: S3_LVDSBIAS bit 1
B33 DCI[0]: S3_LVDSBIAS bit 0 DCI[1]: S3_LVDSBIAS bit 0
B32 MISC_NW: TEST_LL DCI[1]: S3_LVDSBIAS bit 12
B31 DCI[0]: S3_LVDSBIAS bit 12 -
B30 DCI[0]: S3_LVDSBIAS bit 11 -
B29 MISC_NW: TDI_PULL bit 1 DCI[1]: S3_LVDSBIAS bit 11
B28 MISC_NW: TDI_PULL bit 0 -
B27 MISC_NW: HSWAPEN_PULL bit 0 -
B26 MISC_NW: HSWAPEN_PULL bit 1 -
B25 MISC_NW: PROG_PULL bit 0 -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - MISC_CNR_S3: DCM_ENABLE
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -

CNR_NW_FC

This tile is used on FPGAcore.

Tile CNR_NW_FC

Cells: 1

Bels PMV

spartan3 CNR_NW_FC bel PMV pins
PinDirectionPMV
A[0]inIMUX_DATA[0]
A[1]inIMUX_DATA[1]
A[2]inIMUX_DATA[2]
A[3]inIMUX_DATA[3]
A[4]inIMUX_DATA[4]
A[5]inIMUX_DATA[5]
ENinIMUX_DATA[6]
OoutOUT_FAN[0]

Bels MISR_FC

spartan3 CNR_NW_FC bel MISR_FC pins
PinDirectionMISR_FC
CLKinIMUX_CLK_OPTINV[3]
spartan3 CNR_NW_FC bel MISR_FC attribute bits
AttributeMISR_FC
MISR_CLOCKTERM_H[0][1]
MISR_RESETTERM_H[0][0]

Bels MISC_NW

spartan3 CNR_NW_FC bel MISC_NW pins
PinDirectionMISC_NW
spartan3 CNR_NW_FC bel MISC_NW attribute bits
AttributeMISC_NW
TEST_LLTERM_H[1][32]

Bel wires

spartan3 CNR_NW_FC bel wires
WirePins
IMUX_CLK_OPTINV[3]MISR_FC.CLK
IMUX_DATA[0]PMV.A[0]
IMUX_DATA[1]PMV.A[1]
IMUX_DATA[2]PMV.A[2]
IMUX_DATA[3]PMV.A[3]
IMUX_DATA[4]PMV.A[4]
IMUX_DATA[5]PMV.A[5]
IMUX_DATA[6]PMV.EN
OUT_FAN[0]PMV.O

Bitstream

spartan3 CNR_NW_FC rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 MISC_NW: TEST_LL -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - MISR_FC: MISR_CLOCK
B0 - MISR_FC: MISR_RESET

CNR_NW_S3E

This tile is used on Spartan 3E.

Tile CNR_NW_S3E

Cells: 1

Bels PMV

spartan3 CNR_NW_S3E bel PMV pins
PinDirectionPMV
A[0]inIMUX_DATA[0]
A[1]inIMUX_DATA[1]
A[2]inIMUX_DATA[2]
A[3]inIMUX_DATA[3]
A[4]inIMUX_DATA[4]
A[5]inIMUX_DATA[5]
ENinIMUX_DATA[6]
OoutOUT_FAN[0]

Bels MISC_NW

spartan3 CNR_NW_S3E bel MISC_NW pins
PinDirectionMISC_NW
spartan3 CNR_NW_S3E bel MISC_NW attribute bits
AttributeMISC_NW
PROG_PULL[enum: IOB_PULL]
TDI_PULL[enum: IOB_PULL]
TEST_LLTERM_H[1][32]
spartan3 CNR_NW_S3E enum IOB_PULL
MISC_NW.PROG_PULLTERM_H[1][25]
NONE1
PULLUP0
spartan3 CNR_NW_S3E enum IOB_PULL
MISC_NW.TDI_PULLTERM_H[1][29]TERM_H[1][28]
NONE01
PULLUP00
PULLDOWN11

Bels BANK

spartan3 CNR_NW_S3E bel BANK pins
PinDirectionBANK
spartan3 CNR_NW_S3E bel BANK attribute bits
AttributeBANK
S3E_LVDSBIAS[0] bit 0TERM_H[0][44]
S3E_LVDSBIAS[0] bit 1TERM_H[0][39]
S3E_LVDSBIAS[0] bit 2TERM_H[0][38]
S3E_LVDSBIAS[0] bit 3TERM_H[0][37]
S3E_LVDSBIAS[0] bit 4TERM_H[0][36]
S3E_LVDSBIAS[0] bit 5TERM_H[0][27]
S3E_LVDSBIAS[0] bit 6TERM_H[0][26]
S3E_LVDSBIAS[0] bit 7TERM_H[0][25]
S3E_LVDSBIAS[0] bit 8TERM_H[0][24]
S3E_LVDSBIAS[0] bit 9TERM_H[0][23]
S3E_LVDSBIAS[0] bit 10TERM_H[0][22]
S3E_LVDSBIAS[1] bit 0TERM_H[0][45]
S3E_LVDSBIAS[1] bit 1TERM_H[0][43]
S3E_LVDSBIAS[1] bit 2TERM_H[0][42]
S3E_LVDSBIAS[1] bit 3TERM_H[0][41]
S3E_LVDSBIAS[1] bit 4TERM_H[0][40]
S3E_LVDSBIAS[1] bit 5TERM_H[0][35]
S3E_LVDSBIAS[1] bit 6TERM_H[0][34]
S3E_LVDSBIAS[1] bit 7TERM_H[0][33]
S3E_LVDSBIAS[1] bit 8TERM_H[0][32]
S3E_LVDSBIAS[1] bit 9TERM_H[0][29]
S3E_LVDSBIAS[1] bit 10TERM_H[0][28]

Bel wires

spartan3 CNR_NW_S3E bel wires
WirePins
IMUX_DATA[0]PMV.A[0]
IMUX_DATA[1]PMV.A[1]
IMUX_DATA[2]PMV.A[2]
IMUX_DATA[3]PMV.A[3]
IMUX_DATA[4]PMV.A[4]
IMUX_DATA[5]PMV.A[5]
IMUX_DATA[6]PMV.EN
OUT_FAN[0]PMV.O

Bitstream

spartan3 CNR_NW_S3E rect TERM_H
BitFrame
F1 F0
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - BANK: S3E_LVDSBIAS[1] bit 0
B44 - BANK: S3E_LVDSBIAS[0] bit 0
B43 - BANK: S3E_LVDSBIAS[1] bit 1
B42 - BANK: S3E_LVDSBIAS[1] bit 2
B41 - BANK: S3E_LVDSBIAS[1] bit 3
B40 - BANK: S3E_LVDSBIAS[1] bit 4
B39 - BANK: S3E_LVDSBIAS[0] bit 1
B38 - BANK: S3E_LVDSBIAS[0] bit 2
B37 - BANK: S3E_LVDSBIAS[0] bit 3
B36 - BANK: S3E_LVDSBIAS[0] bit 4
B35 - BANK: S3E_LVDSBIAS[1] bit 5
B34 - BANK: S3E_LVDSBIAS[1] bit 6
B33 - BANK: S3E_LVDSBIAS[1] bit 7
B32 MISC_NW: TEST_LL BANK: S3E_LVDSBIAS[1] bit 8
B31 - -
B30 - -
B29 MISC_NW: TDI_PULL bit 1 BANK: S3E_LVDSBIAS[1] bit 9
B28 MISC_NW: TDI_PULL bit 0 BANK: S3E_LVDSBIAS[1] bit 10
B27 - BANK: S3E_LVDSBIAS[0] bit 5
B26 - BANK: S3E_LVDSBIAS[0] bit 6
B25 MISC_NW: PROG_PULL bit 0 BANK: S3E_LVDSBIAS[0] bit 7
B24 - BANK: S3E_LVDSBIAS[0] bit 8
B23 - BANK: S3E_LVDSBIAS[0] bit 9
B22 - BANK: S3E_LVDSBIAS[0] bit 10
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -

CNR_NW_S3A

This tile is used on Spartan 3A.

Tile CNR_NW_S3A

Cells: 1

Bels PMV

spartan3 CNR_NW_S3A bel PMV pins
PinDirectionPMV
A[0]inIMUX_DATA[0]
A[1]inIMUX_DATA[1]
A[2]inIMUX_DATA[2]
A[3]inIMUX_DATA[3]
A[4]inIMUX_DATA[4]
A[5]inIMUX_DATA[5]
ENinIMUX_DATA[6]
OoutOUT_FAN[0]

Bels DNA_PORT

spartan3 CNR_NW_S3A bel DNA_PORT pins
PinDirectionDNA_PORT
CLKinIMUX_CLK_OPTINV[0]
DINinIMUX_SR_OPTINV[1]
READinIMUX_SR_OPTINV[0]
SHIFTinIMUX_SR_OPTINV[2]
DOUToutOUT_FAN[7]

Bels MISC_NW

spartan3 CNR_NW_S3A bel MISC_NW pins
PinDirectionMISC_NW
spartan3 CNR_NW_S3A bel MISC_NW attribute bits
AttributeMISC_NW
PROG_PULL[enum: IOB_PULL]
TDI_PULL[enum: IOB_PULL]
TMS_PULL[enum: IOB_PULL]
TEST_LLTERM_H[1][32]
spartan3 CNR_NW_S3A enum IOB_PULL
MISC_NW.PROG_PULLTERM_H[1][25]
NONE1
PULLUP0
spartan3 CNR_NW_S3A enum IOB_PULL
MISC_NW.TDI_PULLTERM_H[1][29]TERM_H[1][28]
MISC_NW.TMS_PULLTERM_H[0][31]TERM_H[0][30]
NONE01
PULLUP00
PULLDOWN11

Bels BANK

spartan3 CNR_NW_S3A bel BANK pins
PinDirectionBANK
spartan3 CNR_NW_S3A bel BANK attribute bits
AttributeBANK
S3A_LVDSBIAS[0] bit 0TERM_H[1][62]
S3A_LVDSBIAS[0] bit 1TERM_H[1][60]
S3A_LVDSBIAS[0] bit 2TERM_H[1][55]
S3A_LVDSBIAS[0] bit 3TERM_H[1][54]
S3A_LVDSBIAS[0] bit 4TERM_H[1][53]
S3A_LVDSBIAS[0] bit 5TERM_H[1][52]
S3A_LVDSBIAS[0] bit 6TERM_H[1][45]
S3A_LVDSBIAS[0] bit 7TERM_H[1][44]
S3A_LVDSBIAS[0] bit 8TERM_H[1][43]
S3A_LVDSBIAS[0] bit 9TERM_H[1][42]
S3A_LVDSBIAS[0] bit 10TERM_H[1][41]
S3A_LVDSBIAS[0] bit 11TERM_H[1][40]
S3A_LVDSBIAS[1] bit 0TERM_H[1][63]
S3A_LVDSBIAS[1] bit 1TERM_H[1][61]
S3A_LVDSBIAS[1] bit 2TERM_H[1][59]
S3A_LVDSBIAS[1] bit 3TERM_H[1][58]
S3A_LVDSBIAS[1] bit 4TERM_H[1][57]
S3A_LVDSBIAS[1] bit 5TERM_H[1][56]
S3A_LVDSBIAS[1] bit 6TERM_H[1][51]
S3A_LVDSBIAS[1] bit 7TERM_H[1][50]
S3A_LVDSBIAS[1] bit 8TERM_H[1][49]
S3A_LVDSBIAS[1] bit 9TERM_H[1][48]
S3A_LVDSBIAS[1] bit 10TERM_H[1][47]
S3A_LVDSBIAS[1] bit 11TERM_H[1][46]

Bel wires

spartan3 CNR_NW_S3A bel wires
WirePins
IMUX_CLK_OPTINV[0]DNA_PORT.CLK
IMUX_SR_OPTINV[0]DNA_PORT.READ
IMUX_SR_OPTINV[1]DNA_PORT.DIN
IMUX_SR_OPTINV[2]DNA_PORT.SHIFT
IMUX_DATA[0]PMV.A[0]
IMUX_DATA[1]PMV.A[1]
IMUX_DATA[2]PMV.A[2]
IMUX_DATA[3]PMV.A[3]
IMUX_DATA[4]PMV.A[4]
IMUX_DATA[5]PMV.A[5]
IMUX_DATA[6]PMV.EN
OUT_FAN[0]PMV.O
OUT_FAN[7]DNA_PORT.DOUT

Bitstream

spartan3 CNR_NW_S3A rect TERM_H
BitFrame
F1 F0
B63 BANK: S3A_LVDSBIAS[1] bit 0 -
B62 BANK: S3A_LVDSBIAS[0] bit 0 -
B61 BANK: S3A_LVDSBIAS[1] bit 1 -
B60 BANK: S3A_LVDSBIAS[0] bit 1 -
B59 BANK: S3A_LVDSBIAS[1] bit 2 -
B58 BANK: S3A_LVDSBIAS[1] bit 3 -
B57 BANK: S3A_LVDSBIAS[1] bit 4 -
B56 BANK: S3A_LVDSBIAS[1] bit 5 -
B55 BANK: S3A_LVDSBIAS[0] bit 2 -
B54 BANK: S3A_LVDSBIAS[0] bit 3 -
B53 BANK: S3A_LVDSBIAS[0] bit 4 -
B52 BANK: S3A_LVDSBIAS[0] bit 5 -
B51 BANK: S3A_LVDSBIAS[1] bit 6 -
B50 BANK: S3A_LVDSBIAS[1] bit 7 -
B49 BANK: S3A_LVDSBIAS[1] bit 8 -
B48 BANK: S3A_LVDSBIAS[1] bit 9 -
B47 BANK: S3A_LVDSBIAS[1] bit 10 -
B46 BANK: S3A_LVDSBIAS[1] bit 11 -
B45 BANK: S3A_LVDSBIAS[0] bit 6 -
B44 BANK: S3A_LVDSBIAS[0] bit 7 -
B43 BANK: S3A_LVDSBIAS[0] bit 8 -
B42 BANK: S3A_LVDSBIAS[0] bit 9 -
B41 BANK: S3A_LVDSBIAS[0] bit 10 -
B40 BANK: S3A_LVDSBIAS[0] bit 11 -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 MISC_NW: TEST_LL -
B31 - MISC_NW: TMS_PULL bit 1
B30 - MISC_NW: TMS_PULL bit 0
B29 MISC_NW: TDI_PULL bit 1 -
B28 MISC_NW: TDI_PULL bit 0 -
B27 - -
B26 - -
B25 MISC_NW: PROG_PULL bit 0 -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -