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North-west

TODO: document

UL.S3

This tile is used on Spartan 3.

Tile UL.S3

Cells: 1

Bel DCI0

spartan3 UL.S3 bel DCI0
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA23
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA22
HI_LO_NinputIMUX.DATA21
HI_LO_PinputIMUX.DATA20
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCI1

spartan3 UL.S3 bel DCI1
PinDirectionWires
ADDRESS0outputOUT.SEC0
ADDRESS1outputOUT.SEC1
ADDRESS2outputOUT.SEC2
DATAoutputOUT.SEC3
DCI_CLKinputIMUX.DATA15
DCI_DONEoutputOUT.SEC4
DCI_RESETinputIMUX.DATA14
HI_LO_NinputIMUX.DATA13
HI_LO_PinputIMUX.DATA12
IOUPDATEoutputOUT.SEC8
N_OR_PoutputOUT.SEC5
SCLKoutputOUT.SEC6
UPDATEoutputOUT.SEC7

Bel DCIRESET0

spartan3 UL.S3 bel DCIRESET0
PinDirectionWires
RSTinputIMUX.DATA19

Bel DCIRESET1

spartan3 UL.S3 bel DCIRESET1
PinDirectionWires
RSTinputIMUX.DATA11

Bel PMV

spartan3 UL.S3 bel PMV
PinDirectionWires
A0inputIMUX.DATA0
A1inputIMUX.DATA1
A2inputIMUX.DATA2
A3inputIMUX.DATA3
A4inputIMUX.DATA4
A5inputIMUX.DATA5
ENinputIMUX.DATA6
OoutputOUT.FAN0

Bel wires

spartan3 UL.S3 bel wires
WirePins
IMUX.DATA0PMV.A0
IMUX.DATA1PMV.A1
IMUX.DATA2PMV.A2
IMUX.DATA3PMV.A3
IMUX.DATA4PMV.A4
IMUX.DATA5PMV.A5
IMUX.DATA6PMV.EN
IMUX.DATA11DCIRESET1.RST
IMUX.DATA12DCI1.HI_LO_P
IMUX.DATA13DCI1.HI_LO_N
IMUX.DATA14DCI1.DCI_RESET
IMUX.DATA15DCI1.DCI_CLK
IMUX.DATA19DCIRESET0.RST
IMUX.DATA20DCI0.HI_LO_P
IMUX.DATA21DCI0.HI_LO_N
IMUX.DATA22DCI0.DCI_RESET
IMUX.DATA23DCI0.DCI_CLK
OUT.FAN0PMV.O
OUT.SEC0DCI0.ADDRESS0, DCI1.ADDRESS0
OUT.SEC1DCI0.ADDRESS1, DCI1.ADDRESS1
OUT.SEC2DCI0.ADDRESS2, DCI1.ADDRESS2
OUT.SEC3DCI0.DATA, DCI1.DATA
OUT.SEC4DCI0.DCI_DONE, DCI1.DCI_DONE
OUT.SEC5DCI0.N_OR_P, DCI1.N_OR_P
OUT.SEC6DCI0.SCLK, DCI1.SCLK
OUT.SEC7DCI0.UPDATE, DCI1.UPDATE
OUT.SEC8DCI0.IOUPDATE, DCI1.IOUPDATE

Bitstream

spartan3 UL.S3 bittile 0
BitFrame
0 1
63 DCIRESET0:ENABLE DCIRESET1:ENABLE
62 DCI0:TEST_ENABLE DCI1:TEST_ENABLE
61 DCI0:FORCE_DONE_HIGH DCI1:FORCE_DONE_HIGH
60 - -
59 DCI0:PMASK_TERM_SPLIT[3] DCI1:PMASK_TERM_SPLIT[3]
58 DCI0:PMASK_TERM_SPLIT[2] DCI1:PMASK_TERM_SPLIT[2]
57 DCI0:PMASK_TERM_SPLIT[1] DCI1:PMASK_TERM_SPLIT[1]
56 DCI0:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[0]
55 - -
54 DCI0:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_VCC[3]
53 DCI0:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_VCC[2]
52 DCI0:PMASK_TERM_VCC[1] DCI1:PMASK_TERM_VCC[1]
51 DCI0:PMASK_TERM_VCC[0] DCI1:PMASK_TERM_VCC[0]
50 MISC:DCI_TEST_MUX[0] -
49 DCI0:NMASK_TERM_SPLIT[3] DCI1:NMASK_TERM_SPLIT[3]
48 DCI0:NMASK_TERM_SPLIT[2] DCI1:NMASK_TERM_SPLIT[2]
47 DCI0:NMASK_TERM_SPLIT[1] DCI1:NMASK_TERM_SPLIT[1]
46 DCI0:NMASK_TERM_SPLIT[0] DCI1:NMASK_TERM_SPLIT[0]
45 DCI0:QUIET DCI1:QUIET
44 DCI0:ENABLE DCI1:ENABLE
43 DCI1:LVDSBIAS[2] DCI0:LVDSBIAS[2]
42 DCI1:LVDSBIAS[3] DCI0:LVDSBIAS[3]
41 DCI1:LVDSBIAS[4] DCI0:LVDSBIAS[4]
40 DCI1:LVDSBIAS[5] DCI0:LVDSBIAS[5]
39 DCI1:LVDSBIAS[6] DCI0:LVDSBIAS[6]
38 DCI1:LVDSBIAS[7] DCI0:LVDSBIAS[7]
37 DCI1:LVDSBIAS[8] DCI0:LVDSBIAS[8]
36 DCI1:LVDSBIAS[9] DCI0:LVDSBIAS[9]
35 DCI1:LVDSBIAS[10] DCI0:LVDSBIAS[10]
34 DCI1:LVDSBIAS[11] DCI0:LVDSBIAS[11]
33 DCI1:LVDSBIAS[12] DCI0:LVDSBIAS[12]
32 DCI1:LVDSBIAS[0] MISC:TEST_LL
31 - DCI0:LVDSBIAS[0]
30 - DCI0:LVDSBIAS[1]
29 DCI1:LVDSBIAS[1] MISC:TDIPIN[1]
28 - MISC:TDIPIN[0]
27 - MISC:HSWAPENPIN[0]
26 - MISC:HSWAPENPIN[1]
25 - MISC:PROGPIN[0]
24 - -
23 - -
22 - -
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - -
14 - -
13 - -
12 - -
11 - -
10 - -
9 - -
8 MISC:DCM_ENABLE -
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 - -
DCI0:ENABLE 0.0.44
DCI0:FORCE_DONE_HIGH 0.0.61
DCI0:QUIET 0.0.45
DCI0:TEST_ENABLE 0.0.62
DCI1:ENABLE 0.1.44
DCI1:FORCE_DONE_HIGH 0.1.61
DCI1:QUIET 0.1.45
DCI1:TEST_ENABLE 0.1.62
DCIRESET0:ENABLE 0.0.63
DCIRESET1:ENABLE 0.1.63
MISC:DCM_ENABLE 0.0.8
MISC:TEST_LL 0.1.32
non-inverted [0]
DCI0:LVDSBIAS 0.1.33 0.1.34 0.1.35 0.1.36 0.1.37 0.1.38 0.1.39 0.1.40 0.1.41 0.1.42 0.1.43 0.1.30 0.1.31
DCI1:LVDSBIAS 0.0.33 0.0.34 0.0.35 0.0.36 0.0.37 0.0.38 0.0.39 0.0.40 0.0.41 0.0.42 0.0.43 0.0.29 0.0.32
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.0.49 0.0.48 0.0.47 0.0.46
DCI0:PMASK_TERM_SPLIT 0.0.59 0.0.58 0.0.57 0.0.56
DCI0:PMASK_TERM_VCC 0.0.54 0.0.53 0.0.52 0.0.51
DCI1:NMASK_TERM_SPLIT 0.1.49 0.1.48 0.1.47 0.1.46
DCI1:PMASK_TERM_SPLIT 0.1.59 0.1.58 0.1.57 0.1.56
DCI1:PMASK_TERM_VCC 0.1.54 0.1.53 0.1.52 0.1.51
non-inverted [3] [2] [1] [0]
MISC:DCI_TEST_MUX 0.0.50
DCI0 0
DCI1 1
MISC:HSWAPENPIN 0.1.26 0.1.27
MISC:TDIPIN 0.1.29 0.1.28
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1
MISC:PROGPIN 0.1.25
PULLUP 0
PULLNONE 1

UL.S3E

This tile is used on Spartan 3E.

Tile UL.S3E

Cells: 1

Bel PMV

spartan3 UL.S3E bel PMV
PinDirectionWires
A0inputIMUX.DATA0
A1inputIMUX.DATA1
A2inputIMUX.DATA2
A3inputIMUX.DATA3
A4inputIMUX.DATA4
A5inputIMUX.DATA5
ENinputIMUX.DATA6
OoutputOUT.FAN0

Bel wires

spartan3 UL.S3E bel wires
WirePins
IMUX.DATA0PMV.A0
IMUX.DATA1PMV.A1
IMUX.DATA2PMV.A2
IMUX.DATA3PMV.A3
IMUX.DATA4PMV.A4
IMUX.DATA5PMV.A5
IMUX.DATA6PMV.EN
OUT.FAN0PMV.O

Bitstream

spartan3 UL.S3E bittile 0
BitFrame
0 1
45 BANK:LVDSBIAS_1[0] -
44 BANK:LVDSBIAS_0[0] -
43 BANK:LVDSBIAS_1[1] -
42 BANK:LVDSBIAS_1[2] -
41 BANK:LVDSBIAS_1[3] -
40 BANK:LVDSBIAS_1[4] -
39 BANK:LVDSBIAS_0[1] -
38 BANK:LVDSBIAS_0[2] -
37 BANK:LVDSBIAS_0[3] -
36 BANK:LVDSBIAS_0[4] -
35 BANK:LVDSBIAS_1[5] -
34 BANK:LVDSBIAS_1[6] -
33 BANK:LVDSBIAS_1[7] -
32 BANK:LVDSBIAS_1[8] MISC:TEST_LL
31 - -
30 - -
29 BANK:LVDSBIAS_1[9] MISC:TDIPIN[1]
28 BANK:LVDSBIAS_1[10] MISC:TDIPIN[0]
27 BANK:LVDSBIAS_0[5] -
26 BANK:LVDSBIAS_0[6] -
25 BANK:LVDSBIAS_0[7] MISC:PROGPIN[0]
24 BANK:LVDSBIAS_0[8] -
23 BANK:LVDSBIAS_0[9] -
22 BANK:LVDSBIAS_0[10] -
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - -
14 - -
13 - -
12 - -
11 - -
10 - -
9 - -
8 - -
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 - -
BANK:LVDSBIAS_0 0.0.22 0.0.23 0.0.24 0.0.25 0.0.26 0.0.27 0.0.36 0.0.37 0.0.38 0.0.39 0.0.44
BANK:LVDSBIAS_1 0.0.28 0.0.29 0.0.32 0.0.33 0.0.34 0.0.35 0.0.40 0.0.41 0.0.42 0.0.43 0.0.45
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:PROGPIN 0.1.25
PULLUP 0
PULLNONE 1
MISC:TDIPIN 0.1.29 0.1.28
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1
MISC:TEST_LL 0.1.32
non-inverted [0]

UL.S3A

This tile is used on Spartan 3A.

Tile UL.S3A

Cells: 1

Bel PMV

spartan3 UL.S3A bel PMV
PinDirectionWires
A0inputIMUX.DATA0
A1inputIMUX.DATA1
A2inputIMUX.DATA2
A3inputIMUX.DATA3
A4inputIMUX.DATA4
A5inputIMUX.DATA5
ENinputIMUX.DATA6
OoutputOUT.FAN0

Bel DNA_PORT

spartan3 UL.S3A bel DNA_PORT
PinDirectionWires
CLKinputIMUX.CLK0
DINinputIMUX.SR1
DOUToutputOUT.FAN7
READinputIMUX.SR0
SHIFTinputIMUX.SR2

Bel wires

spartan3 UL.S3A bel wires
WirePins
IMUX.SR0DNA_PORT.READ
IMUX.SR1DNA_PORT.DIN
IMUX.SR2DNA_PORT.SHIFT
IMUX.CLK0DNA_PORT.CLK
IMUX.DATA0PMV.A0
IMUX.DATA1PMV.A1
IMUX.DATA2PMV.A2
IMUX.DATA3PMV.A3
IMUX.DATA4PMV.A4
IMUX.DATA5PMV.A5
IMUX.DATA6PMV.EN
OUT.FAN0PMV.O
OUT.FAN7DNA_PORT.DOUT

Bitstream

spartan3 UL.S3A bittile 0
BitFrame
0 1
63 - BANK:LVDSBIAS_1[0]
62 - BANK:LVDSBIAS_0[0]
61 - BANK:LVDSBIAS_1[1]
60 - BANK:LVDSBIAS_0[1]
59 - BANK:LVDSBIAS_1[2]
58 - BANK:LVDSBIAS_1[3]
57 - BANK:LVDSBIAS_1[4]
56 - BANK:LVDSBIAS_1[5]
55 - BANK:LVDSBIAS_0[2]
54 - BANK:LVDSBIAS_0[3]
53 - BANK:LVDSBIAS_0[4]
52 - BANK:LVDSBIAS_0[5]
51 - BANK:LVDSBIAS_1[6]
50 - BANK:LVDSBIAS_1[7]
49 - BANK:LVDSBIAS_1[8]
48 - BANK:LVDSBIAS_1[9]
47 - BANK:LVDSBIAS_1[10]
46 - BANK:LVDSBIAS_1[11]
45 - BANK:LVDSBIAS_0[6]
44 - BANK:LVDSBIAS_0[7]
43 - BANK:LVDSBIAS_0[8]
42 - BANK:LVDSBIAS_0[9]
41 - BANK:LVDSBIAS_0[10]
40 - BANK:LVDSBIAS_0[11]
39 - -
38 - -
37 - -
36 - -
35 - -
34 - -
33 - -
32 - MISC:TEST_LL
31 MISC:TMSPIN[1] -
30 MISC:TMSPIN[0] -
29 - MISC:TDIPIN[1]
28 - MISC:TDIPIN[0]
27 - -
26 - -
25 - MISC:PROGPIN[0]
24 - -
23 - -
22 - -
21 - -
20 - -
19 - -
18 - -
17 - -
16 - -
15 - -
14 - -
13 - -
12 - -
11 - -
10 - -
9 - -
8 - -
7 - -
6 - -
5 - -
4 - -
3 - -
2 - -
1 - -
0 - -
BANK:LVDSBIAS_0 0.1.40 0.1.41 0.1.42 0.1.43 0.1.44 0.1.45 0.1.52 0.1.53 0.1.54 0.1.55 0.1.60 0.1.62
BANK:LVDSBIAS_1 0.1.46 0.1.47 0.1.48 0.1.49 0.1.50 0.1.51 0.1.56 0.1.57 0.1.58 0.1.59 0.1.61 0.1.63
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:PROGPIN 0.1.25
PULLUP 0
PULLNONE 1
MISC:TDIPIN 0.1.29 0.1.28
MISC:TMSPIN 0.0.31 0.0.30
PULLUP 0 0
PULLNONE 0 1
PULLDOWN 1 1
MISC:TEST_LL 0.1.32
non-inverted [0]