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I/O Interface

TODO: document

Tile IOI_S3

Cells: 1

Bel IOI[0]

spartan3 IOI_S3 bel IOI[0]
PinDirectionWires
IoutputOUT_FAN[4]
ICEinputIMUX_DATA[8]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[8]
IQ2outputOUT_SEC[12]
O1inputIMUX_DATA[24]
O2inputIMUX_DATA[28]
OCEinputIMUX_CE[0]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[0]
SRinputIMUX_SR[0]
ToutputOUT_FAN[0]
T1inputIMUX_DATA[16]
T2inputIMUX_DATA[20]
TCEinputIMUX_DATA[4]

Bel IOI[1]

spartan3 IOI_S3 bel IOI[1]
PinDirectionWires
IoutputOUT_FAN[5]
ICEinputIMUX_DATA[9]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[9]
IQ2outputOUT_SEC[13]
O1inputIMUX_DATA[25]
O2inputIMUX_DATA[29]
OCEinputIMUX_CE[1]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[1]
SRinputIMUX_SR[1]
ToutputOUT_FAN[1]
T1inputIMUX_DATA[17]
T2inputIMUX_DATA[21]
TCEinputIMUX_DATA[5]

Bel IOI[2]

spartan3 IOI_S3 bel IOI[2]
PinDirectionWires
IoutputOUT_FAN[6]
ICEinputIMUX_DATA[10]
ICLK1inputIMUX_IOCLK[2]
ICLK2inputIMUX_IOCLK[6]
IQ1outputOUT_SEC[10]
IQ2outputOUT_SEC[14]
O1inputIMUX_DATA[26]
O2inputIMUX_DATA[30]
OCEinputIMUX_CE[2]
OTCLK1inputIMUX_IOCLK[3]
OTCLK2inputIMUX_IOCLK[7]
REVinputIMUX_DATA[2]
SRinputIMUX_SR[2]
ToutputOUT_FAN[2]
T1inputIMUX_DATA[18]
T2inputIMUX_DATA[22]
TCEinputIMUX_DATA[6]

Bel wires

spartan3 IOI_S3 bel wires
WirePins
IMUX_SR[0]IOI[0].SR
IMUX_SR[1]IOI[1].SR
IMUX_SR[2]IOI[2].SR
IMUX_CE[0]IOI[0].OCE
IMUX_CE[1]IOI[1].OCE
IMUX_CE[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3 rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_S3 rect R0
BitFrame
F0 F1 F2 F3
B59 IOI[2]:TMUX[2] IOI[2]:OMUX[2] - -
B58 IOI[2]:TFF2_LATCH IOI[2]:OFF2_LATCH - -
B57 IOI[2]:TFF1_LATCH IOI[2]:OFF1_LATCH - ~IOI[2]:INV.TCE
B56 IOI[2]:TMUX[0] IOI[2]:OMUX[0] ~IOI[2]:IFF2_SRVAL ~IOI[2]:INV.OTCLK1
B55 IOI[2]:TMUX[3] IOI[2]:OMUX[3] - ~IOI[2]:INV.OTCLK2
B54 IOI[2]:TMUX[1] IOI[2]:OMUX[1] - ~IOI[2]:INV.ICE
B53 IOI[2]:TFF_SR_SYNC IOI[2]:OFF_SR_SYNC - ~IOI[2]:INV.ICLK1
B52 IOI[2]:INV.T1 IOI[2]:INV.O1 ~IOI[2]:IFF2_INIT ~IOI[2]:INV.ICLK2
B51 IOI[2]:INV.T2 IOI[2]:INV.O2 IOI[2]:IFF_LATCH ~IOI[2]:INV.REV
B50 IOI[2]:TFF_SR_ENABLE IOI[2]:OFF_SR_ENABLE IOI[2]:IFF_SR_ENABLE IOI[2]:I_DELAY_ENABLE
B49 IOI[2]:TFF_REV_ENABLE IOI[2]:OFF_REV_ENABLE IOI[2]:IFF_REV_ENABLE -
B48 ~IOI[2]:TFF_INIT ~IOI[2]:OFF_INIT IOI[2]:IFF_SR_SYNC -
B47 - - ~IOI[2]:IFF1_INIT IOI[2]:I_TSBYPASS_ENABLE
B46 - - - -
B45 ~IOI[2]:TFF2_SRVAL ~IOI[2]:OFF2_SRVAL - -
B44 - - - IOI[2]:TSBYPASS_MUX[0]
B43 ~IOI[2]:TFF1_SRVAL ~IOI[2]:OFF1_SRVAL ~IOI[2]:IFF1_SRVAL IOI[2]:IFF_TSBYPASS_ENABLE
B42 - - - -
B41 - - - IOI[2]:IFF_DELAY_ENABLE
B40 - - - IOI[2]:READBACK_I
B39 - - - IOI[1]:READBACK_I
B38 - - - IOI[1]:IFF_DELAY_ENABLE
B37 - - - -
B36 ~IOI[1]:TFF1_SRVAL ~IOI[1]:OFF1_SRVAL ~IOI[1]:IFF1_SRVAL IOI[1]:IFF_TSBYPASS_ENABLE
B35 - - - IOI[1]:TSBYPASS_MUX[0]
B34 ~IOI[1]:TFF2_SRVAL ~IOI[1]:OFF2_SRVAL - -
B33 - - - -
B32 - - ~IOI[1]:IFF1_INIT IOI[1]:I_TSBYPASS_ENABLE
B31 ~IOI[1]:TFF_INIT ~IOI[1]:OFF_INIT IOI[1]:IFF_SR_SYNC -
B30 IOI[1]:TFF_REV_ENABLE IOI[1]:OFF_REV_ENABLE IOI[1]:IFF_REV_ENABLE -
B29 IOI[1]:TFF_SR_ENABLE IOI[1]:OFF_SR_ENABLE IOI[1]:IFF_SR_ENABLE IOI[1]:I_DELAY_ENABLE
B28 IOI[1]:INV.T2 IOI[1]:INV.O2 IOI[1]:IFF_LATCH ~IOI[1]:INV.REV
B27 IOI[1]:INV.T1 IOI[1]:INV.O1 ~IOI[1]:IFF2_INIT ~IOI[1]:INV.ICLK2
B26 IOI[1]:TFF_SR_SYNC IOI[1]:OFF_SR_SYNC - ~IOI[1]:INV.ICLK1
B25 IOI[1]:TMUX[1] IOI[1]:OMUX[1] - ~IOI[1]:INV.ICE
B24 IOI[1]:TMUX[3] IOI[1]:OMUX[3] - ~IOI[1]:INV.OTCLK2
B23 IOI[1]:TMUX[0] IOI[1]:OMUX[0] ~IOI[1]:IFF2_SRVAL ~IOI[1]:INV.OTCLK1
B22 IOI[1]:TFF1_LATCH IOI[1]:OFF1_LATCH - ~IOI[1]:INV.TCE
B21 IOI[1]:TFF2_LATCH IOI[1]:OFF2_LATCH - -
B20 IOI[1]:TMUX[2] IOI[1]:OMUX[2] - -
B19 IOI[0]:TMUX[2] IOI[0]:OMUX[2] - -
B18 IOI[0]:TFF2_LATCH IOI[0]:OFF2_LATCH - -
B17 IOI[0]:TFF1_LATCH IOI[0]:OFF1_LATCH - ~IOI[0]:INV.TCE
B16 IOI[0]:TMUX[0] IOI[0]:OMUX[0] ~IOI[0]:IFF2_SRVAL ~IOI[0]:INV.OTCLK1
B15 IOI[0]:TMUX[3] IOI[0]:OMUX[3] - ~IOI[0]:INV.OTCLK2
B14 IOI[0]:TMUX[1] IOI[0]:OMUX[1] - ~IOI[0]:INV.ICE
B13 IOI[0]:TFF_SR_SYNC IOI[0]:OFF_SR_SYNC - ~IOI[0]:INV.ICLK1
B12 IOI[0]:INV.T1 IOI[0]:INV.O1 ~IOI[0]:IFF2_INIT ~IOI[0]:INV.ICLK2
B11 IOI[0]:INV.T2 IOI[0]:INV.O2 IOI[0]:IFF_LATCH ~IOI[0]:INV.REV
B10 IOI[0]:TFF_SR_ENABLE IOI[0]:OFF_SR_ENABLE IOI[0]:IFF_SR_ENABLE IOI[0]:I_DELAY_ENABLE
B9 IOI[0]:TFF_REV_ENABLE IOI[0]:OFF_REV_ENABLE IOI[0]:IFF_REV_ENABLE -
B8 ~IOI[0]:TFF_INIT ~IOI[0]:OFF_INIT IOI[0]:IFF_SR_SYNC -
B7 - - ~IOI[0]:IFF1_INIT IOI[0]:I_TSBYPASS_ENABLE
B6 - - - -
B5 ~IOI[0]:TFF2_SRVAL ~IOI[0]:OFF2_SRVAL - -
B4 - - - IOI[0]:TSBYPASS_MUX[0]
B3 ~IOI[0]:TFF1_SRVAL ~IOI[0]:OFF1_SRVAL ~IOI[0]:IFF1_SRVAL IOI[0]:IFF_TSBYPASS_ENABLE
B2 - - - -
B1 - - - IOI[0]:IFF_DELAY_ENABLE
B0 - - - IOI[0]:READBACK_I
IOI[0]:IFF1_INIT 0.F2.B7
IOI[0]:IFF1_SRVAL 0.F2.B3
IOI[0]:IFF2_INIT 0.F2.B12
IOI[0]:IFF2_SRVAL 0.F2.B16
IOI[0]:INV.ICE 0.F3.B14
IOI[0]:INV.ICLK1 0.F3.B13
IOI[0]:INV.ICLK2 0.F3.B12
IOI[0]:INV.OTCLK1 0.F3.B16
IOI[0]:INV.OTCLK2 0.F3.B15
IOI[0]:INV.REV 0.F3.B11
IOI[0]:INV.TCE 0.F3.B17
IOI[0]:OFF1_SRVAL 0.F1.B3
IOI[0]:OFF2_SRVAL 0.F1.B5
IOI[0]:OFF_INIT 0.F1.B8
IOI[0]:TFF1_SRVAL 0.F0.B3
IOI[0]:TFF2_SRVAL 0.F0.B5
IOI[0]:TFF_INIT 0.F0.B8
IOI[1]:IFF1_INIT 0.F2.B32
IOI[1]:IFF1_SRVAL 0.F2.B36
IOI[1]:IFF2_INIT 0.F2.B27
IOI[1]:IFF2_SRVAL 0.F2.B23
IOI[1]:INV.ICE 0.F3.B25
IOI[1]:INV.ICLK1 0.F3.B26
IOI[1]:INV.ICLK2 0.F3.B27
IOI[1]:INV.OTCLK1 0.F3.B23
IOI[1]:INV.OTCLK2 0.F3.B24
IOI[1]:INV.REV 0.F3.B28
IOI[1]:INV.TCE 0.F3.B22
IOI[1]:OFF1_SRVAL 0.F1.B36
IOI[1]:OFF2_SRVAL 0.F1.B34
IOI[1]:OFF_INIT 0.F1.B31
IOI[1]:TFF1_SRVAL 0.F0.B36
IOI[1]:TFF2_SRVAL 0.F0.B34
IOI[1]:TFF_INIT 0.F0.B31
IOI[2]:IFF1_INIT 0.F2.B47
IOI[2]:IFF1_SRVAL 0.F2.B43
IOI[2]:IFF2_INIT 0.F2.B52
IOI[2]:IFF2_SRVAL 0.F2.B56
IOI[2]:INV.ICE 0.F3.B54
IOI[2]:INV.ICLK1 0.F3.B53
IOI[2]:INV.ICLK2 0.F3.B52
IOI[2]:INV.OTCLK1 0.F3.B56
IOI[2]:INV.OTCLK2 0.F3.B55
IOI[2]:INV.REV 0.F3.B51
IOI[2]:INV.TCE 0.F3.B57
IOI[2]:OFF1_SRVAL 0.F1.B43
IOI[2]:OFF2_SRVAL 0.F1.B45
IOI[2]:OFF_INIT 0.F1.B48
IOI[2]:TFF1_SRVAL 0.F0.B43
IOI[2]:TFF2_SRVAL 0.F0.B45
IOI[2]:TFF_INIT 0.F0.B48
inverted ~[0]
IOI[0]:IFF_DELAY_ENABLE 0.F3.B1
IOI[0]:IFF_LATCH 0.F2.B11
IOI[0]:IFF_REV_ENABLE 0.F2.B9
IOI[0]:IFF_SR_ENABLE 0.F2.B10
IOI[0]:IFF_SR_SYNC 0.F2.B8
IOI[0]:IFF_TSBYPASS_ENABLE 0.F3.B3
IOI[0]:INV.O1 0.F1.B12
IOI[0]:INV.O2 0.F1.B11
IOI[0]:INV.T1 0.F0.B12
IOI[0]:INV.T2 0.F0.B11
IOI[0]:I_DELAY_ENABLE 0.F3.B10
IOI[0]:I_TSBYPASS_ENABLE 0.F3.B7
IOI[0]:OFF1_LATCH 0.F1.B17
IOI[0]:OFF2_LATCH 0.F1.B18
IOI[0]:OFF_REV_ENABLE 0.F1.B9
IOI[0]:OFF_SR_ENABLE 0.F1.B10
IOI[0]:OFF_SR_SYNC 0.F1.B13
IOI[0]:READBACK_I 0.F3.B0
IOI[0]:TFF1_LATCH 0.F0.B17
IOI[0]:TFF2_LATCH 0.F0.B18
IOI[0]:TFF_REV_ENABLE 0.F0.B9
IOI[0]:TFF_SR_ENABLE 0.F0.B10
IOI[0]:TFF_SR_SYNC 0.F0.B13
IOI[1]:IFF_DELAY_ENABLE 0.F3.B38
IOI[1]:IFF_LATCH 0.F2.B28
IOI[1]:IFF_REV_ENABLE 0.F2.B30
IOI[1]:IFF_SR_ENABLE 0.F2.B29
IOI[1]:IFF_SR_SYNC 0.F2.B31
IOI[1]:IFF_TSBYPASS_ENABLE 0.F3.B36
IOI[1]:INV.O1 0.F1.B27
IOI[1]:INV.O2 0.F1.B28
IOI[1]:INV.T1 0.F0.B27
IOI[1]:INV.T2 0.F0.B28
IOI[1]:I_DELAY_ENABLE 0.F3.B29
IOI[1]:I_TSBYPASS_ENABLE 0.F3.B32
IOI[1]:OFF1_LATCH 0.F1.B22
IOI[1]:OFF2_LATCH 0.F1.B21
IOI[1]:OFF_REV_ENABLE 0.F1.B30
IOI[1]:OFF_SR_ENABLE 0.F1.B29
IOI[1]:OFF_SR_SYNC 0.F1.B26
IOI[1]:READBACK_I 0.F3.B39
IOI[1]:TFF1_LATCH 0.F0.B22
IOI[1]:TFF2_LATCH 0.F0.B21
IOI[1]:TFF_REV_ENABLE 0.F0.B30
IOI[1]:TFF_SR_ENABLE 0.F0.B29
IOI[1]:TFF_SR_SYNC 0.F0.B26
IOI[2]:IFF_DELAY_ENABLE 0.F3.B41
IOI[2]:IFF_LATCH 0.F2.B51
IOI[2]:IFF_REV_ENABLE 0.F2.B49
IOI[2]:IFF_SR_ENABLE 0.F2.B50
IOI[2]:IFF_SR_SYNC 0.F2.B48
IOI[2]:IFF_TSBYPASS_ENABLE 0.F3.B43
IOI[2]:INV.O1 0.F1.B52
IOI[2]:INV.O2 0.F1.B51
IOI[2]:INV.T1 0.F0.B52
IOI[2]:INV.T2 0.F0.B51
IOI[2]:I_DELAY_ENABLE 0.F3.B50
IOI[2]:I_TSBYPASS_ENABLE 0.F3.B47
IOI[2]:OFF1_LATCH 0.F1.B57
IOI[2]:OFF2_LATCH 0.F1.B58
IOI[2]:OFF_REV_ENABLE 0.F1.B49
IOI[2]:OFF_SR_ENABLE 0.F1.B50
IOI[2]:OFF_SR_SYNC 0.F1.B53
IOI[2]:READBACK_I 0.F3.B40
IOI[2]:TFF1_LATCH 0.F0.B57
IOI[2]:TFF2_LATCH 0.F0.B58
IOI[2]:TFF_REV_ENABLE 0.F0.B49
IOI[2]:TFF_SR_ENABLE 0.F0.B50
IOI[2]:TFF_SR_SYNC 0.F0.B53
non-inverted [0]
IOI[0]:OMUX 0.F1.B15 0.F1.B19 0.F1.B14 0.F1.B16
IOI[1]:OMUX 0.F1.B24 0.F1.B20 0.F1.B25 0.F1.B23
IOI[2]:OMUX 0.F1.B55 0.F1.B59 0.F1.B54 0.F1.B56
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IOI[0]:TMUX 0.F0.B15 0.F0.B19 0.F0.B14 0.F0.B16
IOI[1]:TMUX 0.F0.B24 0.F0.B20 0.F0.B25 0.F0.B23
IOI[2]:TMUX 0.F0.B55 0.F0.B59 0.F0.B54 0.F0.B56
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IOI[0]:TSBYPASS_MUX 0.F3.B4
IOI[1]:TSBYPASS_MUX 0.F3.B35
IOI[2]:TSBYPASS_MUX 0.F3.B44
TMUX 0
GND 1

Tile IOI_FC

Cells: 1

Bel IBUF[0]

spartan3 IOI_FC bel IBUF[0]
PinDirectionWires
CEinputIMUX_DATA[8]
CLKinputIMUX_IOCLK[0]
IoutputOUT_FAN[4]
IQoutputOUT_SEC[8]
REVinputIMUX_DATA[0]
SRinputIMUX_DATA[12]

Bel IBUF[1]

spartan3 IOI_FC bel IBUF[1]
PinDirectionWires
CEinputIMUX_DATA[9]
CLKinputIMUX_IOCLK[2]
IoutputOUT_FAN[5]
IQoutputOUT_SEC[9]
REVinputIMUX_DATA[1]
SRinputIMUX_DATA[13]

Bel IBUF[2]

spartan3 IOI_FC bel IBUF[2]
PinDirectionWires
CEinputIMUX_DATA[10]
CLKinputIMUX_IOCLK[4]
IoutputOUT_FAN[6]
IQoutputOUT_SEC[10]
REVinputIMUX_DATA[2]
SRinputIMUX_DATA[14]

Bel IBUF[3]

spartan3 IOI_FC bel IBUF[3]
PinDirectionWires
CEinputIMUX_DATA[11]
CLKinputIMUX_IOCLK[6]
IoutputOUT_FAN[7]
IQoutputOUT_SEC[11]
REVinputIMUX_DATA[3]
SRinputIMUX_DATA[15]

Bel OBUF[0]

spartan3 IOI_FC bel OBUF[0]
PinDirectionWires
CEinputIMUX_CE[0]
CLKinputIMUX_IOCLK[1]
OinputIMUX_DATA[24]
REVinputIMUX_DATA[4]
SRinputIMUX_SR[0]

Bel OBUF[1]

spartan3 IOI_FC bel OBUF[1]
PinDirectionWires
CEinputIMUX_CE[1]
CLKinputIMUX_IOCLK[3]
OinputIMUX_DATA[25]
REVinputIMUX_DATA[5]
SRinputIMUX_SR[1]

Bel OBUF[2]

spartan3 IOI_FC bel OBUF[2]
PinDirectionWires
CEinputIMUX_CE[2]
CLKinputIMUX_IOCLK[5]
OinputIMUX_DATA[26]
REVinputIMUX_DATA[6]
SRinputIMUX_SR[2]

Bel OBUF[3]

spartan3 IOI_FC bel OBUF[3]
PinDirectionWires
CEinputIMUX_CE[3]
CLKinputIMUX_IOCLK[7]
OinputIMUX_DATA[27]
REVinputIMUX_DATA[7]
SRinputIMUX_SR[3]

Bel wires

spartan3 IOI_FC bel wires
WirePins
IMUX_SR[0]OBUF[0].SR
IMUX_SR[1]OBUF[1].SR
IMUX_SR[2]OBUF[2].SR
IMUX_SR[3]OBUF[3].SR
IMUX_CE[0]OBUF[0].CE
IMUX_CE[1]OBUF[1].CE
IMUX_CE[2]OBUF[2].CE
IMUX_CE[3]OBUF[3].CE
IMUX_IOCLK[0]IBUF[0].CLK
IMUX_IOCLK[1]OBUF[0].CLK
IMUX_IOCLK[2]IBUF[1].CLK
IMUX_IOCLK[3]OBUF[1].CLK
IMUX_IOCLK[4]IBUF[2].CLK
IMUX_IOCLK[5]OBUF[2].CLK
IMUX_IOCLK[6]IBUF[3].CLK
IMUX_IOCLK[7]OBUF[3].CLK
IMUX_DATA[0]IBUF[0].REV
IMUX_DATA[1]IBUF[1].REV
IMUX_DATA[2]IBUF[2].REV
IMUX_DATA[3]IBUF[3].REV
IMUX_DATA[4]OBUF[0].REV
IMUX_DATA[5]OBUF[1].REV
IMUX_DATA[6]OBUF[2].REV
IMUX_DATA[7]OBUF[3].REV
IMUX_DATA[8]IBUF[0].CE
IMUX_DATA[9]IBUF[1].CE
IMUX_DATA[10]IBUF[2].CE
IMUX_DATA[11]IBUF[3].CE
IMUX_DATA[12]IBUF[0].SR
IMUX_DATA[13]IBUF[1].SR
IMUX_DATA[14]IBUF[2].SR
IMUX_DATA[15]IBUF[3].SR
IMUX_DATA[24]OBUF[0].O
IMUX_DATA[25]OBUF[1].O
IMUX_DATA[26]OBUF[2].O
IMUX_DATA[27]OBUF[3].O
OUT_FAN[4]IBUF[0].I
OUT_FAN[5]IBUF[1].I
OUT_FAN[6]IBUF[2].I
OUT_FAN[7]IBUF[3].I
OUT_SEC[8]IBUF[0].IQ
OUT_SEC[9]IBUF[1].IQ
OUT_SEC[10]IBUF[2].IQ
OUT_SEC[11]IBUF[3].IQ

Bitstream

spartan3 IOI_FC rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_FC rect R0
BitFrame
F0 F1 F2 F3
B63 IBUF[3]:DELAY_ENABLE[7] - IBUF[3]:DELAY_ENABLE[12] IBUF[3]:READBACK_I
B62 IBUF[3]:DELAY_ENABLE[6] IBUF[3]:DELAY_ENABLE[9] IBUF[3]:DELAY_ENABLE[11] IBUF[3]:IFF_DELAY_ENABLE
B61 IBUF[3]:DELAY_ENABLE[5] IBUF[3]:DELAY_ENABLE[8] - IBUF[3]:ENABLE_O2IQPATH
B60 IBUF[3]:DELAY_ENABLE[4] - - -
B59 IBUF[3]:DELAY_ENABLE[3] ~OBUF[3]:FF_SRVAL - IBUF[3]:ENABLE_O2I_O2IQ_PATH
B58 IBUF[3]:DELAY_ENABLE[2] OBUF[3]:INV.O IBUF[3]:DELAY_ENABLE[10] IBUF[3]:DELAY_ENABLE[13]
B57 IBUF[3]:DELAY_ENABLE[1] OBUF[3]:OMUX[1] - IBUF[3]:ENABLE_O2IPATH
B56 - ~OBUF[3]:FF_INIT - ~IBUF[3]:INV.REV
B55 IBUF[3]:DELAY_ENABLE[0] OBUF[3]:OMUX[0] IBUF[3]:FF_LATCH IBUF[3]:I_DELAY_ENABLE
B54 - OBUF[3]:FF_REV_ENABLE ~IBUF[3]:FF_INIT ~OBUF[3]:INV.REV
B53 - OBUF[3]:FF_SR_ENABLE IBUF[3]:FF_REV_ENABLE ~IBUF[3]:INV.CLK
B52 - OBUF[3]:FF_SR_SYNC IBUF[3]:FF_SR_ENABLE -
B51 - - ~IBUF[3]:FF_SRVAL ~IBUF[3]:INV.CE
B50 - OBUF[3]:FF_LATCH - ~OBUF[3]:INV.CLK
B49 - - - -
B48 - - IBUF[3]:FF_SR_SYNC ~IBUF[3]:INV.SR
B47 - OBUF[2]:OMUX[1] IBUF[2]:FF_SR_SYNC ~IBUF[2]:INV.SR
B46 - OBUF[2]:FF_LATCH - ~OBUF[2]:INV.CLK
B45 - - - -
B44 - OBUF[2]:OMUX[0] - ~IBUF[2]:INV.CE
B43 - OBUF[2]:FF_SR_SYNC IBUF[2]:FF_SR_ENABLE ~IBUF[2]:INV.CLK
B42 - OBUF[2]:FF_SR_ENABLE IBUF[2]:FF_REV_ENABLE -
B41 - OBUF[2]:FF_REV_ENABLE - ~OBUF[2]:INV.REV
B40 IBUF[2]:DELAY_ENABLE[7] - IBUF[2]:FF_LATCH IBUF[2]:I_DELAY_ENABLE
B39 - ~OBUF[2]:FF_INIT - ~IBUF[2]:INV.REV
B38 IBUF[2]:DELAY_ENABLE[6] - ~IBUF[2]:FF_INIT IBUF[2]:ENABLE_O2IPATH
B37 IBUF[2]:DELAY_ENABLE[5] - IBUF[2]:DELAY_ENABLE[12] IBUF[2]:DELAY_ENABLE[13]
B36 IBUF[2]:DELAY_ENABLE[4] - - IBUF[2]:ENABLE_O2I_O2IQ_PATH
B35 IBUF[2]:DELAY_ENABLE[3] ~OBUF[2]:FF_SRVAL ~IBUF[2]:FF_SRVAL -
B34 IBUF[2]:DELAY_ENABLE[2] IBUF[2]:DELAY_ENABLE[9] - IBUF[2]:ENABLE_O2IQPATH
B33 IBUF[2]:DELAY_ENABLE[1] IBUF[2]:DELAY_ENABLE[8] IBUF[2]:DELAY_ENABLE[11] IBUF[2]:IFF_DELAY_ENABLE
B32 IBUF[2]:DELAY_ENABLE[0] OBUF[2]:INV.O IBUF[2]:DELAY_ENABLE[10] IBUF[2]:READBACK_I
B31 IBUF[1]:DELAY_ENABLE[7] - IBUF[1]:DELAY_ENABLE[12] IBUF[1]:READBACK_I
B30 IBUF[1]:DELAY_ENABLE[6] IBUF[1]:DELAY_ENABLE[9] IBUF[1]:DELAY_ENABLE[11] IBUF[1]:IFF_DELAY_ENABLE
B29 IBUF[1]:DELAY_ENABLE[5] IBUF[1]:DELAY_ENABLE[8] - IBUF[1]:ENABLE_O2IQPATH
B28 IBUF[1]:DELAY_ENABLE[4] - - -
B27 IBUF[1]:DELAY_ENABLE[3] ~OBUF[1]:FF_SRVAL - IBUF[1]:ENABLE_O2I_O2IQ_PATH
B26 IBUF[1]:DELAY_ENABLE[2] OBUF[1]:INV.O IBUF[1]:DELAY_ENABLE[10] IBUF[1]:DELAY_ENABLE[13]
B25 IBUF[1]:DELAY_ENABLE[1] OBUF[1]:OMUX[1] - IBUF[1]:ENABLE_O2IPATH
B24 - ~OBUF[1]:FF_INIT - ~IBUF[1]:INV.REV
B23 IBUF[1]:DELAY_ENABLE[0] OBUF[1]:OMUX[0] IBUF[1]:FF_LATCH IBUF[1]:I_DELAY_ENABLE
B22 - OBUF[1]:FF_REV_ENABLE ~IBUF[1]:FF_INIT ~OBUF[1]:INV.REV
B21 - OBUF[1]:FF_SR_ENABLE IBUF[1]:FF_REV_ENABLE ~IBUF[1]:INV.CLK
B20 - OBUF[1]:FF_SR_SYNC IBUF[1]:FF_SR_ENABLE -
B19 - - ~IBUF[1]:FF_SRVAL ~IBUF[1]:INV.CE
B18 - OBUF[1]:FF_LATCH - ~OBUF[1]:INV.CLK
B17 - - - -
B16 - - IBUF[1]:FF_SR_SYNC ~IBUF[1]:INV.SR
B15 - OBUF[0]:OMUX[1] IBUF[0]:FF_SR_SYNC ~IBUF[0]:INV.SR
B14 - OBUF[0]:FF_LATCH - ~OBUF[0]:INV.CLK
B13 - - - -
B12 - OBUF[0]:OMUX[0] - ~IBUF[0]:INV.CE
B11 - OBUF[0]:FF_SR_SYNC IBUF[0]:FF_SR_ENABLE ~IBUF[0]:INV.CLK
B10 - OBUF[0]:FF_SR_ENABLE IBUF[0]:FF_REV_ENABLE -
B9 - OBUF[0]:FF_REV_ENABLE - ~OBUF[0]:INV.REV
B8 IBUF[0]:DELAY_ENABLE[7] - IBUF[0]:FF_LATCH IBUF[0]:I_DELAY_ENABLE
B7 - ~OBUF[0]:FF_INIT - ~IBUF[0]:INV.REV
B6 IBUF[0]:DELAY_ENABLE[6] - ~IBUF[0]:FF_INIT IBUF[0]:ENABLE_O2IPATH
B5 IBUF[0]:DELAY_ENABLE[5] - IBUF[0]:DELAY_ENABLE[12] IBUF[0]:DELAY_ENABLE[13]
B4 IBUF[0]:DELAY_ENABLE[4] - - IBUF[0]:ENABLE_O2I_O2IQ_PATH
B3 IBUF[0]:DELAY_ENABLE[3] ~OBUF[0]:FF_SRVAL ~IBUF[0]:FF_SRVAL -
B2 IBUF[0]:DELAY_ENABLE[2] IBUF[0]:DELAY_ENABLE[9] - IBUF[0]:ENABLE_O2IQPATH
B1 IBUF[0]:DELAY_ENABLE[1] IBUF[0]:DELAY_ENABLE[8] IBUF[0]:DELAY_ENABLE[11] IBUF[0]:IFF_DELAY_ENABLE
B0 IBUF[0]:DELAY_ENABLE[0] OBUF[0]:INV.O IBUF[0]:DELAY_ENABLE[10] IBUF[0]:READBACK_I
IBUF[0]:DELAY_ENABLE 0.F3.B5 0.F2.B5 0.F2.B1 0.F2.B0 0.F1.B2 0.F1.B1 0.F0.B8 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
IBUF[1]:DELAY_ENABLE 0.F3.B26 0.F2.B31 0.F2.B30 0.F2.B26 0.F1.B30 0.F1.B29 0.F0.B31 0.F0.B30 0.F0.B29 0.F0.B28 0.F0.B27 0.F0.B26 0.F0.B25 0.F0.B23
IBUF[2]:DELAY_ENABLE 0.F3.B37 0.F2.B37 0.F2.B33 0.F2.B32 0.F1.B34 0.F1.B33 0.F0.B40 0.F0.B38 0.F0.B37 0.F0.B36 0.F0.B35 0.F0.B34 0.F0.B33 0.F0.B32
IBUF[3]:DELAY_ENABLE 0.F3.B58 0.F2.B63 0.F2.B62 0.F2.B58 0.F1.B62 0.F1.B61 0.F0.B63 0.F0.B62 0.F0.B61 0.F0.B60 0.F0.B59 0.F0.B58 0.F0.B57 0.F0.B55
non-inverted [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
IBUF[0]:ENABLE_O2IPATH 0.F3.B6
IBUF[0]:ENABLE_O2IQPATH 0.F3.B2
IBUF[0]:ENABLE_O2I_O2IQ_PATH 0.F3.B4
IBUF[0]:FF_LATCH 0.F2.B8
IBUF[0]:FF_REV_ENABLE 0.F2.B10
IBUF[0]:FF_SR_ENABLE 0.F2.B11
IBUF[0]:FF_SR_SYNC 0.F2.B15
IBUF[0]:IFF_DELAY_ENABLE 0.F3.B1
IBUF[0]:I_DELAY_ENABLE 0.F3.B8
IBUF[0]:READBACK_I 0.F3.B0
IBUF[1]:ENABLE_O2IPATH 0.F3.B25
IBUF[1]:ENABLE_O2IQPATH 0.F3.B29
IBUF[1]:ENABLE_O2I_O2IQ_PATH 0.F3.B27
IBUF[1]:FF_LATCH 0.F2.B23
IBUF[1]:FF_REV_ENABLE 0.F2.B21
IBUF[1]:FF_SR_ENABLE 0.F2.B20
IBUF[1]:FF_SR_SYNC 0.F2.B16
IBUF[1]:IFF_DELAY_ENABLE 0.F3.B30
IBUF[1]:I_DELAY_ENABLE 0.F3.B23
IBUF[1]:READBACK_I 0.F3.B31
IBUF[2]:ENABLE_O2IPATH 0.F3.B38
IBUF[2]:ENABLE_O2IQPATH 0.F3.B34
IBUF[2]:ENABLE_O2I_O2IQ_PATH 0.F3.B36
IBUF[2]:FF_LATCH 0.F2.B40
IBUF[2]:FF_REV_ENABLE 0.F2.B42
IBUF[2]:FF_SR_ENABLE 0.F2.B43
IBUF[2]:FF_SR_SYNC 0.F2.B47
IBUF[2]:IFF_DELAY_ENABLE 0.F3.B33
IBUF[2]:I_DELAY_ENABLE 0.F3.B40
IBUF[2]:READBACK_I 0.F3.B32
IBUF[3]:ENABLE_O2IPATH 0.F3.B57
IBUF[3]:ENABLE_O2IQPATH 0.F3.B61
IBUF[3]:ENABLE_O2I_O2IQ_PATH 0.F3.B59
IBUF[3]:FF_LATCH 0.F2.B55
IBUF[3]:FF_REV_ENABLE 0.F2.B53
IBUF[3]:FF_SR_ENABLE 0.F2.B52
IBUF[3]:FF_SR_SYNC 0.F2.B48
IBUF[3]:IFF_DELAY_ENABLE 0.F3.B62
IBUF[3]:I_DELAY_ENABLE 0.F3.B55
IBUF[3]:READBACK_I 0.F3.B63
OBUF[0]:FF_LATCH 0.F1.B14
OBUF[0]:FF_REV_ENABLE 0.F1.B9
OBUF[0]:FF_SR_ENABLE 0.F1.B10
OBUF[0]:FF_SR_SYNC 0.F1.B11
OBUF[0]:INV.O 0.F1.B0
OBUF[1]:FF_LATCH 0.F1.B18
OBUF[1]:FF_REV_ENABLE 0.F1.B22
OBUF[1]:FF_SR_ENABLE 0.F1.B21
OBUF[1]:FF_SR_SYNC 0.F1.B20
OBUF[1]:INV.O 0.F1.B26
OBUF[2]:FF_LATCH 0.F1.B46
OBUF[2]:FF_REV_ENABLE 0.F1.B41
OBUF[2]:FF_SR_ENABLE 0.F1.B42
OBUF[2]:FF_SR_SYNC 0.F1.B43
OBUF[2]:INV.O 0.F1.B32
OBUF[3]:FF_LATCH 0.F1.B50
OBUF[3]:FF_REV_ENABLE 0.F1.B54
OBUF[3]:FF_SR_ENABLE 0.F1.B53
OBUF[3]:FF_SR_SYNC 0.F1.B52
OBUF[3]:INV.O 0.F1.B58
non-inverted [0]
IBUF[0]:FF_INIT 0.F2.B6
IBUF[0]:FF_SRVAL 0.F2.B3
IBUF[0]:INV.CE 0.F3.B12
IBUF[0]:INV.CLK 0.F3.B11
IBUF[0]:INV.REV 0.F3.B7
IBUF[0]:INV.SR 0.F3.B15
IBUF[1]:FF_INIT 0.F2.B22
IBUF[1]:FF_SRVAL 0.F2.B19
IBUF[1]:INV.CE 0.F3.B19
IBUF[1]:INV.CLK 0.F3.B21
IBUF[1]:INV.REV 0.F3.B24
IBUF[1]:INV.SR 0.F3.B16
IBUF[2]:FF_INIT 0.F2.B38
IBUF[2]:FF_SRVAL 0.F2.B35
IBUF[2]:INV.CE 0.F3.B44
IBUF[2]:INV.CLK 0.F3.B43
IBUF[2]:INV.REV 0.F3.B39
IBUF[2]:INV.SR 0.F3.B47
IBUF[3]:FF_INIT 0.F2.B54
IBUF[3]:FF_SRVAL 0.F2.B51
IBUF[3]:INV.CE 0.F3.B51
IBUF[3]:INV.CLK 0.F3.B53
IBUF[3]:INV.REV 0.F3.B56
IBUF[3]:INV.SR 0.F3.B48
OBUF[0]:FF_INIT 0.F1.B7
OBUF[0]:FF_SRVAL 0.F1.B3
OBUF[0]:INV.CLK 0.F3.B14
OBUF[0]:INV.REV 0.F3.B9
OBUF[1]:FF_INIT 0.F1.B24
OBUF[1]:FF_SRVAL 0.F1.B27
OBUF[1]:INV.CLK 0.F3.B18
OBUF[1]:INV.REV 0.F3.B22
OBUF[2]:FF_INIT 0.F1.B39
OBUF[2]:FF_SRVAL 0.F1.B35
OBUF[2]:INV.CLK 0.F3.B46
OBUF[2]:INV.REV 0.F3.B41
OBUF[3]:FF_INIT 0.F1.B56
OBUF[3]:FF_SRVAL 0.F1.B59
OBUF[3]:INV.CLK 0.F3.B50
OBUF[3]:INV.REV 0.F3.B54
inverted ~[0]
OBUF[0]:OMUX 0.F1.B15 0.F1.B12
OBUF[1]:OMUX 0.F1.B25 0.F1.B23
OBUF[2]:OMUX 0.F1.B47 0.F1.B44
OBUF[3]:OMUX 0.F1.B57 0.F1.B55
NONE 0 0
O 0 1
OFF 1 0

Tile IOI_S3E

Cells: 1

Bel IOI[0]

spartan3 IOI_S3E bel IOI[0]
PinDirectionWires
IoutputOUT_FAN[4]
ICEinputIMUX_DATA[8]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[8]
IQ2outputOUT_SEC[12]
O1inputIMUX_DATA[24]
O2inputIMUX_DATA[28]
OCEinputIMUX_CE[0]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[0]
SRinputIMUX_SR[0]
ToutputOUT_FAN[0]
T1inputIMUX_DATA[16]
T2inputIMUX_DATA[20]
TCEinputIMUX_DATA[4]

Bel IOI[1]

spartan3 IOI_S3E bel IOI[1]
PinDirectionWires
IoutputOUT_FAN[5]
ICEinputIMUX_DATA[9]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[9]
IQ2outputOUT_SEC[13]
O1inputIMUX_DATA[25]
O2inputIMUX_DATA[29]
OCEinputIMUX_CE[1]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[1]
SRinputIMUX_SR[1]
ToutputOUT_FAN[1]
T1inputIMUX_DATA[17]
T2inputIMUX_DATA[21]
TCEinputIMUX_DATA[5]

Bel IOI[2]

spartan3 IOI_S3E bel IOI[2]
PinDirectionWires
IoutputOUT_FAN[6]
ICEinputIMUX_DATA[10]
ICLK1inputIMUX_IOCLK[2]
ICLK2inputIMUX_IOCLK[6]
IQ1outputOUT_SEC[10]
IQ2outputOUT_SEC[14]
O1inputIMUX_DATA[26]
O2inputIMUX_DATA[30]
OCEinputIMUX_CE[2]
OTCLK1inputIMUX_IOCLK[3]
OTCLK2inputIMUX_IOCLK[7]
REVinputIMUX_DATA[2]
SRinputIMUX_SR[2]
ToutputOUT_FAN[2]
T1inputIMUX_DATA[18]
T2inputIMUX_DATA[22]
TCEinputIMUX_DATA[6]

Bel wires

spartan3 IOI_S3E bel wires
WirePins
IMUX_SR[0]IOI[0].SR
IMUX_SR[1]IOI[1].SR
IMUX_SR[2]IOI[2].SR
IMUX_CE[0]IOI[0].OCE
IMUX_CE[1]IOI[1].OCE
IMUX_CE[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3E rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_S3E rect R0
BitFrame
F0 F1 F2 F3
B59 IOI[2]:TMUX[2] IOI[2]:OMUX[2] - -
B58 IOI[2]:TFF2_LATCH IOI[2]:OFF2_LATCH - IOI[2]:IDDRIN_MUX[2]
B57 IOI[2]:TFF1_LATCH IOI[2]:OFF1_LATCH - ~IOI[2]:INV.TCE
B56 IOI[2]:TMUX[0] IOI[2]:OMUX[0] ~IOI[2]:IFF2_SRVAL ~IOI[2]:INV.OTCLK1
B55 IOI[2]:TMUX[3] IOI[2]:OMUX[3] - ~IOI[2]:INV.OTCLK2
B54 IOI[2]:TMUX[1] IOI[2]:OMUX[1] - ~IOI[2]:INV.ICE
B53 IOI[2]:TFF_SR_SYNC IOI[2]:OFF_SR_SYNC - ~IOI[2]:INV.ICLK1
B52 IOI[2]:INV.T1 IOI[2]:INV.O1 ~IOI[2]:IFF2_INIT ~IOI[2]:INV.ICLK2
B51 IOI[2]:INV.T2 IOI[2]:INV.O2 IOI[2]:IFF_LATCH ~IOI[2]:INV.REV
B50 IOI[2]:TFF_SR_ENABLE IOI[2]:OFF_SR_ENABLE IOI[2]:IFF_SR_ENABLE IOI[2]:I_DELAY_ENABLE
B49 IOI[2]:TFF_REV_ENABLE IOI[2]:OFF_REV_ENABLE IOI[2]:IFF_REV_ENABLE -
B48 ~IOI[2]:TFF_INIT ~IOI[2]:OFF_INIT IOI[2]:IFF_SR_SYNC IOI[2]:IDDRIN_MUX[0]
B47 IOI[2]:MISR_RESET - ~IOI[2]:IFF1_INIT IOI[2]:I_TSBYPASS_ENABLE
B46 IOI[2]:MISR_ENABLE - - -
B45 ~IOI[2]:TFF2_SRVAL ~IOI[2]:OFF2_SRVAL - -
B44 - - - IOI[2]:TSBYPASS_MUX[0]
B43 ~IOI[2]:TFF1_SRVAL ~IOI[2]:OFF1_SRVAL ~IOI[2]:IFF1_SRVAL IOI[2]:IFF_TSBYPASS_ENABLE
B42 - - - IOI[2]:IDDRIN_MUX[1]
B41 IOI[2]:MISR_CLOCK[1] - - IOI[2]:IFF_DELAY_ENABLE
B40 IOI[2]:MISR_CLOCK[0] IOI[2]:PCICE_MUX[0] IOI[2]:PCICE_MUX[1] IOI[2]:READBACK_I
B39 IOI[1]:MISR_CLOCK[0] IOI[1]:PCICE_MUX[0] IOI[1]:PCICE_MUX[1] IOI[1]:READBACK_I
B38 IOI[1]:MISR_CLOCK[1] - - IOI[1]:IFF_DELAY_ENABLE
B37 IOI[0]:O2_DDRMUX[0] - - IOI[0]:IDDRIN_MUX[1]
B36 ~IOI[1]:TFF1_SRVAL ~IOI[1]:OFF1_SRVAL ~IOI[1]:IFF1_SRVAL IOI[1]:IFF_TSBYPASS_ENABLE
B35 - IOI[0]:O1_DDRMUX[0] - IOI[1]:TSBYPASS_MUX[0]
B34 ~IOI[1]:TFF2_SRVAL ~IOI[1]:OFF2_SRVAL - -
B33 IOI[1]:MISR_ENABLE - - -
B32 IOI[1]:MISR_RESET - ~IOI[1]:IFF1_INIT IOI[1]:I_TSBYPASS_ENABLE
B31 ~IOI[1]:TFF_INIT ~IOI[1]:OFF_INIT IOI[1]:IFF_SR_SYNC -
B30 IOI[1]:TFF_REV_ENABLE IOI[1]:OFF_REV_ENABLE IOI[1]:IFF_REV_ENABLE IOI[1]:IDDRIN_MUX[0]
B29 IOI[1]:TFF_SR_ENABLE IOI[1]:OFF_SR_ENABLE IOI[1]:IFF_SR_ENABLE IOI[1]:I_DELAY_ENABLE
B28 IOI[1]:INV.T2 IOI[1]:INV.O2 IOI[1]:IFF_LATCH ~IOI[1]:INV.REV
B27 IOI[1]:INV.T1 IOI[1]:INV.O1 ~IOI[1]:IFF2_INIT ~IOI[1]:INV.ICLK2
B26 IOI[1]:TFF_SR_SYNC IOI[1]:OFF_SR_SYNC - ~IOI[1]:INV.ICLK1
B25 IOI[1]:TMUX[1] IOI[1]:OMUX[1] - ~IOI[1]:INV.ICE
B24 IOI[1]:TMUX[3] IOI[1]:OMUX[3] - ~IOI[1]:INV.OTCLK2
B23 IOI[1]:TMUX[0] IOI[1]:OMUX[0] ~IOI[1]:IFF2_SRVAL ~IOI[1]:INV.OTCLK1
B22 IOI[1]:TFF1_LATCH IOI[1]:OFF1_LATCH - ~IOI[1]:INV.TCE
B21 IOI[1]:TFF2_LATCH IOI[1]:OFF2_LATCH - IOI[0]:IDDRIN_MUX[2]
B20 IOI[1]:TMUX[2] IOI[1]:OMUX[2] - -
B19 IOI[0]:TMUX[2] IOI[0]:OMUX[2] - -
B18 IOI[0]:TFF2_LATCH IOI[0]:OFF2_LATCH - IOI[1]:IDDRIN_MUX[2]
B17 IOI[0]:TFF1_LATCH IOI[0]:OFF1_LATCH - ~IOI[0]:INV.TCE
B16 IOI[0]:TMUX[0] IOI[0]:OMUX[0] ~IOI[0]:IFF2_SRVAL ~IOI[0]:INV.OTCLK1
B15 IOI[0]:TMUX[3] IOI[0]:OMUX[3] - ~IOI[0]:INV.OTCLK2
B14 IOI[0]:TMUX[1] IOI[0]:OMUX[1] - ~IOI[0]:INV.ICE
B13 IOI[0]:TFF_SR_SYNC IOI[0]:OFF_SR_SYNC - ~IOI[0]:INV.ICLK1
B12 IOI[0]:INV.T1 IOI[0]:INV.O1 ~IOI[0]:IFF2_INIT ~IOI[0]:INV.ICLK2
B11 IOI[0]:INV.T2 IOI[0]:INV.O2 IOI[0]:IFF_LATCH ~IOI[0]:INV.REV
B10 IOI[0]:TFF_SR_ENABLE IOI[0]:OFF_SR_ENABLE IOI[0]:IFF_SR_ENABLE IOI[0]:I_DELAY_ENABLE
B9 IOI[0]:TFF_REV_ENABLE IOI[0]:OFF_REV_ENABLE IOI[0]:IFF_REV_ENABLE -
B8 ~IOI[0]:TFF_INIT ~IOI[0]:OFF_INIT IOI[0]:IFF_SR_SYNC IOI[0]:IDDRIN_MUX[0]
B7 IOI[0]:MISR_RESET - ~IOI[0]:IFF1_INIT IOI[0]:I_TSBYPASS_ENABLE
B6 IOI[0]:MISR_ENABLE - - -
B5 ~IOI[0]:TFF2_SRVAL ~IOI[0]:OFF2_SRVAL - -
B4 - IOI[1]:O1_DDRMUX[0] - IOI[0]:TSBYPASS_MUX[0]
B3 ~IOI[0]:TFF1_SRVAL ~IOI[0]:OFF1_SRVAL ~IOI[0]:IFF1_SRVAL IOI[0]:IFF_TSBYPASS_ENABLE
B2 IOI[1]:O2_DDRMUX[0] - - IOI[1]:IDDRIN_MUX[1]
B1 IOI[0]:MISR_CLOCK[1] - - IOI[0]:IFF_DELAY_ENABLE
B0 IOI[0]:MISR_CLOCK[0] IOI[0]:PCICE_MUX[0] IOI[0]:PCICE_MUX[1] IOI[0]:READBACK_I
IOI[0]:IDDRIN_MUX 0.F3.B21 0.F3.B37 0.F3.B8
IOI[1]:IDDRIN_MUX 0.F3.B18 0.F3.B2 0.F3.B30
IOI[2]:IDDRIN_MUX 0.F3.B58 0.F3.B42 0.F3.B48
NONE 0 0 0
IFFDMUX 0 0 1
IDDRIN1 0 1 0
IDDRIN2 1 0 0
IOI[0]:IFF1_INIT 0.F2.B7
IOI[0]:IFF1_SRVAL 0.F2.B3
IOI[0]:IFF2_INIT 0.F2.B12
IOI[0]:IFF2_SRVAL 0.F2.B16
IOI[0]:INV.ICE 0.F3.B14
IOI[0]:INV.ICLK1 0.F3.B13
IOI[0]:INV.ICLK2 0.F3.B12
IOI[0]:INV.OTCLK1 0.F3.B16
IOI[0]:INV.OTCLK2 0.F3.B15
IOI[0]:INV.REV 0.F3.B11
IOI[0]:INV.TCE 0.F3.B17
IOI[0]:OFF1_SRVAL 0.F1.B3
IOI[0]:OFF2_SRVAL 0.F1.B5
IOI[0]:OFF_INIT 0.F1.B8
IOI[0]:TFF1_SRVAL 0.F0.B3
IOI[0]:TFF2_SRVAL 0.F0.B5
IOI[0]:TFF_INIT 0.F0.B8
IOI[1]:IFF1_INIT 0.F2.B32
IOI[1]:IFF1_SRVAL 0.F2.B36
IOI[1]:IFF2_INIT 0.F2.B27
IOI[1]:IFF2_SRVAL 0.F2.B23
IOI[1]:INV.ICE 0.F3.B25
IOI[1]:INV.ICLK1 0.F3.B26
IOI[1]:INV.ICLK2 0.F3.B27
IOI[1]:INV.OTCLK1 0.F3.B23
IOI[1]:INV.OTCLK2 0.F3.B24
IOI[1]:INV.REV 0.F3.B28
IOI[1]:INV.TCE 0.F3.B22
IOI[1]:OFF1_SRVAL 0.F1.B36
IOI[1]:OFF2_SRVAL 0.F1.B34
IOI[1]:OFF_INIT 0.F1.B31
IOI[1]:TFF1_SRVAL 0.F0.B36
IOI[1]:TFF2_SRVAL 0.F0.B34
IOI[1]:TFF_INIT 0.F0.B31
IOI[2]:IFF1_INIT 0.F2.B47
IOI[2]:IFF1_SRVAL 0.F2.B43
IOI[2]:IFF2_INIT 0.F2.B52
IOI[2]:IFF2_SRVAL 0.F2.B56
IOI[2]:INV.ICE 0.F3.B54
IOI[2]:INV.ICLK1 0.F3.B53
IOI[2]:INV.ICLK2 0.F3.B52
IOI[2]:INV.OTCLK1 0.F3.B56
IOI[2]:INV.OTCLK2 0.F3.B55
IOI[2]:INV.REV 0.F3.B51
IOI[2]:INV.TCE 0.F3.B57
IOI[2]:OFF1_SRVAL 0.F1.B43
IOI[2]:OFF2_SRVAL 0.F1.B45
IOI[2]:OFF_INIT 0.F1.B48
IOI[2]:TFF1_SRVAL 0.F0.B43
IOI[2]:TFF2_SRVAL 0.F0.B45
IOI[2]:TFF_INIT 0.F0.B48
inverted ~[0]
IOI[0]:IFF_DELAY_ENABLE 0.F3.B1
IOI[0]:IFF_LATCH 0.F2.B11
IOI[0]:IFF_REV_ENABLE 0.F2.B9
IOI[0]:IFF_SR_ENABLE 0.F2.B10
IOI[0]:IFF_SR_SYNC 0.F2.B8
IOI[0]:IFF_TSBYPASS_ENABLE 0.F3.B3
IOI[0]:INV.O1 0.F1.B12
IOI[0]:INV.O2 0.F1.B11
IOI[0]:INV.T1 0.F0.B12
IOI[0]:INV.T2 0.F0.B11
IOI[0]:I_DELAY_ENABLE 0.F3.B10
IOI[0]:I_TSBYPASS_ENABLE 0.F3.B7
IOI[0]:MISR_ENABLE 0.F0.B6
IOI[0]:MISR_RESET 0.F0.B7
IOI[0]:OFF1_LATCH 0.F1.B17
IOI[0]:OFF2_LATCH 0.F1.B18
IOI[0]:OFF_REV_ENABLE 0.F1.B9
IOI[0]:OFF_SR_ENABLE 0.F1.B10
IOI[0]:OFF_SR_SYNC 0.F1.B13
IOI[0]:READBACK_I 0.F3.B0
IOI[0]:TFF1_LATCH 0.F0.B17
IOI[0]:TFF2_LATCH 0.F0.B18
IOI[0]:TFF_REV_ENABLE 0.F0.B9
IOI[0]:TFF_SR_ENABLE 0.F0.B10
IOI[0]:TFF_SR_SYNC 0.F0.B13
IOI[1]:IFF_DELAY_ENABLE 0.F3.B38
IOI[1]:IFF_LATCH 0.F2.B28
IOI[1]:IFF_REV_ENABLE 0.F2.B30
IOI[1]:IFF_SR_ENABLE 0.F2.B29
IOI[1]:IFF_SR_SYNC 0.F2.B31
IOI[1]:IFF_TSBYPASS_ENABLE 0.F3.B36
IOI[1]:INV.O1 0.F1.B27
IOI[1]:INV.O2 0.F1.B28
IOI[1]:INV.T1 0.F0.B27
IOI[1]:INV.T2 0.F0.B28
IOI[1]:I_DELAY_ENABLE 0.F3.B29
IOI[1]:I_TSBYPASS_ENABLE 0.F3.B32
IOI[1]:MISR_ENABLE 0.F0.B33
IOI[1]:MISR_RESET 0.F0.B32
IOI[1]:OFF1_LATCH 0.F1.B22
IOI[1]:OFF2_LATCH 0.F1.B21
IOI[1]:OFF_REV_ENABLE 0.F1.B30
IOI[1]:OFF_SR_ENABLE 0.F1.B29
IOI[1]:OFF_SR_SYNC 0.F1.B26
IOI[1]:READBACK_I 0.F3.B39
IOI[1]:TFF1_LATCH 0.F0.B22
IOI[1]:TFF2_LATCH 0.F0.B21
IOI[1]:TFF_REV_ENABLE 0.F0.B30
IOI[1]:TFF_SR_ENABLE 0.F0.B29
IOI[1]:TFF_SR_SYNC 0.F0.B26
IOI[2]:IFF_DELAY_ENABLE 0.F3.B41
IOI[2]:IFF_LATCH 0.F2.B51
IOI[2]:IFF_REV_ENABLE 0.F2.B49
IOI[2]:IFF_SR_ENABLE 0.F2.B50
IOI[2]:IFF_SR_SYNC 0.F2.B48
IOI[2]:IFF_TSBYPASS_ENABLE 0.F3.B43
IOI[2]:INV.O1 0.F1.B52
IOI[2]:INV.O2 0.F1.B51
IOI[2]:INV.T1 0.F0.B52
IOI[2]:INV.T2 0.F0.B51
IOI[2]:I_DELAY_ENABLE 0.F3.B50
IOI[2]:I_TSBYPASS_ENABLE 0.F3.B47
IOI[2]:MISR_ENABLE 0.F0.B46
IOI[2]:MISR_RESET 0.F0.B47
IOI[2]:OFF1_LATCH 0.F1.B57
IOI[2]:OFF2_LATCH 0.F1.B58
IOI[2]:OFF_REV_ENABLE 0.F1.B49
IOI[2]:OFF_SR_ENABLE 0.F1.B50
IOI[2]:OFF_SR_SYNC 0.F1.B53
IOI[2]:READBACK_I 0.F3.B40
IOI[2]:TFF1_LATCH 0.F0.B57
IOI[2]:TFF2_LATCH 0.F0.B58
IOI[2]:TFF_REV_ENABLE 0.F0.B49
IOI[2]:TFF_SR_ENABLE 0.F0.B50
IOI[2]:TFF_SR_SYNC 0.F0.B53
non-inverted [0]
IOI[0]:MISR_CLOCK 0.F0.B1 0.F0.B0
IOI[1]:MISR_CLOCK 0.F0.B38 0.F0.B39
IOI[2]:MISR_CLOCK 0.F0.B41 0.F0.B40
NONE 0 0
OTCLK1 0 1
OTCLK2 1 0
IOI[0]:O1_DDRMUX 0.F1.B35
IOI[1]:O1_DDRMUX 0.F1.B4
O1 0
ODDRIN1 1
IOI[0]:O2_DDRMUX 0.F0.B37
IOI[1]:O2_DDRMUX 0.F0.B2
O2 0
ODDRIN2 1
IOI[0]:OMUX 0.F1.B15 0.F1.B19 0.F1.B14 0.F1.B16
IOI[1]:OMUX 0.F1.B24 0.F1.B20 0.F1.B25 0.F1.B23
IOI[2]:OMUX 0.F1.B55 0.F1.B59 0.F1.B54 0.F1.B56
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IOI[0]:PCICE_MUX 0.F2.B0 0.F1.B0
IOI[1]:PCICE_MUX 0.F2.B39 0.F1.B39
IOI[2]:PCICE_MUX 0.F2.B40 0.F1.B40
NONE 0 0
OCE 0 1
PCICE 1 0
IOI[0]:TMUX 0.F0.B15 0.F0.B19 0.F0.B14 0.F0.B16
IOI[1]:TMUX 0.F0.B24 0.F0.B20 0.F0.B25 0.F0.B23
IOI[2]:TMUX 0.F0.B55 0.F0.B59 0.F0.B54 0.F0.B56
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IOI[0]:TSBYPASS_MUX 0.F3.B4
IOI[1]:TSBYPASS_MUX 0.F3.B35
IOI[2]:TSBYPASS_MUX 0.F3.B44
TMUX 0
GND 1

Tile IOI_S3A_WE

Cells: 1

Bel IOI[0]

spartan3 IOI_S3A_WE bel IOI[0]
PinDirectionWires
IoutputOUT_FAN[4]
ICEinputIMUX_DATA[8]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[8]
IQ2outputOUT_SEC[12]
O1inputIMUX_DATA[24]
O2inputIMUX_DATA[28]
OCEinputIMUX_CE[0]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[0]
S1inputIMUX_DATA[26]
S2inputIMUX_DATA[30]
S3inputIMUX_DATA[18]
SRinputIMUX_SR[0]
ToutputOUT_FAN[0]
T1inputIMUX_DATA[16]
T2inputIMUX_DATA[20]
TCEinputIMUX_DATA[4]

Bel IOI[1]

spartan3 IOI_S3A_WE bel IOI[1]
PinDirectionWires
IoutputOUT_FAN[5]
ICEinputIMUX_DATA[9]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[9]
IQ2outputOUT_SEC[13]
O1inputIMUX_DATA[25]
O2inputIMUX_DATA[29]
OCEinputIMUX_CE[1]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[1]
S1inputIMUX_DATA[22]
S2inputIMUX_DATA[10]
S3inputIMUX_DATA[2]
SRinputIMUX_SR[1]
ToutputOUT_FAN[1]
T1inputIMUX_DATA[17]
T2inputIMUX_DATA[21]
TCEinputIMUX_DATA[5]

Bel wires

spartan3 IOI_S3A_WE bel wires
WirePins
IMUX_SR[0]IOI[0].SR
IMUX_SR[1]IOI[1].SR
IMUX_CE[0]IOI[0].OCE
IMUX_CE[1]IOI[1].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[1].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[1].S2
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[0].S3
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[1].S1
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[0].S1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[0].S2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2

Bitstream

spartan3 IOI_S3A_WE rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_S3A_WE rect R0
BitFrame
F0 F1 F2 F3
B58 - - - ~IOI[1]:IFF_DELAY[1]
B57 - - - IOI[1]:DELAY_VARIABLE
B56 - - - ~IOI[1]:I_DELAY[2]
B55 - - - ~IOI[1]:I_DELAY[1]
B54 - - - ~IOI[1]:I_DELAY[0]
B53 - - - ~IOI[0]:IFF_DELAY[1]
B52 - - - ~IOI[0]:I_DELAY[0]
B51 - - - ~IOI[0]:IFF_DELAY[0]
B50 - - - ~IOI[0]:I_DELAY[2]
B49 - - - ~IOI[0]:I_DELAY[1]
B48 - - - IOI[0]:DELAY_VARIABLE
B47 - - - ~IOI[1]:IFF_DELAY[0]
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - ~IOI[1]:DELAY_COMMON
B41 - - - ~IOI[0]:DELAY_COMMON
B40 - - - -
B39 IOI[1]:MISR_CLOCK[0] IOI[1]:PCICE_MUX[0] IOI[1]:PCICE_MUX[1] IOI[1]:READBACK_I
B38 IOI[1]:MISR_CLOCK[1] - - IOI[1]:IFF_DELAY_ENABLE
B37 IOI[0]:O2_DDRMUX[0] - - IOI[0]:IDDRIN_MUX[1]
B36 ~IOI[1]:TFF1_SRVAL ~IOI[1]:OFF1_SRVAL ~IOI[1]:IFF1_SRVAL IOI[1]:IFF_TSBYPASS_ENABLE
B35 - IOI[0]:O1_DDRMUX[0] - IOI[1]:TSBYPASS_MUX[0]
B34 ~IOI[1]:TFF2_SRVAL ~IOI[1]:OFF2_SRVAL - -
B33 IOI[1]:MISR_ENABLE - - -
B32 IOI[1]:MISR_RESET - ~IOI[1]:IFF1_INIT IOI[1]:I_TSBYPASS_ENABLE
B31 ~IOI[1]:TFF_INIT ~IOI[1]:OFF_INIT IOI[1]:IFF_SR_SYNC -
B30 IOI[1]:TFF_REV_ENABLE IOI[1]:OFF_REV_ENABLE IOI[1]:IFF_REV_ENABLE IOI[1]:IDDRIN_MUX[0]
B29 IOI[1]:TFF_SR_ENABLE IOI[1]:OFF_SR_ENABLE IOI[1]:IFF_SR_ENABLE IOI[1]:I_DELAY_ENABLE
B28 IOI[1]:INV.T2 IOI[1]:INV.O2 IOI[1]:IFF_LATCH ~IOI[1]:INV.REV
B27 IOI[1]:INV.T1 IOI[1]:INV.O1 ~IOI[1]:IFF2_INIT ~IOI[1]:INV.ICLK2
B26 IOI[1]:TFF_SR_SYNC IOI[1]:OFF_SR_SYNC - ~IOI[1]:INV.ICLK1
B25 IOI[1]:TMUX[1] IOI[1]:OMUX[1] - ~IOI[1]:INV.ICE
B24 IOI[1]:TMUX[3] IOI[1]:OMUX[3] - ~IOI[1]:INV.OTCLK2
B23 IOI[1]:TMUX[0] IOI[1]:OMUX[0] ~IOI[1]:IFF2_SRVAL ~IOI[1]:INV.OTCLK1
B22 IOI[1]:TFF1_LATCH IOI[1]:OFF1_LATCH - ~IOI[1]:INV.TCE
B21 IOI[1]:TFF2_LATCH IOI[1]:OFF2_LATCH - IOI[0]:IDDRIN_MUX[2]
B20 IOI[1]:TMUX[2] IOI[1]:OMUX[2] - -
B19 IOI[0]:TMUX[2] IOI[0]:OMUX[2] - -
B18 IOI[0]:TFF2_LATCH IOI[0]:OFF2_LATCH - IOI[1]:IDDRIN_MUX[2]
B17 IOI[0]:TFF1_LATCH IOI[0]:OFF1_LATCH - ~IOI[0]:INV.TCE
B16 IOI[0]:TMUX[0] IOI[0]:OMUX[0] ~IOI[0]:IFF2_SRVAL ~IOI[0]:INV.OTCLK1
B15 IOI[0]:TMUX[3] IOI[0]:OMUX[3] - ~IOI[0]:INV.OTCLK2
B14 IOI[0]:TMUX[1] IOI[0]:OMUX[1] - ~IOI[0]:INV.ICE
B13 IOI[0]:TFF_SR_SYNC IOI[0]:OFF_SR_SYNC - ~IOI[0]:INV.ICLK1
B12 IOI[0]:INV.T1 IOI[0]:INV.O1 ~IOI[0]:IFF2_INIT ~IOI[0]:INV.ICLK2
B11 IOI[0]:INV.T2 IOI[0]:INV.O2 IOI[0]:IFF_LATCH ~IOI[0]:INV.REV
B10 IOI[0]:TFF_SR_ENABLE IOI[0]:OFF_SR_ENABLE IOI[0]:IFF_SR_ENABLE IOI[0]:I_DELAY_ENABLE
B9 IOI[0]:TFF_REV_ENABLE IOI[0]:OFF_REV_ENABLE IOI[0]:IFF_REV_ENABLE -
B8 ~IOI[0]:TFF_INIT ~IOI[0]:OFF_INIT IOI[0]:IFF_SR_SYNC IOI[0]:IDDRIN_MUX[0]
B7 IOI[0]:MISR_RESET - ~IOI[0]:IFF1_INIT IOI[0]:I_TSBYPASS_ENABLE
B6 IOI[0]:MISR_ENABLE - - -
B5 ~IOI[0]:TFF2_SRVAL ~IOI[0]:OFF2_SRVAL - -
B4 - IOI[1]:O1_DDRMUX[0] - IOI[0]:TSBYPASS_MUX[0]
B3 ~IOI[0]:TFF1_SRVAL ~IOI[0]:OFF1_SRVAL ~IOI[0]:IFF1_SRVAL IOI[0]:IFF_TSBYPASS_ENABLE
B2 IOI[1]:O2_DDRMUX[0] - - IOI[1]:IDDRIN_MUX[1]
B1 IOI[0]:MISR_CLOCK[1] - - IOI[0]:IFF_DELAY_ENABLE
B0 IOI[0]:MISR_CLOCK[0] IOI[0]:PCICE_MUX[0] IOI[0]:PCICE_MUX[1] IOI[0]:READBACK_I
IOI[0]:DELAY_COMMON 0.F3.B41
IOI[0]:IFF1_INIT 0.F2.B7
IOI[0]:IFF1_SRVAL 0.F2.B3
IOI[0]:IFF2_INIT 0.F2.B12
IOI[0]:IFF2_SRVAL 0.F2.B16
IOI[0]:INV.ICE 0.F3.B14
IOI[0]:INV.ICLK1 0.F3.B13
IOI[0]:INV.ICLK2 0.F3.B12
IOI[0]:INV.OTCLK1 0.F3.B16
IOI[0]:INV.OTCLK2 0.F3.B15
IOI[0]:INV.REV 0.F3.B11
IOI[0]:INV.TCE 0.F3.B17
IOI[0]:OFF1_SRVAL 0.F1.B3
IOI[0]:OFF2_SRVAL 0.F1.B5
IOI[0]:OFF_INIT 0.F1.B8
IOI[0]:TFF1_SRVAL 0.F0.B3
IOI[0]:TFF2_SRVAL 0.F0.B5
IOI[0]:TFF_INIT 0.F0.B8
IOI[1]:DELAY_COMMON 0.F3.B42
IOI[1]:IFF1_INIT 0.F2.B32
IOI[1]:IFF1_SRVAL 0.F2.B36
IOI[1]:IFF2_INIT 0.F2.B27
IOI[1]:IFF2_SRVAL 0.F2.B23
IOI[1]:INV.ICE 0.F3.B25
IOI[1]:INV.ICLK1 0.F3.B26
IOI[1]:INV.ICLK2 0.F3.B27
IOI[1]:INV.OTCLK1 0.F3.B23
IOI[1]:INV.OTCLK2 0.F3.B24
IOI[1]:INV.REV 0.F3.B28
IOI[1]:INV.TCE 0.F3.B22
IOI[1]:OFF1_SRVAL 0.F1.B36
IOI[1]:OFF2_SRVAL 0.F1.B34
IOI[1]:OFF_INIT 0.F1.B31
IOI[1]:TFF1_SRVAL 0.F0.B36
IOI[1]:TFF2_SRVAL 0.F0.B34
IOI[1]:TFF_INIT 0.F0.B31
inverted ~[0]
IOI[0]:DELAY_VARIABLE 0.F3.B48
IOI[0]:IFF_DELAY_ENABLE 0.F3.B1
IOI[0]:IFF_LATCH 0.F2.B11
IOI[0]:IFF_REV_ENABLE 0.F2.B9
IOI[0]:IFF_SR_ENABLE 0.F2.B10
IOI[0]:IFF_SR_SYNC 0.F2.B8
IOI[0]:IFF_TSBYPASS_ENABLE 0.F3.B3
IOI[0]:INV.O1 0.F1.B12
IOI[0]:INV.O2 0.F1.B11
IOI[0]:INV.T1 0.F0.B12
IOI[0]:INV.T2 0.F0.B11
IOI[0]:I_DELAY_ENABLE 0.F3.B10
IOI[0]:I_TSBYPASS_ENABLE 0.F3.B7
IOI[0]:MISR_ENABLE 0.F0.B6
IOI[0]:MISR_RESET 0.F0.B7
IOI[0]:OFF1_LATCH 0.F1.B17
IOI[0]:OFF2_LATCH 0.F1.B18
IOI[0]:OFF_REV_ENABLE 0.F1.B9
IOI[0]:OFF_SR_ENABLE 0.F1.B10
IOI[0]:OFF_SR_SYNC 0.F1.B13
IOI[0]:READBACK_I 0.F3.B0
IOI[0]:TFF1_LATCH 0.F0.B17
IOI[0]:TFF2_LATCH 0.F0.B18
IOI[0]:TFF_REV_ENABLE 0.F0.B9
IOI[0]:TFF_SR_ENABLE 0.F0.B10
IOI[0]:TFF_SR_SYNC 0.F0.B13
IOI[1]:DELAY_VARIABLE 0.F3.B57
IOI[1]:IFF_DELAY_ENABLE 0.F3.B38
IOI[1]:IFF_LATCH 0.F2.B28
IOI[1]:IFF_REV_ENABLE 0.F2.B30
IOI[1]:IFF_SR_ENABLE 0.F2.B29
IOI[1]:IFF_SR_SYNC 0.F2.B31
IOI[1]:IFF_TSBYPASS_ENABLE 0.F3.B36
IOI[1]:INV.O1 0.F1.B27
IOI[1]:INV.O2 0.F1.B28
IOI[1]:INV.T1 0.F0.B27
IOI[1]:INV.T2 0.F0.B28
IOI[1]:I_DELAY_ENABLE 0.F3.B29
IOI[1]:I_TSBYPASS_ENABLE 0.F3.B32
IOI[1]:MISR_ENABLE 0.F0.B33
IOI[1]:MISR_RESET 0.F0.B32
IOI[1]:OFF1_LATCH 0.F1.B22
IOI[1]:OFF2_LATCH 0.F1.B21
IOI[1]:OFF_REV_ENABLE 0.F1.B30
IOI[1]:OFF_SR_ENABLE 0.F1.B29
IOI[1]:OFF_SR_SYNC 0.F1.B26
IOI[1]:READBACK_I 0.F3.B39
IOI[1]:TFF1_LATCH 0.F0.B22
IOI[1]:TFF2_LATCH 0.F0.B21
IOI[1]:TFF_REV_ENABLE 0.F0.B30
IOI[1]:TFF_SR_ENABLE 0.F0.B29
IOI[1]:TFF_SR_SYNC 0.F0.B26
non-inverted [0]
IOI[0]:IDDRIN_MUX 0.F3.B21 0.F3.B37 0.F3.B8
IOI[1]:IDDRIN_MUX 0.F3.B18 0.F3.B2 0.F3.B30
NONE 0 0 0
IFFDMUX 0 0 1
IDDRIN1 0 1 0
IDDRIN2 1 0 0
IOI[0]:IFF_DELAY 0.F3.B53 0.F3.B51
IOI[1]:IFF_DELAY 0.F3.B58 0.F3.B47
inverted ~[1] ~[0]
IOI[0]:I_DELAY 0.F3.B50 0.F3.B49 0.F3.B52
IOI[1]:I_DELAY 0.F3.B56 0.F3.B55 0.F3.B54
inverted ~[2] ~[1] ~[0]
IOI[0]:MISR_CLOCK 0.F0.B1 0.F0.B0
IOI[1]:MISR_CLOCK 0.F0.B38 0.F0.B39
NONE 0 0
OTCLK1 0 1
OTCLK2 1 0
IOI[0]:O1_DDRMUX 0.F1.B35
IOI[1]:O1_DDRMUX 0.F1.B4
O1 0
ODDRIN1 1
IOI[0]:O2_DDRMUX 0.F0.B37
IOI[1]:O2_DDRMUX 0.F0.B2
O2 0
ODDRIN2 1
IOI[0]:OMUX 0.F1.B15 0.F1.B19 0.F1.B14 0.F1.B16
IOI[1]:OMUX 0.F1.B24 0.F1.B20 0.F1.B25 0.F1.B23
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IOI[0]:PCICE_MUX 0.F2.B0 0.F1.B0
IOI[1]:PCICE_MUX 0.F2.B39 0.F1.B39
NONE 0 0
OCE 0 1
PCICE 1 0
IOI[0]:TMUX 0.F0.B15 0.F0.B19 0.F0.B14 0.F0.B16
IOI[1]:TMUX 0.F0.B24 0.F0.B20 0.F0.B25 0.F0.B23
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IOI[0]:TSBYPASS_MUX 0.F3.B4
IOI[1]:TSBYPASS_MUX 0.F3.B35
TMUX 0
GND 1

Tile IOI_S3A_S

Cells: 1

Bel IOI[0]

spartan3 IOI_S3A_S bel IOI[0]
PinDirectionWires
IoutputOUT_FAN[4]
ICEinputIMUX_DATA[8]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[8]
IQ2outputOUT_SEC[12]
O1inputIMUX_DATA[24]
O2inputIMUX_DATA[28]
OCEinputIMUX_CE[0]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[0]
S1inputIMUX_DATA[12]
S2inputIMUX_DATA[7]
S3inputIMUX_DATA[3]
SRinputIMUX_SR[0]
ToutputOUT_FAN[0]
T1inputIMUX_DATA[16]
T2inputIMUX_DATA[20]
TCEinputIMUX_DATA[4]

Bel IOI[1]

spartan3 IOI_S3A_S bel IOI[1]
PinDirectionWires
IoutputOUT_FAN[5]
ICEinputIMUX_DATA[9]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[9]
IQ2outputOUT_SEC[13]
O1inputIMUX_DATA[25]
O2inputIMUX_DATA[29]
OCEinputIMUX_CE[1]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[1]
S1inputIMUX_DATA[15]
S2inputIMUX_DATA[14]
S3inputIMUX_DATA[11]
SRinputIMUX_SR[1]
ToutputOUT_FAN[1]
T1inputIMUX_DATA[17]
T2inputIMUX_DATA[21]
TCEinputIMUX_DATA[5]

Bel IOI[2]

spartan3 IOI_S3A_S bel IOI[2]
PinDirectionWires
IoutputOUT_FAN[6]
ICEinputIMUX_DATA[10]
ICLK1inputIMUX_IOCLK[2]
ICLK2inputIMUX_IOCLK[6]
IQ1outputOUT_SEC[10]
IQ2outputOUT_SEC[14]
O1inputIMUX_DATA[26]
O2inputIMUX_DATA[30]
OCEinputIMUX_CE[2]
OTCLK1inputIMUX_IOCLK[3]
OTCLK2inputIMUX_IOCLK[7]
REVinputIMUX_DATA[2]
S1inputIMUX_DATA[31]
S2inputIMUX_DATA[27]
S3inputIMUX_DATA[23]
SRinputIMUX_SR[2]
ToutputOUT_FAN[2]
T1inputIMUX_DATA[18]
T2inputIMUX_DATA[22]
TCEinputIMUX_DATA[6]

Bel wires

spartan3 IOI_S3A_S bel wires
WirePins
IMUX_SR[0]IOI[0].SR
IMUX_SR[1]IOI[1].SR
IMUX_SR[2]IOI[2].SR
IMUX_CE[0]IOI[0].OCE
IMUX_CE[1]IOI[1].OCE
IMUX_CE[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[3]IOI[0].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[7]IOI[0].S2
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[11]IOI[1].S3
IMUX_DATA[12]IOI[0].S1
IMUX_DATA[14]IOI[1].S2
IMUX_DATA[15]IOI[1].S1
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[23]IOI[2].S3
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[27]IOI[2].S2
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
IMUX_DATA[31]IOI[2].S1
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3A_S rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_S3A_S rect R0
BitFrame
F0 F1 F2 F3
B59 IOI[2]:TMUX[2] IOI[2]:OMUX[2] - -
B58 IOI[2]:TFF2_LATCH IOI[2]:OFF2_LATCH - IOI[2]:IDDRIN_MUX[2]
B57 IOI[2]:TFF1_LATCH IOI[2]:OFF1_LATCH - ~IOI[2]:INV.TCE
B56 IOI[2]:TMUX[0] IOI[2]:OMUX[0] ~IOI[2]:IFF2_SRVAL ~IOI[2]:INV.OTCLK1
B55 IOI[2]:TMUX[3] IOI[2]:OMUX[3] - ~IOI[2]:INV.OTCLK2
B54 IOI[2]:TMUX[1] IOI[2]:OMUX[1] - ~IOI[2]:INV.ICE
B53 IOI[2]:TFF_SR_SYNC IOI[2]:OFF_SR_SYNC - ~IOI[2]:INV.ICLK1
B52 IOI[2]:INV.T1 IOI[2]:INV.O1 ~IOI[2]:IFF2_INIT ~IOI[2]:INV.ICLK2
B51 IOI[2]:INV.T2 IOI[2]:INV.O2 IOI[2]:IFF_LATCH ~IOI[2]:INV.REV
B50 IOI[2]:TFF_SR_ENABLE IOI[2]:OFF_SR_ENABLE IOI[2]:IFF_SR_ENABLE IOI[2]:I_DELAY_ENABLE
B49 IOI[2]:TFF_REV_ENABLE IOI[2]:OFF_REV_ENABLE IOI[2]:IFF_REV_ENABLE -
B48 ~IOI[2]:TFF_INIT ~IOI[2]:OFF_INIT IOI[2]:IFF_SR_SYNC IOI[2]:IDDRIN_MUX[0]
B47 IOI[2]:MISR_RESET - ~IOI[2]:IFF1_INIT IOI[2]:I_TSBYPASS_ENABLE
B46 IOI[2]:MISR_ENABLE - - -
B45 ~IOI[2]:TFF2_SRVAL ~IOI[2]:OFF2_SRVAL - -
B44 - - - IOI[2]:TSBYPASS_MUX[0]
B43 ~IOI[2]:TFF1_SRVAL ~IOI[2]:OFF1_SRVAL ~IOI[2]:IFF1_SRVAL IOI[2]:IFF_TSBYPASS_ENABLE
B42 - - - IOI[2]:IDDRIN_MUX[1]
B41 IOI[2]:MISR_CLOCK[1] - - IOI[2]:IFF_DELAY_ENABLE
B40 IOI[2]:MISR_CLOCK[0] IOI[2]:PCICE_MUX[0] IOI[2]:PCICE_MUX[1] IOI[2]:READBACK_I
B39 IOI[1]:MISR_CLOCK[0] IOI[1]:PCICE_MUX[0] IOI[1]:PCICE_MUX[1] IOI[1]:READBACK_I
B38 IOI[1]:MISR_CLOCK[1] - - IOI[1]:IFF_DELAY_ENABLE
B37 IOI[0]:O2_DDRMUX[0] - - IOI[0]:IDDRIN_MUX[1]
B36 ~IOI[1]:TFF1_SRVAL ~IOI[1]:OFF1_SRVAL ~IOI[1]:IFF1_SRVAL IOI[1]:IFF_TSBYPASS_ENABLE
B35 - IOI[0]:O1_DDRMUX[0] - IOI[1]:TSBYPASS_MUX[0]
B34 ~IOI[1]:TFF2_SRVAL ~IOI[1]:OFF2_SRVAL - -
B33 IOI[1]:MISR_ENABLE - - -
B32 IOI[1]:MISR_RESET - ~IOI[1]:IFF1_INIT IOI[1]:I_TSBYPASS_ENABLE
B31 ~IOI[1]:TFF_INIT ~IOI[1]:OFF_INIT IOI[1]:IFF_SR_SYNC -
B30 IOI[1]:TFF_REV_ENABLE IOI[1]:OFF_REV_ENABLE IOI[1]:IFF_REV_ENABLE IOI[1]:IDDRIN_MUX[0]
B29 IOI[1]:TFF_SR_ENABLE IOI[1]:OFF_SR_ENABLE IOI[1]:IFF_SR_ENABLE IOI[1]:I_DELAY_ENABLE
B28 IOI[1]:INV.T2 IOI[1]:INV.O2 IOI[1]:IFF_LATCH ~IOI[1]:INV.REV
B27 IOI[1]:INV.T1 IOI[1]:INV.O1 ~IOI[1]:IFF2_INIT ~IOI[1]:INV.ICLK2
B26 IOI[1]:TFF_SR_SYNC IOI[1]:OFF_SR_SYNC - ~IOI[1]:INV.ICLK1
B25 IOI[1]:TMUX[1] IOI[1]:OMUX[1] - ~IOI[1]:INV.ICE
B24 IOI[1]:TMUX[3] IOI[1]:OMUX[3] - ~IOI[1]:INV.OTCLK2
B23 IOI[1]:TMUX[0] IOI[1]:OMUX[0] ~IOI[1]:IFF2_SRVAL ~IOI[1]:INV.OTCLK1
B22 IOI[1]:TFF1_LATCH IOI[1]:OFF1_LATCH - ~IOI[1]:INV.TCE
B21 IOI[1]:TFF2_LATCH IOI[1]:OFF2_LATCH - IOI[0]:IDDRIN_MUX[2]
B20 IOI[1]:TMUX[2] IOI[1]:OMUX[2] - -
B19 IOI[0]:TMUX[2] IOI[0]:OMUX[2] - -
B18 IOI[0]:TFF2_LATCH IOI[0]:OFF2_LATCH - IOI[1]:IDDRIN_MUX[2]
B17 IOI[0]:TFF1_LATCH IOI[0]:OFF1_LATCH - ~IOI[0]:INV.TCE
B16 IOI[0]:TMUX[0] IOI[0]:OMUX[0] ~IOI[0]:IFF2_SRVAL ~IOI[0]:INV.OTCLK1
B15 IOI[0]:TMUX[3] IOI[0]:OMUX[3] - ~IOI[0]:INV.OTCLK2
B14 IOI[0]:TMUX[1] IOI[0]:OMUX[1] - ~IOI[0]:INV.ICE
B13 IOI[0]:TFF_SR_SYNC IOI[0]:OFF_SR_SYNC - ~IOI[0]:INV.ICLK1
B12 IOI[0]:INV.T1 IOI[0]:INV.O1 ~IOI[0]:IFF2_INIT ~IOI[0]:INV.ICLK2
B11 IOI[0]:INV.T2 IOI[0]:INV.O2 IOI[0]:IFF_LATCH ~IOI[0]:INV.REV
B10 IOI[0]:TFF_SR_ENABLE IOI[0]:OFF_SR_ENABLE IOI[0]:IFF_SR_ENABLE IOI[0]:I_DELAY_ENABLE
B9 IOI[0]:TFF_REV_ENABLE IOI[0]:OFF_REV_ENABLE IOI[0]:IFF_REV_ENABLE -
B8 ~IOI[0]:TFF_INIT ~IOI[0]:OFF_INIT IOI[0]:IFF_SR_SYNC IOI[0]:IDDRIN_MUX[0]
B7 IOI[0]:MISR_RESET - ~IOI[0]:IFF1_INIT IOI[0]:I_TSBYPASS_ENABLE
B6 IOI[0]:MISR_ENABLE - - -
B5 ~IOI[0]:TFF2_SRVAL ~IOI[0]:OFF2_SRVAL - -
B4 - IOI[1]:O1_DDRMUX[0] - IOI[0]:TSBYPASS_MUX[0]
B3 ~IOI[0]:TFF1_SRVAL ~IOI[0]:OFF1_SRVAL ~IOI[0]:IFF1_SRVAL IOI[0]:IFF_TSBYPASS_ENABLE
B2 IOI[1]:O2_DDRMUX[0] - - IOI[1]:IDDRIN_MUX[1]
B1 IOI[0]:MISR_CLOCK[1] - - IOI[0]:IFF_DELAY_ENABLE
B0 IOI[0]:MISR_CLOCK[0] IOI[0]:PCICE_MUX[0] IOI[0]:PCICE_MUX[1] IOI[0]:READBACK_I
IOI[0]:IDDRIN_MUX 0.F3.B21 0.F3.B37 0.F3.B8
IOI[1]:IDDRIN_MUX 0.F3.B18 0.F3.B2 0.F3.B30
IOI[2]:IDDRIN_MUX 0.F3.B58 0.F3.B42 0.F3.B48
NONE 0 0 0
IFFDMUX 0 0 1
IDDRIN1 0 1 0
IDDRIN2 1 0 0
IOI[0]:IFF1_INIT 0.F2.B7
IOI[0]:IFF1_SRVAL 0.F2.B3
IOI[0]:IFF2_INIT 0.F2.B12
IOI[0]:IFF2_SRVAL 0.F2.B16
IOI[0]:INV.ICE 0.F3.B14
IOI[0]:INV.ICLK1 0.F3.B13
IOI[0]:INV.ICLK2 0.F3.B12
IOI[0]:INV.OTCLK1 0.F3.B16
IOI[0]:INV.OTCLK2 0.F3.B15
IOI[0]:INV.REV 0.F3.B11
IOI[0]:INV.TCE 0.F3.B17
IOI[0]:OFF1_SRVAL 0.F1.B3
IOI[0]:OFF2_SRVAL 0.F1.B5
IOI[0]:OFF_INIT 0.F1.B8
IOI[0]:TFF1_SRVAL 0.F0.B3
IOI[0]:TFF2_SRVAL 0.F0.B5
IOI[0]:TFF_INIT 0.F0.B8
IOI[1]:IFF1_INIT 0.F2.B32
IOI[1]:IFF1_SRVAL 0.F2.B36
IOI[1]:IFF2_INIT 0.F2.B27
IOI[1]:IFF2_SRVAL 0.F2.B23
IOI[1]:INV.ICE 0.F3.B25
IOI[1]:INV.ICLK1 0.F3.B26
IOI[1]:INV.ICLK2 0.F3.B27
IOI[1]:INV.OTCLK1 0.F3.B23
IOI[1]:INV.OTCLK2 0.F3.B24
IOI[1]:INV.REV 0.F3.B28
IOI[1]:INV.TCE 0.F3.B22
IOI[1]:OFF1_SRVAL 0.F1.B36
IOI[1]:OFF2_SRVAL 0.F1.B34
IOI[1]:OFF_INIT 0.F1.B31
IOI[1]:TFF1_SRVAL 0.F0.B36
IOI[1]:TFF2_SRVAL 0.F0.B34
IOI[1]:TFF_INIT 0.F0.B31
IOI[2]:IFF1_INIT 0.F2.B47
IOI[2]:IFF1_SRVAL 0.F2.B43
IOI[2]:IFF2_INIT 0.F2.B52
IOI[2]:IFF2_SRVAL 0.F2.B56
IOI[2]:INV.ICE 0.F3.B54
IOI[2]:INV.ICLK1 0.F3.B53
IOI[2]:INV.ICLK2 0.F3.B52
IOI[2]:INV.OTCLK1 0.F3.B56
IOI[2]:INV.OTCLK2 0.F3.B55
IOI[2]:INV.REV 0.F3.B51
IOI[2]:INV.TCE 0.F3.B57
IOI[2]:OFF1_SRVAL 0.F1.B43
IOI[2]:OFF2_SRVAL 0.F1.B45
IOI[2]:OFF_INIT 0.F1.B48
IOI[2]:TFF1_SRVAL 0.F0.B43
IOI[2]:TFF2_SRVAL 0.F0.B45
IOI[2]:TFF_INIT 0.F0.B48
inverted ~[0]
IOI[0]:IFF_DELAY_ENABLE 0.F3.B1
IOI[0]:IFF_LATCH 0.F2.B11
IOI[0]:IFF_REV_ENABLE 0.F2.B9
IOI[0]:IFF_SR_ENABLE 0.F2.B10
IOI[0]:IFF_SR_SYNC 0.F2.B8
IOI[0]:IFF_TSBYPASS_ENABLE 0.F3.B3
IOI[0]:INV.O1 0.F1.B12
IOI[0]:INV.O2 0.F1.B11
IOI[0]:INV.T1 0.F0.B12
IOI[0]:INV.T2 0.F0.B11
IOI[0]:I_DELAY_ENABLE 0.F3.B10
IOI[0]:I_TSBYPASS_ENABLE 0.F3.B7
IOI[0]:MISR_ENABLE 0.F0.B6
IOI[0]:MISR_RESET 0.F0.B7
IOI[0]:OFF1_LATCH 0.F1.B17
IOI[0]:OFF2_LATCH 0.F1.B18
IOI[0]:OFF_REV_ENABLE 0.F1.B9
IOI[0]:OFF_SR_ENABLE 0.F1.B10
IOI[0]:OFF_SR_SYNC 0.F1.B13
IOI[0]:READBACK_I 0.F3.B0
IOI[0]:TFF1_LATCH 0.F0.B17
IOI[0]:TFF2_LATCH 0.F0.B18
IOI[0]:TFF_REV_ENABLE 0.F0.B9
IOI[0]:TFF_SR_ENABLE 0.F0.B10
IOI[0]:TFF_SR_SYNC 0.F0.B13
IOI[1]:IFF_DELAY_ENABLE 0.F3.B38
IOI[1]:IFF_LATCH 0.F2.B28
IOI[1]:IFF_REV_ENABLE 0.F2.B30
IOI[1]:IFF_SR_ENABLE 0.F2.B29
IOI[1]:IFF_SR_SYNC 0.F2.B31
IOI[1]:IFF_TSBYPASS_ENABLE 0.F3.B36
IOI[1]:INV.O1 0.F1.B27
IOI[1]:INV.O2 0.F1.B28
IOI[1]:INV.T1 0.F0.B27
IOI[1]:INV.T2 0.F0.B28
IOI[1]:I_DELAY_ENABLE 0.F3.B29
IOI[1]:I_TSBYPASS_ENABLE 0.F3.B32
IOI[1]:MISR_ENABLE 0.F0.B33
IOI[1]:MISR_RESET 0.F0.B32
IOI[1]:OFF1_LATCH 0.F1.B22
IOI[1]:OFF2_LATCH 0.F1.B21
IOI[1]:OFF_REV_ENABLE 0.F1.B30
IOI[1]:OFF_SR_ENABLE 0.F1.B29
IOI[1]:OFF_SR_SYNC 0.F1.B26
IOI[1]:READBACK_I 0.F3.B39
IOI[1]:TFF1_LATCH 0.F0.B22
IOI[1]:TFF2_LATCH 0.F0.B21
IOI[1]:TFF_REV_ENABLE 0.F0.B30
IOI[1]:TFF_SR_ENABLE 0.F0.B29
IOI[1]:TFF_SR_SYNC 0.F0.B26
IOI[2]:IFF_DELAY_ENABLE 0.F3.B41
IOI[2]:IFF_LATCH 0.F2.B51
IOI[2]:IFF_REV_ENABLE 0.F2.B49
IOI[2]:IFF_SR_ENABLE 0.F2.B50
IOI[2]:IFF_SR_SYNC 0.F2.B48
IOI[2]:IFF_TSBYPASS_ENABLE 0.F3.B43
IOI[2]:INV.O1 0.F1.B52
IOI[2]:INV.O2 0.F1.B51
IOI[2]:INV.T1 0.F0.B52
IOI[2]:INV.T2 0.F0.B51
IOI[2]:I_DELAY_ENABLE 0.F3.B50
IOI[2]:I_TSBYPASS_ENABLE 0.F3.B47
IOI[2]:MISR_ENABLE 0.F0.B46
IOI[2]:MISR_RESET 0.F0.B47
IOI[2]:OFF1_LATCH 0.F1.B57
IOI[2]:OFF2_LATCH 0.F1.B58
IOI[2]:OFF_REV_ENABLE 0.F1.B49
IOI[2]:OFF_SR_ENABLE 0.F1.B50
IOI[2]:OFF_SR_SYNC 0.F1.B53
IOI[2]:READBACK_I 0.F3.B40
IOI[2]:TFF1_LATCH 0.F0.B57
IOI[2]:TFF2_LATCH 0.F0.B58
IOI[2]:TFF_REV_ENABLE 0.F0.B49
IOI[2]:TFF_SR_ENABLE 0.F0.B50
IOI[2]:TFF_SR_SYNC 0.F0.B53
non-inverted [0]
IOI[0]:MISR_CLOCK 0.F0.B1 0.F0.B0
IOI[1]:MISR_CLOCK 0.F0.B38 0.F0.B39
IOI[2]:MISR_CLOCK 0.F0.B41 0.F0.B40
NONE 0 0
OTCLK1 0 1
OTCLK2 1 0
IOI[0]:O1_DDRMUX 0.F1.B35
IOI[1]:O1_DDRMUX 0.F1.B4
O1 0
ODDRIN1 1
IOI[0]:O2_DDRMUX 0.F0.B37
IOI[1]:O2_DDRMUX 0.F0.B2
O2 0
ODDRIN2 1
IOI[0]:OMUX 0.F1.B15 0.F1.B19 0.F1.B14 0.F1.B16
IOI[1]:OMUX 0.F1.B24 0.F1.B20 0.F1.B25 0.F1.B23
IOI[2]:OMUX 0.F1.B55 0.F1.B59 0.F1.B54 0.F1.B56
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IOI[0]:PCICE_MUX 0.F2.B0 0.F1.B0
IOI[1]:PCICE_MUX 0.F2.B39 0.F1.B39
IOI[2]:PCICE_MUX 0.F2.B40 0.F1.B40
NONE 0 0
OCE 0 1
PCICE 1 0
IOI[0]:TMUX 0.F0.B15 0.F0.B19 0.F0.B14 0.F0.B16
IOI[1]:TMUX 0.F0.B24 0.F0.B20 0.F0.B25 0.F0.B23
IOI[2]:TMUX 0.F0.B55 0.F0.B59 0.F0.B54 0.F0.B56
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IOI[0]:TSBYPASS_MUX 0.F3.B4
IOI[1]:TSBYPASS_MUX 0.F3.B35
IOI[2]:TSBYPASS_MUX 0.F3.B44
TMUX 0
GND 1

Tile IOI_S3A_N

Cells: 1

Bel IOI[0]

spartan3 IOI_S3A_N bel IOI[0]
PinDirectionWires
IoutputOUT_FAN[4]
ICEinputIMUX_DATA[8]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[8]
IQ2outputOUT_SEC[12]
O1inputIMUX_DATA[24]
O2inputIMUX_DATA[28]
OCEinputIMUX_CE[0]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[0]
S1inputIMUX_DATA[31]
S2inputIMUX_DATA[27]
S3inputIMUX_DATA[23]
SRinputIMUX_SR[0]
ToutputOUT_FAN[0]
T1inputIMUX_DATA[16]
T2inputIMUX_DATA[20]
TCEinputIMUX_DATA[4]

Bel IOI[1]

spartan3 IOI_S3A_N bel IOI[1]
PinDirectionWires
IoutputOUT_FAN[5]
ICEinputIMUX_DATA[9]
ICLK1inputIMUX_IOCLK[0]
ICLK2inputIMUX_IOCLK[4]
IQ1outputOUT_SEC[9]
IQ2outputOUT_SEC[13]
O1inputIMUX_DATA[25]
O2inputIMUX_DATA[29]
OCEinputIMUX_CE[1]
OTCLK1inputIMUX_IOCLK[1]
OTCLK2inputIMUX_IOCLK[5]
REVinputIMUX_DATA[1]
S1inputIMUX_DATA[15]
S2inputIMUX_DATA[14]
S3inputIMUX_DATA[11]
SRinputIMUX_SR[1]
ToutputOUT_FAN[1]
T1inputIMUX_DATA[17]
T2inputIMUX_DATA[21]
TCEinputIMUX_DATA[5]

Bel IOI[2]

spartan3 IOI_S3A_N bel IOI[2]
PinDirectionWires
IoutputOUT_FAN[6]
ICEinputIMUX_DATA[10]
ICLK1inputIMUX_IOCLK[2]
ICLK2inputIMUX_IOCLK[6]
IQ1outputOUT_SEC[10]
IQ2outputOUT_SEC[14]
O1inputIMUX_DATA[26]
O2inputIMUX_DATA[30]
OCEinputIMUX_CE[2]
OTCLK1inputIMUX_IOCLK[3]
OTCLK2inputIMUX_IOCLK[7]
REVinputIMUX_DATA[2]
S1inputIMUX_DATA[12]
S2inputIMUX_DATA[7]
S3inputIMUX_DATA[3]
SRinputIMUX_SR[2]
ToutputOUT_FAN[2]
T1inputIMUX_DATA[18]
T2inputIMUX_DATA[22]
TCEinputIMUX_DATA[6]

Bel wires

spartan3 IOI_S3A_N bel wires
WirePins
IMUX_SR[0]IOI[0].SR
IMUX_SR[1]IOI[1].SR
IMUX_SR[2]IOI[2].SR
IMUX_CE[0]IOI[0].OCE
IMUX_CE[1]IOI[1].OCE
IMUX_CE[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[3]IOI[2].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[7]IOI[2].S2
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[11]IOI[1].S3
IMUX_DATA[12]IOI[2].S1
IMUX_DATA[14]IOI[1].S2
IMUX_DATA[15]IOI[1].S1
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[23]IOI[0].S3
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[27]IOI[0].S2
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
IMUX_DATA[31]IOI[0].S1
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3A_N rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOI_S3A_N rect R0
BitFrame
F0 F1 F2 F3
B59 IOI[2]:TMUX[2] IOI[2]:OMUX[2] - -
B58 IOI[2]:TFF2_LATCH IOI[2]:OFF2_LATCH - IOI[2]:IDDRIN_MUX[2]
B57 IOI[2]:TFF1_LATCH IOI[2]:OFF1_LATCH - ~IOI[2]:INV.TCE
B56 IOI[2]:TMUX[0] IOI[2]:OMUX[0] ~IOI[2]:IFF2_SRVAL ~IOI[2]:INV.OTCLK1
B55 IOI[2]:TMUX[3] IOI[2]:OMUX[3] - ~IOI[2]:INV.OTCLK2
B54 IOI[2]:TMUX[1] IOI[2]:OMUX[1] - ~IOI[2]:INV.ICE
B53 IOI[2]:TFF_SR_SYNC IOI[2]:OFF_SR_SYNC - ~IOI[2]:INV.ICLK1
B52 IOI[2]:INV.T1 IOI[2]:INV.O1 ~IOI[2]:IFF2_INIT ~IOI[2]:INV.ICLK2
B51 IOI[2]:INV.T2 IOI[2]:INV.O2 IOI[2]:IFF_LATCH ~IOI[2]:INV.REV
B50 IOI[2]:TFF_SR_ENABLE IOI[2]:OFF_SR_ENABLE IOI[2]:IFF_SR_ENABLE IOI[2]:I_DELAY_ENABLE
B49 IOI[2]:TFF_REV_ENABLE IOI[2]:OFF_REV_ENABLE IOI[2]:IFF_REV_ENABLE -
B48 ~IOI[2]:TFF_INIT ~IOI[2]:OFF_INIT IOI[2]:IFF_SR_SYNC IOI[2]:IDDRIN_MUX[0]
B47 IOI[2]:MISR_RESET - ~IOI[2]:IFF1_INIT IOI[2]:I_TSBYPASS_ENABLE
B46 IOI[2]:MISR_ENABLE - - -
B45 ~IOI[2]:TFF2_SRVAL ~IOI[2]:OFF2_SRVAL - -
B44 - - - IOI[2]:TSBYPASS_MUX[0]
B43 ~IOI[2]:TFF1_SRVAL ~IOI[2]:OFF1_SRVAL ~IOI[2]:IFF1_SRVAL IOI[2]:IFF_TSBYPASS_ENABLE
B42 - - - IOI[2]:IDDRIN_MUX[1]
B41 IOI[2]:MISR_CLOCK[1] - - IOI[2]:IFF_DELAY_ENABLE
B40 IOI[2]:MISR_CLOCK[0] IOI[2]:PCICE_MUX[0] IOI[2]:PCICE_MUX[1] IOI[2]:READBACK_I
B39 IOI[1]:MISR_CLOCK[0] IOI[1]:PCICE_MUX[0] IOI[1]:PCICE_MUX[1] IOI[1]:READBACK_I
B38 IOI[1]:MISR_CLOCK[1] - - IOI[1]:IFF_DELAY_ENABLE
B37 IOI[0]:O2_DDRMUX[0] - - IOI[0]:IDDRIN_MUX[1]
B36 ~IOI[1]:TFF1_SRVAL ~IOI[1]:OFF1_SRVAL ~IOI[1]:IFF1_SRVAL IOI[1]:IFF_TSBYPASS_ENABLE
B35 - IOI[0]:O1_DDRMUX[0] - IOI[1]:TSBYPASS_MUX[0]
B34 ~IOI[1]:TFF2_SRVAL ~IOI[1]:OFF2_SRVAL - -
B33 IOI[1]:MISR_ENABLE - - -
B32 IOI[1]:MISR_RESET - ~IOI[1]:IFF1_INIT IOI[1]:I_TSBYPASS_ENABLE
B31 ~IOI[1]:TFF_INIT ~IOI[1]:OFF_INIT IOI[1]:IFF_SR_SYNC -
B30 IOI[1]:TFF_REV_ENABLE IOI[1]:OFF_REV_ENABLE IOI[1]:IFF_REV_ENABLE IOI[1]:IDDRIN_MUX[0]
B29 IOI[1]:TFF_SR_ENABLE IOI[1]:OFF_SR_ENABLE IOI[1]:IFF_SR_ENABLE IOI[1]:I_DELAY_ENABLE
B28 IOI[1]:INV.T2 IOI[1]:INV.O2 IOI[1]:IFF_LATCH ~IOI[1]:INV.REV
B27 IOI[1]:INV.T1 IOI[1]:INV.O1 ~IOI[1]:IFF2_INIT ~IOI[1]:INV.ICLK2
B26 IOI[1]:TFF_SR_SYNC IOI[1]:OFF_SR_SYNC - ~IOI[1]:INV.ICLK1
B25 IOI[1]:TMUX[1] IOI[1]:OMUX[1] - ~IOI[1]:INV.ICE
B24 IOI[1]:TMUX[3] IOI[1]:OMUX[3] - ~IOI[1]:INV.OTCLK2
B23 IOI[1]:TMUX[0] IOI[1]:OMUX[0] ~IOI[1]:IFF2_SRVAL ~IOI[1]:INV.OTCLK1
B22 IOI[1]:TFF1_LATCH IOI[1]:OFF1_LATCH - ~IOI[1]:INV.TCE
B21 IOI[1]:TFF2_LATCH IOI[1]:OFF2_LATCH - IOI[0]:IDDRIN_MUX[2]
B20 IOI[1]:TMUX[2] IOI[1]:OMUX[2] - -
B19 IOI[0]:TMUX[2] IOI[0]:OMUX[2] - -
B18 IOI[0]:TFF2_LATCH IOI[0]:OFF2_LATCH - IOI[1]:IDDRIN_MUX[2]
B17 IOI[0]:TFF1_LATCH IOI[0]:OFF1_LATCH - ~IOI[0]:INV.TCE
B16 IOI[0]:TMUX[0] IOI[0]:OMUX[0] ~IOI[0]:IFF2_SRVAL ~IOI[0]:INV.OTCLK1
B15 IOI[0]:TMUX[3] IOI[0]:OMUX[3] - ~IOI[0]:INV.OTCLK2
B14 IOI[0]:TMUX[1] IOI[0]:OMUX[1] - ~IOI[0]:INV.ICE
B13 IOI[0]:TFF_SR_SYNC IOI[0]:OFF_SR_SYNC - ~IOI[0]:INV.ICLK1
B12 IOI[0]:INV.T1 IOI[0]:INV.O1 ~IOI[0]:IFF2_INIT ~IOI[0]:INV.ICLK2
B11 IOI[0]:INV.T2 IOI[0]:INV.O2 IOI[0]:IFF_LATCH ~IOI[0]:INV.REV
B10 IOI[0]:TFF_SR_ENABLE IOI[0]:OFF_SR_ENABLE IOI[0]:IFF_SR_ENABLE IOI[0]:I_DELAY_ENABLE
B9 IOI[0]:TFF_REV_ENABLE IOI[0]:OFF_REV_ENABLE IOI[0]:IFF_REV_ENABLE -
B8 ~IOI[0]:TFF_INIT ~IOI[0]:OFF_INIT IOI[0]:IFF_SR_SYNC IOI[0]:IDDRIN_MUX[0]
B7 IOI[0]:MISR_RESET - ~IOI[0]:IFF1_INIT IOI[0]:I_TSBYPASS_ENABLE
B6 IOI[0]:MISR_ENABLE - - -
B5 ~IOI[0]:TFF2_SRVAL ~IOI[0]:OFF2_SRVAL - -
B4 - IOI[1]:O1_DDRMUX[0] - IOI[0]:TSBYPASS_MUX[0]
B3 ~IOI[0]:TFF1_SRVAL ~IOI[0]:OFF1_SRVAL ~IOI[0]:IFF1_SRVAL IOI[0]:IFF_TSBYPASS_ENABLE
B2 IOI[1]:O2_DDRMUX[0] - - IOI[1]:IDDRIN_MUX[1]
B1 IOI[0]:MISR_CLOCK[1] - - IOI[0]:IFF_DELAY_ENABLE
B0 IOI[0]:MISR_CLOCK[0] IOI[0]:PCICE_MUX[0] IOI[0]:PCICE_MUX[1] IOI[0]:READBACK_I
IOI[0]:IDDRIN_MUX 0.F3.B21 0.F3.B37 0.F3.B8
IOI[1]:IDDRIN_MUX 0.F3.B18 0.F3.B2 0.F3.B30
IOI[2]:IDDRIN_MUX 0.F3.B58 0.F3.B42 0.F3.B48
NONE 0 0 0
IFFDMUX 0 0 1
IDDRIN1 0 1 0
IDDRIN2 1 0 0
IOI[0]:IFF1_INIT 0.F2.B7
IOI[0]:IFF1_SRVAL 0.F2.B3
IOI[0]:IFF2_INIT 0.F2.B12
IOI[0]:IFF2_SRVAL 0.F2.B16
IOI[0]:INV.ICE 0.F3.B14
IOI[0]:INV.ICLK1 0.F3.B13
IOI[0]:INV.ICLK2 0.F3.B12
IOI[0]:INV.OTCLK1 0.F3.B16
IOI[0]:INV.OTCLK2 0.F3.B15
IOI[0]:INV.REV 0.F3.B11
IOI[0]:INV.TCE 0.F3.B17
IOI[0]:OFF1_SRVAL 0.F1.B3
IOI[0]:OFF2_SRVAL 0.F1.B5
IOI[0]:OFF_INIT 0.F1.B8
IOI[0]:TFF1_SRVAL 0.F0.B3
IOI[0]:TFF2_SRVAL 0.F0.B5
IOI[0]:TFF_INIT 0.F0.B8
IOI[1]:IFF1_INIT 0.F2.B32
IOI[1]:IFF1_SRVAL 0.F2.B36
IOI[1]:IFF2_INIT 0.F2.B27
IOI[1]:IFF2_SRVAL 0.F2.B23
IOI[1]:INV.ICE 0.F3.B25
IOI[1]:INV.ICLK1 0.F3.B26
IOI[1]:INV.ICLK2 0.F3.B27
IOI[1]:INV.OTCLK1 0.F3.B23
IOI[1]:INV.OTCLK2 0.F3.B24
IOI[1]:INV.REV 0.F3.B28
IOI[1]:INV.TCE 0.F3.B22
IOI[1]:OFF1_SRVAL 0.F1.B36
IOI[1]:OFF2_SRVAL 0.F1.B34
IOI[1]:OFF_INIT 0.F1.B31
IOI[1]:TFF1_SRVAL 0.F0.B36
IOI[1]:TFF2_SRVAL 0.F0.B34
IOI[1]:TFF_INIT 0.F0.B31
IOI[2]:IFF1_INIT 0.F2.B47
IOI[2]:IFF1_SRVAL 0.F2.B43
IOI[2]:IFF2_INIT 0.F2.B52
IOI[2]:IFF2_SRVAL 0.F2.B56
IOI[2]:INV.ICE 0.F3.B54
IOI[2]:INV.ICLK1 0.F3.B53
IOI[2]:INV.ICLK2 0.F3.B52
IOI[2]:INV.OTCLK1 0.F3.B56
IOI[2]:INV.OTCLK2 0.F3.B55
IOI[2]:INV.REV 0.F3.B51
IOI[2]:INV.TCE 0.F3.B57
IOI[2]:OFF1_SRVAL 0.F1.B43
IOI[2]:OFF2_SRVAL 0.F1.B45
IOI[2]:OFF_INIT 0.F1.B48
IOI[2]:TFF1_SRVAL 0.F0.B43
IOI[2]:TFF2_SRVAL 0.F0.B45
IOI[2]:TFF_INIT 0.F0.B48
inverted ~[0]
IOI[0]:IFF_DELAY_ENABLE 0.F3.B1
IOI[0]:IFF_LATCH 0.F2.B11
IOI[0]:IFF_REV_ENABLE 0.F2.B9
IOI[0]:IFF_SR_ENABLE 0.F2.B10
IOI[0]:IFF_SR_SYNC 0.F2.B8
IOI[0]:IFF_TSBYPASS_ENABLE 0.F3.B3
IOI[0]:INV.O1 0.F1.B12
IOI[0]:INV.O2 0.F1.B11
IOI[0]:INV.T1 0.F0.B12
IOI[0]:INV.T2 0.F0.B11
IOI[0]:I_DELAY_ENABLE 0.F3.B10
IOI[0]:I_TSBYPASS_ENABLE 0.F3.B7
IOI[0]:MISR_ENABLE 0.F0.B6
IOI[0]:MISR_RESET 0.F0.B7
IOI[0]:OFF1_LATCH 0.F1.B17
IOI[0]:OFF2_LATCH 0.F1.B18
IOI[0]:OFF_REV_ENABLE 0.F1.B9
IOI[0]:OFF_SR_ENABLE 0.F1.B10
IOI[0]:OFF_SR_SYNC 0.F1.B13
IOI[0]:READBACK_I 0.F3.B0
IOI[0]:TFF1_LATCH 0.F0.B17
IOI[0]:TFF2_LATCH 0.F0.B18
IOI[0]:TFF_REV_ENABLE 0.F0.B9
IOI[0]:TFF_SR_ENABLE 0.F0.B10
IOI[0]:TFF_SR_SYNC 0.F0.B13
IOI[1]:IFF_DELAY_ENABLE 0.F3.B38
IOI[1]:IFF_LATCH 0.F2.B28
IOI[1]:IFF_REV_ENABLE 0.F2.B30
IOI[1]:IFF_SR_ENABLE 0.F2.B29
IOI[1]:IFF_SR_SYNC 0.F2.B31
IOI[1]:IFF_TSBYPASS_ENABLE 0.F3.B36
IOI[1]:INV.O1 0.F1.B27
IOI[1]:INV.O2 0.F1.B28
IOI[1]:INV.T1 0.F0.B27
IOI[1]:INV.T2 0.F0.B28
IOI[1]:I_DELAY_ENABLE 0.F3.B29
IOI[1]:I_TSBYPASS_ENABLE 0.F3.B32
IOI[1]:MISR_ENABLE 0.F0.B33
IOI[1]:MISR_RESET 0.F0.B32
IOI[1]:OFF1_LATCH 0.F1.B22
IOI[1]:OFF2_LATCH 0.F1.B21
IOI[1]:OFF_REV_ENABLE 0.F1.B30
IOI[1]:OFF_SR_ENABLE 0.F1.B29
IOI[1]:OFF_SR_SYNC 0.F1.B26
IOI[1]:READBACK_I 0.F3.B39
IOI[1]:TFF1_LATCH 0.F0.B22
IOI[1]:TFF2_LATCH 0.F0.B21
IOI[1]:TFF_REV_ENABLE 0.F0.B30
IOI[1]:TFF_SR_ENABLE 0.F0.B29
IOI[1]:TFF_SR_SYNC 0.F0.B26
IOI[2]:IFF_DELAY_ENABLE 0.F3.B41
IOI[2]:IFF_LATCH 0.F2.B51
IOI[2]:IFF_REV_ENABLE 0.F2.B49
IOI[2]:IFF_SR_ENABLE 0.F2.B50
IOI[2]:IFF_SR_SYNC 0.F2.B48
IOI[2]:IFF_TSBYPASS_ENABLE 0.F3.B43
IOI[2]:INV.O1 0.F1.B52
IOI[2]:INV.O2 0.F1.B51
IOI[2]:INV.T1 0.F0.B52
IOI[2]:INV.T2 0.F0.B51
IOI[2]:I_DELAY_ENABLE 0.F3.B50
IOI[2]:I_TSBYPASS_ENABLE 0.F3.B47
IOI[2]:MISR_ENABLE 0.F0.B46
IOI[2]:MISR_RESET 0.F0.B47
IOI[2]:OFF1_LATCH 0.F1.B57
IOI[2]:OFF2_LATCH 0.F1.B58
IOI[2]:OFF_REV_ENABLE 0.F1.B49
IOI[2]:OFF_SR_ENABLE 0.F1.B50
IOI[2]:OFF_SR_SYNC 0.F1.B53
IOI[2]:READBACK_I 0.F3.B40
IOI[2]:TFF1_LATCH 0.F0.B57
IOI[2]:TFF2_LATCH 0.F0.B58
IOI[2]:TFF_REV_ENABLE 0.F0.B49
IOI[2]:TFF_SR_ENABLE 0.F0.B50
IOI[2]:TFF_SR_SYNC 0.F0.B53
non-inverted [0]
IOI[0]:MISR_CLOCK 0.F0.B1 0.F0.B0
IOI[1]:MISR_CLOCK 0.F0.B38 0.F0.B39
IOI[2]:MISR_CLOCK 0.F0.B41 0.F0.B40
NONE 0 0
OTCLK1 0 1
OTCLK2 1 0
IOI[0]:O1_DDRMUX 0.F1.B35
IOI[1]:O1_DDRMUX 0.F1.B4
O1 0
ODDRIN1 1
IOI[0]:O2_DDRMUX 0.F0.B37
IOI[1]:O2_DDRMUX 0.F0.B2
O2 0
ODDRIN2 1
IOI[0]:OMUX 0.F1.B15 0.F1.B19 0.F1.B14 0.F1.B16
IOI[1]:OMUX 0.F1.B24 0.F1.B20 0.F1.B25 0.F1.B23
IOI[2]:OMUX 0.F1.B55 0.F1.B59 0.F1.B54 0.F1.B56
NONE 0 0 0 0
O1 0 0 0 1
O2 0 0 1 0
OFF1 0 1 0 0
OFF2 1 0 0 0
OFFDDR 1 1 0 0
IOI[0]:PCICE_MUX 0.F2.B0 0.F1.B0
IOI[1]:PCICE_MUX 0.F2.B39 0.F1.B39
IOI[2]:PCICE_MUX 0.F2.B40 0.F1.B40
NONE 0 0
OCE 0 1
PCICE 1 0
IOI[0]:TMUX 0.F0.B15 0.F0.B19 0.F0.B14 0.F0.B16
IOI[1]:TMUX 0.F0.B24 0.F0.B20 0.F0.B25 0.F0.B23
IOI[2]:TMUX 0.F0.B55 0.F0.B59 0.F0.B54 0.F0.B56
NONE 0 0 0 0
T1 0 0 0 1
T2 0 0 1 0
TFF1 0 1 0 0
TFF2 1 0 0 0
TFFDDR 1 1 0 0
IOI[0]:TSBYPASS_MUX 0.F3.B4
IOI[1]:TSBYPASS_MUX 0.F3.B35
IOI[2]:TSBYPASS_MUX 0.F3.B44
TMUX 0
GND 1