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I/O Interface

TODO: document

Tile IOI_S3

Cells: 1

Bels IOI

spartan3 IOI_S3 bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]
ICLK1inIMUX_IOCLK[0] invert by !MAIN[3][13]IMUX_IOCLK[0] invert by !MAIN[3][26]IMUX_IOCLK[2] invert by !MAIN[3][53]
ICLK2inIMUX_IOCLK[4] invert by !MAIN[3][12]IMUX_IOCLK[4] invert by !MAIN[3][27]IMUX_IOCLK[6] invert by !MAIN[3][52]
ICEinIMUX_DATA[8] invert by !MAIN[3][14]IMUX_DATA[9] invert by !MAIN[3][25]IMUX_DATA[10] invert by !MAIN[3][54]
O1inIMUX_DATA[24] invert by MAIN[1][12]IMUX_DATA[25] invert by MAIN[1][27]IMUX_DATA[26] invert by MAIN[1][52]
O2inIMUX_DATA[28] invert by MAIN[1][11]IMUX_DATA[29] invert by MAIN[1][28]IMUX_DATA[30] invert by MAIN[1][51]
T1inIMUX_DATA[16] invert by MAIN[0][12]IMUX_DATA[17] invert by MAIN[0][27]IMUX_DATA[18] invert by MAIN[0][52]
T2inIMUX_DATA[20] invert by MAIN[0][11]IMUX_DATA[21] invert by MAIN[0][28]IMUX_DATA[22] invert by MAIN[0][51]
OTCLK1inIMUX_IOCLK[1] invert by !MAIN[3][16]IMUX_IOCLK[1] invert by !MAIN[3][23]IMUX_IOCLK[3] invert by !MAIN[3][56]
OTCLK2inIMUX_IOCLK[5] invert by !MAIN[3][15]IMUX_IOCLK[5] invert by !MAIN[3][24]IMUX_IOCLK[7] invert by !MAIN[3][55]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]IMUX_CE_OPTINV[2]
TCEinIMUX_DATA[4] invert by !MAIN[3][17]IMUX_DATA[5] invert by !MAIN[3][22]IMUX_DATA[6] invert by !MAIN[3][57]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[2]
REVinIMUX_DATA[0] invert by !MAIN[3][11]IMUX_DATA[1] invert by !MAIN[3][28]IMUX_DATA[2] invert by !MAIN[3][51]
IoutOUT_FAN[4]OUT_FAN[5]OUT_FAN[6]
IQ1outOUT_SEC[8]OUT_SEC[9]OUT_SEC[10]
IQ2outOUT_SEC[12]OUT_SEC[13]OUT_SEC[14]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]-
ToutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]
spartan3 IOI_S3 bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]
FFI1_INIT bit 0!MAIN[2][7]!MAIN[2][32]!MAIN[2][47]
FFI2_INIT bit 0!MAIN[2][12]!MAIN[2][27]!MAIN[2][52]
FFI1_SRVAL bit 0!MAIN[2][3]!MAIN[2][36]!MAIN[2][43]
FFI2_SRVAL bit 0!MAIN[2][16]!MAIN[2][23]!MAIN[2][56]
FFI_LATCHMAIN[2][11]MAIN[2][28]MAIN[2][51]
FFI_SR_SYNCMAIN[2][8]MAIN[2][31]MAIN[2][48]
FFI_SR_ENABLEMAIN[2][10]MAIN[2][29]MAIN[2][50]
FFI_REV_ENABLEMAIN[2][9]MAIN[2][30]MAIN[2][49]
I_DELAY_ENABLEMAIN[3][10]MAIN[3][29]MAIN[3][50]
I_TSBYPASS_ENABLEMAIN[3][7]MAIN[3][32]MAIN[3][47]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][38]MAIN[3][41]
IQ_TSBYPASS_ENABLEMAIN[3][3]MAIN[3][36]MAIN[3][43]
READBACK_I bit 0MAIN[3][0]MAIN[3][39]MAIN[3][40]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
FFO_INIT bit 0!MAIN[1][8]!MAIN[1][31]!MAIN[1][48]
FFO1_SRVAL bit 0!MAIN[1][3]!MAIN[1][36]!MAIN[1][43]
FFO2_SRVAL bit 0!MAIN[1][5]!MAIN[1][34]!MAIN[1][45]
FFO1_LATCHMAIN[1][17]MAIN[1][22]MAIN[1][57]
FFO2_LATCHMAIN[1][18]MAIN[1][21]MAIN[1][58]
FFO_SR_SYNCMAIN[1][13]MAIN[1][26]MAIN[1][53]
FFO_SR_ENABLEMAIN[1][10]MAIN[1][29]MAIN[1][50]
FFO_REV_ENABLEMAIN[1][9]MAIN[1][30]MAIN[1][49]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O]
FFT_INIT bit 0!MAIN[0][8]!MAIN[0][31]!MAIN[0][48]
FFT1_SRVAL bit 0!MAIN[0][3]!MAIN[0][36]!MAIN[0][43]
FFT2_SRVAL bit 0!MAIN[0][5]!MAIN[0][34]!MAIN[0][45]
FFT1_LATCHMAIN[0][17]MAIN[0][22]MAIN[0][57]
FFT2_LATCHMAIN[0][18]MAIN[0][21]MAIN[0][58]
FFT_SR_SYNCMAIN[0][13]MAIN[0][26]MAIN[0][53]
FFT_SR_ENABLEMAIN[0][10]MAIN[0][29]MAIN[0][50]
FFT_REV_ENABLEMAIN[0][9]MAIN[0][30]MAIN[0][49]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T]
spartan3 IOI_S3 enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[3][4]
IOI[1].MUX_TSBYPASSMAIN[3][35]
IOI[2].MUX_TSBYPASSMAIN[3][44]
GND1
T0
spartan3 IOI_S3 enum IOI_MUX_O
IOI[0].MUX_OMAIN[1][15]MAIN[1][19]MAIN[1][14]MAIN[1][16]
IOI[1].MUX_OMAIN[1][24]MAIN[1][20]MAIN[1][25]MAIN[1][23]
IOI[2].MUX_OMAIN[1][55]MAIN[1][59]MAIN[1][54]MAIN[1][56]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
spartan3 IOI_S3 enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][15]MAIN[0][19]MAIN[0][14]MAIN[0][16]
IOI[1].MUX_TMAIN[0][24]MAIN[0][20]MAIN[0][25]MAIN[0][23]
IOI[2].MUX_TMAIN[0][55]MAIN[0][59]MAIN[0][54]MAIN[0][56]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100

Bel wires

spartan3 IOI_S3 bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_SR_OPTINV[0]IOI[0].SR
IMUX_SR_OPTINV[1]IOI[1].SR
IMUX_SR_OPTINV[2]IOI[2].SR
IMUX_CE_OPTINV[0]IOI[0].OCE
IMUX_CE_OPTINV[1]IOI[1].OCE
IMUX_CE_OPTINV[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3 rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: MUX_T bit 2
B58 - - - - - - - - - - - - - - - - - IOI[2]: FFO2_LATCH IOI[2]: FFT2_LATCH
B57 - - - - - - - - - - - - - - - IOI[2]: !invert TCE - IOI[2]: FFO1_LATCH IOI[2]: FFT1_LATCH
B56 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 IOI[2]: ! FFI2_SRVAL bit 0 IOI[2]: MUX_O bit 0 IOI[2]: MUX_T bit 0
B55 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: MUX_O bit 3 IOI[2]: MUX_T bit 3
B54 - - - - - - - - - - - - - - - IOI[2]: !invert ICE - IOI[2]: MUX_O bit 1 IOI[2]: MUX_T bit 1
B53 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - IOI[2]: FFO_SR_SYNC IOI[2]: FFT_SR_SYNC
B52 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: invert O1 IOI[2]: invert T1
B51 - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFI_LATCH IOI[2]: invert O2 IOI[2]: invert T2
B50 - - - - - - - - - - - - - - - IOI[2]: I_DELAY_ENABLE IOI[2]: FFI_SR_ENABLE IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE
B49 - - - - - - - - - - - - - - - - IOI[2]: FFI_REV_ENABLE IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE
B48 - - - - - - - - - - - - - - - - IOI[2]: FFI_SR_SYNC IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0
B47 - - - - - - - - - - - - - - - IOI[2]: I_TSBYPASS_ENABLE IOI[2]: ! FFI1_INIT bit 0 - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 IOI[2]: ! FFT2_SRVAL bit 0
B44 - - - - - - - - - - - - - - - IOI[2]: MUX_TSBYPASS bit 0 - - -
B43 - - - - - - - - - - - - - - - IOI[2]: IQ_TSBYPASS_ENABLE IOI[2]: ! FFI1_SRVAL bit 0 IOI[2]: ! FFO1_SRVAL bit 0 IOI[2]: ! FFT1_SRVAL bit 0
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - IOI[2]: IQ_DELAY_ENABLE - - -
B40 - - - - - - - - - - - - - - - IOI[2]: READBACK_I bit 0 - - -
B39 - - - - - - - - - - - - - - - IOI[1]: READBACK_I bit 0 - - -
B38 - - - - - - - - - - - - - - - IOI[1]: IQ_DELAY_ENABLE - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - IOI[1]: IQ_TSBYPASS_ENABLE IOI[1]: ! FFI1_SRVAL bit 0 IOI[1]: ! FFO1_SRVAL bit 0 IOI[1]: ! FFT1_SRVAL bit 0
B35 - - - - - - - - - - - - - - - IOI[1]: MUX_TSBYPASS bit 0 - - -
B34 - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 IOI[1]: ! FFT2_SRVAL bit 0
B33 - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - IOI[1]: I_TSBYPASS_ENABLE IOI[1]: ! FFI1_INIT bit 0 - -
B31 - - - - - - - - - - - - - - - - IOI[1]: FFI_SR_SYNC IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0
B30 - - - - - - - - - - - - - - - - IOI[1]: FFI_REV_ENABLE IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE
B29 - - - - - - - - - - - - - - - IOI[1]: I_DELAY_ENABLE IOI[1]: FFI_SR_ENABLE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE
B28 - - - - - - - - - - - - - - - IOI[1]: !invert REV IOI[1]: FFI_LATCH IOI[1]: invert O2 IOI[1]: invert T2
B27 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: invert O1 IOI[1]: invert T1
B26 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - IOI[1]: FFO_SR_SYNC IOI[1]: FFT_SR_SYNC
B25 - - - - - - - - - - - - - - - IOI[1]: !invert ICE - IOI[1]: MUX_O bit 1 IOI[1]: MUX_T bit 1
B24 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: MUX_O bit 3 IOI[1]: MUX_T bit 3
B23 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 IOI[1]: ! FFI2_SRVAL bit 0 IOI[1]: MUX_O bit 0 IOI[1]: MUX_T bit 0
B22 - - - - - - - - - - - - - - - IOI[1]: !invert TCE - IOI[1]: FFO1_LATCH IOI[1]: FFT1_LATCH
B21 - - - - - - - - - - - - - - - - - IOI[1]: FFO2_LATCH IOI[1]: FFT2_LATCH
B20 - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: MUX_T bit 2
B19 - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 IOI[0]: MUX_T bit 2
B18 - - - - - - - - - - - - - - - - - IOI[0]: FFO2_LATCH IOI[0]: FFT2_LATCH
B17 - - - - - - - - - - - - - - - IOI[0]: !invert TCE - IOI[0]: FFO1_LATCH IOI[0]: FFT1_LATCH
B16 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 IOI[0]: ! FFI2_SRVAL bit 0 IOI[0]: MUX_O bit 0 IOI[0]: MUX_T bit 0
B15 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: MUX_O bit 3 IOI[0]: MUX_T bit 3
B14 - - - - - - - - - - - - - - - IOI[0]: !invert ICE - IOI[0]: MUX_O bit 1 IOI[0]: MUX_T bit 1
B13 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - IOI[0]: FFO_SR_SYNC IOI[0]: FFT_SR_SYNC
B12 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: invert O1 IOI[0]: invert T1
B11 - - - - - - - - - - - - - - - IOI[0]: !invert REV IOI[0]: FFI_LATCH IOI[0]: invert O2 IOI[0]: invert T2
B10 - - - - - - - - - - - - - - - IOI[0]: I_DELAY_ENABLE IOI[0]: FFI_SR_ENABLE IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE
B9 - - - - - - - - - - - - - - - - IOI[0]: FFI_REV_ENABLE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE
B8 - - - - - - - - - - - - - - - - IOI[0]: FFI_SR_SYNC IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0
B7 - - - - - - - - - - - - - - - IOI[0]: I_TSBYPASS_ENABLE IOI[0]: ! FFI1_INIT bit 0 - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 IOI[0]: ! FFT2_SRVAL bit 0
B4 - - - - - - - - - - - - - - - IOI[0]: MUX_TSBYPASS bit 0 - - -
B3 - - - - - - - - - - - - - - - IOI[0]: IQ_TSBYPASS_ENABLE IOI[0]: ! FFI1_SRVAL bit 0 IOI[0]: ! FFO1_SRVAL bit 0 IOI[0]: ! FFT1_SRVAL bit 0
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - IOI[0]: IQ_DELAY_ENABLE - - -
B0 - - - - - - - - - - - - - - - IOI[0]: READBACK_I bit 0 - - -

Tile IOI_FC

Cells: 1

Bels IREG

spartan3 IOI_FC bel IREG pins
PinDirectionIREG[0]IREG[1]IREG[2]IREG[3]
CLKinIMUX_IOCLK[0] invert by !MAIN[3][11]IMUX_IOCLK[2] invert by !MAIN[3][21]IMUX_IOCLK[4] invert by !MAIN[3][43]IMUX_IOCLK[6] invert by !MAIN[3][53]
SRinIMUX_DATA[12] invert by !MAIN[3][15]IMUX_DATA[13] invert by !MAIN[3][16]IMUX_DATA[14] invert by !MAIN[3][47]IMUX_DATA[15] invert by !MAIN[3][48]
REVinIMUX_DATA[0] invert by !MAIN[3][7]IMUX_DATA[1] invert by !MAIN[3][24]IMUX_DATA[2] invert by !MAIN[3][39]IMUX_DATA[3] invert by !MAIN[3][56]
CEinIMUX_DATA[8] invert by !MAIN[3][12]IMUX_DATA[9] invert by !MAIN[3][19]IMUX_DATA[10] invert by !MAIN[3][44]IMUX_DATA[11] invert by !MAIN[3][51]
IoutOUT_FAN[4]OUT_FAN[5]OUT_FAN[6]OUT_FAN[7]
IQoutOUT_SEC[8]OUT_SEC[9]OUT_SEC[10]OUT_SEC[11]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]--
spartan3 IOI_FC bel IREG attribute bits
AttributeIREG[0]IREG[1]IREG[2]IREG[3]
FF_INIT bit 0!MAIN[2][6]!MAIN[2][22]!MAIN[2][38]!MAIN[2][54]
FF_SRVAL bit 0!MAIN[2][3]!MAIN[2][19]!MAIN[2][35]!MAIN[2][51]
FF_LATCHMAIN[2][8]MAIN[2][23]MAIN[2][40]MAIN[2][55]
FF_SR_SYNCMAIN[2][15]MAIN[2][16]MAIN[2][47]MAIN[2][48]
FF_SR_ENABLEMAIN[2][11]MAIN[2][20]MAIN[2][43]MAIN[2][52]
FF_REV_ENABLEMAIN[2][10]MAIN[2][21]MAIN[2][42]MAIN[2][53]
O2I_ENABLEMAIN[3][6]MAIN[3][25]MAIN[3][38]MAIN[3][57]
O2IQ_ENABLEMAIN[3][2]MAIN[3][29]MAIN[3][34]MAIN[3][61]
O2I_O2IQ_ENABLEMAIN[3][4]MAIN[3][27]MAIN[3][36]MAIN[3][59]
I_DELAY_ENABLEMAIN[3][8]MAIN[3][23]MAIN[3][40]MAIN[3][55]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][30]MAIN[3][33]MAIN[3][62]
DELAY_ENABLE bit 0MAIN[0][0]MAIN[0][23]MAIN[0][32]MAIN[0][55]
DELAY_ENABLE bit 1MAIN[0][1]MAIN[0][25]MAIN[0][33]MAIN[0][57]
DELAY_ENABLE bit 2MAIN[0][2]MAIN[0][26]MAIN[0][34]MAIN[0][58]
DELAY_ENABLE bit 3MAIN[0][3]MAIN[0][27]MAIN[0][35]MAIN[0][59]
DELAY_ENABLE bit 4MAIN[0][4]MAIN[0][28]MAIN[0][36]MAIN[0][60]
DELAY_ENABLE bit 5MAIN[0][5]MAIN[0][29]MAIN[0][37]MAIN[0][61]
DELAY_ENABLE bit 6MAIN[0][6]MAIN[0][30]MAIN[0][38]MAIN[0][62]
DELAY_ENABLE bit 7MAIN[0][8]MAIN[0][31]MAIN[0][40]MAIN[0][63]
DELAY_ENABLE bit 8MAIN[1][1]MAIN[1][29]MAIN[1][33]MAIN[1][61]
DELAY_ENABLE bit 9MAIN[1][2]MAIN[1][30]MAIN[1][34]MAIN[1][62]
DELAY_ENABLE bit 10MAIN[2][0]MAIN[2][26]MAIN[2][32]MAIN[2][58]
DELAY_ENABLE bit 11MAIN[2][1]MAIN[2][30]MAIN[2][33]MAIN[2][62]
DELAY_ENABLE bit 12MAIN[2][5]MAIN[2][31]MAIN[2][37]MAIN[2][63]
DELAY_ENABLE bit 13MAIN[3][5]MAIN[3][26]MAIN[3][37]MAIN[3][58]
READBACK_I bit 0MAIN[3][0]MAIN[3][31]MAIN[3][32]MAIN[3][63]

Bels OREG

spartan3 IOI_FC bel OREG pins
PinDirectionOREG[0]OREG[1]OREG[2]OREG[3]
OinIMUX_DATA[24] invert by MAIN[1][0]IMUX_DATA[25] invert by MAIN[1][26]IMUX_DATA[26] invert by MAIN[1][32]IMUX_DATA[27] invert by MAIN[1][58]
CLKinIMUX_IOCLK[1] invert by !MAIN[3][14]IMUX_IOCLK[3] invert by !MAIN[3][18]IMUX_IOCLK[5] invert by !MAIN[3][46]IMUX_IOCLK[7] invert by !MAIN[3][50]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[2]IMUX_SR_OPTINV[3]
REVinIMUX_DATA[4] invert by !MAIN[3][9]IMUX_DATA[5] invert by !MAIN[3][22]IMUX_DATA[6] invert by !MAIN[3][41]IMUX_DATA[7] invert by !MAIN[3][54]
CEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]IMUX_CE_OPTINV[2]IMUX_CE_OPTINV[3]
spartan3 IOI_FC bel OREG attribute bits
AttributeOREG[0]OREG[1]OREG[2]OREG[3]
FF_INIT bit 0!MAIN[1][7]!MAIN[1][24]!MAIN[1][39]!MAIN[1][56]
FF_SRVAL bit 0!MAIN[1][3]!MAIN[1][27]!MAIN[1][35]!MAIN[1][59]
FF_LATCHMAIN[1][14]MAIN[1][18]MAIN[1][46]MAIN[1][50]
FF_SR_SYNCMAIN[1][11]MAIN[1][20]MAIN[1][43]MAIN[1][52]
FF_SR_ENABLEMAIN[1][10]MAIN[1][21]MAIN[1][42]MAIN[1][53]
FF_REV_ENABLEMAIN[1][9]MAIN[1][22]MAIN[1][41]MAIN[1][54]
MUX_O[enum: OREG_MUX_O][enum: OREG_MUX_O][enum: OREG_MUX_O][enum: OREG_MUX_O]
spartan3 IOI_FC enum OREG_MUX_O
OREG[0].MUX_OMAIN[1][15]MAIN[1][12]
OREG[1].MUX_OMAIN[1][25]MAIN[1][23]
OREG[2].MUX_OMAIN[1][47]MAIN[1][44]
OREG[3].MUX_OMAIN[1][57]MAIN[1][55]
NONE00
O01
OQ10

Bel wires

spartan3 IOI_FC bel wires
WirePins
OUT_CLKPAD[0]IREG[0].CLKPAD
OUT_CLKPAD[1]IREG[1].CLKPAD
IMUX_SR_OPTINV[0]OREG[0].SR
IMUX_SR_OPTINV[1]OREG[1].SR
IMUX_SR_OPTINV[2]OREG[2].SR
IMUX_SR_OPTINV[3]OREG[3].SR
IMUX_CE_OPTINV[0]OREG[0].CE
IMUX_CE_OPTINV[1]OREG[1].CE
IMUX_CE_OPTINV[2]OREG[2].CE
IMUX_CE_OPTINV[3]OREG[3].CE
IMUX_IOCLK[0]IREG[0].CLK
IMUX_IOCLK[1]OREG[0].CLK
IMUX_IOCLK[2]IREG[1].CLK
IMUX_IOCLK[3]OREG[1].CLK
IMUX_IOCLK[4]IREG[2].CLK
IMUX_IOCLK[5]OREG[2].CLK
IMUX_IOCLK[6]IREG[3].CLK
IMUX_IOCLK[7]OREG[3].CLK
IMUX_DATA[0]IREG[0].REV
IMUX_DATA[1]IREG[1].REV
IMUX_DATA[2]IREG[2].REV
IMUX_DATA[3]IREG[3].REV
IMUX_DATA[4]OREG[0].REV
IMUX_DATA[5]OREG[1].REV
IMUX_DATA[6]OREG[2].REV
IMUX_DATA[7]OREG[3].REV
IMUX_DATA[8]IREG[0].CE
IMUX_DATA[9]IREG[1].CE
IMUX_DATA[10]IREG[2].CE
IMUX_DATA[11]IREG[3].CE
IMUX_DATA[12]IREG[0].SR
IMUX_DATA[13]IREG[1].SR
IMUX_DATA[14]IREG[2].SR
IMUX_DATA[15]IREG[3].SR
IMUX_DATA[24]OREG[0].O
IMUX_DATA[25]OREG[1].O
IMUX_DATA[26]OREG[2].O
IMUX_DATA[27]OREG[3].O
OUT_FAN[4]IREG[0].I
OUT_FAN[5]IREG[1].I
OUT_FAN[6]IREG[2].I
OUT_FAN[7]IREG[3].I
OUT_SEC[8]IREG[0].IQ
OUT_SEC[9]IREG[1].IQ
OUT_SEC[10]IREG[2].IQ
OUT_SEC[11]IREG[3].IQ

Bitstream

spartan3 IOI_FC rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - IREG[3]: READBACK_I bit 0 IREG[3]: DELAY_ENABLE bit 12 - IREG[3]: DELAY_ENABLE bit 7
B62 - - - - - - - - - - - - - - - IREG[3]: IQ_DELAY_ENABLE IREG[3]: DELAY_ENABLE bit 11 IREG[3]: DELAY_ENABLE bit 9 IREG[3]: DELAY_ENABLE bit 6
B61 - - - - - - - - - - - - - - - IREG[3]: O2IQ_ENABLE - IREG[3]: DELAY_ENABLE bit 8 IREG[3]: DELAY_ENABLE bit 5
B60 - - - - - - - - - - - - - - - - - - IREG[3]: DELAY_ENABLE bit 4
B59 - - - - - - - - - - - - - - - IREG[3]: O2I_O2IQ_ENABLE - OREG[3]: ! FF_SRVAL bit 0 IREG[3]: DELAY_ENABLE bit 3
B58 - - - - - - - - - - - - - - - IREG[3]: DELAY_ENABLE bit 13 IREG[3]: DELAY_ENABLE bit 10 OREG[3]: invert O IREG[3]: DELAY_ENABLE bit 2
B57 - - - - - - - - - - - - - - - IREG[3]: O2I_ENABLE - OREG[3]: MUX_O bit 1 IREG[3]: DELAY_ENABLE bit 1
B56 - - - - - - - - - - - - - - - IREG[3]: !invert REV - OREG[3]: ! FF_INIT bit 0 -
B55 - - - - - - - - - - - - - - - IREG[3]: I_DELAY_ENABLE IREG[3]: FF_LATCH OREG[3]: MUX_O bit 0 IREG[3]: DELAY_ENABLE bit 0
B54 - - - - - - - - - - - - - - - OREG[3]: !invert REV IREG[3]: ! FF_INIT bit 0 OREG[3]: FF_REV_ENABLE -
B53 - - - - - - - - - - - - - - - IREG[3]: !invert CLK IREG[3]: FF_REV_ENABLE OREG[3]: FF_SR_ENABLE -
B52 - - - - - - - - - - - - - - - - IREG[3]: FF_SR_ENABLE OREG[3]: FF_SR_SYNC -
B51 - - - - - - - - - - - - - - - IREG[3]: !invert CE IREG[3]: ! FF_SRVAL bit 0 - -
B50 - - - - - - - - - - - - - - - OREG[3]: !invert CLK - OREG[3]: FF_LATCH -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - IREG[3]: !invert SR IREG[3]: FF_SR_SYNC - -
B47 - - - - - - - - - - - - - - - IREG[2]: !invert SR IREG[2]: FF_SR_SYNC OREG[2]: MUX_O bit 1 -
B46 - - - - - - - - - - - - - - - OREG[2]: !invert CLK - OREG[2]: FF_LATCH -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - IREG[2]: !invert CE - OREG[2]: MUX_O bit 0 -
B43 - - - - - - - - - - - - - - - IREG[2]: !invert CLK IREG[2]: FF_SR_ENABLE OREG[2]: FF_SR_SYNC -
B42 - - - - - - - - - - - - - - - - IREG[2]: FF_REV_ENABLE OREG[2]: FF_SR_ENABLE -
B41 - - - - - - - - - - - - - - - OREG[2]: !invert REV - OREG[2]: FF_REV_ENABLE -
B40 - - - - - - - - - - - - - - - IREG[2]: I_DELAY_ENABLE IREG[2]: FF_LATCH - IREG[2]: DELAY_ENABLE bit 7
B39 - - - - - - - - - - - - - - - IREG[2]: !invert REV - OREG[2]: ! FF_INIT bit 0 -
B38 - - - - - - - - - - - - - - - IREG[2]: O2I_ENABLE IREG[2]: ! FF_INIT bit 0 - IREG[2]: DELAY_ENABLE bit 6
B37 - - - - - - - - - - - - - - - IREG[2]: DELAY_ENABLE bit 13 IREG[2]: DELAY_ENABLE bit 12 - IREG[2]: DELAY_ENABLE bit 5
B36 - - - - - - - - - - - - - - - IREG[2]: O2I_O2IQ_ENABLE - - IREG[2]: DELAY_ENABLE bit 4
B35 - - - - - - - - - - - - - - - - IREG[2]: ! FF_SRVAL bit 0 OREG[2]: ! FF_SRVAL bit 0 IREG[2]: DELAY_ENABLE bit 3
B34 - - - - - - - - - - - - - - - IREG[2]: O2IQ_ENABLE - IREG[2]: DELAY_ENABLE bit 9 IREG[2]: DELAY_ENABLE bit 2
B33 - - - - - - - - - - - - - - - IREG[2]: IQ_DELAY_ENABLE IREG[2]: DELAY_ENABLE bit 11 IREG[2]: DELAY_ENABLE bit 8 IREG[2]: DELAY_ENABLE bit 1
B32 - - - - - - - - - - - - - - - IREG[2]: READBACK_I bit 0 IREG[2]: DELAY_ENABLE bit 10 OREG[2]: invert O IREG[2]: DELAY_ENABLE bit 0
B31 - - - - - - - - - - - - - - - IREG[1]: READBACK_I bit 0 IREG[1]: DELAY_ENABLE bit 12 - IREG[1]: DELAY_ENABLE bit 7
B30 - - - - - - - - - - - - - - - IREG[1]: IQ_DELAY_ENABLE IREG[1]: DELAY_ENABLE bit 11 IREG[1]: DELAY_ENABLE bit 9 IREG[1]: DELAY_ENABLE bit 6
B29 - - - - - - - - - - - - - - - IREG[1]: O2IQ_ENABLE - IREG[1]: DELAY_ENABLE bit 8 IREG[1]: DELAY_ENABLE bit 5
B28 - - - - - - - - - - - - - - - - - - IREG[1]: DELAY_ENABLE bit 4
B27 - - - - - - - - - - - - - - - IREG[1]: O2I_O2IQ_ENABLE - OREG[1]: ! FF_SRVAL bit 0 IREG[1]: DELAY_ENABLE bit 3
B26 - - - - - - - - - - - - - - - IREG[1]: DELAY_ENABLE bit 13 IREG[1]: DELAY_ENABLE bit 10 OREG[1]: invert O IREG[1]: DELAY_ENABLE bit 2
B25 - - - - - - - - - - - - - - - IREG[1]: O2I_ENABLE - OREG[1]: MUX_O bit 1 IREG[1]: DELAY_ENABLE bit 1
B24 - - - - - - - - - - - - - - - IREG[1]: !invert REV - OREG[1]: ! FF_INIT bit 0 -
B23 - - - - - - - - - - - - - - - IREG[1]: I_DELAY_ENABLE IREG[1]: FF_LATCH OREG[1]: MUX_O bit 0 IREG[1]: DELAY_ENABLE bit 0
B22 - - - - - - - - - - - - - - - OREG[1]: !invert REV IREG[1]: ! FF_INIT bit 0 OREG[1]: FF_REV_ENABLE -
B21 - - - - - - - - - - - - - - - IREG[1]: !invert CLK IREG[1]: FF_REV_ENABLE OREG[1]: FF_SR_ENABLE -
B20 - - - - - - - - - - - - - - - - IREG[1]: FF_SR_ENABLE OREG[1]: FF_SR_SYNC -
B19 - - - - - - - - - - - - - - - IREG[1]: !invert CE IREG[1]: ! FF_SRVAL bit 0 - -
B18 - - - - - - - - - - - - - - - OREG[1]: !invert CLK - OREG[1]: FF_LATCH -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - IREG[1]: !invert SR IREG[1]: FF_SR_SYNC - -
B15 - - - - - - - - - - - - - - - IREG[0]: !invert SR IREG[0]: FF_SR_SYNC OREG[0]: MUX_O bit 1 -
B14 - - - - - - - - - - - - - - - OREG[0]: !invert CLK - OREG[0]: FF_LATCH -
B13 - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - IREG[0]: !invert CE - OREG[0]: MUX_O bit 0 -
B11 - - - - - - - - - - - - - - - IREG[0]: !invert CLK IREG[0]: FF_SR_ENABLE OREG[0]: FF_SR_SYNC -
B10 - - - - - - - - - - - - - - - - IREG[0]: FF_REV_ENABLE OREG[0]: FF_SR_ENABLE -
B9 - - - - - - - - - - - - - - - OREG[0]: !invert REV - OREG[0]: FF_REV_ENABLE -
B8 - - - - - - - - - - - - - - - IREG[0]: I_DELAY_ENABLE IREG[0]: FF_LATCH - IREG[0]: DELAY_ENABLE bit 7
B7 - - - - - - - - - - - - - - - IREG[0]: !invert REV - OREG[0]: ! FF_INIT bit 0 -
B6 - - - - - - - - - - - - - - - IREG[0]: O2I_ENABLE IREG[0]: ! FF_INIT bit 0 - IREG[0]: DELAY_ENABLE bit 6
B5 - - - - - - - - - - - - - - - IREG[0]: DELAY_ENABLE bit 13 IREG[0]: DELAY_ENABLE bit 12 - IREG[0]: DELAY_ENABLE bit 5
B4 - - - - - - - - - - - - - - - IREG[0]: O2I_O2IQ_ENABLE - - IREG[0]: DELAY_ENABLE bit 4
B3 - - - - - - - - - - - - - - - - IREG[0]: ! FF_SRVAL bit 0 OREG[0]: ! FF_SRVAL bit 0 IREG[0]: DELAY_ENABLE bit 3
B2 - - - - - - - - - - - - - - - IREG[0]: O2IQ_ENABLE - IREG[0]: DELAY_ENABLE bit 9 IREG[0]: DELAY_ENABLE bit 2
B1 - - - - - - - - - - - - - - - IREG[0]: IQ_DELAY_ENABLE IREG[0]: DELAY_ENABLE bit 11 IREG[0]: DELAY_ENABLE bit 8 IREG[0]: DELAY_ENABLE bit 1
B0 - - - - - - - - - - - - - - - IREG[0]: READBACK_I bit 0 IREG[0]: DELAY_ENABLE bit 10 OREG[0]: invert O IREG[0]: DELAY_ENABLE bit 0

Tile IOI_S3E

Cells: 1

Bels IOI

spartan3 IOI_S3E bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]
ICLK1inIMUX_IOCLK[0] invert by !MAIN[3][13]IMUX_IOCLK[0] invert by !MAIN[3][26]IMUX_IOCLK[2] invert by !MAIN[3][53]
ICLK2inIMUX_IOCLK[4] invert by !MAIN[3][12]IMUX_IOCLK[4] invert by !MAIN[3][27]IMUX_IOCLK[6] invert by !MAIN[3][52]
ICEinIMUX_DATA[8] invert by !MAIN[3][14]IMUX_DATA[9] invert by !MAIN[3][25]IMUX_DATA[10] invert by !MAIN[3][54]
O1inIMUX_DATA[24] invert by MAIN[1][12]IMUX_DATA[25] invert by MAIN[1][27]IMUX_DATA[26] invert by MAIN[1][52]
O2inIMUX_DATA[28] invert by MAIN[1][11]IMUX_DATA[29] invert by MAIN[1][28]IMUX_DATA[30] invert by MAIN[1][51]
T1inIMUX_DATA[16] invert by MAIN[0][12]IMUX_DATA[17] invert by MAIN[0][27]IMUX_DATA[18] invert by MAIN[0][52]
T2inIMUX_DATA[20] invert by MAIN[0][11]IMUX_DATA[21] invert by MAIN[0][28]IMUX_DATA[22] invert by MAIN[0][51]
OTCLK1inIMUX_IOCLK[1] invert by !MAIN[3][16]IMUX_IOCLK[1] invert by !MAIN[3][23]IMUX_IOCLK[3] invert by !MAIN[3][56]
OTCLK2inIMUX_IOCLK[5] invert by !MAIN[3][15]IMUX_IOCLK[5] invert by !MAIN[3][24]IMUX_IOCLK[7] invert by !MAIN[3][55]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]IMUX_CE_OPTINV[2]
TCEinIMUX_DATA[4] invert by !MAIN[3][17]IMUX_DATA[5] invert by !MAIN[3][22]IMUX_DATA[6] invert by !MAIN[3][57]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[2]
REVinIMUX_DATA[0] invert by !MAIN[3][11]IMUX_DATA[1] invert by !MAIN[3][28]IMUX_DATA[2] invert by !MAIN[3][51]
IoutOUT_FAN[4]OUT_FAN[5]OUT_FAN[6]
IQ1outOUT_SEC[8]OUT_SEC[9]OUT_SEC[10]
IQ2outOUT_SEC[12]OUT_SEC[13]OUT_SEC[14]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]-
ToutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]
spartan3 IOI_S3E bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]
FFI1_INIT bit 0!MAIN[2][7]!MAIN[2][32]!MAIN[2][47]
FFI2_INIT bit 0!MAIN[2][12]!MAIN[2][27]!MAIN[2][52]
FFI1_SRVAL bit 0!MAIN[2][3]!MAIN[2][36]!MAIN[2][43]
FFI2_SRVAL bit 0!MAIN[2][16]!MAIN[2][23]!MAIN[2][56]
FFI_LATCHMAIN[2][11]MAIN[2][28]MAIN[2][51]
FFI_SR_SYNCMAIN[2][8]MAIN[2][31]MAIN[2][48]
FFI_SR_ENABLEMAIN[2][10]MAIN[2][29]MAIN[2][50]
FFI_REV_ENABLEMAIN[2][9]MAIN[2][30]MAIN[2][49]
I_DELAY_ENABLEMAIN[3][10]MAIN[3][29]MAIN[3][50]
I_TSBYPASS_ENABLEMAIN[3][7]MAIN[3][32]MAIN[3][47]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][38]MAIN[3][41]
IQ_TSBYPASS_ENABLEMAIN[3][3]MAIN[3][36]MAIN[3][43]
READBACK_I bit 0MAIN[3][0]MAIN[3][39]MAIN[3][40]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
MUX_FFI[enum: IOI_MUX_FFI][enum: IOI_MUX_FFI][enum: IOI_MUX_FFI]
FFO_INIT bit 0!MAIN[1][8]!MAIN[1][31]!MAIN[1][48]
FFO1_SRVAL bit 0!MAIN[1][3]!MAIN[1][36]!MAIN[1][43]
FFO2_SRVAL bit 0!MAIN[1][5]!MAIN[1][34]!MAIN[1][45]
FFO1_LATCHMAIN[1][17]MAIN[1][22]MAIN[1][57]
FFO2_LATCHMAIN[1][18]MAIN[1][21]MAIN[1][58]
FFO_SR_SYNCMAIN[1][13]MAIN[1][26]MAIN[1][53]
FFO_SR_ENABLEMAIN[1][10]MAIN[1][29]MAIN[1][50]
FFO_REV_ENABLEMAIN[1][9]MAIN[1][30]MAIN[1][49]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O]
MUX_OCE[enum: IOI_MUX_OCE][enum: IOI_MUX_OCE][enum: IOI_MUX_OCE]
MUX_FFO1[enum: IOI_MUX_FFO1][enum: IOI_MUX_FFO1]-
MUX_FFO2[enum: IOI_MUX_FFO2][enum: IOI_MUX_FFO2]-
FFT_INIT bit 0!MAIN[0][8]!MAIN[0][31]!MAIN[0][48]
FFT1_SRVAL bit 0!MAIN[0][3]!MAIN[0][36]!MAIN[0][43]
FFT2_SRVAL bit 0!MAIN[0][5]!MAIN[0][34]!MAIN[0][45]
FFT1_LATCHMAIN[0][17]MAIN[0][22]MAIN[0][57]
FFT2_LATCHMAIN[0][18]MAIN[0][21]MAIN[0][58]
FFT_SR_SYNCMAIN[0][13]MAIN[0][26]MAIN[0][53]
FFT_SR_ENABLEMAIN[0][10]MAIN[0][29]MAIN[0][50]
FFT_REV_ENABLEMAIN[0][9]MAIN[0][30]MAIN[0][49]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T]
MUX_MISR_CLOCK[enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK]
MISR_ENABLEMAIN[0][6]MAIN[0][33]MAIN[0][46]
MISR_RESETMAIN[0][7]MAIN[0][32]MAIN[0][47]
spartan3 IOI_S3E enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[3][4]
IOI[1].MUX_TSBYPASSMAIN[3][35]
IOI[2].MUX_TSBYPASSMAIN[3][44]
GND1
T0
spartan3 IOI_S3E enum IOI_MUX_FFI
IOI[0].MUX_FFIMAIN[3][21]MAIN[3][37]MAIN[3][8]
IOI[1].MUX_FFIMAIN[3][18]MAIN[3][2]MAIN[3][30]
IOI[2].MUX_FFIMAIN[3][58]MAIN[3][42]MAIN[3][48]
NONE000
IBUF001
PAIR_IQ1010
PAIR_IQ2100
spartan3 IOI_S3E enum IOI_MUX_O
IOI[0].MUX_OMAIN[1][15]MAIN[1][19]MAIN[1][14]MAIN[1][16]
IOI[1].MUX_OMAIN[1][24]MAIN[1][20]MAIN[1][25]MAIN[1][23]
IOI[2].MUX_OMAIN[1][55]MAIN[1][59]MAIN[1][54]MAIN[1][56]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
spartan3 IOI_S3E enum IOI_MUX_OCE
IOI[0].MUX_OCEMAIN[2][0]MAIN[1][0]
IOI[1].MUX_OCEMAIN[2][39]MAIN[1][39]
IOI[2].MUX_OCEMAIN[2][40]MAIN[1][40]
NONE00
OCE01
PCI_CE10
spartan3 IOI_S3E enum IOI_MUX_FFO1
IOI[0].MUX_FFO1MAIN[1][35]
IOI[1].MUX_FFO1MAIN[1][4]
O10
PAIR_FFO21
spartan3 IOI_S3E enum IOI_MUX_FFO2
IOI[0].MUX_FFO2MAIN[0][37]
IOI[1].MUX_FFO2MAIN[0][2]
O20
PAIR_FFO11
spartan3 IOI_S3E enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][15]MAIN[0][19]MAIN[0][14]MAIN[0][16]
IOI[1].MUX_TMAIN[0][24]MAIN[0][20]MAIN[0][25]MAIN[0][23]
IOI[2].MUX_TMAIN[0][55]MAIN[0][59]MAIN[0][54]MAIN[0][56]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100
spartan3 IOI_S3E enum IOI_MUX_MISR_CLOCK
IOI[0].MUX_MISR_CLOCKMAIN[0][1]MAIN[0][0]
IOI[1].MUX_MISR_CLOCKMAIN[0][38]MAIN[0][39]
IOI[2].MUX_MISR_CLOCKMAIN[0][41]MAIN[0][40]
NONE00
OTCLK101
OTCLK210

Bel wires

spartan3 IOI_S3E bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_SR_OPTINV[0]IOI[0].SR
IMUX_SR_OPTINV[1]IOI[1].SR
IMUX_SR_OPTINV[2]IOI[2].SR
IMUX_CE_OPTINV[0]IOI[0].OCE
IMUX_CE_OPTINV[1]IOI[1].OCE
IMUX_CE_OPTINV[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3E rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: MUX_T bit 2
B58 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 2 - IOI[2]: FFO2_LATCH IOI[2]: FFT2_LATCH
B57 - - - - - - - - - - - - - - - IOI[2]: !invert TCE - IOI[2]: FFO1_LATCH IOI[2]: FFT1_LATCH
B56 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 IOI[2]: ! FFI2_SRVAL bit 0 IOI[2]: MUX_O bit 0 IOI[2]: MUX_T bit 0
B55 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: MUX_O bit 3 IOI[2]: MUX_T bit 3
B54 - - - - - - - - - - - - - - - IOI[2]: !invert ICE - IOI[2]: MUX_O bit 1 IOI[2]: MUX_T bit 1
B53 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - IOI[2]: FFO_SR_SYNC IOI[2]: FFT_SR_SYNC
B52 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: invert O1 IOI[2]: invert T1
B51 - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFI_LATCH IOI[2]: invert O2 IOI[2]: invert T2
B50 - - - - - - - - - - - - - - - IOI[2]: I_DELAY_ENABLE IOI[2]: FFI_SR_ENABLE IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE
B49 - - - - - - - - - - - - - - - - IOI[2]: FFI_REV_ENABLE IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE
B48 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 0 IOI[2]: FFI_SR_SYNC IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0
B47 - - - - - - - - - - - - - - - IOI[2]: I_TSBYPASS_ENABLE IOI[2]: ! FFI1_INIT bit 0 - IOI[2]: MISR_RESET
B46 - - - - - - - - - - - - - - - - - - IOI[2]: MISR_ENABLE
B45 - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 IOI[2]: ! FFT2_SRVAL bit 0
B44 - - - - - - - - - - - - - - - IOI[2]: MUX_TSBYPASS bit 0 - - -
B43 - - - - - - - - - - - - - - - IOI[2]: IQ_TSBYPASS_ENABLE IOI[2]: ! FFI1_SRVAL bit 0 IOI[2]: ! FFO1_SRVAL bit 0 IOI[2]: ! FFT1_SRVAL bit 0
B42 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 1 - - -
B41 - - - - - - - - - - - - - - - IOI[2]: IQ_DELAY_ENABLE - - IOI[2]: MUX_MISR_CLOCK bit 1
B40 - - - - - - - - - - - - - - - IOI[2]: READBACK_I bit 0 IOI[2]: MUX_OCE bit 1 IOI[2]: MUX_OCE bit 0 IOI[2]: MUX_MISR_CLOCK bit 0
B39 - - - - - - - - - - - - - - - IOI[1]: READBACK_I bit 0 IOI[1]: MUX_OCE bit 1 IOI[1]: MUX_OCE bit 0 IOI[1]: MUX_MISR_CLOCK bit 0
B38 - - - - - - - - - - - - - - - IOI[1]: IQ_DELAY_ENABLE - - IOI[1]: MUX_MISR_CLOCK bit 1
B37 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 1 - - IOI[0]: MUX_FFO2 bit 0
B36 - - - - - - - - - - - - - - - IOI[1]: IQ_TSBYPASS_ENABLE IOI[1]: ! FFI1_SRVAL bit 0 IOI[1]: ! FFO1_SRVAL bit 0 IOI[1]: ! FFT1_SRVAL bit 0
B35 - - - - - - - - - - - - - - - IOI[1]: MUX_TSBYPASS bit 0 - IOI[0]: MUX_FFO1 bit 0 -
B34 - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 IOI[1]: ! FFT2_SRVAL bit 0
B33 - - - - - - - - - - - - - - - - - - IOI[1]: MISR_ENABLE
B32 - - - - - - - - - - - - - - - IOI[1]: I_TSBYPASS_ENABLE IOI[1]: ! FFI1_INIT bit 0 - IOI[1]: MISR_RESET
B31 - - - - - - - - - - - - - - - - IOI[1]: FFI_SR_SYNC IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0
B30 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 0 IOI[1]: FFI_REV_ENABLE IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE
B29 - - - - - - - - - - - - - - - IOI[1]: I_DELAY_ENABLE IOI[1]: FFI_SR_ENABLE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE
B28 - - - - - - - - - - - - - - - IOI[1]: !invert REV IOI[1]: FFI_LATCH IOI[1]: invert O2 IOI[1]: invert T2
B27 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: invert O1 IOI[1]: invert T1
B26 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - IOI[1]: FFO_SR_SYNC IOI[1]: FFT_SR_SYNC
B25 - - - - - - - - - - - - - - - IOI[1]: !invert ICE - IOI[1]: MUX_O bit 1 IOI[1]: MUX_T bit 1
B24 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: MUX_O bit 3 IOI[1]: MUX_T bit 3
B23 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 IOI[1]: ! FFI2_SRVAL bit 0 IOI[1]: MUX_O bit 0 IOI[1]: MUX_T bit 0
B22 - - - - - - - - - - - - - - - IOI[1]: !invert TCE - IOI[1]: FFO1_LATCH IOI[1]: FFT1_LATCH
B21 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 2 - IOI[1]: FFO2_LATCH IOI[1]: FFT2_LATCH
B20 - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: MUX_T bit 2
B19 - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 IOI[0]: MUX_T bit 2
B18 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 2 - IOI[0]: FFO2_LATCH IOI[0]: FFT2_LATCH
B17 - - - - - - - - - - - - - - - IOI[0]: !invert TCE - IOI[0]: FFO1_LATCH IOI[0]: FFT1_LATCH
B16 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 IOI[0]: ! FFI2_SRVAL bit 0 IOI[0]: MUX_O bit 0 IOI[0]: MUX_T bit 0
B15 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: MUX_O bit 3 IOI[0]: MUX_T bit 3
B14 - - - - - - - - - - - - - - - IOI[0]: !invert ICE - IOI[0]: MUX_O bit 1 IOI[0]: MUX_T bit 1
B13 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - IOI[0]: FFO_SR_SYNC IOI[0]: FFT_SR_SYNC
B12 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: invert O1 IOI[0]: invert T1
B11 - - - - - - - - - - - - - - - IOI[0]: !invert REV IOI[0]: FFI_LATCH IOI[0]: invert O2 IOI[0]: invert T2
B10 - - - - - - - - - - - - - - - IOI[0]: I_DELAY_ENABLE IOI[0]: FFI_SR_ENABLE IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE
B9 - - - - - - - - - - - - - - - - IOI[0]: FFI_REV_ENABLE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE
B8 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 0 IOI[0]: FFI_SR_SYNC IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0
B7 - - - - - - - - - - - - - - - IOI[0]: I_TSBYPASS_ENABLE IOI[0]: ! FFI1_INIT bit 0 - IOI[0]: MISR_RESET
B6 - - - - - - - - - - - - - - - - - - IOI[0]: MISR_ENABLE
B5 - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 IOI[0]: ! FFT2_SRVAL bit 0
B4 - - - - - - - - - - - - - - - IOI[0]: MUX_TSBYPASS bit 0 - IOI[1]: MUX_FFO1 bit 0 -
B3 - - - - - - - - - - - - - - - IOI[0]: IQ_TSBYPASS_ENABLE IOI[0]: ! FFI1_SRVAL bit 0 IOI[0]: ! FFO1_SRVAL bit 0 IOI[0]: ! FFT1_SRVAL bit 0
B2 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 1 - - IOI[1]: MUX_FFO2 bit 0
B1 - - - - - - - - - - - - - - - IOI[0]: IQ_DELAY_ENABLE - - IOI[0]: MUX_MISR_CLOCK bit 1
B0 - - - - - - - - - - - - - - - IOI[0]: READBACK_I bit 0 IOI[0]: MUX_OCE bit 1 IOI[0]: MUX_OCE bit 0 IOI[0]: MUX_MISR_CLOCK bit 0

Tile IOI_S3A_WE

Cells: 1

Bels IOI

spartan3 IOI_S3A_WE bel IOI pins
PinDirectionIOI[0]IOI[1]
ICLK1inIMUX_IOCLK[0] invert by !MAIN[3][13]IMUX_IOCLK[0] invert by !MAIN[3][26]
ICLK2inIMUX_IOCLK[4] invert by !MAIN[3][12]IMUX_IOCLK[4] invert by !MAIN[3][27]
ICEinIMUX_DATA[8] invert by !MAIN[3][14]IMUX_DATA[9] invert by !MAIN[3][25]
O1inIMUX_DATA[24] invert by MAIN[1][12]IMUX_DATA[25] invert by MAIN[1][27]
O2inIMUX_DATA[28] invert by MAIN[1][11]IMUX_DATA[29] invert by MAIN[1][28]
T1inIMUX_DATA[16] invert by MAIN[0][12]IMUX_DATA[17] invert by MAIN[0][27]
T2inIMUX_DATA[20] invert by MAIN[0][11]IMUX_DATA[21] invert by MAIN[0][28]
OTCLK1inIMUX_IOCLK[1] invert by !MAIN[3][16]IMUX_IOCLK[1] invert by !MAIN[3][23]
OTCLK2inIMUX_IOCLK[5] invert by !MAIN[3][15]IMUX_IOCLK[5] invert by !MAIN[3][24]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]
TCEinIMUX_DATA[4] invert by !MAIN[3][17]IMUX_DATA[5] invert by !MAIN[3][22]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]
REVinIMUX_DATA[0] invert by !MAIN[3][11]IMUX_DATA[1] invert by !MAIN[3][28]
S1inIMUX_DATA[26]IMUX_DATA[22]
S2inIMUX_DATA[30]IMUX_DATA[10]
S3inIMUX_DATA[18]IMUX_DATA[2]
IoutOUT_FAN[4]OUT_FAN[5]
IQ1outOUT_SEC[8]OUT_SEC[9]
IQ2outOUT_SEC[12]OUT_SEC[13]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]
ToutOUT_FAN[0]OUT_FAN[1]
spartan3 IOI_S3A_WE bel IOI attribute bits
AttributeIOI[0]IOI[1]
FFI1_INIT bit 0!MAIN[2][7]!MAIN[2][32]
FFI2_INIT bit 0!MAIN[2][12]!MAIN[2][27]
FFI1_SRVAL bit 0!MAIN[2][3]!MAIN[2][36]
FFI2_SRVAL bit 0!MAIN[2][16]!MAIN[2][23]
FFI_LATCHMAIN[2][11]MAIN[2][28]
FFI_SR_SYNCMAIN[2][8]MAIN[2][31]
FFI_SR_ENABLEMAIN[2][10]MAIN[2][29]
FFI_REV_ENABLEMAIN[2][9]MAIN[2][30]
I_DELAY_ENABLEMAIN[3][10]MAIN[3][29]
I_TSBYPASS_ENABLEMAIN[3][7]MAIN[3][32]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][38]
IQ_TSBYPASS_ENABLEMAIN[3][3]MAIN[3][36]
READBACK_I bit 0MAIN[3][0]MAIN[3][39]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
MUX_FFI[enum: IOI_MUX_FFI][enum: IOI_MUX_FFI]
DELAY_VARIABLEMAIN[3][48]MAIN[3][57]
DELAY_COMMON bit 0!MAIN[3][41]!MAIN[3][42]
IQ_DELAY bit 0!MAIN[3][51]!MAIN[3][47]
IQ_DELAY bit 1!MAIN[3][53]!MAIN[3][58]
I_DELAY bit 0!MAIN[3][52]!MAIN[3][54]
I_DELAY bit 1!MAIN[3][49]!MAIN[3][55]
I_DELAY bit 2!MAIN[3][50]!MAIN[3][56]
FFO_INIT bit 0!MAIN[1][8]!MAIN[1][31]
FFO1_SRVAL bit 0!MAIN[1][3]!MAIN[1][36]
FFO2_SRVAL bit 0!MAIN[1][5]!MAIN[1][34]
FFO1_LATCHMAIN[1][17]MAIN[1][22]
FFO2_LATCHMAIN[1][18]MAIN[1][21]
FFO_SR_SYNCMAIN[1][13]MAIN[1][26]
FFO_SR_ENABLEMAIN[1][10]MAIN[1][29]
FFO_REV_ENABLEMAIN[1][9]MAIN[1][30]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O]
MUX_OCE[enum: IOI_MUX_OCE][enum: IOI_MUX_OCE]
MUX_FFO1[enum: IOI_MUX_FFO1][enum: IOI_MUX_FFO1]
MUX_FFO2[enum: IOI_MUX_FFO2][enum: IOI_MUX_FFO2]
FFT_INIT bit 0!MAIN[0][8]!MAIN[0][31]
FFT1_SRVAL bit 0!MAIN[0][3]!MAIN[0][36]
FFT2_SRVAL bit 0!MAIN[0][5]!MAIN[0][34]
FFT1_LATCHMAIN[0][17]MAIN[0][22]
FFT2_LATCHMAIN[0][18]MAIN[0][21]
FFT_SR_SYNCMAIN[0][13]MAIN[0][26]
FFT_SR_ENABLEMAIN[0][10]MAIN[0][29]
FFT_REV_ENABLEMAIN[0][9]MAIN[0][30]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T]
MUX_MISR_CLOCK[enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK]
MISR_ENABLEMAIN[0][6]MAIN[0][33]
MISR_RESETMAIN[0][7]MAIN[0][32]
spartan3 IOI_S3A_WE enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[3][4]
IOI[1].MUX_TSBYPASSMAIN[3][35]
GND1
T0
spartan3 IOI_S3A_WE enum IOI_MUX_FFI
IOI[0].MUX_FFIMAIN[3][21]MAIN[3][37]MAIN[3][8]
IOI[1].MUX_FFIMAIN[3][18]MAIN[3][2]MAIN[3][30]
NONE000
IBUF001
PAIR_IQ1010
PAIR_IQ2100
spartan3 IOI_S3A_WE enum IOI_MUX_O
IOI[0].MUX_OMAIN[1][15]MAIN[1][19]MAIN[1][14]MAIN[1][16]
IOI[1].MUX_OMAIN[1][24]MAIN[1][20]MAIN[1][25]MAIN[1][23]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
spartan3 IOI_S3A_WE enum IOI_MUX_OCE
IOI[0].MUX_OCEMAIN[2][0]MAIN[1][0]
IOI[1].MUX_OCEMAIN[2][39]MAIN[1][39]
NONE00
OCE01
PCI_CE10
spartan3 IOI_S3A_WE enum IOI_MUX_FFO1
IOI[0].MUX_FFO1MAIN[1][35]
IOI[1].MUX_FFO1MAIN[1][4]
O10
PAIR_FFO21
spartan3 IOI_S3A_WE enum IOI_MUX_FFO2
IOI[0].MUX_FFO2MAIN[0][37]
IOI[1].MUX_FFO2MAIN[0][2]
O20
PAIR_FFO11
spartan3 IOI_S3A_WE enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][15]MAIN[0][19]MAIN[0][14]MAIN[0][16]
IOI[1].MUX_TMAIN[0][24]MAIN[0][20]MAIN[0][25]MAIN[0][23]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100
spartan3 IOI_S3A_WE enum IOI_MUX_MISR_CLOCK
IOI[0].MUX_MISR_CLOCKMAIN[0][1]MAIN[0][0]
IOI[1].MUX_MISR_CLOCKMAIN[0][38]MAIN[0][39]
NONE00
OTCLK101
OTCLK210

Bel wires

spartan3 IOI_S3A_WE bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_SR_OPTINV[0]IOI[0].SR
IMUX_SR_OPTINV[1]IOI[1].SR
IMUX_CE_OPTINV[0]IOI[0].OCE
IMUX_CE_OPTINV[1]IOI[1].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[1].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[1].S2
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[0].S3
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[1].S1
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[0].S1
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[0].S2
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2

Bitstream

spartan3 IOI_S3A_WE rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - IOI[1]: ! IQ_DELAY bit 1 - - -
B57 - - - - - - - - - - - - - - - IOI[1]: DELAY_VARIABLE - - -
B56 - - - - - - - - - - - - - - - IOI[1]: ! I_DELAY bit 2 - - -
B55 - - - - - - - - - - - - - - - IOI[1]: ! I_DELAY bit 1 - - -
B54 - - - - - - - - - - - - - - - IOI[1]: ! I_DELAY bit 0 - - -
B53 - - - - - - - - - - - - - - - IOI[0]: ! IQ_DELAY bit 1 - - -
B52 - - - - - - - - - - - - - - - IOI[0]: ! I_DELAY bit 0 - - -
B51 - - - - - - - - - - - - - - - IOI[0]: ! IQ_DELAY bit 0 - - -
B50 - - - - - - - - - - - - - - - IOI[0]: ! I_DELAY bit 2 - - -
B49 - - - - - - - - - - - - - - - IOI[0]: ! I_DELAY bit 1 - - -
B48 - - - - - - - - - - - - - - - IOI[0]: DELAY_VARIABLE - - -
B47 - - - - - - - - - - - - - - - IOI[1]: ! IQ_DELAY bit 0 - - -
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - IOI[1]: ! DELAY_COMMON bit 0 - - -
B41 - - - - - - - - - - - - - - - IOI[0]: ! DELAY_COMMON bit 0 - - -
B40 - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - IOI[1]: READBACK_I bit 0 IOI[1]: MUX_OCE bit 1 IOI[1]: MUX_OCE bit 0 IOI[1]: MUX_MISR_CLOCK bit 0
B38 - - - - - - - - - - - - - - - IOI[1]: IQ_DELAY_ENABLE - - IOI[1]: MUX_MISR_CLOCK bit 1
B37 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 1 - - IOI[0]: MUX_FFO2 bit 0
B36 - - - - - - - - - - - - - - - IOI[1]: IQ_TSBYPASS_ENABLE IOI[1]: ! FFI1_SRVAL bit 0 IOI[1]: ! FFO1_SRVAL bit 0 IOI[1]: ! FFT1_SRVAL bit 0
B35 - - - - - - - - - - - - - - - IOI[1]: MUX_TSBYPASS bit 0 - IOI[0]: MUX_FFO1 bit 0 -
B34 - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 IOI[1]: ! FFT2_SRVAL bit 0
B33 - - - - - - - - - - - - - - - - - - IOI[1]: MISR_ENABLE
B32 - - - - - - - - - - - - - - - IOI[1]: I_TSBYPASS_ENABLE IOI[1]: ! FFI1_INIT bit 0 - IOI[1]: MISR_RESET
B31 - - - - - - - - - - - - - - - - IOI[1]: FFI_SR_SYNC IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0
B30 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 0 IOI[1]: FFI_REV_ENABLE IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE
B29 - - - - - - - - - - - - - - - IOI[1]: I_DELAY_ENABLE IOI[1]: FFI_SR_ENABLE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE
B28 - - - - - - - - - - - - - - - IOI[1]: !invert REV IOI[1]: FFI_LATCH IOI[1]: invert O2 IOI[1]: invert T2
B27 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: invert O1 IOI[1]: invert T1
B26 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - IOI[1]: FFO_SR_SYNC IOI[1]: FFT_SR_SYNC
B25 - - - - - - - - - - - - - - - IOI[1]: !invert ICE - IOI[1]: MUX_O bit 1 IOI[1]: MUX_T bit 1
B24 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: MUX_O bit 3 IOI[1]: MUX_T bit 3
B23 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 IOI[1]: ! FFI2_SRVAL bit 0 IOI[1]: MUX_O bit 0 IOI[1]: MUX_T bit 0
B22 - - - - - - - - - - - - - - - IOI[1]: !invert TCE - IOI[1]: FFO1_LATCH IOI[1]: FFT1_LATCH
B21 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 2 - IOI[1]: FFO2_LATCH IOI[1]: FFT2_LATCH
B20 - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: MUX_T bit 2
B19 - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 IOI[0]: MUX_T bit 2
B18 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 2 - IOI[0]: FFO2_LATCH IOI[0]: FFT2_LATCH
B17 - - - - - - - - - - - - - - - IOI[0]: !invert TCE - IOI[0]: FFO1_LATCH IOI[0]: FFT1_LATCH
B16 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 IOI[0]: ! FFI2_SRVAL bit 0 IOI[0]: MUX_O bit 0 IOI[0]: MUX_T bit 0
B15 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: MUX_O bit 3 IOI[0]: MUX_T bit 3
B14 - - - - - - - - - - - - - - - IOI[0]: !invert ICE - IOI[0]: MUX_O bit 1 IOI[0]: MUX_T bit 1
B13 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - IOI[0]: FFO_SR_SYNC IOI[0]: FFT_SR_SYNC
B12 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: invert O1 IOI[0]: invert T1
B11 - - - - - - - - - - - - - - - IOI[0]: !invert REV IOI[0]: FFI_LATCH IOI[0]: invert O2 IOI[0]: invert T2
B10 - - - - - - - - - - - - - - - IOI[0]: I_DELAY_ENABLE IOI[0]: FFI_SR_ENABLE IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE
B9 - - - - - - - - - - - - - - - - IOI[0]: FFI_REV_ENABLE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE
B8 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 0 IOI[0]: FFI_SR_SYNC IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0
B7 - - - - - - - - - - - - - - - IOI[0]: I_TSBYPASS_ENABLE IOI[0]: ! FFI1_INIT bit 0 - IOI[0]: MISR_RESET
B6 - - - - - - - - - - - - - - - - - - IOI[0]: MISR_ENABLE
B5 - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 IOI[0]: ! FFT2_SRVAL bit 0
B4 - - - - - - - - - - - - - - - IOI[0]: MUX_TSBYPASS bit 0 - IOI[1]: MUX_FFO1 bit 0 -
B3 - - - - - - - - - - - - - - - IOI[0]: IQ_TSBYPASS_ENABLE IOI[0]: ! FFI1_SRVAL bit 0 IOI[0]: ! FFO1_SRVAL bit 0 IOI[0]: ! FFT1_SRVAL bit 0
B2 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 1 - - IOI[1]: MUX_FFO2 bit 0
B1 - - - - - - - - - - - - - - - IOI[0]: IQ_DELAY_ENABLE - - IOI[0]: MUX_MISR_CLOCK bit 1
B0 - - - - - - - - - - - - - - - IOI[0]: READBACK_I bit 0 IOI[0]: MUX_OCE bit 1 IOI[0]: MUX_OCE bit 0 IOI[0]: MUX_MISR_CLOCK bit 0

Tile IOI_S3A_S

Cells: 1

Bels IOI

spartan3 IOI_S3A_S bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]
ICLK1inIMUX_IOCLK[0] invert by !MAIN[3][13]IMUX_IOCLK[0] invert by !MAIN[3][26]IMUX_IOCLK[2] invert by !MAIN[3][53]
ICLK2inIMUX_IOCLK[4] invert by !MAIN[3][12]IMUX_IOCLK[4] invert by !MAIN[3][27]IMUX_IOCLK[6] invert by !MAIN[3][52]
ICEinIMUX_DATA[8] invert by !MAIN[3][14]IMUX_DATA[9] invert by !MAIN[3][25]IMUX_DATA[10] invert by !MAIN[3][54]
O1inIMUX_DATA[24] invert by MAIN[1][12]IMUX_DATA[25] invert by MAIN[1][27]IMUX_DATA[26] invert by MAIN[1][52]
O2inIMUX_DATA[28] invert by MAIN[1][11]IMUX_DATA[29] invert by MAIN[1][28]IMUX_DATA[30] invert by MAIN[1][51]
T1inIMUX_DATA[16] invert by MAIN[0][12]IMUX_DATA[17] invert by MAIN[0][27]IMUX_DATA[18] invert by MAIN[0][52]
T2inIMUX_DATA[20] invert by MAIN[0][11]IMUX_DATA[21] invert by MAIN[0][28]IMUX_DATA[22] invert by MAIN[0][51]
OTCLK1inIMUX_IOCLK[1] invert by !MAIN[3][16]IMUX_IOCLK[1] invert by !MAIN[3][23]IMUX_IOCLK[3] invert by !MAIN[3][56]
OTCLK2inIMUX_IOCLK[5] invert by !MAIN[3][15]IMUX_IOCLK[5] invert by !MAIN[3][24]IMUX_IOCLK[7] invert by !MAIN[3][55]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]IMUX_CE_OPTINV[2]
TCEinIMUX_DATA[4] invert by !MAIN[3][17]IMUX_DATA[5] invert by !MAIN[3][22]IMUX_DATA[6] invert by !MAIN[3][57]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[2]
REVinIMUX_DATA[0] invert by !MAIN[3][11]IMUX_DATA[1] invert by !MAIN[3][28]IMUX_DATA[2] invert by !MAIN[3][51]
S1inIMUX_DATA[12]IMUX_DATA[15]IMUX_DATA[31]
S2inIMUX_DATA[7]IMUX_DATA[14]IMUX_DATA[27]
S3inIMUX_DATA[3]IMUX_DATA[11]IMUX_DATA[23]
IoutOUT_FAN[4]OUT_FAN[5]OUT_FAN[6]
IQ1outOUT_SEC[8]OUT_SEC[9]OUT_SEC[10]
IQ2outOUT_SEC[12]OUT_SEC[13]OUT_SEC[14]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]-
ToutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]
spartan3 IOI_S3A_S bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]
FFI1_INIT bit 0!MAIN[2][7]!MAIN[2][32]!MAIN[2][47]
FFI2_INIT bit 0!MAIN[2][12]!MAIN[2][27]!MAIN[2][52]
FFI1_SRVAL bit 0!MAIN[2][3]!MAIN[2][36]!MAIN[2][43]
FFI2_SRVAL bit 0!MAIN[2][16]!MAIN[2][23]!MAIN[2][56]
FFI_LATCHMAIN[2][11]MAIN[2][28]MAIN[2][51]
FFI_SR_SYNCMAIN[2][8]MAIN[2][31]MAIN[2][48]
FFI_SR_ENABLEMAIN[2][10]MAIN[2][29]MAIN[2][50]
FFI_REV_ENABLEMAIN[2][9]MAIN[2][30]MAIN[2][49]
I_DELAY_ENABLEMAIN[3][10]MAIN[3][29]MAIN[3][50]
I_TSBYPASS_ENABLEMAIN[3][7]MAIN[3][32]MAIN[3][47]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][38]MAIN[3][41]
IQ_TSBYPASS_ENABLEMAIN[3][3]MAIN[3][36]MAIN[3][43]
READBACK_I bit 0MAIN[3][0]MAIN[3][39]MAIN[3][40]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
MUX_FFI[enum: IOI_MUX_FFI][enum: IOI_MUX_FFI][enum: IOI_MUX_FFI]
FFO_INIT bit 0!MAIN[1][8]!MAIN[1][31]!MAIN[1][48]
FFO1_SRVAL bit 0!MAIN[1][3]!MAIN[1][36]!MAIN[1][43]
FFO2_SRVAL bit 0!MAIN[1][5]!MAIN[1][34]!MAIN[1][45]
FFO1_LATCHMAIN[1][17]MAIN[1][22]MAIN[1][57]
FFO2_LATCHMAIN[1][18]MAIN[1][21]MAIN[1][58]
FFO_SR_SYNCMAIN[1][13]MAIN[1][26]MAIN[1][53]
FFO_SR_ENABLEMAIN[1][10]MAIN[1][29]MAIN[1][50]
FFO_REV_ENABLEMAIN[1][9]MAIN[1][30]MAIN[1][49]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O]
MUX_OCE[enum: IOI_MUX_OCE][enum: IOI_MUX_OCE][enum: IOI_MUX_OCE]
MUX_FFO1[enum: IOI_MUX_FFO1][enum: IOI_MUX_FFO1]-
MUX_FFO2[enum: IOI_MUX_FFO2][enum: IOI_MUX_FFO2]-
FFT_INIT bit 0!MAIN[0][8]!MAIN[0][31]!MAIN[0][48]
FFT1_SRVAL bit 0!MAIN[0][3]!MAIN[0][36]!MAIN[0][43]
FFT2_SRVAL bit 0!MAIN[0][5]!MAIN[0][34]!MAIN[0][45]
FFT1_LATCHMAIN[0][17]MAIN[0][22]MAIN[0][57]
FFT2_LATCHMAIN[0][18]MAIN[0][21]MAIN[0][58]
FFT_SR_SYNCMAIN[0][13]MAIN[0][26]MAIN[0][53]
FFT_SR_ENABLEMAIN[0][10]MAIN[0][29]MAIN[0][50]
FFT_REV_ENABLEMAIN[0][9]MAIN[0][30]MAIN[0][49]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T]
MUX_MISR_CLOCK[enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK]
MISR_ENABLEMAIN[0][6]MAIN[0][33]MAIN[0][46]
MISR_RESETMAIN[0][7]MAIN[0][32]MAIN[0][47]
spartan3 IOI_S3A_S enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[3][4]
IOI[1].MUX_TSBYPASSMAIN[3][35]
IOI[2].MUX_TSBYPASSMAIN[3][44]
GND1
T0
spartan3 IOI_S3A_S enum IOI_MUX_FFI
IOI[0].MUX_FFIMAIN[3][21]MAIN[3][37]MAIN[3][8]
IOI[1].MUX_FFIMAIN[3][18]MAIN[3][2]MAIN[3][30]
IOI[2].MUX_FFIMAIN[3][58]MAIN[3][42]MAIN[3][48]
NONE000
IBUF001
PAIR_IQ1010
PAIR_IQ2100
spartan3 IOI_S3A_S enum IOI_MUX_O
IOI[0].MUX_OMAIN[1][15]MAIN[1][19]MAIN[1][14]MAIN[1][16]
IOI[1].MUX_OMAIN[1][24]MAIN[1][20]MAIN[1][25]MAIN[1][23]
IOI[2].MUX_OMAIN[1][55]MAIN[1][59]MAIN[1][54]MAIN[1][56]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
spartan3 IOI_S3A_S enum IOI_MUX_OCE
IOI[0].MUX_OCEMAIN[2][0]MAIN[1][0]
IOI[1].MUX_OCEMAIN[2][39]MAIN[1][39]
IOI[2].MUX_OCEMAIN[2][40]MAIN[1][40]
NONE00
OCE01
PCI_CE10
spartan3 IOI_S3A_S enum IOI_MUX_FFO1
IOI[0].MUX_FFO1MAIN[1][35]
IOI[1].MUX_FFO1MAIN[1][4]
O10
PAIR_FFO21
spartan3 IOI_S3A_S enum IOI_MUX_FFO2
IOI[0].MUX_FFO2MAIN[0][37]
IOI[1].MUX_FFO2MAIN[0][2]
O20
PAIR_FFO11
spartan3 IOI_S3A_S enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][15]MAIN[0][19]MAIN[0][14]MAIN[0][16]
IOI[1].MUX_TMAIN[0][24]MAIN[0][20]MAIN[0][25]MAIN[0][23]
IOI[2].MUX_TMAIN[0][55]MAIN[0][59]MAIN[0][54]MAIN[0][56]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100
spartan3 IOI_S3A_S enum IOI_MUX_MISR_CLOCK
IOI[0].MUX_MISR_CLOCKMAIN[0][1]MAIN[0][0]
IOI[1].MUX_MISR_CLOCKMAIN[0][38]MAIN[0][39]
IOI[2].MUX_MISR_CLOCKMAIN[0][41]MAIN[0][40]
NONE00
OTCLK101
OTCLK210

Bel wires

spartan3 IOI_S3A_S bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_SR_OPTINV[0]IOI[0].SR
IMUX_SR_OPTINV[1]IOI[1].SR
IMUX_SR_OPTINV[2]IOI[2].SR
IMUX_CE_OPTINV[0]IOI[0].OCE
IMUX_CE_OPTINV[1]IOI[1].OCE
IMUX_CE_OPTINV[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[3]IOI[0].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[7]IOI[0].S2
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[11]IOI[1].S3
IMUX_DATA[12]IOI[0].S1
IMUX_DATA[14]IOI[1].S2
IMUX_DATA[15]IOI[1].S1
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[23]IOI[2].S3
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[27]IOI[2].S2
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
IMUX_DATA[31]IOI[2].S1
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3A_S rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: MUX_T bit 2
B58 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 2 - IOI[2]: FFO2_LATCH IOI[2]: FFT2_LATCH
B57 - - - - - - - - - - - - - - - IOI[2]: !invert TCE - IOI[2]: FFO1_LATCH IOI[2]: FFT1_LATCH
B56 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 IOI[2]: ! FFI2_SRVAL bit 0 IOI[2]: MUX_O bit 0 IOI[2]: MUX_T bit 0
B55 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: MUX_O bit 3 IOI[2]: MUX_T bit 3
B54 - - - - - - - - - - - - - - - IOI[2]: !invert ICE - IOI[2]: MUX_O bit 1 IOI[2]: MUX_T bit 1
B53 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - IOI[2]: FFO_SR_SYNC IOI[2]: FFT_SR_SYNC
B52 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: invert O1 IOI[2]: invert T1
B51 - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFI_LATCH IOI[2]: invert O2 IOI[2]: invert T2
B50 - - - - - - - - - - - - - - - IOI[2]: I_DELAY_ENABLE IOI[2]: FFI_SR_ENABLE IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE
B49 - - - - - - - - - - - - - - - - IOI[2]: FFI_REV_ENABLE IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE
B48 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 0 IOI[2]: FFI_SR_SYNC IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0
B47 - - - - - - - - - - - - - - - IOI[2]: I_TSBYPASS_ENABLE IOI[2]: ! FFI1_INIT bit 0 - IOI[2]: MISR_RESET
B46 - - - - - - - - - - - - - - - - - - IOI[2]: MISR_ENABLE
B45 - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 IOI[2]: ! FFT2_SRVAL bit 0
B44 - - - - - - - - - - - - - - - IOI[2]: MUX_TSBYPASS bit 0 - - -
B43 - - - - - - - - - - - - - - - IOI[2]: IQ_TSBYPASS_ENABLE IOI[2]: ! FFI1_SRVAL bit 0 IOI[2]: ! FFO1_SRVAL bit 0 IOI[2]: ! FFT1_SRVAL bit 0
B42 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 1 - - -
B41 - - - - - - - - - - - - - - - IOI[2]: IQ_DELAY_ENABLE - - IOI[2]: MUX_MISR_CLOCK bit 1
B40 - - - - - - - - - - - - - - - IOI[2]: READBACK_I bit 0 IOI[2]: MUX_OCE bit 1 IOI[2]: MUX_OCE bit 0 IOI[2]: MUX_MISR_CLOCK bit 0
B39 - - - - - - - - - - - - - - - IOI[1]: READBACK_I bit 0 IOI[1]: MUX_OCE bit 1 IOI[1]: MUX_OCE bit 0 IOI[1]: MUX_MISR_CLOCK bit 0
B38 - - - - - - - - - - - - - - - IOI[1]: IQ_DELAY_ENABLE - - IOI[1]: MUX_MISR_CLOCK bit 1
B37 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 1 - - IOI[0]: MUX_FFO2 bit 0
B36 - - - - - - - - - - - - - - - IOI[1]: IQ_TSBYPASS_ENABLE IOI[1]: ! FFI1_SRVAL bit 0 IOI[1]: ! FFO1_SRVAL bit 0 IOI[1]: ! FFT1_SRVAL bit 0
B35 - - - - - - - - - - - - - - - IOI[1]: MUX_TSBYPASS bit 0 - IOI[0]: MUX_FFO1 bit 0 -
B34 - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 IOI[1]: ! FFT2_SRVAL bit 0
B33 - - - - - - - - - - - - - - - - - - IOI[1]: MISR_ENABLE
B32 - - - - - - - - - - - - - - - IOI[1]: I_TSBYPASS_ENABLE IOI[1]: ! FFI1_INIT bit 0 - IOI[1]: MISR_RESET
B31 - - - - - - - - - - - - - - - - IOI[1]: FFI_SR_SYNC IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0
B30 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 0 IOI[1]: FFI_REV_ENABLE IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE
B29 - - - - - - - - - - - - - - - IOI[1]: I_DELAY_ENABLE IOI[1]: FFI_SR_ENABLE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE
B28 - - - - - - - - - - - - - - - IOI[1]: !invert REV IOI[1]: FFI_LATCH IOI[1]: invert O2 IOI[1]: invert T2
B27 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: invert O1 IOI[1]: invert T1
B26 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - IOI[1]: FFO_SR_SYNC IOI[1]: FFT_SR_SYNC
B25 - - - - - - - - - - - - - - - IOI[1]: !invert ICE - IOI[1]: MUX_O bit 1 IOI[1]: MUX_T bit 1
B24 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: MUX_O bit 3 IOI[1]: MUX_T bit 3
B23 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 IOI[1]: ! FFI2_SRVAL bit 0 IOI[1]: MUX_O bit 0 IOI[1]: MUX_T bit 0
B22 - - - - - - - - - - - - - - - IOI[1]: !invert TCE - IOI[1]: FFO1_LATCH IOI[1]: FFT1_LATCH
B21 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 2 - IOI[1]: FFO2_LATCH IOI[1]: FFT2_LATCH
B20 - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: MUX_T bit 2
B19 - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 IOI[0]: MUX_T bit 2
B18 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 2 - IOI[0]: FFO2_LATCH IOI[0]: FFT2_LATCH
B17 - - - - - - - - - - - - - - - IOI[0]: !invert TCE - IOI[0]: FFO1_LATCH IOI[0]: FFT1_LATCH
B16 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 IOI[0]: ! FFI2_SRVAL bit 0 IOI[0]: MUX_O bit 0 IOI[0]: MUX_T bit 0
B15 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: MUX_O bit 3 IOI[0]: MUX_T bit 3
B14 - - - - - - - - - - - - - - - IOI[0]: !invert ICE - IOI[0]: MUX_O bit 1 IOI[0]: MUX_T bit 1
B13 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - IOI[0]: FFO_SR_SYNC IOI[0]: FFT_SR_SYNC
B12 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: invert O1 IOI[0]: invert T1
B11 - - - - - - - - - - - - - - - IOI[0]: !invert REV IOI[0]: FFI_LATCH IOI[0]: invert O2 IOI[0]: invert T2
B10 - - - - - - - - - - - - - - - IOI[0]: I_DELAY_ENABLE IOI[0]: FFI_SR_ENABLE IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE
B9 - - - - - - - - - - - - - - - - IOI[0]: FFI_REV_ENABLE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE
B8 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 0 IOI[0]: FFI_SR_SYNC IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0
B7 - - - - - - - - - - - - - - - IOI[0]: I_TSBYPASS_ENABLE IOI[0]: ! FFI1_INIT bit 0 - IOI[0]: MISR_RESET
B6 - - - - - - - - - - - - - - - - - - IOI[0]: MISR_ENABLE
B5 - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 IOI[0]: ! FFT2_SRVAL bit 0
B4 - - - - - - - - - - - - - - - IOI[0]: MUX_TSBYPASS bit 0 - IOI[1]: MUX_FFO1 bit 0 -
B3 - - - - - - - - - - - - - - - IOI[0]: IQ_TSBYPASS_ENABLE IOI[0]: ! FFI1_SRVAL bit 0 IOI[0]: ! FFO1_SRVAL bit 0 IOI[0]: ! FFT1_SRVAL bit 0
B2 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 1 - - IOI[1]: MUX_FFO2 bit 0
B1 - - - - - - - - - - - - - - - IOI[0]: IQ_DELAY_ENABLE - - IOI[0]: MUX_MISR_CLOCK bit 1
B0 - - - - - - - - - - - - - - - IOI[0]: READBACK_I bit 0 IOI[0]: MUX_OCE bit 1 IOI[0]: MUX_OCE bit 0 IOI[0]: MUX_MISR_CLOCK bit 0

Tile IOI_S3A_N

Cells: 1

Bels IOI

spartan3 IOI_S3A_N bel IOI pins
PinDirectionIOI[0]IOI[1]IOI[2]
ICLK1inIMUX_IOCLK[0] invert by !MAIN[3][13]IMUX_IOCLK[0] invert by !MAIN[3][26]IMUX_IOCLK[2] invert by !MAIN[3][53]
ICLK2inIMUX_IOCLK[4] invert by !MAIN[3][12]IMUX_IOCLK[4] invert by !MAIN[3][27]IMUX_IOCLK[6] invert by !MAIN[3][52]
ICEinIMUX_DATA[8] invert by !MAIN[3][14]IMUX_DATA[9] invert by !MAIN[3][25]IMUX_DATA[10] invert by !MAIN[3][54]
O1inIMUX_DATA[24] invert by MAIN[1][12]IMUX_DATA[25] invert by MAIN[1][27]IMUX_DATA[26] invert by MAIN[1][52]
O2inIMUX_DATA[28] invert by MAIN[1][11]IMUX_DATA[29] invert by MAIN[1][28]IMUX_DATA[30] invert by MAIN[1][51]
T1inIMUX_DATA[16] invert by MAIN[0][12]IMUX_DATA[17] invert by MAIN[0][27]IMUX_DATA[18] invert by MAIN[0][52]
T2inIMUX_DATA[20] invert by MAIN[0][11]IMUX_DATA[21] invert by MAIN[0][28]IMUX_DATA[22] invert by MAIN[0][51]
OTCLK1inIMUX_IOCLK[1] invert by !MAIN[3][16]IMUX_IOCLK[1] invert by !MAIN[3][23]IMUX_IOCLK[3] invert by !MAIN[3][56]
OTCLK2inIMUX_IOCLK[5] invert by !MAIN[3][15]IMUX_IOCLK[5] invert by !MAIN[3][24]IMUX_IOCLK[7] invert by !MAIN[3][55]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]IMUX_CE_OPTINV[2]
TCEinIMUX_DATA[4] invert by !MAIN[3][17]IMUX_DATA[5] invert by !MAIN[3][22]IMUX_DATA[6] invert by !MAIN[3][57]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]IMUX_SR_OPTINV[2]
REVinIMUX_DATA[0] invert by !MAIN[3][11]IMUX_DATA[1] invert by !MAIN[3][28]IMUX_DATA[2] invert by !MAIN[3][51]
S1inIMUX_DATA[31]IMUX_DATA[15]IMUX_DATA[12]
S2inIMUX_DATA[27]IMUX_DATA[14]IMUX_DATA[7]
S3inIMUX_DATA[23]IMUX_DATA[11]IMUX_DATA[3]
IoutOUT_FAN[4]OUT_FAN[5]OUT_FAN[6]
IQ1outOUT_SEC[8]OUT_SEC[9]OUT_SEC[10]
IQ2outOUT_SEC[12]OUT_SEC[13]OUT_SEC[14]
CLKPADoutOUT_CLKPAD[0]OUT_CLKPAD[1]-
ToutOUT_FAN[0]OUT_FAN[1]OUT_FAN[2]
spartan3 IOI_S3A_N bel IOI attribute bits
AttributeIOI[0]IOI[1]IOI[2]
FFI1_INIT bit 0!MAIN[2][7]!MAIN[2][32]!MAIN[2][47]
FFI2_INIT bit 0!MAIN[2][12]!MAIN[2][27]!MAIN[2][52]
FFI1_SRVAL bit 0!MAIN[2][3]!MAIN[2][36]!MAIN[2][43]
FFI2_SRVAL bit 0!MAIN[2][16]!MAIN[2][23]!MAIN[2][56]
FFI_LATCHMAIN[2][11]MAIN[2][28]MAIN[2][51]
FFI_SR_SYNCMAIN[2][8]MAIN[2][31]MAIN[2][48]
FFI_SR_ENABLEMAIN[2][10]MAIN[2][29]MAIN[2][50]
FFI_REV_ENABLEMAIN[2][9]MAIN[2][30]MAIN[2][49]
I_DELAY_ENABLEMAIN[3][10]MAIN[3][29]MAIN[3][50]
I_TSBYPASS_ENABLEMAIN[3][7]MAIN[3][32]MAIN[3][47]
IQ_DELAY_ENABLEMAIN[3][1]MAIN[3][38]MAIN[3][41]
IQ_TSBYPASS_ENABLEMAIN[3][3]MAIN[3][36]MAIN[3][43]
READBACK_I bit 0MAIN[3][0]MAIN[3][39]MAIN[3][40]
MUX_TSBYPASS[enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS][enum: IOI_MUX_TSBYPASS]
MUX_FFI[enum: IOI_MUX_FFI][enum: IOI_MUX_FFI][enum: IOI_MUX_FFI]
FFO_INIT bit 0!MAIN[1][8]!MAIN[1][31]!MAIN[1][48]
FFO1_SRVAL bit 0!MAIN[1][3]!MAIN[1][36]!MAIN[1][43]
FFO2_SRVAL bit 0!MAIN[1][5]!MAIN[1][34]!MAIN[1][45]
FFO1_LATCHMAIN[1][17]MAIN[1][22]MAIN[1][57]
FFO2_LATCHMAIN[1][18]MAIN[1][21]MAIN[1][58]
FFO_SR_SYNCMAIN[1][13]MAIN[1][26]MAIN[1][53]
FFO_SR_ENABLEMAIN[1][10]MAIN[1][29]MAIN[1][50]
FFO_REV_ENABLEMAIN[1][9]MAIN[1][30]MAIN[1][49]
MUX_O[enum: IOI_MUX_O][enum: IOI_MUX_O][enum: IOI_MUX_O]
MUX_OCE[enum: IOI_MUX_OCE][enum: IOI_MUX_OCE][enum: IOI_MUX_OCE]
MUX_FFO1[enum: IOI_MUX_FFO1][enum: IOI_MUX_FFO1]-
MUX_FFO2[enum: IOI_MUX_FFO2][enum: IOI_MUX_FFO2]-
FFT_INIT bit 0!MAIN[0][8]!MAIN[0][31]!MAIN[0][48]
FFT1_SRVAL bit 0!MAIN[0][3]!MAIN[0][36]!MAIN[0][43]
FFT2_SRVAL bit 0!MAIN[0][5]!MAIN[0][34]!MAIN[0][45]
FFT1_LATCHMAIN[0][17]MAIN[0][22]MAIN[0][57]
FFT2_LATCHMAIN[0][18]MAIN[0][21]MAIN[0][58]
FFT_SR_SYNCMAIN[0][13]MAIN[0][26]MAIN[0][53]
FFT_SR_ENABLEMAIN[0][10]MAIN[0][29]MAIN[0][50]
FFT_REV_ENABLEMAIN[0][9]MAIN[0][30]MAIN[0][49]
MUX_T[enum: IOI_MUX_T][enum: IOI_MUX_T][enum: IOI_MUX_T]
MUX_MISR_CLOCK[enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK][enum: IOI_MUX_MISR_CLOCK]
MISR_ENABLEMAIN[0][6]MAIN[0][33]MAIN[0][46]
MISR_RESETMAIN[0][7]MAIN[0][32]MAIN[0][47]
spartan3 IOI_S3A_N enum IOI_MUX_TSBYPASS
IOI[0].MUX_TSBYPASSMAIN[3][4]
IOI[1].MUX_TSBYPASSMAIN[3][35]
IOI[2].MUX_TSBYPASSMAIN[3][44]
GND1
T0
spartan3 IOI_S3A_N enum IOI_MUX_FFI
IOI[0].MUX_FFIMAIN[3][21]MAIN[3][37]MAIN[3][8]
IOI[1].MUX_FFIMAIN[3][18]MAIN[3][2]MAIN[3][30]
IOI[2].MUX_FFIMAIN[3][58]MAIN[3][42]MAIN[3][48]
NONE000
IBUF001
PAIR_IQ1010
PAIR_IQ2100
spartan3 IOI_S3A_N enum IOI_MUX_O
IOI[0].MUX_OMAIN[1][15]MAIN[1][19]MAIN[1][14]MAIN[1][16]
IOI[1].MUX_OMAIN[1][24]MAIN[1][20]MAIN[1][25]MAIN[1][23]
IOI[2].MUX_OMAIN[1][55]MAIN[1][59]MAIN[1][54]MAIN[1][56]
NONE0000
O10001
O20010
FFO10100
FFO21000
FFODDR1100
spartan3 IOI_S3A_N enum IOI_MUX_OCE
IOI[0].MUX_OCEMAIN[2][0]MAIN[1][0]
IOI[1].MUX_OCEMAIN[2][39]MAIN[1][39]
IOI[2].MUX_OCEMAIN[2][40]MAIN[1][40]
NONE00
OCE01
PCI_CE10
spartan3 IOI_S3A_N enum IOI_MUX_FFO1
IOI[0].MUX_FFO1MAIN[1][35]
IOI[1].MUX_FFO1MAIN[1][4]
O10
PAIR_FFO21
spartan3 IOI_S3A_N enum IOI_MUX_FFO2
IOI[0].MUX_FFO2MAIN[0][37]
IOI[1].MUX_FFO2MAIN[0][2]
O20
PAIR_FFO11
spartan3 IOI_S3A_N enum IOI_MUX_T
IOI[0].MUX_TMAIN[0][15]MAIN[0][19]MAIN[0][14]MAIN[0][16]
IOI[1].MUX_TMAIN[0][24]MAIN[0][20]MAIN[0][25]MAIN[0][23]
IOI[2].MUX_TMAIN[0][55]MAIN[0][59]MAIN[0][54]MAIN[0][56]
NONE0000
T10001
T20010
FFT10100
FFT21000
FFTDDR1100
spartan3 IOI_S3A_N enum IOI_MUX_MISR_CLOCK
IOI[0].MUX_MISR_CLOCKMAIN[0][1]MAIN[0][0]
IOI[1].MUX_MISR_CLOCKMAIN[0][38]MAIN[0][39]
IOI[2].MUX_MISR_CLOCKMAIN[0][41]MAIN[0][40]
NONE00
OTCLK101
OTCLK210

Bel wires

spartan3 IOI_S3A_N bel wires
WirePins
OUT_CLKPAD[0]IOI[0].CLKPAD
OUT_CLKPAD[1]IOI[1].CLKPAD
IMUX_SR_OPTINV[0]IOI[0].SR
IMUX_SR_OPTINV[1]IOI[1].SR
IMUX_SR_OPTINV[2]IOI[2].SR
IMUX_CE_OPTINV[0]IOI[0].OCE
IMUX_CE_OPTINV[1]IOI[1].OCE
IMUX_CE_OPTINV[2]IOI[2].OCE
IMUX_IOCLK[0]IOI[0].ICLK1, IOI[1].ICLK1
IMUX_IOCLK[1]IOI[0].OTCLK1, IOI[1].OTCLK1
IMUX_IOCLK[2]IOI[2].ICLK1
IMUX_IOCLK[3]IOI[2].OTCLK1
IMUX_IOCLK[4]IOI[0].ICLK2, IOI[1].ICLK2
IMUX_IOCLK[5]IOI[0].OTCLK2, IOI[1].OTCLK2
IMUX_IOCLK[6]IOI[2].ICLK2
IMUX_IOCLK[7]IOI[2].OTCLK2
IMUX_DATA[0]IOI[0].REV
IMUX_DATA[1]IOI[1].REV
IMUX_DATA[2]IOI[2].REV
IMUX_DATA[3]IOI[2].S3
IMUX_DATA[4]IOI[0].TCE
IMUX_DATA[5]IOI[1].TCE
IMUX_DATA[6]IOI[2].TCE
IMUX_DATA[7]IOI[2].S2
IMUX_DATA[8]IOI[0].ICE
IMUX_DATA[9]IOI[1].ICE
IMUX_DATA[10]IOI[2].ICE
IMUX_DATA[11]IOI[1].S3
IMUX_DATA[12]IOI[2].S1
IMUX_DATA[14]IOI[1].S2
IMUX_DATA[15]IOI[1].S1
IMUX_DATA[16]IOI[0].T1
IMUX_DATA[17]IOI[1].T1
IMUX_DATA[18]IOI[2].T1
IMUX_DATA[20]IOI[0].T2
IMUX_DATA[21]IOI[1].T2
IMUX_DATA[22]IOI[2].T2
IMUX_DATA[23]IOI[0].S3
IMUX_DATA[24]IOI[0].O1
IMUX_DATA[25]IOI[1].O1
IMUX_DATA[26]IOI[2].O1
IMUX_DATA[27]IOI[0].S2
IMUX_DATA[28]IOI[0].O2
IMUX_DATA[29]IOI[1].O2
IMUX_DATA[30]IOI[2].O2
IMUX_DATA[31]IOI[0].S1
OUT_FAN[0]IOI[0].T
OUT_FAN[1]IOI[1].T
OUT_FAN[2]IOI[2].T
OUT_FAN[4]IOI[0].I
OUT_FAN[5]IOI[1].I
OUT_FAN[6]IOI[2].I
OUT_SEC[8]IOI[0].IQ1
OUT_SEC[9]IOI[1].IQ1
OUT_SEC[10]IOI[2].IQ1
OUT_SEC[12]IOI[0].IQ2
OUT_SEC[13]IOI[1].IQ2
OUT_SEC[14]IOI[2].IQ2

Bitstream

spartan3 IOI_S3A_N rect MAIN
BitFrame
F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - IOI[2]: MUX_O bit 2 IOI[2]: MUX_T bit 2
B58 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 2 - IOI[2]: FFO2_LATCH IOI[2]: FFT2_LATCH
B57 - - - - - - - - - - - - - - - IOI[2]: !invert TCE - IOI[2]: FFO1_LATCH IOI[2]: FFT1_LATCH
B56 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK1 IOI[2]: ! FFI2_SRVAL bit 0 IOI[2]: MUX_O bit 0 IOI[2]: MUX_T bit 0
B55 - - - - - - - - - - - - - - - IOI[2]: !invert OTCLK2 - IOI[2]: MUX_O bit 3 IOI[2]: MUX_T bit 3
B54 - - - - - - - - - - - - - - - IOI[2]: !invert ICE - IOI[2]: MUX_O bit 1 IOI[2]: MUX_T bit 1
B53 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK1 - IOI[2]: FFO_SR_SYNC IOI[2]: FFT_SR_SYNC
B52 - - - - - - - - - - - - - - - IOI[2]: !invert ICLK2 IOI[2]: ! FFI2_INIT bit 0 IOI[2]: invert O1 IOI[2]: invert T1
B51 - - - - - - - - - - - - - - - IOI[2]: !invert REV IOI[2]: FFI_LATCH IOI[2]: invert O2 IOI[2]: invert T2
B50 - - - - - - - - - - - - - - - IOI[2]: I_DELAY_ENABLE IOI[2]: FFI_SR_ENABLE IOI[2]: FFO_SR_ENABLE IOI[2]: FFT_SR_ENABLE
B49 - - - - - - - - - - - - - - - - IOI[2]: FFI_REV_ENABLE IOI[2]: FFO_REV_ENABLE IOI[2]: FFT_REV_ENABLE
B48 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 0 IOI[2]: FFI_SR_SYNC IOI[2]: ! FFO_INIT bit 0 IOI[2]: ! FFT_INIT bit 0
B47 - - - - - - - - - - - - - - - IOI[2]: I_TSBYPASS_ENABLE IOI[2]: ! FFI1_INIT bit 0 - IOI[2]: MISR_RESET
B46 - - - - - - - - - - - - - - - - - - IOI[2]: MISR_ENABLE
B45 - - - - - - - - - - - - - - - - - IOI[2]: ! FFO2_SRVAL bit 0 IOI[2]: ! FFT2_SRVAL bit 0
B44 - - - - - - - - - - - - - - - IOI[2]: MUX_TSBYPASS bit 0 - - -
B43 - - - - - - - - - - - - - - - IOI[2]: IQ_TSBYPASS_ENABLE IOI[2]: ! FFI1_SRVAL bit 0 IOI[2]: ! FFO1_SRVAL bit 0 IOI[2]: ! FFT1_SRVAL bit 0
B42 - - - - - - - - - - - - - - - IOI[2]: MUX_FFI bit 1 - - -
B41 - - - - - - - - - - - - - - - IOI[2]: IQ_DELAY_ENABLE - - IOI[2]: MUX_MISR_CLOCK bit 1
B40 - - - - - - - - - - - - - - - IOI[2]: READBACK_I bit 0 IOI[2]: MUX_OCE bit 1 IOI[2]: MUX_OCE bit 0 IOI[2]: MUX_MISR_CLOCK bit 0
B39 - - - - - - - - - - - - - - - IOI[1]: READBACK_I bit 0 IOI[1]: MUX_OCE bit 1 IOI[1]: MUX_OCE bit 0 IOI[1]: MUX_MISR_CLOCK bit 0
B38 - - - - - - - - - - - - - - - IOI[1]: IQ_DELAY_ENABLE - - IOI[1]: MUX_MISR_CLOCK bit 1
B37 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 1 - - IOI[0]: MUX_FFO2 bit 0
B36 - - - - - - - - - - - - - - - IOI[1]: IQ_TSBYPASS_ENABLE IOI[1]: ! FFI1_SRVAL bit 0 IOI[1]: ! FFO1_SRVAL bit 0 IOI[1]: ! FFT1_SRVAL bit 0
B35 - - - - - - - - - - - - - - - IOI[1]: MUX_TSBYPASS bit 0 - IOI[0]: MUX_FFO1 bit 0 -
B34 - - - - - - - - - - - - - - - - - IOI[1]: ! FFO2_SRVAL bit 0 IOI[1]: ! FFT2_SRVAL bit 0
B33 - - - - - - - - - - - - - - - - - - IOI[1]: MISR_ENABLE
B32 - - - - - - - - - - - - - - - IOI[1]: I_TSBYPASS_ENABLE IOI[1]: ! FFI1_INIT bit 0 - IOI[1]: MISR_RESET
B31 - - - - - - - - - - - - - - - - IOI[1]: FFI_SR_SYNC IOI[1]: ! FFO_INIT bit 0 IOI[1]: ! FFT_INIT bit 0
B30 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 0 IOI[1]: FFI_REV_ENABLE IOI[1]: FFO_REV_ENABLE IOI[1]: FFT_REV_ENABLE
B29 - - - - - - - - - - - - - - - IOI[1]: I_DELAY_ENABLE IOI[1]: FFI_SR_ENABLE IOI[1]: FFO_SR_ENABLE IOI[1]: FFT_SR_ENABLE
B28 - - - - - - - - - - - - - - - IOI[1]: !invert REV IOI[1]: FFI_LATCH IOI[1]: invert O2 IOI[1]: invert T2
B27 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK2 IOI[1]: ! FFI2_INIT bit 0 IOI[1]: invert O1 IOI[1]: invert T1
B26 - - - - - - - - - - - - - - - IOI[1]: !invert ICLK1 - IOI[1]: FFO_SR_SYNC IOI[1]: FFT_SR_SYNC
B25 - - - - - - - - - - - - - - - IOI[1]: !invert ICE - IOI[1]: MUX_O bit 1 IOI[1]: MUX_T bit 1
B24 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK2 - IOI[1]: MUX_O bit 3 IOI[1]: MUX_T bit 3
B23 - - - - - - - - - - - - - - - IOI[1]: !invert OTCLK1 IOI[1]: ! FFI2_SRVAL bit 0 IOI[1]: MUX_O bit 0 IOI[1]: MUX_T bit 0
B22 - - - - - - - - - - - - - - - IOI[1]: !invert TCE - IOI[1]: FFO1_LATCH IOI[1]: FFT1_LATCH
B21 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 2 - IOI[1]: FFO2_LATCH IOI[1]: FFT2_LATCH
B20 - - - - - - - - - - - - - - - - - IOI[1]: MUX_O bit 2 IOI[1]: MUX_T bit 2
B19 - - - - - - - - - - - - - - - - - IOI[0]: MUX_O bit 2 IOI[0]: MUX_T bit 2
B18 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 2 - IOI[0]: FFO2_LATCH IOI[0]: FFT2_LATCH
B17 - - - - - - - - - - - - - - - IOI[0]: !invert TCE - IOI[0]: FFO1_LATCH IOI[0]: FFT1_LATCH
B16 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK1 IOI[0]: ! FFI2_SRVAL bit 0 IOI[0]: MUX_O bit 0 IOI[0]: MUX_T bit 0
B15 - - - - - - - - - - - - - - - IOI[0]: !invert OTCLK2 - IOI[0]: MUX_O bit 3 IOI[0]: MUX_T bit 3
B14 - - - - - - - - - - - - - - - IOI[0]: !invert ICE - IOI[0]: MUX_O bit 1 IOI[0]: MUX_T bit 1
B13 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK1 - IOI[0]: FFO_SR_SYNC IOI[0]: FFT_SR_SYNC
B12 - - - - - - - - - - - - - - - IOI[0]: !invert ICLK2 IOI[0]: ! FFI2_INIT bit 0 IOI[0]: invert O1 IOI[0]: invert T1
B11 - - - - - - - - - - - - - - - IOI[0]: !invert REV IOI[0]: FFI_LATCH IOI[0]: invert O2 IOI[0]: invert T2
B10 - - - - - - - - - - - - - - - IOI[0]: I_DELAY_ENABLE IOI[0]: FFI_SR_ENABLE IOI[0]: FFO_SR_ENABLE IOI[0]: FFT_SR_ENABLE
B9 - - - - - - - - - - - - - - - - IOI[0]: FFI_REV_ENABLE IOI[0]: FFO_REV_ENABLE IOI[0]: FFT_REV_ENABLE
B8 - - - - - - - - - - - - - - - IOI[0]: MUX_FFI bit 0 IOI[0]: FFI_SR_SYNC IOI[0]: ! FFO_INIT bit 0 IOI[0]: ! FFT_INIT bit 0
B7 - - - - - - - - - - - - - - - IOI[0]: I_TSBYPASS_ENABLE IOI[0]: ! FFI1_INIT bit 0 - IOI[0]: MISR_RESET
B6 - - - - - - - - - - - - - - - - - - IOI[0]: MISR_ENABLE
B5 - - - - - - - - - - - - - - - - - IOI[0]: ! FFO2_SRVAL bit 0 IOI[0]: ! FFT2_SRVAL bit 0
B4 - - - - - - - - - - - - - - - IOI[0]: MUX_TSBYPASS bit 0 - IOI[1]: MUX_FFO1 bit 0 -
B3 - - - - - - - - - - - - - - - IOI[0]: IQ_TSBYPASS_ENABLE IOI[0]: ! FFI1_SRVAL bit 0 IOI[0]: ! FFO1_SRVAL bit 0 IOI[0]: ! FFT1_SRVAL bit 0
B2 - - - - - - - - - - - - - - - IOI[1]: MUX_FFI bit 1 - - IOI[1]: MUX_FFO2 bit 0
B1 - - - - - - - - - - - - - - - IOI[0]: IQ_DELAY_ENABLE - - IOI[0]: MUX_MISR_CLOCK bit 1
B0 - - - - - - - - - - - - - - - IOI[0]: READBACK_I bit 0 IOI[0]: MUX_OCE bit 1 IOI[0]: MUX_OCE bit 0 IOI[0]: MUX_MISR_CLOCK bit 0