TODO: document
IO0:IFF1_INIT |
0.2.7 |
IO0:IFF1_SRVAL |
0.2.3 |
IO0:IFF2_INIT |
0.2.12 |
IO0:IFF2_SRVAL |
0.2.16 |
IO0:INV.ICE |
0.3.14 |
IO0:INV.ICLK1 |
0.3.13 |
IO0:INV.ICLK2 |
0.3.12 |
IO0:INV.OTCLK1 |
0.3.16 |
IO0:INV.OTCLK2 |
0.3.15 |
IO0:INV.REV |
0.3.11 |
IO0:INV.TCE |
0.3.17 |
IO0:OFF1_SRVAL |
0.1.3 |
IO0:OFF2_SRVAL |
0.1.5 |
IO0:OFF_INIT |
0.1.8 |
IO0:TFF1_SRVAL |
0.0.3 |
IO0:TFF2_SRVAL |
0.0.5 |
IO0:TFF_INIT |
0.0.8 |
IO1:IFF1_INIT |
0.2.32 |
IO1:IFF1_SRVAL |
0.2.36 |
IO1:IFF2_INIT |
0.2.27 |
IO1:IFF2_SRVAL |
0.2.23 |
IO1:INV.ICE |
0.3.25 |
IO1:INV.ICLK1 |
0.3.26 |
IO1:INV.ICLK2 |
0.3.27 |
IO1:INV.OTCLK1 |
0.3.23 |
IO1:INV.OTCLK2 |
0.3.24 |
IO1:INV.REV |
0.3.28 |
IO1:INV.TCE |
0.3.22 |
IO1:OFF1_SRVAL |
0.1.36 |
IO1:OFF2_SRVAL |
0.1.34 |
IO1:OFF_INIT |
0.1.31 |
IO1:TFF1_SRVAL |
0.0.36 |
IO1:TFF2_SRVAL |
0.0.34 |
IO1:TFF_INIT |
0.0.31 |
IO2:IFF1_INIT |
0.2.47 |
IO2:IFF1_SRVAL |
0.2.43 |
IO2:IFF2_INIT |
0.2.52 |
IO2:IFF2_SRVAL |
0.2.56 |
IO2:INV.ICE |
0.3.54 |
IO2:INV.ICLK1 |
0.3.53 |
IO2:INV.ICLK2 |
0.3.52 |
IO2:INV.OTCLK1 |
0.3.56 |
IO2:INV.OTCLK2 |
0.3.55 |
IO2:INV.REV |
0.3.51 |
IO2:INV.TCE |
0.3.57 |
IO2:OFF1_SRVAL |
0.1.43 |
IO2:OFF2_SRVAL |
0.1.45 |
IO2:OFF_INIT |
0.1.48 |
IO2:TFF1_SRVAL |
0.0.43 |
IO2:TFF2_SRVAL |
0.0.45 |
IO2:TFF_INIT |
0.0.48 |
inverted
|
~[0] |
IO0:IFF_DELAY_ENABLE |
0.3.1 |
IO0:IFF_LATCH |
0.2.11 |
IO0:IFF_REV_ENABLE |
0.2.9 |
IO0:IFF_SR_ENABLE |
0.2.10 |
IO0:IFF_SR_SYNC |
0.2.8 |
IO0:IFF_TSBYPASS_ENABLE |
0.3.3 |
IO0:INV.O1 |
0.1.12 |
IO0:INV.O2 |
0.1.11 |
IO0:INV.T1 |
0.0.12 |
IO0:INV.T2 |
0.0.11 |
IO0:I_DELAY_ENABLE |
0.3.10 |
IO0:I_TSBYPASS_ENABLE |
0.3.7 |
IO0:OFF1_LATCH |
0.1.17 |
IO0:OFF2_LATCH |
0.1.18 |
IO0:OFF_REV_ENABLE |
0.1.9 |
IO0:OFF_SR_ENABLE |
0.1.10 |
IO0:OFF_SR_SYNC |
0.1.13 |
IO0:READBACK_I |
0.3.0 |
IO0:TFF1_LATCH |
0.0.17 |
IO0:TFF2_LATCH |
0.0.18 |
IO0:TFF_REV_ENABLE |
0.0.9 |
IO0:TFF_SR_ENABLE |
0.0.10 |
IO0:TFF_SR_SYNC |
0.0.13 |
IO1:IFF_DELAY_ENABLE |
0.3.38 |
IO1:IFF_LATCH |
0.2.28 |
IO1:IFF_REV_ENABLE |
0.2.30 |
IO1:IFF_SR_ENABLE |
0.2.29 |
IO1:IFF_SR_SYNC |
0.2.31 |
IO1:IFF_TSBYPASS_ENABLE |
0.3.36 |
IO1:INV.O1 |
0.1.27 |
IO1:INV.O2 |
0.1.28 |
IO1:INV.T1 |
0.0.27 |
IO1:INV.T2 |
0.0.28 |
IO1:I_DELAY_ENABLE |
0.3.29 |
IO1:I_TSBYPASS_ENABLE |
0.3.32 |
IO1:OFF1_LATCH |
0.1.22 |
IO1:OFF2_LATCH |
0.1.21 |
IO1:OFF_REV_ENABLE |
0.1.30 |
IO1:OFF_SR_ENABLE |
0.1.29 |
IO1:OFF_SR_SYNC |
0.1.26 |
IO1:READBACK_I |
0.3.39 |
IO1:TFF1_LATCH |
0.0.22 |
IO1:TFF2_LATCH |
0.0.21 |
IO1:TFF_REV_ENABLE |
0.0.30 |
IO1:TFF_SR_ENABLE |
0.0.29 |
IO1:TFF_SR_SYNC |
0.0.26 |
IO2:IFF_DELAY_ENABLE |
0.3.41 |
IO2:IFF_LATCH |
0.2.51 |
IO2:IFF_REV_ENABLE |
0.2.49 |
IO2:IFF_SR_ENABLE |
0.2.50 |
IO2:IFF_SR_SYNC |
0.2.48 |
IO2:IFF_TSBYPASS_ENABLE |
0.3.43 |
IO2:INV.O1 |
0.1.52 |
IO2:INV.O2 |
0.1.51 |
IO2:INV.T1 |
0.0.52 |
IO2:INV.T2 |
0.0.51 |
IO2:I_DELAY_ENABLE |
0.3.50 |
IO2:I_TSBYPASS_ENABLE |
0.3.47 |
IO2:OFF1_LATCH |
0.1.57 |
IO2:OFF2_LATCH |
0.1.58 |
IO2:OFF_REV_ENABLE |
0.1.49 |
IO2:OFF_SR_ENABLE |
0.1.50 |
IO2:OFF_SR_SYNC |
0.1.53 |
IO2:READBACK_I |
0.3.40 |
IO2:TFF1_LATCH |
0.0.57 |
IO2:TFF2_LATCH |
0.0.58 |
IO2:TFF_REV_ENABLE |
0.0.49 |
IO2:TFF_SR_ENABLE |
0.0.50 |
IO2:TFF_SR_SYNC |
0.0.53 |
non-inverted
|
[0] |
IO0:OMUX |
0.1.15 |
0.1.19 |
0.1.14 |
0.1.16 |
IO1:OMUX |
0.1.24 |
0.1.20 |
0.1.25 |
0.1.23 |
IO2:OMUX |
0.1.55 |
0.1.59 |
0.1.54 |
0.1.56 |
NONE |
0 |
0 |
0 |
0 |
O1 |
0 |
0 |
0 |
1 |
O2 |
0 |
0 |
1 |
0 |
OFF1 |
0 |
1 |
0 |
0 |
OFF2 |
1 |
0 |
0 |
0 |
OFFDDR |
1 |
1 |
0 |
0 |
IO0:TMUX |
0.0.15 |
0.0.19 |
0.0.14 |
0.0.16 |
IO1:TMUX |
0.0.24 |
0.0.20 |
0.0.25 |
0.0.23 |
IO2:TMUX |
0.0.55 |
0.0.59 |
0.0.54 |
0.0.56 |
NONE |
0 |
0 |
0 |
0 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
1 |
0 |
TFF1 |
0 |
1 |
0 |
0 |
TFF2 |
1 |
0 |
0 |
0 |
TFFDDR |
1 |
1 |
0 |
0 |
IO0:TSBYPASS_MUX |
0.3.4 |
IO1:TSBYPASS_MUX |
0.3.35 |
IO2:TSBYPASS_MUX |
0.3.44 |
TMUX |
0 |
GND |
1 |
IO0:IDDRIN_MUX |
0.3.21 |
0.3.37 |
0.3.8 |
IO1:IDDRIN_MUX |
0.3.18 |
0.3.2 |
0.3.30 |
IO2:IDDRIN_MUX |
0.3.58 |
0.3.42 |
0.3.48 |
NONE |
0 |
0 |
0 |
IFFDMUX |
0 |
0 |
1 |
IDDRIN1 |
0 |
1 |
0 |
IDDRIN2 |
1 |
0 |
0 |
IO0:IFF1_INIT |
0.2.7 |
IO0:IFF1_SRVAL |
0.2.3 |
IO0:IFF2_INIT |
0.2.12 |
IO0:IFF2_SRVAL |
0.2.16 |
IO0:INV.ICE |
0.3.14 |
IO0:INV.ICLK1 |
0.3.13 |
IO0:INV.ICLK2 |
0.3.12 |
IO0:INV.OTCLK1 |
0.3.16 |
IO0:INV.OTCLK2 |
0.3.15 |
IO0:INV.REV |
0.3.11 |
IO0:INV.TCE |
0.3.17 |
IO0:OFF1_SRVAL |
0.1.3 |
IO0:OFF2_SRVAL |
0.1.5 |
IO0:OFF_INIT |
0.1.8 |
IO0:TFF1_SRVAL |
0.0.3 |
IO0:TFF2_SRVAL |
0.0.5 |
IO0:TFF_INIT |
0.0.8 |
IO1:IFF1_INIT |
0.2.32 |
IO1:IFF1_SRVAL |
0.2.36 |
IO1:IFF2_INIT |
0.2.27 |
IO1:IFF2_SRVAL |
0.2.23 |
IO1:INV.ICE |
0.3.25 |
IO1:INV.ICLK1 |
0.3.26 |
IO1:INV.ICLK2 |
0.3.27 |
IO1:INV.OTCLK1 |
0.3.23 |
IO1:INV.OTCLK2 |
0.3.24 |
IO1:INV.REV |
0.3.28 |
IO1:INV.TCE |
0.3.22 |
IO1:OFF1_SRVAL |
0.1.36 |
IO1:OFF2_SRVAL |
0.1.34 |
IO1:OFF_INIT |
0.1.31 |
IO1:TFF1_SRVAL |
0.0.36 |
IO1:TFF2_SRVAL |
0.0.34 |
IO1:TFF_INIT |
0.0.31 |
IO2:IFF1_INIT |
0.2.47 |
IO2:IFF1_SRVAL |
0.2.43 |
IO2:IFF2_INIT |
0.2.52 |
IO2:IFF2_SRVAL |
0.2.56 |
IO2:INV.ICE |
0.3.54 |
IO2:INV.ICLK1 |
0.3.53 |
IO2:INV.ICLK2 |
0.3.52 |
IO2:INV.OTCLK1 |
0.3.56 |
IO2:INV.OTCLK2 |
0.3.55 |
IO2:INV.REV |
0.3.51 |
IO2:INV.TCE |
0.3.57 |
IO2:OFF1_SRVAL |
0.1.43 |
IO2:OFF2_SRVAL |
0.1.45 |
IO2:OFF_INIT |
0.1.48 |
IO2:TFF1_SRVAL |
0.0.43 |
IO2:TFF2_SRVAL |
0.0.45 |
IO2:TFF_INIT |
0.0.48 |
inverted
|
~[0] |
IO0:IFF_DELAY_ENABLE |
0.3.1 |
IO0:IFF_LATCH |
0.2.11 |
IO0:IFF_REV_ENABLE |
0.2.9 |
IO0:IFF_SR_ENABLE |
0.2.10 |
IO0:IFF_SR_SYNC |
0.2.8 |
IO0:IFF_TSBYPASS_ENABLE |
0.3.3 |
IO0:INV.O1 |
0.1.12 |
IO0:INV.O2 |
0.1.11 |
IO0:INV.T1 |
0.0.12 |
IO0:INV.T2 |
0.0.11 |
IO0:I_DELAY_ENABLE |
0.3.10 |
IO0:I_TSBYPASS_ENABLE |
0.3.7 |
IO0:MISR_ENABLE |
0.0.6 |
IO0:MISR_RESET |
0.0.7 |
IO0:OFF1_LATCH |
0.1.17 |
IO0:OFF2_LATCH |
0.1.18 |
IO0:OFF_REV_ENABLE |
0.1.9 |
IO0:OFF_SR_ENABLE |
0.1.10 |
IO0:OFF_SR_SYNC |
0.1.13 |
IO0:READBACK_I |
0.3.0 |
IO0:TFF1_LATCH |
0.0.17 |
IO0:TFF2_LATCH |
0.0.18 |
IO0:TFF_REV_ENABLE |
0.0.9 |
IO0:TFF_SR_ENABLE |
0.0.10 |
IO0:TFF_SR_SYNC |
0.0.13 |
IO1:IFF_DELAY_ENABLE |
0.3.38 |
IO1:IFF_LATCH |
0.2.28 |
IO1:IFF_REV_ENABLE |
0.2.30 |
IO1:IFF_SR_ENABLE |
0.2.29 |
IO1:IFF_SR_SYNC |
0.2.31 |
IO1:IFF_TSBYPASS_ENABLE |
0.3.36 |
IO1:INV.O1 |
0.1.27 |
IO1:INV.O2 |
0.1.28 |
IO1:INV.T1 |
0.0.27 |
IO1:INV.T2 |
0.0.28 |
IO1:I_DELAY_ENABLE |
0.3.29 |
IO1:I_TSBYPASS_ENABLE |
0.3.32 |
IO1:MISR_ENABLE |
0.0.33 |
IO1:MISR_RESET |
0.0.32 |
IO1:OFF1_LATCH |
0.1.22 |
IO1:OFF2_LATCH |
0.1.21 |
IO1:OFF_REV_ENABLE |
0.1.30 |
IO1:OFF_SR_ENABLE |
0.1.29 |
IO1:OFF_SR_SYNC |
0.1.26 |
IO1:READBACK_I |
0.3.39 |
IO1:TFF1_LATCH |
0.0.22 |
IO1:TFF2_LATCH |
0.0.21 |
IO1:TFF_REV_ENABLE |
0.0.30 |
IO1:TFF_SR_ENABLE |
0.0.29 |
IO1:TFF_SR_SYNC |
0.0.26 |
IO2:IFF_DELAY_ENABLE |
0.3.41 |
IO2:IFF_LATCH |
0.2.51 |
IO2:IFF_REV_ENABLE |
0.2.49 |
IO2:IFF_SR_ENABLE |
0.2.50 |
IO2:IFF_SR_SYNC |
0.2.48 |
IO2:IFF_TSBYPASS_ENABLE |
0.3.43 |
IO2:INV.O1 |
0.1.52 |
IO2:INV.O2 |
0.1.51 |
IO2:INV.T1 |
0.0.52 |
IO2:INV.T2 |
0.0.51 |
IO2:I_DELAY_ENABLE |
0.3.50 |
IO2:I_TSBYPASS_ENABLE |
0.3.47 |
IO2:MISR_ENABLE |
0.0.46 |
IO2:MISR_RESET |
0.0.47 |
IO2:OFF1_LATCH |
0.1.57 |
IO2:OFF2_LATCH |
0.1.58 |
IO2:OFF_REV_ENABLE |
0.1.49 |
IO2:OFF_SR_ENABLE |
0.1.50 |
IO2:OFF_SR_SYNC |
0.1.53 |
IO2:READBACK_I |
0.3.40 |
IO2:TFF1_LATCH |
0.0.57 |
IO2:TFF2_LATCH |
0.0.58 |
IO2:TFF_REV_ENABLE |
0.0.49 |
IO2:TFF_SR_ENABLE |
0.0.50 |
IO2:TFF_SR_SYNC |
0.0.53 |
non-inverted
|
[0] |
IO0:MISR_CLOCK |
0.0.1 |
0.0.0 |
IO1:MISR_CLOCK |
0.0.38 |
0.0.39 |
IO2:MISR_CLOCK |
0.0.41 |
0.0.40 |
NONE |
0 |
0 |
OTCLK1 |
0 |
1 |
OTCLK2 |
1 |
0 |
IO0:O1_DDRMUX |
0.1.35 |
IO1:O1_DDRMUX |
0.1.4 |
O1 |
0 |
ODDRIN1 |
1 |
IO0:O2_DDRMUX |
0.0.37 |
IO1:O2_DDRMUX |
0.0.2 |
O2 |
0 |
ODDRIN2 |
1 |
IO0:OMUX |
0.1.15 |
0.1.19 |
0.1.14 |
0.1.16 |
IO1:OMUX |
0.1.24 |
0.1.20 |
0.1.25 |
0.1.23 |
IO2:OMUX |
0.1.55 |
0.1.59 |
0.1.54 |
0.1.56 |
NONE |
0 |
0 |
0 |
0 |
O1 |
0 |
0 |
0 |
1 |
O2 |
0 |
0 |
1 |
0 |
OFF1 |
0 |
1 |
0 |
0 |
OFF2 |
1 |
0 |
0 |
0 |
OFFDDR |
1 |
1 |
0 |
0 |
IO0:PCICE_MUX |
0.2.0 |
0.1.0 |
IO1:PCICE_MUX |
0.2.39 |
0.1.39 |
IO2:PCICE_MUX |
0.2.40 |
0.1.40 |
NONE |
0 |
0 |
OCE |
0 |
1 |
PCICE |
1 |
0 |
IO0:TMUX |
0.0.15 |
0.0.19 |
0.0.14 |
0.0.16 |
IO1:TMUX |
0.0.24 |
0.0.20 |
0.0.25 |
0.0.23 |
IO2:TMUX |
0.0.55 |
0.0.59 |
0.0.54 |
0.0.56 |
NONE |
0 |
0 |
0 |
0 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
1 |
0 |
TFF1 |
0 |
1 |
0 |
0 |
TFF2 |
1 |
0 |
0 |
0 |
TFFDDR |
1 |
1 |
0 |
0 |
IO0:TSBYPASS_MUX |
0.3.4 |
IO1:TSBYPASS_MUX |
0.3.35 |
IO2:TSBYPASS_MUX |
0.3.44 |
TMUX |
0 |
GND |
1 |
IO0:DELAY_COMMON |
0.3.41 |
IO0:IFF1_INIT |
0.2.7 |
IO0:IFF1_SRVAL |
0.2.3 |
IO0:IFF2_INIT |
0.2.12 |
IO0:IFF2_SRVAL |
0.2.16 |
IO0:INV.ICE |
0.3.14 |
IO0:INV.ICLK1 |
0.3.13 |
IO0:INV.ICLK2 |
0.3.12 |
IO0:INV.OTCLK1 |
0.3.16 |
IO0:INV.OTCLK2 |
0.3.15 |
IO0:INV.REV |
0.3.11 |
IO0:INV.TCE |
0.3.17 |
IO0:OFF1_SRVAL |
0.1.3 |
IO0:OFF2_SRVAL |
0.1.5 |
IO0:OFF_INIT |
0.1.8 |
IO0:TFF1_SRVAL |
0.0.3 |
IO0:TFF2_SRVAL |
0.0.5 |
IO0:TFF_INIT |
0.0.8 |
IO1:DELAY_COMMON |
0.3.42 |
IO1:IFF1_INIT |
0.2.32 |
IO1:IFF1_SRVAL |
0.2.36 |
IO1:IFF2_INIT |
0.2.27 |
IO1:IFF2_SRVAL |
0.2.23 |
IO1:INV.ICE |
0.3.25 |
IO1:INV.ICLK1 |
0.3.26 |
IO1:INV.ICLK2 |
0.3.27 |
IO1:INV.OTCLK1 |
0.3.23 |
IO1:INV.OTCLK2 |
0.3.24 |
IO1:INV.REV |
0.3.28 |
IO1:INV.TCE |
0.3.22 |
IO1:OFF1_SRVAL |
0.1.36 |
IO1:OFF2_SRVAL |
0.1.34 |
IO1:OFF_INIT |
0.1.31 |
IO1:TFF1_SRVAL |
0.0.36 |
IO1:TFF2_SRVAL |
0.0.34 |
IO1:TFF_INIT |
0.0.31 |
inverted
|
~[0] |
IO0:DELAY_VARIABLE |
0.3.48 |
IO0:IFF_DELAY_ENABLE |
0.3.1 |
IO0:IFF_LATCH |
0.2.11 |
IO0:IFF_REV_ENABLE |
0.2.9 |
IO0:IFF_SR_ENABLE |
0.2.10 |
IO0:IFF_SR_SYNC |
0.2.8 |
IO0:IFF_TSBYPASS_ENABLE |
0.3.3 |
IO0:INV.O1 |
0.1.12 |
IO0:INV.O2 |
0.1.11 |
IO0:INV.T1 |
0.0.12 |
IO0:INV.T2 |
0.0.11 |
IO0:I_DELAY_ENABLE |
0.3.10 |
IO0:I_TSBYPASS_ENABLE |
0.3.7 |
IO0:MISR_ENABLE |
0.0.6 |
IO0:MISR_RESET |
0.0.7 |
IO0:OFF1_LATCH |
0.1.17 |
IO0:OFF2_LATCH |
0.1.18 |
IO0:OFF_REV_ENABLE |
0.1.9 |
IO0:OFF_SR_ENABLE |
0.1.10 |
IO0:OFF_SR_SYNC |
0.1.13 |
IO0:READBACK_I |
0.3.0 |
IO0:TFF1_LATCH |
0.0.17 |
IO0:TFF2_LATCH |
0.0.18 |
IO0:TFF_REV_ENABLE |
0.0.9 |
IO0:TFF_SR_ENABLE |
0.0.10 |
IO0:TFF_SR_SYNC |
0.0.13 |
IO1:DELAY_VARIABLE |
0.3.57 |
IO1:IFF_DELAY_ENABLE |
0.3.38 |
IO1:IFF_LATCH |
0.2.28 |
IO1:IFF_REV_ENABLE |
0.2.30 |
IO1:IFF_SR_ENABLE |
0.2.29 |
IO1:IFF_SR_SYNC |
0.2.31 |
IO1:IFF_TSBYPASS_ENABLE |
0.3.36 |
IO1:INV.O1 |
0.1.27 |
IO1:INV.O2 |
0.1.28 |
IO1:INV.T1 |
0.0.27 |
IO1:INV.T2 |
0.0.28 |
IO1:I_DELAY_ENABLE |
0.3.29 |
IO1:I_TSBYPASS_ENABLE |
0.3.32 |
IO1:MISR_ENABLE |
0.0.33 |
IO1:MISR_RESET |
0.0.32 |
IO1:OFF1_LATCH |
0.1.22 |
IO1:OFF2_LATCH |
0.1.21 |
IO1:OFF_REV_ENABLE |
0.1.30 |
IO1:OFF_SR_ENABLE |
0.1.29 |
IO1:OFF_SR_SYNC |
0.1.26 |
IO1:READBACK_I |
0.3.39 |
IO1:TFF1_LATCH |
0.0.22 |
IO1:TFF2_LATCH |
0.0.21 |
IO1:TFF_REV_ENABLE |
0.0.30 |
IO1:TFF_SR_ENABLE |
0.0.29 |
IO1:TFF_SR_SYNC |
0.0.26 |
non-inverted
|
[0] |
IO0:IDDRIN_MUX |
0.3.21 |
0.3.37 |
0.3.8 |
IO1:IDDRIN_MUX |
0.3.18 |
0.3.2 |
0.3.30 |
NONE |
0 |
0 |
0 |
IFFDMUX |
0 |
0 |
1 |
IDDRIN1 |
0 |
1 |
0 |
IDDRIN2 |
1 |
0 |
0 |
IO0:IFF_DELAY |
0.3.53 |
0.3.51 |
IO1:IFF_DELAY |
0.3.58 |
0.3.47 |
inverted
|
~[1] |
~[0] |
IO0:I_DELAY |
0.3.50 |
0.3.49 |
0.3.52 |
IO1:I_DELAY |
0.3.56 |
0.3.55 |
0.3.54 |
inverted
|
~[2] |
~[1] |
~[0] |
IO0:MISR_CLOCK |
0.0.1 |
0.0.0 |
IO1:MISR_CLOCK |
0.0.38 |
0.0.39 |
NONE |
0 |
0 |
OTCLK1 |
0 |
1 |
OTCLK2 |
1 |
0 |
IO0:O1_DDRMUX |
0.1.35 |
IO1:O1_DDRMUX |
0.1.4 |
O1 |
0 |
ODDRIN1 |
1 |
IO0:O2_DDRMUX |
0.0.37 |
IO1:O2_DDRMUX |
0.0.2 |
O2 |
0 |
ODDRIN2 |
1 |
IO0:OMUX |
0.1.15 |
0.1.19 |
0.1.14 |
0.1.16 |
IO1:OMUX |
0.1.24 |
0.1.20 |
0.1.25 |
0.1.23 |
NONE |
0 |
0 |
0 |
0 |
O1 |
0 |
0 |
0 |
1 |
O2 |
0 |
0 |
1 |
0 |
OFF1 |
0 |
1 |
0 |
0 |
OFF2 |
1 |
0 |
0 |
0 |
OFFDDR |
1 |
1 |
0 |
0 |
IO0:PCICE_MUX |
0.2.0 |
0.1.0 |
IO1:PCICE_MUX |
0.2.39 |
0.1.39 |
NONE |
0 |
0 |
OCE |
0 |
1 |
PCICE |
1 |
0 |
IO0:TMUX |
0.0.15 |
0.0.19 |
0.0.14 |
0.0.16 |
IO1:TMUX |
0.0.24 |
0.0.20 |
0.0.25 |
0.0.23 |
NONE |
0 |
0 |
0 |
0 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
1 |
0 |
TFF1 |
0 |
1 |
0 |
0 |
TFF2 |
1 |
0 |
0 |
0 |
TFFDDR |
1 |
1 |
0 |
0 |
IO0:TSBYPASS_MUX |
0.3.4 |
IO1:TSBYPASS_MUX |
0.3.35 |
TMUX |
0 |
GND |
1 |
IO0:IDDRIN_MUX |
0.3.21 |
0.3.37 |
0.3.8 |
IO1:IDDRIN_MUX |
0.3.18 |
0.3.2 |
0.3.30 |
IO2:IDDRIN_MUX |
0.3.58 |
0.3.42 |
0.3.48 |
NONE |
0 |
0 |
0 |
IFFDMUX |
0 |
0 |
1 |
IDDRIN1 |
0 |
1 |
0 |
IDDRIN2 |
1 |
0 |
0 |
IO0:IFF1_INIT |
0.2.7 |
IO0:IFF1_SRVAL |
0.2.3 |
IO0:IFF2_INIT |
0.2.12 |
IO0:IFF2_SRVAL |
0.2.16 |
IO0:INV.ICE |
0.3.14 |
IO0:INV.ICLK1 |
0.3.13 |
IO0:INV.ICLK2 |
0.3.12 |
IO0:INV.OTCLK1 |
0.3.16 |
IO0:INV.OTCLK2 |
0.3.15 |
IO0:INV.REV |
0.3.11 |
IO0:INV.TCE |
0.3.17 |
IO0:OFF1_SRVAL |
0.1.3 |
IO0:OFF2_SRVAL |
0.1.5 |
IO0:OFF_INIT |
0.1.8 |
IO0:TFF1_SRVAL |
0.0.3 |
IO0:TFF2_SRVAL |
0.0.5 |
IO0:TFF_INIT |
0.0.8 |
IO1:IFF1_INIT |
0.2.32 |
IO1:IFF1_SRVAL |
0.2.36 |
IO1:IFF2_INIT |
0.2.27 |
IO1:IFF2_SRVAL |
0.2.23 |
IO1:INV.ICE |
0.3.25 |
IO1:INV.ICLK1 |
0.3.26 |
IO1:INV.ICLK2 |
0.3.27 |
IO1:INV.OTCLK1 |
0.3.23 |
IO1:INV.OTCLK2 |
0.3.24 |
IO1:INV.REV |
0.3.28 |
IO1:INV.TCE |
0.3.22 |
IO1:OFF1_SRVAL |
0.1.36 |
IO1:OFF2_SRVAL |
0.1.34 |
IO1:OFF_INIT |
0.1.31 |
IO1:TFF1_SRVAL |
0.0.36 |
IO1:TFF2_SRVAL |
0.0.34 |
IO1:TFF_INIT |
0.0.31 |
IO2:IFF1_INIT |
0.2.47 |
IO2:IFF1_SRVAL |
0.2.43 |
IO2:IFF2_INIT |
0.2.52 |
IO2:IFF2_SRVAL |
0.2.56 |
IO2:INV.ICE |
0.3.54 |
IO2:INV.ICLK1 |
0.3.53 |
IO2:INV.ICLK2 |
0.3.52 |
IO2:INV.OTCLK1 |
0.3.56 |
IO2:INV.OTCLK2 |
0.3.55 |
IO2:INV.REV |
0.3.51 |
IO2:INV.TCE |
0.3.57 |
IO2:OFF1_SRVAL |
0.1.43 |
IO2:OFF2_SRVAL |
0.1.45 |
IO2:OFF_INIT |
0.1.48 |
IO2:TFF1_SRVAL |
0.0.43 |
IO2:TFF2_SRVAL |
0.0.45 |
IO2:TFF_INIT |
0.0.48 |
inverted
|
~[0] |
IO0:IFF_DELAY_ENABLE |
0.3.1 |
IO0:IFF_LATCH |
0.2.11 |
IO0:IFF_REV_ENABLE |
0.2.9 |
IO0:IFF_SR_ENABLE |
0.2.10 |
IO0:IFF_SR_SYNC |
0.2.8 |
IO0:IFF_TSBYPASS_ENABLE |
0.3.3 |
IO0:INV.O1 |
0.1.12 |
IO0:INV.O2 |
0.1.11 |
IO0:INV.T1 |
0.0.12 |
IO0:INV.T2 |
0.0.11 |
IO0:I_DELAY_ENABLE |
0.3.10 |
IO0:I_TSBYPASS_ENABLE |
0.3.7 |
IO0:MISR_ENABLE |
0.0.6 |
IO0:MISR_RESET |
0.0.7 |
IO0:OFF1_LATCH |
0.1.17 |
IO0:OFF2_LATCH |
0.1.18 |
IO0:OFF_REV_ENABLE |
0.1.9 |
IO0:OFF_SR_ENABLE |
0.1.10 |
IO0:OFF_SR_SYNC |
0.1.13 |
IO0:READBACK_I |
0.3.0 |
IO0:TFF1_LATCH |
0.0.17 |
IO0:TFF2_LATCH |
0.0.18 |
IO0:TFF_REV_ENABLE |
0.0.9 |
IO0:TFF_SR_ENABLE |
0.0.10 |
IO0:TFF_SR_SYNC |
0.0.13 |
IO1:IFF_DELAY_ENABLE |
0.3.38 |
IO1:IFF_LATCH |
0.2.28 |
IO1:IFF_REV_ENABLE |
0.2.30 |
IO1:IFF_SR_ENABLE |
0.2.29 |
IO1:IFF_SR_SYNC |
0.2.31 |
IO1:IFF_TSBYPASS_ENABLE |
0.3.36 |
IO1:INV.O1 |
0.1.27 |
IO1:INV.O2 |
0.1.28 |
IO1:INV.T1 |
0.0.27 |
IO1:INV.T2 |
0.0.28 |
IO1:I_DELAY_ENABLE |
0.3.29 |
IO1:I_TSBYPASS_ENABLE |
0.3.32 |
IO1:MISR_ENABLE |
0.0.33 |
IO1:MISR_RESET |
0.0.32 |
IO1:OFF1_LATCH |
0.1.22 |
IO1:OFF2_LATCH |
0.1.21 |
IO1:OFF_REV_ENABLE |
0.1.30 |
IO1:OFF_SR_ENABLE |
0.1.29 |
IO1:OFF_SR_SYNC |
0.1.26 |
IO1:READBACK_I |
0.3.39 |
IO1:TFF1_LATCH |
0.0.22 |
IO1:TFF2_LATCH |
0.0.21 |
IO1:TFF_REV_ENABLE |
0.0.30 |
IO1:TFF_SR_ENABLE |
0.0.29 |
IO1:TFF_SR_SYNC |
0.0.26 |
IO2:IFF_DELAY_ENABLE |
0.3.41 |
IO2:IFF_LATCH |
0.2.51 |
IO2:IFF_REV_ENABLE |
0.2.49 |
IO2:IFF_SR_ENABLE |
0.2.50 |
IO2:IFF_SR_SYNC |
0.2.48 |
IO2:IFF_TSBYPASS_ENABLE |
0.3.43 |
IO2:INV.O1 |
0.1.52 |
IO2:INV.O2 |
0.1.51 |
IO2:INV.T1 |
0.0.52 |
IO2:INV.T2 |
0.0.51 |
IO2:I_DELAY_ENABLE |
0.3.50 |
IO2:I_TSBYPASS_ENABLE |
0.3.47 |
IO2:MISR_ENABLE |
0.0.46 |
IO2:MISR_RESET |
0.0.47 |
IO2:OFF1_LATCH |
0.1.57 |
IO2:OFF2_LATCH |
0.1.58 |
IO2:OFF_REV_ENABLE |
0.1.49 |
IO2:OFF_SR_ENABLE |
0.1.50 |
IO2:OFF_SR_SYNC |
0.1.53 |
IO2:READBACK_I |
0.3.40 |
IO2:TFF1_LATCH |
0.0.57 |
IO2:TFF2_LATCH |
0.0.58 |
IO2:TFF_REV_ENABLE |
0.0.49 |
IO2:TFF_SR_ENABLE |
0.0.50 |
IO2:TFF_SR_SYNC |
0.0.53 |
non-inverted
|
[0] |
IO0:MISR_CLOCK |
0.0.1 |
0.0.0 |
IO1:MISR_CLOCK |
0.0.38 |
0.0.39 |
IO2:MISR_CLOCK |
0.0.41 |
0.0.40 |
NONE |
0 |
0 |
OTCLK1 |
0 |
1 |
OTCLK2 |
1 |
0 |
IO0:O1_DDRMUX |
0.1.35 |
IO1:O1_DDRMUX |
0.1.4 |
O1 |
0 |
ODDRIN1 |
1 |
IO0:O2_DDRMUX |
0.0.37 |
IO1:O2_DDRMUX |
0.0.2 |
O2 |
0 |
ODDRIN2 |
1 |
IO0:OMUX |
0.1.15 |
0.1.19 |
0.1.14 |
0.1.16 |
IO1:OMUX |
0.1.24 |
0.1.20 |
0.1.25 |
0.1.23 |
IO2:OMUX |
0.1.55 |
0.1.59 |
0.1.54 |
0.1.56 |
NONE |
0 |
0 |
0 |
0 |
O1 |
0 |
0 |
0 |
1 |
O2 |
0 |
0 |
1 |
0 |
OFF1 |
0 |
1 |
0 |
0 |
OFF2 |
1 |
0 |
0 |
0 |
OFFDDR |
1 |
1 |
0 |
0 |
IO0:PCICE_MUX |
0.2.0 |
0.1.0 |
IO1:PCICE_MUX |
0.2.39 |
0.1.39 |
IO2:PCICE_MUX |
0.2.40 |
0.1.40 |
NONE |
0 |
0 |
OCE |
0 |
1 |
PCICE |
1 |
0 |
IO0:TMUX |
0.0.15 |
0.0.19 |
0.0.14 |
0.0.16 |
IO1:TMUX |
0.0.24 |
0.0.20 |
0.0.25 |
0.0.23 |
IO2:TMUX |
0.0.55 |
0.0.59 |
0.0.54 |
0.0.56 |
NONE |
0 |
0 |
0 |
0 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
1 |
0 |
TFF1 |
0 |
1 |
0 |
0 |
TFF2 |
1 |
0 |
0 |
0 |
TFFDDR |
1 |
1 |
0 |
0 |
IO0:TSBYPASS_MUX |
0.3.4 |
IO1:TSBYPASS_MUX |
0.3.35 |
IO2:TSBYPASS_MUX |
0.3.44 |
TMUX |
0 |
GND |
1 |
IO0:IDDRIN_MUX |
0.3.21 |
0.3.37 |
0.3.8 |
IO1:IDDRIN_MUX |
0.3.18 |
0.3.2 |
0.3.30 |
IO2:IDDRIN_MUX |
0.3.58 |
0.3.42 |
0.3.48 |
NONE |
0 |
0 |
0 |
IFFDMUX |
0 |
0 |
1 |
IDDRIN1 |
0 |
1 |
0 |
IDDRIN2 |
1 |
0 |
0 |
IO0:IFF1_INIT |
0.2.7 |
IO0:IFF1_SRVAL |
0.2.3 |
IO0:IFF2_INIT |
0.2.12 |
IO0:IFF2_SRVAL |
0.2.16 |
IO0:INV.ICE |
0.3.14 |
IO0:INV.ICLK1 |
0.3.13 |
IO0:INV.ICLK2 |
0.3.12 |
IO0:INV.OTCLK1 |
0.3.16 |
IO0:INV.OTCLK2 |
0.3.15 |
IO0:INV.REV |
0.3.11 |
IO0:INV.TCE |
0.3.17 |
IO0:OFF1_SRVAL |
0.1.3 |
IO0:OFF2_SRVAL |
0.1.5 |
IO0:OFF_INIT |
0.1.8 |
IO0:TFF1_SRVAL |
0.0.3 |
IO0:TFF2_SRVAL |
0.0.5 |
IO0:TFF_INIT |
0.0.8 |
IO1:IFF1_INIT |
0.2.32 |
IO1:IFF1_SRVAL |
0.2.36 |
IO1:IFF2_INIT |
0.2.27 |
IO1:IFF2_SRVAL |
0.2.23 |
IO1:INV.ICE |
0.3.25 |
IO1:INV.ICLK1 |
0.3.26 |
IO1:INV.ICLK2 |
0.3.27 |
IO1:INV.OTCLK1 |
0.3.23 |
IO1:INV.OTCLK2 |
0.3.24 |
IO1:INV.REV |
0.3.28 |
IO1:INV.TCE |
0.3.22 |
IO1:OFF1_SRVAL |
0.1.36 |
IO1:OFF2_SRVAL |
0.1.34 |
IO1:OFF_INIT |
0.1.31 |
IO1:TFF1_SRVAL |
0.0.36 |
IO1:TFF2_SRVAL |
0.0.34 |
IO1:TFF_INIT |
0.0.31 |
IO2:IFF1_INIT |
0.2.47 |
IO2:IFF1_SRVAL |
0.2.43 |
IO2:IFF2_INIT |
0.2.52 |
IO2:IFF2_SRVAL |
0.2.56 |
IO2:INV.ICE |
0.3.54 |
IO2:INV.ICLK1 |
0.3.53 |
IO2:INV.ICLK2 |
0.3.52 |
IO2:INV.OTCLK1 |
0.3.56 |
IO2:INV.OTCLK2 |
0.3.55 |
IO2:INV.REV |
0.3.51 |
IO2:INV.TCE |
0.3.57 |
IO2:OFF1_SRVAL |
0.1.43 |
IO2:OFF2_SRVAL |
0.1.45 |
IO2:OFF_INIT |
0.1.48 |
IO2:TFF1_SRVAL |
0.0.43 |
IO2:TFF2_SRVAL |
0.0.45 |
IO2:TFF_INIT |
0.0.48 |
inverted
|
~[0] |
IO0:IFF_DELAY_ENABLE |
0.3.1 |
IO0:IFF_LATCH |
0.2.11 |
IO0:IFF_REV_ENABLE |
0.2.9 |
IO0:IFF_SR_ENABLE |
0.2.10 |
IO0:IFF_SR_SYNC |
0.2.8 |
IO0:IFF_TSBYPASS_ENABLE |
0.3.3 |
IO0:INV.O1 |
0.1.12 |
IO0:INV.O2 |
0.1.11 |
IO0:INV.T1 |
0.0.12 |
IO0:INV.T2 |
0.0.11 |
IO0:I_DELAY_ENABLE |
0.3.10 |
IO0:I_TSBYPASS_ENABLE |
0.3.7 |
IO0:MISR_ENABLE |
0.0.6 |
IO0:MISR_RESET |
0.0.7 |
IO0:OFF1_LATCH |
0.1.17 |
IO0:OFF2_LATCH |
0.1.18 |
IO0:OFF_REV_ENABLE |
0.1.9 |
IO0:OFF_SR_ENABLE |
0.1.10 |
IO0:OFF_SR_SYNC |
0.1.13 |
IO0:READBACK_I |
0.3.0 |
IO0:TFF1_LATCH |
0.0.17 |
IO0:TFF2_LATCH |
0.0.18 |
IO0:TFF_REV_ENABLE |
0.0.9 |
IO0:TFF_SR_ENABLE |
0.0.10 |
IO0:TFF_SR_SYNC |
0.0.13 |
IO1:IFF_DELAY_ENABLE |
0.3.38 |
IO1:IFF_LATCH |
0.2.28 |
IO1:IFF_REV_ENABLE |
0.2.30 |
IO1:IFF_SR_ENABLE |
0.2.29 |
IO1:IFF_SR_SYNC |
0.2.31 |
IO1:IFF_TSBYPASS_ENABLE |
0.3.36 |
IO1:INV.O1 |
0.1.27 |
IO1:INV.O2 |
0.1.28 |
IO1:INV.T1 |
0.0.27 |
IO1:INV.T2 |
0.0.28 |
IO1:I_DELAY_ENABLE |
0.3.29 |
IO1:I_TSBYPASS_ENABLE |
0.3.32 |
IO1:MISR_ENABLE |
0.0.33 |
IO1:MISR_RESET |
0.0.32 |
IO1:OFF1_LATCH |
0.1.22 |
IO1:OFF2_LATCH |
0.1.21 |
IO1:OFF_REV_ENABLE |
0.1.30 |
IO1:OFF_SR_ENABLE |
0.1.29 |
IO1:OFF_SR_SYNC |
0.1.26 |
IO1:READBACK_I |
0.3.39 |
IO1:TFF1_LATCH |
0.0.22 |
IO1:TFF2_LATCH |
0.0.21 |
IO1:TFF_REV_ENABLE |
0.0.30 |
IO1:TFF_SR_ENABLE |
0.0.29 |
IO1:TFF_SR_SYNC |
0.0.26 |
IO2:IFF_DELAY_ENABLE |
0.3.41 |
IO2:IFF_LATCH |
0.2.51 |
IO2:IFF_REV_ENABLE |
0.2.49 |
IO2:IFF_SR_ENABLE |
0.2.50 |
IO2:IFF_SR_SYNC |
0.2.48 |
IO2:IFF_TSBYPASS_ENABLE |
0.3.43 |
IO2:INV.O1 |
0.1.52 |
IO2:INV.O2 |
0.1.51 |
IO2:INV.T1 |
0.0.52 |
IO2:INV.T2 |
0.0.51 |
IO2:I_DELAY_ENABLE |
0.3.50 |
IO2:I_TSBYPASS_ENABLE |
0.3.47 |
IO2:MISR_ENABLE |
0.0.46 |
IO2:MISR_RESET |
0.0.47 |
IO2:OFF1_LATCH |
0.1.57 |
IO2:OFF2_LATCH |
0.1.58 |
IO2:OFF_REV_ENABLE |
0.1.49 |
IO2:OFF_SR_ENABLE |
0.1.50 |
IO2:OFF_SR_SYNC |
0.1.53 |
IO2:READBACK_I |
0.3.40 |
IO2:TFF1_LATCH |
0.0.57 |
IO2:TFF2_LATCH |
0.0.58 |
IO2:TFF_REV_ENABLE |
0.0.49 |
IO2:TFF_SR_ENABLE |
0.0.50 |
IO2:TFF_SR_SYNC |
0.0.53 |
non-inverted
|
[0] |
IO0:MISR_CLOCK |
0.0.1 |
0.0.0 |
IO1:MISR_CLOCK |
0.0.38 |
0.0.39 |
IO2:MISR_CLOCK |
0.0.41 |
0.0.40 |
NONE |
0 |
0 |
OTCLK1 |
0 |
1 |
OTCLK2 |
1 |
0 |
IO0:O1_DDRMUX |
0.1.35 |
IO1:O1_DDRMUX |
0.1.4 |
O1 |
0 |
ODDRIN1 |
1 |
IO0:O2_DDRMUX |
0.0.37 |
IO1:O2_DDRMUX |
0.0.2 |
O2 |
0 |
ODDRIN2 |
1 |
IO0:OMUX |
0.1.15 |
0.1.19 |
0.1.14 |
0.1.16 |
IO1:OMUX |
0.1.24 |
0.1.20 |
0.1.25 |
0.1.23 |
IO2:OMUX |
0.1.55 |
0.1.59 |
0.1.54 |
0.1.56 |
NONE |
0 |
0 |
0 |
0 |
O1 |
0 |
0 |
0 |
1 |
O2 |
0 |
0 |
1 |
0 |
OFF1 |
0 |
1 |
0 |
0 |
OFF2 |
1 |
0 |
0 |
0 |
OFFDDR |
1 |
1 |
0 |
0 |
IO0:PCICE_MUX |
0.2.0 |
0.1.0 |
IO1:PCICE_MUX |
0.2.39 |
0.1.39 |
IO2:PCICE_MUX |
0.2.40 |
0.1.40 |
NONE |
0 |
0 |
OCE |
0 |
1 |
PCICE |
1 |
0 |
IO0:TMUX |
0.0.15 |
0.0.19 |
0.0.14 |
0.0.16 |
IO1:TMUX |
0.0.24 |
0.0.20 |
0.0.25 |
0.0.23 |
IO2:TMUX |
0.0.55 |
0.0.59 |
0.0.54 |
0.0.56 |
NONE |
0 |
0 |
0 |
0 |
T1 |
0 |
0 |
0 |
1 |
T2 |
0 |
0 |
1 |
0 |
TFF1 |
0 |
1 |
0 |
0 |
TFF2 |
1 |
0 |
0 |
0 |
TFFDDR |
1 |
1 |
0 |
0 |
IO0:TSBYPASS_MUX |
0.3.4 |
IO1:TSBYPASS_MUX |
0.3.35 |
IO2:TSBYPASS_MUX |
0.3.44 |
TMUX |
0 |
GND |
1 |