I/O Buffers (Spartan 3)
TODO: document
Name | IOSTD:S3:PDRIVE | IOSTD:S3:NDRIVE | ||||||
---|---|---|---|---|---|---|---|---|
[3] | [2] | [1] | [0] | [3] | [2] | [1] | [0] | |
BLVDS_25 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
GTL | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
GTLP | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
GTLP_DCI | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
GTL_DCI | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
HSTL_I | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
HSTL_III | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
HSTL_III_18 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
HSTL_III_DCI | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
HSTL_III_DCI_18 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
HSTL_II_18 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |
HSTL_II_DCI_18 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |
HSTL_I_18 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
HSTL_I_DCI | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
HSTL_I_DCI_18 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
LVCMOS12.2 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 |
LVCMOS12.4 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
LVCMOS12.6 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
LVCMOS15.12 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
LVCMOS15.2 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
LVCMOS15.4 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
LVCMOS15.6 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
LVCMOS15.8 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
LVCMOS18.12 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
LVCMOS18.16 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |
LVCMOS18.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVCMOS18.4 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
LVCMOS18.6 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
LVCMOS18.8 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
LVCMOS25.12 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
LVCMOS25.16 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
LVCMOS25.2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
LVCMOS25.24 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 |
LVCMOS25.4 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
LVCMOS25.6 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
LVCMOS25.8 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
LVCMOS33.12 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
LVCMOS33.16 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
LVCMOS33.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
LVCMOS33.24 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
LVCMOS33.4 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
LVCMOS33.6 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
LVCMOS33.8 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
LVPECL_25 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
LVTTL.12 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
LVTTL.16 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |
LVTTL.2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
LVTTL.24 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
LVTTL.4 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
LVTTL.6 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
LVTTL.8 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
PCI66_3 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
SSTL18_I | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
SSTL18_II | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
SSTL18_I_DCI | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
SSTL2_I | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
SSTL2_II | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
SSTL2_II_DCI | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
SSTL2_I_DCI | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
Name | IOSTD:S3:SLEW | ||||
---|---|---|---|---|---|
[4] | [3] | [2] | [1] | [0] | |
BLVDS_25 | 0 | 0 | 0 | 0 | 0 |
GTL | 1 | 1 | 1 | 1 | 1 |
GTLP | 1 | 1 | 1 | 1 | 1 |
GTLP_DCI | 1 | 1 | 1 | 1 | 1 |
GTL_DCI | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_15 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_18 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_25 | 1 | 1 | 1 | 1 | 1 |
HSLVDCI_33 | 1 | 1 | 1 | 1 | 1 |
HSTL_I | 1 | 1 | 1 | 1 | 1 |
HSTL_III | 1 | 1 | 1 | 1 | 1 |
HSTL_III_18 | 1 | 1 | 1 | 1 | 1 |
HSTL_III_DCI | 1 | 1 | 1 | 1 | 1 |
HSTL_III_DCI_18 | 1 | 1 | 1 | 1 | 1 |
HSTL_II_18 | 1 | 1 | 1 | 1 | 1 |
HSTL_II_DCI_18 | 1 | 1 | 1 | 1 | 1 |
HSTL_I_18 | 1 | 1 | 1 | 1 | 1 |
HSTL_I_DCI | 1 | 1 | 1 | 1 | 1 |
HSTL_I_DCI_18 | 1 | 1 | 1 | 1 | 1 |
LVCMOS12.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS12.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS15.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS15.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS18.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS18.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS25.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS25.SLOW | 0 | 0 | 0 | 0 | 0 |
LVCMOS33.FAST | 1 | 1 | 1 | 1 | 1 |
LVCMOS33.SLOW | 0 | 0 | 0 | 0 | 0 |
LVDCI_15 | 1 | 1 | 1 | 1 | 1 |
LVDCI_18 | 1 | 1 | 1 | 1 | 1 |
LVDCI_25 | 1 | 1 | 1 | 1 | 1 |
LVDCI_33 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_15 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_18 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_25 | 1 | 1 | 1 | 1 | 1 |
LVDCI_DV2_33 | 1 | 1 | 1 | 1 | 1 |
LVPECL_25 | 1 | 1 | 1 | 1 | 1 |
LVTTL.FAST | 1 | 1 | 1 | 1 | 1 |
LVTTL.SLOW | 0 | 0 | 0 | 0 | 0 |
PCI33_3 | 0 | 0 | 0 | 0 | 0 |
PCI66_3 | 0 | 0 | 0 | 0 | 0 |
SSTL18_I | 1 | 1 | 1 | 1 | 1 |
SSTL18_II | 1 | 1 | 1 | 1 | 1 |
SSTL18_I_DCI | 1 | 1 | 1 | 1 | 1 |
SSTL2_I | 1 | 1 | 1 | 1 | 1 |
SSTL2_II | 1 | 1 | 1 | 1 | 1 |
SSTL2_II_DCI | 1 | 1 | 1 | 1 | 1 |
SSTL2_I_DCI | 1 | 1 | 1 | 1 | 1 |
VR | 0 | 0 | 0 | 0 | 0 |
Name | IOSTD:S3:OUTPUT_MISC | |
---|---|---|
[1] | [0] | |
BLVDS_25 | 0 | 1 |
GTL | 0 | 0 |
GTLP | 0 | 0 |
GTLP_DCI | 0 | 0 |
GTL_DCI | 0 | 0 |
HSLVDCI_15 | 0 | 0 |
HSLVDCI_18 | 0 | 0 |
HSLVDCI_25 | 0 | 0 |
HSLVDCI_33 | 0 | 0 |
HSTL_I | 1 | 1 |
HSTL_III | 1 | 1 |
HSTL_III_18 | 1 | 1 |
HSTL_III_DCI | 1 | 1 |
HSTL_III_DCI_18 | 1 | 1 |
HSTL_II_18 | 1 | 1 |
HSTL_II_DCI_18 | 1 | 1 |
HSTL_I_18 | 1 | 1 |
HSTL_I_DCI | 1 | 1 |
HSTL_I_DCI_18 | 1 | 1 |
LVCMOS12 | 0 | 1 |
LVCMOS15 | 0 | 1 |
LVCMOS18 | 0 | 1 |
LVCMOS25 | 0 | 1 |
LVCMOS33 | 0 | 1 |
LVDCI_15 | 0 | 0 |
LVDCI_18 | 0 | 0 |
LVDCI_25 | 0 | 0 |
LVDCI_33 | 0 | 0 |
LVDCI_DV2_15 | 0 | 0 |
LVDCI_DV2_18 | 0 | 0 |
LVDCI_DV2_25 | 0 | 0 |
LVDCI_DV2_33 | 0 | 0 |
LVPECL_25 | 0 | 1 |
LVTTL | 0 | 1 |
PCI33_3 | 0 | 0 |
PCI66_3 | 0 | 0 |
SSTL18_I | 0 | 0 |
SSTL18_II | 0 | 0 |
SSTL18_I_DCI | 0 | 0 |
SSTL2_I | 0 | 0 |
SSTL2_II | 0 | 0 |
SSTL2_II_DCI | 0 | 0 |
SSTL2_I_DCI | 0 | 0 |
Name | IOSTD:S3:OUTPUT_DIFF | ||
---|---|---|---|
[2] | [1] | [0] | |
LDT_25 | 1 | 0 | 1 |
LVDSEXT_25 | 0 | 1 | 1 |
LVDSEXT_25_DCI | 0 | 1 | 1 |
LVDS_25 | 0 | 0 | 1 |
LVDS_25_DCI | 0 | 0 | 1 |
OFF | 0 | 0 | 0 |
RSDS_25 | 0 | 0 | 1 |
ULVDS_25 | 1 | 0 | 1 |
Name | IOSTD:S3:LVDSBIAS | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
[12] | [11] | [10] | [9] | [8] | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] | |
LDT_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
LVDSEXT_25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
LVDSEXT_25_DCI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
LVDS_25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
LVDS_25_DCI | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RSDS_25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
ULVDS_25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
Name | IOSTD:S3:PMASK_TERM_SPLIT | IOSTD:S3:NMASK_TERM_SPLIT | ||||||
---|---|---|---|---|---|---|---|---|
[3] | [2] | [1] | [0] | [3] | [2] | [1] | [0] | |
HSTL_II_DCI_18 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
HSTL_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
HSTL_I_DCI_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
LVDSEXT_25_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
LVDS_25_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
OFF | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
SSTL18_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
SSTL2_II_DCI | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 |
SSTL2_I_DCI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Name | IOSTD:S3:PMASK_TERM_VCC | |||
---|---|---|---|---|
[3] | [2] | [1] | [0] | |
GTLP_DCI | 0 | 0 | 0 | 0 |
GTL_DCI | 0 | 0 | 0 | 0 |
HSTL_III_DCI | 0 | 0 | 0 | 0 |
HSTL_III_DCI_18 | 0 | 0 | 0 | 0 |
OFF | 0 | 0 | 0 | 0 |
IOBS.S3.T2
IOB0:DCIUPDATEMODE_ASREQUIRED | 0.14.3 |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | 0.9.2 |
IOB2:DCIUPDATEMODE_ASREQUIRED | 1.18.3 |
IOB3:DCIUPDATEMODE_ASREQUIRED | 1.13.2 |
IOB4:DCIUPDATEMODE_ASREQUIRED | 1.3.0 |
inverted | ~[0] |
IOB0:DCI_MODE | 0.12.4 | 0.18.1 | 0.17.2 | 0.13.4 |
---|---|---|---|---|
IOB1:DCI_MODE | 0.11.4 | 0.6.0 | 0.8.0 | 0.11.0 |
IOB2:DCI_MODE | 1.17.2 | 0.4.0 | 0.4.4 | 1.16.2 |
IOB3:DCI_MODE | 1.12.3 | 1.8.0 | 1.9.1 | 1.14.3 |
IOB4:DCI_MODE | 1.3.4 | 1.7.2 | 1.6.1 | 1.2.4 |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | 0.14.1 |
---|---|
IOB0:VREF | 0.12.3 |
IOB1:DISABLE_GTS | 0.9.4 |
IOB1:VR | 0.3.1 |
IOB1:VREF | 0.11.2 |
IOB2:DISABLE_GTS | 1.17.0 |
IOB2:VR | 0.1.3 |
IOB2:VREF | 1.17.4 |
IOB3:DISABLE_GTS | 1.13.0 |
IOB3:VR | 1.10.2 |
IOB3:VREF | 1.12.2 |
IOB4:DISABLE_GTS | 1.3.2 |
IOB4:VR | 1.4.4 |
IOB4:VREF | 1.2.0 |
non-inverted | [0] |
IOB0:IBUF_MODE | 0.17.0 | 0.16.0 | 0.15.4 |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:NDRIVE | 0.12.2 | 0.16.4 | 0.13.1 | 0.14.0 |
---|---|---|---|---|
IOB1:NDRIVE | 0.6.4 | 0.7.0 | 0.10.2 | 0.5.3 |
IOB2:NDRIVE | 1.17.3 | 0.2.2 | 1.15.0 | 1.17.1 |
IOB3:NDRIVE | 1.12.1 | 1.11.0 | 1.14.2 | 1.12.4 |
IOB4:NDRIVE | 1.2.1 | 1.6.4 | 1.1.2 | 1.3.3 |
mixed inversion | [3] | ~[2] | [1] | [0] |
IOB0:OUTPUT_ENABLE | 0.18.4 | 0.18.2 |
---|---|---|
IOB0:OUTPUT_MISC | 0.15.2 | 0.14.2 |
IOB1:OUTPUT_ENABLE | 0.6.1 | 0.5.0 |
IOB1:OUTPUT_MISC | 0.3.3 | 0.9.3 |
IOB2:OUTPUT_ENABLE | 0.6.3 | 0.5.2 |
IOB2:OUTPUT_MISC | 0.1.4 | 1.18.4 |
IOB3:OUTPUT_ENABLE | 1.8.3 | 1.8.1 |
IOB3:OUTPUT_MISC | 1.10.1 | 1.13.1 |
IOB4:OUTPUT_ENABLE | 1.8.4 | 1.7.1 |
IOB4:OUTPUT_MISC | 1.5.1 | 1.3.1 |
non-inverted | [1] | [0] |
IOB0:PDRIVE | 0.12.1 | 0.17.4 | 0.13.3 | 0.17.1 |
---|---|---|---|---|
IOB1:PDRIVE | 0.11.1 | 0.8.3 | 0.10.0 | 0.8.1 |
IOB2:PDRIVE | 1.16.0 | 0.4.1 | 1.16.3 | 0.2.0 |
IOB3:PDRIVE | 1.12.0 | 1.9.3 | 1.14.1 | 1.9.0 |
IOB4:PDRIVE | 1.2.2 | 1.7.4 | 1.1.0 | 1.6.2 |
mixed inversion | [3] | ~[2] | [1] | ~[0] |
IOB0:PULL | 0.12.0 | 0.13.0 | 0.13.2 |
---|---|---|---|
IOB1:PULL | 0.7.2 | 0.11.3 | 0.10.1 |
IOB2:PULL | 1.16.1 | 1.15.2 | 1.16.4 |
IOB3:PULL | 1.14.4 | 1.15.4 | 1.14.0 |
IOB4:PULL | 1.2.3 | 1.1.3 | 1.1.1 |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:SLEW | 0.18.3 | 0.18.0 | 0.17.3 | 0.16.3 | 0.16.2 |
---|---|---|---|---|---|
IOB1:SLEW | 0.8.4 | 0.7.3 | 0.7.1 | 0.5.4 | 0.5.1 |
IOB2:SLEW | 0.6.2 | 0.4.3 | 0.4.2 | 0.2.4 | 0.2.3 |
IOB3:SLEW | 1.11.3 | 1.11.1 | 1.9.4 | 1.9.2 | 1.8.2 |
IOB4:SLEW | 1.7.3 | 1.7.0 | 1.6.0 | 1.5.0 | 1.4.0 |
non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB1:IBUF_MODE | 0.8.2 | 0.3.0 | 0.3.2 |
---|---|---|---|
IOB2:IBUF_MODE | 0.2.1 | 0.1.1 | 0.1.2 |
IOB3:IBUF_MODE | 1.11.4 | 1.10.4 | 1.10.3 |
IOB4:IBUF_MODE | 1.6.3 | 1.4.2 | 1.4.3 |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB2:OUTPUT_DIFF | 0.3.4 | 1.18.2 | 1.18.0 |
---|---|---|---|
IOB4:OUTPUT_DIFF | 1.10.0 | 1.5.4 | 1.5.2 |
non-inverted | [2] | [1] | [0] |
IOBS.S3.R1
IOB0:DCIUPDATEMODE_ASREQUIRED | 0.1.51 |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | 0.1.13 |
inverted | ~[0] |
IOB0:DCI_MODE | 0.1.54 | 0.1.35 | 0.0.39 | 0.1.62 |
---|---|---|---|---|
IOB1:DCI_MODE | 0.1.9 | 0.1.28 | 0.1.25 | 0.1.5 |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | 0.0.52 |
---|---|
IOB0:VR | 0.0.46 |
IOB0:VREF | 0.1.55 |
IOB1:DISABLE_GTS | 0.1.11 |
IOB1:VR | 0.1.17 |
IOB1:VREF | 0.1.8 |
non-inverted | [0] |
IOB0:IBUF_MODE | 0.1.40 | 0.1.45 | 0.1.46 |
---|---|---|---|
IOB1:IBUF_MODE | 0.1.23 | 0.1.19 | 0.1.18 |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:NDRIVE | 0.1.56 | 0.1.41 | 0.0.58 | 0.1.53 |
---|---|---|---|---|
IOB1:NDRIVE | 0.1.7 | 0.1.20 | 0.1.2 | 0.1.10 |
mixed inversion | [3] | ~[2] | [1] | [0] |
IOB0:OUTPUT_ENABLE | 0.1.34 | 0.1.32 |
---|---|---|
IOB0:OUTPUT_MISC | 0.1.47 | 0.1.52 |
IOB1:OUTPUT_ENABLE | 0.1.31 | 0.1.29 |
IOB1:OUTPUT_MISC | 0.1.16 | 0.1.12 |
non-inverted | [1] | [0] |
IOB0:PDRIVE | 0.1.57 | 0.1.37 | 0.1.61 | 0.1.39 |
---|---|---|---|---|
IOB1:PDRIVE | 0.0.7 | 0.0.26 | 0.1.4 | 0.1.24 |
mixed inversion | [3] | ~[2] | [1] | ~[0] |
IOB0:PULL | 0.1.58 | 0.1.59 | 0.1.63 |
---|---|---|---|
IOB1:PULL | 0.1.6 | 0.1.1 | 0.1.3 |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:SLEW | 0.1.43 | 0.1.42 | 0.1.38 | 0.1.36 | 0.1.33 |
---|---|---|---|---|---|
IOB1:SLEW | 0.1.30 | 0.1.27 | 0.1.26 | 0.1.21 | 0.0.20 |
non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | 0.1.48 | 0.1.14 | 0.1.15 |
---|---|---|---|
non-inverted | [2] | [1] | [0] |
IOBS.S3.B2
IOB0:DCIUPDATEMODE_ASREQUIRED | 1.5.1 |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | 1.10.0 |
IOB2:DCIUPDATEMODE_ASREQUIRED | 0.1.3 |
IOB3:DCIUPDATEMODE_ASREQUIRED | 0.7.2 |
IOB4:DCIUPDATEMODE_ASREQUIRED | 0.16.4 |
inverted | ~[0] |
IOB0:DCI_MODE | 1.6.0 | 1.1.3 | 1.2.2 | 1.7.0 |
---|---|---|---|---|
IOB1:DCI_MODE | 1.11.1 | 1.14.3 | 1.12.4 | 1.9.2 |
IOB2:DCI_MODE | 0.2.2 | 1.16.0 | 1.16.4 | 0.3.2 |
IOB3:DCI_MODE | 0.6.3 | 0.10.1 | 0.11.1 | 0.5.4 |
IOB4:DCI_MODE | 0.16.3 | 0.13.1 | 0.12.1 | 0.17.4 |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | 1.5.3 |
---|---|
IOB0:VREF | 1.6.1 |
IOB1:DISABLE_GTS | 1.11.3 |
IOB1:VR | 1.13.0 |
IOB2:DISABLE_GTS | 0.2.0 |
IOB2:VR | 1.18.3 |
IOB3:DISABLE_GTS | 0.7.0 |
IOB3:VREF | 0.6.2 |
IOB4:DISABLE_GTS | 0.16.1 |
IOB4:VREF | 0.17.0 |
non-inverted | [0] |
IOB0:IBUF_MODE | 1.2.4 | 1.4.0 | 1.3.4 |
---|---|---|---|
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:NDRIVE | 1.6.2 | 1.3.0 | 1.7.4 | 1.5.4 |
---|---|---|---|---|
IOB1:NDRIVE | 1.9.4 | 1.12.1 | 1.8.4 | 1.11.2 |
IOB2:NDRIVE | 0.2.4 | 1.17.2 | 0.4.0 | 0.2.1 |
IOB3:NDRIVE | 0.6.1 | 0.9.4 | 0.5.0 | 0.6.4 |
IOB4:NDRIVE | 0.17.1 | 0.12.4 | 0.18.2 | 0.16.2 |
mixed inversion | [3] | ~[2] | [1] | [0] |
IOB0:OUTPUT_ENABLE | 1.1.2 | 1.1.0 |
---|---|---|
IOB0:OUTPUT_MISC | 1.4.2 | 1.5.2 |
IOB1:OUTPUT_ENABLE | 1.15.4 | 1.14.4 |
IOB1:OUTPUT_MISC | 1.10.4 | 1.11.4 |
IOB2:OUTPUT_ENABLE | 1.15.3 | 1.15.1 |
IOB2:OUTPUT_MISC | 1.18.4 | 0.1.4 |
IOB3:OUTPUT_ENABLE | 0.13.0 | 0.11.4 |
IOB3:OUTPUT_MISC | 0.8.1 | 0.7.1 |
IOB4:OUTPUT_ENABLE | 0.13.2 | 0.10.4 |
IOB4:OUTPUT_MISC | 0.15.1 | 0.16.0 |
non-inverted | [1] | [0] |
IOB0:PDRIVE | 1.6.3 | 1.2.0 | 1.7.1 | 1.2.3 |
---|---|---|---|---|
IOB1:PDRIVE | 1.9.3 | 1.14.1 | 1.9.1 | 1.12.3 |
IOB2:PDRIVE | 0.3.0 | 1.16.2 | 0.3.3 | 1.17.0 |
IOB3:PDRIVE | 0.6.0 | 0.11.2 | 0.5.2 | 0.11.0 |
IOB4:PDRIVE | 0.17.2 | 0.13.3 | 0.18.0 | 0.12.2 |
mixed inversion | [3] | ~[2] | [1] | ~[0] |
IOB0:PULL | 1.6.4 | 1.8.0 | 1.7.2 |
---|---|---|---|
IOB1:PULL | 1.9.0 | 1.8.3 | 1.7.3 |
IOB2:PULL | 0.3.1 | 0.4.1 | 0.3.4 |
IOB3:PULL | 0.5.3 | 0.4.4 | 0.5.1 |
IOB4:PULL | 0.17.3 | 0.18.3 | 0.18.1 |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:SLEW | 1.3.2 | 1.3.1 | 1.2.1 | 1.1.4 | 1.1.1 |
---|---|---|---|---|---|
IOB1:SLEW | 1.15.0 | 1.14.2 | 1.14.0 | 1.13.4 | 1.12.0 |
IOB2:SLEW | 1.17.4 | 1.17.3 | 1.16.3 | 1.16.1 | 1.15.2 |
IOB3:SLEW | 0.11.3 | 0.10.2 | 0.10.0 | 0.9.3 | 0.9.1 |
IOB4:SLEW | 0.14.4 | 0.14.0 | 0.13.4 | 0.12.0 | 0.10.3 |
non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB1:IBUF_MODE | 1.12.2 | 1.13.2 | 1.13.1 |
---|---|---|---|
IOB2:IBUF_MODE | 1.17.1 | 1.18.0 | 1.18.1 |
IOB3:IBUF_MODE | 0.9.2 | 0.8.4 | 0.8.3 |
IOB4:IBUF_MODE | 0.12.3 | 0.14.2 | 0.14.3 |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB2:OUTPUT_DIFF | 1.10.3 | 0.1.2 | 0.1.0 |
---|---|---|---|
IOB4:OUTPUT_DIFF | 0.7.4 | 0.15.4 | 0.15.2 |
non-inverted | [2] | [1] | [0] |
IOBS.S3.L1
IOB0:DCIUPDATEMODE_ASREQUIRED | 0.0.13 |
---|---|
IOB1:DCIUPDATEMODE_ASREQUIRED | 0.0.51 |
inverted | ~[0] |
IOB0:DCI_MODE | 0.0.9 | 0.0.28 | 0.0.25 | 0.0.5 |
---|---|---|---|---|
IOB1:DCI_MODE | 0.0.54 | 0.0.35 | 0.1.39 | 0.0.62 |
NONE | 0 | 0 | 0 | 0 |
OUTPUT | 0 | 0 | 0 | 1 |
OUTPUT_HALF | 0 | 0 | 1 | 0 |
TERM_SPLIT | 0 | 1 | 0 | 0 |
TERM_VCC | 1 | 0 | 1 | 1 |
IOB0:DISABLE_GTS | 0.0.11 |
---|---|
IOB0:VR | 0.0.17 |
IOB0:VREF | 0.0.8 |
IOB1:DISABLE_GTS | 0.1.52 |
IOB1:VR | 0.1.46 |
IOB1:VREF | 0.0.55 |
non-inverted | [0] |
IOB0:IBUF_MODE | 0.0.23 | 0.0.19 | 0.0.18 |
---|---|---|---|
IOB1:IBUF_MODE | 0.0.40 | 0.0.45 | 0.0.46 |
NONE | 0 | 0 | 0 |
VREF | 0 | 1 | 1 |
DIFF | 1 | 0 | 1 |
CMOS | 1 | 1 | 1 |
IOB0:NDRIVE | 0.0.7 | 0.0.20 | 0.0.2 | 0.0.10 |
---|---|---|---|---|
IOB1:NDRIVE | 0.0.56 | 0.0.41 | 0.1.58 | 0.0.53 |
mixed inversion | [3] | ~[2] | [1] | [0] |
IOB0:OUTPUT_ENABLE | 0.0.31 | 0.0.29 |
---|---|---|
IOB0:OUTPUT_MISC | 0.0.16 | 0.0.12 |
IOB1:OUTPUT_ENABLE | 0.0.34 | 0.0.32 |
IOB1:OUTPUT_MISC | 0.0.47 | 0.0.52 |
non-inverted | [1] | [0] |
IOB0:PDRIVE | 0.1.7 | 0.1.26 | 0.0.4 | 0.0.24 |
---|---|---|---|---|
IOB1:PDRIVE | 0.0.57 | 0.0.37 | 0.0.61 | 0.0.39 |
mixed inversion | [3] | ~[2] | [1] | ~[0] |
IOB0:PULL | 0.0.6 | 0.0.1 | 0.0.3 |
---|---|---|---|
IOB1:PULL | 0.0.58 | 0.0.59 | 0.0.63 |
PULLDOWN | 0 | 0 | 0 |
NONE | 0 | 0 | 1 |
PULLUP | 0 | 1 | 1 |
KEEPER | 1 | 0 | 1 |
IOB0:SLEW | 0.1.20 | 0.0.30 | 0.0.27 | 0.0.26 | 0.0.21 |
---|---|---|---|---|---|
IOB1:SLEW | 0.0.43 | 0.0.42 | 0.0.38 | 0.0.36 | 0.0.33 |
non-inverted | [4] | [3] | [2] | [1] | [0] |
IOB1:OUTPUT_DIFF | 0.0.15 | 0.0.50 | 0.0.48 |
---|---|---|---|
non-inverted | [2] | [1] | [0] |