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I/O Buffers (Spartan 3)

TODO: document

Name IOSTD:S3:PDRIVE IOSTD:S3:NDRIVE
[3] [2] [1] [0] [3] [2] [1] [0]
BLVDS_25 1 1 1 1 1 1 1 1
GTL 0 0 0 0 1 1 1 1
GTLP 0 0 0 0 1 1 1 0
GTLP_DCI 0 0 0 0 1 1 1 0
GTL_DCI 0 0 0 0 1 1 1 1
HSTL_I 1 0 0 1 0 1 0 0
HSTL_III 1 0 0 1 1 0 0 1
HSTL_III_18 0 1 1 1 1 0 0 1
HSTL_III_DCI 1 0 0 1 1 0 0 1
HSTL_III_DCI_18 0 1 1 1 1 0 0 1
HSTL_II_18 1 1 0 1 0 1 1 0
HSTL_II_DCI_18 1 1 0 1 0 1 1 0
HSTL_I_18 0 1 1 1 0 0 1 1
HSTL_I_DCI 1 0 0 1 0 0 1 1
HSTL_I_DCI_18 0 1 1 1 0 0 1 1
LVCMOS12.2 0 1 0 1 0 0 0 1
LVCMOS12.4 1 0 0 1 0 0 1 0
LVCMOS12.6 1 1 0 1 0 0 1 1
LVCMOS15.12 1 1 0 1 0 1 0 1
LVCMOS15.2 0 0 1 1 0 0 0 1
LVCMOS15.4 0 1 0 1 0 0 1 0
LVCMOS15.6 0 1 1 1 0 0 1 1
LVCMOS15.8 1 0 0 1 0 1 0 0
LVCMOS18.12 1 0 1 0 0 1 0 1
LVCMOS18.16 1 1 0 1 0 1 1 0
LVCMOS18.2 0 0 1 0 0 0 0 1
LVCMOS18.4 0 1 0 0 0 0 1 0
LVCMOS18.6 0 1 0 1 0 0 1 1
LVCMOS18.8 0 1 1 1 0 1 0 0
LVCMOS25.12 0 1 1 1 0 1 0 1
LVCMOS25.16 1 0 0 1 0 1 1 0
LVCMOS25.2 0 0 1 0 0 0 0 1
LVCMOS25.24 1 1 0 1 1 0 0 1
LVCMOS25.4 0 0 1 1 0 0 1 0
LVCMOS25.6 0 1 0 0 0 0 1 1
LVCMOS25.8 0 1 0 1 0 1 0 0
LVCMOS33.12 0 1 0 1 0 1 0 1
LVCMOS33.16 0 1 1 1 0 1 1 0
LVCMOS33.2 0 0 0 1 0 0 0 1
LVCMOS33.24 1 0 1 0 1 0 1 0
LVCMOS33.4 0 0 1 0 0 0 1 0
LVCMOS33.6 0 0 1 1 0 0 1 1
LVCMOS33.8 0 1 0 0 0 0 1 1
LVPECL_25 0 1 1 0 1 1 1 1
LVTTL.12 0 1 0 0 0 1 0 1
LVTTL.16 0 1 0 1 0 1 1 0
LVTTL.2 0 0 0 1 0 0 0 1
LVTTL.24 0 1 1 1 1 0 0 1
LVTTL.4 0 0 1 0 0 0 1 0
LVTTL.6 0 0 1 0 0 0 1 1
LVTTL.8 0 0 1 1 0 0 1 1
OFF 0 0 0 0 0 0 0 0
PCI33_3 0 1 1 1 1 1 0 0
PCI66_3 0 1 1 1 1 1 0 0
SSTL18_I 0 1 1 1 0 0 1 1
SSTL18_II 1 1 1 1 1 0 0 0
SSTL18_I_DCI 0 1 0 1 0 0 1 1
SSTL2_I 0 1 0 0 0 0 1 1
SSTL2_II 1 0 0 1 0 1 0 1
SSTL2_II_DCI 0 1 0 1 0 1 0 1
SSTL2_I_DCI 0 0 1 1 0 0 1 0
Name IOSTD:S3:SLEW
[4] [3] [2] [1] [0]
BLVDS_25 0 0 0 0 0
GTL 1 1 1 1 1
GTLP 1 1 1 1 1
GTLP_DCI 1 1 1 1 1
GTL_DCI 1 1 1 1 1
HSLVDCI_15 1 1 1 1 1
HSLVDCI_18 1 1 1 1 1
HSLVDCI_25 1 1 1 1 1
HSLVDCI_33 1 1 1 1 1
HSTL_I 1 1 1 1 1
HSTL_III 1 1 1 1 1
HSTL_III_18 1 1 1 1 1
HSTL_III_DCI 1 1 1 1 1
HSTL_III_DCI_18 1 1 1 1 1
HSTL_II_18 1 1 1 1 1
HSTL_II_DCI_18 1 1 1 1 1
HSTL_I_18 1 1 1 1 1
HSTL_I_DCI 1 1 1 1 1
HSTL_I_DCI_18 1 1 1 1 1
LVCMOS12.FAST 1 1 1 1 1
LVCMOS12.SLOW 0 0 0 0 0
LVCMOS15.FAST 1 1 1 1 1
LVCMOS15.SLOW 0 0 0 0 0
LVCMOS18.FAST 1 1 1 1 1
LVCMOS18.SLOW 0 0 0 0 0
LVCMOS25.FAST 1 1 1 1 1
LVCMOS25.SLOW 0 0 0 0 0
LVCMOS33.FAST 1 1 1 1 1
LVCMOS33.SLOW 0 0 0 0 0
LVDCI_15 1 1 1 1 1
LVDCI_18 1 1 1 1 1
LVDCI_25 1 1 1 1 1
LVDCI_33 1 1 1 1 1
LVDCI_DV2_15 1 1 1 1 1
LVDCI_DV2_18 1 1 1 1 1
LVDCI_DV2_25 1 1 1 1 1
LVDCI_DV2_33 1 1 1 1 1
LVPECL_25 1 1 1 1 1
LVTTL.FAST 1 1 1 1 1
LVTTL.SLOW 0 0 0 0 0
PCI33_3 0 0 0 0 0
PCI66_3 0 0 0 0 0
SSTL18_I 1 1 1 1 1
SSTL18_II 1 1 1 1 1
SSTL18_I_DCI 1 1 1 1 1
SSTL2_I 1 1 1 1 1
SSTL2_II 1 1 1 1 1
SSTL2_II_DCI 1 1 1 1 1
SSTL2_I_DCI 1 1 1 1 1
VR 0 0 0 0 0
Name IOSTD:S3:OUTPUT_MISC
[1] [0]
BLVDS_25 0 1
GTL 0 0
GTLP 0 0
GTLP_DCI 0 0
GTL_DCI 0 0
HSLVDCI_15 0 0
HSLVDCI_18 0 0
HSLVDCI_25 0 0
HSLVDCI_33 0 0
HSTL_I 1 1
HSTL_III 1 1
HSTL_III_18 1 1
HSTL_III_DCI 1 1
HSTL_III_DCI_18 1 1
HSTL_II_18 1 1
HSTL_II_DCI_18 1 1
HSTL_I_18 1 1
HSTL_I_DCI 1 1
HSTL_I_DCI_18 1 1
LVCMOS12 0 1
LVCMOS15 0 1
LVCMOS18 0 1
LVCMOS25 0 1
LVCMOS33 0 1
LVDCI_15 0 0
LVDCI_18 0 0
LVDCI_25 0 0
LVDCI_33 0 0
LVDCI_DV2_15 0 0
LVDCI_DV2_18 0 0
LVDCI_DV2_25 0 0
LVDCI_DV2_33 0 0
LVPECL_25 0 1
LVTTL 0 1
PCI33_3 0 0
PCI66_3 0 0
SSTL18_I 0 0
SSTL18_II 0 0
SSTL18_I_DCI 0 0
SSTL2_I 0 0
SSTL2_II 0 0
SSTL2_II_DCI 0 0
SSTL2_I_DCI 0 0
Name IOSTD:S3:OUTPUT_DIFF
[2] [1] [0]
LDT_25 1 0 1
LVDSEXT_25 0 1 1
LVDSEXT_25_DCI 0 1 1
LVDS_25 0 0 1
LVDS_25_DCI 0 0 1
OFF 0 0 0
RSDS_25 0 0 1
ULVDS_25 1 0 1
Name IOSTD:S3:LVDSBIAS
[12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
LDT_25 0 0 0 0 0 0 0 0 0 0 1 0 0
LVDSEXT_25 1 1 0 0 0 0 0 0 1 0 1 0 1
LVDSEXT_25_DCI 1 1 0 0 0 0 0 0 1 0 0 0 1
LVDS_25 1 1 0 0 0 0 0 0 1 0 1 0 1
LVDS_25_DCI 1 1 0 0 0 0 0 0 1 0 0 0 1
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0
RSDS_25 1 1 0 0 0 0 0 0 1 0 1 0 1
ULVDS_25 0 0 0 0 0 0 0 0 0 0 1 0 0
Name IOSTD:S3:PMASK_TERM_SPLIT IOSTD:S3:NMASK_TERM_SPLIT
[3] [2] [1] [0] [3] [2] [1] [0]
HSTL_II_DCI_18 1 0 0 1 0 1 0 0
HSTL_I_DCI 0 0 0 0 0 0 0 0
HSTL_I_DCI_18 0 0 0 0 0 0 0 0
LVDSEXT_25_DCI 0 0 0 0 0 0 0 0
LVDS_25_DCI 0 0 0 0 0 0 0 0
OFF 0 0 0 0 0 0 0 0
SSTL18_I_DCI 0 0 0 0 0 0 0 0
SSTL2_II_DCI 0 0 0 1 0 1 0 1
SSTL2_I_DCI 0 0 0 0 0 0 0 0
Name IOSTD:S3:PMASK_TERM_VCC
[3] [2] [1] [0]
GTLP_DCI 0 0 0 0
GTL_DCI 0 0 0 0
HSTL_III_DCI 0 0 0 0
HSTL_III_DCI_18 0 0 0 0
OFF 0 0 0 0

Tile IOB_S3_N2

Cells: 2

Bitstream

spartan3 IOB_S3_N2 rect TERM[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
spartan3 IOB_S3_N2 rect TERM[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOB_S3_N2 rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - IOB[2]:OUTPUT_MISC[1] IOB[2]:SLEW[1] IOB[2]:OUTPUT_DIFF[2] IOB[2]:DCI_MODE[1] IOB[1]:SLEW[1] IOB[1]:NDRIVE[3] - IOB[1]:SLEW[4] IOB[1]:DISABLE_GTS - IOB[1]:DCI_MODE[3] IOB[0]:DCI_MODE[3] IOB[0]:DCI_MODE[0] - IOB[0]:IBUF_MODE[0] ~IOB[0]:NDRIVE[2] ~IOB[0]:PDRIVE[2] IOB[0]:OUTPUT_ENABLE[1]
B3 - IOB[2]:VR IOB[2]:SLEW[0] IOB[1]:OUTPUT_MISC[1] IOB[2]:SLEW[3] IOB[1]:NDRIVE[0] IOB[2]:OUTPUT_ENABLE[1] IOB[1]:SLEW[3] ~IOB[1]:PDRIVE[2] IOB[1]:OUTPUT_MISC[0] - IOB[1]:PULL[1] IOB[0]:VREF IOB[0]:PDRIVE[1] ~IOB[0]:DCIUPDATEMODE_ASREQUIRED - IOB[0]:SLEW[1] IOB[0]:SLEW[2] IOB[0]:SLEW[4]
B2 - IOB[2]:IBUF_MODE[0] ~IOB[2]:NDRIVE[2] IOB[1]:IBUF_MODE[0] IOB[2]:SLEW[2] IOB[2]:OUTPUT_ENABLE[0] IOB[2]:SLEW[4] IOB[1]:PULL[2] IOB[1]:IBUF_MODE[2] ~IOB[1]:DCIUPDATEMODE_ASREQUIRED IOB[1]:NDRIVE[1] IOB[1]:VREF IOB[0]:NDRIVE[3] IOB[0]:PULL[0] IOB[0]:OUTPUT_MISC[0] IOB[0]:OUTPUT_MISC[1] IOB[0]:SLEW[0] IOB[0]:DCI_MODE[1] IOB[0]:OUTPUT_ENABLE[0]
B1 - IOB[2]:IBUF_MODE[1] IOB[2]:IBUF_MODE[2] IOB[1]:VR ~IOB[2]:PDRIVE[2] IOB[1]:SLEW[0] IOB[1]:OUTPUT_ENABLE[1] IOB[1]:SLEW[2] ~IOB[1]:PDRIVE[0] - IOB[1]:PULL[0] IOB[1]:PDRIVE[3] IOB[0]:PDRIVE[3] IOB[0]:NDRIVE[1] IOB[0]:DISABLE_GTS - - ~IOB[0]:PDRIVE[0] IOB[0]:DCI_MODE[2]
B0 - - ~IOB[2]:PDRIVE[0] IOB[1]:IBUF_MODE[1] IOB[2]:DCI_MODE[2] IOB[1]:OUTPUT_ENABLE[0] IOB[1]:DCI_MODE[2] ~IOB[1]:NDRIVE[2] IOB[1]:DCI_MODE[1] - IOB[1]:PDRIVE[1] IOB[1]:DCI_MODE[0] IOB[0]:PULL[2] IOB[0]:PULL[1] IOB[0]:NDRIVE[0] - IOB[0]:IBUF_MODE[1] IOB[0]:IBUF_MODE[2] IOB[0]:SLEW[3]
spartan3 IOB_S3_N2 rect R1
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - - IOB[4]:DCI_MODE[0] IOB[4]:DCI_MODE[3] IOB[4]:VR IOB[4]:OUTPUT_DIFF[1] ~IOB[4]:NDRIVE[2] ~IOB[4]:PDRIVE[2] IOB[4]:OUTPUT_ENABLE[1] IOB[3]:SLEW[2] IOB[3]:IBUF_MODE[1] IOB[3]:IBUF_MODE[2] IOB[3]:NDRIVE[0] - IOB[3]:PULL[2] IOB[3]:PULL[1] IOB[2]:PULL[0] IOB[2]:VREF IOB[2]:OUTPUT_MISC[0]
B3 - IOB[4]:PULL[1] IOB[4]:PULL[2] IOB[4]:NDRIVE[0] IOB[4]:IBUF_MODE[0] - IOB[4]:IBUF_MODE[2] IOB[4]:SLEW[4] IOB[3]:OUTPUT_ENABLE[1] ~IOB[3]:PDRIVE[2] IOB[3]:IBUF_MODE[0] IOB[3]:SLEW[4] IOB[3]:DCI_MODE[3] - IOB[3]:DCI_MODE[0] - IOB[2]:PDRIVE[1] IOB[2]:NDRIVE[3] ~IOB[2]:DCIUPDATEMODE_ASREQUIRED
B2 - IOB[4]:NDRIVE[1] IOB[4]:PDRIVE[3] IOB[4]:DISABLE_GTS IOB[4]:IBUF_MODE[1] IOB[4]:OUTPUT_DIFF[0] ~IOB[4]:PDRIVE[0] IOB[4]:DCI_MODE[2] IOB[3]:SLEW[0] IOB[3]:SLEW[1] IOB[3]:VR - IOB[3]:VREF ~IOB[3]:DCIUPDATEMODE_ASREQUIRED IOB[3]:NDRIVE[1] IOB[2]:PULL[1] IOB[2]:DCI_MODE[0] IOB[2]:DCI_MODE[3] IOB[2]:OUTPUT_DIFF[1]
B1 - IOB[4]:PULL[0] IOB[4]:NDRIVE[3] IOB[4]:OUTPUT_MISC[0] - IOB[4]:OUTPUT_MISC[1] IOB[4]:DCI_MODE[1] IOB[4]:OUTPUT_ENABLE[0] IOB[3]:OUTPUT_ENABLE[0] IOB[3]:DCI_MODE[1] IOB[3]:OUTPUT_MISC[1] IOB[3]:SLEW[3] IOB[3]:NDRIVE[3] IOB[3]:OUTPUT_MISC[0] IOB[3]:PDRIVE[1] - IOB[2]:PULL[2] IOB[2]:NDRIVE[0] -
B0 - IOB[4]:PDRIVE[1] IOB[4]:VREF ~IOB[4]:DCIUPDATEMODE_ASREQUIRED IOB[4]:SLEW[0] IOB[4]:SLEW[1] IOB[4]:SLEW[2] IOB[4]:SLEW[3] IOB[3]:DCI_MODE[2] ~IOB[3]:PDRIVE[0] IOB[4]:OUTPUT_DIFF[2] ~IOB[3]:NDRIVE[2] IOB[3]:PDRIVE[3] IOB[3]:DISABLE_GTS IOB[3]:PULL[0] IOB[2]:NDRIVE[1] IOB[2]:PDRIVE[3] IOB[2]:DISABLE_GTS IOB[2]:OUTPUT_DIFF[0]
IOB[0]:DCIUPDATEMODE_ASREQUIRED 0.F14.B3
IOB[1]:DCIUPDATEMODE_ASREQUIRED 0.F9.B2
IOB[2]:DCIUPDATEMODE_ASREQUIRED 1.F18.B3
IOB[3]:DCIUPDATEMODE_ASREQUIRED 1.F13.B2
IOB[4]:DCIUPDATEMODE_ASREQUIRED 1.F3.B0
inverted ~[0]
IOB[0]:DCI_MODE 0.F12.B4 0.F18.B1 0.F17.B2 0.F13.B4
IOB[1]:DCI_MODE 0.F11.B4 0.F6.B0 0.F8.B0 0.F11.B0
IOB[2]:DCI_MODE 1.F17.B2 0.F4.B0 0.F4.B4 1.F16.B2
IOB[3]:DCI_MODE 1.F12.B3 1.F8.B0 1.F9.B1 1.F14.B3
IOB[4]:DCI_MODE 1.F3.B4 1.F7.B2 1.F6.B1 1.F2.B4
NONE 0 0 0 0
OUTPUT 0 0 0 1
OUTPUT_HALF 0 0 1 0
TERM_SPLIT 0 1 0 0
TERM_VCC 1 0 1 1
IOB[0]:DISABLE_GTS 0.F14.B1
IOB[0]:VREF 0.F12.B3
IOB[1]:DISABLE_GTS 0.F9.B4
IOB[1]:VR 0.F3.B1
IOB[1]:VREF 0.F11.B2
IOB[2]:DISABLE_GTS 1.F17.B0
IOB[2]:VR 0.F1.B3
IOB[2]:VREF 1.F17.B4
IOB[3]:DISABLE_GTS 1.F13.B0
IOB[3]:VR 1.F10.B2
IOB[3]:VREF 1.F12.B2
IOB[4]:DISABLE_GTS 1.F3.B2
IOB[4]:VR 1.F4.B4
IOB[4]:VREF 1.F2.B0
non-inverted [0]
IOB[0]:IBUF_MODE 0.F17.B0 0.F16.B0 0.F15.B4
NONE 0 0 0
VREF 0 1 1
CMOS 1 1 1
IOB[0]:NDRIVE 0.F12.B2 0.F16.B4 0.F13.B1 0.F14.B0
IOB[1]:NDRIVE 0.F6.B4 0.F7.B0 0.F10.B2 0.F5.B3
IOB[2]:NDRIVE 1.F17.B3 0.F2.B2 1.F15.B0 1.F17.B1
IOB[3]:NDRIVE 1.F12.B1 1.F11.B0 1.F14.B2 1.F12.B4
IOB[4]:NDRIVE 1.F2.B1 1.F6.B4 1.F1.B2 1.F3.B3
mixed inversion [3] ~[2] [1] [0]
IOB[0]:OUTPUT_ENABLE 0.F18.B4 0.F18.B2
IOB[0]:OUTPUT_MISC 0.F15.B2 0.F14.B2
IOB[1]:OUTPUT_ENABLE 0.F6.B1 0.F5.B0
IOB[1]:OUTPUT_MISC 0.F3.B3 0.F9.B3
IOB[2]:OUTPUT_ENABLE 0.F6.B3 0.F5.B2
IOB[2]:OUTPUT_MISC 0.F1.B4 1.F18.B4
IOB[3]:OUTPUT_ENABLE 1.F8.B3 1.F8.B1
IOB[3]:OUTPUT_MISC 1.F10.B1 1.F13.B1
IOB[4]:OUTPUT_ENABLE 1.F8.B4 1.F7.B1
IOB[4]:OUTPUT_MISC 1.F5.B1 1.F3.B1
non-inverted [1] [0]
IOB[0]:PDRIVE 0.F12.B1 0.F17.B4 0.F13.B3 0.F17.B1
IOB[1]:PDRIVE 0.F11.B1 0.F8.B3 0.F10.B0 0.F8.B1
IOB[2]:PDRIVE 1.F16.B0 0.F4.B1 1.F16.B3 0.F2.B0
IOB[3]:PDRIVE 1.F12.B0 1.F9.B3 1.F14.B1 1.F9.B0
IOB[4]:PDRIVE 1.F2.B2 1.F7.B4 1.F1.B0 1.F6.B2
mixed inversion [3] ~[2] [1] ~[0]
IOB[0]:PULL 0.F12.B0 0.F13.B0 0.F13.B2
IOB[1]:PULL 0.F7.B2 0.F11.B3 0.F10.B1
IOB[2]:PULL 1.F16.B1 1.F15.B2 1.F16.B4
IOB[3]:PULL 1.F14.B4 1.F15.B4 1.F14.B0
IOB[4]:PULL 1.F2.B3 1.F1.B3 1.F1.B1
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB[0]:SLEW 0.F18.B3 0.F18.B0 0.F17.B3 0.F16.B3 0.F16.B2
IOB[1]:SLEW 0.F8.B4 0.F7.B3 0.F7.B1 0.F5.B4 0.F5.B1
IOB[2]:SLEW 0.F6.B2 0.F4.B3 0.F4.B2 0.F2.B4 0.F2.B3
IOB[3]:SLEW 1.F11.B3 1.F11.B1 1.F9.B4 1.F9.B2 1.F8.B2
IOB[4]:SLEW 1.F7.B3 1.F7.B0 1.F6.B0 1.F5.B0 1.F4.B0
non-inverted [4] [3] [2] [1] [0]
IOB[1]:IBUF_MODE 0.F8.B2 0.F3.B0 0.F3.B2
IOB[2]:IBUF_MODE 0.F2.B1 0.F1.B1 0.F1.B2
IOB[3]:IBUF_MODE 1.F11.B4 1.F10.B4 1.F10.B3
IOB[4]:IBUF_MODE 1.F6.B3 1.F4.B2 1.F4.B3
NONE 0 0 0
VREF 0 1 1
DIFF 1 0 1
CMOS 1 1 1
IOB[2]:OUTPUT_DIFF 0.F3.B4 1.F18.B2 1.F18.B0
IOB[4]:OUTPUT_DIFF 1.F10.B0 1.F5.B4 1.F5.B2
non-inverted [2] [1] [0]

Tile IOB_S3_E1

Cells: 1

Bitstream

spartan3 IOB_S3_E1 rect TERM
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 IOB_S3_E1 rect R0
BitFrame
F0 F1
B63 - IOB[0]:PULL[0]
B62 - IOB[0]:DCI_MODE[0]
B61 - IOB[0]:PDRIVE[1]
B60 - -
B59 - IOB[0]:PULL[1]
B58 IOB[0]:NDRIVE[1] IOB[0]:PULL[2]
B57 - IOB[0]:PDRIVE[3]
B56 - IOB[0]:NDRIVE[3]
B55 - IOB[0]:VREF
B54 - IOB[0]:DCI_MODE[3]
B53 - IOB[0]:NDRIVE[0]
B52 IOB[0]:DISABLE_GTS IOB[0]:OUTPUT_MISC[0]
B51 - ~IOB[0]:DCIUPDATEMODE_ASREQUIRED
B50 - -
B49 - -
B48 - IOB[1]:OUTPUT_DIFF[2]
B47 - IOB[0]:OUTPUT_MISC[1]
B46 IOB[0]:VR IOB[0]:IBUF_MODE[0]
B45 - IOB[0]:IBUF_MODE[1]
B44 - -
B43 - IOB[0]:SLEW[4]
B42 - IOB[0]:SLEW[3]
B41 - ~IOB[0]:NDRIVE[2]
B40 - IOB[0]:IBUF_MODE[2]
B39 IOB[0]:DCI_MODE[1] ~IOB[0]:PDRIVE[0]
B38 - IOB[0]:SLEW[2]
B37 - ~IOB[0]:PDRIVE[2]
B36 - IOB[0]:SLEW[1]
B35 - IOB[0]:DCI_MODE[2]
B34 - IOB[0]:OUTPUT_ENABLE[1]
B33 - IOB[0]:SLEW[0]
B32 - IOB[0]:OUTPUT_ENABLE[0]
B31 - IOB[1]:OUTPUT_ENABLE[1]
B30 - IOB[1]:SLEW[4]
B29 - IOB[1]:OUTPUT_ENABLE[0]
B28 - IOB[1]:DCI_MODE[2]
B27 - IOB[1]:SLEW[3]
B26 ~IOB[1]:PDRIVE[2] IOB[1]:SLEW[2]
B25 - IOB[1]:DCI_MODE[1]
B24 - ~IOB[1]:PDRIVE[0]
B23 - IOB[1]:IBUF_MODE[2]
B22 - -
B21 - IOB[1]:SLEW[1]
B20 IOB[1]:SLEW[0] ~IOB[1]:NDRIVE[2]
B19 - IOB[1]:IBUF_MODE[1]
B18 - IOB[1]:IBUF_MODE[0]
B17 - IOB[1]:VR
B16 - IOB[1]:OUTPUT_MISC[1]
B15 - IOB[1]:OUTPUT_DIFF[0]
B14 - IOB[1]:OUTPUT_DIFF[1]
B13 - ~IOB[1]:DCIUPDATEMODE_ASREQUIRED
B12 - IOB[1]:OUTPUT_MISC[0]
B11 - IOB[1]:DISABLE_GTS
B10 - IOB[1]:NDRIVE[0]
B9 - IOB[1]:DCI_MODE[3]
B8 - IOB[1]:VREF
B7 IOB[1]:PDRIVE[3] IOB[1]:NDRIVE[3]
B6 - IOB[1]:PULL[2]
B5 - IOB[1]:DCI_MODE[0]
B4 - IOB[1]:PDRIVE[1]
B3 - IOB[1]:PULL[0]
B2 - IOB[1]:NDRIVE[1]
B1 - IOB[1]:PULL[1]
B0 - -
IOB[0]:DCIUPDATEMODE_ASREQUIRED 0.F1.B51
IOB[1]:DCIUPDATEMODE_ASREQUIRED 0.F1.B13
inverted ~[0]
IOB[0]:DCI_MODE 0.F1.B54 0.F1.B35 0.F0.B39 0.F1.B62
IOB[1]:DCI_MODE 0.F1.B9 0.F1.B28 0.F1.B25 0.F1.B5
NONE 0 0 0 0
OUTPUT 0 0 0 1
OUTPUT_HALF 0 0 1 0
TERM_SPLIT 0 1 0 0
TERM_VCC 1 0 1 1
IOB[0]:DISABLE_GTS 0.F0.B52
IOB[0]:VR 0.F0.B46
IOB[0]:VREF 0.F1.B55
IOB[1]:DISABLE_GTS 0.F1.B11
IOB[1]:VR 0.F1.B17
IOB[1]:VREF 0.F1.B8
non-inverted [0]
IOB[0]:IBUF_MODE 0.F1.B40 0.F1.B45 0.F1.B46
IOB[1]:IBUF_MODE 0.F1.B23 0.F1.B19 0.F1.B18
NONE 0 0 0
VREF 0 1 1
DIFF 1 0 1
CMOS 1 1 1
IOB[0]:NDRIVE 0.F1.B56 0.F1.B41 0.F0.B58 0.F1.B53
IOB[1]:NDRIVE 0.F1.B7 0.F1.B20 0.F1.B2 0.F1.B10
mixed inversion [3] ~[2] [1] [0]
IOB[0]:OUTPUT_ENABLE 0.F1.B34 0.F1.B32
IOB[0]:OUTPUT_MISC 0.F1.B47 0.F1.B52
IOB[1]:OUTPUT_ENABLE 0.F1.B31 0.F1.B29
IOB[1]:OUTPUT_MISC 0.F1.B16 0.F1.B12
non-inverted [1] [0]
IOB[0]:PDRIVE 0.F1.B57 0.F1.B37 0.F1.B61 0.F1.B39
IOB[1]:PDRIVE 0.F0.B7 0.F0.B26 0.F1.B4 0.F1.B24
mixed inversion [3] ~[2] [1] ~[0]
IOB[0]:PULL 0.F1.B58 0.F1.B59 0.F1.B63
IOB[1]:PULL 0.F1.B6 0.F1.B1 0.F1.B3
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB[0]:SLEW 0.F1.B43 0.F1.B42 0.F1.B38 0.F1.B36 0.F1.B33
IOB[1]:SLEW 0.F1.B30 0.F1.B27 0.F1.B26 0.F1.B21 0.F0.B20
non-inverted [4] [3] [2] [1] [0]
IOB[1]:OUTPUT_DIFF 0.F1.B48 0.F1.B14 0.F1.B15
non-inverted [2] [1] [0]

Tile IOB_S3_S2

Cells: 2

Bitstream

spartan3 IOB_S3_S2 rect TERM[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
spartan3 IOB_S3_S2 rect TERM[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
### Bitstream
spartan3 IOB_S3_S2 rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - IOB[2]:OUTPUT_MISC[0] IOB[2]:NDRIVE[3] IOB[2]:PULL[0] IOB[3]:PULL[1] IOB[3]:DCI_MODE[0] IOB[3]:NDRIVE[0] IOB[4]:OUTPUT_DIFF[2] IOB[3]:IBUF_MODE[1] ~IOB[3]:NDRIVE[2] IOB[4]:OUTPUT_ENABLE[0] IOB[3]:OUTPUT_ENABLE[0] ~IOB[4]:NDRIVE[2] IOB[4]:SLEW[2] IOB[4]:SLEW[4] IOB[4]:OUTPUT_DIFF[1] ~IOB[4]:DCIUPDATEMODE_ASREQUIRED IOB[4]:DCI_MODE[0] -
B3 - ~IOB[2]:DCIUPDATEMODE_ASREQUIRED - IOB[2]:PDRIVE[1] - IOB[3]:PULL[2] IOB[3]:DCI_MODE[3] - IOB[3]:IBUF_MODE[0] IOB[3]:SLEW[1] IOB[4]:SLEW[0] IOB[3]:SLEW[4] IOB[4]:IBUF_MODE[2] ~IOB[4]:PDRIVE[2] IOB[4]:IBUF_MODE[0] - IOB[4]:DCI_MODE[3] IOB[4]:PULL[2] IOB[4]:PULL[1]
B2 - IOB[2]:OUTPUT_DIFF[1] IOB[2]:DCI_MODE[3] IOB[2]:DCI_MODE[0] - IOB[3]:PDRIVE[1] IOB[3]:VREF ~IOB[3]:DCIUPDATEMODE_ASREQUIRED - IOB[3]:IBUF_MODE[2] IOB[3]:SLEW[3] ~IOB[3]:PDRIVE[2] ~IOB[4]:PDRIVE[0] IOB[4]:OUTPUT_ENABLE[1] IOB[4]:IBUF_MODE[1] IOB[4]:OUTPUT_DIFF[0] IOB[4]:NDRIVE[0] IOB[4]:PDRIVE[3] IOB[4]:NDRIVE[1]
B1 - - IOB[2]:NDRIVE[0] IOB[2]:PULL[2] IOB[2]:PULL[1] IOB[3]:PULL[0] IOB[3]:NDRIVE[3] IOB[3]:OUTPUT_MISC[0] IOB[3]:OUTPUT_MISC[1] IOB[3]:SLEW[0] IOB[3]:DCI_MODE[2] IOB[3]:DCI_MODE[1] IOB[4]:DCI_MODE[1] IOB[4]:DCI_MODE[2] - IOB[4]:OUTPUT_MISC[1] IOB[4]:DISABLE_GTS IOB[4]:NDRIVE[3] IOB[4]:PULL[0]
B0 - IOB[2]:OUTPUT_DIFF[0] IOB[2]:DISABLE_GTS IOB[2]:PDRIVE[3] IOB[2]:NDRIVE[1] IOB[3]:NDRIVE[1] IOB[3]:PDRIVE[3] IOB[3]:DISABLE_GTS - - IOB[3]:SLEW[2] ~IOB[3]:PDRIVE[0] IOB[4]:SLEW[1] IOB[3]:OUTPUT_ENABLE[1] IOB[4]:SLEW[3] - IOB[4]:OUTPUT_MISC[0] IOB[4]:VREF IOB[4]:PDRIVE[1]
spartan3 IOB_S3_S2 rect R1
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B4 - IOB[0]:SLEW[1] IOB[0]:IBUF_MODE[2] IOB[0]:IBUF_MODE[0] - IOB[0]:NDRIVE[0] IOB[0]:PULL[2] IOB[0]:NDRIVE[1] IOB[1]:NDRIVE[1] IOB[1]:NDRIVE[3] IOB[1]:OUTPUT_MISC[1] IOB[1]:OUTPUT_MISC[0] IOB[1]:DCI_MODE[1] IOB[1]:SLEW[1] IOB[1]:OUTPUT_ENABLE[0] IOB[1]:OUTPUT_ENABLE[1] IOB[2]:DCI_MODE[1] IOB[2]:SLEW[4] IOB[2]:OUTPUT_MISC[1]
B3 - IOB[0]:DCI_MODE[2] ~IOB[0]:PDRIVE[0] - - IOB[0]:DISABLE_GTS IOB[0]:PDRIVE[3] IOB[1]:PULL[0] IOB[1]:PULL[1] IOB[1]:PDRIVE[3] IOB[2]:OUTPUT_DIFF[2] IOB[1]:DISABLE_GTS ~IOB[1]:PDRIVE[0] - IOB[1]:DCI_MODE[2] IOB[2]:OUTPUT_ENABLE[1] IOB[2]:SLEW[2] IOB[2]:SLEW[3] IOB[2]:VR
B2 - IOB[0]:OUTPUT_ENABLE[1] IOB[0]:DCI_MODE[1] IOB[0]:SLEW[4] IOB[0]:OUTPUT_MISC[1] IOB[0]:OUTPUT_MISC[0] IOB[0]:NDRIVE[3] IOB[0]:PULL[0] - IOB[1]:DCI_MODE[0] - IOB[1]:NDRIVE[0] IOB[1]:IBUF_MODE[2] IOB[1]:IBUF_MODE[1] IOB[1]:SLEW[3] IOB[2]:SLEW[0] ~IOB[2]:PDRIVE[2] ~IOB[2]:NDRIVE[2] -
B1 - IOB[0]:SLEW[0] IOB[0]:SLEW[2] IOB[0]:SLEW[3] - ~IOB[0]:DCIUPDATEMODE_ASREQUIRED IOB[0]:VREF IOB[0]:PDRIVE[1] - IOB[1]:PDRIVE[1] - IOB[1]:DCI_MODE[3] ~IOB[1]:NDRIVE[2] IOB[1]:IBUF_MODE[0] ~IOB[1]:PDRIVE[2] IOB[2]:OUTPUT_ENABLE[0] IOB[2]:SLEW[1] IOB[2]:IBUF_MODE[2] IOB[2]:IBUF_MODE[0]
B0 - IOB[0]:OUTPUT_ENABLE[0] ~IOB[0]:PDRIVE[2] ~IOB[0]:NDRIVE[2] IOB[0]:IBUF_MODE[1] - IOB[0]:DCI_MODE[3] IOB[0]:DCI_MODE[0] IOB[0]:PULL[1] IOB[1]:PULL[2] ~IOB[1]:DCIUPDATEMODE_ASREQUIRED - IOB[1]:SLEW[0] IOB[1]:VR IOB[1]:SLEW[2] IOB[1]:SLEW[4] IOB[2]:DCI_MODE[2] ~IOB[2]:PDRIVE[0] IOB[2]:IBUF_MODE[1]
IOB[0]:DCIUPDATEMODE_ASREQUIRED 1.F5.B1
IOB[1]:DCIUPDATEMODE_ASREQUIRED 1.F10.B0
IOB[2]:DCIUPDATEMODE_ASREQUIRED 0.F1.B3
IOB[3]:DCIUPDATEMODE_ASREQUIRED 0.F7.B2
IOB[4]:DCIUPDATEMODE_ASREQUIRED 0.F16.B4
inverted ~[0]
IOB[0]:DCI_MODE 1.F6.B0 1.F1.B3 1.F2.B2 1.F7.B0
IOB[1]:DCI_MODE 1.F11.B1 1.F14.B3 1.F12.B4 1.F9.B2
IOB[2]:DCI_MODE 0.F2.B2 1.F16.B0 1.F16.B4 0.F3.B2
IOB[3]:DCI_MODE 0.F6.B3 0.F10.B1 0.F11.B1 0.F5.B4
IOB[4]:DCI_MODE 0.F16.B3 0.F13.B1 0.F12.B1 0.F17.B4
NONE 0 0 0 0
OUTPUT 0 0 0 1
OUTPUT_HALF 0 0 1 0
TERM_SPLIT 0 1 0 0
TERM_VCC 1 0 1 1
IOB[0]:DISABLE_GTS 1.F5.B3
IOB[0]:VREF 1.F6.B1
IOB[1]:DISABLE_GTS 1.F11.B3
IOB[1]:VR 1.F13.B0
IOB[2]:DISABLE_GTS 0.F2.B0
IOB[2]:VR 1.F18.B3
IOB[3]:DISABLE_GTS 0.F7.B0
IOB[3]:VREF 0.F6.B2
IOB[4]:DISABLE_GTS 0.F16.B1
IOB[4]:VREF 0.F17.B0
non-inverted [0]
IOB[0]:IBUF_MODE 1.F2.B4 1.F4.B0 1.F3.B4
NONE 0 0 0
VREF 0 1 1
CMOS 1 1 1
IOB[0]:NDRIVE 1.F6.B2 1.F3.B0 1.F7.B4 1.F5.B4
IOB[1]:NDRIVE 1.F9.B4 1.F12.B1 1.F8.B4 1.F11.B2
IOB[2]:NDRIVE 0.F2.B4 1.F17.B2 0.F4.B0 0.F2.B1
IOB[3]:NDRIVE 0.F6.B1 0.F9.B4 0.F5.B0 0.F6.B4
IOB[4]:NDRIVE 0.F17.B1 0.F12.B4 0.F18.B2 0.F16.B2
mixed inversion [3] ~[2] [1] [0]
IOB[0]:OUTPUT_ENABLE 1.F1.B2 1.F1.B0
IOB[0]:OUTPUT_MISC 1.F4.B2 1.F5.B2
IOB[1]:OUTPUT_ENABLE 1.F15.B4 1.F14.B4
IOB[1]:OUTPUT_MISC 1.F10.B4 1.F11.B4
IOB[2]:OUTPUT_ENABLE 1.F15.B3 1.F15.B1
IOB[2]:OUTPUT_MISC 1.F18.B4 0.F1.B4
IOB[3]:OUTPUT_ENABLE 0.F13.B0 0.F11.B4
IOB[3]:OUTPUT_MISC 0.F8.B1 0.F7.B1
IOB[4]:OUTPUT_ENABLE 0.F13.B2 0.F10.B4
IOB[4]:OUTPUT_MISC 0.F15.B1 0.F16.B0
non-inverted [1] [0]
IOB[0]:PDRIVE 1.F6.B3 1.F2.B0 1.F7.B1 1.F2.B3
IOB[1]:PDRIVE 1.F9.B3 1.F14.B1 1.F9.B1 1.F12.B3
IOB[2]:PDRIVE 0.F3.B0 1.F16.B2 0.F3.B3 1.F17.B0
IOB[3]:PDRIVE 0.F6.B0 0.F11.B2 0.F5.B2 0.F11.B0
IOB[4]:PDRIVE 0.F17.B2 0.F13.B3 0.F18.B0 0.F12.B2
mixed inversion [3] ~[2] [1] ~[0]
IOB[0]:PULL 1.F6.B4 1.F8.B0 1.F7.B2
IOB[1]:PULL 1.F9.B0 1.F8.B3 1.F7.B3
IOB[2]:PULL 0.F3.B1 0.F4.B1 0.F3.B4
IOB[3]:PULL 0.F5.B3 0.F4.B4 0.F5.B1
IOB[4]:PULL 0.F17.B3 0.F18.B3 0.F18.B1
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB[0]:SLEW 1.F3.B2 1.F3.B1 1.F2.B1 1.F1.B4 1.F1.B1
IOB[1]:SLEW 1.F15.B0 1.F14.B2 1.F14.B0 1.F13.B4 1.F12.B0
IOB[2]:SLEW 1.F17.B4 1.F17.B3 1.F16.B3 1.F16.B1 1.F15.B2
IOB[3]:SLEW 0.F11.B3 0.F10.B2 0.F10.B0 0.F9.B3 0.F9.B1
IOB[4]:SLEW 0.F14.B4 0.F14.B0 0.F13.B4 0.F12.B0 0.F10.B3
non-inverted [4] [3] [2] [1] [0]
IOB[1]:IBUF_MODE 1.F12.B2 1.F13.B2 1.F13.B1
IOB[2]:IBUF_MODE 1.F17.B1 1.F18.B0 1.F18.B1
IOB[3]:IBUF_MODE 0.F9.B2 0.F8.B4 0.F8.B3
IOB[4]:IBUF_MODE 0.F12.B3 0.F14.B2 0.F14.B3
NONE 0 0 0
VREF 0 1 1
DIFF 1 0 1
CMOS 1 1 1
IOB[2]:OUTPUT_DIFF 1.F10.B3 0.F1.B2 0.F1.B0
IOB[4]:OUTPUT_DIFF 0.F7.B4 0.F15.B4 0.F15.B2
non-inverted [2] [1] [0]

Tile IOB_S3_W1

Cells: 1

Bitstream

spartan3 IOB_S3_W1 rect TERM
BitFrame
F0 F1
B63 - -
B62 - -
B61 - -
B60 - -
B59 - -
B58 - -
B57 - -
B56 - -
B55 - -
B54 - -
B53 - -
B52 - -
B51 - -
B50 - -
B49 - -
B48 - -
B47 - -
B46 - -
B45 - -
B44 - -
B43 - -
B42 - -
B41 - -
B40 - -
B39 - -
B38 - -
B37 - -
B36 - -
B35 - -
B34 - -
B33 - -
B32 - -
B31 - -
B30 - -
B29 - -
B28 - -
B27 - -
B26 - -
B25 - -
B24 - -
B23 - -
B22 - -
B21 - -
B20 - -
B19 - -
B18 - -
B17 - -
B16 - -
B15 - -
B14 - -
B13 - -
B12 - -
B11 - -
B10 - -
B9 - -
B8 - -
B7 - -
B6 - -
B5 - -
B4 - -
B3 - -
B2 - -
B1 - -
B0 - -
### Bitstream
spartan3 IOB_S3_W1 rect R0
BitFrame
F0 F1
B63 IOB[1]:PULL[0] -
B62 IOB[1]:DCI_MODE[0] -
B61 IOB[1]:PDRIVE[1] -
B60 - -
B59 IOB[1]:PULL[1] -
B58 IOB[1]:PULL[2] IOB[1]:NDRIVE[1]
B57 IOB[1]:PDRIVE[3] -
B56 IOB[1]:NDRIVE[3] -
B55 IOB[1]:VREF -
B54 IOB[1]:DCI_MODE[3] -
B53 IOB[1]:NDRIVE[0] -
B52 IOB[1]:OUTPUT_MISC[0] IOB[1]:DISABLE_GTS
B51 ~IOB[1]:DCIUPDATEMODE_ASREQUIRED -
B50 IOB[1]:OUTPUT_DIFF[1] -
B49 - -
B48 IOB[1]:OUTPUT_DIFF[0] -
B47 IOB[1]:OUTPUT_MISC[1] -
B46 IOB[1]:IBUF_MODE[0] IOB[1]:VR
B45 IOB[1]:IBUF_MODE[1] -
B44 - -
B43 IOB[1]:SLEW[4] -
B42 IOB[1]:SLEW[3] -
B41 ~IOB[1]:NDRIVE[2] -
B40 IOB[1]:IBUF_MODE[2] -
B39 ~IOB[1]:PDRIVE[0] IOB[1]:DCI_MODE[1]
B38 IOB[1]:SLEW[2] -
B37 ~IOB[1]:PDRIVE[2] -
B36 IOB[1]:SLEW[1] -
B35 IOB[1]:DCI_MODE[2] -
B34 IOB[1]:OUTPUT_ENABLE[1] -
B33 IOB[1]:SLEW[0] -
B32 IOB[1]:OUTPUT_ENABLE[0] -
B31 IOB[0]:OUTPUT_ENABLE[1] -
B30 IOB[0]:SLEW[3] -
B29 IOB[0]:OUTPUT_ENABLE[0] -
B28 IOB[0]:DCI_MODE[2] -
B27 IOB[0]:SLEW[2] -
B26 IOB[0]:SLEW[1] ~IOB[0]:PDRIVE[2]
B25 IOB[0]:DCI_MODE[1] -
B24 ~IOB[0]:PDRIVE[0] -
B23 IOB[0]:IBUF_MODE[2] -
B22 - -
B21 IOB[0]:SLEW[0] -
B20 ~IOB[0]:NDRIVE[2] IOB[0]:SLEW[4]
B19 IOB[0]:IBUF_MODE[1] -
B18 IOB[0]:IBUF_MODE[0] -
B17 IOB[0]:VR -
B16 IOB[0]:OUTPUT_MISC[1] -
B15 IOB[1]:OUTPUT_DIFF[2] -
B14 - -
B13 ~IOB[0]:DCIUPDATEMODE_ASREQUIRED -
B12 IOB[0]:OUTPUT_MISC[0] -
B11 IOB[0]:DISABLE_GTS -
B10 IOB[0]:NDRIVE[0] -
B9 IOB[0]:DCI_MODE[3] -
B8 IOB[0]:VREF -
B7 IOB[0]:NDRIVE[3] IOB[0]:PDRIVE[3]
B6 IOB[0]:PULL[2] -
B5 IOB[0]:DCI_MODE[0] -
B4 IOB[0]:PDRIVE[1] -
B3 IOB[0]:PULL[0] -
B2 IOB[0]:NDRIVE[1] -
B1 IOB[0]:PULL[1] -
B0 - -
IOB[0]:DCIUPDATEMODE_ASREQUIRED 0.F0.B13
IOB[1]:DCIUPDATEMODE_ASREQUIRED 0.F0.B51
inverted ~[0]
IOB[0]:DCI_MODE 0.F0.B9 0.F0.B28 0.F0.B25 0.F0.B5
IOB[1]:DCI_MODE 0.F0.B54 0.F0.B35 0.F1.B39 0.F0.B62
NONE 0 0 0 0
OUTPUT 0 0 0 1
OUTPUT_HALF 0 0 1 0
TERM_SPLIT 0 1 0 0
TERM_VCC 1 0 1 1
IOB[0]:DISABLE_GTS 0.F0.B11
IOB[0]:VR 0.F0.B17
IOB[0]:VREF 0.F0.B8
IOB[1]:DISABLE_GTS 0.F1.B52
IOB[1]:VR 0.F1.B46
IOB[1]:VREF 0.F0.B55
non-inverted [0]
IOB[0]:IBUF_MODE 0.F0.B23 0.F0.B19 0.F0.B18
IOB[1]:IBUF_MODE 0.F0.B40 0.F0.B45 0.F0.B46
NONE 0 0 0
VREF 0 1 1
DIFF 1 0 1
CMOS 1 1 1
IOB[0]:NDRIVE 0.F0.B7 0.F0.B20 0.F0.B2 0.F0.B10
IOB[1]:NDRIVE 0.F0.B56 0.F0.B41 0.F1.B58 0.F0.B53
mixed inversion [3] ~[2] [1] [0]
IOB[0]:OUTPUT_ENABLE 0.F0.B31 0.F0.B29
IOB[0]:OUTPUT_MISC 0.F0.B16 0.F0.B12
IOB[1]:OUTPUT_ENABLE 0.F0.B34 0.F0.B32
IOB[1]:OUTPUT_MISC 0.F0.B47 0.F0.B52
non-inverted [1] [0]
IOB[0]:PDRIVE 0.F1.B7 0.F1.B26 0.F0.B4 0.F0.B24
IOB[1]:PDRIVE 0.F0.B57 0.F0.B37 0.F0.B61 0.F0.B39
mixed inversion [3] ~[2] [1] ~[0]
IOB[0]:PULL 0.F0.B6 0.F0.B1 0.F0.B3
IOB[1]:PULL 0.F0.B58 0.F0.B59 0.F0.B63
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IOB[0]:SLEW 0.F1.B20 0.F0.B30 0.F0.B27 0.F0.B26 0.F0.B21
IOB[1]:SLEW 0.F0.B43 0.F0.B42 0.F0.B38 0.F0.B36 0.F0.B33
non-inverted [4] [3] [2] [1] [0]
IOB[1]:OUTPUT_DIFF 0.F0.B15 0.F0.B50 0.F0.B48
non-inverted [2] [1] [0]