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I/O clock buffers

Tile REG_B

Cells: 1 IRIs: 0

Muxes

spartan6 REG_B muxes
DestinationSources
IMUX.REGB.GCLK0GCLK0, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7, GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15
IMUX.REGB.GCLK1GCLK0, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7, GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15

Bel BUFIO2_0

spartan6 REG_B bel BUFIO2_0
PinDirectionWires

Bel BUFIO2_1

spartan6 REG_B bel BUFIO2_1
PinDirectionWires

Bel BUFIO2_2

spartan6 REG_B bel BUFIO2_2
PinDirectionWires

Bel BUFIO2_3

spartan6 REG_B bel BUFIO2_3
PinDirectionWires

Bel BUFIO2_4

spartan6 REG_B bel BUFIO2_4
PinDirectionWires

Bel BUFIO2_5

spartan6 REG_B bel BUFIO2_5
PinDirectionWires

Bel BUFIO2_6

spartan6 REG_B bel BUFIO2_6
PinDirectionWires

Bel BUFIO2_7

spartan6 REG_B bel BUFIO2_7
PinDirectionWires

Bel BUFIO2FB_0

spartan6 REG_B bel BUFIO2FB_0
PinDirectionWires

Bel BUFIO2FB_1

spartan6 REG_B bel BUFIO2FB_1
PinDirectionWires

Bel BUFIO2FB_2

spartan6 REG_B bel BUFIO2FB_2
PinDirectionWires

Bel BUFIO2FB_3

spartan6 REG_B bel BUFIO2FB_3
PinDirectionWires

Bel BUFIO2FB_4

spartan6 REG_B bel BUFIO2FB_4
PinDirectionWires

Bel BUFIO2FB_5

spartan6 REG_B bel BUFIO2FB_5
PinDirectionWires

Bel BUFIO2FB_6

spartan6 REG_B bel BUFIO2FB_6
PinDirectionWires

Bel BUFIO2FB_7

spartan6 REG_B bel BUFIO2FB_7
PinDirectionWires

Bel BUFPLL0

spartan6 REG_B bel BUFPLL0
PinDirectionWires

Bel BUFPLL1

spartan6 REG_B bel BUFPLL1
PinDirectionWires

Bel BUFPLL_MCB

spartan6 REG_B bel BUFPLL_MCB
PinDirectionWires

Bel BUFPLL_OUT

spartan6 REG_B bel BUFPLL_OUT
PinDirectionWires
LOCK0outputOUT18
LOCK1outputOUT19

Bel BUFPLL_INS_BT

spartan6 REG_B bel BUFPLL_INS_BT
PinDirectionWires
GCLK0inputIMUX.REGB.GCLK0
GCLK1inputIMUX.REGB.GCLK1

Bel BUFIO2_INS

spartan6 REG_B bel BUFIO2_INS
PinDirectionWires

Bel BUFIO2_CKPIN

spartan6 REG_B bel BUFIO2_CKPIN
PinDirectionWires

Bel BUFPLL_BUF

spartan6 REG_B bel BUFPLL_BUF
PinDirectionWires

Bel GTP_H_BUF

spartan6 REG_B bel GTP_H_BUF
PinDirectionWires

Bel TIEOFF_REG

spartan6 REG_B bel TIEOFF_REG
PinDirectionWires

Bel wires

spartan6 REG_B bel wires
WirePins
OUT18BUFPLL_OUT.LOCK0
OUT19BUFPLL_OUT.LOCK1
IMUX.REGB.GCLK0BUFPLL_INS_BT.GCLK0
IMUX.REGB.GCLK1BUFPLL_INS_BT.GCLK1

Bitstream

spartan6 REG_B bittile 0
BitFrame
0
380 MISC:MISR_RESET
379 MISC:MISR_ENABLE
378 BUFPLL1:LOCKED[1]
377 BUFPLL1:LOCKED[0]
376 BUFPLL0:LOCKED[1]
375 BUFPLL0:LOCKED[0]
374 BUFIO2_1:CMT_ENABLE
373 BUFIO2_1:CKPIN[0]
372 BUFIO2_1:IOCLK_ENABLE
371 BUFIO2_1:CKPIN[1]
370 ~BUFIO2_1:FB_DIVIDE_BYPASS[3]
369 ~BUFIO2_1:DIVIDE_BYPASS
368 -
367 BUFIO2_1:FB_ENABLE
366 -
365 ~BUFIO2_1:FB_DIVIDE_BYPASS[2]
364 ~BUFIO2_1:FB_DIVIDE_BYPASS[1]
363 ~BUFIO2_1:FB_DIVIDE_BYPASS[0]
362 -
361 -
360 -
359 -
358 -
357 -
356 BUFIO2_1:ENABLE_2CLK
355 BUFIO2_1:ENABLE
354 BUFIO2_1:R_EDGE
353 BUFIO2_1:DIVIDE[2]
352 BUFIO2_1:DIVIDE[1]
351 BUFIO2_1:DIVIDE[0]
350 -
349 BUFIO2_1:NEG_EDGE[1]
348 BUFIO2_1:NEG_EDGE[0]
347 BUFIO2_1:POS_EDGE[2]
346 BUFIO2_1:POS_EDGE[1]
345 BUFIO2_1:POS_EDGE[0]
344 BUFIO2_1:FB_I[2]
343 BUFIO2_1:FB_I[1]
342 BUFIO2_1:FB_I[0]
341 BUFIO2_1:IB[2]
340 BUFIO2_1:IB[1]
339 BUFIO2_1:IB[0]
338 BUFIO2_1:I[2]
337 BUFIO2_1:I[1]
336 BUFIO2_1:I[0]
335 BUFPLL1:PLLIN[2]
334 BUFPLL1:PLLIN[1]
333 BUFPLL1:PLLIN[0]
332 BUFPLL0:PLLIN[2]
331 BUFPLL0:PLLIN[1]
330 BUFPLL0:PLLIN[0]
329 BUFPLL1:ENABLE_BOTH_SYNC[2]
328 BUFPLL1:ENABLE_NONE_SYNC[1]
327 -
326 BUFIO2_0:CMT_ENABLE
325 BUFIO2_0:CKPIN[0]
324 BUFIO2_0:IOCLK_ENABLE
323 BUFIO2_0:CKPIN[1]
322 ~BUFIO2_0:FB_DIVIDE_BYPASS[3]
321 ~BUFIO2_0:DIVIDE_BYPASS
320 -
319 BUFIO2_0:FB_ENABLE
318 -
317 ~BUFIO2_0:FB_DIVIDE_BYPASS[2]
316 ~BUFIO2_0:FB_DIVIDE_BYPASS[1]
315 ~BUFIO2_0:FB_DIVIDE_BYPASS[0]
314 -
313 -
312 -
311 -
310 -
309 -
308 BUFIO2_0:ENABLE_2CLK
307 BUFIO2_0:ENABLE
306 BUFIO2_0:R_EDGE
305 BUFIO2_0:DIVIDE[2]
304 BUFIO2_0:DIVIDE[1]
303 BUFIO2_0:DIVIDE[0]
302 -
301 BUFIO2_0:NEG_EDGE[1]
300 BUFIO2_0:NEG_EDGE[0]
299 BUFIO2_0:POS_EDGE[2]
298 BUFIO2_0:POS_EDGE[1]
297 BUFIO2_0:POS_EDGE[0]
296 BUFIO2_0:FB_I[2]
295 BUFIO2_0:FB_I[1]
294 BUFIO2_0:FB_I[0]
293 BUFIO2_0:IB[2]
292 BUFIO2_0:IB[1]
291 BUFIO2_0:IB[0]
290 BUFIO2_0:I[2]
289 BUFIO2_0:I[1]
288 BUFIO2_0:I[0]
287 -
286 BUFPLL0:ENABLE_BOTH_SYNC[2]
285 BUFPLL0:ENABLE_NONE_SYNC[1]
284 -
283 -
282 BUFPLL1:ENABLE_BOTH_SYNC[1]
281 BUFPLL1:ENABLE_NONE_SYNC[0]
280 BUFPLL0:ENABLE_BOTH_SYNC[1]
279 BUFPLL0:ENABLE_NONE_SYNC[0]
278 BUFIO2_3:CMT_ENABLE
277 BUFIO2_3:CKPIN[0]
276 BUFIO2_3:IOCLK_ENABLE
275 BUFIO2_3:CKPIN[1]
274 ~BUFIO2_3:FB_DIVIDE_BYPASS[3]
273 ~BUFIO2_3:DIVIDE_BYPASS
272 -
271 BUFIO2_3:FB_ENABLE
270 -
269 ~BUFIO2_3:FB_DIVIDE_BYPASS[2]
268 ~BUFIO2_3:FB_DIVIDE_BYPASS[1]
267 ~BUFIO2_3:FB_DIVIDE_BYPASS[0]
266 -
265 -
264 -
263 -
262 -
261 -
260 BUFIO2_3:ENABLE_2CLK
259 BUFIO2_3:ENABLE
258 BUFIO2_3:R_EDGE
257 BUFIO2_3:DIVIDE[2]
256 BUFIO2_3:DIVIDE[1]
255 BUFIO2_3:DIVIDE[0]
254 -
253 BUFIO2_3:NEG_EDGE[1]
252 BUFIO2_3:NEG_EDGE[0]
251 BUFIO2_3:POS_EDGE[2]
250 BUFIO2_3:POS_EDGE[1]
249 BUFIO2_3:POS_EDGE[0]
248 BUFIO2_3:FB_I[2]
247 BUFIO2_3:FB_I[1]
246 BUFIO2_3:FB_I[0]
245 BUFIO2_3:IB[2]
244 BUFIO2_3:IB[1]
243 BUFIO2_3:IB[0]
242 BUFIO2_3:I[2]
241 BUFIO2_3:I[1]
240 BUFIO2_3:I[0]
239 -
238 -
237 BUFPLL1:ENABLE_BOTH_SYNC[0]
236 -
235 -
234 BUFPLL0:ENABLE_BOTH_SYNC[0]
233 BUFPLL1:DIVIDE[5]
232 BUFPLL1:DIVIDE[4]
231 -
230 BUFIO2_2:CMT_ENABLE
229 BUFIO2_2:CKPIN[0]
228 BUFIO2_2:IOCLK_ENABLE
227 BUFIO2_2:CKPIN[1]
226 ~BUFIO2_2:FB_DIVIDE_BYPASS[3]
225 ~BUFIO2_2:DIVIDE_BYPASS
224 -
223 BUFIO2_2:FB_ENABLE
222 -
221 ~BUFIO2_2:FB_DIVIDE_BYPASS[2]
220 ~BUFIO2_2:FB_DIVIDE_BYPASS[1]
219 ~BUFIO2_2:FB_DIVIDE_BYPASS[0]
218 -
217 -
216 -
215 -
214 -
213 -
212 BUFIO2_2:ENABLE_2CLK
211 BUFIO2_2:ENABLE
210 BUFIO2_2:R_EDGE
209 BUFIO2_2:DIVIDE[2]
208 BUFIO2_2:DIVIDE[1]
207 BUFIO2_2:DIVIDE[0]
206 -
205 BUFIO2_2:NEG_EDGE[1]
204 BUFIO2_2:NEG_EDGE[0]
203 BUFIO2_2:POS_EDGE[2]
202 BUFIO2_2:POS_EDGE[1]
201 BUFIO2_2:POS_EDGE[0]
200 BUFIO2_2:FB_I[2]
199 BUFIO2_2:FB_I[1]
198 BUFIO2_2:FB_I[0]
197 BUFIO2_2:IB[2]
196 BUFIO2_2:IB[1]
195 BUFIO2_2:IB[0]
194 BUFIO2_2:I[2]
193 BUFIO2_2:I[1]
192 BUFIO2_2:I[0]
191 BUFPLL1:DIVIDE[3]
190 BUFPLL0:DIVIDE[5]
189 BUFPLL0:DIVIDE[4]
188 -
187 BUFPLL0:DIVIDE[3]
186 BUFPLL1:DATA_RATE[0]
185 ~BUFPLL1:ENABLE_SYNC
184 BUFPLL_MCB:LOCK_SRC[0]
183 BUFPLL1:DIVIDE[2]
182 BUFIO2_5:CMT_ENABLE
181 BUFIO2_5:CKPIN[0]
180 BUFIO2_5:IOCLK_ENABLE
179 BUFIO2_5:CKPIN[1]
178 ~BUFIO2_5:FB_DIVIDE_BYPASS[3]
177 ~BUFIO2_5:DIVIDE_BYPASS
176 -
175 BUFIO2_5:FB_ENABLE
174 -
173 ~BUFIO2_5:FB_DIVIDE_BYPASS[2]
172 ~BUFIO2_5:FB_DIVIDE_BYPASS[1]
171 ~BUFIO2_5:FB_DIVIDE_BYPASS[0]
170 -
169 -
168 -
167 -
166 -
165 -
164 BUFIO2_5:ENABLE_2CLK
163 BUFIO2_5:ENABLE
162 BUFIO2_5:R_EDGE
161 BUFIO2_5:DIVIDE[2]
160 BUFIO2_5:DIVIDE[1]
159 BUFIO2_5:DIVIDE[0]
158 -
157 BUFIO2_5:NEG_EDGE[1]
156 BUFIO2_5:NEG_EDGE[0]
155 BUFIO2_5:POS_EDGE[2]
154 BUFIO2_5:POS_EDGE[1]
153 BUFIO2_5:POS_EDGE[0]
152 BUFIO2_5:FB_I[2]
151 BUFIO2_5:FB_I[1]
150 BUFIO2_5:FB_I[0]
149 BUFIO2_5:IB[2]
148 BUFIO2_5:IB[1]
147 BUFIO2_5:IB[0]
146 BUFIO2_5:I[2]
145 BUFIO2_5:I[1]
144 BUFIO2_5:I[0]
143 BUFPLL1:DIVIDE[1]
142 BUFPLL1:DIVIDE[0]
141 BUFPLL0:DATA_RATE[0]
140 ~BUFPLL0:ENABLE_SYNC
139 BUFPLL_MCB:LOCK_SRC[1]
138 BUFPLL0:DIVIDE[2]
137 BUFPLL0:DIVIDE[1]
136 BUFPLL0:DIVIDE[0]
135 BUFPLL_COMMON:ENABLE
134 BUFIO2_4:CMT_ENABLE
133 BUFIO2_4:CKPIN[0]
132 BUFIO2_4:IOCLK_ENABLE
131 BUFIO2_4:CKPIN[1]
130 ~BUFIO2_4:FB_DIVIDE_BYPASS[3]
129 ~BUFIO2_4:DIVIDE_BYPASS
128 -
127 BUFIO2_4:FB_ENABLE
126 -
125 ~BUFIO2_4:FB_DIVIDE_BYPASS[2]
124 ~BUFIO2_4:FB_DIVIDE_BYPASS[1]
123 ~BUFIO2_4:FB_DIVIDE_BYPASS[0]
122 -
121 -
120 -
119 -
118 -
117 -
116 BUFIO2_4:ENABLE_2CLK
115 BUFIO2_4:ENABLE
114 BUFIO2_4:R_EDGE
113 BUFIO2_4:DIVIDE[2]
112 BUFIO2_4:DIVIDE[1]
111 BUFIO2_4:DIVIDE[0]
110 -
109 BUFIO2_4:NEG_EDGE[1]
108 BUFIO2_4:NEG_EDGE[0]
107 BUFIO2_4:POS_EDGE[2]
106 BUFIO2_4:POS_EDGE[1]
105 BUFIO2_4:POS_EDGE[0]
104 BUFIO2_4:FB_I[2]
103 BUFIO2_4:FB_I[1]
102 BUFIO2_4:FB_I[0]
101 BUFIO2_4:IB[2]
100 BUFIO2_4:IB[1]
99 BUFIO2_4:IB[0]
98 BUFIO2_4:I[2]
97 BUFIO2_4:I[1]
96 BUFIO2_4:I[0]
95 -
94 -
93 INT:MUX.IMUX.REGB.GCLK0[4]
92 INT:MUX.IMUX.REGB.GCLK0[5]
91 INT:MUX.IMUX.REGB.GCLK0[6]
90 INT:MUX.IMUX.REGB.GCLK0[7]
89 INT:MUX.IMUX.REGB.GCLK0[0]
88 INT:MUX.IMUX.REGB.GCLK0[1]
87 INT:MUX.IMUX.REGB.GCLK0[2]
86 BUFIO2_7:CMT_ENABLE
85 BUFIO2_7:CKPIN[0]
84 BUFIO2_7:IOCLK_ENABLE
83 BUFIO2_7:CKPIN[1]
82 ~BUFIO2_7:FB_DIVIDE_BYPASS[3]
81 ~BUFIO2_7:DIVIDE_BYPASS
80 -
79 BUFIO2_7:FB_ENABLE
78 -
77 ~BUFIO2_7:FB_DIVIDE_BYPASS[2]
76 ~BUFIO2_7:FB_DIVIDE_BYPASS[1]
75 ~BUFIO2_7:FB_DIVIDE_BYPASS[0]
74 -
73 -
72 -
71 -
70 -
69 -
68 BUFIO2_7:ENABLE_2CLK
67 BUFIO2_7:ENABLE
66 BUFIO2_7:R_EDGE
65 BUFIO2_7:DIVIDE[2]
64 BUFIO2_7:DIVIDE[1]
63 BUFIO2_7:DIVIDE[0]
62 -
61 BUFIO2_7:NEG_EDGE[1]
60 BUFIO2_7:NEG_EDGE[0]
59 BUFIO2_7:POS_EDGE[2]
58 BUFIO2_7:POS_EDGE[1]
57 BUFIO2_7:POS_EDGE[0]
56 BUFIO2_7:FB_I[2]
55 BUFIO2_7:FB_I[1]
54 BUFIO2_7:FB_I[0]
53 BUFIO2_7:IB[2]
52 BUFIO2_7:IB[1]
51 BUFIO2_7:IB[0]
50 BUFIO2_7:I[2]
49 BUFIO2_7:I[1]
48 BUFIO2_7:I[0]
47 INT:MUX.IMUX.REGB.GCLK0[3]
46 INT:MUX.IMUX.REGB.GCLK1[3]
45 INT:MUX.IMUX.REGB.GCLK1[2]
44 INT:MUX.IMUX.REGB.GCLK1[1]
43 INT:MUX.IMUX.REGB.GCLK1[0]
42 INT:MUX.IMUX.REGB.GCLK1[7]
41 INT:MUX.IMUX.REGB.GCLK1[6]
40 INT:MUX.IMUX.REGB.GCLK1[5]
39 INT:MUX.IMUX.REGB.GCLK1[4]
38 BUFIO2_6:CMT_ENABLE
37 BUFIO2_6:CKPIN[0]
36 BUFIO2_6:IOCLK_ENABLE
35 BUFIO2_6:CKPIN[1]
34 ~BUFIO2_6:FB_DIVIDE_BYPASS[3]
33 ~BUFIO2_6:DIVIDE_BYPASS
32 -
31 BUFIO2_6:FB_ENABLE
30 -
29 ~BUFIO2_6:FB_DIVIDE_BYPASS[2]
28 ~BUFIO2_6:FB_DIVIDE_BYPASS[1]
27 ~BUFIO2_6:FB_DIVIDE_BYPASS[0]
26 -
25 -
24 -
23 -
22 -
21 -
20 BUFIO2_6:ENABLE_2CLK
19 BUFIO2_6:ENABLE
18 BUFIO2_6:R_EDGE
17 BUFIO2_6:DIVIDE[2]
16 BUFIO2_6:DIVIDE[1]
15 BUFIO2_6:DIVIDE[0]
14 -
13 BUFIO2_6:NEG_EDGE[1]
12 BUFIO2_6:NEG_EDGE[0]
11 BUFIO2_6:POS_EDGE[2]
10 BUFIO2_6:POS_EDGE[1]
9 BUFIO2_6:POS_EDGE[0]
8 BUFIO2_6:FB_I[2]
7 BUFIO2_6:FB_I[1]
6 BUFIO2_6:FB_I[0]
5 BUFIO2_6:IB[2]
4 BUFIO2_6:IB[1]
3 BUFIO2_6:IB[0]
2 BUFIO2_6:I[2]
1 BUFIO2_6:I[1]
0 BUFIO2_6:I[0]
BUFIO2_0:CKPIN 0.0.323 0.0.325
BUFIO2_1:CKPIN 0.0.371 0.0.373
BUFIO2_2:CKPIN 0.0.227 0.0.229
BUFIO2_3:CKPIN 0.0.275 0.0.277
BUFIO2_4:CKPIN 0.0.131 0.0.133
BUFIO2_5:CKPIN 0.0.179 0.0.181
BUFIO2_6:CKPIN 0.0.35 0.0.37
BUFIO2_7:CKPIN 0.0.83 0.0.85
VCC 0 0
CLKPIN 0 1
DIVCLK 1 1
BUFIO2_0:CMT_ENABLE 0.0.326
BUFIO2_0:ENABLE 0.0.307
BUFIO2_0:ENABLE_2CLK 0.0.308
BUFIO2_0:FB_ENABLE 0.0.319
BUFIO2_0:IOCLK_ENABLE 0.0.324
BUFIO2_0:R_EDGE 0.0.306
BUFIO2_1:CMT_ENABLE 0.0.374
BUFIO2_1:ENABLE 0.0.355
BUFIO2_1:ENABLE_2CLK 0.0.356
BUFIO2_1:FB_ENABLE 0.0.367
BUFIO2_1:IOCLK_ENABLE 0.0.372
BUFIO2_1:R_EDGE 0.0.354
BUFIO2_2:CMT_ENABLE 0.0.230
BUFIO2_2:ENABLE 0.0.211
BUFIO2_2:ENABLE_2CLK 0.0.212
BUFIO2_2:FB_ENABLE 0.0.223
BUFIO2_2:IOCLK_ENABLE 0.0.228
BUFIO2_2:R_EDGE 0.0.210
BUFIO2_3:CMT_ENABLE 0.0.278
BUFIO2_3:ENABLE 0.0.259
BUFIO2_3:ENABLE_2CLK 0.0.260
BUFIO2_3:FB_ENABLE 0.0.271
BUFIO2_3:IOCLK_ENABLE 0.0.276
BUFIO2_3:R_EDGE 0.0.258
BUFIO2_4:CMT_ENABLE 0.0.134
BUFIO2_4:ENABLE 0.0.115
BUFIO2_4:ENABLE_2CLK 0.0.116
BUFIO2_4:FB_ENABLE 0.0.127
BUFIO2_4:IOCLK_ENABLE 0.0.132
BUFIO2_4:R_EDGE 0.0.114
BUFIO2_5:CMT_ENABLE 0.0.182
BUFIO2_5:ENABLE 0.0.163
BUFIO2_5:ENABLE_2CLK 0.0.164
BUFIO2_5:FB_ENABLE 0.0.175
BUFIO2_5:IOCLK_ENABLE 0.0.180
BUFIO2_5:R_EDGE 0.0.162
BUFIO2_6:CMT_ENABLE 0.0.38
BUFIO2_6:ENABLE 0.0.19
BUFIO2_6:ENABLE_2CLK 0.0.20
BUFIO2_6:FB_ENABLE 0.0.31
BUFIO2_6:IOCLK_ENABLE 0.0.36
BUFIO2_6:R_EDGE 0.0.18
BUFIO2_7:CMT_ENABLE 0.0.86
BUFIO2_7:ENABLE 0.0.67
BUFIO2_7:ENABLE_2CLK 0.0.68
BUFIO2_7:FB_ENABLE 0.0.79
BUFIO2_7:IOCLK_ENABLE 0.0.84
BUFIO2_7:R_EDGE 0.0.66
BUFPLL_COMMON:ENABLE 0.0.135
MISC:MISR_ENABLE 0.0.379
MISC:MISR_RESET 0.0.380
non-inverted [0]
BUFIO2_0:DIVIDE 0.0.305 0.0.304 0.0.303
BUFIO2_1:DIVIDE 0.0.353 0.0.352 0.0.351
BUFIO2_2:DIVIDE 0.0.209 0.0.208 0.0.207
BUFIO2_3:DIVIDE 0.0.257 0.0.256 0.0.255
BUFIO2_4:DIVIDE 0.0.113 0.0.112 0.0.111
BUFIO2_5:DIVIDE 0.0.161 0.0.160 0.0.159
BUFIO2_6:DIVIDE 0.0.17 0.0.16 0.0.15
BUFIO2_7:DIVIDE 0.0.65 0.0.64 0.0.63
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
1 1 1 1
BUFIO2_0:DIVIDE_BYPASS 0.0.321
BUFIO2_1:DIVIDE_BYPASS 0.0.369
BUFIO2_2:DIVIDE_BYPASS 0.0.225
BUFIO2_3:DIVIDE_BYPASS 0.0.273
BUFIO2_4:DIVIDE_BYPASS 0.0.129
BUFIO2_5:DIVIDE_BYPASS 0.0.177
BUFIO2_6:DIVIDE_BYPASS 0.0.33
BUFIO2_7:DIVIDE_BYPASS 0.0.81
BUFPLL0:ENABLE_SYNC 0.0.140
BUFPLL1:ENABLE_SYNC 0.0.185
inverted ~[0]
BUFIO2_0:FB_DIVIDE_BYPASS 0.0.322 0.0.317 0.0.316 0.0.315
BUFIO2_1:FB_DIVIDE_BYPASS 0.0.370 0.0.365 0.0.364 0.0.363
BUFIO2_2:FB_DIVIDE_BYPASS 0.0.226 0.0.221 0.0.220 0.0.219
BUFIO2_3:FB_DIVIDE_BYPASS 0.0.274 0.0.269 0.0.268 0.0.267
BUFIO2_4:FB_DIVIDE_BYPASS 0.0.130 0.0.125 0.0.124 0.0.123
BUFIO2_5:FB_DIVIDE_BYPASS 0.0.178 0.0.173 0.0.172 0.0.171
BUFIO2_6:FB_DIVIDE_BYPASS 0.0.34 0.0.29 0.0.28 0.0.27
BUFIO2_7:FB_DIVIDE_BYPASS 0.0.82 0.0.77 0.0.76 0.0.75
inverted ~[3] ~[2] ~[1] ~[0]
BUFIO2_0:FB_I 0.0.296 0.0.295 0.0.294
BUFIO2_1:FB_I 0.0.344 0.0.343 0.0.342
BUFIO2_2:FB_I 0.0.200 0.0.199 0.0.198
BUFIO2_3:FB_I 0.0.248 0.0.247 0.0.246
BUFIO2_4:FB_I 0.0.104 0.0.103 0.0.102
BUFIO2_5:FB_I 0.0.152 0.0.151 0.0.150
BUFIO2_6:FB_I 0.0.8 0.0.7 0.0.6
BUFIO2_7:FB_I 0.0.56 0.0.55 0.0.54
CLKPIN 0 0 0
DFB 0 0 1
CFB 0 1 0
CFB_INVERT 0 1 1
GTPFB 1 1 1
BUFIO2_0:I 0.0.290 0.0.289 0.0.288
BUFIO2_1:I 0.0.338 0.0.337 0.0.336
BUFIO2_2:I 0.0.194 0.0.193 0.0.192
BUFIO2_3:I 0.0.242 0.0.241 0.0.240
BUFIO2_4:I 0.0.98 0.0.97 0.0.96
BUFIO2_5:I 0.0.146 0.0.145 0.0.144
BUFIO2_6:I 0.0.2 0.0.1 0.0.0
BUFIO2_7:I 0.0.50 0.0.49 0.0.48
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
GTPCLK 1 1 1
BUFIO2_0:IB 0.0.293 0.0.292 0.0.291
BUFIO2_1:IB 0.0.341 0.0.340 0.0.339
BUFIO2_2:IB 0.0.197 0.0.196 0.0.195
BUFIO2_3:IB 0.0.245 0.0.244 0.0.243
BUFIO2_4:IB 0.0.101 0.0.100 0.0.99
BUFIO2_5:IB 0.0.149 0.0.148 0.0.147
BUFIO2_6:IB 0.0.5 0.0.4 0.0.3
BUFIO2_7:IB 0.0.53 0.0.52 0.0.51
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFIO2_0:NEG_EDGE 0.0.301 0.0.300
BUFIO2_1:NEG_EDGE 0.0.349 0.0.348
BUFIO2_2:NEG_EDGE 0.0.205 0.0.204
BUFIO2_3:NEG_EDGE 0.0.253 0.0.252
BUFIO2_4:NEG_EDGE 0.0.109 0.0.108
BUFIO2_5:NEG_EDGE 0.0.157 0.0.156
BUFIO2_6:NEG_EDGE 0.0.13 0.0.12
BUFIO2_7:NEG_EDGE 0.0.61 0.0.60
DIVIDE_1 0 0
DIVIDE_3 0 0
DIVIDE_4 0 0
NEG_EDGE_1 0 0
NEG_EDGE_4 0 0
NEG_EDGE_5 0 0
NEG_EDGE_6 0 0
NEG_EDGE_7 0 0
NEG_EDGE_8 0 0
DIVIDE_2 0 1
DIVIDE_5 0 1
DIVIDE_6 0 1
NEG_EDGE_2 0 1
DIVIDE_7 1 0
DIVIDE_8 1 0
NEG_EDGE_3 1 0
BUFIO2_0:POS_EDGE 0.0.299 0.0.298 0.0.297
BUFIO2_1:POS_EDGE 0.0.347 0.0.346 0.0.345
BUFIO2_2:POS_EDGE 0.0.203 0.0.202 0.0.201
BUFIO2_3:POS_EDGE 0.0.251 0.0.250 0.0.249
BUFIO2_4:POS_EDGE 0.0.107 0.0.106 0.0.105
BUFIO2_5:POS_EDGE 0.0.155 0.0.154 0.0.153
BUFIO2_6:POS_EDGE 0.0.11 0.0.10 0.0.9
BUFIO2_7:POS_EDGE 0.0.59 0.0.58 0.0.57
DIVIDE_1 0 0 0
POS_EDGE_1 0 0 0
POS_EDGE_3 0 0 0
POS_EDGE_5 0 0 0
DIVIDE_2 0 0 1
POS_EDGE_2 0 0 1
DIVIDE_3 0 1 0
DIVIDE_4 0 1 1
POS_EDGE_4 0 1 1
DIVIDE_5 1 0 0
DIVIDE_6 1 0 1
POS_EDGE_6 1 0 1
DIVIDE_7 1 1 0
POS_EDGE_7 1 1 0
DIVIDE_8 1 1 1
POS_EDGE_8 1 1 1
BUFPLL0:DATA_RATE 0.0.141
BUFPLL1:DATA_RATE 0.0.186
SDR 0
DDR 1
BUFPLL0:DIVIDE 0.0.190 0.0.189 0.0.187 0.0.138 0.0.137 0.0.136
BUFPLL1:DIVIDE 0.0.233 0.0.232 0.0.191 0.0.183 0.0.143 0.0.142
3 0 0 0 0 0 1
2 0 0 1 0 0 0
5 0 1 0 0 1 1
4 0 1 1 0 1 0
7 1 0 0 1 0 1
6 1 0 1 1 0 0
1 1 1 0 1 1 1
8 1 1 1 1 1 0
BUFPLL0:ENABLE_BOTH_SYNC 0.0.286 0.0.280 0.0.234
BUFPLL1:ENABLE_BOTH_SYNC 0.0.329 0.0.282 0.0.237
non-inverted [2] [1] [0]
BUFPLL0:ENABLE_NONE_SYNC 0.0.285 0.0.279
BUFPLL1:ENABLE_NONE_SYNC 0.0.328 0.0.281
non-inverted [1] [0]
BUFPLL0:LOCKED 0.0.376 0.0.375
BUFPLL1:LOCKED 0.0.378 0.0.377
LOCKED0 0 0
LOCKED1 0 1
LOCKED2 1 0
BUFPLL0:PLLIN 0.0.332 0.0.331 0.0.330
BUFPLL1:PLLIN 0.0.335 0.0.334 0.0.333
PLLIN0 0 0 0
PLLIN1 0 0 1
PLLIN2 0 1 0
PLLIN3 0 1 1
PLLIN4 1 0 0
PLLIN5 1 0 1
BUFPLL_MCB:LOCK_SRC 0.0.139 0.0.184
LOCK_TO_0 0 1
LOCK_TO_1 1 0
INT:MUX.IMUX.REGB.GCLK0 0.0.90 0.0.91 0.0.92 0.0.93 0.0.47 0.0.87 0.0.88 0.0.89
INT:MUX.IMUX.REGB.GCLK1 0.0.42 0.0.41 0.0.40 0.0.39 0.0.46 0.0.45 0.0.44 0.0.43
NONE 0 0 0 0 0 0 0 0
GCLK0 0 1 0 1 0 0 0 1
GCLK1 0 1 0 1 0 0 1 0
GCLK2 0 1 0 1 0 1 0 0
GCLK3 0 1 0 1 1 0 0 0
GCLK8 0 1 1 0 0 0 0 1
GCLK9 0 1 1 0 0 0 1 0
GCLK10 0 1 1 0 0 1 0 0
GCLK11 0 1 1 0 1 0 0 0
GCLK4 1 0 0 1 0 0 0 1
GCLK5 1 0 0 1 0 0 1 0
GCLK6 1 0 0 1 0 1 0 0
GCLK7 1 0 0 1 1 0 0 0
GCLK12 1 0 1 0 0 0 0 1
GCLK13 1 0 1 0 0 0 1 0
GCLK14 1 0 1 0 0 1 0 0
GCLK15 1 0 1 0 1 0 0 0

Tile REG_T

Cells: 1 IRIs: 0

Muxes

spartan6 REG_T muxes
DestinationSources
IMUX.REGT.GCLK0GCLK0, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7, GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15
IMUX.REGT.GCLK1GCLK0, GCLK1, GCLK2, GCLK3, GCLK4, GCLK5, GCLK6, GCLK7, GCLK8, GCLK9, GCLK10, GCLK11, GCLK12, GCLK13, GCLK14, GCLK15

Bel BUFIO2_0

spartan6 REG_T bel BUFIO2_0
PinDirectionWires

Bel BUFIO2_1

spartan6 REG_T bel BUFIO2_1
PinDirectionWires

Bel BUFIO2_2

spartan6 REG_T bel BUFIO2_2
PinDirectionWires

Bel BUFIO2_3

spartan6 REG_T bel BUFIO2_3
PinDirectionWires

Bel BUFIO2_4

spartan6 REG_T bel BUFIO2_4
PinDirectionWires

Bel BUFIO2_5

spartan6 REG_T bel BUFIO2_5
PinDirectionWires

Bel BUFIO2_6

spartan6 REG_T bel BUFIO2_6
PinDirectionWires

Bel BUFIO2_7

spartan6 REG_T bel BUFIO2_7
PinDirectionWires

Bel BUFIO2FB_0

spartan6 REG_T bel BUFIO2FB_0
PinDirectionWires

Bel BUFIO2FB_1

spartan6 REG_T bel BUFIO2FB_1
PinDirectionWires

Bel BUFIO2FB_2

spartan6 REG_T bel BUFIO2FB_2
PinDirectionWires

Bel BUFIO2FB_3

spartan6 REG_T bel BUFIO2FB_3
PinDirectionWires

Bel BUFIO2FB_4

spartan6 REG_T bel BUFIO2FB_4
PinDirectionWires

Bel BUFIO2FB_5

spartan6 REG_T bel BUFIO2FB_5
PinDirectionWires

Bel BUFIO2FB_6

spartan6 REG_T bel BUFIO2FB_6
PinDirectionWires

Bel BUFIO2FB_7

spartan6 REG_T bel BUFIO2FB_7
PinDirectionWires

Bel BUFPLL0

spartan6 REG_T bel BUFPLL0
PinDirectionWires

Bel BUFPLL1

spartan6 REG_T bel BUFPLL1
PinDirectionWires

Bel BUFPLL_MCB

spartan6 REG_T bel BUFPLL_MCB
PinDirectionWires

Bel BUFPLL_OUT

spartan6 REG_T bel BUFPLL_OUT
PinDirectionWires
LOCK0outputOUT18
LOCK1outputOUT19

Bel BUFPLL_INS_BT

spartan6 REG_T bel BUFPLL_INS_BT
PinDirectionWires
GCLK0inputIMUX.REGT.GCLK0
GCLK1inputIMUX.REGT.GCLK1

Bel BUFIO2_INS

spartan6 REG_T bel BUFIO2_INS
PinDirectionWires

Bel BUFIO2_CKPIN

spartan6 REG_T bel BUFIO2_CKPIN
PinDirectionWires

Bel BUFPLL_BUF

spartan6 REG_T bel BUFPLL_BUF
PinDirectionWires

Bel GTP_H_BUF

spartan6 REG_T bel GTP_H_BUF
PinDirectionWires

Bel TIEOFF_REG

spartan6 REG_T bel TIEOFF_REG
PinDirectionWires

Bel wires

spartan6 REG_T bel wires
WirePins
OUT18BUFPLL_OUT.LOCK0
OUT19BUFPLL_OUT.LOCK1
IMUX.REGT.GCLK0BUFPLL_INS_BT.GCLK0
IMUX.REGT.GCLK1BUFPLL_INS_BT.GCLK1

Bitstream

spartan6 REG_T bittile 0
BitFrame
0
380 MISC:MISR_RESET
379 MISC:MISR_ENABLE
378 BUFPLL1:LOCKED[1]
377 BUFPLL1:LOCKED[0]
376 BUFPLL0:LOCKED[1]
375 BUFPLL0:LOCKED[0]
374 BUFIO2_1:CMT_ENABLE
373 BUFIO2_1:CKPIN[0]
372 BUFIO2_1:IOCLK_ENABLE
371 BUFIO2_1:CKPIN[1]
370 ~BUFIO2_1:FB_DIVIDE_BYPASS[3]
369 ~BUFIO2_1:DIVIDE_BYPASS
368 -
367 BUFIO2_1:FB_ENABLE
366 -
365 ~BUFIO2_1:FB_DIVIDE_BYPASS[2]
364 ~BUFIO2_1:FB_DIVIDE_BYPASS[1]
363 ~BUFIO2_1:FB_DIVIDE_BYPASS[0]
362 -
361 -
360 -
359 -
358 -
357 -
356 BUFIO2_1:ENABLE_2CLK
355 BUFIO2_1:ENABLE
354 BUFIO2_1:R_EDGE
353 BUFIO2_1:DIVIDE[2]
352 BUFIO2_1:DIVIDE[1]
351 BUFIO2_1:DIVIDE[0]
350 -
349 BUFIO2_1:NEG_EDGE[1]
348 BUFIO2_1:NEG_EDGE[0]
347 BUFIO2_1:POS_EDGE[2]
346 BUFIO2_1:POS_EDGE[1]
345 BUFIO2_1:POS_EDGE[0]
344 BUFIO2_1:FB_I[2]
343 BUFIO2_1:FB_I[1]
342 BUFIO2_1:FB_I[0]
341 BUFIO2_1:IB[2]
340 BUFIO2_1:IB[1]
339 BUFIO2_1:IB[0]
338 BUFIO2_1:I[2]
337 BUFIO2_1:I[1]
336 BUFIO2_1:I[0]
335 BUFPLL1:PLLIN[2]
334 BUFPLL1:PLLIN[1]
333 BUFPLL1:PLLIN[0]
332 BUFPLL0:PLLIN[2]
331 BUFPLL0:PLLIN[1]
330 BUFPLL0:PLLIN[0]
329 BUFPLL1:ENABLE_BOTH_SYNC[2]
328 BUFPLL1:ENABLE_NONE_SYNC[1]
327 -
326 BUFIO2_0:CMT_ENABLE
325 BUFIO2_0:CKPIN[0]
324 BUFIO2_0:IOCLK_ENABLE
323 BUFIO2_0:CKPIN[1]
322 ~BUFIO2_0:FB_DIVIDE_BYPASS[3]
321 ~BUFIO2_0:DIVIDE_BYPASS
320 -
319 BUFIO2_0:FB_ENABLE
318 -
317 ~BUFIO2_0:FB_DIVIDE_BYPASS[2]
316 ~BUFIO2_0:FB_DIVIDE_BYPASS[1]
315 ~BUFIO2_0:FB_DIVIDE_BYPASS[0]
314 -
313 -
312 -
311 -
310 -
309 -
308 BUFIO2_0:ENABLE_2CLK
307 BUFIO2_0:ENABLE
306 BUFIO2_0:R_EDGE
305 BUFIO2_0:DIVIDE[2]
304 BUFIO2_0:DIVIDE[1]
303 BUFIO2_0:DIVIDE[0]
302 -
301 BUFIO2_0:NEG_EDGE[1]
300 BUFIO2_0:NEG_EDGE[0]
299 BUFIO2_0:POS_EDGE[2]
298 BUFIO2_0:POS_EDGE[1]
297 BUFIO2_0:POS_EDGE[0]
296 BUFIO2_0:FB_I[2]
295 BUFIO2_0:FB_I[1]
294 BUFIO2_0:FB_I[0]
293 BUFIO2_0:IB[2]
292 BUFIO2_0:IB[1]
291 BUFIO2_0:IB[0]
290 BUFIO2_0:I[2]
289 BUFIO2_0:I[1]
288 BUFIO2_0:I[0]
287 -
286 BUFPLL0:ENABLE_BOTH_SYNC[2]
285 BUFPLL0:ENABLE_NONE_SYNC[1]
284 -
283 -
282 BUFPLL1:ENABLE_BOTH_SYNC[1]
281 BUFPLL1:ENABLE_NONE_SYNC[0]
280 BUFPLL0:ENABLE_BOTH_SYNC[1]
279 BUFPLL0:ENABLE_NONE_SYNC[0]
278 BUFIO2_3:CMT_ENABLE
277 BUFIO2_3:CKPIN[0]
276 BUFIO2_3:IOCLK_ENABLE
275 BUFIO2_3:CKPIN[1]
274 ~BUFIO2_3:FB_DIVIDE_BYPASS[3]
273 ~BUFIO2_3:DIVIDE_BYPASS
272 -
271 BUFIO2_3:FB_ENABLE
270 -
269 ~BUFIO2_3:FB_DIVIDE_BYPASS[2]
268 ~BUFIO2_3:FB_DIVIDE_BYPASS[1]
267 ~BUFIO2_3:FB_DIVIDE_BYPASS[0]
266 -
265 -
264 -
263 -
262 -
261 -
260 BUFIO2_3:ENABLE_2CLK
259 BUFIO2_3:ENABLE
258 BUFIO2_3:R_EDGE
257 BUFIO2_3:DIVIDE[2]
256 BUFIO2_3:DIVIDE[1]
255 BUFIO2_3:DIVIDE[0]
254 -
253 BUFIO2_3:NEG_EDGE[1]
252 BUFIO2_3:NEG_EDGE[0]
251 BUFIO2_3:POS_EDGE[2]
250 BUFIO2_3:POS_EDGE[1]
249 BUFIO2_3:POS_EDGE[0]
248 BUFIO2_3:FB_I[2]
247 BUFIO2_3:FB_I[1]
246 BUFIO2_3:FB_I[0]
245 BUFIO2_3:IB[2]
244 BUFIO2_3:IB[1]
243 BUFIO2_3:IB[0]
242 BUFIO2_3:I[2]
241 BUFIO2_3:I[1]
240 BUFIO2_3:I[0]
239 -
238 -
237 BUFPLL1:ENABLE_BOTH_SYNC[0]
236 -
235 -
234 BUFPLL0:ENABLE_BOTH_SYNC[0]
233 BUFPLL1:DIVIDE[5]
232 BUFPLL1:DIVIDE[4]
231 -
230 BUFIO2_2:CMT_ENABLE
229 BUFIO2_2:CKPIN[0]
228 BUFIO2_2:IOCLK_ENABLE
227 BUFIO2_2:CKPIN[1]
226 ~BUFIO2_2:FB_DIVIDE_BYPASS[3]
225 ~BUFIO2_2:DIVIDE_BYPASS
224 -
223 BUFIO2_2:FB_ENABLE
222 -
221 ~BUFIO2_2:FB_DIVIDE_BYPASS[2]
220 ~BUFIO2_2:FB_DIVIDE_BYPASS[1]
219 ~BUFIO2_2:FB_DIVIDE_BYPASS[0]
218 -
217 -
216 -
215 -
214 -
213 -
212 BUFIO2_2:ENABLE_2CLK
211 BUFIO2_2:ENABLE
210 BUFIO2_2:R_EDGE
209 BUFIO2_2:DIVIDE[2]
208 BUFIO2_2:DIVIDE[1]
207 BUFIO2_2:DIVIDE[0]
206 -
205 BUFIO2_2:NEG_EDGE[1]
204 BUFIO2_2:NEG_EDGE[0]
203 BUFIO2_2:POS_EDGE[2]
202 BUFIO2_2:POS_EDGE[1]
201 BUFIO2_2:POS_EDGE[0]
200 BUFIO2_2:FB_I[2]
199 BUFIO2_2:FB_I[1]
198 BUFIO2_2:FB_I[0]
197 BUFIO2_2:IB[2]
196 BUFIO2_2:IB[1]
195 BUFIO2_2:IB[0]
194 BUFIO2_2:I[2]
193 BUFIO2_2:I[1]
192 BUFIO2_2:I[0]
191 BUFPLL1:DIVIDE[3]
190 BUFPLL0:DIVIDE[5]
189 BUFPLL0:DIVIDE[4]
188 -
187 BUFPLL0:DIVIDE[3]
186 BUFPLL1:DATA_RATE[0]
185 ~BUFPLL1:ENABLE_SYNC
184 BUFPLL_MCB:LOCK_SRC[0]
183 BUFPLL1:DIVIDE[2]
182 BUFIO2_5:CMT_ENABLE
181 BUFIO2_5:CKPIN[0]
180 BUFIO2_5:IOCLK_ENABLE
179 BUFIO2_5:CKPIN[1]
178 ~BUFIO2_5:FB_DIVIDE_BYPASS[3]
177 ~BUFIO2_5:DIVIDE_BYPASS
176 -
175 BUFIO2_5:FB_ENABLE
174 -
173 ~BUFIO2_5:FB_DIVIDE_BYPASS[2]
172 ~BUFIO2_5:FB_DIVIDE_BYPASS[1]
171 ~BUFIO2_5:FB_DIVIDE_BYPASS[0]
170 -
169 -
168 -
167 -
166 -
165 -
164 BUFIO2_5:ENABLE_2CLK
163 BUFIO2_5:ENABLE
162 BUFIO2_5:R_EDGE
161 BUFIO2_5:DIVIDE[2]
160 BUFIO2_5:DIVIDE[1]
159 BUFIO2_5:DIVIDE[0]
158 -
157 BUFIO2_5:NEG_EDGE[1]
156 BUFIO2_5:NEG_EDGE[0]
155 BUFIO2_5:POS_EDGE[2]
154 BUFIO2_5:POS_EDGE[1]
153 BUFIO2_5:POS_EDGE[0]
152 BUFIO2_5:FB_I[2]
151 BUFIO2_5:FB_I[1]
150 BUFIO2_5:FB_I[0]
149 BUFIO2_5:IB[2]
148 BUFIO2_5:IB[1]
147 BUFIO2_5:IB[0]
146 BUFIO2_5:I[2]
145 BUFIO2_5:I[1]
144 BUFIO2_5:I[0]
143 BUFPLL1:DIVIDE[1]
142 BUFPLL1:DIVIDE[0]
141 BUFPLL0:DATA_RATE[0]
140 ~BUFPLL0:ENABLE_SYNC
139 BUFPLL_MCB:LOCK_SRC[1]
138 BUFPLL0:DIVIDE[2]
137 BUFPLL0:DIVIDE[1]
136 BUFPLL0:DIVIDE[0]
135 BUFPLL_COMMON:ENABLE
134 BUFIO2_4:CMT_ENABLE
133 BUFIO2_4:CKPIN[0]
132 BUFIO2_4:IOCLK_ENABLE
131 BUFIO2_4:CKPIN[1]
130 ~BUFIO2_4:FB_DIVIDE_BYPASS[3]
129 ~BUFIO2_4:DIVIDE_BYPASS
128 -
127 BUFIO2_4:FB_ENABLE
126 -
125 ~BUFIO2_4:FB_DIVIDE_BYPASS[2]
124 ~BUFIO2_4:FB_DIVIDE_BYPASS[1]
123 ~BUFIO2_4:FB_DIVIDE_BYPASS[0]
122 -
121 -
120 -
119 -
118 -
117 -
116 BUFIO2_4:ENABLE_2CLK
115 BUFIO2_4:ENABLE
114 BUFIO2_4:R_EDGE
113 BUFIO2_4:DIVIDE[2]
112 BUFIO2_4:DIVIDE[1]
111 BUFIO2_4:DIVIDE[0]
110 -
109 BUFIO2_4:NEG_EDGE[1]
108 BUFIO2_4:NEG_EDGE[0]
107 BUFIO2_4:POS_EDGE[2]
106 BUFIO2_4:POS_EDGE[1]
105 BUFIO2_4:POS_EDGE[0]
104 BUFIO2_4:FB_I[2]
103 BUFIO2_4:FB_I[1]
102 BUFIO2_4:FB_I[0]
101 BUFIO2_4:IB[2]
100 BUFIO2_4:IB[1]
99 BUFIO2_4:IB[0]
98 BUFIO2_4:I[2]
97 BUFIO2_4:I[1]
96 BUFIO2_4:I[0]
95 -
94 -
93 INT:MUX.IMUX.REGT.GCLK0[4]
92 INT:MUX.IMUX.REGT.GCLK0[5]
91 INT:MUX.IMUX.REGT.GCLK0[6]
90 INT:MUX.IMUX.REGT.GCLK0[7]
89 INT:MUX.IMUX.REGT.GCLK0[0]
88 INT:MUX.IMUX.REGT.GCLK0[1]
87 INT:MUX.IMUX.REGT.GCLK0[2]
86 BUFIO2_7:CMT_ENABLE
85 BUFIO2_7:CKPIN[0]
84 BUFIO2_7:IOCLK_ENABLE
83 BUFIO2_7:CKPIN[1]
82 ~BUFIO2_7:FB_DIVIDE_BYPASS[3]
81 ~BUFIO2_7:DIVIDE_BYPASS
80 -
79 BUFIO2_7:FB_ENABLE
78 -
77 ~BUFIO2_7:FB_DIVIDE_BYPASS[2]
76 ~BUFIO2_7:FB_DIVIDE_BYPASS[1]
75 ~BUFIO2_7:FB_DIVIDE_BYPASS[0]
74 -
73 -
72 -
71 -
70 -
69 -
68 BUFIO2_7:ENABLE_2CLK
67 BUFIO2_7:ENABLE
66 BUFIO2_7:R_EDGE
65 BUFIO2_7:DIVIDE[2]
64 BUFIO2_7:DIVIDE[1]
63 BUFIO2_7:DIVIDE[0]
62 -
61 BUFIO2_7:NEG_EDGE[1]
60 BUFIO2_7:NEG_EDGE[0]
59 BUFIO2_7:POS_EDGE[2]
58 BUFIO2_7:POS_EDGE[1]
57 BUFIO2_7:POS_EDGE[0]
56 BUFIO2_7:FB_I[2]
55 BUFIO2_7:FB_I[1]
54 BUFIO2_7:FB_I[0]
53 BUFIO2_7:IB[2]
52 BUFIO2_7:IB[1]
51 BUFIO2_7:IB[0]
50 BUFIO2_7:I[2]
49 BUFIO2_7:I[1]
48 BUFIO2_7:I[0]
47 INT:MUX.IMUX.REGT.GCLK0[3]
46 INT:MUX.IMUX.REGT.GCLK1[3]
45 INT:MUX.IMUX.REGT.GCLK1[2]
44 INT:MUX.IMUX.REGT.GCLK1[1]
43 INT:MUX.IMUX.REGT.GCLK1[0]
42 INT:MUX.IMUX.REGT.GCLK1[7]
41 INT:MUX.IMUX.REGT.GCLK1[6]
40 INT:MUX.IMUX.REGT.GCLK1[5]
39 INT:MUX.IMUX.REGT.GCLK1[4]
38 BUFIO2_6:CMT_ENABLE
37 BUFIO2_6:CKPIN[0]
36 BUFIO2_6:IOCLK_ENABLE
35 BUFIO2_6:CKPIN[1]
34 ~BUFIO2_6:FB_DIVIDE_BYPASS[3]
33 ~BUFIO2_6:DIVIDE_BYPASS
32 -
31 BUFIO2_6:FB_ENABLE
30 -
29 ~BUFIO2_6:FB_DIVIDE_BYPASS[2]
28 ~BUFIO2_6:FB_DIVIDE_BYPASS[1]
27 ~BUFIO2_6:FB_DIVIDE_BYPASS[0]
26 -
25 -
24 -
23 -
22 -
21 -
20 BUFIO2_6:ENABLE_2CLK
19 BUFIO2_6:ENABLE
18 BUFIO2_6:R_EDGE
17 BUFIO2_6:DIVIDE[2]
16 BUFIO2_6:DIVIDE[1]
15 BUFIO2_6:DIVIDE[0]
14 -
13 BUFIO2_6:NEG_EDGE[1]
12 BUFIO2_6:NEG_EDGE[0]
11 BUFIO2_6:POS_EDGE[2]
10 BUFIO2_6:POS_EDGE[1]
9 BUFIO2_6:POS_EDGE[0]
8 BUFIO2_6:FB_I[2]
7 BUFIO2_6:FB_I[1]
6 BUFIO2_6:FB_I[0]
5 BUFIO2_6:IB[2]
4 BUFIO2_6:IB[1]
3 BUFIO2_6:IB[0]
2 BUFIO2_6:I[2]
1 BUFIO2_6:I[1]
0 BUFIO2_6:I[0]
BUFIO2_0:CKPIN 0.0.323 0.0.325
BUFIO2_1:CKPIN 0.0.371 0.0.373
BUFIO2_2:CKPIN 0.0.227 0.0.229
BUFIO2_3:CKPIN 0.0.275 0.0.277
BUFIO2_4:CKPIN 0.0.131 0.0.133
BUFIO2_5:CKPIN 0.0.179 0.0.181
BUFIO2_6:CKPIN 0.0.35 0.0.37
BUFIO2_7:CKPIN 0.0.83 0.0.85
VCC 0 0
CLKPIN 0 1
DIVCLK 1 1
BUFIO2_0:CMT_ENABLE 0.0.326
BUFIO2_0:ENABLE 0.0.307
BUFIO2_0:ENABLE_2CLK 0.0.308
BUFIO2_0:FB_ENABLE 0.0.319
BUFIO2_0:IOCLK_ENABLE 0.0.324
BUFIO2_0:R_EDGE 0.0.306
BUFIO2_1:CMT_ENABLE 0.0.374
BUFIO2_1:ENABLE 0.0.355
BUFIO2_1:ENABLE_2CLK 0.0.356
BUFIO2_1:FB_ENABLE 0.0.367
BUFIO2_1:IOCLK_ENABLE 0.0.372
BUFIO2_1:R_EDGE 0.0.354
BUFIO2_2:CMT_ENABLE 0.0.230
BUFIO2_2:ENABLE 0.0.211
BUFIO2_2:ENABLE_2CLK 0.0.212
BUFIO2_2:FB_ENABLE 0.0.223
BUFIO2_2:IOCLK_ENABLE 0.0.228
BUFIO2_2:R_EDGE 0.0.210
BUFIO2_3:CMT_ENABLE 0.0.278
BUFIO2_3:ENABLE 0.0.259
BUFIO2_3:ENABLE_2CLK 0.0.260
BUFIO2_3:FB_ENABLE 0.0.271
BUFIO2_3:IOCLK_ENABLE 0.0.276
BUFIO2_3:R_EDGE 0.0.258
BUFIO2_4:CMT_ENABLE 0.0.134
BUFIO2_4:ENABLE 0.0.115
BUFIO2_4:ENABLE_2CLK 0.0.116
BUFIO2_4:FB_ENABLE 0.0.127
BUFIO2_4:IOCLK_ENABLE 0.0.132
BUFIO2_4:R_EDGE 0.0.114
BUFIO2_5:CMT_ENABLE 0.0.182
BUFIO2_5:ENABLE 0.0.163
BUFIO2_5:ENABLE_2CLK 0.0.164
BUFIO2_5:FB_ENABLE 0.0.175
BUFIO2_5:IOCLK_ENABLE 0.0.180
BUFIO2_5:R_EDGE 0.0.162
BUFIO2_6:CMT_ENABLE 0.0.38
BUFIO2_6:ENABLE 0.0.19
BUFIO2_6:ENABLE_2CLK 0.0.20
BUFIO2_6:FB_ENABLE 0.0.31
BUFIO2_6:IOCLK_ENABLE 0.0.36
BUFIO2_6:R_EDGE 0.0.18
BUFIO2_7:CMT_ENABLE 0.0.86
BUFIO2_7:ENABLE 0.0.67
BUFIO2_7:ENABLE_2CLK 0.0.68
BUFIO2_7:FB_ENABLE 0.0.79
BUFIO2_7:IOCLK_ENABLE 0.0.84
BUFIO2_7:R_EDGE 0.0.66
BUFPLL_COMMON:ENABLE 0.0.135
MISC:MISR_ENABLE 0.0.379
MISC:MISR_RESET 0.0.380
non-inverted [0]
BUFIO2_0:DIVIDE 0.0.305 0.0.304 0.0.303
BUFIO2_1:DIVIDE 0.0.353 0.0.352 0.0.351
BUFIO2_2:DIVIDE 0.0.209 0.0.208 0.0.207
BUFIO2_3:DIVIDE 0.0.257 0.0.256 0.0.255
BUFIO2_4:DIVIDE 0.0.113 0.0.112 0.0.111
BUFIO2_5:DIVIDE 0.0.161 0.0.160 0.0.159
BUFIO2_6:DIVIDE 0.0.17 0.0.16 0.0.15
BUFIO2_7:DIVIDE 0.0.65 0.0.64 0.0.63
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
1 1 1 1
BUFIO2_0:DIVIDE_BYPASS 0.0.321
BUFIO2_1:DIVIDE_BYPASS 0.0.369
BUFIO2_2:DIVIDE_BYPASS 0.0.225
BUFIO2_3:DIVIDE_BYPASS 0.0.273
BUFIO2_4:DIVIDE_BYPASS 0.0.129
BUFIO2_5:DIVIDE_BYPASS 0.0.177
BUFIO2_6:DIVIDE_BYPASS 0.0.33
BUFIO2_7:DIVIDE_BYPASS 0.0.81
BUFPLL0:ENABLE_SYNC 0.0.140
BUFPLL1:ENABLE_SYNC 0.0.185
inverted ~[0]
BUFIO2_0:FB_DIVIDE_BYPASS 0.0.322 0.0.317 0.0.316 0.0.315
BUFIO2_1:FB_DIVIDE_BYPASS 0.0.370 0.0.365 0.0.364 0.0.363
BUFIO2_2:FB_DIVIDE_BYPASS 0.0.226 0.0.221 0.0.220 0.0.219
BUFIO2_3:FB_DIVIDE_BYPASS 0.0.274 0.0.269 0.0.268 0.0.267
BUFIO2_4:FB_DIVIDE_BYPASS 0.0.130 0.0.125 0.0.124 0.0.123
BUFIO2_5:FB_DIVIDE_BYPASS 0.0.178 0.0.173 0.0.172 0.0.171
BUFIO2_6:FB_DIVIDE_BYPASS 0.0.34 0.0.29 0.0.28 0.0.27
BUFIO2_7:FB_DIVIDE_BYPASS 0.0.82 0.0.77 0.0.76 0.0.75
inverted ~[3] ~[2] ~[1] ~[0]
BUFIO2_0:FB_I 0.0.296 0.0.295 0.0.294
BUFIO2_1:FB_I 0.0.344 0.0.343 0.0.342
BUFIO2_2:FB_I 0.0.200 0.0.199 0.0.198
BUFIO2_3:FB_I 0.0.248 0.0.247 0.0.246
BUFIO2_4:FB_I 0.0.104 0.0.103 0.0.102
BUFIO2_5:FB_I 0.0.152 0.0.151 0.0.150
BUFIO2_6:FB_I 0.0.8 0.0.7 0.0.6
BUFIO2_7:FB_I 0.0.56 0.0.55 0.0.54
CLKPIN 0 0 0
DFB 0 0 1
CFB 0 1 0
CFB_INVERT 0 1 1
GTPFB 1 1 1
BUFIO2_0:I 0.0.290 0.0.289 0.0.288
BUFIO2_1:I 0.0.338 0.0.337 0.0.336
BUFIO2_2:I 0.0.194 0.0.193 0.0.192
BUFIO2_3:I 0.0.242 0.0.241 0.0.240
BUFIO2_4:I 0.0.98 0.0.97 0.0.96
BUFIO2_5:I 0.0.146 0.0.145 0.0.144
BUFIO2_6:I 0.0.2 0.0.1 0.0.0
BUFIO2_7:I 0.0.50 0.0.49 0.0.48
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
GTPCLK 1 1 1
BUFIO2_0:IB 0.0.293 0.0.292 0.0.291
BUFIO2_1:IB 0.0.341 0.0.340 0.0.339
BUFIO2_2:IB 0.0.197 0.0.196 0.0.195
BUFIO2_3:IB 0.0.245 0.0.244 0.0.243
BUFIO2_4:IB 0.0.101 0.0.100 0.0.99
BUFIO2_5:IB 0.0.149 0.0.148 0.0.147
BUFIO2_6:IB 0.0.5 0.0.4 0.0.3
BUFIO2_7:IB 0.0.53 0.0.52 0.0.51
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFIO2_0:NEG_EDGE 0.0.301 0.0.300
BUFIO2_1:NEG_EDGE 0.0.349 0.0.348
BUFIO2_2:NEG_EDGE 0.0.205 0.0.204
BUFIO2_3:NEG_EDGE 0.0.253 0.0.252
BUFIO2_4:NEG_EDGE 0.0.109 0.0.108
BUFIO2_5:NEG_EDGE 0.0.157 0.0.156
BUFIO2_6:NEG_EDGE 0.0.13 0.0.12
BUFIO2_7:NEG_EDGE 0.0.61 0.0.60
DIVIDE_1 0 0
DIVIDE_3 0 0
DIVIDE_4 0 0
NEG_EDGE_1 0 0
NEG_EDGE_4 0 0
NEG_EDGE_5 0 0
NEG_EDGE_6 0 0
NEG_EDGE_7 0 0
NEG_EDGE_8 0 0
DIVIDE_2 0 1
DIVIDE_5 0 1
DIVIDE_6 0 1
NEG_EDGE_2 0 1
DIVIDE_7 1 0
DIVIDE_8 1 0
NEG_EDGE_3 1 0
BUFIO2_0:POS_EDGE 0.0.299 0.0.298 0.0.297
BUFIO2_1:POS_EDGE 0.0.347 0.0.346 0.0.345
BUFIO2_2:POS_EDGE 0.0.203 0.0.202 0.0.201
BUFIO2_3:POS_EDGE 0.0.251 0.0.250 0.0.249
BUFIO2_4:POS_EDGE 0.0.107 0.0.106 0.0.105
BUFIO2_5:POS_EDGE 0.0.155 0.0.154 0.0.153
BUFIO2_6:POS_EDGE 0.0.11 0.0.10 0.0.9
BUFIO2_7:POS_EDGE 0.0.59 0.0.58 0.0.57
DIVIDE_1 0 0 0
POS_EDGE_1 0 0 0
POS_EDGE_3 0 0 0
POS_EDGE_5 0 0 0
DIVIDE_2 0 0 1
POS_EDGE_2 0 0 1
DIVIDE_3 0 1 0
DIVIDE_4 0 1 1
POS_EDGE_4 0 1 1
DIVIDE_5 1 0 0
DIVIDE_6 1 0 1
POS_EDGE_6 1 0 1
DIVIDE_7 1 1 0
POS_EDGE_7 1 1 0
DIVIDE_8 1 1 1
POS_EDGE_8 1 1 1
BUFPLL0:DATA_RATE 0.0.141
BUFPLL1:DATA_RATE 0.0.186
SDR 0
DDR 1
BUFPLL0:DIVIDE 0.0.190 0.0.189 0.0.187 0.0.138 0.0.137 0.0.136
BUFPLL1:DIVIDE 0.0.233 0.0.232 0.0.191 0.0.183 0.0.143 0.0.142
3 0 0 0 0 0 1
2 0 0 1 0 0 0
5 0 1 0 0 1 1
4 0 1 1 0 1 0
7 1 0 0 1 0 1
6 1 0 1 1 0 0
1 1 1 0 1 1 1
8 1 1 1 1 1 0
BUFPLL0:ENABLE_BOTH_SYNC 0.0.286 0.0.280 0.0.234
BUFPLL1:ENABLE_BOTH_SYNC 0.0.329 0.0.282 0.0.237
non-inverted [2] [1] [0]
BUFPLL0:ENABLE_NONE_SYNC 0.0.285 0.0.279
BUFPLL1:ENABLE_NONE_SYNC 0.0.328 0.0.281
non-inverted [1] [0]
BUFPLL0:LOCKED 0.0.376 0.0.375
BUFPLL1:LOCKED 0.0.378 0.0.377
LOCKED0 0 0
LOCKED1 0 1
LOCKED2 1 0
BUFPLL0:PLLIN 0.0.332 0.0.331 0.0.330
BUFPLL1:PLLIN 0.0.335 0.0.334 0.0.333
PLLIN0 0 0 0
PLLIN1 0 0 1
PLLIN2 0 1 0
PLLIN3 0 1 1
PLLIN4 1 0 0
PLLIN5 1 0 1
BUFPLL_MCB:LOCK_SRC 0.0.139 0.0.184
LOCK_TO_0 0 1
LOCK_TO_1 1 0
INT:MUX.IMUX.REGT.GCLK0 0.0.90 0.0.91 0.0.92 0.0.93 0.0.47 0.0.87 0.0.88 0.0.89
INT:MUX.IMUX.REGT.GCLK1 0.0.42 0.0.41 0.0.40 0.0.39 0.0.46 0.0.45 0.0.44 0.0.43
NONE 0 0 0 0 0 0 0 0
GCLK0 0 1 0 1 0 0 0 1
GCLK1 0 1 0 1 0 0 1 0
GCLK2 0 1 0 1 0 1 0 0
GCLK3 0 1 0 1 1 0 0 0
GCLK8 0 1 1 0 0 0 0 1
GCLK9 0 1 1 0 0 0 1 0
GCLK10 0 1 1 0 0 1 0 0
GCLK11 0 1 1 0 1 0 0 0
GCLK4 1 0 0 1 0 0 0 1
GCLK5 1 0 0 1 0 0 1 0
GCLK6 1 0 0 1 0 1 0 0
GCLK7 1 0 0 1 1 0 0 0
GCLK12 1 0 1 0 0 0 0 1
GCLK13 1 0 1 0 0 0 1 0
GCLK14 1 0 1 0 0 1 0 0
GCLK15 1 0 1 0 1 0 0 0

Tile REG_L

Cells: 1 IRIs: 0

Bel BUFIO2_0

spartan6 REG_L bel BUFIO2_0
PinDirectionWires

Bel BUFIO2_1

spartan6 REG_L bel BUFIO2_1
PinDirectionWires

Bel BUFIO2_2

spartan6 REG_L bel BUFIO2_2
PinDirectionWires

Bel BUFIO2_3

spartan6 REG_L bel BUFIO2_3
PinDirectionWires

Bel BUFIO2_4

spartan6 REG_L bel BUFIO2_4
PinDirectionWires

Bel BUFIO2_5

spartan6 REG_L bel BUFIO2_5
PinDirectionWires

Bel BUFIO2_6

spartan6 REG_L bel BUFIO2_6
PinDirectionWires

Bel BUFIO2_7

spartan6 REG_L bel BUFIO2_7
PinDirectionWires

Bel BUFIO2FB_0

spartan6 REG_L bel BUFIO2FB_0
PinDirectionWires

Bel BUFIO2FB_1

spartan6 REG_L bel BUFIO2FB_1
PinDirectionWires

Bel BUFIO2FB_2

spartan6 REG_L bel BUFIO2FB_2
PinDirectionWires

Bel BUFIO2FB_3

spartan6 REG_L bel BUFIO2FB_3
PinDirectionWires

Bel BUFIO2FB_4

spartan6 REG_L bel BUFIO2FB_4
PinDirectionWires

Bel BUFIO2FB_5

spartan6 REG_L bel BUFIO2FB_5
PinDirectionWires

Bel BUFIO2FB_6

spartan6 REG_L bel BUFIO2FB_6
PinDirectionWires

Bel BUFIO2FB_7

spartan6 REG_L bel BUFIO2FB_7
PinDirectionWires

Bel BUFPLL0

spartan6 REG_L bel BUFPLL0
PinDirectionWires

Bel BUFPLL1

spartan6 REG_L bel BUFPLL1
PinDirectionWires

Bel BUFPLL_MCB

spartan6 REG_L bel BUFPLL_MCB
PinDirectionWires

Bel BUFPLL_OUT

spartan6 REG_L bel BUFPLL_OUT
PinDirectionWires
LOCK0outputOUT0
LOCK1outputOUT1

Bel BUFPLL_INS_LR

spartan6 REG_L bel BUFPLL_INS_LR
PinDirectionWires
GCLK0inputIMUX.CLK0
GCLK1inputIMUX.CLK1
PLLIN0_GCLKinputIMUX.CLK0
PLLIN1_GCLKinputIMUX.CLK1

Bel BUFIO2_INS

spartan6 REG_L bel BUFIO2_INS
PinDirectionWires

Bel BUFIO2_CKPIN

spartan6 REG_L bel BUFIO2_CKPIN
PinDirectionWires

Bel BUFPLL_BUF

spartan6 REG_L bel BUFPLL_BUF
PinDirectionWires

Bel TIEOFF_REG

spartan6 REG_L bel TIEOFF_REG
PinDirectionWires

Bel wires

spartan6 REG_L bel wires
WirePins
IMUX.CLK0BUFPLL_INS_LR.GCLK0
IMUX.CLK1BUFPLL_INS_LR.GCLK1
OUT0BUFPLL_OUT.LOCK0
OUT1BUFPLL_OUT.LOCK1
IMUX.CLK0BUFPLL_INS_LR.PLLIN0_GCLK
IMUX.CLK1BUFPLL_INS_LR.PLLIN1_GCLK

Bitstream

spartan6 REG_L bittile 0
BitFrame
0
374 BUFIO2_1:CMT_ENABLE
373 BUFIO2_1:CKPIN[0]
372 BUFIO2_1:IOCLK_ENABLE
371 BUFIO2_1:CKPIN[1]
370 ~BUFIO2_1:FB_DIVIDE_BYPASS[3]
369 ~BUFIO2_1:DIVIDE_BYPASS
368 -
367 BUFIO2_1:FB_ENABLE
366 -
365 ~BUFIO2_1:FB_DIVIDE_BYPASS[2]
364 ~BUFIO2_1:FB_DIVIDE_BYPASS[1]
363 ~BUFIO2_1:FB_DIVIDE_BYPASS[0]
362 -
361 -
360 -
359 -
358 -
357 -
356 BUFIO2_1:ENABLE_2CLK
355 BUFIO2_1:ENABLE
354 BUFIO2_1:R_EDGE
353 BUFIO2_1:DIVIDE[2]
352 BUFIO2_1:DIVIDE[1]
351 BUFIO2_1:DIVIDE[0]
350 -
349 BUFIO2_1:NEG_EDGE[1]
348 BUFIO2_1:NEG_EDGE[0]
347 BUFIO2_1:POS_EDGE[2]
346 BUFIO2_1:POS_EDGE[1]
345 BUFIO2_1:POS_EDGE[0]
344 BUFIO2_1:FB_I[2]
343 BUFIO2_1:FB_I[1]
342 BUFIO2_1:FB_I[0]
341 BUFIO2_1:IB[2]
340 BUFIO2_1:IB[1]
339 BUFIO2_1:IB[0]
338 BUFIO2_1:I[2]
337 BUFIO2_1:I[1]
336 BUFIO2_1:I[0]
335 -
334 -
333 -
332 -
331 -
330 BUFPLL_COMMON:PLLIN[0]
329 BUFPLL1:ENABLE_BOTH_SYNC[2]
328 BUFPLL1:ENABLE_NONE_SYNC[1]
327 -
326 BUFIO2_0:CMT_ENABLE
325 BUFIO2_0:CKPIN[0]
324 BUFIO2_0:IOCLK_ENABLE
323 BUFIO2_0:CKPIN[1]
322 ~BUFIO2_0:FB_DIVIDE_BYPASS[3]
321 ~BUFIO2_0:DIVIDE_BYPASS
320 -
319 BUFIO2_0:FB_ENABLE
318 -
317 ~BUFIO2_0:FB_DIVIDE_BYPASS[2]
316 ~BUFIO2_0:FB_DIVIDE_BYPASS[1]
315 ~BUFIO2_0:FB_DIVIDE_BYPASS[0]
314 -
313 -
312 -
311 -
310 -
309 -
308 BUFIO2_0:ENABLE_2CLK
307 BUFIO2_0:ENABLE
306 BUFIO2_0:R_EDGE
305 BUFIO2_0:DIVIDE[2]
304 BUFIO2_0:DIVIDE[1]
303 BUFIO2_0:DIVIDE[0]
302 -
301 BUFIO2_0:NEG_EDGE[1]
300 BUFIO2_0:NEG_EDGE[0]
299 BUFIO2_0:POS_EDGE[2]
298 BUFIO2_0:POS_EDGE[1]
297 BUFIO2_0:POS_EDGE[0]
296 BUFIO2_0:FB_I[2]
295 BUFIO2_0:FB_I[1]
294 BUFIO2_0:FB_I[0]
293 BUFIO2_0:IB[2]
292 BUFIO2_0:IB[1]
291 BUFIO2_0:IB[0]
290 BUFIO2_0:I[2]
289 BUFIO2_0:I[1]
288 BUFIO2_0:I[0]
287 -
286 BUFPLL0:ENABLE_BOTH_SYNC[2]
285 BUFPLL0:ENABLE_NONE_SYNC[1]
284 -
283 -
282 BUFPLL1:ENABLE_BOTH_SYNC[1]
281 BUFPLL1:ENABLE_NONE_SYNC[0]
280 BUFPLL0:ENABLE_BOTH_SYNC[1]
279 BUFPLL0:ENABLE_NONE_SYNC[0]
278 BUFIO2_3:CMT_ENABLE
277 BUFIO2_3:CKPIN[0]
276 BUFIO2_3:IOCLK_ENABLE
275 BUFIO2_3:CKPIN[1]
274 ~BUFIO2_3:FB_DIVIDE_BYPASS[3]
273 ~BUFIO2_3:DIVIDE_BYPASS
272 -
271 BUFIO2_3:FB_ENABLE
270 -
269 ~BUFIO2_3:FB_DIVIDE_BYPASS[2]
268 ~BUFIO2_3:FB_DIVIDE_BYPASS[1]
267 ~BUFIO2_3:FB_DIVIDE_BYPASS[0]
266 -
265 -
264 -
263 -
262 -
261 -
260 BUFIO2_3:ENABLE_2CLK
259 BUFIO2_3:ENABLE
258 BUFIO2_3:R_EDGE
257 BUFIO2_3:DIVIDE[2]
256 BUFIO2_3:DIVIDE[1]
255 BUFIO2_3:DIVIDE[0]
254 -
253 BUFIO2_3:NEG_EDGE[1]
252 BUFIO2_3:NEG_EDGE[0]
251 BUFIO2_3:POS_EDGE[2]
250 BUFIO2_3:POS_EDGE[1]
249 BUFIO2_3:POS_EDGE[0]
248 BUFIO2_3:FB_I[2]
247 BUFIO2_3:FB_I[1]
246 BUFIO2_3:FB_I[0]
245 BUFIO2_3:IB[2]
244 BUFIO2_3:IB[1]
243 BUFIO2_3:IB[0]
242 BUFIO2_3:I[2]
241 BUFIO2_3:I[1]
240 BUFIO2_3:I[0]
239 -
238 -
237 BUFPLL1:ENABLE_BOTH_SYNC[0]
236 -
235 -
234 BUFPLL0:ENABLE_BOTH_SYNC[0]
233 BUFPLL1:DIVIDE[5]
232 BUFPLL1:DIVIDE[4]
231 -
230 BUFIO2_2:CMT_ENABLE
229 BUFIO2_2:CKPIN[0]
228 BUFIO2_2:IOCLK_ENABLE
227 BUFIO2_2:CKPIN[1]
226 ~BUFIO2_2:FB_DIVIDE_BYPASS[3]
225 ~BUFIO2_2:DIVIDE_BYPASS
224 -
223 BUFIO2_2:FB_ENABLE
222 -
221 ~BUFIO2_2:FB_DIVIDE_BYPASS[2]
220 ~BUFIO2_2:FB_DIVIDE_BYPASS[1]
219 ~BUFIO2_2:FB_DIVIDE_BYPASS[0]
218 -
217 -
216 -
215 -
214 -
213 -
212 BUFIO2_2:ENABLE_2CLK
211 BUFIO2_2:ENABLE
210 BUFIO2_2:R_EDGE
209 BUFIO2_2:DIVIDE[2]
208 BUFIO2_2:DIVIDE[1]
207 BUFIO2_2:DIVIDE[0]
206 -
205 BUFIO2_2:NEG_EDGE[1]
204 BUFIO2_2:NEG_EDGE[0]
203 BUFIO2_2:POS_EDGE[2]
202 BUFIO2_2:POS_EDGE[1]
201 BUFIO2_2:POS_EDGE[0]
200 BUFIO2_2:FB_I[2]
199 BUFIO2_2:FB_I[1]
198 BUFIO2_2:FB_I[0]
197 BUFIO2_2:IB[2]
196 BUFIO2_2:IB[1]
195 BUFIO2_2:IB[0]
194 BUFIO2_2:I[2]
193 BUFIO2_2:I[1]
192 BUFIO2_2:I[0]
191 BUFPLL1:DIVIDE[3]
190 BUFPLL0:DIVIDE[5]
189 BUFPLL0:DIVIDE[4]
188 -
187 BUFPLL0:DIVIDE[3]
186 BUFPLL1:DATA_RATE[0]
185 ~BUFPLL1:ENABLE_SYNC
184 BUFPLL_MCB:LOCK_SRC[0]
183 BUFPLL1:DIVIDE[2]
182 BUFIO2_5:CMT_ENABLE
181 BUFIO2_5:CKPIN[0]
180 BUFIO2_5:IOCLK_ENABLE
179 BUFIO2_5:CKPIN[1]
178 ~BUFIO2_5:FB_DIVIDE_BYPASS[3]
177 ~BUFIO2_5:DIVIDE_BYPASS
176 -
175 BUFIO2_5:FB_ENABLE
174 -
173 ~BUFIO2_5:FB_DIVIDE_BYPASS[2]
172 ~BUFIO2_5:FB_DIVIDE_BYPASS[1]
171 ~BUFIO2_5:FB_DIVIDE_BYPASS[0]
170 -
169 -
168 -
167 -
166 -
165 -
164 BUFIO2_5:ENABLE_2CLK
163 BUFIO2_5:ENABLE
162 BUFIO2_5:R_EDGE
161 BUFIO2_5:DIVIDE[2]
160 BUFIO2_5:DIVIDE[1]
159 BUFIO2_5:DIVIDE[0]
158 -
157 BUFIO2_5:NEG_EDGE[1]
156 BUFIO2_5:NEG_EDGE[0]
155 BUFIO2_5:POS_EDGE[2]
154 BUFIO2_5:POS_EDGE[1]
153 BUFIO2_5:POS_EDGE[0]
152 BUFIO2_5:FB_I[2]
151 BUFIO2_5:FB_I[1]
150 BUFIO2_5:FB_I[0]
149 BUFIO2_5:IB[2]
148 BUFIO2_5:IB[1]
147 BUFIO2_5:IB[0]
146 BUFIO2_5:I[2]
145 BUFIO2_5:I[1]
144 BUFIO2_5:I[0]
143 BUFPLL1:DIVIDE[1]
142 BUFPLL1:DIVIDE[0]
141 BUFPLL0:DATA_RATE[0]
140 ~BUFPLL0:ENABLE_SYNC
139 BUFPLL_MCB:LOCK_SRC[1]
138 BUFPLL0:DIVIDE[2]
137 BUFPLL0:DIVIDE[1]
136 BUFPLL0:DIVIDE[0]
135 BUFPLL_COMMON:ENABLE
134 BUFIO2_4:CMT_ENABLE
133 BUFIO2_4:CKPIN[0]
132 BUFIO2_4:IOCLK_ENABLE
131 BUFIO2_4:CKPIN[1]
130 ~BUFIO2_4:FB_DIVIDE_BYPASS[3]
129 ~BUFIO2_4:DIVIDE_BYPASS
128 -
127 BUFIO2_4:FB_ENABLE
126 -
125 ~BUFIO2_4:FB_DIVIDE_BYPASS[2]
124 ~BUFIO2_4:FB_DIVIDE_BYPASS[1]
123 ~BUFIO2_4:FB_DIVIDE_BYPASS[0]
122 -
121 -
120 -
119 -
118 -
117 -
116 BUFIO2_4:ENABLE_2CLK
115 BUFIO2_4:ENABLE
114 BUFIO2_4:R_EDGE
113 BUFIO2_4:DIVIDE[2]
112 BUFIO2_4:DIVIDE[1]
111 BUFIO2_4:DIVIDE[0]
110 -
109 BUFIO2_4:NEG_EDGE[1]
108 BUFIO2_4:NEG_EDGE[0]
107 BUFIO2_4:POS_EDGE[2]
106 BUFIO2_4:POS_EDGE[1]
105 BUFIO2_4:POS_EDGE[0]
104 BUFIO2_4:FB_I[2]
103 BUFIO2_4:FB_I[1]
102 BUFIO2_4:FB_I[0]
101 BUFIO2_4:IB[2]
100 BUFIO2_4:IB[1]
99 BUFIO2_4:IB[0]
98 BUFIO2_4:I[2]
97 BUFIO2_4:I[1]
96 BUFIO2_4:I[0]
95 -
94 -
93 -
92 -
91 -
90 -
89 -
88 -
87 -
86 BUFIO2_7:CMT_ENABLE
85 BUFIO2_7:CKPIN[0]
84 BUFIO2_7:IOCLK_ENABLE
83 BUFIO2_7:CKPIN[1]
82 ~BUFIO2_7:FB_DIVIDE_BYPASS[3]
81 ~BUFIO2_7:DIVIDE_BYPASS
80 -
79 BUFIO2_7:FB_ENABLE
78 -
77 ~BUFIO2_7:FB_DIVIDE_BYPASS[2]
76 ~BUFIO2_7:FB_DIVIDE_BYPASS[1]
75 ~BUFIO2_7:FB_DIVIDE_BYPASS[0]
74 -
73 -
72 -
71 -
70 -
69 -
68 BUFIO2_7:ENABLE_2CLK
67 BUFIO2_7:ENABLE
66 BUFIO2_7:R_EDGE
65 BUFIO2_7:DIVIDE[2]
64 BUFIO2_7:DIVIDE[1]
63 BUFIO2_7:DIVIDE[0]
62 -
61 BUFIO2_7:NEG_EDGE[1]
60 BUFIO2_7:NEG_EDGE[0]
59 BUFIO2_7:POS_EDGE[2]
58 BUFIO2_7:POS_EDGE[1]
57 BUFIO2_7:POS_EDGE[0]
56 BUFIO2_7:FB_I[2]
55 BUFIO2_7:FB_I[1]
54 BUFIO2_7:FB_I[0]
53 BUFIO2_7:IB[2]
52 BUFIO2_7:IB[1]
51 BUFIO2_7:IB[0]
50 BUFIO2_7:I[2]
49 BUFIO2_7:I[1]
48 BUFIO2_7:I[0]
47 -
46 -
45 -
44 -
43 -
42 -
41 -
40 -
39 -
38 BUFIO2_6:CMT_ENABLE
37 BUFIO2_6:CKPIN[0]
36 BUFIO2_6:IOCLK_ENABLE
35 BUFIO2_6:CKPIN[1]
34 ~BUFIO2_6:FB_DIVIDE_BYPASS[3]
33 ~BUFIO2_6:DIVIDE_BYPASS
32 -
31 BUFIO2_6:FB_ENABLE
30 -
29 ~BUFIO2_6:FB_DIVIDE_BYPASS[2]
28 ~BUFIO2_6:FB_DIVIDE_BYPASS[1]
27 ~BUFIO2_6:FB_DIVIDE_BYPASS[0]
26 -
25 -
24 -
23 -
22 -
21 -
20 BUFIO2_6:ENABLE_2CLK
19 BUFIO2_6:ENABLE
18 BUFIO2_6:R_EDGE
17 BUFIO2_6:DIVIDE[2]
16 BUFIO2_6:DIVIDE[1]
15 BUFIO2_6:DIVIDE[0]
14 -
13 BUFIO2_6:NEG_EDGE[1]
12 BUFIO2_6:NEG_EDGE[0]
11 BUFIO2_6:POS_EDGE[2]
10 BUFIO2_6:POS_EDGE[1]
9 BUFIO2_6:POS_EDGE[0]
8 BUFIO2_6:FB_I[2]
7 BUFIO2_6:FB_I[1]
6 BUFIO2_6:FB_I[0]
5 BUFIO2_6:IB[2]
4 BUFIO2_6:IB[1]
3 BUFIO2_6:IB[0]
2 BUFIO2_6:I[2]
1 BUFIO2_6:I[1]
0 BUFIO2_6:I[0]
BUFIO2_0:CKPIN 0.0.323 0.0.325
BUFIO2_1:CKPIN 0.0.371 0.0.373
BUFIO2_2:CKPIN 0.0.227 0.0.229
BUFIO2_3:CKPIN 0.0.275 0.0.277
BUFIO2_4:CKPIN 0.0.131 0.0.133
BUFIO2_5:CKPIN 0.0.179 0.0.181
BUFIO2_6:CKPIN 0.0.35 0.0.37
BUFIO2_7:CKPIN 0.0.83 0.0.85
VCC 0 0
CLKPIN 0 1
DIVCLK 1 1
BUFIO2_0:CMT_ENABLE 0.0.326
BUFIO2_0:ENABLE 0.0.307
BUFIO2_0:ENABLE_2CLK 0.0.308
BUFIO2_0:FB_ENABLE 0.0.319
BUFIO2_0:IOCLK_ENABLE 0.0.324
BUFIO2_0:R_EDGE 0.0.306
BUFIO2_1:CMT_ENABLE 0.0.374
BUFIO2_1:ENABLE 0.0.355
BUFIO2_1:ENABLE_2CLK 0.0.356
BUFIO2_1:FB_ENABLE 0.0.367
BUFIO2_1:IOCLK_ENABLE 0.0.372
BUFIO2_1:R_EDGE 0.0.354
BUFIO2_2:CMT_ENABLE 0.0.230
BUFIO2_2:ENABLE 0.0.211
BUFIO2_2:ENABLE_2CLK 0.0.212
BUFIO2_2:FB_ENABLE 0.0.223
BUFIO2_2:IOCLK_ENABLE 0.0.228
BUFIO2_2:R_EDGE 0.0.210
BUFIO2_3:CMT_ENABLE 0.0.278
BUFIO2_3:ENABLE 0.0.259
BUFIO2_3:ENABLE_2CLK 0.0.260
BUFIO2_3:FB_ENABLE 0.0.271
BUFIO2_3:IOCLK_ENABLE 0.0.276
BUFIO2_3:R_EDGE 0.0.258
BUFIO2_4:CMT_ENABLE 0.0.134
BUFIO2_4:ENABLE 0.0.115
BUFIO2_4:ENABLE_2CLK 0.0.116
BUFIO2_4:FB_ENABLE 0.0.127
BUFIO2_4:IOCLK_ENABLE 0.0.132
BUFIO2_4:R_EDGE 0.0.114
BUFIO2_5:CMT_ENABLE 0.0.182
BUFIO2_5:ENABLE 0.0.163
BUFIO2_5:ENABLE_2CLK 0.0.164
BUFIO2_5:FB_ENABLE 0.0.175
BUFIO2_5:IOCLK_ENABLE 0.0.180
BUFIO2_5:R_EDGE 0.0.162
BUFIO2_6:CMT_ENABLE 0.0.38
BUFIO2_6:ENABLE 0.0.19
BUFIO2_6:ENABLE_2CLK 0.0.20
BUFIO2_6:FB_ENABLE 0.0.31
BUFIO2_6:IOCLK_ENABLE 0.0.36
BUFIO2_6:R_EDGE 0.0.18
BUFIO2_7:CMT_ENABLE 0.0.86
BUFIO2_7:ENABLE 0.0.67
BUFIO2_7:ENABLE_2CLK 0.0.68
BUFIO2_7:FB_ENABLE 0.0.79
BUFIO2_7:IOCLK_ENABLE 0.0.84
BUFIO2_7:R_EDGE 0.0.66
BUFPLL_COMMON:ENABLE 0.0.135
non-inverted [0]
BUFIO2_0:DIVIDE 0.0.305 0.0.304 0.0.303
BUFIO2_1:DIVIDE 0.0.353 0.0.352 0.0.351
BUFIO2_2:DIVIDE 0.0.209 0.0.208 0.0.207
BUFIO2_3:DIVIDE 0.0.257 0.0.256 0.0.255
BUFIO2_4:DIVIDE 0.0.113 0.0.112 0.0.111
BUFIO2_5:DIVIDE 0.0.161 0.0.160 0.0.159
BUFIO2_6:DIVIDE 0.0.17 0.0.16 0.0.15
BUFIO2_7:DIVIDE 0.0.65 0.0.64 0.0.63
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
1 1 1 1
BUFIO2_0:DIVIDE_BYPASS 0.0.321
BUFIO2_1:DIVIDE_BYPASS 0.0.369
BUFIO2_2:DIVIDE_BYPASS 0.0.225
BUFIO2_3:DIVIDE_BYPASS 0.0.273
BUFIO2_4:DIVIDE_BYPASS 0.0.129
BUFIO2_5:DIVIDE_BYPASS 0.0.177
BUFIO2_6:DIVIDE_BYPASS 0.0.33
BUFIO2_7:DIVIDE_BYPASS 0.0.81
BUFPLL0:ENABLE_SYNC 0.0.140
BUFPLL1:ENABLE_SYNC 0.0.185
inverted ~[0]
BUFIO2_0:FB_DIVIDE_BYPASS 0.0.322 0.0.317 0.0.316 0.0.315
BUFIO2_1:FB_DIVIDE_BYPASS 0.0.370 0.0.365 0.0.364 0.0.363
BUFIO2_2:FB_DIVIDE_BYPASS 0.0.226 0.0.221 0.0.220 0.0.219
BUFIO2_3:FB_DIVIDE_BYPASS 0.0.274 0.0.269 0.0.268 0.0.267
BUFIO2_4:FB_DIVIDE_BYPASS 0.0.130 0.0.125 0.0.124 0.0.123
BUFIO2_5:FB_DIVIDE_BYPASS 0.0.178 0.0.173 0.0.172 0.0.171
BUFIO2_6:FB_DIVIDE_BYPASS 0.0.34 0.0.29 0.0.28 0.0.27
BUFIO2_7:FB_DIVIDE_BYPASS 0.0.82 0.0.77 0.0.76 0.0.75
inverted ~[3] ~[2] ~[1] ~[0]
BUFIO2_0:FB_I 0.0.296 0.0.295 0.0.294
BUFIO2_1:FB_I 0.0.344 0.0.343 0.0.342
BUFIO2_2:FB_I 0.0.200 0.0.199 0.0.198
BUFIO2_3:FB_I 0.0.248 0.0.247 0.0.246
BUFIO2_4:FB_I 0.0.104 0.0.103 0.0.102
BUFIO2_5:FB_I 0.0.152 0.0.151 0.0.150
BUFIO2_6:FB_I 0.0.8 0.0.7 0.0.6
BUFIO2_7:FB_I 0.0.56 0.0.55 0.0.54
CLKPIN 0 0 0
DFB 0 0 1
CFB 0 1 0
CFB_INVERT 0 1 1
GTPFB 1 1 1
BUFIO2_0:I 0.0.290 0.0.289 0.0.288
BUFIO2_2:I 0.0.194 0.0.193 0.0.192
BUFIO2_4:I 0.0.98 0.0.97 0.0.96
BUFIO2_5:I 0.0.146 0.0.145 0.0.144
BUFIO2_6:I 0.0.2 0.0.1 0.0.0
BUFIO2_7:I 0.0.50 0.0.49 0.0.48
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
GTPCLK 1 1 1
BUFIO2_0:IB 0.0.293 0.0.292 0.0.291
BUFIO2_1:IB 0.0.341 0.0.340 0.0.339
BUFIO2_2:IB 0.0.197 0.0.196 0.0.195
BUFIO2_3:IB 0.0.245 0.0.244 0.0.243
BUFIO2_4:IB 0.0.101 0.0.100 0.0.99
BUFIO2_5:IB 0.0.149 0.0.148 0.0.147
BUFIO2_6:IB 0.0.5 0.0.4 0.0.3
BUFIO2_7:IB 0.0.53 0.0.52 0.0.51
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFIO2_0:NEG_EDGE 0.0.301 0.0.300
BUFIO2_1:NEG_EDGE 0.0.349 0.0.348
BUFIO2_2:NEG_EDGE 0.0.205 0.0.204
BUFIO2_3:NEG_EDGE 0.0.253 0.0.252
BUFIO2_4:NEG_EDGE 0.0.109 0.0.108
BUFIO2_5:NEG_EDGE 0.0.157 0.0.156
BUFIO2_6:NEG_EDGE 0.0.13 0.0.12
BUFIO2_7:NEG_EDGE 0.0.61 0.0.60
DIVIDE_1 0 0
DIVIDE_3 0 0
DIVIDE_4 0 0
NEG_EDGE_1 0 0
NEG_EDGE_4 0 0
NEG_EDGE_5 0 0
NEG_EDGE_6 0 0
NEG_EDGE_7 0 0
NEG_EDGE_8 0 0
DIVIDE_2 0 1
DIVIDE_5 0 1
DIVIDE_6 0 1
NEG_EDGE_2 0 1
DIVIDE_7 1 0
DIVIDE_8 1 0
NEG_EDGE_3 1 0
BUFIO2_0:POS_EDGE 0.0.299 0.0.298 0.0.297
BUFIO2_1:POS_EDGE 0.0.347 0.0.346 0.0.345
BUFIO2_2:POS_EDGE 0.0.203 0.0.202 0.0.201
BUFIO2_3:POS_EDGE 0.0.251 0.0.250 0.0.249
BUFIO2_4:POS_EDGE 0.0.107 0.0.106 0.0.105
BUFIO2_5:POS_EDGE 0.0.155 0.0.154 0.0.153
BUFIO2_6:POS_EDGE 0.0.11 0.0.10 0.0.9
BUFIO2_7:POS_EDGE 0.0.59 0.0.58 0.0.57
DIVIDE_1 0 0 0
POS_EDGE_1 0 0 0
POS_EDGE_3 0 0 0
POS_EDGE_5 0 0 0
DIVIDE_2 0 0 1
POS_EDGE_2 0 0 1
DIVIDE_3 0 1 0
DIVIDE_4 0 1 1
POS_EDGE_4 0 1 1
DIVIDE_5 1 0 0
DIVIDE_6 1 0 1
POS_EDGE_6 1 0 1
DIVIDE_7 1 1 0
POS_EDGE_7 1 1 0
DIVIDE_8 1 1 1
POS_EDGE_8 1 1 1
BUFIO2_1:I 0.0.338 0.0.337 0.0.336
BUFIO2_3:I 0.0.242 0.0.241 0.0.240
CLKPIN0 0 0 0
GTPCLK 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFPLL0:DATA_RATE 0.0.141
BUFPLL1:DATA_RATE 0.0.186
SDR 0
DDR 1
BUFPLL0:DIVIDE 0.0.190 0.0.189 0.0.187 0.0.138 0.0.137 0.0.136
BUFPLL1:DIVIDE 0.0.233 0.0.232 0.0.191 0.0.183 0.0.143 0.0.142
3 0 0 0 0 0 1
2 0 0 1 0 0 0
5 0 1 0 0 1 1
4 0 1 1 0 1 0
7 1 0 0 1 0 1
6 1 0 1 1 0 0
1 1 1 0 1 1 1
8 1 1 1 1 1 0
BUFPLL0:ENABLE_BOTH_SYNC 0.0.286 0.0.280 0.0.234
BUFPLL1:ENABLE_BOTH_SYNC 0.0.329 0.0.282 0.0.237
non-inverted [2] [1] [0]
BUFPLL0:ENABLE_NONE_SYNC 0.0.285 0.0.279
BUFPLL1:ENABLE_NONE_SYNC 0.0.328 0.0.281
non-inverted [1] [0]
BUFPLL_COMMON:PLLIN 0.0.330
CMT 0
GCLK 1
BUFPLL_MCB:LOCK_SRC 0.0.139 0.0.184
LOCK_TO_0 0 1
LOCK_TO_1 1 0

Tile REG_R

Cells: 1 IRIs: 0

Bel BUFIO2_0

spartan6 REG_R bel BUFIO2_0
PinDirectionWires

Bel BUFIO2_1

spartan6 REG_R bel BUFIO2_1
PinDirectionWires

Bel BUFIO2_2

spartan6 REG_R bel BUFIO2_2
PinDirectionWires

Bel BUFIO2_3

spartan6 REG_R bel BUFIO2_3
PinDirectionWires

Bel BUFIO2_4

spartan6 REG_R bel BUFIO2_4
PinDirectionWires

Bel BUFIO2_5

spartan6 REG_R bel BUFIO2_5
PinDirectionWires

Bel BUFIO2_6

spartan6 REG_R bel BUFIO2_6
PinDirectionWires

Bel BUFIO2_7

spartan6 REG_R bel BUFIO2_7
PinDirectionWires

Bel BUFIO2FB_0

spartan6 REG_R bel BUFIO2FB_0
PinDirectionWires

Bel BUFIO2FB_1

spartan6 REG_R bel BUFIO2FB_1
PinDirectionWires

Bel BUFIO2FB_2

spartan6 REG_R bel BUFIO2FB_2
PinDirectionWires

Bel BUFIO2FB_3

spartan6 REG_R bel BUFIO2FB_3
PinDirectionWires

Bel BUFIO2FB_4

spartan6 REG_R bel BUFIO2FB_4
PinDirectionWires

Bel BUFIO2FB_5

spartan6 REG_R bel BUFIO2FB_5
PinDirectionWires

Bel BUFIO2FB_6

spartan6 REG_R bel BUFIO2FB_6
PinDirectionWires

Bel BUFIO2FB_7

spartan6 REG_R bel BUFIO2FB_7
PinDirectionWires

Bel BUFPLL0

spartan6 REG_R bel BUFPLL0
PinDirectionWires

Bel BUFPLL1

spartan6 REG_R bel BUFPLL1
PinDirectionWires

Bel BUFPLL_MCB

spartan6 REG_R bel BUFPLL_MCB
PinDirectionWires

Bel BUFPLL_OUT

spartan6 REG_R bel BUFPLL_OUT
PinDirectionWires
LOCK0outputOUT0
LOCK1outputOUT1

Bel BUFPLL_INS_LR

spartan6 REG_R bel BUFPLL_INS_LR
PinDirectionWires
GCLK0inputIMUX.CLK0
GCLK1inputIMUX.CLK1
PLLIN0_GCLKinputIMUX.CLK0
PLLIN1_GCLKinputIMUX.CLK1

Bel BUFIO2_INS

spartan6 REG_R bel BUFIO2_INS
PinDirectionWires

Bel BUFIO2_CKPIN

spartan6 REG_R bel BUFIO2_CKPIN
PinDirectionWires

Bel BUFPLL_BUF

spartan6 REG_R bel BUFPLL_BUF
PinDirectionWires

Bel TIEOFF_REG

spartan6 REG_R bel TIEOFF_REG
PinDirectionWires

Bel wires

spartan6 REG_R bel wires
WirePins
IMUX.CLK0BUFPLL_INS_LR.GCLK0
IMUX.CLK1BUFPLL_INS_LR.GCLK1
OUT0BUFPLL_OUT.LOCK0
OUT1BUFPLL_OUT.LOCK1
IMUX.CLK0BUFPLL_INS_LR.PLLIN0_GCLK
IMUX.CLK1BUFPLL_INS_LR.PLLIN1_GCLK

Bitstream

spartan6 REG_R bittile 0
BitFrame
0
374 BUFIO2_1:CMT_ENABLE
373 BUFIO2_1:CKPIN[0]
372 BUFIO2_1:IOCLK_ENABLE
371 BUFIO2_1:CKPIN[1]
370 ~BUFIO2_1:FB_DIVIDE_BYPASS[3]
369 ~BUFIO2_1:DIVIDE_BYPASS
368 -
367 BUFIO2_1:FB_ENABLE
366 -
365 ~BUFIO2_1:FB_DIVIDE_BYPASS[2]
364 ~BUFIO2_1:FB_DIVIDE_BYPASS[1]
363 ~BUFIO2_1:FB_DIVIDE_BYPASS[0]
362 -
361 -
360 -
359 -
358 -
357 -
356 BUFIO2_1:ENABLE_2CLK
355 BUFIO2_1:ENABLE
354 BUFIO2_1:R_EDGE
353 BUFIO2_1:DIVIDE[2]
352 BUFIO2_1:DIVIDE[1]
351 BUFIO2_1:DIVIDE[0]
350 -
349 BUFIO2_1:NEG_EDGE[1]
348 BUFIO2_1:NEG_EDGE[0]
347 BUFIO2_1:POS_EDGE[2]
346 BUFIO2_1:POS_EDGE[1]
345 BUFIO2_1:POS_EDGE[0]
344 BUFIO2_1:FB_I[2]
343 BUFIO2_1:FB_I[1]
342 BUFIO2_1:FB_I[0]
341 BUFIO2_1:IB[2]
340 BUFIO2_1:IB[1]
339 BUFIO2_1:IB[0]
338 BUFIO2_1:I[2]
337 BUFIO2_1:I[1]
336 BUFIO2_1:I[0]
335 -
334 -
333 -
332 -
331 -
330 BUFPLL_COMMON:PLLIN[0]
329 BUFPLL1:ENABLE_BOTH_SYNC[2]
328 BUFPLL1:ENABLE_NONE_SYNC[1]
327 -
326 BUFIO2_0:CMT_ENABLE
325 BUFIO2_0:CKPIN[0]
324 BUFIO2_0:IOCLK_ENABLE
323 BUFIO2_0:CKPIN[1]
322 ~BUFIO2_0:FB_DIVIDE_BYPASS[3]
321 ~BUFIO2_0:DIVIDE_BYPASS
320 -
319 BUFIO2_0:FB_ENABLE
318 -
317 ~BUFIO2_0:FB_DIVIDE_BYPASS[2]
316 ~BUFIO2_0:FB_DIVIDE_BYPASS[1]
315 ~BUFIO2_0:FB_DIVIDE_BYPASS[0]
314 -
313 -
312 -
311 -
310 -
309 -
308 BUFIO2_0:ENABLE_2CLK
307 BUFIO2_0:ENABLE
306 BUFIO2_0:R_EDGE
305 BUFIO2_0:DIVIDE[2]
304 BUFIO2_0:DIVIDE[1]
303 BUFIO2_0:DIVIDE[0]
302 -
301 BUFIO2_0:NEG_EDGE[1]
300 BUFIO2_0:NEG_EDGE[0]
299 BUFIO2_0:POS_EDGE[2]
298 BUFIO2_0:POS_EDGE[1]
297 BUFIO2_0:POS_EDGE[0]
296 BUFIO2_0:FB_I[2]
295 BUFIO2_0:FB_I[1]
294 BUFIO2_0:FB_I[0]
293 BUFIO2_0:IB[2]
292 BUFIO2_0:IB[1]
291 BUFIO2_0:IB[0]
290 BUFIO2_0:I[2]
289 BUFIO2_0:I[1]
288 BUFIO2_0:I[0]
287 -
286 BUFPLL0:ENABLE_BOTH_SYNC[2]
285 BUFPLL0:ENABLE_NONE_SYNC[1]
284 -
283 -
282 BUFPLL1:ENABLE_BOTH_SYNC[1]
281 BUFPLL1:ENABLE_NONE_SYNC[0]
280 BUFPLL0:ENABLE_BOTH_SYNC[1]
279 BUFPLL0:ENABLE_NONE_SYNC[0]
278 BUFIO2_3:CMT_ENABLE
277 BUFIO2_3:CKPIN[0]
276 BUFIO2_3:IOCLK_ENABLE
275 BUFIO2_3:CKPIN[1]
274 ~BUFIO2_3:FB_DIVIDE_BYPASS[3]
273 ~BUFIO2_3:DIVIDE_BYPASS
272 -
271 BUFIO2_3:FB_ENABLE
270 -
269 ~BUFIO2_3:FB_DIVIDE_BYPASS[2]
268 ~BUFIO2_3:FB_DIVIDE_BYPASS[1]
267 ~BUFIO2_3:FB_DIVIDE_BYPASS[0]
266 -
265 -
264 -
263 -
262 -
261 -
260 BUFIO2_3:ENABLE_2CLK
259 BUFIO2_3:ENABLE
258 BUFIO2_3:R_EDGE
257 BUFIO2_3:DIVIDE[2]
256 BUFIO2_3:DIVIDE[1]
255 BUFIO2_3:DIVIDE[0]
254 -
253 BUFIO2_3:NEG_EDGE[1]
252 BUFIO2_3:NEG_EDGE[0]
251 BUFIO2_3:POS_EDGE[2]
250 BUFIO2_3:POS_EDGE[1]
249 BUFIO2_3:POS_EDGE[0]
248 BUFIO2_3:FB_I[2]
247 BUFIO2_3:FB_I[1]
246 BUFIO2_3:FB_I[0]
245 BUFIO2_3:IB[2]
244 BUFIO2_3:IB[1]
243 BUFIO2_3:IB[0]
242 BUFIO2_3:I[2]
241 BUFIO2_3:I[1]
240 BUFIO2_3:I[0]
239 -
238 -
237 BUFPLL1:ENABLE_BOTH_SYNC[0]
236 -
235 -
234 BUFPLL0:ENABLE_BOTH_SYNC[0]
233 BUFPLL1:DIVIDE[5]
232 BUFPLL1:DIVIDE[4]
231 -
230 BUFIO2_2:CMT_ENABLE
229 BUFIO2_2:CKPIN[0]
228 BUFIO2_2:IOCLK_ENABLE
227 BUFIO2_2:CKPIN[1]
226 ~BUFIO2_2:FB_DIVIDE_BYPASS[3]
225 ~BUFIO2_2:DIVIDE_BYPASS
224 -
223 BUFIO2_2:FB_ENABLE
222 -
221 ~BUFIO2_2:FB_DIVIDE_BYPASS[2]
220 ~BUFIO2_2:FB_DIVIDE_BYPASS[1]
219 ~BUFIO2_2:FB_DIVIDE_BYPASS[0]
218 -
217 -
216 -
215 -
214 -
213 -
212 BUFIO2_2:ENABLE_2CLK
211 BUFIO2_2:ENABLE
210 BUFIO2_2:R_EDGE
209 BUFIO2_2:DIVIDE[2]
208 BUFIO2_2:DIVIDE[1]
207 BUFIO2_2:DIVIDE[0]
206 -
205 BUFIO2_2:NEG_EDGE[1]
204 BUFIO2_2:NEG_EDGE[0]
203 BUFIO2_2:POS_EDGE[2]
202 BUFIO2_2:POS_EDGE[1]
201 BUFIO2_2:POS_EDGE[0]
200 BUFIO2_2:FB_I[2]
199 BUFIO2_2:FB_I[1]
198 BUFIO2_2:FB_I[0]
197 BUFIO2_2:IB[2]
196 BUFIO2_2:IB[1]
195 BUFIO2_2:IB[0]
194 BUFIO2_2:I[2]
193 BUFIO2_2:I[1]
192 BUFIO2_2:I[0]
191 BUFPLL1:DIVIDE[3]
190 BUFPLL0:DIVIDE[5]
189 BUFPLL0:DIVIDE[4]
188 -
187 BUFPLL0:DIVIDE[3]
186 BUFPLL1:DATA_RATE[0]
185 ~BUFPLL1:ENABLE_SYNC
184 BUFPLL_MCB:LOCK_SRC[0]
183 BUFPLL1:DIVIDE[2]
182 BUFIO2_5:CMT_ENABLE
181 BUFIO2_5:CKPIN[0]
180 BUFIO2_5:IOCLK_ENABLE
179 BUFIO2_5:CKPIN[1]
178 ~BUFIO2_5:FB_DIVIDE_BYPASS[3]
177 ~BUFIO2_5:DIVIDE_BYPASS
176 -
175 BUFIO2_5:FB_ENABLE
174 -
173 ~BUFIO2_5:FB_DIVIDE_BYPASS[2]
172 ~BUFIO2_5:FB_DIVIDE_BYPASS[1]
171 ~BUFIO2_5:FB_DIVIDE_BYPASS[0]
170 -
169 -
168 -
167 -
166 -
165 -
164 BUFIO2_5:ENABLE_2CLK
163 BUFIO2_5:ENABLE
162 BUFIO2_5:R_EDGE
161 BUFIO2_5:DIVIDE[2]
160 BUFIO2_5:DIVIDE[1]
159 BUFIO2_5:DIVIDE[0]
158 -
157 BUFIO2_5:NEG_EDGE[1]
156 BUFIO2_5:NEG_EDGE[0]
155 BUFIO2_5:POS_EDGE[2]
154 BUFIO2_5:POS_EDGE[1]
153 BUFIO2_5:POS_EDGE[0]
152 BUFIO2_5:FB_I[2]
151 BUFIO2_5:FB_I[1]
150 BUFIO2_5:FB_I[0]
149 BUFIO2_5:IB[2]
148 BUFIO2_5:IB[1]
147 BUFIO2_5:IB[0]
146 BUFIO2_5:I[2]
145 BUFIO2_5:I[1]
144 BUFIO2_5:I[0]
143 BUFPLL1:DIVIDE[1]
142 BUFPLL1:DIVIDE[0]
141 BUFPLL0:DATA_RATE[0]
140 ~BUFPLL0:ENABLE_SYNC
139 BUFPLL_MCB:LOCK_SRC[1]
138 BUFPLL0:DIVIDE[2]
137 BUFPLL0:DIVIDE[1]
136 BUFPLL0:DIVIDE[0]
135 BUFPLL_COMMON:ENABLE
134 BUFIO2_4:CMT_ENABLE
133 BUFIO2_4:CKPIN[0]
132 BUFIO2_4:IOCLK_ENABLE
131 BUFIO2_4:CKPIN[1]
130 ~BUFIO2_4:FB_DIVIDE_BYPASS[3]
129 ~BUFIO2_4:DIVIDE_BYPASS
128 -
127 BUFIO2_4:FB_ENABLE
126 -
125 ~BUFIO2_4:FB_DIVIDE_BYPASS[2]
124 ~BUFIO2_4:FB_DIVIDE_BYPASS[1]
123 ~BUFIO2_4:FB_DIVIDE_BYPASS[0]
122 -
121 -
120 -
119 -
118 -
117 -
116 BUFIO2_4:ENABLE_2CLK
115 BUFIO2_4:ENABLE
114 BUFIO2_4:R_EDGE
113 BUFIO2_4:DIVIDE[2]
112 BUFIO2_4:DIVIDE[1]
111 BUFIO2_4:DIVIDE[0]
110 -
109 BUFIO2_4:NEG_EDGE[1]
108 BUFIO2_4:NEG_EDGE[0]
107 BUFIO2_4:POS_EDGE[2]
106 BUFIO2_4:POS_EDGE[1]
105 BUFIO2_4:POS_EDGE[0]
104 BUFIO2_4:FB_I[2]
103 BUFIO2_4:FB_I[1]
102 BUFIO2_4:FB_I[0]
101 BUFIO2_4:IB[2]
100 BUFIO2_4:IB[1]
99 BUFIO2_4:IB[0]
98 BUFIO2_4:I[2]
97 BUFIO2_4:I[1]
96 BUFIO2_4:I[0]
95 -
94 -
93 -
92 -
91 -
90 -
89 -
88 -
87 -
86 BUFIO2_7:CMT_ENABLE
85 BUFIO2_7:CKPIN[0]
84 BUFIO2_7:IOCLK_ENABLE
83 BUFIO2_7:CKPIN[1]
82 ~BUFIO2_7:FB_DIVIDE_BYPASS[3]
81 ~BUFIO2_7:DIVIDE_BYPASS
80 -
79 BUFIO2_7:FB_ENABLE
78 -
77 ~BUFIO2_7:FB_DIVIDE_BYPASS[2]
76 ~BUFIO2_7:FB_DIVIDE_BYPASS[1]
75 ~BUFIO2_7:FB_DIVIDE_BYPASS[0]
74 -
73 -
72 -
71 -
70 -
69 -
68 BUFIO2_7:ENABLE_2CLK
67 BUFIO2_7:ENABLE
66 BUFIO2_7:R_EDGE
65 BUFIO2_7:DIVIDE[2]
64 BUFIO2_7:DIVIDE[1]
63 BUFIO2_7:DIVIDE[0]
62 -
61 BUFIO2_7:NEG_EDGE[1]
60 BUFIO2_7:NEG_EDGE[0]
59 BUFIO2_7:POS_EDGE[2]
58 BUFIO2_7:POS_EDGE[1]
57 BUFIO2_7:POS_EDGE[0]
56 BUFIO2_7:FB_I[2]
55 BUFIO2_7:FB_I[1]
54 BUFIO2_7:FB_I[0]
53 BUFIO2_7:IB[2]
52 BUFIO2_7:IB[1]
51 BUFIO2_7:IB[0]
50 BUFIO2_7:I[2]
49 BUFIO2_7:I[1]
48 BUFIO2_7:I[0]
47 -
46 -
45 -
44 -
43 -
42 -
41 -
40 -
39 -
38 BUFIO2_6:CMT_ENABLE
37 BUFIO2_6:CKPIN[0]
36 BUFIO2_6:IOCLK_ENABLE
35 BUFIO2_6:CKPIN[1]
34 ~BUFIO2_6:FB_DIVIDE_BYPASS[3]
33 ~BUFIO2_6:DIVIDE_BYPASS
32 -
31 BUFIO2_6:FB_ENABLE
30 -
29 ~BUFIO2_6:FB_DIVIDE_BYPASS[2]
28 ~BUFIO2_6:FB_DIVIDE_BYPASS[1]
27 ~BUFIO2_6:FB_DIVIDE_BYPASS[0]
26 -
25 -
24 -
23 -
22 -
21 -
20 BUFIO2_6:ENABLE_2CLK
19 BUFIO2_6:ENABLE
18 BUFIO2_6:R_EDGE
17 BUFIO2_6:DIVIDE[2]
16 BUFIO2_6:DIVIDE[1]
15 BUFIO2_6:DIVIDE[0]
14 -
13 BUFIO2_6:NEG_EDGE[1]
12 BUFIO2_6:NEG_EDGE[0]
11 BUFIO2_6:POS_EDGE[2]
10 BUFIO2_6:POS_EDGE[1]
9 BUFIO2_6:POS_EDGE[0]
8 BUFIO2_6:FB_I[2]
7 BUFIO2_6:FB_I[1]
6 BUFIO2_6:FB_I[0]
5 BUFIO2_6:IB[2]
4 BUFIO2_6:IB[1]
3 BUFIO2_6:IB[0]
2 BUFIO2_6:I[2]
1 BUFIO2_6:I[1]
0 BUFIO2_6:I[0]
BUFIO2_0:CKPIN 0.0.323 0.0.325
BUFIO2_1:CKPIN 0.0.371 0.0.373
BUFIO2_2:CKPIN 0.0.227 0.0.229
BUFIO2_3:CKPIN 0.0.275 0.0.277
BUFIO2_4:CKPIN 0.0.131 0.0.133
BUFIO2_5:CKPIN 0.0.179 0.0.181
BUFIO2_6:CKPIN 0.0.35 0.0.37
BUFIO2_7:CKPIN 0.0.83 0.0.85
VCC 0 0
CLKPIN 0 1
DIVCLK 1 1
BUFIO2_0:CMT_ENABLE 0.0.326
BUFIO2_0:ENABLE 0.0.307
BUFIO2_0:ENABLE_2CLK 0.0.308
BUFIO2_0:FB_ENABLE 0.0.319
BUFIO2_0:IOCLK_ENABLE 0.0.324
BUFIO2_0:R_EDGE 0.0.306
BUFIO2_1:CMT_ENABLE 0.0.374
BUFIO2_1:ENABLE 0.0.355
BUFIO2_1:ENABLE_2CLK 0.0.356
BUFIO2_1:FB_ENABLE 0.0.367
BUFIO2_1:IOCLK_ENABLE 0.0.372
BUFIO2_1:R_EDGE 0.0.354
BUFIO2_2:CMT_ENABLE 0.0.230
BUFIO2_2:ENABLE 0.0.211
BUFIO2_2:ENABLE_2CLK 0.0.212
BUFIO2_2:FB_ENABLE 0.0.223
BUFIO2_2:IOCLK_ENABLE 0.0.228
BUFIO2_2:R_EDGE 0.0.210
BUFIO2_3:CMT_ENABLE 0.0.278
BUFIO2_3:ENABLE 0.0.259
BUFIO2_3:ENABLE_2CLK 0.0.260
BUFIO2_3:FB_ENABLE 0.0.271
BUFIO2_3:IOCLK_ENABLE 0.0.276
BUFIO2_3:R_EDGE 0.0.258
BUFIO2_4:CMT_ENABLE 0.0.134
BUFIO2_4:ENABLE 0.0.115
BUFIO2_4:ENABLE_2CLK 0.0.116
BUFIO2_4:FB_ENABLE 0.0.127
BUFIO2_4:IOCLK_ENABLE 0.0.132
BUFIO2_4:R_EDGE 0.0.114
BUFIO2_5:CMT_ENABLE 0.0.182
BUFIO2_5:ENABLE 0.0.163
BUFIO2_5:ENABLE_2CLK 0.0.164
BUFIO2_5:FB_ENABLE 0.0.175
BUFIO2_5:IOCLK_ENABLE 0.0.180
BUFIO2_5:R_EDGE 0.0.162
BUFIO2_6:CMT_ENABLE 0.0.38
BUFIO2_6:ENABLE 0.0.19
BUFIO2_6:ENABLE_2CLK 0.0.20
BUFIO2_6:FB_ENABLE 0.0.31
BUFIO2_6:IOCLK_ENABLE 0.0.36
BUFIO2_6:R_EDGE 0.0.18
BUFIO2_7:CMT_ENABLE 0.0.86
BUFIO2_7:ENABLE 0.0.67
BUFIO2_7:ENABLE_2CLK 0.0.68
BUFIO2_7:FB_ENABLE 0.0.79
BUFIO2_7:IOCLK_ENABLE 0.0.84
BUFIO2_7:R_EDGE 0.0.66
BUFPLL_COMMON:ENABLE 0.0.135
non-inverted [0]
BUFIO2_0:DIVIDE 0.0.305 0.0.304 0.0.303
BUFIO2_1:DIVIDE 0.0.353 0.0.352 0.0.351
BUFIO2_2:DIVIDE 0.0.209 0.0.208 0.0.207
BUFIO2_3:DIVIDE 0.0.257 0.0.256 0.0.255
BUFIO2_4:DIVIDE 0.0.113 0.0.112 0.0.111
BUFIO2_5:DIVIDE 0.0.161 0.0.160 0.0.159
BUFIO2_6:DIVIDE 0.0.17 0.0.16 0.0.15
BUFIO2_7:DIVIDE 0.0.65 0.0.64 0.0.63
2 0 0 0
3 0 0 1
4 0 1 0
5 0 1 1
6 1 0 0
7 1 0 1
8 1 1 0
1 1 1 1
BUFIO2_0:DIVIDE_BYPASS 0.0.321
BUFIO2_1:DIVIDE_BYPASS 0.0.369
BUFIO2_2:DIVIDE_BYPASS 0.0.225
BUFIO2_3:DIVIDE_BYPASS 0.0.273
BUFIO2_4:DIVIDE_BYPASS 0.0.129
BUFIO2_5:DIVIDE_BYPASS 0.0.177
BUFIO2_6:DIVIDE_BYPASS 0.0.33
BUFIO2_7:DIVIDE_BYPASS 0.0.81
BUFPLL0:ENABLE_SYNC 0.0.140
BUFPLL1:ENABLE_SYNC 0.0.185
inverted ~[0]
BUFIO2_0:FB_DIVIDE_BYPASS 0.0.322 0.0.317 0.0.316 0.0.315
BUFIO2_1:FB_DIVIDE_BYPASS 0.0.370 0.0.365 0.0.364 0.0.363
BUFIO2_2:FB_DIVIDE_BYPASS 0.0.226 0.0.221 0.0.220 0.0.219
BUFIO2_3:FB_DIVIDE_BYPASS 0.0.274 0.0.269 0.0.268 0.0.267
BUFIO2_4:FB_DIVIDE_BYPASS 0.0.130 0.0.125 0.0.124 0.0.123
BUFIO2_5:FB_DIVIDE_BYPASS 0.0.178 0.0.173 0.0.172 0.0.171
BUFIO2_6:FB_DIVIDE_BYPASS 0.0.34 0.0.29 0.0.28 0.0.27
BUFIO2_7:FB_DIVIDE_BYPASS 0.0.82 0.0.77 0.0.76 0.0.75
inverted ~[3] ~[2] ~[1] ~[0]
BUFIO2_0:FB_I 0.0.296 0.0.295 0.0.294
BUFIO2_1:FB_I 0.0.344 0.0.343 0.0.342
BUFIO2_2:FB_I 0.0.200 0.0.199 0.0.198
BUFIO2_3:FB_I 0.0.248 0.0.247 0.0.246
BUFIO2_4:FB_I 0.0.104 0.0.103 0.0.102
BUFIO2_5:FB_I 0.0.152 0.0.151 0.0.150
BUFIO2_6:FB_I 0.0.8 0.0.7 0.0.6
BUFIO2_7:FB_I 0.0.56 0.0.55 0.0.54
CLKPIN 0 0 0
DFB 0 0 1
CFB 0 1 0
CFB_INVERT 0 1 1
GTPFB 1 1 1
BUFIO2_0:I 0.0.290 0.0.289 0.0.288
BUFIO2_2:I 0.0.194 0.0.193 0.0.192
BUFIO2_4:I 0.0.98 0.0.97 0.0.96
BUFIO2_5:I 0.0.146 0.0.145 0.0.144
BUFIO2_6:I 0.0.2 0.0.1 0.0.0
BUFIO2_7:I 0.0.50 0.0.49 0.0.48
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
GTPCLK 1 1 1
BUFIO2_0:IB 0.0.293 0.0.292 0.0.291
BUFIO2_1:IB 0.0.341 0.0.340 0.0.339
BUFIO2_2:IB 0.0.197 0.0.196 0.0.195
BUFIO2_3:IB 0.0.245 0.0.244 0.0.243
BUFIO2_4:IB 0.0.101 0.0.100 0.0.99
BUFIO2_5:IB 0.0.149 0.0.148 0.0.147
BUFIO2_6:IB 0.0.5 0.0.4 0.0.3
BUFIO2_7:IB 0.0.53 0.0.52 0.0.51
CLKPIN0 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFIO2_0:NEG_EDGE 0.0.301 0.0.300
BUFIO2_1:NEG_EDGE 0.0.349 0.0.348
BUFIO2_2:NEG_EDGE 0.0.205 0.0.204
BUFIO2_3:NEG_EDGE 0.0.253 0.0.252
BUFIO2_4:NEG_EDGE 0.0.109 0.0.108
BUFIO2_5:NEG_EDGE 0.0.157 0.0.156
BUFIO2_6:NEG_EDGE 0.0.13 0.0.12
BUFIO2_7:NEG_EDGE 0.0.61 0.0.60
DIVIDE_1 0 0
DIVIDE_3 0 0
DIVIDE_4 0 0
NEG_EDGE_1 0 0
NEG_EDGE_4 0 0
NEG_EDGE_5 0 0
NEG_EDGE_6 0 0
NEG_EDGE_7 0 0
NEG_EDGE_8 0 0
DIVIDE_2 0 1
DIVIDE_5 0 1
DIVIDE_6 0 1
NEG_EDGE_2 0 1
DIVIDE_7 1 0
DIVIDE_8 1 0
NEG_EDGE_3 1 0
BUFIO2_0:POS_EDGE 0.0.299 0.0.298 0.0.297
BUFIO2_1:POS_EDGE 0.0.347 0.0.346 0.0.345
BUFIO2_2:POS_EDGE 0.0.203 0.0.202 0.0.201
BUFIO2_3:POS_EDGE 0.0.251 0.0.250 0.0.249
BUFIO2_4:POS_EDGE 0.0.107 0.0.106 0.0.105
BUFIO2_5:POS_EDGE 0.0.155 0.0.154 0.0.153
BUFIO2_6:POS_EDGE 0.0.11 0.0.10 0.0.9
BUFIO2_7:POS_EDGE 0.0.59 0.0.58 0.0.57
DIVIDE_1 0 0 0
POS_EDGE_1 0 0 0
POS_EDGE_3 0 0 0
POS_EDGE_5 0 0 0
DIVIDE_2 0 0 1
POS_EDGE_2 0 0 1
DIVIDE_3 0 1 0
DIVIDE_4 0 1 1
POS_EDGE_4 0 1 1
DIVIDE_5 1 0 0
DIVIDE_6 1 0 1
POS_EDGE_6 1 0 1
DIVIDE_7 1 1 0
POS_EDGE_7 1 1 0
DIVIDE_8 1 1 1
POS_EDGE_8 1 1 1
BUFIO2_1:I 0.0.338 0.0.337 0.0.336
BUFIO2_3:I 0.0.242 0.0.241 0.0.240
CLKPIN0 0 0 0
GTPCLK 0 0 0
CLKPIN1 0 0 1
DFB 0 1 0
DQS0 0 1 1
CLKPIN4 1 0 0
CLKPIN5 1 0 1
DQS2 1 1 0
BUFPLL0:DATA_RATE 0.0.141
BUFPLL1:DATA_RATE 0.0.186
SDR 0
DDR 1
BUFPLL0:DIVIDE 0.0.190 0.0.189 0.0.187 0.0.138 0.0.137 0.0.136
BUFPLL1:DIVIDE 0.0.233 0.0.232 0.0.191 0.0.183 0.0.143 0.0.142
3 0 0 0 0 0 1
2 0 0 1 0 0 0
5 0 1 0 0 1 1
4 0 1 1 0 1 0
7 1 0 0 1 0 1
6 1 0 1 1 0 0
1 1 1 0 1 1 1
8 1 1 1 1 1 0
BUFPLL0:ENABLE_BOTH_SYNC 0.0.286 0.0.280 0.0.234
BUFPLL1:ENABLE_BOTH_SYNC 0.0.329 0.0.282 0.0.237
non-inverted [2] [1] [0]
BUFPLL0:ENABLE_NONE_SYNC 0.0.285 0.0.279
BUFPLL1:ENABLE_NONE_SYNC 0.0.328 0.0.281
non-inverted [1] [0]
BUFPLL_COMMON:PLLIN 0.0.330
CMT 0
GCLK 1
BUFPLL_MCB:LOCK_SRC 0.0.139 0.0.184
LOCK_TO_0 0 1
LOCK_TO_1 1 0