I/O clock buffers

Tile CLK_S

Cells: 4

Switchbox CLK_INT

spartan6 CLK_S switchbox CLK_INT muxes IMUX_CLK_GCLK[0]
Bits								Destination
MAIN[0][90]	MAIN[0][91]	MAIN[0][92]	MAIN[0][93]	MAIN[0][47]	MAIN[0][87]	MAIN[0][88]	MAIN[0][89]	CELL[1].IMUX_CLK_GCLK[0]
								Source
0	0	0	0	0	0	0	0	off
0	1	0	1	0	0	0	1	CELL[2].HCLK[0]
0	1	0	1	0	0	1	0	CELL[2].HCLK[1]
0	1	0	1	0	1	0	0	CELL[2].HCLK[2]
0	1	0	1	1	0	0	0	CELL[2].HCLK[3]
0	1	1	0	0	0	0	1	CELL[2].HCLK[8]
0	1	1	0	0	0	1	0	CELL[2].HCLK[9]
0	1	1	0	0	1	0	0	CELL[2].HCLK[10]
0	1	1	0	1	0	0	0	CELL[2].HCLK[11]
1	0	0	1	0	0	0	1	CELL[2].HCLK[4]
1	0	0	1	0	0	1	0	CELL[2].HCLK[5]
1	0	0	1	0	1	0	0	CELL[2].HCLK[6]
1	0	0	1	1	0	0	0	CELL[2].HCLK[7]
1	0	1	0	0	0	0	1	CELL[2].HCLK[12]
1	0	1	0	0	0	1	0	CELL[2].HCLK[13]
1	0	1	0	0	1	0	0	CELL[2].HCLK[14]
1	0	1	0	1	0	0	0	CELL[2].HCLK[15]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_CLK_GCLK[1]
Bits								Destination
MAIN[0][42]	MAIN[0][41]	MAIN[0][40]	MAIN[0][39]	MAIN[0][46]	MAIN[0][45]	MAIN[0][44]	MAIN[0][43]	CELL[1].IMUX_CLK_GCLK[1]
								Source
0	0	0	0	0	0	0	0	off
0	1	0	1	0	0	0	1	CELL[2].HCLK[0]
0	1	0	1	0	0	1	0	CELL[2].HCLK[1]
0	1	0	1	0	1	0	0	CELL[2].HCLK[2]
0	1	0	1	1	0	0	0	CELL[2].HCLK[3]
0	1	1	0	0	0	0	1	CELL[2].HCLK[8]
0	1	1	0	0	0	1	0	CELL[2].HCLK[9]
0	1	1	0	0	1	0	0	CELL[2].HCLK[10]
0	1	1	0	1	0	0	0	CELL[2].HCLK[11]
1	0	0	1	0	0	0	1	CELL[2].HCLK[4]
1	0	0	1	0	0	1	0	CELL[2].HCLK[5]
1	0	0	1	0	1	0	0	CELL[2].HCLK[6]
1	0	0	1	1	0	0	0	CELL[2].HCLK[7]
1	0	1	0	0	0	0	1	CELL[2].HCLK[12]
1	0	1	0	0	0	1	0	CELL[2].HCLK[13]
1	0	1	0	0	1	0	0	CELL[2].HCLK[14]
1	0	1	0	1	0	0	0	CELL[2].HCLK[15]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_I[0]
Bits			Destination
MAIN[0][98]	MAIN[0][97]	MAIN[0][96]	CELL[1].IMUX_BUFIO2_I[0]	-
MAIN[0][290]	MAIN[0][289]	MAIN[0][288]	-	CELL[3].IMUX_BUFIO2_I[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[3].OUT_CLKPAD_DQSP
1	0	0	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[3].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[0]	CELL[3].GTPCLK[0]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_I[1]
Bits			Destination
MAIN[0][146]	MAIN[0][145]	MAIN[0][144]	CELL[1].IMUX_BUFIO2_I[1]	-
MAIN[0][338]	MAIN[0][337]	MAIN[0][336]	-	CELL[3].IMUX_BUFIO2_I[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[3].OUT_CLKPAD_DQSN
1	0	0	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[3].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[1]	CELL[3].GTPCLK[1]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_I[2]
Bits			Destination
MAIN[0][2]	MAIN[0][1]	MAIN[0][0]	CELL[1].IMUX_BUFIO2_I[2]	-
MAIN[0][194]	MAIN[0][193]	MAIN[0][192]	-	CELL[3].IMUX_BUFIO2_I[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[2].OUT_CLKPAD_DQSP
1	0	0	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[2].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[2]	CELL[3].GTPCLK[2]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_I[3]
Bits			Destination
MAIN[0][50]	MAIN[0][49]	MAIN[0][48]	CELL[1].IMUX_BUFIO2_I[3]	-
MAIN[0][242]	MAIN[0][241]	MAIN[0][240]	-	CELL[3].IMUX_BUFIO2_I[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[2].OUT_CLKPAD_DQSN
1	0	0	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[2].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[3]	CELL[3].GTPCLK[3]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_IB[0]
Bits			Destination
MAIN[0][101]	MAIN[0][100]	MAIN[0][99]	CELL[1].IMUX_BUFIO2_IB[0]	-
MAIN[0][293]	MAIN[0][292]	MAIN[0][291]	-	CELL[3].IMUX_BUFIO2_IB[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[3].OUT_CLKPAD_DQSN
1	0	0	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[3].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_IB[1]
Bits			Destination
MAIN[0][149]	MAIN[0][148]	MAIN[0][147]	CELL[1].IMUX_BUFIO2_IB[1]	-
MAIN[0][341]	MAIN[0][340]	MAIN[0][339]	-	CELL[3].IMUX_BUFIO2_IB[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[3].OUT_CLKPAD_DQSP
1	0	0	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[3].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_IB[2]
Bits			Destination
MAIN[0][5]	MAIN[0][4]	MAIN[0][3]	CELL[1].IMUX_BUFIO2_IB[2]	-
MAIN[0][197]	MAIN[0][196]	MAIN[0][195]	-	CELL[3].IMUX_BUFIO2_IB[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[2].OUT_CLKPAD_DQSN
1	0	0	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[2].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2_IB[3]
Bits			Destination
MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	CELL[1].IMUX_BUFIO2_IB[3]	-
MAIN[0][245]	MAIN[0][244]	MAIN[0][243]	-	CELL[3].IMUX_BUFIO2_IB[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[2].OUT_CLKPAD_DQSP
1	0	0	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[2].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2FB[0]
Bits			Destination
MAIN[0][104]	MAIN[0][103]	MAIN[0][102]	CELL[1].IMUX_BUFIO2FB[0]	-
MAIN[0][296]	MAIN[0][295]	MAIN[0][294]	-	CELL[3].IMUX_BUFIO2FB[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[1]	CELL[3].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[1]	CELL[3].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[0]	CELL[3].GTPFB[0]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2FB[1]
Bits			Destination
MAIN[0][152]	MAIN[0][151]	MAIN[0][150]	CELL[1].IMUX_BUFIO2FB[1]	-
MAIN[0][344]	MAIN[0][343]	MAIN[0][342]	-	CELL[3].IMUX_BUFIO2FB[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[0]	CELL[3].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[0]	CELL[3].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[1]	CELL[3].GTPFB[1]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2FB[2]
Bits			Destination
MAIN[0][8]	MAIN[0][7]	MAIN[0][6]	CELL[1].IMUX_BUFIO2FB[2]	-
MAIN[0][200]	MAIN[0][199]	MAIN[0][198]	-	CELL[3].IMUX_BUFIO2FB[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[1]	CELL[2].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[1]	CELL[2].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[2]	CELL[3].GTPFB[2]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFIO2FB[3]
Bits			Destination
MAIN[0][56]	MAIN[0][55]	MAIN[0][54]	CELL[1].IMUX_BUFIO2FB[3]	-
MAIN[0][248]	MAIN[0][247]	MAIN[0][246]	-	CELL[3].IMUX_BUFIO2FB[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[0]	CELL[2].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[0]	CELL[2].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[3]	CELL[3].GTPFB[3]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[0]
Bits		Destination
MAIN[0][323]	MAIN[0][325]	CELL[1].DIVCLK_CLKC[0]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[3].OUT_CLKPAD_I[1]
1	1	CELL[3].OUT_DIVCLK[0]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[1]
Bits		Destination
MAIN[0][371]	MAIN[0][373]	CELL[1].DIVCLK_CLKC[1]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[3].OUT_CLKPAD_I[0]
1	1	CELL[3].OUT_DIVCLK[1]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[2]
Bits		Destination
MAIN[0][227]	MAIN[0][229]	CELL[1].DIVCLK_CLKC[2]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[2].OUT_CLKPAD_I[1]
1	1	CELL[3].OUT_DIVCLK[2]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[3]
Bits		Destination
MAIN[0][275]	MAIN[0][277]	CELL[1].DIVCLK_CLKC[3]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[2].OUT_CLKPAD_I[0]
1	1	CELL[3].OUT_DIVCLK[3]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[4]
Bits		Destination
MAIN[0][131]	MAIN[0][133]	CELL[1].DIVCLK_CLKC[4]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[0]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[5]
Bits		Destination
MAIN[0][179]	MAIN[0][181]	CELL[1].DIVCLK_CLKC[5]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[1]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[6]
Bits		Destination
MAIN[0][35]	MAIN[0][37]	CELL[1].DIVCLK_CLKC[6]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[2]

spartan6 CLK_S switchbox CLK_INT muxes DIVCLK_CLKC[7]
Bits		Destination
MAIN[0][83]	MAIN[0][85]	CELL[1].DIVCLK_CLKC[7]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[3]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFPLL_PLLIN[0]
Bits			Destination
MAIN[0][332]	MAIN[0][331]	MAIN[0][330]	CELL[1].IMUX_BUFPLL_PLLIN[0]
			Source
0	0	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[0]
0	0	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[1]
0	1	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[2]
0	1	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[3]
1	0	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[4]
1	0	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[5]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFPLL_PLLIN[1]
Bits			Destination
MAIN[0][335]	MAIN[0][334]	MAIN[0][333]	CELL[1].IMUX_BUFPLL_PLLIN[1]
			Source
0	0	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[0]
0	0	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[1]
0	1	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[2]
0	1	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[3]
1	0	0	CELL[1].CMT_BUFPLL_V_CLKOUT_N[4]
1	0	1	CELL[1].CMT_BUFPLL_V_CLKOUT_N[5]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFPLL_LOCKED[0]
Bits		Destination
MAIN[0][376]	MAIN[0][375]	CELL[1].IMUX_BUFPLL_LOCKED[0]
		Source
0	0	CELL[1].CMT_BUFPLL_V_LOCKED_N[0]
0	1	CELL[1].CMT_BUFPLL_V_LOCKED_N[1]
1	0	CELL[1].CMT_BUFPLL_V_LOCKED_N[2]

spartan6 CLK_S switchbox CLK_INT muxes IMUX_BUFPLL_LOCKED[1]
Bits		Destination
MAIN[0][378]	MAIN[0][377]	CELL[1].IMUX_BUFPLL_LOCKED[1]
		Source
0	0	CELL[1].CMT_BUFPLL_V_LOCKED_N[0]
0	1	CELL[1].CMT_BUFPLL_V_LOCKED_N[1]
1	0	CELL[1].CMT_BUFPLL_V_LOCKED_N[2]

Bels BUFIO2

spartan6 CLK_S bel BUFIO2 pins
Pin	Direction	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
I	in	CELL[3].IMUX_BUFIO2_I[0]	CELL[3].IMUX_BUFIO2_I[1]	CELL[3].IMUX_BUFIO2_I[2]	CELL[3].IMUX_BUFIO2_I[3]	CELL[1].IMUX_BUFIO2_I[0]	CELL[1].IMUX_BUFIO2_I[1]	CELL[1].IMUX_BUFIO2_I[2]	CELL[1].IMUX_BUFIO2_I[3]
IB	in	CELL[3].IMUX_BUFIO2_IB[0]	CELL[3].IMUX_BUFIO2_IB[1]	CELL[3].IMUX_BUFIO2_IB[2]	CELL[3].IMUX_BUFIO2_IB[3]	CELL[1].IMUX_BUFIO2_IB[0]	CELL[1].IMUX_BUFIO2_IB[1]	CELL[1].IMUX_BUFIO2_IB[2]	CELL[1].IMUX_BUFIO2_IB[3]
DIVCLK	out	CELL[3].OUT_DIVCLK[0]	CELL[3].OUT_DIVCLK[1]	CELL[3].OUT_DIVCLK[2]	CELL[3].OUT_DIVCLK[3]	CELL[1].OUT_DIVCLK[0]	CELL[1].OUT_DIVCLK[1]	CELL[1].OUT_DIVCLK[2]	CELL[1].OUT_DIVCLK[3]
DIVCLK_CMT	out	CELL[1].DIVCLK_CMT_V[0]	CELL[1].DIVCLK_CMT_V[1]	CELL[1].DIVCLK_CMT_V[2]	CELL[1].DIVCLK_CMT_V[3]	CELL[1].DIVCLK_CMT_V[4]	CELL[1].DIVCLK_CMT_V[5]	CELL[1].DIVCLK_CMT_V[6]	CELL[1].DIVCLK_CMT_V[7]
IOCLK	out	CELL[3].IOCLK[0]	CELL[3].IOCLK[1]	CELL[3].IOCLK[2]	CELL[3].IOCLK[3]	CELL[1].IOCLK[0]	CELL[1].IOCLK[1]	CELL[1].IOCLK[2]	CELL[1].IOCLK[3]
SERDESSTROBE	out	CELL[3].IOCE[0]	CELL[3].IOCE[1]	CELL[3].IOCE[2]	CELL[3].IOCE[3]	CELL[1].IOCE[0]	CELL[1].IOCE[1]	CELL[1].IOCE[2]	CELL[1].IOCE[3]

spartan6 CLK_S bel BUFIO2 attribute bits
Attribute	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
ENABLE	MAIN[0][307]	MAIN[0][355]	MAIN[0][211]	MAIN[0][259]	MAIN[0][115]	MAIN[0][163]	MAIN[0][19]	MAIN[0][67]
ENABLE_2CLK	MAIN[0][308]	MAIN[0][356]	MAIN[0][212]	MAIN[0][260]	MAIN[0][116]	MAIN[0][164]	MAIN[0][20]	MAIN[0][68]
CMT_ENABLE	MAIN[0][326]	MAIN[0][374]	MAIN[0][230]	MAIN[0][278]	MAIN[0][134]	MAIN[0][182]	MAIN[0][38]	MAIN[0][86]
IOCLK_ENABLE	MAIN[0][324]	MAIN[0][372]	MAIN[0][228]	MAIN[0][276]	MAIN[0][132]	MAIN[0][180]	MAIN[0][36]	MAIN[0][84]
DIVIDE	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]
DIVIDE_BYPASS	!MAIN[0][321]	!MAIN[0][369]	!MAIN[0][225]	!MAIN[0][273]	!MAIN[0][129]	!MAIN[0][177]	!MAIN[0][33]	!MAIN[0][81]
R_EDGE	MAIN[0][306]	MAIN[0][354]	MAIN[0][210]	MAIN[0][258]	MAIN[0][114]	MAIN[0][162]	MAIN[0][18]	MAIN[0][66]
POS_EDGE bit 0	MAIN[0][297]	MAIN[0][345]	MAIN[0][201]	MAIN[0][249]	MAIN[0][105]	MAIN[0][153]	MAIN[0][9]	MAIN[0][57]
POS_EDGE bit 1	MAIN[0][298]	MAIN[0][346]	MAIN[0][202]	MAIN[0][250]	MAIN[0][106]	MAIN[0][154]	MAIN[0][10]	MAIN[0][58]
POS_EDGE bit 2	MAIN[0][299]	MAIN[0][347]	MAIN[0][203]	MAIN[0][251]	MAIN[0][107]	MAIN[0][155]	MAIN[0][11]	MAIN[0][59]
NEG_EDGE bit 0	MAIN[0][300]	MAIN[0][348]	MAIN[0][204]	MAIN[0][252]	MAIN[0][108]	MAIN[0][156]	MAIN[0][12]	MAIN[0][60]
NEG_EDGE bit 1	MAIN[0][301]	MAIN[0][349]	MAIN[0][205]	MAIN[0][253]	MAIN[0][109]	MAIN[0][157]	MAIN[0][13]	MAIN[0][61]

spartan6 CLK_S enum BUFIO2_DIVIDE
BUFIO2[0].DIVIDE	MAIN[0][305]	MAIN[0][304]	MAIN[0][303]
BUFIO2[1].DIVIDE	MAIN[0][353]	MAIN[0][352]	MAIN[0][351]
BUFIO2[2].DIVIDE	MAIN[0][209]	MAIN[0][208]	MAIN[0][207]
BUFIO2[3].DIVIDE	MAIN[0][257]	MAIN[0][256]	MAIN[0][255]
BUFIO2[4].DIVIDE	MAIN[0][113]	MAIN[0][112]	MAIN[0][111]
BUFIO2[5].DIVIDE	MAIN[0][161]	MAIN[0][160]	MAIN[0][159]
BUFIO2[6].DIVIDE	MAIN[0][17]	MAIN[0][16]	MAIN[0][15]
BUFIO2[7].DIVIDE	MAIN[0][65]	MAIN[0][64]	MAIN[0][63]
_1	1	1	1
_2	0	0	0
_3	0	0	1
_4	0	1	0
_5	0	1	1
_6	1	0	0
_7	1	0	1
_8	1	1	0

Bels BUFIO2FB

spartan6 CLK_S bel BUFIO2FB pins
Pin	Direction	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
I	in	CELL[3].IMUX_BUFIO2FB[0]	CELL[3].IMUX_BUFIO2FB[1]	CELL[3].IMUX_BUFIO2FB[2]	CELL[3].IMUX_BUFIO2FB[3]	CELL[1].IMUX_BUFIO2FB[0]	CELL[1].IMUX_BUFIO2FB[1]	CELL[1].IMUX_BUFIO2FB[2]	CELL[1].IMUX_BUFIO2FB[3]
O	out	CELL[1].IOFBCLK_CMT_V[0]	CELL[1].IOFBCLK_CMT_V[1]	CELL[1].IOFBCLK_CMT_V[2]	CELL[1].IOFBCLK_CMT_V[3]	CELL[1].IOFBCLK_CMT_V[4]	CELL[1].IOFBCLK_CMT_V[5]	CELL[1].IOFBCLK_CMT_V[6]	CELL[1].IOFBCLK_CMT_V[7]

spartan6 CLK_S bel BUFIO2FB attribute bits
Attribute	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
ENABLE	MAIN[0][319]	MAIN[0][367]	MAIN[0][223]	MAIN[0][271]	MAIN[0][127]	MAIN[0][175]	MAIN[0][31]	MAIN[0][79]
DIVIDE_BYPASS bit 0	!MAIN[0][315]	!MAIN[0][363]	!MAIN[0][219]	!MAIN[0][267]	!MAIN[0][123]	!MAIN[0][171]	!MAIN[0][27]	!MAIN[0][75]
DIVIDE_BYPASS bit 1	!MAIN[0][316]	!MAIN[0][364]	!MAIN[0][220]	!MAIN[0][268]	!MAIN[0][124]	!MAIN[0][172]	!MAIN[0][28]	!MAIN[0][76]
DIVIDE_BYPASS bit 2	!MAIN[0][317]	!MAIN[0][365]	!MAIN[0][221]	!MAIN[0][269]	!MAIN[0][125]	!MAIN[0][173]	!MAIN[0][29]	!MAIN[0][77]
DIVIDE_BYPASS bit 3	!MAIN[0][322]	!MAIN[0][370]	!MAIN[0][226]	!MAIN[0][274]	!MAIN[0][130]	!MAIN[0][178]	!MAIN[0][34]	!MAIN[0][82]

Bels BUFPLL

spartan6 CLK_S bel BUFPLL pins
Pin	Direction	BUFPLL
GCLK[0]	in	CELL[1].IMUX_CLK_GCLK[0]
GCLK[1]	in	CELL[1].IMUX_CLK_GCLK[1]
PLLIN_CMT[0]	in	CELL[1].IMUX_BUFPLL_PLLIN[0]
PLLIN_CMT[1]	in	CELL[1].IMUX_BUFPLL_PLLIN[1]
LOCKED[0]	in	CELL[1].IMUX_BUFPLL_LOCKED[0]
LOCKED[1]	in	CELL[1].IMUX_BUFPLL_LOCKED[1]
PLLCLK[0]	out	CELL[1].PLLCLK[0]
PLLCLK[1]	out	CELL[1].PLLCLK[1]
PLLCE[0]	out	CELL[1].PLLCE[0]
PLLCE[1]	out	CELL[1].PLLCE[1]
LOCK[0]	out	CELL[2].OUT_BEL[18]
LOCK[1]	out	CELL[2].OUT_BEL[19]

spartan6 CLK_S bel BUFPLL attribute bits
Attribute	BUFPLL
ENABLE	MAIN[0][135]
LOCK_SRC	[enum: BUFPLL_LOCK_SRC]
DATA_RATE0	[enum: BUFPLL_DATA_RATE]
DATA_RATE1	[enum: BUFPLL_DATA_RATE]
DIVIDE0	[enum: BUFIO2_DIVIDE]
DIVIDE1	[enum: BUFIO2_DIVIDE]
ENABLE_BOTH_SYNC0 bit 0	MAIN[0][234]
ENABLE_BOTH_SYNC0 bit 1	MAIN[0][280]
ENABLE_BOTH_SYNC0 bit 2	MAIN[0][286]
ENABLE_BOTH_SYNC1 bit 0	MAIN[0][237]
ENABLE_BOTH_SYNC1 bit 1	MAIN[0][282]
ENABLE_BOTH_SYNC1 bit 2	MAIN[0][329]
ENABLE_NONE_SYNC0 bit 0	MAIN[0][279]
ENABLE_NONE_SYNC0 bit 1	MAIN[0][285]
ENABLE_NONE_SYNC1 bit 0	MAIN[0][281]
ENABLE_NONE_SYNC1 bit 1	MAIN[0][328]
ENABLE_SYNC0	!MAIN[0][140]
ENABLE_SYNC1	!MAIN[0][185]

spartan6 CLK_S enum BUFPLL_LOCK_SRC
BUFPLL.LOCK_SRC	MAIN[0][139]	MAIN[0][184]
NONE	0	0
LOCK_TO_0	0	1
LOCK_TO_1	1	0

spartan6 CLK_S enum BUFPLL_DATA_RATE
BUFPLL.DATA_RATE0	MAIN[0][141]
BUFPLL.DATA_RATE1	MAIN[0][186]
SDR	0
DDR	1

spartan6 CLK_S enum BUFIO2_DIVIDE
BUFPLL.DIVIDE0	MAIN[0][190]	MAIN[0][189]	MAIN[0][187]	MAIN[0][138]	MAIN[0][137]	MAIN[0][136]
BUFPLL.DIVIDE1	MAIN[0][233]	MAIN[0][232]	MAIN[0][191]	MAIN[0][183]	MAIN[0][143]	MAIN[0][142]
_1	1	1	0	1	1	1
_2	0	0	1	0	0	0
_3	0	0	0	0	0	1
_4	0	1	1	0	1	0
_5	0	1	0	0	1	1
_6	1	0	1	1	0	0
_7	1	0	0	1	0	1
_8	1	1	1	1	1	0

Bels MISR

spartan6 CLK_S bel MISR pins
Pin	Direction	MISR_CLK

spartan6 CLK_S bel MISR attribute bits
Attribute	MISR_CLK
ENABLE	MAIN[0][379]
RESET	MAIN[0][380]

Bel wires

spartan6 CLK_S bel wires
Wire	Pins
CELL[1].IMUX_CLK_GCLK[0]	BUFPLL.GCLK[0]
CELL[1].IMUX_CLK_GCLK[1]	BUFPLL.GCLK[1]
CELL[1].IOCLK[0]	BUFIO2[4].IOCLK
CELL[1].IOCLK[1]	BUFIO2[5].IOCLK
CELL[1].IOCLK[2]	BUFIO2[6].IOCLK
CELL[1].IOCLK[3]	BUFIO2[7].IOCLK
CELL[1].IOCE[0]	BUFIO2[4].SERDESSTROBE
CELL[1].IOCE[1]	BUFIO2[5].SERDESSTROBE
CELL[1].IOCE[2]	BUFIO2[6].SERDESSTROBE
CELL[1].IOCE[3]	BUFIO2[7].SERDESSTROBE
CELL[1].PLLCLK[0]	BUFPLL.PLLCLK[0]
CELL[1].PLLCLK[1]	BUFPLL.PLLCLK[1]
CELL[1].PLLCE[0]	BUFPLL.PLLCE[0]
CELL[1].PLLCE[1]	BUFPLL.PLLCE[1]
CELL[1].IMUX_BUFIO2_I[0]	BUFIO2[4].I
CELL[1].IMUX_BUFIO2_I[1]	BUFIO2[5].I
CELL[1].IMUX_BUFIO2_I[2]	BUFIO2[6].I
CELL[1].IMUX_BUFIO2_I[3]	BUFIO2[7].I
CELL[1].IMUX_BUFIO2_IB[0]	BUFIO2[4].IB
CELL[1].IMUX_BUFIO2_IB[1]	BUFIO2[5].IB
CELL[1].IMUX_BUFIO2_IB[2]	BUFIO2[6].IB
CELL[1].IMUX_BUFIO2_IB[3]	BUFIO2[7].IB
CELL[1].IMUX_BUFIO2FB[0]	BUFIO2FB[4].I
CELL[1].IMUX_BUFIO2FB[1]	BUFIO2FB[5].I
CELL[1].IMUX_BUFIO2FB[2]	BUFIO2FB[6].I
CELL[1].IMUX_BUFIO2FB[3]	BUFIO2FB[7].I
CELL[1].OUT_DIVCLK[0]	BUFIO2[4].DIVCLK
CELL[1].OUT_DIVCLK[1]	BUFIO2[5].DIVCLK
CELL[1].OUT_DIVCLK[2]	BUFIO2[6].DIVCLK
CELL[1].OUT_DIVCLK[3]	BUFIO2[7].DIVCLK
CELL[1].DIVCLK_CMT_V[0]	BUFIO2[0].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[1]	BUFIO2[1].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[2]	BUFIO2[2].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[3]	BUFIO2[3].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[4]	BUFIO2[4].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[5]	BUFIO2[5].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[6]	BUFIO2[6].DIVCLK_CMT
CELL[1].DIVCLK_CMT_V[7]	BUFIO2[7].DIVCLK_CMT
CELL[1].IOFBCLK_CMT_V[0]	BUFIO2FB[0].O
CELL[1].IOFBCLK_CMT_V[1]	BUFIO2FB[1].O
CELL[1].IOFBCLK_CMT_V[2]	BUFIO2FB[2].O
CELL[1].IOFBCLK_CMT_V[3]	BUFIO2FB[3].O
CELL[1].IOFBCLK_CMT_V[4]	BUFIO2FB[4].O
CELL[1].IOFBCLK_CMT_V[5]	BUFIO2FB[5].O
CELL[1].IOFBCLK_CMT_V[6]	BUFIO2FB[6].O
CELL[1].IOFBCLK_CMT_V[7]	BUFIO2FB[7].O
CELL[1].IMUX_BUFPLL_PLLIN[0]	BUFPLL.PLLIN_CMT[0]
CELL[1].IMUX_BUFPLL_PLLIN[1]	BUFPLL.PLLIN_CMT[1]
CELL[1].IMUX_BUFPLL_LOCKED[0]	BUFPLL.LOCKED[0]
CELL[1].IMUX_BUFPLL_LOCKED[1]	BUFPLL.LOCKED[1]
CELL[2].OUT_BEL[18]	BUFPLL.LOCK[0]
CELL[2].OUT_BEL[19]	BUFPLL.LOCK[1]
CELL[3].IOCLK[0]	BUFIO2[0].IOCLK
CELL[3].IOCLK[1]	BUFIO2[1].IOCLK
CELL[3].IOCLK[2]	BUFIO2[2].IOCLK
CELL[3].IOCLK[3]	BUFIO2[3].IOCLK
CELL[3].IOCE[0]	BUFIO2[0].SERDESSTROBE
CELL[3].IOCE[1]	BUFIO2[1].SERDESSTROBE
CELL[3].IOCE[2]	BUFIO2[2].SERDESSTROBE
CELL[3].IOCE[3]	BUFIO2[3].SERDESSTROBE
CELL[3].IMUX_BUFIO2_I[0]	BUFIO2[0].I
CELL[3].IMUX_BUFIO2_I[1]	BUFIO2[1].I
CELL[3].IMUX_BUFIO2_I[2]	BUFIO2[2].I
CELL[3].IMUX_BUFIO2_I[3]	BUFIO2[3].I
CELL[3].IMUX_BUFIO2_IB[0]	BUFIO2[0].IB
CELL[3].IMUX_BUFIO2_IB[1]	BUFIO2[1].IB
CELL[3].IMUX_BUFIO2_IB[2]	BUFIO2[2].IB
CELL[3].IMUX_BUFIO2_IB[3]	BUFIO2[3].IB
CELL[3].IMUX_BUFIO2FB[0]	BUFIO2FB[0].I
CELL[3].IMUX_BUFIO2FB[1]	BUFIO2FB[1].I
CELL[3].IMUX_BUFIO2FB[2]	BUFIO2FB[2].I
CELL[3].IMUX_BUFIO2FB[3]	BUFIO2FB[3].I
CELL[3].OUT_DIVCLK[0]	BUFIO2[0].DIVCLK
CELL[3].OUT_DIVCLK[1]	BUFIO2[1].DIVCLK
CELL[3].OUT_DIVCLK[2]	BUFIO2[2].DIVCLK
CELL[3].OUT_DIVCLK[3]	BUFIO2[3].DIVCLK

Bitstream

spartan6 CLK_S rect MAIN
Bit	Frame
Bit	F0
B0	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 0
B1	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 1
B2	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 2
B3	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 1
B5	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 2
B6	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 0
B7	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 1
B8	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 2
B9	BUFIO2[6]: POS_EDGE bit 0
B10	BUFIO2[6]: POS_EDGE bit 1
B11	BUFIO2[6]: POS_EDGE bit 2
B12	BUFIO2[6]: NEG_EDGE bit 0
B13	BUFIO2[6]: NEG_EDGE bit 1
B14	-
B15	BUFIO2[6]: DIVIDE bit 0
B16	BUFIO2[6]: DIVIDE bit 1
B17	BUFIO2[6]: DIVIDE bit 2
B18	BUFIO2[6]: R_EDGE
B19	BUFIO2[6]: ENABLE
B20	BUFIO2[6]: ENABLE_2CLK
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 0
B28	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 1
B29	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 2
B30	-
B31	BUFIO2FB[6]: ENABLE
B32	-
B33	BUFIO2[6]: ! DIVIDE_BYPASS
B34	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 3
B35	CLK_INT: mux CELL[1].DIVCLK_CLKC[6] bit 1
B36	BUFIO2[6]: IOCLK_ENABLE
B37	CLK_INT: mux CELL[1].DIVCLK_CLKC[6] bit 0
B38	BUFIO2[6]: CMT_ENABLE
B39	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 4
B40	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 5
B41	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 6
B42	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 7
B43	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 0
B44	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 1
B45	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 2
B46	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[1] bit 3
B47	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 3
B48	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 0
B49	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 1
B50	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 2
B51	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 0
B52	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 1
B53	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 2
B54	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 0
B55	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 1
B56	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 2
B57	BUFIO2[7]: POS_EDGE bit 0
B58	BUFIO2[7]: POS_EDGE bit 1
B59	BUFIO2[7]: POS_EDGE bit 2
B60	BUFIO2[7]: NEG_EDGE bit 0
B61	BUFIO2[7]: NEG_EDGE bit 1
B62	-
B63	BUFIO2[7]: DIVIDE bit 0
B64	BUFIO2[7]: DIVIDE bit 1
B65	BUFIO2[7]: DIVIDE bit 2
B66	BUFIO2[7]: R_EDGE
B67	BUFIO2[7]: ENABLE
B68	BUFIO2[7]: ENABLE_2CLK
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 0
B76	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 1
B77	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 2
B78	-
B79	BUFIO2FB[7]: ENABLE
B80	-
B81	BUFIO2[7]: ! DIVIDE_BYPASS
B82	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 3
B83	CLK_INT: mux CELL[1].DIVCLK_CLKC[7] bit 1
B84	BUFIO2[7]: IOCLK_ENABLE
B85	CLK_INT: mux CELL[1].DIVCLK_CLKC[7] bit 0
B86	BUFIO2[7]: CMT_ENABLE
B87	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 2
B88	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 1
B89	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 0
B90	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 7
B91	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 6
B92	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 5
B93	CLK_INT: mux CELL[1].IMUX_CLK_GCLK[0] bit 4
B94	-
B95	-
B96	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 0
B97	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 1
B98	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 2
B99	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 0
B100	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 1
B101	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 2
B102	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 0
B103	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 1
B104	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 2
B105	BUFIO2[4]: POS_EDGE bit 0
B106	BUFIO2[4]: POS_EDGE bit 1
B107	BUFIO2[4]: POS_EDGE bit 2
B108	BUFIO2[4]: NEG_EDGE bit 0
B109	BUFIO2[4]: NEG_EDGE bit 1
B110	-
B111	BUFIO2[4]: DIVIDE bit 0
B112	BUFIO2[4]: DIVIDE bit 1
B113	BUFIO2[4]: DIVIDE bit 2
B114	BUFIO2[4]: R_EDGE
B115	BUFIO2[4]: ENABLE
B116	BUFIO2[4]: ENABLE_2CLK
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 0
B124	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 1
B125	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 2
B126	-
B127	BUFIO2FB[4]: ENABLE
B128	-
B129	BUFIO2[4]: ! DIVIDE_BYPASS
B130	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 3
B131	CLK_INT: mux CELL[1].DIVCLK_CLKC[4] bit 1
B132	BUFIO2[4]: IOCLK_ENABLE
B133	CLK_INT: mux CELL[1].DIVCLK_CLKC[4] bit 0
B134	BUFIO2[4]: CMT_ENABLE
B135	BUFPLL: ENABLE
B136	BUFPLL: DIVIDE0 bit 0
B137	BUFPLL: DIVIDE0 bit 1
B138	BUFPLL: DIVIDE0 bit 2
B139	BUFPLL: LOCK_SRC bit 1
B140	BUFPLL: ! ENABLE_SYNC0
B141	BUFPLL: DATA_RATE0 bit 0
B142	BUFPLL: DIVIDE1 bit 0
B143	BUFPLL: DIVIDE1 bit 1
B144	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 0
B145	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 1
B146	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 2
B147	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 0
B148	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 1
B149	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 2
B150	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 0
B151	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 1
B152	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 2
B153	BUFIO2[5]: POS_EDGE bit 0
B154	BUFIO2[5]: POS_EDGE bit 1
B155	BUFIO2[5]: POS_EDGE bit 2
B156	BUFIO2[5]: NEG_EDGE bit 0
B157	BUFIO2[5]: NEG_EDGE bit 1
B158	-
B159	BUFIO2[5]: DIVIDE bit 0
B160	BUFIO2[5]: DIVIDE bit 1
B161	BUFIO2[5]: DIVIDE bit 2
B162	BUFIO2[5]: R_EDGE
B163	BUFIO2[5]: ENABLE
B164	BUFIO2[5]: ENABLE_2CLK
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 0
B172	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 1
B173	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 2
B174	-
B175	BUFIO2FB[5]: ENABLE
B176	-
B177	BUFIO2[5]: ! DIVIDE_BYPASS
B178	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 3
B179	CLK_INT: mux CELL[1].DIVCLK_CLKC[5] bit 1
B180	BUFIO2[5]: IOCLK_ENABLE
B181	CLK_INT: mux CELL[1].DIVCLK_CLKC[5] bit 0
B182	BUFIO2[5]: CMT_ENABLE
B183	BUFPLL: DIVIDE1 bit 2
B184	BUFPLL: LOCK_SRC bit 0
B185	BUFPLL: ! ENABLE_SYNC1
B186	BUFPLL: DATA_RATE1 bit 0
B187	BUFPLL: DIVIDE0 bit 3
B188	-
B189	BUFPLL: DIVIDE0 bit 4
B190	BUFPLL: DIVIDE0 bit 5
B191	BUFPLL: DIVIDE1 bit 3
B192	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[2] bit 0
B193	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[2] bit 1
B194	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[2] bit 2
B195	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[2] bit 0
B196	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[2] bit 1
B197	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[2] bit 2
B198	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[2] bit 0
B199	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[2] bit 1
B200	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[2] bit 2
B201	BUFIO2[2]: POS_EDGE bit 0
B202	BUFIO2[2]: POS_EDGE bit 1
B203	BUFIO2[2]: POS_EDGE bit 2
B204	BUFIO2[2]: NEG_EDGE bit 0
B205	BUFIO2[2]: NEG_EDGE bit 1
B206	-
B207	BUFIO2[2]: DIVIDE bit 0
B208	BUFIO2[2]: DIVIDE bit 1
B209	BUFIO2[2]: DIVIDE bit 2
B210	BUFIO2[2]: R_EDGE
B211	BUFIO2[2]: ENABLE
B212	BUFIO2[2]: ENABLE_2CLK
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 0
B220	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 1
B221	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 2
B222	-
B223	BUFIO2FB[2]: ENABLE
B224	-
B225	BUFIO2[2]: ! DIVIDE_BYPASS
B226	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 3
B227	CLK_INT: mux CELL[1].DIVCLK_CLKC[2] bit 1
B228	BUFIO2[2]: IOCLK_ENABLE
B229	CLK_INT: mux CELL[1].DIVCLK_CLKC[2] bit 0
B230	BUFIO2[2]: CMT_ENABLE
B231	-
B232	BUFPLL: DIVIDE1 bit 4
B233	BUFPLL: DIVIDE1 bit 5
B234	BUFPLL: ENABLE_BOTH_SYNC0 bit 0
B235	-
B236	-
B237	BUFPLL: ENABLE_BOTH_SYNC1 bit 0
B238	-
B239	-
B240	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[3] bit 0
B241	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[3] bit 1
B242	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[3] bit 2
B243	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[3] bit 0
B244	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[3] bit 1
B245	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[3] bit 2
B246	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[3] bit 0
B247	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[3] bit 1
B248	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[3] bit 2
B249	BUFIO2[3]: POS_EDGE bit 0
B250	BUFIO2[3]: POS_EDGE bit 1
B251	BUFIO2[3]: POS_EDGE bit 2
B252	BUFIO2[3]: NEG_EDGE bit 0
B253	BUFIO2[3]: NEG_EDGE bit 1
B254	-
B255	BUFIO2[3]: DIVIDE bit 0
B256	BUFIO2[3]: DIVIDE bit 1
B257	BUFIO2[3]: DIVIDE bit 2
B258	BUFIO2[3]: R_EDGE
B259	BUFIO2[3]: ENABLE
B260	BUFIO2[3]: ENABLE_2CLK
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 0
B268	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 1
B269	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 2
B270	-
B271	BUFIO2FB[3]: ENABLE
B272	-
B273	BUFIO2[3]: ! DIVIDE_BYPASS
B274	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 3
B275	CLK_INT: mux CELL[1].DIVCLK_CLKC[3] bit 1
B276	BUFIO2[3]: IOCLK_ENABLE
B277	CLK_INT: mux CELL[1].DIVCLK_CLKC[3] bit 0
B278	BUFIO2[3]: CMT_ENABLE
B279	BUFPLL: ENABLE_NONE_SYNC0 bit 0
B280	BUFPLL: ENABLE_BOTH_SYNC0 bit 1
B281	BUFPLL: ENABLE_NONE_SYNC1 bit 0
B282	BUFPLL: ENABLE_BOTH_SYNC1 bit 1
B283	-
B284	-
B285	BUFPLL: ENABLE_NONE_SYNC0 bit 1
B286	BUFPLL: ENABLE_BOTH_SYNC0 bit 2
B287	-
B288	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[0] bit 0
B289	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[0] bit 1
B290	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[0] bit 2
B291	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[0] bit 0
B292	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[0] bit 1
B293	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[0] bit 2
B294	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[0] bit 0
B295	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[0] bit 1
B296	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[0] bit 2
B297	BUFIO2[0]: POS_EDGE bit 0
B298	BUFIO2[0]: POS_EDGE bit 1
B299	BUFIO2[0]: POS_EDGE bit 2
B300	BUFIO2[0]: NEG_EDGE bit 0
B301	BUFIO2[0]: NEG_EDGE bit 1
B302	-
B303	BUFIO2[0]: DIVIDE bit 0
B304	BUFIO2[0]: DIVIDE bit 1
B305	BUFIO2[0]: DIVIDE bit 2
B306	BUFIO2[0]: R_EDGE
B307	BUFIO2[0]: ENABLE
B308	BUFIO2[0]: ENABLE_2CLK
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 0
B316	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 1
B317	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 2
B318	-
B319	BUFIO2FB[0]: ENABLE
B320	-
B321	BUFIO2[0]: ! DIVIDE_BYPASS
B322	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 3
B323	CLK_INT: mux CELL[1].DIVCLK_CLKC[0] bit 1
B324	BUFIO2[0]: IOCLK_ENABLE
B325	CLK_INT: mux CELL[1].DIVCLK_CLKC[0] bit 0
B326	BUFIO2[0]: CMT_ENABLE
B327	-
B328	BUFPLL: ENABLE_NONE_SYNC1 bit 1
B329	BUFPLL: ENABLE_BOTH_SYNC1 bit 2
B330	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[0] bit 0
B331	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[0] bit 1
B332	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[0] bit 2
B333	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[1] bit 0
B334	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[1] bit 1
B335	CLK_INT: mux CELL[1].IMUX_BUFPLL_PLLIN[1] bit 2
B336	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[1] bit 0
B337	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[1] bit 1
B338	CLK_INT: mux CELL[3].IMUX_BUFIO2_I[1] bit 2
B339	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[1] bit 0
B340	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[1] bit 1
B341	CLK_INT: mux CELL[3].IMUX_BUFIO2_IB[1] bit 2
B342	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[1] bit 0
B343	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[1] bit 1
B344	CLK_INT: mux CELL[3].IMUX_BUFIO2FB[1] bit 2
B345	BUFIO2[1]: POS_EDGE bit 0
B346	BUFIO2[1]: POS_EDGE bit 1
B347	BUFIO2[1]: POS_EDGE bit 2
B348	BUFIO2[1]: NEG_EDGE bit 0
B349	BUFIO2[1]: NEG_EDGE bit 1
B350	-
B351	BUFIO2[1]: DIVIDE bit 0
B352	BUFIO2[1]: DIVIDE bit 1
B353	BUFIO2[1]: DIVIDE bit 2
B354	BUFIO2[1]: R_EDGE
B355	BUFIO2[1]: ENABLE
B356	BUFIO2[1]: ENABLE_2CLK
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 0
B364	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 1
B365	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 2
B366	-
B367	BUFIO2FB[1]: ENABLE
B368	-
B369	BUFIO2[1]: ! DIVIDE_BYPASS
B370	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 3
B371	CLK_INT: mux CELL[1].DIVCLK_CLKC[1] bit 1
B372	BUFIO2[1]: IOCLK_ENABLE
B373	CLK_INT: mux CELL[1].DIVCLK_CLKC[1] bit 0
B374	BUFIO2[1]: CMT_ENABLE
B375	CLK_INT: mux CELL[1].IMUX_BUFPLL_LOCKED[0] bit 0
B376	CLK_INT: mux CELL[1].IMUX_BUFPLL_LOCKED[0] bit 1
B377	CLK_INT: mux CELL[1].IMUX_BUFPLL_LOCKED[1] bit 0
B378	CLK_INT: mux CELL[1].IMUX_BUFPLL_LOCKED[1] bit 1
B379	MISR_CLK: ENABLE
B380	MISR_CLK: RESET
B381	-
B382	-
B383	-

Tile CLK_N

Cells: 4

Switchbox CLK_INT

spartan6 CLK_N switchbox CLK_INT muxes IMUX_CLK_GCLK[0]
Bits								Destination
MAIN[0][90]	MAIN[0][91]	MAIN[0][92]	MAIN[0][93]	MAIN[0][47]	MAIN[0][87]	MAIN[0][88]	MAIN[0][89]	CELL[0].IMUX_CLK_GCLK[0]
								Source
0	0	0	0	0	0	0	0	off
0	1	0	1	0	0	0	1	CELL[2].HCLK[0]
0	1	0	1	0	0	1	0	CELL[2].HCLK[1]
0	1	0	1	0	1	0	0	CELL[2].HCLK[2]
0	1	0	1	1	0	0	0	CELL[2].HCLK[3]
0	1	1	0	0	0	0	1	CELL[2].HCLK[8]
0	1	1	0	0	0	1	0	CELL[2].HCLK[9]
0	1	1	0	0	1	0	0	CELL[2].HCLK[10]
0	1	1	0	1	0	0	0	CELL[2].HCLK[11]
1	0	0	1	0	0	0	1	CELL[2].HCLK[4]
1	0	0	1	0	0	1	0	CELL[2].HCLK[5]
1	0	0	1	0	1	0	0	CELL[2].HCLK[6]
1	0	0	1	1	0	0	0	CELL[2].HCLK[7]
1	0	1	0	0	0	0	1	CELL[2].HCLK[12]
1	0	1	0	0	0	1	0	CELL[2].HCLK[13]
1	0	1	0	0	1	0	0	CELL[2].HCLK[14]
1	0	1	0	1	0	0	0	CELL[2].HCLK[15]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_CLK_GCLK[1]
Bits								Destination
MAIN[0][42]	MAIN[0][41]	MAIN[0][40]	MAIN[0][39]	MAIN[0][46]	MAIN[0][45]	MAIN[0][44]	MAIN[0][43]	CELL[0].IMUX_CLK_GCLK[1]
								Source
0	0	0	0	0	0	0	0	off
0	1	0	1	0	0	0	1	CELL[2].HCLK[0]
0	1	0	1	0	0	1	0	CELL[2].HCLK[1]
0	1	0	1	0	1	0	0	CELL[2].HCLK[2]
0	1	0	1	1	0	0	0	CELL[2].HCLK[3]
0	1	1	0	0	0	0	1	CELL[2].HCLK[8]
0	1	1	0	0	0	1	0	CELL[2].HCLK[9]
0	1	1	0	0	1	0	0	CELL[2].HCLK[10]
0	1	1	0	1	0	0	0	CELL[2].HCLK[11]
1	0	0	1	0	0	0	1	CELL[2].HCLK[4]
1	0	0	1	0	0	1	0	CELL[2].HCLK[5]
1	0	0	1	0	1	0	0	CELL[2].HCLK[6]
1	0	0	1	1	0	0	0	CELL[2].HCLK[7]
1	0	1	0	0	0	0	1	CELL[2].HCLK[12]
1	0	1	0	0	0	1	0	CELL[2].HCLK[13]
1	0	1	0	0	1	0	0	CELL[2].HCLK[14]
1	0	1	0	1	0	0	0	CELL[2].HCLK[15]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_I[0]
Bits			Destination
MAIN[0][290]	MAIN[0][289]	MAIN[0][288]	CELL[0].IMUX_BUFIO2_I[0]	-
MAIN[0][98]	MAIN[0][97]	MAIN[0][96]	-	CELL[2].IMUX_BUFIO2_I[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[2].OUT_CLKPAD_DQSP
1	0	0	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[2].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP
1	1	1	CELL[0].GTPCLK[0]	CELL[2].GTPCLK[0]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_I[1]
Bits			Destination
MAIN[0][338]	MAIN[0][337]	MAIN[0][336]	CELL[0].IMUX_BUFIO2_I[1]	-
MAIN[0][146]	MAIN[0][145]	MAIN[0][144]	-	CELL[2].IMUX_BUFIO2_I[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[2].OUT_CLKPAD_DQSN
1	0	0	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[2].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN
1	1	1	CELL[0].GTPCLK[1]	CELL[2].GTPCLK[1]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_I[2]
Bits			Destination
MAIN[0][194]	MAIN[0][193]	MAIN[0][192]	CELL[0].IMUX_BUFIO2_I[2]	-
MAIN[0][2]	MAIN[0][1]	MAIN[0][0]	-	CELL[2].IMUX_BUFIO2_I[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[3].OUT_CLKPAD_DQSP
1	0	0	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[3].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP
1	1	1	CELL[0].GTPCLK[2]	CELL[2].GTPCLK[2]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_I[3]
Bits			Destination
MAIN[0][242]	MAIN[0][241]	MAIN[0][240]	CELL[0].IMUX_BUFIO2_I[3]	-
MAIN[0][50]	MAIN[0][49]	MAIN[0][48]	-	CELL[2].IMUX_BUFIO2_I[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[3].OUT_CLKPAD_DQSN
1	0	0	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[3].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN
1	1	1	CELL[0].GTPCLK[3]	CELL[2].GTPCLK[3]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_IB[0]
Bits			Destination
MAIN[0][293]	MAIN[0][292]	MAIN[0][291]	CELL[0].IMUX_BUFIO2_IB[0]	-
MAIN[0][101]	MAIN[0][100]	MAIN[0][99]	-	CELL[2].IMUX_BUFIO2_IB[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[2].OUT_CLKPAD_DQSN
1	0	0	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[2].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_IB[1]
Bits			Destination
MAIN[0][341]	MAIN[0][340]	MAIN[0][339]	CELL[0].IMUX_BUFIO2_IB[1]	-
MAIN[0][149]	MAIN[0][148]	MAIN[0][147]	-	CELL[2].IMUX_BUFIO2_IB[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[2].OUT_CLKPAD_DQSP
1	0	0	CELL[2].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[2].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[2].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_IB[2]
Bits			Destination
MAIN[0][197]	MAIN[0][196]	MAIN[0][195]	CELL[0].IMUX_BUFIO2_IB[2]	-
MAIN[0][5]	MAIN[0][4]	MAIN[0][3]	-	CELL[2].IMUX_BUFIO2_IB[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[3].OUT_CLKPAD_DQSN
1	0	0	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[3].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2_IB[3]
Bits			Destination
MAIN[0][245]	MAIN[0][244]	MAIN[0][243]	CELL[0].IMUX_BUFIO2_IB[3]	-
MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	-	CELL[2].IMUX_BUFIO2_IB[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[3].OUT_CLKPAD_DQSP
1	0	0	CELL[3].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[3].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[3].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2FB[0]
Bits			Destination
MAIN[0][296]	MAIN[0][295]	MAIN[0][294]	CELL[0].IMUX_BUFIO2FB[0]	-
MAIN[0][104]	MAIN[0][103]	MAIN[0][102]	-	CELL[2].IMUX_BUFIO2FB[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[2].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_DFB[1]	CELL[2].OUT_CLKPAD_DFB[1]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[1]	CELL[2].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[1]	CELL[2].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[0].GTPFB[0]	CELL[2].GTPFB[0]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2FB[1]
Bits			Destination
MAIN[0][344]	MAIN[0][343]	MAIN[0][342]	CELL[0].IMUX_BUFIO2FB[1]	-
MAIN[0][152]	MAIN[0][151]	MAIN[0][150]	-	CELL[2].IMUX_BUFIO2FB[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[2].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_DFB[0]	CELL[2].OUT_CLKPAD_DFB[0]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[0]	CELL[2].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[0]	CELL[2].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[0].GTPFB[1]	CELL[2].GTPFB[1]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2FB[2]
Bits			Destination
MAIN[0][200]	MAIN[0][199]	MAIN[0][198]	CELL[0].IMUX_BUFIO2FB[2]	-
MAIN[0][8]	MAIN[0][7]	MAIN[0][6]	-	CELL[2].IMUX_BUFIO2FB[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[3].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_DFB[1]	CELL[3].OUT_CLKPAD_DFB[1]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[1]	CELL[3].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[1]	CELL[3].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[0].GTPFB[2]	CELL[2].GTPFB[2]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFIO2FB[3]
Bits			Destination
MAIN[0][248]	MAIN[0][247]	MAIN[0][246]	CELL[0].IMUX_BUFIO2FB[3]	-
MAIN[0][56]	MAIN[0][55]	MAIN[0][54]	-	CELL[2].IMUX_BUFIO2FB[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[3].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_DFB[0]	CELL[3].OUT_CLKPAD_DFB[0]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[0]	CELL[3].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[0]	CELL[3].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[0].GTPFB[3]	CELL[2].GTPFB[3]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[0]
Bits		Destination
MAIN[0][323]	MAIN[0][325]	CELL[0].DIVCLK_CLKC[0]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[1]
1	1	CELL[0].OUT_DIVCLK[0]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[1]
Bits		Destination
MAIN[0][371]	MAIN[0][373]	CELL[0].DIVCLK_CLKC[1]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[0]
1	1	CELL[0].OUT_DIVCLK[1]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[2]
Bits		Destination
MAIN[0][227]	MAIN[0][229]	CELL[0].DIVCLK_CLKC[2]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[1]
1	1	CELL[0].OUT_DIVCLK[2]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[3]
Bits		Destination
MAIN[0][275]	MAIN[0][277]	CELL[0].DIVCLK_CLKC[3]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[0]
1	1	CELL[0].OUT_DIVCLK[3]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[4]
Bits		Destination
MAIN[0][131]	MAIN[0][133]	CELL[0].DIVCLK_CLKC[4]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[2].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[0]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[5]
Bits		Destination
MAIN[0][179]	MAIN[0][181]	CELL[0].DIVCLK_CLKC[5]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[2].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[1]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[6]
Bits		Destination
MAIN[0][35]	MAIN[0][37]	CELL[0].DIVCLK_CLKC[6]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[3].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[2]

spartan6 CLK_N switchbox CLK_INT muxes DIVCLK_CLKC[7]
Bits		Destination
MAIN[0][83]	MAIN[0][85]	CELL[0].DIVCLK_CLKC[7]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[3].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[3]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFPLL_PLLIN[0]
Bits			Destination
MAIN[0][332]	MAIN[0][331]	MAIN[0][330]	CELL[0].IMUX_BUFPLL_PLLIN[0]
			Source
0	0	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[0]
0	0	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[1]
0	1	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[2]
0	1	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[3]
1	0	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[4]
1	0	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[5]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFPLL_PLLIN[1]
Bits			Destination
MAIN[0][335]	MAIN[0][334]	MAIN[0][333]	CELL[0].IMUX_BUFPLL_PLLIN[1]
			Source
0	0	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[0]
0	0	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[1]
0	1	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[2]
0	1	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[3]
1	0	0	CELL[0].CMT_BUFPLL_V_CLKOUT_S[4]
1	0	1	CELL[0].CMT_BUFPLL_V_CLKOUT_S[5]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFPLL_LOCKED[0]
Bits		Destination
MAIN[0][376]	MAIN[0][375]	CELL[0].IMUX_BUFPLL_LOCKED[0]
		Source
0	0	CELL[0].CMT_BUFPLL_V_LOCKED_S[0]
0	1	CELL[0].CMT_BUFPLL_V_LOCKED_S[1]
1	0	CELL[0].CMT_BUFPLL_V_LOCKED_S[2]

spartan6 CLK_N switchbox CLK_INT muxes IMUX_BUFPLL_LOCKED[1]
Bits		Destination
MAIN[0][378]	MAIN[0][377]	CELL[0].IMUX_BUFPLL_LOCKED[1]
		Source
0	0	CELL[0].CMT_BUFPLL_V_LOCKED_S[0]
0	1	CELL[0].CMT_BUFPLL_V_LOCKED_S[1]
1	0	CELL[0].CMT_BUFPLL_V_LOCKED_S[2]

Bels BUFIO2

spartan6 CLK_N bel BUFIO2 pins
Pin	Direction	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
I	in	CELL[0].IMUX_BUFIO2_I[0]	CELL[0].IMUX_BUFIO2_I[1]	CELL[0].IMUX_BUFIO2_I[2]	CELL[0].IMUX_BUFIO2_I[3]	CELL[2].IMUX_BUFIO2_I[0]	CELL[2].IMUX_BUFIO2_I[1]	CELL[2].IMUX_BUFIO2_I[2]	CELL[2].IMUX_BUFIO2_I[3]
IB	in	CELL[0].IMUX_BUFIO2_IB[0]	CELL[0].IMUX_BUFIO2_IB[1]	CELL[0].IMUX_BUFIO2_IB[2]	CELL[0].IMUX_BUFIO2_IB[3]	CELL[2].IMUX_BUFIO2_IB[0]	CELL[2].IMUX_BUFIO2_IB[1]	CELL[2].IMUX_BUFIO2_IB[2]	CELL[2].IMUX_BUFIO2_IB[3]
DIVCLK	out	CELL[0].OUT_DIVCLK[0]	CELL[0].OUT_DIVCLK[1]	CELL[0].OUT_DIVCLK[2]	CELL[0].OUT_DIVCLK[3]	CELL[2].OUT_DIVCLK[0]	CELL[2].OUT_DIVCLK[1]	CELL[2].OUT_DIVCLK[2]	CELL[2].OUT_DIVCLK[3]
DIVCLK_CMT	out	CELL[0].DIVCLK_CMT_V[0]	CELL[0].DIVCLK_CMT_V[1]	CELL[0].DIVCLK_CMT_V[2]	CELL[0].DIVCLK_CMT_V[3]	CELL[0].DIVCLK_CMT_V[4]	CELL[0].DIVCLK_CMT_V[5]	CELL[0].DIVCLK_CMT_V[6]	CELL[0].DIVCLK_CMT_V[7]
IOCLK	out	CELL[0].IOCLK[0]	CELL[0].IOCLK[1]	CELL[0].IOCLK[2]	CELL[0].IOCLK[3]	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]
SERDESSTROBE	out	CELL[0].IOCE[0]	CELL[0].IOCE[1]	CELL[0].IOCE[2]	CELL[0].IOCE[3]	CELL[2].IOCE[0]	CELL[2].IOCE[1]	CELL[2].IOCE[2]	CELL[2].IOCE[3]

spartan6 CLK_N bel BUFIO2 attribute bits
Attribute	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
ENABLE	MAIN[0][307]	MAIN[0][355]	MAIN[0][211]	MAIN[0][259]	MAIN[0][115]	MAIN[0][163]	MAIN[0][19]	MAIN[0][67]
ENABLE_2CLK	MAIN[0][308]	MAIN[0][356]	MAIN[0][212]	MAIN[0][260]	MAIN[0][116]	MAIN[0][164]	MAIN[0][20]	MAIN[0][68]
CMT_ENABLE	MAIN[0][326]	MAIN[0][374]	MAIN[0][230]	MAIN[0][278]	MAIN[0][134]	MAIN[0][182]	MAIN[0][38]	MAIN[0][86]
IOCLK_ENABLE	MAIN[0][324]	MAIN[0][372]	MAIN[0][228]	MAIN[0][276]	MAIN[0][132]	MAIN[0][180]	MAIN[0][36]	MAIN[0][84]
DIVIDE	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]
DIVIDE_BYPASS	!MAIN[0][321]	!MAIN[0][369]	!MAIN[0][225]	!MAIN[0][273]	!MAIN[0][129]	!MAIN[0][177]	!MAIN[0][33]	!MAIN[0][81]
R_EDGE	MAIN[0][306]	MAIN[0][354]	MAIN[0][210]	MAIN[0][258]	MAIN[0][114]	MAIN[0][162]	MAIN[0][18]	MAIN[0][66]
POS_EDGE bit 0	MAIN[0][297]	MAIN[0][345]	MAIN[0][201]	MAIN[0][249]	MAIN[0][105]	MAIN[0][153]	MAIN[0][9]	MAIN[0][57]
POS_EDGE bit 1	MAIN[0][298]	MAIN[0][346]	MAIN[0][202]	MAIN[0][250]	MAIN[0][106]	MAIN[0][154]	MAIN[0][10]	MAIN[0][58]
POS_EDGE bit 2	MAIN[0][299]	MAIN[0][347]	MAIN[0][203]	MAIN[0][251]	MAIN[0][107]	MAIN[0][155]	MAIN[0][11]	MAIN[0][59]
NEG_EDGE bit 0	MAIN[0][300]	MAIN[0][348]	MAIN[0][204]	MAIN[0][252]	MAIN[0][108]	MAIN[0][156]	MAIN[0][12]	MAIN[0][60]
NEG_EDGE bit 1	MAIN[0][301]	MAIN[0][349]	MAIN[0][205]	MAIN[0][253]	MAIN[0][109]	MAIN[0][157]	MAIN[0][13]	MAIN[0][61]

spartan6 CLK_N enum BUFIO2_DIVIDE
BUFIO2[0].DIVIDE	MAIN[0][305]	MAIN[0][304]	MAIN[0][303]
BUFIO2[1].DIVIDE	MAIN[0][353]	MAIN[0][352]	MAIN[0][351]
BUFIO2[2].DIVIDE	MAIN[0][209]	MAIN[0][208]	MAIN[0][207]
BUFIO2[3].DIVIDE	MAIN[0][257]	MAIN[0][256]	MAIN[0][255]
BUFIO2[4].DIVIDE	MAIN[0][113]	MAIN[0][112]	MAIN[0][111]
BUFIO2[5].DIVIDE	MAIN[0][161]	MAIN[0][160]	MAIN[0][159]
BUFIO2[6].DIVIDE	MAIN[0][17]	MAIN[0][16]	MAIN[0][15]
BUFIO2[7].DIVIDE	MAIN[0][65]	MAIN[0][64]	MAIN[0][63]
_1	1	1	1
_2	0	0	0
_3	0	0	1
_4	0	1	0
_5	0	1	1
_6	1	0	0
_7	1	0	1
_8	1	1	0

Bels BUFIO2FB

spartan6 CLK_N bel BUFIO2FB pins
Pin	Direction	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
I	in	CELL[0].IMUX_BUFIO2FB[0]	CELL[0].IMUX_BUFIO2FB[1]	CELL[0].IMUX_BUFIO2FB[2]	CELL[0].IMUX_BUFIO2FB[3]	CELL[2].IMUX_BUFIO2FB[0]	CELL[2].IMUX_BUFIO2FB[1]	CELL[2].IMUX_BUFIO2FB[2]	CELL[2].IMUX_BUFIO2FB[3]
O	out	CELL[0].IOFBCLK_CMT_V[0]	CELL[0].IOFBCLK_CMT_V[1]	CELL[0].IOFBCLK_CMT_V[2]	CELL[0].IOFBCLK_CMT_V[3]	CELL[0].IOFBCLK_CMT_V[4]	CELL[0].IOFBCLK_CMT_V[5]	CELL[0].IOFBCLK_CMT_V[6]	CELL[0].IOFBCLK_CMT_V[7]

spartan6 CLK_N bel BUFIO2FB attribute bits
Attribute	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
ENABLE	MAIN[0][319]	MAIN[0][367]	MAIN[0][223]	MAIN[0][271]	MAIN[0][127]	MAIN[0][175]	MAIN[0][31]	MAIN[0][79]
DIVIDE_BYPASS bit 0	!MAIN[0][315]	!MAIN[0][363]	!MAIN[0][219]	!MAIN[0][267]	!MAIN[0][123]	!MAIN[0][171]	!MAIN[0][27]	!MAIN[0][75]
DIVIDE_BYPASS bit 1	!MAIN[0][316]	!MAIN[0][364]	!MAIN[0][220]	!MAIN[0][268]	!MAIN[0][124]	!MAIN[0][172]	!MAIN[0][28]	!MAIN[0][76]
DIVIDE_BYPASS bit 2	!MAIN[0][317]	!MAIN[0][365]	!MAIN[0][221]	!MAIN[0][269]	!MAIN[0][125]	!MAIN[0][173]	!MAIN[0][29]	!MAIN[0][77]
DIVIDE_BYPASS bit 3	!MAIN[0][322]	!MAIN[0][370]	!MAIN[0][226]	!MAIN[0][274]	!MAIN[0][130]	!MAIN[0][178]	!MAIN[0][34]	!MAIN[0][82]

Bels BUFPLL

spartan6 CLK_N bel BUFPLL pins
Pin	Direction	BUFPLL
GCLK[0]	in	CELL[0].IMUX_CLK_GCLK[0]
GCLK[1]	in	CELL[0].IMUX_CLK_GCLK[1]
PLLIN_CMT[0]	in	CELL[0].IMUX_BUFPLL_PLLIN[0]
PLLIN_CMT[1]	in	CELL[0].IMUX_BUFPLL_PLLIN[1]
LOCKED[0]	in	CELL[0].IMUX_BUFPLL_LOCKED[0]
LOCKED[1]	in	CELL[0].IMUX_BUFPLL_LOCKED[1]
PLLCLK[0]	out	CELL[0].PLLCLK[0]
PLLCLK[1]	out	CELL[0].PLLCLK[1]
PLLCE[0]	out	CELL[0].PLLCE[0]
PLLCE[1]	out	CELL[0].PLLCE[1]
LOCK[0]	out	CELL[2].OUT_BEL[18]
LOCK[1]	out	CELL[2].OUT_BEL[19]

spartan6 CLK_N bel BUFPLL attribute bits
Attribute	BUFPLL
ENABLE	MAIN[0][135]
LOCK_SRC	[enum: BUFPLL_LOCK_SRC]
DATA_RATE0	[enum: BUFPLL_DATA_RATE]
DATA_RATE1	[enum: BUFPLL_DATA_RATE]
DIVIDE0	[enum: BUFIO2_DIVIDE]
DIVIDE1	[enum: BUFIO2_DIVIDE]
ENABLE_BOTH_SYNC0 bit 0	MAIN[0][234]
ENABLE_BOTH_SYNC0 bit 1	MAIN[0][280]
ENABLE_BOTH_SYNC0 bit 2	MAIN[0][286]
ENABLE_BOTH_SYNC1 bit 0	MAIN[0][237]
ENABLE_BOTH_SYNC1 bit 1	MAIN[0][282]
ENABLE_BOTH_SYNC1 bit 2	MAIN[0][329]
ENABLE_NONE_SYNC0 bit 0	MAIN[0][279]
ENABLE_NONE_SYNC0 bit 1	MAIN[0][285]
ENABLE_NONE_SYNC1 bit 0	MAIN[0][281]
ENABLE_NONE_SYNC1 bit 1	MAIN[0][328]
ENABLE_SYNC0	!MAIN[0][140]
ENABLE_SYNC1	!MAIN[0][185]

spartan6 CLK_N enum BUFPLL_LOCK_SRC
BUFPLL.LOCK_SRC	MAIN[0][139]	MAIN[0][184]
NONE	0	0
LOCK_TO_0	0	1
LOCK_TO_1	1	0

spartan6 CLK_N enum BUFPLL_DATA_RATE
BUFPLL.DATA_RATE0	MAIN[0][141]
BUFPLL.DATA_RATE1	MAIN[0][186]
SDR	0
DDR	1

spartan6 CLK_N enum BUFIO2_DIVIDE
BUFPLL.DIVIDE0	MAIN[0][190]	MAIN[0][189]	MAIN[0][187]	MAIN[0][138]	MAIN[0][137]	MAIN[0][136]
BUFPLL.DIVIDE1	MAIN[0][233]	MAIN[0][232]	MAIN[0][191]	MAIN[0][183]	MAIN[0][143]	MAIN[0][142]
_1	1	1	0	1	1	1
_2	0	0	1	0	0	0
_3	0	0	0	0	0	1
_4	0	1	1	0	1	0
_5	0	1	0	0	1	1
_6	1	0	1	1	0	0
_7	1	0	0	1	0	1
_8	1	1	1	1	1	0

Bels MISR

spartan6 CLK_N bel MISR pins
Pin	Direction	MISR_CLK

spartan6 CLK_N bel MISR attribute bits
Attribute	MISR_CLK
ENABLE	MAIN[0][379]
RESET	MAIN[0][380]

Bel wires

spartan6 CLK_N bel wires
Wire	Pins
CELL[0].IMUX_CLK_GCLK[0]	BUFPLL.GCLK[0]
CELL[0].IMUX_CLK_GCLK[1]	BUFPLL.GCLK[1]
CELL[0].IOCLK[0]	BUFIO2[0].IOCLK
CELL[0].IOCLK[1]	BUFIO2[1].IOCLK
CELL[0].IOCLK[2]	BUFIO2[2].IOCLK
CELL[0].IOCLK[3]	BUFIO2[3].IOCLK
CELL[0].IOCE[0]	BUFIO2[0].SERDESSTROBE
CELL[0].IOCE[1]	BUFIO2[1].SERDESSTROBE
CELL[0].IOCE[2]	BUFIO2[2].SERDESSTROBE
CELL[0].IOCE[3]	BUFIO2[3].SERDESSTROBE
CELL[0].PLLCLK[0]	BUFPLL.PLLCLK[0]
CELL[0].PLLCLK[1]	BUFPLL.PLLCLK[1]
CELL[0].PLLCE[0]	BUFPLL.PLLCE[0]
CELL[0].PLLCE[1]	BUFPLL.PLLCE[1]
CELL[0].IMUX_BUFIO2_I[0]	BUFIO2[0].I
CELL[0].IMUX_BUFIO2_I[1]	BUFIO2[1].I
CELL[0].IMUX_BUFIO2_I[2]	BUFIO2[2].I
CELL[0].IMUX_BUFIO2_I[3]	BUFIO2[3].I
CELL[0].IMUX_BUFIO2_IB[0]	BUFIO2[0].IB
CELL[0].IMUX_BUFIO2_IB[1]	BUFIO2[1].IB
CELL[0].IMUX_BUFIO2_IB[2]	BUFIO2[2].IB
CELL[0].IMUX_BUFIO2_IB[3]	BUFIO2[3].IB
CELL[0].IMUX_BUFIO2FB[0]	BUFIO2FB[0].I
CELL[0].IMUX_BUFIO2FB[1]	BUFIO2FB[1].I
CELL[0].IMUX_BUFIO2FB[2]	BUFIO2FB[2].I
CELL[0].IMUX_BUFIO2FB[3]	BUFIO2FB[3].I
CELL[0].OUT_DIVCLK[0]	BUFIO2[0].DIVCLK
CELL[0].OUT_DIVCLK[1]	BUFIO2[1].DIVCLK
CELL[0].OUT_DIVCLK[2]	BUFIO2[2].DIVCLK
CELL[0].OUT_DIVCLK[3]	BUFIO2[3].DIVCLK
CELL[0].DIVCLK_CMT_V[0]	BUFIO2[0].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[1]	BUFIO2[1].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[2]	BUFIO2[2].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[3]	BUFIO2[3].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[4]	BUFIO2[4].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[5]	BUFIO2[5].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[6]	BUFIO2[6].DIVCLK_CMT
CELL[0].DIVCLK_CMT_V[7]	BUFIO2[7].DIVCLK_CMT
CELL[0].IOFBCLK_CMT_V[0]	BUFIO2FB[0].O
CELL[0].IOFBCLK_CMT_V[1]	BUFIO2FB[1].O
CELL[0].IOFBCLK_CMT_V[2]	BUFIO2FB[2].O
CELL[0].IOFBCLK_CMT_V[3]	BUFIO2FB[3].O
CELL[0].IOFBCLK_CMT_V[4]	BUFIO2FB[4].O
CELL[0].IOFBCLK_CMT_V[5]	BUFIO2FB[5].O
CELL[0].IOFBCLK_CMT_V[6]	BUFIO2FB[6].O
CELL[0].IOFBCLK_CMT_V[7]	BUFIO2FB[7].O
CELL[0].IMUX_BUFPLL_PLLIN[0]	BUFPLL.PLLIN_CMT[0]
CELL[0].IMUX_BUFPLL_PLLIN[1]	BUFPLL.PLLIN_CMT[1]
CELL[0].IMUX_BUFPLL_LOCKED[0]	BUFPLL.LOCKED[0]
CELL[0].IMUX_BUFPLL_LOCKED[1]	BUFPLL.LOCKED[1]
CELL[2].OUT_BEL[18]	BUFPLL.LOCK[0]
CELL[2].OUT_BEL[19]	BUFPLL.LOCK[1]
CELL[2].IOCLK[0]	BUFIO2[4].IOCLK
CELL[2].IOCLK[1]	BUFIO2[5].IOCLK
CELL[2].IOCLK[2]	BUFIO2[6].IOCLK
CELL[2].IOCLK[3]	BUFIO2[7].IOCLK
CELL[2].IOCE[0]	BUFIO2[4].SERDESSTROBE
CELL[2].IOCE[1]	BUFIO2[5].SERDESSTROBE
CELL[2].IOCE[2]	BUFIO2[6].SERDESSTROBE
CELL[2].IOCE[3]	BUFIO2[7].SERDESSTROBE
CELL[2].IMUX_BUFIO2_I[0]	BUFIO2[4].I
CELL[2].IMUX_BUFIO2_I[1]	BUFIO2[5].I
CELL[2].IMUX_BUFIO2_I[2]	BUFIO2[6].I
CELL[2].IMUX_BUFIO2_I[3]	BUFIO2[7].I
CELL[2].IMUX_BUFIO2_IB[0]	BUFIO2[4].IB
CELL[2].IMUX_BUFIO2_IB[1]	BUFIO2[5].IB
CELL[2].IMUX_BUFIO2_IB[2]	BUFIO2[6].IB
CELL[2].IMUX_BUFIO2_IB[3]	BUFIO2[7].IB
CELL[2].IMUX_BUFIO2FB[0]	BUFIO2FB[4].I
CELL[2].IMUX_BUFIO2FB[1]	BUFIO2FB[5].I
CELL[2].IMUX_BUFIO2FB[2]	BUFIO2FB[6].I
CELL[2].IMUX_BUFIO2FB[3]	BUFIO2FB[7].I
CELL[2].OUT_DIVCLK[0]	BUFIO2[4].DIVCLK
CELL[2].OUT_DIVCLK[1]	BUFIO2[5].DIVCLK
CELL[2].OUT_DIVCLK[2]	BUFIO2[6].DIVCLK
CELL[2].OUT_DIVCLK[3]	BUFIO2[7].DIVCLK

Bitstream

spartan6 CLK_N rect MAIN
Bit	Frame
Bit	F0
B0	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 0
B1	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 1
B2	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 2
B3	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 0
B4	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 1
B5	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 2
B6	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 0
B7	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 1
B8	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 2
B9	BUFIO2[6]: POS_EDGE bit 0
B10	BUFIO2[6]: POS_EDGE bit 1
B11	BUFIO2[6]: POS_EDGE bit 2
B12	BUFIO2[6]: NEG_EDGE bit 0
B13	BUFIO2[6]: NEG_EDGE bit 1
B14	-
B15	BUFIO2[6]: DIVIDE bit 0
B16	BUFIO2[6]: DIVIDE bit 1
B17	BUFIO2[6]: DIVIDE bit 2
B18	BUFIO2[6]: R_EDGE
B19	BUFIO2[6]: ENABLE
B20	BUFIO2[6]: ENABLE_2CLK
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 0
B28	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 1
B29	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 2
B30	-
B31	BUFIO2FB[6]: ENABLE
B32	-
B33	BUFIO2[6]: ! DIVIDE_BYPASS
B34	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 3
B35	CLK_INT: mux CELL[0].DIVCLK_CLKC[6] bit 1
B36	BUFIO2[6]: IOCLK_ENABLE
B37	CLK_INT: mux CELL[0].DIVCLK_CLKC[6] bit 0
B38	BUFIO2[6]: CMT_ENABLE
B39	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 4
B40	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 5
B41	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 6
B42	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 7
B43	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 0
B44	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 1
B45	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 2
B46	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[1] bit 3
B47	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 3
B48	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 0
B49	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 1
B50	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 2
B51	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 0
B52	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 1
B53	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 2
B54	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 0
B55	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 1
B56	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 2
B57	BUFIO2[7]: POS_EDGE bit 0
B58	BUFIO2[7]: POS_EDGE bit 1
B59	BUFIO2[7]: POS_EDGE bit 2
B60	BUFIO2[7]: NEG_EDGE bit 0
B61	BUFIO2[7]: NEG_EDGE bit 1
B62	-
B63	BUFIO2[7]: DIVIDE bit 0
B64	BUFIO2[7]: DIVIDE bit 1
B65	BUFIO2[7]: DIVIDE bit 2
B66	BUFIO2[7]: R_EDGE
B67	BUFIO2[7]: ENABLE
B68	BUFIO2[7]: ENABLE_2CLK
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 0
B76	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 1
B77	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 2
B78	-
B79	BUFIO2FB[7]: ENABLE
B80	-
B81	BUFIO2[7]: ! DIVIDE_BYPASS
B82	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 3
B83	CLK_INT: mux CELL[0].DIVCLK_CLKC[7] bit 1
B84	BUFIO2[7]: IOCLK_ENABLE
B85	CLK_INT: mux CELL[0].DIVCLK_CLKC[7] bit 0
B86	BUFIO2[7]: CMT_ENABLE
B87	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 2
B88	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 1
B89	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 0
B90	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 7
B91	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 6
B92	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 5
B93	CLK_INT: mux CELL[0].IMUX_CLK_GCLK[0] bit 4
B94	-
B95	-
B96	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 0
B97	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 1
B98	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 2
B99	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 0
B100	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 1
B101	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 2
B102	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 0
B103	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 1
B104	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 2
B105	BUFIO2[4]: POS_EDGE bit 0
B106	BUFIO2[4]: POS_EDGE bit 1
B107	BUFIO2[4]: POS_EDGE bit 2
B108	BUFIO2[4]: NEG_EDGE bit 0
B109	BUFIO2[4]: NEG_EDGE bit 1
B110	-
B111	BUFIO2[4]: DIVIDE bit 0
B112	BUFIO2[4]: DIVIDE bit 1
B113	BUFIO2[4]: DIVIDE bit 2
B114	BUFIO2[4]: R_EDGE
B115	BUFIO2[4]: ENABLE
B116	BUFIO2[4]: ENABLE_2CLK
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 0
B124	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 1
B125	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 2
B126	-
B127	BUFIO2FB[4]: ENABLE
B128	-
B129	BUFIO2[4]: ! DIVIDE_BYPASS
B130	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 3
B131	CLK_INT: mux CELL[0].DIVCLK_CLKC[4] bit 1
B132	BUFIO2[4]: IOCLK_ENABLE
B133	CLK_INT: mux CELL[0].DIVCLK_CLKC[4] bit 0
B134	BUFIO2[4]: CMT_ENABLE
B135	BUFPLL: ENABLE
B136	BUFPLL: DIVIDE0 bit 0
B137	BUFPLL: DIVIDE0 bit 1
B138	BUFPLL: DIVIDE0 bit 2
B139	BUFPLL: LOCK_SRC bit 1
B140	BUFPLL: ! ENABLE_SYNC0
B141	BUFPLL: DATA_RATE0 bit 0
B142	BUFPLL: DIVIDE1 bit 0
B143	BUFPLL: DIVIDE1 bit 1
B144	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 0
B145	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 1
B146	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 2
B147	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 0
B148	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 1
B149	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 2
B150	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 0
B151	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 1
B152	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 2
B153	BUFIO2[5]: POS_EDGE bit 0
B154	BUFIO2[5]: POS_EDGE bit 1
B155	BUFIO2[5]: POS_EDGE bit 2
B156	BUFIO2[5]: NEG_EDGE bit 0
B157	BUFIO2[5]: NEG_EDGE bit 1
B158	-
B159	BUFIO2[5]: DIVIDE bit 0
B160	BUFIO2[5]: DIVIDE bit 1
B161	BUFIO2[5]: DIVIDE bit 2
B162	BUFIO2[5]: R_EDGE
B163	BUFIO2[5]: ENABLE
B164	BUFIO2[5]: ENABLE_2CLK
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 0
B172	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 1
B173	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 2
B174	-
B175	BUFIO2FB[5]: ENABLE
B176	-
B177	BUFIO2[5]: ! DIVIDE_BYPASS
B178	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 3
B179	CLK_INT: mux CELL[0].DIVCLK_CLKC[5] bit 1
B180	BUFIO2[5]: IOCLK_ENABLE
B181	CLK_INT: mux CELL[0].DIVCLK_CLKC[5] bit 0
B182	BUFIO2[5]: CMT_ENABLE
B183	BUFPLL: DIVIDE1 bit 2
B184	BUFPLL: LOCK_SRC bit 0
B185	BUFPLL: ! ENABLE_SYNC1
B186	BUFPLL: DATA_RATE1 bit 0
B187	BUFPLL: DIVIDE0 bit 3
B188	-
B189	BUFPLL: DIVIDE0 bit 4
B190	BUFPLL: DIVIDE0 bit 5
B191	BUFPLL: DIVIDE1 bit 3
B192	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[2] bit 0
B193	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[2] bit 1
B194	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[2] bit 2
B195	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[2] bit 0
B196	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[2] bit 1
B197	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[2] bit 2
B198	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[2] bit 0
B199	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[2] bit 1
B200	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[2] bit 2
B201	BUFIO2[2]: POS_EDGE bit 0
B202	BUFIO2[2]: POS_EDGE bit 1
B203	BUFIO2[2]: POS_EDGE bit 2
B204	BUFIO2[2]: NEG_EDGE bit 0
B205	BUFIO2[2]: NEG_EDGE bit 1
B206	-
B207	BUFIO2[2]: DIVIDE bit 0
B208	BUFIO2[2]: DIVIDE bit 1
B209	BUFIO2[2]: DIVIDE bit 2
B210	BUFIO2[2]: R_EDGE
B211	BUFIO2[2]: ENABLE
B212	BUFIO2[2]: ENABLE_2CLK
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 0
B220	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 1
B221	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 2
B222	-
B223	BUFIO2FB[2]: ENABLE
B224	-
B225	BUFIO2[2]: ! DIVIDE_BYPASS
B226	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 3
B227	CLK_INT: mux CELL[0].DIVCLK_CLKC[2] bit 1
B228	BUFIO2[2]: IOCLK_ENABLE
B229	CLK_INT: mux CELL[0].DIVCLK_CLKC[2] bit 0
B230	BUFIO2[2]: CMT_ENABLE
B231	-
B232	BUFPLL: DIVIDE1 bit 4
B233	BUFPLL: DIVIDE1 bit 5
B234	BUFPLL: ENABLE_BOTH_SYNC0 bit 0
B235	-
B236	-
B237	BUFPLL: ENABLE_BOTH_SYNC1 bit 0
B238	-
B239	-
B240	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[3] bit 0
B241	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[3] bit 1
B242	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[3] bit 2
B243	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[3] bit 0
B244	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[3] bit 1
B245	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[3] bit 2
B246	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[3] bit 0
B247	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[3] bit 1
B248	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[3] bit 2
B249	BUFIO2[3]: POS_EDGE bit 0
B250	BUFIO2[3]: POS_EDGE bit 1
B251	BUFIO2[3]: POS_EDGE bit 2
B252	BUFIO2[3]: NEG_EDGE bit 0
B253	BUFIO2[3]: NEG_EDGE bit 1
B254	-
B255	BUFIO2[3]: DIVIDE bit 0
B256	BUFIO2[3]: DIVIDE bit 1
B257	BUFIO2[3]: DIVIDE bit 2
B258	BUFIO2[3]: R_EDGE
B259	BUFIO2[3]: ENABLE
B260	BUFIO2[3]: ENABLE_2CLK
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 0
B268	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 1
B269	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 2
B270	-
B271	BUFIO2FB[3]: ENABLE
B272	-
B273	BUFIO2[3]: ! DIVIDE_BYPASS
B274	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 3
B275	CLK_INT: mux CELL[0].DIVCLK_CLKC[3] bit 1
B276	BUFIO2[3]: IOCLK_ENABLE
B277	CLK_INT: mux CELL[0].DIVCLK_CLKC[3] bit 0
B278	BUFIO2[3]: CMT_ENABLE
B279	BUFPLL: ENABLE_NONE_SYNC0 bit 0
B280	BUFPLL: ENABLE_BOTH_SYNC0 bit 1
B281	BUFPLL: ENABLE_NONE_SYNC1 bit 0
B282	BUFPLL: ENABLE_BOTH_SYNC1 bit 1
B283	-
B284	-
B285	BUFPLL: ENABLE_NONE_SYNC0 bit 1
B286	BUFPLL: ENABLE_BOTH_SYNC0 bit 2
B287	-
B288	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[0] bit 0
B289	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[0] bit 1
B290	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[0] bit 2
B291	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[0] bit 0
B292	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[0] bit 1
B293	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[0] bit 2
B294	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[0] bit 0
B295	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[0] bit 1
B296	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[0] bit 2
B297	BUFIO2[0]: POS_EDGE bit 0
B298	BUFIO2[0]: POS_EDGE bit 1
B299	BUFIO2[0]: POS_EDGE bit 2
B300	BUFIO2[0]: NEG_EDGE bit 0
B301	BUFIO2[0]: NEG_EDGE bit 1
B302	-
B303	BUFIO2[0]: DIVIDE bit 0
B304	BUFIO2[0]: DIVIDE bit 1
B305	BUFIO2[0]: DIVIDE bit 2
B306	BUFIO2[0]: R_EDGE
B307	BUFIO2[0]: ENABLE
B308	BUFIO2[0]: ENABLE_2CLK
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 0
B316	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 1
B317	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 2
B318	-
B319	BUFIO2FB[0]: ENABLE
B320	-
B321	BUFIO2[0]: ! DIVIDE_BYPASS
B322	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 3
B323	CLK_INT: mux CELL[0].DIVCLK_CLKC[0] bit 1
B324	BUFIO2[0]: IOCLK_ENABLE
B325	CLK_INT: mux CELL[0].DIVCLK_CLKC[0] bit 0
B326	BUFIO2[0]: CMT_ENABLE
B327	-
B328	BUFPLL: ENABLE_NONE_SYNC1 bit 1
B329	BUFPLL: ENABLE_BOTH_SYNC1 bit 2
B330	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[0] bit 0
B331	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[0] bit 1
B332	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[0] bit 2
B333	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[1] bit 0
B334	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[1] bit 1
B335	CLK_INT: mux CELL[0].IMUX_BUFPLL_PLLIN[1] bit 2
B336	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[1] bit 0
B337	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[1] bit 1
B338	CLK_INT: mux CELL[0].IMUX_BUFIO2_I[1] bit 2
B339	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[1] bit 0
B340	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[1] bit 1
B341	CLK_INT: mux CELL[0].IMUX_BUFIO2_IB[1] bit 2
B342	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[1] bit 0
B343	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[1] bit 1
B344	CLK_INT: mux CELL[0].IMUX_BUFIO2FB[1] bit 2
B345	BUFIO2[1]: POS_EDGE bit 0
B346	BUFIO2[1]: POS_EDGE bit 1
B347	BUFIO2[1]: POS_EDGE bit 2
B348	BUFIO2[1]: NEG_EDGE bit 0
B349	BUFIO2[1]: NEG_EDGE bit 1
B350	-
B351	BUFIO2[1]: DIVIDE bit 0
B352	BUFIO2[1]: DIVIDE bit 1
B353	BUFIO2[1]: DIVIDE bit 2
B354	BUFIO2[1]: R_EDGE
B355	BUFIO2[1]: ENABLE
B356	BUFIO2[1]: ENABLE_2CLK
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 0
B364	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 1
B365	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 2
B366	-
B367	BUFIO2FB[1]: ENABLE
B368	-
B369	BUFIO2[1]: ! DIVIDE_BYPASS
B370	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 3
B371	CLK_INT: mux CELL[0].DIVCLK_CLKC[1] bit 1
B372	BUFIO2[1]: IOCLK_ENABLE
B373	CLK_INT: mux CELL[0].DIVCLK_CLKC[1] bit 0
B374	BUFIO2[1]: CMT_ENABLE
B375	CLK_INT: mux CELL[0].IMUX_BUFPLL_LOCKED[0] bit 0
B376	CLK_INT: mux CELL[0].IMUX_BUFPLL_LOCKED[0] bit 1
B377	CLK_INT: mux CELL[0].IMUX_BUFPLL_LOCKED[1] bit 0
B378	CLK_INT: mux CELL[0].IMUX_BUFPLL_LOCKED[1] bit 1
B379	MISR_CLK: ENABLE
B380	MISR_CLK: RESET
B381	-
B382	-
B383	-

Tile CLK_W

Cells: 6

Switchbox CLK_INT

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_I[0]
Bits			Destination
MAIN[0][290]	MAIN[0][289]	MAIN[0][288]	CELL[1].IMUX_BUFIO2_I[0]	-
MAIN[0][98]	MAIN[0][97]	MAIN[0][96]	-	CELL[2].IMUX_BUFIO2_I[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[4].OUT_CLKPAD_DQSP
1	0	0	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[4].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[0]	CELL[2].GTPCLK[0]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_I[1]
Bits			Destination
MAIN[0][338]	MAIN[0][337]	MAIN[0][336]	CELL[1].IMUX_BUFIO2_I[1]	-
MAIN[0][146]	MAIN[0][145]	MAIN[0][144]	-	CELL[2].IMUX_BUFIO2_I[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[4].OUT_CLKPAD_DQSN
1	0	0	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[4].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[1]	CELL[2].GTPCLK[1]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_I[2]
Bits			Destination
MAIN[0][194]	MAIN[0][193]	MAIN[0][192]	CELL[1].IMUX_BUFIO2_I[2]	-
MAIN[0][2]	MAIN[0][1]	MAIN[0][0]	-	CELL[2].IMUX_BUFIO2_I[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[5].OUT_CLKPAD_DQSP
1	0	0	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[5].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[2]	CELL[2].GTPCLK[2]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_I[3]
Bits			Destination
MAIN[0][242]	MAIN[0][241]	MAIN[0][240]	CELL[1].IMUX_BUFIO2_I[3]	-
MAIN[0][50]	MAIN[0][49]	MAIN[0][48]	-	CELL[2].IMUX_BUFIO2_I[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[5].OUT_CLKPAD_DQSN
1	0	0	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[5].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[3]	CELL[2].GTPCLK[3]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_IB[0]
Bits			Destination
MAIN[0][293]	MAIN[0][292]	MAIN[0][291]	CELL[1].IMUX_BUFIO2_IB[0]	-
MAIN[0][101]	MAIN[0][100]	MAIN[0][99]	-	CELL[2].IMUX_BUFIO2_IB[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[4].OUT_CLKPAD_DQSN
1	0	0	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[4].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_IB[1]
Bits			Destination
MAIN[0][341]	MAIN[0][340]	MAIN[0][339]	CELL[1].IMUX_BUFIO2_IB[1]	-
MAIN[0][149]	MAIN[0][148]	MAIN[0][147]	-	CELL[2].IMUX_BUFIO2_IB[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[4].OUT_CLKPAD_DQSP
1	0	0	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[4].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_IB[2]
Bits			Destination
MAIN[0][197]	MAIN[0][196]	MAIN[0][195]	CELL[1].IMUX_BUFIO2_IB[2]	-
MAIN[0][5]	MAIN[0][4]	MAIN[0][3]	-	CELL[2].IMUX_BUFIO2_IB[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[5].OUT_CLKPAD_DQSN
1	0	0	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[5].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2_IB[3]
Bits			Destination
MAIN[0][245]	MAIN[0][244]	MAIN[0][243]	CELL[1].IMUX_BUFIO2_IB[3]	-
MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	-	CELL[2].IMUX_BUFIO2_IB[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[5].OUT_CLKPAD_DQSP
1	0	0	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[5].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2FB[0]
Bits			Destination
MAIN[0][296]	MAIN[0][295]	MAIN[0][294]	CELL[1].IMUX_BUFIO2FB[0]	-
MAIN[0][104]	MAIN[0][103]	MAIN[0][102]	-	CELL[2].IMUX_BUFIO2FB[0]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[1]	CELL[4].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[1]	CELL[4].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[0]	CELL[2].GTPFB[0]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2FB[1]
Bits			Destination
MAIN[0][344]	MAIN[0][343]	MAIN[0][342]	CELL[1].IMUX_BUFIO2FB[1]	-
MAIN[0][152]	MAIN[0][151]	MAIN[0][150]	-	CELL[2].IMUX_BUFIO2FB[1]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[0]	CELL[4].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[0]	CELL[4].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[1]	CELL[2].GTPFB[1]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2FB[2]
Bits			Destination
MAIN[0][200]	MAIN[0][199]	MAIN[0][198]	CELL[1].IMUX_BUFIO2FB[2]	-
MAIN[0][8]	MAIN[0][7]	MAIN[0][6]	-	CELL[2].IMUX_BUFIO2FB[2]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[1]	CELL[5].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[1]	CELL[5].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[2]	CELL[2].GTPFB[2]

spartan6 CLK_W switchbox CLK_INT muxes IMUX_BUFIO2FB[3]
Bits			Destination
MAIN[0][248]	MAIN[0][247]	MAIN[0][246]	CELL[1].IMUX_BUFIO2FB[3]	-
MAIN[0][56]	MAIN[0][55]	MAIN[0][54]	-	CELL[2].IMUX_BUFIO2FB[3]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[0]	CELL[5].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[0]	CELL[5].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[3]	CELL[2].GTPFB[3]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[0]
Bits		Destination
MAIN[0][323]	MAIN[0][325]	CELL[2].DIVCLK_CLKC[0]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[0]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[1]
Bits		Destination
MAIN[0][371]	MAIN[0][373]	CELL[2].DIVCLK_CLKC[1]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[1]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[2]
Bits		Destination
MAIN[0][227]	MAIN[0][229]	CELL[2].DIVCLK_CLKC[2]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[2]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[3]
Bits		Destination
MAIN[0][275]	MAIN[0][277]	CELL[2].DIVCLK_CLKC[3]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[3]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[4]
Bits		Destination
MAIN[0][131]	MAIN[0][133]	CELL[2].DIVCLK_CLKC[4]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[4].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[0]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[5]
Bits		Destination
MAIN[0][179]	MAIN[0][181]	CELL[2].DIVCLK_CLKC[5]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[4].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[1]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[6]
Bits		Destination
MAIN[0][35]	MAIN[0][37]	CELL[2].DIVCLK_CLKC[6]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[5].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[2]

spartan6 CLK_W switchbox CLK_INT muxes DIVCLK_CLKC[7]
Bits		Destination
MAIN[0][83]	MAIN[0][85]	CELL[2].DIVCLK_CLKC[7]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[5].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[3]

Bels BUFIO2

spartan6 CLK_W bel BUFIO2 pins
Pin	Direction	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
I	in	CELL[1].IMUX_BUFIO2_I[0]	CELL[1].IMUX_BUFIO2_I[1]	CELL[1].IMUX_BUFIO2_I[2]	CELL[1].IMUX_BUFIO2_I[3]	CELL[2].IMUX_BUFIO2_I[0]	CELL[2].IMUX_BUFIO2_I[1]	CELL[2].IMUX_BUFIO2_I[2]	CELL[2].IMUX_BUFIO2_I[3]
IB	in	CELL[1].IMUX_BUFIO2_IB[0]	CELL[1].IMUX_BUFIO2_IB[1]	CELL[1].IMUX_BUFIO2_IB[2]	CELL[1].IMUX_BUFIO2_IB[3]	CELL[2].IMUX_BUFIO2_IB[0]	CELL[2].IMUX_BUFIO2_IB[1]	CELL[2].IMUX_BUFIO2_IB[2]	CELL[2].IMUX_BUFIO2_IB[3]
DIVCLK	out	CELL[1].OUT_DIVCLK[0]	CELL[1].OUT_DIVCLK[1]	CELL[1].OUT_DIVCLK[2]	CELL[1].OUT_DIVCLK[3]	CELL[2].OUT_DIVCLK[0]	CELL[2].OUT_DIVCLK[1]	CELL[2].OUT_DIVCLK[2]	CELL[2].OUT_DIVCLK[3]
DIVCLK_CMT	out	CELL[1].DIVCLK_CMT_W[0]	CELL[1].DIVCLK_CMT_W[1]	CELL[1].DIVCLK_CMT_W[2]	CELL[1].DIVCLK_CMT_W[3]	CELL[2].DIVCLK_CMT_W[0]	CELL[2].DIVCLK_CMT_W[1]	CELL[2].DIVCLK_CMT_W[2]	CELL[2].DIVCLK_CMT_W[3]
IOCLK	out	CELL[1].IOCLK[0]	CELL[1].IOCLK[1]	CELL[1].IOCLK[2]	CELL[1].IOCLK[3]	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]
SERDESSTROBE	out	CELL[1].IOCE[0]	CELL[1].IOCE[1]	CELL[1].IOCE[2]	CELL[1].IOCE[3]	CELL[2].IOCE[0]	CELL[2].IOCE[1]	CELL[2].IOCE[2]	CELL[2].IOCE[3]

spartan6 CLK_W bel BUFIO2 attribute bits
Attribute	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
ENABLE	MAIN[0][307]	MAIN[0][355]	MAIN[0][211]	MAIN[0][259]	MAIN[0][115]	MAIN[0][163]	MAIN[0][19]	MAIN[0][67]
ENABLE_2CLK	MAIN[0][308]	MAIN[0][356]	MAIN[0][212]	MAIN[0][260]	MAIN[0][116]	MAIN[0][164]	MAIN[0][20]	MAIN[0][68]
CMT_ENABLE	MAIN[0][326]	MAIN[0][374]	MAIN[0][230]	MAIN[0][278]	MAIN[0][134]	MAIN[0][182]	MAIN[0][38]	MAIN[0][86]
IOCLK_ENABLE	MAIN[0][324]	MAIN[0][372]	MAIN[0][228]	MAIN[0][276]	MAIN[0][132]	MAIN[0][180]	MAIN[0][36]	MAIN[0][84]
DIVIDE	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]
DIVIDE_BYPASS	!MAIN[0][321]	!MAIN[0][369]	!MAIN[0][225]	!MAIN[0][273]	!MAIN[0][129]	!MAIN[0][177]	!MAIN[0][33]	!MAIN[0][81]
R_EDGE	MAIN[0][306]	MAIN[0][354]	MAIN[0][210]	MAIN[0][258]	MAIN[0][114]	MAIN[0][162]	MAIN[0][18]	MAIN[0][66]
POS_EDGE bit 0	MAIN[0][297]	MAIN[0][345]	MAIN[0][201]	MAIN[0][249]	MAIN[0][105]	MAIN[0][153]	MAIN[0][9]	MAIN[0][57]
POS_EDGE bit 1	MAIN[0][298]	MAIN[0][346]	MAIN[0][202]	MAIN[0][250]	MAIN[0][106]	MAIN[0][154]	MAIN[0][10]	MAIN[0][58]
POS_EDGE bit 2	MAIN[0][299]	MAIN[0][347]	MAIN[0][203]	MAIN[0][251]	MAIN[0][107]	MAIN[0][155]	MAIN[0][11]	MAIN[0][59]
NEG_EDGE bit 0	MAIN[0][300]	MAIN[0][348]	MAIN[0][204]	MAIN[0][252]	MAIN[0][108]	MAIN[0][156]	MAIN[0][12]	MAIN[0][60]
NEG_EDGE bit 1	MAIN[0][301]	MAIN[0][349]	MAIN[0][205]	MAIN[0][253]	MAIN[0][109]	MAIN[0][157]	MAIN[0][13]	MAIN[0][61]

spartan6 CLK_W enum BUFIO2_DIVIDE
BUFIO2[0].DIVIDE	MAIN[0][305]	MAIN[0][304]	MAIN[0][303]
BUFIO2[1].DIVIDE	MAIN[0][353]	MAIN[0][352]	MAIN[0][351]
BUFIO2[2].DIVIDE	MAIN[0][209]	MAIN[0][208]	MAIN[0][207]
BUFIO2[3].DIVIDE	MAIN[0][257]	MAIN[0][256]	MAIN[0][255]
BUFIO2[4].DIVIDE	MAIN[0][113]	MAIN[0][112]	MAIN[0][111]
BUFIO2[5].DIVIDE	MAIN[0][161]	MAIN[0][160]	MAIN[0][159]
BUFIO2[6].DIVIDE	MAIN[0][17]	MAIN[0][16]	MAIN[0][15]
BUFIO2[7].DIVIDE	MAIN[0][65]	MAIN[0][64]	MAIN[0][63]
_1	1	1	1
_2	0	0	0
_3	0	0	1
_4	0	1	0
_5	0	1	1
_6	1	0	0
_7	1	0	1
_8	1	1	0

Bels BUFIO2FB

spartan6 CLK_W bel BUFIO2FB pins
Pin	Direction	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
I	in	CELL[1].IMUX_BUFIO2FB[0]	CELL[1].IMUX_BUFIO2FB[1]	CELL[1].IMUX_BUFIO2FB[2]	CELL[1].IMUX_BUFIO2FB[3]	CELL[2].IMUX_BUFIO2FB[0]	CELL[2].IMUX_BUFIO2FB[1]	CELL[2].IMUX_BUFIO2FB[2]	CELL[2].IMUX_BUFIO2FB[3]
O	out	CELL[1].IOFBCLK_CMT_W[0]	CELL[1].IOFBCLK_CMT_W[1]	CELL[1].IOFBCLK_CMT_W[2]	CELL[1].IOFBCLK_CMT_W[3]	CELL[2].IOFBCLK_CMT_W[0]	CELL[2].IOFBCLK_CMT_W[1]	CELL[2].IOFBCLK_CMT_W[2]	CELL[2].IOFBCLK_CMT_W[3]

spartan6 CLK_W bel BUFIO2FB attribute bits
Attribute	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
ENABLE	MAIN[0][319]	MAIN[0][367]	MAIN[0][223]	MAIN[0][271]	MAIN[0][127]	MAIN[0][175]	MAIN[0][31]	MAIN[0][79]
DIVIDE_BYPASS bit 0	!MAIN[0][315]	!MAIN[0][363]	!MAIN[0][219]	!MAIN[0][267]	!MAIN[0][123]	!MAIN[0][171]	!MAIN[0][27]	!MAIN[0][75]
DIVIDE_BYPASS bit 1	!MAIN[0][316]	!MAIN[0][364]	!MAIN[0][220]	!MAIN[0][268]	!MAIN[0][124]	!MAIN[0][172]	!MAIN[0][28]	!MAIN[0][76]
DIVIDE_BYPASS bit 2	!MAIN[0][317]	!MAIN[0][365]	!MAIN[0][221]	!MAIN[0][269]	!MAIN[0][125]	!MAIN[0][173]	!MAIN[0][29]	!MAIN[0][77]
DIVIDE_BYPASS bit 3	!MAIN[0][322]	!MAIN[0][370]	!MAIN[0][226]	!MAIN[0][274]	!MAIN[0][130]	!MAIN[0][178]	!MAIN[0][34]	!MAIN[0][82]

Bels BUFPLL

spartan6 CLK_W bel BUFPLL pins
Pin	Direction	BUFPLL
GCLK[0]	in	CELL[2].IMUX_CLK[0]
GCLK[1]	in	CELL[2].IMUX_CLK[1]
PLLIN_CMT[0]	in	CELL[2].CMT_BUFPLL_H_CLKOUT[0]
PLLIN_CMT[1]	in	CELL[2].CMT_BUFPLL_H_CLKOUT[1]
PLLIN_GCLK[0]	in	CELL[3].IMUX_CLK[0]
PLLIN_GCLK[1]	in	CELL[3].IMUX_CLK[1]
LOCKED[0]	in	CELL[2].CMT_BUFPLL_H_LOCKED[0]
LOCKED[1]	in	CELL[2].CMT_BUFPLL_H_LOCKED[1]
PLLCLK[0]	out	CELL[2].PLLCLK[0]
PLLCLK[1]	out	CELL[2].PLLCLK[1]
PLLCE[0]	out	CELL[2].PLLCE[0]
PLLCE[1]	out	CELL[2].PLLCE[1]
LOCK[0]	out	CELL[2].OUT_BEL[0]
LOCK[1]	out	CELL[2].OUT_BEL[1]

spartan6 CLK_W bel BUFPLL attribute bits
Attribute	BUFPLL
ENABLE	MAIN[0][135]
MUX_PLLIN	[enum: BUFPLL_MUX_PLLIN]
LOCK_SRC	[enum: BUFPLL_LOCK_SRC]
DATA_RATE0	[enum: BUFPLL_DATA_RATE]
DATA_RATE1	[enum: BUFPLL_DATA_RATE]
DIVIDE0	[enum: BUFIO2_DIVIDE]
DIVIDE1	[enum: BUFIO2_DIVIDE]
ENABLE_BOTH_SYNC0 bit 0	MAIN[0][234]
ENABLE_BOTH_SYNC0 bit 1	MAIN[0][280]
ENABLE_BOTH_SYNC0 bit 2	MAIN[0][286]
ENABLE_BOTH_SYNC1 bit 0	MAIN[0][237]
ENABLE_BOTH_SYNC1 bit 1	MAIN[0][282]
ENABLE_BOTH_SYNC1 bit 2	MAIN[0][329]
ENABLE_NONE_SYNC0 bit 0	MAIN[0][279]
ENABLE_NONE_SYNC0 bit 1	MAIN[0][285]
ENABLE_NONE_SYNC1 bit 0	MAIN[0][281]
ENABLE_NONE_SYNC1 bit 1	MAIN[0][328]
ENABLE_SYNC0	!MAIN[0][140]
ENABLE_SYNC1	!MAIN[0][185]

spartan6 CLK_W enum BUFPLL_MUX_PLLIN
BUFPLL.MUX_PLLIN	MAIN[0][330]
CMT	0
GCLK	1

spartan6 CLK_W enum BUFPLL_LOCK_SRC
BUFPLL.LOCK_SRC	MAIN[0][139]	MAIN[0][184]
NONE	0	0
LOCK_TO_0	0	1
LOCK_TO_1	1	0

spartan6 CLK_W enum BUFPLL_DATA_RATE
BUFPLL.DATA_RATE0	MAIN[0][141]
BUFPLL.DATA_RATE1	MAIN[0][186]
SDR	0
DDR	1

spartan6 CLK_W enum BUFIO2_DIVIDE
BUFPLL.DIVIDE0	MAIN[0][190]	MAIN[0][189]	MAIN[0][187]	MAIN[0][138]	MAIN[0][137]	MAIN[0][136]
BUFPLL.DIVIDE1	MAIN[0][233]	MAIN[0][232]	MAIN[0][191]	MAIN[0][183]	MAIN[0][143]	MAIN[0][142]
_1	1	1	0	1	1	1
_2	0	0	1	0	0	0
_3	0	0	0	0	0	1
_4	0	1	1	0	1	0
_5	0	1	0	0	1	1
_6	1	0	1	1	0	0
_7	1	0	0	1	0	1
_8	1	1	1	1	1	0

Bel wires

spartan6 CLK_W bel wires
Wire	Pins
CELL[1].IOCLK[0]	BUFIO2[0].IOCLK
CELL[1].IOCLK[1]	BUFIO2[1].IOCLK
CELL[1].IOCLK[2]	BUFIO2[2].IOCLK
CELL[1].IOCLK[3]	BUFIO2[3].IOCLK
CELL[1].IOCE[0]	BUFIO2[0].SERDESSTROBE
CELL[1].IOCE[1]	BUFIO2[1].SERDESSTROBE
CELL[1].IOCE[2]	BUFIO2[2].SERDESSTROBE
CELL[1].IOCE[3]	BUFIO2[3].SERDESSTROBE
CELL[1].IMUX_BUFIO2_I[0]	BUFIO2[0].I
CELL[1].IMUX_BUFIO2_I[1]	BUFIO2[1].I
CELL[1].IMUX_BUFIO2_I[2]	BUFIO2[2].I
CELL[1].IMUX_BUFIO2_I[3]	BUFIO2[3].I
CELL[1].IMUX_BUFIO2_IB[0]	BUFIO2[0].IB
CELL[1].IMUX_BUFIO2_IB[1]	BUFIO2[1].IB
CELL[1].IMUX_BUFIO2_IB[2]	BUFIO2[2].IB
CELL[1].IMUX_BUFIO2_IB[3]	BUFIO2[3].IB
CELL[1].IMUX_BUFIO2FB[0]	BUFIO2FB[0].I
CELL[1].IMUX_BUFIO2FB[1]	BUFIO2FB[1].I
CELL[1].IMUX_BUFIO2FB[2]	BUFIO2FB[2].I
CELL[1].IMUX_BUFIO2FB[3]	BUFIO2FB[3].I
CELL[1].OUT_DIVCLK[0]	BUFIO2[0].DIVCLK
CELL[1].OUT_DIVCLK[1]	BUFIO2[1].DIVCLK
CELL[1].OUT_DIVCLK[2]	BUFIO2[2].DIVCLK
CELL[1].OUT_DIVCLK[3]	BUFIO2[3].DIVCLK
CELL[1].DIVCLK_CMT_W[0]	BUFIO2[0].DIVCLK_CMT
CELL[1].DIVCLK_CMT_W[1]	BUFIO2[1].DIVCLK_CMT
CELL[1].DIVCLK_CMT_W[2]	BUFIO2[2].DIVCLK_CMT
CELL[1].DIVCLK_CMT_W[3]	BUFIO2[3].DIVCLK_CMT
CELL[1].IOFBCLK_CMT_W[0]	BUFIO2FB[0].O
CELL[1].IOFBCLK_CMT_W[1]	BUFIO2FB[1].O
CELL[1].IOFBCLK_CMT_W[2]	BUFIO2FB[2].O
CELL[1].IOFBCLK_CMT_W[3]	BUFIO2FB[3].O
CELL[2].IMUX_CLK[0]	BUFPLL.GCLK[0]
CELL[2].IMUX_CLK[1]	BUFPLL.GCLK[1]
CELL[2].OUT_BEL[0]	BUFPLL.LOCK[0]
CELL[2].OUT_BEL[1]	BUFPLL.LOCK[1]
CELL[2].IOCLK[0]	BUFIO2[4].IOCLK
CELL[2].IOCLK[1]	BUFIO2[5].IOCLK
CELL[2].IOCLK[2]	BUFIO2[6].IOCLK
CELL[2].IOCLK[3]	BUFIO2[7].IOCLK
CELL[2].IOCE[0]	BUFIO2[4].SERDESSTROBE
CELL[2].IOCE[1]	BUFIO2[5].SERDESSTROBE
CELL[2].IOCE[2]	BUFIO2[6].SERDESSTROBE
CELL[2].IOCE[3]	BUFIO2[7].SERDESSTROBE
CELL[2].PLLCLK[0]	BUFPLL.PLLCLK[0]
CELL[2].PLLCLK[1]	BUFPLL.PLLCLK[1]
CELL[2].PLLCE[0]	BUFPLL.PLLCE[0]
CELL[2].PLLCE[1]	BUFPLL.PLLCE[1]
CELL[2].IMUX_BUFIO2_I[0]	BUFIO2[4].I
CELL[2].IMUX_BUFIO2_I[1]	BUFIO2[5].I
CELL[2].IMUX_BUFIO2_I[2]	BUFIO2[6].I
CELL[2].IMUX_BUFIO2_I[3]	BUFIO2[7].I
CELL[2].IMUX_BUFIO2_IB[0]	BUFIO2[4].IB
CELL[2].IMUX_BUFIO2_IB[1]	BUFIO2[5].IB
CELL[2].IMUX_BUFIO2_IB[2]	BUFIO2[6].IB
CELL[2].IMUX_BUFIO2_IB[3]	BUFIO2[7].IB
CELL[2].IMUX_BUFIO2FB[0]	BUFIO2FB[4].I
CELL[2].IMUX_BUFIO2FB[1]	BUFIO2FB[5].I
CELL[2].IMUX_BUFIO2FB[2]	BUFIO2FB[6].I
CELL[2].IMUX_BUFIO2FB[3]	BUFIO2FB[7].I
CELL[2].OUT_DIVCLK[0]	BUFIO2[4].DIVCLK
CELL[2].OUT_DIVCLK[1]	BUFIO2[5].DIVCLK
CELL[2].OUT_DIVCLK[2]	BUFIO2[6].DIVCLK
CELL[2].OUT_DIVCLK[3]	BUFIO2[7].DIVCLK
CELL[2].DIVCLK_CMT_W[0]	BUFIO2[4].DIVCLK_CMT
CELL[2].DIVCLK_CMT_W[1]	BUFIO2[5].DIVCLK_CMT
CELL[2].DIVCLK_CMT_W[2]	BUFIO2[6].DIVCLK_CMT
CELL[2].DIVCLK_CMT_W[3]	BUFIO2[7].DIVCLK_CMT
CELL[2].IOFBCLK_CMT_W[0]	BUFIO2FB[4].O
CELL[2].IOFBCLK_CMT_W[1]	BUFIO2FB[5].O
CELL[2].IOFBCLK_CMT_W[2]	BUFIO2FB[6].O
CELL[2].IOFBCLK_CMT_W[3]	BUFIO2FB[7].O
CELL[2].CMT_BUFPLL_H_CLKOUT[0]	BUFPLL.PLLIN_CMT[0]
CELL[2].CMT_BUFPLL_H_CLKOUT[1]	BUFPLL.PLLIN_CMT[1]
CELL[2].CMT_BUFPLL_H_LOCKED[0]	BUFPLL.LOCKED[0]
CELL[2].CMT_BUFPLL_H_LOCKED[1]	BUFPLL.LOCKED[1]
CELL[3].IMUX_CLK[0]	BUFPLL.PLLIN_GCLK[0]
CELL[3].IMUX_CLK[1]	BUFPLL.PLLIN_GCLK[1]

Bitstream

spartan6 CLK_W rect MAIN
Bit	Frame
Bit	F0
B0	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 0
B1	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 1
B2	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 2
B3	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 0
B4	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 1
B5	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 2
B6	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 0
B7	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 1
B8	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 2
B9	BUFIO2[6]: POS_EDGE bit 0
B10	BUFIO2[6]: POS_EDGE bit 1
B11	BUFIO2[6]: POS_EDGE bit 2
B12	BUFIO2[6]: NEG_EDGE bit 0
B13	BUFIO2[6]: NEG_EDGE bit 1
B14	-
B15	BUFIO2[6]: DIVIDE bit 0
B16	BUFIO2[6]: DIVIDE bit 1
B17	BUFIO2[6]: DIVIDE bit 2
B18	BUFIO2[6]: R_EDGE
B19	BUFIO2[6]: ENABLE
B20	BUFIO2[6]: ENABLE_2CLK
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 0
B28	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 1
B29	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 2
B30	-
B31	BUFIO2FB[6]: ENABLE
B32	-
B33	BUFIO2[6]: ! DIVIDE_BYPASS
B34	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 3
B35	CLK_INT: mux CELL[2].DIVCLK_CLKC[6] bit 1
B36	BUFIO2[6]: IOCLK_ENABLE
B37	CLK_INT: mux CELL[2].DIVCLK_CLKC[6] bit 0
B38	BUFIO2[6]: CMT_ENABLE
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 0
B49	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 1
B50	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 2
B51	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 0
B52	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 1
B53	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 2
B54	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 0
B55	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 1
B56	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 2
B57	BUFIO2[7]: POS_EDGE bit 0
B58	BUFIO2[7]: POS_EDGE bit 1
B59	BUFIO2[7]: POS_EDGE bit 2
B60	BUFIO2[7]: NEG_EDGE bit 0
B61	BUFIO2[7]: NEG_EDGE bit 1
B62	-
B63	BUFIO2[7]: DIVIDE bit 0
B64	BUFIO2[7]: DIVIDE bit 1
B65	BUFIO2[7]: DIVIDE bit 2
B66	BUFIO2[7]: R_EDGE
B67	BUFIO2[7]: ENABLE
B68	BUFIO2[7]: ENABLE_2CLK
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 0
B76	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 1
B77	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 2
B78	-
B79	BUFIO2FB[7]: ENABLE
B80	-
B81	BUFIO2[7]: ! DIVIDE_BYPASS
B82	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 3
B83	CLK_INT: mux CELL[2].DIVCLK_CLKC[7] bit 1
B84	BUFIO2[7]: IOCLK_ENABLE
B85	CLK_INT: mux CELL[2].DIVCLK_CLKC[7] bit 0
B86	BUFIO2[7]: CMT_ENABLE
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 0
B97	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 1
B98	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 2
B99	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 0
B100	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 1
B101	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 2
B102	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 0
B103	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 1
B104	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 2
B105	BUFIO2[4]: POS_EDGE bit 0
B106	BUFIO2[4]: POS_EDGE bit 1
B107	BUFIO2[4]: POS_EDGE bit 2
B108	BUFIO2[4]: NEG_EDGE bit 0
B109	BUFIO2[4]: NEG_EDGE bit 1
B110	-
B111	BUFIO2[4]: DIVIDE bit 0
B112	BUFIO2[4]: DIVIDE bit 1
B113	BUFIO2[4]: DIVIDE bit 2
B114	BUFIO2[4]: R_EDGE
B115	BUFIO2[4]: ENABLE
B116	BUFIO2[4]: ENABLE_2CLK
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 0
B124	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 1
B125	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 2
B126	-
B127	BUFIO2FB[4]: ENABLE
B128	-
B129	BUFIO2[4]: ! DIVIDE_BYPASS
B130	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 3
B131	CLK_INT: mux CELL[2].DIVCLK_CLKC[4] bit 1
B132	BUFIO2[4]: IOCLK_ENABLE
B133	CLK_INT: mux CELL[2].DIVCLK_CLKC[4] bit 0
B134	BUFIO2[4]: CMT_ENABLE
B135	BUFPLL: ENABLE
B136	BUFPLL: DIVIDE0 bit 0
B137	BUFPLL: DIVIDE0 bit 1
B138	BUFPLL: DIVIDE0 bit 2
B139	BUFPLL: LOCK_SRC bit 1
B140	BUFPLL: ! ENABLE_SYNC0
B141	BUFPLL: DATA_RATE0 bit 0
B142	BUFPLL: DIVIDE1 bit 0
B143	BUFPLL: DIVIDE1 bit 1
B144	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 0
B145	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 1
B146	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 2
B147	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 0
B148	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 1
B149	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 2
B150	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 0
B151	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 1
B152	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 2
B153	BUFIO2[5]: POS_EDGE bit 0
B154	BUFIO2[5]: POS_EDGE bit 1
B155	BUFIO2[5]: POS_EDGE bit 2
B156	BUFIO2[5]: NEG_EDGE bit 0
B157	BUFIO2[5]: NEG_EDGE bit 1
B158	-
B159	BUFIO2[5]: DIVIDE bit 0
B160	BUFIO2[5]: DIVIDE bit 1
B161	BUFIO2[5]: DIVIDE bit 2
B162	BUFIO2[5]: R_EDGE
B163	BUFIO2[5]: ENABLE
B164	BUFIO2[5]: ENABLE_2CLK
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 0
B172	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 1
B173	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 2
B174	-
B175	BUFIO2FB[5]: ENABLE
B176	-
B177	BUFIO2[5]: ! DIVIDE_BYPASS
B178	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 3
B179	CLK_INT: mux CELL[2].DIVCLK_CLKC[5] bit 1
B180	BUFIO2[5]: IOCLK_ENABLE
B181	CLK_INT: mux CELL[2].DIVCLK_CLKC[5] bit 0
B182	BUFIO2[5]: CMT_ENABLE
B183	BUFPLL: DIVIDE1 bit 2
B184	BUFPLL: LOCK_SRC bit 0
B185	BUFPLL: ! ENABLE_SYNC1
B186	BUFPLL: DATA_RATE1 bit 0
B187	BUFPLL: DIVIDE0 bit 3
B188	-
B189	BUFPLL: DIVIDE0 bit 4
B190	BUFPLL: DIVIDE0 bit 5
B191	BUFPLL: DIVIDE1 bit 3
B192	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 0
B193	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 1
B194	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 2
B195	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 0
B196	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 1
B197	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 2
B198	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 0
B199	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 1
B200	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 2
B201	BUFIO2[2]: POS_EDGE bit 0
B202	BUFIO2[2]: POS_EDGE bit 1
B203	BUFIO2[2]: POS_EDGE bit 2
B204	BUFIO2[2]: NEG_EDGE bit 0
B205	BUFIO2[2]: NEG_EDGE bit 1
B206	-
B207	BUFIO2[2]: DIVIDE bit 0
B208	BUFIO2[2]: DIVIDE bit 1
B209	BUFIO2[2]: DIVIDE bit 2
B210	BUFIO2[2]: R_EDGE
B211	BUFIO2[2]: ENABLE
B212	BUFIO2[2]: ENABLE_2CLK
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 0
B220	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 1
B221	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 2
B222	-
B223	BUFIO2FB[2]: ENABLE
B224	-
B225	BUFIO2[2]: ! DIVIDE_BYPASS
B226	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 3
B227	CLK_INT: mux CELL[2].DIVCLK_CLKC[2] bit 1
B228	BUFIO2[2]: IOCLK_ENABLE
B229	CLK_INT: mux CELL[2].DIVCLK_CLKC[2] bit 0
B230	BUFIO2[2]: CMT_ENABLE
B231	-
B232	BUFPLL: DIVIDE1 bit 4
B233	BUFPLL: DIVIDE1 bit 5
B234	BUFPLL: ENABLE_BOTH_SYNC0 bit 0
B235	-
B236	-
B237	BUFPLL: ENABLE_BOTH_SYNC1 bit 0
B238	-
B239	-
B240	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 0
B241	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 1
B242	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 2
B243	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 0
B244	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 1
B245	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 2
B246	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 0
B247	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 1
B248	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 2
B249	BUFIO2[3]: POS_EDGE bit 0
B250	BUFIO2[3]: POS_EDGE bit 1
B251	BUFIO2[3]: POS_EDGE bit 2
B252	BUFIO2[3]: NEG_EDGE bit 0
B253	BUFIO2[3]: NEG_EDGE bit 1
B254	-
B255	BUFIO2[3]: DIVIDE bit 0
B256	BUFIO2[3]: DIVIDE bit 1
B257	BUFIO2[3]: DIVIDE bit 2
B258	BUFIO2[3]: R_EDGE
B259	BUFIO2[3]: ENABLE
B260	BUFIO2[3]: ENABLE_2CLK
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 0
B268	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 1
B269	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 2
B270	-
B271	BUFIO2FB[3]: ENABLE
B272	-
B273	BUFIO2[3]: ! DIVIDE_BYPASS
B274	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 3
B275	CLK_INT: mux CELL[2].DIVCLK_CLKC[3] bit 1
B276	BUFIO2[3]: IOCLK_ENABLE
B277	CLK_INT: mux CELL[2].DIVCLK_CLKC[3] bit 0
B278	BUFIO2[3]: CMT_ENABLE
B279	BUFPLL: ENABLE_NONE_SYNC0 bit 0
B280	BUFPLL: ENABLE_BOTH_SYNC0 bit 1
B281	BUFPLL: ENABLE_NONE_SYNC1 bit 0
B282	BUFPLL: ENABLE_BOTH_SYNC1 bit 1
B283	-
B284	-
B285	BUFPLL: ENABLE_NONE_SYNC0 bit 1
B286	BUFPLL: ENABLE_BOTH_SYNC0 bit 2
B287	-
B288	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 0
B289	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 1
B290	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 2
B291	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 0
B292	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 1
B293	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 2
B294	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 0
B295	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 1
B296	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 2
B297	BUFIO2[0]: POS_EDGE bit 0
B298	BUFIO2[0]: POS_EDGE bit 1
B299	BUFIO2[0]: POS_EDGE bit 2
B300	BUFIO2[0]: NEG_EDGE bit 0
B301	BUFIO2[0]: NEG_EDGE bit 1
B302	-
B303	BUFIO2[0]: DIVIDE bit 0
B304	BUFIO2[0]: DIVIDE bit 1
B305	BUFIO2[0]: DIVIDE bit 2
B306	BUFIO2[0]: R_EDGE
B307	BUFIO2[0]: ENABLE
B308	BUFIO2[0]: ENABLE_2CLK
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 0
B316	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 1
B317	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 2
B318	-
B319	BUFIO2FB[0]: ENABLE
B320	-
B321	BUFIO2[0]: ! DIVIDE_BYPASS
B322	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 3
B323	CLK_INT: mux CELL[2].DIVCLK_CLKC[0] bit 1
B324	BUFIO2[0]: IOCLK_ENABLE
B325	CLK_INT: mux CELL[2].DIVCLK_CLKC[0] bit 0
B326	BUFIO2[0]: CMT_ENABLE
B327	-
B328	BUFPLL: ENABLE_NONE_SYNC1 bit 1
B329	BUFPLL: ENABLE_BOTH_SYNC1 bit 2
B330	BUFPLL: MUX_PLLIN bit 0
B331	-
B332	-
B333	-
B334	-
B335	-
B336	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 0
B337	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 1
B338	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 2
B339	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 0
B340	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 1
B341	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 2
B342	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 0
B343	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 1
B344	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 2
B345	BUFIO2[1]: POS_EDGE bit 0
B346	BUFIO2[1]: POS_EDGE bit 1
B347	BUFIO2[1]: POS_EDGE bit 2
B348	BUFIO2[1]: NEG_EDGE bit 0
B349	BUFIO2[1]: NEG_EDGE bit 1
B350	-
B351	BUFIO2[1]: DIVIDE bit 0
B352	BUFIO2[1]: DIVIDE bit 1
B353	BUFIO2[1]: DIVIDE bit 2
B354	BUFIO2[1]: R_EDGE
B355	BUFIO2[1]: ENABLE
B356	BUFIO2[1]: ENABLE_2CLK
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 0
B364	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 1
B365	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 2
B366	-
B367	BUFIO2FB[1]: ENABLE
B368	-
B369	BUFIO2[1]: ! DIVIDE_BYPASS
B370	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 3
B371	CLK_INT: mux CELL[2].DIVCLK_CLKC[1] bit 1
B372	BUFIO2[1]: IOCLK_ENABLE
B373	CLK_INT: mux CELL[2].DIVCLK_CLKC[1] bit 0
B374	BUFIO2[1]: CMT_ENABLE
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

Tile CLK_E

Cells: 6

Switchbox CLK_INT

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_I[0]
Bits			Destination
MAIN[0][98]	MAIN[0][97]	MAIN[0][96]	CELL[1].IMUX_BUFIO2_I[0]	-
MAIN[0][290]	MAIN[0][289]	MAIN[0][288]	-	CELL[2].IMUX_BUFIO2_I[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[5].OUT_CLKPAD_DQSP
1	0	0	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[5].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[0]	CELL[2].GTPCLK[0]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_I[1]
Bits			Destination
MAIN[0][146]	MAIN[0][145]	MAIN[0][144]	CELL[1].IMUX_BUFIO2_I[1]	-
MAIN[0][338]	MAIN[0][337]	MAIN[0][336]	-	CELL[2].IMUX_BUFIO2_I[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[5].OUT_CLKPAD_DQSN
1	0	0	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[5].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[1]	CELL[2].GTPCLK[1]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_I[2]
Bits			Destination
MAIN[0][2]	MAIN[0][1]	MAIN[0][0]	CELL[1].IMUX_BUFIO2_I[2]	-
MAIN[0][194]	MAIN[0][193]	MAIN[0][192]	-	CELL[2].IMUX_BUFIO2_I[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[4].OUT_CLKPAD_DQSP
1	0	0	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[4].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP
1	1	1	CELL[1].GTPCLK[2]	CELL[2].GTPCLK[2]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_I[3]
Bits			Destination
MAIN[0][50]	MAIN[0][49]	MAIN[0][48]	CELL[1].IMUX_BUFIO2_I[3]	-
MAIN[0][242]	MAIN[0][241]	MAIN[0][240]	-	CELL[2].IMUX_BUFIO2_I[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[4].OUT_CLKPAD_DQSN
1	0	0	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[4].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN
1	1	1	CELL[1].GTPCLK[3]	CELL[2].GTPCLK[3]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_IB[0]
Bits			Destination
MAIN[0][101]	MAIN[0][100]	MAIN[0][99]	CELL[1].IMUX_BUFIO2_IB[0]	-
MAIN[0][293]	MAIN[0][292]	MAIN[0][291]	-	CELL[2].IMUX_BUFIO2_IB[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	1	0	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	1	CELL[1].OUT_CLKPAD_DQSN	CELL[5].OUT_CLKPAD_DQSN
1	0	0	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	0	1	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	1	0	CELL[5].OUT_CLKPAD_DQSN	CELL[1].OUT_CLKPAD_DQSN

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_IB[1]
Bits			Destination
MAIN[0][149]	MAIN[0][148]	MAIN[0][147]	CELL[1].IMUX_BUFIO2_IB[1]	-
MAIN[0][341]	MAIN[0][340]	MAIN[0][339]	-	CELL[2].IMUX_BUFIO2_IB[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	1	0	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	1	CELL[1].OUT_CLKPAD_DQSP	CELL[5].OUT_CLKPAD_DQSP
1	0	0	CELL[5].OUT_CLKPAD_I[0]	CELL[1].OUT_CLKPAD_I[0]
1	0	1	CELL[5].OUT_CLKPAD_I[1]	CELL[1].OUT_CLKPAD_I[1]
1	1	0	CELL[5].OUT_CLKPAD_DQSP	CELL[1].OUT_CLKPAD_DQSP

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_IB[2]
Bits			Destination
MAIN[0][5]	MAIN[0][4]	MAIN[0][3]	CELL[1].IMUX_BUFIO2_IB[2]	-
MAIN[0][197]	MAIN[0][196]	MAIN[0][195]	-	CELL[2].IMUX_BUFIO2_IB[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	1	0	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	1	CELL[0].OUT_CLKPAD_DQSN	CELL[4].OUT_CLKPAD_DQSN
1	0	0	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	0	1	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	1	0	CELL[4].OUT_CLKPAD_DQSN	CELL[0].OUT_CLKPAD_DQSN

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2_IB[3]
Bits			Destination
MAIN[0][53]	MAIN[0][52]	MAIN[0][51]	CELL[1].IMUX_BUFIO2_IB[3]	-
MAIN[0][245]	MAIN[0][244]	MAIN[0][243]	-	CELL[2].IMUX_BUFIO2_IB[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	1	0	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	1	CELL[0].OUT_CLKPAD_DQSP	CELL[4].OUT_CLKPAD_DQSP
1	0	0	CELL[4].OUT_CLKPAD_I[0]	CELL[0].OUT_CLKPAD_I[0]
1	0	1	CELL[4].OUT_CLKPAD_I[1]	CELL[0].OUT_CLKPAD_I[1]
1	1	0	CELL[4].OUT_CLKPAD_DQSP	CELL[0].OUT_CLKPAD_DQSP

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2FB[0]
Bits			Destination
MAIN[0][104]	MAIN[0][103]	MAIN[0][102]	CELL[1].IMUX_BUFIO2FB[0]	-
MAIN[0][296]	MAIN[0][295]	MAIN[0][294]	-	CELL[2].IMUX_BUFIO2FB[0]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[0]	CELL[5].OUT_CLKPAD_I[0]
0	0	1	CELL[1].OUT_CLKPAD_DFB[1]	CELL[5].OUT_CLKPAD_DFB[1]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[1]	CELL[5].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[1]	CELL[5].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[0]	CELL[2].GTPFB[0]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2FB[1]
Bits			Destination
MAIN[0][152]	MAIN[0][151]	MAIN[0][150]	CELL[1].IMUX_BUFIO2FB[1]	-
MAIN[0][344]	MAIN[0][343]	MAIN[0][342]	-	CELL[2].IMUX_BUFIO2FB[1]
			Source
0	0	0	CELL[1].OUT_CLKPAD_I[1]	CELL[5].OUT_CLKPAD_I[1]
0	0	1	CELL[1].OUT_CLKPAD_DFB[0]	CELL[5].OUT_CLKPAD_DFB[0]
0	1	0	CELL[1].OUT_CLKPAD_CFB0[0]	CELL[5].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[1].OUT_CLKPAD_CFB1[0]	CELL[5].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[1]	CELL[2].GTPFB[1]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2FB[2]
Bits			Destination
MAIN[0][8]	MAIN[0][7]	MAIN[0][6]	CELL[1].IMUX_BUFIO2FB[2]	-
MAIN[0][200]	MAIN[0][199]	MAIN[0][198]	-	CELL[2].IMUX_BUFIO2FB[2]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[0]	CELL[4].OUT_CLKPAD_I[0]
0	0	1	CELL[0].OUT_CLKPAD_DFB[1]	CELL[4].OUT_CLKPAD_DFB[1]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[1]	CELL[4].OUT_CLKPAD_CFB0[1]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[1]	CELL[4].OUT_CLKPAD_CFB1[1]
1	1	1	CELL[1].GTPFB[2]	CELL[2].GTPFB[2]

spartan6 CLK_E switchbox CLK_INT muxes IMUX_BUFIO2FB[3]
Bits			Destination
MAIN[0][56]	MAIN[0][55]	MAIN[0][54]	CELL[1].IMUX_BUFIO2FB[3]	-
MAIN[0][248]	MAIN[0][247]	MAIN[0][246]	-	CELL[2].IMUX_BUFIO2FB[3]
			Source
0	0	0	CELL[0].OUT_CLKPAD_I[1]	CELL[4].OUT_CLKPAD_I[1]
0	0	1	CELL[0].OUT_CLKPAD_DFB[0]	CELL[4].OUT_CLKPAD_DFB[0]
0	1	0	CELL[0].OUT_CLKPAD_CFB0[0]	CELL[4].OUT_CLKPAD_CFB0[0]
0	1	1	CELL[0].OUT_CLKPAD_CFB1[0]	CELL[4].OUT_CLKPAD_CFB1[0]
1	1	1	CELL[1].GTPFB[3]	CELL[2].GTPFB[3]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[0]
Bits		Destination
MAIN[0][323]	MAIN[0][325]	CELL[2].DIVCLK_CLKC[0]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[5].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[0]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[1]
Bits		Destination
MAIN[0][371]	MAIN[0][373]	CELL[2].DIVCLK_CLKC[1]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[5].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[1]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[2]
Bits		Destination
MAIN[0][227]	MAIN[0][229]	CELL[2].DIVCLK_CLKC[2]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[4].OUT_CLKPAD_I[1]
1	1	CELL[2].OUT_DIVCLK[2]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[3]
Bits		Destination
MAIN[0][275]	MAIN[0][277]	CELL[2].DIVCLK_CLKC[3]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[4].OUT_CLKPAD_I[0]
1	1	CELL[2].OUT_DIVCLK[3]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[4]
Bits		Destination
MAIN[0][131]	MAIN[0][133]	CELL[2].DIVCLK_CLKC[4]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[0]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[5]
Bits		Destination
MAIN[0][179]	MAIN[0][181]	CELL[2].DIVCLK_CLKC[5]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[1].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[1]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[6]
Bits		Destination
MAIN[0][35]	MAIN[0][37]	CELL[2].DIVCLK_CLKC[6]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[1]
1	1	CELL[1].OUT_DIVCLK[2]

spartan6 CLK_E switchbox CLK_INT muxes DIVCLK_CLKC[7]
Bits		Destination
MAIN[0][83]	MAIN[0][85]	CELL[2].DIVCLK_CLKC[7]
		Source
0	0	CELL[0].TIE_1
0	1	CELL[0].OUT_CLKPAD_I[0]
1	1	CELL[1].OUT_DIVCLK[3]

Bels BUFIO2

spartan6 CLK_E bel BUFIO2 pins
Pin	Direction	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
I	in	CELL[2].IMUX_BUFIO2_I[0]	CELL[2].IMUX_BUFIO2_I[1]	CELL[2].IMUX_BUFIO2_I[2]	CELL[2].IMUX_BUFIO2_I[3]	CELL[1].IMUX_BUFIO2_I[0]	CELL[1].IMUX_BUFIO2_I[1]	CELL[1].IMUX_BUFIO2_I[2]	CELL[1].IMUX_BUFIO2_I[3]
IB	in	CELL[2].IMUX_BUFIO2_IB[0]	CELL[2].IMUX_BUFIO2_IB[1]	CELL[2].IMUX_BUFIO2_IB[2]	CELL[2].IMUX_BUFIO2_IB[3]	CELL[1].IMUX_BUFIO2_IB[0]	CELL[1].IMUX_BUFIO2_IB[1]	CELL[1].IMUX_BUFIO2_IB[2]	CELL[1].IMUX_BUFIO2_IB[3]
DIVCLK	out	CELL[2].OUT_DIVCLK[0]	CELL[2].OUT_DIVCLK[1]	CELL[2].OUT_DIVCLK[2]	CELL[2].OUT_DIVCLK[3]	CELL[1].OUT_DIVCLK[0]	CELL[1].OUT_DIVCLK[1]	CELL[1].OUT_DIVCLK[2]	CELL[1].OUT_DIVCLK[3]
DIVCLK_CMT	out	CELL[2].DIVCLK_CMT_E[0]	CELL[2].DIVCLK_CMT_E[1]	CELL[2].DIVCLK_CMT_E[2]	CELL[2].DIVCLK_CMT_E[3]	CELL[1].DIVCLK_CMT_E[0]	CELL[1].DIVCLK_CMT_E[1]	CELL[1].DIVCLK_CMT_E[2]	CELL[1].DIVCLK_CMT_E[3]
IOCLK	out	CELL[2].IOCLK[0]	CELL[2].IOCLK[1]	CELL[2].IOCLK[2]	CELL[2].IOCLK[3]	CELL[1].IOCLK[0]	CELL[1].IOCLK[1]	CELL[1].IOCLK[2]	CELL[1].IOCLK[3]
SERDESSTROBE	out	CELL[2].IOCE[0]	CELL[2].IOCE[1]	CELL[2].IOCE[2]	CELL[2].IOCE[3]	CELL[1].IOCE[0]	CELL[1].IOCE[1]	CELL[1].IOCE[2]	CELL[1].IOCE[3]

spartan6 CLK_E bel BUFIO2 attribute bits
Attribute	BUFIO2[0]	BUFIO2[1]	BUFIO2[2]	BUFIO2[3]	BUFIO2[4]	BUFIO2[5]	BUFIO2[6]	BUFIO2[7]
ENABLE	MAIN[0][307]	MAIN[0][355]	MAIN[0][211]	MAIN[0][259]	MAIN[0][115]	MAIN[0][163]	MAIN[0][19]	MAIN[0][67]
ENABLE_2CLK	MAIN[0][308]	MAIN[0][356]	MAIN[0][212]	MAIN[0][260]	MAIN[0][116]	MAIN[0][164]	MAIN[0][20]	MAIN[0][68]
CMT_ENABLE	MAIN[0][326]	MAIN[0][374]	MAIN[0][230]	MAIN[0][278]	MAIN[0][134]	MAIN[0][182]	MAIN[0][38]	MAIN[0][86]
IOCLK_ENABLE	MAIN[0][324]	MAIN[0][372]	MAIN[0][228]	MAIN[0][276]	MAIN[0][132]	MAIN[0][180]	MAIN[0][36]	MAIN[0][84]
DIVIDE	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]	[enum: BUFIO2_DIVIDE]
DIVIDE_BYPASS	!MAIN[0][321]	!MAIN[0][369]	!MAIN[0][225]	!MAIN[0][273]	!MAIN[0][129]	!MAIN[0][177]	!MAIN[0][33]	!MAIN[0][81]
R_EDGE	MAIN[0][306]	MAIN[0][354]	MAIN[0][210]	MAIN[0][258]	MAIN[0][114]	MAIN[0][162]	MAIN[0][18]	MAIN[0][66]
POS_EDGE bit 0	MAIN[0][297]	MAIN[0][345]	MAIN[0][201]	MAIN[0][249]	MAIN[0][105]	MAIN[0][153]	MAIN[0][9]	MAIN[0][57]
POS_EDGE bit 1	MAIN[0][298]	MAIN[0][346]	MAIN[0][202]	MAIN[0][250]	MAIN[0][106]	MAIN[0][154]	MAIN[0][10]	MAIN[0][58]
POS_EDGE bit 2	MAIN[0][299]	MAIN[0][347]	MAIN[0][203]	MAIN[0][251]	MAIN[0][107]	MAIN[0][155]	MAIN[0][11]	MAIN[0][59]
NEG_EDGE bit 0	MAIN[0][300]	MAIN[0][348]	MAIN[0][204]	MAIN[0][252]	MAIN[0][108]	MAIN[0][156]	MAIN[0][12]	MAIN[0][60]
NEG_EDGE bit 1	MAIN[0][301]	MAIN[0][349]	MAIN[0][205]	MAIN[0][253]	MAIN[0][109]	MAIN[0][157]	MAIN[0][13]	MAIN[0][61]

spartan6 CLK_E enum BUFIO2_DIVIDE
BUFIO2[0].DIVIDE	MAIN[0][305]	MAIN[0][304]	MAIN[0][303]
BUFIO2[1].DIVIDE	MAIN[0][353]	MAIN[0][352]	MAIN[0][351]
BUFIO2[2].DIVIDE	MAIN[0][209]	MAIN[0][208]	MAIN[0][207]
BUFIO2[3].DIVIDE	MAIN[0][257]	MAIN[0][256]	MAIN[0][255]
BUFIO2[4].DIVIDE	MAIN[0][113]	MAIN[0][112]	MAIN[0][111]
BUFIO2[5].DIVIDE	MAIN[0][161]	MAIN[0][160]	MAIN[0][159]
BUFIO2[6].DIVIDE	MAIN[0][17]	MAIN[0][16]	MAIN[0][15]
BUFIO2[7].DIVIDE	MAIN[0][65]	MAIN[0][64]	MAIN[0][63]
_1	1	1	1
_2	0	0	0
_3	0	0	1
_4	0	1	0
_5	0	1	1
_6	1	0	0
_7	1	0	1
_8	1	1	0

Bels BUFIO2FB

spartan6 CLK_E bel BUFIO2FB pins
Pin	Direction	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
I	in	CELL[2].IMUX_BUFIO2FB[0]	CELL[2].IMUX_BUFIO2FB[1]	CELL[2].IMUX_BUFIO2FB[2]	CELL[2].IMUX_BUFIO2FB[3]	CELL[1].IMUX_BUFIO2FB[0]	CELL[1].IMUX_BUFIO2FB[1]	CELL[1].IMUX_BUFIO2FB[2]	CELL[1].IMUX_BUFIO2FB[3]
O	out	CELL[2].IOFBCLK_CMT_E[0]	CELL[2].IOFBCLK_CMT_E[1]	CELL[2].IOFBCLK_CMT_E[2]	CELL[2].IOFBCLK_CMT_E[3]	CELL[1].IOFBCLK_CMT_E[0]	CELL[1].IOFBCLK_CMT_E[1]	CELL[1].IOFBCLK_CMT_E[2]	CELL[1].IOFBCLK_CMT_E[3]

spartan6 CLK_E bel BUFIO2FB attribute bits
Attribute	BUFIO2FB[0]	BUFIO2FB[1]	BUFIO2FB[2]	BUFIO2FB[3]	BUFIO2FB[4]	BUFIO2FB[5]	BUFIO2FB[6]	BUFIO2FB[7]
ENABLE	MAIN[0][319]	MAIN[0][367]	MAIN[0][223]	MAIN[0][271]	MAIN[0][127]	MAIN[0][175]	MAIN[0][31]	MAIN[0][79]
DIVIDE_BYPASS bit 0	!MAIN[0][315]	!MAIN[0][363]	!MAIN[0][219]	!MAIN[0][267]	!MAIN[0][123]	!MAIN[0][171]	!MAIN[0][27]	!MAIN[0][75]
DIVIDE_BYPASS bit 1	!MAIN[0][316]	!MAIN[0][364]	!MAIN[0][220]	!MAIN[0][268]	!MAIN[0][124]	!MAIN[0][172]	!MAIN[0][28]	!MAIN[0][76]
DIVIDE_BYPASS bit 2	!MAIN[0][317]	!MAIN[0][365]	!MAIN[0][221]	!MAIN[0][269]	!MAIN[0][125]	!MAIN[0][173]	!MAIN[0][29]	!MAIN[0][77]
DIVIDE_BYPASS bit 3	!MAIN[0][322]	!MAIN[0][370]	!MAIN[0][226]	!MAIN[0][274]	!MAIN[0][130]	!MAIN[0][178]	!MAIN[0][34]	!MAIN[0][82]

Bels BUFPLL

spartan6 CLK_E bel BUFPLL pins
Pin	Direction	BUFPLL
GCLK[0]	in	CELL[2].IMUX_CLK[0]
GCLK[1]	in	CELL[2].IMUX_CLK[1]
PLLIN_CMT[0]	in	CELL[2].CMT_BUFPLL_H_CLKOUT[0]
PLLIN_CMT[1]	in	CELL[2].CMT_BUFPLL_H_CLKOUT[1]
PLLIN_GCLK[0]	in	CELL[3].IMUX_CLK[0]
PLLIN_GCLK[1]	in	CELL[3].IMUX_CLK[1]
LOCKED[0]	in	CELL[2].CMT_BUFPLL_H_LOCKED[0]
LOCKED[1]	in	CELL[2].CMT_BUFPLL_H_LOCKED[1]
PLLCLK[0]	out	CELL[2].PLLCLK[0]
PLLCLK[1]	out	CELL[2].PLLCLK[1]
PLLCE[0]	out	CELL[2].PLLCE[0]
PLLCE[1]	out	CELL[2].PLLCE[1]
LOCK[0]	out	CELL[2].OUT_BEL[0]
LOCK[1]	out	CELL[2].OUT_BEL[1]

spartan6 CLK_E bel BUFPLL attribute bits
Attribute	BUFPLL
ENABLE	MAIN[0][135]
MUX_PLLIN	[enum: BUFPLL_MUX_PLLIN]
LOCK_SRC	[enum: BUFPLL_LOCK_SRC]
DATA_RATE0	[enum: BUFPLL_DATA_RATE]
DATA_RATE1	[enum: BUFPLL_DATA_RATE]
DIVIDE0	[enum: BUFIO2_DIVIDE]
DIVIDE1	[enum: BUFIO2_DIVIDE]
ENABLE_BOTH_SYNC0 bit 0	MAIN[0][234]
ENABLE_BOTH_SYNC0 bit 1	MAIN[0][280]
ENABLE_BOTH_SYNC0 bit 2	MAIN[0][286]
ENABLE_BOTH_SYNC1 bit 0	MAIN[0][237]
ENABLE_BOTH_SYNC1 bit 1	MAIN[0][282]
ENABLE_BOTH_SYNC1 bit 2	MAIN[0][329]
ENABLE_NONE_SYNC0 bit 0	MAIN[0][279]
ENABLE_NONE_SYNC0 bit 1	MAIN[0][285]
ENABLE_NONE_SYNC1 bit 0	MAIN[0][281]
ENABLE_NONE_SYNC1 bit 1	MAIN[0][328]
ENABLE_SYNC0	!MAIN[0][140]
ENABLE_SYNC1	!MAIN[0][185]

spartan6 CLK_E enum BUFPLL_MUX_PLLIN
BUFPLL.MUX_PLLIN	MAIN[0][330]
CMT	0
GCLK	1

spartan6 CLK_E enum BUFPLL_LOCK_SRC
BUFPLL.LOCK_SRC	MAIN[0][139]	MAIN[0][184]
NONE	0	0
LOCK_TO_0	0	1
LOCK_TO_1	1	0

spartan6 CLK_E enum BUFPLL_DATA_RATE
BUFPLL.DATA_RATE0	MAIN[0][141]
BUFPLL.DATA_RATE1	MAIN[0][186]
SDR	0
DDR	1

spartan6 CLK_E enum BUFIO2_DIVIDE
BUFPLL.DIVIDE0	MAIN[0][190]	MAIN[0][189]	MAIN[0][187]	MAIN[0][138]	MAIN[0][137]	MAIN[0][136]
BUFPLL.DIVIDE1	MAIN[0][233]	MAIN[0][232]	MAIN[0][191]	MAIN[0][183]	MAIN[0][143]	MAIN[0][142]
_1	1	1	0	1	1	1
_2	0	0	1	0	0	0
_3	0	0	0	0	0	1
_4	0	1	1	0	1	0
_5	0	1	0	0	1	1
_6	1	0	1	1	0	0
_7	1	0	0	1	0	1
_8	1	1	1	1	1	0

Bel wires

spartan6 CLK_E bel wires
Wire	Pins
CELL[1].IOCLK[0]	BUFIO2[4].IOCLK
CELL[1].IOCLK[1]	BUFIO2[5].IOCLK
CELL[1].IOCLK[2]	BUFIO2[6].IOCLK
CELL[1].IOCLK[3]	BUFIO2[7].IOCLK
CELL[1].IOCE[0]	BUFIO2[4].SERDESSTROBE
CELL[1].IOCE[1]	BUFIO2[5].SERDESSTROBE
CELL[1].IOCE[2]	BUFIO2[6].SERDESSTROBE
CELL[1].IOCE[3]	BUFIO2[7].SERDESSTROBE
CELL[1].IMUX_BUFIO2_I[0]	BUFIO2[4].I
CELL[1].IMUX_BUFIO2_I[1]	BUFIO2[5].I
CELL[1].IMUX_BUFIO2_I[2]	BUFIO2[6].I
CELL[1].IMUX_BUFIO2_I[3]	BUFIO2[7].I
CELL[1].IMUX_BUFIO2_IB[0]	BUFIO2[4].IB
CELL[1].IMUX_BUFIO2_IB[1]	BUFIO2[5].IB
CELL[1].IMUX_BUFIO2_IB[2]	BUFIO2[6].IB
CELL[1].IMUX_BUFIO2_IB[3]	BUFIO2[7].IB
CELL[1].IMUX_BUFIO2FB[0]	BUFIO2FB[4].I
CELL[1].IMUX_BUFIO2FB[1]	BUFIO2FB[5].I
CELL[1].IMUX_BUFIO2FB[2]	BUFIO2FB[6].I
CELL[1].IMUX_BUFIO2FB[3]	BUFIO2FB[7].I
CELL[1].OUT_DIVCLK[0]	BUFIO2[4].DIVCLK
CELL[1].OUT_DIVCLK[1]	BUFIO2[5].DIVCLK
CELL[1].OUT_DIVCLK[2]	BUFIO2[6].DIVCLK
CELL[1].OUT_DIVCLK[3]	BUFIO2[7].DIVCLK
CELL[1].DIVCLK_CMT_E[0]	BUFIO2[4].DIVCLK_CMT
CELL[1].DIVCLK_CMT_E[1]	BUFIO2[5].DIVCLK_CMT
CELL[1].DIVCLK_CMT_E[2]	BUFIO2[6].DIVCLK_CMT
CELL[1].DIVCLK_CMT_E[3]	BUFIO2[7].DIVCLK_CMT
CELL[1].IOFBCLK_CMT_E[0]	BUFIO2FB[4].O
CELL[1].IOFBCLK_CMT_E[1]	BUFIO2FB[5].O
CELL[1].IOFBCLK_CMT_E[2]	BUFIO2FB[6].O
CELL[1].IOFBCLK_CMT_E[3]	BUFIO2FB[7].O
CELL[2].IMUX_CLK[0]	BUFPLL.GCLK[0]
CELL[2].IMUX_CLK[1]	BUFPLL.GCLK[1]
CELL[2].OUT_BEL[0]	BUFPLL.LOCK[0]
CELL[2].OUT_BEL[1]	BUFPLL.LOCK[1]
CELL[2].IOCLK[0]	BUFIO2[0].IOCLK
CELL[2].IOCLK[1]	BUFIO2[1].IOCLK
CELL[2].IOCLK[2]	BUFIO2[2].IOCLK
CELL[2].IOCLK[3]	BUFIO2[3].IOCLK
CELL[2].IOCE[0]	BUFIO2[0].SERDESSTROBE
CELL[2].IOCE[1]	BUFIO2[1].SERDESSTROBE
CELL[2].IOCE[2]	BUFIO2[2].SERDESSTROBE
CELL[2].IOCE[3]	BUFIO2[3].SERDESSTROBE
CELL[2].PLLCLK[0]	BUFPLL.PLLCLK[0]
CELL[2].PLLCLK[1]	BUFPLL.PLLCLK[1]
CELL[2].PLLCE[0]	BUFPLL.PLLCE[0]
CELL[2].PLLCE[1]	BUFPLL.PLLCE[1]
CELL[2].IMUX_BUFIO2_I[0]	BUFIO2[0].I
CELL[2].IMUX_BUFIO2_I[1]	BUFIO2[1].I
CELL[2].IMUX_BUFIO2_I[2]	BUFIO2[2].I
CELL[2].IMUX_BUFIO2_I[3]	BUFIO2[3].I
CELL[2].IMUX_BUFIO2_IB[0]	BUFIO2[0].IB
CELL[2].IMUX_BUFIO2_IB[1]	BUFIO2[1].IB
CELL[2].IMUX_BUFIO2_IB[2]	BUFIO2[2].IB
CELL[2].IMUX_BUFIO2_IB[3]	BUFIO2[3].IB
CELL[2].IMUX_BUFIO2FB[0]	BUFIO2FB[0].I
CELL[2].IMUX_BUFIO2FB[1]	BUFIO2FB[1].I
CELL[2].IMUX_BUFIO2FB[2]	BUFIO2FB[2].I
CELL[2].IMUX_BUFIO2FB[3]	BUFIO2FB[3].I
CELL[2].OUT_DIVCLK[0]	BUFIO2[0].DIVCLK
CELL[2].OUT_DIVCLK[1]	BUFIO2[1].DIVCLK
CELL[2].OUT_DIVCLK[2]	BUFIO2[2].DIVCLK
CELL[2].OUT_DIVCLK[3]	BUFIO2[3].DIVCLK
CELL[2].DIVCLK_CMT_E[0]	BUFIO2[0].DIVCLK_CMT
CELL[2].DIVCLK_CMT_E[1]	BUFIO2[1].DIVCLK_CMT
CELL[2].DIVCLK_CMT_E[2]	BUFIO2[2].DIVCLK_CMT
CELL[2].DIVCLK_CMT_E[3]	BUFIO2[3].DIVCLK_CMT
CELL[2].IOFBCLK_CMT_E[0]	BUFIO2FB[0].O
CELL[2].IOFBCLK_CMT_E[1]	BUFIO2FB[1].O
CELL[2].IOFBCLK_CMT_E[2]	BUFIO2FB[2].O
CELL[2].IOFBCLK_CMT_E[3]	BUFIO2FB[3].O
CELL[2].CMT_BUFPLL_H_CLKOUT[0]	BUFPLL.PLLIN_CMT[0]
CELL[2].CMT_BUFPLL_H_CLKOUT[1]	BUFPLL.PLLIN_CMT[1]
CELL[2].CMT_BUFPLL_H_LOCKED[0]	BUFPLL.LOCKED[0]
CELL[2].CMT_BUFPLL_H_LOCKED[1]	BUFPLL.LOCKED[1]
CELL[3].IMUX_CLK[0]	BUFPLL.PLLIN_GCLK[0]
CELL[3].IMUX_CLK[1]	BUFPLL.PLLIN_GCLK[1]

Bitstream

spartan6 CLK_E rect MAIN
Bit	Frame
Bit	F0
B0	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 0
B1	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 1
B2	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[2] bit 2
B3	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 0
B4	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 1
B5	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[2] bit 2
B6	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 0
B7	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 1
B8	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[2] bit 2
B9	BUFIO2[6]: POS_EDGE bit 0
B10	BUFIO2[6]: POS_EDGE bit 1
B11	BUFIO2[6]: POS_EDGE bit 2
B12	BUFIO2[6]: NEG_EDGE bit 0
B13	BUFIO2[6]: NEG_EDGE bit 1
B14	-
B15	BUFIO2[6]: DIVIDE bit 0
B16	BUFIO2[6]: DIVIDE bit 1
B17	BUFIO2[6]: DIVIDE bit 2
B18	BUFIO2[6]: R_EDGE
B19	BUFIO2[6]: ENABLE
B20	BUFIO2[6]: ENABLE_2CLK
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 0
B28	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 1
B29	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 2
B30	-
B31	BUFIO2FB[6]: ENABLE
B32	-
B33	BUFIO2[6]: ! DIVIDE_BYPASS
B34	BUFIO2FB[6]: ! DIVIDE_BYPASS bit 3
B35	CLK_INT: mux CELL[2].DIVCLK_CLKC[6] bit 1
B36	BUFIO2[6]: IOCLK_ENABLE
B37	CLK_INT: mux CELL[2].DIVCLK_CLKC[6] bit 0
B38	BUFIO2[6]: CMT_ENABLE
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 0
B49	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 1
B50	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[3] bit 2
B51	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 0
B52	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 1
B53	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[3] bit 2
B54	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 0
B55	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 1
B56	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[3] bit 2
B57	BUFIO2[7]: POS_EDGE bit 0
B58	BUFIO2[7]: POS_EDGE bit 1
B59	BUFIO2[7]: POS_EDGE bit 2
B60	BUFIO2[7]: NEG_EDGE bit 0
B61	BUFIO2[7]: NEG_EDGE bit 1
B62	-
B63	BUFIO2[7]: DIVIDE bit 0
B64	BUFIO2[7]: DIVIDE bit 1
B65	BUFIO2[7]: DIVIDE bit 2
B66	BUFIO2[7]: R_EDGE
B67	BUFIO2[7]: ENABLE
B68	BUFIO2[7]: ENABLE_2CLK
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 0
B76	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 1
B77	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 2
B78	-
B79	BUFIO2FB[7]: ENABLE
B80	-
B81	BUFIO2[7]: ! DIVIDE_BYPASS
B82	BUFIO2FB[7]: ! DIVIDE_BYPASS bit 3
B83	CLK_INT: mux CELL[2].DIVCLK_CLKC[7] bit 1
B84	BUFIO2[7]: IOCLK_ENABLE
B85	CLK_INT: mux CELL[2].DIVCLK_CLKC[7] bit 0
B86	BUFIO2[7]: CMT_ENABLE
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 0
B97	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 1
B98	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[0] bit 2
B99	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 0
B100	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 1
B101	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[0] bit 2
B102	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 0
B103	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 1
B104	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[0] bit 2
B105	BUFIO2[4]: POS_EDGE bit 0
B106	BUFIO2[4]: POS_EDGE bit 1
B107	BUFIO2[4]: POS_EDGE bit 2
B108	BUFIO2[4]: NEG_EDGE bit 0
B109	BUFIO2[4]: NEG_EDGE bit 1
B110	-
B111	BUFIO2[4]: DIVIDE bit 0
B112	BUFIO2[4]: DIVIDE bit 1
B113	BUFIO2[4]: DIVIDE bit 2
B114	BUFIO2[4]: R_EDGE
B115	BUFIO2[4]: ENABLE
B116	BUFIO2[4]: ENABLE_2CLK
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 0
B124	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 1
B125	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 2
B126	-
B127	BUFIO2FB[4]: ENABLE
B128	-
B129	BUFIO2[4]: ! DIVIDE_BYPASS
B130	BUFIO2FB[4]: ! DIVIDE_BYPASS bit 3
B131	CLK_INT: mux CELL[2].DIVCLK_CLKC[4] bit 1
B132	BUFIO2[4]: IOCLK_ENABLE
B133	CLK_INT: mux CELL[2].DIVCLK_CLKC[4] bit 0
B134	BUFIO2[4]: CMT_ENABLE
B135	BUFPLL: ENABLE
B136	BUFPLL: DIVIDE0 bit 0
B137	BUFPLL: DIVIDE0 bit 1
B138	BUFPLL: DIVIDE0 bit 2
B139	BUFPLL: LOCK_SRC bit 1
B140	BUFPLL: ! ENABLE_SYNC0
B141	BUFPLL: DATA_RATE0 bit 0
B142	BUFPLL: DIVIDE1 bit 0
B143	BUFPLL: DIVIDE1 bit 1
B144	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 0
B145	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 1
B146	CLK_INT: mux CELL[1].IMUX_BUFIO2_I[1] bit 2
B147	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 0
B148	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 1
B149	CLK_INT: mux CELL[1].IMUX_BUFIO2_IB[1] bit 2
B150	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 0
B151	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 1
B152	CLK_INT: mux CELL[1].IMUX_BUFIO2FB[1] bit 2
B153	BUFIO2[5]: POS_EDGE bit 0
B154	BUFIO2[5]: POS_EDGE bit 1
B155	BUFIO2[5]: POS_EDGE bit 2
B156	BUFIO2[5]: NEG_EDGE bit 0
B157	BUFIO2[5]: NEG_EDGE bit 1
B158	-
B159	BUFIO2[5]: DIVIDE bit 0
B160	BUFIO2[5]: DIVIDE bit 1
B161	BUFIO2[5]: DIVIDE bit 2
B162	BUFIO2[5]: R_EDGE
B163	BUFIO2[5]: ENABLE
B164	BUFIO2[5]: ENABLE_2CLK
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 0
B172	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 1
B173	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 2
B174	-
B175	BUFIO2FB[5]: ENABLE
B176	-
B177	BUFIO2[5]: ! DIVIDE_BYPASS
B178	BUFIO2FB[5]: ! DIVIDE_BYPASS bit 3
B179	CLK_INT: mux CELL[2].DIVCLK_CLKC[5] bit 1
B180	BUFIO2[5]: IOCLK_ENABLE
B181	CLK_INT: mux CELL[2].DIVCLK_CLKC[5] bit 0
B182	BUFIO2[5]: CMT_ENABLE
B183	BUFPLL: DIVIDE1 bit 2
B184	BUFPLL: LOCK_SRC bit 0
B185	BUFPLL: ! ENABLE_SYNC1
B186	BUFPLL: DATA_RATE1 bit 0
B187	BUFPLL: DIVIDE0 bit 3
B188	-
B189	BUFPLL: DIVIDE0 bit 4
B190	BUFPLL: DIVIDE0 bit 5
B191	BUFPLL: DIVIDE1 bit 3
B192	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 0
B193	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 1
B194	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[2] bit 2
B195	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 0
B196	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 1
B197	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[2] bit 2
B198	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 0
B199	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 1
B200	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[2] bit 2
B201	BUFIO2[2]: POS_EDGE bit 0
B202	BUFIO2[2]: POS_EDGE bit 1
B203	BUFIO2[2]: POS_EDGE bit 2
B204	BUFIO2[2]: NEG_EDGE bit 0
B205	BUFIO2[2]: NEG_EDGE bit 1
B206	-
B207	BUFIO2[2]: DIVIDE bit 0
B208	BUFIO2[2]: DIVIDE bit 1
B209	BUFIO2[2]: DIVIDE bit 2
B210	BUFIO2[2]: R_EDGE
B211	BUFIO2[2]: ENABLE
B212	BUFIO2[2]: ENABLE_2CLK
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 0
B220	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 1
B221	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 2
B222	-
B223	BUFIO2FB[2]: ENABLE
B224	-
B225	BUFIO2[2]: ! DIVIDE_BYPASS
B226	BUFIO2FB[2]: ! DIVIDE_BYPASS bit 3
B227	CLK_INT: mux CELL[2].DIVCLK_CLKC[2] bit 1
B228	BUFIO2[2]: IOCLK_ENABLE
B229	CLK_INT: mux CELL[2].DIVCLK_CLKC[2] bit 0
B230	BUFIO2[2]: CMT_ENABLE
B231	-
B232	BUFPLL: DIVIDE1 bit 4
B233	BUFPLL: DIVIDE1 bit 5
B234	BUFPLL: ENABLE_BOTH_SYNC0 bit 0
B235	-
B236	-
B237	BUFPLL: ENABLE_BOTH_SYNC1 bit 0
B238	-
B239	-
B240	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 0
B241	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 1
B242	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[3] bit 2
B243	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 0
B244	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 1
B245	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[3] bit 2
B246	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 0
B247	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 1
B248	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[3] bit 2
B249	BUFIO2[3]: POS_EDGE bit 0
B250	BUFIO2[3]: POS_EDGE bit 1
B251	BUFIO2[3]: POS_EDGE bit 2
B252	BUFIO2[3]: NEG_EDGE bit 0
B253	BUFIO2[3]: NEG_EDGE bit 1
B254	-
B255	BUFIO2[3]: DIVIDE bit 0
B256	BUFIO2[3]: DIVIDE bit 1
B257	BUFIO2[3]: DIVIDE bit 2
B258	BUFIO2[3]: R_EDGE
B259	BUFIO2[3]: ENABLE
B260	BUFIO2[3]: ENABLE_2CLK
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 0
B268	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 1
B269	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 2
B270	-
B271	BUFIO2FB[3]: ENABLE
B272	-
B273	BUFIO2[3]: ! DIVIDE_BYPASS
B274	BUFIO2FB[3]: ! DIVIDE_BYPASS bit 3
B275	CLK_INT: mux CELL[2].DIVCLK_CLKC[3] bit 1
B276	BUFIO2[3]: IOCLK_ENABLE
B277	CLK_INT: mux CELL[2].DIVCLK_CLKC[3] bit 0
B278	BUFIO2[3]: CMT_ENABLE
B279	BUFPLL: ENABLE_NONE_SYNC0 bit 0
B280	BUFPLL: ENABLE_BOTH_SYNC0 bit 1
B281	BUFPLL: ENABLE_NONE_SYNC1 bit 0
B282	BUFPLL: ENABLE_BOTH_SYNC1 bit 1
B283	-
B284	-
B285	BUFPLL: ENABLE_NONE_SYNC0 bit 1
B286	BUFPLL: ENABLE_BOTH_SYNC0 bit 2
B287	-
B288	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 0
B289	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 1
B290	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[0] bit 2
B291	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 0
B292	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 1
B293	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[0] bit 2
B294	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 0
B295	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 1
B296	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[0] bit 2
B297	BUFIO2[0]: POS_EDGE bit 0
B298	BUFIO2[0]: POS_EDGE bit 1
B299	BUFIO2[0]: POS_EDGE bit 2
B300	BUFIO2[0]: NEG_EDGE bit 0
B301	BUFIO2[0]: NEG_EDGE bit 1
B302	-
B303	BUFIO2[0]: DIVIDE bit 0
B304	BUFIO2[0]: DIVIDE bit 1
B305	BUFIO2[0]: DIVIDE bit 2
B306	BUFIO2[0]: R_EDGE
B307	BUFIO2[0]: ENABLE
B308	BUFIO2[0]: ENABLE_2CLK
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 0
B316	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 1
B317	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 2
B318	-
B319	BUFIO2FB[0]: ENABLE
B320	-
B321	BUFIO2[0]: ! DIVIDE_BYPASS
B322	BUFIO2FB[0]: ! DIVIDE_BYPASS bit 3
B323	CLK_INT: mux CELL[2].DIVCLK_CLKC[0] bit 1
B324	BUFIO2[0]: IOCLK_ENABLE
B325	CLK_INT: mux CELL[2].DIVCLK_CLKC[0] bit 0
B326	BUFIO2[0]: CMT_ENABLE
B327	-
B328	BUFPLL: ENABLE_NONE_SYNC1 bit 1
B329	BUFPLL: ENABLE_BOTH_SYNC1 bit 2
B330	BUFPLL: MUX_PLLIN bit 0
B331	-
B332	-
B333	-
B334	-
B335	-
B336	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 0
B337	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 1
B338	CLK_INT: mux CELL[2].IMUX_BUFIO2_I[1] bit 2
B339	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 0
B340	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 1
B341	CLK_INT: mux CELL[2].IMUX_BUFIO2_IB[1] bit 2
B342	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 0
B343	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 1
B344	CLK_INT: mux CELL[2].IMUX_BUFIO2FB[1] bit 2
B345	BUFIO2[1]: POS_EDGE bit 0
B346	BUFIO2[1]: POS_EDGE bit 1
B347	BUFIO2[1]: POS_EDGE bit 2
B348	BUFIO2[1]: NEG_EDGE bit 0
B349	BUFIO2[1]: NEG_EDGE bit 1
B350	-
B351	BUFIO2[1]: DIVIDE bit 0
B352	BUFIO2[1]: DIVIDE bit 1
B353	BUFIO2[1]: DIVIDE bit 2
B354	BUFIO2[1]: R_EDGE
B355	BUFIO2[1]: ENABLE
B356	BUFIO2[1]: ENABLE_2CLK
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 0
B364	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 1
B365	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 2
B366	-
B367	BUFIO2FB[1]: ENABLE
B368	-
B369	BUFIO2[1]: ! DIVIDE_BYPASS
B370	BUFIO2FB[1]: ! DIVIDE_BYPASS bit 3
B371	CLK_INT: mux CELL[2].DIVCLK_CLKC[1] bit 1
B372	BUFIO2[1]: IOCLK_ENABLE
B373	CLK_INT: mux CELL[2].DIVCLK_CLKC[1] bit 0
B374	BUFIO2[1]: CMT_ENABLE
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

Keyboard shortcuts

Project Combine