I/O clock buffers

Tile CLK_S

Cells: 1

Switchbox REG_INT

spartan6 CLK_S switchbox REG_INT muxes IMUX_CLK_GCLK[0]
Bits	Destination
IMUX_CLK_GCLK[0]
	Source
GCLK[15]

spartan6 CLK_S switchbox REG_INT muxes IMUX_CLK_GCLK[1]
Bits	Destination
IMUX_CLK_GCLK[1]
	Source
GCLK[15]

Bel BUFIO2[0]

spartan6 CLK_S bel BUFIO2[0]
Pin	Direction	Wires

Bel BUFIO2[1]

spartan6 CLK_S bel BUFIO2[1]
Pin	Direction	Wires

Bel BUFIO2[2]

spartan6 CLK_S bel BUFIO2[2]
Pin	Direction	Wires

Bel BUFIO2[3]

spartan6 CLK_S bel BUFIO2[3]
Pin	Direction	Wires

Bel BUFIO2[4]

spartan6 CLK_S bel BUFIO2[4]
Pin	Direction	Wires

Bel BUFIO2[5]

spartan6 CLK_S bel BUFIO2[5]
Pin	Direction	Wires

Bel BUFIO2[6]

spartan6 CLK_S bel BUFIO2[6]
Pin	Direction	Wires

Bel BUFIO2[7]

spartan6 CLK_S bel BUFIO2[7]
Pin	Direction	Wires

Bel BUFIO2FB[0]

spartan6 CLK_S bel BUFIO2FB[0]
Pin	Direction	Wires

Bel BUFIO2FB[1]

spartan6 CLK_S bel BUFIO2FB[1]
Pin	Direction	Wires

Bel BUFIO2FB[2]

spartan6 CLK_S bel BUFIO2FB[2]
Pin	Direction	Wires

Bel BUFIO2FB[3]

spartan6 CLK_S bel BUFIO2FB[3]
Pin	Direction	Wires

Bel BUFIO2FB[4]

spartan6 CLK_S bel BUFIO2FB[4]
Pin	Direction	Wires

Bel BUFIO2FB[5]

spartan6 CLK_S bel BUFIO2FB[5]
Pin	Direction	Wires

Bel BUFIO2FB[6]

spartan6 CLK_S bel BUFIO2FB[6]
Pin	Direction	Wires

Bel BUFIO2FB[7]

spartan6 CLK_S bel BUFIO2FB[7]
Pin	Direction	Wires

Bel BUFPLL[0]

spartan6 CLK_S bel BUFPLL[0]
Pin	Direction	Wires

Bel BUFPLL[1]

spartan6 CLK_S bel BUFPLL[1]
Pin	Direction	Wires

Bel BUFPLL_MCB

spartan6 CLK_S bel BUFPLL_MCB
Pin	Direction	Wires

Bel BUFPLL_OUT

spartan6 CLK_S bel BUFPLL_OUT
Pin	Direction	Wires
LOCK0	output	OUT[18]
LOCK1	output	OUT[19]

Bel BUFPLL_INS_SN

spartan6 CLK_S bel BUFPLL_INS_SN
Pin	Direction	Wires
GCLK0	input	IMUX_CLK_GCLK[0]
GCLK1	input	IMUX_CLK_GCLK[1]

Bel BUFIO2_INS

spartan6 CLK_S bel BUFIO2_INS
Pin	Direction	Wires

Bel BUFIO2_CKPIN

spartan6 CLK_S bel BUFIO2_CKPIN
Pin	Direction	Wires

Bel BUFPLL_BUF

spartan6 CLK_S bel BUFPLL_BUF
Pin	Direction	Wires

Bel GTP_H_BUF

spartan6 CLK_S bel GTP_H_BUF
Pin	Direction	Wires

Bel TIEOFF_REG

spartan6 CLK_S bel TIEOFF_REG
Pin	Direction	Wires

Bel wires

spartan6 CLK_S bel wires
Wire	Pins
OUT[18]	BUFPLL_OUT.LOCK0
OUT[19]	BUFPLL_OUT.LOCK1
IMUX_CLK_GCLK[0]	BUFPLL_INS_SN.GCLK0
IMUX_CLK_GCLK[1]	BUFPLL_INS_SN.GCLK1

Bitstream

spartan6 CLK_S rect MAIN
Bit	Frame
Bit	F0
B0	-
B1	-
B2	-
B3	-
B4	-
B5	-
B6	-
B7	-
B8	-
B9	-
B10	-
B11	-
B12	-
B13	-
B14	-
B15	-
B16	-
B17	-
B18	-
B19	-
B20	-
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	-
B28	-
B29	-
B30	-
B31	-
B32	-
B33	-
B34	-
B35	-
B36	-
B37	-
B38	-
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	-
B49	-
B50	-
B51	-
B52	-
B53	-
B54	-
B55	-
B56	-
B57	-
B58	-
B59	-
B60	-
B61	-
B62	-
B63	-
B64	-
B65	-
B66	-
B67	-
B68	-
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	-
B76	-
B77	-
B78	-
B79	-
B80	-
B81	-
B82	-
B83	-
B84	-
B85	-
B86	-
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	-
B97	-
B98	-
B99	-
B100	-
B101	-
B102	-
B103	-
B104	-
B105	-
B106	-
B107	-
B108	-
B109	-
B110	-
B111	-
B112	-
B113	-
B114	-
B115	-
B116	-
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	-
B124	-
B125	-
B126	-
B127	-
B128	-
B129	-
B130	-
B131	-
B132	-
B133	-
B134	-
B135	-
B136	-
B137	-
B138	-
B139	-
B140	-
B141	-
B142	-
B143	-
B144	-
B145	-
B146	-
B147	-
B148	-
B149	-
B150	-
B151	-
B152	-
B153	-
B154	-
B155	-
B156	-
B157	-
B158	-
B159	-
B160	-
B161	-
B162	-
B163	-
B164	-
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	-
B172	-
B173	-
B174	-
B175	-
B176	-
B177	-
B178	-
B179	-
B180	-
B181	-
B182	-
B183	-
B184	-
B185	-
B186	-
B187	-
B188	-
B189	-
B190	-
B191	-
B192	-
B193	-
B194	-
B195	-
B196	-
B197	-
B198	-
B199	-
B200	-
B201	-
B202	-
B203	-
B204	-
B205	-
B206	-
B207	-
B208	-
B209	-
B210	-
B211	-
B212	-
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	-
B220	-
B221	-
B222	-
B223	-
B224	-
B225	-
B226	-
B227	-
B228	-
B229	-
B230	-
B231	-
B232	-
B233	-
B234	-
B235	-
B236	-
B237	-
B238	-
B239	-
B240	-
B241	-
B242	-
B243	-
B244	-
B245	-
B246	-
B247	-
B248	-
B249	-
B250	-
B251	-
B252	-
B253	-
B254	-
B255	-
B256	-
B257	-
B258	-
B259	-
B260	-
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	-
B268	-
B269	-
B270	-
B271	-
B272	-
B273	-
B274	-
B275	-
B276	-
B277	-
B278	-
B279	-
B280	-
B281	-
B282	-
B283	-
B284	-
B285	-
B286	-
B287	-
B288	-
B289	-
B290	-
B291	-
B292	-
B293	-
B294	-
B295	-
B296	-
B297	-
B298	-
B299	-
B300	-
B301	-
B302	-
B303	-
B304	-
B305	-
B306	-
B307	-
B308	-
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	-
B316	-
B317	-
B318	-
B319	-
B320	-
B321	-
B322	-
B323	-
B324	-
B325	-
B326	-
B327	-
B328	-
B329	-
B330	-
B331	-
B332	-
B333	-
B334	-
B335	-
B336	-
B337	-
B338	-
B339	-
B340	-
B341	-
B342	-
B343	-
B344	-
B345	-
B346	-
B347	-
B348	-
B349	-
B350	-
B351	-
B352	-
B353	-
B354	-
B355	-
B356	-
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	-
B364	-
B365	-
B366	-
B367	-
B368	-
B369	-
B370	-
B371	-
B372	-
B373	-
B374	-
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

### Bitstream

spartan6 CLK_S rect R0
Bit	Frame
Bit	F0
B380	MISC:MISR_RESET
B379	MISC:MISR_ENABLE
B378	BUFPLL[1]:LOCKED[1]
B377	BUFPLL[1]:LOCKED[0]
B376	BUFPLL[0]:LOCKED[1]
B375	BUFPLL[0]:LOCKED[0]
B374	BUFIO2[1]:CMT_ENABLE
B373	BUFIO2[1]:CKPIN[0]
B372	BUFIO2[1]:IOCLK_ENABLE
B371	BUFIO2[1]:CKPIN[1]
B370	~BUFIO2[1]:FB_DIVIDE_BYPASS[3]
B369	~BUFIO2[1]:DIVIDE_BYPASS
B368	-
B367	BUFIO2[1]:FB_ENABLE
B366	-
B365	~BUFIO2[1]:FB_DIVIDE_BYPASS[2]
B364	~BUFIO2[1]:FB_DIVIDE_BYPASS[1]
B363	~BUFIO2[1]:FB_DIVIDE_BYPASS[0]
B362	-
B361	-
B360	-
B359	-
B358	-
B357	-
B356	BUFIO2[1]:ENABLE_2CLK
B355	BUFIO2[1]:ENABLE
B354	BUFIO2[1]:R_EDGE
B353	BUFIO2[1]:DIVIDE[2]
B352	BUFIO2[1]:DIVIDE[1]
B351	BUFIO2[1]:DIVIDE[0]
B350	-
B349	BUFIO2[1]:NEG_EDGE[1]
B348	BUFIO2[1]:NEG_EDGE[0]
B347	BUFIO2[1]:POS_EDGE[2]
B346	BUFIO2[1]:POS_EDGE[1]
B345	BUFIO2[1]:POS_EDGE[0]
B344	BUFIO2[1]:FB_I[2]
B343	BUFIO2[1]:FB_I[1]
B342	BUFIO2[1]:FB_I[0]
B341	BUFIO2[1]:IB[2]
B340	BUFIO2[1]:IB[1]
B339	BUFIO2[1]:IB[0]
B338	BUFIO2[1]:I[2]
B337	BUFIO2[1]:I[1]
B336	BUFIO2[1]:I[0]
B335	BUFPLL[1]:PLLIN[2]
B334	BUFPLL[1]:PLLIN[1]
B333	BUFPLL[1]:PLLIN[0]
B332	BUFPLL[0]:PLLIN[2]
B331	BUFPLL[0]:PLLIN[1]
B330	BUFPLL[0]:PLLIN[0]
B329	BUFPLL[1]:ENABLE_BOTH_SYNC[2]
B328	BUFPLL[1]:ENABLE_NONE_SYNC[1]
B327	-
B326	BUFIO2[0]:CMT_ENABLE
B325	BUFIO2[0]:CKPIN[0]
B324	BUFIO2[0]:IOCLK_ENABLE
B323	BUFIO2[0]:CKPIN[1]
B322	~BUFIO2[0]:FB_DIVIDE_BYPASS[3]
B321	~BUFIO2[0]:DIVIDE_BYPASS
B320	-
B319	BUFIO2[0]:FB_ENABLE
B318	-
B317	~BUFIO2[0]:FB_DIVIDE_BYPASS[2]
B316	~BUFIO2[0]:FB_DIVIDE_BYPASS[1]
B315	~BUFIO2[0]:FB_DIVIDE_BYPASS[0]
B314	-
B313	-
B312	-
B311	-
B310	-
B309	-
B308	BUFIO2[0]:ENABLE_2CLK
B307	BUFIO2[0]:ENABLE
B306	BUFIO2[0]:R_EDGE
B305	BUFIO2[0]:DIVIDE[2]
B304	BUFIO2[0]:DIVIDE[1]
B303	BUFIO2[0]:DIVIDE[0]
B302	-
B301	BUFIO2[0]:NEG_EDGE[1]
B300	BUFIO2[0]:NEG_EDGE[0]
B299	BUFIO2[0]:POS_EDGE[2]
B298	BUFIO2[0]:POS_EDGE[1]
B297	BUFIO2[0]:POS_EDGE[0]
B296	BUFIO2[0]:FB_I[2]
B295	BUFIO2[0]:FB_I[1]
B294	BUFIO2[0]:FB_I[0]
B293	BUFIO2[0]:IB[2]
B292	BUFIO2[0]:IB[1]
B291	BUFIO2[0]:IB[0]
B290	BUFIO2[0]:I[2]
B289	BUFIO2[0]:I[1]
B288	BUFIO2[0]:I[0]
B287	-
B286	BUFPLL[0]:ENABLE_BOTH_SYNC[2]
B285	BUFPLL[0]:ENABLE_NONE_SYNC[1]
B284	-
B283	-
B282	BUFPLL[1]:ENABLE_BOTH_SYNC[1]
B281	BUFPLL[1]:ENABLE_NONE_SYNC[0]
B280	BUFPLL[0]:ENABLE_BOTH_SYNC[1]
B279	BUFPLL[0]:ENABLE_NONE_SYNC[0]
B278	BUFIO2[3]:CMT_ENABLE
B277	BUFIO2[3]:CKPIN[0]
B276	BUFIO2[3]:IOCLK_ENABLE
B275	BUFIO2[3]:CKPIN[1]
B274	~BUFIO2[3]:FB_DIVIDE_BYPASS[3]
B273	~BUFIO2[3]:DIVIDE_BYPASS
B272	-
B271	BUFIO2[3]:FB_ENABLE
B270	-
B269	~BUFIO2[3]:FB_DIVIDE_BYPASS[2]
B268	~BUFIO2[3]:FB_DIVIDE_BYPASS[1]
B267	~BUFIO2[3]:FB_DIVIDE_BYPASS[0]
B266	-
B265	-
B264	-
B263	-
B262	-
B261	-
B260	BUFIO2[3]:ENABLE_2CLK
B259	BUFIO2[3]:ENABLE
B258	BUFIO2[3]:R_EDGE
B257	BUFIO2[3]:DIVIDE[2]
B256	BUFIO2[3]:DIVIDE[1]
B255	BUFIO2[3]:DIVIDE[0]
B254	-
B253	BUFIO2[3]:NEG_EDGE[1]
B252	BUFIO2[3]:NEG_EDGE[0]
B251	BUFIO2[3]:POS_EDGE[2]
B250	BUFIO2[3]:POS_EDGE[1]
B249	BUFIO2[3]:POS_EDGE[0]
B248	BUFIO2[3]:FB_I[2]
B247	BUFIO2[3]:FB_I[1]
B246	BUFIO2[3]:FB_I[0]
B245	BUFIO2[3]:IB[2]
B244	BUFIO2[3]:IB[1]
B243	BUFIO2[3]:IB[0]
B242	BUFIO2[3]:I[2]
B241	BUFIO2[3]:I[1]
B240	BUFIO2[3]:I[0]
B239	-
B238	-
B237	BUFPLL[1]:ENABLE_BOTH_SYNC[0]
B236	-
B235	-
B234	BUFPLL[0]:ENABLE_BOTH_SYNC[0]
B233	BUFPLL[1]:DIVIDE[5]
B232	BUFPLL[1]:DIVIDE[4]
B231	-
B230	BUFIO2[2]:CMT_ENABLE
B229	BUFIO2[2]:CKPIN[0]
B228	BUFIO2[2]:IOCLK_ENABLE
B227	BUFIO2[2]:CKPIN[1]
B226	~BUFIO2[2]:FB_DIVIDE_BYPASS[3]
B225	~BUFIO2[2]:DIVIDE_BYPASS
B224	-
B223	BUFIO2[2]:FB_ENABLE
B222	-
B221	~BUFIO2[2]:FB_DIVIDE_BYPASS[2]
B220	~BUFIO2[2]:FB_DIVIDE_BYPASS[1]
B219	~BUFIO2[2]:FB_DIVIDE_BYPASS[0]
B218	-
B217	-
B216	-
B215	-
B214	-
B213	-
B212	BUFIO2[2]:ENABLE_2CLK
B211	BUFIO2[2]:ENABLE
B210	BUFIO2[2]:R_EDGE
B209	BUFIO2[2]:DIVIDE[2]
B208	BUFIO2[2]:DIVIDE[1]
B207	BUFIO2[2]:DIVIDE[0]
B206	-
B205	BUFIO2[2]:NEG_EDGE[1]
B204	BUFIO2[2]:NEG_EDGE[0]
B203	BUFIO2[2]:POS_EDGE[2]
B202	BUFIO2[2]:POS_EDGE[1]
B201	BUFIO2[2]:POS_EDGE[0]
B200	BUFIO2[2]:FB_I[2]
B199	BUFIO2[2]:FB_I[1]
B198	BUFIO2[2]:FB_I[0]
B197	BUFIO2[2]:IB[2]
B196	BUFIO2[2]:IB[1]
B195	BUFIO2[2]:IB[0]
B194	BUFIO2[2]:I[2]
B193	BUFIO2[2]:I[1]
B192	BUFIO2[2]:I[0]
B191	BUFPLL[1]:DIVIDE[3]
B190	BUFPLL[0]:DIVIDE[5]
B189	BUFPLL[0]:DIVIDE[4]
B188	-
B187	BUFPLL[0]:DIVIDE[3]
B186	BUFPLL[1]:DATA_RATE[0]
B185	~BUFPLL[1]:ENABLE_SYNC
B184	BUFPLL_MCB:LOCK_SRC[0]
B183	BUFPLL[1]:DIVIDE[2]
B182	BUFIO2[5]:CMT_ENABLE
B181	BUFIO2[5]:CKPIN[0]
B180	BUFIO2[5]:IOCLK_ENABLE
B179	BUFIO2[5]:CKPIN[1]
B178	~BUFIO2[5]:FB_DIVIDE_BYPASS[3]
B177	~BUFIO2[5]:DIVIDE_BYPASS
B176	-
B175	BUFIO2[5]:FB_ENABLE
B174	-
B173	~BUFIO2[5]:FB_DIVIDE_BYPASS[2]
B172	~BUFIO2[5]:FB_DIVIDE_BYPASS[1]
B171	~BUFIO2[5]:FB_DIVIDE_BYPASS[0]
B170	-
B169	-
B168	-
B167	-
B166	-
B165	-
B164	BUFIO2[5]:ENABLE_2CLK
B163	BUFIO2[5]:ENABLE
B162	BUFIO2[5]:R_EDGE
B161	BUFIO2[5]:DIVIDE[2]
B160	BUFIO2[5]:DIVIDE[1]
B159	BUFIO2[5]:DIVIDE[0]
B158	-
B157	BUFIO2[5]:NEG_EDGE[1]
B156	BUFIO2[5]:NEG_EDGE[0]
B155	BUFIO2[5]:POS_EDGE[2]
B154	BUFIO2[5]:POS_EDGE[1]
B153	BUFIO2[5]:POS_EDGE[0]
B152	BUFIO2[5]:FB_I[2]
B151	BUFIO2[5]:FB_I[1]
B150	BUFIO2[5]:FB_I[0]
B149	BUFIO2[5]:IB[2]
B148	BUFIO2[5]:IB[1]
B147	BUFIO2[5]:IB[0]
B146	BUFIO2[5]:I[2]
B145	BUFIO2[5]:I[1]
B144	BUFIO2[5]:I[0]
B143	BUFPLL[1]:DIVIDE[1]
B142	BUFPLL[1]:DIVIDE[0]
B141	BUFPLL[0]:DATA_RATE[0]
B140	~BUFPLL[0]:ENABLE_SYNC
B139	BUFPLL_MCB:LOCK_SRC[1]
B138	BUFPLL[0]:DIVIDE[2]
B137	BUFPLL[0]:DIVIDE[1]
B136	BUFPLL[0]:DIVIDE[0]
B135	BUFPLL_COMMON:ENABLE
B134	BUFIO2[4]:CMT_ENABLE
B133	BUFIO2[4]:CKPIN[0]
B132	BUFIO2[4]:IOCLK_ENABLE
B131	BUFIO2[4]:CKPIN[1]
B130	~BUFIO2[4]:FB_DIVIDE_BYPASS[3]
B129	~BUFIO2[4]:DIVIDE_BYPASS
B128	-
B127	BUFIO2[4]:FB_ENABLE
B126	-
B125	~BUFIO2[4]:FB_DIVIDE_BYPASS[2]
B124	~BUFIO2[4]:FB_DIVIDE_BYPASS[1]
B123	~BUFIO2[4]:FB_DIVIDE_BYPASS[0]
B122	-
B121	-
B120	-
B119	-
B118	-
B117	-
B116	BUFIO2[4]:ENABLE_2CLK
B115	BUFIO2[4]:ENABLE
B114	BUFIO2[4]:R_EDGE
B113	BUFIO2[4]:DIVIDE[2]
B112	BUFIO2[4]:DIVIDE[1]
B111	BUFIO2[4]:DIVIDE[0]
B110	-
B109	BUFIO2[4]:NEG_EDGE[1]
B108	BUFIO2[4]:NEG_EDGE[0]
B107	BUFIO2[4]:POS_EDGE[2]
B106	BUFIO2[4]:POS_EDGE[1]
B105	BUFIO2[4]:POS_EDGE[0]
B104	BUFIO2[4]:FB_I[2]
B103	BUFIO2[4]:FB_I[1]
B102	BUFIO2[4]:FB_I[0]
B101	BUFIO2[4]:IB[2]
B100	BUFIO2[4]:IB[1]
B99	BUFIO2[4]:IB[0]
B98	BUFIO2[4]:I[2]
B97	BUFIO2[4]:I[1]
B96	BUFIO2[4]:I[0]
B95	-
B94	-
B93	REG_INT:MUX.IMUX_CLK_GCLK[0][4]
B92	REG_INT:MUX.IMUX_CLK_GCLK[0][5]
B91	REG_INT:MUX.IMUX_CLK_GCLK[0][6]
B90	REG_INT:MUX.IMUX_CLK_GCLK[0][7]
B89	REG_INT:MUX.IMUX_CLK_GCLK[0][0]
B88	REG_INT:MUX.IMUX_CLK_GCLK[0][1]
B87	REG_INT:MUX.IMUX_CLK_GCLK[0][2]
B86	BUFIO2[7]:CMT_ENABLE
B85	BUFIO2[7]:CKPIN[0]
B84	BUFIO2[7]:IOCLK_ENABLE
B83	BUFIO2[7]:CKPIN[1]
B82	~BUFIO2[7]:FB_DIVIDE_BYPASS[3]
B81	~BUFIO2[7]:DIVIDE_BYPASS
B80	-
B79	BUFIO2[7]:FB_ENABLE
B78	-
B77	~BUFIO2[7]:FB_DIVIDE_BYPASS[2]
B76	~BUFIO2[7]:FB_DIVIDE_BYPASS[1]
B75	~BUFIO2[7]:FB_DIVIDE_BYPASS[0]
B74	-
B73	-
B72	-
B71	-
B70	-
B69	-
B68	BUFIO2[7]:ENABLE_2CLK
B67	BUFIO2[7]:ENABLE
B66	BUFIO2[7]:R_EDGE
B65	BUFIO2[7]:DIVIDE[2]
B64	BUFIO2[7]:DIVIDE[1]
B63	BUFIO2[7]:DIVIDE[0]
B62	-
B61	BUFIO2[7]:NEG_EDGE[1]
B60	BUFIO2[7]:NEG_EDGE[0]
B59	BUFIO2[7]:POS_EDGE[2]
B58	BUFIO2[7]:POS_EDGE[1]
B57	BUFIO2[7]:POS_EDGE[0]
B56	BUFIO2[7]:FB_I[2]
B55	BUFIO2[7]:FB_I[1]
B54	BUFIO2[7]:FB_I[0]
B53	BUFIO2[7]:IB[2]
B52	BUFIO2[7]:IB[1]
B51	BUFIO2[7]:IB[0]
B50	BUFIO2[7]:I[2]
B49	BUFIO2[7]:I[1]
B48	BUFIO2[7]:I[0]
B47	REG_INT:MUX.IMUX_CLK_GCLK[0][3]
B46	REG_INT:MUX.IMUX_CLK_GCLK[1][3]
B45	REG_INT:MUX.IMUX_CLK_GCLK[1][2]
B44	REG_INT:MUX.IMUX_CLK_GCLK[1][1]
B43	REG_INT:MUX.IMUX_CLK_GCLK[1][0]
B42	REG_INT:MUX.IMUX_CLK_GCLK[1][7]
B41	REG_INT:MUX.IMUX_CLK_GCLK[1][6]
B40	REG_INT:MUX.IMUX_CLK_GCLK[1][5]
B39	REG_INT:MUX.IMUX_CLK_GCLK[1][4]
B38	BUFIO2[6]:CMT_ENABLE
B37	BUFIO2[6]:CKPIN[0]
B36	BUFIO2[6]:IOCLK_ENABLE
B35	BUFIO2[6]:CKPIN[1]
B34	~BUFIO2[6]:FB_DIVIDE_BYPASS[3]
B33	~BUFIO2[6]:DIVIDE_BYPASS
B32	-
B31	BUFIO2[6]:FB_ENABLE
B30	-
B29	~BUFIO2[6]:FB_DIVIDE_BYPASS[2]
B28	~BUFIO2[6]:FB_DIVIDE_BYPASS[1]
B27	~BUFIO2[6]:FB_DIVIDE_BYPASS[0]
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	BUFIO2[6]:ENABLE_2CLK
B19	BUFIO2[6]:ENABLE
B18	BUFIO2[6]:R_EDGE
B17	BUFIO2[6]:DIVIDE[2]
B16	BUFIO2[6]:DIVIDE[1]
B15	BUFIO2[6]:DIVIDE[0]
B14	-
B13	BUFIO2[6]:NEG_EDGE[1]
B12	BUFIO2[6]:NEG_EDGE[0]
B11	BUFIO2[6]:POS_EDGE[2]
B10	BUFIO2[6]:POS_EDGE[1]
B9	BUFIO2[6]:POS_EDGE[0]
B8	BUFIO2[6]:FB_I[2]
B7	BUFIO2[6]:FB_I[1]
B6	BUFIO2[6]:FB_I[0]
B5	BUFIO2[6]:IB[2]
B4	BUFIO2[6]:IB[1]
B3	BUFIO2[6]:IB[0]
B2	BUFIO2[6]:I[2]
B1	BUFIO2[6]:I[1]
B0	BUFIO2[6]:I[0]

BUFIO2[0]:CKPIN	0.F0.B323	0.F0.B325
BUFIO2[1]:CKPIN	0.F0.B371	0.F0.B373
BUFIO2[2]:CKPIN	0.F0.B227	0.F0.B229
BUFIO2[3]:CKPIN	0.F0.B275	0.F0.B277
BUFIO2[4]:CKPIN	0.F0.B131	0.F0.B133
BUFIO2[5]:CKPIN	0.F0.B179	0.F0.B181
BUFIO2[6]:CKPIN	0.F0.B35	0.F0.B37
BUFIO2[7]:CKPIN	0.F0.B83	0.F0.B85
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFIO2[0]:CMT_ENABLE	0.F0.B326
BUFIO2[0]:ENABLE	0.F0.B307
BUFIO2[0]:ENABLE_2CLK	0.F0.B308
BUFIO2[0]:FB_ENABLE	0.F0.B319
BUFIO2[0]:IOCLK_ENABLE	0.F0.B324
BUFIO2[0]:R_EDGE	0.F0.B306
BUFIO2[1]:CMT_ENABLE	0.F0.B374
BUFIO2[1]:ENABLE	0.F0.B355
BUFIO2[1]:ENABLE_2CLK	0.F0.B356
BUFIO2[1]:FB_ENABLE	0.F0.B367
BUFIO2[1]:IOCLK_ENABLE	0.F0.B372
BUFIO2[1]:R_EDGE	0.F0.B354
BUFIO2[2]:CMT_ENABLE	0.F0.B230
BUFIO2[2]:ENABLE	0.F0.B211
BUFIO2[2]:ENABLE_2CLK	0.F0.B212
BUFIO2[2]:FB_ENABLE	0.F0.B223
BUFIO2[2]:IOCLK_ENABLE	0.F0.B228
BUFIO2[2]:R_EDGE	0.F0.B210
BUFIO2[3]:CMT_ENABLE	0.F0.B278
BUFIO2[3]:ENABLE	0.F0.B259
BUFIO2[3]:ENABLE_2CLK	0.F0.B260
BUFIO2[3]:FB_ENABLE	0.F0.B271
BUFIO2[3]:IOCLK_ENABLE	0.F0.B276
BUFIO2[3]:R_EDGE	0.F0.B258
BUFIO2[4]:CMT_ENABLE	0.F0.B134
BUFIO2[4]:ENABLE	0.F0.B115
BUFIO2[4]:ENABLE_2CLK	0.F0.B116
BUFIO2[4]:FB_ENABLE	0.F0.B127
BUFIO2[4]:IOCLK_ENABLE	0.F0.B132
BUFIO2[4]:R_EDGE	0.F0.B114
BUFIO2[5]:CMT_ENABLE	0.F0.B182
BUFIO2[5]:ENABLE	0.F0.B163
BUFIO2[5]:ENABLE_2CLK	0.F0.B164
BUFIO2[5]:FB_ENABLE	0.F0.B175
BUFIO2[5]:IOCLK_ENABLE	0.F0.B180
BUFIO2[5]:R_EDGE	0.F0.B162
BUFIO2[6]:CMT_ENABLE	0.F0.B38
BUFIO2[6]:ENABLE	0.F0.B19
BUFIO2[6]:ENABLE_2CLK	0.F0.B20
BUFIO2[6]:FB_ENABLE	0.F0.B31
BUFIO2[6]:IOCLK_ENABLE	0.F0.B36
BUFIO2[6]:R_EDGE	0.F0.B18
BUFIO2[7]:CMT_ENABLE	0.F0.B86
BUFIO2[7]:ENABLE	0.F0.B67
BUFIO2[7]:ENABLE_2CLK	0.F0.B68
BUFIO2[7]:FB_ENABLE	0.F0.B79
BUFIO2[7]:IOCLK_ENABLE	0.F0.B84
BUFIO2[7]:R_EDGE	0.F0.B66
BUFPLL_COMMON:ENABLE	0.F0.B135
MISC:MISR_ENABLE	0.F0.B379
MISC:MISR_RESET	0.F0.B380
non-inverted	[0]

BUFIO2[0]:DIVIDE	0.F0.B305	0.F0.B304	0.F0.B303
BUFIO2[1]:DIVIDE	0.F0.B353	0.F0.B352	0.F0.B351
BUFIO2[2]:DIVIDE	0.F0.B209	0.F0.B208	0.F0.B207
BUFIO2[3]:DIVIDE	0.F0.B257	0.F0.B256	0.F0.B255
BUFIO2[4]:DIVIDE	0.F0.B113	0.F0.B112	0.F0.B111
BUFIO2[5]:DIVIDE	0.F0.B161	0.F0.B160	0.F0.B159
BUFIO2[6]:DIVIDE	0.F0.B17	0.F0.B16	0.F0.B15
BUFIO2[7]:DIVIDE	0.F0.B65	0.F0.B64	0.F0.B63
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2[0]:DIVIDE_BYPASS	0.F0.B321
BUFIO2[1]:DIVIDE_BYPASS	0.F0.B369
BUFIO2[2]:DIVIDE_BYPASS	0.F0.B225
BUFIO2[3]:DIVIDE_BYPASS	0.F0.B273
BUFIO2[4]:DIVIDE_BYPASS	0.F0.B129
BUFIO2[5]:DIVIDE_BYPASS	0.F0.B177
BUFIO2[6]:DIVIDE_BYPASS	0.F0.B33
BUFIO2[7]:DIVIDE_BYPASS	0.F0.B81
BUFPLL[0]:ENABLE_SYNC	0.F0.B140
BUFPLL[1]:ENABLE_SYNC	0.F0.B185
inverted	~[0]

BUFIO2[0]:FB_DIVIDE_BYPASS	0.F0.B322	0.F0.B317	0.F0.B316	0.F0.B315
BUFIO2[1]:FB_DIVIDE_BYPASS	0.F0.B370	0.F0.B365	0.F0.B364	0.F0.B363
BUFIO2[2]:FB_DIVIDE_BYPASS	0.F0.B226	0.F0.B221	0.F0.B220	0.F0.B219
BUFIO2[3]:FB_DIVIDE_BYPASS	0.F0.B274	0.F0.B269	0.F0.B268	0.F0.B267
BUFIO2[4]:FB_DIVIDE_BYPASS	0.F0.B130	0.F0.B125	0.F0.B124	0.F0.B123
BUFIO2[5]:FB_DIVIDE_BYPASS	0.F0.B178	0.F0.B173	0.F0.B172	0.F0.B171
BUFIO2[6]:FB_DIVIDE_BYPASS	0.F0.B34	0.F0.B29	0.F0.B28	0.F0.B27
BUFIO2[7]:FB_DIVIDE_BYPASS	0.F0.B82	0.F0.B77	0.F0.B76	0.F0.B75
inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2[0]:FB_I	0.F0.B296	0.F0.B295	0.F0.B294
BUFIO2[1]:FB_I	0.F0.B344	0.F0.B343	0.F0.B342
BUFIO2[2]:FB_I	0.F0.B200	0.F0.B199	0.F0.B198
BUFIO2[3]:FB_I	0.F0.B248	0.F0.B247	0.F0.B246
BUFIO2[4]:FB_I	0.F0.B104	0.F0.B103	0.F0.B102
BUFIO2[5]:FB_I	0.F0.B152	0.F0.B151	0.F0.B150
BUFIO2[6]:FB_I	0.F0.B8	0.F0.B7	0.F0.B6
BUFIO2[7]:FB_I	0.F0.B56	0.F0.B55	0.F0.B54
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2[0]:I	0.F0.B290	0.F0.B289	0.F0.B288
BUFIO2[1]:I	0.F0.B338	0.F0.B337	0.F0.B336
BUFIO2[2]:I	0.F0.B194	0.F0.B193	0.F0.B192
BUFIO2[3]:I	0.F0.B242	0.F0.B241	0.F0.B240
BUFIO2[4]:I	0.F0.B98	0.F0.B97	0.F0.B96
BUFIO2[5]:I	0.F0.B146	0.F0.B145	0.F0.B144
BUFIO2[6]:I	0.F0.B2	0.F0.B1	0.F0.B0
BUFIO2[7]:I	0.F0.B50	0.F0.B49	0.F0.B48
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2[0]:IB	0.F0.B293	0.F0.B292	0.F0.B291
BUFIO2[1]:IB	0.F0.B341	0.F0.B340	0.F0.B339
BUFIO2[2]:IB	0.F0.B197	0.F0.B196	0.F0.B195
BUFIO2[3]:IB	0.F0.B245	0.F0.B244	0.F0.B243
BUFIO2[4]:IB	0.F0.B101	0.F0.B100	0.F0.B99
BUFIO2[5]:IB	0.F0.B149	0.F0.B148	0.F0.B147
BUFIO2[6]:IB	0.F0.B5	0.F0.B4	0.F0.B3
BUFIO2[7]:IB	0.F0.B53	0.F0.B52	0.F0.B51
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2[0]:NEG_EDGE	0.F0.B301	0.F0.B300
BUFIO2[1]:NEG_EDGE	0.F0.B349	0.F0.B348
BUFIO2[2]:NEG_EDGE	0.F0.B205	0.F0.B204
BUFIO2[3]:NEG_EDGE	0.F0.B253	0.F0.B252
BUFIO2[4]:NEG_EDGE	0.F0.B109	0.F0.B108
BUFIO2[5]:NEG_EDGE	0.F0.B157	0.F0.B156
BUFIO2[6]:NEG_EDGE	0.F0.B13	0.F0.B12
BUFIO2[7]:NEG_EDGE	0.F0.B61	0.F0.B60
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2[0]:POS_EDGE	0.F0.B299	0.F0.B298	0.F0.B297
BUFIO2[1]:POS_EDGE	0.F0.B347	0.F0.B346	0.F0.B345
BUFIO2[2]:POS_EDGE	0.F0.B203	0.F0.B202	0.F0.B201
BUFIO2[3]:POS_EDGE	0.F0.B251	0.F0.B250	0.F0.B249
BUFIO2[4]:POS_EDGE	0.F0.B107	0.F0.B106	0.F0.B105
BUFIO2[5]:POS_EDGE	0.F0.B155	0.F0.B154	0.F0.B153
BUFIO2[6]:POS_EDGE	0.F0.B11	0.F0.B10	0.F0.B9
BUFIO2[7]:POS_EDGE	0.F0.B59	0.F0.B58	0.F0.B57
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFPLL[0]:DATA_RATE	0.F0.B141
BUFPLL[1]:DATA_RATE	0.F0.B186
SDR	0
DDR	1

BUFPLL[0]:DIVIDE	0.F0.B190	0.F0.B189	0.F0.B187	0.F0.B138	0.F0.B137	0.F0.B136
BUFPLL[1]:DIVIDE	0.F0.B233	0.F0.B232	0.F0.B191	0.F0.B183	0.F0.B143	0.F0.B142
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL[0]:ENABLE_BOTH_SYNC	0.F0.B286	0.F0.B280	0.F0.B234
BUFPLL[1]:ENABLE_BOTH_SYNC	0.F0.B329	0.F0.B282	0.F0.B237
non-inverted	[2]	[1]	[0]

BUFPLL[0]:ENABLE_NONE_SYNC	0.F0.B285	0.F0.B279
BUFPLL[1]:ENABLE_NONE_SYNC	0.F0.B328	0.F0.B281
non-inverted	[1]	[0]

BUFPLL[0]:LOCKED	0.F0.B376	0.F0.B375
BUFPLL[1]:LOCKED	0.F0.B378	0.F0.B377
LOCKED0	0	0
LOCKED1	0	1
LOCKED2	1	0

BUFPLL[0]:PLLIN	0.F0.B332	0.F0.B331	0.F0.B330
BUFPLL[1]:PLLIN	0.F0.B335	0.F0.B334	0.F0.B333
PLLIN0	0	0	0
PLLIN1	0	0	1
PLLIN2	0	1	0
PLLIN3	0	1	1
PLLIN4	1	0	0
PLLIN5	1	0	1

BUFPLL_MCB:LOCK_SRC	0.F0.B139	0.F0.B184
LOCK_TO_0	0	1
LOCK_TO_1	1	0

REG_INT:MUX.IMUX_CLK_GCLK[0]	0.F0.B90	0.F0.B91	0.F0.B92	0.F0.B93	0.F0.B47	0.F0.B87	0.F0.B88	0.F0.B89
REG_INT:MUX.IMUX_CLK_GCLK[1]	0.F0.B42	0.F0.B41	0.F0.B40	0.F0.B39	0.F0.B46	0.F0.B45	0.F0.B44	0.F0.B43
NONE	0	0	0	0	0	0	0	0
GCLK[0]	0	1	0	1	0	0	0	1
GCLK[1]	0	1	0	1	0	0	1	0
GCLK[2]	0	1	0	1	0	1	0	0
GCLK[3]	0	1	0	1	1	0	0	0
GCLK[8]	0	1	1	0	0	0	0	1
GCLK[9]	0	1	1	0	0	0	1	0
GCLK[10]	0	1	1	0	0	1	0	0
GCLK[11]	0	1	1	0	1	0	0	0
GCLK[4]	1	0	0	1	0	0	0	1
GCLK[5]	1	0	0	1	0	0	1	0
GCLK[6]	1	0	0	1	0	1	0	0
GCLK[7]	1	0	0	1	1	0	0	0
GCLK[12]	1	0	1	0	0	0	0	1
GCLK[13]	1	0	1	0	0	0	1	0
GCLK[14]	1	0	1	0	0	1	0	0
GCLK[15]	1	0	1	0	1	0	0	0

Tile CLK_N

Cells: 1

Switchbox REG_INT

spartan6 CLK_N switchbox REG_INT muxes IMUX_CLK_GCLK[0]
Bits	Destination
IMUX_CLK_GCLK[0]
	Source
GCLK[15]

spartan6 CLK_N switchbox REG_INT muxes IMUX_CLK_GCLK[1]
Bits	Destination
IMUX_CLK_GCLK[1]
	Source
GCLK[15]

Bel BUFIO2[0]

spartan6 CLK_N bel BUFIO2[0]
Pin	Direction	Wires

Bel BUFIO2[1]

spartan6 CLK_N bel BUFIO2[1]
Pin	Direction	Wires

Bel BUFIO2[2]

spartan6 CLK_N bel BUFIO2[2]
Pin	Direction	Wires

Bel BUFIO2[3]

spartan6 CLK_N bel BUFIO2[3]
Pin	Direction	Wires

Bel BUFIO2[4]

spartan6 CLK_N bel BUFIO2[4]
Pin	Direction	Wires

Bel BUFIO2[5]

spartan6 CLK_N bel BUFIO2[5]
Pin	Direction	Wires

Bel BUFIO2[6]

spartan6 CLK_N bel BUFIO2[6]
Pin	Direction	Wires

Bel BUFIO2[7]

spartan6 CLK_N bel BUFIO2[7]
Pin	Direction	Wires

Bel BUFIO2FB[0]

spartan6 CLK_N bel BUFIO2FB[0]
Pin	Direction	Wires

Bel BUFIO2FB[1]

spartan6 CLK_N bel BUFIO2FB[1]
Pin	Direction	Wires

Bel BUFIO2FB[2]

spartan6 CLK_N bel BUFIO2FB[2]
Pin	Direction	Wires

Bel BUFIO2FB[3]

spartan6 CLK_N bel BUFIO2FB[3]
Pin	Direction	Wires

Bel BUFIO2FB[4]

spartan6 CLK_N bel BUFIO2FB[4]
Pin	Direction	Wires

Bel BUFIO2FB[5]

spartan6 CLK_N bel BUFIO2FB[5]
Pin	Direction	Wires

Bel BUFIO2FB[6]

spartan6 CLK_N bel BUFIO2FB[6]
Pin	Direction	Wires

Bel BUFIO2FB[7]

spartan6 CLK_N bel BUFIO2FB[7]
Pin	Direction	Wires

Bel BUFPLL[0]

spartan6 CLK_N bel BUFPLL[0]
Pin	Direction	Wires

Bel BUFPLL[1]

spartan6 CLK_N bel BUFPLL[1]
Pin	Direction	Wires

Bel BUFPLL_MCB

spartan6 CLK_N bel BUFPLL_MCB
Pin	Direction	Wires

Bel BUFPLL_OUT

spartan6 CLK_N bel BUFPLL_OUT
Pin	Direction	Wires
LOCK0	output	OUT[18]
LOCK1	output	OUT[19]

Bel BUFPLL_INS_SN

spartan6 CLK_N bel BUFPLL_INS_SN
Pin	Direction	Wires
GCLK0	input	IMUX_CLK_GCLK[0]
GCLK1	input	IMUX_CLK_GCLK[1]

Bel BUFIO2_INS

spartan6 CLK_N bel BUFIO2_INS
Pin	Direction	Wires

Bel BUFIO2_CKPIN

spartan6 CLK_N bel BUFIO2_CKPIN
Pin	Direction	Wires

Bel BUFPLL_BUF

spartan6 CLK_N bel BUFPLL_BUF
Pin	Direction	Wires

Bel GTP_H_BUF

spartan6 CLK_N bel GTP_H_BUF
Pin	Direction	Wires

Bel TIEOFF_REG

spartan6 CLK_N bel TIEOFF_REG
Pin	Direction	Wires

Bel wires

spartan6 CLK_N bel wires
Wire	Pins
OUT[18]	BUFPLL_OUT.LOCK0
OUT[19]	BUFPLL_OUT.LOCK1
IMUX_CLK_GCLK[0]	BUFPLL_INS_SN.GCLK0
IMUX_CLK_GCLK[1]	BUFPLL_INS_SN.GCLK1

Bitstream

spartan6 CLK_N rect MAIN
Bit	Frame
Bit	F0
B0	-
B1	-
B2	-
B3	-
B4	-
B5	-
B6	-
B7	-
B8	-
B9	-
B10	-
B11	-
B12	-
B13	-
B14	-
B15	-
B16	-
B17	-
B18	-
B19	-
B20	-
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	-
B28	-
B29	-
B30	-
B31	-
B32	-
B33	-
B34	-
B35	-
B36	-
B37	-
B38	-
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	-
B49	-
B50	-
B51	-
B52	-
B53	-
B54	-
B55	-
B56	-
B57	-
B58	-
B59	-
B60	-
B61	-
B62	-
B63	-
B64	-
B65	-
B66	-
B67	-
B68	-
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	-
B76	-
B77	-
B78	-
B79	-
B80	-
B81	-
B82	-
B83	-
B84	-
B85	-
B86	-
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	-
B97	-
B98	-
B99	-
B100	-
B101	-
B102	-
B103	-
B104	-
B105	-
B106	-
B107	-
B108	-
B109	-
B110	-
B111	-
B112	-
B113	-
B114	-
B115	-
B116	-
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	-
B124	-
B125	-
B126	-
B127	-
B128	-
B129	-
B130	-
B131	-
B132	-
B133	-
B134	-
B135	-
B136	-
B137	-
B138	-
B139	-
B140	-
B141	-
B142	-
B143	-
B144	-
B145	-
B146	-
B147	-
B148	-
B149	-
B150	-
B151	-
B152	-
B153	-
B154	-
B155	-
B156	-
B157	-
B158	-
B159	-
B160	-
B161	-
B162	-
B163	-
B164	-
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	-
B172	-
B173	-
B174	-
B175	-
B176	-
B177	-
B178	-
B179	-
B180	-
B181	-
B182	-
B183	-
B184	-
B185	-
B186	-
B187	-
B188	-
B189	-
B190	-
B191	-
B192	-
B193	-
B194	-
B195	-
B196	-
B197	-
B198	-
B199	-
B200	-
B201	-
B202	-
B203	-
B204	-
B205	-
B206	-
B207	-
B208	-
B209	-
B210	-
B211	-
B212	-
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	-
B220	-
B221	-
B222	-
B223	-
B224	-
B225	-
B226	-
B227	-
B228	-
B229	-
B230	-
B231	-
B232	-
B233	-
B234	-
B235	-
B236	-
B237	-
B238	-
B239	-
B240	-
B241	-
B242	-
B243	-
B244	-
B245	-
B246	-
B247	-
B248	-
B249	-
B250	-
B251	-
B252	-
B253	-
B254	-
B255	-
B256	-
B257	-
B258	-
B259	-
B260	-
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	-
B268	-
B269	-
B270	-
B271	-
B272	-
B273	-
B274	-
B275	-
B276	-
B277	-
B278	-
B279	-
B280	-
B281	-
B282	-
B283	-
B284	-
B285	-
B286	-
B287	-
B288	-
B289	-
B290	-
B291	-
B292	-
B293	-
B294	-
B295	-
B296	-
B297	-
B298	-
B299	-
B300	-
B301	-
B302	-
B303	-
B304	-
B305	-
B306	-
B307	-
B308	-
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	-
B316	-
B317	-
B318	-
B319	-
B320	-
B321	-
B322	-
B323	-
B324	-
B325	-
B326	-
B327	-
B328	-
B329	-
B330	-
B331	-
B332	-
B333	-
B334	-
B335	-
B336	-
B337	-
B338	-
B339	-
B340	-
B341	-
B342	-
B343	-
B344	-
B345	-
B346	-
B347	-
B348	-
B349	-
B350	-
B351	-
B352	-
B353	-
B354	-
B355	-
B356	-
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	-
B364	-
B365	-
B366	-
B367	-
B368	-
B369	-
B370	-
B371	-
B372	-
B373	-
B374	-
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

### Bitstream

spartan6 CLK_N rect R0
Bit	Frame
Bit	F0
B380	MISC:MISR_RESET
B379	MISC:MISR_ENABLE
B378	BUFPLL[1]:LOCKED[1]
B377	BUFPLL[1]:LOCKED[0]
B376	BUFPLL[0]:LOCKED[1]
B375	BUFPLL[0]:LOCKED[0]
B374	BUFIO2[1]:CMT_ENABLE
B373	BUFIO2[1]:CKPIN[0]
B372	BUFIO2[1]:IOCLK_ENABLE
B371	BUFIO2[1]:CKPIN[1]
B370	~BUFIO2[1]:FB_DIVIDE_BYPASS[3]
B369	~BUFIO2[1]:DIVIDE_BYPASS
B368	-
B367	BUFIO2[1]:FB_ENABLE
B366	-
B365	~BUFIO2[1]:FB_DIVIDE_BYPASS[2]
B364	~BUFIO2[1]:FB_DIVIDE_BYPASS[1]
B363	~BUFIO2[1]:FB_DIVIDE_BYPASS[0]
B362	-
B361	-
B360	-
B359	-
B358	-
B357	-
B356	BUFIO2[1]:ENABLE_2CLK
B355	BUFIO2[1]:ENABLE
B354	BUFIO2[1]:R_EDGE
B353	BUFIO2[1]:DIVIDE[2]
B352	BUFIO2[1]:DIVIDE[1]
B351	BUFIO2[1]:DIVIDE[0]
B350	-
B349	BUFIO2[1]:NEG_EDGE[1]
B348	BUFIO2[1]:NEG_EDGE[0]
B347	BUFIO2[1]:POS_EDGE[2]
B346	BUFIO2[1]:POS_EDGE[1]
B345	BUFIO2[1]:POS_EDGE[0]
B344	BUFIO2[1]:FB_I[2]
B343	BUFIO2[1]:FB_I[1]
B342	BUFIO2[1]:FB_I[0]
B341	BUFIO2[1]:IB[2]
B340	BUFIO2[1]:IB[1]
B339	BUFIO2[1]:IB[0]
B338	BUFIO2[1]:I[2]
B337	BUFIO2[1]:I[1]
B336	BUFIO2[1]:I[0]
B335	BUFPLL[1]:PLLIN[2]
B334	BUFPLL[1]:PLLIN[1]
B333	BUFPLL[1]:PLLIN[0]
B332	BUFPLL[0]:PLLIN[2]
B331	BUFPLL[0]:PLLIN[1]
B330	BUFPLL[0]:PLLIN[0]
B329	BUFPLL[1]:ENABLE_BOTH_SYNC[2]
B328	BUFPLL[1]:ENABLE_NONE_SYNC[1]
B327	-
B326	BUFIO2[0]:CMT_ENABLE
B325	BUFIO2[0]:CKPIN[0]
B324	BUFIO2[0]:IOCLK_ENABLE
B323	BUFIO2[0]:CKPIN[1]
B322	~BUFIO2[0]:FB_DIVIDE_BYPASS[3]
B321	~BUFIO2[0]:DIVIDE_BYPASS
B320	-
B319	BUFIO2[0]:FB_ENABLE
B318	-
B317	~BUFIO2[0]:FB_DIVIDE_BYPASS[2]
B316	~BUFIO2[0]:FB_DIVIDE_BYPASS[1]
B315	~BUFIO2[0]:FB_DIVIDE_BYPASS[0]
B314	-
B313	-
B312	-
B311	-
B310	-
B309	-
B308	BUFIO2[0]:ENABLE_2CLK
B307	BUFIO2[0]:ENABLE
B306	BUFIO2[0]:R_EDGE
B305	BUFIO2[0]:DIVIDE[2]
B304	BUFIO2[0]:DIVIDE[1]
B303	BUFIO2[0]:DIVIDE[0]
B302	-
B301	BUFIO2[0]:NEG_EDGE[1]
B300	BUFIO2[0]:NEG_EDGE[0]
B299	BUFIO2[0]:POS_EDGE[2]
B298	BUFIO2[0]:POS_EDGE[1]
B297	BUFIO2[0]:POS_EDGE[0]
B296	BUFIO2[0]:FB_I[2]
B295	BUFIO2[0]:FB_I[1]
B294	BUFIO2[0]:FB_I[0]
B293	BUFIO2[0]:IB[2]
B292	BUFIO2[0]:IB[1]
B291	BUFIO2[0]:IB[0]
B290	BUFIO2[0]:I[2]
B289	BUFIO2[0]:I[1]
B288	BUFIO2[0]:I[0]
B287	-
B286	BUFPLL[0]:ENABLE_BOTH_SYNC[2]
B285	BUFPLL[0]:ENABLE_NONE_SYNC[1]
B284	-
B283	-
B282	BUFPLL[1]:ENABLE_BOTH_SYNC[1]
B281	BUFPLL[1]:ENABLE_NONE_SYNC[0]
B280	BUFPLL[0]:ENABLE_BOTH_SYNC[1]
B279	BUFPLL[0]:ENABLE_NONE_SYNC[0]
B278	BUFIO2[3]:CMT_ENABLE
B277	BUFIO2[3]:CKPIN[0]
B276	BUFIO2[3]:IOCLK_ENABLE
B275	BUFIO2[3]:CKPIN[1]
B274	~BUFIO2[3]:FB_DIVIDE_BYPASS[3]
B273	~BUFIO2[3]:DIVIDE_BYPASS
B272	-
B271	BUFIO2[3]:FB_ENABLE
B270	-
B269	~BUFIO2[3]:FB_DIVIDE_BYPASS[2]
B268	~BUFIO2[3]:FB_DIVIDE_BYPASS[1]
B267	~BUFIO2[3]:FB_DIVIDE_BYPASS[0]
B266	-
B265	-
B264	-
B263	-
B262	-
B261	-
B260	BUFIO2[3]:ENABLE_2CLK
B259	BUFIO2[3]:ENABLE
B258	BUFIO2[3]:R_EDGE
B257	BUFIO2[3]:DIVIDE[2]
B256	BUFIO2[3]:DIVIDE[1]
B255	BUFIO2[3]:DIVIDE[0]
B254	-
B253	BUFIO2[3]:NEG_EDGE[1]
B252	BUFIO2[3]:NEG_EDGE[0]
B251	BUFIO2[3]:POS_EDGE[2]
B250	BUFIO2[3]:POS_EDGE[1]
B249	BUFIO2[3]:POS_EDGE[0]
B248	BUFIO2[3]:FB_I[2]
B247	BUFIO2[3]:FB_I[1]
B246	BUFIO2[3]:FB_I[0]
B245	BUFIO2[3]:IB[2]
B244	BUFIO2[3]:IB[1]
B243	BUFIO2[3]:IB[0]
B242	BUFIO2[3]:I[2]
B241	BUFIO2[3]:I[1]
B240	BUFIO2[3]:I[0]
B239	-
B238	-
B237	BUFPLL[1]:ENABLE_BOTH_SYNC[0]
B236	-
B235	-
B234	BUFPLL[0]:ENABLE_BOTH_SYNC[0]
B233	BUFPLL[1]:DIVIDE[5]
B232	BUFPLL[1]:DIVIDE[4]
B231	-
B230	BUFIO2[2]:CMT_ENABLE
B229	BUFIO2[2]:CKPIN[0]
B228	BUFIO2[2]:IOCLK_ENABLE
B227	BUFIO2[2]:CKPIN[1]
B226	~BUFIO2[2]:FB_DIVIDE_BYPASS[3]
B225	~BUFIO2[2]:DIVIDE_BYPASS
B224	-
B223	BUFIO2[2]:FB_ENABLE
B222	-
B221	~BUFIO2[2]:FB_DIVIDE_BYPASS[2]
B220	~BUFIO2[2]:FB_DIVIDE_BYPASS[1]
B219	~BUFIO2[2]:FB_DIVIDE_BYPASS[0]
B218	-
B217	-
B216	-
B215	-
B214	-
B213	-
B212	BUFIO2[2]:ENABLE_2CLK
B211	BUFIO2[2]:ENABLE
B210	BUFIO2[2]:R_EDGE
B209	BUFIO2[2]:DIVIDE[2]
B208	BUFIO2[2]:DIVIDE[1]
B207	BUFIO2[2]:DIVIDE[0]
B206	-
B205	BUFIO2[2]:NEG_EDGE[1]
B204	BUFIO2[2]:NEG_EDGE[0]
B203	BUFIO2[2]:POS_EDGE[2]
B202	BUFIO2[2]:POS_EDGE[1]
B201	BUFIO2[2]:POS_EDGE[0]
B200	BUFIO2[2]:FB_I[2]
B199	BUFIO2[2]:FB_I[1]
B198	BUFIO2[2]:FB_I[0]
B197	BUFIO2[2]:IB[2]
B196	BUFIO2[2]:IB[1]
B195	BUFIO2[2]:IB[0]
B194	BUFIO2[2]:I[2]
B193	BUFIO2[2]:I[1]
B192	BUFIO2[2]:I[0]
B191	BUFPLL[1]:DIVIDE[3]
B190	BUFPLL[0]:DIVIDE[5]
B189	BUFPLL[0]:DIVIDE[4]
B188	-
B187	BUFPLL[0]:DIVIDE[3]
B186	BUFPLL[1]:DATA_RATE[0]
B185	~BUFPLL[1]:ENABLE_SYNC
B184	BUFPLL_MCB:LOCK_SRC[0]
B183	BUFPLL[1]:DIVIDE[2]
B182	BUFIO2[5]:CMT_ENABLE
B181	BUFIO2[5]:CKPIN[0]
B180	BUFIO2[5]:IOCLK_ENABLE
B179	BUFIO2[5]:CKPIN[1]
B178	~BUFIO2[5]:FB_DIVIDE_BYPASS[3]
B177	~BUFIO2[5]:DIVIDE_BYPASS
B176	-
B175	BUFIO2[5]:FB_ENABLE
B174	-
B173	~BUFIO2[5]:FB_DIVIDE_BYPASS[2]
B172	~BUFIO2[5]:FB_DIVIDE_BYPASS[1]
B171	~BUFIO2[5]:FB_DIVIDE_BYPASS[0]
B170	-
B169	-
B168	-
B167	-
B166	-
B165	-
B164	BUFIO2[5]:ENABLE_2CLK
B163	BUFIO2[5]:ENABLE
B162	BUFIO2[5]:R_EDGE
B161	BUFIO2[5]:DIVIDE[2]
B160	BUFIO2[5]:DIVIDE[1]
B159	BUFIO2[5]:DIVIDE[0]
B158	-
B157	BUFIO2[5]:NEG_EDGE[1]
B156	BUFIO2[5]:NEG_EDGE[0]
B155	BUFIO2[5]:POS_EDGE[2]
B154	BUFIO2[5]:POS_EDGE[1]
B153	BUFIO2[5]:POS_EDGE[0]
B152	BUFIO2[5]:FB_I[2]
B151	BUFIO2[5]:FB_I[1]
B150	BUFIO2[5]:FB_I[0]
B149	BUFIO2[5]:IB[2]
B148	BUFIO2[5]:IB[1]
B147	BUFIO2[5]:IB[0]
B146	BUFIO2[5]:I[2]
B145	BUFIO2[5]:I[1]
B144	BUFIO2[5]:I[0]
B143	BUFPLL[1]:DIVIDE[1]
B142	BUFPLL[1]:DIVIDE[0]
B141	BUFPLL[0]:DATA_RATE[0]
B140	~BUFPLL[0]:ENABLE_SYNC
B139	BUFPLL_MCB:LOCK_SRC[1]
B138	BUFPLL[0]:DIVIDE[2]
B137	BUFPLL[0]:DIVIDE[1]
B136	BUFPLL[0]:DIVIDE[0]
B135	BUFPLL_COMMON:ENABLE
B134	BUFIO2[4]:CMT_ENABLE
B133	BUFIO2[4]:CKPIN[0]
B132	BUFIO2[4]:IOCLK_ENABLE
B131	BUFIO2[4]:CKPIN[1]
B130	~BUFIO2[4]:FB_DIVIDE_BYPASS[3]
B129	~BUFIO2[4]:DIVIDE_BYPASS
B128	-
B127	BUFIO2[4]:FB_ENABLE
B126	-
B125	~BUFIO2[4]:FB_DIVIDE_BYPASS[2]
B124	~BUFIO2[4]:FB_DIVIDE_BYPASS[1]
B123	~BUFIO2[4]:FB_DIVIDE_BYPASS[0]
B122	-
B121	-
B120	-
B119	-
B118	-
B117	-
B116	BUFIO2[4]:ENABLE_2CLK
B115	BUFIO2[4]:ENABLE
B114	BUFIO2[4]:R_EDGE
B113	BUFIO2[4]:DIVIDE[2]
B112	BUFIO2[4]:DIVIDE[1]
B111	BUFIO2[4]:DIVIDE[0]
B110	-
B109	BUFIO2[4]:NEG_EDGE[1]
B108	BUFIO2[4]:NEG_EDGE[0]
B107	BUFIO2[4]:POS_EDGE[2]
B106	BUFIO2[4]:POS_EDGE[1]
B105	BUFIO2[4]:POS_EDGE[0]
B104	BUFIO2[4]:FB_I[2]
B103	BUFIO2[4]:FB_I[1]
B102	BUFIO2[4]:FB_I[0]
B101	BUFIO2[4]:IB[2]
B100	BUFIO2[4]:IB[1]
B99	BUFIO2[4]:IB[0]
B98	BUFIO2[4]:I[2]
B97	BUFIO2[4]:I[1]
B96	BUFIO2[4]:I[0]
B95	-
B94	-
B93	REG_INT:MUX.IMUX_CLK_GCLK[0][4]
B92	REG_INT:MUX.IMUX_CLK_GCLK[0][5]
B91	REG_INT:MUX.IMUX_CLK_GCLK[0][6]
B90	REG_INT:MUX.IMUX_CLK_GCLK[0][7]
B89	REG_INT:MUX.IMUX_CLK_GCLK[0][0]
B88	REG_INT:MUX.IMUX_CLK_GCLK[0][1]
B87	REG_INT:MUX.IMUX_CLK_GCLK[0][2]
B86	BUFIO2[7]:CMT_ENABLE
B85	BUFIO2[7]:CKPIN[0]
B84	BUFIO2[7]:IOCLK_ENABLE
B83	BUFIO2[7]:CKPIN[1]
B82	~BUFIO2[7]:FB_DIVIDE_BYPASS[3]
B81	~BUFIO2[7]:DIVIDE_BYPASS
B80	-
B79	BUFIO2[7]:FB_ENABLE
B78	-
B77	~BUFIO2[7]:FB_DIVIDE_BYPASS[2]
B76	~BUFIO2[7]:FB_DIVIDE_BYPASS[1]
B75	~BUFIO2[7]:FB_DIVIDE_BYPASS[0]
B74	-
B73	-
B72	-
B71	-
B70	-
B69	-
B68	BUFIO2[7]:ENABLE_2CLK
B67	BUFIO2[7]:ENABLE
B66	BUFIO2[7]:R_EDGE
B65	BUFIO2[7]:DIVIDE[2]
B64	BUFIO2[7]:DIVIDE[1]
B63	BUFIO2[7]:DIVIDE[0]
B62	-
B61	BUFIO2[7]:NEG_EDGE[1]
B60	BUFIO2[7]:NEG_EDGE[0]
B59	BUFIO2[7]:POS_EDGE[2]
B58	BUFIO2[7]:POS_EDGE[1]
B57	BUFIO2[7]:POS_EDGE[0]
B56	BUFIO2[7]:FB_I[2]
B55	BUFIO2[7]:FB_I[1]
B54	BUFIO2[7]:FB_I[0]
B53	BUFIO2[7]:IB[2]
B52	BUFIO2[7]:IB[1]
B51	BUFIO2[7]:IB[0]
B50	BUFIO2[7]:I[2]
B49	BUFIO2[7]:I[1]
B48	BUFIO2[7]:I[0]
B47	REG_INT:MUX.IMUX_CLK_GCLK[0][3]
B46	REG_INT:MUX.IMUX_CLK_GCLK[1][3]
B45	REG_INT:MUX.IMUX_CLK_GCLK[1][2]
B44	REG_INT:MUX.IMUX_CLK_GCLK[1][1]
B43	REG_INT:MUX.IMUX_CLK_GCLK[1][0]
B42	REG_INT:MUX.IMUX_CLK_GCLK[1][7]
B41	REG_INT:MUX.IMUX_CLK_GCLK[1][6]
B40	REG_INT:MUX.IMUX_CLK_GCLK[1][5]
B39	REG_INT:MUX.IMUX_CLK_GCLK[1][4]
B38	BUFIO2[6]:CMT_ENABLE
B37	BUFIO2[6]:CKPIN[0]
B36	BUFIO2[6]:IOCLK_ENABLE
B35	BUFIO2[6]:CKPIN[1]
B34	~BUFIO2[6]:FB_DIVIDE_BYPASS[3]
B33	~BUFIO2[6]:DIVIDE_BYPASS
B32	-
B31	BUFIO2[6]:FB_ENABLE
B30	-
B29	~BUFIO2[6]:FB_DIVIDE_BYPASS[2]
B28	~BUFIO2[6]:FB_DIVIDE_BYPASS[1]
B27	~BUFIO2[6]:FB_DIVIDE_BYPASS[0]
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	BUFIO2[6]:ENABLE_2CLK
B19	BUFIO2[6]:ENABLE
B18	BUFIO2[6]:R_EDGE
B17	BUFIO2[6]:DIVIDE[2]
B16	BUFIO2[6]:DIVIDE[1]
B15	BUFIO2[6]:DIVIDE[0]
B14	-
B13	BUFIO2[6]:NEG_EDGE[1]
B12	BUFIO2[6]:NEG_EDGE[0]
B11	BUFIO2[6]:POS_EDGE[2]
B10	BUFIO2[6]:POS_EDGE[1]
B9	BUFIO2[6]:POS_EDGE[0]
B8	BUFIO2[6]:FB_I[2]
B7	BUFIO2[6]:FB_I[1]
B6	BUFIO2[6]:FB_I[0]
B5	BUFIO2[6]:IB[2]
B4	BUFIO2[6]:IB[1]
B3	BUFIO2[6]:IB[0]
B2	BUFIO2[6]:I[2]
B1	BUFIO2[6]:I[1]
B0	BUFIO2[6]:I[0]

BUFIO2[0]:CKPIN	0.F0.B323	0.F0.B325
BUFIO2[1]:CKPIN	0.F0.B371	0.F0.B373
BUFIO2[2]:CKPIN	0.F0.B227	0.F0.B229
BUFIO2[3]:CKPIN	0.F0.B275	0.F0.B277
BUFIO2[4]:CKPIN	0.F0.B131	0.F0.B133
BUFIO2[5]:CKPIN	0.F0.B179	0.F0.B181
BUFIO2[6]:CKPIN	0.F0.B35	0.F0.B37
BUFIO2[7]:CKPIN	0.F0.B83	0.F0.B85
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFIO2[0]:CMT_ENABLE	0.F0.B326
BUFIO2[0]:ENABLE	0.F0.B307
BUFIO2[0]:ENABLE_2CLK	0.F0.B308
BUFIO2[0]:FB_ENABLE	0.F0.B319
BUFIO2[0]:IOCLK_ENABLE	0.F0.B324
BUFIO2[0]:R_EDGE	0.F0.B306
BUFIO2[1]:CMT_ENABLE	0.F0.B374
BUFIO2[1]:ENABLE	0.F0.B355
BUFIO2[1]:ENABLE_2CLK	0.F0.B356
BUFIO2[1]:FB_ENABLE	0.F0.B367
BUFIO2[1]:IOCLK_ENABLE	0.F0.B372
BUFIO2[1]:R_EDGE	0.F0.B354
BUFIO2[2]:CMT_ENABLE	0.F0.B230
BUFIO2[2]:ENABLE	0.F0.B211
BUFIO2[2]:ENABLE_2CLK	0.F0.B212
BUFIO2[2]:FB_ENABLE	0.F0.B223
BUFIO2[2]:IOCLK_ENABLE	0.F0.B228
BUFIO2[2]:R_EDGE	0.F0.B210
BUFIO2[3]:CMT_ENABLE	0.F0.B278
BUFIO2[3]:ENABLE	0.F0.B259
BUFIO2[3]:ENABLE_2CLK	0.F0.B260
BUFIO2[3]:FB_ENABLE	0.F0.B271
BUFIO2[3]:IOCLK_ENABLE	0.F0.B276
BUFIO2[3]:R_EDGE	0.F0.B258
BUFIO2[4]:CMT_ENABLE	0.F0.B134
BUFIO2[4]:ENABLE	0.F0.B115
BUFIO2[4]:ENABLE_2CLK	0.F0.B116
BUFIO2[4]:FB_ENABLE	0.F0.B127
BUFIO2[4]:IOCLK_ENABLE	0.F0.B132
BUFIO2[4]:R_EDGE	0.F0.B114
BUFIO2[5]:CMT_ENABLE	0.F0.B182
BUFIO2[5]:ENABLE	0.F0.B163
BUFIO2[5]:ENABLE_2CLK	0.F0.B164
BUFIO2[5]:FB_ENABLE	0.F0.B175
BUFIO2[5]:IOCLK_ENABLE	0.F0.B180
BUFIO2[5]:R_EDGE	0.F0.B162
BUFIO2[6]:CMT_ENABLE	0.F0.B38
BUFIO2[6]:ENABLE	0.F0.B19
BUFIO2[6]:ENABLE_2CLK	0.F0.B20
BUFIO2[6]:FB_ENABLE	0.F0.B31
BUFIO2[6]:IOCLK_ENABLE	0.F0.B36
BUFIO2[6]:R_EDGE	0.F0.B18
BUFIO2[7]:CMT_ENABLE	0.F0.B86
BUFIO2[7]:ENABLE	0.F0.B67
BUFIO2[7]:ENABLE_2CLK	0.F0.B68
BUFIO2[7]:FB_ENABLE	0.F0.B79
BUFIO2[7]:IOCLK_ENABLE	0.F0.B84
BUFIO2[7]:R_EDGE	0.F0.B66
BUFPLL_COMMON:ENABLE	0.F0.B135
MISC:MISR_ENABLE	0.F0.B379
MISC:MISR_RESET	0.F0.B380
non-inverted	[0]

BUFIO2[0]:DIVIDE	0.F0.B305	0.F0.B304	0.F0.B303
BUFIO2[1]:DIVIDE	0.F0.B353	0.F0.B352	0.F0.B351
BUFIO2[2]:DIVIDE	0.F0.B209	0.F0.B208	0.F0.B207
BUFIO2[3]:DIVIDE	0.F0.B257	0.F0.B256	0.F0.B255
BUFIO2[4]:DIVIDE	0.F0.B113	0.F0.B112	0.F0.B111
BUFIO2[5]:DIVIDE	0.F0.B161	0.F0.B160	0.F0.B159
BUFIO2[6]:DIVIDE	0.F0.B17	0.F0.B16	0.F0.B15
BUFIO2[7]:DIVIDE	0.F0.B65	0.F0.B64	0.F0.B63
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2[0]:DIVIDE_BYPASS	0.F0.B321
BUFIO2[1]:DIVIDE_BYPASS	0.F0.B369
BUFIO2[2]:DIVIDE_BYPASS	0.F0.B225
BUFIO2[3]:DIVIDE_BYPASS	0.F0.B273
BUFIO2[4]:DIVIDE_BYPASS	0.F0.B129
BUFIO2[5]:DIVIDE_BYPASS	0.F0.B177
BUFIO2[6]:DIVIDE_BYPASS	0.F0.B33
BUFIO2[7]:DIVIDE_BYPASS	0.F0.B81
BUFPLL[0]:ENABLE_SYNC	0.F0.B140
BUFPLL[1]:ENABLE_SYNC	0.F0.B185
inverted	~[0]

BUFIO2[0]:FB_DIVIDE_BYPASS	0.F0.B322	0.F0.B317	0.F0.B316	0.F0.B315
BUFIO2[1]:FB_DIVIDE_BYPASS	0.F0.B370	0.F0.B365	0.F0.B364	0.F0.B363
BUFIO2[2]:FB_DIVIDE_BYPASS	0.F0.B226	0.F0.B221	0.F0.B220	0.F0.B219
BUFIO2[3]:FB_DIVIDE_BYPASS	0.F0.B274	0.F0.B269	0.F0.B268	0.F0.B267
BUFIO2[4]:FB_DIVIDE_BYPASS	0.F0.B130	0.F0.B125	0.F0.B124	0.F0.B123
BUFIO2[5]:FB_DIVIDE_BYPASS	0.F0.B178	0.F0.B173	0.F0.B172	0.F0.B171
BUFIO2[6]:FB_DIVIDE_BYPASS	0.F0.B34	0.F0.B29	0.F0.B28	0.F0.B27
BUFIO2[7]:FB_DIVIDE_BYPASS	0.F0.B82	0.F0.B77	0.F0.B76	0.F0.B75
inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2[0]:FB_I	0.F0.B296	0.F0.B295	0.F0.B294
BUFIO2[1]:FB_I	0.F0.B344	0.F0.B343	0.F0.B342
BUFIO2[2]:FB_I	0.F0.B200	0.F0.B199	0.F0.B198
BUFIO2[3]:FB_I	0.F0.B248	0.F0.B247	0.F0.B246
BUFIO2[4]:FB_I	0.F0.B104	0.F0.B103	0.F0.B102
BUFIO2[5]:FB_I	0.F0.B152	0.F0.B151	0.F0.B150
BUFIO2[6]:FB_I	0.F0.B8	0.F0.B7	0.F0.B6
BUFIO2[7]:FB_I	0.F0.B56	0.F0.B55	0.F0.B54
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2[0]:I	0.F0.B290	0.F0.B289	0.F0.B288
BUFIO2[1]:I	0.F0.B338	0.F0.B337	0.F0.B336
BUFIO2[2]:I	0.F0.B194	0.F0.B193	0.F0.B192
BUFIO2[3]:I	0.F0.B242	0.F0.B241	0.F0.B240
BUFIO2[4]:I	0.F0.B98	0.F0.B97	0.F0.B96
BUFIO2[5]:I	0.F0.B146	0.F0.B145	0.F0.B144
BUFIO2[6]:I	0.F0.B2	0.F0.B1	0.F0.B0
BUFIO2[7]:I	0.F0.B50	0.F0.B49	0.F0.B48
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2[0]:IB	0.F0.B293	0.F0.B292	0.F0.B291
BUFIO2[1]:IB	0.F0.B341	0.F0.B340	0.F0.B339
BUFIO2[2]:IB	0.F0.B197	0.F0.B196	0.F0.B195
BUFIO2[3]:IB	0.F0.B245	0.F0.B244	0.F0.B243
BUFIO2[4]:IB	0.F0.B101	0.F0.B100	0.F0.B99
BUFIO2[5]:IB	0.F0.B149	0.F0.B148	0.F0.B147
BUFIO2[6]:IB	0.F0.B5	0.F0.B4	0.F0.B3
BUFIO2[7]:IB	0.F0.B53	0.F0.B52	0.F0.B51
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2[0]:NEG_EDGE	0.F0.B301	0.F0.B300
BUFIO2[1]:NEG_EDGE	0.F0.B349	0.F0.B348
BUFIO2[2]:NEG_EDGE	0.F0.B205	0.F0.B204
BUFIO2[3]:NEG_EDGE	0.F0.B253	0.F0.B252
BUFIO2[4]:NEG_EDGE	0.F0.B109	0.F0.B108
BUFIO2[5]:NEG_EDGE	0.F0.B157	0.F0.B156
BUFIO2[6]:NEG_EDGE	0.F0.B13	0.F0.B12
BUFIO2[7]:NEG_EDGE	0.F0.B61	0.F0.B60
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2[0]:POS_EDGE	0.F0.B299	0.F0.B298	0.F0.B297
BUFIO2[1]:POS_EDGE	0.F0.B347	0.F0.B346	0.F0.B345
BUFIO2[2]:POS_EDGE	0.F0.B203	0.F0.B202	0.F0.B201
BUFIO2[3]:POS_EDGE	0.F0.B251	0.F0.B250	0.F0.B249
BUFIO2[4]:POS_EDGE	0.F0.B107	0.F0.B106	0.F0.B105
BUFIO2[5]:POS_EDGE	0.F0.B155	0.F0.B154	0.F0.B153
BUFIO2[6]:POS_EDGE	0.F0.B11	0.F0.B10	0.F0.B9
BUFIO2[7]:POS_EDGE	0.F0.B59	0.F0.B58	0.F0.B57
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFPLL[0]:DATA_RATE	0.F0.B141
BUFPLL[1]:DATA_RATE	0.F0.B186
SDR	0
DDR	1

BUFPLL[0]:DIVIDE	0.F0.B190	0.F0.B189	0.F0.B187	0.F0.B138	0.F0.B137	0.F0.B136
BUFPLL[1]:DIVIDE	0.F0.B233	0.F0.B232	0.F0.B191	0.F0.B183	0.F0.B143	0.F0.B142
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL[0]:ENABLE_BOTH_SYNC	0.F0.B286	0.F0.B280	0.F0.B234
BUFPLL[1]:ENABLE_BOTH_SYNC	0.F0.B329	0.F0.B282	0.F0.B237
non-inverted	[2]	[1]	[0]

BUFPLL[0]:ENABLE_NONE_SYNC	0.F0.B285	0.F0.B279
BUFPLL[1]:ENABLE_NONE_SYNC	0.F0.B328	0.F0.B281
non-inverted	[1]	[0]

BUFPLL[0]:LOCKED	0.F0.B376	0.F0.B375
BUFPLL[1]:LOCKED	0.F0.B378	0.F0.B377
LOCKED0	0	0
LOCKED1	0	1
LOCKED2	1	0

BUFPLL[0]:PLLIN	0.F0.B332	0.F0.B331	0.F0.B330
BUFPLL[1]:PLLIN	0.F0.B335	0.F0.B334	0.F0.B333
PLLIN0	0	0	0
PLLIN1	0	0	1
PLLIN2	0	1	0
PLLIN3	0	1	1
PLLIN4	1	0	0
PLLIN5	1	0	1

BUFPLL_MCB:LOCK_SRC	0.F0.B139	0.F0.B184
LOCK_TO_0	0	1
LOCK_TO_1	1	0

REG_INT:MUX.IMUX_CLK_GCLK[0]	0.F0.B90	0.F0.B91	0.F0.B92	0.F0.B93	0.F0.B47	0.F0.B87	0.F0.B88	0.F0.B89
REG_INT:MUX.IMUX_CLK_GCLK[1]	0.F0.B42	0.F0.B41	0.F0.B40	0.F0.B39	0.F0.B46	0.F0.B45	0.F0.B44	0.F0.B43
NONE	0	0	0	0	0	0	0	0
GCLK[0]	0	1	0	1	0	0	0	1
GCLK[1]	0	1	0	1	0	0	1	0
GCLK[2]	0	1	0	1	0	1	0	0
GCLK[3]	0	1	0	1	1	0	0	0
GCLK[8]	0	1	1	0	0	0	0	1
GCLK[9]	0	1	1	0	0	0	1	0
GCLK[10]	0	1	1	0	0	1	0	0
GCLK[11]	0	1	1	0	1	0	0	0
GCLK[4]	1	0	0	1	0	0	0	1
GCLK[5]	1	0	0	1	0	0	1	0
GCLK[6]	1	0	0	1	0	1	0	0
GCLK[7]	1	0	0	1	1	0	0	0
GCLK[12]	1	0	1	0	0	0	0	1
GCLK[13]	1	0	1	0	0	0	1	0
GCLK[14]	1	0	1	0	0	1	0	0
GCLK[15]	1	0	1	0	1	0	0	0

Tile CLK_W

Cells: 2

Bel BUFIO2[0]

spartan6 CLK_W bel BUFIO2[0]
Pin	Direction	Wires

Bel BUFIO2[1]

spartan6 CLK_W bel BUFIO2[1]
Pin	Direction	Wires

Bel BUFIO2[2]

spartan6 CLK_W bel BUFIO2[2]
Pin	Direction	Wires

Bel BUFIO2[3]

spartan6 CLK_W bel BUFIO2[3]
Pin	Direction	Wires

Bel BUFIO2[4]

spartan6 CLK_W bel BUFIO2[4]
Pin	Direction	Wires

Bel BUFIO2[5]

spartan6 CLK_W bel BUFIO2[5]
Pin	Direction	Wires

Bel BUFIO2[6]

spartan6 CLK_W bel BUFIO2[6]
Pin	Direction	Wires

Bel BUFIO2[7]

spartan6 CLK_W bel BUFIO2[7]
Pin	Direction	Wires

Bel BUFIO2FB[0]

spartan6 CLK_W bel BUFIO2FB[0]
Pin	Direction	Wires

Bel BUFIO2FB[1]

spartan6 CLK_W bel BUFIO2FB[1]
Pin	Direction	Wires

Bel BUFIO2FB[2]

spartan6 CLK_W bel BUFIO2FB[2]
Pin	Direction	Wires

Bel BUFIO2FB[3]

spartan6 CLK_W bel BUFIO2FB[3]
Pin	Direction	Wires

Bel BUFIO2FB[4]

spartan6 CLK_W bel BUFIO2FB[4]
Pin	Direction	Wires

Bel BUFIO2FB[5]

spartan6 CLK_W bel BUFIO2FB[5]
Pin	Direction	Wires

Bel BUFIO2FB[6]

spartan6 CLK_W bel BUFIO2FB[6]
Pin	Direction	Wires

Bel BUFIO2FB[7]

spartan6 CLK_W bel BUFIO2FB[7]
Pin	Direction	Wires

Bel BUFPLL[0]

spartan6 CLK_W bel BUFPLL[0]
Pin	Direction	Wires

Bel BUFPLL[1]

spartan6 CLK_W bel BUFPLL[1]
Pin	Direction	Wires

Bel BUFPLL_MCB

spartan6 CLK_W bel BUFPLL_MCB
Pin	Direction	Wires

Bel BUFPLL_OUT

spartan6 CLK_W bel BUFPLL_OUT
Pin	Direction	Wires
LOCK0	output	CELL[0].OUT[0]
LOCK1	output	CELL[0].OUT[1]

Bel BUFPLL_INS_WE

spartan6 CLK_W bel BUFPLL_INS_WE
Pin	Direction	Wires
GCLK0	input	CELL[0].IMUX_CLK[0]
GCLK1	input	CELL[0].IMUX_CLK[1]
PLLIN0_GCLK	input	CELL[1].IMUX_CLK[0]
PLLIN1_GCLK	input	CELL[1].IMUX_CLK[1]

Bel BUFIO2_INS

spartan6 CLK_W bel BUFIO2_INS
Pin	Direction	Wires

Bel BUFIO2_CKPIN

spartan6 CLK_W bel BUFIO2_CKPIN
Pin	Direction	Wires

Bel BUFPLL_BUF

spartan6 CLK_W bel BUFPLL_BUF
Pin	Direction	Wires

Bel TIEOFF_REG

spartan6 CLK_W bel TIEOFF_REG
Pin	Direction	Wires

Bel wires

spartan6 CLK_W bel wires
Wire	Pins
CELL[0].IMUX_CLK[0]	BUFPLL_INS_WE.GCLK0
CELL[0].IMUX_CLK[1]	BUFPLL_INS_WE.GCLK1
CELL[0].OUT[0]	BUFPLL_OUT.LOCK0
CELL[0].OUT[1]	BUFPLL_OUT.LOCK1
CELL[1].IMUX_CLK[0]	BUFPLL_INS_WE.PLLIN0_GCLK
CELL[1].IMUX_CLK[1]	BUFPLL_INS_WE.PLLIN1_GCLK

Bitstream

spartan6 CLK_W rect MAIN
Bit	Frame
Bit	F0
B0	-
B1	-
B2	-
B3	-
B4	-
B5	-
B6	-
B7	-
B8	-
B9	-
B10	-
B11	-
B12	-
B13	-
B14	-
B15	-
B16	-
B17	-
B18	-
B19	-
B20	-
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	-
B28	-
B29	-
B30	-
B31	-
B32	-
B33	-
B34	-
B35	-
B36	-
B37	-
B38	-
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	-
B49	-
B50	-
B51	-
B52	-
B53	-
B54	-
B55	-
B56	-
B57	-
B58	-
B59	-
B60	-
B61	-
B62	-
B63	-
B64	-
B65	-
B66	-
B67	-
B68	-
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	-
B76	-
B77	-
B78	-
B79	-
B80	-
B81	-
B82	-
B83	-
B84	-
B85	-
B86	-
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	-
B97	-
B98	-
B99	-
B100	-
B101	-
B102	-
B103	-
B104	-
B105	-
B106	-
B107	-
B108	-
B109	-
B110	-
B111	-
B112	-
B113	-
B114	-
B115	-
B116	-
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	-
B124	-
B125	-
B126	-
B127	-
B128	-
B129	-
B130	-
B131	-
B132	-
B133	-
B134	-
B135	-
B136	-
B137	-
B138	-
B139	-
B140	-
B141	-
B142	-
B143	-
B144	-
B145	-
B146	-
B147	-
B148	-
B149	-
B150	-
B151	-
B152	-
B153	-
B154	-
B155	-
B156	-
B157	-
B158	-
B159	-
B160	-
B161	-
B162	-
B163	-
B164	-
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	-
B172	-
B173	-
B174	-
B175	-
B176	-
B177	-
B178	-
B179	-
B180	-
B181	-
B182	-
B183	-
B184	-
B185	-
B186	-
B187	-
B188	-
B189	-
B190	-
B191	-
B192	-
B193	-
B194	-
B195	-
B196	-
B197	-
B198	-
B199	-
B200	-
B201	-
B202	-
B203	-
B204	-
B205	-
B206	-
B207	-
B208	-
B209	-
B210	-
B211	-
B212	-
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	-
B220	-
B221	-
B222	-
B223	-
B224	-
B225	-
B226	-
B227	-
B228	-
B229	-
B230	-
B231	-
B232	-
B233	-
B234	-
B235	-
B236	-
B237	-
B238	-
B239	-
B240	-
B241	-
B242	-
B243	-
B244	-
B245	-
B246	-
B247	-
B248	-
B249	-
B250	-
B251	-
B252	-
B253	-
B254	-
B255	-
B256	-
B257	-
B258	-
B259	-
B260	-
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	-
B268	-
B269	-
B270	-
B271	-
B272	-
B273	-
B274	-
B275	-
B276	-
B277	-
B278	-
B279	-
B280	-
B281	-
B282	-
B283	-
B284	-
B285	-
B286	-
B287	-
B288	-
B289	-
B290	-
B291	-
B292	-
B293	-
B294	-
B295	-
B296	-
B297	-
B298	-
B299	-
B300	-
B301	-
B302	-
B303	-
B304	-
B305	-
B306	-
B307	-
B308	-
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	-
B316	-
B317	-
B318	-
B319	-
B320	-
B321	-
B322	-
B323	-
B324	-
B325	-
B326	-
B327	-
B328	-
B329	-
B330	-
B331	-
B332	-
B333	-
B334	-
B335	-
B336	-
B337	-
B338	-
B339	-
B340	-
B341	-
B342	-
B343	-
B344	-
B345	-
B346	-
B347	-
B348	-
B349	-
B350	-
B351	-
B352	-
B353	-
B354	-
B355	-
B356	-
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	-
B364	-
B365	-
B366	-
B367	-
B368	-
B369	-
B370	-
B371	-
B372	-
B373	-
B374	-
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

### Bitstream

spartan6 CLK_W rect R0
Bit	Frame
Bit	F0
B374	BUFIO2[1]:CMT_ENABLE
B373	BUFIO2[1]:CKPIN[0]
B372	BUFIO2[1]:IOCLK_ENABLE
B371	BUFIO2[1]:CKPIN[1]
B370	~BUFIO2[1]:FB_DIVIDE_BYPASS[3]
B369	~BUFIO2[1]:DIVIDE_BYPASS
B368	-
B367	BUFIO2[1]:FB_ENABLE
B366	-
B365	~BUFIO2[1]:FB_DIVIDE_BYPASS[2]
B364	~BUFIO2[1]:FB_DIVIDE_BYPASS[1]
B363	~BUFIO2[1]:FB_DIVIDE_BYPASS[0]
B362	-
B361	-
B360	-
B359	-
B358	-
B357	-
B356	BUFIO2[1]:ENABLE_2CLK
B355	BUFIO2[1]:ENABLE
B354	BUFIO2[1]:R_EDGE
B353	BUFIO2[1]:DIVIDE[2]
B352	BUFIO2[1]:DIVIDE[1]
B351	BUFIO2[1]:DIVIDE[0]
B350	-
B349	BUFIO2[1]:NEG_EDGE[1]
B348	BUFIO2[1]:NEG_EDGE[0]
B347	BUFIO2[1]:POS_EDGE[2]
B346	BUFIO2[1]:POS_EDGE[1]
B345	BUFIO2[1]:POS_EDGE[0]
B344	BUFIO2[1]:FB_I[2]
B343	BUFIO2[1]:FB_I[1]
B342	BUFIO2[1]:FB_I[0]
B341	BUFIO2[1]:IB[2]
B340	BUFIO2[1]:IB[1]
B339	BUFIO2[1]:IB[0]
B338	BUFIO2[1]:I[2]
B337	BUFIO2[1]:I[1]
B336	BUFIO2[1]:I[0]
B335	-
B334	-
B333	-
B332	-
B331	-
B330	BUFPLL_COMMON:PLLIN[0]
B329	BUFPLL[1]:ENABLE_BOTH_SYNC[2]
B328	BUFPLL[1]:ENABLE_NONE_SYNC[1]
B327	-
B326	BUFIO2[0]:CMT_ENABLE
B325	BUFIO2[0]:CKPIN[0]
B324	BUFIO2[0]:IOCLK_ENABLE
B323	BUFIO2[0]:CKPIN[1]
B322	~BUFIO2[0]:FB_DIVIDE_BYPASS[3]
B321	~BUFIO2[0]:DIVIDE_BYPASS
B320	-
B319	BUFIO2[0]:FB_ENABLE
B318	-
B317	~BUFIO2[0]:FB_DIVIDE_BYPASS[2]
B316	~BUFIO2[0]:FB_DIVIDE_BYPASS[1]
B315	~BUFIO2[0]:FB_DIVIDE_BYPASS[0]
B314	-
B313	-
B312	-
B311	-
B310	-
B309	-
B308	BUFIO2[0]:ENABLE_2CLK
B307	BUFIO2[0]:ENABLE
B306	BUFIO2[0]:R_EDGE
B305	BUFIO2[0]:DIVIDE[2]
B304	BUFIO2[0]:DIVIDE[1]
B303	BUFIO2[0]:DIVIDE[0]
B302	-
B301	BUFIO2[0]:NEG_EDGE[1]
B300	BUFIO2[0]:NEG_EDGE[0]
B299	BUFIO2[0]:POS_EDGE[2]
B298	BUFIO2[0]:POS_EDGE[1]
B297	BUFIO2[0]:POS_EDGE[0]
B296	BUFIO2[0]:FB_I[2]
B295	BUFIO2[0]:FB_I[1]
B294	BUFIO2[0]:FB_I[0]
B293	BUFIO2[0]:IB[2]
B292	BUFIO2[0]:IB[1]
B291	BUFIO2[0]:IB[0]
B290	BUFIO2[0]:I[2]
B289	BUFIO2[0]:I[1]
B288	BUFIO2[0]:I[0]
B287	-
B286	BUFPLL[0]:ENABLE_BOTH_SYNC[2]
B285	BUFPLL[0]:ENABLE_NONE_SYNC[1]
B284	-
B283	-
B282	BUFPLL[1]:ENABLE_BOTH_SYNC[1]
B281	BUFPLL[1]:ENABLE_NONE_SYNC[0]
B280	BUFPLL[0]:ENABLE_BOTH_SYNC[1]
B279	BUFPLL[0]:ENABLE_NONE_SYNC[0]
B278	BUFIO2[3]:CMT_ENABLE
B277	BUFIO2[3]:CKPIN[0]
B276	BUFIO2[3]:IOCLK_ENABLE
B275	BUFIO2[3]:CKPIN[1]
B274	~BUFIO2[3]:FB_DIVIDE_BYPASS[3]
B273	~BUFIO2[3]:DIVIDE_BYPASS
B272	-
B271	BUFIO2[3]:FB_ENABLE
B270	-
B269	~BUFIO2[3]:FB_DIVIDE_BYPASS[2]
B268	~BUFIO2[3]:FB_DIVIDE_BYPASS[1]
B267	~BUFIO2[3]:FB_DIVIDE_BYPASS[0]
B266	-
B265	-
B264	-
B263	-
B262	-
B261	-
B260	BUFIO2[3]:ENABLE_2CLK
B259	BUFIO2[3]:ENABLE
B258	BUFIO2[3]:R_EDGE
B257	BUFIO2[3]:DIVIDE[2]
B256	BUFIO2[3]:DIVIDE[1]
B255	BUFIO2[3]:DIVIDE[0]
B254	-
B253	BUFIO2[3]:NEG_EDGE[1]
B252	BUFIO2[3]:NEG_EDGE[0]
B251	BUFIO2[3]:POS_EDGE[2]
B250	BUFIO2[3]:POS_EDGE[1]
B249	BUFIO2[3]:POS_EDGE[0]
B248	BUFIO2[3]:FB_I[2]
B247	BUFIO2[3]:FB_I[1]
B246	BUFIO2[3]:FB_I[0]
B245	BUFIO2[3]:IB[2]
B244	BUFIO2[3]:IB[1]
B243	BUFIO2[3]:IB[0]
B242	BUFIO2[3]:I[2]
B241	BUFIO2[3]:I[1]
B240	BUFIO2[3]:I[0]
B239	-
B238	-
B237	BUFPLL[1]:ENABLE_BOTH_SYNC[0]
B236	-
B235	-
B234	BUFPLL[0]:ENABLE_BOTH_SYNC[0]
B233	BUFPLL[1]:DIVIDE[5]
B232	BUFPLL[1]:DIVIDE[4]
B231	-
B230	BUFIO2[2]:CMT_ENABLE
B229	BUFIO2[2]:CKPIN[0]
B228	BUFIO2[2]:IOCLK_ENABLE
B227	BUFIO2[2]:CKPIN[1]
B226	~BUFIO2[2]:FB_DIVIDE_BYPASS[3]
B225	~BUFIO2[2]:DIVIDE_BYPASS
B224	-
B223	BUFIO2[2]:FB_ENABLE
B222	-
B221	~BUFIO2[2]:FB_DIVIDE_BYPASS[2]
B220	~BUFIO2[2]:FB_DIVIDE_BYPASS[1]
B219	~BUFIO2[2]:FB_DIVIDE_BYPASS[0]
B218	-
B217	-
B216	-
B215	-
B214	-
B213	-
B212	BUFIO2[2]:ENABLE_2CLK
B211	BUFIO2[2]:ENABLE
B210	BUFIO2[2]:R_EDGE
B209	BUFIO2[2]:DIVIDE[2]
B208	BUFIO2[2]:DIVIDE[1]
B207	BUFIO2[2]:DIVIDE[0]
B206	-
B205	BUFIO2[2]:NEG_EDGE[1]
B204	BUFIO2[2]:NEG_EDGE[0]
B203	BUFIO2[2]:POS_EDGE[2]
B202	BUFIO2[2]:POS_EDGE[1]
B201	BUFIO2[2]:POS_EDGE[0]
B200	BUFIO2[2]:FB_I[2]
B199	BUFIO2[2]:FB_I[1]
B198	BUFIO2[2]:FB_I[0]
B197	BUFIO2[2]:IB[2]
B196	BUFIO2[2]:IB[1]
B195	BUFIO2[2]:IB[0]
B194	BUFIO2[2]:I[2]
B193	BUFIO2[2]:I[1]
B192	BUFIO2[2]:I[0]
B191	BUFPLL[1]:DIVIDE[3]
B190	BUFPLL[0]:DIVIDE[5]
B189	BUFPLL[0]:DIVIDE[4]
B188	-
B187	BUFPLL[0]:DIVIDE[3]
B186	BUFPLL[1]:DATA_RATE[0]
B185	~BUFPLL[1]:ENABLE_SYNC
B184	BUFPLL_MCB:LOCK_SRC[0]
B183	BUFPLL[1]:DIVIDE[2]
B182	BUFIO2[5]:CMT_ENABLE
B181	BUFIO2[5]:CKPIN[0]
B180	BUFIO2[5]:IOCLK_ENABLE
B179	BUFIO2[5]:CKPIN[1]
B178	~BUFIO2[5]:FB_DIVIDE_BYPASS[3]
B177	~BUFIO2[5]:DIVIDE_BYPASS
B176	-
B175	BUFIO2[5]:FB_ENABLE
B174	-
B173	~BUFIO2[5]:FB_DIVIDE_BYPASS[2]
B172	~BUFIO2[5]:FB_DIVIDE_BYPASS[1]
B171	~BUFIO2[5]:FB_DIVIDE_BYPASS[0]
B170	-
B169	-
B168	-
B167	-
B166	-
B165	-
B164	BUFIO2[5]:ENABLE_2CLK
B163	BUFIO2[5]:ENABLE
B162	BUFIO2[5]:R_EDGE
B161	BUFIO2[5]:DIVIDE[2]
B160	BUFIO2[5]:DIVIDE[1]
B159	BUFIO2[5]:DIVIDE[0]
B158	-
B157	BUFIO2[5]:NEG_EDGE[1]
B156	BUFIO2[5]:NEG_EDGE[0]
B155	BUFIO2[5]:POS_EDGE[2]
B154	BUFIO2[5]:POS_EDGE[1]
B153	BUFIO2[5]:POS_EDGE[0]
B152	BUFIO2[5]:FB_I[2]
B151	BUFIO2[5]:FB_I[1]
B150	BUFIO2[5]:FB_I[0]
B149	BUFIO2[5]:IB[2]
B148	BUFIO2[5]:IB[1]
B147	BUFIO2[5]:IB[0]
B146	BUFIO2[5]:I[2]
B145	BUFIO2[5]:I[1]
B144	BUFIO2[5]:I[0]
B143	BUFPLL[1]:DIVIDE[1]
B142	BUFPLL[1]:DIVIDE[0]
B141	BUFPLL[0]:DATA_RATE[0]
B140	~BUFPLL[0]:ENABLE_SYNC
B139	BUFPLL_MCB:LOCK_SRC[1]
B138	BUFPLL[0]:DIVIDE[2]
B137	BUFPLL[0]:DIVIDE[1]
B136	BUFPLL[0]:DIVIDE[0]
B135	BUFPLL_COMMON:ENABLE
B134	BUFIO2[4]:CMT_ENABLE
B133	BUFIO2[4]:CKPIN[0]
B132	BUFIO2[4]:IOCLK_ENABLE
B131	BUFIO2[4]:CKPIN[1]
B130	~BUFIO2[4]:FB_DIVIDE_BYPASS[3]
B129	~BUFIO2[4]:DIVIDE_BYPASS
B128	-
B127	BUFIO2[4]:FB_ENABLE
B126	-
B125	~BUFIO2[4]:FB_DIVIDE_BYPASS[2]
B124	~BUFIO2[4]:FB_DIVIDE_BYPASS[1]
B123	~BUFIO2[4]:FB_DIVIDE_BYPASS[0]
B122	-
B121	-
B120	-
B119	-
B118	-
B117	-
B116	BUFIO2[4]:ENABLE_2CLK
B115	BUFIO2[4]:ENABLE
B114	BUFIO2[4]:R_EDGE
B113	BUFIO2[4]:DIVIDE[2]
B112	BUFIO2[4]:DIVIDE[1]
B111	BUFIO2[4]:DIVIDE[0]
B110	-
B109	BUFIO2[4]:NEG_EDGE[1]
B108	BUFIO2[4]:NEG_EDGE[0]
B107	BUFIO2[4]:POS_EDGE[2]
B106	BUFIO2[4]:POS_EDGE[1]
B105	BUFIO2[4]:POS_EDGE[0]
B104	BUFIO2[4]:FB_I[2]
B103	BUFIO2[4]:FB_I[1]
B102	BUFIO2[4]:FB_I[0]
B101	BUFIO2[4]:IB[2]
B100	BUFIO2[4]:IB[1]
B99	BUFIO2[4]:IB[0]
B98	BUFIO2[4]:I[2]
B97	BUFIO2[4]:I[1]
B96	BUFIO2[4]:I[0]
B95	-
B94	-
B93	-
B92	-
B91	-
B90	-
B89	-
B88	-
B87	-
B86	BUFIO2[7]:CMT_ENABLE
B85	BUFIO2[7]:CKPIN[0]
B84	BUFIO2[7]:IOCLK_ENABLE
B83	BUFIO2[7]:CKPIN[1]
B82	~BUFIO2[7]:FB_DIVIDE_BYPASS[3]
B81	~BUFIO2[7]:DIVIDE_BYPASS
B80	-
B79	BUFIO2[7]:FB_ENABLE
B78	-
B77	~BUFIO2[7]:FB_DIVIDE_BYPASS[2]
B76	~BUFIO2[7]:FB_DIVIDE_BYPASS[1]
B75	~BUFIO2[7]:FB_DIVIDE_BYPASS[0]
B74	-
B73	-
B72	-
B71	-
B70	-
B69	-
B68	BUFIO2[7]:ENABLE_2CLK
B67	BUFIO2[7]:ENABLE
B66	BUFIO2[7]:R_EDGE
B65	BUFIO2[7]:DIVIDE[2]
B64	BUFIO2[7]:DIVIDE[1]
B63	BUFIO2[7]:DIVIDE[0]
B62	-
B61	BUFIO2[7]:NEG_EDGE[1]
B60	BUFIO2[7]:NEG_EDGE[0]
B59	BUFIO2[7]:POS_EDGE[2]
B58	BUFIO2[7]:POS_EDGE[1]
B57	BUFIO2[7]:POS_EDGE[0]
B56	BUFIO2[7]:FB_I[2]
B55	BUFIO2[7]:FB_I[1]
B54	BUFIO2[7]:FB_I[0]
B53	BUFIO2[7]:IB[2]
B52	BUFIO2[7]:IB[1]
B51	BUFIO2[7]:IB[0]
B50	BUFIO2[7]:I[2]
B49	BUFIO2[7]:I[1]
B48	BUFIO2[7]:I[0]
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	BUFIO2[6]:CMT_ENABLE
B37	BUFIO2[6]:CKPIN[0]
B36	BUFIO2[6]:IOCLK_ENABLE
B35	BUFIO2[6]:CKPIN[1]
B34	~BUFIO2[6]:FB_DIVIDE_BYPASS[3]
B33	~BUFIO2[6]:DIVIDE_BYPASS
B32	-
B31	BUFIO2[6]:FB_ENABLE
B30	-
B29	~BUFIO2[6]:FB_DIVIDE_BYPASS[2]
B28	~BUFIO2[6]:FB_DIVIDE_BYPASS[1]
B27	~BUFIO2[6]:FB_DIVIDE_BYPASS[0]
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	BUFIO2[6]:ENABLE_2CLK
B19	BUFIO2[6]:ENABLE
B18	BUFIO2[6]:R_EDGE
B17	BUFIO2[6]:DIVIDE[2]
B16	BUFIO2[6]:DIVIDE[1]
B15	BUFIO2[6]:DIVIDE[0]
B14	-
B13	BUFIO2[6]:NEG_EDGE[1]
B12	BUFIO2[6]:NEG_EDGE[0]
B11	BUFIO2[6]:POS_EDGE[2]
B10	BUFIO2[6]:POS_EDGE[1]
B9	BUFIO2[6]:POS_EDGE[0]
B8	BUFIO2[6]:FB_I[2]
B7	BUFIO2[6]:FB_I[1]
B6	BUFIO2[6]:FB_I[0]
B5	BUFIO2[6]:IB[2]
B4	BUFIO2[6]:IB[1]
B3	BUFIO2[6]:IB[0]
B2	BUFIO2[6]:I[2]
B1	BUFIO2[6]:I[1]
B0	BUFIO2[6]:I[0]

BUFIO2[0]:CKPIN	0.F0.B323	0.F0.B325
BUFIO2[1]:CKPIN	0.F0.B371	0.F0.B373
BUFIO2[2]:CKPIN	0.F0.B227	0.F0.B229
BUFIO2[3]:CKPIN	0.F0.B275	0.F0.B277
BUFIO2[4]:CKPIN	0.F0.B131	0.F0.B133
BUFIO2[5]:CKPIN	0.F0.B179	0.F0.B181
BUFIO2[6]:CKPIN	0.F0.B35	0.F0.B37
BUFIO2[7]:CKPIN	0.F0.B83	0.F0.B85
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFIO2[0]:CMT_ENABLE	0.F0.B326
BUFIO2[0]:ENABLE	0.F0.B307
BUFIO2[0]:ENABLE_2CLK	0.F0.B308
BUFIO2[0]:FB_ENABLE	0.F0.B319
BUFIO2[0]:IOCLK_ENABLE	0.F0.B324
BUFIO2[0]:R_EDGE	0.F0.B306
BUFIO2[1]:CMT_ENABLE	0.F0.B374
BUFIO2[1]:ENABLE	0.F0.B355
BUFIO2[1]:ENABLE_2CLK	0.F0.B356
BUFIO2[1]:FB_ENABLE	0.F0.B367
BUFIO2[1]:IOCLK_ENABLE	0.F0.B372
BUFIO2[1]:R_EDGE	0.F0.B354
BUFIO2[2]:CMT_ENABLE	0.F0.B230
BUFIO2[2]:ENABLE	0.F0.B211
BUFIO2[2]:ENABLE_2CLK	0.F0.B212
BUFIO2[2]:FB_ENABLE	0.F0.B223
BUFIO2[2]:IOCLK_ENABLE	0.F0.B228
BUFIO2[2]:R_EDGE	0.F0.B210
BUFIO2[3]:CMT_ENABLE	0.F0.B278
BUFIO2[3]:ENABLE	0.F0.B259
BUFIO2[3]:ENABLE_2CLK	0.F0.B260
BUFIO2[3]:FB_ENABLE	0.F0.B271
BUFIO2[3]:IOCLK_ENABLE	0.F0.B276
BUFIO2[3]:R_EDGE	0.F0.B258
BUFIO2[4]:CMT_ENABLE	0.F0.B134
BUFIO2[4]:ENABLE	0.F0.B115
BUFIO2[4]:ENABLE_2CLK	0.F0.B116
BUFIO2[4]:FB_ENABLE	0.F0.B127
BUFIO2[4]:IOCLK_ENABLE	0.F0.B132
BUFIO2[4]:R_EDGE	0.F0.B114
BUFIO2[5]:CMT_ENABLE	0.F0.B182
BUFIO2[5]:ENABLE	0.F0.B163
BUFIO2[5]:ENABLE_2CLK	0.F0.B164
BUFIO2[5]:FB_ENABLE	0.F0.B175
BUFIO2[5]:IOCLK_ENABLE	0.F0.B180
BUFIO2[5]:R_EDGE	0.F0.B162
BUFIO2[6]:CMT_ENABLE	0.F0.B38
BUFIO2[6]:ENABLE	0.F0.B19
BUFIO2[6]:ENABLE_2CLK	0.F0.B20
BUFIO2[6]:FB_ENABLE	0.F0.B31
BUFIO2[6]:IOCLK_ENABLE	0.F0.B36
BUFIO2[6]:R_EDGE	0.F0.B18
BUFIO2[7]:CMT_ENABLE	0.F0.B86
BUFIO2[7]:ENABLE	0.F0.B67
BUFIO2[7]:ENABLE_2CLK	0.F0.B68
BUFIO2[7]:FB_ENABLE	0.F0.B79
BUFIO2[7]:IOCLK_ENABLE	0.F0.B84
BUFIO2[7]:R_EDGE	0.F0.B66
BUFPLL_COMMON:ENABLE	0.F0.B135
non-inverted	[0]

BUFIO2[0]:DIVIDE	0.F0.B305	0.F0.B304	0.F0.B303
BUFIO2[1]:DIVIDE	0.F0.B353	0.F0.B352	0.F0.B351
BUFIO2[2]:DIVIDE	0.F0.B209	0.F0.B208	0.F0.B207
BUFIO2[3]:DIVIDE	0.F0.B257	0.F0.B256	0.F0.B255
BUFIO2[4]:DIVIDE	0.F0.B113	0.F0.B112	0.F0.B111
BUFIO2[5]:DIVIDE	0.F0.B161	0.F0.B160	0.F0.B159
BUFIO2[6]:DIVIDE	0.F0.B17	0.F0.B16	0.F0.B15
BUFIO2[7]:DIVIDE	0.F0.B65	0.F0.B64	0.F0.B63
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2[0]:DIVIDE_BYPASS	0.F0.B321
BUFIO2[1]:DIVIDE_BYPASS	0.F0.B369
BUFIO2[2]:DIVIDE_BYPASS	0.F0.B225
BUFIO2[3]:DIVIDE_BYPASS	0.F0.B273
BUFIO2[4]:DIVIDE_BYPASS	0.F0.B129
BUFIO2[5]:DIVIDE_BYPASS	0.F0.B177
BUFIO2[6]:DIVIDE_BYPASS	0.F0.B33
BUFIO2[7]:DIVIDE_BYPASS	0.F0.B81
BUFPLL[0]:ENABLE_SYNC	0.F0.B140
BUFPLL[1]:ENABLE_SYNC	0.F0.B185
inverted	~[0]

BUFIO2[0]:FB_DIVIDE_BYPASS	0.F0.B322	0.F0.B317	0.F0.B316	0.F0.B315
BUFIO2[1]:FB_DIVIDE_BYPASS	0.F0.B370	0.F0.B365	0.F0.B364	0.F0.B363
BUFIO2[2]:FB_DIVIDE_BYPASS	0.F0.B226	0.F0.B221	0.F0.B220	0.F0.B219
BUFIO2[3]:FB_DIVIDE_BYPASS	0.F0.B274	0.F0.B269	0.F0.B268	0.F0.B267
BUFIO2[4]:FB_DIVIDE_BYPASS	0.F0.B130	0.F0.B125	0.F0.B124	0.F0.B123
BUFIO2[5]:FB_DIVIDE_BYPASS	0.F0.B178	0.F0.B173	0.F0.B172	0.F0.B171
BUFIO2[6]:FB_DIVIDE_BYPASS	0.F0.B34	0.F0.B29	0.F0.B28	0.F0.B27
BUFIO2[7]:FB_DIVIDE_BYPASS	0.F0.B82	0.F0.B77	0.F0.B76	0.F0.B75
inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2[0]:FB_I	0.F0.B296	0.F0.B295	0.F0.B294
BUFIO2[1]:FB_I	0.F0.B344	0.F0.B343	0.F0.B342
BUFIO2[2]:FB_I	0.F0.B200	0.F0.B199	0.F0.B198
BUFIO2[3]:FB_I	0.F0.B248	0.F0.B247	0.F0.B246
BUFIO2[4]:FB_I	0.F0.B104	0.F0.B103	0.F0.B102
BUFIO2[5]:FB_I	0.F0.B152	0.F0.B151	0.F0.B150
BUFIO2[6]:FB_I	0.F0.B8	0.F0.B7	0.F0.B6
BUFIO2[7]:FB_I	0.F0.B56	0.F0.B55	0.F0.B54
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2[0]:I	0.F0.B290	0.F0.B289	0.F0.B288
BUFIO2[2]:I	0.F0.B194	0.F0.B193	0.F0.B192
BUFIO2[4]:I	0.F0.B98	0.F0.B97	0.F0.B96
BUFIO2[5]:I	0.F0.B146	0.F0.B145	0.F0.B144
BUFIO2[6]:I	0.F0.B2	0.F0.B1	0.F0.B0
BUFIO2[7]:I	0.F0.B50	0.F0.B49	0.F0.B48
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2[0]:IB	0.F0.B293	0.F0.B292	0.F0.B291
BUFIO2[1]:IB	0.F0.B341	0.F0.B340	0.F0.B339
BUFIO2[2]:IB	0.F0.B197	0.F0.B196	0.F0.B195
BUFIO2[3]:IB	0.F0.B245	0.F0.B244	0.F0.B243
BUFIO2[4]:IB	0.F0.B101	0.F0.B100	0.F0.B99
BUFIO2[5]:IB	0.F0.B149	0.F0.B148	0.F0.B147
BUFIO2[6]:IB	0.F0.B5	0.F0.B4	0.F0.B3
BUFIO2[7]:IB	0.F0.B53	0.F0.B52	0.F0.B51
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2[0]:NEG_EDGE	0.F0.B301	0.F0.B300
BUFIO2[1]:NEG_EDGE	0.F0.B349	0.F0.B348
BUFIO2[2]:NEG_EDGE	0.F0.B205	0.F0.B204
BUFIO2[3]:NEG_EDGE	0.F0.B253	0.F0.B252
BUFIO2[4]:NEG_EDGE	0.F0.B109	0.F0.B108
BUFIO2[5]:NEG_EDGE	0.F0.B157	0.F0.B156
BUFIO2[6]:NEG_EDGE	0.F0.B13	0.F0.B12
BUFIO2[7]:NEG_EDGE	0.F0.B61	0.F0.B60
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2[0]:POS_EDGE	0.F0.B299	0.F0.B298	0.F0.B297
BUFIO2[1]:POS_EDGE	0.F0.B347	0.F0.B346	0.F0.B345
BUFIO2[2]:POS_EDGE	0.F0.B203	0.F0.B202	0.F0.B201
BUFIO2[3]:POS_EDGE	0.F0.B251	0.F0.B250	0.F0.B249
BUFIO2[4]:POS_EDGE	0.F0.B107	0.F0.B106	0.F0.B105
BUFIO2[5]:POS_EDGE	0.F0.B155	0.F0.B154	0.F0.B153
BUFIO2[6]:POS_EDGE	0.F0.B11	0.F0.B10	0.F0.B9
BUFIO2[7]:POS_EDGE	0.F0.B59	0.F0.B58	0.F0.B57
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2[1]:I	0.F0.B338	0.F0.B337	0.F0.B336
BUFIO2[3]:I	0.F0.B242	0.F0.B241	0.F0.B240
CLKPIN0	0	0	0
GTPCLK	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFPLL[0]:DATA_RATE	0.F0.B141
BUFPLL[1]:DATA_RATE	0.F0.B186
SDR	0
DDR	1

BUFPLL[0]:DIVIDE	0.F0.B190	0.F0.B189	0.F0.B187	0.F0.B138	0.F0.B137	0.F0.B136
BUFPLL[1]:DIVIDE	0.F0.B233	0.F0.B232	0.F0.B191	0.F0.B183	0.F0.B143	0.F0.B142
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL[0]:ENABLE_BOTH_SYNC	0.F0.B286	0.F0.B280	0.F0.B234
BUFPLL[1]:ENABLE_BOTH_SYNC	0.F0.B329	0.F0.B282	0.F0.B237
non-inverted	[2]	[1]	[0]

BUFPLL[0]:ENABLE_NONE_SYNC	0.F0.B285	0.F0.B279
BUFPLL[1]:ENABLE_NONE_SYNC	0.F0.B328	0.F0.B281
non-inverted	[1]	[0]

BUFPLL_COMMON:PLLIN	0.F0.B330
CMT	0
GCLK	1

BUFPLL_MCB:LOCK_SRC	0.F0.B139	0.F0.B184
LOCK_TO_0	0	1
LOCK_TO_1	1	0

Tile CLK_E

Cells: 2

Bel BUFIO2[0]

spartan6 CLK_E bel BUFIO2[0]
Pin	Direction	Wires

Bel BUFIO2[1]

spartan6 CLK_E bel BUFIO2[1]
Pin	Direction	Wires

Bel BUFIO2[2]

spartan6 CLK_E bel BUFIO2[2]
Pin	Direction	Wires

Bel BUFIO2[3]

spartan6 CLK_E bel BUFIO2[3]
Pin	Direction	Wires

Bel BUFIO2[4]

spartan6 CLK_E bel BUFIO2[4]
Pin	Direction	Wires

Bel BUFIO2[5]

spartan6 CLK_E bel BUFIO2[5]
Pin	Direction	Wires

Bel BUFIO2[6]

spartan6 CLK_E bel BUFIO2[6]
Pin	Direction	Wires

Bel BUFIO2[7]

spartan6 CLK_E bel BUFIO2[7]
Pin	Direction	Wires

Bel BUFIO2FB[0]

spartan6 CLK_E bel BUFIO2FB[0]
Pin	Direction	Wires

Bel BUFIO2FB[1]

spartan6 CLK_E bel BUFIO2FB[1]
Pin	Direction	Wires

Bel BUFIO2FB[2]

spartan6 CLK_E bel BUFIO2FB[2]
Pin	Direction	Wires

Bel BUFIO2FB[3]

spartan6 CLK_E bel BUFIO2FB[3]
Pin	Direction	Wires

Bel BUFIO2FB[4]

spartan6 CLK_E bel BUFIO2FB[4]
Pin	Direction	Wires

Bel BUFIO2FB[5]

spartan6 CLK_E bel BUFIO2FB[5]
Pin	Direction	Wires

Bel BUFIO2FB[6]

spartan6 CLK_E bel BUFIO2FB[6]
Pin	Direction	Wires

Bel BUFIO2FB[7]

spartan6 CLK_E bel BUFIO2FB[7]
Pin	Direction	Wires

Bel BUFPLL[0]

spartan6 CLK_E bel BUFPLL[0]
Pin	Direction	Wires

Bel BUFPLL[1]

spartan6 CLK_E bel BUFPLL[1]
Pin	Direction	Wires

Bel BUFPLL_MCB

spartan6 CLK_E bel BUFPLL_MCB
Pin	Direction	Wires

Bel BUFPLL_OUT

spartan6 CLK_E bel BUFPLL_OUT
Pin	Direction	Wires
LOCK0	output	CELL[0].OUT[0]
LOCK1	output	CELL[0].OUT[1]

Bel BUFPLL_INS_WE

spartan6 CLK_E bel BUFPLL_INS_WE
Pin	Direction	Wires
GCLK0	input	CELL[0].IMUX_CLK[0]
GCLK1	input	CELL[0].IMUX_CLK[1]
PLLIN0_GCLK	input	CELL[1].IMUX_CLK[0]
PLLIN1_GCLK	input	CELL[1].IMUX_CLK[1]

Bel BUFIO2_INS

spartan6 CLK_E bel BUFIO2_INS
Pin	Direction	Wires

Bel BUFIO2_CKPIN

spartan6 CLK_E bel BUFIO2_CKPIN
Pin	Direction	Wires

Bel BUFPLL_BUF

spartan6 CLK_E bel BUFPLL_BUF
Pin	Direction	Wires

Bel TIEOFF_REG

spartan6 CLK_E bel TIEOFF_REG
Pin	Direction	Wires

Bel wires

spartan6 CLK_E bel wires
Wire	Pins
CELL[0].IMUX_CLK[0]	BUFPLL_INS_WE.GCLK0
CELL[0].IMUX_CLK[1]	BUFPLL_INS_WE.GCLK1
CELL[0].OUT[0]	BUFPLL_OUT.LOCK0
CELL[0].OUT[1]	BUFPLL_OUT.LOCK1
CELL[1].IMUX_CLK[0]	BUFPLL_INS_WE.PLLIN0_GCLK
CELL[1].IMUX_CLK[1]	BUFPLL_INS_WE.PLLIN1_GCLK

Bitstream

spartan6 CLK_E rect MAIN
Bit	Frame
Bit	F0
B0	-
B1	-
B2	-
B3	-
B4	-
B5	-
B6	-
B7	-
B8	-
B9	-
B10	-
B11	-
B12	-
B13	-
B14	-
B15	-
B16	-
B17	-
B18	-
B19	-
B20	-
B21	-
B22	-
B23	-
B24	-
B25	-
B26	-
B27	-
B28	-
B29	-
B30	-
B31	-
B32	-
B33	-
B34	-
B35	-
B36	-
B37	-
B38	-
B39	-
B40	-
B41	-
B42	-
B43	-
B44	-
B45	-
B46	-
B47	-
B48	-
B49	-
B50	-
B51	-
B52	-
B53	-
B54	-
B55	-
B56	-
B57	-
B58	-
B59	-
B60	-
B61	-
B62	-
B63	-
B64	-
B65	-
B66	-
B67	-
B68	-
B69	-
B70	-
B71	-
B72	-
B73	-
B74	-
B75	-
B76	-
B77	-
B78	-
B79	-
B80	-
B81	-
B82	-
B83	-
B84	-
B85	-
B86	-
B87	-
B88	-
B89	-
B90	-
B91	-
B92	-
B93	-
B94	-
B95	-
B96	-
B97	-
B98	-
B99	-
B100	-
B101	-
B102	-
B103	-
B104	-
B105	-
B106	-
B107	-
B108	-
B109	-
B110	-
B111	-
B112	-
B113	-
B114	-
B115	-
B116	-
B117	-
B118	-
B119	-
B120	-
B121	-
B122	-
B123	-
B124	-
B125	-
B126	-
B127	-
B128	-
B129	-
B130	-
B131	-
B132	-
B133	-
B134	-
B135	-
B136	-
B137	-
B138	-
B139	-
B140	-
B141	-
B142	-
B143	-
B144	-
B145	-
B146	-
B147	-
B148	-
B149	-
B150	-
B151	-
B152	-
B153	-
B154	-
B155	-
B156	-
B157	-
B158	-
B159	-
B160	-
B161	-
B162	-
B163	-
B164	-
B165	-
B166	-
B167	-
B168	-
B169	-
B170	-
B171	-
B172	-
B173	-
B174	-
B175	-
B176	-
B177	-
B178	-
B179	-
B180	-
B181	-
B182	-
B183	-
B184	-
B185	-
B186	-
B187	-
B188	-
B189	-
B190	-
B191	-
B192	-
B193	-
B194	-
B195	-
B196	-
B197	-
B198	-
B199	-
B200	-
B201	-
B202	-
B203	-
B204	-
B205	-
B206	-
B207	-
B208	-
B209	-
B210	-
B211	-
B212	-
B213	-
B214	-
B215	-
B216	-
B217	-
B218	-
B219	-
B220	-
B221	-
B222	-
B223	-
B224	-
B225	-
B226	-
B227	-
B228	-
B229	-
B230	-
B231	-
B232	-
B233	-
B234	-
B235	-
B236	-
B237	-
B238	-
B239	-
B240	-
B241	-
B242	-
B243	-
B244	-
B245	-
B246	-
B247	-
B248	-
B249	-
B250	-
B251	-
B252	-
B253	-
B254	-
B255	-
B256	-
B257	-
B258	-
B259	-
B260	-
B261	-
B262	-
B263	-
B264	-
B265	-
B266	-
B267	-
B268	-
B269	-
B270	-
B271	-
B272	-
B273	-
B274	-
B275	-
B276	-
B277	-
B278	-
B279	-
B280	-
B281	-
B282	-
B283	-
B284	-
B285	-
B286	-
B287	-
B288	-
B289	-
B290	-
B291	-
B292	-
B293	-
B294	-
B295	-
B296	-
B297	-
B298	-
B299	-
B300	-
B301	-
B302	-
B303	-
B304	-
B305	-
B306	-
B307	-
B308	-
B309	-
B310	-
B311	-
B312	-
B313	-
B314	-
B315	-
B316	-
B317	-
B318	-
B319	-
B320	-
B321	-
B322	-
B323	-
B324	-
B325	-
B326	-
B327	-
B328	-
B329	-
B330	-
B331	-
B332	-
B333	-
B334	-
B335	-
B336	-
B337	-
B338	-
B339	-
B340	-
B341	-
B342	-
B343	-
B344	-
B345	-
B346	-
B347	-
B348	-
B349	-
B350	-
B351	-
B352	-
B353	-
B354	-
B355	-
B356	-
B357	-
B358	-
B359	-
B360	-
B361	-
B362	-
B363	-
B364	-
B365	-
B366	-
B367	-
B368	-
B369	-
B370	-
B371	-
B372	-
B373	-
B374	-
B375	-
B376	-
B377	-
B378	-
B379	-
B380	-
B381	-
B382	-
B383	-

### Bitstream

spartan6 CLK_E rect R0
Bit	Frame
Bit	F0
B374	BUFIO2[1]:CMT_ENABLE
B373	BUFIO2[1]:CKPIN[0]
B372	BUFIO2[1]:IOCLK_ENABLE
B371	BUFIO2[1]:CKPIN[1]
B370	~BUFIO2[1]:FB_DIVIDE_BYPASS[3]
B369	~BUFIO2[1]:DIVIDE_BYPASS
B368	-
B367	BUFIO2[1]:FB_ENABLE
B366	-
B365	~BUFIO2[1]:FB_DIVIDE_BYPASS[2]
B364	~BUFIO2[1]:FB_DIVIDE_BYPASS[1]
B363	~BUFIO2[1]:FB_DIVIDE_BYPASS[0]
B362	-
B361	-
B360	-
B359	-
B358	-
B357	-
B356	BUFIO2[1]:ENABLE_2CLK
B355	BUFIO2[1]:ENABLE
B354	BUFIO2[1]:R_EDGE
B353	BUFIO2[1]:DIVIDE[2]
B352	BUFIO2[1]:DIVIDE[1]
B351	BUFIO2[1]:DIVIDE[0]
B350	-
B349	BUFIO2[1]:NEG_EDGE[1]
B348	BUFIO2[1]:NEG_EDGE[0]
B347	BUFIO2[1]:POS_EDGE[2]
B346	BUFIO2[1]:POS_EDGE[1]
B345	BUFIO2[1]:POS_EDGE[0]
B344	BUFIO2[1]:FB_I[2]
B343	BUFIO2[1]:FB_I[1]
B342	BUFIO2[1]:FB_I[0]
B341	BUFIO2[1]:IB[2]
B340	BUFIO2[1]:IB[1]
B339	BUFIO2[1]:IB[0]
B338	BUFIO2[1]:I[2]
B337	BUFIO2[1]:I[1]
B336	BUFIO2[1]:I[0]
B335	-
B334	-
B333	-
B332	-
B331	-
B330	BUFPLL_COMMON:PLLIN[0]
B329	BUFPLL[1]:ENABLE_BOTH_SYNC[2]
B328	BUFPLL[1]:ENABLE_NONE_SYNC[1]
B327	-
B326	BUFIO2[0]:CMT_ENABLE
B325	BUFIO2[0]:CKPIN[0]
B324	BUFIO2[0]:IOCLK_ENABLE
B323	BUFIO2[0]:CKPIN[1]
B322	~BUFIO2[0]:FB_DIVIDE_BYPASS[3]
B321	~BUFIO2[0]:DIVIDE_BYPASS
B320	-
B319	BUFIO2[0]:FB_ENABLE
B318	-
B317	~BUFIO2[0]:FB_DIVIDE_BYPASS[2]
B316	~BUFIO2[0]:FB_DIVIDE_BYPASS[1]
B315	~BUFIO2[0]:FB_DIVIDE_BYPASS[0]
B314	-
B313	-
B312	-
B311	-
B310	-
B309	-
B308	BUFIO2[0]:ENABLE_2CLK
B307	BUFIO2[0]:ENABLE
B306	BUFIO2[0]:R_EDGE
B305	BUFIO2[0]:DIVIDE[2]
B304	BUFIO2[0]:DIVIDE[1]
B303	BUFIO2[0]:DIVIDE[0]
B302	-
B301	BUFIO2[0]:NEG_EDGE[1]
B300	BUFIO2[0]:NEG_EDGE[0]
B299	BUFIO2[0]:POS_EDGE[2]
B298	BUFIO2[0]:POS_EDGE[1]
B297	BUFIO2[0]:POS_EDGE[0]
B296	BUFIO2[0]:FB_I[2]
B295	BUFIO2[0]:FB_I[1]
B294	BUFIO2[0]:FB_I[0]
B293	BUFIO2[0]:IB[2]
B292	BUFIO2[0]:IB[1]
B291	BUFIO2[0]:IB[0]
B290	BUFIO2[0]:I[2]
B289	BUFIO2[0]:I[1]
B288	BUFIO2[0]:I[0]
B287	-
B286	BUFPLL[0]:ENABLE_BOTH_SYNC[2]
B285	BUFPLL[0]:ENABLE_NONE_SYNC[1]
B284	-
B283	-
B282	BUFPLL[1]:ENABLE_BOTH_SYNC[1]
B281	BUFPLL[1]:ENABLE_NONE_SYNC[0]
B280	BUFPLL[0]:ENABLE_BOTH_SYNC[1]
B279	BUFPLL[0]:ENABLE_NONE_SYNC[0]
B278	BUFIO2[3]:CMT_ENABLE
B277	BUFIO2[3]:CKPIN[0]
B276	BUFIO2[3]:IOCLK_ENABLE
B275	BUFIO2[3]:CKPIN[1]
B274	~BUFIO2[3]:FB_DIVIDE_BYPASS[3]
B273	~BUFIO2[3]:DIVIDE_BYPASS
B272	-
B271	BUFIO2[3]:FB_ENABLE
B270	-
B269	~BUFIO2[3]:FB_DIVIDE_BYPASS[2]
B268	~BUFIO2[3]:FB_DIVIDE_BYPASS[1]
B267	~BUFIO2[3]:FB_DIVIDE_BYPASS[0]
B266	-
B265	-
B264	-
B263	-
B262	-
B261	-
B260	BUFIO2[3]:ENABLE_2CLK
B259	BUFIO2[3]:ENABLE
B258	BUFIO2[3]:R_EDGE
B257	BUFIO2[3]:DIVIDE[2]
B256	BUFIO2[3]:DIVIDE[1]
B255	BUFIO2[3]:DIVIDE[0]
B254	-
B253	BUFIO2[3]:NEG_EDGE[1]
B252	BUFIO2[3]:NEG_EDGE[0]
B251	BUFIO2[3]:POS_EDGE[2]
B250	BUFIO2[3]:POS_EDGE[1]
B249	BUFIO2[3]:POS_EDGE[0]
B248	BUFIO2[3]:FB_I[2]
B247	BUFIO2[3]:FB_I[1]
B246	BUFIO2[3]:FB_I[0]
B245	BUFIO2[3]:IB[2]
B244	BUFIO2[3]:IB[1]
B243	BUFIO2[3]:IB[0]
B242	BUFIO2[3]:I[2]
B241	BUFIO2[3]:I[1]
B240	BUFIO2[3]:I[0]
B239	-
B238	-
B237	BUFPLL[1]:ENABLE_BOTH_SYNC[0]
B236	-
B235	-
B234	BUFPLL[0]:ENABLE_BOTH_SYNC[0]
B233	BUFPLL[1]:DIVIDE[5]
B232	BUFPLL[1]:DIVIDE[4]
B231	-
B230	BUFIO2[2]:CMT_ENABLE
B229	BUFIO2[2]:CKPIN[0]
B228	BUFIO2[2]:IOCLK_ENABLE
B227	BUFIO2[2]:CKPIN[1]
B226	~BUFIO2[2]:FB_DIVIDE_BYPASS[3]
B225	~BUFIO2[2]:DIVIDE_BYPASS
B224	-
B223	BUFIO2[2]:FB_ENABLE
B222	-
B221	~BUFIO2[2]:FB_DIVIDE_BYPASS[2]
B220	~BUFIO2[2]:FB_DIVIDE_BYPASS[1]
B219	~BUFIO2[2]:FB_DIVIDE_BYPASS[0]
B218	-
B217	-
B216	-
B215	-
B214	-
B213	-
B212	BUFIO2[2]:ENABLE_2CLK
B211	BUFIO2[2]:ENABLE
B210	BUFIO2[2]:R_EDGE
B209	BUFIO2[2]:DIVIDE[2]
B208	BUFIO2[2]:DIVIDE[1]
B207	BUFIO2[2]:DIVIDE[0]
B206	-
B205	BUFIO2[2]:NEG_EDGE[1]
B204	BUFIO2[2]:NEG_EDGE[0]
B203	BUFIO2[2]:POS_EDGE[2]
B202	BUFIO2[2]:POS_EDGE[1]
B201	BUFIO2[2]:POS_EDGE[0]
B200	BUFIO2[2]:FB_I[2]
B199	BUFIO2[2]:FB_I[1]
B198	BUFIO2[2]:FB_I[0]
B197	BUFIO2[2]:IB[2]
B196	BUFIO2[2]:IB[1]
B195	BUFIO2[2]:IB[0]
B194	BUFIO2[2]:I[2]
B193	BUFIO2[2]:I[1]
B192	BUFIO2[2]:I[0]
B191	BUFPLL[1]:DIVIDE[3]
B190	BUFPLL[0]:DIVIDE[5]
B189	BUFPLL[0]:DIVIDE[4]
B188	-
B187	BUFPLL[0]:DIVIDE[3]
B186	BUFPLL[1]:DATA_RATE[0]
B185	~BUFPLL[1]:ENABLE_SYNC
B184	BUFPLL_MCB:LOCK_SRC[0]
B183	BUFPLL[1]:DIVIDE[2]
B182	BUFIO2[5]:CMT_ENABLE
B181	BUFIO2[5]:CKPIN[0]
B180	BUFIO2[5]:IOCLK_ENABLE
B179	BUFIO2[5]:CKPIN[1]
B178	~BUFIO2[5]:FB_DIVIDE_BYPASS[3]
B177	~BUFIO2[5]:DIVIDE_BYPASS
B176	-
B175	BUFIO2[5]:FB_ENABLE
B174	-
B173	~BUFIO2[5]:FB_DIVIDE_BYPASS[2]
B172	~BUFIO2[5]:FB_DIVIDE_BYPASS[1]
B171	~BUFIO2[5]:FB_DIVIDE_BYPASS[0]
B170	-
B169	-
B168	-
B167	-
B166	-
B165	-
B164	BUFIO2[5]:ENABLE_2CLK
B163	BUFIO2[5]:ENABLE
B162	BUFIO2[5]:R_EDGE
B161	BUFIO2[5]:DIVIDE[2]
B160	BUFIO2[5]:DIVIDE[1]
B159	BUFIO2[5]:DIVIDE[0]
B158	-
B157	BUFIO2[5]:NEG_EDGE[1]
B156	BUFIO2[5]:NEG_EDGE[0]
B155	BUFIO2[5]:POS_EDGE[2]
B154	BUFIO2[5]:POS_EDGE[1]
B153	BUFIO2[5]:POS_EDGE[0]
B152	BUFIO2[5]:FB_I[2]
B151	BUFIO2[5]:FB_I[1]
B150	BUFIO2[5]:FB_I[0]
B149	BUFIO2[5]:IB[2]
B148	BUFIO2[5]:IB[1]
B147	BUFIO2[5]:IB[0]
B146	BUFIO2[5]:I[2]
B145	BUFIO2[5]:I[1]
B144	BUFIO2[5]:I[0]
B143	BUFPLL[1]:DIVIDE[1]
B142	BUFPLL[1]:DIVIDE[0]
B141	BUFPLL[0]:DATA_RATE[0]
B140	~BUFPLL[0]:ENABLE_SYNC
B139	BUFPLL_MCB:LOCK_SRC[1]
B138	BUFPLL[0]:DIVIDE[2]
B137	BUFPLL[0]:DIVIDE[1]
B136	BUFPLL[0]:DIVIDE[0]
B135	BUFPLL_COMMON:ENABLE
B134	BUFIO2[4]:CMT_ENABLE
B133	BUFIO2[4]:CKPIN[0]
B132	BUFIO2[4]:IOCLK_ENABLE
B131	BUFIO2[4]:CKPIN[1]
B130	~BUFIO2[4]:FB_DIVIDE_BYPASS[3]
B129	~BUFIO2[4]:DIVIDE_BYPASS
B128	-
B127	BUFIO2[4]:FB_ENABLE
B126	-
B125	~BUFIO2[4]:FB_DIVIDE_BYPASS[2]
B124	~BUFIO2[4]:FB_DIVIDE_BYPASS[1]
B123	~BUFIO2[4]:FB_DIVIDE_BYPASS[0]
B122	-
B121	-
B120	-
B119	-
B118	-
B117	-
B116	BUFIO2[4]:ENABLE_2CLK
B115	BUFIO2[4]:ENABLE
B114	BUFIO2[4]:R_EDGE
B113	BUFIO2[4]:DIVIDE[2]
B112	BUFIO2[4]:DIVIDE[1]
B111	BUFIO2[4]:DIVIDE[0]
B110	-
B109	BUFIO2[4]:NEG_EDGE[1]
B108	BUFIO2[4]:NEG_EDGE[0]
B107	BUFIO2[4]:POS_EDGE[2]
B106	BUFIO2[4]:POS_EDGE[1]
B105	BUFIO2[4]:POS_EDGE[0]
B104	BUFIO2[4]:FB_I[2]
B103	BUFIO2[4]:FB_I[1]
B102	BUFIO2[4]:FB_I[0]
B101	BUFIO2[4]:IB[2]
B100	BUFIO2[4]:IB[1]
B99	BUFIO2[4]:IB[0]
B98	BUFIO2[4]:I[2]
B97	BUFIO2[4]:I[1]
B96	BUFIO2[4]:I[0]
B95	-
B94	-
B93	-
B92	-
B91	-
B90	-
B89	-
B88	-
B87	-
B86	BUFIO2[7]:CMT_ENABLE
B85	BUFIO2[7]:CKPIN[0]
B84	BUFIO2[7]:IOCLK_ENABLE
B83	BUFIO2[7]:CKPIN[1]
B82	~BUFIO2[7]:FB_DIVIDE_BYPASS[3]
B81	~BUFIO2[7]:DIVIDE_BYPASS
B80	-
B79	BUFIO2[7]:FB_ENABLE
B78	-
B77	~BUFIO2[7]:FB_DIVIDE_BYPASS[2]
B76	~BUFIO2[7]:FB_DIVIDE_BYPASS[1]
B75	~BUFIO2[7]:FB_DIVIDE_BYPASS[0]
B74	-
B73	-
B72	-
B71	-
B70	-
B69	-
B68	BUFIO2[7]:ENABLE_2CLK
B67	BUFIO2[7]:ENABLE
B66	BUFIO2[7]:R_EDGE
B65	BUFIO2[7]:DIVIDE[2]
B64	BUFIO2[7]:DIVIDE[1]
B63	BUFIO2[7]:DIVIDE[0]
B62	-
B61	BUFIO2[7]:NEG_EDGE[1]
B60	BUFIO2[7]:NEG_EDGE[0]
B59	BUFIO2[7]:POS_EDGE[2]
B58	BUFIO2[7]:POS_EDGE[1]
B57	BUFIO2[7]:POS_EDGE[0]
B56	BUFIO2[7]:FB_I[2]
B55	BUFIO2[7]:FB_I[1]
B54	BUFIO2[7]:FB_I[0]
B53	BUFIO2[7]:IB[2]
B52	BUFIO2[7]:IB[1]
B51	BUFIO2[7]:IB[0]
B50	BUFIO2[7]:I[2]
B49	BUFIO2[7]:I[1]
B48	BUFIO2[7]:I[0]
B47	-
B46	-
B45	-
B44	-
B43	-
B42	-
B41	-
B40	-
B39	-
B38	BUFIO2[6]:CMT_ENABLE
B37	BUFIO2[6]:CKPIN[0]
B36	BUFIO2[6]:IOCLK_ENABLE
B35	BUFIO2[6]:CKPIN[1]
B34	~BUFIO2[6]:FB_DIVIDE_BYPASS[3]
B33	~BUFIO2[6]:DIVIDE_BYPASS
B32	-
B31	BUFIO2[6]:FB_ENABLE
B30	-
B29	~BUFIO2[6]:FB_DIVIDE_BYPASS[2]
B28	~BUFIO2[6]:FB_DIVIDE_BYPASS[1]
B27	~BUFIO2[6]:FB_DIVIDE_BYPASS[0]
B26	-
B25	-
B24	-
B23	-
B22	-
B21	-
B20	BUFIO2[6]:ENABLE_2CLK
B19	BUFIO2[6]:ENABLE
B18	BUFIO2[6]:R_EDGE
B17	BUFIO2[6]:DIVIDE[2]
B16	BUFIO2[6]:DIVIDE[1]
B15	BUFIO2[6]:DIVIDE[0]
B14	-
B13	BUFIO2[6]:NEG_EDGE[1]
B12	BUFIO2[6]:NEG_EDGE[0]
B11	BUFIO2[6]:POS_EDGE[2]
B10	BUFIO2[6]:POS_EDGE[1]
B9	BUFIO2[6]:POS_EDGE[0]
B8	BUFIO2[6]:FB_I[2]
B7	BUFIO2[6]:FB_I[1]
B6	BUFIO2[6]:FB_I[0]
B5	BUFIO2[6]:IB[2]
B4	BUFIO2[6]:IB[1]
B3	BUFIO2[6]:IB[0]
B2	BUFIO2[6]:I[2]
B1	BUFIO2[6]:I[1]
B0	BUFIO2[6]:I[0]

BUFIO2[0]:CKPIN	0.F0.B323	0.F0.B325
BUFIO2[1]:CKPIN	0.F0.B371	0.F0.B373
BUFIO2[2]:CKPIN	0.F0.B227	0.F0.B229
BUFIO2[3]:CKPIN	0.F0.B275	0.F0.B277
BUFIO2[4]:CKPIN	0.F0.B131	0.F0.B133
BUFIO2[5]:CKPIN	0.F0.B179	0.F0.B181
BUFIO2[6]:CKPIN	0.F0.B35	0.F0.B37
BUFIO2[7]:CKPIN	0.F0.B83	0.F0.B85
VCC	0	0
CLKPIN	0	1
DIVCLK	1	1

BUFIO2[0]:CMT_ENABLE	0.F0.B326
BUFIO2[0]:ENABLE	0.F0.B307
BUFIO2[0]:ENABLE_2CLK	0.F0.B308
BUFIO2[0]:FB_ENABLE	0.F0.B319
BUFIO2[0]:IOCLK_ENABLE	0.F0.B324
BUFIO2[0]:R_EDGE	0.F0.B306
BUFIO2[1]:CMT_ENABLE	0.F0.B374
BUFIO2[1]:ENABLE	0.F0.B355
BUFIO2[1]:ENABLE_2CLK	0.F0.B356
BUFIO2[1]:FB_ENABLE	0.F0.B367
BUFIO2[1]:IOCLK_ENABLE	0.F0.B372
BUFIO2[1]:R_EDGE	0.F0.B354
BUFIO2[2]:CMT_ENABLE	0.F0.B230
BUFIO2[2]:ENABLE	0.F0.B211
BUFIO2[2]:ENABLE_2CLK	0.F0.B212
BUFIO2[2]:FB_ENABLE	0.F0.B223
BUFIO2[2]:IOCLK_ENABLE	0.F0.B228
BUFIO2[2]:R_EDGE	0.F0.B210
BUFIO2[3]:CMT_ENABLE	0.F0.B278
BUFIO2[3]:ENABLE	0.F0.B259
BUFIO2[3]:ENABLE_2CLK	0.F0.B260
BUFIO2[3]:FB_ENABLE	0.F0.B271
BUFIO2[3]:IOCLK_ENABLE	0.F0.B276
BUFIO2[3]:R_EDGE	0.F0.B258
BUFIO2[4]:CMT_ENABLE	0.F0.B134
BUFIO2[4]:ENABLE	0.F0.B115
BUFIO2[4]:ENABLE_2CLK	0.F0.B116
BUFIO2[4]:FB_ENABLE	0.F0.B127
BUFIO2[4]:IOCLK_ENABLE	0.F0.B132
BUFIO2[4]:R_EDGE	0.F0.B114
BUFIO2[5]:CMT_ENABLE	0.F0.B182
BUFIO2[5]:ENABLE	0.F0.B163
BUFIO2[5]:ENABLE_2CLK	0.F0.B164
BUFIO2[5]:FB_ENABLE	0.F0.B175
BUFIO2[5]:IOCLK_ENABLE	0.F0.B180
BUFIO2[5]:R_EDGE	0.F0.B162
BUFIO2[6]:CMT_ENABLE	0.F0.B38
BUFIO2[6]:ENABLE	0.F0.B19
BUFIO2[6]:ENABLE_2CLK	0.F0.B20
BUFIO2[6]:FB_ENABLE	0.F0.B31
BUFIO2[6]:IOCLK_ENABLE	0.F0.B36
BUFIO2[6]:R_EDGE	0.F0.B18
BUFIO2[7]:CMT_ENABLE	0.F0.B86
BUFIO2[7]:ENABLE	0.F0.B67
BUFIO2[7]:ENABLE_2CLK	0.F0.B68
BUFIO2[7]:FB_ENABLE	0.F0.B79
BUFIO2[7]:IOCLK_ENABLE	0.F0.B84
BUFIO2[7]:R_EDGE	0.F0.B66
BUFPLL_COMMON:ENABLE	0.F0.B135
non-inverted	[0]

BUFIO2[0]:DIVIDE	0.F0.B305	0.F0.B304	0.F0.B303
BUFIO2[1]:DIVIDE	0.F0.B353	0.F0.B352	0.F0.B351
BUFIO2[2]:DIVIDE	0.F0.B209	0.F0.B208	0.F0.B207
BUFIO2[3]:DIVIDE	0.F0.B257	0.F0.B256	0.F0.B255
BUFIO2[4]:DIVIDE	0.F0.B113	0.F0.B112	0.F0.B111
BUFIO2[5]:DIVIDE	0.F0.B161	0.F0.B160	0.F0.B159
BUFIO2[6]:DIVIDE	0.F0.B17	0.F0.B16	0.F0.B15
BUFIO2[7]:DIVIDE	0.F0.B65	0.F0.B64	0.F0.B63
2	0	0	0
3	0	0	1
4	0	1	0
5	0	1	1
6	1	0	0
7	1	0	1
8	1	1	0
1	1	1	1

BUFIO2[0]:DIVIDE_BYPASS	0.F0.B321
BUFIO2[1]:DIVIDE_BYPASS	0.F0.B369
BUFIO2[2]:DIVIDE_BYPASS	0.F0.B225
BUFIO2[3]:DIVIDE_BYPASS	0.F0.B273
BUFIO2[4]:DIVIDE_BYPASS	0.F0.B129
BUFIO2[5]:DIVIDE_BYPASS	0.F0.B177
BUFIO2[6]:DIVIDE_BYPASS	0.F0.B33
BUFIO2[7]:DIVIDE_BYPASS	0.F0.B81
BUFPLL[0]:ENABLE_SYNC	0.F0.B140
BUFPLL[1]:ENABLE_SYNC	0.F0.B185
inverted	~[0]

BUFIO2[0]:FB_DIVIDE_BYPASS	0.F0.B322	0.F0.B317	0.F0.B316	0.F0.B315
BUFIO2[1]:FB_DIVIDE_BYPASS	0.F0.B370	0.F0.B365	0.F0.B364	0.F0.B363
BUFIO2[2]:FB_DIVIDE_BYPASS	0.F0.B226	0.F0.B221	0.F0.B220	0.F0.B219
BUFIO2[3]:FB_DIVIDE_BYPASS	0.F0.B274	0.F0.B269	0.F0.B268	0.F0.B267
BUFIO2[4]:FB_DIVIDE_BYPASS	0.F0.B130	0.F0.B125	0.F0.B124	0.F0.B123
BUFIO2[5]:FB_DIVIDE_BYPASS	0.F0.B178	0.F0.B173	0.F0.B172	0.F0.B171
BUFIO2[6]:FB_DIVIDE_BYPASS	0.F0.B34	0.F0.B29	0.F0.B28	0.F0.B27
BUFIO2[7]:FB_DIVIDE_BYPASS	0.F0.B82	0.F0.B77	0.F0.B76	0.F0.B75
inverted	~[3]	~[2]	~[1]	~[0]

BUFIO2[0]:FB_I	0.F0.B296	0.F0.B295	0.F0.B294
BUFIO2[1]:FB_I	0.F0.B344	0.F0.B343	0.F0.B342
BUFIO2[2]:FB_I	0.F0.B200	0.F0.B199	0.F0.B198
BUFIO2[3]:FB_I	0.F0.B248	0.F0.B247	0.F0.B246
BUFIO2[4]:FB_I	0.F0.B104	0.F0.B103	0.F0.B102
BUFIO2[5]:FB_I	0.F0.B152	0.F0.B151	0.F0.B150
BUFIO2[6]:FB_I	0.F0.B8	0.F0.B7	0.F0.B6
BUFIO2[7]:FB_I	0.F0.B56	0.F0.B55	0.F0.B54
CLKPIN	0	0	0
DFB	0	0	1
CFB	0	1	0
CFB_INVERT	0	1	1
GTPFB	1	1	1

BUFIO2[0]:I	0.F0.B290	0.F0.B289	0.F0.B288
BUFIO2[2]:I	0.F0.B194	0.F0.B193	0.F0.B192
BUFIO2[4]:I	0.F0.B98	0.F0.B97	0.F0.B96
BUFIO2[5]:I	0.F0.B146	0.F0.B145	0.F0.B144
BUFIO2[6]:I	0.F0.B2	0.F0.B1	0.F0.B0
BUFIO2[7]:I	0.F0.B50	0.F0.B49	0.F0.B48
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0
GTPCLK	1	1	1

BUFIO2[0]:IB	0.F0.B293	0.F0.B292	0.F0.B291
BUFIO2[1]:IB	0.F0.B341	0.F0.B340	0.F0.B339
BUFIO2[2]:IB	0.F0.B197	0.F0.B196	0.F0.B195
BUFIO2[3]:IB	0.F0.B245	0.F0.B244	0.F0.B243
BUFIO2[4]:IB	0.F0.B101	0.F0.B100	0.F0.B99
BUFIO2[5]:IB	0.F0.B149	0.F0.B148	0.F0.B147
BUFIO2[6]:IB	0.F0.B5	0.F0.B4	0.F0.B3
BUFIO2[7]:IB	0.F0.B53	0.F0.B52	0.F0.B51
CLKPIN0	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFIO2[0]:NEG_EDGE	0.F0.B301	0.F0.B300
BUFIO2[1]:NEG_EDGE	0.F0.B349	0.F0.B348
BUFIO2[2]:NEG_EDGE	0.F0.B205	0.F0.B204
BUFIO2[3]:NEG_EDGE	0.F0.B253	0.F0.B252
BUFIO2[4]:NEG_EDGE	0.F0.B109	0.F0.B108
BUFIO2[5]:NEG_EDGE	0.F0.B157	0.F0.B156
BUFIO2[6]:NEG_EDGE	0.F0.B13	0.F0.B12
BUFIO2[7]:NEG_EDGE	0.F0.B61	0.F0.B60
DIVIDE_1	0	0
DIVIDE_3	0	0
DIVIDE_4	0	0
NEG_EDGE_1	0	0
NEG_EDGE_4	0	0
NEG_EDGE_5	0	0
NEG_EDGE_6	0	0
NEG_EDGE_7	0	0
NEG_EDGE_8	0	0
DIVIDE_2	0	1
DIVIDE_5	0	1
DIVIDE_6	0	1
NEG_EDGE_2	0	1
DIVIDE_7	1	0
DIVIDE_8	1	0
NEG_EDGE_3	1	0

BUFIO2[0]:POS_EDGE	0.F0.B299	0.F0.B298	0.F0.B297
BUFIO2[1]:POS_EDGE	0.F0.B347	0.F0.B346	0.F0.B345
BUFIO2[2]:POS_EDGE	0.F0.B203	0.F0.B202	0.F0.B201
BUFIO2[3]:POS_EDGE	0.F0.B251	0.F0.B250	0.F0.B249
BUFIO2[4]:POS_EDGE	0.F0.B107	0.F0.B106	0.F0.B105
BUFIO2[5]:POS_EDGE	0.F0.B155	0.F0.B154	0.F0.B153
BUFIO2[6]:POS_EDGE	0.F0.B11	0.F0.B10	0.F0.B9
BUFIO2[7]:POS_EDGE	0.F0.B59	0.F0.B58	0.F0.B57
DIVIDE_1	0	0	0
POS_EDGE_1	0	0	0
POS_EDGE_3	0	0	0
POS_EDGE_5	0	0	0
DIVIDE_2	0	0	1
POS_EDGE_2	0	0	1
DIVIDE_3	0	1	0
DIVIDE_4	0	1	1
POS_EDGE_4	0	1	1
DIVIDE_5	1	0	0
DIVIDE_6	1	0	1
POS_EDGE_6	1	0	1
DIVIDE_7	1	1	0
POS_EDGE_7	1	1	0
DIVIDE_8	1	1	1
POS_EDGE_8	1	1	1

BUFIO2[1]:I	0.F0.B338	0.F0.B337	0.F0.B336
BUFIO2[3]:I	0.F0.B242	0.F0.B241	0.F0.B240
CLKPIN0	0	0	0
GTPCLK	0	0	0
CLKPIN1	0	0	1
DFB	0	1	0
DQS0	0	1	1
CLKPIN4	1	0	0
CLKPIN5	1	0	1
DQS2	1	1	0

BUFPLL[0]:DATA_RATE	0.F0.B141
BUFPLL[1]:DATA_RATE	0.F0.B186
SDR	0
DDR	1

BUFPLL[0]:DIVIDE	0.F0.B190	0.F0.B189	0.F0.B187	0.F0.B138	0.F0.B137	0.F0.B136
BUFPLL[1]:DIVIDE	0.F0.B233	0.F0.B232	0.F0.B191	0.F0.B183	0.F0.B143	0.F0.B142
3	0	0	0	0	0	1
2	0	0	1	0	0	0
5	0	1	0	0	1	1
4	0	1	1	0	1	0
7	1	0	0	1	0	1
6	1	0	1	1	0	0
1	1	1	0	1	1	1
8	1	1	1	1	1	0

BUFPLL[0]:ENABLE_BOTH_SYNC	0.F0.B286	0.F0.B280	0.F0.B234
BUFPLL[1]:ENABLE_BOTH_SYNC	0.F0.B329	0.F0.B282	0.F0.B237
non-inverted	[2]	[1]	[0]

BUFPLL[0]:ENABLE_NONE_SYNC	0.F0.B285	0.F0.B279
BUFPLL[1]:ENABLE_NONE_SYNC	0.F0.B328	0.F0.B281
non-inverted	[1]	[0]

BUFPLL_COMMON:PLLIN	0.F0.B330
CMT	0
GCLK	1

BUFPLL_MCB:LOCK_SRC	0.F0.B139	0.F0.B184
LOCK_TO_0	0	1
LOCK_TO_1	1	0

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