Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Global buffers

Tile CLKC

Cells: 6

Switchbox CLKC_INT

spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[0]
BitsDestination
MAIN[25][32]MAIN[25][48]MAIN[25][0]MAIN[25][16]N.IMUX_BUFG[0]
Source
0000off
0001S.CMT_CLKC_I[0]
0010N.CMT_CLKC_I[0]
0100EDGE_E.DIVCLK_CLKC[0]
1000EDGE_N.DIVCLK_CLKC[0]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[1]
BitsDestination
MAIN[25][33]MAIN[25][49]MAIN[25][1]MAIN[25][17]N.IMUX_BUFG[1]
Source
0000off
0001S.CMT_CLKC_I[1]
0010N.CMT_CLKC_I[1]
0100EDGE_E.DIVCLK_CLKC[1]
1000EDGE_N.DIVCLK_CLKC[1]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[2]
BitsDestination
MAIN[25][34]MAIN[25][50]MAIN[25][2]MAIN[25][18]N.IMUX_BUFG[2]
Source
0000off
0001S.CMT_CLKC_I[2]
0010N.CMT_CLKC_I[2]
0100EDGE_E.DIVCLK_CLKC[2]
1000EDGE_N.DIVCLK_CLKC[2]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[3]
BitsDestination
MAIN[25][35]MAIN[25][51]MAIN[25][3]MAIN[25][19]N.IMUX_BUFG[3]
Source
0000off
0001S.CMT_CLKC_I[3]
0010N.CMT_CLKC_I[3]
0100EDGE_E.DIVCLK_CLKC[3]
1000EDGE_N.DIVCLK_CLKC[3]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[4]
BitsDestination
MAIN[25][36]MAIN[25][52]MAIN[25][4]MAIN[25][20]N.IMUX_BUFG[4]
Source
0000off
0001S.CMT_CLKC_I[4]
0010N.CMT_CLKC_I[4]
0100EDGE_E.DIVCLK_CLKC[4]
1000EDGE_N.DIVCLK_CLKC[4]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[5]
BitsDestination
MAIN[25][37]MAIN[25][53]MAIN[25][5]MAIN[25][21]N.IMUX_BUFG[5]
Source
0000off
0001S.CMT_CLKC_I[5]
0010N.CMT_CLKC_I[5]
0100EDGE_E.DIVCLK_CLKC[5]
1000EDGE_N.DIVCLK_CLKC[5]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[6]
BitsDestination
MAIN[25][38]MAIN[25][54]MAIN[25][6]MAIN[25][22]N.IMUX_BUFG[6]
Source
0000off
0001S.CMT_CLKC_I[6]
0010N.CMT_CLKC_I[6]
0100EDGE_E.DIVCLK_CLKC[6]
1000EDGE_N.DIVCLK_CLKC[6]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[7]
BitsDestination
MAIN[25][39]MAIN[25][55]MAIN[25][7]MAIN[25][23]N.IMUX_BUFG[7]
Source
0000off
0001S.CMT_CLKC_I[7]
0010N.CMT_CLKC_I[7]
0100EDGE_E.DIVCLK_CLKC[7]
1000EDGE_N.DIVCLK_CLKC[7]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[8]
BitsDestination
MAIN[25][40]MAIN[25][56]MAIN[25][8]MAIN[25][24]N.IMUX_BUFG[8]
Source
0000off
0001S.CMT_CLKC_I[8]
0010N.CMT_CLKC_I[8]
0100EDGE_W.DIVCLK_CLKC[0]
1000EDGE_S.DIVCLK_CLKC[0]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[9]
BitsDestination
MAIN[25][41]MAIN[25][57]MAIN[25][9]MAIN[25][25]N.IMUX_BUFG[9]
Source
0000off
0001S.CMT_CLKC_I[9]
0010N.CMT_CLKC_I[9]
0100EDGE_W.DIVCLK_CLKC[1]
1000EDGE_S.DIVCLK_CLKC[1]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[10]
BitsDestination
MAIN[25][42]MAIN[25][58]MAIN[25][10]MAIN[25][26]N.IMUX_BUFG[10]
Source
0000off
0001S.CMT_CLKC_I[10]
0010N.CMT_CLKC_I[10]
0100EDGE_W.DIVCLK_CLKC[2]
1000EDGE_S.DIVCLK_CLKC[2]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[11]
BitsDestination
MAIN[25][43]MAIN[25][59]MAIN[25][11]MAIN[25][27]N.IMUX_BUFG[11]
Source
0000off
0001S.CMT_CLKC_I[11]
0010N.CMT_CLKC_I[11]
0100EDGE_W.DIVCLK_CLKC[3]
1000EDGE_S.DIVCLK_CLKC[3]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[12]
BitsDestination
MAIN[25][44]MAIN[25][60]MAIN[25][12]MAIN[25][28]N.IMUX_BUFG[12]
Source
0000off
0001S.CMT_CLKC_I[12]
0010N.CMT_CLKC_I[12]
0100EDGE_W.DIVCLK_CLKC[4]
1000EDGE_S.DIVCLK_CLKC[4]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[13]
BitsDestination
MAIN[25][45]MAIN[25][61]MAIN[25][13]MAIN[25][29]N.IMUX_BUFG[13]
Source
0000off
0001S.CMT_CLKC_I[13]
0010N.CMT_CLKC_I[13]
0100EDGE_W.DIVCLK_CLKC[5]
1000EDGE_S.DIVCLK_CLKC[5]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[14]
BitsDestination
MAIN[25][46]MAIN[25][62]MAIN[25][14]MAIN[25][30]N.IMUX_BUFG[14]
Source
0000off
0001S.CMT_CLKC_I[14]
0010N.CMT_CLKC_I[14]
0100EDGE_W.DIVCLK_CLKC[6]
1000EDGE_S.DIVCLK_CLKC[6]
spartan6 CLKC switchbox CLKC_INT muxes IMUX_BUFG[15]
BitsDestination
MAIN[25][47]MAIN[25][63]MAIN[25][15]MAIN[25][31]N.IMUX_BUFG[15]
Source
0000off
0001S.CMT_CLKC_I[15]
0010N.CMT_CLKC_I[15]
0100EDGE_W.DIVCLK_CLKC[7]
1000EDGE_S.DIVCLK_CLKC[7]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_CLKOUT_S[4]
BitsDestination
MAIN[22][23]MAIN[22][22]N.CMT_BUFPLL_V_CLKOUT_S[4]
Source
00N.CMT_BUFPLL_V_CLKOUT_N[1]
01N.CMT_BUFPLL_V_CLKOUT_N[0]
10N.CMT_BUFPLL_V_CLKOUT_N[3]
11N.CMT_BUFPLL_V_CLKOUT_N[2]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_CLKOUT_S[5]
BitsDestination
MAIN[22][21]MAIN[22][20]N.CMT_BUFPLL_V_CLKOUT_S[5]
Source
00N.CMT_BUFPLL_V_CLKOUT_N[1]
01N.CMT_BUFPLL_V_CLKOUT_N[0]
10N.CMT_BUFPLL_V_CLKOUT_N[3]
11N.CMT_BUFPLL_V_CLKOUT_N[2]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_CLKOUT_N[4]
BitsDestination
MAIN[22][17]MAIN[22][16]N.CMT_BUFPLL_V_CLKOUT_N[4]
Source
00N.CMT_BUFPLL_V_CLKOUT_S[0]
01N.CMT_BUFPLL_V_CLKOUT_S[1]
10N.CMT_BUFPLL_V_CLKOUT_S[2]
11N.CMT_BUFPLL_V_CLKOUT_S[3]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_CLKOUT_N[5]
BitsDestination
MAIN[22][19]MAIN[22][18]N.CMT_BUFPLL_V_CLKOUT_N[5]
Source
00N.CMT_BUFPLL_V_CLKOUT_S[0]
01N.CMT_BUFPLL_V_CLKOUT_S[1]
10N.CMT_BUFPLL_V_CLKOUT_S[2]
11N.CMT_BUFPLL_V_CLKOUT_S[3]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_LOCKED_S[2]
BitsDestination
MAIN[22][32]N.CMT_BUFPLL_V_LOCKED_S[2]
Source
0N.CMT_BUFPLL_V_LOCKED_N[1]
1N.CMT_BUFPLL_V_LOCKED_N[0]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_V_LOCKED_N[2]
BitsDestination
MAIN[22][33]N.CMT_BUFPLL_V_LOCKED_N[2]
Source
0N.CMT_BUFPLL_V_LOCKED_S[1]
1N.CMT_BUFPLL_V_LOCKED_S[0]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_H_CLKOUT[0]
BitsDestination
MAIN[22][2]MAIN[22][1]MAIN[22][0]EDGE_W.CMT_BUFPLL_H_CLKOUT[0]
MAIN[22][10]MAIN[22][9]MAIN[22][8]EDGE_E.CMT_BUFPLL_H_CLKOUT[0]
Source
000N.CMT_BUFPLL_V_CLKOUT_N[0]
001N.CMT_BUFPLL_V_CLKOUT_N[1]
010N.CMT_BUFPLL_V_CLKOUT_N[2]
011N.CMT_BUFPLL_V_CLKOUT_N[3]
100N.CMT_BUFPLL_V_CLKOUT_S[3]
101N.CMT_BUFPLL_V_CLKOUT_S[2]
110N.CMT_BUFPLL_V_CLKOUT_S[1]
111N.CMT_BUFPLL_V_CLKOUT_S[0]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_H_CLKOUT[1]
BitsDestination
MAIN[22][5]MAIN[22][4]MAIN[22][3]EDGE_W.CMT_BUFPLL_H_CLKOUT[1]
MAIN[22][13]MAIN[22][12]MAIN[22][11]EDGE_E.CMT_BUFPLL_H_CLKOUT[1]
Source
000N.CMT_BUFPLL_V_CLKOUT_N[0]
001N.CMT_BUFPLL_V_CLKOUT_N[1]
010N.CMT_BUFPLL_V_CLKOUT_N[2]
011N.CMT_BUFPLL_V_CLKOUT_N[3]
100N.CMT_BUFPLL_V_CLKOUT_S[3]
101N.CMT_BUFPLL_V_CLKOUT_S[2]
110N.CMT_BUFPLL_V_CLKOUT_S[1]
111N.CMT_BUFPLL_V_CLKOUT_S[0]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_H_LOCKED[0]
BitsDestination
MAIN[22][27]MAIN[22][26]EDGE_W.CMT_BUFPLL_H_LOCKED[0]
MAIN[22][31]MAIN[22][30]EDGE_E.CMT_BUFPLL_H_LOCKED[0]
Source
00N.CMT_BUFPLL_V_LOCKED_S[0]
01N.CMT_BUFPLL_V_LOCKED_S[1]
10N.CMT_BUFPLL_V_LOCKED_N[1]
11N.CMT_BUFPLL_V_LOCKED_N[0]
spartan6 CLKC switchbox CLKC_INT muxes CMT_BUFPLL_H_LOCKED[1]
BitsDestination
MAIN[22][25]MAIN[22][24]EDGE_W.CMT_BUFPLL_H_LOCKED[1]
MAIN[22][29]MAIN[22][28]EDGE_E.CMT_BUFPLL_H_LOCKED[1]
Source
00N.CMT_BUFPLL_V_LOCKED_S[0]
01N.CMT_BUFPLL_V_LOCKED_S[1]
10N.CMT_BUFPLL_V_LOCKED_N[1]
11N.CMT_BUFPLL_V_LOCKED_N[0]

Bels BUFGMUX

spartan6 CLKC bel BUFGMUX pins
PinDirectionBUFGMUX[0]BUFGMUX[1]BUFGMUX[2]BUFGMUX[3]BUFGMUX[4]BUFGMUX[5]BUFGMUX[6]BUFGMUX[7]BUFGMUX[8]BUFGMUX[9]BUFGMUX[10]BUFGMUX[11]BUFGMUX[12]BUFGMUX[13]BUFGMUX[14]BUFGMUX[15]
I0inN.IMUX_BUFG[0]N.IMUX_BUFG[1]N.IMUX_BUFG[2]N.IMUX_BUFG[4]N.IMUX_BUFG[3]N.IMUX_BUFG[5]N.IMUX_BUFG[6]N.IMUX_BUFG[7]N.IMUX_BUFG[8]N.IMUX_BUFG[9]N.IMUX_BUFG[10]N.IMUX_BUFG[12]N.IMUX_BUFG[11]N.IMUX_BUFG[13]N.IMUX_BUFG[14]N.IMUX_BUFG[15]
I1inN.IMUX_BUFG[1]N.IMUX_BUFG[0]N.IMUX_BUFG[4]N.IMUX_BUFG[2]N.IMUX_BUFG[5]N.IMUX_BUFG[3]N.IMUX_BUFG[7]N.IMUX_BUFG[6]N.IMUX_BUFG[9]N.IMUX_BUFG[8]N.IMUX_BUFG[12]N.IMUX_BUFG[10]N.IMUX_BUFG[13]N.IMUX_BUFG[11]N.IMUX_BUFG[15]N.IMUX_BUFG[14]
SinN.IMUX_LOGICIN[24] invert by !MAIN[28][0]N.IMUX_LOGICIN[15] invert by !MAIN[28][1]N.IMUX_LOGICIN[7] invert by !MAIN[28][2]N.IMUX_LOGICIN[42] invert by !MAIN[28][3]N.IMUX_LOGICIN[5] invert by !MAIN[28][4]N.IMUX_LOGICIN[12] invert by !MAIN[28][5]N.IMUX_LOGICIN[62] invert by !MAIN[28][6]N.IMUX_LOGICIN[16] invert by !MAIN[28][7]N.IMUX_LOGICIN[47] invert by !MAIN[28][8]N.IMUX_LOGICIN[20] invert by !MAIN[28][9]N.IMUX_LOGICIN[38] invert by !MAIN[28][10]N.IMUX_LOGICIN[23] invert by !MAIN[28][11]N.IMUX_LOGICIN[48] invert by !MAIN[28][12]N.IMUX_LOGICIN[57] invert by !MAIN[28][13]N.IMUX_LOGICIN[44] invert by !MAIN[28][14]N.IMUX_LOGICIN[4] invert by !MAIN[28][15]
OoutN.GCLK[0]N.GCLK[1]N.GCLK[2]N.GCLK[3]N.GCLK[4]N.GCLK[5]N.GCLK[6]N.GCLK[7]N.GCLK[8]N.GCLK[9]N.GCLK[10]N.GCLK[11]N.GCLK[12]N.GCLK[13]N.GCLK[14]N.GCLK[15]
spartan6 CLKC bel BUFGMUX attribute bits
AttributeBUFGMUX[0]BUFGMUX[1]BUFGMUX[2]BUFGMUX[3]BUFGMUX[4]BUFGMUX[5]BUFGMUX[6]BUFGMUX[7]BUFGMUX[8]BUFGMUX[9]BUFGMUX[10]BUFGMUX[11]BUFGMUX[12]BUFGMUX[13]BUFGMUX[14]BUFGMUX[15]
INIT_OUT bit 0MAIN[27][16]MAIN[27][17]MAIN[27][18]MAIN[27][19]MAIN[27][20]MAIN[27][21]MAIN[27][22]MAIN[27][23]MAIN[27][24]MAIN[27][25]MAIN[27][26]MAIN[27][27]MAIN[27][28]MAIN[27][29]MAIN[27][30]MAIN[27][31]
CLK_SEL_TYPE[enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE][enum: BUFGMUX_CLK_SEL_TYPE]
spartan6 CLKC enum BUFGMUX_CLK_SEL_TYPE
BUFGMUX[0].CLK_SEL_TYPEMAIN[26][0]
BUFGMUX[1].CLK_SEL_TYPEMAIN[26][1]
BUFGMUX[2].CLK_SEL_TYPEMAIN[26][2]
BUFGMUX[3].CLK_SEL_TYPEMAIN[26][3]
BUFGMUX[4].CLK_SEL_TYPEMAIN[26][4]
BUFGMUX[5].CLK_SEL_TYPEMAIN[26][5]
BUFGMUX[6].CLK_SEL_TYPEMAIN[26][6]
BUFGMUX[7].CLK_SEL_TYPEMAIN[26][7]
BUFGMUX[8].CLK_SEL_TYPEMAIN[26][8]
BUFGMUX[9].CLK_SEL_TYPEMAIN[26][9]
BUFGMUX[10].CLK_SEL_TYPEMAIN[26][10]
BUFGMUX[11].CLK_SEL_TYPEMAIN[26][11]
BUFGMUX[12].CLK_SEL_TYPEMAIN[26][12]
BUFGMUX[13].CLK_SEL_TYPEMAIN[26][13]
BUFGMUX[14].CLK_SEL_TYPEMAIN[26][14]
BUFGMUX[15].CLK_SEL_TYPEMAIN[26][15]
SYNC0
ASYNC1

Bel wires

spartan6 CLKC bel wires
WirePins
N.IMUX_LOGICIN[4]BUFGMUX[15].S
N.IMUX_LOGICIN[5]BUFGMUX[4].S
N.IMUX_LOGICIN[7]BUFGMUX[2].S
N.IMUX_LOGICIN[12]BUFGMUX[5].S
N.IMUX_LOGICIN[15]BUFGMUX[1].S
N.IMUX_LOGICIN[16]BUFGMUX[7].S
N.IMUX_LOGICIN[20]BUFGMUX[9].S
N.IMUX_LOGICIN[23]BUFGMUX[11].S
N.IMUX_LOGICIN[24]BUFGMUX[0].S
N.IMUX_LOGICIN[38]BUFGMUX[10].S
N.IMUX_LOGICIN[42]BUFGMUX[3].S
N.IMUX_LOGICIN[44]BUFGMUX[14].S
N.IMUX_LOGICIN[47]BUFGMUX[8].S
N.IMUX_LOGICIN[48]BUFGMUX[12].S
N.IMUX_LOGICIN[57]BUFGMUX[13].S
N.IMUX_LOGICIN[62]BUFGMUX[6].S
N.IMUX_BUFG[0]BUFGMUX[0].I0, BUFGMUX[1].I1
N.IMUX_BUFG[1]BUFGMUX[1].I0, BUFGMUX[0].I1
N.IMUX_BUFG[2]BUFGMUX[2].I0, BUFGMUX[3].I1
N.IMUX_BUFG[3]BUFGMUX[4].I0, BUFGMUX[5].I1
N.IMUX_BUFG[4]BUFGMUX[3].I0, BUFGMUX[2].I1
N.IMUX_BUFG[5]BUFGMUX[5].I0, BUFGMUX[4].I1
N.IMUX_BUFG[6]BUFGMUX[6].I0, BUFGMUX[7].I1
N.IMUX_BUFG[7]BUFGMUX[7].I0, BUFGMUX[6].I1
N.IMUX_BUFG[8]BUFGMUX[8].I0, BUFGMUX[9].I1
N.IMUX_BUFG[9]BUFGMUX[9].I0, BUFGMUX[8].I1
N.IMUX_BUFG[10]BUFGMUX[10].I0, BUFGMUX[11].I1
N.IMUX_BUFG[11]BUFGMUX[12].I0, BUFGMUX[13].I1
N.IMUX_BUFG[12]BUFGMUX[11].I0, BUFGMUX[10].I1
N.IMUX_BUFG[13]BUFGMUX[13].I0, BUFGMUX[12].I1
N.IMUX_BUFG[14]BUFGMUX[14].I0, BUFGMUX[15].I1
N.IMUX_BUFG[15]BUFGMUX[15].I0, BUFGMUX[14].I1
N.GCLK[0]BUFGMUX[0].O
N.GCLK[1]BUFGMUX[1].O
N.GCLK[2]BUFGMUX[2].O
N.GCLK[3]BUFGMUX[3].O
N.GCLK[4]BUFGMUX[4].O
N.GCLK[5]BUFGMUX[5].O
N.GCLK[6]BUFGMUX[6].O
N.GCLK[7]BUFGMUX[7].O
N.GCLK[8]BUFGMUX[8].O
N.GCLK[9]BUFGMUX[9].O
N.GCLK[10]BUFGMUX[10].O
N.GCLK[11]BUFGMUX[11].O
N.GCLK[12]BUFGMUX[12].O
N.GCLK[13]BUFGMUX[13].O
N.GCLK[14]BUFGMUX[14].O
N.GCLK[15]BUFGMUX[15].O

Bitstream

spartan6 CLKC rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
B63 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[15] bit 2 - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[14] bit 2 - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[13] bit 2 - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[12] bit 2 - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[11] bit 2 - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[10] bit 2 - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[9] bit 2 - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[8] bit 2 - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[7] bit 2 - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[6] bit 2 - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[5] bit 2 - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[4] bit 2 - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[3] bit 2 - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[2] bit 2 - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[1] bit 2 - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[0] bit 2 - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[15] bit 3 - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[14] bit 3 - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[13] bit 3 - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[12] bit 3 - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[11] bit 3 - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[10] bit 3 - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[9] bit 3 - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[8] bit 3 - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[7] bit 3 - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[6] bit 3 - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[5] bit 3 - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[4] bit 3 - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[3] bit 3 - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[2] bit 3 - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_LOCKED_N[2] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[1] bit 3 - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_LOCKED_S[2] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[0] bit 3 - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_LOCKED[0] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[15] bit 0 - BUFGMUX[15]: INIT_OUT bit 0 - - -
B30 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_LOCKED[0] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[14] bit 0 - BUFGMUX[14]: INIT_OUT bit 0 - - -
B29 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_LOCKED[1] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[13] bit 0 - BUFGMUX[13]: INIT_OUT bit 0 - - -
B28 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_LOCKED[1] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[12] bit 0 - BUFGMUX[12]: INIT_OUT bit 0 - - -
B27 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_LOCKED[0] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[11] bit 0 - BUFGMUX[11]: INIT_OUT bit 0 - - -
B26 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_LOCKED[0] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[10] bit 0 - BUFGMUX[10]: INIT_OUT bit 0 - - -
B25 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_LOCKED[1] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[9] bit 0 - BUFGMUX[9]: INIT_OUT bit 0 - - -
B24 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_LOCKED[1] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[8] bit 0 - BUFGMUX[8]: INIT_OUT bit 0 - - -
B23 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_S[4] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[7] bit 0 - BUFGMUX[7]: INIT_OUT bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_S[4] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[6] bit 0 - BUFGMUX[6]: INIT_OUT bit 0 - - -
B21 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_S[5] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[5] bit 0 - BUFGMUX[5]: INIT_OUT bit 0 - - -
B20 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_S[5] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[4] bit 0 - BUFGMUX[4]: INIT_OUT bit 0 - - -
B19 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_N[5] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[3] bit 0 - BUFGMUX[3]: INIT_OUT bit 0 - - -
B18 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_N[5] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[2] bit 0 - BUFGMUX[2]: INIT_OUT bit 0 - - -
B17 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_N[4] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[1] bit 0 - BUFGMUX[1]: INIT_OUT bit 0 - - -
B16 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.CMT_BUFPLL_V_CLKOUT_N[4] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[0] bit 0 - BUFGMUX[0]: INIT_OUT bit 0 - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[15] bit 1 BUFGMUX[15]: CLK_SEL_TYPE bit 0 - BUFGMUX[15]: !invert S - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[14] bit 1 BUFGMUX[14]: CLK_SEL_TYPE bit 0 - BUFGMUX[14]: !invert S - -
B13 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[1] bit 2 - - CLKC_INT: mux N.IMUX_BUFG[13] bit 1 BUFGMUX[13]: CLK_SEL_TYPE bit 0 - BUFGMUX[13]: !invert S - -
B12 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[1] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[12] bit 1 BUFGMUX[12]: CLK_SEL_TYPE bit 0 - BUFGMUX[12]: !invert S - -
B11 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[1] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[11] bit 1 BUFGMUX[11]: CLK_SEL_TYPE bit 0 - BUFGMUX[11]: !invert S - -
B10 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[0] bit 2 - - CLKC_INT: mux N.IMUX_BUFG[10] bit 1 BUFGMUX[10]: CLK_SEL_TYPE bit 0 - BUFGMUX[10]: !invert S - -
B9 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[0] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[9] bit 1 BUFGMUX[9]: CLK_SEL_TYPE bit 0 - BUFGMUX[9]: !invert S - -
B8 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_E.CMT_BUFPLL_H_CLKOUT[0] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[8] bit 1 BUFGMUX[8]: CLK_SEL_TYPE bit 0 - BUFGMUX[8]: !invert S - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[7] bit 1 BUFGMUX[7]: CLK_SEL_TYPE bit 0 - BUFGMUX[7]: !invert S - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux N.IMUX_BUFG[6] bit 1 BUFGMUX[6]: CLK_SEL_TYPE bit 0 - BUFGMUX[6]: !invert S - -
B5 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[1] bit 2 - - CLKC_INT: mux N.IMUX_BUFG[5] bit 1 BUFGMUX[5]: CLK_SEL_TYPE bit 0 - BUFGMUX[5]: !invert S - -
B4 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[1] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[4] bit 1 BUFGMUX[4]: CLK_SEL_TYPE bit 0 - BUFGMUX[4]: !invert S - -
B3 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[1] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[3] bit 1 BUFGMUX[3]: CLK_SEL_TYPE bit 0 - BUFGMUX[3]: !invert S - -
B2 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[0] bit 2 - - CLKC_INT: mux N.IMUX_BUFG[2] bit 1 BUFGMUX[2]: CLK_SEL_TYPE bit 0 - BUFGMUX[2]: !invert S - -
B1 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[0] bit 1 - - CLKC_INT: mux N.IMUX_BUFG[1] bit 1 BUFGMUX[1]: CLK_SEL_TYPE bit 0 - BUFGMUX[1]: !invert S - -
B0 - - - - - - - - - - - - - - - - - - - - - - CLKC_INT: mux EDGE_W.CMT_BUFPLL_H_CLKOUT[0] bit 0 - - CLKC_INT: mux N.IMUX_BUFG[0] bit 1 BUFGMUX[0]: CLK_SEL_TYPE bit 0 - BUFGMUX[0]: !invert S - -