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Configuration registers

TODO: document

COR1

spartan6 REG.COR1 rect R0
BitFrame
F0
B0 STARTUP:STARTUPCLK[0]
B1 STARTUP:STARTUPCLK[1]
B2 STARTUP:DRIVE_DONE
B3 STARTUP:DONE_PIPE
B4 ~STARTUP:CRC
B5 STARTUP:VRDSEL[0]
B6 STARTUP:VRDSEL[1]
B7 STARTUP:VRDSEL[2]
B8 MISC:SEND_VGG[0]
B9 MISC:SEND_VGG[1]
B10 MISC:SEND_VGG[2]
B11 MISC:SEND_VGG[3]
B12 ~MISC:VGG_SENDMAX
B13 ~MISC:VGG_ENABLE_OFFCHIP
B14 -
B15 STARTUP:DRIVE_AWAKE
MISC:SEND_VGG 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8
non-inverted [3] [2] [1] [0]
MISC:VGG_ENABLE_OFFCHIP 0.F0.B13
MISC:VGG_SENDMAX 0.F0.B12
STARTUP:CRC 0.F0.B4
inverted ~[0]
STARTUP:DONE_PIPE 0.F0.B3
STARTUP:DRIVE_AWAKE 0.F0.B15
STARTUP:DRIVE_DONE 0.F0.B2
non-inverted [0]
STARTUP:STARTUPCLK 0.F0.B1 0.F0.B0
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.F0.B7 0.F0.B6 0.F0.B5
non-inverted [2] [1] [0]

COR2

spartan6 REG.COR2 rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 STARTUP:LCK_CYCLE[0]
B7 STARTUP:LCK_CYCLE[1]
B8 STARTUP:LCK_CYCLE[2]
B9 STARTUP:DONE_CYCLE[0]
B10 STARTUP:DONE_CYCLE[1]
B11 STARTUP:DONE_CYCLE[2]
B12 STARTUP:DISABLE_VRD_REG
B13 STARTUP:BPI_DIV8
B14 STARTUP:BPI_DIV16
B15 STARTUP:RESET_ON_ERR
STARTUP:BPI_DIV16 0.F0.B14
STARTUP:BPI_DIV8 0.F0.B13
STARTUP:DISABLE_VRD_REG 0.F0.B12
STARTUP:RESET_ON_ERR 0.F0.B15
non-inverted [0]
STARTUP:DONE_CYCLE 0.F0.B11 0.F0.B10 0.F0.B9
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
KEEP 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
DONE 1 1 1
STARTUP:LCK_CYCLE 0.F0.B8 0.F0.B7 0.F0.B6
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1

CTL

spartan6 REG.CTL rect R0
BitFrame
F0
B0 MISC:GTS_USR_B
B1 ~MISC:POST_CRC_INIT_FLAG
B2 MISC:ENCRYPT_KEY_SELECT[0]
B3 MISC:PERSIST
B4 MISC:SECURITY[0]
B5 MISC:SECURITY[1]
B6 MISC:ENCRYPT
B7 MISC:MULTIBOOT_ENABLE
MISC:ENCRYPT 0.F0.B6
MISC:GTS_USR_B 0.F0.B0
MISC:MULTIBOOT_ENABLE 0.F0.B7
MISC:PERSIST 0.F0.B3
non-inverted [0]
MISC:ENCRYPT_KEY_SELECT 0.F0.B2
BBRAM 0
EFUSE 1
MISC:POST_CRC_INIT_FLAG 0.F0.B1
inverted ~[0]
MISC:SECURITY 0.F0.B5 0.F0.B4
NONE 0 0
LEVEL1 0 1
LEVEL2 1 0
LEVEL3 1 1

CCLK_FREQ

spartan6 REG.CCLK_FREQ rect R0
BitFrame
F0
B0 STARTUP:CCLK_DIVISOR[0]
B1 STARTUP:CCLK_DIVISOR[1]
B2 STARTUP:CCLK_DIVISOR[2]
B3 STARTUP:CCLK_DIVISOR[3]
B4 STARTUP:CCLK_DIVISOR[4]
B5 STARTUP:CCLK_DIVISOR[5]
B6 STARTUP:CCLK_DIVISOR[6]
B7 STARTUP:CCLK_DIVISOR[7]
B8 STARTUP:CCLK_DIVISOR[8]
B9 STARTUP:CCLK_DIVISOR[9]
B10 STARTUP:CCLK_DLY[0]
B11 STARTUP:CCLK_DLY[1]
B12 STARTUP:CCLK_SEP[0]
B13 STARTUP:CCLK_SEP[1]
B14 STARTUP:EXT_CCLK_ENABLE
STARTUP:CCLK_DIVISOR 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
STARTUP:CCLK_DLY 0.F0.B11 0.F0.B10
STARTUP:CCLK_SEP 0.F0.B13 0.F0.B12
non-inverted [1] [0]
STARTUP:EXT_CCLK_ENABLE 0.F0.B14
non-inverted [0]

HC_OPT

spartan6 REG.HC_OPT rect R0
BitFrame
F0
B0 MISC:HC_CYCLE[0]
B1 MISC:HC_CYCLE[1]
B2 MISC:HC_CYCLE[2]
B3 MISC:HC_CYCLE[3]
B4 MISC:TWO_ROUND
B5 MISC:BRAM_SKIP
B6 MISC:INIT_SKIP
MISC:BRAM_SKIP 0.F0.B5
MISC:INIT_SKIP 0.F0.B6
MISC:TWO_ROUND 0.F0.B4
non-inverted [0]
MISC:HC_CYCLE 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [3] [2] [1] [0]

POWERDOWN

spartan6 REG.POWERDOWN rect R0
BitFrame
F0
B0 MISC:SW_CLK[0]
B1 -
B2 MISC:EN_SUSPEND
B3 -
B4 MISC:EN_SW_GSR
B5 ~MISC:SUSPEND_FILTER
B6 MISC:WAKE_DELAY1[0]
B7 MISC:WAKE_DELAY1[1]
B8 MISC:WAKE_DELAY1[2]
B9 MISC:WAKE_DELAY2[0]
B10 MISC:WAKE_DELAY2[1]
B11 MISC:WAKE_DELAY2[2]
B12 MISC:WAKE_DELAY2[3]
B13 MISC:WAKE_DELAY2[4]
B14 MISC:MULTIPIN_WAKEUP
MISC:EN_SUSPEND 0.F0.B2
MISC:EN_SW_GSR 0.F0.B4
MISC:MULTIPIN_WAKEUP 0.F0.B14
non-inverted [0]
MISC:SUSPEND_FILTER 0.F0.B5
inverted ~[0]
MISC:SW_CLK 0.F0.B0
INTERNALCLK 0
STARTUPCLK 1
MISC:WAKE_DELAY1 0.F0.B8 0.F0.B7 0.F0.B6
non-inverted [2] [1] [0]
MISC:WAKE_DELAY2 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9
non-inverted [4] [3] [2] [1] [0]

PU_GWE

spartan6 REG.PU_GWE rect R0
BitFrame
F0
B0 MISC:SW_GWE_CYCLE[0]
B1 MISC:SW_GWE_CYCLE[1]
B2 MISC:SW_GWE_CYCLE[2]
B3 MISC:SW_GWE_CYCLE[3]
B4 MISC:SW_GWE_CYCLE[4]
B5 MISC:SW_GWE_CYCLE[5]
B6 MISC:SW_GWE_CYCLE[6]
B7 MISC:SW_GWE_CYCLE[7]
B8 MISC:SW_GWE_CYCLE[8]
B9 MISC:SW_GWE_CYCLE[9]
MISC:SW_GWE_CYCLE 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

PU_GTS

spartan6 REG.PU_GTS rect R0
BitFrame
F0
B0 MISC:SW_GTS_CYCLE[0]
B1 MISC:SW_GTS_CYCLE[1]
B2 MISC:SW_GTS_CYCLE[2]
B3 MISC:SW_GTS_CYCLE[3]
B4 MISC:SW_GTS_CYCLE[4]
B5 MISC:SW_GTS_CYCLE[5]
B6 MISC:SW_GTS_CYCLE[6]
B7 MISC:SW_GTS_CYCLE[7]
B8 MISC:SW_GTS_CYCLE[8]
B9 MISC:SW_GTS_CYCLE[9]
MISC:SW_GTS_CYCLE 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

EYE_MASK

spartan6 REG.EYE_MASK rect R0
BitFrame
F0
B0 MISC:WAKEUP_MASK[0]
B1 MISC:WAKEUP_MASK[1]
B2 MISC:WAKEUP_MASK[2]
B3 MISC:WAKEUP_MASK[3]
B4 MISC:WAKEUP_MASK[4]
B5 MISC:WAKEUP_MASK[5]
B6 MISC:WAKEUP_MASK[6]
B7 MISC:WAKEUP_MASK[7]
MISC:WAKEUP_MASK 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]

MODE

spartan6 REG.MODE rect R0
BitFrame
F0
B0 -
B1 -
B2 -
B3 -
B4 -
B5 -
B6 -
B7 -
B8 MISC:NEXT_CONFIG_BOOT_MODE[0]
B9 MISC:NEXT_CONFIG_BOOT_MODE[1]
B10 MISC:NEXT_CONFIG_BOOT_MODE[2]
B11 MISC:SPI_BUSWIDTH[0]
B12 MISC:SPI_BUSWIDTH[1]
B13 MISC:NEXT_CONFIG_NEW_MODE
MISC:NEXT_CONFIG_BOOT_MODE 0.F0.B10 0.F0.B9 0.F0.B8
non-inverted [2] [1] [0]
MISC:NEXT_CONFIG_NEW_MODE 0.F0.B13
non-inverted [0]
MISC:SPI_BUSWIDTH 0.F0.B12 0.F0.B11
1 0 0
2 0 1
4 1 0

GENERAL[12]

spartan6 REG.GENERAL12 rect R0
BitFrame
F0
B0 MISC:NEXT_CONFIG_ADDR[0]
B1 MISC:NEXT_CONFIG_ADDR[1]
B2 MISC:NEXT_CONFIG_ADDR[2]
B3 MISC:NEXT_CONFIG_ADDR[3]
B4 MISC:NEXT_CONFIG_ADDR[4]
B5 MISC:NEXT_CONFIG_ADDR[5]
B6 MISC:NEXT_CONFIG_ADDR[6]
B7 MISC:NEXT_CONFIG_ADDR[7]
B8 MISC:NEXT_CONFIG_ADDR[8]
B9 MISC:NEXT_CONFIG_ADDR[9]
B10 MISC:NEXT_CONFIG_ADDR[10]
B11 MISC:NEXT_CONFIG_ADDR[11]
B12 MISC:NEXT_CONFIG_ADDR[12]
B13 MISC:NEXT_CONFIG_ADDR[13]
B14 MISC:NEXT_CONFIG_ADDR[14]
B15 MISC:NEXT_CONFIG_ADDR[15]
spartan6 REG.GENERAL12 rect R1
BitFrame
F0
B0 MISC:NEXT_CONFIG_ADDR[16]
B1 MISC:NEXT_CONFIG_ADDR[17]
B2 MISC:NEXT_CONFIG_ADDR[18]
B3 MISC:NEXT_CONFIG_ADDR[19]
B4 MISC:NEXT_CONFIG_ADDR[20]
B5 MISC:NEXT_CONFIG_ADDR[21]
B6 MISC:NEXT_CONFIG_ADDR[22]
B7 MISC:NEXT_CONFIG_ADDR[23]
B8 MISC:NEXT_CONFIG_ADDR[24]
B9 MISC:NEXT_CONFIG_ADDR[25]
B10 MISC:NEXT_CONFIG_ADDR[26]
B11 MISC:NEXT_CONFIG_ADDR[27]
B12 MISC:NEXT_CONFIG_ADDR[28]
B13 MISC:NEXT_CONFIG_ADDR[29]
B14 MISC:NEXT_CONFIG_ADDR[30]
B15 MISC:NEXT_CONFIG_ADDR[31]
MISC:NEXT_CONFIG_ADDR 1.F0.B15 1.F0.B14 1.F0.B13 1.F0.B12 1.F0.B11 1.F0.B10 1.F0.B9 1.F0.B8 1.F0.B7 1.F0.B6 1.F0.B5 1.F0.B4 1.F0.B3 1.F0.B2 1.F0.B1 1.F0.B0 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

GENERAL[34]

spartan6 REG.GENERAL34 rect R0
BitFrame
F0
B0 MISC:GOLDEN_CONFIG_ADDR[0]
B1 MISC:GOLDEN_CONFIG_ADDR[1]
B2 MISC:GOLDEN_CONFIG_ADDR[2]
B3 MISC:GOLDEN_CONFIG_ADDR[3]
B4 MISC:GOLDEN_CONFIG_ADDR[4]
B5 MISC:GOLDEN_CONFIG_ADDR[5]
B6 MISC:GOLDEN_CONFIG_ADDR[6]
B7 MISC:GOLDEN_CONFIG_ADDR[7]
B8 MISC:GOLDEN_CONFIG_ADDR[8]
B9 MISC:GOLDEN_CONFIG_ADDR[9]
B10 MISC:GOLDEN_CONFIG_ADDR[10]
B11 MISC:GOLDEN_CONFIG_ADDR[11]
B12 MISC:GOLDEN_CONFIG_ADDR[12]
B13 MISC:GOLDEN_CONFIG_ADDR[13]
B14 MISC:GOLDEN_CONFIG_ADDR[14]
B15 MISC:GOLDEN_CONFIG_ADDR[15]
spartan6 REG.GENERAL34 rect R1
BitFrame
F0
B0 MISC:GOLDEN_CONFIG_ADDR[16]
B1 MISC:GOLDEN_CONFIG_ADDR[17]
B2 MISC:GOLDEN_CONFIG_ADDR[18]
B3 MISC:GOLDEN_CONFIG_ADDR[19]
B4 MISC:GOLDEN_CONFIG_ADDR[20]
B5 MISC:GOLDEN_CONFIG_ADDR[21]
B6 MISC:GOLDEN_CONFIG_ADDR[22]
B7 MISC:GOLDEN_CONFIG_ADDR[23]
B8 MISC:GOLDEN_CONFIG_ADDR[24]
B9 MISC:GOLDEN_CONFIG_ADDR[25]
B10 MISC:GOLDEN_CONFIG_ADDR[26]
B11 MISC:GOLDEN_CONFIG_ADDR[27]
B12 MISC:GOLDEN_CONFIG_ADDR[28]
B13 MISC:GOLDEN_CONFIG_ADDR[29]
B14 MISC:GOLDEN_CONFIG_ADDR[30]
B15 MISC:GOLDEN_CONFIG_ADDR[31]
MISC:GOLDEN_CONFIG_ADDR 1.F0.B15 1.F0.B14 1.F0.B13 1.F0.B12 1.F0.B11 1.F0.B10 1.F0.B9 1.F0.B8 1.F0.B7 1.F0.B6 1.F0.B5 1.F0.B4 1.F0.B3 1.F0.B2 1.F0.B1 1.F0.B0 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

GENERAL5

spartan6 REG.GENERAL5 rect R0
BitFrame
F0
B0 MISC:FAILSAFE_USER[0]
B1 MISC:FAILSAFE_USER[1]
B2 MISC:FAILSAFE_USER[2]
B3 MISC:FAILSAFE_USER[3]
B4 MISC:FAILSAFE_USER[4]
B5 MISC:FAILSAFE_USER[5]
B6 MISC:FAILSAFE_USER[6]
B7 MISC:FAILSAFE_USER[7]
B8 MISC:FAILSAFE_USER[8]
B9 MISC:FAILSAFE_USER[9]
B10 MISC:FAILSAFE_USER[10]
B11 MISC:FAILSAFE_USER[11]
B12 MISC:FAILSAFE_USER[12]
B13 MISC:FAILSAFE_USER[13]
B14 MISC:FAILSAFE_USER[14]
B15 MISC:FAILSAFE_USER[15]
MISC:FAILSAFE_USER 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

TIMER

spartan6 REG.TIMER rect R0
BitFrame
F0
B0 MISC:TIMER_CFG[0]
B1 MISC:TIMER_CFG[1]
B2 MISC:TIMER_CFG[2]
B3 MISC:TIMER_CFG[3]
B4 MISC:TIMER_CFG[4]
B5 MISC:TIMER_CFG[5]
B6 MISC:TIMER_CFG[6]
B7 MISC:TIMER_CFG[7]
B8 MISC:TIMER_CFG[8]
B9 MISC:TIMER_CFG[9]
B10 MISC:TIMER_CFG[10]
B11 MISC:TIMER_CFG[11]
B12 MISC:TIMER_CFG[12]
B13 MISC:TIMER_CFG[13]
B14 MISC:TIMER_CFG[14]
B15 MISC:TIMER_CFG[15]
MISC:TIMER_CFG 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

SEU_OPT

spartan6 REG.SEU_OPT rect R0
BitFrame
F0
B0 MISC:POST_CRC_EN
B1 MISC:GLUTMASK
B2 -
B3 MISC:POST_CRC_KEEP
B4 MISC:POST_CRC_FREQ[0]
B5 MISC:POST_CRC_FREQ[1]
B6 MISC:POST_CRC_FREQ[2]
B7 MISC:POST_CRC_FREQ[3]
B8 MISC:POST_CRC_FREQ[4]
B9 MISC:POST_CRC_FREQ[5]
B10 MISC:POST_CRC_FREQ[6]
B11 MISC:POST_CRC_FREQ[7]
B12 MISC:POST_CRC_FREQ[8]
B13 MISC:POST_CRC_FREQ[9]
B14 MISC:POST_CRC_ONESHOT
B15 ~MISC:POST_CRC_SEL
MISC:GLUTMASK 0.F0.B1
MISC:POST_CRC_EN 0.F0.B0
MISC:POST_CRC_KEEP 0.F0.B3
MISC:POST_CRC_ONESHOT 0.F0.B14
non-inverted [0]
MISC:POST_CRC_FREQ 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:POST_CRC_SEL 0.F0.B15
inverted ~[0]

TESTMODE

spartan6 REG.TESTMODE rect R0
BitFrame
F0
B0 MISC:VGG_TEST
B1 MISC:ICAP_BYPASS
B2 MISC:TESTMODE_EN
MISC:ICAP_BYPASS 0.F0.B1
MISC:TESTMODE_EN 0.F0.B2
MISC:VGG_TEST 0.F0.B0
non-inverted [0]