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Configuration registers

TODO: document

Tile GLOBAL

Cells: 0

Bels GLOBAL

spartan6 GLOBAL bel GLOBAL pins
PinDirectionGLOBAL
spartan6 GLOBAL bel GLOBAL attribute bits
AttributeGLOBAL
GWE_CYCLE[enum: STARTUP_CYCLE]
GTS_CYCLE[enum: STARTUP_CYCLE]
LOCK_CYCLE[enum: STARTUP_CYCLE]
DONE_CYCLE[enum: STARTUP_CYCLE]
BPI_DIV8COR2[0][13]
BPI_DIV16COR2[0][14]
RESET_ON_ERRCOR2[0][15]
DISABLE_VRD_REGCOR2[0][12]
DRIVE_DONECOR1[0][2]
DONE_PIPECOR1[0][3]
DRIVE_AWAKECOR1[0][15]
CRC_ENABLE!COR1[0][4]
VRDSEL bit 0COR1[0][5]
VRDSEL bit 1COR1[0][6]
VRDSEL bit 2COR1[0][7]
SEND_VGG bit 0COR1[0][8]
SEND_VGG bit 1COR1[0][9]
SEND_VGG bit 2COR1[0][10]
SEND_VGG bit 3COR1[0][11]
VGG_ENABLE_OFFCHIP!COR1[0][13]
VGG_SENDMAX!COR1[0][12]
STARTUP_CLOCK[enum: STARTUP_CLOCK]
GTS_USR_BCTL[0][0]
POST_CRC_INIT_FLAG!CTL[0][1]
MULTIBOOT_ENABLECTL[0][7]
SECURITY[enum: SECURITY]
PERSISTCTL[0][3]
ENCRYPTCTL[0][6]
ENCRYPT_KEY_SELECT[enum: ENCRYPT_KEY_SELECT]
CONFIG_RATE_DIV bit 0CCLK_FREQ[0][0]
CONFIG_RATE_DIV bit 1!CCLK_FREQ[0][1]
CONFIG_RATE_DIV bit 2!CCLK_FREQ[0][2]
CONFIG_RATE_DIV bit 3CCLK_FREQ[0][3]
CONFIG_RATE_DIV bit 4CCLK_FREQ[0][4]
CONFIG_RATE_DIV bit 5CCLK_FREQ[0][5]
CONFIG_RATE_DIV bit 6CCLK_FREQ[0][6]
CONFIG_RATE_DIV bit 7CCLK_FREQ[0][7]
CONFIG_RATE_DIV bit 8CCLK_FREQ[0][8]
CONFIG_RATE_DIV bit 9CCLK_FREQ[0][9]
CCLK_DLY bit 0CCLK_FREQ[0][10]
CCLK_DLY bit 1CCLK_FREQ[0][11]
CCLK_SEP bit 0CCLK_FREQ[0][12]
CCLK_SEP bit 1CCLK_FREQ[0][13]
EXT_CCLK_ENABLECCLK_FREQ[0][14]
HC_CYCLE bit 0HC_OPT[0][0]
HC_CYCLE bit 1HC_OPT[0][1]
HC_CYCLE bit 2HC_OPT[0][2]
HC_CYCLE bit 3HC_OPT[0][3]
TWO_ROUNDHC_OPT[0][4]
BRAM_SKIPHC_OPT[0][5]
INIT_SKIPCOR1[0][6]
SW_CLK[enum: SW_CLK]
EN_SUSPENDPOWERDOWN[0][2]
EN_SW_GSRPOWERDOWN[0][4]
SUSPEND_FILTER!POWERDOWN[0][5]
MULTIPIN_WAKEUPPOWERDOWN[0][14]
WAKE_DELAY1 bit 0POWERDOWN[0][6]
WAKE_DELAY1 bit 1POWERDOWN[0][7]
WAKE_DELAY1 bit 2POWERDOWN[0][8]
WAKE_DELAY2 bit 0POWERDOWN[0][9]
WAKE_DELAY2 bit 1POWERDOWN[0][10]
WAKE_DELAY2 bit 2POWERDOWN[0][11]
WAKE_DELAY2 bit 3POWERDOWN[0][12]
WAKE_DELAY2 bit 4POWERDOWN[0][13]
SW_GWE_CYCLE bit 0PU_GWE[0][0]
SW_GWE_CYCLE bit 1PU_GWE[0][1]
SW_GWE_CYCLE bit 2PU_GWE[0][2]
SW_GWE_CYCLE bit 3PU_GWE[0][3]
SW_GWE_CYCLE bit 4PU_GWE[0][4]
SW_GWE_CYCLE bit 5PU_GWE[0][5]
SW_GWE_CYCLE bit 6PU_GWE[0][6]
SW_GWE_CYCLE bit 7PU_GWE[0][7]
SW_GWE_CYCLE bit 8PU_GWE[0][8]
SW_GWE_CYCLE bit 9PU_GWE[0][9]
SW_GTS_CYCLE bit 0PU_GTS[0][0]
SW_GTS_CYCLE bit 1PU_GTS[0][1]
SW_GTS_CYCLE bit 2PU_GTS[0][2]
SW_GTS_CYCLE bit 3PU_GTS[0][3]
SW_GTS_CYCLE bit 4PU_GTS[0][4]
SW_GTS_CYCLE bit 5PU_GTS[0][5]
SW_GTS_CYCLE bit 6PU_GTS[0][6]
SW_GTS_CYCLE bit 7PU_GTS[0][7]
SW_GTS_CYCLE bit 8PU_GTS[0][8]
SW_GTS_CYCLE bit 9PU_GTS[0][9]
WAKEUP_MASK bit 0EYE_MASK[0][0]
WAKEUP_MASK bit 1EYE_MASK[0][1]
WAKEUP_MASK bit 2EYE_MASK[0][2]
WAKEUP_MASK bit 3EYE_MASK[0][3]
WAKEUP_MASK bit 4EYE_MASK[0][4]
WAKEUP_MASK bit 5EYE_MASK[0][5]
WAKEUP_MASK bit 6EYE_MASK[0][6]
WAKEUP_MASK bit 7EYE_MASK[0][7]
NEXT_CONFIG_BOOT_MODE bit 0MODE[0][8]
NEXT_CONFIG_BOOT_MODE bit 1MODE[0][9]
NEXT_CONFIG_BOOT_MODE bit 2MODE[0][10]
NEXT_CONFIG_NEW_MODEMODE[0][13]
SPI_BUSWIDTH[enum: SPI_BUSWIDTH]
NEXT_CONFIG_ADDR bit 0GENERAL1[0][0]
NEXT_CONFIG_ADDR bit 1GENERAL1[0][1]
NEXT_CONFIG_ADDR bit 2GENERAL1[0][2]
NEXT_CONFIG_ADDR bit 3GENERAL1[0][3]
NEXT_CONFIG_ADDR bit 4GENERAL1[0][4]
NEXT_CONFIG_ADDR bit 5GENERAL1[0][5]
NEXT_CONFIG_ADDR bit 6GENERAL1[0][6]
NEXT_CONFIG_ADDR bit 7GENERAL1[0][7]
NEXT_CONFIG_ADDR bit 8GENERAL1[0][8]
NEXT_CONFIG_ADDR bit 9GENERAL1[0][9]
NEXT_CONFIG_ADDR bit 10GENERAL1[0][10]
NEXT_CONFIG_ADDR bit 11GENERAL1[0][11]
NEXT_CONFIG_ADDR bit 12GENERAL1[0][12]
NEXT_CONFIG_ADDR bit 13GENERAL1[0][13]
NEXT_CONFIG_ADDR bit 14GENERAL1[0][14]
NEXT_CONFIG_ADDR bit 15GENERAL1[0][15]
NEXT_CONFIG_ADDR bit 16GENERAL2[0][0]
NEXT_CONFIG_ADDR bit 17GENERAL2[0][1]
NEXT_CONFIG_ADDR bit 18GENERAL2[0][2]
NEXT_CONFIG_ADDR bit 19GENERAL2[0][3]
NEXT_CONFIG_ADDR bit 20GENERAL2[0][4]
NEXT_CONFIG_ADDR bit 21GENERAL2[0][5]
NEXT_CONFIG_ADDR bit 22GENERAL2[0][6]
NEXT_CONFIG_ADDR bit 23GENERAL2[0][7]
NEXT_CONFIG_ADDR bit 24GENERAL2[0][8]
NEXT_CONFIG_ADDR bit 25GENERAL2[0][9]
NEXT_CONFIG_ADDR bit 26GENERAL2[0][10]
NEXT_CONFIG_ADDR bit 27GENERAL2[0][11]
NEXT_CONFIG_ADDR bit 28GENERAL2[0][12]
NEXT_CONFIG_ADDR bit 29GENERAL2[0][13]
NEXT_CONFIG_ADDR bit 30GENERAL2[0][14]
NEXT_CONFIG_ADDR bit 31GENERAL2[0][15]
GOLDEN_CONFIG_ADDR bit 0GENERAL3[0][0]
GOLDEN_CONFIG_ADDR bit 1GENERAL3[0][1]
GOLDEN_CONFIG_ADDR bit 2GENERAL3[0][2]
GOLDEN_CONFIG_ADDR bit 3GENERAL3[0][3]
GOLDEN_CONFIG_ADDR bit 4GENERAL3[0][4]
GOLDEN_CONFIG_ADDR bit 5GENERAL3[0][5]
GOLDEN_CONFIG_ADDR bit 6GENERAL3[0][6]
GOLDEN_CONFIG_ADDR bit 7GENERAL3[0][7]
GOLDEN_CONFIG_ADDR bit 8GENERAL3[0][8]
GOLDEN_CONFIG_ADDR bit 9GENERAL3[0][9]
GOLDEN_CONFIG_ADDR bit 10GENERAL3[0][10]
GOLDEN_CONFIG_ADDR bit 11GENERAL3[0][11]
GOLDEN_CONFIG_ADDR bit 12GENERAL3[0][12]
GOLDEN_CONFIG_ADDR bit 13GENERAL3[0][13]
GOLDEN_CONFIG_ADDR bit 14GENERAL3[0][14]
GOLDEN_CONFIG_ADDR bit 15GENERAL3[0][15]
GOLDEN_CONFIG_ADDR bit 16GENERAL4[0][0]
GOLDEN_CONFIG_ADDR bit 17GENERAL4[0][1]
GOLDEN_CONFIG_ADDR bit 18GENERAL4[0][2]
GOLDEN_CONFIG_ADDR bit 19GENERAL4[0][3]
GOLDEN_CONFIG_ADDR bit 20GENERAL4[0][4]
GOLDEN_CONFIG_ADDR bit 21GENERAL4[0][5]
GOLDEN_CONFIG_ADDR bit 22GENERAL4[0][6]
GOLDEN_CONFIG_ADDR bit 23GENERAL4[0][7]
GOLDEN_CONFIG_ADDR bit 24GENERAL4[0][8]
GOLDEN_CONFIG_ADDR bit 25GENERAL4[0][9]
GOLDEN_CONFIG_ADDR bit 26GENERAL4[0][10]
GOLDEN_CONFIG_ADDR bit 27GENERAL4[0][11]
GOLDEN_CONFIG_ADDR bit 28GENERAL4[0][12]
GOLDEN_CONFIG_ADDR bit 29GENERAL4[0][13]
GOLDEN_CONFIG_ADDR bit 30GENERAL4[0][14]
GOLDEN_CONFIG_ADDR bit 31GENERAL4[0][15]
FAILSAFE_USER bit 0GENERAL5[0][0]
FAILSAFE_USER bit 1GENERAL5[0][1]
FAILSAFE_USER bit 2GENERAL5[0][2]
FAILSAFE_USER bit 3GENERAL5[0][3]
FAILSAFE_USER bit 4GENERAL5[0][4]
FAILSAFE_USER bit 5GENERAL5[0][5]
FAILSAFE_USER bit 6GENERAL5[0][6]
FAILSAFE_USER bit 7GENERAL5[0][7]
FAILSAFE_USER bit 8GENERAL5[0][8]
FAILSAFE_USER bit 9GENERAL5[0][9]
FAILSAFE_USER bit 10GENERAL5[0][10]
FAILSAFE_USER bit 11GENERAL5[0][11]
FAILSAFE_USER bit 12GENERAL5[0][12]
FAILSAFE_USER bit 13GENERAL5[0][13]
FAILSAFE_USER bit 14GENERAL5[0][14]
FAILSAFE_USER bit 15GENERAL5[0][15]
TIMER_CFG bit 0TIMER[0][0]
TIMER_CFG bit 1TIMER[0][1]
TIMER_CFG bit 2TIMER[0][2]
TIMER_CFG bit 3TIMER[0][3]
TIMER_CFG bit 4TIMER[0][4]
TIMER_CFG bit 5TIMER[0][5]
TIMER_CFG bit 6TIMER[0][6]
TIMER_CFG bit 7TIMER[0][7]
TIMER_CFG bit 8TIMER[0][8]
TIMER_CFG bit 9TIMER[0][9]
TIMER_CFG bit 10TIMER[0][10]
TIMER_CFG bit 11TIMER[0][11]
TIMER_CFG bit 12TIMER[0][12]
TIMER_CFG bit 13TIMER[0][13]
TIMER_CFG bit 14TIMER[0][14]
TIMER_CFG bit 15TIMER[0][15]
POST_CRC_ENSEU_OPT[0][0]
GLUTMASKSEU_OPT[0][1]
POST_CRC_KEEPSEU_OPT[0][3]
POST_CRC_ONESHOTSEU_OPT[0][14]
POST_CRC_SEL!SEU_OPT[0][15]
POST_CRC_FREQ_DIV bit 0SEU_OPT[0][4]
POST_CRC_FREQ_DIV bit 1SEU_OPT[0][5]
POST_CRC_FREQ_DIV bit 2SEU_OPT[0][6]
POST_CRC_FREQ_DIV bit 3SEU_OPT[0][7]
POST_CRC_FREQ_DIV bit 4SEU_OPT[0][8]
POST_CRC_FREQ_DIV bit 5SEU_OPT[0][9]
POST_CRC_FREQ_DIV bit 6SEU_OPT[0][10]
POST_CRC_FREQ_DIV bit 7SEU_OPT[0][11]
POST_CRC_FREQ_DIV bit 8SEU_OPT[0][12]
POST_CRC_FREQ_DIV bit 9SEU_OPT[0][13]
VGG_TESTTESTMODE[0][0]
ICAP_BYPASSTESTMODE[0][1]
TESTMODE_ENTESTMODE[0][2]
spartan6 GLOBAL enum STARTUP_CYCLE
GLOBAL.GWE_CYCLECOR2[0][2]COR2[0][1]COR2[0][0]
GLOBAL.GTS_CYCLECOR2[0][5]COR2[0][4]COR2[0][3]
_1001
_2010
_3011
_4100
_5101
_6110
DONE111
KEEP000
spartan6 GLOBAL enum STARTUP_CYCLE
GLOBAL.LOCK_CYCLECOR2[0][8]COR2[0][7]COR2[0][6]
_1001
_2010
_3011
_4100
_5101
_6110
NOWAIT111
spartan6 GLOBAL enum STARTUP_CYCLE
GLOBAL.DONE_CYCLECOR2[0][11]COR2[0][10]COR2[0][9]
_1001
_2010
_3011
_4100
_5101
_6110
spartan6 GLOBAL enum STARTUP_CLOCK
GLOBAL.STARTUP_CLOCKCOR1[0][1]COR1[0][0]
CCLK00
USERCLK01
JTAGCLK10
spartan6 GLOBAL enum SECURITY
GLOBAL.SECURITYCTL[0][5]CTL[0][4]
NONE00
LEVEL101
LEVEL210
LEVEL311
spartan6 GLOBAL enum ENCRYPT_KEY_SELECT
GLOBAL.ENCRYPT_KEY_SELECTCTL[0][2]
BBRAM0
EFUSE1
spartan6 GLOBAL enum SW_CLK
GLOBAL.SW_CLKPOWERDOWN[0][0]
INTERNALCLK0
STARTUPCLK1
spartan6 GLOBAL enum SPI_BUSWIDTH
GLOBAL.SPI_BUSWIDTHCOR1[0][12]COR1[0][11]
_100
_201
_410

Bitstream

spartan6 GLOBAL rect COR1
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: DRIVE_AWAKE - GLOBAL: ! VGG_ENABLE_OFFCHIP GLOBAL: ! VGG_SENDMAX GLOBAL: SPI_BUSWIDTH bit 1 GLOBAL: SEND_VGG bit 3 GLOBAL: SPI_BUSWIDTH bit 0 GLOBAL: SEND_VGG bit 2 GLOBAL: SEND_VGG bit 1 GLOBAL: SEND_VGG bit 0 GLOBAL: VRDSEL bit 2 GLOBAL: VRDSEL bit 1 GLOBAL: INIT_SKIP GLOBAL: VRDSEL bit 0 GLOBAL: ! CRC_ENABLE GLOBAL: DONE_PIPE GLOBAL: DRIVE_DONE GLOBAL: STARTUP_CLOCK bit 1 GLOBAL: STARTUP_CLOCK bit 0
spartan6 GLOBAL rect COR2
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: RESET_ON_ERR GLOBAL: BPI_DIV16 GLOBAL: BPI_DIV8 GLOBAL: DISABLE_VRD_REG GLOBAL: DONE_CYCLE bit 2 GLOBAL: DONE_CYCLE bit 1 GLOBAL: DONE_CYCLE bit 0 GLOBAL: LOCK_CYCLE bit 2 GLOBAL: LOCK_CYCLE bit 1 GLOBAL: LOCK_CYCLE bit 0 GLOBAL: GTS_CYCLE bit 2 GLOBAL: GTS_CYCLE bit 1 GLOBAL: GTS_CYCLE bit 0 GLOBAL: GWE_CYCLE bit 2 GLOBAL: GWE_CYCLE bit 1 GLOBAL: GWE_CYCLE bit 0
spartan6 GLOBAL rect CTL
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - GLOBAL: MULTIBOOT_ENABLE GLOBAL: ENCRYPT GLOBAL: SECURITY bit 1 GLOBAL: SECURITY bit 0 GLOBAL: PERSIST GLOBAL: ENCRYPT_KEY_SELECT bit 0 GLOBAL: ! POST_CRC_INIT_FLAG GLOBAL: GTS_USR_B
spartan6 GLOBAL rect CCLK_FREQ
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - GLOBAL: EXT_CCLK_ENABLE GLOBAL: CCLK_SEP bit 1 GLOBAL: CCLK_SEP bit 0 GLOBAL: CCLK_DLY bit 1 GLOBAL: CCLK_DLY bit 0 GLOBAL: CONFIG_RATE_DIV bit 9 GLOBAL: CONFIG_RATE_DIV bit 8 GLOBAL: CONFIG_RATE_DIV bit 7 GLOBAL: CONFIG_RATE_DIV bit 6 GLOBAL: CONFIG_RATE_DIV bit 5 GLOBAL: CONFIG_RATE_DIV bit 4 GLOBAL: CONFIG_RATE_DIV bit 3 GLOBAL: ! CONFIG_RATE_DIV bit 2 GLOBAL: ! CONFIG_RATE_DIV bit 1 GLOBAL: CONFIG_RATE_DIV bit 0
spartan6 GLOBAL rect HC_OPT
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - GLOBAL: BRAM_SKIP GLOBAL: TWO_ROUND GLOBAL: HC_CYCLE bit 3 GLOBAL: HC_CYCLE bit 2 GLOBAL: HC_CYCLE bit 1 GLOBAL: HC_CYCLE bit 0
spartan6 GLOBAL rect POWERDOWN
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - GLOBAL: MULTIPIN_WAKEUP GLOBAL: WAKE_DELAY2 bit 4 GLOBAL: WAKE_DELAY2 bit 3 GLOBAL: WAKE_DELAY2 bit 2 GLOBAL: WAKE_DELAY2 bit 1 GLOBAL: WAKE_DELAY2 bit 0 GLOBAL: WAKE_DELAY1 bit 2 GLOBAL: WAKE_DELAY1 bit 1 GLOBAL: WAKE_DELAY1 bit 0 GLOBAL: ! SUSPEND_FILTER GLOBAL: EN_SW_GSR - GLOBAL: EN_SUSPEND - GLOBAL: SW_CLK bit 0
spartan6 GLOBAL rect PU_GWE
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - GLOBAL: SW_GWE_CYCLE bit 9 GLOBAL: SW_GWE_CYCLE bit 8 GLOBAL: SW_GWE_CYCLE bit 7 GLOBAL: SW_GWE_CYCLE bit 6 GLOBAL: SW_GWE_CYCLE bit 5 GLOBAL: SW_GWE_CYCLE bit 4 GLOBAL: SW_GWE_CYCLE bit 3 GLOBAL: SW_GWE_CYCLE bit 2 GLOBAL: SW_GWE_CYCLE bit 1 GLOBAL: SW_GWE_CYCLE bit 0
spartan6 GLOBAL rect PU_GTS
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - GLOBAL: SW_GTS_CYCLE bit 9 GLOBAL: SW_GTS_CYCLE bit 8 GLOBAL: SW_GTS_CYCLE bit 7 GLOBAL: SW_GTS_CYCLE bit 6 GLOBAL: SW_GTS_CYCLE bit 5 GLOBAL: SW_GTS_CYCLE bit 4 GLOBAL: SW_GTS_CYCLE bit 3 GLOBAL: SW_GTS_CYCLE bit 2 GLOBAL: SW_GTS_CYCLE bit 1 GLOBAL: SW_GTS_CYCLE bit 0
spartan6 GLOBAL rect MODE
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - GLOBAL: NEXT_CONFIG_NEW_MODE - - GLOBAL: NEXT_CONFIG_BOOT_MODE bit 2 GLOBAL: NEXT_CONFIG_BOOT_MODE bit 1 GLOBAL: NEXT_CONFIG_BOOT_MODE bit 0 - - - - - - - -
spartan6 GLOBAL rect GENERAL1
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: NEXT_CONFIG_ADDR bit 15 GLOBAL: NEXT_CONFIG_ADDR bit 14 GLOBAL: NEXT_CONFIG_ADDR bit 13 GLOBAL: NEXT_CONFIG_ADDR bit 12 GLOBAL: NEXT_CONFIG_ADDR bit 11 GLOBAL: NEXT_CONFIG_ADDR bit 10 GLOBAL: NEXT_CONFIG_ADDR bit 9 GLOBAL: NEXT_CONFIG_ADDR bit 8 GLOBAL: NEXT_CONFIG_ADDR bit 7 GLOBAL: NEXT_CONFIG_ADDR bit 6 GLOBAL: NEXT_CONFIG_ADDR bit 5 GLOBAL: NEXT_CONFIG_ADDR bit 4 GLOBAL: NEXT_CONFIG_ADDR bit 3 GLOBAL: NEXT_CONFIG_ADDR bit 2 GLOBAL: NEXT_CONFIG_ADDR bit 1 GLOBAL: NEXT_CONFIG_ADDR bit 0
spartan6 GLOBAL rect GENERAL2
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: NEXT_CONFIG_ADDR bit 31 GLOBAL: NEXT_CONFIG_ADDR bit 30 GLOBAL: NEXT_CONFIG_ADDR bit 29 GLOBAL: NEXT_CONFIG_ADDR bit 28 GLOBAL: NEXT_CONFIG_ADDR bit 27 GLOBAL: NEXT_CONFIG_ADDR bit 26 GLOBAL: NEXT_CONFIG_ADDR bit 25 GLOBAL: NEXT_CONFIG_ADDR bit 24 GLOBAL: NEXT_CONFIG_ADDR bit 23 GLOBAL: NEXT_CONFIG_ADDR bit 22 GLOBAL: NEXT_CONFIG_ADDR bit 21 GLOBAL: NEXT_CONFIG_ADDR bit 20 GLOBAL: NEXT_CONFIG_ADDR bit 19 GLOBAL: NEXT_CONFIG_ADDR bit 18 GLOBAL: NEXT_CONFIG_ADDR bit 17 GLOBAL: NEXT_CONFIG_ADDR bit 16
spartan6 GLOBAL rect GENERAL3
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: GOLDEN_CONFIG_ADDR bit 15 GLOBAL: GOLDEN_CONFIG_ADDR bit 14 GLOBAL: GOLDEN_CONFIG_ADDR bit 13 GLOBAL: GOLDEN_CONFIG_ADDR bit 12 GLOBAL: GOLDEN_CONFIG_ADDR bit 11 GLOBAL: GOLDEN_CONFIG_ADDR bit 10 GLOBAL: GOLDEN_CONFIG_ADDR bit 9 GLOBAL: GOLDEN_CONFIG_ADDR bit 8 GLOBAL: GOLDEN_CONFIG_ADDR bit 7 GLOBAL: GOLDEN_CONFIG_ADDR bit 6 GLOBAL: GOLDEN_CONFIG_ADDR bit 5 GLOBAL: GOLDEN_CONFIG_ADDR bit 4 GLOBAL: GOLDEN_CONFIG_ADDR bit 3 GLOBAL: GOLDEN_CONFIG_ADDR bit 2 GLOBAL: GOLDEN_CONFIG_ADDR bit 1 GLOBAL: GOLDEN_CONFIG_ADDR bit 0
spartan6 GLOBAL rect GENERAL4
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: GOLDEN_CONFIG_ADDR bit 31 GLOBAL: GOLDEN_CONFIG_ADDR bit 30 GLOBAL: GOLDEN_CONFIG_ADDR bit 29 GLOBAL: GOLDEN_CONFIG_ADDR bit 28 GLOBAL: GOLDEN_CONFIG_ADDR bit 27 GLOBAL: GOLDEN_CONFIG_ADDR bit 26 GLOBAL: GOLDEN_CONFIG_ADDR bit 25 GLOBAL: GOLDEN_CONFIG_ADDR bit 24 GLOBAL: GOLDEN_CONFIG_ADDR bit 23 GLOBAL: GOLDEN_CONFIG_ADDR bit 22 GLOBAL: GOLDEN_CONFIG_ADDR bit 21 GLOBAL: GOLDEN_CONFIG_ADDR bit 20 GLOBAL: GOLDEN_CONFIG_ADDR bit 19 GLOBAL: GOLDEN_CONFIG_ADDR bit 18 GLOBAL: GOLDEN_CONFIG_ADDR bit 17 GLOBAL: GOLDEN_CONFIG_ADDR bit 16
spartan6 GLOBAL rect GENERAL5
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: FAILSAFE_USER bit 15 GLOBAL: FAILSAFE_USER bit 14 GLOBAL: FAILSAFE_USER bit 13 GLOBAL: FAILSAFE_USER bit 12 GLOBAL: FAILSAFE_USER bit 11 GLOBAL: FAILSAFE_USER bit 10 GLOBAL: FAILSAFE_USER bit 9 GLOBAL: FAILSAFE_USER bit 8 GLOBAL: FAILSAFE_USER bit 7 GLOBAL: FAILSAFE_USER bit 6 GLOBAL: FAILSAFE_USER bit 5 GLOBAL: FAILSAFE_USER bit 4 GLOBAL: FAILSAFE_USER bit 3 GLOBAL: FAILSAFE_USER bit 2 GLOBAL: FAILSAFE_USER bit 1 GLOBAL: FAILSAFE_USER bit 0
spartan6 GLOBAL rect SEU_OPT
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: ! POST_CRC_SEL GLOBAL: POST_CRC_ONESHOT GLOBAL: POST_CRC_FREQ_DIV bit 9 GLOBAL: POST_CRC_FREQ_DIV bit 8 GLOBAL: POST_CRC_FREQ_DIV bit 7 GLOBAL: POST_CRC_FREQ_DIV bit 6 GLOBAL: POST_CRC_FREQ_DIV bit 5 GLOBAL: POST_CRC_FREQ_DIV bit 4 GLOBAL: POST_CRC_FREQ_DIV bit 3 GLOBAL: POST_CRC_FREQ_DIV bit 2 GLOBAL: POST_CRC_FREQ_DIV bit 1 GLOBAL: POST_CRC_FREQ_DIV bit 0 GLOBAL: POST_CRC_KEEP - GLOBAL: GLUTMASK GLOBAL: POST_CRC_EN
spartan6 GLOBAL rect EYE_MASK
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - GLOBAL: WAKEUP_MASK bit 7 GLOBAL: WAKEUP_MASK bit 6 GLOBAL: WAKEUP_MASK bit 5 GLOBAL: WAKEUP_MASK bit 4 GLOBAL: WAKEUP_MASK bit 3 GLOBAL: WAKEUP_MASK bit 2 GLOBAL: WAKEUP_MASK bit 1 GLOBAL: WAKEUP_MASK bit 0
spartan6 GLOBAL rect TIMER
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 GLOBAL: TIMER_CFG bit 15 GLOBAL: TIMER_CFG bit 14 GLOBAL: TIMER_CFG bit 13 GLOBAL: TIMER_CFG bit 12 GLOBAL: TIMER_CFG bit 11 GLOBAL: TIMER_CFG bit 10 GLOBAL: TIMER_CFG bit 9 GLOBAL: TIMER_CFG bit 8 GLOBAL: TIMER_CFG bit 7 GLOBAL: TIMER_CFG bit 6 GLOBAL: TIMER_CFG bit 5 GLOBAL: TIMER_CFG bit 4 GLOBAL: TIMER_CFG bit 3 GLOBAL: TIMER_CFG bit 2 GLOBAL: TIMER_CFG bit 1 GLOBAL: TIMER_CFG bit 0
spartan6 GLOBAL rect TESTMODE
FrameBit
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - - - - GLOBAL: TESTMODE_EN GLOBAL: ICAP_BYPASS GLOBAL: VGG_TEST