Configuration registers

TODO: document

COR1

spartan6 REG.COR1 bittile 0
BitFrame
0
0 STARTUP:STARTUPCLK[0]
1 STARTUP:STARTUPCLK[1]
2 STARTUP:DRIVE_DONE
3 STARTUP:DONE_PIPE
4 ~STARTUP:CRC
5 STARTUP:VRDSEL[0]
6 STARTUP:VRDSEL[1]
7 STARTUP:VRDSEL[2]
8 MISC:SEND_VGG[0]
9 MISC:SEND_VGG[1]
10 MISC:SEND_VGG[2]
11 MISC:SEND_VGG[3]
12 ~MISC:VGG_SENDMAX
13 ~MISC:VGG_ENABLE_OFFCHIP
14 -
15 STARTUP:DRIVE_AWAKE
MISC:SEND_VGG 0.0.11 0.0.10 0.0.9 0.0.8
non-inverted [3] [2] [1] [0]
MISC:VGG_ENABLE_OFFCHIP 0.0.13
MISC:VGG_SENDMAX 0.0.12
STARTUP:CRC 0.0.4
inverted ~[0]
STARTUP:DONE_PIPE 0.0.3
STARTUP:DRIVE_AWAKE 0.0.15
STARTUP:DRIVE_DONE 0.0.2
non-inverted [0]
STARTUP:STARTUPCLK 0.0.1 0.0.0
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0
STARTUP:VRDSEL 0.0.7 0.0.6 0.0.5
non-inverted [2] [1] [0]

COR2

spartan6 REG.COR2 bittile 0
BitFrame
0
0 STARTUP:GWE_CYCLE[0]
1 STARTUP:GWE_CYCLE[1]
2 STARTUP:GWE_CYCLE[2]
3 STARTUP:GTS_CYCLE[0]
4 STARTUP:GTS_CYCLE[1]
5 STARTUP:GTS_CYCLE[2]
6 STARTUP:LCK_CYCLE[0]
7 STARTUP:LCK_CYCLE[1]
8 STARTUP:LCK_CYCLE[2]
9 STARTUP:DONE_CYCLE[0]
10 STARTUP:DONE_CYCLE[1]
11 STARTUP:DONE_CYCLE[2]
12 STARTUP:DISABLE_VRD_REG
13 STARTUP:BPI_DIV8
14 STARTUP:BPI_DIV16
15 STARTUP:RESET_ON_ERR
STARTUP:BPI_DIV16 0.0.14
STARTUP:BPI_DIV8 0.0.13
STARTUP:DISABLE_VRD_REG 0.0.12
STARTUP:RESET_ON_ERR 0.0.15
non-inverted [0]
STARTUP:DONE_CYCLE 0.0.11 0.0.10 0.0.9
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
STARTUP:GTS_CYCLE 0.0.5 0.0.4 0.0.3
STARTUP:GWE_CYCLE 0.0.2 0.0.1 0.0.0
KEEP 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
DONE 1 1 1
STARTUP:LCK_CYCLE 0.0.8 0.0.7 0.0.6
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1

CTL

spartan6 REG.CTL bittile 0
BitFrame
0
0 MISC:GTS_USR_B
1 ~MISC:POST_CRC_INIT_FLAG
2 MISC:ENCRYPT_KEY_SELECT[0]
3 MISC:PERSIST
4 MISC:SECURITY[0]
5 MISC:SECURITY[1]
6 MISC:ENCRYPT
7 MISC:MULTIBOOT_ENABLE
MISC:ENCRYPT 0.0.6
MISC:GTS_USR_B 0.0.0
MISC:MULTIBOOT_ENABLE 0.0.7
MISC:PERSIST 0.0.3
non-inverted [0]
MISC:ENCRYPT_KEY_SELECT 0.0.2
BBRAM 0
EFUSE 1
MISC:POST_CRC_INIT_FLAG 0.0.1
inverted ~[0]
MISC:SECURITY 0.0.5 0.0.4
NONE 0 0
LEVEL1 0 1
LEVEL2 1 0
LEVEL3 1 1

CCLK_FREQ

spartan6 REG.CCLK_FREQ bittile 0
BitFrame
0
0 STARTUP:CCLK_DIVISOR[0]
1 STARTUP:CCLK_DIVISOR[1]
2 STARTUP:CCLK_DIVISOR[2]
3 STARTUP:CCLK_DIVISOR[3]
4 STARTUP:CCLK_DIVISOR[4]
5 STARTUP:CCLK_DIVISOR[5]
6 STARTUP:CCLK_DIVISOR[6]
7 STARTUP:CCLK_DIVISOR[7]
8 STARTUP:CCLK_DIVISOR[8]
9 STARTUP:CCLK_DIVISOR[9]
10 STARTUP:CCLK_DLY[0]
11 STARTUP:CCLK_DLY[1]
12 STARTUP:CCLK_SEP[0]
13 STARTUP:CCLK_SEP[1]
14 STARTUP:EXT_CCLK_ENABLE
STARTUP:CCLK_DIVISOR 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
STARTUP:CCLK_DLY 0.0.11 0.0.10
STARTUP:CCLK_SEP 0.0.13 0.0.12
non-inverted [1] [0]
STARTUP:EXT_CCLK_ENABLE 0.0.14
non-inverted [0]

HC_OPT

spartan6 REG.HC_OPT bittile 0
BitFrame
0
0 MISC:HC_CYCLE[0]
1 MISC:HC_CYCLE[1]
2 MISC:HC_CYCLE[2]
3 MISC:HC_CYCLE[3]
4 MISC:TWO_ROUND
5 MISC:BRAM_SKIP
6 MISC:INIT_SKIP
MISC:BRAM_SKIP 0.0.5
MISC:INIT_SKIP 0.0.6
MISC:TWO_ROUND 0.0.4
non-inverted [0]
MISC:HC_CYCLE 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [3] [2] [1] [0]

POWERDOWN

spartan6 REG.POWERDOWN bittile 0
BitFrame
0
0 MISC:SW_CLK[0]
1 -
2 MISC:EN_SUSPEND
3 -
4 MISC:EN_SW_GSR
5 ~MISC:SUSPEND_FILTER
6 MISC:WAKE_DELAY1[0]
7 MISC:WAKE_DELAY1[1]
8 MISC:WAKE_DELAY1[2]
9 MISC:WAKE_DELAY2[0]
10 MISC:WAKE_DELAY2[1]
11 MISC:WAKE_DELAY2[2]
12 MISC:WAKE_DELAY2[3]
13 MISC:WAKE_DELAY2[4]
14 MISC:MULTIPIN_WAKEUP
MISC:EN_SUSPEND 0.0.2
MISC:EN_SW_GSR 0.0.4
MISC:MULTIPIN_WAKEUP 0.0.14
non-inverted [0]
MISC:SUSPEND_FILTER 0.0.5
inverted ~[0]
MISC:SW_CLK 0.0.0
INTERNALCLK 0
STARTUPCLK 1
MISC:WAKE_DELAY1 0.0.8 0.0.7 0.0.6
non-inverted [2] [1] [0]
MISC:WAKE_DELAY2 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9
non-inverted [4] [3] [2] [1] [0]

PU_GWE

spartan6 REG.PU_GWE bittile 0
BitFrame
0
0 MISC:SW_GWE_CYCLE[0]
1 MISC:SW_GWE_CYCLE[1]
2 MISC:SW_GWE_CYCLE[2]
3 MISC:SW_GWE_CYCLE[3]
4 MISC:SW_GWE_CYCLE[4]
5 MISC:SW_GWE_CYCLE[5]
6 MISC:SW_GWE_CYCLE[6]
7 MISC:SW_GWE_CYCLE[7]
8 MISC:SW_GWE_CYCLE[8]
9 MISC:SW_GWE_CYCLE[9]
MISC:SW_GWE_CYCLE 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

PU_GTS

spartan6 REG.PU_GTS bittile 0
BitFrame
0
0 MISC:SW_GTS_CYCLE[0]
1 MISC:SW_GTS_CYCLE[1]
2 MISC:SW_GTS_CYCLE[2]
3 MISC:SW_GTS_CYCLE[3]
4 MISC:SW_GTS_CYCLE[4]
5 MISC:SW_GTS_CYCLE[5]
6 MISC:SW_GTS_CYCLE[6]
7 MISC:SW_GTS_CYCLE[7]
8 MISC:SW_GTS_CYCLE[8]
9 MISC:SW_GTS_CYCLE[9]
MISC:SW_GTS_CYCLE 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

EYE_MASK

spartan6 REG.EYE_MASK bittile 0
BitFrame
0
0 MISC:WAKEUP_MASK[0]
1 MISC:WAKEUP_MASK[1]
2 MISC:WAKEUP_MASK[2]
3 MISC:WAKEUP_MASK[3]
4 MISC:WAKEUP_MASK[4]
5 MISC:WAKEUP_MASK[5]
6 MISC:WAKEUP_MASK[6]
7 MISC:WAKEUP_MASK[7]
MISC:WAKEUP_MASK 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]

MODE

spartan6 REG.MODE bittile 0
BitFrame
0
0 -
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8 MISC:NEXT_CONFIG_BOOT_MODE[0]
9 MISC:NEXT_CONFIG_BOOT_MODE[1]
10 MISC:NEXT_CONFIG_BOOT_MODE[2]
11 MISC:SPI_BUSWIDTH[0]
12 MISC:SPI_BUSWIDTH[1]
13 MISC:NEXT_CONFIG_NEW_MODE
MISC:NEXT_CONFIG_BOOT_MODE 0.0.10 0.0.9 0.0.8
non-inverted [2] [1] [0]
MISC:NEXT_CONFIG_NEW_MODE 0.0.13
non-inverted [0]
MISC:SPI_BUSWIDTH 0.0.12 0.0.11
1 0 0
2 0 1
4 1 0

GENERAL[12]

spartan6 REG.GENERAL12 bittile 0
BitFrame
0
0 MISC:NEXT_CONFIG_ADDR[0]
1 MISC:NEXT_CONFIG_ADDR[1]
2 MISC:NEXT_CONFIG_ADDR[2]
3 MISC:NEXT_CONFIG_ADDR[3]
4 MISC:NEXT_CONFIG_ADDR[4]
5 MISC:NEXT_CONFIG_ADDR[5]
6 MISC:NEXT_CONFIG_ADDR[6]
7 MISC:NEXT_CONFIG_ADDR[7]
8 MISC:NEXT_CONFIG_ADDR[8]
9 MISC:NEXT_CONFIG_ADDR[9]
10 MISC:NEXT_CONFIG_ADDR[10]
11 MISC:NEXT_CONFIG_ADDR[11]
12 MISC:NEXT_CONFIG_ADDR[12]
13 MISC:NEXT_CONFIG_ADDR[13]
14 MISC:NEXT_CONFIG_ADDR[14]
15 MISC:NEXT_CONFIG_ADDR[15]
spartan6 REG.GENERAL12 bittile 1
BitFrame
0
0 MISC:NEXT_CONFIG_ADDR[16]
1 MISC:NEXT_CONFIG_ADDR[17]
2 MISC:NEXT_CONFIG_ADDR[18]
3 MISC:NEXT_CONFIG_ADDR[19]
4 MISC:NEXT_CONFIG_ADDR[20]
5 MISC:NEXT_CONFIG_ADDR[21]
6 MISC:NEXT_CONFIG_ADDR[22]
7 MISC:NEXT_CONFIG_ADDR[23]
8 MISC:NEXT_CONFIG_ADDR[24]
9 MISC:NEXT_CONFIG_ADDR[25]
10 MISC:NEXT_CONFIG_ADDR[26]
11 MISC:NEXT_CONFIG_ADDR[27]
12 MISC:NEXT_CONFIG_ADDR[28]
13 MISC:NEXT_CONFIG_ADDR[29]
14 MISC:NEXT_CONFIG_ADDR[30]
15 MISC:NEXT_CONFIG_ADDR[31]
MISC:NEXT_CONFIG_ADDR 1.0.15 1.0.14 1.0.13 1.0.12 1.0.11 1.0.10 1.0.9 1.0.8 1.0.7 1.0.6 1.0.5 1.0.4 1.0.3 1.0.2 1.0.1 1.0.0 0.0.15 0.0.14 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

GENERAL[34]

spartan6 REG.GENERAL34 bittile 0
BitFrame
0
0 MISC:GOLDEN_CONFIG_ADDR[0]
1 MISC:GOLDEN_CONFIG_ADDR[1]
2 MISC:GOLDEN_CONFIG_ADDR[2]
3 MISC:GOLDEN_CONFIG_ADDR[3]
4 MISC:GOLDEN_CONFIG_ADDR[4]
5 MISC:GOLDEN_CONFIG_ADDR[5]
6 MISC:GOLDEN_CONFIG_ADDR[6]
7 MISC:GOLDEN_CONFIG_ADDR[7]
8 MISC:GOLDEN_CONFIG_ADDR[8]
9 MISC:GOLDEN_CONFIG_ADDR[9]
10 MISC:GOLDEN_CONFIG_ADDR[10]
11 MISC:GOLDEN_CONFIG_ADDR[11]
12 MISC:GOLDEN_CONFIG_ADDR[12]
13 MISC:GOLDEN_CONFIG_ADDR[13]
14 MISC:GOLDEN_CONFIG_ADDR[14]
15 MISC:GOLDEN_CONFIG_ADDR[15]
spartan6 REG.GENERAL34 bittile 1
BitFrame
0
0 MISC:GOLDEN_CONFIG_ADDR[16]
1 MISC:GOLDEN_CONFIG_ADDR[17]
2 MISC:GOLDEN_CONFIG_ADDR[18]
3 MISC:GOLDEN_CONFIG_ADDR[19]
4 MISC:GOLDEN_CONFIG_ADDR[20]
5 MISC:GOLDEN_CONFIG_ADDR[21]
6 MISC:GOLDEN_CONFIG_ADDR[22]
7 MISC:GOLDEN_CONFIG_ADDR[23]
8 MISC:GOLDEN_CONFIG_ADDR[24]
9 MISC:GOLDEN_CONFIG_ADDR[25]
10 MISC:GOLDEN_CONFIG_ADDR[26]
11 MISC:GOLDEN_CONFIG_ADDR[27]
12 MISC:GOLDEN_CONFIG_ADDR[28]
13 MISC:GOLDEN_CONFIG_ADDR[29]
14 MISC:GOLDEN_CONFIG_ADDR[30]
15 MISC:GOLDEN_CONFIG_ADDR[31]
MISC:GOLDEN_CONFIG_ADDR 1.0.15 1.0.14 1.0.13 1.0.12 1.0.11 1.0.10 1.0.9 1.0.8 1.0.7 1.0.6 1.0.5 1.0.4 1.0.3 1.0.2 1.0.1 1.0.0 0.0.15 0.0.14 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

GENERAL5

spartan6 REG.GENERAL5 bittile 0
BitFrame
0
0 MISC:FAILSAFE_USER[0]
1 MISC:FAILSAFE_USER[1]
2 MISC:FAILSAFE_USER[2]
3 MISC:FAILSAFE_USER[3]
4 MISC:FAILSAFE_USER[4]
5 MISC:FAILSAFE_USER[5]
6 MISC:FAILSAFE_USER[6]
7 MISC:FAILSAFE_USER[7]
8 MISC:FAILSAFE_USER[8]
9 MISC:FAILSAFE_USER[9]
10 MISC:FAILSAFE_USER[10]
11 MISC:FAILSAFE_USER[11]
12 MISC:FAILSAFE_USER[12]
13 MISC:FAILSAFE_USER[13]
14 MISC:FAILSAFE_USER[14]
15 MISC:FAILSAFE_USER[15]
MISC:FAILSAFE_USER 0.0.15 0.0.14 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

TIMER

spartan6 REG.TIMER bittile 0
BitFrame
0
0 MISC:TIMER_CFG[0]
1 MISC:TIMER_CFG[1]
2 MISC:TIMER_CFG[2]
3 MISC:TIMER_CFG[3]
4 MISC:TIMER_CFG[4]
5 MISC:TIMER_CFG[5]
6 MISC:TIMER_CFG[6]
7 MISC:TIMER_CFG[7]
8 MISC:TIMER_CFG[8]
9 MISC:TIMER_CFG[9]
10 MISC:TIMER_CFG[10]
11 MISC:TIMER_CFG[11]
12 MISC:TIMER_CFG[12]
13 MISC:TIMER_CFG[13]
14 MISC:TIMER_CFG[14]
15 MISC:TIMER_CFG[15]
MISC:TIMER_CFG 0.0.15 0.0.14 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4 0.0.3 0.0.2 0.0.1 0.0.0
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

SEU_OPT

spartan6 REG.SEU_OPT bittile 0
BitFrame
0
0 MISC:POST_CRC_EN
1 MISC:GLUTMASK
2 -
3 MISC:POST_CRC_KEEP
4 MISC:POST_CRC_FREQ[0]
5 MISC:POST_CRC_FREQ[1]
6 MISC:POST_CRC_FREQ[2]
7 MISC:POST_CRC_FREQ[3]
8 MISC:POST_CRC_FREQ[4]
9 MISC:POST_CRC_FREQ[5]
10 MISC:POST_CRC_FREQ[6]
11 MISC:POST_CRC_FREQ[7]
12 MISC:POST_CRC_FREQ[8]
13 MISC:POST_CRC_FREQ[9]
14 MISC:POST_CRC_ONESHOT
15 ~MISC:POST_CRC_SEL
MISC:GLUTMASK 0.0.1
MISC:POST_CRC_EN 0.0.0
MISC:POST_CRC_KEEP 0.0.3
MISC:POST_CRC_ONESHOT 0.0.14
non-inverted [0]
MISC:POST_CRC_FREQ 0.0.13 0.0.12 0.0.11 0.0.10 0.0.9 0.0.8 0.0.7 0.0.6 0.0.5 0.0.4
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:POST_CRC_SEL 0.0.15
inverted ~[0]

TESTMODE

spartan6 REG.TESTMODE bittile 0
BitFrame
0
0 MISC:VGG_TEST
1 MISC:ICAP_BYPASS
2 MISC:TESTMODE_EN
MISC:ICAP_BYPASS 0.0.1
MISC:TESTMODE_EN 0.0.2
MISC:VGG_TEST 0.0.0
non-inverted [0]