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North-west

Tile CNR_NW

Cells: 1

Bels OCT_CAL

spartan6 CNR_NW bel OCT_CAL pins
PinDirectionOCT_CAL[0]OCT_CAL[4]
S[0]inIMUX_LOGICIN[29]IMUX_LOGICIN[15]
S[1]inIMUX_LOGICIN[32]IMUX_LOGICIN[7]
spartan6 CNR_NW bel OCT_CAL attribute bits
AttributeOCT_CAL[0]OCT_CAL[4]
VREF_VALUE[enum: OCT_CAL_VREF_VALUE][enum: OCT_CAL_VREF_VALUE]
ACCESS_MODE[enum: OCT_CAL_ACCESS_MODE][enum: OCT_CAL_ACCESS_MODE]
spartan6 CNR_NW enum OCT_CAL_VREF_VALUE
OCT_CAL[0].VREF_VALUEMAIN[22][42]MAIN[22][43]
OCT_CAL[4].VREF_VALUEMAIN[22][45]MAIN[22][46]
NONE00
_0P2501
_0P511
_0P7510
spartan6 CNR_NW enum OCT_CAL_ACCESS_MODE
OCT_CAL[0].ACCESS_MODEMAIN[22][38]
OCT_CAL[4].ACCESS_MODEMAIN[22][39]
STATIC0
USER1

Bels PMV

spartan6 CNR_NW bel PMV pins
PinDirectionPMV
SELECTB[0]inIMUX_LOGICIN[54]
SELECTB[1]inIMUX_LOGICIN[48]
SELECTB[2]inIMUX_LOGICIN[23]
SELECTB[3]inIMUX_LOGICIN[57]
SELECTB[4]inIMUX_LOGICIN[44]
SELECTB[5]inIMUX_LOGICIN[4]
ENABLEBinIMUX_LOGICIN[20]
OUToutOUT_BEL[0]
OUT_DIV2outOUT_BEL[1]
OUT_DIV4outOUT_BEL[2]
spartan6 CNR_NW bel PMV attribute bits
AttributePMV
PSLEW bit 0MAIN[22][54]
PSLEW bit 1MAIN[22][53]
PSLEW bit 2MAIN[22][52]
PSLEW bit 3MAIN[22][51]
NSLEW bit 0MAIN[22][58]
NSLEW bit 1MAIN[22][57]
NSLEW bit 2MAIN[22][56]
NSLEW bit 3MAIN[22][55]

Bels DNA_PORT

spartan6 CNR_NW bel DNA_PORT pins
PinDirectionDNA_PORT
CLKinIMUX_CLK[0]
READinIMUX_LOGICIN[31]
SHIFTinIMUX_LOGICIN[8]
TESTinIMUX_LOGICIN[14]
DINinIMUX_LOGICIN[39]
DOUToutOUT_BEL[23]
spartan6 CNR_NW bel DNA_PORT attribute bits
AttributeDNA_PORT
ENABLEMAIN[22][3]
OPTIONS[enum: DNA_PORT_OPTIONS]
spartan6 CNR_NW enum DNA_PORT_OPTIONS
DNA_PORT.OPTIONSMAIN[22][0]MAIN[22][2]MAIN[22][1]
READ000
PROGRAM011
ANALOG_READ111

Bels MISR

spartan6 CNR_NW bel MISR pins
PinDirectionMISR_CNR_HMISR_CNR_V
spartan6 CNR_NW bel MISR attribute bits
AttributeMISR_CNR_HMISR_CNR_V
ENABLEMAIN[22][49]MAIN[22][47]
RESETMAIN[22][50]MAIN[22][48]

Bels BANK

spartan6 CNR_NW bel BANK pins
PinDirectionBANK[0]BANK[4]
spartan6 CNR_NW bel BANK attribute bits
AttributeBANK[0]BANK[4]
LVDSBIAS[0] bit 0MAIN[22][9]-
LVDSBIAS[0] bit 1MAIN[22][21]-
LVDSBIAS[0] bit 2MAIN[22][20]-
LVDSBIAS[0] bit 3MAIN[22][19]-
LVDSBIAS[0] bit 4MAIN[22][18]-
LVDSBIAS[0] bit 5MAIN[22][17]-
LVDSBIAS[0] bit 6MAIN[22][16]-
LVDSBIAS[0] bit 7MAIN[22][15]-
LVDSBIAS[0] bit 8MAIN[22][14]-
LVDSBIAS[0] bit 9MAIN[22][13]-
LVDSBIAS[0] bit 10MAIN[22][12]-
LVDSBIAS[0] bit 11MAIN[22][11]-
LVDSBIAS[1] bit 0MAIN[22][10]-
LVDSBIAS[1] bit 1MAIN[22][27]-
LVDSBIAS[1] bit 2MAIN[22][26]-
LVDSBIAS[1] bit 3MAIN[22][25]-
LVDSBIAS[1] bit 4MAIN[22][24]-
LVDSBIAS[1] bit 5MAIN[22][23]-
LVDSBIAS[1] bit 6MAIN[22][22]-
LVDSBIAS[1] bit 7MAIN[22][32]-
LVDSBIAS[1] bit 8MAIN[22][31]-
LVDSBIAS[1] bit 9MAIN[22][30]-
LVDSBIAS[1] bit 10MAIN[22][29]-
LVDSBIAS[1] bit 11MAIN[22][28]-

Bels MISC_NW

spartan6 CNR_NW bel MISC_NW pins
PinDirectionMISC_NW
spartan6 CNR_NW bel MISC_NW attribute bits
AttributeMISC_NW
M2_PULL[enum: IOB_PULL]
SELECTHS_PULL[enum: IOB_PULL]
VREF_LV bit 0MAIN[22][34]
VREF_LV bit 1MAIN[22][35]
spartan6 CNR_NW enum IOB_PULL
MISC_NW.M2_PULLMAIN[22][5]MAIN[22][6]
MISC_NW.SELECTHS_PULLMAIN[22][8]MAIN[22][7]
NONE01
PULLUP00
PULLDOWN11

Bel wires

spartan6 CNR_NW bel wires
WirePins
IMUX_CLK[0]DNA_PORT.CLK
IMUX_LOGICIN[4]PMV.SELECTB[5]
IMUX_LOGICIN[7]OCT_CAL[4].S[1]
IMUX_LOGICIN[8]DNA_PORT.SHIFT
IMUX_LOGICIN[14]DNA_PORT.TEST
IMUX_LOGICIN[15]OCT_CAL[4].S[0]
IMUX_LOGICIN[20]PMV.ENABLEB
IMUX_LOGICIN[23]PMV.SELECTB[2]
IMUX_LOGICIN[29]OCT_CAL[0].S[0]
IMUX_LOGICIN[31]DNA_PORT.READ
IMUX_LOGICIN[32]OCT_CAL[0].S[1]
IMUX_LOGICIN[39]DNA_PORT.DIN
IMUX_LOGICIN[44]PMV.SELECTB[4]
IMUX_LOGICIN[48]PMV.SELECTB[1]
IMUX_LOGICIN[54]PMV.SELECTB[0]
IMUX_LOGICIN[57]PMV.SELECTB[3]
OUT_BEL[0]PMV.OUT
OUT_BEL[1]PMV.OUT_DIV2
OUT_BEL[2]PMV.OUT_DIV4
OUT_BEL[23]DNA_PORT.DOUT

Bitstream

spartan6 CNR_NW rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - PMV: NSLEW bit 0 - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - PMV: NSLEW bit 1 - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - PMV: NSLEW bit 2 - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - PMV: NSLEW bit 3 - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - PMV: PSLEW bit 0 - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - PMV: PSLEW bit 1 - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - PMV: PSLEW bit 2 - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - PMV: PSLEW bit 3 - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - MISR_CNR_H: RESET - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - MISR_CNR_H: ENABLE - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - MISR_CNR_V: RESET - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - MISR_CNR_V: ENABLE - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[4]: VREF_VALUE bit 0 - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[4]: VREF_VALUE bit 1 - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[0]: VREF_VALUE bit 0 - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[0]: VREF_VALUE bit 1 - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[4]: ACCESS_MODE bit 0 - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - OCT_CAL[0]: ACCESS_MODE bit 0 - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: VREF_LV bit 1 - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: VREF_LV bit 0 - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 7 - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 8 - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 9 - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 10 - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 11 - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 1 - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 2 - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 3 - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 4 - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 5 - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 6 - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 1 - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 2 - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 3 - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 4 - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 5 - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 6 - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 7 - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 8 - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 9 - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 10 - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 11 - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[1] bit 0 - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - BANK[0]: LVDSBIAS[0] bit 0 - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: SELECTHS_PULL bit 1 - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: SELECTHS_PULL bit 0 - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: M2_PULL bit 0 - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - MISC_NW: M2_PULL bit 1 - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - DNA_PORT: ENABLE - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - DNA_PORT: OPTIONS bit 1 - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - DNA_PORT: OPTIONS bit 0 - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - DNA_PORT: OPTIONS bit 2 - - - - - - -