General interconnect

Tile slots

spartan6 tile slots
Slot	Tiles	Bel slots
INT	INT, INT_IOI	INT
INTF	INTF, INTF_IOI, INTF_CMT, INTF_CMT_IOI	INTF_INT, INTF_TESTMUX
BEL	CLEXL, CLEXM, BRAM, DSP, IOI_WE, IOI_SN, CMT_DCM, CMT_PLL, MCB, PCIE, GTP, PCILOGICSE, CNR_SW, CNR_NW, CNR_SE, CNR_NE, CLKC	SLICE[0], SLICE[1], BRAM[0], BRAM[1], DSP, IOI_INT, IOI_DDR[0], IOI_DDR[1], ILOGIC[0], ILOGIC[1], OLOGIC[0], OLOGIC[1], IODELAY[0], IODELAY[1], MISC_IOI, DCM[0], DCM[1], CMT_VREG, PLL, CMT_INT, MCB, PCIE, GTP, PCILOGICSE, OCT_CAL[0], OCT_CAL[1], OCT_CAL[2], OCT_CAL[3], OCT_CAL[4], OCT_CAL[5], PMV, DNA_PORT, ICAP, SPI_ACCESS, SUSPEND_SYNC, POST_CRC_INTERNAL, STARTUP, SLAVE_SPI, BSCAN[0], BSCAN[1], BSCAN[2], BSCAN[3], MISR_CNR_H, MISR_CNR_V, BANK[0], BANK[1], BANK[2], BANK[3], BANK[4], BANK[5], MISC_SW, MISC_SE, MISC_NW, MISC_NE, BUFGMUX[0], BUFGMUX[1], BUFGMUX[2], BUFGMUX[3], BUFGMUX[4], BUFGMUX[5], BUFGMUX[6], BUFGMUX[7], BUFGMUX[8], BUFGMUX[9], BUFGMUX[10], BUFGMUX[11], BUFGMUX[12], BUFGMUX[13], BUFGMUX[14], BUFGMUX[15], CLKC_INT
IOB	IOB	IOB[0], IOB[1]
HCLK	HCLK	HCLK
HCLK_BEL	HCLK_CLEXL, HCLK_CLEXM, HCLK_IOI, HCLK_GTP	GLUTMASK_HCLK
HCLK_ROW	HCLK_ROW	HCLK_ROW
CLK	CLK_W, CLK_E, CLK_S, CLK_N	CLK_INT, BUFIO2[0], BUFIO2[1], BUFIO2[2], BUFIO2[3], BUFIO2[4], BUFIO2[5], BUFIO2[6], BUFIO2[7], BUFIO2FB[0], BUFIO2FB[1], BUFIO2FB[2], BUFIO2FB[3], BUFIO2FB[4], BUFIO2FB[5], BUFIO2FB[6], BUFIO2FB[7], BUFPLL, MISR_CLK
CMT_BUF	DCM_BUFPLL_BUF_S, DCM_BUFPLL_BUF_S_MID, DCM_BUFPLL_BUF_N, DCM_BUFPLL_BUF_N_MID, PLL_BUFPLL_OUT0_S, PLL_BUFPLL_OUT0_N, PLL_BUFPLL_OUT1_S, PLL_BUFPLL_OUT1_N, PLL_BUFPLL_S, PLL_BUFPLL_N	CMT_BUF
GLOBAL	GLOBAL	GLOBAL

Bel slots

spartan6 bel slots
Slot	Class	Tile slot	Tiles
INT	routing	INT	INT, INT_IOI
INTF_INT	routing	INTF	INTF, INTF_IOI, INTF_CMT, INTF_CMT_IOI
INTF_TESTMUX	routing	INTF	INTF, INTF_IOI, INTF_CMT, INTF_CMT_IOI
SLICE[0]	SLICE	BEL	CLEXL, CLEXM
SLICE[1]	SLICE	BEL	CLEXL, CLEXM
BRAM[0]	BRAM	BEL	BRAM
BRAM[1]	BRAM	BEL	BRAM
DSP	DSP	BEL	DSP
IOI_INT	routing	BEL	IOI_WE, IOI_SN
IOI_DDR[0]	IOI_DDR	BEL	IOI_WE, IOI_SN
IOI_DDR[1]	IOI_DDR	BEL	IOI_WE, IOI_SN
ILOGIC[0]	ILOGIC	BEL	IOI_WE, IOI_SN
ILOGIC[1]	ILOGIC	BEL	IOI_WE, IOI_SN
OLOGIC[0]	OLOGIC	BEL	IOI_WE, IOI_SN
OLOGIC[1]	OLOGIC	BEL	IOI_WE, IOI_SN
IODELAY[0]	IODELAY	BEL	IOI_WE, IOI_SN
IODELAY[1]	IODELAY	BEL	IOI_WE, IOI_SN
MISC_IOI	MISC_IOI	BEL	IOI_WE, IOI_SN
DCM[0]	DCM	BEL	CMT_DCM
DCM[1]	DCM	BEL	CMT_DCM
CMT_VREG	CMT_VREG	BEL	CMT_DCM
PLL	PLL	BEL	CMT_PLL
CMT_INT	routing	BEL	CMT_DCM, CMT_PLL
MCB	MCB	BEL	MCB
PCIE	PCIE	BEL	PCIE
GTP	GTP	BEL	GTP
PCILOGICSE	PCILOGICSE	BEL	PCILOGICSE
OCT_CAL[0]	OCT_CAL	BEL	CNR_NW
OCT_CAL[1]	OCT_CAL	BEL	CNR_SE
OCT_CAL[2]	OCT_CAL	BEL	CNR_SW
OCT_CAL[3]	OCT_CAL	BEL	CNR_SW
OCT_CAL[4]	OCT_CAL	BEL	CNR_NW
OCT_CAL[5]	OCT_CAL	BEL	CNR_NE
PMV	PMV	BEL	CNR_NW
DNA_PORT	DNA_PORT	BEL	CNR_NW
ICAP	ICAP	BEL	CNR_SE
SPI_ACCESS	SPI_ACCESS	BEL	CNR_SE
SUSPEND_SYNC	SUSPEND_SYNC	BEL	CNR_SE
POST_CRC_INTERNAL	POST_CRC_INTERNAL	BEL	CNR_SE
STARTUP	STARTUP	BEL	CNR_SE
SLAVE_SPI	SLAVE_SPI	BEL	CNR_SE
BSCAN[0]	BSCAN	BEL	CNR_NE
BSCAN[1]	BSCAN	BEL	CNR_NE
BSCAN[2]	BSCAN	BEL	CNR_NE
BSCAN[3]	BSCAN	BEL	CNR_NE
MISR_CNR_H	MISR	BEL	CNR_SW, CNR_NW, CNR_SE, CNR_NE
MISR_CNR_V	MISR	BEL	CNR_SW, CNR_NW, CNR_SE, CNR_NE
BANK[0]	BANK	BEL	CNR_NW
BANK[1]	BANK	BEL	CNR_SE
BANK[2]	BANK	BEL	CNR_SW
BANK[3]	BANK	BEL	CNR_SW
BANK[4]	BANK	BEL	CNR_NW
BANK[5]	BANK	BEL	CNR_NE
MISC_SW	MISC_SW	BEL	CNR_SW
MISC_SE	MISC_SE	BEL	CNR_SE
MISC_NW	MISC_NW	BEL	CNR_NW
MISC_NE	MISC_NE	BEL	CNR_NE
BUFGMUX[0]	BUFGMUX	BEL	CLKC
BUFGMUX[1]	BUFGMUX	BEL	CLKC
BUFGMUX[2]	BUFGMUX	BEL	CLKC
BUFGMUX[3]	BUFGMUX	BEL	CLKC
BUFGMUX[4]	BUFGMUX	BEL	CLKC
BUFGMUX[5]	BUFGMUX	BEL	CLKC
BUFGMUX[6]	BUFGMUX	BEL	CLKC
BUFGMUX[7]	BUFGMUX	BEL	CLKC
BUFGMUX[8]	BUFGMUX	BEL	CLKC
BUFGMUX[9]	BUFGMUX	BEL	CLKC
BUFGMUX[10]	BUFGMUX	BEL	CLKC
BUFGMUX[11]	BUFGMUX	BEL	CLKC
BUFGMUX[12]	BUFGMUX	BEL	CLKC
BUFGMUX[13]	BUFGMUX	BEL	CLKC
BUFGMUX[14]	BUFGMUX	BEL	CLKC
BUFGMUX[15]	BUFGMUX	BEL	CLKC
CLKC_INT	routing	BEL	CLKC
IOB[0]	IOB	IOB	IOB
IOB[1]	IOB	IOB	IOB
HCLK	routing	HCLK	HCLK
GLUTMASK_HCLK	GLUTMASK_HCLK	HCLK_BEL	HCLK_CLEXL, HCLK_CLEXM, HCLK_IOI, HCLK_GTP
HCLK_ROW	routing	HCLK_ROW	HCLK_ROW
CLK_INT	routing	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[0]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[1]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[2]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[3]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[4]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[5]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[6]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2[7]	BUFIO2	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[0]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[1]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[2]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[3]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[4]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[5]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[6]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFIO2FB[7]	BUFIO2FB	CLK	CLK_W, CLK_E, CLK_S, CLK_N
BUFPLL	BUFPLL	CLK	CLK_W, CLK_E, CLK_S, CLK_N
MISR_CLK	MISR	CLK	CLK_S, CLK_N
CMT_BUF	routing	CMT_BUF	DCM_BUFPLL_BUF_S, DCM_BUFPLL_BUF_S_MID, DCM_BUFPLL_BUF_N, DCM_BUFPLL_BUF_N_MID, PLL_BUFPLL_OUT0_S, PLL_BUFPLL_OUT0_N, PLL_BUFPLL_OUT1_S, PLL_BUFPLL_OUT1_N, PLL_BUFPLL_S, PLL_BUFPLL_N
GLOBAL	GLOBAL	GLOBAL	GLOBAL

Connector slots

spartan6 connector slots
Slot	Opposite	Connectors
W	E	PASS_W, TERM_W
E	W	PASS_E, TERM_E
S	N	PASS_S, TERM_S
N	S	PASS_N, TERM_N
CMT_PREV	CMT_NEXT	CMT_PREV
CMT_NEXT	CMT_PREV	CMT_NEXT
CMT_S	CMT_N	CMT_S
CMT_N	CMT_S	CMT_N

Region slots

spartan6 region slots
Slot	Wires
GLOBAL	GCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15]
PLLCLK	PLLCLK[0], PLLCLK[1], PLLCE[0], PLLCE[1]
IOCLK	IOCLK[0], IOCLK[1], IOCLK[2], IOCLK[3], IOCE[0], IOCE[1], IOCE[2], IOCE[3], GTPCLK[0], GTPCLK[1], GTPCLK[2], GTPCLK[3], GTPFB[0], GTPFB[1], GTPFB[2], GTPFB[3]
DIVCLK_CMT	DIVCLK_CMT_W[0], DIVCLK_CMT_W[1], DIVCLK_CMT_W[2], DIVCLK_CMT_W[3], DIVCLK_CMT_E[0], DIVCLK_CMT_E[1], DIVCLK_CMT_E[2], DIVCLK_CMT_E[3], DIVCLK_CMT_V[0], DIVCLK_CMT_V[1], DIVCLK_CMT_V[2], DIVCLK_CMT_V[3], DIVCLK_CMT_V[4], DIVCLK_CMT_V[5], DIVCLK_CMT_V[6], DIVCLK_CMT_V[7], IOFBCLK_CMT_W[0], IOFBCLK_CMT_W[1], IOFBCLK_CMT_W[2], IOFBCLK_CMT_W[3], IOFBCLK_CMT_E[0], IOFBCLK_CMT_E[1], IOFBCLK_CMT_E[2], IOFBCLK_CMT_E[3], IOFBCLK_CMT_V[0], IOFBCLK_CMT_V[1], IOFBCLK_CMT_V[2], IOFBCLK_CMT_V[3], IOFBCLK_CMT_V[4], IOFBCLK_CMT_V[5], IOFBCLK_CMT_V[6], IOFBCLK_CMT_V[7]
HROW	HCLK_ROW[0], HCLK_ROW[1], HCLK_ROW[2], HCLK_ROW[3], HCLK_ROW[4], HCLK_ROW[5], HCLK_ROW[6], HCLK_ROW[7], HCLK_ROW[8], HCLK_ROW[9], HCLK_ROW[10], HCLK_ROW[11], HCLK_ROW[12], HCLK_ROW[13], HCLK_ROW[14], HCLK_ROW[15]
LEAF	HCLK[0], HCLK[1], HCLK[2], HCLK[3], HCLK[4], HCLK[5], HCLK[6], HCLK[7], HCLK[8], HCLK[9], HCLK[10], HCLK[11], HCLK[12], HCLK[13], HCLK[14], HCLK[15]

Wires

spartan6 wires
Wire	Kind
PULLUP	pullup
TIE_0	tie 0
TIE_1	tie 1
HCLK[0]	regional LEAF
HCLK[1]	regional LEAF
HCLK[2]	regional LEAF
HCLK[3]	regional LEAF
HCLK[4]	regional LEAF
HCLK[5]	regional LEAF
HCLK[6]	regional LEAF
HCLK[7]	regional LEAF
HCLK[8]	regional LEAF
HCLK[9]	regional LEAF
HCLK[10]	regional LEAF
HCLK[11]	regional LEAF
HCLK[12]	regional LEAF
HCLK[13]	regional LEAF
HCLK[14]	regional LEAF
HCLK[15]	regional LEAF
SNG_W0[0]	mux
SNG_W0[1]	mux
SNG_W0[2]	mux
SNG_W0[3]	mux
SNG_W0[4]	mux
SNG_W0[5]	mux
SNG_W0[6]	mux
SNG_W0[7]	mux
SNG_W1[0]	branch E
SNG_W1[1]	branch E
SNG_W1[2]	branch E
SNG_W1[3]	branch E
SNG_W1[4]	branch E
SNG_W1[5]	branch E
SNG_W1[6]	branch E
SNG_W1[7]	branch E
SNG_W1_N3	branch S
SNG_W1_S4	branch N
SNG_E0[0]	mux
SNG_E0[1]	mux
SNG_E0[2]	mux
SNG_E0[3]	mux
SNG_E0[4]	mux
SNG_E0[5]	mux
SNG_E0[6]	mux
SNG_E0[7]	mux
SNG_E1[0]	branch W
SNG_E1[1]	branch W
SNG_E1[2]	branch W
SNG_E1[3]	branch W
SNG_E1[4]	branch W
SNG_E1[5]	branch W
SNG_E1[6]	branch W
SNG_E1[7]	branch W
SNG_E1_S0	branch N
SNG_E1_N7	branch S
SNG_S0[0]	mux
SNG_S0[1]	mux
SNG_S0[2]	mux
SNG_S0[3]	mux
SNG_S0[4]	mux
SNG_S0[5]	mux
SNG_S0[6]	mux
SNG_S0[7]	mux
SNG_S1[0]	branch N
SNG_S1[1]	branch N
SNG_S1[2]	branch N
SNG_S1[3]	branch N
SNG_S1[4]	branch N
SNG_S1[5]	branch N
SNG_S1[6]	branch N
SNG_S1[7]	branch N
SNG_S1_N7	branch S
SNG_N0[0]	mux
SNG_N0[1]	mux
SNG_N0[2]	mux
SNG_N0[3]	mux
SNG_N0[4]	mux
SNG_N0[5]	mux
SNG_N0[6]	mux
SNG_N0[7]	mux
SNG_N1[0]	branch S
SNG_N1[1]	branch S
SNG_N1[2]	branch S
SNG_N1[3]	branch S
SNG_N1[4]	branch S
SNG_N1[5]	branch S
SNG_N1[6]	branch S
SNG_N1[7]	branch S
SNG_N1_S0	branch N
DBL_WW0[0]	mux
DBL_WW0[1]	mux
DBL_WW0[2]	mux
DBL_WW0[3]	mux
DBL_WW1[0]	branch E
DBL_WW1[1]	branch E
DBL_WW1[2]	branch E
DBL_WW1[3]	branch E
DBL_WW2[0]	branch E
DBL_WW2[1]	branch E
DBL_WW2[2]	branch E
DBL_WW2[3]	branch E
DBL_WW2_N3	branch S
DBL_EE0[0]	mux
DBL_EE0[1]	mux
DBL_EE0[2]	mux
DBL_EE0[3]	mux
DBL_EE1[0]	branch W
DBL_EE1[1]	branch W
DBL_EE1[2]	branch W
DBL_EE1[3]	branch W
DBL_EE2[0]	branch W
DBL_EE2[1]	branch W
DBL_EE2[2]	branch W
DBL_EE2[3]	branch W
DBL_SS0[0]	mux
DBL_SS0[1]	mux
DBL_SS0[2]	mux
DBL_SS0[3]	mux
DBL_SS1[0]	branch N
DBL_SS1[1]	branch N
DBL_SS1[2]	branch N
DBL_SS1[3]	branch N
DBL_SS2[0]	branch N
DBL_SS2[1]	branch N
DBL_SS2[2]	branch N
DBL_SS2[3]	branch N
DBL_SS2_N3	branch S
DBL_SW0[0]	mux
DBL_SW0[1]	mux
DBL_SW0[2]	mux
DBL_SW0[3]	mux
DBL_SW1[0]	branch N
DBL_SW1[1]	branch N
DBL_SW1[2]	branch N
DBL_SW1[3]	branch N
DBL_SW2[0]	branch E
DBL_SW2[1]	branch E
DBL_SW2[2]	branch E
DBL_SW2[3]	branch E
DBL_SW2_N3	branch S
DBL_SE0[0]	mux
DBL_SE0[1]	mux
DBL_SE0[2]	mux
DBL_SE0[3]	mux
DBL_SE1[0]	branch N
DBL_SE1[1]	branch N
DBL_SE1[2]	branch N
DBL_SE1[3]	branch N
DBL_SE2[0]	branch W
DBL_SE2[1]	branch W
DBL_SE2[2]	branch W
DBL_SE2[3]	branch W
DBL_NN0[0]	mux
DBL_NN0[1]	mux
DBL_NN0[2]	mux
DBL_NN0[3]	mux
DBL_NN1[0]	branch S
DBL_NN1[1]	branch S
DBL_NN1[2]	branch S
DBL_NN1[3]	branch S
DBL_NN2[0]	branch S
DBL_NN2[1]	branch S
DBL_NN2[2]	branch S
DBL_NN2[3]	branch S
DBL_NN2_S0	branch N
DBL_NW0[0]	mux
DBL_NW0[1]	mux
DBL_NW0[2]	mux
DBL_NW0[3]	mux
DBL_NW1[0]	branch S
DBL_NW1[1]	branch S
DBL_NW1[2]	branch S
DBL_NW1[3]	branch S
DBL_NW2[0]	branch E
DBL_NW2[1]	branch E
DBL_NW2[2]	branch E
DBL_NW2[3]	branch E
DBL_NW2_S0	branch N
DBL_NE0[0]	mux
DBL_NE0[1]	mux
DBL_NE0[2]	mux
DBL_NE0[3]	mux
DBL_NE1[0]	branch S
DBL_NE1[1]	branch S
DBL_NE1[2]	branch S
DBL_NE1[3]	branch S
DBL_NE2[0]	branch W
DBL_NE2[1]	branch W
DBL_NE2[2]	branch W
DBL_NE2[3]	branch W
DBL_NE2_S0	branch N
QUAD_WW0[0]	mux
QUAD_WW0[1]	mux
QUAD_WW0[2]	mux
QUAD_WW0[3]	mux
QUAD_WW1[0]	branch E
QUAD_WW1[1]	branch E
QUAD_WW1[2]	branch E
QUAD_WW1[3]	branch E
QUAD_WW2[0]	branch E
QUAD_WW2[1]	branch E
QUAD_WW2[2]	branch E
QUAD_WW2[3]	branch E
QUAD_WW3[0]	branch E
QUAD_WW3[1]	branch E
QUAD_WW3[2]	branch E
QUAD_WW3[3]	branch E
QUAD_WW4[0]	branch E
QUAD_WW4[1]	branch E
QUAD_WW4[2]	branch E
QUAD_WW4[3]	branch E
QUAD_WW4_S0	branch N
QUAD_EE0[0]	mux
QUAD_EE0[1]	mux
QUAD_EE0[2]	mux
QUAD_EE0[3]	mux
QUAD_EE1[0]	branch W
QUAD_EE1[1]	branch W
QUAD_EE1[2]	branch W
QUAD_EE1[3]	branch W
QUAD_EE2[0]	branch W
QUAD_EE2[1]	branch W
QUAD_EE2[2]	branch W
QUAD_EE2[3]	branch W
QUAD_EE3[0]	branch W
QUAD_EE3[1]	branch W
QUAD_EE3[2]	branch W
QUAD_EE3[3]	branch W
QUAD_EE4[0]	branch W
QUAD_EE4[1]	branch W
QUAD_EE4[2]	branch W
QUAD_EE4[3]	branch W
QUAD_SS0[0]	mux
QUAD_SS0[1]	mux
QUAD_SS0[2]	mux
QUAD_SS0[3]	mux
QUAD_SS1[0]	branch N
QUAD_SS1[1]	branch N
QUAD_SS1[2]	branch N
QUAD_SS1[3]	branch N
QUAD_SS2[0]	branch N
QUAD_SS2[1]	branch N
QUAD_SS2[2]	branch N
QUAD_SS2[3]	branch N
QUAD_SS3[0]	branch N
QUAD_SS3[1]	branch N
QUAD_SS3[2]	branch N
QUAD_SS3[3]	branch N
QUAD_SS4[0]	branch N
QUAD_SS4[1]	branch N
QUAD_SS4[2]	branch N
QUAD_SS4[3]	branch N
QUAD_SS4_N3	branch S
QUAD_SW0[0]	mux
QUAD_SW0[1]	mux
QUAD_SW0[2]	mux
QUAD_SW0[3]	mux
QUAD_SW1[0]	branch N
QUAD_SW1[1]	branch N
QUAD_SW1[2]	branch N
QUAD_SW1[3]	branch N
QUAD_SW2[0]	branch N
QUAD_SW2[1]	branch N
QUAD_SW2[2]	branch N
QUAD_SW2[3]	branch N
QUAD_SW3[0]	branch E
QUAD_SW3[1]	branch E
QUAD_SW3[2]	branch E
QUAD_SW3[3]	branch E
QUAD_SW4[0]	branch E
QUAD_SW4[1]	branch E
QUAD_SW4[2]	branch E
QUAD_SW4[3]	branch E
QUAD_SW4_N3	branch S
QUAD_SE0[0]	mux
QUAD_SE0[1]	mux
QUAD_SE0[2]	mux
QUAD_SE0[3]	mux
QUAD_SE1[0]	branch N
QUAD_SE1[1]	branch N
QUAD_SE1[2]	branch N
QUAD_SE1[3]	branch N
QUAD_SE2[0]	branch N
QUAD_SE2[1]	branch N
QUAD_SE2[2]	branch N
QUAD_SE2[3]	branch N
QUAD_SE3[0]	branch W
QUAD_SE3[1]	branch W
QUAD_SE3[2]	branch W
QUAD_SE3[3]	branch W
QUAD_SE4[0]	branch W
QUAD_SE4[1]	branch W
QUAD_SE4[2]	branch W
QUAD_SE4[3]	branch W
QUAD_NN0[0]	mux
QUAD_NN0[1]	mux
QUAD_NN0[2]	mux
QUAD_NN0[3]	mux
QUAD_NN1[0]	branch S
QUAD_NN1[1]	branch S
QUAD_NN1[2]	branch S
QUAD_NN1[3]	branch S
QUAD_NN2[0]	branch S
QUAD_NN2[1]	branch S
QUAD_NN2[2]	branch S
QUAD_NN2[3]	branch S
QUAD_NN3[0]	branch S
QUAD_NN3[1]	branch S
QUAD_NN3[2]	branch S
QUAD_NN3[3]	branch S
QUAD_NN4[0]	branch S
QUAD_NN4[1]	branch S
QUAD_NN4[2]	branch S
QUAD_NN4[3]	branch S
QUAD_NW0[0]	mux
QUAD_NW0[1]	mux
QUAD_NW0[2]	mux
QUAD_NW0[3]	mux
QUAD_NW1[0]	branch S
QUAD_NW1[1]	branch S
QUAD_NW1[2]	branch S
QUAD_NW1[3]	branch S
QUAD_NW2[0]	branch S
QUAD_NW2[1]	branch S
QUAD_NW2[2]	branch S
QUAD_NW2[3]	branch S
QUAD_NW3[0]	branch E
QUAD_NW3[1]	branch E
QUAD_NW3[2]	branch E
QUAD_NW3[3]	branch E
QUAD_NW4[0]	branch E
QUAD_NW4[1]	branch E
QUAD_NW4[2]	branch E
QUAD_NW4[3]	branch E
QUAD_NW4_S0	branch N
QUAD_NE0[0]	mux
QUAD_NE0[1]	mux
QUAD_NE0[2]	mux
QUAD_NE0[3]	mux
QUAD_NE1[0]	branch S
QUAD_NE1[1]	branch S
QUAD_NE1[2]	branch S
QUAD_NE1[3]	branch S
QUAD_NE2[0]	branch S
QUAD_NE2[1]	branch S
QUAD_NE2[2]	branch S
QUAD_NE2[3]	branch S
QUAD_NE3[0]	branch W
QUAD_NE3[1]	branch W
QUAD_NE3[2]	branch W
QUAD_NE3[3]	branch W
QUAD_NE4[0]	branch W
QUAD_NE4[1]	branch W
QUAD_NE4[2]	branch W
QUAD_NE4[3]	branch W
IMUX_GFAN[0]	mux
IMUX_GFAN[1]	mux
IMUX_CLK[0]	mux
IMUX_CLK[1]	mux
IMUX_SR[0]	mux
IMUX_SR[1]	mux
IMUX_LOGICIN[0]	mux
IMUX_LOGICIN[1]	mux
IMUX_LOGICIN[2]	mux
IMUX_LOGICIN[3]	mux
IMUX_LOGICIN[4]	mux
IMUX_LOGICIN[5]	mux
IMUX_LOGICIN[6]	mux
IMUX_LOGICIN[7]	mux
IMUX_LOGICIN[8]	mux
IMUX_LOGICIN[9]	mux
IMUX_LOGICIN[10]	mux
IMUX_LOGICIN[11]	mux
IMUX_LOGICIN[12]	mux
IMUX_LOGICIN[13]	mux
IMUX_LOGICIN[14]	mux
IMUX_LOGICIN[15]	mux
IMUX_LOGICIN[16]	mux
IMUX_LOGICIN[17]	mux
IMUX_LOGICIN[18]	mux
IMUX_LOGICIN[19]	mux
IMUX_LOGICIN[20]	mux
IMUX_LOGICIN[21]	mux
IMUX_LOGICIN[22]	mux
IMUX_LOGICIN[23]	mux
IMUX_LOGICIN[24]	mux
IMUX_LOGICIN[25]	mux
IMUX_LOGICIN[26]	mux
IMUX_LOGICIN[27]	mux
IMUX_LOGICIN[28]	mux
IMUX_LOGICIN[29]	mux
IMUX_LOGICIN[30]	mux
IMUX_LOGICIN[31]	mux
IMUX_LOGICIN[32]	mux
IMUX_LOGICIN[33]	mux
IMUX_LOGICIN[34]	mux
IMUX_LOGICIN[35]	mux
IMUX_LOGICIN[36]	mux
IMUX_LOGICIN[37]	mux
IMUX_LOGICIN[38]	mux
IMUX_LOGICIN[39]	mux
IMUX_LOGICIN[40]	mux
IMUX_LOGICIN[41]	mux
IMUX_LOGICIN[42]	mux
IMUX_LOGICIN[43]	mux
IMUX_LOGICIN[44]	mux
IMUX_LOGICIN[45]	mux
IMUX_LOGICIN[46]	mux
IMUX_LOGICIN[47]	mux
IMUX_LOGICIN[48]	mux
IMUX_LOGICIN[49]	mux
IMUX_LOGICIN[50]	mux
IMUX_LOGICIN[51]	mux
IMUX_LOGICIN[52]	mux
IMUX_LOGICIN[53]	mux
IMUX_LOGICIN[54]	mux
IMUX_LOGICIN[55]	mux
IMUX_LOGICIN[56]	mux
IMUX_LOGICIN[57]	mux
IMUX_LOGICIN[58]	mux
IMUX_LOGICIN[59]	mux
IMUX_LOGICIN[60]	mux
IMUX_LOGICIN[61]	mux
IMUX_LOGICIN[62]	mux
IMUX_LOGICIN[63]	mux
IMUX_LOGICIN20_BOUNCE	mux
IMUX_LOGICIN36_BOUNCE	mux
IMUX_LOGICIN44_BOUNCE	mux
IMUX_LOGICIN62_BOUNCE	mux
IMUX_LOGICIN21_BOUNCE	mux
IMUX_LOGICIN28_BOUNCE	mux
IMUX_LOGICIN52_BOUNCE	mux
IMUX_LOGICIN60_BOUNCE	mux
IMUX_LOGICIN20_S	branch N
IMUX_LOGICIN36_S	branch N
IMUX_LOGICIN44_S	branch N
IMUX_LOGICIN62_S	branch N
IMUX_LOGICIN21_N	branch S
IMUX_LOGICIN28_N	branch S
IMUX_LOGICIN52_N	branch S
IMUX_LOGICIN60_N	branch S
OUT[0]	bel
OUT[1]	bel
OUT[2]	bel
OUT[3]	bel
OUT[4]	bel
OUT[5]	bel
OUT[6]	bel
OUT[7]	bel
OUT[8]	bel
OUT[9]	bel
OUT[10]	bel
OUT[11]	bel
OUT[12]	bel
OUT[13]	bel
OUT[14]	bel
OUT[15]	bel
OUT[16]	bel
OUT[17]	bel
OUT[18]	bel
OUT[19]	bel
OUT[20]	bel
OUT[21]	bel
OUT[22]	bel
OUT[23]	bel
OUT_BEL[0]	bel
OUT_BEL[1]	bel
OUT_BEL[2]	bel
OUT_BEL[3]	bel
OUT_BEL[4]	bel
OUT_BEL[5]	bel
OUT_BEL[6]	bel
OUT_BEL[7]	bel
OUT_BEL[8]	bel
OUT_BEL[9]	bel
OUT_BEL[10]	bel
OUT_BEL[11]	bel
OUT_BEL[12]	bel
OUT_BEL[13]	bel
OUT_BEL[14]	bel
OUT_BEL[15]	bel
OUT_BEL[16]	bel
OUT_BEL[17]	bel
OUT_BEL[18]	bel
OUT_BEL[19]	bel
OUT_BEL[20]	bel
OUT_BEL[21]	bel
OUT_BEL[22]	bel
OUT_BEL[23]	bel
OUT_TEST[0]	test
OUT_TEST[1]	test
OUT_TEST[2]	test
OUT_TEST[3]	test
OUT_TEST[4]	test
OUT_TEST[5]	test
OUT_TEST[6]	test
OUT_TEST[7]	test
OUT_TEST[8]	test
OUT_TEST[9]	test
OUT_TEST[10]	test
OUT_TEST[11]	test
OUT_TEST[12]	test
OUT_TEST[13]	test
OUT_TEST[14]	test
OUT_TEST[15]	test
OUT_TEST[16]	test
OUT_TEST[17]	test
OUT_TEST[18]	test
OUT_TEST[19]	test
OUT_TEST[20]	test
OUT_TEST[21]	test
OUT_TEST[22]	test
OUT_TEST[23]	test
IMUX_CLK_GCLK[0]	mux
IMUX_CLK_GCLK[1]	mux
IOCLK[0]	regional IOCLK
IOCLK[1]	regional IOCLK
IOCLK[2]	regional IOCLK
IOCLK[3]	regional IOCLK
IOCE[0]	regional IOCLK
IOCE[1]	regional IOCLK
IOCE[2]	regional IOCLK
IOCE[3]	regional IOCLK
PLLCLK[0]	regional PLLCLK
PLLCLK[1]	regional PLLCLK
PLLCE[0]	regional PLLCLK
PLLCE[1]	regional PLLCLK
GTPCLK[0]	regional IOCLK
GTPCLK[1]	regional IOCLK
GTPCLK[2]	regional IOCLK
GTPCLK[3]	regional IOCLK
GTPFB[0]	regional IOCLK
GTPFB[1]	regional IOCLK
GTPFB[2]	regional IOCLK
GTPFB[3]	regional IOCLK
IMUX_BUFIO2_I[0]	mux
IMUX_BUFIO2_I[1]	mux
IMUX_BUFIO2_I[2]	mux
IMUX_BUFIO2_I[3]	mux
IMUX_BUFIO2_IB[0]	mux
IMUX_BUFIO2_IB[1]	mux
IMUX_BUFIO2_IB[2]	mux
IMUX_BUFIO2_IB[3]	mux
IMUX_BUFIO2FB[0]	mux
IMUX_BUFIO2FB[1]	mux
IMUX_BUFIO2FB[2]	mux
IMUX_BUFIO2FB[3]	mux
OUT_DIVCLK[0]	bel
OUT_DIVCLK[1]	bel
OUT_DIVCLK[2]	bel
OUT_DIVCLK[3]	bel
DIVCLK_CLKC[0]	mux
DIVCLK_CLKC[1]	mux
DIVCLK_CLKC[2]	mux
DIVCLK_CLKC[3]	mux
DIVCLK_CLKC[4]	mux
DIVCLK_CLKC[5]	mux
DIVCLK_CLKC[6]	mux
DIVCLK_CLKC[7]	mux
DIVCLK_CMT_W[0]	regional DIVCLK_CMT
DIVCLK_CMT_W[1]	regional DIVCLK_CMT
DIVCLK_CMT_W[2]	regional DIVCLK_CMT
DIVCLK_CMT_W[3]	regional DIVCLK_CMT
DIVCLK_CMT_E[0]	regional DIVCLK_CMT
DIVCLK_CMT_E[1]	regional DIVCLK_CMT
DIVCLK_CMT_E[2]	regional DIVCLK_CMT
DIVCLK_CMT_E[3]	regional DIVCLK_CMT
DIVCLK_CMT_V[0]	regional DIVCLK_CMT
DIVCLK_CMT_V[1]	regional DIVCLK_CMT
DIVCLK_CMT_V[2]	regional DIVCLK_CMT
DIVCLK_CMT_V[3]	regional DIVCLK_CMT
DIVCLK_CMT_V[4]	regional DIVCLK_CMT
DIVCLK_CMT_V[5]	regional DIVCLK_CMT
DIVCLK_CMT_V[6]	regional DIVCLK_CMT
DIVCLK_CMT_V[7]	regional DIVCLK_CMT
IOFBCLK_CMT_W[0]	regional DIVCLK_CMT
IOFBCLK_CMT_W[1]	regional DIVCLK_CMT
IOFBCLK_CMT_W[2]	regional DIVCLK_CMT
IOFBCLK_CMT_W[3]	regional DIVCLK_CMT
IOFBCLK_CMT_E[0]	regional DIVCLK_CMT
IOFBCLK_CMT_E[1]	regional DIVCLK_CMT
IOFBCLK_CMT_E[2]	regional DIVCLK_CMT
IOFBCLK_CMT_E[3]	regional DIVCLK_CMT
IOFBCLK_CMT_V[0]	regional DIVCLK_CMT
IOFBCLK_CMT_V[1]	regional DIVCLK_CMT
IOFBCLK_CMT_V[2]	regional DIVCLK_CMT
IOFBCLK_CMT_V[3]	regional DIVCLK_CMT
IOFBCLK_CMT_V[4]	regional DIVCLK_CMT
IOFBCLK_CMT_V[5]	regional DIVCLK_CMT
IOFBCLK_CMT_V[6]	regional DIVCLK_CMT
IOFBCLK_CMT_V[7]	regional DIVCLK_CMT
OUT_CLKPAD_I[0]	bel
OUT_CLKPAD_I[1]	bel
OUT_CLKPAD_DFB[0]	bel
OUT_CLKPAD_DFB[1]	bel
OUT_CLKPAD_CFB0[0]	bel
OUT_CLKPAD_CFB0[1]	bel
OUT_CLKPAD_CFB1[0]	bel
OUT_CLKPAD_CFB1[1]	bel
OUT_CLKPAD_DQSP	bel
OUT_CLKPAD_DQSN	bel
IMUX_BUFG[0]	mux
IMUX_BUFG[1]	mux
IMUX_BUFG[2]	mux
IMUX_BUFG[3]	mux
IMUX_BUFG[4]	mux
IMUX_BUFG[5]	mux
IMUX_BUFG[6]	mux
IMUX_BUFG[7]	mux
IMUX_BUFG[8]	mux
IMUX_BUFG[9]	mux
IMUX_BUFG[10]	mux
IMUX_BUFG[11]	mux
IMUX_BUFG[12]	mux
IMUX_BUFG[13]	mux
IMUX_BUFG[14]	mux
IMUX_BUFG[15]	mux
GCLK[0]	regional GLOBAL
GCLK[1]	regional GLOBAL
GCLK[2]	regional GLOBAL
GCLK[3]	regional GLOBAL
GCLK[4]	regional GLOBAL
GCLK[5]	regional GLOBAL
GCLK[6]	regional GLOBAL
GCLK[7]	regional GLOBAL
GCLK[8]	regional GLOBAL
GCLK[9]	regional GLOBAL
GCLK[10]	regional GLOBAL
GCLK[11]	regional GLOBAL
GCLK[12]	regional GLOBAL
GCLK[13]	regional GLOBAL
GCLK[14]	regional GLOBAL
GCLK[15]	regional GLOBAL
HCLK_ROW[0]	regional HROW
HCLK_ROW[1]	regional HROW
HCLK_ROW[2]	regional HROW
HCLK_ROW[3]	regional HROW
HCLK_ROW[4]	regional HROW
HCLK_ROW[5]	regional HROW
HCLK_ROW[6]	regional HROW
HCLK_ROW[7]	regional HROW
HCLK_ROW[8]	regional HROW
HCLK_ROW[9]	regional HROW
HCLK_ROW[10]	regional HROW
HCLK_ROW[11]	regional HROW
HCLK_ROW[12]	regional HROW
HCLK_ROW[13]	regional HROW
HCLK_ROW[14]	regional HROW
HCLK_ROW[15]	regional HROW
CMT_OUT[0]	mux
CMT_OUT[1]	mux
CMT_OUT[2]	mux
CMT_OUT[3]	mux
CMT_OUT[4]	mux
CMT_OUT[5]	mux
CMT_OUT[6]	mux
CMT_OUT[7]	mux
CMT_OUT[8]	mux
CMT_OUT[9]	mux
CMT_OUT[10]	mux
CMT_OUT[11]	mux
CMT_OUT[12]	mux
CMT_OUT[13]	mux
CMT_OUT[14]	mux
CMT_OUT[15]	mux
CMT_CLKC_O[0]	mux
CMT_CLKC_O[1]	mux
CMT_CLKC_O[2]	mux
CMT_CLKC_O[3]	mux
CMT_CLKC_O[4]	mux
CMT_CLKC_O[5]	mux
CMT_CLKC_O[6]	mux
CMT_CLKC_O[7]	mux
CMT_CLKC_O[8]	mux
CMT_CLKC_O[9]	mux
CMT_CLKC_O[10]	mux
CMT_CLKC_O[11]	mux
CMT_CLKC_O[12]	mux
CMT_CLKC_O[13]	mux
CMT_CLKC_O[14]	mux
CMT_CLKC_O[15]	mux
CMT_CLKC_I[0]	branch CMT_PREV
CMT_CLKC_I[1]	branch CMT_PREV
CMT_CLKC_I[2]	branch CMT_PREV
CMT_CLKC_I[3]	branch CMT_PREV
CMT_CLKC_I[4]	branch CMT_PREV
CMT_CLKC_I[5]	branch CMT_PREV
CMT_CLKC_I[6]	branch CMT_PREV
CMT_CLKC_I[7]	branch CMT_PREV
CMT_CLKC_I[8]	branch CMT_PREV
CMT_CLKC_I[9]	branch CMT_PREV
CMT_CLKC_I[10]	branch CMT_PREV
CMT_CLKC_I[11]	branch CMT_PREV
CMT_CLKC_I[12]	branch CMT_PREV
CMT_CLKC_I[13]	branch CMT_PREV
CMT_CLKC_I[14]	branch CMT_PREV
CMT_CLKC_I[15]	branch CMT_PREV
CMT_BUFPLL_H_CLKOUT[0]	mux
CMT_BUFPLL_H_CLKOUT[1]	mux
CMT_BUFPLL_H_LOCKED[0]	mux
CMT_BUFPLL_H_LOCKED[1]	mux
CMT_BUFPLL_V_CLKOUT_S[0]	multi_root
CMT_BUFPLL_V_CLKOUT_S[1]	multi_root
CMT_BUFPLL_V_CLKOUT_S[2]	multi_root
CMT_BUFPLL_V_CLKOUT_S[3]	multi_root
CMT_BUFPLL_V_CLKOUT_S[4]	multi_root
CMT_BUFPLL_V_CLKOUT_S[5]	multi_root
CMT_BUFPLL_V_CLKOUT_N[0]	multi_branch CMT_N
CMT_BUFPLL_V_CLKOUT_N[1]	multi_branch CMT_N
CMT_BUFPLL_V_CLKOUT_N[2]	multi_branch CMT_N
CMT_BUFPLL_V_CLKOUT_N[3]	multi_branch CMT_N
CMT_BUFPLL_V_CLKOUT_N[4]	multi_branch CMT_N
CMT_BUFPLL_V_CLKOUT_N[5]	multi_branch CMT_N
CMT_BUFPLL_V_LOCKED_S[0]	multi_root
CMT_BUFPLL_V_LOCKED_S[1]	multi_root
CMT_BUFPLL_V_LOCKED_S[2]	multi_root
CMT_BUFPLL_V_LOCKED_N[0]	multi_branch CMT_N
CMT_BUFPLL_V_LOCKED_N[1]	multi_branch CMT_N
CMT_BUFPLL_V_LOCKED_N[2]	multi_branch CMT_N
IMUX_BUFPLL_PLLIN[0]	mux
IMUX_BUFPLL_PLLIN[1]	mux
IMUX_BUFPLL_LOCKED[0]	mux
IMUX_BUFPLL_LOCKED[1]	mux
IMUX_DCM_CLKIN[0]	mux
IMUX_DCM_CLKIN[1]	mux
IMUX_DCM_CLKFB[0]	mux
IMUX_DCM_CLKFB[1]	mux
OMUX_DCM_SKEWCLKIN1[0]	mux
OMUX_DCM_SKEWCLKIN1[1]	mux
OMUX_DCM_SKEWCLKIN2[0]	mux
OMUX_DCM_SKEWCLKIN2[1]	mux
OUT_DCM_CLK0[0]	bel
OUT_DCM_CLK0[1]	bel
OUT_DCM_CLK90[0]	bel
OUT_DCM_CLK90[1]	bel
OUT_DCM_CLK180[0]	bel
OUT_DCM_CLK180[1]	bel
OUT_DCM_CLK270[0]	bel
OUT_DCM_CLK270[1]	bel
OUT_DCM_CLK2X[0]	bel
OUT_DCM_CLK2X[1]	bel
OUT_DCM_CLK2X180[0]	bel
OUT_DCM_CLK2X180[1]	bel
OUT_DCM_CLKDV[0]	bel
OUT_DCM_CLKDV[1]	bel
OUT_DCM_CLKFX[0]	bel
OUT_DCM_CLKFX[1]	bel
OUT_DCM_CLKFX180[0]	bel
OUT_DCM_CLKFX180[1]	bel
OUT_DCM_CONCUR[0]	bel
OUT_DCM_CONCUR[1]	bel
IMUX_PLL_CLKIN1	mux
IMUX_PLL_CLKIN2	mux
IMUX_PLL_CLKFB	mux
TEST_PLL_CLKIN	bel
OMUX_PLL_SKEWCLKIN1	mux
OMUX_PLL_SKEWCLKIN2	mux
OUT_PLL_CLKOUT[0]	bel
OUT_PLL_CLKOUT[1]	bel
OUT_PLL_CLKOUT[2]	bel
OUT_PLL_CLKOUT[3]	bel
OUT_PLL_CLKOUT[4]	bel
OUT_PLL_CLKOUT[5]	bel
OUT_PLL_CLKOUTDCM[0]	bel
OUT_PLL_CLKOUTDCM[1]	bel
OUT_PLL_CLKOUTDCM[2]	bel
OUT_PLL_CLKOUTDCM[3]	bel
OUT_PLL_CLKOUTDCM[4]	bel
OUT_PLL_CLKOUTDCM[5]	bel
OUT_PLL_CLKFBOUT	bel
OUT_PLL_CLKFBDCM	bel
OUT_PLL_LOCKED	bel
OMUX_PLL_SKEWCLKIN1_BUF	mux
OMUX_PLL_SKEWCLKIN2_BUF	mux
CMT_TEST_CLK	mux
IOI_IOCLK[0]	mux
IOI_IOCLK[1]	mux
IOI_IOCLK[2]	mux
IOI_IOCLK[3]	mux
IOI_IOCLK[4]	mux
IOI_IOCLK[5]	mux
IOI_IOCLK_OPTINV[0]	mux
IOI_IOCLK_OPTINV[1]	mux
IOI_IOCLK_OPTINV[2]	mux
IOI_IOCLK_OPTINV[3]	mux
IOI_IOCLK_OPTINV[4]	mux
IOI_IOCLK_OPTINV[5]	mux
IOI_IOCE[0]	mux
IOI_IOCE[1]	mux
IOI_IOCE[2]	mux
IOI_IOCE[3]	mux
OUT_DDR_IOCLK[0]	bel
OUT_DDR_IOCLK[1]	bel
OUT_DDR_IOCE[0]	bel
OUT_DDR_IOCE[1]	bel
IOI_ICLK[0]	mux
IOI_ICLK[1]	mux
IOI_OCLK[0]	mux
IOI_OCLK[1]	mux
IMUX_ILOGIC_CLK[0]	mux
IMUX_ILOGIC_CLK[1]	mux
IMUX_OLOGIC_CLK[0]	mux
IMUX_OLOGIC_CLK[1]	mux
IMUX_IODELAY_IOCLK[0]	mux
IMUX_IODELAY_IOCLK[1]	mux
IMUX_ILOGIC_IOCE[0]	mux
IMUX_ILOGIC_IOCE[1]	mux
IMUX_OLOGIC_IOCE[0]	mux
IMUX_OLOGIC_IOCE[1]	mux

Connectors — W

spartan6 wires
Wire	PASS_W	TERM_W
SNG_E1[0]	→ SNG_E0[0]	← SNG_W0[0]
SNG_E1[1]	→ SNG_E0[1]	← SNG_W0[1]
SNG_E1[2]	→ SNG_E0[2]	← SNG_W0[2]
SNG_E1[3]	→ SNG_E0[3]	← SNG_W0[3]
SNG_E1[4]	→ SNG_E0[4]	← SNG_W0[4]
SNG_E1[5]	→ SNG_E0[5]	← SNG_W0[5]
SNG_E1[6]	→ SNG_E0[6]	← SNG_W0[6]
SNG_E1[7]	→ SNG_E0[7]	← SNG_W0[7]
DBL_EE1[0]	→ DBL_EE0[0]	← DBL_WW0[0]
DBL_EE1[1]	→ DBL_EE0[1]	← DBL_WW0[1]
DBL_EE1[2]	→ DBL_EE0[2]	← DBL_WW0[2]
DBL_EE1[3]	→ DBL_EE0[3]	← DBL_WW0[3]
DBL_EE2[0]	→ DBL_EE1[0]	← DBL_WW1[0]
DBL_EE2[1]	→ DBL_EE1[1]	← DBL_WW1[1]
DBL_EE2[2]	→ DBL_EE1[2]	← DBL_WW1[2]
DBL_EE2[3]	→ DBL_EE1[3]	← DBL_WW1[3]
DBL_SE2[0]	→ DBL_SE1[0]	← DBL_SW1[0]
DBL_SE2[1]	→ DBL_SE1[1]	← DBL_SW1[1]
DBL_SE2[2]	→ DBL_SE1[2]	← DBL_SW1[2]
DBL_SE2[3]	→ DBL_SE1[3]	← DBL_SW1[3]
DBL_NE2[0]	→ DBL_NE1[0]	← DBL_NW1[0]
DBL_NE2[1]	→ DBL_NE1[1]	← DBL_NW1[1]
DBL_NE2[2]	→ DBL_NE1[2]	← DBL_NW1[2]
DBL_NE2[3]	→ DBL_NE1[3]	← DBL_NW1[3]
QUAD_EE1[0]	→ QUAD_EE0[0]	← QUAD_WW0[0]
QUAD_EE1[1]	→ QUAD_EE0[1]	← QUAD_WW0[1]
QUAD_EE1[2]	→ QUAD_EE0[2]	← QUAD_WW0[2]
QUAD_EE1[3]	→ QUAD_EE0[3]	← QUAD_WW0[3]
QUAD_EE2[0]	→ QUAD_EE1[0]	← QUAD_WW1[0]
QUAD_EE2[1]	→ QUAD_EE1[1]	← QUAD_WW1[1]
QUAD_EE2[2]	→ QUAD_EE1[2]	← QUAD_WW1[2]
QUAD_EE2[3]	→ QUAD_EE1[3]	← QUAD_WW1[3]
QUAD_EE3[0]	→ QUAD_EE2[0]	← QUAD_WW2[0]
QUAD_EE3[1]	→ QUAD_EE2[1]	← QUAD_WW2[1]
QUAD_EE3[2]	→ QUAD_EE2[2]	← QUAD_WW2[2]
QUAD_EE3[3]	→ QUAD_EE2[3]	← QUAD_WW2[3]
QUAD_EE4[0]	→ QUAD_EE3[0]	← QUAD_WW3[0]
QUAD_EE4[1]	→ QUAD_EE3[1]	← QUAD_WW3[1]
QUAD_EE4[2]	→ QUAD_EE3[2]	← QUAD_WW3[2]
QUAD_EE4[3]	→ QUAD_EE3[3]	← QUAD_WW3[3]
QUAD_SE3[0]	→ QUAD_SE2[0]	← QUAD_SW2[0]
QUAD_SE3[1]	→ QUAD_SE2[1]	← QUAD_SW2[1]
QUAD_SE3[2]	→ QUAD_SE2[2]	← QUAD_SW2[2]
QUAD_SE3[3]	→ QUAD_SE2[3]	← QUAD_SW2[3]
QUAD_SE4[0]	→ QUAD_SE3[0]	← QUAD_SW3[0]
QUAD_SE4[1]	→ QUAD_SE3[1]	← QUAD_SW3[1]
QUAD_SE4[2]	→ QUAD_SE3[2]	← QUAD_SW3[2]
QUAD_SE4[3]	→ QUAD_SE3[3]	← QUAD_SW3[3]
QUAD_NE3[0]	→ QUAD_NE2[0]	-
QUAD_NE3[1]	→ QUAD_NE2[1]	-
QUAD_NE3[2]	→ QUAD_NE2[2]	-
QUAD_NE3[3]	→ QUAD_NE2[3]	-
QUAD_NE4[0]	→ QUAD_NE3[0]	← QUAD_NW3[0]
QUAD_NE4[1]	→ QUAD_NE3[1]	← QUAD_NW3[1]
QUAD_NE4[2]	→ QUAD_NE3[2]	← QUAD_NW3[2]
QUAD_NE4[3]	→ QUAD_NE3[3]	← QUAD_NW3[3]

Connectors — E

spartan6 wires
Wire	PASS_E	TERM_E
SNG_W1[0]	→ SNG_W0[0]	← SNG_E0[0]
SNG_W1[1]	→ SNG_W0[1]	← SNG_E0[1]
SNG_W1[2]	→ SNG_W0[2]	← SNG_E0[2]
SNG_W1[3]	→ SNG_W0[3]	← SNG_E0[3]
SNG_W1[4]	→ SNG_W0[4]	← SNG_E0[4]
SNG_W1[5]	→ SNG_W0[5]	← SNG_E0[5]
SNG_W1[6]	→ SNG_W0[6]	← SNG_E0[6]
SNG_W1[7]	→ SNG_W0[7]	← SNG_E0[7]
DBL_WW1[0]	→ DBL_WW0[0]	← DBL_EE0[0]
DBL_WW1[1]	→ DBL_WW0[1]	← DBL_EE0[1]
DBL_WW1[2]	→ DBL_WW0[2]	← DBL_EE0[2]
DBL_WW1[3]	→ DBL_WW0[3]	← DBL_EE0[3]
DBL_WW2[0]	→ DBL_WW1[0]	← DBL_EE1[0]
DBL_WW2[1]	→ DBL_WW1[1]	← DBL_EE1[1]
DBL_WW2[2]	→ DBL_WW1[2]	← DBL_EE1[2]
DBL_WW2[3]	→ DBL_WW1[3]	← DBL_EE1[3]
DBL_SW2[0]	→ DBL_SW1[0]	← DBL_SE1[0]
DBL_SW2[1]	→ DBL_SW1[1]	← DBL_SE1[1]
DBL_SW2[2]	→ DBL_SW1[2]	← DBL_SE1[2]
DBL_SW2[3]	→ DBL_SW1[3]	← DBL_SE1[3]
DBL_NW2[0]	→ DBL_NW1[0]	← DBL_NE1[0]
DBL_NW2[1]	→ DBL_NW1[1]	← DBL_NE1[1]
DBL_NW2[2]	→ DBL_NW1[2]	← DBL_NE1[2]
DBL_NW2[3]	→ DBL_NW1[3]	← DBL_NE1[3]
QUAD_WW1[0]	→ QUAD_WW0[0]	← QUAD_EE0[0]
QUAD_WW1[1]	→ QUAD_WW0[1]	← QUAD_EE0[1]
QUAD_WW1[2]	→ QUAD_WW0[2]	← QUAD_EE0[2]
QUAD_WW1[3]	→ QUAD_WW0[3]	← QUAD_EE0[3]
QUAD_WW2[0]	→ QUAD_WW1[0]	← QUAD_EE1[0]
QUAD_WW2[1]	→ QUAD_WW1[1]	← QUAD_EE1[1]
QUAD_WW2[2]	→ QUAD_WW1[2]	← QUAD_EE1[2]
QUAD_WW2[3]	→ QUAD_WW1[3]	← QUAD_EE1[3]
QUAD_WW3[0]	→ QUAD_WW2[0]	← QUAD_EE2[0]
QUAD_WW3[1]	→ QUAD_WW2[1]	← QUAD_EE2[1]
QUAD_WW3[2]	→ QUAD_WW2[2]	← QUAD_EE2[2]
QUAD_WW3[3]	→ QUAD_WW2[3]	← QUAD_EE2[3]
QUAD_WW4[0]	→ QUAD_WW3[0]	← QUAD_EE3[0]
QUAD_WW4[1]	→ QUAD_WW3[1]	← QUAD_EE3[1]
QUAD_WW4[2]	→ QUAD_WW3[2]	← QUAD_EE3[2]
QUAD_WW4[3]	→ QUAD_WW3[3]	← QUAD_EE3[3]
QUAD_SW3[0]	→ QUAD_SW2[0]	← QUAD_SE2[0]
QUAD_SW3[1]	→ QUAD_SW2[1]	← QUAD_SE2[1]
QUAD_SW3[2]	→ QUAD_SW2[2]	← QUAD_SE2[2]
QUAD_SW3[3]	→ QUAD_SW2[3]	← QUAD_SE2[3]
QUAD_SW4[0]	→ QUAD_SW3[0]	← QUAD_SE3[0]
QUAD_SW4[1]	→ QUAD_SW3[1]	← QUAD_SE3[1]
QUAD_SW4[2]	→ QUAD_SW3[2]	← QUAD_SE3[2]
QUAD_SW4[3]	→ QUAD_SW3[3]	← QUAD_SE3[3]
QUAD_NW3[0]	→ QUAD_NW2[0]	← QUAD_NE2[0]
QUAD_NW3[1]	→ QUAD_NW2[1]	← QUAD_NE2[1]
QUAD_NW3[2]	→ QUAD_NW2[2]	← QUAD_NE2[2]
QUAD_NW3[3]	→ QUAD_NW2[3]	← QUAD_NE2[3]
QUAD_NW4[0]	→ QUAD_NW3[0]	← QUAD_NE3[0]
QUAD_NW4[1]	→ QUAD_NW3[1]	← QUAD_NE3[1]
QUAD_NW4[2]	→ QUAD_NW3[2]	← QUAD_NE3[2]
QUAD_NW4[3]	→ QUAD_NW3[3]	← QUAD_NE3[3]

Connectors — S

spartan6 wires
Wire	PASS_S	TERM_S
SNG_W1_N3	→ SNG_W1[3]	← SNG_W1[4]
SNG_E1_N7	→ SNG_E1[7]	← SNG_E1[0]
SNG_S1_N7	→ SNG_S1[7]	← SNG_N1[0]
SNG_N1[0]	→ SNG_N0[0]	-
SNG_N1[1]	→ SNG_N0[1]	-
SNG_N1[2]	→ SNG_N0[2]	-
SNG_N1[3]	→ SNG_N0[3]	-
SNG_N1[4]	→ SNG_N0[4]	← SNG_S0[4]
SNG_N1[5]	→ SNG_N0[5]	← SNG_S0[5]
SNG_N1[6]	→ SNG_N0[6]	← SNG_S0[6]
SNG_N1[7]	→ SNG_N0[7]	← SNG_S0[7]
DBL_WW2_N3	→ DBL_WW2[3]	← DBL_NW2[0]
DBL_SS2_N3	→ DBL_SS2[3]	← DBL_NN2[0]
DBL_SW2_N3	→ DBL_SW2[3]	← DBL_NE2[0]
DBL_NN1[0]	→ DBL_NN0[0]	← DBL_SS0[0]
DBL_NN1[1]	→ DBL_NN0[1]	← DBL_SS0[1]
DBL_NN1[2]	→ DBL_NN0[2]	← DBL_SS0[2]
DBL_NN1[3]	→ DBL_NN0[3]	← DBL_SS0[3]
DBL_NN2[0]	→ DBL_NN1[0]	← DBL_SS1[0]
DBL_NN2[1]	→ DBL_NN1[1]	← DBL_SS1[1]
DBL_NN2[2]	→ DBL_NN1[2]	← DBL_SS1[2]
DBL_NN2[3]	→ DBL_NN1[3]	← DBL_SS1[3]
DBL_NW1[0]	→ DBL_NW0[0]	← DBL_SW0[0]
DBL_NW1[1]	→ DBL_NW0[1]	← DBL_SW0[1]
DBL_NW1[2]	→ DBL_NW0[2]	← DBL_SW0[2]
DBL_NW1[3]	→ DBL_NW0[3]	← DBL_SW0[3]
DBL_NE1[0]	→ DBL_NE0[0]	← DBL_SE0[0]
DBL_NE1[1]	→ DBL_NE0[1]	← DBL_SE0[1]
DBL_NE1[2]	→ DBL_NE0[2]	← DBL_SE0[2]
DBL_NE1[3]	→ DBL_NE0[3]	← DBL_SE0[3]
QUAD_SS4_N3	→ QUAD_SS4[3]	← QUAD_NW4[0]
QUAD_SW4_N3	→ QUAD_SW4[3]	← QUAD_WW4[0]
QUAD_NN1[0]	→ QUAD_NN0[0]	← QUAD_SS0[0]
QUAD_NN1[1]	→ QUAD_NN0[1]	← QUAD_SS0[1]
QUAD_NN1[2]	→ QUAD_NN0[2]	← QUAD_SS0[2]
QUAD_NN1[3]	→ QUAD_NN0[3]	← QUAD_SS0[3]
QUAD_NN2[0]	→ QUAD_NN1[0]	← QUAD_SS1[0]
QUAD_NN2[1]	→ QUAD_NN1[1]	← QUAD_SS1[1]
QUAD_NN2[2]	→ QUAD_NN1[2]	← QUAD_SS1[2]
QUAD_NN2[3]	→ QUAD_NN1[3]	← QUAD_SS1[3]
QUAD_NN3[0]	→ QUAD_NN2[0]	← QUAD_SS2[0]
QUAD_NN3[1]	→ QUAD_NN2[1]	← QUAD_SS2[1]
QUAD_NN3[2]	→ QUAD_NN2[2]	← QUAD_SS2[2]
QUAD_NN3[3]	→ QUAD_NN2[3]	← QUAD_SS2[3]
QUAD_NN4[0]	→ QUAD_NN3[0]	← QUAD_SS3[0]
QUAD_NN4[1]	→ QUAD_NN3[1]	← QUAD_SS3[1]
QUAD_NN4[2]	→ QUAD_NN3[2]	← QUAD_SS3[2]
QUAD_NN4[3]	→ QUAD_NN3[3]	← QUAD_SS3[3]
QUAD_NW1[0]	→ QUAD_NW0[0]	← QUAD_SW0[0]
QUAD_NW1[1]	→ QUAD_NW0[1]	← QUAD_SW0[1]
QUAD_NW1[2]	→ QUAD_NW0[2]	← QUAD_SW0[2]
QUAD_NW1[3]	→ QUAD_NW0[3]	← QUAD_SW0[3]
QUAD_NW2[0]	→ QUAD_NW1[0]	← QUAD_SW1[0]
QUAD_NW2[1]	→ QUAD_NW1[1]	← QUAD_SW1[1]
QUAD_NW2[2]	→ QUAD_NW1[2]	← QUAD_SW1[2]
QUAD_NW2[3]	→ QUAD_NW1[3]	← QUAD_SW1[3]
QUAD_NE1[0]	→ QUAD_NE0[0]	← QUAD_SE0[0]
QUAD_NE1[1]	→ QUAD_NE0[1]	← QUAD_SE0[1]
QUAD_NE1[2]	→ QUAD_NE0[2]	← QUAD_SE0[2]
QUAD_NE1[3]	→ QUAD_NE0[3]	← QUAD_SE0[3]
QUAD_NE2[0]	→ QUAD_NE1[0]	← QUAD_SE1[0]
QUAD_NE2[1]	→ QUAD_NE1[1]	← QUAD_SE1[1]
QUAD_NE2[2]	→ QUAD_NE1[2]	← QUAD_SE1[2]
QUAD_NE2[3]	→ QUAD_NE1[3]	← QUAD_SE1[3]
IMUX_LOGICIN21_N	→ IMUX_LOGICIN21_BOUNCE	← IMUX_LOGICIN20_BOUNCE
IMUX_LOGICIN28_N	→ IMUX_LOGICIN28_BOUNCE	← IMUX_LOGICIN36_BOUNCE
IMUX_LOGICIN52_N	→ IMUX_LOGICIN52_BOUNCE	← IMUX_LOGICIN44_BOUNCE
IMUX_LOGICIN60_N	→ IMUX_LOGICIN60_BOUNCE	← IMUX_LOGICIN62_BOUNCE

Connectors — N

spartan6 wires
Wire	PASS_N	TERM_N
SNG_W1_S4	→ SNG_W1[4]	← SNG_W1[3]
SNG_E1_S0	→ SNG_E1[0]	← SNG_E1[7]
SNG_S1[0]	→ SNG_S0[0]	← SNG_N0[0]
SNG_S1[1]	→ SNG_S0[1]	← SNG_N0[1]
SNG_S1[2]	→ SNG_S0[2]	← SNG_N0[2]
SNG_S1[3]	→ SNG_S0[3]	← SNG_N0[3]
SNG_S1[4]	→ SNG_S0[4]	← SNG_N0[4]
SNG_S1[5]	→ SNG_S0[5]	← SNG_N0[5]
SNG_S1[6]	→ SNG_S0[6]	← SNG_N0[6]
SNG_S1[7]	→ SNG_S0[7]	← SNG_N0[7]
SNG_N1_S0	→ SNG_N1[0]	← SNG_S1[7]
DBL_SS1[0]	→ DBL_SS0[0]	← DBL_NN0[0]
DBL_SS1[1]	→ DBL_SS0[1]	← DBL_NN0[1]
DBL_SS1[2]	→ DBL_SS0[2]	← DBL_NN0[2]
DBL_SS1[3]	→ DBL_SS0[3]	← DBL_NN0[3]
DBL_SS2[0]	→ DBL_SS1[0]	← DBL_NN1[0]
DBL_SS2[1]	→ DBL_SS1[1]	← DBL_NN1[1]
DBL_SS2[2]	→ DBL_SS1[2]	← DBL_NN1[2]
DBL_SS2[3]	→ DBL_SS1[3]	← DBL_NN1[3]
DBL_SW1[0]	→ DBL_SW0[0]	← DBL_NW0[0]
DBL_SW1[1]	→ DBL_SW0[1]	← DBL_NW0[1]
DBL_SW1[2]	→ DBL_SW0[2]	← DBL_NW0[2]
DBL_SW1[3]	→ DBL_SW0[3]	← DBL_NW0[3]
DBL_SE1[0]	→ DBL_SE0[0]	← DBL_NE0[0]
DBL_SE1[1]	→ DBL_SE0[1]	← DBL_NE0[1]
DBL_SE1[2]	→ DBL_SE0[2]	← DBL_NE0[2]
DBL_SE1[3]	→ DBL_SE0[3]	← DBL_NE0[3]
DBL_NN2_S0	→ DBL_NN2[0]	← DBL_SS2[3]
DBL_NW2_S0	→ DBL_NW2[0]	← DBL_WW2[3]
DBL_NE2_S0	→ DBL_NE2[0]	← DBL_SW2[3]
QUAD_WW4_S0	→ QUAD_WW4[0]	← QUAD_SW4[3]
QUAD_SS1[0]	→ QUAD_SS0[0]	← QUAD_NN0[0]
QUAD_SS1[1]	→ QUAD_SS0[1]	← QUAD_NN0[1]
QUAD_SS1[2]	→ QUAD_SS0[2]	← QUAD_NN0[2]
QUAD_SS1[3]	→ QUAD_SS0[3]	← QUAD_NN0[3]
QUAD_SS2[0]	→ QUAD_SS1[0]	← QUAD_NN1[0]
QUAD_SS2[1]	→ QUAD_SS1[1]	← QUAD_NN1[1]
QUAD_SS2[2]	→ QUAD_SS1[2]	← QUAD_NN1[2]
QUAD_SS2[3]	→ QUAD_SS1[3]	← QUAD_NN1[3]
QUAD_SS3[0]	→ QUAD_SS2[0]	← QUAD_NN2[0]
QUAD_SS3[1]	→ QUAD_SS2[1]	← QUAD_NN2[1]
QUAD_SS3[2]	→ QUAD_SS2[2]	← QUAD_NN2[2]
QUAD_SS3[3]	→ QUAD_SS2[3]	← QUAD_NN2[3]
QUAD_SS4[0]	→ QUAD_SS3[0]	← QUAD_NN3[0]
QUAD_SS4[1]	→ QUAD_SS3[1]	← QUAD_NN3[1]
QUAD_SS4[2]	→ QUAD_SS3[2]	← QUAD_NN3[2]
QUAD_SS4[3]	→ QUAD_SS3[3]	← QUAD_NN3[3]
QUAD_SW1[0]	→ QUAD_SW0[0]	← QUAD_NW0[0]
QUAD_SW1[1]	→ QUAD_SW0[1]	← QUAD_NW0[1]
QUAD_SW1[2]	→ QUAD_SW0[2]	← QUAD_NW0[2]
QUAD_SW1[3]	→ QUAD_SW0[3]	← QUAD_NW0[3]
QUAD_SW2[0]	→ QUAD_SW1[0]	← QUAD_NW1[0]
QUAD_SW2[1]	→ QUAD_SW1[1]	← QUAD_NW1[1]
QUAD_SW2[2]	→ QUAD_SW1[2]	← QUAD_NW1[2]
QUAD_SW2[3]	→ QUAD_SW1[3]	← QUAD_NW1[3]
QUAD_SE1[0]	→ QUAD_SE0[0]	← QUAD_NE0[0]
QUAD_SE1[1]	→ QUAD_SE0[1]	← QUAD_NE0[1]
QUAD_SE1[2]	→ QUAD_SE0[2]	← QUAD_NE0[2]
QUAD_SE1[3]	→ QUAD_SE0[3]	← QUAD_NE0[3]
QUAD_SE2[0]	→ QUAD_SE1[0]	← QUAD_NE1[0]
QUAD_SE2[1]	→ QUAD_SE1[1]	← QUAD_NE1[1]
QUAD_SE2[2]	→ QUAD_SE1[2]	← QUAD_NE1[2]
QUAD_SE2[3]	→ QUAD_SE1[3]	← QUAD_NE1[3]
QUAD_NW4_S0	→ QUAD_NW4[0]	← QUAD_SS4[3]
IMUX_LOGICIN20_S	→ IMUX_LOGICIN20_BOUNCE	← IMUX_LOGICIN21_BOUNCE
IMUX_LOGICIN36_S	→ IMUX_LOGICIN36_BOUNCE	← IMUX_LOGICIN28_BOUNCE
IMUX_LOGICIN44_S	→ IMUX_LOGICIN44_BOUNCE	← IMUX_LOGICIN52_BOUNCE
IMUX_LOGICIN62_S	→ IMUX_LOGICIN62_BOUNCE	← IMUX_LOGICIN60_BOUNCE

Connectors — CMT_PREV

spartan6 wires
Wire	CMT_PREV
CMT_CLKC_I[0]	→ CMT_CLKC_O[0]
CMT_CLKC_I[1]	→ CMT_CLKC_O[1]
CMT_CLKC_I[2]	→ CMT_CLKC_O[2]
CMT_CLKC_I[3]	→ CMT_CLKC_O[3]
CMT_CLKC_I[4]	→ CMT_CLKC_O[4]
CMT_CLKC_I[5]	→ CMT_CLKC_O[5]
CMT_CLKC_I[6]	→ CMT_CLKC_O[6]
CMT_CLKC_I[7]	→ CMT_CLKC_O[7]
CMT_CLKC_I[8]	→ CMT_CLKC_O[8]
CMT_CLKC_I[9]	→ CMT_CLKC_O[9]
CMT_CLKC_I[10]	→ CMT_CLKC_O[10]
CMT_CLKC_I[11]	→ CMT_CLKC_O[11]
CMT_CLKC_I[12]	→ CMT_CLKC_O[12]
CMT_CLKC_I[13]	→ CMT_CLKC_O[13]
CMT_CLKC_I[14]	→ CMT_CLKC_O[14]
CMT_CLKC_I[15]	→ CMT_CLKC_O[15]

Connectors — CMT_NEXT

spartan6 wires
Wire	CMT_NEXT

Connectors — CMT_S

spartan6 wires
Wire	CMT_S

Connectors — CMT_N

spartan6 wires
Wire	CMT_N
CMT_BUFPLL_V_CLKOUT_N[0]	→ CMT_BUFPLL_V_CLKOUT_S[0]
CMT_BUFPLL_V_CLKOUT_N[1]	→ CMT_BUFPLL_V_CLKOUT_S[1]
CMT_BUFPLL_V_CLKOUT_N[2]	→ CMT_BUFPLL_V_CLKOUT_S[2]
CMT_BUFPLL_V_CLKOUT_N[3]	→ CMT_BUFPLL_V_CLKOUT_S[3]
CMT_BUFPLL_V_CLKOUT_N[4]	→ CMT_BUFPLL_V_CLKOUT_S[4]
CMT_BUFPLL_V_CLKOUT_N[5]	→ CMT_BUFPLL_V_CLKOUT_S[5]
CMT_BUFPLL_V_LOCKED_N[0]	→ CMT_BUFPLL_V_LOCKED_S[0]
CMT_BUFPLL_V_LOCKED_N[1]	→ CMT_BUFPLL_V_LOCKED_S[1]
CMT_BUFPLL_V_LOCKED_N[2]	→ CMT_BUFPLL_V_LOCKED_S[2]

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