Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Interconnect tiles

Tile INT

Cells: 1

Switchbox INT

spartan6 INT switchbox INT permanent buffers
DestinationSource
IMUX_LOGICIN20_BOUNCEIMUX_LOGICIN[20]
IMUX_LOGICIN36_BOUNCEIMUX_LOGICIN[36]
IMUX_LOGICIN44_BOUNCEIMUX_LOGICIN[44]
IMUX_LOGICIN62_BOUNCEIMUX_LOGICIN[62]
IMUX_LOGICIN21_BOUNCEIMUX_LOGICIN[21]
IMUX_LOGICIN28_BOUNCEIMUX_LOGICIN[28]
IMUX_LOGICIN52_BOUNCEIMUX_LOGICIN[52]
IMUX_LOGICIN60_BOUNCEIMUX_LOGICIN[60]
spartan6 INT switchbox INT muxes SNG_W0[0]
BitsDestination
MAIN[8][24]MAIN[9][24]MAIN[9][26]MAIN[9][25]MAIN[9][30]MAIN[9][29]MAIN[9][28]MAIN[9][27]SNG_W0[0]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes SNG_W0[1]
BitsDestination
MAIN[8][40]MAIN[9][40]MAIN[9][42]MAIN[9][41]MAIN[9][46]MAIN[9][45]MAIN[9][44]MAIN[9][43]SNG_W0[1]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes SNG_W0[2]
BitsDestination
MAIN[8][56]MAIN[9][56]MAIN[9][58]MAIN[9][57]MAIN[9][62]MAIN[9][61]MAIN[9][60]MAIN[9][59]SNG_W0[2]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes SNG_W0[3]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[9][10]MAIN[9][9]MAIN[9][14]MAIN[9][13]MAIN[9][12]MAIN[9][11]SNG_W0[3]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes SNG_W0[4]
BitsDestination
MAIN[8][55]MAIN[9][55]MAIN[9][54]MAIN[9][53]MAIN[9][50]MAIN[9][49]MAIN[9][51]MAIN[9][52]SNG_W0[4]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes SNG_W0[5]
BitsDestination
MAIN[8][7]MAIN[9][7]MAIN[9][6]MAIN[9][5]MAIN[9][2]MAIN[9][1]MAIN[9][4]MAIN[9][3]SNG_W0[5]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes SNG_W0[6]
BitsDestination
MAIN[8][23]MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[9][18]MAIN[9][17]MAIN[9][19]MAIN[9][20]SNG_W0[6]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes SNG_W0[7]
BitsDestination
MAIN[8][39]MAIN[9][39]MAIN[9][38]MAIN[9][37]MAIN[9][34]MAIN[9][33]MAIN[9][35]MAIN[9][36]SNG_W0[7]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes SNG_E0[0]
BitsDestination
MAIN[10][23]MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][18]MAIN[11][17]MAIN[11][19]MAIN[11][20]SNG_E0[0]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes SNG_E0[1]
BitsDestination
MAIN[10][39]MAIN[11][39]MAIN[11][38]MAIN[11][37]MAIN[11][34]MAIN[11][33]MAIN[11][35]MAIN[11][36]SNG_E0[1]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes SNG_E0[2]
BitsDestination
MAIN[10][55]MAIN[11][55]MAIN[11][54]MAIN[11][53]MAIN[11][50]MAIN[11][49]MAIN[11][51]MAIN[11][52]SNG_E0[2]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes SNG_E0[3]
BitsDestination
MAIN[10][7]MAIN[11][7]MAIN[11][6]MAIN[11][5]MAIN[11][2]MAIN[11][1]MAIN[11][3]MAIN[11][4]SNG_E0[3]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes SNG_E0[4]
BitsDestination
MAIN[10][56]MAIN[11][56]MAIN[11][58]MAIN[11][57]MAIN[11][62]MAIN[11][61]MAIN[11][60]MAIN[11][59]SNG_E0[4]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes SNG_E0[5]
BitsDestination
MAIN[10][8]MAIN[11][8]MAIN[11][10]MAIN[11][9]MAIN[11][14]MAIN[11][13]MAIN[11][12]MAIN[11][11]SNG_E0[5]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes SNG_E0[6]
BitsDestination
MAIN[10][24]MAIN[11][24]MAIN[11][26]MAIN[11][25]MAIN[11][30]MAIN[11][29]MAIN[11][28]MAIN[11][27]SNG_E0[6]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes SNG_E0[7]
BitsDestination
MAIN[10][40]MAIN[11][40]MAIN[11][42]MAIN[11][41]MAIN[11][46]MAIN[11][45]MAIN[11][44]MAIN[11][43]SNG_E0[7]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes SNG_S0[0]
BitsDestination
MAIN[11][15]MAIN[10][15]MAIN[10][10]MAIN[10][9]MAIN[10][14]MAIN[10][13]MAIN[10][12]MAIN[10][11]SNG_S0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes SNG_S0[1]
BitsDestination
MAIN[11][31]MAIN[10][31]MAIN[10][26]MAIN[10][25]MAIN[10][30]MAIN[10][29]MAIN[10][28]MAIN[10][27]SNG_S0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes SNG_S0[2]
BitsDestination
MAIN[11][47]MAIN[10][47]MAIN[10][42]MAIN[10][41]MAIN[10][46]MAIN[10][45]MAIN[10][44]MAIN[10][43]SNG_S0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes SNG_S0[3]
BitsDestination
MAIN[11][63]MAIN[10][63]MAIN[10][58]MAIN[10][57]MAIN[10][62]MAIN[10][61]MAIN[10][60]MAIN[10][59]SNG_S0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes SNG_S0[4]
BitsDestination
MAIN[9][63]MAIN[8][63]MAIN[8][58]MAIN[8][57]MAIN[8][62]MAIN[8][61]MAIN[8][60]MAIN[8][59]SNG_S0[4]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes SNG_S0[5]
BitsDestination
MAIN[9][15]MAIN[8][15]MAIN[8][10]MAIN[8][9]MAIN[8][14]MAIN[8][13]MAIN[8][12]MAIN[8][11]SNG_S0[5]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes SNG_S0[6]
BitsDestination
MAIN[9][31]MAIN[8][31]MAIN[8][26]MAIN[8][25]MAIN[8][30]MAIN[8][29]MAIN[8][28]MAIN[8][27]SNG_S0[6]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes SNG_S0[7]
BitsDestination
MAIN[9][47]MAIN[8][47]MAIN[8][42]MAIN[8][41]MAIN[8][46]MAIN[8][45]MAIN[8][44]MAIN[8][43]SNG_S0[7]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes SNG_N0[0]
BitsDestination
MAIN[9][16]MAIN[8][16]MAIN[8][22]MAIN[8][21]MAIN[8][18]MAIN[8][17]MAIN[8][19]MAIN[8][20]SNG_N0[0]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes SNG_N0[1]
BitsDestination
MAIN[9][32]MAIN[8][32]MAIN[8][38]MAIN[8][37]MAIN[8][34]MAIN[8][33]MAIN[8][35]MAIN[8][36]SNG_N0[1]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes SNG_N0[2]
BitsDestination
MAIN[9][48]MAIN[8][48]MAIN[8][54]MAIN[8][53]MAIN[8][50]MAIN[8][49]MAIN[8][51]MAIN[8][52]SNG_N0[2]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes SNG_N0[3]
BitsDestination
MAIN[9][0]MAIN[8][0]MAIN[8][6]MAIN[8][5]MAIN[8][2]MAIN[8][1]MAIN[8][4]MAIN[8][3]SNG_N0[3]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes SNG_N0[4]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][6]MAIN[10][5]MAIN[10][2]MAIN[10][1]MAIN[10][3]MAIN[10][4]SNG_N0[4]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes SNG_N0[5]
BitsDestination
MAIN[11][16]MAIN[10][16]MAIN[10][22]MAIN[10][21]MAIN[10][18]MAIN[10][17]MAIN[10][19]MAIN[10][20]SNG_N0[5]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes SNG_N0[6]
BitsDestination
MAIN[11][32]MAIN[10][32]MAIN[10][38]MAIN[10][37]MAIN[10][34]MAIN[10][33]MAIN[10][35]MAIN[10][36]SNG_N0[6]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes SNG_N0[7]
BitsDestination
MAIN[11][48]MAIN[10][48]MAIN[10][54]MAIN[10][53]MAIN[10][50]MAIN[10][49]MAIN[10][51]MAIN[10][52]SNG_N0[7]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes DBL_WW0[0]
BitsDestination
MAIN[5][15]MAIN[4][15]MAIN[4][10]MAIN[4][9]MAIN[4][14]MAIN[4][13]MAIN[4][12]MAIN[4][11]DBL_WW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes DBL_WW0[1]
BitsDestination
MAIN[5][31]MAIN[4][31]MAIN[4][26]MAIN[4][25]MAIN[4][30]MAIN[4][29]MAIN[4][28]MAIN[4][27]DBL_WW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes DBL_WW0[2]
BitsDestination
MAIN[5][47]MAIN[4][47]MAIN[4][42]MAIN[4][41]MAIN[4][46]MAIN[4][45]MAIN[4][44]MAIN[4][43]DBL_WW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes DBL_WW0[3]
BitsDestination
MAIN[5][63]MAIN[4][63]MAIN[4][58]MAIN[4][57]MAIN[4][62]MAIN[4][61]MAIN[4][60]MAIN[4][59]DBL_WW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes DBL_EE0[0]
BitsDestination
MAIN[7][0]MAIN[6][0]MAIN[6][6]MAIN[6][5]MAIN[6][2]MAIN[6][1]MAIN[6][3]MAIN[6][4]DBL_EE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes DBL_EE0[1]
BitsDestination
MAIN[7][16]MAIN[6][16]MAIN[6][22]MAIN[6][21]MAIN[6][18]MAIN[6][17]MAIN[6][19]MAIN[6][20]DBL_EE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes DBL_EE0[2]
BitsDestination
MAIN[7][32]MAIN[6][32]MAIN[6][38]MAIN[6][37]MAIN[6][34]MAIN[6][33]MAIN[6][35]MAIN[6][36]DBL_EE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes DBL_EE0[3]
BitsDestination
MAIN[7][48]MAIN[6][48]MAIN[6][54]MAIN[6][53]MAIN[6][50]MAIN[6][49]MAIN[6][51]MAIN[6][52]DBL_EE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes DBL_SS0[0]
BitsDestination
MAIN[7][15]MAIN[6][15]MAIN[6][10]MAIN[6][9]MAIN[6][14]MAIN[6][13]MAIN[6][12]MAIN[6][11]DBL_SS0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes DBL_SS0[1]
BitsDestination
MAIN[7][31]MAIN[6][31]MAIN[6][26]MAIN[6][25]MAIN[6][30]MAIN[6][29]MAIN[6][28]MAIN[6][27]DBL_SS0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes DBL_SS0[2]
BitsDestination
MAIN[7][47]MAIN[6][47]MAIN[6][42]MAIN[6][41]MAIN[6][46]MAIN[6][45]MAIN[6][44]MAIN[6][43]DBL_SS0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes DBL_SS0[3]
BitsDestination
MAIN[7][63]MAIN[6][63]MAIN[6][58]MAIN[6][57]MAIN[6][62]MAIN[6][61]MAIN[6][60]MAIN[6][59]DBL_SS0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes DBL_SW0[0]
BitsDestination
MAIN[4][8]MAIN[5][8]MAIN[5][10]MAIN[5][9]MAIN[5][14]MAIN[5][13]MAIN[5][12]MAIN[5][11]DBL_SW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes DBL_SW0[1]
BitsDestination
MAIN[4][24]MAIN[5][24]MAIN[5][26]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[5][27]DBL_SW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes DBL_SW0[2]
BitsDestination
MAIN[4][40]MAIN[5][40]MAIN[5][42]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[5][43]DBL_SW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes DBL_SW0[3]
BitsDestination
MAIN[4][56]MAIN[5][56]MAIN[5][58]MAIN[5][57]MAIN[5][62]MAIN[5][61]MAIN[5][60]MAIN[5][59]DBL_SW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes DBL_SE0[0]
BitsDestination
MAIN[6][8]MAIN[7][8]MAIN[7][10]MAIN[7][9]MAIN[7][14]MAIN[7][13]MAIN[7][12]MAIN[7][11]DBL_SE0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT switchbox INT muxes DBL_SE0[1]
BitsDestination
MAIN[6][24]MAIN[7][24]MAIN[7][26]MAIN[7][25]MAIN[7][30]MAIN[7][29]MAIN[7][28]MAIN[7][27]DBL_SE0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT switchbox INT muxes DBL_SE0[2]
BitsDestination
MAIN[6][40]MAIN[7][40]MAIN[7][42]MAIN[7][41]MAIN[7][46]MAIN[7][45]MAIN[7][44]MAIN[7][43]DBL_SE0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT switchbox INT muxes DBL_SE0[3]
BitsDestination
MAIN[6][56]MAIN[7][56]MAIN[7][58]MAIN[7][57]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[7][59]DBL_SE0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT switchbox INT muxes DBL_NN0[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[4][6]MAIN[4][5]MAIN[4][2]MAIN[4][1]MAIN[4][4]MAIN[4][3]DBL_NN0[0]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes DBL_NN0[1]
BitsDestination
MAIN[5][16]MAIN[4][16]MAIN[4][22]MAIN[4][21]MAIN[4][18]MAIN[4][17]MAIN[4][19]MAIN[4][20]DBL_NN0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes DBL_NN0[2]
BitsDestination
MAIN[5][32]MAIN[4][32]MAIN[4][38]MAIN[4][37]MAIN[4][34]MAIN[4][33]MAIN[4][35]MAIN[4][36]DBL_NN0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes DBL_NN0[3]
BitsDestination
MAIN[5][48]MAIN[4][48]MAIN[4][54]MAIN[4][53]MAIN[4][50]MAIN[4][49]MAIN[4][51]MAIN[4][52]DBL_NN0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes DBL_NW0[0]
BitsDestination
MAIN[4][7]MAIN[5][7]MAIN[5][6]MAIN[5][5]MAIN[5][2]MAIN[5][1]MAIN[5][4]MAIN[5][3]DBL_NW0[0]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes DBL_NW0[1]
BitsDestination
MAIN[4][23]MAIN[5][23]MAIN[5][22]MAIN[5][21]MAIN[5][18]MAIN[5][17]MAIN[5][19]MAIN[5][20]DBL_NW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes DBL_NW0[2]
BitsDestination
MAIN[4][39]MAIN[5][39]MAIN[5][38]MAIN[5][37]MAIN[5][34]MAIN[5][33]MAIN[5][35]MAIN[5][36]DBL_NW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes DBL_NW0[3]
BitsDestination
MAIN[4][55]MAIN[5][55]MAIN[5][54]MAIN[5][53]MAIN[5][50]MAIN[5][49]MAIN[5][51]MAIN[5][52]DBL_NW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes DBL_NE0[0]
BitsDestination
MAIN[6][7]MAIN[7][7]MAIN[7][6]MAIN[7][5]MAIN[7][2]MAIN[7][1]MAIN[7][3]MAIN[7][4]DBL_NE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT switchbox INT muxes DBL_NE0[1]
BitsDestination
MAIN[6][23]MAIN[7][23]MAIN[7][22]MAIN[7][21]MAIN[7][18]MAIN[7][17]MAIN[7][19]MAIN[7][20]DBL_NE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT switchbox INT muxes DBL_NE0[2]
BitsDestination
MAIN[6][39]MAIN[7][39]MAIN[7][38]MAIN[7][37]MAIN[7][34]MAIN[7][33]MAIN[7][35]MAIN[7][36]DBL_NE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT switchbox INT muxes DBL_NE0[3]
BitsDestination
MAIN[6][55]MAIN[7][55]MAIN[7][54]MAIN[7][53]MAIN[7][50]MAIN[7][49]MAIN[7][51]MAIN[7][52]DBL_NE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT switchbox INT muxes QUAD_WW0[0]
BitsDestination
MAIN[0][7]MAIN[1][7]MAIN[1][3]MAIN[1][1]MAIN[1][2]MAIN[1][6]MAIN[1][5]MAIN[1][4]QUAD_WW0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_SS4_N3
00000100QUAD_SW4_N3
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_SS2_N3
01000100DBL_SW2_N3
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[14]
10000100OUT[19]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_WW0[1]
BitsDestination
MAIN[0][23]MAIN[1][23]MAIN[1][19]MAIN[1][17]MAIN[1][18]MAIN[1][22]MAIN[1][21]MAIN[1][20]QUAD_WW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_SS4[0]
00000100QUAD_SW4[0]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[17]
10000100OUT[22]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_WW0[2]
BitsDestination
MAIN[0][39]MAIN[1][39]MAIN[1][35]MAIN[1][33]MAIN[1][34]MAIN[1][38]MAIN[1][37]MAIN[1][36]QUAD_WW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_SS4[1]
00000100QUAD_SW4[1]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[20]
10000100OUT[13]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_WW0[3]
BitsDestination
MAIN[0][55]MAIN[1][55]MAIN[1][51]MAIN[1][49]MAIN[1][50]MAIN[1][54]MAIN[1][53]MAIN[1][52]QUAD_WW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_SS4[2]
00000100QUAD_SW4[2]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[23]
10000100OUT[16]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_EE0[0]
BitsDestination
MAIN[3][15]MAIN[2][15]MAIN[2][12]MAIN[2][13]MAIN[2][10]MAIN[2][14]MAIN[2][11]MAIN[2][9]QUAD_EE0[0]
Source
00000000off
00000001QUAD_EE4[0]
00000010QUAD_NE4[0]
00000100QUAD_SW4[0]
00001000QUAD_SE4[0]
00010000QUAD_SS4[0]
00100000QUAD_NN4[0]
01000001DBL_EE2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_SE2[0]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[19]
10000010OUT[12]
10000100OUT[0]
10001000OUT[14]
10010000OUT[2]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_EE0[1]
BitsDestination
MAIN[3][31]MAIN[2][31]MAIN[2][28]MAIN[2][29]MAIN[2][26]MAIN[2][30]MAIN[2][27]MAIN[2][25]QUAD_EE0[1]
Source
00000000off
00000001QUAD_EE4[1]
00000010QUAD_NE4[1]
00000100QUAD_SW4[1]
00001000QUAD_SE4[1]
00010000QUAD_SS4[1]
00100000QUAD_NN4[1]
01000001DBL_EE2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_SE2[1]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[22]
10000010OUT[15]
10000100OUT[3]
10001000OUT[17]
10010000OUT[5]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_EE0[2]
BitsDestination
MAIN[3][47]MAIN[2][47]MAIN[2][44]MAIN[2][45]MAIN[2][42]MAIN[2][46]MAIN[2][43]MAIN[2][41]QUAD_EE0[2]
Source
00000000off
00000001QUAD_EE4[2]
00000010QUAD_NE4[2]
00000100QUAD_SW4[2]
00001000QUAD_SE4[2]
00010000QUAD_SS4[2]
00100000QUAD_NN4[2]
01000001DBL_EE2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_SE2[2]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[13]
10000010OUT[18]
10000100OUT[6]
10001000OUT[20]
10010000OUT[8]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_EE0[3]
BitsDestination
MAIN[3][63]MAIN[2][63]MAIN[2][60]MAIN[2][61]MAIN[2][58]MAIN[2][62]MAIN[2][59]MAIN[2][57]QUAD_EE0[3]
Source
00000000off
00000001QUAD_EE4[3]
00000010QUAD_NE4[3]
00000100QUAD_SW4[3]
00001000QUAD_SE4[3]
00010000QUAD_SS4[3]
00100000QUAD_NN4[3]
01000001DBL_EE2[3]
01000010DBL_SS2[3]
01000100DBL_SW2[3]
01001000DBL_SE2[3]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[16]
10000010OUT[21]
10000100OUT[9]
10001000OUT[23]
10010000OUT[11]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_SS0[0]
BitsDestination
MAIN[1][15]MAIN[0][15]MAIN[0][12]MAIN[0][10]MAIN[0][14]MAIN[0][11]MAIN[0][9]MAIN[0][13]QUAD_SS0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_EE4[0]
00000100QUAD_NW4[1]
00001000QUAD_SW4[0]
00010000QUAD_SE4[0]
00100000QUAD_WW4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[0]
01000100DBL_SS2[0]
01001000DBL_SW2[0]
01010000DBL_SE2[0]
01100000DBL_NW2[1]
10000001OUT[2]
10000010OUT[19]
10000100OUT[12]
10001000OUT[0]
10010000OUT[14]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_SS0[1]
BitsDestination
MAIN[1][31]MAIN[0][31]MAIN[0][28]MAIN[0][26]MAIN[0][30]MAIN[0][27]MAIN[0][25]MAIN[0][29]QUAD_SS0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_EE4[1]
00000100QUAD_NW4[2]
00001000QUAD_SW4[1]
00010000QUAD_SE4[1]
00100000QUAD_WW4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[1]
01000100DBL_SS2[1]
01001000DBL_SW2[1]
01010000DBL_SE2[1]
01100000DBL_NW2[2]
10000001OUT[5]
10000010OUT[22]
10000100OUT[15]
10001000OUT[3]
10010000OUT[17]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_SS0[2]
BitsDestination
MAIN[1][47]MAIN[0][47]MAIN[0][44]MAIN[0][42]MAIN[0][46]MAIN[0][43]MAIN[0][41]MAIN[0][45]QUAD_SS0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_EE4[2]
00000100QUAD_NW4[3]
00001000QUAD_SW4[2]
00010000QUAD_SE4[2]
00100000QUAD_WW4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[2]
01000100DBL_SS2[2]
01001000DBL_SW2[2]
01010000DBL_SE2[2]
01100000DBL_NW2[3]
10000001OUT[8]
10000010OUT[13]
10000100OUT[18]
10001000OUT[6]
10010000OUT[20]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_SS0[3]
BitsDestination
MAIN[1][63]MAIN[0][63]MAIN[0][60]MAIN[0][58]MAIN[0][62]MAIN[0][59]MAIN[0][57]MAIN[0][61]QUAD_SS0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_EE4[3]
00000100QUAD_NW4_S0
00001000QUAD_SW4[3]
00010000QUAD_SE4[3]
00100000QUAD_WW4_S0
01000001DBL_WW2[3]
01000010DBL_EE2[3]
01000100DBL_SS2[3]
01001000DBL_SW2[3]
01010000DBL_SE2[3]
01100000DBL_NW2_S0
10000001OUT[11]
10000010OUT[16]
10000100OUT[21]
10001000OUT[9]
10010000OUT[23]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_SW0[0]
BitsDestination
MAIN[0][8]MAIN[1][8]MAIN[1][12]MAIN[1][10]MAIN[1][14]MAIN[1][11]MAIN[1][9]MAIN[1][13]QUAD_SW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_EE4[0]
00000100QUAD_NW4[1]
00001000QUAD_SW4[0]
00010000QUAD_SE4[0]
00100000QUAD_WW4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[0]
01000100DBL_SS2[0]
01001000DBL_SW2[0]
01010000DBL_SE2[0]
01100000DBL_NW2[1]
10000001OUT[2]
10000010OUT[19]
10000100OUT[12]
10001000OUT[0]
10010000OUT[14]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_SW0[1]
BitsDestination
MAIN[0][24]MAIN[1][24]MAIN[1][28]MAIN[1][26]MAIN[1][30]MAIN[1][27]MAIN[1][25]MAIN[1][29]QUAD_SW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_EE4[1]
00000100QUAD_NW4[2]
00001000QUAD_SW4[1]
00010000QUAD_SE4[1]
00100000QUAD_WW4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[1]
01000100DBL_SS2[1]
01001000DBL_SW2[1]
01010000DBL_SE2[1]
01100000DBL_NW2[2]
10000001OUT[5]
10000010OUT[22]
10000100OUT[15]
10001000OUT[3]
10010000OUT[17]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_SW0[2]
BitsDestination
MAIN[0][40]MAIN[1][40]MAIN[1][44]MAIN[1][42]MAIN[1][46]MAIN[1][43]MAIN[1][41]MAIN[1][45]QUAD_SW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_EE4[2]
00000100QUAD_NW4[3]
00001000QUAD_SW4[2]
00010000QUAD_SE4[2]
00100000QUAD_WW4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[2]
01000100DBL_SS2[2]
01001000DBL_SW2[2]
01010000DBL_SE2[2]
01100000DBL_NW2[3]
10000001OUT[8]
10000010OUT[13]
10000100OUT[18]
10001000OUT[6]
10010000OUT[20]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_SW0[3]
BitsDestination
MAIN[0][56]MAIN[1][56]MAIN[1][60]MAIN[1][58]MAIN[1][62]MAIN[1][59]MAIN[1][57]MAIN[1][61]QUAD_SW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_EE4[3]
00000100QUAD_NW4_S0
00001000QUAD_SW4[3]
00010000QUAD_SE4[3]
00100000QUAD_WW4_S0
01000001DBL_WW2[3]
01000010DBL_EE2[3]
01000100DBL_SS2[3]
01001000DBL_SW2[3]
01010000DBL_SE2[3]
01100000DBL_NW2_S0
10000001OUT[11]
10000010OUT[16]
10000100OUT[21]
10001000OUT[9]
10010000OUT[23]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_SE0[0]
BitsDestination
MAIN[2][8]MAIN[3][8]MAIN[3][12]MAIN[3][13]MAIN[3][10]MAIN[3][14]MAIN[3][11]MAIN[3][9]QUAD_SE0[0]
Source
00000000off
00000001QUAD_EE4[0]
00000010QUAD_NE4[0]
00000100QUAD_SW4[0]
00001000QUAD_SE4[0]
00010000QUAD_SS4[0]
00100000QUAD_NN4[0]
01000001DBL_EE2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_SE2[0]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[19]
10000010OUT[12]
10000100OUT[0]
10001000OUT[14]
10010000OUT[2]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_SE0[1]
BitsDestination
MAIN[2][24]MAIN[3][24]MAIN[3][28]MAIN[3][29]MAIN[3][26]MAIN[3][30]MAIN[3][27]MAIN[3][25]QUAD_SE0[1]
Source
00000000off
00000001QUAD_EE4[1]
00000010QUAD_NE4[1]
00000100QUAD_SW4[1]
00001000QUAD_SE4[1]
00010000QUAD_SS4[1]
00100000QUAD_NN4[1]
01000001DBL_EE2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_SE2[1]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[22]
10000010OUT[15]
10000100OUT[3]
10001000OUT[17]
10010000OUT[5]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_SE0[2]
BitsDestination
MAIN[2][40]MAIN[3][40]MAIN[3][44]MAIN[3][45]MAIN[3][42]MAIN[3][46]MAIN[3][43]MAIN[3][41]QUAD_SE0[2]
Source
00000000off
00000001QUAD_EE4[2]
00000010QUAD_NE4[2]
00000100QUAD_SW4[2]
00001000QUAD_SE4[2]
00010000QUAD_SS4[2]
00100000QUAD_NN4[2]
01000001DBL_EE2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_SE2[2]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[13]
10000010OUT[18]
10000100OUT[6]
10001000OUT[20]
10010000OUT[8]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_SE0[3]
BitsDestination
MAIN[2][56]MAIN[3][56]MAIN[3][60]MAIN[3][61]MAIN[3][58]MAIN[3][62]MAIN[3][59]MAIN[3][57]QUAD_SE0[3]
Source
00000000off
00000001QUAD_EE4[3]
00000010QUAD_NE4[3]
00000100QUAD_SW4[3]
00001000QUAD_SE4[3]
00010000QUAD_SS4[3]
00100000QUAD_NN4[3]
01000001DBL_EE2[3]
01000010DBL_SS2[3]
01000100DBL_SW2[3]
01001000DBL_SE2[3]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[16]
10000010OUT[21]
10000100OUT[9]
10001000OUT[23]
10010000OUT[11]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_NN0[0]
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][3]MAIN[3][1]MAIN[3][2]MAIN[3][5]MAIN[3][6]MAIN[3][4]QUAD_NN0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_EE4[0]
00000100QUAD_SE4[0]
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_EE2[0]
01000100DBL_SE2[0]
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[19]
10000100OUT[14]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_NN0[1]
BitsDestination
MAIN[2][23]MAIN[3][23]MAIN[3][19]MAIN[3][17]MAIN[3][18]MAIN[3][21]MAIN[3][22]MAIN[3][20]QUAD_NN0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_EE4[1]
00000100QUAD_SE4[1]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[1]
01000100DBL_SE2[1]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[22]
10000100OUT[17]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_NN0[2]
BitsDestination
MAIN[2][39]MAIN[3][39]MAIN[3][35]MAIN[3][33]MAIN[3][34]MAIN[3][37]MAIN[3][38]MAIN[3][36]QUAD_NN0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_EE4[2]
00000100QUAD_SE4[2]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[2]
01000100DBL_SE2[2]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[13]
10000100OUT[20]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_NN0[3]
BitsDestination
MAIN[2][55]MAIN[3][55]MAIN[3][51]MAIN[3][49]MAIN[3][50]MAIN[3][53]MAIN[3][54]MAIN[3][52]QUAD_NN0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_EE4[3]
00000100QUAD_SE4[3]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[3]
01000100DBL_SE2[3]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[16]
10000100OUT[23]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_NW0[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[0][3]MAIN[0][1]MAIN[0][2]MAIN[0][6]MAIN[0][5]MAIN[0][4]QUAD_NW0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_SS4_N3
00000100QUAD_SW4_N3
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_SS2_N3
01000100DBL_SW2_N3
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[14]
10000100OUT[19]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_NW0[1]
BitsDestination
MAIN[1][16]MAIN[0][16]MAIN[0][19]MAIN[0][17]MAIN[0][18]MAIN[0][22]MAIN[0][21]MAIN[0][20]QUAD_NW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_SS4[0]
00000100QUAD_SW4[0]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[17]
10000100OUT[22]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_NW0[2]
BitsDestination
MAIN[1][32]MAIN[0][32]MAIN[0][35]MAIN[0][33]MAIN[0][34]MAIN[0][38]MAIN[0][37]MAIN[0][36]QUAD_NW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_SS4[1]
00000100QUAD_SW4[1]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[20]
10000100OUT[13]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_NW0[3]
BitsDestination
MAIN[1][48]MAIN[0][48]MAIN[0][51]MAIN[0][49]MAIN[0][50]MAIN[0][54]MAIN[0][53]MAIN[0][52]QUAD_NW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_SS4[2]
00000100QUAD_SW4[2]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[23]
10000100OUT[16]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT switchbox INT muxes QUAD_NE0[0]
BitsDestination
MAIN[3][0]MAIN[2][0]MAIN[2][3]MAIN[2][1]MAIN[2][2]MAIN[2][5]MAIN[2][6]MAIN[2][4]QUAD_NE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_EE4[0]
00000100QUAD_SE4[0]
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_EE2[0]
01000100DBL_SE2[0]
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[19]
10000100OUT[14]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT switchbox INT muxes QUAD_NE0[1]
BitsDestination
MAIN[3][16]MAIN[2][16]MAIN[2][19]MAIN[2][17]MAIN[2][18]MAIN[2][21]MAIN[2][22]MAIN[2][20]QUAD_NE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_EE4[1]
00000100QUAD_SE4[1]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[1]
01000100DBL_SE2[1]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[22]
10000100OUT[17]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT switchbox INT muxes QUAD_NE0[2]
BitsDestination
MAIN[3][32]MAIN[2][32]MAIN[2][35]MAIN[2][33]MAIN[2][34]MAIN[2][37]MAIN[2][38]MAIN[2][36]QUAD_NE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_EE4[2]
00000100QUAD_SE4[2]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[2]
01000100DBL_SE2[2]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[13]
10000100OUT[20]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT switchbox INT muxes QUAD_NE0[3]
BitsDestination
MAIN[3][48]MAIN[2][48]MAIN[2][51]MAIN[2][49]MAIN[2][50]MAIN[2][53]MAIN[2][54]MAIN[2][52]QUAD_NE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_EE4[3]
00000100QUAD_SE4[3]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[3]
01000100DBL_SE2[3]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[16]
10000100OUT[23]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT switchbox INT muxes IMUX_GFAN[0]
BitsDestination
MAIN[20][0]MAIN[20][1]MAIN[20][7]MAIN[20][4]MAIN[20][3]MAIN[20][2]MAIN[20][5]MAIN[20][6]IMUX_GFAN[0]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[5]
01001000SNG_E1[5]
01010000SNG_N1[5]
01100000SNG_W1[5]
10000001IMUX_LOGICIN[35]
10000010IMUX_LOGICIN[6]
10000100HCLK[6]
10001000HCLK[7]
10010000IMUX_LOGICIN[53]
10100000IMUX_LOGICIN[51]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT switchbox INT muxes IMUX_GFAN[1]
BitsDestination
MAIN[20][15]MAIN[20][14]MAIN[20][8]MAIN[20][9]MAIN[20][12]MAIN[20][13]MAIN[20][10]MAIN[20][11]IMUX_GFAN[1]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[5]
01001000SNG_E1[5]
01010000SNG_N1[5]
01100000SNG_W1[5]
10000001IMUX_LOGICIN[35]
10000010IMUX_LOGICIN[6]
10000100HCLK[6]
10001000HCLK[7]
10010000IMUX_LOGICIN[53]
10100000IMUX_LOGICIN[51]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[20][38]MAIN[20][39]MAIN[20][32]MAIN[20][35]MAIN[20][36]MAIN[20][37]MAIN[20][34]MAIN[20][33]IMUX_CLK[0]
Source
00000000PULLUP
00000001TIE_0
00000010TIE_1
00000100SNG_N1[6]
00001000SNG_W1[6]
00010000SNG_S1[5]
00100000SNG_E1[5]
01000001HCLK[10]
01000010HCLK[11]
01000100HCLK[6]
01001000HCLK[7]
01010000HCLK[8]
01100000HCLK[9]
10000001IMUX_LOGICIN[53]
10000010IMUX_LOGICIN[43]
10000100HCLK[12]
10001000HCLK[13]
10010000HCLK[14]
10100000HCLK[15]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[20][25]MAIN[20][24]MAIN[20][31]MAIN[20][30]MAIN[20][27]MAIN[20][26]MAIN[20][29]MAIN[20][28]IMUX_CLK[1]
Source
00000000PULLUP
00000001TIE_0
00000010TIE_1
00000100SNG_N1[6]
00001000SNG_W1[6]
00010000SNG_S1[5]
00100000SNG_E1[5]
01000001HCLK[10]
01000010HCLK[11]
01000100HCLK[6]
01001000HCLK[7]
01010000HCLK[8]
01100000HCLK[9]
10000001IMUX_LOGICIN[53]
10000010IMUX_LOGICIN[43]
10000100HCLK[12]
10001000HCLK[13]
10010000HCLK[14]
10100000HCLK[15]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[20][63]MAIN[20][62]MAIN[20][56]MAIN[20][59]MAIN[20][60]MAIN[20][61]MAIN[20][58]MAIN[20][57]IMUX_SR[0]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[6]
01001000SNG_E1[6]
01010000SNG_N1[6]
01100000SNG_W1[6]
10000001IMUX_LOGICIN[13]
10000010IMUX_LOGICIN[43]
10000100HCLK[14]
10001000HCLK[15]
10010000IMUX_LOGICIN[61]
10100000IMUX_LOGICIN[63]
11000001HCLK[12]
11000010HCLK[13]
11000100HCLK[8]
11001000HCLK[9]
11010000HCLK[10]
11100000HCLK[11]
spartan6 INT switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][55]MAIN[20][54]MAIN[20][51]MAIN[20][50]MAIN[20][53]MAIN[20][52]IMUX_SR[1]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[6]
01001000SNG_E1[6]
01010000SNG_N1[6]
01100000SNG_W1[6]
10000001IMUX_LOGICIN[13]
10000010IMUX_LOGICIN[43]
10000100HCLK[14]
10001000HCLK[15]
10010000IMUX_LOGICIN[61]
10100000IMUX_LOGICIN[63]
11000001HCLK[12]
11000010HCLK[13]
11000100HCLK[8]
11001000HCLK[9]
11010000HCLK[10]
11100000HCLK[11]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[0]
BitsDestination
MAIN[13][31]MAIN[12][31]MAIN[12][25]MAIN[12][26]MAIN[12][29]MAIN[12][30]MAIN[12][27]MAIN[12][28]IMUX_LOGICIN[0]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[1]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[2]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[61]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001OUT[5]
11000010OUT[22]
11000100IMUX_GFAN[0]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[1]
BitsDestination
MAIN[13][40]MAIN[12][40]MAIN[13][41]MAIN[13][42]MAIN[13][45]MAIN[13][46]MAIN[13][43]MAIN[13][44]IMUX_LOGICIN[1]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[2]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[3]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001OUT[20]
11000010OUT[1]
11000100IMUX_GFAN[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[2]
BitsDestination
MAIN[17][48]MAIN[16][48]MAIN[17][49]MAIN[17][50]MAIN[17][53]MAIN[17][51]MAIN[17][52]MAIN[17][54]IMUX_LOGICIN[2]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[3]
BitsDestination
MAIN[17][32]MAIN[16][32]MAIN[17][33]MAIN[17][34]MAIN[17][37]MAIN[17][35]MAIN[17][36]MAIN[17][38]IMUX_LOGICIN[3]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[4]
BitsDestination
MAIN[17][16]MAIN[16][16]MAIN[17][17]MAIN[17][18]MAIN[17][21]MAIN[17][19]MAIN[17][20]MAIN[17][22]IMUX_LOGICIN[4]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[5]
BitsDestination
MAIN[17][0]MAIN[16][0]MAIN[17][1]MAIN[17][2]MAIN[17][5]MAIN[17][3]MAIN[17][4]MAIN[17][6]IMUX_LOGICIN[5]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[6]
BitsDestination
MAIN[17][8]MAIN[16][8]MAIN[17][9]MAIN[17][10]MAIN[17][13]MAIN[17][14]MAIN[17][11]MAIN[17][12]IMUX_LOGICIN[6]
Source
00000000PULLUP
00000001DBL_NW2[0]
00000010DBL_WW2_N3
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[0]
01000010SNG_W1[4]
01000100SNG_E1[0]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[0]
10000010SNG_N1[4]
10000100IMUX_LOGICIN21_N
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001OUT[2]
11000010OUT[19]
11000100IMUX_GFAN[0]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[7]
BitsDestination
MAIN[18][0]MAIN[19][0]MAIN[18][1]MAIN[18][2]MAIN[18][5]MAIN[18][6]MAIN[18][4]MAIN[18][3]IMUX_LOGICIN[7]
Source
00000000PULLUP
00000001DBL_WW2_N3
00000010DBL_NW2[0]
00000100DBL_SS2_N3
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_E1[0]
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[4]
10000010SNG_N1[0]
10000100IMUX_LOGICIN21_N
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001OUT[19]
11000010OUT[2]
11000100IMUX_GFAN[0]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[8]
BitsDestination
MAIN[18][55]MAIN[19][55]MAIN[19][49]MAIN[19][50]MAIN[19][53]MAIN[19][54]MAIN[19][51]MAIN[19][52]IMUX_LOGICIN[8]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1[3]
10000010SNG_N1[7]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001OUT[23]
11000010OUT[4]
11000100IMUX_GFAN[1]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[9]
BitsDestination
MAIN[14][56]MAIN[15][56]MAIN[14][57]MAIN[14][58]MAIN[14][61]MAIN[14][59]MAIN[14][60]MAIN[14][62]IMUX_LOGICIN[9]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[10]
BitsDestination
MAIN[14][40]MAIN[15][40]MAIN[14][41]MAIN[14][42]MAIN[14][45]MAIN[14][43]MAIN[14][44]MAIN[14][46]IMUX_LOGICIN[10]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[11]
BitsDestination
MAIN[14][24]MAIN[15][24]MAIN[14][25]MAIN[14][26]MAIN[14][29]MAIN[14][27]MAIN[14][28]MAIN[14][30]IMUX_LOGICIN[11]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[12]
BitsDestination
MAIN[14][8]MAIN[15][8]MAIN[14][9]MAIN[14][10]MAIN[14][13]MAIN[14][11]MAIN[14][12]MAIN[14][14]IMUX_LOGICIN[12]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[13]
BitsDestination
MAIN[14][16]MAIN[15][16]MAIN[14][17]MAIN[14][18]MAIN[14][21]MAIN[14][22]MAIN[14][19]MAIN[14][20]IMUX_LOGICIN[13]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[2]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[61]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001OUT[5]
11000010OUT[22]
11000100IMUX_GFAN[0]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[14]
BitsDestination
MAIN[14][55]MAIN[15][55]MAIN[15][49]MAIN[15][50]MAIN[15][54]MAIN[15][53]MAIN[15][51]MAIN[15][52]IMUX_LOGICIN[14]
Source
00000000PULLUP
00000001DBL_NW2_S0
00000010DBL_WW2[3]
00000100DBL_SW2[3]
00001000DBL_SS2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_E1[7]
01001000SNG_E1_S0
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1_S0
10000010SNG_N1[7]
10000100IMUX_LOGICIN52_BOUNCE
10001000IMUX_LOGICIN[13]
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001OUT[11]
11000010OUT[16]
11000100OUT[21]
11001000IMUX_GFAN[1]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[15]
BitsDestination
MAIN[14][0]MAIN[15][0]MAIN[14][1]MAIN[14][2]MAIN[14][5]MAIN[14][6]MAIN[14][3]MAIN[14][4]IMUX_LOGICIN[15]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[1]
10000010SNG_N1[4]
10000100IMUX_LOGICIN52_N
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001OUT[14]
11000010OUT[7]
11000100IMUX_GFAN[0]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[16]
BitsDestination
MAIN[18][8]MAIN[19][8]MAIN[18][9]MAIN[18][10]MAIN[18][13]MAIN[18][12]MAIN[18][11]MAIN[18][14]IMUX_LOGICIN[16]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[17]
BitsDestination
MAIN[18][24]MAIN[19][24]MAIN[18][25]MAIN[18][26]MAIN[18][29]MAIN[18][27]MAIN[18][28]MAIN[18][30]IMUX_LOGICIN[17]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[18]
BitsDestination
MAIN[18][40]MAIN[19][40]MAIN[18][41]MAIN[18][42]MAIN[18][45]MAIN[18][43]MAIN[18][44]MAIN[18][46]IMUX_LOGICIN[18]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[19]
BitsDestination
MAIN[18][56]MAIN[19][56]MAIN[18][57]MAIN[18][58]MAIN[18][61]MAIN[18][59]MAIN[18][60]MAIN[18][62]IMUX_LOGICIN[19]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[20]
BitsDestination
MAIN[13][24]MAIN[12][24]MAIN[13][25]MAIN[13][26]MAIN[13][29]MAIN[13][30]MAIN[13][27]MAIN[13][28]IMUX_LOGICIN[20]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[1]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[2]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[61]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001OUT[5]
11000010OUT[22]
11000100IMUX_GFAN[0]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[21]
BitsDestination
MAIN[17][47]MAIN[16][47]MAIN[16][41]MAIN[16][42]MAIN[16][45]MAIN[16][46]MAIN[16][43]MAIN[16][44]IMUX_LOGICIN[21]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[2]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[2]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001OUT[8]
11000010OUT[13]
11000100IMUX_GFAN[1]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[22]
BitsDestination
MAIN[17][40]MAIN[16][40]MAIN[17][41]MAIN[17][42]MAIN[17][45]MAIN[17][46]MAIN[17][43]MAIN[17][44]IMUX_LOGICIN[22]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[2]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[2]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001OUT[8]
11000010OUT[13]
11000100IMUX_GFAN[1]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[23]
BitsDestination
MAIN[17][24]MAIN[16][24]MAIN[17][25]MAIN[17][26]MAIN[17][29]MAIN[17][30]MAIN[17][27]MAIN[17][28]IMUX_LOGICIN[23]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[1]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[1]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[63]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001OUT[17]
11000010OUT[10]
11000100IMUX_GFAN[0]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[24]
BitsDestination
MAIN[13][0]MAIN[12][0]MAIN[13][1]MAIN[13][2]MAIN[13][5]MAIN[13][3]MAIN[13][4]MAIN[13][6]IMUX_LOGICIN[24]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[25]
BitsDestination
MAIN[13][16]MAIN[12][16]MAIN[13][17]MAIN[13][18]MAIN[13][21]MAIN[13][19]MAIN[13][20]MAIN[13][22]IMUX_LOGICIN[25]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[26]
BitsDestination
MAIN[13][32]MAIN[12][32]MAIN[13][33]MAIN[13][34]MAIN[13][37]MAIN[13][35]MAIN[13][36]MAIN[13][38]IMUX_LOGICIN[26]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[27]
BitsDestination
MAIN[13][48]MAIN[12][48]MAIN[13][49]MAIN[13][50]MAIN[13][53]MAIN[13][51]MAIN[13][52]MAIN[13][54]IMUX_LOGICIN[27]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[28]
BitsDestination
MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[14][50]MAIN[14][54]MAIN[14][53]MAIN[14][51]MAIN[14][52]IMUX_LOGICIN[28]
Source
00000000PULLUP
00000001DBL_NW2_S0
00000010DBL_WW2[3]
00000100DBL_SW2[3]
00001000DBL_SS2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_E1[7]
01001000SNG_E1_S0
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1_S0
10000010SNG_N1[7]
10000100IMUX_LOGICIN52_BOUNCE
10001000IMUX_LOGICIN[13]
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001OUT[11]
11000010OUT[16]
11000100OUT[21]
11001000IMUX_GFAN[1]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[29]
BitsDestination
MAIN[18][39]MAIN[19][39]MAIN[19][33]MAIN[19][34]MAIN[19][37]MAIN[19][38]MAIN[19][35]MAIN[19][36]IMUX_LOGICIN[29]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[2]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001OUT[8]
11000010OUT[13]
11000100IMUX_GFAN[1]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[30]
BitsDestination
MAIN[18][23]MAIN[19][23]MAIN[19][17]MAIN[19][18]MAIN[19][21]MAIN[19][22]MAIN[19][19]MAIN[19][20]IMUX_LOGICIN[30]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[1]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[63]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001OUT[17]
11000010OUT[10]
11000100IMUX_GFAN[0]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[31]
BitsDestination
MAIN[14][63]MAIN[15][63]MAIN[15][57]MAIN[15][58]MAIN[15][61]MAIN[15][59]MAIN[15][60]MAIN[15][62]IMUX_LOGICIN[31]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[32]
BitsDestination
MAIN[14][47]MAIN[15][47]MAIN[15][41]MAIN[15][42]MAIN[15][45]MAIN[15][43]MAIN[15][44]MAIN[15][46]IMUX_LOGICIN[32]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[33]
BitsDestination
MAIN[14][31]MAIN[15][31]MAIN[15][25]MAIN[15][26]MAIN[15][29]MAIN[15][27]MAIN[15][28]MAIN[15][30]IMUX_LOGICIN[33]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[34]
BitsDestination
MAIN[14][15]MAIN[15][15]MAIN[15][9]MAIN[15][10]MAIN[15][13]MAIN[15][11]MAIN[15][12]MAIN[15][14]IMUX_LOGICIN[34]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[35]
BitsDestination
MAIN[14][7]MAIN[15][7]MAIN[15][1]MAIN[15][2]MAIN[15][5]MAIN[15][6]MAIN[15][3]MAIN[15][4]IMUX_LOGICIN[35]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[1]
10000010SNG_N1[4]
10000100IMUX_LOGICIN52_N
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001OUT[14]
11000010OUT[7]
11000100IMUX_GFAN[0]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[36]
BitsDestination
MAIN[18][7]MAIN[19][7]MAIN[19][1]MAIN[19][2]MAIN[19][5]MAIN[19][6]MAIN[19][4]MAIN[19][3]IMUX_LOGICIN[36]
Source
00000000PULLUP
00000001DBL_WW2_N3
00000010DBL_NW2[0]
00000100DBL_SS2_N3
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_E1[0]
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[4]
10000010SNG_N1[0]
10000100IMUX_LOGICIN21_N
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001OUT[19]
11000010OUT[2]
11000100IMUX_GFAN[0]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[37]
BitsDestination
MAIN[13][63]MAIN[12][63]MAIN[12][57]MAIN[12][58]MAIN[12][61]MAIN[12][62]MAIN[12][59]MAIN[12][60]IMUX_LOGICIN[37]
Source
00000000PULLUP
00000001DBL_NW2_S0
00000010DBL_WW2[3]
00000100DBL_SS2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[3]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1_S0
10000010SNG_N1[7]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001OUT[11]
11000010OUT[16]
11000100IMUX_GFAN[1]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[38]
BitsDestination
MAIN[13][15]MAIN[12][15]MAIN[12][9]MAIN[12][10]MAIN[12][13]MAIN[12][14]MAIN[12][11]MAIN[12][12]IMUX_LOGICIN[38]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[0]
01000010SNG_W1[4]
01000100SNG_E1[0]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[1]
10000010SNG_N1[4]
10000100IMUX_LOGICIN52_N
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001OUT[14]
11000010OUT[7]
11000100IMUX_GFAN[0]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[39]
BitsDestination
MAIN[17][55]MAIN[16][55]MAIN[16][49]MAIN[16][50]MAIN[16][53]MAIN[16][51]MAIN[16][52]MAIN[16][54]IMUX_LOGICIN[39]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[40]
BitsDestination
MAIN[17][39]MAIN[16][39]MAIN[16][33]MAIN[16][34]MAIN[16][37]MAIN[16][35]MAIN[16][36]MAIN[16][38]IMUX_LOGICIN[40]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[41]
BitsDestination
MAIN[17][23]MAIN[16][23]MAIN[16][17]MAIN[16][18]MAIN[16][21]MAIN[16][19]MAIN[16][20]MAIN[16][22]IMUX_LOGICIN[41]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[42]
BitsDestination
MAIN[17][7]MAIN[16][7]MAIN[16][1]MAIN[16][2]MAIN[16][5]MAIN[16][3]MAIN[16][4]MAIN[16][6]IMUX_LOGICIN[42]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[43]
BitsDestination
MAIN[17][31]MAIN[16][31]MAIN[16][25]MAIN[16][26]MAIN[16][29]MAIN[16][30]MAIN[16][27]MAIN[16][28]IMUX_LOGICIN[43]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[1]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[1]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[63]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001OUT[17]
11000010OUT[10]
11000100IMUX_GFAN[0]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[44]
BitsDestination
MAIN[18][16]MAIN[19][16]MAIN[18][17]MAIN[18][18]MAIN[18][21]MAIN[18][22]MAIN[18][19]MAIN[18][20]IMUX_LOGICIN[44]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_E1[1]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[1]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[63]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001OUT[17]
11000010OUT[10]
11000100IMUX_GFAN[0]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[45]
BitsDestination
MAIN[17][15]MAIN[16][15]MAIN[16][9]MAIN[16][10]MAIN[16][13]MAIN[16][14]MAIN[16][11]MAIN[16][12]IMUX_LOGICIN[45]
Source
00000000PULLUP
00000001DBL_NW2[0]
00000010DBL_WW2_N3
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[0]
01000010SNG_W1[4]
01000100SNG_E1[0]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[0]
10000010SNG_N1[4]
10000100IMUX_LOGICIN21_N
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001OUT[2]
11000010OUT[19]
11000100IMUX_GFAN[0]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[46]
BitsDestination
MAIN[17][63]MAIN[16][63]MAIN[16][57]MAIN[16][58]MAIN[16][61]MAIN[16][62]MAIN[16][59]MAIN[16][60]IMUX_LOGICIN[46]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[3]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1[3]
10000010SNG_N1[7]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001OUT[23]
11000010OUT[4]
11000100IMUX_GFAN[1]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[47]
BitsDestination
MAIN[13][7]MAIN[12][7]MAIN[12][1]MAIN[12][2]MAIN[12][5]MAIN[12][3]MAIN[12][4]MAIN[12][6]IMUX_LOGICIN[47]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[48]
BitsDestination
MAIN[13][23]MAIN[12][23]MAIN[12][17]MAIN[12][18]MAIN[12][21]MAIN[12][19]MAIN[12][20]MAIN[12][22]IMUX_LOGICIN[48]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[49]
BitsDestination
MAIN[13][39]MAIN[12][39]MAIN[12][33]MAIN[12][34]MAIN[12][37]MAIN[12][35]MAIN[12][36]MAIN[12][38]IMUX_LOGICIN[49]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[50]
BitsDestination
MAIN[13][55]MAIN[12][55]MAIN[12][49]MAIN[12][50]MAIN[12][53]MAIN[12][51]MAIN[12][52]MAIN[12][54]IMUX_LOGICIN[50]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[51]
BitsDestination
MAIN[18][32]MAIN[19][32]MAIN[18][33]MAIN[18][34]MAIN[18][37]MAIN[18][38]MAIN[18][35]MAIN[18][36]IMUX_LOGICIN[51]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[2]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001OUT[8]
11000010OUT[13]
11000100IMUX_GFAN[1]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[52]
BitsDestination
MAIN[14][39]MAIN[15][39]MAIN[15][33]MAIN[15][34]MAIN[15][37]MAIN[15][38]MAIN[15][35]MAIN[15][36]IMUX_LOGICIN[52]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[3]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001OUT[20]
11000010OUT[1]
11000100IMUX_GFAN[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[53]
BitsDestination
MAIN[13][47]MAIN[12][47]MAIN[12][41]MAIN[12][42]MAIN[12][45]MAIN[12][46]MAIN[12][43]MAIN[12][44]IMUX_LOGICIN[53]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[2]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[3]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001OUT[20]
11000010OUT[1]
11000100IMUX_GFAN[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[54]
BitsDestination
MAIN[14][23]MAIN[15][23]MAIN[15][17]MAIN[15][18]MAIN[15][21]MAIN[15][22]MAIN[15][19]MAIN[15][20]IMUX_LOGICIN[54]
Source
00000000PULLUP
00000001DBL_NW2[2]
00000010DBL_WW2[1]
00000100DBL_SS2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_E1[2]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001SNG_N1[2]
10000010SNG_N1[5]
10000100IMUX_LOGICIN[61]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001OUT[5]
11000010OUT[22]
11000100IMUX_GFAN[0]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[55]
BitsDestination
MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[14][34]MAIN[14][37]MAIN[14][38]MAIN[14][35]MAIN[14][36]IMUX_LOGICIN[55]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001SNG_N1[3]
10000010SNG_N1[6]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001OUT[20]
11000010OUT[1]
11000100IMUX_GFAN[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[56]
BitsDestination
MAIN[18][15]MAIN[19][15]MAIN[19][9]MAIN[19][10]MAIN[19][13]MAIN[19][12]MAIN[19][11]MAIN[19][14]IMUX_LOGICIN[56]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[57]
BitsDestination
MAIN[18][31]MAIN[19][31]MAIN[19][25]MAIN[19][26]MAIN[19][29]MAIN[19][27]MAIN[19][28]MAIN[19][30]IMUX_LOGICIN[57]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[58]
BitsDestination
MAIN[18][47]MAIN[19][47]MAIN[19][41]MAIN[19][42]MAIN[19][45]MAIN[19][43]MAIN[19][44]MAIN[19][46]IMUX_LOGICIN[58]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[59]
BitsDestination
MAIN[18][63]MAIN[19][63]MAIN[19][57]MAIN[19][58]MAIN[19][61]MAIN[19][59]MAIN[19][60]MAIN[19][62]IMUX_LOGICIN[59]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[60]
BitsDestination
MAIN[17][56]MAIN[16][56]MAIN[17][57]MAIN[17][58]MAIN[17][61]MAIN[17][62]MAIN[17][59]MAIN[17][60]IMUX_LOGICIN[60]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[3]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1[3]
10000010SNG_N1[7]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001OUT[23]
11000010OUT[4]
11000100IMUX_GFAN[1]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[61]
BitsDestination
MAIN[13][56]MAIN[12][56]MAIN[13][57]MAIN[13][58]MAIN[13][61]MAIN[13][62]MAIN[13][59]MAIN[13][60]IMUX_LOGICIN[61]
Source
00000000PULLUP
00000001DBL_NW2_S0
00000010DBL_WW2[3]
00000100DBL_SS2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[3]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1_S0
10000010SNG_N1[7]
10000100IMUX_LOGICIN[13]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001OUT[11]
11000010OUT[16]
11000100IMUX_GFAN[1]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT switchbox INT muxes IMUX_LOGICIN[62]
BitsDestination
MAIN[13][8]MAIN[12][8]MAIN[13][9]MAIN[13][10]MAIN[13][13]MAIN[13][14]MAIN[13][11]MAIN[13][12]IMUX_LOGICIN[62]
Source
00000000PULLUP
00000001DBL_NW2[1]
00000010DBL_WW2[0]
00000100DBL_SS2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_W1[0]
01000010SNG_W1[4]
01000100SNG_E1[0]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001SNG_N1[1]
10000010SNG_N1[4]
10000100IMUX_LOGICIN52_N
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001OUT[14]
11000010OUT[7]
11000100IMUX_GFAN[0]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT switchbox INT muxes IMUX_LOGICIN[63]
BitsDestination
MAIN[18][48]MAIN[19][48]MAIN[18][49]MAIN[18][50]MAIN[18][53]MAIN[18][54]MAIN[18][51]MAIN[18][52]IMUX_LOGICIN[63]
Source
00000000PULLUP
00000001DBL_NW2[3]
00000010DBL_WW2[2]
00000100DBL_SS2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_E1[3]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001SNG_N1[3]
10000010SNG_N1[7]
10000100IMUX_LOGICIN[43]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001OUT[23]
11000010OUT[4]
11000100IMUX_GFAN[1]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S

Bitstream

spartan6 INT rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B63 INT: mux QUAD_SS0[3] bit 6 INT: mux QUAD_SS0[3] bit 7 INT: mux QUAD_EE0[3] bit 6 INT: mux QUAD_EE0[3] bit 7 INT: mux DBL_WW0[3] bit 6 INT: mux DBL_WW0[3] bit 7 INT: mux DBL_SS0[3] bit 6 INT: mux DBL_SS0[3] bit 7 INT: mux SNG_S0[4] bit 6 INT: mux SNG_S0[4] bit 7 INT: mux SNG_S0[3] bit 6 INT: mux SNG_S0[3] bit 7 INT: mux IMUX_LOGICIN[37] bit 6 INT: mux IMUX_LOGICIN[37] bit 7 INT: mux IMUX_LOGICIN[31] bit 7 INT: mux IMUX_LOGICIN[31] bit 6 INT: mux IMUX_LOGICIN[46] bit 6 INT: mux IMUX_LOGICIN[46] bit 7 INT: mux IMUX_LOGICIN[59] bit 7 INT: mux IMUX_LOGICIN[59] bit 6 INT: mux IMUX_SR[0] bit 7 -
B62 INT: mux QUAD_SS0[3] bit 3 INT: mux QUAD_SW0[3] bit 3 INT: mux QUAD_EE0[3] bit 2 INT: mux QUAD_SE0[3] bit 2 INT: mux DBL_WW0[3] bit 3 INT: mux DBL_SW0[3] bit 3 INT: mux DBL_SS0[3] bit 3 INT: mux DBL_SE0[3] bit 3 INT: mux SNG_S0[4] bit 3 INT: mux SNG_W0[2] bit 3 INT: mux SNG_S0[3] bit 3 INT: mux SNG_E0[4] bit 3 INT: mux IMUX_LOGICIN[37] bit 2 INT: mux IMUX_LOGICIN[61] bit 2 INT: mux IMUX_LOGICIN[9] bit 0 INT: mux IMUX_LOGICIN[31] bit 0 INT: mux IMUX_LOGICIN[46] bit 2 INT: mux IMUX_LOGICIN[60] bit 2 INT: mux IMUX_LOGICIN[19] bit 0 INT: mux IMUX_LOGICIN[59] bit 0 INT: mux IMUX_SR[0] bit 6 -
B61 INT: mux QUAD_SS0[3] bit 0 INT: mux QUAD_SW0[3] bit 0 INT: mux QUAD_EE0[3] bit 4 INT: mux QUAD_SE0[3] bit 4 INT: mux DBL_WW0[3] bit 2 INT: mux DBL_SW0[3] bit 2 INT: mux DBL_SS0[3] bit 2 INT: mux DBL_SE0[3] bit 2 INT: mux SNG_S0[4] bit 2 INT: mux SNG_W0[2] bit 2 INT: mux SNG_S0[3] bit 2 INT: mux SNG_E0[4] bit 2 INT: mux IMUX_LOGICIN[37] bit 3 INT: mux IMUX_LOGICIN[61] bit 3 INT: mux IMUX_LOGICIN[9] bit 3 INT: mux IMUX_LOGICIN[31] bit 3 INT: mux IMUX_LOGICIN[46] bit 3 INT: mux IMUX_LOGICIN[60] bit 3 INT: mux IMUX_LOGICIN[19] bit 3 INT: mux IMUX_LOGICIN[59] bit 3 INT: mux IMUX_SR[0] bit 2 -
B60 INT: mux QUAD_SS0[3] bit 5 INT: mux QUAD_SW0[3] bit 5 INT: mux QUAD_EE0[3] bit 5 INT: mux QUAD_SE0[3] bit 5 INT: mux DBL_WW0[3] bit 1 INT: mux DBL_SW0[3] bit 1 INT: mux DBL_SS0[3] bit 1 INT: mux DBL_SE0[3] bit 1 INT: mux SNG_S0[4] bit 1 INT: mux SNG_W0[2] bit 1 INT: mux SNG_S0[3] bit 1 INT: mux SNG_E0[4] bit 1 INT: mux IMUX_LOGICIN[37] bit 0 INT: mux IMUX_LOGICIN[61] bit 0 INT: mux IMUX_LOGICIN[9] bit 1 INT: mux IMUX_LOGICIN[31] bit 1 INT: mux IMUX_LOGICIN[46] bit 0 INT: mux IMUX_LOGICIN[60] bit 0 INT: mux IMUX_LOGICIN[19] bit 1 INT: mux IMUX_LOGICIN[59] bit 1 INT: mux IMUX_SR[0] bit 3 -
B59 INT: mux QUAD_SS0[3] bit 2 INT: mux QUAD_SW0[3] bit 2 INT: mux QUAD_EE0[3] bit 1 INT: mux QUAD_SE0[3] bit 1 INT: mux DBL_WW0[3] bit 0 INT: mux DBL_SW0[3] bit 0 INT: mux DBL_SS0[3] bit 0 INT: mux DBL_SE0[3] bit 0 INT: mux SNG_S0[4] bit 0 INT: mux SNG_W0[2] bit 0 INT: mux SNG_S0[3] bit 0 INT: mux SNG_E0[4] bit 0 INT: mux IMUX_LOGICIN[37] bit 1 INT: mux IMUX_LOGICIN[61] bit 1 INT: mux IMUX_LOGICIN[9] bit 2 INT: mux IMUX_LOGICIN[31] bit 2 INT: mux IMUX_LOGICIN[46] bit 1 INT: mux IMUX_LOGICIN[60] bit 1 INT: mux IMUX_LOGICIN[19] bit 2 INT: mux IMUX_LOGICIN[59] bit 2 INT: mux IMUX_SR[0] bit 4 -
B58 INT: mux QUAD_SS0[3] bit 4 INT: mux QUAD_SW0[3] bit 4 INT: mux QUAD_EE0[3] bit 3 INT: mux QUAD_SE0[3] bit 3 INT: mux DBL_WW0[3] bit 5 INT: mux DBL_SW0[3] bit 5 INT: mux DBL_SS0[3] bit 5 INT: mux DBL_SE0[3] bit 5 INT: mux SNG_S0[4] bit 5 INT: mux SNG_W0[2] bit 5 INT: mux SNG_S0[3] bit 5 INT: mux SNG_E0[4] bit 5 INT: mux IMUX_LOGICIN[37] bit 4 INT: mux IMUX_LOGICIN[61] bit 4 INT: mux IMUX_LOGICIN[9] bit 4 INT: mux IMUX_LOGICIN[31] bit 4 INT: mux IMUX_LOGICIN[46] bit 4 INT: mux IMUX_LOGICIN[60] bit 4 INT: mux IMUX_LOGICIN[19] bit 4 INT: mux IMUX_LOGICIN[59] bit 4 INT: mux IMUX_SR[0] bit 1 -
B57 INT: mux QUAD_SS0[3] bit 1 INT: mux QUAD_SW0[3] bit 1 INT: mux QUAD_EE0[3] bit 0 INT: mux QUAD_SE0[3] bit 0 INT: mux DBL_WW0[3] bit 4 INT: mux DBL_SW0[3] bit 4 INT: mux DBL_SS0[3] bit 4 INT: mux DBL_SE0[3] bit 4 INT: mux SNG_S0[4] bit 4 INT: mux SNG_W0[2] bit 4 INT: mux SNG_S0[3] bit 4 INT: mux SNG_E0[4] bit 4 INT: mux IMUX_LOGICIN[37] bit 5 INT: mux IMUX_LOGICIN[61] bit 5 INT: mux IMUX_LOGICIN[9] bit 5 INT: mux IMUX_LOGICIN[31] bit 5 INT: mux IMUX_LOGICIN[46] bit 5 INT: mux IMUX_LOGICIN[60] bit 5 INT: mux IMUX_LOGICIN[19] bit 5 INT: mux IMUX_LOGICIN[59] bit 5 INT: mux IMUX_SR[0] bit 0 -
B56 INT: mux QUAD_SW0[3] bit 7 INT: mux QUAD_SW0[3] bit 6 INT: mux QUAD_SE0[3] bit 7 INT: mux QUAD_SE0[3] bit 6 INT: mux DBL_SW0[3] bit 7 INT: mux DBL_SW0[3] bit 6 INT: mux DBL_SE0[3] bit 7 INT: mux DBL_SE0[3] bit 6 INT: mux SNG_W0[2] bit 7 INT: mux SNG_W0[2] bit 6 INT: mux SNG_E0[4] bit 7 INT: mux SNG_E0[4] bit 6 INT: mux IMUX_LOGICIN[61] bit 6 INT: mux IMUX_LOGICIN[61] bit 7 INT: mux IMUX_LOGICIN[9] bit 7 INT: mux IMUX_LOGICIN[9] bit 6 INT: mux IMUX_LOGICIN[60] bit 6 INT: mux IMUX_LOGICIN[60] bit 7 INT: mux IMUX_LOGICIN[19] bit 7 INT: mux IMUX_LOGICIN[19] bit 6 INT: mux IMUX_SR[0] bit 5 -
B55 INT: mux QUAD_WW0[3] bit 7 INT: mux QUAD_WW0[3] bit 6 INT: mux QUAD_NN0[3] bit 7 INT: mux QUAD_NN0[3] bit 6 INT: mux DBL_NW0[3] bit 7 INT: mux DBL_NW0[3] bit 6 INT: mux DBL_NE0[3] bit 7 INT: mux DBL_NE0[3] bit 6 INT: mux SNG_W0[4] bit 7 INT: mux SNG_W0[4] bit 6 INT: mux SNG_E0[2] bit 7 INT: mux SNG_E0[2] bit 6 INT: mux IMUX_LOGICIN[50] bit 6 INT: mux IMUX_LOGICIN[50] bit 7 INT: mux IMUX_LOGICIN[14] bit 7 INT: mux IMUX_LOGICIN[14] bit 6 INT: mux IMUX_LOGICIN[39] bit 6 INT: mux IMUX_LOGICIN[39] bit 7 INT: mux IMUX_LOGICIN[8] bit 7 INT: mux IMUX_LOGICIN[8] bit 6 INT: mux IMUX_SR[1] bit 5 -
B54 INT: mux QUAD_NW0[3] bit 2 INT: mux QUAD_WW0[3] bit 2 INT: mux QUAD_NE0[3] bit 1 INT: mux QUAD_NN0[3] bit 1 INT: mux DBL_NN0[3] bit 5 INT: mux DBL_NW0[3] bit 5 INT: mux DBL_EE0[3] bit 5 INT: mux DBL_NE0[3] bit 5 INT: mux SNG_N0[2] bit 5 INT: mux SNG_W0[4] bit 5 INT: mux SNG_N0[7] bit 5 INT: mux SNG_E0[2] bit 5 INT: mux IMUX_LOGICIN[50] bit 0 INT: mux IMUX_LOGICIN[27] bit 0 INT: mux IMUX_LOGICIN[28] bit 3 INT: mux IMUX_LOGICIN[14] bit 3 INT: mux IMUX_LOGICIN[39] bit 0 INT: mux IMUX_LOGICIN[2] bit 0 INT: mux IMUX_LOGICIN[63] bit 2 INT: mux IMUX_LOGICIN[8] bit 2 INT: mux IMUX_SR[1] bit 4 -
B53 INT: mux QUAD_NW0[3] bit 1 INT: mux QUAD_WW0[3] bit 1 INT: mux QUAD_NE0[3] bit 2 INT: mux QUAD_NN0[3] bit 2 INT: mux DBL_NN0[3] bit 4 INT: mux DBL_NW0[3] bit 4 INT: mux DBL_EE0[3] bit 4 INT: mux DBL_NE0[3] bit 4 INT: mux SNG_N0[2] bit 4 INT: mux SNG_W0[4] bit 4 INT: mux SNG_N0[7] bit 4 INT: mux SNG_E0[2] bit 4 INT: mux IMUX_LOGICIN[50] bit 3 INT: mux IMUX_LOGICIN[27] bit 3 INT: mux IMUX_LOGICIN[28] bit 2 INT: mux IMUX_LOGICIN[14] bit 2 INT: mux IMUX_LOGICIN[39] bit 3 INT: mux IMUX_LOGICIN[2] bit 3 INT: mux IMUX_LOGICIN[63] bit 3 INT: mux IMUX_LOGICIN[8] bit 3 INT: mux IMUX_SR[1] bit 1 -
B52 INT: mux QUAD_NW0[3] bit 0 INT: mux QUAD_WW0[3] bit 0 INT: mux QUAD_NE0[3] bit 0 INT: mux QUAD_NN0[3] bit 0 INT: mux DBL_NN0[3] bit 0 INT: mux DBL_NW0[3] bit 0 INT: mux DBL_EE0[3] bit 0 INT: mux DBL_NE0[3] bit 0 INT: mux SNG_N0[2] bit 0 INT: mux SNG_W0[4] bit 0 INT: mux SNG_N0[7] bit 0 INT: mux SNG_E0[2] bit 0 INT: mux IMUX_LOGICIN[50] bit 1 INT: mux IMUX_LOGICIN[27] bit 1 INT: mux IMUX_LOGICIN[28] bit 0 INT: mux IMUX_LOGICIN[14] bit 0 INT: mux IMUX_LOGICIN[39] bit 1 INT: mux IMUX_LOGICIN[2] bit 1 INT: mux IMUX_LOGICIN[63] bit 0 INT: mux IMUX_LOGICIN[8] bit 0 INT: mux IMUX_SR[1] bit 0 -
B51 INT: mux QUAD_NW0[3] bit 5 INT: mux QUAD_WW0[3] bit 5 INT: mux QUAD_NE0[3] bit 5 INT: mux QUAD_NN0[3] bit 5 INT: mux DBL_NN0[3] bit 1 INT: mux DBL_NW0[3] bit 1 INT: mux DBL_EE0[3] bit 1 INT: mux DBL_NE0[3] bit 1 INT: mux SNG_N0[2] bit 1 INT: mux SNG_W0[4] bit 1 INT: mux SNG_N0[7] bit 1 INT: mux SNG_E0[2] bit 1 INT: mux IMUX_LOGICIN[50] bit 2 INT: mux IMUX_LOGICIN[27] bit 2 INT: mux IMUX_LOGICIN[28] bit 1 INT: mux IMUX_LOGICIN[14] bit 1 INT: mux IMUX_LOGICIN[39] bit 2 INT: mux IMUX_LOGICIN[2] bit 2 INT: mux IMUX_LOGICIN[63] bit 1 INT: mux IMUX_LOGICIN[8] bit 1 INT: mux IMUX_SR[1] bit 3 -
B50 INT: mux QUAD_NW0[3] bit 3 INT: mux QUAD_WW0[3] bit 3 INT: mux QUAD_NE0[3] bit 3 INT: mux QUAD_NN0[3] bit 3 INT: mux DBL_NN0[3] bit 3 INT: mux DBL_NW0[3] bit 3 INT: mux DBL_EE0[3] bit 3 INT: mux DBL_NE0[3] bit 3 INT: mux SNG_N0[2] bit 3 INT: mux SNG_W0[4] bit 3 INT: mux SNG_N0[7] bit 3 INT: mux SNG_E0[2] bit 3 INT: mux IMUX_LOGICIN[50] bit 4 INT: mux IMUX_LOGICIN[27] bit 4 INT: mux IMUX_LOGICIN[28] bit 4 INT: mux IMUX_LOGICIN[14] bit 4 INT: mux IMUX_LOGICIN[39] bit 4 INT: mux IMUX_LOGICIN[2] bit 4 INT: mux IMUX_LOGICIN[63] bit 4 INT: mux IMUX_LOGICIN[8] bit 4 INT: mux IMUX_SR[1] bit 2 -
B49 INT: mux QUAD_NW0[3] bit 4 INT: mux QUAD_WW0[3] bit 4 INT: mux QUAD_NE0[3] bit 4 INT: mux QUAD_NN0[3] bit 4 INT: mux DBL_NN0[3] bit 2 INT: mux DBL_NW0[3] bit 2 INT: mux DBL_EE0[3] bit 2 INT: mux DBL_NE0[3] bit 2 INT: mux SNG_N0[2] bit 2 INT: mux SNG_W0[4] bit 2 INT: mux SNG_N0[7] bit 2 INT: mux SNG_E0[2] bit 2 INT: mux IMUX_LOGICIN[50] bit 5 INT: mux IMUX_LOGICIN[27] bit 5 INT: mux IMUX_LOGICIN[28] bit 5 INT: mux IMUX_LOGICIN[14] bit 5 INT: mux IMUX_LOGICIN[39] bit 5 INT: mux IMUX_LOGICIN[2] bit 5 INT: mux IMUX_LOGICIN[63] bit 5 INT: mux IMUX_LOGICIN[8] bit 5 INT: mux IMUX_SR[1] bit 6 -
B48 INT: mux QUAD_NW0[3] bit 6 INT: mux QUAD_NW0[3] bit 7 INT: mux QUAD_NE0[3] bit 6 INT: mux QUAD_NE0[3] bit 7 INT: mux DBL_NN0[3] bit 6 INT: mux DBL_NN0[3] bit 7 INT: mux DBL_EE0[3] bit 6 INT: mux DBL_EE0[3] bit 7 INT: mux SNG_N0[2] bit 6 INT: mux SNG_N0[2] bit 7 INT: mux SNG_N0[7] bit 6 INT: mux SNG_N0[7] bit 7 INT: mux IMUX_LOGICIN[27] bit 6 INT: mux IMUX_LOGICIN[27] bit 7 INT: mux IMUX_LOGICIN[28] bit 7 INT: mux IMUX_LOGICIN[28] bit 6 INT: mux IMUX_LOGICIN[2] bit 6 INT: mux IMUX_LOGICIN[2] bit 7 INT: mux IMUX_LOGICIN[63] bit 7 INT: mux IMUX_LOGICIN[63] bit 6 INT: mux IMUX_SR[1] bit 7 -
B47 INT: mux QUAD_SS0[2] bit 6 INT: mux QUAD_SS0[2] bit 7 INT: mux QUAD_EE0[2] bit 6 INT: mux QUAD_EE0[2] bit 7 INT: mux DBL_WW0[2] bit 6 INT: mux DBL_WW0[2] bit 7 INT: mux DBL_SS0[2] bit 6 INT: mux DBL_SS0[2] bit 7 INT: mux SNG_S0[7] bit 6 INT: mux SNG_S0[7] bit 7 INT: mux SNG_S0[2] bit 6 INT: mux SNG_S0[2] bit 7 INT: mux IMUX_LOGICIN[53] bit 6 INT: mux IMUX_LOGICIN[53] bit 7 INT: mux IMUX_LOGICIN[32] bit 7 INT: mux IMUX_LOGICIN[32] bit 6 INT: mux IMUX_LOGICIN[21] bit 6 INT: mux IMUX_LOGICIN[21] bit 7 INT: mux IMUX_LOGICIN[58] bit 7 INT: mux IMUX_LOGICIN[58] bit 6 - -
B46 INT: mux QUAD_SS0[2] bit 3 INT: mux QUAD_SW0[2] bit 3 INT: mux QUAD_EE0[2] bit 2 INT: mux QUAD_SE0[2] bit 2 INT: mux DBL_WW0[2] bit 3 INT: mux DBL_SW0[2] bit 3 INT: mux DBL_SS0[2] bit 3 INT: mux DBL_SE0[2] bit 3 INT: mux SNG_S0[7] bit 3 INT: mux SNG_W0[1] bit 3 INT: mux SNG_S0[2] bit 3 INT: mux SNG_E0[7] bit 3 INT: mux IMUX_LOGICIN[53] bit 2 INT: mux IMUX_LOGICIN[1] bit 2 INT: mux IMUX_LOGICIN[10] bit 0 INT: mux IMUX_LOGICIN[32] bit 0 INT: mux IMUX_LOGICIN[21] bit 2 INT: mux IMUX_LOGICIN[22] bit 2 INT: mux IMUX_LOGICIN[18] bit 0 INT: mux IMUX_LOGICIN[58] bit 0 - -
B45 INT: mux QUAD_SS0[2] bit 0 INT: mux QUAD_SW0[2] bit 0 INT: mux QUAD_EE0[2] bit 4 INT: mux QUAD_SE0[2] bit 4 INT: mux DBL_WW0[2] bit 2 INT: mux DBL_SW0[2] bit 2 INT: mux DBL_SS0[2] bit 2 INT: mux DBL_SE0[2] bit 2 INT: mux SNG_S0[7] bit 2 INT: mux SNG_W0[1] bit 2 INT: mux SNG_S0[2] bit 2 INT: mux SNG_E0[7] bit 2 INT: mux IMUX_LOGICIN[53] bit 3 INT: mux IMUX_LOGICIN[1] bit 3 INT: mux IMUX_LOGICIN[10] bit 3 INT: mux IMUX_LOGICIN[32] bit 3 INT: mux IMUX_LOGICIN[21] bit 3 INT: mux IMUX_LOGICIN[22] bit 3 INT: mux IMUX_LOGICIN[18] bit 3 INT: mux IMUX_LOGICIN[58] bit 3 - -
B44 INT: mux QUAD_SS0[2] bit 5 INT: mux QUAD_SW0[2] bit 5 INT: mux QUAD_EE0[2] bit 5 INT: mux QUAD_SE0[2] bit 5 INT: mux DBL_WW0[2] bit 1 INT: mux DBL_SW0[2] bit 1 INT: mux DBL_SS0[2] bit 1 INT: mux DBL_SE0[2] bit 1 INT: mux SNG_S0[7] bit 1 INT: mux SNG_W0[1] bit 1 INT: mux SNG_S0[2] bit 1 INT: mux SNG_E0[7] bit 1 INT: mux IMUX_LOGICIN[53] bit 0 INT: mux IMUX_LOGICIN[1] bit 0 INT: mux IMUX_LOGICIN[10] bit 1 INT: mux IMUX_LOGICIN[32] bit 1 INT: mux IMUX_LOGICIN[21] bit 0 INT: mux IMUX_LOGICIN[22] bit 0 INT: mux IMUX_LOGICIN[18] bit 1 INT: mux IMUX_LOGICIN[58] bit 1 - -
B43 INT: mux QUAD_SS0[2] bit 2 INT: mux QUAD_SW0[2] bit 2 INT: mux QUAD_EE0[2] bit 1 INT: mux QUAD_SE0[2] bit 1 INT: mux DBL_WW0[2] bit 0 INT: mux DBL_SW0[2] bit 0 INT: mux DBL_SS0[2] bit 0 INT: mux DBL_SE0[2] bit 0 INT: mux SNG_S0[7] bit 0 INT: mux SNG_W0[1] bit 0 INT: mux SNG_S0[2] bit 0 INT: mux SNG_E0[7] bit 0 INT: mux IMUX_LOGICIN[53] bit 1 INT: mux IMUX_LOGICIN[1] bit 1 INT: mux IMUX_LOGICIN[10] bit 2 INT: mux IMUX_LOGICIN[32] bit 2 INT: mux IMUX_LOGICIN[21] bit 1 INT: mux IMUX_LOGICIN[22] bit 1 INT: mux IMUX_LOGICIN[18] bit 2 INT: mux IMUX_LOGICIN[58] bit 2 - -
B42 INT: mux QUAD_SS0[2] bit 4 INT: mux QUAD_SW0[2] bit 4 INT: mux QUAD_EE0[2] bit 3 INT: mux QUAD_SE0[2] bit 3 INT: mux DBL_WW0[2] bit 5 INT: mux DBL_SW0[2] bit 5 INT: mux DBL_SS0[2] bit 5 INT: mux DBL_SE0[2] bit 5 INT: mux SNG_S0[7] bit 5 INT: mux SNG_W0[1] bit 5 INT: mux SNG_S0[2] bit 5 INT: mux SNG_E0[7] bit 5 INT: mux IMUX_LOGICIN[53] bit 4 INT: mux IMUX_LOGICIN[1] bit 4 INT: mux IMUX_LOGICIN[10] bit 4 INT: mux IMUX_LOGICIN[32] bit 4 INT: mux IMUX_LOGICIN[21] bit 4 INT: mux IMUX_LOGICIN[22] bit 4 INT: mux IMUX_LOGICIN[18] bit 4 INT: mux IMUX_LOGICIN[58] bit 4 - -
B41 INT: mux QUAD_SS0[2] bit 1 INT: mux QUAD_SW0[2] bit 1 INT: mux QUAD_EE0[2] bit 0 INT: mux QUAD_SE0[2] bit 0 INT: mux DBL_WW0[2] bit 4 INT: mux DBL_SW0[2] bit 4 INT: mux DBL_SS0[2] bit 4 INT: mux DBL_SE0[2] bit 4 INT: mux SNG_S0[7] bit 4 INT: mux SNG_W0[1] bit 4 INT: mux SNG_S0[2] bit 4 INT: mux SNG_E0[7] bit 4 INT: mux IMUX_LOGICIN[53] bit 5 INT: mux IMUX_LOGICIN[1] bit 5 INT: mux IMUX_LOGICIN[10] bit 5 INT: mux IMUX_LOGICIN[32] bit 5 INT: mux IMUX_LOGICIN[21] bit 5 INT: mux IMUX_LOGICIN[22] bit 5 INT: mux IMUX_LOGICIN[18] bit 5 INT: mux IMUX_LOGICIN[58] bit 5 - -
B40 INT: mux QUAD_SW0[2] bit 7 INT: mux QUAD_SW0[2] bit 6 INT: mux QUAD_SE0[2] bit 7 INT: mux QUAD_SE0[2] bit 6 INT: mux DBL_SW0[2] bit 7 INT: mux DBL_SW0[2] bit 6 INT: mux DBL_SE0[2] bit 7 INT: mux DBL_SE0[2] bit 6 INT: mux SNG_W0[1] bit 7 INT: mux SNG_W0[1] bit 6 INT: mux SNG_E0[7] bit 7 INT: mux SNG_E0[7] bit 6 INT: mux IMUX_LOGICIN[1] bit 6 INT: mux IMUX_LOGICIN[1] bit 7 INT: mux IMUX_LOGICIN[10] bit 7 INT: mux IMUX_LOGICIN[10] bit 6 INT: mux IMUX_LOGICIN[22] bit 6 INT: mux IMUX_LOGICIN[22] bit 7 INT: mux IMUX_LOGICIN[18] bit 7 INT: mux IMUX_LOGICIN[18] bit 6 - -
B39 INT: mux QUAD_WW0[2] bit 7 INT: mux QUAD_WW0[2] bit 6 INT: mux QUAD_NN0[2] bit 7 INT: mux QUAD_NN0[2] bit 6 INT: mux DBL_NW0[2] bit 7 INT: mux DBL_NW0[2] bit 6 INT: mux DBL_NE0[2] bit 7 INT: mux DBL_NE0[2] bit 6 INT: mux SNG_W0[7] bit 7 INT: mux SNG_W0[7] bit 6 INT: mux SNG_E0[1] bit 7 INT: mux SNG_E0[1] bit 6 INT: mux IMUX_LOGICIN[49] bit 6 INT: mux IMUX_LOGICIN[49] bit 7 INT: mux IMUX_LOGICIN[52] bit 7 INT: mux IMUX_LOGICIN[52] bit 6 INT: mux IMUX_LOGICIN[40] bit 6 INT: mux IMUX_LOGICIN[40] bit 7 INT: mux IMUX_LOGICIN[29] bit 7 INT: mux IMUX_LOGICIN[29] bit 6 INT: mux IMUX_CLK[0] bit 6 -
B38 INT: mux QUAD_NW0[2] bit 2 INT: mux QUAD_WW0[2] bit 2 INT: mux QUAD_NE0[2] bit 1 INT: mux QUAD_NN0[2] bit 1 INT: mux DBL_NN0[2] bit 5 INT: mux DBL_NW0[2] bit 5 INT: mux DBL_EE0[2] bit 5 INT: mux DBL_NE0[2] bit 5 INT: mux SNG_N0[1] bit 5 INT: mux SNG_W0[7] bit 5 INT: mux SNG_N0[6] bit 5 INT: mux SNG_E0[1] bit 5 INT: mux IMUX_LOGICIN[49] bit 0 INT: mux IMUX_LOGICIN[26] bit 0 INT: mux IMUX_LOGICIN[55] bit 2 INT: mux IMUX_LOGICIN[52] bit 2 INT: mux IMUX_LOGICIN[40] bit 0 INT: mux IMUX_LOGICIN[3] bit 0 INT: mux IMUX_LOGICIN[51] bit 2 INT: mux IMUX_LOGICIN[29] bit 2 INT: mux IMUX_CLK[0] bit 7 -
B37 INT: mux QUAD_NW0[2] bit 1 INT: mux QUAD_WW0[2] bit 1 INT: mux QUAD_NE0[2] bit 2 INT: mux QUAD_NN0[2] bit 2 INT: mux DBL_NN0[2] bit 4 INT: mux DBL_NW0[2] bit 4 INT: mux DBL_EE0[2] bit 4 INT: mux DBL_NE0[2] bit 4 INT: mux SNG_N0[1] bit 4 INT: mux SNG_W0[7] bit 4 INT: mux SNG_N0[6] bit 4 INT: mux SNG_E0[1] bit 4 INT: mux IMUX_LOGICIN[49] bit 3 INT: mux IMUX_LOGICIN[26] bit 3 INT: mux IMUX_LOGICIN[55] bit 3 INT: mux IMUX_LOGICIN[52] bit 3 INT: mux IMUX_LOGICIN[40] bit 3 INT: mux IMUX_LOGICIN[3] bit 3 INT: mux IMUX_LOGICIN[51] bit 3 INT: mux IMUX_LOGICIN[29] bit 3 INT: mux IMUX_CLK[0] bit 2 -
B36 INT: mux QUAD_NW0[2] bit 0 INT: mux QUAD_WW0[2] bit 0 INT: mux QUAD_NE0[2] bit 0 INT: mux QUAD_NN0[2] bit 0 INT: mux DBL_NN0[2] bit 0 INT: mux DBL_NW0[2] bit 0 INT: mux DBL_EE0[2] bit 0 INT: mux DBL_NE0[2] bit 0 INT: mux SNG_N0[1] bit 0 INT: mux SNG_W0[7] bit 0 INT: mux SNG_N0[6] bit 0 INT: mux SNG_E0[1] bit 0 INT: mux IMUX_LOGICIN[49] bit 1 INT: mux IMUX_LOGICIN[26] bit 1 INT: mux IMUX_LOGICIN[55] bit 0 INT: mux IMUX_LOGICIN[52] bit 0 INT: mux IMUX_LOGICIN[40] bit 1 INT: mux IMUX_LOGICIN[3] bit 1 INT: mux IMUX_LOGICIN[51] bit 0 INT: mux IMUX_LOGICIN[29] bit 0 INT: mux IMUX_CLK[0] bit 3 -
B35 INT: mux QUAD_NW0[2] bit 5 INT: mux QUAD_WW0[2] bit 5 INT: mux QUAD_NE0[2] bit 5 INT: mux QUAD_NN0[2] bit 5 INT: mux DBL_NN0[2] bit 1 INT: mux DBL_NW0[2] bit 1 INT: mux DBL_EE0[2] bit 1 INT: mux DBL_NE0[2] bit 1 INT: mux SNG_N0[1] bit 1 INT: mux SNG_W0[7] bit 1 INT: mux SNG_N0[6] bit 1 INT: mux SNG_E0[1] bit 1 INT: mux IMUX_LOGICIN[49] bit 2 INT: mux IMUX_LOGICIN[26] bit 2 INT: mux IMUX_LOGICIN[55] bit 1 INT: mux IMUX_LOGICIN[52] bit 1 INT: mux IMUX_LOGICIN[40] bit 2 INT: mux IMUX_LOGICIN[3] bit 2 INT: mux IMUX_LOGICIN[51] bit 1 INT: mux IMUX_LOGICIN[29] bit 1 INT: mux IMUX_CLK[0] bit 4 -
B34 INT: mux QUAD_NW0[2] bit 3 INT: mux QUAD_WW0[2] bit 3 INT: mux QUAD_NE0[2] bit 3 INT: mux QUAD_NN0[2] bit 3 INT: mux DBL_NN0[2] bit 3 INT: mux DBL_NW0[2] bit 3 INT: mux DBL_EE0[2] bit 3 INT: mux DBL_NE0[2] bit 3 INT: mux SNG_N0[1] bit 3 INT: mux SNG_W0[7] bit 3 INT: mux SNG_N0[6] bit 3 INT: mux SNG_E0[1] bit 3 INT: mux IMUX_LOGICIN[49] bit 4 INT: mux IMUX_LOGICIN[26] bit 4 INT: mux IMUX_LOGICIN[55] bit 4 INT: mux IMUX_LOGICIN[52] bit 4 INT: mux IMUX_LOGICIN[40] bit 4 INT: mux IMUX_LOGICIN[3] bit 4 INT: mux IMUX_LOGICIN[51] bit 4 INT: mux IMUX_LOGICIN[29] bit 4 INT: mux IMUX_CLK[0] bit 1 -
B33 INT: mux QUAD_NW0[2] bit 4 INT: mux QUAD_WW0[2] bit 4 INT: mux QUAD_NE0[2] bit 4 INT: mux QUAD_NN0[2] bit 4 INT: mux DBL_NN0[2] bit 2 INT: mux DBL_NW0[2] bit 2 INT: mux DBL_EE0[2] bit 2 INT: mux DBL_NE0[2] bit 2 INT: mux SNG_N0[1] bit 2 INT: mux SNG_W0[7] bit 2 INT: mux SNG_N0[6] bit 2 INT: mux SNG_E0[1] bit 2 INT: mux IMUX_LOGICIN[49] bit 5 INT: mux IMUX_LOGICIN[26] bit 5 INT: mux IMUX_LOGICIN[55] bit 5 INT: mux IMUX_LOGICIN[52] bit 5 INT: mux IMUX_LOGICIN[40] bit 5 INT: mux IMUX_LOGICIN[3] bit 5 INT: mux IMUX_LOGICIN[51] bit 5 INT: mux IMUX_LOGICIN[29] bit 5 INT: mux IMUX_CLK[0] bit 0 -
B32 INT: mux QUAD_NW0[2] bit 6 INT: mux QUAD_NW0[2] bit 7 INT: mux QUAD_NE0[2] bit 6 INT: mux QUAD_NE0[2] bit 7 INT: mux DBL_NN0[2] bit 6 INT: mux DBL_NN0[2] bit 7 INT: mux DBL_EE0[2] bit 6 INT: mux DBL_EE0[2] bit 7 INT: mux SNG_N0[1] bit 6 INT: mux SNG_N0[1] bit 7 INT: mux SNG_N0[6] bit 6 INT: mux SNG_N0[6] bit 7 INT: mux IMUX_LOGICIN[26] bit 6 INT: mux IMUX_LOGICIN[26] bit 7 INT: mux IMUX_LOGICIN[55] bit 7 INT: mux IMUX_LOGICIN[55] bit 6 INT: mux IMUX_LOGICIN[3] bit 6 INT: mux IMUX_LOGICIN[3] bit 7 INT: mux IMUX_LOGICIN[51] bit 7 INT: mux IMUX_LOGICIN[51] bit 6 INT: mux IMUX_CLK[0] bit 5 -
B31 INT: mux QUAD_SS0[1] bit 6 INT: mux QUAD_SS0[1] bit 7 INT: mux QUAD_EE0[1] bit 6 INT: mux QUAD_EE0[1] bit 7 INT: mux DBL_WW0[1] bit 6 INT: mux DBL_WW0[1] bit 7 INT: mux DBL_SS0[1] bit 6 INT: mux DBL_SS0[1] bit 7 INT: mux SNG_S0[6] bit 6 INT: mux SNG_S0[6] bit 7 INT: mux SNG_S0[1] bit 6 INT: mux SNG_S0[1] bit 7 INT: mux IMUX_LOGICIN[0] bit 6 INT: mux IMUX_LOGICIN[0] bit 7 INT: mux IMUX_LOGICIN[33] bit 7 INT: mux IMUX_LOGICIN[33] bit 6 INT: mux IMUX_LOGICIN[43] bit 6 INT: mux IMUX_LOGICIN[43] bit 7 INT: mux IMUX_LOGICIN[57] bit 7 INT: mux IMUX_LOGICIN[57] bit 6 INT: mux IMUX_CLK[1] bit 5 -
B30 INT: mux QUAD_SS0[1] bit 3 INT: mux QUAD_SW0[1] bit 3 INT: mux QUAD_EE0[1] bit 2 INT: mux QUAD_SE0[1] bit 2 INT: mux DBL_WW0[1] bit 3 INT: mux DBL_SW0[1] bit 3 INT: mux DBL_SS0[1] bit 3 INT: mux DBL_SE0[1] bit 3 INT: mux SNG_S0[6] bit 3 INT: mux SNG_W0[0] bit 3 INT: mux SNG_S0[1] bit 3 INT: mux SNG_E0[6] bit 3 INT: mux IMUX_LOGICIN[0] bit 2 INT: mux IMUX_LOGICIN[20] bit 2 INT: mux IMUX_LOGICIN[11] bit 0 INT: mux IMUX_LOGICIN[33] bit 0 INT: mux IMUX_LOGICIN[43] bit 2 INT: mux IMUX_LOGICIN[23] bit 2 INT: mux IMUX_LOGICIN[17] bit 0 INT: mux IMUX_LOGICIN[57] bit 0 INT: mux IMUX_CLK[1] bit 4 -
B29 INT: mux QUAD_SS0[1] bit 0 INT: mux QUAD_SW0[1] bit 0 INT: mux QUAD_EE0[1] bit 4 INT: mux QUAD_SE0[1] bit 4 INT: mux DBL_WW0[1] bit 2 INT: mux DBL_SW0[1] bit 2 INT: mux DBL_SS0[1] bit 2 INT: mux DBL_SE0[1] bit 2 INT: mux SNG_S0[6] bit 2 INT: mux SNG_W0[0] bit 2 INT: mux SNG_S0[1] bit 2 INT: mux SNG_E0[6] bit 2 INT: mux IMUX_LOGICIN[0] bit 3 INT: mux IMUX_LOGICIN[20] bit 3 INT: mux IMUX_LOGICIN[11] bit 3 INT: mux IMUX_LOGICIN[33] bit 3 INT: mux IMUX_LOGICIN[43] bit 3 INT: mux IMUX_LOGICIN[23] bit 3 INT: mux IMUX_LOGICIN[17] bit 3 INT: mux IMUX_LOGICIN[57] bit 3 INT: mux IMUX_CLK[1] bit 1 -
B28 INT: mux QUAD_SS0[1] bit 5 INT: mux QUAD_SW0[1] bit 5 INT: mux QUAD_EE0[1] bit 5 INT: mux QUAD_SE0[1] bit 5 INT: mux DBL_WW0[1] bit 1 INT: mux DBL_SW0[1] bit 1 INT: mux DBL_SS0[1] bit 1 INT: mux DBL_SE0[1] bit 1 INT: mux SNG_S0[6] bit 1 INT: mux SNG_W0[0] bit 1 INT: mux SNG_S0[1] bit 1 INT: mux SNG_E0[6] bit 1 INT: mux IMUX_LOGICIN[0] bit 0 INT: mux IMUX_LOGICIN[20] bit 0 INT: mux IMUX_LOGICIN[11] bit 1 INT: mux IMUX_LOGICIN[33] bit 1 INT: mux IMUX_LOGICIN[43] bit 0 INT: mux IMUX_LOGICIN[23] bit 0 INT: mux IMUX_LOGICIN[17] bit 1 INT: mux IMUX_LOGICIN[57] bit 1 INT: mux IMUX_CLK[1] bit 0 -
B27 INT: mux QUAD_SS0[1] bit 2 INT: mux QUAD_SW0[1] bit 2 INT: mux QUAD_EE0[1] bit 1 INT: mux QUAD_SE0[1] bit 1 INT: mux DBL_WW0[1] bit 0 INT: mux DBL_SW0[1] bit 0 INT: mux DBL_SS0[1] bit 0 INT: mux DBL_SE0[1] bit 0 INT: mux SNG_S0[6] bit 0 INT: mux SNG_W0[0] bit 0 INT: mux SNG_S0[1] bit 0 INT: mux SNG_E0[6] bit 0 INT: mux IMUX_LOGICIN[0] bit 1 INT: mux IMUX_LOGICIN[20] bit 1 INT: mux IMUX_LOGICIN[11] bit 2 INT: mux IMUX_LOGICIN[33] bit 2 INT: mux IMUX_LOGICIN[43] bit 1 INT: mux IMUX_LOGICIN[23] bit 1 INT: mux IMUX_LOGICIN[17] bit 2 INT: mux IMUX_LOGICIN[57] bit 2 INT: mux IMUX_CLK[1] bit 3 -
B26 INT: mux QUAD_SS0[1] bit 4 INT: mux QUAD_SW0[1] bit 4 INT: mux QUAD_EE0[1] bit 3 INT: mux QUAD_SE0[1] bit 3 INT: mux DBL_WW0[1] bit 5 INT: mux DBL_SW0[1] bit 5 INT: mux DBL_SS0[1] bit 5 INT: mux DBL_SE0[1] bit 5 INT: mux SNG_S0[6] bit 5 INT: mux SNG_W0[0] bit 5 INT: mux SNG_S0[1] bit 5 INT: mux SNG_E0[6] bit 5 INT: mux IMUX_LOGICIN[0] bit 4 INT: mux IMUX_LOGICIN[20] bit 4 INT: mux IMUX_LOGICIN[11] bit 4 INT: mux IMUX_LOGICIN[33] bit 4 INT: mux IMUX_LOGICIN[43] bit 4 INT: mux IMUX_LOGICIN[23] bit 4 INT: mux IMUX_LOGICIN[17] bit 4 INT: mux IMUX_LOGICIN[57] bit 4 INT: mux IMUX_CLK[1] bit 2 -
B25 INT: mux QUAD_SS0[1] bit 1 INT: mux QUAD_SW0[1] bit 1 INT: mux QUAD_EE0[1] bit 0 INT: mux QUAD_SE0[1] bit 0 INT: mux DBL_WW0[1] bit 4 INT: mux DBL_SW0[1] bit 4 INT: mux DBL_SS0[1] bit 4 INT: mux DBL_SE0[1] bit 4 INT: mux SNG_S0[6] bit 4 INT: mux SNG_W0[0] bit 4 INT: mux SNG_S0[1] bit 4 INT: mux SNG_E0[6] bit 4 INT: mux IMUX_LOGICIN[0] bit 5 INT: mux IMUX_LOGICIN[20] bit 5 INT: mux IMUX_LOGICIN[11] bit 5 INT: mux IMUX_LOGICIN[33] bit 5 INT: mux IMUX_LOGICIN[43] bit 5 INT: mux IMUX_LOGICIN[23] bit 5 INT: mux IMUX_LOGICIN[17] bit 5 INT: mux IMUX_LOGICIN[57] bit 5 INT: mux IMUX_CLK[1] bit 7 -
B24 INT: mux QUAD_SW0[1] bit 7 INT: mux QUAD_SW0[1] bit 6 INT: mux QUAD_SE0[1] bit 7 INT: mux QUAD_SE0[1] bit 6 INT: mux DBL_SW0[1] bit 7 INT: mux DBL_SW0[1] bit 6 INT: mux DBL_SE0[1] bit 7 INT: mux DBL_SE0[1] bit 6 INT: mux SNG_W0[0] bit 7 INT: mux SNG_W0[0] bit 6 INT: mux SNG_E0[6] bit 7 INT: mux SNG_E0[6] bit 6 INT: mux IMUX_LOGICIN[20] bit 6 INT: mux IMUX_LOGICIN[20] bit 7 INT: mux IMUX_LOGICIN[11] bit 7 INT: mux IMUX_LOGICIN[11] bit 6 INT: mux IMUX_LOGICIN[23] bit 6 INT: mux IMUX_LOGICIN[23] bit 7 INT: mux IMUX_LOGICIN[17] bit 7 INT: mux IMUX_LOGICIN[17] bit 6 INT: mux IMUX_CLK[1] bit 6 -
B23 INT: mux QUAD_WW0[1] bit 7 INT: mux QUAD_WW0[1] bit 6 INT: mux QUAD_NN0[1] bit 7 INT: mux QUAD_NN0[1] bit 6 INT: mux DBL_NW0[1] bit 7 INT: mux DBL_NW0[1] bit 6 INT: mux DBL_NE0[1] bit 7 INT: mux DBL_NE0[1] bit 6 INT: mux SNG_W0[6] bit 7 INT: mux SNG_W0[6] bit 6 INT: mux SNG_E0[0] bit 7 INT: mux SNG_E0[0] bit 6 INT: mux IMUX_LOGICIN[48] bit 6 INT: mux IMUX_LOGICIN[48] bit 7 INT: mux IMUX_LOGICIN[54] bit 7 INT: mux IMUX_LOGICIN[54] bit 6 INT: mux IMUX_LOGICIN[41] bit 6 INT: mux IMUX_LOGICIN[41] bit 7 INT: mux IMUX_LOGICIN[30] bit 7 INT: mux IMUX_LOGICIN[30] bit 6 - -
B22 INT: mux QUAD_NW0[1] bit 2 INT: mux QUAD_WW0[1] bit 2 INT: mux QUAD_NE0[1] bit 1 INT: mux QUAD_NN0[1] bit 1 INT: mux DBL_NN0[1] bit 5 INT: mux DBL_NW0[1] bit 5 INT: mux DBL_EE0[1] bit 5 INT: mux DBL_NE0[1] bit 5 INT: mux SNG_N0[0] bit 5 INT: mux SNG_W0[6] bit 5 INT: mux SNG_N0[5] bit 5 INT: mux SNG_E0[0] bit 5 INT: mux IMUX_LOGICIN[48] bit 0 INT: mux IMUX_LOGICIN[25] bit 0 INT: mux IMUX_LOGICIN[13] bit 2 INT: mux IMUX_LOGICIN[54] bit 2 INT: mux IMUX_LOGICIN[41] bit 0 INT: mux IMUX_LOGICIN[4] bit 0 INT: mux IMUX_LOGICIN[44] bit 2 INT: mux IMUX_LOGICIN[30] bit 2 - -
B21 INT: mux QUAD_NW0[1] bit 1 INT: mux QUAD_WW0[1] bit 1 INT: mux QUAD_NE0[1] bit 2 INT: mux QUAD_NN0[1] bit 2 INT: mux DBL_NN0[1] bit 4 INT: mux DBL_NW0[1] bit 4 INT: mux DBL_EE0[1] bit 4 INT: mux DBL_NE0[1] bit 4 INT: mux SNG_N0[0] bit 4 INT: mux SNG_W0[6] bit 4 INT: mux SNG_N0[5] bit 4 INT: mux SNG_E0[0] bit 4 INT: mux IMUX_LOGICIN[48] bit 3 INT: mux IMUX_LOGICIN[25] bit 3 INT: mux IMUX_LOGICIN[13] bit 3 INT: mux IMUX_LOGICIN[54] bit 3 INT: mux IMUX_LOGICIN[41] bit 3 INT: mux IMUX_LOGICIN[4] bit 3 INT: mux IMUX_LOGICIN[44] bit 3 INT: mux IMUX_LOGICIN[30] bit 3 - -
B20 INT: mux QUAD_NW0[1] bit 0 INT: mux QUAD_WW0[1] bit 0 INT: mux QUAD_NE0[1] bit 0 INT: mux QUAD_NN0[1] bit 0 INT: mux DBL_NN0[1] bit 0 INT: mux DBL_NW0[1] bit 0 INT: mux DBL_EE0[1] bit 0 INT: mux DBL_NE0[1] bit 0 INT: mux SNG_N0[0] bit 0 INT: mux SNG_W0[6] bit 0 INT: mux SNG_N0[5] bit 0 INT: mux SNG_E0[0] bit 0 INT: mux IMUX_LOGICIN[48] bit 1 INT: mux IMUX_LOGICIN[25] bit 1 INT: mux IMUX_LOGICIN[13] bit 0 INT: mux IMUX_LOGICIN[54] bit 0 INT: mux IMUX_LOGICIN[41] bit 1 INT: mux IMUX_LOGICIN[4] bit 1 INT: mux IMUX_LOGICIN[44] bit 0 INT: mux IMUX_LOGICIN[30] bit 0 - -
B19 INT: mux QUAD_NW0[1] bit 5 INT: mux QUAD_WW0[1] bit 5 INT: mux QUAD_NE0[1] bit 5 INT: mux QUAD_NN0[1] bit 5 INT: mux DBL_NN0[1] bit 1 INT: mux DBL_NW0[1] bit 1 INT: mux DBL_EE0[1] bit 1 INT: mux DBL_NE0[1] bit 1 INT: mux SNG_N0[0] bit 1 INT: mux SNG_W0[6] bit 1 INT: mux SNG_N0[5] bit 1 INT: mux SNG_E0[0] bit 1 INT: mux IMUX_LOGICIN[48] bit 2 INT: mux IMUX_LOGICIN[25] bit 2 INT: mux IMUX_LOGICIN[13] bit 1 INT: mux IMUX_LOGICIN[54] bit 1 INT: mux IMUX_LOGICIN[41] bit 2 INT: mux IMUX_LOGICIN[4] bit 2 INT: mux IMUX_LOGICIN[44] bit 1 INT: mux IMUX_LOGICIN[30] bit 1 - -
B18 INT: mux QUAD_NW0[1] bit 3 INT: mux QUAD_WW0[1] bit 3 INT: mux QUAD_NE0[1] bit 3 INT: mux QUAD_NN0[1] bit 3 INT: mux DBL_NN0[1] bit 3 INT: mux DBL_NW0[1] bit 3 INT: mux DBL_EE0[1] bit 3 INT: mux DBL_NE0[1] bit 3 INT: mux SNG_N0[0] bit 3 INT: mux SNG_W0[6] bit 3 INT: mux SNG_N0[5] bit 3 INT: mux SNG_E0[0] bit 3 INT: mux IMUX_LOGICIN[48] bit 4 INT: mux IMUX_LOGICIN[25] bit 4 INT: mux IMUX_LOGICIN[13] bit 4 INT: mux IMUX_LOGICIN[54] bit 4 INT: mux IMUX_LOGICIN[41] bit 4 INT: mux IMUX_LOGICIN[4] bit 4 INT: mux IMUX_LOGICIN[44] bit 4 INT: mux IMUX_LOGICIN[30] bit 4 - -
B17 INT: mux QUAD_NW0[1] bit 4 INT: mux QUAD_WW0[1] bit 4 INT: mux QUAD_NE0[1] bit 4 INT: mux QUAD_NN0[1] bit 4 INT: mux DBL_NN0[1] bit 2 INT: mux DBL_NW0[1] bit 2 INT: mux DBL_EE0[1] bit 2 INT: mux DBL_NE0[1] bit 2 INT: mux SNG_N0[0] bit 2 INT: mux SNG_W0[6] bit 2 INT: mux SNG_N0[5] bit 2 INT: mux SNG_E0[0] bit 2 INT: mux IMUX_LOGICIN[48] bit 5 INT: mux IMUX_LOGICIN[25] bit 5 INT: mux IMUX_LOGICIN[13] bit 5 INT: mux IMUX_LOGICIN[54] bit 5 INT: mux IMUX_LOGICIN[41] bit 5 INT: mux IMUX_LOGICIN[4] bit 5 INT: mux IMUX_LOGICIN[44] bit 5 INT: mux IMUX_LOGICIN[30] bit 5 - -
B16 INT: mux QUAD_NW0[1] bit 6 INT: mux QUAD_NW0[1] bit 7 INT: mux QUAD_NE0[1] bit 6 INT: mux QUAD_NE0[1] bit 7 INT: mux DBL_NN0[1] bit 6 INT: mux DBL_NN0[1] bit 7 INT: mux DBL_EE0[1] bit 6 INT: mux DBL_EE0[1] bit 7 INT: mux SNG_N0[0] bit 6 INT: mux SNG_N0[0] bit 7 INT: mux SNG_N0[5] bit 6 INT: mux SNG_N0[5] bit 7 INT: mux IMUX_LOGICIN[25] bit 6 INT: mux IMUX_LOGICIN[25] bit 7 INT: mux IMUX_LOGICIN[13] bit 7 INT: mux IMUX_LOGICIN[13] bit 6 INT: mux IMUX_LOGICIN[4] bit 6 INT: mux IMUX_LOGICIN[4] bit 7 INT: mux IMUX_LOGICIN[44] bit 7 INT: mux IMUX_LOGICIN[44] bit 6 - -
B15 INT: mux QUAD_SS0[0] bit 6 INT: mux QUAD_SS0[0] bit 7 INT: mux QUAD_EE0[0] bit 6 INT: mux QUAD_EE0[0] bit 7 INT: mux DBL_WW0[0] bit 6 INT: mux DBL_WW0[0] bit 7 INT: mux DBL_SS0[0] bit 6 INT: mux DBL_SS0[0] bit 7 INT: mux SNG_S0[5] bit 6 INT: mux SNG_S0[5] bit 7 INT: mux SNG_S0[0] bit 6 INT: mux SNG_S0[0] bit 7 INT: mux IMUX_LOGICIN[38] bit 6 INT: mux IMUX_LOGICIN[38] bit 7 INT: mux IMUX_LOGICIN[34] bit 7 INT: mux IMUX_LOGICIN[34] bit 6 INT: mux IMUX_LOGICIN[45] bit 6 INT: mux IMUX_LOGICIN[45] bit 7 INT: mux IMUX_LOGICIN[56] bit 7 INT: mux IMUX_LOGICIN[56] bit 6 INT: mux IMUX_GFAN[1] bit 7 -
B14 INT: mux QUAD_SS0[0] bit 3 INT: mux QUAD_SW0[0] bit 3 INT: mux QUAD_EE0[0] bit 2 INT: mux QUAD_SE0[0] bit 2 INT: mux DBL_WW0[0] bit 3 INT: mux DBL_SW0[0] bit 3 INT: mux DBL_SS0[0] bit 3 INT: mux DBL_SE0[0] bit 3 INT: mux SNG_S0[5] bit 3 INT: mux SNG_W0[3] bit 3 INT: mux SNG_S0[0] bit 3 INT: mux SNG_E0[5] bit 3 INT: mux IMUX_LOGICIN[38] bit 2 INT: mux IMUX_LOGICIN[62] bit 2 INT: mux IMUX_LOGICIN[12] bit 0 INT: mux IMUX_LOGICIN[34] bit 0 INT: mux IMUX_LOGICIN[45] bit 2 INT: mux IMUX_LOGICIN[6] bit 2 INT: mux IMUX_LOGICIN[16] bit 0 INT: mux IMUX_LOGICIN[56] bit 0 INT: mux IMUX_GFAN[1] bit 6 -
B13 INT: mux QUAD_SS0[0] bit 0 INT: mux QUAD_SW0[0] bit 0 INT: mux QUAD_EE0[0] bit 4 INT: mux QUAD_SE0[0] bit 4 INT: mux DBL_WW0[0] bit 2 INT: mux DBL_SW0[0] bit 2 INT: mux DBL_SS0[0] bit 2 INT: mux DBL_SE0[0] bit 2 INT: mux SNG_S0[5] bit 2 INT: mux SNG_W0[3] bit 2 INT: mux SNG_S0[0] bit 2 INT: mux SNG_E0[5] bit 2 INT: mux IMUX_LOGICIN[38] bit 3 INT: mux IMUX_LOGICIN[62] bit 3 INT: mux IMUX_LOGICIN[12] bit 3 INT: mux IMUX_LOGICIN[34] bit 3 INT: mux IMUX_LOGICIN[45] bit 3 INT: mux IMUX_LOGICIN[6] bit 3 INT: mux IMUX_LOGICIN[16] bit 3 INT: mux IMUX_LOGICIN[56] bit 3 INT: mux IMUX_GFAN[1] bit 2 -
B12 INT: mux QUAD_SS0[0] bit 5 INT: mux QUAD_SW0[0] bit 5 INT: mux QUAD_EE0[0] bit 5 INT: mux QUAD_SE0[0] bit 5 INT: mux DBL_WW0[0] bit 1 INT: mux DBL_SW0[0] bit 1 INT: mux DBL_SS0[0] bit 1 INT: mux DBL_SE0[0] bit 1 INT: mux SNG_S0[5] bit 1 INT: mux SNG_W0[3] bit 1 INT: mux SNG_S0[0] bit 1 INT: mux SNG_E0[5] bit 1 INT: mux IMUX_LOGICIN[38] bit 0 INT: mux IMUX_LOGICIN[62] bit 0 INT: mux IMUX_LOGICIN[12] bit 1 INT: mux IMUX_LOGICIN[34] bit 1 INT: mux IMUX_LOGICIN[45] bit 0 INT: mux IMUX_LOGICIN[6] bit 0 INT: mux IMUX_LOGICIN[16] bit 2 INT: mux IMUX_LOGICIN[56] bit 2 INT: mux IMUX_GFAN[1] bit 3 -
B11 INT: mux QUAD_SS0[0] bit 2 INT: mux QUAD_SW0[0] bit 2 INT: mux QUAD_EE0[0] bit 1 INT: mux QUAD_SE0[0] bit 1 INT: mux DBL_WW0[0] bit 0 INT: mux DBL_SW0[0] bit 0 INT: mux DBL_SS0[0] bit 0 INT: mux DBL_SE0[0] bit 0 INT: mux SNG_S0[5] bit 0 INT: mux SNG_W0[3] bit 0 INT: mux SNG_S0[0] bit 0 INT: mux SNG_E0[5] bit 0 INT: mux IMUX_LOGICIN[38] bit 1 INT: mux IMUX_LOGICIN[62] bit 1 INT: mux IMUX_LOGICIN[12] bit 2 INT: mux IMUX_LOGICIN[34] bit 2 INT: mux IMUX_LOGICIN[45] bit 1 INT: mux IMUX_LOGICIN[6] bit 1 INT: mux IMUX_LOGICIN[16] bit 1 INT: mux IMUX_LOGICIN[56] bit 1 INT: mux IMUX_GFAN[1] bit 0 -
B10 INT: mux QUAD_SS0[0] bit 4 INT: mux QUAD_SW0[0] bit 4 INT: mux QUAD_EE0[0] bit 3 INT: mux QUAD_SE0[0] bit 3 INT: mux DBL_WW0[0] bit 5 INT: mux DBL_SW0[0] bit 5 INT: mux DBL_SS0[0] bit 5 INT: mux DBL_SE0[0] bit 5 INT: mux SNG_S0[5] bit 5 INT: mux SNG_W0[3] bit 5 INT: mux SNG_S0[0] bit 5 INT: mux SNG_E0[5] bit 5 INT: mux IMUX_LOGICIN[38] bit 4 INT: mux IMUX_LOGICIN[62] bit 4 INT: mux IMUX_LOGICIN[12] bit 4 INT: mux IMUX_LOGICIN[34] bit 4 INT: mux IMUX_LOGICIN[45] bit 4 INT: mux IMUX_LOGICIN[6] bit 4 INT: mux IMUX_LOGICIN[16] bit 4 INT: mux IMUX_LOGICIN[56] bit 4 INT: mux IMUX_GFAN[1] bit 1 -
B9 INT: mux QUAD_SS0[0] bit 1 INT: mux QUAD_SW0[0] bit 1 INT: mux QUAD_EE0[0] bit 0 INT: mux QUAD_SE0[0] bit 0 INT: mux DBL_WW0[0] bit 4 INT: mux DBL_SW0[0] bit 4 INT: mux DBL_SS0[0] bit 4 INT: mux DBL_SE0[0] bit 4 INT: mux SNG_S0[5] bit 4 INT: mux SNG_W0[3] bit 4 INT: mux SNG_S0[0] bit 4 INT: mux SNG_E0[5] bit 4 INT: mux IMUX_LOGICIN[38] bit 5 INT: mux IMUX_LOGICIN[62] bit 5 INT: mux IMUX_LOGICIN[12] bit 5 INT: mux IMUX_LOGICIN[34] bit 5 INT: mux IMUX_LOGICIN[45] bit 5 INT: mux IMUX_LOGICIN[6] bit 5 INT: mux IMUX_LOGICIN[16] bit 5 INT: mux IMUX_LOGICIN[56] bit 5 INT: mux IMUX_GFAN[1] bit 4 -
B8 INT: mux QUAD_SW0[0] bit 7 INT: mux QUAD_SW0[0] bit 6 INT: mux QUAD_SE0[0] bit 7 INT: mux QUAD_SE0[0] bit 6 INT: mux DBL_SW0[0] bit 7 INT: mux DBL_SW0[0] bit 6 INT: mux DBL_SE0[0] bit 7 INT: mux DBL_SE0[0] bit 6 INT: mux SNG_W0[3] bit 7 INT: mux SNG_W0[3] bit 6 INT: mux SNG_E0[5] bit 7 INT: mux SNG_E0[5] bit 6 INT: mux IMUX_LOGICIN[62] bit 6 INT: mux IMUX_LOGICIN[62] bit 7 INT: mux IMUX_LOGICIN[12] bit 7 INT: mux IMUX_LOGICIN[12] bit 6 INT: mux IMUX_LOGICIN[6] bit 6 INT: mux IMUX_LOGICIN[6] bit 7 INT: mux IMUX_LOGICIN[16] bit 7 INT: mux IMUX_LOGICIN[16] bit 6 INT: mux IMUX_GFAN[1] bit 5 -
B7 INT: mux QUAD_WW0[0] bit 7 INT: mux QUAD_WW0[0] bit 6 INT: mux QUAD_NN0[0] bit 7 INT: mux QUAD_NN0[0] bit 6 INT: mux DBL_NW0[0] bit 7 INT: mux DBL_NW0[0] bit 6 INT: mux DBL_NE0[0] bit 7 INT: mux DBL_NE0[0] bit 6 INT: mux SNG_W0[5] bit 7 INT: mux SNG_W0[5] bit 6 INT: mux SNG_E0[3] bit 7 INT: mux SNG_E0[3] bit 6 INT: mux IMUX_LOGICIN[47] bit 6 INT: mux IMUX_LOGICIN[47] bit 7 INT: mux IMUX_LOGICIN[35] bit 7 INT: mux IMUX_LOGICIN[35] bit 6 INT: mux IMUX_LOGICIN[42] bit 6 INT: mux IMUX_LOGICIN[42] bit 7 INT: mux IMUX_LOGICIN[36] bit 7 INT: mux IMUX_LOGICIN[36] bit 6 INT: mux IMUX_GFAN[0] bit 5 -
B6 INT: mux QUAD_NW0[0] bit 2 INT: mux QUAD_WW0[0] bit 2 INT: mux QUAD_NE0[0] bit 1 INT: mux QUAD_NN0[0] bit 1 INT: mux DBL_NN0[0] bit 5 INT: mux DBL_NW0[0] bit 5 INT: mux DBL_EE0[0] bit 5 INT: mux DBL_NE0[0] bit 5 INT: mux SNG_N0[3] bit 5 INT: mux SNG_W0[5] bit 5 INT: mux SNG_N0[4] bit 5 INT: mux SNG_E0[3] bit 5 INT: mux IMUX_LOGICIN[47] bit 0 INT: mux IMUX_LOGICIN[24] bit 0 INT: mux IMUX_LOGICIN[15] bit 2 INT: mux IMUX_LOGICIN[35] bit 2 INT: mux IMUX_LOGICIN[42] bit 0 INT: mux IMUX_LOGICIN[5] bit 0 INT: mux IMUX_LOGICIN[7] bit 2 INT: mux IMUX_LOGICIN[36] bit 2 INT: mux IMUX_GFAN[0] bit 0 -
B5 INT: mux QUAD_NW0[0] bit 1 INT: mux QUAD_WW0[0] bit 1 INT: mux QUAD_NE0[0] bit 2 INT: mux QUAD_NN0[0] bit 2 INT: mux DBL_NN0[0] bit 4 INT: mux DBL_NW0[0] bit 4 INT: mux DBL_EE0[0] bit 4 INT: mux DBL_NE0[0] bit 4 INT: mux SNG_N0[3] bit 4 INT: mux SNG_W0[5] bit 4 INT: mux SNG_N0[4] bit 4 INT: mux SNG_E0[3] bit 4 INT: mux IMUX_LOGICIN[47] bit 3 INT: mux IMUX_LOGICIN[24] bit 3 INT: mux IMUX_LOGICIN[15] bit 3 INT: mux IMUX_LOGICIN[35] bit 3 INT: mux IMUX_LOGICIN[42] bit 3 INT: mux IMUX_LOGICIN[5] bit 3 INT: mux IMUX_LOGICIN[7] bit 3 INT: mux IMUX_LOGICIN[36] bit 3 INT: mux IMUX_GFAN[0] bit 1 -
B4 INT: mux QUAD_NW0[0] bit 0 INT: mux QUAD_WW0[0] bit 0 INT: mux QUAD_NE0[0] bit 0 INT: mux QUAD_NN0[0] bit 0 INT: mux DBL_NN0[0] bit 1 INT: mux DBL_NW0[0] bit 1 INT: mux DBL_EE0[0] bit 0 INT: mux DBL_NE0[0] bit 0 INT: mux SNG_N0[3] bit 1 INT: mux SNG_W0[5] bit 1 INT: mux SNG_N0[4] bit 0 INT: mux SNG_E0[3] bit 0 INT: mux IMUX_LOGICIN[47] bit 1 INT: mux IMUX_LOGICIN[24] bit 1 INT: mux IMUX_LOGICIN[15] bit 0 INT: mux IMUX_LOGICIN[35] bit 0 INT: mux IMUX_LOGICIN[42] bit 1 INT: mux IMUX_LOGICIN[5] bit 1 INT: mux IMUX_LOGICIN[7] bit 1 INT: mux IMUX_LOGICIN[36] bit 1 INT: mux IMUX_GFAN[0] bit 4 -
B3 INT: mux QUAD_NW0[0] bit 5 INT: mux QUAD_WW0[0] bit 5 INT: mux QUAD_NE0[0] bit 5 INT: mux QUAD_NN0[0] bit 5 INT: mux DBL_NN0[0] bit 0 INT: mux DBL_NW0[0] bit 0 INT: mux DBL_EE0[0] bit 1 INT: mux DBL_NE0[0] bit 1 INT: mux SNG_N0[3] bit 0 INT: mux SNG_W0[5] bit 0 INT: mux SNG_N0[4] bit 1 INT: mux SNG_E0[3] bit 1 INT: mux IMUX_LOGICIN[47] bit 2 INT: mux IMUX_LOGICIN[24] bit 2 INT: mux IMUX_LOGICIN[15] bit 1 INT: mux IMUX_LOGICIN[35] bit 1 INT: mux IMUX_LOGICIN[42] bit 2 INT: mux IMUX_LOGICIN[5] bit 2 INT: mux IMUX_LOGICIN[7] bit 0 INT: mux IMUX_LOGICIN[36] bit 0 INT: mux IMUX_GFAN[0] bit 3 -
B2 INT: mux QUAD_NW0[0] bit 3 INT: mux QUAD_WW0[0] bit 3 INT: mux QUAD_NE0[0] bit 3 INT: mux QUAD_NN0[0] bit 3 INT: mux DBL_NN0[0] bit 3 INT: mux DBL_NW0[0] bit 3 INT: mux DBL_EE0[0] bit 3 INT: mux DBL_NE0[0] bit 3 INT: mux SNG_N0[3] bit 3 INT: mux SNG_W0[5] bit 3 INT: mux SNG_N0[4] bit 3 INT: mux SNG_E0[3] bit 3 INT: mux IMUX_LOGICIN[47] bit 4 INT: mux IMUX_LOGICIN[24] bit 4 INT: mux IMUX_LOGICIN[15] bit 4 INT: mux IMUX_LOGICIN[35] bit 4 INT: mux IMUX_LOGICIN[42] bit 4 INT: mux IMUX_LOGICIN[5] bit 4 INT: mux IMUX_LOGICIN[7] bit 4 INT: mux IMUX_LOGICIN[36] bit 4 INT: mux IMUX_GFAN[0] bit 2 -
B1 INT: mux QUAD_NW0[0] bit 4 INT: mux QUAD_WW0[0] bit 4 INT: mux QUAD_NE0[0] bit 4 INT: mux QUAD_NN0[0] bit 4 INT: mux DBL_NN0[0] bit 2 INT: mux DBL_NW0[0] bit 2 INT: mux DBL_EE0[0] bit 2 INT: mux DBL_NE0[0] bit 2 INT: mux SNG_N0[3] bit 2 INT: mux SNG_W0[5] bit 2 INT: mux SNG_N0[4] bit 2 INT: mux SNG_E0[3] bit 2 INT: mux IMUX_LOGICIN[47] bit 5 INT: mux IMUX_LOGICIN[24] bit 5 INT: mux IMUX_LOGICIN[15] bit 5 INT: mux IMUX_LOGICIN[35] bit 5 INT: mux IMUX_LOGICIN[42] bit 5 INT: mux IMUX_LOGICIN[5] bit 5 INT: mux IMUX_LOGICIN[7] bit 5 INT: mux IMUX_LOGICIN[36] bit 5 INT: mux IMUX_GFAN[0] bit 6 -
B0 INT: mux QUAD_NW0[0] bit 6 INT: mux QUAD_NW0[0] bit 7 INT: mux QUAD_NE0[0] bit 6 INT: mux QUAD_NE0[0] bit 7 INT: mux DBL_NN0[0] bit 6 INT: mux DBL_NN0[0] bit 7 INT: mux DBL_EE0[0] bit 6 INT: mux DBL_EE0[0] bit 7 INT: mux SNG_N0[3] bit 6 INT: mux SNG_N0[3] bit 7 INT: mux SNG_N0[4] bit 6 INT: mux SNG_N0[4] bit 7 INT: mux IMUX_LOGICIN[24] bit 6 INT: mux IMUX_LOGICIN[24] bit 7 INT: mux IMUX_LOGICIN[15] bit 7 INT: mux IMUX_LOGICIN[15] bit 6 INT: mux IMUX_LOGICIN[5] bit 6 INT: mux IMUX_LOGICIN[5] bit 7 INT: mux IMUX_LOGICIN[7] bit 7 INT: mux IMUX_LOGICIN[7] bit 6 INT: mux IMUX_GFAN[0] bit 7 -

Tile INT_IOI

Cells: 1

Switchbox INT

spartan6 INT_IOI switchbox INT permanent buffers
DestinationSource
IMUX_LOGICIN20_BOUNCEIMUX_LOGICIN[20]
IMUX_LOGICIN36_BOUNCEIMUX_LOGICIN[36]
IMUX_LOGICIN44_BOUNCEIMUX_LOGICIN[44]
IMUX_LOGICIN62_BOUNCEIMUX_LOGICIN[62]
IMUX_LOGICIN21_BOUNCEIMUX_LOGICIN[21]
IMUX_LOGICIN28_BOUNCEIMUX_LOGICIN[28]
IMUX_LOGICIN52_BOUNCEIMUX_LOGICIN[52]
IMUX_LOGICIN60_BOUNCEIMUX_LOGICIN[60]
spartan6 INT_IOI switchbox INT muxes SNG_W0[0]
BitsDestination
MAIN[8][24]MAIN[9][24]MAIN[9][26]MAIN[9][25]MAIN[9][30]MAIN[9][29]MAIN[9][28]MAIN[9][27]SNG_W0[0]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes SNG_W0[1]
BitsDestination
MAIN[8][40]MAIN[9][40]MAIN[9][42]MAIN[9][41]MAIN[9][46]MAIN[9][45]MAIN[9][44]MAIN[9][43]SNG_W0[1]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes SNG_W0[2]
BitsDestination
MAIN[8][56]MAIN[9][56]MAIN[9][58]MAIN[9][57]MAIN[9][62]MAIN[9][61]MAIN[9][60]MAIN[9][59]SNG_W0[2]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes SNG_W0[3]
BitsDestination
MAIN[8][8]MAIN[9][8]MAIN[9][10]MAIN[9][9]MAIN[9][14]MAIN[9][13]MAIN[9][12]MAIN[9][11]SNG_W0[3]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes SNG_W0[4]
BitsDestination
MAIN[8][55]MAIN[9][55]MAIN[9][54]MAIN[9][53]MAIN[9][50]MAIN[9][49]MAIN[9][51]MAIN[9][52]SNG_W0[4]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes SNG_W0[5]
BitsDestination
MAIN[8][7]MAIN[9][7]MAIN[9][6]MAIN[9][5]MAIN[9][2]MAIN[9][1]MAIN[9][4]MAIN[9][3]SNG_W0[5]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes SNG_W0[6]
BitsDestination
MAIN[8][23]MAIN[9][23]MAIN[9][22]MAIN[9][21]MAIN[9][18]MAIN[9][17]MAIN[9][19]MAIN[9][20]SNG_W0[6]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes SNG_W0[7]
BitsDestination
MAIN[8][39]MAIN[9][39]MAIN[9][38]MAIN[9][37]MAIN[9][34]MAIN[9][33]MAIN[9][35]MAIN[9][36]SNG_W0[7]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes SNG_E0[0]
BitsDestination
MAIN[10][23]MAIN[11][23]MAIN[11][22]MAIN[11][21]MAIN[11][18]MAIN[11][17]MAIN[11][19]MAIN[11][20]SNG_E0[0]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes SNG_E0[1]
BitsDestination
MAIN[10][39]MAIN[11][39]MAIN[11][38]MAIN[11][37]MAIN[11][34]MAIN[11][33]MAIN[11][35]MAIN[11][36]SNG_E0[1]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes SNG_E0[2]
BitsDestination
MAIN[10][55]MAIN[11][55]MAIN[11][54]MAIN[11][53]MAIN[11][50]MAIN[11][49]MAIN[11][51]MAIN[11][52]SNG_E0[2]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes SNG_E0[3]
BitsDestination
MAIN[10][7]MAIN[11][7]MAIN[11][6]MAIN[11][5]MAIN[11][2]MAIN[11][1]MAIN[11][3]MAIN[11][4]SNG_E0[3]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes SNG_E0[4]
BitsDestination
MAIN[10][56]MAIN[11][56]MAIN[11][58]MAIN[11][57]MAIN[11][62]MAIN[11][61]MAIN[11][60]MAIN[11][59]SNG_E0[4]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes SNG_E0[5]
BitsDestination
MAIN[10][8]MAIN[11][8]MAIN[11][10]MAIN[11][9]MAIN[11][14]MAIN[11][13]MAIN[11][12]MAIN[11][11]SNG_E0[5]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes SNG_E0[6]
BitsDestination
MAIN[10][24]MAIN[11][24]MAIN[11][26]MAIN[11][25]MAIN[11][30]MAIN[11][29]MAIN[11][28]MAIN[11][27]SNG_E0[6]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes SNG_E0[7]
BitsDestination
MAIN[10][40]MAIN[11][40]MAIN[11][42]MAIN[11][41]MAIN[11][46]MAIN[11][45]MAIN[11][44]MAIN[11][43]SNG_E0[7]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes SNG_S0[0]
BitsDestination
MAIN[11][15]MAIN[10][15]MAIN[10][10]MAIN[10][9]MAIN[10][14]MAIN[10][13]MAIN[10][12]MAIN[10][11]SNG_S0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes SNG_S0[1]
BitsDestination
MAIN[11][31]MAIN[10][31]MAIN[10][26]MAIN[10][25]MAIN[10][30]MAIN[10][29]MAIN[10][28]MAIN[10][27]SNG_S0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes SNG_S0[2]
BitsDestination
MAIN[11][47]MAIN[10][47]MAIN[10][42]MAIN[10][41]MAIN[10][46]MAIN[10][45]MAIN[10][44]MAIN[10][43]SNG_S0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes SNG_S0[3]
BitsDestination
MAIN[11][63]MAIN[10][63]MAIN[10][58]MAIN[10][57]MAIN[10][62]MAIN[10][61]MAIN[10][60]MAIN[10][59]SNG_S0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes SNG_S0[4]
BitsDestination
MAIN[9][63]MAIN[8][63]MAIN[8][58]MAIN[8][57]MAIN[8][62]MAIN[8][61]MAIN[8][60]MAIN[8][59]SNG_S0[4]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes SNG_S0[5]
BitsDestination
MAIN[9][15]MAIN[8][15]MAIN[8][10]MAIN[8][9]MAIN[8][14]MAIN[8][13]MAIN[8][12]MAIN[8][11]SNG_S0[5]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes SNG_S0[6]
BitsDestination
MAIN[9][31]MAIN[8][31]MAIN[8][26]MAIN[8][25]MAIN[8][30]MAIN[8][29]MAIN[8][28]MAIN[8][27]SNG_S0[6]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes SNG_S0[7]
BitsDestination
MAIN[9][47]MAIN[8][47]MAIN[8][42]MAIN[8][41]MAIN[8][46]MAIN[8][45]MAIN[8][44]MAIN[8][43]SNG_S0[7]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes SNG_N0[0]
BitsDestination
MAIN[9][16]MAIN[8][16]MAIN[8][22]MAIN[8][21]MAIN[8][18]MAIN[8][17]MAIN[8][19]MAIN[8][20]SNG_N0[0]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes SNG_N0[1]
BitsDestination
MAIN[9][32]MAIN[8][32]MAIN[8][38]MAIN[8][37]MAIN[8][34]MAIN[8][33]MAIN[8][35]MAIN[8][36]SNG_N0[1]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes SNG_N0[2]
BitsDestination
MAIN[9][48]MAIN[8][48]MAIN[8][54]MAIN[8][53]MAIN[8][50]MAIN[8][49]MAIN[8][51]MAIN[8][52]SNG_N0[2]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes SNG_N0[3]
BitsDestination
MAIN[9][0]MAIN[8][0]MAIN[8][6]MAIN[8][5]MAIN[8][2]MAIN[8][1]MAIN[8][4]MAIN[8][3]SNG_N0[3]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes SNG_N0[4]
BitsDestination
MAIN[11][0]MAIN[10][0]MAIN[10][6]MAIN[10][5]MAIN[10][2]MAIN[10][1]MAIN[10][3]MAIN[10][4]SNG_N0[4]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes SNG_N0[5]
BitsDestination
MAIN[11][16]MAIN[10][16]MAIN[10][22]MAIN[10][21]MAIN[10][18]MAIN[10][17]MAIN[10][19]MAIN[10][20]SNG_N0[5]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes SNG_N0[6]
BitsDestination
MAIN[11][32]MAIN[10][32]MAIN[10][38]MAIN[10][37]MAIN[10][34]MAIN[10][33]MAIN[10][35]MAIN[10][36]SNG_N0[6]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes SNG_N0[7]
BitsDestination
MAIN[11][48]MAIN[10][48]MAIN[10][54]MAIN[10][53]MAIN[10][50]MAIN[10][49]MAIN[10][51]MAIN[10][52]SNG_N0[7]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes DBL_WW0[0]
BitsDestination
MAIN[5][15]MAIN[4][15]MAIN[4][10]MAIN[4][9]MAIN[4][14]MAIN[4][13]MAIN[4][12]MAIN[4][11]DBL_WW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes DBL_WW0[1]
BitsDestination
MAIN[5][31]MAIN[4][31]MAIN[4][26]MAIN[4][25]MAIN[4][30]MAIN[4][29]MAIN[4][28]MAIN[4][27]DBL_WW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes DBL_WW0[2]
BitsDestination
MAIN[5][47]MAIN[4][47]MAIN[4][42]MAIN[4][41]MAIN[4][46]MAIN[4][45]MAIN[4][44]MAIN[4][43]DBL_WW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes DBL_WW0[3]
BitsDestination
MAIN[5][63]MAIN[4][63]MAIN[4][58]MAIN[4][57]MAIN[4][62]MAIN[4][61]MAIN[4][60]MAIN[4][59]DBL_WW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes DBL_EE0[0]
BitsDestination
MAIN[7][0]MAIN[6][0]MAIN[6][6]MAIN[6][5]MAIN[6][2]MAIN[6][1]MAIN[6][3]MAIN[6][4]DBL_EE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes DBL_EE0[1]
BitsDestination
MAIN[7][16]MAIN[6][16]MAIN[6][22]MAIN[6][21]MAIN[6][18]MAIN[6][17]MAIN[6][19]MAIN[6][20]DBL_EE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes DBL_EE0[2]
BitsDestination
MAIN[7][32]MAIN[6][32]MAIN[6][38]MAIN[6][37]MAIN[6][34]MAIN[6][33]MAIN[6][35]MAIN[6][36]DBL_EE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes DBL_EE0[3]
BitsDestination
MAIN[7][48]MAIN[6][48]MAIN[6][54]MAIN[6][53]MAIN[6][50]MAIN[6][49]MAIN[6][51]MAIN[6][52]DBL_EE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes DBL_SS0[0]
BitsDestination
MAIN[7][15]MAIN[6][15]MAIN[6][10]MAIN[6][9]MAIN[6][14]MAIN[6][13]MAIN[6][12]MAIN[6][11]DBL_SS0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes DBL_SS0[1]
BitsDestination
MAIN[7][31]MAIN[6][31]MAIN[6][26]MAIN[6][25]MAIN[6][30]MAIN[6][29]MAIN[6][28]MAIN[6][27]DBL_SS0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes DBL_SS0[2]
BitsDestination
MAIN[7][47]MAIN[6][47]MAIN[6][42]MAIN[6][41]MAIN[6][46]MAIN[6][45]MAIN[6][44]MAIN[6][43]DBL_SS0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes DBL_SS0[3]
BitsDestination
MAIN[7][63]MAIN[6][63]MAIN[6][58]MAIN[6][57]MAIN[6][62]MAIN[6][61]MAIN[6][60]MAIN[6][59]DBL_SS0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes DBL_SW0[0]
BitsDestination
MAIN[4][8]MAIN[5][8]MAIN[5][10]MAIN[5][9]MAIN[5][14]MAIN[5][13]MAIN[5][12]MAIN[5][11]DBL_SW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_NW4[1]
00100000QUAD_WW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes DBL_SW0[1]
BitsDestination
MAIN[4][24]MAIN[5][24]MAIN[5][26]MAIN[5][25]MAIN[5][30]MAIN[5][29]MAIN[5][28]MAIN[5][27]DBL_SW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_NW4[2]
00100000QUAD_WW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes DBL_SW0[2]
BitsDestination
MAIN[4][40]MAIN[5][40]MAIN[5][42]MAIN[5][41]MAIN[5][46]MAIN[5][45]MAIN[5][44]MAIN[5][43]DBL_SW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_NW4[3]
00100000QUAD_WW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes DBL_SW0[3]
BitsDestination
MAIN[4][56]MAIN[5][56]MAIN[5][58]MAIN[5][57]MAIN[5][62]MAIN[5][61]MAIN[5][60]MAIN[5][59]DBL_SW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_NW2_S0
00001000DBL_WW2[3]
00010000QUAD_NW4_S0
00100000QUAD_WW4_S0
01000001SNG_W1[3]
01000010SNG_W1_S4
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes DBL_SE0[0]
BitsDestination
MAIN[6][8]MAIN[7][8]MAIN[7][10]MAIN[7][9]MAIN[7][14]MAIN[7][13]MAIN[7][12]MAIN[7][11]DBL_SE0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_SW4[0]
00000100DBL_EE2[0]
00001000DBL_SE2[0]
00010000QUAD_EE4[0]
00100000QUAD_SE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_S1[0]
01001000SNG_S1[4]
01010000DBL_SS2[0]
01100000DBL_SW2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[2]
10001000OUT[0]
10010000OUT[19]
10100000OUT[14]
spartan6 INT_IOI switchbox INT muxes DBL_SE0[1]
BitsDestination
MAIN[6][24]MAIN[7][24]MAIN[7][26]MAIN[7][25]MAIN[7][30]MAIN[7][29]MAIN[7][28]MAIN[7][27]DBL_SE0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_SW4[1]
00000100DBL_EE2[1]
00001000DBL_SE2[1]
00010000QUAD_EE4[1]
00100000QUAD_SE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_S1[1]
01001000SNG_S1[5]
01010000DBL_SS2[1]
01100000DBL_SW2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[5]
10001000OUT[3]
10010000OUT[22]
10100000OUT[17]
spartan6 INT_IOI switchbox INT muxes DBL_SE0[2]
BitsDestination
MAIN[6][40]MAIN[7][40]MAIN[7][42]MAIN[7][41]MAIN[7][46]MAIN[7][45]MAIN[7][44]MAIN[7][43]DBL_SE0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_SW4[2]
00000100DBL_EE2[2]
00001000DBL_SE2[2]
00010000QUAD_EE4[2]
00100000QUAD_SE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_S1[2]
01001000SNG_S1[6]
01010000DBL_SS2[2]
01100000DBL_SW2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[8]
10001000OUT[6]
10010000OUT[13]
10100000OUT[20]
spartan6 INT_IOI switchbox INT muxes DBL_SE0[3]
BitsDestination
MAIN[6][56]MAIN[7][56]MAIN[7][58]MAIN[7][57]MAIN[7][62]MAIN[7][61]MAIN[7][60]MAIN[7][59]DBL_SE0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_SW4[3]
00000100DBL_EE2[3]
00001000DBL_SE2[3]
00010000QUAD_EE4[3]
00100000QUAD_SE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_S1[3]
01001000SNG_S1[7]
01010000DBL_SS2[3]
01100000DBL_SW2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[11]
10001000OUT[9]
10010000OUT[16]
10100000OUT[23]
spartan6 INT_IOI switchbox INT muxes DBL_NN0[0]
BitsDestination
MAIN[5][0]MAIN[4][0]MAIN[4][6]MAIN[4][5]MAIN[4][2]MAIN[4][1]MAIN[4][4]MAIN[4][3]DBL_NN0[0]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes DBL_NN0[1]
BitsDestination
MAIN[5][16]MAIN[4][16]MAIN[4][22]MAIN[4][21]MAIN[4][18]MAIN[4][17]MAIN[4][19]MAIN[4][20]DBL_NN0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes DBL_NN0[2]
BitsDestination
MAIN[5][32]MAIN[4][32]MAIN[4][38]MAIN[4][37]MAIN[4][34]MAIN[4][33]MAIN[4][35]MAIN[4][36]DBL_NN0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes DBL_NN0[3]
BitsDestination
MAIN[5][48]MAIN[4][48]MAIN[4][54]MAIN[4][53]MAIN[4][50]MAIN[4][49]MAIN[4][51]MAIN[4][52]DBL_NN0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes DBL_NW0[0]
BitsDestination
MAIN[4][7]MAIN[5][7]MAIN[5][6]MAIN[5][5]MAIN[5][2]MAIN[5][1]MAIN[5][4]MAIN[5][3]DBL_NW0[0]
Source
00000000off
00000001QUAD_NN4[0]
00000010QUAD_NE4[0]
00000100DBL_NW2[0]
00001000DBL_WW2_N3
00010000QUAD_WW4[0]
00100000QUAD_NW4[0]
01000001SNG_W1[4]
01000010SNG_W1_N3
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[7]
10000010OUT[12]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes DBL_NW0[1]
BitsDestination
MAIN[4][23]MAIN[5][23]MAIN[5][22]MAIN[5][21]MAIN[5][18]MAIN[5][17]MAIN[5][19]MAIN[5][20]DBL_NW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_NW2[1]
00001000DBL_WW2[0]
00010000QUAD_WW4[1]
00100000QUAD_NW4[1]
01000001SNG_W1[0]
01000010SNG_W1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes DBL_NW0[2]
BitsDestination
MAIN[4][39]MAIN[5][39]MAIN[5][38]MAIN[5][37]MAIN[5][34]MAIN[5][33]MAIN[5][35]MAIN[5][36]DBL_NW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_NW2[2]
00001000DBL_WW2[1]
00010000QUAD_WW4[2]
00100000QUAD_NW4[2]
01000001SNG_W1[1]
01000010SNG_W1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes DBL_NW0[3]
BitsDestination
MAIN[4][55]MAIN[5][55]MAIN[5][54]MAIN[5][53]MAIN[5][50]MAIN[5][49]MAIN[5][51]MAIN[5][52]DBL_NW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_NW2[3]
00001000DBL_WW2[2]
00010000QUAD_WW4[3]
00100000QUAD_NW4[3]
01000001SNG_W1[2]
01000010SNG_W1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes DBL_NE0[0]
BitsDestination
MAIN[6][7]MAIN[7][7]MAIN[7][6]MAIN[7][5]MAIN[7][2]MAIN[7][1]MAIN[7][3]MAIN[7][4]DBL_NE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_NN4[0]
00000100DBL_SE2[0]
00001000DBL_EE2[0]
00010000QUAD_SE4[0]
00100000QUAD_EE4[0]
01000001SNG_E1[0]
01000010SNG_E1[4]
01000100SNG_N1[0]
01001000SNG_N1[4]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[7]
10000100OUT[0]
10001000OUT[2]
10010000OUT[14]
10100000OUT[19]
spartan6 INT_IOI switchbox INT muxes DBL_NE0[1]
BitsDestination
MAIN[6][23]MAIN[7][23]MAIN[7][22]MAIN[7][21]MAIN[7][18]MAIN[7][17]MAIN[7][19]MAIN[7][20]DBL_NE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_NN4[1]
00000100DBL_SE2[1]
00001000DBL_EE2[1]
00010000QUAD_SE4[1]
00100000QUAD_EE4[1]
01000001SNG_E1[1]
01000010SNG_E1[5]
01000100SNG_N1[1]
01001000SNG_N1[5]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[10]
10000100OUT[3]
10001000OUT[5]
10010000OUT[17]
10100000OUT[22]
spartan6 INT_IOI switchbox INT muxes DBL_NE0[2]
BitsDestination
MAIN[6][39]MAIN[7][39]MAIN[7][38]MAIN[7][37]MAIN[7][34]MAIN[7][33]MAIN[7][35]MAIN[7][36]DBL_NE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_NN4[2]
00000100DBL_SE2[2]
00001000DBL_EE2[2]
00010000QUAD_SE4[2]
00100000QUAD_EE4[2]
01000001SNG_E1[2]
01000010SNG_E1[6]
01000100SNG_N1[2]
01001000SNG_N1[6]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[1]
10000100OUT[6]
10001000OUT[8]
10010000OUT[20]
10100000OUT[13]
spartan6 INT_IOI switchbox INT muxes DBL_NE0[3]
BitsDestination
MAIN[6][55]MAIN[7][55]MAIN[7][54]MAIN[7][53]MAIN[7][50]MAIN[7][49]MAIN[7][51]MAIN[7][52]DBL_NE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_NN4[3]
00000100DBL_SE2[3]
00001000DBL_EE2[3]
00010000QUAD_SE4[3]
00100000QUAD_EE4[3]
01000001SNG_E1[3]
01000010SNG_E1[7]
01000100SNG_N1[3]
01001000SNG_N1[7]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[4]
10000100OUT[9]
10001000OUT[11]
10010000OUT[23]
10100000OUT[16]
spartan6 INT_IOI switchbox INT muxes QUAD_WW0[0]
BitsDestination
MAIN[0][7]MAIN[1][7]MAIN[1][3]MAIN[1][1]MAIN[1][2]MAIN[1][6]MAIN[1][5]MAIN[1][4]QUAD_WW0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_SS4_N3
00000100QUAD_SW4_N3
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_SS2_N3
01000100DBL_SW2_N3
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[14]
10000100OUT[19]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_WW0[1]
BitsDestination
MAIN[0][23]MAIN[1][23]MAIN[1][19]MAIN[1][17]MAIN[1][18]MAIN[1][22]MAIN[1][21]MAIN[1][20]QUAD_WW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_SS4[0]
00000100QUAD_SW4[0]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[17]
10000100OUT[22]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_WW0[2]
BitsDestination
MAIN[0][39]MAIN[1][39]MAIN[1][35]MAIN[1][33]MAIN[1][34]MAIN[1][38]MAIN[1][37]MAIN[1][36]QUAD_WW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_SS4[1]
00000100QUAD_SW4[1]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[20]
10000100OUT[13]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_WW0[3]
BitsDestination
MAIN[0][55]MAIN[1][55]MAIN[1][51]MAIN[1][49]MAIN[1][50]MAIN[1][54]MAIN[1][53]MAIN[1][52]QUAD_WW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_SS4[2]
00000100QUAD_SW4[2]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[23]
10000100OUT[16]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_EE0[0]
BitsDestination
MAIN[3][15]MAIN[2][15]MAIN[2][12]MAIN[2][13]MAIN[2][10]MAIN[2][14]MAIN[2][11]MAIN[2][9]QUAD_EE0[0]
Source
00000000off
00000001QUAD_EE4[0]
00000010QUAD_NE4[0]
00000100QUAD_SW4[0]
00001000QUAD_SE4[0]
00010000QUAD_SS4[0]
00100000QUAD_NN4[0]
01000001DBL_EE2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_SE2[0]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[19]
10000010OUT[12]
10000100OUT[0]
10001000OUT[14]
10010000OUT[2]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_EE0[1]
BitsDestination
MAIN[3][31]MAIN[2][31]MAIN[2][28]MAIN[2][29]MAIN[2][26]MAIN[2][30]MAIN[2][27]MAIN[2][25]QUAD_EE0[1]
Source
00000000off
00000001QUAD_EE4[1]
00000010QUAD_NE4[1]
00000100QUAD_SW4[1]
00001000QUAD_SE4[1]
00010000QUAD_SS4[1]
00100000QUAD_NN4[1]
01000001DBL_EE2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_SE2[1]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[22]
10000010OUT[15]
10000100OUT[3]
10001000OUT[17]
10010000OUT[5]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_EE0[2]
BitsDestination
MAIN[3][47]MAIN[2][47]MAIN[2][44]MAIN[2][45]MAIN[2][42]MAIN[2][46]MAIN[2][43]MAIN[2][41]QUAD_EE0[2]
Source
00000000off
00000001QUAD_EE4[2]
00000010QUAD_NE4[2]
00000100QUAD_SW4[2]
00001000QUAD_SE4[2]
00010000QUAD_SS4[2]
00100000QUAD_NN4[2]
01000001DBL_EE2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_SE2[2]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[13]
10000010OUT[18]
10000100OUT[6]
10001000OUT[20]
10010000OUT[8]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_EE0[3]
BitsDestination
MAIN[3][63]MAIN[2][63]MAIN[2][60]MAIN[2][61]MAIN[2][58]MAIN[2][62]MAIN[2][59]MAIN[2][57]QUAD_EE0[3]
Source
00000000off
00000001QUAD_EE4[3]
00000010QUAD_NE4[3]
00000100QUAD_SW4[3]
00001000QUAD_SE4[3]
00010000QUAD_SS4[3]
00100000QUAD_NN4[3]
01000001DBL_EE2[3]
01000010DBL_SS2[3]
01000100DBL_SW2[3]
01001000DBL_SE2[3]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[16]
10000010OUT[21]
10000100OUT[9]
10001000OUT[23]
10010000OUT[11]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_SS0[0]
BitsDestination
MAIN[1][15]MAIN[0][15]MAIN[0][12]MAIN[0][10]MAIN[0][14]MAIN[0][11]MAIN[0][9]MAIN[0][13]QUAD_SS0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_EE4[0]
00000100QUAD_NW4[1]
00001000QUAD_SW4[0]
00010000QUAD_SE4[0]
00100000QUAD_WW4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[0]
01000100DBL_SS2[0]
01001000DBL_SW2[0]
01010000DBL_SE2[0]
01100000DBL_NW2[1]
10000001OUT[2]
10000010OUT[19]
10000100OUT[12]
10001000OUT[0]
10010000OUT[14]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_SS0[1]
BitsDestination
MAIN[1][31]MAIN[0][31]MAIN[0][28]MAIN[0][26]MAIN[0][30]MAIN[0][27]MAIN[0][25]MAIN[0][29]QUAD_SS0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_EE4[1]
00000100QUAD_NW4[2]
00001000QUAD_SW4[1]
00010000QUAD_SE4[1]
00100000QUAD_WW4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[1]
01000100DBL_SS2[1]
01001000DBL_SW2[1]
01010000DBL_SE2[1]
01100000DBL_NW2[2]
10000001OUT[5]
10000010OUT[22]
10000100OUT[15]
10001000OUT[3]
10010000OUT[17]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_SS0[2]
BitsDestination
MAIN[1][47]MAIN[0][47]MAIN[0][44]MAIN[0][42]MAIN[0][46]MAIN[0][43]MAIN[0][41]MAIN[0][45]QUAD_SS0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_EE4[2]
00000100QUAD_NW4[3]
00001000QUAD_SW4[2]
00010000QUAD_SE4[2]
00100000QUAD_WW4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[2]
01000100DBL_SS2[2]
01001000DBL_SW2[2]
01010000DBL_SE2[2]
01100000DBL_NW2[3]
10000001OUT[8]
10000010OUT[13]
10000100OUT[18]
10001000OUT[6]
10010000OUT[20]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_SS0[3]
BitsDestination
MAIN[1][63]MAIN[0][63]MAIN[0][60]MAIN[0][58]MAIN[0][62]MAIN[0][59]MAIN[0][57]MAIN[0][61]QUAD_SS0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_EE4[3]
00000100QUAD_NW4_S0
00001000QUAD_SW4[3]
00010000QUAD_SE4[3]
00100000QUAD_WW4_S0
01000001DBL_WW2[3]
01000010DBL_EE2[3]
01000100DBL_SS2[3]
01001000DBL_SW2[3]
01010000DBL_SE2[3]
01100000DBL_NW2_S0
10000001OUT[11]
10000010OUT[16]
10000100OUT[21]
10001000OUT[9]
10010000OUT[23]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_SW0[0]
BitsDestination
MAIN[0][8]MAIN[1][8]MAIN[1][12]MAIN[1][10]MAIN[1][14]MAIN[1][11]MAIN[1][9]MAIN[1][13]QUAD_SW0[0]
Source
00000000off
00000001QUAD_SS4[0]
00000010QUAD_EE4[0]
00000100QUAD_NW4[1]
00001000QUAD_SW4[0]
00010000QUAD_SE4[0]
00100000QUAD_WW4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[0]
01000100DBL_SS2[0]
01001000DBL_SW2[0]
01010000DBL_SE2[0]
01100000DBL_NW2[1]
10000001OUT[2]
10000010OUT[19]
10000100OUT[12]
10001000OUT[0]
10010000OUT[14]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_SW0[1]
BitsDestination
MAIN[0][24]MAIN[1][24]MAIN[1][28]MAIN[1][26]MAIN[1][30]MAIN[1][27]MAIN[1][25]MAIN[1][29]QUAD_SW0[1]
Source
00000000off
00000001QUAD_SS4[1]
00000010QUAD_EE4[1]
00000100QUAD_NW4[2]
00001000QUAD_SW4[1]
00010000QUAD_SE4[1]
00100000QUAD_WW4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[1]
01000100DBL_SS2[1]
01001000DBL_SW2[1]
01010000DBL_SE2[1]
01100000DBL_NW2[2]
10000001OUT[5]
10000010OUT[22]
10000100OUT[15]
10001000OUT[3]
10010000OUT[17]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_SW0[2]
BitsDestination
MAIN[0][40]MAIN[1][40]MAIN[1][44]MAIN[1][42]MAIN[1][46]MAIN[1][43]MAIN[1][41]MAIN[1][45]QUAD_SW0[2]
Source
00000000off
00000001QUAD_SS4[2]
00000010QUAD_EE4[2]
00000100QUAD_NW4[3]
00001000QUAD_SW4[2]
00010000QUAD_SE4[2]
00100000QUAD_WW4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[2]
01000100DBL_SS2[2]
01001000DBL_SW2[2]
01010000DBL_SE2[2]
01100000DBL_NW2[3]
10000001OUT[8]
10000010OUT[13]
10000100OUT[18]
10001000OUT[6]
10010000OUT[20]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_SW0[3]
BitsDestination
MAIN[0][56]MAIN[1][56]MAIN[1][60]MAIN[1][58]MAIN[1][62]MAIN[1][59]MAIN[1][57]MAIN[1][61]QUAD_SW0[3]
Source
00000000off
00000001QUAD_SS4[3]
00000010QUAD_EE4[3]
00000100QUAD_NW4_S0
00001000QUAD_SW4[3]
00010000QUAD_SE4[3]
00100000QUAD_WW4_S0
01000001DBL_WW2[3]
01000010DBL_EE2[3]
01000100DBL_SS2[3]
01001000DBL_SW2[3]
01010000DBL_SE2[3]
01100000DBL_NW2_S0
10000001OUT[11]
10000010OUT[16]
10000100OUT[21]
10001000OUT[9]
10010000OUT[23]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_SE0[0]
BitsDestination
MAIN[2][8]MAIN[3][8]MAIN[3][12]MAIN[3][13]MAIN[3][10]MAIN[3][14]MAIN[3][11]MAIN[3][9]QUAD_SE0[0]
Source
00000000off
00000001QUAD_EE4[0]
00000010QUAD_NE4[0]
00000100QUAD_SW4[0]
00001000QUAD_SE4[0]
00010000QUAD_SS4[0]
00100000QUAD_NN4[0]
01000001DBL_EE2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_SE2[0]
01010000DBL_NN2[0]
01100000DBL_NE2[0]
10000001OUT[19]
10000010OUT[12]
10000100OUT[0]
10001000OUT[14]
10010000OUT[2]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_SE0[1]
BitsDestination
MAIN[2][24]MAIN[3][24]MAIN[3][28]MAIN[3][29]MAIN[3][26]MAIN[3][30]MAIN[3][27]MAIN[3][25]QUAD_SE0[1]
Source
00000000off
00000001QUAD_EE4[1]
00000010QUAD_NE4[1]
00000100QUAD_SW4[1]
00001000QUAD_SE4[1]
00010000QUAD_SS4[1]
00100000QUAD_NN4[1]
01000001DBL_EE2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_SE2[1]
01010000DBL_NN2[1]
01100000DBL_NE2[1]
10000001OUT[22]
10000010OUT[15]
10000100OUT[3]
10001000OUT[17]
10010000OUT[5]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_SE0[2]
BitsDestination
MAIN[2][40]MAIN[3][40]MAIN[3][44]MAIN[3][45]MAIN[3][42]MAIN[3][46]MAIN[3][43]MAIN[3][41]QUAD_SE0[2]
Source
00000000off
00000001QUAD_EE4[2]
00000010QUAD_NE4[2]
00000100QUAD_SW4[2]
00001000QUAD_SE4[2]
00010000QUAD_SS4[2]
00100000QUAD_NN4[2]
01000001DBL_EE2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_SE2[2]
01010000DBL_NN2[2]
01100000DBL_NE2[2]
10000001OUT[13]
10000010OUT[18]
10000100OUT[6]
10001000OUT[20]
10010000OUT[8]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_SE0[3]
BitsDestination
MAIN[2][56]MAIN[3][56]MAIN[3][60]MAIN[3][61]MAIN[3][58]MAIN[3][62]MAIN[3][59]MAIN[3][57]QUAD_SE0[3]
Source
00000000off
00000001QUAD_EE4[3]
00000010QUAD_NE4[3]
00000100QUAD_SW4[3]
00001000QUAD_SE4[3]
00010000QUAD_SS4[3]
00100000QUAD_NN4[3]
01000001DBL_EE2[3]
01000010DBL_SS2[3]
01000100DBL_SW2[3]
01001000DBL_SE2[3]
01010000DBL_NN2[3]
01100000DBL_NE2[3]
10000001OUT[16]
10000010OUT[21]
10000100OUT[9]
10001000OUT[23]
10010000OUT[11]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_NN0[0]
BitsDestination
MAIN[2][7]MAIN[3][7]MAIN[3][3]MAIN[3][1]MAIN[3][2]MAIN[3][5]MAIN[3][6]MAIN[3][4]QUAD_NN0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_EE4[0]
00000100QUAD_SE4[0]
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_EE2[0]
01000100DBL_SE2[0]
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[19]
10000100OUT[14]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_NN0[1]
BitsDestination
MAIN[2][23]MAIN[3][23]MAIN[3][19]MAIN[3][17]MAIN[3][18]MAIN[3][21]MAIN[3][22]MAIN[3][20]QUAD_NN0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_EE4[1]
00000100QUAD_SE4[1]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[1]
01000100DBL_SE2[1]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[22]
10000100OUT[17]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_NN0[2]
BitsDestination
MAIN[2][39]MAIN[3][39]MAIN[3][35]MAIN[3][33]MAIN[3][34]MAIN[3][37]MAIN[3][38]MAIN[3][36]QUAD_NN0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_EE4[2]
00000100QUAD_SE4[2]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[2]
01000100DBL_SE2[2]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[13]
10000100OUT[20]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_NN0[3]
BitsDestination
MAIN[2][55]MAIN[3][55]MAIN[3][51]MAIN[3][49]MAIN[3][50]MAIN[3][53]MAIN[3][54]MAIN[3][52]QUAD_NN0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_EE4[3]
00000100QUAD_SE4[3]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[3]
01000100DBL_SE2[3]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[16]
10000100OUT[23]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_NW0[0]
BitsDestination
MAIN[1][0]MAIN[0][0]MAIN[0][3]MAIN[0][1]MAIN[0][2]MAIN[0][6]MAIN[0][5]MAIN[0][4]QUAD_NW0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_SS4_N3
00000100QUAD_SW4_N3
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_SS2_N3
01000100DBL_SW2_N3
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[14]
10000100OUT[19]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_NW0[1]
BitsDestination
MAIN[1][16]MAIN[0][16]MAIN[0][19]MAIN[0][17]MAIN[0][18]MAIN[0][22]MAIN[0][21]MAIN[0][20]QUAD_NW0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_SS4[0]
00000100QUAD_SW4[0]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_SS2[0]
01000100DBL_SW2[0]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[17]
10000100OUT[22]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_NW0[2]
BitsDestination
MAIN[1][32]MAIN[0][32]MAIN[0][35]MAIN[0][33]MAIN[0][34]MAIN[0][38]MAIN[0][37]MAIN[0][36]QUAD_NW0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_SS4[1]
00000100QUAD_SW4[1]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_SS2[1]
01000100DBL_SW2[1]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[20]
10000100OUT[13]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_NW0[3]
BitsDestination
MAIN[1][48]MAIN[0][48]MAIN[0][51]MAIN[0][49]MAIN[0][50]MAIN[0][54]MAIN[0][53]MAIN[0][52]QUAD_NW0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_SS4[2]
00000100QUAD_SW4[2]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_SS2[2]
01000100DBL_SW2[2]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[23]
10000100OUT[16]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes QUAD_NE0[0]
BitsDestination
MAIN[3][0]MAIN[2][0]MAIN[2][3]MAIN[2][1]MAIN[2][2]MAIN[2][5]MAIN[2][6]MAIN[2][4]QUAD_NE0[0]
Source
00000000off
00000001QUAD_NE4[0]
00000010QUAD_EE4[0]
00000100QUAD_SE4[0]
00001000QUAD_NW4[0]
00010000QUAD_WW4[0]
00100000QUAD_NN4[0]
01000001DBL_WW2_N3
01000010DBL_EE2[0]
01000100DBL_SE2[0]
01001000DBL_NN2[0]
01010000DBL_NW2[0]
01100000DBL_NE2[0]
10000001OUT[12]
10000010OUT[19]
10000100OUT[14]
10001000OUT[2]
10010000OUT[0]
10100000OUT[7]
spartan6 INT_IOI switchbox INT muxes QUAD_NE0[1]
BitsDestination
MAIN[3][16]MAIN[2][16]MAIN[2][19]MAIN[2][17]MAIN[2][18]MAIN[2][21]MAIN[2][22]MAIN[2][20]QUAD_NE0[1]
Source
00000000off
00000001QUAD_NE4[1]
00000010QUAD_EE4[1]
00000100QUAD_SE4[1]
00001000QUAD_NW4[1]
00010000QUAD_WW4[1]
00100000QUAD_NN4[1]
01000001DBL_WW2[0]
01000010DBL_EE2[1]
01000100DBL_SE2[1]
01001000DBL_NN2[1]
01010000DBL_NW2[1]
01100000DBL_NE2[1]
10000001OUT[15]
10000010OUT[22]
10000100OUT[17]
10001000OUT[5]
10010000OUT[3]
10100000OUT[10]
spartan6 INT_IOI switchbox INT muxes QUAD_NE0[2]
BitsDestination
MAIN[3][32]MAIN[2][32]MAIN[2][35]MAIN[2][33]MAIN[2][34]MAIN[2][37]MAIN[2][38]MAIN[2][36]QUAD_NE0[2]
Source
00000000off
00000001QUAD_NE4[2]
00000010QUAD_EE4[2]
00000100QUAD_SE4[2]
00001000QUAD_NW4[2]
00010000QUAD_WW4[2]
00100000QUAD_NN4[2]
01000001DBL_WW2[1]
01000010DBL_EE2[2]
01000100DBL_SE2[2]
01001000DBL_NN2[2]
01010000DBL_NW2[2]
01100000DBL_NE2[2]
10000001OUT[18]
10000010OUT[13]
10000100OUT[20]
10001000OUT[8]
10010000OUT[6]
10100000OUT[1]
spartan6 INT_IOI switchbox INT muxes QUAD_NE0[3]
BitsDestination
MAIN[3][48]MAIN[2][48]MAIN[2][51]MAIN[2][49]MAIN[2][50]MAIN[2][53]MAIN[2][54]MAIN[2][52]QUAD_NE0[3]
Source
00000000off
00000001QUAD_NE4[3]
00000010QUAD_EE4[3]
00000100QUAD_SE4[3]
00001000QUAD_NW4[3]
00010000QUAD_WW4[3]
00100000QUAD_NN4[3]
01000001DBL_WW2[2]
01000010DBL_EE2[3]
01000100DBL_SE2[3]
01001000DBL_NN2[3]
01010000DBL_NW2[3]
01100000DBL_NE2[3]
10000001OUT[21]
10000010OUT[16]
10000100OUT[23]
10001000OUT[11]
10010000OUT[9]
10100000OUT[4]
spartan6 INT_IOI switchbox INT muxes IMUX_GFAN[0]
BitsDestination
MAIN[20][0]MAIN[20][1]MAIN[20][7]MAIN[20][4]MAIN[20][3]MAIN[20][2]MAIN[20][5]MAIN[20][6]IMUX_GFAN[0]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[5]
01001000SNG_E1[5]
01010000SNG_N1[5]
01100000SNG_W1[5]
10000001IMUX_LOGICIN[35]
10000010IMUX_LOGICIN[6]
10000100HCLK[6]
10001000HCLK[7]
10010000IMUX_LOGICIN[53]
10100000IMUX_LOGICIN[51]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT_IOI switchbox INT muxes IMUX_GFAN[1]
BitsDestination
MAIN[20][15]MAIN[20][14]MAIN[20][8]MAIN[20][9]MAIN[20][12]MAIN[20][13]MAIN[20][10]MAIN[20][11]IMUX_GFAN[1]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[5]
01001000SNG_E1[5]
01010000SNG_N1[5]
01100000SNG_W1[5]
10000001IMUX_LOGICIN[35]
10000010IMUX_LOGICIN[6]
10000100HCLK[6]
10001000HCLK[7]
10010000IMUX_LOGICIN[53]
10100000IMUX_LOGICIN[51]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT_IOI switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[20][38]MAIN[20][39]MAIN[20][32]MAIN[20][35]MAIN[20][36]MAIN[20][37]MAIN[20][34]MAIN[20][33]IMUX_CLK[0]
Source
00000000PULLUP
00000001TIE_0
00000010TIE_1
00000100SNG_N1[6]
00001000SNG_W1[6]
00010000SNG_S1[5]
00100000SNG_E1[5]
01000001HCLK[10]
01000010HCLK[11]
01000100HCLK[6]
01001000HCLK[7]
01010000HCLK[8]
01100000HCLK[9]
10000001IMUX_LOGICIN[53]
10000010IMUX_LOGICIN[43]
10000100HCLK[12]
10001000HCLK[13]
10010000HCLK[14]
10100000HCLK[15]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT_IOI switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[20][25]MAIN[20][24]MAIN[20][31]MAIN[20][30]MAIN[20][27]MAIN[20][26]MAIN[20][29]MAIN[20][28]IMUX_CLK[1]
Source
00000000PULLUP
00000001TIE_0
00000010TIE_1
00000100SNG_N1[6]
00001000SNG_W1[6]
00010000SNG_S1[5]
00100000SNG_E1[5]
01000001HCLK[10]
01000010HCLK[11]
01000100HCLK[6]
01001000HCLK[7]
01010000HCLK[8]
01100000HCLK[9]
10000001IMUX_LOGICIN[53]
10000010IMUX_LOGICIN[43]
10000100HCLK[12]
10001000HCLK[13]
10010000HCLK[14]
10100000HCLK[15]
11000001HCLK[4]
11000010HCLK[5]
11000100HCLK[0]
11001000HCLK[1]
11010000HCLK[2]
11100000HCLK[3]
spartan6 INT_IOI switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[20][63]MAIN[20][62]MAIN[20][56]MAIN[20][59]MAIN[20][60]MAIN[20][61]MAIN[20][58]MAIN[20][57]IMUX_SR[0]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[6]
01001000SNG_E1[6]
01010000SNG_N1[6]
01100000SNG_W1[6]
10000001IMUX_LOGICIN[13]
10000010IMUX_LOGICIN[43]
10000100HCLK[14]
10001000HCLK[15]
10010000IMUX_LOGICIN[61]
10100000IMUX_LOGICIN[63]
11000001HCLK[12]
11000010HCLK[13]
11000100HCLK[8]
11001000HCLK[9]
11010000HCLK[10]
11100000HCLK[11]
spartan6 INT_IOI switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[20][48]MAIN[20][49]MAIN[20][55]MAIN[20][54]MAIN[20][51]MAIN[20][50]MAIN[20][53]MAIN[20][52]IMUX_SR[1]
Source
00000000PULLUP
01000001TIE_0
01000010TIE_1
01000100SNG_S1[6]
01001000SNG_E1[6]
01010000SNG_N1[6]
01100000SNG_W1[6]
10000001IMUX_LOGICIN[13]
10000010IMUX_LOGICIN[43]
10000100HCLK[14]
10001000HCLK[15]
10010000IMUX_LOGICIN[61]
10100000IMUX_LOGICIN[63]
11000001HCLK[12]
11000010HCLK[13]
11000100HCLK[8]
11001000HCLK[9]
11010000HCLK[10]
11100000HCLK[11]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[0]
BitsDestination
MAIN[13][31]MAIN[12][31]MAIN[12][25]MAIN[12][26]MAIN[12][29]MAIN[12][27]MAIN[12][28]MAIN[12][30]IMUX_LOGICIN[0]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[1]
BitsDestination
MAIN[13][40]MAIN[12][40]MAIN[13][41]MAIN[13][42]MAIN[13][45]MAIN[13][43]MAIN[13][44]MAIN[13][46]IMUX_LOGICIN[1]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[2]
BitsDestination
MAIN[17][48]MAIN[16][48]MAIN[17][49]MAIN[17][50]MAIN[17][53]MAIN[17][51]MAIN[17][52]MAIN[17][54]IMUX_LOGICIN[2]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[3]
BitsDestination
MAIN[17][32]MAIN[16][32]MAIN[17][33]MAIN[17][34]MAIN[17][37]MAIN[17][35]MAIN[17][36]MAIN[17][38]IMUX_LOGICIN[3]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[5]
BitsDestination
MAIN[17][0]MAIN[16][0]MAIN[17][1]MAIN[17][2]MAIN[17][5]MAIN[17][3]MAIN[17][4]MAIN[17][6]IMUX_LOGICIN[5]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[6]
BitsDestination
MAIN[17][8]MAIN[16][8]MAIN[17][9]MAIN[17][10]MAIN[17][13]MAIN[17][11]MAIN[17][12]MAIN[17][14]IMUX_LOGICIN[6]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[7]
BitsDestination
MAIN[18][0]MAIN[19][0]MAIN[18][1]MAIN[18][2]MAIN[18][5]MAIN[18][4]MAIN[18][3]MAIN[18][6]IMUX_LOGICIN[7]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[8]
BitsDestination
MAIN[18][55]MAIN[19][55]MAIN[19][49]MAIN[19][50]MAIN[19][53]MAIN[19][51]MAIN[19][52]MAIN[19][54]IMUX_LOGICIN[8]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[9]
BitsDestination
MAIN[14][56]MAIN[15][56]MAIN[14][57]MAIN[14][58]MAIN[14][61]MAIN[14][59]MAIN[14][60]MAIN[14][62]IMUX_LOGICIN[9]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[11]
BitsDestination
MAIN[14][24]MAIN[15][24]MAIN[14][25]MAIN[14][26]MAIN[14][29]MAIN[14][27]MAIN[14][28]MAIN[14][30]IMUX_LOGICIN[11]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[12]
BitsDestination
MAIN[14][8]MAIN[15][8]MAIN[14][9]MAIN[14][10]MAIN[14][13]MAIN[14][11]MAIN[14][12]MAIN[14][14]IMUX_LOGICIN[12]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[13]
BitsDestination
MAIN[14][16]MAIN[15][16]MAIN[14][17]MAIN[14][18]MAIN[14][21]MAIN[14][19]MAIN[14][20]MAIN[14][22]IMUX_LOGICIN[13]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[14]
BitsDestination
MAIN[14][55]MAIN[15][55]MAIN[15][49]MAIN[15][50]MAIN[15][53]MAIN[15][51]MAIN[15][52]MAIN[15][54]IMUX_LOGICIN[14]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[15]
BitsDestination
MAIN[14][0]MAIN[15][0]MAIN[14][1]MAIN[14][2]MAIN[14][5]MAIN[14][3]MAIN[14][4]MAIN[14][6]IMUX_LOGICIN[15]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[16]
BitsDestination
MAIN[18][8]MAIN[19][8]MAIN[18][9]MAIN[18][10]MAIN[18][13]MAIN[18][12]MAIN[18][11]MAIN[18][14]IMUX_LOGICIN[16]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[17]
BitsDestination
MAIN[18][24]MAIN[19][24]MAIN[18][25]MAIN[18][26]MAIN[18][29]MAIN[18][27]MAIN[18][28]MAIN[18][30]IMUX_LOGICIN[17]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[18]
BitsDestination
MAIN[18][40]MAIN[19][40]MAIN[18][41]MAIN[18][42]MAIN[18][45]MAIN[18][43]MAIN[18][44]MAIN[18][46]IMUX_LOGICIN[18]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[19]
BitsDestination
MAIN[18][56]MAIN[19][56]MAIN[18][57]MAIN[18][58]MAIN[18][61]MAIN[18][59]MAIN[18][60]MAIN[18][62]IMUX_LOGICIN[19]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[20]
BitsDestination
MAIN[13][24]MAIN[12][24]MAIN[13][25]MAIN[13][26]MAIN[13][29]MAIN[13][27]MAIN[13][28]MAIN[13][30]IMUX_LOGICIN[20]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[21]
BitsDestination
MAIN[17][47]MAIN[16][47]MAIN[16][41]MAIN[16][42]MAIN[16][45]MAIN[16][43]MAIN[16][44]MAIN[16][46]IMUX_LOGICIN[21]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[22]
BitsDestination
MAIN[17][40]MAIN[16][40]MAIN[17][41]MAIN[17][42]MAIN[17][45]MAIN[17][43]MAIN[17][44]MAIN[17][46]IMUX_LOGICIN[22]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[23]
BitsDestination
MAIN[17][24]MAIN[16][24]MAIN[17][25]MAIN[17][26]MAIN[17][29]MAIN[17][27]MAIN[17][28]MAIN[17][30]IMUX_LOGICIN[23]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[24]
BitsDestination
MAIN[13][0]MAIN[12][0]MAIN[13][1]MAIN[13][2]MAIN[13][5]MAIN[13][3]MAIN[13][4]MAIN[13][6]IMUX_LOGICIN[24]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[25]
BitsDestination
MAIN[13][16]MAIN[12][16]MAIN[13][17]MAIN[13][18]MAIN[13][21]MAIN[13][19]MAIN[13][20]MAIN[13][22]IMUX_LOGICIN[25]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[26]
BitsDestination
MAIN[13][32]MAIN[12][32]MAIN[13][33]MAIN[13][34]MAIN[13][37]MAIN[13][35]MAIN[13][36]MAIN[13][38]IMUX_LOGICIN[26]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[27]
BitsDestination
MAIN[13][48]MAIN[12][48]MAIN[13][49]MAIN[13][50]MAIN[13][53]MAIN[13][51]MAIN[13][52]MAIN[13][54]IMUX_LOGICIN[27]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[28]
BitsDestination
MAIN[14][48]MAIN[15][48]MAIN[14][49]MAIN[14][50]MAIN[14][53]MAIN[14][51]MAIN[14][52]MAIN[14][54]IMUX_LOGICIN[28]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[29]
BitsDestination
MAIN[18][39]MAIN[19][39]MAIN[19][33]MAIN[19][34]MAIN[19][37]MAIN[19][35]MAIN[19][36]MAIN[19][38]IMUX_LOGICIN[29]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[30]
BitsDestination
MAIN[18][23]MAIN[19][23]MAIN[19][17]MAIN[19][18]MAIN[19][21]MAIN[19][19]MAIN[19][20]MAIN[19][22]IMUX_LOGICIN[30]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[31]
BitsDestination
MAIN[14][63]MAIN[15][63]MAIN[15][57]MAIN[15][58]MAIN[15][61]MAIN[15][59]MAIN[15][60]MAIN[15][62]IMUX_LOGICIN[31]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2_S0
00100000DBL_NN2_S0
01000001SNG_E1_S0
01000010SNG_W1[3]
01000100SNG_W1_S4
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[32]
BitsDestination
MAIN[14][47]MAIN[15][47]MAIN[15][41]MAIN[15][42]MAIN[15][45]MAIN[15][43]MAIN[15][44]MAIN[15][46]IMUX_LOGICIN[32]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[33]
BitsDestination
MAIN[14][31]MAIN[15][31]MAIN[15][25]MAIN[15][26]MAIN[15][29]MAIN[15][27]MAIN[15][28]MAIN[15][30]IMUX_LOGICIN[33]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[34]
BitsDestination
MAIN[14][15]MAIN[15][15]MAIN[15][9]MAIN[15][10]MAIN[15][13]MAIN[15][11]MAIN[15][12]MAIN[15][14]IMUX_LOGICIN[34]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[35]
BitsDestination
MAIN[14][7]MAIN[15][7]MAIN[15][1]MAIN[15][2]MAIN[15][5]MAIN[15][3]MAIN[15][4]MAIN[15][6]IMUX_LOGICIN[35]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[36]
BitsDestination
MAIN[18][7]MAIN[19][7]MAIN[19][1]MAIN[19][2]MAIN[19][5]MAIN[19][4]MAIN[19][3]MAIN[19][6]IMUX_LOGICIN[36]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[37]
BitsDestination
MAIN[13][63]MAIN[12][63]MAIN[12][57]MAIN[12][58]MAIN[12][61]MAIN[12][59]MAIN[12][60]MAIN[12][62]IMUX_LOGICIN[37]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[38]
BitsDestination
MAIN[13][15]MAIN[12][15]MAIN[12][9]MAIN[12][10]MAIN[12][13]MAIN[12][11]MAIN[12][12]MAIN[12][14]IMUX_LOGICIN[38]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[39]
BitsDestination
MAIN[17][55]MAIN[16][55]MAIN[16][49]MAIN[16][50]MAIN[16][53]MAIN[16][51]MAIN[16][52]MAIN[16][54]IMUX_LOGICIN[39]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[40]
BitsDestination
MAIN[17][39]MAIN[16][39]MAIN[16][33]MAIN[16][34]MAIN[16][37]MAIN[16][35]MAIN[16][36]MAIN[16][38]IMUX_LOGICIN[40]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[41]
BitsDestination
MAIN[17][23]MAIN[16][23]MAIN[16][17]MAIN[16][18]MAIN[16][21]MAIN[16][19]MAIN[16][20]MAIN[16][22]IMUX_LOGICIN[41]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[42]
BitsDestination
MAIN[17][7]MAIN[16][7]MAIN[16][1]MAIN[16][2]MAIN[16][5]MAIN[16][3]MAIN[16][4]MAIN[16][6]IMUX_LOGICIN[42]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[43]
BitsDestination
MAIN[17][31]MAIN[16][31]MAIN[16][25]MAIN[16][26]MAIN[16][29]MAIN[16][27]MAIN[16][28]MAIN[16][30]IMUX_LOGICIN[43]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[44]
BitsDestination
MAIN[18][16]MAIN[19][16]MAIN[18][17]MAIN[18][18]MAIN[18][21]MAIN[18][19]MAIN[18][20]MAIN[18][22]IMUX_LOGICIN[44]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[45]
BitsDestination
MAIN[17][15]MAIN[16][15]MAIN[16][9]MAIN[16][10]MAIN[16][13]MAIN[16][11]MAIN[16][12]MAIN[16][14]IMUX_LOGICIN[45]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[0]
00000100DBL_WW2_N3
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[0]
10000100SNG_N1[4]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[2]
11000100OUT[19]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[46]
BitsDestination
MAIN[17][63]MAIN[16][63]MAIN[16][57]MAIN[16][58]MAIN[16][61]MAIN[16][59]MAIN[16][60]MAIN[16][62]IMUX_LOGICIN[46]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[47]
BitsDestination
MAIN[13][7]MAIN[12][7]MAIN[12][1]MAIN[12][2]MAIN[12][5]MAIN[12][3]MAIN[12][4]MAIN[12][6]IMUX_LOGICIN[47]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[48]
BitsDestination
MAIN[13][23]MAIN[12][23]MAIN[12][17]MAIN[12][18]MAIN[12][21]MAIN[12][19]MAIN[12][20]MAIN[12][22]IMUX_LOGICIN[48]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[1]
01000100SNG_W1[5]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[49]
BitsDestination
MAIN[13][39]MAIN[12][39]MAIN[12][33]MAIN[12][34]MAIN[12][37]MAIN[12][35]MAIN[12][36]MAIN[12][38]IMUX_LOGICIN[49]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[50]
BitsDestination
MAIN[13][55]MAIN[12][55]MAIN[12][49]MAIN[12][50]MAIN[12][53]MAIN[12][51]MAIN[12][52]MAIN[12][54]IMUX_LOGICIN[50]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[51]
BitsDestination
MAIN[18][32]MAIN[19][32]MAIN[18][33]MAIN[18][34]MAIN[18][37]MAIN[18][35]MAIN[18][36]MAIN[18][38]IMUX_LOGICIN[51]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[52]
BitsDestination
MAIN[14][39]MAIN[15][39]MAIN[15][33]MAIN[15][34]MAIN[15][37]MAIN[15][35]MAIN[15][36]MAIN[15][38]IMUX_LOGICIN[52]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[53]
BitsDestination
MAIN[13][47]MAIN[12][47]MAIN[12][41]MAIN[12][42]MAIN[12][45]MAIN[12][43]MAIN[12][44]MAIN[12][46]IMUX_LOGICIN[53]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[2]
01000100SNG_W1[6]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[54]
BitsDestination
MAIN[14][23]MAIN[15][23]MAIN[15][17]MAIN[15][18]MAIN[15][21]MAIN[15][19]MAIN[15][20]MAIN[15][22]IMUX_LOGICIN[54]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[61]
10000010SNG_N1[2]
10000100SNG_N1[5]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[1]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[5]
11000100OUT[22]
11001000OUT[15]
11010000IMUX_LOGICIN[35]
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[55]
BitsDestination
MAIN[14][32]MAIN[15][32]MAIN[14][33]MAIN[14][34]MAIN[14][37]MAIN[14][35]MAIN[14][36]MAIN[14][38]IMUX_LOGICIN[55]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[13]
10000010SNG_N1[3]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[61]
10010000SNG_S1[2]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[20]
11000100OUT[1]
11001000OUT[6]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN[35]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[56]
BitsDestination
MAIN[18][15]MAIN[19][15]MAIN[19][9]MAIN[19][10]MAIN[19][13]MAIN[19][12]MAIN[19][11]MAIN[19][14]IMUX_LOGICIN[56]
Source
00000000PULLUP
00000001DBL_SS2_N3
00000010DBL_WW2_N3
00000100DBL_NW2[0]
00001000DBL_SW2_N3
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[4]
01000100SNG_W1_N3
01001000SNG_E1_N7
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN21_N
10000010SNG_N1[4]
10000100SNG_N1[0]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[0]
10100000SNG_S1_N7
11000001TIE_1
11000010OUT[19]
11000100OUT[2]
11001000OUT[12]
11010000IMUX_LOGICIN44_BOUNCE
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[57]
BitsDestination
MAIN[18][31]MAIN[19][31]MAIN[19][25]MAIN[19][26]MAIN[19][29]MAIN[19][27]MAIN[19][28]MAIN[19][30]IMUX_LOGICIN[57]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[1]
00100000DBL_NN2[1]
01000001SNG_E1[1]
01000010SNG_W1[0]
01000100SNG_W1[5]
01001000SNG_E1[4]
01010000DBL_EE2[1]
01100000DBL_SE2[1]
10000001IMUX_LOGICIN[63]
10000010SNG_N1[1]
10000100SNG_N1[5]
10001000IMUX_LOGICIN60_N
10010000SNG_S1[1]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[17]
11000100OUT[10]
11001000OUT[3]
11010000IMUX_LOGICIN[6]
11100000IMUX_LOGICIN[51]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[58]
BitsDestination
MAIN[18][47]MAIN[19][47]MAIN[19][41]MAIN[19][42]MAIN[19][45]MAIN[19][43]MAIN[19][44]MAIN[19][46]IMUX_LOGICIN[58]
Source
00000000PULLUP
00000001DBL_SS2[1]
00000010DBL_NW2[2]
00000100DBL_WW2[1]
00001000DBL_SW2[1]
00010000DBL_NE2[2]
00100000DBL_NN2[2]
01000001SNG_E1[2]
01000010SNG_W1[1]
01000100SNG_W1[6]
01001000SNG_E1[5]
01010000DBL_EE2[2]
01100000DBL_SE2[2]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[2]
10000100SNG_N1[6]
10001000IMUX_LOGICIN[63]
10010000SNG_S1[2]
10100000SNG_S1[5]
11000001TIE_1
11000010OUT[8]
11000100OUT[13]
11001000OUT[18]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN[6]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[59]
BitsDestination
MAIN[18][63]MAIN[19][63]MAIN[19][57]MAIN[19][58]MAIN[19][61]MAIN[19][59]MAIN[19][60]MAIN[19][62]IMUX_LOGICIN[59]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[60]
BitsDestination
MAIN[17][56]MAIN[16][56]MAIN[17][57]MAIN[17][58]MAIN[17][61]MAIN[17][59]MAIN[17][60]MAIN[17][62]IMUX_LOGICIN[60]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[61]
BitsDestination
MAIN[13][56]MAIN[12][56]MAIN[13][57]MAIN[13][58]MAIN[13][61]MAIN[13][59]MAIN[13][60]MAIN[13][62]IMUX_LOGICIN[61]
Source
00000000PULLUP
00000001DBL_SS2[3]
00000010DBL_NW2_S0
00000100DBL_WW2[3]
00001000DBL_SW2[3]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[3]
01000100SNG_W1[7]
01001000SNG_E1[7]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[13]
10000010SNG_N1_S0
10000100SNG_N1[7]
10001000IMUX_LOGICIN52_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[7]
11000001TIE_1
11000010OUT[11]
11000100OUT[16]
11001000OUT[21]
11010000IMUX_LOGICIN62_S
11100000IMUX_LOGICIN20_S
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[62]
BitsDestination
MAIN[13][8]MAIN[12][8]MAIN[13][9]MAIN[13][10]MAIN[13][13]MAIN[13][11]MAIN[13][12]MAIN[13][14]IMUX_LOGICIN[62]
Source
00000000PULLUP
00000001DBL_SS2[0]
00000010DBL_NW2[1]
00000100DBL_WW2[0]
00001000DBL_SW2[0]
00010000DBL_NE2[0]
00100000DBL_NN2[0]
01000001SNG_E1[0]
01000010SNG_W1[0]
01000100SNG_W1[4]
01001000SNG_E1[4]
01010000DBL_EE2[0]
01100000DBL_SE2[0]
10000001IMUX_LOGICIN52_N
10000010SNG_N1[1]
10000100SNG_N1[4]
10001000IMUX_LOGICIN28_N
10010000SNG_S1[0]
10100000SNG_S1[4]
11000001TIE_1
11000010OUT[14]
11000100OUT[7]
11001000OUT[0]
11010000IMUX_LOGICIN20_BOUNCE
11100000IMUX_LOGICIN[53]
spartan6 INT_IOI switchbox INT muxes IMUX_LOGICIN[63]
BitsDestination
MAIN[18][48]MAIN[19][48]MAIN[18][49]MAIN[18][50]MAIN[18][53]MAIN[18][51]MAIN[18][52]MAIN[18][54]IMUX_LOGICIN[63]
Source
00000000PULLUP
00000001DBL_SS2[2]
00000010DBL_NW2[3]
00000100DBL_WW2[2]
00001000DBL_SW2[2]
00010000DBL_NE2[3]
00100000DBL_NN2[3]
01000001SNG_E1[3]
01000010SNG_W1[2]
01000100SNG_W1[7]
01001000SNG_E1[6]
01010000DBL_EE2[3]
01100000DBL_SE2[3]
10000001IMUX_LOGICIN[43]
10000010SNG_N1[3]
10000100SNG_N1[7]
10001000IMUX_LOGICIN21_BOUNCE
10010000SNG_S1[3]
10100000SNG_S1[6]
11000001TIE_1
11000010OUT[23]
11000100OUT[4]
11001000OUT[9]
11010000IMUX_LOGICIN36_S
11100000IMUX_LOGICIN44_S

Bitstream

spartan6 INT_IOI rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B63 INT: mux QUAD_SS0[3] bit 6 INT: mux QUAD_SS0[3] bit 7 INT: mux QUAD_EE0[3] bit 6 INT: mux QUAD_EE0[3] bit 7 INT: mux DBL_WW0[3] bit 6 INT: mux DBL_WW0[3] bit 7 INT: mux DBL_SS0[3] bit 6 INT: mux DBL_SS0[3] bit 7 INT: mux SNG_S0[4] bit 6 INT: mux SNG_S0[4] bit 7 INT: mux SNG_S0[3] bit 6 INT: mux SNG_S0[3] bit 7 INT: mux IMUX_LOGICIN[37] bit 6 INT: mux IMUX_LOGICIN[37] bit 7 INT: mux IMUX_LOGICIN[31] bit 7 INT: mux IMUX_LOGICIN[31] bit 6 INT: mux IMUX_LOGICIN[46] bit 6 INT: mux IMUX_LOGICIN[46] bit 7 INT: mux IMUX_LOGICIN[59] bit 7 INT: mux IMUX_LOGICIN[59] bit 6 INT: mux IMUX_SR[0] bit 7 -
B62 INT: mux QUAD_SS0[3] bit 3 INT: mux QUAD_SW0[3] bit 3 INT: mux QUAD_EE0[3] bit 2 INT: mux QUAD_SE0[3] bit 2 INT: mux DBL_WW0[3] bit 3 INT: mux DBL_SW0[3] bit 3 INT: mux DBL_SS0[3] bit 3 INT: mux DBL_SE0[3] bit 3 INT: mux SNG_S0[4] bit 3 INT: mux SNG_W0[2] bit 3 INT: mux SNG_S0[3] bit 3 INT: mux SNG_E0[4] bit 3 INT: mux IMUX_LOGICIN[37] bit 0 INT: mux IMUX_LOGICIN[61] bit 0 INT: mux IMUX_LOGICIN[9] bit 0 INT: mux IMUX_LOGICIN[31] bit 0 INT: mux IMUX_LOGICIN[46] bit 0 INT: mux IMUX_LOGICIN[60] bit 0 INT: mux IMUX_LOGICIN[19] bit 0 INT: mux IMUX_LOGICIN[59] bit 0 INT: mux IMUX_SR[0] bit 6 -
B61 INT: mux QUAD_SS0[3] bit 0 INT: mux QUAD_SW0[3] bit 0 INT: mux QUAD_EE0[3] bit 4 INT: mux QUAD_SE0[3] bit 4 INT: mux DBL_WW0[3] bit 2 INT: mux DBL_SW0[3] bit 2 INT: mux DBL_SS0[3] bit 2 INT: mux DBL_SE0[3] bit 2 INT: mux SNG_S0[4] bit 2 INT: mux SNG_W0[2] bit 2 INT: mux SNG_S0[3] bit 2 INT: mux SNG_E0[4] bit 2 INT: mux IMUX_LOGICIN[37] bit 3 INT: mux IMUX_LOGICIN[61] bit 3 INT: mux IMUX_LOGICIN[9] bit 3 INT: mux IMUX_LOGICIN[31] bit 3 INT: mux IMUX_LOGICIN[46] bit 3 INT: mux IMUX_LOGICIN[60] bit 3 INT: mux IMUX_LOGICIN[19] bit 3 INT: mux IMUX_LOGICIN[59] bit 3 INT: mux IMUX_SR[0] bit 2 -
B60 INT: mux QUAD_SS0[3] bit 5 INT: mux QUAD_SW0[3] bit 5 INT: mux QUAD_EE0[3] bit 5 INT: mux QUAD_SE0[3] bit 5 INT: mux DBL_WW0[3] bit 1 INT: mux DBL_SW0[3] bit 1 INT: mux DBL_SS0[3] bit 1 INT: mux DBL_SE0[3] bit 1 INT: mux SNG_S0[4] bit 1 INT: mux SNG_W0[2] bit 1 INT: mux SNG_S0[3] bit 1 INT: mux SNG_E0[4] bit 1 INT: mux IMUX_LOGICIN[37] bit 1 INT: mux IMUX_LOGICIN[61] bit 1 INT: mux IMUX_LOGICIN[9] bit 1 INT: mux IMUX_LOGICIN[31] bit 1 INT: mux IMUX_LOGICIN[46] bit 1 INT: mux IMUX_LOGICIN[60] bit 1 INT: mux IMUX_LOGICIN[19] bit 1 INT: mux IMUX_LOGICIN[59] bit 1 INT: mux IMUX_SR[0] bit 3 -
B59 INT: mux QUAD_SS0[3] bit 2 INT: mux QUAD_SW0[3] bit 2 INT: mux QUAD_EE0[3] bit 1 INT: mux QUAD_SE0[3] bit 1 INT: mux DBL_WW0[3] bit 0 INT: mux DBL_SW0[3] bit 0 INT: mux DBL_SS0[3] bit 0 INT: mux DBL_SE0[3] bit 0 INT: mux SNG_S0[4] bit 0 INT: mux SNG_W0[2] bit 0 INT: mux SNG_S0[3] bit 0 INT: mux SNG_E0[4] bit 0 INT: mux IMUX_LOGICIN[37] bit 2 INT: mux IMUX_LOGICIN[61] bit 2 INT: mux IMUX_LOGICIN[9] bit 2 INT: mux IMUX_LOGICIN[31] bit 2 INT: mux IMUX_LOGICIN[46] bit 2 INT: mux IMUX_LOGICIN[60] bit 2 INT: mux IMUX_LOGICIN[19] bit 2 INT: mux IMUX_LOGICIN[59] bit 2 INT: mux IMUX_SR[0] bit 4 -
B58 INT: mux QUAD_SS0[3] bit 4 INT: mux QUAD_SW0[3] bit 4 INT: mux QUAD_EE0[3] bit 3 INT: mux QUAD_SE0[3] bit 3 INT: mux DBL_WW0[3] bit 5 INT: mux DBL_SW0[3] bit 5 INT: mux DBL_SS0[3] bit 5 INT: mux DBL_SE0[3] bit 5 INT: mux SNG_S0[4] bit 5 INT: mux SNG_W0[2] bit 5 INT: mux SNG_S0[3] bit 5 INT: mux SNG_E0[4] bit 5 INT: mux IMUX_LOGICIN[37] bit 4 INT: mux IMUX_LOGICIN[61] bit 4 INT: mux IMUX_LOGICIN[9] bit 4 INT: mux IMUX_LOGICIN[31] bit 4 INT: mux IMUX_LOGICIN[46] bit 4 INT: mux IMUX_LOGICIN[60] bit 4 INT: mux IMUX_LOGICIN[19] bit 4 INT: mux IMUX_LOGICIN[59] bit 4 INT: mux IMUX_SR[0] bit 1 -
B57 INT: mux QUAD_SS0[3] bit 1 INT: mux QUAD_SW0[3] bit 1 INT: mux QUAD_EE0[3] bit 0 INT: mux QUAD_SE0[3] bit 0 INT: mux DBL_WW0[3] bit 4 INT: mux DBL_SW0[3] bit 4 INT: mux DBL_SS0[3] bit 4 INT: mux DBL_SE0[3] bit 4 INT: mux SNG_S0[4] bit 4 INT: mux SNG_W0[2] bit 4 INT: mux SNG_S0[3] bit 4 INT: mux SNG_E0[4] bit 4 INT: mux IMUX_LOGICIN[37] bit 5 INT: mux IMUX_LOGICIN[61] bit 5 INT: mux IMUX_LOGICIN[9] bit 5 INT: mux IMUX_LOGICIN[31] bit 5 INT: mux IMUX_LOGICIN[46] bit 5 INT: mux IMUX_LOGICIN[60] bit 5 INT: mux IMUX_LOGICIN[19] bit 5 INT: mux IMUX_LOGICIN[59] bit 5 INT: mux IMUX_SR[0] bit 0 -
B56 INT: mux QUAD_SW0[3] bit 7 INT: mux QUAD_SW0[3] bit 6 INT: mux QUAD_SE0[3] bit 7 INT: mux QUAD_SE0[3] bit 6 INT: mux DBL_SW0[3] bit 7 INT: mux DBL_SW0[3] bit 6 INT: mux DBL_SE0[3] bit 7 INT: mux DBL_SE0[3] bit 6 INT: mux SNG_W0[2] bit 7 INT: mux SNG_W0[2] bit 6 INT: mux SNG_E0[4] bit 7 INT: mux SNG_E0[4] bit 6 INT: mux IMUX_LOGICIN[61] bit 6 INT: mux IMUX_LOGICIN[61] bit 7 INT: mux IMUX_LOGICIN[9] bit 7 INT: mux IMUX_LOGICIN[9] bit 6 INT: mux IMUX_LOGICIN[60] bit 6 INT: mux IMUX_LOGICIN[60] bit 7 INT: mux IMUX_LOGICIN[19] bit 7 INT: mux IMUX_LOGICIN[19] bit 6 INT: mux IMUX_SR[0] bit 5 -
B55 INT: mux QUAD_WW0[3] bit 7 INT: mux QUAD_WW0[3] bit 6 INT: mux QUAD_NN0[3] bit 7 INT: mux QUAD_NN0[3] bit 6 INT: mux DBL_NW0[3] bit 7 INT: mux DBL_NW0[3] bit 6 INT: mux DBL_NE0[3] bit 7 INT: mux DBL_NE0[3] bit 6 INT: mux SNG_W0[4] bit 7 INT: mux SNG_W0[4] bit 6 INT: mux SNG_E0[2] bit 7 INT: mux SNG_E0[2] bit 6 INT: mux IMUX_LOGICIN[50] bit 6 INT: mux IMUX_LOGICIN[50] bit 7 INT: mux IMUX_LOGICIN[14] bit 7 INT: mux IMUX_LOGICIN[14] bit 6 INT: mux IMUX_LOGICIN[39] bit 6 INT: mux IMUX_LOGICIN[39] bit 7 INT: mux IMUX_LOGICIN[8] bit 7 INT: mux IMUX_LOGICIN[8] bit 6 INT: mux IMUX_SR[1] bit 5 -
B54 INT: mux QUAD_NW0[3] bit 2 INT: mux QUAD_WW0[3] bit 2 INT: mux QUAD_NE0[3] bit 1 INT: mux QUAD_NN0[3] bit 1 INT: mux DBL_NN0[3] bit 5 INT: mux DBL_NW0[3] bit 5 INT: mux DBL_EE0[3] bit 5 INT: mux DBL_NE0[3] bit 5 INT: mux SNG_N0[2] bit 5 INT: mux SNG_W0[4] bit 5 INT: mux SNG_N0[7] bit 5 INT: mux SNG_E0[2] bit 5 INT: mux IMUX_LOGICIN[50] bit 0 INT: mux IMUX_LOGICIN[27] bit 0 INT: mux IMUX_LOGICIN[28] bit 0 INT: mux IMUX_LOGICIN[14] bit 0 INT: mux IMUX_LOGICIN[39] bit 0 INT: mux IMUX_LOGICIN[2] bit 0 INT: mux IMUX_LOGICIN[63] bit 0 INT: mux IMUX_LOGICIN[8] bit 0 INT: mux IMUX_SR[1] bit 4 -
B53 INT: mux QUAD_NW0[3] bit 1 INT: mux QUAD_WW0[3] bit 1 INT: mux QUAD_NE0[3] bit 2 INT: mux QUAD_NN0[3] bit 2 INT: mux DBL_NN0[3] bit 4 INT: mux DBL_NW0[3] bit 4 INT: mux DBL_EE0[3] bit 4 INT: mux DBL_NE0[3] bit 4 INT: mux SNG_N0[2] bit 4 INT: mux SNG_W0[4] bit 4 INT: mux SNG_N0[7] bit 4 INT: mux SNG_E0[2] bit 4 INT: mux IMUX_LOGICIN[50] bit 3 INT: mux IMUX_LOGICIN[27] bit 3 INT: mux IMUX_LOGICIN[28] bit 3 INT: mux IMUX_LOGICIN[14] bit 3 INT: mux IMUX_LOGICIN[39] bit 3 INT: mux IMUX_LOGICIN[2] bit 3 INT: mux IMUX_LOGICIN[63] bit 3 INT: mux IMUX_LOGICIN[8] bit 3 INT: mux IMUX_SR[1] bit 1 -
B52 INT: mux QUAD_NW0[3] bit 0 INT: mux QUAD_WW0[3] bit 0 INT: mux QUAD_NE0[3] bit 0 INT: mux QUAD_NN0[3] bit 0 INT: mux DBL_NN0[3] bit 0 INT: mux DBL_NW0[3] bit 0 INT: mux DBL_EE0[3] bit 0 INT: mux DBL_NE0[3] bit 0 INT: mux SNG_N0[2] bit 0 INT: mux SNG_W0[4] bit 0 INT: mux SNG_N0[7] bit 0 INT: mux SNG_E0[2] bit 0 INT: mux IMUX_LOGICIN[50] bit 1 INT: mux IMUX_LOGICIN[27] bit 1 INT: mux IMUX_LOGICIN[28] bit 1 INT: mux IMUX_LOGICIN[14] bit 1 INT: mux IMUX_LOGICIN[39] bit 1 INT: mux IMUX_LOGICIN[2] bit 1 INT: mux IMUX_LOGICIN[63] bit 1 INT: mux IMUX_LOGICIN[8] bit 1 INT: mux IMUX_SR[1] bit 0 -
B51 INT: mux QUAD_NW0[3] bit 5 INT: mux QUAD_WW0[3] bit 5 INT: mux QUAD_NE0[3] bit 5 INT: mux QUAD_NN0[3] bit 5 INT: mux DBL_NN0[3] bit 1 INT: mux DBL_NW0[3] bit 1 INT: mux DBL_EE0[3] bit 1 INT: mux DBL_NE0[3] bit 1 INT: mux SNG_N0[2] bit 1 INT: mux SNG_W0[4] bit 1 INT: mux SNG_N0[7] bit 1 INT: mux SNG_E0[2] bit 1 INT: mux IMUX_LOGICIN[50] bit 2 INT: mux IMUX_LOGICIN[27] bit 2 INT: mux IMUX_LOGICIN[28] bit 2 INT: mux IMUX_LOGICIN[14] bit 2 INT: mux IMUX_LOGICIN[39] bit 2 INT: mux IMUX_LOGICIN[2] bit 2 INT: mux IMUX_LOGICIN[63] bit 2 INT: mux IMUX_LOGICIN[8] bit 2 INT: mux IMUX_SR[1] bit 3 -
B50 INT: mux QUAD_NW0[3] bit 3 INT: mux QUAD_WW0[3] bit 3 INT: mux QUAD_NE0[3] bit 3 INT: mux QUAD_NN0[3] bit 3 INT: mux DBL_NN0[3] bit 3 INT: mux DBL_NW0[3] bit 3 INT: mux DBL_EE0[3] bit 3 INT: mux DBL_NE0[3] bit 3 INT: mux SNG_N0[2] bit 3 INT: mux SNG_W0[4] bit 3 INT: mux SNG_N0[7] bit 3 INT: mux SNG_E0[2] bit 3 INT: mux IMUX_LOGICIN[50] bit 4 INT: mux IMUX_LOGICIN[27] bit 4 INT: mux IMUX_LOGICIN[28] bit 4 INT: mux IMUX_LOGICIN[14] bit 4 INT: mux IMUX_LOGICIN[39] bit 4 INT: mux IMUX_LOGICIN[2] bit 4 INT: mux IMUX_LOGICIN[63] bit 4 INT: mux IMUX_LOGICIN[8] bit 4 INT: mux IMUX_SR[1] bit 2 -
B49 INT: mux QUAD_NW0[3] bit 4 INT: mux QUAD_WW0[3] bit 4 INT: mux QUAD_NE0[3] bit 4 INT: mux QUAD_NN0[3] bit 4 INT: mux DBL_NN0[3] bit 2 INT: mux DBL_NW0[3] bit 2 INT: mux DBL_EE0[3] bit 2 INT: mux DBL_NE0[3] bit 2 INT: mux SNG_N0[2] bit 2 INT: mux SNG_W0[4] bit 2 INT: mux SNG_N0[7] bit 2 INT: mux SNG_E0[2] bit 2 INT: mux IMUX_LOGICIN[50] bit 5 INT: mux IMUX_LOGICIN[27] bit 5 INT: mux IMUX_LOGICIN[28] bit 5 INT: mux IMUX_LOGICIN[14] bit 5 INT: mux IMUX_LOGICIN[39] bit 5 INT: mux IMUX_LOGICIN[2] bit 5 INT: mux IMUX_LOGICIN[63] bit 5 INT: mux IMUX_LOGICIN[8] bit 5 INT: mux IMUX_SR[1] bit 6 -
B48 INT: mux QUAD_NW0[3] bit 6 INT: mux QUAD_NW0[3] bit 7 INT: mux QUAD_NE0[3] bit 6 INT: mux QUAD_NE0[3] bit 7 INT: mux DBL_NN0[3] bit 6 INT: mux DBL_NN0[3] bit 7 INT: mux DBL_EE0[3] bit 6 INT: mux DBL_EE0[3] bit 7 INT: mux SNG_N0[2] bit 6 INT: mux SNG_N0[2] bit 7 INT: mux SNG_N0[7] bit 6 INT: mux SNG_N0[7] bit 7 INT: mux IMUX_LOGICIN[27] bit 6 INT: mux IMUX_LOGICIN[27] bit 7 INT: mux IMUX_LOGICIN[28] bit 7 INT: mux IMUX_LOGICIN[28] bit 6 INT: mux IMUX_LOGICIN[2] bit 6 INT: mux IMUX_LOGICIN[2] bit 7 INT: mux IMUX_LOGICIN[63] bit 7 INT: mux IMUX_LOGICIN[63] bit 6 INT: mux IMUX_SR[1] bit 7 -
B47 INT: mux QUAD_SS0[2] bit 6 INT: mux QUAD_SS0[2] bit 7 INT: mux QUAD_EE0[2] bit 6 INT: mux QUAD_EE0[2] bit 7 INT: mux DBL_WW0[2] bit 6 INT: mux DBL_WW0[2] bit 7 INT: mux DBL_SS0[2] bit 6 INT: mux DBL_SS0[2] bit 7 INT: mux SNG_S0[7] bit 6 INT: mux SNG_S0[7] bit 7 INT: mux SNG_S0[2] bit 6 INT: mux SNG_S0[2] bit 7 INT: mux IMUX_LOGICIN[53] bit 6 INT: mux IMUX_LOGICIN[53] bit 7 INT: mux IMUX_LOGICIN[32] bit 7 INT: mux IMUX_LOGICIN[32] bit 6 INT: mux IMUX_LOGICIN[21] bit 6 INT: mux IMUX_LOGICIN[21] bit 7 INT: mux IMUX_LOGICIN[58] bit 7 INT: mux IMUX_LOGICIN[58] bit 6 - -
B46 INT: mux QUAD_SS0[2] bit 3 INT: mux QUAD_SW0[2] bit 3 INT: mux QUAD_EE0[2] bit 2 INT: mux QUAD_SE0[2] bit 2 INT: mux DBL_WW0[2] bit 3 INT: mux DBL_SW0[2] bit 3 INT: mux DBL_SS0[2] bit 3 INT: mux DBL_SE0[2] bit 3 INT: mux SNG_S0[7] bit 3 INT: mux SNG_W0[1] bit 3 INT: mux SNG_S0[2] bit 3 INT: mux SNG_E0[7] bit 3 INT: mux IMUX_LOGICIN[53] bit 0 INT: mux IMUX_LOGICIN[1] bit 0 - INT: mux IMUX_LOGICIN[32] bit 0 INT: mux IMUX_LOGICIN[21] bit 0 INT: mux IMUX_LOGICIN[22] bit 0 INT: mux IMUX_LOGICIN[18] bit 0 INT: mux IMUX_LOGICIN[58] bit 0 - -
B45 INT: mux QUAD_SS0[2] bit 0 INT: mux QUAD_SW0[2] bit 0 INT: mux QUAD_EE0[2] bit 4 INT: mux QUAD_SE0[2] bit 4 INT: mux DBL_WW0[2] bit 2 INT: mux DBL_SW0[2] bit 2 INT: mux DBL_SS0[2] bit 2 INT: mux DBL_SE0[2] bit 2 INT: mux SNG_S0[7] bit 2 INT: mux SNG_W0[1] bit 2 INT: mux SNG_S0[2] bit 2 INT: mux SNG_E0[7] bit 2 INT: mux IMUX_LOGICIN[53] bit 3 INT: mux IMUX_LOGICIN[1] bit 3 - INT: mux IMUX_LOGICIN[32] bit 3 INT: mux IMUX_LOGICIN[21] bit 3 INT: mux IMUX_LOGICIN[22] bit 3 INT: mux IMUX_LOGICIN[18] bit 3 INT: mux IMUX_LOGICIN[58] bit 3 - -
B44 INT: mux QUAD_SS0[2] bit 5 INT: mux QUAD_SW0[2] bit 5 INT: mux QUAD_EE0[2] bit 5 INT: mux QUAD_SE0[2] bit 5 INT: mux DBL_WW0[2] bit 1 INT: mux DBL_SW0[2] bit 1 INT: mux DBL_SS0[2] bit 1 INT: mux DBL_SE0[2] bit 1 INT: mux SNG_S0[7] bit 1 INT: mux SNG_W0[1] bit 1 INT: mux SNG_S0[2] bit 1 INT: mux SNG_E0[7] bit 1 INT: mux IMUX_LOGICIN[53] bit 1 INT: mux IMUX_LOGICIN[1] bit 1 - INT: mux IMUX_LOGICIN[32] bit 1 INT: mux IMUX_LOGICIN[21] bit 1 INT: mux IMUX_LOGICIN[22] bit 1 INT: mux IMUX_LOGICIN[18] bit 1 INT: mux IMUX_LOGICIN[58] bit 1 - -
B43 INT: mux QUAD_SS0[2] bit 2 INT: mux QUAD_SW0[2] bit 2 INT: mux QUAD_EE0[2] bit 1 INT: mux QUAD_SE0[2] bit 1 INT: mux DBL_WW0[2] bit 0 INT: mux DBL_SW0[2] bit 0 INT: mux DBL_SS0[2] bit 0 INT: mux DBL_SE0[2] bit 0 INT: mux SNG_S0[7] bit 0 INT: mux SNG_W0[1] bit 0 INT: mux SNG_S0[2] bit 0 INT: mux SNG_E0[7] bit 0 INT: mux IMUX_LOGICIN[53] bit 2 INT: mux IMUX_LOGICIN[1] bit 2 - INT: mux IMUX_LOGICIN[32] bit 2 INT: mux IMUX_LOGICIN[21] bit 2 INT: mux IMUX_LOGICIN[22] bit 2 INT: mux IMUX_LOGICIN[18] bit 2 INT: mux IMUX_LOGICIN[58] bit 2 - -
B42 INT: mux QUAD_SS0[2] bit 4 INT: mux QUAD_SW0[2] bit 4 INT: mux QUAD_EE0[2] bit 3 INT: mux QUAD_SE0[2] bit 3 INT: mux DBL_WW0[2] bit 5 INT: mux DBL_SW0[2] bit 5 INT: mux DBL_SS0[2] bit 5 INT: mux DBL_SE0[2] bit 5 INT: mux SNG_S0[7] bit 5 INT: mux SNG_W0[1] bit 5 INT: mux SNG_S0[2] bit 5 INT: mux SNG_E0[7] bit 5 INT: mux IMUX_LOGICIN[53] bit 4 INT: mux IMUX_LOGICIN[1] bit 4 - INT: mux IMUX_LOGICIN[32] bit 4 INT: mux IMUX_LOGICIN[21] bit 4 INT: mux IMUX_LOGICIN[22] bit 4 INT: mux IMUX_LOGICIN[18] bit 4 INT: mux IMUX_LOGICIN[58] bit 4 - -
B41 INT: mux QUAD_SS0[2] bit 1 INT: mux QUAD_SW0[2] bit 1 INT: mux QUAD_EE0[2] bit 0 INT: mux QUAD_SE0[2] bit 0 INT: mux DBL_WW0[2] bit 4 INT: mux DBL_SW0[2] bit 4 INT: mux DBL_SS0[2] bit 4 INT: mux DBL_SE0[2] bit 4 INT: mux SNG_S0[7] bit 4 INT: mux SNG_W0[1] bit 4 INT: mux SNG_S0[2] bit 4 INT: mux SNG_E0[7] bit 4 INT: mux IMUX_LOGICIN[53] bit 5 INT: mux IMUX_LOGICIN[1] bit 5 - INT: mux IMUX_LOGICIN[32] bit 5 INT: mux IMUX_LOGICIN[21] bit 5 INT: mux IMUX_LOGICIN[22] bit 5 INT: mux IMUX_LOGICIN[18] bit 5 INT: mux IMUX_LOGICIN[58] bit 5 - -
B40 INT: mux QUAD_SW0[2] bit 7 INT: mux QUAD_SW0[2] bit 6 INT: mux QUAD_SE0[2] bit 7 INT: mux QUAD_SE0[2] bit 6 INT: mux DBL_SW0[2] bit 7 INT: mux DBL_SW0[2] bit 6 INT: mux DBL_SE0[2] bit 7 INT: mux DBL_SE0[2] bit 6 INT: mux SNG_W0[1] bit 7 INT: mux SNG_W0[1] bit 6 INT: mux SNG_E0[7] bit 7 INT: mux SNG_E0[7] bit 6 INT: mux IMUX_LOGICIN[1] bit 6 INT: mux IMUX_LOGICIN[1] bit 7 - - INT: mux IMUX_LOGICIN[22] bit 6 INT: mux IMUX_LOGICIN[22] bit 7 INT: mux IMUX_LOGICIN[18] bit 7 INT: mux IMUX_LOGICIN[18] bit 6 - -
B39 INT: mux QUAD_WW0[2] bit 7 INT: mux QUAD_WW0[2] bit 6 INT: mux QUAD_NN0[2] bit 7 INT: mux QUAD_NN0[2] bit 6 INT: mux DBL_NW0[2] bit 7 INT: mux DBL_NW0[2] bit 6 INT: mux DBL_NE0[2] bit 7 INT: mux DBL_NE0[2] bit 6 INT: mux SNG_W0[7] bit 7 INT: mux SNG_W0[7] bit 6 INT: mux SNG_E0[1] bit 7 INT: mux SNG_E0[1] bit 6 INT: mux IMUX_LOGICIN[49] bit 6 INT: mux IMUX_LOGICIN[49] bit 7 INT: mux IMUX_LOGICIN[52] bit 7 INT: mux IMUX_LOGICIN[52] bit 6 INT: mux IMUX_LOGICIN[40] bit 6 INT: mux IMUX_LOGICIN[40] bit 7 INT: mux IMUX_LOGICIN[29] bit 7 INT: mux IMUX_LOGICIN[29] bit 6 INT: mux IMUX_CLK[0] bit 6 -
B38 INT: mux QUAD_NW0[2] bit 2 INT: mux QUAD_WW0[2] bit 2 INT: mux QUAD_NE0[2] bit 1 INT: mux QUAD_NN0[2] bit 1 INT: mux DBL_NN0[2] bit 5 INT: mux DBL_NW0[2] bit 5 INT: mux DBL_EE0[2] bit 5 INT: mux DBL_NE0[2] bit 5 INT: mux SNG_N0[1] bit 5 INT: mux SNG_W0[7] bit 5 INT: mux SNG_N0[6] bit 5 INT: mux SNG_E0[1] bit 5 INT: mux IMUX_LOGICIN[49] bit 0 INT: mux IMUX_LOGICIN[26] bit 0 INT: mux IMUX_LOGICIN[55] bit 0 INT: mux IMUX_LOGICIN[52] bit 0 INT: mux IMUX_LOGICIN[40] bit 0 INT: mux IMUX_LOGICIN[3] bit 0 INT: mux IMUX_LOGICIN[51] bit 0 INT: mux IMUX_LOGICIN[29] bit 0 INT: mux IMUX_CLK[0] bit 7 -
B37 INT: mux QUAD_NW0[2] bit 1 INT: mux QUAD_WW0[2] bit 1 INT: mux QUAD_NE0[2] bit 2 INT: mux QUAD_NN0[2] bit 2 INT: mux DBL_NN0[2] bit 4 INT: mux DBL_NW0[2] bit 4 INT: mux DBL_EE0[2] bit 4 INT: mux DBL_NE0[2] bit 4 INT: mux SNG_N0[1] bit 4 INT: mux SNG_W0[7] bit 4 INT: mux SNG_N0[6] bit 4 INT: mux SNG_E0[1] bit 4 INT: mux IMUX_LOGICIN[49] bit 3 INT: mux IMUX_LOGICIN[26] bit 3 INT: mux IMUX_LOGICIN[55] bit 3 INT: mux IMUX_LOGICIN[52] bit 3 INT: mux IMUX_LOGICIN[40] bit 3 INT: mux IMUX_LOGICIN[3] bit 3 INT: mux IMUX_LOGICIN[51] bit 3 INT: mux IMUX_LOGICIN[29] bit 3 INT: mux IMUX_CLK[0] bit 2 -
B36 INT: mux QUAD_NW0[2] bit 0 INT: mux QUAD_WW0[2] bit 0 INT: mux QUAD_NE0[2] bit 0 INT: mux QUAD_NN0[2] bit 0 INT: mux DBL_NN0[2] bit 0 INT: mux DBL_NW0[2] bit 0 INT: mux DBL_EE0[2] bit 0 INT: mux DBL_NE0[2] bit 0 INT: mux SNG_N0[1] bit 0 INT: mux SNG_W0[7] bit 0 INT: mux SNG_N0[6] bit 0 INT: mux SNG_E0[1] bit 0 INT: mux IMUX_LOGICIN[49] bit 1 INT: mux IMUX_LOGICIN[26] bit 1 INT: mux IMUX_LOGICIN[55] bit 1 INT: mux IMUX_LOGICIN[52] bit 1 INT: mux IMUX_LOGICIN[40] bit 1 INT: mux IMUX_LOGICIN[3] bit 1 INT: mux IMUX_LOGICIN[51] bit 1 INT: mux IMUX_LOGICIN[29] bit 1 INT: mux IMUX_CLK[0] bit 3 -
B35 INT: mux QUAD_NW0[2] bit 5 INT: mux QUAD_WW0[2] bit 5 INT: mux QUAD_NE0[2] bit 5 INT: mux QUAD_NN0[2] bit 5 INT: mux DBL_NN0[2] bit 1 INT: mux DBL_NW0[2] bit 1 INT: mux DBL_EE0[2] bit 1 INT: mux DBL_NE0[2] bit 1 INT: mux SNG_N0[1] bit 1 INT: mux SNG_W0[7] bit 1 INT: mux SNG_N0[6] bit 1 INT: mux SNG_E0[1] bit 1 INT: mux IMUX_LOGICIN[49] bit 2 INT: mux IMUX_LOGICIN[26] bit 2 INT: mux IMUX_LOGICIN[55] bit 2 INT: mux IMUX_LOGICIN[52] bit 2 INT: mux IMUX_LOGICIN[40] bit 2 INT: mux IMUX_LOGICIN[3] bit 2 INT: mux IMUX_LOGICIN[51] bit 2 INT: mux IMUX_LOGICIN[29] bit 2 INT: mux IMUX_CLK[0] bit 4 -
B34 INT: mux QUAD_NW0[2] bit 3 INT: mux QUAD_WW0[2] bit 3 INT: mux QUAD_NE0[2] bit 3 INT: mux QUAD_NN0[2] bit 3 INT: mux DBL_NN0[2] bit 3 INT: mux DBL_NW0[2] bit 3 INT: mux DBL_EE0[2] bit 3 INT: mux DBL_NE0[2] bit 3 INT: mux SNG_N0[1] bit 3 INT: mux SNG_W0[7] bit 3 INT: mux SNG_N0[6] bit 3 INT: mux SNG_E0[1] bit 3 INT: mux IMUX_LOGICIN[49] bit 4 INT: mux IMUX_LOGICIN[26] bit 4 INT: mux IMUX_LOGICIN[55] bit 4 INT: mux IMUX_LOGICIN[52] bit 4 INT: mux IMUX_LOGICIN[40] bit 4 INT: mux IMUX_LOGICIN[3] bit 4 INT: mux IMUX_LOGICIN[51] bit 4 INT: mux IMUX_LOGICIN[29] bit 4 INT: mux IMUX_CLK[0] bit 1 -
B33 INT: mux QUAD_NW0[2] bit 4 INT: mux QUAD_WW0[2] bit 4 INT: mux QUAD_NE0[2] bit 4 INT: mux QUAD_NN0[2] bit 4 INT: mux DBL_NN0[2] bit 2 INT: mux DBL_NW0[2] bit 2 INT: mux DBL_EE0[2] bit 2 INT: mux DBL_NE0[2] bit 2 INT: mux SNG_N0[1] bit 2 INT: mux SNG_W0[7] bit 2 INT: mux SNG_N0[6] bit 2 INT: mux SNG_E0[1] bit 2 INT: mux IMUX_LOGICIN[49] bit 5 INT: mux IMUX_LOGICIN[26] bit 5 INT: mux IMUX_LOGICIN[55] bit 5 INT: mux IMUX_LOGICIN[52] bit 5 INT: mux IMUX_LOGICIN[40] bit 5 INT: mux IMUX_LOGICIN[3] bit 5 INT: mux IMUX_LOGICIN[51] bit 5 INT: mux IMUX_LOGICIN[29] bit 5 INT: mux IMUX_CLK[0] bit 0 -
B32 INT: mux QUAD_NW0[2] bit 6 INT: mux QUAD_NW0[2] bit 7 INT: mux QUAD_NE0[2] bit 6 INT: mux QUAD_NE0[2] bit 7 INT: mux DBL_NN0[2] bit 6 INT: mux DBL_NN0[2] bit 7 INT: mux DBL_EE0[2] bit 6 INT: mux DBL_EE0[2] bit 7 INT: mux SNG_N0[1] bit 6 INT: mux SNG_N0[1] bit 7 INT: mux SNG_N0[6] bit 6 INT: mux SNG_N0[6] bit 7 INT: mux IMUX_LOGICIN[26] bit 6 INT: mux IMUX_LOGICIN[26] bit 7 INT: mux IMUX_LOGICIN[55] bit 7 INT: mux IMUX_LOGICIN[55] bit 6 INT: mux IMUX_LOGICIN[3] bit 6 INT: mux IMUX_LOGICIN[3] bit 7 INT: mux IMUX_LOGICIN[51] bit 7 INT: mux IMUX_LOGICIN[51] bit 6 INT: mux IMUX_CLK[0] bit 5 -
B31 INT: mux QUAD_SS0[1] bit 6 INT: mux QUAD_SS0[1] bit 7 INT: mux QUAD_EE0[1] bit 6 INT: mux QUAD_EE0[1] bit 7 INT: mux DBL_WW0[1] bit 6 INT: mux DBL_WW0[1] bit 7 INT: mux DBL_SS0[1] bit 6 INT: mux DBL_SS0[1] bit 7 INT: mux SNG_S0[6] bit 6 INT: mux SNG_S0[6] bit 7 INT: mux SNG_S0[1] bit 6 INT: mux SNG_S0[1] bit 7 INT: mux IMUX_LOGICIN[0] bit 6 INT: mux IMUX_LOGICIN[0] bit 7 INT: mux IMUX_LOGICIN[33] bit 7 INT: mux IMUX_LOGICIN[33] bit 6 INT: mux IMUX_LOGICIN[43] bit 6 INT: mux IMUX_LOGICIN[43] bit 7 INT: mux IMUX_LOGICIN[57] bit 7 INT: mux IMUX_LOGICIN[57] bit 6 INT: mux IMUX_CLK[1] bit 5 -
B30 INT: mux QUAD_SS0[1] bit 3 INT: mux QUAD_SW0[1] bit 3 INT: mux QUAD_EE0[1] bit 2 INT: mux QUAD_SE0[1] bit 2 INT: mux DBL_WW0[1] bit 3 INT: mux DBL_SW0[1] bit 3 INT: mux DBL_SS0[1] bit 3 INT: mux DBL_SE0[1] bit 3 INT: mux SNG_S0[6] bit 3 INT: mux SNG_W0[0] bit 3 INT: mux SNG_S0[1] bit 3 INT: mux SNG_E0[6] bit 3 INT: mux IMUX_LOGICIN[0] bit 0 INT: mux IMUX_LOGICIN[20] bit 0 INT: mux IMUX_LOGICIN[11] bit 0 INT: mux IMUX_LOGICIN[33] bit 0 INT: mux IMUX_LOGICIN[43] bit 0 INT: mux IMUX_LOGICIN[23] bit 0 INT: mux IMUX_LOGICIN[17] bit 0 INT: mux IMUX_LOGICIN[57] bit 0 INT: mux IMUX_CLK[1] bit 4 -
B29 INT: mux QUAD_SS0[1] bit 0 INT: mux QUAD_SW0[1] bit 0 INT: mux QUAD_EE0[1] bit 4 INT: mux QUAD_SE0[1] bit 4 INT: mux DBL_WW0[1] bit 2 INT: mux DBL_SW0[1] bit 2 INT: mux DBL_SS0[1] bit 2 INT: mux DBL_SE0[1] bit 2 INT: mux SNG_S0[6] bit 2 INT: mux SNG_W0[0] bit 2 INT: mux SNG_S0[1] bit 2 INT: mux SNG_E0[6] bit 2 INT: mux IMUX_LOGICIN[0] bit 3 INT: mux IMUX_LOGICIN[20] bit 3 INT: mux IMUX_LOGICIN[11] bit 3 INT: mux IMUX_LOGICIN[33] bit 3 INT: mux IMUX_LOGICIN[43] bit 3 INT: mux IMUX_LOGICIN[23] bit 3 INT: mux IMUX_LOGICIN[17] bit 3 INT: mux IMUX_LOGICIN[57] bit 3 INT: mux IMUX_CLK[1] bit 1 -
B28 INT: mux QUAD_SS0[1] bit 5 INT: mux QUAD_SW0[1] bit 5 INT: mux QUAD_EE0[1] bit 5 INT: mux QUAD_SE0[1] bit 5 INT: mux DBL_WW0[1] bit 1 INT: mux DBL_SW0[1] bit 1 INT: mux DBL_SS0[1] bit 1 INT: mux DBL_SE0[1] bit 1 INT: mux SNG_S0[6] bit 1 INT: mux SNG_W0[0] bit 1 INT: mux SNG_S0[1] bit 1 INT: mux SNG_E0[6] bit 1 INT: mux IMUX_LOGICIN[0] bit 1 INT: mux IMUX_LOGICIN[20] bit 1 INT: mux IMUX_LOGICIN[11] bit 1 INT: mux IMUX_LOGICIN[33] bit 1 INT: mux IMUX_LOGICIN[43] bit 1 INT: mux IMUX_LOGICIN[23] bit 1 INT: mux IMUX_LOGICIN[17] bit 1 INT: mux IMUX_LOGICIN[57] bit 1 INT: mux IMUX_CLK[1] bit 0 -
B27 INT: mux QUAD_SS0[1] bit 2 INT: mux QUAD_SW0[1] bit 2 INT: mux QUAD_EE0[1] bit 1 INT: mux QUAD_SE0[1] bit 1 INT: mux DBL_WW0[1] bit 0 INT: mux DBL_SW0[1] bit 0 INT: mux DBL_SS0[1] bit 0 INT: mux DBL_SE0[1] bit 0 INT: mux SNG_S0[6] bit 0 INT: mux SNG_W0[0] bit 0 INT: mux SNG_S0[1] bit 0 INT: mux SNG_E0[6] bit 0 INT: mux IMUX_LOGICIN[0] bit 2 INT: mux IMUX_LOGICIN[20] bit 2 INT: mux IMUX_LOGICIN[11] bit 2 INT: mux IMUX_LOGICIN[33] bit 2 INT: mux IMUX_LOGICIN[43] bit 2 INT: mux IMUX_LOGICIN[23] bit 2 INT: mux IMUX_LOGICIN[17] bit 2 INT: mux IMUX_LOGICIN[57] bit 2 INT: mux IMUX_CLK[1] bit 3 -
B26 INT: mux QUAD_SS0[1] bit 4 INT: mux QUAD_SW0[1] bit 4 INT: mux QUAD_EE0[1] bit 3 INT: mux QUAD_SE0[1] bit 3 INT: mux DBL_WW0[1] bit 5 INT: mux DBL_SW0[1] bit 5 INT: mux DBL_SS0[1] bit 5 INT: mux DBL_SE0[1] bit 5 INT: mux SNG_S0[6] bit 5 INT: mux SNG_W0[0] bit 5 INT: mux SNG_S0[1] bit 5 INT: mux SNG_E0[6] bit 5 INT: mux IMUX_LOGICIN[0] bit 4 INT: mux IMUX_LOGICIN[20] bit 4 INT: mux IMUX_LOGICIN[11] bit 4 INT: mux IMUX_LOGICIN[33] bit 4 INT: mux IMUX_LOGICIN[43] bit 4 INT: mux IMUX_LOGICIN[23] bit 4 INT: mux IMUX_LOGICIN[17] bit 4 INT: mux IMUX_LOGICIN[57] bit 4 INT: mux IMUX_CLK[1] bit 2 -
B25 INT: mux QUAD_SS0[1] bit 1 INT: mux QUAD_SW0[1] bit 1 INT: mux QUAD_EE0[1] bit 0 INT: mux QUAD_SE0[1] bit 0 INT: mux DBL_WW0[1] bit 4 INT: mux DBL_SW0[1] bit 4 INT: mux DBL_SS0[1] bit 4 INT: mux DBL_SE0[1] bit 4 INT: mux SNG_S0[6] bit 4 INT: mux SNG_W0[0] bit 4 INT: mux SNG_S0[1] bit 4 INT: mux SNG_E0[6] bit 4 INT: mux IMUX_LOGICIN[0] bit 5 INT: mux IMUX_LOGICIN[20] bit 5 INT: mux IMUX_LOGICIN[11] bit 5 INT: mux IMUX_LOGICIN[33] bit 5 INT: mux IMUX_LOGICIN[43] bit 5 INT: mux IMUX_LOGICIN[23] bit 5 INT: mux IMUX_LOGICIN[17] bit 5 INT: mux IMUX_LOGICIN[57] bit 5 INT: mux IMUX_CLK[1] bit 7 -
B24 INT: mux QUAD_SW0[1] bit 7 INT: mux QUAD_SW0[1] bit 6 INT: mux QUAD_SE0[1] bit 7 INT: mux QUAD_SE0[1] bit 6 INT: mux DBL_SW0[1] bit 7 INT: mux DBL_SW0[1] bit 6 INT: mux DBL_SE0[1] bit 7 INT: mux DBL_SE0[1] bit 6 INT: mux SNG_W0[0] bit 7 INT: mux SNG_W0[0] bit 6 INT: mux SNG_E0[6] bit 7 INT: mux SNG_E0[6] bit 6 INT: mux IMUX_LOGICIN[20] bit 6 INT: mux IMUX_LOGICIN[20] bit 7 INT: mux IMUX_LOGICIN[11] bit 7 INT: mux IMUX_LOGICIN[11] bit 6 INT: mux IMUX_LOGICIN[23] bit 6 INT: mux IMUX_LOGICIN[23] bit 7 INT: mux IMUX_LOGICIN[17] bit 7 INT: mux IMUX_LOGICIN[17] bit 6 INT: mux IMUX_CLK[1] bit 6 -
B23 INT: mux QUAD_WW0[1] bit 7 INT: mux QUAD_WW0[1] bit 6 INT: mux QUAD_NN0[1] bit 7 INT: mux QUAD_NN0[1] bit 6 INT: mux DBL_NW0[1] bit 7 INT: mux DBL_NW0[1] bit 6 INT: mux DBL_NE0[1] bit 7 INT: mux DBL_NE0[1] bit 6 INT: mux SNG_W0[6] bit 7 INT: mux SNG_W0[6] bit 6 INT: mux SNG_E0[0] bit 7 INT: mux SNG_E0[0] bit 6 INT: mux IMUX_LOGICIN[48] bit 6 INT: mux IMUX_LOGICIN[48] bit 7 INT: mux IMUX_LOGICIN[54] bit 7 INT: mux IMUX_LOGICIN[54] bit 6 INT: mux IMUX_LOGICIN[41] bit 6 INT: mux IMUX_LOGICIN[41] bit 7 INT: mux IMUX_LOGICIN[30] bit 7 INT: mux IMUX_LOGICIN[30] bit 6 - -
B22 INT: mux QUAD_NW0[1] bit 2 INT: mux QUAD_WW0[1] bit 2 INT: mux QUAD_NE0[1] bit 1 INT: mux QUAD_NN0[1] bit 1 INT: mux DBL_NN0[1] bit 5 INT: mux DBL_NW0[1] bit 5 INT: mux DBL_EE0[1] bit 5 INT: mux DBL_NE0[1] bit 5 INT: mux SNG_N0[0] bit 5 INT: mux SNG_W0[6] bit 5 INT: mux SNG_N0[5] bit 5 INT: mux SNG_E0[0] bit 5 INT: mux IMUX_LOGICIN[48] bit 0 INT: mux IMUX_LOGICIN[25] bit 0 INT: mux IMUX_LOGICIN[13] bit 0 INT: mux IMUX_LOGICIN[54] bit 0 INT: mux IMUX_LOGICIN[41] bit 0 - INT: mux IMUX_LOGICIN[44] bit 0 INT: mux IMUX_LOGICIN[30] bit 0 - -
B21 INT: mux QUAD_NW0[1] bit 1 INT: mux QUAD_WW0[1] bit 1 INT: mux QUAD_NE0[1] bit 2 INT: mux QUAD_NN0[1] bit 2 INT: mux DBL_NN0[1] bit 4 INT: mux DBL_NW0[1] bit 4 INT: mux DBL_EE0[1] bit 4 INT: mux DBL_NE0[1] bit 4 INT: mux SNG_N0[0] bit 4 INT: mux SNG_W0[6] bit 4 INT: mux SNG_N0[5] bit 4 INT: mux SNG_E0[0] bit 4 INT: mux IMUX_LOGICIN[48] bit 3 INT: mux IMUX_LOGICIN[25] bit 3 INT: mux IMUX_LOGICIN[13] bit 3 INT: mux IMUX_LOGICIN[54] bit 3 INT: mux IMUX_LOGICIN[41] bit 3 - INT: mux IMUX_LOGICIN[44] bit 3 INT: mux IMUX_LOGICIN[30] bit 3 - -
B20 INT: mux QUAD_NW0[1] bit 0 INT: mux QUAD_WW0[1] bit 0 INT: mux QUAD_NE0[1] bit 0 INT: mux QUAD_NN0[1] bit 0 INT: mux DBL_NN0[1] bit 0 INT: mux DBL_NW0[1] bit 0 INT: mux DBL_EE0[1] bit 0 INT: mux DBL_NE0[1] bit 0 INT: mux SNG_N0[0] bit 0 INT: mux SNG_W0[6] bit 0 INT: mux SNG_N0[5] bit 0 INT: mux SNG_E0[0] bit 0 INT: mux IMUX_LOGICIN[48] bit 1 INT: mux IMUX_LOGICIN[25] bit 1 INT: mux IMUX_LOGICIN[13] bit 1 INT: mux IMUX_LOGICIN[54] bit 1 INT: mux IMUX_LOGICIN[41] bit 1 - INT: mux IMUX_LOGICIN[44] bit 1 INT: mux IMUX_LOGICIN[30] bit 1 - -
B19 INT: mux QUAD_NW0[1] bit 5 INT: mux QUAD_WW0[1] bit 5 INT: mux QUAD_NE0[1] bit 5 INT: mux QUAD_NN0[1] bit 5 INT: mux DBL_NN0[1] bit 1 INT: mux DBL_NW0[1] bit 1 INT: mux DBL_EE0[1] bit 1 INT: mux DBL_NE0[1] bit 1 INT: mux SNG_N0[0] bit 1 INT: mux SNG_W0[6] bit 1 INT: mux SNG_N0[5] bit 1 INT: mux SNG_E0[0] bit 1 INT: mux IMUX_LOGICIN[48] bit 2 INT: mux IMUX_LOGICIN[25] bit 2 INT: mux IMUX_LOGICIN[13] bit 2 INT: mux IMUX_LOGICIN[54] bit 2 INT: mux IMUX_LOGICIN[41] bit 2 - INT: mux IMUX_LOGICIN[44] bit 2 INT: mux IMUX_LOGICIN[30] bit 2 - -
B18 INT: mux QUAD_NW0[1] bit 3 INT: mux QUAD_WW0[1] bit 3 INT: mux QUAD_NE0[1] bit 3 INT: mux QUAD_NN0[1] bit 3 INT: mux DBL_NN0[1] bit 3 INT: mux DBL_NW0[1] bit 3 INT: mux DBL_EE0[1] bit 3 INT: mux DBL_NE0[1] bit 3 INT: mux SNG_N0[0] bit 3 INT: mux SNG_W0[6] bit 3 INT: mux SNG_N0[5] bit 3 INT: mux SNG_E0[0] bit 3 INT: mux IMUX_LOGICIN[48] bit 4 INT: mux IMUX_LOGICIN[25] bit 4 INT: mux IMUX_LOGICIN[13] bit 4 INT: mux IMUX_LOGICIN[54] bit 4 INT: mux IMUX_LOGICIN[41] bit 4 - INT: mux IMUX_LOGICIN[44] bit 4 INT: mux IMUX_LOGICIN[30] bit 4 - -
B17 INT: mux QUAD_NW0[1] bit 4 INT: mux QUAD_WW0[1] bit 4 INT: mux QUAD_NE0[1] bit 4 INT: mux QUAD_NN0[1] bit 4 INT: mux DBL_NN0[1] bit 2 INT: mux DBL_NW0[1] bit 2 INT: mux DBL_EE0[1] bit 2 INT: mux DBL_NE0[1] bit 2 INT: mux SNG_N0[0] bit 2 INT: mux SNG_W0[6] bit 2 INT: mux SNG_N0[5] bit 2 INT: mux SNG_E0[0] bit 2 INT: mux IMUX_LOGICIN[48] bit 5 INT: mux IMUX_LOGICIN[25] bit 5 INT: mux IMUX_LOGICIN[13] bit 5 INT: mux IMUX_LOGICIN[54] bit 5 INT: mux IMUX_LOGICIN[41] bit 5 - INT: mux IMUX_LOGICIN[44] bit 5 INT: mux IMUX_LOGICIN[30] bit 5 - -
B16 INT: mux QUAD_NW0[1] bit 6 INT: mux QUAD_NW0[1] bit 7 INT: mux QUAD_NE0[1] bit 6 INT: mux QUAD_NE0[1] bit 7 INT: mux DBL_NN0[1] bit 6 INT: mux DBL_NN0[1] bit 7 INT: mux DBL_EE0[1] bit 6 INT: mux DBL_EE0[1] bit 7 INT: mux SNG_N0[0] bit 6 INT: mux SNG_N0[0] bit 7 INT: mux SNG_N0[5] bit 6 INT: mux SNG_N0[5] bit 7 INT: mux IMUX_LOGICIN[25] bit 6 INT: mux IMUX_LOGICIN[25] bit 7 INT: mux IMUX_LOGICIN[13] bit 7 INT: mux IMUX_LOGICIN[13] bit 6 - - INT: mux IMUX_LOGICIN[44] bit 7 INT: mux IMUX_LOGICIN[44] bit 6 - -
B15 INT: mux QUAD_SS0[0] bit 6 INT: mux QUAD_SS0[0] bit 7 INT: mux QUAD_EE0[0] bit 6 INT: mux QUAD_EE0[0] bit 7 INT: mux DBL_WW0[0] bit 6 INT: mux DBL_WW0[0] bit 7 INT: mux DBL_SS0[0] bit 6 INT: mux DBL_SS0[0] bit 7 INT: mux SNG_S0[5] bit 6 INT: mux SNG_S0[5] bit 7 INT: mux SNG_S0[0] bit 6 INT: mux SNG_S0[0] bit 7 INT: mux IMUX_LOGICIN[38] bit 6 INT: mux IMUX_LOGICIN[38] bit 7 INT: mux IMUX_LOGICIN[34] bit 7 INT: mux IMUX_LOGICIN[34] bit 6 INT: mux IMUX_LOGICIN[45] bit 6 INT: mux IMUX_LOGICIN[45] bit 7 INT: mux IMUX_LOGICIN[56] bit 7 INT: mux IMUX_LOGICIN[56] bit 6 INT: mux IMUX_GFAN[1] bit 7 -
B14 INT: mux QUAD_SS0[0] bit 3 INT: mux QUAD_SW0[0] bit 3 INT: mux QUAD_EE0[0] bit 2 INT: mux QUAD_SE0[0] bit 2 INT: mux DBL_WW0[0] bit 3 INT: mux DBL_SW0[0] bit 3 INT: mux DBL_SS0[0] bit 3 INT: mux DBL_SE0[0] bit 3 INT: mux SNG_S0[5] bit 3 INT: mux SNG_W0[3] bit 3 INT: mux SNG_S0[0] bit 3 INT: mux SNG_E0[5] bit 3 INT: mux IMUX_LOGICIN[38] bit 0 INT: mux IMUX_LOGICIN[62] bit 0 INT: mux IMUX_LOGICIN[12] bit 0 INT: mux IMUX_LOGICIN[34] bit 0 INT: mux IMUX_LOGICIN[45] bit 0 INT: mux IMUX_LOGICIN[6] bit 0 INT: mux IMUX_LOGICIN[16] bit 0 INT: mux IMUX_LOGICIN[56] bit 0 INT: mux IMUX_GFAN[1] bit 6 -
B13 INT: mux QUAD_SS0[0] bit 0 INT: mux QUAD_SW0[0] bit 0 INT: mux QUAD_EE0[0] bit 4 INT: mux QUAD_SE0[0] bit 4 INT: mux DBL_WW0[0] bit 2 INT: mux DBL_SW0[0] bit 2 INT: mux DBL_SS0[0] bit 2 INT: mux DBL_SE0[0] bit 2 INT: mux SNG_S0[5] bit 2 INT: mux SNG_W0[3] bit 2 INT: mux SNG_S0[0] bit 2 INT: mux SNG_E0[5] bit 2 INT: mux IMUX_LOGICIN[38] bit 3 INT: mux IMUX_LOGICIN[62] bit 3 INT: mux IMUX_LOGICIN[12] bit 3 INT: mux IMUX_LOGICIN[34] bit 3 INT: mux IMUX_LOGICIN[45] bit 3 INT: mux IMUX_LOGICIN[6] bit 3 INT: mux IMUX_LOGICIN[16] bit 3 INT: mux IMUX_LOGICIN[56] bit 3 INT: mux IMUX_GFAN[1] bit 2 -
B12 INT: mux QUAD_SS0[0] bit 5 INT: mux QUAD_SW0[0] bit 5 INT: mux QUAD_EE0[0] bit 5 INT: mux QUAD_SE0[0] bit 5 INT: mux DBL_WW0[0] bit 1 INT: mux DBL_SW0[0] bit 1 INT: mux DBL_SS0[0] bit 1 INT: mux DBL_SE0[0] bit 1 INT: mux SNG_S0[5] bit 1 INT: mux SNG_W0[3] bit 1 INT: mux SNG_S0[0] bit 1 INT: mux SNG_E0[5] bit 1 INT: mux IMUX_LOGICIN[38] bit 1 INT: mux IMUX_LOGICIN[62] bit 1 INT: mux IMUX_LOGICIN[12] bit 1 INT: mux IMUX_LOGICIN[34] bit 1 INT: mux IMUX_LOGICIN[45] bit 1 INT: mux IMUX_LOGICIN[6] bit 1 INT: mux IMUX_LOGICIN[16] bit 2 INT: mux IMUX_LOGICIN[56] bit 2 INT: mux IMUX_GFAN[1] bit 3 -
B11 INT: mux QUAD_SS0[0] bit 2 INT: mux QUAD_SW0[0] bit 2 INT: mux QUAD_EE0[0] bit 1 INT: mux QUAD_SE0[0] bit 1 INT: mux DBL_WW0[0] bit 0 INT: mux DBL_SW0[0] bit 0 INT: mux DBL_SS0[0] bit 0 INT: mux DBL_SE0[0] bit 0 INT: mux SNG_S0[5] bit 0 INT: mux SNG_W0[3] bit 0 INT: mux SNG_S0[0] bit 0 INT: mux SNG_E0[5] bit 0 INT: mux IMUX_LOGICIN[38] bit 2 INT: mux IMUX_LOGICIN[62] bit 2 INT: mux IMUX_LOGICIN[12] bit 2 INT: mux IMUX_LOGICIN[34] bit 2 INT: mux IMUX_LOGICIN[45] bit 2 INT: mux IMUX_LOGICIN[6] bit 2 INT: mux IMUX_LOGICIN[16] bit 1 INT: mux IMUX_LOGICIN[56] bit 1 INT: mux IMUX_GFAN[1] bit 0 -
B10 INT: mux QUAD_SS0[0] bit 4 INT: mux QUAD_SW0[0] bit 4 INT: mux QUAD_EE0[0] bit 3 INT: mux QUAD_SE0[0] bit 3 INT: mux DBL_WW0[0] bit 5 INT: mux DBL_SW0[0] bit 5 INT: mux DBL_SS0[0] bit 5 INT: mux DBL_SE0[0] bit 5 INT: mux SNG_S0[5] bit 5 INT: mux SNG_W0[3] bit 5 INT: mux SNG_S0[0] bit 5 INT: mux SNG_E0[5] bit 5 INT: mux IMUX_LOGICIN[38] bit 4 INT: mux IMUX_LOGICIN[62] bit 4 INT: mux IMUX_LOGICIN[12] bit 4 INT: mux IMUX_LOGICIN[34] bit 4 INT: mux IMUX_LOGICIN[45] bit 4 INT: mux IMUX_LOGICIN[6] bit 4 INT: mux IMUX_LOGICIN[16] bit 4 INT: mux IMUX_LOGICIN[56] bit 4 INT: mux IMUX_GFAN[1] bit 1 -
B9 INT: mux QUAD_SS0[0] bit 1 INT: mux QUAD_SW0[0] bit 1 INT: mux QUAD_EE0[0] bit 0 INT: mux QUAD_SE0[0] bit 0 INT: mux DBL_WW0[0] bit 4 INT: mux DBL_SW0[0] bit 4 INT: mux DBL_SS0[0] bit 4 INT: mux DBL_SE0[0] bit 4 INT: mux SNG_S0[5] bit 4 INT: mux SNG_W0[3] bit 4 INT: mux SNG_S0[0] bit 4 INT: mux SNG_E0[5] bit 4 INT: mux IMUX_LOGICIN[38] bit 5 INT: mux IMUX_LOGICIN[62] bit 5 INT: mux IMUX_LOGICIN[12] bit 5 INT: mux IMUX_LOGICIN[34] bit 5 INT: mux IMUX_LOGICIN[45] bit 5 INT: mux IMUX_LOGICIN[6] bit 5 INT: mux IMUX_LOGICIN[16] bit 5 INT: mux IMUX_LOGICIN[56] bit 5 INT: mux IMUX_GFAN[1] bit 4 -
B8 INT: mux QUAD_SW0[0] bit 7 INT: mux QUAD_SW0[0] bit 6 INT: mux QUAD_SE0[0] bit 7 INT: mux QUAD_SE0[0] bit 6 INT: mux DBL_SW0[0] bit 7 INT: mux DBL_SW0[0] bit 6 INT: mux DBL_SE0[0] bit 7 INT: mux DBL_SE0[0] bit 6 INT: mux SNG_W0[3] bit 7 INT: mux SNG_W0[3] bit 6 INT: mux SNG_E0[5] bit 7 INT: mux SNG_E0[5] bit 6 INT: mux IMUX_LOGICIN[62] bit 6 INT: mux IMUX_LOGICIN[62] bit 7 INT: mux IMUX_LOGICIN[12] bit 7 INT: mux IMUX_LOGICIN[12] bit 6 INT: mux IMUX_LOGICIN[6] bit 6 INT: mux IMUX_LOGICIN[6] bit 7 INT: mux IMUX_LOGICIN[16] bit 7 INT: mux IMUX_LOGICIN[16] bit 6 INT: mux IMUX_GFAN[1] bit 5 -
B7 INT: mux QUAD_WW0[0] bit 7 INT: mux QUAD_WW0[0] bit 6 INT: mux QUAD_NN0[0] bit 7 INT: mux QUAD_NN0[0] bit 6 INT: mux DBL_NW0[0] bit 7 INT: mux DBL_NW0[0] bit 6 INT: mux DBL_NE0[0] bit 7 INT: mux DBL_NE0[0] bit 6 INT: mux SNG_W0[5] bit 7 INT: mux SNG_W0[5] bit 6 INT: mux SNG_E0[3] bit 7 INT: mux SNG_E0[3] bit 6 INT: mux IMUX_LOGICIN[47] bit 6 INT: mux IMUX_LOGICIN[47] bit 7 INT: mux IMUX_LOGICIN[35] bit 7 INT: mux IMUX_LOGICIN[35] bit 6 INT: mux IMUX_LOGICIN[42] bit 6 INT: mux IMUX_LOGICIN[42] bit 7 INT: mux IMUX_LOGICIN[36] bit 7 INT: mux IMUX_LOGICIN[36] bit 6 INT: mux IMUX_GFAN[0] bit 5 -
B6 INT: mux QUAD_NW0[0] bit 2 INT: mux QUAD_WW0[0] bit 2 INT: mux QUAD_NE0[0] bit 1 INT: mux QUAD_NN0[0] bit 1 INT: mux DBL_NN0[0] bit 5 INT: mux DBL_NW0[0] bit 5 INT: mux DBL_EE0[0] bit 5 INT: mux DBL_NE0[0] bit 5 INT: mux SNG_N0[3] bit 5 INT: mux SNG_W0[5] bit 5 INT: mux SNG_N0[4] bit 5 INT: mux SNG_E0[3] bit 5 INT: mux IMUX_LOGICIN[47] bit 0 INT: mux IMUX_LOGICIN[24] bit 0 INT: mux IMUX_LOGICIN[15] bit 0 INT: mux IMUX_LOGICIN[35] bit 0 INT: mux IMUX_LOGICIN[42] bit 0 INT: mux IMUX_LOGICIN[5] bit 0 INT: mux IMUX_LOGICIN[7] bit 0 INT: mux IMUX_LOGICIN[36] bit 0 INT: mux IMUX_GFAN[0] bit 0 -
B5 INT: mux QUAD_NW0[0] bit 1 INT: mux QUAD_WW0[0] bit 1 INT: mux QUAD_NE0[0] bit 2 INT: mux QUAD_NN0[0] bit 2 INT: mux DBL_NN0[0] bit 4 INT: mux DBL_NW0[0] bit 4 INT: mux DBL_EE0[0] bit 4 INT: mux DBL_NE0[0] bit 4 INT: mux SNG_N0[3] bit 4 INT: mux SNG_W0[5] bit 4 INT: mux SNG_N0[4] bit 4 INT: mux SNG_E0[3] bit 4 INT: mux IMUX_LOGICIN[47] bit 3 INT: mux IMUX_LOGICIN[24] bit 3 INT: mux IMUX_LOGICIN[15] bit 3 INT: mux IMUX_LOGICIN[35] bit 3 INT: mux IMUX_LOGICIN[42] bit 3 INT: mux IMUX_LOGICIN[5] bit 3 INT: mux IMUX_LOGICIN[7] bit 3 INT: mux IMUX_LOGICIN[36] bit 3 INT: mux IMUX_GFAN[0] bit 1 -
B4 INT: mux QUAD_NW0[0] bit 0 INT: mux QUAD_WW0[0] bit 0 INT: mux QUAD_NE0[0] bit 0 INT: mux QUAD_NN0[0] bit 0 INT: mux DBL_NN0[0] bit 1 INT: mux DBL_NW0[0] bit 1 INT: mux DBL_EE0[0] bit 0 INT: mux DBL_NE0[0] bit 0 INT: mux SNG_N0[3] bit 1 INT: mux SNG_W0[5] bit 1 INT: mux SNG_N0[4] bit 0 INT: mux SNG_E0[3] bit 0 INT: mux IMUX_LOGICIN[47] bit 1 INT: mux IMUX_LOGICIN[24] bit 1 INT: mux IMUX_LOGICIN[15] bit 1 INT: mux IMUX_LOGICIN[35] bit 1 INT: mux IMUX_LOGICIN[42] bit 1 INT: mux IMUX_LOGICIN[5] bit 1 INT: mux IMUX_LOGICIN[7] bit 2 INT: mux IMUX_LOGICIN[36] bit 2 INT: mux IMUX_GFAN[0] bit 4 -
B3 INT: mux QUAD_NW0[0] bit 5 INT: mux QUAD_WW0[0] bit 5 INT: mux QUAD_NE0[0] bit 5 INT: mux QUAD_NN0[0] bit 5 INT: mux DBL_NN0[0] bit 0 INT: mux DBL_NW0[0] bit 0 INT: mux DBL_EE0[0] bit 1 INT: mux DBL_NE0[0] bit 1 INT: mux SNG_N0[3] bit 0 INT: mux SNG_W0[5] bit 0 INT: mux SNG_N0[4] bit 1 INT: mux SNG_E0[3] bit 1 INT: mux IMUX_LOGICIN[47] bit 2 INT: mux IMUX_LOGICIN[24] bit 2 INT: mux IMUX_LOGICIN[15] bit 2 INT: mux IMUX_LOGICIN[35] bit 2 INT: mux IMUX_LOGICIN[42] bit 2 INT: mux IMUX_LOGICIN[5] bit 2 INT: mux IMUX_LOGICIN[7] bit 1 INT: mux IMUX_LOGICIN[36] bit 1 INT: mux IMUX_GFAN[0] bit 3 -
B2 INT: mux QUAD_NW0[0] bit 3 INT: mux QUAD_WW0[0] bit 3 INT: mux QUAD_NE0[0] bit 3 INT: mux QUAD_NN0[0] bit 3 INT: mux DBL_NN0[0] bit 3 INT: mux DBL_NW0[0] bit 3 INT: mux DBL_EE0[0] bit 3 INT: mux DBL_NE0[0] bit 3 INT: mux SNG_N0[3] bit 3 INT: mux SNG_W0[5] bit 3 INT: mux SNG_N0[4] bit 3 INT: mux SNG_E0[3] bit 3 INT: mux IMUX_LOGICIN[47] bit 4 INT: mux IMUX_LOGICIN[24] bit 4 INT: mux IMUX_LOGICIN[15] bit 4 INT: mux IMUX_LOGICIN[35] bit 4 INT: mux IMUX_LOGICIN[42] bit 4 INT: mux IMUX_LOGICIN[5] bit 4 INT: mux IMUX_LOGICIN[7] bit 4 INT: mux IMUX_LOGICIN[36] bit 4 INT: mux IMUX_GFAN[0] bit 2 -
B1 INT: mux QUAD_NW0[0] bit 4 INT: mux QUAD_WW0[0] bit 4 INT: mux QUAD_NE0[0] bit 4 INT: mux QUAD_NN0[0] bit 4 INT: mux DBL_NN0[0] bit 2 INT: mux DBL_NW0[0] bit 2 INT: mux DBL_EE0[0] bit 2 INT: mux DBL_NE0[0] bit 2 INT: mux SNG_N0[3] bit 2 INT: mux SNG_W0[5] bit 2 INT: mux SNG_N0[4] bit 2 INT: mux SNG_E0[3] bit 2 INT: mux IMUX_LOGICIN[47] bit 5 INT: mux IMUX_LOGICIN[24] bit 5 INT: mux IMUX_LOGICIN[15] bit 5 INT: mux IMUX_LOGICIN[35] bit 5 INT: mux IMUX_LOGICIN[42] bit 5 INT: mux IMUX_LOGICIN[5] bit 5 INT: mux IMUX_LOGICIN[7] bit 5 INT: mux IMUX_LOGICIN[36] bit 5 INT: mux IMUX_GFAN[0] bit 6 -
B0 INT: mux QUAD_NW0[0] bit 6 INT: mux QUAD_NW0[0] bit 7 INT: mux QUAD_NE0[0] bit 6 INT: mux QUAD_NE0[0] bit 7 INT: mux DBL_NN0[0] bit 6 INT: mux DBL_NN0[0] bit 7 INT: mux DBL_EE0[0] bit 6 INT: mux DBL_EE0[0] bit 7 INT: mux SNG_N0[3] bit 6 INT: mux SNG_N0[3] bit 7 INT: mux SNG_N0[4] bit 6 INT: mux SNG_N0[4] bit 7 INT: mux IMUX_LOGICIN[24] bit 6 INT: mux IMUX_LOGICIN[24] bit 7 INT: mux IMUX_LOGICIN[15] bit 7 INT: mux IMUX_LOGICIN[15] bit 6 INT: mux IMUX_LOGICIN[5] bit 6 INT: mux IMUX_LOGICIN[5] bit 7 INT: mux IMUX_LOGICIN[7] bit 7 INT: mux IMUX_LOGICIN[7] bit 6 INT: mux IMUX_GFAN[0] bit 7 -