Clock vertical nodes

Tile RCLK_V_SINGLE.CLE

Cells: 1

Bel BUFCE_ROW_RCLK0

ultrascale RCLK_V_SINGLE.CLE bel BUFCE_ROW_RCLK0
Pin	Direction	Wires
CE_PRE_OPTINV	input	RCLK.IMUX.3
OPT_DELAY_TEST0	input	RCLK.IMUX.0
OPT_DELAY_TEST1	input	RCLK.IMUX.1
OPT_DELAY_TEST2	input	RCLK.IMUX.2

Bel GCLK_TEST_BUF_RCLK0

ultrascale RCLK_V_SINGLE.CLE bel GCLK_TEST_BUF_RCLK0
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_SINGLE.CLE bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_SINGLE.CLE bel wires
Wire	Pins
RCLK.IMUX.0	BUFCE_ROW_RCLK0.OPT_DELAY_TEST0
RCLK.IMUX.1	BUFCE_ROW_RCLK0.OPT_DELAY_TEST1
RCLK.IMUX.2	BUFCE_ROW_RCLK0.OPT_DELAY_TEST2
RCLK.IMUX.3	BUFCE_ROW_RCLK0.CE_PRE_OPTINV

Tile RCLK_V_DOUBLE.BRAM

Cells: 1

Bel BUFCE_ROW_RCLK0

ultrascale RCLK_V_DOUBLE.BRAM bel BUFCE_ROW_RCLK0
Pin	Direction	Wires
CE_PRE_OPTINV	input	RCLK.IMUX.3
OPT_DELAY_TEST0	input	RCLK.IMUX.0
OPT_DELAY_TEST1	input	RCLK.IMUX.1
OPT_DELAY_TEST2	input	RCLK.IMUX.2

Bel BUFCE_ROW_RCLK1

ultrascale RCLK_V_DOUBLE.BRAM bel BUFCE_ROW_RCLK1
Pin	Direction	Wires
CE_PRE_OPTINV	input	RCLK.IMUX.9
OPT_DELAY_TEST0	input	RCLK.IMUX.6
OPT_DELAY_TEST1	input	RCLK.IMUX.7
OPT_DELAY_TEST2	input	RCLK.IMUX.8

Bel GCLK_TEST_BUF_RCLK0

ultrascale RCLK_V_DOUBLE.BRAM bel GCLK_TEST_BUF_RCLK0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_RCLK1

ultrascale RCLK_V_DOUBLE.BRAM bel GCLK_TEST_BUF_RCLK1
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_DOUBLE.BRAM bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_DOUBLE.BRAM bel wires
Wire	Pins
RCLK.IMUX.0	BUFCE_ROW_RCLK0.OPT_DELAY_TEST0
RCLK.IMUX.1	BUFCE_ROW_RCLK0.OPT_DELAY_TEST1
RCLK.IMUX.2	BUFCE_ROW_RCLK0.OPT_DELAY_TEST2
RCLK.IMUX.3	BUFCE_ROW_RCLK0.CE_PRE_OPTINV
RCLK.IMUX.6	BUFCE_ROW_RCLK1.OPT_DELAY_TEST0
RCLK.IMUX.7	BUFCE_ROW_RCLK1.OPT_DELAY_TEST1
RCLK.IMUX.8	BUFCE_ROW_RCLK1.OPT_DELAY_TEST2
RCLK.IMUX.9	BUFCE_ROW_RCLK1.CE_PRE_OPTINV

Tile RCLK_V_DOUBLE.DSP

Cells: 1

Bel BUFCE_ROW_RCLK0

ultrascale RCLK_V_DOUBLE.DSP bel BUFCE_ROW_RCLK0
Pin	Direction	Wires
CE_PRE_OPTINV	input	RCLK.IMUX.3
OPT_DELAY_TEST0	input	RCLK.IMUX.0
OPT_DELAY_TEST1	input	RCLK.IMUX.1
OPT_DELAY_TEST2	input	RCLK.IMUX.2

Bel BUFCE_ROW_RCLK1

ultrascale RCLK_V_DOUBLE.DSP bel BUFCE_ROW_RCLK1
Pin	Direction	Wires
CE_PRE_OPTINV	input	RCLK.IMUX.9
OPT_DELAY_TEST0	input	RCLK.IMUX.6
OPT_DELAY_TEST1	input	RCLK.IMUX.7
OPT_DELAY_TEST2	input	RCLK.IMUX.8

Bel GCLK_TEST_BUF_RCLK0

ultrascale RCLK_V_DOUBLE.DSP bel GCLK_TEST_BUF_RCLK0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_RCLK1

ultrascale RCLK_V_DOUBLE.DSP bel GCLK_TEST_BUF_RCLK1
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_DOUBLE.DSP bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_DOUBLE.DSP bel wires
Wire	Pins
RCLK.IMUX.0	BUFCE_ROW_RCLK0.OPT_DELAY_TEST0
RCLK.IMUX.1	BUFCE_ROW_RCLK0.OPT_DELAY_TEST1
RCLK.IMUX.2	BUFCE_ROW_RCLK0.OPT_DELAY_TEST2
RCLK.IMUX.3	BUFCE_ROW_RCLK0.CE_PRE_OPTINV
RCLK.IMUX.6	BUFCE_ROW_RCLK1.OPT_DELAY_TEST0
RCLK.IMUX.7	BUFCE_ROW_RCLK1.OPT_DELAY_TEST1
RCLK.IMUX.8	BUFCE_ROW_RCLK1.OPT_DELAY_TEST2
RCLK.IMUX.9	BUFCE_ROW_RCLK1.CE_PRE_OPTINV