Clock vertical nodes

Tile RCLK_V_SINGLE_CLE

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascale RCLK_V_SINGLE_CLE bel BUFCE_ROW_RCLK[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	IMUX_RCLK[3]
OPT_DELAY_TEST0	input	IMUX_RCLK[0]
OPT_DELAY_TEST1	input	IMUX_RCLK[1]
OPT_DELAY_TEST2	input	IMUX_RCLK[2]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascale RCLK_V_SINGLE_CLE bel GCLK_TEST_BUF_RCLK[0]
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_SINGLE_CLE bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_SINGLE_CLE bel wires
Wire	Pins
IMUX_RCLK[0]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0
IMUX_RCLK[1]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1
IMUX_RCLK[2]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2
IMUX_RCLK[3]	BUFCE_ROW_RCLK[0].CE_PRE_OPTINV

Tile RCLK_V_DOUBLE_BRAM

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascale RCLK_V_DOUBLE_BRAM bel BUFCE_ROW_RCLK[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	IMUX_RCLK[3]
OPT_DELAY_TEST0	input	IMUX_RCLK[0]
OPT_DELAY_TEST1	input	IMUX_RCLK[1]
OPT_DELAY_TEST2	input	IMUX_RCLK[2]

Bel BUFCE_ROW_RCLK[1]

ultrascale RCLK_V_DOUBLE_BRAM bel BUFCE_ROW_RCLK[1]
Pin	Direction	Wires
CE_PRE_OPTINV	input	IMUX_RCLK[9]
OPT_DELAY_TEST0	input	IMUX_RCLK[6]
OPT_DELAY_TEST1	input	IMUX_RCLK[7]
OPT_DELAY_TEST2	input	IMUX_RCLK[8]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascale RCLK_V_DOUBLE_BRAM bel GCLK_TEST_BUF_RCLK[0]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_RCLK[1]

ultrascale RCLK_V_DOUBLE_BRAM bel GCLK_TEST_BUF_RCLK[1]
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_DOUBLE_BRAM bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_DOUBLE_BRAM bel wires
Wire	Pins
IMUX_RCLK[0]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0
IMUX_RCLK[1]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1
IMUX_RCLK[2]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2
IMUX_RCLK[3]	BUFCE_ROW_RCLK[0].CE_PRE_OPTINV
IMUX_RCLK[6]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST0
IMUX_RCLK[7]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST1
IMUX_RCLK[8]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST2
IMUX_RCLK[9]	BUFCE_ROW_RCLK[1].CE_PRE_OPTINV

Tile RCLK_V_DOUBLE_DSP

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascale RCLK_V_DOUBLE_DSP bel BUFCE_ROW_RCLK[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	IMUX_RCLK[3]
OPT_DELAY_TEST0	input	IMUX_RCLK[0]
OPT_DELAY_TEST1	input	IMUX_RCLK[1]
OPT_DELAY_TEST2	input	IMUX_RCLK[2]

Bel BUFCE_ROW_RCLK[1]

ultrascale RCLK_V_DOUBLE_DSP bel BUFCE_ROW_RCLK[1]
Pin	Direction	Wires
CE_PRE_OPTINV	input	IMUX_RCLK[9]
OPT_DELAY_TEST0	input	IMUX_RCLK[6]
OPT_DELAY_TEST1	input	IMUX_RCLK[7]
OPT_DELAY_TEST2	input	IMUX_RCLK[8]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascale RCLK_V_DOUBLE_DSP bel GCLK_TEST_BUF_RCLK[0]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_RCLK[1]

ultrascale RCLK_V_DOUBLE_DSP bel GCLK_TEST_BUF_RCLK[1]
Pin	Direction	Wires

Bel VCC_RCLK_V

ultrascale RCLK_V_DOUBLE_DSP bel VCC_RCLK_V
Pin	Direction	Wires

Bel wires

ultrascale RCLK_V_DOUBLE_DSP bel wires
Wire	Pins
IMUX_RCLK[0]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0
IMUX_RCLK[1]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1
IMUX_RCLK[2]	BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2
IMUX_RCLK[3]	BUFCE_ROW_RCLK[0].CE_PRE_OPTINV
IMUX_RCLK[6]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST0
IMUX_RCLK[7]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST1
IMUX_RCLK[8]	BUFCE_ROW_RCLK[1].OPT_DELAY_TEST2
IMUX_RCLK[9]	BUFCE_ROW_RCLK[1].CE_PRE_OPTINV