CMAC
Tile CMAC
Cells: 120
Bel CMAC
| Pin | Direction | Wires |
|---|---|---|
| CTL_CAUI4_MODE | input | TCELL19:IMUX.IMUX.47.DELAY |
| CTL_RX_CHECK_ETYPE_GCP | input | TCELL113:IMUX.IMUX.46.DELAY |
| CTL_RX_CHECK_ETYPE_GPP | input | TCELL115:IMUX.IMUX.46.DELAY |
| CTL_RX_CHECK_ETYPE_PCP | input | TCELL115:IMUX.IMUX.40.DELAY |
| CTL_RX_CHECK_ETYPE_PPP | input | TCELL115:IMUX.IMUX.34.DELAY |
| CTL_RX_CHECK_MCAST_GCP | input | TCELL112:IMUX.IMUX.46.DELAY |
| CTL_RX_CHECK_MCAST_GPP | input | TCELL110:IMUX.IMUX.46.DELAY |
| CTL_RX_CHECK_MCAST_PCP | input | TCELL110:IMUX.IMUX.40.DELAY |
| CTL_RX_CHECK_MCAST_PPP | input | TCELL110:IMUX.IMUX.34.DELAY |
| CTL_RX_CHECK_OPCODE_GCP | input | TCELL110:IMUX.IMUX.28.DELAY |
| CTL_RX_CHECK_OPCODE_GPP | input | TCELL110:IMUX.IMUX.22.DELAY |
| CTL_RX_CHECK_OPCODE_PCP | input | TCELL110:IMUX.IMUX.16.DELAY |
| CTL_RX_CHECK_OPCODE_PPP | input | TCELL110:IMUX.IMUX.10.DELAY |
| CTL_RX_CHECK_SA_GCP | input | TCELL113:IMUX.IMUX.28.DELAY |
| CTL_RX_CHECK_SA_GPP | input | TCELL113:IMUX.IMUX.34.DELAY |
| CTL_RX_CHECK_SA_PCP | input | TCELL113:IMUX.IMUX.40.DELAY |
| CTL_RX_CHECK_SA_PPP | input | TCELL112:IMUX.IMUX.40.DELAY |
| CTL_RX_CHECK_UCAST_GCP | input | TCELL112:IMUX.IMUX.34.DELAY |
| CTL_RX_CHECK_UCAST_GPP | input | TCELL112:IMUX.IMUX.28.DELAY |
| CTL_RX_CHECK_UCAST_PCP | input | TCELL112:IMUX.IMUX.22.DELAY |
| CTL_RX_CHECK_UCAST_PPP | input | TCELL112:IMUX.IMUX.16.DELAY |
| CTL_RX_ENABLE | input | TCELL115:IMUX.IMUX.10.DELAY |
| CTL_RX_ENABLE_GCP | input | TCELL113:IMUX.IMUX.10.DELAY |
| CTL_RX_ENABLE_GPP | input | TCELL112:IMUX.IMUX.10.DELAY |
| CTL_RX_ENABLE_PCP | input | TCELL113:IMUX.IMUX.4.DELAY |
| CTL_RX_ENABLE_PPP | input | TCELL112:IMUX.IMUX.4.DELAY |
| CTL_RX_FORCE_RESYNC | input | TCELL113:IMUX.IMUX.22.DELAY |
| CTL_RX_PAUSE_ACK0 | input | TCELL111:IMUX.IMUX.4.DELAY |
| CTL_RX_PAUSE_ACK1 | input | TCELL111:IMUX.IMUX.10.DELAY |
| CTL_RX_PAUSE_ACK2 | input | TCELL111:IMUX.IMUX.16.DELAY |
| CTL_RX_PAUSE_ACK3 | input | TCELL111:IMUX.IMUX.22.DELAY |
| CTL_RX_PAUSE_ACK4 | input | TCELL111:IMUX.IMUX.28.DELAY |
| CTL_RX_PAUSE_ACK5 | input | TCELL111:IMUX.IMUX.34.DELAY |
| CTL_RX_PAUSE_ACK6 | input | TCELL111:IMUX.IMUX.40.DELAY |
| CTL_RX_PAUSE_ACK7 | input | TCELL111:IMUX.IMUX.46.DELAY |
| CTL_RX_PAUSE_ACK8 | input | TCELL110:IMUX.IMUX.4.DELAY |
| CTL_RX_PAUSE_ENABLE0 | input | TCELL114:IMUX.IMUX.4.DELAY |
| CTL_RX_PAUSE_ENABLE1 | input | TCELL114:IMUX.IMUX.10.DELAY |
| CTL_RX_PAUSE_ENABLE2 | input | TCELL114:IMUX.IMUX.16.DELAY |
| CTL_RX_PAUSE_ENABLE3 | input | TCELL114:IMUX.IMUX.22.DELAY |
| CTL_RX_PAUSE_ENABLE4 | input | TCELL114:IMUX.IMUX.28.DELAY |
| CTL_RX_PAUSE_ENABLE5 | input | TCELL114:IMUX.IMUX.34.DELAY |
| CTL_RX_PAUSE_ENABLE6 | input | TCELL114:IMUX.IMUX.40.DELAY |
| CTL_RX_PAUSE_ENABLE7 | input | TCELL114:IMUX.IMUX.46.DELAY |
| CTL_RX_PAUSE_ENABLE8 | input | TCELL115:IMUX.IMUX.4.DELAY |
| CTL_RX_SYSTEMTIMERIN0 | input | TCELL119:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN1 | input | TCELL119:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN10 | input | TCELL118:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN11 | input | TCELL118:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN12 | input | TCELL118:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN13 | input | TCELL118:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN14 | input | TCELL118:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN15 | input | TCELL118:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN16 | input | TCELL117:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN17 | input | TCELL117:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN18 | input | TCELL117:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN19 | input | TCELL117:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN2 | input | TCELL119:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN20 | input | TCELL117:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN21 | input | TCELL117:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN22 | input | TCELL117:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN23 | input | TCELL117:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN24 | input | TCELL116:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN25 | input | TCELL116:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN26 | input | TCELL116:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN27 | input | TCELL116:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN28 | input | TCELL116:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN29 | input | TCELL116:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN3 | input | TCELL119:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN30 | input | TCELL116:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN31 | input | TCELL116:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN32 | input | TCELL115:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN33 | input | TCELL115:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN34 | input | TCELL115:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN35 | input | TCELL115:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN36 | input | TCELL115:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN37 | input | TCELL115:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN38 | input | TCELL115:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN39 | input | TCELL115:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN4 | input | TCELL119:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN40 | input | TCELL114:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN41 | input | TCELL114:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN42 | input | TCELL114:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN43 | input | TCELL114:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN44 | input | TCELL114:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN45 | input | TCELL114:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN46 | input | TCELL114:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN47 | input | TCELL114:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN48 | input | TCELL113:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN49 | input | TCELL113:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN5 | input | TCELL119:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN50 | input | TCELL113:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN51 | input | TCELL113:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN52 | input | TCELL113:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN53 | input | TCELL113:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN54 | input | TCELL113:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN55 | input | TCELL113:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN56 | input | TCELL112:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN57 | input | TCELL112:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN58 | input | TCELL112:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN59 | input | TCELL112:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN6 | input | TCELL119:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN60 | input | TCELL112:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN61 | input | TCELL112:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN62 | input | TCELL112:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN63 | input | TCELL112:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN64 | input | TCELL111:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN65 | input | TCELL111:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN66 | input | TCELL111:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN67 | input | TCELL111:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN68 | input | TCELL111:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN69 | input | TCELL111:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN7 | input | TCELL119:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN70 | input | TCELL111:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN71 | input | TCELL111:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN72 | input | TCELL110:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN73 | input | TCELL110:IMUX.IMUX.7.DELAY |
| CTL_RX_SYSTEMTIMERIN74 | input | TCELL110:IMUX.IMUX.13.DELAY |
| CTL_RX_SYSTEMTIMERIN75 | input | TCELL110:IMUX.IMUX.19.DELAY |
| CTL_RX_SYSTEMTIMERIN76 | input | TCELL110:IMUX.IMUX.25.DELAY |
| CTL_RX_SYSTEMTIMERIN77 | input | TCELL110:IMUX.IMUX.31.DELAY |
| CTL_RX_SYSTEMTIMERIN78 | input | TCELL110:IMUX.IMUX.37.DELAY |
| CTL_RX_SYSTEMTIMERIN79 | input | TCELL110:IMUX.IMUX.43.DELAY |
| CTL_RX_SYSTEMTIMERIN8 | input | TCELL118:IMUX.IMUX.1.DELAY |
| CTL_RX_SYSTEMTIMERIN9 | input | TCELL118:IMUX.IMUX.7.DELAY |
| CTL_RX_TEST_PATTERN | input | TCELL113:IMUX.IMUX.16.DELAY |
| CTL_TX_ENABLE | input | TCELL19:IMUX.IMUX.32.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE | input | TCELL19:IMUX.IMUX.29.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE0 | input | TCELL17:IMUX.IMUX.26.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE1 | input | TCELL17:IMUX.IMUX.29.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE2 | input | TCELL17:IMUX.IMUX.32.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE3 | input | TCELL17:IMUX.IMUX.35.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE4 | input | TCELL17:IMUX.IMUX.38.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE5 | input | TCELL17:IMUX.IMUX.41.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE6 | input | TCELL17:IMUX.IMUX.44.DELAY |
| CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE7 | input | TCELL17:IMUX.IMUX.47.DELAY |
| CTL_TX_PAUSE_ENABLE0 | input | TCELL16:IMUX.IMUX.26.DELAY |
| CTL_TX_PAUSE_ENABLE1 | input | TCELL16:IMUX.IMUX.29.DELAY |
| CTL_TX_PAUSE_ENABLE2 | input | TCELL16:IMUX.IMUX.32.DELAY |
| CTL_TX_PAUSE_ENABLE3 | input | TCELL16:IMUX.IMUX.35.DELAY |
| CTL_TX_PAUSE_ENABLE4 | input | TCELL16:IMUX.IMUX.38.DELAY |
| CTL_TX_PAUSE_ENABLE5 | input | TCELL16:IMUX.IMUX.41.DELAY |
| CTL_TX_PAUSE_ENABLE6 | input | TCELL16:IMUX.IMUX.44.DELAY |
| CTL_TX_PAUSE_ENABLE7 | input | TCELL16:IMUX.IMUX.47.DELAY |
| CTL_TX_PAUSE_ENABLE8 | input | TCELL15:IMUX.IMUX.26.DELAY |
| CTL_TX_PAUSE_QUANTA0_0 | input | TCELL92:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA0_1 | input | TCELL92:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA0_10 | input | TCELL93:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA0_11 | input | TCELL93:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA0_12 | input | TCELL93:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA0_13 | input | TCELL93:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA0_14 | input | TCELL93:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA0_15 | input | TCELL93:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA0_2 | input | TCELL92:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA0_3 | input | TCELL92:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA0_4 | input | TCELL92:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA0_5 | input | TCELL92:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA0_6 | input | TCELL92:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA0_7 | input | TCELL92:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA0_8 | input | TCELL93:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA0_9 | input | TCELL93:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA1_0 | input | TCELL94:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA1_1 | input | TCELL94:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA1_10 | input | TCELL95:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA1_11 | input | TCELL95:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA1_12 | input | TCELL95:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA1_13 | input | TCELL95:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA1_14 | input | TCELL95:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA1_15 | input | TCELL95:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA1_2 | input | TCELL94:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA1_3 | input | TCELL94:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA1_4 | input | TCELL94:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA1_5 | input | TCELL94:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA1_6 | input | TCELL94:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA1_7 | input | TCELL94:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA1_8 | input | TCELL95:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA1_9 | input | TCELL95:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA2_0 | input | TCELL96:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA2_1 | input | TCELL96:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA2_10 | input | TCELL97:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA2_11 | input | TCELL97:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA2_12 | input | TCELL97:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA2_13 | input | TCELL97:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA2_14 | input | TCELL97:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA2_15 | input | TCELL97:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA2_2 | input | TCELL96:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA2_3 | input | TCELL96:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA2_4 | input | TCELL96:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA2_5 | input | TCELL96:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA2_6 | input | TCELL96:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA2_7 | input | TCELL96:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA2_8 | input | TCELL97:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA2_9 | input | TCELL97:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA3_0 | input | TCELL98:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA3_1 | input | TCELL98:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA3_10 | input | TCELL99:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA3_11 | input | TCELL99:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA3_12 | input | TCELL99:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA3_13 | input | TCELL99:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA3_14 | input | TCELL99:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA3_15 | input | TCELL99:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA3_2 | input | TCELL98:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA3_3 | input | TCELL98:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA3_4 | input | TCELL98:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA3_5 | input | TCELL98:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA3_6 | input | TCELL98:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA3_7 | input | TCELL98:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA3_8 | input | TCELL99:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA3_9 | input | TCELL99:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA4_0 | input | TCELL100:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA4_1 | input | TCELL100:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA4_10 | input | TCELL101:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA4_11 | input | TCELL101:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA4_12 | input | TCELL101:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA4_13 | input | TCELL101:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA4_14 | input | TCELL101:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA4_15 | input | TCELL101:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA4_2 | input | TCELL100:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA4_3 | input | TCELL100:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA4_4 | input | TCELL100:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA4_5 | input | TCELL100:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA4_6 | input | TCELL100:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA4_7 | input | TCELL100:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA4_8 | input | TCELL101:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA4_9 | input | TCELL101:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA5_0 | input | TCELL102:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA5_1 | input | TCELL102:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA5_10 | input | TCELL103:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA5_11 | input | TCELL103:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA5_12 | input | TCELL103:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA5_13 | input | TCELL103:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA5_14 | input | TCELL103:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA5_15 | input | TCELL103:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA5_2 | input | TCELL102:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA5_3 | input | TCELL102:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA5_4 | input | TCELL102:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA5_5 | input | TCELL102:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA5_6 | input | TCELL102:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA5_7 | input | TCELL102:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA5_8 | input | TCELL103:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA5_9 | input | TCELL103:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA6_0 | input | TCELL104:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA6_1 | input | TCELL104:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA6_10 | input | TCELL105:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA6_11 | input | TCELL105:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA6_12 | input | TCELL105:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA6_13 | input | TCELL105:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA6_14 | input | TCELL105:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA6_15 | input | TCELL105:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA6_2 | input | TCELL104:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA6_3 | input | TCELL104:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA6_4 | input | TCELL104:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA6_5 | input | TCELL104:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA6_6 | input | TCELL104:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA6_7 | input | TCELL104:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA6_8 | input | TCELL105:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA6_9 | input | TCELL105:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA7_0 | input | TCELL106:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA7_1 | input | TCELL106:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA7_10 | input | TCELL107:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA7_11 | input | TCELL107:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA7_12 | input | TCELL107:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA7_13 | input | TCELL107:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA7_14 | input | TCELL107:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA7_15 | input | TCELL107:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA7_2 | input | TCELL106:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA7_3 | input | TCELL106:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA7_4 | input | TCELL106:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA7_5 | input | TCELL106:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA7_6 | input | TCELL106:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA7_7 | input | TCELL106:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA7_8 | input | TCELL107:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA7_9 | input | TCELL107:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA8_0 | input | TCELL108:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA8_1 | input | TCELL108:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_QUANTA8_10 | input | TCELL109:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA8_11 | input | TCELL109:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA8_12 | input | TCELL109:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA8_13 | input | TCELL109:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA8_14 | input | TCELL109:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA8_15 | input | TCELL109:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA8_2 | input | TCELL108:IMUX.IMUX.16.DELAY |
| CTL_TX_PAUSE_QUANTA8_3 | input | TCELL108:IMUX.IMUX.22.DELAY |
| CTL_TX_PAUSE_QUANTA8_4 | input | TCELL108:IMUX.IMUX.28.DELAY |
| CTL_TX_PAUSE_QUANTA8_5 | input | TCELL108:IMUX.IMUX.34.DELAY |
| CTL_TX_PAUSE_QUANTA8_6 | input | TCELL108:IMUX.IMUX.40.DELAY |
| CTL_TX_PAUSE_QUANTA8_7 | input | TCELL108:IMUX.IMUX.46.DELAY |
| CTL_TX_PAUSE_QUANTA8_8 | input | TCELL109:IMUX.IMUX.4.DELAY |
| CTL_TX_PAUSE_QUANTA8_9 | input | TCELL109:IMUX.IMUX.10.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_0 | input | TCELL92:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_1 | input | TCELL92:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_10 | input | TCELL93:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_11 | input | TCELL93:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_12 | input | TCELL93:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_13 | input | TCELL93:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_14 | input | TCELL93:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_15 | input | TCELL93:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_2 | input | TCELL92:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_3 | input | TCELL92:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_4 | input | TCELL92:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_5 | input | TCELL92:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_6 | input | TCELL92:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_7 | input | TCELL92:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_8 | input | TCELL93:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER0_9 | input | TCELL93:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_0 | input | TCELL94:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_1 | input | TCELL94:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_10 | input | TCELL95:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_11 | input | TCELL95:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_12 | input | TCELL95:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_13 | input | TCELL95:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_14 | input | TCELL95:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_15 | input | TCELL95:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_2 | input | TCELL94:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_3 | input | TCELL94:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_4 | input | TCELL94:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_5 | input | TCELL94:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_6 | input | TCELL94:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_7 | input | TCELL94:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_8 | input | TCELL95:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER1_9 | input | TCELL95:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_0 | input | TCELL96:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_1 | input | TCELL96:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_10 | input | TCELL97:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_11 | input | TCELL97:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_12 | input | TCELL97:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_13 | input | TCELL97:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_14 | input | TCELL97:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_15 | input | TCELL97:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_2 | input | TCELL96:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_3 | input | TCELL96:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_4 | input | TCELL96:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_5 | input | TCELL96:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_6 | input | TCELL96:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_7 | input | TCELL96:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_8 | input | TCELL97:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER2_9 | input | TCELL97:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_0 | input | TCELL98:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_1 | input | TCELL98:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_10 | input | TCELL99:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_11 | input | TCELL99:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_12 | input | TCELL99:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_13 | input | TCELL99:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_14 | input | TCELL99:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_15 | input | TCELL99:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_2 | input | TCELL98:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_3 | input | TCELL98:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_4 | input | TCELL98:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_5 | input | TCELL98:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_6 | input | TCELL98:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_7 | input | TCELL98:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_8 | input | TCELL99:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER3_9 | input | TCELL99:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_0 | input | TCELL100:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_1 | input | TCELL100:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_10 | input | TCELL101:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_11 | input | TCELL101:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_12 | input | TCELL101:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_13 | input | TCELL101:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_14 | input | TCELL101:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_15 | input | TCELL101:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_2 | input | TCELL100:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_3 | input | TCELL100:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_4 | input | TCELL100:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_5 | input | TCELL100:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_6 | input | TCELL100:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_7 | input | TCELL100:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_8 | input | TCELL101:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER4_9 | input | TCELL101:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_0 | input | TCELL102:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_1 | input | TCELL102:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_10 | input | TCELL103:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_11 | input | TCELL103:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_12 | input | TCELL103:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_13 | input | TCELL103:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_14 | input | TCELL103:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_15 | input | TCELL103:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_2 | input | TCELL102:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_3 | input | TCELL102:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_4 | input | TCELL102:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_5 | input | TCELL102:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_6 | input | TCELL102:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_7 | input | TCELL102:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_8 | input | TCELL103:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER5_9 | input | TCELL103:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_0 | input | TCELL104:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_1 | input | TCELL104:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_10 | input | TCELL105:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_11 | input | TCELL105:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_12 | input | TCELL105:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_13 | input | TCELL105:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_14 | input | TCELL105:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_15 | input | TCELL105:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_2 | input | TCELL104:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_3 | input | TCELL104:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_4 | input | TCELL104:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_5 | input | TCELL104:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_6 | input | TCELL104:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_7 | input | TCELL104:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_8 | input | TCELL105:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER6_9 | input | TCELL105:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_0 | input | TCELL106:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_1 | input | TCELL106:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_10 | input | TCELL107:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_11 | input | TCELL107:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_12 | input | TCELL107:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_13 | input | TCELL107:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_14 | input | TCELL107:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_15 | input | TCELL107:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_2 | input | TCELL106:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_3 | input | TCELL106:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_4 | input | TCELL106:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_5 | input | TCELL106:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_6 | input | TCELL106:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_7 | input | TCELL106:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_8 | input | TCELL107:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER7_9 | input | TCELL107:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_0 | input | TCELL108:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_1 | input | TCELL108:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_10 | input | TCELL109:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_11 | input | TCELL109:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_12 | input | TCELL109:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_13 | input | TCELL109:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_14 | input | TCELL109:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_15 | input | TCELL109:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_2 | input | TCELL108:IMUX.IMUX.13.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_3 | input | TCELL108:IMUX.IMUX.19.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_4 | input | TCELL108:IMUX.IMUX.25.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_5 | input | TCELL108:IMUX.IMUX.31.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_6 | input | TCELL108:IMUX.IMUX.37.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_7 | input | TCELL108:IMUX.IMUX.43.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_8 | input | TCELL109:IMUX.IMUX.1.DELAY |
| CTL_TX_PAUSE_REFRESH_TIMER8_9 | input | TCELL109:IMUX.IMUX.7.DELAY |
| CTL_TX_PAUSE_REQ0 | input | TCELL18:IMUX.IMUX.26.DELAY |
| CTL_TX_PAUSE_REQ1 | input | TCELL18:IMUX.IMUX.29.DELAY |
| CTL_TX_PAUSE_REQ2 | input | TCELL18:IMUX.IMUX.32.DELAY |
| CTL_TX_PAUSE_REQ3 | input | TCELL18:IMUX.IMUX.35.DELAY |
| CTL_TX_PAUSE_REQ4 | input | TCELL18:IMUX.IMUX.38.DELAY |
| CTL_TX_PAUSE_REQ5 | input | TCELL18:IMUX.IMUX.41.DELAY |
| CTL_TX_PAUSE_REQ6 | input | TCELL18:IMUX.IMUX.44.DELAY |
| CTL_TX_PAUSE_REQ7 | input | TCELL18:IMUX.IMUX.47.DELAY |
| CTL_TX_PAUSE_REQ8 | input | TCELL19:IMUX.IMUX.26.DELAY |
| CTL_TX_PTP_VLANE_ADJUST_MODE | input | TCELL15:IMUX.IMUX.38.DELAY |
| CTL_TX_RESEND_PAUSE | input | TCELL19:IMUX.IMUX.35.DELAY |
| CTL_TX_SEND_IDLE | input | TCELL19:IMUX.IMUX.41.DELAY |
| CTL_TX_SEND_RFI | input | TCELL19:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN0 | input | TCELL20:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN1 | input | TCELL20:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN10 | input | TCELL21:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN11 | input | TCELL21:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN12 | input | TCELL21:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN13 | input | TCELL21:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN14 | input | TCELL21:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN15 | input | TCELL21:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN16 | input | TCELL22:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN17 | input | TCELL22:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN18 | input | TCELL22:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN19 | input | TCELL22:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN2 | input | TCELL20:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN20 | input | TCELL22:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN21 | input | TCELL22:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN22 | input | TCELL22:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN23 | input | TCELL22:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN24 | input | TCELL23:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN25 | input | TCELL23:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN26 | input | TCELL23:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN27 | input | TCELL23:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN28 | input | TCELL23:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN29 | input | TCELL23:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN3 | input | TCELL20:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN30 | input | TCELL23:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN31 | input | TCELL23:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN32 | input | TCELL24:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN33 | input | TCELL24:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN34 | input | TCELL24:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN35 | input | TCELL24:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN36 | input | TCELL24:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN37 | input | TCELL24:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN38 | input | TCELL24:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN39 | input | TCELL24:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN4 | input | TCELL20:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN40 | input | TCELL25:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN41 | input | TCELL25:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN42 | input | TCELL25:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN43 | input | TCELL25:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN44 | input | TCELL25:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN45 | input | TCELL25:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN46 | input | TCELL25:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN47 | input | TCELL25:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN48 | input | TCELL26:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN49 | input | TCELL26:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN5 | input | TCELL20:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN50 | input | TCELL26:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN51 | input | TCELL26:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN52 | input | TCELL26:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN53 | input | TCELL26:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN54 | input | TCELL26:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN55 | input | TCELL26:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN56 | input | TCELL27:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN57 | input | TCELL27:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN58 | input | TCELL27:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN59 | input | TCELL27:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN6 | input | TCELL20:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN60 | input | TCELL27:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN61 | input | TCELL27:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN62 | input | TCELL27:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN63 | input | TCELL27:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN64 | input | TCELL28:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN65 | input | TCELL28:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN66 | input | TCELL28:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN67 | input | TCELL28:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN68 | input | TCELL28:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN69 | input | TCELL28:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN7 | input | TCELL20:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN70 | input | TCELL28:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN71 | input | TCELL28:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN72 | input | TCELL29:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN73 | input | TCELL29:IMUX.IMUX.29.DELAY |
| CTL_TX_SYSTEMTIMERIN74 | input | TCELL29:IMUX.IMUX.32.DELAY |
| CTL_TX_SYSTEMTIMERIN75 | input | TCELL29:IMUX.IMUX.35.DELAY |
| CTL_TX_SYSTEMTIMERIN76 | input | TCELL29:IMUX.IMUX.38.DELAY |
| CTL_TX_SYSTEMTIMERIN77 | input | TCELL29:IMUX.IMUX.41.DELAY |
| CTL_TX_SYSTEMTIMERIN78 | input | TCELL29:IMUX.IMUX.44.DELAY |
| CTL_TX_SYSTEMTIMERIN79 | input | TCELL29:IMUX.IMUX.47.DELAY |
| CTL_TX_SYSTEMTIMERIN8 | input | TCELL21:IMUX.IMUX.26.DELAY |
| CTL_TX_SYSTEMTIMERIN9 | input | TCELL21:IMUX.IMUX.29.DELAY |
| CTL_TX_TEST_PATTERN | input | TCELL19:IMUX.IMUX.44.DELAY |
| DRP_ADDR0 | input | TCELL118:IMUX.IMUX.4.DELAY |
| DRP_ADDR1 | input | TCELL118:IMUX.IMUX.10.DELAY |
| DRP_ADDR2 | input | TCELL118:IMUX.IMUX.16.DELAY |
| DRP_ADDR3 | input | TCELL118:IMUX.IMUX.22.DELAY |
| DRP_ADDR4 | input | TCELL118:IMUX.IMUX.28.DELAY |
| DRP_ADDR5 | input | TCELL118:IMUX.IMUX.34.DELAY |
| DRP_ADDR6 | input | TCELL118:IMUX.IMUX.40.DELAY |
| DRP_ADDR7 | input | TCELL118:IMUX.IMUX.46.DELAY |
| DRP_ADDR8 | input | TCELL119:IMUX.IMUX.4.DELAY |
| DRP_ADDR9 | input | TCELL119:IMUX.IMUX.10.DELAY |
| DRP_CLK_B | input | TCELL57:IMUX.CTRL.3 |
| DRP_DI0 | input | TCELL116:IMUX.IMUX.4.DELAY |
| DRP_DI1 | input | TCELL116:IMUX.IMUX.10.DELAY |
| DRP_DI10 | input | TCELL117:IMUX.IMUX.16.DELAY |
| DRP_DI11 | input | TCELL117:IMUX.IMUX.22.DELAY |
| DRP_DI12 | input | TCELL117:IMUX.IMUX.28.DELAY |
| DRP_DI13 | input | TCELL117:IMUX.IMUX.34.DELAY |
| DRP_DI14 | input | TCELL117:IMUX.IMUX.40.DELAY |
| DRP_DI15 | input | TCELL117:IMUX.IMUX.46.DELAY |
| DRP_DI2 | input | TCELL116:IMUX.IMUX.16.DELAY |
| DRP_DI3 | input | TCELL116:IMUX.IMUX.22.DELAY |
| DRP_DI4 | input | TCELL116:IMUX.IMUX.28.DELAY |
| DRP_DI5 | input | TCELL116:IMUX.IMUX.34.DELAY |
| DRP_DI6 | input | TCELL116:IMUX.IMUX.40.DELAY |
| DRP_DI7 | input | TCELL116:IMUX.IMUX.46.DELAY |
| DRP_DI8 | input | TCELL117:IMUX.IMUX.4.DELAY |
| DRP_DI9 | input | TCELL117:IMUX.IMUX.10.DELAY |
| DRP_DO0 | output | TCELL59:OUT.0.TMIN |
| DRP_DO1 | output | TCELL59:OUT.2.TMIN |
| DRP_DO10 | output | TCELL58:OUT.4.TMIN |
| DRP_DO11 | output | TCELL58:OUT.6.TMIN |
| DRP_DO12 | output | TCELL58:OUT.8.TMIN |
| DRP_DO13 | output | TCELL58:OUT.10.TMIN |
| DRP_DO14 | output | TCELL58:OUT.12.TMIN |
| DRP_DO15 | output | TCELL58:OUT.14.TMIN |
| DRP_DO2 | output | TCELL59:OUT.4.TMIN |
| DRP_DO3 | output | TCELL59:OUT.6.TMIN |
| DRP_DO4 | output | TCELL59:OUT.8.TMIN |
| DRP_DO5 | output | TCELL59:OUT.10.TMIN |
| DRP_DO6 | output | TCELL59:OUT.12.TMIN |
| DRP_DO7 | output | TCELL59:OUT.14.TMIN |
| DRP_DO8 | output | TCELL58:OUT.0.TMIN |
| DRP_DO9 | output | TCELL58:OUT.2.TMIN |
| DRP_EN | input | TCELL115:IMUX.IMUX.16.DELAY |
| DRP_RDY | output | TCELL56:OUT.14.TMIN |
| DRP_WE | input | TCELL115:IMUX.IMUX.22.DELAY |
| RX_CLK_B | input | TCELL30:IMUX.CTRL.3 |
| RX_DATAOUT0_0 | output | TCELL88:OUT.1.TMIN |
| RX_DATAOUT0_1 | output | TCELL88:OUT.5.TMIN |
| RX_DATAOUT0_10 | output | TCELL89:OUT.9.TMIN |
| RX_DATAOUT0_100 | output | TCELL92:OUT.19.TMIN |
| RX_DATAOUT0_101 | output | TCELL92:OUT.23.TMIN |
| RX_DATAOUT0_102 | output | TCELL92:OUT.27.TMIN |
| RX_DATAOUT0_103 | output | TCELL92:OUT.31.TMIN |
| RX_DATAOUT0_104 | output | TCELL93:OUT.3.TMIN |
| RX_DATAOUT0_105 | output | TCELL93:OUT.7.TMIN |
| RX_DATAOUT0_106 | output | TCELL93:OUT.11.TMIN |
| RX_DATAOUT0_107 | output | TCELL93:OUT.15.TMIN |
| RX_DATAOUT0_108 | output | TCELL93:OUT.19.TMIN |
| RX_DATAOUT0_109 | output | TCELL93:OUT.23.TMIN |
| RX_DATAOUT0_11 | output | TCELL89:OUT.13.TMIN |
| RX_DATAOUT0_110 | output | TCELL93:OUT.27.TMIN |
| RX_DATAOUT0_111 | output | TCELL93:OUT.31.TMIN |
| RX_DATAOUT0_112 | output | TCELL94:OUT.3.TMIN |
| RX_DATAOUT0_113 | output | TCELL94:OUT.7.TMIN |
| RX_DATAOUT0_114 | output | TCELL94:OUT.11.TMIN |
| RX_DATAOUT0_115 | output | TCELL94:OUT.15.TMIN |
| RX_DATAOUT0_116 | output | TCELL94:OUT.19.TMIN |
| RX_DATAOUT0_117 | output | TCELL94:OUT.23.TMIN |
| RX_DATAOUT0_118 | output | TCELL94:OUT.27.TMIN |
| RX_DATAOUT0_119 | output | TCELL94:OUT.31.TMIN |
| RX_DATAOUT0_12 | output | TCELL89:OUT.17.TMIN |
| RX_DATAOUT0_120 | output | TCELL95:OUT.3.TMIN |
| RX_DATAOUT0_121 | output | TCELL95:OUT.7.TMIN |
| RX_DATAOUT0_122 | output | TCELL95:OUT.11.TMIN |
| RX_DATAOUT0_123 | output | TCELL95:OUT.15.TMIN |
| RX_DATAOUT0_124 | output | TCELL95:OUT.19.TMIN |
| RX_DATAOUT0_125 | output | TCELL95:OUT.23.TMIN |
| RX_DATAOUT0_126 | output | TCELL95:OUT.27.TMIN |
| RX_DATAOUT0_127 | output | TCELL95:OUT.31.TMIN |
| RX_DATAOUT0_13 | output | TCELL89:OUT.21.TMIN |
| RX_DATAOUT0_14 | output | TCELL89:OUT.25.TMIN |
| RX_DATAOUT0_15 | output | TCELL89:OUT.29.TMIN |
| RX_DATAOUT0_16 | output | TCELL90:OUT.1.TMIN |
| RX_DATAOUT0_17 | output | TCELL90:OUT.5.TMIN |
| RX_DATAOUT0_18 | output | TCELL90:OUT.9.TMIN |
| RX_DATAOUT0_19 | output | TCELL90:OUT.13.TMIN |
| RX_DATAOUT0_2 | output | TCELL88:OUT.9.TMIN |
| RX_DATAOUT0_20 | output | TCELL90:OUT.17.TMIN |
| RX_DATAOUT0_21 | output | TCELL90:OUT.21.TMIN |
| RX_DATAOUT0_22 | output | TCELL90:OUT.25.TMIN |
| RX_DATAOUT0_23 | output | TCELL90:OUT.29.TMIN |
| RX_DATAOUT0_24 | output | TCELL91:OUT.1.TMIN |
| RX_DATAOUT0_25 | output | TCELL91:OUT.5.TMIN |
| RX_DATAOUT0_26 | output | TCELL91:OUT.9.TMIN |
| RX_DATAOUT0_27 | output | TCELL91:OUT.13.TMIN |
| RX_DATAOUT0_28 | output | TCELL91:OUT.17.TMIN |
| RX_DATAOUT0_29 | output | TCELL91:OUT.21.TMIN |
| RX_DATAOUT0_3 | output | TCELL88:OUT.13.TMIN |
| RX_DATAOUT0_30 | output | TCELL91:OUT.25.TMIN |
| RX_DATAOUT0_31 | output | TCELL91:OUT.29.TMIN |
| RX_DATAOUT0_32 | output | TCELL92:OUT.1.TMIN |
| RX_DATAOUT0_33 | output | TCELL92:OUT.5.TMIN |
| RX_DATAOUT0_34 | output | TCELL92:OUT.9.TMIN |
| RX_DATAOUT0_35 | output | TCELL92:OUT.13.TMIN |
| RX_DATAOUT0_36 | output | TCELL92:OUT.17.TMIN |
| RX_DATAOUT0_37 | output | TCELL92:OUT.21.TMIN |
| RX_DATAOUT0_38 | output | TCELL92:OUT.25.TMIN |
| RX_DATAOUT0_39 | output | TCELL92:OUT.29.TMIN |
| RX_DATAOUT0_4 | output | TCELL88:OUT.17.TMIN |
| RX_DATAOUT0_40 | output | TCELL93:OUT.1.TMIN |
| RX_DATAOUT0_41 | output | TCELL93:OUT.5.TMIN |
| RX_DATAOUT0_42 | output | TCELL93:OUT.9.TMIN |
| RX_DATAOUT0_43 | output | TCELL93:OUT.13.TMIN |
| RX_DATAOUT0_44 | output | TCELL93:OUT.17.TMIN |
| RX_DATAOUT0_45 | output | TCELL93:OUT.21.TMIN |
| RX_DATAOUT0_46 | output | TCELL93:OUT.25.TMIN |
| RX_DATAOUT0_47 | output | TCELL93:OUT.29.TMIN |
| RX_DATAOUT0_48 | output | TCELL94:OUT.1.TMIN |
| RX_DATAOUT0_49 | output | TCELL94:OUT.5.TMIN |
| RX_DATAOUT0_5 | output | TCELL88:OUT.21.TMIN |
| RX_DATAOUT0_50 | output | TCELL94:OUT.9.TMIN |
| RX_DATAOUT0_51 | output | TCELL94:OUT.13.TMIN |
| RX_DATAOUT0_52 | output | TCELL94:OUT.17.TMIN |
| RX_DATAOUT0_53 | output | TCELL94:OUT.21.TMIN |
| RX_DATAOUT0_54 | output | TCELL94:OUT.25.TMIN |
| RX_DATAOUT0_55 | output | TCELL94:OUT.29.TMIN |
| RX_DATAOUT0_56 | output | TCELL95:OUT.1.TMIN |
| RX_DATAOUT0_57 | output | TCELL95:OUT.5.TMIN |
| RX_DATAOUT0_58 | output | TCELL95:OUT.9.TMIN |
| RX_DATAOUT0_59 | output | TCELL95:OUT.13.TMIN |
| RX_DATAOUT0_6 | output | TCELL88:OUT.25.TMIN |
| RX_DATAOUT0_60 | output | TCELL95:OUT.17.TMIN |
| RX_DATAOUT0_61 | output | TCELL95:OUT.21.TMIN |
| RX_DATAOUT0_62 | output | TCELL95:OUT.25.TMIN |
| RX_DATAOUT0_63 | output | TCELL95:OUT.29.TMIN |
| RX_DATAOUT0_64 | output | TCELL88:OUT.3.TMIN |
| RX_DATAOUT0_65 | output | TCELL88:OUT.7.TMIN |
| RX_DATAOUT0_66 | output | TCELL88:OUT.11.TMIN |
| RX_DATAOUT0_67 | output | TCELL88:OUT.15.TMIN |
| RX_DATAOUT0_68 | output | TCELL88:OUT.19.TMIN |
| RX_DATAOUT0_69 | output | TCELL88:OUT.23.TMIN |
| RX_DATAOUT0_7 | output | TCELL88:OUT.29.TMIN |
| RX_DATAOUT0_70 | output | TCELL88:OUT.27.TMIN |
| RX_DATAOUT0_71 | output | TCELL88:OUT.31.TMIN |
| RX_DATAOUT0_72 | output | TCELL89:OUT.3.TMIN |
| RX_DATAOUT0_73 | output | TCELL89:OUT.7.TMIN |
| RX_DATAOUT0_74 | output | TCELL89:OUT.11.TMIN |
| RX_DATAOUT0_75 | output | TCELL89:OUT.15.TMIN |
| RX_DATAOUT0_76 | output | TCELL89:OUT.19.TMIN |
| RX_DATAOUT0_77 | output | TCELL89:OUT.23.TMIN |
| RX_DATAOUT0_78 | output | TCELL89:OUT.27.TMIN |
| RX_DATAOUT0_79 | output | TCELL89:OUT.31.TMIN |
| RX_DATAOUT0_8 | output | TCELL89:OUT.1.TMIN |
| RX_DATAOUT0_80 | output | TCELL90:OUT.3.TMIN |
| RX_DATAOUT0_81 | output | TCELL90:OUT.7.TMIN |
| RX_DATAOUT0_82 | output | TCELL90:OUT.11.TMIN |
| RX_DATAOUT0_83 | output | TCELL90:OUT.15.TMIN |
| RX_DATAOUT0_84 | output | TCELL90:OUT.19.TMIN |
| RX_DATAOUT0_85 | output | TCELL90:OUT.23.TMIN |
| RX_DATAOUT0_86 | output | TCELL90:OUT.27.TMIN |
| RX_DATAOUT0_87 | output | TCELL90:OUT.31.TMIN |
| RX_DATAOUT0_88 | output | TCELL91:OUT.3.TMIN |
| RX_DATAOUT0_89 | output | TCELL91:OUT.7.TMIN |
| RX_DATAOUT0_9 | output | TCELL89:OUT.5.TMIN |
| RX_DATAOUT0_90 | output | TCELL91:OUT.11.TMIN |
| RX_DATAOUT0_91 | output | TCELL91:OUT.15.TMIN |
| RX_DATAOUT0_92 | output | TCELL91:OUT.19.TMIN |
| RX_DATAOUT0_93 | output | TCELL91:OUT.23.TMIN |
| RX_DATAOUT0_94 | output | TCELL91:OUT.27.TMIN |
| RX_DATAOUT0_95 | output | TCELL91:OUT.31.TMIN |
| RX_DATAOUT0_96 | output | TCELL92:OUT.3.TMIN |
| RX_DATAOUT0_97 | output | TCELL92:OUT.7.TMIN |
| RX_DATAOUT0_98 | output | TCELL92:OUT.11.TMIN |
| RX_DATAOUT0_99 | output | TCELL92:OUT.15.TMIN |
| RX_DATAOUT1_0 | output | TCELL96:OUT.1.TMIN |
| RX_DATAOUT1_1 | output | TCELL96:OUT.5.TMIN |
| RX_DATAOUT1_10 | output | TCELL97:OUT.9.TMIN |
| RX_DATAOUT1_100 | output | TCELL100:OUT.19.TMIN |
| RX_DATAOUT1_101 | output | TCELL100:OUT.23.TMIN |
| RX_DATAOUT1_102 | output | TCELL100:OUT.27.TMIN |
| RX_DATAOUT1_103 | output | TCELL100:OUT.31.TMIN |
| RX_DATAOUT1_104 | output | TCELL101:OUT.3.TMIN |
| RX_DATAOUT1_105 | output | TCELL101:OUT.7.TMIN |
| RX_DATAOUT1_106 | output | TCELL101:OUT.11.TMIN |
| RX_DATAOUT1_107 | output | TCELL101:OUT.15.TMIN |
| RX_DATAOUT1_108 | output | TCELL101:OUT.19.TMIN |
| RX_DATAOUT1_109 | output | TCELL101:OUT.23.TMIN |
| RX_DATAOUT1_11 | output | TCELL97:OUT.13.TMIN |
| RX_DATAOUT1_110 | output | TCELL101:OUT.27.TMIN |
| RX_DATAOUT1_111 | output | TCELL101:OUT.31.TMIN |
| RX_DATAOUT1_112 | output | TCELL102:OUT.3.TMIN |
| RX_DATAOUT1_113 | output | TCELL102:OUT.7.TMIN |
| RX_DATAOUT1_114 | output | TCELL102:OUT.11.TMIN |
| RX_DATAOUT1_115 | output | TCELL102:OUT.15.TMIN |
| RX_DATAOUT1_116 | output | TCELL102:OUT.19.TMIN |
| RX_DATAOUT1_117 | output | TCELL102:OUT.23.TMIN |
| RX_DATAOUT1_118 | output | TCELL102:OUT.27.TMIN |
| RX_DATAOUT1_119 | output | TCELL102:OUT.31.TMIN |
| RX_DATAOUT1_12 | output | TCELL97:OUT.17.TMIN |
| RX_DATAOUT1_120 | output | TCELL103:OUT.3.TMIN |
| RX_DATAOUT1_121 | output | TCELL103:OUT.7.TMIN |
| RX_DATAOUT1_122 | output | TCELL103:OUT.11.TMIN |
| RX_DATAOUT1_123 | output | TCELL103:OUT.15.TMIN |
| RX_DATAOUT1_124 | output | TCELL103:OUT.19.TMIN |
| RX_DATAOUT1_125 | output | TCELL103:OUT.23.TMIN |
| RX_DATAOUT1_126 | output | TCELL103:OUT.27.TMIN |
| RX_DATAOUT1_127 | output | TCELL103:OUT.31.TMIN |
| RX_DATAOUT1_13 | output | TCELL97:OUT.21.TMIN |
| RX_DATAOUT1_14 | output | TCELL97:OUT.25.TMIN |
| RX_DATAOUT1_15 | output | TCELL97:OUT.29.TMIN |
| RX_DATAOUT1_16 | output | TCELL98:OUT.1.TMIN |
| RX_DATAOUT1_17 | output | TCELL98:OUT.5.TMIN |
| RX_DATAOUT1_18 | output | TCELL98:OUT.9.TMIN |
| RX_DATAOUT1_19 | output | TCELL98:OUT.13.TMIN |
| RX_DATAOUT1_2 | output | TCELL96:OUT.9.TMIN |
| RX_DATAOUT1_20 | output | TCELL98:OUT.17.TMIN |
| RX_DATAOUT1_21 | output | TCELL98:OUT.21.TMIN |
| RX_DATAOUT1_22 | output | TCELL98:OUT.25.TMIN |
| RX_DATAOUT1_23 | output | TCELL98:OUT.29.TMIN |
| RX_DATAOUT1_24 | output | TCELL99:OUT.1.TMIN |
| RX_DATAOUT1_25 | output | TCELL99:OUT.5.TMIN |
| RX_DATAOUT1_26 | output | TCELL99:OUT.9.TMIN |
| RX_DATAOUT1_27 | output | TCELL99:OUT.13.TMIN |
| RX_DATAOUT1_28 | output | TCELL99:OUT.17.TMIN |
| RX_DATAOUT1_29 | output | TCELL99:OUT.21.TMIN |
| RX_DATAOUT1_3 | output | TCELL96:OUT.13.TMIN |
| RX_DATAOUT1_30 | output | TCELL99:OUT.25.TMIN |
| RX_DATAOUT1_31 | output | TCELL99:OUT.29.TMIN |
| RX_DATAOUT1_32 | output | TCELL100:OUT.1.TMIN |
| RX_DATAOUT1_33 | output | TCELL100:OUT.5.TMIN |
| RX_DATAOUT1_34 | output | TCELL100:OUT.9.TMIN |
| RX_DATAOUT1_35 | output | TCELL100:OUT.13.TMIN |
| RX_DATAOUT1_36 | output | TCELL100:OUT.17.TMIN |
| RX_DATAOUT1_37 | output | TCELL100:OUT.21.TMIN |
| RX_DATAOUT1_38 | output | TCELL100:OUT.25.TMIN |
| RX_DATAOUT1_39 | output | TCELL100:OUT.29.TMIN |
| RX_DATAOUT1_4 | output | TCELL96:OUT.17.TMIN |
| RX_DATAOUT1_40 | output | TCELL101:OUT.1.TMIN |
| RX_DATAOUT1_41 | output | TCELL101:OUT.5.TMIN |
| RX_DATAOUT1_42 | output | TCELL101:OUT.9.TMIN |
| RX_DATAOUT1_43 | output | TCELL101:OUT.13.TMIN |
| RX_DATAOUT1_44 | output | TCELL101:OUT.17.TMIN |
| RX_DATAOUT1_45 | output | TCELL101:OUT.21.TMIN |
| RX_DATAOUT1_46 | output | TCELL101:OUT.25.TMIN |
| RX_DATAOUT1_47 | output | TCELL101:OUT.29.TMIN |
| RX_DATAOUT1_48 | output | TCELL102:OUT.1.TMIN |
| RX_DATAOUT1_49 | output | TCELL102:OUT.5.TMIN |
| RX_DATAOUT1_5 | output | TCELL96:OUT.21.TMIN |
| RX_DATAOUT1_50 | output | TCELL102:OUT.9.TMIN |
| RX_DATAOUT1_51 | output | TCELL102:OUT.13.TMIN |
| RX_DATAOUT1_52 | output | TCELL102:OUT.17.TMIN |
| RX_DATAOUT1_53 | output | TCELL102:OUT.21.TMIN |
| RX_DATAOUT1_54 | output | TCELL102:OUT.25.TMIN |
| RX_DATAOUT1_55 | output | TCELL102:OUT.29.TMIN |
| RX_DATAOUT1_56 | output | TCELL103:OUT.1.TMIN |
| RX_DATAOUT1_57 | output | TCELL103:OUT.5.TMIN |
| RX_DATAOUT1_58 | output | TCELL103:OUT.9.TMIN |
| RX_DATAOUT1_59 | output | TCELL103:OUT.13.TMIN |
| RX_DATAOUT1_6 | output | TCELL96:OUT.25.TMIN |
| RX_DATAOUT1_60 | output | TCELL103:OUT.17.TMIN |
| RX_DATAOUT1_61 | output | TCELL103:OUT.21.TMIN |
| RX_DATAOUT1_62 | output | TCELL103:OUT.25.TMIN |
| RX_DATAOUT1_63 | output | TCELL103:OUT.29.TMIN |
| RX_DATAOUT1_64 | output | TCELL96:OUT.3.TMIN |
| RX_DATAOUT1_65 | output | TCELL96:OUT.7.TMIN |
| RX_DATAOUT1_66 | output | TCELL96:OUT.11.TMIN |
| RX_DATAOUT1_67 | output | TCELL96:OUT.15.TMIN |
| RX_DATAOUT1_68 | output | TCELL96:OUT.19.TMIN |
| RX_DATAOUT1_69 | output | TCELL96:OUT.23.TMIN |
| RX_DATAOUT1_7 | output | TCELL96:OUT.29.TMIN |
| RX_DATAOUT1_70 | output | TCELL96:OUT.27.TMIN |
| RX_DATAOUT1_71 | output | TCELL96:OUT.31.TMIN |
| RX_DATAOUT1_72 | output | TCELL97:OUT.3.TMIN |
| RX_DATAOUT1_73 | output | TCELL97:OUT.7.TMIN |
| RX_DATAOUT1_74 | output | TCELL97:OUT.11.TMIN |
| RX_DATAOUT1_75 | output | TCELL97:OUT.15.TMIN |
| RX_DATAOUT1_76 | output | TCELL97:OUT.19.TMIN |
| RX_DATAOUT1_77 | output | TCELL97:OUT.23.TMIN |
| RX_DATAOUT1_78 | output | TCELL97:OUT.27.TMIN |
| RX_DATAOUT1_79 | output | TCELL97:OUT.31.TMIN |
| RX_DATAOUT1_8 | output | TCELL97:OUT.1.TMIN |
| RX_DATAOUT1_80 | output | TCELL98:OUT.3.TMIN |
| RX_DATAOUT1_81 | output | TCELL98:OUT.7.TMIN |
| RX_DATAOUT1_82 | output | TCELL98:OUT.11.TMIN |
| RX_DATAOUT1_83 | output | TCELL98:OUT.15.TMIN |
| RX_DATAOUT1_84 | output | TCELL98:OUT.19.TMIN |
| RX_DATAOUT1_85 | output | TCELL98:OUT.23.TMIN |
| RX_DATAOUT1_86 | output | TCELL98:OUT.27.TMIN |
| RX_DATAOUT1_87 | output | TCELL98:OUT.31.TMIN |
| RX_DATAOUT1_88 | output | TCELL99:OUT.3.TMIN |
| RX_DATAOUT1_89 | output | TCELL99:OUT.7.TMIN |
| RX_DATAOUT1_9 | output | TCELL97:OUT.5.TMIN |
| RX_DATAOUT1_90 | output | TCELL99:OUT.11.TMIN |
| RX_DATAOUT1_91 | output | TCELL99:OUT.15.TMIN |
| RX_DATAOUT1_92 | output | TCELL99:OUT.19.TMIN |
| RX_DATAOUT1_93 | output | TCELL99:OUT.23.TMIN |
| RX_DATAOUT1_94 | output | TCELL99:OUT.27.TMIN |
| RX_DATAOUT1_95 | output | TCELL99:OUT.31.TMIN |
| RX_DATAOUT1_96 | output | TCELL100:OUT.3.TMIN |
| RX_DATAOUT1_97 | output | TCELL100:OUT.7.TMIN |
| RX_DATAOUT1_98 | output | TCELL100:OUT.11.TMIN |
| RX_DATAOUT1_99 | output | TCELL100:OUT.15.TMIN |
| RX_DATAOUT2_0 | output | TCELL104:OUT.1.TMIN |
| RX_DATAOUT2_1 | output | TCELL104:OUT.5.TMIN |
| RX_DATAOUT2_10 | output | TCELL105:OUT.9.TMIN |
| RX_DATAOUT2_100 | output | TCELL108:OUT.19.TMIN |
| RX_DATAOUT2_101 | output | TCELL108:OUT.23.TMIN |
| RX_DATAOUT2_102 | output | TCELL108:OUT.27.TMIN |
| RX_DATAOUT2_103 | output | TCELL108:OUT.31.TMIN |
| RX_DATAOUT2_104 | output | TCELL109:OUT.3.TMIN |
| RX_DATAOUT2_105 | output | TCELL109:OUT.7.TMIN |
| RX_DATAOUT2_106 | output | TCELL109:OUT.11.TMIN |
| RX_DATAOUT2_107 | output | TCELL109:OUT.15.TMIN |
| RX_DATAOUT2_108 | output | TCELL109:OUT.19.TMIN |
| RX_DATAOUT2_109 | output | TCELL109:OUT.23.TMIN |
| RX_DATAOUT2_11 | output | TCELL105:OUT.13.TMIN |
| RX_DATAOUT2_110 | output | TCELL109:OUT.27.TMIN |
| RX_DATAOUT2_111 | output | TCELL109:OUT.31.TMIN |
| RX_DATAOUT2_112 | output | TCELL110:OUT.3.TMIN |
| RX_DATAOUT2_113 | output | TCELL110:OUT.7.TMIN |
| RX_DATAOUT2_114 | output | TCELL110:OUT.11.TMIN |
| RX_DATAOUT2_115 | output | TCELL110:OUT.15.TMIN |
| RX_DATAOUT2_116 | output | TCELL110:OUT.19.TMIN |
| RX_DATAOUT2_117 | output | TCELL110:OUT.23.TMIN |
| RX_DATAOUT2_118 | output | TCELL110:OUT.27.TMIN |
| RX_DATAOUT2_119 | output | TCELL110:OUT.31.TMIN |
| RX_DATAOUT2_12 | output | TCELL105:OUT.17.TMIN |
| RX_DATAOUT2_120 | output | TCELL111:OUT.3.TMIN |
| RX_DATAOUT2_121 | output | TCELL111:OUT.7.TMIN |
| RX_DATAOUT2_122 | output | TCELL111:OUT.11.TMIN |
| RX_DATAOUT2_123 | output | TCELL111:OUT.15.TMIN |
| RX_DATAOUT2_124 | output | TCELL111:OUT.19.TMIN |
| RX_DATAOUT2_125 | output | TCELL111:OUT.23.TMIN |
| RX_DATAOUT2_126 | output | TCELL111:OUT.27.TMIN |
| RX_DATAOUT2_127 | output | TCELL111:OUT.31.TMIN |
| RX_DATAOUT2_13 | output | TCELL105:OUT.21.TMIN |
| RX_DATAOUT2_14 | output | TCELL105:OUT.25.TMIN |
| RX_DATAOUT2_15 | output | TCELL105:OUT.29.TMIN |
| RX_DATAOUT2_16 | output | TCELL106:OUT.1.TMIN |
| RX_DATAOUT2_17 | output | TCELL106:OUT.5.TMIN |
| RX_DATAOUT2_18 | output | TCELL106:OUT.9.TMIN |
| RX_DATAOUT2_19 | output | TCELL106:OUT.13.TMIN |
| RX_DATAOUT2_2 | output | TCELL104:OUT.9.TMIN |
| RX_DATAOUT2_20 | output | TCELL106:OUT.17.TMIN |
| RX_DATAOUT2_21 | output | TCELL106:OUT.21.TMIN |
| RX_DATAOUT2_22 | output | TCELL106:OUT.25.TMIN |
| RX_DATAOUT2_23 | output | TCELL106:OUT.29.TMIN |
| RX_DATAOUT2_24 | output | TCELL107:OUT.1.TMIN |
| RX_DATAOUT2_25 | output | TCELL107:OUT.5.TMIN |
| RX_DATAOUT2_26 | output | TCELL107:OUT.9.TMIN |
| RX_DATAOUT2_27 | output | TCELL107:OUT.13.TMIN |
| RX_DATAOUT2_28 | output | TCELL107:OUT.17.TMIN |
| RX_DATAOUT2_29 | output | TCELL107:OUT.21.TMIN |
| RX_DATAOUT2_3 | output | TCELL104:OUT.13.TMIN |
| RX_DATAOUT2_30 | output | TCELL107:OUT.25.TMIN |
| RX_DATAOUT2_31 | output | TCELL107:OUT.29.TMIN |
| RX_DATAOUT2_32 | output | TCELL108:OUT.1.TMIN |
| RX_DATAOUT2_33 | output | TCELL108:OUT.5.TMIN |
| RX_DATAOUT2_34 | output | TCELL108:OUT.9.TMIN |
| RX_DATAOUT2_35 | output | TCELL108:OUT.13.TMIN |
| RX_DATAOUT2_36 | output | TCELL108:OUT.17.TMIN |
| RX_DATAOUT2_37 | output | TCELL108:OUT.21.TMIN |
| RX_DATAOUT2_38 | output | TCELL108:OUT.25.TMIN |
| RX_DATAOUT2_39 | output | TCELL108:OUT.29.TMIN |
| RX_DATAOUT2_4 | output | TCELL104:OUT.17.TMIN |
| RX_DATAOUT2_40 | output | TCELL109:OUT.1.TMIN |
| RX_DATAOUT2_41 | output | TCELL109:OUT.5.TMIN |
| RX_DATAOUT2_42 | output | TCELL109:OUT.9.TMIN |
| RX_DATAOUT2_43 | output | TCELL109:OUT.13.TMIN |
| RX_DATAOUT2_44 | output | TCELL109:OUT.17.TMIN |
| RX_DATAOUT2_45 | output | TCELL109:OUT.21.TMIN |
| RX_DATAOUT2_46 | output | TCELL109:OUT.25.TMIN |
| RX_DATAOUT2_47 | output | TCELL109:OUT.29.TMIN |
| RX_DATAOUT2_48 | output | TCELL110:OUT.1.TMIN |
| RX_DATAOUT2_49 | output | TCELL110:OUT.5.TMIN |
| RX_DATAOUT2_5 | output | TCELL104:OUT.21.TMIN |
| RX_DATAOUT2_50 | output | TCELL110:OUT.9.TMIN |
| RX_DATAOUT2_51 | output | TCELL110:OUT.13.TMIN |
| RX_DATAOUT2_52 | output | TCELL110:OUT.17.TMIN |
| RX_DATAOUT2_53 | output | TCELL110:OUT.21.TMIN |
| RX_DATAOUT2_54 | output | TCELL110:OUT.25.TMIN |
| RX_DATAOUT2_55 | output | TCELL110:OUT.29.TMIN |
| RX_DATAOUT2_56 | output | TCELL111:OUT.1.TMIN |
| RX_DATAOUT2_57 | output | TCELL111:OUT.5.TMIN |
| RX_DATAOUT2_58 | output | TCELL111:OUT.9.TMIN |
| RX_DATAOUT2_59 | output | TCELL111:OUT.13.TMIN |
| RX_DATAOUT2_6 | output | TCELL104:OUT.25.TMIN |
| RX_DATAOUT2_60 | output | TCELL111:OUT.17.TMIN |
| RX_DATAOUT2_61 | output | TCELL111:OUT.21.TMIN |
| RX_DATAOUT2_62 | output | TCELL111:OUT.25.TMIN |
| RX_DATAOUT2_63 | output | TCELL111:OUT.29.TMIN |
| RX_DATAOUT2_64 | output | TCELL104:OUT.3.TMIN |
| RX_DATAOUT2_65 | output | TCELL104:OUT.7.TMIN |
| RX_DATAOUT2_66 | output | TCELL104:OUT.11.TMIN |
| RX_DATAOUT2_67 | output | TCELL104:OUT.15.TMIN |
| RX_DATAOUT2_68 | output | TCELL104:OUT.19.TMIN |
| RX_DATAOUT2_69 | output | TCELL104:OUT.23.TMIN |
| RX_DATAOUT2_7 | output | TCELL104:OUT.29.TMIN |
| RX_DATAOUT2_70 | output | TCELL104:OUT.27.TMIN |
| RX_DATAOUT2_71 | output | TCELL104:OUT.31.TMIN |
| RX_DATAOUT2_72 | output | TCELL105:OUT.3.TMIN |
| RX_DATAOUT2_73 | output | TCELL105:OUT.7.TMIN |
| RX_DATAOUT2_74 | output | TCELL105:OUT.11.TMIN |
| RX_DATAOUT2_75 | output | TCELL105:OUT.15.TMIN |
| RX_DATAOUT2_76 | output | TCELL105:OUT.19.TMIN |
| RX_DATAOUT2_77 | output | TCELL105:OUT.23.TMIN |
| RX_DATAOUT2_78 | output | TCELL105:OUT.27.TMIN |
| RX_DATAOUT2_79 | output | TCELL105:OUT.31.TMIN |
| RX_DATAOUT2_8 | output | TCELL105:OUT.1.TMIN |
| RX_DATAOUT2_80 | output | TCELL106:OUT.3.TMIN |
| RX_DATAOUT2_81 | output | TCELL106:OUT.7.TMIN |
| RX_DATAOUT2_82 | output | TCELL106:OUT.11.TMIN |
| RX_DATAOUT2_83 | output | TCELL106:OUT.15.TMIN |
| RX_DATAOUT2_84 | output | TCELL106:OUT.19.TMIN |
| RX_DATAOUT2_85 | output | TCELL106:OUT.23.TMIN |
| RX_DATAOUT2_86 | output | TCELL106:OUT.27.TMIN |
| RX_DATAOUT2_87 | output | TCELL106:OUT.31.TMIN |
| RX_DATAOUT2_88 | output | TCELL107:OUT.3.TMIN |
| RX_DATAOUT2_89 | output | TCELL107:OUT.7.TMIN |
| RX_DATAOUT2_9 | output | TCELL105:OUT.5.TMIN |
| RX_DATAOUT2_90 | output | TCELL107:OUT.11.TMIN |
| RX_DATAOUT2_91 | output | TCELL107:OUT.15.TMIN |
| RX_DATAOUT2_92 | output | TCELL107:OUT.19.TMIN |
| RX_DATAOUT2_93 | output | TCELL107:OUT.23.TMIN |
| RX_DATAOUT2_94 | output | TCELL107:OUT.27.TMIN |
| RX_DATAOUT2_95 | output | TCELL107:OUT.31.TMIN |
| RX_DATAOUT2_96 | output | TCELL108:OUT.3.TMIN |
| RX_DATAOUT2_97 | output | TCELL108:OUT.7.TMIN |
| RX_DATAOUT2_98 | output | TCELL108:OUT.11.TMIN |
| RX_DATAOUT2_99 | output | TCELL108:OUT.15.TMIN |
| RX_DATAOUT3_0 | output | TCELL112:OUT.1.TMIN |
| RX_DATAOUT3_1 | output | TCELL112:OUT.5.TMIN |
| RX_DATAOUT3_10 | output | TCELL113:OUT.9.TMIN |
| RX_DATAOUT3_100 | output | TCELL116:OUT.19.TMIN |
| RX_DATAOUT3_101 | output | TCELL116:OUT.23.TMIN |
| RX_DATAOUT3_102 | output | TCELL116:OUT.27.TMIN |
| RX_DATAOUT3_103 | output | TCELL116:OUT.31.TMIN |
| RX_DATAOUT3_104 | output | TCELL117:OUT.3.TMIN |
| RX_DATAOUT3_105 | output | TCELL117:OUT.7.TMIN |
| RX_DATAOUT3_106 | output | TCELL117:OUT.11.TMIN |
| RX_DATAOUT3_107 | output | TCELL117:OUT.15.TMIN |
| RX_DATAOUT3_108 | output | TCELL117:OUT.19.TMIN |
| RX_DATAOUT3_109 | output | TCELL117:OUT.23.TMIN |
| RX_DATAOUT3_11 | output | TCELL113:OUT.13.TMIN |
| RX_DATAOUT3_110 | output | TCELL117:OUT.27.TMIN |
| RX_DATAOUT3_111 | output | TCELL117:OUT.31.TMIN |
| RX_DATAOUT3_112 | output | TCELL118:OUT.3.TMIN |
| RX_DATAOUT3_113 | output | TCELL118:OUT.7.TMIN |
| RX_DATAOUT3_114 | output | TCELL118:OUT.11.TMIN |
| RX_DATAOUT3_115 | output | TCELL118:OUT.15.TMIN |
| RX_DATAOUT3_116 | output | TCELL118:OUT.19.TMIN |
| RX_DATAOUT3_117 | output | TCELL118:OUT.23.TMIN |
| RX_DATAOUT3_118 | output | TCELL118:OUT.27.TMIN |
| RX_DATAOUT3_119 | output | TCELL118:OUT.31.TMIN |
| RX_DATAOUT3_12 | output | TCELL113:OUT.17.TMIN |
| RX_DATAOUT3_120 | output | TCELL119:OUT.3.TMIN |
| RX_DATAOUT3_121 | output | TCELL119:OUT.7.TMIN |
| RX_DATAOUT3_122 | output | TCELL119:OUT.11.TMIN |
| RX_DATAOUT3_123 | output | TCELL119:OUT.15.TMIN |
| RX_DATAOUT3_124 | output | TCELL119:OUT.19.TMIN |
| RX_DATAOUT3_125 | output | TCELL119:OUT.23.TMIN |
| RX_DATAOUT3_126 | output | TCELL119:OUT.27.TMIN |
| RX_DATAOUT3_127 | output | TCELL119:OUT.31.TMIN |
| RX_DATAOUT3_13 | output | TCELL113:OUT.21.TMIN |
| RX_DATAOUT3_14 | output | TCELL113:OUT.25.TMIN |
| RX_DATAOUT3_15 | output | TCELL113:OUT.29.TMIN |
| RX_DATAOUT3_16 | output | TCELL114:OUT.1.TMIN |
| RX_DATAOUT3_17 | output | TCELL114:OUT.5.TMIN |
| RX_DATAOUT3_18 | output | TCELL114:OUT.9.TMIN |
| RX_DATAOUT3_19 | output | TCELL114:OUT.13.TMIN |
| RX_DATAOUT3_2 | output | TCELL112:OUT.9.TMIN |
| RX_DATAOUT3_20 | output | TCELL114:OUT.17.TMIN |
| RX_DATAOUT3_21 | output | TCELL114:OUT.21.TMIN |
| RX_DATAOUT3_22 | output | TCELL114:OUT.25.TMIN |
| RX_DATAOUT3_23 | output | TCELL114:OUT.29.TMIN |
| RX_DATAOUT3_24 | output | TCELL115:OUT.1.TMIN |
| RX_DATAOUT3_25 | output | TCELL115:OUT.5.TMIN |
| RX_DATAOUT3_26 | output | TCELL115:OUT.9.TMIN |
| RX_DATAOUT3_27 | output | TCELL115:OUT.13.TMIN |
| RX_DATAOUT3_28 | output | TCELL115:OUT.17.TMIN |
| RX_DATAOUT3_29 | output | TCELL115:OUT.21.TMIN |
| RX_DATAOUT3_3 | output | TCELL112:OUT.13.TMIN |
| RX_DATAOUT3_30 | output | TCELL115:OUT.25.TMIN |
| RX_DATAOUT3_31 | output | TCELL115:OUT.29.TMIN |
| RX_DATAOUT3_32 | output | TCELL116:OUT.1.TMIN |
| RX_DATAOUT3_33 | output | TCELL116:OUT.5.TMIN |
| RX_DATAOUT3_34 | output | TCELL116:OUT.9.TMIN |
| RX_DATAOUT3_35 | output | TCELL116:OUT.13.TMIN |
| RX_DATAOUT3_36 | output | TCELL116:OUT.17.TMIN |
| RX_DATAOUT3_37 | output | TCELL116:OUT.21.TMIN |
| RX_DATAOUT3_38 | output | TCELL116:OUT.25.TMIN |
| RX_DATAOUT3_39 | output | TCELL116:OUT.29.TMIN |
| RX_DATAOUT3_4 | output | TCELL112:OUT.17.TMIN |
| RX_DATAOUT3_40 | output | TCELL117:OUT.1.TMIN |
| RX_DATAOUT3_41 | output | TCELL117:OUT.5.TMIN |
| RX_DATAOUT3_42 | output | TCELL117:OUT.9.TMIN |
| RX_DATAOUT3_43 | output | TCELL117:OUT.13.TMIN |
| RX_DATAOUT3_44 | output | TCELL117:OUT.17.TMIN |
| RX_DATAOUT3_45 | output | TCELL117:OUT.21.TMIN |
| RX_DATAOUT3_46 | output | TCELL117:OUT.25.TMIN |
| RX_DATAOUT3_47 | output | TCELL117:OUT.29.TMIN |
| RX_DATAOUT3_48 | output | TCELL118:OUT.1.TMIN |
| RX_DATAOUT3_49 | output | TCELL118:OUT.5.TMIN |
| RX_DATAOUT3_5 | output | TCELL112:OUT.21.TMIN |
| RX_DATAOUT3_50 | output | TCELL118:OUT.9.TMIN |
| RX_DATAOUT3_51 | output | TCELL118:OUT.13.TMIN |
| RX_DATAOUT3_52 | output | TCELL118:OUT.17.TMIN |
| RX_DATAOUT3_53 | output | TCELL118:OUT.21.TMIN |
| RX_DATAOUT3_54 | output | TCELL118:OUT.25.TMIN |
| RX_DATAOUT3_55 | output | TCELL118:OUT.29.TMIN |
| RX_DATAOUT3_56 | output | TCELL119:OUT.1.TMIN |
| RX_DATAOUT3_57 | output | TCELL119:OUT.5.TMIN |
| RX_DATAOUT3_58 | output | TCELL119:OUT.9.TMIN |
| RX_DATAOUT3_59 | output | TCELL119:OUT.13.TMIN |
| RX_DATAOUT3_6 | output | TCELL112:OUT.25.TMIN |
| RX_DATAOUT3_60 | output | TCELL119:OUT.17.TMIN |
| RX_DATAOUT3_61 | output | TCELL119:OUT.21.TMIN |
| RX_DATAOUT3_62 | output | TCELL119:OUT.25.TMIN |
| RX_DATAOUT3_63 | output | TCELL119:OUT.29.TMIN |
| RX_DATAOUT3_64 | output | TCELL112:OUT.3.TMIN |
| RX_DATAOUT3_65 | output | TCELL112:OUT.7.TMIN |
| RX_DATAOUT3_66 | output | TCELL112:OUT.11.TMIN |
| RX_DATAOUT3_67 | output | TCELL112:OUT.15.TMIN |
| RX_DATAOUT3_68 | output | TCELL112:OUT.19.TMIN |
| RX_DATAOUT3_69 | output | TCELL112:OUT.23.TMIN |
| RX_DATAOUT3_7 | output | TCELL112:OUT.29.TMIN |
| RX_DATAOUT3_70 | output | TCELL112:OUT.27.TMIN |
| RX_DATAOUT3_71 | output | TCELL112:OUT.31.TMIN |
| RX_DATAOUT3_72 | output | TCELL113:OUT.3.TMIN |
| RX_DATAOUT3_73 | output | TCELL113:OUT.7.TMIN |
| RX_DATAOUT3_74 | output | TCELL113:OUT.11.TMIN |
| RX_DATAOUT3_75 | output | TCELL113:OUT.15.TMIN |
| RX_DATAOUT3_76 | output | TCELL113:OUT.19.TMIN |
| RX_DATAOUT3_77 | output | TCELL113:OUT.23.TMIN |
| RX_DATAOUT3_78 | output | TCELL113:OUT.27.TMIN |
| RX_DATAOUT3_79 | output | TCELL113:OUT.31.TMIN |
| RX_DATAOUT3_8 | output | TCELL113:OUT.1.TMIN |
| RX_DATAOUT3_80 | output | TCELL114:OUT.3.TMIN |
| RX_DATAOUT3_81 | output | TCELL114:OUT.7.TMIN |
| RX_DATAOUT3_82 | output | TCELL114:OUT.11.TMIN |
| RX_DATAOUT3_83 | output | TCELL114:OUT.15.TMIN |
| RX_DATAOUT3_84 | output | TCELL114:OUT.19.TMIN |
| RX_DATAOUT3_85 | output | TCELL114:OUT.23.TMIN |
| RX_DATAOUT3_86 | output | TCELL114:OUT.27.TMIN |
| RX_DATAOUT3_87 | output | TCELL114:OUT.31.TMIN |
| RX_DATAOUT3_88 | output | TCELL115:OUT.3.TMIN |
| RX_DATAOUT3_89 | output | TCELL115:OUT.7.TMIN |
| RX_DATAOUT3_9 | output | TCELL113:OUT.5.TMIN |
| RX_DATAOUT3_90 | output | TCELL115:OUT.11.TMIN |
| RX_DATAOUT3_91 | output | TCELL115:OUT.15.TMIN |
| RX_DATAOUT3_92 | output | TCELL115:OUT.19.TMIN |
| RX_DATAOUT3_93 | output | TCELL115:OUT.23.TMIN |
| RX_DATAOUT3_94 | output | TCELL115:OUT.27.TMIN |
| RX_DATAOUT3_95 | output | TCELL115:OUT.31.TMIN |
| RX_DATAOUT3_96 | output | TCELL116:OUT.3.TMIN |
| RX_DATAOUT3_97 | output | TCELL116:OUT.7.TMIN |
| RX_DATAOUT3_98 | output | TCELL116:OUT.11.TMIN |
| RX_DATAOUT3_99 | output | TCELL116:OUT.15.TMIN |
| RX_ENAOUT0 | output | TCELL88:OUT.16.TMIN |
| RX_ENAOUT1 | output | TCELL96:OUT.16.TMIN |
| RX_ENAOUT2 | output | TCELL104:OUT.16.TMIN |
| RX_ENAOUT3 | output | TCELL112:OUT.16.TMIN |
| RX_EOPOUT0 | output | TCELL89:OUT.16.TMIN |
| RX_EOPOUT1 | output | TCELL97:OUT.16.TMIN |
| RX_EOPOUT2 | output | TCELL105:OUT.16.TMIN |
| RX_EOPOUT3 | output | TCELL113:OUT.16.TMIN |
| RX_ERROUT0 | output | TCELL91:OUT.16.TMIN |
| RX_ERROUT1 | output | TCELL99:OUT.16.TMIN |
| RX_ERROUT2 | output | TCELL107:OUT.16.TMIN |
| RX_ERROUT3 | output | TCELL115:OUT.16.TMIN |
| RX_LANE_ALIGNER_FILL_0_0 | output | TCELL87:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_0_1 | output | TCELL87:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_0_2 | output | TCELL87:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_0_3 | output | TCELL87:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_0_4 | output | TCELL87:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_0_5 | output | TCELL87:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_0_6 | output | TCELL87:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_10_0 | output | TCELL82:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_10_1 | output | TCELL82:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_10_2 | output | TCELL82:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_10_3 | output | TCELL82:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_10_4 | output | TCELL82:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_10_5 | output | TCELL82:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_10_6 | output | TCELL82:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_11_0 | output | TCELL82:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_11_1 | output | TCELL82:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_11_2 | output | TCELL82:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_11_3 | output | TCELL82:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_11_4 | output | TCELL82:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_11_5 | output | TCELL82:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_11_6 | output | TCELL82:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_12_0 | output | TCELL81:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_12_1 | output | TCELL81:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_12_2 | output | TCELL81:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_12_3 | output | TCELL81:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_12_4 | output | TCELL81:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_12_5 | output | TCELL81:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_12_6 | output | TCELL81:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_13_0 | output | TCELL81:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_13_1 | output | TCELL81:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_13_2 | output | TCELL81:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_13_3 | output | TCELL81:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_13_4 | output | TCELL81:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_13_5 | output | TCELL81:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_13_6 | output | TCELL81:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_14_0 | output | TCELL80:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_14_1 | output | TCELL80:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_14_2 | output | TCELL80:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_14_3 | output | TCELL80:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_14_4 | output | TCELL80:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_14_5 | output | TCELL80:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_14_6 | output | TCELL80:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_15_0 | output | TCELL80:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_15_1 | output | TCELL80:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_15_2 | output | TCELL80:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_15_3 | output | TCELL80:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_15_4 | output | TCELL80:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_15_5 | output | TCELL80:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_15_6 | output | TCELL80:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_16_0 | output | TCELL79:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_16_1 | output | TCELL79:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_16_2 | output | TCELL79:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_16_3 | output | TCELL79:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_16_4 | output | TCELL79:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_16_5 | output | TCELL79:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_16_6 | output | TCELL79:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_17_0 | output | TCELL79:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_17_1 | output | TCELL79:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_17_2 | output | TCELL79:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_17_3 | output | TCELL79:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_17_4 | output | TCELL79:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_17_5 | output | TCELL79:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_17_6 | output | TCELL79:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_18_0 | output | TCELL78:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_18_1 | output | TCELL78:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_18_2 | output | TCELL78:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_18_3 | output | TCELL78:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_18_4 | output | TCELL78:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_18_5 | output | TCELL78:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_18_6 | output | TCELL78:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_19_0 | output | TCELL78:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_19_1 | output | TCELL78:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_19_2 | output | TCELL78:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_19_3 | output | TCELL78:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_19_4 | output | TCELL78:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_19_5 | output | TCELL78:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_19_6 | output | TCELL78:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_1_0 | output | TCELL87:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_1_1 | output | TCELL87:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_1_2 | output | TCELL87:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_1_3 | output | TCELL87:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_1_4 | output | TCELL87:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_1_5 | output | TCELL87:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_1_6 | output | TCELL87:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_2_0 | output | TCELL86:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_2_1 | output | TCELL86:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_2_2 | output | TCELL86:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_2_3 | output | TCELL86:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_2_4 | output | TCELL86:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_2_5 | output | TCELL86:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_2_6 | output | TCELL86:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_3_0 | output | TCELL86:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_3_1 | output | TCELL86:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_3_2 | output | TCELL86:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_3_3 | output | TCELL86:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_3_4 | output | TCELL86:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_3_5 | output | TCELL86:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_3_6 | output | TCELL86:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_4_0 | output | TCELL85:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_4_1 | output | TCELL85:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_4_2 | output | TCELL85:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_4_3 | output | TCELL85:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_4_4 | output | TCELL85:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_4_5 | output | TCELL85:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_4_6 | output | TCELL85:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_5_0 | output | TCELL85:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_5_1 | output | TCELL85:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_5_2 | output | TCELL85:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_5_3 | output | TCELL85:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_5_4 | output | TCELL85:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_5_5 | output | TCELL85:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_5_6 | output | TCELL85:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_6_0 | output | TCELL84:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_6_1 | output | TCELL84:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_6_2 | output | TCELL84:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_6_3 | output | TCELL84:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_6_4 | output | TCELL84:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_6_5 | output | TCELL84:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_6_6 | output | TCELL84:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_7_0 | output | TCELL84:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_7_1 | output | TCELL84:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_7_2 | output | TCELL84:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_7_3 | output | TCELL84:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_7_4 | output | TCELL84:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_7_5 | output | TCELL84:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_7_6 | output | TCELL84:OUT.25.TMIN |
| RX_LANE_ALIGNER_FILL_8_0 | output | TCELL83:OUT.3.TMIN |
| RX_LANE_ALIGNER_FILL_8_1 | output | TCELL83:OUT.7.TMIN |
| RX_LANE_ALIGNER_FILL_8_2 | output | TCELL83:OUT.11.TMIN |
| RX_LANE_ALIGNER_FILL_8_3 | output | TCELL83:OUT.15.TMIN |
| RX_LANE_ALIGNER_FILL_8_4 | output | TCELL83:OUT.19.TMIN |
| RX_LANE_ALIGNER_FILL_8_5 | output | TCELL83:OUT.23.TMIN |
| RX_LANE_ALIGNER_FILL_8_6 | output | TCELL83:OUT.27.TMIN |
| RX_LANE_ALIGNER_FILL_9_0 | output | TCELL83:OUT.1.TMIN |
| RX_LANE_ALIGNER_FILL_9_1 | output | TCELL83:OUT.5.TMIN |
| RX_LANE_ALIGNER_FILL_9_2 | output | TCELL83:OUT.9.TMIN |
| RX_LANE_ALIGNER_FILL_9_3 | output | TCELL83:OUT.13.TMIN |
| RX_LANE_ALIGNER_FILL_9_4 | output | TCELL83:OUT.17.TMIN |
| RX_LANE_ALIGNER_FILL_9_5 | output | TCELL83:OUT.21.TMIN |
| RX_LANE_ALIGNER_FILL_9_6 | output | TCELL83:OUT.25.TMIN |
| RX_MTYOUT0_0 | output | TCELL92:OUT.16.TMIN |
| RX_MTYOUT0_1 | output | TCELL93:OUT.16.TMIN |
| RX_MTYOUT0_2 | output | TCELL94:OUT.16.TMIN |
| RX_MTYOUT0_3 | output | TCELL95:OUT.16.TMIN |
| RX_MTYOUT1_0 | output | TCELL100:OUT.16.TMIN |
| RX_MTYOUT1_1 | output | TCELL101:OUT.16.TMIN |
| RX_MTYOUT1_2 | output | TCELL102:OUT.16.TMIN |
| RX_MTYOUT1_3 | output | TCELL103:OUT.16.TMIN |
| RX_MTYOUT2_0 | output | TCELL108:OUT.16.TMIN |
| RX_MTYOUT2_1 | output | TCELL109:OUT.16.TMIN |
| RX_MTYOUT2_2 | output | TCELL110:OUT.16.TMIN |
| RX_MTYOUT2_3 | output | TCELL111:OUT.16.TMIN |
| RX_MTYOUT3_0 | output | TCELL116:OUT.16.TMIN |
| RX_MTYOUT3_1 | output | TCELL117:OUT.16.TMIN |
| RX_MTYOUT3_2 | output | TCELL118:OUT.16.TMIN |
| RX_MTYOUT3_3 | output | TCELL119:OUT.16.TMIN |
| RX_PTP_PCSLANE_OUT0 | output | TCELL56:OUT.0.TMIN |
| RX_PTP_PCSLANE_OUT1 | output | TCELL56:OUT.2.TMIN |
| RX_PTP_PCSLANE_OUT2 | output | TCELL56:OUT.4.TMIN |
| RX_PTP_PCSLANE_OUT3 | output | TCELL56:OUT.6.TMIN |
| RX_PTP_PCSLANE_OUT4 | output | TCELL56:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT0 | output | TCELL55:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT1 | output | TCELL55:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT10 | output | TCELL54:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT11 | output | TCELL54:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT12 | output | TCELL54:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT13 | output | TCELL54:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT14 | output | TCELL54:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT15 | output | TCELL54:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT16 | output | TCELL53:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT17 | output | TCELL53:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT18 | output | TCELL53:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT19 | output | TCELL53:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT2 | output | TCELL55:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT20 | output | TCELL53:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT21 | output | TCELL53:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT22 | output | TCELL53:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT23 | output | TCELL53:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT24 | output | TCELL52:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT25 | output | TCELL52:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT26 | output | TCELL52:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT27 | output | TCELL52:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT28 | output | TCELL52:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT29 | output | TCELL52:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT3 | output | TCELL55:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT30 | output | TCELL52:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT31 | output | TCELL52:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT32 | output | TCELL51:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT33 | output | TCELL51:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT34 | output | TCELL51:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT35 | output | TCELL51:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT36 | output | TCELL51:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT37 | output | TCELL51:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT38 | output | TCELL51:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT39 | output | TCELL51:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT4 | output | TCELL55:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT40 | output | TCELL50:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT41 | output | TCELL50:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT42 | output | TCELL50:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT43 | output | TCELL50:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT44 | output | TCELL50:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT45 | output | TCELL50:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT46 | output | TCELL50:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT47 | output | TCELL50:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT48 | output | TCELL49:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT49 | output | TCELL49:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT5 | output | TCELL55:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT50 | output | TCELL49:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT51 | output | TCELL49:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT52 | output | TCELL49:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT53 | output | TCELL49:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT54 | output | TCELL49:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT55 | output | TCELL49:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT56 | output | TCELL48:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT57 | output | TCELL48:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT58 | output | TCELL48:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT59 | output | TCELL48:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT6 | output | TCELL55:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT60 | output | TCELL48:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT61 | output | TCELL48:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT62 | output | TCELL48:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT63 | output | TCELL48:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT64 | output | TCELL47:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT65 | output | TCELL47:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT66 | output | TCELL47:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT67 | output | TCELL47:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT68 | output | TCELL47:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT69 | output | TCELL47:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT7 | output | TCELL55:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT70 | output | TCELL47:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT71 | output | TCELL47:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT72 | output | TCELL46:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT73 | output | TCELL46:OUT.2.TMIN |
| RX_PTP_TSTAMP_OUT74 | output | TCELL46:OUT.4.TMIN |
| RX_PTP_TSTAMP_OUT75 | output | TCELL46:OUT.6.TMIN |
| RX_PTP_TSTAMP_OUT76 | output | TCELL46:OUT.8.TMIN |
| RX_PTP_TSTAMP_OUT77 | output | TCELL46:OUT.10.TMIN |
| RX_PTP_TSTAMP_OUT78 | output | TCELL46:OUT.12.TMIN |
| RX_PTP_TSTAMP_OUT79 | output | TCELL46:OUT.14.TMIN |
| RX_PTP_TSTAMP_OUT8 | output | TCELL54:OUT.0.TMIN |
| RX_PTP_TSTAMP_OUT9 | output | TCELL54:OUT.2.TMIN |
| RX_RESET | input | TCELL26:IMUX.IMUX.4.DELAY |
| RX_SERDES_ALT_DATA0_0 | input | TCELL5:IMUX.IMUX.1.DELAY |
| RX_SERDES_ALT_DATA0_1 | input | TCELL5:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA0_10 | input | TCELL10:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA0_11 | input | TCELL10:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA0_12 | input | TCELL11:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA0_13 | input | TCELL11:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA0_14 | input | TCELL12:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA0_15 | input | TCELL12:IMUX.IMUX.24.DELAY |
| RX_SERDES_ALT_DATA0_2 | input | TCELL6:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA0_3 | input | TCELL6:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA0_4 | input | TCELL7:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA0_5 | input | TCELL7:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA0_6 | input | TCELL8:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA0_7 | input | TCELL8:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA0_8 | input | TCELL9:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA0_9 | input | TCELL9:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA1_0 | input | TCELL18:IMUX.IMUX.1.DELAY |
| RX_SERDES_ALT_DATA1_1 | input | TCELL18:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA1_10 | input | TCELL23:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA1_11 | input | TCELL23:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA1_12 | input | TCELL24:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA1_13 | input | TCELL24:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA1_14 | input | TCELL25:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA1_15 | input | TCELL25:IMUX.IMUX.24.DELAY |
| RX_SERDES_ALT_DATA1_2 | input | TCELL19:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA1_3 | input | TCELL19:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA1_4 | input | TCELL20:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA1_5 | input | TCELL20:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA1_6 | input | TCELL21:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA1_7 | input | TCELL21:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA1_8 | input | TCELL22:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA1_9 | input | TCELL22:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA2_0 | input | TCELL31:IMUX.IMUX.1.DELAY |
| RX_SERDES_ALT_DATA2_1 | input | TCELL31:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA2_10 | input | TCELL36:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA2_11 | input | TCELL36:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA2_12 | input | TCELL37:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA2_13 | input | TCELL37:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA2_14 | input | TCELL38:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA2_15 | input | TCELL38:IMUX.IMUX.24.DELAY |
| RX_SERDES_ALT_DATA2_2 | input | TCELL32:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA2_3 | input | TCELL32:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA2_4 | input | TCELL33:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA2_5 | input | TCELL33:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA2_6 | input | TCELL34:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA2_7 | input | TCELL34:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA2_8 | input | TCELL35:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA2_9 | input | TCELL35:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA3_0 | input | TCELL44:IMUX.IMUX.1.DELAY |
| RX_SERDES_ALT_DATA3_1 | input | TCELL44:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA3_10 | input | TCELL49:IMUX.IMUX.15.DELAY |
| RX_SERDES_ALT_DATA3_11 | input | TCELL49:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA3_12 | input | TCELL50:IMUX.IMUX.18.DELAY |
| RX_SERDES_ALT_DATA3_13 | input | TCELL50:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA3_14 | input | TCELL51:IMUX.IMUX.21.DELAY |
| RX_SERDES_ALT_DATA3_15 | input | TCELL51:IMUX.IMUX.24.DELAY |
| RX_SERDES_ALT_DATA3_2 | input | TCELL45:IMUX.IMUX.3.DELAY |
| RX_SERDES_ALT_DATA3_3 | input | TCELL45:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA3_4 | input | TCELL46:IMUX.IMUX.6.DELAY |
| RX_SERDES_ALT_DATA3_5 | input | TCELL46:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA3_6 | input | TCELL47:IMUX.IMUX.9.DELAY |
| RX_SERDES_ALT_DATA3_7 | input | TCELL47:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA3_8 | input | TCELL48:IMUX.IMUX.12.DELAY |
| RX_SERDES_ALT_DATA3_9 | input | TCELL48:IMUX.IMUX.15.DELAY |
| RX_SERDES_CLK_B0 | input | TCELL29:IMUX.CTRL.3 |
| RX_SERDES_CLK_B1 | input | TCELL29:IMUX.CTRL.2 |
| RX_SERDES_CLK_B2 | input | TCELL28:IMUX.CTRL.3 |
| RX_SERDES_CLK_B3 | input | TCELL28:IMUX.CTRL.2 |
| RX_SERDES_CLK_B4 | input | TCELL27:IMUX.CTRL.3 |
| RX_SERDES_CLK_B5 | input | TCELL27:IMUX.CTRL.2 |
| RX_SERDES_CLK_B6 | input | TCELL31:IMUX.CTRL.3 |
| RX_SERDES_CLK_B7 | input | TCELL31:IMUX.CTRL.2 |
| RX_SERDES_CLK_B8 | input | TCELL32:IMUX.CTRL.3 |
| RX_SERDES_CLK_B9 | input | TCELL32:IMUX.CTRL.2 |
| RX_SERDES_DATA0_0 | input | TCELL4:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_1 | input | TCELL4:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_10 | input | TCELL5:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_11 | input | TCELL5:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_12 | input | TCELL5:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_13 | input | TCELL5:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_14 | input | TCELL5:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_15 | input | TCELL6:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_16 | input | TCELL6:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_17 | input | TCELL6:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_18 | input | TCELL6:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_19 | input | TCELL6:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_2 | input | TCELL4:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_20 | input | TCELL6:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_21 | input | TCELL6:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_22 | input | TCELL7:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_23 | input | TCELL7:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_24 | input | TCELL7:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_25 | input | TCELL7:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_26 | input | TCELL7:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_27 | input | TCELL7:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_28 | input | TCELL7:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_29 | input | TCELL8:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_3 | input | TCELL4:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_30 | input | TCELL8:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_31 | input | TCELL8:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_32 | input | TCELL8:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_33 | input | TCELL8:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_34 | input | TCELL8:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_35 | input | TCELL8:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_36 | input | TCELL9:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_37 | input | TCELL9:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_38 | input | TCELL9:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_39 | input | TCELL9:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_4 | input | TCELL4:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_40 | input | TCELL9:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_41 | input | TCELL9:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_42 | input | TCELL9:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_43 | input | TCELL10:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_44 | input | TCELL10:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_45 | input | TCELL10:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_46 | input | TCELL10:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_47 | input | TCELL10:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_48 | input | TCELL10:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_49 | input | TCELL10:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_5 | input | TCELL4:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_50 | input | TCELL11:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_51 | input | TCELL11:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_52 | input | TCELL11:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_53 | input | TCELL11:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_54 | input | TCELL11:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_55 | input | TCELL11:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_56 | input | TCELL11:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA0_57 | input | TCELL12:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA0_58 | input | TCELL12:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA0_59 | input | TCELL12:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_6 | input | TCELL4:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_60 | input | TCELL12:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA0_61 | input | TCELL12:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA0_62 | input | TCELL12:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA0_63 | input | TCELL12:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA0_7 | input | TCELL4:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA0_8 | input | TCELL5:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA0_9 | input | TCELL5:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_0 | input | TCELL17:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_1 | input | TCELL17:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_10 | input | TCELL18:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_11 | input | TCELL18:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_12 | input | TCELL18:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_13 | input | TCELL18:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_14 | input | TCELL18:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_15 | input | TCELL19:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_16 | input | TCELL19:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_17 | input | TCELL19:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_18 | input | TCELL19:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_19 | input | TCELL19:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_2 | input | TCELL17:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_20 | input | TCELL19:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_21 | input | TCELL19:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_22 | input | TCELL20:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_23 | input | TCELL20:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_24 | input | TCELL20:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_25 | input | TCELL20:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_26 | input | TCELL20:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_27 | input | TCELL20:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_28 | input | TCELL20:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_29 | input | TCELL21:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_3 | input | TCELL17:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_30 | input | TCELL21:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_31 | input | TCELL21:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_32 | input | TCELL21:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_33 | input | TCELL21:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_34 | input | TCELL21:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_35 | input | TCELL21:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_36 | input | TCELL22:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_37 | input | TCELL22:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_38 | input | TCELL22:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_39 | input | TCELL22:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_4 | input | TCELL17:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_40 | input | TCELL22:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_41 | input | TCELL22:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_42 | input | TCELL22:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_43 | input | TCELL23:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_44 | input | TCELL23:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_45 | input | TCELL23:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_46 | input | TCELL23:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_47 | input | TCELL23:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_48 | input | TCELL23:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_49 | input | TCELL23:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_5 | input | TCELL17:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_50 | input | TCELL24:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_51 | input | TCELL24:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_52 | input | TCELL24:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_53 | input | TCELL24:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_54 | input | TCELL24:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_55 | input | TCELL24:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_56 | input | TCELL24:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA1_57 | input | TCELL25:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA1_58 | input | TCELL25:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA1_59 | input | TCELL25:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_6 | input | TCELL17:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_60 | input | TCELL25:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA1_61 | input | TCELL25:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA1_62 | input | TCELL25:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA1_63 | input | TCELL25:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA1_7 | input | TCELL17:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA1_8 | input | TCELL18:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA1_9 | input | TCELL18:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_0 | input | TCELL30:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_1 | input | TCELL30:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_10 | input | TCELL31:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_11 | input | TCELL31:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_12 | input | TCELL31:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_13 | input | TCELL31:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_14 | input | TCELL31:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_15 | input | TCELL32:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_16 | input | TCELL32:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_17 | input | TCELL32:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_18 | input | TCELL32:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_19 | input | TCELL32:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_2 | input | TCELL30:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_20 | input | TCELL32:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_21 | input | TCELL32:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_22 | input | TCELL33:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_23 | input | TCELL33:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_24 | input | TCELL33:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_25 | input | TCELL33:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_26 | input | TCELL33:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_27 | input | TCELL33:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_28 | input | TCELL33:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_29 | input | TCELL34:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_3 | input | TCELL30:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_30 | input | TCELL34:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_31 | input | TCELL34:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_32 | input | TCELL34:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_33 | input | TCELL34:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_34 | input | TCELL34:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_35 | input | TCELL34:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_36 | input | TCELL35:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_37 | input | TCELL35:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_38 | input | TCELL35:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_39 | input | TCELL35:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_4 | input | TCELL30:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_40 | input | TCELL35:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_41 | input | TCELL35:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_42 | input | TCELL35:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_43 | input | TCELL36:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_44 | input | TCELL36:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_45 | input | TCELL36:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_46 | input | TCELL36:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_47 | input | TCELL36:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_48 | input | TCELL36:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_49 | input | TCELL36:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_5 | input | TCELL30:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_50 | input | TCELL37:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_51 | input | TCELL37:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_52 | input | TCELL37:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_53 | input | TCELL37:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_54 | input | TCELL37:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_55 | input | TCELL37:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_56 | input | TCELL37:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA2_57 | input | TCELL38:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA2_58 | input | TCELL38:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA2_59 | input | TCELL38:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_6 | input | TCELL30:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_60 | input | TCELL38:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA2_61 | input | TCELL38:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA2_62 | input | TCELL38:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA2_63 | input | TCELL38:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA2_7 | input | TCELL30:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA2_8 | input | TCELL31:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA2_9 | input | TCELL31:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_0 | input | TCELL43:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_1 | input | TCELL43:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_10 | input | TCELL44:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_11 | input | TCELL44:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_12 | input | TCELL44:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_13 | input | TCELL44:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_14 | input | TCELL44:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_15 | input | TCELL45:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_16 | input | TCELL45:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_17 | input | TCELL45:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_18 | input | TCELL45:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_19 | input | TCELL45:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_2 | input | TCELL43:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_20 | input | TCELL45:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_21 | input | TCELL45:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_22 | input | TCELL46:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_23 | input | TCELL46:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_24 | input | TCELL46:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_25 | input | TCELL46:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_26 | input | TCELL46:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_27 | input | TCELL46:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_28 | input | TCELL46:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_29 | input | TCELL47:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_3 | input | TCELL43:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_30 | input | TCELL47:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_31 | input | TCELL47:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_32 | input | TCELL47:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_33 | input | TCELL47:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_34 | input | TCELL47:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_35 | input | TCELL47:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_36 | input | TCELL48:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_37 | input | TCELL48:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_38 | input | TCELL48:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_39 | input | TCELL48:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_4 | input | TCELL43:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_40 | input | TCELL48:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_41 | input | TCELL48:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_42 | input | TCELL48:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_43 | input | TCELL49:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_44 | input | TCELL49:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_45 | input | TCELL49:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_46 | input | TCELL49:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_47 | input | TCELL49:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_48 | input | TCELL49:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_49 | input | TCELL49:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_5 | input | TCELL43:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_50 | input | TCELL50:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_51 | input | TCELL50:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_52 | input | TCELL50:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_53 | input | TCELL50:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_54 | input | TCELL50:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_55 | input | TCELL50:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_56 | input | TCELL50:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA3_57 | input | TCELL51:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA3_58 | input | TCELL51:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA3_59 | input | TCELL51:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_6 | input | TCELL43:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_60 | input | TCELL51:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA3_61 | input | TCELL51:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA3_62 | input | TCELL51:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA3_63 | input | TCELL51:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA3_7 | input | TCELL43:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA3_8 | input | TCELL44:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA3_9 | input | TCELL44:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA4_0 | input | TCELL0:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA4_1 | input | TCELL0:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA4_10 | input | TCELL1:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA4_11 | input | TCELL1:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA4_12 | input | TCELL1:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA4_13 | input | TCELL1:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA4_14 | input | TCELL1:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA4_15 | input | TCELL1:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA4_16 | input | TCELL2:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA4_17 | input | TCELL2:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA4_18 | input | TCELL2:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA4_19 | input | TCELL2:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA4_2 | input | TCELL0:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA4_20 | input | TCELL2:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA4_21 | input | TCELL2:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA4_22 | input | TCELL2:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA4_23 | input | TCELL2:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA4_24 | input | TCELL3:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA4_25 | input | TCELL3:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA4_26 | input | TCELL3:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA4_27 | input | TCELL3:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA4_28 | input | TCELL3:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA4_29 | input | TCELL3:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA4_3 | input | TCELL0:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA4_30 | input | TCELL3:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA4_31 | input | TCELL3:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA4_4 | input | TCELL0:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA4_5 | input | TCELL0:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA4_6 | input | TCELL0:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA4_7 | input | TCELL0:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA4_8 | input | TCELL1:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA4_9 | input | TCELL1:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA5_0 | input | TCELL13:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA5_1 | input | TCELL13:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA5_10 | input | TCELL14:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA5_11 | input | TCELL14:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA5_12 | input | TCELL14:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA5_13 | input | TCELL14:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA5_14 | input | TCELL14:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA5_15 | input | TCELL14:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA5_16 | input | TCELL15:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA5_17 | input | TCELL15:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA5_18 | input | TCELL15:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA5_19 | input | TCELL15:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA5_2 | input | TCELL13:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA5_20 | input | TCELL15:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA5_21 | input | TCELL15:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA5_22 | input | TCELL15:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA5_23 | input | TCELL15:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA5_24 | input | TCELL16:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA5_25 | input | TCELL16:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA5_26 | input | TCELL16:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA5_27 | input | TCELL16:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA5_28 | input | TCELL16:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA5_29 | input | TCELL16:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA5_3 | input | TCELL13:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA5_30 | input | TCELL16:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA5_31 | input | TCELL16:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA5_4 | input | TCELL13:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA5_5 | input | TCELL13:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA5_6 | input | TCELL13:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA5_7 | input | TCELL13:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA5_8 | input | TCELL14:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA5_9 | input | TCELL14:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA6_0 | input | TCELL26:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA6_1 | input | TCELL26:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA6_10 | input | TCELL27:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA6_11 | input | TCELL27:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA6_12 | input | TCELL27:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA6_13 | input | TCELL27:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA6_14 | input | TCELL27:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA6_15 | input | TCELL27:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA6_16 | input | TCELL28:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA6_17 | input | TCELL28:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA6_18 | input | TCELL28:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA6_19 | input | TCELL28:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA6_2 | input | TCELL26:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA6_20 | input | TCELL28:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA6_21 | input | TCELL28:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA6_22 | input | TCELL28:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA6_23 | input | TCELL28:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA6_24 | input | TCELL29:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA6_25 | input | TCELL29:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA6_26 | input | TCELL29:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA6_27 | input | TCELL29:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA6_28 | input | TCELL29:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA6_29 | input | TCELL29:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA6_3 | input | TCELL26:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA6_30 | input | TCELL29:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA6_31 | input | TCELL29:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA6_4 | input | TCELL26:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA6_5 | input | TCELL26:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA6_6 | input | TCELL26:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA6_7 | input | TCELL26:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA6_8 | input | TCELL27:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA6_9 | input | TCELL27:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA7_0 | input | TCELL39:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA7_1 | input | TCELL39:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA7_10 | input | TCELL40:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA7_11 | input | TCELL40:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA7_12 | input | TCELL40:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA7_13 | input | TCELL40:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA7_14 | input | TCELL40:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA7_15 | input | TCELL40:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA7_16 | input | TCELL41:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA7_17 | input | TCELL41:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA7_18 | input | TCELL41:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA7_19 | input | TCELL41:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA7_2 | input | TCELL39:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA7_20 | input | TCELL41:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA7_21 | input | TCELL41:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA7_22 | input | TCELL41:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA7_23 | input | TCELL41:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA7_24 | input | TCELL42:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA7_25 | input | TCELL42:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA7_26 | input | TCELL42:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA7_27 | input | TCELL42:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA7_28 | input | TCELL42:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA7_29 | input | TCELL42:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA7_3 | input | TCELL39:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA7_30 | input | TCELL42:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA7_31 | input | TCELL42:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA7_4 | input | TCELL39:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA7_5 | input | TCELL39:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA7_6 | input | TCELL39:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA7_7 | input | TCELL39:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA7_8 | input | TCELL40:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA7_9 | input | TCELL40:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA8_0 | input | TCELL52:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA8_1 | input | TCELL52:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA8_10 | input | TCELL53:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA8_11 | input | TCELL53:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA8_12 | input | TCELL53:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA8_13 | input | TCELL53:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA8_14 | input | TCELL53:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA8_15 | input | TCELL53:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA8_16 | input | TCELL54:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA8_17 | input | TCELL54:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA8_18 | input | TCELL54:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA8_19 | input | TCELL54:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA8_2 | input | TCELL52:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA8_20 | input | TCELL54:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA8_21 | input | TCELL54:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA8_22 | input | TCELL54:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA8_23 | input | TCELL54:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA8_24 | input | TCELL55:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA8_25 | input | TCELL55:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA8_26 | input | TCELL55:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA8_27 | input | TCELL55:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA8_28 | input | TCELL55:IMUX.IMUX.15.DELAY |
| RX_SERDES_DATA8_29 | input | TCELL55:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA8_3 | input | TCELL52:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA8_30 | input | TCELL55:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA8_31 | input | TCELL55:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA8_4 | input | TCELL52:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA8_5 | input | TCELL52:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA8_6 | input | TCELL52:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA8_7 | input | TCELL52:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA8_8 | input | TCELL53:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA8_9 | input | TCELL53:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA9_0 | input | TCELL56:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA9_1 | input | TCELL57:IMUX.IMUX.46.DELAY |
| RX_SERDES_DATA9_10 | input | TCELL57:IMUX.IMUX.33.DELAY |
| RX_SERDES_DATA9_11 | input | TCELL57:IMUX.IMUX.42.DELAY |
| RX_SERDES_DATA9_12 | input | TCELL57:IMUX.IMUX.14.DELAY |
| RX_SERDES_DATA9_13 | input | TCELL57:IMUX.IMUX.19.DELAY |
| RX_SERDES_DATA9_14 | input | TCELL59:IMUX.IMUX.43.DELAY |
| RX_SERDES_DATA9_15 | input | TCELL57:IMUX.IMUX.39.DELAY |
| RX_SERDES_DATA9_16 | input | TCELL58:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA9_17 | input | TCELL57:IMUX.IMUX.29.DELAY |
| RX_SERDES_DATA9_18 | input | TCELL57:IMUX.IMUX.7.DELAY |
| RX_SERDES_DATA9_19 | input | TCELL59:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA9_2 | input | TCELL57:IMUX.IMUX.28.DELAY |
| RX_SERDES_DATA9_20 | input | TCELL58:IMUX.IMUX.18.DELAY |
| RX_SERDES_DATA9_21 | input | TCELL58:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA9_22 | input | TCELL59:IMUX.IMUX.21.DELAY |
| RX_SERDES_DATA9_23 | input | TCELL58:IMUX.IMUX.1.DELAY |
| RX_SERDES_DATA9_24 | input | TCELL59:IMUX.IMUX.3.DELAY |
| RX_SERDES_DATA9_25 | input | TCELL57:IMUX.IMUX.40.DELAY |
| RX_SERDES_DATA9_26 | input | TCELL59:IMUX.IMUX.9.DELAY |
| RX_SERDES_DATA9_27 | input | TCELL59:IMUX.IMUX.12.DELAY |
| RX_SERDES_DATA9_28 | input | TCELL57:IMUX.IMUX.25.DELAY |
| RX_SERDES_DATA9_29 | input | TCELL56:IMUX.IMUX.42.DELAY |
| RX_SERDES_DATA9_3 | input | TCELL57:IMUX.IMUX.23.DELAY |
| RX_SERDES_DATA9_30 | input | TCELL57:IMUX.IMUX.35.DELAY |
| RX_SERDES_DATA9_31 | input | TCELL59:IMUX.IMUX.24.DELAY |
| RX_SERDES_DATA9_4 | input | TCELL57:IMUX.IMUX.20.DELAY |
| RX_SERDES_DATA9_5 | input | TCELL57:IMUX.IMUX.0.DELAY |
| RX_SERDES_DATA9_6 | input | TCELL57:IMUX.IMUX.43.DELAY |
| RX_SERDES_DATA9_7 | input | TCELL56:IMUX.IMUX.6.DELAY |
| RX_SERDES_DATA9_8 | input | TCELL57:IMUX.IMUX.8.DELAY |
| RX_SERDES_DATA9_9 | input | TCELL57:IMUX.IMUX.17.DELAY |
| RX_SERDES_RESET0 | input | TCELL34:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET1 | input | TCELL33:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET2 | input | TCELL32:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET3 | input | TCELL31:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET4 | input | TCELL30:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET5 | input | TCELL29:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET6 | input | TCELL28:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET7 | input | TCELL27:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET8 | input | TCELL26:IMUX.IMUX.2.DELAY |
| RX_SERDES_RESET9 | input | TCELL25:IMUX.IMUX.2.DELAY |
| RX_SOPOUT0 | output | TCELL90:OUT.16.TMIN |
| RX_SOPOUT1 | output | TCELL98:OUT.16.TMIN |
| RX_SOPOUT2 | output | TCELL106:OUT.16.TMIN |
| RX_SOPOUT3 | output | TCELL114:OUT.16.TMIN |
| SCAN_EN_N | input | TCELL33:IMUX.CTRL.2 |
| SCAN_IN_CMAC0 | input | TCELL0:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC1 | input | TCELL1:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC10 | input | TCELL10:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC100 | input | TCELL44:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC101 | input | TCELL45:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC102 | input | TCELL46:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC103 | input | TCELL47:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC104 | input | TCELL48:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC105 | input | TCELL49:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC106 | input | TCELL50:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC107 | input | TCELL51:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC108 | input | TCELL52:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC109 | input | TCELL53:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC11 | input | TCELL11:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC110 | input | TCELL54:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC111 | input | TCELL55:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC112 | input | TCELL0:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC113 | input | TCELL1:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC114 | input | TCELL2:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC115 | input | TCELL3:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC116 | input | TCELL4:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC117 | input | TCELL5:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC118 | input | TCELL6:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC119 | input | TCELL7:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC12 | input | TCELL12:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC120 | input | TCELL8:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC121 | input | TCELL9:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC122 | input | TCELL10:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC123 | input | TCELL11:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC124 | input | TCELL12:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC125 | input | TCELL13:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC126 | input | TCELL14:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC127 | input | TCELL15:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC128 | input | TCELL16:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC129 | input | TCELL17:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC13 | input | TCELL13:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC130 | input | TCELL18:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC131 | input | TCELL19:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC132 | input | TCELL20:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC133 | input | TCELL21:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC134 | input | TCELL22:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC135 | input | TCELL23:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC136 | input | TCELL24:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC137 | input | TCELL25:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC138 | input | TCELL26:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC139 | input | TCELL27:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC14 | input | TCELL14:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC140 | input | TCELL28:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC141 | input | TCELL29:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC142 | input | TCELL30:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC143 | input | TCELL31:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC144 | input | TCELL32:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC145 | input | TCELL33:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC146 | input | TCELL34:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC147 | input | TCELL35:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC148 | input | TCELL36:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC149 | input | TCELL37:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC15 | input | TCELL15:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC150 | input | TCELL38:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC151 | input | TCELL39:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC152 | input | TCELL40:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC153 | input | TCELL41:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC154 | input | TCELL42:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC155 | input | TCELL43:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC156 | input | TCELL44:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC157 | input | TCELL45:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC158 | input | TCELL46:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC159 | input | TCELL47:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC16 | input | TCELL16:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC160 | input | TCELL48:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC161 | input | TCELL49:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC162 | input | TCELL50:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC163 | input | TCELL51:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC164 | input | TCELL52:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC165 | input | TCELL53:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC166 | input | TCELL54:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC167 | input | TCELL55:IMUX.IMUX.30.DELAY |
| SCAN_IN_CMAC168 | input | TCELL0:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC169 | input | TCELL1:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC17 | input | TCELL17:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC170 | input | TCELL2:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC171 | input | TCELL3:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC172 | input | TCELL4:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC173 | input | TCELL5:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC174 | input | TCELL6:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC175 | input | TCELL7:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC176 | input | TCELL8:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC177 | input | TCELL9:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC178 | input | TCELL10:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC179 | input | TCELL11:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC18 | input | TCELL18:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC180 | input | TCELL12:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC181 | input | TCELL13:IMUX.IMUX.46.DELAY |
| SCAN_IN_CMAC19 | input | TCELL19:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC2 | input | TCELL2:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC20 | input | TCELL20:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC21 | input | TCELL21:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC22 | input | TCELL22:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC23 | input | TCELL23:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC24 | input | TCELL24:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC25 | input | TCELL25:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC26 | input | TCELL26:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC27 | input | TCELL27:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC28 | input | TCELL28:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC29 | input | TCELL29:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC3 | input | TCELL3:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC30 | input | TCELL30:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC31 | input | TCELL31:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC32 | input | TCELL32:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC33 | input | TCELL33:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC34 | input | TCELL34:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC35 | input | TCELL35:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC36 | input | TCELL36:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC37 | input | TCELL37:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC38 | input | TCELL38:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC39 | input | TCELL39:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC4 | input | TCELL4:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC40 | input | TCELL40:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC41 | input | TCELL41:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC42 | input | TCELL42:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC43 | input | TCELL43:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC44 | input | TCELL44:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC45 | input | TCELL45:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC46 | input | TCELL46:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC47 | input | TCELL47:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC48 | input | TCELL48:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC49 | input | TCELL49:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC5 | input | TCELL5:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC50 | input | TCELL50:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC51 | input | TCELL51:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC52 | input | TCELL52:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC53 | input | TCELL53:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC54 | input | TCELL54:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC55 | input | TCELL55:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC56 | input | TCELL0:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC57 | input | TCELL1:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC58 | input | TCELL2:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC59 | input | TCELL3:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC6 | input | TCELL6:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC60 | input | TCELL4:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC61 | input | TCELL5:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC62 | input | TCELL6:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC63 | input | TCELL7:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC64 | input | TCELL8:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC65 | input | TCELL9:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC66 | input | TCELL10:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC67 | input | TCELL11:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC68 | input | TCELL12:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC69 | input | TCELL13:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC7 | input | TCELL7:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC70 | input | TCELL14:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC71 | input | TCELL15:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC72 | input | TCELL16:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC73 | input | TCELL17:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC74 | input | TCELL18:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC75 | input | TCELL19:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC76 | input | TCELL20:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC77 | input | TCELL21:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC78 | input | TCELL22:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC79 | input | TCELL23:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC8 | input | TCELL8:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC80 | input | TCELL24:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC81 | input | TCELL25:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC82 | input | TCELL26:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC83 | input | TCELL27:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC84 | input | TCELL28:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC85 | input | TCELL29:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC86 | input | TCELL30:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC87 | input | TCELL31:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC88 | input | TCELL32:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC89 | input | TCELL33:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC9 | input | TCELL9:IMUX.IMUX.0.DELAY |
| SCAN_IN_CMAC90 | input | TCELL34:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC91 | input | TCELL35:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC92 | input | TCELL36:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC93 | input | TCELL37:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC94 | input | TCELL38:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC95 | input | TCELL39:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC96 | input | TCELL40:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC97 | input | TCELL41:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC98 | input | TCELL42:IMUX.IMUX.16.DELAY |
| SCAN_IN_CMAC99 | input | TCELL43:IMUX.IMUX.16.DELAY |
| SCAN_IN_DRPCTRL0 | input | TCELL14:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL1 | input | TCELL15:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL10 | input | TCELL24:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL11 | input | TCELL25:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL12 | input | TCELL26:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL2 | input | TCELL16:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL3 | input | TCELL17:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL4 | input | TCELL18:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL5 | input | TCELL19:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL6 | input | TCELL20:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL7 | input | TCELL21:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL8 | input | TCELL22:IMUX.IMUX.46.DELAY |
| SCAN_IN_DRPCTRL9 | input | TCELL23:IMUX.IMUX.46.DELAY |
| SCAN_OUT_CMAC0 | output | TCELL60:OUT.28.TMIN |
| SCAN_OUT_CMAC1 | output | TCELL60:OUT.2.TMIN |
| SCAN_OUT_CMAC10 | output | TCELL65:OUT.28.TMIN |
| SCAN_OUT_CMAC100 | output | TCELL59:OUT.28.TMIN |
| SCAN_OUT_CMAC101 | output | TCELL58:OUT.28.TMIN |
| SCAN_OUT_CMAC102 | output | TCELL57:OUT.28.TMIN |
| SCAN_OUT_CMAC103 | output | TCELL56:OUT.28.TMIN |
| SCAN_OUT_CMAC104 | output | TCELL55:OUT.28.TMIN |
| SCAN_OUT_CMAC105 | output | TCELL54:OUT.28.TMIN |
| SCAN_OUT_CMAC106 | output | TCELL53:OUT.28.TMIN |
| SCAN_OUT_CMAC107 | output | TCELL52:OUT.28.TMIN |
| SCAN_OUT_CMAC108 | output | TCELL51:OUT.28.TMIN |
| SCAN_OUT_CMAC109 | output | TCELL50:OUT.28.TMIN |
| SCAN_OUT_CMAC11 | output | TCELL65:OUT.2.TMIN |
| SCAN_OUT_CMAC110 | output | TCELL49:OUT.28.TMIN |
| SCAN_OUT_CMAC111 | output | TCELL48:OUT.28.TMIN |
| SCAN_OUT_CMAC112 | output | TCELL47:OUT.28.TMIN |
| SCAN_OUT_CMAC113 | output | TCELL46:OUT.28.TMIN |
| SCAN_OUT_CMAC114 | output | TCELL45:OUT.28.TMIN |
| SCAN_OUT_CMAC115 | output | TCELL44:OUT.28.TMIN |
| SCAN_OUT_CMAC116 | output | TCELL43:OUT.28.TMIN |
| SCAN_OUT_CMAC117 | output | TCELL42:OUT.28.TMIN |
| SCAN_OUT_CMAC118 | output | TCELL41:OUT.28.TMIN |
| SCAN_OUT_CMAC119 | output | TCELL40:OUT.28.TMIN |
| SCAN_OUT_CMAC12 | output | TCELL66:OUT.28.TMIN |
| SCAN_OUT_CMAC120 | output | TCELL39:OUT.28.TMIN |
| SCAN_OUT_CMAC121 | output | TCELL38:OUT.28.TMIN |
| SCAN_OUT_CMAC122 | output | TCELL37:OUT.28.TMIN |
| SCAN_OUT_CMAC123 | output | TCELL36:OUT.28.TMIN |
| SCAN_OUT_CMAC124 | output | TCELL35:OUT.28.TMIN |
| SCAN_OUT_CMAC125 | output | TCELL34:OUT.28.TMIN |
| SCAN_OUT_CMAC126 | output | TCELL33:OUT.28.TMIN |
| SCAN_OUT_CMAC127 | output | TCELL32:OUT.28.TMIN |
| SCAN_OUT_CMAC128 | output | TCELL31:OUT.28.TMIN |
| SCAN_OUT_CMAC129 | output | TCELL30:OUT.28.TMIN |
| SCAN_OUT_CMAC13 | output | TCELL66:OUT.2.TMIN |
| SCAN_OUT_CMAC130 | output | TCELL29:OUT.28.TMIN |
| SCAN_OUT_CMAC131 | output | TCELL28:OUT.28.TMIN |
| SCAN_OUT_CMAC132 | output | TCELL27:OUT.28.TMIN |
| SCAN_OUT_CMAC133 | output | TCELL26:OUT.28.TMIN |
| SCAN_OUT_CMAC134 | output | TCELL25:OUT.28.TMIN |
| SCAN_OUT_CMAC135 | output | TCELL24:OUT.28.TMIN |
| SCAN_OUT_CMAC136 | output | TCELL23:OUT.28.TMIN |
| SCAN_OUT_CMAC137 | output | TCELL22:OUT.28.TMIN |
| SCAN_OUT_CMAC138 | output | TCELL21:OUT.28.TMIN |
| SCAN_OUT_CMAC139 | output | TCELL20:OUT.28.TMIN |
| SCAN_OUT_CMAC14 | output | TCELL67:OUT.28.TMIN |
| SCAN_OUT_CMAC140 | output | TCELL19:OUT.28.TMIN |
| SCAN_OUT_CMAC141 | output | TCELL18:OUT.28.TMIN |
| SCAN_OUT_CMAC142 | output | TCELL17:OUT.28.TMIN |
| SCAN_OUT_CMAC143 | output | TCELL16:OUT.28.TMIN |
| SCAN_OUT_CMAC144 | output | TCELL15:OUT.28.TMIN |
| SCAN_OUT_CMAC145 | output | TCELL14:OUT.28.TMIN |
| SCAN_OUT_CMAC146 | output | TCELL13:OUT.28.TMIN |
| SCAN_OUT_CMAC147 | output | TCELL12:OUT.28.TMIN |
| SCAN_OUT_CMAC148 | output | TCELL11:OUT.28.TMIN |
| SCAN_OUT_CMAC149 | output | TCELL10:OUT.28.TMIN |
| SCAN_OUT_CMAC15 | output | TCELL67:OUT.2.TMIN |
| SCAN_OUT_CMAC150 | output | TCELL9:OUT.28.TMIN |
| SCAN_OUT_CMAC151 | output | TCELL8:OUT.28.TMIN |
| SCAN_OUT_CMAC152 | output | TCELL7:OUT.28.TMIN |
| SCAN_OUT_CMAC153 | output | TCELL6:OUT.28.TMIN |
| SCAN_OUT_CMAC154 | output | TCELL5:OUT.28.TMIN |
| SCAN_OUT_CMAC155 | output | TCELL4:OUT.28.TMIN |
| SCAN_OUT_CMAC156 | output | TCELL3:OUT.28.TMIN |
| SCAN_OUT_CMAC157 | output | TCELL2:OUT.28.TMIN |
| SCAN_OUT_CMAC158 | output | TCELL1:OUT.28.TMIN |
| SCAN_OUT_CMAC159 | output | TCELL0:OUT.28.TMIN |
| SCAN_OUT_CMAC16 | output | TCELL68:OUT.28.TMIN |
| SCAN_OUT_CMAC160 | output | TCELL59:OUT.24.TMIN |
| SCAN_OUT_CMAC161 | output | TCELL58:OUT.24.TMIN |
| SCAN_OUT_CMAC162 | output | TCELL57:OUT.24.TMIN |
| SCAN_OUT_CMAC163 | output | TCELL56:OUT.24.TMIN |
| SCAN_OUT_CMAC164 | output | TCELL55:OUT.24.TMIN |
| SCAN_OUT_CMAC165 | output | TCELL54:OUT.24.TMIN |
| SCAN_OUT_CMAC166 | output | TCELL53:OUT.24.TMIN |
| SCAN_OUT_CMAC167 | output | TCELL52:OUT.24.TMIN |
| SCAN_OUT_CMAC168 | output | TCELL51:OUT.24.TMIN |
| SCAN_OUT_CMAC169 | output | TCELL50:OUT.24.TMIN |
| SCAN_OUT_CMAC17 | output | TCELL68:OUT.2.TMIN |
| SCAN_OUT_CMAC170 | output | TCELL49:OUT.24.TMIN |
| SCAN_OUT_CMAC171 | output | TCELL48:OUT.24.TMIN |
| SCAN_OUT_CMAC172 | output | TCELL47:OUT.24.TMIN |
| SCAN_OUT_CMAC173 | output | TCELL46:OUT.24.TMIN |
| SCAN_OUT_CMAC174 | output | TCELL45:OUT.24.TMIN |
| SCAN_OUT_CMAC175 | output | TCELL44:OUT.24.TMIN |
| SCAN_OUT_CMAC176 | output | TCELL43:OUT.24.TMIN |
| SCAN_OUT_CMAC177 | output | TCELL42:OUT.24.TMIN |
| SCAN_OUT_CMAC178 | output | TCELL41:OUT.24.TMIN |
| SCAN_OUT_CMAC179 | output | TCELL40:OUT.24.TMIN |
| SCAN_OUT_CMAC18 | output | TCELL69:OUT.28.TMIN |
| SCAN_OUT_CMAC180 | output | TCELL39:OUT.24.TMIN |
| SCAN_OUT_CMAC181 | output | TCELL38:OUT.24.TMIN |
| SCAN_OUT_CMAC19 | output | TCELL69:OUT.2.TMIN |
| SCAN_OUT_CMAC2 | output | TCELL61:OUT.28.TMIN |
| SCAN_OUT_CMAC20 | output | TCELL70:OUT.28.TMIN |
| SCAN_OUT_CMAC21 | output | TCELL70:OUT.2.TMIN |
| SCAN_OUT_CMAC22 | output | TCELL71:OUT.28.TMIN |
| SCAN_OUT_CMAC23 | output | TCELL71:OUT.2.TMIN |
| SCAN_OUT_CMAC24 | output | TCELL72:OUT.28.TMIN |
| SCAN_OUT_CMAC25 | output | TCELL72:OUT.2.TMIN |
| SCAN_OUT_CMAC26 | output | TCELL73:OUT.28.TMIN |
| SCAN_OUT_CMAC27 | output | TCELL73:OUT.2.TMIN |
| SCAN_OUT_CMAC28 | output | TCELL74:OUT.28.TMIN |
| SCAN_OUT_CMAC29 | output | TCELL74:OUT.2.TMIN |
| SCAN_OUT_CMAC3 | output | TCELL61:OUT.2.TMIN |
| SCAN_OUT_CMAC30 | output | TCELL75:OUT.28.TMIN |
| SCAN_OUT_CMAC31 | output | TCELL75:OUT.2.TMIN |
| SCAN_OUT_CMAC32 | output | TCELL76:OUT.28.TMIN |
| SCAN_OUT_CMAC33 | output | TCELL76:OUT.2.TMIN |
| SCAN_OUT_CMAC34 | output | TCELL77:OUT.28.TMIN |
| SCAN_OUT_CMAC35 | output | TCELL77:OUT.2.TMIN |
| SCAN_OUT_CMAC36 | output | TCELL78:OUT.28.TMIN |
| SCAN_OUT_CMAC37 | output | TCELL78:OUT.2.TMIN |
| SCAN_OUT_CMAC38 | output | TCELL79:OUT.28.TMIN |
| SCAN_OUT_CMAC39 | output | TCELL79:OUT.2.TMIN |
| SCAN_OUT_CMAC4 | output | TCELL62:OUT.28.TMIN |
| SCAN_OUT_CMAC40 | output | TCELL80:OUT.28.TMIN |
| SCAN_OUT_CMAC41 | output | TCELL80:OUT.2.TMIN |
| SCAN_OUT_CMAC42 | output | TCELL81:OUT.28.TMIN |
| SCAN_OUT_CMAC43 | output | TCELL81:OUT.2.TMIN |
| SCAN_OUT_CMAC44 | output | TCELL82:OUT.28.TMIN |
| SCAN_OUT_CMAC45 | output | TCELL82:OUT.2.TMIN |
| SCAN_OUT_CMAC46 | output | TCELL83:OUT.28.TMIN |
| SCAN_OUT_CMAC47 | output | TCELL83:OUT.2.TMIN |
| SCAN_OUT_CMAC48 | output | TCELL84:OUT.28.TMIN |
| SCAN_OUT_CMAC49 | output | TCELL84:OUT.2.TMIN |
| SCAN_OUT_CMAC5 | output | TCELL62:OUT.2.TMIN |
| SCAN_OUT_CMAC50 | output | TCELL85:OUT.28.TMIN |
| SCAN_OUT_CMAC51 | output | TCELL85:OUT.2.TMIN |
| SCAN_OUT_CMAC52 | output | TCELL86:OUT.28.TMIN |
| SCAN_OUT_CMAC53 | output | TCELL86:OUT.2.TMIN |
| SCAN_OUT_CMAC54 | output | TCELL87:OUT.28.TMIN |
| SCAN_OUT_CMAC55 | output | TCELL87:OUT.2.TMIN |
| SCAN_OUT_CMAC56 | output | TCELL88:OUT.28.TMIN |
| SCAN_OUT_CMAC57 | output | TCELL88:OUT.2.TMIN |
| SCAN_OUT_CMAC58 | output | TCELL89:OUT.28.TMIN |
| SCAN_OUT_CMAC59 | output | TCELL89:OUT.2.TMIN |
| SCAN_OUT_CMAC6 | output | TCELL63:OUT.28.TMIN |
| SCAN_OUT_CMAC60 | output | TCELL90:OUT.28.TMIN |
| SCAN_OUT_CMAC61 | output | TCELL90:OUT.2.TMIN |
| SCAN_OUT_CMAC62 | output | TCELL91:OUT.28.TMIN |
| SCAN_OUT_CMAC63 | output | TCELL91:OUT.2.TMIN |
| SCAN_OUT_CMAC64 | output | TCELL92:OUT.28.TMIN |
| SCAN_OUT_CMAC65 | output | TCELL92:OUT.2.TMIN |
| SCAN_OUT_CMAC66 | output | TCELL93:OUT.28.TMIN |
| SCAN_OUT_CMAC67 | output | TCELL93:OUT.2.TMIN |
| SCAN_OUT_CMAC68 | output | TCELL94:OUT.28.TMIN |
| SCAN_OUT_CMAC69 | output | TCELL94:OUT.2.TMIN |
| SCAN_OUT_CMAC7 | output | TCELL63:OUT.2.TMIN |
| SCAN_OUT_CMAC70 | output | TCELL95:OUT.28.TMIN |
| SCAN_OUT_CMAC71 | output | TCELL95:OUT.2.TMIN |
| SCAN_OUT_CMAC72 | output | TCELL96:OUT.28.TMIN |
| SCAN_OUT_CMAC73 | output | TCELL96:OUT.2.TMIN |
| SCAN_OUT_CMAC74 | output | TCELL97:OUT.28.TMIN |
| SCAN_OUT_CMAC75 | output | TCELL97:OUT.2.TMIN |
| SCAN_OUT_CMAC76 | output | TCELL98:OUT.28.TMIN |
| SCAN_OUT_CMAC77 | output | TCELL98:OUT.2.TMIN |
| SCAN_OUT_CMAC78 | output | TCELL99:OUT.28.TMIN |
| SCAN_OUT_CMAC79 | output | TCELL99:OUT.2.TMIN |
| SCAN_OUT_CMAC8 | output | TCELL64:OUT.28.TMIN |
| SCAN_OUT_CMAC80 | output | TCELL100:OUT.28.TMIN |
| SCAN_OUT_CMAC81 | output | TCELL100:OUT.2.TMIN |
| SCAN_OUT_CMAC82 | output | TCELL101:OUT.28.TMIN |
| SCAN_OUT_CMAC83 | output | TCELL101:OUT.2.TMIN |
| SCAN_OUT_CMAC84 | output | TCELL102:OUT.28.TMIN |
| SCAN_OUT_CMAC85 | output | TCELL102:OUT.2.TMIN |
| SCAN_OUT_CMAC86 | output | TCELL103:OUT.28.TMIN |
| SCAN_OUT_CMAC87 | output | TCELL103:OUT.2.TMIN |
| SCAN_OUT_CMAC88 | output | TCELL104:OUT.28.TMIN |
| SCAN_OUT_CMAC89 | output | TCELL104:OUT.2.TMIN |
| SCAN_OUT_CMAC9 | output | TCELL64:OUT.2.TMIN |
| SCAN_OUT_CMAC90 | output | TCELL105:OUT.28.TMIN |
| SCAN_OUT_CMAC91 | output | TCELL105:OUT.2.TMIN |
| SCAN_OUT_CMAC92 | output | TCELL106:OUT.28.TMIN |
| SCAN_OUT_CMAC93 | output | TCELL106:OUT.2.TMIN |
| SCAN_OUT_CMAC94 | output | TCELL107:OUT.28.TMIN |
| SCAN_OUT_CMAC95 | output | TCELL107:OUT.2.TMIN |
| SCAN_OUT_CMAC96 | output | TCELL108:OUT.28.TMIN |
| SCAN_OUT_CMAC97 | output | TCELL108:OUT.2.TMIN |
| SCAN_OUT_CMAC98 | output | TCELL109:OUT.28.TMIN |
| SCAN_OUT_CMAC99 | output | TCELL109:OUT.2.TMIN |
| SCAN_OUT_DRPCTRL0 | output | TCELL37:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL1 | output | TCELL36:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL10 | output | TCELL27:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL11 | output | TCELL26:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL12 | output | TCELL25:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL2 | output | TCELL35:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL3 | output | TCELL34:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL4 | output | TCELL33:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL5 | output | TCELL32:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL6 | output | TCELL31:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL7 | output | TCELL30:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL8 | output | TCELL29:OUT.24.TMIN |
| SCAN_OUT_DRPCTRL9 | output | TCELL28:OUT.24.TMIN |
| STAT_RX_ALIGNED | output | TCELL1:OUT.16.TMIN |
| STAT_RX_ALIGNED_ERR | output | TCELL2:OUT.16.TMIN |
| STAT_RX_BAD_CODE0 | output | TCELL39:OUT.0.TMIN |
| STAT_RX_BAD_CODE1 | output | TCELL39:OUT.2.TMIN |
| STAT_RX_BAD_CODE2 | output | TCELL39:OUT.4.TMIN |
| STAT_RX_BAD_CODE3 | output | TCELL39:OUT.6.TMIN |
| STAT_RX_BAD_CODE4 | output | TCELL39:OUT.8.TMIN |
| STAT_RX_BAD_CODE5 | output | TCELL39:OUT.10.TMIN |
| STAT_RX_BAD_CODE6 | output | TCELL39:OUT.12.TMIN |
| STAT_RX_BAD_FCS0 | output | TCELL38:OUT.8.TMIN |
| STAT_RX_BAD_FCS1 | output | TCELL38:OUT.10.TMIN |
| STAT_RX_BAD_FCS2 | output | TCELL38:OUT.12.TMIN |
| STAT_RX_BAD_FCS3 | output | TCELL38:OUT.14.TMIN |
| STAT_RX_BAD_PREAMBLE | output | TCELL40:OUT.8.TMIN |
| STAT_RX_BAD_SFD | output | TCELL40:OUT.6.TMIN |
| STAT_RX_BIP_ERR_0 | output | TCELL36:OUT.0.TMIN |
| STAT_RX_BIP_ERR_1 | output | TCELL36:OUT.2.TMIN |
| STAT_RX_BIP_ERR_10 | output | TCELL37:OUT.4.TMIN |
| STAT_RX_BIP_ERR_11 | output | TCELL37:OUT.6.TMIN |
| STAT_RX_BIP_ERR_12 | output | TCELL37:OUT.8.TMIN |
| STAT_RX_BIP_ERR_13 | output | TCELL37:OUT.10.TMIN |
| STAT_RX_BIP_ERR_14 | output | TCELL37:OUT.12.TMIN |
| STAT_RX_BIP_ERR_15 | output | TCELL37:OUT.14.TMIN |
| STAT_RX_BIP_ERR_16 | output | TCELL38:OUT.0.TMIN |
| STAT_RX_BIP_ERR_17 | output | TCELL38:OUT.2.TMIN |
| STAT_RX_BIP_ERR_18 | output | TCELL38:OUT.4.TMIN |
| STAT_RX_BIP_ERR_19 | output | TCELL38:OUT.6.TMIN |
| STAT_RX_BIP_ERR_2 | output | TCELL36:OUT.4.TMIN |
| STAT_RX_BIP_ERR_3 | output | TCELL36:OUT.6.TMIN |
| STAT_RX_BIP_ERR_4 | output | TCELL36:OUT.8.TMIN |
| STAT_RX_BIP_ERR_5 | output | TCELL36:OUT.10.TMIN |
| STAT_RX_BIP_ERR_6 | output | TCELL36:OUT.12.TMIN |
| STAT_RX_BIP_ERR_7 | output | TCELL36:OUT.14.TMIN |
| STAT_RX_BIP_ERR_8 | output | TCELL37:OUT.0.TMIN |
| STAT_RX_BIP_ERR_9 | output | TCELL37:OUT.2.TMIN |
| STAT_RX_BLOCK_LOCK0 | output | TCELL69:OUT.3.TMIN |
| STAT_RX_BLOCK_LOCK1 | output | TCELL69:OUT.7.TMIN |
| STAT_RX_BLOCK_LOCK10 | output | TCELL70:OUT.11.TMIN |
| STAT_RX_BLOCK_LOCK11 | output | TCELL70:OUT.15.TMIN |
| STAT_RX_BLOCK_LOCK12 | output | TCELL70:OUT.19.TMIN |
| STAT_RX_BLOCK_LOCK13 | output | TCELL70:OUT.23.TMIN |
| STAT_RX_BLOCK_LOCK14 | output | TCELL70:OUT.27.TMIN |
| STAT_RX_BLOCK_LOCK15 | output | TCELL70:OUT.31.TMIN |
| STAT_RX_BLOCK_LOCK16 | output | TCELL71:OUT.3.TMIN |
| STAT_RX_BLOCK_LOCK17 | output | TCELL71:OUT.7.TMIN |
| STAT_RX_BLOCK_LOCK18 | output | TCELL71:OUT.11.TMIN |
| STAT_RX_BLOCK_LOCK19 | output | TCELL71:OUT.15.TMIN |
| STAT_RX_BLOCK_LOCK2 | output | TCELL69:OUT.11.TMIN |
| STAT_RX_BLOCK_LOCK3 | output | TCELL69:OUT.15.TMIN |
| STAT_RX_BLOCK_LOCK4 | output | TCELL69:OUT.19.TMIN |
| STAT_RX_BLOCK_LOCK5 | output | TCELL69:OUT.23.TMIN |
| STAT_RX_BLOCK_LOCK6 | output | TCELL69:OUT.27.TMIN |
| STAT_RX_BLOCK_LOCK7 | output | TCELL69:OUT.31.TMIN |
| STAT_RX_BLOCK_LOCK8 | output | TCELL70:OUT.3.TMIN |
| STAT_RX_BLOCK_LOCK9 | output | TCELL70:OUT.7.TMIN |
| STAT_RX_BROADCAST | output | TCELL56:OUT.12.TMIN |
| STAT_RX_FRAGMENT0 | output | TCELL71:OUT.19.TMIN |
| STAT_RX_FRAGMENT1 | output | TCELL71:OUT.23.TMIN |
| STAT_RX_FRAGMENT2 | output | TCELL71:OUT.27.TMIN |
| STAT_RX_FRAGMENT3 | output | TCELL71:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_0_0 | output | TCELL72:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_0_1 | output | TCELL72:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_0_2 | output | TCELL72:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_0_3 | output | TCELL72:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_10_0 | output | TCELL72:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_10_1 | output | TCELL72:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_10_2 | output | TCELL72:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_10_3 | output | TCELL72:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_11_0 | output | TCELL72:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_11_1 | output | TCELL72:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_11_2 | output | TCELL72:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_11_3 | output | TCELL72:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_12_0 | output | TCELL73:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_12_1 | output | TCELL73:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_12_2 | output | TCELL73:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_12_3 | output | TCELL73:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_13_0 | output | TCELL73:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_13_1 | output | TCELL73:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_13_2 | output | TCELL73:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_13_3 | output | TCELL73:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_14_0 | output | TCELL74:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_14_1 | output | TCELL74:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_14_2 | output | TCELL74:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_14_3 | output | TCELL74:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_15_0 | output | TCELL74:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_15_1 | output | TCELL74:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_15_2 | output | TCELL74:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_15_3 | output | TCELL74:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_16_0 | output | TCELL75:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_16_1 | output | TCELL75:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_16_2 | output | TCELL75:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_16_3 | output | TCELL75:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_17_0 | output | TCELL75:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_17_1 | output | TCELL75:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_17_2 | output | TCELL75:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_17_3 | output | TCELL75:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_18_0 | output | TCELL76:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_18_1 | output | TCELL76:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_18_2 | output | TCELL76:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_18_3 | output | TCELL76:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_19_0 | output | TCELL76:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_19_1 | output | TCELL76:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_19_2 | output | TCELL76:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_19_3 | output | TCELL76:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_1_0 | output | TCELL72:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_1_1 | output | TCELL72:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_1_2 | output | TCELL72:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_1_3 | output | TCELL72:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_2_0 | output | TCELL73:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_2_1 | output | TCELL73:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_2_2 | output | TCELL73:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_2_3 | output | TCELL73:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_3_0 | output | TCELL73:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_3_1 | output | TCELL73:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_3_2 | output | TCELL73:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_3_3 | output | TCELL73:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_4_0 | output | TCELL74:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_4_1 | output | TCELL74:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_4_2 | output | TCELL74:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_4_3 | output | TCELL74:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_5_0 | output | TCELL74:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_5_1 | output | TCELL74:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_5_2 | output | TCELL74:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_5_3 | output | TCELL74:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_6_0 | output | TCELL75:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_6_1 | output | TCELL75:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_6_2 | output | TCELL75:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_6_3 | output | TCELL75:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_7_0 | output | TCELL75:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_7_1 | output | TCELL75:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_7_2 | output | TCELL75:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_7_3 | output | TCELL75:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_8_0 | output | TCELL76:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_8_1 | output | TCELL76:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_8_2 | output | TCELL76:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_8_3 | output | TCELL76:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_9_0 | output | TCELL76:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_9_1 | output | TCELL76:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_9_2 | output | TCELL76:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_9_3 | output | TCELL76:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_VALID_0 | output | TCELL77:OUT.1.TMIN |
| STAT_RX_FRAMING_ERR_VALID_1 | output | TCELL77:OUT.5.TMIN |
| STAT_RX_FRAMING_ERR_VALID_10 | output | TCELL77:OUT.3.TMIN |
| STAT_RX_FRAMING_ERR_VALID_11 | output | TCELL77:OUT.7.TMIN |
| STAT_RX_FRAMING_ERR_VALID_12 | output | TCELL77:OUT.11.TMIN |
| STAT_RX_FRAMING_ERR_VALID_13 | output | TCELL77:OUT.15.TMIN |
| STAT_RX_FRAMING_ERR_VALID_14 | output | TCELL77:OUT.19.TMIN |
| STAT_RX_FRAMING_ERR_VALID_15 | output | TCELL77:OUT.23.TMIN |
| STAT_RX_FRAMING_ERR_VALID_16 | output | TCELL77:OUT.27.TMIN |
| STAT_RX_FRAMING_ERR_VALID_17 | output | TCELL77:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_VALID_18 | output | TCELL78:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_VALID_19 | output | TCELL79:OUT.31.TMIN |
| STAT_RX_FRAMING_ERR_VALID_2 | output | TCELL77:OUT.9.TMIN |
| STAT_RX_FRAMING_ERR_VALID_3 | output | TCELL77:OUT.13.TMIN |
| STAT_RX_FRAMING_ERR_VALID_4 | output | TCELL77:OUT.17.TMIN |
| STAT_RX_FRAMING_ERR_VALID_5 | output | TCELL77:OUT.21.TMIN |
| STAT_RX_FRAMING_ERR_VALID_6 | output | TCELL77:OUT.25.TMIN |
| STAT_RX_FRAMING_ERR_VALID_7 | output | TCELL77:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_VALID_8 | output | TCELL78:OUT.29.TMIN |
| STAT_RX_FRAMING_ERR_VALID_9 | output | TCELL79:OUT.29.TMIN |
| STAT_RX_GOT_SIGNAL_OS | output | TCELL4:OUT.16.TMIN |
| STAT_RX_HI_BER | output | TCELL2:OUT.14.TMIN |
| STAT_RX_INRANGEERR | output | TCELL4:OUT.6.TMIN |
| STAT_RX_INTERNAL_LOCAL_FAULT | output | TCELL2:OUT.12.TMIN |
| STAT_RX_JABBER | output | TCELL2:OUT.10.TMIN |
| STAT_RX_LANE0_VLM_BIP7_0 | output | TCELL41:OUT.0.TMIN |
| STAT_RX_LANE0_VLM_BIP7_1 | output | TCELL41:OUT.2.TMIN |
| STAT_RX_LANE0_VLM_BIP7_2 | output | TCELL41:OUT.4.TMIN |
| STAT_RX_LANE0_VLM_BIP7_3 | output | TCELL41:OUT.6.TMIN |
| STAT_RX_LANE0_VLM_BIP7_4 | output | TCELL41:OUT.8.TMIN |
| STAT_RX_LANE0_VLM_BIP7_5 | output | TCELL41:OUT.10.TMIN |
| STAT_RX_LANE0_VLM_BIP7_6 | output | TCELL41:OUT.12.TMIN |
| STAT_RX_LANE0_VLM_BIP7_7 | output | TCELL41:OUT.14.TMIN |
| STAT_RX_LANE0_VLM_BIP7_VALID | output | TCELL40:OUT.10.TMIN |
| STAT_RX_LOCAL_FAULT | output | TCELL2:OUT.8.TMIN |
| STAT_RX_MF_ERR0 | output | TCELL0:OUT.0.TMIN |
| STAT_RX_MF_ERR1 | output | TCELL0:OUT.2.TMIN |
| STAT_RX_MF_ERR10 | output | TCELL1:OUT.4.TMIN |
| STAT_RX_MF_ERR11 | output | TCELL1:OUT.6.TMIN |
| STAT_RX_MF_ERR12 | output | TCELL1:OUT.8.TMIN |
| STAT_RX_MF_ERR13 | output | TCELL1:OUT.10.TMIN |
| STAT_RX_MF_ERR14 | output | TCELL1:OUT.12.TMIN |
| STAT_RX_MF_ERR15 | output | TCELL1:OUT.14.TMIN |
| STAT_RX_MF_ERR16 | output | TCELL2:OUT.0.TMIN |
| STAT_RX_MF_ERR17 | output | TCELL2:OUT.2.TMIN |
| STAT_RX_MF_ERR18 | output | TCELL2:OUT.4.TMIN |
| STAT_RX_MF_ERR19 | output | TCELL2:OUT.6.TMIN |
| STAT_RX_MF_ERR2 | output | TCELL0:OUT.4.TMIN |
| STAT_RX_MF_ERR3 | output | TCELL0:OUT.6.TMIN |
| STAT_RX_MF_ERR4 | output | TCELL0:OUT.8.TMIN |
| STAT_RX_MF_ERR5 | output | TCELL0:OUT.10.TMIN |
| STAT_RX_MF_ERR6 | output | TCELL0:OUT.12.TMIN |
| STAT_RX_MF_ERR7 | output | TCELL0:OUT.14.TMIN |
| STAT_RX_MF_ERR8 | output | TCELL1:OUT.0.TMIN |
| STAT_RX_MF_ERR9 | output | TCELL1:OUT.2.TMIN |
| STAT_RX_MF_LEN_ERR0 | output | TCELL0:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR1 | output | TCELL1:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR10 | output | TCELL10:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR11 | output | TCELL11:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR12 | output | TCELL12:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR13 | output | TCELL13:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR14 | output | TCELL14:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR15 | output | TCELL15:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR16 | output | TCELL16:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR17 | output | TCELL17:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR18 | output | TCELL18:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR19 | output | TCELL19:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR2 | output | TCELL2:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR3 | output | TCELL3:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR4 | output | TCELL4:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR5 | output | TCELL5:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR6 | output | TCELL6:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR7 | output | TCELL7:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR8 | output | TCELL8:OUT.30.TMIN |
| STAT_RX_MF_LEN_ERR9 | output | TCELL9:OUT.30.TMIN |
| STAT_RX_MF_REPEAT_ERR0 | output | TCELL0:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR1 | output | TCELL1:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR10 | output | TCELL10:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR11 | output | TCELL11:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR12 | output | TCELL12:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR13 | output | TCELL13:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR14 | output | TCELL14:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR15 | output | TCELL15:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR16 | output | TCELL16:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR17 | output | TCELL17:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR18 | output | TCELL18:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR19 | output | TCELL19:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR2 | output | TCELL2:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR3 | output | TCELL3:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR4 | output | TCELL4:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR5 | output | TCELL5:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR6 | output | TCELL6:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR7 | output | TCELL7:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR8 | output | TCELL8:OUT.26.TMIN |
| STAT_RX_MF_REPEAT_ERR9 | output | TCELL9:OUT.26.TMIN |
| STAT_RX_MISALIGNED | output | TCELL80:OUT.29.TMIN |
| STAT_RX_MULTICAST | output | TCELL80:OUT.31.TMIN |
| STAT_RX_OVERSIZE | output | TCELL81:OUT.31.TMIN |
| STAT_RX_PACKET_1024_1518_BYTES | output | TCELL82:OUT.29.TMIN |
| STAT_RX_PACKET_128_255_BYTES | output | TCELL82:OUT.31.TMIN |
| STAT_RX_PACKET_1519_1522_BYTES | output | TCELL83:OUT.29.TMIN |
| STAT_RX_PACKET_1523_1548_BYTES | output | TCELL83:OUT.31.TMIN |
| STAT_RX_PACKET_1549_2047_BYTES | output | TCELL84:OUT.29.TMIN |
| STAT_RX_PACKET_2048_4095_BYTES | output | TCELL84:OUT.31.TMIN |
| STAT_RX_PACKET_256_511_BYTES | output | TCELL85:OUT.29.TMIN |
| STAT_RX_PACKET_4096_8191_BYTES | output | TCELL85:OUT.31.TMIN |
| STAT_RX_PACKET_512_1023_BYTES | output | TCELL86:OUT.29.TMIN |
| STAT_RX_PACKET_64_BYTES | output | TCELL86:OUT.31.TMIN |
| STAT_RX_PACKET_65_127_BYTES | output | TCELL87:OUT.29.TMIN |
| STAT_RX_PACKET_8192_9215_BYTES | output | TCELL87:OUT.31.TMIN |
| STAT_RX_PACKET_BAD_FCS | output | TCELL57:OUT.10.TMIN |
| STAT_RX_PACKET_LARGE | output | TCELL57:OUT.8.TMIN |
| STAT_RX_PACKET_SMALL0 | output | TCELL57:OUT.0.TMIN |
| STAT_RX_PACKET_SMALL1 | output | TCELL57:OUT.2.TMIN |
| STAT_RX_PACKET_SMALL2 | output | TCELL57:OUT.4.TMIN |
| STAT_RX_PACKET_SMALL3 | output | TCELL57:OUT.6.TMIN |
| STAT_RX_PAUSE | output | TCELL4:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA0_0 | output | TCELL33:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA0_1 | output | TCELL33:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA0_10 | output | TCELL32:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA0_11 | output | TCELL32:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA0_12 | output | TCELL32:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA0_13 | output | TCELL32:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA0_14 | output | TCELL32:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA0_15 | output | TCELL32:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA0_2 | output | TCELL33:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA0_3 | output | TCELL33:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA0_4 | output | TCELL33:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA0_5 | output | TCELL33:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA0_6 | output | TCELL33:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA0_7 | output | TCELL33:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA0_8 | output | TCELL32:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA0_9 | output | TCELL32:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA1_0 | output | TCELL31:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA1_1 | output | TCELL31:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA1_10 | output | TCELL30:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA1_11 | output | TCELL30:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA1_12 | output | TCELL30:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA1_13 | output | TCELL30:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA1_14 | output | TCELL30:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA1_15 | output | TCELL30:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA1_2 | output | TCELL31:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA1_3 | output | TCELL31:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA1_4 | output | TCELL31:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA1_5 | output | TCELL31:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA1_6 | output | TCELL31:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA1_7 | output | TCELL31:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA1_8 | output | TCELL30:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA1_9 | output | TCELL30:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA2_0 | output | TCELL29:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA2_1 | output | TCELL29:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA2_10 | output | TCELL28:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA2_11 | output | TCELL28:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA2_12 | output | TCELL28:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA2_13 | output | TCELL28:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA2_14 | output | TCELL28:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA2_15 | output | TCELL28:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA2_2 | output | TCELL29:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA2_3 | output | TCELL29:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA2_4 | output | TCELL29:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA2_5 | output | TCELL29:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA2_6 | output | TCELL29:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA2_7 | output | TCELL29:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA2_8 | output | TCELL28:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA2_9 | output | TCELL28:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA3_0 | output | TCELL27:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA3_1 | output | TCELL27:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA3_10 | output | TCELL26:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA3_11 | output | TCELL26:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA3_12 | output | TCELL26:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA3_13 | output | TCELL26:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA3_14 | output | TCELL26:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA3_15 | output | TCELL26:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA3_2 | output | TCELL27:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA3_3 | output | TCELL27:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA3_4 | output | TCELL27:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA3_5 | output | TCELL27:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA3_6 | output | TCELL27:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA3_7 | output | TCELL27:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA3_8 | output | TCELL26:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA3_9 | output | TCELL26:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA4_0 | output | TCELL25:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA4_1 | output | TCELL25:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA4_10 | output | TCELL24:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA4_11 | output | TCELL24:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA4_12 | output | TCELL24:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA4_13 | output | TCELL24:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA4_14 | output | TCELL24:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA4_15 | output | TCELL24:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA4_2 | output | TCELL25:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA4_3 | output | TCELL25:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA4_4 | output | TCELL25:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA4_5 | output | TCELL25:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA4_6 | output | TCELL25:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA4_7 | output | TCELL25:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA4_8 | output | TCELL24:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA4_9 | output | TCELL24:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA5_0 | output | TCELL23:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA5_1 | output | TCELL23:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA5_10 | output | TCELL22:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA5_11 | output | TCELL22:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA5_12 | output | TCELL22:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA5_13 | output | TCELL22:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA5_14 | output | TCELL22:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA5_15 | output | TCELL22:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA5_2 | output | TCELL23:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA5_3 | output | TCELL23:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA5_4 | output | TCELL23:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA5_5 | output | TCELL23:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA5_6 | output | TCELL23:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA5_7 | output | TCELL23:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA5_8 | output | TCELL22:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA5_9 | output | TCELL22:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA6_0 | output | TCELL21:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA6_1 | output | TCELL21:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA6_10 | output | TCELL20:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA6_11 | output | TCELL20:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA6_12 | output | TCELL20:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA6_13 | output | TCELL20:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA6_14 | output | TCELL20:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA6_15 | output | TCELL20:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA6_2 | output | TCELL21:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA6_3 | output | TCELL21:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA6_4 | output | TCELL21:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA6_5 | output | TCELL21:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA6_6 | output | TCELL21:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA6_7 | output | TCELL21:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA6_8 | output | TCELL20:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA6_9 | output | TCELL20:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA7_0 | output | TCELL19:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA7_1 | output | TCELL19:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA7_10 | output | TCELL18:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA7_11 | output | TCELL18:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA7_12 | output | TCELL18:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA7_13 | output | TCELL18:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA7_14 | output | TCELL18:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA7_15 | output | TCELL18:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA7_2 | output | TCELL19:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA7_3 | output | TCELL19:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA7_4 | output | TCELL19:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA7_5 | output | TCELL19:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA7_6 | output | TCELL19:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA7_7 | output | TCELL19:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA7_8 | output | TCELL18:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA7_9 | output | TCELL18:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA8_0 | output | TCELL17:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA8_1 | output | TCELL17:OUT.2.TMIN |
| STAT_RX_PAUSE_QUANTA8_10 | output | TCELL16:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA8_11 | output | TCELL16:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA8_12 | output | TCELL16:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA8_13 | output | TCELL16:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA8_14 | output | TCELL16:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA8_15 | output | TCELL16:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA8_2 | output | TCELL17:OUT.4.TMIN |
| STAT_RX_PAUSE_QUANTA8_3 | output | TCELL17:OUT.6.TMIN |
| STAT_RX_PAUSE_QUANTA8_4 | output | TCELL17:OUT.8.TMIN |
| STAT_RX_PAUSE_QUANTA8_5 | output | TCELL17:OUT.10.TMIN |
| STAT_RX_PAUSE_QUANTA8_6 | output | TCELL17:OUT.12.TMIN |
| STAT_RX_PAUSE_QUANTA8_7 | output | TCELL17:OUT.14.TMIN |
| STAT_RX_PAUSE_QUANTA8_8 | output | TCELL16:OUT.0.TMIN |
| STAT_RX_PAUSE_QUANTA8_9 | output | TCELL16:OUT.2.TMIN |
| STAT_RX_PAUSE_REQ0 | output | TCELL5:OUT.0.TMIN |
| STAT_RX_PAUSE_REQ1 | output | TCELL5:OUT.2.TMIN |
| STAT_RX_PAUSE_REQ2 | output | TCELL5:OUT.4.TMIN |
| STAT_RX_PAUSE_REQ3 | output | TCELL5:OUT.6.TMIN |
| STAT_RX_PAUSE_REQ4 | output | TCELL5:OUT.8.TMIN |
| STAT_RX_PAUSE_REQ5 | output | TCELL5:OUT.10.TMIN |
| STAT_RX_PAUSE_REQ6 | output | TCELL5:OUT.12.TMIN |
| STAT_RX_PAUSE_REQ7 | output | TCELL5:OUT.14.TMIN |
| STAT_RX_PAUSE_REQ8 | output | TCELL4:OUT.0.TMIN |
| STAT_RX_PAUSE_VALID0 | output | TCELL3:OUT.0.TMIN |
| STAT_RX_PAUSE_VALID1 | output | TCELL3:OUT.2.TMIN |
| STAT_RX_PAUSE_VALID2 | output | TCELL3:OUT.4.TMIN |
| STAT_RX_PAUSE_VALID3 | output | TCELL3:OUT.6.TMIN |
| STAT_RX_PAUSE_VALID4 | output | TCELL3:OUT.8.TMIN |
| STAT_RX_PAUSE_VALID5 | output | TCELL3:OUT.10.TMIN |
| STAT_RX_PAUSE_VALID6 | output | TCELL3:OUT.12.TMIN |
| STAT_RX_PAUSE_VALID7 | output | TCELL3:OUT.14.TMIN |
| STAT_RX_PAUSE_VALID8 | output | TCELL3:OUT.16.TMIN |
| STAT_RX_RECEIVED_LOCAL_FAULT | output | TCELL68:OUT.31.TMIN |
| STAT_RX_REMOTE_FAULT | output | TCELL68:OUT.27.TMIN |
| STAT_RX_STATUS | output | TCELL56:OUT.10.TMIN |
| STAT_RX_STOMPED_FCS0 | output | TCELL68:OUT.11.TMIN |
| STAT_RX_STOMPED_FCS1 | output | TCELL68:OUT.15.TMIN |
| STAT_RX_STOMPED_FCS2 | output | TCELL68:OUT.19.TMIN |
| STAT_RX_STOMPED_FCS3 | output | TCELL68:OUT.23.TMIN |
| STAT_RX_SYNCED0 | output | TCELL20:OUT.30.TMIN |
| STAT_RX_SYNCED1 | output | TCELL21:OUT.30.TMIN |
| STAT_RX_SYNCED10 | output | TCELL30:OUT.30.TMIN |
| STAT_RX_SYNCED11 | output | TCELL31:OUT.30.TMIN |
| STAT_RX_SYNCED12 | output | TCELL32:OUT.30.TMIN |
| STAT_RX_SYNCED13 | output | TCELL33:OUT.30.TMIN |
| STAT_RX_SYNCED14 | output | TCELL34:OUT.30.TMIN |
| STAT_RX_SYNCED15 | output | TCELL35:OUT.30.TMIN |
| STAT_RX_SYNCED16 | output | TCELL36:OUT.30.TMIN |
| STAT_RX_SYNCED17 | output | TCELL37:OUT.30.TMIN |
| STAT_RX_SYNCED18 | output | TCELL38:OUT.30.TMIN |
| STAT_RX_SYNCED19 | output | TCELL39:OUT.30.TMIN |
| STAT_RX_SYNCED2 | output | TCELL22:OUT.30.TMIN |
| STAT_RX_SYNCED3 | output | TCELL23:OUT.30.TMIN |
| STAT_RX_SYNCED4 | output | TCELL24:OUT.30.TMIN |
| STAT_RX_SYNCED5 | output | TCELL25:OUT.30.TMIN |
| STAT_RX_SYNCED6 | output | TCELL26:OUT.30.TMIN |
| STAT_RX_SYNCED7 | output | TCELL27:OUT.30.TMIN |
| STAT_RX_SYNCED8 | output | TCELL28:OUT.30.TMIN |
| STAT_RX_SYNCED9 | output | TCELL29:OUT.30.TMIN |
| STAT_RX_SYNCED_ERR0 | output | TCELL20:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR1 | output | TCELL21:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR10 | output | TCELL30:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR11 | output | TCELL31:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR12 | output | TCELL32:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR13 | output | TCELL33:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR14 | output | TCELL34:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR15 | output | TCELL35:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR16 | output | TCELL36:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR17 | output | TCELL37:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR18 | output | TCELL38:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR19 | output | TCELL39:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR2 | output | TCELL22:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR3 | output | TCELL23:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR4 | output | TCELL24:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR5 | output | TCELL25:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR6 | output | TCELL26:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR7 | output | TCELL27:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR8 | output | TCELL28:OUT.26.TMIN |
| STAT_RX_SYNCED_ERR9 | output | TCELL29:OUT.26.TMIN |
| STAT_RX_TEST_PATTERN_MISMATCH0 | output | TCELL40:OUT.0.TMIN |
| STAT_RX_TEST_PATTERN_MISMATCH1 | output | TCELL40:OUT.2.TMIN |
| STAT_RX_TEST_PATTERN_MISMATCH2 | output | TCELL40:OUT.4.TMIN |
| STAT_RX_TOOLONG | output | TCELL35:OUT.14.TMIN |
| STAT_RX_TOTAL_BYTES0 | output | TCELL42:OUT.0.TMIN |
| STAT_RX_TOTAL_BYTES1 | output | TCELL42:OUT.2.TMIN |
| STAT_RX_TOTAL_BYTES2 | output | TCELL42:OUT.4.TMIN |
| STAT_RX_TOTAL_BYTES3 | output | TCELL42:OUT.6.TMIN |
| STAT_RX_TOTAL_BYTES4 | output | TCELL42:OUT.8.TMIN |
| STAT_RX_TOTAL_BYTES5 | output | TCELL42:OUT.10.TMIN |
| STAT_RX_TOTAL_BYTES6 | output | TCELL42:OUT.12.TMIN |
| STAT_RX_TOTAL_BYTES7 | output | TCELL42:OUT.14.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES0 | output | TCELL34:OUT.0.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES1 | output | TCELL34:OUT.2.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES10 | output | TCELL35:OUT.4.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES11 | output | TCELL35:OUT.6.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES12 | output | TCELL35:OUT.8.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES13 | output | TCELL35:OUT.10.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES2 | output | TCELL34:OUT.4.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES3 | output | TCELL34:OUT.6.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES4 | output | TCELL34:OUT.8.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES5 | output | TCELL34:OUT.10.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES6 | output | TCELL34:OUT.12.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES7 | output | TCELL34:OUT.14.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES8 | output | TCELL35:OUT.0.TMIN |
| STAT_RX_TOTAL_GOOD_BYTES9 | output | TCELL35:OUT.2.TMIN |
| STAT_RX_TOTAL_GOOD_PACKETS | output | TCELL35:OUT.12.TMIN |
| STAT_RX_TOTAL_PACKETS0 | output | TCELL43:OUT.8.TMIN |
| STAT_RX_TOTAL_PACKETS1 | output | TCELL43:OUT.10.TMIN |
| STAT_RX_TOTAL_PACKETS2 | output | TCELL43:OUT.12.TMIN |
| STAT_RX_TOTAL_PACKETS3 | output | TCELL43:OUT.14.TMIN |
| STAT_RX_TRUNCATED | output | TCELL57:OUT.14.TMIN |
| STAT_RX_UNDERSIZE0 | output | TCELL4:OUT.8.TMIN |
| STAT_RX_UNDERSIZE1 | output | TCELL4:OUT.10.TMIN |
| STAT_RX_UNDERSIZE2 | output | TCELL4:OUT.12.TMIN |
| STAT_RX_UNDERSIZE3 | output | TCELL4:OUT.14.TMIN |
| STAT_RX_UNICAST | output | TCELL57:OUT.12.TMIN |
| STAT_RX_USER_PAUSE | output | TCELL4:OUT.2.TMIN |
| STAT_RX_VLAN | output | TCELL39:OUT.14.TMIN |
| STAT_RX_VL_DEMUXED0 | output | TCELL45:OUT.0.TMIN |
| STAT_RX_VL_DEMUXED1 | output | TCELL45:OUT.2.TMIN |
| STAT_RX_VL_DEMUXED10 | output | TCELL44:OUT.4.TMIN |
| STAT_RX_VL_DEMUXED11 | output | TCELL44:OUT.6.TMIN |
| STAT_RX_VL_DEMUXED12 | output | TCELL44:OUT.8.TMIN |
| STAT_RX_VL_DEMUXED13 | output | TCELL44:OUT.10.TMIN |
| STAT_RX_VL_DEMUXED14 | output | TCELL44:OUT.12.TMIN |
| STAT_RX_VL_DEMUXED15 | output | TCELL44:OUT.14.TMIN |
| STAT_RX_VL_DEMUXED16 | output | TCELL43:OUT.0.TMIN |
| STAT_RX_VL_DEMUXED17 | output | TCELL43:OUT.2.TMIN |
| STAT_RX_VL_DEMUXED18 | output | TCELL43:OUT.4.TMIN |
| STAT_RX_VL_DEMUXED19 | output | TCELL43:OUT.6.TMIN |
| STAT_RX_VL_DEMUXED2 | output | TCELL45:OUT.4.TMIN |
| STAT_RX_VL_DEMUXED3 | output | TCELL45:OUT.6.TMIN |
| STAT_RX_VL_DEMUXED4 | output | TCELL45:OUT.8.TMIN |
| STAT_RX_VL_DEMUXED5 | output | TCELL45:OUT.10.TMIN |
| STAT_RX_VL_DEMUXED6 | output | TCELL45:OUT.12.TMIN |
| STAT_RX_VL_DEMUXED7 | output | TCELL45:OUT.14.TMIN |
| STAT_RX_VL_DEMUXED8 | output | TCELL44:OUT.0.TMIN |
| STAT_RX_VL_DEMUXED9 | output | TCELL44:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_0_0 | output | TCELL6:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_0_1 | output | TCELL6:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_0_2 | output | TCELL6:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_0_3 | output | TCELL6:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_0_4 | output | TCELL6:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_10_0 | output | TCELL11:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_10_1 | output | TCELL11:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_10_2 | output | TCELL11:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_10_3 | output | TCELL11:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_10_4 | output | TCELL11:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_11_0 | output | TCELL11:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_11_1 | output | TCELL11:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_11_2 | output | TCELL11:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_11_3 | output | TCELL11:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_11_4 | output | TCELL11:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_12_0 | output | TCELL12:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_12_1 | output | TCELL12:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_12_2 | output | TCELL12:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_12_3 | output | TCELL12:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_12_4 | output | TCELL12:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_13_0 | output | TCELL12:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_13_1 | output | TCELL12:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_13_2 | output | TCELL12:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_13_3 | output | TCELL12:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_13_4 | output | TCELL12:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_14_0 | output | TCELL13:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_14_1 | output | TCELL13:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_14_2 | output | TCELL13:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_14_3 | output | TCELL13:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_14_4 | output | TCELL13:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_15_0 | output | TCELL13:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_15_1 | output | TCELL13:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_15_2 | output | TCELL13:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_15_3 | output | TCELL13:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_15_4 | output | TCELL13:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_16_0 | output | TCELL14:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_16_1 | output | TCELL14:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_16_2 | output | TCELL14:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_16_3 | output | TCELL14:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_16_4 | output | TCELL14:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_17_0 | output | TCELL14:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_17_1 | output | TCELL14:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_17_2 | output | TCELL14:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_17_3 | output | TCELL14:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_17_4 | output | TCELL14:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_18_0 | output | TCELL15:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_18_1 | output | TCELL15:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_18_2 | output | TCELL15:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_18_3 | output | TCELL15:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_18_4 | output | TCELL15:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_19_0 | output | TCELL15:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_19_1 | output | TCELL15:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_19_2 | output | TCELL15:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_19_3 | output | TCELL15:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_19_4 | output | TCELL15:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_1_0 | output | TCELL6:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_1_1 | output | TCELL6:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_1_2 | output | TCELL6:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_1_3 | output | TCELL6:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_1_4 | output | TCELL6:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_2_0 | output | TCELL7:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_2_1 | output | TCELL7:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_2_2 | output | TCELL7:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_2_3 | output | TCELL7:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_2_4 | output | TCELL7:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_3_0 | output | TCELL7:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_3_1 | output | TCELL7:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_3_2 | output | TCELL7:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_3_3 | output | TCELL7:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_3_4 | output | TCELL7:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_4_0 | output | TCELL8:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_4_1 | output | TCELL8:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_4_2 | output | TCELL8:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_4_3 | output | TCELL8:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_4_4 | output | TCELL8:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_5_0 | output | TCELL8:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_5_1 | output | TCELL8:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_5_2 | output | TCELL8:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_5_3 | output | TCELL8:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_5_4 | output | TCELL8:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_6_0 | output | TCELL9:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_6_1 | output | TCELL9:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_6_2 | output | TCELL9:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_6_3 | output | TCELL9:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_6_4 | output | TCELL9:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_7_0 | output | TCELL9:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_7_1 | output | TCELL9:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_7_2 | output | TCELL9:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_7_3 | output | TCELL9:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_7_4 | output | TCELL9:OUT.18.TMIN |
| STAT_RX_VL_NUMBER_8_0 | output | TCELL10:OUT.0.TMIN |
| STAT_RX_VL_NUMBER_8_1 | output | TCELL10:OUT.2.TMIN |
| STAT_RX_VL_NUMBER_8_2 | output | TCELL10:OUT.4.TMIN |
| STAT_RX_VL_NUMBER_8_3 | output | TCELL10:OUT.6.TMIN |
| STAT_RX_VL_NUMBER_8_4 | output | TCELL10:OUT.8.TMIN |
| STAT_RX_VL_NUMBER_9_0 | output | TCELL10:OUT.10.TMIN |
| STAT_RX_VL_NUMBER_9_1 | output | TCELL10:OUT.12.TMIN |
| STAT_RX_VL_NUMBER_9_2 | output | TCELL10:OUT.14.TMIN |
| STAT_RX_VL_NUMBER_9_3 | output | TCELL10:OUT.16.TMIN |
| STAT_RX_VL_NUMBER_9_4 | output | TCELL10:OUT.18.TMIN |
| STAT_TX_BAD_FCS | output | TCELL60:OUT.27.TMIN |
| STAT_TX_BROADCAST | output | TCELL60:OUT.31.TMIN |
| STAT_TX_FRAME_ERROR | output | TCELL61:OUT.31.TMIN |
| STAT_TX_LOCAL_FAULT | output | TCELL61:OUT.27.TMIN |
| STAT_TX_MULTICAST | output | TCELL61:OUT.23.TMIN |
| STAT_TX_PACKET_1024_1518_BYTES | output | TCELL61:OUT.19.TMIN |
| STAT_TX_PACKET_128_255_BYTES | output | TCELL61:OUT.15.TMIN |
| STAT_TX_PACKET_1519_1522_BYTES | output | TCELL61:OUT.11.TMIN |
| STAT_TX_PACKET_1523_1548_BYTES | output | TCELL61:OUT.7.TMIN |
| STAT_TX_PACKET_1549_2047_BYTES | output | TCELL61:OUT.3.TMIN |
| STAT_TX_PACKET_2048_4095_BYTES | output | TCELL62:OUT.3.TMIN |
| STAT_TX_PACKET_256_511_BYTES | output | TCELL62:OUT.7.TMIN |
| STAT_TX_PACKET_4096_8191_BYTES | output | TCELL62:OUT.11.TMIN |
| STAT_TX_PACKET_512_1023_BYTES | output | TCELL62:OUT.15.TMIN |
| STAT_TX_PACKET_64_BYTES | output | TCELL62:OUT.19.TMIN |
| STAT_TX_PACKET_65_127_BYTES | output | TCELL62:OUT.23.TMIN |
| STAT_TX_PACKET_8192_9215_BYTES | output | TCELL62:OUT.27.TMIN |
| STAT_TX_PACKET_LARGE | output | TCELL62:OUT.31.TMIN |
| STAT_TX_PACKET_SMALL | output | TCELL63:OUT.31.TMIN |
| STAT_TX_PAUSE | output | TCELL63:OUT.27.TMIN |
| STAT_TX_PAUSE_VALID0 | output | TCELL65:OUT.3.TMIN |
| STAT_TX_PAUSE_VALID1 | output | TCELL65:OUT.7.TMIN |
| STAT_TX_PAUSE_VALID2 | output | TCELL65:OUT.11.TMIN |
| STAT_TX_PAUSE_VALID3 | output | TCELL65:OUT.15.TMIN |
| STAT_TX_PAUSE_VALID4 | output | TCELL65:OUT.19.TMIN |
| STAT_TX_PAUSE_VALID5 | output | TCELL65:OUT.23.TMIN |
| STAT_TX_PAUSE_VALID6 | output | TCELL65:OUT.27.TMIN |
| STAT_TX_PAUSE_VALID7 | output | TCELL65:OUT.31.TMIN |
| STAT_TX_PAUSE_VALID8 | output | TCELL66:OUT.3.TMIN |
| STAT_TX_PTP_FIFO_READ_ERROR | output | TCELL67:OUT.31.TMIN |
| STAT_TX_PTP_FIFO_WRITE_ERROR | output | TCELL67:OUT.27.TMIN |
| STAT_TX_TOTAL_BYTES0 | output | TCELL66:OUT.7.TMIN |
| STAT_TX_TOTAL_BYTES1 | output | TCELL66:OUT.11.TMIN |
| STAT_TX_TOTAL_BYTES2 | output | TCELL66:OUT.15.TMIN |
| STAT_TX_TOTAL_BYTES3 | output | TCELL66:OUT.19.TMIN |
| STAT_TX_TOTAL_BYTES4 | output | TCELL66:OUT.23.TMIN |
| STAT_TX_TOTAL_BYTES5 | output | TCELL66:OUT.27.TMIN |
| STAT_TX_TOTAL_BYTES6 | output | TCELL66:OUT.31.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES0 | output | TCELL64:OUT.3.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES1 | output | TCELL64:OUT.7.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES10 | output | TCELL63:OUT.11.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES11 | output | TCELL63:OUT.15.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES12 | output | TCELL63:OUT.19.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES13 | output | TCELL63:OUT.23.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES2 | output | TCELL64:OUT.11.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES3 | output | TCELL64:OUT.15.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES4 | output | TCELL64:OUT.19.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES5 | output | TCELL64:OUT.23.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES6 | output | TCELL64:OUT.27.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES7 | output | TCELL64:OUT.31.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES8 | output | TCELL63:OUT.3.TMIN |
| STAT_TX_TOTAL_GOOD_BYTES9 | output | TCELL63:OUT.7.TMIN |
| STAT_TX_TOTAL_GOOD_PACKETS | output | TCELL67:OUT.23.TMIN |
| STAT_TX_TOTAL_PACKETS | output | TCELL67:OUT.19.TMIN |
| STAT_TX_UNICAST | output | TCELL67:OUT.15.TMIN |
| STAT_TX_USER_PAUSE | output | TCELL67:OUT.11.TMIN |
| STAT_TX_VLAN | output | TCELL67:OUT.7.TMIN |
| TEST_MODE_N | input | TCELL55:IMUX.CTRL.3 |
| TEST_RESET | input | TCELL33:IMUX.IMUX.4.DELAY |
| TX_CLK_B | input | TCELL30:IMUX.CTRL.2 |
| TX_DATAIN0_0 | input | TCELL60:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_1 | input | TCELL60:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_10 | input | TCELL61:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_100 | input | TCELL64:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_101 | input | TCELL64:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_102 | input | TCELL64:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_103 | input | TCELL64:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_104 | input | TCELL65:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_105 | input | TCELL65:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_106 | input | TCELL65:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_107 | input | TCELL65:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_108 | input | TCELL65:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_109 | input | TCELL65:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_11 | input | TCELL61:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_110 | input | TCELL65:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_111 | input | TCELL65:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_112 | input | TCELL66:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_113 | input | TCELL66:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_114 | input | TCELL66:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_115 | input | TCELL66:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_116 | input | TCELL66:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_117 | input | TCELL66:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_118 | input | TCELL66:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_119 | input | TCELL66:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_12 | input | TCELL61:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_120 | input | TCELL67:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_121 | input | TCELL67:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_122 | input | TCELL67:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_123 | input | TCELL67:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_124 | input | TCELL67:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_125 | input | TCELL67:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_126 | input | TCELL67:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_127 | input | TCELL67:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_13 | input | TCELL61:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_14 | input | TCELL61:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_15 | input | TCELL61:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_16 | input | TCELL62:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_17 | input | TCELL62:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_18 | input | TCELL62:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_19 | input | TCELL62:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_2 | input | TCELL60:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_20 | input | TCELL62:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_21 | input | TCELL62:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_22 | input | TCELL62:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_23 | input | TCELL62:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_24 | input | TCELL63:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_25 | input | TCELL63:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_26 | input | TCELL63:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_27 | input | TCELL63:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_28 | input | TCELL63:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_29 | input | TCELL63:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_3 | input | TCELL60:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_30 | input | TCELL63:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_31 | input | TCELL63:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_32 | input | TCELL64:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_33 | input | TCELL64:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_34 | input | TCELL64:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_35 | input | TCELL64:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_36 | input | TCELL64:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_37 | input | TCELL64:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_38 | input | TCELL64:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_39 | input | TCELL64:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_4 | input | TCELL60:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_40 | input | TCELL65:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_41 | input | TCELL65:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_42 | input | TCELL65:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_43 | input | TCELL65:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_44 | input | TCELL65:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_45 | input | TCELL65:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_46 | input | TCELL65:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_47 | input | TCELL65:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_48 | input | TCELL66:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_49 | input | TCELL66:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_5 | input | TCELL60:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_50 | input | TCELL66:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_51 | input | TCELL66:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_52 | input | TCELL66:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_53 | input | TCELL66:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_54 | input | TCELL66:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_55 | input | TCELL66:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_56 | input | TCELL67:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_57 | input | TCELL67:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_58 | input | TCELL67:IMUX.IMUX.13.DELAY |
| TX_DATAIN0_59 | input | TCELL67:IMUX.IMUX.19.DELAY |
| TX_DATAIN0_6 | input | TCELL60:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_60 | input | TCELL67:IMUX.IMUX.25.DELAY |
| TX_DATAIN0_61 | input | TCELL67:IMUX.IMUX.31.DELAY |
| TX_DATAIN0_62 | input | TCELL67:IMUX.IMUX.37.DELAY |
| TX_DATAIN0_63 | input | TCELL67:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_64 | input | TCELL60:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_65 | input | TCELL60:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_66 | input | TCELL60:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_67 | input | TCELL60:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_68 | input | TCELL60:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_69 | input | TCELL60:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_7 | input | TCELL60:IMUX.IMUX.43.DELAY |
| TX_DATAIN0_70 | input | TCELL60:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_71 | input | TCELL60:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_72 | input | TCELL61:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_73 | input | TCELL61:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_74 | input | TCELL61:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_75 | input | TCELL61:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_76 | input | TCELL61:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_77 | input | TCELL61:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_78 | input | TCELL61:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_79 | input | TCELL61:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_8 | input | TCELL61:IMUX.IMUX.1.DELAY |
| TX_DATAIN0_80 | input | TCELL62:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_81 | input | TCELL62:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_82 | input | TCELL62:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_83 | input | TCELL62:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_84 | input | TCELL62:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_85 | input | TCELL62:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_86 | input | TCELL62:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_87 | input | TCELL62:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_88 | input | TCELL63:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_89 | input | TCELL63:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_9 | input | TCELL61:IMUX.IMUX.7.DELAY |
| TX_DATAIN0_90 | input | TCELL63:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_91 | input | TCELL63:IMUX.IMUX.22.DELAY |
| TX_DATAIN0_92 | input | TCELL63:IMUX.IMUX.28.DELAY |
| TX_DATAIN0_93 | input | TCELL63:IMUX.IMUX.34.DELAY |
| TX_DATAIN0_94 | input | TCELL63:IMUX.IMUX.40.DELAY |
| TX_DATAIN0_95 | input | TCELL63:IMUX.IMUX.46.DELAY |
| TX_DATAIN0_96 | input | TCELL64:IMUX.IMUX.4.DELAY |
| TX_DATAIN0_97 | input | TCELL64:IMUX.IMUX.10.DELAY |
| TX_DATAIN0_98 | input | TCELL64:IMUX.IMUX.16.DELAY |
| TX_DATAIN0_99 | input | TCELL64:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_0 | input | TCELL68:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_1 | input | TCELL68:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_10 | input | TCELL69:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_100 | input | TCELL72:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_101 | input | TCELL72:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_102 | input | TCELL72:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_103 | input | TCELL72:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_104 | input | TCELL73:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_105 | input | TCELL73:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_106 | input | TCELL73:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_107 | input | TCELL73:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_108 | input | TCELL73:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_109 | input | TCELL73:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_11 | input | TCELL69:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_110 | input | TCELL73:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_111 | input | TCELL73:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_112 | input | TCELL74:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_113 | input | TCELL74:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_114 | input | TCELL74:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_115 | input | TCELL74:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_116 | input | TCELL74:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_117 | input | TCELL74:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_118 | input | TCELL74:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_119 | input | TCELL74:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_12 | input | TCELL69:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_120 | input | TCELL75:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_121 | input | TCELL75:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_122 | input | TCELL75:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_123 | input | TCELL75:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_124 | input | TCELL75:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_125 | input | TCELL75:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_126 | input | TCELL75:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_127 | input | TCELL75:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_13 | input | TCELL69:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_14 | input | TCELL69:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_15 | input | TCELL69:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_16 | input | TCELL70:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_17 | input | TCELL70:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_18 | input | TCELL70:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_19 | input | TCELL70:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_2 | input | TCELL68:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_20 | input | TCELL70:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_21 | input | TCELL70:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_22 | input | TCELL70:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_23 | input | TCELL70:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_24 | input | TCELL71:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_25 | input | TCELL71:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_26 | input | TCELL71:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_27 | input | TCELL71:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_28 | input | TCELL71:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_29 | input | TCELL71:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_3 | input | TCELL68:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_30 | input | TCELL71:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_31 | input | TCELL71:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_32 | input | TCELL72:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_33 | input | TCELL72:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_34 | input | TCELL72:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_35 | input | TCELL72:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_36 | input | TCELL72:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_37 | input | TCELL72:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_38 | input | TCELL72:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_39 | input | TCELL72:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_4 | input | TCELL68:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_40 | input | TCELL73:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_41 | input | TCELL73:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_42 | input | TCELL73:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_43 | input | TCELL73:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_44 | input | TCELL73:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_45 | input | TCELL73:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_46 | input | TCELL73:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_47 | input | TCELL73:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_48 | input | TCELL74:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_49 | input | TCELL74:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_5 | input | TCELL68:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_50 | input | TCELL74:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_51 | input | TCELL74:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_52 | input | TCELL74:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_53 | input | TCELL74:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_54 | input | TCELL74:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_55 | input | TCELL74:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_56 | input | TCELL75:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_57 | input | TCELL75:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_58 | input | TCELL75:IMUX.IMUX.13.DELAY |
| TX_DATAIN1_59 | input | TCELL75:IMUX.IMUX.19.DELAY |
| TX_DATAIN1_6 | input | TCELL68:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_60 | input | TCELL75:IMUX.IMUX.25.DELAY |
| TX_DATAIN1_61 | input | TCELL75:IMUX.IMUX.31.DELAY |
| TX_DATAIN1_62 | input | TCELL75:IMUX.IMUX.37.DELAY |
| TX_DATAIN1_63 | input | TCELL75:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_64 | input | TCELL68:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_65 | input | TCELL68:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_66 | input | TCELL68:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_67 | input | TCELL68:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_68 | input | TCELL68:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_69 | input | TCELL68:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_7 | input | TCELL68:IMUX.IMUX.43.DELAY |
| TX_DATAIN1_70 | input | TCELL68:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_71 | input | TCELL68:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_72 | input | TCELL69:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_73 | input | TCELL69:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_74 | input | TCELL69:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_75 | input | TCELL69:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_76 | input | TCELL69:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_77 | input | TCELL69:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_78 | input | TCELL69:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_79 | input | TCELL69:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_8 | input | TCELL69:IMUX.IMUX.1.DELAY |
| TX_DATAIN1_80 | input | TCELL70:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_81 | input | TCELL70:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_82 | input | TCELL70:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_83 | input | TCELL70:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_84 | input | TCELL70:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_85 | input | TCELL70:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_86 | input | TCELL70:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_87 | input | TCELL70:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_88 | input | TCELL71:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_89 | input | TCELL71:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_9 | input | TCELL69:IMUX.IMUX.7.DELAY |
| TX_DATAIN1_90 | input | TCELL71:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_91 | input | TCELL71:IMUX.IMUX.22.DELAY |
| TX_DATAIN1_92 | input | TCELL71:IMUX.IMUX.28.DELAY |
| TX_DATAIN1_93 | input | TCELL71:IMUX.IMUX.34.DELAY |
| TX_DATAIN1_94 | input | TCELL71:IMUX.IMUX.40.DELAY |
| TX_DATAIN1_95 | input | TCELL71:IMUX.IMUX.46.DELAY |
| TX_DATAIN1_96 | input | TCELL72:IMUX.IMUX.4.DELAY |
| TX_DATAIN1_97 | input | TCELL72:IMUX.IMUX.10.DELAY |
| TX_DATAIN1_98 | input | TCELL72:IMUX.IMUX.16.DELAY |
| TX_DATAIN1_99 | input | TCELL72:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_0 | input | TCELL76:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_1 | input | TCELL76:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_10 | input | TCELL77:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_100 | input | TCELL80:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_101 | input | TCELL80:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_102 | input | TCELL80:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_103 | input | TCELL80:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_104 | input | TCELL81:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_105 | input | TCELL81:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_106 | input | TCELL81:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_107 | input | TCELL81:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_108 | input | TCELL81:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_109 | input | TCELL81:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_11 | input | TCELL77:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_110 | input | TCELL81:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_111 | input | TCELL81:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_112 | input | TCELL82:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_113 | input | TCELL82:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_114 | input | TCELL82:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_115 | input | TCELL82:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_116 | input | TCELL82:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_117 | input | TCELL82:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_118 | input | TCELL82:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_119 | input | TCELL82:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_12 | input | TCELL77:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_120 | input | TCELL83:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_121 | input | TCELL83:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_122 | input | TCELL83:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_123 | input | TCELL83:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_124 | input | TCELL83:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_125 | input | TCELL83:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_126 | input | TCELL83:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_127 | input | TCELL83:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_13 | input | TCELL77:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_14 | input | TCELL77:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_15 | input | TCELL77:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_16 | input | TCELL78:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_17 | input | TCELL78:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_18 | input | TCELL78:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_19 | input | TCELL78:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_2 | input | TCELL76:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_20 | input | TCELL78:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_21 | input | TCELL78:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_22 | input | TCELL78:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_23 | input | TCELL78:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_24 | input | TCELL79:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_25 | input | TCELL79:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_26 | input | TCELL79:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_27 | input | TCELL79:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_28 | input | TCELL79:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_29 | input | TCELL79:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_3 | input | TCELL76:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_30 | input | TCELL79:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_31 | input | TCELL79:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_32 | input | TCELL80:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_33 | input | TCELL80:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_34 | input | TCELL80:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_35 | input | TCELL80:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_36 | input | TCELL80:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_37 | input | TCELL80:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_38 | input | TCELL80:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_39 | input | TCELL80:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_4 | input | TCELL76:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_40 | input | TCELL81:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_41 | input | TCELL81:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_42 | input | TCELL81:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_43 | input | TCELL81:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_44 | input | TCELL81:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_45 | input | TCELL81:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_46 | input | TCELL81:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_47 | input | TCELL81:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_48 | input | TCELL82:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_49 | input | TCELL82:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_5 | input | TCELL76:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_50 | input | TCELL82:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_51 | input | TCELL82:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_52 | input | TCELL82:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_53 | input | TCELL82:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_54 | input | TCELL82:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_55 | input | TCELL82:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_56 | input | TCELL83:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_57 | input | TCELL83:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_58 | input | TCELL83:IMUX.IMUX.13.DELAY |
| TX_DATAIN2_59 | input | TCELL83:IMUX.IMUX.19.DELAY |
| TX_DATAIN2_6 | input | TCELL76:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_60 | input | TCELL83:IMUX.IMUX.25.DELAY |
| TX_DATAIN2_61 | input | TCELL83:IMUX.IMUX.31.DELAY |
| TX_DATAIN2_62 | input | TCELL83:IMUX.IMUX.37.DELAY |
| TX_DATAIN2_63 | input | TCELL83:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_64 | input | TCELL76:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_65 | input | TCELL76:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_66 | input | TCELL76:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_67 | input | TCELL76:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_68 | input | TCELL76:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_69 | input | TCELL76:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_7 | input | TCELL76:IMUX.IMUX.43.DELAY |
| TX_DATAIN2_70 | input | TCELL76:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_71 | input | TCELL76:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_72 | input | TCELL77:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_73 | input | TCELL77:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_74 | input | TCELL77:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_75 | input | TCELL77:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_76 | input | TCELL77:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_77 | input | TCELL77:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_78 | input | TCELL77:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_79 | input | TCELL77:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_8 | input | TCELL77:IMUX.IMUX.1.DELAY |
| TX_DATAIN2_80 | input | TCELL78:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_81 | input | TCELL78:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_82 | input | TCELL78:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_83 | input | TCELL78:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_84 | input | TCELL78:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_85 | input | TCELL78:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_86 | input | TCELL78:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_87 | input | TCELL78:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_88 | input | TCELL79:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_89 | input | TCELL79:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_9 | input | TCELL77:IMUX.IMUX.7.DELAY |
| TX_DATAIN2_90 | input | TCELL79:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_91 | input | TCELL79:IMUX.IMUX.22.DELAY |
| TX_DATAIN2_92 | input | TCELL79:IMUX.IMUX.28.DELAY |
| TX_DATAIN2_93 | input | TCELL79:IMUX.IMUX.34.DELAY |
| TX_DATAIN2_94 | input | TCELL79:IMUX.IMUX.40.DELAY |
| TX_DATAIN2_95 | input | TCELL79:IMUX.IMUX.46.DELAY |
| TX_DATAIN2_96 | input | TCELL80:IMUX.IMUX.4.DELAY |
| TX_DATAIN2_97 | input | TCELL80:IMUX.IMUX.10.DELAY |
| TX_DATAIN2_98 | input | TCELL80:IMUX.IMUX.16.DELAY |
| TX_DATAIN2_99 | input | TCELL80:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_0 | input | TCELL84:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_1 | input | TCELL84:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_10 | input | TCELL85:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_100 | input | TCELL88:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_101 | input | TCELL88:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_102 | input | TCELL88:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_103 | input | TCELL88:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_104 | input | TCELL89:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_105 | input | TCELL89:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_106 | input | TCELL89:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_107 | input | TCELL89:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_108 | input | TCELL89:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_109 | input | TCELL89:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_11 | input | TCELL85:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_110 | input | TCELL89:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_111 | input | TCELL89:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_112 | input | TCELL90:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_113 | input | TCELL90:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_114 | input | TCELL90:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_115 | input | TCELL90:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_116 | input | TCELL90:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_117 | input | TCELL90:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_118 | input | TCELL90:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_119 | input | TCELL90:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_12 | input | TCELL85:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_120 | input | TCELL91:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_121 | input | TCELL91:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_122 | input | TCELL91:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_123 | input | TCELL91:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_124 | input | TCELL91:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_125 | input | TCELL91:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_126 | input | TCELL91:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_127 | input | TCELL91:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_13 | input | TCELL85:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_14 | input | TCELL85:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_15 | input | TCELL85:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_16 | input | TCELL86:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_17 | input | TCELL86:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_18 | input | TCELL86:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_19 | input | TCELL86:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_2 | input | TCELL84:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_20 | input | TCELL86:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_21 | input | TCELL86:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_22 | input | TCELL86:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_23 | input | TCELL86:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_24 | input | TCELL87:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_25 | input | TCELL87:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_26 | input | TCELL87:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_27 | input | TCELL87:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_28 | input | TCELL87:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_29 | input | TCELL87:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_3 | input | TCELL84:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_30 | input | TCELL87:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_31 | input | TCELL87:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_32 | input | TCELL88:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_33 | input | TCELL88:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_34 | input | TCELL88:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_35 | input | TCELL88:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_36 | input | TCELL88:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_37 | input | TCELL88:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_38 | input | TCELL88:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_39 | input | TCELL88:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_4 | input | TCELL84:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_40 | input | TCELL89:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_41 | input | TCELL89:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_42 | input | TCELL89:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_43 | input | TCELL89:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_44 | input | TCELL89:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_45 | input | TCELL89:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_46 | input | TCELL89:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_47 | input | TCELL89:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_48 | input | TCELL90:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_49 | input | TCELL90:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_5 | input | TCELL84:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_50 | input | TCELL90:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_51 | input | TCELL90:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_52 | input | TCELL90:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_53 | input | TCELL90:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_54 | input | TCELL90:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_55 | input | TCELL90:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_56 | input | TCELL91:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_57 | input | TCELL91:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_58 | input | TCELL91:IMUX.IMUX.13.DELAY |
| TX_DATAIN3_59 | input | TCELL91:IMUX.IMUX.19.DELAY |
| TX_DATAIN3_6 | input | TCELL84:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_60 | input | TCELL91:IMUX.IMUX.25.DELAY |
| TX_DATAIN3_61 | input | TCELL91:IMUX.IMUX.31.DELAY |
| TX_DATAIN3_62 | input | TCELL91:IMUX.IMUX.37.DELAY |
| TX_DATAIN3_63 | input | TCELL91:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_64 | input | TCELL84:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_65 | input | TCELL84:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_66 | input | TCELL84:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_67 | input | TCELL84:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_68 | input | TCELL84:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_69 | input | TCELL84:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_7 | input | TCELL84:IMUX.IMUX.43.DELAY |
| TX_DATAIN3_70 | input | TCELL84:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_71 | input | TCELL84:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_72 | input | TCELL85:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_73 | input | TCELL85:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_74 | input | TCELL85:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_75 | input | TCELL85:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_76 | input | TCELL85:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_77 | input | TCELL85:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_78 | input | TCELL85:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_79 | input | TCELL85:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_8 | input | TCELL85:IMUX.IMUX.1.DELAY |
| TX_DATAIN3_80 | input | TCELL86:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_81 | input | TCELL86:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_82 | input | TCELL86:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_83 | input | TCELL86:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_84 | input | TCELL86:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_85 | input | TCELL86:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_86 | input | TCELL86:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_87 | input | TCELL86:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_88 | input | TCELL87:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_89 | input | TCELL87:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_9 | input | TCELL85:IMUX.IMUX.7.DELAY |
| TX_DATAIN3_90 | input | TCELL87:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_91 | input | TCELL87:IMUX.IMUX.22.DELAY |
| TX_DATAIN3_92 | input | TCELL87:IMUX.IMUX.28.DELAY |
| TX_DATAIN3_93 | input | TCELL87:IMUX.IMUX.34.DELAY |
| TX_DATAIN3_94 | input | TCELL87:IMUX.IMUX.40.DELAY |
| TX_DATAIN3_95 | input | TCELL87:IMUX.IMUX.46.DELAY |
| TX_DATAIN3_96 | input | TCELL88:IMUX.IMUX.4.DELAY |
| TX_DATAIN3_97 | input | TCELL88:IMUX.IMUX.10.DELAY |
| TX_DATAIN3_98 | input | TCELL88:IMUX.IMUX.16.DELAY |
| TX_DATAIN3_99 | input | TCELL88:IMUX.IMUX.22.DELAY |
| TX_ENAIN0 | input | TCELL60:IMUX.IMUX.24.DELAY |
| TX_ENAIN1 | input | TCELL68:IMUX.IMUX.24.DELAY |
| TX_ENAIN2 | input | TCELL76:IMUX.IMUX.24.DELAY |
| TX_ENAIN3 | input | TCELL84:IMUX.IMUX.24.DELAY |
| TX_EOPIN0 | input | TCELL61:IMUX.IMUX.24.DELAY |
| TX_EOPIN1 | input | TCELL69:IMUX.IMUX.24.DELAY |
| TX_EOPIN2 | input | TCELL77:IMUX.IMUX.24.DELAY |
| TX_EOPIN3 | input | TCELL85:IMUX.IMUX.24.DELAY |
| TX_ERRIN0 | input | TCELL63:IMUX.IMUX.24.DELAY |
| TX_ERRIN1 | input | TCELL71:IMUX.IMUX.24.DELAY |
| TX_ERRIN2 | input | TCELL79:IMUX.IMUX.24.DELAY |
| TX_ERRIN3 | input | TCELL87:IMUX.IMUX.24.DELAY |
| TX_MTYIN0_0 | input | TCELL64:IMUX.IMUX.24.DELAY |
| TX_MTYIN0_1 | input | TCELL65:IMUX.IMUX.24.DELAY |
| TX_MTYIN0_2 | input | TCELL66:IMUX.IMUX.24.DELAY |
| TX_MTYIN0_3 | input | TCELL67:IMUX.IMUX.24.DELAY |
| TX_MTYIN1_0 | input | TCELL72:IMUX.IMUX.24.DELAY |
| TX_MTYIN1_1 | input | TCELL73:IMUX.IMUX.24.DELAY |
| TX_MTYIN1_2 | input | TCELL74:IMUX.IMUX.24.DELAY |
| TX_MTYIN1_3 | input | TCELL75:IMUX.IMUX.24.DELAY |
| TX_MTYIN2_0 | input | TCELL80:IMUX.IMUX.24.DELAY |
| TX_MTYIN2_1 | input | TCELL81:IMUX.IMUX.24.DELAY |
| TX_MTYIN2_2 | input | TCELL82:IMUX.IMUX.24.DELAY |
| TX_MTYIN2_3 | input | TCELL83:IMUX.IMUX.24.DELAY |
| TX_MTYIN3_0 | input | TCELL88:IMUX.IMUX.24.DELAY |
| TX_MTYIN3_1 | input | TCELL89:IMUX.IMUX.24.DELAY |
| TX_MTYIN3_2 | input | TCELL90:IMUX.IMUX.24.DELAY |
| TX_MTYIN3_3 | input | TCELL91:IMUX.IMUX.24.DELAY |
| TX_OVFOUT | output | TCELL68:OUT.7.TMIN |
| TX_PTP_1588OP_IN0 | input | TCELL15:IMUX.IMUX.32.DELAY |
| TX_PTP_1588OP_IN1 | input | TCELL15:IMUX.IMUX.35.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN0 | input | TCELL13:IMUX.IMUX.26.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN1 | input | TCELL13:IMUX.IMUX.29.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN10 | input | TCELL14:IMUX.IMUX.32.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN11 | input | TCELL14:IMUX.IMUX.35.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN12 | input | TCELL14:IMUX.IMUX.38.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN13 | input | TCELL14:IMUX.IMUX.41.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN14 | input | TCELL14:IMUX.IMUX.44.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN15 | input | TCELL14:IMUX.IMUX.47.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN2 | input | TCELL13:IMUX.IMUX.32.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN3 | input | TCELL13:IMUX.IMUX.35.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN4 | input | TCELL13:IMUX.IMUX.38.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN5 | input | TCELL13:IMUX.IMUX.41.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN6 | input | TCELL13:IMUX.IMUX.44.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN7 | input | TCELL13:IMUX.IMUX.47.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN8 | input | TCELL14:IMUX.IMUX.26.DELAY |
| TX_PTP_CHKSUM_OFFSET_IN9 | input | TCELL14:IMUX.IMUX.29.DELAY |
| TX_PTP_PCSLANE_OUT0 | output | TCELL60:OUT.3.TMIN |
| TX_PTP_PCSLANE_OUT1 | output | TCELL60:OUT.7.TMIN |
| TX_PTP_PCSLANE_OUT2 | output | TCELL60:OUT.11.TMIN |
| TX_PTP_PCSLANE_OUT3 | output | TCELL60:OUT.15.TMIN |
| TX_PTP_PCSLANE_OUT4 | output | TCELL60:OUT.19.TMIN |
| TX_PTP_RXTSTAMP_IN0 | input | TCELL5:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN1 | input | TCELL5:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN10 | input | TCELL6:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN11 | input | TCELL6:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN12 | input | TCELL6:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN13 | input | TCELL6:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN14 | input | TCELL6:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN15 | input | TCELL6:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN16 | input | TCELL7:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN17 | input | TCELL7:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN18 | input | TCELL7:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN19 | input | TCELL7:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN2 | input | TCELL5:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN20 | input | TCELL7:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN21 | input | TCELL7:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN22 | input | TCELL7:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN23 | input | TCELL7:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN24 | input | TCELL8:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN25 | input | TCELL8:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN26 | input | TCELL8:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN27 | input | TCELL8:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN28 | input | TCELL8:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN29 | input | TCELL8:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN3 | input | TCELL5:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN30 | input | TCELL8:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN31 | input | TCELL8:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN32 | input | TCELL9:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN33 | input | TCELL9:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN34 | input | TCELL9:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN35 | input | TCELL9:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN36 | input | TCELL9:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN37 | input | TCELL9:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN38 | input | TCELL9:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN39 | input | TCELL9:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN4 | input | TCELL5:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN40 | input | TCELL10:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN41 | input | TCELL10:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN42 | input | TCELL10:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN43 | input | TCELL10:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN44 | input | TCELL10:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN45 | input | TCELL10:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN46 | input | TCELL10:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN47 | input | TCELL10:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN48 | input | TCELL11:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN49 | input | TCELL11:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN5 | input | TCELL5:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN50 | input | TCELL11:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN51 | input | TCELL11:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN52 | input | TCELL11:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN53 | input | TCELL11:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN54 | input | TCELL11:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN55 | input | TCELL11:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN56 | input | TCELL12:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN57 | input | TCELL12:IMUX.IMUX.29.DELAY |
| TX_PTP_RXTSTAMP_IN58 | input | TCELL12:IMUX.IMUX.32.DELAY |
| TX_PTP_RXTSTAMP_IN59 | input | TCELL12:IMUX.IMUX.35.DELAY |
| TX_PTP_RXTSTAMP_IN6 | input | TCELL5:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN60 | input | TCELL12:IMUX.IMUX.38.DELAY |
| TX_PTP_RXTSTAMP_IN61 | input | TCELL12:IMUX.IMUX.41.DELAY |
| TX_PTP_RXTSTAMP_IN62 | input | TCELL12:IMUX.IMUX.44.DELAY |
| TX_PTP_RXTSTAMP_IN63 | input | TCELL12:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN7 | input | TCELL5:IMUX.IMUX.47.DELAY |
| TX_PTP_RXTSTAMP_IN8 | input | TCELL6:IMUX.IMUX.26.DELAY |
| TX_PTP_RXTSTAMP_IN9 | input | TCELL6:IMUX.IMUX.29.DELAY |
| TX_PTP_TAG_FIELD_IN0 | input | TCELL1:IMUX.IMUX.26.DELAY |
| TX_PTP_TAG_FIELD_IN1 | input | TCELL1:IMUX.IMUX.29.DELAY |
| TX_PTP_TAG_FIELD_IN10 | input | TCELL2:IMUX.IMUX.32.DELAY |
| TX_PTP_TAG_FIELD_IN11 | input | TCELL2:IMUX.IMUX.35.DELAY |
| TX_PTP_TAG_FIELD_IN12 | input | TCELL2:IMUX.IMUX.38.DELAY |
| TX_PTP_TAG_FIELD_IN13 | input | TCELL2:IMUX.IMUX.41.DELAY |
| TX_PTP_TAG_FIELD_IN14 | input | TCELL2:IMUX.IMUX.44.DELAY |
| TX_PTP_TAG_FIELD_IN15 | input | TCELL2:IMUX.IMUX.47.DELAY |
| TX_PTP_TAG_FIELD_IN2 | input | TCELL1:IMUX.IMUX.32.DELAY |
| TX_PTP_TAG_FIELD_IN3 | input | TCELL1:IMUX.IMUX.35.DELAY |
| TX_PTP_TAG_FIELD_IN4 | input | TCELL1:IMUX.IMUX.38.DELAY |
| TX_PTP_TAG_FIELD_IN5 | input | TCELL1:IMUX.IMUX.41.DELAY |
| TX_PTP_TAG_FIELD_IN6 | input | TCELL1:IMUX.IMUX.44.DELAY |
| TX_PTP_TAG_FIELD_IN7 | input | TCELL1:IMUX.IMUX.47.DELAY |
| TX_PTP_TAG_FIELD_IN8 | input | TCELL2:IMUX.IMUX.26.DELAY |
| TX_PTP_TAG_FIELD_IN9 | input | TCELL2:IMUX.IMUX.29.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN0 | input | TCELL3:IMUX.IMUX.26.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN1 | input | TCELL3:IMUX.IMUX.29.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN10 | input | TCELL4:IMUX.IMUX.32.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN11 | input | TCELL4:IMUX.IMUX.35.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN12 | input | TCELL4:IMUX.IMUX.38.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN13 | input | TCELL4:IMUX.IMUX.41.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN14 | input | TCELL4:IMUX.IMUX.44.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN15 | input | TCELL4:IMUX.IMUX.47.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN2 | input | TCELL3:IMUX.IMUX.32.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN3 | input | TCELL3:IMUX.IMUX.35.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN4 | input | TCELL3:IMUX.IMUX.38.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN5 | input | TCELL3:IMUX.IMUX.41.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN6 | input | TCELL3:IMUX.IMUX.44.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN7 | input | TCELL3:IMUX.IMUX.47.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN8 | input | TCELL4:IMUX.IMUX.26.DELAY |
| TX_PTP_TSTAMP_OFFSET_IN9 | input | TCELL4:IMUX.IMUX.29.DELAY |
| TX_PTP_TSTAMP_OUT0 | output | TCELL60:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT1 | output | TCELL60:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT10 | output | TCELL61:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT11 | output | TCELL61:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT12 | output | TCELL61:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT13 | output | TCELL61:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT14 | output | TCELL61:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT15 | output | TCELL61:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT16 | output | TCELL62:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT17 | output | TCELL62:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT18 | output | TCELL62:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT19 | output | TCELL62:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT2 | output | TCELL60:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT20 | output | TCELL62:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT21 | output | TCELL62:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT22 | output | TCELL62:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT23 | output | TCELL62:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT24 | output | TCELL63:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT25 | output | TCELL63:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT26 | output | TCELL63:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT27 | output | TCELL63:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT28 | output | TCELL63:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT29 | output | TCELL63:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT3 | output | TCELL60:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT30 | output | TCELL63:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT31 | output | TCELL63:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT32 | output | TCELL64:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT33 | output | TCELL64:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT34 | output | TCELL64:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT35 | output | TCELL64:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT36 | output | TCELL64:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT37 | output | TCELL64:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT38 | output | TCELL64:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT39 | output | TCELL64:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT4 | output | TCELL60:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT40 | output | TCELL65:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT41 | output | TCELL65:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT42 | output | TCELL65:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT43 | output | TCELL65:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT44 | output | TCELL65:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT45 | output | TCELL65:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT46 | output | TCELL65:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT47 | output | TCELL65:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT48 | output | TCELL66:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT49 | output | TCELL66:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT5 | output | TCELL60:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT50 | output | TCELL66:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT51 | output | TCELL66:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT52 | output | TCELL66:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT53 | output | TCELL66:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT54 | output | TCELL66:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT55 | output | TCELL66:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT56 | output | TCELL67:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT57 | output | TCELL67:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT58 | output | TCELL67:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT59 | output | TCELL67:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT6 | output | TCELL60:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT60 | output | TCELL67:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT61 | output | TCELL67:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT62 | output | TCELL67:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT63 | output | TCELL67:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT64 | output | TCELL68:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT65 | output | TCELL68:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT66 | output | TCELL68:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT67 | output | TCELL68:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT68 | output | TCELL68:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT69 | output | TCELL68:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT7 | output | TCELL60:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT70 | output | TCELL68:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT71 | output | TCELL68:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT72 | output | TCELL69:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT73 | output | TCELL69:OUT.5.TMIN |
| TX_PTP_TSTAMP_OUT74 | output | TCELL69:OUT.9.TMIN |
| TX_PTP_TSTAMP_OUT75 | output | TCELL69:OUT.13.TMIN |
| TX_PTP_TSTAMP_OUT76 | output | TCELL69:OUT.17.TMIN |
| TX_PTP_TSTAMP_OUT77 | output | TCELL69:OUT.21.TMIN |
| TX_PTP_TSTAMP_OUT78 | output | TCELL69:OUT.25.TMIN |
| TX_PTP_TSTAMP_OUT79 | output | TCELL69:OUT.29.TMIN |
| TX_PTP_TSTAMP_OUT8 | output | TCELL61:OUT.1.TMIN |
| TX_PTP_TSTAMP_OUT9 | output | TCELL61:OUT.5.TMIN |
| TX_PTP_TSTAMP_TAG_OUT0 | output | TCELL70:OUT.1.TMIN |
| TX_PTP_TSTAMP_TAG_OUT1 | output | TCELL70:OUT.5.TMIN |
| TX_PTP_TSTAMP_TAG_OUT10 | output | TCELL71:OUT.9.TMIN |
| TX_PTP_TSTAMP_TAG_OUT11 | output | TCELL71:OUT.13.TMIN |
| TX_PTP_TSTAMP_TAG_OUT12 | output | TCELL71:OUT.17.TMIN |
| TX_PTP_TSTAMP_TAG_OUT13 | output | TCELL71:OUT.21.TMIN |
| TX_PTP_TSTAMP_TAG_OUT14 | output | TCELL71:OUT.25.TMIN |
| TX_PTP_TSTAMP_TAG_OUT15 | output | TCELL71:OUT.29.TMIN |
| TX_PTP_TSTAMP_TAG_OUT2 | output | TCELL70:OUT.9.TMIN |
| TX_PTP_TSTAMP_TAG_OUT3 | output | TCELL70:OUT.13.TMIN |
| TX_PTP_TSTAMP_TAG_OUT4 | output | TCELL70:OUT.17.TMIN |
| TX_PTP_TSTAMP_TAG_OUT5 | output | TCELL70:OUT.21.TMIN |
| TX_PTP_TSTAMP_TAG_OUT6 | output | TCELL70:OUT.25.TMIN |
| TX_PTP_TSTAMP_TAG_OUT7 | output | TCELL70:OUT.29.TMIN |
| TX_PTP_TSTAMP_TAG_OUT8 | output | TCELL71:OUT.1.TMIN |
| TX_PTP_TSTAMP_TAG_OUT9 | output | TCELL71:OUT.5.TMIN |
| TX_PTP_TSTAMP_VALID_OUT | output | TCELL60:OUT.23.TMIN |
| TX_PTP_UPD_CHKSUM_IN | input | TCELL15:IMUX.IMUX.29.DELAY |
| TX_RDYOUT | output | TCELL68:OUT.3.TMIN |
| TX_RESET | input | TCELL26:IMUX.IMUX.5.DELAY |
| TX_SERDES_ALT_DATA0_0 | output | TCELL5:OUT.15.TMIN |
| TX_SERDES_ALT_DATA0_1 | output | TCELL5:OUT.17.TMIN |
| TX_SERDES_ALT_DATA0_10 | output | TCELL10:OUT.25.TMIN |
| TX_SERDES_ALT_DATA0_11 | output | TCELL10:OUT.27.TMIN |
| TX_SERDES_ALT_DATA0_12 | output | TCELL11:OUT.27.TMIN |
| TX_SERDES_ALT_DATA0_13 | output | TCELL11:OUT.29.TMIN |
| TX_SERDES_ALT_DATA0_14 | output | TCELL12:OUT.29.TMIN |
| TX_SERDES_ALT_DATA0_15 | output | TCELL12:OUT.31.TMIN |
| TX_SERDES_ALT_DATA0_2 | output | TCELL6:OUT.17.TMIN |
| TX_SERDES_ALT_DATA0_3 | output | TCELL6:OUT.19.TMIN |
| TX_SERDES_ALT_DATA0_4 | output | TCELL7:OUT.19.TMIN |
| TX_SERDES_ALT_DATA0_5 | output | TCELL7:OUT.21.TMIN |
| TX_SERDES_ALT_DATA0_6 | output | TCELL8:OUT.21.TMIN |
| TX_SERDES_ALT_DATA0_7 | output | TCELL8:OUT.23.TMIN |
| TX_SERDES_ALT_DATA0_8 | output | TCELL9:OUT.23.TMIN |
| TX_SERDES_ALT_DATA0_9 | output | TCELL9:OUT.25.TMIN |
| TX_SERDES_ALT_DATA1_0 | output | TCELL18:OUT.15.TMIN |
| TX_SERDES_ALT_DATA1_1 | output | TCELL18:OUT.17.TMIN |
| TX_SERDES_ALT_DATA1_10 | output | TCELL23:OUT.25.TMIN |
| TX_SERDES_ALT_DATA1_11 | output | TCELL23:OUT.27.TMIN |
| TX_SERDES_ALT_DATA1_12 | output | TCELL24:OUT.27.TMIN |
| TX_SERDES_ALT_DATA1_13 | output | TCELL24:OUT.29.TMIN |
| TX_SERDES_ALT_DATA1_14 | output | TCELL25:OUT.29.TMIN |
| TX_SERDES_ALT_DATA1_15 | output | TCELL25:OUT.31.TMIN |
| TX_SERDES_ALT_DATA1_2 | output | TCELL19:OUT.17.TMIN |
| TX_SERDES_ALT_DATA1_3 | output | TCELL19:OUT.19.TMIN |
| TX_SERDES_ALT_DATA1_4 | output | TCELL20:OUT.19.TMIN |
| TX_SERDES_ALT_DATA1_5 | output | TCELL20:OUT.21.TMIN |
| TX_SERDES_ALT_DATA1_6 | output | TCELL21:OUT.21.TMIN |
| TX_SERDES_ALT_DATA1_7 | output | TCELL21:OUT.23.TMIN |
| TX_SERDES_ALT_DATA1_8 | output | TCELL22:OUT.23.TMIN |
| TX_SERDES_ALT_DATA1_9 | output | TCELL22:OUT.25.TMIN |
| TX_SERDES_ALT_DATA2_0 | output | TCELL31:OUT.15.TMIN |
| TX_SERDES_ALT_DATA2_1 | output | TCELL31:OUT.17.TMIN |
| TX_SERDES_ALT_DATA2_10 | output | TCELL36:OUT.25.TMIN |
| TX_SERDES_ALT_DATA2_11 | output | TCELL36:OUT.27.TMIN |
| TX_SERDES_ALT_DATA2_12 | output | TCELL37:OUT.27.TMIN |
| TX_SERDES_ALT_DATA2_13 | output | TCELL37:OUT.29.TMIN |
| TX_SERDES_ALT_DATA2_14 | output | TCELL38:OUT.29.TMIN |
| TX_SERDES_ALT_DATA2_15 | output | TCELL38:OUT.31.TMIN |
| TX_SERDES_ALT_DATA2_2 | output | TCELL32:OUT.17.TMIN |
| TX_SERDES_ALT_DATA2_3 | output | TCELL32:OUT.19.TMIN |
| TX_SERDES_ALT_DATA2_4 | output | TCELL33:OUT.19.TMIN |
| TX_SERDES_ALT_DATA2_5 | output | TCELL33:OUT.21.TMIN |
| TX_SERDES_ALT_DATA2_6 | output | TCELL34:OUT.21.TMIN |
| TX_SERDES_ALT_DATA2_7 | output | TCELL34:OUT.23.TMIN |
| TX_SERDES_ALT_DATA2_8 | output | TCELL35:OUT.23.TMIN |
| TX_SERDES_ALT_DATA2_9 | output | TCELL35:OUT.25.TMIN |
| TX_SERDES_ALT_DATA3_0 | output | TCELL44:OUT.15.TMIN |
| TX_SERDES_ALT_DATA3_1 | output | TCELL44:OUT.17.TMIN |
| TX_SERDES_ALT_DATA3_10 | output | TCELL49:OUT.25.TMIN |
| TX_SERDES_ALT_DATA3_11 | output | TCELL49:OUT.27.TMIN |
| TX_SERDES_ALT_DATA3_12 | output | TCELL50:OUT.27.TMIN |
| TX_SERDES_ALT_DATA3_13 | output | TCELL50:OUT.29.TMIN |
| TX_SERDES_ALT_DATA3_14 | output | TCELL51:OUT.29.TMIN |
| TX_SERDES_ALT_DATA3_15 | output | TCELL51:OUT.31.TMIN |
| TX_SERDES_ALT_DATA3_2 | output | TCELL45:OUT.17.TMIN |
| TX_SERDES_ALT_DATA3_3 | output | TCELL45:OUT.19.TMIN |
| TX_SERDES_ALT_DATA3_4 | output | TCELL46:OUT.19.TMIN |
| TX_SERDES_ALT_DATA3_5 | output | TCELL46:OUT.21.TMIN |
| TX_SERDES_ALT_DATA3_6 | output | TCELL47:OUT.21.TMIN |
| TX_SERDES_ALT_DATA3_7 | output | TCELL47:OUT.23.TMIN |
| TX_SERDES_ALT_DATA3_8 | output | TCELL48:OUT.23.TMIN |
| TX_SERDES_ALT_DATA3_9 | output | TCELL48:OUT.25.TMIN |
| TX_SERDES_DATA0_0 | output | TCELL4:OUT.17.TMIN |
| TX_SERDES_DATA0_1 | output | TCELL4:OUT.19.TMIN |
| TX_SERDES_DATA0_10 | output | TCELL5:OUT.23.TMIN |
| TX_SERDES_DATA0_11 | output | TCELL5:OUT.25.TMIN |
| TX_SERDES_DATA0_12 | output | TCELL5:OUT.27.TMIN |
| TX_SERDES_DATA0_13 | output | TCELL5:OUT.29.TMIN |
| TX_SERDES_DATA0_14 | output | TCELL5:OUT.31.TMIN |
| TX_SERDES_DATA0_15 | output | TCELL6:OUT.15.TMIN |
| TX_SERDES_DATA0_16 | output | TCELL6:OUT.21.TMIN |
| TX_SERDES_DATA0_17 | output | TCELL6:OUT.23.TMIN |
| TX_SERDES_DATA0_18 | output | TCELL6:OUT.25.TMIN |
| TX_SERDES_DATA0_19 | output | TCELL6:OUT.27.TMIN |
| TX_SERDES_DATA0_2 | output | TCELL4:OUT.21.TMIN |
| TX_SERDES_DATA0_20 | output | TCELL6:OUT.29.TMIN |
| TX_SERDES_DATA0_21 | output | TCELL6:OUT.31.TMIN |
| TX_SERDES_DATA0_22 | output | TCELL7:OUT.15.TMIN |
| TX_SERDES_DATA0_23 | output | TCELL7:OUT.17.TMIN |
| TX_SERDES_DATA0_24 | output | TCELL7:OUT.23.TMIN |
| TX_SERDES_DATA0_25 | output | TCELL7:OUT.25.TMIN |
| TX_SERDES_DATA0_26 | output | TCELL7:OUT.27.TMIN |
| TX_SERDES_DATA0_27 | output | TCELL7:OUT.29.TMIN |
| TX_SERDES_DATA0_28 | output | TCELL7:OUT.31.TMIN |
| TX_SERDES_DATA0_29 | output | TCELL8:OUT.15.TMIN |
| TX_SERDES_DATA0_3 | output | TCELL4:OUT.23.TMIN |
| TX_SERDES_DATA0_30 | output | TCELL8:OUT.17.TMIN |
| TX_SERDES_DATA0_31 | output | TCELL8:OUT.19.TMIN |
| TX_SERDES_DATA0_32 | output | TCELL8:OUT.25.TMIN |
| TX_SERDES_DATA0_33 | output | TCELL8:OUT.27.TMIN |
| TX_SERDES_DATA0_34 | output | TCELL8:OUT.29.TMIN |
| TX_SERDES_DATA0_35 | output | TCELL8:OUT.31.TMIN |
| TX_SERDES_DATA0_36 | output | TCELL9:OUT.15.TMIN |
| TX_SERDES_DATA0_37 | output | TCELL9:OUT.17.TMIN |
| TX_SERDES_DATA0_38 | output | TCELL9:OUT.19.TMIN |
| TX_SERDES_DATA0_39 | output | TCELL9:OUT.21.TMIN |
| TX_SERDES_DATA0_4 | output | TCELL4:OUT.25.TMIN |
| TX_SERDES_DATA0_40 | output | TCELL9:OUT.27.TMIN |
| TX_SERDES_DATA0_41 | output | TCELL9:OUT.29.TMIN |
| TX_SERDES_DATA0_42 | output | TCELL9:OUT.31.TMIN |
| TX_SERDES_DATA0_43 | output | TCELL10:OUT.15.TMIN |
| TX_SERDES_DATA0_44 | output | TCELL10:OUT.17.TMIN |
| TX_SERDES_DATA0_45 | output | TCELL10:OUT.19.TMIN |
| TX_SERDES_DATA0_46 | output | TCELL10:OUT.21.TMIN |
| TX_SERDES_DATA0_47 | output | TCELL10:OUT.23.TMIN |
| TX_SERDES_DATA0_48 | output | TCELL10:OUT.29.TMIN |
| TX_SERDES_DATA0_49 | output | TCELL10:OUT.31.TMIN |
| TX_SERDES_DATA0_5 | output | TCELL4:OUT.27.TMIN |
| TX_SERDES_DATA0_50 | output | TCELL11:OUT.15.TMIN |
| TX_SERDES_DATA0_51 | output | TCELL11:OUT.17.TMIN |
| TX_SERDES_DATA0_52 | output | TCELL11:OUT.19.TMIN |
| TX_SERDES_DATA0_53 | output | TCELL11:OUT.21.TMIN |
| TX_SERDES_DATA0_54 | output | TCELL11:OUT.23.TMIN |
| TX_SERDES_DATA0_55 | output | TCELL11:OUT.25.TMIN |
| TX_SERDES_DATA0_56 | output | TCELL11:OUT.31.TMIN |
| TX_SERDES_DATA0_57 | output | TCELL12:OUT.15.TMIN |
| TX_SERDES_DATA0_58 | output | TCELL12:OUT.17.TMIN |
| TX_SERDES_DATA0_59 | output | TCELL12:OUT.19.TMIN |
| TX_SERDES_DATA0_6 | output | TCELL4:OUT.29.TMIN |
| TX_SERDES_DATA0_60 | output | TCELL12:OUT.21.TMIN |
| TX_SERDES_DATA0_61 | output | TCELL12:OUT.23.TMIN |
| TX_SERDES_DATA0_62 | output | TCELL12:OUT.25.TMIN |
| TX_SERDES_DATA0_63 | output | TCELL12:OUT.27.TMIN |
| TX_SERDES_DATA0_7 | output | TCELL4:OUT.31.TMIN |
| TX_SERDES_DATA0_8 | output | TCELL5:OUT.19.TMIN |
| TX_SERDES_DATA0_9 | output | TCELL5:OUT.21.TMIN |
| TX_SERDES_DATA1_0 | output | TCELL17:OUT.17.TMIN |
| TX_SERDES_DATA1_1 | output | TCELL17:OUT.19.TMIN |
| TX_SERDES_DATA1_10 | output | TCELL18:OUT.23.TMIN |
| TX_SERDES_DATA1_11 | output | TCELL18:OUT.25.TMIN |
| TX_SERDES_DATA1_12 | output | TCELL18:OUT.27.TMIN |
| TX_SERDES_DATA1_13 | output | TCELL18:OUT.29.TMIN |
| TX_SERDES_DATA1_14 | output | TCELL18:OUT.31.TMIN |
| TX_SERDES_DATA1_15 | output | TCELL19:OUT.15.TMIN |
| TX_SERDES_DATA1_16 | output | TCELL19:OUT.21.TMIN |
| TX_SERDES_DATA1_17 | output | TCELL19:OUT.23.TMIN |
| TX_SERDES_DATA1_18 | output | TCELL19:OUT.25.TMIN |
| TX_SERDES_DATA1_19 | output | TCELL19:OUT.27.TMIN |
| TX_SERDES_DATA1_2 | output | TCELL17:OUT.21.TMIN |
| TX_SERDES_DATA1_20 | output | TCELL19:OUT.29.TMIN |
| TX_SERDES_DATA1_21 | output | TCELL19:OUT.31.TMIN |
| TX_SERDES_DATA1_22 | output | TCELL20:OUT.15.TMIN |
| TX_SERDES_DATA1_23 | output | TCELL20:OUT.17.TMIN |
| TX_SERDES_DATA1_24 | output | TCELL20:OUT.23.TMIN |
| TX_SERDES_DATA1_25 | output | TCELL20:OUT.25.TMIN |
| TX_SERDES_DATA1_26 | output | TCELL20:OUT.27.TMIN |
| TX_SERDES_DATA1_27 | output | TCELL20:OUT.29.TMIN |
| TX_SERDES_DATA1_28 | output | TCELL20:OUT.31.TMIN |
| TX_SERDES_DATA1_29 | output | TCELL21:OUT.15.TMIN |
| TX_SERDES_DATA1_3 | output | TCELL17:OUT.23.TMIN |
| TX_SERDES_DATA1_30 | output | TCELL21:OUT.17.TMIN |
| TX_SERDES_DATA1_31 | output | TCELL21:OUT.19.TMIN |
| TX_SERDES_DATA1_32 | output | TCELL21:OUT.25.TMIN |
| TX_SERDES_DATA1_33 | output | TCELL21:OUT.27.TMIN |
| TX_SERDES_DATA1_34 | output | TCELL21:OUT.29.TMIN |
| TX_SERDES_DATA1_35 | output | TCELL21:OUT.31.TMIN |
| TX_SERDES_DATA1_36 | output | TCELL22:OUT.15.TMIN |
| TX_SERDES_DATA1_37 | output | TCELL22:OUT.17.TMIN |
| TX_SERDES_DATA1_38 | output | TCELL22:OUT.19.TMIN |
| TX_SERDES_DATA1_39 | output | TCELL22:OUT.21.TMIN |
| TX_SERDES_DATA1_4 | output | TCELL17:OUT.25.TMIN |
| TX_SERDES_DATA1_40 | output | TCELL22:OUT.27.TMIN |
| TX_SERDES_DATA1_41 | output | TCELL22:OUT.29.TMIN |
| TX_SERDES_DATA1_42 | output | TCELL22:OUT.31.TMIN |
| TX_SERDES_DATA1_43 | output | TCELL23:OUT.15.TMIN |
| TX_SERDES_DATA1_44 | output | TCELL23:OUT.17.TMIN |
| TX_SERDES_DATA1_45 | output | TCELL23:OUT.19.TMIN |
| TX_SERDES_DATA1_46 | output | TCELL23:OUT.21.TMIN |
| TX_SERDES_DATA1_47 | output | TCELL23:OUT.23.TMIN |
| TX_SERDES_DATA1_48 | output | TCELL23:OUT.29.TMIN |
| TX_SERDES_DATA1_49 | output | TCELL23:OUT.31.TMIN |
| TX_SERDES_DATA1_5 | output | TCELL17:OUT.27.TMIN |
| TX_SERDES_DATA1_50 | output | TCELL24:OUT.15.TMIN |
| TX_SERDES_DATA1_51 | output | TCELL24:OUT.17.TMIN |
| TX_SERDES_DATA1_52 | output | TCELL24:OUT.19.TMIN |
| TX_SERDES_DATA1_53 | output | TCELL24:OUT.21.TMIN |
| TX_SERDES_DATA1_54 | output | TCELL24:OUT.23.TMIN |
| TX_SERDES_DATA1_55 | output | TCELL24:OUT.25.TMIN |
| TX_SERDES_DATA1_56 | output | TCELL24:OUT.31.TMIN |
| TX_SERDES_DATA1_57 | output | TCELL25:OUT.15.TMIN |
| TX_SERDES_DATA1_58 | output | TCELL25:OUT.17.TMIN |
| TX_SERDES_DATA1_59 | output | TCELL25:OUT.19.TMIN |
| TX_SERDES_DATA1_6 | output | TCELL17:OUT.29.TMIN |
| TX_SERDES_DATA1_60 | output | TCELL25:OUT.21.TMIN |
| TX_SERDES_DATA1_61 | output | TCELL25:OUT.23.TMIN |
| TX_SERDES_DATA1_62 | output | TCELL25:OUT.25.TMIN |
| TX_SERDES_DATA1_63 | output | TCELL25:OUT.27.TMIN |
| TX_SERDES_DATA1_7 | output | TCELL17:OUT.31.TMIN |
| TX_SERDES_DATA1_8 | output | TCELL18:OUT.19.TMIN |
| TX_SERDES_DATA1_9 | output | TCELL18:OUT.21.TMIN |
| TX_SERDES_DATA2_0 | output | TCELL30:OUT.17.TMIN |
| TX_SERDES_DATA2_1 | output | TCELL30:OUT.19.TMIN |
| TX_SERDES_DATA2_10 | output | TCELL31:OUT.23.TMIN |
| TX_SERDES_DATA2_11 | output | TCELL31:OUT.25.TMIN |
| TX_SERDES_DATA2_12 | output | TCELL31:OUT.27.TMIN |
| TX_SERDES_DATA2_13 | output | TCELL31:OUT.29.TMIN |
| TX_SERDES_DATA2_14 | output | TCELL31:OUT.31.TMIN |
| TX_SERDES_DATA2_15 | output | TCELL32:OUT.15.TMIN |
| TX_SERDES_DATA2_16 | output | TCELL32:OUT.21.TMIN |
| TX_SERDES_DATA2_17 | output | TCELL32:OUT.23.TMIN |
| TX_SERDES_DATA2_18 | output | TCELL32:OUT.25.TMIN |
| TX_SERDES_DATA2_19 | output | TCELL32:OUT.27.TMIN |
| TX_SERDES_DATA2_2 | output | TCELL30:OUT.21.TMIN |
| TX_SERDES_DATA2_20 | output | TCELL32:OUT.29.TMIN |
| TX_SERDES_DATA2_21 | output | TCELL32:OUT.31.TMIN |
| TX_SERDES_DATA2_22 | output | TCELL33:OUT.15.TMIN |
| TX_SERDES_DATA2_23 | output | TCELL33:OUT.17.TMIN |
| TX_SERDES_DATA2_24 | output | TCELL33:OUT.23.TMIN |
| TX_SERDES_DATA2_25 | output | TCELL33:OUT.25.TMIN |
| TX_SERDES_DATA2_26 | output | TCELL33:OUT.27.TMIN |
| TX_SERDES_DATA2_27 | output | TCELL33:OUT.29.TMIN |
| TX_SERDES_DATA2_28 | output | TCELL33:OUT.31.TMIN |
| TX_SERDES_DATA2_29 | output | TCELL34:OUT.15.TMIN |
| TX_SERDES_DATA2_3 | output | TCELL30:OUT.23.TMIN |
| TX_SERDES_DATA2_30 | output | TCELL34:OUT.17.TMIN |
| TX_SERDES_DATA2_31 | output | TCELL34:OUT.19.TMIN |
| TX_SERDES_DATA2_32 | output | TCELL34:OUT.25.TMIN |
| TX_SERDES_DATA2_33 | output | TCELL34:OUT.27.TMIN |
| TX_SERDES_DATA2_34 | output | TCELL34:OUT.29.TMIN |
| TX_SERDES_DATA2_35 | output | TCELL34:OUT.31.TMIN |
| TX_SERDES_DATA2_36 | output | TCELL35:OUT.15.TMIN |
| TX_SERDES_DATA2_37 | output | TCELL35:OUT.17.TMIN |
| TX_SERDES_DATA2_38 | output | TCELL35:OUT.19.TMIN |
| TX_SERDES_DATA2_39 | output | TCELL35:OUT.21.TMIN |
| TX_SERDES_DATA2_4 | output | TCELL30:OUT.25.TMIN |
| TX_SERDES_DATA2_40 | output | TCELL35:OUT.27.TMIN |
| TX_SERDES_DATA2_41 | output | TCELL35:OUT.29.TMIN |
| TX_SERDES_DATA2_42 | output | TCELL35:OUT.31.TMIN |
| TX_SERDES_DATA2_43 | output | TCELL36:OUT.15.TMIN |
| TX_SERDES_DATA2_44 | output | TCELL36:OUT.17.TMIN |
| TX_SERDES_DATA2_45 | output | TCELL36:OUT.19.TMIN |
| TX_SERDES_DATA2_46 | output | TCELL36:OUT.21.TMIN |
| TX_SERDES_DATA2_47 | output | TCELL36:OUT.23.TMIN |
| TX_SERDES_DATA2_48 | output | TCELL36:OUT.29.TMIN |
| TX_SERDES_DATA2_49 | output | TCELL36:OUT.31.TMIN |
| TX_SERDES_DATA2_5 | output | TCELL30:OUT.27.TMIN |
| TX_SERDES_DATA2_50 | output | TCELL37:OUT.15.TMIN |
| TX_SERDES_DATA2_51 | output | TCELL37:OUT.17.TMIN |
| TX_SERDES_DATA2_52 | output | TCELL37:OUT.19.TMIN |
| TX_SERDES_DATA2_53 | output | TCELL37:OUT.21.TMIN |
| TX_SERDES_DATA2_54 | output | TCELL37:OUT.23.TMIN |
| TX_SERDES_DATA2_55 | output | TCELL37:OUT.25.TMIN |
| TX_SERDES_DATA2_56 | output | TCELL37:OUT.31.TMIN |
| TX_SERDES_DATA2_57 | output | TCELL38:OUT.15.TMIN |
| TX_SERDES_DATA2_58 | output | TCELL38:OUT.17.TMIN |
| TX_SERDES_DATA2_59 | output | TCELL38:OUT.19.TMIN |
| TX_SERDES_DATA2_6 | output | TCELL30:OUT.29.TMIN |
| TX_SERDES_DATA2_60 | output | TCELL38:OUT.21.TMIN |
| TX_SERDES_DATA2_61 | output | TCELL38:OUT.23.TMIN |
| TX_SERDES_DATA2_62 | output | TCELL38:OUT.25.TMIN |
| TX_SERDES_DATA2_63 | output | TCELL38:OUT.27.TMIN |
| TX_SERDES_DATA2_7 | output | TCELL30:OUT.31.TMIN |
| TX_SERDES_DATA2_8 | output | TCELL31:OUT.19.TMIN |
| TX_SERDES_DATA2_9 | output | TCELL31:OUT.21.TMIN |
| TX_SERDES_DATA3_0 | output | TCELL43:OUT.17.TMIN |
| TX_SERDES_DATA3_1 | output | TCELL43:OUT.19.TMIN |
| TX_SERDES_DATA3_10 | output | TCELL44:OUT.23.TMIN |
| TX_SERDES_DATA3_11 | output | TCELL44:OUT.25.TMIN |
| TX_SERDES_DATA3_12 | output | TCELL44:OUT.27.TMIN |
| TX_SERDES_DATA3_13 | output | TCELL44:OUT.29.TMIN |
| TX_SERDES_DATA3_14 | output | TCELL44:OUT.31.TMIN |
| TX_SERDES_DATA3_15 | output | TCELL45:OUT.15.TMIN |
| TX_SERDES_DATA3_16 | output | TCELL45:OUT.21.TMIN |
| TX_SERDES_DATA3_17 | output | TCELL45:OUT.23.TMIN |
| TX_SERDES_DATA3_18 | output | TCELL45:OUT.25.TMIN |
| TX_SERDES_DATA3_19 | output | TCELL45:OUT.27.TMIN |
| TX_SERDES_DATA3_2 | output | TCELL43:OUT.21.TMIN |
| TX_SERDES_DATA3_20 | output | TCELL45:OUT.29.TMIN |
| TX_SERDES_DATA3_21 | output | TCELL45:OUT.31.TMIN |
| TX_SERDES_DATA3_22 | output | TCELL46:OUT.15.TMIN |
| TX_SERDES_DATA3_23 | output | TCELL46:OUT.17.TMIN |
| TX_SERDES_DATA3_24 | output | TCELL46:OUT.23.TMIN |
| TX_SERDES_DATA3_25 | output | TCELL46:OUT.25.TMIN |
| TX_SERDES_DATA3_26 | output | TCELL46:OUT.27.TMIN |
| TX_SERDES_DATA3_27 | output | TCELL46:OUT.29.TMIN |
| TX_SERDES_DATA3_28 | output | TCELL46:OUT.31.TMIN |
| TX_SERDES_DATA3_29 | output | TCELL47:OUT.15.TMIN |
| TX_SERDES_DATA3_3 | output | TCELL43:OUT.23.TMIN |
| TX_SERDES_DATA3_30 | output | TCELL47:OUT.17.TMIN |
| TX_SERDES_DATA3_31 | output | TCELL47:OUT.19.TMIN |
| TX_SERDES_DATA3_32 | output | TCELL47:OUT.25.TMIN |
| TX_SERDES_DATA3_33 | output | TCELL47:OUT.27.TMIN |
| TX_SERDES_DATA3_34 | output | TCELL47:OUT.29.TMIN |
| TX_SERDES_DATA3_35 | output | TCELL47:OUT.31.TMIN |
| TX_SERDES_DATA3_36 | output | TCELL48:OUT.15.TMIN |
| TX_SERDES_DATA3_37 | output | TCELL48:OUT.17.TMIN |
| TX_SERDES_DATA3_38 | output | TCELL48:OUT.19.TMIN |
| TX_SERDES_DATA3_39 | output | TCELL48:OUT.21.TMIN |
| TX_SERDES_DATA3_4 | output | TCELL43:OUT.25.TMIN |
| TX_SERDES_DATA3_40 | output | TCELL48:OUT.27.TMIN |
| TX_SERDES_DATA3_41 | output | TCELL48:OUT.29.TMIN |
| TX_SERDES_DATA3_42 | output | TCELL48:OUT.31.TMIN |
| TX_SERDES_DATA3_43 | output | TCELL49:OUT.15.TMIN |
| TX_SERDES_DATA3_44 | output | TCELL49:OUT.17.TMIN |
| TX_SERDES_DATA3_45 | output | TCELL49:OUT.19.TMIN |
| TX_SERDES_DATA3_46 | output | TCELL49:OUT.21.TMIN |
| TX_SERDES_DATA3_47 | output | TCELL49:OUT.23.TMIN |
| TX_SERDES_DATA3_48 | output | TCELL49:OUT.29.TMIN |
| TX_SERDES_DATA3_49 | output | TCELL49:OUT.31.TMIN |
| TX_SERDES_DATA3_5 | output | TCELL43:OUT.27.TMIN |
| TX_SERDES_DATA3_50 | output | TCELL50:OUT.15.TMIN |
| TX_SERDES_DATA3_51 | output | TCELL50:OUT.17.TMIN |
| TX_SERDES_DATA3_52 | output | TCELL50:OUT.19.TMIN |
| TX_SERDES_DATA3_53 | output | TCELL50:OUT.21.TMIN |
| TX_SERDES_DATA3_54 | output | TCELL50:OUT.23.TMIN |
| TX_SERDES_DATA3_55 | output | TCELL50:OUT.25.TMIN |
| TX_SERDES_DATA3_56 | output | TCELL50:OUT.31.TMIN |
| TX_SERDES_DATA3_57 | output | TCELL51:OUT.15.TMIN |
| TX_SERDES_DATA3_58 | output | TCELL51:OUT.17.TMIN |
| TX_SERDES_DATA3_59 | output | TCELL51:OUT.19.TMIN |
| TX_SERDES_DATA3_6 | output | TCELL43:OUT.29.TMIN |
| TX_SERDES_DATA3_60 | output | TCELL51:OUT.21.TMIN |
| TX_SERDES_DATA3_61 | output | TCELL51:OUT.23.TMIN |
| TX_SERDES_DATA3_62 | output | TCELL51:OUT.25.TMIN |
| TX_SERDES_DATA3_63 | output | TCELL51:OUT.27.TMIN |
| TX_SERDES_DATA3_7 | output | TCELL43:OUT.31.TMIN |
| TX_SERDES_DATA3_8 | output | TCELL44:OUT.19.TMIN |
| TX_SERDES_DATA3_9 | output | TCELL44:OUT.21.TMIN |
| TX_SERDES_DATA4_0 | output | TCELL0:OUT.23.TMIN |
| TX_SERDES_DATA4_1 | output | TCELL0:OUT.25.TMIN |
| TX_SERDES_DATA4_10 | output | TCELL1:OUT.25.TMIN |
| TX_SERDES_DATA4_11 | output | TCELL1:OUT.27.TMIN |
| TX_SERDES_DATA4_12 | output | TCELL1:OUT.29.TMIN |
| TX_SERDES_DATA4_13 | output | TCELL1:OUT.31.TMIN |
| TX_SERDES_DATA4_14 | output | TCELL1:OUT.15.TMIN |
| TX_SERDES_DATA4_15 | output | TCELL1:OUT.17.TMIN |
| TX_SERDES_DATA4_16 | output | TCELL2:OUT.19.TMIN |
| TX_SERDES_DATA4_17 | output | TCELL2:OUT.21.TMIN |
| TX_SERDES_DATA4_18 | output | TCELL2:OUT.23.TMIN |
| TX_SERDES_DATA4_19 | output | TCELL2:OUT.25.TMIN |
| TX_SERDES_DATA4_2 | output | TCELL0:OUT.27.TMIN |
| TX_SERDES_DATA4_20 | output | TCELL2:OUT.27.TMIN |
| TX_SERDES_DATA4_21 | output | TCELL2:OUT.29.TMIN |
| TX_SERDES_DATA4_22 | output | TCELL2:OUT.31.TMIN |
| TX_SERDES_DATA4_23 | output | TCELL2:OUT.15.TMIN |
| TX_SERDES_DATA4_24 | output | TCELL3:OUT.17.TMIN |
| TX_SERDES_DATA4_25 | output | TCELL3:OUT.19.TMIN |
| TX_SERDES_DATA4_26 | output | TCELL3:OUT.21.TMIN |
| TX_SERDES_DATA4_27 | output | TCELL3:OUT.23.TMIN |
| TX_SERDES_DATA4_28 | output | TCELL3:OUT.25.TMIN |
| TX_SERDES_DATA4_29 | output | TCELL3:OUT.27.TMIN |
| TX_SERDES_DATA4_3 | output | TCELL0:OUT.29.TMIN |
| TX_SERDES_DATA4_30 | output | TCELL3:OUT.29.TMIN |
| TX_SERDES_DATA4_31 | output | TCELL3:OUT.31.TMIN |
| TX_SERDES_DATA4_4 | output | TCELL0:OUT.31.TMIN |
| TX_SERDES_DATA4_5 | output | TCELL0:OUT.15.TMIN |
| TX_SERDES_DATA4_6 | output | TCELL0:OUT.17.TMIN |
| TX_SERDES_DATA4_7 | output | TCELL0:OUT.19.TMIN |
| TX_SERDES_DATA4_8 | output | TCELL1:OUT.21.TMIN |
| TX_SERDES_DATA4_9 | output | TCELL1:OUT.23.TMIN |
| TX_SERDES_DATA5_0 | output | TCELL13:OUT.23.TMIN |
| TX_SERDES_DATA5_1 | output | TCELL13:OUT.25.TMIN |
| TX_SERDES_DATA5_10 | output | TCELL14:OUT.25.TMIN |
| TX_SERDES_DATA5_11 | output | TCELL14:OUT.27.TMIN |
| TX_SERDES_DATA5_12 | output | TCELL14:OUT.29.TMIN |
| TX_SERDES_DATA5_13 | output | TCELL14:OUT.31.TMIN |
| TX_SERDES_DATA5_14 | output | TCELL14:OUT.15.TMIN |
| TX_SERDES_DATA5_15 | output | TCELL14:OUT.17.TMIN |
| TX_SERDES_DATA5_16 | output | TCELL15:OUT.19.TMIN |
| TX_SERDES_DATA5_17 | output | TCELL15:OUT.21.TMIN |
| TX_SERDES_DATA5_18 | output | TCELL15:OUT.23.TMIN |
| TX_SERDES_DATA5_19 | output | TCELL15:OUT.25.TMIN |
| TX_SERDES_DATA5_2 | output | TCELL13:OUT.27.TMIN |
| TX_SERDES_DATA5_20 | output | TCELL15:OUT.27.TMIN |
| TX_SERDES_DATA5_21 | output | TCELL15:OUT.29.TMIN |
| TX_SERDES_DATA5_22 | output | TCELL15:OUT.31.TMIN |
| TX_SERDES_DATA5_23 | output | TCELL15:OUT.15.TMIN |
| TX_SERDES_DATA5_24 | output | TCELL16:OUT.17.TMIN |
| TX_SERDES_DATA5_25 | output | TCELL16:OUT.19.TMIN |
| TX_SERDES_DATA5_26 | output | TCELL16:OUT.21.TMIN |
| TX_SERDES_DATA5_27 | output | TCELL16:OUT.23.TMIN |
| TX_SERDES_DATA5_28 | output | TCELL16:OUT.25.TMIN |
| TX_SERDES_DATA5_29 | output | TCELL16:OUT.27.TMIN |
| TX_SERDES_DATA5_3 | output | TCELL13:OUT.29.TMIN |
| TX_SERDES_DATA5_30 | output | TCELL16:OUT.29.TMIN |
| TX_SERDES_DATA5_31 | output | TCELL16:OUT.31.TMIN |
| TX_SERDES_DATA5_4 | output | TCELL13:OUT.31.TMIN |
| TX_SERDES_DATA5_5 | output | TCELL13:OUT.15.TMIN |
| TX_SERDES_DATA5_6 | output | TCELL13:OUT.17.TMIN |
| TX_SERDES_DATA5_7 | output | TCELL13:OUT.19.TMIN |
| TX_SERDES_DATA5_8 | output | TCELL14:OUT.21.TMIN |
| TX_SERDES_DATA5_9 | output | TCELL14:OUT.23.TMIN |
| TX_SERDES_DATA6_0 | output | TCELL26:OUT.23.TMIN |
| TX_SERDES_DATA6_1 | output | TCELL26:OUT.25.TMIN |
| TX_SERDES_DATA6_10 | output | TCELL27:OUT.25.TMIN |
| TX_SERDES_DATA6_11 | output | TCELL27:OUT.27.TMIN |
| TX_SERDES_DATA6_12 | output | TCELL27:OUT.29.TMIN |
| TX_SERDES_DATA6_13 | output | TCELL27:OUT.31.TMIN |
| TX_SERDES_DATA6_14 | output | TCELL27:OUT.15.TMIN |
| TX_SERDES_DATA6_15 | output | TCELL27:OUT.17.TMIN |
| TX_SERDES_DATA6_16 | output | TCELL28:OUT.19.TMIN |
| TX_SERDES_DATA6_17 | output | TCELL28:OUT.21.TMIN |
| TX_SERDES_DATA6_18 | output | TCELL28:OUT.23.TMIN |
| TX_SERDES_DATA6_19 | output | TCELL28:OUT.25.TMIN |
| TX_SERDES_DATA6_2 | output | TCELL26:OUT.27.TMIN |
| TX_SERDES_DATA6_20 | output | TCELL28:OUT.27.TMIN |
| TX_SERDES_DATA6_21 | output | TCELL28:OUT.29.TMIN |
| TX_SERDES_DATA6_22 | output | TCELL28:OUT.31.TMIN |
| TX_SERDES_DATA6_23 | output | TCELL28:OUT.15.TMIN |
| TX_SERDES_DATA6_24 | output | TCELL29:OUT.17.TMIN |
| TX_SERDES_DATA6_25 | output | TCELL29:OUT.19.TMIN |
| TX_SERDES_DATA6_26 | output | TCELL29:OUT.21.TMIN |
| TX_SERDES_DATA6_27 | output | TCELL29:OUT.23.TMIN |
| TX_SERDES_DATA6_28 | output | TCELL29:OUT.25.TMIN |
| TX_SERDES_DATA6_29 | output | TCELL29:OUT.27.TMIN |
| TX_SERDES_DATA6_3 | output | TCELL26:OUT.29.TMIN |
| TX_SERDES_DATA6_30 | output | TCELL29:OUT.29.TMIN |
| TX_SERDES_DATA6_31 | output | TCELL29:OUT.31.TMIN |
| TX_SERDES_DATA6_4 | output | TCELL26:OUT.31.TMIN |
| TX_SERDES_DATA6_5 | output | TCELL26:OUT.15.TMIN |
| TX_SERDES_DATA6_6 | output | TCELL26:OUT.17.TMIN |
| TX_SERDES_DATA6_7 | output | TCELL26:OUT.19.TMIN |
| TX_SERDES_DATA6_8 | output | TCELL27:OUT.21.TMIN |
| TX_SERDES_DATA6_9 | output | TCELL27:OUT.23.TMIN |
| TX_SERDES_DATA7_0 | output | TCELL39:OUT.23.TMIN |
| TX_SERDES_DATA7_1 | output | TCELL39:OUT.25.TMIN |
| TX_SERDES_DATA7_10 | output | TCELL40:OUT.25.TMIN |
| TX_SERDES_DATA7_11 | output | TCELL40:OUT.27.TMIN |
| TX_SERDES_DATA7_12 | output | TCELL40:OUT.29.TMIN |
| TX_SERDES_DATA7_13 | output | TCELL40:OUT.31.TMIN |
| TX_SERDES_DATA7_14 | output | TCELL40:OUT.15.TMIN |
| TX_SERDES_DATA7_15 | output | TCELL40:OUT.17.TMIN |
| TX_SERDES_DATA7_16 | output | TCELL41:OUT.19.TMIN |
| TX_SERDES_DATA7_17 | output | TCELL41:OUT.21.TMIN |
| TX_SERDES_DATA7_18 | output | TCELL41:OUT.23.TMIN |
| TX_SERDES_DATA7_19 | output | TCELL41:OUT.25.TMIN |
| TX_SERDES_DATA7_2 | output | TCELL39:OUT.27.TMIN |
| TX_SERDES_DATA7_20 | output | TCELL41:OUT.27.TMIN |
| TX_SERDES_DATA7_21 | output | TCELL41:OUT.29.TMIN |
| TX_SERDES_DATA7_22 | output | TCELL41:OUT.31.TMIN |
| TX_SERDES_DATA7_23 | output | TCELL41:OUT.15.TMIN |
| TX_SERDES_DATA7_24 | output | TCELL42:OUT.17.TMIN |
| TX_SERDES_DATA7_25 | output | TCELL42:OUT.19.TMIN |
| TX_SERDES_DATA7_26 | output | TCELL42:OUT.21.TMIN |
| TX_SERDES_DATA7_27 | output | TCELL42:OUT.23.TMIN |
| TX_SERDES_DATA7_28 | output | TCELL42:OUT.25.TMIN |
| TX_SERDES_DATA7_29 | output | TCELL42:OUT.27.TMIN |
| TX_SERDES_DATA7_3 | output | TCELL39:OUT.29.TMIN |
| TX_SERDES_DATA7_30 | output | TCELL42:OUT.29.TMIN |
| TX_SERDES_DATA7_31 | output | TCELL42:OUT.31.TMIN |
| TX_SERDES_DATA7_4 | output | TCELL39:OUT.31.TMIN |
| TX_SERDES_DATA7_5 | output | TCELL39:OUT.15.TMIN |
| TX_SERDES_DATA7_6 | output | TCELL39:OUT.17.TMIN |
| TX_SERDES_DATA7_7 | output | TCELL39:OUT.19.TMIN |
| TX_SERDES_DATA7_8 | output | TCELL40:OUT.21.TMIN |
| TX_SERDES_DATA7_9 | output | TCELL40:OUT.23.TMIN |
| TX_SERDES_DATA8_0 | output | TCELL52:OUT.17.TMIN |
| TX_SERDES_DATA8_1 | output | TCELL52:OUT.19.TMIN |
| TX_SERDES_DATA8_10 | output | TCELL53:OUT.19.TMIN |
| TX_SERDES_DATA8_11 | output | TCELL53:OUT.21.TMIN |
| TX_SERDES_DATA8_12 | output | TCELL53:OUT.23.TMIN |
| TX_SERDES_DATA8_13 | output | TCELL53:OUT.25.TMIN |
| TX_SERDES_DATA8_14 | output | TCELL53:OUT.27.TMIN |
| TX_SERDES_DATA8_15 | output | TCELL53:OUT.29.TMIN |
| TX_SERDES_DATA8_16 | output | TCELL54:OUT.31.TMIN |
| TX_SERDES_DATA8_17 | output | TCELL54:OUT.15.TMIN |
| TX_SERDES_DATA8_18 | output | TCELL54:OUT.17.TMIN |
| TX_SERDES_DATA8_19 | output | TCELL54:OUT.19.TMIN |
| TX_SERDES_DATA8_2 | output | TCELL52:OUT.21.TMIN |
| TX_SERDES_DATA8_20 | output | TCELL54:OUT.21.TMIN |
| TX_SERDES_DATA8_21 | output | TCELL54:OUT.23.TMIN |
| TX_SERDES_DATA8_22 | output | TCELL54:OUT.25.TMIN |
| TX_SERDES_DATA8_23 | output | TCELL54:OUT.27.TMIN |
| TX_SERDES_DATA8_24 | output | TCELL55:OUT.29.TMIN |
| TX_SERDES_DATA8_25 | output | TCELL55:OUT.31.TMIN |
| TX_SERDES_DATA8_26 | output | TCELL55:OUT.15.TMIN |
| TX_SERDES_DATA8_27 | output | TCELL55:OUT.17.TMIN |
| TX_SERDES_DATA8_28 | output | TCELL55:OUT.19.TMIN |
| TX_SERDES_DATA8_29 | output | TCELL55:OUT.21.TMIN |
| TX_SERDES_DATA8_3 | output | TCELL52:OUT.23.TMIN |
| TX_SERDES_DATA8_30 | output | TCELL55:OUT.23.TMIN |
| TX_SERDES_DATA8_31 | output | TCELL55:OUT.25.TMIN |
| TX_SERDES_DATA8_4 | output | TCELL52:OUT.25.TMIN |
| TX_SERDES_DATA8_5 | output | TCELL52:OUT.27.TMIN |
| TX_SERDES_DATA8_6 | output | TCELL52:OUT.29.TMIN |
| TX_SERDES_DATA8_7 | output | TCELL52:OUT.31.TMIN |
| TX_SERDES_DATA8_8 | output | TCELL53:OUT.15.TMIN |
| TX_SERDES_DATA8_9 | output | TCELL53:OUT.17.TMIN |
| TX_SERDES_DATA9_0 | output | TCELL56:OUT.17.TMIN |
| TX_SERDES_DATA9_1 | output | TCELL56:OUT.19.TMIN |
| TX_SERDES_DATA9_10 | output | TCELL57:OUT.19.TMIN |
| TX_SERDES_DATA9_11 | output | TCELL57:OUT.21.TMIN |
| TX_SERDES_DATA9_12 | output | TCELL57:OUT.23.TMIN |
| TX_SERDES_DATA9_13 | output | TCELL57:OUT.25.TMIN |
| TX_SERDES_DATA9_14 | output | TCELL57:OUT.27.TMIN |
| TX_SERDES_DATA9_15 | output | TCELL57:OUT.29.TMIN |
| TX_SERDES_DATA9_16 | output | TCELL58:OUT.31.TMIN |
| TX_SERDES_DATA9_17 | output | TCELL58:OUT.15.TMIN |
| TX_SERDES_DATA9_18 | output | TCELL58:OUT.17.TMIN |
| TX_SERDES_DATA9_19 | output | TCELL58:OUT.19.TMIN |
| TX_SERDES_DATA9_2 | output | TCELL56:OUT.21.TMIN |
| TX_SERDES_DATA9_20 | output | TCELL58:OUT.21.TMIN |
| TX_SERDES_DATA9_21 | output | TCELL58:OUT.23.TMIN |
| TX_SERDES_DATA9_22 | output | TCELL58:OUT.25.TMIN |
| TX_SERDES_DATA9_23 | output | TCELL58:OUT.27.TMIN |
| TX_SERDES_DATA9_24 | output | TCELL59:OUT.29.TMIN |
| TX_SERDES_DATA9_25 | output | TCELL59:OUT.31.TMIN |
| TX_SERDES_DATA9_26 | output | TCELL59:OUT.15.TMIN |
| TX_SERDES_DATA9_27 | output | TCELL59:OUT.17.TMIN |
| TX_SERDES_DATA9_28 | output | TCELL59:OUT.19.TMIN |
| TX_SERDES_DATA9_29 | output | TCELL59:OUT.21.TMIN |
| TX_SERDES_DATA9_3 | output | TCELL56:OUT.23.TMIN |
| TX_SERDES_DATA9_30 | output | TCELL59:OUT.23.TMIN |
| TX_SERDES_DATA9_31 | output | TCELL59:OUT.25.TMIN |
| TX_SERDES_DATA9_4 | output | TCELL56:OUT.25.TMIN |
| TX_SERDES_DATA9_5 | output | TCELL56:OUT.27.TMIN |
| TX_SERDES_DATA9_6 | output | TCELL56:OUT.29.TMIN |
| TX_SERDES_DATA9_7 | output | TCELL56:OUT.31.TMIN |
| TX_SERDES_DATA9_8 | output | TCELL57:OUT.15.TMIN |
| TX_SERDES_DATA9_9 | output | TCELL57:OUT.17.TMIN |
| TX_SOPIN0 | input | TCELL62:IMUX.IMUX.24.DELAY |
| TX_SOPIN1 | input | TCELL70:IMUX.IMUX.24.DELAY |
| TX_SOPIN2 | input | TCELL78:IMUX.IMUX.24.DELAY |
| TX_SOPIN3 | input | TCELL86:IMUX.IMUX.24.DELAY |
| TX_UNFOUT | output | TCELL67:OUT.3.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:OUT.0.TMIN | CMAC.STAT_RX_MF_ERR0 |
| TCELL0:OUT.2.TMIN | CMAC.STAT_RX_MF_ERR1 |
| TCELL0:OUT.4.TMIN | CMAC.STAT_RX_MF_ERR2 |
| TCELL0:OUT.6.TMIN | CMAC.STAT_RX_MF_ERR3 |
| TCELL0:OUT.8.TMIN | CMAC.STAT_RX_MF_ERR4 |
| TCELL0:OUT.10.TMIN | CMAC.STAT_RX_MF_ERR5 |
| TCELL0:OUT.12.TMIN | CMAC.STAT_RX_MF_ERR6 |
| TCELL0:OUT.14.TMIN | CMAC.STAT_RX_MF_ERR7 |
| TCELL0:OUT.15.TMIN | CMAC.TX_SERDES_DATA4_5 |
| TCELL0:OUT.17.TMIN | CMAC.TX_SERDES_DATA4_6 |
| TCELL0:OUT.19.TMIN | CMAC.TX_SERDES_DATA4_7 |
| TCELL0:OUT.23.TMIN | CMAC.TX_SERDES_DATA4_0 |
| TCELL0:OUT.25.TMIN | CMAC.TX_SERDES_DATA4_1 |
| TCELL0:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR0 |
| TCELL0:OUT.27.TMIN | CMAC.TX_SERDES_DATA4_2 |
| TCELL0:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC159 |
| TCELL0:OUT.29.TMIN | CMAC.TX_SERDES_DATA4_3 |
| TCELL0:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR0 |
| TCELL0:OUT.31.TMIN | CMAC.TX_SERDES_DATA4_4 |
| TCELL0:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC0 |
| TCELL0:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA4_0 |
| TCELL0:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA4_1 |
| TCELL0:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA4_2 |
| TCELL0:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA4_3 |
| TCELL0:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA4_4 |
| TCELL0:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA4_5 |
| TCELL0:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC56 |
| TCELL0:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA4_6 |
| TCELL0:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA4_7 |
| TCELL0:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC112 |
| TCELL0:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC168 |
| TCELL1:OUT.0.TMIN | CMAC.STAT_RX_MF_ERR8 |
| TCELL1:OUT.2.TMIN | CMAC.STAT_RX_MF_ERR9 |
| TCELL1:OUT.4.TMIN | CMAC.STAT_RX_MF_ERR10 |
| TCELL1:OUT.6.TMIN | CMAC.STAT_RX_MF_ERR11 |
| TCELL1:OUT.8.TMIN | CMAC.STAT_RX_MF_ERR12 |
| TCELL1:OUT.10.TMIN | CMAC.STAT_RX_MF_ERR13 |
| TCELL1:OUT.12.TMIN | CMAC.STAT_RX_MF_ERR14 |
| TCELL1:OUT.14.TMIN | CMAC.STAT_RX_MF_ERR15 |
| TCELL1:OUT.15.TMIN | CMAC.TX_SERDES_DATA4_14 |
| TCELL1:OUT.16.TMIN | CMAC.STAT_RX_ALIGNED |
| TCELL1:OUT.17.TMIN | CMAC.TX_SERDES_DATA4_15 |
| TCELL1:OUT.21.TMIN | CMAC.TX_SERDES_DATA4_8 |
| TCELL1:OUT.23.TMIN | CMAC.TX_SERDES_DATA4_9 |
| TCELL1:OUT.25.TMIN | CMAC.TX_SERDES_DATA4_10 |
| TCELL1:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR1 |
| TCELL1:OUT.27.TMIN | CMAC.TX_SERDES_DATA4_11 |
| TCELL1:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC158 |
| TCELL1:OUT.29.TMIN | CMAC.TX_SERDES_DATA4_12 |
| TCELL1:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR1 |
| TCELL1:OUT.31.TMIN | CMAC.TX_SERDES_DATA4_13 |
| TCELL1:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC1 |
| TCELL1:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA4_8 |
| TCELL1:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA4_9 |
| TCELL1:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA4_10 |
| TCELL1:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA4_11 |
| TCELL1:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA4_12 |
| TCELL1:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA4_13 |
| TCELL1:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC57 |
| TCELL1:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA4_14 |
| TCELL1:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA4_15 |
| TCELL1:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_TAG_FIELD_IN0 |
| TCELL1:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_TAG_FIELD_IN1 |
| TCELL1:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC113 |
| TCELL1:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_TAG_FIELD_IN2 |
| TCELL1:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_TAG_FIELD_IN3 |
| TCELL1:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_TAG_FIELD_IN4 |
| TCELL1:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_TAG_FIELD_IN5 |
| TCELL1:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_TAG_FIELD_IN6 |
| TCELL1:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC169 |
| TCELL1:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_TAG_FIELD_IN7 |
| TCELL2:OUT.0.TMIN | CMAC.STAT_RX_MF_ERR16 |
| TCELL2:OUT.2.TMIN | CMAC.STAT_RX_MF_ERR17 |
| TCELL2:OUT.4.TMIN | CMAC.STAT_RX_MF_ERR18 |
| TCELL2:OUT.6.TMIN | CMAC.STAT_RX_MF_ERR19 |
| TCELL2:OUT.8.TMIN | CMAC.STAT_RX_LOCAL_FAULT |
| TCELL2:OUT.10.TMIN | CMAC.STAT_RX_JABBER |
| TCELL2:OUT.12.TMIN | CMAC.STAT_RX_INTERNAL_LOCAL_FAULT |
| TCELL2:OUT.14.TMIN | CMAC.STAT_RX_HI_BER |
| TCELL2:OUT.15.TMIN | CMAC.TX_SERDES_DATA4_23 |
| TCELL2:OUT.16.TMIN | CMAC.STAT_RX_ALIGNED_ERR |
| TCELL2:OUT.19.TMIN | CMAC.TX_SERDES_DATA4_16 |
| TCELL2:OUT.21.TMIN | CMAC.TX_SERDES_DATA4_17 |
| TCELL2:OUT.23.TMIN | CMAC.TX_SERDES_DATA4_18 |
| TCELL2:OUT.25.TMIN | CMAC.TX_SERDES_DATA4_19 |
| TCELL2:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR2 |
| TCELL2:OUT.27.TMIN | CMAC.TX_SERDES_DATA4_20 |
| TCELL2:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC157 |
| TCELL2:OUT.29.TMIN | CMAC.TX_SERDES_DATA4_21 |
| TCELL2:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR2 |
| TCELL2:OUT.31.TMIN | CMAC.TX_SERDES_DATA4_22 |
| TCELL2:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC2 |
| TCELL2:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA4_16 |
| TCELL2:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA4_17 |
| TCELL2:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA4_18 |
| TCELL2:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA4_19 |
| TCELL2:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA4_20 |
| TCELL2:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA4_21 |
| TCELL2:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC58 |
| TCELL2:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA4_22 |
| TCELL2:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA4_23 |
| TCELL2:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_TAG_FIELD_IN8 |
| TCELL2:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_TAG_FIELD_IN9 |
| TCELL2:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC114 |
| TCELL2:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_TAG_FIELD_IN10 |
| TCELL2:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_TAG_FIELD_IN11 |
| TCELL2:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_TAG_FIELD_IN12 |
| TCELL2:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_TAG_FIELD_IN13 |
| TCELL2:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_TAG_FIELD_IN14 |
| TCELL2:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC170 |
| TCELL2:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_TAG_FIELD_IN15 |
| TCELL3:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_VALID0 |
| TCELL3:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_VALID1 |
| TCELL3:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_VALID2 |
| TCELL3:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_VALID3 |
| TCELL3:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_VALID4 |
| TCELL3:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_VALID5 |
| TCELL3:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_VALID6 |
| TCELL3:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_VALID7 |
| TCELL3:OUT.16.TMIN | CMAC.STAT_RX_PAUSE_VALID8 |
| TCELL3:OUT.17.TMIN | CMAC.TX_SERDES_DATA4_24 |
| TCELL3:OUT.19.TMIN | CMAC.TX_SERDES_DATA4_25 |
| TCELL3:OUT.21.TMIN | CMAC.TX_SERDES_DATA4_26 |
| TCELL3:OUT.23.TMIN | CMAC.TX_SERDES_DATA4_27 |
| TCELL3:OUT.25.TMIN | CMAC.TX_SERDES_DATA4_28 |
| TCELL3:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR3 |
| TCELL3:OUT.27.TMIN | CMAC.TX_SERDES_DATA4_29 |
| TCELL3:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC156 |
| TCELL3:OUT.29.TMIN | CMAC.TX_SERDES_DATA4_30 |
| TCELL3:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR3 |
| TCELL3:OUT.31.TMIN | CMAC.TX_SERDES_DATA4_31 |
| TCELL3:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC3 |
| TCELL3:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA4_24 |
| TCELL3:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA4_25 |
| TCELL3:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA4_26 |
| TCELL3:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA4_27 |
| TCELL3:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA4_28 |
| TCELL3:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA4_29 |
| TCELL3:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC59 |
| TCELL3:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA4_30 |
| TCELL3:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA4_31 |
| TCELL3:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN0 |
| TCELL3:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN1 |
| TCELL3:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC115 |
| TCELL3:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN2 |
| TCELL3:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN3 |
| TCELL3:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN4 |
| TCELL3:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN5 |
| TCELL3:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN6 |
| TCELL3:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC171 |
| TCELL3:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN7 |
| TCELL4:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_REQ8 |
| TCELL4:OUT.2.TMIN | CMAC.STAT_RX_USER_PAUSE |
| TCELL4:OUT.4.TMIN | CMAC.STAT_RX_PAUSE |
| TCELL4:OUT.6.TMIN | CMAC.STAT_RX_INRANGEERR |
| TCELL4:OUT.8.TMIN | CMAC.STAT_RX_UNDERSIZE0 |
| TCELL4:OUT.10.TMIN | CMAC.STAT_RX_UNDERSIZE1 |
| TCELL4:OUT.12.TMIN | CMAC.STAT_RX_UNDERSIZE2 |
| TCELL4:OUT.14.TMIN | CMAC.STAT_RX_UNDERSIZE3 |
| TCELL4:OUT.16.TMIN | CMAC.STAT_RX_GOT_SIGNAL_OS |
| TCELL4:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_0 |
| TCELL4:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_1 |
| TCELL4:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_2 |
| TCELL4:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_3 |
| TCELL4:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_4 |
| TCELL4:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR4 |
| TCELL4:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_5 |
| TCELL4:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC155 |
| TCELL4:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_6 |
| TCELL4:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR4 |
| TCELL4:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_7 |
| TCELL4:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC4 |
| TCELL4:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_0 |
| TCELL4:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_1 |
| TCELL4:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_2 |
| TCELL4:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_3 |
| TCELL4:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_4 |
| TCELL4:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_5 |
| TCELL4:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC60 |
| TCELL4:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_6 |
| TCELL4:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_7 |
| TCELL4:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN8 |
| TCELL4:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN9 |
| TCELL4:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC116 |
| TCELL4:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN10 |
| TCELL4:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN11 |
| TCELL4:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN12 |
| TCELL4:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN13 |
| TCELL4:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN14 |
| TCELL4:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC172 |
| TCELL4:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_TSTAMP_OFFSET_IN15 |
| TCELL5:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_REQ0 |
| TCELL5:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_REQ1 |
| TCELL5:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_REQ2 |
| TCELL5:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_REQ3 |
| TCELL5:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_REQ4 |
| TCELL5:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_REQ5 |
| TCELL5:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_REQ6 |
| TCELL5:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_REQ7 |
| TCELL5:OUT.15.TMIN | CMAC.TX_SERDES_ALT_DATA0_0 |
| TCELL5:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA0_1 |
| TCELL5:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_8 |
| TCELL5:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_9 |
| TCELL5:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_10 |
| TCELL5:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_11 |
| TCELL5:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR5 |
| TCELL5:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_12 |
| TCELL5:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC154 |
| TCELL5:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_13 |
| TCELL5:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR5 |
| TCELL5:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_14 |
| TCELL5:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC5 |
| TCELL5:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_ALT_DATA0_0 |
| TCELL5:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA0_1 |
| TCELL5:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_8 |
| TCELL5:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_9 |
| TCELL5:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_10 |
| TCELL5:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_11 |
| TCELL5:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC61 |
| TCELL5:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_12 |
| TCELL5:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_13 |
| TCELL5:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_14 |
| TCELL5:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN0 |
| TCELL5:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN1 |
| TCELL5:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC117 |
| TCELL5:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN2 |
| TCELL5:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN3 |
| TCELL5:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN4 |
| TCELL5:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN5 |
| TCELL5:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN6 |
| TCELL5:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC173 |
| TCELL5:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN7 |
| TCELL6:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_0_0 |
| TCELL6:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_0_1 |
| TCELL6:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_0_2 |
| TCELL6:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_0_3 |
| TCELL6:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_0_4 |
| TCELL6:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_1_0 |
| TCELL6:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_1_1 |
| TCELL6:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_1_2 |
| TCELL6:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_15 |
| TCELL6:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_1_3 |
| TCELL6:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA0_2 |
| TCELL6:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_1_4 |
| TCELL6:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA0_3 |
| TCELL6:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_16 |
| TCELL6:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_17 |
| TCELL6:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_18 |
| TCELL6:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR6 |
| TCELL6:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_19 |
| TCELL6:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC153 |
| TCELL6:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_20 |
| TCELL6:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR6 |
| TCELL6:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_21 |
| TCELL6:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC6 |
| TCELL6:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_15 |
| TCELL6:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA0_2 |
| TCELL6:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA0_3 |
| TCELL6:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_16 |
| TCELL6:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_17 |
| TCELL6:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_18 |
| TCELL6:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC62 |
| TCELL6:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_19 |
| TCELL6:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_20 |
| TCELL6:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_21 |
| TCELL6:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN8 |
| TCELL6:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN9 |
| TCELL6:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC118 |
| TCELL6:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN10 |
| TCELL6:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN11 |
| TCELL6:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN12 |
| TCELL6:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN13 |
| TCELL6:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN14 |
| TCELL6:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC174 |
| TCELL6:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN15 |
| TCELL7:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_2_0 |
| TCELL7:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_2_1 |
| TCELL7:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_2_2 |
| TCELL7:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_2_3 |
| TCELL7:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_2_4 |
| TCELL7:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_3_0 |
| TCELL7:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_3_1 |
| TCELL7:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_3_2 |
| TCELL7:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_22 |
| TCELL7:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_3_3 |
| TCELL7:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_23 |
| TCELL7:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_3_4 |
| TCELL7:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA0_4 |
| TCELL7:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA0_5 |
| TCELL7:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_24 |
| TCELL7:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_25 |
| TCELL7:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR7 |
| TCELL7:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_26 |
| TCELL7:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC152 |
| TCELL7:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_27 |
| TCELL7:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR7 |
| TCELL7:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_28 |
| TCELL7:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC7 |
| TCELL7:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_22 |
| TCELL7:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_23 |
| TCELL7:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA0_4 |
| TCELL7:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA0_5 |
| TCELL7:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_24 |
| TCELL7:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_25 |
| TCELL7:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC63 |
| TCELL7:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_26 |
| TCELL7:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_27 |
| TCELL7:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_28 |
| TCELL7:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN16 |
| TCELL7:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN17 |
| TCELL7:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC119 |
| TCELL7:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN18 |
| TCELL7:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN19 |
| TCELL7:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN20 |
| TCELL7:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN21 |
| TCELL7:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN22 |
| TCELL7:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC175 |
| TCELL7:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN23 |
| TCELL8:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_4_0 |
| TCELL8:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_4_1 |
| TCELL8:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_4_2 |
| TCELL8:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_4_3 |
| TCELL8:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_4_4 |
| TCELL8:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_5_0 |
| TCELL8:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_5_1 |
| TCELL8:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_5_2 |
| TCELL8:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_29 |
| TCELL8:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_5_3 |
| TCELL8:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_30 |
| TCELL8:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_5_4 |
| TCELL8:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_31 |
| TCELL8:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA0_6 |
| TCELL8:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA0_7 |
| TCELL8:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_32 |
| TCELL8:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR8 |
| TCELL8:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_33 |
| TCELL8:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC151 |
| TCELL8:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_34 |
| TCELL8:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR8 |
| TCELL8:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_35 |
| TCELL8:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC8 |
| TCELL8:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_29 |
| TCELL8:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_30 |
| TCELL8:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_31 |
| TCELL8:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA0_6 |
| TCELL8:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA0_7 |
| TCELL8:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_32 |
| TCELL8:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC64 |
| TCELL8:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_33 |
| TCELL8:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_34 |
| TCELL8:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_35 |
| TCELL8:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN24 |
| TCELL8:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN25 |
| TCELL8:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC120 |
| TCELL8:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN26 |
| TCELL8:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN27 |
| TCELL8:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN28 |
| TCELL8:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN29 |
| TCELL8:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN30 |
| TCELL8:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC176 |
| TCELL8:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN31 |
| TCELL9:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_6_0 |
| TCELL9:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_6_1 |
| TCELL9:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_6_2 |
| TCELL9:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_6_3 |
| TCELL9:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_6_4 |
| TCELL9:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_7_0 |
| TCELL9:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_7_1 |
| TCELL9:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_7_2 |
| TCELL9:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_36 |
| TCELL9:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_7_3 |
| TCELL9:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_37 |
| TCELL9:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_7_4 |
| TCELL9:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_38 |
| TCELL9:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_39 |
| TCELL9:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA0_8 |
| TCELL9:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA0_9 |
| TCELL9:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR9 |
| TCELL9:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_40 |
| TCELL9:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC150 |
| TCELL9:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_41 |
| TCELL9:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR9 |
| TCELL9:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_42 |
| TCELL9:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC9 |
| TCELL9:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_36 |
| TCELL9:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_37 |
| TCELL9:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_38 |
| TCELL9:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_39 |
| TCELL9:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA0_8 |
| TCELL9:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA0_9 |
| TCELL9:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC65 |
| TCELL9:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_40 |
| TCELL9:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_41 |
| TCELL9:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_42 |
| TCELL9:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN32 |
| TCELL9:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN33 |
| TCELL9:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC121 |
| TCELL9:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN34 |
| TCELL9:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN35 |
| TCELL9:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN36 |
| TCELL9:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN37 |
| TCELL9:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN38 |
| TCELL9:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC177 |
| TCELL9:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN39 |
| TCELL10:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_8_0 |
| TCELL10:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_8_1 |
| TCELL10:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_8_2 |
| TCELL10:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_8_3 |
| TCELL10:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_8_4 |
| TCELL10:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_9_0 |
| TCELL10:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_9_1 |
| TCELL10:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_9_2 |
| TCELL10:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_43 |
| TCELL10:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_9_3 |
| TCELL10:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_44 |
| TCELL10:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_9_4 |
| TCELL10:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_45 |
| TCELL10:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_46 |
| TCELL10:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_47 |
| TCELL10:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA0_10 |
| TCELL10:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR10 |
| TCELL10:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA0_11 |
| TCELL10:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC149 |
| TCELL10:OUT.29.TMIN | CMAC.TX_SERDES_DATA0_48 |
| TCELL10:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR10 |
| TCELL10:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_49 |
| TCELL10:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC10 |
| TCELL10:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_43 |
| TCELL10:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_44 |
| TCELL10:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_45 |
| TCELL10:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_46 |
| TCELL10:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_47 |
| TCELL10:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA0_10 |
| TCELL10:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC66 |
| TCELL10:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA0_11 |
| TCELL10:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA0_48 |
| TCELL10:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_49 |
| TCELL10:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN40 |
| TCELL10:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN41 |
| TCELL10:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC122 |
| TCELL10:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN42 |
| TCELL10:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN43 |
| TCELL10:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN44 |
| TCELL10:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN45 |
| TCELL10:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN46 |
| TCELL10:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC178 |
| TCELL10:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN47 |
| TCELL11:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_10_0 |
| TCELL11:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_10_1 |
| TCELL11:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_10_2 |
| TCELL11:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_10_3 |
| TCELL11:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_10_4 |
| TCELL11:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_11_0 |
| TCELL11:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_11_1 |
| TCELL11:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_11_2 |
| TCELL11:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_50 |
| TCELL11:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_11_3 |
| TCELL11:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_51 |
| TCELL11:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_11_4 |
| TCELL11:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_52 |
| TCELL11:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_53 |
| TCELL11:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_54 |
| TCELL11:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_55 |
| TCELL11:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR11 |
| TCELL11:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA0_12 |
| TCELL11:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC148 |
| TCELL11:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA0_13 |
| TCELL11:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR11 |
| TCELL11:OUT.31.TMIN | CMAC.TX_SERDES_DATA0_56 |
| TCELL11:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC11 |
| TCELL11:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_50 |
| TCELL11:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_51 |
| TCELL11:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_52 |
| TCELL11:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_53 |
| TCELL11:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_54 |
| TCELL11:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_55 |
| TCELL11:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC67 |
| TCELL11:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA0_12 |
| TCELL11:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA0_13 |
| TCELL11:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA0_56 |
| TCELL11:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN48 |
| TCELL11:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN49 |
| TCELL11:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC123 |
| TCELL11:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN50 |
| TCELL11:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN51 |
| TCELL11:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN52 |
| TCELL11:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN53 |
| TCELL11:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN54 |
| TCELL11:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC179 |
| TCELL11:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN55 |
| TCELL12:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_12_0 |
| TCELL12:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_12_1 |
| TCELL12:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_12_2 |
| TCELL12:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_12_3 |
| TCELL12:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_12_4 |
| TCELL12:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_13_0 |
| TCELL12:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_13_1 |
| TCELL12:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_13_2 |
| TCELL12:OUT.15.TMIN | CMAC.TX_SERDES_DATA0_57 |
| TCELL12:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_13_3 |
| TCELL12:OUT.17.TMIN | CMAC.TX_SERDES_DATA0_58 |
| TCELL12:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_13_4 |
| TCELL12:OUT.19.TMIN | CMAC.TX_SERDES_DATA0_59 |
| TCELL12:OUT.21.TMIN | CMAC.TX_SERDES_DATA0_60 |
| TCELL12:OUT.23.TMIN | CMAC.TX_SERDES_DATA0_61 |
| TCELL12:OUT.25.TMIN | CMAC.TX_SERDES_DATA0_62 |
| TCELL12:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR12 |
| TCELL12:OUT.27.TMIN | CMAC.TX_SERDES_DATA0_63 |
| TCELL12:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC147 |
| TCELL12:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA0_14 |
| TCELL12:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR12 |
| TCELL12:OUT.31.TMIN | CMAC.TX_SERDES_ALT_DATA0_15 |
| TCELL12:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC12 |
| TCELL12:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA0_57 |
| TCELL12:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA0_58 |
| TCELL12:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA0_59 |
| TCELL12:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA0_60 |
| TCELL12:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA0_61 |
| TCELL12:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA0_62 |
| TCELL12:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC68 |
| TCELL12:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA0_63 |
| TCELL12:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA0_14 |
| TCELL12:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_ALT_DATA0_15 |
| TCELL12:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_RXTSTAMP_IN56 |
| TCELL12:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_RXTSTAMP_IN57 |
| TCELL12:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC124 |
| TCELL12:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_RXTSTAMP_IN58 |
| TCELL12:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_RXTSTAMP_IN59 |
| TCELL12:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_RXTSTAMP_IN60 |
| TCELL12:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_RXTSTAMP_IN61 |
| TCELL12:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_RXTSTAMP_IN62 |
| TCELL12:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC180 |
| TCELL12:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_RXTSTAMP_IN63 |
| TCELL13:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_14_0 |
| TCELL13:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_14_1 |
| TCELL13:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_14_2 |
| TCELL13:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_14_3 |
| TCELL13:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_14_4 |
| TCELL13:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_15_0 |
| TCELL13:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_15_1 |
| TCELL13:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_15_2 |
| TCELL13:OUT.15.TMIN | CMAC.TX_SERDES_DATA5_5 |
| TCELL13:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_15_3 |
| TCELL13:OUT.17.TMIN | CMAC.TX_SERDES_DATA5_6 |
| TCELL13:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_15_4 |
| TCELL13:OUT.19.TMIN | CMAC.TX_SERDES_DATA5_7 |
| TCELL13:OUT.23.TMIN | CMAC.TX_SERDES_DATA5_0 |
| TCELL13:OUT.25.TMIN | CMAC.TX_SERDES_DATA5_1 |
| TCELL13:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR13 |
| TCELL13:OUT.27.TMIN | CMAC.TX_SERDES_DATA5_2 |
| TCELL13:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC146 |
| TCELL13:OUT.29.TMIN | CMAC.TX_SERDES_DATA5_3 |
| TCELL13:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR13 |
| TCELL13:OUT.31.TMIN | CMAC.TX_SERDES_DATA5_4 |
| TCELL13:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC13 |
| TCELL13:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA5_7 |
| TCELL13:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA5_0 |
| TCELL13:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA5_1 |
| TCELL13:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA5_2 |
| TCELL13:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA5_3 |
| TCELL13:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC69 |
| TCELL13:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA5_4 |
| TCELL13:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA5_5 |
| TCELL13:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA5_6 |
| TCELL13:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN0 |
| TCELL13:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN1 |
| TCELL13:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC125 |
| TCELL13:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN2 |
| TCELL13:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN3 |
| TCELL13:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN4 |
| TCELL13:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN5 |
| TCELL13:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN6 |
| TCELL13:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_CMAC181 |
| TCELL13:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN7 |
| TCELL14:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_16_0 |
| TCELL14:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_16_1 |
| TCELL14:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_16_2 |
| TCELL14:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_16_3 |
| TCELL14:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_16_4 |
| TCELL14:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_17_0 |
| TCELL14:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_17_1 |
| TCELL14:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_17_2 |
| TCELL14:OUT.15.TMIN | CMAC.TX_SERDES_DATA5_14 |
| TCELL14:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_17_3 |
| TCELL14:OUT.17.TMIN | CMAC.TX_SERDES_DATA5_15 |
| TCELL14:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_17_4 |
| TCELL14:OUT.21.TMIN | CMAC.TX_SERDES_DATA5_8 |
| TCELL14:OUT.23.TMIN | CMAC.TX_SERDES_DATA5_9 |
| TCELL14:OUT.25.TMIN | CMAC.TX_SERDES_DATA5_10 |
| TCELL14:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR14 |
| TCELL14:OUT.27.TMIN | CMAC.TX_SERDES_DATA5_11 |
| TCELL14:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC145 |
| TCELL14:OUT.29.TMIN | CMAC.TX_SERDES_DATA5_12 |
| TCELL14:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR14 |
| TCELL14:OUT.31.TMIN | CMAC.TX_SERDES_DATA5_13 |
| TCELL14:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC14 |
| TCELL14:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA5_8 |
| TCELL14:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA5_9 |
| TCELL14:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA5_10 |
| TCELL14:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA5_11 |
| TCELL14:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA5_12 |
| TCELL14:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC70 |
| TCELL14:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA5_13 |
| TCELL14:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA5_14 |
| TCELL14:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA5_15 |
| TCELL14:IMUX.IMUX.26.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN8 |
| TCELL14:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN9 |
| TCELL14:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC126 |
| TCELL14:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN10 |
| TCELL14:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN11 |
| TCELL14:IMUX.IMUX.38.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN12 |
| TCELL14:IMUX.IMUX.41.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN13 |
| TCELL14:IMUX.IMUX.44.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN14 |
| TCELL14:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL0 |
| TCELL14:IMUX.IMUX.47.DELAY | CMAC.TX_PTP_CHKSUM_OFFSET_IN15 |
| TCELL15:OUT.0.TMIN | CMAC.STAT_RX_VL_NUMBER_18_0 |
| TCELL15:OUT.2.TMIN | CMAC.STAT_RX_VL_NUMBER_18_1 |
| TCELL15:OUT.4.TMIN | CMAC.STAT_RX_VL_NUMBER_18_2 |
| TCELL15:OUT.6.TMIN | CMAC.STAT_RX_VL_NUMBER_18_3 |
| TCELL15:OUT.8.TMIN | CMAC.STAT_RX_VL_NUMBER_18_4 |
| TCELL15:OUT.10.TMIN | CMAC.STAT_RX_VL_NUMBER_19_0 |
| TCELL15:OUT.12.TMIN | CMAC.STAT_RX_VL_NUMBER_19_1 |
| TCELL15:OUT.14.TMIN | CMAC.STAT_RX_VL_NUMBER_19_2 |
| TCELL15:OUT.15.TMIN | CMAC.TX_SERDES_DATA5_23 |
| TCELL15:OUT.16.TMIN | CMAC.STAT_RX_VL_NUMBER_19_3 |
| TCELL15:OUT.18.TMIN | CMAC.STAT_RX_VL_NUMBER_19_4 |
| TCELL15:OUT.19.TMIN | CMAC.TX_SERDES_DATA5_16 |
| TCELL15:OUT.21.TMIN | CMAC.TX_SERDES_DATA5_17 |
| TCELL15:OUT.23.TMIN | CMAC.TX_SERDES_DATA5_18 |
| TCELL15:OUT.25.TMIN | CMAC.TX_SERDES_DATA5_19 |
| TCELL15:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR15 |
| TCELL15:OUT.27.TMIN | CMAC.TX_SERDES_DATA5_20 |
| TCELL15:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC144 |
| TCELL15:OUT.29.TMIN | CMAC.TX_SERDES_DATA5_21 |
| TCELL15:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR15 |
| TCELL15:OUT.31.TMIN | CMAC.TX_SERDES_DATA5_22 |
| TCELL15:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC15 |
| TCELL15:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA5_21 |
| TCELL15:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA5_22 |
| TCELL15:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA5_23 |
| TCELL15:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA5_16 |
| TCELL15:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA5_17 |
| TCELL15:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC71 |
| TCELL15:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA5_18 |
| TCELL15:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA5_19 |
| TCELL15:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA5_20 |
| TCELL15:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_PAUSE_ENABLE8 |
| TCELL15:IMUX.IMUX.29.DELAY | CMAC.TX_PTP_UPD_CHKSUM_IN |
| TCELL15:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC127 |
| TCELL15:IMUX.IMUX.32.DELAY | CMAC.TX_PTP_1588OP_IN0 |
| TCELL15:IMUX.IMUX.35.DELAY | CMAC.TX_PTP_1588OP_IN1 |
| TCELL15:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_PTP_VLANE_ADJUST_MODE |
| TCELL15:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL1 |
| TCELL16:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_8 |
| TCELL16:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_9 |
| TCELL16:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_10 |
| TCELL16:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_11 |
| TCELL16:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_12 |
| TCELL16:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_13 |
| TCELL16:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_14 |
| TCELL16:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_15 |
| TCELL16:OUT.17.TMIN | CMAC.TX_SERDES_DATA5_24 |
| TCELL16:OUT.19.TMIN | CMAC.TX_SERDES_DATA5_25 |
| TCELL16:OUT.21.TMIN | CMAC.TX_SERDES_DATA5_26 |
| TCELL16:OUT.23.TMIN | CMAC.TX_SERDES_DATA5_27 |
| TCELL16:OUT.25.TMIN | CMAC.TX_SERDES_DATA5_28 |
| TCELL16:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR16 |
| TCELL16:OUT.27.TMIN | CMAC.TX_SERDES_DATA5_29 |
| TCELL16:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC143 |
| TCELL16:OUT.29.TMIN | CMAC.TX_SERDES_DATA5_30 |
| TCELL16:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR16 |
| TCELL16:OUT.31.TMIN | CMAC.TX_SERDES_DATA5_31 |
| TCELL16:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC16 |
| TCELL16:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA5_30 |
| TCELL16:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA5_31 |
| TCELL16:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA5_24 |
| TCELL16:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA5_25 |
| TCELL16:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA5_26 |
| TCELL16:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC72 |
| TCELL16:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA5_27 |
| TCELL16:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA5_28 |
| TCELL16:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA5_29 |
| TCELL16:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_PAUSE_ENABLE0 |
| TCELL16:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_PAUSE_ENABLE1 |
| TCELL16:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC128 |
| TCELL16:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_PAUSE_ENABLE2 |
| TCELL16:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_PAUSE_ENABLE3 |
| TCELL16:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_PAUSE_ENABLE4 |
| TCELL16:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_PAUSE_ENABLE5 |
| TCELL16:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_PAUSE_ENABLE6 |
| TCELL16:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL2 |
| TCELL16:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_PAUSE_ENABLE7 |
| TCELL17:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_0 |
| TCELL17:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_1 |
| TCELL17:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_2 |
| TCELL17:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_3 |
| TCELL17:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_4 |
| TCELL17:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_5 |
| TCELL17:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_6 |
| TCELL17:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA8_7 |
| TCELL17:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_0 |
| TCELL17:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_1 |
| TCELL17:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_2 |
| TCELL17:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_3 |
| TCELL17:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_4 |
| TCELL17:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR17 |
| TCELL17:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_5 |
| TCELL17:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC142 |
| TCELL17:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_6 |
| TCELL17:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR17 |
| TCELL17:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_7 |
| TCELL17:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC17 |
| TCELL17:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_0 |
| TCELL17:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_1 |
| TCELL17:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_2 |
| TCELL17:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_3 |
| TCELL17:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_4 |
| TCELL17:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_5 |
| TCELL17:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC73 |
| TCELL17:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_6 |
| TCELL17:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_7 |
| TCELL17:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE0 |
| TCELL17:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE1 |
| TCELL17:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC129 |
| TCELL17:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE2 |
| TCELL17:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE3 |
| TCELL17:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE4 |
| TCELL17:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE5 |
| TCELL17:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE6 |
| TCELL17:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL3 |
| TCELL17:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE7 |
| TCELL18:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_8 |
| TCELL18:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_9 |
| TCELL18:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_10 |
| TCELL18:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_11 |
| TCELL18:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_12 |
| TCELL18:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_13 |
| TCELL18:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_14 |
| TCELL18:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_15 |
| TCELL18:OUT.15.TMIN | CMAC.TX_SERDES_ALT_DATA1_0 |
| TCELL18:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA1_1 |
| TCELL18:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_8 |
| TCELL18:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_9 |
| TCELL18:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_10 |
| TCELL18:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_11 |
| TCELL18:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR18 |
| TCELL18:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_12 |
| TCELL18:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC141 |
| TCELL18:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_13 |
| TCELL18:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR18 |
| TCELL18:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_14 |
| TCELL18:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC18 |
| TCELL18:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_ALT_DATA1_0 |
| TCELL18:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA1_1 |
| TCELL18:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_8 |
| TCELL18:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_9 |
| TCELL18:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_10 |
| TCELL18:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_11 |
| TCELL18:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC74 |
| TCELL18:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_12 |
| TCELL18:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_13 |
| TCELL18:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_14 |
| TCELL18:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_PAUSE_REQ0 |
| TCELL18:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_PAUSE_REQ1 |
| TCELL18:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC130 |
| TCELL18:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_PAUSE_REQ2 |
| TCELL18:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_PAUSE_REQ3 |
| TCELL18:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_PAUSE_REQ4 |
| TCELL18:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_PAUSE_REQ5 |
| TCELL18:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_PAUSE_REQ6 |
| TCELL18:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL4 |
| TCELL18:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_PAUSE_REQ7 |
| TCELL19:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_0 |
| TCELL19:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_1 |
| TCELL19:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_2 |
| TCELL19:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_3 |
| TCELL19:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_4 |
| TCELL19:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_5 |
| TCELL19:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_6 |
| TCELL19:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA7_7 |
| TCELL19:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_15 |
| TCELL19:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA1_2 |
| TCELL19:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA1_3 |
| TCELL19:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_16 |
| TCELL19:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_17 |
| TCELL19:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_18 |
| TCELL19:OUT.26.TMIN | CMAC.STAT_RX_MF_REPEAT_ERR19 |
| TCELL19:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_19 |
| TCELL19:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC140 |
| TCELL19:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_20 |
| TCELL19:OUT.30.TMIN | CMAC.STAT_RX_MF_LEN_ERR19 |
| TCELL19:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_21 |
| TCELL19:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC19 |
| TCELL19:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_15 |
| TCELL19:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA1_2 |
| TCELL19:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA1_3 |
| TCELL19:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_16 |
| TCELL19:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_17 |
| TCELL19:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_18 |
| TCELL19:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC75 |
| TCELL19:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_19 |
| TCELL19:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_20 |
| TCELL19:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_21 |
| TCELL19:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_PAUSE_REQ8 |
| TCELL19:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_LANE0_VLM_BIP7_OVERRIDE |
| TCELL19:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC131 |
| TCELL19:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_ENABLE |
| TCELL19:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_RESEND_PAUSE |
| TCELL19:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SEND_RFI |
| TCELL19:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SEND_IDLE |
| TCELL19:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_TEST_PATTERN |
| TCELL19:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL5 |
| TCELL19:IMUX.IMUX.47.DELAY | CMAC.CTL_CAUI4_MODE |
| TCELL20:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_8 |
| TCELL20:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_9 |
| TCELL20:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_10 |
| TCELL20:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_11 |
| TCELL20:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_12 |
| TCELL20:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_13 |
| TCELL20:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_14 |
| TCELL20:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_15 |
| TCELL20:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_22 |
| TCELL20:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_23 |
| TCELL20:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA1_4 |
| TCELL20:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA1_5 |
| TCELL20:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_24 |
| TCELL20:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_25 |
| TCELL20:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR0 |
| TCELL20:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_26 |
| TCELL20:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC139 |
| TCELL20:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_27 |
| TCELL20:OUT.30.TMIN | CMAC.STAT_RX_SYNCED0 |
| TCELL20:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_28 |
| TCELL20:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC20 |
| TCELL20:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_22 |
| TCELL20:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_23 |
| TCELL20:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA1_4 |
| TCELL20:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA1_5 |
| TCELL20:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_24 |
| TCELL20:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_25 |
| TCELL20:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC76 |
| TCELL20:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_26 |
| TCELL20:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_27 |
| TCELL20:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_28 |
| TCELL20:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN0 |
| TCELL20:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN1 |
| TCELL20:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC132 |
| TCELL20:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN2 |
| TCELL20:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN3 |
| TCELL20:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN4 |
| TCELL20:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN5 |
| TCELL20:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN6 |
| TCELL20:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL6 |
| TCELL20:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN7 |
| TCELL21:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_0 |
| TCELL21:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_1 |
| TCELL21:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_2 |
| TCELL21:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_3 |
| TCELL21:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_4 |
| TCELL21:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_5 |
| TCELL21:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_6 |
| TCELL21:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA6_7 |
| TCELL21:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_29 |
| TCELL21:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_30 |
| TCELL21:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_31 |
| TCELL21:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA1_6 |
| TCELL21:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA1_7 |
| TCELL21:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_32 |
| TCELL21:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR1 |
| TCELL21:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_33 |
| TCELL21:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC138 |
| TCELL21:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_34 |
| TCELL21:OUT.30.TMIN | CMAC.STAT_RX_SYNCED1 |
| TCELL21:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_35 |
| TCELL21:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC21 |
| TCELL21:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_29 |
| TCELL21:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_30 |
| TCELL21:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_31 |
| TCELL21:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA1_6 |
| TCELL21:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA1_7 |
| TCELL21:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_32 |
| TCELL21:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC77 |
| TCELL21:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_33 |
| TCELL21:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_34 |
| TCELL21:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_35 |
| TCELL21:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN8 |
| TCELL21:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN9 |
| TCELL21:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC133 |
| TCELL21:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN10 |
| TCELL21:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN11 |
| TCELL21:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN12 |
| TCELL21:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN13 |
| TCELL21:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN14 |
| TCELL21:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL7 |
| TCELL21:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN15 |
| TCELL22:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_8 |
| TCELL22:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_9 |
| TCELL22:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_10 |
| TCELL22:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_11 |
| TCELL22:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_12 |
| TCELL22:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_13 |
| TCELL22:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_14 |
| TCELL22:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_15 |
| TCELL22:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_36 |
| TCELL22:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_37 |
| TCELL22:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_38 |
| TCELL22:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_39 |
| TCELL22:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA1_8 |
| TCELL22:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA1_9 |
| TCELL22:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR2 |
| TCELL22:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_40 |
| TCELL22:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC137 |
| TCELL22:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_41 |
| TCELL22:OUT.30.TMIN | CMAC.STAT_RX_SYNCED2 |
| TCELL22:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_42 |
| TCELL22:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC22 |
| TCELL22:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_36 |
| TCELL22:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_37 |
| TCELL22:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_38 |
| TCELL22:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_39 |
| TCELL22:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA1_8 |
| TCELL22:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA1_9 |
| TCELL22:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC78 |
| TCELL22:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_40 |
| TCELL22:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_41 |
| TCELL22:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_42 |
| TCELL22:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN16 |
| TCELL22:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN17 |
| TCELL22:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC134 |
| TCELL22:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN18 |
| TCELL22:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN19 |
| TCELL22:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN20 |
| TCELL22:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN21 |
| TCELL22:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN22 |
| TCELL22:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL8 |
| TCELL22:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN23 |
| TCELL23:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_0 |
| TCELL23:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_1 |
| TCELL23:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_2 |
| TCELL23:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_3 |
| TCELL23:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_4 |
| TCELL23:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_5 |
| TCELL23:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_6 |
| TCELL23:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA5_7 |
| TCELL23:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_43 |
| TCELL23:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_44 |
| TCELL23:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_45 |
| TCELL23:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_46 |
| TCELL23:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_47 |
| TCELL23:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA1_10 |
| TCELL23:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR3 |
| TCELL23:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA1_11 |
| TCELL23:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC136 |
| TCELL23:OUT.29.TMIN | CMAC.TX_SERDES_DATA1_48 |
| TCELL23:OUT.30.TMIN | CMAC.STAT_RX_SYNCED3 |
| TCELL23:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_49 |
| TCELL23:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC23 |
| TCELL23:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_43 |
| TCELL23:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_44 |
| TCELL23:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_45 |
| TCELL23:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_46 |
| TCELL23:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_47 |
| TCELL23:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA1_10 |
| TCELL23:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC79 |
| TCELL23:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA1_11 |
| TCELL23:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA1_48 |
| TCELL23:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_49 |
| TCELL23:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN24 |
| TCELL23:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN25 |
| TCELL23:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC135 |
| TCELL23:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN26 |
| TCELL23:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN27 |
| TCELL23:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN28 |
| TCELL23:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN29 |
| TCELL23:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN30 |
| TCELL23:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL9 |
| TCELL23:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN31 |
| TCELL24:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_8 |
| TCELL24:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_9 |
| TCELL24:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_10 |
| TCELL24:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_11 |
| TCELL24:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_12 |
| TCELL24:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_13 |
| TCELL24:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_14 |
| TCELL24:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_15 |
| TCELL24:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_50 |
| TCELL24:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_51 |
| TCELL24:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_52 |
| TCELL24:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_53 |
| TCELL24:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_54 |
| TCELL24:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_55 |
| TCELL24:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR4 |
| TCELL24:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA1_12 |
| TCELL24:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC135 |
| TCELL24:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA1_13 |
| TCELL24:OUT.30.TMIN | CMAC.STAT_RX_SYNCED4 |
| TCELL24:OUT.31.TMIN | CMAC.TX_SERDES_DATA1_56 |
| TCELL24:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC24 |
| TCELL24:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_50 |
| TCELL24:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_51 |
| TCELL24:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_52 |
| TCELL24:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_53 |
| TCELL24:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_54 |
| TCELL24:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_55 |
| TCELL24:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC80 |
| TCELL24:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA1_12 |
| TCELL24:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA1_13 |
| TCELL24:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA1_56 |
| TCELL24:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN32 |
| TCELL24:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN33 |
| TCELL24:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC136 |
| TCELL24:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN34 |
| TCELL24:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN35 |
| TCELL24:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN36 |
| TCELL24:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN37 |
| TCELL24:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN38 |
| TCELL24:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL10 |
| TCELL24:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN39 |
| TCELL25:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_0 |
| TCELL25:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_1 |
| TCELL25:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_2 |
| TCELL25:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_3 |
| TCELL25:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_4 |
| TCELL25:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_5 |
| TCELL25:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_6 |
| TCELL25:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA4_7 |
| TCELL25:OUT.15.TMIN | CMAC.TX_SERDES_DATA1_57 |
| TCELL25:OUT.17.TMIN | CMAC.TX_SERDES_DATA1_58 |
| TCELL25:OUT.19.TMIN | CMAC.TX_SERDES_DATA1_59 |
| TCELL25:OUT.21.TMIN | CMAC.TX_SERDES_DATA1_60 |
| TCELL25:OUT.23.TMIN | CMAC.TX_SERDES_DATA1_61 |
| TCELL25:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL12 |
| TCELL25:OUT.25.TMIN | CMAC.TX_SERDES_DATA1_62 |
| TCELL25:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR5 |
| TCELL25:OUT.27.TMIN | CMAC.TX_SERDES_DATA1_63 |
| TCELL25:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC134 |
| TCELL25:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA1_14 |
| TCELL25:OUT.30.TMIN | CMAC.STAT_RX_SYNCED5 |
| TCELL25:OUT.31.TMIN | CMAC.TX_SERDES_ALT_DATA1_15 |
| TCELL25:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC25 |
| TCELL25:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA1_57 |
| TCELL25:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET9 |
| TCELL25:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA1_58 |
| TCELL25:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA1_59 |
| TCELL25:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA1_60 |
| TCELL25:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA1_61 |
| TCELL25:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA1_62 |
| TCELL25:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC81 |
| TCELL25:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA1_63 |
| TCELL25:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA1_14 |
| TCELL25:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_ALT_DATA1_15 |
| TCELL25:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN40 |
| TCELL25:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN41 |
| TCELL25:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC137 |
| TCELL25:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN42 |
| TCELL25:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN43 |
| TCELL25:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN44 |
| TCELL25:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN45 |
| TCELL25:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN46 |
| TCELL25:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL11 |
| TCELL25:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN47 |
| TCELL26:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_8 |
| TCELL26:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_9 |
| TCELL26:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_10 |
| TCELL26:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_11 |
| TCELL26:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_12 |
| TCELL26:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_13 |
| TCELL26:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_14 |
| TCELL26:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_15 |
| TCELL26:OUT.15.TMIN | CMAC.TX_SERDES_DATA6_5 |
| TCELL26:OUT.17.TMIN | CMAC.TX_SERDES_DATA6_6 |
| TCELL26:OUT.19.TMIN | CMAC.TX_SERDES_DATA6_7 |
| TCELL26:OUT.23.TMIN | CMAC.TX_SERDES_DATA6_0 |
| TCELL26:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL11 |
| TCELL26:OUT.25.TMIN | CMAC.TX_SERDES_DATA6_1 |
| TCELL26:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR6 |
| TCELL26:OUT.27.TMIN | CMAC.TX_SERDES_DATA6_2 |
| TCELL26:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC133 |
| TCELL26:OUT.29.TMIN | CMAC.TX_SERDES_DATA6_3 |
| TCELL26:OUT.30.TMIN | CMAC.STAT_RX_SYNCED6 |
| TCELL26:OUT.31.TMIN | CMAC.TX_SERDES_DATA6_4 |
| TCELL26:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC26 |
| TCELL26:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA6_5 |
| TCELL26:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET8 |
| TCELL26:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA6_6 |
| TCELL26:IMUX.IMUX.4.DELAY | CMAC.RX_RESET |
| TCELL26:IMUX.IMUX.5.DELAY | CMAC.TX_RESET |
| TCELL26:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA6_7 |
| TCELL26:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA6_0 |
| TCELL26:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA6_1 |
| TCELL26:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC82 |
| TCELL26:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA6_2 |
| TCELL26:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA6_3 |
| TCELL26:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA6_4 |
| TCELL26:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN48 |
| TCELL26:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN49 |
| TCELL26:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC138 |
| TCELL26:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN50 |
| TCELL26:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN51 |
| TCELL26:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN52 |
| TCELL26:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN53 |
| TCELL26:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN54 |
| TCELL26:IMUX.IMUX.46.DELAY | CMAC.SCAN_IN_DRPCTRL12 |
| TCELL26:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN55 |
| TCELL27:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_0 |
| TCELL27:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_1 |
| TCELL27:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_2 |
| TCELL27:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_3 |
| TCELL27:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_4 |
| TCELL27:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_5 |
| TCELL27:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_6 |
| TCELL27:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA3_7 |
| TCELL27:OUT.15.TMIN | CMAC.TX_SERDES_DATA6_14 |
| TCELL27:OUT.17.TMIN | CMAC.TX_SERDES_DATA6_15 |
| TCELL27:OUT.21.TMIN | CMAC.TX_SERDES_DATA6_8 |
| TCELL27:OUT.23.TMIN | CMAC.TX_SERDES_DATA6_9 |
| TCELL27:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL10 |
| TCELL27:OUT.25.TMIN | CMAC.TX_SERDES_DATA6_10 |
| TCELL27:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR7 |
| TCELL27:OUT.27.TMIN | CMAC.TX_SERDES_DATA6_11 |
| TCELL27:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC132 |
| TCELL27:OUT.29.TMIN | CMAC.TX_SERDES_DATA6_12 |
| TCELL27:OUT.30.TMIN | CMAC.STAT_RX_SYNCED7 |
| TCELL27:OUT.31.TMIN | CMAC.TX_SERDES_DATA6_13 |
| TCELL27:IMUX.CTRL.2 | CMAC.RX_SERDES_CLK_B5 |
| TCELL27:IMUX.CTRL.3 | CMAC.RX_SERDES_CLK_B4 |
| TCELL27:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC27 |
| TCELL27:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA6_14 |
| TCELL27:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET7 |
| TCELL27:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA6_15 |
| TCELL27:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA6_8 |
| TCELL27:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA6_9 |
| TCELL27:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA6_10 |
| TCELL27:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC83 |
| TCELL27:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA6_11 |
| TCELL27:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA6_12 |
| TCELL27:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA6_13 |
| TCELL27:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN56 |
| TCELL27:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN57 |
| TCELL27:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC139 |
| TCELL27:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN58 |
| TCELL27:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN59 |
| TCELL27:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN60 |
| TCELL27:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN61 |
| TCELL27:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN62 |
| TCELL27:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN63 |
| TCELL28:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_8 |
| TCELL28:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_9 |
| TCELL28:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_10 |
| TCELL28:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_11 |
| TCELL28:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_12 |
| TCELL28:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_13 |
| TCELL28:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_14 |
| TCELL28:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_15 |
| TCELL28:OUT.15.TMIN | CMAC.TX_SERDES_DATA6_23 |
| TCELL28:OUT.19.TMIN | CMAC.TX_SERDES_DATA6_16 |
| TCELL28:OUT.21.TMIN | CMAC.TX_SERDES_DATA6_17 |
| TCELL28:OUT.23.TMIN | CMAC.TX_SERDES_DATA6_18 |
| TCELL28:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL9 |
| TCELL28:OUT.25.TMIN | CMAC.TX_SERDES_DATA6_19 |
| TCELL28:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR8 |
| TCELL28:OUT.27.TMIN | CMAC.TX_SERDES_DATA6_20 |
| TCELL28:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC131 |
| TCELL28:OUT.29.TMIN | CMAC.TX_SERDES_DATA6_21 |
| TCELL28:OUT.30.TMIN | CMAC.STAT_RX_SYNCED8 |
| TCELL28:OUT.31.TMIN | CMAC.TX_SERDES_DATA6_22 |
| TCELL28:IMUX.CTRL.2 | CMAC.RX_SERDES_CLK_B3 |
| TCELL28:IMUX.CTRL.3 | CMAC.RX_SERDES_CLK_B2 |
| TCELL28:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC28 |
| TCELL28:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA6_23 |
| TCELL28:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET6 |
| TCELL28:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA6_16 |
| TCELL28:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA6_17 |
| TCELL28:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA6_18 |
| TCELL28:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA6_19 |
| TCELL28:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC84 |
| TCELL28:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA6_20 |
| TCELL28:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA6_21 |
| TCELL28:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA6_22 |
| TCELL28:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN64 |
| TCELL28:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN65 |
| TCELL28:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC140 |
| TCELL28:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN66 |
| TCELL28:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN67 |
| TCELL28:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN68 |
| TCELL28:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN69 |
| TCELL28:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN70 |
| TCELL28:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN71 |
| TCELL29:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_0 |
| TCELL29:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_1 |
| TCELL29:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_2 |
| TCELL29:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_3 |
| TCELL29:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_4 |
| TCELL29:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_5 |
| TCELL29:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_6 |
| TCELL29:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA2_7 |
| TCELL29:OUT.17.TMIN | CMAC.TX_SERDES_DATA6_24 |
| TCELL29:OUT.19.TMIN | CMAC.TX_SERDES_DATA6_25 |
| TCELL29:OUT.21.TMIN | CMAC.TX_SERDES_DATA6_26 |
| TCELL29:OUT.23.TMIN | CMAC.TX_SERDES_DATA6_27 |
| TCELL29:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL8 |
| TCELL29:OUT.25.TMIN | CMAC.TX_SERDES_DATA6_28 |
| TCELL29:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR9 |
| TCELL29:OUT.27.TMIN | CMAC.TX_SERDES_DATA6_29 |
| TCELL29:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC130 |
| TCELL29:OUT.29.TMIN | CMAC.TX_SERDES_DATA6_30 |
| TCELL29:OUT.30.TMIN | CMAC.STAT_RX_SYNCED9 |
| TCELL29:OUT.31.TMIN | CMAC.TX_SERDES_DATA6_31 |
| TCELL29:IMUX.CTRL.2 | CMAC.RX_SERDES_CLK_B1 |
| TCELL29:IMUX.CTRL.3 | CMAC.RX_SERDES_CLK_B0 |
| TCELL29:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC29 |
| TCELL29:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET5 |
| TCELL29:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA6_24 |
| TCELL29:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA6_25 |
| TCELL29:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA6_26 |
| TCELL29:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA6_27 |
| TCELL29:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA6_28 |
| TCELL29:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC85 |
| TCELL29:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA6_29 |
| TCELL29:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA6_30 |
| TCELL29:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA6_31 |
| TCELL29:IMUX.IMUX.26.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN72 |
| TCELL29:IMUX.IMUX.29.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN73 |
| TCELL29:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC141 |
| TCELL29:IMUX.IMUX.32.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN74 |
| TCELL29:IMUX.IMUX.35.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN75 |
| TCELL29:IMUX.IMUX.38.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN76 |
| TCELL29:IMUX.IMUX.41.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN77 |
| TCELL29:IMUX.IMUX.44.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN78 |
| TCELL29:IMUX.IMUX.47.DELAY | CMAC.CTL_TX_SYSTEMTIMERIN79 |
| TCELL30:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_8 |
| TCELL30:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_9 |
| TCELL30:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_10 |
| TCELL30:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_11 |
| TCELL30:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_12 |
| TCELL30:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_13 |
| TCELL30:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_14 |
| TCELL30:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_15 |
| TCELL30:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_0 |
| TCELL30:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_1 |
| TCELL30:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_2 |
| TCELL30:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_3 |
| TCELL30:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL7 |
| TCELL30:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_4 |
| TCELL30:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR10 |
| TCELL30:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_5 |
| TCELL30:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC129 |
| TCELL30:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_6 |
| TCELL30:OUT.30.TMIN | CMAC.STAT_RX_SYNCED10 |
| TCELL30:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_7 |
| TCELL30:IMUX.CTRL.2 | CMAC.TX_CLK_B |
| TCELL30:IMUX.CTRL.3 | CMAC.RX_CLK_B |
| TCELL30:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC30 |
| TCELL30:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_0 |
| TCELL30:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET4 |
| TCELL30:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_1 |
| TCELL30:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_2 |
| TCELL30:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_3 |
| TCELL30:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_4 |
| TCELL30:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_5 |
| TCELL30:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC86 |
| TCELL30:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_6 |
| TCELL30:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_7 |
| TCELL30:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC142 |
| TCELL31:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_0 |
| TCELL31:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_1 |
| TCELL31:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_2 |
| TCELL31:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_3 |
| TCELL31:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_4 |
| TCELL31:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_5 |
| TCELL31:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_6 |
| TCELL31:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA1_7 |
| TCELL31:OUT.15.TMIN | CMAC.TX_SERDES_ALT_DATA2_0 |
| TCELL31:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA2_1 |
| TCELL31:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_8 |
| TCELL31:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_9 |
| TCELL31:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_10 |
| TCELL31:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL6 |
| TCELL31:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_11 |
| TCELL31:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR11 |
| TCELL31:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_12 |
| TCELL31:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC128 |
| TCELL31:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_13 |
| TCELL31:OUT.30.TMIN | CMAC.STAT_RX_SYNCED11 |
| TCELL31:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_14 |
| TCELL31:IMUX.CTRL.2 | CMAC.RX_SERDES_CLK_B7 |
| TCELL31:IMUX.CTRL.3 | CMAC.RX_SERDES_CLK_B6 |
| TCELL31:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC31 |
| TCELL31:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_ALT_DATA2_0 |
| TCELL31:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET3 |
| TCELL31:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA2_1 |
| TCELL31:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_8 |
| TCELL31:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_9 |
| TCELL31:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_10 |
| TCELL31:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_11 |
| TCELL31:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC87 |
| TCELL31:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_12 |
| TCELL31:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_13 |
| TCELL31:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_14 |
| TCELL31:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC143 |
| TCELL32:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_8 |
| TCELL32:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_9 |
| TCELL32:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_10 |
| TCELL32:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_11 |
| TCELL32:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_12 |
| TCELL32:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_13 |
| TCELL32:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_14 |
| TCELL32:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_15 |
| TCELL32:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_15 |
| TCELL32:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA2_2 |
| TCELL32:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA2_3 |
| TCELL32:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_16 |
| TCELL32:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_17 |
| TCELL32:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL5 |
| TCELL32:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_18 |
| TCELL32:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR12 |
| TCELL32:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_19 |
| TCELL32:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC127 |
| TCELL32:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_20 |
| TCELL32:OUT.30.TMIN | CMAC.STAT_RX_SYNCED12 |
| TCELL32:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_21 |
| TCELL32:IMUX.CTRL.2 | CMAC.RX_SERDES_CLK_B9 |
| TCELL32:IMUX.CTRL.3 | CMAC.RX_SERDES_CLK_B8 |
| TCELL32:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC32 |
| TCELL32:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_15 |
| TCELL32:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET2 |
| TCELL32:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA2_2 |
| TCELL32:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA2_3 |
| TCELL32:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_16 |
| TCELL32:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_17 |
| TCELL32:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_18 |
| TCELL32:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC88 |
| TCELL32:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_19 |
| TCELL32:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_20 |
| TCELL32:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_21 |
| TCELL32:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC144 |
| TCELL33:OUT.0.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_0 |
| TCELL33:OUT.2.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_1 |
| TCELL33:OUT.4.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_2 |
| TCELL33:OUT.6.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_3 |
| TCELL33:OUT.8.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_4 |
| TCELL33:OUT.10.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_5 |
| TCELL33:OUT.12.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_6 |
| TCELL33:OUT.14.TMIN | CMAC.STAT_RX_PAUSE_QUANTA0_7 |
| TCELL33:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_22 |
| TCELL33:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_23 |
| TCELL33:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA2_4 |
| TCELL33:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA2_5 |
| TCELL33:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_24 |
| TCELL33:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL4 |
| TCELL33:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_25 |
| TCELL33:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR13 |
| TCELL33:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_26 |
| TCELL33:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC126 |
| TCELL33:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_27 |
| TCELL33:OUT.30.TMIN | CMAC.STAT_RX_SYNCED13 |
| TCELL33:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_28 |
| TCELL33:IMUX.CTRL.2 | CMAC.SCAN_EN_N |
| TCELL33:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC33 |
| TCELL33:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_22 |
| TCELL33:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET1 |
| TCELL33:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_23 |
| TCELL33:IMUX.IMUX.4.DELAY | CMAC.TEST_RESET |
| TCELL33:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA2_4 |
| TCELL33:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA2_5 |
| TCELL33:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_24 |
| TCELL33:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_25 |
| TCELL33:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC89 |
| TCELL33:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_26 |
| TCELL33:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_27 |
| TCELL33:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_28 |
| TCELL33:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC145 |
| TCELL34:OUT.0.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES0 |
| TCELL34:OUT.2.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES1 |
| TCELL34:OUT.4.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES2 |
| TCELL34:OUT.6.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES3 |
| TCELL34:OUT.8.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES4 |
| TCELL34:OUT.10.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES5 |
| TCELL34:OUT.12.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES6 |
| TCELL34:OUT.14.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES7 |
| TCELL34:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_29 |
| TCELL34:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_30 |
| TCELL34:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_31 |
| TCELL34:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA2_6 |
| TCELL34:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA2_7 |
| TCELL34:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL3 |
| TCELL34:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_32 |
| TCELL34:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR14 |
| TCELL34:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_33 |
| TCELL34:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC125 |
| TCELL34:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_34 |
| TCELL34:OUT.30.TMIN | CMAC.STAT_RX_SYNCED14 |
| TCELL34:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_35 |
| TCELL34:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC34 |
| TCELL34:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_29 |
| TCELL34:IMUX.IMUX.2.DELAY | CMAC.RX_SERDES_RESET0 |
| TCELL34:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_30 |
| TCELL34:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_31 |
| TCELL34:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA2_6 |
| TCELL34:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA2_7 |
| TCELL34:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_32 |
| TCELL34:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC90 |
| TCELL34:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_33 |
| TCELL34:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_34 |
| TCELL34:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_35 |
| TCELL34:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC146 |
| TCELL35:OUT.0.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES8 |
| TCELL35:OUT.2.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES9 |
| TCELL35:OUT.4.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES10 |
| TCELL35:OUT.6.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES11 |
| TCELL35:OUT.8.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES12 |
| TCELL35:OUT.10.TMIN | CMAC.STAT_RX_TOTAL_GOOD_BYTES13 |
| TCELL35:OUT.12.TMIN | CMAC.STAT_RX_TOTAL_GOOD_PACKETS |
| TCELL35:OUT.14.TMIN | CMAC.STAT_RX_TOOLONG |
| TCELL35:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_36 |
| TCELL35:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_37 |
| TCELL35:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_38 |
| TCELL35:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_39 |
| TCELL35:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA2_8 |
| TCELL35:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL2 |
| TCELL35:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA2_9 |
| TCELL35:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR15 |
| TCELL35:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_40 |
| TCELL35:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC124 |
| TCELL35:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_41 |
| TCELL35:OUT.30.TMIN | CMAC.STAT_RX_SYNCED15 |
| TCELL35:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_42 |
| TCELL35:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC35 |
| TCELL35:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_36 |
| TCELL35:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_37 |
| TCELL35:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_38 |
| TCELL35:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_39 |
| TCELL35:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA2_8 |
| TCELL35:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA2_9 |
| TCELL35:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC91 |
| TCELL35:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_40 |
| TCELL35:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_41 |
| TCELL35:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_42 |
| TCELL35:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC147 |
| TCELL36:OUT.0.TMIN | CMAC.STAT_RX_BIP_ERR_0 |
| TCELL36:OUT.2.TMIN | CMAC.STAT_RX_BIP_ERR_1 |
| TCELL36:OUT.4.TMIN | CMAC.STAT_RX_BIP_ERR_2 |
| TCELL36:OUT.6.TMIN | CMAC.STAT_RX_BIP_ERR_3 |
| TCELL36:OUT.8.TMIN | CMAC.STAT_RX_BIP_ERR_4 |
| TCELL36:OUT.10.TMIN | CMAC.STAT_RX_BIP_ERR_5 |
| TCELL36:OUT.12.TMIN | CMAC.STAT_RX_BIP_ERR_6 |
| TCELL36:OUT.14.TMIN | CMAC.STAT_RX_BIP_ERR_7 |
| TCELL36:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_43 |
| TCELL36:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_44 |
| TCELL36:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_45 |
| TCELL36:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_46 |
| TCELL36:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_47 |
| TCELL36:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL1 |
| TCELL36:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA2_10 |
| TCELL36:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR16 |
| TCELL36:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA2_11 |
| TCELL36:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC123 |
| TCELL36:OUT.29.TMIN | CMAC.TX_SERDES_DATA2_48 |
| TCELL36:OUT.30.TMIN | CMAC.STAT_RX_SYNCED16 |
| TCELL36:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_49 |
| TCELL36:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC36 |
| TCELL36:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_43 |
| TCELL36:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_44 |
| TCELL36:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_45 |
| TCELL36:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_46 |
| TCELL36:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_47 |
| TCELL36:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA2_10 |
| TCELL36:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC92 |
| TCELL36:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA2_11 |
| TCELL36:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA2_48 |
| TCELL36:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_49 |
| TCELL36:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC148 |
| TCELL37:OUT.0.TMIN | CMAC.STAT_RX_BIP_ERR_8 |
| TCELL37:OUT.2.TMIN | CMAC.STAT_RX_BIP_ERR_9 |
| TCELL37:OUT.4.TMIN | CMAC.STAT_RX_BIP_ERR_10 |
| TCELL37:OUT.6.TMIN | CMAC.STAT_RX_BIP_ERR_11 |
| TCELL37:OUT.8.TMIN | CMAC.STAT_RX_BIP_ERR_12 |
| TCELL37:OUT.10.TMIN | CMAC.STAT_RX_BIP_ERR_13 |
| TCELL37:OUT.12.TMIN | CMAC.STAT_RX_BIP_ERR_14 |
| TCELL37:OUT.14.TMIN | CMAC.STAT_RX_BIP_ERR_15 |
| TCELL37:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_50 |
| TCELL37:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_51 |
| TCELL37:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_52 |
| TCELL37:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_53 |
| TCELL37:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_54 |
| TCELL37:OUT.24.TMIN | CMAC.SCAN_OUT_DRPCTRL0 |
| TCELL37:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_55 |
| TCELL37:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR17 |
| TCELL37:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA2_12 |
| TCELL37:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC122 |
| TCELL37:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA2_13 |
| TCELL37:OUT.30.TMIN | CMAC.STAT_RX_SYNCED17 |
| TCELL37:OUT.31.TMIN | CMAC.TX_SERDES_DATA2_56 |
| TCELL37:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC37 |
| TCELL37:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_50 |
| TCELL37:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_51 |
| TCELL37:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_52 |
| TCELL37:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_53 |
| TCELL37:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_54 |
| TCELL37:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_55 |
| TCELL37:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC93 |
| TCELL37:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA2_12 |
| TCELL37:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA2_13 |
| TCELL37:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA2_56 |
| TCELL37:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC149 |
| TCELL38:OUT.0.TMIN | CMAC.STAT_RX_BIP_ERR_16 |
| TCELL38:OUT.2.TMIN | CMAC.STAT_RX_BIP_ERR_17 |
| TCELL38:OUT.4.TMIN | CMAC.STAT_RX_BIP_ERR_18 |
| TCELL38:OUT.6.TMIN | CMAC.STAT_RX_BIP_ERR_19 |
| TCELL38:OUT.8.TMIN | CMAC.STAT_RX_BAD_FCS0 |
| TCELL38:OUT.10.TMIN | CMAC.STAT_RX_BAD_FCS1 |
| TCELL38:OUT.12.TMIN | CMAC.STAT_RX_BAD_FCS2 |
| TCELL38:OUT.14.TMIN | CMAC.STAT_RX_BAD_FCS3 |
| TCELL38:OUT.15.TMIN | CMAC.TX_SERDES_DATA2_57 |
| TCELL38:OUT.17.TMIN | CMAC.TX_SERDES_DATA2_58 |
| TCELL38:OUT.19.TMIN | CMAC.TX_SERDES_DATA2_59 |
| TCELL38:OUT.21.TMIN | CMAC.TX_SERDES_DATA2_60 |
| TCELL38:OUT.23.TMIN | CMAC.TX_SERDES_DATA2_61 |
| TCELL38:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC181 |
| TCELL38:OUT.25.TMIN | CMAC.TX_SERDES_DATA2_62 |
| TCELL38:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR18 |
| TCELL38:OUT.27.TMIN | CMAC.TX_SERDES_DATA2_63 |
| TCELL38:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC121 |
| TCELL38:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA2_14 |
| TCELL38:OUT.30.TMIN | CMAC.STAT_RX_SYNCED18 |
| TCELL38:OUT.31.TMIN | CMAC.TX_SERDES_ALT_DATA2_15 |
| TCELL38:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC38 |
| TCELL38:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA2_57 |
| TCELL38:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA2_58 |
| TCELL38:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA2_59 |
| TCELL38:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA2_60 |
| TCELL38:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA2_61 |
| TCELL38:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA2_62 |
| TCELL38:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC94 |
| TCELL38:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA2_63 |
| TCELL38:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA2_14 |
| TCELL38:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_ALT_DATA2_15 |
| TCELL38:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC150 |
| TCELL39:OUT.0.TMIN | CMAC.STAT_RX_BAD_CODE0 |
| TCELL39:OUT.2.TMIN | CMAC.STAT_RX_BAD_CODE1 |
| TCELL39:OUT.4.TMIN | CMAC.STAT_RX_BAD_CODE2 |
| TCELL39:OUT.6.TMIN | CMAC.STAT_RX_BAD_CODE3 |
| TCELL39:OUT.8.TMIN | CMAC.STAT_RX_BAD_CODE4 |
| TCELL39:OUT.10.TMIN | CMAC.STAT_RX_BAD_CODE5 |
| TCELL39:OUT.12.TMIN | CMAC.STAT_RX_BAD_CODE6 |
| TCELL39:OUT.14.TMIN | CMAC.STAT_RX_VLAN |
| TCELL39:OUT.15.TMIN | CMAC.TX_SERDES_DATA7_5 |
| TCELL39:OUT.17.TMIN | CMAC.TX_SERDES_DATA7_6 |
| TCELL39:OUT.19.TMIN | CMAC.TX_SERDES_DATA7_7 |
| TCELL39:OUT.23.TMIN | CMAC.TX_SERDES_DATA7_0 |
| TCELL39:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC180 |
| TCELL39:OUT.25.TMIN | CMAC.TX_SERDES_DATA7_1 |
| TCELL39:OUT.26.TMIN | CMAC.STAT_RX_SYNCED_ERR19 |
| TCELL39:OUT.27.TMIN | CMAC.TX_SERDES_DATA7_2 |
| TCELL39:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC120 |
| TCELL39:OUT.29.TMIN | CMAC.TX_SERDES_DATA7_3 |
| TCELL39:OUT.30.TMIN | CMAC.STAT_RX_SYNCED19 |
| TCELL39:OUT.31.TMIN | CMAC.TX_SERDES_DATA7_4 |
| TCELL39:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC39 |
| TCELL39:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA7_5 |
| TCELL39:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA7_6 |
| TCELL39:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA7_7 |
| TCELL39:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA7_0 |
| TCELL39:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA7_1 |
| TCELL39:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC95 |
| TCELL39:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA7_2 |
| TCELL39:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA7_3 |
| TCELL39:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA7_4 |
| TCELL39:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC151 |
| TCELL40:OUT.0.TMIN | CMAC.STAT_RX_TEST_PATTERN_MISMATCH0 |
| TCELL40:OUT.2.TMIN | CMAC.STAT_RX_TEST_PATTERN_MISMATCH1 |
| TCELL40:OUT.4.TMIN | CMAC.STAT_RX_TEST_PATTERN_MISMATCH2 |
| TCELL40:OUT.6.TMIN | CMAC.STAT_RX_BAD_SFD |
| TCELL40:OUT.8.TMIN | CMAC.STAT_RX_BAD_PREAMBLE |
| TCELL40:OUT.10.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_VALID |
| TCELL40:OUT.15.TMIN | CMAC.TX_SERDES_DATA7_14 |
| TCELL40:OUT.17.TMIN | CMAC.TX_SERDES_DATA7_15 |
| TCELL40:OUT.21.TMIN | CMAC.TX_SERDES_DATA7_8 |
| TCELL40:OUT.23.TMIN | CMAC.TX_SERDES_DATA7_9 |
| TCELL40:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC179 |
| TCELL40:OUT.25.TMIN | CMAC.TX_SERDES_DATA7_10 |
| TCELL40:OUT.27.TMIN | CMAC.TX_SERDES_DATA7_11 |
| TCELL40:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC119 |
| TCELL40:OUT.29.TMIN | CMAC.TX_SERDES_DATA7_12 |
| TCELL40:OUT.31.TMIN | CMAC.TX_SERDES_DATA7_13 |
| TCELL40:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC40 |
| TCELL40:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA7_14 |
| TCELL40:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA7_15 |
| TCELL40:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA7_8 |
| TCELL40:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA7_9 |
| TCELL40:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA7_10 |
| TCELL40:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC96 |
| TCELL40:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA7_11 |
| TCELL40:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA7_12 |
| TCELL40:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA7_13 |
| TCELL40:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC152 |
| TCELL41:OUT.0.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_0 |
| TCELL41:OUT.2.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_1 |
| TCELL41:OUT.4.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_2 |
| TCELL41:OUT.6.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_3 |
| TCELL41:OUT.8.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_4 |
| TCELL41:OUT.10.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_5 |
| TCELL41:OUT.12.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_6 |
| TCELL41:OUT.14.TMIN | CMAC.STAT_RX_LANE0_VLM_BIP7_7 |
| TCELL41:OUT.15.TMIN | CMAC.TX_SERDES_DATA7_23 |
| TCELL41:OUT.19.TMIN | CMAC.TX_SERDES_DATA7_16 |
| TCELL41:OUT.21.TMIN | CMAC.TX_SERDES_DATA7_17 |
| TCELL41:OUT.23.TMIN | CMAC.TX_SERDES_DATA7_18 |
| TCELL41:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC178 |
| TCELL41:OUT.25.TMIN | CMAC.TX_SERDES_DATA7_19 |
| TCELL41:OUT.27.TMIN | CMAC.TX_SERDES_DATA7_20 |
| TCELL41:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC118 |
| TCELL41:OUT.29.TMIN | CMAC.TX_SERDES_DATA7_21 |
| TCELL41:OUT.31.TMIN | CMAC.TX_SERDES_DATA7_22 |
| TCELL41:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC41 |
| TCELL41:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA7_23 |
| TCELL41:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA7_16 |
| TCELL41:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA7_17 |
| TCELL41:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA7_18 |
| TCELL41:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA7_19 |
| TCELL41:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC97 |
| TCELL41:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA7_20 |
| TCELL41:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA7_21 |
| TCELL41:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA7_22 |
| TCELL41:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC153 |
| TCELL42:OUT.0.TMIN | CMAC.STAT_RX_TOTAL_BYTES0 |
| TCELL42:OUT.2.TMIN | CMAC.STAT_RX_TOTAL_BYTES1 |
| TCELL42:OUT.4.TMIN | CMAC.STAT_RX_TOTAL_BYTES2 |
| TCELL42:OUT.6.TMIN | CMAC.STAT_RX_TOTAL_BYTES3 |
| TCELL42:OUT.8.TMIN | CMAC.STAT_RX_TOTAL_BYTES4 |
| TCELL42:OUT.10.TMIN | CMAC.STAT_RX_TOTAL_BYTES5 |
| TCELL42:OUT.12.TMIN | CMAC.STAT_RX_TOTAL_BYTES6 |
| TCELL42:OUT.14.TMIN | CMAC.STAT_RX_TOTAL_BYTES7 |
| TCELL42:OUT.17.TMIN | CMAC.TX_SERDES_DATA7_24 |
| TCELL42:OUT.19.TMIN | CMAC.TX_SERDES_DATA7_25 |
| TCELL42:OUT.21.TMIN | CMAC.TX_SERDES_DATA7_26 |
| TCELL42:OUT.23.TMIN | CMAC.TX_SERDES_DATA7_27 |
| TCELL42:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC177 |
| TCELL42:OUT.25.TMIN | CMAC.TX_SERDES_DATA7_28 |
| TCELL42:OUT.27.TMIN | CMAC.TX_SERDES_DATA7_29 |
| TCELL42:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC117 |
| TCELL42:OUT.29.TMIN | CMAC.TX_SERDES_DATA7_30 |
| TCELL42:OUT.31.TMIN | CMAC.TX_SERDES_DATA7_31 |
| TCELL42:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC42 |
| TCELL42:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA7_24 |
| TCELL42:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA7_25 |
| TCELL42:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA7_26 |
| TCELL42:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA7_27 |
| TCELL42:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA7_28 |
| TCELL42:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC98 |
| TCELL42:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA7_29 |
| TCELL42:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA7_30 |
| TCELL42:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA7_31 |
| TCELL42:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC154 |
| TCELL43:OUT.0.TMIN | CMAC.STAT_RX_VL_DEMUXED16 |
| TCELL43:OUT.2.TMIN | CMAC.STAT_RX_VL_DEMUXED17 |
| TCELL43:OUT.4.TMIN | CMAC.STAT_RX_VL_DEMUXED18 |
| TCELL43:OUT.6.TMIN | CMAC.STAT_RX_VL_DEMUXED19 |
| TCELL43:OUT.8.TMIN | CMAC.STAT_RX_TOTAL_PACKETS0 |
| TCELL43:OUT.10.TMIN | CMAC.STAT_RX_TOTAL_PACKETS1 |
| TCELL43:OUT.12.TMIN | CMAC.STAT_RX_TOTAL_PACKETS2 |
| TCELL43:OUT.14.TMIN | CMAC.STAT_RX_TOTAL_PACKETS3 |
| TCELL43:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_0 |
| TCELL43:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_1 |
| TCELL43:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_2 |
| TCELL43:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_3 |
| TCELL43:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC176 |
| TCELL43:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_4 |
| TCELL43:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_5 |
| TCELL43:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC116 |
| TCELL43:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_6 |
| TCELL43:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_7 |
| TCELL43:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC43 |
| TCELL43:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_0 |
| TCELL43:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_1 |
| TCELL43:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_2 |
| TCELL43:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_3 |
| TCELL43:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_4 |
| TCELL43:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_5 |
| TCELL43:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC99 |
| TCELL43:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_6 |
| TCELL43:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_7 |
| TCELL43:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC155 |
| TCELL44:OUT.0.TMIN | CMAC.STAT_RX_VL_DEMUXED8 |
| TCELL44:OUT.2.TMIN | CMAC.STAT_RX_VL_DEMUXED9 |
| TCELL44:OUT.4.TMIN | CMAC.STAT_RX_VL_DEMUXED10 |
| TCELL44:OUT.6.TMIN | CMAC.STAT_RX_VL_DEMUXED11 |
| TCELL44:OUT.8.TMIN | CMAC.STAT_RX_VL_DEMUXED12 |
| TCELL44:OUT.10.TMIN | CMAC.STAT_RX_VL_DEMUXED13 |
| TCELL44:OUT.12.TMIN | CMAC.STAT_RX_VL_DEMUXED14 |
| TCELL44:OUT.14.TMIN | CMAC.STAT_RX_VL_DEMUXED15 |
| TCELL44:OUT.15.TMIN | CMAC.TX_SERDES_ALT_DATA3_0 |
| TCELL44:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA3_1 |
| TCELL44:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_8 |
| TCELL44:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_9 |
| TCELL44:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_10 |
| TCELL44:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC175 |
| TCELL44:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_11 |
| TCELL44:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_12 |
| TCELL44:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC115 |
| TCELL44:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_13 |
| TCELL44:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_14 |
| TCELL44:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC44 |
| TCELL44:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_ALT_DATA3_0 |
| TCELL44:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA3_1 |
| TCELL44:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_8 |
| TCELL44:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_9 |
| TCELL44:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_10 |
| TCELL44:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_11 |
| TCELL44:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC100 |
| TCELL44:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_12 |
| TCELL44:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_13 |
| TCELL44:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_14 |
| TCELL44:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC156 |
| TCELL45:OUT.0.TMIN | CMAC.STAT_RX_VL_DEMUXED0 |
| TCELL45:OUT.2.TMIN | CMAC.STAT_RX_VL_DEMUXED1 |
| TCELL45:OUT.4.TMIN | CMAC.STAT_RX_VL_DEMUXED2 |
| TCELL45:OUT.6.TMIN | CMAC.STAT_RX_VL_DEMUXED3 |
| TCELL45:OUT.8.TMIN | CMAC.STAT_RX_VL_DEMUXED4 |
| TCELL45:OUT.10.TMIN | CMAC.STAT_RX_VL_DEMUXED5 |
| TCELL45:OUT.12.TMIN | CMAC.STAT_RX_VL_DEMUXED6 |
| TCELL45:OUT.14.TMIN | CMAC.STAT_RX_VL_DEMUXED7 |
| TCELL45:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_15 |
| TCELL45:OUT.17.TMIN | CMAC.TX_SERDES_ALT_DATA3_2 |
| TCELL45:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA3_3 |
| TCELL45:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_16 |
| TCELL45:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_17 |
| TCELL45:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC174 |
| TCELL45:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_18 |
| TCELL45:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_19 |
| TCELL45:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC114 |
| TCELL45:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_20 |
| TCELL45:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_21 |
| TCELL45:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC45 |
| TCELL45:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_15 |
| TCELL45:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_ALT_DATA3_2 |
| TCELL45:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA3_3 |
| TCELL45:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_16 |
| TCELL45:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_17 |
| TCELL45:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_18 |
| TCELL45:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC101 |
| TCELL45:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_19 |
| TCELL45:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_20 |
| TCELL45:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_21 |
| TCELL45:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC157 |
| TCELL46:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT72 |
| TCELL46:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT73 |
| TCELL46:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT74 |
| TCELL46:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT75 |
| TCELL46:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT76 |
| TCELL46:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT77 |
| TCELL46:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT78 |
| TCELL46:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT79 |
| TCELL46:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_22 |
| TCELL46:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_23 |
| TCELL46:OUT.19.TMIN | CMAC.TX_SERDES_ALT_DATA3_4 |
| TCELL46:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA3_5 |
| TCELL46:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_24 |
| TCELL46:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC173 |
| TCELL46:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_25 |
| TCELL46:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_26 |
| TCELL46:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC113 |
| TCELL46:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_27 |
| TCELL46:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_28 |
| TCELL46:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC46 |
| TCELL46:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_22 |
| TCELL46:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_23 |
| TCELL46:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_ALT_DATA3_4 |
| TCELL46:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA3_5 |
| TCELL46:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_24 |
| TCELL46:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_25 |
| TCELL46:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC102 |
| TCELL46:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_26 |
| TCELL46:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_27 |
| TCELL46:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_28 |
| TCELL46:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC158 |
| TCELL47:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT64 |
| TCELL47:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT65 |
| TCELL47:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT66 |
| TCELL47:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT67 |
| TCELL47:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT68 |
| TCELL47:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT69 |
| TCELL47:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT70 |
| TCELL47:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT71 |
| TCELL47:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_29 |
| TCELL47:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_30 |
| TCELL47:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_31 |
| TCELL47:OUT.21.TMIN | CMAC.TX_SERDES_ALT_DATA3_6 |
| TCELL47:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA3_7 |
| TCELL47:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC172 |
| TCELL47:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_32 |
| TCELL47:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_33 |
| TCELL47:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC112 |
| TCELL47:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_34 |
| TCELL47:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_35 |
| TCELL47:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC47 |
| TCELL47:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_29 |
| TCELL47:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_30 |
| TCELL47:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_31 |
| TCELL47:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_ALT_DATA3_6 |
| TCELL47:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA3_7 |
| TCELL47:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_32 |
| TCELL47:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC103 |
| TCELL47:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_33 |
| TCELL47:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_34 |
| TCELL47:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_35 |
| TCELL47:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC159 |
| TCELL48:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT56 |
| TCELL48:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT57 |
| TCELL48:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT58 |
| TCELL48:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT59 |
| TCELL48:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT60 |
| TCELL48:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT61 |
| TCELL48:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT62 |
| TCELL48:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT63 |
| TCELL48:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_36 |
| TCELL48:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_37 |
| TCELL48:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_38 |
| TCELL48:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_39 |
| TCELL48:OUT.23.TMIN | CMAC.TX_SERDES_ALT_DATA3_8 |
| TCELL48:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC171 |
| TCELL48:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA3_9 |
| TCELL48:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_40 |
| TCELL48:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC111 |
| TCELL48:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_41 |
| TCELL48:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_42 |
| TCELL48:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC48 |
| TCELL48:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_36 |
| TCELL48:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_37 |
| TCELL48:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_38 |
| TCELL48:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_39 |
| TCELL48:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_ALT_DATA3_8 |
| TCELL48:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA3_9 |
| TCELL48:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC104 |
| TCELL48:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_40 |
| TCELL48:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_41 |
| TCELL48:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_42 |
| TCELL48:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC160 |
| TCELL49:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT48 |
| TCELL49:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT49 |
| TCELL49:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT50 |
| TCELL49:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT51 |
| TCELL49:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT52 |
| TCELL49:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT53 |
| TCELL49:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT54 |
| TCELL49:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT55 |
| TCELL49:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_43 |
| TCELL49:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_44 |
| TCELL49:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_45 |
| TCELL49:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_46 |
| TCELL49:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_47 |
| TCELL49:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC170 |
| TCELL49:OUT.25.TMIN | CMAC.TX_SERDES_ALT_DATA3_10 |
| TCELL49:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA3_11 |
| TCELL49:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC110 |
| TCELL49:OUT.29.TMIN | CMAC.TX_SERDES_DATA3_48 |
| TCELL49:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_49 |
| TCELL49:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC49 |
| TCELL49:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_43 |
| TCELL49:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_44 |
| TCELL49:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_45 |
| TCELL49:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_46 |
| TCELL49:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_47 |
| TCELL49:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_ALT_DATA3_10 |
| TCELL49:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC105 |
| TCELL49:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA3_11 |
| TCELL49:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA3_48 |
| TCELL49:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_49 |
| TCELL49:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC161 |
| TCELL50:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT40 |
| TCELL50:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT41 |
| TCELL50:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT42 |
| TCELL50:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT43 |
| TCELL50:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT44 |
| TCELL50:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT45 |
| TCELL50:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT46 |
| TCELL50:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT47 |
| TCELL50:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_50 |
| TCELL50:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_51 |
| TCELL50:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_52 |
| TCELL50:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_53 |
| TCELL50:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_54 |
| TCELL50:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC169 |
| TCELL50:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_55 |
| TCELL50:OUT.27.TMIN | CMAC.TX_SERDES_ALT_DATA3_12 |
| TCELL50:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC109 |
| TCELL50:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA3_13 |
| TCELL50:OUT.31.TMIN | CMAC.TX_SERDES_DATA3_56 |
| TCELL50:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC50 |
| TCELL50:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_50 |
| TCELL50:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_51 |
| TCELL50:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_52 |
| TCELL50:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_53 |
| TCELL50:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_54 |
| TCELL50:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_55 |
| TCELL50:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC106 |
| TCELL50:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_ALT_DATA3_12 |
| TCELL50:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA3_13 |
| TCELL50:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA3_56 |
| TCELL50:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC162 |
| TCELL51:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT32 |
| TCELL51:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT33 |
| TCELL51:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT34 |
| TCELL51:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT35 |
| TCELL51:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT36 |
| TCELL51:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT37 |
| TCELL51:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT38 |
| TCELL51:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT39 |
| TCELL51:OUT.15.TMIN | CMAC.TX_SERDES_DATA3_57 |
| TCELL51:OUT.17.TMIN | CMAC.TX_SERDES_DATA3_58 |
| TCELL51:OUT.19.TMIN | CMAC.TX_SERDES_DATA3_59 |
| TCELL51:OUT.21.TMIN | CMAC.TX_SERDES_DATA3_60 |
| TCELL51:OUT.23.TMIN | CMAC.TX_SERDES_DATA3_61 |
| TCELL51:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC168 |
| TCELL51:OUT.25.TMIN | CMAC.TX_SERDES_DATA3_62 |
| TCELL51:OUT.27.TMIN | CMAC.TX_SERDES_DATA3_63 |
| TCELL51:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC108 |
| TCELL51:OUT.29.TMIN | CMAC.TX_SERDES_ALT_DATA3_14 |
| TCELL51:OUT.31.TMIN | CMAC.TX_SERDES_ALT_DATA3_15 |
| TCELL51:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC51 |
| TCELL51:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA3_57 |
| TCELL51:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA3_58 |
| TCELL51:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA3_59 |
| TCELL51:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA3_60 |
| TCELL51:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA3_61 |
| TCELL51:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA3_62 |
| TCELL51:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC107 |
| TCELL51:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA3_63 |
| TCELL51:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_ALT_DATA3_14 |
| TCELL51:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_ALT_DATA3_15 |
| TCELL51:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC163 |
| TCELL52:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT24 |
| TCELL52:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT25 |
| TCELL52:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT26 |
| TCELL52:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT27 |
| TCELL52:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT28 |
| TCELL52:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT29 |
| TCELL52:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT30 |
| TCELL52:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT31 |
| TCELL52:OUT.17.TMIN | CMAC.TX_SERDES_DATA8_0 |
| TCELL52:OUT.19.TMIN | CMAC.TX_SERDES_DATA8_1 |
| TCELL52:OUT.21.TMIN | CMAC.TX_SERDES_DATA8_2 |
| TCELL52:OUT.23.TMIN | CMAC.TX_SERDES_DATA8_3 |
| TCELL52:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC167 |
| TCELL52:OUT.25.TMIN | CMAC.TX_SERDES_DATA8_4 |
| TCELL52:OUT.27.TMIN | CMAC.TX_SERDES_DATA8_5 |
| TCELL52:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC107 |
| TCELL52:OUT.29.TMIN | CMAC.TX_SERDES_DATA8_6 |
| TCELL52:OUT.31.TMIN | CMAC.TX_SERDES_DATA8_7 |
| TCELL52:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC52 |
| TCELL52:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA8_5 |
| TCELL52:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA8_6 |
| TCELL52:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA8_7 |
| TCELL52:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA8_0 |
| TCELL52:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA8_1 |
| TCELL52:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC108 |
| TCELL52:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA8_2 |
| TCELL52:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA8_3 |
| TCELL52:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA8_4 |
| TCELL52:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC164 |
| TCELL53:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT16 |
| TCELL53:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT17 |
| TCELL53:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT18 |
| TCELL53:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT19 |
| TCELL53:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT20 |
| TCELL53:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT21 |
| TCELL53:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT22 |
| TCELL53:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT23 |
| TCELL53:OUT.15.TMIN | CMAC.TX_SERDES_DATA8_8 |
| TCELL53:OUT.17.TMIN | CMAC.TX_SERDES_DATA8_9 |
| TCELL53:OUT.19.TMIN | CMAC.TX_SERDES_DATA8_10 |
| TCELL53:OUT.21.TMIN | CMAC.TX_SERDES_DATA8_11 |
| TCELL53:OUT.23.TMIN | CMAC.TX_SERDES_DATA8_12 |
| TCELL53:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC166 |
| TCELL53:OUT.25.TMIN | CMAC.TX_SERDES_DATA8_13 |
| TCELL53:OUT.27.TMIN | CMAC.TX_SERDES_DATA8_14 |
| TCELL53:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC106 |
| TCELL53:OUT.29.TMIN | CMAC.TX_SERDES_DATA8_15 |
| TCELL53:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC53 |
| TCELL53:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA8_14 |
| TCELL53:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA8_15 |
| TCELL53:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA8_8 |
| TCELL53:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA8_9 |
| TCELL53:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA8_10 |
| TCELL53:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC109 |
| TCELL53:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA8_11 |
| TCELL53:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA8_12 |
| TCELL53:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA8_13 |
| TCELL53:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC165 |
| TCELL54:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT8 |
| TCELL54:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT9 |
| TCELL54:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT10 |
| TCELL54:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT11 |
| TCELL54:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT12 |
| TCELL54:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT13 |
| TCELL54:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT14 |
| TCELL54:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT15 |
| TCELL54:OUT.15.TMIN | CMAC.TX_SERDES_DATA8_17 |
| TCELL54:OUT.17.TMIN | CMAC.TX_SERDES_DATA8_18 |
| TCELL54:OUT.19.TMIN | CMAC.TX_SERDES_DATA8_19 |
| TCELL54:OUT.21.TMIN | CMAC.TX_SERDES_DATA8_20 |
| TCELL54:OUT.23.TMIN | CMAC.TX_SERDES_DATA8_21 |
| TCELL54:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC165 |
| TCELL54:OUT.25.TMIN | CMAC.TX_SERDES_DATA8_22 |
| TCELL54:OUT.27.TMIN | CMAC.TX_SERDES_DATA8_23 |
| TCELL54:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC105 |
| TCELL54:OUT.31.TMIN | CMAC.TX_SERDES_DATA8_16 |
| TCELL54:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC54 |
| TCELL54:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA8_23 |
| TCELL54:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA8_16 |
| TCELL54:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA8_17 |
| TCELL54:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA8_18 |
| TCELL54:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA8_19 |
| TCELL54:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC110 |
| TCELL54:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA8_20 |
| TCELL54:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA8_21 |
| TCELL54:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA8_22 |
| TCELL54:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC166 |
| TCELL55:OUT.0.TMIN | CMAC.RX_PTP_TSTAMP_OUT0 |
| TCELL55:OUT.2.TMIN | CMAC.RX_PTP_TSTAMP_OUT1 |
| TCELL55:OUT.4.TMIN | CMAC.RX_PTP_TSTAMP_OUT2 |
| TCELL55:OUT.6.TMIN | CMAC.RX_PTP_TSTAMP_OUT3 |
| TCELL55:OUT.8.TMIN | CMAC.RX_PTP_TSTAMP_OUT4 |
| TCELL55:OUT.10.TMIN | CMAC.RX_PTP_TSTAMP_OUT5 |
| TCELL55:OUT.12.TMIN | CMAC.RX_PTP_TSTAMP_OUT6 |
| TCELL55:OUT.14.TMIN | CMAC.RX_PTP_TSTAMP_OUT7 |
| TCELL55:OUT.15.TMIN | CMAC.TX_SERDES_DATA8_26 |
| TCELL55:OUT.17.TMIN | CMAC.TX_SERDES_DATA8_27 |
| TCELL55:OUT.19.TMIN | CMAC.TX_SERDES_DATA8_28 |
| TCELL55:OUT.21.TMIN | CMAC.TX_SERDES_DATA8_29 |
| TCELL55:OUT.23.TMIN | CMAC.TX_SERDES_DATA8_30 |
| TCELL55:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC164 |
| TCELL55:OUT.25.TMIN | CMAC.TX_SERDES_DATA8_31 |
| TCELL55:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC104 |
| TCELL55:OUT.29.TMIN | CMAC.TX_SERDES_DATA8_24 |
| TCELL55:OUT.31.TMIN | CMAC.TX_SERDES_DATA8_25 |
| TCELL55:IMUX.CTRL.3 | CMAC.TEST_MODE_N |
| TCELL55:IMUX.IMUX.0.DELAY | CMAC.SCAN_IN_CMAC55 |
| TCELL55:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA8_24 |
| TCELL55:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA8_25 |
| TCELL55:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA8_26 |
| TCELL55:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA8_27 |
| TCELL55:IMUX.IMUX.15.DELAY | CMAC.RX_SERDES_DATA8_28 |
| TCELL55:IMUX.IMUX.16.DELAY | CMAC.SCAN_IN_CMAC111 |
| TCELL55:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA8_29 |
| TCELL55:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA8_30 |
| TCELL55:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA8_31 |
| TCELL55:IMUX.IMUX.30.DELAY | CMAC.SCAN_IN_CMAC167 |
| TCELL56:OUT.0.TMIN | CMAC.RX_PTP_PCSLANE_OUT0 |
| TCELL56:OUT.2.TMIN | CMAC.RX_PTP_PCSLANE_OUT1 |
| TCELL56:OUT.4.TMIN | CMAC.RX_PTP_PCSLANE_OUT2 |
| TCELL56:OUT.6.TMIN | CMAC.RX_PTP_PCSLANE_OUT3 |
| TCELL56:OUT.8.TMIN | CMAC.RX_PTP_PCSLANE_OUT4 |
| TCELL56:OUT.10.TMIN | CMAC.STAT_RX_STATUS |
| TCELL56:OUT.12.TMIN | CMAC.STAT_RX_BROADCAST |
| TCELL56:OUT.14.TMIN | CMAC.DRP_RDY |
| TCELL56:OUT.17.TMIN | CMAC.TX_SERDES_DATA9_0 |
| TCELL56:OUT.19.TMIN | CMAC.TX_SERDES_DATA9_1 |
| TCELL56:OUT.21.TMIN | CMAC.TX_SERDES_DATA9_2 |
| TCELL56:OUT.23.TMIN | CMAC.TX_SERDES_DATA9_3 |
| TCELL56:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC163 |
| TCELL56:OUT.25.TMIN | CMAC.TX_SERDES_DATA9_4 |
| TCELL56:OUT.27.TMIN | CMAC.TX_SERDES_DATA9_5 |
| TCELL56:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC103 |
| TCELL56:OUT.29.TMIN | CMAC.TX_SERDES_DATA9_6 |
| TCELL56:OUT.31.TMIN | CMAC.TX_SERDES_DATA9_7 |
| TCELL56:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA9_7 |
| TCELL56:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA9_0 |
| TCELL56:IMUX.IMUX.42.DELAY | CMAC.RX_SERDES_DATA9_29 |
| TCELL57:OUT.0.TMIN | CMAC.STAT_RX_PACKET_SMALL0 |
| TCELL57:OUT.2.TMIN | CMAC.STAT_RX_PACKET_SMALL1 |
| TCELL57:OUT.4.TMIN | CMAC.STAT_RX_PACKET_SMALL2 |
| TCELL57:OUT.6.TMIN | CMAC.STAT_RX_PACKET_SMALL3 |
| TCELL57:OUT.8.TMIN | CMAC.STAT_RX_PACKET_LARGE |
| TCELL57:OUT.10.TMIN | CMAC.STAT_RX_PACKET_BAD_FCS |
| TCELL57:OUT.12.TMIN | CMAC.STAT_RX_UNICAST |
| TCELL57:OUT.14.TMIN | CMAC.STAT_RX_TRUNCATED |
| TCELL57:OUT.15.TMIN | CMAC.TX_SERDES_DATA9_8 |
| TCELL57:OUT.17.TMIN | CMAC.TX_SERDES_DATA9_9 |
| TCELL57:OUT.19.TMIN | CMAC.TX_SERDES_DATA9_10 |
| TCELL57:OUT.21.TMIN | CMAC.TX_SERDES_DATA9_11 |
| TCELL57:OUT.23.TMIN | CMAC.TX_SERDES_DATA9_12 |
| TCELL57:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC162 |
| TCELL57:OUT.25.TMIN | CMAC.TX_SERDES_DATA9_13 |
| TCELL57:OUT.27.TMIN | CMAC.TX_SERDES_DATA9_14 |
| TCELL57:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC102 |
| TCELL57:OUT.29.TMIN | CMAC.TX_SERDES_DATA9_15 |
| TCELL57:IMUX.CTRL.3 | CMAC.DRP_CLK_B |
| TCELL57:IMUX.IMUX.0.DELAY | CMAC.RX_SERDES_DATA9_5 |
| TCELL57:IMUX.IMUX.7.DELAY | CMAC.RX_SERDES_DATA9_18 |
| TCELL57:IMUX.IMUX.8.DELAY | CMAC.RX_SERDES_DATA9_8 |
| TCELL57:IMUX.IMUX.14.DELAY | CMAC.RX_SERDES_DATA9_12 |
| TCELL57:IMUX.IMUX.17.DELAY | CMAC.RX_SERDES_DATA9_9 |
| TCELL57:IMUX.IMUX.19.DELAY | CMAC.RX_SERDES_DATA9_13 |
| TCELL57:IMUX.IMUX.20.DELAY | CMAC.RX_SERDES_DATA9_4 |
| TCELL57:IMUX.IMUX.23.DELAY | CMAC.RX_SERDES_DATA9_3 |
| TCELL57:IMUX.IMUX.25.DELAY | CMAC.RX_SERDES_DATA9_28 |
| TCELL57:IMUX.IMUX.28.DELAY | CMAC.RX_SERDES_DATA9_2 |
| TCELL57:IMUX.IMUX.29.DELAY | CMAC.RX_SERDES_DATA9_17 |
| TCELL57:IMUX.IMUX.33.DELAY | CMAC.RX_SERDES_DATA9_10 |
| TCELL57:IMUX.IMUX.35.DELAY | CMAC.RX_SERDES_DATA9_30 |
| TCELL57:IMUX.IMUX.39.DELAY | CMAC.RX_SERDES_DATA9_15 |
| TCELL57:IMUX.IMUX.40.DELAY | CMAC.RX_SERDES_DATA9_25 |
| TCELL57:IMUX.IMUX.42.DELAY | CMAC.RX_SERDES_DATA9_11 |
| TCELL57:IMUX.IMUX.43.DELAY | CMAC.RX_SERDES_DATA9_6 |
| TCELL57:IMUX.IMUX.46.DELAY | CMAC.RX_SERDES_DATA9_1 |
| TCELL58:OUT.0.TMIN | CMAC.DRP_DO8 |
| TCELL58:OUT.2.TMIN | CMAC.DRP_DO9 |
| TCELL58:OUT.4.TMIN | CMAC.DRP_DO10 |
| TCELL58:OUT.6.TMIN | CMAC.DRP_DO11 |
| TCELL58:OUT.8.TMIN | CMAC.DRP_DO12 |
| TCELL58:OUT.10.TMIN | CMAC.DRP_DO13 |
| TCELL58:OUT.12.TMIN | CMAC.DRP_DO14 |
| TCELL58:OUT.14.TMIN | CMAC.DRP_DO15 |
| TCELL58:OUT.15.TMIN | CMAC.TX_SERDES_DATA9_17 |
| TCELL58:OUT.17.TMIN | CMAC.TX_SERDES_DATA9_18 |
| TCELL58:OUT.19.TMIN | CMAC.TX_SERDES_DATA9_19 |
| TCELL58:OUT.21.TMIN | CMAC.TX_SERDES_DATA9_20 |
| TCELL58:OUT.23.TMIN | CMAC.TX_SERDES_DATA9_21 |
| TCELL58:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC161 |
| TCELL58:OUT.25.TMIN | CMAC.TX_SERDES_DATA9_22 |
| TCELL58:OUT.27.TMIN | CMAC.TX_SERDES_DATA9_23 |
| TCELL58:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC101 |
| TCELL58:OUT.31.TMIN | CMAC.TX_SERDES_DATA9_16 |
| TCELL58:IMUX.IMUX.1.DELAY | CMAC.RX_SERDES_DATA9_23 |
| TCELL58:IMUX.IMUX.6.DELAY | CMAC.RX_SERDES_DATA9_16 |
| TCELL58:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA9_20 |
| TCELL58:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA9_21 |
| TCELL59:OUT.0.TMIN | CMAC.DRP_DO0 |
| TCELL59:OUT.2.TMIN | CMAC.DRP_DO1 |
| TCELL59:OUT.4.TMIN | CMAC.DRP_DO2 |
| TCELL59:OUT.6.TMIN | CMAC.DRP_DO3 |
| TCELL59:OUT.8.TMIN | CMAC.DRP_DO4 |
| TCELL59:OUT.10.TMIN | CMAC.DRP_DO5 |
| TCELL59:OUT.12.TMIN | CMAC.DRP_DO6 |
| TCELL59:OUT.14.TMIN | CMAC.DRP_DO7 |
| TCELL59:OUT.15.TMIN | CMAC.TX_SERDES_DATA9_26 |
| TCELL59:OUT.17.TMIN | CMAC.TX_SERDES_DATA9_27 |
| TCELL59:OUT.19.TMIN | CMAC.TX_SERDES_DATA9_28 |
| TCELL59:OUT.21.TMIN | CMAC.TX_SERDES_DATA9_29 |
| TCELL59:OUT.23.TMIN | CMAC.TX_SERDES_DATA9_30 |
| TCELL59:OUT.24.TMIN | CMAC.SCAN_OUT_CMAC160 |
| TCELL59:OUT.25.TMIN | CMAC.TX_SERDES_DATA9_31 |
| TCELL59:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC100 |
| TCELL59:OUT.29.TMIN | CMAC.TX_SERDES_DATA9_24 |
| TCELL59:OUT.31.TMIN | CMAC.TX_SERDES_DATA9_25 |
| TCELL59:IMUX.IMUX.3.DELAY | CMAC.RX_SERDES_DATA9_24 |
| TCELL59:IMUX.IMUX.9.DELAY | CMAC.RX_SERDES_DATA9_26 |
| TCELL59:IMUX.IMUX.12.DELAY | CMAC.RX_SERDES_DATA9_27 |
| TCELL59:IMUX.IMUX.18.DELAY | CMAC.RX_SERDES_DATA9_19 |
| TCELL59:IMUX.IMUX.21.DELAY | CMAC.RX_SERDES_DATA9_22 |
| TCELL59:IMUX.IMUX.24.DELAY | CMAC.RX_SERDES_DATA9_31 |
| TCELL59:IMUX.IMUX.43.DELAY | CMAC.RX_SERDES_DATA9_14 |
| TCELL60:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT0 |
| TCELL60:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC1 |
| TCELL60:OUT.3.TMIN | CMAC.TX_PTP_PCSLANE_OUT0 |
| TCELL60:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT1 |
| TCELL60:OUT.7.TMIN | CMAC.TX_PTP_PCSLANE_OUT1 |
| TCELL60:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT2 |
| TCELL60:OUT.11.TMIN | CMAC.TX_PTP_PCSLANE_OUT2 |
| TCELL60:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT3 |
| TCELL60:OUT.15.TMIN | CMAC.TX_PTP_PCSLANE_OUT3 |
| TCELL60:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT4 |
| TCELL60:OUT.19.TMIN | CMAC.TX_PTP_PCSLANE_OUT4 |
| TCELL60:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT5 |
| TCELL60:OUT.23.TMIN | CMAC.TX_PTP_TSTAMP_VALID_OUT |
| TCELL60:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT6 |
| TCELL60:OUT.27.TMIN | CMAC.STAT_TX_BAD_FCS |
| TCELL60:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC0 |
| TCELL60:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT7 |
| TCELL60:OUT.31.TMIN | CMAC.STAT_TX_BROADCAST |
| TCELL60:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_0 |
| TCELL60:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_64 |
| TCELL60:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_1 |
| TCELL60:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_65 |
| TCELL60:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_2 |
| TCELL60:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_66 |
| TCELL60:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_3 |
| TCELL60:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_67 |
| TCELL60:IMUX.IMUX.24.DELAY | CMAC.TX_ENAIN0 |
| TCELL60:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_4 |
| TCELL60:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_68 |
| TCELL60:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_5 |
| TCELL60:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_69 |
| TCELL60:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_6 |
| TCELL60:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_70 |
| TCELL60:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_7 |
| TCELL60:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_71 |
| TCELL61:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT8 |
| TCELL61:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC3 |
| TCELL61:OUT.3.TMIN | CMAC.STAT_TX_PACKET_1549_2047_BYTES |
| TCELL61:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT9 |
| TCELL61:OUT.7.TMIN | CMAC.STAT_TX_PACKET_1523_1548_BYTES |
| TCELL61:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT10 |
| TCELL61:OUT.11.TMIN | CMAC.STAT_TX_PACKET_1519_1522_BYTES |
| TCELL61:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT11 |
| TCELL61:OUT.15.TMIN | CMAC.STAT_TX_PACKET_128_255_BYTES |
| TCELL61:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT12 |
| TCELL61:OUT.19.TMIN | CMAC.STAT_TX_PACKET_1024_1518_BYTES |
| TCELL61:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT13 |
| TCELL61:OUT.23.TMIN | CMAC.STAT_TX_MULTICAST |
| TCELL61:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT14 |
| TCELL61:OUT.27.TMIN | CMAC.STAT_TX_LOCAL_FAULT |
| TCELL61:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC2 |
| TCELL61:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT15 |
| TCELL61:OUT.31.TMIN | CMAC.STAT_TX_FRAME_ERROR |
| TCELL61:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_8 |
| TCELL61:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_72 |
| TCELL61:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_9 |
| TCELL61:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_73 |
| TCELL61:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_10 |
| TCELL61:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_74 |
| TCELL61:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_11 |
| TCELL61:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_75 |
| TCELL61:IMUX.IMUX.24.DELAY | CMAC.TX_EOPIN0 |
| TCELL61:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_12 |
| TCELL61:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_76 |
| TCELL61:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_13 |
| TCELL61:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_77 |
| TCELL61:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_14 |
| TCELL61:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_78 |
| TCELL61:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_15 |
| TCELL61:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_79 |
| TCELL62:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT16 |
| TCELL62:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC5 |
| TCELL62:OUT.3.TMIN | CMAC.STAT_TX_PACKET_2048_4095_BYTES |
| TCELL62:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT17 |
| TCELL62:OUT.7.TMIN | CMAC.STAT_TX_PACKET_256_511_BYTES |
| TCELL62:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT18 |
| TCELL62:OUT.11.TMIN | CMAC.STAT_TX_PACKET_4096_8191_BYTES |
| TCELL62:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT19 |
| TCELL62:OUT.15.TMIN | CMAC.STAT_TX_PACKET_512_1023_BYTES |
| TCELL62:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT20 |
| TCELL62:OUT.19.TMIN | CMAC.STAT_TX_PACKET_64_BYTES |
| TCELL62:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT21 |
| TCELL62:OUT.23.TMIN | CMAC.STAT_TX_PACKET_65_127_BYTES |
| TCELL62:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT22 |
| TCELL62:OUT.27.TMIN | CMAC.STAT_TX_PACKET_8192_9215_BYTES |
| TCELL62:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC4 |
| TCELL62:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT23 |
| TCELL62:OUT.31.TMIN | CMAC.STAT_TX_PACKET_LARGE |
| TCELL62:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_16 |
| TCELL62:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_80 |
| TCELL62:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_17 |
| TCELL62:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_81 |
| TCELL62:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_18 |
| TCELL62:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_82 |
| TCELL62:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_19 |
| TCELL62:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_83 |
| TCELL62:IMUX.IMUX.24.DELAY | CMAC.TX_SOPIN0 |
| TCELL62:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_20 |
| TCELL62:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_84 |
| TCELL62:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_21 |
| TCELL62:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_85 |
| TCELL62:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_22 |
| TCELL62:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_86 |
| TCELL62:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_23 |
| TCELL62:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_87 |
| TCELL63:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT24 |
| TCELL63:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC7 |
| TCELL63:OUT.3.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES8 |
| TCELL63:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT25 |
| TCELL63:OUT.7.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES9 |
| TCELL63:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT26 |
| TCELL63:OUT.11.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES10 |
| TCELL63:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT27 |
| TCELL63:OUT.15.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES11 |
| TCELL63:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT28 |
| TCELL63:OUT.19.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES12 |
| TCELL63:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT29 |
| TCELL63:OUT.23.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES13 |
| TCELL63:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT30 |
| TCELL63:OUT.27.TMIN | CMAC.STAT_TX_PAUSE |
| TCELL63:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC6 |
| TCELL63:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT31 |
| TCELL63:OUT.31.TMIN | CMAC.STAT_TX_PACKET_SMALL |
| TCELL63:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_24 |
| TCELL63:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_88 |
| TCELL63:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_25 |
| TCELL63:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_89 |
| TCELL63:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_26 |
| TCELL63:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_90 |
| TCELL63:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_27 |
| TCELL63:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_91 |
| TCELL63:IMUX.IMUX.24.DELAY | CMAC.TX_ERRIN0 |
| TCELL63:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_28 |
| TCELL63:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_92 |
| TCELL63:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_29 |
| TCELL63:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_93 |
| TCELL63:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_30 |
| TCELL63:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_94 |
| TCELL63:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_31 |
| TCELL63:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_95 |
| TCELL64:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT32 |
| TCELL64:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC9 |
| TCELL64:OUT.3.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES0 |
| TCELL64:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT33 |
| TCELL64:OUT.7.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES1 |
| TCELL64:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT34 |
| TCELL64:OUT.11.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES2 |
| TCELL64:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT35 |
| TCELL64:OUT.15.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES3 |
| TCELL64:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT36 |
| TCELL64:OUT.19.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES4 |
| TCELL64:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT37 |
| TCELL64:OUT.23.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES5 |
| TCELL64:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT38 |
| TCELL64:OUT.27.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES6 |
| TCELL64:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC8 |
| TCELL64:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT39 |
| TCELL64:OUT.31.TMIN | CMAC.STAT_TX_TOTAL_GOOD_BYTES7 |
| TCELL64:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_32 |
| TCELL64:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_96 |
| TCELL64:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_33 |
| TCELL64:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_97 |
| TCELL64:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_34 |
| TCELL64:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_98 |
| TCELL64:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_35 |
| TCELL64:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_99 |
| TCELL64:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN0_0 |
| TCELL64:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_36 |
| TCELL64:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_100 |
| TCELL64:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_37 |
| TCELL64:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_101 |
| TCELL64:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_38 |
| TCELL64:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_102 |
| TCELL64:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_39 |
| TCELL64:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_103 |
| TCELL65:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT40 |
| TCELL65:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC11 |
| TCELL65:OUT.3.TMIN | CMAC.STAT_TX_PAUSE_VALID0 |
| TCELL65:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT41 |
| TCELL65:OUT.7.TMIN | CMAC.STAT_TX_PAUSE_VALID1 |
| TCELL65:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT42 |
| TCELL65:OUT.11.TMIN | CMAC.STAT_TX_PAUSE_VALID2 |
| TCELL65:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT43 |
| TCELL65:OUT.15.TMIN | CMAC.STAT_TX_PAUSE_VALID3 |
| TCELL65:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT44 |
| TCELL65:OUT.19.TMIN | CMAC.STAT_TX_PAUSE_VALID4 |
| TCELL65:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT45 |
| TCELL65:OUT.23.TMIN | CMAC.STAT_TX_PAUSE_VALID5 |
| TCELL65:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT46 |
| TCELL65:OUT.27.TMIN | CMAC.STAT_TX_PAUSE_VALID6 |
| TCELL65:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC10 |
| TCELL65:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT47 |
| TCELL65:OUT.31.TMIN | CMAC.STAT_TX_PAUSE_VALID7 |
| TCELL65:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_40 |
| TCELL65:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_104 |
| TCELL65:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_41 |
| TCELL65:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_105 |
| TCELL65:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_42 |
| TCELL65:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_106 |
| TCELL65:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_43 |
| TCELL65:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_107 |
| TCELL65:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN0_1 |
| TCELL65:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_44 |
| TCELL65:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_108 |
| TCELL65:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_45 |
| TCELL65:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_109 |
| TCELL65:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_46 |
| TCELL65:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_110 |
| TCELL65:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_47 |
| TCELL65:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_111 |
| TCELL66:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT48 |
| TCELL66:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC13 |
| TCELL66:OUT.3.TMIN | CMAC.STAT_TX_PAUSE_VALID8 |
| TCELL66:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT49 |
| TCELL66:OUT.7.TMIN | CMAC.STAT_TX_TOTAL_BYTES0 |
| TCELL66:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT50 |
| TCELL66:OUT.11.TMIN | CMAC.STAT_TX_TOTAL_BYTES1 |
| TCELL66:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT51 |
| TCELL66:OUT.15.TMIN | CMAC.STAT_TX_TOTAL_BYTES2 |
| TCELL66:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT52 |
| TCELL66:OUT.19.TMIN | CMAC.STAT_TX_TOTAL_BYTES3 |
| TCELL66:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT53 |
| TCELL66:OUT.23.TMIN | CMAC.STAT_TX_TOTAL_BYTES4 |
| TCELL66:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT54 |
| TCELL66:OUT.27.TMIN | CMAC.STAT_TX_TOTAL_BYTES5 |
| TCELL66:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC12 |
| TCELL66:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT55 |
| TCELL66:OUT.31.TMIN | CMAC.STAT_TX_TOTAL_BYTES6 |
| TCELL66:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_48 |
| TCELL66:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_112 |
| TCELL66:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_49 |
| TCELL66:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_113 |
| TCELL66:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_50 |
| TCELL66:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_114 |
| TCELL66:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_51 |
| TCELL66:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_115 |
| TCELL66:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN0_2 |
| TCELL66:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_52 |
| TCELL66:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_116 |
| TCELL66:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_53 |
| TCELL66:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_117 |
| TCELL66:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_54 |
| TCELL66:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_118 |
| TCELL66:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_55 |
| TCELL66:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_119 |
| TCELL67:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT56 |
| TCELL67:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC15 |
| TCELL67:OUT.3.TMIN | CMAC.TX_UNFOUT |
| TCELL67:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT57 |
| TCELL67:OUT.7.TMIN | CMAC.STAT_TX_VLAN |
| TCELL67:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT58 |
| TCELL67:OUT.11.TMIN | CMAC.STAT_TX_USER_PAUSE |
| TCELL67:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT59 |
| TCELL67:OUT.15.TMIN | CMAC.STAT_TX_UNICAST |
| TCELL67:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT60 |
| TCELL67:OUT.19.TMIN | CMAC.STAT_TX_TOTAL_PACKETS |
| TCELL67:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT61 |
| TCELL67:OUT.23.TMIN | CMAC.STAT_TX_TOTAL_GOOD_PACKETS |
| TCELL67:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT62 |
| TCELL67:OUT.27.TMIN | CMAC.STAT_TX_PTP_FIFO_WRITE_ERROR |
| TCELL67:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC14 |
| TCELL67:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT63 |
| TCELL67:OUT.31.TMIN | CMAC.STAT_TX_PTP_FIFO_READ_ERROR |
| TCELL67:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN0_56 |
| TCELL67:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN0_120 |
| TCELL67:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN0_57 |
| TCELL67:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN0_121 |
| TCELL67:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN0_58 |
| TCELL67:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN0_122 |
| TCELL67:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN0_59 |
| TCELL67:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN0_123 |
| TCELL67:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN0_3 |
| TCELL67:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN0_60 |
| TCELL67:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN0_124 |
| TCELL67:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN0_61 |
| TCELL67:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN0_125 |
| TCELL67:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN0_62 |
| TCELL67:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN0_126 |
| TCELL67:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN0_63 |
| TCELL67:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN0_127 |
| TCELL68:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT64 |
| TCELL68:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC17 |
| TCELL68:OUT.3.TMIN | CMAC.TX_RDYOUT |
| TCELL68:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT65 |
| TCELL68:OUT.7.TMIN | CMAC.TX_OVFOUT |
| TCELL68:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT66 |
| TCELL68:OUT.11.TMIN | CMAC.STAT_RX_STOMPED_FCS0 |
| TCELL68:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT67 |
| TCELL68:OUT.15.TMIN | CMAC.STAT_RX_STOMPED_FCS1 |
| TCELL68:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT68 |
| TCELL68:OUT.19.TMIN | CMAC.STAT_RX_STOMPED_FCS2 |
| TCELL68:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT69 |
| TCELL68:OUT.23.TMIN | CMAC.STAT_RX_STOMPED_FCS3 |
| TCELL68:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT70 |
| TCELL68:OUT.27.TMIN | CMAC.STAT_RX_REMOTE_FAULT |
| TCELL68:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC16 |
| TCELL68:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT71 |
| TCELL68:OUT.31.TMIN | CMAC.STAT_RX_RECEIVED_LOCAL_FAULT |
| TCELL68:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_0 |
| TCELL68:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_64 |
| TCELL68:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_1 |
| TCELL68:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_65 |
| TCELL68:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_2 |
| TCELL68:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_66 |
| TCELL68:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_3 |
| TCELL68:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_67 |
| TCELL68:IMUX.IMUX.24.DELAY | CMAC.TX_ENAIN1 |
| TCELL68:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_4 |
| TCELL68:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_68 |
| TCELL68:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_5 |
| TCELL68:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_69 |
| TCELL68:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_6 |
| TCELL68:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_70 |
| TCELL68:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_7 |
| TCELL68:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_71 |
| TCELL69:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_OUT72 |
| TCELL69:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC19 |
| TCELL69:OUT.3.TMIN | CMAC.STAT_RX_BLOCK_LOCK0 |
| TCELL69:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_OUT73 |
| TCELL69:OUT.7.TMIN | CMAC.STAT_RX_BLOCK_LOCK1 |
| TCELL69:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_OUT74 |
| TCELL69:OUT.11.TMIN | CMAC.STAT_RX_BLOCK_LOCK2 |
| TCELL69:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_OUT75 |
| TCELL69:OUT.15.TMIN | CMAC.STAT_RX_BLOCK_LOCK3 |
| TCELL69:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_OUT76 |
| TCELL69:OUT.19.TMIN | CMAC.STAT_RX_BLOCK_LOCK4 |
| TCELL69:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_OUT77 |
| TCELL69:OUT.23.TMIN | CMAC.STAT_RX_BLOCK_LOCK5 |
| TCELL69:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_OUT78 |
| TCELL69:OUT.27.TMIN | CMAC.STAT_RX_BLOCK_LOCK6 |
| TCELL69:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC18 |
| TCELL69:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_OUT79 |
| TCELL69:OUT.31.TMIN | CMAC.STAT_RX_BLOCK_LOCK7 |
| TCELL69:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_8 |
| TCELL69:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_72 |
| TCELL69:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_9 |
| TCELL69:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_73 |
| TCELL69:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_10 |
| TCELL69:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_74 |
| TCELL69:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_11 |
| TCELL69:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_75 |
| TCELL69:IMUX.IMUX.24.DELAY | CMAC.TX_EOPIN1 |
| TCELL69:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_12 |
| TCELL69:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_76 |
| TCELL69:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_13 |
| TCELL69:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_77 |
| TCELL69:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_14 |
| TCELL69:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_78 |
| TCELL69:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_15 |
| TCELL69:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_79 |
| TCELL70:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT0 |
| TCELL70:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC21 |
| TCELL70:OUT.3.TMIN | CMAC.STAT_RX_BLOCK_LOCK8 |
| TCELL70:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT1 |
| TCELL70:OUT.7.TMIN | CMAC.STAT_RX_BLOCK_LOCK9 |
| TCELL70:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT2 |
| TCELL70:OUT.11.TMIN | CMAC.STAT_RX_BLOCK_LOCK10 |
| TCELL70:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT3 |
| TCELL70:OUT.15.TMIN | CMAC.STAT_RX_BLOCK_LOCK11 |
| TCELL70:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT4 |
| TCELL70:OUT.19.TMIN | CMAC.STAT_RX_BLOCK_LOCK12 |
| TCELL70:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT5 |
| TCELL70:OUT.23.TMIN | CMAC.STAT_RX_BLOCK_LOCK13 |
| TCELL70:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT6 |
| TCELL70:OUT.27.TMIN | CMAC.STAT_RX_BLOCK_LOCK14 |
| TCELL70:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC20 |
| TCELL70:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT7 |
| TCELL70:OUT.31.TMIN | CMAC.STAT_RX_BLOCK_LOCK15 |
| TCELL70:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_16 |
| TCELL70:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_80 |
| TCELL70:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_17 |
| TCELL70:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_81 |
| TCELL70:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_18 |
| TCELL70:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_82 |
| TCELL70:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_19 |
| TCELL70:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_83 |
| TCELL70:IMUX.IMUX.24.DELAY | CMAC.TX_SOPIN1 |
| TCELL70:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_20 |
| TCELL70:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_84 |
| TCELL70:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_21 |
| TCELL70:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_85 |
| TCELL70:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_22 |
| TCELL70:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_86 |
| TCELL70:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_23 |
| TCELL70:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_87 |
| TCELL71:OUT.1.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT8 |
| TCELL71:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC23 |
| TCELL71:OUT.3.TMIN | CMAC.STAT_RX_BLOCK_LOCK16 |
| TCELL71:OUT.5.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT9 |
| TCELL71:OUT.7.TMIN | CMAC.STAT_RX_BLOCK_LOCK17 |
| TCELL71:OUT.9.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT10 |
| TCELL71:OUT.11.TMIN | CMAC.STAT_RX_BLOCK_LOCK18 |
| TCELL71:OUT.13.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT11 |
| TCELL71:OUT.15.TMIN | CMAC.STAT_RX_BLOCK_LOCK19 |
| TCELL71:OUT.17.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT12 |
| TCELL71:OUT.19.TMIN | CMAC.STAT_RX_FRAGMENT0 |
| TCELL71:OUT.21.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT13 |
| TCELL71:OUT.23.TMIN | CMAC.STAT_RX_FRAGMENT1 |
| TCELL71:OUT.25.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT14 |
| TCELL71:OUT.27.TMIN | CMAC.STAT_RX_FRAGMENT2 |
| TCELL71:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC22 |
| TCELL71:OUT.29.TMIN | CMAC.TX_PTP_TSTAMP_TAG_OUT15 |
| TCELL71:OUT.31.TMIN | CMAC.STAT_RX_FRAGMENT3 |
| TCELL71:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_24 |
| TCELL71:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_88 |
| TCELL71:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_25 |
| TCELL71:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_89 |
| TCELL71:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_26 |
| TCELL71:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_90 |
| TCELL71:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_27 |
| TCELL71:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_91 |
| TCELL71:IMUX.IMUX.24.DELAY | CMAC.TX_ERRIN1 |
| TCELL71:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_28 |
| TCELL71:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_92 |
| TCELL71:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_29 |
| TCELL71:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_93 |
| TCELL71:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_30 |
| TCELL71:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_94 |
| TCELL71:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_31 |
| TCELL71:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_95 |
| TCELL72:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_0_0 |
| TCELL72:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC25 |
| TCELL72:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_10_0 |
| TCELL72:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_0_1 |
| TCELL72:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_10_1 |
| TCELL72:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_0_2 |
| TCELL72:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_10_2 |
| TCELL72:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_0_3 |
| TCELL72:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_10_3 |
| TCELL72:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_1_0 |
| TCELL72:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_11_0 |
| TCELL72:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_1_1 |
| TCELL72:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_11_1 |
| TCELL72:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_1_2 |
| TCELL72:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_11_2 |
| TCELL72:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC24 |
| TCELL72:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_1_3 |
| TCELL72:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_11_3 |
| TCELL72:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_32 |
| TCELL72:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_96 |
| TCELL72:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_33 |
| TCELL72:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_97 |
| TCELL72:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_34 |
| TCELL72:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_98 |
| TCELL72:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_35 |
| TCELL72:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_99 |
| TCELL72:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN1_0 |
| TCELL72:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_36 |
| TCELL72:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_100 |
| TCELL72:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_37 |
| TCELL72:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_101 |
| TCELL72:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_38 |
| TCELL72:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_102 |
| TCELL72:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_39 |
| TCELL72:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_103 |
| TCELL73:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_2_0 |
| TCELL73:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC27 |
| TCELL73:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_12_0 |
| TCELL73:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_2_1 |
| TCELL73:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_12_1 |
| TCELL73:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_2_2 |
| TCELL73:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_12_2 |
| TCELL73:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_2_3 |
| TCELL73:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_12_3 |
| TCELL73:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_3_0 |
| TCELL73:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_13_0 |
| TCELL73:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_3_1 |
| TCELL73:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_13_1 |
| TCELL73:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_3_2 |
| TCELL73:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_13_2 |
| TCELL73:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC26 |
| TCELL73:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_3_3 |
| TCELL73:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_13_3 |
| TCELL73:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_40 |
| TCELL73:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_104 |
| TCELL73:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_41 |
| TCELL73:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_105 |
| TCELL73:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_42 |
| TCELL73:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_106 |
| TCELL73:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_43 |
| TCELL73:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_107 |
| TCELL73:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN1_1 |
| TCELL73:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_44 |
| TCELL73:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_108 |
| TCELL73:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_45 |
| TCELL73:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_109 |
| TCELL73:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_46 |
| TCELL73:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_110 |
| TCELL73:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_47 |
| TCELL73:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_111 |
| TCELL74:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_4_0 |
| TCELL74:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC29 |
| TCELL74:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_14_0 |
| TCELL74:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_4_1 |
| TCELL74:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_14_1 |
| TCELL74:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_4_2 |
| TCELL74:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_14_2 |
| TCELL74:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_4_3 |
| TCELL74:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_14_3 |
| TCELL74:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_5_0 |
| TCELL74:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_15_0 |
| TCELL74:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_5_1 |
| TCELL74:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_15_1 |
| TCELL74:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_5_2 |
| TCELL74:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_15_2 |
| TCELL74:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC28 |
| TCELL74:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_5_3 |
| TCELL74:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_15_3 |
| TCELL74:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_48 |
| TCELL74:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_112 |
| TCELL74:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_49 |
| TCELL74:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_113 |
| TCELL74:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_50 |
| TCELL74:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_114 |
| TCELL74:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_51 |
| TCELL74:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_115 |
| TCELL74:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN1_2 |
| TCELL74:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_52 |
| TCELL74:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_116 |
| TCELL74:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_53 |
| TCELL74:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_117 |
| TCELL74:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_54 |
| TCELL74:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_118 |
| TCELL74:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_55 |
| TCELL74:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_119 |
| TCELL75:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_6_0 |
| TCELL75:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC31 |
| TCELL75:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_16_0 |
| TCELL75:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_6_1 |
| TCELL75:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_16_1 |
| TCELL75:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_6_2 |
| TCELL75:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_16_2 |
| TCELL75:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_6_3 |
| TCELL75:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_16_3 |
| TCELL75:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_7_0 |
| TCELL75:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_17_0 |
| TCELL75:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_7_1 |
| TCELL75:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_17_1 |
| TCELL75:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_7_2 |
| TCELL75:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_17_2 |
| TCELL75:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC30 |
| TCELL75:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_7_3 |
| TCELL75:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_17_3 |
| TCELL75:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN1_56 |
| TCELL75:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN1_120 |
| TCELL75:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN1_57 |
| TCELL75:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN1_121 |
| TCELL75:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN1_58 |
| TCELL75:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN1_122 |
| TCELL75:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN1_59 |
| TCELL75:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN1_123 |
| TCELL75:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN1_3 |
| TCELL75:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN1_60 |
| TCELL75:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN1_124 |
| TCELL75:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN1_61 |
| TCELL75:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN1_125 |
| TCELL75:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN1_62 |
| TCELL75:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN1_126 |
| TCELL75:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN1_63 |
| TCELL75:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN1_127 |
| TCELL76:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_8_0 |
| TCELL76:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC33 |
| TCELL76:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_18_0 |
| TCELL76:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_8_1 |
| TCELL76:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_18_1 |
| TCELL76:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_8_2 |
| TCELL76:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_18_2 |
| TCELL76:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_8_3 |
| TCELL76:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_18_3 |
| TCELL76:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_9_0 |
| TCELL76:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_19_0 |
| TCELL76:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_9_1 |
| TCELL76:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_19_1 |
| TCELL76:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_9_2 |
| TCELL76:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_19_2 |
| TCELL76:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC32 |
| TCELL76:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_9_3 |
| TCELL76:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_19_3 |
| TCELL76:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_0 |
| TCELL76:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_64 |
| TCELL76:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_1 |
| TCELL76:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_65 |
| TCELL76:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_2 |
| TCELL76:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_66 |
| TCELL76:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_3 |
| TCELL76:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_67 |
| TCELL76:IMUX.IMUX.24.DELAY | CMAC.TX_ENAIN2 |
| TCELL76:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_4 |
| TCELL76:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_68 |
| TCELL76:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_5 |
| TCELL76:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_69 |
| TCELL76:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_6 |
| TCELL76:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_70 |
| TCELL76:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_7 |
| TCELL76:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_71 |
| TCELL77:OUT.1.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_0 |
| TCELL77:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC35 |
| TCELL77:OUT.3.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_10 |
| TCELL77:OUT.5.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_1 |
| TCELL77:OUT.7.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_11 |
| TCELL77:OUT.9.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_2 |
| TCELL77:OUT.11.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_12 |
| TCELL77:OUT.13.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_3 |
| TCELL77:OUT.15.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_13 |
| TCELL77:OUT.17.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_4 |
| TCELL77:OUT.19.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_14 |
| TCELL77:OUT.21.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_5 |
| TCELL77:OUT.23.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_15 |
| TCELL77:OUT.25.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_6 |
| TCELL77:OUT.27.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_16 |
| TCELL77:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC34 |
| TCELL77:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_7 |
| TCELL77:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_17 |
| TCELL77:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_8 |
| TCELL77:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_72 |
| TCELL77:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_9 |
| TCELL77:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_73 |
| TCELL77:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_10 |
| TCELL77:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_74 |
| TCELL77:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_11 |
| TCELL77:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_75 |
| TCELL77:IMUX.IMUX.24.DELAY | CMAC.TX_EOPIN2 |
| TCELL77:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_12 |
| TCELL77:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_76 |
| TCELL77:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_13 |
| TCELL77:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_77 |
| TCELL77:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_14 |
| TCELL77:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_78 |
| TCELL77:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_15 |
| TCELL77:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_79 |
| TCELL78:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_0 |
| TCELL78:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC37 |
| TCELL78:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_0 |
| TCELL78:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_1 |
| TCELL78:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_1 |
| TCELL78:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_2 |
| TCELL78:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_2 |
| TCELL78:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_3 |
| TCELL78:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_3 |
| TCELL78:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_4 |
| TCELL78:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_4 |
| TCELL78:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_5 |
| TCELL78:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_5 |
| TCELL78:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_19_6 |
| TCELL78:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_18_6 |
| TCELL78:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC36 |
| TCELL78:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_8 |
| TCELL78:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_18 |
| TCELL78:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_16 |
| TCELL78:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_80 |
| TCELL78:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_17 |
| TCELL78:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_81 |
| TCELL78:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_18 |
| TCELL78:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_82 |
| TCELL78:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_19 |
| TCELL78:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_83 |
| TCELL78:IMUX.IMUX.24.DELAY | CMAC.TX_SOPIN2 |
| TCELL78:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_20 |
| TCELL78:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_84 |
| TCELL78:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_21 |
| TCELL78:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_85 |
| TCELL78:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_22 |
| TCELL78:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_86 |
| TCELL78:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_23 |
| TCELL78:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_87 |
| TCELL79:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_0 |
| TCELL79:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC39 |
| TCELL79:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_0 |
| TCELL79:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_1 |
| TCELL79:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_1 |
| TCELL79:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_2 |
| TCELL79:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_2 |
| TCELL79:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_3 |
| TCELL79:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_3 |
| TCELL79:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_4 |
| TCELL79:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_4 |
| TCELL79:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_5 |
| TCELL79:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_5 |
| TCELL79:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_17_6 |
| TCELL79:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_16_6 |
| TCELL79:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC38 |
| TCELL79:OUT.29.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_9 |
| TCELL79:OUT.31.TMIN | CMAC.STAT_RX_FRAMING_ERR_VALID_19 |
| TCELL79:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_24 |
| TCELL79:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_88 |
| TCELL79:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_25 |
| TCELL79:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_89 |
| TCELL79:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_26 |
| TCELL79:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_90 |
| TCELL79:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_27 |
| TCELL79:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_91 |
| TCELL79:IMUX.IMUX.24.DELAY | CMAC.TX_ERRIN2 |
| TCELL79:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_28 |
| TCELL79:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_92 |
| TCELL79:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_29 |
| TCELL79:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_93 |
| TCELL79:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_30 |
| TCELL79:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_94 |
| TCELL79:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_31 |
| TCELL79:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_95 |
| TCELL80:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_0 |
| TCELL80:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC41 |
| TCELL80:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_0 |
| TCELL80:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_1 |
| TCELL80:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_1 |
| TCELL80:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_2 |
| TCELL80:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_2 |
| TCELL80:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_3 |
| TCELL80:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_3 |
| TCELL80:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_4 |
| TCELL80:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_4 |
| TCELL80:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_5 |
| TCELL80:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_5 |
| TCELL80:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_15_6 |
| TCELL80:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_14_6 |
| TCELL80:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC40 |
| TCELL80:OUT.29.TMIN | CMAC.STAT_RX_MISALIGNED |
| TCELL80:OUT.31.TMIN | CMAC.STAT_RX_MULTICAST |
| TCELL80:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_32 |
| TCELL80:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_96 |
| TCELL80:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_33 |
| TCELL80:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_97 |
| TCELL80:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_34 |
| TCELL80:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_98 |
| TCELL80:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_35 |
| TCELL80:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_99 |
| TCELL80:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN2_0 |
| TCELL80:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_36 |
| TCELL80:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_100 |
| TCELL80:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_37 |
| TCELL80:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_101 |
| TCELL80:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_38 |
| TCELL80:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_102 |
| TCELL80:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_39 |
| TCELL80:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_103 |
| TCELL81:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_0 |
| TCELL81:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC43 |
| TCELL81:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_0 |
| TCELL81:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_1 |
| TCELL81:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_1 |
| TCELL81:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_2 |
| TCELL81:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_2 |
| TCELL81:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_3 |
| TCELL81:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_3 |
| TCELL81:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_4 |
| TCELL81:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_4 |
| TCELL81:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_5 |
| TCELL81:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_5 |
| TCELL81:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_13_6 |
| TCELL81:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_12_6 |
| TCELL81:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC42 |
| TCELL81:OUT.31.TMIN | CMAC.STAT_RX_OVERSIZE |
| TCELL81:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_40 |
| TCELL81:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_104 |
| TCELL81:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_41 |
| TCELL81:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_105 |
| TCELL81:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_42 |
| TCELL81:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_106 |
| TCELL81:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_43 |
| TCELL81:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_107 |
| TCELL81:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN2_1 |
| TCELL81:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_44 |
| TCELL81:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_108 |
| TCELL81:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_45 |
| TCELL81:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_109 |
| TCELL81:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_46 |
| TCELL81:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_110 |
| TCELL81:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_47 |
| TCELL81:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_111 |
| TCELL82:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_0 |
| TCELL82:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC45 |
| TCELL82:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_0 |
| TCELL82:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_1 |
| TCELL82:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_1 |
| TCELL82:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_2 |
| TCELL82:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_2 |
| TCELL82:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_3 |
| TCELL82:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_3 |
| TCELL82:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_4 |
| TCELL82:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_4 |
| TCELL82:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_5 |
| TCELL82:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_5 |
| TCELL82:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_11_6 |
| TCELL82:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_10_6 |
| TCELL82:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC44 |
| TCELL82:OUT.29.TMIN | CMAC.STAT_RX_PACKET_1024_1518_BYTES |
| TCELL82:OUT.31.TMIN | CMAC.STAT_RX_PACKET_128_255_BYTES |
| TCELL82:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_48 |
| TCELL82:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_112 |
| TCELL82:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_49 |
| TCELL82:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_113 |
| TCELL82:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_50 |
| TCELL82:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_114 |
| TCELL82:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_51 |
| TCELL82:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_115 |
| TCELL82:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN2_2 |
| TCELL82:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_52 |
| TCELL82:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_116 |
| TCELL82:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_53 |
| TCELL82:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_117 |
| TCELL82:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_54 |
| TCELL82:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_118 |
| TCELL82:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_55 |
| TCELL82:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_119 |
| TCELL83:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_0 |
| TCELL83:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC47 |
| TCELL83:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_0 |
| TCELL83:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_1 |
| TCELL83:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_1 |
| TCELL83:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_2 |
| TCELL83:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_2 |
| TCELL83:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_3 |
| TCELL83:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_3 |
| TCELL83:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_4 |
| TCELL83:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_4 |
| TCELL83:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_5 |
| TCELL83:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_5 |
| TCELL83:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_9_6 |
| TCELL83:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_8_6 |
| TCELL83:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC46 |
| TCELL83:OUT.29.TMIN | CMAC.STAT_RX_PACKET_1519_1522_BYTES |
| TCELL83:OUT.31.TMIN | CMAC.STAT_RX_PACKET_1523_1548_BYTES |
| TCELL83:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN2_56 |
| TCELL83:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN2_120 |
| TCELL83:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN2_57 |
| TCELL83:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN2_121 |
| TCELL83:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN2_58 |
| TCELL83:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN2_122 |
| TCELL83:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN2_59 |
| TCELL83:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN2_123 |
| TCELL83:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN2_3 |
| TCELL83:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN2_60 |
| TCELL83:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN2_124 |
| TCELL83:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN2_61 |
| TCELL83:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN2_125 |
| TCELL83:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN2_62 |
| TCELL83:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN2_126 |
| TCELL83:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN2_63 |
| TCELL83:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN2_127 |
| TCELL84:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_0 |
| TCELL84:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC49 |
| TCELL84:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_0 |
| TCELL84:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_1 |
| TCELL84:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_1 |
| TCELL84:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_2 |
| TCELL84:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_2 |
| TCELL84:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_3 |
| TCELL84:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_3 |
| TCELL84:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_4 |
| TCELL84:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_4 |
| TCELL84:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_5 |
| TCELL84:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_5 |
| TCELL84:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_7_6 |
| TCELL84:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_6_6 |
| TCELL84:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC48 |
| TCELL84:OUT.29.TMIN | CMAC.STAT_RX_PACKET_1549_2047_BYTES |
| TCELL84:OUT.31.TMIN | CMAC.STAT_RX_PACKET_2048_4095_BYTES |
| TCELL84:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_0 |
| TCELL84:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_64 |
| TCELL84:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_1 |
| TCELL84:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_65 |
| TCELL84:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_2 |
| TCELL84:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_66 |
| TCELL84:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_3 |
| TCELL84:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_67 |
| TCELL84:IMUX.IMUX.24.DELAY | CMAC.TX_ENAIN3 |
| TCELL84:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_4 |
| TCELL84:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_68 |
| TCELL84:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_5 |
| TCELL84:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_69 |
| TCELL84:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_6 |
| TCELL84:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_70 |
| TCELL84:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_7 |
| TCELL84:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_71 |
| TCELL85:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_0 |
| TCELL85:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC51 |
| TCELL85:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_0 |
| TCELL85:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_1 |
| TCELL85:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_1 |
| TCELL85:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_2 |
| TCELL85:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_2 |
| TCELL85:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_3 |
| TCELL85:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_3 |
| TCELL85:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_4 |
| TCELL85:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_4 |
| TCELL85:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_5 |
| TCELL85:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_5 |
| TCELL85:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_5_6 |
| TCELL85:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_4_6 |
| TCELL85:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC50 |
| TCELL85:OUT.29.TMIN | CMAC.STAT_RX_PACKET_256_511_BYTES |
| TCELL85:OUT.31.TMIN | CMAC.STAT_RX_PACKET_4096_8191_BYTES |
| TCELL85:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_8 |
| TCELL85:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_72 |
| TCELL85:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_9 |
| TCELL85:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_73 |
| TCELL85:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_10 |
| TCELL85:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_74 |
| TCELL85:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_11 |
| TCELL85:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_75 |
| TCELL85:IMUX.IMUX.24.DELAY | CMAC.TX_EOPIN3 |
| TCELL85:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_12 |
| TCELL85:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_76 |
| TCELL85:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_13 |
| TCELL85:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_77 |
| TCELL85:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_14 |
| TCELL85:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_78 |
| TCELL85:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_15 |
| TCELL85:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_79 |
| TCELL86:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_0 |
| TCELL86:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC53 |
| TCELL86:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_0 |
| TCELL86:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_1 |
| TCELL86:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_1 |
| TCELL86:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_2 |
| TCELL86:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_2 |
| TCELL86:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_3 |
| TCELL86:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_3 |
| TCELL86:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_4 |
| TCELL86:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_4 |
| TCELL86:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_5 |
| TCELL86:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_5 |
| TCELL86:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_3_6 |
| TCELL86:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_2_6 |
| TCELL86:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC52 |
| TCELL86:OUT.29.TMIN | CMAC.STAT_RX_PACKET_512_1023_BYTES |
| TCELL86:OUT.31.TMIN | CMAC.STAT_RX_PACKET_64_BYTES |
| TCELL86:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_16 |
| TCELL86:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_80 |
| TCELL86:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_17 |
| TCELL86:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_81 |
| TCELL86:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_18 |
| TCELL86:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_82 |
| TCELL86:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_19 |
| TCELL86:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_83 |
| TCELL86:IMUX.IMUX.24.DELAY | CMAC.TX_SOPIN3 |
| TCELL86:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_20 |
| TCELL86:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_84 |
| TCELL86:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_21 |
| TCELL86:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_85 |
| TCELL86:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_22 |
| TCELL86:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_86 |
| TCELL86:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_23 |
| TCELL86:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_87 |
| TCELL87:OUT.1.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_0 |
| TCELL87:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC55 |
| TCELL87:OUT.3.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_0 |
| TCELL87:OUT.5.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_1 |
| TCELL87:OUT.7.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_1 |
| TCELL87:OUT.9.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_2 |
| TCELL87:OUT.11.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_2 |
| TCELL87:OUT.13.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_3 |
| TCELL87:OUT.15.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_3 |
| TCELL87:OUT.17.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_4 |
| TCELL87:OUT.19.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_4 |
| TCELL87:OUT.21.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_5 |
| TCELL87:OUT.23.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_5 |
| TCELL87:OUT.25.TMIN | CMAC.RX_LANE_ALIGNER_FILL_1_6 |
| TCELL87:OUT.27.TMIN | CMAC.RX_LANE_ALIGNER_FILL_0_6 |
| TCELL87:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC54 |
| TCELL87:OUT.29.TMIN | CMAC.STAT_RX_PACKET_65_127_BYTES |
| TCELL87:OUT.31.TMIN | CMAC.STAT_RX_PACKET_8192_9215_BYTES |
| TCELL87:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_24 |
| TCELL87:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_88 |
| TCELL87:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_25 |
| TCELL87:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_89 |
| TCELL87:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_26 |
| TCELL87:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_90 |
| TCELL87:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_27 |
| TCELL87:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_91 |
| TCELL87:IMUX.IMUX.24.DELAY | CMAC.TX_ERRIN3 |
| TCELL87:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_28 |
| TCELL87:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_92 |
| TCELL87:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_29 |
| TCELL87:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_93 |
| TCELL87:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_30 |
| TCELL87:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_94 |
| TCELL87:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_31 |
| TCELL87:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_95 |
| TCELL88:OUT.1.TMIN | CMAC.RX_DATAOUT0_0 |
| TCELL88:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC57 |
| TCELL88:OUT.3.TMIN | CMAC.RX_DATAOUT0_64 |
| TCELL88:OUT.5.TMIN | CMAC.RX_DATAOUT0_1 |
| TCELL88:OUT.7.TMIN | CMAC.RX_DATAOUT0_65 |
| TCELL88:OUT.9.TMIN | CMAC.RX_DATAOUT0_2 |
| TCELL88:OUT.11.TMIN | CMAC.RX_DATAOUT0_66 |
| TCELL88:OUT.13.TMIN | CMAC.RX_DATAOUT0_3 |
| TCELL88:OUT.15.TMIN | CMAC.RX_DATAOUT0_67 |
| TCELL88:OUT.16.TMIN | CMAC.RX_ENAOUT0 |
| TCELL88:OUT.17.TMIN | CMAC.RX_DATAOUT0_4 |
| TCELL88:OUT.19.TMIN | CMAC.RX_DATAOUT0_68 |
| TCELL88:OUT.21.TMIN | CMAC.RX_DATAOUT0_5 |
| TCELL88:OUT.23.TMIN | CMAC.RX_DATAOUT0_69 |
| TCELL88:OUT.25.TMIN | CMAC.RX_DATAOUT0_6 |
| TCELL88:OUT.27.TMIN | CMAC.RX_DATAOUT0_70 |
| TCELL88:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC56 |
| TCELL88:OUT.29.TMIN | CMAC.RX_DATAOUT0_7 |
| TCELL88:OUT.31.TMIN | CMAC.RX_DATAOUT0_71 |
| TCELL88:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_32 |
| TCELL88:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_96 |
| TCELL88:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_33 |
| TCELL88:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_97 |
| TCELL88:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_34 |
| TCELL88:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_98 |
| TCELL88:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_35 |
| TCELL88:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_99 |
| TCELL88:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN3_0 |
| TCELL88:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_36 |
| TCELL88:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_100 |
| TCELL88:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_37 |
| TCELL88:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_101 |
| TCELL88:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_38 |
| TCELL88:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_102 |
| TCELL88:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_39 |
| TCELL88:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_103 |
| TCELL89:OUT.1.TMIN | CMAC.RX_DATAOUT0_8 |
| TCELL89:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC59 |
| TCELL89:OUT.3.TMIN | CMAC.RX_DATAOUT0_72 |
| TCELL89:OUT.5.TMIN | CMAC.RX_DATAOUT0_9 |
| TCELL89:OUT.7.TMIN | CMAC.RX_DATAOUT0_73 |
| TCELL89:OUT.9.TMIN | CMAC.RX_DATAOUT0_10 |
| TCELL89:OUT.11.TMIN | CMAC.RX_DATAOUT0_74 |
| TCELL89:OUT.13.TMIN | CMAC.RX_DATAOUT0_11 |
| TCELL89:OUT.15.TMIN | CMAC.RX_DATAOUT0_75 |
| TCELL89:OUT.16.TMIN | CMAC.RX_EOPOUT0 |
| TCELL89:OUT.17.TMIN | CMAC.RX_DATAOUT0_12 |
| TCELL89:OUT.19.TMIN | CMAC.RX_DATAOUT0_76 |
| TCELL89:OUT.21.TMIN | CMAC.RX_DATAOUT0_13 |
| TCELL89:OUT.23.TMIN | CMAC.RX_DATAOUT0_77 |
| TCELL89:OUT.25.TMIN | CMAC.RX_DATAOUT0_14 |
| TCELL89:OUT.27.TMIN | CMAC.RX_DATAOUT0_78 |
| TCELL89:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC58 |
| TCELL89:OUT.29.TMIN | CMAC.RX_DATAOUT0_15 |
| TCELL89:OUT.31.TMIN | CMAC.RX_DATAOUT0_79 |
| TCELL89:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_40 |
| TCELL89:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_104 |
| TCELL89:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_41 |
| TCELL89:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_105 |
| TCELL89:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_42 |
| TCELL89:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_106 |
| TCELL89:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_43 |
| TCELL89:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_107 |
| TCELL89:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN3_1 |
| TCELL89:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_44 |
| TCELL89:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_108 |
| TCELL89:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_45 |
| TCELL89:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_109 |
| TCELL89:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_46 |
| TCELL89:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_110 |
| TCELL89:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_47 |
| TCELL89:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_111 |
| TCELL90:OUT.1.TMIN | CMAC.RX_DATAOUT0_16 |
| TCELL90:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC61 |
| TCELL90:OUT.3.TMIN | CMAC.RX_DATAOUT0_80 |
| TCELL90:OUT.5.TMIN | CMAC.RX_DATAOUT0_17 |
| TCELL90:OUT.7.TMIN | CMAC.RX_DATAOUT0_81 |
| TCELL90:OUT.9.TMIN | CMAC.RX_DATAOUT0_18 |
| TCELL90:OUT.11.TMIN | CMAC.RX_DATAOUT0_82 |
| TCELL90:OUT.13.TMIN | CMAC.RX_DATAOUT0_19 |
| TCELL90:OUT.15.TMIN | CMAC.RX_DATAOUT0_83 |
| TCELL90:OUT.16.TMIN | CMAC.RX_SOPOUT0 |
| TCELL90:OUT.17.TMIN | CMAC.RX_DATAOUT0_20 |
| TCELL90:OUT.19.TMIN | CMAC.RX_DATAOUT0_84 |
| TCELL90:OUT.21.TMIN | CMAC.RX_DATAOUT0_21 |
| TCELL90:OUT.23.TMIN | CMAC.RX_DATAOUT0_85 |
| TCELL90:OUT.25.TMIN | CMAC.RX_DATAOUT0_22 |
| TCELL90:OUT.27.TMIN | CMAC.RX_DATAOUT0_86 |
| TCELL90:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC60 |
| TCELL90:OUT.29.TMIN | CMAC.RX_DATAOUT0_23 |
| TCELL90:OUT.31.TMIN | CMAC.RX_DATAOUT0_87 |
| TCELL90:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_48 |
| TCELL90:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_112 |
| TCELL90:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_49 |
| TCELL90:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_113 |
| TCELL90:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_50 |
| TCELL90:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_114 |
| TCELL90:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_51 |
| TCELL90:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_115 |
| TCELL90:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN3_2 |
| TCELL90:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_52 |
| TCELL90:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_116 |
| TCELL90:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_53 |
| TCELL90:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_117 |
| TCELL90:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_54 |
| TCELL90:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_118 |
| TCELL90:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_55 |
| TCELL90:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_119 |
| TCELL91:OUT.1.TMIN | CMAC.RX_DATAOUT0_24 |
| TCELL91:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC63 |
| TCELL91:OUT.3.TMIN | CMAC.RX_DATAOUT0_88 |
| TCELL91:OUT.5.TMIN | CMAC.RX_DATAOUT0_25 |
| TCELL91:OUT.7.TMIN | CMAC.RX_DATAOUT0_89 |
| TCELL91:OUT.9.TMIN | CMAC.RX_DATAOUT0_26 |
| TCELL91:OUT.11.TMIN | CMAC.RX_DATAOUT0_90 |
| TCELL91:OUT.13.TMIN | CMAC.RX_DATAOUT0_27 |
| TCELL91:OUT.15.TMIN | CMAC.RX_DATAOUT0_91 |
| TCELL91:OUT.16.TMIN | CMAC.RX_ERROUT0 |
| TCELL91:OUT.17.TMIN | CMAC.RX_DATAOUT0_28 |
| TCELL91:OUT.19.TMIN | CMAC.RX_DATAOUT0_92 |
| TCELL91:OUT.21.TMIN | CMAC.RX_DATAOUT0_29 |
| TCELL91:OUT.23.TMIN | CMAC.RX_DATAOUT0_93 |
| TCELL91:OUT.25.TMIN | CMAC.RX_DATAOUT0_30 |
| TCELL91:OUT.27.TMIN | CMAC.RX_DATAOUT0_94 |
| TCELL91:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC62 |
| TCELL91:OUT.29.TMIN | CMAC.RX_DATAOUT0_31 |
| TCELL91:OUT.31.TMIN | CMAC.RX_DATAOUT0_95 |
| TCELL91:IMUX.IMUX.1.DELAY | CMAC.TX_DATAIN3_56 |
| TCELL91:IMUX.IMUX.4.DELAY | CMAC.TX_DATAIN3_120 |
| TCELL91:IMUX.IMUX.7.DELAY | CMAC.TX_DATAIN3_57 |
| TCELL91:IMUX.IMUX.10.DELAY | CMAC.TX_DATAIN3_121 |
| TCELL91:IMUX.IMUX.13.DELAY | CMAC.TX_DATAIN3_58 |
| TCELL91:IMUX.IMUX.16.DELAY | CMAC.TX_DATAIN3_122 |
| TCELL91:IMUX.IMUX.19.DELAY | CMAC.TX_DATAIN3_59 |
| TCELL91:IMUX.IMUX.22.DELAY | CMAC.TX_DATAIN3_123 |
| TCELL91:IMUX.IMUX.24.DELAY | CMAC.TX_MTYIN3_3 |
| TCELL91:IMUX.IMUX.25.DELAY | CMAC.TX_DATAIN3_60 |
| TCELL91:IMUX.IMUX.28.DELAY | CMAC.TX_DATAIN3_124 |
| TCELL91:IMUX.IMUX.31.DELAY | CMAC.TX_DATAIN3_61 |
| TCELL91:IMUX.IMUX.34.DELAY | CMAC.TX_DATAIN3_125 |
| TCELL91:IMUX.IMUX.37.DELAY | CMAC.TX_DATAIN3_62 |
| TCELL91:IMUX.IMUX.40.DELAY | CMAC.TX_DATAIN3_126 |
| TCELL91:IMUX.IMUX.43.DELAY | CMAC.TX_DATAIN3_63 |
| TCELL91:IMUX.IMUX.46.DELAY | CMAC.TX_DATAIN3_127 |
| TCELL92:OUT.1.TMIN | CMAC.RX_DATAOUT0_32 |
| TCELL92:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC65 |
| TCELL92:OUT.3.TMIN | CMAC.RX_DATAOUT0_96 |
| TCELL92:OUT.5.TMIN | CMAC.RX_DATAOUT0_33 |
| TCELL92:OUT.7.TMIN | CMAC.RX_DATAOUT0_97 |
| TCELL92:OUT.9.TMIN | CMAC.RX_DATAOUT0_34 |
| TCELL92:OUT.11.TMIN | CMAC.RX_DATAOUT0_98 |
| TCELL92:OUT.13.TMIN | CMAC.RX_DATAOUT0_35 |
| TCELL92:OUT.15.TMIN | CMAC.RX_DATAOUT0_99 |
| TCELL92:OUT.16.TMIN | CMAC.RX_MTYOUT0_0 |
| TCELL92:OUT.17.TMIN | CMAC.RX_DATAOUT0_36 |
| TCELL92:OUT.19.TMIN | CMAC.RX_DATAOUT0_100 |
| TCELL92:OUT.21.TMIN | CMAC.RX_DATAOUT0_37 |
| TCELL92:OUT.23.TMIN | CMAC.RX_DATAOUT0_101 |
| TCELL92:OUT.25.TMIN | CMAC.RX_DATAOUT0_38 |
| TCELL92:OUT.27.TMIN | CMAC.RX_DATAOUT0_102 |
| TCELL92:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC64 |
| TCELL92:OUT.29.TMIN | CMAC.RX_DATAOUT0_39 |
| TCELL92:OUT.31.TMIN | CMAC.RX_DATAOUT0_103 |
| TCELL92:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_0 |
| TCELL92:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_0 |
| TCELL92:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_1 |
| TCELL92:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_1 |
| TCELL92:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_2 |
| TCELL92:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_2 |
| TCELL92:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_3 |
| TCELL92:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_3 |
| TCELL92:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_4 |
| TCELL92:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_4 |
| TCELL92:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_5 |
| TCELL92:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_5 |
| TCELL92:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_6 |
| TCELL92:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_6 |
| TCELL92:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_7 |
| TCELL92:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_7 |
| TCELL93:OUT.1.TMIN | CMAC.RX_DATAOUT0_40 |
| TCELL93:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC67 |
| TCELL93:OUT.3.TMIN | CMAC.RX_DATAOUT0_104 |
| TCELL93:OUT.5.TMIN | CMAC.RX_DATAOUT0_41 |
| TCELL93:OUT.7.TMIN | CMAC.RX_DATAOUT0_105 |
| TCELL93:OUT.9.TMIN | CMAC.RX_DATAOUT0_42 |
| TCELL93:OUT.11.TMIN | CMAC.RX_DATAOUT0_106 |
| TCELL93:OUT.13.TMIN | CMAC.RX_DATAOUT0_43 |
| TCELL93:OUT.15.TMIN | CMAC.RX_DATAOUT0_107 |
| TCELL93:OUT.16.TMIN | CMAC.RX_MTYOUT0_1 |
| TCELL93:OUT.17.TMIN | CMAC.RX_DATAOUT0_44 |
| TCELL93:OUT.19.TMIN | CMAC.RX_DATAOUT0_108 |
| TCELL93:OUT.21.TMIN | CMAC.RX_DATAOUT0_45 |
| TCELL93:OUT.23.TMIN | CMAC.RX_DATAOUT0_109 |
| TCELL93:OUT.25.TMIN | CMAC.RX_DATAOUT0_46 |
| TCELL93:OUT.27.TMIN | CMAC.RX_DATAOUT0_110 |
| TCELL93:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC66 |
| TCELL93:OUT.29.TMIN | CMAC.RX_DATAOUT0_47 |
| TCELL93:OUT.31.TMIN | CMAC.RX_DATAOUT0_111 |
| TCELL93:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_8 |
| TCELL93:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_8 |
| TCELL93:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_9 |
| TCELL93:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_9 |
| TCELL93:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_10 |
| TCELL93:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_10 |
| TCELL93:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_11 |
| TCELL93:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_11 |
| TCELL93:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_12 |
| TCELL93:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_12 |
| TCELL93:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_13 |
| TCELL93:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_13 |
| TCELL93:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_14 |
| TCELL93:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_14 |
| TCELL93:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER0_15 |
| TCELL93:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA0_15 |
| TCELL94:OUT.1.TMIN | CMAC.RX_DATAOUT0_48 |
| TCELL94:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC69 |
| TCELL94:OUT.3.TMIN | CMAC.RX_DATAOUT0_112 |
| TCELL94:OUT.5.TMIN | CMAC.RX_DATAOUT0_49 |
| TCELL94:OUT.7.TMIN | CMAC.RX_DATAOUT0_113 |
| TCELL94:OUT.9.TMIN | CMAC.RX_DATAOUT0_50 |
| TCELL94:OUT.11.TMIN | CMAC.RX_DATAOUT0_114 |
| TCELL94:OUT.13.TMIN | CMAC.RX_DATAOUT0_51 |
| TCELL94:OUT.15.TMIN | CMAC.RX_DATAOUT0_115 |
| TCELL94:OUT.16.TMIN | CMAC.RX_MTYOUT0_2 |
| TCELL94:OUT.17.TMIN | CMAC.RX_DATAOUT0_52 |
| TCELL94:OUT.19.TMIN | CMAC.RX_DATAOUT0_116 |
| TCELL94:OUT.21.TMIN | CMAC.RX_DATAOUT0_53 |
| TCELL94:OUT.23.TMIN | CMAC.RX_DATAOUT0_117 |
| TCELL94:OUT.25.TMIN | CMAC.RX_DATAOUT0_54 |
| TCELL94:OUT.27.TMIN | CMAC.RX_DATAOUT0_118 |
| TCELL94:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC68 |
| TCELL94:OUT.29.TMIN | CMAC.RX_DATAOUT0_55 |
| TCELL94:OUT.31.TMIN | CMAC.RX_DATAOUT0_119 |
| TCELL94:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_0 |
| TCELL94:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_0 |
| TCELL94:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_1 |
| TCELL94:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_1 |
| TCELL94:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_2 |
| TCELL94:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_2 |
| TCELL94:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_3 |
| TCELL94:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_3 |
| TCELL94:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_4 |
| TCELL94:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_4 |
| TCELL94:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_5 |
| TCELL94:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_5 |
| TCELL94:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_6 |
| TCELL94:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_6 |
| TCELL94:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_7 |
| TCELL94:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_7 |
| TCELL95:OUT.1.TMIN | CMAC.RX_DATAOUT0_56 |
| TCELL95:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC71 |
| TCELL95:OUT.3.TMIN | CMAC.RX_DATAOUT0_120 |
| TCELL95:OUT.5.TMIN | CMAC.RX_DATAOUT0_57 |
| TCELL95:OUT.7.TMIN | CMAC.RX_DATAOUT0_121 |
| TCELL95:OUT.9.TMIN | CMAC.RX_DATAOUT0_58 |
| TCELL95:OUT.11.TMIN | CMAC.RX_DATAOUT0_122 |
| TCELL95:OUT.13.TMIN | CMAC.RX_DATAOUT0_59 |
| TCELL95:OUT.15.TMIN | CMAC.RX_DATAOUT0_123 |
| TCELL95:OUT.16.TMIN | CMAC.RX_MTYOUT0_3 |
| TCELL95:OUT.17.TMIN | CMAC.RX_DATAOUT0_60 |
| TCELL95:OUT.19.TMIN | CMAC.RX_DATAOUT0_124 |
| TCELL95:OUT.21.TMIN | CMAC.RX_DATAOUT0_61 |
| TCELL95:OUT.23.TMIN | CMAC.RX_DATAOUT0_125 |
| TCELL95:OUT.25.TMIN | CMAC.RX_DATAOUT0_62 |
| TCELL95:OUT.27.TMIN | CMAC.RX_DATAOUT0_126 |
| TCELL95:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC70 |
| TCELL95:OUT.29.TMIN | CMAC.RX_DATAOUT0_63 |
| TCELL95:OUT.31.TMIN | CMAC.RX_DATAOUT0_127 |
| TCELL95:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_8 |
| TCELL95:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_8 |
| TCELL95:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_9 |
| TCELL95:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_9 |
| TCELL95:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_10 |
| TCELL95:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_10 |
| TCELL95:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_11 |
| TCELL95:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_11 |
| TCELL95:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_12 |
| TCELL95:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_12 |
| TCELL95:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_13 |
| TCELL95:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_13 |
| TCELL95:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_14 |
| TCELL95:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_14 |
| TCELL95:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER1_15 |
| TCELL95:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA1_15 |
| TCELL96:OUT.1.TMIN | CMAC.RX_DATAOUT1_0 |
| TCELL96:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC73 |
| TCELL96:OUT.3.TMIN | CMAC.RX_DATAOUT1_64 |
| TCELL96:OUT.5.TMIN | CMAC.RX_DATAOUT1_1 |
| TCELL96:OUT.7.TMIN | CMAC.RX_DATAOUT1_65 |
| TCELL96:OUT.9.TMIN | CMAC.RX_DATAOUT1_2 |
| TCELL96:OUT.11.TMIN | CMAC.RX_DATAOUT1_66 |
| TCELL96:OUT.13.TMIN | CMAC.RX_DATAOUT1_3 |
| TCELL96:OUT.15.TMIN | CMAC.RX_DATAOUT1_67 |
| TCELL96:OUT.16.TMIN | CMAC.RX_ENAOUT1 |
| TCELL96:OUT.17.TMIN | CMAC.RX_DATAOUT1_4 |
| TCELL96:OUT.19.TMIN | CMAC.RX_DATAOUT1_68 |
| TCELL96:OUT.21.TMIN | CMAC.RX_DATAOUT1_5 |
| TCELL96:OUT.23.TMIN | CMAC.RX_DATAOUT1_69 |
| TCELL96:OUT.25.TMIN | CMAC.RX_DATAOUT1_6 |
| TCELL96:OUT.27.TMIN | CMAC.RX_DATAOUT1_70 |
| TCELL96:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC72 |
| TCELL96:OUT.29.TMIN | CMAC.RX_DATAOUT1_7 |
| TCELL96:OUT.31.TMIN | CMAC.RX_DATAOUT1_71 |
| TCELL96:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_0 |
| TCELL96:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_0 |
| TCELL96:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_1 |
| TCELL96:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_1 |
| TCELL96:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_2 |
| TCELL96:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_2 |
| TCELL96:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_3 |
| TCELL96:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_3 |
| TCELL96:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_4 |
| TCELL96:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_4 |
| TCELL96:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_5 |
| TCELL96:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_5 |
| TCELL96:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_6 |
| TCELL96:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_6 |
| TCELL96:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_7 |
| TCELL96:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_7 |
| TCELL97:OUT.1.TMIN | CMAC.RX_DATAOUT1_8 |
| TCELL97:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC75 |
| TCELL97:OUT.3.TMIN | CMAC.RX_DATAOUT1_72 |
| TCELL97:OUT.5.TMIN | CMAC.RX_DATAOUT1_9 |
| TCELL97:OUT.7.TMIN | CMAC.RX_DATAOUT1_73 |
| TCELL97:OUT.9.TMIN | CMAC.RX_DATAOUT1_10 |
| TCELL97:OUT.11.TMIN | CMAC.RX_DATAOUT1_74 |
| TCELL97:OUT.13.TMIN | CMAC.RX_DATAOUT1_11 |
| TCELL97:OUT.15.TMIN | CMAC.RX_DATAOUT1_75 |
| TCELL97:OUT.16.TMIN | CMAC.RX_EOPOUT1 |
| TCELL97:OUT.17.TMIN | CMAC.RX_DATAOUT1_12 |
| TCELL97:OUT.19.TMIN | CMAC.RX_DATAOUT1_76 |
| TCELL97:OUT.21.TMIN | CMAC.RX_DATAOUT1_13 |
| TCELL97:OUT.23.TMIN | CMAC.RX_DATAOUT1_77 |
| TCELL97:OUT.25.TMIN | CMAC.RX_DATAOUT1_14 |
| TCELL97:OUT.27.TMIN | CMAC.RX_DATAOUT1_78 |
| TCELL97:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC74 |
| TCELL97:OUT.29.TMIN | CMAC.RX_DATAOUT1_15 |
| TCELL97:OUT.31.TMIN | CMAC.RX_DATAOUT1_79 |
| TCELL97:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_8 |
| TCELL97:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_8 |
| TCELL97:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_9 |
| TCELL97:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_9 |
| TCELL97:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_10 |
| TCELL97:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_10 |
| TCELL97:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_11 |
| TCELL97:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_11 |
| TCELL97:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_12 |
| TCELL97:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_12 |
| TCELL97:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_13 |
| TCELL97:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_13 |
| TCELL97:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_14 |
| TCELL97:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_14 |
| TCELL97:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER2_15 |
| TCELL97:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA2_15 |
| TCELL98:OUT.1.TMIN | CMAC.RX_DATAOUT1_16 |
| TCELL98:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC77 |
| TCELL98:OUT.3.TMIN | CMAC.RX_DATAOUT1_80 |
| TCELL98:OUT.5.TMIN | CMAC.RX_DATAOUT1_17 |
| TCELL98:OUT.7.TMIN | CMAC.RX_DATAOUT1_81 |
| TCELL98:OUT.9.TMIN | CMAC.RX_DATAOUT1_18 |
| TCELL98:OUT.11.TMIN | CMAC.RX_DATAOUT1_82 |
| TCELL98:OUT.13.TMIN | CMAC.RX_DATAOUT1_19 |
| TCELL98:OUT.15.TMIN | CMAC.RX_DATAOUT1_83 |
| TCELL98:OUT.16.TMIN | CMAC.RX_SOPOUT1 |
| TCELL98:OUT.17.TMIN | CMAC.RX_DATAOUT1_20 |
| TCELL98:OUT.19.TMIN | CMAC.RX_DATAOUT1_84 |
| TCELL98:OUT.21.TMIN | CMAC.RX_DATAOUT1_21 |
| TCELL98:OUT.23.TMIN | CMAC.RX_DATAOUT1_85 |
| TCELL98:OUT.25.TMIN | CMAC.RX_DATAOUT1_22 |
| TCELL98:OUT.27.TMIN | CMAC.RX_DATAOUT1_86 |
| TCELL98:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC76 |
| TCELL98:OUT.29.TMIN | CMAC.RX_DATAOUT1_23 |
| TCELL98:OUT.31.TMIN | CMAC.RX_DATAOUT1_87 |
| TCELL98:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_0 |
| TCELL98:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_0 |
| TCELL98:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_1 |
| TCELL98:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_1 |
| TCELL98:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_2 |
| TCELL98:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_2 |
| TCELL98:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_3 |
| TCELL98:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_3 |
| TCELL98:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_4 |
| TCELL98:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_4 |
| TCELL98:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_5 |
| TCELL98:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_5 |
| TCELL98:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_6 |
| TCELL98:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_6 |
| TCELL98:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_7 |
| TCELL98:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_7 |
| TCELL99:OUT.1.TMIN | CMAC.RX_DATAOUT1_24 |
| TCELL99:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC79 |
| TCELL99:OUT.3.TMIN | CMAC.RX_DATAOUT1_88 |
| TCELL99:OUT.5.TMIN | CMAC.RX_DATAOUT1_25 |
| TCELL99:OUT.7.TMIN | CMAC.RX_DATAOUT1_89 |
| TCELL99:OUT.9.TMIN | CMAC.RX_DATAOUT1_26 |
| TCELL99:OUT.11.TMIN | CMAC.RX_DATAOUT1_90 |
| TCELL99:OUT.13.TMIN | CMAC.RX_DATAOUT1_27 |
| TCELL99:OUT.15.TMIN | CMAC.RX_DATAOUT1_91 |
| TCELL99:OUT.16.TMIN | CMAC.RX_ERROUT1 |
| TCELL99:OUT.17.TMIN | CMAC.RX_DATAOUT1_28 |
| TCELL99:OUT.19.TMIN | CMAC.RX_DATAOUT1_92 |
| TCELL99:OUT.21.TMIN | CMAC.RX_DATAOUT1_29 |
| TCELL99:OUT.23.TMIN | CMAC.RX_DATAOUT1_93 |
| TCELL99:OUT.25.TMIN | CMAC.RX_DATAOUT1_30 |
| TCELL99:OUT.27.TMIN | CMAC.RX_DATAOUT1_94 |
| TCELL99:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC78 |
| TCELL99:OUT.29.TMIN | CMAC.RX_DATAOUT1_31 |
| TCELL99:OUT.31.TMIN | CMAC.RX_DATAOUT1_95 |
| TCELL99:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_8 |
| TCELL99:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_8 |
| TCELL99:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_9 |
| TCELL99:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_9 |
| TCELL99:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_10 |
| TCELL99:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_10 |
| TCELL99:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_11 |
| TCELL99:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_11 |
| TCELL99:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_12 |
| TCELL99:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_12 |
| TCELL99:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_13 |
| TCELL99:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_13 |
| TCELL99:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_14 |
| TCELL99:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_14 |
| TCELL99:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER3_15 |
| TCELL99:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA3_15 |
| TCELL100:OUT.1.TMIN | CMAC.RX_DATAOUT1_32 |
| TCELL100:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC81 |
| TCELL100:OUT.3.TMIN | CMAC.RX_DATAOUT1_96 |
| TCELL100:OUT.5.TMIN | CMAC.RX_DATAOUT1_33 |
| TCELL100:OUT.7.TMIN | CMAC.RX_DATAOUT1_97 |
| TCELL100:OUT.9.TMIN | CMAC.RX_DATAOUT1_34 |
| TCELL100:OUT.11.TMIN | CMAC.RX_DATAOUT1_98 |
| TCELL100:OUT.13.TMIN | CMAC.RX_DATAOUT1_35 |
| TCELL100:OUT.15.TMIN | CMAC.RX_DATAOUT1_99 |
| TCELL100:OUT.16.TMIN | CMAC.RX_MTYOUT1_0 |
| TCELL100:OUT.17.TMIN | CMAC.RX_DATAOUT1_36 |
| TCELL100:OUT.19.TMIN | CMAC.RX_DATAOUT1_100 |
| TCELL100:OUT.21.TMIN | CMAC.RX_DATAOUT1_37 |
| TCELL100:OUT.23.TMIN | CMAC.RX_DATAOUT1_101 |
| TCELL100:OUT.25.TMIN | CMAC.RX_DATAOUT1_38 |
| TCELL100:OUT.27.TMIN | CMAC.RX_DATAOUT1_102 |
| TCELL100:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC80 |
| TCELL100:OUT.29.TMIN | CMAC.RX_DATAOUT1_39 |
| TCELL100:OUT.31.TMIN | CMAC.RX_DATAOUT1_103 |
| TCELL100:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_0 |
| TCELL100:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_0 |
| TCELL100:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_1 |
| TCELL100:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_1 |
| TCELL100:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_2 |
| TCELL100:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_2 |
| TCELL100:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_3 |
| TCELL100:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_3 |
| TCELL100:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_4 |
| TCELL100:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_4 |
| TCELL100:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_5 |
| TCELL100:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_5 |
| TCELL100:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_6 |
| TCELL100:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_6 |
| TCELL100:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_7 |
| TCELL100:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_7 |
| TCELL101:OUT.1.TMIN | CMAC.RX_DATAOUT1_40 |
| TCELL101:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC83 |
| TCELL101:OUT.3.TMIN | CMAC.RX_DATAOUT1_104 |
| TCELL101:OUT.5.TMIN | CMAC.RX_DATAOUT1_41 |
| TCELL101:OUT.7.TMIN | CMAC.RX_DATAOUT1_105 |
| TCELL101:OUT.9.TMIN | CMAC.RX_DATAOUT1_42 |
| TCELL101:OUT.11.TMIN | CMAC.RX_DATAOUT1_106 |
| TCELL101:OUT.13.TMIN | CMAC.RX_DATAOUT1_43 |
| TCELL101:OUT.15.TMIN | CMAC.RX_DATAOUT1_107 |
| TCELL101:OUT.16.TMIN | CMAC.RX_MTYOUT1_1 |
| TCELL101:OUT.17.TMIN | CMAC.RX_DATAOUT1_44 |
| TCELL101:OUT.19.TMIN | CMAC.RX_DATAOUT1_108 |
| TCELL101:OUT.21.TMIN | CMAC.RX_DATAOUT1_45 |
| TCELL101:OUT.23.TMIN | CMAC.RX_DATAOUT1_109 |
| TCELL101:OUT.25.TMIN | CMAC.RX_DATAOUT1_46 |
| TCELL101:OUT.27.TMIN | CMAC.RX_DATAOUT1_110 |
| TCELL101:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC82 |
| TCELL101:OUT.29.TMIN | CMAC.RX_DATAOUT1_47 |
| TCELL101:OUT.31.TMIN | CMAC.RX_DATAOUT1_111 |
| TCELL101:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_8 |
| TCELL101:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_8 |
| TCELL101:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_9 |
| TCELL101:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_9 |
| TCELL101:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_10 |
| TCELL101:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_10 |
| TCELL101:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_11 |
| TCELL101:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_11 |
| TCELL101:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_12 |
| TCELL101:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_12 |
| TCELL101:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_13 |
| TCELL101:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_13 |
| TCELL101:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_14 |
| TCELL101:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_14 |
| TCELL101:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER4_15 |
| TCELL101:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA4_15 |
| TCELL102:OUT.1.TMIN | CMAC.RX_DATAOUT1_48 |
| TCELL102:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC85 |
| TCELL102:OUT.3.TMIN | CMAC.RX_DATAOUT1_112 |
| TCELL102:OUT.5.TMIN | CMAC.RX_DATAOUT1_49 |
| TCELL102:OUT.7.TMIN | CMAC.RX_DATAOUT1_113 |
| TCELL102:OUT.9.TMIN | CMAC.RX_DATAOUT1_50 |
| TCELL102:OUT.11.TMIN | CMAC.RX_DATAOUT1_114 |
| TCELL102:OUT.13.TMIN | CMAC.RX_DATAOUT1_51 |
| TCELL102:OUT.15.TMIN | CMAC.RX_DATAOUT1_115 |
| TCELL102:OUT.16.TMIN | CMAC.RX_MTYOUT1_2 |
| TCELL102:OUT.17.TMIN | CMAC.RX_DATAOUT1_52 |
| TCELL102:OUT.19.TMIN | CMAC.RX_DATAOUT1_116 |
| TCELL102:OUT.21.TMIN | CMAC.RX_DATAOUT1_53 |
| TCELL102:OUT.23.TMIN | CMAC.RX_DATAOUT1_117 |
| TCELL102:OUT.25.TMIN | CMAC.RX_DATAOUT1_54 |
| TCELL102:OUT.27.TMIN | CMAC.RX_DATAOUT1_118 |
| TCELL102:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC84 |
| TCELL102:OUT.29.TMIN | CMAC.RX_DATAOUT1_55 |
| TCELL102:OUT.31.TMIN | CMAC.RX_DATAOUT1_119 |
| TCELL102:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_0 |
| TCELL102:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_0 |
| TCELL102:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_1 |
| TCELL102:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_1 |
| TCELL102:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_2 |
| TCELL102:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_2 |
| TCELL102:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_3 |
| TCELL102:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_3 |
| TCELL102:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_4 |
| TCELL102:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_4 |
| TCELL102:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_5 |
| TCELL102:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_5 |
| TCELL102:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_6 |
| TCELL102:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_6 |
| TCELL102:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_7 |
| TCELL102:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_7 |
| TCELL103:OUT.1.TMIN | CMAC.RX_DATAOUT1_56 |
| TCELL103:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC87 |
| TCELL103:OUT.3.TMIN | CMAC.RX_DATAOUT1_120 |
| TCELL103:OUT.5.TMIN | CMAC.RX_DATAOUT1_57 |
| TCELL103:OUT.7.TMIN | CMAC.RX_DATAOUT1_121 |
| TCELL103:OUT.9.TMIN | CMAC.RX_DATAOUT1_58 |
| TCELL103:OUT.11.TMIN | CMAC.RX_DATAOUT1_122 |
| TCELL103:OUT.13.TMIN | CMAC.RX_DATAOUT1_59 |
| TCELL103:OUT.15.TMIN | CMAC.RX_DATAOUT1_123 |
| TCELL103:OUT.16.TMIN | CMAC.RX_MTYOUT1_3 |
| TCELL103:OUT.17.TMIN | CMAC.RX_DATAOUT1_60 |
| TCELL103:OUT.19.TMIN | CMAC.RX_DATAOUT1_124 |
| TCELL103:OUT.21.TMIN | CMAC.RX_DATAOUT1_61 |
| TCELL103:OUT.23.TMIN | CMAC.RX_DATAOUT1_125 |
| TCELL103:OUT.25.TMIN | CMAC.RX_DATAOUT1_62 |
| TCELL103:OUT.27.TMIN | CMAC.RX_DATAOUT1_126 |
| TCELL103:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC86 |
| TCELL103:OUT.29.TMIN | CMAC.RX_DATAOUT1_63 |
| TCELL103:OUT.31.TMIN | CMAC.RX_DATAOUT1_127 |
| TCELL103:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_8 |
| TCELL103:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_8 |
| TCELL103:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_9 |
| TCELL103:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_9 |
| TCELL103:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_10 |
| TCELL103:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_10 |
| TCELL103:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_11 |
| TCELL103:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_11 |
| TCELL103:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_12 |
| TCELL103:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_12 |
| TCELL103:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_13 |
| TCELL103:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_13 |
| TCELL103:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_14 |
| TCELL103:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_14 |
| TCELL103:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER5_15 |
| TCELL103:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA5_15 |
| TCELL104:OUT.1.TMIN | CMAC.RX_DATAOUT2_0 |
| TCELL104:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC89 |
| TCELL104:OUT.3.TMIN | CMAC.RX_DATAOUT2_64 |
| TCELL104:OUT.5.TMIN | CMAC.RX_DATAOUT2_1 |
| TCELL104:OUT.7.TMIN | CMAC.RX_DATAOUT2_65 |
| TCELL104:OUT.9.TMIN | CMAC.RX_DATAOUT2_2 |
| TCELL104:OUT.11.TMIN | CMAC.RX_DATAOUT2_66 |
| TCELL104:OUT.13.TMIN | CMAC.RX_DATAOUT2_3 |
| TCELL104:OUT.15.TMIN | CMAC.RX_DATAOUT2_67 |
| TCELL104:OUT.16.TMIN | CMAC.RX_ENAOUT2 |
| TCELL104:OUT.17.TMIN | CMAC.RX_DATAOUT2_4 |
| TCELL104:OUT.19.TMIN | CMAC.RX_DATAOUT2_68 |
| TCELL104:OUT.21.TMIN | CMAC.RX_DATAOUT2_5 |
| TCELL104:OUT.23.TMIN | CMAC.RX_DATAOUT2_69 |
| TCELL104:OUT.25.TMIN | CMAC.RX_DATAOUT2_6 |
| TCELL104:OUT.27.TMIN | CMAC.RX_DATAOUT2_70 |
| TCELL104:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC88 |
| TCELL104:OUT.29.TMIN | CMAC.RX_DATAOUT2_7 |
| TCELL104:OUT.31.TMIN | CMAC.RX_DATAOUT2_71 |
| TCELL104:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_0 |
| TCELL104:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_0 |
| TCELL104:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_1 |
| TCELL104:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_1 |
| TCELL104:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_2 |
| TCELL104:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_2 |
| TCELL104:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_3 |
| TCELL104:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_3 |
| TCELL104:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_4 |
| TCELL104:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_4 |
| TCELL104:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_5 |
| TCELL104:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_5 |
| TCELL104:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_6 |
| TCELL104:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_6 |
| TCELL104:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_7 |
| TCELL104:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_7 |
| TCELL105:OUT.1.TMIN | CMAC.RX_DATAOUT2_8 |
| TCELL105:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC91 |
| TCELL105:OUT.3.TMIN | CMAC.RX_DATAOUT2_72 |
| TCELL105:OUT.5.TMIN | CMAC.RX_DATAOUT2_9 |
| TCELL105:OUT.7.TMIN | CMAC.RX_DATAOUT2_73 |
| TCELL105:OUT.9.TMIN | CMAC.RX_DATAOUT2_10 |
| TCELL105:OUT.11.TMIN | CMAC.RX_DATAOUT2_74 |
| TCELL105:OUT.13.TMIN | CMAC.RX_DATAOUT2_11 |
| TCELL105:OUT.15.TMIN | CMAC.RX_DATAOUT2_75 |
| TCELL105:OUT.16.TMIN | CMAC.RX_EOPOUT2 |
| TCELL105:OUT.17.TMIN | CMAC.RX_DATAOUT2_12 |
| TCELL105:OUT.19.TMIN | CMAC.RX_DATAOUT2_76 |
| TCELL105:OUT.21.TMIN | CMAC.RX_DATAOUT2_13 |
| TCELL105:OUT.23.TMIN | CMAC.RX_DATAOUT2_77 |
| TCELL105:OUT.25.TMIN | CMAC.RX_DATAOUT2_14 |
| TCELL105:OUT.27.TMIN | CMAC.RX_DATAOUT2_78 |
| TCELL105:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC90 |
| TCELL105:OUT.29.TMIN | CMAC.RX_DATAOUT2_15 |
| TCELL105:OUT.31.TMIN | CMAC.RX_DATAOUT2_79 |
| TCELL105:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_8 |
| TCELL105:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_8 |
| TCELL105:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_9 |
| TCELL105:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_9 |
| TCELL105:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_10 |
| TCELL105:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_10 |
| TCELL105:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_11 |
| TCELL105:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_11 |
| TCELL105:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_12 |
| TCELL105:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_12 |
| TCELL105:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_13 |
| TCELL105:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_13 |
| TCELL105:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_14 |
| TCELL105:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_14 |
| TCELL105:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER6_15 |
| TCELL105:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA6_15 |
| TCELL106:OUT.1.TMIN | CMAC.RX_DATAOUT2_16 |
| TCELL106:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC93 |
| TCELL106:OUT.3.TMIN | CMAC.RX_DATAOUT2_80 |
| TCELL106:OUT.5.TMIN | CMAC.RX_DATAOUT2_17 |
| TCELL106:OUT.7.TMIN | CMAC.RX_DATAOUT2_81 |
| TCELL106:OUT.9.TMIN | CMAC.RX_DATAOUT2_18 |
| TCELL106:OUT.11.TMIN | CMAC.RX_DATAOUT2_82 |
| TCELL106:OUT.13.TMIN | CMAC.RX_DATAOUT2_19 |
| TCELL106:OUT.15.TMIN | CMAC.RX_DATAOUT2_83 |
| TCELL106:OUT.16.TMIN | CMAC.RX_SOPOUT2 |
| TCELL106:OUT.17.TMIN | CMAC.RX_DATAOUT2_20 |
| TCELL106:OUT.19.TMIN | CMAC.RX_DATAOUT2_84 |
| TCELL106:OUT.21.TMIN | CMAC.RX_DATAOUT2_21 |
| TCELL106:OUT.23.TMIN | CMAC.RX_DATAOUT2_85 |
| TCELL106:OUT.25.TMIN | CMAC.RX_DATAOUT2_22 |
| TCELL106:OUT.27.TMIN | CMAC.RX_DATAOUT2_86 |
| TCELL106:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC92 |
| TCELL106:OUT.29.TMIN | CMAC.RX_DATAOUT2_23 |
| TCELL106:OUT.31.TMIN | CMAC.RX_DATAOUT2_87 |
| TCELL106:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_0 |
| TCELL106:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_0 |
| TCELL106:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_1 |
| TCELL106:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_1 |
| TCELL106:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_2 |
| TCELL106:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_2 |
| TCELL106:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_3 |
| TCELL106:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_3 |
| TCELL106:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_4 |
| TCELL106:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_4 |
| TCELL106:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_5 |
| TCELL106:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_5 |
| TCELL106:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_6 |
| TCELL106:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_6 |
| TCELL106:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_7 |
| TCELL106:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_7 |
| TCELL107:OUT.1.TMIN | CMAC.RX_DATAOUT2_24 |
| TCELL107:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC95 |
| TCELL107:OUT.3.TMIN | CMAC.RX_DATAOUT2_88 |
| TCELL107:OUT.5.TMIN | CMAC.RX_DATAOUT2_25 |
| TCELL107:OUT.7.TMIN | CMAC.RX_DATAOUT2_89 |
| TCELL107:OUT.9.TMIN | CMAC.RX_DATAOUT2_26 |
| TCELL107:OUT.11.TMIN | CMAC.RX_DATAOUT2_90 |
| TCELL107:OUT.13.TMIN | CMAC.RX_DATAOUT2_27 |
| TCELL107:OUT.15.TMIN | CMAC.RX_DATAOUT2_91 |
| TCELL107:OUT.16.TMIN | CMAC.RX_ERROUT2 |
| TCELL107:OUT.17.TMIN | CMAC.RX_DATAOUT2_28 |
| TCELL107:OUT.19.TMIN | CMAC.RX_DATAOUT2_92 |
| TCELL107:OUT.21.TMIN | CMAC.RX_DATAOUT2_29 |
| TCELL107:OUT.23.TMIN | CMAC.RX_DATAOUT2_93 |
| TCELL107:OUT.25.TMIN | CMAC.RX_DATAOUT2_30 |
| TCELL107:OUT.27.TMIN | CMAC.RX_DATAOUT2_94 |
| TCELL107:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC94 |
| TCELL107:OUT.29.TMIN | CMAC.RX_DATAOUT2_31 |
| TCELL107:OUT.31.TMIN | CMAC.RX_DATAOUT2_95 |
| TCELL107:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_8 |
| TCELL107:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_8 |
| TCELL107:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_9 |
| TCELL107:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_9 |
| TCELL107:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_10 |
| TCELL107:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_10 |
| TCELL107:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_11 |
| TCELL107:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_11 |
| TCELL107:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_12 |
| TCELL107:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_12 |
| TCELL107:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_13 |
| TCELL107:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_13 |
| TCELL107:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_14 |
| TCELL107:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_14 |
| TCELL107:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER7_15 |
| TCELL107:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA7_15 |
| TCELL108:OUT.1.TMIN | CMAC.RX_DATAOUT2_32 |
| TCELL108:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC97 |
| TCELL108:OUT.3.TMIN | CMAC.RX_DATAOUT2_96 |
| TCELL108:OUT.5.TMIN | CMAC.RX_DATAOUT2_33 |
| TCELL108:OUT.7.TMIN | CMAC.RX_DATAOUT2_97 |
| TCELL108:OUT.9.TMIN | CMAC.RX_DATAOUT2_34 |
| TCELL108:OUT.11.TMIN | CMAC.RX_DATAOUT2_98 |
| TCELL108:OUT.13.TMIN | CMAC.RX_DATAOUT2_35 |
| TCELL108:OUT.15.TMIN | CMAC.RX_DATAOUT2_99 |
| TCELL108:OUT.16.TMIN | CMAC.RX_MTYOUT2_0 |
| TCELL108:OUT.17.TMIN | CMAC.RX_DATAOUT2_36 |
| TCELL108:OUT.19.TMIN | CMAC.RX_DATAOUT2_100 |
| TCELL108:OUT.21.TMIN | CMAC.RX_DATAOUT2_37 |
| TCELL108:OUT.23.TMIN | CMAC.RX_DATAOUT2_101 |
| TCELL108:OUT.25.TMIN | CMAC.RX_DATAOUT2_38 |
| TCELL108:OUT.27.TMIN | CMAC.RX_DATAOUT2_102 |
| TCELL108:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC96 |
| TCELL108:OUT.29.TMIN | CMAC.RX_DATAOUT2_39 |
| TCELL108:OUT.31.TMIN | CMAC.RX_DATAOUT2_103 |
| TCELL108:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_0 |
| TCELL108:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_0 |
| TCELL108:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_1 |
| TCELL108:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_1 |
| TCELL108:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_2 |
| TCELL108:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_2 |
| TCELL108:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_3 |
| TCELL108:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_3 |
| TCELL108:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_4 |
| TCELL108:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_4 |
| TCELL108:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_5 |
| TCELL108:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_5 |
| TCELL108:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_6 |
| TCELL108:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_6 |
| TCELL108:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_7 |
| TCELL108:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_7 |
| TCELL109:OUT.1.TMIN | CMAC.RX_DATAOUT2_40 |
| TCELL109:OUT.2.TMIN | CMAC.SCAN_OUT_CMAC99 |
| TCELL109:OUT.3.TMIN | CMAC.RX_DATAOUT2_104 |
| TCELL109:OUT.5.TMIN | CMAC.RX_DATAOUT2_41 |
| TCELL109:OUT.7.TMIN | CMAC.RX_DATAOUT2_105 |
| TCELL109:OUT.9.TMIN | CMAC.RX_DATAOUT2_42 |
| TCELL109:OUT.11.TMIN | CMAC.RX_DATAOUT2_106 |
| TCELL109:OUT.13.TMIN | CMAC.RX_DATAOUT2_43 |
| TCELL109:OUT.15.TMIN | CMAC.RX_DATAOUT2_107 |
| TCELL109:OUT.16.TMIN | CMAC.RX_MTYOUT2_1 |
| TCELL109:OUT.17.TMIN | CMAC.RX_DATAOUT2_44 |
| TCELL109:OUT.19.TMIN | CMAC.RX_DATAOUT2_108 |
| TCELL109:OUT.21.TMIN | CMAC.RX_DATAOUT2_45 |
| TCELL109:OUT.23.TMIN | CMAC.RX_DATAOUT2_109 |
| TCELL109:OUT.25.TMIN | CMAC.RX_DATAOUT2_46 |
| TCELL109:OUT.27.TMIN | CMAC.RX_DATAOUT2_110 |
| TCELL109:OUT.28.TMIN | CMAC.SCAN_OUT_CMAC98 |
| TCELL109:OUT.29.TMIN | CMAC.RX_DATAOUT2_47 |
| TCELL109:OUT.31.TMIN | CMAC.RX_DATAOUT2_111 |
| TCELL109:IMUX.IMUX.1.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_8 |
| TCELL109:IMUX.IMUX.4.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_8 |
| TCELL109:IMUX.IMUX.7.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_9 |
| TCELL109:IMUX.IMUX.10.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_9 |
| TCELL109:IMUX.IMUX.13.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_10 |
| TCELL109:IMUX.IMUX.16.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_10 |
| TCELL109:IMUX.IMUX.19.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_11 |
| TCELL109:IMUX.IMUX.22.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_11 |
| TCELL109:IMUX.IMUX.25.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_12 |
| TCELL109:IMUX.IMUX.28.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_12 |
| TCELL109:IMUX.IMUX.31.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_13 |
| TCELL109:IMUX.IMUX.34.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_13 |
| TCELL109:IMUX.IMUX.37.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_14 |
| TCELL109:IMUX.IMUX.40.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_14 |
| TCELL109:IMUX.IMUX.43.DELAY | CMAC.CTL_TX_PAUSE_REFRESH_TIMER8_15 |
| TCELL109:IMUX.IMUX.46.DELAY | CMAC.CTL_TX_PAUSE_QUANTA8_15 |
| TCELL110:OUT.1.TMIN | CMAC.RX_DATAOUT2_48 |
| TCELL110:OUT.3.TMIN | CMAC.RX_DATAOUT2_112 |
| TCELL110:OUT.5.TMIN | CMAC.RX_DATAOUT2_49 |
| TCELL110:OUT.7.TMIN | CMAC.RX_DATAOUT2_113 |
| TCELL110:OUT.9.TMIN | CMAC.RX_DATAOUT2_50 |
| TCELL110:OUT.11.TMIN | CMAC.RX_DATAOUT2_114 |
| TCELL110:OUT.13.TMIN | CMAC.RX_DATAOUT2_51 |
| TCELL110:OUT.15.TMIN | CMAC.RX_DATAOUT2_115 |
| TCELL110:OUT.16.TMIN | CMAC.RX_MTYOUT2_2 |
| TCELL110:OUT.17.TMIN | CMAC.RX_DATAOUT2_52 |
| TCELL110:OUT.19.TMIN | CMAC.RX_DATAOUT2_116 |
| TCELL110:OUT.21.TMIN | CMAC.RX_DATAOUT2_53 |
| TCELL110:OUT.23.TMIN | CMAC.RX_DATAOUT2_117 |
| TCELL110:OUT.25.TMIN | CMAC.RX_DATAOUT2_54 |
| TCELL110:OUT.27.TMIN | CMAC.RX_DATAOUT2_118 |
| TCELL110:OUT.29.TMIN | CMAC.RX_DATAOUT2_55 |
| TCELL110:OUT.31.TMIN | CMAC.RX_DATAOUT2_119 |
| TCELL110:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN72 |
| TCELL110:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_PAUSE_ACK8 |
| TCELL110:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN73 |
| TCELL110:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_CHECK_OPCODE_PPP |
| TCELL110:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN74 |
| TCELL110:IMUX.IMUX.16.DELAY | CMAC.CTL_RX_CHECK_OPCODE_PCP |
| TCELL110:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN75 |
| TCELL110:IMUX.IMUX.22.DELAY | CMAC.CTL_RX_CHECK_OPCODE_GPP |
| TCELL110:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN76 |
| TCELL110:IMUX.IMUX.28.DELAY | CMAC.CTL_RX_CHECK_OPCODE_GCP |
| TCELL110:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN77 |
| TCELL110:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_CHECK_MCAST_PPP |
| TCELL110:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN78 |
| TCELL110:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_CHECK_MCAST_PCP |
| TCELL110:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN79 |
| TCELL110:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_CHECK_MCAST_GPP |
| TCELL111:OUT.1.TMIN | CMAC.RX_DATAOUT2_56 |
| TCELL111:OUT.3.TMIN | CMAC.RX_DATAOUT2_120 |
| TCELL111:OUT.5.TMIN | CMAC.RX_DATAOUT2_57 |
| TCELL111:OUT.7.TMIN | CMAC.RX_DATAOUT2_121 |
| TCELL111:OUT.9.TMIN | CMAC.RX_DATAOUT2_58 |
| TCELL111:OUT.11.TMIN | CMAC.RX_DATAOUT2_122 |
| TCELL111:OUT.13.TMIN | CMAC.RX_DATAOUT2_59 |
| TCELL111:OUT.15.TMIN | CMAC.RX_DATAOUT2_123 |
| TCELL111:OUT.16.TMIN | CMAC.RX_MTYOUT2_3 |
| TCELL111:OUT.17.TMIN | CMAC.RX_DATAOUT2_60 |
| TCELL111:OUT.19.TMIN | CMAC.RX_DATAOUT2_124 |
| TCELL111:OUT.21.TMIN | CMAC.RX_DATAOUT2_61 |
| TCELL111:OUT.23.TMIN | CMAC.RX_DATAOUT2_125 |
| TCELL111:OUT.25.TMIN | CMAC.RX_DATAOUT2_62 |
| TCELL111:OUT.27.TMIN | CMAC.RX_DATAOUT2_126 |
| TCELL111:OUT.29.TMIN | CMAC.RX_DATAOUT2_63 |
| TCELL111:OUT.31.TMIN | CMAC.RX_DATAOUT2_127 |
| TCELL111:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN64 |
| TCELL111:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_PAUSE_ACK0 |
| TCELL111:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN65 |
| TCELL111:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_PAUSE_ACK1 |
| TCELL111:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN66 |
| TCELL111:IMUX.IMUX.16.DELAY | CMAC.CTL_RX_PAUSE_ACK2 |
| TCELL111:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN67 |
| TCELL111:IMUX.IMUX.22.DELAY | CMAC.CTL_RX_PAUSE_ACK3 |
| TCELL111:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN68 |
| TCELL111:IMUX.IMUX.28.DELAY | CMAC.CTL_RX_PAUSE_ACK4 |
| TCELL111:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN69 |
| TCELL111:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_PAUSE_ACK5 |
| TCELL111:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN70 |
| TCELL111:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_PAUSE_ACK6 |
| TCELL111:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN71 |
| TCELL111:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_PAUSE_ACK7 |
| TCELL112:OUT.1.TMIN | CMAC.RX_DATAOUT3_0 |
| TCELL112:OUT.3.TMIN | CMAC.RX_DATAOUT3_64 |
| TCELL112:OUT.5.TMIN | CMAC.RX_DATAOUT3_1 |
| TCELL112:OUT.7.TMIN | CMAC.RX_DATAOUT3_65 |
| TCELL112:OUT.9.TMIN | CMAC.RX_DATAOUT3_2 |
| TCELL112:OUT.11.TMIN | CMAC.RX_DATAOUT3_66 |
| TCELL112:OUT.13.TMIN | CMAC.RX_DATAOUT3_3 |
| TCELL112:OUT.15.TMIN | CMAC.RX_DATAOUT3_67 |
| TCELL112:OUT.16.TMIN | CMAC.RX_ENAOUT3 |
| TCELL112:OUT.17.TMIN | CMAC.RX_DATAOUT3_4 |
| TCELL112:OUT.19.TMIN | CMAC.RX_DATAOUT3_68 |
| TCELL112:OUT.21.TMIN | CMAC.RX_DATAOUT3_5 |
| TCELL112:OUT.23.TMIN | CMAC.RX_DATAOUT3_69 |
| TCELL112:OUT.25.TMIN | CMAC.RX_DATAOUT3_6 |
| TCELL112:OUT.27.TMIN | CMAC.RX_DATAOUT3_70 |
| TCELL112:OUT.29.TMIN | CMAC.RX_DATAOUT3_7 |
| TCELL112:OUT.31.TMIN | CMAC.RX_DATAOUT3_71 |
| TCELL112:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN56 |
| TCELL112:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_ENABLE_PPP |
| TCELL112:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN57 |
| TCELL112:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_ENABLE_GPP |
| TCELL112:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN58 |
| TCELL112:IMUX.IMUX.16.DELAY | CMAC.CTL_RX_CHECK_UCAST_PPP |
| TCELL112:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN59 |
| TCELL112:IMUX.IMUX.22.DELAY | CMAC.CTL_RX_CHECK_UCAST_PCP |
| TCELL112:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN60 |
| TCELL112:IMUX.IMUX.28.DELAY | CMAC.CTL_RX_CHECK_UCAST_GPP |
| TCELL112:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN61 |
| TCELL112:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_CHECK_UCAST_GCP |
| TCELL112:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN62 |
| TCELL112:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_CHECK_SA_PPP |
| TCELL112:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN63 |
| TCELL112:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_CHECK_MCAST_GCP |
| TCELL113:OUT.1.TMIN | CMAC.RX_DATAOUT3_8 |
| TCELL113:OUT.3.TMIN | CMAC.RX_DATAOUT3_72 |
| TCELL113:OUT.5.TMIN | CMAC.RX_DATAOUT3_9 |
| TCELL113:OUT.7.TMIN | CMAC.RX_DATAOUT3_73 |
| TCELL113:OUT.9.TMIN | CMAC.RX_DATAOUT3_10 |
| TCELL113:OUT.11.TMIN | CMAC.RX_DATAOUT3_74 |
| TCELL113:OUT.13.TMIN | CMAC.RX_DATAOUT3_11 |
| TCELL113:OUT.15.TMIN | CMAC.RX_DATAOUT3_75 |
| TCELL113:OUT.16.TMIN | CMAC.RX_EOPOUT3 |
| TCELL113:OUT.17.TMIN | CMAC.RX_DATAOUT3_12 |
| TCELL113:OUT.19.TMIN | CMAC.RX_DATAOUT3_76 |
| TCELL113:OUT.21.TMIN | CMAC.RX_DATAOUT3_13 |
| TCELL113:OUT.23.TMIN | CMAC.RX_DATAOUT3_77 |
| TCELL113:OUT.25.TMIN | CMAC.RX_DATAOUT3_14 |
| TCELL113:OUT.27.TMIN | CMAC.RX_DATAOUT3_78 |
| TCELL113:OUT.29.TMIN | CMAC.RX_DATAOUT3_15 |
| TCELL113:OUT.31.TMIN | CMAC.RX_DATAOUT3_79 |
| TCELL113:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN48 |
| TCELL113:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_ENABLE_PCP |
| TCELL113:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN49 |
| TCELL113:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_ENABLE_GCP |
| TCELL113:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN50 |
| TCELL113:IMUX.IMUX.16.DELAY | CMAC.CTL_RX_TEST_PATTERN |
| TCELL113:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN51 |
| TCELL113:IMUX.IMUX.22.DELAY | CMAC.CTL_RX_FORCE_RESYNC |
| TCELL113:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN52 |
| TCELL113:IMUX.IMUX.28.DELAY | CMAC.CTL_RX_CHECK_SA_GCP |
| TCELL113:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN53 |
| TCELL113:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_CHECK_SA_GPP |
| TCELL113:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN54 |
| TCELL113:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_CHECK_SA_PCP |
| TCELL113:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN55 |
| TCELL113:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_CHECK_ETYPE_GCP |
| TCELL114:OUT.1.TMIN | CMAC.RX_DATAOUT3_16 |
| TCELL114:OUT.3.TMIN | CMAC.RX_DATAOUT3_80 |
| TCELL114:OUT.5.TMIN | CMAC.RX_DATAOUT3_17 |
| TCELL114:OUT.7.TMIN | CMAC.RX_DATAOUT3_81 |
| TCELL114:OUT.9.TMIN | CMAC.RX_DATAOUT3_18 |
| TCELL114:OUT.11.TMIN | CMAC.RX_DATAOUT3_82 |
| TCELL114:OUT.13.TMIN | CMAC.RX_DATAOUT3_19 |
| TCELL114:OUT.15.TMIN | CMAC.RX_DATAOUT3_83 |
| TCELL114:OUT.16.TMIN | CMAC.RX_SOPOUT3 |
| TCELL114:OUT.17.TMIN | CMAC.RX_DATAOUT3_20 |
| TCELL114:OUT.19.TMIN | CMAC.RX_DATAOUT3_84 |
| TCELL114:OUT.21.TMIN | CMAC.RX_DATAOUT3_21 |
| TCELL114:OUT.23.TMIN | CMAC.RX_DATAOUT3_85 |
| TCELL114:OUT.25.TMIN | CMAC.RX_DATAOUT3_22 |
| TCELL114:OUT.27.TMIN | CMAC.RX_DATAOUT3_86 |
| TCELL114:OUT.29.TMIN | CMAC.RX_DATAOUT3_23 |
| TCELL114:OUT.31.TMIN | CMAC.RX_DATAOUT3_87 |
| TCELL114:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN40 |
| TCELL114:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_PAUSE_ENABLE0 |
| TCELL114:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN41 |
| TCELL114:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_PAUSE_ENABLE1 |
| TCELL114:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN42 |
| TCELL114:IMUX.IMUX.16.DELAY | CMAC.CTL_RX_PAUSE_ENABLE2 |
| TCELL114:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN43 |
| TCELL114:IMUX.IMUX.22.DELAY | CMAC.CTL_RX_PAUSE_ENABLE3 |
| TCELL114:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN44 |
| TCELL114:IMUX.IMUX.28.DELAY | CMAC.CTL_RX_PAUSE_ENABLE4 |
| TCELL114:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN45 |
| TCELL114:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_PAUSE_ENABLE5 |
| TCELL114:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN46 |
| TCELL114:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_PAUSE_ENABLE6 |
| TCELL114:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN47 |
| TCELL114:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_PAUSE_ENABLE7 |
| TCELL115:OUT.1.TMIN | CMAC.RX_DATAOUT3_24 |
| TCELL115:OUT.3.TMIN | CMAC.RX_DATAOUT3_88 |
| TCELL115:OUT.5.TMIN | CMAC.RX_DATAOUT3_25 |
| TCELL115:OUT.7.TMIN | CMAC.RX_DATAOUT3_89 |
| TCELL115:OUT.9.TMIN | CMAC.RX_DATAOUT3_26 |
| TCELL115:OUT.11.TMIN | CMAC.RX_DATAOUT3_90 |
| TCELL115:OUT.13.TMIN | CMAC.RX_DATAOUT3_27 |
| TCELL115:OUT.15.TMIN | CMAC.RX_DATAOUT3_91 |
| TCELL115:OUT.16.TMIN | CMAC.RX_ERROUT3 |
| TCELL115:OUT.17.TMIN | CMAC.RX_DATAOUT3_28 |
| TCELL115:OUT.19.TMIN | CMAC.RX_DATAOUT3_92 |
| TCELL115:OUT.21.TMIN | CMAC.RX_DATAOUT3_29 |
| TCELL115:OUT.23.TMIN | CMAC.RX_DATAOUT3_93 |
| TCELL115:OUT.25.TMIN | CMAC.RX_DATAOUT3_30 |
| TCELL115:OUT.27.TMIN | CMAC.RX_DATAOUT3_94 |
| TCELL115:OUT.29.TMIN | CMAC.RX_DATAOUT3_31 |
| TCELL115:OUT.31.TMIN | CMAC.RX_DATAOUT3_95 |
| TCELL115:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN32 |
| TCELL115:IMUX.IMUX.4.DELAY | CMAC.CTL_RX_PAUSE_ENABLE8 |
| TCELL115:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN33 |
| TCELL115:IMUX.IMUX.10.DELAY | CMAC.CTL_RX_ENABLE |
| TCELL115:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN34 |
| TCELL115:IMUX.IMUX.16.DELAY | CMAC.DRP_EN |
| TCELL115:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN35 |
| TCELL115:IMUX.IMUX.22.DELAY | CMAC.DRP_WE |
| TCELL115:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN36 |
| TCELL115:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN37 |
| TCELL115:IMUX.IMUX.34.DELAY | CMAC.CTL_RX_CHECK_ETYPE_PPP |
| TCELL115:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN38 |
| TCELL115:IMUX.IMUX.40.DELAY | CMAC.CTL_RX_CHECK_ETYPE_PCP |
| TCELL115:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN39 |
| TCELL115:IMUX.IMUX.46.DELAY | CMAC.CTL_RX_CHECK_ETYPE_GPP |
| TCELL116:OUT.1.TMIN | CMAC.RX_DATAOUT3_32 |
| TCELL116:OUT.3.TMIN | CMAC.RX_DATAOUT3_96 |
| TCELL116:OUT.5.TMIN | CMAC.RX_DATAOUT3_33 |
| TCELL116:OUT.7.TMIN | CMAC.RX_DATAOUT3_97 |
| TCELL116:OUT.9.TMIN | CMAC.RX_DATAOUT3_34 |
| TCELL116:OUT.11.TMIN | CMAC.RX_DATAOUT3_98 |
| TCELL116:OUT.13.TMIN | CMAC.RX_DATAOUT3_35 |
| TCELL116:OUT.15.TMIN | CMAC.RX_DATAOUT3_99 |
| TCELL116:OUT.16.TMIN | CMAC.RX_MTYOUT3_0 |
| TCELL116:OUT.17.TMIN | CMAC.RX_DATAOUT3_36 |
| TCELL116:OUT.19.TMIN | CMAC.RX_DATAOUT3_100 |
| TCELL116:OUT.21.TMIN | CMAC.RX_DATAOUT3_37 |
| TCELL116:OUT.23.TMIN | CMAC.RX_DATAOUT3_101 |
| TCELL116:OUT.25.TMIN | CMAC.RX_DATAOUT3_38 |
| TCELL116:OUT.27.TMIN | CMAC.RX_DATAOUT3_102 |
| TCELL116:OUT.29.TMIN | CMAC.RX_DATAOUT3_39 |
| TCELL116:OUT.31.TMIN | CMAC.RX_DATAOUT3_103 |
| TCELL116:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN24 |
| TCELL116:IMUX.IMUX.4.DELAY | CMAC.DRP_DI0 |
| TCELL116:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN25 |
| TCELL116:IMUX.IMUX.10.DELAY | CMAC.DRP_DI1 |
| TCELL116:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN26 |
| TCELL116:IMUX.IMUX.16.DELAY | CMAC.DRP_DI2 |
| TCELL116:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN27 |
| TCELL116:IMUX.IMUX.22.DELAY | CMAC.DRP_DI3 |
| TCELL116:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN28 |
| TCELL116:IMUX.IMUX.28.DELAY | CMAC.DRP_DI4 |
| TCELL116:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN29 |
| TCELL116:IMUX.IMUX.34.DELAY | CMAC.DRP_DI5 |
| TCELL116:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN30 |
| TCELL116:IMUX.IMUX.40.DELAY | CMAC.DRP_DI6 |
| TCELL116:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN31 |
| TCELL116:IMUX.IMUX.46.DELAY | CMAC.DRP_DI7 |
| TCELL117:OUT.1.TMIN | CMAC.RX_DATAOUT3_40 |
| TCELL117:OUT.3.TMIN | CMAC.RX_DATAOUT3_104 |
| TCELL117:OUT.5.TMIN | CMAC.RX_DATAOUT3_41 |
| TCELL117:OUT.7.TMIN | CMAC.RX_DATAOUT3_105 |
| TCELL117:OUT.9.TMIN | CMAC.RX_DATAOUT3_42 |
| TCELL117:OUT.11.TMIN | CMAC.RX_DATAOUT3_106 |
| TCELL117:OUT.13.TMIN | CMAC.RX_DATAOUT3_43 |
| TCELL117:OUT.15.TMIN | CMAC.RX_DATAOUT3_107 |
| TCELL117:OUT.16.TMIN | CMAC.RX_MTYOUT3_1 |
| TCELL117:OUT.17.TMIN | CMAC.RX_DATAOUT3_44 |
| TCELL117:OUT.19.TMIN | CMAC.RX_DATAOUT3_108 |
| TCELL117:OUT.21.TMIN | CMAC.RX_DATAOUT3_45 |
| TCELL117:OUT.23.TMIN | CMAC.RX_DATAOUT3_109 |
| TCELL117:OUT.25.TMIN | CMAC.RX_DATAOUT3_46 |
| TCELL117:OUT.27.TMIN | CMAC.RX_DATAOUT3_110 |
| TCELL117:OUT.29.TMIN | CMAC.RX_DATAOUT3_47 |
| TCELL117:OUT.31.TMIN | CMAC.RX_DATAOUT3_111 |
| TCELL117:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN16 |
| TCELL117:IMUX.IMUX.4.DELAY | CMAC.DRP_DI8 |
| TCELL117:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN17 |
| TCELL117:IMUX.IMUX.10.DELAY | CMAC.DRP_DI9 |
| TCELL117:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN18 |
| TCELL117:IMUX.IMUX.16.DELAY | CMAC.DRP_DI10 |
| TCELL117:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN19 |
| TCELL117:IMUX.IMUX.22.DELAY | CMAC.DRP_DI11 |
| TCELL117:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN20 |
| TCELL117:IMUX.IMUX.28.DELAY | CMAC.DRP_DI12 |
| TCELL117:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN21 |
| TCELL117:IMUX.IMUX.34.DELAY | CMAC.DRP_DI13 |
| TCELL117:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN22 |
| TCELL117:IMUX.IMUX.40.DELAY | CMAC.DRP_DI14 |
| TCELL117:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN23 |
| TCELL117:IMUX.IMUX.46.DELAY | CMAC.DRP_DI15 |
| TCELL118:OUT.1.TMIN | CMAC.RX_DATAOUT3_48 |
| TCELL118:OUT.3.TMIN | CMAC.RX_DATAOUT3_112 |
| TCELL118:OUT.5.TMIN | CMAC.RX_DATAOUT3_49 |
| TCELL118:OUT.7.TMIN | CMAC.RX_DATAOUT3_113 |
| TCELL118:OUT.9.TMIN | CMAC.RX_DATAOUT3_50 |
| TCELL118:OUT.11.TMIN | CMAC.RX_DATAOUT3_114 |
| TCELL118:OUT.13.TMIN | CMAC.RX_DATAOUT3_51 |
| TCELL118:OUT.15.TMIN | CMAC.RX_DATAOUT3_115 |
| TCELL118:OUT.16.TMIN | CMAC.RX_MTYOUT3_2 |
| TCELL118:OUT.17.TMIN | CMAC.RX_DATAOUT3_52 |
| TCELL118:OUT.19.TMIN | CMAC.RX_DATAOUT3_116 |
| TCELL118:OUT.21.TMIN | CMAC.RX_DATAOUT3_53 |
| TCELL118:OUT.23.TMIN | CMAC.RX_DATAOUT3_117 |
| TCELL118:OUT.25.TMIN | CMAC.RX_DATAOUT3_54 |
| TCELL118:OUT.27.TMIN | CMAC.RX_DATAOUT3_118 |
| TCELL118:OUT.29.TMIN | CMAC.RX_DATAOUT3_55 |
| TCELL118:OUT.31.TMIN | CMAC.RX_DATAOUT3_119 |
| TCELL118:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN8 |
| TCELL118:IMUX.IMUX.4.DELAY | CMAC.DRP_ADDR0 |
| TCELL118:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN9 |
| TCELL118:IMUX.IMUX.10.DELAY | CMAC.DRP_ADDR1 |
| TCELL118:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN10 |
| TCELL118:IMUX.IMUX.16.DELAY | CMAC.DRP_ADDR2 |
| TCELL118:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN11 |
| TCELL118:IMUX.IMUX.22.DELAY | CMAC.DRP_ADDR3 |
| TCELL118:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN12 |
| TCELL118:IMUX.IMUX.28.DELAY | CMAC.DRP_ADDR4 |
| TCELL118:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN13 |
| TCELL118:IMUX.IMUX.34.DELAY | CMAC.DRP_ADDR5 |
| TCELL118:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN14 |
| TCELL118:IMUX.IMUX.40.DELAY | CMAC.DRP_ADDR6 |
| TCELL118:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN15 |
| TCELL118:IMUX.IMUX.46.DELAY | CMAC.DRP_ADDR7 |
| TCELL119:OUT.1.TMIN | CMAC.RX_DATAOUT3_56 |
| TCELL119:OUT.3.TMIN | CMAC.RX_DATAOUT3_120 |
| TCELL119:OUT.5.TMIN | CMAC.RX_DATAOUT3_57 |
| TCELL119:OUT.7.TMIN | CMAC.RX_DATAOUT3_121 |
| TCELL119:OUT.9.TMIN | CMAC.RX_DATAOUT3_58 |
| TCELL119:OUT.11.TMIN | CMAC.RX_DATAOUT3_122 |
| TCELL119:OUT.13.TMIN | CMAC.RX_DATAOUT3_59 |
| TCELL119:OUT.15.TMIN | CMAC.RX_DATAOUT3_123 |
| TCELL119:OUT.16.TMIN | CMAC.RX_MTYOUT3_3 |
| TCELL119:OUT.17.TMIN | CMAC.RX_DATAOUT3_60 |
| TCELL119:OUT.19.TMIN | CMAC.RX_DATAOUT3_124 |
| TCELL119:OUT.21.TMIN | CMAC.RX_DATAOUT3_61 |
| TCELL119:OUT.23.TMIN | CMAC.RX_DATAOUT3_125 |
| TCELL119:OUT.25.TMIN | CMAC.RX_DATAOUT3_62 |
| TCELL119:OUT.27.TMIN | CMAC.RX_DATAOUT3_126 |
| TCELL119:OUT.29.TMIN | CMAC.RX_DATAOUT3_63 |
| TCELL119:OUT.31.TMIN | CMAC.RX_DATAOUT3_127 |
| TCELL119:IMUX.IMUX.1.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN0 |
| TCELL119:IMUX.IMUX.4.DELAY | CMAC.DRP_ADDR8 |
| TCELL119:IMUX.IMUX.7.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN1 |
| TCELL119:IMUX.IMUX.10.DELAY | CMAC.DRP_ADDR9 |
| TCELL119:IMUX.IMUX.13.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN2 |
| TCELL119:IMUX.IMUX.19.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN3 |
| TCELL119:IMUX.IMUX.25.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN4 |
| TCELL119:IMUX.IMUX.31.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN5 |
| TCELL119:IMUX.IMUX.37.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN6 |
| TCELL119:IMUX.IMUX.43.DELAY | CMAC.CTL_RX_SYSTEMTIMERIN7 |