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Configuration center

Tile CFG

Cells: 60 IRIs: 0

Bel CFG

ultrascale CFG bel CFG
PinDirectionWires
BSCAN_CDR1outputTCELL42:OUT.4
BSCAN_CDR2outputTCELL42:OUT.6
BSCAN_CDR3outputTCELL54:OUT.18
BSCAN_CDR4outputTCELL54:OUT.20
BSCAN_CLKDR1outputTCELL42:OUT.8
BSCAN_CLKDR2outputTCELL42:OUT.10
BSCAN_CLKDR3outputTCELL54:OUT.22
BSCAN_CLKDR4outputTCELL54:OUT.24
BSCAN_RTI1outputTCELL42:OUT.12
BSCAN_RTI2outputTCELL42:OUT.14
BSCAN_RTI3outputTCELL54:OUT.26
BSCAN_RTI4outputTCELL54:OUT.28
BSCAN_SDR1outputTCELL42:OUT.16
BSCAN_SDR2outputTCELL42:OUT.18
BSCAN_SDR3outputTCELL53:OUT.0
BSCAN_SDR4outputTCELL53:OUT.2
BSCAN_SEL1outputTCELL42:OUT.20
BSCAN_SEL2outputTCELL42:OUT.22
BSCAN_SEL3outputTCELL53:OUT.4
BSCAN_SEL4outputTCELL53:OUT.6
BSCAN_TCK1outputTCELL43:OUT.6
BSCAN_TCK2outputTCELL43:OUT.8
BSCAN_TCK3outputTCELL54:OUT.6
BSCAN_TCK4outputTCELL54:OUT.8
BSCAN_TDI1outputTCELL43:OUT.14
BSCAN_TDI2outputTCELL43:OUT.16
BSCAN_TDI3outputTCELL54:OUT.14
BSCAN_TDI4outputTCELL54:OUT.16
BSCAN_TDO1inputTCELL43:IMUX.IMUX.2
BSCAN_TDO2inputTCELL43:IMUX.IMUX.3
BSCAN_TDO3inputTCELL54:IMUX.IMUX.2
BSCAN_TDO4inputTCELL54:IMUX.IMUX.3
BSCAN_TLR1outputTCELL42:OUT.24
BSCAN_TLR2outputTCELL42:OUT.26
BSCAN_TLR3outputTCELL53:OUT.8
BSCAN_TLR4outputTCELL53:OUT.10
BSCAN_TMS1outputTCELL43:OUT.10
BSCAN_TMS2outputTCELL43:OUT.12
BSCAN_TMS3outputTCELL54:OUT.10
BSCAN_TMS4outputTCELL54:OUT.12
BSCAN_UDR1outputTCELL42:OUT.28
BSCAN_UDR2outputTCELL42:OUT.30
BSCAN_UDR3outputTCELL53:OUT.12
BSCAN_UDR4outputTCELL53:OUT.14
DCI_LOCKoutputTCELL42:OUT.2
DCI_USR_RESET_INinputTCELL42:IMUX.IMUX.3
ECC_END_OF_FRAMEoutputTCELL51:OUT.26
ECC_END_OF_SCANoutputTCELL51:OUT.28
ECC_ERROR_NOTSINGLEoutputTCELL51:OUT.22
ECC_ERROR_SINGLEoutputTCELL51:OUT.24
ECC_FAR0outputTCELL52:OUT.0
ECC_FAR1outputTCELL52:OUT.2
ECC_FAR10outputTCELL52:OUT.20
ECC_FAR11outputTCELL52:OUT.22
ECC_FAR12outputTCELL52:OUT.24
ECC_FAR13outputTCELL52:OUT.26
ECC_FAR14outputTCELL52:OUT.28
ECC_FAR15outputTCELL52:OUT.30
ECC_FAR16outputTCELL51:OUT.0
ECC_FAR17outputTCELL51:OUT.2
ECC_FAR18outputTCELL51:OUT.4
ECC_FAR19outputTCELL51:OUT.6
ECC_FAR2outputTCELL52:OUT.4
ECC_FAR20outputTCELL51:OUT.8
ECC_FAR21outputTCELL51:OUT.10
ECC_FAR22outputTCELL51:OUT.12
ECC_FAR23outputTCELL51:OUT.14
ECC_FAR24outputTCELL51:OUT.16
ECC_FAR25outputTCELL51:OUT.18
ECC_FAR3outputTCELL52:OUT.6
ECC_FAR4outputTCELL52:OUT.8
ECC_FAR5outputTCELL52:OUT.10
ECC_FAR6outputTCELL52:OUT.12
ECC_FAR7outputTCELL52:OUT.14
ECC_FAR8outputTCELL52:OUT.16
ECC_FAR9outputTCELL52:OUT.18
ECC_FAR_SEL0inputTCELL51:IMUX.IMUX.15
ECC_FAR_SEL1inputTCELL51:IMUX.IMUX.16
EOSoutputTCELL47:OUT.10
ICAP_AVAIL_BOToutputTCELL43:OUT.4
ICAP_AVAIL_TOPoutputTCELL54:OUT.4
ICAP_CLK_BOT_BinputTCELL45:IMUX.CTRL.0
ICAP_CLK_TOP_BinputTCELL56:IMUX.CTRL.0
ICAP_CS_B_BOTinputTCELL43:IMUX.IMUX.1
ICAP_CS_B_TOPinputTCELL54:IMUX.IMUX.1
ICAP_DATA_BOT0inputTCELL44:IMUX.IMUX.0
ICAP_DATA_BOT1inputTCELL44:IMUX.IMUX.1
ICAP_DATA_BOT10inputTCELL44:IMUX.IMUX.10
ICAP_DATA_BOT11inputTCELL44:IMUX.IMUX.11
ICAP_DATA_BOT12inputTCELL44:IMUX.IMUX.12
ICAP_DATA_BOT13inputTCELL44:IMUX.IMUX.13
ICAP_DATA_BOT14inputTCELL44:IMUX.IMUX.14
ICAP_DATA_BOT15inputTCELL44:IMUX.IMUX.15
ICAP_DATA_BOT16inputTCELL45:IMUX.IMUX.0
ICAP_DATA_BOT17inputTCELL45:IMUX.IMUX.1
ICAP_DATA_BOT18inputTCELL45:IMUX.IMUX.2
ICAP_DATA_BOT19inputTCELL45:IMUX.IMUX.3
ICAP_DATA_BOT2inputTCELL44:IMUX.IMUX.2
ICAP_DATA_BOT20inputTCELL45:IMUX.IMUX.4
ICAP_DATA_BOT21inputTCELL45:IMUX.IMUX.5
ICAP_DATA_BOT22inputTCELL45:IMUX.IMUX.6
ICAP_DATA_BOT23inputTCELL45:IMUX.IMUX.7
ICAP_DATA_BOT24inputTCELL45:IMUX.IMUX.8
ICAP_DATA_BOT25inputTCELL45:IMUX.IMUX.9
ICAP_DATA_BOT26inputTCELL45:IMUX.IMUX.10
ICAP_DATA_BOT27inputTCELL45:IMUX.IMUX.11
ICAP_DATA_BOT28inputTCELL45:IMUX.IMUX.12
ICAP_DATA_BOT29inputTCELL45:IMUX.IMUX.13
ICAP_DATA_BOT3inputTCELL44:IMUX.IMUX.3
ICAP_DATA_BOT30inputTCELL45:IMUX.IMUX.14
ICAP_DATA_BOT31inputTCELL45:IMUX.IMUX.15
ICAP_DATA_BOT4inputTCELL44:IMUX.IMUX.4
ICAP_DATA_BOT5inputTCELL44:IMUX.IMUX.5
ICAP_DATA_BOT6inputTCELL44:IMUX.IMUX.6
ICAP_DATA_BOT7inputTCELL44:IMUX.IMUX.7
ICAP_DATA_BOT8inputTCELL44:IMUX.IMUX.8
ICAP_DATA_BOT9inputTCELL44:IMUX.IMUX.9
ICAP_DATA_TOP0inputTCELL55:IMUX.IMUX.0
ICAP_DATA_TOP1inputTCELL55:IMUX.IMUX.1
ICAP_DATA_TOP10inputTCELL55:IMUX.IMUX.10
ICAP_DATA_TOP11inputTCELL55:IMUX.IMUX.11
ICAP_DATA_TOP12inputTCELL55:IMUX.IMUX.12
ICAP_DATA_TOP13inputTCELL55:IMUX.IMUX.13
ICAP_DATA_TOP14inputTCELL55:IMUX.IMUX.14
ICAP_DATA_TOP15inputTCELL55:IMUX.IMUX.15
ICAP_DATA_TOP16inputTCELL56:IMUX.IMUX.0
ICAP_DATA_TOP17inputTCELL56:IMUX.IMUX.1
ICAP_DATA_TOP18inputTCELL56:IMUX.IMUX.2
ICAP_DATA_TOP19inputTCELL56:IMUX.IMUX.3
ICAP_DATA_TOP2inputTCELL55:IMUX.IMUX.2
ICAP_DATA_TOP20inputTCELL56:IMUX.IMUX.4
ICAP_DATA_TOP21inputTCELL56:IMUX.IMUX.5
ICAP_DATA_TOP22inputTCELL56:IMUX.IMUX.6
ICAP_DATA_TOP23inputTCELL56:IMUX.IMUX.7
ICAP_DATA_TOP24inputTCELL56:IMUX.IMUX.8
ICAP_DATA_TOP25inputTCELL56:IMUX.IMUX.9
ICAP_DATA_TOP26inputTCELL56:IMUX.IMUX.10
ICAP_DATA_TOP27inputTCELL56:IMUX.IMUX.11
ICAP_DATA_TOP28inputTCELL56:IMUX.IMUX.12
ICAP_DATA_TOP29inputTCELL56:IMUX.IMUX.13
ICAP_DATA_TOP3inputTCELL55:IMUX.IMUX.3
ICAP_DATA_TOP30inputTCELL56:IMUX.IMUX.14
ICAP_DATA_TOP31inputTCELL56:IMUX.IMUX.15
ICAP_DATA_TOP4inputTCELL55:IMUX.IMUX.4
ICAP_DATA_TOP5inputTCELL55:IMUX.IMUX.5
ICAP_DATA_TOP6inputTCELL55:IMUX.IMUX.6
ICAP_DATA_TOP7inputTCELL55:IMUX.IMUX.7
ICAP_DATA_TOP8inputTCELL55:IMUX.IMUX.8
ICAP_DATA_TOP9inputTCELL55:IMUX.IMUX.9
ICAP_OUT_BOT0outputTCELL44:OUT.0
ICAP_OUT_BOT1outputTCELL44:OUT.2
ICAP_OUT_BOT10outputTCELL44:OUT.20
ICAP_OUT_BOT11outputTCELL44:OUT.22
ICAP_OUT_BOT12outputTCELL44:OUT.24
ICAP_OUT_BOT13outputTCELL44:OUT.26
ICAP_OUT_BOT14outputTCELL44:OUT.28
ICAP_OUT_BOT15outputTCELL44:OUT.30
ICAP_OUT_BOT16outputTCELL45:OUT.0
ICAP_OUT_BOT17outputTCELL45:OUT.2
ICAP_OUT_BOT18outputTCELL45:OUT.4
ICAP_OUT_BOT19outputTCELL45:OUT.6
ICAP_OUT_BOT2outputTCELL44:OUT.4
ICAP_OUT_BOT20outputTCELL45:OUT.8
ICAP_OUT_BOT21outputTCELL45:OUT.10
ICAP_OUT_BOT22outputTCELL45:OUT.12
ICAP_OUT_BOT23outputTCELL45:OUT.14
ICAP_OUT_BOT24outputTCELL45:OUT.16
ICAP_OUT_BOT25outputTCELL45:OUT.18
ICAP_OUT_BOT26outputTCELL45:OUT.20
ICAP_OUT_BOT27outputTCELL45:OUT.22
ICAP_OUT_BOT28outputTCELL45:OUT.24
ICAP_OUT_BOT29outputTCELL45:OUT.26
ICAP_OUT_BOT3outputTCELL44:OUT.6
ICAP_OUT_BOT30outputTCELL45:OUT.28
ICAP_OUT_BOT31outputTCELL45:OUT.30
ICAP_OUT_BOT4outputTCELL44:OUT.8
ICAP_OUT_BOT5outputTCELL44:OUT.10
ICAP_OUT_BOT6outputTCELL44:OUT.12
ICAP_OUT_BOT7outputTCELL44:OUT.14
ICAP_OUT_BOT8outputTCELL44:OUT.16
ICAP_OUT_BOT9outputTCELL44:OUT.18
ICAP_OUT_TOP0outputTCELL55:OUT.0
ICAP_OUT_TOP1outputTCELL55:OUT.2
ICAP_OUT_TOP10outputTCELL55:OUT.20
ICAP_OUT_TOP11outputTCELL55:OUT.22
ICAP_OUT_TOP12outputTCELL55:OUT.24
ICAP_OUT_TOP13outputTCELL55:OUT.26
ICAP_OUT_TOP14outputTCELL55:OUT.28
ICAP_OUT_TOP15outputTCELL55:OUT.30
ICAP_OUT_TOP16outputTCELL56:OUT.0
ICAP_OUT_TOP17outputTCELL56:OUT.2
ICAP_OUT_TOP18outputTCELL56:OUT.4
ICAP_OUT_TOP19outputTCELL56:OUT.6
ICAP_OUT_TOP2outputTCELL55:OUT.4
ICAP_OUT_TOP20outputTCELL56:OUT.8
ICAP_OUT_TOP21outputTCELL56:OUT.10
ICAP_OUT_TOP22outputTCELL56:OUT.12
ICAP_OUT_TOP23outputTCELL56:OUT.14
ICAP_OUT_TOP24outputTCELL56:OUT.16
ICAP_OUT_TOP25outputTCELL56:OUT.18
ICAP_OUT_TOP26outputTCELL56:OUT.20
ICAP_OUT_TOP27outputTCELL56:OUT.22
ICAP_OUT_TOP28outputTCELL56:OUT.24
ICAP_OUT_TOP29outputTCELL56:OUT.26
ICAP_OUT_TOP3outputTCELL55:OUT.6
ICAP_OUT_TOP30outputTCELL56:OUT.28
ICAP_OUT_TOP31outputTCELL56:OUT.30
ICAP_OUT_TOP4outputTCELL55:OUT.8
ICAP_OUT_TOP5outputTCELL55:OUT.10
ICAP_OUT_TOP6outputTCELL55:OUT.12
ICAP_OUT_TOP7outputTCELL55:OUT.14
ICAP_OUT_TOP8outputTCELL55:OUT.16
ICAP_OUT_TOP9outputTCELL55:OUT.18
ICAP_PR_DONE_BOToutputTCELL43:OUT.0
ICAP_PR_DONE_TOPoutputTCELL54:OUT.0
ICAP_PR_ERROR_BOToutputTCELL43:OUT.2
ICAP_PR_ERROR_TOPoutputTCELL54:OUT.2
ICAP_RDWR_B_BOTinputTCELL43:IMUX.IMUX.0
ICAP_RDWR_B_TOPinputTCELL54:IMUX.IMUX.0
IOX_CCLKoutputTCELL50:OUT.0
IOX_CFGDATA0outputTCELL48:OUT.0
IOX_CFGDATA1outputTCELL48:OUT.2
IOX_CFGDATA10outputTCELL48:OUT.20
IOX_CFGDATA11outputTCELL48:OUT.22
IOX_CFGDATA12outputTCELL48:OUT.24
IOX_CFGDATA13outputTCELL48:OUT.26
IOX_CFGDATA14outputTCELL48:OUT.28
IOX_CFGDATA15outputTCELL48:OUT.30
IOX_CFGDATA16outputTCELL49:OUT.0
IOX_CFGDATA17outputTCELL49:OUT.2
IOX_CFGDATA18outputTCELL49:OUT.4
IOX_CFGDATA19outputTCELL49:OUT.6
IOX_CFGDATA2outputTCELL48:OUT.4
IOX_CFGDATA20outputTCELL49:OUT.8
IOX_CFGDATA21outputTCELL49:OUT.10
IOX_CFGDATA22outputTCELL49:OUT.12
IOX_CFGDATA23outputTCELL49:OUT.14
IOX_CFGDATA24outputTCELL49:OUT.16
IOX_CFGDATA25outputTCELL49:OUT.18
IOX_CFGDATA26outputTCELL49:OUT.20
IOX_CFGDATA27outputTCELL49:OUT.22
IOX_CFGDATA28outputTCELL49:OUT.24
IOX_CFGDATA29outputTCELL49:OUT.26
IOX_CFGDATA3outputTCELL48:OUT.6
IOX_CFGDATA30outputTCELL49:OUT.28
IOX_CFGDATA31outputTCELL49:OUT.30
IOX_CFGDATA4outputTCELL48:OUT.8
IOX_CFGDATA5outputTCELL48:OUT.10
IOX_CFGDATA6outputTCELL48:OUT.12
IOX_CFGDATA7outputTCELL48:OUT.14
IOX_CFGDATA8outputTCELL48:OUT.16
IOX_CFGDATA9outputTCELL48:OUT.18
IOX_CFGMASTERoutputTCELL50:OUT.2
IOX_INITBIoutputTCELL50:OUT.6
IOX_INITBOinputTCELL48:IMUX.IMUX.1
IOX_MODE0outputTCELL50:OUT.12
IOX_MODE1outputTCELL50:OUT.14
IOX_MODE2outputTCELL50:OUT.16
IOX_PUDCBoutputTCELL50:OUT.8
IOX_RDWRBoutputTCELL50:OUT.10
IOX_TDOinputTCELL48:IMUX.IMUX.0
IOX_VGG_COMP_OUToutputTCELL50:OUT.4
KEY_CLEARinputTCELL47:IMUX.IMUX.0
PROG_ACKinputTCELL47:IMUX.IMUX.1
PROG_REQoutputTCELL47:OUT.8
RBCRC_ERRORoutputTCELL51:OUT.20
START_CFG_CLKoutputTCELL47:OUT.14
START_CFG_MCLKoutputTCELL47:OUT.12
USR_ACCESS_CLKoutputTCELL57:OUT.2
USR_ACCESS_DATA0outputTCELL58:OUT.0
USR_ACCESS_DATA1outputTCELL58:OUT.2
USR_ACCESS_DATA10outputTCELL58:OUT.20
USR_ACCESS_DATA11outputTCELL58:OUT.22
USR_ACCESS_DATA12outputTCELL58:OUT.24
USR_ACCESS_DATA13outputTCELL58:OUT.26
USR_ACCESS_DATA14outputTCELL58:OUT.28
USR_ACCESS_DATA15outputTCELL58:OUT.30
USR_ACCESS_DATA16outputTCELL59:OUT.0
USR_ACCESS_DATA17outputTCELL59:OUT.2
USR_ACCESS_DATA18outputTCELL59:OUT.4
USR_ACCESS_DATA19outputTCELL59:OUT.6
USR_ACCESS_DATA2outputTCELL58:OUT.4
USR_ACCESS_DATA20outputTCELL59:OUT.8
USR_ACCESS_DATA21outputTCELL59:OUT.10
USR_ACCESS_DATA22outputTCELL59:OUT.12
USR_ACCESS_DATA23outputTCELL59:OUT.14
USR_ACCESS_DATA24outputTCELL59:OUT.16
USR_ACCESS_DATA25outputTCELL59:OUT.18
USR_ACCESS_DATA26outputTCELL59:OUT.20
USR_ACCESS_DATA27outputTCELL59:OUT.22
USR_ACCESS_DATA28outputTCELL59:OUT.24
USR_ACCESS_DATA29outputTCELL59:OUT.26
USR_ACCESS_DATA3outputTCELL58:OUT.6
USR_ACCESS_DATA30outputTCELL59:OUT.28
USR_ACCESS_DATA31outputTCELL59:OUT.30
USR_ACCESS_DATA4outputTCELL58:OUT.8
USR_ACCESS_DATA5outputTCELL58:OUT.10
USR_ACCESS_DATA6outputTCELL58:OUT.12
USR_ACCESS_DATA7outputTCELL58:OUT.14
USR_ACCESS_DATA8outputTCELL58:OUT.16
USR_ACCESS_DATA9outputTCELL58:OUT.18
USR_ACCESS_VALIDoutputTCELL57:OUT.0
USR_CCLK_O_BinputTCELL47:IMUX.CTRL.0
USR_CCLK_TSinputTCELL47:IMUX.IMUX.2
USR_DNA_CLK_BinputTCELL42:IMUX.CTRL.0
USR_DNA_DINinputTCELL42:IMUX.IMUX.0
USR_DNA_OUToutputTCELL42:OUT.0
USR_DNA_READinputTCELL42:IMUX.IMUX.1
USR_DNA_SHIFTinputTCELL42:IMUX.IMUX.2
USR_DONE_OinputTCELL47:IMUX.IMUX.3
USR_DONE_TSinputTCELL47:IMUX.IMUX.4
USR_D_O_CFGIO0inputTCELL47:IMUX.IMUX.9
USR_D_O_CFGIO1inputTCELL47:IMUX.IMUX.10
USR_D_O_CFGIO2inputTCELL47:IMUX.IMUX.11
USR_D_O_CFGIO3inputTCELL47:IMUX.IMUX.12
USR_D_PIN_CFGIO0outputTCELL47:OUT.0
USR_D_PIN_CFGIO1outputTCELL47:OUT.2
USR_D_PIN_CFGIO2outputTCELL47:OUT.4
USR_D_PIN_CFGIO3outputTCELL47:OUT.6
USR_D_TS_CFGIO0inputTCELL47:IMUX.IMUX.13
USR_D_TS_CFGIO1inputTCELL47:IMUX.IMUX.14
USR_D_TS_CFGIO2inputTCELL47:IMUX.IMUX.15
USR_D_TS_CFGIO3inputTCELL47:IMUX.IMUX.16
USR_EFUSE0outputTCELL46:OUT.0
USR_EFUSE1outputTCELL46:OUT.2
USR_EFUSE10outputTCELL46:OUT.20
USR_EFUSE11outputTCELL46:OUT.22
USR_EFUSE12outputTCELL46:OUT.24
USR_EFUSE13outputTCELL46:OUT.26
USR_EFUSE14outputTCELL46:OUT.28
USR_EFUSE15outputTCELL46:OUT.30
USR_EFUSE16outputTCELL41:OUT.0
USR_EFUSE17outputTCELL41:OUT.2
USR_EFUSE18outputTCELL41:OUT.4
USR_EFUSE19outputTCELL41:OUT.6
USR_EFUSE2outputTCELL46:OUT.4
USR_EFUSE20outputTCELL41:OUT.8
USR_EFUSE21outputTCELL41:OUT.10
USR_EFUSE22outputTCELL41:OUT.12
USR_EFUSE23outputTCELL41:OUT.14
USR_EFUSE24outputTCELL41:OUT.16
USR_EFUSE25outputTCELL41:OUT.18
USR_EFUSE26outputTCELL41:OUT.20
USR_EFUSE27outputTCELL41:OUT.22
USR_EFUSE28outputTCELL41:OUT.24
USR_EFUSE29outputTCELL41:OUT.26
USR_EFUSE3outputTCELL46:OUT.6
USR_EFUSE30outputTCELL41:OUT.28
USR_EFUSE31outputTCELL41:OUT.30
USR_EFUSE4outputTCELL46:OUT.8
USR_EFUSE5outputTCELL46:OUT.10
USR_EFUSE6outputTCELL46:OUT.12
USR_EFUSE7outputTCELL46:OUT.14
USR_EFUSE8outputTCELL46:OUT.16
USR_EFUSE9outputTCELL46:OUT.18
USR_FCS_B_OinputTCELL47:IMUX.IMUX.7
USR_FCS_B_TSinputTCELL47:IMUX.IMUX.8
USR_GSRinputTCELL47:IMUX.IMUX.5
USR_GTSinputTCELL47:IMUX.IMUX.6
USR_TCK_BinputTCELL43:IMUX.CTRL.1
USR_TDIinputTCELL43:IMUX.IMUX.6
USR_TDOoutputTCELL43:OUT.18
USR_TMSinputTCELL43:IMUX.IMUX.5

Bel ABUS_SWITCH_CFG

ultrascale CFG bel ABUS_SWITCH_CFG
PinDirectionWires

Bel wires

ultrascale CFG bel wires
WirePins
TCELL41:OUT.0CFG.USR_EFUSE16
TCELL41:OUT.2CFG.USR_EFUSE17
TCELL41:OUT.4CFG.USR_EFUSE18
TCELL41:OUT.6CFG.USR_EFUSE19
TCELL41:OUT.8CFG.USR_EFUSE20
TCELL41:OUT.10CFG.USR_EFUSE21
TCELL41:OUT.12CFG.USR_EFUSE22
TCELL41:OUT.14CFG.USR_EFUSE23
TCELL41:OUT.16CFG.USR_EFUSE24
TCELL41:OUT.18CFG.USR_EFUSE25
TCELL41:OUT.20CFG.USR_EFUSE26
TCELL41:OUT.22CFG.USR_EFUSE27
TCELL41:OUT.24CFG.USR_EFUSE28
TCELL41:OUT.26CFG.USR_EFUSE29
TCELL41:OUT.28CFG.USR_EFUSE30
TCELL41:OUT.30CFG.USR_EFUSE31
TCELL42:OUT.0CFG.USR_DNA_OUT
TCELL42:OUT.2CFG.DCI_LOCK
TCELL42:OUT.4CFG.BSCAN_CDR1
TCELL42:OUT.6CFG.BSCAN_CDR2
TCELL42:OUT.8CFG.BSCAN_CLKDR1
TCELL42:OUT.10CFG.BSCAN_CLKDR2
TCELL42:OUT.12CFG.BSCAN_RTI1
TCELL42:OUT.14CFG.BSCAN_RTI2
TCELL42:OUT.16CFG.BSCAN_SDR1
TCELL42:OUT.18CFG.BSCAN_SDR2
TCELL42:OUT.20CFG.BSCAN_SEL1
TCELL42:OUT.22CFG.BSCAN_SEL2
TCELL42:OUT.24CFG.BSCAN_TLR1
TCELL42:OUT.26CFG.BSCAN_TLR2
TCELL42:OUT.28CFG.BSCAN_UDR1
TCELL42:OUT.30CFG.BSCAN_UDR2
TCELL42:IMUX.CTRL.0CFG.USR_DNA_CLK_B
TCELL42:IMUX.IMUX.0CFG.USR_DNA_DIN
TCELL42:IMUX.IMUX.1CFG.USR_DNA_READ
TCELL42:IMUX.IMUX.2CFG.USR_DNA_SHIFT
TCELL42:IMUX.IMUX.3CFG.DCI_USR_RESET_IN
TCELL43:OUT.0CFG.ICAP_PR_DONE_BOT
TCELL43:OUT.2CFG.ICAP_PR_ERROR_BOT
TCELL43:OUT.4CFG.ICAP_AVAIL_BOT
TCELL43:OUT.6CFG.BSCAN_TCK1
TCELL43:OUT.8CFG.BSCAN_TCK2
TCELL43:OUT.10CFG.BSCAN_TMS1
TCELL43:OUT.12CFG.BSCAN_TMS2
TCELL43:OUT.14CFG.BSCAN_TDI1
TCELL43:OUT.16CFG.BSCAN_TDI2
TCELL43:OUT.18CFG.USR_TDO
TCELL43:IMUX.CTRL.1CFG.USR_TCK_B
TCELL43:IMUX.IMUX.0CFG.ICAP_RDWR_B_BOT
TCELL43:IMUX.IMUX.1CFG.ICAP_CS_B_BOT
TCELL43:IMUX.IMUX.2CFG.BSCAN_TDO1
TCELL43:IMUX.IMUX.3CFG.BSCAN_TDO2
TCELL43:IMUX.IMUX.5CFG.USR_TMS
TCELL43:IMUX.IMUX.6CFG.USR_TDI
TCELL44:OUT.0CFG.ICAP_OUT_BOT0
TCELL44:OUT.2CFG.ICAP_OUT_BOT1
TCELL44:OUT.4CFG.ICAP_OUT_BOT2
TCELL44:OUT.6CFG.ICAP_OUT_BOT3
TCELL44:OUT.8CFG.ICAP_OUT_BOT4
TCELL44:OUT.10CFG.ICAP_OUT_BOT5
TCELL44:OUT.12CFG.ICAP_OUT_BOT6
TCELL44:OUT.14CFG.ICAP_OUT_BOT7
TCELL44:OUT.16CFG.ICAP_OUT_BOT8
TCELL44:OUT.18CFG.ICAP_OUT_BOT9
TCELL44:OUT.20CFG.ICAP_OUT_BOT10
TCELL44:OUT.22CFG.ICAP_OUT_BOT11
TCELL44:OUT.24CFG.ICAP_OUT_BOT12
TCELL44:OUT.26CFG.ICAP_OUT_BOT13
TCELL44:OUT.28CFG.ICAP_OUT_BOT14
TCELL44:OUT.30CFG.ICAP_OUT_BOT15
TCELL44:IMUX.IMUX.0CFG.ICAP_DATA_BOT0
TCELL44:IMUX.IMUX.1CFG.ICAP_DATA_BOT1
TCELL44:IMUX.IMUX.2CFG.ICAP_DATA_BOT2
TCELL44:IMUX.IMUX.3CFG.ICAP_DATA_BOT3
TCELL44:IMUX.IMUX.4CFG.ICAP_DATA_BOT4
TCELL44:IMUX.IMUX.5CFG.ICAP_DATA_BOT5
TCELL44:IMUX.IMUX.6CFG.ICAP_DATA_BOT6
TCELL44:IMUX.IMUX.7CFG.ICAP_DATA_BOT7
TCELL44:IMUX.IMUX.8CFG.ICAP_DATA_BOT8
TCELL44:IMUX.IMUX.9CFG.ICAP_DATA_BOT9
TCELL44:IMUX.IMUX.10CFG.ICAP_DATA_BOT10
TCELL44:IMUX.IMUX.11CFG.ICAP_DATA_BOT11
TCELL44:IMUX.IMUX.12CFG.ICAP_DATA_BOT12
TCELL44:IMUX.IMUX.13CFG.ICAP_DATA_BOT13
TCELL44:IMUX.IMUX.14CFG.ICAP_DATA_BOT14
TCELL44:IMUX.IMUX.15CFG.ICAP_DATA_BOT15
TCELL45:OUT.0CFG.ICAP_OUT_BOT16
TCELL45:OUT.2CFG.ICAP_OUT_BOT17
TCELL45:OUT.4CFG.ICAP_OUT_BOT18
TCELL45:OUT.6CFG.ICAP_OUT_BOT19
TCELL45:OUT.8CFG.ICAP_OUT_BOT20
TCELL45:OUT.10CFG.ICAP_OUT_BOT21
TCELL45:OUT.12CFG.ICAP_OUT_BOT22
TCELL45:OUT.14CFG.ICAP_OUT_BOT23
TCELL45:OUT.16CFG.ICAP_OUT_BOT24
TCELL45:OUT.18CFG.ICAP_OUT_BOT25
TCELL45:OUT.20CFG.ICAP_OUT_BOT26
TCELL45:OUT.22CFG.ICAP_OUT_BOT27
TCELL45:OUT.24CFG.ICAP_OUT_BOT28
TCELL45:OUT.26CFG.ICAP_OUT_BOT29
TCELL45:OUT.28CFG.ICAP_OUT_BOT30
TCELL45:OUT.30CFG.ICAP_OUT_BOT31
TCELL45:IMUX.CTRL.0CFG.ICAP_CLK_BOT_B
TCELL45:IMUX.IMUX.0CFG.ICAP_DATA_BOT16
TCELL45:IMUX.IMUX.1CFG.ICAP_DATA_BOT17
TCELL45:IMUX.IMUX.2CFG.ICAP_DATA_BOT18
TCELL45:IMUX.IMUX.3CFG.ICAP_DATA_BOT19
TCELL45:IMUX.IMUX.4CFG.ICAP_DATA_BOT20
TCELL45:IMUX.IMUX.5CFG.ICAP_DATA_BOT21
TCELL45:IMUX.IMUX.6CFG.ICAP_DATA_BOT22
TCELL45:IMUX.IMUX.7CFG.ICAP_DATA_BOT23
TCELL45:IMUX.IMUX.8CFG.ICAP_DATA_BOT24
TCELL45:IMUX.IMUX.9CFG.ICAP_DATA_BOT25
TCELL45:IMUX.IMUX.10CFG.ICAP_DATA_BOT26
TCELL45:IMUX.IMUX.11CFG.ICAP_DATA_BOT27
TCELL45:IMUX.IMUX.12CFG.ICAP_DATA_BOT28
TCELL45:IMUX.IMUX.13CFG.ICAP_DATA_BOT29
TCELL45:IMUX.IMUX.14CFG.ICAP_DATA_BOT30
TCELL45:IMUX.IMUX.15CFG.ICAP_DATA_BOT31
TCELL46:OUT.0CFG.USR_EFUSE0
TCELL46:OUT.2CFG.USR_EFUSE1
TCELL46:OUT.4CFG.USR_EFUSE2
TCELL46:OUT.6CFG.USR_EFUSE3
TCELL46:OUT.8CFG.USR_EFUSE4
TCELL46:OUT.10CFG.USR_EFUSE5
TCELL46:OUT.12CFG.USR_EFUSE6
TCELL46:OUT.14CFG.USR_EFUSE7
TCELL46:OUT.16CFG.USR_EFUSE8
TCELL46:OUT.18CFG.USR_EFUSE9
TCELL46:OUT.20CFG.USR_EFUSE10
TCELL46:OUT.22CFG.USR_EFUSE11
TCELL46:OUT.24CFG.USR_EFUSE12
TCELL46:OUT.26CFG.USR_EFUSE13
TCELL46:OUT.28CFG.USR_EFUSE14
TCELL46:OUT.30CFG.USR_EFUSE15
TCELL47:OUT.0CFG.USR_D_PIN_CFGIO0
TCELL47:OUT.2CFG.USR_D_PIN_CFGIO1
TCELL47:OUT.4CFG.USR_D_PIN_CFGIO2
TCELL47:OUT.6CFG.USR_D_PIN_CFGIO3
TCELL47:OUT.8CFG.PROG_REQ
TCELL47:OUT.10CFG.EOS
TCELL47:OUT.12CFG.START_CFG_MCLK
TCELL47:OUT.14CFG.START_CFG_CLK
TCELL47:IMUX.CTRL.0CFG.USR_CCLK_O_B
TCELL47:IMUX.IMUX.0CFG.KEY_CLEAR
TCELL47:IMUX.IMUX.1CFG.PROG_ACK
TCELL47:IMUX.IMUX.2CFG.USR_CCLK_TS
TCELL47:IMUX.IMUX.3CFG.USR_DONE_O
TCELL47:IMUX.IMUX.4CFG.USR_DONE_TS
TCELL47:IMUX.IMUX.5CFG.USR_GSR
TCELL47:IMUX.IMUX.6CFG.USR_GTS
TCELL47:IMUX.IMUX.7CFG.USR_FCS_B_O
TCELL47:IMUX.IMUX.8CFG.USR_FCS_B_TS
TCELL47:IMUX.IMUX.9CFG.USR_D_O_CFGIO0
TCELL47:IMUX.IMUX.10CFG.USR_D_O_CFGIO1
TCELL47:IMUX.IMUX.11CFG.USR_D_O_CFGIO2
TCELL47:IMUX.IMUX.12CFG.USR_D_O_CFGIO3
TCELL47:IMUX.IMUX.13CFG.USR_D_TS_CFGIO0
TCELL47:IMUX.IMUX.14CFG.USR_D_TS_CFGIO1
TCELL47:IMUX.IMUX.15CFG.USR_D_TS_CFGIO2
TCELL47:IMUX.IMUX.16CFG.USR_D_TS_CFGIO3
TCELL48:OUT.0CFG.IOX_CFGDATA0
TCELL48:OUT.2CFG.IOX_CFGDATA1
TCELL48:OUT.4CFG.IOX_CFGDATA2
TCELL48:OUT.6CFG.IOX_CFGDATA3
TCELL48:OUT.8CFG.IOX_CFGDATA4
TCELL48:OUT.10CFG.IOX_CFGDATA5
TCELL48:OUT.12CFG.IOX_CFGDATA6
TCELL48:OUT.14CFG.IOX_CFGDATA7
TCELL48:OUT.16CFG.IOX_CFGDATA8
TCELL48:OUT.18CFG.IOX_CFGDATA9
TCELL48:OUT.20CFG.IOX_CFGDATA10
TCELL48:OUT.22CFG.IOX_CFGDATA11
TCELL48:OUT.24CFG.IOX_CFGDATA12
TCELL48:OUT.26CFG.IOX_CFGDATA13
TCELL48:OUT.28CFG.IOX_CFGDATA14
TCELL48:OUT.30CFG.IOX_CFGDATA15
TCELL48:IMUX.IMUX.0CFG.IOX_TDO
TCELL48:IMUX.IMUX.1CFG.IOX_INITBO
TCELL49:OUT.0CFG.IOX_CFGDATA16
TCELL49:OUT.2CFG.IOX_CFGDATA17
TCELL49:OUT.4CFG.IOX_CFGDATA18
TCELL49:OUT.6CFG.IOX_CFGDATA19
TCELL49:OUT.8CFG.IOX_CFGDATA20
TCELL49:OUT.10CFG.IOX_CFGDATA21
TCELL49:OUT.12CFG.IOX_CFGDATA22
TCELL49:OUT.14CFG.IOX_CFGDATA23
TCELL49:OUT.16CFG.IOX_CFGDATA24
TCELL49:OUT.18CFG.IOX_CFGDATA25
TCELL49:OUT.20CFG.IOX_CFGDATA26
TCELL49:OUT.22CFG.IOX_CFGDATA27
TCELL49:OUT.24CFG.IOX_CFGDATA28
TCELL49:OUT.26CFG.IOX_CFGDATA29
TCELL49:OUT.28CFG.IOX_CFGDATA30
TCELL49:OUT.30CFG.IOX_CFGDATA31
TCELL50:OUT.0CFG.IOX_CCLK
TCELL50:OUT.2CFG.IOX_CFGMASTER
TCELL50:OUT.4CFG.IOX_VGG_COMP_OUT
TCELL50:OUT.6CFG.IOX_INITBI
TCELL50:OUT.8CFG.IOX_PUDCB
TCELL50:OUT.10CFG.IOX_RDWRB
TCELL50:OUT.12CFG.IOX_MODE0
TCELL50:OUT.14CFG.IOX_MODE1
TCELL50:OUT.16CFG.IOX_MODE2
TCELL51:OUT.0CFG.ECC_FAR16
TCELL51:OUT.2CFG.ECC_FAR17
TCELL51:OUT.4CFG.ECC_FAR18
TCELL51:OUT.6CFG.ECC_FAR19
TCELL51:OUT.8CFG.ECC_FAR20
TCELL51:OUT.10CFG.ECC_FAR21
TCELL51:OUT.12CFG.ECC_FAR22
TCELL51:OUT.14CFG.ECC_FAR23
TCELL51:OUT.16CFG.ECC_FAR24
TCELL51:OUT.18CFG.ECC_FAR25
TCELL51:OUT.20CFG.RBCRC_ERROR
TCELL51:OUT.22CFG.ECC_ERROR_NOTSINGLE
TCELL51:OUT.24CFG.ECC_ERROR_SINGLE
TCELL51:OUT.26CFG.ECC_END_OF_FRAME
TCELL51:OUT.28CFG.ECC_END_OF_SCAN
TCELL51:IMUX.IMUX.15CFG.ECC_FAR_SEL0
TCELL51:IMUX.IMUX.16CFG.ECC_FAR_SEL1
TCELL52:OUT.0CFG.ECC_FAR0
TCELL52:OUT.2CFG.ECC_FAR1
TCELL52:OUT.4CFG.ECC_FAR2
TCELL52:OUT.6CFG.ECC_FAR3
TCELL52:OUT.8CFG.ECC_FAR4
TCELL52:OUT.10CFG.ECC_FAR5
TCELL52:OUT.12CFG.ECC_FAR6
TCELL52:OUT.14CFG.ECC_FAR7
TCELL52:OUT.16CFG.ECC_FAR8
TCELL52:OUT.18CFG.ECC_FAR9
TCELL52:OUT.20CFG.ECC_FAR10
TCELL52:OUT.22CFG.ECC_FAR11
TCELL52:OUT.24CFG.ECC_FAR12
TCELL52:OUT.26CFG.ECC_FAR13
TCELL52:OUT.28CFG.ECC_FAR14
TCELL52:OUT.30CFG.ECC_FAR15
TCELL53:OUT.0CFG.BSCAN_SDR3
TCELL53:OUT.2CFG.BSCAN_SDR4
TCELL53:OUT.4CFG.BSCAN_SEL3
TCELL53:OUT.6CFG.BSCAN_SEL4
TCELL53:OUT.8CFG.BSCAN_TLR3
TCELL53:OUT.10CFG.BSCAN_TLR4
TCELL53:OUT.12CFG.BSCAN_UDR3
TCELL53:OUT.14CFG.BSCAN_UDR4
TCELL54:OUT.0CFG.ICAP_PR_DONE_TOP
TCELL54:OUT.2CFG.ICAP_PR_ERROR_TOP
TCELL54:OUT.4CFG.ICAP_AVAIL_TOP
TCELL54:OUT.6CFG.BSCAN_TCK3
TCELL54:OUT.8CFG.BSCAN_TCK4
TCELL54:OUT.10CFG.BSCAN_TMS3
TCELL54:OUT.12CFG.BSCAN_TMS4
TCELL54:OUT.14CFG.BSCAN_TDI3
TCELL54:OUT.16CFG.BSCAN_TDI4
TCELL54:OUT.18CFG.BSCAN_CDR3
TCELL54:OUT.20CFG.BSCAN_CDR4
TCELL54:OUT.22CFG.BSCAN_CLKDR3
TCELL54:OUT.24CFG.BSCAN_CLKDR4
TCELL54:OUT.26CFG.BSCAN_RTI3
TCELL54:OUT.28CFG.BSCAN_RTI4
TCELL54:IMUX.IMUX.0CFG.ICAP_RDWR_B_TOP
TCELL54:IMUX.IMUX.1CFG.ICAP_CS_B_TOP
TCELL54:IMUX.IMUX.2CFG.BSCAN_TDO3
TCELL54:IMUX.IMUX.3CFG.BSCAN_TDO4
TCELL55:OUT.0CFG.ICAP_OUT_TOP0
TCELL55:OUT.2CFG.ICAP_OUT_TOP1
TCELL55:OUT.4CFG.ICAP_OUT_TOP2
TCELL55:OUT.6CFG.ICAP_OUT_TOP3
TCELL55:OUT.8CFG.ICAP_OUT_TOP4
TCELL55:OUT.10CFG.ICAP_OUT_TOP5
TCELL55:OUT.12CFG.ICAP_OUT_TOP6
TCELL55:OUT.14CFG.ICAP_OUT_TOP7
TCELL55:OUT.16CFG.ICAP_OUT_TOP8
TCELL55:OUT.18CFG.ICAP_OUT_TOP9
TCELL55:OUT.20CFG.ICAP_OUT_TOP10
TCELL55:OUT.22CFG.ICAP_OUT_TOP11
TCELL55:OUT.24CFG.ICAP_OUT_TOP12
TCELL55:OUT.26CFG.ICAP_OUT_TOP13
TCELL55:OUT.28CFG.ICAP_OUT_TOP14
TCELL55:OUT.30CFG.ICAP_OUT_TOP15
TCELL55:IMUX.IMUX.0CFG.ICAP_DATA_TOP0
TCELL55:IMUX.IMUX.1CFG.ICAP_DATA_TOP1
TCELL55:IMUX.IMUX.2CFG.ICAP_DATA_TOP2
TCELL55:IMUX.IMUX.3CFG.ICAP_DATA_TOP3
TCELL55:IMUX.IMUX.4CFG.ICAP_DATA_TOP4
TCELL55:IMUX.IMUX.5CFG.ICAP_DATA_TOP5
TCELL55:IMUX.IMUX.6CFG.ICAP_DATA_TOP6
TCELL55:IMUX.IMUX.7CFG.ICAP_DATA_TOP7
TCELL55:IMUX.IMUX.8CFG.ICAP_DATA_TOP8
TCELL55:IMUX.IMUX.9CFG.ICAP_DATA_TOP9
TCELL55:IMUX.IMUX.10CFG.ICAP_DATA_TOP10
TCELL55:IMUX.IMUX.11CFG.ICAP_DATA_TOP11
TCELL55:IMUX.IMUX.12CFG.ICAP_DATA_TOP12
TCELL55:IMUX.IMUX.13CFG.ICAP_DATA_TOP13
TCELL55:IMUX.IMUX.14CFG.ICAP_DATA_TOP14
TCELL55:IMUX.IMUX.15CFG.ICAP_DATA_TOP15
TCELL56:OUT.0CFG.ICAP_OUT_TOP16
TCELL56:OUT.2CFG.ICAP_OUT_TOP17
TCELL56:OUT.4CFG.ICAP_OUT_TOP18
TCELL56:OUT.6CFG.ICAP_OUT_TOP19
TCELL56:OUT.8CFG.ICAP_OUT_TOP20
TCELL56:OUT.10CFG.ICAP_OUT_TOP21
TCELL56:OUT.12CFG.ICAP_OUT_TOP22
TCELL56:OUT.14CFG.ICAP_OUT_TOP23
TCELL56:OUT.16CFG.ICAP_OUT_TOP24
TCELL56:OUT.18CFG.ICAP_OUT_TOP25
TCELL56:OUT.20CFG.ICAP_OUT_TOP26
TCELL56:OUT.22CFG.ICAP_OUT_TOP27
TCELL56:OUT.24CFG.ICAP_OUT_TOP28
TCELL56:OUT.26CFG.ICAP_OUT_TOP29
TCELL56:OUT.28CFG.ICAP_OUT_TOP30
TCELL56:OUT.30CFG.ICAP_OUT_TOP31
TCELL56:IMUX.CTRL.0CFG.ICAP_CLK_TOP_B
TCELL56:IMUX.IMUX.0CFG.ICAP_DATA_TOP16
TCELL56:IMUX.IMUX.1CFG.ICAP_DATA_TOP17
TCELL56:IMUX.IMUX.2CFG.ICAP_DATA_TOP18
TCELL56:IMUX.IMUX.3CFG.ICAP_DATA_TOP19
TCELL56:IMUX.IMUX.4CFG.ICAP_DATA_TOP20
TCELL56:IMUX.IMUX.5CFG.ICAP_DATA_TOP21
TCELL56:IMUX.IMUX.6CFG.ICAP_DATA_TOP22
TCELL56:IMUX.IMUX.7CFG.ICAP_DATA_TOP23
TCELL56:IMUX.IMUX.8CFG.ICAP_DATA_TOP24
TCELL56:IMUX.IMUX.9CFG.ICAP_DATA_TOP25
TCELL56:IMUX.IMUX.10CFG.ICAP_DATA_TOP26
TCELL56:IMUX.IMUX.11CFG.ICAP_DATA_TOP27
TCELL56:IMUX.IMUX.12CFG.ICAP_DATA_TOP28
TCELL56:IMUX.IMUX.13CFG.ICAP_DATA_TOP29
TCELL56:IMUX.IMUX.14CFG.ICAP_DATA_TOP30
TCELL56:IMUX.IMUX.15CFG.ICAP_DATA_TOP31
TCELL57:OUT.0CFG.USR_ACCESS_VALID
TCELL57:OUT.2CFG.USR_ACCESS_CLK
TCELL58:OUT.0CFG.USR_ACCESS_DATA0
TCELL58:OUT.2CFG.USR_ACCESS_DATA1
TCELL58:OUT.4CFG.USR_ACCESS_DATA2
TCELL58:OUT.6CFG.USR_ACCESS_DATA3
TCELL58:OUT.8CFG.USR_ACCESS_DATA4
TCELL58:OUT.10CFG.USR_ACCESS_DATA5
TCELL58:OUT.12CFG.USR_ACCESS_DATA6
TCELL58:OUT.14CFG.USR_ACCESS_DATA7
TCELL58:OUT.16CFG.USR_ACCESS_DATA8
TCELL58:OUT.18CFG.USR_ACCESS_DATA9
TCELL58:OUT.20CFG.USR_ACCESS_DATA10
TCELL58:OUT.22CFG.USR_ACCESS_DATA11
TCELL58:OUT.24CFG.USR_ACCESS_DATA12
TCELL58:OUT.26CFG.USR_ACCESS_DATA13
TCELL58:OUT.28CFG.USR_ACCESS_DATA14
TCELL58:OUT.30CFG.USR_ACCESS_DATA15
TCELL59:OUT.0CFG.USR_ACCESS_DATA16
TCELL59:OUT.2CFG.USR_ACCESS_DATA17
TCELL59:OUT.4CFG.USR_ACCESS_DATA18
TCELL59:OUT.6CFG.USR_ACCESS_DATA19
TCELL59:OUT.8CFG.USR_ACCESS_DATA20
TCELL59:OUT.10CFG.USR_ACCESS_DATA21
TCELL59:OUT.12CFG.USR_ACCESS_DATA22
TCELL59:OUT.14CFG.USR_ACCESS_DATA23
TCELL59:OUT.16CFG.USR_ACCESS_DATA24
TCELL59:OUT.18CFG.USR_ACCESS_DATA25
TCELL59:OUT.20CFG.USR_ACCESS_DATA26
TCELL59:OUT.22CFG.USR_ACCESS_DATA27
TCELL59:OUT.24CFG.USR_ACCESS_DATA28
TCELL59:OUT.26CFG.USR_ACCESS_DATA29
TCELL59:OUT.28CFG.USR_ACCESS_DATA30
TCELL59:OUT.30CFG.USR_ACCESS_DATA31

Tile CFGIO

Cells: 30 IRIs: 0

Bel PMV

ultrascale CFGIO bel PMV
PinDirectionWires
OUT1_INTOPoutputTCELL15:OUT.18
OUT2_INTOPoutputTCELL15:OUT.17
OUT3_INTOPoutputTCELL16:OUT.21
OUT4_INTOPoutputTCELL16:OUT.20
PMV_EN1_INTIPinputTCELL19:IMUX.IMUX.43
SPARE_IN1_INTIP0inputTCELL19:IMUX.IMUX.44
SPARE_IN1_INTIP1inputTCELL19:IMUX.IMUX.13
SPARE_IN1_INTIP2inputTCELL19:IMUX.IMUX.45
SPARE_IN1_INTIP3inputTCELL19:IMUX.IMUX.46
SPARE_IN1_INTIP4inputTCELL19:IMUX.IMUX.47
SPARE_IN1_INTIP5inputTCELL19:IMUX.IMUX.14

Bel PMV2

ultrascale CFGIO bel PMV2
PinDirectionWires
IMUX_IN_INT0inputTCELL25:IMUX.IMUX.38
IMUX_IN_INT1inputTCELL25:IMUX.IMUX.41
IMUX_IN_INT2inputTCELL25:IMUX.IMUX.40
IMUX_IN_INT3inputTCELL25:IMUX.IMUX.39
OUTS_INT0outputTCELL27:OUT.8
OUTS_INT1outputTCELL27:OUT.4
OUTS_INT2outputTCELL27:OUT.3

Bel PMVIOB

ultrascale CFGIO bel PMVIOB
PinDirectionWires
OUT_DIV2_HPIO_INTOPoutputTCELL24:OUT.11
OUT_DIV4_HPIO_INTOPoutputTCELL24:OUT.10
OUT_HPIO_INTOPoutputTCELL24:OUT.12
PMV_A_HPIO_INTIP0inputTCELL24:IMUX.IMUX.3
PMV_A_HPIO_INTIP1inputTCELL24:IMUX.IMUX.23
PMV_EN_HPIO_INTIPinputTCELL24:IMUX.IMUX.25

Bel MTBF3

ultrascale CFGIO bel MTBF3
PinDirectionWires
CAPTURE_CLK_INTIPinputTCELL27:IMUX.IMUX.24
CAPTURE_Q_INTOP0outputTCELL27:OUT.27
CAPTURE_Q_INTOP1outputTCELL27:OUT.28
CAPTURE_Q_INTOP2outputTCELL27:OUT.29
CAPTURE_Q_INTOP3outputTCELL27:OUT.30
CAPTURE_Q_INTOP4outputTCELL27:OUT.31
DATAIN_INTIPinputTCELL27:IMUX.IMUX.26
FF_CLK_INTIPinputTCELL27:IMUX.IMUX.25
FF_Q_INTOP0outputTCELL27:OUT.22
FF_Q_INTOP1outputTCELL27:OUT.23
FF_Q_INTOP2outputTCELL27:OUT.24
FF_Q_INTOP3outputTCELL27:OUT.25
FF_Q_INTOP4outputTCELL27:OUT.26
OUTPUT_SEL_INTIP0inputTCELL27:IMUX.IMUX.28
OUTPUT_SEL_INTIP1inputTCELL27:IMUX.IMUX.29
OUTPUT_SEL_INTIP2inputTCELL27:IMUX.IMUX.30
OUTPUT_SEL_INTIP3inputTCELL27:IMUX.IMUX.31
RESET_INTIPinputTCELL27:IMUX.IMUX.27
SYNC_ENABLE_INTIPinputTCELL27:IMUX.IMUX.5
TOGGLE_SEL_INTIPinputTCELL27:IMUX.IMUX.4

Bel wires

ultrascale CFGIO bel wires
WirePins
TCELL15:OUT.17PMV.OUT2_INTOP
TCELL15:OUT.18PMV.OUT1_INTOP
TCELL16:OUT.20PMV.OUT4_INTOP
TCELL16:OUT.21PMV.OUT3_INTOP
TCELL19:IMUX.IMUX.13PMV.SPARE_IN1_INTIP1
TCELL19:IMUX.IMUX.14PMV.SPARE_IN1_INTIP5
TCELL19:IMUX.IMUX.43PMV.PMV_EN1_INTIP
TCELL19:IMUX.IMUX.44PMV.SPARE_IN1_INTIP0
TCELL19:IMUX.IMUX.45PMV.SPARE_IN1_INTIP2
TCELL19:IMUX.IMUX.46PMV.SPARE_IN1_INTIP3
TCELL19:IMUX.IMUX.47PMV.SPARE_IN1_INTIP4
TCELL24:OUT.10PMVIOB.OUT_DIV4_HPIO_INTOP
TCELL24:OUT.11PMVIOB.OUT_DIV2_HPIO_INTOP
TCELL24:OUT.12PMVIOB.OUT_HPIO_INTOP
TCELL24:IMUX.IMUX.3PMVIOB.PMV_A_HPIO_INTIP0
TCELL24:IMUX.IMUX.23PMVIOB.PMV_A_HPIO_INTIP1
TCELL24:IMUX.IMUX.25PMVIOB.PMV_EN_HPIO_INTIP
TCELL25:IMUX.IMUX.38PMV2.IMUX_IN_INT0
TCELL25:IMUX.IMUX.39PMV2.IMUX_IN_INT3
TCELL25:IMUX.IMUX.40PMV2.IMUX_IN_INT2
TCELL25:IMUX.IMUX.41PMV2.IMUX_IN_INT1
TCELL27:OUT.3PMV2.OUTS_INT2
TCELL27:OUT.4PMV2.OUTS_INT1
TCELL27:OUT.8PMV2.OUTS_INT0
TCELL27:OUT.22MTBF3.FF_Q_INTOP0
TCELL27:OUT.23MTBF3.FF_Q_INTOP1
TCELL27:OUT.24MTBF3.FF_Q_INTOP2
TCELL27:OUT.25MTBF3.FF_Q_INTOP3
TCELL27:OUT.26MTBF3.FF_Q_INTOP4
TCELL27:OUT.27MTBF3.CAPTURE_Q_INTOP0
TCELL27:OUT.28MTBF3.CAPTURE_Q_INTOP1
TCELL27:OUT.29MTBF3.CAPTURE_Q_INTOP2
TCELL27:OUT.30MTBF3.CAPTURE_Q_INTOP3
TCELL27:OUT.31MTBF3.CAPTURE_Q_INTOP4
TCELL27:IMUX.IMUX.4MTBF3.TOGGLE_SEL_INTIP
TCELL27:IMUX.IMUX.5MTBF3.SYNC_ENABLE_INTIP
TCELL27:IMUX.IMUX.24MTBF3.CAPTURE_CLK_INTIP
TCELL27:IMUX.IMUX.25MTBF3.FF_CLK_INTIP
TCELL27:IMUX.IMUX.26MTBF3.DATAIN_INTIP
TCELL27:IMUX.IMUX.27MTBF3.RESET_INTIP
TCELL27:IMUX.IMUX.28MTBF3.OUTPUT_SEL_INTIP0
TCELL27:IMUX.IMUX.29MTBF3.OUTPUT_SEL_INTIP1
TCELL27:IMUX.IMUX.30MTBF3.OUTPUT_SEL_INTIP2
TCELL27:IMUX.IMUX.31MTBF3.OUTPUT_SEL_INTIP3

Tile AMS

Cells: 30 IRIs: 0

Bel SYSMON

ultrascale AMS bel SYSMON
PinDirectionWires
ALM0outputTCELL7:OUT.0
ALM1outputTCELL7:OUT.1
ALM10outputTCELL7:OUT.10
ALM11outputTCELL7:OUT.11
ALM12outputTCELL7:OUT.12
ALM13outputTCELL7:OUT.13
ALM14outputTCELL7:OUT.14
ALM15outputTCELL7:OUT.15
ALM2outputTCELL7:OUT.2
ALM3outputTCELL7:OUT.3
ALM4outputTCELL7:OUT.4
ALM5outputTCELL7:OUT.5
ALM6outputTCELL7:OUT.6
ALM7outputTCELL7:OUT.7
ALM8outputTCELL7:OUT.8
ALM9outputTCELL7:OUT.9
BUSYoutputTCELL7:OUT.17
CHANNEL0outputTCELL7:OUT.18
CHANNEL1outputTCELL7:OUT.19
CHANNEL2outputTCELL7:OUT.20
CHANNEL3outputTCELL7:OUT.21
CHANNEL4outputTCELL7:OUT.22
CHANNEL5outputTCELL7:OUT.23
CONVSTinputTCELL7:IMUX.IMUX.2
CONVST_CLK_BinputTCELL6:IMUX.CTRL.1
DADDR0inputTCELL0:IMUX.IMUX.0
DADDR1inputTCELL0:IMUX.IMUX.1
DADDR2inputTCELL0:IMUX.IMUX.2
DADDR3inputTCELL0:IMUX.IMUX.3
DADDR4inputTCELL0:IMUX.IMUX.4
DADDR5inputTCELL0:IMUX.IMUX.5
DADDR6inputTCELL0:IMUX.IMUX.6
DADDR7inputTCELL0:IMUX.IMUX.7
DATA_READY_ADC1_FinputTCELL0:IMUX.IMUX.24
DATA_READY_ADC2_FinputTCELL0:IMUX.IMUX.25
DCLK_BinputTCELL6:IMUX.CTRL.0
DEC_OUT_ADC1_F0inputTCELL0:IMUX.IMUX.26
DEC_OUT_ADC1_F1inputTCELL0:IMUX.IMUX.27
DEC_OUT_ADC1_F10inputTCELL0:IMUX.IMUX.36
DEC_OUT_ADC1_F11inputTCELL0:IMUX.IMUX.37
DEC_OUT_ADC1_F12inputTCELL0:IMUX.IMUX.38
DEC_OUT_ADC1_F13inputTCELL0:IMUX.IMUX.39
DEC_OUT_ADC1_F14inputTCELL0:IMUX.IMUX.40
DEC_OUT_ADC1_F15inputTCELL0:IMUX.IMUX.41
DEC_OUT_ADC1_F2inputTCELL0:IMUX.IMUX.28
DEC_OUT_ADC1_F3inputTCELL0:IMUX.IMUX.29
DEC_OUT_ADC1_F4inputTCELL0:IMUX.IMUX.30
DEC_OUT_ADC1_F5inputTCELL0:IMUX.IMUX.31
DEC_OUT_ADC1_F6inputTCELL0:IMUX.IMUX.32
DEC_OUT_ADC1_F7inputTCELL0:IMUX.IMUX.33
DEC_OUT_ADC1_F8inputTCELL0:IMUX.IMUX.34
DEC_OUT_ADC1_F9inputTCELL0:IMUX.IMUX.35
DEC_OUT_ADC2_F0inputTCELL7:IMUX.IMUX.3
DEC_OUT_ADC2_F1inputTCELL7:IMUX.IMUX.4
DEC_OUT_ADC2_F10inputTCELL7:IMUX.IMUX.13
DEC_OUT_ADC2_F11inputTCELL7:IMUX.IMUX.14
DEC_OUT_ADC2_F12inputTCELL7:IMUX.IMUX.15
DEC_OUT_ADC2_F13inputTCELL7:IMUX.IMUX.16
DEC_OUT_ADC2_F14inputTCELL7:IMUX.IMUX.17
DEC_OUT_ADC2_F15inputTCELL7:IMUX.IMUX.18
DEC_OUT_ADC2_F2inputTCELL7:IMUX.IMUX.5
DEC_OUT_ADC2_F3inputTCELL7:IMUX.IMUX.6
DEC_OUT_ADC2_F4inputTCELL7:IMUX.IMUX.7
DEC_OUT_ADC2_F5inputTCELL7:IMUX.IMUX.8
DEC_OUT_ADC2_F6inputTCELL7:IMUX.IMUX.9
DEC_OUT_ADC2_F7inputTCELL7:IMUX.IMUX.10
DEC_OUT_ADC2_F8inputTCELL7:IMUX.IMUX.11
DEC_OUT_ADC2_F9inputTCELL7:IMUX.IMUX.12
DENinputTCELL7:IMUX.IMUX.0
DI0inputTCELL0:IMUX.IMUX.8
DI1inputTCELL0:IMUX.IMUX.9
DI10inputTCELL0:IMUX.IMUX.18
DI11inputTCELL0:IMUX.IMUX.19
DI12inputTCELL0:IMUX.IMUX.20
DI13inputTCELL0:IMUX.IMUX.21
DI14inputTCELL0:IMUX.IMUX.22
DI15inputTCELL0:IMUX.IMUX.23
DI2inputTCELL0:IMUX.IMUX.10
DI3inputTCELL0:IMUX.IMUX.11
DI4inputTCELL0:IMUX.IMUX.12
DI5inputTCELL0:IMUX.IMUX.13
DI6inputTCELL0:IMUX.IMUX.14
DI7inputTCELL0:IMUX.IMUX.15
DI8inputTCELL0:IMUX.IMUX.16
DI9inputTCELL0:IMUX.IMUX.17
DOUT0outputTCELL6:OUT.0
DOUT1outputTCELL6:OUT.1
DOUT10outputTCELL6:OUT.10
DOUT11outputTCELL6:OUT.11
DOUT12outputTCELL6:OUT.12
DOUT13outputTCELL6:OUT.13
DOUT14outputTCELL6:OUT.14
DOUT15outputTCELL6:OUT.15
DOUT2outputTCELL6:OUT.2
DOUT3outputTCELL6:OUT.3
DOUT4outputTCELL6:OUT.4
DOUT5outputTCELL6:OUT.5
DOUT6outputTCELL6:OUT.6
DOUT7outputTCELL6:OUT.7
DOUT8outputTCELL6:OUT.8
DOUT9outputTCELL6:OUT.9
DRDYoutputTCELL7:OUT.16
DWEinputTCELL7:IMUX.IMUX.1
EOCoutputTCELL7:OUT.24
EOSoutputTCELL7:OUT.25
JTAG_BUSYoutputTCELL6:OUT.16
JTAG_LOCKEDoutputTCELL6:OUT.17
JTAG_MODIFIEDoutputTCELL6:OUT.18
MUX_ADDR0outputTCELL7:OUT.26
MUX_ADDR1outputTCELL7:OUT.27
MUX_ADDR2outputTCELL7:OUT.28
MUX_ADDR3outputTCELL7:OUT.29
MUX_ADDR4outputTCELL7:OUT.30
OToutputTCELL7:OUT.31
RESET_USER_BinputTCELL6:IMUX.CTRL.2
TEST_ADC_CLK_B0inputTCELL6:IMUX.CTRL.3
TEST_ADC_CLK_B1inputTCELL6:IMUX.CTRL.4
TEST_ADC_CLK_B2inputTCELL6:IMUX.CTRL.5
TEST_ADC_CLK_B3inputTCELL6:IMUX.CTRL.6
TEST_ADC_IN0inputTCELL6:IMUX.IMUX.20
TEST_ADC_IN1inputTCELL6:IMUX.IMUX.21
TEST_ADC_IN10inputTCELL6:IMUX.IMUX.30
TEST_ADC_IN11inputTCELL6:IMUX.IMUX.31
TEST_ADC_IN12inputTCELL6:IMUX.IMUX.32
TEST_ADC_IN13inputTCELL6:IMUX.IMUX.33
TEST_ADC_IN14inputTCELL6:IMUX.IMUX.34
TEST_ADC_IN15inputTCELL6:IMUX.IMUX.35
TEST_ADC_IN16inputTCELL6:IMUX.IMUX.36
TEST_ADC_IN17inputTCELL6:IMUX.IMUX.37
TEST_ADC_IN18inputTCELL6:IMUX.IMUX.38
TEST_ADC_IN19inputTCELL6:IMUX.IMUX.39
TEST_ADC_IN2inputTCELL6:IMUX.IMUX.22
TEST_ADC_IN2_0inputTCELL6:IMUX.IMUX.0
TEST_ADC_IN2_1inputTCELL6:IMUX.IMUX.1
TEST_ADC_IN2_10inputTCELL6:IMUX.IMUX.10
TEST_ADC_IN2_11inputTCELL6:IMUX.IMUX.11
TEST_ADC_IN2_12inputTCELL6:IMUX.IMUX.12
TEST_ADC_IN2_13inputTCELL6:IMUX.IMUX.13
TEST_ADC_IN2_14inputTCELL6:IMUX.IMUX.14
TEST_ADC_IN2_15inputTCELL6:IMUX.IMUX.15
TEST_ADC_IN2_16inputTCELL6:IMUX.IMUX.16
TEST_ADC_IN2_17inputTCELL6:IMUX.IMUX.17
TEST_ADC_IN2_18inputTCELL6:IMUX.IMUX.18
TEST_ADC_IN2_19inputTCELL6:IMUX.IMUX.19
TEST_ADC_IN2_2inputTCELL6:IMUX.IMUX.2
TEST_ADC_IN2_3inputTCELL6:IMUX.IMUX.3
TEST_ADC_IN2_4inputTCELL6:IMUX.IMUX.4
TEST_ADC_IN2_5inputTCELL6:IMUX.IMUX.5
TEST_ADC_IN2_6inputTCELL6:IMUX.IMUX.6
TEST_ADC_IN2_7inputTCELL6:IMUX.IMUX.7
TEST_ADC_IN2_8inputTCELL6:IMUX.IMUX.8
TEST_ADC_IN2_9inputTCELL6:IMUX.IMUX.9
TEST_ADC_IN3inputTCELL6:IMUX.IMUX.23
TEST_ADC_IN4inputTCELL6:IMUX.IMUX.24
TEST_ADC_IN5inputTCELL6:IMUX.IMUX.25
TEST_ADC_IN6inputTCELL6:IMUX.IMUX.26
TEST_ADC_IN7inputTCELL6:IMUX.IMUX.27
TEST_ADC_IN8inputTCELL6:IMUX.IMUX.28
TEST_ADC_IN9inputTCELL6:IMUX.IMUX.29
TEST_ADC_OUT0outputTCELL0:OUT.0
TEST_ADC_OUT1outputTCELL0:OUT.1
TEST_ADC_OUT10outputTCELL6:OUT.19
TEST_ADC_OUT11outputTCELL6:OUT.20
TEST_ADC_OUT12outputTCELL6:OUT.21
TEST_ADC_OUT13outputTCELL6:OUT.22
TEST_ADC_OUT14outputTCELL6:OUT.23
TEST_ADC_OUT15outputTCELL6:OUT.24
TEST_ADC_OUT16outputTCELL6:OUT.25
TEST_ADC_OUT17outputTCELL6:OUT.26
TEST_ADC_OUT18outputTCELL6:OUT.27
TEST_ADC_OUT19outputTCELL6:OUT.28
TEST_ADC_OUT2outputTCELL0:OUT.2
TEST_ADC_OUT3outputTCELL0:OUT.3
TEST_ADC_OUT4outputTCELL6:OUT.29
TEST_ADC_OUT5outputTCELL0:OUT.5
TEST_ADC_OUT6outputTCELL0:OUT.6
TEST_ADC_OUT7outputTCELL0:OUT.7
TEST_ADC_OUT8outputTCELL0:OUT.8
TEST_ADC_OUT9outputTCELL0:OUT.9
TEST_CAPTUREinputTCELL7:IMUX.IMUX.19
TEST_DB0outputTCELL0:OUT.10
TEST_DB1outputTCELL0:OUT.11
TEST_DB10outputTCELL0:OUT.20
TEST_DB11outputTCELL0:OUT.21
TEST_DB12outputTCELL0:OUT.22
TEST_DB13outputTCELL0:OUT.23
TEST_DB14outputTCELL0:OUT.24
TEST_DB15outputTCELL0:OUT.25
TEST_DB2outputTCELL0:OUT.12
TEST_DB3outputTCELL0:OUT.13
TEST_DB4outputTCELL0:OUT.14
TEST_DB5outputTCELL0:OUT.15
TEST_DB6outputTCELL0:OUT.16
TEST_DB7outputTCELL0:OUT.17
TEST_DB8outputTCELL0:OUT.18
TEST_DB9outputTCELL0:OUT.19
TEST_DRCKinputTCELL7:IMUX.IMUX.20
TEST_EN_JTAGinputTCELL7:IMUX.IMUX.21
TEST_RSTinputTCELL7:IMUX.IMUX.22
TEST_SCAN_CLK0inputTCELL7:IMUX.IMUX.27
TEST_SCAN_CLK1inputTCELL7:IMUX.IMUX.28
TEST_SCAN_CLK2inputTCELL7:IMUX.IMUX.29
TEST_SCAN_CLK3inputTCELL7:IMUX.IMUX.30
TEST_SCAN_CLK4inputTCELL7:IMUX.IMUX.31
TEST_SCAN_MODE0inputTCELL7:IMUX.IMUX.32
TEST_SCAN_MODE1inputTCELL7:IMUX.IMUX.33
TEST_SCAN_MODE2inputTCELL7:IMUX.IMUX.34
TEST_SCAN_MODE3inputTCELL7:IMUX.IMUX.35
TEST_SCAN_MODE4inputTCELL7:IMUX.IMUX.36
TEST_SCAN_RESETinputTCELL7:IMUX.IMUX.37
TEST_SE0inputTCELL7:IMUX.IMUX.38
TEST_SE1inputTCELL7:IMUX.IMUX.39
TEST_SE2inputTCELL7:IMUX.IMUX.40
TEST_SE3inputTCELL7:IMUX.IMUX.41
TEST_SE4inputTCELL7:IMUX.IMUX.42
TEST_SELinputTCELL7:IMUX.IMUX.23
TEST_SHIFTinputTCELL7:IMUX.IMUX.24
TEST_SI0inputTCELL7:IMUX.IMUX.43
TEST_SI1inputTCELL7:IMUX.IMUX.44
TEST_SI2inputTCELL7:IMUX.IMUX.45
TEST_SI3inputTCELL7:IMUX.IMUX.46
TEST_SI4inputTCELL7:IMUX.IMUX.47
TEST_SO0outputTCELL0:OUT.26
TEST_SO1outputTCELL0:OUT.27
TEST_SO2outputTCELL0:OUT.28
TEST_SO3outputTCELL0:OUT.29
TEST_SO4outputTCELL0:OUT.30
TEST_TDIinputTCELL7:IMUX.IMUX.25
TEST_TDOoutputTCELL0:OUT.31
TEST_UPDATEinputTCELL7:IMUX.IMUX.26

Bel wires

ultrascale AMS bel wires
WirePins
TCELL0:OUT.0SYSMON.TEST_ADC_OUT0
TCELL0:OUT.1SYSMON.TEST_ADC_OUT1
TCELL0:OUT.2SYSMON.TEST_ADC_OUT2
TCELL0:OUT.3SYSMON.TEST_ADC_OUT3
TCELL0:OUT.5SYSMON.TEST_ADC_OUT5
TCELL0:OUT.6SYSMON.TEST_ADC_OUT6
TCELL0:OUT.7SYSMON.TEST_ADC_OUT7
TCELL0:OUT.8SYSMON.TEST_ADC_OUT8
TCELL0:OUT.9SYSMON.TEST_ADC_OUT9
TCELL0:OUT.10SYSMON.TEST_DB0
TCELL0:OUT.11SYSMON.TEST_DB1
TCELL0:OUT.12SYSMON.TEST_DB2
TCELL0:OUT.13SYSMON.TEST_DB3
TCELL0:OUT.14SYSMON.TEST_DB4
TCELL0:OUT.15SYSMON.TEST_DB5
TCELL0:OUT.16SYSMON.TEST_DB6
TCELL0:OUT.17SYSMON.TEST_DB7
TCELL0:OUT.18SYSMON.TEST_DB8
TCELL0:OUT.19SYSMON.TEST_DB9
TCELL0:OUT.20SYSMON.TEST_DB10
TCELL0:OUT.21SYSMON.TEST_DB11
TCELL0:OUT.22SYSMON.TEST_DB12
TCELL0:OUT.23SYSMON.TEST_DB13
TCELL0:OUT.24SYSMON.TEST_DB14
TCELL0:OUT.25SYSMON.TEST_DB15
TCELL0:OUT.26SYSMON.TEST_SO0
TCELL0:OUT.27SYSMON.TEST_SO1
TCELL0:OUT.28SYSMON.TEST_SO2
TCELL0:OUT.29SYSMON.TEST_SO3
TCELL0:OUT.30SYSMON.TEST_SO4
TCELL0:OUT.31SYSMON.TEST_TDO
TCELL0:IMUX.IMUX.0SYSMON.DADDR0
TCELL0:IMUX.IMUX.1SYSMON.DADDR1
TCELL0:IMUX.IMUX.2SYSMON.DADDR2
TCELL0:IMUX.IMUX.3SYSMON.DADDR3
TCELL0:IMUX.IMUX.4SYSMON.DADDR4
TCELL0:IMUX.IMUX.5SYSMON.DADDR5
TCELL0:IMUX.IMUX.6SYSMON.DADDR6
TCELL0:IMUX.IMUX.7SYSMON.DADDR7
TCELL0:IMUX.IMUX.8SYSMON.DI0
TCELL0:IMUX.IMUX.9SYSMON.DI1
TCELL0:IMUX.IMUX.10SYSMON.DI2
TCELL0:IMUX.IMUX.11SYSMON.DI3
TCELL0:IMUX.IMUX.12SYSMON.DI4
TCELL0:IMUX.IMUX.13SYSMON.DI5
TCELL0:IMUX.IMUX.14SYSMON.DI6
TCELL0:IMUX.IMUX.15SYSMON.DI7
TCELL0:IMUX.IMUX.16SYSMON.DI8
TCELL0:IMUX.IMUX.17SYSMON.DI9
TCELL0:IMUX.IMUX.18SYSMON.DI10
TCELL0:IMUX.IMUX.19SYSMON.DI11
TCELL0:IMUX.IMUX.20SYSMON.DI12
TCELL0:IMUX.IMUX.21SYSMON.DI13
TCELL0:IMUX.IMUX.22SYSMON.DI14
TCELL0:IMUX.IMUX.23SYSMON.DI15
TCELL0:IMUX.IMUX.24SYSMON.DATA_READY_ADC1_F
TCELL0:IMUX.IMUX.25SYSMON.DATA_READY_ADC2_F
TCELL0:IMUX.IMUX.26SYSMON.DEC_OUT_ADC1_F0
TCELL0:IMUX.IMUX.27SYSMON.DEC_OUT_ADC1_F1
TCELL0:IMUX.IMUX.28SYSMON.DEC_OUT_ADC1_F2
TCELL0:IMUX.IMUX.29SYSMON.DEC_OUT_ADC1_F3
TCELL0:IMUX.IMUX.30SYSMON.DEC_OUT_ADC1_F4
TCELL0:IMUX.IMUX.31SYSMON.DEC_OUT_ADC1_F5
TCELL0:IMUX.IMUX.32SYSMON.DEC_OUT_ADC1_F6
TCELL0:IMUX.IMUX.33SYSMON.DEC_OUT_ADC1_F7
TCELL0:IMUX.IMUX.34SYSMON.DEC_OUT_ADC1_F8
TCELL0:IMUX.IMUX.35SYSMON.DEC_OUT_ADC1_F9
TCELL0:IMUX.IMUX.36SYSMON.DEC_OUT_ADC1_F10
TCELL0:IMUX.IMUX.37SYSMON.DEC_OUT_ADC1_F11
TCELL0:IMUX.IMUX.38SYSMON.DEC_OUT_ADC1_F12
TCELL0:IMUX.IMUX.39SYSMON.DEC_OUT_ADC1_F13
TCELL0:IMUX.IMUX.40SYSMON.DEC_OUT_ADC1_F14
TCELL0:IMUX.IMUX.41SYSMON.DEC_OUT_ADC1_F15
TCELL6:OUT.0SYSMON.DOUT0
TCELL6:OUT.1SYSMON.DOUT1
TCELL6:OUT.2SYSMON.DOUT2
TCELL6:OUT.3SYSMON.DOUT3
TCELL6:OUT.4SYSMON.DOUT4
TCELL6:OUT.5SYSMON.DOUT5
TCELL6:OUT.6SYSMON.DOUT6
TCELL6:OUT.7SYSMON.DOUT7
TCELL6:OUT.8SYSMON.DOUT8
TCELL6:OUT.9SYSMON.DOUT9
TCELL6:OUT.10SYSMON.DOUT10
TCELL6:OUT.11SYSMON.DOUT11
TCELL6:OUT.12SYSMON.DOUT12
TCELL6:OUT.13SYSMON.DOUT13
TCELL6:OUT.14SYSMON.DOUT14
TCELL6:OUT.15SYSMON.DOUT15
TCELL6:OUT.16SYSMON.JTAG_BUSY
TCELL6:OUT.17SYSMON.JTAG_LOCKED
TCELL6:OUT.18SYSMON.JTAG_MODIFIED
TCELL6:OUT.19SYSMON.TEST_ADC_OUT10
TCELL6:OUT.20SYSMON.TEST_ADC_OUT11
TCELL6:OUT.21SYSMON.TEST_ADC_OUT12
TCELL6:OUT.22SYSMON.TEST_ADC_OUT13
TCELL6:OUT.23SYSMON.TEST_ADC_OUT14
TCELL6:OUT.24SYSMON.TEST_ADC_OUT15
TCELL6:OUT.25SYSMON.TEST_ADC_OUT16
TCELL6:OUT.26SYSMON.TEST_ADC_OUT17
TCELL6:OUT.27SYSMON.TEST_ADC_OUT18
TCELL6:OUT.28SYSMON.TEST_ADC_OUT19
TCELL6:OUT.29SYSMON.TEST_ADC_OUT4
TCELL6:IMUX.CTRL.0SYSMON.DCLK_B
TCELL6:IMUX.CTRL.1SYSMON.CONVST_CLK_B
TCELL6:IMUX.CTRL.2SYSMON.RESET_USER_B
TCELL6:IMUX.CTRL.3SYSMON.TEST_ADC_CLK_B0
TCELL6:IMUX.CTRL.4SYSMON.TEST_ADC_CLK_B1
TCELL6:IMUX.CTRL.5SYSMON.TEST_ADC_CLK_B2
TCELL6:IMUX.CTRL.6SYSMON.TEST_ADC_CLK_B3
TCELL6:IMUX.IMUX.0SYSMON.TEST_ADC_IN2_0
TCELL6:IMUX.IMUX.1SYSMON.TEST_ADC_IN2_1
TCELL6:IMUX.IMUX.2SYSMON.TEST_ADC_IN2_2
TCELL6:IMUX.IMUX.3SYSMON.TEST_ADC_IN2_3
TCELL6:IMUX.IMUX.4SYSMON.TEST_ADC_IN2_4
TCELL6:IMUX.IMUX.5SYSMON.TEST_ADC_IN2_5
TCELL6:IMUX.IMUX.6SYSMON.TEST_ADC_IN2_6
TCELL6:IMUX.IMUX.7SYSMON.TEST_ADC_IN2_7
TCELL6:IMUX.IMUX.8SYSMON.TEST_ADC_IN2_8
TCELL6:IMUX.IMUX.9SYSMON.TEST_ADC_IN2_9
TCELL6:IMUX.IMUX.10SYSMON.TEST_ADC_IN2_10
TCELL6:IMUX.IMUX.11SYSMON.TEST_ADC_IN2_11
TCELL6:IMUX.IMUX.12SYSMON.TEST_ADC_IN2_12
TCELL6:IMUX.IMUX.13SYSMON.TEST_ADC_IN2_13
TCELL6:IMUX.IMUX.14SYSMON.TEST_ADC_IN2_14
TCELL6:IMUX.IMUX.15SYSMON.TEST_ADC_IN2_15
TCELL6:IMUX.IMUX.16SYSMON.TEST_ADC_IN2_16
TCELL6:IMUX.IMUX.17SYSMON.TEST_ADC_IN2_17
TCELL6:IMUX.IMUX.18SYSMON.TEST_ADC_IN2_18
TCELL6:IMUX.IMUX.19SYSMON.TEST_ADC_IN2_19
TCELL6:IMUX.IMUX.20SYSMON.TEST_ADC_IN0
TCELL6:IMUX.IMUX.21SYSMON.TEST_ADC_IN1
TCELL6:IMUX.IMUX.22SYSMON.TEST_ADC_IN2
TCELL6:IMUX.IMUX.23SYSMON.TEST_ADC_IN3
TCELL6:IMUX.IMUX.24SYSMON.TEST_ADC_IN4
TCELL6:IMUX.IMUX.25SYSMON.TEST_ADC_IN5
TCELL6:IMUX.IMUX.26SYSMON.TEST_ADC_IN6
TCELL6:IMUX.IMUX.27SYSMON.TEST_ADC_IN7
TCELL6:IMUX.IMUX.28SYSMON.TEST_ADC_IN8
TCELL6:IMUX.IMUX.29SYSMON.TEST_ADC_IN9
TCELL6:IMUX.IMUX.30SYSMON.TEST_ADC_IN10
TCELL6:IMUX.IMUX.31SYSMON.TEST_ADC_IN11
TCELL6:IMUX.IMUX.32SYSMON.TEST_ADC_IN12
TCELL6:IMUX.IMUX.33SYSMON.TEST_ADC_IN13
TCELL6:IMUX.IMUX.34SYSMON.TEST_ADC_IN14
TCELL6:IMUX.IMUX.35SYSMON.TEST_ADC_IN15
TCELL6:IMUX.IMUX.36SYSMON.TEST_ADC_IN16
TCELL6:IMUX.IMUX.37SYSMON.TEST_ADC_IN17
TCELL6:IMUX.IMUX.38SYSMON.TEST_ADC_IN18
TCELL6:IMUX.IMUX.39SYSMON.TEST_ADC_IN19
TCELL7:OUT.0SYSMON.ALM0
TCELL7:OUT.1SYSMON.ALM1
TCELL7:OUT.2SYSMON.ALM2
TCELL7:OUT.3SYSMON.ALM3
TCELL7:OUT.4SYSMON.ALM4
TCELL7:OUT.5SYSMON.ALM5
TCELL7:OUT.6SYSMON.ALM6
TCELL7:OUT.7SYSMON.ALM7
TCELL7:OUT.8SYSMON.ALM8
TCELL7:OUT.9SYSMON.ALM9
TCELL7:OUT.10SYSMON.ALM10
TCELL7:OUT.11SYSMON.ALM11
TCELL7:OUT.12SYSMON.ALM12
TCELL7:OUT.13SYSMON.ALM13
TCELL7:OUT.14SYSMON.ALM14
TCELL7:OUT.15SYSMON.ALM15
TCELL7:OUT.16SYSMON.DRDY
TCELL7:OUT.17SYSMON.BUSY
TCELL7:OUT.18SYSMON.CHANNEL0
TCELL7:OUT.19SYSMON.CHANNEL1
TCELL7:OUT.20SYSMON.CHANNEL2
TCELL7:OUT.21SYSMON.CHANNEL3
TCELL7:OUT.22SYSMON.CHANNEL4
TCELL7:OUT.23SYSMON.CHANNEL5
TCELL7:OUT.24SYSMON.EOC
TCELL7:OUT.25SYSMON.EOS
TCELL7:OUT.26SYSMON.MUX_ADDR0
TCELL7:OUT.27SYSMON.MUX_ADDR1
TCELL7:OUT.28SYSMON.MUX_ADDR2
TCELL7:OUT.29SYSMON.MUX_ADDR3
TCELL7:OUT.30SYSMON.MUX_ADDR4
TCELL7:OUT.31SYSMON.OT
TCELL7:IMUX.IMUX.0SYSMON.DEN
TCELL7:IMUX.IMUX.1SYSMON.DWE
TCELL7:IMUX.IMUX.2SYSMON.CONVST
TCELL7:IMUX.IMUX.3SYSMON.DEC_OUT_ADC2_F0
TCELL7:IMUX.IMUX.4SYSMON.DEC_OUT_ADC2_F1
TCELL7:IMUX.IMUX.5SYSMON.DEC_OUT_ADC2_F2
TCELL7:IMUX.IMUX.6SYSMON.DEC_OUT_ADC2_F3
TCELL7:IMUX.IMUX.7SYSMON.DEC_OUT_ADC2_F4
TCELL7:IMUX.IMUX.8SYSMON.DEC_OUT_ADC2_F5
TCELL7:IMUX.IMUX.9SYSMON.DEC_OUT_ADC2_F6
TCELL7:IMUX.IMUX.10SYSMON.DEC_OUT_ADC2_F7
TCELL7:IMUX.IMUX.11SYSMON.DEC_OUT_ADC2_F8
TCELL7:IMUX.IMUX.12SYSMON.DEC_OUT_ADC2_F9
TCELL7:IMUX.IMUX.13SYSMON.DEC_OUT_ADC2_F10
TCELL7:IMUX.IMUX.14SYSMON.DEC_OUT_ADC2_F11
TCELL7:IMUX.IMUX.15SYSMON.DEC_OUT_ADC2_F12
TCELL7:IMUX.IMUX.16SYSMON.DEC_OUT_ADC2_F13
TCELL7:IMUX.IMUX.17SYSMON.DEC_OUT_ADC2_F14
TCELL7:IMUX.IMUX.18SYSMON.DEC_OUT_ADC2_F15
TCELL7:IMUX.IMUX.19SYSMON.TEST_CAPTURE
TCELL7:IMUX.IMUX.20SYSMON.TEST_DRCK
TCELL7:IMUX.IMUX.21SYSMON.TEST_EN_JTAG
TCELL7:IMUX.IMUX.22SYSMON.TEST_RST
TCELL7:IMUX.IMUX.23SYSMON.TEST_SEL
TCELL7:IMUX.IMUX.24SYSMON.TEST_SHIFT
TCELL7:IMUX.IMUX.25SYSMON.TEST_TDI
TCELL7:IMUX.IMUX.26SYSMON.TEST_UPDATE
TCELL7:IMUX.IMUX.27SYSMON.TEST_SCAN_CLK0
TCELL7:IMUX.IMUX.28SYSMON.TEST_SCAN_CLK1
TCELL7:IMUX.IMUX.29SYSMON.TEST_SCAN_CLK2
TCELL7:IMUX.IMUX.30SYSMON.TEST_SCAN_CLK3
TCELL7:IMUX.IMUX.31SYSMON.TEST_SCAN_CLK4
TCELL7:IMUX.IMUX.32SYSMON.TEST_SCAN_MODE0
TCELL7:IMUX.IMUX.33SYSMON.TEST_SCAN_MODE1
TCELL7:IMUX.IMUX.34SYSMON.TEST_SCAN_MODE2
TCELL7:IMUX.IMUX.35SYSMON.TEST_SCAN_MODE3
TCELL7:IMUX.IMUX.36SYSMON.TEST_SCAN_MODE4
TCELL7:IMUX.IMUX.37SYSMON.TEST_SCAN_RESET
TCELL7:IMUX.IMUX.38SYSMON.TEST_SE0
TCELL7:IMUX.IMUX.39SYSMON.TEST_SE1
TCELL7:IMUX.IMUX.40SYSMON.TEST_SE2
TCELL7:IMUX.IMUX.41SYSMON.TEST_SE3
TCELL7:IMUX.IMUX.42SYSMON.TEST_SE4
TCELL7:IMUX.IMUX.43SYSMON.TEST_SI0
TCELL7:IMUX.IMUX.44SYSMON.TEST_SI1
TCELL7:IMUX.IMUX.45SYSMON.TEST_SI2
TCELL7:IMUX.IMUX.46SYSMON.TEST_SI3
TCELL7:IMUX.IMUX.47SYSMON.TEST_SI4