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HPIO/HRIO XIPHY

Tile XIPHY

Cells: 60

Bel BUFCE_ROW_CMT0

ultrascale XIPHY bel BUFCE_ROW_CMT0
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.17.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT1

ultrascale XIPHY bel BUFCE_ROW_CMT1
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.18.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT2

ultrascale XIPHY bel BUFCE_ROW_CMT2
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.19.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT3

ultrascale XIPHY bel BUFCE_ROW_CMT3
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.20.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT4

ultrascale XIPHY bel BUFCE_ROW_CMT4
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.21.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT5

ultrascale XIPHY bel BUFCE_ROW_CMT5
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.22.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT6

ultrascale XIPHY bel BUFCE_ROW_CMT6
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.23.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT7

ultrascale XIPHY bel BUFCE_ROW_CMT7
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.24.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT8

ultrascale XIPHY bel BUFCE_ROW_CMT8
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.25.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT9

ultrascale XIPHY bel BUFCE_ROW_CMT9
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.26.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT10

ultrascale XIPHY bel BUFCE_ROW_CMT10
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.27.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT11

ultrascale XIPHY bel BUFCE_ROW_CMT11
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.28.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT12

ultrascale XIPHY bel BUFCE_ROW_CMT12
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.29.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT13

ultrascale XIPHY bel BUFCE_ROW_CMT13
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.30.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT14

ultrascale XIPHY bel BUFCE_ROW_CMT14
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.31.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT15

ultrascale XIPHY bel BUFCE_ROW_CMT15
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.32.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT16

ultrascale XIPHY bel BUFCE_ROW_CMT16
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.33.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT17

ultrascale XIPHY bel BUFCE_ROW_CMT17
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.34.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT18

ultrascale XIPHY bel BUFCE_ROW_CMT18
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.35.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT19

ultrascale XIPHY bel BUFCE_ROW_CMT19
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.36.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT20

ultrascale XIPHY bel BUFCE_ROW_CMT20
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.37.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT21

ultrascale XIPHY bel BUFCE_ROW_CMT21
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.38.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT22

ultrascale XIPHY bel BUFCE_ROW_CMT22
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.39.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT23

ultrascale XIPHY bel BUFCE_ROW_CMT23
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.40.DELAY
OPT_DELAY_TEST0inputTCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1inputTCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2inputTCELL30:RCLK.IMUX.8

Bel GCLK_TEST_BUF_CMT0

ultrascale XIPHY bel GCLK_TEST_BUF_CMT0
PinDirectionWires

Bel GCLK_TEST_BUF_CMT1

ultrascale XIPHY bel GCLK_TEST_BUF_CMT1
PinDirectionWires

Bel GCLK_TEST_BUF_CMT2

ultrascale XIPHY bel GCLK_TEST_BUF_CMT2
PinDirectionWires

Bel GCLK_TEST_BUF_CMT3

ultrascale XIPHY bel GCLK_TEST_BUF_CMT3
PinDirectionWires

Bel GCLK_TEST_BUF_CMT4

ultrascale XIPHY bel GCLK_TEST_BUF_CMT4
PinDirectionWires

Bel GCLK_TEST_BUF_CMT5

ultrascale XIPHY bel GCLK_TEST_BUF_CMT5
PinDirectionWires

Bel GCLK_TEST_BUF_CMT6

ultrascale XIPHY bel GCLK_TEST_BUF_CMT6
PinDirectionWires

Bel GCLK_TEST_BUF_CMT7

ultrascale XIPHY bel GCLK_TEST_BUF_CMT7
PinDirectionWires

Bel GCLK_TEST_BUF_CMT8

ultrascale XIPHY bel GCLK_TEST_BUF_CMT8
PinDirectionWires

Bel GCLK_TEST_BUF_CMT9

ultrascale XIPHY bel GCLK_TEST_BUF_CMT9
PinDirectionWires

Bel GCLK_TEST_BUF_CMT10

ultrascale XIPHY bel GCLK_TEST_BUF_CMT10
PinDirectionWires

Bel GCLK_TEST_BUF_CMT11

ultrascale XIPHY bel GCLK_TEST_BUF_CMT11
PinDirectionWires

Bel GCLK_TEST_BUF_CMT12

ultrascale XIPHY bel GCLK_TEST_BUF_CMT12
PinDirectionWires

Bel GCLK_TEST_BUF_CMT13

ultrascale XIPHY bel GCLK_TEST_BUF_CMT13
PinDirectionWires

Bel GCLK_TEST_BUF_CMT14

ultrascale XIPHY bel GCLK_TEST_BUF_CMT14
PinDirectionWires

Bel GCLK_TEST_BUF_CMT15

ultrascale XIPHY bel GCLK_TEST_BUF_CMT15
PinDirectionWires

Bel GCLK_TEST_BUF_CMT16

ultrascale XIPHY bel GCLK_TEST_BUF_CMT16
PinDirectionWires

Bel GCLK_TEST_BUF_CMT17

ultrascale XIPHY bel GCLK_TEST_BUF_CMT17
PinDirectionWires

Bel GCLK_TEST_BUF_CMT18

ultrascale XIPHY bel GCLK_TEST_BUF_CMT18
PinDirectionWires

Bel GCLK_TEST_BUF_CMT19

ultrascale XIPHY bel GCLK_TEST_BUF_CMT19
PinDirectionWires

Bel GCLK_TEST_BUF_CMT20

ultrascale XIPHY bel GCLK_TEST_BUF_CMT20
PinDirectionWires

Bel GCLK_TEST_BUF_CMT21

ultrascale XIPHY bel GCLK_TEST_BUF_CMT21
PinDirectionWires

Bel GCLK_TEST_BUF_CMT22

ultrascale XIPHY bel GCLK_TEST_BUF_CMT22
PinDirectionWires

Bel GCLK_TEST_BUF_CMT23

ultrascale XIPHY bel GCLK_TEST_BUF_CMT23
PinDirectionWires

Bel BUFGCE0

ultrascale XIPHY bel BUFGCE0
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.31.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.24.DELAY

Bel BUFGCE1

ultrascale XIPHY bel BUFGCE1
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.32.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.25.DELAY

Bel BUFGCE2

ultrascale XIPHY bel BUFGCE2
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.33.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.26.DELAY

Bel BUFGCE3

ultrascale XIPHY bel BUFGCE3
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.34.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.27.DELAY

Bel BUFGCE4

ultrascale XIPHY bel BUFGCE4
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.35.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.28.DELAY

Bel BUFGCE5

ultrascale XIPHY bel BUFGCE5
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.36.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.29.DELAY

Bel BUFGCE6

ultrascale XIPHY bel BUFGCE6
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.37.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.30.DELAY

Bel BUFGCE7

ultrascale XIPHY bel BUFGCE7
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.38.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.31.DELAY

Bel BUFGCE8

ultrascale XIPHY bel BUFGCE8
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.39.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.32.DELAY

Bel BUFGCE9

ultrascale XIPHY bel BUFGCE9
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.40.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.33.DELAY

Bel BUFGCE10

ultrascale XIPHY bel BUFGCE10
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.41.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.34.DELAY

Bel BUFGCE11

ultrascale XIPHY bel BUFGCE11
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.42.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.35.DELAY

Bel BUFGCE12

ultrascale XIPHY bel BUFGCE12
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.43.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.36.DELAY

Bel BUFGCE13

ultrascale XIPHY bel BUFGCE13
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.44.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.37.DELAY

Bel BUFGCE14

ultrascale XIPHY bel BUFGCE14
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.45.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.38.DELAY

Bel BUFGCE15

ultrascale XIPHY bel BUFGCE15
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.46.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.39.DELAY

Bel BUFGCE16

ultrascale XIPHY bel BUFGCE16
PinDirectionWires
CE_PRE_OPTINVinputTCELL30:IMUX.IMUX.47.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.40.DELAY

Bel BUFGCE17

ultrascale XIPHY bel BUFGCE17
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.17.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.41.DELAY

Bel BUFGCE18

ultrascale XIPHY bel BUFGCE18
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.18.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.42.DELAY

Bel BUFGCE19

ultrascale XIPHY bel BUFGCE19
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.19.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.43.DELAY

Bel BUFGCE20

ultrascale XIPHY bel BUFGCE20
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.20.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.44.DELAY

Bel BUFGCE21

ultrascale XIPHY bel BUFGCE21
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.21.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.45.DELAY

Bel BUFGCE22

ultrascale XIPHY bel BUFGCE22
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.22.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.46.DELAY

Bel BUFGCE23

ultrascale XIPHY bel BUFGCE23
PinDirectionWires
CE_PRE_OPTINVinputTCELL31:IMUX.IMUX.23.DELAY
CLK_IN_CKINTinputTCELL31:IMUX.IMUX.47.DELAY

Bel BUFGCTRL0

ultrascale XIPHY bel BUFGCTRL0
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.23.DELAY
CE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.46.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.38.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.30.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.22.DELAY
SEL1_PRE_OPTINVinputTCELL28:IMUX.IMUX.45.DELAY

Bel BUFGCTRL1

ultrascale XIPHY bel BUFGCTRL1
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.24.DELAY
CE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.47.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.39.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.31.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.23.DELAY
SEL1_PRE_OPTINVinputTCELL28:IMUX.IMUX.46.DELAY

Bel BUFGCTRL2

ultrascale XIPHY bel BUFGCTRL2
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.25.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.17.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.40.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.32.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.24.DELAY
SEL1_PRE_OPTINVinputTCELL28:IMUX.IMUX.47.DELAY

Bel BUFGCTRL3

ultrascale XIPHY bel BUFGCTRL3
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.26.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.18.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.41.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.33.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.25.DELAY
SEL1_PRE_OPTINVinputTCELL29:IMUX.IMUX.17.DELAY

Bel BUFGCTRL4

ultrascale XIPHY bel BUFGCTRL4
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.27.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.19.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.42.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.34.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.26.DELAY
SEL1_PRE_OPTINVinputTCELL29:IMUX.IMUX.18.DELAY

Bel BUFGCTRL5

ultrascale XIPHY bel BUFGCTRL5
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.28.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.20.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.43.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.35.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.27.DELAY
SEL1_PRE_OPTINVinputTCELL29:IMUX.IMUX.19.DELAY

Bel BUFGCTRL6

ultrascale XIPHY bel BUFGCTRL6
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.29.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.21.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.44.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.36.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.28.DELAY
SEL1_PRE_OPTINVinputTCELL29:IMUX.IMUX.20.DELAY

Bel BUFGCTRL7

ultrascale XIPHY bel BUFGCTRL7
PinDirectionWires
CE0_PRE_OPTINVinputTCELL30:IMUX.IMUX.30.DELAY
CE1_PRE_OPTINVinputTCELL30:IMUX.IMUX.22.DELAY
IGNORE0_PRE_OPTINVinputTCELL29:IMUX.IMUX.45.DELAY
IGNORE1_PRE_OPTINVinputTCELL29:IMUX.IMUX.37.DELAY
SEL0_PRE_OPTINVinputTCELL29:IMUX.IMUX.29.DELAY
SEL1_PRE_OPTINVinputTCELL29:IMUX.IMUX.21.DELAY

Bel BUFGCE_DIV0

ultrascale XIPHY bel BUFGCE_DIV0
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.41.DELAY
RST_PRE_OPTINVinputTCELL28:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV1

ultrascale XIPHY bel BUFGCE_DIV1
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.42.DELAY
RST_PRE_OPTINVinputTCELL29:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV2

ultrascale XIPHY bel BUFGCE_DIV2
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.43.DELAY
RST_PRE_OPTINVinputTCELL30:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV3

ultrascale XIPHY bel BUFGCE_DIV3
PinDirectionWires
CE_PRE_OPTINVinputTCELL28:IMUX.IMUX.44.DELAY
RST_PRE_OPTINVinputTCELL31:IMUX.IMUX.0.DELAY

Bel PLL0

ultrascale XIPHY bel PLL0
PinDirectionWires
CLKOUTPHY_ENinputTCELL1:IMUX.IMUX.0.DELAY
DADDR0inputTCELL9:IMUX.BYP.0
DADDR1inputTCELL9:IMUX.BYP.1
DADDR2inputTCELL9:IMUX.BYP.2
DADDR3inputTCELL9:IMUX.BYP.3
DADDR4inputTCELL8:IMUX.BYP.0
DADDR5inputTCELL8:IMUX.BYP.1
DADDR6inputTCELL8:IMUX.BYP.2
DCLK_BinputTCELL11:IMUX.CTRL.0
DENinputTCELL11:IMUX.IMUX.0.DELAY
DI0inputTCELL13:IMUX.BYP.0
DI1inputTCELL13:IMUX.BYP.1
DI10inputTCELL11:IMUX.BYP.2
DI11inputTCELL11:IMUX.BYP.3
DI12inputTCELL10:IMUX.BYP.0
DI13inputTCELL10:IMUX.BYP.1
DI14inputTCELL10:IMUX.BYP.2
DI15inputTCELL10:IMUX.BYP.3
DI2inputTCELL13:IMUX.BYP.2
DI3inputTCELL13:IMUX.BYP.3
DI4inputTCELL12:IMUX.BYP.0
DI5inputTCELL12:IMUX.BYP.1
DI6inputTCELL12:IMUX.BYP.2
DI7inputTCELL12:IMUX.BYP.3
DI8inputTCELL11:IMUX.BYP.0
DI9inputTCELL11:IMUX.BYP.1
DOUT0outputTCELL12:OUT.0.TMIN
DOUT1outputTCELL12:OUT.1.TMIN
DOUT10outputTCELL10:OUT.2.TMIN
DOUT11outputTCELL10:OUT.3.TMIN
DOUT12outputTCELL9:OUT.0.TMIN
DOUT13outputTCELL9:OUT.1.TMIN
DOUT14outputTCELL9:OUT.2.TMIN
DOUT15outputTCELL9:OUT.3.TMIN
DOUT2outputTCELL12:OUT.2.TMIN
DOUT3outputTCELL12:OUT.3.TMIN
DOUT4outputTCELL11:OUT.0.TMIN
DOUT5outputTCELL11:OUT.1.TMIN
DOUT6outputTCELL11:OUT.2.TMIN
DOUT7outputTCELL11:OUT.3.TMIN
DOUT8outputTCELL10:OUT.0.TMIN
DOUT9outputTCELL10:OUT.1.TMIN
DRDYoutputTCELL13:OUT.0.TMIN
DWEinputTCELL10:IMUX.IMUX.0.DELAY
LOCKEDoutputTCELL13:OUT.1.TMIN
PWRDWNinputTCELL12:IMUX.IMUX.0.DELAY
RSTinputTCELL13:IMUX.IMUX.0.DELAY
SCANCLK_BinputTCELL13:IMUX.CTRL.0
SCANENBinputTCELL7:IMUX.IMUX.0.DELAY
SCANINinputTCELL8:IMUX.IMUX.0.DELAY
SCANMODEBinputTCELL6:IMUX.IMUX.0.DELAY
SCANOUToutputTCELL13:OUT.3.TMIN
TESTIN0inputTCELL7:IMUX.BYP.0
TESTIN1inputTCELL7:IMUX.BYP.1
TESTIN10inputTCELL5:IMUX.BYP.2
TESTIN11inputTCELL5:IMUX.BYP.3
TESTIN12inputTCELL4:IMUX.BYP.0
TESTIN13inputTCELL4:IMUX.BYP.1
TESTIN14inputTCELL4:IMUX.BYP.2
TESTIN15inputTCELL4:IMUX.BYP.3
TESTIN16inputTCELL3:IMUX.BYP.0
TESTIN17inputTCELL3:IMUX.BYP.1
TESTIN18inputTCELL3:IMUX.BYP.2
TESTIN19inputTCELL3:IMUX.BYP.3
TESTIN2inputTCELL7:IMUX.BYP.2
TESTIN20inputTCELL2:IMUX.BYP.0
TESTIN21inputTCELL2:IMUX.BYP.1
TESTIN22inputTCELL2:IMUX.BYP.2
TESTIN23inputTCELL2:IMUX.BYP.3
TESTIN24inputTCELL1:IMUX.BYP.0
TESTIN25inputTCELL1:IMUX.BYP.1
TESTIN26inputTCELL1:IMUX.BYP.2
TESTIN27inputTCELL1:IMUX.BYP.3
TESTIN28inputTCELL0:IMUX.BYP.0
TESTIN29inputTCELL0:IMUX.BYP.1
TESTIN3inputTCELL7:IMUX.BYP.3
TESTIN30inputTCELL0:IMUX.BYP.2
TESTIN31inputTCELL0:IMUX.BYP.3
TESTIN4inputTCELL6:IMUX.BYP.0
TESTIN5inputTCELL6:IMUX.BYP.1
TESTIN6inputTCELL6:IMUX.BYP.2
TESTIN7inputTCELL6:IMUX.BYP.3
TESTIN8inputTCELL5:IMUX.BYP.0
TESTIN9inputTCELL5:IMUX.BYP.1
TESTOUT0outputTCELL8:OUT.0.TMIN
TESTOUT1outputTCELL8:OUT.1.TMIN
TESTOUT10outputTCELL6:OUT.2.TMIN
TESTOUT11outputTCELL6:OUT.3.TMIN
TESTOUT12outputTCELL5:OUT.0.TMIN
TESTOUT13outputTCELL5:OUT.1.TMIN
TESTOUT14outputTCELL5:OUT.2.TMIN
TESTOUT15outputTCELL5:OUT.3.TMIN
TESTOUT16outputTCELL4:OUT.0.TMIN
TESTOUT17outputTCELL4:OUT.1.TMIN
TESTOUT18outputTCELL4:OUT.2.TMIN
TESTOUT19outputTCELL4:OUT.3.TMIN
TESTOUT2outputTCELL8:OUT.2.TMIN
TESTOUT20outputTCELL3:OUT.0.TMIN
TESTOUT21outputTCELL3:OUT.1.TMIN
TESTOUT22outputTCELL3:OUT.2.TMIN
TESTOUT23outputTCELL3:OUT.3.TMIN
TESTOUT24outputTCELL2:OUT.0.TMIN
TESTOUT25outputTCELL2:OUT.1.TMIN
TESTOUT26outputTCELL2:OUT.2.TMIN
TESTOUT27outputTCELL2:OUT.3.TMIN
TESTOUT28outputTCELL1:OUT.0.TMIN
TESTOUT29outputTCELL1:OUT.1.TMIN
TESTOUT3outputTCELL8:OUT.3.TMIN
TESTOUT30outputTCELL1:OUT.2.TMIN
TESTOUT31outputTCELL1:OUT.3.TMIN
TESTOUT32outputTCELL0:OUT.0.TMIN
TESTOUT33outputTCELL0:OUT.1.TMIN
TESTOUT34outputTCELL0:OUT.2.TMIN
TESTOUT35outputTCELL0:OUT.3.TMIN
TESTOUT36outputTCELL13:OUT.2.TMIN
TESTOUT4outputTCELL7:OUT.0.TMIN
TESTOUT5outputTCELL7:OUT.1.TMIN
TESTOUT6outputTCELL7:OUT.2.TMIN
TESTOUT7outputTCELL7:OUT.3.TMIN
TESTOUT8outputTCELL6:OUT.0.TMIN
TESTOUT9outputTCELL6:OUT.1.TMIN

Bel PLL1

ultrascale XIPHY bel PLL1
PinDirectionWires
CLKOUTPHY_ENinputTCELL15:IMUX.IMUX.0.DELAY
DADDR0inputTCELL23:IMUX.BYP.0
DADDR1inputTCELL23:IMUX.BYP.1
DADDR2inputTCELL23:IMUX.BYP.2
DADDR3inputTCELL23:IMUX.BYP.3
DADDR4inputTCELL22:IMUX.BYP.0
DADDR5inputTCELL22:IMUX.BYP.1
DADDR6inputTCELL22:IMUX.BYP.2
DCLK_BinputTCELL25:IMUX.CTRL.0
DENinputTCELL25:IMUX.IMUX.0.DELAY
DI0inputTCELL27:IMUX.BYP.0
DI1inputTCELL27:IMUX.BYP.1
DI10inputTCELL25:IMUX.BYP.2
DI11inputTCELL25:IMUX.BYP.3
DI12inputTCELL24:IMUX.BYP.0
DI13inputTCELL24:IMUX.BYP.1
DI14inputTCELL24:IMUX.BYP.2
DI15inputTCELL24:IMUX.BYP.3
DI2inputTCELL27:IMUX.BYP.2
DI3inputTCELL27:IMUX.BYP.3
DI4inputTCELL26:IMUX.BYP.0
DI5inputTCELL26:IMUX.BYP.1
DI6inputTCELL26:IMUX.BYP.2
DI7inputTCELL26:IMUX.BYP.3
DI8inputTCELL25:IMUX.BYP.0
DI9inputTCELL25:IMUX.BYP.1
DOUT0outputTCELL26:OUT.0.TMIN
DOUT1outputTCELL26:OUT.1.TMIN
DOUT10outputTCELL24:OUT.2.TMIN
DOUT11outputTCELL24:OUT.3.TMIN
DOUT12outputTCELL23:OUT.0.TMIN
DOUT13outputTCELL23:OUT.1.TMIN
DOUT14outputTCELL23:OUT.2.TMIN
DOUT15outputTCELL23:OUT.3.TMIN
DOUT2outputTCELL26:OUT.2.TMIN
DOUT3outputTCELL26:OUT.3.TMIN
DOUT4outputTCELL25:OUT.0.TMIN
DOUT5outputTCELL25:OUT.1.TMIN
DOUT6outputTCELL25:OUT.2.TMIN
DOUT7outputTCELL25:OUT.3.TMIN
DOUT8outputTCELL24:OUT.0.TMIN
DOUT9outputTCELL24:OUT.1.TMIN
DRDYoutputTCELL27:OUT.0.TMIN
DWEinputTCELL24:IMUX.IMUX.0.DELAY
LOCKEDoutputTCELL27:OUT.1.TMIN
PWRDWNinputTCELL26:IMUX.IMUX.0.DELAY
RSTinputTCELL27:IMUX.IMUX.0.DELAY
SCANCLK_BinputTCELL27:IMUX.CTRL.0
SCANENBinputTCELL21:IMUX.IMUX.0.DELAY
SCANINinputTCELL22:IMUX.IMUX.0.DELAY
SCANMODEBinputTCELL20:IMUX.IMUX.0.DELAY
SCANOUToutputTCELL27:OUT.3.TMIN
TESTIN0inputTCELL21:IMUX.BYP.0
TESTIN1inputTCELL21:IMUX.BYP.1
TESTIN10inputTCELL19:IMUX.BYP.2
TESTIN11inputTCELL19:IMUX.BYP.3
TESTIN12inputTCELL18:IMUX.BYP.0
TESTIN13inputTCELL18:IMUX.BYP.1
TESTIN14inputTCELL18:IMUX.BYP.2
TESTIN15inputTCELL18:IMUX.BYP.3
TESTIN16inputTCELL17:IMUX.BYP.0
TESTIN17inputTCELL17:IMUX.BYP.1
TESTIN18inputTCELL17:IMUX.BYP.2
TESTIN19inputTCELL17:IMUX.BYP.3
TESTIN2inputTCELL21:IMUX.BYP.2
TESTIN20inputTCELL16:IMUX.BYP.0
TESTIN21inputTCELL16:IMUX.BYP.1
TESTIN22inputTCELL16:IMUX.BYP.2
TESTIN23inputTCELL16:IMUX.BYP.3
TESTIN24inputTCELL15:IMUX.BYP.0
TESTIN25inputTCELL15:IMUX.BYP.1
TESTIN26inputTCELL15:IMUX.BYP.2
TESTIN27inputTCELL15:IMUX.BYP.3
TESTIN28inputTCELL14:IMUX.BYP.0
TESTIN29inputTCELL14:IMUX.BYP.1
TESTIN3inputTCELL21:IMUX.BYP.3
TESTIN30inputTCELL14:IMUX.BYP.2
TESTIN31inputTCELL14:IMUX.BYP.3
TESTIN4inputTCELL20:IMUX.BYP.0
TESTIN5inputTCELL20:IMUX.BYP.1
TESTIN6inputTCELL20:IMUX.BYP.2
TESTIN7inputTCELL20:IMUX.BYP.3
TESTIN8inputTCELL19:IMUX.BYP.0
TESTIN9inputTCELL19:IMUX.BYP.1
TESTOUT0outputTCELL22:OUT.0.TMIN
TESTOUT1outputTCELL22:OUT.1.TMIN
TESTOUT10outputTCELL20:OUT.2.TMIN
TESTOUT11outputTCELL20:OUT.3.TMIN
TESTOUT12outputTCELL19:OUT.0.TMIN
TESTOUT13outputTCELL19:OUT.1.TMIN
TESTOUT14outputTCELL19:OUT.2.TMIN
TESTOUT15outputTCELL19:OUT.3.TMIN
TESTOUT16outputTCELL18:OUT.0.TMIN
TESTOUT17outputTCELL18:OUT.1.TMIN
TESTOUT18outputTCELL18:OUT.2.TMIN
TESTOUT19outputTCELL18:OUT.3.TMIN
TESTOUT2outputTCELL22:OUT.2.TMIN
TESTOUT20outputTCELL17:OUT.0.TMIN
TESTOUT21outputTCELL17:OUT.1.TMIN
TESTOUT22outputTCELL17:OUT.2.TMIN
TESTOUT23outputTCELL17:OUT.3.TMIN
TESTOUT24outputTCELL16:OUT.0.TMIN
TESTOUT25outputTCELL16:OUT.1.TMIN
TESTOUT26outputTCELL16:OUT.2.TMIN
TESTOUT27outputTCELL16:OUT.3.TMIN
TESTOUT28outputTCELL15:OUT.0.TMIN
TESTOUT29outputTCELL15:OUT.1.TMIN
TESTOUT3outputTCELL22:OUT.3.TMIN
TESTOUT30outputTCELL15:OUT.2.TMIN
TESTOUT31outputTCELL15:OUT.3.TMIN
TESTOUT32outputTCELL14:OUT.0.TMIN
TESTOUT33outputTCELL14:OUT.1.TMIN
TESTOUT34outputTCELL14:OUT.2.TMIN
TESTOUT35outputTCELL14:OUT.3.TMIN
TESTOUT36outputTCELL27:OUT.2.TMIN
TESTOUT4outputTCELL21:OUT.0.TMIN
TESTOUT5outputTCELL21:OUT.1.TMIN
TESTOUT6outputTCELL21:OUT.2.TMIN
TESTOUT7outputTCELL21:OUT.3.TMIN
TESTOUT8outputTCELL20:OUT.0.TMIN
TESTOUT9outputTCELL20:OUT.1.TMIN

Bel MMCM

ultrascale XIPHY bel MMCM
PinDirectionWires
CDDCDONEoutputTCELL55:OUT.3.TMIN
CDDCREQinputTCELL50:IMUX.IMUX.0.DELAY
CLKFBSTOPPEDoutputTCELL55:OUT.0.TMIN
CLKINSELinputTCELL41:IMUX.IMUX.0.DELAY
CLKINSTOPPEDoutputTCELL55:OUT.1.TMIN
DADDR0inputTCELL50:IMUX.BYP.0
DADDR1inputTCELL50:IMUX.BYP.1
DADDR2inputTCELL50:IMUX.BYP.2
DADDR3inputTCELL50:IMUX.BYP.3
DADDR4inputTCELL49:IMUX.BYP.0
DADDR5inputTCELL49:IMUX.BYP.1
DADDR6inputTCELL49:IMUX.BYP.2
DCLK_BinputTCELL52:IMUX.CTRL.0
DENinputTCELL52:IMUX.IMUX.0.DELAY
DI0inputTCELL54:IMUX.BYP.0
DI1inputTCELL54:IMUX.BYP.1
DI10inputTCELL52:IMUX.BYP.2
DI11inputTCELL52:IMUX.BYP.3
DI12inputTCELL51:IMUX.BYP.0
DI13inputTCELL51:IMUX.BYP.1
DI14inputTCELL51:IMUX.BYP.2
DI15inputTCELL51:IMUX.BYP.3
DI2inputTCELL54:IMUX.BYP.2
DI3inputTCELL54:IMUX.BYP.3
DI4inputTCELL53:IMUX.BYP.0
DI5inputTCELL53:IMUX.BYP.1
DI6inputTCELL53:IMUX.BYP.2
DI7inputTCELL53:IMUX.BYP.3
DI8inputTCELL52:IMUX.BYP.0
DI9inputTCELL52:IMUX.BYP.1
DOUT0outputTCELL53:OUT.0.TMIN
DOUT1outputTCELL53:OUT.1.TMIN
DOUT10outputTCELL51:OUT.2.TMIN
DOUT11outputTCELL51:OUT.3.TMIN
DOUT12outputTCELL50:OUT.0.TMIN
DOUT13outputTCELL50:OUT.1.TMIN
DOUT14outputTCELL50:OUT.2.TMIN
DOUT15outputTCELL50:OUT.3.TMIN
DOUT2outputTCELL53:OUT.2.TMIN
DOUT3outputTCELL53:OUT.3.TMIN
DOUT4outputTCELL52:OUT.0.TMIN
DOUT5outputTCELL52:OUT.1.TMIN
DOUT6outputTCELL52:OUT.2.TMIN
DOUT7outputTCELL52:OUT.3.TMIN
DOUT8outputTCELL51:OUT.0.TMIN
DOUT9outputTCELL51:OUT.1.TMIN
DRDYoutputTCELL54:OUT.0.TMIN
DWEinputTCELL51:IMUX.IMUX.0.DELAY
LOCKEDoutputTCELL54:OUT.1.TMIN
PSCLK_BinputTCELL53:IMUX.CTRL.0
PSDONEoutputTCELL55:OUT.2.TMIN
PSENinputTCELL56:IMUX.IMUX.0.DELAY
PSINCDECinputTCELL55:IMUX.IMUX.0.DELAY
PWRDWNinputTCELL53:IMUX.IMUX.0.DELAY
RSTinputTCELL54:IMUX.IMUX.0.DELAY
SCANCLK_BinputTCELL54:IMUX.CTRL.0
SCANENBinputTCELL48:IMUX.IMUX.0.DELAY
SCANINinputTCELL49:IMUX.IMUX.0.DELAY
SCANMODEBinputTCELL47:IMUX.IMUX.0.DELAY
SCANOUToutputTCELL54:OUT.3.TMIN
TESTIN0inputTCELL48:IMUX.BYP.0
TESTIN1inputTCELL48:IMUX.BYP.1
TESTIN10inputTCELL46:IMUX.BYP.2
TESTIN11inputTCELL46:IMUX.BYP.3
TESTIN12inputTCELL45:IMUX.BYP.0
TESTIN13inputTCELL45:IMUX.BYP.1
TESTIN14inputTCELL45:IMUX.BYP.2
TESTIN15inputTCELL45:IMUX.BYP.3
TESTIN16inputTCELL44:IMUX.BYP.0
TESTIN17inputTCELL44:IMUX.BYP.1
TESTIN18inputTCELL44:IMUX.BYP.2
TESTIN19inputTCELL44:IMUX.BYP.3
TESTIN2inputTCELL48:IMUX.BYP.2
TESTIN20inputTCELL43:IMUX.BYP.0
TESTIN21inputTCELL43:IMUX.BYP.1
TESTIN22inputTCELL43:IMUX.BYP.2
TESTIN23inputTCELL43:IMUX.BYP.3
TESTIN24inputTCELL42:IMUX.BYP.0
TESTIN25inputTCELL42:IMUX.BYP.1
TESTIN26inputTCELL42:IMUX.BYP.2
TESTIN27inputTCELL42:IMUX.BYP.3
TESTIN28inputTCELL41:IMUX.BYP.0
TESTIN29inputTCELL41:IMUX.BYP.1
TESTIN3inputTCELL48:IMUX.BYP.3
TESTIN30inputTCELL41:IMUX.BYP.2
TESTIN31inputTCELL41:IMUX.BYP.3
TESTIN4inputTCELL47:IMUX.BYP.0
TESTIN5inputTCELL47:IMUX.BYP.1
TESTIN6inputTCELL47:IMUX.BYP.2
TESTIN7inputTCELL47:IMUX.BYP.3
TESTIN8inputTCELL46:IMUX.BYP.0
TESTIN9inputTCELL46:IMUX.BYP.1
TESTOUT0outputTCELL49:OUT.0.TMIN
TESTOUT1outputTCELL49:OUT.1.TMIN
TESTOUT10outputTCELL47:OUT.2.TMIN
TESTOUT11outputTCELL47:OUT.3.TMIN
TESTOUT12outputTCELL46:OUT.0.TMIN
TESTOUT13outputTCELL46:OUT.1.TMIN
TESTOUT14outputTCELL46:OUT.2.TMIN
TESTOUT15outputTCELL46:OUT.3.TMIN
TESTOUT16outputTCELL45:OUT.0.TMIN
TESTOUT17outputTCELL45:OUT.1.TMIN
TESTOUT18outputTCELL45:OUT.2.TMIN
TESTOUT19outputTCELL45:OUT.3.TMIN
TESTOUT2outputTCELL49:OUT.2.TMIN
TESTOUT20outputTCELL44:OUT.0.TMIN
TESTOUT21outputTCELL44:OUT.1.TMIN
TESTOUT22outputTCELL44:OUT.2.TMIN
TESTOUT23outputTCELL44:OUT.3.TMIN
TESTOUT24outputTCELL43:OUT.0.TMIN
TESTOUT25outputTCELL43:OUT.1.TMIN
TESTOUT26outputTCELL43:OUT.2.TMIN
TESTOUT27outputTCELL43:OUT.3.TMIN
TESTOUT28outputTCELL42:OUT.0.TMIN
TESTOUT29outputTCELL42:OUT.1.TMIN
TESTOUT3outputTCELL49:OUT.3.TMIN
TESTOUT30outputTCELL42:OUT.2.TMIN
TESTOUT31outputTCELL42:OUT.3.TMIN
TESTOUT32outputTCELL41:OUT.0.TMIN
TESTOUT33outputTCELL41:OUT.1.TMIN
TESTOUT34outputTCELL41:OUT.2.TMIN
TESTOUT35outputTCELL41:OUT.3.TMIN
TESTOUT36outputTCELL54:OUT.2.TMIN
TESTOUT4outputTCELL48:OUT.0.TMIN
TESTOUT5outputTCELL48:OUT.1.TMIN
TESTOUT6outputTCELL48:OUT.2.TMIN
TESTOUT7outputTCELL48:OUT.3.TMIN
TESTOUT8outputTCELL47:OUT.0.TMIN
TESTOUT9outputTCELL47:OUT.1.TMIN

Bel CMT

ultrascale XIPHY bel CMT
PinDirectionWires

Bel VCC_CMT

ultrascale XIPHY bel VCC_CMT
PinDirectionWires

Bel BITSLICE0

ultrascale XIPHY bel BITSLICE0
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL0:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INTinputTCELL0:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL0:OUT.4.TMIN
RX_CE_IDELAYinputTCELL0:IMUX.BYP.14
RX_CE_IFDinputTCELL0:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0inputTCELL2:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL2:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL2:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL2:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL2:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL2:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL2:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL2:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL2:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL0:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL0:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL0:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL0:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL0:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL0:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL0:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL0:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL0:OUT.31.TMIN
RX_DATAIN1inputTCELL0:IMUX.IMUX.8.DELAY
RX_EN_VTCinputTCELL0:IMUX.BYP.13
RX_INCinputTCELL0:IMUX.BYP.12
RX_LDinputTCELL0:IMUX.BYP.11
RX_Q0outputTCELL0:OUT.5.TMIN
RX_Q1outputTCELL0:OUT.6.TMIN
RX_Q2outputTCELL0:OUT.7.TMIN
RX_Q3outputTCELL0:OUT.8.TMIN
RX_Q4outputTCELL0:OUT.9.TMIN
RX_Q5outputTCELL0:OUT.10.TMIN
RX_Q6outputTCELL0:OUT.11.TMIN
RX_Q7outputTCELL0:OUT.12.TMIN
TX_CE_ODELAYinputTCELL0:IMUX.BYP.10
TX_CE_OFDinputTCELL0:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0inputTCELL1:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1inputTCELL1:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2inputTCELL1:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3inputTCELL1:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4inputTCELL1:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL1:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6inputTCELL1:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7inputTCELL1:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8inputTCELL1:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL0:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL0:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL0:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL0:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL0:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL0:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL0:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL0:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL0:OUT.21.TMIN
TX_D0inputTCELL1:IMUX.IMUX.16.DELAY
TX_D1inputTCELL1:IMUX.IMUX.6.DELAY
TX_D2inputTCELL0:IMUX.IMUX.15.DELAY
TX_D3inputTCELL0:IMUX.IMUX.14.DELAY
TX_D4inputTCELL0:IMUX.IMUX.13.DELAY
TX_D5inputTCELL0:IMUX.IMUX.12.DELAY
TX_D6inputTCELL0:IMUX.IMUX.11.DELAY
TX_D7inputTCELL0:IMUX.IMUX.10.DELAY
TX_EN_VTCinputTCELL0:IMUX.BYP.9
TX_INCinputTCELL0:IMUX.BYP.8
TX_LDinputTCELL0:IMUX.BYP.7
TX_TinputTCELL0:IMUX.IMUX.16.DELAY
TX_T_OUToutputTCELL0:OUT.22.TMIN

Bel BITSLICE1

ultrascale XIPHY bel BITSLICE1
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL2:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INTinputTCELL1:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL1:OUT.4.TMIN
RX_CE_IDELAYinputTCELL1:IMUX.BYP.14
RX_CE_IFDinputTCELL2:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL2:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1inputTCELL2:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2inputTCELL2:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3inputTCELL2:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4inputTCELL2:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5inputTCELL2:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6inputTCELL2:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7inputTCELL2:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8inputTCELL2:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0outputTCELL1:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL1:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL1:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL1:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL1:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL1:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL1:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL1:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL1:OUT.31.TMIN
RX_DATAIN1inputTCELL2:IMUX.IMUX.28.DELAY
RX_EN_VTCinputTCELL1:IMUX.BYP.13
RX_INCinputTCELL1:IMUX.BYP.12
RX_LDinputTCELL1:IMUX.BYP.11
RX_Q0outputTCELL1:OUT.5.TMIN
RX_Q1outputTCELL1:OUT.6.TMIN
RX_Q2outputTCELL1:OUT.7.TMIN
RX_Q3outputTCELL1:OUT.8.TMIN
RX_Q4outputTCELL1:OUT.9.TMIN
RX_Q5outputTCELL1:OUT.10.TMIN
RX_Q6outputTCELL1:OUT.11.TMIN
RX_Q7outputTCELL1:OUT.12.TMIN
TX_CE_ODELAYinputTCELL1:IMUX.BYP.10
TX_CE_OFDinputTCELL2:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL2:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1inputTCELL2:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2inputTCELL2:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3inputTCELL2:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4inputTCELL2:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5inputTCELL2:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6inputTCELL2:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7inputTCELL2:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8inputTCELL2:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0outputTCELL1:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL1:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL1:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL1:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL1:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL1:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL1:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL1:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL1:OUT.21.TMIN
TX_D0inputTCELL2:IMUX.IMUX.30.DELAY
TX_D1inputTCELL2:IMUX.IMUX.6.DELAY
TX_D2inputTCELL2:IMUX.IMUX.31.DELAY
TX_D3inputTCELL2:IMUX.IMUX.7.DELAY
TX_D4inputTCELL2:IMUX.IMUX.32.DELAY
TX_D5inputTCELL2:IMUX.IMUX.33.DELAY
TX_D6inputTCELL2:IMUX.IMUX.34.DELAY
TX_D7inputTCELL2:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL1:IMUX.BYP.9
TX_INCinputTCELL1:IMUX.BYP.8
TX_LDinputTCELL1:IMUX.BYP.7
TX_TinputTCELL2:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL1:OUT.22.TMIN

Bel BITSLICE2

ultrascale XIPHY bel BITSLICE2
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL3:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INTinputTCELL2:IMUX.BYP.14
PHY2CLB_FIFO_EMPTYoutputTCELL2:OUT.4.TMIN
RX_CE_IDELAYinputTCELL2:IMUX.BYP.13
RX_CE_IFDinputTCELL3:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0inputTCELL3:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL3:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL3:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL3:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL3:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL3:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL3:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL3:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL3:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL2:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL2:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL2:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL2:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL2:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL2:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL2:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL2:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL2:OUT.31.TMIN
RX_DATAIN1inputTCELL3:IMUX.IMUX.17.DELAY
RX_EN_VTCinputTCELL2:IMUX.BYP.12
RX_INCinputTCELL2:IMUX.BYP.11
RX_LDinputTCELL2:IMUX.BYP.10
RX_Q0outputTCELL2:OUT.5.TMIN
RX_Q1outputTCELL2:OUT.6.TMIN
RX_Q2outputTCELL2:OUT.7.TMIN
RX_Q3outputTCELL2:OUT.8.TMIN
RX_Q4outputTCELL2:OUT.9.TMIN
RX_Q5outputTCELL2:OUT.10.TMIN
RX_Q6outputTCELL2:OUT.11.TMIN
RX_Q7outputTCELL2:OUT.12.TMIN
TX_CE_ODELAYinputTCELL2:IMUX.BYP.9
TX_CE_OFDinputTCELL2:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0inputTCELL3:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL3:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL3:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL3:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL3:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL3:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL3:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL3:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL3:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL2:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL2:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL2:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL2:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL2:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL2:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL2:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL2:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL2:OUT.21.TMIN
TX_D0inputTCELL3:IMUX.IMUX.20.DELAY
TX_D1inputTCELL3:IMUX.IMUX.21.DELAY
TX_D2inputTCELL3:IMUX.IMUX.22.DELAY
TX_D3inputTCELL3:IMUX.IMUX.23.DELAY
TX_D4inputTCELL3:IMUX.IMUX.24.DELAY
TX_D5inputTCELL3:IMUX.IMUX.25.DELAY
TX_D6inputTCELL3:IMUX.IMUX.26.DELAY
TX_D7inputTCELL3:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL2:IMUX.BYP.8
TX_INCinputTCELL2:IMUX.BYP.7
TX_LDinputTCELL2:IMUX.BYP.6
TX_TinputTCELL2:IMUX.IMUX.47.DELAY
TX_T_OUToutputTCELL2:OUT.22.TMIN

Bel BITSLICE3

ultrascale XIPHY bel BITSLICE3
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL4:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INTinputTCELL4:IMUX.BYP.10
PHY2CLB_FIFO_EMPTYoutputTCELL3:OUT.18.TMIN
RX_CE_IDELAYinputTCELL4:IMUX.BYP.9
RX_CE_IFDinputTCELL4:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0inputTCELL5:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1inputTCELL5:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2inputTCELL5:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3inputTCELL5:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4inputTCELL5:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5inputTCELL5:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6inputTCELL5:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7inputTCELL5:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8inputTCELL5:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0outputTCELL4:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL4:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL4:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL4:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL4:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL4:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL4:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL4:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL4:OUT.17.TMIN
RX_DATAIN1inputTCELL4:IMUX.IMUX.37.DELAY
RX_EN_VTCinputTCELL4:IMUX.BYP.8
RX_INCinputTCELL4:IMUX.BYP.7
RX_LDinputTCELL4:IMUX.BYP.6
RX_Q0outputTCELL3:OUT.19.TMIN
RX_Q1outputTCELL3:OUT.20.TMIN
RX_Q2outputTCELL3:OUT.21.TMIN
RX_Q3outputTCELL3:OUT.22.TMIN
RX_Q4outputTCELL3:OUT.23.TMIN
RX_Q5outputTCELL3:OUT.24.TMIN
RX_Q6outputTCELL3:OUT.25.TMIN
RX_Q7outputTCELL3:OUT.26.TMIN
TX_CE_ODELAYinputTCELL3:IMUX.BYP.15
TX_CE_OFDinputTCELL4:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0inputTCELL4:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1inputTCELL4:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2inputTCELL4:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3inputTCELL4:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4inputTCELL4:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5inputTCELL4:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6inputTCELL5:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7inputTCELL5:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8inputTCELL5:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0outputTCELL3:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL3:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL3:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL3:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL3:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL4:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL4:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL4:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL4:OUT.7.TMIN
TX_D0inputTCELL4:IMUX.IMUX.10.DELAY
TX_D1inputTCELL4:IMUX.IMUX.39.DELAY
TX_D2inputTCELL4:IMUX.IMUX.11.DELAY
TX_D3inputTCELL4:IMUX.IMUX.40.DELAY
TX_D4inputTCELL4:IMUX.IMUX.41.DELAY
TX_D5inputTCELL4:IMUX.IMUX.42.DELAY
TX_D6inputTCELL4:IMUX.IMUX.12.DELAY
TX_D7inputTCELL4:IMUX.IMUX.13.DELAY
TX_EN_VTCinputTCELL3:IMUX.BYP.14
TX_INCinputTCELL3:IMUX.BYP.13
TX_LDinputTCELL3:IMUX.BYP.12
TX_TinputTCELL4:IMUX.IMUX.35.DELAY
TX_T_OUToutputTCELL3:OUT.13.TMIN

Bel BITSLICE4

ultrascale XIPHY bel BITSLICE4
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL5:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL5:IMUX.BYP.9
PHY2CLB_FIFO_EMPTYoutputTCELL4:OUT.18.TMIN
RX_CE_IDELAYinputTCELL5:IMUX.BYP.8
RX_CE_IFDinputTCELL5:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL5:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1inputTCELL5:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2inputTCELL5:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3inputTCELL5:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4inputTCELL5:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5inputTCELL5:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6inputTCELL5:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7inputTCELL5:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8inputTCELL6:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0outputTCELL5:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL5:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL5:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL5:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL5:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL5:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL5:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL5:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL5:OUT.17.TMIN
RX_DATAIN1inputTCELL5:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL5:IMUX.BYP.7
RX_INCinputTCELL5:IMUX.BYP.6
RX_LDinputTCELL4:IMUX.BYP.15
RX_Q0outputTCELL4:OUT.19.TMIN
RX_Q1outputTCELL4:OUT.20.TMIN
RX_Q2outputTCELL4:OUT.21.TMIN
RX_Q3outputTCELL4:OUT.22.TMIN
RX_Q4outputTCELL4:OUT.23.TMIN
RX_Q5outputTCELL4:OUT.24.TMIN
RX_Q6outputTCELL4:OUT.25.TMIN
RX_Q7outputTCELL4:OUT.26.TMIN
TX_CE_ODELAYinputTCELL4:IMUX.BYP.14
TX_CE_OFDinputTCELL5:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL5:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL5:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL5:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL5:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL5:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL5:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL5:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL5:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8inputTCELL5:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0outputTCELL4:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL4:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL4:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL4:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL4:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL5:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL5:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL5:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL5:OUT.7.TMIN
TX_D0inputTCELL5:IMUX.IMUX.7.DELAY
TX_D1inputTCELL5:IMUX.IMUX.32.DELAY
TX_D2inputTCELL5:IMUX.IMUX.33.DELAY
TX_D3inputTCELL5:IMUX.IMUX.34.DELAY
TX_D4inputTCELL5:IMUX.IMUX.8.DELAY
TX_D5inputTCELL5:IMUX.IMUX.35.DELAY
TX_D6inputTCELL5:IMUX.IMUX.9.DELAY
TX_D7inputTCELL5:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL4:IMUX.BYP.13
TX_INCinputTCELL4:IMUX.BYP.12
TX_LDinputTCELL4:IMUX.BYP.11
TX_TinputTCELL5:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL4:OUT.8.TMIN

Bel BITSLICE5

ultrascale XIPHY bel BITSLICE5
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL6:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INTinputTCELL6:IMUX.BYP.8
PHY2CLB_FIFO_EMPTYoutputTCELL5:OUT.18.TMIN
RX_CE_IDELAYinputTCELL6:IMUX.BYP.7
RX_CE_IFDinputTCELL6:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0inputTCELL6:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL6:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL6:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL6:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL6:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL6:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL6:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL6:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL6:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL6:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL6:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL6:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL6:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL6:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL6:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL6:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL6:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL6:OUT.17.TMIN
RX_DATAIN1inputTCELL6:IMUX.IMUX.20.DELAY
RX_EN_VTCinputTCELL6:IMUX.BYP.6
RX_INCinputTCELL5:IMUX.BYP.15
RX_LDinputTCELL5:IMUX.BYP.14
RX_Q0outputTCELL5:OUT.19.TMIN
RX_Q1outputTCELL5:OUT.20.TMIN
RX_Q2outputTCELL5:OUT.21.TMIN
RX_Q3outputTCELL5:OUT.22.TMIN
RX_Q4outputTCELL5:OUT.23.TMIN
RX_Q5outputTCELL5:OUT.24.TMIN
RX_Q6outputTCELL5:OUT.25.TMIN
RX_Q7outputTCELL5:OUT.26.TMIN
TX_CE_ODELAYinputTCELL5:IMUX.BYP.13
TX_CE_OFDinputTCELL6:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0inputTCELL6:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1inputTCELL6:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2inputTCELL6:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3inputTCELL6:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4inputTCELL6:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5inputTCELL6:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6inputTCELL6:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7inputTCELL6:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8inputTCELL6:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0outputTCELL5:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL5:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL5:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL5:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL5:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL6:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL6:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL6:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL6:OUT.7.TMIN
TX_D0inputTCELL6:IMUX.IMUX.22.DELAY
TX_D1inputTCELL6:IMUX.IMUX.23.DELAY
TX_D2inputTCELL6:IMUX.IMUX.24.DELAY
TX_D3inputTCELL6:IMUX.IMUX.25.DELAY
TX_D4inputTCELL6:IMUX.IMUX.26.DELAY
TX_D5inputTCELL6:IMUX.IMUX.27.DELAY
TX_D6inputTCELL6:IMUX.IMUX.28.DELAY
TX_D7inputTCELL6:IMUX.IMUX.29.DELAY
TX_EN_VTCinputTCELL5:IMUX.BYP.12
TX_INCinputTCELL5:IMUX.BYP.11
TX_LDinputTCELL5:IMUX.BYP.10
TX_TinputTCELL6:IMUX.IMUX.17.DELAY
TX_T_OUToutputTCELL5:OUT.8.TMIN

Bel BITSLICE6

ultrascale XIPHY bel BITSLICE6
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL8:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INTinputTCELL9:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL8:OUT.18.TMIN
RX_CE_IDELAYinputTCELL9:IMUX.BYP.11
RX_CE_IFDinputTCELL8:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL8:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1inputTCELL8:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2inputTCELL8:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3inputTCELL8:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4inputTCELL8:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5inputTCELL8:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6inputTCELL8:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7inputTCELL8:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL8:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0outputTCELL9:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL9:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL9:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL9:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL9:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL9:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL9:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL9:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL9:OUT.17.TMIN
RX_DATAIN1inputTCELL8:IMUX.IMUX.29.DELAY
RX_EN_VTCinputTCELL9:IMUX.BYP.10
RX_INCinputTCELL9:IMUX.BYP.9
RX_LDinputTCELL9:IMUX.BYP.8
RX_Q0outputTCELL8:OUT.19.TMIN
RX_Q1outputTCELL8:OUT.20.TMIN
RX_Q2outputTCELL8:OUT.21.TMIN
RX_Q3outputTCELL8:OUT.22.TMIN
RX_Q4outputTCELL8:OUT.23.TMIN
RX_Q5outputTCELL8:OUT.24.TMIN
RX_Q6outputTCELL8:OUT.25.TMIN
RX_Q7outputTCELL8:OUT.26.TMIN
TX_CE_ODELAYinputTCELL9:IMUX.BYP.7
TX_CE_OFDinputTCELL8:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL8:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL8:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2inputTCELL8:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3inputTCELL8:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4inputTCELL8:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5inputTCELL8:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6inputTCELL8:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7inputTCELL8:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8inputTCELL8:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0outputTCELL8:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL8:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL8:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL8:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL8:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL9:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL9:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL9:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL9:OUT.7.TMIN
TX_D0inputTCELL8:IMUX.IMUX.6.DELAY
TX_D1inputTCELL8:IMUX.IMUX.31.DELAY
TX_D2inputTCELL8:IMUX.IMUX.7.DELAY
TX_D3inputTCELL8:IMUX.IMUX.32.DELAY
TX_D4inputTCELL8:IMUX.IMUX.33.DELAY
TX_D5inputTCELL8:IMUX.IMUX.34.DELAY
TX_D6inputTCELL8:IMUX.IMUX.8.DELAY
TX_D7inputTCELL8:IMUX.IMUX.35.DELAY
TX_EN_VTCinputTCELL9:IMUX.BYP.6
TX_INCinputTCELL8:IMUX.BYP.15
TX_LDinputTCELL8:IMUX.BYP.14
TX_TinputTCELL8:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL6:OUT.8.TMIN

Bel BITSLICE7

ultrascale XIPHY bel BITSLICE7
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL9:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INTinputTCELL10:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL9:OUT.18.TMIN
RX_CE_IDELAYinputTCELL10:IMUX.BYP.11
RX_CE_IFDinputTCELL9:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0inputTCELL9:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL9:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL9:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL9:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL9:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL9:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL9:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL9:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL9:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL10:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL10:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL10:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL10:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL10:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL10:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL10:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL10:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL10:OUT.17.TMIN
RX_DATAIN1inputTCELL9:IMUX.IMUX.18.DELAY
RX_EN_VTCinputTCELL10:IMUX.BYP.10
RX_INCinputTCELL10:IMUX.BYP.9
RX_LDinputTCELL10:IMUX.BYP.8
RX_Q0outputTCELL9:OUT.19.TMIN
RX_Q1outputTCELL9:OUT.20.TMIN
RX_Q2outputTCELL9:OUT.21.TMIN
RX_Q3outputTCELL9:OUT.22.TMIN
RX_Q4outputTCELL9:OUT.23.TMIN
RX_Q5outputTCELL9:OUT.24.TMIN
RX_Q6outputTCELL9:OUT.25.TMIN
RX_Q7outputTCELL9:OUT.26.TMIN
TX_CE_ODELAYinputTCELL10:IMUX.BYP.7
TX_CE_OFDinputTCELL9:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0inputTCELL9:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL9:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL9:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL9:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL9:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL9:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL9:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL9:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL9:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL9:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL9:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL9:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL9:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL9:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL10:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL10:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL10:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL10:OUT.7.TMIN
TX_D0inputTCELL9:IMUX.IMUX.20.DELAY
TX_D1inputTCELL9:IMUX.IMUX.21.DELAY
TX_D2inputTCELL9:IMUX.IMUX.22.DELAY
TX_D3inputTCELL9:IMUX.IMUX.23.DELAY
TX_D4inputTCELL9:IMUX.IMUX.24.DELAY
TX_D5inputTCELL9:IMUX.IMUX.25.DELAY
TX_D6inputTCELL9:IMUX.IMUX.26.DELAY
TX_D7inputTCELL9:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL10:IMUX.BYP.6
TX_INCinputTCELL9:IMUX.BYP.15
TX_LDinputTCELL9:IMUX.BYP.14
TX_TinputTCELL8:IMUX.IMUX.15.DELAY
TX_T_OUToutputTCELL8:OUT.8.TMIN

Bel BITSLICE8

ultrascale XIPHY bel BITSLICE8
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL9:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INTinputTCELL11:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL10:OUT.18.TMIN
RX_CE_IDELAYinputTCELL11:IMUX.BYP.11
RX_CE_IFDinputTCELL9:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0inputTCELL10:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1inputTCELL10:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2inputTCELL10:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3inputTCELL10:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4inputTCELL10:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5inputTCELL10:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6inputTCELL10:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7inputTCELL10:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8inputTCELL10:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0outputTCELL11:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL11:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL11:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL11:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL11:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL11:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL11:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL11:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL11:OUT.17.TMIN
RX_DATAIN1inputTCELL9:IMUX.IMUX.12.DELAY
RX_EN_VTCinputTCELL11:IMUX.BYP.10
RX_INCinputTCELL11:IMUX.BYP.9
RX_LDinputTCELL11:IMUX.BYP.8
RX_Q0outputTCELL10:OUT.19.TMIN
RX_Q1outputTCELL10:OUT.20.TMIN
RX_Q2outputTCELL10:OUT.21.TMIN
RX_Q3outputTCELL10:OUT.22.TMIN
RX_Q4outputTCELL10:OUT.23.TMIN
RX_Q5outputTCELL10:OUT.24.TMIN
RX_Q6outputTCELL10:OUT.25.TMIN
RX_Q7outputTCELL10:OUT.26.TMIN
TX_CE_ODELAYinputTCELL11:IMUX.BYP.6
TX_CE_OFDinputTCELL9:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0inputTCELL10:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1inputTCELL10:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2inputTCELL10:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3inputTCELL10:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4inputTCELL10:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5inputTCELL10:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6inputTCELL10:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7inputTCELL10:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8inputTCELL10:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0outputTCELL10:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL10:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL10:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL10:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL10:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL11:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL11:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL11:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL11:OUT.7.TMIN
TX_D0inputTCELL9:IMUX.IMUX.13.DELAY
TX_D1inputTCELL9:IMUX.IMUX.44.DELAY
TX_D2inputTCELL9:IMUX.IMUX.45.DELAY
TX_D3inputTCELL9:IMUX.IMUX.46.DELAY
TX_D4inputTCELL9:IMUX.IMUX.14.DELAY
TX_D5inputTCELL9:IMUX.IMUX.47.DELAY
TX_D6inputTCELL9:IMUX.IMUX.15.DELAY
TX_D7inputTCELL10:IMUX.IMUX.16.DELAY
TX_EN_VTCinputTCELL10:IMUX.BYP.15
TX_INCinputTCELL10:IMUX.BYP.14
TX_LDinputTCELL10:IMUX.BYP.13
TX_TinputTCELL9:IMUX.IMUX.40.DELAY
TX_T_OUToutputTCELL9:OUT.8.TMIN

Bel BITSLICE9

ultrascale XIPHY bel BITSLICE9
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL11:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL13:IMUX.BYP.7
PHY2CLB_FIFO_EMPTYoutputTCELL12:OUT.4.TMIN
RX_CE_IDELAYinputTCELL13:IMUX.BYP.6
RX_CE_IFDinputTCELL11:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL11:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1inputTCELL11:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2inputTCELL11:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3inputTCELL11:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4inputTCELL11:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5inputTCELL11:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6inputTCELL11:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7inputTCELL12:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8inputTCELL12:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0outputTCELL12:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL12:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL12:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL12:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL12:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL12:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL12:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL12:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL12:OUT.31.TMIN
RX_DATAIN1inputTCELL11:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL12:IMUX.BYP.15
RX_INCinputTCELL12:IMUX.BYP.14
RX_LDinputTCELL12:IMUX.BYP.13
RX_Q0outputTCELL12:OUT.5.TMIN
RX_Q1outputTCELL12:OUT.6.TMIN
RX_Q2outputTCELL12:OUT.7.TMIN
RX_Q3outputTCELL12:OUT.8.TMIN
RX_Q4outputTCELL12:OUT.9.TMIN
RX_Q5outputTCELL12:OUT.10.TMIN
RX_Q6outputTCELL12:OUT.11.TMIN
RX_Q7outputTCELL12:OUT.12.TMIN
TX_CE_ODELAYinputTCELL12:IMUX.BYP.12
TX_CE_OFDinputTCELL11:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL11:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL11:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL11:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL11:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL11:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL11:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL11:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL11:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8inputTCELL11:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0outputTCELL12:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL12:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL12:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL12:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL12:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL12:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL12:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL12:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL12:OUT.21.TMIN
TX_D0inputTCELL11:IMUX.IMUX.7.DELAY
TX_D1inputTCELL11:IMUX.IMUX.32.DELAY
TX_D2inputTCELL11:IMUX.IMUX.33.DELAY
TX_D3inputTCELL11:IMUX.IMUX.34.DELAY
TX_D4inputTCELL11:IMUX.IMUX.8.DELAY
TX_D5inputTCELL11:IMUX.IMUX.35.DELAY
TX_D6inputTCELL11:IMUX.IMUX.9.DELAY
TX_D7inputTCELL11:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL12:IMUX.BYP.11
TX_INCinputTCELL12:IMUX.BYP.10
TX_LDinputTCELL12:IMUX.BYP.9
TX_TinputTCELL11:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL10:OUT.8.TMIN

Bel BITSLICE10

ultrascale XIPHY bel BITSLICE10
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL12:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INTinputTCELL14:IMUX.BYP.6
PHY2CLB_FIFO_EMPTYoutputTCELL13:OUT.4.TMIN
RX_CE_IDELAYinputTCELL13:IMUX.BYP.15
RX_CE_IFDinputTCELL12:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0inputTCELL12:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL12:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL12:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL12:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL12:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL12:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL12:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL12:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL12:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL13:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL13:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL13:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL13:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL13:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL13:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL13:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL13:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL13:OUT.31.TMIN
RX_DATAIN1inputTCELL12:IMUX.IMUX.21.DELAY
RX_EN_VTCinputTCELL13:IMUX.BYP.14
RX_INCinputTCELL13:IMUX.BYP.13
RX_LDinputTCELL13:IMUX.BYP.12
RX_Q0outputTCELL13:OUT.5.TMIN
RX_Q1outputTCELL13:OUT.6.TMIN
RX_Q2outputTCELL13:OUT.7.TMIN
RX_Q3outputTCELL13:OUT.8.TMIN
RX_Q4outputTCELL13:OUT.9.TMIN
RX_Q5outputTCELL13:OUT.10.TMIN
RX_Q6outputTCELL13:OUT.11.TMIN
RX_Q7outputTCELL13:OUT.12.TMIN
TX_CE_ODELAYinputTCELL13:IMUX.BYP.11
TX_CE_OFDinputTCELL12:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0inputTCELL12:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1inputTCELL12:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2inputTCELL12:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3inputTCELL12:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4inputTCELL12:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5inputTCELL12:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6inputTCELL12:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7inputTCELL12:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8inputTCELL12:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0outputTCELL13:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL13:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL13:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL13:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL13:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL13:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL13:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL13:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL13:OUT.21.TMIN
TX_D0inputTCELL12:IMUX.IMUX.28.DELAY
TX_D1inputTCELL12:IMUX.IMUX.27.DELAY
TX_D2inputTCELL12:IMUX.IMUX.26.DELAY
TX_D3inputTCELL12:IMUX.IMUX.25.DELAY
TX_D4inputTCELL12:IMUX.IMUX.24.DELAY
TX_D5inputTCELL12:IMUX.IMUX.23.DELAY
TX_D6inputTCELL12:IMUX.IMUX.29.DELAY
TX_D7inputTCELL12:IMUX.IMUX.30.DELAY
TX_EN_VTCinputTCELL13:IMUX.BYP.10
TX_INCinputTCELL13:IMUX.BYP.9
TX_LDinputTCELL13:IMUX.BYP.8
TX_TinputTCELL12:IMUX.IMUX.18.DELAY
TX_T_OUToutputTCELL11:OUT.8.TMIN

Bel BITSLICE11

ultrascale XIPHY bel BITSLICE11
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL12:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INTinputTCELL14:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL14:OUT.4.TMIN
RX_CE_IDELAYinputTCELL14:IMUX.BYP.14
RX_CE_IFDinputTCELL12:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0inputTCELL14:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1inputTCELL14:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2inputTCELL14:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL14:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL14:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5inputTCELL14:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6inputTCELL14:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7inputTCELL14:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL14:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0outputTCELL14:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL14:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL14:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL14:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL14:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL14:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL14:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL14:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL14:OUT.31.TMIN
RX_DATAIN1inputTCELL12:IMUX.IMUX.44.DELAY
RX_EN_VTCinputTCELL14:IMUX.BYP.13
RX_INCinputTCELL14:IMUX.BYP.12
RX_LDinputTCELL14:IMUX.BYP.11
RX_Q0outputTCELL14:OUT.5.TMIN
RX_Q1outputTCELL14:OUT.6.TMIN
RX_Q2outputTCELL14:OUT.7.TMIN
RX_Q3outputTCELL14:OUT.8.TMIN
RX_Q4outputTCELL14:OUT.9.TMIN
RX_Q5outputTCELL14:OUT.10.TMIN
RX_Q6outputTCELL14:OUT.11.TMIN
RX_Q7outputTCELL14:OUT.12.TMIN
TX_CE_ODELAYinputTCELL14:IMUX.BYP.10
TX_CE_OFDinputTCELL12:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0inputTCELL13:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL13:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2inputTCELL13:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3inputTCELL13:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4inputTCELL13:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5inputTCELL13:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6inputTCELL13:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7inputTCELL14:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8inputTCELL14:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0outputTCELL14:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL14:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL14:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL14:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL14:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL14:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL14:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL14:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL14:OUT.21.TMIN
TX_D0inputTCELL12:IMUX.IMUX.46.DELAY
TX_D1inputTCELL12:IMUX.IMUX.14.DELAY
TX_D2inputTCELL12:IMUX.IMUX.47.DELAY
TX_D3inputTCELL12:IMUX.IMUX.15.DELAY
TX_D4inputTCELL13:IMUX.IMUX.16.DELAY
TX_D5inputTCELL13:IMUX.IMUX.6.DELAY
TX_D6inputTCELL13:IMUX.IMUX.7.DELAY
TX_D7inputTCELL13:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL14:IMUX.BYP.9
TX_INCinputTCELL14:IMUX.BYP.8
TX_LDinputTCELL14:IMUX.BYP.7
TX_TinputTCELL12:IMUX.IMUX.12.DELAY
TX_T_OUToutputTCELL11:OUT.31.TMIN

Bel BITSLICE12

ultrascale XIPHY bel BITSLICE12
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL7:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INTinputTCELL8:IMUX.BYP.13
PHY2CLB_FIFO_EMPTYoutputTCELL7:OUT.18.TMIN
RX_CE_IDELAYinputTCELL8:IMUX.BYP.12
RX_CE_IFDinputTCELL7:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0inputTCELL8:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL8:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL8:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL8:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL8:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL8:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL8:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL8:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL8:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL8:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL8:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL8:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL8:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL8:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL8:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL8:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL8:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL8:OUT.17.TMIN
RX_DATAIN1inputTCELL7:IMUX.IMUX.9.DELAY
RX_EN_VTCinputTCELL8:IMUX.BYP.11
RX_INCinputTCELL8:IMUX.BYP.10
RX_LDinputTCELL8:IMUX.BYP.9
RX_Q0outputTCELL7:OUT.19.TMIN
RX_Q1outputTCELL7:OUT.20.TMIN
RX_Q2outputTCELL7:OUT.21.TMIN
RX_Q3outputTCELL7:OUT.22.TMIN
RX_Q4outputTCELL7:OUT.23.TMIN
RX_Q5outputTCELL7:OUT.24.TMIN
RX_Q6outputTCELL7:OUT.25.TMIN
RX_Q7outputTCELL7:OUT.26.TMIN
TX_CE_ODELAYinputTCELL8:IMUX.BYP.8
TX_CE_OFDinputTCELL7:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0inputTCELL7:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1inputTCELL7:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2inputTCELL7:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3inputTCELL7:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4inputTCELL7:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5inputTCELL7:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6inputTCELL7:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7inputTCELL7:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8inputTCELL7:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL7:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL7:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL7:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL7:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL7:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL8:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL8:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL8:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL8:OUT.7.TMIN
TX_D0inputTCELL7:IMUX.IMUX.37.DELAY
TX_D1inputTCELL7:IMUX.IMUX.38.DELAY
TX_D2inputTCELL7:IMUX.IMUX.10.DELAY
TX_D3inputTCELL7:IMUX.IMUX.39.DELAY
TX_D4inputTCELL7:IMUX.IMUX.11.DELAY
TX_D5inputTCELL7:IMUX.IMUX.40.DELAY
TX_D6inputTCELL7:IMUX.IMUX.41.DELAY
TX_D7inputTCELL7:IMUX.IMUX.42.DELAY
TX_EN_VTCinputTCELL8:IMUX.BYP.7
TX_INCinputTCELL8:IMUX.BYP.6
TX_LDinputTCELL7:IMUX.BYP.15
TX_TinputTCELL7:IMUX.IMUX.34.DELAY
TX_T_OUToutputTCELL12:OUT.22.TMIN

Bel BITSLICE13

ultrascale XIPHY bel BITSLICE13
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL15:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INTinputTCELL15:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL15:OUT.4.TMIN
RX_CE_IDELAYinputTCELL15:IMUX.BYP.14
RX_CE_IFDinputTCELL15:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0inputTCELL17:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL17:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL17:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL17:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL17:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL17:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL17:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL17:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL17:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL15:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL15:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL15:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL15:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL15:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL15:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL15:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL15:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL15:OUT.31.TMIN
RX_DATAIN1inputTCELL15:IMUX.IMUX.8.DELAY
RX_EN_VTCinputTCELL15:IMUX.BYP.13
RX_INCinputTCELL15:IMUX.BYP.12
RX_LDinputTCELL15:IMUX.BYP.11
RX_Q0outputTCELL15:OUT.5.TMIN
RX_Q1outputTCELL15:OUT.6.TMIN
RX_Q2outputTCELL15:OUT.7.TMIN
RX_Q3outputTCELL15:OUT.8.TMIN
RX_Q4outputTCELL15:OUT.9.TMIN
RX_Q5outputTCELL15:OUT.10.TMIN
RX_Q6outputTCELL15:OUT.11.TMIN
RX_Q7outputTCELL15:OUT.12.TMIN
TX_CE_ODELAYinputTCELL15:IMUX.BYP.10
TX_CE_OFDinputTCELL15:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0inputTCELL16:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1inputTCELL16:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2inputTCELL16:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3inputTCELL16:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4inputTCELL16:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL16:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6inputTCELL16:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7inputTCELL16:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8inputTCELL16:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL15:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL15:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL15:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL15:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL15:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL15:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL15:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL15:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL15:OUT.21.TMIN
TX_D0inputTCELL16:IMUX.IMUX.16.DELAY
TX_D1inputTCELL16:IMUX.IMUX.6.DELAY
TX_D2inputTCELL15:IMUX.IMUX.15.DELAY
TX_D3inputTCELL15:IMUX.IMUX.14.DELAY
TX_D4inputTCELL15:IMUX.IMUX.13.DELAY
TX_D5inputTCELL15:IMUX.IMUX.12.DELAY
TX_D6inputTCELL15:IMUX.IMUX.11.DELAY
TX_D7inputTCELL15:IMUX.IMUX.10.DELAY
TX_EN_VTCinputTCELL15:IMUX.BYP.9
TX_INCinputTCELL15:IMUX.BYP.8
TX_LDinputTCELL15:IMUX.BYP.7
TX_TinputTCELL15:IMUX.IMUX.16.DELAY
TX_T_OUToutputTCELL15:OUT.22.TMIN

Bel BITSLICE14

ultrascale XIPHY bel BITSLICE14
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL17:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INTinputTCELL16:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL16:OUT.4.TMIN
RX_CE_IDELAYinputTCELL16:IMUX.BYP.14
RX_CE_IFDinputTCELL17:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL17:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1inputTCELL17:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2inputTCELL17:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3inputTCELL17:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4inputTCELL17:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5inputTCELL17:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6inputTCELL17:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7inputTCELL17:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8inputTCELL17:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0outputTCELL16:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL16:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL16:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL16:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL16:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL16:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL16:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL16:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL16:OUT.31.TMIN
RX_DATAIN1inputTCELL17:IMUX.IMUX.28.DELAY
RX_EN_VTCinputTCELL16:IMUX.BYP.13
RX_INCinputTCELL16:IMUX.BYP.12
RX_LDinputTCELL16:IMUX.BYP.11
RX_Q0outputTCELL16:OUT.5.TMIN
RX_Q1outputTCELL16:OUT.6.TMIN
RX_Q2outputTCELL16:OUT.7.TMIN
RX_Q3outputTCELL16:OUT.8.TMIN
RX_Q4outputTCELL16:OUT.9.TMIN
RX_Q5outputTCELL16:OUT.10.TMIN
RX_Q6outputTCELL16:OUT.11.TMIN
RX_Q7outputTCELL16:OUT.12.TMIN
TX_CE_ODELAYinputTCELL16:IMUX.BYP.10
TX_CE_OFDinputTCELL17:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL17:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1inputTCELL17:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2inputTCELL17:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3inputTCELL17:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4inputTCELL17:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5inputTCELL17:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6inputTCELL17:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7inputTCELL17:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8inputTCELL17:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0outputTCELL16:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL16:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL16:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL16:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL16:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL16:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL16:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL16:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL16:OUT.21.TMIN
TX_D0inputTCELL17:IMUX.IMUX.30.DELAY
TX_D1inputTCELL17:IMUX.IMUX.6.DELAY
TX_D2inputTCELL17:IMUX.IMUX.31.DELAY
TX_D3inputTCELL17:IMUX.IMUX.7.DELAY
TX_D4inputTCELL17:IMUX.IMUX.32.DELAY
TX_D5inputTCELL17:IMUX.IMUX.33.DELAY
TX_D6inputTCELL17:IMUX.IMUX.34.DELAY
TX_D7inputTCELL17:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL16:IMUX.BYP.9
TX_INCinputTCELL16:IMUX.BYP.8
TX_LDinputTCELL16:IMUX.BYP.7
TX_TinputTCELL17:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL16:OUT.22.TMIN

Bel BITSLICE15

ultrascale XIPHY bel BITSLICE15
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL18:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INTinputTCELL17:IMUX.BYP.14
PHY2CLB_FIFO_EMPTYoutputTCELL17:OUT.4.TMIN
RX_CE_IDELAYinputTCELL17:IMUX.BYP.13
RX_CE_IFDinputTCELL18:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0inputTCELL18:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL18:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL18:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL18:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL18:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL18:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL18:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL18:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL18:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL17:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL17:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL17:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL17:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL17:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL17:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL17:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL17:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL17:OUT.31.TMIN
RX_DATAIN1inputTCELL18:IMUX.IMUX.17.DELAY
RX_EN_VTCinputTCELL17:IMUX.BYP.12
RX_INCinputTCELL17:IMUX.BYP.11
RX_LDinputTCELL17:IMUX.BYP.10
RX_Q0outputTCELL17:OUT.5.TMIN
RX_Q1outputTCELL17:OUT.6.TMIN
RX_Q2outputTCELL17:OUT.7.TMIN
RX_Q3outputTCELL17:OUT.8.TMIN
RX_Q4outputTCELL17:OUT.9.TMIN
RX_Q5outputTCELL17:OUT.10.TMIN
RX_Q6outputTCELL17:OUT.11.TMIN
RX_Q7outputTCELL17:OUT.12.TMIN
TX_CE_ODELAYinputTCELL17:IMUX.BYP.9
TX_CE_OFDinputTCELL17:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0inputTCELL18:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL18:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL18:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL18:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL18:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL18:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL18:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL18:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL18:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL17:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL17:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL17:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL17:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL17:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL17:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL17:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL17:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL17:OUT.21.TMIN
TX_D0inputTCELL18:IMUX.IMUX.20.DELAY
TX_D1inputTCELL18:IMUX.IMUX.21.DELAY
TX_D2inputTCELL18:IMUX.IMUX.22.DELAY
TX_D3inputTCELL18:IMUX.IMUX.23.DELAY
TX_D4inputTCELL18:IMUX.IMUX.24.DELAY
TX_D5inputTCELL18:IMUX.IMUX.25.DELAY
TX_D6inputTCELL18:IMUX.IMUX.26.DELAY
TX_D7inputTCELL18:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL17:IMUX.BYP.8
TX_INCinputTCELL17:IMUX.BYP.7
TX_LDinputTCELL17:IMUX.BYP.6
TX_TinputTCELL17:IMUX.IMUX.47.DELAY
TX_T_OUToutputTCELL17:OUT.22.TMIN

Bel BITSLICE16

ultrascale XIPHY bel BITSLICE16
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL19:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INTinputTCELL19:IMUX.BYP.10
PHY2CLB_FIFO_EMPTYoutputTCELL18:OUT.18.TMIN
RX_CE_IDELAYinputTCELL19:IMUX.BYP.9
RX_CE_IFDinputTCELL19:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0inputTCELL20:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1inputTCELL20:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2inputTCELL20:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3inputTCELL20:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4inputTCELL20:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5inputTCELL20:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6inputTCELL20:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7inputTCELL20:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8inputTCELL20:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0outputTCELL19:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL19:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL19:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL19:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL19:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL19:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL19:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL19:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL19:OUT.17.TMIN
RX_DATAIN1inputTCELL19:IMUX.IMUX.37.DELAY
RX_EN_VTCinputTCELL19:IMUX.BYP.8
RX_INCinputTCELL19:IMUX.BYP.7
RX_LDinputTCELL19:IMUX.BYP.6
RX_Q0outputTCELL18:OUT.19.TMIN
RX_Q1outputTCELL18:OUT.20.TMIN
RX_Q2outputTCELL18:OUT.21.TMIN
RX_Q3outputTCELL18:OUT.22.TMIN
RX_Q4outputTCELL18:OUT.23.TMIN
RX_Q5outputTCELL18:OUT.24.TMIN
RX_Q6outputTCELL18:OUT.25.TMIN
RX_Q7outputTCELL18:OUT.26.TMIN
TX_CE_ODELAYinputTCELL18:IMUX.BYP.15
TX_CE_OFDinputTCELL19:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0inputTCELL19:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1inputTCELL19:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2inputTCELL19:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3inputTCELL19:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4inputTCELL19:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5inputTCELL19:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6inputTCELL20:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7inputTCELL20:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8inputTCELL20:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0outputTCELL18:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL18:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL18:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL18:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL18:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL19:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL19:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL19:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL19:OUT.7.TMIN
TX_D0inputTCELL19:IMUX.IMUX.10.DELAY
TX_D1inputTCELL19:IMUX.IMUX.39.DELAY
TX_D2inputTCELL19:IMUX.IMUX.11.DELAY
TX_D3inputTCELL19:IMUX.IMUX.40.DELAY
TX_D4inputTCELL19:IMUX.IMUX.41.DELAY
TX_D5inputTCELL19:IMUX.IMUX.42.DELAY
TX_D6inputTCELL19:IMUX.IMUX.12.DELAY
TX_D7inputTCELL19:IMUX.IMUX.13.DELAY
TX_EN_VTCinputTCELL18:IMUX.BYP.14
TX_INCinputTCELL18:IMUX.BYP.13
TX_LDinputTCELL18:IMUX.BYP.12
TX_TinputTCELL19:IMUX.IMUX.35.DELAY
TX_T_OUToutputTCELL18:OUT.13.TMIN

Bel BITSLICE17

ultrascale XIPHY bel BITSLICE17
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL20:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL20:IMUX.BYP.9
PHY2CLB_FIFO_EMPTYoutputTCELL19:OUT.18.TMIN
RX_CE_IDELAYinputTCELL20:IMUX.BYP.8
RX_CE_IFDinputTCELL20:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL20:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1inputTCELL20:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2inputTCELL20:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3inputTCELL20:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4inputTCELL20:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5inputTCELL20:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6inputTCELL20:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7inputTCELL20:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8inputTCELL21:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0outputTCELL20:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL20:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL20:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL20:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL20:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL20:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL20:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL20:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL20:OUT.17.TMIN
RX_DATAIN1inputTCELL20:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL20:IMUX.BYP.7
RX_INCinputTCELL20:IMUX.BYP.6
RX_LDinputTCELL19:IMUX.BYP.15
RX_Q0outputTCELL19:OUT.19.TMIN
RX_Q1outputTCELL19:OUT.20.TMIN
RX_Q2outputTCELL19:OUT.21.TMIN
RX_Q3outputTCELL19:OUT.22.TMIN
RX_Q4outputTCELL19:OUT.23.TMIN
RX_Q5outputTCELL19:OUT.24.TMIN
RX_Q6outputTCELL19:OUT.25.TMIN
RX_Q7outputTCELL19:OUT.26.TMIN
TX_CE_ODELAYinputTCELL19:IMUX.BYP.14
TX_CE_OFDinputTCELL20:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL20:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL20:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL20:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL20:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL20:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL20:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL20:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL20:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8inputTCELL20:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0outputTCELL19:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL19:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL19:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL19:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL19:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL20:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL20:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL20:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL20:OUT.7.TMIN
TX_D0inputTCELL20:IMUX.IMUX.7.DELAY
TX_D1inputTCELL20:IMUX.IMUX.32.DELAY
TX_D2inputTCELL20:IMUX.IMUX.33.DELAY
TX_D3inputTCELL20:IMUX.IMUX.34.DELAY
TX_D4inputTCELL20:IMUX.IMUX.8.DELAY
TX_D5inputTCELL20:IMUX.IMUX.35.DELAY
TX_D6inputTCELL20:IMUX.IMUX.9.DELAY
TX_D7inputTCELL20:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL19:IMUX.BYP.13
TX_INCinputTCELL19:IMUX.BYP.12
TX_LDinputTCELL19:IMUX.BYP.11
TX_TinputTCELL20:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL19:OUT.8.TMIN

Bel BITSLICE18

ultrascale XIPHY bel BITSLICE18
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL21:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INTinputTCELL21:IMUX.BYP.8
PHY2CLB_FIFO_EMPTYoutputTCELL20:OUT.18.TMIN
RX_CE_IDELAYinputTCELL21:IMUX.BYP.7
RX_CE_IFDinputTCELL21:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0inputTCELL21:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL21:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL21:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL21:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL21:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL21:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL21:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL21:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL21:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL21:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL21:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL21:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL21:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL21:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL21:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL21:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL21:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL21:OUT.17.TMIN
RX_DATAIN1inputTCELL21:IMUX.IMUX.20.DELAY
RX_EN_VTCinputTCELL21:IMUX.BYP.6
RX_INCinputTCELL20:IMUX.BYP.15
RX_LDinputTCELL20:IMUX.BYP.14
RX_Q0outputTCELL20:OUT.19.TMIN
RX_Q1outputTCELL20:OUT.20.TMIN
RX_Q2outputTCELL20:OUT.21.TMIN
RX_Q3outputTCELL20:OUT.22.TMIN
RX_Q4outputTCELL20:OUT.23.TMIN
RX_Q5outputTCELL20:OUT.24.TMIN
RX_Q6outputTCELL20:OUT.25.TMIN
RX_Q7outputTCELL20:OUT.26.TMIN
TX_CE_ODELAYinputTCELL20:IMUX.BYP.13
TX_CE_OFDinputTCELL21:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0inputTCELL21:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1inputTCELL21:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2inputTCELL21:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3inputTCELL21:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4inputTCELL21:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5inputTCELL21:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6inputTCELL21:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7inputTCELL21:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8inputTCELL21:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0outputTCELL20:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL20:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL20:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL20:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL20:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL21:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL21:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL21:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL21:OUT.7.TMIN
TX_D0inputTCELL21:IMUX.IMUX.22.DELAY
TX_D1inputTCELL21:IMUX.IMUX.23.DELAY
TX_D2inputTCELL21:IMUX.IMUX.24.DELAY
TX_D3inputTCELL21:IMUX.IMUX.25.DELAY
TX_D4inputTCELL21:IMUX.IMUX.26.DELAY
TX_D5inputTCELL21:IMUX.IMUX.27.DELAY
TX_D6inputTCELL21:IMUX.IMUX.28.DELAY
TX_D7inputTCELL21:IMUX.IMUX.29.DELAY
TX_EN_VTCinputTCELL20:IMUX.BYP.12
TX_INCinputTCELL20:IMUX.BYP.11
TX_LDinputTCELL20:IMUX.BYP.10
TX_TinputTCELL21:IMUX.IMUX.17.DELAY
TX_T_OUToutputTCELL20:OUT.8.TMIN

Bel BITSLICE19

ultrascale XIPHY bel BITSLICE19
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL23:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INTinputTCELL24:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL23:OUT.18.TMIN
RX_CE_IDELAYinputTCELL24:IMUX.BYP.11
RX_CE_IFDinputTCELL23:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL23:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1inputTCELL23:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2inputTCELL23:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3inputTCELL23:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4inputTCELL23:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5inputTCELL23:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6inputTCELL23:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7inputTCELL23:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL23:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0outputTCELL24:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL24:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL24:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL24:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL24:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL24:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL24:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL24:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL24:OUT.17.TMIN
RX_DATAIN1inputTCELL23:IMUX.IMUX.29.DELAY
RX_EN_VTCinputTCELL24:IMUX.BYP.10
RX_INCinputTCELL24:IMUX.BYP.9
RX_LDinputTCELL24:IMUX.BYP.8
RX_Q0outputTCELL23:OUT.19.TMIN
RX_Q1outputTCELL23:OUT.20.TMIN
RX_Q2outputTCELL23:OUT.21.TMIN
RX_Q3outputTCELL23:OUT.22.TMIN
RX_Q4outputTCELL23:OUT.23.TMIN
RX_Q5outputTCELL23:OUT.24.TMIN
RX_Q6outputTCELL23:OUT.25.TMIN
RX_Q7outputTCELL23:OUT.26.TMIN
TX_CE_ODELAYinputTCELL24:IMUX.BYP.7
TX_CE_OFDinputTCELL23:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL23:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL23:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2inputTCELL23:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3inputTCELL23:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4inputTCELL23:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5inputTCELL23:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6inputTCELL23:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7inputTCELL23:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8inputTCELL23:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0outputTCELL23:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL23:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL23:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL23:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL23:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL24:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL24:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL24:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL24:OUT.7.TMIN
TX_D0inputTCELL23:IMUX.IMUX.6.DELAY
TX_D1inputTCELL23:IMUX.IMUX.31.DELAY
TX_D2inputTCELL23:IMUX.IMUX.7.DELAY
TX_D3inputTCELL23:IMUX.IMUX.32.DELAY
TX_D4inputTCELL23:IMUX.IMUX.33.DELAY
TX_D5inputTCELL23:IMUX.IMUX.34.DELAY
TX_D6inputTCELL23:IMUX.IMUX.8.DELAY
TX_D7inputTCELL23:IMUX.IMUX.35.DELAY
TX_EN_VTCinputTCELL24:IMUX.BYP.6
TX_INCinputTCELL23:IMUX.BYP.15
TX_LDinputTCELL23:IMUX.BYP.14
TX_TinputTCELL23:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL21:OUT.8.TMIN

Bel BITSLICE20

ultrascale XIPHY bel BITSLICE20
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL24:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INTinputTCELL25:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL24:OUT.18.TMIN
RX_CE_IDELAYinputTCELL25:IMUX.BYP.11
RX_CE_IFDinputTCELL24:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0inputTCELL24:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL24:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL24:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL24:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL24:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL24:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL24:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL24:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL24:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL25:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL25:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL25:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL25:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL25:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL25:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL25:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL25:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL25:OUT.17.TMIN
RX_DATAIN1inputTCELL24:IMUX.IMUX.18.DELAY
RX_EN_VTCinputTCELL25:IMUX.BYP.10
RX_INCinputTCELL25:IMUX.BYP.9
RX_LDinputTCELL25:IMUX.BYP.8
RX_Q0outputTCELL24:OUT.19.TMIN
RX_Q1outputTCELL24:OUT.20.TMIN
RX_Q2outputTCELL24:OUT.21.TMIN
RX_Q3outputTCELL24:OUT.22.TMIN
RX_Q4outputTCELL24:OUT.23.TMIN
RX_Q5outputTCELL24:OUT.24.TMIN
RX_Q6outputTCELL24:OUT.25.TMIN
RX_Q7outputTCELL24:OUT.26.TMIN
TX_CE_ODELAYinputTCELL25:IMUX.BYP.7
TX_CE_OFDinputTCELL24:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0inputTCELL24:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL24:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL24:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL24:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL24:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL24:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL24:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL24:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL24:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL24:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL24:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL24:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL24:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL24:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL25:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL25:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL25:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL25:OUT.7.TMIN
TX_D0inputTCELL24:IMUX.IMUX.20.DELAY
TX_D1inputTCELL24:IMUX.IMUX.21.DELAY
TX_D2inputTCELL24:IMUX.IMUX.22.DELAY
TX_D3inputTCELL24:IMUX.IMUX.23.DELAY
TX_D4inputTCELL24:IMUX.IMUX.24.DELAY
TX_D5inputTCELL24:IMUX.IMUX.25.DELAY
TX_D6inputTCELL24:IMUX.IMUX.26.DELAY
TX_D7inputTCELL24:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL25:IMUX.BYP.6
TX_INCinputTCELL24:IMUX.BYP.15
TX_LDinputTCELL24:IMUX.BYP.14
TX_TinputTCELL23:IMUX.IMUX.15.DELAY
TX_T_OUToutputTCELL23:OUT.8.TMIN

Bel BITSLICE21

ultrascale XIPHY bel BITSLICE21
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL24:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INTinputTCELL26:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL25:OUT.18.TMIN
RX_CE_IDELAYinputTCELL26:IMUX.BYP.11
RX_CE_IFDinputTCELL24:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0inputTCELL25:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1inputTCELL25:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2inputTCELL25:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3inputTCELL25:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4inputTCELL25:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5inputTCELL25:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6inputTCELL25:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7inputTCELL25:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8inputTCELL25:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0outputTCELL26:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL26:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL26:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL26:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL26:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL26:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL26:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL26:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL26:OUT.17.TMIN
RX_DATAIN1inputTCELL24:IMUX.IMUX.12.DELAY
RX_EN_VTCinputTCELL26:IMUX.BYP.10
RX_INCinputTCELL26:IMUX.BYP.9
RX_LDinputTCELL26:IMUX.BYP.8
RX_Q0outputTCELL25:OUT.19.TMIN
RX_Q1outputTCELL25:OUT.20.TMIN
RX_Q2outputTCELL25:OUT.21.TMIN
RX_Q3outputTCELL25:OUT.22.TMIN
RX_Q4outputTCELL25:OUT.23.TMIN
RX_Q5outputTCELL25:OUT.24.TMIN
RX_Q6outputTCELL25:OUT.25.TMIN
RX_Q7outputTCELL25:OUT.26.TMIN
TX_CE_ODELAYinputTCELL26:IMUX.BYP.6
TX_CE_OFDinputTCELL24:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0inputTCELL25:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1inputTCELL25:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2inputTCELL25:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3inputTCELL25:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4inputTCELL25:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5inputTCELL25:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6inputTCELL25:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7inputTCELL25:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8inputTCELL25:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0outputTCELL25:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL25:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL25:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL25:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL25:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL26:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL26:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL26:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL26:OUT.7.TMIN
TX_D0inputTCELL24:IMUX.IMUX.13.DELAY
TX_D1inputTCELL24:IMUX.IMUX.44.DELAY
TX_D2inputTCELL24:IMUX.IMUX.45.DELAY
TX_D3inputTCELL24:IMUX.IMUX.46.DELAY
TX_D4inputTCELL24:IMUX.IMUX.14.DELAY
TX_D5inputTCELL24:IMUX.IMUX.47.DELAY
TX_D6inputTCELL24:IMUX.IMUX.15.DELAY
TX_D7inputTCELL25:IMUX.IMUX.16.DELAY
TX_EN_VTCinputTCELL25:IMUX.BYP.15
TX_INCinputTCELL25:IMUX.BYP.14
TX_LDinputTCELL25:IMUX.BYP.13
TX_TinputTCELL24:IMUX.IMUX.40.DELAY
TX_T_OUToutputTCELL24:OUT.8.TMIN

Bel BITSLICE22

ultrascale XIPHY bel BITSLICE22
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL26:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL28:IMUX.BYP.7
PHY2CLB_FIFO_EMPTYoutputTCELL27:OUT.4.TMIN
RX_CE_IDELAYinputTCELL28:IMUX.BYP.6
RX_CE_IFDinputTCELL26:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL26:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1inputTCELL26:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2inputTCELL26:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3inputTCELL26:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4inputTCELL26:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5inputTCELL26:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6inputTCELL26:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7inputTCELL27:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8inputTCELL27:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0outputTCELL27:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL27:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL27:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL27:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL27:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL27:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL27:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL27:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL27:OUT.31.TMIN
RX_DATAIN1inputTCELL26:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL27:IMUX.BYP.15
RX_INCinputTCELL27:IMUX.BYP.14
RX_LDinputTCELL27:IMUX.BYP.13
RX_Q0outputTCELL27:OUT.5.TMIN
RX_Q1outputTCELL27:OUT.6.TMIN
RX_Q2outputTCELL27:OUT.7.TMIN
RX_Q3outputTCELL27:OUT.8.TMIN
RX_Q4outputTCELL27:OUT.9.TMIN
RX_Q5outputTCELL27:OUT.10.TMIN
RX_Q6outputTCELL27:OUT.11.TMIN
RX_Q7outputTCELL27:OUT.12.TMIN
TX_CE_ODELAYinputTCELL27:IMUX.BYP.12
TX_CE_OFDinputTCELL26:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL26:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL26:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL26:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL26:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL26:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL26:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL26:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL26:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8inputTCELL26:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0outputTCELL27:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL27:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL27:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL27:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL27:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL27:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL27:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL27:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL27:OUT.21.TMIN
TX_D0inputTCELL26:IMUX.IMUX.7.DELAY
TX_D1inputTCELL26:IMUX.IMUX.32.DELAY
TX_D2inputTCELL26:IMUX.IMUX.33.DELAY
TX_D3inputTCELL26:IMUX.IMUX.34.DELAY
TX_D4inputTCELL26:IMUX.IMUX.8.DELAY
TX_D5inputTCELL26:IMUX.IMUX.35.DELAY
TX_D6inputTCELL26:IMUX.IMUX.9.DELAY
TX_D7inputTCELL26:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL27:IMUX.BYP.11
TX_INCinputTCELL27:IMUX.BYP.10
TX_LDinputTCELL27:IMUX.BYP.9
TX_TinputTCELL26:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL25:OUT.8.TMIN

Bel BITSLICE23

ultrascale XIPHY bel BITSLICE23
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL27:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INTinputTCELL29:IMUX.BYP.6
PHY2CLB_FIFO_EMPTYoutputTCELL28:OUT.4.TMIN
RX_CE_IDELAYinputTCELL28:IMUX.BYP.15
RX_CE_IFDinputTCELL27:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0inputTCELL27:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL27:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL27:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL27:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL27:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL27:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL27:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL27:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL27:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL28:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL28:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL28:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL28:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL28:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL28:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL28:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL28:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL28:OUT.31.TMIN
RX_DATAIN1inputTCELL27:IMUX.IMUX.21.DELAY
RX_EN_VTCinputTCELL28:IMUX.BYP.14
RX_INCinputTCELL28:IMUX.BYP.13
RX_LDinputTCELL28:IMUX.BYP.12
RX_Q0outputTCELL28:OUT.5.TMIN
RX_Q1outputTCELL28:OUT.6.TMIN
RX_Q2outputTCELL28:OUT.7.TMIN
RX_Q3outputTCELL28:OUT.8.TMIN
RX_Q4outputTCELL28:OUT.9.TMIN
RX_Q5outputTCELL28:OUT.10.TMIN
RX_Q6outputTCELL28:OUT.11.TMIN
RX_Q7outputTCELL28:OUT.12.TMIN
TX_CE_ODELAYinputTCELL28:IMUX.BYP.11
TX_CE_OFDinputTCELL27:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0inputTCELL27:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1inputTCELL27:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2inputTCELL27:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3inputTCELL27:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4inputTCELL27:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5inputTCELL27:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6inputTCELL27:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7inputTCELL27:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8inputTCELL27:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0outputTCELL28:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL28:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL28:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL28:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL28:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL28:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL28:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL28:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL28:OUT.21.TMIN
TX_D0inputTCELL27:IMUX.IMUX.28.DELAY
TX_D1inputTCELL27:IMUX.IMUX.27.DELAY
TX_D2inputTCELL27:IMUX.IMUX.26.DELAY
TX_D3inputTCELL27:IMUX.IMUX.25.DELAY
TX_D4inputTCELL27:IMUX.IMUX.24.DELAY
TX_D5inputTCELL27:IMUX.IMUX.23.DELAY
TX_D6inputTCELL27:IMUX.IMUX.29.DELAY
TX_D7inputTCELL27:IMUX.IMUX.30.DELAY
TX_EN_VTCinputTCELL28:IMUX.BYP.10
TX_INCinputTCELL28:IMUX.BYP.9
TX_LDinputTCELL28:IMUX.BYP.8
TX_TinputTCELL27:IMUX.IMUX.18.DELAY
TX_T_OUToutputTCELL26:OUT.8.TMIN

Bel BITSLICE24

ultrascale XIPHY bel BITSLICE24
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL27:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INTinputTCELL29:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL29:OUT.4.TMIN
RX_CE_IDELAYinputTCELL29:IMUX.BYP.14
RX_CE_IFDinputTCELL27:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0inputTCELL29:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1inputTCELL29:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2inputTCELL29:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL29:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL29:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5inputTCELL29:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6inputTCELL29:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7inputTCELL29:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL29:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0outputTCELL29:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL29:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL29:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL29:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL29:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL29:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL29:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL29:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL29:OUT.31.TMIN
RX_DATAIN1inputTCELL27:IMUX.IMUX.44.DELAY
RX_EN_VTCinputTCELL29:IMUX.BYP.13
RX_INCinputTCELL29:IMUX.BYP.12
RX_LDinputTCELL29:IMUX.BYP.11
RX_Q0outputTCELL29:OUT.5.TMIN
RX_Q1outputTCELL29:OUT.6.TMIN
RX_Q2outputTCELL29:OUT.7.TMIN
RX_Q3outputTCELL29:OUT.8.TMIN
RX_Q4outputTCELL29:OUT.9.TMIN
RX_Q5outputTCELL29:OUT.10.TMIN
RX_Q6outputTCELL29:OUT.11.TMIN
RX_Q7outputTCELL29:OUT.12.TMIN
TX_CE_ODELAYinputTCELL29:IMUX.BYP.10
TX_CE_OFDinputTCELL27:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0inputTCELL28:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL28:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2inputTCELL28:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3inputTCELL28:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4inputTCELL28:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5inputTCELL28:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6inputTCELL28:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7inputTCELL29:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8inputTCELL29:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0outputTCELL29:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL29:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL29:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL29:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL29:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL29:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL29:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL29:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL29:OUT.21.TMIN
TX_D0inputTCELL27:IMUX.IMUX.46.DELAY
TX_D1inputTCELL27:IMUX.IMUX.14.DELAY
TX_D2inputTCELL27:IMUX.IMUX.47.DELAY
TX_D3inputTCELL27:IMUX.IMUX.15.DELAY
TX_D4inputTCELL28:IMUX.IMUX.16.DELAY
TX_D5inputTCELL28:IMUX.IMUX.6.DELAY
TX_D6inputTCELL28:IMUX.IMUX.7.DELAY
TX_D7inputTCELL28:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL29:IMUX.BYP.9
TX_INCinputTCELL29:IMUX.BYP.8
TX_LDinputTCELL29:IMUX.BYP.7
TX_TinputTCELL27:IMUX.IMUX.12.DELAY
TX_T_OUToutputTCELL26:OUT.31.TMIN

Bel BITSLICE25

ultrascale XIPHY bel BITSLICE25
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL22:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INTinputTCELL23:IMUX.BYP.13
PHY2CLB_FIFO_EMPTYoutputTCELL22:OUT.18.TMIN
RX_CE_IDELAYinputTCELL23:IMUX.BYP.12
RX_CE_IFDinputTCELL22:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0inputTCELL23:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL23:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL23:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL23:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL23:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL23:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL23:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL23:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL23:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL23:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL23:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL23:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL23:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL23:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL23:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL23:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL23:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL23:OUT.17.TMIN
RX_DATAIN1inputTCELL22:IMUX.IMUX.9.DELAY
RX_EN_VTCinputTCELL23:IMUX.BYP.11
RX_INCinputTCELL23:IMUX.BYP.10
RX_LDinputTCELL23:IMUX.BYP.9
RX_Q0outputTCELL22:OUT.19.TMIN
RX_Q1outputTCELL22:OUT.20.TMIN
RX_Q2outputTCELL22:OUT.21.TMIN
RX_Q3outputTCELL22:OUT.22.TMIN
RX_Q4outputTCELL22:OUT.23.TMIN
RX_Q5outputTCELL22:OUT.24.TMIN
RX_Q6outputTCELL22:OUT.25.TMIN
RX_Q7outputTCELL22:OUT.26.TMIN
TX_CE_ODELAYinputTCELL23:IMUX.BYP.8
TX_CE_OFDinputTCELL22:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0inputTCELL22:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1inputTCELL22:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2inputTCELL22:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3inputTCELL22:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4inputTCELL22:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5inputTCELL22:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6inputTCELL22:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7inputTCELL22:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8inputTCELL22:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL22:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL22:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL22:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL22:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL22:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL23:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL23:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL23:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL23:OUT.7.TMIN
TX_D0inputTCELL22:IMUX.IMUX.37.DELAY
TX_D1inputTCELL22:IMUX.IMUX.38.DELAY
TX_D2inputTCELL22:IMUX.IMUX.10.DELAY
TX_D3inputTCELL22:IMUX.IMUX.39.DELAY
TX_D4inputTCELL22:IMUX.IMUX.11.DELAY
TX_D5inputTCELL22:IMUX.IMUX.40.DELAY
TX_D6inputTCELL22:IMUX.IMUX.41.DELAY
TX_D7inputTCELL22:IMUX.IMUX.42.DELAY
TX_EN_VTCinputTCELL23:IMUX.BYP.7
TX_INCinputTCELL23:IMUX.BYP.6
TX_LDinputTCELL22:IMUX.BYP.15
TX_TinputTCELL22:IMUX.IMUX.34.DELAY
TX_T_OUToutputTCELL27:OUT.22.TMIN

Bel BITSLICE26

ultrascale XIPHY bel BITSLICE26
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL30:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INTinputTCELL30:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL30:OUT.4.TMIN
RX_CE_IDELAYinputTCELL30:IMUX.BYP.14
RX_CE_IFDinputTCELL30:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0inputTCELL32:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL32:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL32:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL32:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL32:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL32:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL32:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL32:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL32:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL30:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL30:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL30:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL30:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL30:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL30:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL30:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL30:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL30:OUT.31.TMIN
RX_DATAIN1inputTCELL30:IMUX.IMUX.8.DELAY
RX_EN_VTCinputTCELL30:IMUX.BYP.13
RX_INCinputTCELL30:IMUX.BYP.12
RX_LDinputTCELL30:IMUX.BYP.11
RX_Q0outputTCELL30:OUT.5.TMIN
RX_Q1outputTCELL30:OUT.6.TMIN
RX_Q2outputTCELL30:OUT.7.TMIN
RX_Q3outputTCELL30:OUT.8.TMIN
RX_Q4outputTCELL30:OUT.9.TMIN
RX_Q5outputTCELL30:OUT.10.TMIN
RX_Q6outputTCELL30:OUT.11.TMIN
RX_Q7outputTCELL30:OUT.12.TMIN
TX_CE_ODELAYinputTCELL30:IMUX.BYP.10
TX_CE_OFDinputTCELL30:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0inputTCELL31:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1inputTCELL31:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2inputTCELL31:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3inputTCELL31:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4inputTCELL31:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL31:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6inputTCELL31:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7inputTCELL31:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8inputTCELL31:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL30:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL30:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL30:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL30:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL30:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL30:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL30:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL30:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL30:OUT.21.TMIN
TX_D0inputTCELL31:IMUX.IMUX.16.DELAY
TX_D1inputTCELL31:IMUX.IMUX.6.DELAY
TX_D2inputTCELL30:IMUX.IMUX.15.DELAY
TX_D3inputTCELL30:IMUX.IMUX.14.DELAY
TX_D4inputTCELL30:IMUX.IMUX.13.DELAY
TX_D5inputTCELL30:IMUX.IMUX.12.DELAY
TX_D6inputTCELL30:IMUX.IMUX.11.DELAY
TX_D7inputTCELL30:IMUX.IMUX.10.DELAY
TX_EN_VTCinputTCELL30:IMUX.BYP.9
TX_INCinputTCELL30:IMUX.BYP.8
TX_LDinputTCELL30:IMUX.BYP.7
TX_TinputTCELL30:IMUX.IMUX.16.DELAY
TX_T_OUToutputTCELL30:OUT.22.TMIN

Bel BITSLICE27

ultrascale XIPHY bel BITSLICE27
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL32:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INTinputTCELL31:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL31:OUT.4.TMIN
RX_CE_IDELAYinputTCELL31:IMUX.BYP.14
RX_CE_IFDinputTCELL32:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL32:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1inputTCELL32:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2inputTCELL32:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3inputTCELL32:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4inputTCELL32:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5inputTCELL32:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6inputTCELL32:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7inputTCELL32:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8inputTCELL32:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0outputTCELL31:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL31:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL31:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL31:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL31:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL31:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL31:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL31:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL31:OUT.31.TMIN
RX_DATAIN1inputTCELL32:IMUX.IMUX.28.DELAY
RX_EN_VTCinputTCELL31:IMUX.BYP.13
RX_INCinputTCELL31:IMUX.BYP.12
RX_LDinputTCELL31:IMUX.BYP.11
RX_Q0outputTCELL31:OUT.5.TMIN
RX_Q1outputTCELL31:OUT.6.TMIN
RX_Q2outputTCELL31:OUT.7.TMIN
RX_Q3outputTCELL31:OUT.8.TMIN
RX_Q4outputTCELL31:OUT.9.TMIN
RX_Q5outputTCELL31:OUT.10.TMIN
RX_Q6outputTCELL31:OUT.11.TMIN
RX_Q7outputTCELL31:OUT.12.TMIN
TX_CE_ODELAYinputTCELL31:IMUX.BYP.10
TX_CE_OFDinputTCELL32:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL32:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1inputTCELL32:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2inputTCELL32:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3inputTCELL32:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4inputTCELL32:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5inputTCELL32:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6inputTCELL32:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7inputTCELL32:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8inputTCELL32:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0outputTCELL31:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL31:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL31:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL31:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL31:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL31:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL31:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL31:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL31:OUT.21.TMIN
TX_D0inputTCELL32:IMUX.IMUX.30.DELAY
TX_D1inputTCELL32:IMUX.IMUX.6.DELAY
TX_D2inputTCELL32:IMUX.IMUX.31.DELAY
TX_D3inputTCELL32:IMUX.IMUX.7.DELAY
TX_D4inputTCELL32:IMUX.IMUX.32.DELAY
TX_D5inputTCELL32:IMUX.IMUX.33.DELAY
TX_D6inputTCELL32:IMUX.IMUX.34.DELAY
TX_D7inputTCELL32:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL31:IMUX.BYP.9
TX_INCinputTCELL31:IMUX.BYP.8
TX_LDinputTCELL31:IMUX.BYP.7
TX_TinputTCELL32:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL31:OUT.22.TMIN

Bel BITSLICE28

ultrascale XIPHY bel BITSLICE28
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL33:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INTinputTCELL32:IMUX.BYP.14
PHY2CLB_FIFO_EMPTYoutputTCELL32:OUT.4.TMIN
RX_CE_IDELAYinputTCELL32:IMUX.BYP.13
RX_CE_IFDinputTCELL33:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0inputTCELL33:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL33:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL33:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL33:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL33:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL33:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL33:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL33:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL33:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL32:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL32:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL32:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL32:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL32:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL32:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL32:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL32:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL32:OUT.31.TMIN
RX_DATAIN1inputTCELL33:IMUX.IMUX.17.DELAY
RX_EN_VTCinputTCELL32:IMUX.BYP.12
RX_INCinputTCELL32:IMUX.BYP.11
RX_LDinputTCELL32:IMUX.BYP.10
RX_Q0outputTCELL32:OUT.5.TMIN
RX_Q1outputTCELL32:OUT.6.TMIN
RX_Q2outputTCELL32:OUT.7.TMIN
RX_Q3outputTCELL32:OUT.8.TMIN
RX_Q4outputTCELL32:OUT.9.TMIN
RX_Q5outputTCELL32:OUT.10.TMIN
RX_Q6outputTCELL32:OUT.11.TMIN
RX_Q7outputTCELL32:OUT.12.TMIN
TX_CE_ODELAYinputTCELL32:IMUX.BYP.9
TX_CE_OFDinputTCELL32:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0inputTCELL33:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL33:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL33:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL33:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL33:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL33:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL33:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL33:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL33:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL32:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL32:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL32:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL32:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL32:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL32:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL32:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL32:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL32:OUT.21.TMIN
TX_D0inputTCELL33:IMUX.IMUX.20.DELAY
TX_D1inputTCELL33:IMUX.IMUX.21.DELAY
TX_D2inputTCELL33:IMUX.IMUX.22.DELAY
TX_D3inputTCELL33:IMUX.IMUX.23.DELAY
TX_D4inputTCELL33:IMUX.IMUX.24.DELAY
TX_D5inputTCELL33:IMUX.IMUX.25.DELAY
TX_D6inputTCELL33:IMUX.IMUX.26.DELAY
TX_D7inputTCELL33:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL32:IMUX.BYP.8
TX_INCinputTCELL32:IMUX.BYP.7
TX_LDinputTCELL32:IMUX.BYP.6
TX_TinputTCELL32:IMUX.IMUX.47.DELAY
TX_T_OUToutputTCELL32:OUT.22.TMIN

Bel BITSLICE29

ultrascale XIPHY bel BITSLICE29
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL34:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INTinputTCELL34:IMUX.BYP.10
PHY2CLB_FIFO_EMPTYoutputTCELL33:OUT.18.TMIN
RX_CE_IDELAYinputTCELL34:IMUX.BYP.9
RX_CE_IFDinputTCELL34:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0inputTCELL35:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1inputTCELL35:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2inputTCELL35:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3inputTCELL35:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4inputTCELL35:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5inputTCELL35:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6inputTCELL35:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7inputTCELL35:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8inputTCELL35:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0outputTCELL34:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL34:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL34:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL34:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL34:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL34:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL34:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL34:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL34:OUT.17.TMIN
RX_DATAIN1inputTCELL34:IMUX.IMUX.37.DELAY
RX_EN_VTCinputTCELL34:IMUX.BYP.8
RX_INCinputTCELL34:IMUX.BYP.7
RX_LDinputTCELL34:IMUX.BYP.6
RX_Q0outputTCELL33:OUT.19.TMIN
RX_Q1outputTCELL33:OUT.20.TMIN
RX_Q2outputTCELL33:OUT.21.TMIN
RX_Q3outputTCELL33:OUT.22.TMIN
RX_Q4outputTCELL33:OUT.23.TMIN
RX_Q5outputTCELL33:OUT.24.TMIN
RX_Q6outputTCELL33:OUT.25.TMIN
RX_Q7outputTCELL33:OUT.26.TMIN
TX_CE_ODELAYinputTCELL33:IMUX.BYP.15
TX_CE_OFDinputTCELL34:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0inputTCELL34:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1inputTCELL34:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2inputTCELL34:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3inputTCELL34:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4inputTCELL34:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5inputTCELL34:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6inputTCELL35:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7inputTCELL35:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8inputTCELL35:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0outputTCELL33:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL33:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL33:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL33:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL33:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL34:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL34:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL34:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL34:OUT.7.TMIN
TX_D0inputTCELL34:IMUX.IMUX.10.DELAY
TX_D1inputTCELL34:IMUX.IMUX.39.DELAY
TX_D2inputTCELL34:IMUX.IMUX.11.DELAY
TX_D3inputTCELL34:IMUX.IMUX.40.DELAY
TX_D4inputTCELL34:IMUX.IMUX.41.DELAY
TX_D5inputTCELL34:IMUX.IMUX.42.DELAY
TX_D6inputTCELL34:IMUX.IMUX.12.DELAY
TX_D7inputTCELL34:IMUX.IMUX.13.DELAY
TX_EN_VTCinputTCELL33:IMUX.BYP.14
TX_INCinputTCELL33:IMUX.BYP.13
TX_LDinputTCELL33:IMUX.BYP.12
TX_TinputTCELL34:IMUX.IMUX.35.DELAY
TX_T_OUToutputTCELL33:OUT.13.TMIN

Bel BITSLICE30

ultrascale XIPHY bel BITSLICE30
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL35:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL35:IMUX.BYP.9
PHY2CLB_FIFO_EMPTYoutputTCELL34:OUT.18.TMIN
RX_CE_IDELAYinputTCELL35:IMUX.BYP.8
RX_CE_IFDinputTCELL35:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL35:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1inputTCELL35:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2inputTCELL35:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3inputTCELL35:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4inputTCELL35:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5inputTCELL35:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6inputTCELL35:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7inputTCELL35:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8inputTCELL36:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0outputTCELL35:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL35:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL35:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL35:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL35:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL35:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL35:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL35:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL35:OUT.17.TMIN
RX_DATAIN1inputTCELL35:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL35:IMUX.BYP.7
RX_INCinputTCELL35:IMUX.BYP.6
RX_LDinputTCELL34:IMUX.BYP.15
RX_Q0outputTCELL34:OUT.19.TMIN
RX_Q1outputTCELL34:OUT.20.TMIN
RX_Q2outputTCELL34:OUT.21.TMIN
RX_Q3outputTCELL34:OUT.22.TMIN
RX_Q4outputTCELL34:OUT.23.TMIN
RX_Q5outputTCELL34:OUT.24.TMIN
RX_Q6outputTCELL34:OUT.25.TMIN
RX_Q7outputTCELL34:OUT.26.TMIN
TX_CE_ODELAYinputTCELL34:IMUX.BYP.14
TX_CE_OFDinputTCELL35:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL35:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL35:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL35:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL35:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL35:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL35:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL35:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL35:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8inputTCELL35:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0outputTCELL34:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL34:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL34:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL34:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL34:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL35:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL35:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL35:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL35:OUT.7.TMIN
TX_D0inputTCELL35:IMUX.IMUX.7.DELAY
TX_D1inputTCELL35:IMUX.IMUX.32.DELAY
TX_D2inputTCELL35:IMUX.IMUX.33.DELAY
TX_D3inputTCELL35:IMUX.IMUX.34.DELAY
TX_D4inputTCELL35:IMUX.IMUX.8.DELAY
TX_D5inputTCELL35:IMUX.IMUX.35.DELAY
TX_D6inputTCELL35:IMUX.IMUX.9.DELAY
TX_D7inputTCELL35:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL34:IMUX.BYP.13
TX_INCinputTCELL34:IMUX.BYP.12
TX_LDinputTCELL34:IMUX.BYP.11
TX_TinputTCELL35:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL34:OUT.8.TMIN

Bel BITSLICE31

ultrascale XIPHY bel BITSLICE31
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL36:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INTinputTCELL36:IMUX.BYP.8
PHY2CLB_FIFO_EMPTYoutputTCELL35:OUT.18.TMIN
RX_CE_IDELAYinputTCELL36:IMUX.BYP.7
RX_CE_IFDinputTCELL36:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0inputTCELL36:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL36:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL36:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL36:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL36:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL36:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL36:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL36:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL36:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL36:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL36:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL36:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL36:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL36:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL36:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL36:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL36:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL36:OUT.17.TMIN
RX_DATAIN1inputTCELL36:IMUX.IMUX.20.DELAY
RX_EN_VTCinputTCELL36:IMUX.BYP.6
RX_INCinputTCELL35:IMUX.BYP.15
RX_LDinputTCELL35:IMUX.BYP.14
RX_Q0outputTCELL35:OUT.19.TMIN
RX_Q1outputTCELL35:OUT.20.TMIN
RX_Q2outputTCELL35:OUT.21.TMIN
RX_Q3outputTCELL35:OUT.22.TMIN
RX_Q4outputTCELL35:OUT.23.TMIN
RX_Q5outputTCELL35:OUT.24.TMIN
RX_Q6outputTCELL35:OUT.25.TMIN
RX_Q7outputTCELL35:OUT.26.TMIN
TX_CE_ODELAYinputTCELL35:IMUX.BYP.13
TX_CE_OFDinputTCELL36:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0inputTCELL36:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1inputTCELL36:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2inputTCELL36:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3inputTCELL36:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4inputTCELL36:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5inputTCELL36:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6inputTCELL36:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7inputTCELL36:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8inputTCELL36:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0outputTCELL35:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL35:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL35:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL35:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL35:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL36:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL36:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL36:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL36:OUT.7.TMIN
TX_D0inputTCELL36:IMUX.IMUX.22.DELAY
TX_D1inputTCELL36:IMUX.IMUX.23.DELAY
TX_D2inputTCELL36:IMUX.IMUX.24.DELAY
TX_D3inputTCELL36:IMUX.IMUX.25.DELAY
TX_D4inputTCELL36:IMUX.IMUX.26.DELAY
TX_D5inputTCELL36:IMUX.IMUX.27.DELAY
TX_D6inputTCELL36:IMUX.IMUX.28.DELAY
TX_D7inputTCELL36:IMUX.IMUX.29.DELAY
TX_EN_VTCinputTCELL35:IMUX.BYP.12
TX_INCinputTCELL35:IMUX.BYP.11
TX_LDinputTCELL35:IMUX.BYP.10
TX_TinputTCELL36:IMUX.IMUX.17.DELAY
TX_T_OUToutputTCELL35:OUT.8.TMIN

Bel BITSLICE32

ultrascale XIPHY bel BITSLICE32
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL38:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INTinputTCELL39:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL38:OUT.18.TMIN
RX_CE_IDELAYinputTCELL39:IMUX.BYP.11
RX_CE_IFDinputTCELL38:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL38:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1inputTCELL38:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2inputTCELL38:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3inputTCELL38:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4inputTCELL38:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5inputTCELL38:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6inputTCELL38:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7inputTCELL38:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL38:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0outputTCELL39:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL39:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL39:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL39:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL39:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL39:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL39:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL39:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL39:OUT.17.TMIN
RX_DATAIN1inputTCELL38:IMUX.IMUX.29.DELAY
RX_EN_VTCinputTCELL39:IMUX.BYP.10
RX_INCinputTCELL39:IMUX.BYP.9
RX_LDinputTCELL39:IMUX.BYP.8
RX_Q0outputTCELL38:OUT.19.TMIN
RX_Q1outputTCELL38:OUT.20.TMIN
RX_Q2outputTCELL38:OUT.21.TMIN
RX_Q3outputTCELL38:OUT.22.TMIN
RX_Q4outputTCELL38:OUT.23.TMIN
RX_Q5outputTCELL38:OUT.24.TMIN
RX_Q6outputTCELL38:OUT.25.TMIN
RX_Q7outputTCELL38:OUT.26.TMIN
TX_CE_ODELAYinputTCELL39:IMUX.BYP.7
TX_CE_OFDinputTCELL38:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL38:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL38:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2inputTCELL38:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3inputTCELL38:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4inputTCELL38:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5inputTCELL38:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6inputTCELL38:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7inputTCELL38:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8inputTCELL38:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0outputTCELL38:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL38:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL38:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL38:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL38:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL39:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL39:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL39:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL39:OUT.7.TMIN
TX_D0inputTCELL38:IMUX.IMUX.6.DELAY
TX_D1inputTCELL38:IMUX.IMUX.31.DELAY
TX_D2inputTCELL38:IMUX.IMUX.7.DELAY
TX_D3inputTCELL38:IMUX.IMUX.32.DELAY
TX_D4inputTCELL38:IMUX.IMUX.33.DELAY
TX_D5inputTCELL38:IMUX.IMUX.34.DELAY
TX_D6inputTCELL38:IMUX.IMUX.8.DELAY
TX_D7inputTCELL38:IMUX.IMUX.35.DELAY
TX_EN_VTCinputTCELL39:IMUX.BYP.6
TX_INCinputTCELL38:IMUX.BYP.15
TX_LDinputTCELL38:IMUX.BYP.14
TX_TinputTCELL38:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL36:OUT.8.TMIN

Bel BITSLICE33

ultrascale XIPHY bel BITSLICE33
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL39:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INTinputTCELL40:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL39:OUT.18.TMIN
RX_CE_IDELAYinputTCELL40:IMUX.BYP.11
RX_CE_IFDinputTCELL39:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0inputTCELL39:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL39:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL39:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL39:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL39:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL39:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL39:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL39:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL39:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL40:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL40:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL40:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL40:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL40:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL40:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL40:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL40:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL40:OUT.17.TMIN
RX_DATAIN1inputTCELL39:IMUX.IMUX.18.DELAY
RX_EN_VTCinputTCELL40:IMUX.BYP.10
RX_INCinputTCELL40:IMUX.BYP.9
RX_LDinputTCELL40:IMUX.BYP.8
RX_Q0outputTCELL39:OUT.19.TMIN
RX_Q1outputTCELL39:OUT.20.TMIN
RX_Q2outputTCELL39:OUT.21.TMIN
RX_Q3outputTCELL39:OUT.22.TMIN
RX_Q4outputTCELL39:OUT.23.TMIN
RX_Q5outputTCELL39:OUT.24.TMIN
RX_Q6outputTCELL39:OUT.25.TMIN
RX_Q7outputTCELL39:OUT.26.TMIN
TX_CE_ODELAYinputTCELL40:IMUX.BYP.7
TX_CE_OFDinputTCELL39:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0inputTCELL39:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL39:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL39:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL39:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL39:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL39:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL39:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL39:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL39:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL39:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL39:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL39:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL39:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL39:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL40:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL40:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL40:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL40:OUT.7.TMIN
TX_D0inputTCELL39:IMUX.IMUX.20.DELAY
TX_D1inputTCELL39:IMUX.IMUX.21.DELAY
TX_D2inputTCELL39:IMUX.IMUX.22.DELAY
TX_D3inputTCELL39:IMUX.IMUX.23.DELAY
TX_D4inputTCELL39:IMUX.IMUX.24.DELAY
TX_D5inputTCELL39:IMUX.IMUX.25.DELAY
TX_D6inputTCELL39:IMUX.IMUX.26.DELAY
TX_D7inputTCELL39:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL40:IMUX.BYP.6
TX_INCinputTCELL39:IMUX.BYP.15
TX_LDinputTCELL39:IMUX.BYP.14
TX_TinputTCELL38:IMUX.IMUX.15.DELAY
TX_T_OUToutputTCELL38:OUT.8.TMIN

Bel BITSLICE34

ultrascale XIPHY bel BITSLICE34
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL39:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INTinputTCELL41:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL40:OUT.18.TMIN
RX_CE_IDELAYinputTCELL41:IMUX.BYP.11
RX_CE_IFDinputTCELL39:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0inputTCELL40:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1inputTCELL40:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2inputTCELL40:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3inputTCELL40:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4inputTCELL40:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5inputTCELL40:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6inputTCELL40:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7inputTCELL40:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8inputTCELL40:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0outputTCELL41:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL41:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL41:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL41:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL41:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL41:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL41:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL41:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL41:OUT.17.TMIN
RX_DATAIN1inputTCELL39:IMUX.IMUX.12.DELAY
RX_EN_VTCinputTCELL41:IMUX.BYP.10
RX_INCinputTCELL41:IMUX.BYP.9
RX_LDinputTCELL41:IMUX.BYP.8
RX_Q0outputTCELL40:OUT.19.TMIN
RX_Q1outputTCELL40:OUT.20.TMIN
RX_Q2outputTCELL40:OUT.21.TMIN
RX_Q3outputTCELL40:OUT.22.TMIN
RX_Q4outputTCELL40:OUT.23.TMIN
RX_Q5outputTCELL40:OUT.24.TMIN
RX_Q6outputTCELL40:OUT.25.TMIN
RX_Q7outputTCELL40:OUT.26.TMIN
TX_CE_ODELAYinputTCELL41:IMUX.BYP.6
TX_CE_OFDinputTCELL39:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0inputTCELL40:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1inputTCELL40:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2inputTCELL40:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3inputTCELL40:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4inputTCELL40:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5inputTCELL40:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6inputTCELL40:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7inputTCELL40:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8inputTCELL40:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0outputTCELL40:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL40:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL40:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL40:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL40:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL41:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL41:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL41:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL41:OUT.7.TMIN
TX_D0inputTCELL39:IMUX.IMUX.13.DELAY
TX_D1inputTCELL39:IMUX.IMUX.44.DELAY
TX_D2inputTCELL39:IMUX.IMUX.45.DELAY
TX_D3inputTCELL39:IMUX.IMUX.46.DELAY
TX_D4inputTCELL39:IMUX.IMUX.14.DELAY
TX_D5inputTCELL39:IMUX.IMUX.47.DELAY
TX_D6inputTCELL39:IMUX.IMUX.15.DELAY
TX_D7inputTCELL40:IMUX.IMUX.16.DELAY
TX_EN_VTCinputTCELL40:IMUX.BYP.15
TX_INCinputTCELL40:IMUX.BYP.14
TX_LDinputTCELL40:IMUX.BYP.13
TX_TinputTCELL39:IMUX.IMUX.40.DELAY
TX_T_OUToutputTCELL39:OUT.8.TMIN

Bel BITSLICE35

ultrascale XIPHY bel BITSLICE35
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL41:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL43:IMUX.BYP.7
PHY2CLB_FIFO_EMPTYoutputTCELL42:OUT.4.TMIN
RX_CE_IDELAYinputTCELL43:IMUX.BYP.6
RX_CE_IFDinputTCELL41:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL41:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1inputTCELL41:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2inputTCELL41:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3inputTCELL41:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4inputTCELL41:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5inputTCELL41:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6inputTCELL41:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7inputTCELL42:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8inputTCELL42:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0outputTCELL42:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL42:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL42:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL42:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL42:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL42:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL42:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL42:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL42:OUT.31.TMIN
RX_DATAIN1inputTCELL41:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL42:IMUX.BYP.15
RX_INCinputTCELL42:IMUX.BYP.14
RX_LDinputTCELL42:IMUX.BYP.13
RX_Q0outputTCELL42:OUT.5.TMIN
RX_Q1outputTCELL42:OUT.6.TMIN
RX_Q2outputTCELL42:OUT.7.TMIN
RX_Q3outputTCELL42:OUT.8.TMIN
RX_Q4outputTCELL42:OUT.9.TMIN
RX_Q5outputTCELL42:OUT.10.TMIN
RX_Q6outputTCELL42:OUT.11.TMIN
RX_Q7outputTCELL42:OUT.12.TMIN
TX_CE_ODELAYinputTCELL42:IMUX.BYP.12
TX_CE_OFDinputTCELL41:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL41:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL41:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL41:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL41:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL41:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL41:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL41:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL41:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8inputTCELL41:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0outputTCELL42:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL42:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL42:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL42:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL42:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL42:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL42:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL42:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL42:OUT.21.TMIN
TX_D0inputTCELL41:IMUX.IMUX.7.DELAY
TX_D1inputTCELL41:IMUX.IMUX.32.DELAY
TX_D2inputTCELL41:IMUX.IMUX.33.DELAY
TX_D3inputTCELL41:IMUX.IMUX.34.DELAY
TX_D4inputTCELL41:IMUX.IMUX.8.DELAY
TX_D5inputTCELL41:IMUX.IMUX.35.DELAY
TX_D6inputTCELL41:IMUX.IMUX.9.DELAY
TX_D7inputTCELL41:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL42:IMUX.BYP.11
TX_INCinputTCELL42:IMUX.BYP.10
TX_LDinputTCELL42:IMUX.BYP.9
TX_TinputTCELL41:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL40:OUT.8.TMIN

Bel BITSLICE36

ultrascale XIPHY bel BITSLICE36
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL42:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INTinputTCELL44:IMUX.BYP.6
PHY2CLB_FIFO_EMPTYoutputTCELL43:OUT.4.TMIN
RX_CE_IDELAYinputTCELL43:IMUX.BYP.15
RX_CE_IFDinputTCELL42:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0inputTCELL42:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL42:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL42:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL42:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL42:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL42:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL42:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL42:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL42:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL43:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL43:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL43:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL43:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL43:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL43:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL43:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL43:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL43:OUT.31.TMIN
RX_DATAIN1inputTCELL42:IMUX.IMUX.21.DELAY
RX_EN_VTCinputTCELL43:IMUX.BYP.14
RX_INCinputTCELL43:IMUX.BYP.13
RX_LDinputTCELL43:IMUX.BYP.12
RX_Q0outputTCELL43:OUT.5.TMIN
RX_Q1outputTCELL43:OUT.6.TMIN
RX_Q2outputTCELL43:OUT.7.TMIN
RX_Q3outputTCELL43:OUT.8.TMIN
RX_Q4outputTCELL43:OUT.9.TMIN
RX_Q5outputTCELL43:OUT.10.TMIN
RX_Q6outputTCELL43:OUT.11.TMIN
RX_Q7outputTCELL43:OUT.12.TMIN
TX_CE_ODELAYinputTCELL43:IMUX.BYP.11
TX_CE_OFDinputTCELL42:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0inputTCELL42:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1inputTCELL42:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2inputTCELL42:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3inputTCELL42:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4inputTCELL42:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5inputTCELL42:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6inputTCELL42:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7inputTCELL42:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8inputTCELL42:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0outputTCELL43:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL43:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL43:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL43:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL43:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL43:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL43:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL43:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL43:OUT.21.TMIN
TX_D0inputTCELL42:IMUX.IMUX.28.DELAY
TX_D1inputTCELL42:IMUX.IMUX.27.DELAY
TX_D2inputTCELL42:IMUX.IMUX.26.DELAY
TX_D3inputTCELL42:IMUX.IMUX.25.DELAY
TX_D4inputTCELL42:IMUX.IMUX.24.DELAY
TX_D5inputTCELL42:IMUX.IMUX.23.DELAY
TX_D6inputTCELL42:IMUX.IMUX.29.DELAY
TX_D7inputTCELL42:IMUX.IMUX.30.DELAY
TX_EN_VTCinputTCELL43:IMUX.BYP.10
TX_INCinputTCELL43:IMUX.BYP.9
TX_LDinputTCELL43:IMUX.BYP.8
TX_TinputTCELL42:IMUX.IMUX.18.DELAY
TX_T_OUToutputTCELL41:OUT.8.TMIN

Bel BITSLICE37

ultrascale XIPHY bel BITSLICE37
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL42:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INTinputTCELL44:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL44:OUT.4.TMIN
RX_CE_IDELAYinputTCELL44:IMUX.BYP.14
RX_CE_IFDinputTCELL42:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0inputTCELL44:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1inputTCELL44:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2inputTCELL44:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL44:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL44:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5inputTCELL44:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6inputTCELL44:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7inputTCELL44:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL44:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0outputTCELL44:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL44:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL44:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL44:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL44:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL44:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL44:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL44:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL44:OUT.31.TMIN
RX_DATAIN1inputTCELL42:IMUX.IMUX.44.DELAY
RX_EN_VTCinputTCELL44:IMUX.BYP.13
RX_INCinputTCELL44:IMUX.BYP.12
RX_LDinputTCELL44:IMUX.BYP.11
RX_Q0outputTCELL44:OUT.5.TMIN
RX_Q1outputTCELL44:OUT.6.TMIN
RX_Q2outputTCELL44:OUT.7.TMIN
RX_Q3outputTCELL44:OUT.8.TMIN
RX_Q4outputTCELL44:OUT.9.TMIN
RX_Q5outputTCELL44:OUT.10.TMIN
RX_Q6outputTCELL44:OUT.11.TMIN
RX_Q7outputTCELL44:OUT.12.TMIN
TX_CE_ODELAYinputTCELL44:IMUX.BYP.10
TX_CE_OFDinputTCELL42:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0inputTCELL43:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL43:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2inputTCELL43:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3inputTCELL43:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4inputTCELL43:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5inputTCELL43:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6inputTCELL43:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7inputTCELL44:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8inputTCELL44:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0outputTCELL44:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL44:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL44:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL44:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL44:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL44:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL44:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL44:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL44:OUT.21.TMIN
TX_D0inputTCELL42:IMUX.IMUX.46.DELAY
TX_D1inputTCELL42:IMUX.IMUX.14.DELAY
TX_D2inputTCELL42:IMUX.IMUX.47.DELAY
TX_D3inputTCELL42:IMUX.IMUX.15.DELAY
TX_D4inputTCELL43:IMUX.IMUX.16.DELAY
TX_D5inputTCELL43:IMUX.IMUX.6.DELAY
TX_D6inputTCELL43:IMUX.IMUX.7.DELAY
TX_D7inputTCELL43:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL44:IMUX.BYP.9
TX_INCinputTCELL44:IMUX.BYP.8
TX_LDinputTCELL44:IMUX.BYP.7
TX_TinputTCELL42:IMUX.IMUX.12.DELAY
TX_T_OUToutputTCELL41:OUT.31.TMIN

Bel BITSLICE38

ultrascale XIPHY bel BITSLICE38
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL37:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INTinputTCELL38:IMUX.BYP.13
PHY2CLB_FIFO_EMPTYoutputTCELL37:OUT.18.TMIN
RX_CE_IDELAYinputTCELL38:IMUX.BYP.12
RX_CE_IFDinputTCELL37:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0inputTCELL38:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL38:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL38:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL38:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL38:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL38:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL38:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL38:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL38:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL38:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL38:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL38:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL38:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL38:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL38:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL38:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL38:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL38:OUT.17.TMIN
RX_DATAIN1inputTCELL37:IMUX.IMUX.9.DELAY
RX_EN_VTCinputTCELL38:IMUX.BYP.11
RX_INCinputTCELL38:IMUX.BYP.10
RX_LDinputTCELL38:IMUX.BYP.9
RX_Q0outputTCELL37:OUT.19.TMIN
RX_Q1outputTCELL37:OUT.20.TMIN
RX_Q2outputTCELL37:OUT.21.TMIN
RX_Q3outputTCELL37:OUT.22.TMIN
RX_Q4outputTCELL37:OUT.23.TMIN
RX_Q5outputTCELL37:OUT.24.TMIN
RX_Q6outputTCELL37:OUT.25.TMIN
RX_Q7outputTCELL37:OUT.26.TMIN
TX_CE_ODELAYinputTCELL38:IMUX.BYP.8
TX_CE_OFDinputTCELL37:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0inputTCELL37:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1inputTCELL37:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2inputTCELL37:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3inputTCELL37:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4inputTCELL37:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5inputTCELL37:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6inputTCELL37:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7inputTCELL37:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8inputTCELL37:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL37:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL37:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL37:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL37:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL37:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL38:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL38:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL38:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL38:OUT.7.TMIN
TX_D0inputTCELL37:IMUX.IMUX.37.DELAY
TX_D1inputTCELL37:IMUX.IMUX.38.DELAY
TX_D2inputTCELL37:IMUX.IMUX.10.DELAY
TX_D3inputTCELL37:IMUX.IMUX.39.DELAY
TX_D4inputTCELL37:IMUX.IMUX.11.DELAY
TX_D5inputTCELL37:IMUX.IMUX.40.DELAY
TX_D6inputTCELL37:IMUX.IMUX.41.DELAY
TX_D7inputTCELL37:IMUX.IMUX.42.DELAY
TX_EN_VTCinputTCELL38:IMUX.BYP.7
TX_INCinputTCELL38:IMUX.BYP.6
TX_LDinputTCELL37:IMUX.BYP.15
TX_TinputTCELL37:IMUX.IMUX.34.DELAY
TX_T_OUToutputTCELL42:OUT.22.TMIN

Bel BITSLICE39

ultrascale XIPHY bel BITSLICE39
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL45:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INTinputTCELL45:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL45:OUT.4.TMIN
RX_CE_IDELAYinputTCELL45:IMUX.BYP.14
RX_CE_IFDinputTCELL45:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0inputTCELL47:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL47:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL47:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL47:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL47:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL47:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL47:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL47:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL47:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL45:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL45:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL45:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL45:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL45:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL45:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL45:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL45:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL45:OUT.31.TMIN
RX_DATAIN1inputTCELL45:IMUX.IMUX.8.DELAY
RX_EN_VTCinputTCELL45:IMUX.BYP.13
RX_INCinputTCELL45:IMUX.BYP.12
RX_LDinputTCELL45:IMUX.BYP.11
RX_Q0outputTCELL45:OUT.5.TMIN
RX_Q1outputTCELL45:OUT.6.TMIN
RX_Q2outputTCELL45:OUT.7.TMIN
RX_Q3outputTCELL45:OUT.8.TMIN
RX_Q4outputTCELL45:OUT.9.TMIN
RX_Q5outputTCELL45:OUT.10.TMIN
RX_Q6outputTCELL45:OUT.11.TMIN
RX_Q7outputTCELL45:OUT.12.TMIN
TX_CE_ODELAYinputTCELL45:IMUX.BYP.10
TX_CE_OFDinputTCELL45:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0inputTCELL46:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1inputTCELL46:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2inputTCELL46:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3inputTCELL46:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4inputTCELL46:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL46:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6inputTCELL46:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7inputTCELL46:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8inputTCELL46:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL45:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL45:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL45:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL45:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL45:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL45:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL45:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL45:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL45:OUT.21.TMIN
TX_D0inputTCELL46:IMUX.IMUX.16.DELAY
TX_D1inputTCELL46:IMUX.IMUX.6.DELAY
TX_D2inputTCELL45:IMUX.IMUX.15.DELAY
TX_D3inputTCELL45:IMUX.IMUX.14.DELAY
TX_D4inputTCELL45:IMUX.IMUX.13.DELAY
TX_D5inputTCELL45:IMUX.IMUX.12.DELAY
TX_D6inputTCELL45:IMUX.IMUX.11.DELAY
TX_D7inputTCELL45:IMUX.IMUX.10.DELAY
TX_EN_VTCinputTCELL45:IMUX.BYP.9
TX_INCinputTCELL45:IMUX.BYP.8
TX_LDinputTCELL45:IMUX.BYP.7
TX_TinputTCELL45:IMUX.IMUX.16.DELAY
TX_T_OUToutputTCELL45:OUT.22.TMIN

Bel BITSLICE40

ultrascale XIPHY bel BITSLICE40
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL47:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INTinputTCELL46:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL46:OUT.4.TMIN
RX_CE_IDELAYinputTCELL46:IMUX.BYP.14
RX_CE_IFDinputTCELL47:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL47:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1inputTCELL47:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2inputTCELL47:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3inputTCELL47:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4inputTCELL47:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5inputTCELL47:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6inputTCELL47:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7inputTCELL47:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8inputTCELL47:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0outputTCELL46:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL46:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL46:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL46:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL46:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL46:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL46:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL46:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL46:OUT.31.TMIN
RX_DATAIN1inputTCELL47:IMUX.IMUX.28.DELAY
RX_EN_VTCinputTCELL46:IMUX.BYP.13
RX_INCinputTCELL46:IMUX.BYP.12
RX_LDinputTCELL46:IMUX.BYP.11
RX_Q0outputTCELL46:OUT.5.TMIN
RX_Q1outputTCELL46:OUT.6.TMIN
RX_Q2outputTCELL46:OUT.7.TMIN
RX_Q3outputTCELL46:OUT.8.TMIN
RX_Q4outputTCELL46:OUT.9.TMIN
RX_Q5outputTCELL46:OUT.10.TMIN
RX_Q6outputTCELL46:OUT.11.TMIN
RX_Q7outputTCELL46:OUT.12.TMIN
TX_CE_ODELAYinputTCELL46:IMUX.BYP.10
TX_CE_OFDinputTCELL47:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL47:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1inputTCELL47:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2inputTCELL47:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3inputTCELL47:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4inputTCELL47:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5inputTCELL47:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6inputTCELL47:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7inputTCELL47:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8inputTCELL47:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0outputTCELL46:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL46:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL46:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL46:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL46:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL46:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL46:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL46:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL46:OUT.21.TMIN
TX_D0inputTCELL47:IMUX.IMUX.30.DELAY
TX_D1inputTCELL47:IMUX.IMUX.6.DELAY
TX_D2inputTCELL47:IMUX.IMUX.31.DELAY
TX_D3inputTCELL47:IMUX.IMUX.7.DELAY
TX_D4inputTCELL47:IMUX.IMUX.32.DELAY
TX_D5inputTCELL47:IMUX.IMUX.33.DELAY
TX_D6inputTCELL47:IMUX.IMUX.34.DELAY
TX_D7inputTCELL47:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL46:IMUX.BYP.9
TX_INCinputTCELL46:IMUX.BYP.8
TX_LDinputTCELL46:IMUX.BYP.7
TX_TinputTCELL47:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL46:OUT.22.TMIN

Bel BITSLICE41

ultrascale XIPHY bel BITSLICE41
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL48:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INTinputTCELL47:IMUX.BYP.14
PHY2CLB_FIFO_EMPTYoutputTCELL47:OUT.4.TMIN
RX_CE_IDELAYinputTCELL47:IMUX.BYP.13
RX_CE_IFDinputTCELL48:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0inputTCELL48:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL48:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL48:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL48:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL48:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL48:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL48:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL48:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL48:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL47:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL47:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL47:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL47:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL47:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL47:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL47:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL47:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL47:OUT.31.TMIN
RX_DATAIN1inputTCELL48:IMUX.IMUX.17.DELAY
RX_EN_VTCinputTCELL47:IMUX.BYP.12
RX_INCinputTCELL47:IMUX.BYP.11
RX_LDinputTCELL47:IMUX.BYP.10
RX_Q0outputTCELL47:OUT.5.TMIN
RX_Q1outputTCELL47:OUT.6.TMIN
RX_Q2outputTCELL47:OUT.7.TMIN
RX_Q3outputTCELL47:OUT.8.TMIN
RX_Q4outputTCELL47:OUT.9.TMIN
RX_Q5outputTCELL47:OUT.10.TMIN
RX_Q6outputTCELL47:OUT.11.TMIN
RX_Q7outputTCELL47:OUT.12.TMIN
TX_CE_ODELAYinputTCELL47:IMUX.BYP.9
TX_CE_OFDinputTCELL47:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0inputTCELL48:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL48:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL48:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL48:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL48:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL48:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL48:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL48:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL48:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL47:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL47:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL47:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL47:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL47:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL47:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL47:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL47:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL47:OUT.21.TMIN
TX_D0inputTCELL48:IMUX.IMUX.20.DELAY
TX_D1inputTCELL48:IMUX.IMUX.21.DELAY
TX_D2inputTCELL48:IMUX.IMUX.22.DELAY
TX_D3inputTCELL48:IMUX.IMUX.23.DELAY
TX_D4inputTCELL48:IMUX.IMUX.24.DELAY
TX_D5inputTCELL48:IMUX.IMUX.25.DELAY
TX_D6inputTCELL48:IMUX.IMUX.26.DELAY
TX_D7inputTCELL48:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL47:IMUX.BYP.8
TX_INCinputTCELL47:IMUX.BYP.7
TX_LDinputTCELL47:IMUX.BYP.6
TX_TinputTCELL47:IMUX.IMUX.47.DELAY
TX_T_OUToutputTCELL47:OUT.22.TMIN

Bel BITSLICE42

ultrascale XIPHY bel BITSLICE42
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL49:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INTinputTCELL49:IMUX.BYP.10
PHY2CLB_FIFO_EMPTYoutputTCELL48:OUT.18.TMIN
RX_CE_IDELAYinputTCELL49:IMUX.BYP.9
RX_CE_IFDinputTCELL49:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0inputTCELL50:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1inputTCELL50:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2inputTCELL50:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3inputTCELL50:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4inputTCELL50:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5inputTCELL50:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6inputTCELL50:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7inputTCELL50:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8inputTCELL50:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0outputTCELL49:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL49:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL49:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL49:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL49:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL49:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL49:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL49:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL49:OUT.17.TMIN
RX_DATAIN1inputTCELL49:IMUX.IMUX.37.DELAY
RX_EN_VTCinputTCELL49:IMUX.BYP.8
RX_INCinputTCELL49:IMUX.BYP.7
RX_LDinputTCELL49:IMUX.BYP.6
RX_Q0outputTCELL48:OUT.19.TMIN
RX_Q1outputTCELL48:OUT.20.TMIN
RX_Q2outputTCELL48:OUT.21.TMIN
RX_Q3outputTCELL48:OUT.22.TMIN
RX_Q4outputTCELL48:OUT.23.TMIN
RX_Q5outputTCELL48:OUT.24.TMIN
RX_Q6outputTCELL48:OUT.25.TMIN
RX_Q7outputTCELL48:OUT.26.TMIN
TX_CE_ODELAYinputTCELL48:IMUX.BYP.15
TX_CE_OFDinputTCELL49:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0inputTCELL49:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1inputTCELL49:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2inputTCELL49:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3inputTCELL49:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4inputTCELL49:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5inputTCELL49:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6inputTCELL50:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7inputTCELL50:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8inputTCELL50:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0outputTCELL48:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL48:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL48:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL48:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL48:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL49:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL49:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL49:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL49:OUT.7.TMIN
TX_D0inputTCELL49:IMUX.IMUX.10.DELAY
TX_D1inputTCELL49:IMUX.IMUX.39.DELAY
TX_D2inputTCELL49:IMUX.IMUX.11.DELAY
TX_D3inputTCELL49:IMUX.IMUX.40.DELAY
TX_D4inputTCELL49:IMUX.IMUX.41.DELAY
TX_D5inputTCELL49:IMUX.IMUX.42.DELAY
TX_D6inputTCELL49:IMUX.IMUX.12.DELAY
TX_D7inputTCELL49:IMUX.IMUX.13.DELAY
TX_EN_VTCinputTCELL48:IMUX.BYP.14
TX_INCinputTCELL48:IMUX.BYP.13
TX_LDinputTCELL48:IMUX.BYP.12
TX_TinputTCELL49:IMUX.IMUX.35.DELAY
TX_T_OUToutputTCELL48:OUT.13.TMIN

Bel BITSLICE43

ultrascale XIPHY bel BITSLICE43
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL50:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL50:IMUX.BYP.9
PHY2CLB_FIFO_EMPTYoutputTCELL49:OUT.18.TMIN
RX_CE_IDELAYinputTCELL50:IMUX.BYP.8
RX_CE_IFDinputTCELL50:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL50:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1inputTCELL50:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2inputTCELL50:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3inputTCELL50:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4inputTCELL50:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5inputTCELL50:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6inputTCELL50:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7inputTCELL50:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8inputTCELL51:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0outputTCELL50:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL50:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL50:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL50:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL50:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL50:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL50:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL50:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL50:OUT.17.TMIN
RX_DATAIN1inputTCELL50:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL50:IMUX.BYP.7
RX_INCinputTCELL50:IMUX.BYP.6
RX_LDinputTCELL49:IMUX.BYP.15
RX_Q0outputTCELL49:OUT.19.TMIN
RX_Q1outputTCELL49:OUT.20.TMIN
RX_Q2outputTCELL49:OUT.21.TMIN
RX_Q3outputTCELL49:OUT.22.TMIN
RX_Q4outputTCELL49:OUT.23.TMIN
RX_Q5outputTCELL49:OUT.24.TMIN
RX_Q6outputTCELL49:OUT.25.TMIN
RX_Q7outputTCELL49:OUT.26.TMIN
TX_CE_ODELAYinputTCELL49:IMUX.BYP.14
TX_CE_OFDinputTCELL50:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL50:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL50:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL50:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL50:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL50:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL50:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL50:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL50:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8inputTCELL50:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0outputTCELL49:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL49:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL49:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL49:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL49:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL50:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL50:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL50:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL50:OUT.7.TMIN
TX_D0inputTCELL50:IMUX.IMUX.7.DELAY
TX_D1inputTCELL50:IMUX.IMUX.32.DELAY
TX_D2inputTCELL50:IMUX.IMUX.33.DELAY
TX_D3inputTCELL50:IMUX.IMUX.34.DELAY
TX_D4inputTCELL50:IMUX.IMUX.8.DELAY
TX_D5inputTCELL50:IMUX.IMUX.35.DELAY
TX_D6inputTCELL50:IMUX.IMUX.9.DELAY
TX_D7inputTCELL50:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL49:IMUX.BYP.13
TX_INCinputTCELL49:IMUX.BYP.12
TX_LDinputTCELL49:IMUX.BYP.11
TX_TinputTCELL50:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL49:OUT.8.TMIN

Bel BITSLICE44

ultrascale XIPHY bel BITSLICE44
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL51:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INTinputTCELL51:IMUX.BYP.8
PHY2CLB_FIFO_EMPTYoutputTCELL50:OUT.18.TMIN
RX_CE_IDELAYinputTCELL51:IMUX.BYP.7
RX_CE_IFDinputTCELL51:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0inputTCELL51:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL51:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL51:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL51:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL51:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL51:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL51:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL51:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL51:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL51:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL51:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL51:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL51:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL51:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL51:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL51:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL51:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL51:OUT.17.TMIN
RX_DATAIN1inputTCELL51:IMUX.IMUX.20.DELAY
RX_EN_VTCinputTCELL51:IMUX.BYP.6
RX_INCinputTCELL50:IMUX.BYP.15
RX_LDinputTCELL50:IMUX.BYP.14
RX_Q0outputTCELL50:OUT.19.TMIN
RX_Q1outputTCELL50:OUT.20.TMIN
RX_Q2outputTCELL50:OUT.21.TMIN
RX_Q3outputTCELL50:OUT.22.TMIN
RX_Q4outputTCELL50:OUT.23.TMIN
RX_Q5outputTCELL50:OUT.24.TMIN
RX_Q6outputTCELL50:OUT.25.TMIN
RX_Q7outputTCELL50:OUT.26.TMIN
TX_CE_ODELAYinputTCELL50:IMUX.BYP.13
TX_CE_OFDinputTCELL51:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0inputTCELL51:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1inputTCELL51:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2inputTCELL51:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3inputTCELL51:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4inputTCELL51:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5inputTCELL51:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6inputTCELL51:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7inputTCELL51:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8inputTCELL51:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0outputTCELL50:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL50:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL50:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL50:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL50:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL51:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL51:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL51:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL51:OUT.7.TMIN
TX_D0inputTCELL51:IMUX.IMUX.22.DELAY
TX_D1inputTCELL51:IMUX.IMUX.23.DELAY
TX_D2inputTCELL51:IMUX.IMUX.24.DELAY
TX_D3inputTCELL51:IMUX.IMUX.25.DELAY
TX_D4inputTCELL51:IMUX.IMUX.26.DELAY
TX_D5inputTCELL51:IMUX.IMUX.27.DELAY
TX_D6inputTCELL51:IMUX.IMUX.28.DELAY
TX_D7inputTCELL51:IMUX.IMUX.29.DELAY
TX_EN_VTCinputTCELL50:IMUX.BYP.12
TX_INCinputTCELL50:IMUX.BYP.11
TX_LDinputTCELL50:IMUX.BYP.10
TX_TinputTCELL51:IMUX.IMUX.17.DELAY
TX_T_OUToutputTCELL50:OUT.8.TMIN

Bel BITSLICE45

ultrascale XIPHY bel BITSLICE45
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL53:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INTinputTCELL54:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL53:OUT.18.TMIN
RX_CE_IDELAYinputTCELL54:IMUX.BYP.11
RX_CE_IFDinputTCELL53:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0inputTCELL53:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1inputTCELL53:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2inputTCELL53:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3inputTCELL53:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4inputTCELL53:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5inputTCELL53:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6inputTCELL53:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7inputTCELL53:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL53:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0outputTCELL54:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL54:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL54:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL54:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL54:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL54:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL54:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL54:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL54:OUT.17.TMIN
RX_DATAIN1inputTCELL53:IMUX.IMUX.29.DELAY
RX_EN_VTCinputTCELL54:IMUX.BYP.10
RX_INCinputTCELL54:IMUX.BYP.9
RX_LDinputTCELL54:IMUX.BYP.8
RX_Q0outputTCELL53:OUT.19.TMIN
RX_Q1outputTCELL53:OUT.20.TMIN
RX_Q2outputTCELL53:OUT.21.TMIN
RX_Q3outputTCELL53:OUT.22.TMIN
RX_Q4outputTCELL53:OUT.23.TMIN
RX_Q5outputTCELL53:OUT.24.TMIN
RX_Q6outputTCELL53:OUT.25.TMIN
RX_Q7outputTCELL53:OUT.26.TMIN
TX_CE_ODELAYinputTCELL54:IMUX.BYP.7
TX_CE_OFDinputTCELL53:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0inputTCELL53:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL53:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2inputTCELL53:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3inputTCELL53:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4inputTCELL53:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5inputTCELL53:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6inputTCELL53:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7inputTCELL53:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8inputTCELL53:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0outputTCELL53:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL53:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL53:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL53:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL53:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL54:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL54:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL54:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL54:OUT.7.TMIN
TX_D0inputTCELL53:IMUX.IMUX.6.DELAY
TX_D1inputTCELL53:IMUX.IMUX.31.DELAY
TX_D2inputTCELL53:IMUX.IMUX.7.DELAY
TX_D3inputTCELL53:IMUX.IMUX.32.DELAY
TX_D4inputTCELL53:IMUX.IMUX.33.DELAY
TX_D5inputTCELL53:IMUX.IMUX.34.DELAY
TX_D6inputTCELL53:IMUX.IMUX.8.DELAY
TX_D7inputTCELL53:IMUX.IMUX.35.DELAY
TX_EN_VTCinputTCELL54:IMUX.BYP.6
TX_INCinputTCELL53:IMUX.BYP.15
TX_LDinputTCELL53:IMUX.BYP.14
TX_TinputTCELL53:IMUX.IMUX.25.DELAY
TX_T_OUToutputTCELL51:OUT.8.TMIN

Bel BITSLICE46

ultrascale XIPHY bel BITSLICE46
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL54:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INTinputTCELL55:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL54:OUT.18.TMIN
RX_CE_IDELAYinputTCELL55:IMUX.BYP.11
RX_CE_IFDinputTCELL54:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0inputTCELL54:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1inputTCELL54:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2inputTCELL54:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL54:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4inputTCELL54:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5inputTCELL54:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6inputTCELL54:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7inputTCELL54:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8inputTCELL54:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0outputTCELL55:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL55:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL55:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL55:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL55:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL55:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL55:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL55:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL55:OUT.17.TMIN
RX_DATAIN1inputTCELL54:IMUX.IMUX.18.DELAY
RX_EN_VTCinputTCELL55:IMUX.BYP.10
RX_INCinputTCELL55:IMUX.BYP.9
RX_LDinputTCELL55:IMUX.BYP.8
RX_Q0outputTCELL54:OUT.19.TMIN
RX_Q1outputTCELL54:OUT.20.TMIN
RX_Q2outputTCELL54:OUT.21.TMIN
RX_Q3outputTCELL54:OUT.22.TMIN
RX_Q4outputTCELL54:OUT.23.TMIN
RX_Q5outputTCELL54:OUT.24.TMIN
RX_Q6outputTCELL54:OUT.25.TMIN
RX_Q7outputTCELL54:OUT.26.TMIN
TX_CE_ODELAYinputTCELL55:IMUX.BYP.7
TX_CE_OFDinputTCELL54:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0inputTCELL54:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1inputTCELL54:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2inputTCELL54:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3inputTCELL54:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4inputTCELL54:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5inputTCELL54:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6inputTCELL54:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7inputTCELL54:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8inputTCELL54:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0outputTCELL54:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL54:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL54:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL54:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL54:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL55:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL55:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL55:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL55:OUT.7.TMIN
TX_D0inputTCELL54:IMUX.IMUX.20.DELAY
TX_D1inputTCELL54:IMUX.IMUX.21.DELAY
TX_D2inputTCELL54:IMUX.IMUX.22.DELAY
TX_D3inputTCELL54:IMUX.IMUX.23.DELAY
TX_D4inputTCELL54:IMUX.IMUX.24.DELAY
TX_D5inputTCELL54:IMUX.IMUX.25.DELAY
TX_D6inputTCELL54:IMUX.IMUX.26.DELAY
TX_D7inputTCELL54:IMUX.IMUX.27.DELAY
TX_EN_VTCinputTCELL55:IMUX.BYP.6
TX_INCinputTCELL54:IMUX.BYP.15
TX_LDinputTCELL54:IMUX.BYP.14
TX_TinputTCELL53:IMUX.IMUX.15.DELAY
TX_T_OUToutputTCELL53:OUT.8.TMIN

Bel BITSLICE47

ultrascale XIPHY bel BITSLICE47
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL54:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INTinputTCELL56:IMUX.BYP.12
PHY2CLB_FIFO_EMPTYoutputTCELL55:OUT.18.TMIN
RX_CE_IDELAYinputTCELL56:IMUX.BYP.11
RX_CE_IFDinputTCELL54:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0inputTCELL55:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1inputTCELL55:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2inputTCELL55:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3inputTCELL55:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4inputTCELL55:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5inputTCELL55:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6inputTCELL55:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7inputTCELL55:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8inputTCELL55:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0outputTCELL56:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL56:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL56:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL56:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL56:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL56:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL56:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL56:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL56:OUT.17.TMIN
RX_DATAIN1inputTCELL54:IMUX.IMUX.12.DELAY
RX_EN_VTCinputTCELL56:IMUX.BYP.10
RX_INCinputTCELL56:IMUX.BYP.9
RX_LDinputTCELL56:IMUX.BYP.8
RX_Q0outputTCELL55:OUT.19.TMIN
RX_Q1outputTCELL55:OUT.20.TMIN
RX_Q2outputTCELL55:OUT.21.TMIN
RX_Q3outputTCELL55:OUT.22.TMIN
RX_Q4outputTCELL55:OUT.23.TMIN
RX_Q5outputTCELL55:OUT.24.TMIN
RX_Q6outputTCELL55:OUT.25.TMIN
RX_Q7outputTCELL55:OUT.26.TMIN
TX_CE_ODELAYinputTCELL56:IMUX.BYP.6
TX_CE_OFDinputTCELL54:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0inputTCELL55:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1inputTCELL55:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2inputTCELL55:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3inputTCELL55:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4inputTCELL55:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5inputTCELL55:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6inputTCELL55:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7inputTCELL55:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8inputTCELL55:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0outputTCELL55:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL55:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL55:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL55:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL55:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL56:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL56:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL56:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL56:OUT.7.TMIN
TX_D0inputTCELL54:IMUX.IMUX.13.DELAY
TX_D1inputTCELL54:IMUX.IMUX.44.DELAY
TX_D2inputTCELL54:IMUX.IMUX.45.DELAY
TX_D3inputTCELL54:IMUX.IMUX.46.DELAY
TX_D4inputTCELL54:IMUX.IMUX.14.DELAY
TX_D5inputTCELL54:IMUX.IMUX.47.DELAY
TX_D6inputTCELL54:IMUX.IMUX.15.DELAY
TX_D7inputTCELL55:IMUX.IMUX.16.DELAY
TX_EN_VTCinputTCELL55:IMUX.BYP.15
TX_INCinputTCELL55:IMUX.BYP.14
TX_LDinputTCELL55:IMUX.BYP.13
TX_TinputTCELL54:IMUX.IMUX.40.DELAY
TX_T_OUToutputTCELL54:OUT.8.TMIN

Bel BITSLICE48

ultrascale XIPHY bel BITSLICE48
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL56:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INTinputTCELL58:IMUX.BYP.7
PHY2CLB_FIFO_EMPTYoutputTCELL57:OUT.4.TMIN
RX_CE_IDELAYinputTCELL58:IMUX.BYP.6
RX_CE_IFDinputTCELL56:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0inputTCELL56:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1inputTCELL56:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2inputTCELL56:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3inputTCELL56:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4inputTCELL56:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5inputTCELL56:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6inputTCELL56:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7inputTCELL57:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8inputTCELL57:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0outputTCELL57:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL57:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL57:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL57:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL57:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL57:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL57:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL57:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL57:OUT.31.TMIN
RX_DATAIN1inputTCELL56:IMUX.IMUX.6.DELAY
RX_EN_VTCinputTCELL57:IMUX.BYP.15
RX_INCinputTCELL57:IMUX.BYP.14
RX_LDinputTCELL57:IMUX.BYP.13
RX_Q0outputTCELL57:OUT.5.TMIN
RX_Q1outputTCELL57:OUT.6.TMIN
RX_Q2outputTCELL57:OUT.7.TMIN
RX_Q3outputTCELL57:OUT.8.TMIN
RX_Q4outputTCELL57:OUT.9.TMIN
RX_Q5outputTCELL57:OUT.10.TMIN
RX_Q6outputTCELL57:OUT.11.TMIN
RX_Q7outputTCELL57:OUT.12.TMIN
TX_CE_ODELAYinputTCELL57:IMUX.BYP.12
TX_CE_OFDinputTCELL56:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0inputTCELL56:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1inputTCELL56:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2inputTCELL56:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3inputTCELL56:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4inputTCELL56:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5inputTCELL56:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6inputTCELL56:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7inputTCELL56:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8inputTCELL56:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0outputTCELL57:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL57:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL57:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL57:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL57:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL57:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL57:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL57:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL57:OUT.21.TMIN
TX_D0inputTCELL56:IMUX.IMUX.7.DELAY
TX_D1inputTCELL56:IMUX.IMUX.32.DELAY
TX_D2inputTCELL56:IMUX.IMUX.33.DELAY
TX_D3inputTCELL56:IMUX.IMUX.34.DELAY
TX_D4inputTCELL56:IMUX.IMUX.8.DELAY
TX_D5inputTCELL56:IMUX.IMUX.35.DELAY
TX_D6inputTCELL56:IMUX.IMUX.9.DELAY
TX_D7inputTCELL56:IMUX.IMUX.36.DELAY
TX_EN_VTCinputTCELL57:IMUX.BYP.11
TX_INCinputTCELL57:IMUX.BYP.10
TX_LDinputTCELL57:IMUX.BYP.9
TX_TinputTCELL56:IMUX.IMUX.28.DELAY
TX_T_OUToutputTCELL55:OUT.8.TMIN

Bel BITSLICE49

ultrascale XIPHY bel BITSLICE49
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL57:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INTinputTCELL59:IMUX.BYP.6
PHY2CLB_FIFO_EMPTYoutputTCELL58:OUT.4.TMIN
RX_CE_IDELAYinputTCELL58:IMUX.BYP.15
RX_CE_IFDinputTCELL57:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0inputTCELL57:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1inputTCELL57:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2inputTCELL57:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3inputTCELL57:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL57:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5inputTCELL57:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6inputTCELL57:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7inputTCELL57:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8inputTCELL57:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0outputTCELL58:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL58:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL58:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL58:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL58:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL58:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL58:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL58:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL58:OUT.31.TMIN
RX_DATAIN1inputTCELL57:IMUX.IMUX.21.DELAY
RX_EN_VTCinputTCELL58:IMUX.BYP.14
RX_INCinputTCELL58:IMUX.BYP.13
RX_LDinputTCELL58:IMUX.BYP.12
RX_Q0outputTCELL58:OUT.5.TMIN
RX_Q1outputTCELL58:OUT.6.TMIN
RX_Q2outputTCELL58:OUT.7.TMIN
RX_Q3outputTCELL58:OUT.8.TMIN
RX_Q4outputTCELL58:OUT.9.TMIN
RX_Q5outputTCELL58:OUT.10.TMIN
RX_Q6outputTCELL58:OUT.11.TMIN
RX_Q7outputTCELL58:OUT.12.TMIN
TX_CE_ODELAYinputTCELL58:IMUX.BYP.11
TX_CE_OFDinputTCELL57:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0inputTCELL57:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1inputTCELL57:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2inputTCELL57:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3inputTCELL57:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4inputTCELL57:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5inputTCELL57:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6inputTCELL57:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7inputTCELL57:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8inputTCELL57:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0outputTCELL58:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL58:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL58:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL58:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL58:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL58:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL58:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL58:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL58:OUT.21.TMIN
TX_D0inputTCELL57:IMUX.IMUX.28.DELAY
TX_D1inputTCELL57:IMUX.IMUX.27.DELAY
TX_D2inputTCELL57:IMUX.IMUX.26.DELAY
TX_D3inputTCELL57:IMUX.IMUX.25.DELAY
TX_D4inputTCELL57:IMUX.IMUX.24.DELAY
TX_D5inputTCELL57:IMUX.IMUX.23.DELAY
TX_D6inputTCELL57:IMUX.IMUX.29.DELAY
TX_D7inputTCELL57:IMUX.IMUX.30.DELAY
TX_EN_VTCinputTCELL58:IMUX.BYP.10
TX_INCinputTCELL58:IMUX.BYP.9
TX_LDinputTCELL58:IMUX.BYP.8
TX_TinputTCELL57:IMUX.IMUX.18.DELAY
TX_T_OUToutputTCELL56:OUT.8.TMIN

Bel BITSLICE50

ultrascale XIPHY bel BITSLICE50
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL57:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INTinputTCELL59:IMUX.BYP.15
PHY2CLB_FIFO_EMPTYoutputTCELL59:OUT.4.TMIN
RX_CE_IDELAYinputTCELL59:IMUX.BYP.14
RX_CE_IFDinputTCELL57:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0inputTCELL59:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1inputTCELL59:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2inputTCELL59:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3inputTCELL59:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4inputTCELL59:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5inputTCELL59:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6inputTCELL59:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7inputTCELL59:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8inputTCELL59:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0outputTCELL59:OUT.23.TMIN
RX_CNTVALUEOUT1outputTCELL59:OUT.24.TMIN
RX_CNTVALUEOUT2outputTCELL59:OUT.25.TMIN
RX_CNTVALUEOUT3outputTCELL59:OUT.26.TMIN
RX_CNTVALUEOUT4outputTCELL59:OUT.27.TMIN
RX_CNTVALUEOUT5outputTCELL59:OUT.28.TMIN
RX_CNTVALUEOUT6outputTCELL59:OUT.29.TMIN
RX_CNTVALUEOUT7outputTCELL59:OUT.30.TMIN
RX_CNTVALUEOUT8outputTCELL59:OUT.31.TMIN
RX_DATAIN1inputTCELL57:IMUX.IMUX.44.DELAY
RX_EN_VTCinputTCELL59:IMUX.BYP.13
RX_INCinputTCELL59:IMUX.BYP.12
RX_LDinputTCELL59:IMUX.BYP.11
RX_Q0outputTCELL59:OUT.5.TMIN
RX_Q1outputTCELL59:OUT.6.TMIN
RX_Q2outputTCELL59:OUT.7.TMIN
RX_Q3outputTCELL59:OUT.8.TMIN
RX_Q4outputTCELL59:OUT.9.TMIN
RX_Q5outputTCELL59:OUT.10.TMIN
RX_Q6outputTCELL59:OUT.11.TMIN
RX_Q7outputTCELL59:OUT.12.TMIN
TX_CE_ODELAYinputTCELL59:IMUX.BYP.10
TX_CE_OFDinputTCELL57:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0inputTCELL58:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1inputTCELL58:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2inputTCELL58:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3inputTCELL58:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4inputTCELL58:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5inputTCELL58:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6inputTCELL58:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7inputTCELL59:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8inputTCELL59:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0outputTCELL59:OUT.13.TMIN
TX_CNTVALUEOUT1outputTCELL59:OUT.14.TMIN
TX_CNTVALUEOUT2outputTCELL59:OUT.15.TMIN
TX_CNTVALUEOUT3outputTCELL59:OUT.16.TMIN
TX_CNTVALUEOUT4outputTCELL59:OUT.17.TMIN
TX_CNTVALUEOUT5outputTCELL59:OUT.18.TMIN
TX_CNTVALUEOUT6outputTCELL59:OUT.19.TMIN
TX_CNTVALUEOUT7outputTCELL59:OUT.20.TMIN
TX_CNTVALUEOUT8outputTCELL59:OUT.21.TMIN
TX_D0inputTCELL57:IMUX.IMUX.46.DELAY
TX_D1inputTCELL57:IMUX.IMUX.14.DELAY
TX_D2inputTCELL57:IMUX.IMUX.47.DELAY
TX_D3inputTCELL57:IMUX.IMUX.15.DELAY
TX_D4inputTCELL58:IMUX.IMUX.16.DELAY
TX_D5inputTCELL58:IMUX.IMUX.6.DELAY
TX_D6inputTCELL58:IMUX.IMUX.7.DELAY
TX_D7inputTCELL58:IMUX.IMUX.8.DELAY
TX_EN_VTCinputTCELL59:IMUX.BYP.9
TX_INCinputTCELL59:IMUX.BYP.8
TX_LDinputTCELL59:IMUX.BYP.7
TX_TinputTCELL57:IMUX.IMUX.12.DELAY
TX_T_OUToutputTCELL56:OUT.31.TMIN

Bel BITSLICE51

ultrascale XIPHY bel BITSLICE51
PinDirectionWires
CLB2PHY_FIFO_RDENinputTCELL52:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INTinputTCELL53:IMUX.BYP.13
PHY2CLB_FIFO_EMPTYoutputTCELL52:OUT.18.TMIN
RX_CE_IDELAYinputTCELL53:IMUX.BYP.12
RX_CE_IFDinputTCELL52:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0inputTCELL53:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1inputTCELL53:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2inputTCELL53:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3inputTCELL53:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4inputTCELL53:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5inputTCELL53:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6inputTCELL53:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7inputTCELL53:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8inputTCELL53:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0outputTCELL53:OUT.9.TMIN
RX_CNTVALUEOUT1outputTCELL53:OUT.10.TMIN
RX_CNTVALUEOUT2outputTCELL53:OUT.11.TMIN
RX_CNTVALUEOUT3outputTCELL53:OUT.12.TMIN
RX_CNTVALUEOUT4outputTCELL53:OUT.13.TMIN
RX_CNTVALUEOUT5outputTCELL53:OUT.14.TMIN
RX_CNTVALUEOUT6outputTCELL53:OUT.15.TMIN
RX_CNTVALUEOUT7outputTCELL53:OUT.16.TMIN
RX_CNTVALUEOUT8outputTCELL53:OUT.17.TMIN
RX_DATAIN1inputTCELL52:IMUX.IMUX.9.DELAY
RX_EN_VTCinputTCELL53:IMUX.BYP.11
RX_INCinputTCELL53:IMUX.BYP.10
RX_LDinputTCELL53:IMUX.BYP.9
RX_Q0outputTCELL52:OUT.19.TMIN
RX_Q1outputTCELL52:OUT.20.TMIN
RX_Q2outputTCELL52:OUT.21.TMIN
RX_Q3outputTCELL52:OUT.22.TMIN
RX_Q4outputTCELL52:OUT.23.TMIN
RX_Q5outputTCELL52:OUT.24.TMIN
RX_Q6outputTCELL52:OUT.25.TMIN
RX_Q7outputTCELL52:OUT.26.TMIN
TX_CE_ODELAYinputTCELL53:IMUX.BYP.8
TX_CE_OFDinputTCELL52:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0inputTCELL52:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1inputTCELL52:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2inputTCELL52:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3inputTCELL52:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4inputTCELL52:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5inputTCELL52:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6inputTCELL52:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7inputTCELL52:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8inputTCELL52:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0outputTCELL52:OUT.27.TMIN
TX_CNTVALUEOUT1outputTCELL52:OUT.28.TMIN
TX_CNTVALUEOUT2outputTCELL52:OUT.29.TMIN
TX_CNTVALUEOUT3outputTCELL52:OUT.30.TMIN
TX_CNTVALUEOUT4outputTCELL52:OUT.31.TMIN
TX_CNTVALUEOUT5outputTCELL53:OUT.4.TMIN
TX_CNTVALUEOUT6outputTCELL53:OUT.5.TMIN
TX_CNTVALUEOUT7outputTCELL53:OUT.6.TMIN
TX_CNTVALUEOUT8outputTCELL53:OUT.7.TMIN
TX_D0inputTCELL52:IMUX.IMUX.37.DELAY
TX_D1inputTCELL52:IMUX.IMUX.38.DELAY
TX_D2inputTCELL52:IMUX.IMUX.10.DELAY
TX_D3inputTCELL52:IMUX.IMUX.39.DELAY
TX_D4inputTCELL52:IMUX.IMUX.11.DELAY
TX_D5inputTCELL52:IMUX.IMUX.40.DELAY
TX_D6inputTCELL52:IMUX.IMUX.41.DELAY
TX_D7inputTCELL52:IMUX.IMUX.42.DELAY
TX_EN_VTCinputTCELL53:IMUX.BYP.7
TX_INCinputTCELL53:IMUX.BYP.6
TX_LDinputTCELL52:IMUX.BYP.15
TX_TinputTCELL52:IMUX.IMUX.34.DELAY
TX_T_OUToutputTCELL57:OUT.22.TMIN

Bel BITSLICE_T0

ultrascale XIPHY bel BITSLICE_T0
PinDirectionWires
CE_ODELAYinputTCELL3:IMUX.BYP.8
CE_OFDinputTCELL2:IMUX.BYP.15
CNTVALUEIN0inputTCELL3:IMUX.IMUX.40.DELAY
CNTVALUEIN1inputTCELL3:IMUX.IMUX.41.DELAY
CNTVALUEIN2inputTCELL3:IMUX.IMUX.42.DELAY
CNTVALUEIN3inputTCELL3:IMUX.IMUX.12.DELAY
CNTVALUEIN4inputTCELL3:IMUX.IMUX.43.DELAY
CNTVALUEIN5inputTCELL3:IMUX.IMUX.13.DELAY
CNTVALUEIN6inputTCELL3:IMUX.IMUX.44.DELAY
CNTVALUEIN7inputTCELL3:IMUX.IMUX.45.DELAY
CNTVALUEIN8inputTCELL3:IMUX.IMUX.46.DELAY
CNTVALUEOUT0outputTCELL3:OUT.4.TMIN
CNTVALUEOUT1outputTCELL3:OUT.5.TMIN
CNTVALUEOUT2outputTCELL3:OUT.6.TMIN
CNTVALUEOUT3outputTCELL3:OUT.7.TMIN
CNTVALUEOUT4outputTCELL3:OUT.8.TMIN
CNTVALUEOUT5outputTCELL3:OUT.9.TMIN
CNTVALUEOUT6outputTCELL3:OUT.10.TMIN
CNTVALUEOUT7outputTCELL3:OUT.11.TMIN
CNTVALUEOUT8outputTCELL3:OUT.12.TMIN
EN_VTCinputTCELL0:IMUX.BYP.6
INCinputTCELL3:IMUX.BYP.7
LDinputTCELL3:IMUX.BYP.6

Bel BITSLICE_T1

ultrascale XIPHY bel BITSLICE_T1
PinDirectionWires
CE_ODELAYinputTCELL12:IMUX.BYP.6
CE_OFDinputTCELL11:IMUX.BYP.13
CNTVALUEIN0inputTCELL10:IMUX.IMUX.34.DELAY
CNTVALUEIN1inputTCELL10:IMUX.IMUX.8.DELAY
CNTVALUEIN2inputTCELL10:IMUX.IMUX.35.DELAY
CNTVALUEIN3inputTCELL10:IMUX.IMUX.9.DELAY
CNTVALUEIN4inputTCELL10:IMUX.IMUX.36.DELAY
CNTVALUEIN5inputTCELL10:IMUX.IMUX.37.DELAY
CNTVALUEIN6inputTCELL10:IMUX.IMUX.38.DELAY
CNTVALUEIN7inputTCELL10:IMUX.IMUX.10.DELAY
CNTVALUEIN8inputTCELL10:IMUX.IMUX.39.DELAY
CNTVALUEOUT0outputTCELL11:OUT.18.TMIN
CNTVALUEOUT1outputTCELL11:OUT.19.TMIN
CNTVALUEOUT2outputTCELL11:OUT.20.TMIN
CNTVALUEOUT3outputTCELL11:OUT.21.TMIN
CNTVALUEOUT4outputTCELL11:OUT.22.TMIN
CNTVALUEOUT5outputTCELL11:OUT.23.TMIN
CNTVALUEOUT6outputTCELL11:OUT.24.TMIN
CNTVALUEOUT7outputTCELL11:OUT.25.TMIN
CNTVALUEOUT8outputTCELL11:OUT.26.TMIN
EN_VTCinputTCELL1:IMUX.BYP.6
INCinputTCELL11:IMUX.BYP.15
LDinputTCELL11:IMUX.BYP.14

Bel BITSLICE_T2

ultrascale XIPHY bel BITSLICE_T2
PinDirectionWires
CE_ODELAYinputTCELL18:IMUX.BYP.8
CE_OFDinputTCELL17:IMUX.BYP.15
CNTVALUEIN0inputTCELL18:IMUX.IMUX.40.DELAY
CNTVALUEIN1inputTCELL18:IMUX.IMUX.41.DELAY
CNTVALUEIN2inputTCELL18:IMUX.IMUX.42.DELAY
CNTVALUEIN3inputTCELL18:IMUX.IMUX.12.DELAY
CNTVALUEIN4inputTCELL18:IMUX.IMUX.43.DELAY
CNTVALUEIN5inputTCELL18:IMUX.IMUX.13.DELAY
CNTVALUEIN6inputTCELL18:IMUX.IMUX.44.DELAY
CNTVALUEIN7inputTCELL18:IMUX.IMUX.45.DELAY
CNTVALUEIN8inputTCELL18:IMUX.IMUX.46.DELAY
CNTVALUEOUT0outputTCELL18:OUT.4.TMIN
CNTVALUEOUT1outputTCELL18:OUT.5.TMIN
CNTVALUEOUT2outputTCELL18:OUT.6.TMIN
CNTVALUEOUT3outputTCELL18:OUT.7.TMIN
CNTVALUEOUT4outputTCELL18:OUT.8.TMIN
CNTVALUEOUT5outputTCELL18:OUT.9.TMIN
CNTVALUEOUT6outputTCELL18:OUT.10.TMIN
CNTVALUEOUT7outputTCELL18:OUT.11.TMIN
CNTVALUEOUT8outputTCELL18:OUT.12.TMIN
EN_VTCinputTCELL15:IMUX.BYP.6
INCinputTCELL18:IMUX.BYP.7
LDinputTCELL18:IMUX.BYP.6

Bel BITSLICE_T3

ultrascale XIPHY bel BITSLICE_T3
PinDirectionWires
CE_ODELAYinputTCELL27:IMUX.BYP.6
CE_OFDinputTCELL26:IMUX.BYP.13
CNTVALUEIN0inputTCELL25:IMUX.IMUX.34.DELAY
CNTVALUEIN1inputTCELL25:IMUX.IMUX.8.DELAY
CNTVALUEIN2inputTCELL25:IMUX.IMUX.35.DELAY
CNTVALUEIN3inputTCELL25:IMUX.IMUX.9.DELAY
CNTVALUEIN4inputTCELL25:IMUX.IMUX.36.DELAY
CNTVALUEIN5inputTCELL25:IMUX.IMUX.37.DELAY
CNTVALUEIN6inputTCELL25:IMUX.IMUX.38.DELAY
CNTVALUEIN7inputTCELL25:IMUX.IMUX.10.DELAY
CNTVALUEIN8inputTCELL25:IMUX.IMUX.39.DELAY
CNTVALUEOUT0outputTCELL26:OUT.18.TMIN
CNTVALUEOUT1outputTCELL26:OUT.19.TMIN
CNTVALUEOUT2outputTCELL26:OUT.20.TMIN
CNTVALUEOUT3outputTCELL26:OUT.21.TMIN
CNTVALUEOUT4outputTCELL26:OUT.22.TMIN
CNTVALUEOUT5outputTCELL26:OUT.23.TMIN
CNTVALUEOUT6outputTCELL26:OUT.24.TMIN
CNTVALUEOUT7outputTCELL26:OUT.25.TMIN
CNTVALUEOUT8outputTCELL26:OUT.26.TMIN
EN_VTCinputTCELL16:IMUX.BYP.6
INCinputTCELL26:IMUX.BYP.15
LDinputTCELL26:IMUX.BYP.14

Bel BITSLICE_T4

ultrascale XIPHY bel BITSLICE_T4
PinDirectionWires
CE_ODELAYinputTCELL33:IMUX.BYP.8
CE_OFDinputTCELL32:IMUX.BYP.15
CNTVALUEIN0inputTCELL33:IMUX.IMUX.40.DELAY
CNTVALUEIN1inputTCELL33:IMUX.IMUX.41.DELAY
CNTVALUEIN2inputTCELL33:IMUX.IMUX.42.DELAY
CNTVALUEIN3inputTCELL33:IMUX.IMUX.12.DELAY
CNTVALUEIN4inputTCELL33:IMUX.IMUX.43.DELAY
CNTVALUEIN5inputTCELL33:IMUX.IMUX.13.DELAY
CNTVALUEIN6inputTCELL33:IMUX.IMUX.44.DELAY
CNTVALUEIN7inputTCELL33:IMUX.IMUX.45.DELAY
CNTVALUEIN8inputTCELL33:IMUX.IMUX.46.DELAY
CNTVALUEOUT0outputTCELL33:OUT.4.TMIN
CNTVALUEOUT1outputTCELL33:OUT.5.TMIN
CNTVALUEOUT2outputTCELL33:OUT.6.TMIN
CNTVALUEOUT3outputTCELL33:OUT.7.TMIN
CNTVALUEOUT4outputTCELL33:OUT.8.TMIN
CNTVALUEOUT5outputTCELL33:OUT.9.TMIN
CNTVALUEOUT6outputTCELL33:OUT.10.TMIN
CNTVALUEOUT7outputTCELL33:OUT.11.TMIN
CNTVALUEOUT8outputTCELL33:OUT.12.TMIN
EN_VTCinputTCELL30:IMUX.BYP.6
INCinputTCELL33:IMUX.BYP.7
LDinputTCELL33:IMUX.BYP.6

Bel BITSLICE_T5

ultrascale XIPHY bel BITSLICE_T5
PinDirectionWires
CE_ODELAYinputTCELL42:IMUX.BYP.6
CE_OFDinputTCELL41:IMUX.BYP.13
CNTVALUEIN0inputTCELL40:IMUX.IMUX.34.DELAY
CNTVALUEIN1inputTCELL40:IMUX.IMUX.8.DELAY
CNTVALUEIN2inputTCELL40:IMUX.IMUX.35.DELAY
CNTVALUEIN3inputTCELL40:IMUX.IMUX.9.DELAY
CNTVALUEIN4inputTCELL40:IMUX.IMUX.36.DELAY
CNTVALUEIN5inputTCELL40:IMUX.IMUX.37.DELAY
CNTVALUEIN6inputTCELL40:IMUX.IMUX.38.DELAY
CNTVALUEIN7inputTCELL40:IMUX.IMUX.10.DELAY
CNTVALUEIN8inputTCELL40:IMUX.IMUX.39.DELAY
CNTVALUEOUT0outputTCELL41:OUT.18.TMIN
CNTVALUEOUT1outputTCELL41:OUT.19.TMIN
CNTVALUEOUT2outputTCELL41:OUT.20.TMIN
CNTVALUEOUT3outputTCELL41:OUT.21.TMIN
CNTVALUEOUT4outputTCELL41:OUT.22.TMIN
CNTVALUEOUT5outputTCELL41:OUT.23.TMIN
CNTVALUEOUT6outputTCELL41:OUT.24.TMIN
CNTVALUEOUT7outputTCELL41:OUT.25.TMIN
CNTVALUEOUT8outputTCELL41:OUT.26.TMIN
EN_VTCinputTCELL31:IMUX.BYP.6
INCinputTCELL41:IMUX.BYP.15
LDinputTCELL41:IMUX.BYP.14

Bel BITSLICE_T6

ultrascale XIPHY bel BITSLICE_T6
PinDirectionWires
CE_ODELAYinputTCELL48:IMUX.BYP.8
CE_OFDinputTCELL47:IMUX.BYP.15
CNTVALUEIN0inputTCELL48:IMUX.IMUX.40.DELAY
CNTVALUEIN1inputTCELL48:IMUX.IMUX.41.DELAY
CNTVALUEIN2inputTCELL48:IMUX.IMUX.42.DELAY
CNTVALUEIN3inputTCELL48:IMUX.IMUX.12.DELAY
CNTVALUEIN4inputTCELL48:IMUX.IMUX.43.DELAY
CNTVALUEIN5inputTCELL48:IMUX.IMUX.13.DELAY
CNTVALUEIN6inputTCELL48:IMUX.IMUX.44.DELAY
CNTVALUEIN7inputTCELL48:IMUX.IMUX.45.DELAY
CNTVALUEIN8inputTCELL48:IMUX.IMUX.46.DELAY
CNTVALUEOUT0outputTCELL48:OUT.4.TMIN
CNTVALUEOUT1outputTCELL48:OUT.5.TMIN
CNTVALUEOUT2outputTCELL48:OUT.6.TMIN
CNTVALUEOUT3outputTCELL48:OUT.7.TMIN
CNTVALUEOUT4outputTCELL48:OUT.8.TMIN
CNTVALUEOUT5outputTCELL48:OUT.9.TMIN
CNTVALUEOUT6outputTCELL48:OUT.10.TMIN
CNTVALUEOUT7outputTCELL48:OUT.11.TMIN
CNTVALUEOUT8outputTCELL48:OUT.12.TMIN
EN_VTCinputTCELL45:IMUX.BYP.6
INCinputTCELL48:IMUX.BYP.7
LDinputTCELL48:IMUX.BYP.6

Bel BITSLICE_T7

ultrascale XIPHY bel BITSLICE_T7
PinDirectionWires
CE_ODELAYinputTCELL57:IMUX.BYP.6
CE_OFDinputTCELL56:IMUX.BYP.13
CNTVALUEIN0inputTCELL55:IMUX.IMUX.34.DELAY
CNTVALUEIN1inputTCELL55:IMUX.IMUX.8.DELAY
CNTVALUEIN2inputTCELL55:IMUX.IMUX.35.DELAY
CNTVALUEIN3inputTCELL55:IMUX.IMUX.9.DELAY
CNTVALUEIN4inputTCELL55:IMUX.IMUX.36.DELAY
CNTVALUEIN5inputTCELL55:IMUX.IMUX.37.DELAY
CNTVALUEIN6inputTCELL55:IMUX.IMUX.38.DELAY
CNTVALUEIN7inputTCELL55:IMUX.IMUX.10.DELAY
CNTVALUEIN8inputTCELL55:IMUX.IMUX.39.DELAY
CNTVALUEOUT0outputTCELL56:OUT.18.TMIN
CNTVALUEOUT1outputTCELL56:OUT.19.TMIN
CNTVALUEOUT2outputTCELL56:OUT.20.TMIN
CNTVALUEOUT3outputTCELL56:OUT.21.TMIN
CNTVALUEOUT4outputTCELL56:OUT.22.TMIN
CNTVALUEOUT5outputTCELL56:OUT.23.TMIN
CNTVALUEOUT6outputTCELL56:OUT.24.TMIN
CNTVALUEOUT7outputTCELL56:OUT.25.TMIN
CNTVALUEOUT8outputTCELL56:OUT.26.TMIN
EN_VTCinputTCELL46:IMUX.BYP.6
INCinputTCELL56:IMUX.BYP.15
LDinputTCELL56:IMUX.BYP.14

Bel BITSLICE_CONTROL0

ultrascale XIPHY bel BITSLICE_CONTROL0
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL4:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1inputTCELL4:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2inputTCELL4:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3inputTCELL4:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0inputTCELL4:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1inputTCELL4:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2inputTCELL4:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3inputTCELL4:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0inputTCELL4:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1inputTCELL4:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2inputTCELL4:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3inputTCELL4:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0inputTCELL4:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1inputTCELL4:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2inputTCELL4:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3inputTCELL4:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0inputTCELL4:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1inputTCELL4:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2inputTCELL4:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3inputTCELL4:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0inputTCELL3:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1inputTCELL3:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2inputTCELL4:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3inputTCELL4:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0inputTCELL7:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL7:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL7:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL7:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL7:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL7:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL3:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0inputTCELL6:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL6:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL7:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL7:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL7:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL7:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL7:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL7:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL6:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL6:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL6:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL6:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL6:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL6:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL7:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL7:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL6:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL3:IMUX.BYP.10
CTRL_DLY_TEST_OUToutputTCELL3:OUT.17.TMIN
EN_VTCinputTCELL3:IMUX.BYP.9
MASTER_PD_OUToutputTCELL3:OUT.15.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL3:OUT.16.TMIN
PHY2CLB_PHY_RDYoutputTCELL3:OUT.14.TMIN
REFCLKinputTCELL3:IMUX.CTRL.5
RIU_CLKinputTCELL3:IMUX.CTRL.7

Bel BITSLICE_CONTROL1

ultrascale XIPHY bel BITSLICE_CONTROL1
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL11:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1inputTCELL11:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2inputTCELL11:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3inputTCELL11:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0inputTCELL11:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1inputTCELL11:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2inputTCELL11:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3inputTCELL11:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0inputTCELL11:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1inputTCELL11:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2inputTCELL11:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3inputTCELL11:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0inputTCELL10:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1inputTCELL10:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2inputTCELL10:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3inputTCELL10:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0inputTCELL10:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1inputTCELL10:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2inputTCELL10:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3inputTCELL10:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0inputTCELL10:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1inputTCELL10:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2inputTCELL10:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3inputTCELL10:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0inputTCELL7:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL7:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL7:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL7:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL7:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL7:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL10:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0inputTCELL6:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL6:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL7:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL7:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL7:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL7:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL7:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL7:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL6:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL6:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL6:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL6:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL6:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL6:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL7:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL7:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL6:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL12:IMUX.BYP.8
CTRL_DLY_TEST_OUToutputTCELL11:OUT.30.TMIN
EN_VTCinputTCELL12:IMUX.BYP.7
MASTER_PD_OUToutputTCELL11:OUT.28.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL11:OUT.29.TMIN
PHY2CLB_PHY_RDYoutputTCELL11:OUT.27.TMIN
REFCLKinputTCELL11:IMUX.CTRL.6
RIU_CLKinputTCELL12:IMUX.CTRL.2

Bel BITSLICE_CONTROL2

ultrascale XIPHY bel BITSLICE_CONTROL2
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL19:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1inputTCELL19:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2inputTCELL19:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3inputTCELL19:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0inputTCELL19:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1inputTCELL19:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2inputTCELL19:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3inputTCELL19:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0inputTCELL19:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1inputTCELL19:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2inputTCELL19:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3inputTCELL19:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0inputTCELL19:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1inputTCELL19:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2inputTCELL19:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3inputTCELL19:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0inputTCELL19:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1inputTCELL19:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2inputTCELL19:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3inputTCELL19:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0inputTCELL18:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1inputTCELL18:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2inputTCELL19:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3inputTCELL19:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0inputTCELL22:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL22:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL22:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL22:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL22:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL22:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL18:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0inputTCELL21:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL21:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL22:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL22:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL22:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL22:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL22:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL22:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL21:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL21:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL21:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL21:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL21:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL21:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL22:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL22:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL21:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL18:IMUX.BYP.10
CTRL_DLY_TEST_OUToutputTCELL18:OUT.17.TMIN
EN_VTCinputTCELL18:IMUX.BYP.9
MASTER_PD_OUToutputTCELL18:OUT.15.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL18:OUT.16.TMIN
PHY2CLB_PHY_RDYoutputTCELL18:OUT.14.TMIN
REFCLKinputTCELL18:IMUX.CTRL.5
RIU_CLKinputTCELL18:IMUX.CTRL.7

Bel BITSLICE_CONTROL3

ultrascale XIPHY bel BITSLICE_CONTROL3
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL26:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1inputTCELL26:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2inputTCELL26:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3inputTCELL26:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0inputTCELL26:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1inputTCELL26:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2inputTCELL26:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3inputTCELL26:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0inputTCELL26:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1inputTCELL26:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2inputTCELL26:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3inputTCELL26:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0inputTCELL25:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1inputTCELL25:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2inputTCELL25:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3inputTCELL25:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0inputTCELL25:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1inputTCELL25:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2inputTCELL25:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3inputTCELL25:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0inputTCELL25:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1inputTCELL25:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2inputTCELL25:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3inputTCELL25:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0inputTCELL22:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL22:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL22:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL22:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL22:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL22:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL25:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0inputTCELL21:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL21:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL22:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL22:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL22:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL22:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL22:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL22:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL21:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL21:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL21:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL21:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL21:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL21:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL22:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL22:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL21:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL27:IMUX.BYP.8
CTRL_DLY_TEST_OUToutputTCELL26:OUT.30.TMIN
EN_VTCinputTCELL27:IMUX.BYP.7
MASTER_PD_OUToutputTCELL26:OUT.28.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL26:OUT.29.TMIN
PHY2CLB_PHY_RDYoutputTCELL26:OUT.27.TMIN
REFCLKinputTCELL26:IMUX.CTRL.6
RIU_CLKinputTCELL27:IMUX.CTRL.2

Bel BITSLICE_CONTROL4

ultrascale XIPHY bel BITSLICE_CONTROL4
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL34:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1inputTCELL34:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2inputTCELL34:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3inputTCELL34:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0inputTCELL34:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1inputTCELL34:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2inputTCELL34:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3inputTCELL34:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0inputTCELL34:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1inputTCELL34:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2inputTCELL34:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3inputTCELL34:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0inputTCELL34:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1inputTCELL34:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2inputTCELL34:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3inputTCELL34:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0inputTCELL34:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1inputTCELL34:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2inputTCELL34:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3inputTCELL34:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0inputTCELL33:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1inputTCELL33:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2inputTCELL34:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3inputTCELL34:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0inputTCELL37:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL37:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL37:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL37:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL37:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL37:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL33:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0inputTCELL36:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL36:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL37:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL37:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL37:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL37:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL37:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL37:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL36:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL36:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL36:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL36:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL36:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL36:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL37:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL37:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL36:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL33:IMUX.BYP.10
CTRL_DLY_TEST_OUToutputTCELL33:OUT.17.TMIN
EN_VTCinputTCELL33:IMUX.BYP.9
MASTER_PD_OUToutputTCELL33:OUT.15.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL33:OUT.16.TMIN
PHY2CLB_PHY_RDYoutputTCELL33:OUT.14.TMIN
REFCLKinputTCELL33:IMUX.CTRL.5
RIU_CLKinputTCELL33:IMUX.CTRL.7

Bel BITSLICE_CONTROL5

ultrascale XIPHY bel BITSLICE_CONTROL5
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL41:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1inputTCELL41:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2inputTCELL41:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3inputTCELL41:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0inputTCELL41:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1inputTCELL41:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2inputTCELL41:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3inputTCELL41:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0inputTCELL41:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1inputTCELL41:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2inputTCELL41:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3inputTCELL41:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0inputTCELL40:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1inputTCELL40:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2inputTCELL40:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3inputTCELL40:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0inputTCELL40:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1inputTCELL40:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2inputTCELL40:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3inputTCELL40:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0inputTCELL40:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1inputTCELL40:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2inputTCELL40:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3inputTCELL40:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0inputTCELL37:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL37:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL37:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL37:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL37:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL37:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL40:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0inputTCELL36:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL36:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL37:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL37:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL37:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL37:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL37:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL37:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL36:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL36:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL36:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL36:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL36:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL36:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL37:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL37:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL36:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL42:IMUX.BYP.8
CTRL_DLY_TEST_OUToutputTCELL41:OUT.30.TMIN
EN_VTCinputTCELL42:IMUX.BYP.7
MASTER_PD_OUToutputTCELL41:OUT.28.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL41:OUT.29.TMIN
PHY2CLB_PHY_RDYoutputTCELL41:OUT.27.TMIN
REFCLKinputTCELL41:IMUX.CTRL.6
RIU_CLKinputTCELL42:IMUX.CTRL.2

Bel BITSLICE_CONTROL6

ultrascale XIPHY bel BITSLICE_CONTROL6
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL49:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1inputTCELL49:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2inputTCELL49:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3inputTCELL49:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0inputTCELL49:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1inputTCELL49:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2inputTCELL49:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3inputTCELL49:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0inputTCELL49:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1inputTCELL49:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2inputTCELL49:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3inputTCELL49:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0inputTCELL49:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1inputTCELL49:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2inputTCELL49:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3inputTCELL49:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0inputTCELL49:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1inputTCELL49:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2inputTCELL49:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3inputTCELL49:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0inputTCELL48:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1inputTCELL48:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2inputTCELL49:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3inputTCELL49:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0inputTCELL52:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL52:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL52:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL52:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL52:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL52:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL48:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0inputTCELL51:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL51:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL52:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL52:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL52:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL52:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL52:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL52:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL51:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL51:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL51:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL51:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL51:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL51:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL52:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL52:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL51:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL48:IMUX.BYP.10
CTRL_DLY_TEST_OUToutputTCELL48:OUT.17.TMIN
EN_VTCinputTCELL48:IMUX.BYP.9
MASTER_PD_OUToutputTCELL48:OUT.15.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL48:OUT.16.TMIN
PHY2CLB_PHY_RDYoutputTCELL48:OUT.14.TMIN
REFCLKinputTCELL48:IMUX.CTRL.5
RIU_CLKinputTCELL48:IMUX.CTRL.7

Bel BITSLICE_CONTROL7

ultrascale XIPHY bel BITSLICE_CONTROL7
PinDirectionWires
CLB2PHY_RDCS0_0inputTCELL56:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1inputTCELL56:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2inputTCELL56:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3inputTCELL56:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0inputTCELL56:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1inputTCELL56:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2inputTCELL56:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3inputTCELL56:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0inputTCELL56:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1inputTCELL56:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2inputTCELL56:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3inputTCELL56:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0inputTCELL55:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1inputTCELL55:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2inputTCELL55:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3inputTCELL55:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0inputTCELL55:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1inputTCELL55:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2inputTCELL55:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3inputTCELL55:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0inputTCELL55:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1inputTCELL55:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2inputTCELL55:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3inputTCELL55:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0inputTCELL52:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1inputTCELL52:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2inputTCELL52:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3inputTCELL52:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4inputTCELL52:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5inputTCELL52:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SELinputTCELL55:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0inputTCELL51:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1inputTCELL51:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10inputTCELL52:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11inputTCELL52:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12inputTCELL52:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13inputTCELL52:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14inputTCELL52:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15inputTCELL52:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2inputTCELL51:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3inputTCELL51:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4inputTCELL51:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5inputTCELL51:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6inputTCELL51:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7inputTCELL51:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8inputTCELL52:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9inputTCELL52:IMUX.IMUX.17.DELAY
CLB2RIU_WR_ENinputTCELL51:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_INinputTCELL57:IMUX.BYP.8
CTRL_DLY_TEST_OUToutputTCELL56:OUT.30.TMIN
EN_VTCinputTCELL57:IMUX.BYP.7
MASTER_PD_OUToutputTCELL56:OUT.28.TMIN
PHY2CLB_FIXDLY_RDYoutputTCELL56:OUT.29.TMIN
PHY2CLB_PHY_RDYoutputTCELL56:OUT.27.TMIN
REFCLKinputTCELL56:IMUX.CTRL.6
RIU_CLKinputTCELL57:IMUX.CTRL.2

Bel PLL_SELECT0

ultrascale XIPHY bel PLL_SELECT0
PinDirectionWires

Bel PLL_SELECT1

ultrascale XIPHY bel PLL_SELECT1
PinDirectionWires

Bel PLL_SELECT2

ultrascale XIPHY bel PLL_SELECT2
PinDirectionWires

Bel PLL_SELECT3

ultrascale XIPHY bel PLL_SELECT3
PinDirectionWires

Bel PLL_SELECT4

ultrascale XIPHY bel PLL_SELECT4
PinDirectionWires

Bel PLL_SELECT5

ultrascale XIPHY bel PLL_SELECT5
PinDirectionWires

Bel PLL_SELECT6

ultrascale XIPHY bel PLL_SELECT6
PinDirectionWires

Bel PLL_SELECT7

ultrascale XIPHY bel PLL_SELECT7
PinDirectionWires

Bel RIU_OR0

ultrascale XIPHY bel RIU_OR0
PinDirectionWires
RIU_RD_DATA0outputTCELL6:OUT.19.TMIN
RIU_RD_DATA1outputTCELL6:OUT.20.TMIN
RIU_RD_DATA10outputTCELL6:OUT.29.TMIN
RIU_RD_DATA11outputTCELL6:OUT.30.TMIN
RIU_RD_DATA12outputTCELL6:OUT.31.TMIN
RIU_RD_DATA13outputTCELL7:OUT.4.TMIN
RIU_RD_DATA14outputTCELL7:OUT.5.TMIN
RIU_RD_DATA15outputTCELL7:OUT.6.TMIN
RIU_RD_DATA2outputTCELL6:OUT.21.TMIN
RIU_RD_DATA3outputTCELL6:OUT.22.TMIN
RIU_RD_DATA4outputTCELL6:OUT.23.TMIN
RIU_RD_DATA5outputTCELL6:OUT.24.TMIN
RIU_RD_DATA6outputTCELL6:OUT.25.TMIN
RIU_RD_DATA7outputTCELL6:OUT.26.TMIN
RIU_RD_DATA8outputTCELL6:OUT.27.TMIN
RIU_RD_DATA9outputTCELL6:OUT.28.TMIN
RIU_RD_VALIDoutputTCELL6:OUT.18.TMIN

Bel RIU_OR1

ultrascale XIPHY bel RIU_OR1
PinDirectionWires
RIU_RD_DATA0outputTCELL21:OUT.19.TMIN
RIU_RD_DATA1outputTCELL21:OUT.20.TMIN
RIU_RD_DATA10outputTCELL21:OUT.29.TMIN
RIU_RD_DATA11outputTCELL21:OUT.30.TMIN
RIU_RD_DATA12outputTCELL21:OUT.31.TMIN
RIU_RD_DATA13outputTCELL22:OUT.4.TMIN
RIU_RD_DATA14outputTCELL22:OUT.5.TMIN
RIU_RD_DATA15outputTCELL22:OUT.6.TMIN
RIU_RD_DATA2outputTCELL21:OUT.21.TMIN
RIU_RD_DATA3outputTCELL21:OUT.22.TMIN
RIU_RD_DATA4outputTCELL21:OUT.23.TMIN
RIU_RD_DATA5outputTCELL21:OUT.24.TMIN
RIU_RD_DATA6outputTCELL21:OUT.25.TMIN
RIU_RD_DATA7outputTCELL21:OUT.26.TMIN
RIU_RD_DATA8outputTCELL21:OUT.27.TMIN
RIU_RD_DATA9outputTCELL21:OUT.28.TMIN
RIU_RD_VALIDoutputTCELL21:OUT.18.TMIN

Bel RIU_OR2

ultrascale XIPHY bel RIU_OR2
PinDirectionWires
RIU_RD_DATA0outputTCELL36:OUT.19.TMIN
RIU_RD_DATA1outputTCELL36:OUT.20.TMIN
RIU_RD_DATA10outputTCELL36:OUT.29.TMIN
RIU_RD_DATA11outputTCELL36:OUT.30.TMIN
RIU_RD_DATA12outputTCELL36:OUT.31.TMIN
RIU_RD_DATA13outputTCELL37:OUT.4.TMIN
RIU_RD_DATA14outputTCELL37:OUT.5.TMIN
RIU_RD_DATA15outputTCELL37:OUT.6.TMIN
RIU_RD_DATA2outputTCELL36:OUT.21.TMIN
RIU_RD_DATA3outputTCELL36:OUT.22.TMIN
RIU_RD_DATA4outputTCELL36:OUT.23.TMIN
RIU_RD_DATA5outputTCELL36:OUT.24.TMIN
RIU_RD_DATA6outputTCELL36:OUT.25.TMIN
RIU_RD_DATA7outputTCELL36:OUT.26.TMIN
RIU_RD_DATA8outputTCELL36:OUT.27.TMIN
RIU_RD_DATA9outputTCELL36:OUT.28.TMIN
RIU_RD_VALIDoutputTCELL36:OUT.18.TMIN

Bel RIU_OR3

ultrascale XIPHY bel RIU_OR3
PinDirectionWires
RIU_RD_DATA0outputTCELL51:OUT.19.TMIN
RIU_RD_DATA1outputTCELL51:OUT.20.TMIN
RIU_RD_DATA10outputTCELL51:OUT.29.TMIN
RIU_RD_DATA11outputTCELL51:OUT.30.TMIN
RIU_RD_DATA12outputTCELL51:OUT.31.TMIN
RIU_RD_DATA13outputTCELL52:OUT.4.TMIN
RIU_RD_DATA14outputTCELL52:OUT.5.TMIN
RIU_RD_DATA15outputTCELL52:OUT.6.TMIN
RIU_RD_DATA2outputTCELL51:OUT.21.TMIN
RIU_RD_DATA3outputTCELL51:OUT.22.TMIN
RIU_RD_DATA4outputTCELL51:OUT.23.TMIN
RIU_RD_DATA5outputTCELL51:OUT.24.TMIN
RIU_RD_DATA6outputTCELL51:OUT.25.TMIN
RIU_RD_DATA7outputTCELL51:OUT.26.TMIN
RIU_RD_DATA8outputTCELL51:OUT.27.TMIN
RIU_RD_DATA9outputTCELL51:OUT.28.TMIN
RIU_RD_VALIDoutputTCELL51:OUT.18.TMIN

Bel XIPHY_FEEDTHROUGH0

ultrascale XIPHY bel XIPHY_FEEDTHROUGH0
PinDirectionWires
CLB2PHY_CTRL_CLK_LOWinputTCELL3:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPPinputTCELL12:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUTinputTCELL7:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUTinputTCELL7:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_ENinputTCELL7:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0inputTCELL1:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1inputTCELL2:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10inputTCELL14:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11inputTCELL14:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12inputTCELL8:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2inputTCELL3:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3inputTCELL4:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4inputTCELL5:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5inputTCELL6:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6inputTCELL9:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7inputTCELL10:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8inputTCELL11:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9inputTCELL13:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2inputTCELL7:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4inputTCELL7:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDRinputTCELL7:IMUX.CTRL.2
CLB2PHY_SCAN_EN_BinputTCELL7:IMUX.BYP.14
CLB2PHY_SCAN_IN0inputTCELL6:IMUX.BYP.15
CLB2PHY_SCAN_IN1inputTCELL7:IMUX.BYP.6
CLB2PHY_SCAN_IN2inputTCELL7:IMUX.BYP.7
CLB2PHY_SCAN_IN3inputTCELL7:IMUX.BYP.8
CLB2PHY_SCAN_IN4inputTCELL7:IMUX.BYP.10
CLB2PHY_SCAN_IN5inputTCELL7:IMUX.BYP.11
CLB2PHY_SCAN_IN6inputTCELL7:IMUX.BYP.12
CLB2PHY_SCAN_IN7inputTCELL7:IMUX.BYP.13
CLB2PHY_SCAN_MODE_BinputTCELL6:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_BinputTCELL6:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_BinputTCELL7:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_BinputTCELL7:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_BinputTCELL7:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0inputTCELL6:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1inputTCELL6:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2inputTCELL6:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3inputTCELL6:IMUX.BYP.12
CTRL_RST_B_LOWinputTCELL3:IMUX.CTRL.6
CTRL_RST_B_UPPinputTCELL11:IMUX.CTRL.7
IDELAY_RST_B0inputTCELL0:IMUX.CTRL.6
IDELAY_RST_B1inputTCELL1:IMUX.CTRL.7
IDELAY_RST_B10inputTCELL13:IMUX.CTRL.7
IDELAY_RST_B11inputTCELL14:IMUX.CTRL.6
IDELAY_RST_B12inputTCELL8:IMUX.CTRL.3
IDELAY_RST_B2inputTCELL2:IMUX.CTRL.7
IDELAY_RST_B3inputTCELL4:IMUX.CTRL.6
IDELAY_RST_B4inputTCELL5:IMUX.CTRL.6
IDELAY_RST_B5inputTCELL6:IMUX.CTRL.5
IDELAY_RST_B6inputTCELL9:IMUX.CTRL.3
IDELAY_RST_B7inputTCELL10:IMUX.CTRL.2
IDELAY_RST_B8inputTCELL11:IMUX.CTRL.2
IDELAY_RST_B9inputTCELL12:IMUX.CTRL.7
ODELAY_RST_B0inputTCELL0:IMUX.CTRL.5
ODELAY_RST_B1inputTCELL1:IMUX.CTRL.6
ODELAY_RST_B10inputTCELL13:IMUX.CTRL.5
ODELAY_RST_B11inputTCELL14:IMUX.CTRL.5
ODELAY_RST_B12inputTCELL8:IMUX.CTRL.2
ODELAY_RST_B2inputTCELL2:IMUX.CTRL.6
ODELAY_RST_B3inputTCELL4:IMUX.CTRL.5
ODELAY_RST_B4inputTCELL5:IMUX.CTRL.4
ODELAY_RST_B5inputTCELL6:IMUX.CTRL.4
ODELAY_RST_B6inputTCELL8:IMUX.CTRL.7
ODELAY_RST_B7inputTCELL9:IMUX.CTRL.7
ODELAY_RST_B8inputTCELL10:IMUX.CTRL.7
ODELAY_RST_B9inputTCELL12:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUToutputTCELL7:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUToutputTCELL7:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUToutputTCELL7:OUT.15.TMIN
PHY2CLB_SCAN_OUT0outputTCELL7:OUT.7.TMIN
PHY2CLB_SCAN_OUT1outputTCELL7:OUT.8.TMIN
PHY2CLB_SCAN_OUT2outputTCELL7:OUT.9.TMIN
PHY2CLB_SCAN_OUT3outputTCELL7:OUT.10.TMIN
PHY2CLB_SCAN_OUT4outputTCELL7:OUT.11.TMIN
PHY2CLB_SCAN_OUT5outputTCELL7:OUT.12.TMIN
PHY2CLB_SCAN_OUT6outputTCELL7:OUT.13.TMIN
PHY2CLB_SCAN_OUT7outputTCELL7:OUT.14.TMIN
RXBIT_RST_B0inputTCELL0:IMUX.CTRL.4
RXBIT_RST_B1inputTCELL1:IMUX.CTRL.5
RXBIT_RST_B10inputTCELL13:IMUX.CTRL.4
RXBIT_RST_B11inputTCELL14:IMUX.CTRL.4
RXBIT_RST_B12inputTCELL7:IMUX.CTRL.6
RXBIT_RST_B2inputTCELL2:IMUX.CTRL.5
RXBIT_RST_B3inputTCELL4:IMUX.CTRL.3
RXBIT_RST_B4inputTCELL5:IMUX.CTRL.3
RXBIT_RST_B5inputTCELL6:IMUX.CTRL.3
RXBIT_RST_B6inputTCELL8:IMUX.CTRL.6
RXBIT_RST_B7inputTCELL9:IMUX.CTRL.6
RXBIT_RST_B8inputTCELL10:IMUX.CTRL.6
RXBIT_RST_B9inputTCELL12:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0inputTCELL3:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1inputTCELL11:IMUX.CTRL.5
TXBIT_RST_B0inputTCELL0:IMUX.CTRL.3
TXBIT_RST_B1inputTCELL1:IMUX.CTRL.4
TXBIT_RST_B10inputTCELL13:IMUX.CTRL.3
TXBIT_RST_B11inputTCELL14:IMUX.CTRL.3
TXBIT_RST_B12inputTCELL7:IMUX.CTRL.5
TXBIT_RST_B2inputTCELL2:IMUX.CTRL.4
TXBIT_RST_B3inputTCELL4:IMUX.CTRL.2
TXBIT_RST_B4inputTCELL5:IMUX.CTRL.2
TXBIT_RST_B5inputTCELL6:IMUX.CTRL.2
TXBIT_RST_B6inputTCELL8:IMUX.CTRL.5
TXBIT_RST_B7inputTCELL9:IMUX.CTRL.5
TXBIT_RST_B8inputTCELL10:IMUX.CTRL.5
TXBIT_RST_B9inputTCELL12:IMUX.CTRL.3
TXBIT_TRI_RST_B0inputTCELL0:IMUX.CTRL.2
TXBIT_TRI_RST_B1inputTCELL1:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH1

ultrascale XIPHY bel XIPHY_FEEDTHROUGH1
PinDirectionWires
CLB2PHY_CTRL_CLK_LOWinputTCELL18:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPPinputTCELL27:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUTinputTCELL22:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUTinputTCELL22:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_ENinputTCELL22:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0inputTCELL16:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1inputTCELL17:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10inputTCELL29:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11inputTCELL29:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12inputTCELL23:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2inputTCELL18:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3inputTCELL19:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4inputTCELL20:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5inputTCELL21:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6inputTCELL24:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7inputTCELL25:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8inputTCELL26:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9inputTCELL28:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2inputTCELL22:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4inputTCELL22:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDRinputTCELL22:IMUX.CTRL.2
CLB2PHY_SCAN_EN_BinputTCELL22:IMUX.BYP.14
CLB2PHY_SCAN_IN0inputTCELL21:IMUX.BYP.15
CLB2PHY_SCAN_IN1inputTCELL22:IMUX.BYP.6
CLB2PHY_SCAN_IN2inputTCELL22:IMUX.BYP.7
CLB2PHY_SCAN_IN3inputTCELL22:IMUX.BYP.8
CLB2PHY_SCAN_IN4inputTCELL22:IMUX.BYP.10
CLB2PHY_SCAN_IN5inputTCELL22:IMUX.BYP.11
CLB2PHY_SCAN_IN6inputTCELL22:IMUX.BYP.12
CLB2PHY_SCAN_IN7inputTCELL22:IMUX.BYP.13
CLB2PHY_SCAN_MODE_BinputTCELL21:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_BinputTCELL21:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_BinputTCELL22:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_BinputTCELL22:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_BinputTCELL22:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0inputTCELL21:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1inputTCELL21:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2inputTCELL21:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3inputTCELL21:IMUX.BYP.12
CTRL_RST_B_LOWinputTCELL18:IMUX.CTRL.6
CTRL_RST_B_UPPinputTCELL26:IMUX.CTRL.7
IDELAY_RST_B0inputTCELL15:IMUX.CTRL.6
IDELAY_RST_B1inputTCELL16:IMUX.CTRL.7
IDELAY_RST_B10inputTCELL28:IMUX.CTRL.7
IDELAY_RST_B11inputTCELL29:IMUX.CTRL.6
IDELAY_RST_B12inputTCELL23:IMUX.CTRL.3
IDELAY_RST_B2inputTCELL17:IMUX.CTRL.7
IDELAY_RST_B3inputTCELL19:IMUX.CTRL.6
IDELAY_RST_B4inputTCELL20:IMUX.CTRL.6
IDELAY_RST_B5inputTCELL21:IMUX.CTRL.5
IDELAY_RST_B6inputTCELL24:IMUX.CTRL.3
IDELAY_RST_B7inputTCELL25:IMUX.CTRL.2
IDELAY_RST_B8inputTCELL26:IMUX.CTRL.2
IDELAY_RST_B9inputTCELL27:IMUX.CTRL.7
ODELAY_RST_B0inputTCELL15:IMUX.CTRL.5
ODELAY_RST_B1inputTCELL16:IMUX.CTRL.6
ODELAY_RST_B10inputTCELL28:IMUX.CTRL.5
ODELAY_RST_B11inputTCELL29:IMUX.CTRL.5
ODELAY_RST_B12inputTCELL23:IMUX.CTRL.2
ODELAY_RST_B2inputTCELL17:IMUX.CTRL.6
ODELAY_RST_B3inputTCELL19:IMUX.CTRL.5
ODELAY_RST_B4inputTCELL20:IMUX.CTRL.4
ODELAY_RST_B5inputTCELL21:IMUX.CTRL.4
ODELAY_RST_B6inputTCELL23:IMUX.CTRL.7
ODELAY_RST_B7inputTCELL24:IMUX.CTRL.7
ODELAY_RST_B8inputTCELL25:IMUX.CTRL.7
ODELAY_RST_B9inputTCELL27:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUToutputTCELL22:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUToutputTCELL22:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUToutputTCELL22:OUT.15.TMIN
PHY2CLB_SCAN_OUT0outputTCELL22:OUT.7.TMIN
PHY2CLB_SCAN_OUT1outputTCELL22:OUT.8.TMIN
PHY2CLB_SCAN_OUT2outputTCELL22:OUT.9.TMIN
PHY2CLB_SCAN_OUT3outputTCELL22:OUT.10.TMIN
PHY2CLB_SCAN_OUT4outputTCELL22:OUT.11.TMIN
PHY2CLB_SCAN_OUT5outputTCELL22:OUT.12.TMIN
PHY2CLB_SCAN_OUT6outputTCELL22:OUT.13.TMIN
PHY2CLB_SCAN_OUT7outputTCELL22:OUT.14.TMIN
RXBIT_RST_B0inputTCELL15:IMUX.CTRL.4
RXBIT_RST_B1inputTCELL16:IMUX.CTRL.5
RXBIT_RST_B10inputTCELL28:IMUX.CTRL.4
RXBIT_RST_B11inputTCELL29:IMUX.CTRL.4
RXBIT_RST_B12inputTCELL22:IMUX.CTRL.6
RXBIT_RST_B2inputTCELL17:IMUX.CTRL.5
RXBIT_RST_B3inputTCELL19:IMUX.CTRL.3
RXBIT_RST_B4inputTCELL20:IMUX.CTRL.3
RXBIT_RST_B5inputTCELL21:IMUX.CTRL.3
RXBIT_RST_B6inputTCELL23:IMUX.CTRL.6
RXBIT_RST_B7inputTCELL24:IMUX.CTRL.6
RXBIT_RST_B8inputTCELL25:IMUX.CTRL.6
RXBIT_RST_B9inputTCELL27:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0inputTCELL18:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1inputTCELL26:IMUX.CTRL.5
TXBIT_RST_B0inputTCELL15:IMUX.CTRL.3
TXBIT_RST_B1inputTCELL16:IMUX.CTRL.4
TXBIT_RST_B10inputTCELL28:IMUX.CTRL.3
TXBIT_RST_B11inputTCELL29:IMUX.CTRL.3
TXBIT_RST_B12inputTCELL22:IMUX.CTRL.5
TXBIT_RST_B2inputTCELL17:IMUX.CTRL.4
TXBIT_RST_B3inputTCELL19:IMUX.CTRL.2
TXBIT_RST_B4inputTCELL20:IMUX.CTRL.2
TXBIT_RST_B5inputTCELL21:IMUX.CTRL.2
TXBIT_RST_B6inputTCELL23:IMUX.CTRL.5
TXBIT_RST_B7inputTCELL24:IMUX.CTRL.5
TXBIT_RST_B8inputTCELL25:IMUX.CTRL.5
TXBIT_RST_B9inputTCELL27:IMUX.CTRL.3
TXBIT_TRI_RST_B0inputTCELL15:IMUX.CTRL.2
TXBIT_TRI_RST_B1inputTCELL16:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH2

ultrascale XIPHY bel XIPHY_FEEDTHROUGH2
PinDirectionWires
CLB2PHY_CTRL_CLK_LOWinputTCELL33:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPPinputTCELL42:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUTinputTCELL37:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUTinputTCELL37:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_ENinputTCELL37:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0inputTCELL31:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1inputTCELL32:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10inputTCELL44:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11inputTCELL44:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12inputTCELL38:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2inputTCELL33:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3inputTCELL34:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4inputTCELL35:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5inputTCELL36:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6inputTCELL39:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7inputTCELL40:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8inputTCELL41:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9inputTCELL43:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2inputTCELL37:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4inputTCELL37:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDRinputTCELL37:IMUX.CTRL.2
CLB2PHY_SCAN_EN_BinputTCELL37:IMUX.BYP.14
CLB2PHY_SCAN_IN0inputTCELL36:IMUX.BYP.15
CLB2PHY_SCAN_IN1inputTCELL37:IMUX.BYP.6
CLB2PHY_SCAN_IN2inputTCELL37:IMUX.BYP.7
CLB2PHY_SCAN_IN3inputTCELL37:IMUX.BYP.8
CLB2PHY_SCAN_IN4inputTCELL37:IMUX.BYP.10
CLB2PHY_SCAN_IN5inputTCELL37:IMUX.BYP.11
CLB2PHY_SCAN_IN6inputTCELL37:IMUX.BYP.12
CLB2PHY_SCAN_IN7inputTCELL37:IMUX.BYP.13
CLB2PHY_SCAN_MODE_BinputTCELL36:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_BinputTCELL36:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_BinputTCELL37:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_BinputTCELL37:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_BinputTCELL37:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0inputTCELL36:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1inputTCELL36:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2inputTCELL36:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3inputTCELL36:IMUX.BYP.12
CTRL_RST_B_LOWinputTCELL33:IMUX.CTRL.6
CTRL_RST_B_UPPinputTCELL41:IMUX.CTRL.7
IDELAY_RST_B0inputTCELL30:IMUX.CTRL.6
IDELAY_RST_B1inputTCELL31:IMUX.CTRL.7
IDELAY_RST_B10inputTCELL43:IMUX.CTRL.7
IDELAY_RST_B11inputTCELL44:IMUX.CTRL.6
IDELAY_RST_B12inputTCELL38:IMUX.CTRL.3
IDELAY_RST_B2inputTCELL32:IMUX.CTRL.7
IDELAY_RST_B3inputTCELL34:IMUX.CTRL.6
IDELAY_RST_B4inputTCELL35:IMUX.CTRL.6
IDELAY_RST_B5inputTCELL36:IMUX.CTRL.5
IDELAY_RST_B6inputTCELL39:IMUX.CTRL.3
IDELAY_RST_B7inputTCELL40:IMUX.CTRL.2
IDELAY_RST_B8inputTCELL41:IMUX.CTRL.2
IDELAY_RST_B9inputTCELL42:IMUX.CTRL.7
ODELAY_RST_B0inputTCELL30:IMUX.CTRL.5
ODELAY_RST_B1inputTCELL31:IMUX.CTRL.6
ODELAY_RST_B10inputTCELL43:IMUX.CTRL.5
ODELAY_RST_B11inputTCELL44:IMUX.CTRL.5
ODELAY_RST_B12inputTCELL38:IMUX.CTRL.2
ODELAY_RST_B2inputTCELL32:IMUX.CTRL.6
ODELAY_RST_B3inputTCELL34:IMUX.CTRL.5
ODELAY_RST_B4inputTCELL35:IMUX.CTRL.4
ODELAY_RST_B5inputTCELL36:IMUX.CTRL.4
ODELAY_RST_B6inputTCELL38:IMUX.CTRL.7
ODELAY_RST_B7inputTCELL39:IMUX.CTRL.7
ODELAY_RST_B8inputTCELL40:IMUX.CTRL.7
ODELAY_RST_B9inputTCELL42:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUToutputTCELL37:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUToutputTCELL37:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUToutputTCELL37:OUT.15.TMIN
PHY2CLB_SCAN_OUT0outputTCELL37:OUT.7.TMIN
PHY2CLB_SCAN_OUT1outputTCELL37:OUT.8.TMIN
PHY2CLB_SCAN_OUT2outputTCELL37:OUT.9.TMIN
PHY2CLB_SCAN_OUT3outputTCELL37:OUT.10.TMIN
PHY2CLB_SCAN_OUT4outputTCELL37:OUT.11.TMIN
PHY2CLB_SCAN_OUT5outputTCELL37:OUT.12.TMIN
PHY2CLB_SCAN_OUT6outputTCELL37:OUT.13.TMIN
PHY2CLB_SCAN_OUT7outputTCELL37:OUT.14.TMIN
RXBIT_RST_B0inputTCELL30:IMUX.CTRL.4
RXBIT_RST_B1inputTCELL31:IMUX.CTRL.5
RXBIT_RST_B10inputTCELL43:IMUX.CTRL.4
RXBIT_RST_B11inputTCELL44:IMUX.CTRL.4
RXBIT_RST_B12inputTCELL37:IMUX.CTRL.6
RXBIT_RST_B2inputTCELL32:IMUX.CTRL.5
RXBIT_RST_B3inputTCELL34:IMUX.CTRL.3
RXBIT_RST_B4inputTCELL35:IMUX.CTRL.3
RXBIT_RST_B5inputTCELL36:IMUX.CTRL.3
RXBIT_RST_B6inputTCELL38:IMUX.CTRL.6
RXBIT_RST_B7inputTCELL39:IMUX.CTRL.6
RXBIT_RST_B8inputTCELL40:IMUX.CTRL.6
RXBIT_RST_B9inputTCELL42:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0inputTCELL33:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1inputTCELL41:IMUX.CTRL.5
TXBIT_RST_B0inputTCELL30:IMUX.CTRL.3
TXBIT_RST_B1inputTCELL31:IMUX.CTRL.4
TXBIT_RST_B10inputTCELL43:IMUX.CTRL.3
TXBIT_RST_B11inputTCELL44:IMUX.CTRL.3
TXBIT_RST_B12inputTCELL37:IMUX.CTRL.5
TXBIT_RST_B2inputTCELL32:IMUX.CTRL.4
TXBIT_RST_B3inputTCELL34:IMUX.CTRL.2
TXBIT_RST_B4inputTCELL35:IMUX.CTRL.2
TXBIT_RST_B5inputTCELL36:IMUX.CTRL.2
TXBIT_RST_B6inputTCELL38:IMUX.CTRL.5
TXBIT_RST_B7inputTCELL39:IMUX.CTRL.5
TXBIT_RST_B8inputTCELL40:IMUX.CTRL.5
TXBIT_RST_B9inputTCELL42:IMUX.CTRL.3
TXBIT_TRI_RST_B0inputTCELL30:IMUX.CTRL.2
TXBIT_TRI_RST_B1inputTCELL31:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH3

ultrascale XIPHY bel XIPHY_FEEDTHROUGH3
PinDirectionWires
CLB2PHY_CTRL_CLK_LOWinputTCELL48:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPPinputTCELL57:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUTinputTCELL52:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUTinputTCELL52:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_ENinputTCELL52:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0inputTCELL46:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1inputTCELL47:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10inputTCELL59:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11inputTCELL59:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12inputTCELL53:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2inputTCELL48:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3inputTCELL49:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4inputTCELL50:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5inputTCELL51:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6inputTCELL54:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7inputTCELL55:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8inputTCELL56:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9inputTCELL58:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2inputTCELL52:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4inputTCELL52:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDRinputTCELL52:IMUX.CTRL.2
CLB2PHY_SCAN_EN_BinputTCELL52:IMUX.BYP.14
CLB2PHY_SCAN_IN0inputTCELL51:IMUX.BYP.15
CLB2PHY_SCAN_IN1inputTCELL52:IMUX.BYP.6
CLB2PHY_SCAN_IN2inputTCELL52:IMUX.BYP.7
CLB2PHY_SCAN_IN3inputTCELL52:IMUX.BYP.8
CLB2PHY_SCAN_IN4inputTCELL52:IMUX.BYP.10
CLB2PHY_SCAN_IN5inputTCELL52:IMUX.BYP.11
CLB2PHY_SCAN_IN6inputTCELL52:IMUX.BYP.12
CLB2PHY_SCAN_IN7inputTCELL52:IMUX.BYP.13
CLB2PHY_SCAN_MODE_BinputTCELL51:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_BinputTCELL51:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_BinputTCELL52:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_BinputTCELL52:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_BinputTCELL52:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0inputTCELL51:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1inputTCELL51:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2inputTCELL51:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3inputTCELL51:IMUX.BYP.12
CTRL_RST_B_LOWinputTCELL48:IMUX.CTRL.6
CTRL_RST_B_UPPinputTCELL56:IMUX.CTRL.7
IDELAY_RST_B0inputTCELL45:IMUX.CTRL.6
IDELAY_RST_B1inputTCELL46:IMUX.CTRL.7
IDELAY_RST_B10inputTCELL58:IMUX.CTRL.7
IDELAY_RST_B11inputTCELL59:IMUX.CTRL.6
IDELAY_RST_B12inputTCELL53:IMUX.CTRL.3
IDELAY_RST_B2inputTCELL47:IMUX.CTRL.7
IDELAY_RST_B3inputTCELL49:IMUX.CTRL.6
IDELAY_RST_B4inputTCELL50:IMUX.CTRL.6
IDELAY_RST_B5inputTCELL51:IMUX.CTRL.5
IDELAY_RST_B6inputTCELL54:IMUX.CTRL.3
IDELAY_RST_B7inputTCELL55:IMUX.CTRL.2
IDELAY_RST_B8inputTCELL56:IMUX.CTRL.2
IDELAY_RST_B9inputTCELL57:IMUX.CTRL.7
ODELAY_RST_B0inputTCELL45:IMUX.CTRL.5
ODELAY_RST_B1inputTCELL46:IMUX.CTRL.6
ODELAY_RST_B10inputTCELL58:IMUX.CTRL.5
ODELAY_RST_B11inputTCELL59:IMUX.CTRL.5
ODELAY_RST_B12inputTCELL53:IMUX.CTRL.2
ODELAY_RST_B2inputTCELL47:IMUX.CTRL.6
ODELAY_RST_B3inputTCELL49:IMUX.CTRL.5
ODELAY_RST_B4inputTCELL50:IMUX.CTRL.4
ODELAY_RST_B5inputTCELL51:IMUX.CTRL.4
ODELAY_RST_B6inputTCELL53:IMUX.CTRL.7
ODELAY_RST_B7inputTCELL54:IMUX.CTRL.7
ODELAY_RST_B8inputTCELL55:IMUX.CTRL.7
ODELAY_RST_B9inputTCELL57:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUToutputTCELL52:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUToutputTCELL52:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUToutputTCELL52:OUT.15.TMIN
PHY2CLB_SCAN_OUT0outputTCELL52:OUT.7.TMIN
PHY2CLB_SCAN_OUT1outputTCELL52:OUT.8.TMIN
PHY2CLB_SCAN_OUT2outputTCELL52:OUT.9.TMIN
PHY2CLB_SCAN_OUT3outputTCELL52:OUT.10.TMIN
PHY2CLB_SCAN_OUT4outputTCELL52:OUT.11.TMIN
PHY2CLB_SCAN_OUT5outputTCELL52:OUT.12.TMIN
PHY2CLB_SCAN_OUT6outputTCELL52:OUT.13.TMIN
PHY2CLB_SCAN_OUT7outputTCELL52:OUT.14.TMIN
RXBIT_RST_B0inputTCELL45:IMUX.CTRL.4
RXBIT_RST_B1inputTCELL46:IMUX.CTRL.5
RXBIT_RST_B10inputTCELL58:IMUX.CTRL.4
RXBIT_RST_B11inputTCELL59:IMUX.CTRL.4
RXBIT_RST_B12inputTCELL52:IMUX.CTRL.6
RXBIT_RST_B2inputTCELL47:IMUX.CTRL.5
RXBIT_RST_B3inputTCELL49:IMUX.CTRL.3
RXBIT_RST_B4inputTCELL50:IMUX.CTRL.3
RXBIT_RST_B5inputTCELL51:IMUX.CTRL.3
RXBIT_RST_B6inputTCELL53:IMUX.CTRL.6
RXBIT_RST_B7inputTCELL54:IMUX.CTRL.6
RXBIT_RST_B8inputTCELL55:IMUX.CTRL.6
RXBIT_RST_B9inputTCELL57:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0inputTCELL48:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1inputTCELL56:IMUX.CTRL.5
TXBIT_RST_B0inputTCELL45:IMUX.CTRL.3
TXBIT_RST_B1inputTCELL46:IMUX.CTRL.4
TXBIT_RST_B10inputTCELL58:IMUX.CTRL.3
TXBIT_RST_B11inputTCELL59:IMUX.CTRL.3
TXBIT_RST_B12inputTCELL52:IMUX.CTRL.5
TXBIT_RST_B2inputTCELL47:IMUX.CTRL.4
TXBIT_RST_B3inputTCELL49:IMUX.CTRL.2
TXBIT_RST_B4inputTCELL50:IMUX.CTRL.2
TXBIT_RST_B5inputTCELL51:IMUX.CTRL.2
TXBIT_RST_B6inputTCELL53:IMUX.CTRL.5
TXBIT_RST_B7inputTCELL54:IMUX.CTRL.5
TXBIT_RST_B8inputTCELL55:IMUX.CTRL.5
TXBIT_RST_B9inputTCELL57:IMUX.CTRL.3
TXBIT_TRI_RST_B0inputTCELL45:IMUX.CTRL.2
TXBIT_TRI_RST_B1inputTCELL46:IMUX.CTRL.3

Bel ABUS_SWITCH_CMT

ultrascale XIPHY bel ABUS_SWITCH_CMT
PinDirectionWires

Bel wires

ultrascale XIPHY bel wires
WirePins
TCELL0:OUT.0.TMINPLL0.TESTOUT32
TCELL0:OUT.1.TMINPLL0.TESTOUT33
TCELL0:OUT.2.TMINPLL0.TESTOUT34
TCELL0:OUT.3.TMINPLL0.TESTOUT35
TCELL0:OUT.4.TMINBITSLICE0.PHY2CLB_FIFO_EMPTY
TCELL0:OUT.5.TMINBITSLICE0.RX_Q0
TCELL0:OUT.6.TMINBITSLICE0.RX_Q1
TCELL0:OUT.7.TMINBITSLICE0.RX_Q2
TCELL0:OUT.8.TMINBITSLICE0.RX_Q3
TCELL0:OUT.9.TMINBITSLICE0.RX_Q4
TCELL0:OUT.10.TMINBITSLICE0.RX_Q5
TCELL0:OUT.11.TMINBITSLICE0.RX_Q6
TCELL0:OUT.12.TMINBITSLICE0.RX_Q7
TCELL0:OUT.13.TMINBITSLICE0.TX_CNTVALUEOUT0
TCELL0:OUT.14.TMINBITSLICE0.TX_CNTVALUEOUT1
TCELL0:OUT.15.TMINBITSLICE0.TX_CNTVALUEOUT2
TCELL0:OUT.16.TMINBITSLICE0.TX_CNTVALUEOUT3
TCELL0:OUT.17.TMINBITSLICE0.TX_CNTVALUEOUT4
TCELL0:OUT.18.TMINBITSLICE0.TX_CNTVALUEOUT5
TCELL0:OUT.19.TMINBITSLICE0.TX_CNTVALUEOUT6
TCELL0:OUT.20.TMINBITSLICE0.TX_CNTVALUEOUT7
TCELL0:OUT.21.TMINBITSLICE0.TX_CNTVALUEOUT8
TCELL0:OUT.22.TMINBITSLICE0.TX_T_OUT
TCELL0:OUT.23.TMINBITSLICE0.RX_CNTVALUEOUT0
TCELL0:OUT.24.TMINBITSLICE0.RX_CNTVALUEOUT1
TCELL0:OUT.25.TMINBITSLICE0.RX_CNTVALUEOUT2
TCELL0:OUT.26.TMINBITSLICE0.RX_CNTVALUEOUT3
TCELL0:OUT.27.TMINBITSLICE0.RX_CNTVALUEOUT4
TCELL0:OUT.28.TMINBITSLICE0.RX_CNTVALUEOUT5
TCELL0:OUT.29.TMINBITSLICE0.RX_CNTVALUEOUT6
TCELL0:OUT.30.TMINBITSLICE0.RX_CNTVALUEOUT7
TCELL0:OUT.31.TMINBITSLICE0.RX_CNTVALUEOUT8
TCELL0:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.TXBIT_TRI_RST_B0
TCELL0:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.TXBIT_RST_B0
TCELL0:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.RXBIT_RST_B0
TCELL0:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.ODELAY_RST_B0
TCELL0:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.IDELAY_RST_B0
TCELL0:IMUX.BYP.0PLL0.TESTIN28
TCELL0:IMUX.BYP.1PLL0.TESTIN29
TCELL0:IMUX.BYP.2PLL0.TESTIN30
TCELL0:IMUX.BYP.3PLL0.TESTIN31
TCELL0:IMUX.BYP.6BITSLICE_T0.EN_VTC
TCELL0:IMUX.BYP.7BITSLICE0.TX_LD
TCELL0:IMUX.BYP.8BITSLICE0.TX_INC
TCELL0:IMUX.BYP.9BITSLICE0.TX_EN_VTC
TCELL0:IMUX.BYP.10BITSLICE0.TX_CE_ODELAY
TCELL0:IMUX.BYP.11BITSLICE0.RX_LD
TCELL0:IMUX.BYP.12BITSLICE0.RX_INC
TCELL0:IMUX.BYP.13BITSLICE0.RX_EN_VTC
TCELL0:IMUX.BYP.14BITSLICE0.RX_CE_IDELAY
TCELL0:IMUX.BYP.15BITSLICE0.DYN_DCI_OUT_INT
TCELL0:IMUX.IMUX.6.DELAYBITSLICE0.TX_CE_OFD
TCELL0:IMUX.IMUX.7.DELAYBITSLICE0.RX_CE_IFD
TCELL0:IMUX.IMUX.8.DELAYBITSLICE0.RX_DATAIN1
TCELL0:IMUX.IMUX.9.DELAYBITSLICE0.CLB2PHY_FIFO_RDEN
TCELL0:IMUX.IMUX.10.DELAYBITSLICE0.TX_D7
TCELL0:IMUX.IMUX.11.DELAYBITSLICE0.TX_D6
TCELL0:IMUX.IMUX.12.DELAYBITSLICE0.TX_D5
TCELL0:IMUX.IMUX.13.DELAYBITSLICE0.TX_D4
TCELL0:IMUX.IMUX.14.DELAYBITSLICE0.TX_D3
TCELL0:IMUX.IMUX.15.DELAYBITSLICE0.TX_D2
TCELL0:IMUX.IMUX.16.DELAYBITSLICE0.TX_T
TCELL1:OUT.0.TMINPLL0.TESTOUT28
TCELL1:OUT.1.TMINPLL0.TESTOUT29
TCELL1:OUT.2.TMINPLL0.TESTOUT30
TCELL1:OUT.3.TMINPLL0.TESTOUT31
TCELL1:OUT.4.TMINBITSLICE1.PHY2CLB_FIFO_EMPTY
TCELL1:OUT.5.TMINBITSLICE1.RX_Q0
TCELL1:OUT.6.TMINBITSLICE1.RX_Q1
TCELL1:OUT.7.TMINBITSLICE1.RX_Q2
TCELL1:OUT.8.TMINBITSLICE1.RX_Q3
TCELL1:OUT.9.TMINBITSLICE1.RX_Q4
TCELL1:OUT.10.TMINBITSLICE1.RX_Q5
TCELL1:OUT.11.TMINBITSLICE1.RX_Q6
TCELL1:OUT.12.TMINBITSLICE1.RX_Q7
TCELL1:OUT.13.TMINBITSLICE1.TX_CNTVALUEOUT0
TCELL1:OUT.14.TMINBITSLICE1.TX_CNTVALUEOUT1
TCELL1:OUT.15.TMINBITSLICE1.TX_CNTVALUEOUT2
TCELL1:OUT.16.TMINBITSLICE1.TX_CNTVALUEOUT3
TCELL1:OUT.17.TMINBITSLICE1.TX_CNTVALUEOUT4
TCELL1:OUT.18.TMINBITSLICE1.TX_CNTVALUEOUT5
TCELL1:OUT.19.TMINBITSLICE1.TX_CNTVALUEOUT6
TCELL1:OUT.20.TMINBITSLICE1.TX_CNTVALUEOUT7
TCELL1:OUT.21.TMINBITSLICE1.TX_CNTVALUEOUT8
TCELL1:OUT.22.TMINBITSLICE1.TX_T_OUT
TCELL1:OUT.23.TMINBITSLICE1.RX_CNTVALUEOUT0
TCELL1:OUT.24.TMINBITSLICE1.RX_CNTVALUEOUT1
TCELL1:OUT.25.TMINBITSLICE1.RX_CNTVALUEOUT2
TCELL1:OUT.26.TMINBITSLICE1.RX_CNTVALUEOUT3
TCELL1:OUT.27.TMINBITSLICE1.RX_CNTVALUEOUT4
TCELL1:OUT.28.TMINBITSLICE1.RX_CNTVALUEOUT5
TCELL1:OUT.29.TMINBITSLICE1.RX_CNTVALUEOUT6
TCELL1:OUT.30.TMINBITSLICE1.RX_CNTVALUEOUT7
TCELL1:OUT.31.TMINBITSLICE1.RX_CNTVALUEOUT8
TCELL1:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK0
TCELL1:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.TXBIT_TRI_RST_B1
TCELL1:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.TXBIT_RST_B1
TCELL1:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.RXBIT_RST_B1
TCELL1:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.ODELAY_RST_B1
TCELL1:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.IDELAY_RST_B1
TCELL1:IMUX.BYP.0PLL0.TESTIN24
TCELL1:IMUX.BYP.1PLL0.TESTIN25
TCELL1:IMUX.BYP.2PLL0.TESTIN26
TCELL1:IMUX.BYP.3PLL0.TESTIN27
TCELL1:IMUX.BYP.6BITSLICE_T1.EN_VTC
TCELL1:IMUX.BYP.7BITSLICE1.TX_LD
TCELL1:IMUX.BYP.8BITSLICE1.TX_INC
TCELL1:IMUX.BYP.9BITSLICE1.TX_EN_VTC
TCELL1:IMUX.BYP.10BITSLICE1.TX_CE_ODELAY
TCELL1:IMUX.BYP.11BITSLICE1.RX_LD
TCELL1:IMUX.BYP.12BITSLICE1.RX_INC
TCELL1:IMUX.BYP.13BITSLICE1.RX_EN_VTC
TCELL1:IMUX.BYP.14BITSLICE1.RX_CE_IDELAY
TCELL1:IMUX.BYP.15BITSLICE1.DYN_DCI_OUT_INT
TCELL1:IMUX.IMUX.0.DELAYPLL0.CLKOUTPHY_EN
TCELL1:IMUX.IMUX.6.DELAYBITSLICE0.TX_D1
TCELL1:IMUX.IMUX.7.DELAYBITSLICE0.TX_CNTVALUEIN0
TCELL1:IMUX.IMUX.8.DELAYBITSLICE0.TX_CNTVALUEIN1
TCELL1:IMUX.IMUX.9.DELAYBITSLICE0.TX_CNTVALUEIN2
TCELL1:IMUX.IMUX.10.DELAYBITSLICE0.TX_CNTVALUEIN3
TCELL1:IMUX.IMUX.11.DELAYBITSLICE0.TX_CNTVALUEIN4
TCELL1:IMUX.IMUX.12.DELAYBITSLICE0.TX_CNTVALUEIN5
TCELL1:IMUX.IMUX.13.DELAYBITSLICE0.TX_CNTVALUEIN6
TCELL1:IMUX.IMUX.14.DELAYBITSLICE0.TX_CNTVALUEIN7
TCELL1:IMUX.IMUX.15.DELAYBITSLICE0.TX_CNTVALUEIN8
TCELL1:IMUX.IMUX.16.DELAYBITSLICE0.TX_D0
TCELL2:OUT.0.TMINPLL0.TESTOUT24
TCELL2:OUT.1.TMINPLL0.TESTOUT25
TCELL2:OUT.2.TMINPLL0.TESTOUT26
TCELL2:OUT.3.TMINPLL0.TESTOUT27
TCELL2:OUT.4.TMINBITSLICE2.PHY2CLB_FIFO_EMPTY
TCELL2:OUT.5.TMINBITSLICE2.RX_Q0
TCELL2:OUT.6.TMINBITSLICE2.RX_Q1
TCELL2:OUT.7.TMINBITSLICE2.RX_Q2
TCELL2:OUT.8.TMINBITSLICE2.RX_Q3
TCELL2:OUT.9.TMINBITSLICE2.RX_Q4
TCELL2:OUT.10.TMINBITSLICE2.RX_Q5
TCELL2:OUT.11.TMINBITSLICE2.RX_Q6
TCELL2:OUT.12.TMINBITSLICE2.RX_Q7
TCELL2:OUT.13.TMINBITSLICE2.TX_CNTVALUEOUT0
TCELL2:OUT.14.TMINBITSLICE2.TX_CNTVALUEOUT1
TCELL2:OUT.15.TMINBITSLICE2.TX_CNTVALUEOUT2
TCELL2:OUT.16.TMINBITSLICE2.TX_CNTVALUEOUT3
TCELL2:OUT.17.TMINBITSLICE2.TX_CNTVALUEOUT4
TCELL2:OUT.18.TMINBITSLICE2.TX_CNTVALUEOUT5
TCELL2:OUT.19.TMINBITSLICE2.TX_CNTVALUEOUT6
TCELL2:OUT.20.TMINBITSLICE2.TX_CNTVALUEOUT7
TCELL2:OUT.21.TMINBITSLICE2.TX_CNTVALUEOUT8
TCELL2:OUT.22.TMINBITSLICE2.TX_T_OUT
TCELL2:OUT.23.TMINBITSLICE2.RX_CNTVALUEOUT0
TCELL2:OUT.24.TMINBITSLICE2.RX_CNTVALUEOUT1
TCELL2:OUT.25.TMINBITSLICE2.RX_CNTVALUEOUT2
TCELL2:OUT.26.TMINBITSLICE2.RX_CNTVALUEOUT3
TCELL2:OUT.27.TMINBITSLICE2.RX_CNTVALUEOUT4
TCELL2:OUT.28.TMINBITSLICE2.RX_CNTVALUEOUT5
TCELL2:OUT.29.TMINBITSLICE2.RX_CNTVALUEOUT6
TCELL2:OUT.30.TMINBITSLICE2.RX_CNTVALUEOUT7
TCELL2:OUT.31.TMINBITSLICE2.RX_CNTVALUEOUT8
TCELL2:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK1
TCELL2:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.TXBIT_RST_B2
TCELL2:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.RXBIT_RST_B2
TCELL2:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.ODELAY_RST_B2
TCELL2:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.IDELAY_RST_B2
TCELL2:IMUX.BYP.0PLL0.TESTIN20
TCELL2:IMUX.BYP.1PLL0.TESTIN21
TCELL2:IMUX.BYP.2PLL0.TESTIN22
TCELL2:IMUX.BYP.3PLL0.TESTIN23
TCELL2:IMUX.BYP.6BITSLICE2.TX_LD
TCELL2:IMUX.BYP.7BITSLICE2.TX_INC
TCELL2:IMUX.BYP.8BITSLICE2.TX_EN_VTC
TCELL2:IMUX.BYP.9BITSLICE2.TX_CE_ODELAY
TCELL2:IMUX.BYP.10BITSLICE2.RX_LD
TCELL2:IMUX.BYP.11BITSLICE2.RX_INC
TCELL2:IMUX.BYP.12BITSLICE2.RX_EN_VTC
TCELL2:IMUX.BYP.13BITSLICE2.RX_CE_IDELAY
TCELL2:IMUX.BYP.14BITSLICE2.DYN_DCI_OUT_INT
TCELL2:IMUX.BYP.15BITSLICE_T0.CE_OFD
TCELL2:IMUX.IMUX.6.DELAYBITSLICE1.TX_D1
TCELL2:IMUX.IMUX.7.DELAYBITSLICE1.TX_D3
TCELL2:IMUX.IMUX.8.DELAYBITSLICE1.TX_D7
TCELL2:IMUX.IMUX.9.DELAYBITSLICE1.TX_CNTVALUEIN1
TCELL2:IMUX.IMUX.10.DELAYBITSLICE1.TX_CNTVALUEIN5
TCELL2:IMUX.IMUX.11.DELAYBITSLICE1.TX_CNTVALUEIN7
TCELL2:IMUX.IMUX.12.DELAYBITSLICE1.RX_CNTVALUEIN2
TCELL2:IMUX.IMUX.13.DELAYBITSLICE1.RX_CNTVALUEIN4
TCELL2:IMUX.IMUX.14.DELAYBITSLICE1.RX_CNTVALUEIN8
TCELL2:IMUX.IMUX.15.DELAYBITSLICE2.TX_CE_OFD
TCELL2:IMUX.IMUX.16.DELAYBITSLICE0.RX_CNTVALUEIN0
TCELL2:IMUX.IMUX.17.DELAYBITSLICE0.RX_CNTVALUEIN1
TCELL2:IMUX.IMUX.18.DELAYBITSLICE0.RX_CNTVALUEIN2
TCELL2:IMUX.IMUX.19.DELAYBITSLICE0.RX_CNTVALUEIN3
TCELL2:IMUX.IMUX.20.DELAYBITSLICE0.RX_CNTVALUEIN4
TCELL2:IMUX.IMUX.21.DELAYBITSLICE0.RX_CNTVALUEIN5
TCELL2:IMUX.IMUX.22.DELAYBITSLICE0.RX_CNTVALUEIN6
TCELL2:IMUX.IMUX.23.DELAYBITSLICE0.RX_CNTVALUEIN7
TCELL2:IMUX.IMUX.24.DELAYBITSLICE0.RX_CNTVALUEIN8
TCELL2:IMUX.IMUX.25.DELAYBITSLICE1.TX_T
TCELL2:IMUX.IMUX.26.DELAYBITSLICE1.TX_CE_OFD
TCELL2:IMUX.IMUX.27.DELAYBITSLICE1.RX_CE_IFD
TCELL2:IMUX.IMUX.28.DELAYBITSLICE1.RX_DATAIN1
TCELL2:IMUX.IMUX.29.DELAYBITSLICE1.CLB2PHY_FIFO_RDEN
TCELL2:IMUX.IMUX.30.DELAYBITSLICE1.TX_D0
TCELL2:IMUX.IMUX.31.DELAYBITSLICE1.TX_D2
TCELL2:IMUX.IMUX.32.DELAYBITSLICE1.TX_D4
TCELL2:IMUX.IMUX.33.DELAYBITSLICE1.TX_D5
TCELL2:IMUX.IMUX.34.DELAYBITSLICE1.TX_D6
TCELL2:IMUX.IMUX.35.DELAYBITSLICE1.TX_CNTVALUEIN0
TCELL2:IMUX.IMUX.36.DELAYBITSLICE1.TX_CNTVALUEIN2
TCELL2:IMUX.IMUX.37.DELAYBITSLICE1.TX_CNTVALUEIN3
TCELL2:IMUX.IMUX.38.DELAYBITSLICE1.TX_CNTVALUEIN4
TCELL2:IMUX.IMUX.39.DELAYBITSLICE1.TX_CNTVALUEIN6
TCELL2:IMUX.IMUX.40.DELAYBITSLICE1.TX_CNTVALUEIN8
TCELL2:IMUX.IMUX.41.DELAYBITSLICE1.RX_CNTVALUEIN0
TCELL2:IMUX.IMUX.42.DELAYBITSLICE1.RX_CNTVALUEIN1
TCELL2:IMUX.IMUX.43.DELAYBITSLICE1.RX_CNTVALUEIN3
TCELL2:IMUX.IMUX.44.DELAYBITSLICE1.RX_CNTVALUEIN5
TCELL2:IMUX.IMUX.45.DELAYBITSLICE1.RX_CNTVALUEIN6
TCELL2:IMUX.IMUX.46.DELAYBITSLICE1.RX_CNTVALUEIN7
TCELL2:IMUX.IMUX.47.DELAYBITSLICE2.TX_T
TCELL3:OUT.0.TMINPLL0.TESTOUT20
TCELL3:OUT.1.TMINPLL0.TESTOUT21
TCELL3:OUT.2.TMINPLL0.TESTOUT22
TCELL3:OUT.3.TMINPLL0.TESTOUT23
TCELL3:OUT.4.TMINBITSLICE_T0.CNTVALUEOUT0
TCELL3:OUT.5.TMINBITSLICE_T0.CNTVALUEOUT1
TCELL3:OUT.6.TMINBITSLICE_T0.CNTVALUEOUT2
TCELL3:OUT.7.TMINBITSLICE_T0.CNTVALUEOUT3
TCELL3:OUT.8.TMINBITSLICE_T0.CNTVALUEOUT4
TCELL3:OUT.9.TMINBITSLICE_T0.CNTVALUEOUT5
TCELL3:OUT.10.TMINBITSLICE_T0.CNTVALUEOUT6
TCELL3:OUT.11.TMINBITSLICE_T0.CNTVALUEOUT7
TCELL3:OUT.12.TMINBITSLICE_T0.CNTVALUEOUT8
TCELL3:OUT.13.TMINBITSLICE3.TX_T_OUT
TCELL3:OUT.14.TMINBITSLICE_CONTROL0.PHY2CLB_PHY_RDY
TCELL3:OUT.15.TMINBITSLICE_CONTROL0.MASTER_PD_OUT
TCELL3:OUT.16.TMINBITSLICE_CONTROL0.PHY2CLB_FIXDLY_RDY
TCELL3:OUT.17.TMINBITSLICE_CONTROL0.CTRL_DLY_TEST_OUT
TCELL3:OUT.18.TMINBITSLICE3.PHY2CLB_FIFO_EMPTY
TCELL3:OUT.19.TMINBITSLICE3.RX_Q0
TCELL3:OUT.20.TMINBITSLICE3.RX_Q1
TCELL3:OUT.21.TMINBITSLICE3.RX_Q2
TCELL3:OUT.22.TMINBITSLICE3.RX_Q3
TCELL3:OUT.23.TMINBITSLICE3.RX_Q4
TCELL3:OUT.24.TMINBITSLICE3.RX_Q5
TCELL3:OUT.25.TMINBITSLICE3.RX_Q6
TCELL3:OUT.26.TMINBITSLICE3.RX_Q7
TCELL3:OUT.27.TMINBITSLICE3.TX_CNTVALUEOUT0
TCELL3:OUT.28.TMINBITSLICE3.TX_CNTVALUEOUT1
TCELL3:OUT.29.TMINBITSLICE3.TX_CNTVALUEOUT2
TCELL3:OUT.30.TMINBITSLICE3.TX_CNTVALUEOUT3
TCELL3:OUT.31.TMINBITSLICE3.TX_CNTVALUEOUT4
TCELL3:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK2
TCELL3:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.TRISTATE_ODELAY_RST_B0
TCELL3:IMUX.CTRL.5BITSLICE_CONTROL0.REFCLK
TCELL3:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.CTRL_RST_B_LOW
TCELL3:IMUX.CTRL.7BITSLICE_CONTROL0.RIU_CLK, XIPHY_FEEDTHROUGH0.CLB2PHY_CTRL_CLK_LOW
TCELL3:IMUX.BYP.0PLL0.TESTIN16
TCELL3:IMUX.BYP.1PLL0.TESTIN17
TCELL3:IMUX.BYP.2PLL0.TESTIN18
TCELL3:IMUX.BYP.3PLL0.TESTIN19
TCELL3:IMUX.BYP.6BITSLICE_T0.LD
TCELL3:IMUX.BYP.7BITSLICE_T0.INC
TCELL3:IMUX.BYP.8BITSLICE_T0.CE_ODELAY
TCELL3:IMUX.BYP.9BITSLICE_CONTROL0.EN_VTC
TCELL3:IMUX.BYP.10BITSLICE_CONTROL0.CTRL_DLY_TEST_IN
TCELL3:IMUX.BYP.12BITSLICE3.TX_LD
TCELL3:IMUX.BYP.13BITSLICE3.TX_INC
TCELL3:IMUX.BYP.14BITSLICE3.TX_EN_VTC
TCELL3:IMUX.BYP.15BITSLICE3.TX_CE_ODELAY
TCELL3:IMUX.IMUX.6.DELAYBITSLICE2.TX_CNTVALUEIN3
TCELL3:IMUX.IMUX.7.DELAYBITSLICE2.TX_CNTVALUEIN5
TCELL3:IMUX.IMUX.8.DELAYBITSLICE2.RX_CNTVALUEIN0
TCELL3:IMUX.IMUX.9.DELAYBITSLICE2.RX_CNTVALUEIN2
TCELL3:IMUX.IMUX.10.DELAYBITSLICE2.RX_CNTVALUEIN6
TCELL3:IMUX.IMUX.11.DELAYBITSLICE2.RX_CNTVALUEIN8
TCELL3:IMUX.IMUX.12.DELAYBITSLICE_T0.CNTVALUEIN3
TCELL3:IMUX.IMUX.13.DELAYBITSLICE_T0.CNTVALUEIN5
TCELL3:IMUX.IMUX.14.DELAYBITSLICE_CONTROL0.CLB2RIU_NIBBLE_SEL
TCELL3:IMUX.IMUX.15.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS1_1
TCELL3:IMUX.IMUX.16.DELAYBITSLICE2.RX_CE_IFD
TCELL3:IMUX.IMUX.17.DELAYBITSLICE2.RX_DATAIN1
TCELL3:IMUX.IMUX.18.DELAYBITSLICE2.CLB2PHY_FIFO_RDEN
TCELL3:IMUX.IMUX.20.DELAYBITSLICE2.TX_D0
TCELL3:IMUX.IMUX.21.DELAYBITSLICE2.TX_D1
TCELL3:IMUX.IMUX.22.DELAYBITSLICE2.TX_D2
TCELL3:IMUX.IMUX.23.DELAYBITSLICE2.TX_D3
TCELL3:IMUX.IMUX.24.DELAYBITSLICE2.TX_D4
TCELL3:IMUX.IMUX.25.DELAYBITSLICE2.TX_D5
TCELL3:IMUX.IMUX.26.DELAYBITSLICE2.TX_D6
TCELL3:IMUX.IMUX.27.DELAYBITSLICE2.TX_D7
TCELL3:IMUX.IMUX.28.DELAYBITSLICE2.TX_CNTVALUEIN0
TCELL3:IMUX.IMUX.29.DELAYBITSLICE2.TX_CNTVALUEIN1
TCELL3:IMUX.IMUX.30.DELAYBITSLICE2.TX_CNTVALUEIN2
TCELL3:IMUX.IMUX.31.DELAYBITSLICE2.TX_CNTVALUEIN4
TCELL3:IMUX.IMUX.32.DELAYBITSLICE2.TX_CNTVALUEIN6
TCELL3:IMUX.IMUX.33.DELAYBITSLICE2.TX_CNTVALUEIN7
TCELL3:IMUX.IMUX.34.DELAYBITSLICE2.TX_CNTVALUEIN8
TCELL3:IMUX.IMUX.35.DELAYBITSLICE2.RX_CNTVALUEIN1
TCELL3:IMUX.IMUX.36.DELAYBITSLICE2.RX_CNTVALUEIN3
TCELL3:IMUX.IMUX.37.DELAYBITSLICE2.RX_CNTVALUEIN4
TCELL3:IMUX.IMUX.38.DELAYBITSLICE2.RX_CNTVALUEIN5
TCELL3:IMUX.IMUX.39.DELAYBITSLICE2.RX_CNTVALUEIN7
TCELL3:IMUX.IMUX.40.DELAYBITSLICE_T0.CNTVALUEIN0
TCELL3:IMUX.IMUX.41.DELAYBITSLICE_T0.CNTVALUEIN1
TCELL3:IMUX.IMUX.42.DELAYBITSLICE_T0.CNTVALUEIN2
TCELL3:IMUX.IMUX.43.DELAYBITSLICE_T0.CNTVALUEIN4
TCELL3:IMUX.IMUX.44.DELAYBITSLICE_T0.CNTVALUEIN6
TCELL3:IMUX.IMUX.45.DELAYBITSLICE_T0.CNTVALUEIN7
TCELL3:IMUX.IMUX.46.DELAYBITSLICE_T0.CNTVALUEIN8
TCELL3:IMUX.IMUX.47.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS1_0
TCELL4:OUT.0.TMINPLL0.TESTOUT16
TCELL4:OUT.1.TMINPLL0.TESTOUT17
TCELL4:OUT.2.TMINPLL0.TESTOUT18
TCELL4:OUT.3.TMINPLL0.TESTOUT19
TCELL4:OUT.4.TMINBITSLICE3.TX_CNTVALUEOUT5
TCELL4:OUT.5.TMINBITSLICE3.TX_CNTVALUEOUT6
TCELL4:OUT.6.TMINBITSLICE3.TX_CNTVALUEOUT7
TCELL4:OUT.7.TMINBITSLICE3.TX_CNTVALUEOUT8
TCELL4:OUT.8.TMINBITSLICE4.TX_T_OUT
TCELL4:OUT.9.TMINBITSLICE3.RX_CNTVALUEOUT0
TCELL4:OUT.10.TMINBITSLICE3.RX_CNTVALUEOUT1
TCELL4:OUT.11.TMINBITSLICE3.RX_CNTVALUEOUT2
TCELL4:OUT.12.TMINBITSLICE3.RX_CNTVALUEOUT3
TCELL4:OUT.13.TMINBITSLICE3.RX_CNTVALUEOUT4
TCELL4:OUT.14.TMINBITSLICE3.RX_CNTVALUEOUT5
TCELL4:OUT.15.TMINBITSLICE3.RX_CNTVALUEOUT6
TCELL4:OUT.16.TMINBITSLICE3.RX_CNTVALUEOUT7
TCELL4:OUT.17.TMINBITSLICE3.RX_CNTVALUEOUT8
TCELL4:OUT.18.TMINBITSLICE4.PHY2CLB_FIFO_EMPTY
TCELL4:OUT.19.TMINBITSLICE4.RX_Q0
TCELL4:OUT.20.TMINBITSLICE4.RX_Q1
TCELL4:OUT.21.TMINBITSLICE4.RX_Q2
TCELL4:OUT.22.TMINBITSLICE4.RX_Q3
TCELL4:OUT.23.TMINBITSLICE4.RX_Q4
TCELL4:OUT.24.TMINBITSLICE4.RX_Q5
TCELL4:OUT.25.TMINBITSLICE4.RX_Q6
TCELL4:OUT.26.TMINBITSLICE4.RX_Q7
TCELL4:OUT.27.TMINBITSLICE4.TX_CNTVALUEOUT0
TCELL4:OUT.28.TMINBITSLICE4.TX_CNTVALUEOUT1
TCELL4:OUT.29.TMINBITSLICE4.TX_CNTVALUEOUT2
TCELL4:OUT.30.TMINBITSLICE4.TX_CNTVALUEOUT3
TCELL4:OUT.31.TMINBITSLICE4.TX_CNTVALUEOUT4
TCELL4:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.TXBIT_RST_B3
TCELL4:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.RXBIT_RST_B3
TCELL4:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.ODELAY_RST_B3
TCELL4:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.IDELAY_RST_B3
TCELL4:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK3
TCELL4:IMUX.BYP.0PLL0.TESTIN12
TCELL4:IMUX.BYP.1PLL0.TESTIN13
TCELL4:IMUX.BYP.2PLL0.TESTIN14
TCELL4:IMUX.BYP.3PLL0.TESTIN15
TCELL4:IMUX.BYP.6BITSLICE3.RX_LD
TCELL4:IMUX.BYP.7BITSLICE3.RX_INC
TCELL4:IMUX.BYP.8BITSLICE3.RX_EN_VTC
TCELL4:IMUX.BYP.9BITSLICE3.RX_CE_IDELAY
TCELL4:IMUX.BYP.10BITSLICE3.DYN_DCI_OUT_INT
TCELL4:IMUX.BYP.11BITSLICE4.TX_LD
TCELL4:IMUX.BYP.12BITSLICE4.TX_INC
TCELL4:IMUX.BYP.13BITSLICE4.TX_EN_VTC
TCELL4:IMUX.BYP.14BITSLICE4.TX_CE_ODELAY
TCELL4:IMUX.BYP.15BITSLICE4.RX_LD
TCELL4:IMUX.IMUX.6.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS1_1
TCELL4:IMUX.IMUX.7.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS1_3
TCELL4:IMUX.IMUX.8.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS0_3
TCELL4:IMUX.IMUX.9.DELAYBITSLICE3.TX_CE_OFD
TCELL4:IMUX.IMUX.10.DELAYBITSLICE3.TX_D0
TCELL4:IMUX.IMUX.11.DELAYBITSLICE3.TX_D2
TCELL4:IMUX.IMUX.12.DELAYBITSLICE3.TX_D6
TCELL4:IMUX.IMUX.13.DELAYBITSLICE3.TX_D7
TCELL4:IMUX.IMUX.14.DELAYBITSLICE3.TX_CNTVALUEIN3
TCELL4:IMUX.IMUX.15.DELAYBITSLICE3.TX_CNTVALUEIN5
TCELL4:IMUX.IMUX.16.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS1_2
TCELL4:IMUX.IMUX.17.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS1_3
TCELL4:IMUX.IMUX.18.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS0_0
TCELL4:IMUX.IMUX.19.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS0_1
TCELL4:IMUX.IMUX.20.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS0_2
TCELL4:IMUX.IMUX.21.DELAYBITSLICE_CONTROL0.CLB2PHY_WRCS0_3
TCELL4:IMUX.IMUX.22.DELAYBITSLICE_CONTROL0.CLB2PHY_T_B0
TCELL4:IMUX.IMUX.23.DELAYBITSLICE_CONTROL0.CLB2PHY_T_B1
TCELL4:IMUX.IMUX.24.DELAYBITSLICE_CONTROL0.CLB2PHY_T_B2
TCELL4:IMUX.IMUX.25.DELAYBITSLICE_CONTROL0.CLB2PHY_T_B3
TCELL4:IMUX.IMUX.26.DELAYBITSLICE_CONTROL0.CLB2PHY_RDEN0
TCELL4:IMUX.IMUX.27.DELAYBITSLICE_CONTROL0.CLB2PHY_RDEN1
TCELL4:IMUX.IMUX.28.DELAYBITSLICE_CONTROL0.CLB2PHY_RDEN2
TCELL4:IMUX.IMUX.29.DELAYBITSLICE_CONTROL0.CLB2PHY_RDEN3
TCELL4:IMUX.IMUX.30.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS1_0
TCELL4:IMUX.IMUX.31.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS1_2
TCELL4:IMUX.IMUX.32.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS0_0
TCELL4:IMUX.IMUX.33.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS0_1
TCELL4:IMUX.IMUX.34.DELAYBITSLICE_CONTROL0.CLB2PHY_RDCS0_2
TCELL4:IMUX.IMUX.35.DELAYBITSLICE3.TX_T
TCELL4:IMUX.IMUX.36.DELAYBITSLICE3.RX_CE_IFD
TCELL4:IMUX.IMUX.37.DELAYBITSLICE3.RX_DATAIN1
TCELL4:IMUX.IMUX.38.DELAYBITSLICE3.CLB2PHY_FIFO_RDEN
TCELL4:IMUX.IMUX.39.DELAYBITSLICE3.TX_D1
TCELL4:IMUX.IMUX.40.DELAYBITSLICE3.TX_D3
TCELL4:IMUX.IMUX.41.DELAYBITSLICE3.TX_D4
TCELL4:IMUX.IMUX.42.DELAYBITSLICE3.TX_D5
TCELL4:IMUX.IMUX.44.DELAYBITSLICE3.TX_CNTVALUEIN0
TCELL4:IMUX.IMUX.45.DELAYBITSLICE3.TX_CNTVALUEIN1
TCELL4:IMUX.IMUX.46.DELAYBITSLICE3.TX_CNTVALUEIN2
TCELL4:IMUX.IMUX.47.DELAYBITSLICE3.TX_CNTVALUEIN4
TCELL5:OUT.0.TMINPLL0.TESTOUT12
TCELL5:OUT.1.TMINPLL0.TESTOUT13
TCELL5:OUT.2.TMINPLL0.TESTOUT14
TCELL5:OUT.3.TMINPLL0.TESTOUT15
TCELL5:OUT.4.TMINBITSLICE4.TX_CNTVALUEOUT5
TCELL5:OUT.5.TMINBITSLICE4.TX_CNTVALUEOUT6
TCELL5:OUT.6.TMINBITSLICE4.TX_CNTVALUEOUT7
TCELL5:OUT.7.TMINBITSLICE4.TX_CNTVALUEOUT8
TCELL5:OUT.8.TMINBITSLICE5.TX_T_OUT
TCELL5:OUT.9.TMINBITSLICE4.RX_CNTVALUEOUT0
TCELL5:OUT.10.TMINBITSLICE4.RX_CNTVALUEOUT1
TCELL5:OUT.11.TMINBITSLICE4.RX_CNTVALUEOUT2
TCELL5:OUT.12.TMINBITSLICE4.RX_CNTVALUEOUT3
TCELL5:OUT.13.TMINBITSLICE4.RX_CNTVALUEOUT4
TCELL5:OUT.14.TMINBITSLICE4.RX_CNTVALUEOUT5
TCELL5:OUT.15.TMINBITSLICE4.RX_CNTVALUEOUT6
TCELL5:OUT.16.TMINBITSLICE4.RX_CNTVALUEOUT7
TCELL5:OUT.17.TMINBITSLICE4.RX_CNTVALUEOUT8
TCELL5:OUT.18.TMINBITSLICE5.PHY2CLB_FIFO_EMPTY
TCELL5:OUT.19.TMINBITSLICE5.RX_Q0
TCELL5:OUT.20.TMINBITSLICE5.RX_Q1
TCELL5:OUT.21.TMINBITSLICE5.RX_Q2
TCELL5:OUT.22.TMINBITSLICE5.RX_Q3
TCELL5:OUT.23.TMINBITSLICE5.RX_Q4
TCELL5:OUT.24.TMINBITSLICE5.RX_Q5
TCELL5:OUT.25.TMINBITSLICE5.RX_Q6
TCELL5:OUT.26.TMINBITSLICE5.RX_Q7
TCELL5:OUT.27.TMINBITSLICE5.TX_CNTVALUEOUT0
TCELL5:OUT.28.TMINBITSLICE5.TX_CNTVALUEOUT1
TCELL5:OUT.29.TMINBITSLICE5.TX_CNTVALUEOUT2
TCELL5:OUT.30.TMINBITSLICE5.TX_CNTVALUEOUT3
TCELL5:OUT.31.TMINBITSLICE5.TX_CNTVALUEOUT4
TCELL5:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.TXBIT_RST_B4
TCELL5:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.RXBIT_RST_B4
TCELL5:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.ODELAY_RST_B4
TCELL5:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.IDELAY_RST_B4
TCELL5:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK4
TCELL5:IMUX.BYP.0PLL0.TESTIN8
TCELL5:IMUX.BYP.1PLL0.TESTIN9
TCELL5:IMUX.BYP.2PLL0.TESTIN10
TCELL5:IMUX.BYP.3PLL0.TESTIN11
TCELL5:IMUX.BYP.6BITSLICE4.RX_INC
TCELL5:IMUX.BYP.7BITSLICE4.RX_EN_VTC
TCELL5:IMUX.BYP.8BITSLICE4.RX_CE_IDELAY
TCELL5:IMUX.BYP.9BITSLICE4.DYN_DCI_OUT_INT
TCELL5:IMUX.BYP.10BITSLICE5.TX_LD
TCELL5:IMUX.BYP.11BITSLICE5.TX_INC
TCELL5:IMUX.BYP.12BITSLICE5.TX_EN_VTC
TCELL5:IMUX.BYP.13BITSLICE5.TX_CE_ODELAY
TCELL5:IMUX.BYP.14BITSLICE5.RX_LD
TCELL5:IMUX.BYP.15BITSLICE5.RX_INC
TCELL5:IMUX.IMUX.6.DELAYBITSLICE4.RX_DATAIN1
TCELL5:IMUX.IMUX.7.DELAYBITSLICE4.TX_D0
TCELL5:IMUX.IMUX.8.DELAYBITSLICE4.TX_D4
TCELL5:IMUX.IMUX.9.DELAYBITSLICE4.TX_D6
TCELL5:IMUX.IMUX.10.DELAYBITSLICE4.TX_CNTVALUEIN2
TCELL5:IMUX.IMUX.11.DELAYBITSLICE4.TX_CNTVALUEIN4
TCELL5:IMUX.IMUX.12.DELAYBITSLICE4.TX_CNTVALUEIN8
TCELL5:IMUX.IMUX.13.DELAYBITSLICE4.RX_CNTVALUEIN1
TCELL5:IMUX.IMUX.14.DELAYBITSLICE4.RX_CNTVALUEIN5
TCELL5:IMUX.IMUX.15.DELAYBITSLICE4.RX_CNTVALUEIN7
TCELL5:IMUX.IMUX.16.DELAYBITSLICE3.TX_CNTVALUEIN6
TCELL5:IMUX.IMUX.17.DELAYBITSLICE3.TX_CNTVALUEIN7
TCELL5:IMUX.IMUX.18.DELAYBITSLICE3.TX_CNTVALUEIN8
TCELL5:IMUX.IMUX.19.DELAYBITSLICE3.RX_CNTVALUEIN0
TCELL5:IMUX.IMUX.20.DELAYBITSLICE3.RX_CNTVALUEIN1
TCELL5:IMUX.IMUX.21.DELAYBITSLICE3.RX_CNTVALUEIN2
TCELL5:IMUX.IMUX.22.DELAYBITSLICE3.RX_CNTVALUEIN3
TCELL5:IMUX.IMUX.23.DELAYBITSLICE3.RX_CNTVALUEIN4
TCELL5:IMUX.IMUX.24.DELAYBITSLICE3.RX_CNTVALUEIN5
TCELL5:IMUX.IMUX.25.DELAYBITSLICE3.RX_CNTVALUEIN6
TCELL5:IMUX.IMUX.26.DELAYBITSLICE3.RX_CNTVALUEIN7
TCELL5:IMUX.IMUX.27.DELAYBITSLICE3.RX_CNTVALUEIN8
TCELL5:IMUX.IMUX.28.DELAYBITSLICE4.TX_T
TCELL5:IMUX.IMUX.29.DELAYBITSLICE4.TX_CE_OFD
TCELL5:IMUX.IMUX.30.DELAYBITSLICE4.RX_CE_IFD
TCELL5:IMUX.IMUX.31.DELAYBITSLICE4.CLB2PHY_FIFO_RDEN
TCELL5:IMUX.IMUX.32.DELAYBITSLICE4.TX_D1
TCELL5:IMUX.IMUX.33.DELAYBITSLICE4.TX_D2
TCELL5:IMUX.IMUX.34.DELAYBITSLICE4.TX_D3
TCELL5:IMUX.IMUX.35.DELAYBITSLICE4.TX_D5
TCELL5:IMUX.IMUX.36.DELAYBITSLICE4.TX_D7
TCELL5:IMUX.IMUX.37.DELAYBITSLICE4.TX_CNTVALUEIN0
TCELL5:IMUX.IMUX.38.DELAYBITSLICE4.TX_CNTVALUEIN1
TCELL5:IMUX.IMUX.39.DELAYBITSLICE4.TX_CNTVALUEIN3
TCELL5:IMUX.IMUX.40.DELAYBITSLICE4.TX_CNTVALUEIN5
TCELL5:IMUX.IMUX.41.DELAYBITSLICE4.TX_CNTVALUEIN6
TCELL5:IMUX.IMUX.42.DELAYBITSLICE4.TX_CNTVALUEIN7
TCELL5:IMUX.IMUX.43.DELAYBITSLICE4.RX_CNTVALUEIN0
TCELL5:IMUX.IMUX.44.DELAYBITSLICE4.RX_CNTVALUEIN2
TCELL5:IMUX.IMUX.45.DELAYBITSLICE4.RX_CNTVALUEIN3
TCELL5:IMUX.IMUX.46.DELAYBITSLICE4.RX_CNTVALUEIN4
TCELL5:IMUX.IMUX.47.DELAYBITSLICE4.RX_CNTVALUEIN6
TCELL6:OUT.0.TMINPLL0.TESTOUT8
TCELL6:OUT.1.TMINPLL0.TESTOUT9
TCELL6:OUT.2.TMINPLL0.TESTOUT10
TCELL6:OUT.3.TMINPLL0.TESTOUT11
TCELL6:OUT.4.TMINBITSLICE5.TX_CNTVALUEOUT5
TCELL6:OUT.5.TMINBITSLICE5.TX_CNTVALUEOUT6
TCELL6:OUT.6.TMINBITSLICE5.TX_CNTVALUEOUT7
TCELL6:OUT.7.TMINBITSLICE5.TX_CNTVALUEOUT8
TCELL6:OUT.8.TMINBITSLICE6.TX_T_OUT
TCELL6:OUT.9.TMINBITSLICE5.RX_CNTVALUEOUT0
TCELL6:OUT.10.TMINBITSLICE5.RX_CNTVALUEOUT1
TCELL6:OUT.11.TMINBITSLICE5.RX_CNTVALUEOUT2
TCELL6:OUT.12.TMINBITSLICE5.RX_CNTVALUEOUT3
TCELL6:OUT.13.TMINBITSLICE5.RX_CNTVALUEOUT4
TCELL6:OUT.14.TMINBITSLICE5.RX_CNTVALUEOUT5
TCELL6:OUT.15.TMINBITSLICE5.RX_CNTVALUEOUT6
TCELL6:OUT.16.TMINBITSLICE5.RX_CNTVALUEOUT7
TCELL6:OUT.17.TMINBITSLICE5.RX_CNTVALUEOUT8
TCELL6:OUT.18.TMINRIU_OR0.RIU_RD_VALID
TCELL6:OUT.19.TMINRIU_OR0.RIU_RD_DATA0
TCELL6:OUT.20.TMINRIU_OR0.RIU_RD_DATA1
TCELL6:OUT.21.TMINRIU_OR0.RIU_RD_DATA2
TCELL6:OUT.22.TMINRIU_OR0.RIU_RD_DATA3
TCELL6:OUT.23.TMINRIU_OR0.RIU_RD_DATA4
TCELL6:OUT.24.TMINRIU_OR0.RIU_RD_DATA5
TCELL6:OUT.25.TMINRIU_OR0.RIU_RD_DATA6
TCELL6:OUT.26.TMINRIU_OR0.RIU_RD_DATA7
TCELL6:OUT.27.TMINRIU_OR0.RIU_RD_DATA8
TCELL6:OUT.28.TMINRIU_OR0.RIU_RD_DATA9
TCELL6:OUT.29.TMINRIU_OR0.RIU_RD_DATA10
TCELL6:OUT.30.TMINRIU_OR0.RIU_RD_DATA11
TCELL6:OUT.31.TMINRIU_OR0.RIU_RD_DATA12
TCELL6:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.TXBIT_RST_B5
TCELL6:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.RXBIT_RST_B5
TCELL6:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.ODELAY_RST_B5
TCELL6:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.IDELAY_RST_B5
TCELL6:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK5
TCELL6:IMUX.BYP.0PLL0.TESTIN4
TCELL6:IMUX.BYP.1PLL0.TESTIN5
TCELL6:IMUX.BYP.2PLL0.TESTIN6
TCELL6:IMUX.BYP.3PLL0.TESTIN7
TCELL6:IMUX.BYP.6BITSLICE5.RX_EN_VTC
TCELL6:IMUX.BYP.7BITSLICE5.RX_CE_IDELAY
TCELL6:IMUX.BYP.8BITSLICE5.DYN_DCI_OUT_INT
TCELL6:IMUX.BYP.9XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B0
TCELL6:IMUX.BYP.10XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B1
TCELL6:IMUX.BYP.11XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B2
TCELL6:IMUX.BYP.12XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B3
TCELL6:IMUX.BYP.13XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_RST_MASK_B
TCELL6:IMUX.BYP.14XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_MODE_B
TCELL6:IMUX.BYP.15XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN0
TCELL6:IMUX.IMUX.0.DELAYPLL0.SCANMODEB
TCELL6:IMUX.IMUX.6.DELAYBITSLICE5.TX_CNTVALUEIN1
TCELL6:IMUX.IMUX.7.DELAYBITSLICE5.TX_CNTVALUEIN3
TCELL6:IMUX.IMUX.8.DELAYBITSLICE5.TX_CNTVALUEIN7
TCELL6:IMUX.IMUX.10.DELAYBITSLICE5.RX_CNTVALUEIN3
TCELL6:IMUX.IMUX.11.DELAYBITSLICE5.RX_CNTVALUEIN5
TCELL6:IMUX.IMUX.12.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_EN, BITSLICE_CONTROL1.CLB2RIU_WR_EN
TCELL6:IMUX.IMUX.13.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA1, BITSLICE_CONTROL1.CLB2RIU_WR_DATA1
TCELL6:IMUX.IMUX.14.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA5, BITSLICE_CONTROL1.CLB2RIU_WR_DATA5
TCELL6:IMUX.IMUX.15.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA7, BITSLICE_CONTROL1.CLB2RIU_WR_DATA7
TCELL6:IMUX.IMUX.16.DELAYBITSLICE4.RX_CNTVALUEIN8
TCELL6:IMUX.IMUX.17.DELAYBITSLICE5.TX_T
TCELL6:IMUX.IMUX.18.DELAYBITSLICE5.TX_CE_OFD
TCELL6:IMUX.IMUX.19.DELAYBITSLICE5.RX_CE_IFD
TCELL6:IMUX.IMUX.20.DELAYBITSLICE5.RX_DATAIN1
TCELL6:IMUX.IMUX.21.DELAYBITSLICE5.CLB2PHY_FIFO_RDEN
TCELL6:IMUX.IMUX.22.DELAYBITSLICE5.TX_D0
TCELL6:IMUX.IMUX.23.DELAYBITSLICE5.TX_D1
TCELL6:IMUX.IMUX.24.DELAYBITSLICE5.TX_D2
TCELL6:IMUX.IMUX.25.DELAYBITSLICE5.TX_D3
TCELL6:IMUX.IMUX.26.DELAYBITSLICE5.TX_D4
TCELL6:IMUX.IMUX.27.DELAYBITSLICE5.TX_D5
TCELL6:IMUX.IMUX.28.DELAYBITSLICE5.TX_D6
TCELL6:IMUX.IMUX.29.DELAYBITSLICE5.TX_D7
TCELL6:IMUX.IMUX.30.DELAYBITSLICE5.TX_CNTVALUEIN0
TCELL6:IMUX.IMUX.31.DELAYBITSLICE5.TX_CNTVALUEIN2
TCELL6:IMUX.IMUX.32.DELAYBITSLICE5.TX_CNTVALUEIN4
TCELL6:IMUX.IMUX.33.DELAYBITSLICE5.TX_CNTVALUEIN5
TCELL6:IMUX.IMUX.34.DELAYBITSLICE5.TX_CNTVALUEIN6
TCELL6:IMUX.IMUX.35.DELAYBITSLICE5.TX_CNTVALUEIN8
TCELL6:IMUX.IMUX.36.DELAYBITSLICE5.RX_CNTVALUEIN0
TCELL6:IMUX.IMUX.37.DELAYBITSLICE5.RX_CNTVALUEIN1
TCELL6:IMUX.IMUX.38.DELAYBITSLICE5.RX_CNTVALUEIN2
TCELL6:IMUX.IMUX.39.DELAYBITSLICE5.RX_CNTVALUEIN4
TCELL6:IMUX.IMUX.40.DELAYBITSLICE5.RX_CNTVALUEIN6
TCELL6:IMUX.IMUX.41.DELAYBITSLICE5.RX_CNTVALUEIN7
TCELL6:IMUX.IMUX.42.DELAYBITSLICE5.RX_CNTVALUEIN8
TCELL6:IMUX.IMUX.43.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA0, BITSLICE_CONTROL1.CLB2RIU_WR_DATA0
TCELL6:IMUX.IMUX.44.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA2, BITSLICE_CONTROL1.CLB2RIU_WR_DATA2
TCELL6:IMUX.IMUX.45.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA3, BITSLICE_CONTROL1.CLB2RIU_WR_DATA3
TCELL6:IMUX.IMUX.46.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA4, BITSLICE_CONTROL1.CLB2RIU_WR_DATA4
TCELL6:IMUX.IMUX.47.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA6, BITSLICE_CONTROL1.CLB2RIU_WR_DATA6
TCELL7:OUT.0.TMINPLL0.TESTOUT4
TCELL7:OUT.1.TMINPLL0.TESTOUT5
TCELL7:OUT.2.TMINPLL0.TESTOUT6
TCELL7:OUT.3.TMINPLL0.TESTOUT7
TCELL7:OUT.4.TMINRIU_OR0.RIU_RD_DATA13
TCELL7:OUT.5.TMINRIU_OR0.RIU_RD_DATA14
TCELL7:OUT.6.TMINRIU_OR0.RIU_RD_DATA15
TCELL7:OUT.7.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT0
TCELL7:OUT.8.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT1
TCELL7:OUT.9.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT2
TCELL7:OUT.10.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT3
TCELL7:OUT.11.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT4
TCELL7:OUT.12.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT5
TCELL7:OUT.13.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT6
TCELL7:OUT.14.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT7
TCELL7:OUT.15.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_OUT
TCELL7:OUT.16.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_FLG_OUT
TCELL7:OUT.17.TMINXIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
TCELL7:OUT.18.TMINBITSLICE12.PHY2CLB_FIFO_EMPTY
TCELL7:OUT.19.TMINBITSLICE12.RX_Q0
TCELL7:OUT.20.TMINBITSLICE12.RX_Q1
TCELL7:OUT.21.TMINBITSLICE12.RX_Q2
TCELL7:OUT.22.TMINBITSLICE12.RX_Q3
TCELL7:OUT.23.TMINBITSLICE12.RX_Q4
TCELL7:OUT.24.TMINBITSLICE12.RX_Q5
TCELL7:OUT.25.TMINBITSLICE12.RX_Q6
TCELL7:OUT.26.TMINBITSLICE12.RX_Q7
TCELL7:OUT.27.TMINBITSLICE12.TX_CNTVALUEOUT0
TCELL7:OUT.28.TMINBITSLICE12.TX_CNTVALUEOUT1
TCELL7:OUT.29.TMINBITSLICE12.TX_CNTVALUEOUT2
TCELL7:OUT.30.TMINBITSLICE12.TX_CNTVALUEOUT3
TCELL7:OUT.31.TMINBITSLICE12.TX_CNTVALUEOUT4
TCELL7:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_SDR
TCELL7:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_DIV4
TCELL7:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_DIV2
TCELL7:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.TXBIT_RST_B12
TCELL7:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.RXBIT_RST_B12
TCELL7:IMUX.BYP.0PLL0.TESTIN0
TCELL7:IMUX.BYP.1PLL0.TESTIN1
TCELL7:IMUX.BYP.2PLL0.TESTIN2
TCELL7:IMUX.BYP.3PLL0.TESTIN3
TCELL7:IMUX.BYP.6XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN1
TCELL7:IMUX.BYP.7XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN2
TCELL7:IMUX.BYP.8XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN3
TCELL7:IMUX.BYP.10XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN4
TCELL7:IMUX.BYP.11XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN5
TCELL7:IMUX.BYP.12XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN6
TCELL7:IMUX.BYP.13XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN7
TCELL7:IMUX.BYP.14XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_EN_B
TCELL7:IMUX.BYP.15BITSLICE12.TX_LD
TCELL7:IMUX.IMUX.0.DELAYPLL0.SCANENB
TCELL7:IMUX.IMUX.6.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_TEST_DIV4_CLK_SEL_B
TCELL7:IMUX.IMUX.7.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CT_START_EN
TCELL7:IMUX.IMUX.8.DELAYBITSLICE12.TX_CE_OFD
TCELL7:IMUX.IMUX.9.DELAYBITSLICE12.RX_DATAIN1
TCELL7:IMUX.IMUX.10.DELAYBITSLICE12.TX_D2
TCELL7:IMUX.IMUX.11.DELAYBITSLICE12.TX_D4
TCELL7:IMUX.IMUX.12.DELAYBITSLICE12.TX_CNTVALUEIN0
TCELL7:IMUX.IMUX.13.DELAYBITSLICE12.TX_CNTVALUEIN2
TCELL7:IMUX.IMUX.14.DELAYBITSLICE12.TX_CNTVALUEIN6
TCELL7:IMUX.IMUX.15.DELAYBITSLICE12.TX_CNTVALUEIN8
TCELL7:IMUX.IMUX.16.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA8, BITSLICE_CONTROL1.CLB2RIU_WR_DATA8
TCELL7:IMUX.IMUX.17.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA9, BITSLICE_CONTROL1.CLB2RIU_WR_DATA9
TCELL7:IMUX.IMUX.18.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA10, BITSLICE_CONTROL1.CLB2RIU_WR_DATA10
TCELL7:IMUX.IMUX.19.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA11, BITSLICE_CONTROL1.CLB2RIU_WR_DATA11
TCELL7:IMUX.IMUX.20.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA12, BITSLICE_CONTROL1.CLB2RIU_WR_DATA12
TCELL7:IMUX.IMUX.21.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA13, BITSLICE_CONTROL1.CLB2RIU_WR_DATA13
TCELL7:IMUX.IMUX.22.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA14, BITSLICE_CONTROL1.CLB2RIU_WR_DATA14
TCELL7:IMUX.IMUX.23.DELAYBITSLICE_CONTROL0.CLB2RIU_WR_DATA15, BITSLICE_CONTROL1.CLB2RIU_WR_DATA15
TCELL7:IMUX.IMUX.24.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR0, BITSLICE_CONTROL1.CLB2RIU_ADDR0
TCELL7:IMUX.IMUX.25.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR1, BITSLICE_CONTROL1.CLB2RIU_ADDR1
TCELL7:IMUX.IMUX.26.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR2, BITSLICE_CONTROL1.CLB2RIU_ADDR2
TCELL7:IMUX.IMUX.27.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR3, BITSLICE_CONTROL1.CLB2RIU_ADDR3
TCELL7:IMUX.IMUX.28.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR4, BITSLICE_CONTROL1.CLB2RIU_ADDR4
TCELL7:IMUX.IMUX.29.DELAYBITSLICE_CONTROL0.CLB2RIU_ADDR5, BITSLICE_CONTROL1.CLB2RIU_ADDR5
TCELL7:IMUX.IMUX.30.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SDR_CLK_SEL_B
TCELL7:IMUX.IMUX.31.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_TEST_DIV2_CLK_SEL_B
TCELL7:IMUX.IMUX.32.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CLK_STOP_FLG_OUT
TCELL7:IMUX.IMUX.33.DELAYXIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
TCELL7:IMUX.IMUX.34.DELAYBITSLICE12.TX_T
TCELL7:IMUX.IMUX.35.DELAYBITSLICE12.RX_CE_IFD
TCELL7:IMUX.IMUX.36.DELAYBITSLICE12.CLB2PHY_FIFO_RDEN
TCELL7:IMUX.IMUX.37.DELAYBITSLICE12.TX_D0
TCELL7:IMUX.IMUX.38.DELAYBITSLICE12.TX_D1
TCELL7:IMUX.IMUX.39.DELAYBITSLICE12.TX_D3
TCELL7:IMUX.IMUX.40.DELAYBITSLICE12.TX_D5
TCELL7:IMUX.IMUX.41.DELAYBITSLICE12.TX_D6
TCELL7:IMUX.IMUX.42.DELAYBITSLICE12.TX_D7
TCELL7:IMUX.IMUX.43.DELAYBITSLICE12.TX_CNTVALUEIN1
TCELL7:IMUX.IMUX.44.DELAYBITSLICE12.TX_CNTVALUEIN3
TCELL7:IMUX.IMUX.45.DELAYBITSLICE12.TX_CNTVALUEIN4
TCELL7:IMUX.IMUX.46.DELAYBITSLICE12.TX_CNTVALUEIN5
TCELL7:IMUX.IMUX.47.DELAYBITSLICE12.TX_CNTVALUEIN7
TCELL8:OUT.0.TMINPLL0.TESTOUT0
TCELL8:OUT.1.TMINPLL0.TESTOUT1
TCELL8:OUT.2.TMINPLL0.TESTOUT2
TCELL8:OUT.3.TMINPLL0.TESTOUT3
TCELL8:OUT.4.TMINBITSLICE12.TX_CNTVALUEOUT5
TCELL8:OUT.5.TMINBITSLICE12.TX_CNTVALUEOUT6
TCELL8:OUT.6.TMINBITSLICE12.TX_CNTVALUEOUT7
TCELL8:OUT.7.TMINBITSLICE12.TX_CNTVALUEOUT8
TCELL8:OUT.8.TMINBITSLICE7.TX_T_OUT
TCELL8:OUT.9.TMINBITSLICE12.RX_CNTVALUEOUT0
TCELL8:OUT.10.TMINBITSLICE12.RX_CNTVALUEOUT1
TCELL8:OUT.11.TMINBITSLICE12.RX_CNTVALUEOUT2
TCELL8:OUT.12.TMINBITSLICE12.RX_CNTVALUEOUT3
TCELL8:OUT.13.TMINBITSLICE12.RX_CNTVALUEOUT4
TCELL8:OUT.14.TMINBITSLICE12.RX_CNTVALUEOUT5
TCELL8:OUT.15.TMINBITSLICE12.RX_CNTVALUEOUT6
TCELL8:OUT.16.TMINBITSLICE12.RX_CNTVALUEOUT7
TCELL8:OUT.17.TMINBITSLICE12.RX_CNTVALUEOUT8
TCELL8:OUT.18.TMINBITSLICE6.PHY2CLB_FIFO_EMPTY
TCELL8:OUT.19.TMINBITSLICE6.RX_Q0
TCELL8:OUT.20.TMINBITSLICE6.RX_Q1
TCELL8:OUT.21.TMINBITSLICE6.RX_Q2
TCELL8:OUT.22.TMINBITSLICE6.RX_Q3
TCELL8:OUT.23.TMINBITSLICE6.RX_Q4
TCELL8:OUT.24.TMINBITSLICE6.RX_Q5
TCELL8:OUT.25.TMINBITSLICE6.RX_Q6
TCELL8:OUT.26.TMINBITSLICE6.RX_Q7
TCELL8:OUT.27.TMINBITSLICE6.TX_CNTVALUEOUT0
TCELL8:OUT.28.TMINBITSLICE6.TX_CNTVALUEOUT1
TCELL8:OUT.29.TMINBITSLICE6.TX_CNTVALUEOUT2
TCELL8:OUT.30.TMINBITSLICE6.TX_CNTVALUEOUT3
TCELL8:OUT.31.TMINBITSLICE6.TX_CNTVALUEOUT4
TCELL8:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.ODELAY_RST_B12
TCELL8:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.IDELAY_RST_B12
TCELL8:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK12
TCELL8:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.TXBIT_RST_B6
TCELL8:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.RXBIT_RST_B6
TCELL8:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.ODELAY_RST_B6
TCELL8:IMUX.BYP.0PLL0.DADDR4
TCELL8:IMUX.BYP.1PLL0.DADDR5
TCELL8:IMUX.BYP.2PLL0.DADDR6
TCELL8:IMUX.BYP.6BITSLICE12.TX_INC
TCELL8:IMUX.BYP.7BITSLICE12.TX_EN_VTC
TCELL8:IMUX.BYP.8BITSLICE12.TX_CE_ODELAY
TCELL8:IMUX.BYP.9BITSLICE12.RX_LD
TCELL8:IMUX.BYP.10BITSLICE12.RX_INC
TCELL8:IMUX.BYP.11BITSLICE12.RX_EN_VTC
TCELL8:IMUX.BYP.12BITSLICE12.RX_CE_IDELAY
TCELL8:IMUX.BYP.13BITSLICE12.DYN_DCI_OUT_INT
TCELL8:IMUX.BYP.14BITSLICE6.TX_LD
TCELL8:IMUX.BYP.15BITSLICE6.TX_INC
TCELL8:IMUX.IMUX.0.DELAYPLL0.SCANIN
TCELL8:IMUX.IMUX.6.DELAYBITSLICE6.TX_D0
TCELL8:IMUX.IMUX.7.DELAYBITSLICE6.TX_D2
TCELL8:IMUX.IMUX.8.DELAYBITSLICE6.TX_D6
TCELL8:IMUX.IMUX.9.DELAYBITSLICE6.TX_CNTVALUEIN0
TCELL8:IMUX.IMUX.10.DELAYBITSLICE6.TX_CNTVALUEIN4
TCELL8:IMUX.IMUX.11.DELAYBITSLICE6.TX_CNTVALUEIN6
TCELL8:IMUX.IMUX.12.DELAYBITSLICE6.RX_CNTVALUEIN1
TCELL8:IMUX.IMUX.13.DELAYBITSLICE6.RX_CNTVALUEIN3
TCELL8:IMUX.IMUX.14.DELAYBITSLICE6.RX_CNTVALUEIN7
TCELL8:IMUX.IMUX.15.DELAYBITSLICE7.TX_T
TCELL8:IMUX.IMUX.16.DELAYBITSLICE12.RX_CNTVALUEIN0
TCELL8:IMUX.IMUX.17.DELAYBITSLICE12.RX_CNTVALUEIN1
TCELL8:IMUX.IMUX.18.DELAYBITSLICE12.RX_CNTVALUEIN2
TCELL8:IMUX.IMUX.19.DELAYBITSLICE12.RX_CNTVALUEIN3
TCELL8:IMUX.IMUX.20.DELAYBITSLICE12.RX_CNTVALUEIN4
TCELL8:IMUX.IMUX.21.DELAYBITSLICE12.RX_CNTVALUEIN5
TCELL8:IMUX.IMUX.22.DELAYBITSLICE12.RX_CNTVALUEIN6
TCELL8:IMUX.IMUX.23.DELAYBITSLICE12.RX_CNTVALUEIN7
TCELL8:IMUX.IMUX.24.DELAYBITSLICE12.RX_CNTVALUEIN8
TCELL8:IMUX.IMUX.25.DELAYBITSLICE6.TX_T
TCELL8:IMUX.IMUX.26.DELAYBITSLICE6.TX_CE_OFD
TCELL8:IMUX.IMUX.27.DELAYBITSLICE6.RX_CE_IFD
TCELL8:IMUX.IMUX.29.DELAYBITSLICE6.RX_DATAIN1
TCELL8:IMUX.IMUX.30.DELAYBITSLICE6.CLB2PHY_FIFO_RDEN
TCELL8:IMUX.IMUX.31.DELAYBITSLICE6.TX_D1
TCELL8:IMUX.IMUX.32.DELAYBITSLICE6.TX_D3
TCELL8:IMUX.IMUX.33.DELAYBITSLICE6.TX_D4
TCELL8:IMUX.IMUX.34.DELAYBITSLICE6.TX_D5
TCELL8:IMUX.IMUX.35.DELAYBITSLICE6.TX_D7
TCELL8:IMUX.IMUX.36.DELAYBITSLICE6.TX_CNTVALUEIN1
TCELL8:IMUX.IMUX.37.DELAYBITSLICE6.TX_CNTVALUEIN2
TCELL8:IMUX.IMUX.38.DELAYBITSLICE6.TX_CNTVALUEIN3
TCELL8:IMUX.IMUX.39.DELAYBITSLICE6.TX_CNTVALUEIN5
TCELL8:IMUX.IMUX.40.DELAYBITSLICE6.TX_CNTVALUEIN7
TCELL8:IMUX.IMUX.41.DELAYBITSLICE6.TX_CNTVALUEIN8
TCELL8:IMUX.IMUX.42.DELAYBITSLICE6.RX_CNTVALUEIN0
TCELL8:IMUX.IMUX.43.DELAYBITSLICE6.RX_CNTVALUEIN2
TCELL8:IMUX.IMUX.44.DELAYBITSLICE6.RX_CNTVALUEIN4
TCELL8:IMUX.IMUX.45.DELAYBITSLICE6.RX_CNTVALUEIN5
TCELL8:IMUX.IMUX.46.DELAYBITSLICE6.RX_CNTVALUEIN6
TCELL8:IMUX.IMUX.47.DELAYBITSLICE6.RX_CNTVALUEIN8
TCELL9:OUT.0.TMINPLL0.DOUT12
TCELL9:OUT.1.TMINPLL0.DOUT13
TCELL9:OUT.2.TMINPLL0.DOUT14
TCELL9:OUT.3.TMINPLL0.DOUT15
TCELL9:OUT.4.TMINBITSLICE6.TX_CNTVALUEOUT5
TCELL9:OUT.5.TMINBITSLICE6.TX_CNTVALUEOUT6
TCELL9:OUT.6.TMINBITSLICE6.TX_CNTVALUEOUT7
TCELL9:OUT.7.TMINBITSLICE6.TX_CNTVALUEOUT8
TCELL9:OUT.8.TMINBITSLICE8.TX_T_OUT
TCELL9:OUT.9.TMINBITSLICE6.RX_CNTVALUEOUT0
TCELL9:OUT.10.TMINBITSLICE6.RX_CNTVALUEOUT1
TCELL9:OUT.11.TMINBITSLICE6.RX_CNTVALUEOUT2
TCELL9:OUT.12.TMINBITSLICE6.RX_CNTVALUEOUT3
TCELL9:OUT.13.TMINBITSLICE6.RX_CNTVALUEOUT4
TCELL9:OUT.14.TMINBITSLICE6.RX_CNTVALUEOUT5
TCELL9:OUT.15.TMINBITSLICE6.RX_CNTVALUEOUT6
TCELL9:OUT.16.TMINBITSLICE6.RX_CNTVALUEOUT7
TCELL9:OUT.17.TMINBITSLICE6.RX_CNTVALUEOUT8
TCELL9:OUT.18.TMINBITSLICE7.PHY2CLB_FIFO_EMPTY
TCELL9:OUT.19.TMINBITSLICE7.RX_Q0
TCELL9:OUT.20.TMINBITSLICE7.RX_Q1
TCELL9:OUT.21.TMINBITSLICE7.RX_Q2
TCELL9:OUT.22.TMINBITSLICE7.RX_Q3
TCELL9:OUT.23.TMINBITSLICE7.RX_Q4
TCELL9:OUT.24.TMINBITSLICE7.RX_Q5
TCELL9:OUT.25.TMINBITSLICE7.RX_Q6
TCELL9:OUT.26.TMINBITSLICE7.RX_Q7
TCELL9:OUT.27.TMINBITSLICE7.TX_CNTVALUEOUT0
TCELL9:OUT.28.TMINBITSLICE7.TX_CNTVALUEOUT1
TCELL9:OUT.29.TMINBITSLICE7.TX_CNTVALUEOUT2
TCELL9:OUT.30.TMINBITSLICE7.TX_CNTVALUEOUT3
TCELL9:OUT.31.TMINBITSLICE7.TX_CNTVALUEOUT4
TCELL9:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.IDELAY_RST_B6
TCELL9:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK6
TCELL9:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.TXBIT_RST_B7
TCELL9:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.RXBIT_RST_B7
TCELL9:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.ODELAY_RST_B7
TCELL9:IMUX.BYP.0PLL0.DADDR0
TCELL9:IMUX.BYP.1PLL0.DADDR1
TCELL9:IMUX.BYP.2PLL0.DADDR2
TCELL9:IMUX.BYP.3PLL0.DADDR3
TCELL9:IMUX.BYP.6BITSLICE6.TX_EN_VTC
TCELL9:IMUX.BYP.7BITSLICE6.TX_CE_ODELAY
TCELL9:IMUX.BYP.8BITSLICE6.RX_LD
TCELL9:IMUX.BYP.9BITSLICE6.RX_INC
TCELL9:IMUX.BYP.10BITSLICE6.RX_EN_VTC
TCELL9:IMUX.BYP.11BITSLICE6.RX_CE_IDELAY
TCELL9:IMUX.BYP.12BITSLICE6.DYN_DCI_OUT_INT
TCELL9:IMUX.BYP.14BITSLICE7.TX_LD
TCELL9:IMUX.BYP.15BITSLICE7.TX_INC
TCELL9:IMUX.IMUX.6.DELAYBITSLICE7.TX_CNTVALUEIN3
TCELL9:IMUX.IMUX.7.DELAYBITSLICE7.TX_CNTVALUEIN5
TCELL9:IMUX.IMUX.8.DELAYBITSLICE7.RX_CNTVALUEIN0
TCELL9:IMUX.IMUX.9.DELAYBITSLICE7.RX_CNTVALUEIN2
TCELL9:IMUX.IMUX.10.DELAYBITSLICE7.RX_CNTVALUEIN6
TCELL9:IMUX.IMUX.11.DELAYBITSLICE7.RX_CNTVALUEIN8
TCELL9:IMUX.IMUX.12.DELAYBITSLICE8.RX_DATAIN1
TCELL9:IMUX.IMUX.13.DELAYBITSLICE8.TX_D0
TCELL9:IMUX.IMUX.14.DELAYBITSLICE8.TX_D4
TCELL9:IMUX.IMUX.15.DELAYBITSLICE8.TX_D6
TCELL9:IMUX.IMUX.16.DELAYBITSLICE7.TX_CE_OFD
TCELL9:IMUX.IMUX.17.DELAYBITSLICE7.RX_CE_IFD
TCELL9:IMUX.IMUX.18.DELAYBITSLICE7.RX_DATAIN1
TCELL9:IMUX.IMUX.19.DELAYBITSLICE7.CLB2PHY_FIFO_RDEN
TCELL9:IMUX.IMUX.20.DELAYBITSLICE7.TX_D0
TCELL9:IMUX.IMUX.21.DELAYBITSLICE7.TX_D1
TCELL9:IMUX.IMUX.22.DELAYBITSLICE7.TX_D2
TCELL9:IMUX.IMUX.23.DELAYBITSLICE7.TX_D3
TCELL9:IMUX.IMUX.24.DELAYBITSLICE7.TX_D4
TCELL9:IMUX.IMUX.25.DELAYBITSLICE7.TX_D5
TCELL9:IMUX.IMUX.26.DELAYBITSLICE7.TX_D6
TCELL9:IMUX.IMUX.27.DELAYBITSLICE7.TX_D7
TCELL9:IMUX.IMUX.28.DELAYBITSLICE7.TX_CNTVALUEIN0
TCELL9:IMUX.IMUX.29.DELAYBITSLICE7.TX_CNTVALUEIN1
TCELL9:IMUX.IMUX.30.DELAYBITSLICE7.TX_CNTVALUEIN2
TCELL9:IMUX.IMUX.31.DELAYBITSLICE7.TX_CNTVALUEIN4
TCELL9:IMUX.IMUX.32.DELAYBITSLICE7.TX_CNTVALUEIN6
TCELL9:IMUX.IMUX.33.DELAYBITSLICE7.TX_CNTVALUEIN7
TCELL9:IMUX.IMUX.34.DELAYBITSLICE7.TX_CNTVALUEIN8
TCELL9:IMUX.IMUX.35.DELAYBITSLICE7.RX_CNTVALUEIN1
TCELL9:IMUX.IMUX.36.DELAYBITSLICE7.RX_CNTVALUEIN3
TCELL9:IMUX.IMUX.37.DELAYBITSLICE7.RX_CNTVALUEIN4
TCELL9:IMUX.IMUX.38.DELAYBITSLICE7.RX_CNTVALUEIN5
TCELL9:IMUX.IMUX.39.DELAYBITSLICE7.RX_CNTVALUEIN7
TCELL9:IMUX.IMUX.40.DELAYBITSLICE8.TX_T
TCELL9:IMUX.IMUX.41.DELAYBITSLICE8.TX_CE_OFD
TCELL9:IMUX.IMUX.42.DELAYBITSLICE8.RX_CE_IFD
TCELL9:IMUX.IMUX.43.DELAYBITSLICE8.CLB2PHY_FIFO_RDEN
TCELL9:IMUX.IMUX.44.DELAYBITSLICE8.TX_D1
TCELL9:IMUX.IMUX.45.DELAYBITSLICE8.TX_D2
TCELL9:IMUX.IMUX.46.DELAYBITSLICE8.TX_D3
TCELL9:IMUX.IMUX.47.DELAYBITSLICE8.TX_D5
TCELL10:OUT.0.TMINPLL0.DOUT8
TCELL10:OUT.1.TMINPLL0.DOUT9
TCELL10:OUT.2.TMINPLL0.DOUT10
TCELL10:OUT.3.TMINPLL0.DOUT11
TCELL10:OUT.4.TMINBITSLICE7.TX_CNTVALUEOUT5
TCELL10:OUT.5.TMINBITSLICE7.TX_CNTVALUEOUT6
TCELL10:OUT.6.TMINBITSLICE7.TX_CNTVALUEOUT7
TCELL10:OUT.7.TMINBITSLICE7.TX_CNTVALUEOUT8
TCELL10:OUT.8.TMINBITSLICE9.TX_T_OUT
TCELL10:OUT.9.TMINBITSLICE7.RX_CNTVALUEOUT0
TCELL10:OUT.10.TMINBITSLICE7.RX_CNTVALUEOUT1
TCELL10:OUT.11.TMINBITSLICE7.RX_CNTVALUEOUT2
TCELL10:OUT.12.TMINBITSLICE7.RX_CNTVALUEOUT3
TCELL10:OUT.13.TMINBITSLICE7.RX_CNTVALUEOUT4
TCELL10:OUT.14.TMINBITSLICE7.RX_CNTVALUEOUT5
TCELL10:OUT.15.TMINBITSLICE7.RX_CNTVALUEOUT6
TCELL10:OUT.16.TMINBITSLICE7.RX_CNTVALUEOUT7
TCELL10:OUT.17.TMINBITSLICE7.RX_CNTVALUEOUT8
TCELL10:OUT.18.TMINBITSLICE8.PHY2CLB_FIFO_EMPTY
TCELL10:OUT.19.TMINBITSLICE8.RX_Q0
TCELL10:OUT.20.TMINBITSLICE8.RX_Q1
TCELL10:OUT.21.TMINBITSLICE8.RX_Q2
TCELL10:OUT.22.TMINBITSLICE8.RX_Q3
TCELL10:OUT.23.TMINBITSLICE8.RX_Q4
TCELL10:OUT.24.TMINBITSLICE8.RX_Q5
TCELL10:OUT.25.TMINBITSLICE8.RX_Q6
TCELL10:OUT.26.TMINBITSLICE8.RX_Q7
TCELL10:OUT.27.TMINBITSLICE8.TX_CNTVALUEOUT0
TCELL10:OUT.28.TMINBITSLICE8.TX_CNTVALUEOUT1
TCELL10:OUT.29.TMINBITSLICE8.TX_CNTVALUEOUT2
TCELL10:OUT.30.TMINBITSLICE8.TX_CNTVALUEOUT3
TCELL10:OUT.31.TMINBITSLICE8.TX_CNTVALUEOUT4
TCELL10:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.IDELAY_RST_B7
TCELL10:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK7
TCELL10:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.TXBIT_RST_B8
TCELL10:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.RXBIT_RST_B8
TCELL10:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.ODELAY_RST_B8
TCELL10:IMUX.BYP.0PLL0.DI12
TCELL10:IMUX.BYP.1PLL0.DI13
TCELL10:IMUX.BYP.2PLL0.DI14
TCELL10:IMUX.BYP.3PLL0.DI15
TCELL10:IMUX.BYP.6BITSLICE7.TX_EN_VTC
TCELL10:IMUX.BYP.7BITSLICE7.TX_CE_ODELAY
TCELL10:IMUX.BYP.8BITSLICE7.RX_LD
TCELL10:IMUX.BYP.9BITSLICE7.RX_INC
TCELL10:IMUX.BYP.10BITSLICE7.RX_EN_VTC
TCELL10:IMUX.BYP.11BITSLICE7.RX_CE_IDELAY
TCELL10:IMUX.BYP.12BITSLICE7.DYN_DCI_OUT_INT
TCELL10:IMUX.BYP.13BITSLICE8.TX_LD
TCELL10:IMUX.BYP.14BITSLICE8.TX_INC
TCELL10:IMUX.BYP.15BITSLICE8.TX_EN_VTC
TCELL10:IMUX.IMUX.0.DELAYPLL0.DWE
TCELL10:IMUX.IMUX.6.DELAYBITSLICE8.RX_CNTVALUEIN4
TCELL10:IMUX.IMUX.7.DELAYBITSLICE8.RX_CNTVALUEIN6
TCELL10:IMUX.IMUX.8.DELAYBITSLICE_T1.CNTVALUEIN1
TCELL10:IMUX.IMUX.9.DELAYBITSLICE_T1.CNTVALUEIN3
TCELL10:IMUX.IMUX.10.DELAYBITSLICE_T1.CNTVALUEIN7
TCELL10:IMUX.IMUX.11.DELAYBITSLICE_CONTROL1.CLB2RIU_NIBBLE_SEL
TCELL10:IMUX.IMUX.12.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS1_3
TCELL10:IMUX.IMUX.13.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS0_1
TCELL10:IMUX.IMUX.14.DELAYBITSLICE_CONTROL1.CLB2PHY_T_B1
TCELL10:IMUX.IMUX.15.DELAYBITSLICE_CONTROL1.CLB2PHY_T_B3
TCELL10:IMUX.IMUX.16.DELAYBITSLICE8.TX_D7
TCELL10:IMUX.IMUX.18.DELAYBITSLICE8.TX_CNTVALUEIN0
TCELL10:IMUX.IMUX.19.DELAYBITSLICE8.TX_CNTVALUEIN1
TCELL10:IMUX.IMUX.20.DELAYBITSLICE8.TX_CNTVALUEIN2
TCELL10:IMUX.IMUX.21.DELAYBITSLICE8.TX_CNTVALUEIN3
TCELL10:IMUX.IMUX.22.DELAYBITSLICE8.TX_CNTVALUEIN4
TCELL10:IMUX.IMUX.23.DELAYBITSLICE8.TX_CNTVALUEIN5
TCELL10:IMUX.IMUX.24.DELAYBITSLICE8.TX_CNTVALUEIN6
TCELL10:IMUX.IMUX.25.DELAYBITSLICE8.TX_CNTVALUEIN7
TCELL10:IMUX.IMUX.26.DELAYBITSLICE8.TX_CNTVALUEIN8
TCELL10:IMUX.IMUX.27.DELAYBITSLICE8.RX_CNTVALUEIN0
TCELL10:IMUX.IMUX.28.DELAYBITSLICE8.RX_CNTVALUEIN1
TCELL10:IMUX.IMUX.29.DELAYBITSLICE8.RX_CNTVALUEIN2
TCELL10:IMUX.IMUX.30.DELAYBITSLICE8.RX_CNTVALUEIN3
TCELL10:IMUX.IMUX.31.DELAYBITSLICE8.RX_CNTVALUEIN5
TCELL10:IMUX.IMUX.32.DELAYBITSLICE8.RX_CNTVALUEIN7
TCELL10:IMUX.IMUX.33.DELAYBITSLICE8.RX_CNTVALUEIN8
TCELL10:IMUX.IMUX.34.DELAYBITSLICE_T1.CNTVALUEIN0
TCELL10:IMUX.IMUX.35.DELAYBITSLICE_T1.CNTVALUEIN2
TCELL10:IMUX.IMUX.36.DELAYBITSLICE_T1.CNTVALUEIN4
TCELL10:IMUX.IMUX.37.DELAYBITSLICE_T1.CNTVALUEIN5
TCELL10:IMUX.IMUX.38.DELAYBITSLICE_T1.CNTVALUEIN6
TCELL10:IMUX.IMUX.39.DELAYBITSLICE_T1.CNTVALUEIN8
TCELL10:IMUX.IMUX.40.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS1_0
TCELL10:IMUX.IMUX.41.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS1_1
TCELL10:IMUX.IMUX.42.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS1_2
TCELL10:IMUX.IMUX.43.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS0_0
TCELL10:IMUX.IMUX.44.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS0_2
TCELL10:IMUX.IMUX.45.DELAYBITSLICE_CONTROL1.CLB2PHY_WRCS0_3
TCELL10:IMUX.IMUX.46.DELAYBITSLICE_CONTROL1.CLB2PHY_T_B0
TCELL10:IMUX.IMUX.47.DELAYBITSLICE_CONTROL1.CLB2PHY_T_B2
TCELL11:OUT.0.TMINPLL0.DOUT4
TCELL11:OUT.1.TMINPLL0.DOUT5
TCELL11:OUT.2.TMINPLL0.DOUT6
TCELL11:OUT.3.TMINPLL0.DOUT7
TCELL11:OUT.4.TMINBITSLICE8.TX_CNTVALUEOUT5
TCELL11:OUT.5.TMINBITSLICE8.TX_CNTVALUEOUT6
TCELL11:OUT.6.TMINBITSLICE8.TX_CNTVALUEOUT7
TCELL11:OUT.7.TMINBITSLICE8.TX_CNTVALUEOUT8
TCELL11:OUT.8.TMINBITSLICE10.TX_T_OUT
TCELL11:OUT.9.TMINBITSLICE8.RX_CNTVALUEOUT0
TCELL11:OUT.10.TMINBITSLICE8.RX_CNTVALUEOUT1
TCELL11:OUT.11.TMINBITSLICE8.RX_CNTVALUEOUT2
TCELL11:OUT.12.TMINBITSLICE8.RX_CNTVALUEOUT3
TCELL11:OUT.13.TMINBITSLICE8.RX_CNTVALUEOUT4
TCELL11:OUT.14.TMINBITSLICE8.RX_CNTVALUEOUT5
TCELL11:OUT.15.TMINBITSLICE8.RX_CNTVALUEOUT6
TCELL11:OUT.16.TMINBITSLICE8.RX_CNTVALUEOUT7
TCELL11:OUT.17.TMINBITSLICE8.RX_CNTVALUEOUT8
TCELL11:OUT.18.TMINBITSLICE_T1.CNTVALUEOUT0
TCELL11:OUT.19.TMINBITSLICE_T1.CNTVALUEOUT1
TCELL11:OUT.20.TMINBITSLICE_T1.CNTVALUEOUT2
TCELL11:OUT.21.TMINBITSLICE_T1.CNTVALUEOUT3
TCELL11:OUT.22.TMINBITSLICE_T1.CNTVALUEOUT4
TCELL11:OUT.23.TMINBITSLICE_T1.CNTVALUEOUT5
TCELL11:OUT.24.TMINBITSLICE_T1.CNTVALUEOUT6
TCELL11:OUT.25.TMINBITSLICE_T1.CNTVALUEOUT7
TCELL11:OUT.26.TMINBITSLICE_T1.CNTVALUEOUT8
TCELL11:OUT.27.TMINBITSLICE_CONTROL1.PHY2CLB_PHY_RDY
TCELL11:OUT.28.TMINBITSLICE_CONTROL1.MASTER_PD_OUT
TCELL11:OUT.29.TMINBITSLICE_CONTROL1.PHY2CLB_FIXDLY_RDY
TCELL11:OUT.30.TMINBITSLICE_CONTROL1.CTRL_DLY_TEST_OUT
TCELL11:OUT.31.TMINBITSLICE11.TX_T_OUT
TCELL11:IMUX.CTRL.0PLL0.DCLK_B
TCELL11:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.IDELAY_RST_B8
TCELL11:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK8
TCELL11:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.TRISTATE_ODELAY_RST_B1
TCELL11:IMUX.CTRL.6BITSLICE_CONTROL1.REFCLK
TCELL11:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.CTRL_RST_B_UPP
TCELL11:IMUX.BYP.0PLL0.DI8
TCELL11:IMUX.BYP.1PLL0.DI9
TCELL11:IMUX.BYP.2PLL0.DI10
TCELL11:IMUX.BYP.3PLL0.DI11
TCELL11:IMUX.BYP.6BITSLICE8.TX_CE_ODELAY
TCELL11:IMUX.BYP.8BITSLICE8.RX_LD
TCELL11:IMUX.BYP.9BITSLICE8.RX_INC
TCELL11:IMUX.BYP.10BITSLICE8.RX_EN_VTC
TCELL11:IMUX.BYP.11BITSLICE8.RX_CE_IDELAY
TCELL11:IMUX.BYP.12BITSLICE8.DYN_DCI_OUT_INT
TCELL11:IMUX.BYP.13BITSLICE_T1.CE_OFD
TCELL11:IMUX.BYP.14BITSLICE_T1.LD
TCELL11:IMUX.BYP.15BITSLICE_T1.INC
TCELL11:IMUX.IMUX.0.DELAYPLL0.DEN
TCELL11:IMUX.IMUX.6.DELAYBITSLICE9.RX_DATAIN1
TCELL11:IMUX.IMUX.7.DELAYBITSLICE9.TX_D0
TCELL11:IMUX.IMUX.8.DELAYBITSLICE9.TX_D4
TCELL11:IMUX.IMUX.9.DELAYBITSLICE9.TX_D6
TCELL11:IMUX.IMUX.10.DELAYBITSLICE9.TX_CNTVALUEIN2
TCELL11:IMUX.IMUX.11.DELAYBITSLICE9.TX_CNTVALUEIN4
TCELL11:IMUX.IMUX.12.DELAYBITSLICE9.TX_CNTVALUEIN7
TCELL11:IMUX.IMUX.13.DELAYBITSLICE9.RX_CNTVALUEIN0
TCELL11:IMUX.IMUX.14.DELAYBITSLICE9.RX_CNTVALUEIN4
TCELL11:IMUX.IMUX.15.DELAYBITSLICE9.RX_CNTVALUEIN6
TCELL11:IMUX.IMUX.16.DELAYBITSLICE_CONTROL1.CLB2PHY_RDEN0
TCELL11:IMUX.IMUX.17.DELAYBITSLICE_CONTROL1.CLB2PHY_RDEN1
TCELL11:IMUX.IMUX.18.DELAYBITSLICE_CONTROL1.CLB2PHY_RDEN2
TCELL11:IMUX.IMUX.19.DELAYBITSLICE_CONTROL1.CLB2PHY_RDEN3
TCELL11:IMUX.IMUX.20.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS1_0
TCELL11:IMUX.IMUX.21.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS1_1
TCELL11:IMUX.IMUX.22.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS1_2
TCELL11:IMUX.IMUX.23.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS1_3
TCELL11:IMUX.IMUX.24.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS0_0
TCELL11:IMUX.IMUX.25.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS0_1
TCELL11:IMUX.IMUX.26.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS0_2
TCELL11:IMUX.IMUX.27.DELAYBITSLICE_CONTROL1.CLB2PHY_RDCS0_3
TCELL11:IMUX.IMUX.28.DELAYBITSLICE9.TX_T
TCELL11:IMUX.IMUX.29.DELAYBITSLICE9.TX_CE_OFD
TCELL11:IMUX.IMUX.30.DELAYBITSLICE9.RX_CE_IFD
TCELL11:IMUX.IMUX.31.DELAYBITSLICE9.CLB2PHY_FIFO_RDEN
TCELL11:IMUX.IMUX.32.DELAYBITSLICE9.TX_D1
TCELL11:IMUX.IMUX.33.DELAYBITSLICE9.TX_D2
TCELL11:IMUX.IMUX.34.DELAYBITSLICE9.TX_D3
TCELL11:IMUX.IMUX.35.DELAYBITSLICE9.TX_D5
TCELL11:IMUX.IMUX.36.DELAYBITSLICE9.TX_D7
TCELL11:IMUX.IMUX.37.DELAYBITSLICE9.TX_CNTVALUEIN0
TCELL11:IMUX.IMUX.38.DELAYBITSLICE9.TX_CNTVALUEIN1
TCELL11:IMUX.IMUX.39.DELAYBITSLICE9.TX_CNTVALUEIN3
TCELL11:IMUX.IMUX.40.DELAYBITSLICE9.TX_CNTVALUEIN5
TCELL11:IMUX.IMUX.41.DELAYBITSLICE9.TX_CNTVALUEIN6
TCELL11:IMUX.IMUX.43.DELAYBITSLICE9.TX_CNTVALUEIN8
TCELL11:IMUX.IMUX.44.DELAYBITSLICE9.RX_CNTVALUEIN1
TCELL11:IMUX.IMUX.45.DELAYBITSLICE9.RX_CNTVALUEIN2
TCELL11:IMUX.IMUX.46.DELAYBITSLICE9.RX_CNTVALUEIN3
TCELL11:IMUX.IMUX.47.DELAYBITSLICE9.RX_CNTVALUEIN5
TCELL12:OUT.0.TMINPLL0.DOUT0
TCELL12:OUT.1.TMINPLL0.DOUT1
TCELL12:OUT.2.TMINPLL0.DOUT2
TCELL12:OUT.3.TMINPLL0.DOUT3
TCELL12:OUT.4.TMINBITSLICE9.PHY2CLB_FIFO_EMPTY
TCELL12:OUT.5.TMINBITSLICE9.RX_Q0
TCELL12:OUT.6.TMINBITSLICE9.RX_Q1
TCELL12:OUT.7.TMINBITSLICE9.RX_Q2
TCELL12:OUT.8.TMINBITSLICE9.RX_Q3
TCELL12:OUT.9.TMINBITSLICE9.RX_Q4
TCELL12:OUT.10.TMINBITSLICE9.RX_Q5
TCELL12:OUT.11.TMINBITSLICE9.RX_Q6
TCELL12:OUT.12.TMINBITSLICE9.RX_Q7
TCELL12:OUT.13.TMINBITSLICE9.TX_CNTVALUEOUT0
TCELL12:OUT.14.TMINBITSLICE9.TX_CNTVALUEOUT1
TCELL12:OUT.15.TMINBITSLICE9.TX_CNTVALUEOUT2
TCELL12:OUT.16.TMINBITSLICE9.TX_CNTVALUEOUT3
TCELL12:OUT.17.TMINBITSLICE9.TX_CNTVALUEOUT4
TCELL12:OUT.18.TMINBITSLICE9.TX_CNTVALUEOUT5
TCELL12:OUT.19.TMINBITSLICE9.TX_CNTVALUEOUT6
TCELL12:OUT.20.TMINBITSLICE9.TX_CNTVALUEOUT7
TCELL12:OUT.21.TMINBITSLICE9.TX_CNTVALUEOUT8
TCELL12:OUT.22.TMINBITSLICE12.TX_T_OUT
TCELL12:OUT.23.TMINBITSLICE9.RX_CNTVALUEOUT0
TCELL12:OUT.24.TMINBITSLICE9.RX_CNTVALUEOUT1
TCELL12:OUT.25.TMINBITSLICE9.RX_CNTVALUEOUT2
TCELL12:OUT.26.TMINBITSLICE9.RX_CNTVALUEOUT3
TCELL12:OUT.27.TMINBITSLICE9.RX_CNTVALUEOUT4
TCELL12:OUT.28.TMINBITSLICE9.RX_CNTVALUEOUT5
TCELL12:OUT.29.TMINBITSLICE9.RX_CNTVALUEOUT6
TCELL12:OUT.30.TMINBITSLICE9.RX_CNTVALUEOUT7
TCELL12:OUT.31.TMINBITSLICE9.RX_CNTVALUEOUT8
TCELL12:IMUX.CTRL.2BITSLICE_CONTROL1.RIU_CLK, XIPHY_FEEDTHROUGH0.CLB2PHY_CTRL_CLK_UPP
TCELL12:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.TXBIT_RST_B9
TCELL12:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.RXBIT_RST_B9
TCELL12:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.ODELAY_RST_B9
TCELL12:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.IDELAY_RST_B9
TCELL12:IMUX.BYP.0PLL0.DI4
TCELL12:IMUX.BYP.1PLL0.DI5
TCELL12:IMUX.BYP.2PLL0.DI6
TCELL12:IMUX.BYP.3PLL0.DI7
TCELL12:IMUX.BYP.6BITSLICE_T1.CE_ODELAY
TCELL12:IMUX.BYP.7BITSLICE_CONTROL1.EN_VTC
TCELL12:IMUX.BYP.8BITSLICE_CONTROL1.CTRL_DLY_TEST_IN
TCELL12:IMUX.BYP.9BITSLICE9.TX_LD
TCELL12:IMUX.BYP.10BITSLICE9.TX_INC
TCELL12:IMUX.BYP.11BITSLICE9.TX_EN_VTC
TCELL12:IMUX.BYP.12BITSLICE9.TX_CE_ODELAY
TCELL12:IMUX.BYP.13BITSLICE9.RX_LD
TCELL12:IMUX.BYP.14BITSLICE9.RX_INC
TCELL12:IMUX.BYP.15BITSLICE9.RX_EN_VTC
TCELL12:IMUX.IMUX.0.DELAYPLL0.PWRDWN
TCELL12:IMUX.IMUX.6.DELAYBITSLICE10.TX_CNTVALUEIN0
TCELL12:IMUX.IMUX.7.DELAYBITSLICE10.TX_CNTVALUEIN2
TCELL12:IMUX.IMUX.8.DELAYBITSLICE10.TX_CNTVALUEIN6
TCELL12:IMUX.IMUX.9.DELAYBITSLICE10.TX_CNTVALUEIN8
TCELL12:IMUX.IMUX.10.DELAYBITSLICE10.RX_CNTVALUEIN3
TCELL12:IMUX.IMUX.11.DELAYBITSLICE10.RX_CNTVALUEIN5
TCELL12:IMUX.IMUX.12.DELAYBITSLICE11.TX_T
TCELL12:IMUX.IMUX.13.DELAYBITSLICE11.RX_CE_IFD
TCELL12:IMUX.IMUX.14.DELAYBITSLICE11.TX_D1
TCELL12:IMUX.IMUX.15.DELAYBITSLICE11.TX_D3
TCELL12:IMUX.IMUX.16.DELAYBITSLICE9.RX_CNTVALUEIN7
TCELL12:IMUX.IMUX.17.DELAYBITSLICE9.RX_CNTVALUEIN8
TCELL12:IMUX.IMUX.18.DELAYBITSLICE10.TX_T
TCELL12:IMUX.IMUX.19.DELAYBITSLICE10.TX_CE_OFD
TCELL12:IMUX.IMUX.20.DELAYBITSLICE10.RX_CE_IFD
TCELL12:IMUX.IMUX.21.DELAYBITSLICE10.RX_DATAIN1
TCELL12:IMUX.IMUX.22.DELAYBITSLICE10.CLB2PHY_FIFO_RDEN
TCELL12:IMUX.IMUX.23.DELAYBITSLICE10.TX_D5
TCELL12:IMUX.IMUX.24.DELAYBITSLICE10.TX_D4
TCELL12:IMUX.IMUX.25.DELAYBITSLICE10.TX_D3
TCELL12:IMUX.IMUX.26.DELAYBITSLICE10.TX_D2
TCELL12:IMUX.IMUX.27.DELAYBITSLICE10.TX_D1
TCELL12:IMUX.IMUX.28.DELAYBITSLICE10.TX_D0
TCELL12:IMUX.IMUX.29.DELAYBITSLICE10.TX_D6
TCELL12:IMUX.IMUX.30.DELAYBITSLICE10.TX_D7
TCELL12:IMUX.IMUX.31.DELAYBITSLICE10.TX_CNTVALUEIN1
TCELL12:IMUX.IMUX.32.DELAYBITSLICE10.TX_CNTVALUEIN3
TCELL12:IMUX.IMUX.33.DELAYBITSLICE10.TX_CNTVALUEIN4
TCELL12:IMUX.IMUX.34.DELAYBITSLICE10.TX_CNTVALUEIN5
TCELL12:IMUX.IMUX.35.DELAYBITSLICE10.TX_CNTVALUEIN7
TCELL12:IMUX.IMUX.36.DELAYBITSLICE10.RX_CNTVALUEIN0
TCELL12:IMUX.IMUX.37.DELAYBITSLICE10.RX_CNTVALUEIN1
TCELL12:IMUX.IMUX.38.DELAYBITSLICE10.RX_CNTVALUEIN2
TCELL12:IMUX.IMUX.39.DELAYBITSLICE10.RX_CNTVALUEIN4
TCELL12:IMUX.IMUX.40.DELAYBITSLICE10.RX_CNTVALUEIN6
TCELL12:IMUX.IMUX.41.DELAYBITSLICE10.RX_CNTVALUEIN7
TCELL12:IMUX.IMUX.42.DELAYBITSLICE10.RX_CNTVALUEIN8
TCELL12:IMUX.IMUX.43.DELAYBITSLICE11.TX_CE_OFD
TCELL12:IMUX.IMUX.44.DELAYBITSLICE11.RX_DATAIN1
TCELL12:IMUX.IMUX.45.DELAYBITSLICE11.CLB2PHY_FIFO_RDEN
TCELL12:IMUX.IMUX.46.DELAYBITSLICE11.TX_D0
TCELL12:IMUX.IMUX.47.DELAYBITSLICE11.TX_D2
TCELL13:OUT.0.TMINPLL0.DRDY
TCELL13:OUT.1.TMINPLL0.LOCKED
TCELL13:OUT.2.TMINPLL0.TESTOUT36
TCELL13:OUT.3.TMINPLL0.SCANOUT
TCELL13:OUT.4.TMINBITSLICE10.PHY2CLB_FIFO_EMPTY
TCELL13:OUT.5.TMINBITSLICE10.RX_Q0
TCELL13:OUT.6.TMINBITSLICE10.RX_Q1
TCELL13:OUT.7.TMINBITSLICE10.RX_Q2
TCELL13:OUT.8.TMINBITSLICE10.RX_Q3
TCELL13:OUT.9.TMINBITSLICE10.RX_Q4
TCELL13:OUT.10.TMINBITSLICE10.RX_Q5
TCELL13:OUT.11.TMINBITSLICE10.RX_Q6
TCELL13:OUT.12.TMINBITSLICE10.RX_Q7
TCELL13:OUT.13.TMINBITSLICE10.TX_CNTVALUEOUT0
TCELL13:OUT.14.TMINBITSLICE10.TX_CNTVALUEOUT1
TCELL13:OUT.15.TMINBITSLICE10.TX_CNTVALUEOUT2
TCELL13:OUT.16.TMINBITSLICE10.TX_CNTVALUEOUT3
TCELL13:OUT.17.TMINBITSLICE10.TX_CNTVALUEOUT4
TCELL13:OUT.18.TMINBITSLICE10.TX_CNTVALUEOUT5
TCELL13:OUT.19.TMINBITSLICE10.TX_CNTVALUEOUT6
TCELL13:OUT.20.TMINBITSLICE10.TX_CNTVALUEOUT7
TCELL13:OUT.21.TMINBITSLICE10.TX_CNTVALUEOUT8
TCELL13:OUT.23.TMINBITSLICE10.RX_CNTVALUEOUT0
TCELL13:OUT.24.TMINBITSLICE10.RX_CNTVALUEOUT1
TCELL13:OUT.25.TMINBITSLICE10.RX_CNTVALUEOUT2
TCELL13:OUT.26.TMINBITSLICE10.RX_CNTVALUEOUT3
TCELL13:OUT.27.TMINBITSLICE10.RX_CNTVALUEOUT4
TCELL13:OUT.28.TMINBITSLICE10.RX_CNTVALUEOUT5
TCELL13:OUT.29.TMINBITSLICE10.RX_CNTVALUEOUT6
TCELL13:OUT.30.TMINBITSLICE10.RX_CNTVALUEOUT7
TCELL13:OUT.31.TMINBITSLICE10.RX_CNTVALUEOUT8
TCELL13:IMUX.CTRL.0PLL0.SCANCLK_B
TCELL13:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK9
TCELL13:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.TXBIT_RST_B10
TCELL13:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.RXBIT_RST_B10
TCELL13:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.ODELAY_RST_B10
TCELL13:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.IDELAY_RST_B10
TCELL13:IMUX.BYP.0PLL0.DI0
TCELL13:IMUX.BYP.1PLL0.DI1
TCELL13:IMUX.BYP.2PLL0.DI2
TCELL13:IMUX.BYP.3PLL0.DI3
TCELL13:IMUX.BYP.6BITSLICE9.RX_CE_IDELAY
TCELL13:IMUX.BYP.7BITSLICE9.DYN_DCI_OUT_INT
TCELL13:IMUX.BYP.8BITSLICE10.TX_LD
TCELL13:IMUX.BYP.9BITSLICE10.TX_INC
TCELL13:IMUX.BYP.10BITSLICE10.TX_EN_VTC
TCELL13:IMUX.BYP.11BITSLICE10.TX_CE_ODELAY
TCELL13:IMUX.BYP.12BITSLICE10.RX_LD
TCELL13:IMUX.BYP.13BITSLICE10.RX_INC
TCELL13:IMUX.BYP.14BITSLICE10.RX_EN_VTC
TCELL13:IMUX.BYP.15BITSLICE10.RX_CE_IDELAY
TCELL13:IMUX.IMUX.0.DELAYPLL0.RST
TCELL13:IMUX.IMUX.6.DELAYBITSLICE11.TX_D5
TCELL13:IMUX.IMUX.7.DELAYBITSLICE11.TX_D6
TCELL13:IMUX.IMUX.8.DELAYBITSLICE11.TX_D7
TCELL13:IMUX.IMUX.9.DELAYBITSLICE11.TX_CNTVALUEIN0
TCELL13:IMUX.IMUX.10.DELAYBITSLICE11.TX_CNTVALUEIN1
TCELL13:IMUX.IMUX.11.DELAYBITSLICE11.TX_CNTVALUEIN2
TCELL13:IMUX.IMUX.12.DELAYBITSLICE11.TX_CNTVALUEIN3
TCELL13:IMUX.IMUX.13.DELAYBITSLICE11.TX_CNTVALUEIN4
TCELL13:IMUX.IMUX.14.DELAYBITSLICE11.TX_CNTVALUEIN5
TCELL13:IMUX.IMUX.15.DELAYBITSLICE11.TX_CNTVALUEIN6
TCELL13:IMUX.IMUX.16.DELAYBITSLICE11.TX_D4
TCELL14:OUT.0.TMINPLL1.TESTOUT32
TCELL14:OUT.1.TMINPLL1.TESTOUT33
TCELL14:OUT.2.TMINPLL1.TESTOUT34
TCELL14:OUT.3.TMINPLL1.TESTOUT35
TCELL14:OUT.4.TMINBITSLICE11.PHY2CLB_FIFO_EMPTY
TCELL14:OUT.5.TMINBITSLICE11.RX_Q0
TCELL14:OUT.6.TMINBITSLICE11.RX_Q1
TCELL14:OUT.7.TMINBITSLICE11.RX_Q2
TCELL14:OUT.8.TMINBITSLICE11.RX_Q3
TCELL14:OUT.9.TMINBITSLICE11.RX_Q4
TCELL14:OUT.10.TMINBITSLICE11.RX_Q5
TCELL14:OUT.11.TMINBITSLICE11.RX_Q6
TCELL14:OUT.12.TMINBITSLICE11.RX_Q7
TCELL14:OUT.13.TMINBITSLICE11.TX_CNTVALUEOUT0
TCELL14:OUT.14.TMINBITSLICE11.TX_CNTVALUEOUT1
TCELL14:OUT.15.TMINBITSLICE11.TX_CNTVALUEOUT2
TCELL14:OUT.16.TMINBITSLICE11.TX_CNTVALUEOUT3
TCELL14:OUT.17.TMINBITSLICE11.TX_CNTVALUEOUT4
TCELL14:OUT.18.TMINBITSLICE11.TX_CNTVALUEOUT5
TCELL14:OUT.19.TMINBITSLICE11.TX_CNTVALUEOUT6
TCELL14:OUT.20.TMINBITSLICE11.TX_CNTVALUEOUT7
TCELL14:OUT.21.TMINBITSLICE11.TX_CNTVALUEOUT8
TCELL14:OUT.23.TMINBITSLICE11.RX_CNTVALUEOUT0
TCELL14:OUT.24.TMINBITSLICE11.RX_CNTVALUEOUT1
TCELL14:OUT.25.TMINBITSLICE11.RX_CNTVALUEOUT2
TCELL14:OUT.26.TMINBITSLICE11.RX_CNTVALUEOUT3
TCELL14:OUT.27.TMINBITSLICE11.RX_CNTVALUEOUT4
TCELL14:OUT.28.TMINBITSLICE11.RX_CNTVALUEOUT5
TCELL14:OUT.29.TMINBITSLICE11.RX_CNTVALUEOUT6
TCELL14:OUT.30.TMINBITSLICE11.RX_CNTVALUEOUT7
TCELL14:OUT.31.TMINBITSLICE11.RX_CNTVALUEOUT8
TCELL14:IMUX.CTRL.2XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK10
TCELL14:IMUX.CTRL.3XIPHY_FEEDTHROUGH0.TXBIT_RST_B11
TCELL14:IMUX.CTRL.4XIPHY_FEEDTHROUGH0.RXBIT_RST_B11
TCELL14:IMUX.CTRL.5XIPHY_FEEDTHROUGH0.ODELAY_RST_B11
TCELL14:IMUX.CTRL.6XIPHY_FEEDTHROUGH0.IDELAY_RST_B11
TCELL14:IMUX.CTRL.7XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK11
TCELL14:IMUX.BYP.0PLL1.TESTIN28
TCELL14:IMUX.BYP.1PLL1.TESTIN29
TCELL14:IMUX.BYP.2PLL1.TESTIN30
TCELL14:IMUX.BYP.3PLL1.TESTIN31
TCELL14:IMUX.BYP.6BITSLICE10.DYN_DCI_OUT_INT
TCELL14:IMUX.BYP.7BITSLICE11.TX_LD
TCELL14:IMUX.BYP.8BITSLICE11.TX_INC
TCELL14:IMUX.BYP.9BITSLICE11.TX_EN_VTC
TCELL14:IMUX.BYP.10BITSLICE11.TX_CE_ODELAY
TCELL14:IMUX.BYP.11BITSLICE11.RX_LD
TCELL14:IMUX.BYP.12BITSLICE11.RX_INC
TCELL14:IMUX.BYP.13BITSLICE11.RX_EN_VTC
TCELL14:IMUX.BYP.14BITSLICE11.RX_CE_IDELAY
TCELL14:IMUX.BYP.15BITSLICE11.DYN_DCI_OUT_INT
TCELL14:IMUX.IMUX.6.DELAYBITSLICE11.TX_CNTVALUEIN8
TCELL14:IMUX.IMUX.7.DELAYBITSLICE11.RX_CNTVALUEIN0
TCELL14:IMUX.IMUX.8.DELAYBITSLICE11.RX_CNTVALUEIN1
TCELL14:IMUX.IMUX.9.DELAYBITSLICE11.RX_CNTVALUEIN2
TCELL14:IMUX.IMUX.10.DELAYBITSLICE11.RX_CNTVALUEIN3
TCELL14:IMUX.IMUX.11.DELAYBITSLICE11.RX_CNTVALUEIN4
TCELL14:IMUX.IMUX.12.DELAYBITSLICE11.RX_CNTVALUEIN5
TCELL14:IMUX.IMUX.13.DELAYBITSLICE11.RX_CNTVALUEIN6
TCELL14:IMUX.IMUX.14.DELAYBITSLICE11.RX_CNTVALUEIN7
TCELL14:IMUX.IMUX.15.DELAYBITSLICE11.RX_CNTVALUEIN8
TCELL14:IMUX.IMUX.16.DELAYBITSLICE11.TX_CNTVALUEIN7
TCELL15:OUT.0.TMINPLL1.TESTOUT28
TCELL15:OUT.1.TMINPLL1.TESTOUT29
TCELL15:OUT.2.TMINPLL1.TESTOUT30
TCELL15:OUT.3.TMINPLL1.TESTOUT31
TCELL15:OUT.4.TMINBITSLICE13.PHY2CLB_FIFO_EMPTY
TCELL15:OUT.5.TMINBITSLICE13.RX_Q0
TCELL15:OUT.6.TMINBITSLICE13.RX_Q1
TCELL15:OUT.7.TMINBITSLICE13.RX_Q2
TCELL15:OUT.8.TMINBITSLICE13.RX_Q3
TCELL15:OUT.9.TMINBITSLICE13.RX_Q4
TCELL15:OUT.10.TMINBITSLICE13.RX_Q5
TCELL15:OUT.11.TMINBITSLICE13.RX_Q6
TCELL15:OUT.12.TMINBITSLICE13.RX_Q7
TCELL15:OUT.13.TMINBITSLICE13.TX_CNTVALUEOUT0
TCELL15:OUT.14.TMINBITSLICE13.TX_CNTVALUEOUT1
TCELL15:OUT.15.TMINBITSLICE13.TX_CNTVALUEOUT2
TCELL15:OUT.16.TMINBITSLICE13.TX_CNTVALUEOUT3
TCELL15:OUT.17.TMINBITSLICE13.TX_CNTVALUEOUT4
TCELL15:OUT.18.TMINBITSLICE13.TX_CNTVALUEOUT5
TCELL15:OUT.19.TMINBITSLICE13.TX_CNTVALUEOUT6
TCELL15:OUT.20.TMINBITSLICE13.TX_CNTVALUEOUT7
TCELL15:OUT.21.TMINBITSLICE13.TX_CNTVALUEOUT8
TCELL15:OUT.22.TMINBITSLICE13.TX_T_OUT
TCELL15:OUT.23.TMINBITSLICE13.RX_CNTVALUEOUT0
TCELL15:OUT.24.TMINBITSLICE13.RX_CNTVALUEOUT1
TCELL15:OUT.25.TMINBITSLICE13.RX_CNTVALUEOUT2
TCELL15:OUT.26.TMINBITSLICE13.RX_CNTVALUEOUT3
TCELL15:OUT.27.TMINBITSLICE13.RX_CNTVALUEOUT4
TCELL15:OUT.28.TMINBITSLICE13.RX_CNTVALUEOUT5
TCELL15:OUT.29.TMINBITSLICE13.RX_CNTVALUEOUT6
TCELL15:OUT.30.TMINBITSLICE13.RX_CNTVALUEOUT7
TCELL15:OUT.31.TMINBITSLICE13.RX_CNTVALUEOUT8
TCELL15:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.TXBIT_TRI_RST_B0
TCELL15:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.TXBIT_RST_B0
TCELL15:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.RXBIT_RST_B0
TCELL15:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.ODELAY_RST_B0
TCELL15:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.IDELAY_RST_B0
TCELL15:IMUX.BYP.0PLL1.TESTIN24
TCELL15:IMUX.BYP.1PLL1.TESTIN25
TCELL15:IMUX.BYP.2PLL1.TESTIN26
TCELL15:IMUX.BYP.3PLL1.TESTIN27
TCELL15:IMUX.BYP.6BITSLICE_T2.EN_VTC
TCELL15:IMUX.BYP.7BITSLICE13.TX_LD
TCELL15:IMUX.BYP.8BITSLICE13.TX_INC
TCELL15:IMUX.BYP.9BITSLICE13.TX_EN_VTC
TCELL15:IMUX.BYP.10BITSLICE13.TX_CE_ODELAY
TCELL15:IMUX.BYP.11BITSLICE13.RX_LD
TCELL15:IMUX.BYP.12BITSLICE13.RX_INC
TCELL15:IMUX.BYP.13BITSLICE13.RX_EN_VTC
TCELL15:IMUX.BYP.14BITSLICE13.RX_CE_IDELAY
TCELL15:IMUX.BYP.15BITSLICE13.DYN_DCI_OUT_INT
TCELL15:IMUX.IMUX.0.DELAYPLL1.CLKOUTPHY_EN
TCELL15:IMUX.IMUX.6.DELAYBITSLICE13.TX_CE_OFD
TCELL15:IMUX.IMUX.7.DELAYBITSLICE13.RX_CE_IFD
TCELL15:IMUX.IMUX.8.DELAYBITSLICE13.RX_DATAIN1
TCELL15:IMUX.IMUX.9.DELAYBITSLICE13.CLB2PHY_FIFO_RDEN
TCELL15:IMUX.IMUX.10.DELAYBITSLICE13.TX_D7
TCELL15:IMUX.IMUX.11.DELAYBITSLICE13.TX_D6
TCELL15:IMUX.IMUX.12.DELAYBITSLICE13.TX_D5
TCELL15:IMUX.IMUX.13.DELAYBITSLICE13.TX_D4
TCELL15:IMUX.IMUX.14.DELAYBITSLICE13.TX_D3
TCELL15:IMUX.IMUX.15.DELAYBITSLICE13.TX_D2
TCELL15:IMUX.IMUX.16.DELAYBITSLICE13.TX_T
TCELL16:OUT.0.TMINPLL1.TESTOUT24
TCELL16:OUT.1.TMINPLL1.TESTOUT25
TCELL16:OUT.2.TMINPLL1.TESTOUT26
TCELL16:OUT.3.TMINPLL1.TESTOUT27
TCELL16:OUT.4.TMINBITSLICE14.PHY2CLB_FIFO_EMPTY
TCELL16:OUT.5.TMINBITSLICE14.RX_Q0
TCELL16:OUT.6.TMINBITSLICE14.RX_Q1
TCELL16:OUT.7.TMINBITSLICE14.RX_Q2
TCELL16:OUT.8.TMINBITSLICE14.RX_Q3
TCELL16:OUT.9.TMINBITSLICE14.RX_Q4
TCELL16:OUT.10.TMINBITSLICE14.RX_Q5
TCELL16:OUT.11.TMINBITSLICE14.RX_Q6
TCELL16:OUT.12.TMINBITSLICE14.RX_Q7
TCELL16:OUT.13.TMINBITSLICE14.TX_CNTVALUEOUT0
TCELL16:OUT.14.TMINBITSLICE14.TX_CNTVALUEOUT1
TCELL16:OUT.15.TMINBITSLICE14.TX_CNTVALUEOUT2
TCELL16:OUT.16.TMINBITSLICE14.TX_CNTVALUEOUT3
TCELL16:OUT.17.TMINBITSLICE14.TX_CNTVALUEOUT4
TCELL16:OUT.18.TMINBITSLICE14.TX_CNTVALUEOUT5
TCELL16:OUT.19.TMINBITSLICE14.TX_CNTVALUEOUT6
TCELL16:OUT.20.TMINBITSLICE14.TX_CNTVALUEOUT7
TCELL16:OUT.21.TMINBITSLICE14.TX_CNTVALUEOUT8
TCELL16:OUT.22.TMINBITSLICE14.TX_T_OUT
TCELL16:OUT.23.TMINBITSLICE14.RX_CNTVALUEOUT0
TCELL16:OUT.24.TMINBITSLICE14.RX_CNTVALUEOUT1
TCELL16:OUT.25.TMINBITSLICE14.RX_CNTVALUEOUT2
TCELL16:OUT.26.TMINBITSLICE14.RX_CNTVALUEOUT3
TCELL16:OUT.27.TMINBITSLICE14.RX_CNTVALUEOUT4
TCELL16:OUT.28.TMINBITSLICE14.RX_CNTVALUEOUT5
TCELL16:OUT.29.TMINBITSLICE14.RX_CNTVALUEOUT6
TCELL16:OUT.30.TMINBITSLICE14.RX_CNTVALUEOUT7
TCELL16:OUT.31.TMINBITSLICE14.RX_CNTVALUEOUT8
TCELL16:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK0
TCELL16:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.TXBIT_TRI_RST_B1
TCELL16:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.TXBIT_RST_B1
TCELL16:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.RXBIT_RST_B1
TCELL16:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.ODELAY_RST_B1
TCELL16:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.IDELAY_RST_B1
TCELL16:IMUX.BYP.0PLL1.TESTIN20
TCELL16:IMUX.BYP.1PLL1.TESTIN21
TCELL16:IMUX.BYP.2PLL1.TESTIN22
TCELL16:IMUX.BYP.3PLL1.TESTIN23
TCELL16:IMUX.BYP.6BITSLICE_T3.EN_VTC
TCELL16:IMUX.BYP.7BITSLICE14.TX_LD
TCELL16:IMUX.BYP.8BITSLICE14.TX_INC
TCELL16:IMUX.BYP.9BITSLICE14.TX_EN_VTC
TCELL16:IMUX.BYP.10BITSLICE14.TX_CE_ODELAY
TCELL16:IMUX.BYP.11BITSLICE14.RX_LD
TCELL16:IMUX.BYP.12BITSLICE14.RX_INC
TCELL16:IMUX.BYP.13BITSLICE14.RX_EN_VTC
TCELL16:IMUX.BYP.14BITSLICE14.RX_CE_IDELAY
TCELL16:IMUX.BYP.15BITSLICE14.DYN_DCI_OUT_INT
TCELL16:IMUX.IMUX.6.DELAYBITSLICE13.TX_D1
TCELL16:IMUX.IMUX.7.DELAYBITSLICE13.TX_CNTVALUEIN0
TCELL16:IMUX.IMUX.8.DELAYBITSLICE13.TX_CNTVALUEIN1
TCELL16:IMUX.IMUX.9.DELAYBITSLICE13.TX_CNTVALUEIN2
TCELL16:IMUX.IMUX.10.DELAYBITSLICE13.TX_CNTVALUEIN3
TCELL16:IMUX.IMUX.11.DELAYBITSLICE13.TX_CNTVALUEIN4
TCELL16:IMUX.IMUX.12.DELAYBITSLICE13.TX_CNTVALUEIN5
TCELL16:IMUX.IMUX.13.DELAYBITSLICE13.TX_CNTVALUEIN6
TCELL16:IMUX.IMUX.14.DELAYBITSLICE13.TX_CNTVALUEIN7
TCELL16:IMUX.IMUX.15.DELAYBITSLICE13.TX_CNTVALUEIN8
TCELL16:IMUX.IMUX.16.DELAYBITSLICE13.TX_D0
TCELL17:OUT.0.TMINPLL1.TESTOUT20
TCELL17:OUT.1.TMINPLL1.TESTOUT21
TCELL17:OUT.2.TMINPLL1.TESTOUT22
TCELL17:OUT.3.TMINPLL1.TESTOUT23
TCELL17:OUT.4.TMINBITSLICE15.PHY2CLB_FIFO_EMPTY
TCELL17:OUT.5.TMINBITSLICE15.RX_Q0
TCELL17:OUT.6.TMINBITSLICE15.RX_Q1
TCELL17:OUT.7.TMINBITSLICE15.RX_Q2
TCELL17:OUT.8.TMINBITSLICE15.RX_Q3
TCELL17:OUT.9.TMINBITSLICE15.RX_Q4
TCELL17:OUT.10.TMINBITSLICE15.RX_Q5
TCELL17:OUT.11.TMINBITSLICE15.RX_Q6
TCELL17:OUT.12.TMINBITSLICE15.RX_Q7
TCELL17:OUT.13.TMINBITSLICE15.TX_CNTVALUEOUT0
TCELL17:OUT.14.TMINBITSLICE15.TX_CNTVALUEOUT1
TCELL17:OUT.15.TMINBITSLICE15.TX_CNTVALUEOUT2
TCELL17:OUT.16.TMINBITSLICE15.TX_CNTVALUEOUT3
TCELL17:OUT.17.TMINBITSLICE15.TX_CNTVALUEOUT4
TCELL17:OUT.18.TMINBITSLICE15.TX_CNTVALUEOUT5
TCELL17:OUT.19.TMINBITSLICE15.TX_CNTVALUEOUT6
TCELL17:OUT.20.TMINBITSLICE15.TX_CNTVALUEOUT7
TCELL17:OUT.21.TMINBITSLICE15.TX_CNTVALUEOUT8
TCELL17:OUT.22.TMINBITSLICE15.TX_T_OUT
TCELL17:OUT.23.TMINBITSLICE15.RX_CNTVALUEOUT0
TCELL17:OUT.24.TMINBITSLICE15.RX_CNTVALUEOUT1
TCELL17:OUT.25.TMINBITSLICE15.RX_CNTVALUEOUT2
TCELL17:OUT.26.TMINBITSLICE15.RX_CNTVALUEOUT3
TCELL17:OUT.27.TMINBITSLICE15.RX_CNTVALUEOUT4
TCELL17:OUT.28.TMINBITSLICE15.RX_CNTVALUEOUT5
TCELL17:OUT.29.TMINBITSLICE15.RX_CNTVALUEOUT6
TCELL17:OUT.30.TMINBITSLICE15.RX_CNTVALUEOUT7
TCELL17:OUT.31.TMINBITSLICE15.RX_CNTVALUEOUT8
TCELL17:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK1
TCELL17:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.TXBIT_RST_B2
TCELL17:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.RXBIT_RST_B2
TCELL17:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.ODELAY_RST_B2
TCELL17:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.IDELAY_RST_B2
TCELL17:IMUX.BYP.0PLL1.TESTIN16
TCELL17:IMUX.BYP.1PLL1.TESTIN17
TCELL17:IMUX.BYP.2PLL1.TESTIN18
TCELL17:IMUX.BYP.3PLL1.TESTIN19
TCELL17:IMUX.BYP.6BITSLICE15.TX_LD
TCELL17:IMUX.BYP.7BITSLICE15.TX_INC
TCELL17:IMUX.BYP.8BITSLICE15.TX_EN_VTC
TCELL17:IMUX.BYP.9BITSLICE15.TX_CE_ODELAY
TCELL17:IMUX.BYP.10BITSLICE15.RX_LD
TCELL17:IMUX.BYP.11BITSLICE15.RX_INC
TCELL17:IMUX.BYP.12BITSLICE15.RX_EN_VTC
TCELL17:IMUX.BYP.13BITSLICE15.RX_CE_IDELAY
TCELL17:IMUX.BYP.14BITSLICE15.DYN_DCI_OUT_INT
TCELL17:IMUX.BYP.15BITSLICE_T2.CE_OFD
TCELL17:IMUX.IMUX.6.DELAYBITSLICE14.TX_D1
TCELL17:IMUX.IMUX.7.DELAYBITSLICE14.TX_D3
TCELL17:IMUX.IMUX.8.DELAYBITSLICE14.TX_D7
TCELL17:IMUX.IMUX.9.DELAYBITSLICE14.TX_CNTVALUEIN1
TCELL17:IMUX.IMUX.10.DELAYBITSLICE14.TX_CNTVALUEIN5
TCELL17:IMUX.IMUX.11.DELAYBITSLICE14.TX_CNTVALUEIN7
TCELL17:IMUX.IMUX.12.DELAYBITSLICE14.RX_CNTVALUEIN2
TCELL17:IMUX.IMUX.13.DELAYBITSLICE14.RX_CNTVALUEIN4
TCELL17:IMUX.IMUX.14.DELAYBITSLICE14.RX_CNTVALUEIN8
TCELL17:IMUX.IMUX.15.DELAYBITSLICE15.TX_CE_OFD
TCELL17:IMUX.IMUX.16.DELAYBITSLICE13.RX_CNTVALUEIN0
TCELL17:IMUX.IMUX.17.DELAYBITSLICE13.RX_CNTVALUEIN1
TCELL17:IMUX.IMUX.18.DELAYBITSLICE13.RX_CNTVALUEIN2
TCELL17:IMUX.IMUX.19.DELAYBITSLICE13.RX_CNTVALUEIN3
TCELL17:IMUX.IMUX.20.DELAYBITSLICE13.RX_CNTVALUEIN4
TCELL17:IMUX.IMUX.21.DELAYBITSLICE13.RX_CNTVALUEIN5
TCELL17:IMUX.IMUX.22.DELAYBITSLICE13.RX_CNTVALUEIN6
TCELL17:IMUX.IMUX.23.DELAYBITSLICE13.RX_CNTVALUEIN7
TCELL17:IMUX.IMUX.24.DELAYBITSLICE13.RX_CNTVALUEIN8
TCELL17:IMUX.IMUX.25.DELAYBITSLICE14.TX_T
TCELL17:IMUX.IMUX.26.DELAYBITSLICE14.TX_CE_OFD
TCELL17:IMUX.IMUX.27.DELAYBITSLICE14.RX_CE_IFD
TCELL17:IMUX.IMUX.28.DELAYBITSLICE14.RX_DATAIN1
TCELL17:IMUX.IMUX.29.DELAYBITSLICE14.CLB2PHY_FIFO_RDEN
TCELL17:IMUX.IMUX.30.DELAYBITSLICE14.TX_D0
TCELL17:IMUX.IMUX.31.DELAYBITSLICE14.TX_D2
TCELL17:IMUX.IMUX.32.DELAYBITSLICE14.TX_D4
TCELL17:IMUX.IMUX.33.DELAYBITSLICE14.TX_D5
TCELL17:IMUX.IMUX.34.DELAYBITSLICE14.TX_D6
TCELL17:IMUX.IMUX.35.DELAYBITSLICE14.TX_CNTVALUEIN0
TCELL17:IMUX.IMUX.36.DELAYBITSLICE14.TX_CNTVALUEIN2
TCELL17:IMUX.IMUX.37.DELAYBITSLICE14.TX_CNTVALUEIN3
TCELL17:IMUX.IMUX.38.DELAYBITSLICE14.TX_CNTVALUEIN4
TCELL17:IMUX.IMUX.39.DELAYBITSLICE14.TX_CNTVALUEIN6
TCELL17:IMUX.IMUX.40.DELAYBITSLICE14.TX_CNTVALUEIN8
TCELL17:IMUX.IMUX.41.DELAYBITSLICE14.RX_CNTVALUEIN0
TCELL17:IMUX.IMUX.42.DELAYBITSLICE14.RX_CNTVALUEIN1
TCELL17:IMUX.IMUX.43.DELAYBITSLICE14.RX_CNTVALUEIN3
TCELL17:IMUX.IMUX.44.DELAYBITSLICE14.RX_CNTVALUEIN5
TCELL17:IMUX.IMUX.45.DELAYBITSLICE14.RX_CNTVALUEIN6
TCELL17:IMUX.IMUX.46.DELAYBITSLICE14.RX_CNTVALUEIN7
TCELL17:IMUX.IMUX.47.DELAYBITSLICE15.TX_T
TCELL18:OUT.0.TMINPLL1.TESTOUT16
TCELL18:OUT.1.TMINPLL1.TESTOUT17
TCELL18:OUT.2.TMINPLL1.TESTOUT18
TCELL18:OUT.3.TMINPLL1.TESTOUT19
TCELL18:OUT.4.TMINBITSLICE_T2.CNTVALUEOUT0
TCELL18:OUT.5.TMINBITSLICE_T2.CNTVALUEOUT1
TCELL18:OUT.6.TMINBITSLICE_T2.CNTVALUEOUT2
TCELL18:OUT.7.TMINBITSLICE_T2.CNTVALUEOUT3
TCELL18:OUT.8.TMINBITSLICE_T2.CNTVALUEOUT4
TCELL18:OUT.9.TMINBITSLICE_T2.CNTVALUEOUT5
TCELL18:OUT.10.TMINBITSLICE_T2.CNTVALUEOUT6
TCELL18:OUT.11.TMINBITSLICE_T2.CNTVALUEOUT7
TCELL18:OUT.12.TMINBITSLICE_T2.CNTVALUEOUT8
TCELL18:OUT.13.TMINBITSLICE16.TX_T_OUT
TCELL18:OUT.14.TMINBITSLICE_CONTROL2.PHY2CLB_PHY_RDY
TCELL18:OUT.15.TMINBITSLICE_CONTROL2.MASTER_PD_OUT
TCELL18:OUT.16.TMINBITSLICE_CONTROL2.PHY2CLB_FIXDLY_RDY
TCELL18:OUT.17.TMINBITSLICE_CONTROL2.CTRL_DLY_TEST_OUT
TCELL18:OUT.18.TMINBITSLICE16.PHY2CLB_FIFO_EMPTY
TCELL18:OUT.19.TMINBITSLICE16.RX_Q0
TCELL18:OUT.20.TMINBITSLICE16.RX_Q1
TCELL18:OUT.21.TMINBITSLICE16.RX_Q2
TCELL18:OUT.22.TMINBITSLICE16.RX_Q3
TCELL18:OUT.23.TMINBITSLICE16.RX_Q4
TCELL18:OUT.24.TMINBITSLICE16.RX_Q5
TCELL18:OUT.25.TMINBITSLICE16.RX_Q6
TCELL18:OUT.26.TMINBITSLICE16.RX_Q7
TCELL18:OUT.27.TMINBITSLICE16.TX_CNTVALUEOUT0
TCELL18:OUT.28.TMINBITSLICE16.TX_CNTVALUEOUT1
TCELL18:OUT.29.TMINBITSLICE16.TX_CNTVALUEOUT2
TCELL18:OUT.30.TMINBITSLICE16.TX_CNTVALUEOUT3
TCELL18:OUT.31.TMINBITSLICE16.TX_CNTVALUEOUT4
TCELL18:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK2
TCELL18:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.TRISTATE_ODELAY_RST_B0
TCELL18:IMUX.CTRL.5BITSLICE_CONTROL2.REFCLK
TCELL18:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.CTRL_RST_B_LOW
TCELL18:IMUX.CTRL.7BITSLICE_CONTROL2.RIU_CLK, XIPHY_FEEDTHROUGH1.CLB2PHY_CTRL_CLK_LOW
TCELL18:IMUX.BYP.0PLL1.TESTIN12
TCELL18:IMUX.BYP.1PLL1.TESTIN13
TCELL18:IMUX.BYP.2PLL1.TESTIN14
TCELL18:IMUX.BYP.3PLL1.TESTIN15
TCELL18:IMUX.BYP.6BITSLICE_T2.LD
TCELL18:IMUX.BYP.7BITSLICE_T2.INC
TCELL18:IMUX.BYP.8BITSLICE_T2.CE_ODELAY
TCELL18:IMUX.BYP.9BITSLICE_CONTROL2.EN_VTC
TCELL18:IMUX.BYP.10BITSLICE_CONTROL2.CTRL_DLY_TEST_IN
TCELL18:IMUX.BYP.12BITSLICE16.TX_LD
TCELL18:IMUX.BYP.13BITSLICE16.TX_INC
TCELL18:IMUX.BYP.14BITSLICE16.TX_EN_VTC
TCELL18:IMUX.BYP.15BITSLICE16.TX_CE_ODELAY
TCELL18:IMUX.IMUX.6.DELAYBITSLICE15.TX_CNTVALUEIN3
TCELL18:IMUX.IMUX.7.DELAYBITSLICE15.TX_CNTVALUEIN5
TCELL18:IMUX.IMUX.8.DELAYBITSLICE15.RX_CNTVALUEIN0
TCELL18:IMUX.IMUX.9.DELAYBITSLICE15.RX_CNTVALUEIN2
TCELL18:IMUX.IMUX.10.DELAYBITSLICE15.RX_CNTVALUEIN6
TCELL18:IMUX.IMUX.11.DELAYBITSLICE15.RX_CNTVALUEIN8
TCELL18:IMUX.IMUX.12.DELAYBITSLICE_T2.CNTVALUEIN3
TCELL18:IMUX.IMUX.13.DELAYBITSLICE_T2.CNTVALUEIN5
TCELL18:IMUX.IMUX.14.DELAYBITSLICE_CONTROL2.CLB2RIU_NIBBLE_SEL
TCELL18:IMUX.IMUX.15.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS1_1
TCELL18:IMUX.IMUX.16.DELAYBITSLICE15.RX_CE_IFD
TCELL18:IMUX.IMUX.17.DELAYBITSLICE15.RX_DATAIN1
TCELL18:IMUX.IMUX.18.DELAYBITSLICE15.CLB2PHY_FIFO_RDEN
TCELL18:IMUX.IMUX.20.DELAYBITSLICE15.TX_D0
TCELL18:IMUX.IMUX.21.DELAYBITSLICE15.TX_D1
TCELL18:IMUX.IMUX.22.DELAYBITSLICE15.TX_D2
TCELL18:IMUX.IMUX.23.DELAYBITSLICE15.TX_D3
TCELL18:IMUX.IMUX.24.DELAYBITSLICE15.TX_D4
TCELL18:IMUX.IMUX.25.DELAYBITSLICE15.TX_D5
TCELL18:IMUX.IMUX.26.DELAYBITSLICE15.TX_D6
TCELL18:IMUX.IMUX.27.DELAYBITSLICE15.TX_D7
TCELL18:IMUX.IMUX.28.DELAYBITSLICE15.TX_CNTVALUEIN0
TCELL18:IMUX.IMUX.29.DELAYBITSLICE15.TX_CNTVALUEIN1
TCELL18:IMUX.IMUX.30.DELAYBITSLICE15.TX_CNTVALUEIN2
TCELL18:IMUX.IMUX.31.DELAYBITSLICE15.TX_CNTVALUEIN4
TCELL18:IMUX.IMUX.32.DELAYBITSLICE15.TX_CNTVALUEIN6
TCELL18:IMUX.IMUX.33.DELAYBITSLICE15.TX_CNTVALUEIN7
TCELL18:IMUX.IMUX.34.DELAYBITSLICE15.TX_CNTVALUEIN8
TCELL18:IMUX.IMUX.35.DELAYBITSLICE15.RX_CNTVALUEIN1
TCELL18:IMUX.IMUX.36.DELAYBITSLICE15.RX_CNTVALUEIN3
TCELL18:IMUX.IMUX.37.DELAYBITSLICE15.RX_CNTVALUEIN4
TCELL18:IMUX.IMUX.38.DELAYBITSLICE15.RX_CNTVALUEIN5
TCELL18:IMUX.IMUX.39.DELAYBITSLICE15.RX_CNTVALUEIN7
TCELL18:IMUX.IMUX.40.DELAYBITSLICE_T2.CNTVALUEIN0
TCELL18:IMUX.IMUX.41.DELAYBITSLICE_T2.CNTVALUEIN1
TCELL18:IMUX.IMUX.42.DELAYBITSLICE_T2.CNTVALUEIN2
TCELL18:IMUX.IMUX.43.DELAYBITSLICE_T2.CNTVALUEIN4
TCELL18:IMUX.IMUX.44.DELAYBITSLICE_T2.CNTVALUEIN6
TCELL18:IMUX.IMUX.45.DELAYBITSLICE_T2.CNTVALUEIN7
TCELL18:IMUX.IMUX.46.DELAYBITSLICE_T2.CNTVALUEIN8
TCELL18:IMUX.IMUX.47.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS1_0
TCELL19:OUT.0.TMINPLL1.TESTOUT12
TCELL19:OUT.1.TMINPLL1.TESTOUT13
TCELL19:OUT.2.TMINPLL1.TESTOUT14
TCELL19:OUT.3.TMINPLL1.TESTOUT15
TCELL19:OUT.4.TMINBITSLICE16.TX_CNTVALUEOUT5
TCELL19:OUT.5.TMINBITSLICE16.TX_CNTVALUEOUT6
TCELL19:OUT.6.TMINBITSLICE16.TX_CNTVALUEOUT7
TCELL19:OUT.7.TMINBITSLICE16.TX_CNTVALUEOUT8
TCELL19:OUT.8.TMINBITSLICE17.TX_T_OUT
TCELL19:OUT.9.TMINBITSLICE16.RX_CNTVALUEOUT0
TCELL19:OUT.10.TMINBITSLICE16.RX_CNTVALUEOUT1
TCELL19:OUT.11.TMINBITSLICE16.RX_CNTVALUEOUT2
TCELL19:OUT.12.TMINBITSLICE16.RX_CNTVALUEOUT3
TCELL19:OUT.13.TMINBITSLICE16.RX_CNTVALUEOUT4
TCELL19:OUT.14.TMINBITSLICE16.RX_CNTVALUEOUT5
TCELL19:OUT.15.TMINBITSLICE16.RX_CNTVALUEOUT6
TCELL19:OUT.16.TMINBITSLICE16.RX_CNTVALUEOUT7
TCELL19:OUT.17.TMINBITSLICE16.RX_CNTVALUEOUT8
TCELL19:OUT.18.TMINBITSLICE17.PHY2CLB_FIFO_EMPTY
TCELL19:OUT.19.TMINBITSLICE17.RX_Q0
TCELL19:OUT.20.TMINBITSLICE17.RX_Q1
TCELL19:OUT.21.TMINBITSLICE17.RX_Q2
TCELL19:OUT.22.TMINBITSLICE17.RX_Q3
TCELL19:OUT.23.TMINBITSLICE17.RX_Q4
TCELL19:OUT.24.TMINBITSLICE17.RX_Q5
TCELL19:OUT.25.TMINBITSLICE17.RX_Q6
TCELL19:OUT.26.TMINBITSLICE17.RX_Q7
TCELL19:OUT.27.TMINBITSLICE17.TX_CNTVALUEOUT0
TCELL19:OUT.28.TMINBITSLICE17.TX_CNTVALUEOUT1
TCELL19:OUT.29.TMINBITSLICE17.TX_CNTVALUEOUT2
TCELL19:OUT.30.TMINBITSLICE17.TX_CNTVALUEOUT3
TCELL19:OUT.31.TMINBITSLICE17.TX_CNTVALUEOUT4
TCELL19:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.TXBIT_RST_B3
TCELL19:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.RXBIT_RST_B3
TCELL19:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.ODELAY_RST_B3
TCELL19:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.IDELAY_RST_B3
TCELL19:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK3
TCELL19:IMUX.BYP.0PLL1.TESTIN8
TCELL19:IMUX.BYP.1PLL1.TESTIN9
TCELL19:IMUX.BYP.2PLL1.TESTIN10
TCELL19:IMUX.BYP.3PLL1.TESTIN11
TCELL19:IMUX.BYP.6BITSLICE16.RX_LD
TCELL19:IMUX.BYP.7BITSLICE16.RX_INC
TCELL19:IMUX.BYP.8BITSLICE16.RX_EN_VTC
TCELL19:IMUX.BYP.9BITSLICE16.RX_CE_IDELAY
TCELL19:IMUX.BYP.10BITSLICE16.DYN_DCI_OUT_INT
TCELL19:IMUX.BYP.11BITSLICE17.TX_LD
TCELL19:IMUX.BYP.12BITSLICE17.TX_INC
TCELL19:IMUX.BYP.13BITSLICE17.TX_EN_VTC
TCELL19:IMUX.BYP.14BITSLICE17.TX_CE_ODELAY
TCELL19:IMUX.BYP.15BITSLICE17.RX_LD
TCELL19:IMUX.IMUX.6.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS1_1
TCELL19:IMUX.IMUX.7.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS1_3
TCELL19:IMUX.IMUX.8.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS0_3
TCELL19:IMUX.IMUX.9.DELAYBITSLICE16.TX_CE_OFD
TCELL19:IMUX.IMUX.10.DELAYBITSLICE16.TX_D0
TCELL19:IMUX.IMUX.11.DELAYBITSLICE16.TX_D2
TCELL19:IMUX.IMUX.12.DELAYBITSLICE16.TX_D6
TCELL19:IMUX.IMUX.13.DELAYBITSLICE16.TX_D7
TCELL19:IMUX.IMUX.14.DELAYBITSLICE16.TX_CNTVALUEIN3
TCELL19:IMUX.IMUX.15.DELAYBITSLICE16.TX_CNTVALUEIN5
TCELL19:IMUX.IMUX.16.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS1_2
TCELL19:IMUX.IMUX.17.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS1_3
TCELL19:IMUX.IMUX.18.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS0_0
TCELL19:IMUX.IMUX.19.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS0_1
TCELL19:IMUX.IMUX.20.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS0_2
TCELL19:IMUX.IMUX.21.DELAYBITSLICE_CONTROL2.CLB2PHY_WRCS0_3
TCELL19:IMUX.IMUX.22.DELAYBITSLICE_CONTROL2.CLB2PHY_T_B0
TCELL19:IMUX.IMUX.23.DELAYBITSLICE_CONTROL2.CLB2PHY_T_B1
TCELL19:IMUX.IMUX.24.DELAYBITSLICE_CONTROL2.CLB2PHY_T_B2
TCELL19:IMUX.IMUX.25.DELAYBITSLICE_CONTROL2.CLB2PHY_T_B3
TCELL19:IMUX.IMUX.26.DELAYBITSLICE_CONTROL2.CLB2PHY_RDEN0
TCELL19:IMUX.IMUX.27.DELAYBITSLICE_CONTROL2.CLB2PHY_RDEN1
TCELL19:IMUX.IMUX.28.DELAYBITSLICE_CONTROL2.CLB2PHY_RDEN2
TCELL19:IMUX.IMUX.29.DELAYBITSLICE_CONTROL2.CLB2PHY_RDEN3
TCELL19:IMUX.IMUX.30.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS1_0
TCELL19:IMUX.IMUX.31.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS1_2
TCELL19:IMUX.IMUX.32.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS0_0
TCELL19:IMUX.IMUX.33.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS0_1
TCELL19:IMUX.IMUX.34.DELAYBITSLICE_CONTROL2.CLB2PHY_RDCS0_2
TCELL19:IMUX.IMUX.35.DELAYBITSLICE16.TX_T
TCELL19:IMUX.IMUX.36.DELAYBITSLICE16.RX_CE_IFD
TCELL19:IMUX.IMUX.37.DELAYBITSLICE16.RX_DATAIN1
TCELL19:IMUX.IMUX.38.DELAYBITSLICE16.CLB2PHY_FIFO_RDEN
TCELL19:IMUX.IMUX.39.DELAYBITSLICE16.TX_D1
TCELL19:IMUX.IMUX.40.DELAYBITSLICE16.TX_D3
TCELL19:IMUX.IMUX.41.DELAYBITSLICE16.TX_D4
TCELL19:IMUX.IMUX.42.DELAYBITSLICE16.TX_D5
TCELL19:IMUX.IMUX.44.DELAYBITSLICE16.TX_CNTVALUEIN0
TCELL19:IMUX.IMUX.45.DELAYBITSLICE16.TX_CNTVALUEIN1
TCELL19:IMUX.IMUX.46.DELAYBITSLICE16.TX_CNTVALUEIN2
TCELL19:IMUX.IMUX.47.DELAYBITSLICE16.TX_CNTVALUEIN4
TCELL20:OUT.0.TMINPLL1.TESTOUT8
TCELL20:OUT.1.TMINPLL1.TESTOUT9
TCELL20:OUT.2.TMINPLL1.TESTOUT10
TCELL20:OUT.3.TMINPLL1.TESTOUT11
TCELL20:OUT.4.TMINBITSLICE17.TX_CNTVALUEOUT5
TCELL20:OUT.5.TMINBITSLICE17.TX_CNTVALUEOUT6
TCELL20:OUT.6.TMINBITSLICE17.TX_CNTVALUEOUT7
TCELL20:OUT.7.TMINBITSLICE17.TX_CNTVALUEOUT8
TCELL20:OUT.8.TMINBITSLICE18.TX_T_OUT
TCELL20:OUT.9.TMINBITSLICE17.RX_CNTVALUEOUT0
TCELL20:OUT.10.TMINBITSLICE17.RX_CNTVALUEOUT1
TCELL20:OUT.11.TMINBITSLICE17.RX_CNTVALUEOUT2
TCELL20:OUT.12.TMINBITSLICE17.RX_CNTVALUEOUT3
TCELL20:OUT.13.TMINBITSLICE17.RX_CNTVALUEOUT4
TCELL20:OUT.14.TMINBITSLICE17.RX_CNTVALUEOUT5
TCELL20:OUT.15.TMINBITSLICE17.RX_CNTVALUEOUT6
TCELL20:OUT.16.TMINBITSLICE17.RX_CNTVALUEOUT7
TCELL20:OUT.17.TMINBITSLICE17.RX_CNTVALUEOUT8
TCELL20:OUT.18.TMINBITSLICE18.PHY2CLB_FIFO_EMPTY
TCELL20:OUT.19.TMINBITSLICE18.RX_Q0
TCELL20:OUT.20.TMINBITSLICE18.RX_Q1
TCELL20:OUT.21.TMINBITSLICE18.RX_Q2
TCELL20:OUT.22.TMINBITSLICE18.RX_Q3
TCELL20:OUT.23.TMINBITSLICE18.RX_Q4
TCELL20:OUT.24.TMINBITSLICE18.RX_Q5
TCELL20:OUT.25.TMINBITSLICE18.RX_Q6
TCELL20:OUT.26.TMINBITSLICE18.RX_Q7
TCELL20:OUT.27.TMINBITSLICE18.TX_CNTVALUEOUT0
TCELL20:OUT.28.TMINBITSLICE18.TX_CNTVALUEOUT1
TCELL20:OUT.29.TMINBITSLICE18.TX_CNTVALUEOUT2
TCELL20:OUT.30.TMINBITSLICE18.TX_CNTVALUEOUT3
TCELL20:OUT.31.TMINBITSLICE18.TX_CNTVALUEOUT4
TCELL20:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.TXBIT_RST_B4
TCELL20:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.RXBIT_RST_B4
TCELL20:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.ODELAY_RST_B4
TCELL20:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.IDELAY_RST_B4
TCELL20:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK4
TCELL20:IMUX.BYP.0PLL1.TESTIN4
TCELL20:IMUX.BYP.1PLL1.TESTIN5
TCELL20:IMUX.BYP.2PLL1.TESTIN6
TCELL20:IMUX.BYP.3PLL1.TESTIN7
TCELL20:IMUX.BYP.6BITSLICE17.RX_INC
TCELL20:IMUX.BYP.7BITSLICE17.RX_EN_VTC
TCELL20:IMUX.BYP.8BITSLICE17.RX_CE_IDELAY
TCELL20:IMUX.BYP.9BITSLICE17.DYN_DCI_OUT_INT
TCELL20:IMUX.BYP.10BITSLICE18.TX_LD
TCELL20:IMUX.BYP.11BITSLICE18.TX_INC
TCELL20:IMUX.BYP.12BITSLICE18.TX_EN_VTC
TCELL20:IMUX.BYP.13BITSLICE18.TX_CE_ODELAY
TCELL20:IMUX.BYP.14BITSLICE18.RX_LD
TCELL20:IMUX.BYP.15BITSLICE18.RX_INC
TCELL20:IMUX.IMUX.0.DELAYPLL1.SCANMODEB
TCELL20:IMUX.IMUX.6.DELAYBITSLICE17.RX_DATAIN1
TCELL20:IMUX.IMUX.7.DELAYBITSLICE17.TX_D0
TCELL20:IMUX.IMUX.8.DELAYBITSLICE17.TX_D4
TCELL20:IMUX.IMUX.9.DELAYBITSLICE17.TX_D6
TCELL20:IMUX.IMUX.10.DELAYBITSLICE17.TX_CNTVALUEIN2
TCELL20:IMUX.IMUX.11.DELAYBITSLICE17.TX_CNTVALUEIN4
TCELL20:IMUX.IMUX.12.DELAYBITSLICE17.TX_CNTVALUEIN8
TCELL20:IMUX.IMUX.13.DELAYBITSLICE17.RX_CNTVALUEIN1
TCELL20:IMUX.IMUX.14.DELAYBITSLICE17.RX_CNTVALUEIN5
TCELL20:IMUX.IMUX.15.DELAYBITSLICE17.RX_CNTVALUEIN7
TCELL20:IMUX.IMUX.16.DELAYBITSLICE16.TX_CNTVALUEIN6
TCELL20:IMUX.IMUX.17.DELAYBITSLICE16.TX_CNTVALUEIN7
TCELL20:IMUX.IMUX.18.DELAYBITSLICE16.TX_CNTVALUEIN8
TCELL20:IMUX.IMUX.19.DELAYBITSLICE16.RX_CNTVALUEIN0
TCELL20:IMUX.IMUX.20.DELAYBITSLICE16.RX_CNTVALUEIN1
TCELL20:IMUX.IMUX.21.DELAYBITSLICE16.RX_CNTVALUEIN2
TCELL20:IMUX.IMUX.22.DELAYBITSLICE16.RX_CNTVALUEIN3
TCELL20:IMUX.IMUX.23.DELAYBITSLICE16.RX_CNTVALUEIN4
TCELL20:IMUX.IMUX.24.DELAYBITSLICE16.RX_CNTVALUEIN5
TCELL20:IMUX.IMUX.25.DELAYBITSLICE16.RX_CNTVALUEIN6
TCELL20:IMUX.IMUX.26.DELAYBITSLICE16.RX_CNTVALUEIN7
TCELL20:IMUX.IMUX.27.DELAYBITSLICE16.RX_CNTVALUEIN8
TCELL20:IMUX.IMUX.28.DELAYBITSLICE17.TX_T
TCELL20:IMUX.IMUX.29.DELAYBITSLICE17.TX_CE_OFD
TCELL20:IMUX.IMUX.30.DELAYBITSLICE17.RX_CE_IFD
TCELL20:IMUX.IMUX.31.DELAYBITSLICE17.CLB2PHY_FIFO_RDEN
TCELL20:IMUX.IMUX.32.DELAYBITSLICE17.TX_D1
TCELL20:IMUX.IMUX.33.DELAYBITSLICE17.TX_D2
TCELL20:IMUX.IMUX.34.DELAYBITSLICE17.TX_D3
TCELL20:IMUX.IMUX.35.DELAYBITSLICE17.TX_D5
TCELL20:IMUX.IMUX.36.DELAYBITSLICE17.TX_D7
TCELL20:IMUX.IMUX.37.DELAYBITSLICE17.TX_CNTVALUEIN0
TCELL20:IMUX.IMUX.38.DELAYBITSLICE17.TX_CNTVALUEIN1
TCELL20:IMUX.IMUX.39.DELAYBITSLICE17.TX_CNTVALUEIN3
TCELL20:IMUX.IMUX.40.DELAYBITSLICE17.TX_CNTVALUEIN5
TCELL20:IMUX.IMUX.41.DELAYBITSLICE17.TX_CNTVALUEIN6
TCELL20:IMUX.IMUX.42.DELAYBITSLICE17.TX_CNTVALUEIN7
TCELL20:IMUX.IMUX.43.DELAYBITSLICE17.RX_CNTVALUEIN0
TCELL20:IMUX.IMUX.44.DELAYBITSLICE17.RX_CNTVALUEIN2
TCELL20:IMUX.IMUX.45.DELAYBITSLICE17.RX_CNTVALUEIN3
TCELL20:IMUX.IMUX.46.DELAYBITSLICE17.RX_CNTVALUEIN4
TCELL20:IMUX.IMUX.47.DELAYBITSLICE17.RX_CNTVALUEIN6
TCELL21:OUT.0.TMINPLL1.TESTOUT4
TCELL21:OUT.1.TMINPLL1.TESTOUT5
TCELL21:OUT.2.TMINPLL1.TESTOUT6
TCELL21:OUT.3.TMINPLL1.TESTOUT7
TCELL21:OUT.4.TMINBITSLICE18.TX_CNTVALUEOUT5
TCELL21:OUT.5.TMINBITSLICE18.TX_CNTVALUEOUT6
TCELL21:OUT.6.TMINBITSLICE18.TX_CNTVALUEOUT7
TCELL21:OUT.7.TMINBITSLICE18.TX_CNTVALUEOUT8
TCELL21:OUT.8.TMINBITSLICE19.TX_T_OUT
TCELL21:OUT.9.TMINBITSLICE18.RX_CNTVALUEOUT0
TCELL21:OUT.10.TMINBITSLICE18.RX_CNTVALUEOUT1
TCELL21:OUT.11.TMINBITSLICE18.RX_CNTVALUEOUT2
TCELL21:OUT.12.TMINBITSLICE18.RX_CNTVALUEOUT3
TCELL21:OUT.13.TMINBITSLICE18.RX_CNTVALUEOUT4
TCELL21:OUT.14.TMINBITSLICE18.RX_CNTVALUEOUT5
TCELL21:OUT.15.TMINBITSLICE18.RX_CNTVALUEOUT6
TCELL21:OUT.16.TMINBITSLICE18.RX_CNTVALUEOUT7
TCELL21:OUT.17.TMINBITSLICE18.RX_CNTVALUEOUT8
TCELL21:OUT.18.TMINRIU_OR1.RIU_RD_VALID
TCELL21:OUT.19.TMINRIU_OR1.RIU_RD_DATA0
TCELL21:OUT.20.TMINRIU_OR1.RIU_RD_DATA1
TCELL21:OUT.21.TMINRIU_OR1.RIU_RD_DATA2
TCELL21:OUT.22.TMINRIU_OR1.RIU_RD_DATA3
TCELL21:OUT.23.TMINRIU_OR1.RIU_RD_DATA4
TCELL21:OUT.24.TMINRIU_OR1.RIU_RD_DATA5
TCELL21:OUT.25.TMINRIU_OR1.RIU_RD_DATA6
TCELL21:OUT.26.TMINRIU_OR1.RIU_RD_DATA7
TCELL21:OUT.27.TMINRIU_OR1.RIU_RD_DATA8
TCELL21:OUT.28.TMINRIU_OR1.RIU_RD_DATA9
TCELL21:OUT.29.TMINRIU_OR1.RIU_RD_DATA10
TCELL21:OUT.30.TMINRIU_OR1.RIU_RD_DATA11
TCELL21:OUT.31.TMINRIU_OR1.RIU_RD_DATA12
TCELL21:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.TXBIT_RST_B5
TCELL21:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.RXBIT_RST_B5
TCELL21:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.ODELAY_RST_B5
TCELL21:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.IDELAY_RST_B5
TCELL21:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK5
TCELL21:IMUX.BYP.0PLL1.TESTIN0
TCELL21:IMUX.BYP.1PLL1.TESTIN1
TCELL21:IMUX.BYP.2PLL1.TESTIN2
TCELL21:IMUX.BYP.3PLL1.TESTIN3
TCELL21:IMUX.BYP.6BITSLICE18.RX_EN_VTC
TCELL21:IMUX.BYP.7BITSLICE18.RX_CE_IDELAY
TCELL21:IMUX.BYP.8BITSLICE18.DYN_DCI_OUT_INT
TCELL21:IMUX.BYP.9XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B0
TCELL21:IMUX.BYP.10XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B1
TCELL21:IMUX.BYP.11XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B2
TCELL21:IMUX.BYP.12XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B3
TCELL21:IMUX.BYP.13XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_RST_MASK_B
TCELL21:IMUX.BYP.14XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_MODE_B
TCELL21:IMUX.BYP.15XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN0
TCELL21:IMUX.IMUX.0.DELAYPLL1.SCANENB
TCELL21:IMUX.IMUX.6.DELAYBITSLICE18.TX_CNTVALUEIN1
TCELL21:IMUX.IMUX.7.DELAYBITSLICE18.TX_CNTVALUEIN3
TCELL21:IMUX.IMUX.8.DELAYBITSLICE18.TX_CNTVALUEIN7
TCELL21:IMUX.IMUX.10.DELAYBITSLICE18.RX_CNTVALUEIN3
TCELL21:IMUX.IMUX.11.DELAYBITSLICE18.RX_CNTVALUEIN5
TCELL21:IMUX.IMUX.12.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_EN, BITSLICE_CONTROL3.CLB2RIU_WR_EN
TCELL21:IMUX.IMUX.13.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA1, BITSLICE_CONTROL3.CLB2RIU_WR_DATA1
TCELL21:IMUX.IMUX.14.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA5, BITSLICE_CONTROL3.CLB2RIU_WR_DATA5
TCELL21:IMUX.IMUX.15.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA7, BITSLICE_CONTROL3.CLB2RIU_WR_DATA7
TCELL21:IMUX.IMUX.16.DELAYBITSLICE17.RX_CNTVALUEIN8
TCELL21:IMUX.IMUX.17.DELAYBITSLICE18.TX_T
TCELL21:IMUX.IMUX.18.DELAYBITSLICE18.TX_CE_OFD
TCELL21:IMUX.IMUX.19.DELAYBITSLICE18.RX_CE_IFD
TCELL21:IMUX.IMUX.20.DELAYBITSLICE18.RX_DATAIN1
TCELL21:IMUX.IMUX.21.DELAYBITSLICE18.CLB2PHY_FIFO_RDEN
TCELL21:IMUX.IMUX.22.DELAYBITSLICE18.TX_D0
TCELL21:IMUX.IMUX.23.DELAYBITSLICE18.TX_D1
TCELL21:IMUX.IMUX.24.DELAYBITSLICE18.TX_D2
TCELL21:IMUX.IMUX.25.DELAYBITSLICE18.TX_D3
TCELL21:IMUX.IMUX.26.DELAYBITSLICE18.TX_D4
TCELL21:IMUX.IMUX.27.DELAYBITSLICE18.TX_D5
TCELL21:IMUX.IMUX.28.DELAYBITSLICE18.TX_D6
TCELL21:IMUX.IMUX.29.DELAYBITSLICE18.TX_D7
TCELL21:IMUX.IMUX.30.DELAYBITSLICE18.TX_CNTVALUEIN0
TCELL21:IMUX.IMUX.31.DELAYBITSLICE18.TX_CNTVALUEIN2
TCELL21:IMUX.IMUX.32.DELAYBITSLICE18.TX_CNTVALUEIN4
TCELL21:IMUX.IMUX.33.DELAYBITSLICE18.TX_CNTVALUEIN5
TCELL21:IMUX.IMUX.34.DELAYBITSLICE18.TX_CNTVALUEIN6
TCELL21:IMUX.IMUX.35.DELAYBITSLICE18.TX_CNTVALUEIN8
TCELL21:IMUX.IMUX.36.DELAYBITSLICE18.RX_CNTVALUEIN0
TCELL21:IMUX.IMUX.37.DELAYBITSLICE18.RX_CNTVALUEIN1
TCELL21:IMUX.IMUX.38.DELAYBITSLICE18.RX_CNTVALUEIN2
TCELL21:IMUX.IMUX.39.DELAYBITSLICE18.RX_CNTVALUEIN4
TCELL21:IMUX.IMUX.40.DELAYBITSLICE18.RX_CNTVALUEIN6
TCELL21:IMUX.IMUX.41.DELAYBITSLICE18.RX_CNTVALUEIN7
TCELL21:IMUX.IMUX.42.DELAYBITSLICE18.RX_CNTVALUEIN8
TCELL21:IMUX.IMUX.43.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA0, BITSLICE_CONTROL3.CLB2RIU_WR_DATA0
TCELL21:IMUX.IMUX.44.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA2, BITSLICE_CONTROL3.CLB2RIU_WR_DATA2
TCELL21:IMUX.IMUX.45.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA3, BITSLICE_CONTROL3.CLB2RIU_WR_DATA3
TCELL21:IMUX.IMUX.46.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA4, BITSLICE_CONTROL3.CLB2RIU_WR_DATA4
TCELL21:IMUX.IMUX.47.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA6, BITSLICE_CONTROL3.CLB2RIU_WR_DATA6
TCELL22:OUT.0.TMINPLL1.TESTOUT0
TCELL22:OUT.1.TMINPLL1.TESTOUT1
TCELL22:OUT.2.TMINPLL1.TESTOUT2
TCELL22:OUT.3.TMINPLL1.TESTOUT3
TCELL22:OUT.4.TMINRIU_OR1.RIU_RD_DATA13
TCELL22:OUT.5.TMINRIU_OR1.RIU_RD_DATA14
TCELL22:OUT.6.TMINRIU_OR1.RIU_RD_DATA15
TCELL22:OUT.7.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT0
TCELL22:OUT.8.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT1
TCELL22:OUT.9.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT2
TCELL22:OUT.10.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT3
TCELL22:OUT.11.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT4
TCELL22:OUT.12.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT5
TCELL22:OUT.13.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT6
TCELL22:OUT.14.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT7
TCELL22:OUT.15.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_OUT
TCELL22:OUT.16.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_FLG_OUT
TCELL22:OUT.17.TMINXIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
TCELL22:OUT.18.TMINBITSLICE25.PHY2CLB_FIFO_EMPTY
TCELL22:OUT.19.TMINBITSLICE25.RX_Q0
TCELL22:OUT.20.TMINBITSLICE25.RX_Q1
TCELL22:OUT.21.TMINBITSLICE25.RX_Q2
TCELL22:OUT.22.TMINBITSLICE25.RX_Q3
TCELL22:OUT.23.TMINBITSLICE25.RX_Q4
TCELL22:OUT.24.TMINBITSLICE25.RX_Q5
TCELL22:OUT.25.TMINBITSLICE25.RX_Q6
TCELL22:OUT.26.TMINBITSLICE25.RX_Q7
TCELL22:OUT.27.TMINBITSLICE25.TX_CNTVALUEOUT0
TCELL22:OUT.28.TMINBITSLICE25.TX_CNTVALUEOUT1
TCELL22:OUT.29.TMINBITSLICE25.TX_CNTVALUEOUT2
TCELL22:OUT.30.TMINBITSLICE25.TX_CNTVALUEOUT3
TCELL22:OUT.31.TMINBITSLICE25.TX_CNTVALUEOUT4
TCELL22:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_SDR
TCELL22:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_DIV4
TCELL22:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_DIV2
TCELL22:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.TXBIT_RST_B12
TCELL22:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.RXBIT_RST_B12
TCELL22:IMUX.BYP.0PLL1.DADDR4
TCELL22:IMUX.BYP.1PLL1.DADDR5
TCELL22:IMUX.BYP.2PLL1.DADDR6
TCELL22:IMUX.BYP.6XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN1
TCELL22:IMUX.BYP.7XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN2
TCELL22:IMUX.BYP.8XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN3
TCELL22:IMUX.BYP.10XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN4
TCELL22:IMUX.BYP.11XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN5
TCELL22:IMUX.BYP.12XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN6
TCELL22:IMUX.BYP.13XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN7
TCELL22:IMUX.BYP.14XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_EN_B
TCELL22:IMUX.BYP.15BITSLICE25.TX_LD
TCELL22:IMUX.IMUX.0.DELAYPLL1.SCANIN
TCELL22:IMUX.IMUX.6.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_TEST_DIV4_CLK_SEL_B
TCELL22:IMUX.IMUX.7.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CT_START_EN
TCELL22:IMUX.IMUX.8.DELAYBITSLICE25.TX_CE_OFD
TCELL22:IMUX.IMUX.9.DELAYBITSLICE25.RX_DATAIN1
TCELL22:IMUX.IMUX.10.DELAYBITSLICE25.TX_D2
TCELL22:IMUX.IMUX.11.DELAYBITSLICE25.TX_D4
TCELL22:IMUX.IMUX.12.DELAYBITSLICE25.TX_CNTVALUEIN0
TCELL22:IMUX.IMUX.13.DELAYBITSLICE25.TX_CNTVALUEIN2
TCELL22:IMUX.IMUX.14.DELAYBITSLICE25.TX_CNTVALUEIN6
TCELL22:IMUX.IMUX.15.DELAYBITSLICE25.TX_CNTVALUEIN8
TCELL22:IMUX.IMUX.16.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA8, BITSLICE_CONTROL3.CLB2RIU_WR_DATA8
TCELL22:IMUX.IMUX.17.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA9, BITSLICE_CONTROL3.CLB2RIU_WR_DATA9
TCELL22:IMUX.IMUX.18.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA10, BITSLICE_CONTROL3.CLB2RIU_WR_DATA10
TCELL22:IMUX.IMUX.19.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA11, BITSLICE_CONTROL3.CLB2RIU_WR_DATA11
TCELL22:IMUX.IMUX.20.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA12, BITSLICE_CONTROL3.CLB2RIU_WR_DATA12
TCELL22:IMUX.IMUX.21.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA13, BITSLICE_CONTROL3.CLB2RIU_WR_DATA13
TCELL22:IMUX.IMUX.22.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA14, BITSLICE_CONTROL3.CLB2RIU_WR_DATA14
TCELL22:IMUX.IMUX.23.DELAYBITSLICE_CONTROL2.CLB2RIU_WR_DATA15, BITSLICE_CONTROL3.CLB2RIU_WR_DATA15
TCELL22:IMUX.IMUX.24.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR0, BITSLICE_CONTROL3.CLB2RIU_ADDR0
TCELL22:IMUX.IMUX.25.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR1, BITSLICE_CONTROL3.CLB2RIU_ADDR1
TCELL22:IMUX.IMUX.26.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR2, BITSLICE_CONTROL3.CLB2RIU_ADDR2
TCELL22:IMUX.IMUX.27.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR3, BITSLICE_CONTROL3.CLB2RIU_ADDR3
TCELL22:IMUX.IMUX.28.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR4, BITSLICE_CONTROL3.CLB2RIU_ADDR4
TCELL22:IMUX.IMUX.29.DELAYBITSLICE_CONTROL2.CLB2RIU_ADDR5, BITSLICE_CONTROL3.CLB2RIU_ADDR5
TCELL22:IMUX.IMUX.30.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SDR_CLK_SEL_B
TCELL22:IMUX.IMUX.31.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_TEST_DIV2_CLK_SEL_B
TCELL22:IMUX.IMUX.32.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CLK_STOP_FLG_OUT
TCELL22:IMUX.IMUX.33.DELAYXIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
TCELL22:IMUX.IMUX.34.DELAYBITSLICE25.TX_T
TCELL22:IMUX.IMUX.35.DELAYBITSLICE25.RX_CE_IFD
TCELL22:IMUX.IMUX.36.DELAYBITSLICE25.CLB2PHY_FIFO_RDEN
TCELL22:IMUX.IMUX.37.DELAYBITSLICE25.TX_D0
TCELL22:IMUX.IMUX.38.DELAYBITSLICE25.TX_D1
TCELL22:IMUX.IMUX.39.DELAYBITSLICE25.TX_D3
TCELL22:IMUX.IMUX.40.DELAYBITSLICE25.TX_D5
TCELL22:IMUX.IMUX.41.DELAYBITSLICE25.TX_D6
TCELL22:IMUX.IMUX.42.DELAYBITSLICE25.TX_D7
TCELL22:IMUX.IMUX.43.DELAYBITSLICE25.TX_CNTVALUEIN1
TCELL22:IMUX.IMUX.44.DELAYBITSLICE25.TX_CNTVALUEIN3
TCELL22:IMUX.IMUX.45.DELAYBITSLICE25.TX_CNTVALUEIN4
TCELL22:IMUX.IMUX.46.DELAYBITSLICE25.TX_CNTVALUEIN5
TCELL22:IMUX.IMUX.47.DELAYBITSLICE25.TX_CNTVALUEIN7
TCELL23:OUT.0.TMINPLL1.DOUT12
TCELL23:OUT.1.TMINPLL1.DOUT13
TCELL23:OUT.2.TMINPLL1.DOUT14
TCELL23:OUT.3.TMINPLL1.DOUT15
TCELL23:OUT.4.TMINBITSLICE25.TX_CNTVALUEOUT5
TCELL23:OUT.5.TMINBITSLICE25.TX_CNTVALUEOUT6
TCELL23:OUT.6.TMINBITSLICE25.TX_CNTVALUEOUT7
TCELL23:OUT.7.TMINBITSLICE25.TX_CNTVALUEOUT8
TCELL23:OUT.8.TMINBITSLICE20.TX_T_OUT
TCELL23:OUT.9.TMINBITSLICE25.RX_CNTVALUEOUT0
TCELL23:OUT.10.TMINBITSLICE25.RX_CNTVALUEOUT1
TCELL23:OUT.11.TMINBITSLICE25.RX_CNTVALUEOUT2
TCELL23:OUT.12.TMINBITSLICE25.RX_CNTVALUEOUT3
TCELL23:OUT.13.TMINBITSLICE25.RX_CNTVALUEOUT4
TCELL23:OUT.14.TMINBITSLICE25.RX_CNTVALUEOUT5
TCELL23:OUT.15.TMINBITSLICE25.RX_CNTVALUEOUT6
TCELL23:OUT.16.TMINBITSLICE25.RX_CNTVALUEOUT7
TCELL23:OUT.17.TMINBITSLICE25.RX_CNTVALUEOUT8
TCELL23:OUT.18.TMINBITSLICE19.PHY2CLB_FIFO_EMPTY
TCELL23:OUT.19.TMINBITSLICE19.RX_Q0
TCELL23:OUT.20.TMINBITSLICE19.RX_Q1
TCELL23:OUT.21.TMINBITSLICE19.RX_Q2
TCELL23:OUT.22.TMINBITSLICE19.RX_Q3
TCELL23:OUT.23.TMINBITSLICE19.RX_Q4
TCELL23:OUT.24.TMINBITSLICE19.RX_Q5
TCELL23:OUT.25.TMINBITSLICE19.RX_Q6
TCELL23:OUT.26.TMINBITSLICE19.RX_Q7
TCELL23:OUT.27.TMINBITSLICE19.TX_CNTVALUEOUT0
TCELL23:OUT.28.TMINBITSLICE19.TX_CNTVALUEOUT1
TCELL23:OUT.29.TMINBITSLICE19.TX_CNTVALUEOUT2
TCELL23:OUT.30.TMINBITSLICE19.TX_CNTVALUEOUT3
TCELL23:OUT.31.TMINBITSLICE19.TX_CNTVALUEOUT4
TCELL23:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.ODELAY_RST_B12
TCELL23:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.IDELAY_RST_B12
TCELL23:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK12
TCELL23:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.TXBIT_RST_B6
TCELL23:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.RXBIT_RST_B6
TCELL23:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.ODELAY_RST_B6
TCELL23:IMUX.BYP.0PLL1.DADDR0
TCELL23:IMUX.BYP.1PLL1.DADDR1
TCELL23:IMUX.BYP.2PLL1.DADDR2
TCELL23:IMUX.BYP.3PLL1.DADDR3
TCELL23:IMUX.BYP.6BITSLICE25.TX_INC
TCELL23:IMUX.BYP.7BITSLICE25.TX_EN_VTC
TCELL23:IMUX.BYP.8BITSLICE25.TX_CE_ODELAY
TCELL23:IMUX.BYP.9BITSLICE25.RX_LD
TCELL23:IMUX.BYP.10BITSLICE25.RX_INC
TCELL23:IMUX.BYP.11BITSLICE25.RX_EN_VTC
TCELL23:IMUX.BYP.12BITSLICE25.RX_CE_IDELAY
TCELL23:IMUX.BYP.13BITSLICE25.DYN_DCI_OUT_INT
TCELL23:IMUX.BYP.14BITSLICE19.TX_LD
TCELL23:IMUX.BYP.15BITSLICE19.TX_INC
TCELL23:IMUX.IMUX.6.DELAYBITSLICE19.TX_D0
TCELL23:IMUX.IMUX.7.DELAYBITSLICE19.TX_D2
TCELL23:IMUX.IMUX.8.DELAYBITSLICE19.TX_D6
TCELL23:IMUX.IMUX.9.DELAYBITSLICE19.TX_CNTVALUEIN0
TCELL23:IMUX.IMUX.10.DELAYBITSLICE19.TX_CNTVALUEIN4
TCELL23:IMUX.IMUX.11.DELAYBITSLICE19.TX_CNTVALUEIN6
TCELL23:IMUX.IMUX.12.DELAYBITSLICE19.RX_CNTVALUEIN1
TCELL23:IMUX.IMUX.13.DELAYBITSLICE19.RX_CNTVALUEIN3
TCELL23:IMUX.IMUX.14.DELAYBITSLICE19.RX_CNTVALUEIN7
TCELL23:IMUX.IMUX.15.DELAYBITSLICE20.TX_T
TCELL23:IMUX.IMUX.16.DELAYBITSLICE25.RX_CNTVALUEIN0
TCELL23:IMUX.IMUX.17.DELAYBITSLICE25.RX_CNTVALUEIN1
TCELL23:IMUX.IMUX.18.DELAYBITSLICE25.RX_CNTVALUEIN2
TCELL23:IMUX.IMUX.19.DELAYBITSLICE25.RX_CNTVALUEIN3
TCELL23:IMUX.IMUX.20.DELAYBITSLICE25.RX_CNTVALUEIN4
TCELL23:IMUX.IMUX.21.DELAYBITSLICE25.RX_CNTVALUEIN5
TCELL23:IMUX.IMUX.22.DELAYBITSLICE25.RX_CNTVALUEIN6
TCELL23:IMUX.IMUX.23.DELAYBITSLICE25.RX_CNTVALUEIN7
TCELL23:IMUX.IMUX.24.DELAYBITSLICE25.RX_CNTVALUEIN8
TCELL23:IMUX.IMUX.25.DELAYBITSLICE19.TX_T
TCELL23:IMUX.IMUX.26.DELAYBITSLICE19.TX_CE_OFD
TCELL23:IMUX.IMUX.27.DELAYBITSLICE19.RX_CE_IFD
TCELL23:IMUX.IMUX.29.DELAYBITSLICE19.RX_DATAIN1
TCELL23:IMUX.IMUX.30.DELAYBITSLICE19.CLB2PHY_FIFO_RDEN
TCELL23:IMUX.IMUX.31.DELAYBITSLICE19.TX_D1
TCELL23:IMUX.IMUX.32.DELAYBITSLICE19.TX_D3
TCELL23:IMUX.IMUX.33.DELAYBITSLICE19.TX_D4
TCELL23:IMUX.IMUX.34.DELAYBITSLICE19.TX_D5
TCELL23:IMUX.IMUX.35.DELAYBITSLICE19.TX_D7
TCELL23:IMUX.IMUX.36.DELAYBITSLICE19.TX_CNTVALUEIN1
TCELL23:IMUX.IMUX.37.DELAYBITSLICE19.TX_CNTVALUEIN2
TCELL23:IMUX.IMUX.38.DELAYBITSLICE19.TX_CNTVALUEIN3
TCELL23:IMUX.IMUX.39.DELAYBITSLICE19.TX_CNTVALUEIN5
TCELL23:IMUX.IMUX.40.DELAYBITSLICE19.TX_CNTVALUEIN7
TCELL23:IMUX.IMUX.41.DELAYBITSLICE19.TX_CNTVALUEIN8
TCELL23:IMUX.IMUX.42.DELAYBITSLICE19.RX_CNTVALUEIN0
TCELL23:IMUX.IMUX.43.DELAYBITSLICE19.RX_CNTVALUEIN2
TCELL23:IMUX.IMUX.44.DELAYBITSLICE19.RX_CNTVALUEIN4
TCELL23:IMUX.IMUX.45.DELAYBITSLICE19.RX_CNTVALUEIN5
TCELL23:IMUX.IMUX.46.DELAYBITSLICE19.RX_CNTVALUEIN6
TCELL23:IMUX.IMUX.47.DELAYBITSLICE19.RX_CNTVALUEIN8
TCELL24:OUT.0.TMINPLL1.DOUT8
TCELL24:OUT.1.TMINPLL1.DOUT9
TCELL24:OUT.2.TMINPLL1.DOUT10
TCELL24:OUT.3.TMINPLL1.DOUT11
TCELL24:OUT.4.TMINBITSLICE19.TX_CNTVALUEOUT5
TCELL24:OUT.5.TMINBITSLICE19.TX_CNTVALUEOUT6
TCELL24:OUT.6.TMINBITSLICE19.TX_CNTVALUEOUT7
TCELL24:OUT.7.TMINBITSLICE19.TX_CNTVALUEOUT8
TCELL24:OUT.8.TMINBITSLICE21.TX_T_OUT
TCELL24:OUT.9.TMINBITSLICE19.RX_CNTVALUEOUT0
TCELL24:OUT.10.TMINBITSLICE19.RX_CNTVALUEOUT1
TCELL24:OUT.11.TMINBITSLICE19.RX_CNTVALUEOUT2
TCELL24:OUT.12.TMINBITSLICE19.RX_CNTVALUEOUT3
TCELL24:OUT.13.TMINBITSLICE19.RX_CNTVALUEOUT4
TCELL24:OUT.14.TMINBITSLICE19.RX_CNTVALUEOUT5
TCELL24:OUT.15.TMINBITSLICE19.RX_CNTVALUEOUT6
TCELL24:OUT.16.TMINBITSLICE19.RX_CNTVALUEOUT7
TCELL24:OUT.17.TMINBITSLICE19.RX_CNTVALUEOUT8
TCELL24:OUT.18.TMINBITSLICE20.PHY2CLB_FIFO_EMPTY
TCELL24:OUT.19.TMINBITSLICE20.RX_Q0
TCELL24:OUT.20.TMINBITSLICE20.RX_Q1
TCELL24:OUT.21.TMINBITSLICE20.RX_Q2
TCELL24:OUT.22.TMINBITSLICE20.RX_Q3
TCELL24:OUT.23.TMINBITSLICE20.RX_Q4
TCELL24:OUT.24.TMINBITSLICE20.RX_Q5
TCELL24:OUT.25.TMINBITSLICE20.RX_Q6
TCELL24:OUT.26.TMINBITSLICE20.RX_Q7
TCELL24:OUT.27.TMINBITSLICE20.TX_CNTVALUEOUT0
TCELL24:OUT.28.TMINBITSLICE20.TX_CNTVALUEOUT1
TCELL24:OUT.29.TMINBITSLICE20.TX_CNTVALUEOUT2
TCELL24:OUT.30.TMINBITSLICE20.TX_CNTVALUEOUT3
TCELL24:OUT.31.TMINBITSLICE20.TX_CNTVALUEOUT4
TCELL24:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.IDELAY_RST_B6
TCELL24:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK6
TCELL24:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.TXBIT_RST_B7
TCELL24:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.RXBIT_RST_B7
TCELL24:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.ODELAY_RST_B7
TCELL24:IMUX.BYP.0PLL1.DI12
TCELL24:IMUX.BYP.1PLL1.DI13
TCELL24:IMUX.BYP.2PLL1.DI14
TCELL24:IMUX.BYP.3PLL1.DI15
TCELL24:IMUX.BYP.6BITSLICE19.TX_EN_VTC
TCELL24:IMUX.BYP.7BITSLICE19.TX_CE_ODELAY
TCELL24:IMUX.BYP.8BITSLICE19.RX_LD
TCELL24:IMUX.BYP.9BITSLICE19.RX_INC
TCELL24:IMUX.BYP.10BITSLICE19.RX_EN_VTC
TCELL24:IMUX.BYP.11BITSLICE19.RX_CE_IDELAY
TCELL24:IMUX.BYP.12BITSLICE19.DYN_DCI_OUT_INT
TCELL24:IMUX.BYP.14BITSLICE20.TX_LD
TCELL24:IMUX.BYP.15BITSLICE20.TX_INC
TCELL24:IMUX.IMUX.0.DELAYPLL1.DWE
TCELL24:IMUX.IMUX.6.DELAYBITSLICE20.TX_CNTVALUEIN3
TCELL24:IMUX.IMUX.7.DELAYBITSLICE20.TX_CNTVALUEIN5
TCELL24:IMUX.IMUX.8.DELAYBITSLICE20.RX_CNTVALUEIN0
TCELL24:IMUX.IMUX.9.DELAYBITSLICE20.RX_CNTVALUEIN2
TCELL24:IMUX.IMUX.10.DELAYBITSLICE20.RX_CNTVALUEIN6
TCELL24:IMUX.IMUX.11.DELAYBITSLICE20.RX_CNTVALUEIN8
TCELL24:IMUX.IMUX.12.DELAYBITSLICE21.RX_DATAIN1
TCELL24:IMUX.IMUX.13.DELAYBITSLICE21.TX_D0
TCELL24:IMUX.IMUX.14.DELAYBITSLICE21.TX_D4
TCELL24:IMUX.IMUX.15.DELAYBITSLICE21.TX_D6
TCELL24:IMUX.IMUX.16.DELAYBITSLICE20.TX_CE_OFD
TCELL24:IMUX.IMUX.17.DELAYBITSLICE20.RX_CE_IFD
TCELL24:IMUX.IMUX.18.DELAYBITSLICE20.RX_DATAIN1
TCELL24:IMUX.IMUX.19.DELAYBITSLICE20.CLB2PHY_FIFO_RDEN
TCELL24:IMUX.IMUX.20.DELAYBITSLICE20.TX_D0
TCELL24:IMUX.IMUX.21.DELAYBITSLICE20.TX_D1
TCELL24:IMUX.IMUX.22.DELAYBITSLICE20.TX_D2
TCELL24:IMUX.IMUX.23.DELAYBITSLICE20.TX_D3
TCELL24:IMUX.IMUX.24.DELAYBITSLICE20.TX_D4
TCELL24:IMUX.IMUX.25.DELAYBITSLICE20.TX_D5
TCELL24:IMUX.IMUX.26.DELAYBITSLICE20.TX_D6
TCELL24:IMUX.IMUX.27.DELAYBITSLICE20.TX_D7
TCELL24:IMUX.IMUX.28.DELAYBITSLICE20.TX_CNTVALUEIN0
TCELL24:IMUX.IMUX.29.DELAYBITSLICE20.TX_CNTVALUEIN1
TCELL24:IMUX.IMUX.30.DELAYBITSLICE20.TX_CNTVALUEIN2
TCELL24:IMUX.IMUX.31.DELAYBITSLICE20.TX_CNTVALUEIN4
TCELL24:IMUX.IMUX.32.DELAYBITSLICE20.TX_CNTVALUEIN6
TCELL24:IMUX.IMUX.33.DELAYBITSLICE20.TX_CNTVALUEIN7
TCELL24:IMUX.IMUX.34.DELAYBITSLICE20.TX_CNTVALUEIN8
TCELL24:IMUX.IMUX.35.DELAYBITSLICE20.RX_CNTVALUEIN1
TCELL24:IMUX.IMUX.36.DELAYBITSLICE20.RX_CNTVALUEIN3
TCELL24:IMUX.IMUX.37.DELAYBITSLICE20.RX_CNTVALUEIN4
TCELL24:IMUX.IMUX.38.DELAYBITSLICE20.RX_CNTVALUEIN5
TCELL24:IMUX.IMUX.39.DELAYBITSLICE20.RX_CNTVALUEIN7
TCELL24:IMUX.IMUX.40.DELAYBITSLICE21.TX_T
TCELL24:IMUX.IMUX.41.DELAYBITSLICE21.TX_CE_OFD
TCELL24:IMUX.IMUX.42.DELAYBITSLICE21.RX_CE_IFD
TCELL24:IMUX.IMUX.43.DELAYBITSLICE21.CLB2PHY_FIFO_RDEN
TCELL24:IMUX.IMUX.44.DELAYBITSLICE21.TX_D1
TCELL24:IMUX.IMUX.45.DELAYBITSLICE21.TX_D2
TCELL24:IMUX.IMUX.46.DELAYBITSLICE21.TX_D3
TCELL24:IMUX.IMUX.47.DELAYBITSLICE21.TX_D5
TCELL25:OUT.0.TMINPLL1.DOUT4
TCELL25:OUT.1.TMINPLL1.DOUT5
TCELL25:OUT.2.TMINPLL1.DOUT6
TCELL25:OUT.3.TMINPLL1.DOUT7
TCELL25:OUT.4.TMINBITSLICE20.TX_CNTVALUEOUT5
TCELL25:OUT.5.TMINBITSLICE20.TX_CNTVALUEOUT6
TCELL25:OUT.6.TMINBITSLICE20.TX_CNTVALUEOUT7
TCELL25:OUT.7.TMINBITSLICE20.TX_CNTVALUEOUT8
TCELL25:OUT.8.TMINBITSLICE22.TX_T_OUT
TCELL25:OUT.9.TMINBITSLICE20.RX_CNTVALUEOUT0
TCELL25:OUT.10.TMINBITSLICE20.RX_CNTVALUEOUT1
TCELL25:OUT.11.TMINBITSLICE20.RX_CNTVALUEOUT2
TCELL25:OUT.12.TMINBITSLICE20.RX_CNTVALUEOUT3
TCELL25:OUT.13.TMINBITSLICE20.RX_CNTVALUEOUT4
TCELL25:OUT.14.TMINBITSLICE20.RX_CNTVALUEOUT5
TCELL25:OUT.15.TMINBITSLICE20.RX_CNTVALUEOUT6
TCELL25:OUT.16.TMINBITSLICE20.RX_CNTVALUEOUT7
TCELL25:OUT.17.TMINBITSLICE20.RX_CNTVALUEOUT8
TCELL25:OUT.18.TMINBITSLICE21.PHY2CLB_FIFO_EMPTY
TCELL25:OUT.19.TMINBITSLICE21.RX_Q0
TCELL25:OUT.20.TMINBITSLICE21.RX_Q1
TCELL25:OUT.21.TMINBITSLICE21.RX_Q2
TCELL25:OUT.22.TMINBITSLICE21.RX_Q3
TCELL25:OUT.23.TMINBITSLICE21.RX_Q4
TCELL25:OUT.24.TMINBITSLICE21.RX_Q5
TCELL25:OUT.25.TMINBITSLICE21.RX_Q6
TCELL25:OUT.26.TMINBITSLICE21.RX_Q7
TCELL25:OUT.27.TMINBITSLICE21.TX_CNTVALUEOUT0
TCELL25:OUT.28.TMINBITSLICE21.TX_CNTVALUEOUT1
TCELL25:OUT.29.TMINBITSLICE21.TX_CNTVALUEOUT2
TCELL25:OUT.30.TMINBITSLICE21.TX_CNTVALUEOUT3
TCELL25:OUT.31.TMINBITSLICE21.TX_CNTVALUEOUT4
TCELL25:IMUX.CTRL.0PLL1.DCLK_B
TCELL25:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.IDELAY_RST_B7
TCELL25:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK7
TCELL25:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.TXBIT_RST_B8
TCELL25:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.RXBIT_RST_B8
TCELL25:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.ODELAY_RST_B8
TCELL25:IMUX.BYP.0PLL1.DI8
TCELL25:IMUX.BYP.1PLL1.DI9
TCELL25:IMUX.BYP.2PLL1.DI10
TCELL25:IMUX.BYP.3PLL1.DI11
TCELL25:IMUX.BYP.6BITSLICE20.TX_EN_VTC
TCELL25:IMUX.BYP.7BITSLICE20.TX_CE_ODELAY
TCELL25:IMUX.BYP.8BITSLICE20.RX_LD
TCELL25:IMUX.BYP.9BITSLICE20.RX_INC
TCELL25:IMUX.BYP.10BITSLICE20.RX_EN_VTC
TCELL25:IMUX.BYP.11BITSLICE20.RX_CE_IDELAY
TCELL25:IMUX.BYP.12BITSLICE20.DYN_DCI_OUT_INT
TCELL25:IMUX.BYP.13BITSLICE21.TX_LD
TCELL25:IMUX.BYP.14BITSLICE21.TX_INC
TCELL25:IMUX.BYP.15BITSLICE21.TX_EN_VTC
TCELL25:IMUX.IMUX.0.DELAYPLL1.DEN
TCELL25:IMUX.IMUX.6.DELAYBITSLICE21.RX_CNTVALUEIN4
TCELL25:IMUX.IMUX.7.DELAYBITSLICE21.RX_CNTVALUEIN6
TCELL25:IMUX.IMUX.8.DELAYBITSLICE_T3.CNTVALUEIN1
TCELL25:IMUX.IMUX.9.DELAYBITSLICE_T3.CNTVALUEIN3
TCELL25:IMUX.IMUX.10.DELAYBITSLICE_T3.CNTVALUEIN7
TCELL25:IMUX.IMUX.11.DELAYBITSLICE_CONTROL3.CLB2RIU_NIBBLE_SEL
TCELL25:IMUX.IMUX.12.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS1_3
TCELL25:IMUX.IMUX.13.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS0_1
TCELL25:IMUX.IMUX.14.DELAYBITSLICE_CONTROL3.CLB2PHY_T_B1
TCELL25:IMUX.IMUX.15.DELAYBITSLICE_CONTROL3.CLB2PHY_T_B3
TCELL25:IMUX.IMUX.16.DELAYBITSLICE21.TX_D7
TCELL25:IMUX.IMUX.18.DELAYBITSLICE21.TX_CNTVALUEIN0
TCELL25:IMUX.IMUX.19.DELAYBITSLICE21.TX_CNTVALUEIN1
TCELL25:IMUX.IMUX.20.DELAYBITSLICE21.TX_CNTVALUEIN2
TCELL25:IMUX.IMUX.21.DELAYBITSLICE21.TX_CNTVALUEIN3
TCELL25:IMUX.IMUX.22.DELAYBITSLICE21.TX_CNTVALUEIN4
TCELL25:IMUX.IMUX.23.DELAYBITSLICE21.TX_CNTVALUEIN5
TCELL25:IMUX.IMUX.24.DELAYBITSLICE21.TX_CNTVALUEIN6
TCELL25:IMUX.IMUX.25.DELAYBITSLICE21.TX_CNTVALUEIN7
TCELL25:IMUX.IMUX.26.DELAYBITSLICE21.TX_CNTVALUEIN8
TCELL25:IMUX.IMUX.27.DELAYBITSLICE21.RX_CNTVALUEIN0
TCELL25:IMUX.IMUX.28.DELAYBITSLICE21.RX_CNTVALUEIN1
TCELL25:IMUX.IMUX.29.DELAYBITSLICE21.RX_CNTVALUEIN2
TCELL25:IMUX.IMUX.30.DELAYBITSLICE21.RX_CNTVALUEIN3
TCELL25:IMUX.IMUX.31.DELAYBITSLICE21.RX_CNTVALUEIN5
TCELL25:IMUX.IMUX.32.DELAYBITSLICE21.RX_CNTVALUEIN7
TCELL25:IMUX.IMUX.33.DELAYBITSLICE21.RX_CNTVALUEIN8
TCELL25:IMUX.IMUX.34.DELAYBITSLICE_T3.CNTVALUEIN0
TCELL25:IMUX.IMUX.35.DELAYBITSLICE_T3.CNTVALUEIN2
TCELL25:IMUX.IMUX.36.DELAYBITSLICE_T3.CNTVALUEIN4
TCELL25:IMUX.IMUX.37.DELAYBITSLICE_T3.CNTVALUEIN5
TCELL25:IMUX.IMUX.38.DELAYBITSLICE_T3.CNTVALUEIN6
TCELL25:IMUX.IMUX.39.DELAYBITSLICE_T3.CNTVALUEIN8
TCELL25:IMUX.IMUX.40.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS1_0
TCELL25:IMUX.IMUX.41.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS1_1
TCELL25:IMUX.IMUX.42.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS1_2
TCELL25:IMUX.IMUX.43.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS0_0
TCELL25:IMUX.IMUX.44.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS0_2
TCELL25:IMUX.IMUX.45.DELAYBITSLICE_CONTROL3.CLB2PHY_WRCS0_3
TCELL25:IMUX.IMUX.46.DELAYBITSLICE_CONTROL3.CLB2PHY_T_B0
TCELL25:IMUX.IMUX.47.DELAYBITSLICE_CONTROL3.CLB2PHY_T_B2
TCELL26:OUT.0.TMINPLL1.DOUT0
TCELL26:OUT.1.TMINPLL1.DOUT1
TCELL26:OUT.2.TMINPLL1.DOUT2
TCELL26:OUT.3.TMINPLL1.DOUT3
TCELL26:OUT.4.TMINBITSLICE21.TX_CNTVALUEOUT5
TCELL26:OUT.5.TMINBITSLICE21.TX_CNTVALUEOUT6
TCELL26:OUT.6.TMINBITSLICE21.TX_CNTVALUEOUT7
TCELL26:OUT.7.TMINBITSLICE21.TX_CNTVALUEOUT8
TCELL26:OUT.8.TMINBITSLICE23.TX_T_OUT
TCELL26:OUT.9.TMINBITSLICE21.RX_CNTVALUEOUT0
TCELL26:OUT.10.TMINBITSLICE21.RX_CNTVALUEOUT1
TCELL26:OUT.11.TMINBITSLICE21.RX_CNTVALUEOUT2
TCELL26:OUT.12.TMINBITSLICE21.RX_CNTVALUEOUT3
TCELL26:OUT.13.TMINBITSLICE21.RX_CNTVALUEOUT4
TCELL26:OUT.14.TMINBITSLICE21.RX_CNTVALUEOUT5
TCELL26:OUT.15.TMINBITSLICE21.RX_CNTVALUEOUT6
TCELL26:OUT.16.TMINBITSLICE21.RX_CNTVALUEOUT7
TCELL26:OUT.17.TMINBITSLICE21.RX_CNTVALUEOUT8
TCELL26:OUT.18.TMINBITSLICE_T3.CNTVALUEOUT0
TCELL26:OUT.19.TMINBITSLICE_T3.CNTVALUEOUT1
TCELL26:OUT.20.TMINBITSLICE_T3.CNTVALUEOUT2
TCELL26:OUT.21.TMINBITSLICE_T3.CNTVALUEOUT3
TCELL26:OUT.22.TMINBITSLICE_T3.CNTVALUEOUT4
TCELL26:OUT.23.TMINBITSLICE_T3.CNTVALUEOUT5
TCELL26:OUT.24.TMINBITSLICE_T3.CNTVALUEOUT6
TCELL26:OUT.25.TMINBITSLICE_T3.CNTVALUEOUT7
TCELL26:OUT.26.TMINBITSLICE_T3.CNTVALUEOUT8
TCELL26:OUT.27.TMINBITSLICE_CONTROL3.PHY2CLB_PHY_RDY
TCELL26:OUT.28.TMINBITSLICE_CONTROL3.MASTER_PD_OUT
TCELL26:OUT.29.TMINBITSLICE_CONTROL3.PHY2CLB_FIXDLY_RDY
TCELL26:OUT.30.TMINBITSLICE_CONTROL3.CTRL_DLY_TEST_OUT
TCELL26:OUT.31.TMINBITSLICE24.TX_T_OUT
TCELL26:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.IDELAY_RST_B8
TCELL26:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK8
TCELL26:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.TRISTATE_ODELAY_RST_B1
TCELL26:IMUX.CTRL.6BITSLICE_CONTROL3.REFCLK
TCELL26:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.CTRL_RST_B_UPP
TCELL26:IMUX.BYP.0PLL1.DI4
TCELL26:IMUX.BYP.1PLL1.DI5
TCELL26:IMUX.BYP.2PLL1.DI6
TCELL26:IMUX.BYP.3PLL1.DI7
TCELL26:IMUX.BYP.6BITSLICE21.TX_CE_ODELAY
TCELL26:IMUX.BYP.8BITSLICE21.RX_LD
TCELL26:IMUX.BYP.9BITSLICE21.RX_INC
TCELL26:IMUX.BYP.10BITSLICE21.RX_EN_VTC
TCELL26:IMUX.BYP.11BITSLICE21.RX_CE_IDELAY
TCELL26:IMUX.BYP.12BITSLICE21.DYN_DCI_OUT_INT
TCELL26:IMUX.BYP.13BITSLICE_T3.CE_OFD
TCELL26:IMUX.BYP.14BITSLICE_T3.LD
TCELL26:IMUX.BYP.15BITSLICE_T3.INC
TCELL26:IMUX.IMUX.0.DELAYPLL1.PWRDWN
TCELL26:IMUX.IMUX.6.DELAYBITSLICE22.RX_DATAIN1
TCELL26:IMUX.IMUX.7.DELAYBITSLICE22.TX_D0
TCELL26:IMUX.IMUX.8.DELAYBITSLICE22.TX_D4
TCELL26:IMUX.IMUX.9.DELAYBITSLICE22.TX_D6
TCELL26:IMUX.IMUX.10.DELAYBITSLICE22.TX_CNTVALUEIN2
TCELL26:IMUX.IMUX.11.DELAYBITSLICE22.TX_CNTVALUEIN4
TCELL26:IMUX.IMUX.12.DELAYBITSLICE22.TX_CNTVALUEIN7
TCELL26:IMUX.IMUX.13.DELAYBITSLICE22.RX_CNTVALUEIN0
TCELL26:IMUX.IMUX.14.DELAYBITSLICE22.RX_CNTVALUEIN4
TCELL26:IMUX.IMUX.15.DELAYBITSLICE22.RX_CNTVALUEIN6
TCELL26:IMUX.IMUX.16.DELAYBITSLICE_CONTROL3.CLB2PHY_RDEN0
TCELL26:IMUX.IMUX.17.DELAYBITSLICE_CONTROL3.CLB2PHY_RDEN1
TCELL26:IMUX.IMUX.18.DELAYBITSLICE_CONTROL3.CLB2PHY_RDEN2
TCELL26:IMUX.IMUX.19.DELAYBITSLICE_CONTROL3.CLB2PHY_RDEN3
TCELL26:IMUX.IMUX.20.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS1_0
TCELL26:IMUX.IMUX.21.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS1_1
TCELL26:IMUX.IMUX.22.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS1_2
TCELL26:IMUX.IMUX.23.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS1_3
TCELL26:IMUX.IMUX.24.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS0_0
TCELL26:IMUX.IMUX.25.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS0_1
TCELL26:IMUX.IMUX.26.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS0_2
TCELL26:IMUX.IMUX.27.DELAYBITSLICE_CONTROL3.CLB2PHY_RDCS0_3
TCELL26:IMUX.IMUX.28.DELAYBITSLICE22.TX_T
TCELL26:IMUX.IMUX.29.DELAYBITSLICE22.TX_CE_OFD
TCELL26:IMUX.IMUX.30.DELAYBITSLICE22.RX_CE_IFD
TCELL26:IMUX.IMUX.31.DELAYBITSLICE22.CLB2PHY_FIFO_RDEN
TCELL26:IMUX.IMUX.32.DELAYBITSLICE22.TX_D1
TCELL26:IMUX.IMUX.33.DELAYBITSLICE22.TX_D2
TCELL26:IMUX.IMUX.34.DELAYBITSLICE22.TX_D3
TCELL26:IMUX.IMUX.35.DELAYBITSLICE22.TX_D5
TCELL26:IMUX.IMUX.36.DELAYBITSLICE22.TX_D7
TCELL26:IMUX.IMUX.37.DELAYBITSLICE22.TX_CNTVALUEIN0
TCELL26:IMUX.IMUX.38.DELAYBITSLICE22.TX_CNTVALUEIN1
TCELL26:IMUX.IMUX.39.DELAYBITSLICE22.TX_CNTVALUEIN3
TCELL26:IMUX.IMUX.40.DELAYBITSLICE22.TX_CNTVALUEIN5
TCELL26:IMUX.IMUX.41.DELAYBITSLICE22.TX_CNTVALUEIN6
TCELL26:IMUX.IMUX.43.DELAYBITSLICE22.TX_CNTVALUEIN8
TCELL26:IMUX.IMUX.44.DELAYBITSLICE22.RX_CNTVALUEIN1
TCELL26:IMUX.IMUX.45.DELAYBITSLICE22.RX_CNTVALUEIN2
TCELL26:IMUX.IMUX.46.DELAYBITSLICE22.RX_CNTVALUEIN3
TCELL26:IMUX.IMUX.47.DELAYBITSLICE22.RX_CNTVALUEIN5
TCELL27:OUT.0.TMINPLL1.DRDY
TCELL27:OUT.1.TMINPLL1.LOCKED
TCELL27:OUT.2.TMINPLL1.TESTOUT36
TCELL27:OUT.3.TMINPLL1.SCANOUT
TCELL27:OUT.4.TMINBITSLICE22.PHY2CLB_FIFO_EMPTY
TCELL27:OUT.5.TMINBITSLICE22.RX_Q0
TCELL27:OUT.6.TMINBITSLICE22.RX_Q1
TCELL27:OUT.7.TMINBITSLICE22.RX_Q2
TCELL27:OUT.8.TMINBITSLICE22.RX_Q3
TCELL27:OUT.9.TMINBITSLICE22.RX_Q4
TCELL27:OUT.10.TMINBITSLICE22.RX_Q5
TCELL27:OUT.11.TMINBITSLICE22.RX_Q6
TCELL27:OUT.12.TMINBITSLICE22.RX_Q7
TCELL27:OUT.13.TMINBITSLICE22.TX_CNTVALUEOUT0
TCELL27:OUT.14.TMINBITSLICE22.TX_CNTVALUEOUT1
TCELL27:OUT.15.TMINBITSLICE22.TX_CNTVALUEOUT2
TCELL27:OUT.16.TMINBITSLICE22.TX_CNTVALUEOUT3
TCELL27:OUT.17.TMINBITSLICE22.TX_CNTVALUEOUT4
TCELL27:OUT.18.TMINBITSLICE22.TX_CNTVALUEOUT5
TCELL27:OUT.19.TMINBITSLICE22.TX_CNTVALUEOUT6
TCELL27:OUT.20.TMINBITSLICE22.TX_CNTVALUEOUT7
TCELL27:OUT.21.TMINBITSLICE22.TX_CNTVALUEOUT8
TCELL27:OUT.22.TMINBITSLICE25.TX_T_OUT
TCELL27:OUT.23.TMINBITSLICE22.RX_CNTVALUEOUT0
TCELL27:OUT.24.TMINBITSLICE22.RX_CNTVALUEOUT1
TCELL27:OUT.25.TMINBITSLICE22.RX_CNTVALUEOUT2
TCELL27:OUT.26.TMINBITSLICE22.RX_CNTVALUEOUT3
TCELL27:OUT.27.TMINBITSLICE22.RX_CNTVALUEOUT4
TCELL27:OUT.28.TMINBITSLICE22.RX_CNTVALUEOUT5
TCELL27:OUT.29.TMINBITSLICE22.RX_CNTVALUEOUT6
TCELL27:OUT.30.TMINBITSLICE22.RX_CNTVALUEOUT7
TCELL27:OUT.31.TMINBITSLICE22.RX_CNTVALUEOUT8
TCELL27:IMUX.CTRL.0PLL1.SCANCLK_B
TCELL27:IMUX.CTRL.2BITSLICE_CONTROL3.RIU_CLK, XIPHY_FEEDTHROUGH1.CLB2PHY_CTRL_CLK_UPP
TCELL27:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.TXBIT_RST_B9
TCELL27:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.RXBIT_RST_B9
TCELL27:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.ODELAY_RST_B9
TCELL27:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.IDELAY_RST_B9
TCELL27:IMUX.BYP.0PLL1.DI0
TCELL27:IMUX.BYP.1PLL1.DI1
TCELL27:IMUX.BYP.2PLL1.DI2
TCELL27:IMUX.BYP.3PLL1.DI3
TCELL27:IMUX.BYP.6BITSLICE_T3.CE_ODELAY
TCELL27:IMUX.BYP.7BITSLICE_CONTROL3.EN_VTC
TCELL27:IMUX.BYP.8BITSLICE_CONTROL3.CTRL_DLY_TEST_IN
TCELL27:IMUX.BYP.9BITSLICE22.TX_LD
TCELL27:IMUX.BYP.10BITSLICE22.TX_INC
TCELL27:IMUX.BYP.11BITSLICE22.TX_EN_VTC
TCELL27:IMUX.BYP.12BITSLICE22.TX_CE_ODELAY
TCELL27:IMUX.BYP.13BITSLICE22.RX_LD
TCELL27:IMUX.BYP.14BITSLICE22.RX_INC
TCELL27:IMUX.BYP.15BITSLICE22.RX_EN_VTC
TCELL27:IMUX.IMUX.0.DELAYPLL1.RST
TCELL27:IMUX.IMUX.6.DELAYBITSLICE23.TX_CNTVALUEIN0
TCELL27:IMUX.IMUX.7.DELAYBITSLICE23.TX_CNTVALUEIN2
TCELL27:IMUX.IMUX.8.DELAYBITSLICE23.TX_CNTVALUEIN6
TCELL27:IMUX.IMUX.9.DELAYBITSLICE23.TX_CNTVALUEIN8
TCELL27:IMUX.IMUX.10.DELAYBITSLICE23.RX_CNTVALUEIN3
TCELL27:IMUX.IMUX.11.DELAYBITSLICE23.RX_CNTVALUEIN5
TCELL27:IMUX.IMUX.12.DELAYBITSLICE24.TX_T
TCELL27:IMUX.IMUX.13.DELAYBITSLICE24.RX_CE_IFD
TCELL27:IMUX.IMUX.14.DELAYBITSLICE24.TX_D1
TCELL27:IMUX.IMUX.15.DELAYBITSLICE24.TX_D3
TCELL27:IMUX.IMUX.16.DELAYBITSLICE22.RX_CNTVALUEIN7
TCELL27:IMUX.IMUX.17.DELAYBITSLICE22.RX_CNTVALUEIN8
TCELL27:IMUX.IMUX.18.DELAYBITSLICE23.TX_T
TCELL27:IMUX.IMUX.19.DELAYBITSLICE23.TX_CE_OFD
TCELL27:IMUX.IMUX.20.DELAYBITSLICE23.RX_CE_IFD
TCELL27:IMUX.IMUX.21.DELAYBITSLICE23.RX_DATAIN1
TCELL27:IMUX.IMUX.22.DELAYBITSLICE23.CLB2PHY_FIFO_RDEN
TCELL27:IMUX.IMUX.23.DELAYBITSLICE23.TX_D5
TCELL27:IMUX.IMUX.24.DELAYBITSLICE23.TX_D4
TCELL27:IMUX.IMUX.25.DELAYBITSLICE23.TX_D3
TCELL27:IMUX.IMUX.26.DELAYBITSLICE23.TX_D2
TCELL27:IMUX.IMUX.27.DELAYBITSLICE23.TX_D1
TCELL27:IMUX.IMUX.28.DELAYBITSLICE23.TX_D0
TCELL27:IMUX.IMUX.29.DELAYBITSLICE23.TX_D6
TCELL27:IMUX.IMUX.30.DELAYBITSLICE23.TX_D7
TCELL27:IMUX.IMUX.31.DELAYBITSLICE23.TX_CNTVALUEIN1
TCELL27:IMUX.IMUX.32.DELAYBITSLICE23.TX_CNTVALUEIN3
TCELL27:IMUX.IMUX.33.DELAYBITSLICE23.TX_CNTVALUEIN4
TCELL27:IMUX.IMUX.34.DELAYBITSLICE23.TX_CNTVALUEIN5
TCELL27:IMUX.IMUX.35.DELAYBITSLICE23.TX_CNTVALUEIN7
TCELL27:IMUX.IMUX.36.DELAYBITSLICE23.RX_CNTVALUEIN0
TCELL27:IMUX.IMUX.37.DELAYBITSLICE23.RX_CNTVALUEIN1
TCELL27:IMUX.IMUX.38.DELAYBITSLICE23.RX_CNTVALUEIN2
TCELL27:IMUX.IMUX.39.DELAYBITSLICE23.RX_CNTVALUEIN4
TCELL27:IMUX.IMUX.40.DELAYBITSLICE23.RX_CNTVALUEIN6
TCELL27:IMUX.IMUX.41.DELAYBITSLICE23.RX_CNTVALUEIN7
TCELL27:IMUX.IMUX.42.DELAYBITSLICE23.RX_CNTVALUEIN8
TCELL27:IMUX.IMUX.43.DELAYBITSLICE24.TX_CE_OFD
TCELL27:IMUX.IMUX.44.DELAYBITSLICE24.RX_DATAIN1
TCELL27:IMUX.IMUX.45.DELAYBITSLICE24.CLB2PHY_FIFO_RDEN
TCELL27:IMUX.IMUX.46.DELAYBITSLICE24.TX_D0
TCELL27:IMUX.IMUX.47.DELAYBITSLICE24.TX_D2
TCELL28:OUT.4.TMINBITSLICE23.PHY2CLB_FIFO_EMPTY
TCELL28:OUT.5.TMINBITSLICE23.RX_Q0
TCELL28:OUT.6.TMINBITSLICE23.RX_Q1
TCELL28:OUT.7.TMINBITSLICE23.RX_Q2
TCELL28:OUT.8.TMINBITSLICE23.RX_Q3
TCELL28:OUT.9.TMINBITSLICE23.RX_Q4
TCELL28:OUT.10.TMINBITSLICE23.RX_Q5
TCELL28:OUT.11.TMINBITSLICE23.RX_Q6
TCELL28:OUT.12.TMINBITSLICE23.RX_Q7
TCELL28:OUT.13.TMINBITSLICE23.TX_CNTVALUEOUT0
TCELL28:OUT.14.TMINBITSLICE23.TX_CNTVALUEOUT1
TCELL28:OUT.15.TMINBITSLICE23.TX_CNTVALUEOUT2
TCELL28:OUT.16.TMINBITSLICE23.TX_CNTVALUEOUT3
TCELL28:OUT.17.TMINBITSLICE23.TX_CNTVALUEOUT4
TCELL28:OUT.18.TMINBITSLICE23.TX_CNTVALUEOUT5
TCELL28:OUT.19.TMINBITSLICE23.TX_CNTVALUEOUT6
TCELL28:OUT.20.TMINBITSLICE23.TX_CNTVALUEOUT7
TCELL28:OUT.21.TMINBITSLICE23.TX_CNTVALUEOUT8
TCELL28:OUT.23.TMINBITSLICE23.RX_CNTVALUEOUT0
TCELL28:OUT.24.TMINBITSLICE23.RX_CNTVALUEOUT1
TCELL28:OUT.25.TMINBITSLICE23.RX_CNTVALUEOUT2
TCELL28:OUT.26.TMINBITSLICE23.RX_CNTVALUEOUT3
TCELL28:OUT.27.TMINBITSLICE23.RX_CNTVALUEOUT4
TCELL28:OUT.28.TMINBITSLICE23.RX_CNTVALUEOUT5
TCELL28:OUT.29.TMINBITSLICE23.RX_CNTVALUEOUT6
TCELL28:OUT.30.TMINBITSLICE23.RX_CNTVALUEOUT7
TCELL28:OUT.31.TMINBITSLICE23.RX_CNTVALUEOUT8
TCELL28:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK9
TCELL28:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.TXBIT_RST_B10
TCELL28:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.RXBIT_RST_B10
TCELL28:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.ODELAY_RST_B10
TCELL28:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.IDELAY_RST_B10
TCELL28:IMUX.BYP.6BITSLICE22.RX_CE_IDELAY
TCELL28:IMUX.BYP.7BITSLICE22.DYN_DCI_OUT_INT
TCELL28:IMUX.BYP.8BITSLICE23.TX_LD
TCELL28:IMUX.BYP.9BITSLICE23.TX_INC
TCELL28:IMUX.BYP.10BITSLICE23.TX_EN_VTC
TCELL28:IMUX.BYP.11BITSLICE23.TX_CE_ODELAY
TCELL28:IMUX.BYP.12BITSLICE23.RX_LD
TCELL28:IMUX.BYP.13BITSLICE23.RX_INC
TCELL28:IMUX.BYP.14BITSLICE23.RX_EN_VTC
TCELL28:IMUX.BYP.15BITSLICE23.RX_CE_IDELAY
TCELL28:IMUX.IMUX.0.DELAYBUFGCE_DIV0.RST_PRE_OPTINV
TCELL28:IMUX.IMUX.6.DELAYBITSLICE24.TX_D5
TCELL28:IMUX.IMUX.7.DELAYBITSLICE24.TX_D6
TCELL28:IMUX.IMUX.8.DELAYBITSLICE24.TX_D7
TCELL28:IMUX.IMUX.9.DELAYBITSLICE24.TX_CNTVALUEIN0
TCELL28:IMUX.IMUX.10.DELAYBITSLICE24.TX_CNTVALUEIN1
TCELL28:IMUX.IMUX.11.DELAYBITSLICE24.TX_CNTVALUEIN2
TCELL28:IMUX.IMUX.12.DELAYBITSLICE24.TX_CNTVALUEIN3
TCELL28:IMUX.IMUX.13.DELAYBITSLICE24.TX_CNTVALUEIN4
TCELL28:IMUX.IMUX.14.DELAYBITSLICE24.TX_CNTVALUEIN5
TCELL28:IMUX.IMUX.15.DELAYBITSLICE24.TX_CNTVALUEIN6
TCELL28:IMUX.IMUX.16.DELAYBITSLICE24.TX_D4
TCELL28:IMUX.IMUX.17.DELAYBUFCE_ROW_CMT0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.18.DELAYBUFCE_ROW_CMT1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.19.DELAYBUFCE_ROW_CMT2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.20.DELAYBUFCE_ROW_CMT3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.21.DELAYBUFCE_ROW_CMT4.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.22.DELAYBUFCE_ROW_CMT5.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.23.DELAYBUFCE_ROW_CMT6.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.24.DELAYBUFCE_ROW_CMT7.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.25.DELAYBUFCE_ROW_CMT8.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.26.DELAYBUFCE_ROW_CMT9.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.27.DELAYBUFCE_ROW_CMT10.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.28.DELAYBUFCE_ROW_CMT11.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.29.DELAYBUFCE_ROW_CMT12.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.30.DELAYBUFCE_ROW_CMT13.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.31.DELAYBUFCE_ROW_CMT14.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.32.DELAYBUFCE_ROW_CMT15.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.33.DELAYBUFCE_ROW_CMT16.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.34.DELAYBUFCE_ROW_CMT17.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.35.DELAYBUFCE_ROW_CMT18.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.36.DELAYBUFCE_ROW_CMT19.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.37.DELAYBUFCE_ROW_CMT20.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.38.DELAYBUFCE_ROW_CMT21.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.39.DELAYBUFCE_ROW_CMT22.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.40.DELAYBUFCE_ROW_CMT23.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.41.DELAYBUFGCE_DIV0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.42.DELAYBUFGCE_DIV1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.43.DELAYBUFGCE_DIV2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.44.DELAYBUFGCE_DIV3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.45.DELAYBUFGCTRL0.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.46.DELAYBUFGCTRL1.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.47.DELAYBUFGCTRL2.SEL1_PRE_OPTINV
TCELL29:OUT.4.TMINBITSLICE24.PHY2CLB_FIFO_EMPTY
TCELL29:OUT.5.TMINBITSLICE24.RX_Q0
TCELL29:OUT.6.TMINBITSLICE24.RX_Q1
TCELL29:OUT.7.TMINBITSLICE24.RX_Q2
TCELL29:OUT.8.TMINBITSLICE24.RX_Q3
TCELL29:OUT.9.TMINBITSLICE24.RX_Q4
TCELL29:OUT.10.TMINBITSLICE24.RX_Q5
TCELL29:OUT.11.TMINBITSLICE24.RX_Q6
TCELL29:OUT.12.TMINBITSLICE24.RX_Q7
TCELL29:OUT.13.TMINBITSLICE24.TX_CNTVALUEOUT0
TCELL29:OUT.14.TMINBITSLICE24.TX_CNTVALUEOUT1
TCELL29:OUT.15.TMINBITSLICE24.TX_CNTVALUEOUT2
TCELL29:OUT.16.TMINBITSLICE24.TX_CNTVALUEOUT3
TCELL29:OUT.17.TMINBITSLICE24.TX_CNTVALUEOUT4
TCELL29:OUT.18.TMINBITSLICE24.TX_CNTVALUEOUT5
TCELL29:OUT.19.TMINBITSLICE24.TX_CNTVALUEOUT6
TCELL29:OUT.20.TMINBITSLICE24.TX_CNTVALUEOUT7
TCELL29:OUT.21.TMINBITSLICE24.TX_CNTVALUEOUT8
TCELL29:OUT.23.TMINBITSLICE24.RX_CNTVALUEOUT0
TCELL29:OUT.24.TMINBITSLICE24.RX_CNTVALUEOUT1
TCELL29:OUT.25.TMINBITSLICE24.RX_CNTVALUEOUT2
TCELL29:OUT.26.TMINBITSLICE24.RX_CNTVALUEOUT3
TCELL29:OUT.27.TMINBITSLICE24.RX_CNTVALUEOUT4
TCELL29:OUT.28.TMINBITSLICE24.RX_CNTVALUEOUT5
TCELL29:OUT.29.TMINBITSLICE24.RX_CNTVALUEOUT6
TCELL29:OUT.30.TMINBITSLICE24.RX_CNTVALUEOUT7
TCELL29:OUT.31.TMINBITSLICE24.RX_CNTVALUEOUT8
TCELL29:IMUX.CTRL.2XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK10
TCELL29:IMUX.CTRL.3XIPHY_FEEDTHROUGH1.TXBIT_RST_B11
TCELL29:IMUX.CTRL.4XIPHY_FEEDTHROUGH1.RXBIT_RST_B11
TCELL29:IMUX.CTRL.5XIPHY_FEEDTHROUGH1.ODELAY_RST_B11
TCELL29:IMUX.CTRL.6XIPHY_FEEDTHROUGH1.IDELAY_RST_B11
TCELL29:IMUX.CTRL.7XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK11
TCELL29:IMUX.BYP.6BITSLICE23.DYN_DCI_OUT_INT
TCELL29:IMUX.BYP.7BITSLICE24.TX_LD
TCELL29:IMUX.BYP.8BITSLICE24.TX_INC
TCELL29:IMUX.BYP.9BITSLICE24.TX_EN_VTC
TCELL29:IMUX.BYP.10BITSLICE24.TX_CE_ODELAY
TCELL29:IMUX.BYP.11BITSLICE24.RX_LD
TCELL29:IMUX.BYP.12BITSLICE24.RX_INC
TCELL29:IMUX.BYP.13BITSLICE24.RX_EN_VTC
TCELL29:IMUX.BYP.14BITSLICE24.RX_CE_IDELAY
TCELL29:IMUX.BYP.15BITSLICE24.DYN_DCI_OUT_INT
TCELL29:IMUX.IMUX.0.DELAYBUFGCE_DIV1.RST_PRE_OPTINV
TCELL29:IMUX.IMUX.6.DELAYBITSLICE24.TX_CNTVALUEIN8
TCELL29:IMUX.IMUX.7.DELAYBITSLICE24.RX_CNTVALUEIN0
TCELL29:IMUX.IMUX.8.DELAYBITSLICE24.RX_CNTVALUEIN1
TCELL29:IMUX.IMUX.9.DELAYBITSLICE24.RX_CNTVALUEIN2
TCELL29:IMUX.IMUX.10.DELAYBITSLICE24.RX_CNTVALUEIN3
TCELL29:IMUX.IMUX.11.DELAYBITSLICE24.RX_CNTVALUEIN4
TCELL29:IMUX.IMUX.12.DELAYBITSLICE24.RX_CNTVALUEIN5
TCELL29:IMUX.IMUX.13.DELAYBITSLICE24.RX_CNTVALUEIN6
TCELL29:IMUX.IMUX.14.DELAYBITSLICE24.RX_CNTVALUEIN7
TCELL29:IMUX.IMUX.15.DELAYBITSLICE24.RX_CNTVALUEIN8
TCELL29:IMUX.IMUX.16.DELAYBITSLICE24.TX_CNTVALUEIN7
TCELL29:IMUX.IMUX.17.DELAYBUFGCTRL3.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.18.DELAYBUFGCTRL4.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.19.DELAYBUFGCTRL5.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.20.DELAYBUFGCTRL6.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.21.DELAYBUFGCTRL7.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.22.DELAYBUFGCTRL0.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.23.DELAYBUFGCTRL1.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.24.DELAYBUFGCTRL2.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.25.DELAYBUFGCTRL3.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.26.DELAYBUFGCTRL4.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.27.DELAYBUFGCTRL5.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.28.DELAYBUFGCTRL6.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.29.DELAYBUFGCTRL7.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.30.DELAYBUFGCTRL0.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.31.DELAYBUFGCTRL1.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.32.DELAYBUFGCTRL2.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.33.DELAYBUFGCTRL3.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.34.DELAYBUFGCTRL4.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.35.DELAYBUFGCTRL5.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.36.DELAYBUFGCTRL6.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.37.DELAYBUFGCTRL7.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.38.DELAYBUFGCTRL0.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.39.DELAYBUFGCTRL1.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.40.DELAYBUFGCTRL2.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.41.DELAYBUFGCTRL3.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.42.DELAYBUFGCTRL4.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.43.DELAYBUFGCTRL5.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.44.DELAYBUFGCTRL6.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.45.DELAYBUFGCTRL7.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.46.DELAYBUFGCTRL0.CE1_PRE_OPTINV
TCELL29:IMUX.IMUX.47.DELAYBUFGCTRL1.CE1_PRE_OPTINV
TCELL30:OUT.4.TMINBITSLICE26.PHY2CLB_FIFO_EMPTY
TCELL30:OUT.5.TMINBITSLICE26.RX_Q0
TCELL30:OUT.6.TMINBITSLICE26.RX_Q1
TCELL30:OUT.7.TMINBITSLICE26.RX_Q2
TCELL30:OUT.8.TMINBITSLICE26.RX_Q3
TCELL30:OUT.9.TMINBITSLICE26.RX_Q4
TCELL30:OUT.10.TMINBITSLICE26.RX_Q5
TCELL30:OUT.11.TMINBITSLICE26.RX_Q6
TCELL30:OUT.12.TMINBITSLICE26.RX_Q7
TCELL30:OUT.13.TMINBITSLICE26.TX_CNTVALUEOUT0
TCELL30:OUT.14.TMINBITSLICE26.TX_CNTVALUEOUT1
TCELL30:OUT.15.TMINBITSLICE26.TX_CNTVALUEOUT2
TCELL30:OUT.16.TMINBITSLICE26.TX_CNTVALUEOUT3
TCELL30:OUT.17.TMINBITSLICE26.TX_CNTVALUEOUT4
TCELL30:OUT.18.TMINBITSLICE26.TX_CNTVALUEOUT5
TCELL30:OUT.19.TMINBITSLICE26.TX_CNTVALUEOUT6
TCELL30:OUT.20.TMINBITSLICE26.TX_CNTVALUEOUT7
TCELL30:OUT.21.TMINBITSLICE26.TX_CNTVALUEOUT8
TCELL30:OUT.22.TMINBITSLICE26.TX_T_OUT
TCELL30:OUT.23.TMINBITSLICE26.RX_CNTVALUEOUT0
TCELL30:OUT.24.TMINBITSLICE26.RX_CNTVALUEOUT1
TCELL30:OUT.25.TMINBITSLICE26.RX_CNTVALUEOUT2
TCELL30:OUT.26.TMINBITSLICE26.RX_CNTVALUEOUT3
TCELL30:OUT.27.TMINBITSLICE26.RX_CNTVALUEOUT4
TCELL30:OUT.28.TMINBITSLICE26.RX_CNTVALUEOUT5
TCELL30:OUT.29.TMINBITSLICE26.RX_CNTVALUEOUT6
TCELL30:OUT.30.TMINBITSLICE26.RX_CNTVALUEOUT7
TCELL30:OUT.31.TMINBITSLICE26.RX_CNTVALUEOUT8
TCELL30:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.TXBIT_TRI_RST_B0
TCELL30:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.TXBIT_RST_B0
TCELL30:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.RXBIT_RST_B0
TCELL30:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.ODELAY_RST_B0
TCELL30:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.IDELAY_RST_B0
TCELL30:IMUX.BYP.6BITSLICE_T4.EN_VTC
TCELL30:IMUX.BYP.7BITSLICE26.TX_LD
TCELL30:IMUX.BYP.8BITSLICE26.TX_INC
TCELL30:IMUX.BYP.9BITSLICE26.TX_EN_VTC
TCELL30:IMUX.BYP.10BITSLICE26.TX_CE_ODELAY
TCELL30:IMUX.BYP.11BITSLICE26.RX_LD
TCELL30:IMUX.BYP.12BITSLICE26.RX_INC
TCELL30:IMUX.BYP.13BITSLICE26.RX_EN_VTC
TCELL30:IMUX.BYP.14BITSLICE26.RX_CE_IDELAY
TCELL30:IMUX.BYP.15BITSLICE26.DYN_DCI_OUT_INT
TCELL30:IMUX.IMUX.0.DELAYBUFGCE_DIV2.RST_PRE_OPTINV
TCELL30:IMUX.IMUX.6.DELAYBITSLICE26.TX_CE_OFD
TCELL30:IMUX.IMUX.7.DELAYBITSLICE26.RX_CE_IFD
TCELL30:IMUX.IMUX.8.DELAYBITSLICE26.RX_DATAIN1
TCELL30:IMUX.IMUX.9.DELAYBITSLICE26.CLB2PHY_FIFO_RDEN
TCELL30:IMUX.IMUX.10.DELAYBITSLICE26.TX_D7
TCELL30:IMUX.IMUX.11.DELAYBITSLICE26.TX_D6
TCELL30:IMUX.IMUX.12.DELAYBITSLICE26.TX_D5
TCELL30:IMUX.IMUX.13.DELAYBITSLICE26.TX_D4
TCELL30:IMUX.IMUX.14.DELAYBITSLICE26.TX_D3
TCELL30:IMUX.IMUX.15.DELAYBITSLICE26.TX_D2
TCELL30:IMUX.IMUX.16.DELAYBITSLICE26.TX_T
TCELL30:IMUX.IMUX.17.DELAYBUFGCTRL2.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.18.DELAYBUFGCTRL3.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.19.DELAYBUFGCTRL4.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.20.DELAYBUFGCTRL5.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.21.DELAYBUFGCTRL6.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.22.DELAYBUFGCTRL7.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.23.DELAYBUFGCTRL0.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.24.DELAYBUFGCTRL1.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.25.DELAYBUFGCTRL2.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.26.DELAYBUFGCTRL3.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.27.DELAYBUFGCTRL4.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.28.DELAYBUFGCTRL5.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.29.DELAYBUFGCTRL6.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.30.DELAYBUFGCTRL7.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.31.DELAYBUFGCE0.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.32.DELAYBUFGCE1.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.33.DELAYBUFGCE2.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.34.DELAYBUFGCE3.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.35.DELAYBUFGCE4.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.36.DELAYBUFGCE5.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.37.DELAYBUFGCE6.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.38.DELAYBUFGCE7.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.39.DELAYBUFGCE8.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.40.DELAYBUFGCE9.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.41.DELAYBUFGCE10.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.42.DELAYBUFGCE11.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.43.DELAYBUFGCE12.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.44.DELAYBUFGCE13.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.45.DELAYBUFGCE14.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.46.DELAYBUFGCE15.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.47.DELAYBUFGCE16.CE_PRE_OPTINV
TCELL30:RCLK.IMUX.0BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.1BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.2BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2
TCELL30:RCLK.IMUX.6BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.7BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.8BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2
TCELL31:OUT.4.TMINBITSLICE27.PHY2CLB_FIFO_EMPTY
TCELL31:OUT.5.TMINBITSLICE27.RX_Q0
TCELL31:OUT.6.TMINBITSLICE27.RX_Q1
TCELL31:OUT.7.TMINBITSLICE27.RX_Q2
TCELL31:OUT.8.TMINBITSLICE27.RX_Q3
TCELL31:OUT.9.TMINBITSLICE27.RX_Q4
TCELL31:OUT.10.TMINBITSLICE27.RX_Q5
TCELL31:OUT.11.TMINBITSLICE27.RX_Q6
TCELL31:OUT.12.TMINBITSLICE27.RX_Q7
TCELL31:OUT.13.TMINBITSLICE27.TX_CNTVALUEOUT0
TCELL31:OUT.14.TMINBITSLICE27.TX_CNTVALUEOUT1
TCELL31:OUT.15.TMINBITSLICE27.TX_CNTVALUEOUT2
TCELL31:OUT.16.TMINBITSLICE27.TX_CNTVALUEOUT3
TCELL31:OUT.17.TMINBITSLICE27.TX_CNTVALUEOUT4
TCELL31:OUT.18.TMINBITSLICE27.TX_CNTVALUEOUT5
TCELL31:OUT.19.TMINBITSLICE27.TX_CNTVALUEOUT6
TCELL31:OUT.20.TMINBITSLICE27.TX_CNTVALUEOUT7
TCELL31:OUT.21.TMINBITSLICE27.TX_CNTVALUEOUT8
TCELL31:OUT.22.TMINBITSLICE27.TX_T_OUT
TCELL31:OUT.23.TMINBITSLICE27.RX_CNTVALUEOUT0
TCELL31:OUT.24.TMINBITSLICE27.RX_CNTVALUEOUT1
TCELL31:OUT.25.TMINBITSLICE27.RX_CNTVALUEOUT2
TCELL31:OUT.26.TMINBITSLICE27.RX_CNTVALUEOUT3
TCELL31:OUT.27.TMINBITSLICE27.RX_CNTVALUEOUT4
TCELL31:OUT.28.TMINBITSLICE27.RX_CNTVALUEOUT5
TCELL31:OUT.29.TMINBITSLICE27.RX_CNTVALUEOUT6
TCELL31:OUT.30.TMINBITSLICE27.RX_CNTVALUEOUT7
TCELL31:OUT.31.TMINBITSLICE27.RX_CNTVALUEOUT8
TCELL31:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK0
TCELL31:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.TXBIT_TRI_RST_B1
TCELL31:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.TXBIT_RST_B1
TCELL31:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.RXBIT_RST_B1
TCELL31:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.ODELAY_RST_B1
TCELL31:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.IDELAY_RST_B1
TCELL31:IMUX.BYP.6BITSLICE_T5.EN_VTC
TCELL31:IMUX.BYP.7BITSLICE27.TX_LD
TCELL31:IMUX.BYP.8BITSLICE27.TX_INC
TCELL31:IMUX.BYP.9BITSLICE27.TX_EN_VTC
TCELL31:IMUX.BYP.10BITSLICE27.TX_CE_ODELAY
TCELL31:IMUX.BYP.11BITSLICE27.RX_LD
TCELL31:IMUX.BYP.12BITSLICE27.RX_INC
TCELL31:IMUX.BYP.13BITSLICE27.RX_EN_VTC
TCELL31:IMUX.BYP.14BITSLICE27.RX_CE_IDELAY
TCELL31:IMUX.BYP.15BITSLICE27.DYN_DCI_OUT_INT
TCELL31:IMUX.IMUX.0.DELAYBUFGCE_DIV3.RST_PRE_OPTINV
TCELL31:IMUX.IMUX.6.DELAYBITSLICE26.TX_D1
TCELL31:IMUX.IMUX.7.DELAYBITSLICE26.TX_CNTVALUEIN0
TCELL31:IMUX.IMUX.8.DELAYBITSLICE26.TX_CNTVALUEIN1
TCELL31:IMUX.IMUX.9.DELAYBITSLICE26.TX_CNTVALUEIN2
TCELL31:IMUX.IMUX.10.DELAYBITSLICE26.TX_CNTVALUEIN3
TCELL31:IMUX.IMUX.11.DELAYBITSLICE26.TX_CNTVALUEIN4
TCELL31:IMUX.IMUX.12.DELAYBITSLICE26.TX_CNTVALUEIN5
TCELL31:IMUX.IMUX.13.DELAYBITSLICE26.TX_CNTVALUEIN6
TCELL31:IMUX.IMUX.14.DELAYBITSLICE26.TX_CNTVALUEIN7
TCELL31:IMUX.IMUX.15.DELAYBITSLICE26.TX_CNTVALUEIN8
TCELL31:IMUX.IMUX.16.DELAYBITSLICE26.TX_D0
TCELL31:IMUX.IMUX.17.DELAYBUFGCE17.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.18.DELAYBUFGCE18.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.19.DELAYBUFGCE19.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.20.DELAYBUFGCE20.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.21.DELAYBUFGCE21.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.22.DELAYBUFGCE22.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.23.DELAYBUFGCE23.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.24.DELAYBUFGCE0.CLK_IN_CKINT
TCELL31:IMUX.IMUX.25.DELAYBUFGCE1.CLK_IN_CKINT
TCELL31:IMUX.IMUX.26.DELAYBUFGCE2.CLK_IN_CKINT
TCELL31:IMUX.IMUX.27.DELAYBUFGCE3.CLK_IN_CKINT
TCELL31:IMUX.IMUX.28.DELAYBUFGCE4.CLK_IN_CKINT
TCELL31:IMUX.IMUX.29.DELAYBUFGCE5.CLK_IN_CKINT
TCELL31:IMUX.IMUX.30.DELAYBUFGCE6.CLK_IN_CKINT
TCELL31:IMUX.IMUX.31.DELAYBUFGCE7.CLK_IN_CKINT
TCELL31:IMUX.IMUX.32.DELAYBUFGCE8.CLK_IN_CKINT
TCELL31:IMUX.IMUX.33.DELAYBUFGCE9.CLK_IN_CKINT
TCELL31:IMUX.IMUX.34.DELAYBUFGCE10.CLK_IN_CKINT
TCELL31:IMUX.IMUX.35.DELAYBUFGCE11.CLK_IN_CKINT
TCELL31:IMUX.IMUX.36.DELAYBUFGCE12.CLK_IN_CKINT
TCELL31:IMUX.IMUX.37.DELAYBUFGCE13.CLK_IN_CKINT
TCELL31:IMUX.IMUX.38.DELAYBUFGCE14.CLK_IN_CKINT
TCELL31:IMUX.IMUX.39.DELAYBUFGCE15.CLK_IN_CKINT
TCELL31:IMUX.IMUX.40.DELAYBUFGCE16.CLK_IN_CKINT
TCELL31:IMUX.IMUX.41.DELAYBUFGCE17.CLK_IN_CKINT
TCELL31:IMUX.IMUX.42.DELAYBUFGCE18.CLK_IN_CKINT
TCELL31:IMUX.IMUX.43.DELAYBUFGCE19.CLK_IN_CKINT
TCELL31:IMUX.IMUX.44.DELAYBUFGCE20.CLK_IN_CKINT
TCELL31:IMUX.IMUX.45.DELAYBUFGCE21.CLK_IN_CKINT
TCELL31:IMUX.IMUX.46.DELAYBUFGCE22.CLK_IN_CKINT
TCELL31:IMUX.IMUX.47.DELAYBUFGCE23.CLK_IN_CKINT
TCELL32:OUT.4.TMINBITSLICE28.PHY2CLB_FIFO_EMPTY
TCELL32:OUT.5.TMINBITSLICE28.RX_Q0
TCELL32:OUT.6.TMINBITSLICE28.RX_Q1
TCELL32:OUT.7.TMINBITSLICE28.RX_Q2
TCELL32:OUT.8.TMINBITSLICE28.RX_Q3
TCELL32:OUT.9.TMINBITSLICE28.RX_Q4
TCELL32:OUT.10.TMINBITSLICE28.RX_Q5
TCELL32:OUT.11.TMINBITSLICE28.RX_Q6
TCELL32:OUT.12.TMINBITSLICE28.RX_Q7
TCELL32:OUT.13.TMINBITSLICE28.TX_CNTVALUEOUT0
TCELL32:OUT.14.TMINBITSLICE28.TX_CNTVALUEOUT1
TCELL32:OUT.15.TMINBITSLICE28.TX_CNTVALUEOUT2
TCELL32:OUT.16.TMINBITSLICE28.TX_CNTVALUEOUT3
TCELL32:OUT.17.TMINBITSLICE28.TX_CNTVALUEOUT4
TCELL32:OUT.18.TMINBITSLICE28.TX_CNTVALUEOUT5
TCELL32:OUT.19.TMINBITSLICE28.TX_CNTVALUEOUT6
TCELL32:OUT.20.TMINBITSLICE28.TX_CNTVALUEOUT7
TCELL32:OUT.21.TMINBITSLICE28.TX_CNTVALUEOUT8
TCELL32:OUT.22.TMINBITSLICE28.TX_T_OUT
TCELL32:OUT.23.TMINBITSLICE28.RX_CNTVALUEOUT0
TCELL32:OUT.24.TMINBITSLICE28.RX_CNTVALUEOUT1
TCELL32:OUT.25.TMINBITSLICE28.RX_CNTVALUEOUT2
TCELL32:OUT.26.TMINBITSLICE28.RX_CNTVALUEOUT3
TCELL32:OUT.27.TMINBITSLICE28.RX_CNTVALUEOUT4
TCELL32:OUT.28.TMINBITSLICE28.RX_CNTVALUEOUT5
TCELL32:OUT.29.TMINBITSLICE28.RX_CNTVALUEOUT6
TCELL32:OUT.30.TMINBITSLICE28.RX_CNTVALUEOUT7
TCELL32:OUT.31.TMINBITSLICE28.RX_CNTVALUEOUT8
TCELL32:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK1
TCELL32:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.TXBIT_RST_B2
TCELL32:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.RXBIT_RST_B2
TCELL32:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.ODELAY_RST_B2
TCELL32:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.IDELAY_RST_B2
TCELL32:IMUX.BYP.6BITSLICE28.TX_LD
TCELL32:IMUX.BYP.7BITSLICE28.TX_INC
TCELL32:IMUX.BYP.8BITSLICE28.TX_EN_VTC
TCELL32:IMUX.BYP.9BITSLICE28.TX_CE_ODELAY
TCELL32:IMUX.BYP.10BITSLICE28.RX_LD
TCELL32:IMUX.BYP.11BITSLICE28.RX_INC
TCELL32:IMUX.BYP.12BITSLICE28.RX_EN_VTC
TCELL32:IMUX.BYP.13BITSLICE28.RX_CE_IDELAY
TCELL32:IMUX.BYP.14BITSLICE28.DYN_DCI_OUT_INT
TCELL32:IMUX.BYP.15BITSLICE_T4.CE_OFD
TCELL32:IMUX.IMUX.6.DELAYBITSLICE27.TX_D1
TCELL32:IMUX.IMUX.7.DELAYBITSLICE27.TX_D3
TCELL32:IMUX.IMUX.8.DELAYBITSLICE27.TX_D7
TCELL32:IMUX.IMUX.9.DELAYBITSLICE27.TX_CNTVALUEIN1
TCELL32:IMUX.IMUX.10.DELAYBITSLICE27.TX_CNTVALUEIN5
TCELL32:IMUX.IMUX.11.DELAYBITSLICE27.TX_CNTVALUEIN7
TCELL32:IMUX.IMUX.12.DELAYBITSLICE27.RX_CNTVALUEIN2
TCELL32:IMUX.IMUX.13.DELAYBITSLICE27.RX_CNTVALUEIN4
TCELL32:IMUX.IMUX.14.DELAYBITSLICE27.RX_CNTVALUEIN8
TCELL32:IMUX.IMUX.15.DELAYBITSLICE28.TX_CE_OFD
TCELL32:IMUX.IMUX.16.DELAYBITSLICE26.RX_CNTVALUEIN0
TCELL32:IMUX.IMUX.17.DELAYBITSLICE26.RX_CNTVALUEIN1
TCELL32:IMUX.IMUX.18.DELAYBITSLICE26.RX_CNTVALUEIN2
TCELL32:IMUX.IMUX.19.DELAYBITSLICE26.RX_CNTVALUEIN3
TCELL32:IMUX.IMUX.20.DELAYBITSLICE26.RX_CNTVALUEIN4
TCELL32:IMUX.IMUX.21.DELAYBITSLICE26.RX_CNTVALUEIN5
TCELL32:IMUX.IMUX.22.DELAYBITSLICE26.RX_CNTVALUEIN6
TCELL32:IMUX.IMUX.23.DELAYBITSLICE26.RX_CNTVALUEIN7
TCELL32:IMUX.IMUX.24.DELAYBITSLICE26.RX_CNTVALUEIN8
TCELL32:IMUX.IMUX.25.DELAYBITSLICE27.TX_T
TCELL32:IMUX.IMUX.26.DELAYBITSLICE27.TX_CE_OFD
TCELL32:IMUX.IMUX.27.DELAYBITSLICE27.RX_CE_IFD
TCELL32:IMUX.IMUX.28.DELAYBITSLICE27.RX_DATAIN1
TCELL32:IMUX.IMUX.29.DELAYBITSLICE27.CLB2PHY_FIFO_RDEN
TCELL32:IMUX.IMUX.30.DELAYBITSLICE27.TX_D0
TCELL32:IMUX.IMUX.31.DELAYBITSLICE27.TX_D2
TCELL32:IMUX.IMUX.32.DELAYBITSLICE27.TX_D4
TCELL32:IMUX.IMUX.33.DELAYBITSLICE27.TX_D5
TCELL32:IMUX.IMUX.34.DELAYBITSLICE27.TX_D6
TCELL32:IMUX.IMUX.35.DELAYBITSLICE27.TX_CNTVALUEIN0
TCELL32:IMUX.IMUX.36.DELAYBITSLICE27.TX_CNTVALUEIN2
TCELL32:IMUX.IMUX.37.DELAYBITSLICE27.TX_CNTVALUEIN3
TCELL32:IMUX.IMUX.38.DELAYBITSLICE27.TX_CNTVALUEIN4
TCELL32:IMUX.IMUX.39.DELAYBITSLICE27.TX_CNTVALUEIN6
TCELL32:IMUX.IMUX.40.DELAYBITSLICE27.TX_CNTVALUEIN8
TCELL32:IMUX.IMUX.41.DELAYBITSLICE27.RX_CNTVALUEIN0
TCELL32:IMUX.IMUX.42.DELAYBITSLICE27.RX_CNTVALUEIN1
TCELL32:IMUX.IMUX.43.DELAYBITSLICE27.RX_CNTVALUEIN3
TCELL32:IMUX.IMUX.44.DELAYBITSLICE27.RX_CNTVALUEIN5
TCELL32:IMUX.IMUX.45.DELAYBITSLICE27.RX_CNTVALUEIN6
TCELL32:IMUX.IMUX.46.DELAYBITSLICE27.RX_CNTVALUEIN7
TCELL32:IMUX.IMUX.47.DELAYBITSLICE28.TX_T
TCELL33:OUT.4.TMINBITSLICE_T4.CNTVALUEOUT0
TCELL33:OUT.5.TMINBITSLICE_T4.CNTVALUEOUT1
TCELL33:OUT.6.TMINBITSLICE_T4.CNTVALUEOUT2
TCELL33:OUT.7.TMINBITSLICE_T4.CNTVALUEOUT3
TCELL33:OUT.8.TMINBITSLICE_T4.CNTVALUEOUT4
TCELL33:OUT.9.TMINBITSLICE_T4.CNTVALUEOUT5
TCELL33:OUT.10.TMINBITSLICE_T4.CNTVALUEOUT6
TCELL33:OUT.11.TMINBITSLICE_T4.CNTVALUEOUT7
TCELL33:OUT.12.TMINBITSLICE_T4.CNTVALUEOUT8
TCELL33:OUT.13.TMINBITSLICE29.TX_T_OUT
TCELL33:OUT.14.TMINBITSLICE_CONTROL4.PHY2CLB_PHY_RDY
TCELL33:OUT.15.TMINBITSLICE_CONTROL4.MASTER_PD_OUT
TCELL33:OUT.16.TMINBITSLICE_CONTROL4.PHY2CLB_FIXDLY_RDY
TCELL33:OUT.17.TMINBITSLICE_CONTROL4.CTRL_DLY_TEST_OUT
TCELL33:OUT.18.TMINBITSLICE29.PHY2CLB_FIFO_EMPTY
TCELL33:OUT.19.TMINBITSLICE29.RX_Q0
TCELL33:OUT.20.TMINBITSLICE29.RX_Q1
TCELL33:OUT.21.TMINBITSLICE29.RX_Q2
TCELL33:OUT.22.TMINBITSLICE29.RX_Q3
TCELL33:OUT.23.TMINBITSLICE29.RX_Q4
TCELL33:OUT.24.TMINBITSLICE29.RX_Q5
TCELL33:OUT.25.TMINBITSLICE29.RX_Q6
TCELL33:OUT.26.TMINBITSLICE29.RX_Q7
TCELL33:OUT.27.TMINBITSLICE29.TX_CNTVALUEOUT0
TCELL33:OUT.28.TMINBITSLICE29.TX_CNTVALUEOUT1
TCELL33:OUT.29.TMINBITSLICE29.TX_CNTVALUEOUT2
TCELL33:OUT.30.TMINBITSLICE29.TX_CNTVALUEOUT3
TCELL33:OUT.31.TMINBITSLICE29.TX_CNTVALUEOUT4
TCELL33:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK2
TCELL33:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.TRISTATE_ODELAY_RST_B0
TCELL33:IMUX.CTRL.5BITSLICE_CONTROL4.REFCLK
TCELL33:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.CTRL_RST_B_LOW
TCELL33:IMUX.CTRL.7BITSLICE_CONTROL4.RIU_CLK, XIPHY_FEEDTHROUGH2.CLB2PHY_CTRL_CLK_LOW
TCELL33:IMUX.BYP.6BITSLICE_T4.LD
TCELL33:IMUX.BYP.7BITSLICE_T4.INC
TCELL33:IMUX.BYP.8BITSLICE_T4.CE_ODELAY
TCELL33:IMUX.BYP.9BITSLICE_CONTROL4.EN_VTC
TCELL33:IMUX.BYP.10BITSLICE_CONTROL4.CTRL_DLY_TEST_IN
TCELL33:IMUX.BYP.12BITSLICE29.TX_LD
TCELL33:IMUX.BYP.13BITSLICE29.TX_INC
TCELL33:IMUX.BYP.14BITSLICE29.TX_EN_VTC
TCELL33:IMUX.BYP.15BITSLICE29.TX_CE_ODELAY
TCELL33:IMUX.IMUX.6.DELAYBITSLICE28.TX_CNTVALUEIN3
TCELL33:IMUX.IMUX.7.DELAYBITSLICE28.TX_CNTVALUEIN5
TCELL33:IMUX.IMUX.8.DELAYBITSLICE28.RX_CNTVALUEIN0
TCELL33:IMUX.IMUX.9.DELAYBITSLICE28.RX_CNTVALUEIN2
TCELL33:IMUX.IMUX.10.DELAYBITSLICE28.RX_CNTVALUEIN6
TCELL33:IMUX.IMUX.11.DELAYBITSLICE28.RX_CNTVALUEIN8
TCELL33:IMUX.IMUX.12.DELAYBITSLICE_T4.CNTVALUEIN3
TCELL33:IMUX.IMUX.13.DELAYBITSLICE_T4.CNTVALUEIN5
TCELL33:IMUX.IMUX.14.DELAYBITSLICE_CONTROL4.CLB2RIU_NIBBLE_SEL
TCELL33:IMUX.IMUX.15.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS1_1
TCELL33:IMUX.IMUX.16.DELAYBITSLICE28.RX_CE_IFD
TCELL33:IMUX.IMUX.17.DELAYBITSLICE28.RX_DATAIN1
TCELL33:IMUX.IMUX.18.DELAYBITSLICE28.CLB2PHY_FIFO_RDEN
TCELL33:IMUX.IMUX.20.DELAYBITSLICE28.TX_D0
TCELL33:IMUX.IMUX.21.DELAYBITSLICE28.TX_D1
TCELL33:IMUX.IMUX.22.DELAYBITSLICE28.TX_D2
TCELL33:IMUX.IMUX.23.DELAYBITSLICE28.TX_D3
TCELL33:IMUX.IMUX.24.DELAYBITSLICE28.TX_D4
TCELL33:IMUX.IMUX.25.DELAYBITSLICE28.TX_D5
TCELL33:IMUX.IMUX.26.DELAYBITSLICE28.TX_D6
TCELL33:IMUX.IMUX.27.DELAYBITSLICE28.TX_D7
TCELL33:IMUX.IMUX.28.DELAYBITSLICE28.TX_CNTVALUEIN0
TCELL33:IMUX.IMUX.29.DELAYBITSLICE28.TX_CNTVALUEIN1
TCELL33:IMUX.IMUX.30.DELAYBITSLICE28.TX_CNTVALUEIN2
TCELL33:IMUX.IMUX.31.DELAYBITSLICE28.TX_CNTVALUEIN4
TCELL33:IMUX.IMUX.32.DELAYBITSLICE28.TX_CNTVALUEIN6
TCELL33:IMUX.IMUX.33.DELAYBITSLICE28.TX_CNTVALUEIN7
TCELL33:IMUX.IMUX.34.DELAYBITSLICE28.TX_CNTVALUEIN8
TCELL33:IMUX.IMUX.35.DELAYBITSLICE28.RX_CNTVALUEIN1
TCELL33:IMUX.IMUX.36.DELAYBITSLICE28.RX_CNTVALUEIN3
TCELL33:IMUX.IMUX.37.DELAYBITSLICE28.RX_CNTVALUEIN4
TCELL33:IMUX.IMUX.38.DELAYBITSLICE28.RX_CNTVALUEIN5
TCELL33:IMUX.IMUX.39.DELAYBITSLICE28.RX_CNTVALUEIN7
TCELL33:IMUX.IMUX.40.DELAYBITSLICE_T4.CNTVALUEIN0
TCELL33:IMUX.IMUX.41.DELAYBITSLICE_T4.CNTVALUEIN1
TCELL33:IMUX.IMUX.42.DELAYBITSLICE_T4.CNTVALUEIN2
TCELL33:IMUX.IMUX.43.DELAYBITSLICE_T4.CNTVALUEIN4
TCELL33:IMUX.IMUX.44.DELAYBITSLICE_T4.CNTVALUEIN6
TCELL33:IMUX.IMUX.45.DELAYBITSLICE_T4.CNTVALUEIN7
TCELL33:IMUX.IMUX.46.DELAYBITSLICE_T4.CNTVALUEIN8
TCELL33:IMUX.IMUX.47.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS1_0
TCELL34:OUT.4.TMINBITSLICE29.TX_CNTVALUEOUT5
TCELL34:OUT.5.TMINBITSLICE29.TX_CNTVALUEOUT6
TCELL34:OUT.6.TMINBITSLICE29.TX_CNTVALUEOUT7
TCELL34:OUT.7.TMINBITSLICE29.TX_CNTVALUEOUT8
TCELL34:OUT.8.TMINBITSLICE30.TX_T_OUT
TCELL34:OUT.9.TMINBITSLICE29.RX_CNTVALUEOUT0
TCELL34:OUT.10.TMINBITSLICE29.RX_CNTVALUEOUT1
TCELL34:OUT.11.TMINBITSLICE29.RX_CNTVALUEOUT2
TCELL34:OUT.12.TMINBITSLICE29.RX_CNTVALUEOUT3
TCELL34:OUT.13.TMINBITSLICE29.RX_CNTVALUEOUT4
TCELL34:OUT.14.TMINBITSLICE29.RX_CNTVALUEOUT5
TCELL34:OUT.15.TMINBITSLICE29.RX_CNTVALUEOUT6
TCELL34:OUT.16.TMINBITSLICE29.RX_CNTVALUEOUT7
TCELL34:OUT.17.TMINBITSLICE29.RX_CNTVALUEOUT8
TCELL34:OUT.18.TMINBITSLICE30.PHY2CLB_FIFO_EMPTY
TCELL34:OUT.19.TMINBITSLICE30.RX_Q0
TCELL34:OUT.20.TMINBITSLICE30.RX_Q1
TCELL34:OUT.21.TMINBITSLICE30.RX_Q2
TCELL34:OUT.22.TMINBITSLICE30.RX_Q3
TCELL34:OUT.23.TMINBITSLICE30.RX_Q4
TCELL34:OUT.24.TMINBITSLICE30.RX_Q5
TCELL34:OUT.25.TMINBITSLICE30.RX_Q6
TCELL34:OUT.26.TMINBITSLICE30.RX_Q7
TCELL34:OUT.27.TMINBITSLICE30.TX_CNTVALUEOUT0
TCELL34:OUT.28.TMINBITSLICE30.TX_CNTVALUEOUT1
TCELL34:OUT.29.TMINBITSLICE30.TX_CNTVALUEOUT2
TCELL34:OUT.30.TMINBITSLICE30.TX_CNTVALUEOUT3
TCELL34:OUT.31.TMINBITSLICE30.TX_CNTVALUEOUT4
TCELL34:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.TXBIT_RST_B3
TCELL34:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.RXBIT_RST_B3
TCELL34:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.ODELAY_RST_B3
TCELL34:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.IDELAY_RST_B3
TCELL34:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK3
TCELL34:IMUX.BYP.6BITSLICE29.RX_LD
TCELL34:IMUX.BYP.7BITSLICE29.RX_INC
TCELL34:IMUX.BYP.8BITSLICE29.RX_EN_VTC
TCELL34:IMUX.BYP.9BITSLICE29.RX_CE_IDELAY
TCELL34:IMUX.BYP.10BITSLICE29.DYN_DCI_OUT_INT
TCELL34:IMUX.BYP.11BITSLICE30.TX_LD
TCELL34:IMUX.BYP.12BITSLICE30.TX_INC
TCELL34:IMUX.BYP.13BITSLICE30.TX_EN_VTC
TCELL34:IMUX.BYP.14BITSLICE30.TX_CE_ODELAY
TCELL34:IMUX.BYP.15BITSLICE30.RX_LD
TCELL34:IMUX.IMUX.6.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS1_1
TCELL34:IMUX.IMUX.7.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS1_3
TCELL34:IMUX.IMUX.8.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS0_3
TCELL34:IMUX.IMUX.9.DELAYBITSLICE29.TX_CE_OFD
TCELL34:IMUX.IMUX.10.DELAYBITSLICE29.TX_D0
TCELL34:IMUX.IMUX.11.DELAYBITSLICE29.TX_D2
TCELL34:IMUX.IMUX.12.DELAYBITSLICE29.TX_D6
TCELL34:IMUX.IMUX.13.DELAYBITSLICE29.TX_D7
TCELL34:IMUX.IMUX.14.DELAYBITSLICE29.TX_CNTVALUEIN3
TCELL34:IMUX.IMUX.15.DELAYBITSLICE29.TX_CNTVALUEIN5
TCELL34:IMUX.IMUX.16.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS1_2
TCELL34:IMUX.IMUX.17.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS1_3
TCELL34:IMUX.IMUX.18.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS0_0
TCELL34:IMUX.IMUX.19.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS0_1
TCELL34:IMUX.IMUX.20.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS0_2
TCELL34:IMUX.IMUX.21.DELAYBITSLICE_CONTROL4.CLB2PHY_WRCS0_3
TCELL34:IMUX.IMUX.22.DELAYBITSLICE_CONTROL4.CLB2PHY_T_B0
TCELL34:IMUX.IMUX.23.DELAYBITSLICE_CONTROL4.CLB2PHY_T_B1
TCELL34:IMUX.IMUX.24.DELAYBITSLICE_CONTROL4.CLB2PHY_T_B2
TCELL34:IMUX.IMUX.25.DELAYBITSLICE_CONTROL4.CLB2PHY_T_B3
TCELL34:IMUX.IMUX.26.DELAYBITSLICE_CONTROL4.CLB2PHY_RDEN0
TCELL34:IMUX.IMUX.27.DELAYBITSLICE_CONTROL4.CLB2PHY_RDEN1
TCELL34:IMUX.IMUX.28.DELAYBITSLICE_CONTROL4.CLB2PHY_RDEN2
TCELL34:IMUX.IMUX.29.DELAYBITSLICE_CONTROL4.CLB2PHY_RDEN3
TCELL34:IMUX.IMUX.30.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS1_0
TCELL34:IMUX.IMUX.31.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS1_2
TCELL34:IMUX.IMUX.32.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS0_0
TCELL34:IMUX.IMUX.33.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS0_1
TCELL34:IMUX.IMUX.34.DELAYBITSLICE_CONTROL4.CLB2PHY_RDCS0_2
TCELL34:IMUX.IMUX.35.DELAYBITSLICE29.TX_T
TCELL34:IMUX.IMUX.36.DELAYBITSLICE29.RX_CE_IFD
TCELL34:IMUX.IMUX.37.DELAYBITSLICE29.RX_DATAIN1
TCELL34:IMUX.IMUX.38.DELAYBITSLICE29.CLB2PHY_FIFO_RDEN
TCELL34:IMUX.IMUX.39.DELAYBITSLICE29.TX_D1
TCELL34:IMUX.IMUX.40.DELAYBITSLICE29.TX_D3
TCELL34:IMUX.IMUX.41.DELAYBITSLICE29.TX_D4
TCELL34:IMUX.IMUX.42.DELAYBITSLICE29.TX_D5
TCELL34:IMUX.IMUX.44.DELAYBITSLICE29.TX_CNTVALUEIN0
TCELL34:IMUX.IMUX.45.DELAYBITSLICE29.TX_CNTVALUEIN1
TCELL34:IMUX.IMUX.46.DELAYBITSLICE29.TX_CNTVALUEIN2
TCELL34:IMUX.IMUX.47.DELAYBITSLICE29.TX_CNTVALUEIN4
TCELL35:OUT.4.TMINBITSLICE30.TX_CNTVALUEOUT5
TCELL35:OUT.5.TMINBITSLICE30.TX_CNTVALUEOUT6
TCELL35:OUT.6.TMINBITSLICE30.TX_CNTVALUEOUT7
TCELL35:OUT.7.TMINBITSLICE30.TX_CNTVALUEOUT8
TCELL35:OUT.8.TMINBITSLICE31.TX_T_OUT
TCELL35:OUT.9.TMINBITSLICE30.RX_CNTVALUEOUT0
TCELL35:OUT.10.TMINBITSLICE30.RX_CNTVALUEOUT1
TCELL35:OUT.11.TMINBITSLICE30.RX_CNTVALUEOUT2
TCELL35:OUT.12.TMINBITSLICE30.RX_CNTVALUEOUT3
TCELL35:OUT.13.TMINBITSLICE30.RX_CNTVALUEOUT4
TCELL35:OUT.14.TMINBITSLICE30.RX_CNTVALUEOUT5
TCELL35:OUT.15.TMINBITSLICE30.RX_CNTVALUEOUT6
TCELL35:OUT.16.TMINBITSLICE30.RX_CNTVALUEOUT7
TCELL35:OUT.17.TMINBITSLICE30.RX_CNTVALUEOUT8
TCELL35:OUT.18.TMINBITSLICE31.PHY2CLB_FIFO_EMPTY
TCELL35:OUT.19.TMINBITSLICE31.RX_Q0
TCELL35:OUT.20.TMINBITSLICE31.RX_Q1
TCELL35:OUT.21.TMINBITSLICE31.RX_Q2
TCELL35:OUT.22.TMINBITSLICE31.RX_Q3
TCELL35:OUT.23.TMINBITSLICE31.RX_Q4
TCELL35:OUT.24.TMINBITSLICE31.RX_Q5
TCELL35:OUT.25.TMINBITSLICE31.RX_Q6
TCELL35:OUT.26.TMINBITSLICE31.RX_Q7
TCELL35:OUT.27.TMINBITSLICE31.TX_CNTVALUEOUT0
TCELL35:OUT.28.TMINBITSLICE31.TX_CNTVALUEOUT1
TCELL35:OUT.29.TMINBITSLICE31.TX_CNTVALUEOUT2
TCELL35:OUT.30.TMINBITSLICE31.TX_CNTVALUEOUT3
TCELL35:OUT.31.TMINBITSLICE31.TX_CNTVALUEOUT4
TCELL35:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.TXBIT_RST_B4
TCELL35:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.RXBIT_RST_B4
TCELL35:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.ODELAY_RST_B4
TCELL35:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.IDELAY_RST_B4
TCELL35:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK4
TCELL35:IMUX.BYP.6BITSLICE30.RX_INC
TCELL35:IMUX.BYP.7BITSLICE30.RX_EN_VTC
TCELL35:IMUX.BYP.8BITSLICE30.RX_CE_IDELAY
TCELL35:IMUX.BYP.9BITSLICE30.DYN_DCI_OUT_INT
TCELL35:IMUX.BYP.10BITSLICE31.TX_LD
TCELL35:IMUX.BYP.11BITSLICE31.TX_INC
TCELL35:IMUX.BYP.12BITSLICE31.TX_EN_VTC
TCELL35:IMUX.BYP.13BITSLICE31.TX_CE_ODELAY
TCELL35:IMUX.BYP.14BITSLICE31.RX_LD
TCELL35:IMUX.BYP.15BITSLICE31.RX_INC
TCELL35:IMUX.IMUX.6.DELAYBITSLICE30.RX_DATAIN1
TCELL35:IMUX.IMUX.7.DELAYBITSLICE30.TX_D0
TCELL35:IMUX.IMUX.8.DELAYBITSLICE30.TX_D4
TCELL35:IMUX.IMUX.9.DELAYBITSLICE30.TX_D6
TCELL35:IMUX.IMUX.10.DELAYBITSLICE30.TX_CNTVALUEIN2
TCELL35:IMUX.IMUX.11.DELAYBITSLICE30.TX_CNTVALUEIN4
TCELL35:IMUX.IMUX.12.DELAYBITSLICE30.TX_CNTVALUEIN8
TCELL35:IMUX.IMUX.13.DELAYBITSLICE30.RX_CNTVALUEIN1
TCELL35:IMUX.IMUX.14.DELAYBITSLICE30.RX_CNTVALUEIN5
TCELL35:IMUX.IMUX.15.DELAYBITSLICE30.RX_CNTVALUEIN7
TCELL35:IMUX.IMUX.16.DELAYBITSLICE29.TX_CNTVALUEIN6
TCELL35:IMUX.IMUX.17.DELAYBITSLICE29.TX_CNTVALUEIN7
TCELL35:IMUX.IMUX.18.DELAYBITSLICE29.TX_CNTVALUEIN8
TCELL35:IMUX.IMUX.19.DELAYBITSLICE29.RX_CNTVALUEIN0
TCELL35:IMUX.IMUX.20.DELAYBITSLICE29.RX_CNTVALUEIN1
TCELL35:IMUX.IMUX.21.DELAYBITSLICE29.RX_CNTVALUEIN2
TCELL35:IMUX.IMUX.22.DELAYBITSLICE29.RX_CNTVALUEIN3
TCELL35:IMUX.IMUX.23.DELAYBITSLICE29.RX_CNTVALUEIN4
TCELL35:IMUX.IMUX.24.DELAYBITSLICE29.RX_CNTVALUEIN5
TCELL35:IMUX.IMUX.25.DELAYBITSLICE29.RX_CNTVALUEIN6
TCELL35:IMUX.IMUX.26.DELAYBITSLICE29.RX_CNTVALUEIN7
TCELL35:IMUX.IMUX.27.DELAYBITSLICE29.RX_CNTVALUEIN8
TCELL35:IMUX.IMUX.28.DELAYBITSLICE30.TX_T
TCELL35:IMUX.IMUX.29.DELAYBITSLICE30.TX_CE_OFD
TCELL35:IMUX.IMUX.30.DELAYBITSLICE30.RX_CE_IFD
TCELL35:IMUX.IMUX.31.DELAYBITSLICE30.CLB2PHY_FIFO_RDEN
TCELL35:IMUX.IMUX.32.DELAYBITSLICE30.TX_D1
TCELL35:IMUX.IMUX.33.DELAYBITSLICE30.TX_D2
TCELL35:IMUX.IMUX.34.DELAYBITSLICE30.TX_D3
TCELL35:IMUX.IMUX.35.DELAYBITSLICE30.TX_D5
TCELL35:IMUX.IMUX.36.DELAYBITSLICE30.TX_D7
TCELL35:IMUX.IMUX.37.DELAYBITSLICE30.TX_CNTVALUEIN0
TCELL35:IMUX.IMUX.38.DELAYBITSLICE30.TX_CNTVALUEIN1
TCELL35:IMUX.IMUX.39.DELAYBITSLICE30.TX_CNTVALUEIN3
TCELL35:IMUX.IMUX.40.DELAYBITSLICE30.TX_CNTVALUEIN5
TCELL35:IMUX.IMUX.41.DELAYBITSLICE30.TX_CNTVALUEIN6
TCELL35:IMUX.IMUX.42.DELAYBITSLICE30.TX_CNTVALUEIN7
TCELL35:IMUX.IMUX.43.DELAYBITSLICE30.RX_CNTVALUEIN0
TCELL35:IMUX.IMUX.44.DELAYBITSLICE30.RX_CNTVALUEIN2
TCELL35:IMUX.IMUX.45.DELAYBITSLICE30.RX_CNTVALUEIN3
TCELL35:IMUX.IMUX.46.DELAYBITSLICE30.RX_CNTVALUEIN4
TCELL35:IMUX.IMUX.47.DELAYBITSLICE30.RX_CNTVALUEIN6
TCELL36:OUT.4.TMINBITSLICE31.TX_CNTVALUEOUT5
TCELL36:OUT.5.TMINBITSLICE31.TX_CNTVALUEOUT6
TCELL36:OUT.6.TMINBITSLICE31.TX_CNTVALUEOUT7
TCELL36:OUT.7.TMINBITSLICE31.TX_CNTVALUEOUT8
TCELL36:OUT.8.TMINBITSLICE32.TX_T_OUT
TCELL36:OUT.9.TMINBITSLICE31.RX_CNTVALUEOUT0
TCELL36:OUT.10.TMINBITSLICE31.RX_CNTVALUEOUT1
TCELL36:OUT.11.TMINBITSLICE31.RX_CNTVALUEOUT2
TCELL36:OUT.12.TMINBITSLICE31.RX_CNTVALUEOUT3
TCELL36:OUT.13.TMINBITSLICE31.RX_CNTVALUEOUT4
TCELL36:OUT.14.TMINBITSLICE31.RX_CNTVALUEOUT5
TCELL36:OUT.15.TMINBITSLICE31.RX_CNTVALUEOUT6
TCELL36:OUT.16.TMINBITSLICE31.RX_CNTVALUEOUT7
TCELL36:OUT.17.TMINBITSLICE31.RX_CNTVALUEOUT8
TCELL36:OUT.18.TMINRIU_OR2.RIU_RD_VALID
TCELL36:OUT.19.TMINRIU_OR2.RIU_RD_DATA0
TCELL36:OUT.20.TMINRIU_OR2.RIU_RD_DATA1
TCELL36:OUT.21.TMINRIU_OR2.RIU_RD_DATA2
TCELL36:OUT.22.TMINRIU_OR2.RIU_RD_DATA3
TCELL36:OUT.23.TMINRIU_OR2.RIU_RD_DATA4
TCELL36:OUT.24.TMINRIU_OR2.RIU_RD_DATA5
TCELL36:OUT.25.TMINRIU_OR2.RIU_RD_DATA6
TCELL36:OUT.26.TMINRIU_OR2.RIU_RD_DATA7
TCELL36:OUT.27.TMINRIU_OR2.RIU_RD_DATA8
TCELL36:OUT.28.TMINRIU_OR2.RIU_RD_DATA9
TCELL36:OUT.29.TMINRIU_OR2.RIU_RD_DATA10
TCELL36:OUT.30.TMINRIU_OR2.RIU_RD_DATA11
TCELL36:OUT.31.TMINRIU_OR2.RIU_RD_DATA12
TCELL36:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.TXBIT_RST_B5
TCELL36:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.RXBIT_RST_B5
TCELL36:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.ODELAY_RST_B5
TCELL36:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.IDELAY_RST_B5
TCELL36:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK5
TCELL36:IMUX.BYP.6BITSLICE31.RX_EN_VTC
TCELL36:IMUX.BYP.7BITSLICE31.RX_CE_IDELAY
TCELL36:IMUX.BYP.8BITSLICE31.DYN_DCI_OUT_INT
TCELL36:IMUX.BYP.9XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B0
TCELL36:IMUX.BYP.10XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B1
TCELL36:IMUX.BYP.11XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B2
TCELL36:IMUX.BYP.12XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B3
TCELL36:IMUX.BYP.13XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_RST_MASK_B
TCELL36:IMUX.BYP.14XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_MODE_B
TCELL36:IMUX.BYP.15XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN0
TCELL36:IMUX.IMUX.6.DELAYBITSLICE31.TX_CNTVALUEIN1
TCELL36:IMUX.IMUX.7.DELAYBITSLICE31.TX_CNTVALUEIN3
TCELL36:IMUX.IMUX.8.DELAYBITSLICE31.TX_CNTVALUEIN7
TCELL36:IMUX.IMUX.10.DELAYBITSLICE31.RX_CNTVALUEIN3
TCELL36:IMUX.IMUX.11.DELAYBITSLICE31.RX_CNTVALUEIN5
TCELL36:IMUX.IMUX.12.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_EN, BITSLICE_CONTROL5.CLB2RIU_WR_EN
TCELL36:IMUX.IMUX.13.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA1, BITSLICE_CONTROL5.CLB2RIU_WR_DATA1
TCELL36:IMUX.IMUX.14.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA5, BITSLICE_CONTROL5.CLB2RIU_WR_DATA5
TCELL36:IMUX.IMUX.15.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA7, BITSLICE_CONTROL5.CLB2RIU_WR_DATA7
TCELL36:IMUX.IMUX.16.DELAYBITSLICE30.RX_CNTVALUEIN8
TCELL36:IMUX.IMUX.17.DELAYBITSLICE31.TX_T
TCELL36:IMUX.IMUX.18.DELAYBITSLICE31.TX_CE_OFD
TCELL36:IMUX.IMUX.19.DELAYBITSLICE31.RX_CE_IFD
TCELL36:IMUX.IMUX.20.DELAYBITSLICE31.RX_DATAIN1
TCELL36:IMUX.IMUX.21.DELAYBITSLICE31.CLB2PHY_FIFO_RDEN
TCELL36:IMUX.IMUX.22.DELAYBITSLICE31.TX_D0
TCELL36:IMUX.IMUX.23.DELAYBITSLICE31.TX_D1
TCELL36:IMUX.IMUX.24.DELAYBITSLICE31.TX_D2
TCELL36:IMUX.IMUX.25.DELAYBITSLICE31.TX_D3
TCELL36:IMUX.IMUX.26.DELAYBITSLICE31.TX_D4
TCELL36:IMUX.IMUX.27.DELAYBITSLICE31.TX_D5
TCELL36:IMUX.IMUX.28.DELAYBITSLICE31.TX_D6
TCELL36:IMUX.IMUX.29.DELAYBITSLICE31.TX_D7
TCELL36:IMUX.IMUX.30.DELAYBITSLICE31.TX_CNTVALUEIN0
TCELL36:IMUX.IMUX.31.DELAYBITSLICE31.TX_CNTVALUEIN2
TCELL36:IMUX.IMUX.32.DELAYBITSLICE31.TX_CNTVALUEIN4
TCELL36:IMUX.IMUX.33.DELAYBITSLICE31.TX_CNTVALUEIN5
TCELL36:IMUX.IMUX.34.DELAYBITSLICE31.TX_CNTVALUEIN6
TCELL36:IMUX.IMUX.35.DELAYBITSLICE31.TX_CNTVALUEIN8
TCELL36:IMUX.IMUX.36.DELAYBITSLICE31.RX_CNTVALUEIN0
TCELL36:IMUX.IMUX.37.DELAYBITSLICE31.RX_CNTVALUEIN1
TCELL36:IMUX.IMUX.38.DELAYBITSLICE31.RX_CNTVALUEIN2
TCELL36:IMUX.IMUX.39.DELAYBITSLICE31.RX_CNTVALUEIN4
TCELL36:IMUX.IMUX.40.DELAYBITSLICE31.RX_CNTVALUEIN6
TCELL36:IMUX.IMUX.41.DELAYBITSLICE31.RX_CNTVALUEIN7
TCELL36:IMUX.IMUX.42.DELAYBITSLICE31.RX_CNTVALUEIN8
TCELL36:IMUX.IMUX.43.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA0, BITSLICE_CONTROL5.CLB2RIU_WR_DATA0
TCELL36:IMUX.IMUX.44.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA2, BITSLICE_CONTROL5.CLB2RIU_WR_DATA2
TCELL36:IMUX.IMUX.45.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA3, BITSLICE_CONTROL5.CLB2RIU_WR_DATA3
TCELL36:IMUX.IMUX.46.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA4, BITSLICE_CONTROL5.CLB2RIU_WR_DATA4
TCELL36:IMUX.IMUX.47.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA6, BITSLICE_CONTROL5.CLB2RIU_WR_DATA6
TCELL37:OUT.4.TMINRIU_OR2.RIU_RD_DATA13
TCELL37:OUT.5.TMINRIU_OR2.RIU_RD_DATA14
TCELL37:OUT.6.TMINRIU_OR2.RIU_RD_DATA15
TCELL37:OUT.7.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT0
TCELL37:OUT.8.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT1
TCELL37:OUT.9.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT2
TCELL37:OUT.10.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT3
TCELL37:OUT.11.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT4
TCELL37:OUT.12.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT5
TCELL37:OUT.13.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT6
TCELL37:OUT.14.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT7
TCELL37:OUT.15.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_OUT
TCELL37:OUT.16.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_FLG_OUT
TCELL37:OUT.17.TMINXIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
TCELL37:OUT.18.TMINBITSLICE38.PHY2CLB_FIFO_EMPTY
TCELL37:OUT.19.TMINBITSLICE38.RX_Q0
TCELL37:OUT.20.TMINBITSLICE38.RX_Q1
TCELL37:OUT.21.TMINBITSLICE38.RX_Q2
TCELL37:OUT.22.TMINBITSLICE38.RX_Q3
TCELL37:OUT.23.TMINBITSLICE38.RX_Q4
TCELL37:OUT.24.TMINBITSLICE38.RX_Q5
TCELL37:OUT.25.TMINBITSLICE38.RX_Q6
TCELL37:OUT.26.TMINBITSLICE38.RX_Q7
TCELL37:OUT.27.TMINBITSLICE38.TX_CNTVALUEOUT0
TCELL37:OUT.28.TMINBITSLICE38.TX_CNTVALUEOUT1
TCELL37:OUT.29.TMINBITSLICE38.TX_CNTVALUEOUT2
TCELL37:OUT.30.TMINBITSLICE38.TX_CNTVALUEOUT3
TCELL37:OUT.31.TMINBITSLICE38.TX_CNTVALUEOUT4
TCELL37:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_SDR
TCELL37:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_DIV4
TCELL37:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_DIV2
TCELL37:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.TXBIT_RST_B12
TCELL37:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.RXBIT_RST_B12
TCELL37:IMUX.BYP.6XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN1
TCELL37:IMUX.BYP.7XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN2
TCELL37:IMUX.BYP.8XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN3
TCELL37:IMUX.BYP.10XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN4
TCELL37:IMUX.BYP.11XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN5
TCELL37:IMUX.BYP.12XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN6
TCELL37:IMUX.BYP.13XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN7
TCELL37:IMUX.BYP.14XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_EN_B
TCELL37:IMUX.BYP.15BITSLICE38.TX_LD
TCELL37:IMUX.IMUX.6.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_TEST_DIV4_CLK_SEL_B
TCELL37:IMUX.IMUX.7.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CT_START_EN
TCELL37:IMUX.IMUX.8.DELAYBITSLICE38.TX_CE_OFD
TCELL37:IMUX.IMUX.9.DELAYBITSLICE38.RX_DATAIN1
TCELL37:IMUX.IMUX.10.DELAYBITSLICE38.TX_D2
TCELL37:IMUX.IMUX.11.DELAYBITSLICE38.TX_D4
TCELL37:IMUX.IMUX.12.DELAYBITSLICE38.TX_CNTVALUEIN0
TCELL37:IMUX.IMUX.13.DELAYBITSLICE38.TX_CNTVALUEIN2
TCELL37:IMUX.IMUX.14.DELAYBITSLICE38.TX_CNTVALUEIN6
TCELL37:IMUX.IMUX.15.DELAYBITSLICE38.TX_CNTVALUEIN8
TCELL37:IMUX.IMUX.16.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA8, BITSLICE_CONTROL5.CLB2RIU_WR_DATA8
TCELL37:IMUX.IMUX.17.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA9, BITSLICE_CONTROL5.CLB2RIU_WR_DATA9
TCELL37:IMUX.IMUX.18.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA10, BITSLICE_CONTROL5.CLB2RIU_WR_DATA10
TCELL37:IMUX.IMUX.19.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA11, BITSLICE_CONTROL5.CLB2RIU_WR_DATA11
TCELL37:IMUX.IMUX.20.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA12, BITSLICE_CONTROL5.CLB2RIU_WR_DATA12
TCELL37:IMUX.IMUX.21.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA13, BITSLICE_CONTROL5.CLB2RIU_WR_DATA13
TCELL37:IMUX.IMUX.22.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA14, BITSLICE_CONTROL5.CLB2RIU_WR_DATA14
TCELL37:IMUX.IMUX.23.DELAYBITSLICE_CONTROL4.CLB2RIU_WR_DATA15, BITSLICE_CONTROL5.CLB2RIU_WR_DATA15
TCELL37:IMUX.IMUX.24.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR0, BITSLICE_CONTROL5.CLB2RIU_ADDR0
TCELL37:IMUX.IMUX.25.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR1, BITSLICE_CONTROL5.CLB2RIU_ADDR1
TCELL37:IMUX.IMUX.26.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR2, BITSLICE_CONTROL5.CLB2RIU_ADDR2
TCELL37:IMUX.IMUX.27.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR3, BITSLICE_CONTROL5.CLB2RIU_ADDR3
TCELL37:IMUX.IMUX.28.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR4, BITSLICE_CONTROL5.CLB2RIU_ADDR4
TCELL37:IMUX.IMUX.29.DELAYBITSLICE_CONTROL4.CLB2RIU_ADDR5, BITSLICE_CONTROL5.CLB2RIU_ADDR5
TCELL37:IMUX.IMUX.30.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SDR_CLK_SEL_B
TCELL37:IMUX.IMUX.31.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_TEST_DIV2_CLK_SEL_B
TCELL37:IMUX.IMUX.32.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CLK_STOP_FLG_OUT
TCELL37:IMUX.IMUX.33.DELAYXIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
TCELL37:IMUX.IMUX.34.DELAYBITSLICE38.TX_T
TCELL37:IMUX.IMUX.35.DELAYBITSLICE38.RX_CE_IFD
TCELL37:IMUX.IMUX.36.DELAYBITSLICE38.CLB2PHY_FIFO_RDEN
TCELL37:IMUX.IMUX.37.DELAYBITSLICE38.TX_D0
TCELL37:IMUX.IMUX.38.DELAYBITSLICE38.TX_D1
TCELL37:IMUX.IMUX.39.DELAYBITSLICE38.TX_D3
TCELL37:IMUX.IMUX.40.DELAYBITSLICE38.TX_D5
TCELL37:IMUX.IMUX.41.DELAYBITSLICE38.TX_D6
TCELL37:IMUX.IMUX.42.DELAYBITSLICE38.TX_D7
TCELL37:IMUX.IMUX.43.DELAYBITSLICE38.TX_CNTVALUEIN1
TCELL37:IMUX.IMUX.44.DELAYBITSLICE38.TX_CNTVALUEIN3
TCELL37:IMUX.IMUX.45.DELAYBITSLICE38.TX_CNTVALUEIN4
TCELL37:IMUX.IMUX.46.DELAYBITSLICE38.TX_CNTVALUEIN5
TCELL37:IMUX.IMUX.47.DELAYBITSLICE38.TX_CNTVALUEIN7
TCELL38:OUT.4.TMINBITSLICE38.TX_CNTVALUEOUT5
TCELL38:OUT.5.TMINBITSLICE38.TX_CNTVALUEOUT6
TCELL38:OUT.6.TMINBITSLICE38.TX_CNTVALUEOUT7
TCELL38:OUT.7.TMINBITSLICE38.TX_CNTVALUEOUT8
TCELL38:OUT.8.TMINBITSLICE33.TX_T_OUT
TCELL38:OUT.9.TMINBITSLICE38.RX_CNTVALUEOUT0
TCELL38:OUT.10.TMINBITSLICE38.RX_CNTVALUEOUT1
TCELL38:OUT.11.TMINBITSLICE38.RX_CNTVALUEOUT2
TCELL38:OUT.12.TMINBITSLICE38.RX_CNTVALUEOUT3
TCELL38:OUT.13.TMINBITSLICE38.RX_CNTVALUEOUT4
TCELL38:OUT.14.TMINBITSLICE38.RX_CNTVALUEOUT5
TCELL38:OUT.15.TMINBITSLICE38.RX_CNTVALUEOUT6
TCELL38:OUT.16.TMINBITSLICE38.RX_CNTVALUEOUT7
TCELL38:OUT.17.TMINBITSLICE38.RX_CNTVALUEOUT8
TCELL38:OUT.18.TMINBITSLICE32.PHY2CLB_FIFO_EMPTY
TCELL38:OUT.19.TMINBITSLICE32.RX_Q0
TCELL38:OUT.20.TMINBITSLICE32.RX_Q1
TCELL38:OUT.21.TMINBITSLICE32.RX_Q2
TCELL38:OUT.22.TMINBITSLICE32.RX_Q3
TCELL38:OUT.23.TMINBITSLICE32.RX_Q4
TCELL38:OUT.24.TMINBITSLICE32.RX_Q5
TCELL38:OUT.25.TMINBITSLICE32.RX_Q6
TCELL38:OUT.26.TMINBITSLICE32.RX_Q7
TCELL38:OUT.27.TMINBITSLICE32.TX_CNTVALUEOUT0
TCELL38:OUT.28.TMINBITSLICE32.TX_CNTVALUEOUT1
TCELL38:OUT.29.TMINBITSLICE32.TX_CNTVALUEOUT2
TCELL38:OUT.30.TMINBITSLICE32.TX_CNTVALUEOUT3
TCELL38:OUT.31.TMINBITSLICE32.TX_CNTVALUEOUT4
TCELL38:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.ODELAY_RST_B12
TCELL38:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.IDELAY_RST_B12
TCELL38:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK12
TCELL38:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.TXBIT_RST_B6
TCELL38:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.RXBIT_RST_B6
TCELL38:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.ODELAY_RST_B6
TCELL38:IMUX.BYP.6BITSLICE38.TX_INC
TCELL38:IMUX.BYP.7BITSLICE38.TX_EN_VTC
TCELL38:IMUX.BYP.8BITSLICE38.TX_CE_ODELAY
TCELL38:IMUX.BYP.9BITSLICE38.RX_LD
TCELL38:IMUX.BYP.10BITSLICE38.RX_INC
TCELL38:IMUX.BYP.11BITSLICE38.RX_EN_VTC
TCELL38:IMUX.BYP.12BITSLICE38.RX_CE_IDELAY
TCELL38:IMUX.BYP.13BITSLICE38.DYN_DCI_OUT_INT
TCELL38:IMUX.BYP.14BITSLICE32.TX_LD
TCELL38:IMUX.BYP.15BITSLICE32.TX_INC
TCELL38:IMUX.IMUX.6.DELAYBITSLICE32.TX_D0
TCELL38:IMUX.IMUX.7.DELAYBITSLICE32.TX_D2
TCELL38:IMUX.IMUX.8.DELAYBITSLICE32.TX_D6
TCELL38:IMUX.IMUX.9.DELAYBITSLICE32.TX_CNTVALUEIN0
TCELL38:IMUX.IMUX.10.DELAYBITSLICE32.TX_CNTVALUEIN4
TCELL38:IMUX.IMUX.11.DELAYBITSLICE32.TX_CNTVALUEIN6
TCELL38:IMUX.IMUX.12.DELAYBITSLICE32.RX_CNTVALUEIN1
TCELL38:IMUX.IMUX.13.DELAYBITSLICE32.RX_CNTVALUEIN3
TCELL38:IMUX.IMUX.14.DELAYBITSLICE32.RX_CNTVALUEIN7
TCELL38:IMUX.IMUX.15.DELAYBITSLICE33.TX_T
TCELL38:IMUX.IMUX.16.DELAYBITSLICE38.RX_CNTVALUEIN0
TCELL38:IMUX.IMUX.17.DELAYBITSLICE38.RX_CNTVALUEIN1
TCELL38:IMUX.IMUX.18.DELAYBITSLICE38.RX_CNTVALUEIN2
TCELL38:IMUX.IMUX.19.DELAYBITSLICE38.RX_CNTVALUEIN3
TCELL38:IMUX.IMUX.20.DELAYBITSLICE38.RX_CNTVALUEIN4
TCELL38:IMUX.IMUX.21.DELAYBITSLICE38.RX_CNTVALUEIN5
TCELL38:IMUX.IMUX.22.DELAYBITSLICE38.RX_CNTVALUEIN6
TCELL38:IMUX.IMUX.23.DELAYBITSLICE38.RX_CNTVALUEIN7
TCELL38:IMUX.IMUX.24.DELAYBITSLICE38.RX_CNTVALUEIN8
TCELL38:IMUX.IMUX.25.DELAYBITSLICE32.TX_T
TCELL38:IMUX.IMUX.26.DELAYBITSLICE32.TX_CE_OFD
TCELL38:IMUX.IMUX.27.DELAYBITSLICE32.RX_CE_IFD
TCELL38:IMUX.IMUX.29.DELAYBITSLICE32.RX_DATAIN1
TCELL38:IMUX.IMUX.30.DELAYBITSLICE32.CLB2PHY_FIFO_RDEN
TCELL38:IMUX.IMUX.31.DELAYBITSLICE32.TX_D1
TCELL38:IMUX.IMUX.32.DELAYBITSLICE32.TX_D3
TCELL38:IMUX.IMUX.33.DELAYBITSLICE32.TX_D4
TCELL38:IMUX.IMUX.34.DELAYBITSLICE32.TX_D5
TCELL38:IMUX.IMUX.35.DELAYBITSLICE32.TX_D7
TCELL38:IMUX.IMUX.36.DELAYBITSLICE32.TX_CNTVALUEIN1
TCELL38:IMUX.IMUX.37.DELAYBITSLICE32.TX_CNTVALUEIN2
TCELL38:IMUX.IMUX.38.DELAYBITSLICE32.TX_CNTVALUEIN3
TCELL38:IMUX.IMUX.39.DELAYBITSLICE32.TX_CNTVALUEIN5
TCELL38:IMUX.IMUX.40.DELAYBITSLICE32.TX_CNTVALUEIN7
TCELL38:IMUX.IMUX.41.DELAYBITSLICE32.TX_CNTVALUEIN8
TCELL38:IMUX.IMUX.42.DELAYBITSLICE32.RX_CNTVALUEIN0
TCELL38:IMUX.IMUX.43.DELAYBITSLICE32.RX_CNTVALUEIN2
TCELL38:IMUX.IMUX.44.DELAYBITSLICE32.RX_CNTVALUEIN4
TCELL38:IMUX.IMUX.45.DELAYBITSLICE32.RX_CNTVALUEIN5
TCELL38:IMUX.IMUX.46.DELAYBITSLICE32.RX_CNTVALUEIN6
TCELL38:IMUX.IMUX.47.DELAYBITSLICE32.RX_CNTVALUEIN8
TCELL39:OUT.4.TMINBITSLICE32.TX_CNTVALUEOUT5
TCELL39:OUT.5.TMINBITSLICE32.TX_CNTVALUEOUT6
TCELL39:OUT.6.TMINBITSLICE32.TX_CNTVALUEOUT7
TCELL39:OUT.7.TMINBITSLICE32.TX_CNTVALUEOUT8
TCELL39:OUT.8.TMINBITSLICE34.TX_T_OUT
TCELL39:OUT.9.TMINBITSLICE32.RX_CNTVALUEOUT0
TCELL39:OUT.10.TMINBITSLICE32.RX_CNTVALUEOUT1
TCELL39:OUT.11.TMINBITSLICE32.RX_CNTVALUEOUT2
TCELL39:OUT.12.TMINBITSLICE32.RX_CNTVALUEOUT3
TCELL39:OUT.13.TMINBITSLICE32.RX_CNTVALUEOUT4
TCELL39:OUT.14.TMINBITSLICE32.RX_CNTVALUEOUT5
TCELL39:OUT.15.TMINBITSLICE32.RX_CNTVALUEOUT6
TCELL39:OUT.16.TMINBITSLICE32.RX_CNTVALUEOUT7
TCELL39:OUT.17.TMINBITSLICE32.RX_CNTVALUEOUT8
TCELL39:OUT.18.TMINBITSLICE33.PHY2CLB_FIFO_EMPTY
TCELL39:OUT.19.TMINBITSLICE33.RX_Q0
TCELL39:OUT.20.TMINBITSLICE33.RX_Q1
TCELL39:OUT.21.TMINBITSLICE33.RX_Q2
TCELL39:OUT.22.TMINBITSLICE33.RX_Q3
TCELL39:OUT.23.TMINBITSLICE33.RX_Q4
TCELL39:OUT.24.TMINBITSLICE33.RX_Q5
TCELL39:OUT.25.TMINBITSLICE33.RX_Q6
TCELL39:OUT.26.TMINBITSLICE33.RX_Q7
TCELL39:OUT.27.TMINBITSLICE33.TX_CNTVALUEOUT0
TCELL39:OUT.28.TMINBITSLICE33.TX_CNTVALUEOUT1
TCELL39:OUT.29.TMINBITSLICE33.TX_CNTVALUEOUT2
TCELL39:OUT.30.TMINBITSLICE33.TX_CNTVALUEOUT3
TCELL39:OUT.31.TMINBITSLICE33.TX_CNTVALUEOUT4
TCELL39:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.IDELAY_RST_B6
TCELL39:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK6
TCELL39:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.TXBIT_RST_B7
TCELL39:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.RXBIT_RST_B7
TCELL39:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.ODELAY_RST_B7
TCELL39:IMUX.BYP.6BITSLICE32.TX_EN_VTC
TCELL39:IMUX.BYP.7BITSLICE32.TX_CE_ODELAY
TCELL39:IMUX.BYP.8BITSLICE32.RX_LD
TCELL39:IMUX.BYP.9BITSLICE32.RX_INC
TCELL39:IMUX.BYP.10BITSLICE32.RX_EN_VTC
TCELL39:IMUX.BYP.11BITSLICE32.RX_CE_IDELAY
TCELL39:IMUX.BYP.12BITSLICE32.DYN_DCI_OUT_INT
TCELL39:IMUX.BYP.14BITSLICE33.TX_LD
TCELL39:IMUX.BYP.15BITSLICE33.TX_INC
TCELL39:IMUX.IMUX.6.DELAYBITSLICE33.TX_CNTVALUEIN3
TCELL39:IMUX.IMUX.7.DELAYBITSLICE33.TX_CNTVALUEIN5
TCELL39:IMUX.IMUX.8.DELAYBITSLICE33.RX_CNTVALUEIN0
TCELL39:IMUX.IMUX.9.DELAYBITSLICE33.RX_CNTVALUEIN2
TCELL39:IMUX.IMUX.10.DELAYBITSLICE33.RX_CNTVALUEIN6
TCELL39:IMUX.IMUX.11.DELAYBITSLICE33.RX_CNTVALUEIN8
TCELL39:IMUX.IMUX.12.DELAYBITSLICE34.RX_DATAIN1
TCELL39:IMUX.IMUX.13.DELAYBITSLICE34.TX_D0
TCELL39:IMUX.IMUX.14.DELAYBITSLICE34.TX_D4
TCELL39:IMUX.IMUX.15.DELAYBITSLICE34.TX_D6
TCELL39:IMUX.IMUX.16.DELAYBITSLICE33.TX_CE_OFD
TCELL39:IMUX.IMUX.17.DELAYBITSLICE33.RX_CE_IFD
TCELL39:IMUX.IMUX.18.DELAYBITSLICE33.RX_DATAIN1
TCELL39:IMUX.IMUX.19.DELAYBITSLICE33.CLB2PHY_FIFO_RDEN
TCELL39:IMUX.IMUX.20.DELAYBITSLICE33.TX_D0
TCELL39:IMUX.IMUX.21.DELAYBITSLICE33.TX_D1
TCELL39:IMUX.IMUX.22.DELAYBITSLICE33.TX_D2
TCELL39:IMUX.IMUX.23.DELAYBITSLICE33.TX_D3
TCELL39:IMUX.IMUX.24.DELAYBITSLICE33.TX_D4
TCELL39:IMUX.IMUX.25.DELAYBITSLICE33.TX_D5
TCELL39:IMUX.IMUX.26.DELAYBITSLICE33.TX_D6
TCELL39:IMUX.IMUX.27.DELAYBITSLICE33.TX_D7
TCELL39:IMUX.IMUX.28.DELAYBITSLICE33.TX_CNTVALUEIN0
TCELL39:IMUX.IMUX.29.DELAYBITSLICE33.TX_CNTVALUEIN1
TCELL39:IMUX.IMUX.30.DELAYBITSLICE33.TX_CNTVALUEIN2
TCELL39:IMUX.IMUX.31.DELAYBITSLICE33.TX_CNTVALUEIN4
TCELL39:IMUX.IMUX.32.DELAYBITSLICE33.TX_CNTVALUEIN6
TCELL39:IMUX.IMUX.33.DELAYBITSLICE33.TX_CNTVALUEIN7
TCELL39:IMUX.IMUX.34.DELAYBITSLICE33.TX_CNTVALUEIN8
TCELL39:IMUX.IMUX.35.DELAYBITSLICE33.RX_CNTVALUEIN1
TCELL39:IMUX.IMUX.36.DELAYBITSLICE33.RX_CNTVALUEIN3
TCELL39:IMUX.IMUX.37.DELAYBITSLICE33.RX_CNTVALUEIN4
TCELL39:IMUX.IMUX.38.DELAYBITSLICE33.RX_CNTVALUEIN5
TCELL39:IMUX.IMUX.39.DELAYBITSLICE33.RX_CNTVALUEIN7
TCELL39:IMUX.IMUX.40.DELAYBITSLICE34.TX_T
TCELL39:IMUX.IMUX.41.DELAYBITSLICE34.TX_CE_OFD
TCELL39:IMUX.IMUX.42.DELAYBITSLICE34.RX_CE_IFD
TCELL39:IMUX.IMUX.43.DELAYBITSLICE34.CLB2PHY_FIFO_RDEN
TCELL39:IMUX.IMUX.44.DELAYBITSLICE34.TX_D1
TCELL39:IMUX.IMUX.45.DELAYBITSLICE34.TX_D2
TCELL39:IMUX.IMUX.46.DELAYBITSLICE34.TX_D3
TCELL39:IMUX.IMUX.47.DELAYBITSLICE34.TX_D5
TCELL40:OUT.4.TMINBITSLICE33.TX_CNTVALUEOUT5
TCELL40:OUT.5.TMINBITSLICE33.TX_CNTVALUEOUT6
TCELL40:OUT.6.TMINBITSLICE33.TX_CNTVALUEOUT7
TCELL40:OUT.7.TMINBITSLICE33.TX_CNTVALUEOUT8
TCELL40:OUT.8.TMINBITSLICE35.TX_T_OUT
TCELL40:OUT.9.TMINBITSLICE33.RX_CNTVALUEOUT0
TCELL40:OUT.10.TMINBITSLICE33.RX_CNTVALUEOUT1
TCELL40:OUT.11.TMINBITSLICE33.RX_CNTVALUEOUT2
TCELL40:OUT.12.TMINBITSLICE33.RX_CNTVALUEOUT3
TCELL40:OUT.13.TMINBITSLICE33.RX_CNTVALUEOUT4
TCELL40:OUT.14.TMINBITSLICE33.RX_CNTVALUEOUT5
TCELL40:OUT.15.TMINBITSLICE33.RX_CNTVALUEOUT6
TCELL40:OUT.16.TMINBITSLICE33.RX_CNTVALUEOUT7
TCELL40:OUT.17.TMINBITSLICE33.RX_CNTVALUEOUT8
TCELL40:OUT.18.TMINBITSLICE34.PHY2CLB_FIFO_EMPTY
TCELL40:OUT.19.TMINBITSLICE34.RX_Q0
TCELL40:OUT.20.TMINBITSLICE34.RX_Q1
TCELL40:OUT.21.TMINBITSLICE34.RX_Q2
TCELL40:OUT.22.TMINBITSLICE34.RX_Q3
TCELL40:OUT.23.TMINBITSLICE34.RX_Q4
TCELL40:OUT.24.TMINBITSLICE34.RX_Q5
TCELL40:OUT.25.TMINBITSLICE34.RX_Q6
TCELL40:OUT.26.TMINBITSLICE34.RX_Q7
TCELL40:OUT.27.TMINBITSLICE34.TX_CNTVALUEOUT0
TCELL40:OUT.28.TMINBITSLICE34.TX_CNTVALUEOUT1
TCELL40:OUT.29.TMINBITSLICE34.TX_CNTVALUEOUT2
TCELL40:OUT.30.TMINBITSLICE34.TX_CNTVALUEOUT3
TCELL40:OUT.31.TMINBITSLICE34.TX_CNTVALUEOUT4
TCELL40:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.IDELAY_RST_B7
TCELL40:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK7
TCELL40:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.TXBIT_RST_B8
TCELL40:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.RXBIT_RST_B8
TCELL40:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.ODELAY_RST_B8
TCELL40:IMUX.BYP.6BITSLICE33.TX_EN_VTC
TCELL40:IMUX.BYP.7BITSLICE33.TX_CE_ODELAY
TCELL40:IMUX.BYP.8BITSLICE33.RX_LD
TCELL40:IMUX.BYP.9BITSLICE33.RX_INC
TCELL40:IMUX.BYP.10BITSLICE33.RX_EN_VTC
TCELL40:IMUX.BYP.11BITSLICE33.RX_CE_IDELAY
TCELL40:IMUX.BYP.12BITSLICE33.DYN_DCI_OUT_INT
TCELL40:IMUX.BYP.13BITSLICE34.TX_LD
TCELL40:IMUX.BYP.14BITSLICE34.TX_INC
TCELL40:IMUX.BYP.15BITSLICE34.TX_EN_VTC
TCELL40:IMUX.IMUX.6.DELAYBITSLICE34.RX_CNTVALUEIN4
TCELL40:IMUX.IMUX.7.DELAYBITSLICE34.RX_CNTVALUEIN6
TCELL40:IMUX.IMUX.8.DELAYBITSLICE_T5.CNTVALUEIN1
TCELL40:IMUX.IMUX.9.DELAYBITSLICE_T5.CNTVALUEIN3
TCELL40:IMUX.IMUX.10.DELAYBITSLICE_T5.CNTVALUEIN7
TCELL40:IMUX.IMUX.11.DELAYBITSLICE_CONTROL5.CLB2RIU_NIBBLE_SEL
TCELL40:IMUX.IMUX.12.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS1_3
TCELL40:IMUX.IMUX.13.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS0_1
TCELL40:IMUX.IMUX.14.DELAYBITSLICE_CONTROL5.CLB2PHY_T_B1
TCELL40:IMUX.IMUX.15.DELAYBITSLICE_CONTROL5.CLB2PHY_T_B3
TCELL40:IMUX.IMUX.16.DELAYBITSLICE34.TX_D7
TCELL40:IMUX.IMUX.18.DELAYBITSLICE34.TX_CNTVALUEIN0
TCELL40:IMUX.IMUX.19.DELAYBITSLICE34.TX_CNTVALUEIN1
TCELL40:IMUX.IMUX.20.DELAYBITSLICE34.TX_CNTVALUEIN2
TCELL40:IMUX.IMUX.21.DELAYBITSLICE34.TX_CNTVALUEIN3
TCELL40:IMUX.IMUX.22.DELAYBITSLICE34.TX_CNTVALUEIN4
TCELL40:IMUX.IMUX.23.DELAYBITSLICE34.TX_CNTVALUEIN5
TCELL40:IMUX.IMUX.24.DELAYBITSLICE34.TX_CNTVALUEIN6
TCELL40:IMUX.IMUX.25.DELAYBITSLICE34.TX_CNTVALUEIN7
TCELL40:IMUX.IMUX.26.DELAYBITSLICE34.TX_CNTVALUEIN8
TCELL40:IMUX.IMUX.27.DELAYBITSLICE34.RX_CNTVALUEIN0
TCELL40:IMUX.IMUX.28.DELAYBITSLICE34.RX_CNTVALUEIN1
TCELL40:IMUX.IMUX.29.DELAYBITSLICE34.RX_CNTVALUEIN2
TCELL40:IMUX.IMUX.30.DELAYBITSLICE34.RX_CNTVALUEIN3
TCELL40:IMUX.IMUX.31.DELAYBITSLICE34.RX_CNTVALUEIN5
TCELL40:IMUX.IMUX.32.DELAYBITSLICE34.RX_CNTVALUEIN7
TCELL40:IMUX.IMUX.33.DELAYBITSLICE34.RX_CNTVALUEIN8
TCELL40:IMUX.IMUX.34.DELAYBITSLICE_T5.CNTVALUEIN0
TCELL40:IMUX.IMUX.35.DELAYBITSLICE_T5.CNTVALUEIN2
TCELL40:IMUX.IMUX.36.DELAYBITSLICE_T5.CNTVALUEIN4
TCELL40:IMUX.IMUX.37.DELAYBITSLICE_T5.CNTVALUEIN5
TCELL40:IMUX.IMUX.38.DELAYBITSLICE_T5.CNTVALUEIN6
TCELL40:IMUX.IMUX.39.DELAYBITSLICE_T5.CNTVALUEIN8
TCELL40:IMUX.IMUX.40.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS1_0
TCELL40:IMUX.IMUX.41.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS1_1
TCELL40:IMUX.IMUX.42.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS1_2
TCELL40:IMUX.IMUX.43.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS0_0
TCELL40:IMUX.IMUX.44.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS0_2
TCELL40:IMUX.IMUX.45.DELAYBITSLICE_CONTROL5.CLB2PHY_WRCS0_3
TCELL40:IMUX.IMUX.46.DELAYBITSLICE_CONTROL5.CLB2PHY_T_B0
TCELL40:IMUX.IMUX.47.DELAYBITSLICE_CONTROL5.CLB2PHY_T_B2
TCELL41:OUT.0.TMINMMCM.TESTOUT32
TCELL41:OUT.1.TMINMMCM.TESTOUT33
TCELL41:OUT.2.TMINMMCM.TESTOUT34
TCELL41:OUT.3.TMINMMCM.TESTOUT35
TCELL41:OUT.4.TMINBITSLICE34.TX_CNTVALUEOUT5
TCELL41:OUT.5.TMINBITSLICE34.TX_CNTVALUEOUT6
TCELL41:OUT.6.TMINBITSLICE34.TX_CNTVALUEOUT7
TCELL41:OUT.7.TMINBITSLICE34.TX_CNTVALUEOUT8
TCELL41:OUT.8.TMINBITSLICE36.TX_T_OUT
TCELL41:OUT.9.TMINBITSLICE34.RX_CNTVALUEOUT0
TCELL41:OUT.10.TMINBITSLICE34.RX_CNTVALUEOUT1
TCELL41:OUT.11.TMINBITSLICE34.RX_CNTVALUEOUT2
TCELL41:OUT.12.TMINBITSLICE34.RX_CNTVALUEOUT3
TCELL41:OUT.13.TMINBITSLICE34.RX_CNTVALUEOUT4
TCELL41:OUT.14.TMINBITSLICE34.RX_CNTVALUEOUT5
TCELL41:OUT.15.TMINBITSLICE34.RX_CNTVALUEOUT6
TCELL41:OUT.16.TMINBITSLICE34.RX_CNTVALUEOUT7
TCELL41:OUT.17.TMINBITSLICE34.RX_CNTVALUEOUT8
TCELL41:OUT.18.TMINBITSLICE_T5.CNTVALUEOUT0
TCELL41:OUT.19.TMINBITSLICE_T5.CNTVALUEOUT1
TCELL41:OUT.20.TMINBITSLICE_T5.CNTVALUEOUT2
TCELL41:OUT.21.TMINBITSLICE_T5.CNTVALUEOUT3
TCELL41:OUT.22.TMINBITSLICE_T5.CNTVALUEOUT4
TCELL41:OUT.23.TMINBITSLICE_T5.CNTVALUEOUT5
TCELL41:OUT.24.TMINBITSLICE_T5.CNTVALUEOUT6
TCELL41:OUT.25.TMINBITSLICE_T5.CNTVALUEOUT7
TCELL41:OUT.26.TMINBITSLICE_T5.CNTVALUEOUT8
TCELL41:OUT.27.TMINBITSLICE_CONTROL5.PHY2CLB_PHY_RDY
TCELL41:OUT.28.TMINBITSLICE_CONTROL5.MASTER_PD_OUT
TCELL41:OUT.29.TMINBITSLICE_CONTROL5.PHY2CLB_FIXDLY_RDY
TCELL41:OUT.30.TMINBITSLICE_CONTROL5.CTRL_DLY_TEST_OUT
TCELL41:OUT.31.TMINBITSLICE37.TX_T_OUT
TCELL41:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.IDELAY_RST_B8
TCELL41:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK8
TCELL41:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.TRISTATE_ODELAY_RST_B1
TCELL41:IMUX.CTRL.6BITSLICE_CONTROL5.REFCLK
TCELL41:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.CTRL_RST_B_UPP
TCELL41:IMUX.BYP.0MMCM.TESTIN28
TCELL41:IMUX.BYP.1MMCM.TESTIN29
TCELL41:IMUX.BYP.2MMCM.TESTIN30
TCELL41:IMUX.BYP.3MMCM.TESTIN31
TCELL41:IMUX.BYP.6BITSLICE34.TX_CE_ODELAY
TCELL41:IMUX.BYP.8BITSLICE34.RX_LD
TCELL41:IMUX.BYP.9BITSLICE34.RX_INC
TCELL41:IMUX.BYP.10BITSLICE34.RX_EN_VTC
TCELL41:IMUX.BYP.11BITSLICE34.RX_CE_IDELAY
TCELL41:IMUX.BYP.12BITSLICE34.DYN_DCI_OUT_INT
TCELL41:IMUX.BYP.13BITSLICE_T5.CE_OFD
TCELL41:IMUX.BYP.14BITSLICE_T5.LD
TCELL41:IMUX.BYP.15BITSLICE_T5.INC
TCELL41:IMUX.IMUX.0.DELAYMMCM.CLKINSEL
TCELL41:IMUX.IMUX.6.DELAYBITSLICE35.RX_DATAIN1
TCELL41:IMUX.IMUX.7.DELAYBITSLICE35.TX_D0
TCELL41:IMUX.IMUX.8.DELAYBITSLICE35.TX_D4
TCELL41:IMUX.IMUX.9.DELAYBITSLICE35.TX_D6
TCELL41:IMUX.IMUX.10.DELAYBITSLICE35.TX_CNTVALUEIN2
TCELL41:IMUX.IMUX.11.DELAYBITSLICE35.TX_CNTVALUEIN4
TCELL41:IMUX.IMUX.12.DELAYBITSLICE35.TX_CNTVALUEIN7
TCELL41:IMUX.IMUX.13.DELAYBITSLICE35.RX_CNTVALUEIN0
TCELL41:IMUX.IMUX.14.DELAYBITSLICE35.RX_CNTVALUEIN4
TCELL41:IMUX.IMUX.15.DELAYBITSLICE35.RX_CNTVALUEIN6
TCELL41:IMUX.IMUX.16.DELAYBITSLICE_CONTROL5.CLB2PHY_RDEN0
TCELL41:IMUX.IMUX.17.DELAYBITSLICE_CONTROL5.CLB2PHY_RDEN1
TCELL41:IMUX.IMUX.18.DELAYBITSLICE_CONTROL5.CLB2PHY_RDEN2
TCELL41:IMUX.IMUX.19.DELAYBITSLICE_CONTROL5.CLB2PHY_RDEN3
TCELL41:IMUX.IMUX.20.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS1_0
TCELL41:IMUX.IMUX.21.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS1_1
TCELL41:IMUX.IMUX.22.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS1_2
TCELL41:IMUX.IMUX.23.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS1_3
TCELL41:IMUX.IMUX.24.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS0_0
TCELL41:IMUX.IMUX.25.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS0_1
TCELL41:IMUX.IMUX.26.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS0_2
TCELL41:IMUX.IMUX.27.DELAYBITSLICE_CONTROL5.CLB2PHY_RDCS0_3
TCELL41:IMUX.IMUX.28.DELAYBITSLICE35.TX_T
TCELL41:IMUX.IMUX.29.DELAYBITSLICE35.TX_CE_OFD
TCELL41:IMUX.IMUX.30.DELAYBITSLICE35.RX_CE_IFD
TCELL41:IMUX.IMUX.31.DELAYBITSLICE35.CLB2PHY_FIFO_RDEN
TCELL41:IMUX.IMUX.32.DELAYBITSLICE35.TX_D1
TCELL41:IMUX.IMUX.33.DELAYBITSLICE35.TX_D2
TCELL41:IMUX.IMUX.34.DELAYBITSLICE35.TX_D3
TCELL41:IMUX.IMUX.35.DELAYBITSLICE35.TX_D5
TCELL41:IMUX.IMUX.36.DELAYBITSLICE35.TX_D7
TCELL41:IMUX.IMUX.37.DELAYBITSLICE35.TX_CNTVALUEIN0
TCELL41:IMUX.IMUX.38.DELAYBITSLICE35.TX_CNTVALUEIN1
TCELL41:IMUX.IMUX.39.DELAYBITSLICE35.TX_CNTVALUEIN3
TCELL41:IMUX.IMUX.40.DELAYBITSLICE35.TX_CNTVALUEIN5
TCELL41:IMUX.IMUX.41.DELAYBITSLICE35.TX_CNTVALUEIN6
TCELL41:IMUX.IMUX.43.DELAYBITSLICE35.TX_CNTVALUEIN8
TCELL41:IMUX.IMUX.44.DELAYBITSLICE35.RX_CNTVALUEIN1
TCELL41:IMUX.IMUX.45.DELAYBITSLICE35.RX_CNTVALUEIN2
TCELL41:IMUX.IMUX.46.DELAYBITSLICE35.RX_CNTVALUEIN3
TCELL41:IMUX.IMUX.47.DELAYBITSLICE35.RX_CNTVALUEIN5
TCELL42:OUT.0.TMINMMCM.TESTOUT28
TCELL42:OUT.1.TMINMMCM.TESTOUT29
TCELL42:OUT.2.TMINMMCM.TESTOUT30
TCELL42:OUT.3.TMINMMCM.TESTOUT31
TCELL42:OUT.4.TMINBITSLICE35.PHY2CLB_FIFO_EMPTY
TCELL42:OUT.5.TMINBITSLICE35.RX_Q0
TCELL42:OUT.6.TMINBITSLICE35.RX_Q1
TCELL42:OUT.7.TMINBITSLICE35.RX_Q2
TCELL42:OUT.8.TMINBITSLICE35.RX_Q3
TCELL42:OUT.9.TMINBITSLICE35.RX_Q4
TCELL42:OUT.10.TMINBITSLICE35.RX_Q5
TCELL42:OUT.11.TMINBITSLICE35.RX_Q6
TCELL42:OUT.12.TMINBITSLICE35.RX_Q7
TCELL42:OUT.13.TMINBITSLICE35.TX_CNTVALUEOUT0
TCELL42:OUT.14.TMINBITSLICE35.TX_CNTVALUEOUT1
TCELL42:OUT.15.TMINBITSLICE35.TX_CNTVALUEOUT2
TCELL42:OUT.16.TMINBITSLICE35.TX_CNTVALUEOUT3
TCELL42:OUT.17.TMINBITSLICE35.TX_CNTVALUEOUT4
TCELL42:OUT.18.TMINBITSLICE35.TX_CNTVALUEOUT5
TCELL42:OUT.19.TMINBITSLICE35.TX_CNTVALUEOUT6
TCELL42:OUT.20.TMINBITSLICE35.TX_CNTVALUEOUT7
TCELL42:OUT.21.TMINBITSLICE35.TX_CNTVALUEOUT8
TCELL42:OUT.22.TMINBITSLICE38.TX_T_OUT
TCELL42:OUT.23.TMINBITSLICE35.RX_CNTVALUEOUT0
TCELL42:OUT.24.TMINBITSLICE35.RX_CNTVALUEOUT1
TCELL42:OUT.25.TMINBITSLICE35.RX_CNTVALUEOUT2
TCELL42:OUT.26.TMINBITSLICE35.RX_CNTVALUEOUT3
TCELL42:OUT.27.TMINBITSLICE35.RX_CNTVALUEOUT4
TCELL42:OUT.28.TMINBITSLICE35.RX_CNTVALUEOUT5
TCELL42:OUT.29.TMINBITSLICE35.RX_CNTVALUEOUT6
TCELL42:OUT.30.TMINBITSLICE35.RX_CNTVALUEOUT7
TCELL42:OUT.31.TMINBITSLICE35.RX_CNTVALUEOUT8
TCELL42:IMUX.CTRL.2BITSLICE_CONTROL5.RIU_CLK, XIPHY_FEEDTHROUGH2.CLB2PHY_CTRL_CLK_UPP
TCELL42:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.TXBIT_RST_B9
TCELL42:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.RXBIT_RST_B9
TCELL42:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.ODELAY_RST_B9
TCELL42:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.IDELAY_RST_B9
TCELL42:IMUX.BYP.0MMCM.TESTIN24
TCELL42:IMUX.BYP.1MMCM.TESTIN25
TCELL42:IMUX.BYP.2MMCM.TESTIN26
TCELL42:IMUX.BYP.3MMCM.TESTIN27
TCELL42:IMUX.BYP.6BITSLICE_T5.CE_ODELAY
TCELL42:IMUX.BYP.7BITSLICE_CONTROL5.EN_VTC
TCELL42:IMUX.BYP.8BITSLICE_CONTROL5.CTRL_DLY_TEST_IN
TCELL42:IMUX.BYP.9BITSLICE35.TX_LD
TCELL42:IMUX.BYP.10BITSLICE35.TX_INC
TCELL42:IMUX.BYP.11BITSLICE35.TX_EN_VTC
TCELL42:IMUX.BYP.12BITSLICE35.TX_CE_ODELAY
TCELL42:IMUX.BYP.13BITSLICE35.RX_LD
TCELL42:IMUX.BYP.14BITSLICE35.RX_INC
TCELL42:IMUX.BYP.15BITSLICE35.RX_EN_VTC
TCELL42:IMUX.IMUX.6.DELAYBITSLICE36.TX_CNTVALUEIN0
TCELL42:IMUX.IMUX.7.DELAYBITSLICE36.TX_CNTVALUEIN2
TCELL42:IMUX.IMUX.8.DELAYBITSLICE36.TX_CNTVALUEIN6
TCELL42:IMUX.IMUX.9.DELAYBITSLICE36.TX_CNTVALUEIN8
TCELL42:IMUX.IMUX.10.DELAYBITSLICE36.RX_CNTVALUEIN3
TCELL42:IMUX.IMUX.11.DELAYBITSLICE36.RX_CNTVALUEIN5
TCELL42:IMUX.IMUX.12.DELAYBITSLICE37.TX_T
TCELL42:IMUX.IMUX.13.DELAYBITSLICE37.RX_CE_IFD
TCELL42:IMUX.IMUX.14.DELAYBITSLICE37.TX_D1
TCELL42:IMUX.IMUX.15.DELAYBITSLICE37.TX_D3
TCELL42:IMUX.IMUX.16.DELAYBITSLICE35.RX_CNTVALUEIN7
TCELL42:IMUX.IMUX.17.DELAYBITSLICE35.RX_CNTVALUEIN8
TCELL42:IMUX.IMUX.18.DELAYBITSLICE36.TX_T
TCELL42:IMUX.IMUX.19.DELAYBITSLICE36.TX_CE_OFD
TCELL42:IMUX.IMUX.20.DELAYBITSLICE36.RX_CE_IFD
TCELL42:IMUX.IMUX.21.DELAYBITSLICE36.RX_DATAIN1
TCELL42:IMUX.IMUX.22.DELAYBITSLICE36.CLB2PHY_FIFO_RDEN
TCELL42:IMUX.IMUX.23.DELAYBITSLICE36.TX_D5
TCELL42:IMUX.IMUX.24.DELAYBITSLICE36.TX_D4
TCELL42:IMUX.IMUX.25.DELAYBITSLICE36.TX_D3
TCELL42:IMUX.IMUX.26.DELAYBITSLICE36.TX_D2
TCELL42:IMUX.IMUX.27.DELAYBITSLICE36.TX_D1
TCELL42:IMUX.IMUX.28.DELAYBITSLICE36.TX_D0
TCELL42:IMUX.IMUX.29.DELAYBITSLICE36.TX_D6
TCELL42:IMUX.IMUX.30.DELAYBITSLICE36.TX_D7
TCELL42:IMUX.IMUX.31.DELAYBITSLICE36.TX_CNTVALUEIN1
TCELL42:IMUX.IMUX.32.DELAYBITSLICE36.TX_CNTVALUEIN3
TCELL42:IMUX.IMUX.33.DELAYBITSLICE36.TX_CNTVALUEIN4
TCELL42:IMUX.IMUX.34.DELAYBITSLICE36.TX_CNTVALUEIN5
TCELL42:IMUX.IMUX.35.DELAYBITSLICE36.TX_CNTVALUEIN7
TCELL42:IMUX.IMUX.36.DELAYBITSLICE36.RX_CNTVALUEIN0
TCELL42:IMUX.IMUX.37.DELAYBITSLICE36.RX_CNTVALUEIN1
TCELL42:IMUX.IMUX.38.DELAYBITSLICE36.RX_CNTVALUEIN2
TCELL42:IMUX.IMUX.39.DELAYBITSLICE36.RX_CNTVALUEIN4
TCELL42:IMUX.IMUX.40.DELAYBITSLICE36.RX_CNTVALUEIN6
TCELL42:IMUX.IMUX.41.DELAYBITSLICE36.RX_CNTVALUEIN7
TCELL42:IMUX.IMUX.42.DELAYBITSLICE36.RX_CNTVALUEIN8
TCELL42:IMUX.IMUX.43.DELAYBITSLICE37.TX_CE_OFD
TCELL42:IMUX.IMUX.44.DELAYBITSLICE37.RX_DATAIN1
TCELL42:IMUX.IMUX.45.DELAYBITSLICE37.CLB2PHY_FIFO_RDEN
TCELL42:IMUX.IMUX.46.DELAYBITSLICE37.TX_D0
TCELL42:IMUX.IMUX.47.DELAYBITSLICE37.TX_D2
TCELL43:OUT.0.TMINMMCM.TESTOUT24
TCELL43:OUT.1.TMINMMCM.TESTOUT25
TCELL43:OUT.2.TMINMMCM.TESTOUT26
TCELL43:OUT.3.TMINMMCM.TESTOUT27
TCELL43:OUT.4.TMINBITSLICE36.PHY2CLB_FIFO_EMPTY
TCELL43:OUT.5.TMINBITSLICE36.RX_Q0
TCELL43:OUT.6.TMINBITSLICE36.RX_Q1
TCELL43:OUT.7.TMINBITSLICE36.RX_Q2
TCELL43:OUT.8.TMINBITSLICE36.RX_Q3
TCELL43:OUT.9.TMINBITSLICE36.RX_Q4
TCELL43:OUT.10.TMINBITSLICE36.RX_Q5
TCELL43:OUT.11.TMINBITSLICE36.RX_Q6
TCELL43:OUT.12.TMINBITSLICE36.RX_Q7
TCELL43:OUT.13.TMINBITSLICE36.TX_CNTVALUEOUT0
TCELL43:OUT.14.TMINBITSLICE36.TX_CNTVALUEOUT1
TCELL43:OUT.15.TMINBITSLICE36.TX_CNTVALUEOUT2
TCELL43:OUT.16.TMINBITSLICE36.TX_CNTVALUEOUT3
TCELL43:OUT.17.TMINBITSLICE36.TX_CNTVALUEOUT4
TCELL43:OUT.18.TMINBITSLICE36.TX_CNTVALUEOUT5
TCELL43:OUT.19.TMINBITSLICE36.TX_CNTVALUEOUT6
TCELL43:OUT.20.TMINBITSLICE36.TX_CNTVALUEOUT7
TCELL43:OUT.21.TMINBITSLICE36.TX_CNTVALUEOUT8
TCELL43:OUT.23.TMINBITSLICE36.RX_CNTVALUEOUT0
TCELL43:OUT.24.TMINBITSLICE36.RX_CNTVALUEOUT1
TCELL43:OUT.25.TMINBITSLICE36.RX_CNTVALUEOUT2
TCELL43:OUT.26.TMINBITSLICE36.RX_CNTVALUEOUT3
TCELL43:OUT.27.TMINBITSLICE36.RX_CNTVALUEOUT4
TCELL43:OUT.28.TMINBITSLICE36.RX_CNTVALUEOUT5
TCELL43:OUT.29.TMINBITSLICE36.RX_CNTVALUEOUT6
TCELL43:OUT.30.TMINBITSLICE36.RX_CNTVALUEOUT7
TCELL43:OUT.31.TMINBITSLICE36.RX_CNTVALUEOUT8
TCELL43:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK9
TCELL43:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.TXBIT_RST_B10
TCELL43:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.RXBIT_RST_B10
TCELL43:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.ODELAY_RST_B10
TCELL43:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.IDELAY_RST_B10
TCELL43:IMUX.BYP.0MMCM.TESTIN20
TCELL43:IMUX.BYP.1MMCM.TESTIN21
TCELL43:IMUX.BYP.2MMCM.TESTIN22
TCELL43:IMUX.BYP.3MMCM.TESTIN23
TCELL43:IMUX.BYP.6BITSLICE35.RX_CE_IDELAY
TCELL43:IMUX.BYP.7BITSLICE35.DYN_DCI_OUT_INT
TCELL43:IMUX.BYP.8BITSLICE36.TX_LD
TCELL43:IMUX.BYP.9BITSLICE36.TX_INC
TCELL43:IMUX.BYP.10BITSLICE36.TX_EN_VTC
TCELL43:IMUX.BYP.11BITSLICE36.TX_CE_ODELAY
TCELL43:IMUX.BYP.12BITSLICE36.RX_LD
TCELL43:IMUX.BYP.13BITSLICE36.RX_INC
TCELL43:IMUX.BYP.14BITSLICE36.RX_EN_VTC
TCELL43:IMUX.BYP.15BITSLICE36.RX_CE_IDELAY
TCELL43:IMUX.IMUX.6.DELAYBITSLICE37.TX_D5
TCELL43:IMUX.IMUX.7.DELAYBITSLICE37.TX_D6
TCELL43:IMUX.IMUX.8.DELAYBITSLICE37.TX_D7
TCELL43:IMUX.IMUX.9.DELAYBITSLICE37.TX_CNTVALUEIN0
TCELL43:IMUX.IMUX.10.DELAYBITSLICE37.TX_CNTVALUEIN1
TCELL43:IMUX.IMUX.11.DELAYBITSLICE37.TX_CNTVALUEIN2
TCELL43:IMUX.IMUX.12.DELAYBITSLICE37.TX_CNTVALUEIN3
TCELL43:IMUX.IMUX.13.DELAYBITSLICE37.TX_CNTVALUEIN4
TCELL43:IMUX.IMUX.14.DELAYBITSLICE37.TX_CNTVALUEIN5
TCELL43:IMUX.IMUX.15.DELAYBITSLICE37.TX_CNTVALUEIN6
TCELL43:IMUX.IMUX.16.DELAYBITSLICE37.TX_D4
TCELL44:OUT.0.TMINMMCM.TESTOUT20
TCELL44:OUT.1.TMINMMCM.TESTOUT21
TCELL44:OUT.2.TMINMMCM.TESTOUT22
TCELL44:OUT.3.TMINMMCM.TESTOUT23
TCELL44:OUT.4.TMINBITSLICE37.PHY2CLB_FIFO_EMPTY
TCELL44:OUT.5.TMINBITSLICE37.RX_Q0
TCELL44:OUT.6.TMINBITSLICE37.RX_Q1
TCELL44:OUT.7.TMINBITSLICE37.RX_Q2
TCELL44:OUT.8.TMINBITSLICE37.RX_Q3
TCELL44:OUT.9.TMINBITSLICE37.RX_Q4
TCELL44:OUT.10.TMINBITSLICE37.RX_Q5
TCELL44:OUT.11.TMINBITSLICE37.RX_Q6
TCELL44:OUT.12.TMINBITSLICE37.RX_Q7
TCELL44:OUT.13.TMINBITSLICE37.TX_CNTVALUEOUT0
TCELL44:OUT.14.TMINBITSLICE37.TX_CNTVALUEOUT1
TCELL44:OUT.15.TMINBITSLICE37.TX_CNTVALUEOUT2
TCELL44:OUT.16.TMINBITSLICE37.TX_CNTVALUEOUT3
TCELL44:OUT.17.TMINBITSLICE37.TX_CNTVALUEOUT4
TCELL44:OUT.18.TMINBITSLICE37.TX_CNTVALUEOUT5
TCELL44:OUT.19.TMINBITSLICE37.TX_CNTVALUEOUT6
TCELL44:OUT.20.TMINBITSLICE37.TX_CNTVALUEOUT7
TCELL44:OUT.21.TMINBITSLICE37.TX_CNTVALUEOUT8
TCELL44:OUT.23.TMINBITSLICE37.RX_CNTVALUEOUT0
TCELL44:OUT.24.TMINBITSLICE37.RX_CNTVALUEOUT1
TCELL44:OUT.25.TMINBITSLICE37.RX_CNTVALUEOUT2
TCELL44:OUT.26.TMINBITSLICE37.RX_CNTVALUEOUT3
TCELL44:OUT.27.TMINBITSLICE37.RX_CNTVALUEOUT4
TCELL44:OUT.28.TMINBITSLICE37.RX_CNTVALUEOUT5
TCELL44:OUT.29.TMINBITSLICE37.RX_CNTVALUEOUT6
TCELL44:OUT.30.TMINBITSLICE37.RX_CNTVALUEOUT7
TCELL44:OUT.31.TMINBITSLICE37.RX_CNTVALUEOUT8
TCELL44:IMUX.CTRL.2XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK10
TCELL44:IMUX.CTRL.3XIPHY_FEEDTHROUGH2.TXBIT_RST_B11
TCELL44:IMUX.CTRL.4XIPHY_FEEDTHROUGH2.RXBIT_RST_B11
TCELL44:IMUX.CTRL.5XIPHY_FEEDTHROUGH2.ODELAY_RST_B11
TCELL44:IMUX.CTRL.6XIPHY_FEEDTHROUGH2.IDELAY_RST_B11
TCELL44:IMUX.CTRL.7XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK11
TCELL44:IMUX.BYP.0MMCM.TESTIN16
TCELL44:IMUX.BYP.1MMCM.TESTIN17
TCELL44:IMUX.BYP.2MMCM.TESTIN18
TCELL44:IMUX.BYP.3MMCM.TESTIN19
TCELL44:IMUX.BYP.6BITSLICE36.DYN_DCI_OUT_INT
TCELL44:IMUX.BYP.7BITSLICE37.TX_LD
TCELL44:IMUX.BYP.8BITSLICE37.TX_INC
TCELL44:IMUX.BYP.9BITSLICE37.TX_EN_VTC
TCELL44:IMUX.BYP.10BITSLICE37.TX_CE_ODELAY
TCELL44:IMUX.BYP.11BITSLICE37.RX_LD
TCELL44:IMUX.BYP.12BITSLICE37.RX_INC
TCELL44:IMUX.BYP.13BITSLICE37.RX_EN_VTC
TCELL44:IMUX.BYP.14BITSLICE37.RX_CE_IDELAY
TCELL44:IMUX.BYP.15BITSLICE37.DYN_DCI_OUT_INT
TCELL44:IMUX.IMUX.6.DELAYBITSLICE37.TX_CNTVALUEIN8
TCELL44:IMUX.IMUX.7.DELAYBITSLICE37.RX_CNTVALUEIN0
TCELL44:IMUX.IMUX.8.DELAYBITSLICE37.RX_CNTVALUEIN1
TCELL44:IMUX.IMUX.9.DELAYBITSLICE37.RX_CNTVALUEIN2
TCELL44:IMUX.IMUX.10.DELAYBITSLICE37.RX_CNTVALUEIN3
TCELL44:IMUX.IMUX.11.DELAYBITSLICE37.RX_CNTVALUEIN4
TCELL44:IMUX.IMUX.12.DELAYBITSLICE37.RX_CNTVALUEIN5
TCELL44:IMUX.IMUX.13.DELAYBITSLICE37.RX_CNTVALUEIN6
TCELL44:IMUX.IMUX.14.DELAYBITSLICE37.RX_CNTVALUEIN7
TCELL44:IMUX.IMUX.15.DELAYBITSLICE37.RX_CNTVALUEIN8
TCELL44:IMUX.IMUX.16.DELAYBITSLICE37.TX_CNTVALUEIN7
TCELL45:OUT.0.TMINMMCM.TESTOUT16
TCELL45:OUT.1.TMINMMCM.TESTOUT17
TCELL45:OUT.2.TMINMMCM.TESTOUT18
TCELL45:OUT.3.TMINMMCM.TESTOUT19
TCELL45:OUT.4.TMINBITSLICE39.PHY2CLB_FIFO_EMPTY
TCELL45:OUT.5.TMINBITSLICE39.RX_Q0
TCELL45:OUT.6.TMINBITSLICE39.RX_Q1
TCELL45:OUT.7.TMINBITSLICE39.RX_Q2
TCELL45:OUT.8.TMINBITSLICE39.RX_Q3
TCELL45:OUT.9.TMINBITSLICE39.RX_Q4
TCELL45:OUT.10.TMINBITSLICE39.RX_Q5
TCELL45:OUT.11.TMINBITSLICE39.RX_Q6
TCELL45:OUT.12.TMINBITSLICE39.RX_Q7
TCELL45:OUT.13.TMINBITSLICE39.TX_CNTVALUEOUT0
TCELL45:OUT.14.TMINBITSLICE39.TX_CNTVALUEOUT1
TCELL45:OUT.15.TMINBITSLICE39.TX_CNTVALUEOUT2
TCELL45:OUT.16.TMINBITSLICE39.TX_CNTVALUEOUT3
TCELL45:OUT.17.TMINBITSLICE39.TX_CNTVALUEOUT4
TCELL45:OUT.18.TMINBITSLICE39.TX_CNTVALUEOUT5
TCELL45:OUT.19.TMINBITSLICE39.TX_CNTVALUEOUT6
TCELL45:OUT.20.TMINBITSLICE39.TX_CNTVALUEOUT7
TCELL45:OUT.21.TMINBITSLICE39.TX_CNTVALUEOUT8
TCELL45:OUT.22.TMINBITSLICE39.TX_T_OUT
TCELL45:OUT.23.TMINBITSLICE39.RX_CNTVALUEOUT0
TCELL45:OUT.24.TMINBITSLICE39.RX_CNTVALUEOUT1
TCELL45:OUT.25.TMINBITSLICE39.RX_CNTVALUEOUT2
TCELL45:OUT.26.TMINBITSLICE39.RX_CNTVALUEOUT3
TCELL45:OUT.27.TMINBITSLICE39.RX_CNTVALUEOUT4
TCELL45:OUT.28.TMINBITSLICE39.RX_CNTVALUEOUT5
TCELL45:OUT.29.TMINBITSLICE39.RX_CNTVALUEOUT6
TCELL45:OUT.30.TMINBITSLICE39.RX_CNTVALUEOUT7
TCELL45:OUT.31.TMINBITSLICE39.RX_CNTVALUEOUT8
TCELL45:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.TXBIT_TRI_RST_B0
TCELL45:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.TXBIT_RST_B0
TCELL45:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.RXBIT_RST_B0
TCELL45:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.ODELAY_RST_B0
TCELL45:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.IDELAY_RST_B0
TCELL45:IMUX.BYP.0MMCM.TESTIN12
TCELL45:IMUX.BYP.1MMCM.TESTIN13
TCELL45:IMUX.BYP.2MMCM.TESTIN14
TCELL45:IMUX.BYP.3MMCM.TESTIN15
TCELL45:IMUX.BYP.6BITSLICE_T6.EN_VTC
TCELL45:IMUX.BYP.7BITSLICE39.TX_LD
TCELL45:IMUX.BYP.8BITSLICE39.TX_INC
TCELL45:IMUX.BYP.9BITSLICE39.TX_EN_VTC
TCELL45:IMUX.BYP.10BITSLICE39.TX_CE_ODELAY
TCELL45:IMUX.BYP.11BITSLICE39.RX_LD
TCELL45:IMUX.BYP.12BITSLICE39.RX_INC
TCELL45:IMUX.BYP.13BITSLICE39.RX_EN_VTC
TCELL45:IMUX.BYP.14BITSLICE39.RX_CE_IDELAY
TCELL45:IMUX.BYP.15BITSLICE39.DYN_DCI_OUT_INT
TCELL45:IMUX.IMUX.6.DELAYBITSLICE39.TX_CE_OFD
TCELL45:IMUX.IMUX.7.DELAYBITSLICE39.RX_CE_IFD
TCELL45:IMUX.IMUX.8.DELAYBITSLICE39.RX_DATAIN1
TCELL45:IMUX.IMUX.9.DELAYBITSLICE39.CLB2PHY_FIFO_RDEN
TCELL45:IMUX.IMUX.10.DELAYBITSLICE39.TX_D7
TCELL45:IMUX.IMUX.11.DELAYBITSLICE39.TX_D6
TCELL45:IMUX.IMUX.12.DELAYBITSLICE39.TX_D5
TCELL45:IMUX.IMUX.13.DELAYBITSLICE39.TX_D4
TCELL45:IMUX.IMUX.14.DELAYBITSLICE39.TX_D3
TCELL45:IMUX.IMUX.15.DELAYBITSLICE39.TX_D2
TCELL45:IMUX.IMUX.16.DELAYBITSLICE39.TX_T
TCELL46:OUT.0.TMINMMCM.TESTOUT12
TCELL46:OUT.1.TMINMMCM.TESTOUT13
TCELL46:OUT.2.TMINMMCM.TESTOUT14
TCELL46:OUT.3.TMINMMCM.TESTOUT15
TCELL46:OUT.4.TMINBITSLICE40.PHY2CLB_FIFO_EMPTY
TCELL46:OUT.5.TMINBITSLICE40.RX_Q0
TCELL46:OUT.6.TMINBITSLICE40.RX_Q1
TCELL46:OUT.7.TMINBITSLICE40.RX_Q2
TCELL46:OUT.8.TMINBITSLICE40.RX_Q3
TCELL46:OUT.9.TMINBITSLICE40.RX_Q4
TCELL46:OUT.10.TMINBITSLICE40.RX_Q5
TCELL46:OUT.11.TMINBITSLICE40.RX_Q6
TCELL46:OUT.12.TMINBITSLICE40.RX_Q7
TCELL46:OUT.13.TMINBITSLICE40.TX_CNTVALUEOUT0
TCELL46:OUT.14.TMINBITSLICE40.TX_CNTVALUEOUT1
TCELL46:OUT.15.TMINBITSLICE40.TX_CNTVALUEOUT2
TCELL46:OUT.16.TMINBITSLICE40.TX_CNTVALUEOUT3
TCELL46:OUT.17.TMINBITSLICE40.TX_CNTVALUEOUT4
TCELL46:OUT.18.TMINBITSLICE40.TX_CNTVALUEOUT5
TCELL46:OUT.19.TMINBITSLICE40.TX_CNTVALUEOUT6
TCELL46:OUT.20.TMINBITSLICE40.TX_CNTVALUEOUT7
TCELL46:OUT.21.TMINBITSLICE40.TX_CNTVALUEOUT8
TCELL46:OUT.22.TMINBITSLICE40.TX_T_OUT
TCELL46:OUT.23.TMINBITSLICE40.RX_CNTVALUEOUT0
TCELL46:OUT.24.TMINBITSLICE40.RX_CNTVALUEOUT1
TCELL46:OUT.25.TMINBITSLICE40.RX_CNTVALUEOUT2
TCELL46:OUT.26.TMINBITSLICE40.RX_CNTVALUEOUT3
TCELL46:OUT.27.TMINBITSLICE40.RX_CNTVALUEOUT4
TCELL46:OUT.28.TMINBITSLICE40.RX_CNTVALUEOUT5
TCELL46:OUT.29.TMINBITSLICE40.RX_CNTVALUEOUT6
TCELL46:OUT.30.TMINBITSLICE40.RX_CNTVALUEOUT7
TCELL46:OUT.31.TMINBITSLICE40.RX_CNTVALUEOUT8
TCELL46:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK0
TCELL46:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.TXBIT_TRI_RST_B1
TCELL46:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.TXBIT_RST_B1
TCELL46:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.RXBIT_RST_B1
TCELL46:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.ODELAY_RST_B1
TCELL46:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.IDELAY_RST_B1
TCELL46:IMUX.BYP.0MMCM.TESTIN8
TCELL46:IMUX.BYP.1MMCM.TESTIN9
TCELL46:IMUX.BYP.2MMCM.TESTIN10
TCELL46:IMUX.BYP.3MMCM.TESTIN11
TCELL46:IMUX.BYP.6BITSLICE_T7.EN_VTC
TCELL46:IMUX.BYP.7BITSLICE40.TX_LD
TCELL46:IMUX.BYP.8BITSLICE40.TX_INC
TCELL46:IMUX.BYP.9BITSLICE40.TX_EN_VTC
TCELL46:IMUX.BYP.10BITSLICE40.TX_CE_ODELAY
TCELL46:IMUX.BYP.11BITSLICE40.RX_LD
TCELL46:IMUX.BYP.12BITSLICE40.RX_INC
TCELL46:IMUX.BYP.13BITSLICE40.RX_EN_VTC
TCELL46:IMUX.BYP.14BITSLICE40.RX_CE_IDELAY
TCELL46:IMUX.BYP.15BITSLICE40.DYN_DCI_OUT_INT
TCELL46:IMUX.IMUX.6.DELAYBITSLICE39.TX_D1
TCELL46:IMUX.IMUX.7.DELAYBITSLICE39.TX_CNTVALUEIN0
TCELL46:IMUX.IMUX.8.DELAYBITSLICE39.TX_CNTVALUEIN1
TCELL46:IMUX.IMUX.9.DELAYBITSLICE39.TX_CNTVALUEIN2
TCELL46:IMUX.IMUX.10.DELAYBITSLICE39.TX_CNTVALUEIN3
TCELL46:IMUX.IMUX.11.DELAYBITSLICE39.TX_CNTVALUEIN4
TCELL46:IMUX.IMUX.12.DELAYBITSLICE39.TX_CNTVALUEIN5
TCELL46:IMUX.IMUX.13.DELAYBITSLICE39.TX_CNTVALUEIN6
TCELL46:IMUX.IMUX.14.DELAYBITSLICE39.TX_CNTVALUEIN7
TCELL46:IMUX.IMUX.15.DELAYBITSLICE39.TX_CNTVALUEIN8
TCELL46:IMUX.IMUX.16.DELAYBITSLICE39.TX_D0
TCELL47:OUT.0.TMINMMCM.TESTOUT8
TCELL47:OUT.1.TMINMMCM.TESTOUT9
TCELL47:OUT.2.TMINMMCM.TESTOUT10
TCELL47:OUT.3.TMINMMCM.TESTOUT11
TCELL47:OUT.4.TMINBITSLICE41.PHY2CLB_FIFO_EMPTY
TCELL47:OUT.5.TMINBITSLICE41.RX_Q0
TCELL47:OUT.6.TMINBITSLICE41.RX_Q1
TCELL47:OUT.7.TMINBITSLICE41.RX_Q2
TCELL47:OUT.8.TMINBITSLICE41.RX_Q3
TCELL47:OUT.9.TMINBITSLICE41.RX_Q4
TCELL47:OUT.10.TMINBITSLICE41.RX_Q5
TCELL47:OUT.11.TMINBITSLICE41.RX_Q6
TCELL47:OUT.12.TMINBITSLICE41.RX_Q7
TCELL47:OUT.13.TMINBITSLICE41.TX_CNTVALUEOUT0
TCELL47:OUT.14.TMINBITSLICE41.TX_CNTVALUEOUT1
TCELL47:OUT.15.TMINBITSLICE41.TX_CNTVALUEOUT2
TCELL47:OUT.16.TMINBITSLICE41.TX_CNTVALUEOUT3
TCELL47:OUT.17.TMINBITSLICE41.TX_CNTVALUEOUT4
TCELL47:OUT.18.TMINBITSLICE41.TX_CNTVALUEOUT5
TCELL47:OUT.19.TMINBITSLICE41.TX_CNTVALUEOUT6
TCELL47:OUT.20.TMINBITSLICE41.TX_CNTVALUEOUT7
TCELL47:OUT.21.TMINBITSLICE41.TX_CNTVALUEOUT8
TCELL47:OUT.22.TMINBITSLICE41.TX_T_OUT
TCELL47:OUT.23.TMINBITSLICE41.RX_CNTVALUEOUT0
TCELL47:OUT.24.TMINBITSLICE41.RX_CNTVALUEOUT1
TCELL47:OUT.25.TMINBITSLICE41.RX_CNTVALUEOUT2
TCELL47:OUT.26.TMINBITSLICE41.RX_CNTVALUEOUT3
TCELL47:OUT.27.TMINBITSLICE41.RX_CNTVALUEOUT4
TCELL47:OUT.28.TMINBITSLICE41.RX_CNTVALUEOUT5
TCELL47:OUT.29.TMINBITSLICE41.RX_CNTVALUEOUT6
TCELL47:OUT.30.TMINBITSLICE41.RX_CNTVALUEOUT7
TCELL47:OUT.31.TMINBITSLICE41.RX_CNTVALUEOUT8
TCELL47:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK1
TCELL47:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.TXBIT_RST_B2
TCELL47:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.RXBIT_RST_B2
TCELL47:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.ODELAY_RST_B2
TCELL47:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.IDELAY_RST_B2
TCELL47:IMUX.BYP.0MMCM.TESTIN4
TCELL47:IMUX.BYP.1MMCM.TESTIN5
TCELL47:IMUX.BYP.2MMCM.TESTIN6
TCELL47:IMUX.BYP.3MMCM.TESTIN7
TCELL47:IMUX.BYP.6BITSLICE41.TX_LD
TCELL47:IMUX.BYP.7BITSLICE41.TX_INC
TCELL47:IMUX.BYP.8BITSLICE41.TX_EN_VTC
TCELL47:IMUX.BYP.9BITSLICE41.TX_CE_ODELAY
TCELL47:IMUX.BYP.10BITSLICE41.RX_LD
TCELL47:IMUX.BYP.11BITSLICE41.RX_INC
TCELL47:IMUX.BYP.12BITSLICE41.RX_EN_VTC
TCELL47:IMUX.BYP.13BITSLICE41.RX_CE_IDELAY
TCELL47:IMUX.BYP.14BITSLICE41.DYN_DCI_OUT_INT
TCELL47:IMUX.BYP.15BITSLICE_T6.CE_OFD
TCELL47:IMUX.IMUX.0.DELAYMMCM.SCANMODEB
TCELL47:IMUX.IMUX.6.DELAYBITSLICE40.TX_D1
TCELL47:IMUX.IMUX.7.DELAYBITSLICE40.TX_D3
TCELL47:IMUX.IMUX.8.DELAYBITSLICE40.TX_D7
TCELL47:IMUX.IMUX.9.DELAYBITSLICE40.TX_CNTVALUEIN1
TCELL47:IMUX.IMUX.10.DELAYBITSLICE40.TX_CNTVALUEIN5
TCELL47:IMUX.IMUX.11.DELAYBITSLICE40.TX_CNTVALUEIN7
TCELL47:IMUX.IMUX.12.DELAYBITSLICE40.RX_CNTVALUEIN2
TCELL47:IMUX.IMUX.13.DELAYBITSLICE40.RX_CNTVALUEIN4
TCELL47:IMUX.IMUX.14.DELAYBITSLICE40.RX_CNTVALUEIN8
TCELL47:IMUX.IMUX.15.DELAYBITSLICE41.TX_CE_OFD
TCELL47:IMUX.IMUX.16.DELAYBITSLICE39.RX_CNTVALUEIN0
TCELL47:IMUX.IMUX.17.DELAYBITSLICE39.RX_CNTVALUEIN1
TCELL47:IMUX.IMUX.18.DELAYBITSLICE39.RX_CNTVALUEIN2
TCELL47:IMUX.IMUX.19.DELAYBITSLICE39.RX_CNTVALUEIN3
TCELL47:IMUX.IMUX.20.DELAYBITSLICE39.RX_CNTVALUEIN4
TCELL47:IMUX.IMUX.21.DELAYBITSLICE39.RX_CNTVALUEIN5
TCELL47:IMUX.IMUX.22.DELAYBITSLICE39.RX_CNTVALUEIN6
TCELL47:IMUX.IMUX.23.DELAYBITSLICE39.RX_CNTVALUEIN7
TCELL47:IMUX.IMUX.24.DELAYBITSLICE39.RX_CNTVALUEIN8
TCELL47:IMUX.IMUX.25.DELAYBITSLICE40.TX_T
TCELL47:IMUX.IMUX.26.DELAYBITSLICE40.TX_CE_OFD
TCELL47:IMUX.IMUX.27.DELAYBITSLICE40.RX_CE_IFD
TCELL47:IMUX.IMUX.28.DELAYBITSLICE40.RX_DATAIN1
TCELL47:IMUX.IMUX.29.DELAYBITSLICE40.CLB2PHY_FIFO_RDEN
TCELL47:IMUX.IMUX.30.DELAYBITSLICE40.TX_D0
TCELL47:IMUX.IMUX.31.DELAYBITSLICE40.TX_D2
TCELL47:IMUX.IMUX.32.DELAYBITSLICE40.TX_D4
TCELL47:IMUX.IMUX.33.DELAYBITSLICE40.TX_D5
TCELL47:IMUX.IMUX.34.DELAYBITSLICE40.TX_D6
TCELL47:IMUX.IMUX.35.DELAYBITSLICE40.TX_CNTVALUEIN0
TCELL47:IMUX.IMUX.36.DELAYBITSLICE40.TX_CNTVALUEIN2
TCELL47:IMUX.IMUX.37.DELAYBITSLICE40.TX_CNTVALUEIN3
TCELL47:IMUX.IMUX.38.DELAYBITSLICE40.TX_CNTVALUEIN4
TCELL47:IMUX.IMUX.39.DELAYBITSLICE40.TX_CNTVALUEIN6
TCELL47:IMUX.IMUX.40.DELAYBITSLICE40.TX_CNTVALUEIN8
TCELL47:IMUX.IMUX.41.DELAYBITSLICE40.RX_CNTVALUEIN0
TCELL47:IMUX.IMUX.42.DELAYBITSLICE40.RX_CNTVALUEIN1
TCELL47:IMUX.IMUX.43.DELAYBITSLICE40.RX_CNTVALUEIN3
TCELL47:IMUX.IMUX.44.DELAYBITSLICE40.RX_CNTVALUEIN5
TCELL47:IMUX.IMUX.45.DELAYBITSLICE40.RX_CNTVALUEIN6
TCELL47:IMUX.IMUX.46.DELAYBITSLICE40.RX_CNTVALUEIN7
TCELL47:IMUX.IMUX.47.DELAYBITSLICE41.TX_T
TCELL48:OUT.0.TMINMMCM.TESTOUT4
TCELL48:OUT.1.TMINMMCM.TESTOUT5
TCELL48:OUT.2.TMINMMCM.TESTOUT6
TCELL48:OUT.3.TMINMMCM.TESTOUT7
TCELL48:OUT.4.TMINBITSLICE_T6.CNTVALUEOUT0
TCELL48:OUT.5.TMINBITSLICE_T6.CNTVALUEOUT1
TCELL48:OUT.6.TMINBITSLICE_T6.CNTVALUEOUT2
TCELL48:OUT.7.TMINBITSLICE_T6.CNTVALUEOUT3
TCELL48:OUT.8.TMINBITSLICE_T6.CNTVALUEOUT4
TCELL48:OUT.9.TMINBITSLICE_T6.CNTVALUEOUT5
TCELL48:OUT.10.TMINBITSLICE_T6.CNTVALUEOUT6
TCELL48:OUT.11.TMINBITSLICE_T6.CNTVALUEOUT7
TCELL48:OUT.12.TMINBITSLICE_T6.CNTVALUEOUT8
TCELL48:OUT.13.TMINBITSLICE42.TX_T_OUT
TCELL48:OUT.14.TMINBITSLICE_CONTROL6.PHY2CLB_PHY_RDY
TCELL48:OUT.15.TMINBITSLICE_CONTROL6.MASTER_PD_OUT
TCELL48:OUT.16.TMINBITSLICE_CONTROL6.PHY2CLB_FIXDLY_RDY
TCELL48:OUT.17.TMINBITSLICE_CONTROL6.CTRL_DLY_TEST_OUT
TCELL48:OUT.18.TMINBITSLICE42.PHY2CLB_FIFO_EMPTY
TCELL48:OUT.19.TMINBITSLICE42.RX_Q0
TCELL48:OUT.20.TMINBITSLICE42.RX_Q1
TCELL48:OUT.21.TMINBITSLICE42.RX_Q2
TCELL48:OUT.22.TMINBITSLICE42.RX_Q3
TCELL48:OUT.23.TMINBITSLICE42.RX_Q4
TCELL48:OUT.24.TMINBITSLICE42.RX_Q5
TCELL48:OUT.25.TMINBITSLICE42.RX_Q6
TCELL48:OUT.26.TMINBITSLICE42.RX_Q7
TCELL48:OUT.27.TMINBITSLICE42.TX_CNTVALUEOUT0
TCELL48:OUT.28.TMINBITSLICE42.TX_CNTVALUEOUT1
TCELL48:OUT.29.TMINBITSLICE42.TX_CNTVALUEOUT2
TCELL48:OUT.30.TMINBITSLICE42.TX_CNTVALUEOUT3
TCELL48:OUT.31.TMINBITSLICE42.TX_CNTVALUEOUT4
TCELL48:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK2
TCELL48:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.TRISTATE_ODELAY_RST_B0
TCELL48:IMUX.CTRL.5BITSLICE_CONTROL6.REFCLK
TCELL48:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.CTRL_RST_B_LOW
TCELL48:IMUX.CTRL.7BITSLICE_CONTROL6.RIU_CLK, XIPHY_FEEDTHROUGH3.CLB2PHY_CTRL_CLK_LOW
TCELL48:IMUX.BYP.0MMCM.TESTIN0
TCELL48:IMUX.BYP.1MMCM.TESTIN1
TCELL48:IMUX.BYP.2MMCM.TESTIN2
TCELL48:IMUX.BYP.3MMCM.TESTIN3
TCELL48:IMUX.BYP.6BITSLICE_T6.LD
TCELL48:IMUX.BYP.7BITSLICE_T6.INC
TCELL48:IMUX.BYP.8BITSLICE_T6.CE_ODELAY
TCELL48:IMUX.BYP.9BITSLICE_CONTROL6.EN_VTC
TCELL48:IMUX.BYP.10BITSLICE_CONTROL6.CTRL_DLY_TEST_IN
TCELL48:IMUX.BYP.12BITSLICE42.TX_LD
TCELL48:IMUX.BYP.13BITSLICE42.TX_INC
TCELL48:IMUX.BYP.14BITSLICE42.TX_EN_VTC
TCELL48:IMUX.BYP.15BITSLICE42.TX_CE_ODELAY
TCELL48:IMUX.IMUX.0.DELAYMMCM.SCANENB
TCELL48:IMUX.IMUX.6.DELAYBITSLICE41.TX_CNTVALUEIN3
TCELL48:IMUX.IMUX.7.DELAYBITSLICE41.TX_CNTVALUEIN5
TCELL48:IMUX.IMUX.8.DELAYBITSLICE41.RX_CNTVALUEIN0
TCELL48:IMUX.IMUX.9.DELAYBITSLICE41.RX_CNTVALUEIN2
TCELL48:IMUX.IMUX.10.DELAYBITSLICE41.RX_CNTVALUEIN6
TCELL48:IMUX.IMUX.11.DELAYBITSLICE41.RX_CNTVALUEIN8
TCELL48:IMUX.IMUX.12.DELAYBITSLICE_T6.CNTVALUEIN3
TCELL48:IMUX.IMUX.13.DELAYBITSLICE_T6.CNTVALUEIN5
TCELL48:IMUX.IMUX.14.DELAYBITSLICE_CONTROL6.CLB2RIU_NIBBLE_SEL
TCELL48:IMUX.IMUX.15.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS1_1
TCELL48:IMUX.IMUX.16.DELAYBITSLICE41.RX_CE_IFD
TCELL48:IMUX.IMUX.17.DELAYBITSLICE41.RX_DATAIN1
TCELL48:IMUX.IMUX.18.DELAYBITSLICE41.CLB2PHY_FIFO_RDEN
TCELL48:IMUX.IMUX.20.DELAYBITSLICE41.TX_D0
TCELL48:IMUX.IMUX.21.DELAYBITSLICE41.TX_D1
TCELL48:IMUX.IMUX.22.DELAYBITSLICE41.TX_D2
TCELL48:IMUX.IMUX.23.DELAYBITSLICE41.TX_D3
TCELL48:IMUX.IMUX.24.DELAYBITSLICE41.TX_D4
TCELL48:IMUX.IMUX.25.DELAYBITSLICE41.TX_D5
TCELL48:IMUX.IMUX.26.DELAYBITSLICE41.TX_D6
TCELL48:IMUX.IMUX.27.DELAYBITSLICE41.TX_D7
TCELL48:IMUX.IMUX.28.DELAYBITSLICE41.TX_CNTVALUEIN0
TCELL48:IMUX.IMUX.29.DELAYBITSLICE41.TX_CNTVALUEIN1
TCELL48:IMUX.IMUX.30.DELAYBITSLICE41.TX_CNTVALUEIN2
TCELL48:IMUX.IMUX.31.DELAYBITSLICE41.TX_CNTVALUEIN4
TCELL48:IMUX.IMUX.32.DELAYBITSLICE41.TX_CNTVALUEIN6
TCELL48:IMUX.IMUX.33.DELAYBITSLICE41.TX_CNTVALUEIN7
TCELL48:IMUX.IMUX.34.DELAYBITSLICE41.TX_CNTVALUEIN8
TCELL48:IMUX.IMUX.35.DELAYBITSLICE41.RX_CNTVALUEIN1
TCELL48:IMUX.IMUX.36.DELAYBITSLICE41.RX_CNTVALUEIN3
TCELL48:IMUX.IMUX.37.DELAYBITSLICE41.RX_CNTVALUEIN4
TCELL48:IMUX.IMUX.38.DELAYBITSLICE41.RX_CNTVALUEIN5
TCELL48:IMUX.IMUX.39.DELAYBITSLICE41.RX_CNTVALUEIN7
TCELL48:IMUX.IMUX.40.DELAYBITSLICE_T6.CNTVALUEIN0
TCELL48:IMUX.IMUX.41.DELAYBITSLICE_T6.CNTVALUEIN1
TCELL48:IMUX.IMUX.42.DELAYBITSLICE_T6.CNTVALUEIN2
TCELL48:IMUX.IMUX.43.DELAYBITSLICE_T6.CNTVALUEIN4
TCELL48:IMUX.IMUX.44.DELAYBITSLICE_T6.CNTVALUEIN6
TCELL48:IMUX.IMUX.45.DELAYBITSLICE_T6.CNTVALUEIN7
TCELL48:IMUX.IMUX.46.DELAYBITSLICE_T6.CNTVALUEIN8
TCELL48:IMUX.IMUX.47.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS1_0
TCELL49:OUT.0.TMINMMCM.TESTOUT0
TCELL49:OUT.1.TMINMMCM.TESTOUT1
TCELL49:OUT.2.TMINMMCM.TESTOUT2
TCELL49:OUT.3.TMINMMCM.TESTOUT3
TCELL49:OUT.4.TMINBITSLICE42.TX_CNTVALUEOUT5
TCELL49:OUT.5.TMINBITSLICE42.TX_CNTVALUEOUT6
TCELL49:OUT.6.TMINBITSLICE42.TX_CNTVALUEOUT7
TCELL49:OUT.7.TMINBITSLICE42.TX_CNTVALUEOUT8
TCELL49:OUT.8.TMINBITSLICE43.TX_T_OUT
TCELL49:OUT.9.TMINBITSLICE42.RX_CNTVALUEOUT0
TCELL49:OUT.10.TMINBITSLICE42.RX_CNTVALUEOUT1
TCELL49:OUT.11.TMINBITSLICE42.RX_CNTVALUEOUT2
TCELL49:OUT.12.TMINBITSLICE42.RX_CNTVALUEOUT3
TCELL49:OUT.13.TMINBITSLICE42.RX_CNTVALUEOUT4
TCELL49:OUT.14.TMINBITSLICE42.RX_CNTVALUEOUT5
TCELL49:OUT.15.TMINBITSLICE42.RX_CNTVALUEOUT6
TCELL49:OUT.16.TMINBITSLICE42.RX_CNTVALUEOUT7
TCELL49:OUT.17.TMINBITSLICE42.RX_CNTVALUEOUT8
TCELL49:OUT.18.TMINBITSLICE43.PHY2CLB_FIFO_EMPTY
TCELL49:OUT.19.TMINBITSLICE43.RX_Q0
TCELL49:OUT.20.TMINBITSLICE43.RX_Q1
TCELL49:OUT.21.TMINBITSLICE43.RX_Q2
TCELL49:OUT.22.TMINBITSLICE43.RX_Q3
TCELL49:OUT.23.TMINBITSLICE43.RX_Q4
TCELL49:OUT.24.TMINBITSLICE43.RX_Q5
TCELL49:OUT.25.TMINBITSLICE43.RX_Q6
TCELL49:OUT.26.TMINBITSLICE43.RX_Q7
TCELL49:OUT.27.TMINBITSLICE43.TX_CNTVALUEOUT0
TCELL49:OUT.28.TMINBITSLICE43.TX_CNTVALUEOUT1
TCELL49:OUT.29.TMINBITSLICE43.TX_CNTVALUEOUT2
TCELL49:OUT.30.TMINBITSLICE43.TX_CNTVALUEOUT3
TCELL49:OUT.31.TMINBITSLICE43.TX_CNTVALUEOUT4
TCELL49:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.TXBIT_RST_B3
TCELL49:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.RXBIT_RST_B3
TCELL49:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.ODELAY_RST_B3
TCELL49:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.IDELAY_RST_B3
TCELL49:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK3
TCELL49:IMUX.BYP.0MMCM.DADDR4
TCELL49:IMUX.BYP.1MMCM.DADDR5
TCELL49:IMUX.BYP.2MMCM.DADDR6
TCELL49:IMUX.BYP.6BITSLICE42.RX_LD
TCELL49:IMUX.BYP.7BITSLICE42.RX_INC
TCELL49:IMUX.BYP.8BITSLICE42.RX_EN_VTC
TCELL49:IMUX.BYP.9BITSLICE42.RX_CE_IDELAY
TCELL49:IMUX.BYP.10BITSLICE42.DYN_DCI_OUT_INT
TCELL49:IMUX.BYP.11BITSLICE43.TX_LD
TCELL49:IMUX.BYP.12BITSLICE43.TX_INC
TCELL49:IMUX.BYP.13BITSLICE43.TX_EN_VTC
TCELL49:IMUX.BYP.14BITSLICE43.TX_CE_ODELAY
TCELL49:IMUX.BYP.15BITSLICE43.RX_LD
TCELL49:IMUX.IMUX.0.DELAYMMCM.SCANIN
TCELL49:IMUX.IMUX.6.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS1_1
TCELL49:IMUX.IMUX.7.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS1_3
TCELL49:IMUX.IMUX.8.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS0_3
TCELL49:IMUX.IMUX.9.DELAYBITSLICE42.TX_CE_OFD
TCELL49:IMUX.IMUX.10.DELAYBITSLICE42.TX_D0
TCELL49:IMUX.IMUX.11.DELAYBITSLICE42.TX_D2
TCELL49:IMUX.IMUX.12.DELAYBITSLICE42.TX_D6
TCELL49:IMUX.IMUX.13.DELAYBITSLICE42.TX_D7
TCELL49:IMUX.IMUX.14.DELAYBITSLICE42.TX_CNTVALUEIN3
TCELL49:IMUX.IMUX.15.DELAYBITSLICE42.TX_CNTVALUEIN5
TCELL49:IMUX.IMUX.16.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS1_2
TCELL49:IMUX.IMUX.17.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS1_3
TCELL49:IMUX.IMUX.18.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS0_0
TCELL49:IMUX.IMUX.19.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS0_1
TCELL49:IMUX.IMUX.20.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS0_2
TCELL49:IMUX.IMUX.21.DELAYBITSLICE_CONTROL6.CLB2PHY_WRCS0_3
TCELL49:IMUX.IMUX.22.DELAYBITSLICE_CONTROL6.CLB2PHY_T_B0
TCELL49:IMUX.IMUX.23.DELAYBITSLICE_CONTROL6.CLB2PHY_T_B1
TCELL49:IMUX.IMUX.24.DELAYBITSLICE_CONTROL6.CLB2PHY_T_B2
TCELL49:IMUX.IMUX.25.DELAYBITSLICE_CONTROL6.CLB2PHY_T_B3
TCELL49:IMUX.IMUX.26.DELAYBITSLICE_CONTROL6.CLB2PHY_RDEN0
TCELL49:IMUX.IMUX.27.DELAYBITSLICE_CONTROL6.CLB2PHY_RDEN1
TCELL49:IMUX.IMUX.28.DELAYBITSLICE_CONTROL6.CLB2PHY_RDEN2
TCELL49:IMUX.IMUX.29.DELAYBITSLICE_CONTROL6.CLB2PHY_RDEN3
TCELL49:IMUX.IMUX.30.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS1_0
TCELL49:IMUX.IMUX.31.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS1_2
TCELL49:IMUX.IMUX.32.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS0_0
TCELL49:IMUX.IMUX.33.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS0_1
TCELL49:IMUX.IMUX.34.DELAYBITSLICE_CONTROL6.CLB2PHY_RDCS0_2
TCELL49:IMUX.IMUX.35.DELAYBITSLICE42.TX_T
TCELL49:IMUX.IMUX.36.DELAYBITSLICE42.RX_CE_IFD
TCELL49:IMUX.IMUX.37.DELAYBITSLICE42.RX_DATAIN1
TCELL49:IMUX.IMUX.38.DELAYBITSLICE42.CLB2PHY_FIFO_RDEN
TCELL49:IMUX.IMUX.39.DELAYBITSLICE42.TX_D1
TCELL49:IMUX.IMUX.40.DELAYBITSLICE42.TX_D3
TCELL49:IMUX.IMUX.41.DELAYBITSLICE42.TX_D4
TCELL49:IMUX.IMUX.42.DELAYBITSLICE42.TX_D5
TCELL49:IMUX.IMUX.44.DELAYBITSLICE42.TX_CNTVALUEIN0
TCELL49:IMUX.IMUX.45.DELAYBITSLICE42.TX_CNTVALUEIN1
TCELL49:IMUX.IMUX.46.DELAYBITSLICE42.TX_CNTVALUEIN2
TCELL49:IMUX.IMUX.47.DELAYBITSLICE42.TX_CNTVALUEIN4
TCELL50:OUT.0.TMINMMCM.DOUT12
TCELL50:OUT.1.TMINMMCM.DOUT13
TCELL50:OUT.2.TMINMMCM.DOUT14
TCELL50:OUT.3.TMINMMCM.DOUT15
TCELL50:OUT.4.TMINBITSLICE43.TX_CNTVALUEOUT5
TCELL50:OUT.5.TMINBITSLICE43.TX_CNTVALUEOUT6
TCELL50:OUT.6.TMINBITSLICE43.TX_CNTVALUEOUT7
TCELL50:OUT.7.TMINBITSLICE43.TX_CNTVALUEOUT8
TCELL50:OUT.8.TMINBITSLICE44.TX_T_OUT
TCELL50:OUT.9.TMINBITSLICE43.RX_CNTVALUEOUT0
TCELL50:OUT.10.TMINBITSLICE43.RX_CNTVALUEOUT1
TCELL50:OUT.11.TMINBITSLICE43.RX_CNTVALUEOUT2
TCELL50:OUT.12.TMINBITSLICE43.RX_CNTVALUEOUT3
TCELL50:OUT.13.TMINBITSLICE43.RX_CNTVALUEOUT4
TCELL50:OUT.14.TMINBITSLICE43.RX_CNTVALUEOUT5
TCELL50:OUT.15.TMINBITSLICE43.RX_CNTVALUEOUT6
TCELL50:OUT.16.TMINBITSLICE43.RX_CNTVALUEOUT7
TCELL50:OUT.17.TMINBITSLICE43.RX_CNTVALUEOUT8
TCELL50:OUT.18.TMINBITSLICE44.PHY2CLB_FIFO_EMPTY
TCELL50:OUT.19.TMINBITSLICE44.RX_Q0
TCELL50:OUT.20.TMINBITSLICE44.RX_Q1
TCELL50:OUT.21.TMINBITSLICE44.RX_Q2
TCELL50:OUT.22.TMINBITSLICE44.RX_Q3
TCELL50:OUT.23.TMINBITSLICE44.RX_Q4
TCELL50:OUT.24.TMINBITSLICE44.RX_Q5
TCELL50:OUT.25.TMINBITSLICE44.RX_Q6
TCELL50:OUT.26.TMINBITSLICE44.RX_Q7
TCELL50:OUT.27.TMINBITSLICE44.TX_CNTVALUEOUT0
TCELL50:OUT.28.TMINBITSLICE44.TX_CNTVALUEOUT1
TCELL50:OUT.29.TMINBITSLICE44.TX_CNTVALUEOUT2
TCELL50:OUT.30.TMINBITSLICE44.TX_CNTVALUEOUT3
TCELL50:OUT.31.TMINBITSLICE44.TX_CNTVALUEOUT4
TCELL50:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.TXBIT_RST_B4
TCELL50:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.RXBIT_RST_B4
TCELL50:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.ODELAY_RST_B4
TCELL50:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.IDELAY_RST_B4
TCELL50:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK4
TCELL50:IMUX.BYP.0MMCM.DADDR0
TCELL50:IMUX.BYP.1MMCM.DADDR1
TCELL50:IMUX.BYP.2MMCM.DADDR2
TCELL50:IMUX.BYP.3MMCM.DADDR3
TCELL50:IMUX.BYP.6BITSLICE43.RX_INC
TCELL50:IMUX.BYP.7BITSLICE43.RX_EN_VTC
TCELL50:IMUX.BYP.8BITSLICE43.RX_CE_IDELAY
TCELL50:IMUX.BYP.9BITSLICE43.DYN_DCI_OUT_INT
TCELL50:IMUX.BYP.10BITSLICE44.TX_LD
TCELL50:IMUX.BYP.11BITSLICE44.TX_INC
TCELL50:IMUX.BYP.12BITSLICE44.TX_EN_VTC
TCELL50:IMUX.BYP.13BITSLICE44.TX_CE_ODELAY
TCELL50:IMUX.BYP.14BITSLICE44.RX_LD
TCELL50:IMUX.BYP.15BITSLICE44.RX_INC
TCELL50:IMUX.IMUX.0.DELAYMMCM.CDDCREQ
TCELL50:IMUX.IMUX.6.DELAYBITSLICE43.RX_DATAIN1
TCELL50:IMUX.IMUX.7.DELAYBITSLICE43.TX_D0
TCELL50:IMUX.IMUX.8.DELAYBITSLICE43.TX_D4
TCELL50:IMUX.IMUX.9.DELAYBITSLICE43.TX_D6
TCELL50:IMUX.IMUX.10.DELAYBITSLICE43.TX_CNTVALUEIN2
TCELL50:IMUX.IMUX.11.DELAYBITSLICE43.TX_CNTVALUEIN4
TCELL50:IMUX.IMUX.12.DELAYBITSLICE43.TX_CNTVALUEIN8
TCELL50:IMUX.IMUX.13.DELAYBITSLICE43.RX_CNTVALUEIN1
TCELL50:IMUX.IMUX.14.DELAYBITSLICE43.RX_CNTVALUEIN5
TCELL50:IMUX.IMUX.15.DELAYBITSLICE43.RX_CNTVALUEIN7
TCELL50:IMUX.IMUX.16.DELAYBITSLICE42.TX_CNTVALUEIN6
TCELL50:IMUX.IMUX.17.DELAYBITSLICE42.TX_CNTVALUEIN7
TCELL50:IMUX.IMUX.18.DELAYBITSLICE42.TX_CNTVALUEIN8
TCELL50:IMUX.IMUX.19.DELAYBITSLICE42.RX_CNTVALUEIN0
TCELL50:IMUX.IMUX.20.DELAYBITSLICE42.RX_CNTVALUEIN1
TCELL50:IMUX.IMUX.21.DELAYBITSLICE42.RX_CNTVALUEIN2
TCELL50:IMUX.IMUX.22.DELAYBITSLICE42.RX_CNTVALUEIN3
TCELL50:IMUX.IMUX.23.DELAYBITSLICE42.RX_CNTVALUEIN4
TCELL50:IMUX.IMUX.24.DELAYBITSLICE42.RX_CNTVALUEIN5
TCELL50:IMUX.IMUX.25.DELAYBITSLICE42.RX_CNTVALUEIN6
TCELL50:IMUX.IMUX.26.DELAYBITSLICE42.RX_CNTVALUEIN7
TCELL50:IMUX.IMUX.27.DELAYBITSLICE42.RX_CNTVALUEIN8
TCELL50:IMUX.IMUX.28.DELAYBITSLICE43.TX_T
TCELL50:IMUX.IMUX.29.DELAYBITSLICE43.TX_CE_OFD
TCELL50:IMUX.IMUX.30.DELAYBITSLICE43.RX_CE_IFD
TCELL50:IMUX.IMUX.31.DELAYBITSLICE43.CLB2PHY_FIFO_RDEN
TCELL50:IMUX.IMUX.32.DELAYBITSLICE43.TX_D1
TCELL50:IMUX.IMUX.33.DELAYBITSLICE43.TX_D2
TCELL50:IMUX.IMUX.34.DELAYBITSLICE43.TX_D3
TCELL50:IMUX.IMUX.35.DELAYBITSLICE43.TX_D5
TCELL50:IMUX.IMUX.36.DELAYBITSLICE43.TX_D7
TCELL50:IMUX.IMUX.37.DELAYBITSLICE43.TX_CNTVALUEIN0
TCELL50:IMUX.IMUX.38.DELAYBITSLICE43.TX_CNTVALUEIN1
TCELL50:IMUX.IMUX.39.DELAYBITSLICE43.TX_CNTVALUEIN3
TCELL50:IMUX.IMUX.40.DELAYBITSLICE43.TX_CNTVALUEIN5
TCELL50:IMUX.IMUX.41.DELAYBITSLICE43.TX_CNTVALUEIN6
TCELL50:IMUX.IMUX.42.DELAYBITSLICE43.TX_CNTVALUEIN7
TCELL50:IMUX.IMUX.43.DELAYBITSLICE43.RX_CNTVALUEIN0
TCELL50:IMUX.IMUX.44.DELAYBITSLICE43.RX_CNTVALUEIN2
TCELL50:IMUX.IMUX.45.DELAYBITSLICE43.RX_CNTVALUEIN3
TCELL50:IMUX.IMUX.46.DELAYBITSLICE43.RX_CNTVALUEIN4
TCELL50:IMUX.IMUX.47.DELAYBITSLICE43.RX_CNTVALUEIN6
TCELL51:OUT.0.TMINMMCM.DOUT8
TCELL51:OUT.1.TMINMMCM.DOUT9
TCELL51:OUT.2.TMINMMCM.DOUT10
TCELL51:OUT.3.TMINMMCM.DOUT11
TCELL51:OUT.4.TMINBITSLICE44.TX_CNTVALUEOUT5
TCELL51:OUT.5.TMINBITSLICE44.TX_CNTVALUEOUT6
TCELL51:OUT.6.TMINBITSLICE44.TX_CNTVALUEOUT7
TCELL51:OUT.7.TMINBITSLICE44.TX_CNTVALUEOUT8
TCELL51:OUT.8.TMINBITSLICE45.TX_T_OUT
TCELL51:OUT.9.TMINBITSLICE44.RX_CNTVALUEOUT0
TCELL51:OUT.10.TMINBITSLICE44.RX_CNTVALUEOUT1
TCELL51:OUT.11.TMINBITSLICE44.RX_CNTVALUEOUT2
TCELL51:OUT.12.TMINBITSLICE44.RX_CNTVALUEOUT3
TCELL51:OUT.13.TMINBITSLICE44.RX_CNTVALUEOUT4
TCELL51:OUT.14.TMINBITSLICE44.RX_CNTVALUEOUT5
TCELL51:OUT.15.TMINBITSLICE44.RX_CNTVALUEOUT6
TCELL51:OUT.16.TMINBITSLICE44.RX_CNTVALUEOUT7
TCELL51:OUT.17.TMINBITSLICE44.RX_CNTVALUEOUT8
TCELL51:OUT.18.TMINRIU_OR3.RIU_RD_VALID
TCELL51:OUT.19.TMINRIU_OR3.RIU_RD_DATA0
TCELL51:OUT.20.TMINRIU_OR3.RIU_RD_DATA1
TCELL51:OUT.21.TMINRIU_OR3.RIU_RD_DATA2
TCELL51:OUT.22.TMINRIU_OR3.RIU_RD_DATA3
TCELL51:OUT.23.TMINRIU_OR3.RIU_RD_DATA4
TCELL51:OUT.24.TMINRIU_OR3.RIU_RD_DATA5
TCELL51:OUT.25.TMINRIU_OR3.RIU_RD_DATA6
TCELL51:OUT.26.TMINRIU_OR3.RIU_RD_DATA7
TCELL51:OUT.27.TMINRIU_OR3.RIU_RD_DATA8
TCELL51:OUT.28.TMINRIU_OR3.RIU_RD_DATA9
TCELL51:OUT.29.TMINRIU_OR3.RIU_RD_DATA10
TCELL51:OUT.30.TMINRIU_OR3.RIU_RD_DATA11
TCELL51:OUT.31.TMINRIU_OR3.RIU_RD_DATA12
TCELL51:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.TXBIT_RST_B5
TCELL51:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.RXBIT_RST_B5
TCELL51:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.ODELAY_RST_B5
TCELL51:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.IDELAY_RST_B5
TCELL51:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK5
TCELL51:IMUX.BYP.0MMCM.DI12
TCELL51:IMUX.BYP.1MMCM.DI13
TCELL51:IMUX.BYP.2MMCM.DI14
TCELL51:IMUX.BYP.3MMCM.DI15
TCELL51:IMUX.BYP.6BITSLICE44.RX_EN_VTC
TCELL51:IMUX.BYP.7BITSLICE44.RX_CE_IDELAY
TCELL51:IMUX.BYP.8BITSLICE44.DYN_DCI_OUT_INT
TCELL51:IMUX.BYP.9XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B0
TCELL51:IMUX.BYP.10XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B1
TCELL51:IMUX.BYP.11XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B2
TCELL51:IMUX.BYP.12XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B3
TCELL51:IMUX.BYP.13XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_RST_MASK_B
TCELL51:IMUX.BYP.14XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_MODE_B
TCELL51:IMUX.BYP.15XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN0
TCELL51:IMUX.IMUX.0.DELAYMMCM.DWE
TCELL51:IMUX.IMUX.6.DELAYBITSLICE44.TX_CNTVALUEIN1
TCELL51:IMUX.IMUX.7.DELAYBITSLICE44.TX_CNTVALUEIN3
TCELL51:IMUX.IMUX.8.DELAYBITSLICE44.TX_CNTVALUEIN7
TCELL51:IMUX.IMUX.10.DELAYBITSLICE44.RX_CNTVALUEIN3
TCELL51:IMUX.IMUX.11.DELAYBITSLICE44.RX_CNTVALUEIN5
TCELL51:IMUX.IMUX.12.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_EN, BITSLICE_CONTROL7.CLB2RIU_WR_EN
TCELL51:IMUX.IMUX.13.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA1, BITSLICE_CONTROL7.CLB2RIU_WR_DATA1
TCELL51:IMUX.IMUX.14.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA5, BITSLICE_CONTROL7.CLB2RIU_WR_DATA5
TCELL51:IMUX.IMUX.15.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA7, BITSLICE_CONTROL7.CLB2RIU_WR_DATA7
TCELL51:IMUX.IMUX.16.DELAYBITSLICE43.RX_CNTVALUEIN8
TCELL51:IMUX.IMUX.17.DELAYBITSLICE44.TX_T
TCELL51:IMUX.IMUX.18.DELAYBITSLICE44.TX_CE_OFD
TCELL51:IMUX.IMUX.19.DELAYBITSLICE44.RX_CE_IFD
TCELL51:IMUX.IMUX.20.DELAYBITSLICE44.RX_DATAIN1
TCELL51:IMUX.IMUX.21.DELAYBITSLICE44.CLB2PHY_FIFO_RDEN
TCELL51:IMUX.IMUX.22.DELAYBITSLICE44.TX_D0
TCELL51:IMUX.IMUX.23.DELAYBITSLICE44.TX_D1
TCELL51:IMUX.IMUX.24.DELAYBITSLICE44.TX_D2
TCELL51:IMUX.IMUX.25.DELAYBITSLICE44.TX_D3
TCELL51:IMUX.IMUX.26.DELAYBITSLICE44.TX_D4
TCELL51:IMUX.IMUX.27.DELAYBITSLICE44.TX_D5
TCELL51:IMUX.IMUX.28.DELAYBITSLICE44.TX_D6
TCELL51:IMUX.IMUX.29.DELAYBITSLICE44.TX_D7
TCELL51:IMUX.IMUX.30.DELAYBITSLICE44.TX_CNTVALUEIN0
TCELL51:IMUX.IMUX.31.DELAYBITSLICE44.TX_CNTVALUEIN2
TCELL51:IMUX.IMUX.32.DELAYBITSLICE44.TX_CNTVALUEIN4
TCELL51:IMUX.IMUX.33.DELAYBITSLICE44.TX_CNTVALUEIN5
TCELL51:IMUX.IMUX.34.DELAYBITSLICE44.TX_CNTVALUEIN6
TCELL51:IMUX.IMUX.35.DELAYBITSLICE44.TX_CNTVALUEIN8
TCELL51:IMUX.IMUX.36.DELAYBITSLICE44.RX_CNTVALUEIN0
TCELL51:IMUX.IMUX.37.DELAYBITSLICE44.RX_CNTVALUEIN1
TCELL51:IMUX.IMUX.38.DELAYBITSLICE44.RX_CNTVALUEIN2
TCELL51:IMUX.IMUX.39.DELAYBITSLICE44.RX_CNTVALUEIN4
TCELL51:IMUX.IMUX.40.DELAYBITSLICE44.RX_CNTVALUEIN6
TCELL51:IMUX.IMUX.41.DELAYBITSLICE44.RX_CNTVALUEIN7
TCELL51:IMUX.IMUX.42.DELAYBITSLICE44.RX_CNTVALUEIN8
TCELL51:IMUX.IMUX.43.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA0, BITSLICE_CONTROL7.CLB2RIU_WR_DATA0
TCELL51:IMUX.IMUX.44.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA2, BITSLICE_CONTROL7.CLB2RIU_WR_DATA2
TCELL51:IMUX.IMUX.45.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA3, BITSLICE_CONTROL7.CLB2RIU_WR_DATA3
TCELL51:IMUX.IMUX.46.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA4, BITSLICE_CONTROL7.CLB2RIU_WR_DATA4
TCELL51:IMUX.IMUX.47.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA6, BITSLICE_CONTROL7.CLB2RIU_WR_DATA6
TCELL52:OUT.0.TMINMMCM.DOUT4
TCELL52:OUT.1.TMINMMCM.DOUT5
TCELL52:OUT.2.TMINMMCM.DOUT6
TCELL52:OUT.3.TMINMMCM.DOUT7
TCELL52:OUT.4.TMINRIU_OR3.RIU_RD_DATA13
TCELL52:OUT.5.TMINRIU_OR3.RIU_RD_DATA14
TCELL52:OUT.6.TMINRIU_OR3.RIU_RD_DATA15
TCELL52:OUT.7.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT0
TCELL52:OUT.8.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT1
TCELL52:OUT.9.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT2
TCELL52:OUT.10.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT3
TCELL52:OUT.11.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT4
TCELL52:OUT.12.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT5
TCELL52:OUT.13.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT6
TCELL52:OUT.14.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT7
TCELL52:OUT.15.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_OUT
TCELL52:OUT.16.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_FLG_OUT
TCELL52:OUT.17.TMINXIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
TCELL52:OUT.18.TMINBITSLICE51.PHY2CLB_FIFO_EMPTY
TCELL52:OUT.19.TMINBITSLICE51.RX_Q0
TCELL52:OUT.20.TMINBITSLICE51.RX_Q1
TCELL52:OUT.21.TMINBITSLICE51.RX_Q2
TCELL52:OUT.22.TMINBITSLICE51.RX_Q3
TCELL52:OUT.23.TMINBITSLICE51.RX_Q4
TCELL52:OUT.24.TMINBITSLICE51.RX_Q5
TCELL52:OUT.25.TMINBITSLICE51.RX_Q6
TCELL52:OUT.26.TMINBITSLICE51.RX_Q7
TCELL52:OUT.27.TMINBITSLICE51.TX_CNTVALUEOUT0
TCELL52:OUT.28.TMINBITSLICE51.TX_CNTVALUEOUT1
TCELL52:OUT.29.TMINBITSLICE51.TX_CNTVALUEOUT2
TCELL52:OUT.30.TMINBITSLICE51.TX_CNTVALUEOUT3
TCELL52:OUT.31.TMINBITSLICE51.TX_CNTVALUEOUT4
TCELL52:IMUX.CTRL.0MMCM.DCLK_B
TCELL52:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_SDR
TCELL52:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_DIV4
TCELL52:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_DIV2
TCELL52:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.TXBIT_RST_B12
TCELL52:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.RXBIT_RST_B12
TCELL52:IMUX.BYP.0MMCM.DI8
TCELL52:IMUX.BYP.1MMCM.DI9
TCELL52:IMUX.BYP.2MMCM.DI10
TCELL52:IMUX.BYP.3MMCM.DI11
TCELL52:IMUX.BYP.6XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN1
TCELL52:IMUX.BYP.7XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN2
TCELL52:IMUX.BYP.8XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN3
TCELL52:IMUX.BYP.10XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN4
TCELL52:IMUX.BYP.11XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN5
TCELL52:IMUX.BYP.12XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN6
TCELL52:IMUX.BYP.13XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN7
TCELL52:IMUX.BYP.14XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_EN_B
TCELL52:IMUX.BYP.15BITSLICE51.TX_LD
TCELL52:IMUX.IMUX.0.DELAYMMCM.DEN
TCELL52:IMUX.IMUX.6.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_TEST_DIV4_CLK_SEL_B
TCELL52:IMUX.IMUX.7.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CT_START_EN
TCELL52:IMUX.IMUX.8.DELAYBITSLICE51.TX_CE_OFD
TCELL52:IMUX.IMUX.9.DELAYBITSLICE51.RX_DATAIN1
TCELL52:IMUX.IMUX.10.DELAYBITSLICE51.TX_D2
TCELL52:IMUX.IMUX.11.DELAYBITSLICE51.TX_D4
TCELL52:IMUX.IMUX.12.DELAYBITSLICE51.TX_CNTVALUEIN0
TCELL52:IMUX.IMUX.13.DELAYBITSLICE51.TX_CNTVALUEIN2
TCELL52:IMUX.IMUX.14.DELAYBITSLICE51.TX_CNTVALUEIN6
TCELL52:IMUX.IMUX.15.DELAYBITSLICE51.TX_CNTVALUEIN8
TCELL52:IMUX.IMUX.16.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA8, BITSLICE_CONTROL7.CLB2RIU_WR_DATA8
TCELL52:IMUX.IMUX.17.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA9, BITSLICE_CONTROL7.CLB2RIU_WR_DATA9
TCELL52:IMUX.IMUX.18.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA10, BITSLICE_CONTROL7.CLB2RIU_WR_DATA10
TCELL52:IMUX.IMUX.19.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA11, BITSLICE_CONTROL7.CLB2RIU_WR_DATA11
TCELL52:IMUX.IMUX.20.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA12, BITSLICE_CONTROL7.CLB2RIU_WR_DATA12
TCELL52:IMUX.IMUX.21.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA13, BITSLICE_CONTROL7.CLB2RIU_WR_DATA13
TCELL52:IMUX.IMUX.22.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA14, BITSLICE_CONTROL7.CLB2RIU_WR_DATA14
TCELL52:IMUX.IMUX.23.DELAYBITSLICE_CONTROL6.CLB2RIU_WR_DATA15, BITSLICE_CONTROL7.CLB2RIU_WR_DATA15
TCELL52:IMUX.IMUX.24.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR0, BITSLICE_CONTROL7.CLB2RIU_ADDR0
TCELL52:IMUX.IMUX.25.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR1, BITSLICE_CONTROL7.CLB2RIU_ADDR1
TCELL52:IMUX.IMUX.26.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR2, BITSLICE_CONTROL7.CLB2RIU_ADDR2
TCELL52:IMUX.IMUX.27.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR3, BITSLICE_CONTROL7.CLB2RIU_ADDR3
TCELL52:IMUX.IMUX.28.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR4, BITSLICE_CONTROL7.CLB2RIU_ADDR4
TCELL52:IMUX.IMUX.29.DELAYBITSLICE_CONTROL6.CLB2RIU_ADDR5, BITSLICE_CONTROL7.CLB2RIU_ADDR5
TCELL52:IMUX.IMUX.30.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SDR_CLK_SEL_B
TCELL52:IMUX.IMUX.31.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_TEST_DIV2_CLK_SEL_B
TCELL52:IMUX.IMUX.32.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CLK_STOP_FLG_OUT
TCELL52:IMUX.IMUX.33.DELAYXIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
TCELL52:IMUX.IMUX.34.DELAYBITSLICE51.TX_T
TCELL52:IMUX.IMUX.35.DELAYBITSLICE51.RX_CE_IFD
TCELL52:IMUX.IMUX.36.DELAYBITSLICE51.CLB2PHY_FIFO_RDEN
TCELL52:IMUX.IMUX.37.DELAYBITSLICE51.TX_D0
TCELL52:IMUX.IMUX.38.DELAYBITSLICE51.TX_D1
TCELL52:IMUX.IMUX.39.DELAYBITSLICE51.TX_D3
TCELL52:IMUX.IMUX.40.DELAYBITSLICE51.TX_D5
TCELL52:IMUX.IMUX.41.DELAYBITSLICE51.TX_D6
TCELL52:IMUX.IMUX.42.DELAYBITSLICE51.TX_D7
TCELL52:IMUX.IMUX.43.DELAYBITSLICE51.TX_CNTVALUEIN1
TCELL52:IMUX.IMUX.44.DELAYBITSLICE51.TX_CNTVALUEIN3
TCELL52:IMUX.IMUX.45.DELAYBITSLICE51.TX_CNTVALUEIN4
TCELL52:IMUX.IMUX.46.DELAYBITSLICE51.TX_CNTVALUEIN5
TCELL52:IMUX.IMUX.47.DELAYBITSLICE51.TX_CNTVALUEIN7
TCELL53:OUT.0.TMINMMCM.DOUT0
TCELL53:OUT.1.TMINMMCM.DOUT1
TCELL53:OUT.2.TMINMMCM.DOUT2
TCELL53:OUT.3.TMINMMCM.DOUT3
TCELL53:OUT.4.TMINBITSLICE51.TX_CNTVALUEOUT5
TCELL53:OUT.5.TMINBITSLICE51.TX_CNTVALUEOUT6
TCELL53:OUT.6.TMINBITSLICE51.TX_CNTVALUEOUT7
TCELL53:OUT.7.TMINBITSLICE51.TX_CNTVALUEOUT8
TCELL53:OUT.8.TMINBITSLICE46.TX_T_OUT
TCELL53:OUT.9.TMINBITSLICE51.RX_CNTVALUEOUT0
TCELL53:OUT.10.TMINBITSLICE51.RX_CNTVALUEOUT1
TCELL53:OUT.11.TMINBITSLICE51.RX_CNTVALUEOUT2
TCELL53:OUT.12.TMINBITSLICE51.RX_CNTVALUEOUT3
TCELL53:OUT.13.TMINBITSLICE51.RX_CNTVALUEOUT4
TCELL53:OUT.14.TMINBITSLICE51.RX_CNTVALUEOUT5
TCELL53:OUT.15.TMINBITSLICE51.RX_CNTVALUEOUT6
TCELL53:OUT.16.TMINBITSLICE51.RX_CNTVALUEOUT7
TCELL53:OUT.17.TMINBITSLICE51.RX_CNTVALUEOUT8
TCELL53:OUT.18.TMINBITSLICE45.PHY2CLB_FIFO_EMPTY
TCELL53:OUT.19.TMINBITSLICE45.RX_Q0
TCELL53:OUT.20.TMINBITSLICE45.RX_Q1
TCELL53:OUT.21.TMINBITSLICE45.RX_Q2
TCELL53:OUT.22.TMINBITSLICE45.RX_Q3
TCELL53:OUT.23.TMINBITSLICE45.RX_Q4
TCELL53:OUT.24.TMINBITSLICE45.RX_Q5
TCELL53:OUT.25.TMINBITSLICE45.RX_Q6
TCELL53:OUT.26.TMINBITSLICE45.RX_Q7
TCELL53:OUT.27.TMINBITSLICE45.TX_CNTVALUEOUT0
TCELL53:OUT.28.TMINBITSLICE45.TX_CNTVALUEOUT1
TCELL53:OUT.29.TMINBITSLICE45.TX_CNTVALUEOUT2
TCELL53:OUT.30.TMINBITSLICE45.TX_CNTVALUEOUT3
TCELL53:OUT.31.TMINBITSLICE45.TX_CNTVALUEOUT4
TCELL53:IMUX.CTRL.0MMCM.PSCLK_B
TCELL53:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.ODELAY_RST_B12
TCELL53:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.IDELAY_RST_B12
TCELL53:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK12
TCELL53:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.TXBIT_RST_B6
TCELL53:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.RXBIT_RST_B6
TCELL53:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.ODELAY_RST_B6
TCELL53:IMUX.BYP.0MMCM.DI4
TCELL53:IMUX.BYP.1MMCM.DI5
TCELL53:IMUX.BYP.2MMCM.DI6
TCELL53:IMUX.BYP.3MMCM.DI7
TCELL53:IMUX.BYP.6BITSLICE51.TX_INC
TCELL53:IMUX.BYP.7BITSLICE51.TX_EN_VTC
TCELL53:IMUX.BYP.8BITSLICE51.TX_CE_ODELAY
TCELL53:IMUX.BYP.9BITSLICE51.RX_LD
TCELL53:IMUX.BYP.10BITSLICE51.RX_INC
TCELL53:IMUX.BYP.11BITSLICE51.RX_EN_VTC
TCELL53:IMUX.BYP.12BITSLICE51.RX_CE_IDELAY
TCELL53:IMUX.BYP.13BITSLICE51.DYN_DCI_OUT_INT
TCELL53:IMUX.BYP.14BITSLICE45.TX_LD
TCELL53:IMUX.BYP.15BITSLICE45.TX_INC
TCELL53:IMUX.IMUX.0.DELAYMMCM.PWRDWN
TCELL53:IMUX.IMUX.6.DELAYBITSLICE45.TX_D0
TCELL53:IMUX.IMUX.7.DELAYBITSLICE45.TX_D2
TCELL53:IMUX.IMUX.8.DELAYBITSLICE45.TX_D6
TCELL53:IMUX.IMUX.9.DELAYBITSLICE45.TX_CNTVALUEIN0
TCELL53:IMUX.IMUX.10.DELAYBITSLICE45.TX_CNTVALUEIN4
TCELL53:IMUX.IMUX.11.DELAYBITSLICE45.TX_CNTVALUEIN6
TCELL53:IMUX.IMUX.12.DELAYBITSLICE45.RX_CNTVALUEIN1
TCELL53:IMUX.IMUX.13.DELAYBITSLICE45.RX_CNTVALUEIN3
TCELL53:IMUX.IMUX.14.DELAYBITSLICE45.RX_CNTVALUEIN7
TCELL53:IMUX.IMUX.15.DELAYBITSLICE46.TX_T
TCELL53:IMUX.IMUX.16.DELAYBITSLICE51.RX_CNTVALUEIN0
TCELL53:IMUX.IMUX.17.DELAYBITSLICE51.RX_CNTVALUEIN1
TCELL53:IMUX.IMUX.18.DELAYBITSLICE51.RX_CNTVALUEIN2
TCELL53:IMUX.IMUX.19.DELAYBITSLICE51.RX_CNTVALUEIN3
TCELL53:IMUX.IMUX.20.DELAYBITSLICE51.RX_CNTVALUEIN4
TCELL53:IMUX.IMUX.21.DELAYBITSLICE51.RX_CNTVALUEIN5
TCELL53:IMUX.IMUX.22.DELAYBITSLICE51.RX_CNTVALUEIN6
TCELL53:IMUX.IMUX.23.DELAYBITSLICE51.RX_CNTVALUEIN7
TCELL53:IMUX.IMUX.24.DELAYBITSLICE51.RX_CNTVALUEIN8
TCELL53:IMUX.IMUX.25.DELAYBITSLICE45.TX_T
TCELL53:IMUX.IMUX.26.DELAYBITSLICE45.TX_CE_OFD
TCELL53:IMUX.IMUX.27.DELAYBITSLICE45.RX_CE_IFD
TCELL53:IMUX.IMUX.29.DELAYBITSLICE45.RX_DATAIN1
TCELL53:IMUX.IMUX.30.DELAYBITSLICE45.CLB2PHY_FIFO_RDEN
TCELL53:IMUX.IMUX.31.DELAYBITSLICE45.TX_D1
TCELL53:IMUX.IMUX.32.DELAYBITSLICE45.TX_D3
TCELL53:IMUX.IMUX.33.DELAYBITSLICE45.TX_D4
TCELL53:IMUX.IMUX.34.DELAYBITSLICE45.TX_D5
TCELL53:IMUX.IMUX.35.DELAYBITSLICE45.TX_D7
TCELL53:IMUX.IMUX.36.DELAYBITSLICE45.TX_CNTVALUEIN1
TCELL53:IMUX.IMUX.37.DELAYBITSLICE45.TX_CNTVALUEIN2
TCELL53:IMUX.IMUX.38.DELAYBITSLICE45.TX_CNTVALUEIN3
TCELL53:IMUX.IMUX.39.DELAYBITSLICE45.TX_CNTVALUEIN5
TCELL53:IMUX.IMUX.40.DELAYBITSLICE45.TX_CNTVALUEIN7
TCELL53:IMUX.IMUX.41.DELAYBITSLICE45.TX_CNTVALUEIN8
TCELL53:IMUX.IMUX.42.DELAYBITSLICE45.RX_CNTVALUEIN0
TCELL53:IMUX.IMUX.43.DELAYBITSLICE45.RX_CNTVALUEIN2
TCELL53:IMUX.IMUX.44.DELAYBITSLICE45.RX_CNTVALUEIN4
TCELL53:IMUX.IMUX.45.DELAYBITSLICE45.RX_CNTVALUEIN5
TCELL53:IMUX.IMUX.46.DELAYBITSLICE45.RX_CNTVALUEIN6
TCELL53:IMUX.IMUX.47.DELAYBITSLICE45.RX_CNTVALUEIN8
TCELL54:OUT.0.TMINMMCM.DRDY
TCELL54:OUT.1.TMINMMCM.LOCKED
TCELL54:OUT.2.TMINMMCM.TESTOUT36
TCELL54:OUT.3.TMINMMCM.SCANOUT
TCELL54:OUT.4.TMINBITSLICE45.TX_CNTVALUEOUT5
TCELL54:OUT.5.TMINBITSLICE45.TX_CNTVALUEOUT6
TCELL54:OUT.6.TMINBITSLICE45.TX_CNTVALUEOUT7
TCELL54:OUT.7.TMINBITSLICE45.TX_CNTVALUEOUT8
TCELL54:OUT.8.TMINBITSLICE47.TX_T_OUT
TCELL54:OUT.9.TMINBITSLICE45.RX_CNTVALUEOUT0
TCELL54:OUT.10.TMINBITSLICE45.RX_CNTVALUEOUT1
TCELL54:OUT.11.TMINBITSLICE45.RX_CNTVALUEOUT2
TCELL54:OUT.12.TMINBITSLICE45.RX_CNTVALUEOUT3
TCELL54:OUT.13.TMINBITSLICE45.RX_CNTVALUEOUT4
TCELL54:OUT.14.TMINBITSLICE45.RX_CNTVALUEOUT5
TCELL54:OUT.15.TMINBITSLICE45.RX_CNTVALUEOUT6
TCELL54:OUT.16.TMINBITSLICE45.RX_CNTVALUEOUT7
TCELL54:OUT.17.TMINBITSLICE45.RX_CNTVALUEOUT8
TCELL54:OUT.18.TMINBITSLICE46.PHY2CLB_FIFO_EMPTY
TCELL54:OUT.19.TMINBITSLICE46.RX_Q0
TCELL54:OUT.20.TMINBITSLICE46.RX_Q1
TCELL54:OUT.21.TMINBITSLICE46.RX_Q2
TCELL54:OUT.22.TMINBITSLICE46.RX_Q3
TCELL54:OUT.23.TMINBITSLICE46.RX_Q4
TCELL54:OUT.24.TMINBITSLICE46.RX_Q5
TCELL54:OUT.25.TMINBITSLICE46.RX_Q6
TCELL54:OUT.26.TMINBITSLICE46.RX_Q7
TCELL54:OUT.27.TMINBITSLICE46.TX_CNTVALUEOUT0
TCELL54:OUT.28.TMINBITSLICE46.TX_CNTVALUEOUT1
TCELL54:OUT.29.TMINBITSLICE46.TX_CNTVALUEOUT2
TCELL54:OUT.30.TMINBITSLICE46.TX_CNTVALUEOUT3
TCELL54:OUT.31.TMINBITSLICE46.TX_CNTVALUEOUT4
TCELL54:IMUX.CTRL.0MMCM.SCANCLK_B
TCELL54:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.IDELAY_RST_B6
TCELL54:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK6
TCELL54:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.TXBIT_RST_B7
TCELL54:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.RXBIT_RST_B7
TCELL54:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.ODELAY_RST_B7
TCELL54:IMUX.BYP.0MMCM.DI0
TCELL54:IMUX.BYP.1MMCM.DI1
TCELL54:IMUX.BYP.2MMCM.DI2
TCELL54:IMUX.BYP.3MMCM.DI3
TCELL54:IMUX.BYP.6BITSLICE45.TX_EN_VTC
TCELL54:IMUX.BYP.7BITSLICE45.TX_CE_ODELAY
TCELL54:IMUX.BYP.8BITSLICE45.RX_LD
TCELL54:IMUX.BYP.9BITSLICE45.RX_INC
TCELL54:IMUX.BYP.10BITSLICE45.RX_EN_VTC
TCELL54:IMUX.BYP.11BITSLICE45.RX_CE_IDELAY
TCELL54:IMUX.BYP.12BITSLICE45.DYN_DCI_OUT_INT
TCELL54:IMUX.BYP.14BITSLICE46.TX_LD
TCELL54:IMUX.BYP.15BITSLICE46.TX_INC
TCELL54:IMUX.IMUX.0.DELAYMMCM.RST
TCELL54:IMUX.IMUX.6.DELAYBITSLICE46.TX_CNTVALUEIN3
TCELL54:IMUX.IMUX.7.DELAYBITSLICE46.TX_CNTVALUEIN5
TCELL54:IMUX.IMUX.8.DELAYBITSLICE46.RX_CNTVALUEIN0
TCELL54:IMUX.IMUX.9.DELAYBITSLICE46.RX_CNTVALUEIN2
TCELL54:IMUX.IMUX.10.DELAYBITSLICE46.RX_CNTVALUEIN6
TCELL54:IMUX.IMUX.11.DELAYBITSLICE46.RX_CNTVALUEIN8
TCELL54:IMUX.IMUX.12.DELAYBITSLICE47.RX_DATAIN1
TCELL54:IMUX.IMUX.13.DELAYBITSLICE47.TX_D0
TCELL54:IMUX.IMUX.14.DELAYBITSLICE47.TX_D4
TCELL54:IMUX.IMUX.15.DELAYBITSLICE47.TX_D6
TCELL54:IMUX.IMUX.16.DELAYBITSLICE46.TX_CE_OFD
TCELL54:IMUX.IMUX.17.DELAYBITSLICE46.RX_CE_IFD
TCELL54:IMUX.IMUX.18.DELAYBITSLICE46.RX_DATAIN1
TCELL54:IMUX.IMUX.19.DELAYBITSLICE46.CLB2PHY_FIFO_RDEN
TCELL54:IMUX.IMUX.20.DELAYBITSLICE46.TX_D0
TCELL54:IMUX.IMUX.21.DELAYBITSLICE46.TX_D1
TCELL54:IMUX.IMUX.22.DELAYBITSLICE46.TX_D2
TCELL54:IMUX.IMUX.23.DELAYBITSLICE46.TX_D3
TCELL54:IMUX.IMUX.24.DELAYBITSLICE46.TX_D4
TCELL54:IMUX.IMUX.25.DELAYBITSLICE46.TX_D5
TCELL54:IMUX.IMUX.26.DELAYBITSLICE46.TX_D6
TCELL54:IMUX.IMUX.27.DELAYBITSLICE46.TX_D7
TCELL54:IMUX.IMUX.28.DELAYBITSLICE46.TX_CNTVALUEIN0
TCELL54:IMUX.IMUX.29.DELAYBITSLICE46.TX_CNTVALUEIN1
TCELL54:IMUX.IMUX.30.DELAYBITSLICE46.TX_CNTVALUEIN2
TCELL54:IMUX.IMUX.31.DELAYBITSLICE46.TX_CNTVALUEIN4
TCELL54:IMUX.IMUX.32.DELAYBITSLICE46.TX_CNTVALUEIN6
TCELL54:IMUX.IMUX.33.DELAYBITSLICE46.TX_CNTVALUEIN7
TCELL54:IMUX.IMUX.34.DELAYBITSLICE46.TX_CNTVALUEIN8
TCELL54:IMUX.IMUX.35.DELAYBITSLICE46.RX_CNTVALUEIN1
TCELL54:IMUX.IMUX.36.DELAYBITSLICE46.RX_CNTVALUEIN3
TCELL54:IMUX.IMUX.37.DELAYBITSLICE46.RX_CNTVALUEIN4
TCELL54:IMUX.IMUX.38.DELAYBITSLICE46.RX_CNTVALUEIN5
TCELL54:IMUX.IMUX.39.DELAYBITSLICE46.RX_CNTVALUEIN7
TCELL54:IMUX.IMUX.40.DELAYBITSLICE47.TX_T
TCELL54:IMUX.IMUX.41.DELAYBITSLICE47.TX_CE_OFD
TCELL54:IMUX.IMUX.42.DELAYBITSLICE47.RX_CE_IFD
TCELL54:IMUX.IMUX.43.DELAYBITSLICE47.CLB2PHY_FIFO_RDEN
TCELL54:IMUX.IMUX.44.DELAYBITSLICE47.TX_D1
TCELL54:IMUX.IMUX.45.DELAYBITSLICE47.TX_D2
TCELL54:IMUX.IMUX.46.DELAYBITSLICE47.TX_D3
TCELL54:IMUX.IMUX.47.DELAYBITSLICE47.TX_D5
TCELL55:OUT.0.TMINMMCM.CLKFBSTOPPED
TCELL55:OUT.1.TMINMMCM.CLKINSTOPPED
TCELL55:OUT.2.TMINMMCM.PSDONE
TCELL55:OUT.3.TMINMMCM.CDDCDONE
TCELL55:OUT.4.TMINBITSLICE46.TX_CNTVALUEOUT5
TCELL55:OUT.5.TMINBITSLICE46.TX_CNTVALUEOUT6
TCELL55:OUT.6.TMINBITSLICE46.TX_CNTVALUEOUT7
TCELL55:OUT.7.TMINBITSLICE46.TX_CNTVALUEOUT8
TCELL55:OUT.8.TMINBITSLICE48.TX_T_OUT
TCELL55:OUT.9.TMINBITSLICE46.RX_CNTVALUEOUT0
TCELL55:OUT.10.TMINBITSLICE46.RX_CNTVALUEOUT1
TCELL55:OUT.11.TMINBITSLICE46.RX_CNTVALUEOUT2
TCELL55:OUT.12.TMINBITSLICE46.RX_CNTVALUEOUT3
TCELL55:OUT.13.TMINBITSLICE46.RX_CNTVALUEOUT4
TCELL55:OUT.14.TMINBITSLICE46.RX_CNTVALUEOUT5
TCELL55:OUT.15.TMINBITSLICE46.RX_CNTVALUEOUT6
TCELL55:OUT.16.TMINBITSLICE46.RX_CNTVALUEOUT7
TCELL55:OUT.17.TMINBITSLICE46.RX_CNTVALUEOUT8
TCELL55:OUT.18.TMINBITSLICE47.PHY2CLB_FIFO_EMPTY
TCELL55:OUT.19.TMINBITSLICE47.RX_Q0
TCELL55:OUT.20.TMINBITSLICE47.RX_Q1
TCELL55:OUT.21.TMINBITSLICE47.RX_Q2
TCELL55:OUT.22.TMINBITSLICE47.RX_Q3
TCELL55:OUT.23.TMINBITSLICE47.RX_Q4
TCELL55:OUT.24.TMINBITSLICE47.RX_Q5
TCELL55:OUT.25.TMINBITSLICE47.RX_Q6
TCELL55:OUT.26.TMINBITSLICE47.RX_Q7
TCELL55:OUT.27.TMINBITSLICE47.TX_CNTVALUEOUT0
TCELL55:OUT.28.TMINBITSLICE47.TX_CNTVALUEOUT1
TCELL55:OUT.29.TMINBITSLICE47.TX_CNTVALUEOUT2
TCELL55:OUT.30.TMINBITSLICE47.TX_CNTVALUEOUT3
TCELL55:OUT.31.TMINBITSLICE47.TX_CNTVALUEOUT4
TCELL55:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.IDELAY_RST_B7
TCELL55:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK7
TCELL55:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.TXBIT_RST_B8
TCELL55:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.RXBIT_RST_B8
TCELL55:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.ODELAY_RST_B8
TCELL55:IMUX.BYP.6BITSLICE46.TX_EN_VTC
TCELL55:IMUX.BYP.7BITSLICE46.TX_CE_ODELAY
TCELL55:IMUX.BYP.8BITSLICE46.RX_LD
TCELL55:IMUX.BYP.9BITSLICE46.RX_INC
TCELL55:IMUX.BYP.10BITSLICE46.RX_EN_VTC
TCELL55:IMUX.BYP.11BITSLICE46.RX_CE_IDELAY
TCELL55:IMUX.BYP.12BITSLICE46.DYN_DCI_OUT_INT
TCELL55:IMUX.BYP.13BITSLICE47.TX_LD
TCELL55:IMUX.BYP.14BITSLICE47.TX_INC
TCELL55:IMUX.BYP.15BITSLICE47.TX_EN_VTC
TCELL55:IMUX.IMUX.0.DELAYMMCM.PSINCDEC
TCELL55:IMUX.IMUX.6.DELAYBITSLICE47.RX_CNTVALUEIN4
TCELL55:IMUX.IMUX.7.DELAYBITSLICE47.RX_CNTVALUEIN6
TCELL55:IMUX.IMUX.8.DELAYBITSLICE_T7.CNTVALUEIN1
TCELL55:IMUX.IMUX.9.DELAYBITSLICE_T7.CNTVALUEIN3
TCELL55:IMUX.IMUX.10.DELAYBITSLICE_T7.CNTVALUEIN7
TCELL55:IMUX.IMUX.11.DELAYBITSLICE_CONTROL7.CLB2RIU_NIBBLE_SEL
TCELL55:IMUX.IMUX.12.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS1_3
TCELL55:IMUX.IMUX.13.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS0_1
TCELL55:IMUX.IMUX.14.DELAYBITSLICE_CONTROL7.CLB2PHY_T_B1
TCELL55:IMUX.IMUX.15.DELAYBITSLICE_CONTROL7.CLB2PHY_T_B3
TCELL55:IMUX.IMUX.16.DELAYBITSLICE47.TX_D7
TCELL55:IMUX.IMUX.18.DELAYBITSLICE47.TX_CNTVALUEIN0
TCELL55:IMUX.IMUX.19.DELAYBITSLICE47.TX_CNTVALUEIN1
TCELL55:IMUX.IMUX.20.DELAYBITSLICE47.TX_CNTVALUEIN2
TCELL55:IMUX.IMUX.21.DELAYBITSLICE47.TX_CNTVALUEIN3
TCELL55:IMUX.IMUX.22.DELAYBITSLICE47.TX_CNTVALUEIN4
TCELL55:IMUX.IMUX.23.DELAYBITSLICE47.TX_CNTVALUEIN5
TCELL55:IMUX.IMUX.24.DELAYBITSLICE47.TX_CNTVALUEIN6
TCELL55:IMUX.IMUX.25.DELAYBITSLICE47.TX_CNTVALUEIN7
TCELL55:IMUX.IMUX.26.DELAYBITSLICE47.TX_CNTVALUEIN8
TCELL55:IMUX.IMUX.27.DELAYBITSLICE47.RX_CNTVALUEIN0
TCELL55:IMUX.IMUX.28.DELAYBITSLICE47.RX_CNTVALUEIN1
TCELL55:IMUX.IMUX.29.DELAYBITSLICE47.RX_CNTVALUEIN2
TCELL55:IMUX.IMUX.30.DELAYBITSLICE47.RX_CNTVALUEIN3
TCELL55:IMUX.IMUX.31.DELAYBITSLICE47.RX_CNTVALUEIN5
TCELL55:IMUX.IMUX.32.DELAYBITSLICE47.RX_CNTVALUEIN7
TCELL55:IMUX.IMUX.33.DELAYBITSLICE47.RX_CNTVALUEIN8
TCELL55:IMUX.IMUX.34.DELAYBITSLICE_T7.CNTVALUEIN0
TCELL55:IMUX.IMUX.35.DELAYBITSLICE_T7.CNTVALUEIN2
TCELL55:IMUX.IMUX.36.DELAYBITSLICE_T7.CNTVALUEIN4
TCELL55:IMUX.IMUX.37.DELAYBITSLICE_T7.CNTVALUEIN5
TCELL55:IMUX.IMUX.38.DELAYBITSLICE_T7.CNTVALUEIN6
TCELL55:IMUX.IMUX.39.DELAYBITSLICE_T7.CNTVALUEIN8
TCELL55:IMUX.IMUX.40.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS1_0
TCELL55:IMUX.IMUX.41.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS1_1
TCELL55:IMUX.IMUX.42.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS1_2
TCELL55:IMUX.IMUX.43.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS0_0
TCELL55:IMUX.IMUX.44.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS0_2
TCELL55:IMUX.IMUX.45.DELAYBITSLICE_CONTROL7.CLB2PHY_WRCS0_3
TCELL55:IMUX.IMUX.46.DELAYBITSLICE_CONTROL7.CLB2PHY_T_B0
TCELL55:IMUX.IMUX.47.DELAYBITSLICE_CONTROL7.CLB2PHY_T_B2
TCELL56:OUT.4.TMINBITSLICE47.TX_CNTVALUEOUT5
TCELL56:OUT.5.TMINBITSLICE47.TX_CNTVALUEOUT6
TCELL56:OUT.6.TMINBITSLICE47.TX_CNTVALUEOUT7
TCELL56:OUT.7.TMINBITSLICE47.TX_CNTVALUEOUT8
TCELL56:OUT.8.TMINBITSLICE49.TX_T_OUT
TCELL56:OUT.9.TMINBITSLICE47.RX_CNTVALUEOUT0
TCELL56:OUT.10.TMINBITSLICE47.RX_CNTVALUEOUT1
TCELL56:OUT.11.TMINBITSLICE47.RX_CNTVALUEOUT2
TCELL56:OUT.12.TMINBITSLICE47.RX_CNTVALUEOUT3
TCELL56:OUT.13.TMINBITSLICE47.RX_CNTVALUEOUT4
TCELL56:OUT.14.TMINBITSLICE47.RX_CNTVALUEOUT5
TCELL56:OUT.15.TMINBITSLICE47.RX_CNTVALUEOUT6
TCELL56:OUT.16.TMINBITSLICE47.RX_CNTVALUEOUT7
TCELL56:OUT.17.TMINBITSLICE47.RX_CNTVALUEOUT8
TCELL56:OUT.18.TMINBITSLICE_T7.CNTVALUEOUT0
TCELL56:OUT.19.TMINBITSLICE_T7.CNTVALUEOUT1
TCELL56:OUT.20.TMINBITSLICE_T7.CNTVALUEOUT2
TCELL56:OUT.21.TMINBITSLICE_T7.CNTVALUEOUT3
TCELL56:OUT.22.TMINBITSLICE_T7.CNTVALUEOUT4
TCELL56:OUT.23.TMINBITSLICE_T7.CNTVALUEOUT5
TCELL56:OUT.24.TMINBITSLICE_T7.CNTVALUEOUT6
TCELL56:OUT.25.TMINBITSLICE_T7.CNTVALUEOUT7
TCELL56:OUT.26.TMINBITSLICE_T7.CNTVALUEOUT8
TCELL56:OUT.27.TMINBITSLICE_CONTROL7.PHY2CLB_PHY_RDY
TCELL56:OUT.28.TMINBITSLICE_CONTROL7.MASTER_PD_OUT
TCELL56:OUT.29.TMINBITSLICE_CONTROL7.PHY2CLB_FIXDLY_RDY
TCELL56:OUT.30.TMINBITSLICE_CONTROL7.CTRL_DLY_TEST_OUT
TCELL56:OUT.31.TMINBITSLICE50.TX_T_OUT
TCELL56:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.IDELAY_RST_B8
TCELL56:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK8
TCELL56:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.TRISTATE_ODELAY_RST_B1
TCELL56:IMUX.CTRL.6BITSLICE_CONTROL7.REFCLK
TCELL56:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.CTRL_RST_B_UPP
TCELL56:IMUX.BYP.6BITSLICE47.TX_CE_ODELAY
TCELL56:IMUX.BYP.8BITSLICE47.RX_LD
TCELL56:IMUX.BYP.9BITSLICE47.RX_INC
TCELL56:IMUX.BYP.10BITSLICE47.RX_EN_VTC
TCELL56:IMUX.BYP.11BITSLICE47.RX_CE_IDELAY
TCELL56:IMUX.BYP.12BITSLICE47.DYN_DCI_OUT_INT
TCELL56:IMUX.BYP.13BITSLICE_T7.CE_OFD
TCELL56:IMUX.BYP.14BITSLICE_T7.LD
TCELL56:IMUX.BYP.15BITSLICE_T7.INC
TCELL56:IMUX.IMUX.0.DELAYMMCM.PSEN
TCELL56:IMUX.IMUX.6.DELAYBITSLICE48.RX_DATAIN1
TCELL56:IMUX.IMUX.7.DELAYBITSLICE48.TX_D0
TCELL56:IMUX.IMUX.8.DELAYBITSLICE48.TX_D4
TCELL56:IMUX.IMUX.9.DELAYBITSLICE48.TX_D6
TCELL56:IMUX.IMUX.10.DELAYBITSLICE48.TX_CNTVALUEIN2
TCELL56:IMUX.IMUX.11.DELAYBITSLICE48.TX_CNTVALUEIN4
TCELL56:IMUX.IMUX.12.DELAYBITSLICE48.TX_CNTVALUEIN7
TCELL56:IMUX.IMUX.13.DELAYBITSLICE48.RX_CNTVALUEIN0
TCELL56:IMUX.IMUX.14.DELAYBITSLICE48.RX_CNTVALUEIN4
TCELL56:IMUX.IMUX.15.DELAYBITSLICE48.RX_CNTVALUEIN6
TCELL56:IMUX.IMUX.16.DELAYBITSLICE_CONTROL7.CLB2PHY_RDEN0
TCELL56:IMUX.IMUX.17.DELAYBITSLICE_CONTROL7.CLB2PHY_RDEN1
TCELL56:IMUX.IMUX.18.DELAYBITSLICE_CONTROL7.CLB2PHY_RDEN2
TCELL56:IMUX.IMUX.19.DELAYBITSLICE_CONTROL7.CLB2PHY_RDEN3
TCELL56:IMUX.IMUX.20.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS1_0
TCELL56:IMUX.IMUX.21.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS1_1
TCELL56:IMUX.IMUX.22.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS1_2
TCELL56:IMUX.IMUX.23.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS1_3
TCELL56:IMUX.IMUX.24.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS0_0
TCELL56:IMUX.IMUX.25.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS0_1
TCELL56:IMUX.IMUX.26.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS0_2
TCELL56:IMUX.IMUX.27.DELAYBITSLICE_CONTROL7.CLB2PHY_RDCS0_3
TCELL56:IMUX.IMUX.28.DELAYBITSLICE48.TX_T
TCELL56:IMUX.IMUX.29.DELAYBITSLICE48.TX_CE_OFD
TCELL56:IMUX.IMUX.30.DELAYBITSLICE48.RX_CE_IFD
TCELL56:IMUX.IMUX.31.DELAYBITSLICE48.CLB2PHY_FIFO_RDEN
TCELL56:IMUX.IMUX.32.DELAYBITSLICE48.TX_D1
TCELL56:IMUX.IMUX.33.DELAYBITSLICE48.TX_D2
TCELL56:IMUX.IMUX.34.DELAYBITSLICE48.TX_D3
TCELL56:IMUX.IMUX.35.DELAYBITSLICE48.TX_D5
TCELL56:IMUX.IMUX.36.DELAYBITSLICE48.TX_D7
TCELL56:IMUX.IMUX.37.DELAYBITSLICE48.TX_CNTVALUEIN0
TCELL56:IMUX.IMUX.38.DELAYBITSLICE48.TX_CNTVALUEIN1
TCELL56:IMUX.IMUX.39.DELAYBITSLICE48.TX_CNTVALUEIN3
TCELL56:IMUX.IMUX.40.DELAYBITSLICE48.TX_CNTVALUEIN5
TCELL56:IMUX.IMUX.41.DELAYBITSLICE48.TX_CNTVALUEIN6
TCELL56:IMUX.IMUX.43.DELAYBITSLICE48.TX_CNTVALUEIN8
TCELL56:IMUX.IMUX.44.DELAYBITSLICE48.RX_CNTVALUEIN1
TCELL56:IMUX.IMUX.45.DELAYBITSLICE48.RX_CNTVALUEIN2
TCELL56:IMUX.IMUX.46.DELAYBITSLICE48.RX_CNTVALUEIN3
TCELL56:IMUX.IMUX.47.DELAYBITSLICE48.RX_CNTVALUEIN5
TCELL57:OUT.4.TMINBITSLICE48.PHY2CLB_FIFO_EMPTY
TCELL57:OUT.5.TMINBITSLICE48.RX_Q0
TCELL57:OUT.6.TMINBITSLICE48.RX_Q1
TCELL57:OUT.7.TMINBITSLICE48.RX_Q2
TCELL57:OUT.8.TMINBITSLICE48.RX_Q3
TCELL57:OUT.9.TMINBITSLICE48.RX_Q4
TCELL57:OUT.10.TMINBITSLICE48.RX_Q5
TCELL57:OUT.11.TMINBITSLICE48.RX_Q6
TCELL57:OUT.12.TMINBITSLICE48.RX_Q7
TCELL57:OUT.13.TMINBITSLICE48.TX_CNTVALUEOUT0
TCELL57:OUT.14.TMINBITSLICE48.TX_CNTVALUEOUT1
TCELL57:OUT.15.TMINBITSLICE48.TX_CNTVALUEOUT2
TCELL57:OUT.16.TMINBITSLICE48.TX_CNTVALUEOUT3
TCELL57:OUT.17.TMINBITSLICE48.TX_CNTVALUEOUT4
TCELL57:OUT.18.TMINBITSLICE48.TX_CNTVALUEOUT5
TCELL57:OUT.19.TMINBITSLICE48.TX_CNTVALUEOUT6
TCELL57:OUT.20.TMINBITSLICE48.TX_CNTVALUEOUT7
TCELL57:OUT.21.TMINBITSLICE48.TX_CNTVALUEOUT8
TCELL57:OUT.22.TMINBITSLICE51.TX_T_OUT
TCELL57:OUT.23.TMINBITSLICE48.RX_CNTVALUEOUT0
TCELL57:OUT.24.TMINBITSLICE48.RX_CNTVALUEOUT1
TCELL57:OUT.25.TMINBITSLICE48.RX_CNTVALUEOUT2
TCELL57:OUT.26.TMINBITSLICE48.RX_CNTVALUEOUT3
TCELL57:OUT.27.TMINBITSLICE48.RX_CNTVALUEOUT4
TCELL57:OUT.28.TMINBITSLICE48.RX_CNTVALUEOUT5
TCELL57:OUT.29.TMINBITSLICE48.RX_CNTVALUEOUT6
TCELL57:OUT.30.TMINBITSLICE48.RX_CNTVALUEOUT7
TCELL57:OUT.31.TMINBITSLICE48.RX_CNTVALUEOUT8
TCELL57:IMUX.CTRL.2BITSLICE_CONTROL7.RIU_CLK, XIPHY_FEEDTHROUGH3.CLB2PHY_CTRL_CLK_UPP
TCELL57:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.TXBIT_RST_B9
TCELL57:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.RXBIT_RST_B9
TCELL57:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.ODELAY_RST_B9
TCELL57:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.IDELAY_RST_B9
TCELL57:IMUX.BYP.6BITSLICE_T7.CE_ODELAY
TCELL57:IMUX.BYP.7BITSLICE_CONTROL7.EN_VTC
TCELL57:IMUX.BYP.8BITSLICE_CONTROL7.CTRL_DLY_TEST_IN
TCELL57:IMUX.BYP.9BITSLICE48.TX_LD
TCELL57:IMUX.BYP.10BITSLICE48.TX_INC
TCELL57:IMUX.BYP.11BITSLICE48.TX_EN_VTC
TCELL57:IMUX.BYP.12BITSLICE48.TX_CE_ODELAY
TCELL57:IMUX.BYP.13BITSLICE48.RX_LD
TCELL57:IMUX.BYP.14BITSLICE48.RX_INC
TCELL57:IMUX.BYP.15BITSLICE48.RX_EN_VTC
TCELL57:IMUX.IMUX.6.DELAYBITSLICE49.TX_CNTVALUEIN0
TCELL57:IMUX.IMUX.7.DELAYBITSLICE49.TX_CNTVALUEIN2
TCELL57:IMUX.IMUX.8.DELAYBITSLICE49.TX_CNTVALUEIN6
TCELL57:IMUX.IMUX.9.DELAYBITSLICE49.TX_CNTVALUEIN8
TCELL57:IMUX.IMUX.10.DELAYBITSLICE49.RX_CNTVALUEIN3
TCELL57:IMUX.IMUX.11.DELAYBITSLICE49.RX_CNTVALUEIN5
TCELL57:IMUX.IMUX.12.DELAYBITSLICE50.TX_T
TCELL57:IMUX.IMUX.13.DELAYBITSLICE50.RX_CE_IFD
TCELL57:IMUX.IMUX.14.DELAYBITSLICE50.TX_D1
TCELL57:IMUX.IMUX.15.DELAYBITSLICE50.TX_D3
TCELL57:IMUX.IMUX.16.DELAYBITSLICE48.RX_CNTVALUEIN7
TCELL57:IMUX.IMUX.17.DELAYBITSLICE48.RX_CNTVALUEIN8
TCELL57:IMUX.IMUX.18.DELAYBITSLICE49.TX_T
TCELL57:IMUX.IMUX.19.DELAYBITSLICE49.TX_CE_OFD
TCELL57:IMUX.IMUX.20.DELAYBITSLICE49.RX_CE_IFD
TCELL57:IMUX.IMUX.21.DELAYBITSLICE49.RX_DATAIN1
TCELL57:IMUX.IMUX.22.DELAYBITSLICE49.CLB2PHY_FIFO_RDEN
TCELL57:IMUX.IMUX.23.DELAYBITSLICE49.TX_D5
TCELL57:IMUX.IMUX.24.DELAYBITSLICE49.TX_D4
TCELL57:IMUX.IMUX.25.DELAYBITSLICE49.TX_D3
TCELL57:IMUX.IMUX.26.DELAYBITSLICE49.TX_D2
TCELL57:IMUX.IMUX.27.DELAYBITSLICE49.TX_D1
TCELL57:IMUX.IMUX.28.DELAYBITSLICE49.TX_D0
TCELL57:IMUX.IMUX.29.DELAYBITSLICE49.TX_D6
TCELL57:IMUX.IMUX.30.DELAYBITSLICE49.TX_D7
TCELL57:IMUX.IMUX.31.DELAYBITSLICE49.TX_CNTVALUEIN1
TCELL57:IMUX.IMUX.32.DELAYBITSLICE49.TX_CNTVALUEIN3
TCELL57:IMUX.IMUX.33.DELAYBITSLICE49.TX_CNTVALUEIN4
TCELL57:IMUX.IMUX.34.DELAYBITSLICE49.TX_CNTVALUEIN5
TCELL57:IMUX.IMUX.35.DELAYBITSLICE49.TX_CNTVALUEIN7
TCELL57:IMUX.IMUX.36.DELAYBITSLICE49.RX_CNTVALUEIN0
TCELL57:IMUX.IMUX.37.DELAYBITSLICE49.RX_CNTVALUEIN1
TCELL57:IMUX.IMUX.38.DELAYBITSLICE49.RX_CNTVALUEIN2
TCELL57:IMUX.IMUX.39.DELAYBITSLICE49.RX_CNTVALUEIN4
TCELL57:IMUX.IMUX.40.DELAYBITSLICE49.RX_CNTVALUEIN6
TCELL57:IMUX.IMUX.41.DELAYBITSLICE49.RX_CNTVALUEIN7
TCELL57:IMUX.IMUX.42.DELAYBITSLICE49.RX_CNTVALUEIN8
TCELL57:IMUX.IMUX.43.DELAYBITSLICE50.TX_CE_OFD
TCELL57:IMUX.IMUX.44.DELAYBITSLICE50.RX_DATAIN1
TCELL57:IMUX.IMUX.45.DELAYBITSLICE50.CLB2PHY_FIFO_RDEN
TCELL57:IMUX.IMUX.46.DELAYBITSLICE50.TX_D0
TCELL57:IMUX.IMUX.47.DELAYBITSLICE50.TX_D2
TCELL58:OUT.4.TMINBITSLICE49.PHY2CLB_FIFO_EMPTY
TCELL58:OUT.5.TMINBITSLICE49.RX_Q0
TCELL58:OUT.6.TMINBITSLICE49.RX_Q1
TCELL58:OUT.7.TMINBITSLICE49.RX_Q2
TCELL58:OUT.8.TMINBITSLICE49.RX_Q3
TCELL58:OUT.9.TMINBITSLICE49.RX_Q4
TCELL58:OUT.10.TMINBITSLICE49.RX_Q5
TCELL58:OUT.11.TMINBITSLICE49.RX_Q6
TCELL58:OUT.12.TMINBITSLICE49.RX_Q7
TCELL58:OUT.13.TMINBITSLICE49.TX_CNTVALUEOUT0
TCELL58:OUT.14.TMINBITSLICE49.TX_CNTVALUEOUT1
TCELL58:OUT.15.TMINBITSLICE49.TX_CNTVALUEOUT2
TCELL58:OUT.16.TMINBITSLICE49.TX_CNTVALUEOUT3
TCELL58:OUT.17.TMINBITSLICE49.TX_CNTVALUEOUT4
TCELL58:OUT.18.TMINBITSLICE49.TX_CNTVALUEOUT5
TCELL58:OUT.19.TMINBITSLICE49.TX_CNTVALUEOUT6
TCELL58:OUT.20.TMINBITSLICE49.TX_CNTVALUEOUT7
TCELL58:OUT.21.TMINBITSLICE49.TX_CNTVALUEOUT8
TCELL58:OUT.23.TMINBITSLICE49.RX_CNTVALUEOUT0
TCELL58:OUT.24.TMINBITSLICE49.RX_CNTVALUEOUT1
TCELL58:OUT.25.TMINBITSLICE49.RX_CNTVALUEOUT2
TCELL58:OUT.26.TMINBITSLICE49.RX_CNTVALUEOUT3
TCELL58:OUT.27.TMINBITSLICE49.RX_CNTVALUEOUT4
TCELL58:OUT.28.TMINBITSLICE49.RX_CNTVALUEOUT5
TCELL58:OUT.29.TMINBITSLICE49.RX_CNTVALUEOUT6
TCELL58:OUT.30.TMINBITSLICE49.RX_CNTVALUEOUT7
TCELL58:OUT.31.TMINBITSLICE49.RX_CNTVALUEOUT8
TCELL58:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK9
TCELL58:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.TXBIT_RST_B10
TCELL58:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.RXBIT_RST_B10
TCELL58:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.ODELAY_RST_B10
TCELL58:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.IDELAY_RST_B10
TCELL58:IMUX.BYP.6BITSLICE48.RX_CE_IDELAY
TCELL58:IMUX.BYP.7BITSLICE48.DYN_DCI_OUT_INT
TCELL58:IMUX.BYP.8BITSLICE49.TX_LD
TCELL58:IMUX.BYP.9BITSLICE49.TX_INC
TCELL58:IMUX.BYP.10BITSLICE49.TX_EN_VTC
TCELL58:IMUX.BYP.11BITSLICE49.TX_CE_ODELAY
TCELL58:IMUX.BYP.12BITSLICE49.RX_LD
TCELL58:IMUX.BYP.13BITSLICE49.RX_INC
TCELL58:IMUX.BYP.14BITSLICE49.RX_EN_VTC
TCELL58:IMUX.BYP.15BITSLICE49.RX_CE_IDELAY
TCELL58:IMUX.IMUX.6.DELAYBITSLICE50.TX_D5
TCELL58:IMUX.IMUX.7.DELAYBITSLICE50.TX_D6
TCELL58:IMUX.IMUX.8.DELAYBITSLICE50.TX_D7
TCELL58:IMUX.IMUX.9.DELAYBITSLICE50.TX_CNTVALUEIN0
TCELL58:IMUX.IMUX.10.DELAYBITSLICE50.TX_CNTVALUEIN1
TCELL58:IMUX.IMUX.11.DELAYBITSLICE50.TX_CNTVALUEIN2
TCELL58:IMUX.IMUX.12.DELAYBITSLICE50.TX_CNTVALUEIN3
TCELL58:IMUX.IMUX.13.DELAYBITSLICE50.TX_CNTVALUEIN4
TCELL58:IMUX.IMUX.14.DELAYBITSLICE50.TX_CNTVALUEIN5
TCELL58:IMUX.IMUX.15.DELAYBITSLICE50.TX_CNTVALUEIN6
TCELL58:IMUX.IMUX.16.DELAYBITSLICE50.TX_D4
TCELL59:OUT.4.TMINBITSLICE50.PHY2CLB_FIFO_EMPTY
TCELL59:OUT.5.TMINBITSLICE50.RX_Q0
TCELL59:OUT.6.TMINBITSLICE50.RX_Q1
TCELL59:OUT.7.TMINBITSLICE50.RX_Q2
TCELL59:OUT.8.TMINBITSLICE50.RX_Q3
TCELL59:OUT.9.TMINBITSLICE50.RX_Q4
TCELL59:OUT.10.TMINBITSLICE50.RX_Q5
TCELL59:OUT.11.TMINBITSLICE50.RX_Q6
TCELL59:OUT.12.TMINBITSLICE50.RX_Q7
TCELL59:OUT.13.TMINBITSLICE50.TX_CNTVALUEOUT0
TCELL59:OUT.14.TMINBITSLICE50.TX_CNTVALUEOUT1
TCELL59:OUT.15.TMINBITSLICE50.TX_CNTVALUEOUT2
TCELL59:OUT.16.TMINBITSLICE50.TX_CNTVALUEOUT3
TCELL59:OUT.17.TMINBITSLICE50.TX_CNTVALUEOUT4
TCELL59:OUT.18.TMINBITSLICE50.TX_CNTVALUEOUT5
TCELL59:OUT.19.TMINBITSLICE50.TX_CNTVALUEOUT6
TCELL59:OUT.20.TMINBITSLICE50.TX_CNTVALUEOUT7
TCELL59:OUT.21.TMINBITSLICE50.TX_CNTVALUEOUT8
TCELL59:OUT.23.TMINBITSLICE50.RX_CNTVALUEOUT0
TCELL59:OUT.24.TMINBITSLICE50.RX_CNTVALUEOUT1
TCELL59:OUT.25.TMINBITSLICE50.RX_CNTVALUEOUT2
TCELL59:OUT.26.TMINBITSLICE50.RX_CNTVALUEOUT3
TCELL59:OUT.27.TMINBITSLICE50.RX_CNTVALUEOUT4
TCELL59:OUT.28.TMINBITSLICE50.RX_CNTVALUEOUT5
TCELL59:OUT.29.TMINBITSLICE50.RX_CNTVALUEOUT6
TCELL59:OUT.30.TMINBITSLICE50.RX_CNTVALUEOUT7
TCELL59:OUT.31.TMINBITSLICE50.RX_CNTVALUEOUT8
TCELL59:IMUX.CTRL.2XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK10
TCELL59:IMUX.CTRL.3XIPHY_FEEDTHROUGH3.TXBIT_RST_B11
TCELL59:IMUX.CTRL.4XIPHY_FEEDTHROUGH3.RXBIT_RST_B11
TCELL59:IMUX.CTRL.5XIPHY_FEEDTHROUGH3.ODELAY_RST_B11
TCELL59:IMUX.CTRL.6XIPHY_FEEDTHROUGH3.IDELAY_RST_B11
TCELL59:IMUX.CTRL.7XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK11
TCELL59:IMUX.BYP.6BITSLICE49.DYN_DCI_OUT_INT
TCELL59:IMUX.BYP.7BITSLICE50.TX_LD
TCELL59:IMUX.BYP.8BITSLICE50.TX_INC
TCELL59:IMUX.BYP.9BITSLICE50.TX_EN_VTC
TCELL59:IMUX.BYP.10BITSLICE50.TX_CE_ODELAY
TCELL59:IMUX.BYP.11BITSLICE50.RX_LD
TCELL59:IMUX.BYP.12BITSLICE50.RX_INC
TCELL59:IMUX.BYP.13BITSLICE50.RX_EN_VTC
TCELL59:IMUX.BYP.14BITSLICE50.RX_CE_IDELAY
TCELL59:IMUX.BYP.15BITSLICE50.DYN_DCI_OUT_INT
TCELL59:IMUX.IMUX.6.DELAYBITSLICE50.TX_CNTVALUEIN8
TCELL59:IMUX.IMUX.7.DELAYBITSLICE50.RX_CNTVALUEIN0
TCELL59:IMUX.IMUX.8.DELAYBITSLICE50.RX_CNTVALUEIN1
TCELL59:IMUX.IMUX.9.DELAYBITSLICE50.RX_CNTVALUEIN2
TCELL59:IMUX.IMUX.10.DELAYBITSLICE50.RX_CNTVALUEIN3
TCELL59:IMUX.IMUX.11.DELAYBITSLICE50.RX_CNTVALUEIN4
TCELL59:IMUX.IMUX.12.DELAYBITSLICE50.RX_CNTVALUEIN5
TCELL59:IMUX.IMUX.13.DELAYBITSLICE50.RX_CNTVALUEIN6
TCELL59:IMUX.IMUX.14.DELAYBITSLICE50.RX_CNTVALUEIN7
TCELL59:IMUX.IMUX.15.DELAYBITSLICE50.RX_CNTVALUEIN8
TCELL59:IMUX.IMUX.16.DELAYBITSLICE50.TX_CNTVALUEIN7