HPIO/HRIO XIPHY

Tile XIPHY

Cells: 60

Bel BUFCE_ROW_CMT0

ultrascale XIPHY bel BUFCE_ROW_CMT0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.17.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT1

ultrascale XIPHY bel BUFCE_ROW_CMT1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.18.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT2

ultrascale XIPHY bel BUFCE_ROW_CMT2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.19.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT3

ultrascale XIPHY bel BUFCE_ROW_CMT3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.20.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT4

ultrascale XIPHY bel BUFCE_ROW_CMT4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.21.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT5

ultrascale XIPHY bel BUFCE_ROW_CMT5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.22.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT6

ultrascale XIPHY bel BUFCE_ROW_CMT6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.23.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT7

ultrascale XIPHY bel BUFCE_ROW_CMT7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.24.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT8

ultrascale XIPHY bel BUFCE_ROW_CMT8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.25.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT9

ultrascale XIPHY bel BUFCE_ROW_CMT9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.26.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT10

ultrascale XIPHY bel BUFCE_ROW_CMT10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.27.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT11

ultrascale XIPHY bel BUFCE_ROW_CMT11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.28.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT12

ultrascale XIPHY bel BUFCE_ROW_CMT12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.29.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT13

ultrascale XIPHY bel BUFCE_ROW_CMT13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.30.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT14

ultrascale XIPHY bel BUFCE_ROW_CMT14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.31.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT15

ultrascale XIPHY bel BUFCE_ROW_CMT15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.32.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT16

ultrascale XIPHY bel BUFCE_ROW_CMT16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.33.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT17

ultrascale XIPHY bel BUFCE_ROW_CMT17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.34.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT18

ultrascale XIPHY bel BUFCE_ROW_CMT18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.35.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT19

ultrascale XIPHY bel BUFCE_ROW_CMT19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.36.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT20

ultrascale XIPHY bel BUFCE_ROW_CMT20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.37.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.0
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.1
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.2

Bel BUFCE_ROW_CMT21

ultrascale XIPHY bel BUFCE_ROW_CMT21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.38.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT22

ultrascale XIPHY bel BUFCE_ROW_CMT22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.39.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel BUFCE_ROW_CMT23

ultrascale XIPHY bel BUFCE_ROW_CMT23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.40.DELAY
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.6
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.7
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.8

Bel GCLK_TEST_BUF_CMT0

ultrascale XIPHY bel GCLK_TEST_BUF_CMT0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT1

ultrascale XIPHY bel GCLK_TEST_BUF_CMT1
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT2

ultrascale XIPHY bel GCLK_TEST_BUF_CMT2
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT3

ultrascale XIPHY bel GCLK_TEST_BUF_CMT3
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT4

ultrascale XIPHY bel GCLK_TEST_BUF_CMT4
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT5

ultrascale XIPHY bel GCLK_TEST_BUF_CMT5
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT6

ultrascale XIPHY bel GCLK_TEST_BUF_CMT6
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT7

ultrascale XIPHY bel GCLK_TEST_BUF_CMT7
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT8

ultrascale XIPHY bel GCLK_TEST_BUF_CMT8
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT9

ultrascale XIPHY bel GCLK_TEST_BUF_CMT9
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT10

ultrascale XIPHY bel GCLK_TEST_BUF_CMT10
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT11

ultrascale XIPHY bel GCLK_TEST_BUF_CMT11
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT12

ultrascale XIPHY bel GCLK_TEST_BUF_CMT12
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT13

ultrascale XIPHY bel GCLK_TEST_BUF_CMT13
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT14

ultrascale XIPHY bel GCLK_TEST_BUF_CMT14
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT15

ultrascale XIPHY bel GCLK_TEST_BUF_CMT15
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT16

ultrascale XIPHY bel GCLK_TEST_BUF_CMT16
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT17

ultrascale XIPHY bel GCLK_TEST_BUF_CMT17
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT18

ultrascale XIPHY bel GCLK_TEST_BUF_CMT18
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT19

ultrascale XIPHY bel GCLK_TEST_BUF_CMT19
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT20

ultrascale XIPHY bel GCLK_TEST_BUF_CMT20
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT21

ultrascale XIPHY bel GCLK_TEST_BUF_CMT21
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT22

ultrascale XIPHY bel GCLK_TEST_BUF_CMT22
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT23

ultrascale XIPHY bel GCLK_TEST_BUF_CMT23
Pin	Direction	Wires

Bel BUFGCE0

ultrascale XIPHY bel BUFGCE0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.31.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.24.DELAY

Bel BUFGCE1

ultrascale XIPHY bel BUFGCE1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.32.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.25.DELAY

Bel BUFGCE2

ultrascale XIPHY bel BUFGCE2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.33.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.26.DELAY

Bel BUFGCE3

ultrascale XIPHY bel BUFGCE3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.34.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.27.DELAY

Bel BUFGCE4

ultrascale XIPHY bel BUFGCE4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.35.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.28.DELAY

Bel BUFGCE5

ultrascale XIPHY bel BUFGCE5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.36.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.29.DELAY

Bel BUFGCE6

ultrascale XIPHY bel BUFGCE6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.37.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.30.DELAY

Bel BUFGCE7

ultrascale XIPHY bel BUFGCE7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.38.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.31.DELAY

Bel BUFGCE8

ultrascale XIPHY bel BUFGCE8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.39.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.32.DELAY

Bel BUFGCE9

ultrascale XIPHY bel BUFGCE9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.40.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.33.DELAY

Bel BUFGCE10

ultrascale XIPHY bel BUFGCE10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.41.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.34.DELAY

Bel BUFGCE11

ultrascale XIPHY bel BUFGCE11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.42.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.35.DELAY

Bel BUFGCE12

ultrascale XIPHY bel BUFGCE12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.43.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.36.DELAY

Bel BUFGCE13

ultrascale XIPHY bel BUFGCE13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.44.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.37.DELAY

Bel BUFGCE14

ultrascale XIPHY bel BUFGCE14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.45.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.38.DELAY

Bel BUFGCE15

ultrascale XIPHY bel BUFGCE15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.46.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.39.DELAY

Bel BUFGCE16

ultrascale XIPHY bel BUFGCE16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.47.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.40.DELAY

Bel BUFGCE17

ultrascale XIPHY bel BUFGCE17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.17.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.41.DELAY

Bel BUFGCE18

ultrascale XIPHY bel BUFGCE18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.18.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.42.DELAY

Bel BUFGCE19

ultrascale XIPHY bel BUFGCE19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.19.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.43.DELAY

Bel BUFGCE20

ultrascale XIPHY bel BUFGCE20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.20.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.44.DELAY

Bel BUFGCE21

ultrascale XIPHY bel BUFGCE21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.21.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.45.DELAY

Bel BUFGCE22

ultrascale XIPHY bel BUFGCE22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.22.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.46.DELAY

Bel BUFGCE23

ultrascale XIPHY bel BUFGCE23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.23.DELAY
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.47.DELAY

Bel BUFGCTRL0

ultrascale XIPHY bel BUFGCTRL0
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.23.DELAY
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.46.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.38.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.30.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.22.DELAY
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.45.DELAY

Bel BUFGCTRL1

ultrascale XIPHY bel BUFGCTRL1
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.24.DELAY
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.47.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.39.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.31.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.23.DELAY
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.46.DELAY

Bel BUFGCTRL2

ultrascale XIPHY bel BUFGCTRL2
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.25.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.17.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.40.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.32.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.24.DELAY
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.47.DELAY

Bel BUFGCTRL3

ultrascale XIPHY bel BUFGCTRL3
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.26.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.18.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.41.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.33.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.25.DELAY
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.17.DELAY

Bel BUFGCTRL4

ultrascale XIPHY bel BUFGCTRL4
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.27.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.19.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.42.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.34.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.26.DELAY
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.18.DELAY

Bel BUFGCTRL5

ultrascale XIPHY bel BUFGCTRL5
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.28.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.20.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.43.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.35.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.27.DELAY
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.19.DELAY

Bel BUFGCTRL6

ultrascale XIPHY bel BUFGCTRL6
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.29.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.21.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.44.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.36.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.28.DELAY
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.20.DELAY

Bel BUFGCTRL7

ultrascale XIPHY bel BUFGCTRL7
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.30.DELAY
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.22.DELAY
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.45.DELAY
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.37.DELAY
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.29.DELAY
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.21.DELAY

Bel BUFGCE_DIV0

ultrascale XIPHY bel BUFGCE_DIV0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.41.DELAY
RST_PRE_OPTINV	input	TCELL28:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV1

ultrascale XIPHY bel BUFGCE_DIV1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.42.DELAY
RST_PRE_OPTINV	input	TCELL29:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV2

ultrascale XIPHY bel BUFGCE_DIV2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.43.DELAY
RST_PRE_OPTINV	input	TCELL30:IMUX.IMUX.0.DELAY

Bel BUFGCE_DIV3

ultrascale XIPHY bel BUFGCE_DIV3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.44.DELAY
RST_PRE_OPTINV	input	TCELL31:IMUX.IMUX.0.DELAY

Bel PLL0

ultrascale XIPHY bel PLL0
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL1:IMUX.IMUX.0.DELAY
DADDR0	input	TCELL9:IMUX.BYP.0
DADDR1	input	TCELL9:IMUX.BYP.1
DADDR2	input	TCELL9:IMUX.BYP.2
DADDR3	input	TCELL9:IMUX.BYP.3
DADDR4	input	TCELL8:IMUX.BYP.0
DADDR5	input	TCELL8:IMUX.BYP.1
DADDR6	input	TCELL8:IMUX.BYP.2
DCLK_B	input	TCELL11:IMUX.CTRL.0
DEN	input	TCELL11:IMUX.IMUX.0.DELAY
DI0	input	TCELL13:IMUX.BYP.0
DI1	input	TCELL13:IMUX.BYP.1
DI10	input	TCELL11:IMUX.BYP.2
DI11	input	TCELL11:IMUX.BYP.3
DI12	input	TCELL10:IMUX.BYP.0
DI13	input	TCELL10:IMUX.BYP.1
DI14	input	TCELL10:IMUX.BYP.2
DI15	input	TCELL10:IMUX.BYP.3
DI2	input	TCELL13:IMUX.BYP.2
DI3	input	TCELL13:IMUX.BYP.3
DI4	input	TCELL12:IMUX.BYP.0
DI5	input	TCELL12:IMUX.BYP.1
DI6	input	TCELL12:IMUX.BYP.2
DI7	input	TCELL12:IMUX.BYP.3
DI8	input	TCELL11:IMUX.BYP.0
DI9	input	TCELL11:IMUX.BYP.1
DOUT0	output	TCELL12:OUT.0.TMIN
DOUT1	output	TCELL12:OUT.1.TMIN
DOUT10	output	TCELL10:OUT.2.TMIN
DOUT11	output	TCELL10:OUT.3.TMIN
DOUT12	output	TCELL9:OUT.0.TMIN
DOUT13	output	TCELL9:OUT.1.TMIN
DOUT14	output	TCELL9:OUT.2.TMIN
DOUT15	output	TCELL9:OUT.3.TMIN
DOUT2	output	TCELL12:OUT.2.TMIN
DOUT3	output	TCELL12:OUT.3.TMIN
DOUT4	output	TCELL11:OUT.0.TMIN
DOUT5	output	TCELL11:OUT.1.TMIN
DOUT6	output	TCELL11:OUT.2.TMIN
DOUT7	output	TCELL11:OUT.3.TMIN
DOUT8	output	TCELL10:OUT.0.TMIN
DOUT9	output	TCELL10:OUT.1.TMIN
DRDY	output	TCELL13:OUT.0.TMIN
DWE	input	TCELL10:IMUX.IMUX.0.DELAY
LOCKED	output	TCELL13:OUT.1.TMIN
PWRDWN	input	TCELL12:IMUX.IMUX.0.DELAY
RST	input	TCELL13:IMUX.IMUX.0.DELAY
SCANCLK_B	input	TCELL13:IMUX.CTRL.0
SCANENB	input	TCELL7:IMUX.IMUX.0.DELAY
SCANIN	input	TCELL8:IMUX.IMUX.0.DELAY
SCANMODEB	input	TCELL6:IMUX.IMUX.0.DELAY
SCANOUT	output	TCELL13:OUT.3.TMIN
TESTIN0	input	TCELL7:IMUX.BYP.0
TESTIN1	input	TCELL7:IMUX.BYP.1
TESTIN10	input	TCELL5:IMUX.BYP.2
TESTIN11	input	TCELL5:IMUX.BYP.3
TESTIN12	input	TCELL4:IMUX.BYP.0
TESTIN13	input	TCELL4:IMUX.BYP.1
TESTIN14	input	TCELL4:IMUX.BYP.2
TESTIN15	input	TCELL4:IMUX.BYP.3
TESTIN16	input	TCELL3:IMUX.BYP.0
TESTIN17	input	TCELL3:IMUX.BYP.1
TESTIN18	input	TCELL3:IMUX.BYP.2
TESTIN19	input	TCELL3:IMUX.BYP.3
TESTIN2	input	TCELL7:IMUX.BYP.2
TESTIN20	input	TCELL2:IMUX.BYP.0
TESTIN21	input	TCELL2:IMUX.BYP.1
TESTIN22	input	TCELL2:IMUX.BYP.2
TESTIN23	input	TCELL2:IMUX.BYP.3
TESTIN24	input	TCELL1:IMUX.BYP.0
TESTIN25	input	TCELL1:IMUX.BYP.1
TESTIN26	input	TCELL1:IMUX.BYP.2
TESTIN27	input	TCELL1:IMUX.BYP.3
TESTIN28	input	TCELL0:IMUX.BYP.0
TESTIN29	input	TCELL0:IMUX.BYP.1
TESTIN3	input	TCELL7:IMUX.BYP.3
TESTIN30	input	TCELL0:IMUX.BYP.2
TESTIN31	input	TCELL0:IMUX.BYP.3
TESTIN4	input	TCELL6:IMUX.BYP.0
TESTIN5	input	TCELL6:IMUX.BYP.1
TESTIN6	input	TCELL6:IMUX.BYP.2
TESTIN7	input	TCELL6:IMUX.BYP.3
TESTIN8	input	TCELL5:IMUX.BYP.0
TESTIN9	input	TCELL5:IMUX.BYP.1
TESTOUT0	output	TCELL8:OUT.0.TMIN
TESTOUT1	output	TCELL8:OUT.1.TMIN
TESTOUT10	output	TCELL6:OUT.2.TMIN
TESTOUT11	output	TCELL6:OUT.3.TMIN
TESTOUT12	output	TCELL5:OUT.0.TMIN
TESTOUT13	output	TCELL5:OUT.1.TMIN
TESTOUT14	output	TCELL5:OUT.2.TMIN
TESTOUT15	output	TCELL5:OUT.3.TMIN
TESTOUT16	output	TCELL4:OUT.0.TMIN
TESTOUT17	output	TCELL4:OUT.1.TMIN
TESTOUT18	output	TCELL4:OUT.2.TMIN
TESTOUT19	output	TCELL4:OUT.3.TMIN
TESTOUT2	output	TCELL8:OUT.2.TMIN
TESTOUT20	output	TCELL3:OUT.0.TMIN
TESTOUT21	output	TCELL3:OUT.1.TMIN
TESTOUT22	output	TCELL3:OUT.2.TMIN
TESTOUT23	output	TCELL3:OUT.3.TMIN
TESTOUT24	output	TCELL2:OUT.0.TMIN
TESTOUT25	output	TCELL2:OUT.1.TMIN
TESTOUT26	output	TCELL2:OUT.2.TMIN
TESTOUT27	output	TCELL2:OUT.3.TMIN
TESTOUT28	output	TCELL1:OUT.0.TMIN
TESTOUT29	output	TCELL1:OUT.1.TMIN
TESTOUT3	output	TCELL8:OUT.3.TMIN
TESTOUT30	output	TCELL1:OUT.2.TMIN
TESTOUT31	output	TCELL1:OUT.3.TMIN
TESTOUT32	output	TCELL0:OUT.0.TMIN
TESTOUT33	output	TCELL0:OUT.1.TMIN
TESTOUT34	output	TCELL0:OUT.2.TMIN
TESTOUT35	output	TCELL0:OUT.3.TMIN
TESTOUT36	output	TCELL13:OUT.2.TMIN
TESTOUT4	output	TCELL7:OUT.0.TMIN
TESTOUT5	output	TCELL7:OUT.1.TMIN
TESTOUT6	output	TCELL7:OUT.2.TMIN
TESTOUT7	output	TCELL7:OUT.3.TMIN
TESTOUT8	output	TCELL6:OUT.0.TMIN
TESTOUT9	output	TCELL6:OUT.1.TMIN

Bel PLL1

ultrascale XIPHY bel PLL1
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL15:IMUX.IMUX.0.DELAY
DADDR0	input	TCELL23:IMUX.BYP.0
DADDR1	input	TCELL23:IMUX.BYP.1
DADDR2	input	TCELL23:IMUX.BYP.2
DADDR3	input	TCELL23:IMUX.BYP.3
DADDR4	input	TCELL22:IMUX.BYP.0
DADDR5	input	TCELL22:IMUX.BYP.1
DADDR6	input	TCELL22:IMUX.BYP.2
DCLK_B	input	TCELL25:IMUX.CTRL.0
DEN	input	TCELL25:IMUX.IMUX.0.DELAY
DI0	input	TCELL27:IMUX.BYP.0
DI1	input	TCELL27:IMUX.BYP.1
DI10	input	TCELL25:IMUX.BYP.2
DI11	input	TCELL25:IMUX.BYP.3
DI12	input	TCELL24:IMUX.BYP.0
DI13	input	TCELL24:IMUX.BYP.1
DI14	input	TCELL24:IMUX.BYP.2
DI15	input	TCELL24:IMUX.BYP.3
DI2	input	TCELL27:IMUX.BYP.2
DI3	input	TCELL27:IMUX.BYP.3
DI4	input	TCELL26:IMUX.BYP.0
DI5	input	TCELL26:IMUX.BYP.1
DI6	input	TCELL26:IMUX.BYP.2
DI7	input	TCELL26:IMUX.BYP.3
DI8	input	TCELL25:IMUX.BYP.0
DI9	input	TCELL25:IMUX.BYP.1
DOUT0	output	TCELL26:OUT.0.TMIN
DOUT1	output	TCELL26:OUT.1.TMIN
DOUT10	output	TCELL24:OUT.2.TMIN
DOUT11	output	TCELL24:OUT.3.TMIN
DOUT12	output	TCELL23:OUT.0.TMIN
DOUT13	output	TCELL23:OUT.1.TMIN
DOUT14	output	TCELL23:OUT.2.TMIN
DOUT15	output	TCELL23:OUT.3.TMIN
DOUT2	output	TCELL26:OUT.2.TMIN
DOUT3	output	TCELL26:OUT.3.TMIN
DOUT4	output	TCELL25:OUT.0.TMIN
DOUT5	output	TCELL25:OUT.1.TMIN
DOUT6	output	TCELL25:OUT.2.TMIN
DOUT7	output	TCELL25:OUT.3.TMIN
DOUT8	output	TCELL24:OUT.0.TMIN
DOUT9	output	TCELL24:OUT.1.TMIN
DRDY	output	TCELL27:OUT.0.TMIN
DWE	input	TCELL24:IMUX.IMUX.0.DELAY
LOCKED	output	TCELL27:OUT.1.TMIN
PWRDWN	input	TCELL26:IMUX.IMUX.0.DELAY
RST	input	TCELL27:IMUX.IMUX.0.DELAY
SCANCLK_B	input	TCELL27:IMUX.CTRL.0
SCANENB	input	TCELL21:IMUX.IMUX.0.DELAY
SCANIN	input	TCELL22:IMUX.IMUX.0.DELAY
SCANMODEB	input	TCELL20:IMUX.IMUX.0.DELAY
SCANOUT	output	TCELL27:OUT.3.TMIN
TESTIN0	input	TCELL21:IMUX.BYP.0
TESTIN1	input	TCELL21:IMUX.BYP.1
TESTIN10	input	TCELL19:IMUX.BYP.2
TESTIN11	input	TCELL19:IMUX.BYP.3
TESTIN12	input	TCELL18:IMUX.BYP.0
TESTIN13	input	TCELL18:IMUX.BYP.1
TESTIN14	input	TCELL18:IMUX.BYP.2
TESTIN15	input	TCELL18:IMUX.BYP.3
TESTIN16	input	TCELL17:IMUX.BYP.0
TESTIN17	input	TCELL17:IMUX.BYP.1
TESTIN18	input	TCELL17:IMUX.BYP.2
TESTIN19	input	TCELL17:IMUX.BYP.3
TESTIN2	input	TCELL21:IMUX.BYP.2
TESTIN20	input	TCELL16:IMUX.BYP.0
TESTIN21	input	TCELL16:IMUX.BYP.1
TESTIN22	input	TCELL16:IMUX.BYP.2
TESTIN23	input	TCELL16:IMUX.BYP.3
TESTIN24	input	TCELL15:IMUX.BYP.0
TESTIN25	input	TCELL15:IMUX.BYP.1
TESTIN26	input	TCELL15:IMUX.BYP.2
TESTIN27	input	TCELL15:IMUX.BYP.3
TESTIN28	input	TCELL14:IMUX.BYP.0
TESTIN29	input	TCELL14:IMUX.BYP.1
TESTIN3	input	TCELL21:IMUX.BYP.3
TESTIN30	input	TCELL14:IMUX.BYP.2
TESTIN31	input	TCELL14:IMUX.BYP.3
TESTIN4	input	TCELL20:IMUX.BYP.0
TESTIN5	input	TCELL20:IMUX.BYP.1
TESTIN6	input	TCELL20:IMUX.BYP.2
TESTIN7	input	TCELL20:IMUX.BYP.3
TESTIN8	input	TCELL19:IMUX.BYP.0
TESTIN9	input	TCELL19:IMUX.BYP.1
TESTOUT0	output	TCELL22:OUT.0.TMIN
TESTOUT1	output	TCELL22:OUT.1.TMIN
TESTOUT10	output	TCELL20:OUT.2.TMIN
TESTOUT11	output	TCELL20:OUT.3.TMIN
TESTOUT12	output	TCELL19:OUT.0.TMIN
TESTOUT13	output	TCELL19:OUT.1.TMIN
TESTOUT14	output	TCELL19:OUT.2.TMIN
TESTOUT15	output	TCELL19:OUT.3.TMIN
TESTOUT16	output	TCELL18:OUT.0.TMIN
TESTOUT17	output	TCELL18:OUT.1.TMIN
TESTOUT18	output	TCELL18:OUT.2.TMIN
TESTOUT19	output	TCELL18:OUT.3.TMIN
TESTOUT2	output	TCELL22:OUT.2.TMIN
TESTOUT20	output	TCELL17:OUT.0.TMIN
TESTOUT21	output	TCELL17:OUT.1.TMIN
TESTOUT22	output	TCELL17:OUT.2.TMIN
TESTOUT23	output	TCELL17:OUT.3.TMIN
TESTOUT24	output	TCELL16:OUT.0.TMIN
TESTOUT25	output	TCELL16:OUT.1.TMIN
TESTOUT26	output	TCELL16:OUT.2.TMIN
TESTOUT27	output	TCELL16:OUT.3.TMIN
TESTOUT28	output	TCELL15:OUT.0.TMIN
TESTOUT29	output	TCELL15:OUT.1.TMIN
TESTOUT3	output	TCELL22:OUT.3.TMIN
TESTOUT30	output	TCELL15:OUT.2.TMIN
TESTOUT31	output	TCELL15:OUT.3.TMIN
TESTOUT32	output	TCELL14:OUT.0.TMIN
TESTOUT33	output	TCELL14:OUT.1.TMIN
TESTOUT34	output	TCELL14:OUT.2.TMIN
TESTOUT35	output	TCELL14:OUT.3.TMIN
TESTOUT36	output	TCELL27:OUT.2.TMIN
TESTOUT4	output	TCELL21:OUT.0.TMIN
TESTOUT5	output	TCELL21:OUT.1.TMIN
TESTOUT6	output	TCELL21:OUT.2.TMIN
TESTOUT7	output	TCELL21:OUT.3.TMIN
TESTOUT8	output	TCELL20:OUT.0.TMIN
TESTOUT9	output	TCELL20:OUT.1.TMIN

Bel MMCM

ultrascale XIPHY bel MMCM
Pin	Direction	Wires
CDDCDONE	output	TCELL55:OUT.3.TMIN
CDDCREQ	input	TCELL50:IMUX.IMUX.0.DELAY
CLKFBSTOPPED	output	TCELL55:OUT.0.TMIN
CLKINSEL	input	TCELL41:IMUX.IMUX.0.DELAY
CLKINSTOPPED	output	TCELL55:OUT.1.TMIN
DADDR0	input	TCELL50:IMUX.BYP.0
DADDR1	input	TCELL50:IMUX.BYP.1
DADDR2	input	TCELL50:IMUX.BYP.2
DADDR3	input	TCELL50:IMUX.BYP.3
DADDR4	input	TCELL49:IMUX.BYP.0
DADDR5	input	TCELL49:IMUX.BYP.1
DADDR6	input	TCELL49:IMUX.BYP.2
DCLK_B	input	TCELL52:IMUX.CTRL.0
DEN	input	TCELL52:IMUX.IMUX.0.DELAY
DI0	input	TCELL54:IMUX.BYP.0
DI1	input	TCELL54:IMUX.BYP.1
DI10	input	TCELL52:IMUX.BYP.2
DI11	input	TCELL52:IMUX.BYP.3
DI12	input	TCELL51:IMUX.BYP.0
DI13	input	TCELL51:IMUX.BYP.1
DI14	input	TCELL51:IMUX.BYP.2
DI15	input	TCELL51:IMUX.BYP.3
DI2	input	TCELL54:IMUX.BYP.2
DI3	input	TCELL54:IMUX.BYP.3
DI4	input	TCELL53:IMUX.BYP.0
DI5	input	TCELL53:IMUX.BYP.1
DI6	input	TCELL53:IMUX.BYP.2
DI7	input	TCELL53:IMUX.BYP.3
DI8	input	TCELL52:IMUX.BYP.0
DI9	input	TCELL52:IMUX.BYP.1
DOUT0	output	TCELL53:OUT.0.TMIN
DOUT1	output	TCELL53:OUT.1.TMIN
DOUT10	output	TCELL51:OUT.2.TMIN
DOUT11	output	TCELL51:OUT.3.TMIN
DOUT12	output	TCELL50:OUT.0.TMIN
DOUT13	output	TCELL50:OUT.1.TMIN
DOUT14	output	TCELL50:OUT.2.TMIN
DOUT15	output	TCELL50:OUT.3.TMIN
DOUT2	output	TCELL53:OUT.2.TMIN
DOUT3	output	TCELL53:OUT.3.TMIN
DOUT4	output	TCELL52:OUT.0.TMIN
DOUT5	output	TCELL52:OUT.1.TMIN
DOUT6	output	TCELL52:OUT.2.TMIN
DOUT7	output	TCELL52:OUT.3.TMIN
DOUT8	output	TCELL51:OUT.0.TMIN
DOUT9	output	TCELL51:OUT.1.TMIN
DRDY	output	TCELL54:OUT.0.TMIN
DWE	input	TCELL51:IMUX.IMUX.0.DELAY
LOCKED	output	TCELL54:OUT.1.TMIN
PSCLK_B	input	TCELL53:IMUX.CTRL.0
PSDONE	output	TCELL55:OUT.2.TMIN
PSEN	input	TCELL56:IMUX.IMUX.0.DELAY
PSINCDEC	input	TCELL55:IMUX.IMUX.0.DELAY
PWRDWN	input	TCELL53:IMUX.IMUX.0.DELAY
RST	input	TCELL54:IMUX.IMUX.0.DELAY
SCANCLK_B	input	TCELL54:IMUX.CTRL.0
SCANENB	input	TCELL48:IMUX.IMUX.0.DELAY
SCANIN	input	TCELL49:IMUX.IMUX.0.DELAY
SCANMODEB	input	TCELL47:IMUX.IMUX.0.DELAY
SCANOUT	output	TCELL54:OUT.3.TMIN
TESTIN0	input	TCELL48:IMUX.BYP.0
TESTIN1	input	TCELL48:IMUX.BYP.1
TESTIN10	input	TCELL46:IMUX.BYP.2
TESTIN11	input	TCELL46:IMUX.BYP.3
TESTIN12	input	TCELL45:IMUX.BYP.0
TESTIN13	input	TCELL45:IMUX.BYP.1
TESTIN14	input	TCELL45:IMUX.BYP.2
TESTIN15	input	TCELL45:IMUX.BYP.3
TESTIN16	input	TCELL44:IMUX.BYP.0
TESTIN17	input	TCELL44:IMUX.BYP.1
TESTIN18	input	TCELL44:IMUX.BYP.2
TESTIN19	input	TCELL44:IMUX.BYP.3
TESTIN2	input	TCELL48:IMUX.BYP.2
TESTIN20	input	TCELL43:IMUX.BYP.0
TESTIN21	input	TCELL43:IMUX.BYP.1
TESTIN22	input	TCELL43:IMUX.BYP.2
TESTIN23	input	TCELL43:IMUX.BYP.3
TESTIN24	input	TCELL42:IMUX.BYP.0
TESTIN25	input	TCELL42:IMUX.BYP.1
TESTIN26	input	TCELL42:IMUX.BYP.2
TESTIN27	input	TCELL42:IMUX.BYP.3
TESTIN28	input	TCELL41:IMUX.BYP.0
TESTIN29	input	TCELL41:IMUX.BYP.1
TESTIN3	input	TCELL48:IMUX.BYP.3
TESTIN30	input	TCELL41:IMUX.BYP.2
TESTIN31	input	TCELL41:IMUX.BYP.3
TESTIN4	input	TCELL47:IMUX.BYP.0
TESTIN5	input	TCELL47:IMUX.BYP.1
TESTIN6	input	TCELL47:IMUX.BYP.2
TESTIN7	input	TCELL47:IMUX.BYP.3
TESTIN8	input	TCELL46:IMUX.BYP.0
TESTIN9	input	TCELL46:IMUX.BYP.1
TESTOUT0	output	TCELL49:OUT.0.TMIN
TESTOUT1	output	TCELL49:OUT.1.TMIN
TESTOUT10	output	TCELL47:OUT.2.TMIN
TESTOUT11	output	TCELL47:OUT.3.TMIN
TESTOUT12	output	TCELL46:OUT.0.TMIN
TESTOUT13	output	TCELL46:OUT.1.TMIN
TESTOUT14	output	TCELL46:OUT.2.TMIN
TESTOUT15	output	TCELL46:OUT.3.TMIN
TESTOUT16	output	TCELL45:OUT.0.TMIN
TESTOUT17	output	TCELL45:OUT.1.TMIN
TESTOUT18	output	TCELL45:OUT.2.TMIN
TESTOUT19	output	TCELL45:OUT.3.TMIN
TESTOUT2	output	TCELL49:OUT.2.TMIN
TESTOUT20	output	TCELL44:OUT.0.TMIN
TESTOUT21	output	TCELL44:OUT.1.TMIN
TESTOUT22	output	TCELL44:OUT.2.TMIN
TESTOUT23	output	TCELL44:OUT.3.TMIN
TESTOUT24	output	TCELL43:OUT.0.TMIN
TESTOUT25	output	TCELL43:OUT.1.TMIN
TESTOUT26	output	TCELL43:OUT.2.TMIN
TESTOUT27	output	TCELL43:OUT.3.TMIN
TESTOUT28	output	TCELL42:OUT.0.TMIN
TESTOUT29	output	TCELL42:OUT.1.TMIN
TESTOUT3	output	TCELL49:OUT.3.TMIN
TESTOUT30	output	TCELL42:OUT.2.TMIN
TESTOUT31	output	TCELL42:OUT.3.TMIN
TESTOUT32	output	TCELL41:OUT.0.TMIN
TESTOUT33	output	TCELL41:OUT.1.TMIN
TESTOUT34	output	TCELL41:OUT.2.TMIN
TESTOUT35	output	TCELL41:OUT.3.TMIN
TESTOUT36	output	TCELL54:OUT.2.TMIN
TESTOUT4	output	TCELL48:OUT.0.TMIN
TESTOUT5	output	TCELL48:OUT.1.TMIN
TESTOUT6	output	TCELL48:OUT.2.TMIN
TESTOUT7	output	TCELL48:OUT.3.TMIN
TESTOUT8	output	TCELL47:OUT.0.TMIN
TESTOUT9	output	TCELL47:OUT.1.TMIN

Bel CMT

ultrascale XIPHY bel CMT
Pin	Direction	Wires

Bel VCC_CMT

ultrascale XIPHY bel VCC_CMT
Pin	Direction	Wires

Bel BITSLICE0

ultrascale XIPHY bel BITSLICE0
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL0:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INT	input	TCELL0:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL0:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL0:IMUX.BYP.14
RX_CE_IFD	input	TCELL0:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0	input	TCELL2:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL2:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL2:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL2:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL2:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL2:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL2:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL2:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL2:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL0:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL0:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL0:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL0:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL0:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL0:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL0:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL0:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL0:OUT.31.TMIN
RX_DATAIN1	input	TCELL0:IMUX.IMUX.8.DELAY
RX_EN_VTC	input	TCELL0:IMUX.BYP.13
RX_INC	input	TCELL0:IMUX.BYP.12
RX_LD	input	TCELL0:IMUX.BYP.11
RX_Q0	output	TCELL0:OUT.5.TMIN
RX_Q1	output	TCELL0:OUT.6.TMIN
RX_Q2	output	TCELL0:OUT.7.TMIN
RX_Q3	output	TCELL0:OUT.8.TMIN
RX_Q4	output	TCELL0:OUT.9.TMIN
RX_Q5	output	TCELL0:OUT.10.TMIN
RX_Q6	output	TCELL0:OUT.11.TMIN
RX_Q7	output	TCELL0:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL0:IMUX.BYP.10
TX_CE_OFD	input	TCELL0:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0	input	TCELL1:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1	input	TCELL1:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2	input	TCELL1:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3	input	TCELL1:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4	input	TCELL1:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL1:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6	input	TCELL1:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7	input	TCELL1:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8	input	TCELL1:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL0:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL0:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL0:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL0:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL0:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL0:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL0:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL0:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL0:OUT.21.TMIN
TX_D0	input	TCELL1:IMUX.IMUX.16.DELAY
TX_D1	input	TCELL1:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL0:IMUX.IMUX.15.DELAY
TX_D3	input	TCELL0:IMUX.IMUX.14.DELAY
TX_D4	input	TCELL0:IMUX.IMUX.13.DELAY
TX_D5	input	TCELL0:IMUX.IMUX.12.DELAY
TX_D6	input	TCELL0:IMUX.IMUX.11.DELAY
TX_D7	input	TCELL0:IMUX.IMUX.10.DELAY
TX_EN_VTC	input	TCELL0:IMUX.BYP.9
TX_INC	input	TCELL0:IMUX.BYP.8
TX_LD	input	TCELL0:IMUX.BYP.7
TX_T	input	TCELL0:IMUX.IMUX.16.DELAY
TX_T_OUT	output	TCELL0:OUT.22.TMIN

Bel BITSLICE1

ultrascale XIPHY bel BITSLICE1
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL2:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INT	input	TCELL1:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL1:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL1:IMUX.BYP.14
RX_CE_IFD	input	TCELL2:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL2:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1	input	TCELL2:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2	input	TCELL2:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3	input	TCELL2:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4	input	TCELL2:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5	input	TCELL2:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6	input	TCELL2:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7	input	TCELL2:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8	input	TCELL2:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0	output	TCELL1:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL1:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL1:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL1:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL1:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL1:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL1:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL1:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL1:OUT.31.TMIN
RX_DATAIN1	input	TCELL2:IMUX.IMUX.28.DELAY
RX_EN_VTC	input	TCELL1:IMUX.BYP.13
RX_INC	input	TCELL1:IMUX.BYP.12
RX_LD	input	TCELL1:IMUX.BYP.11
RX_Q0	output	TCELL1:OUT.5.TMIN
RX_Q1	output	TCELL1:OUT.6.TMIN
RX_Q2	output	TCELL1:OUT.7.TMIN
RX_Q3	output	TCELL1:OUT.8.TMIN
RX_Q4	output	TCELL1:OUT.9.TMIN
RX_Q5	output	TCELL1:OUT.10.TMIN
RX_Q6	output	TCELL1:OUT.11.TMIN
RX_Q7	output	TCELL1:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL1:IMUX.BYP.10
TX_CE_OFD	input	TCELL2:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL2:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1	input	TCELL2:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2	input	TCELL2:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3	input	TCELL2:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4	input	TCELL2:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5	input	TCELL2:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6	input	TCELL2:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7	input	TCELL2:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8	input	TCELL2:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0	output	TCELL1:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL1:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL1:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL1:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL1:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL1:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL1:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL1:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL1:OUT.21.TMIN
TX_D0	input	TCELL2:IMUX.IMUX.30.DELAY
TX_D1	input	TCELL2:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL2:IMUX.IMUX.31.DELAY
TX_D3	input	TCELL2:IMUX.IMUX.7.DELAY
TX_D4	input	TCELL2:IMUX.IMUX.32.DELAY
TX_D5	input	TCELL2:IMUX.IMUX.33.DELAY
TX_D6	input	TCELL2:IMUX.IMUX.34.DELAY
TX_D7	input	TCELL2:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL1:IMUX.BYP.9
TX_INC	input	TCELL1:IMUX.BYP.8
TX_LD	input	TCELL1:IMUX.BYP.7
TX_T	input	TCELL2:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL1:OUT.22.TMIN

Bel BITSLICE2

ultrascale XIPHY bel BITSLICE2
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL3:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INT	input	TCELL2:IMUX.BYP.14
PHY2CLB_FIFO_EMPTY	output	TCELL2:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL2:IMUX.BYP.13
RX_CE_IFD	input	TCELL3:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0	input	TCELL3:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL3:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL3:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL3:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL3:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL3:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL3:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL3:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL3:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL2:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL2:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL2:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL2:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL2:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL2:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL2:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL2:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL2:OUT.31.TMIN
RX_DATAIN1	input	TCELL3:IMUX.IMUX.17.DELAY
RX_EN_VTC	input	TCELL2:IMUX.BYP.12
RX_INC	input	TCELL2:IMUX.BYP.11
RX_LD	input	TCELL2:IMUX.BYP.10
RX_Q0	output	TCELL2:OUT.5.TMIN
RX_Q1	output	TCELL2:OUT.6.TMIN
RX_Q2	output	TCELL2:OUT.7.TMIN
RX_Q3	output	TCELL2:OUT.8.TMIN
RX_Q4	output	TCELL2:OUT.9.TMIN
RX_Q5	output	TCELL2:OUT.10.TMIN
RX_Q6	output	TCELL2:OUT.11.TMIN
RX_Q7	output	TCELL2:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL2:IMUX.BYP.9
TX_CE_OFD	input	TCELL2:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0	input	TCELL3:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL3:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL3:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL3:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL3:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL3:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL3:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL3:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL3:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL2:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL2:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL2:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL2:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL2:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL2:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL2:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL2:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL2:OUT.21.TMIN
TX_D0	input	TCELL3:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL3:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL3:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL3:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL3:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL3:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL3:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL3:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL2:IMUX.BYP.8
TX_INC	input	TCELL2:IMUX.BYP.7
TX_LD	input	TCELL2:IMUX.BYP.6
TX_T	input	TCELL2:IMUX.IMUX.47.DELAY
TX_T_OUT	output	TCELL2:OUT.22.TMIN

Bel BITSLICE3

ultrascale XIPHY bel BITSLICE3
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL4:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INT	input	TCELL4:IMUX.BYP.10
PHY2CLB_FIFO_EMPTY	output	TCELL3:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL4:IMUX.BYP.9
RX_CE_IFD	input	TCELL4:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0	input	TCELL5:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1	input	TCELL5:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2	input	TCELL5:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3	input	TCELL5:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4	input	TCELL5:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5	input	TCELL5:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6	input	TCELL5:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7	input	TCELL5:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8	input	TCELL5:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0	output	TCELL4:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL4:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL4:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL4:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL4:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL4:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL4:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL4:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL4:OUT.17.TMIN
RX_DATAIN1	input	TCELL4:IMUX.IMUX.37.DELAY
RX_EN_VTC	input	TCELL4:IMUX.BYP.8
RX_INC	input	TCELL4:IMUX.BYP.7
RX_LD	input	TCELL4:IMUX.BYP.6
RX_Q0	output	TCELL3:OUT.19.TMIN
RX_Q1	output	TCELL3:OUT.20.TMIN
RX_Q2	output	TCELL3:OUT.21.TMIN
RX_Q3	output	TCELL3:OUT.22.TMIN
RX_Q4	output	TCELL3:OUT.23.TMIN
RX_Q5	output	TCELL3:OUT.24.TMIN
RX_Q6	output	TCELL3:OUT.25.TMIN
RX_Q7	output	TCELL3:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL3:IMUX.BYP.15
TX_CE_OFD	input	TCELL4:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0	input	TCELL4:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1	input	TCELL4:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2	input	TCELL4:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3	input	TCELL4:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4	input	TCELL4:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5	input	TCELL4:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6	input	TCELL5:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7	input	TCELL5:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8	input	TCELL5:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0	output	TCELL3:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL3:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL3:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL3:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL3:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL4:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL4:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL4:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL4:OUT.7.TMIN
TX_D0	input	TCELL4:IMUX.IMUX.10.DELAY
TX_D1	input	TCELL4:IMUX.IMUX.39.DELAY
TX_D2	input	TCELL4:IMUX.IMUX.11.DELAY
TX_D3	input	TCELL4:IMUX.IMUX.40.DELAY
TX_D4	input	TCELL4:IMUX.IMUX.41.DELAY
TX_D5	input	TCELL4:IMUX.IMUX.42.DELAY
TX_D6	input	TCELL4:IMUX.IMUX.12.DELAY
TX_D7	input	TCELL4:IMUX.IMUX.13.DELAY
TX_EN_VTC	input	TCELL3:IMUX.BYP.14
TX_INC	input	TCELL3:IMUX.BYP.13
TX_LD	input	TCELL3:IMUX.BYP.12
TX_T	input	TCELL4:IMUX.IMUX.35.DELAY
TX_T_OUT	output	TCELL3:OUT.13.TMIN

Bel BITSLICE4

ultrascale XIPHY bel BITSLICE4
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL5:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL5:IMUX.BYP.9
PHY2CLB_FIFO_EMPTY	output	TCELL4:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL5:IMUX.BYP.8
RX_CE_IFD	input	TCELL5:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL5:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1	input	TCELL5:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2	input	TCELL5:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3	input	TCELL5:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4	input	TCELL5:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5	input	TCELL5:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6	input	TCELL5:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7	input	TCELL5:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8	input	TCELL6:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0	output	TCELL5:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL5:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL5:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL5:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL5:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL5:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL5:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL5:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL5:OUT.17.TMIN
RX_DATAIN1	input	TCELL5:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL5:IMUX.BYP.7
RX_INC	input	TCELL5:IMUX.BYP.6
RX_LD	input	TCELL4:IMUX.BYP.15
RX_Q0	output	TCELL4:OUT.19.TMIN
RX_Q1	output	TCELL4:OUT.20.TMIN
RX_Q2	output	TCELL4:OUT.21.TMIN
RX_Q3	output	TCELL4:OUT.22.TMIN
RX_Q4	output	TCELL4:OUT.23.TMIN
RX_Q5	output	TCELL4:OUT.24.TMIN
RX_Q6	output	TCELL4:OUT.25.TMIN
RX_Q7	output	TCELL4:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL4:IMUX.BYP.14
TX_CE_OFD	input	TCELL5:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL5:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL5:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL5:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL5:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL5:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL5:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL5:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL5:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8	input	TCELL5:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0	output	TCELL4:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL4:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL4:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL4:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL4:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL5:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL5:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL5:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL5:OUT.7.TMIN
TX_D0	input	TCELL5:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL5:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL5:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL5:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL5:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL5:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL5:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL5:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL4:IMUX.BYP.13
TX_INC	input	TCELL4:IMUX.BYP.12
TX_LD	input	TCELL4:IMUX.BYP.11
TX_T	input	TCELL5:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL4:OUT.8.TMIN

Bel BITSLICE5

ultrascale XIPHY bel BITSLICE5
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL6:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INT	input	TCELL6:IMUX.BYP.8
PHY2CLB_FIFO_EMPTY	output	TCELL5:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL6:IMUX.BYP.7
RX_CE_IFD	input	TCELL6:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0	input	TCELL6:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL6:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL6:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL6:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL6:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL6:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL6:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL6:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL6:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL6:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL6:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL6:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL6:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL6:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL6:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL6:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL6:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL6:OUT.17.TMIN
RX_DATAIN1	input	TCELL6:IMUX.IMUX.20.DELAY
RX_EN_VTC	input	TCELL6:IMUX.BYP.6
RX_INC	input	TCELL5:IMUX.BYP.15
RX_LD	input	TCELL5:IMUX.BYP.14
RX_Q0	output	TCELL5:OUT.19.TMIN
RX_Q1	output	TCELL5:OUT.20.TMIN
RX_Q2	output	TCELL5:OUT.21.TMIN
RX_Q3	output	TCELL5:OUT.22.TMIN
RX_Q4	output	TCELL5:OUT.23.TMIN
RX_Q5	output	TCELL5:OUT.24.TMIN
RX_Q6	output	TCELL5:OUT.25.TMIN
RX_Q7	output	TCELL5:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL5:IMUX.BYP.13
TX_CE_OFD	input	TCELL6:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0	input	TCELL6:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1	input	TCELL6:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2	input	TCELL6:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3	input	TCELL6:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4	input	TCELL6:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5	input	TCELL6:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6	input	TCELL6:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7	input	TCELL6:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8	input	TCELL6:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0	output	TCELL5:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL5:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL5:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL5:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL5:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL6:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL6:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL6:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL6:OUT.7.TMIN
TX_D0	input	TCELL6:IMUX.IMUX.22.DELAY
TX_D1	input	TCELL6:IMUX.IMUX.23.DELAY
TX_D2	input	TCELL6:IMUX.IMUX.24.DELAY
TX_D3	input	TCELL6:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL6:IMUX.IMUX.26.DELAY
TX_D5	input	TCELL6:IMUX.IMUX.27.DELAY
TX_D6	input	TCELL6:IMUX.IMUX.28.DELAY
TX_D7	input	TCELL6:IMUX.IMUX.29.DELAY
TX_EN_VTC	input	TCELL5:IMUX.BYP.12
TX_INC	input	TCELL5:IMUX.BYP.11
TX_LD	input	TCELL5:IMUX.BYP.10
TX_T	input	TCELL6:IMUX.IMUX.17.DELAY
TX_T_OUT	output	TCELL5:OUT.8.TMIN

Bel BITSLICE6

ultrascale XIPHY bel BITSLICE6
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL8:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INT	input	TCELL9:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL8:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL9:IMUX.BYP.11
RX_CE_IFD	input	TCELL8:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL8:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1	input	TCELL8:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2	input	TCELL8:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3	input	TCELL8:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4	input	TCELL8:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5	input	TCELL8:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6	input	TCELL8:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7	input	TCELL8:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL8:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0	output	TCELL9:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL9:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL9:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL9:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL9:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL9:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL9:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL9:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL9:OUT.17.TMIN
RX_DATAIN1	input	TCELL8:IMUX.IMUX.29.DELAY
RX_EN_VTC	input	TCELL9:IMUX.BYP.10
RX_INC	input	TCELL9:IMUX.BYP.9
RX_LD	input	TCELL9:IMUX.BYP.8
RX_Q0	output	TCELL8:OUT.19.TMIN
RX_Q1	output	TCELL8:OUT.20.TMIN
RX_Q2	output	TCELL8:OUT.21.TMIN
RX_Q3	output	TCELL8:OUT.22.TMIN
RX_Q4	output	TCELL8:OUT.23.TMIN
RX_Q5	output	TCELL8:OUT.24.TMIN
RX_Q6	output	TCELL8:OUT.25.TMIN
RX_Q7	output	TCELL8:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL9:IMUX.BYP.7
TX_CE_OFD	input	TCELL8:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL8:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL8:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2	input	TCELL8:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3	input	TCELL8:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4	input	TCELL8:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5	input	TCELL8:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6	input	TCELL8:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7	input	TCELL8:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8	input	TCELL8:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0	output	TCELL8:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL8:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL8:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL8:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL8:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL9:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL9:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL9:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL9:OUT.7.TMIN
TX_D0	input	TCELL8:IMUX.IMUX.6.DELAY
TX_D1	input	TCELL8:IMUX.IMUX.31.DELAY
TX_D2	input	TCELL8:IMUX.IMUX.7.DELAY
TX_D3	input	TCELL8:IMUX.IMUX.32.DELAY
TX_D4	input	TCELL8:IMUX.IMUX.33.DELAY
TX_D5	input	TCELL8:IMUX.IMUX.34.DELAY
TX_D6	input	TCELL8:IMUX.IMUX.8.DELAY
TX_D7	input	TCELL8:IMUX.IMUX.35.DELAY
TX_EN_VTC	input	TCELL9:IMUX.BYP.6
TX_INC	input	TCELL8:IMUX.BYP.15
TX_LD	input	TCELL8:IMUX.BYP.14
TX_T	input	TCELL8:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL6:OUT.8.TMIN

Bel BITSLICE7

ultrascale XIPHY bel BITSLICE7
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL9:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INT	input	TCELL10:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL9:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL10:IMUX.BYP.11
RX_CE_IFD	input	TCELL9:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0	input	TCELL9:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL9:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL9:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL9:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL9:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL9:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL9:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL9:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL9:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL10:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL10:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL10:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL10:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL10:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL10:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL10:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL10:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL10:OUT.17.TMIN
RX_DATAIN1	input	TCELL9:IMUX.IMUX.18.DELAY
RX_EN_VTC	input	TCELL10:IMUX.BYP.10
RX_INC	input	TCELL10:IMUX.BYP.9
RX_LD	input	TCELL10:IMUX.BYP.8
RX_Q0	output	TCELL9:OUT.19.TMIN
RX_Q1	output	TCELL9:OUT.20.TMIN
RX_Q2	output	TCELL9:OUT.21.TMIN
RX_Q3	output	TCELL9:OUT.22.TMIN
RX_Q4	output	TCELL9:OUT.23.TMIN
RX_Q5	output	TCELL9:OUT.24.TMIN
RX_Q6	output	TCELL9:OUT.25.TMIN
RX_Q7	output	TCELL9:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL10:IMUX.BYP.7
TX_CE_OFD	input	TCELL9:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0	input	TCELL9:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL9:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL9:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL9:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL9:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL9:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL9:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL9:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL9:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL9:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL9:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL9:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL9:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL9:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL10:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL10:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL10:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL10:OUT.7.TMIN
TX_D0	input	TCELL9:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL9:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL9:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL9:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL9:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL9:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL9:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL9:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL10:IMUX.BYP.6
TX_INC	input	TCELL9:IMUX.BYP.15
TX_LD	input	TCELL9:IMUX.BYP.14
TX_T	input	TCELL8:IMUX.IMUX.15.DELAY
TX_T_OUT	output	TCELL8:OUT.8.TMIN

Bel BITSLICE8

ultrascale XIPHY bel BITSLICE8
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL9:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INT	input	TCELL11:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL10:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL11:IMUX.BYP.11
RX_CE_IFD	input	TCELL9:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0	input	TCELL10:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1	input	TCELL10:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2	input	TCELL10:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3	input	TCELL10:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4	input	TCELL10:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5	input	TCELL10:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6	input	TCELL10:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7	input	TCELL10:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8	input	TCELL10:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0	output	TCELL11:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL11:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL11:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL11:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL11:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL11:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL11:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL11:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL11:OUT.17.TMIN
RX_DATAIN1	input	TCELL9:IMUX.IMUX.12.DELAY
RX_EN_VTC	input	TCELL11:IMUX.BYP.10
RX_INC	input	TCELL11:IMUX.BYP.9
RX_LD	input	TCELL11:IMUX.BYP.8
RX_Q0	output	TCELL10:OUT.19.TMIN
RX_Q1	output	TCELL10:OUT.20.TMIN
RX_Q2	output	TCELL10:OUT.21.TMIN
RX_Q3	output	TCELL10:OUT.22.TMIN
RX_Q4	output	TCELL10:OUT.23.TMIN
RX_Q5	output	TCELL10:OUT.24.TMIN
RX_Q6	output	TCELL10:OUT.25.TMIN
RX_Q7	output	TCELL10:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL11:IMUX.BYP.6
TX_CE_OFD	input	TCELL9:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0	input	TCELL10:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1	input	TCELL10:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2	input	TCELL10:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3	input	TCELL10:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4	input	TCELL10:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5	input	TCELL10:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6	input	TCELL10:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7	input	TCELL10:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8	input	TCELL10:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0	output	TCELL10:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL10:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL10:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL10:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL10:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL11:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL11:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL11:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL11:OUT.7.TMIN
TX_D0	input	TCELL9:IMUX.IMUX.13.DELAY
TX_D1	input	TCELL9:IMUX.IMUX.44.DELAY
TX_D2	input	TCELL9:IMUX.IMUX.45.DELAY
TX_D3	input	TCELL9:IMUX.IMUX.46.DELAY
TX_D4	input	TCELL9:IMUX.IMUX.14.DELAY
TX_D5	input	TCELL9:IMUX.IMUX.47.DELAY
TX_D6	input	TCELL9:IMUX.IMUX.15.DELAY
TX_D7	input	TCELL10:IMUX.IMUX.16.DELAY
TX_EN_VTC	input	TCELL10:IMUX.BYP.15
TX_INC	input	TCELL10:IMUX.BYP.14
TX_LD	input	TCELL10:IMUX.BYP.13
TX_T	input	TCELL9:IMUX.IMUX.40.DELAY
TX_T_OUT	output	TCELL9:OUT.8.TMIN

Bel BITSLICE9

ultrascale XIPHY bel BITSLICE9
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL11:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL13:IMUX.BYP.7
PHY2CLB_FIFO_EMPTY	output	TCELL12:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL13:IMUX.BYP.6
RX_CE_IFD	input	TCELL11:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL11:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1	input	TCELL11:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2	input	TCELL11:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3	input	TCELL11:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4	input	TCELL11:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5	input	TCELL11:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6	input	TCELL11:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7	input	TCELL12:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8	input	TCELL12:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0	output	TCELL12:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL12:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL12:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL12:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL12:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL12:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL12:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL12:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL12:OUT.31.TMIN
RX_DATAIN1	input	TCELL11:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL12:IMUX.BYP.15
RX_INC	input	TCELL12:IMUX.BYP.14
RX_LD	input	TCELL12:IMUX.BYP.13
RX_Q0	output	TCELL12:OUT.5.TMIN
RX_Q1	output	TCELL12:OUT.6.TMIN
RX_Q2	output	TCELL12:OUT.7.TMIN
RX_Q3	output	TCELL12:OUT.8.TMIN
RX_Q4	output	TCELL12:OUT.9.TMIN
RX_Q5	output	TCELL12:OUT.10.TMIN
RX_Q6	output	TCELL12:OUT.11.TMIN
RX_Q7	output	TCELL12:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL12:IMUX.BYP.12
TX_CE_OFD	input	TCELL11:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL11:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL11:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL11:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL11:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL11:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL11:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL11:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL11:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8	input	TCELL11:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0	output	TCELL12:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL12:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL12:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL12:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL12:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL12:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL12:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL12:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL12:OUT.21.TMIN
TX_D0	input	TCELL11:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL11:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL11:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL11:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL11:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL11:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL11:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL11:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL12:IMUX.BYP.11
TX_INC	input	TCELL12:IMUX.BYP.10
TX_LD	input	TCELL12:IMUX.BYP.9
TX_T	input	TCELL11:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL10:OUT.8.TMIN

Bel BITSLICE10

ultrascale XIPHY bel BITSLICE10
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL12:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INT	input	TCELL14:IMUX.BYP.6
PHY2CLB_FIFO_EMPTY	output	TCELL13:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL13:IMUX.BYP.15
RX_CE_IFD	input	TCELL12:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0	input	TCELL12:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL12:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL12:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL12:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL12:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL12:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL12:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL12:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL12:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL13:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL13:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL13:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL13:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL13:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL13:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL13:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL13:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL13:OUT.31.TMIN
RX_DATAIN1	input	TCELL12:IMUX.IMUX.21.DELAY
RX_EN_VTC	input	TCELL13:IMUX.BYP.14
RX_INC	input	TCELL13:IMUX.BYP.13
RX_LD	input	TCELL13:IMUX.BYP.12
RX_Q0	output	TCELL13:OUT.5.TMIN
RX_Q1	output	TCELL13:OUT.6.TMIN
RX_Q2	output	TCELL13:OUT.7.TMIN
RX_Q3	output	TCELL13:OUT.8.TMIN
RX_Q4	output	TCELL13:OUT.9.TMIN
RX_Q5	output	TCELL13:OUT.10.TMIN
RX_Q6	output	TCELL13:OUT.11.TMIN
RX_Q7	output	TCELL13:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL13:IMUX.BYP.11
TX_CE_OFD	input	TCELL12:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0	input	TCELL12:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1	input	TCELL12:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2	input	TCELL12:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3	input	TCELL12:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4	input	TCELL12:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5	input	TCELL12:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6	input	TCELL12:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7	input	TCELL12:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8	input	TCELL12:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0	output	TCELL13:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL13:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL13:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL13:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL13:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL13:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL13:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL13:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL13:OUT.21.TMIN
TX_D0	input	TCELL12:IMUX.IMUX.28.DELAY
TX_D1	input	TCELL12:IMUX.IMUX.27.DELAY
TX_D2	input	TCELL12:IMUX.IMUX.26.DELAY
TX_D3	input	TCELL12:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL12:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL12:IMUX.IMUX.23.DELAY
TX_D6	input	TCELL12:IMUX.IMUX.29.DELAY
TX_D7	input	TCELL12:IMUX.IMUX.30.DELAY
TX_EN_VTC	input	TCELL13:IMUX.BYP.10
TX_INC	input	TCELL13:IMUX.BYP.9
TX_LD	input	TCELL13:IMUX.BYP.8
TX_T	input	TCELL12:IMUX.IMUX.18.DELAY
TX_T_OUT	output	TCELL11:OUT.8.TMIN

Bel BITSLICE11

ultrascale XIPHY bel BITSLICE11
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL12:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INT	input	TCELL14:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL14:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL14:IMUX.BYP.14
RX_CE_IFD	input	TCELL12:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0	input	TCELL14:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1	input	TCELL14:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2	input	TCELL14:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL14:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL14:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5	input	TCELL14:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6	input	TCELL14:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7	input	TCELL14:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL14:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0	output	TCELL14:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL14:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL14:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL14:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL14:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL14:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL14:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL14:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL14:OUT.31.TMIN
RX_DATAIN1	input	TCELL12:IMUX.IMUX.44.DELAY
RX_EN_VTC	input	TCELL14:IMUX.BYP.13
RX_INC	input	TCELL14:IMUX.BYP.12
RX_LD	input	TCELL14:IMUX.BYP.11
RX_Q0	output	TCELL14:OUT.5.TMIN
RX_Q1	output	TCELL14:OUT.6.TMIN
RX_Q2	output	TCELL14:OUT.7.TMIN
RX_Q3	output	TCELL14:OUT.8.TMIN
RX_Q4	output	TCELL14:OUT.9.TMIN
RX_Q5	output	TCELL14:OUT.10.TMIN
RX_Q6	output	TCELL14:OUT.11.TMIN
RX_Q7	output	TCELL14:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL14:IMUX.BYP.10
TX_CE_OFD	input	TCELL12:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0	input	TCELL13:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL13:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2	input	TCELL13:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3	input	TCELL13:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4	input	TCELL13:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5	input	TCELL13:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6	input	TCELL13:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7	input	TCELL14:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8	input	TCELL14:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0	output	TCELL14:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL14:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL14:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL14:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL14:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL14:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL14:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL14:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL14:OUT.21.TMIN
TX_D0	input	TCELL12:IMUX.IMUX.46.DELAY
TX_D1	input	TCELL12:IMUX.IMUX.14.DELAY
TX_D2	input	TCELL12:IMUX.IMUX.47.DELAY
TX_D3	input	TCELL12:IMUX.IMUX.15.DELAY
TX_D4	input	TCELL13:IMUX.IMUX.16.DELAY
TX_D5	input	TCELL13:IMUX.IMUX.6.DELAY
TX_D6	input	TCELL13:IMUX.IMUX.7.DELAY
TX_D7	input	TCELL13:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL14:IMUX.BYP.9
TX_INC	input	TCELL14:IMUX.BYP.8
TX_LD	input	TCELL14:IMUX.BYP.7
TX_T	input	TCELL12:IMUX.IMUX.12.DELAY
TX_T_OUT	output	TCELL11:OUT.31.TMIN

Bel BITSLICE12

ultrascale XIPHY bel BITSLICE12
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL7:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INT	input	TCELL8:IMUX.BYP.13
PHY2CLB_FIFO_EMPTY	output	TCELL7:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL8:IMUX.BYP.12
RX_CE_IFD	input	TCELL7:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0	input	TCELL8:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL8:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL8:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL8:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL8:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL8:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL8:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL8:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL8:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL8:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL8:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL8:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL8:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL8:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL8:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL8:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL8:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL8:OUT.17.TMIN
RX_DATAIN1	input	TCELL7:IMUX.IMUX.9.DELAY
RX_EN_VTC	input	TCELL8:IMUX.BYP.11
RX_INC	input	TCELL8:IMUX.BYP.10
RX_LD	input	TCELL8:IMUX.BYP.9
RX_Q0	output	TCELL7:OUT.19.TMIN
RX_Q1	output	TCELL7:OUT.20.TMIN
RX_Q2	output	TCELL7:OUT.21.TMIN
RX_Q3	output	TCELL7:OUT.22.TMIN
RX_Q4	output	TCELL7:OUT.23.TMIN
RX_Q5	output	TCELL7:OUT.24.TMIN
RX_Q6	output	TCELL7:OUT.25.TMIN
RX_Q7	output	TCELL7:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL8:IMUX.BYP.8
TX_CE_OFD	input	TCELL7:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0	input	TCELL7:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1	input	TCELL7:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2	input	TCELL7:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3	input	TCELL7:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4	input	TCELL7:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5	input	TCELL7:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6	input	TCELL7:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7	input	TCELL7:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8	input	TCELL7:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL7:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL7:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL7:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL7:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL7:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL8:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL8:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL8:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL8:OUT.7.TMIN
TX_D0	input	TCELL7:IMUX.IMUX.37.DELAY
TX_D1	input	TCELL7:IMUX.IMUX.38.DELAY
TX_D2	input	TCELL7:IMUX.IMUX.10.DELAY
TX_D3	input	TCELL7:IMUX.IMUX.39.DELAY
TX_D4	input	TCELL7:IMUX.IMUX.11.DELAY
TX_D5	input	TCELL7:IMUX.IMUX.40.DELAY
TX_D6	input	TCELL7:IMUX.IMUX.41.DELAY
TX_D7	input	TCELL7:IMUX.IMUX.42.DELAY
TX_EN_VTC	input	TCELL8:IMUX.BYP.7
TX_INC	input	TCELL8:IMUX.BYP.6
TX_LD	input	TCELL7:IMUX.BYP.15
TX_T	input	TCELL7:IMUX.IMUX.34.DELAY
TX_T_OUT	output	TCELL12:OUT.22.TMIN

Bel BITSLICE13

ultrascale XIPHY bel BITSLICE13
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL15:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INT	input	TCELL15:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL15:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL15:IMUX.BYP.14
RX_CE_IFD	input	TCELL15:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0	input	TCELL17:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL17:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL17:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL17:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL17:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL17:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL17:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL17:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL17:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL15:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL15:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL15:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL15:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL15:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL15:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL15:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL15:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL15:OUT.31.TMIN
RX_DATAIN1	input	TCELL15:IMUX.IMUX.8.DELAY
RX_EN_VTC	input	TCELL15:IMUX.BYP.13
RX_INC	input	TCELL15:IMUX.BYP.12
RX_LD	input	TCELL15:IMUX.BYP.11
RX_Q0	output	TCELL15:OUT.5.TMIN
RX_Q1	output	TCELL15:OUT.6.TMIN
RX_Q2	output	TCELL15:OUT.7.TMIN
RX_Q3	output	TCELL15:OUT.8.TMIN
RX_Q4	output	TCELL15:OUT.9.TMIN
RX_Q5	output	TCELL15:OUT.10.TMIN
RX_Q6	output	TCELL15:OUT.11.TMIN
RX_Q7	output	TCELL15:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL15:IMUX.BYP.10
TX_CE_OFD	input	TCELL15:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0	input	TCELL16:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1	input	TCELL16:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2	input	TCELL16:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3	input	TCELL16:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4	input	TCELL16:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL16:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6	input	TCELL16:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7	input	TCELL16:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8	input	TCELL16:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL15:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL15:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL15:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL15:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL15:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL15:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL15:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL15:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL15:OUT.21.TMIN
TX_D0	input	TCELL16:IMUX.IMUX.16.DELAY
TX_D1	input	TCELL16:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL15:IMUX.IMUX.15.DELAY
TX_D3	input	TCELL15:IMUX.IMUX.14.DELAY
TX_D4	input	TCELL15:IMUX.IMUX.13.DELAY
TX_D5	input	TCELL15:IMUX.IMUX.12.DELAY
TX_D6	input	TCELL15:IMUX.IMUX.11.DELAY
TX_D7	input	TCELL15:IMUX.IMUX.10.DELAY
TX_EN_VTC	input	TCELL15:IMUX.BYP.9
TX_INC	input	TCELL15:IMUX.BYP.8
TX_LD	input	TCELL15:IMUX.BYP.7
TX_T	input	TCELL15:IMUX.IMUX.16.DELAY
TX_T_OUT	output	TCELL15:OUT.22.TMIN

Bel BITSLICE14

ultrascale XIPHY bel BITSLICE14
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL17:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INT	input	TCELL16:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL16:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL16:IMUX.BYP.14
RX_CE_IFD	input	TCELL17:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL17:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1	input	TCELL17:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2	input	TCELL17:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3	input	TCELL17:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4	input	TCELL17:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5	input	TCELL17:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6	input	TCELL17:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7	input	TCELL17:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8	input	TCELL17:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0	output	TCELL16:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL16:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL16:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL16:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL16:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL16:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL16:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL16:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL16:OUT.31.TMIN
RX_DATAIN1	input	TCELL17:IMUX.IMUX.28.DELAY
RX_EN_VTC	input	TCELL16:IMUX.BYP.13
RX_INC	input	TCELL16:IMUX.BYP.12
RX_LD	input	TCELL16:IMUX.BYP.11
RX_Q0	output	TCELL16:OUT.5.TMIN
RX_Q1	output	TCELL16:OUT.6.TMIN
RX_Q2	output	TCELL16:OUT.7.TMIN
RX_Q3	output	TCELL16:OUT.8.TMIN
RX_Q4	output	TCELL16:OUT.9.TMIN
RX_Q5	output	TCELL16:OUT.10.TMIN
RX_Q6	output	TCELL16:OUT.11.TMIN
RX_Q7	output	TCELL16:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL16:IMUX.BYP.10
TX_CE_OFD	input	TCELL17:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL17:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1	input	TCELL17:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2	input	TCELL17:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3	input	TCELL17:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4	input	TCELL17:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5	input	TCELL17:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6	input	TCELL17:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7	input	TCELL17:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8	input	TCELL17:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0	output	TCELL16:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL16:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL16:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL16:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL16:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL16:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL16:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL16:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL16:OUT.21.TMIN
TX_D0	input	TCELL17:IMUX.IMUX.30.DELAY
TX_D1	input	TCELL17:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL17:IMUX.IMUX.31.DELAY
TX_D3	input	TCELL17:IMUX.IMUX.7.DELAY
TX_D4	input	TCELL17:IMUX.IMUX.32.DELAY
TX_D5	input	TCELL17:IMUX.IMUX.33.DELAY
TX_D6	input	TCELL17:IMUX.IMUX.34.DELAY
TX_D7	input	TCELL17:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL16:IMUX.BYP.9
TX_INC	input	TCELL16:IMUX.BYP.8
TX_LD	input	TCELL16:IMUX.BYP.7
TX_T	input	TCELL17:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL16:OUT.22.TMIN

Bel BITSLICE15

ultrascale XIPHY bel BITSLICE15
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL18:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INT	input	TCELL17:IMUX.BYP.14
PHY2CLB_FIFO_EMPTY	output	TCELL17:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL17:IMUX.BYP.13
RX_CE_IFD	input	TCELL18:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0	input	TCELL18:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL18:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL18:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL18:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL18:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL18:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL18:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL18:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL18:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL17:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL17:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL17:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL17:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL17:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL17:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL17:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL17:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL17:OUT.31.TMIN
RX_DATAIN1	input	TCELL18:IMUX.IMUX.17.DELAY
RX_EN_VTC	input	TCELL17:IMUX.BYP.12
RX_INC	input	TCELL17:IMUX.BYP.11
RX_LD	input	TCELL17:IMUX.BYP.10
RX_Q0	output	TCELL17:OUT.5.TMIN
RX_Q1	output	TCELL17:OUT.6.TMIN
RX_Q2	output	TCELL17:OUT.7.TMIN
RX_Q3	output	TCELL17:OUT.8.TMIN
RX_Q4	output	TCELL17:OUT.9.TMIN
RX_Q5	output	TCELL17:OUT.10.TMIN
RX_Q6	output	TCELL17:OUT.11.TMIN
RX_Q7	output	TCELL17:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL17:IMUX.BYP.9
TX_CE_OFD	input	TCELL17:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0	input	TCELL18:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL18:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL18:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL18:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL18:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL18:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL18:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL18:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL18:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL17:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL17:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL17:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL17:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL17:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL17:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL17:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL17:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL17:OUT.21.TMIN
TX_D0	input	TCELL18:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL18:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL18:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL18:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL18:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL18:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL18:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL18:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL17:IMUX.BYP.8
TX_INC	input	TCELL17:IMUX.BYP.7
TX_LD	input	TCELL17:IMUX.BYP.6
TX_T	input	TCELL17:IMUX.IMUX.47.DELAY
TX_T_OUT	output	TCELL17:OUT.22.TMIN

Bel BITSLICE16

ultrascale XIPHY bel BITSLICE16
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL19:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INT	input	TCELL19:IMUX.BYP.10
PHY2CLB_FIFO_EMPTY	output	TCELL18:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL19:IMUX.BYP.9
RX_CE_IFD	input	TCELL19:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0	input	TCELL20:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1	input	TCELL20:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2	input	TCELL20:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3	input	TCELL20:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4	input	TCELL20:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5	input	TCELL20:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6	input	TCELL20:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7	input	TCELL20:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8	input	TCELL20:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0	output	TCELL19:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL19:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL19:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL19:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL19:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL19:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL19:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL19:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL19:OUT.17.TMIN
RX_DATAIN1	input	TCELL19:IMUX.IMUX.37.DELAY
RX_EN_VTC	input	TCELL19:IMUX.BYP.8
RX_INC	input	TCELL19:IMUX.BYP.7
RX_LD	input	TCELL19:IMUX.BYP.6
RX_Q0	output	TCELL18:OUT.19.TMIN
RX_Q1	output	TCELL18:OUT.20.TMIN
RX_Q2	output	TCELL18:OUT.21.TMIN
RX_Q3	output	TCELL18:OUT.22.TMIN
RX_Q4	output	TCELL18:OUT.23.TMIN
RX_Q5	output	TCELL18:OUT.24.TMIN
RX_Q6	output	TCELL18:OUT.25.TMIN
RX_Q7	output	TCELL18:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL18:IMUX.BYP.15
TX_CE_OFD	input	TCELL19:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0	input	TCELL19:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1	input	TCELL19:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2	input	TCELL19:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3	input	TCELL19:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4	input	TCELL19:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5	input	TCELL19:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6	input	TCELL20:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7	input	TCELL20:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8	input	TCELL20:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0	output	TCELL18:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL18:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL18:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL18:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL18:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL19:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL19:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL19:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL19:OUT.7.TMIN
TX_D0	input	TCELL19:IMUX.IMUX.10.DELAY
TX_D1	input	TCELL19:IMUX.IMUX.39.DELAY
TX_D2	input	TCELL19:IMUX.IMUX.11.DELAY
TX_D3	input	TCELL19:IMUX.IMUX.40.DELAY
TX_D4	input	TCELL19:IMUX.IMUX.41.DELAY
TX_D5	input	TCELL19:IMUX.IMUX.42.DELAY
TX_D6	input	TCELL19:IMUX.IMUX.12.DELAY
TX_D7	input	TCELL19:IMUX.IMUX.13.DELAY
TX_EN_VTC	input	TCELL18:IMUX.BYP.14
TX_INC	input	TCELL18:IMUX.BYP.13
TX_LD	input	TCELL18:IMUX.BYP.12
TX_T	input	TCELL19:IMUX.IMUX.35.DELAY
TX_T_OUT	output	TCELL18:OUT.13.TMIN

Bel BITSLICE17

ultrascale XIPHY bel BITSLICE17
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL20:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL20:IMUX.BYP.9
PHY2CLB_FIFO_EMPTY	output	TCELL19:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL20:IMUX.BYP.8
RX_CE_IFD	input	TCELL20:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL20:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1	input	TCELL20:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2	input	TCELL20:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3	input	TCELL20:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4	input	TCELL20:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5	input	TCELL20:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6	input	TCELL20:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7	input	TCELL20:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8	input	TCELL21:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0	output	TCELL20:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL20:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL20:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL20:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL20:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL20:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL20:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL20:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL20:OUT.17.TMIN
RX_DATAIN1	input	TCELL20:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL20:IMUX.BYP.7
RX_INC	input	TCELL20:IMUX.BYP.6
RX_LD	input	TCELL19:IMUX.BYP.15
RX_Q0	output	TCELL19:OUT.19.TMIN
RX_Q1	output	TCELL19:OUT.20.TMIN
RX_Q2	output	TCELL19:OUT.21.TMIN
RX_Q3	output	TCELL19:OUT.22.TMIN
RX_Q4	output	TCELL19:OUT.23.TMIN
RX_Q5	output	TCELL19:OUT.24.TMIN
RX_Q6	output	TCELL19:OUT.25.TMIN
RX_Q7	output	TCELL19:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL19:IMUX.BYP.14
TX_CE_OFD	input	TCELL20:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL20:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL20:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL20:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL20:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL20:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL20:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL20:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL20:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8	input	TCELL20:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0	output	TCELL19:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL19:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL19:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL19:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL19:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL20:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL20:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL20:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL20:OUT.7.TMIN
TX_D0	input	TCELL20:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL20:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL20:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL20:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL20:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL20:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL20:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL20:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL19:IMUX.BYP.13
TX_INC	input	TCELL19:IMUX.BYP.12
TX_LD	input	TCELL19:IMUX.BYP.11
TX_T	input	TCELL20:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL19:OUT.8.TMIN

Bel BITSLICE18

ultrascale XIPHY bel BITSLICE18
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL21:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INT	input	TCELL21:IMUX.BYP.8
PHY2CLB_FIFO_EMPTY	output	TCELL20:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL21:IMUX.BYP.7
RX_CE_IFD	input	TCELL21:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0	input	TCELL21:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL21:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL21:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL21:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL21:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL21:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL21:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL21:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL21:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL21:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL21:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL21:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL21:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL21:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL21:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL21:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL21:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL21:OUT.17.TMIN
RX_DATAIN1	input	TCELL21:IMUX.IMUX.20.DELAY
RX_EN_VTC	input	TCELL21:IMUX.BYP.6
RX_INC	input	TCELL20:IMUX.BYP.15
RX_LD	input	TCELL20:IMUX.BYP.14
RX_Q0	output	TCELL20:OUT.19.TMIN
RX_Q1	output	TCELL20:OUT.20.TMIN
RX_Q2	output	TCELL20:OUT.21.TMIN
RX_Q3	output	TCELL20:OUT.22.TMIN
RX_Q4	output	TCELL20:OUT.23.TMIN
RX_Q5	output	TCELL20:OUT.24.TMIN
RX_Q6	output	TCELL20:OUT.25.TMIN
RX_Q7	output	TCELL20:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL20:IMUX.BYP.13
TX_CE_OFD	input	TCELL21:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0	input	TCELL21:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1	input	TCELL21:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2	input	TCELL21:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3	input	TCELL21:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4	input	TCELL21:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5	input	TCELL21:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6	input	TCELL21:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7	input	TCELL21:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8	input	TCELL21:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0	output	TCELL20:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL20:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL20:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL20:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL20:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL21:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL21:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL21:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL21:OUT.7.TMIN
TX_D0	input	TCELL21:IMUX.IMUX.22.DELAY
TX_D1	input	TCELL21:IMUX.IMUX.23.DELAY
TX_D2	input	TCELL21:IMUX.IMUX.24.DELAY
TX_D3	input	TCELL21:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL21:IMUX.IMUX.26.DELAY
TX_D5	input	TCELL21:IMUX.IMUX.27.DELAY
TX_D6	input	TCELL21:IMUX.IMUX.28.DELAY
TX_D7	input	TCELL21:IMUX.IMUX.29.DELAY
TX_EN_VTC	input	TCELL20:IMUX.BYP.12
TX_INC	input	TCELL20:IMUX.BYP.11
TX_LD	input	TCELL20:IMUX.BYP.10
TX_T	input	TCELL21:IMUX.IMUX.17.DELAY
TX_T_OUT	output	TCELL20:OUT.8.TMIN

Bel BITSLICE19

ultrascale XIPHY bel BITSLICE19
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL23:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INT	input	TCELL24:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL23:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL24:IMUX.BYP.11
RX_CE_IFD	input	TCELL23:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL23:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1	input	TCELL23:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2	input	TCELL23:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3	input	TCELL23:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4	input	TCELL23:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5	input	TCELL23:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6	input	TCELL23:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7	input	TCELL23:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL23:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0	output	TCELL24:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL24:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL24:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL24:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL24:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL24:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL24:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL24:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL24:OUT.17.TMIN
RX_DATAIN1	input	TCELL23:IMUX.IMUX.29.DELAY
RX_EN_VTC	input	TCELL24:IMUX.BYP.10
RX_INC	input	TCELL24:IMUX.BYP.9
RX_LD	input	TCELL24:IMUX.BYP.8
RX_Q0	output	TCELL23:OUT.19.TMIN
RX_Q1	output	TCELL23:OUT.20.TMIN
RX_Q2	output	TCELL23:OUT.21.TMIN
RX_Q3	output	TCELL23:OUT.22.TMIN
RX_Q4	output	TCELL23:OUT.23.TMIN
RX_Q5	output	TCELL23:OUT.24.TMIN
RX_Q6	output	TCELL23:OUT.25.TMIN
RX_Q7	output	TCELL23:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL24:IMUX.BYP.7
TX_CE_OFD	input	TCELL23:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL23:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL23:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2	input	TCELL23:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3	input	TCELL23:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4	input	TCELL23:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5	input	TCELL23:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6	input	TCELL23:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7	input	TCELL23:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8	input	TCELL23:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0	output	TCELL23:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL23:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL23:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL23:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL23:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL24:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL24:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL24:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL24:OUT.7.TMIN
TX_D0	input	TCELL23:IMUX.IMUX.6.DELAY
TX_D1	input	TCELL23:IMUX.IMUX.31.DELAY
TX_D2	input	TCELL23:IMUX.IMUX.7.DELAY
TX_D3	input	TCELL23:IMUX.IMUX.32.DELAY
TX_D4	input	TCELL23:IMUX.IMUX.33.DELAY
TX_D5	input	TCELL23:IMUX.IMUX.34.DELAY
TX_D6	input	TCELL23:IMUX.IMUX.8.DELAY
TX_D7	input	TCELL23:IMUX.IMUX.35.DELAY
TX_EN_VTC	input	TCELL24:IMUX.BYP.6
TX_INC	input	TCELL23:IMUX.BYP.15
TX_LD	input	TCELL23:IMUX.BYP.14
TX_T	input	TCELL23:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL21:OUT.8.TMIN

Bel BITSLICE20

ultrascale XIPHY bel BITSLICE20
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL24:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INT	input	TCELL25:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL24:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL25:IMUX.BYP.11
RX_CE_IFD	input	TCELL24:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0	input	TCELL24:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL24:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL24:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL24:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL24:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL24:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL24:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL24:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL24:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL25:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL25:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL25:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL25:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL25:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL25:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL25:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL25:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL25:OUT.17.TMIN
RX_DATAIN1	input	TCELL24:IMUX.IMUX.18.DELAY
RX_EN_VTC	input	TCELL25:IMUX.BYP.10
RX_INC	input	TCELL25:IMUX.BYP.9
RX_LD	input	TCELL25:IMUX.BYP.8
RX_Q0	output	TCELL24:OUT.19.TMIN
RX_Q1	output	TCELL24:OUT.20.TMIN
RX_Q2	output	TCELL24:OUT.21.TMIN
RX_Q3	output	TCELL24:OUT.22.TMIN
RX_Q4	output	TCELL24:OUT.23.TMIN
RX_Q5	output	TCELL24:OUT.24.TMIN
RX_Q6	output	TCELL24:OUT.25.TMIN
RX_Q7	output	TCELL24:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL25:IMUX.BYP.7
TX_CE_OFD	input	TCELL24:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0	input	TCELL24:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL24:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL24:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL24:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL24:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL24:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL24:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL24:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL24:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL24:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL24:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL24:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL24:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL24:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL25:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL25:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL25:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL25:OUT.7.TMIN
TX_D0	input	TCELL24:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL24:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL24:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL24:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL24:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL24:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL24:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL24:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL25:IMUX.BYP.6
TX_INC	input	TCELL24:IMUX.BYP.15
TX_LD	input	TCELL24:IMUX.BYP.14
TX_T	input	TCELL23:IMUX.IMUX.15.DELAY
TX_T_OUT	output	TCELL23:OUT.8.TMIN

Bel BITSLICE21

ultrascale XIPHY bel BITSLICE21
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL24:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INT	input	TCELL26:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL25:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL26:IMUX.BYP.11
RX_CE_IFD	input	TCELL24:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0	input	TCELL25:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1	input	TCELL25:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2	input	TCELL25:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3	input	TCELL25:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4	input	TCELL25:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5	input	TCELL25:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6	input	TCELL25:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7	input	TCELL25:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8	input	TCELL25:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0	output	TCELL26:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL26:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL26:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL26:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL26:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL26:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL26:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL26:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL26:OUT.17.TMIN
RX_DATAIN1	input	TCELL24:IMUX.IMUX.12.DELAY
RX_EN_VTC	input	TCELL26:IMUX.BYP.10
RX_INC	input	TCELL26:IMUX.BYP.9
RX_LD	input	TCELL26:IMUX.BYP.8
RX_Q0	output	TCELL25:OUT.19.TMIN
RX_Q1	output	TCELL25:OUT.20.TMIN
RX_Q2	output	TCELL25:OUT.21.TMIN
RX_Q3	output	TCELL25:OUT.22.TMIN
RX_Q4	output	TCELL25:OUT.23.TMIN
RX_Q5	output	TCELL25:OUT.24.TMIN
RX_Q6	output	TCELL25:OUT.25.TMIN
RX_Q7	output	TCELL25:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL26:IMUX.BYP.6
TX_CE_OFD	input	TCELL24:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0	input	TCELL25:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1	input	TCELL25:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2	input	TCELL25:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3	input	TCELL25:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4	input	TCELL25:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5	input	TCELL25:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6	input	TCELL25:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7	input	TCELL25:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8	input	TCELL25:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0	output	TCELL25:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL25:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL25:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL25:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL25:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL26:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL26:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL26:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL26:OUT.7.TMIN
TX_D0	input	TCELL24:IMUX.IMUX.13.DELAY
TX_D1	input	TCELL24:IMUX.IMUX.44.DELAY
TX_D2	input	TCELL24:IMUX.IMUX.45.DELAY
TX_D3	input	TCELL24:IMUX.IMUX.46.DELAY
TX_D4	input	TCELL24:IMUX.IMUX.14.DELAY
TX_D5	input	TCELL24:IMUX.IMUX.47.DELAY
TX_D6	input	TCELL24:IMUX.IMUX.15.DELAY
TX_D7	input	TCELL25:IMUX.IMUX.16.DELAY
TX_EN_VTC	input	TCELL25:IMUX.BYP.15
TX_INC	input	TCELL25:IMUX.BYP.14
TX_LD	input	TCELL25:IMUX.BYP.13
TX_T	input	TCELL24:IMUX.IMUX.40.DELAY
TX_T_OUT	output	TCELL24:OUT.8.TMIN

Bel BITSLICE22

ultrascale XIPHY bel BITSLICE22
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL26:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL28:IMUX.BYP.7
PHY2CLB_FIFO_EMPTY	output	TCELL27:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL28:IMUX.BYP.6
RX_CE_IFD	input	TCELL26:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL26:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1	input	TCELL26:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2	input	TCELL26:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3	input	TCELL26:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4	input	TCELL26:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5	input	TCELL26:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6	input	TCELL26:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7	input	TCELL27:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8	input	TCELL27:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0	output	TCELL27:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL27:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL27:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL27:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL27:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL27:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL27:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL27:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL27:OUT.31.TMIN
RX_DATAIN1	input	TCELL26:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL27:IMUX.BYP.15
RX_INC	input	TCELL27:IMUX.BYP.14
RX_LD	input	TCELL27:IMUX.BYP.13
RX_Q0	output	TCELL27:OUT.5.TMIN
RX_Q1	output	TCELL27:OUT.6.TMIN
RX_Q2	output	TCELL27:OUT.7.TMIN
RX_Q3	output	TCELL27:OUT.8.TMIN
RX_Q4	output	TCELL27:OUT.9.TMIN
RX_Q5	output	TCELL27:OUT.10.TMIN
RX_Q6	output	TCELL27:OUT.11.TMIN
RX_Q7	output	TCELL27:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL27:IMUX.BYP.12
TX_CE_OFD	input	TCELL26:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL26:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL26:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL26:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL26:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL26:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL26:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL26:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL26:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8	input	TCELL26:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0	output	TCELL27:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL27:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL27:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL27:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL27:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL27:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL27:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL27:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL27:OUT.21.TMIN
TX_D0	input	TCELL26:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL26:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL26:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL26:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL26:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL26:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL26:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL26:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL27:IMUX.BYP.11
TX_INC	input	TCELL27:IMUX.BYP.10
TX_LD	input	TCELL27:IMUX.BYP.9
TX_T	input	TCELL26:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL25:OUT.8.TMIN

Bel BITSLICE23

ultrascale XIPHY bel BITSLICE23
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL27:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INT	input	TCELL29:IMUX.BYP.6
PHY2CLB_FIFO_EMPTY	output	TCELL28:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL28:IMUX.BYP.15
RX_CE_IFD	input	TCELL27:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0	input	TCELL27:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL27:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL27:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL27:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL27:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL27:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL27:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL27:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL27:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL28:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL28:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL28:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL28:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL28:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL28:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL28:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL28:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL28:OUT.31.TMIN
RX_DATAIN1	input	TCELL27:IMUX.IMUX.21.DELAY
RX_EN_VTC	input	TCELL28:IMUX.BYP.14
RX_INC	input	TCELL28:IMUX.BYP.13
RX_LD	input	TCELL28:IMUX.BYP.12
RX_Q0	output	TCELL28:OUT.5.TMIN
RX_Q1	output	TCELL28:OUT.6.TMIN
RX_Q2	output	TCELL28:OUT.7.TMIN
RX_Q3	output	TCELL28:OUT.8.TMIN
RX_Q4	output	TCELL28:OUT.9.TMIN
RX_Q5	output	TCELL28:OUT.10.TMIN
RX_Q6	output	TCELL28:OUT.11.TMIN
RX_Q7	output	TCELL28:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL28:IMUX.BYP.11
TX_CE_OFD	input	TCELL27:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0	input	TCELL27:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1	input	TCELL27:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2	input	TCELL27:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3	input	TCELL27:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4	input	TCELL27:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5	input	TCELL27:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6	input	TCELL27:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7	input	TCELL27:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8	input	TCELL27:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0	output	TCELL28:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL28:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL28:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL28:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL28:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL28:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL28:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL28:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL28:OUT.21.TMIN
TX_D0	input	TCELL27:IMUX.IMUX.28.DELAY
TX_D1	input	TCELL27:IMUX.IMUX.27.DELAY
TX_D2	input	TCELL27:IMUX.IMUX.26.DELAY
TX_D3	input	TCELL27:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL27:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL27:IMUX.IMUX.23.DELAY
TX_D6	input	TCELL27:IMUX.IMUX.29.DELAY
TX_D7	input	TCELL27:IMUX.IMUX.30.DELAY
TX_EN_VTC	input	TCELL28:IMUX.BYP.10
TX_INC	input	TCELL28:IMUX.BYP.9
TX_LD	input	TCELL28:IMUX.BYP.8
TX_T	input	TCELL27:IMUX.IMUX.18.DELAY
TX_T_OUT	output	TCELL26:OUT.8.TMIN

Bel BITSLICE24

ultrascale XIPHY bel BITSLICE24
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL27:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INT	input	TCELL29:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL29:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL29:IMUX.BYP.14
RX_CE_IFD	input	TCELL27:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0	input	TCELL29:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1	input	TCELL29:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2	input	TCELL29:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL29:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL29:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5	input	TCELL29:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6	input	TCELL29:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7	input	TCELL29:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL29:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0	output	TCELL29:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL29:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL29:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL29:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL29:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL29:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL29:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL29:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL29:OUT.31.TMIN
RX_DATAIN1	input	TCELL27:IMUX.IMUX.44.DELAY
RX_EN_VTC	input	TCELL29:IMUX.BYP.13
RX_INC	input	TCELL29:IMUX.BYP.12
RX_LD	input	TCELL29:IMUX.BYP.11
RX_Q0	output	TCELL29:OUT.5.TMIN
RX_Q1	output	TCELL29:OUT.6.TMIN
RX_Q2	output	TCELL29:OUT.7.TMIN
RX_Q3	output	TCELL29:OUT.8.TMIN
RX_Q4	output	TCELL29:OUT.9.TMIN
RX_Q5	output	TCELL29:OUT.10.TMIN
RX_Q6	output	TCELL29:OUT.11.TMIN
RX_Q7	output	TCELL29:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL29:IMUX.BYP.10
TX_CE_OFD	input	TCELL27:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0	input	TCELL28:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL28:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2	input	TCELL28:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3	input	TCELL28:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4	input	TCELL28:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5	input	TCELL28:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6	input	TCELL28:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7	input	TCELL29:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8	input	TCELL29:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0	output	TCELL29:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL29:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL29:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL29:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL29:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL29:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL29:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL29:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL29:OUT.21.TMIN
TX_D0	input	TCELL27:IMUX.IMUX.46.DELAY
TX_D1	input	TCELL27:IMUX.IMUX.14.DELAY
TX_D2	input	TCELL27:IMUX.IMUX.47.DELAY
TX_D3	input	TCELL27:IMUX.IMUX.15.DELAY
TX_D4	input	TCELL28:IMUX.IMUX.16.DELAY
TX_D5	input	TCELL28:IMUX.IMUX.6.DELAY
TX_D6	input	TCELL28:IMUX.IMUX.7.DELAY
TX_D7	input	TCELL28:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL29:IMUX.BYP.9
TX_INC	input	TCELL29:IMUX.BYP.8
TX_LD	input	TCELL29:IMUX.BYP.7
TX_T	input	TCELL27:IMUX.IMUX.12.DELAY
TX_T_OUT	output	TCELL26:OUT.31.TMIN

Bel BITSLICE25

ultrascale XIPHY bel BITSLICE25
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL22:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INT	input	TCELL23:IMUX.BYP.13
PHY2CLB_FIFO_EMPTY	output	TCELL22:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL23:IMUX.BYP.12
RX_CE_IFD	input	TCELL22:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0	input	TCELL23:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL23:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL23:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL23:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL23:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL23:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL23:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL23:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL23:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL23:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL23:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL23:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL23:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL23:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL23:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL23:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL23:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL23:OUT.17.TMIN
RX_DATAIN1	input	TCELL22:IMUX.IMUX.9.DELAY
RX_EN_VTC	input	TCELL23:IMUX.BYP.11
RX_INC	input	TCELL23:IMUX.BYP.10
RX_LD	input	TCELL23:IMUX.BYP.9
RX_Q0	output	TCELL22:OUT.19.TMIN
RX_Q1	output	TCELL22:OUT.20.TMIN
RX_Q2	output	TCELL22:OUT.21.TMIN
RX_Q3	output	TCELL22:OUT.22.TMIN
RX_Q4	output	TCELL22:OUT.23.TMIN
RX_Q5	output	TCELL22:OUT.24.TMIN
RX_Q6	output	TCELL22:OUT.25.TMIN
RX_Q7	output	TCELL22:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL23:IMUX.BYP.8
TX_CE_OFD	input	TCELL22:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0	input	TCELL22:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1	input	TCELL22:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2	input	TCELL22:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3	input	TCELL22:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4	input	TCELL22:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5	input	TCELL22:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6	input	TCELL22:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7	input	TCELL22:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8	input	TCELL22:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL22:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL22:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL22:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL22:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL22:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL23:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL23:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL23:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL23:OUT.7.TMIN
TX_D0	input	TCELL22:IMUX.IMUX.37.DELAY
TX_D1	input	TCELL22:IMUX.IMUX.38.DELAY
TX_D2	input	TCELL22:IMUX.IMUX.10.DELAY
TX_D3	input	TCELL22:IMUX.IMUX.39.DELAY
TX_D4	input	TCELL22:IMUX.IMUX.11.DELAY
TX_D5	input	TCELL22:IMUX.IMUX.40.DELAY
TX_D6	input	TCELL22:IMUX.IMUX.41.DELAY
TX_D7	input	TCELL22:IMUX.IMUX.42.DELAY
TX_EN_VTC	input	TCELL23:IMUX.BYP.7
TX_INC	input	TCELL23:IMUX.BYP.6
TX_LD	input	TCELL22:IMUX.BYP.15
TX_T	input	TCELL22:IMUX.IMUX.34.DELAY
TX_T_OUT	output	TCELL27:OUT.22.TMIN

Bel BITSLICE26

ultrascale XIPHY bel BITSLICE26
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL30:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INT	input	TCELL30:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL30:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL30:IMUX.BYP.14
RX_CE_IFD	input	TCELL30:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0	input	TCELL32:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL32:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL32:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL32:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL32:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL32:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL32:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL32:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL32:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL30:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL30:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL30:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL30:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL30:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL30:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL30:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL30:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL30:OUT.31.TMIN
RX_DATAIN1	input	TCELL30:IMUX.IMUX.8.DELAY
RX_EN_VTC	input	TCELL30:IMUX.BYP.13
RX_INC	input	TCELL30:IMUX.BYP.12
RX_LD	input	TCELL30:IMUX.BYP.11
RX_Q0	output	TCELL30:OUT.5.TMIN
RX_Q1	output	TCELL30:OUT.6.TMIN
RX_Q2	output	TCELL30:OUT.7.TMIN
RX_Q3	output	TCELL30:OUT.8.TMIN
RX_Q4	output	TCELL30:OUT.9.TMIN
RX_Q5	output	TCELL30:OUT.10.TMIN
RX_Q6	output	TCELL30:OUT.11.TMIN
RX_Q7	output	TCELL30:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL30:IMUX.BYP.10
TX_CE_OFD	input	TCELL30:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0	input	TCELL31:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1	input	TCELL31:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2	input	TCELL31:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3	input	TCELL31:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4	input	TCELL31:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL31:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6	input	TCELL31:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7	input	TCELL31:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8	input	TCELL31:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL30:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL30:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL30:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL30:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL30:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL30:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL30:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL30:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL30:OUT.21.TMIN
TX_D0	input	TCELL31:IMUX.IMUX.16.DELAY
TX_D1	input	TCELL31:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL30:IMUX.IMUX.15.DELAY
TX_D3	input	TCELL30:IMUX.IMUX.14.DELAY
TX_D4	input	TCELL30:IMUX.IMUX.13.DELAY
TX_D5	input	TCELL30:IMUX.IMUX.12.DELAY
TX_D6	input	TCELL30:IMUX.IMUX.11.DELAY
TX_D7	input	TCELL30:IMUX.IMUX.10.DELAY
TX_EN_VTC	input	TCELL30:IMUX.BYP.9
TX_INC	input	TCELL30:IMUX.BYP.8
TX_LD	input	TCELL30:IMUX.BYP.7
TX_T	input	TCELL30:IMUX.IMUX.16.DELAY
TX_T_OUT	output	TCELL30:OUT.22.TMIN

Bel BITSLICE27

ultrascale XIPHY bel BITSLICE27
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL32:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INT	input	TCELL31:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL31:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL31:IMUX.BYP.14
RX_CE_IFD	input	TCELL32:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL32:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1	input	TCELL32:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2	input	TCELL32:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3	input	TCELL32:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4	input	TCELL32:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5	input	TCELL32:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6	input	TCELL32:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7	input	TCELL32:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8	input	TCELL32:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0	output	TCELL31:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL31:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL31:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL31:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL31:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL31:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL31:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL31:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL31:OUT.31.TMIN
RX_DATAIN1	input	TCELL32:IMUX.IMUX.28.DELAY
RX_EN_VTC	input	TCELL31:IMUX.BYP.13
RX_INC	input	TCELL31:IMUX.BYP.12
RX_LD	input	TCELL31:IMUX.BYP.11
RX_Q0	output	TCELL31:OUT.5.TMIN
RX_Q1	output	TCELL31:OUT.6.TMIN
RX_Q2	output	TCELL31:OUT.7.TMIN
RX_Q3	output	TCELL31:OUT.8.TMIN
RX_Q4	output	TCELL31:OUT.9.TMIN
RX_Q5	output	TCELL31:OUT.10.TMIN
RX_Q6	output	TCELL31:OUT.11.TMIN
RX_Q7	output	TCELL31:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL31:IMUX.BYP.10
TX_CE_OFD	input	TCELL32:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL32:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1	input	TCELL32:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2	input	TCELL32:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3	input	TCELL32:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4	input	TCELL32:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5	input	TCELL32:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6	input	TCELL32:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7	input	TCELL32:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8	input	TCELL32:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0	output	TCELL31:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL31:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL31:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL31:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL31:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL31:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL31:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL31:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL31:OUT.21.TMIN
TX_D0	input	TCELL32:IMUX.IMUX.30.DELAY
TX_D1	input	TCELL32:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL32:IMUX.IMUX.31.DELAY
TX_D3	input	TCELL32:IMUX.IMUX.7.DELAY
TX_D4	input	TCELL32:IMUX.IMUX.32.DELAY
TX_D5	input	TCELL32:IMUX.IMUX.33.DELAY
TX_D6	input	TCELL32:IMUX.IMUX.34.DELAY
TX_D7	input	TCELL32:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL31:IMUX.BYP.9
TX_INC	input	TCELL31:IMUX.BYP.8
TX_LD	input	TCELL31:IMUX.BYP.7
TX_T	input	TCELL32:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL31:OUT.22.TMIN

Bel BITSLICE28

ultrascale XIPHY bel BITSLICE28
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL33:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INT	input	TCELL32:IMUX.BYP.14
PHY2CLB_FIFO_EMPTY	output	TCELL32:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL32:IMUX.BYP.13
RX_CE_IFD	input	TCELL33:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0	input	TCELL33:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL33:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL33:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL33:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL33:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL33:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL33:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL33:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL33:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL32:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL32:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL32:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL32:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL32:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL32:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL32:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL32:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL32:OUT.31.TMIN
RX_DATAIN1	input	TCELL33:IMUX.IMUX.17.DELAY
RX_EN_VTC	input	TCELL32:IMUX.BYP.12
RX_INC	input	TCELL32:IMUX.BYP.11
RX_LD	input	TCELL32:IMUX.BYP.10
RX_Q0	output	TCELL32:OUT.5.TMIN
RX_Q1	output	TCELL32:OUT.6.TMIN
RX_Q2	output	TCELL32:OUT.7.TMIN
RX_Q3	output	TCELL32:OUT.8.TMIN
RX_Q4	output	TCELL32:OUT.9.TMIN
RX_Q5	output	TCELL32:OUT.10.TMIN
RX_Q6	output	TCELL32:OUT.11.TMIN
RX_Q7	output	TCELL32:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL32:IMUX.BYP.9
TX_CE_OFD	input	TCELL32:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0	input	TCELL33:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL33:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL33:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL33:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL33:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL33:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL33:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL33:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL33:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL32:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL32:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL32:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL32:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL32:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL32:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL32:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL32:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL32:OUT.21.TMIN
TX_D0	input	TCELL33:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL33:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL33:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL33:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL33:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL33:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL33:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL33:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL32:IMUX.BYP.8
TX_INC	input	TCELL32:IMUX.BYP.7
TX_LD	input	TCELL32:IMUX.BYP.6
TX_T	input	TCELL32:IMUX.IMUX.47.DELAY
TX_T_OUT	output	TCELL32:OUT.22.TMIN

Bel BITSLICE29

ultrascale XIPHY bel BITSLICE29
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL34:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INT	input	TCELL34:IMUX.BYP.10
PHY2CLB_FIFO_EMPTY	output	TCELL33:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL34:IMUX.BYP.9
RX_CE_IFD	input	TCELL34:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0	input	TCELL35:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1	input	TCELL35:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2	input	TCELL35:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3	input	TCELL35:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4	input	TCELL35:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5	input	TCELL35:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6	input	TCELL35:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7	input	TCELL35:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8	input	TCELL35:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0	output	TCELL34:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL34:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL34:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL34:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL34:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL34:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL34:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL34:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL34:OUT.17.TMIN
RX_DATAIN1	input	TCELL34:IMUX.IMUX.37.DELAY
RX_EN_VTC	input	TCELL34:IMUX.BYP.8
RX_INC	input	TCELL34:IMUX.BYP.7
RX_LD	input	TCELL34:IMUX.BYP.6
RX_Q0	output	TCELL33:OUT.19.TMIN
RX_Q1	output	TCELL33:OUT.20.TMIN
RX_Q2	output	TCELL33:OUT.21.TMIN
RX_Q3	output	TCELL33:OUT.22.TMIN
RX_Q4	output	TCELL33:OUT.23.TMIN
RX_Q5	output	TCELL33:OUT.24.TMIN
RX_Q6	output	TCELL33:OUT.25.TMIN
RX_Q7	output	TCELL33:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL33:IMUX.BYP.15
TX_CE_OFD	input	TCELL34:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0	input	TCELL34:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1	input	TCELL34:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2	input	TCELL34:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3	input	TCELL34:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4	input	TCELL34:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5	input	TCELL34:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6	input	TCELL35:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7	input	TCELL35:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8	input	TCELL35:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0	output	TCELL33:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL33:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL33:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL33:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL33:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL34:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL34:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL34:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL34:OUT.7.TMIN
TX_D0	input	TCELL34:IMUX.IMUX.10.DELAY
TX_D1	input	TCELL34:IMUX.IMUX.39.DELAY
TX_D2	input	TCELL34:IMUX.IMUX.11.DELAY
TX_D3	input	TCELL34:IMUX.IMUX.40.DELAY
TX_D4	input	TCELL34:IMUX.IMUX.41.DELAY
TX_D5	input	TCELL34:IMUX.IMUX.42.DELAY
TX_D6	input	TCELL34:IMUX.IMUX.12.DELAY
TX_D7	input	TCELL34:IMUX.IMUX.13.DELAY
TX_EN_VTC	input	TCELL33:IMUX.BYP.14
TX_INC	input	TCELL33:IMUX.BYP.13
TX_LD	input	TCELL33:IMUX.BYP.12
TX_T	input	TCELL34:IMUX.IMUX.35.DELAY
TX_T_OUT	output	TCELL33:OUT.13.TMIN

Bel BITSLICE30

ultrascale XIPHY bel BITSLICE30
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL35:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL35:IMUX.BYP.9
PHY2CLB_FIFO_EMPTY	output	TCELL34:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL35:IMUX.BYP.8
RX_CE_IFD	input	TCELL35:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL35:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1	input	TCELL35:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2	input	TCELL35:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3	input	TCELL35:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4	input	TCELL35:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5	input	TCELL35:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6	input	TCELL35:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7	input	TCELL35:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8	input	TCELL36:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0	output	TCELL35:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL35:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL35:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL35:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL35:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL35:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL35:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL35:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL35:OUT.17.TMIN
RX_DATAIN1	input	TCELL35:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL35:IMUX.BYP.7
RX_INC	input	TCELL35:IMUX.BYP.6
RX_LD	input	TCELL34:IMUX.BYP.15
RX_Q0	output	TCELL34:OUT.19.TMIN
RX_Q1	output	TCELL34:OUT.20.TMIN
RX_Q2	output	TCELL34:OUT.21.TMIN
RX_Q3	output	TCELL34:OUT.22.TMIN
RX_Q4	output	TCELL34:OUT.23.TMIN
RX_Q5	output	TCELL34:OUT.24.TMIN
RX_Q6	output	TCELL34:OUT.25.TMIN
RX_Q7	output	TCELL34:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL34:IMUX.BYP.14
TX_CE_OFD	input	TCELL35:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL35:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL35:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL35:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL35:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL35:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL35:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL35:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL35:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8	input	TCELL35:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0	output	TCELL34:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL34:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL34:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL34:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL34:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL35:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL35:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL35:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL35:OUT.7.TMIN
TX_D0	input	TCELL35:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL35:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL35:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL35:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL35:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL35:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL35:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL35:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL34:IMUX.BYP.13
TX_INC	input	TCELL34:IMUX.BYP.12
TX_LD	input	TCELL34:IMUX.BYP.11
TX_T	input	TCELL35:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL34:OUT.8.TMIN

Bel BITSLICE31

ultrascale XIPHY bel BITSLICE31
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL36:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INT	input	TCELL36:IMUX.BYP.8
PHY2CLB_FIFO_EMPTY	output	TCELL35:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL36:IMUX.BYP.7
RX_CE_IFD	input	TCELL36:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0	input	TCELL36:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL36:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL36:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL36:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL36:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL36:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL36:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL36:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL36:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL36:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL36:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL36:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL36:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL36:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL36:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL36:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL36:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL36:OUT.17.TMIN
RX_DATAIN1	input	TCELL36:IMUX.IMUX.20.DELAY
RX_EN_VTC	input	TCELL36:IMUX.BYP.6
RX_INC	input	TCELL35:IMUX.BYP.15
RX_LD	input	TCELL35:IMUX.BYP.14
RX_Q0	output	TCELL35:OUT.19.TMIN
RX_Q1	output	TCELL35:OUT.20.TMIN
RX_Q2	output	TCELL35:OUT.21.TMIN
RX_Q3	output	TCELL35:OUT.22.TMIN
RX_Q4	output	TCELL35:OUT.23.TMIN
RX_Q5	output	TCELL35:OUT.24.TMIN
RX_Q6	output	TCELL35:OUT.25.TMIN
RX_Q7	output	TCELL35:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL35:IMUX.BYP.13
TX_CE_OFD	input	TCELL36:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0	input	TCELL36:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1	input	TCELL36:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2	input	TCELL36:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3	input	TCELL36:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4	input	TCELL36:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5	input	TCELL36:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6	input	TCELL36:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7	input	TCELL36:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8	input	TCELL36:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0	output	TCELL35:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL35:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL35:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL35:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL35:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL36:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL36:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL36:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL36:OUT.7.TMIN
TX_D0	input	TCELL36:IMUX.IMUX.22.DELAY
TX_D1	input	TCELL36:IMUX.IMUX.23.DELAY
TX_D2	input	TCELL36:IMUX.IMUX.24.DELAY
TX_D3	input	TCELL36:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL36:IMUX.IMUX.26.DELAY
TX_D5	input	TCELL36:IMUX.IMUX.27.DELAY
TX_D6	input	TCELL36:IMUX.IMUX.28.DELAY
TX_D7	input	TCELL36:IMUX.IMUX.29.DELAY
TX_EN_VTC	input	TCELL35:IMUX.BYP.12
TX_INC	input	TCELL35:IMUX.BYP.11
TX_LD	input	TCELL35:IMUX.BYP.10
TX_T	input	TCELL36:IMUX.IMUX.17.DELAY
TX_T_OUT	output	TCELL35:OUT.8.TMIN

Bel BITSLICE32

ultrascale XIPHY bel BITSLICE32
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL38:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INT	input	TCELL39:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL38:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL39:IMUX.BYP.11
RX_CE_IFD	input	TCELL38:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL38:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1	input	TCELL38:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2	input	TCELL38:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3	input	TCELL38:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4	input	TCELL38:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5	input	TCELL38:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6	input	TCELL38:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7	input	TCELL38:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL38:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0	output	TCELL39:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL39:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL39:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL39:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL39:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL39:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL39:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL39:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL39:OUT.17.TMIN
RX_DATAIN1	input	TCELL38:IMUX.IMUX.29.DELAY
RX_EN_VTC	input	TCELL39:IMUX.BYP.10
RX_INC	input	TCELL39:IMUX.BYP.9
RX_LD	input	TCELL39:IMUX.BYP.8
RX_Q0	output	TCELL38:OUT.19.TMIN
RX_Q1	output	TCELL38:OUT.20.TMIN
RX_Q2	output	TCELL38:OUT.21.TMIN
RX_Q3	output	TCELL38:OUT.22.TMIN
RX_Q4	output	TCELL38:OUT.23.TMIN
RX_Q5	output	TCELL38:OUT.24.TMIN
RX_Q6	output	TCELL38:OUT.25.TMIN
RX_Q7	output	TCELL38:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL39:IMUX.BYP.7
TX_CE_OFD	input	TCELL38:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL38:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL38:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2	input	TCELL38:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3	input	TCELL38:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4	input	TCELL38:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5	input	TCELL38:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6	input	TCELL38:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7	input	TCELL38:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8	input	TCELL38:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0	output	TCELL38:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL38:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL38:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL38:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL38:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL39:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL39:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL39:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL39:OUT.7.TMIN
TX_D0	input	TCELL38:IMUX.IMUX.6.DELAY
TX_D1	input	TCELL38:IMUX.IMUX.31.DELAY
TX_D2	input	TCELL38:IMUX.IMUX.7.DELAY
TX_D3	input	TCELL38:IMUX.IMUX.32.DELAY
TX_D4	input	TCELL38:IMUX.IMUX.33.DELAY
TX_D5	input	TCELL38:IMUX.IMUX.34.DELAY
TX_D6	input	TCELL38:IMUX.IMUX.8.DELAY
TX_D7	input	TCELL38:IMUX.IMUX.35.DELAY
TX_EN_VTC	input	TCELL39:IMUX.BYP.6
TX_INC	input	TCELL38:IMUX.BYP.15
TX_LD	input	TCELL38:IMUX.BYP.14
TX_T	input	TCELL38:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL36:OUT.8.TMIN

Bel BITSLICE33

ultrascale XIPHY bel BITSLICE33
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL39:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INT	input	TCELL40:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL39:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL40:IMUX.BYP.11
RX_CE_IFD	input	TCELL39:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0	input	TCELL39:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL39:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL39:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL39:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL39:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL39:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL39:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL39:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL39:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL40:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL40:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL40:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL40:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL40:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL40:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL40:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL40:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL40:OUT.17.TMIN
RX_DATAIN1	input	TCELL39:IMUX.IMUX.18.DELAY
RX_EN_VTC	input	TCELL40:IMUX.BYP.10
RX_INC	input	TCELL40:IMUX.BYP.9
RX_LD	input	TCELL40:IMUX.BYP.8
RX_Q0	output	TCELL39:OUT.19.TMIN
RX_Q1	output	TCELL39:OUT.20.TMIN
RX_Q2	output	TCELL39:OUT.21.TMIN
RX_Q3	output	TCELL39:OUT.22.TMIN
RX_Q4	output	TCELL39:OUT.23.TMIN
RX_Q5	output	TCELL39:OUT.24.TMIN
RX_Q6	output	TCELL39:OUT.25.TMIN
RX_Q7	output	TCELL39:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL40:IMUX.BYP.7
TX_CE_OFD	input	TCELL39:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0	input	TCELL39:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL39:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL39:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL39:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL39:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL39:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL39:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL39:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL39:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL39:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL39:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL39:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL39:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL39:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL40:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL40:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL40:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL40:OUT.7.TMIN
TX_D0	input	TCELL39:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL39:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL39:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL39:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL39:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL39:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL39:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL39:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL40:IMUX.BYP.6
TX_INC	input	TCELL39:IMUX.BYP.15
TX_LD	input	TCELL39:IMUX.BYP.14
TX_T	input	TCELL38:IMUX.IMUX.15.DELAY
TX_T_OUT	output	TCELL38:OUT.8.TMIN

Bel BITSLICE34

ultrascale XIPHY bel BITSLICE34
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL39:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INT	input	TCELL41:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL40:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL41:IMUX.BYP.11
RX_CE_IFD	input	TCELL39:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0	input	TCELL40:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1	input	TCELL40:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2	input	TCELL40:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3	input	TCELL40:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4	input	TCELL40:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5	input	TCELL40:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6	input	TCELL40:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7	input	TCELL40:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8	input	TCELL40:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0	output	TCELL41:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL41:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL41:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL41:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL41:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL41:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL41:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL41:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL41:OUT.17.TMIN
RX_DATAIN1	input	TCELL39:IMUX.IMUX.12.DELAY
RX_EN_VTC	input	TCELL41:IMUX.BYP.10
RX_INC	input	TCELL41:IMUX.BYP.9
RX_LD	input	TCELL41:IMUX.BYP.8
RX_Q0	output	TCELL40:OUT.19.TMIN
RX_Q1	output	TCELL40:OUT.20.TMIN
RX_Q2	output	TCELL40:OUT.21.TMIN
RX_Q3	output	TCELL40:OUT.22.TMIN
RX_Q4	output	TCELL40:OUT.23.TMIN
RX_Q5	output	TCELL40:OUT.24.TMIN
RX_Q6	output	TCELL40:OUT.25.TMIN
RX_Q7	output	TCELL40:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL41:IMUX.BYP.6
TX_CE_OFD	input	TCELL39:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0	input	TCELL40:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1	input	TCELL40:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2	input	TCELL40:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3	input	TCELL40:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4	input	TCELL40:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5	input	TCELL40:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6	input	TCELL40:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7	input	TCELL40:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8	input	TCELL40:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0	output	TCELL40:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL40:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL40:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL40:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL40:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL41:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL41:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL41:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL41:OUT.7.TMIN
TX_D0	input	TCELL39:IMUX.IMUX.13.DELAY
TX_D1	input	TCELL39:IMUX.IMUX.44.DELAY
TX_D2	input	TCELL39:IMUX.IMUX.45.DELAY
TX_D3	input	TCELL39:IMUX.IMUX.46.DELAY
TX_D4	input	TCELL39:IMUX.IMUX.14.DELAY
TX_D5	input	TCELL39:IMUX.IMUX.47.DELAY
TX_D6	input	TCELL39:IMUX.IMUX.15.DELAY
TX_D7	input	TCELL40:IMUX.IMUX.16.DELAY
TX_EN_VTC	input	TCELL40:IMUX.BYP.15
TX_INC	input	TCELL40:IMUX.BYP.14
TX_LD	input	TCELL40:IMUX.BYP.13
TX_T	input	TCELL39:IMUX.IMUX.40.DELAY
TX_T_OUT	output	TCELL39:OUT.8.TMIN

Bel BITSLICE35

ultrascale XIPHY bel BITSLICE35
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL41:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL43:IMUX.BYP.7
PHY2CLB_FIFO_EMPTY	output	TCELL42:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL43:IMUX.BYP.6
RX_CE_IFD	input	TCELL41:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL41:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1	input	TCELL41:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2	input	TCELL41:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3	input	TCELL41:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4	input	TCELL41:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5	input	TCELL41:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6	input	TCELL41:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7	input	TCELL42:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8	input	TCELL42:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0	output	TCELL42:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL42:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL42:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL42:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL42:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL42:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL42:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL42:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL42:OUT.31.TMIN
RX_DATAIN1	input	TCELL41:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL42:IMUX.BYP.15
RX_INC	input	TCELL42:IMUX.BYP.14
RX_LD	input	TCELL42:IMUX.BYP.13
RX_Q0	output	TCELL42:OUT.5.TMIN
RX_Q1	output	TCELL42:OUT.6.TMIN
RX_Q2	output	TCELL42:OUT.7.TMIN
RX_Q3	output	TCELL42:OUT.8.TMIN
RX_Q4	output	TCELL42:OUT.9.TMIN
RX_Q5	output	TCELL42:OUT.10.TMIN
RX_Q6	output	TCELL42:OUT.11.TMIN
RX_Q7	output	TCELL42:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL42:IMUX.BYP.12
TX_CE_OFD	input	TCELL41:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL41:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL41:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL41:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL41:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL41:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL41:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL41:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL41:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8	input	TCELL41:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0	output	TCELL42:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL42:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL42:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL42:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL42:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL42:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL42:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL42:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL42:OUT.21.TMIN
TX_D0	input	TCELL41:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL41:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL41:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL41:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL41:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL41:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL41:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL41:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL42:IMUX.BYP.11
TX_INC	input	TCELL42:IMUX.BYP.10
TX_LD	input	TCELL42:IMUX.BYP.9
TX_T	input	TCELL41:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL40:OUT.8.TMIN

Bel BITSLICE36

ultrascale XIPHY bel BITSLICE36
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL42:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INT	input	TCELL44:IMUX.BYP.6
PHY2CLB_FIFO_EMPTY	output	TCELL43:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL43:IMUX.BYP.15
RX_CE_IFD	input	TCELL42:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0	input	TCELL42:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL42:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL42:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL42:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL42:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL42:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL42:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL42:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL42:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL43:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL43:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL43:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL43:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL43:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL43:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL43:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL43:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL43:OUT.31.TMIN
RX_DATAIN1	input	TCELL42:IMUX.IMUX.21.DELAY
RX_EN_VTC	input	TCELL43:IMUX.BYP.14
RX_INC	input	TCELL43:IMUX.BYP.13
RX_LD	input	TCELL43:IMUX.BYP.12
RX_Q0	output	TCELL43:OUT.5.TMIN
RX_Q1	output	TCELL43:OUT.6.TMIN
RX_Q2	output	TCELL43:OUT.7.TMIN
RX_Q3	output	TCELL43:OUT.8.TMIN
RX_Q4	output	TCELL43:OUT.9.TMIN
RX_Q5	output	TCELL43:OUT.10.TMIN
RX_Q6	output	TCELL43:OUT.11.TMIN
RX_Q7	output	TCELL43:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL43:IMUX.BYP.11
TX_CE_OFD	input	TCELL42:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0	input	TCELL42:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1	input	TCELL42:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2	input	TCELL42:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3	input	TCELL42:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4	input	TCELL42:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5	input	TCELL42:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6	input	TCELL42:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7	input	TCELL42:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8	input	TCELL42:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0	output	TCELL43:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL43:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL43:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL43:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL43:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL43:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL43:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL43:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL43:OUT.21.TMIN
TX_D0	input	TCELL42:IMUX.IMUX.28.DELAY
TX_D1	input	TCELL42:IMUX.IMUX.27.DELAY
TX_D2	input	TCELL42:IMUX.IMUX.26.DELAY
TX_D3	input	TCELL42:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL42:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL42:IMUX.IMUX.23.DELAY
TX_D6	input	TCELL42:IMUX.IMUX.29.DELAY
TX_D7	input	TCELL42:IMUX.IMUX.30.DELAY
TX_EN_VTC	input	TCELL43:IMUX.BYP.10
TX_INC	input	TCELL43:IMUX.BYP.9
TX_LD	input	TCELL43:IMUX.BYP.8
TX_T	input	TCELL42:IMUX.IMUX.18.DELAY
TX_T_OUT	output	TCELL41:OUT.8.TMIN

Bel BITSLICE37

ultrascale XIPHY bel BITSLICE37
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL42:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INT	input	TCELL44:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL44:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL44:IMUX.BYP.14
RX_CE_IFD	input	TCELL42:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0	input	TCELL44:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1	input	TCELL44:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2	input	TCELL44:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL44:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL44:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5	input	TCELL44:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6	input	TCELL44:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7	input	TCELL44:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL44:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0	output	TCELL44:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL44:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL44:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL44:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL44:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL44:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL44:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL44:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL44:OUT.31.TMIN
RX_DATAIN1	input	TCELL42:IMUX.IMUX.44.DELAY
RX_EN_VTC	input	TCELL44:IMUX.BYP.13
RX_INC	input	TCELL44:IMUX.BYP.12
RX_LD	input	TCELL44:IMUX.BYP.11
RX_Q0	output	TCELL44:OUT.5.TMIN
RX_Q1	output	TCELL44:OUT.6.TMIN
RX_Q2	output	TCELL44:OUT.7.TMIN
RX_Q3	output	TCELL44:OUT.8.TMIN
RX_Q4	output	TCELL44:OUT.9.TMIN
RX_Q5	output	TCELL44:OUT.10.TMIN
RX_Q6	output	TCELL44:OUT.11.TMIN
RX_Q7	output	TCELL44:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL44:IMUX.BYP.10
TX_CE_OFD	input	TCELL42:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0	input	TCELL43:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL43:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2	input	TCELL43:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3	input	TCELL43:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4	input	TCELL43:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5	input	TCELL43:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6	input	TCELL43:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7	input	TCELL44:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8	input	TCELL44:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0	output	TCELL44:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL44:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL44:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL44:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL44:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL44:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL44:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL44:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL44:OUT.21.TMIN
TX_D0	input	TCELL42:IMUX.IMUX.46.DELAY
TX_D1	input	TCELL42:IMUX.IMUX.14.DELAY
TX_D2	input	TCELL42:IMUX.IMUX.47.DELAY
TX_D3	input	TCELL42:IMUX.IMUX.15.DELAY
TX_D4	input	TCELL43:IMUX.IMUX.16.DELAY
TX_D5	input	TCELL43:IMUX.IMUX.6.DELAY
TX_D6	input	TCELL43:IMUX.IMUX.7.DELAY
TX_D7	input	TCELL43:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL44:IMUX.BYP.9
TX_INC	input	TCELL44:IMUX.BYP.8
TX_LD	input	TCELL44:IMUX.BYP.7
TX_T	input	TCELL42:IMUX.IMUX.12.DELAY
TX_T_OUT	output	TCELL41:OUT.31.TMIN

Bel BITSLICE38

ultrascale XIPHY bel BITSLICE38
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL37:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INT	input	TCELL38:IMUX.BYP.13
PHY2CLB_FIFO_EMPTY	output	TCELL37:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL38:IMUX.BYP.12
RX_CE_IFD	input	TCELL37:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0	input	TCELL38:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL38:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL38:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL38:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL38:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL38:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL38:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL38:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL38:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL38:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL38:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL38:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL38:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL38:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL38:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL38:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL38:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL38:OUT.17.TMIN
RX_DATAIN1	input	TCELL37:IMUX.IMUX.9.DELAY
RX_EN_VTC	input	TCELL38:IMUX.BYP.11
RX_INC	input	TCELL38:IMUX.BYP.10
RX_LD	input	TCELL38:IMUX.BYP.9
RX_Q0	output	TCELL37:OUT.19.TMIN
RX_Q1	output	TCELL37:OUT.20.TMIN
RX_Q2	output	TCELL37:OUT.21.TMIN
RX_Q3	output	TCELL37:OUT.22.TMIN
RX_Q4	output	TCELL37:OUT.23.TMIN
RX_Q5	output	TCELL37:OUT.24.TMIN
RX_Q6	output	TCELL37:OUT.25.TMIN
RX_Q7	output	TCELL37:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL38:IMUX.BYP.8
TX_CE_OFD	input	TCELL37:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0	input	TCELL37:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1	input	TCELL37:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2	input	TCELL37:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3	input	TCELL37:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4	input	TCELL37:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5	input	TCELL37:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6	input	TCELL37:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7	input	TCELL37:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8	input	TCELL37:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL37:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL37:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL37:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL37:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL37:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL38:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL38:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL38:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL38:OUT.7.TMIN
TX_D0	input	TCELL37:IMUX.IMUX.37.DELAY
TX_D1	input	TCELL37:IMUX.IMUX.38.DELAY
TX_D2	input	TCELL37:IMUX.IMUX.10.DELAY
TX_D3	input	TCELL37:IMUX.IMUX.39.DELAY
TX_D4	input	TCELL37:IMUX.IMUX.11.DELAY
TX_D5	input	TCELL37:IMUX.IMUX.40.DELAY
TX_D6	input	TCELL37:IMUX.IMUX.41.DELAY
TX_D7	input	TCELL37:IMUX.IMUX.42.DELAY
TX_EN_VTC	input	TCELL38:IMUX.BYP.7
TX_INC	input	TCELL38:IMUX.BYP.6
TX_LD	input	TCELL37:IMUX.BYP.15
TX_T	input	TCELL37:IMUX.IMUX.34.DELAY
TX_T_OUT	output	TCELL42:OUT.22.TMIN

Bel BITSLICE39

ultrascale XIPHY bel BITSLICE39
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL45:IMUX.IMUX.9.DELAY
DYN_DCI_OUT_INT	input	TCELL45:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL45:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL45:IMUX.BYP.14
RX_CE_IFD	input	TCELL45:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN0	input	TCELL47:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL47:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL47:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL47:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL47:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL47:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL47:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL47:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL47:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL45:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL45:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL45:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL45:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL45:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL45:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL45:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL45:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL45:OUT.31.TMIN
RX_DATAIN1	input	TCELL45:IMUX.IMUX.8.DELAY
RX_EN_VTC	input	TCELL45:IMUX.BYP.13
RX_INC	input	TCELL45:IMUX.BYP.12
RX_LD	input	TCELL45:IMUX.BYP.11
RX_Q0	output	TCELL45:OUT.5.TMIN
RX_Q1	output	TCELL45:OUT.6.TMIN
RX_Q2	output	TCELL45:OUT.7.TMIN
RX_Q3	output	TCELL45:OUT.8.TMIN
RX_Q4	output	TCELL45:OUT.9.TMIN
RX_Q5	output	TCELL45:OUT.10.TMIN
RX_Q6	output	TCELL45:OUT.11.TMIN
RX_Q7	output	TCELL45:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL45:IMUX.BYP.10
TX_CE_OFD	input	TCELL45:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN0	input	TCELL46:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN1	input	TCELL46:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN2	input	TCELL46:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN3	input	TCELL46:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN4	input	TCELL46:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL46:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN6	input	TCELL46:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN7	input	TCELL46:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN8	input	TCELL46:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL45:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL45:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL45:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL45:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL45:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL45:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL45:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL45:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL45:OUT.21.TMIN
TX_D0	input	TCELL46:IMUX.IMUX.16.DELAY
TX_D1	input	TCELL46:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL45:IMUX.IMUX.15.DELAY
TX_D3	input	TCELL45:IMUX.IMUX.14.DELAY
TX_D4	input	TCELL45:IMUX.IMUX.13.DELAY
TX_D5	input	TCELL45:IMUX.IMUX.12.DELAY
TX_D6	input	TCELL45:IMUX.IMUX.11.DELAY
TX_D7	input	TCELL45:IMUX.IMUX.10.DELAY
TX_EN_VTC	input	TCELL45:IMUX.BYP.9
TX_INC	input	TCELL45:IMUX.BYP.8
TX_LD	input	TCELL45:IMUX.BYP.7
TX_T	input	TCELL45:IMUX.IMUX.16.DELAY
TX_T_OUT	output	TCELL45:OUT.22.TMIN

Bel BITSLICE40

ultrascale XIPHY bel BITSLICE40
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL47:IMUX.IMUX.29.DELAY
DYN_DCI_OUT_INT	input	TCELL46:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL46:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL46:IMUX.BYP.14
RX_CE_IFD	input	TCELL47:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL47:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN1	input	TCELL47:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN2	input	TCELL47:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN3	input	TCELL47:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN4	input	TCELL47:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN5	input	TCELL47:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN6	input	TCELL47:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN7	input	TCELL47:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN8	input	TCELL47:IMUX.IMUX.14.DELAY
RX_CNTVALUEOUT0	output	TCELL46:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL46:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL46:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL46:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL46:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL46:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL46:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL46:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL46:OUT.31.TMIN
RX_DATAIN1	input	TCELL47:IMUX.IMUX.28.DELAY
RX_EN_VTC	input	TCELL46:IMUX.BYP.13
RX_INC	input	TCELL46:IMUX.BYP.12
RX_LD	input	TCELL46:IMUX.BYP.11
RX_Q0	output	TCELL46:OUT.5.TMIN
RX_Q1	output	TCELL46:OUT.6.TMIN
RX_Q2	output	TCELL46:OUT.7.TMIN
RX_Q3	output	TCELL46:OUT.8.TMIN
RX_Q4	output	TCELL46:OUT.9.TMIN
RX_Q5	output	TCELL46:OUT.10.TMIN
RX_Q6	output	TCELL46:OUT.11.TMIN
RX_Q7	output	TCELL46:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL46:IMUX.BYP.10
TX_CE_OFD	input	TCELL47:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL47:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN1	input	TCELL47:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN2	input	TCELL47:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN3	input	TCELL47:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN4	input	TCELL47:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN5	input	TCELL47:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN6	input	TCELL47:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN7	input	TCELL47:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN8	input	TCELL47:IMUX.IMUX.40.DELAY
TX_CNTVALUEOUT0	output	TCELL46:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL46:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL46:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL46:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL46:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL46:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL46:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL46:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL46:OUT.21.TMIN
TX_D0	input	TCELL47:IMUX.IMUX.30.DELAY
TX_D1	input	TCELL47:IMUX.IMUX.6.DELAY
TX_D2	input	TCELL47:IMUX.IMUX.31.DELAY
TX_D3	input	TCELL47:IMUX.IMUX.7.DELAY
TX_D4	input	TCELL47:IMUX.IMUX.32.DELAY
TX_D5	input	TCELL47:IMUX.IMUX.33.DELAY
TX_D6	input	TCELL47:IMUX.IMUX.34.DELAY
TX_D7	input	TCELL47:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL46:IMUX.BYP.9
TX_INC	input	TCELL46:IMUX.BYP.8
TX_LD	input	TCELL46:IMUX.BYP.7
TX_T	input	TCELL47:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL46:OUT.22.TMIN

Bel BITSLICE41

ultrascale XIPHY bel BITSLICE41
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL48:IMUX.IMUX.18.DELAY
DYN_DCI_OUT_INT	input	TCELL47:IMUX.BYP.14
PHY2CLB_FIFO_EMPTY	output	TCELL47:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL47:IMUX.BYP.13
RX_CE_IFD	input	TCELL48:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN0	input	TCELL48:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL48:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL48:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL48:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL48:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL48:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL48:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL48:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL48:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL47:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL47:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL47:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL47:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL47:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL47:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL47:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL47:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL47:OUT.31.TMIN
RX_DATAIN1	input	TCELL48:IMUX.IMUX.17.DELAY
RX_EN_VTC	input	TCELL47:IMUX.BYP.12
RX_INC	input	TCELL47:IMUX.BYP.11
RX_LD	input	TCELL47:IMUX.BYP.10
RX_Q0	output	TCELL47:OUT.5.TMIN
RX_Q1	output	TCELL47:OUT.6.TMIN
RX_Q2	output	TCELL47:OUT.7.TMIN
RX_Q3	output	TCELL47:OUT.8.TMIN
RX_Q4	output	TCELL47:OUT.9.TMIN
RX_Q5	output	TCELL47:OUT.10.TMIN
RX_Q6	output	TCELL47:OUT.11.TMIN
RX_Q7	output	TCELL47:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL47:IMUX.BYP.9
TX_CE_OFD	input	TCELL47:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN0	input	TCELL48:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL48:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL48:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL48:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL48:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL48:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL48:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL48:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL48:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL47:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL47:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL47:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL47:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL47:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL47:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL47:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL47:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL47:OUT.21.TMIN
TX_D0	input	TCELL48:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL48:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL48:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL48:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL48:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL48:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL48:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL48:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL47:IMUX.BYP.8
TX_INC	input	TCELL47:IMUX.BYP.7
TX_LD	input	TCELL47:IMUX.BYP.6
TX_T	input	TCELL47:IMUX.IMUX.47.DELAY
TX_T_OUT	output	TCELL47:OUT.22.TMIN

Bel BITSLICE42

ultrascale XIPHY bel BITSLICE42
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL49:IMUX.IMUX.38.DELAY
DYN_DCI_OUT_INT	input	TCELL49:IMUX.BYP.10
PHY2CLB_FIFO_EMPTY	output	TCELL48:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL49:IMUX.BYP.9
RX_CE_IFD	input	TCELL49:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN0	input	TCELL50:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN1	input	TCELL50:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN2	input	TCELL50:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN3	input	TCELL50:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN4	input	TCELL50:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN5	input	TCELL50:IMUX.IMUX.24.DELAY
RX_CNTVALUEIN6	input	TCELL50:IMUX.IMUX.25.DELAY
RX_CNTVALUEIN7	input	TCELL50:IMUX.IMUX.26.DELAY
RX_CNTVALUEIN8	input	TCELL50:IMUX.IMUX.27.DELAY
RX_CNTVALUEOUT0	output	TCELL49:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL49:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL49:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL49:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL49:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL49:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL49:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL49:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL49:OUT.17.TMIN
RX_DATAIN1	input	TCELL49:IMUX.IMUX.37.DELAY
RX_EN_VTC	input	TCELL49:IMUX.BYP.8
RX_INC	input	TCELL49:IMUX.BYP.7
RX_LD	input	TCELL49:IMUX.BYP.6
RX_Q0	output	TCELL48:OUT.19.TMIN
RX_Q1	output	TCELL48:OUT.20.TMIN
RX_Q2	output	TCELL48:OUT.21.TMIN
RX_Q3	output	TCELL48:OUT.22.TMIN
RX_Q4	output	TCELL48:OUT.23.TMIN
RX_Q5	output	TCELL48:OUT.24.TMIN
RX_Q6	output	TCELL48:OUT.25.TMIN
RX_Q7	output	TCELL48:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL48:IMUX.BYP.15
TX_CE_OFD	input	TCELL49:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN0	input	TCELL49:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN1	input	TCELL49:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN2	input	TCELL49:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN3	input	TCELL49:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN4	input	TCELL49:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN5	input	TCELL49:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN6	input	TCELL50:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN7	input	TCELL50:IMUX.IMUX.17.DELAY
TX_CNTVALUEIN8	input	TCELL50:IMUX.IMUX.18.DELAY
TX_CNTVALUEOUT0	output	TCELL48:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL48:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL48:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL48:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL48:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL49:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL49:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL49:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL49:OUT.7.TMIN
TX_D0	input	TCELL49:IMUX.IMUX.10.DELAY
TX_D1	input	TCELL49:IMUX.IMUX.39.DELAY
TX_D2	input	TCELL49:IMUX.IMUX.11.DELAY
TX_D3	input	TCELL49:IMUX.IMUX.40.DELAY
TX_D4	input	TCELL49:IMUX.IMUX.41.DELAY
TX_D5	input	TCELL49:IMUX.IMUX.42.DELAY
TX_D6	input	TCELL49:IMUX.IMUX.12.DELAY
TX_D7	input	TCELL49:IMUX.IMUX.13.DELAY
TX_EN_VTC	input	TCELL48:IMUX.BYP.14
TX_INC	input	TCELL48:IMUX.BYP.13
TX_LD	input	TCELL48:IMUX.BYP.12
TX_T	input	TCELL49:IMUX.IMUX.35.DELAY
TX_T_OUT	output	TCELL48:OUT.13.TMIN

Bel BITSLICE43

ultrascale XIPHY bel BITSLICE43
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL50:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL50:IMUX.BYP.9
PHY2CLB_FIFO_EMPTY	output	TCELL49:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL50:IMUX.BYP.8
RX_CE_IFD	input	TCELL50:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL50:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN1	input	TCELL50:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN2	input	TCELL50:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN3	input	TCELL50:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN4	input	TCELL50:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN5	input	TCELL50:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN6	input	TCELL50:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN7	input	TCELL50:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN8	input	TCELL51:IMUX.IMUX.16.DELAY
RX_CNTVALUEOUT0	output	TCELL50:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL50:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL50:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL50:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL50:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL50:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL50:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL50:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL50:OUT.17.TMIN
RX_DATAIN1	input	TCELL50:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL50:IMUX.BYP.7
RX_INC	input	TCELL50:IMUX.BYP.6
RX_LD	input	TCELL49:IMUX.BYP.15
RX_Q0	output	TCELL49:OUT.19.TMIN
RX_Q1	output	TCELL49:OUT.20.TMIN
RX_Q2	output	TCELL49:OUT.21.TMIN
RX_Q3	output	TCELL49:OUT.22.TMIN
RX_Q4	output	TCELL49:OUT.23.TMIN
RX_Q5	output	TCELL49:OUT.24.TMIN
RX_Q6	output	TCELL49:OUT.25.TMIN
RX_Q7	output	TCELL49:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL49:IMUX.BYP.14
TX_CE_OFD	input	TCELL50:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL50:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL50:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL50:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL50:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL50:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL50:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL50:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL50:IMUX.IMUX.42.DELAY
TX_CNTVALUEIN8	input	TCELL50:IMUX.IMUX.12.DELAY
TX_CNTVALUEOUT0	output	TCELL49:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL49:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL49:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL49:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL49:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL50:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL50:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL50:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL50:OUT.7.TMIN
TX_D0	input	TCELL50:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL50:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL50:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL50:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL50:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL50:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL50:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL50:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL49:IMUX.BYP.13
TX_INC	input	TCELL49:IMUX.BYP.12
TX_LD	input	TCELL49:IMUX.BYP.11
TX_T	input	TCELL50:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL49:OUT.8.TMIN

Bel BITSLICE44

ultrascale XIPHY bel BITSLICE44
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL51:IMUX.IMUX.21.DELAY
DYN_DCI_OUT_INT	input	TCELL51:IMUX.BYP.8
PHY2CLB_FIFO_EMPTY	output	TCELL50:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL51:IMUX.BYP.7
RX_CE_IFD	input	TCELL51:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN0	input	TCELL51:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL51:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL51:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL51:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL51:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL51:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL51:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL51:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL51:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL51:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL51:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL51:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL51:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL51:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL51:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL51:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL51:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL51:OUT.17.TMIN
RX_DATAIN1	input	TCELL51:IMUX.IMUX.20.DELAY
RX_EN_VTC	input	TCELL51:IMUX.BYP.6
RX_INC	input	TCELL50:IMUX.BYP.15
RX_LD	input	TCELL50:IMUX.BYP.14
RX_Q0	output	TCELL50:OUT.19.TMIN
RX_Q1	output	TCELL50:OUT.20.TMIN
RX_Q2	output	TCELL50:OUT.21.TMIN
RX_Q3	output	TCELL50:OUT.22.TMIN
RX_Q4	output	TCELL50:OUT.23.TMIN
RX_Q5	output	TCELL50:OUT.24.TMIN
RX_Q6	output	TCELL50:OUT.25.TMIN
RX_Q7	output	TCELL50:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL50:IMUX.BYP.13
TX_CE_OFD	input	TCELL51:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN0	input	TCELL51:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN1	input	TCELL51:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN2	input	TCELL51:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN3	input	TCELL51:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN4	input	TCELL51:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN5	input	TCELL51:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN6	input	TCELL51:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN7	input	TCELL51:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN8	input	TCELL51:IMUX.IMUX.35.DELAY
TX_CNTVALUEOUT0	output	TCELL50:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL50:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL50:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL50:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL50:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL51:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL51:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL51:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL51:OUT.7.TMIN
TX_D0	input	TCELL51:IMUX.IMUX.22.DELAY
TX_D1	input	TCELL51:IMUX.IMUX.23.DELAY
TX_D2	input	TCELL51:IMUX.IMUX.24.DELAY
TX_D3	input	TCELL51:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL51:IMUX.IMUX.26.DELAY
TX_D5	input	TCELL51:IMUX.IMUX.27.DELAY
TX_D6	input	TCELL51:IMUX.IMUX.28.DELAY
TX_D7	input	TCELL51:IMUX.IMUX.29.DELAY
TX_EN_VTC	input	TCELL50:IMUX.BYP.12
TX_INC	input	TCELL50:IMUX.BYP.11
TX_LD	input	TCELL50:IMUX.BYP.10
TX_T	input	TCELL51:IMUX.IMUX.17.DELAY
TX_T_OUT	output	TCELL50:OUT.8.TMIN

Bel BITSLICE45

ultrascale XIPHY bel BITSLICE45
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL53:IMUX.IMUX.30.DELAY
DYN_DCI_OUT_INT	input	TCELL54:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL53:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL54:IMUX.BYP.11
RX_CE_IFD	input	TCELL53:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN0	input	TCELL53:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN1	input	TCELL53:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN2	input	TCELL53:IMUX.IMUX.43.DELAY
RX_CNTVALUEIN3	input	TCELL53:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN4	input	TCELL53:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN5	input	TCELL53:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN6	input	TCELL53:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN7	input	TCELL53:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL53:IMUX.IMUX.47.DELAY
RX_CNTVALUEOUT0	output	TCELL54:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL54:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL54:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL54:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL54:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL54:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL54:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL54:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL54:OUT.17.TMIN
RX_DATAIN1	input	TCELL53:IMUX.IMUX.29.DELAY
RX_EN_VTC	input	TCELL54:IMUX.BYP.10
RX_INC	input	TCELL54:IMUX.BYP.9
RX_LD	input	TCELL54:IMUX.BYP.8
RX_Q0	output	TCELL53:OUT.19.TMIN
RX_Q1	output	TCELL53:OUT.20.TMIN
RX_Q2	output	TCELL53:OUT.21.TMIN
RX_Q3	output	TCELL53:OUT.22.TMIN
RX_Q4	output	TCELL53:OUT.23.TMIN
RX_Q5	output	TCELL53:OUT.24.TMIN
RX_Q6	output	TCELL53:OUT.25.TMIN
RX_Q7	output	TCELL53:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL54:IMUX.BYP.7
TX_CE_OFD	input	TCELL53:IMUX.IMUX.26.DELAY
TX_CNTVALUEIN0	input	TCELL53:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL53:IMUX.IMUX.36.DELAY
TX_CNTVALUEIN2	input	TCELL53:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN3	input	TCELL53:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN4	input	TCELL53:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN5	input	TCELL53:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN6	input	TCELL53:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN7	input	TCELL53:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN8	input	TCELL53:IMUX.IMUX.41.DELAY
TX_CNTVALUEOUT0	output	TCELL53:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL53:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL53:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL53:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL53:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL54:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL54:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL54:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL54:OUT.7.TMIN
TX_D0	input	TCELL53:IMUX.IMUX.6.DELAY
TX_D1	input	TCELL53:IMUX.IMUX.31.DELAY
TX_D2	input	TCELL53:IMUX.IMUX.7.DELAY
TX_D3	input	TCELL53:IMUX.IMUX.32.DELAY
TX_D4	input	TCELL53:IMUX.IMUX.33.DELAY
TX_D5	input	TCELL53:IMUX.IMUX.34.DELAY
TX_D6	input	TCELL53:IMUX.IMUX.8.DELAY
TX_D7	input	TCELL53:IMUX.IMUX.35.DELAY
TX_EN_VTC	input	TCELL54:IMUX.BYP.6
TX_INC	input	TCELL53:IMUX.BYP.15
TX_LD	input	TCELL53:IMUX.BYP.14
TX_T	input	TCELL53:IMUX.IMUX.25.DELAY
TX_T_OUT	output	TCELL51:OUT.8.TMIN

Bel BITSLICE46

ultrascale XIPHY bel BITSLICE46
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL54:IMUX.IMUX.19.DELAY
DYN_DCI_OUT_INT	input	TCELL55:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL54:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL55:IMUX.BYP.11
RX_CE_IFD	input	TCELL54:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN0	input	TCELL54:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN1	input	TCELL54:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN2	input	TCELL54:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL54:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN4	input	TCELL54:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN5	input	TCELL54:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN6	input	TCELL54:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN7	input	TCELL54:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN8	input	TCELL54:IMUX.IMUX.11.DELAY
RX_CNTVALUEOUT0	output	TCELL55:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL55:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL55:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL55:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL55:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL55:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL55:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL55:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL55:OUT.17.TMIN
RX_DATAIN1	input	TCELL54:IMUX.IMUX.18.DELAY
RX_EN_VTC	input	TCELL55:IMUX.BYP.10
RX_INC	input	TCELL55:IMUX.BYP.9
RX_LD	input	TCELL55:IMUX.BYP.8
RX_Q0	output	TCELL54:OUT.19.TMIN
RX_Q1	output	TCELL54:OUT.20.TMIN
RX_Q2	output	TCELL54:OUT.21.TMIN
RX_Q3	output	TCELL54:OUT.22.TMIN
RX_Q4	output	TCELL54:OUT.23.TMIN
RX_Q5	output	TCELL54:OUT.24.TMIN
RX_Q6	output	TCELL54:OUT.25.TMIN
RX_Q7	output	TCELL54:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL55:IMUX.BYP.7
TX_CE_OFD	input	TCELL54:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN0	input	TCELL54:IMUX.IMUX.28.DELAY
TX_CNTVALUEIN1	input	TCELL54:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN2	input	TCELL54:IMUX.IMUX.30.DELAY
TX_CNTVALUEIN3	input	TCELL54:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN4	input	TCELL54:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN5	input	TCELL54:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN6	input	TCELL54:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN7	input	TCELL54:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN8	input	TCELL54:IMUX.IMUX.34.DELAY
TX_CNTVALUEOUT0	output	TCELL54:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL54:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL54:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL54:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL54:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL55:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL55:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL55:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL55:OUT.7.TMIN
TX_D0	input	TCELL54:IMUX.IMUX.20.DELAY
TX_D1	input	TCELL54:IMUX.IMUX.21.DELAY
TX_D2	input	TCELL54:IMUX.IMUX.22.DELAY
TX_D3	input	TCELL54:IMUX.IMUX.23.DELAY
TX_D4	input	TCELL54:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL54:IMUX.IMUX.25.DELAY
TX_D6	input	TCELL54:IMUX.IMUX.26.DELAY
TX_D7	input	TCELL54:IMUX.IMUX.27.DELAY
TX_EN_VTC	input	TCELL55:IMUX.BYP.6
TX_INC	input	TCELL54:IMUX.BYP.15
TX_LD	input	TCELL54:IMUX.BYP.14
TX_T	input	TCELL53:IMUX.IMUX.15.DELAY
TX_T_OUT	output	TCELL53:OUT.8.TMIN

Bel BITSLICE47

ultrascale XIPHY bel BITSLICE47
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL54:IMUX.IMUX.43.DELAY
DYN_DCI_OUT_INT	input	TCELL56:IMUX.BYP.12
PHY2CLB_FIFO_EMPTY	output	TCELL55:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL56:IMUX.BYP.11
RX_CE_IFD	input	TCELL54:IMUX.IMUX.42.DELAY
RX_CNTVALUEIN0	input	TCELL55:IMUX.IMUX.27.DELAY
RX_CNTVALUEIN1	input	TCELL55:IMUX.IMUX.28.DELAY
RX_CNTVALUEIN2	input	TCELL55:IMUX.IMUX.29.DELAY
RX_CNTVALUEIN3	input	TCELL55:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN4	input	TCELL55:IMUX.IMUX.6.DELAY
RX_CNTVALUEIN5	input	TCELL55:IMUX.IMUX.31.DELAY
RX_CNTVALUEIN6	input	TCELL55:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN7	input	TCELL55:IMUX.IMUX.32.DELAY
RX_CNTVALUEIN8	input	TCELL55:IMUX.IMUX.33.DELAY
RX_CNTVALUEOUT0	output	TCELL56:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL56:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL56:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL56:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL56:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL56:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL56:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL56:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL56:OUT.17.TMIN
RX_DATAIN1	input	TCELL54:IMUX.IMUX.12.DELAY
RX_EN_VTC	input	TCELL56:IMUX.BYP.10
RX_INC	input	TCELL56:IMUX.BYP.9
RX_LD	input	TCELL56:IMUX.BYP.8
RX_Q0	output	TCELL55:OUT.19.TMIN
RX_Q1	output	TCELL55:OUT.20.TMIN
RX_Q2	output	TCELL55:OUT.21.TMIN
RX_Q3	output	TCELL55:OUT.22.TMIN
RX_Q4	output	TCELL55:OUT.23.TMIN
RX_Q5	output	TCELL55:OUT.24.TMIN
RX_Q6	output	TCELL55:OUT.25.TMIN
RX_Q7	output	TCELL55:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL56:IMUX.BYP.6
TX_CE_OFD	input	TCELL54:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN0	input	TCELL55:IMUX.IMUX.18.DELAY
TX_CNTVALUEIN1	input	TCELL55:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN2	input	TCELL55:IMUX.IMUX.20.DELAY
TX_CNTVALUEIN3	input	TCELL55:IMUX.IMUX.21.DELAY
TX_CNTVALUEIN4	input	TCELL55:IMUX.IMUX.22.DELAY
TX_CNTVALUEIN5	input	TCELL55:IMUX.IMUX.23.DELAY
TX_CNTVALUEIN6	input	TCELL55:IMUX.IMUX.24.DELAY
TX_CNTVALUEIN7	input	TCELL55:IMUX.IMUX.25.DELAY
TX_CNTVALUEIN8	input	TCELL55:IMUX.IMUX.26.DELAY
TX_CNTVALUEOUT0	output	TCELL55:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL55:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL55:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL55:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL55:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL56:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL56:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL56:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL56:OUT.7.TMIN
TX_D0	input	TCELL54:IMUX.IMUX.13.DELAY
TX_D1	input	TCELL54:IMUX.IMUX.44.DELAY
TX_D2	input	TCELL54:IMUX.IMUX.45.DELAY
TX_D3	input	TCELL54:IMUX.IMUX.46.DELAY
TX_D4	input	TCELL54:IMUX.IMUX.14.DELAY
TX_D5	input	TCELL54:IMUX.IMUX.47.DELAY
TX_D6	input	TCELL54:IMUX.IMUX.15.DELAY
TX_D7	input	TCELL55:IMUX.IMUX.16.DELAY
TX_EN_VTC	input	TCELL55:IMUX.BYP.15
TX_INC	input	TCELL55:IMUX.BYP.14
TX_LD	input	TCELL55:IMUX.BYP.13
TX_T	input	TCELL54:IMUX.IMUX.40.DELAY
TX_T_OUT	output	TCELL54:OUT.8.TMIN

Bel BITSLICE48

ultrascale XIPHY bel BITSLICE48
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL56:IMUX.IMUX.31.DELAY
DYN_DCI_OUT_INT	input	TCELL58:IMUX.BYP.7
PHY2CLB_FIFO_EMPTY	output	TCELL57:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL58:IMUX.BYP.6
RX_CE_IFD	input	TCELL56:IMUX.IMUX.30.DELAY
RX_CNTVALUEIN0	input	TCELL56:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN1	input	TCELL56:IMUX.IMUX.44.DELAY
RX_CNTVALUEIN2	input	TCELL56:IMUX.IMUX.45.DELAY
RX_CNTVALUEIN3	input	TCELL56:IMUX.IMUX.46.DELAY
RX_CNTVALUEIN4	input	TCELL56:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN5	input	TCELL56:IMUX.IMUX.47.DELAY
RX_CNTVALUEIN6	input	TCELL56:IMUX.IMUX.15.DELAY
RX_CNTVALUEIN7	input	TCELL57:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN8	input	TCELL57:IMUX.IMUX.17.DELAY
RX_CNTVALUEOUT0	output	TCELL57:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL57:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL57:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL57:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL57:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL57:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL57:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL57:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL57:OUT.31.TMIN
RX_DATAIN1	input	TCELL56:IMUX.IMUX.6.DELAY
RX_EN_VTC	input	TCELL57:IMUX.BYP.15
RX_INC	input	TCELL57:IMUX.BYP.14
RX_LD	input	TCELL57:IMUX.BYP.13
RX_Q0	output	TCELL57:OUT.5.TMIN
RX_Q1	output	TCELL57:OUT.6.TMIN
RX_Q2	output	TCELL57:OUT.7.TMIN
RX_Q3	output	TCELL57:OUT.8.TMIN
RX_Q4	output	TCELL57:OUT.9.TMIN
RX_Q5	output	TCELL57:OUT.10.TMIN
RX_Q6	output	TCELL57:OUT.11.TMIN
RX_Q7	output	TCELL57:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL57:IMUX.BYP.12
TX_CE_OFD	input	TCELL56:IMUX.IMUX.29.DELAY
TX_CNTVALUEIN0	input	TCELL56:IMUX.IMUX.37.DELAY
TX_CNTVALUEIN1	input	TCELL56:IMUX.IMUX.38.DELAY
TX_CNTVALUEIN2	input	TCELL56:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN3	input	TCELL56:IMUX.IMUX.39.DELAY
TX_CNTVALUEIN4	input	TCELL56:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN5	input	TCELL56:IMUX.IMUX.40.DELAY
TX_CNTVALUEIN6	input	TCELL56:IMUX.IMUX.41.DELAY
TX_CNTVALUEIN7	input	TCELL56:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN8	input	TCELL56:IMUX.IMUX.43.DELAY
TX_CNTVALUEOUT0	output	TCELL57:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL57:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL57:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL57:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL57:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL57:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL57:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL57:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL57:OUT.21.TMIN
TX_D0	input	TCELL56:IMUX.IMUX.7.DELAY
TX_D1	input	TCELL56:IMUX.IMUX.32.DELAY
TX_D2	input	TCELL56:IMUX.IMUX.33.DELAY
TX_D3	input	TCELL56:IMUX.IMUX.34.DELAY
TX_D4	input	TCELL56:IMUX.IMUX.8.DELAY
TX_D5	input	TCELL56:IMUX.IMUX.35.DELAY
TX_D6	input	TCELL56:IMUX.IMUX.9.DELAY
TX_D7	input	TCELL56:IMUX.IMUX.36.DELAY
TX_EN_VTC	input	TCELL57:IMUX.BYP.11
TX_INC	input	TCELL57:IMUX.BYP.10
TX_LD	input	TCELL57:IMUX.BYP.9
TX_T	input	TCELL56:IMUX.IMUX.28.DELAY
TX_T_OUT	output	TCELL55:OUT.8.TMIN

Bel BITSLICE49

ultrascale XIPHY bel BITSLICE49
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL57:IMUX.IMUX.22.DELAY
DYN_DCI_OUT_INT	input	TCELL59:IMUX.BYP.6
PHY2CLB_FIFO_EMPTY	output	TCELL58:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL58:IMUX.BYP.15
RX_CE_IFD	input	TCELL57:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN0	input	TCELL57:IMUX.IMUX.36.DELAY
RX_CNTVALUEIN1	input	TCELL57:IMUX.IMUX.37.DELAY
RX_CNTVALUEIN2	input	TCELL57:IMUX.IMUX.38.DELAY
RX_CNTVALUEIN3	input	TCELL57:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL57:IMUX.IMUX.39.DELAY
RX_CNTVALUEIN5	input	TCELL57:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN6	input	TCELL57:IMUX.IMUX.40.DELAY
RX_CNTVALUEIN7	input	TCELL57:IMUX.IMUX.41.DELAY
RX_CNTVALUEIN8	input	TCELL57:IMUX.IMUX.42.DELAY
RX_CNTVALUEOUT0	output	TCELL58:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL58:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL58:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL58:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL58:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL58:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL58:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL58:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL58:OUT.31.TMIN
RX_DATAIN1	input	TCELL57:IMUX.IMUX.21.DELAY
RX_EN_VTC	input	TCELL58:IMUX.BYP.14
RX_INC	input	TCELL58:IMUX.BYP.13
RX_LD	input	TCELL58:IMUX.BYP.12
RX_Q0	output	TCELL58:OUT.5.TMIN
RX_Q1	output	TCELL58:OUT.6.TMIN
RX_Q2	output	TCELL58:OUT.7.TMIN
RX_Q3	output	TCELL58:OUT.8.TMIN
RX_Q4	output	TCELL58:OUT.9.TMIN
RX_Q5	output	TCELL58:OUT.10.TMIN
RX_Q6	output	TCELL58:OUT.11.TMIN
RX_Q7	output	TCELL58:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL58:IMUX.BYP.11
TX_CE_OFD	input	TCELL57:IMUX.IMUX.19.DELAY
TX_CNTVALUEIN0	input	TCELL57:IMUX.IMUX.6.DELAY
TX_CNTVALUEIN1	input	TCELL57:IMUX.IMUX.31.DELAY
TX_CNTVALUEIN2	input	TCELL57:IMUX.IMUX.7.DELAY
TX_CNTVALUEIN3	input	TCELL57:IMUX.IMUX.32.DELAY
TX_CNTVALUEIN4	input	TCELL57:IMUX.IMUX.33.DELAY
TX_CNTVALUEIN5	input	TCELL57:IMUX.IMUX.34.DELAY
TX_CNTVALUEIN6	input	TCELL57:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN7	input	TCELL57:IMUX.IMUX.35.DELAY
TX_CNTVALUEIN8	input	TCELL57:IMUX.IMUX.9.DELAY
TX_CNTVALUEOUT0	output	TCELL58:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL58:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL58:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL58:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL58:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL58:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL58:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL58:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL58:OUT.21.TMIN
TX_D0	input	TCELL57:IMUX.IMUX.28.DELAY
TX_D1	input	TCELL57:IMUX.IMUX.27.DELAY
TX_D2	input	TCELL57:IMUX.IMUX.26.DELAY
TX_D3	input	TCELL57:IMUX.IMUX.25.DELAY
TX_D4	input	TCELL57:IMUX.IMUX.24.DELAY
TX_D5	input	TCELL57:IMUX.IMUX.23.DELAY
TX_D6	input	TCELL57:IMUX.IMUX.29.DELAY
TX_D7	input	TCELL57:IMUX.IMUX.30.DELAY
TX_EN_VTC	input	TCELL58:IMUX.BYP.10
TX_INC	input	TCELL58:IMUX.BYP.9
TX_LD	input	TCELL58:IMUX.BYP.8
TX_T	input	TCELL57:IMUX.IMUX.18.DELAY
TX_T_OUT	output	TCELL56:OUT.8.TMIN

Bel BITSLICE50

ultrascale XIPHY bel BITSLICE50
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL57:IMUX.IMUX.45.DELAY
DYN_DCI_OUT_INT	input	TCELL59:IMUX.BYP.15
PHY2CLB_FIFO_EMPTY	output	TCELL59:OUT.4.TMIN
RX_CE_IDELAY	input	TCELL59:IMUX.BYP.14
RX_CE_IFD	input	TCELL57:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN0	input	TCELL59:IMUX.IMUX.7.DELAY
RX_CNTVALUEIN1	input	TCELL59:IMUX.IMUX.8.DELAY
RX_CNTVALUEIN2	input	TCELL59:IMUX.IMUX.9.DELAY
RX_CNTVALUEIN3	input	TCELL59:IMUX.IMUX.10.DELAY
RX_CNTVALUEIN4	input	TCELL59:IMUX.IMUX.11.DELAY
RX_CNTVALUEIN5	input	TCELL59:IMUX.IMUX.12.DELAY
RX_CNTVALUEIN6	input	TCELL59:IMUX.IMUX.13.DELAY
RX_CNTVALUEIN7	input	TCELL59:IMUX.IMUX.14.DELAY
RX_CNTVALUEIN8	input	TCELL59:IMUX.IMUX.15.DELAY
RX_CNTVALUEOUT0	output	TCELL59:OUT.23.TMIN
RX_CNTVALUEOUT1	output	TCELL59:OUT.24.TMIN
RX_CNTVALUEOUT2	output	TCELL59:OUT.25.TMIN
RX_CNTVALUEOUT3	output	TCELL59:OUT.26.TMIN
RX_CNTVALUEOUT4	output	TCELL59:OUT.27.TMIN
RX_CNTVALUEOUT5	output	TCELL59:OUT.28.TMIN
RX_CNTVALUEOUT6	output	TCELL59:OUT.29.TMIN
RX_CNTVALUEOUT7	output	TCELL59:OUT.30.TMIN
RX_CNTVALUEOUT8	output	TCELL59:OUT.31.TMIN
RX_DATAIN1	input	TCELL57:IMUX.IMUX.44.DELAY
RX_EN_VTC	input	TCELL59:IMUX.BYP.13
RX_INC	input	TCELL59:IMUX.BYP.12
RX_LD	input	TCELL59:IMUX.BYP.11
RX_Q0	output	TCELL59:OUT.5.TMIN
RX_Q1	output	TCELL59:OUT.6.TMIN
RX_Q2	output	TCELL59:OUT.7.TMIN
RX_Q3	output	TCELL59:OUT.8.TMIN
RX_Q4	output	TCELL59:OUT.9.TMIN
RX_Q5	output	TCELL59:OUT.10.TMIN
RX_Q6	output	TCELL59:OUT.11.TMIN
RX_Q7	output	TCELL59:OUT.12.TMIN
TX_CE_ODELAY	input	TCELL59:IMUX.BYP.10
TX_CE_OFD	input	TCELL57:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN0	input	TCELL58:IMUX.IMUX.9.DELAY
TX_CNTVALUEIN1	input	TCELL58:IMUX.IMUX.10.DELAY
TX_CNTVALUEIN2	input	TCELL58:IMUX.IMUX.11.DELAY
TX_CNTVALUEIN3	input	TCELL58:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN4	input	TCELL58:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN5	input	TCELL58:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN6	input	TCELL58:IMUX.IMUX.15.DELAY
TX_CNTVALUEIN7	input	TCELL59:IMUX.IMUX.16.DELAY
TX_CNTVALUEIN8	input	TCELL59:IMUX.IMUX.6.DELAY
TX_CNTVALUEOUT0	output	TCELL59:OUT.13.TMIN
TX_CNTVALUEOUT1	output	TCELL59:OUT.14.TMIN
TX_CNTVALUEOUT2	output	TCELL59:OUT.15.TMIN
TX_CNTVALUEOUT3	output	TCELL59:OUT.16.TMIN
TX_CNTVALUEOUT4	output	TCELL59:OUT.17.TMIN
TX_CNTVALUEOUT5	output	TCELL59:OUT.18.TMIN
TX_CNTVALUEOUT6	output	TCELL59:OUT.19.TMIN
TX_CNTVALUEOUT7	output	TCELL59:OUT.20.TMIN
TX_CNTVALUEOUT8	output	TCELL59:OUT.21.TMIN
TX_D0	input	TCELL57:IMUX.IMUX.46.DELAY
TX_D1	input	TCELL57:IMUX.IMUX.14.DELAY
TX_D2	input	TCELL57:IMUX.IMUX.47.DELAY
TX_D3	input	TCELL57:IMUX.IMUX.15.DELAY
TX_D4	input	TCELL58:IMUX.IMUX.16.DELAY
TX_D5	input	TCELL58:IMUX.IMUX.6.DELAY
TX_D6	input	TCELL58:IMUX.IMUX.7.DELAY
TX_D7	input	TCELL58:IMUX.IMUX.8.DELAY
TX_EN_VTC	input	TCELL59:IMUX.BYP.9
TX_INC	input	TCELL59:IMUX.BYP.8
TX_LD	input	TCELL59:IMUX.BYP.7
TX_T	input	TCELL57:IMUX.IMUX.12.DELAY
TX_T_OUT	output	TCELL56:OUT.31.TMIN

Bel BITSLICE51

ultrascale XIPHY bel BITSLICE51
Pin	Direction	Wires
CLB2PHY_FIFO_RDEN	input	TCELL52:IMUX.IMUX.36.DELAY
DYN_DCI_OUT_INT	input	TCELL53:IMUX.BYP.13
PHY2CLB_FIFO_EMPTY	output	TCELL52:OUT.18.TMIN
RX_CE_IDELAY	input	TCELL53:IMUX.BYP.12
RX_CE_IFD	input	TCELL52:IMUX.IMUX.35.DELAY
RX_CNTVALUEIN0	input	TCELL53:IMUX.IMUX.16.DELAY
RX_CNTVALUEIN1	input	TCELL53:IMUX.IMUX.17.DELAY
RX_CNTVALUEIN2	input	TCELL53:IMUX.IMUX.18.DELAY
RX_CNTVALUEIN3	input	TCELL53:IMUX.IMUX.19.DELAY
RX_CNTVALUEIN4	input	TCELL53:IMUX.IMUX.20.DELAY
RX_CNTVALUEIN5	input	TCELL53:IMUX.IMUX.21.DELAY
RX_CNTVALUEIN6	input	TCELL53:IMUX.IMUX.22.DELAY
RX_CNTVALUEIN7	input	TCELL53:IMUX.IMUX.23.DELAY
RX_CNTVALUEIN8	input	TCELL53:IMUX.IMUX.24.DELAY
RX_CNTVALUEOUT0	output	TCELL53:OUT.9.TMIN
RX_CNTVALUEOUT1	output	TCELL53:OUT.10.TMIN
RX_CNTVALUEOUT2	output	TCELL53:OUT.11.TMIN
RX_CNTVALUEOUT3	output	TCELL53:OUT.12.TMIN
RX_CNTVALUEOUT4	output	TCELL53:OUT.13.TMIN
RX_CNTVALUEOUT5	output	TCELL53:OUT.14.TMIN
RX_CNTVALUEOUT6	output	TCELL53:OUT.15.TMIN
RX_CNTVALUEOUT7	output	TCELL53:OUT.16.TMIN
RX_CNTVALUEOUT8	output	TCELL53:OUT.17.TMIN
RX_DATAIN1	input	TCELL52:IMUX.IMUX.9.DELAY
RX_EN_VTC	input	TCELL53:IMUX.BYP.11
RX_INC	input	TCELL53:IMUX.BYP.10
RX_LD	input	TCELL53:IMUX.BYP.9
RX_Q0	output	TCELL52:OUT.19.TMIN
RX_Q1	output	TCELL52:OUT.20.TMIN
RX_Q2	output	TCELL52:OUT.21.TMIN
RX_Q3	output	TCELL52:OUT.22.TMIN
RX_Q4	output	TCELL52:OUT.23.TMIN
RX_Q5	output	TCELL52:OUT.24.TMIN
RX_Q6	output	TCELL52:OUT.25.TMIN
RX_Q7	output	TCELL52:OUT.26.TMIN
TX_CE_ODELAY	input	TCELL53:IMUX.BYP.8
TX_CE_OFD	input	TCELL52:IMUX.IMUX.8.DELAY
TX_CNTVALUEIN0	input	TCELL52:IMUX.IMUX.12.DELAY
TX_CNTVALUEIN1	input	TCELL52:IMUX.IMUX.43.DELAY
TX_CNTVALUEIN2	input	TCELL52:IMUX.IMUX.13.DELAY
TX_CNTVALUEIN3	input	TCELL52:IMUX.IMUX.44.DELAY
TX_CNTVALUEIN4	input	TCELL52:IMUX.IMUX.45.DELAY
TX_CNTVALUEIN5	input	TCELL52:IMUX.IMUX.46.DELAY
TX_CNTVALUEIN6	input	TCELL52:IMUX.IMUX.14.DELAY
TX_CNTVALUEIN7	input	TCELL52:IMUX.IMUX.47.DELAY
TX_CNTVALUEIN8	input	TCELL52:IMUX.IMUX.15.DELAY
TX_CNTVALUEOUT0	output	TCELL52:OUT.27.TMIN
TX_CNTVALUEOUT1	output	TCELL52:OUT.28.TMIN
TX_CNTVALUEOUT2	output	TCELL52:OUT.29.TMIN
TX_CNTVALUEOUT3	output	TCELL52:OUT.30.TMIN
TX_CNTVALUEOUT4	output	TCELL52:OUT.31.TMIN
TX_CNTVALUEOUT5	output	TCELL53:OUT.4.TMIN
TX_CNTVALUEOUT6	output	TCELL53:OUT.5.TMIN
TX_CNTVALUEOUT7	output	TCELL53:OUT.6.TMIN
TX_CNTVALUEOUT8	output	TCELL53:OUT.7.TMIN
TX_D0	input	TCELL52:IMUX.IMUX.37.DELAY
TX_D1	input	TCELL52:IMUX.IMUX.38.DELAY
TX_D2	input	TCELL52:IMUX.IMUX.10.DELAY
TX_D3	input	TCELL52:IMUX.IMUX.39.DELAY
TX_D4	input	TCELL52:IMUX.IMUX.11.DELAY
TX_D5	input	TCELL52:IMUX.IMUX.40.DELAY
TX_D6	input	TCELL52:IMUX.IMUX.41.DELAY
TX_D7	input	TCELL52:IMUX.IMUX.42.DELAY
TX_EN_VTC	input	TCELL53:IMUX.BYP.7
TX_INC	input	TCELL53:IMUX.BYP.6
TX_LD	input	TCELL52:IMUX.BYP.15
TX_T	input	TCELL52:IMUX.IMUX.34.DELAY
TX_T_OUT	output	TCELL57:OUT.22.TMIN

Bel BITSLICE_T0

ultrascale XIPHY bel BITSLICE_T0
Pin	Direction	Wires
CE_ODELAY	input	TCELL3:IMUX.BYP.8
CE_OFD	input	TCELL2:IMUX.BYP.15
CNTVALUEIN0	input	TCELL3:IMUX.IMUX.40.DELAY
CNTVALUEIN1	input	TCELL3:IMUX.IMUX.41.DELAY
CNTVALUEIN2	input	TCELL3:IMUX.IMUX.42.DELAY
CNTVALUEIN3	input	TCELL3:IMUX.IMUX.12.DELAY
CNTVALUEIN4	input	TCELL3:IMUX.IMUX.43.DELAY
CNTVALUEIN5	input	TCELL3:IMUX.IMUX.13.DELAY
CNTVALUEIN6	input	TCELL3:IMUX.IMUX.44.DELAY
CNTVALUEIN7	input	TCELL3:IMUX.IMUX.45.DELAY
CNTVALUEIN8	input	TCELL3:IMUX.IMUX.46.DELAY
CNTVALUEOUT0	output	TCELL3:OUT.4.TMIN
CNTVALUEOUT1	output	TCELL3:OUT.5.TMIN
CNTVALUEOUT2	output	TCELL3:OUT.6.TMIN
CNTVALUEOUT3	output	TCELL3:OUT.7.TMIN
CNTVALUEOUT4	output	TCELL3:OUT.8.TMIN
CNTVALUEOUT5	output	TCELL3:OUT.9.TMIN
CNTVALUEOUT6	output	TCELL3:OUT.10.TMIN
CNTVALUEOUT7	output	TCELL3:OUT.11.TMIN
CNTVALUEOUT8	output	TCELL3:OUT.12.TMIN
EN_VTC	input	TCELL0:IMUX.BYP.6
INC	input	TCELL3:IMUX.BYP.7
LD	input	TCELL3:IMUX.BYP.6

Bel BITSLICE_T1

ultrascale XIPHY bel BITSLICE_T1
Pin	Direction	Wires
CE_ODELAY	input	TCELL12:IMUX.BYP.6
CE_OFD	input	TCELL11:IMUX.BYP.13
CNTVALUEIN0	input	TCELL10:IMUX.IMUX.34.DELAY
CNTVALUEIN1	input	TCELL10:IMUX.IMUX.8.DELAY
CNTVALUEIN2	input	TCELL10:IMUX.IMUX.35.DELAY
CNTVALUEIN3	input	TCELL10:IMUX.IMUX.9.DELAY
CNTVALUEIN4	input	TCELL10:IMUX.IMUX.36.DELAY
CNTVALUEIN5	input	TCELL10:IMUX.IMUX.37.DELAY
CNTVALUEIN6	input	TCELL10:IMUX.IMUX.38.DELAY
CNTVALUEIN7	input	TCELL10:IMUX.IMUX.10.DELAY
CNTVALUEIN8	input	TCELL10:IMUX.IMUX.39.DELAY
CNTVALUEOUT0	output	TCELL11:OUT.18.TMIN
CNTVALUEOUT1	output	TCELL11:OUT.19.TMIN
CNTVALUEOUT2	output	TCELL11:OUT.20.TMIN
CNTVALUEOUT3	output	TCELL11:OUT.21.TMIN
CNTVALUEOUT4	output	TCELL11:OUT.22.TMIN
CNTVALUEOUT5	output	TCELL11:OUT.23.TMIN
CNTVALUEOUT6	output	TCELL11:OUT.24.TMIN
CNTVALUEOUT7	output	TCELL11:OUT.25.TMIN
CNTVALUEOUT8	output	TCELL11:OUT.26.TMIN
EN_VTC	input	TCELL1:IMUX.BYP.6
INC	input	TCELL11:IMUX.BYP.15
LD	input	TCELL11:IMUX.BYP.14

Bel BITSLICE_T2

ultrascale XIPHY bel BITSLICE_T2
Pin	Direction	Wires
CE_ODELAY	input	TCELL18:IMUX.BYP.8
CE_OFD	input	TCELL17:IMUX.BYP.15
CNTVALUEIN0	input	TCELL18:IMUX.IMUX.40.DELAY
CNTVALUEIN1	input	TCELL18:IMUX.IMUX.41.DELAY
CNTVALUEIN2	input	TCELL18:IMUX.IMUX.42.DELAY
CNTVALUEIN3	input	TCELL18:IMUX.IMUX.12.DELAY
CNTVALUEIN4	input	TCELL18:IMUX.IMUX.43.DELAY
CNTVALUEIN5	input	TCELL18:IMUX.IMUX.13.DELAY
CNTVALUEIN6	input	TCELL18:IMUX.IMUX.44.DELAY
CNTVALUEIN7	input	TCELL18:IMUX.IMUX.45.DELAY
CNTVALUEIN8	input	TCELL18:IMUX.IMUX.46.DELAY
CNTVALUEOUT0	output	TCELL18:OUT.4.TMIN
CNTVALUEOUT1	output	TCELL18:OUT.5.TMIN
CNTVALUEOUT2	output	TCELL18:OUT.6.TMIN
CNTVALUEOUT3	output	TCELL18:OUT.7.TMIN
CNTVALUEOUT4	output	TCELL18:OUT.8.TMIN
CNTVALUEOUT5	output	TCELL18:OUT.9.TMIN
CNTVALUEOUT6	output	TCELL18:OUT.10.TMIN
CNTVALUEOUT7	output	TCELL18:OUT.11.TMIN
CNTVALUEOUT8	output	TCELL18:OUT.12.TMIN
EN_VTC	input	TCELL15:IMUX.BYP.6
INC	input	TCELL18:IMUX.BYP.7
LD	input	TCELL18:IMUX.BYP.6

Bel BITSLICE_T3

ultrascale XIPHY bel BITSLICE_T3
Pin	Direction	Wires
CE_ODELAY	input	TCELL27:IMUX.BYP.6
CE_OFD	input	TCELL26:IMUX.BYP.13
CNTVALUEIN0	input	TCELL25:IMUX.IMUX.34.DELAY
CNTVALUEIN1	input	TCELL25:IMUX.IMUX.8.DELAY
CNTVALUEIN2	input	TCELL25:IMUX.IMUX.35.DELAY
CNTVALUEIN3	input	TCELL25:IMUX.IMUX.9.DELAY
CNTVALUEIN4	input	TCELL25:IMUX.IMUX.36.DELAY
CNTVALUEIN5	input	TCELL25:IMUX.IMUX.37.DELAY
CNTVALUEIN6	input	TCELL25:IMUX.IMUX.38.DELAY
CNTVALUEIN7	input	TCELL25:IMUX.IMUX.10.DELAY
CNTVALUEIN8	input	TCELL25:IMUX.IMUX.39.DELAY
CNTVALUEOUT0	output	TCELL26:OUT.18.TMIN
CNTVALUEOUT1	output	TCELL26:OUT.19.TMIN
CNTVALUEOUT2	output	TCELL26:OUT.20.TMIN
CNTVALUEOUT3	output	TCELL26:OUT.21.TMIN
CNTVALUEOUT4	output	TCELL26:OUT.22.TMIN
CNTVALUEOUT5	output	TCELL26:OUT.23.TMIN
CNTVALUEOUT6	output	TCELL26:OUT.24.TMIN
CNTVALUEOUT7	output	TCELL26:OUT.25.TMIN
CNTVALUEOUT8	output	TCELL26:OUT.26.TMIN
EN_VTC	input	TCELL16:IMUX.BYP.6
INC	input	TCELL26:IMUX.BYP.15
LD	input	TCELL26:IMUX.BYP.14

Bel BITSLICE_T4

ultrascale XIPHY bel BITSLICE_T4
Pin	Direction	Wires
CE_ODELAY	input	TCELL33:IMUX.BYP.8
CE_OFD	input	TCELL32:IMUX.BYP.15
CNTVALUEIN0	input	TCELL33:IMUX.IMUX.40.DELAY
CNTVALUEIN1	input	TCELL33:IMUX.IMUX.41.DELAY
CNTVALUEIN2	input	TCELL33:IMUX.IMUX.42.DELAY
CNTVALUEIN3	input	TCELL33:IMUX.IMUX.12.DELAY
CNTVALUEIN4	input	TCELL33:IMUX.IMUX.43.DELAY
CNTVALUEIN5	input	TCELL33:IMUX.IMUX.13.DELAY
CNTVALUEIN6	input	TCELL33:IMUX.IMUX.44.DELAY
CNTVALUEIN7	input	TCELL33:IMUX.IMUX.45.DELAY
CNTVALUEIN8	input	TCELL33:IMUX.IMUX.46.DELAY
CNTVALUEOUT0	output	TCELL33:OUT.4.TMIN
CNTVALUEOUT1	output	TCELL33:OUT.5.TMIN
CNTVALUEOUT2	output	TCELL33:OUT.6.TMIN
CNTVALUEOUT3	output	TCELL33:OUT.7.TMIN
CNTVALUEOUT4	output	TCELL33:OUT.8.TMIN
CNTVALUEOUT5	output	TCELL33:OUT.9.TMIN
CNTVALUEOUT6	output	TCELL33:OUT.10.TMIN
CNTVALUEOUT7	output	TCELL33:OUT.11.TMIN
CNTVALUEOUT8	output	TCELL33:OUT.12.TMIN
EN_VTC	input	TCELL30:IMUX.BYP.6
INC	input	TCELL33:IMUX.BYP.7
LD	input	TCELL33:IMUX.BYP.6

Bel BITSLICE_T5

ultrascale XIPHY bel BITSLICE_T5
Pin	Direction	Wires
CE_ODELAY	input	TCELL42:IMUX.BYP.6
CE_OFD	input	TCELL41:IMUX.BYP.13
CNTVALUEIN0	input	TCELL40:IMUX.IMUX.34.DELAY
CNTVALUEIN1	input	TCELL40:IMUX.IMUX.8.DELAY
CNTVALUEIN2	input	TCELL40:IMUX.IMUX.35.DELAY
CNTVALUEIN3	input	TCELL40:IMUX.IMUX.9.DELAY
CNTVALUEIN4	input	TCELL40:IMUX.IMUX.36.DELAY
CNTVALUEIN5	input	TCELL40:IMUX.IMUX.37.DELAY
CNTVALUEIN6	input	TCELL40:IMUX.IMUX.38.DELAY
CNTVALUEIN7	input	TCELL40:IMUX.IMUX.10.DELAY
CNTVALUEIN8	input	TCELL40:IMUX.IMUX.39.DELAY
CNTVALUEOUT0	output	TCELL41:OUT.18.TMIN
CNTVALUEOUT1	output	TCELL41:OUT.19.TMIN
CNTVALUEOUT2	output	TCELL41:OUT.20.TMIN
CNTVALUEOUT3	output	TCELL41:OUT.21.TMIN
CNTVALUEOUT4	output	TCELL41:OUT.22.TMIN
CNTVALUEOUT5	output	TCELL41:OUT.23.TMIN
CNTVALUEOUT6	output	TCELL41:OUT.24.TMIN
CNTVALUEOUT7	output	TCELL41:OUT.25.TMIN
CNTVALUEOUT8	output	TCELL41:OUT.26.TMIN
EN_VTC	input	TCELL31:IMUX.BYP.6
INC	input	TCELL41:IMUX.BYP.15
LD	input	TCELL41:IMUX.BYP.14

Bel BITSLICE_T6

ultrascale XIPHY bel BITSLICE_T6
Pin	Direction	Wires
CE_ODELAY	input	TCELL48:IMUX.BYP.8
CE_OFD	input	TCELL47:IMUX.BYP.15
CNTVALUEIN0	input	TCELL48:IMUX.IMUX.40.DELAY
CNTVALUEIN1	input	TCELL48:IMUX.IMUX.41.DELAY
CNTVALUEIN2	input	TCELL48:IMUX.IMUX.42.DELAY
CNTVALUEIN3	input	TCELL48:IMUX.IMUX.12.DELAY
CNTVALUEIN4	input	TCELL48:IMUX.IMUX.43.DELAY
CNTVALUEIN5	input	TCELL48:IMUX.IMUX.13.DELAY
CNTVALUEIN6	input	TCELL48:IMUX.IMUX.44.DELAY
CNTVALUEIN7	input	TCELL48:IMUX.IMUX.45.DELAY
CNTVALUEIN8	input	TCELL48:IMUX.IMUX.46.DELAY
CNTVALUEOUT0	output	TCELL48:OUT.4.TMIN
CNTVALUEOUT1	output	TCELL48:OUT.5.TMIN
CNTVALUEOUT2	output	TCELL48:OUT.6.TMIN
CNTVALUEOUT3	output	TCELL48:OUT.7.TMIN
CNTVALUEOUT4	output	TCELL48:OUT.8.TMIN
CNTVALUEOUT5	output	TCELL48:OUT.9.TMIN
CNTVALUEOUT6	output	TCELL48:OUT.10.TMIN
CNTVALUEOUT7	output	TCELL48:OUT.11.TMIN
CNTVALUEOUT8	output	TCELL48:OUT.12.TMIN
EN_VTC	input	TCELL45:IMUX.BYP.6
INC	input	TCELL48:IMUX.BYP.7
LD	input	TCELL48:IMUX.BYP.6

Bel BITSLICE_T7

ultrascale XIPHY bel BITSLICE_T7
Pin	Direction	Wires
CE_ODELAY	input	TCELL57:IMUX.BYP.6
CE_OFD	input	TCELL56:IMUX.BYP.13
CNTVALUEIN0	input	TCELL55:IMUX.IMUX.34.DELAY
CNTVALUEIN1	input	TCELL55:IMUX.IMUX.8.DELAY
CNTVALUEIN2	input	TCELL55:IMUX.IMUX.35.DELAY
CNTVALUEIN3	input	TCELL55:IMUX.IMUX.9.DELAY
CNTVALUEIN4	input	TCELL55:IMUX.IMUX.36.DELAY
CNTVALUEIN5	input	TCELL55:IMUX.IMUX.37.DELAY
CNTVALUEIN6	input	TCELL55:IMUX.IMUX.38.DELAY
CNTVALUEIN7	input	TCELL55:IMUX.IMUX.10.DELAY
CNTVALUEIN8	input	TCELL55:IMUX.IMUX.39.DELAY
CNTVALUEOUT0	output	TCELL56:OUT.18.TMIN
CNTVALUEOUT1	output	TCELL56:OUT.19.TMIN
CNTVALUEOUT2	output	TCELL56:OUT.20.TMIN
CNTVALUEOUT3	output	TCELL56:OUT.21.TMIN
CNTVALUEOUT4	output	TCELL56:OUT.22.TMIN
CNTVALUEOUT5	output	TCELL56:OUT.23.TMIN
CNTVALUEOUT6	output	TCELL56:OUT.24.TMIN
CNTVALUEOUT7	output	TCELL56:OUT.25.TMIN
CNTVALUEOUT8	output	TCELL56:OUT.26.TMIN
EN_VTC	input	TCELL46:IMUX.BYP.6
INC	input	TCELL56:IMUX.BYP.15
LD	input	TCELL56:IMUX.BYP.14

Bel BITSLICE_CONTROL0

ultrascale XIPHY bel BITSLICE_CONTROL0
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL4:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1	input	TCELL4:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2	input	TCELL4:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3	input	TCELL4:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0	input	TCELL4:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1	input	TCELL4:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2	input	TCELL4:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3	input	TCELL4:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0	input	TCELL4:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1	input	TCELL4:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2	input	TCELL4:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3	input	TCELL4:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0	input	TCELL4:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1	input	TCELL4:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2	input	TCELL4:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3	input	TCELL4:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0	input	TCELL4:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1	input	TCELL4:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2	input	TCELL4:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3	input	TCELL4:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0	input	TCELL3:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1	input	TCELL3:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2	input	TCELL4:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3	input	TCELL4:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0	input	TCELL7:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL7:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL7:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL7:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL7:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL7:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL3:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0	input	TCELL6:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL6:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL7:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL7:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL7:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL7:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL7:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL7:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL6:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL6:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL6:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL6:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL6:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL6:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL7:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL7:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL6:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL3:IMUX.BYP.10
CTRL_DLY_TEST_OUT	output	TCELL3:OUT.17.TMIN
EN_VTC	input	TCELL3:IMUX.BYP.9
MASTER_PD_OUT	output	TCELL3:OUT.15.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL3:OUT.16.TMIN
PHY2CLB_PHY_RDY	output	TCELL3:OUT.14.TMIN
REFCLK	input	TCELL3:IMUX.CTRL.5
RIU_CLK	input	TCELL3:IMUX.CTRL.7

Bel BITSLICE_CONTROL1

ultrascale XIPHY bel BITSLICE_CONTROL1
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL11:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1	input	TCELL11:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2	input	TCELL11:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3	input	TCELL11:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0	input	TCELL11:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1	input	TCELL11:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2	input	TCELL11:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3	input	TCELL11:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0	input	TCELL11:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1	input	TCELL11:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2	input	TCELL11:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3	input	TCELL11:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0	input	TCELL10:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1	input	TCELL10:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2	input	TCELL10:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3	input	TCELL10:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0	input	TCELL10:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1	input	TCELL10:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2	input	TCELL10:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3	input	TCELL10:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0	input	TCELL10:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1	input	TCELL10:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2	input	TCELL10:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3	input	TCELL10:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0	input	TCELL7:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL7:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL7:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL7:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL7:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL7:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL10:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0	input	TCELL6:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL6:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL7:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL7:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL7:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL7:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL7:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL7:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL6:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL6:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL6:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL6:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL6:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL6:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL7:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL7:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL6:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL12:IMUX.BYP.8
CTRL_DLY_TEST_OUT	output	TCELL11:OUT.30.TMIN
EN_VTC	input	TCELL12:IMUX.BYP.7
MASTER_PD_OUT	output	TCELL11:OUT.28.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL11:OUT.29.TMIN
PHY2CLB_PHY_RDY	output	TCELL11:OUT.27.TMIN
REFCLK	input	TCELL11:IMUX.CTRL.6
RIU_CLK	input	TCELL12:IMUX.CTRL.2

Bel BITSLICE_CONTROL2

ultrascale XIPHY bel BITSLICE_CONTROL2
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL19:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1	input	TCELL19:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2	input	TCELL19:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3	input	TCELL19:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0	input	TCELL19:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1	input	TCELL19:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2	input	TCELL19:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3	input	TCELL19:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0	input	TCELL19:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1	input	TCELL19:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2	input	TCELL19:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3	input	TCELL19:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0	input	TCELL19:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1	input	TCELL19:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2	input	TCELL19:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3	input	TCELL19:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0	input	TCELL19:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1	input	TCELL19:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2	input	TCELL19:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3	input	TCELL19:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0	input	TCELL18:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1	input	TCELL18:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2	input	TCELL19:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3	input	TCELL19:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0	input	TCELL22:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL22:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL22:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL22:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL22:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL22:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL18:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0	input	TCELL21:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL21:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL22:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL22:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL22:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL22:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL22:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL22:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL21:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL21:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL21:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL21:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL21:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL21:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL22:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL22:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL21:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL18:IMUX.BYP.10
CTRL_DLY_TEST_OUT	output	TCELL18:OUT.17.TMIN
EN_VTC	input	TCELL18:IMUX.BYP.9
MASTER_PD_OUT	output	TCELL18:OUT.15.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL18:OUT.16.TMIN
PHY2CLB_PHY_RDY	output	TCELL18:OUT.14.TMIN
REFCLK	input	TCELL18:IMUX.CTRL.5
RIU_CLK	input	TCELL18:IMUX.CTRL.7

Bel BITSLICE_CONTROL3

ultrascale XIPHY bel BITSLICE_CONTROL3
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL26:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1	input	TCELL26:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2	input	TCELL26:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3	input	TCELL26:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0	input	TCELL26:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1	input	TCELL26:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2	input	TCELL26:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3	input	TCELL26:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0	input	TCELL26:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1	input	TCELL26:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2	input	TCELL26:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3	input	TCELL26:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0	input	TCELL25:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1	input	TCELL25:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2	input	TCELL25:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3	input	TCELL25:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0	input	TCELL25:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1	input	TCELL25:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2	input	TCELL25:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3	input	TCELL25:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0	input	TCELL25:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1	input	TCELL25:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2	input	TCELL25:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3	input	TCELL25:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0	input	TCELL22:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL22:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL22:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL22:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL22:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL22:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL25:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0	input	TCELL21:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL21:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL22:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL22:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL22:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL22:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL22:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL22:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL21:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL21:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL21:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL21:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL21:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL21:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL22:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL22:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL21:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL27:IMUX.BYP.8
CTRL_DLY_TEST_OUT	output	TCELL26:OUT.30.TMIN
EN_VTC	input	TCELL27:IMUX.BYP.7
MASTER_PD_OUT	output	TCELL26:OUT.28.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL26:OUT.29.TMIN
PHY2CLB_PHY_RDY	output	TCELL26:OUT.27.TMIN
REFCLK	input	TCELL26:IMUX.CTRL.6
RIU_CLK	input	TCELL27:IMUX.CTRL.2

Bel BITSLICE_CONTROL4

ultrascale XIPHY bel BITSLICE_CONTROL4
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL34:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1	input	TCELL34:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2	input	TCELL34:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3	input	TCELL34:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0	input	TCELL34:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1	input	TCELL34:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2	input	TCELL34:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3	input	TCELL34:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0	input	TCELL34:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1	input	TCELL34:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2	input	TCELL34:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3	input	TCELL34:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0	input	TCELL34:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1	input	TCELL34:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2	input	TCELL34:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3	input	TCELL34:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0	input	TCELL34:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1	input	TCELL34:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2	input	TCELL34:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3	input	TCELL34:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0	input	TCELL33:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1	input	TCELL33:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2	input	TCELL34:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3	input	TCELL34:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0	input	TCELL37:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL37:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL37:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL37:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL37:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL37:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL33:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0	input	TCELL36:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL36:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL37:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL37:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL37:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL37:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL37:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL37:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL36:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL36:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL36:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL36:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL36:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL36:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL37:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL37:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL36:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL33:IMUX.BYP.10
CTRL_DLY_TEST_OUT	output	TCELL33:OUT.17.TMIN
EN_VTC	input	TCELL33:IMUX.BYP.9
MASTER_PD_OUT	output	TCELL33:OUT.15.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL33:OUT.16.TMIN
PHY2CLB_PHY_RDY	output	TCELL33:OUT.14.TMIN
REFCLK	input	TCELL33:IMUX.CTRL.5
RIU_CLK	input	TCELL33:IMUX.CTRL.7

Bel BITSLICE_CONTROL5

ultrascale XIPHY bel BITSLICE_CONTROL5
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL41:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1	input	TCELL41:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2	input	TCELL41:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3	input	TCELL41:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0	input	TCELL41:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1	input	TCELL41:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2	input	TCELL41:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3	input	TCELL41:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0	input	TCELL41:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1	input	TCELL41:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2	input	TCELL41:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3	input	TCELL41:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0	input	TCELL40:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1	input	TCELL40:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2	input	TCELL40:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3	input	TCELL40:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0	input	TCELL40:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1	input	TCELL40:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2	input	TCELL40:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3	input	TCELL40:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0	input	TCELL40:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1	input	TCELL40:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2	input	TCELL40:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3	input	TCELL40:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0	input	TCELL37:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL37:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL37:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL37:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL37:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL37:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL40:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0	input	TCELL36:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL36:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL37:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL37:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL37:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL37:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL37:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL37:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL36:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL36:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL36:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL36:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL36:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL36:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL37:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL37:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL36:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL42:IMUX.BYP.8
CTRL_DLY_TEST_OUT	output	TCELL41:OUT.30.TMIN
EN_VTC	input	TCELL42:IMUX.BYP.7
MASTER_PD_OUT	output	TCELL41:OUT.28.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL41:OUT.29.TMIN
PHY2CLB_PHY_RDY	output	TCELL41:OUT.27.TMIN
REFCLK	input	TCELL41:IMUX.CTRL.6
RIU_CLK	input	TCELL42:IMUX.CTRL.2

Bel BITSLICE_CONTROL6

ultrascale XIPHY bel BITSLICE_CONTROL6
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL49:IMUX.IMUX.32.DELAY
CLB2PHY_RDCS0_1	input	TCELL49:IMUX.IMUX.33.DELAY
CLB2PHY_RDCS0_2	input	TCELL49:IMUX.IMUX.34.DELAY
CLB2PHY_RDCS0_3	input	TCELL49:IMUX.IMUX.8.DELAY
CLB2PHY_RDCS1_0	input	TCELL49:IMUX.IMUX.30.DELAY
CLB2PHY_RDCS1_1	input	TCELL49:IMUX.IMUX.6.DELAY
CLB2PHY_RDCS1_2	input	TCELL49:IMUX.IMUX.31.DELAY
CLB2PHY_RDCS1_3	input	TCELL49:IMUX.IMUX.7.DELAY
CLB2PHY_RDEN0	input	TCELL49:IMUX.IMUX.26.DELAY
CLB2PHY_RDEN1	input	TCELL49:IMUX.IMUX.27.DELAY
CLB2PHY_RDEN2	input	TCELL49:IMUX.IMUX.28.DELAY
CLB2PHY_RDEN3	input	TCELL49:IMUX.IMUX.29.DELAY
CLB2PHY_T_B0	input	TCELL49:IMUX.IMUX.22.DELAY
CLB2PHY_T_B1	input	TCELL49:IMUX.IMUX.23.DELAY
CLB2PHY_T_B2	input	TCELL49:IMUX.IMUX.24.DELAY
CLB2PHY_T_B3	input	TCELL49:IMUX.IMUX.25.DELAY
CLB2PHY_WRCS0_0	input	TCELL49:IMUX.IMUX.18.DELAY
CLB2PHY_WRCS0_1	input	TCELL49:IMUX.IMUX.19.DELAY
CLB2PHY_WRCS0_2	input	TCELL49:IMUX.IMUX.20.DELAY
CLB2PHY_WRCS0_3	input	TCELL49:IMUX.IMUX.21.DELAY
CLB2PHY_WRCS1_0	input	TCELL48:IMUX.IMUX.47.DELAY
CLB2PHY_WRCS1_1	input	TCELL48:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS1_2	input	TCELL49:IMUX.IMUX.16.DELAY
CLB2PHY_WRCS1_3	input	TCELL49:IMUX.IMUX.17.DELAY
CLB2RIU_ADDR0	input	TCELL52:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL52:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL52:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL52:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL52:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL52:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL48:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA0	input	TCELL51:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL51:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL52:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL52:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL52:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL52:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL52:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL52:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL51:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL51:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL51:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL51:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL51:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL51:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL52:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL52:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL51:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL48:IMUX.BYP.10
CTRL_DLY_TEST_OUT	output	TCELL48:OUT.17.TMIN
EN_VTC	input	TCELL48:IMUX.BYP.9
MASTER_PD_OUT	output	TCELL48:OUT.15.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL48:OUT.16.TMIN
PHY2CLB_PHY_RDY	output	TCELL48:OUT.14.TMIN
REFCLK	input	TCELL48:IMUX.CTRL.5
RIU_CLK	input	TCELL48:IMUX.CTRL.7

Bel BITSLICE_CONTROL7

ultrascale XIPHY bel BITSLICE_CONTROL7
Pin	Direction	Wires
CLB2PHY_RDCS0_0	input	TCELL56:IMUX.IMUX.24.DELAY
CLB2PHY_RDCS0_1	input	TCELL56:IMUX.IMUX.25.DELAY
CLB2PHY_RDCS0_2	input	TCELL56:IMUX.IMUX.26.DELAY
CLB2PHY_RDCS0_3	input	TCELL56:IMUX.IMUX.27.DELAY
CLB2PHY_RDCS1_0	input	TCELL56:IMUX.IMUX.20.DELAY
CLB2PHY_RDCS1_1	input	TCELL56:IMUX.IMUX.21.DELAY
CLB2PHY_RDCS1_2	input	TCELL56:IMUX.IMUX.22.DELAY
CLB2PHY_RDCS1_3	input	TCELL56:IMUX.IMUX.23.DELAY
CLB2PHY_RDEN0	input	TCELL56:IMUX.IMUX.16.DELAY
CLB2PHY_RDEN1	input	TCELL56:IMUX.IMUX.17.DELAY
CLB2PHY_RDEN2	input	TCELL56:IMUX.IMUX.18.DELAY
CLB2PHY_RDEN3	input	TCELL56:IMUX.IMUX.19.DELAY
CLB2PHY_T_B0	input	TCELL55:IMUX.IMUX.46.DELAY
CLB2PHY_T_B1	input	TCELL55:IMUX.IMUX.14.DELAY
CLB2PHY_T_B2	input	TCELL55:IMUX.IMUX.47.DELAY
CLB2PHY_T_B3	input	TCELL55:IMUX.IMUX.15.DELAY
CLB2PHY_WRCS0_0	input	TCELL55:IMUX.IMUX.43.DELAY
CLB2PHY_WRCS0_1	input	TCELL55:IMUX.IMUX.13.DELAY
CLB2PHY_WRCS0_2	input	TCELL55:IMUX.IMUX.44.DELAY
CLB2PHY_WRCS0_3	input	TCELL55:IMUX.IMUX.45.DELAY
CLB2PHY_WRCS1_0	input	TCELL55:IMUX.IMUX.40.DELAY
CLB2PHY_WRCS1_1	input	TCELL55:IMUX.IMUX.41.DELAY
CLB2PHY_WRCS1_2	input	TCELL55:IMUX.IMUX.42.DELAY
CLB2PHY_WRCS1_3	input	TCELL55:IMUX.IMUX.12.DELAY
CLB2RIU_ADDR0	input	TCELL52:IMUX.IMUX.24.DELAY
CLB2RIU_ADDR1	input	TCELL52:IMUX.IMUX.25.DELAY
CLB2RIU_ADDR2	input	TCELL52:IMUX.IMUX.26.DELAY
CLB2RIU_ADDR3	input	TCELL52:IMUX.IMUX.27.DELAY
CLB2RIU_ADDR4	input	TCELL52:IMUX.IMUX.28.DELAY
CLB2RIU_ADDR5	input	TCELL52:IMUX.IMUX.29.DELAY
CLB2RIU_NIBBLE_SEL	input	TCELL55:IMUX.IMUX.11.DELAY
CLB2RIU_WR_DATA0	input	TCELL51:IMUX.IMUX.43.DELAY
CLB2RIU_WR_DATA1	input	TCELL51:IMUX.IMUX.13.DELAY
CLB2RIU_WR_DATA10	input	TCELL52:IMUX.IMUX.18.DELAY
CLB2RIU_WR_DATA11	input	TCELL52:IMUX.IMUX.19.DELAY
CLB2RIU_WR_DATA12	input	TCELL52:IMUX.IMUX.20.DELAY
CLB2RIU_WR_DATA13	input	TCELL52:IMUX.IMUX.21.DELAY
CLB2RIU_WR_DATA14	input	TCELL52:IMUX.IMUX.22.DELAY
CLB2RIU_WR_DATA15	input	TCELL52:IMUX.IMUX.23.DELAY
CLB2RIU_WR_DATA2	input	TCELL51:IMUX.IMUX.44.DELAY
CLB2RIU_WR_DATA3	input	TCELL51:IMUX.IMUX.45.DELAY
CLB2RIU_WR_DATA4	input	TCELL51:IMUX.IMUX.46.DELAY
CLB2RIU_WR_DATA5	input	TCELL51:IMUX.IMUX.14.DELAY
CLB2RIU_WR_DATA6	input	TCELL51:IMUX.IMUX.47.DELAY
CLB2RIU_WR_DATA7	input	TCELL51:IMUX.IMUX.15.DELAY
CLB2RIU_WR_DATA8	input	TCELL52:IMUX.IMUX.16.DELAY
CLB2RIU_WR_DATA9	input	TCELL52:IMUX.IMUX.17.DELAY
CLB2RIU_WR_EN	input	TCELL51:IMUX.IMUX.12.DELAY
CTRL_DLY_TEST_IN	input	TCELL57:IMUX.BYP.8
CTRL_DLY_TEST_OUT	output	TCELL56:OUT.30.TMIN
EN_VTC	input	TCELL57:IMUX.BYP.7
MASTER_PD_OUT	output	TCELL56:OUT.28.TMIN
PHY2CLB_FIXDLY_RDY	output	TCELL56:OUT.29.TMIN
PHY2CLB_PHY_RDY	output	TCELL56:OUT.27.TMIN
REFCLK	input	TCELL56:IMUX.CTRL.6
RIU_CLK	input	TCELL57:IMUX.CTRL.2

Bel PLL_SELECT0

ultrascale XIPHY bel PLL_SELECT0
Pin	Direction	Wires

Bel PLL_SELECT1

ultrascale XIPHY bel PLL_SELECT1
Pin	Direction	Wires

Bel PLL_SELECT2

ultrascale XIPHY bel PLL_SELECT2
Pin	Direction	Wires

Bel PLL_SELECT3

ultrascale XIPHY bel PLL_SELECT3
Pin	Direction	Wires

Bel PLL_SELECT4

ultrascale XIPHY bel PLL_SELECT4
Pin	Direction	Wires

Bel PLL_SELECT5

ultrascale XIPHY bel PLL_SELECT5
Pin	Direction	Wires

Bel PLL_SELECT6

ultrascale XIPHY bel PLL_SELECT6
Pin	Direction	Wires

Bel PLL_SELECT7

ultrascale XIPHY bel PLL_SELECT7
Pin	Direction	Wires

Bel RIU_OR0

ultrascale XIPHY bel RIU_OR0
Pin	Direction	Wires
RIU_RD_DATA0	output	TCELL6:OUT.19.TMIN
RIU_RD_DATA1	output	TCELL6:OUT.20.TMIN
RIU_RD_DATA10	output	TCELL6:OUT.29.TMIN
RIU_RD_DATA11	output	TCELL6:OUT.30.TMIN
RIU_RD_DATA12	output	TCELL6:OUT.31.TMIN
RIU_RD_DATA13	output	TCELL7:OUT.4.TMIN
RIU_RD_DATA14	output	TCELL7:OUT.5.TMIN
RIU_RD_DATA15	output	TCELL7:OUT.6.TMIN
RIU_RD_DATA2	output	TCELL6:OUT.21.TMIN
RIU_RD_DATA3	output	TCELL6:OUT.22.TMIN
RIU_RD_DATA4	output	TCELL6:OUT.23.TMIN
RIU_RD_DATA5	output	TCELL6:OUT.24.TMIN
RIU_RD_DATA6	output	TCELL6:OUT.25.TMIN
RIU_RD_DATA7	output	TCELL6:OUT.26.TMIN
RIU_RD_DATA8	output	TCELL6:OUT.27.TMIN
RIU_RD_DATA9	output	TCELL6:OUT.28.TMIN
RIU_RD_VALID	output	TCELL6:OUT.18.TMIN

Bel RIU_OR1

ultrascale XIPHY bel RIU_OR1
Pin	Direction	Wires
RIU_RD_DATA0	output	TCELL21:OUT.19.TMIN
RIU_RD_DATA1	output	TCELL21:OUT.20.TMIN
RIU_RD_DATA10	output	TCELL21:OUT.29.TMIN
RIU_RD_DATA11	output	TCELL21:OUT.30.TMIN
RIU_RD_DATA12	output	TCELL21:OUT.31.TMIN
RIU_RD_DATA13	output	TCELL22:OUT.4.TMIN
RIU_RD_DATA14	output	TCELL22:OUT.5.TMIN
RIU_RD_DATA15	output	TCELL22:OUT.6.TMIN
RIU_RD_DATA2	output	TCELL21:OUT.21.TMIN
RIU_RD_DATA3	output	TCELL21:OUT.22.TMIN
RIU_RD_DATA4	output	TCELL21:OUT.23.TMIN
RIU_RD_DATA5	output	TCELL21:OUT.24.TMIN
RIU_RD_DATA6	output	TCELL21:OUT.25.TMIN
RIU_RD_DATA7	output	TCELL21:OUT.26.TMIN
RIU_RD_DATA8	output	TCELL21:OUT.27.TMIN
RIU_RD_DATA9	output	TCELL21:OUT.28.TMIN
RIU_RD_VALID	output	TCELL21:OUT.18.TMIN

Bel RIU_OR2

ultrascale XIPHY bel RIU_OR2
Pin	Direction	Wires
RIU_RD_DATA0	output	TCELL36:OUT.19.TMIN
RIU_RD_DATA1	output	TCELL36:OUT.20.TMIN
RIU_RD_DATA10	output	TCELL36:OUT.29.TMIN
RIU_RD_DATA11	output	TCELL36:OUT.30.TMIN
RIU_RD_DATA12	output	TCELL36:OUT.31.TMIN
RIU_RD_DATA13	output	TCELL37:OUT.4.TMIN
RIU_RD_DATA14	output	TCELL37:OUT.5.TMIN
RIU_RD_DATA15	output	TCELL37:OUT.6.TMIN
RIU_RD_DATA2	output	TCELL36:OUT.21.TMIN
RIU_RD_DATA3	output	TCELL36:OUT.22.TMIN
RIU_RD_DATA4	output	TCELL36:OUT.23.TMIN
RIU_RD_DATA5	output	TCELL36:OUT.24.TMIN
RIU_RD_DATA6	output	TCELL36:OUT.25.TMIN
RIU_RD_DATA7	output	TCELL36:OUT.26.TMIN
RIU_RD_DATA8	output	TCELL36:OUT.27.TMIN
RIU_RD_DATA9	output	TCELL36:OUT.28.TMIN
RIU_RD_VALID	output	TCELL36:OUT.18.TMIN

Bel RIU_OR3

ultrascale XIPHY bel RIU_OR3
Pin	Direction	Wires
RIU_RD_DATA0	output	TCELL51:OUT.19.TMIN
RIU_RD_DATA1	output	TCELL51:OUT.20.TMIN
RIU_RD_DATA10	output	TCELL51:OUT.29.TMIN
RIU_RD_DATA11	output	TCELL51:OUT.30.TMIN
RIU_RD_DATA12	output	TCELL51:OUT.31.TMIN
RIU_RD_DATA13	output	TCELL52:OUT.4.TMIN
RIU_RD_DATA14	output	TCELL52:OUT.5.TMIN
RIU_RD_DATA15	output	TCELL52:OUT.6.TMIN
RIU_RD_DATA2	output	TCELL51:OUT.21.TMIN
RIU_RD_DATA3	output	TCELL51:OUT.22.TMIN
RIU_RD_DATA4	output	TCELL51:OUT.23.TMIN
RIU_RD_DATA5	output	TCELL51:OUT.24.TMIN
RIU_RD_DATA6	output	TCELL51:OUT.25.TMIN
RIU_RD_DATA7	output	TCELL51:OUT.26.TMIN
RIU_RD_DATA8	output	TCELL51:OUT.27.TMIN
RIU_RD_DATA9	output	TCELL51:OUT.28.TMIN
RIU_RD_VALID	output	TCELL51:OUT.18.TMIN

Bel XIPHY_FEEDTHROUGH0

ultrascale XIPHY bel XIPHY_FEEDTHROUGH0
Pin	Direction	Wires
CLB2PHY_CTRL_CLK_LOW	input	TCELL3:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPP	input	TCELL12:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT	input	TCELL7:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUT	input	TCELL7:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_EN	input	TCELL7:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0	input	TCELL1:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1	input	TCELL2:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10	input	TCELL14:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11	input	TCELL14:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12	input	TCELL8:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2	input	TCELL3:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3	input	TCELL4:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4	input	TCELL5:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5	input	TCELL6:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6	input	TCELL9:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7	input	TCELL10:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8	input	TCELL11:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9	input	TCELL13:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2	input	TCELL7:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4	input	TCELL7:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDR	input	TCELL7:IMUX.CTRL.2
CLB2PHY_SCAN_EN_B	input	TCELL7:IMUX.BYP.14
CLB2PHY_SCAN_IN0	input	TCELL6:IMUX.BYP.15
CLB2PHY_SCAN_IN1	input	TCELL7:IMUX.BYP.6
CLB2PHY_SCAN_IN2	input	TCELL7:IMUX.BYP.7
CLB2PHY_SCAN_IN3	input	TCELL7:IMUX.BYP.8
CLB2PHY_SCAN_IN4	input	TCELL7:IMUX.BYP.10
CLB2PHY_SCAN_IN5	input	TCELL7:IMUX.BYP.11
CLB2PHY_SCAN_IN6	input	TCELL7:IMUX.BYP.12
CLB2PHY_SCAN_IN7	input	TCELL7:IMUX.BYP.13
CLB2PHY_SCAN_MODE_B	input	TCELL6:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_B	input	TCELL6:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_B	input	TCELL7:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_B	input	TCELL7:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_B	input	TCELL7:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0	input	TCELL6:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1	input	TCELL6:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2	input	TCELL6:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3	input	TCELL6:IMUX.BYP.12
CTRL_RST_B_LOW	input	TCELL3:IMUX.CTRL.6
CTRL_RST_B_UPP	input	TCELL11:IMUX.CTRL.7
IDELAY_RST_B0	input	TCELL0:IMUX.CTRL.6
IDELAY_RST_B1	input	TCELL1:IMUX.CTRL.7
IDELAY_RST_B10	input	TCELL13:IMUX.CTRL.7
IDELAY_RST_B11	input	TCELL14:IMUX.CTRL.6
IDELAY_RST_B12	input	TCELL8:IMUX.CTRL.3
IDELAY_RST_B2	input	TCELL2:IMUX.CTRL.7
IDELAY_RST_B3	input	TCELL4:IMUX.CTRL.6
IDELAY_RST_B4	input	TCELL5:IMUX.CTRL.6
IDELAY_RST_B5	input	TCELL6:IMUX.CTRL.5
IDELAY_RST_B6	input	TCELL9:IMUX.CTRL.3
IDELAY_RST_B7	input	TCELL10:IMUX.CTRL.2
IDELAY_RST_B8	input	TCELL11:IMUX.CTRL.2
IDELAY_RST_B9	input	TCELL12:IMUX.CTRL.7
ODELAY_RST_B0	input	TCELL0:IMUX.CTRL.5
ODELAY_RST_B1	input	TCELL1:IMUX.CTRL.6
ODELAY_RST_B10	input	TCELL13:IMUX.CTRL.5
ODELAY_RST_B11	input	TCELL14:IMUX.CTRL.5
ODELAY_RST_B12	input	TCELL8:IMUX.CTRL.2
ODELAY_RST_B2	input	TCELL2:IMUX.CTRL.6
ODELAY_RST_B3	input	TCELL4:IMUX.CTRL.5
ODELAY_RST_B4	input	TCELL5:IMUX.CTRL.4
ODELAY_RST_B5	input	TCELL6:IMUX.CTRL.4
ODELAY_RST_B6	input	TCELL8:IMUX.CTRL.7
ODELAY_RST_B7	input	TCELL9:IMUX.CTRL.7
ODELAY_RST_B8	input	TCELL10:IMUX.CTRL.7
ODELAY_RST_B9	input	TCELL12:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT	output	TCELL7:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUT	output	TCELL7:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUT	output	TCELL7:OUT.15.TMIN
PHY2CLB_SCAN_OUT0	output	TCELL7:OUT.7.TMIN
PHY2CLB_SCAN_OUT1	output	TCELL7:OUT.8.TMIN
PHY2CLB_SCAN_OUT2	output	TCELL7:OUT.9.TMIN
PHY2CLB_SCAN_OUT3	output	TCELL7:OUT.10.TMIN
PHY2CLB_SCAN_OUT4	output	TCELL7:OUT.11.TMIN
PHY2CLB_SCAN_OUT5	output	TCELL7:OUT.12.TMIN
PHY2CLB_SCAN_OUT6	output	TCELL7:OUT.13.TMIN
PHY2CLB_SCAN_OUT7	output	TCELL7:OUT.14.TMIN
RXBIT_RST_B0	input	TCELL0:IMUX.CTRL.4
RXBIT_RST_B1	input	TCELL1:IMUX.CTRL.5
RXBIT_RST_B10	input	TCELL13:IMUX.CTRL.4
RXBIT_RST_B11	input	TCELL14:IMUX.CTRL.4
RXBIT_RST_B12	input	TCELL7:IMUX.CTRL.6
RXBIT_RST_B2	input	TCELL2:IMUX.CTRL.5
RXBIT_RST_B3	input	TCELL4:IMUX.CTRL.3
RXBIT_RST_B4	input	TCELL5:IMUX.CTRL.3
RXBIT_RST_B5	input	TCELL6:IMUX.CTRL.3
RXBIT_RST_B6	input	TCELL8:IMUX.CTRL.6
RXBIT_RST_B7	input	TCELL9:IMUX.CTRL.6
RXBIT_RST_B8	input	TCELL10:IMUX.CTRL.6
RXBIT_RST_B9	input	TCELL12:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0	input	TCELL3:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1	input	TCELL11:IMUX.CTRL.5
TXBIT_RST_B0	input	TCELL0:IMUX.CTRL.3
TXBIT_RST_B1	input	TCELL1:IMUX.CTRL.4
TXBIT_RST_B10	input	TCELL13:IMUX.CTRL.3
TXBIT_RST_B11	input	TCELL14:IMUX.CTRL.3
TXBIT_RST_B12	input	TCELL7:IMUX.CTRL.5
TXBIT_RST_B2	input	TCELL2:IMUX.CTRL.4
TXBIT_RST_B3	input	TCELL4:IMUX.CTRL.2
TXBIT_RST_B4	input	TCELL5:IMUX.CTRL.2
TXBIT_RST_B5	input	TCELL6:IMUX.CTRL.2
TXBIT_RST_B6	input	TCELL8:IMUX.CTRL.5
TXBIT_RST_B7	input	TCELL9:IMUX.CTRL.5
TXBIT_RST_B8	input	TCELL10:IMUX.CTRL.5
TXBIT_RST_B9	input	TCELL12:IMUX.CTRL.3
TXBIT_TRI_RST_B0	input	TCELL0:IMUX.CTRL.2
TXBIT_TRI_RST_B1	input	TCELL1:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH1

ultrascale XIPHY bel XIPHY_FEEDTHROUGH1
Pin	Direction	Wires
CLB2PHY_CTRL_CLK_LOW	input	TCELL18:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPP	input	TCELL27:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT	input	TCELL22:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUT	input	TCELL22:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_EN	input	TCELL22:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0	input	TCELL16:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1	input	TCELL17:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10	input	TCELL29:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11	input	TCELL29:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12	input	TCELL23:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2	input	TCELL18:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3	input	TCELL19:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4	input	TCELL20:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5	input	TCELL21:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6	input	TCELL24:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7	input	TCELL25:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8	input	TCELL26:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9	input	TCELL28:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2	input	TCELL22:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4	input	TCELL22:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDR	input	TCELL22:IMUX.CTRL.2
CLB2PHY_SCAN_EN_B	input	TCELL22:IMUX.BYP.14
CLB2PHY_SCAN_IN0	input	TCELL21:IMUX.BYP.15
CLB2PHY_SCAN_IN1	input	TCELL22:IMUX.BYP.6
CLB2PHY_SCAN_IN2	input	TCELL22:IMUX.BYP.7
CLB2PHY_SCAN_IN3	input	TCELL22:IMUX.BYP.8
CLB2PHY_SCAN_IN4	input	TCELL22:IMUX.BYP.10
CLB2PHY_SCAN_IN5	input	TCELL22:IMUX.BYP.11
CLB2PHY_SCAN_IN6	input	TCELL22:IMUX.BYP.12
CLB2PHY_SCAN_IN7	input	TCELL22:IMUX.BYP.13
CLB2PHY_SCAN_MODE_B	input	TCELL21:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_B	input	TCELL21:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_B	input	TCELL22:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_B	input	TCELL22:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_B	input	TCELL22:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0	input	TCELL21:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1	input	TCELL21:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2	input	TCELL21:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3	input	TCELL21:IMUX.BYP.12
CTRL_RST_B_LOW	input	TCELL18:IMUX.CTRL.6
CTRL_RST_B_UPP	input	TCELL26:IMUX.CTRL.7
IDELAY_RST_B0	input	TCELL15:IMUX.CTRL.6
IDELAY_RST_B1	input	TCELL16:IMUX.CTRL.7
IDELAY_RST_B10	input	TCELL28:IMUX.CTRL.7
IDELAY_RST_B11	input	TCELL29:IMUX.CTRL.6
IDELAY_RST_B12	input	TCELL23:IMUX.CTRL.3
IDELAY_RST_B2	input	TCELL17:IMUX.CTRL.7
IDELAY_RST_B3	input	TCELL19:IMUX.CTRL.6
IDELAY_RST_B4	input	TCELL20:IMUX.CTRL.6
IDELAY_RST_B5	input	TCELL21:IMUX.CTRL.5
IDELAY_RST_B6	input	TCELL24:IMUX.CTRL.3
IDELAY_RST_B7	input	TCELL25:IMUX.CTRL.2
IDELAY_RST_B8	input	TCELL26:IMUX.CTRL.2
IDELAY_RST_B9	input	TCELL27:IMUX.CTRL.7
ODELAY_RST_B0	input	TCELL15:IMUX.CTRL.5
ODELAY_RST_B1	input	TCELL16:IMUX.CTRL.6
ODELAY_RST_B10	input	TCELL28:IMUX.CTRL.5
ODELAY_RST_B11	input	TCELL29:IMUX.CTRL.5
ODELAY_RST_B12	input	TCELL23:IMUX.CTRL.2
ODELAY_RST_B2	input	TCELL17:IMUX.CTRL.6
ODELAY_RST_B3	input	TCELL19:IMUX.CTRL.5
ODELAY_RST_B4	input	TCELL20:IMUX.CTRL.4
ODELAY_RST_B5	input	TCELL21:IMUX.CTRL.4
ODELAY_RST_B6	input	TCELL23:IMUX.CTRL.7
ODELAY_RST_B7	input	TCELL24:IMUX.CTRL.7
ODELAY_RST_B8	input	TCELL25:IMUX.CTRL.7
ODELAY_RST_B9	input	TCELL27:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT	output	TCELL22:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUT	output	TCELL22:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUT	output	TCELL22:OUT.15.TMIN
PHY2CLB_SCAN_OUT0	output	TCELL22:OUT.7.TMIN
PHY2CLB_SCAN_OUT1	output	TCELL22:OUT.8.TMIN
PHY2CLB_SCAN_OUT2	output	TCELL22:OUT.9.TMIN
PHY2CLB_SCAN_OUT3	output	TCELL22:OUT.10.TMIN
PHY2CLB_SCAN_OUT4	output	TCELL22:OUT.11.TMIN
PHY2CLB_SCAN_OUT5	output	TCELL22:OUT.12.TMIN
PHY2CLB_SCAN_OUT6	output	TCELL22:OUT.13.TMIN
PHY2CLB_SCAN_OUT7	output	TCELL22:OUT.14.TMIN
RXBIT_RST_B0	input	TCELL15:IMUX.CTRL.4
RXBIT_RST_B1	input	TCELL16:IMUX.CTRL.5
RXBIT_RST_B10	input	TCELL28:IMUX.CTRL.4
RXBIT_RST_B11	input	TCELL29:IMUX.CTRL.4
RXBIT_RST_B12	input	TCELL22:IMUX.CTRL.6
RXBIT_RST_B2	input	TCELL17:IMUX.CTRL.5
RXBIT_RST_B3	input	TCELL19:IMUX.CTRL.3
RXBIT_RST_B4	input	TCELL20:IMUX.CTRL.3
RXBIT_RST_B5	input	TCELL21:IMUX.CTRL.3
RXBIT_RST_B6	input	TCELL23:IMUX.CTRL.6
RXBIT_RST_B7	input	TCELL24:IMUX.CTRL.6
RXBIT_RST_B8	input	TCELL25:IMUX.CTRL.6
RXBIT_RST_B9	input	TCELL27:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0	input	TCELL18:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1	input	TCELL26:IMUX.CTRL.5
TXBIT_RST_B0	input	TCELL15:IMUX.CTRL.3
TXBIT_RST_B1	input	TCELL16:IMUX.CTRL.4
TXBIT_RST_B10	input	TCELL28:IMUX.CTRL.3
TXBIT_RST_B11	input	TCELL29:IMUX.CTRL.3
TXBIT_RST_B12	input	TCELL22:IMUX.CTRL.5
TXBIT_RST_B2	input	TCELL17:IMUX.CTRL.4
TXBIT_RST_B3	input	TCELL19:IMUX.CTRL.2
TXBIT_RST_B4	input	TCELL20:IMUX.CTRL.2
TXBIT_RST_B5	input	TCELL21:IMUX.CTRL.2
TXBIT_RST_B6	input	TCELL23:IMUX.CTRL.5
TXBIT_RST_B7	input	TCELL24:IMUX.CTRL.5
TXBIT_RST_B8	input	TCELL25:IMUX.CTRL.5
TXBIT_RST_B9	input	TCELL27:IMUX.CTRL.3
TXBIT_TRI_RST_B0	input	TCELL15:IMUX.CTRL.2
TXBIT_TRI_RST_B1	input	TCELL16:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH2

ultrascale XIPHY bel XIPHY_FEEDTHROUGH2
Pin	Direction	Wires
CLB2PHY_CTRL_CLK_LOW	input	TCELL33:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPP	input	TCELL42:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT	input	TCELL37:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUT	input	TCELL37:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_EN	input	TCELL37:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0	input	TCELL31:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1	input	TCELL32:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10	input	TCELL44:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11	input	TCELL44:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12	input	TCELL38:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2	input	TCELL33:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3	input	TCELL34:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4	input	TCELL35:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5	input	TCELL36:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6	input	TCELL39:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7	input	TCELL40:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8	input	TCELL41:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9	input	TCELL43:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2	input	TCELL37:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4	input	TCELL37:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDR	input	TCELL37:IMUX.CTRL.2
CLB2PHY_SCAN_EN_B	input	TCELL37:IMUX.BYP.14
CLB2PHY_SCAN_IN0	input	TCELL36:IMUX.BYP.15
CLB2PHY_SCAN_IN1	input	TCELL37:IMUX.BYP.6
CLB2PHY_SCAN_IN2	input	TCELL37:IMUX.BYP.7
CLB2PHY_SCAN_IN3	input	TCELL37:IMUX.BYP.8
CLB2PHY_SCAN_IN4	input	TCELL37:IMUX.BYP.10
CLB2PHY_SCAN_IN5	input	TCELL37:IMUX.BYP.11
CLB2PHY_SCAN_IN6	input	TCELL37:IMUX.BYP.12
CLB2PHY_SCAN_IN7	input	TCELL37:IMUX.BYP.13
CLB2PHY_SCAN_MODE_B	input	TCELL36:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_B	input	TCELL36:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_B	input	TCELL37:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_B	input	TCELL37:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_B	input	TCELL37:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0	input	TCELL36:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1	input	TCELL36:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2	input	TCELL36:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3	input	TCELL36:IMUX.BYP.12
CTRL_RST_B_LOW	input	TCELL33:IMUX.CTRL.6
CTRL_RST_B_UPP	input	TCELL41:IMUX.CTRL.7
IDELAY_RST_B0	input	TCELL30:IMUX.CTRL.6
IDELAY_RST_B1	input	TCELL31:IMUX.CTRL.7
IDELAY_RST_B10	input	TCELL43:IMUX.CTRL.7
IDELAY_RST_B11	input	TCELL44:IMUX.CTRL.6
IDELAY_RST_B12	input	TCELL38:IMUX.CTRL.3
IDELAY_RST_B2	input	TCELL32:IMUX.CTRL.7
IDELAY_RST_B3	input	TCELL34:IMUX.CTRL.6
IDELAY_RST_B4	input	TCELL35:IMUX.CTRL.6
IDELAY_RST_B5	input	TCELL36:IMUX.CTRL.5
IDELAY_RST_B6	input	TCELL39:IMUX.CTRL.3
IDELAY_RST_B7	input	TCELL40:IMUX.CTRL.2
IDELAY_RST_B8	input	TCELL41:IMUX.CTRL.2
IDELAY_RST_B9	input	TCELL42:IMUX.CTRL.7
ODELAY_RST_B0	input	TCELL30:IMUX.CTRL.5
ODELAY_RST_B1	input	TCELL31:IMUX.CTRL.6
ODELAY_RST_B10	input	TCELL43:IMUX.CTRL.5
ODELAY_RST_B11	input	TCELL44:IMUX.CTRL.5
ODELAY_RST_B12	input	TCELL38:IMUX.CTRL.2
ODELAY_RST_B2	input	TCELL32:IMUX.CTRL.6
ODELAY_RST_B3	input	TCELL34:IMUX.CTRL.5
ODELAY_RST_B4	input	TCELL35:IMUX.CTRL.4
ODELAY_RST_B5	input	TCELL36:IMUX.CTRL.4
ODELAY_RST_B6	input	TCELL38:IMUX.CTRL.7
ODELAY_RST_B7	input	TCELL39:IMUX.CTRL.7
ODELAY_RST_B8	input	TCELL40:IMUX.CTRL.7
ODELAY_RST_B9	input	TCELL42:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT	output	TCELL37:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUT	output	TCELL37:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUT	output	TCELL37:OUT.15.TMIN
PHY2CLB_SCAN_OUT0	output	TCELL37:OUT.7.TMIN
PHY2CLB_SCAN_OUT1	output	TCELL37:OUT.8.TMIN
PHY2CLB_SCAN_OUT2	output	TCELL37:OUT.9.TMIN
PHY2CLB_SCAN_OUT3	output	TCELL37:OUT.10.TMIN
PHY2CLB_SCAN_OUT4	output	TCELL37:OUT.11.TMIN
PHY2CLB_SCAN_OUT5	output	TCELL37:OUT.12.TMIN
PHY2CLB_SCAN_OUT6	output	TCELL37:OUT.13.TMIN
PHY2CLB_SCAN_OUT7	output	TCELL37:OUT.14.TMIN
RXBIT_RST_B0	input	TCELL30:IMUX.CTRL.4
RXBIT_RST_B1	input	TCELL31:IMUX.CTRL.5
RXBIT_RST_B10	input	TCELL43:IMUX.CTRL.4
RXBIT_RST_B11	input	TCELL44:IMUX.CTRL.4
RXBIT_RST_B12	input	TCELL37:IMUX.CTRL.6
RXBIT_RST_B2	input	TCELL32:IMUX.CTRL.5
RXBIT_RST_B3	input	TCELL34:IMUX.CTRL.3
RXBIT_RST_B4	input	TCELL35:IMUX.CTRL.3
RXBIT_RST_B5	input	TCELL36:IMUX.CTRL.3
RXBIT_RST_B6	input	TCELL38:IMUX.CTRL.6
RXBIT_RST_B7	input	TCELL39:IMUX.CTRL.6
RXBIT_RST_B8	input	TCELL40:IMUX.CTRL.6
RXBIT_RST_B9	input	TCELL42:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0	input	TCELL33:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1	input	TCELL41:IMUX.CTRL.5
TXBIT_RST_B0	input	TCELL30:IMUX.CTRL.3
TXBIT_RST_B1	input	TCELL31:IMUX.CTRL.4
TXBIT_RST_B10	input	TCELL43:IMUX.CTRL.3
TXBIT_RST_B11	input	TCELL44:IMUX.CTRL.3
TXBIT_RST_B12	input	TCELL37:IMUX.CTRL.5
TXBIT_RST_B2	input	TCELL32:IMUX.CTRL.4
TXBIT_RST_B3	input	TCELL34:IMUX.CTRL.2
TXBIT_RST_B4	input	TCELL35:IMUX.CTRL.2
TXBIT_RST_B5	input	TCELL36:IMUX.CTRL.2
TXBIT_RST_B6	input	TCELL38:IMUX.CTRL.5
TXBIT_RST_B7	input	TCELL39:IMUX.CTRL.5
TXBIT_RST_B8	input	TCELL40:IMUX.CTRL.5
TXBIT_RST_B9	input	TCELL42:IMUX.CTRL.3
TXBIT_TRI_RST_B0	input	TCELL30:IMUX.CTRL.2
TXBIT_TRI_RST_B1	input	TCELL31:IMUX.CTRL.3

Bel XIPHY_FEEDTHROUGH3

ultrascale XIPHY bel XIPHY_FEEDTHROUGH3
Pin	Direction	Wires
CLB2PHY_CTRL_CLK_LOW	input	TCELL48:IMUX.CTRL.7
CLB2PHY_CTRL_CLK_UPP	input	TCELL57:IMUX.CTRL.2
CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT	input	TCELL52:IMUX.IMUX.33.DELAY
CLB2PHY_DBG_CLK_STOP_FLG_OUT	input	TCELL52:IMUX.IMUX.32.DELAY
CLB2PHY_DBG_CT_START_EN	input	TCELL52:IMUX.IMUX.7.DELAY
CLB2PHY_FIFO_CLK0	input	TCELL46:IMUX.CTRL.2
CLB2PHY_FIFO_CLK1	input	TCELL47:IMUX.CTRL.3
CLB2PHY_FIFO_CLK10	input	TCELL59:IMUX.CTRL.2
CLB2PHY_FIFO_CLK11	input	TCELL59:IMUX.CTRL.7
CLB2PHY_FIFO_CLK12	input	TCELL53:IMUX.CTRL.4
CLB2PHY_FIFO_CLK2	input	TCELL48:IMUX.CTRL.2
CLB2PHY_FIFO_CLK3	input	TCELL49:IMUX.CTRL.7
CLB2PHY_FIFO_CLK4	input	TCELL50:IMUX.CTRL.7
CLB2PHY_FIFO_CLK5	input	TCELL51:IMUX.CTRL.7
CLB2PHY_FIFO_CLK6	input	TCELL54:IMUX.CTRL.4
CLB2PHY_FIFO_CLK7	input	TCELL55:IMUX.CTRL.4
CLB2PHY_FIFO_CLK8	input	TCELL56:IMUX.CTRL.3
CLB2PHY_FIFO_CLK9	input	TCELL58:IMUX.CTRL.2
CLB2PHY_SCAN_CLK_DIV2	input	TCELL52:IMUX.CTRL.4
CLB2PHY_SCAN_CLK_DIV4	input	TCELL52:IMUX.CTRL.3
CLB2PHY_SCAN_CLK_SDR	input	TCELL52:IMUX.CTRL.2
CLB2PHY_SCAN_EN_B	input	TCELL52:IMUX.BYP.14
CLB2PHY_SCAN_IN0	input	TCELL51:IMUX.BYP.15
CLB2PHY_SCAN_IN1	input	TCELL52:IMUX.BYP.6
CLB2PHY_SCAN_IN2	input	TCELL52:IMUX.BYP.7
CLB2PHY_SCAN_IN3	input	TCELL52:IMUX.BYP.8
CLB2PHY_SCAN_IN4	input	TCELL52:IMUX.BYP.10
CLB2PHY_SCAN_IN5	input	TCELL52:IMUX.BYP.11
CLB2PHY_SCAN_IN6	input	TCELL52:IMUX.BYP.12
CLB2PHY_SCAN_IN7	input	TCELL52:IMUX.BYP.13
CLB2PHY_SCAN_MODE_B	input	TCELL51:IMUX.BYP.14
CLB2PHY_SCAN_RST_MASK_B	input	TCELL51:IMUX.BYP.13
CLB2PHY_TEST_DIV2_CLK_SEL_B	input	TCELL52:IMUX.IMUX.31.DELAY
CLB2PHY_TEST_DIV4_CLK_SEL_B	input	TCELL52:IMUX.IMUX.6.DELAY
CLB2PHY_TEST_SDR_CLK_SEL_B	input	TCELL52:IMUX.IMUX.30.DELAY
CLB2PHY_TEST_SPARE_B0	input	TCELL51:IMUX.BYP.9
CLB2PHY_TEST_SPARE_B1	input	TCELL51:IMUX.BYP.10
CLB2PHY_TEST_SPARE_B2	input	TCELL51:IMUX.BYP.11
CLB2PHY_TEST_SPARE_B3	input	TCELL51:IMUX.BYP.12
CTRL_RST_B_LOW	input	TCELL48:IMUX.CTRL.6
CTRL_RST_B_UPP	input	TCELL56:IMUX.CTRL.7
IDELAY_RST_B0	input	TCELL45:IMUX.CTRL.6
IDELAY_RST_B1	input	TCELL46:IMUX.CTRL.7
IDELAY_RST_B10	input	TCELL58:IMUX.CTRL.7
IDELAY_RST_B11	input	TCELL59:IMUX.CTRL.6
IDELAY_RST_B12	input	TCELL53:IMUX.CTRL.3
IDELAY_RST_B2	input	TCELL47:IMUX.CTRL.7
IDELAY_RST_B3	input	TCELL49:IMUX.CTRL.6
IDELAY_RST_B4	input	TCELL50:IMUX.CTRL.6
IDELAY_RST_B5	input	TCELL51:IMUX.CTRL.5
IDELAY_RST_B6	input	TCELL54:IMUX.CTRL.3
IDELAY_RST_B7	input	TCELL55:IMUX.CTRL.2
IDELAY_RST_B8	input	TCELL56:IMUX.CTRL.2
IDELAY_RST_B9	input	TCELL57:IMUX.CTRL.7
ODELAY_RST_B0	input	TCELL45:IMUX.CTRL.5
ODELAY_RST_B1	input	TCELL46:IMUX.CTRL.6
ODELAY_RST_B10	input	TCELL58:IMUX.CTRL.5
ODELAY_RST_B11	input	TCELL59:IMUX.CTRL.5
ODELAY_RST_B12	input	TCELL53:IMUX.CTRL.2
ODELAY_RST_B2	input	TCELL47:IMUX.CTRL.6
ODELAY_RST_B3	input	TCELL49:IMUX.CTRL.5
ODELAY_RST_B4	input	TCELL50:IMUX.CTRL.4
ODELAY_RST_B5	input	TCELL51:IMUX.CTRL.4
ODELAY_RST_B6	input	TCELL53:IMUX.CTRL.7
ODELAY_RST_B7	input	TCELL54:IMUX.CTRL.7
ODELAY_RST_B8	input	TCELL55:IMUX.CTRL.7
ODELAY_RST_B9	input	TCELL57:IMUX.CTRL.6
PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT	output	TCELL52:OUT.17.TMIN
PHY2CLB_DBG_CLK_STOP_FLG_OUT	output	TCELL52:OUT.16.TMIN
PHY2CLB_DBG_CLK_STOP_OUT	output	TCELL52:OUT.15.TMIN
PHY2CLB_SCAN_OUT0	output	TCELL52:OUT.7.TMIN
PHY2CLB_SCAN_OUT1	output	TCELL52:OUT.8.TMIN
PHY2CLB_SCAN_OUT2	output	TCELL52:OUT.9.TMIN
PHY2CLB_SCAN_OUT3	output	TCELL52:OUT.10.TMIN
PHY2CLB_SCAN_OUT4	output	TCELL52:OUT.11.TMIN
PHY2CLB_SCAN_OUT5	output	TCELL52:OUT.12.TMIN
PHY2CLB_SCAN_OUT6	output	TCELL52:OUT.13.TMIN
PHY2CLB_SCAN_OUT7	output	TCELL52:OUT.14.TMIN
RXBIT_RST_B0	input	TCELL45:IMUX.CTRL.4
RXBIT_RST_B1	input	TCELL46:IMUX.CTRL.5
RXBIT_RST_B10	input	TCELL58:IMUX.CTRL.4
RXBIT_RST_B11	input	TCELL59:IMUX.CTRL.4
RXBIT_RST_B12	input	TCELL52:IMUX.CTRL.6
RXBIT_RST_B2	input	TCELL47:IMUX.CTRL.5
RXBIT_RST_B3	input	TCELL49:IMUX.CTRL.3
RXBIT_RST_B4	input	TCELL50:IMUX.CTRL.3
RXBIT_RST_B5	input	TCELL51:IMUX.CTRL.3
RXBIT_RST_B6	input	TCELL53:IMUX.CTRL.6
RXBIT_RST_B7	input	TCELL54:IMUX.CTRL.6
RXBIT_RST_B8	input	TCELL55:IMUX.CTRL.6
RXBIT_RST_B9	input	TCELL57:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B0	input	TCELL48:IMUX.CTRL.4
TRISTATE_ODELAY_RST_B1	input	TCELL56:IMUX.CTRL.5
TXBIT_RST_B0	input	TCELL45:IMUX.CTRL.3
TXBIT_RST_B1	input	TCELL46:IMUX.CTRL.4
TXBIT_RST_B10	input	TCELL58:IMUX.CTRL.3
TXBIT_RST_B11	input	TCELL59:IMUX.CTRL.3
TXBIT_RST_B12	input	TCELL52:IMUX.CTRL.5
TXBIT_RST_B2	input	TCELL47:IMUX.CTRL.4
TXBIT_RST_B3	input	TCELL49:IMUX.CTRL.2
TXBIT_RST_B4	input	TCELL50:IMUX.CTRL.2
TXBIT_RST_B5	input	TCELL51:IMUX.CTRL.2
TXBIT_RST_B6	input	TCELL53:IMUX.CTRL.5
TXBIT_RST_B7	input	TCELL54:IMUX.CTRL.5
TXBIT_RST_B8	input	TCELL55:IMUX.CTRL.5
TXBIT_RST_B9	input	TCELL57:IMUX.CTRL.3
TXBIT_TRI_RST_B0	input	TCELL45:IMUX.CTRL.2
TXBIT_TRI_RST_B1	input	TCELL46:IMUX.CTRL.3

Bel ABUS_SWITCH_CMT

ultrascale XIPHY bel ABUS_SWITCH_CMT
Pin	Direction	Wires

Bel wires

ultrascale XIPHY bel wires
Wire	Pins
CELL0.OUT.0.TMIN	PLL0.TESTOUT32
CELL0.OUT.1.TMIN	PLL0.TESTOUT33
CELL0.OUT.2.TMIN	PLL0.TESTOUT34
CELL0.OUT.3.TMIN	PLL0.TESTOUT35
CELL0.OUT.4.TMIN	BITSLICE0.PHY2CLB_FIFO_EMPTY
CELL0.OUT.5.TMIN	BITSLICE0.RX_Q0
CELL0.OUT.6.TMIN	BITSLICE0.RX_Q1
CELL0.OUT.7.TMIN	BITSLICE0.RX_Q2
CELL0.OUT.8.TMIN	BITSLICE0.RX_Q3
CELL0.OUT.9.TMIN	BITSLICE0.RX_Q4
CELL0.OUT.10.TMIN	BITSLICE0.RX_Q5
CELL0.OUT.11.TMIN	BITSLICE0.RX_Q6
CELL0.OUT.12.TMIN	BITSLICE0.RX_Q7
CELL0.OUT.13.TMIN	BITSLICE0.TX_CNTVALUEOUT0
CELL0.OUT.14.TMIN	BITSLICE0.TX_CNTVALUEOUT1
CELL0.OUT.15.TMIN	BITSLICE0.TX_CNTVALUEOUT2
CELL0.OUT.16.TMIN	BITSLICE0.TX_CNTVALUEOUT3
CELL0.OUT.17.TMIN	BITSLICE0.TX_CNTVALUEOUT4
CELL0.OUT.18.TMIN	BITSLICE0.TX_CNTVALUEOUT5
CELL0.OUT.19.TMIN	BITSLICE0.TX_CNTVALUEOUT6
CELL0.OUT.20.TMIN	BITSLICE0.TX_CNTVALUEOUT7
CELL0.OUT.21.TMIN	BITSLICE0.TX_CNTVALUEOUT8
CELL0.OUT.22.TMIN	BITSLICE0.TX_T_OUT
CELL0.OUT.23.TMIN	BITSLICE0.RX_CNTVALUEOUT0
CELL0.OUT.24.TMIN	BITSLICE0.RX_CNTVALUEOUT1
CELL0.OUT.25.TMIN	BITSLICE0.RX_CNTVALUEOUT2
CELL0.OUT.26.TMIN	BITSLICE0.RX_CNTVALUEOUT3
CELL0.OUT.27.TMIN	BITSLICE0.RX_CNTVALUEOUT4
CELL0.OUT.28.TMIN	BITSLICE0.RX_CNTVALUEOUT5
CELL0.OUT.29.TMIN	BITSLICE0.RX_CNTVALUEOUT6
CELL0.OUT.30.TMIN	BITSLICE0.RX_CNTVALUEOUT7
CELL0.OUT.31.TMIN	BITSLICE0.RX_CNTVALUEOUT8
CELL0.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.TXBIT_TRI_RST_B0
CELL0.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.TXBIT_RST_B0
CELL0.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.RXBIT_RST_B0
CELL0.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.ODELAY_RST_B0
CELL0.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.IDELAY_RST_B0
CELL0.IMUX.BYP.0	PLL0.TESTIN28
CELL0.IMUX.BYP.1	PLL0.TESTIN29
CELL0.IMUX.BYP.2	PLL0.TESTIN30
CELL0.IMUX.BYP.3	PLL0.TESTIN31
CELL0.IMUX.BYP.6	BITSLICE_T0.EN_VTC
CELL0.IMUX.BYP.7	BITSLICE0.TX_LD
CELL0.IMUX.BYP.8	BITSLICE0.TX_INC
CELL0.IMUX.BYP.9	BITSLICE0.TX_EN_VTC
CELL0.IMUX.BYP.10	BITSLICE0.TX_CE_ODELAY
CELL0.IMUX.BYP.11	BITSLICE0.RX_LD
CELL0.IMUX.BYP.12	BITSLICE0.RX_INC
CELL0.IMUX.BYP.13	BITSLICE0.RX_EN_VTC
CELL0.IMUX.BYP.14	BITSLICE0.RX_CE_IDELAY
CELL0.IMUX.BYP.15	BITSLICE0.DYN_DCI_OUT_INT
CELL0.IMUX.IMUX.6.DELAY	BITSLICE0.TX_CE_OFD
CELL0.IMUX.IMUX.7.DELAY	BITSLICE0.RX_CE_IFD
CELL0.IMUX.IMUX.8.DELAY	BITSLICE0.RX_DATAIN1
CELL0.IMUX.IMUX.9.DELAY	BITSLICE0.CLB2PHY_FIFO_RDEN
CELL0.IMUX.IMUX.10.DELAY	BITSLICE0.TX_D7
CELL0.IMUX.IMUX.11.DELAY	BITSLICE0.TX_D6
CELL0.IMUX.IMUX.12.DELAY	BITSLICE0.TX_D5
CELL0.IMUX.IMUX.13.DELAY	BITSLICE0.TX_D4
CELL0.IMUX.IMUX.14.DELAY	BITSLICE0.TX_D3
CELL0.IMUX.IMUX.15.DELAY	BITSLICE0.TX_D2
CELL0.IMUX.IMUX.16.DELAY	BITSLICE0.TX_T
CELL1.OUT.0.TMIN	PLL0.TESTOUT28
CELL1.OUT.1.TMIN	PLL0.TESTOUT29
CELL1.OUT.2.TMIN	PLL0.TESTOUT30
CELL1.OUT.3.TMIN	PLL0.TESTOUT31
CELL1.OUT.4.TMIN	BITSLICE1.PHY2CLB_FIFO_EMPTY
CELL1.OUT.5.TMIN	BITSLICE1.RX_Q0
CELL1.OUT.6.TMIN	BITSLICE1.RX_Q1
CELL1.OUT.7.TMIN	BITSLICE1.RX_Q2
CELL1.OUT.8.TMIN	BITSLICE1.RX_Q3
CELL1.OUT.9.TMIN	BITSLICE1.RX_Q4
CELL1.OUT.10.TMIN	BITSLICE1.RX_Q5
CELL1.OUT.11.TMIN	BITSLICE1.RX_Q6
CELL1.OUT.12.TMIN	BITSLICE1.RX_Q7
CELL1.OUT.13.TMIN	BITSLICE1.TX_CNTVALUEOUT0
CELL1.OUT.14.TMIN	BITSLICE1.TX_CNTVALUEOUT1
CELL1.OUT.15.TMIN	BITSLICE1.TX_CNTVALUEOUT2
CELL1.OUT.16.TMIN	BITSLICE1.TX_CNTVALUEOUT3
CELL1.OUT.17.TMIN	BITSLICE1.TX_CNTVALUEOUT4
CELL1.OUT.18.TMIN	BITSLICE1.TX_CNTVALUEOUT5
CELL1.OUT.19.TMIN	BITSLICE1.TX_CNTVALUEOUT6
CELL1.OUT.20.TMIN	BITSLICE1.TX_CNTVALUEOUT7
CELL1.OUT.21.TMIN	BITSLICE1.TX_CNTVALUEOUT8
CELL1.OUT.22.TMIN	BITSLICE1.TX_T_OUT
CELL1.OUT.23.TMIN	BITSLICE1.RX_CNTVALUEOUT0
CELL1.OUT.24.TMIN	BITSLICE1.RX_CNTVALUEOUT1
CELL1.OUT.25.TMIN	BITSLICE1.RX_CNTVALUEOUT2
CELL1.OUT.26.TMIN	BITSLICE1.RX_CNTVALUEOUT3
CELL1.OUT.27.TMIN	BITSLICE1.RX_CNTVALUEOUT4
CELL1.OUT.28.TMIN	BITSLICE1.RX_CNTVALUEOUT5
CELL1.OUT.29.TMIN	BITSLICE1.RX_CNTVALUEOUT6
CELL1.OUT.30.TMIN	BITSLICE1.RX_CNTVALUEOUT7
CELL1.OUT.31.TMIN	BITSLICE1.RX_CNTVALUEOUT8
CELL1.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK0
CELL1.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.TXBIT_TRI_RST_B1
CELL1.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.TXBIT_RST_B1
CELL1.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.RXBIT_RST_B1
CELL1.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.ODELAY_RST_B1
CELL1.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.IDELAY_RST_B1
CELL1.IMUX.BYP.0	PLL0.TESTIN24
CELL1.IMUX.BYP.1	PLL0.TESTIN25
CELL1.IMUX.BYP.2	PLL0.TESTIN26
CELL1.IMUX.BYP.3	PLL0.TESTIN27
CELL1.IMUX.BYP.6	BITSLICE_T1.EN_VTC
CELL1.IMUX.BYP.7	BITSLICE1.TX_LD
CELL1.IMUX.BYP.8	BITSLICE1.TX_INC
CELL1.IMUX.BYP.9	BITSLICE1.TX_EN_VTC
CELL1.IMUX.BYP.10	BITSLICE1.TX_CE_ODELAY
CELL1.IMUX.BYP.11	BITSLICE1.RX_LD
CELL1.IMUX.BYP.12	BITSLICE1.RX_INC
CELL1.IMUX.BYP.13	BITSLICE1.RX_EN_VTC
CELL1.IMUX.BYP.14	BITSLICE1.RX_CE_IDELAY
CELL1.IMUX.BYP.15	BITSLICE1.DYN_DCI_OUT_INT
CELL1.IMUX.IMUX.0.DELAY	PLL0.CLKOUTPHY_EN
CELL1.IMUX.IMUX.6.DELAY	BITSLICE0.TX_D1
CELL1.IMUX.IMUX.7.DELAY	BITSLICE0.TX_CNTVALUEIN0
CELL1.IMUX.IMUX.8.DELAY	BITSLICE0.TX_CNTVALUEIN1
CELL1.IMUX.IMUX.9.DELAY	BITSLICE0.TX_CNTVALUEIN2
CELL1.IMUX.IMUX.10.DELAY	BITSLICE0.TX_CNTVALUEIN3
CELL1.IMUX.IMUX.11.DELAY	BITSLICE0.TX_CNTVALUEIN4
CELL1.IMUX.IMUX.12.DELAY	BITSLICE0.TX_CNTVALUEIN5
CELL1.IMUX.IMUX.13.DELAY	BITSLICE0.TX_CNTVALUEIN6
CELL1.IMUX.IMUX.14.DELAY	BITSLICE0.TX_CNTVALUEIN7
CELL1.IMUX.IMUX.15.DELAY	BITSLICE0.TX_CNTVALUEIN8
CELL1.IMUX.IMUX.16.DELAY	BITSLICE0.TX_D0
CELL2.OUT.0.TMIN	PLL0.TESTOUT24
CELL2.OUT.1.TMIN	PLL0.TESTOUT25
CELL2.OUT.2.TMIN	PLL0.TESTOUT26
CELL2.OUT.3.TMIN	PLL0.TESTOUT27
CELL2.OUT.4.TMIN	BITSLICE2.PHY2CLB_FIFO_EMPTY
CELL2.OUT.5.TMIN	BITSLICE2.RX_Q0
CELL2.OUT.6.TMIN	BITSLICE2.RX_Q1
CELL2.OUT.7.TMIN	BITSLICE2.RX_Q2
CELL2.OUT.8.TMIN	BITSLICE2.RX_Q3
CELL2.OUT.9.TMIN	BITSLICE2.RX_Q4
CELL2.OUT.10.TMIN	BITSLICE2.RX_Q5
CELL2.OUT.11.TMIN	BITSLICE2.RX_Q6
CELL2.OUT.12.TMIN	BITSLICE2.RX_Q7
CELL2.OUT.13.TMIN	BITSLICE2.TX_CNTVALUEOUT0
CELL2.OUT.14.TMIN	BITSLICE2.TX_CNTVALUEOUT1
CELL2.OUT.15.TMIN	BITSLICE2.TX_CNTVALUEOUT2
CELL2.OUT.16.TMIN	BITSLICE2.TX_CNTVALUEOUT3
CELL2.OUT.17.TMIN	BITSLICE2.TX_CNTVALUEOUT4
CELL2.OUT.18.TMIN	BITSLICE2.TX_CNTVALUEOUT5
CELL2.OUT.19.TMIN	BITSLICE2.TX_CNTVALUEOUT6
CELL2.OUT.20.TMIN	BITSLICE2.TX_CNTVALUEOUT7
CELL2.OUT.21.TMIN	BITSLICE2.TX_CNTVALUEOUT8
CELL2.OUT.22.TMIN	BITSLICE2.TX_T_OUT
CELL2.OUT.23.TMIN	BITSLICE2.RX_CNTVALUEOUT0
CELL2.OUT.24.TMIN	BITSLICE2.RX_CNTVALUEOUT1
CELL2.OUT.25.TMIN	BITSLICE2.RX_CNTVALUEOUT2
CELL2.OUT.26.TMIN	BITSLICE2.RX_CNTVALUEOUT3
CELL2.OUT.27.TMIN	BITSLICE2.RX_CNTVALUEOUT4
CELL2.OUT.28.TMIN	BITSLICE2.RX_CNTVALUEOUT5
CELL2.OUT.29.TMIN	BITSLICE2.RX_CNTVALUEOUT6
CELL2.OUT.30.TMIN	BITSLICE2.RX_CNTVALUEOUT7
CELL2.OUT.31.TMIN	BITSLICE2.RX_CNTVALUEOUT8
CELL2.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK1
CELL2.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.TXBIT_RST_B2
CELL2.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.RXBIT_RST_B2
CELL2.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.ODELAY_RST_B2
CELL2.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.IDELAY_RST_B2
CELL2.IMUX.BYP.0	PLL0.TESTIN20
CELL2.IMUX.BYP.1	PLL0.TESTIN21
CELL2.IMUX.BYP.2	PLL0.TESTIN22
CELL2.IMUX.BYP.3	PLL0.TESTIN23
CELL2.IMUX.BYP.6	BITSLICE2.TX_LD
CELL2.IMUX.BYP.7	BITSLICE2.TX_INC
CELL2.IMUX.BYP.8	BITSLICE2.TX_EN_VTC
CELL2.IMUX.BYP.9	BITSLICE2.TX_CE_ODELAY
CELL2.IMUX.BYP.10	BITSLICE2.RX_LD
CELL2.IMUX.BYP.11	BITSLICE2.RX_INC
CELL2.IMUX.BYP.12	BITSLICE2.RX_EN_VTC
CELL2.IMUX.BYP.13	BITSLICE2.RX_CE_IDELAY
CELL2.IMUX.BYP.14	BITSLICE2.DYN_DCI_OUT_INT
CELL2.IMUX.BYP.15	BITSLICE_T0.CE_OFD
CELL2.IMUX.IMUX.6.DELAY	BITSLICE1.TX_D1
CELL2.IMUX.IMUX.7.DELAY	BITSLICE1.TX_D3
CELL2.IMUX.IMUX.8.DELAY	BITSLICE1.TX_D7
CELL2.IMUX.IMUX.9.DELAY	BITSLICE1.TX_CNTVALUEIN1
CELL2.IMUX.IMUX.10.DELAY	BITSLICE1.TX_CNTVALUEIN5
CELL2.IMUX.IMUX.11.DELAY	BITSLICE1.TX_CNTVALUEIN7
CELL2.IMUX.IMUX.12.DELAY	BITSLICE1.RX_CNTVALUEIN2
CELL2.IMUX.IMUX.13.DELAY	BITSLICE1.RX_CNTVALUEIN4
CELL2.IMUX.IMUX.14.DELAY	BITSLICE1.RX_CNTVALUEIN8
CELL2.IMUX.IMUX.15.DELAY	BITSLICE2.TX_CE_OFD
CELL2.IMUX.IMUX.16.DELAY	BITSLICE0.RX_CNTVALUEIN0
CELL2.IMUX.IMUX.17.DELAY	BITSLICE0.RX_CNTVALUEIN1
CELL2.IMUX.IMUX.18.DELAY	BITSLICE0.RX_CNTVALUEIN2
CELL2.IMUX.IMUX.19.DELAY	BITSLICE0.RX_CNTVALUEIN3
CELL2.IMUX.IMUX.20.DELAY	BITSLICE0.RX_CNTVALUEIN4
CELL2.IMUX.IMUX.21.DELAY	BITSLICE0.RX_CNTVALUEIN5
CELL2.IMUX.IMUX.22.DELAY	BITSLICE0.RX_CNTVALUEIN6
CELL2.IMUX.IMUX.23.DELAY	BITSLICE0.RX_CNTVALUEIN7
CELL2.IMUX.IMUX.24.DELAY	BITSLICE0.RX_CNTVALUEIN8
CELL2.IMUX.IMUX.25.DELAY	BITSLICE1.TX_T
CELL2.IMUX.IMUX.26.DELAY	BITSLICE1.TX_CE_OFD
CELL2.IMUX.IMUX.27.DELAY	BITSLICE1.RX_CE_IFD
CELL2.IMUX.IMUX.28.DELAY	BITSLICE1.RX_DATAIN1
CELL2.IMUX.IMUX.29.DELAY	BITSLICE1.CLB2PHY_FIFO_RDEN
CELL2.IMUX.IMUX.30.DELAY	BITSLICE1.TX_D0
CELL2.IMUX.IMUX.31.DELAY	BITSLICE1.TX_D2
CELL2.IMUX.IMUX.32.DELAY	BITSLICE1.TX_D4
CELL2.IMUX.IMUX.33.DELAY	BITSLICE1.TX_D5
CELL2.IMUX.IMUX.34.DELAY	BITSLICE1.TX_D6
CELL2.IMUX.IMUX.35.DELAY	BITSLICE1.TX_CNTVALUEIN0
CELL2.IMUX.IMUX.36.DELAY	BITSLICE1.TX_CNTVALUEIN2
CELL2.IMUX.IMUX.37.DELAY	BITSLICE1.TX_CNTVALUEIN3
CELL2.IMUX.IMUX.38.DELAY	BITSLICE1.TX_CNTVALUEIN4
CELL2.IMUX.IMUX.39.DELAY	BITSLICE1.TX_CNTVALUEIN6
CELL2.IMUX.IMUX.40.DELAY	BITSLICE1.TX_CNTVALUEIN8
CELL2.IMUX.IMUX.41.DELAY	BITSLICE1.RX_CNTVALUEIN0
CELL2.IMUX.IMUX.42.DELAY	BITSLICE1.RX_CNTVALUEIN1
CELL2.IMUX.IMUX.43.DELAY	BITSLICE1.RX_CNTVALUEIN3
CELL2.IMUX.IMUX.44.DELAY	BITSLICE1.RX_CNTVALUEIN5
CELL2.IMUX.IMUX.45.DELAY	BITSLICE1.RX_CNTVALUEIN6
CELL2.IMUX.IMUX.46.DELAY	BITSLICE1.RX_CNTVALUEIN7
CELL2.IMUX.IMUX.47.DELAY	BITSLICE2.TX_T
CELL3.OUT.0.TMIN	PLL0.TESTOUT20
CELL3.OUT.1.TMIN	PLL0.TESTOUT21
CELL3.OUT.2.TMIN	PLL0.TESTOUT22
CELL3.OUT.3.TMIN	PLL0.TESTOUT23
CELL3.OUT.4.TMIN	BITSLICE_T0.CNTVALUEOUT0
CELL3.OUT.5.TMIN	BITSLICE_T0.CNTVALUEOUT1
CELL3.OUT.6.TMIN	BITSLICE_T0.CNTVALUEOUT2
CELL3.OUT.7.TMIN	BITSLICE_T0.CNTVALUEOUT3
CELL3.OUT.8.TMIN	BITSLICE_T0.CNTVALUEOUT4
CELL3.OUT.9.TMIN	BITSLICE_T0.CNTVALUEOUT5
CELL3.OUT.10.TMIN	BITSLICE_T0.CNTVALUEOUT6
CELL3.OUT.11.TMIN	BITSLICE_T0.CNTVALUEOUT7
CELL3.OUT.12.TMIN	BITSLICE_T0.CNTVALUEOUT8
CELL3.OUT.13.TMIN	BITSLICE3.TX_T_OUT
CELL3.OUT.14.TMIN	BITSLICE_CONTROL0.PHY2CLB_PHY_RDY
CELL3.OUT.15.TMIN	BITSLICE_CONTROL0.MASTER_PD_OUT
CELL3.OUT.16.TMIN	BITSLICE_CONTROL0.PHY2CLB_FIXDLY_RDY
CELL3.OUT.17.TMIN	BITSLICE_CONTROL0.CTRL_DLY_TEST_OUT
CELL3.OUT.18.TMIN	BITSLICE3.PHY2CLB_FIFO_EMPTY
CELL3.OUT.19.TMIN	BITSLICE3.RX_Q0
CELL3.OUT.20.TMIN	BITSLICE3.RX_Q1
CELL3.OUT.21.TMIN	BITSLICE3.RX_Q2
CELL3.OUT.22.TMIN	BITSLICE3.RX_Q3
CELL3.OUT.23.TMIN	BITSLICE3.RX_Q4
CELL3.OUT.24.TMIN	BITSLICE3.RX_Q5
CELL3.OUT.25.TMIN	BITSLICE3.RX_Q6
CELL3.OUT.26.TMIN	BITSLICE3.RX_Q7
CELL3.OUT.27.TMIN	BITSLICE3.TX_CNTVALUEOUT0
CELL3.OUT.28.TMIN	BITSLICE3.TX_CNTVALUEOUT1
CELL3.OUT.29.TMIN	BITSLICE3.TX_CNTVALUEOUT2
CELL3.OUT.30.TMIN	BITSLICE3.TX_CNTVALUEOUT3
CELL3.OUT.31.TMIN	BITSLICE3.TX_CNTVALUEOUT4
CELL3.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK2
CELL3.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.TRISTATE_ODELAY_RST_B0
CELL3.IMUX.CTRL.5	BITSLICE_CONTROL0.REFCLK
CELL3.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.CTRL_RST_B_LOW
CELL3.IMUX.CTRL.7	BITSLICE_CONTROL0.RIU_CLK, XIPHY_FEEDTHROUGH0.CLB2PHY_CTRL_CLK_LOW
CELL3.IMUX.BYP.0	PLL0.TESTIN16
CELL3.IMUX.BYP.1	PLL0.TESTIN17
CELL3.IMUX.BYP.2	PLL0.TESTIN18
CELL3.IMUX.BYP.3	PLL0.TESTIN19
CELL3.IMUX.BYP.6	BITSLICE_T0.LD
CELL3.IMUX.BYP.7	BITSLICE_T0.INC
CELL3.IMUX.BYP.8	BITSLICE_T0.CE_ODELAY
CELL3.IMUX.BYP.9	BITSLICE_CONTROL0.EN_VTC
CELL3.IMUX.BYP.10	BITSLICE_CONTROL0.CTRL_DLY_TEST_IN
CELL3.IMUX.BYP.12	BITSLICE3.TX_LD
CELL3.IMUX.BYP.13	BITSLICE3.TX_INC
CELL3.IMUX.BYP.14	BITSLICE3.TX_EN_VTC
CELL3.IMUX.BYP.15	BITSLICE3.TX_CE_ODELAY
CELL3.IMUX.IMUX.6.DELAY	BITSLICE2.TX_CNTVALUEIN3
CELL3.IMUX.IMUX.7.DELAY	BITSLICE2.TX_CNTVALUEIN5
CELL3.IMUX.IMUX.8.DELAY	BITSLICE2.RX_CNTVALUEIN0
CELL3.IMUX.IMUX.9.DELAY	BITSLICE2.RX_CNTVALUEIN2
CELL3.IMUX.IMUX.10.DELAY	BITSLICE2.RX_CNTVALUEIN6
CELL3.IMUX.IMUX.11.DELAY	BITSLICE2.RX_CNTVALUEIN8
CELL3.IMUX.IMUX.12.DELAY	BITSLICE_T0.CNTVALUEIN3
CELL3.IMUX.IMUX.13.DELAY	BITSLICE_T0.CNTVALUEIN5
CELL3.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL0.CLB2RIU_NIBBLE_SEL
CELL3.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS1_1
CELL3.IMUX.IMUX.16.DELAY	BITSLICE2.RX_CE_IFD
CELL3.IMUX.IMUX.17.DELAY	BITSLICE2.RX_DATAIN1
CELL3.IMUX.IMUX.18.DELAY	BITSLICE2.CLB2PHY_FIFO_RDEN
CELL3.IMUX.IMUX.20.DELAY	BITSLICE2.TX_D0
CELL3.IMUX.IMUX.21.DELAY	BITSLICE2.TX_D1
CELL3.IMUX.IMUX.22.DELAY	BITSLICE2.TX_D2
CELL3.IMUX.IMUX.23.DELAY	BITSLICE2.TX_D3
CELL3.IMUX.IMUX.24.DELAY	BITSLICE2.TX_D4
CELL3.IMUX.IMUX.25.DELAY	BITSLICE2.TX_D5
CELL3.IMUX.IMUX.26.DELAY	BITSLICE2.TX_D6
CELL3.IMUX.IMUX.27.DELAY	BITSLICE2.TX_D7
CELL3.IMUX.IMUX.28.DELAY	BITSLICE2.TX_CNTVALUEIN0
CELL3.IMUX.IMUX.29.DELAY	BITSLICE2.TX_CNTVALUEIN1
CELL3.IMUX.IMUX.30.DELAY	BITSLICE2.TX_CNTVALUEIN2
CELL3.IMUX.IMUX.31.DELAY	BITSLICE2.TX_CNTVALUEIN4
CELL3.IMUX.IMUX.32.DELAY	BITSLICE2.TX_CNTVALUEIN6
CELL3.IMUX.IMUX.33.DELAY	BITSLICE2.TX_CNTVALUEIN7
CELL3.IMUX.IMUX.34.DELAY	BITSLICE2.TX_CNTVALUEIN8
CELL3.IMUX.IMUX.35.DELAY	BITSLICE2.RX_CNTVALUEIN1
CELL3.IMUX.IMUX.36.DELAY	BITSLICE2.RX_CNTVALUEIN3
CELL3.IMUX.IMUX.37.DELAY	BITSLICE2.RX_CNTVALUEIN4
CELL3.IMUX.IMUX.38.DELAY	BITSLICE2.RX_CNTVALUEIN5
CELL3.IMUX.IMUX.39.DELAY	BITSLICE2.RX_CNTVALUEIN7
CELL3.IMUX.IMUX.40.DELAY	BITSLICE_T0.CNTVALUEIN0
CELL3.IMUX.IMUX.41.DELAY	BITSLICE_T0.CNTVALUEIN1
CELL3.IMUX.IMUX.42.DELAY	BITSLICE_T0.CNTVALUEIN2
CELL3.IMUX.IMUX.43.DELAY	BITSLICE_T0.CNTVALUEIN4
CELL3.IMUX.IMUX.44.DELAY	BITSLICE_T0.CNTVALUEIN6
CELL3.IMUX.IMUX.45.DELAY	BITSLICE_T0.CNTVALUEIN7
CELL3.IMUX.IMUX.46.DELAY	BITSLICE_T0.CNTVALUEIN8
CELL3.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS1_0
CELL4.OUT.0.TMIN	PLL0.TESTOUT16
CELL4.OUT.1.TMIN	PLL0.TESTOUT17
CELL4.OUT.2.TMIN	PLL0.TESTOUT18
CELL4.OUT.3.TMIN	PLL0.TESTOUT19
CELL4.OUT.4.TMIN	BITSLICE3.TX_CNTVALUEOUT5
CELL4.OUT.5.TMIN	BITSLICE3.TX_CNTVALUEOUT6
CELL4.OUT.6.TMIN	BITSLICE3.TX_CNTVALUEOUT7
CELL4.OUT.7.TMIN	BITSLICE3.TX_CNTVALUEOUT8
CELL4.OUT.8.TMIN	BITSLICE4.TX_T_OUT
CELL4.OUT.9.TMIN	BITSLICE3.RX_CNTVALUEOUT0
CELL4.OUT.10.TMIN	BITSLICE3.RX_CNTVALUEOUT1
CELL4.OUT.11.TMIN	BITSLICE3.RX_CNTVALUEOUT2
CELL4.OUT.12.TMIN	BITSLICE3.RX_CNTVALUEOUT3
CELL4.OUT.13.TMIN	BITSLICE3.RX_CNTVALUEOUT4
CELL4.OUT.14.TMIN	BITSLICE3.RX_CNTVALUEOUT5
CELL4.OUT.15.TMIN	BITSLICE3.RX_CNTVALUEOUT6
CELL4.OUT.16.TMIN	BITSLICE3.RX_CNTVALUEOUT7
CELL4.OUT.17.TMIN	BITSLICE3.RX_CNTVALUEOUT8
CELL4.OUT.18.TMIN	BITSLICE4.PHY2CLB_FIFO_EMPTY
CELL4.OUT.19.TMIN	BITSLICE4.RX_Q0
CELL4.OUT.20.TMIN	BITSLICE4.RX_Q1
CELL4.OUT.21.TMIN	BITSLICE4.RX_Q2
CELL4.OUT.22.TMIN	BITSLICE4.RX_Q3
CELL4.OUT.23.TMIN	BITSLICE4.RX_Q4
CELL4.OUT.24.TMIN	BITSLICE4.RX_Q5
CELL4.OUT.25.TMIN	BITSLICE4.RX_Q6
CELL4.OUT.26.TMIN	BITSLICE4.RX_Q7
CELL4.OUT.27.TMIN	BITSLICE4.TX_CNTVALUEOUT0
CELL4.OUT.28.TMIN	BITSLICE4.TX_CNTVALUEOUT1
CELL4.OUT.29.TMIN	BITSLICE4.TX_CNTVALUEOUT2
CELL4.OUT.30.TMIN	BITSLICE4.TX_CNTVALUEOUT3
CELL4.OUT.31.TMIN	BITSLICE4.TX_CNTVALUEOUT4
CELL4.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.TXBIT_RST_B3
CELL4.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.RXBIT_RST_B3
CELL4.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.ODELAY_RST_B3
CELL4.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.IDELAY_RST_B3
CELL4.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK3
CELL4.IMUX.BYP.0	PLL0.TESTIN12
CELL4.IMUX.BYP.1	PLL0.TESTIN13
CELL4.IMUX.BYP.2	PLL0.TESTIN14
CELL4.IMUX.BYP.3	PLL0.TESTIN15
CELL4.IMUX.BYP.6	BITSLICE3.RX_LD
CELL4.IMUX.BYP.7	BITSLICE3.RX_INC
CELL4.IMUX.BYP.8	BITSLICE3.RX_EN_VTC
CELL4.IMUX.BYP.9	BITSLICE3.RX_CE_IDELAY
CELL4.IMUX.BYP.10	BITSLICE3.DYN_DCI_OUT_INT
CELL4.IMUX.BYP.11	BITSLICE4.TX_LD
CELL4.IMUX.BYP.12	BITSLICE4.TX_INC
CELL4.IMUX.BYP.13	BITSLICE4.TX_EN_VTC
CELL4.IMUX.BYP.14	BITSLICE4.TX_CE_ODELAY
CELL4.IMUX.BYP.15	BITSLICE4.RX_LD
CELL4.IMUX.IMUX.6.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS1_1
CELL4.IMUX.IMUX.7.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS1_3
CELL4.IMUX.IMUX.8.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS0_3
CELL4.IMUX.IMUX.9.DELAY	BITSLICE3.TX_CE_OFD
CELL4.IMUX.IMUX.10.DELAY	BITSLICE3.TX_D0
CELL4.IMUX.IMUX.11.DELAY	BITSLICE3.TX_D2
CELL4.IMUX.IMUX.12.DELAY	BITSLICE3.TX_D6
CELL4.IMUX.IMUX.13.DELAY	BITSLICE3.TX_D7
CELL4.IMUX.IMUX.14.DELAY	BITSLICE3.TX_CNTVALUEIN3
CELL4.IMUX.IMUX.15.DELAY	BITSLICE3.TX_CNTVALUEIN5
CELL4.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS1_2
CELL4.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS1_3
CELL4.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS0_0
CELL4.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS0_1
CELL4.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS0_2
CELL4.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL0.CLB2PHY_WRCS0_3
CELL4.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL0.CLB2PHY_T_B0
CELL4.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL0.CLB2PHY_T_B1
CELL4.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL0.CLB2PHY_T_B2
CELL4.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL0.CLB2PHY_T_B3
CELL4.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDEN0
CELL4.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDEN1
CELL4.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDEN2
CELL4.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDEN3
CELL4.IMUX.IMUX.30.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS1_0
CELL4.IMUX.IMUX.31.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS1_2
CELL4.IMUX.IMUX.32.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS0_0
CELL4.IMUX.IMUX.33.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS0_1
CELL4.IMUX.IMUX.34.DELAY	BITSLICE_CONTROL0.CLB2PHY_RDCS0_2
CELL4.IMUX.IMUX.35.DELAY	BITSLICE3.TX_T
CELL4.IMUX.IMUX.36.DELAY	BITSLICE3.RX_CE_IFD
CELL4.IMUX.IMUX.37.DELAY	BITSLICE3.RX_DATAIN1
CELL4.IMUX.IMUX.38.DELAY	BITSLICE3.CLB2PHY_FIFO_RDEN
CELL4.IMUX.IMUX.39.DELAY	BITSLICE3.TX_D1
CELL4.IMUX.IMUX.40.DELAY	BITSLICE3.TX_D3
CELL4.IMUX.IMUX.41.DELAY	BITSLICE3.TX_D4
CELL4.IMUX.IMUX.42.DELAY	BITSLICE3.TX_D5
CELL4.IMUX.IMUX.44.DELAY	BITSLICE3.TX_CNTVALUEIN0
CELL4.IMUX.IMUX.45.DELAY	BITSLICE3.TX_CNTVALUEIN1
CELL4.IMUX.IMUX.46.DELAY	BITSLICE3.TX_CNTVALUEIN2
CELL4.IMUX.IMUX.47.DELAY	BITSLICE3.TX_CNTVALUEIN4
CELL5.OUT.0.TMIN	PLL0.TESTOUT12
CELL5.OUT.1.TMIN	PLL0.TESTOUT13
CELL5.OUT.2.TMIN	PLL0.TESTOUT14
CELL5.OUT.3.TMIN	PLL0.TESTOUT15
CELL5.OUT.4.TMIN	BITSLICE4.TX_CNTVALUEOUT5
CELL5.OUT.5.TMIN	BITSLICE4.TX_CNTVALUEOUT6
CELL5.OUT.6.TMIN	BITSLICE4.TX_CNTVALUEOUT7
CELL5.OUT.7.TMIN	BITSLICE4.TX_CNTVALUEOUT8
CELL5.OUT.8.TMIN	BITSLICE5.TX_T_OUT
CELL5.OUT.9.TMIN	BITSLICE4.RX_CNTVALUEOUT0
CELL5.OUT.10.TMIN	BITSLICE4.RX_CNTVALUEOUT1
CELL5.OUT.11.TMIN	BITSLICE4.RX_CNTVALUEOUT2
CELL5.OUT.12.TMIN	BITSLICE4.RX_CNTVALUEOUT3
CELL5.OUT.13.TMIN	BITSLICE4.RX_CNTVALUEOUT4
CELL5.OUT.14.TMIN	BITSLICE4.RX_CNTVALUEOUT5
CELL5.OUT.15.TMIN	BITSLICE4.RX_CNTVALUEOUT6
CELL5.OUT.16.TMIN	BITSLICE4.RX_CNTVALUEOUT7
CELL5.OUT.17.TMIN	BITSLICE4.RX_CNTVALUEOUT8
CELL5.OUT.18.TMIN	BITSLICE5.PHY2CLB_FIFO_EMPTY
CELL5.OUT.19.TMIN	BITSLICE5.RX_Q0
CELL5.OUT.20.TMIN	BITSLICE5.RX_Q1
CELL5.OUT.21.TMIN	BITSLICE5.RX_Q2
CELL5.OUT.22.TMIN	BITSLICE5.RX_Q3
CELL5.OUT.23.TMIN	BITSLICE5.RX_Q4
CELL5.OUT.24.TMIN	BITSLICE5.RX_Q5
CELL5.OUT.25.TMIN	BITSLICE5.RX_Q6
CELL5.OUT.26.TMIN	BITSLICE5.RX_Q7
CELL5.OUT.27.TMIN	BITSLICE5.TX_CNTVALUEOUT0
CELL5.OUT.28.TMIN	BITSLICE5.TX_CNTVALUEOUT1
CELL5.OUT.29.TMIN	BITSLICE5.TX_CNTVALUEOUT2
CELL5.OUT.30.TMIN	BITSLICE5.TX_CNTVALUEOUT3
CELL5.OUT.31.TMIN	BITSLICE5.TX_CNTVALUEOUT4
CELL5.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.TXBIT_RST_B4
CELL5.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.RXBIT_RST_B4
CELL5.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.ODELAY_RST_B4
CELL5.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.IDELAY_RST_B4
CELL5.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK4
CELL5.IMUX.BYP.0	PLL0.TESTIN8
CELL5.IMUX.BYP.1	PLL0.TESTIN9
CELL5.IMUX.BYP.2	PLL0.TESTIN10
CELL5.IMUX.BYP.3	PLL0.TESTIN11
CELL5.IMUX.BYP.6	BITSLICE4.RX_INC
CELL5.IMUX.BYP.7	BITSLICE4.RX_EN_VTC
CELL5.IMUX.BYP.8	BITSLICE4.RX_CE_IDELAY
CELL5.IMUX.BYP.9	BITSLICE4.DYN_DCI_OUT_INT
CELL5.IMUX.BYP.10	BITSLICE5.TX_LD
CELL5.IMUX.BYP.11	BITSLICE5.TX_INC
CELL5.IMUX.BYP.12	BITSLICE5.TX_EN_VTC
CELL5.IMUX.BYP.13	BITSLICE5.TX_CE_ODELAY
CELL5.IMUX.BYP.14	BITSLICE5.RX_LD
CELL5.IMUX.BYP.15	BITSLICE5.RX_INC
CELL5.IMUX.IMUX.6.DELAY	BITSLICE4.RX_DATAIN1
CELL5.IMUX.IMUX.7.DELAY	BITSLICE4.TX_D0
CELL5.IMUX.IMUX.8.DELAY	BITSLICE4.TX_D4
CELL5.IMUX.IMUX.9.DELAY	BITSLICE4.TX_D6
CELL5.IMUX.IMUX.10.DELAY	BITSLICE4.TX_CNTVALUEIN2
CELL5.IMUX.IMUX.11.DELAY	BITSLICE4.TX_CNTVALUEIN4
CELL5.IMUX.IMUX.12.DELAY	BITSLICE4.TX_CNTVALUEIN8
CELL5.IMUX.IMUX.13.DELAY	BITSLICE4.RX_CNTVALUEIN1
CELL5.IMUX.IMUX.14.DELAY	BITSLICE4.RX_CNTVALUEIN5
CELL5.IMUX.IMUX.15.DELAY	BITSLICE4.RX_CNTVALUEIN7
CELL5.IMUX.IMUX.16.DELAY	BITSLICE3.TX_CNTVALUEIN6
CELL5.IMUX.IMUX.17.DELAY	BITSLICE3.TX_CNTVALUEIN7
CELL5.IMUX.IMUX.18.DELAY	BITSLICE3.TX_CNTVALUEIN8
CELL5.IMUX.IMUX.19.DELAY	BITSLICE3.RX_CNTVALUEIN0
CELL5.IMUX.IMUX.20.DELAY	BITSLICE3.RX_CNTVALUEIN1
CELL5.IMUX.IMUX.21.DELAY	BITSLICE3.RX_CNTVALUEIN2
CELL5.IMUX.IMUX.22.DELAY	BITSLICE3.RX_CNTVALUEIN3
CELL5.IMUX.IMUX.23.DELAY	BITSLICE3.RX_CNTVALUEIN4
CELL5.IMUX.IMUX.24.DELAY	BITSLICE3.RX_CNTVALUEIN5
CELL5.IMUX.IMUX.25.DELAY	BITSLICE3.RX_CNTVALUEIN6
CELL5.IMUX.IMUX.26.DELAY	BITSLICE3.RX_CNTVALUEIN7
CELL5.IMUX.IMUX.27.DELAY	BITSLICE3.RX_CNTVALUEIN8
CELL5.IMUX.IMUX.28.DELAY	BITSLICE4.TX_T
CELL5.IMUX.IMUX.29.DELAY	BITSLICE4.TX_CE_OFD
CELL5.IMUX.IMUX.30.DELAY	BITSLICE4.RX_CE_IFD
CELL5.IMUX.IMUX.31.DELAY	BITSLICE4.CLB2PHY_FIFO_RDEN
CELL5.IMUX.IMUX.32.DELAY	BITSLICE4.TX_D1
CELL5.IMUX.IMUX.33.DELAY	BITSLICE4.TX_D2
CELL5.IMUX.IMUX.34.DELAY	BITSLICE4.TX_D3
CELL5.IMUX.IMUX.35.DELAY	BITSLICE4.TX_D5
CELL5.IMUX.IMUX.36.DELAY	BITSLICE4.TX_D7
CELL5.IMUX.IMUX.37.DELAY	BITSLICE4.TX_CNTVALUEIN0
CELL5.IMUX.IMUX.38.DELAY	BITSLICE4.TX_CNTVALUEIN1
CELL5.IMUX.IMUX.39.DELAY	BITSLICE4.TX_CNTVALUEIN3
CELL5.IMUX.IMUX.40.DELAY	BITSLICE4.TX_CNTVALUEIN5
CELL5.IMUX.IMUX.41.DELAY	BITSLICE4.TX_CNTVALUEIN6
CELL5.IMUX.IMUX.42.DELAY	BITSLICE4.TX_CNTVALUEIN7
CELL5.IMUX.IMUX.43.DELAY	BITSLICE4.RX_CNTVALUEIN0
CELL5.IMUX.IMUX.44.DELAY	BITSLICE4.RX_CNTVALUEIN2
CELL5.IMUX.IMUX.45.DELAY	BITSLICE4.RX_CNTVALUEIN3
CELL5.IMUX.IMUX.46.DELAY	BITSLICE4.RX_CNTVALUEIN4
CELL5.IMUX.IMUX.47.DELAY	BITSLICE4.RX_CNTVALUEIN6
CELL6.OUT.0.TMIN	PLL0.TESTOUT8
CELL6.OUT.1.TMIN	PLL0.TESTOUT9
CELL6.OUT.2.TMIN	PLL0.TESTOUT10
CELL6.OUT.3.TMIN	PLL0.TESTOUT11
CELL6.OUT.4.TMIN	BITSLICE5.TX_CNTVALUEOUT5
CELL6.OUT.5.TMIN	BITSLICE5.TX_CNTVALUEOUT6
CELL6.OUT.6.TMIN	BITSLICE5.TX_CNTVALUEOUT7
CELL6.OUT.7.TMIN	BITSLICE5.TX_CNTVALUEOUT8
CELL6.OUT.8.TMIN	BITSLICE6.TX_T_OUT
CELL6.OUT.9.TMIN	BITSLICE5.RX_CNTVALUEOUT0
CELL6.OUT.10.TMIN	BITSLICE5.RX_CNTVALUEOUT1
CELL6.OUT.11.TMIN	BITSLICE5.RX_CNTVALUEOUT2
CELL6.OUT.12.TMIN	BITSLICE5.RX_CNTVALUEOUT3
CELL6.OUT.13.TMIN	BITSLICE5.RX_CNTVALUEOUT4
CELL6.OUT.14.TMIN	BITSLICE5.RX_CNTVALUEOUT5
CELL6.OUT.15.TMIN	BITSLICE5.RX_CNTVALUEOUT6
CELL6.OUT.16.TMIN	BITSLICE5.RX_CNTVALUEOUT7
CELL6.OUT.17.TMIN	BITSLICE5.RX_CNTVALUEOUT8
CELL6.OUT.18.TMIN	RIU_OR0.RIU_RD_VALID
CELL6.OUT.19.TMIN	RIU_OR0.RIU_RD_DATA0
CELL6.OUT.20.TMIN	RIU_OR0.RIU_RD_DATA1
CELL6.OUT.21.TMIN	RIU_OR0.RIU_RD_DATA2
CELL6.OUT.22.TMIN	RIU_OR0.RIU_RD_DATA3
CELL6.OUT.23.TMIN	RIU_OR0.RIU_RD_DATA4
CELL6.OUT.24.TMIN	RIU_OR0.RIU_RD_DATA5
CELL6.OUT.25.TMIN	RIU_OR0.RIU_RD_DATA6
CELL6.OUT.26.TMIN	RIU_OR0.RIU_RD_DATA7
CELL6.OUT.27.TMIN	RIU_OR0.RIU_RD_DATA8
CELL6.OUT.28.TMIN	RIU_OR0.RIU_RD_DATA9
CELL6.OUT.29.TMIN	RIU_OR0.RIU_RD_DATA10
CELL6.OUT.30.TMIN	RIU_OR0.RIU_RD_DATA11
CELL6.OUT.31.TMIN	RIU_OR0.RIU_RD_DATA12
CELL6.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.TXBIT_RST_B5
CELL6.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.RXBIT_RST_B5
CELL6.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.ODELAY_RST_B5
CELL6.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.IDELAY_RST_B5
CELL6.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK5
CELL6.IMUX.BYP.0	PLL0.TESTIN4
CELL6.IMUX.BYP.1	PLL0.TESTIN5
CELL6.IMUX.BYP.2	PLL0.TESTIN6
CELL6.IMUX.BYP.3	PLL0.TESTIN7
CELL6.IMUX.BYP.6	BITSLICE5.RX_EN_VTC
CELL6.IMUX.BYP.7	BITSLICE5.RX_CE_IDELAY
CELL6.IMUX.BYP.8	BITSLICE5.DYN_DCI_OUT_INT
CELL6.IMUX.BYP.9	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B0
CELL6.IMUX.BYP.10	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B1
CELL6.IMUX.BYP.11	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B2
CELL6.IMUX.BYP.12	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SPARE_B3
CELL6.IMUX.BYP.13	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_RST_MASK_B
CELL6.IMUX.BYP.14	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_MODE_B
CELL6.IMUX.BYP.15	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN0
CELL6.IMUX.IMUX.0.DELAY	PLL0.SCANMODEB
CELL6.IMUX.IMUX.6.DELAY	BITSLICE5.TX_CNTVALUEIN1
CELL6.IMUX.IMUX.7.DELAY	BITSLICE5.TX_CNTVALUEIN3
CELL6.IMUX.IMUX.8.DELAY	BITSLICE5.TX_CNTVALUEIN7
CELL6.IMUX.IMUX.10.DELAY	BITSLICE5.RX_CNTVALUEIN3
CELL6.IMUX.IMUX.11.DELAY	BITSLICE5.RX_CNTVALUEIN5
CELL6.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_EN, BITSLICE_CONTROL1.CLB2RIU_WR_EN
CELL6.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA1, BITSLICE_CONTROL1.CLB2RIU_WR_DATA1
CELL6.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA5, BITSLICE_CONTROL1.CLB2RIU_WR_DATA5
CELL6.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA7, BITSLICE_CONTROL1.CLB2RIU_WR_DATA7
CELL6.IMUX.IMUX.16.DELAY	BITSLICE4.RX_CNTVALUEIN8
CELL6.IMUX.IMUX.17.DELAY	BITSLICE5.TX_T
CELL6.IMUX.IMUX.18.DELAY	BITSLICE5.TX_CE_OFD
CELL6.IMUX.IMUX.19.DELAY	BITSLICE5.RX_CE_IFD
CELL6.IMUX.IMUX.20.DELAY	BITSLICE5.RX_DATAIN1
CELL6.IMUX.IMUX.21.DELAY	BITSLICE5.CLB2PHY_FIFO_RDEN
CELL6.IMUX.IMUX.22.DELAY	BITSLICE5.TX_D0
CELL6.IMUX.IMUX.23.DELAY	BITSLICE5.TX_D1
CELL6.IMUX.IMUX.24.DELAY	BITSLICE5.TX_D2
CELL6.IMUX.IMUX.25.DELAY	BITSLICE5.TX_D3
CELL6.IMUX.IMUX.26.DELAY	BITSLICE5.TX_D4
CELL6.IMUX.IMUX.27.DELAY	BITSLICE5.TX_D5
CELL6.IMUX.IMUX.28.DELAY	BITSLICE5.TX_D6
CELL6.IMUX.IMUX.29.DELAY	BITSLICE5.TX_D7
CELL6.IMUX.IMUX.30.DELAY	BITSLICE5.TX_CNTVALUEIN0
CELL6.IMUX.IMUX.31.DELAY	BITSLICE5.TX_CNTVALUEIN2
CELL6.IMUX.IMUX.32.DELAY	BITSLICE5.TX_CNTVALUEIN4
CELL6.IMUX.IMUX.33.DELAY	BITSLICE5.TX_CNTVALUEIN5
CELL6.IMUX.IMUX.34.DELAY	BITSLICE5.TX_CNTVALUEIN6
CELL6.IMUX.IMUX.35.DELAY	BITSLICE5.TX_CNTVALUEIN8
CELL6.IMUX.IMUX.36.DELAY	BITSLICE5.RX_CNTVALUEIN0
CELL6.IMUX.IMUX.37.DELAY	BITSLICE5.RX_CNTVALUEIN1
CELL6.IMUX.IMUX.38.DELAY	BITSLICE5.RX_CNTVALUEIN2
CELL6.IMUX.IMUX.39.DELAY	BITSLICE5.RX_CNTVALUEIN4
CELL6.IMUX.IMUX.40.DELAY	BITSLICE5.RX_CNTVALUEIN6
CELL6.IMUX.IMUX.41.DELAY	BITSLICE5.RX_CNTVALUEIN7
CELL6.IMUX.IMUX.42.DELAY	BITSLICE5.RX_CNTVALUEIN8
CELL6.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA0, BITSLICE_CONTROL1.CLB2RIU_WR_DATA0
CELL6.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA2, BITSLICE_CONTROL1.CLB2RIU_WR_DATA2
CELL6.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA3, BITSLICE_CONTROL1.CLB2RIU_WR_DATA3
CELL6.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA4, BITSLICE_CONTROL1.CLB2RIU_WR_DATA4
CELL6.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA6, BITSLICE_CONTROL1.CLB2RIU_WR_DATA6
CELL7.OUT.0.TMIN	PLL0.TESTOUT4
CELL7.OUT.1.TMIN	PLL0.TESTOUT5
CELL7.OUT.2.TMIN	PLL0.TESTOUT6
CELL7.OUT.3.TMIN	PLL0.TESTOUT7
CELL7.OUT.4.TMIN	RIU_OR0.RIU_RD_DATA13
CELL7.OUT.5.TMIN	RIU_OR0.RIU_RD_DATA14
CELL7.OUT.6.TMIN	RIU_OR0.RIU_RD_DATA15
CELL7.OUT.7.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT0
CELL7.OUT.8.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT1
CELL7.OUT.9.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT2
CELL7.OUT.10.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT3
CELL7.OUT.11.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT4
CELL7.OUT.12.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT5
CELL7.OUT.13.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT6
CELL7.OUT.14.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_SCAN_OUT7
CELL7.OUT.15.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_OUT
CELL7.OUT.16.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_FLG_OUT
CELL7.OUT.17.TMIN	XIPHY_FEEDTHROUGH0.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
CELL7.OUT.18.TMIN	BITSLICE12.PHY2CLB_FIFO_EMPTY
CELL7.OUT.19.TMIN	BITSLICE12.RX_Q0
CELL7.OUT.20.TMIN	BITSLICE12.RX_Q1
CELL7.OUT.21.TMIN	BITSLICE12.RX_Q2
CELL7.OUT.22.TMIN	BITSLICE12.RX_Q3
CELL7.OUT.23.TMIN	BITSLICE12.RX_Q4
CELL7.OUT.24.TMIN	BITSLICE12.RX_Q5
CELL7.OUT.25.TMIN	BITSLICE12.RX_Q6
CELL7.OUT.26.TMIN	BITSLICE12.RX_Q7
CELL7.OUT.27.TMIN	BITSLICE12.TX_CNTVALUEOUT0
CELL7.OUT.28.TMIN	BITSLICE12.TX_CNTVALUEOUT1
CELL7.OUT.29.TMIN	BITSLICE12.TX_CNTVALUEOUT2
CELL7.OUT.30.TMIN	BITSLICE12.TX_CNTVALUEOUT3
CELL7.OUT.31.TMIN	BITSLICE12.TX_CNTVALUEOUT4
CELL7.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_SDR
CELL7.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_DIV4
CELL7.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_CLK_DIV2
CELL7.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.TXBIT_RST_B12
CELL7.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.RXBIT_RST_B12
CELL7.IMUX.BYP.0	PLL0.TESTIN0
CELL7.IMUX.BYP.1	PLL0.TESTIN1
CELL7.IMUX.BYP.2	PLL0.TESTIN2
CELL7.IMUX.BYP.3	PLL0.TESTIN3
CELL7.IMUX.BYP.6	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN1
CELL7.IMUX.BYP.7	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN2
CELL7.IMUX.BYP.8	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN3
CELL7.IMUX.BYP.10	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN4
CELL7.IMUX.BYP.11	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN5
CELL7.IMUX.BYP.12	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN6
CELL7.IMUX.BYP.13	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_IN7
CELL7.IMUX.BYP.14	XIPHY_FEEDTHROUGH0.CLB2PHY_SCAN_EN_B
CELL7.IMUX.BYP.15	BITSLICE12.TX_LD
CELL7.IMUX.IMUX.0.DELAY	PLL0.SCANENB
CELL7.IMUX.IMUX.6.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_DIV4_CLK_SEL_B
CELL7.IMUX.IMUX.7.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CT_START_EN
CELL7.IMUX.IMUX.8.DELAY	BITSLICE12.TX_CE_OFD
CELL7.IMUX.IMUX.9.DELAY	BITSLICE12.RX_DATAIN1
CELL7.IMUX.IMUX.10.DELAY	BITSLICE12.TX_D2
CELL7.IMUX.IMUX.11.DELAY	BITSLICE12.TX_D4
CELL7.IMUX.IMUX.12.DELAY	BITSLICE12.TX_CNTVALUEIN0
CELL7.IMUX.IMUX.13.DELAY	BITSLICE12.TX_CNTVALUEIN2
CELL7.IMUX.IMUX.14.DELAY	BITSLICE12.TX_CNTVALUEIN6
CELL7.IMUX.IMUX.15.DELAY	BITSLICE12.TX_CNTVALUEIN8
CELL7.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA8, BITSLICE_CONTROL1.CLB2RIU_WR_DATA8
CELL7.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA9, BITSLICE_CONTROL1.CLB2RIU_WR_DATA9
CELL7.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA10, BITSLICE_CONTROL1.CLB2RIU_WR_DATA10
CELL7.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA11, BITSLICE_CONTROL1.CLB2RIU_WR_DATA11
CELL7.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA12, BITSLICE_CONTROL1.CLB2RIU_WR_DATA12
CELL7.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA13, BITSLICE_CONTROL1.CLB2RIU_WR_DATA13
CELL7.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA14, BITSLICE_CONTROL1.CLB2RIU_WR_DATA14
CELL7.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL0.CLB2RIU_WR_DATA15, BITSLICE_CONTROL1.CLB2RIU_WR_DATA15
CELL7.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR0, BITSLICE_CONTROL1.CLB2RIU_ADDR0
CELL7.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR1, BITSLICE_CONTROL1.CLB2RIU_ADDR1
CELL7.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR2, BITSLICE_CONTROL1.CLB2RIU_ADDR2
CELL7.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR3, BITSLICE_CONTROL1.CLB2RIU_ADDR3
CELL7.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR4, BITSLICE_CONTROL1.CLB2RIU_ADDR4
CELL7.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL0.CLB2RIU_ADDR5, BITSLICE_CONTROL1.CLB2RIU_ADDR5
CELL7.IMUX.IMUX.30.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_SDR_CLK_SEL_B
CELL7.IMUX.IMUX.31.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_TEST_DIV2_CLK_SEL_B
CELL7.IMUX.IMUX.32.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CLK_STOP_FLG_OUT
CELL7.IMUX.IMUX.33.DELAY	XIPHY_FEEDTHROUGH0.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
CELL7.IMUX.IMUX.34.DELAY	BITSLICE12.TX_T
CELL7.IMUX.IMUX.35.DELAY	BITSLICE12.RX_CE_IFD
CELL7.IMUX.IMUX.36.DELAY	BITSLICE12.CLB2PHY_FIFO_RDEN
CELL7.IMUX.IMUX.37.DELAY	BITSLICE12.TX_D0
CELL7.IMUX.IMUX.38.DELAY	BITSLICE12.TX_D1
CELL7.IMUX.IMUX.39.DELAY	BITSLICE12.TX_D3
CELL7.IMUX.IMUX.40.DELAY	BITSLICE12.TX_D5
CELL7.IMUX.IMUX.41.DELAY	BITSLICE12.TX_D6
CELL7.IMUX.IMUX.42.DELAY	BITSLICE12.TX_D7
CELL7.IMUX.IMUX.43.DELAY	BITSLICE12.TX_CNTVALUEIN1
CELL7.IMUX.IMUX.44.DELAY	BITSLICE12.TX_CNTVALUEIN3
CELL7.IMUX.IMUX.45.DELAY	BITSLICE12.TX_CNTVALUEIN4
CELL7.IMUX.IMUX.46.DELAY	BITSLICE12.TX_CNTVALUEIN5
CELL7.IMUX.IMUX.47.DELAY	BITSLICE12.TX_CNTVALUEIN7
CELL8.OUT.0.TMIN	PLL0.TESTOUT0
CELL8.OUT.1.TMIN	PLL0.TESTOUT1
CELL8.OUT.2.TMIN	PLL0.TESTOUT2
CELL8.OUT.3.TMIN	PLL0.TESTOUT3
CELL8.OUT.4.TMIN	BITSLICE12.TX_CNTVALUEOUT5
CELL8.OUT.5.TMIN	BITSLICE12.TX_CNTVALUEOUT6
CELL8.OUT.6.TMIN	BITSLICE12.TX_CNTVALUEOUT7
CELL8.OUT.7.TMIN	BITSLICE12.TX_CNTVALUEOUT8
CELL8.OUT.8.TMIN	BITSLICE7.TX_T_OUT
CELL8.OUT.9.TMIN	BITSLICE12.RX_CNTVALUEOUT0
CELL8.OUT.10.TMIN	BITSLICE12.RX_CNTVALUEOUT1
CELL8.OUT.11.TMIN	BITSLICE12.RX_CNTVALUEOUT2
CELL8.OUT.12.TMIN	BITSLICE12.RX_CNTVALUEOUT3
CELL8.OUT.13.TMIN	BITSLICE12.RX_CNTVALUEOUT4
CELL8.OUT.14.TMIN	BITSLICE12.RX_CNTVALUEOUT5
CELL8.OUT.15.TMIN	BITSLICE12.RX_CNTVALUEOUT6
CELL8.OUT.16.TMIN	BITSLICE12.RX_CNTVALUEOUT7
CELL8.OUT.17.TMIN	BITSLICE12.RX_CNTVALUEOUT8
CELL8.OUT.18.TMIN	BITSLICE6.PHY2CLB_FIFO_EMPTY
CELL8.OUT.19.TMIN	BITSLICE6.RX_Q0
CELL8.OUT.20.TMIN	BITSLICE6.RX_Q1
CELL8.OUT.21.TMIN	BITSLICE6.RX_Q2
CELL8.OUT.22.TMIN	BITSLICE6.RX_Q3
CELL8.OUT.23.TMIN	BITSLICE6.RX_Q4
CELL8.OUT.24.TMIN	BITSLICE6.RX_Q5
CELL8.OUT.25.TMIN	BITSLICE6.RX_Q6
CELL8.OUT.26.TMIN	BITSLICE6.RX_Q7
CELL8.OUT.27.TMIN	BITSLICE6.TX_CNTVALUEOUT0
CELL8.OUT.28.TMIN	BITSLICE6.TX_CNTVALUEOUT1
CELL8.OUT.29.TMIN	BITSLICE6.TX_CNTVALUEOUT2
CELL8.OUT.30.TMIN	BITSLICE6.TX_CNTVALUEOUT3
CELL8.OUT.31.TMIN	BITSLICE6.TX_CNTVALUEOUT4
CELL8.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.ODELAY_RST_B12
CELL8.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.IDELAY_RST_B12
CELL8.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK12
CELL8.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.TXBIT_RST_B6
CELL8.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.RXBIT_RST_B6
CELL8.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.ODELAY_RST_B6
CELL8.IMUX.BYP.0	PLL0.DADDR4
CELL8.IMUX.BYP.1	PLL0.DADDR5
CELL8.IMUX.BYP.2	PLL0.DADDR6
CELL8.IMUX.BYP.6	BITSLICE12.TX_INC
CELL8.IMUX.BYP.7	BITSLICE12.TX_EN_VTC
CELL8.IMUX.BYP.8	BITSLICE12.TX_CE_ODELAY
CELL8.IMUX.BYP.9	BITSLICE12.RX_LD
CELL8.IMUX.BYP.10	BITSLICE12.RX_INC
CELL8.IMUX.BYP.11	BITSLICE12.RX_EN_VTC
CELL8.IMUX.BYP.12	BITSLICE12.RX_CE_IDELAY
CELL8.IMUX.BYP.13	BITSLICE12.DYN_DCI_OUT_INT
CELL8.IMUX.BYP.14	BITSLICE6.TX_LD
CELL8.IMUX.BYP.15	BITSLICE6.TX_INC
CELL8.IMUX.IMUX.0.DELAY	PLL0.SCANIN
CELL8.IMUX.IMUX.6.DELAY	BITSLICE6.TX_D0
CELL8.IMUX.IMUX.7.DELAY	BITSLICE6.TX_D2
CELL8.IMUX.IMUX.8.DELAY	BITSLICE6.TX_D6
CELL8.IMUX.IMUX.9.DELAY	BITSLICE6.TX_CNTVALUEIN0
CELL8.IMUX.IMUX.10.DELAY	BITSLICE6.TX_CNTVALUEIN4
CELL8.IMUX.IMUX.11.DELAY	BITSLICE6.TX_CNTVALUEIN6
CELL8.IMUX.IMUX.12.DELAY	BITSLICE6.RX_CNTVALUEIN1
CELL8.IMUX.IMUX.13.DELAY	BITSLICE6.RX_CNTVALUEIN3
CELL8.IMUX.IMUX.14.DELAY	BITSLICE6.RX_CNTVALUEIN7
CELL8.IMUX.IMUX.15.DELAY	BITSLICE7.TX_T
CELL8.IMUX.IMUX.16.DELAY	BITSLICE12.RX_CNTVALUEIN0
CELL8.IMUX.IMUX.17.DELAY	BITSLICE12.RX_CNTVALUEIN1
CELL8.IMUX.IMUX.18.DELAY	BITSLICE12.RX_CNTVALUEIN2
CELL8.IMUX.IMUX.19.DELAY	BITSLICE12.RX_CNTVALUEIN3
CELL8.IMUX.IMUX.20.DELAY	BITSLICE12.RX_CNTVALUEIN4
CELL8.IMUX.IMUX.21.DELAY	BITSLICE12.RX_CNTVALUEIN5
CELL8.IMUX.IMUX.22.DELAY	BITSLICE12.RX_CNTVALUEIN6
CELL8.IMUX.IMUX.23.DELAY	BITSLICE12.RX_CNTVALUEIN7
CELL8.IMUX.IMUX.24.DELAY	BITSLICE12.RX_CNTVALUEIN8
CELL8.IMUX.IMUX.25.DELAY	BITSLICE6.TX_T
CELL8.IMUX.IMUX.26.DELAY	BITSLICE6.TX_CE_OFD
CELL8.IMUX.IMUX.27.DELAY	BITSLICE6.RX_CE_IFD
CELL8.IMUX.IMUX.29.DELAY	BITSLICE6.RX_DATAIN1
CELL8.IMUX.IMUX.30.DELAY	BITSLICE6.CLB2PHY_FIFO_RDEN
CELL8.IMUX.IMUX.31.DELAY	BITSLICE6.TX_D1
CELL8.IMUX.IMUX.32.DELAY	BITSLICE6.TX_D3
CELL8.IMUX.IMUX.33.DELAY	BITSLICE6.TX_D4
CELL8.IMUX.IMUX.34.DELAY	BITSLICE6.TX_D5
CELL8.IMUX.IMUX.35.DELAY	BITSLICE6.TX_D7
CELL8.IMUX.IMUX.36.DELAY	BITSLICE6.TX_CNTVALUEIN1
CELL8.IMUX.IMUX.37.DELAY	BITSLICE6.TX_CNTVALUEIN2
CELL8.IMUX.IMUX.38.DELAY	BITSLICE6.TX_CNTVALUEIN3
CELL8.IMUX.IMUX.39.DELAY	BITSLICE6.TX_CNTVALUEIN5
CELL8.IMUX.IMUX.40.DELAY	BITSLICE6.TX_CNTVALUEIN7
CELL8.IMUX.IMUX.41.DELAY	BITSLICE6.TX_CNTVALUEIN8
CELL8.IMUX.IMUX.42.DELAY	BITSLICE6.RX_CNTVALUEIN0
CELL8.IMUX.IMUX.43.DELAY	BITSLICE6.RX_CNTVALUEIN2
CELL8.IMUX.IMUX.44.DELAY	BITSLICE6.RX_CNTVALUEIN4
CELL8.IMUX.IMUX.45.DELAY	BITSLICE6.RX_CNTVALUEIN5
CELL8.IMUX.IMUX.46.DELAY	BITSLICE6.RX_CNTVALUEIN6
CELL8.IMUX.IMUX.47.DELAY	BITSLICE6.RX_CNTVALUEIN8
CELL9.OUT.0.TMIN	PLL0.DOUT12
CELL9.OUT.1.TMIN	PLL0.DOUT13
CELL9.OUT.2.TMIN	PLL0.DOUT14
CELL9.OUT.3.TMIN	PLL0.DOUT15
CELL9.OUT.4.TMIN	BITSLICE6.TX_CNTVALUEOUT5
CELL9.OUT.5.TMIN	BITSLICE6.TX_CNTVALUEOUT6
CELL9.OUT.6.TMIN	BITSLICE6.TX_CNTVALUEOUT7
CELL9.OUT.7.TMIN	BITSLICE6.TX_CNTVALUEOUT8
CELL9.OUT.8.TMIN	BITSLICE8.TX_T_OUT
CELL9.OUT.9.TMIN	BITSLICE6.RX_CNTVALUEOUT0
CELL9.OUT.10.TMIN	BITSLICE6.RX_CNTVALUEOUT1
CELL9.OUT.11.TMIN	BITSLICE6.RX_CNTVALUEOUT2
CELL9.OUT.12.TMIN	BITSLICE6.RX_CNTVALUEOUT3
CELL9.OUT.13.TMIN	BITSLICE6.RX_CNTVALUEOUT4
CELL9.OUT.14.TMIN	BITSLICE6.RX_CNTVALUEOUT5
CELL9.OUT.15.TMIN	BITSLICE6.RX_CNTVALUEOUT6
CELL9.OUT.16.TMIN	BITSLICE6.RX_CNTVALUEOUT7
CELL9.OUT.17.TMIN	BITSLICE6.RX_CNTVALUEOUT8
CELL9.OUT.18.TMIN	BITSLICE7.PHY2CLB_FIFO_EMPTY
CELL9.OUT.19.TMIN	BITSLICE7.RX_Q0
CELL9.OUT.20.TMIN	BITSLICE7.RX_Q1
CELL9.OUT.21.TMIN	BITSLICE7.RX_Q2
CELL9.OUT.22.TMIN	BITSLICE7.RX_Q3
CELL9.OUT.23.TMIN	BITSLICE7.RX_Q4
CELL9.OUT.24.TMIN	BITSLICE7.RX_Q5
CELL9.OUT.25.TMIN	BITSLICE7.RX_Q6
CELL9.OUT.26.TMIN	BITSLICE7.RX_Q7
CELL9.OUT.27.TMIN	BITSLICE7.TX_CNTVALUEOUT0
CELL9.OUT.28.TMIN	BITSLICE7.TX_CNTVALUEOUT1
CELL9.OUT.29.TMIN	BITSLICE7.TX_CNTVALUEOUT2
CELL9.OUT.30.TMIN	BITSLICE7.TX_CNTVALUEOUT3
CELL9.OUT.31.TMIN	BITSLICE7.TX_CNTVALUEOUT4
CELL9.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.IDELAY_RST_B6
CELL9.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK6
CELL9.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.TXBIT_RST_B7
CELL9.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.RXBIT_RST_B7
CELL9.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.ODELAY_RST_B7
CELL9.IMUX.BYP.0	PLL0.DADDR0
CELL9.IMUX.BYP.1	PLL0.DADDR1
CELL9.IMUX.BYP.2	PLL0.DADDR2
CELL9.IMUX.BYP.3	PLL0.DADDR3
CELL9.IMUX.BYP.6	BITSLICE6.TX_EN_VTC
CELL9.IMUX.BYP.7	BITSLICE6.TX_CE_ODELAY
CELL9.IMUX.BYP.8	BITSLICE6.RX_LD
CELL9.IMUX.BYP.9	BITSLICE6.RX_INC
CELL9.IMUX.BYP.10	BITSLICE6.RX_EN_VTC
CELL9.IMUX.BYP.11	BITSLICE6.RX_CE_IDELAY
CELL9.IMUX.BYP.12	BITSLICE6.DYN_DCI_OUT_INT
CELL9.IMUX.BYP.14	BITSLICE7.TX_LD
CELL9.IMUX.BYP.15	BITSLICE7.TX_INC
CELL9.IMUX.IMUX.6.DELAY	BITSLICE7.TX_CNTVALUEIN3
CELL9.IMUX.IMUX.7.DELAY	BITSLICE7.TX_CNTVALUEIN5
CELL9.IMUX.IMUX.8.DELAY	BITSLICE7.RX_CNTVALUEIN0
CELL9.IMUX.IMUX.9.DELAY	BITSLICE7.RX_CNTVALUEIN2
CELL9.IMUX.IMUX.10.DELAY	BITSLICE7.RX_CNTVALUEIN6
CELL9.IMUX.IMUX.11.DELAY	BITSLICE7.RX_CNTVALUEIN8
CELL9.IMUX.IMUX.12.DELAY	BITSLICE8.RX_DATAIN1
CELL9.IMUX.IMUX.13.DELAY	BITSLICE8.TX_D0
CELL9.IMUX.IMUX.14.DELAY	BITSLICE8.TX_D4
CELL9.IMUX.IMUX.15.DELAY	BITSLICE8.TX_D6
CELL9.IMUX.IMUX.16.DELAY	BITSLICE7.TX_CE_OFD
CELL9.IMUX.IMUX.17.DELAY	BITSLICE7.RX_CE_IFD
CELL9.IMUX.IMUX.18.DELAY	BITSLICE7.RX_DATAIN1
CELL9.IMUX.IMUX.19.DELAY	BITSLICE7.CLB2PHY_FIFO_RDEN
CELL9.IMUX.IMUX.20.DELAY	BITSLICE7.TX_D0
CELL9.IMUX.IMUX.21.DELAY	BITSLICE7.TX_D1
CELL9.IMUX.IMUX.22.DELAY	BITSLICE7.TX_D2
CELL9.IMUX.IMUX.23.DELAY	BITSLICE7.TX_D3
CELL9.IMUX.IMUX.24.DELAY	BITSLICE7.TX_D4
CELL9.IMUX.IMUX.25.DELAY	BITSLICE7.TX_D5
CELL9.IMUX.IMUX.26.DELAY	BITSLICE7.TX_D6
CELL9.IMUX.IMUX.27.DELAY	BITSLICE7.TX_D7
CELL9.IMUX.IMUX.28.DELAY	BITSLICE7.TX_CNTVALUEIN0
CELL9.IMUX.IMUX.29.DELAY	BITSLICE7.TX_CNTVALUEIN1
CELL9.IMUX.IMUX.30.DELAY	BITSLICE7.TX_CNTVALUEIN2
CELL9.IMUX.IMUX.31.DELAY	BITSLICE7.TX_CNTVALUEIN4
CELL9.IMUX.IMUX.32.DELAY	BITSLICE7.TX_CNTVALUEIN6
CELL9.IMUX.IMUX.33.DELAY	BITSLICE7.TX_CNTVALUEIN7
CELL9.IMUX.IMUX.34.DELAY	BITSLICE7.TX_CNTVALUEIN8
CELL9.IMUX.IMUX.35.DELAY	BITSLICE7.RX_CNTVALUEIN1
CELL9.IMUX.IMUX.36.DELAY	BITSLICE7.RX_CNTVALUEIN3
CELL9.IMUX.IMUX.37.DELAY	BITSLICE7.RX_CNTVALUEIN4
CELL9.IMUX.IMUX.38.DELAY	BITSLICE7.RX_CNTVALUEIN5
CELL9.IMUX.IMUX.39.DELAY	BITSLICE7.RX_CNTVALUEIN7
CELL9.IMUX.IMUX.40.DELAY	BITSLICE8.TX_T
CELL9.IMUX.IMUX.41.DELAY	BITSLICE8.TX_CE_OFD
CELL9.IMUX.IMUX.42.DELAY	BITSLICE8.RX_CE_IFD
CELL9.IMUX.IMUX.43.DELAY	BITSLICE8.CLB2PHY_FIFO_RDEN
CELL9.IMUX.IMUX.44.DELAY	BITSLICE8.TX_D1
CELL9.IMUX.IMUX.45.DELAY	BITSLICE8.TX_D2
CELL9.IMUX.IMUX.46.DELAY	BITSLICE8.TX_D3
CELL9.IMUX.IMUX.47.DELAY	BITSLICE8.TX_D5
CELL10.OUT.0.TMIN	PLL0.DOUT8
CELL10.OUT.1.TMIN	PLL0.DOUT9
CELL10.OUT.2.TMIN	PLL0.DOUT10
CELL10.OUT.3.TMIN	PLL0.DOUT11
CELL10.OUT.4.TMIN	BITSLICE7.TX_CNTVALUEOUT5
CELL10.OUT.5.TMIN	BITSLICE7.TX_CNTVALUEOUT6
CELL10.OUT.6.TMIN	BITSLICE7.TX_CNTVALUEOUT7
CELL10.OUT.7.TMIN	BITSLICE7.TX_CNTVALUEOUT8
CELL10.OUT.8.TMIN	BITSLICE9.TX_T_OUT
CELL10.OUT.9.TMIN	BITSLICE7.RX_CNTVALUEOUT0
CELL10.OUT.10.TMIN	BITSLICE7.RX_CNTVALUEOUT1
CELL10.OUT.11.TMIN	BITSLICE7.RX_CNTVALUEOUT2
CELL10.OUT.12.TMIN	BITSLICE7.RX_CNTVALUEOUT3
CELL10.OUT.13.TMIN	BITSLICE7.RX_CNTVALUEOUT4
CELL10.OUT.14.TMIN	BITSLICE7.RX_CNTVALUEOUT5
CELL10.OUT.15.TMIN	BITSLICE7.RX_CNTVALUEOUT6
CELL10.OUT.16.TMIN	BITSLICE7.RX_CNTVALUEOUT7
CELL10.OUT.17.TMIN	BITSLICE7.RX_CNTVALUEOUT8
CELL10.OUT.18.TMIN	BITSLICE8.PHY2CLB_FIFO_EMPTY
CELL10.OUT.19.TMIN	BITSLICE8.RX_Q0
CELL10.OUT.20.TMIN	BITSLICE8.RX_Q1
CELL10.OUT.21.TMIN	BITSLICE8.RX_Q2
CELL10.OUT.22.TMIN	BITSLICE8.RX_Q3
CELL10.OUT.23.TMIN	BITSLICE8.RX_Q4
CELL10.OUT.24.TMIN	BITSLICE8.RX_Q5
CELL10.OUT.25.TMIN	BITSLICE8.RX_Q6
CELL10.OUT.26.TMIN	BITSLICE8.RX_Q7
CELL10.OUT.27.TMIN	BITSLICE8.TX_CNTVALUEOUT0
CELL10.OUT.28.TMIN	BITSLICE8.TX_CNTVALUEOUT1
CELL10.OUT.29.TMIN	BITSLICE8.TX_CNTVALUEOUT2
CELL10.OUT.30.TMIN	BITSLICE8.TX_CNTVALUEOUT3
CELL10.OUT.31.TMIN	BITSLICE8.TX_CNTVALUEOUT4
CELL10.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.IDELAY_RST_B7
CELL10.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK7
CELL10.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.TXBIT_RST_B8
CELL10.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.RXBIT_RST_B8
CELL10.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.ODELAY_RST_B8
CELL10.IMUX.BYP.0	PLL0.DI12
CELL10.IMUX.BYP.1	PLL0.DI13
CELL10.IMUX.BYP.2	PLL0.DI14
CELL10.IMUX.BYP.3	PLL0.DI15
CELL10.IMUX.BYP.6	BITSLICE7.TX_EN_VTC
CELL10.IMUX.BYP.7	BITSLICE7.TX_CE_ODELAY
CELL10.IMUX.BYP.8	BITSLICE7.RX_LD
CELL10.IMUX.BYP.9	BITSLICE7.RX_INC
CELL10.IMUX.BYP.10	BITSLICE7.RX_EN_VTC
CELL10.IMUX.BYP.11	BITSLICE7.RX_CE_IDELAY
CELL10.IMUX.BYP.12	BITSLICE7.DYN_DCI_OUT_INT
CELL10.IMUX.BYP.13	BITSLICE8.TX_LD
CELL10.IMUX.BYP.14	BITSLICE8.TX_INC
CELL10.IMUX.BYP.15	BITSLICE8.TX_EN_VTC
CELL10.IMUX.IMUX.0.DELAY	PLL0.DWE
CELL10.IMUX.IMUX.6.DELAY	BITSLICE8.RX_CNTVALUEIN4
CELL10.IMUX.IMUX.7.DELAY	BITSLICE8.RX_CNTVALUEIN6
CELL10.IMUX.IMUX.8.DELAY	BITSLICE_T1.CNTVALUEIN1
CELL10.IMUX.IMUX.9.DELAY	BITSLICE_T1.CNTVALUEIN3
CELL10.IMUX.IMUX.10.DELAY	BITSLICE_T1.CNTVALUEIN7
CELL10.IMUX.IMUX.11.DELAY	BITSLICE_CONTROL1.CLB2RIU_NIBBLE_SEL
CELL10.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS1_3
CELL10.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS0_1
CELL10.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL1.CLB2PHY_T_B1
CELL10.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL1.CLB2PHY_T_B3
CELL10.IMUX.IMUX.16.DELAY	BITSLICE8.TX_D7
CELL10.IMUX.IMUX.18.DELAY	BITSLICE8.TX_CNTVALUEIN0
CELL10.IMUX.IMUX.19.DELAY	BITSLICE8.TX_CNTVALUEIN1
CELL10.IMUX.IMUX.20.DELAY	BITSLICE8.TX_CNTVALUEIN2
CELL10.IMUX.IMUX.21.DELAY	BITSLICE8.TX_CNTVALUEIN3
CELL10.IMUX.IMUX.22.DELAY	BITSLICE8.TX_CNTVALUEIN4
CELL10.IMUX.IMUX.23.DELAY	BITSLICE8.TX_CNTVALUEIN5
CELL10.IMUX.IMUX.24.DELAY	BITSLICE8.TX_CNTVALUEIN6
CELL10.IMUX.IMUX.25.DELAY	BITSLICE8.TX_CNTVALUEIN7
CELL10.IMUX.IMUX.26.DELAY	BITSLICE8.TX_CNTVALUEIN8
CELL10.IMUX.IMUX.27.DELAY	BITSLICE8.RX_CNTVALUEIN0
CELL10.IMUX.IMUX.28.DELAY	BITSLICE8.RX_CNTVALUEIN1
CELL10.IMUX.IMUX.29.DELAY	BITSLICE8.RX_CNTVALUEIN2
CELL10.IMUX.IMUX.30.DELAY	BITSLICE8.RX_CNTVALUEIN3
CELL10.IMUX.IMUX.31.DELAY	BITSLICE8.RX_CNTVALUEIN5
CELL10.IMUX.IMUX.32.DELAY	BITSLICE8.RX_CNTVALUEIN7
CELL10.IMUX.IMUX.33.DELAY	BITSLICE8.RX_CNTVALUEIN8
CELL10.IMUX.IMUX.34.DELAY	BITSLICE_T1.CNTVALUEIN0
CELL10.IMUX.IMUX.35.DELAY	BITSLICE_T1.CNTVALUEIN2
CELL10.IMUX.IMUX.36.DELAY	BITSLICE_T1.CNTVALUEIN4
CELL10.IMUX.IMUX.37.DELAY	BITSLICE_T1.CNTVALUEIN5
CELL10.IMUX.IMUX.38.DELAY	BITSLICE_T1.CNTVALUEIN6
CELL10.IMUX.IMUX.39.DELAY	BITSLICE_T1.CNTVALUEIN8
CELL10.IMUX.IMUX.40.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS1_0
CELL10.IMUX.IMUX.41.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS1_1
CELL10.IMUX.IMUX.42.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS1_2
CELL10.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS0_0
CELL10.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS0_2
CELL10.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL1.CLB2PHY_WRCS0_3
CELL10.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL1.CLB2PHY_T_B0
CELL10.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL1.CLB2PHY_T_B2
CELL11.OUT.0.TMIN	PLL0.DOUT4
CELL11.OUT.1.TMIN	PLL0.DOUT5
CELL11.OUT.2.TMIN	PLL0.DOUT6
CELL11.OUT.3.TMIN	PLL0.DOUT7
CELL11.OUT.4.TMIN	BITSLICE8.TX_CNTVALUEOUT5
CELL11.OUT.5.TMIN	BITSLICE8.TX_CNTVALUEOUT6
CELL11.OUT.6.TMIN	BITSLICE8.TX_CNTVALUEOUT7
CELL11.OUT.7.TMIN	BITSLICE8.TX_CNTVALUEOUT8
CELL11.OUT.8.TMIN	BITSLICE10.TX_T_OUT
CELL11.OUT.9.TMIN	BITSLICE8.RX_CNTVALUEOUT0
CELL11.OUT.10.TMIN	BITSLICE8.RX_CNTVALUEOUT1
CELL11.OUT.11.TMIN	BITSLICE8.RX_CNTVALUEOUT2
CELL11.OUT.12.TMIN	BITSLICE8.RX_CNTVALUEOUT3
CELL11.OUT.13.TMIN	BITSLICE8.RX_CNTVALUEOUT4
CELL11.OUT.14.TMIN	BITSLICE8.RX_CNTVALUEOUT5
CELL11.OUT.15.TMIN	BITSLICE8.RX_CNTVALUEOUT6
CELL11.OUT.16.TMIN	BITSLICE8.RX_CNTVALUEOUT7
CELL11.OUT.17.TMIN	BITSLICE8.RX_CNTVALUEOUT8
CELL11.OUT.18.TMIN	BITSLICE_T1.CNTVALUEOUT0
CELL11.OUT.19.TMIN	BITSLICE_T1.CNTVALUEOUT1
CELL11.OUT.20.TMIN	BITSLICE_T1.CNTVALUEOUT2
CELL11.OUT.21.TMIN	BITSLICE_T1.CNTVALUEOUT3
CELL11.OUT.22.TMIN	BITSLICE_T1.CNTVALUEOUT4
CELL11.OUT.23.TMIN	BITSLICE_T1.CNTVALUEOUT5
CELL11.OUT.24.TMIN	BITSLICE_T1.CNTVALUEOUT6
CELL11.OUT.25.TMIN	BITSLICE_T1.CNTVALUEOUT7
CELL11.OUT.26.TMIN	BITSLICE_T1.CNTVALUEOUT8
CELL11.OUT.27.TMIN	BITSLICE_CONTROL1.PHY2CLB_PHY_RDY
CELL11.OUT.28.TMIN	BITSLICE_CONTROL1.MASTER_PD_OUT
CELL11.OUT.29.TMIN	BITSLICE_CONTROL1.PHY2CLB_FIXDLY_RDY
CELL11.OUT.30.TMIN	BITSLICE_CONTROL1.CTRL_DLY_TEST_OUT
CELL11.OUT.31.TMIN	BITSLICE11.TX_T_OUT
CELL11.IMUX.CTRL.0	PLL0.DCLK_B
CELL11.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.IDELAY_RST_B8
CELL11.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK8
CELL11.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.TRISTATE_ODELAY_RST_B1
CELL11.IMUX.CTRL.6	BITSLICE_CONTROL1.REFCLK
CELL11.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.CTRL_RST_B_UPP
CELL11.IMUX.BYP.0	PLL0.DI8
CELL11.IMUX.BYP.1	PLL0.DI9
CELL11.IMUX.BYP.2	PLL0.DI10
CELL11.IMUX.BYP.3	PLL0.DI11
CELL11.IMUX.BYP.6	BITSLICE8.TX_CE_ODELAY
CELL11.IMUX.BYP.8	BITSLICE8.RX_LD
CELL11.IMUX.BYP.9	BITSLICE8.RX_INC
CELL11.IMUX.BYP.10	BITSLICE8.RX_EN_VTC
CELL11.IMUX.BYP.11	BITSLICE8.RX_CE_IDELAY
CELL11.IMUX.BYP.12	BITSLICE8.DYN_DCI_OUT_INT
CELL11.IMUX.BYP.13	BITSLICE_T1.CE_OFD
CELL11.IMUX.BYP.14	BITSLICE_T1.LD
CELL11.IMUX.BYP.15	BITSLICE_T1.INC
CELL11.IMUX.IMUX.0.DELAY	PLL0.DEN
CELL11.IMUX.IMUX.6.DELAY	BITSLICE9.RX_DATAIN1
CELL11.IMUX.IMUX.7.DELAY	BITSLICE9.TX_D0
CELL11.IMUX.IMUX.8.DELAY	BITSLICE9.TX_D4
CELL11.IMUX.IMUX.9.DELAY	BITSLICE9.TX_D6
CELL11.IMUX.IMUX.10.DELAY	BITSLICE9.TX_CNTVALUEIN2
CELL11.IMUX.IMUX.11.DELAY	BITSLICE9.TX_CNTVALUEIN4
CELL11.IMUX.IMUX.12.DELAY	BITSLICE9.TX_CNTVALUEIN7
CELL11.IMUX.IMUX.13.DELAY	BITSLICE9.RX_CNTVALUEIN0
CELL11.IMUX.IMUX.14.DELAY	BITSLICE9.RX_CNTVALUEIN4
CELL11.IMUX.IMUX.15.DELAY	BITSLICE9.RX_CNTVALUEIN6
CELL11.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDEN0
CELL11.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDEN1
CELL11.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDEN2
CELL11.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDEN3
CELL11.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS1_0
CELL11.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS1_1
CELL11.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS1_2
CELL11.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS1_3
CELL11.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS0_0
CELL11.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS0_1
CELL11.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS0_2
CELL11.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL1.CLB2PHY_RDCS0_3
CELL11.IMUX.IMUX.28.DELAY	BITSLICE9.TX_T
CELL11.IMUX.IMUX.29.DELAY	BITSLICE9.TX_CE_OFD
CELL11.IMUX.IMUX.30.DELAY	BITSLICE9.RX_CE_IFD
CELL11.IMUX.IMUX.31.DELAY	BITSLICE9.CLB2PHY_FIFO_RDEN
CELL11.IMUX.IMUX.32.DELAY	BITSLICE9.TX_D1
CELL11.IMUX.IMUX.33.DELAY	BITSLICE9.TX_D2
CELL11.IMUX.IMUX.34.DELAY	BITSLICE9.TX_D3
CELL11.IMUX.IMUX.35.DELAY	BITSLICE9.TX_D5
CELL11.IMUX.IMUX.36.DELAY	BITSLICE9.TX_D7
CELL11.IMUX.IMUX.37.DELAY	BITSLICE9.TX_CNTVALUEIN0
CELL11.IMUX.IMUX.38.DELAY	BITSLICE9.TX_CNTVALUEIN1
CELL11.IMUX.IMUX.39.DELAY	BITSLICE9.TX_CNTVALUEIN3
CELL11.IMUX.IMUX.40.DELAY	BITSLICE9.TX_CNTVALUEIN5
CELL11.IMUX.IMUX.41.DELAY	BITSLICE9.TX_CNTVALUEIN6
CELL11.IMUX.IMUX.43.DELAY	BITSLICE9.TX_CNTVALUEIN8
CELL11.IMUX.IMUX.44.DELAY	BITSLICE9.RX_CNTVALUEIN1
CELL11.IMUX.IMUX.45.DELAY	BITSLICE9.RX_CNTVALUEIN2
CELL11.IMUX.IMUX.46.DELAY	BITSLICE9.RX_CNTVALUEIN3
CELL11.IMUX.IMUX.47.DELAY	BITSLICE9.RX_CNTVALUEIN5
CELL12.OUT.0.TMIN	PLL0.DOUT0
CELL12.OUT.1.TMIN	PLL0.DOUT1
CELL12.OUT.2.TMIN	PLL0.DOUT2
CELL12.OUT.3.TMIN	PLL0.DOUT3
CELL12.OUT.4.TMIN	BITSLICE9.PHY2CLB_FIFO_EMPTY
CELL12.OUT.5.TMIN	BITSLICE9.RX_Q0
CELL12.OUT.6.TMIN	BITSLICE9.RX_Q1
CELL12.OUT.7.TMIN	BITSLICE9.RX_Q2
CELL12.OUT.8.TMIN	BITSLICE9.RX_Q3
CELL12.OUT.9.TMIN	BITSLICE9.RX_Q4
CELL12.OUT.10.TMIN	BITSLICE9.RX_Q5
CELL12.OUT.11.TMIN	BITSLICE9.RX_Q6
CELL12.OUT.12.TMIN	BITSLICE9.RX_Q7
CELL12.OUT.13.TMIN	BITSLICE9.TX_CNTVALUEOUT0
CELL12.OUT.14.TMIN	BITSLICE9.TX_CNTVALUEOUT1
CELL12.OUT.15.TMIN	BITSLICE9.TX_CNTVALUEOUT2
CELL12.OUT.16.TMIN	BITSLICE9.TX_CNTVALUEOUT3
CELL12.OUT.17.TMIN	BITSLICE9.TX_CNTVALUEOUT4
CELL12.OUT.18.TMIN	BITSLICE9.TX_CNTVALUEOUT5
CELL12.OUT.19.TMIN	BITSLICE9.TX_CNTVALUEOUT6
CELL12.OUT.20.TMIN	BITSLICE9.TX_CNTVALUEOUT7
CELL12.OUT.21.TMIN	BITSLICE9.TX_CNTVALUEOUT8
CELL12.OUT.22.TMIN	BITSLICE12.TX_T_OUT
CELL12.OUT.23.TMIN	BITSLICE9.RX_CNTVALUEOUT0
CELL12.OUT.24.TMIN	BITSLICE9.RX_CNTVALUEOUT1
CELL12.OUT.25.TMIN	BITSLICE9.RX_CNTVALUEOUT2
CELL12.OUT.26.TMIN	BITSLICE9.RX_CNTVALUEOUT3
CELL12.OUT.27.TMIN	BITSLICE9.RX_CNTVALUEOUT4
CELL12.OUT.28.TMIN	BITSLICE9.RX_CNTVALUEOUT5
CELL12.OUT.29.TMIN	BITSLICE9.RX_CNTVALUEOUT6
CELL12.OUT.30.TMIN	BITSLICE9.RX_CNTVALUEOUT7
CELL12.OUT.31.TMIN	BITSLICE9.RX_CNTVALUEOUT8
CELL12.IMUX.CTRL.2	BITSLICE_CONTROL1.RIU_CLK, XIPHY_FEEDTHROUGH0.CLB2PHY_CTRL_CLK_UPP
CELL12.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.TXBIT_RST_B9
CELL12.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.RXBIT_RST_B9
CELL12.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.ODELAY_RST_B9
CELL12.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.IDELAY_RST_B9
CELL12.IMUX.BYP.0	PLL0.DI4
CELL12.IMUX.BYP.1	PLL0.DI5
CELL12.IMUX.BYP.2	PLL0.DI6
CELL12.IMUX.BYP.3	PLL0.DI7
CELL12.IMUX.BYP.6	BITSLICE_T1.CE_ODELAY
CELL12.IMUX.BYP.7	BITSLICE_CONTROL1.EN_VTC
CELL12.IMUX.BYP.8	BITSLICE_CONTROL1.CTRL_DLY_TEST_IN
CELL12.IMUX.BYP.9	BITSLICE9.TX_LD
CELL12.IMUX.BYP.10	BITSLICE9.TX_INC
CELL12.IMUX.BYP.11	BITSLICE9.TX_EN_VTC
CELL12.IMUX.BYP.12	BITSLICE9.TX_CE_ODELAY
CELL12.IMUX.BYP.13	BITSLICE9.RX_LD
CELL12.IMUX.BYP.14	BITSLICE9.RX_INC
CELL12.IMUX.BYP.15	BITSLICE9.RX_EN_VTC
CELL12.IMUX.IMUX.0.DELAY	PLL0.PWRDWN
CELL12.IMUX.IMUX.6.DELAY	BITSLICE10.TX_CNTVALUEIN0
CELL12.IMUX.IMUX.7.DELAY	BITSLICE10.TX_CNTVALUEIN2
CELL12.IMUX.IMUX.8.DELAY	BITSLICE10.TX_CNTVALUEIN6
CELL12.IMUX.IMUX.9.DELAY	BITSLICE10.TX_CNTVALUEIN8
CELL12.IMUX.IMUX.10.DELAY	BITSLICE10.RX_CNTVALUEIN3
CELL12.IMUX.IMUX.11.DELAY	BITSLICE10.RX_CNTVALUEIN5
CELL12.IMUX.IMUX.12.DELAY	BITSLICE11.TX_T
CELL12.IMUX.IMUX.13.DELAY	BITSLICE11.RX_CE_IFD
CELL12.IMUX.IMUX.14.DELAY	BITSLICE11.TX_D1
CELL12.IMUX.IMUX.15.DELAY	BITSLICE11.TX_D3
CELL12.IMUX.IMUX.16.DELAY	BITSLICE9.RX_CNTVALUEIN7
CELL12.IMUX.IMUX.17.DELAY	BITSLICE9.RX_CNTVALUEIN8
CELL12.IMUX.IMUX.18.DELAY	BITSLICE10.TX_T
CELL12.IMUX.IMUX.19.DELAY	BITSLICE10.TX_CE_OFD
CELL12.IMUX.IMUX.20.DELAY	BITSLICE10.RX_CE_IFD
CELL12.IMUX.IMUX.21.DELAY	BITSLICE10.RX_DATAIN1
CELL12.IMUX.IMUX.22.DELAY	BITSLICE10.CLB2PHY_FIFO_RDEN
CELL12.IMUX.IMUX.23.DELAY	BITSLICE10.TX_D5
CELL12.IMUX.IMUX.24.DELAY	BITSLICE10.TX_D4
CELL12.IMUX.IMUX.25.DELAY	BITSLICE10.TX_D3
CELL12.IMUX.IMUX.26.DELAY	BITSLICE10.TX_D2
CELL12.IMUX.IMUX.27.DELAY	BITSLICE10.TX_D1
CELL12.IMUX.IMUX.28.DELAY	BITSLICE10.TX_D0
CELL12.IMUX.IMUX.29.DELAY	BITSLICE10.TX_D6
CELL12.IMUX.IMUX.30.DELAY	BITSLICE10.TX_D7
CELL12.IMUX.IMUX.31.DELAY	BITSLICE10.TX_CNTVALUEIN1
CELL12.IMUX.IMUX.32.DELAY	BITSLICE10.TX_CNTVALUEIN3
CELL12.IMUX.IMUX.33.DELAY	BITSLICE10.TX_CNTVALUEIN4
CELL12.IMUX.IMUX.34.DELAY	BITSLICE10.TX_CNTVALUEIN5
CELL12.IMUX.IMUX.35.DELAY	BITSLICE10.TX_CNTVALUEIN7
CELL12.IMUX.IMUX.36.DELAY	BITSLICE10.RX_CNTVALUEIN0
CELL12.IMUX.IMUX.37.DELAY	BITSLICE10.RX_CNTVALUEIN1
CELL12.IMUX.IMUX.38.DELAY	BITSLICE10.RX_CNTVALUEIN2
CELL12.IMUX.IMUX.39.DELAY	BITSLICE10.RX_CNTVALUEIN4
CELL12.IMUX.IMUX.40.DELAY	BITSLICE10.RX_CNTVALUEIN6
CELL12.IMUX.IMUX.41.DELAY	BITSLICE10.RX_CNTVALUEIN7
CELL12.IMUX.IMUX.42.DELAY	BITSLICE10.RX_CNTVALUEIN8
CELL12.IMUX.IMUX.43.DELAY	BITSLICE11.TX_CE_OFD
CELL12.IMUX.IMUX.44.DELAY	BITSLICE11.RX_DATAIN1
CELL12.IMUX.IMUX.45.DELAY	BITSLICE11.CLB2PHY_FIFO_RDEN
CELL12.IMUX.IMUX.46.DELAY	BITSLICE11.TX_D0
CELL12.IMUX.IMUX.47.DELAY	BITSLICE11.TX_D2
CELL13.OUT.0.TMIN	PLL0.DRDY
CELL13.OUT.1.TMIN	PLL0.LOCKED
CELL13.OUT.2.TMIN	PLL0.TESTOUT36
CELL13.OUT.3.TMIN	PLL0.SCANOUT
CELL13.OUT.4.TMIN	BITSLICE10.PHY2CLB_FIFO_EMPTY
CELL13.OUT.5.TMIN	BITSLICE10.RX_Q0
CELL13.OUT.6.TMIN	BITSLICE10.RX_Q1
CELL13.OUT.7.TMIN	BITSLICE10.RX_Q2
CELL13.OUT.8.TMIN	BITSLICE10.RX_Q3
CELL13.OUT.9.TMIN	BITSLICE10.RX_Q4
CELL13.OUT.10.TMIN	BITSLICE10.RX_Q5
CELL13.OUT.11.TMIN	BITSLICE10.RX_Q6
CELL13.OUT.12.TMIN	BITSLICE10.RX_Q7
CELL13.OUT.13.TMIN	BITSLICE10.TX_CNTVALUEOUT0
CELL13.OUT.14.TMIN	BITSLICE10.TX_CNTVALUEOUT1
CELL13.OUT.15.TMIN	BITSLICE10.TX_CNTVALUEOUT2
CELL13.OUT.16.TMIN	BITSLICE10.TX_CNTVALUEOUT3
CELL13.OUT.17.TMIN	BITSLICE10.TX_CNTVALUEOUT4
CELL13.OUT.18.TMIN	BITSLICE10.TX_CNTVALUEOUT5
CELL13.OUT.19.TMIN	BITSLICE10.TX_CNTVALUEOUT6
CELL13.OUT.20.TMIN	BITSLICE10.TX_CNTVALUEOUT7
CELL13.OUT.21.TMIN	BITSLICE10.TX_CNTVALUEOUT8
CELL13.OUT.23.TMIN	BITSLICE10.RX_CNTVALUEOUT0
CELL13.OUT.24.TMIN	BITSLICE10.RX_CNTVALUEOUT1
CELL13.OUT.25.TMIN	BITSLICE10.RX_CNTVALUEOUT2
CELL13.OUT.26.TMIN	BITSLICE10.RX_CNTVALUEOUT3
CELL13.OUT.27.TMIN	BITSLICE10.RX_CNTVALUEOUT4
CELL13.OUT.28.TMIN	BITSLICE10.RX_CNTVALUEOUT5
CELL13.OUT.29.TMIN	BITSLICE10.RX_CNTVALUEOUT6
CELL13.OUT.30.TMIN	BITSLICE10.RX_CNTVALUEOUT7
CELL13.OUT.31.TMIN	BITSLICE10.RX_CNTVALUEOUT8
CELL13.IMUX.CTRL.0	PLL0.SCANCLK_B
CELL13.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK9
CELL13.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.TXBIT_RST_B10
CELL13.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.RXBIT_RST_B10
CELL13.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.ODELAY_RST_B10
CELL13.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.IDELAY_RST_B10
CELL13.IMUX.BYP.0	PLL0.DI0
CELL13.IMUX.BYP.1	PLL0.DI1
CELL13.IMUX.BYP.2	PLL0.DI2
CELL13.IMUX.BYP.3	PLL0.DI3
CELL13.IMUX.BYP.6	BITSLICE9.RX_CE_IDELAY
CELL13.IMUX.BYP.7	BITSLICE9.DYN_DCI_OUT_INT
CELL13.IMUX.BYP.8	BITSLICE10.TX_LD
CELL13.IMUX.BYP.9	BITSLICE10.TX_INC
CELL13.IMUX.BYP.10	BITSLICE10.TX_EN_VTC
CELL13.IMUX.BYP.11	BITSLICE10.TX_CE_ODELAY
CELL13.IMUX.BYP.12	BITSLICE10.RX_LD
CELL13.IMUX.BYP.13	BITSLICE10.RX_INC
CELL13.IMUX.BYP.14	BITSLICE10.RX_EN_VTC
CELL13.IMUX.BYP.15	BITSLICE10.RX_CE_IDELAY
CELL13.IMUX.IMUX.0.DELAY	PLL0.RST
CELL13.IMUX.IMUX.6.DELAY	BITSLICE11.TX_D5
CELL13.IMUX.IMUX.7.DELAY	BITSLICE11.TX_D6
CELL13.IMUX.IMUX.8.DELAY	BITSLICE11.TX_D7
CELL13.IMUX.IMUX.9.DELAY	BITSLICE11.TX_CNTVALUEIN0
CELL13.IMUX.IMUX.10.DELAY	BITSLICE11.TX_CNTVALUEIN1
CELL13.IMUX.IMUX.11.DELAY	BITSLICE11.TX_CNTVALUEIN2
CELL13.IMUX.IMUX.12.DELAY	BITSLICE11.TX_CNTVALUEIN3
CELL13.IMUX.IMUX.13.DELAY	BITSLICE11.TX_CNTVALUEIN4
CELL13.IMUX.IMUX.14.DELAY	BITSLICE11.TX_CNTVALUEIN5
CELL13.IMUX.IMUX.15.DELAY	BITSLICE11.TX_CNTVALUEIN6
CELL13.IMUX.IMUX.16.DELAY	BITSLICE11.TX_D4
CELL14.OUT.0.TMIN	PLL1.TESTOUT32
CELL14.OUT.1.TMIN	PLL1.TESTOUT33
CELL14.OUT.2.TMIN	PLL1.TESTOUT34
CELL14.OUT.3.TMIN	PLL1.TESTOUT35
CELL14.OUT.4.TMIN	BITSLICE11.PHY2CLB_FIFO_EMPTY
CELL14.OUT.5.TMIN	BITSLICE11.RX_Q0
CELL14.OUT.6.TMIN	BITSLICE11.RX_Q1
CELL14.OUT.7.TMIN	BITSLICE11.RX_Q2
CELL14.OUT.8.TMIN	BITSLICE11.RX_Q3
CELL14.OUT.9.TMIN	BITSLICE11.RX_Q4
CELL14.OUT.10.TMIN	BITSLICE11.RX_Q5
CELL14.OUT.11.TMIN	BITSLICE11.RX_Q6
CELL14.OUT.12.TMIN	BITSLICE11.RX_Q7
CELL14.OUT.13.TMIN	BITSLICE11.TX_CNTVALUEOUT0
CELL14.OUT.14.TMIN	BITSLICE11.TX_CNTVALUEOUT1
CELL14.OUT.15.TMIN	BITSLICE11.TX_CNTVALUEOUT2
CELL14.OUT.16.TMIN	BITSLICE11.TX_CNTVALUEOUT3
CELL14.OUT.17.TMIN	BITSLICE11.TX_CNTVALUEOUT4
CELL14.OUT.18.TMIN	BITSLICE11.TX_CNTVALUEOUT5
CELL14.OUT.19.TMIN	BITSLICE11.TX_CNTVALUEOUT6
CELL14.OUT.20.TMIN	BITSLICE11.TX_CNTVALUEOUT7
CELL14.OUT.21.TMIN	BITSLICE11.TX_CNTVALUEOUT8
CELL14.OUT.23.TMIN	BITSLICE11.RX_CNTVALUEOUT0
CELL14.OUT.24.TMIN	BITSLICE11.RX_CNTVALUEOUT1
CELL14.OUT.25.TMIN	BITSLICE11.RX_CNTVALUEOUT2
CELL14.OUT.26.TMIN	BITSLICE11.RX_CNTVALUEOUT3
CELL14.OUT.27.TMIN	BITSLICE11.RX_CNTVALUEOUT4
CELL14.OUT.28.TMIN	BITSLICE11.RX_CNTVALUEOUT5
CELL14.OUT.29.TMIN	BITSLICE11.RX_CNTVALUEOUT6
CELL14.OUT.30.TMIN	BITSLICE11.RX_CNTVALUEOUT7
CELL14.OUT.31.TMIN	BITSLICE11.RX_CNTVALUEOUT8
CELL14.IMUX.CTRL.2	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK10
CELL14.IMUX.CTRL.3	XIPHY_FEEDTHROUGH0.TXBIT_RST_B11
CELL14.IMUX.CTRL.4	XIPHY_FEEDTHROUGH0.RXBIT_RST_B11
CELL14.IMUX.CTRL.5	XIPHY_FEEDTHROUGH0.ODELAY_RST_B11
CELL14.IMUX.CTRL.6	XIPHY_FEEDTHROUGH0.IDELAY_RST_B11
CELL14.IMUX.CTRL.7	XIPHY_FEEDTHROUGH0.CLB2PHY_FIFO_CLK11
CELL14.IMUX.BYP.0	PLL1.TESTIN28
CELL14.IMUX.BYP.1	PLL1.TESTIN29
CELL14.IMUX.BYP.2	PLL1.TESTIN30
CELL14.IMUX.BYP.3	PLL1.TESTIN31
CELL14.IMUX.BYP.6	BITSLICE10.DYN_DCI_OUT_INT
CELL14.IMUX.BYP.7	BITSLICE11.TX_LD
CELL14.IMUX.BYP.8	BITSLICE11.TX_INC
CELL14.IMUX.BYP.9	BITSLICE11.TX_EN_VTC
CELL14.IMUX.BYP.10	BITSLICE11.TX_CE_ODELAY
CELL14.IMUX.BYP.11	BITSLICE11.RX_LD
CELL14.IMUX.BYP.12	BITSLICE11.RX_INC
CELL14.IMUX.BYP.13	BITSLICE11.RX_EN_VTC
CELL14.IMUX.BYP.14	BITSLICE11.RX_CE_IDELAY
CELL14.IMUX.BYP.15	BITSLICE11.DYN_DCI_OUT_INT
CELL14.IMUX.IMUX.6.DELAY	BITSLICE11.TX_CNTVALUEIN8
CELL14.IMUX.IMUX.7.DELAY	BITSLICE11.RX_CNTVALUEIN0
CELL14.IMUX.IMUX.8.DELAY	BITSLICE11.RX_CNTVALUEIN1
CELL14.IMUX.IMUX.9.DELAY	BITSLICE11.RX_CNTVALUEIN2
CELL14.IMUX.IMUX.10.DELAY	BITSLICE11.RX_CNTVALUEIN3
CELL14.IMUX.IMUX.11.DELAY	BITSLICE11.RX_CNTVALUEIN4
CELL14.IMUX.IMUX.12.DELAY	BITSLICE11.RX_CNTVALUEIN5
CELL14.IMUX.IMUX.13.DELAY	BITSLICE11.RX_CNTVALUEIN6
CELL14.IMUX.IMUX.14.DELAY	BITSLICE11.RX_CNTVALUEIN7
CELL14.IMUX.IMUX.15.DELAY	BITSLICE11.RX_CNTVALUEIN8
CELL14.IMUX.IMUX.16.DELAY	BITSLICE11.TX_CNTVALUEIN7
CELL15.OUT.0.TMIN	PLL1.TESTOUT28
CELL15.OUT.1.TMIN	PLL1.TESTOUT29
CELL15.OUT.2.TMIN	PLL1.TESTOUT30
CELL15.OUT.3.TMIN	PLL1.TESTOUT31
CELL15.OUT.4.TMIN	BITSLICE13.PHY2CLB_FIFO_EMPTY
CELL15.OUT.5.TMIN	BITSLICE13.RX_Q0
CELL15.OUT.6.TMIN	BITSLICE13.RX_Q1
CELL15.OUT.7.TMIN	BITSLICE13.RX_Q2
CELL15.OUT.8.TMIN	BITSLICE13.RX_Q3
CELL15.OUT.9.TMIN	BITSLICE13.RX_Q4
CELL15.OUT.10.TMIN	BITSLICE13.RX_Q5
CELL15.OUT.11.TMIN	BITSLICE13.RX_Q6
CELL15.OUT.12.TMIN	BITSLICE13.RX_Q7
CELL15.OUT.13.TMIN	BITSLICE13.TX_CNTVALUEOUT0
CELL15.OUT.14.TMIN	BITSLICE13.TX_CNTVALUEOUT1
CELL15.OUT.15.TMIN	BITSLICE13.TX_CNTVALUEOUT2
CELL15.OUT.16.TMIN	BITSLICE13.TX_CNTVALUEOUT3
CELL15.OUT.17.TMIN	BITSLICE13.TX_CNTVALUEOUT4
CELL15.OUT.18.TMIN	BITSLICE13.TX_CNTVALUEOUT5
CELL15.OUT.19.TMIN	BITSLICE13.TX_CNTVALUEOUT6
CELL15.OUT.20.TMIN	BITSLICE13.TX_CNTVALUEOUT7
CELL15.OUT.21.TMIN	BITSLICE13.TX_CNTVALUEOUT8
CELL15.OUT.22.TMIN	BITSLICE13.TX_T_OUT
CELL15.OUT.23.TMIN	BITSLICE13.RX_CNTVALUEOUT0
CELL15.OUT.24.TMIN	BITSLICE13.RX_CNTVALUEOUT1
CELL15.OUT.25.TMIN	BITSLICE13.RX_CNTVALUEOUT2
CELL15.OUT.26.TMIN	BITSLICE13.RX_CNTVALUEOUT3
CELL15.OUT.27.TMIN	BITSLICE13.RX_CNTVALUEOUT4
CELL15.OUT.28.TMIN	BITSLICE13.RX_CNTVALUEOUT5
CELL15.OUT.29.TMIN	BITSLICE13.RX_CNTVALUEOUT6
CELL15.OUT.30.TMIN	BITSLICE13.RX_CNTVALUEOUT7
CELL15.OUT.31.TMIN	BITSLICE13.RX_CNTVALUEOUT8
CELL15.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.TXBIT_TRI_RST_B0
CELL15.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.TXBIT_RST_B0
CELL15.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.RXBIT_RST_B0
CELL15.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.ODELAY_RST_B0
CELL15.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.IDELAY_RST_B0
CELL15.IMUX.BYP.0	PLL1.TESTIN24
CELL15.IMUX.BYP.1	PLL1.TESTIN25
CELL15.IMUX.BYP.2	PLL1.TESTIN26
CELL15.IMUX.BYP.3	PLL1.TESTIN27
CELL15.IMUX.BYP.6	BITSLICE_T2.EN_VTC
CELL15.IMUX.BYP.7	BITSLICE13.TX_LD
CELL15.IMUX.BYP.8	BITSLICE13.TX_INC
CELL15.IMUX.BYP.9	BITSLICE13.TX_EN_VTC
CELL15.IMUX.BYP.10	BITSLICE13.TX_CE_ODELAY
CELL15.IMUX.BYP.11	BITSLICE13.RX_LD
CELL15.IMUX.BYP.12	BITSLICE13.RX_INC
CELL15.IMUX.BYP.13	BITSLICE13.RX_EN_VTC
CELL15.IMUX.BYP.14	BITSLICE13.RX_CE_IDELAY
CELL15.IMUX.BYP.15	BITSLICE13.DYN_DCI_OUT_INT
CELL15.IMUX.IMUX.0.DELAY	PLL1.CLKOUTPHY_EN
CELL15.IMUX.IMUX.6.DELAY	BITSLICE13.TX_CE_OFD
CELL15.IMUX.IMUX.7.DELAY	BITSLICE13.RX_CE_IFD
CELL15.IMUX.IMUX.8.DELAY	BITSLICE13.RX_DATAIN1
CELL15.IMUX.IMUX.9.DELAY	BITSLICE13.CLB2PHY_FIFO_RDEN
CELL15.IMUX.IMUX.10.DELAY	BITSLICE13.TX_D7
CELL15.IMUX.IMUX.11.DELAY	BITSLICE13.TX_D6
CELL15.IMUX.IMUX.12.DELAY	BITSLICE13.TX_D5
CELL15.IMUX.IMUX.13.DELAY	BITSLICE13.TX_D4
CELL15.IMUX.IMUX.14.DELAY	BITSLICE13.TX_D3
CELL15.IMUX.IMUX.15.DELAY	BITSLICE13.TX_D2
CELL15.IMUX.IMUX.16.DELAY	BITSLICE13.TX_T
CELL16.OUT.0.TMIN	PLL1.TESTOUT24
CELL16.OUT.1.TMIN	PLL1.TESTOUT25
CELL16.OUT.2.TMIN	PLL1.TESTOUT26
CELL16.OUT.3.TMIN	PLL1.TESTOUT27
CELL16.OUT.4.TMIN	BITSLICE14.PHY2CLB_FIFO_EMPTY
CELL16.OUT.5.TMIN	BITSLICE14.RX_Q0
CELL16.OUT.6.TMIN	BITSLICE14.RX_Q1
CELL16.OUT.7.TMIN	BITSLICE14.RX_Q2
CELL16.OUT.8.TMIN	BITSLICE14.RX_Q3
CELL16.OUT.9.TMIN	BITSLICE14.RX_Q4
CELL16.OUT.10.TMIN	BITSLICE14.RX_Q5
CELL16.OUT.11.TMIN	BITSLICE14.RX_Q6
CELL16.OUT.12.TMIN	BITSLICE14.RX_Q7
CELL16.OUT.13.TMIN	BITSLICE14.TX_CNTVALUEOUT0
CELL16.OUT.14.TMIN	BITSLICE14.TX_CNTVALUEOUT1
CELL16.OUT.15.TMIN	BITSLICE14.TX_CNTVALUEOUT2
CELL16.OUT.16.TMIN	BITSLICE14.TX_CNTVALUEOUT3
CELL16.OUT.17.TMIN	BITSLICE14.TX_CNTVALUEOUT4
CELL16.OUT.18.TMIN	BITSLICE14.TX_CNTVALUEOUT5
CELL16.OUT.19.TMIN	BITSLICE14.TX_CNTVALUEOUT6
CELL16.OUT.20.TMIN	BITSLICE14.TX_CNTVALUEOUT7
CELL16.OUT.21.TMIN	BITSLICE14.TX_CNTVALUEOUT8
CELL16.OUT.22.TMIN	BITSLICE14.TX_T_OUT
CELL16.OUT.23.TMIN	BITSLICE14.RX_CNTVALUEOUT0
CELL16.OUT.24.TMIN	BITSLICE14.RX_CNTVALUEOUT1
CELL16.OUT.25.TMIN	BITSLICE14.RX_CNTVALUEOUT2
CELL16.OUT.26.TMIN	BITSLICE14.RX_CNTVALUEOUT3
CELL16.OUT.27.TMIN	BITSLICE14.RX_CNTVALUEOUT4
CELL16.OUT.28.TMIN	BITSLICE14.RX_CNTVALUEOUT5
CELL16.OUT.29.TMIN	BITSLICE14.RX_CNTVALUEOUT6
CELL16.OUT.30.TMIN	BITSLICE14.RX_CNTVALUEOUT7
CELL16.OUT.31.TMIN	BITSLICE14.RX_CNTVALUEOUT8
CELL16.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK0
CELL16.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.TXBIT_TRI_RST_B1
CELL16.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.TXBIT_RST_B1
CELL16.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.RXBIT_RST_B1
CELL16.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.ODELAY_RST_B1
CELL16.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.IDELAY_RST_B1
CELL16.IMUX.BYP.0	PLL1.TESTIN20
CELL16.IMUX.BYP.1	PLL1.TESTIN21
CELL16.IMUX.BYP.2	PLL1.TESTIN22
CELL16.IMUX.BYP.3	PLL1.TESTIN23
CELL16.IMUX.BYP.6	BITSLICE_T3.EN_VTC
CELL16.IMUX.BYP.7	BITSLICE14.TX_LD
CELL16.IMUX.BYP.8	BITSLICE14.TX_INC
CELL16.IMUX.BYP.9	BITSLICE14.TX_EN_VTC
CELL16.IMUX.BYP.10	BITSLICE14.TX_CE_ODELAY
CELL16.IMUX.BYP.11	BITSLICE14.RX_LD
CELL16.IMUX.BYP.12	BITSLICE14.RX_INC
CELL16.IMUX.BYP.13	BITSLICE14.RX_EN_VTC
CELL16.IMUX.BYP.14	BITSLICE14.RX_CE_IDELAY
CELL16.IMUX.BYP.15	BITSLICE14.DYN_DCI_OUT_INT
CELL16.IMUX.IMUX.6.DELAY	BITSLICE13.TX_D1
CELL16.IMUX.IMUX.7.DELAY	BITSLICE13.TX_CNTVALUEIN0
CELL16.IMUX.IMUX.8.DELAY	BITSLICE13.TX_CNTVALUEIN1
CELL16.IMUX.IMUX.9.DELAY	BITSLICE13.TX_CNTVALUEIN2
CELL16.IMUX.IMUX.10.DELAY	BITSLICE13.TX_CNTVALUEIN3
CELL16.IMUX.IMUX.11.DELAY	BITSLICE13.TX_CNTVALUEIN4
CELL16.IMUX.IMUX.12.DELAY	BITSLICE13.TX_CNTVALUEIN5
CELL16.IMUX.IMUX.13.DELAY	BITSLICE13.TX_CNTVALUEIN6
CELL16.IMUX.IMUX.14.DELAY	BITSLICE13.TX_CNTVALUEIN7
CELL16.IMUX.IMUX.15.DELAY	BITSLICE13.TX_CNTVALUEIN8
CELL16.IMUX.IMUX.16.DELAY	BITSLICE13.TX_D0
CELL17.OUT.0.TMIN	PLL1.TESTOUT20
CELL17.OUT.1.TMIN	PLL1.TESTOUT21
CELL17.OUT.2.TMIN	PLL1.TESTOUT22
CELL17.OUT.3.TMIN	PLL1.TESTOUT23
CELL17.OUT.4.TMIN	BITSLICE15.PHY2CLB_FIFO_EMPTY
CELL17.OUT.5.TMIN	BITSLICE15.RX_Q0
CELL17.OUT.6.TMIN	BITSLICE15.RX_Q1
CELL17.OUT.7.TMIN	BITSLICE15.RX_Q2
CELL17.OUT.8.TMIN	BITSLICE15.RX_Q3
CELL17.OUT.9.TMIN	BITSLICE15.RX_Q4
CELL17.OUT.10.TMIN	BITSLICE15.RX_Q5
CELL17.OUT.11.TMIN	BITSLICE15.RX_Q6
CELL17.OUT.12.TMIN	BITSLICE15.RX_Q7
CELL17.OUT.13.TMIN	BITSLICE15.TX_CNTVALUEOUT0
CELL17.OUT.14.TMIN	BITSLICE15.TX_CNTVALUEOUT1
CELL17.OUT.15.TMIN	BITSLICE15.TX_CNTVALUEOUT2
CELL17.OUT.16.TMIN	BITSLICE15.TX_CNTVALUEOUT3
CELL17.OUT.17.TMIN	BITSLICE15.TX_CNTVALUEOUT4
CELL17.OUT.18.TMIN	BITSLICE15.TX_CNTVALUEOUT5
CELL17.OUT.19.TMIN	BITSLICE15.TX_CNTVALUEOUT6
CELL17.OUT.20.TMIN	BITSLICE15.TX_CNTVALUEOUT7
CELL17.OUT.21.TMIN	BITSLICE15.TX_CNTVALUEOUT8
CELL17.OUT.22.TMIN	BITSLICE15.TX_T_OUT
CELL17.OUT.23.TMIN	BITSLICE15.RX_CNTVALUEOUT0
CELL17.OUT.24.TMIN	BITSLICE15.RX_CNTVALUEOUT1
CELL17.OUT.25.TMIN	BITSLICE15.RX_CNTVALUEOUT2
CELL17.OUT.26.TMIN	BITSLICE15.RX_CNTVALUEOUT3
CELL17.OUT.27.TMIN	BITSLICE15.RX_CNTVALUEOUT4
CELL17.OUT.28.TMIN	BITSLICE15.RX_CNTVALUEOUT5
CELL17.OUT.29.TMIN	BITSLICE15.RX_CNTVALUEOUT6
CELL17.OUT.30.TMIN	BITSLICE15.RX_CNTVALUEOUT7
CELL17.OUT.31.TMIN	BITSLICE15.RX_CNTVALUEOUT8
CELL17.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK1
CELL17.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.TXBIT_RST_B2
CELL17.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.RXBIT_RST_B2
CELL17.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.ODELAY_RST_B2
CELL17.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.IDELAY_RST_B2
CELL17.IMUX.BYP.0	PLL1.TESTIN16
CELL17.IMUX.BYP.1	PLL1.TESTIN17
CELL17.IMUX.BYP.2	PLL1.TESTIN18
CELL17.IMUX.BYP.3	PLL1.TESTIN19
CELL17.IMUX.BYP.6	BITSLICE15.TX_LD
CELL17.IMUX.BYP.7	BITSLICE15.TX_INC
CELL17.IMUX.BYP.8	BITSLICE15.TX_EN_VTC
CELL17.IMUX.BYP.9	BITSLICE15.TX_CE_ODELAY
CELL17.IMUX.BYP.10	BITSLICE15.RX_LD
CELL17.IMUX.BYP.11	BITSLICE15.RX_INC
CELL17.IMUX.BYP.12	BITSLICE15.RX_EN_VTC
CELL17.IMUX.BYP.13	BITSLICE15.RX_CE_IDELAY
CELL17.IMUX.BYP.14	BITSLICE15.DYN_DCI_OUT_INT
CELL17.IMUX.BYP.15	BITSLICE_T2.CE_OFD
CELL17.IMUX.IMUX.6.DELAY	BITSLICE14.TX_D1
CELL17.IMUX.IMUX.7.DELAY	BITSLICE14.TX_D3
CELL17.IMUX.IMUX.8.DELAY	BITSLICE14.TX_D7
CELL17.IMUX.IMUX.9.DELAY	BITSLICE14.TX_CNTVALUEIN1
CELL17.IMUX.IMUX.10.DELAY	BITSLICE14.TX_CNTVALUEIN5
CELL17.IMUX.IMUX.11.DELAY	BITSLICE14.TX_CNTVALUEIN7
CELL17.IMUX.IMUX.12.DELAY	BITSLICE14.RX_CNTVALUEIN2
CELL17.IMUX.IMUX.13.DELAY	BITSLICE14.RX_CNTVALUEIN4
CELL17.IMUX.IMUX.14.DELAY	BITSLICE14.RX_CNTVALUEIN8
CELL17.IMUX.IMUX.15.DELAY	BITSLICE15.TX_CE_OFD
CELL17.IMUX.IMUX.16.DELAY	BITSLICE13.RX_CNTVALUEIN0
CELL17.IMUX.IMUX.17.DELAY	BITSLICE13.RX_CNTVALUEIN1
CELL17.IMUX.IMUX.18.DELAY	BITSLICE13.RX_CNTVALUEIN2
CELL17.IMUX.IMUX.19.DELAY	BITSLICE13.RX_CNTVALUEIN3
CELL17.IMUX.IMUX.20.DELAY	BITSLICE13.RX_CNTVALUEIN4
CELL17.IMUX.IMUX.21.DELAY	BITSLICE13.RX_CNTVALUEIN5
CELL17.IMUX.IMUX.22.DELAY	BITSLICE13.RX_CNTVALUEIN6
CELL17.IMUX.IMUX.23.DELAY	BITSLICE13.RX_CNTVALUEIN7
CELL17.IMUX.IMUX.24.DELAY	BITSLICE13.RX_CNTVALUEIN8
CELL17.IMUX.IMUX.25.DELAY	BITSLICE14.TX_T
CELL17.IMUX.IMUX.26.DELAY	BITSLICE14.TX_CE_OFD
CELL17.IMUX.IMUX.27.DELAY	BITSLICE14.RX_CE_IFD
CELL17.IMUX.IMUX.28.DELAY	BITSLICE14.RX_DATAIN1
CELL17.IMUX.IMUX.29.DELAY	BITSLICE14.CLB2PHY_FIFO_RDEN
CELL17.IMUX.IMUX.30.DELAY	BITSLICE14.TX_D0
CELL17.IMUX.IMUX.31.DELAY	BITSLICE14.TX_D2
CELL17.IMUX.IMUX.32.DELAY	BITSLICE14.TX_D4
CELL17.IMUX.IMUX.33.DELAY	BITSLICE14.TX_D5
CELL17.IMUX.IMUX.34.DELAY	BITSLICE14.TX_D6
CELL17.IMUX.IMUX.35.DELAY	BITSLICE14.TX_CNTVALUEIN0
CELL17.IMUX.IMUX.36.DELAY	BITSLICE14.TX_CNTVALUEIN2
CELL17.IMUX.IMUX.37.DELAY	BITSLICE14.TX_CNTVALUEIN3
CELL17.IMUX.IMUX.38.DELAY	BITSLICE14.TX_CNTVALUEIN4
CELL17.IMUX.IMUX.39.DELAY	BITSLICE14.TX_CNTVALUEIN6
CELL17.IMUX.IMUX.40.DELAY	BITSLICE14.TX_CNTVALUEIN8
CELL17.IMUX.IMUX.41.DELAY	BITSLICE14.RX_CNTVALUEIN0
CELL17.IMUX.IMUX.42.DELAY	BITSLICE14.RX_CNTVALUEIN1
CELL17.IMUX.IMUX.43.DELAY	BITSLICE14.RX_CNTVALUEIN3
CELL17.IMUX.IMUX.44.DELAY	BITSLICE14.RX_CNTVALUEIN5
CELL17.IMUX.IMUX.45.DELAY	BITSLICE14.RX_CNTVALUEIN6
CELL17.IMUX.IMUX.46.DELAY	BITSLICE14.RX_CNTVALUEIN7
CELL17.IMUX.IMUX.47.DELAY	BITSLICE15.TX_T
CELL18.OUT.0.TMIN	PLL1.TESTOUT16
CELL18.OUT.1.TMIN	PLL1.TESTOUT17
CELL18.OUT.2.TMIN	PLL1.TESTOUT18
CELL18.OUT.3.TMIN	PLL1.TESTOUT19
CELL18.OUT.4.TMIN	BITSLICE_T2.CNTVALUEOUT0
CELL18.OUT.5.TMIN	BITSLICE_T2.CNTVALUEOUT1
CELL18.OUT.6.TMIN	BITSLICE_T2.CNTVALUEOUT2
CELL18.OUT.7.TMIN	BITSLICE_T2.CNTVALUEOUT3
CELL18.OUT.8.TMIN	BITSLICE_T2.CNTVALUEOUT4
CELL18.OUT.9.TMIN	BITSLICE_T2.CNTVALUEOUT5
CELL18.OUT.10.TMIN	BITSLICE_T2.CNTVALUEOUT6
CELL18.OUT.11.TMIN	BITSLICE_T2.CNTVALUEOUT7
CELL18.OUT.12.TMIN	BITSLICE_T2.CNTVALUEOUT8
CELL18.OUT.13.TMIN	BITSLICE16.TX_T_OUT
CELL18.OUT.14.TMIN	BITSLICE_CONTROL2.PHY2CLB_PHY_RDY
CELL18.OUT.15.TMIN	BITSLICE_CONTROL2.MASTER_PD_OUT
CELL18.OUT.16.TMIN	BITSLICE_CONTROL2.PHY2CLB_FIXDLY_RDY
CELL18.OUT.17.TMIN	BITSLICE_CONTROL2.CTRL_DLY_TEST_OUT
CELL18.OUT.18.TMIN	BITSLICE16.PHY2CLB_FIFO_EMPTY
CELL18.OUT.19.TMIN	BITSLICE16.RX_Q0
CELL18.OUT.20.TMIN	BITSLICE16.RX_Q1
CELL18.OUT.21.TMIN	BITSLICE16.RX_Q2
CELL18.OUT.22.TMIN	BITSLICE16.RX_Q3
CELL18.OUT.23.TMIN	BITSLICE16.RX_Q4
CELL18.OUT.24.TMIN	BITSLICE16.RX_Q5
CELL18.OUT.25.TMIN	BITSLICE16.RX_Q6
CELL18.OUT.26.TMIN	BITSLICE16.RX_Q7
CELL18.OUT.27.TMIN	BITSLICE16.TX_CNTVALUEOUT0
CELL18.OUT.28.TMIN	BITSLICE16.TX_CNTVALUEOUT1
CELL18.OUT.29.TMIN	BITSLICE16.TX_CNTVALUEOUT2
CELL18.OUT.30.TMIN	BITSLICE16.TX_CNTVALUEOUT3
CELL18.OUT.31.TMIN	BITSLICE16.TX_CNTVALUEOUT4
CELL18.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK2
CELL18.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.TRISTATE_ODELAY_RST_B0
CELL18.IMUX.CTRL.5	BITSLICE_CONTROL2.REFCLK
CELL18.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.CTRL_RST_B_LOW
CELL18.IMUX.CTRL.7	BITSLICE_CONTROL2.RIU_CLK, XIPHY_FEEDTHROUGH1.CLB2PHY_CTRL_CLK_LOW
CELL18.IMUX.BYP.0	PLL1.TESTIN12
CELL18.IMUX.BYP.1	PLL1.TESTIN13
CELL18.IMUX.BYP.2	PLL1.TESTIN14
CELL18.IMUX.BYP.3	PLL1.TESTIN15
CELL18.IMUX.BYP.6	BITSLICE_T2.LD
CELL18.IMUX.BYP.7	BITSLICE_T2.INC
CELL18.IMUX.BYP.8	BITSLICE_T2.CE_ODELAY
CELL18.IMUX.BYP.9	BITSLICE_CONTROL2.EN_VTC
CELL18.IMUX.BYP.10	BITSLICE_CONTROL2.CTRL_DLY_TEST_IN
CELL18.IMUX.BYP.12	BITSLICE16.TX_LD
CELL18.IMUX.BYP.13	BITSLICE16.TX_INC
CELL18.IMUX.BYP.14	BITSLICE16.TX_EN_VTC
CELL18.IMUX.BYP.15	BITSLICE16.TX_CE_ODELAY
CELL18.IMUX.IMUX.6.DELAY	BITSLICE15.TX_CNTVALUEIN3
CELL18.IMUX.IMUX.7.DELAY	BITSLICE15.TX_CNTVALUEIN5
CELL18.IMUX.IMUX.8.DELAY	BITSLICE15.RX_CNTVALUEIN0
CELL18.IMUX.IMUX.9.DELAY	BITSLICE15.RX_CNTVALUEIN2
CELL18.IMUX.IMUX.10.DELAY	BITSLICE15.RX_CNTVALUEIN6
CELL18.IMUX.IMUX.11.DELAY	BITSLICE15.RX_CNTVALUEIN8
CELL18.IMUX.IMUX.12.DELAY	BITSLICE_T2.CNTVALUEIN3
CELL18.IMUX.IMUX.13.DELAY	BITSLICE_T2.CNTVALUEIN5
CELL18.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL2.CLB2RIU_NIBBLE_SEL
CELL18.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS1_1
CELL18.IMUX.IMUX.16.DELAY	BITSLICE15.RX_CE_IFD
CELL18.IMUX.IMUX.17.DELAY	BITSLICE15.RX_DATAIN1
CELL18.IMUX.IMUX.18.DELAY	BITSLICE15.CLB2PHY_FIFO_RDEN
CELL18.IMUX.IMUX.20.DELAY	BITSLICE15.TX_D0
CELL18.IMUX.IMUX.21.DELAY	BITSLICE15.TX_D1
CELL18.IMUX.IMUX.22.DELAY	BITSLICE15.TX_D2
CELL18.IMUX.IMUX.23.DELAY	BITSLICE15.TX_D3
CELL18.IMUX.IMUX.24.DELAY	BITSLICE15.TX_D4
CELL18.IMUX.IMUX.25.DELAY	BITSLICE15.TX_D5
CELL18.IMUX.IMUX.26.DELAY	BITSLICE15.TX_D6
CELL18.IMUX.IMUX.27.DELAY	BITSLICE15.TX_D7
CELL18.IMUX.IMUX.28.DELAY	BITSLICE15.TX_CNTVALUEIN0
CELL18.IMUX.IMUX.29.DELAY	BITSLICE15.TX_CNTVALUEIN1
CELL18.IMUX.IMUX.30.DELAY	BITSLICE15.TX_CNTVALUEIN2
CELL18.IMUX.IMUX.31.DELAY	BITSLICE15.TX_CNTVALUEIN4
CELL18.IMUX.IMUX.32.DELAY	BITSLICE15.TX_CNTVALUEIN6
CELL18.IMUX.IMUX.33.DELAY	BITSLICE15.TX_CNTVALUEIN7
CELL18.IMUX.IMUX.34.DELAY	BITSLICE15.TX_CNTVALUEIN8
CELL18.IMUX.IMUX.35.DELAY	BITSLICE15.RX_CNTVALUEIN1
CELL18.IMUX.IMUX.36.DELAY	BITSLICE15.RX_CNTVALUEIN3
CELL18.IMUX.IMUX.37.DELAY	BITSLICE15.RX_CNTVALUEIN4
CELL18.IMUX.IMUX.38.DELAY	BITSLICE15.RX_CNTVALUEIN5
CELL18.IMUX.IMUX.39.DELAY	BITSLICE15.RX_CNTVALUEIN7
CELL18.IMUX.IMUX.40.DELAY	BITSLICE_T2.CNTVALUEIN0
CELL18.IMUX.IMUX.41.DELAY	BITSLICE_T2.CNTVALUEIN1
CELL18.IMUX.IMUX.42.DELAY	BITSLICE_T2.CNTVALUEIN2
CELL18.IMUX.IMUX.43.DELAY	BITSLICE_T2.CNTVALUEIN4
CELL18.IMUX.IMUX.44.DELAY	BITSLICE_T2.CNTVALUEIN6
CELL18.IMUX.IMUX.45.DELAY	BITSLICE_T2.CNTVALUEIN7
CELL18.IMUX.IMUX.46.DELAY	BITSLICE_T2.CNTVALUEIN8
CELL18.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS1_0
CELL19.OUT.0.TMIN	PLL1.TESTOUT12
CELL19.OUT.1.TMIN	PLL1.TESTOUT13
CELL19.OUT.2.TMIN	PLL1.TESTOUT14
CELL19.OUT.3.TMIN	PLL1.TESTOUT15
CELL19.OUT.4.TMIN	BITSLICE16.TX_CNTVALUEOUT5
CELL19.OUT.5.TMIN	BITSLICE16.TX_CNTVALUEOUT6
CELL19.OUT.6.TMIN	BITSLICE16.TX_CNTVALUEOUT7
CELL19.OUT.7.TMIN	BITSLICE16.TX_CNTVALUEOUT8
CELL19.OUT.8.TMIN	BITSLICE17.TX_T_OUT
CELL19.OUT.9.TMIN	BITSLICE16.RX_CNTVALUEOUT0
CELL19.OUT.10.TMIN	BITSLICE16.RX_CNTVALUEOUT1
CELL19.OUT.11.TMIN	BITSLICE16.RX_CNTVALUEOUT2
CELL19.OUT.12.TMIN	BITSLICE16.RX_CNTVALUEOUT3
CELL19.OUT.13.TMIN	BITSLICE16.RX_CNTVALUEOUT4
CELL19.OUT.14.TMIN	BITSLICE16.RX_CNTVALUEOUT5
CELL19.OUT.15.TMIN	BITSLICE16.RX_CNTVALUEOUT6
CELL19.OUT.16.TMIN	BITSLICE16.RX_CNTVALUEOUT7
CELL19.OUT.17.TMIN	BITSLICE16.RX_CNTVALUEOUT8
CELL19.OUT.18.TMIN	BITSLICE17.PHY2CLB_FIFO_EMPTY
CELL19.OUT.19.TMIN	BITSLICE17.RX_Q0
CELL19.OUT.20.TMIN	BITSLICE17.RX_Q1
CELL19.OUT.21.TMIN	BITSLICE17.RX_Q2
CELL19.OUT.22.TMIN	BITSLICE17.RX_Q3
CELL19.OUT.23.TMIN	BITSLICE17.RX_Q4
CELL19.OUT.24.TMIN	BITSLICE17.RX_Q5
CELL19.OUT.25.TMIN	BITSLICE17.RX_Q6
CELL19.OUT.26.TMIN	BITSLICE17.RX_Q7
CELL19.OUT.27.TMIN	BITSLICE17.TX_CNTVALUEOUT0
CELL19.OUT.28.TMIN	BITSLICE17.TX_CNTVALUEOUT1
CELL19.OUT.29.TMIN	BITSLICE17.TX_CNTVALUEOUT2
CELL19.OUT.30.TMIN	BITSLICE17.TX_CNTVALUEOUT3
CELL19.OUT.31.TMIN	BITSLICE17.TX_CNTVALUEOUT4
CELL19.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.TXBIT_RST_B3
CELL19.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.RXBIT_RST_B3
CELL19.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.ODELAY_RST_B3
CELL19.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.IDELAY_RST_B3
CELL19.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK3
CELL19.IMUX.BYP.0	PLL1.TESTIN8
CELL19.IMUX.BYP.1	PLL1.TESTIN9
CELL19.IMUX.BYP.2	PLL1.TESTIN10
CELL19.IMUX.BYP.3	PLL1.TESTIN11
CELL19.IMUX.BYP.6	BITSLICE16.RX_LD
CELL19.IMUX.BYP.7	BITSLICE16.RX_INC
CELL19.IMUX.BYP.8	BITSLICE16.RX_EN_VTC
CELL19.IMUX.BYP.9	BITSLICE16.RX_CE_IDELAY
CELL19.IMUX.BYP.10	BITSLICE16.DYN_DCI_OUT_INT
CELL19.IMUX.BYP.11	BITSLICE17.TX_LD
CELL19.IMUX.BYP.12	BITSLICE17.TX_INC
CELL19.IMUX.BYP.13	BITSLICE17.TX_EN_VTC
CELL19.IMUX.BYP.14	BITSLICE17.TX_CE_ODELAY
CELL19.IMUX.BYP.15	BITSLICE17.RX_LD
CELL19.IMUX.IMUX.6.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS1_1
CELL19.IMUX.IMUX.7.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS1_3
CELL19.IMUX.IMUX.8.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS0_3
CELL19.IMUX.IMUX.9.DELAY	BITSLICE16.TX_CE_OFD
CELL19.IMUX.IMUX.10.DELAY	BITSLICE16.TX_D0
CELL19.IMUX.IMUX.11.DELAY	BITSLICE16.TX_D2
CELL19.IMUX.IMUX.12.DELAY	BITSLICE16.TX_D6
CELL19.IMUX.IMUX.13.DELAY	BITSLICE16.TX_D7
CELL19.IMUX.IMUX.14.DELAY	BITSLICE16.TX_CNTVALUEIN3
CELL19.IMUX.IMUX.15.DELAY	BITSLICE16.TX_CNTVALUEIN5
CELL19.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS1_2
CELL19.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS1_3
CELL19.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS0_0
CELL19.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS0_1
CELL19.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS0_2
CELL19.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL2.CLB2PHY_WRCS0_3
CELL19.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL2.CLB2PHY_T_B0
CELL19.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL2.CLB2PHY_T_B1
CELL19.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL2.CLB2PHY_T_B2
CELL19.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL2.CLB2PHY_T_B3
CELL19.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDEN0
CELL19.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDEN1
CELL19.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDEN2
CELL19.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDEN3
CELL19.IMUX.IMUX.30.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS1_0
CELL19.IMUX.IMUX.31.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS1_2
CELL19.IMUX.IMUX.32.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS0_0
CELL19.IMUX.IMUX.33.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS0_1
CELL19.IMUX.IMUX.34.DELAY	BITSLICE_CONTROL2.CLB2PHY_RDCS0_2
CELL19.IMUX.IMUX.35.DELAY	BITSLICE16.TX_T
CELL19.IMUX.IMUX.36.DELAY	BITSLICE16.RX_CE_IFD
CELL19.IMUX.IMUX.37.DELAY	BITSLICE16.RX_DATAIN1
CELL19.IMUX.IMUX.38.DELAY	BITSLICE16.CLB2PHY_FIFO_RDEN
CELL19.IMUX.IMUX.39.DELAY	BITSLICE16.TX_D1
CELL19.IMUX.IMUX.40.DELAY	BITSLICE16.TX_D3
CELL19.IMUX.IMUX.41.DELAY	BITSLICE16.TX_D4
CELL19.IMUX.IMUX.42.DELAY	BITSLICE16.TX_D5
CELL19.IMUX.IMUX.44.DELAY	BITSLICE16.TX_CNTVALUEIN0
CELL19.IMUX.IMUX.45.DELAY	BITSLICE16.TX_CNTVALUEIN1
CELL19.IMUX.IMUX.46.DELAY	BITSLICE16.TX_CNTVALUEIN2
CELL19.IMUX.IMUX.47.DELAY	BITSLICE16.TX_CNTVALUEIN4
CELL20.OUT.0.TMIN	PLL1.TESTOUT8
CELL20.OUT.1.TMIN	PLL1.TESTOUT9
CELL20.OUT.2.TMIN	PLL1.TESTOUT10
CELL20.OUT.3.TMIN	PLL1.TESTOUT11
CELL20.OUT.4.TMIN	BITSLICE17.TX_CNTVALUEOUT5
CELL20.OUT.5.TMIN	BITSLICE17.TX_CNTVALUEOUT6
CELL20.OUT.6.TMIN	BITSLICE17.TX_CNTVALUEOUT7
CELL20.OUT.7.TMIN	BITSLICE17.TX_CNTVALUEOUT8
CELL20.OUT.8.TMIN	BITSLICE18.TX_T_OUT
CELL20.OUT.9.TMIN	BITSLICE17.RX_CNTVALUEOUT0
CELL20.OUT.10.TMIN	BITSLICE17.RX_CNTVALUEOUT1
CELL20.OUT.11.TMIN	BITSLICE17.RX_CNTVALUEOUT2
CELL20.OUT.12.TMIN	BITSLICE17.RX_CNTVALUEOUT3
CELL20.OUT.13.TMIN	BITSLICE17.RX_CNTVALUEOUT4
CELL20.OUT.14.TMIN	BITSLICE17.RX_CNTVALUEOUT5
CELL20.OUT.15.TMIN	BITSLICE17.RX_CNTVALUEOUT6
CELL20.OUT.16.TMIN	BITSLICE17.RX_CNTVALUEOUT7
CELL20.OUT.17.TMIN	BITSLICE17.RX_CNTVALUEOUT8
CELL20.OUT.18.TMIN	BITSLICE18.PHY2CLB_FIFO_EMPTY
CELL20.OUT.19.TMIN	BITSLICE18.RX_Q0
CELL20.OUT.20.TMIN	BITSLICE18.RX_Q1
CELL20.OUT.21.TMIN	BITSLICE18.RX_Q2
CELL20.OUT.22.TMIN	BITSLICE18.RX_Q3
CELL20.OUT.23.TMIN	BITSLICE18.RX_Q4
CELL20.OUT.24.TMIN	BITSLICE18.RX_Q5
CELL20.OUT.25.TMIN	BITSLICE18.RX_Q6
CELL20.OUT.26.TMIN	BITSLICE18.RX_Q7
CELL20.OUT.27.TMIN	BITSLICE18.TX_CNTVALUEOUT0
CELL20.OUT.28.TMIN	BITSLICE18.TX_CNTVALUEOUT1
CELL20.OUT.29.TMIN	BITSLICE18.TX_CNTVALUEOUT2
CELL20.OUT.30.TMIN	BITSLICE18.TX_CNTVALUEOUT3
CELL20.OUT.31.TMIN	BITSLICE18.TX_CNTVALUEOUT4
CELL20.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.TXBIT_RST_B4
CELL20.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.RXBIT_RST_B4
CELL20.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.ODELAY_RST_B4
CELL20.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.IDELAY_RST_B4
CELL20.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK4
CELL20.IMUX.BYP.0	PLL1.TESTIN4
CELL20.IMUX.BYP.1	PLL1.TESTIN5
CELL20.IMUX.BYP.2	PLL1.TESTIN6
CELL20.IMUX.BYP.3	PLL1.TESTIN7
CELL20.IMUX.BYP.6	BITSLICE17.RX_INC
CELL20.IMUX.BYP.7	BITSLICE17.RX_EN_VTC
CELL20.IMUX.BYP.8	BITSLICE17.RX_CE_IDELAY
CELL20.IMUX.BYP.9	BITSLICE17.DYN_DCI_OUT_INT
CELL20.IMUX.BYP.10	BITSLICE18.TX_LD
CELL20.IMUX.BYP.11	BITSLICE18.TX_INC
CELL20.IMUX.BYP.12	BITSLICE18.TX_EN_VTC
CELL20.IMUX.BYP.13	BITSLICE18.TX_CE_ODELAY
CELL20.IMUX.BYP.14	BITSLICE18.RX_LD
CELL20.IMUX.BYP.15	BITSLICE18.RX_INC
CELL20.IMUX.IMUX.0.DELAY	PLL1.SCANMODEB
CELL20.IMUX.IMUX.6.DELAY	BITSLICE17.RX_DATAIN1
CELL20.IMUX.IMUX.7.DELAY	BITSLICE17.TX_D0
CELL20.IMUX.IMUX.8.DELAY	BITSLICE17.TX_D4
CELL20.IMUX.IMUX.9.DELAY	BITSLICE17.TX_D6
CELL20.IMUX.IMUX.10.DELAY	BITSLICE17.TX_CNTVALUEIN2
CELL20.IMUX.IMUX.11.DELAY	BITSLICE17.TX_CNTVALUEIN4
CELL20.IMUX.IMUX.12.DELAY	BITSLICE17.TX_CNTVALUEIN8
CELL20.IMUX.IMUX.13.DELAY	BITSLICE17.RX_CNTVALUEIN1
CELL20.IMUX.IMUX.14.DELAY	BITSLICE17.RX_CNTVALUEIN5
CELL20.IMUX.IMUX.15.DELAY	BITSLICE17.RX_CNTVALUEIN7
CELL20.IMUX.IMUX.16.DELAY	BITSLICE16.TX_CNTVALUEIN6
CELL20.IMUX.IMUX.17.DELAY	BITSLICE16.TX_CNTVALUEIN7
CELL20.IMUX.IMUX.18.DELAY	BITSLICE16.TX_CNTVALUEIN8
CELL20.IMUX.IMUX.19.DELAY	BITSLICE16.RX_CNTVALUEIN0
CELL20.IMUX.IMUX.20.DELAY	BITSLICE16.RX_CNTVALUEIN1
CELL20.IMUX.IMUX.21.DELAY	BITSLICE16.RX_CNTVALUEIN2
CELL20.IMUX.IMUX.22.DELAY	BITSLICE16.RX_CNTVALUEIN3
CELL20.IMUX.IMUX.23.DELAY	BITSLICE16.RX_CNTVALUEIN4
CELL20.IMUX.IMUX.24.DELAY	BITSLICE16.RX_CNTVALUEIN5
CELL20.IMUX.IMUX.25.DELAY	BITSLICE16.RX_CNTVALUEIN6
CELL20.IMUX.IMUX.26.DELAY	BITSLICE16.RX_CNTVALUEIN7
CELL20.IMUX.IMUX.27.DELAY	BITSLICE16.RX_CNTVALUEIN8
CELL20.IMUX.IMUX.28.DELAY	BITSLICE17.TX_T
CELL20.IMUX.IMUX.29.DELAY	BITSLICE17.TX_CE_OFD
CELL20.IMUX.IMUX.30.DELAY	BITSLICE17.RX_CE_IFD
CELL20.IMUX.IMUX.31.DELAY	BITSLICE17.CLB2PHY_FIFO_RDEN
CELL20.IMUX.IMUX.32.DELAY	BITSLICE17.TX_D1
CELL20.IMUX.IMUX.33.DELAY	BITSLICE17.TX_D2
CELL20.IMUX.IMUX.34.DELAY	BITSLICE17.TX_D3
CELL20.IMUX.IMUX.35.DELAY	BITSLICE17.TX_D5
CELL20.IMUX.IMUX.36.DELAY	BITSLICE17.TX_D7
CELL20.IMUX.IMUX.37.DELAY	BITSLICE17.TX_CNTVALUEIN0
CELL20.IMUX.IMUX.38.DELAY	BITSLICE17.TX_CNTVALUEIN1
CELL20.IMUX.IMUX.39.DELAY	BITSLICE17.TX_CNTVALUEIN3
CELL20.IMUX.IMUX.40.DELAY	BITSLICE17.TX_CNTVALUEIN5
CELL20.IMUX.IMUX.41.DELAY	BITSLICE17.TX_CNTVALUEIN6
CELL20.IMUX.IMUX.42.DELAY	BITSLICE17.TX_CNTVALUEIN7
CELL20.IMUX.IMUX.43.DELAY	BITSLICE17.RX_CNTVALUEIN0
CELL20.IMUX.IMUX.44.DELAY	BITSLICE17.RX_CNTVALUEIN2
CELL20.IMUX.IMUX.45.DELAY	BITSLICE17.RX_CNTVALUEIN3
CELL20.IMUX.IMUX.46.DELAY	BITSLICE17.RX_CNTVALUEIN4
CELL20.IMUX.IMUX.47.DELAY	BITSLICE17.RX_CNTVALUEIN6
CELL21.OUT.0.TMIN	PLL1.TESTOUT4
CELL21.OUT.1.TMIN	PLL1.TESTOUT5
CELL21.OUT.2.TMIN	PLL1.TESTOUT6
CELL21.OUT.3.TMIN	PLL1.TESTOUT7
CELL21.OUT.4.TMIN	BITSLICE18.TX_CNTVALUEOUT5
CELL21.OUT.5.TMIN	BITSLICE18.TX_CNTVALUEOUT6
CELL21.OUT.6.TMIN	BITSLICE18.TX_CNTVALUEOUT7
CELL21.OUT.7.TMIN	BITSLICE18.TX_CNTVALUEOUT8
CELL21.OUT.8.TMIN	BITSLICE19.TX_T_OUT
CELL21.OUT.9.TMIN	BITSLICE18.RX_CNTVALUEOUT0
CELL21.OUT.10.TMIN	BITSLICE18.RX_CNTVALUEOUT1
CELL21.OUT.11.TMIN	BITSLICE18.RX_CNTVALUEOUT2
CELL21.OUT.12.TMIN	BITSLICE18.RX_CNTVALUEOUT3
CELL21.OUT.13.TMIN	BITSLICE18.RX_CNTVALUEOUT4
CELL21.OUT.14.TMIN	BITSLICE18.RX_CNTVALUEOUT5
CELL21.OUT.15.TMIN	BITSLICE18.RX_CNTVALUEOUT6
CELL21.OUT.16.TMIN	BITSLICE18.RX_CNTVALUEOUT7
CELL21.OUT.17.TMIN	BITSLICE18.RX_CNTVALUEOUT8
CELL21.OUT.18.TMIN	RIU_OR1.RIU_RD_VALID
CELL21.OUT.19.TMIN	RIU_OR1.RIU_RD_DATA0
CELL21.OUT.20.TMIN	RIU_OR1.RIU_RD_DATA1
CELL21.OUT.21.TMIN	RIU_OR1.RIU_RD_DATA2
CELL21.OUT.22.TMIN	RIU_OR1.RIU_RD_DATA3
CELL21.OUT.23.TMIN	RIU_OR1.RIU_RD_DATA4
CELL21.OUT.24.TMIN	RIU_OR1.RIU_RD_DATA5
CELL21.OUT.25.TMIN	RIU_OR1.RIU_RD_DATA6
CELL21.OUT.26.TMIN	RIU_OR1.RIU_RD_DATA7
CELL21.OUT.27.TMIN	RIU_OR1.RIU_RD_DATA8
CELL21.OUT.28.TMIN	RIU_OR1.RIU_RD_DATA9
CELL21.OUT.29.TMIN	RIU_OR1.RIU_RD_DATA10
CELL21.OUT.30.TMIN	RIU_OR1.RIU_RD_DATA11
CELL21.OUT.31.TMIN	RIU_OR1.RIU_RD_DATA12
CELL21.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.TXBIT_RST_B5
CELL21.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.RXBIT_RST_B5
CELL21.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.ODELAY_RST_B5
CELL21.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.IDELAY_RST_B5
CELL21.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK5
CELL21.IMUX.BYP.0	PLL1.TESTIN0
CELL21.IMUX.BYP.1	PLL1.TESTIN1
CELL21.IMUX.BYP.2	PLL1.TESTIN2
CELL21.IMUX.BYP.3	PLL1.TESTIN3
CELL21.IMUX.BYP.6	BITSLICE18.RX_EN_VTC
CELL21.IMUX.BYP.7	BITSLICE18.RX_CE_IDELAY
CELL21.IMUX.BYP.8	BITSLICE18.DYN_DCI_OUT_INT
CELL21.IMUX.BYP.9	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B0
CELL21.IMUX.BYP.10	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B1
CELL21.IMUX.BYP.11	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B2
CELL21.IMUX.BYP.12	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SPARE_B3
CELL21.IMUX.BYP.13	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_RST_MASK_B
CELL21.IMUX.BYP.14	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_MODE_B
CELL21.IMUX.BYP.15	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN0
CELL21.IMUX.IMUX.0.DELAY	PLL1.SCANENB
CELL21.IMUX.IMUX.6.DELAY	BITSLICE18.TX_CNTVALUEIN1
CELL21.IMUX.IMUX.7.DELAY	BITSLICE18.TX_CNTVALUEIN3
CELL21.IMUX.IMUX.8.DELAY	BITSLICE18.TX_CNTVALUEIN7
CELL21.IMUX.IMUX.10.DELAY	BITSLICE18.RX_CNTVALUEIN3
CELL21.IMUX.IMUX.11.DELAY	BITSLICE18.RX_CNTVALUEIN5
CELL21.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_EN, BITSLICE_CONTROL3.CLB2RIU_WR_EN
CELL21.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA1, BITSLICE_CONTROL3.CLB2RIU_WR_DATA1
CELL21.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA5, BITSLICE_CONTROL3.CLB2RIU_WR_DATA5
CELL21.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA7, BITSLICE_CONTROL3.CLB2RIU_WR_DATA7
CELL21.IMUX.IMUX.16.DELAY	BITSLICE17.RX_CNTVALUEIN8
CELL21.IMUX.IMUX.17.DELAY	BITSLICE18.TX_T
CELL21.IMUX.IMUX.18.DELAY	BITSLICE18.TX_CE_OFD
CELL21.IMUX.IMUX.19.DELAY	BITSLICE18.RX_CE_IFD
CELL21.IMUX.IMUX.20.DELAY	BITSLICE18.RX_DATAIN1
CELL21.IMUX.IMUX.21.DELAY	BITSLICE18.CLB2PHY_FIFO_RDEN
CELL21.IMUX.IMUX.22.DELAY	BITSLICE18.TX_D0
CELL21.IMUX.IMUX.23.DELAY	BITSLICE18.TX_D1
CELL21.IMUX.IMUX.24.DELAY	BITSLICE18.TX_D2
CELL21.IMUX.IMUX.25.DELAY	BITSLICE18.TX_D3
CELL21.IMUX.IMUX.26.DELAY	BITSLICE18.TX_D4
CELL21.IMUX.IMUX.27.DELAY	BITSLICE18.TX_D5
CELL21.IMUX.IMUX.28.DELAY	BITSLICE18.TX_D6
CELL21.IMUX.IMUX.29.DELAY	BITSLICE18.TX_D7
CELL21.IMUX.IMUX.30.DELAY	BITSLICE18.TX_CNTVALUEIN0
CELL21.IMUX.IMUX.31.DELAY	BITSLICE18.TX_CNTVALUEIN2
CELL21.IMUX.IMUX.32.DELAY	BITSLICE18.TX_CNTVALUEIN4
CELL21.IMUX.IMUX.33.DELAY	BITSLICE18.TX_CNTVALUEIN5
CELL21.IMUX.IMUX.34.DELAY	BITSLICE18.TX_CNTVALUEIN6
CELL21.IMUX.IMUX.35.DELAY	BITSLICE18.TX_CNTVALUEIN8
CELL21.IMUX.IMUX.36.DELAY	BITSLICE18.RX_CNTVALUEIN0
CELL21.IMUX.IMUX.37.DELAY	BITSLICE18.RX_CNTVALUEIN1
CELL21.IMUX.IMUX.38.DELAY	BITSLICE18.RX_CNTVALUEIN2
CELL21.IMUX.IMUX.39.DELAY	BITSLICE18.RX_CNTVALUEIN4
CELL21.IMUX.IMUX.40.DELAY	BITSLICE18.RX_CNTVALUEIN6
CELL21.IMUX.IMUX.41.DELAY	BITSLICE18.RX_CNTVALUEIN7
CELL21.IMUX.IMUX.42.DELAY	BITSLICE18.RX_CNTVALUEIN8
CELL21.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA0, BITSLICE_CONTROL3.CLB2RIU_WR_DATA0
CELL21.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA2, BITSLICE_CONTROL3.CLB2RIU_WR_DATA2
CELL21.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA3, BITSLICE_CONTROL3.CLB2RIU_WR_DATA3
CELL21.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA4, BITSLICE_CONTROL3.CLB2RIU_WR_DATA4
CELL21.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA6, BITSLICE_CONTROL3.CLB2RIU_WR_DATA6
CELL22.OUT.0.TMIN	PLL1.TESTOUT0
CELL22.OUT.1.TMIN	PLL1.TESTOUT1
CELL22.OUT.2.TMIN	PLL1.TESTOUT2
CELL22.OUT.3.TMIN	PLL1.TESTOUT3
CELL22.OUT.4.TMIN	RIU_OR1.RIU_RD_DATA13
CELL22.OUT.5.TMIN	RIU_OR1.RIU_RD_DATA14
CELL22.OUT.6.TMIN	RIU_OR1.RIU_RD_DATA15
CELL22.OUT.7.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT0
CELL22.OUT.8.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT1
CELL22.OUT.9.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT2
CELL22.OUT.10.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT3
CELL22.OUT.11.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT4
CELL22.OUT.12.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT5
CELL22.OUT.13.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT6
CELL22.OUT.14.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_SCAN_OUT7
CELL22.OUT.15.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_OUT
CELL22.OUT.16.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_FLG_OUT
CELL22.OUT.17.TMIN	XIPHY_FEEDTHROUGH1.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
CELL22.OUT.18.TMIN	BITSLICE25.PHY2CLB_FIFO_EMPTY
CELL22.OUT.19.TMIN	BITSLICE25.RX_Q0
CELL22.OUT.20.TMIN	BITSLICE25.RX_Q1
CELL22.OUT.21.TMIN	BITSLICE25.RX_Q2
CELL22.OUT.22.TMIN	BITSLICE25.RX_Q3
CELL22.OUT.23.TMIN	BITSLICE25.RX_Q4
CELL22.OUT.24.TMIN	BITSLICE25.RX_Q5
CELL22.OUT.25.TMIN	BITSLICE25.RX_Q6
CELL22.OUT.26.TMIN	BITSLICE25.RX_Q7
CELL22.OUT.27.TMIN	BITSLICE25.TX_CNTVALUEOUT0
CELL22.OUT.28.TMIN	BITSLICE25.TX_CNTVALUEOUT1
CELL22.OUT.29.TMIN	BITSLICE25.TX_CNTVALUEOUT2
CELL22.OUT.30.TMIN	BITSLICE25.TX_CNTVALUEOUT3
CELL22.OUT.31.TMIN	BITSLICE25.TX_CNTVALUEOUT4
CELL22.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_SDR
CELL22.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_DIV4
CELL22.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_CLK_DIV2
CELL22.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.TXBIT_RST_B12
CELL22.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.RXBIT_RST_B12
CELL22.IMUX.BYP.0	PLL1.DADDR4
CELL22.IMUX.BYP.1	PLL1.DADDR5
CELL22.IMUX.BYP.2	PLL1.DADDR6
CELL22.IMUX.BYP.6	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN1
CELL22.IMUX.BYP.7	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN2
CELL22.IMUX.BYP.8	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN3
CELL22.IMUX.BYP.10	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN4
CELL22.IMUX.BYP.11	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN5
CELL22.IMUX.BYP.12	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN6
CELL22.IMUX.BYP.13	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_IN7
CELL22.IMUX.BYP.14	XIPHY_FEEDTHROUGH1.CLB2PHY_SCAN_EN_B
CELL22.IMUX.BYP.15	BITSLICE25.TX_LD
CELL22.IMUX.IMUX.0.DELAY	PLL1.SCANIN
CELL22.IMUX.IMUX.6.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_DIV4_CLK_SEL_B
CELL22.IMUX.IMUX.7.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CT_START_EN
CELL22.IMUX.IMUX.8.DELAY	BITSLICE25.TX_CE_OFD
CELL22.IMUX.IMUX.9.DELAY	BITSLICE25.RX_DATAIN1
CELL22.IMUX.IMUX.10.DELAY	BITSLICE25.TX_D2
CELL22.IMUX.IMUX.11.DELAY	BITSLICE25.TX_D4
CELL22.IMUX.IMUX.12.DELAY	BITSLICE25.TX_CNTVALUEIN0
CELL22.IMUX.IMUX.13.DELAY	BITSLICE25.TX_CNTVALUEIN2
CELL22.IMUX.IMUX.14.DELAY	BITSLICE25.TX_CNTVALUEIN6
CELL22.IMUX.IMUX.15.DELAY	BITSLICE25.TX_CNTVALUEIN8
CELL22.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA8, BITSLICE_CONTROL3.CLB2RIU_WR_DATA8
CELL22.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA9, BITSLICE_CONTROL3.CLB2RIU_WR_DATA9
CELL22.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA10, BITSLICE_CONTROL3.CLB2RIU_WR_DATA10
CELL22.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA11, BITSLICE_CONTROL3.CLB2RIU_WR_DATA11
CELL22.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA12, BITSLICE_CONTROL3.CLB2RIU_WR_DATA12
CELL22.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA13, BITSLICE_CONTROL3.CLB2RIU_WR_DATA13
CELL22.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA14, BITSLICE_CONTROL3.CLB2RIU_WR_DATA14
CELL22.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL2.CLB2RIU_WR_DATA15, BITSLICE_CONTROL3.CLB2RIU_WR_DATA15
CELL22.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR0, BITSLICE_CONTROL3.CLB2RIU_ADDR0
CELL22.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR1, BITSLICE_CONTROL3.CLB2RIU_ADDR1
CELL22.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR2, BITSLICE_CONTROL3.CLB2RIU_ADDR2
CELL22.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR3, BITSLICE_CONTROL3.CLB2RIU_ADDR3
CELL22.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR4, BITSLICE_CONTROL3.CLB2RIU_ADDR4
CELL22.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL2.CLB2RIU_ADDR5, BITSLICE_CONTROL3.CLB2RIU_ADDR5
CELL22.IMUX.IMUX.30.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_SDR_CLK_SEL_B
CELL22.IMUX.IMUX.31.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_TEST_DIV2_CLK_SEL_B
CELL22.IMUX.IMUX.32.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CLK_STOP_FLG_OUT
CELL22.IMUX.IMUX.33.DELAY	XIPHY_FEEDTHROUGH1.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
CELL22.IMUX.IMUX.34.DELAY	BITSLICE25.TX_T
CELL22.IMUX.IMUX.35.DELAY	BITSLICE25.RX_CE_IFD
CELL22.IMUX.IMUX.36.DELAY	BITSLICE25.CLB2PHY_FIFO_RDEN
CELL22.IMUX.IMUX.37.DELAY	BITSLICE25.TX_D0
CELL22.IMUX.IMUX.38.DELAY	BITSLICE25.TX_D1
CELL22.IMUX.IMUX.39.DELAY	BITSLICE25.TX_D3
CELL22.IMUX.IMUX.40.DELAY	BITSLICE25.TX_D5
CELL22.IMUX.IMUX.41.DELAY	BITSLICE25.TX_D6
CELL22.IMUX.IMUX.42.DELAY	BITSLICE25.TX_D7
CELL22.IMUX.IMUX.43.DELAY	BITSLICE25.TX_CNTVALUEIN1
CELL22.IMUX.IMUX.44.DELAY	BITSLICE25.TX_CNTVALUEIN3
CELL22.IMUX.IMUX.45.DELAY	BITSLICE25.TX_CNTVALUEIN4
CELL22.IMUX.IMUX.46.DELAY	BITSLICE25.TX_CNTVALUEIN5
CELL22.IMUX.IMUX.47.DELAY	BITSLICE25.TX_CNTVALUEIN7
CELL23.OUT.0.TMIN	PLL1.DOUT12
CELL23.OUT.1.TMIN	PLL1.DOUT13
CELL23.OUT.2.TMIN	PLL1.DOUT14
CELL23.OUT.3.TMIN	PLL1.DOUT15
CELL23.OUT.4.TMIN	BITSLICE25.TX_CNTVALUEOUT5
CELL23.OUT.5.TMIN	BITSLICE25.TX_CNTVALUEOUT6
CELL23.OUT.6.TMIN	BITSLICE25.TX_CNTVALUEOUT7
CELL23.OUT.7.TMIN	BITSLICE25.TX_CNTVALUEOUT8
CELL23.OUT.8.TMIN	BITSLICE20.TX_T_OUT
CELL23.OUT.9.TMIN	BITSLICE25.RX_CNTVALUEOUT0
CELL23.OUT.10.TMIN	BITSLICE25.RX_CNTVALUEOUT1
CELL23.OUT.11.TMIN	BITSLICE25.RX_CNTVALUEOUT2
CELL23.OUT.12.TMIN	BITSLICE25.RX_CNTVALUEOUT3
CELL23.OUT.13.TMIN	BITSLICE25.RX_CNTVALUEOUT4
CELL23.OUT.14.TMIN	BITSLICE25.RX_CNTVALUEOUT5
CELL23.OUT.15.TMIN	BITSLICE25.RX_CNTVALUEOUT6
CELL23.OUT.16.TMIN	BITSLICE25.RX_CNTVALUEOUT7
CELL23.OUT.17.TMIN	BITSLICE25.RX_CNTVALUEOUT8
CELL23.OUT.18.TMIN	BITSLICE19.PHY2CLB_FIFO_EMPTY
CELL23.OUT.19.TMIN	BITSLICE19.RX_Q0
CELL23.OUT.20.TMIN	BITSLICE19.RX_Q1
CELL23.OUT.21.TMIN	BITSLICE19.RX_Q2
CELL23.OUT.22.TMIN	BITSLICE19.RX_Q3
CELL23.OUT.23.TMIN	BITSLICE19.RX_Q4
CELL23.OUT.24.TMIN	BITSLICE19.RX_Q5
CELL23.OUT.25.TMIN	BITSLICE19.RX_Q6
CELL23.OUT.26.TMIN	BITSLICE19.RX_Q7
CELL23.OUT.27.TMIN	BITSLICE19.TX_CNTVALUEOUT0
CELL23.OUT.28.TMIN	BITSLICE19.TX_CNTVALUEOUT1
CELL23.OUT.29.TMIN	BITSLICE19.TX_CNTVALUEOUT2
CELL23.OUT.30.TMIN	BITSLICE19.TX_CNTVALUEOUT3
CELL23.OUT.31.TMIN	BITSLICE19.TX_CNTVALUEOUT4
CELL23.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.ODELAY_RST_B12
CELL23.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.IDELAY_RST_B12
CELL23.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK12
CELL23.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.TXBIT_RST_B6
CELL23.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.RXBIT_RST_B6
CELL23.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.ODELAY_RST_B6
CELL23.IMUX.BYP.0	PLL1.DADDR0
CELL23.IMUX.BYP.1	PLL1.DADDR1
CELL23.IMUX.BYP.2	PLL1.DADDR2
CELL23.IMUX.BYP.3	PLL1.DADDR3
CELL23.IMUX.BYP.6	BITSLICE25.TX_INC
CELL23.IMUX.BYP.7	BITSLICE25.TX_EN_VTC
CELL23.IMUX.BYP.8	BITSLICE25.TX_CE_ODELAY
CELL23.IMUX.BYP.9	BITSLICE25.RX_LD
CELL23.IMUX.BYP.10	BITSLICE25.RX_INC
CELL23.IMUX.BYP.11	BITSLICE25.RX_EN_VTC
CELL23.IMUX.BYP.12	BITSLICE25.RX_CE_IDELAY
CELL23.IMUX.BYP.13	BITSLICE25.DYN_DCI_OUT_INT
CELL23.IMUX.BYP.14	BITSLICE19.TX_LD
CELL23.IMUX.BYP.15	BITSLICE19.TX_INC
CELL23.IMUX.IMUX.6.DELAY	BITSLICE19.TX_D0
CELL23.IMUX.IMUX.7.DELAY	BITSLICE19.TX_D2
CELL23.IMUX.IMUX.8.DELAY	BITSLICE19.TX_D6
CELL23.IMUX.IMUX.9.DELAY	BITSLICE19.TX_CNTVALUEIN0
CELL23.IMUX.IMUX.10.DELAY	BITSLICE19.TX_CNTVALUEIN4
CELL23.IMUX.IMUX.11.DELAY	BITSLICE19.TX_CNTVALUEIN6
CELL23.IMUX.IMUX.12.DELAY	BITSLICE19.RX_CNTVALUEIN1
CELL23.IMUX.IMUX.13.DELAY	BITSLICE19.RX_CNTVALUEIN3
CELL23.IMUX.IMUX.14.DELAY	BITSLICE19.RX_CNTVALUEIN7
CELL23.IMUX.IMUX.15.DELAY	BITSLICE20.TX_T
CELL23.IMUX.IMUX.16.DELAY	BITSLICE25.RX_CNTVALUEIN0
CELL23.IMUX.IMUX.17.DELAY	BITSLICE25.RX_CNTVALUEIN1
CELL23.IMUX.IMUX.18.DELAY	BITSLICE25.RX_CNTVALUEIN2
CELL23.IMUX.IMUX.19.DELAY	BITSLICE25.RX_CNTVALUEIN3
CELL23.IMUX.IMUX.20.DELAY	BITSLICE25.RX_CNTVALUEIN4
CELL23.IMUX.IMUX.21.DELAY	BITSLICE25.RX_CNTVALUEIN5
CELL23.IMUX.IMUX.22.DELAY	BITSLICE25.RX_CNTVALUEIN6
CELL23.IMUX.IMUX.23.DELAY	BITSLICE25.RX_CNTVALUEIN7
CELL23.IMUX.IMUX.24.DELAY	BITSLICE25.RX_CNTVALUEIN8
CELL23.IMUX.IMUX.25.DELAY	BITSLICE19.TX_T
CELL23.IMUX.IMUX.26.DELAY	BITSLICE19.TX_CE_OFD
CELL23.IMUX.IMUX.27.DELAY	BITSLICE19.RX_CE_IFD
CELL23.IMUX.IMUX.29.DELAY	BITSLICE19.RX_DATAIN1
CELL23.IMUX.IMUX.30.DELAY	BITSLICE19.CLB2PHY_FIFO_RDEN
CELL23.IMUX.IMUX.31.DELAY	BITSLICE19.TX_D1
CELL23.IMUX.IMUX.32.DELAY	BITSLICE19.TX_D3
CELL23.IMUX.IMUX.33.DELAY	BITSLICE19.TX_D4
CELL23.IMUX.IMUX.34.DELAY	BITSLICE19.TX_D5
CELL23.IMUX.IMUX.35.DELAY	BITSLICE19.TX_D7
CELL23.IMUX.IMUX.36.DELAY	BITSLICE19.TX_CNTVALUEIN1
CELL23.IMUX.IMUX.37.DELAY	BITSLICE19.TX_CNTVALUEIN2
CELL23.IMUX.IMUX.38.DELAY	BITSLICE19.TX_CNTVALUEIN3
CELL23.IMUX.IMUX.39.DELAY	BITSLICE19.TX_CNTVALUEIN5
CELL23.IMUX.IMUX.40.DELAY	BITSLICE19.TX_CNTVALUEIN7
CELL23.IMUX.IMUX.41.DELAY	BITSLICE19.TX_CNTVALUEIN8
CELL23.IMUX.IMUX.42.DELAY	BITSLICE19.RX_CNTVALUEIN0
CELL23.IMUX.IMUX.43.DELAY	BITSLICE19.RX_CNTVALUEIN2
CELL23.IMUX.IMUX.44.DELAY	BITSLICE19.RX_CNTVALUEIN4
CELL23.IMUX.IMUX.45.DELAY	BITSLICE19.RX_CNTVALUEIN5
CELL23.IMUX.IMUX.46.DELAY	BITSLICE19.RX_CNTVALUEIN6
CELL23.IMUX.IMUX.47.DELAY	BITSLICE19.RX_CNTVALUEIN8
CELL24.OUT.0.TMIN	PLL1.DOUT8
CELL24.OUT.1.TMIN	PLL1.DOUT9
CELL24.OUT.2.TMIN	PLL1.DOUT10
CELL24.OUT.3.TMIN	PLL1.DOUT11
CELL24.OUT.4.TMIN	BITSLICE19.TX_CNTVALUEOUT5
CELL24.OUT.5.TMIN	BITSLICE19.TX_CNTVALUEOUT6
CELL24.OUT.6.TMIN	BITSLICE19.TX_CNTVALUEOUT7
CELL24.OUT.7.TMIN	BITSLICE19.TX_CNTVALUEOUT8
CELL24.OUT.8.TMIN	BITSLICE21.TX_T_OUT
CELL24.OUT.9.TMIN	BITSLICE19.RX_CNTVALUEOUT0
CELL24.OUT.10.TMIN	BITSLICE19.RX_CNTVALUEOUT1
CELL24.OUT.11.TMIN	BITSLICE19.RX_CNTVALUEOUT2
CELL24.OUT.12.TMIN	BITSLICE19.RX_CNTVALUEOUT3
CELL24.OUT.13.TMIN	BITSLICE19.RX_CNTVALUEOUT4
CELL24.OUT.14.TMIN	BITSLICE19.RX_CNTVALUEOUT5
CELL24.OUT.15.TMIN	BITSLICE19.RX_CNTVALUEOUT6
CELL24.OUT.16.TMIN	BITSLICE19.RX_CNTVALUEOUT7
CELL24.OUT.17.TMIN	BITSLICE19.RX_CNTVALUEOUT8
CELL24.OUT.18.TMIN	BITSLICE20.PHY2CLB_FIFO_EMPTY
CELL24.OUT.19.TMIN	BITSLICE20.RX_Q0
CELL24.OUT.20.TMIN	BITSLICE20.RX_Q1
CELL24.OUT.21.TMIN	BITSLICE20.RX_Q2
CELL24.OUT.22.TMIN	BITSLICE20.RX_Q3
CELL24.OUT.23.TMIN	BITSLICE20.RX_Q4
CELL24.OUT.24.TMIN	BITSLICE20.RX_Q5
CELL24.OUT.25.TMIN	BITSLICE20.RX_Q6
CELL24.OUT.26.TMIN	BITSLICE20.RX_Q7
CELL24.OUT.27.TMIN	BITSLICE20.TX_CNTVALUEOUT0
CELL24.OUT.28.TMIN	BITSLICE20.TX_CNTVALUEOUT1
CELL24.OUT.29.TMIN	BITSLICE20.TX_CNTVALUEOUT2
CELL24.OUT.30.TMIN	BITSLICE20.TX_CNTVALUEOUT3
CELL24.OUT.31.TMIN	BITSLICE20.TX_CNTVALUEOUT4
CELL24.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.IDELAY_RST_B6
CELL24.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK6
CELL24.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.TXBIT_RST_B7
CELL24.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.RXBIT_RST_B7
CELL24.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.ODELAY_RST_B7
CELL24.IMUX.BYP.0	PLL1.DI12
CELL24.IMUX.BYP.1	PLL1.DI13
CELL24.IMUX.BYP.2	PLL1.DI14
CELL24.IMUX.BYP.3	PLL1.DI15
CELL24.IMUX.BYP.6	BITSLICE19.TX_EN_VTC
CELL24.IMUX.BYP.7	BITSLICE19.TX_CE_ODELAY
CELL24.IMUX.BYP.8	BITSLICE19.RX_LD
CELL24.IMUX.BYP.9	BITSLICE19.RX_INC
CELL24.IMUX.BYP.10	BITSLICE19.RX_EN_VTC
CELL24.IMUX.BYP.11	BITSLICE19.RX_CE_IDELAY
CELL24.IMUX.BYP.12	BITSLICE19.DYN_DCI_OUT_INT
CELL24.IMUX.BYP.14	BITSLICE20.TX_LD
CELL24.IMUX.BYP.15	BITSLICE20.TX_INC
CELL24.IMUX.IMUX.0.DELAY	PLL1.DWE
CELL24.IMUX.IMUX.6.DELAY	BITSLICE20.TX_CNTVALUEIN3
CELL24.IMUX.IMUX.7.DELAY	BITSLICE20.TX_CNTVALUEIN5
CELL24.IMUX.IMUX.8.DELAY	BITSLICE20.RX_CNTVALUEIN0
CELL24.IMUX.IMUX.9.DELAY	BITSLICE20.RX_CNTVALUEIN2
CELL24.IMUX.IMUX.10.DELAY	BITSLICE20.RX_CNTVALUEIN6
CELL24.IMUX.IMUX.11.DELAY	BITSLICE20.RX_CNTVALUEIN8
CELL24.IMUX.IMUX.12.DELAY	BITSLICE21.RX_DATAIN1
CELL24.IMUX.IMUX.13.DELAY	BITSLICE21.TX_D0
CELL24.IMUX.IMUX.14.DELAY	BITSLICE21.TX_D4
CELL24.IMUX.IMUX.15.DELAY	BITSLICE21.TX_D6
CELL24.IMUX.IMUX.16.DELAY	BITSLICE20.TX_CE_OFD
CELL24.IMUX.IMUX.17.DELAY	BITSLICE20.RX_CE_IFD
CELL24.IMUX.IMUX.18.DELAY	BITSLICE20.RX_DATAIN1
CELL24.IMUX.IMUX.19.DELAY	BITSLICE20.CLB2PHY_FIFO_RDEN
CELL24.IMUX.IMUX.20.DELAY	BITSLICE20.TX_D0
CELL24.IMUX.IMUX.21.DELAY	BITSLICE20.TX_D1
CELL24.IMUX.IMUX.22.DELAY	BITSLICE20.TX_D2
CELL24.IMUX.IMUX.23.DELAY	BITSLICE20.TX_D3
CELL24.IMUX.IMUX.24.DELAY	BITSLICE20.TX_D4
CELL24.IMUX.IMUX.25.DELAY	BITSLICE20.TX_D5
CELL24.IMUX.IMUX.26.DELAY	BITSLICE20.TX_D6
CELL24.IMUX.IMUX.27.DELAY	BITSLICE20.TX_D7
CELL24.IMUX.IMUX.28.DELAY	BITSLICE20.TX_CNTVALUEIN0
CELL24.IMUX.IMUX.29.DELAY	BITSLICE20.TX_CNTVALUEIN1
CELL24.IMUX.IMUX.30.DELAY	BITSLICE20.TX_CNTVALUEIN2
CELL24.IMUX.IMUX.31.DELAY	BITSLICE20.TX_CNTVALUEIN4
CELL24.IMUX.IMUX.32.DELAY	BITSLICE20.TX_CNTVALUEIN6
CELL24.IMUX.IMUX.33.DELAY	BITSLICE20.TX_CNTVALUEIN7
CELL24.IMUX.IMUX.34.DELAY	BITSLICE20.TX_CNTVALUEIN8
CELL24.IMUX.IMUX.35.DELAY	BITSLICE20.RX_CNTVALUEIN1
CELL24.IMUX.IMUX.36.DELAY	BITSLICE20.RX_CNTVALUEIN3
CELL24.IMUX.IMUX.37.DELAY	BITSLICE20.RX_CNTVALUEIN4
CELL24.IMUX.IMUX.38.DELAY	BITSLICE20.RX_CNTVALUEIN5
CELL24.IMUX.IMUX.39.DELAY	BITSLICE20.RX_CNTVALUEIN7
CELL24.IMUX.IMUX.40.DELAY	BITSLICE21.TX_T
CELL24.IMUX.IMUX.41.DELAY	BITSLICE21.TX_CE_OFD
CELL24.IMUX.IMUX.42.DELAY	BITSLICE21.RX_CE_IFD
CELL24.IMUX.IMUX.43.DELAY	BITSLICE21.CLB2PHY_FIFO_RDEN
CELL24.IMUX.IMUX.44.DELAY	BITSLICE21.TX_D1
CELL24.IMUX.IMUX.45.DELAY	BITSLICE21.TX_D2
CELL24.IMUX.IMUX.46.DELAY	BITSLICE21.TX_D3
CELL24.IMUX.IMUX.47.DELAY	BITSLICE21.TX_D5
CELL25.OUT.0.TMIN	PLL1.DOUT4
CELL25.OUT.1.TMIN	PLL1.DOUT5
CELL25.OUT.2.TMIN	PLL1.DOUT6
CELL25.OUT.3.TMIN	PLL1.DOUT7
CELL25.OUT.4.TMIN	BITSLICE20.TX_CNTVALUEOUT5
CELL25.OUT.5.TMIN	BITSLICE20.TX_CNTVALUEOUT6
CELL25.OUT.6.TMIN	BITSLICE20.TX_CNTVALUEOUT7
CELL25.OUT.7.TMIN	BITSLICE20.TX_CNTVALUEOUT8
CELL25.OUT.8.TMIN	BITSLICE22.TX_T_OUT
CELL25.OUT.9.TMIN	BITSLICE20.RX_CNTVALUEOUT0
CELL25.OUT.10.TMIN	BITSLICE20.RX_CNTVALUEOUT1
CELL25.OUT.11.TMIN	BITSLICE20.RX_CNTVALUEOUT2
CELL25.OUT.12.TMIN	BITSLICE20.RX_CNTVALUEOUT3
CELL25.OUT.13.TMIN	BITSLICE20.RX_CNTVALUEOUT4
CELL25.OUT.14.TMIN	BITSLICE20.RX_CNTVALUEOUT5
CELL25.OUT.15.TMIN	BITSLICE20.RX_CNTVALUEOUT6
CELL25.OUT.16.TMIN	BITSLICE20.RX_CNTVALUEOUT7
CELL25.OUT.17.TMIN	BITSLICE20.RX_CNTVALUEOUT8
CELL25.OUT.18.TMIN	BITSLICE21.PHY2CLB_FIFO_EMPTY
CELL25.OUT.19.TMIN	BITSLICE21.RX_Q0
CELL25.OUT.20.TMIN	BITSLICE21.RX_Q1
CELL25.OUT.21.TMIN	BITSLICE21.RX_Q2
CELL25.OUT.22.TMIN	BITSLICE21.RX_Q3
CELL25.OUT.23.TMIN	BITSLICE21.RX_Q4
CELL25.OUT.24.TMIN	BITSLICE21.RX_Q5
CELL25.OUT.25.TMIN	BITSLICE21.RX_Q6
CELL25.OUT.26.TMIN	BITSLICE21.RX_Q7
CELL25.OUT.27.TMIN	BITSLICE21.TX_CNTVALUEOUT0
CELL25.OUT.28.TMIN	BITSLICE21.TX_CNTVALUEOUT1
CELL25.OUT.29.TMIN	BITSLICE21.TX_CNTVALUEOUT2
CELL25.OUT.30.TMIN	BITSLICE21.TX_CNTVALUEOUT3
CELL25.OUT.31.TMIN	BITSLICE21.TX_CNTVALUEOUT4
CELL25.IMUX.CTRL.0	PLL1.DCLK_B
CELL25.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.IDELAY_RST_B7
CELL25.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK7
CELL25.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.TXBIT_RST_B8
CELL25.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.RXBIT_RST_B8
CELL25.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.ODELAY_RST_B8
CELL25.IMUX.BYP.0	PLL1.DI8
CELL25.IMUX.BYP.1	PLL1.DI9
CELL25.IMUX.BYP.2	PLL1.DI10
CELL25.IMUX.BYP.3	PLL1.DI11
CELL25.IMUX.BYP.6	BITSLICE20.TX_EN_VTC
CELL25.IMUX.BYP.7	BITSLICE20.TX_CE_ODELAY
CELL25.IMUX.BYP.8	BITSLICE20.RX_LD
CELL25.IMUX.BYP.9	BITSLICE20.RX_INC
CELL25.IMUX.BYP.10	BITSLICE20.RX_EN_VTC
CELL25.IMUX.BYP.11	BITSLICE20.RX_CE_IDELAY
CELL25.IMUX.BYP.12	BITSLICE20.DYN_DCI_OUT_INT
CELL25.IMUX.BYP.13	BITSLICE21.TX_LD
CELL25.IMUX.BYP.14	BITSLICE21.TX_INC
CELL25.IMUX.BYP.15	BITSLICE21.TX_EN_VTC
CELL25.IMUX.IMUX.0.DELAY	PLL1.DEN
CELL25.IMUX.IMUX.6.DELAY	BITSLICE21.RX_CNTVALUEIN4
CELL25.IMUX.IMUX.7.DELAY	BITSLICE21.RX_CNTVALUEIN6
CELL25.IMUX.IMUX.8.DELAY	BITSLICE_T3.CNTVALUEIN1
CELL25.IMUX.IMUX.9.DELAY	BITSLICE_T3.CNTVALUEIN3
CELL25.IMUX.IMUX.10.DELAY	BITSLICE_T3.CNTVALUEIN7
CELL25.IMUX.IMUX.11.DELAY	BITSLICE_CONTROL3.CLB2RIU_NIBBLE_SEL
CELL25.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS1_3
CELL25.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS0_1
CELL25.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL3.CLB2PHY_T_B1
CELL25.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL3.CLB2PHY_T_B3
CELL25.IMUX.IMUX.16.DELAY	BITSLICE21.TX_D7
CELL25.IMUX.IMUX.18.DELAY	BITSLICE21.TX_CNTVALUEIN0
CELL25.IMUX.IMUX.19.DELAY	BITSLICE21.TX_CNTVALUEIN1
CELL25.IMUX.IMUX.20.DELAY	BITSLICE21.TX_CNTVALUEIN2
CELL25.IMUX.IMUX.21.DELAY	BITSLICE21.TX_CNTVALUEIN3
CELL25.IMUX.IMUX.22.DELAY	BITSLICE21.TX_CNTVALUEIN4
CELL25.IMUX.IMUX.23.DELAY	BITSLICE21.TX_CNTVALUEIN5
CELL25.IMUX.IMUX.24.DELAY	BITSLICE21.TX_CNTVALUEIN6
CELL25.IMUX.IMUX.25.DELAY	BITSLICE21.TX_CNTVALUEIN7
CELL25.IMUX.IMUX.26.DELAY	BITSLICE21.TX_CNTVALUEIN8
CELL25.IMUX.IMUX.27.DELAY	BITSLICE21.RX_CNTVALUEIN0
CELL25.IMUX.IMUX.28.DELAY	BITSLICE21.RX_CNTVALUEIN1
CELL25.IMUX.IMUX.29.DELAY	BITSLICE21.RX_CNTVALUEIN2
CELL25.IMUX.IMUX.30.DELAY	BITSLICE21.RX_CNTVALUEIN3
CELL25.IMUX.IMUX.31.DELAY	BITSLICE21.RX_CNTVALUEIN5
CELL25.IMUX.IMUX.32.DELAY	BITSLICE21.RX_CNTVALUEIN7
CELL25.IMUX.IMUX.33.DELAY	BITSLICE21.RX_CNTVALUEIN8
CELL25.IMUX.IMUX.34.DELAY	BITSLICE_T3.CNTVALUEIN0
CELL25.IMUX.IMUX.35.DELAY	BITSLICE_T3.CNTVALUEIN2
CELL25.IMUX.IMUX.36.DELAY	BITSLICE_T3.CNTVALUEIN4
CELL25.IMUX.IMUX.37.DELAY	BITSLICE_T3.CNTVALUEIN5
CELL25.IMUX.IMUX.38.DELAY	BITSLICE_T3.CNTVALUEIN6
CELL25.IMUX.IMUX.39.DELAY	BITSLICE_T3.CNTVALUEIN8
CELL25.IMUX.IMUX.40.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS1_0
CELL25.IMUX.IMUX.41.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS1_1
CELL25.IMUX.IMUX.42.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS1_2
CELL25.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS0_0
CELL25.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS0_2
CELL25.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL3.CLB2PHY_WRCS0_3
CELL25.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL3.CLB2PHY_T_B0
CELL25.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL3.CLB2PHY_T_B2
CELL26.OUT.0.TMIN	PLL1.DOUT0
CELL26.OUT.1.TMIN	PLL1.DOUT1
CELL26.OUT.2.TMIN	PLL1.DOUT2
CELL26.OUT.3.TMIN	PLL1.DOUT3
CELL26.OUT.4.TMIN	BITSLICE21.TX_CNTVALUEOUT5
CELL26.OUT.5.TMIN	BITSLICE21.TX_CNTVALUEOUT6
CELL26.OUT.6.TMIN	BITSLICE21.TX_CNTVALUEOUT7
CELL26.OUT.7.TMIN	BITSLICE21.TX_CNTVALUEOUT8
CELL26.OUT.8.TMIN	BITSLICE23.TX_T_OUT
CELL26.OUT.9.TMIN	BITSLICE21.RX_CNTVALUEOUT0
CELL26.OUT.10.TMIN	BITSLICE21.RX_CNTVALUEOUT1
CELL26.OUT.11.TMIN	BITSLICE21.RX_CNTVALUEOUT2
CELL26.OUT.12.TMIN	BITSLICE21.RX_CNTVALUEOUT3
CELL26.OUT.13.TMIN	BITSLICE21.RX_CNTVALUEOUT4
CELL26.OUT.14.TMIN	BITSLICE21.RX_CNTVALUEOUT5
CELL26.OUT.15.TMIN	BITSLICE21.RX_CNTVALUEOUT6
CELL26.OUT.16.TMIN	BITSLICE21.RX_CNTVALUEOUT7
CELL26.OUT.17.TMIN	BITSLICE21.RX_CNTVALUEOUT8
CELL26.OUT.18.TMIN	BITSLICE_T3.CNTVALUEOUT0
CELL26.OUT.19.TMIN	BITSLICE_T3.CNTVALUEOUT1
CELL26.OUT.20.TMIN	BITSLICE_T3.CNTVALUEOUT2
CELL26.OUT.21.TMIN	BITSLICE_T3.CNTVALUEOUT3
CELL26.OUT.22.TMIN	BITSLICE_T3.CNTVALUEOUT4
CELL26.OUT.23.TMIN	BITSLICE_T3.CNTVALUEOUT5
CELL26.OUT.24.TMIN	BITSLICE_T3.CNTVALUEOUT6
CELL26.OUT.25.TMIN	BITSLICE_T3.CNTVALUEOUT7
CELL26.OUT.26.TMIN	BITSLICE_T3.CNTVALUEOUT8
CELL26.OUT.27.TMIN	BITSLICE_CONTROL3.PHY2CLB_PHY_RDY
CELL26.OUT.28.TMIN	BITSLICE_CONTROL3.MASTER_PD_OUT
CELL26.OUT.29.TMIN	BITSLICE_CONTROL3.PHY2CLB_FIXDLY_RDY
CELL26.OUT.30.TMIN	BITSLICE_CONTROL3.CTRL_DLY_TEST_OUT
CELL26.OUT.31.TMIN	BITSLICE24.TX_T_OUT
CELL26.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.IDELAY_RST_B8
CELL26.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK8
CELL26.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.TRISTATE_ODELAY_RST_B1
CELL26.IMUX.CTRL.6	BITSLICE_CONTROL3.REFCLK
CELL26.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.CTRL_RST_B_UPP
CELL26.IMUX.BYP.0	PLL1.DI4
CELL26.IMUX.BYP.1	PLL1.DI5
CELL26.IMUX.BYP.2	PLL1.DI6
CELL26.IMUX.BYP.3	PLL1.DI7
CELL26.IMUX.BYP.6	BITSLICE21.TX_CE_ODELAY
CELL26.IMUX.BYP.8	BITSLICE21.RX_LD
CELL26.IMUX.BYP.9	BITSLICE21.RX_INC
CELL26.IMUX.BYP.10	BITSLICE21.RX_EN_VTC
CELL26.IMUX.BYP.11	BITSLICE21.RX_CE_IDELAY
CELL26.IMUX.BYP.12	BITSLICE21.DYN_DCI_OUT_INT
CELL26.IMUX.BYP.13	BITSLICE_T3.CE_OFD
CELL26.IMUX.BYP.14	BITSLICE_T3.LD
CELL26.IMUX.BYP.15	BITSLICE_T3.INC
CELL26.IMUX.IMUX.0.DELAY	PLL1.PWRDWN
CELL26.IMUX.IMUX.6.DELAY	BITSLICE22.RX_DATAIN1
CELL26.IMUX.IMUX.7.DELAY	BITSLICE22.TX_D0
CELL26.IMUX.IMUX.8.DELAY	BITSLICE22.TX_D4
CELL26.IMUX.IMUX.9.DELAY	BITSLICE22.TX_D6
CELL26.IMUX.IMUX.10.DELAY	BITSLICE22.TX_CNTVALUEIN2
CELL26.IMUX.IMUX.11.DELAY	BITSLICE22.TX_CNTVALUEIN4
CELL26.IMUX.IMUX.12.DELAY	BITSLICE22.TX_CNTVALUEIN7
CELL26.IMUX.IMUX.13.DELAY	BITSLICE22.RX_CNTVALUEIN0
CELL26.IMUX.IMUX.14.DELAY	BITSLICE22.RX_CNTVALUEIN4
CELL26.IMUX.IMUX.15.DELAY	BITSLICE22.RX_CNTVALUEIN6
CELL26.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDEN0
CELL26.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDEN1
CELL26.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDEN2
CELL26.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDEN3
CELL26.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS1_0
CELL26.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS1_1
CELL26.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS1_2
CELL26.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS1_3
CELL26.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS0_0
CELL26.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS0_1
CELL26.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS0_2
CELL26.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL3.CLB2PHY_RDCS0_3
CELL26.IMUX.IMUX.28.DELAY	BITSLICE22.TX_T
CELL26.IMUX.IMUX.29.DELAY	BITSLICE22.TX_CE_OFD
CELL26.IMUX.IMUX.30.DELAY	BITSLICE22.RX_CE_IFD
CELL26.IMUX.IMUX.31.DELAY	BITSLICE22.CLB2PHY_FIFO_RDEN
CELL26.IMUX.IMUX.32.DELAY	BITSLICE22.TX_D1
CELL26.IMUX.IMUX.33.DELAY	BITSLICE22.TX_D2
CELL26.IMUX.IMUX.34.DELAY	BITSLICE22.TX_D3
CELL26.IMUX.IMUX.35.DELAY	BITSLICE22.TX_D5
CELL26.IMUX.IMUX.36.DELAY	BITSLICE22.TX_D7
CELL26.IMUX.IMUX.37.DELAY	BITSLICE22.TX_CNTVALUEIN0
CELL26.IMUX.IMUX.38.DELAY	BITSLICE22.TX_CNTVALUEIN1
CELL26.IMUX.IMUX.39.DELAY	BITSLICE22.TX_CNTVALUEIN3
CELL26.IMUX.IMUX.40.DELAY	BITSLICE22.TX_CNTVALUEIN5
CELL26.IMUX.IMUX.41.DELAY	BITSLICE22.TX_CNTVALUEIN6
CELL26.IMUX.IMUX.43.DELAY	BITSLICE22.TX_CNTVALUEIN8
CELL26.IMUX.IMUX.44.DELAY	BITSLICE22.RX_CNTVALUEIN1
CELL26.IMUX.IMUX.45.DELAY	BITSLICE22.RX_CNTVALUEIN2
CELL26.IMUX.IMUX.46.DELAY	BITSLICE22.RX_CNTVALUEIN3
CELL26.IMUX.IMUX.47.DELAY	BITSLICE22.RX_CNTVALUEIN5
CELL27.OUT.0.TMIN	PLL1.DRDY
CELL27.OUT.1.TMIN	PLL1.LOCKED
CELL27.OUT.2.TMIN	PLL1.TESTOUT36
CELL27.OUT.3.TMIN	PLL1.SCANOUT
CELL27.OUT.4.TMIN	BITSLICE22.PHY2CLB_FIFO_EMPTY
CELL27.OUT.5.TMIN	BITSLICE22.RX_Q0
CELL27.OUT.6.TMIN	BITSLICE22.RX_Q1
CELL27.OUT.7.TMIN	BITSLICE22.RX_Q2
CELL27.OUT.8.TMIN	BITSLICE22.RX_Q3
CELL27.OUT.9.TMIN	BITSLICE22.RX_Q4
CELL27.OUT.10.TMIN	BITSLICE22.RX_Q5
CELL27.OUT.11.TMIN	BITSLICE22.RX_Q6
CELL27.OUT.12.TMIN	BITSLICE22.RX_Q7
CELL27.OUT.13.TMIN	BITSLICE22.TX_CNTVALUEOUT0
CELL27.OUT.14.TMIN	BITSLICE22.TX_CNTVALUEOUT1
CELL27.OUT.15.TMIN	BITSLICE22.TX_CNTVALUEOUT2
CELL27.OUT.16.TMIN	BITSLICE22.TX_CNTVALUEOUT3
CELL27.OUT.17.TMIN	BITSLICE22.TX_CNTVALUEOUT4
CELL27.OUT.18.TMIN	BITSLICE22.TX_CNTVALUEOUT5
CELL27.OUT.19.TMIN	BITSLICE22.TX_CNTVALUEOUT6
CELL27.OUT.20.TMIN	BITSLICE22.TX_CNTVALUEOUT7
CELL27.OUT.21.TMIN	BITSLICE22.TX_CNTVALUEOUT8
CELL27.OUT.22.TMIN	BITSLICE25.TX_T_OUT
CELL27.OUT.23.TMIN	BITSLICE22.RX_CNTVALUEOUT0
CELL27.OUT.24.TMIN	BITSLICE22.RX_CNTVALUEOUT1
CELL27.OUT.25.TMIN	BITSLICE22.RX_CNTVALUEOUT2
CELL27.OUT.26.TMIN	BITSLICE22.RX_CNTVALUEOUT3
CELL27.OUT.27.TMIN	BITSLICE22.RX_CNTVALUEOUT4
CELL27.OUT.28.TMIN	BITSLICE22.RX_CNTVALUEOUT5
CELL27.OUT.29.TMIN	BITSLICE22.RX_CNTVALUEOUT6
CELL27.OUT.30.TMIN	BITSLICE22.RX_CNTVALUEOUT7
CELL27.OUT.31.TMIN	BITSLICE22.RX_CNTVALUEOUT8
CELL27.IMUX.CTRL.0	PLL1.SCANCLK_B
CELL27.IMUX.CTRL.2	BITSLICE_CONTROL3.RIU_CLK, XIPHY_FEEDTHROUGH1.CLB2PHY_CTRL_CLK_UPP
CELL27.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.TXBIT_RST_B9
CELL27.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.RXBIT_RST_B9
CELL27.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.ODELAY_RST_B9
CELL27.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.IDELAY_RST_B9
CELL27.IMUX.BYP.0	PLL1.DI0
CELL27.IMUX.BYP.1	PLL1.DI1
CELL27.IMUX.BYP.2	PLL1.DI2
CELL27.IMUX.BYP.3	PLL1.DI3
CELL27.IMUX.BYP.6	BITSLICE_T3.CE_ODELAY
CELL27.IMUX.BYP.7	BITSLICE_CONTROL3.EN_VTC
CELL27.IMUX.BYP.8	BITSLICE_CONTROL3.CTRL_DLY_TEST_IN
CELL27.IMUX.BYP.9	BITSLICE22.TX_LD
CELL27.IMUX.BYP.10	BITSLICE22.TX_INC
CELL27.IMUX.BYP.11	BITSLICE22.TX_EN_VTC
CELL27.IMUX.BYP.12	BITSLICE22.TX_CE_ODELAY
CELL27.IMUX.BYP.13	BITSLICE22.RX_LD
CELL27.IMUX.BYP.14	BITSLICE22.RX_INC
CELL27.IMUX.BYP.15	BITSLICE22.RX_EN_VTC
CELL27.IMUX.IMUX.0.DELAY	PLL1.RST
CELL27.IMUX.IMUX.6.DELAY	BITSLICE23.TX_CNTVALUEIN0
CELL27.IMUX.IMUX.7.DELAY	BITSLICE23.TX_CNTVALUEIN2
CELL27.IMUX.IMUX.8.DELAY	BITSLICE23.TX_CNTVALUEIN6
CELL27.IMUX.IMUX.9.DELAY	BITSLICE23.TX_CNTVALUEIN8
CELL27.IMUX.IMUX.10.DELAY	BITSLICE23.RX_CNTVALUEIN3
CELL27.IMUX.IMUX.11.DELAY	BITSLICE23.RX_CNTVALUEIN5
CELL27.IMUX.IMUX.12.DELAY	BITSLICE24.TX_T
CELL27.IMUX.IMUX.13.DELAY	BITSLICE24.RX_CE_IFD
CELL27.IMUX.IMUX.14.DELAY	BITSLICE24.TX_D1
CELL27.IMUX.IMUX.15.DELAY	BITSLICE24.TX_D3
CELL27.IMUX.IMUX.16.DELAY	BITSLICE22.RX_CNTVALUEIN7
CELL27.IMUX.IMUX.17.DELAY	BITSLICE22.RX_CNTVALUEIN8
CELL27.IMUX.IMUX.18.DELAY	BITSLICE23.TX_T
CELL27.IMUX.IMUX.19.DELAY	BITSLICE23.TX_CE_OFD
CELL27.IMUX.IMUX.20.DELAY	BITSLICE23.RX_CE_IFD
CELL27.IMUX.IMUX.21.DELAY	BITSLICE23.RX_DATAIN1
CELL27.IMUX.IMUX.22.DELAY	BITSLICE23.CLB2PHY_FIFO_RDEN
CELL27.IMUX.IMUX.23.DELAY	BITSLICE23.TX_D5
CELL27.IMUX.IMUX.24.DELAY	BITSLICE23.TX_D4
CELL27.IMUX.IMUX.25.DELAY	BITSLICE23.TX_D3
CELL27.IMUX.IMUX.26.DELAY	BITSLICE23.TX_D2
CELL27.IMUX.IMUX.27.DELAY	BITSLICE23.TX_D1
CELL27.IMUX.IMUX.28.DELAY	BITSLICE23.TX_D0
CELL27.IMUX.IMUX.29.DELAY	BITSLICE23.TX_D6
CELL27.IMUX.IMUX.30.DELAY	BITSLICE23.TX_D7
CELL27.IMUX.IMUX.31.DELAY	BITSLICE23.TX_CNTVALUEIN1
CELL27.IMUX.IMUX.32.DELAY	BITSLICE23.TX_CNTVALUEIN3
CELL27.IMUX.IMUX.33.DELAY	BITSLICE23.TX_CNTVALUEIN4
CELL27.IMUX.IMUX.34.DELAY	BITSLICE23.TX_CNTVALUEIN5
CELL27.IMUX.IMUX.35.DELAY	BITSLICE23.TX_CNTVALUEIN7
CELL27.IMUX.IMUX.36.DELAY	BITSLICE23.RX_CNTVALUEIN0
CELL27.IMUX.IMUX.37.DELAY	BITSLICE23.RX_CNTVALUEIN1
CELL27.IMUX.IMUX.38.DELAY	BITSLICE23.RX_CNTVALUEIN2
CELL27.IMUX.IMUX.39.DELAY	BITSLICE23.RX_CNTVALUEIN4
CELL27.IMUX.IMUX.40.DELAY	BITSLICE23.RX_CNTVALUEIN6
CELL27.IMUX.IMUX.41.DELAY	BITSLICE23.RX_CNTVALUEIN7
CELL27.IMUX.IMUX.42.DELAY	BITSLICE23.RX_CNTVALUEIN8
CELL27.IMUX.IMUX.43.DELAY	BITSLICE24.TX_CE_OFD
CELL27.IMUX.IMUX.44.DELAY	BITSLICE24.RX_DATAIN1
CELL27.IMUX.IMUX.45.DELAY	BITSLICE24.CLB2PHY_FIFO_RDEN
CELL27.IMUX.IMUX.46.DELAY	BITSLICE24.TX_D0
CELL27.IMUX.IMUX.47.DELAY	BITSLICE24.TX_D2
CELL28.OUT.4.TMIN	BITSLICE23.PHY2CLB_FIFO_EMPTY
CELL28.OUT.5.TMIN	BITSLICE23.RX_Q0
CELL28.OUT.6.TMIN	BITSLICE23.RX_Q1
CELL28.OUT.7.TMIN	BITSLICE23.RX_Q2
CELL28.OUT.8.TMIN	BITSLICE23.RX_Q3
CELL28.OUT.9.TMIN	BITSLICE23.RX_Q4
CELL28.OUT.10.TMIN	BITSLICE23.RX_Q5
CELL28.OUT.11.TMIN	BITSLICE23.RX_Q6
CELL28.OUT.12.TMIN	BITSLICE23.RX_Q7
CELL28.OUT.13.TMIN	BITSLICE23.TX_CNTVALUEOUT0
CELL28.OUT.14.TMIN	BITSLICE23.TX_CNTVALUEOUT1
CELL28.OUT.15.TMIN	BITSLICE23.TX_CNTVALUEOUT2
CELL28.OUT.16.TMIN	BITSLICE23.TX_CNTVALUEOUT3
CELL28.OUT.17.TMIN	BITSLICE23.TX_CNTVALUEOUT4
CELL28.OUT.18.TMIN	BITSLICE23.TX_CNTVALUEOUT5
CELL28.OUT.19.TMIN	BITSLICE23.TX_CNTVALUEOUT6
CELL28.OUT.20.TMIN	BITSLICE23.TX_CNTVALUEOUT7
CELL28.OUT.21.TMIN	BITSLICE23.TX_CNTVALUEOUT8
CELL28.OUT.23.TMIN	BITSLICE23.RX_CNTVALUEOUT0
CELL28.OUT.24.TMIN	BITSLICE23.RX_CNTVALUEOUT1
CELL28.OUT.25.TMIN	BITSLICE23.RX_CNTVALUEOUT2
CELL28.OUT.26.TMIN	BITSLICE23.RX_CNTVALUEOUT3
CELL28.OUT.27.TMIN	BITSLICE23.RX_CNTVALUEOUT4
CELL28.OUT.28.TMIN	BITSLICE23.RX_CNTVALUEOUT5
CELL28.OUT.29.TMIN	BITSLICE23.RX_CNTVALUEOUT6
CELL28.OUT.30.TMIN	BITSLICE23.RX_CNTVALUEOUT7
CELL28.OUT.31.TMIN	BITSLICE23.RX_CNTVALUEOUT8
CELL28.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK9
CELL28.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.TXBIT_RST_B10
CELL28.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.RXBIT_RST_B10
CELL28.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.ODELAY_RST_B10
CELL28.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.IDELAY_RST_B10
CELL28.IMUX.BYP.6	BITSLICE22.RX_CE_IDELAY
CELL28.IMUX.BYP.7	BITSLICE22.DYN_DCI_OUT_INT
CELL28.IMUX.BYP.8	BITSLICE23.TX_LD
CELL28.IMUX.BYP.9	BITSLICE23.TX_INC
CELL28.IMUX.BYP.10	BITSLICE23.TX_EN_VTC
CELL28.IMUX.BYP.11	BITSLICE23.TX_CE_ODELAY
CELL28.IMUX.BYP.12	BITSLICE23.RX_LD
CELL28.IMUX.BYP.13	BITSLICE23.RX_INC
CELL28.IMUX.BYP.14	BITSLICE23.RX_EN_VTC
CELL28.IMUX.BYP.15	BITSLICE23.RX_CE_IDELAY
CELL28.IMUX.IMUX.0.DELAY	BUFGCE_DIV0.RST_PRE_OPTINV
CELL28.IMUX.IMUX.6.DELAY	BITSLICE24.TX_D5
CELL28.IMUX.IMUX.7.DELAY	BITSLICE24.TX_D6
CELL28.IMUX.IMUX.8.DELAY	BITSLICE24.TX_D7
CELL28.IMUX.IMUX.9.DELAY	BITSLICE24.TX_CNTVALUEIN0
CELL28.IMUX.IMUX.10.DELAY	BITSLICE24.TX_CNTVALUEIN1
CELL28.IMUX.IMUX.11.DELAY	BITSLICE24.TX_CNTVALUEIN2
CELL28.IMUX.IMUX.12.DELAY	BITSLICE24.TX_CNTVALUEIN3
CELL28.IMUX.IMUX.13.DELAY	BITSLICE24.TX_CNTVALUEIN4
CELL28.IMUX.IMUX.14.DELAY	BITSLICE24.TX_CNTVALUEIN5
CELL28.IMUX.IMUX.15.DELAY	BITSLICE24.TX_CNTVALUEIN6
CELL28.IMUX.IMUX.16.DELAY	BITSLICE24.TX_D4
CELL28.IMUX.IMUX.17.DELAY	BUFCE_ROW_CMT0.CE_PRE_OPTINV
CELL28.IMUX.IMUX.18.DELAY	BUFCE_ROW_CMT1.CE_PRE_OPTINV
CELL28.IMUX.IMUX.19.DELAY	BUFCE_ROW_CMT2.CE_PRE_OPTINV
CELL28.IMUX.IMUX.20.DELAY	BUFCE_ROW_CMT3.CE_PRE_OPTINV
CELL28.IMUX.IMUX.21.DELAY	BUFCE_ROW_CMT4.CE_PRE_OPTINV
CELL28.IMUX.IMUX.22.DELAY	BUFCE_ROW_CMT5.CE_PRE_OPTINV
CELL28.IMUX.IMUX.23.DELAY	BUFCE_ROW_CMT6.CE_PRE_OPTINV
CELL28.IMUX.IMUX.24.DELAY	BUFCE_ROW_CMT7.CE_PRE_OPTINV
CELL28.IMUX.IMUX.25.DELAY	BUFCE_ROW_CMT8.CE_PRE_OPTINV
CELL28.IMUX.IMUX.26.DELAY	BUFCE_ROW_CMT9.CE_PRE_OPTINV
CELL28.IMUX.IMUX.27.DELAY	BUFCE_ROW_CMT10.CE_PRE_OPTINV
CELL28.IMUX.IMUX.28.DELAY	BUFCE_ROW_CMT11.CE_PRE_OPTINV
CELL28.IMUX.IMUX.29.DELAY	BUFCE_ROW_CMT12.CE_PRE_OPTINV
CELL28.IMUX.IMUX.30.DELAY	BUFCE_ROW_CMT13.CE_PRE_OPTINV
CELL28.IMUX.IMUX.31.DELAY	BUFCE_ROW_CMT14.CE_PRE_OPTINV
CELL28.IMUX.IMUX.32.DELAY	BUFCE_ROW_CMT15.CE_PRE_OPTINV
CELL28.IMUX.IMUX.33.DELAY	BUFCE_ROW_CMT16.CE_PRE_OPTINV
CELL28.IMUX.IMUX.34.DELAY	BUFCE_ROW_CMT17.CE_PRE_OPTINV
CELL28.IMUX.IMUX.35.DELAY	BUFCE_ROW_CMT18.CE_PRE_OPTINV
CELL28.IMUX.IMUX.36.DELAY	BUFCE_ROW_CMT19.CE_PRE_OPTINV
CELL28.IMUX.IMUX.37.DELAY	BUFCE_ROW_CMT20.CE_PRE_OPTINV
CELL28.IMUX.IMUX.38.DELAY	BUFCE_ROW_CMT21.CE_PRE_OPTINV
CELL28.IMUX.IMUX.39.DELAY	BUFCE_ROW_CMT22.CE_PRE_OPTINV
CELL28.IMUX.IMUX.40.DELAY	BUFCE_ROW_CMT23.CE_PRE_OPTINV
CELL28.IMUX.IMUX.41.DELAY	BUFGCE_DIV0.CE_PRE_OPTINV
CELL28.IMUX.IMUX.42.DELAY	BUFGCE_DIV1.CE_PRE_OPTINV
CELL28.IMUX.IMUX.43.DELAY	BUFGCE_DIV2.CE_PRE_OPTINV
CELL28.IMUX.IMUX.44.DELAY	BUFGCE_DIV3.CE_PRE_OPTINV
CELL28.IMUX.IMUX.45.DELAY	BUFGCTRL0.SEL1_PRE_OPTINV
CELL28.IMUX.IMUX.46.DELAY	BUFGCTRL1.SEL1_PRE_OPTINV
CELL28.IMUX.IMUX.47.DELAY	BUFGCTRL2.SEL1_PRE_OPTINV
CELL29.OUT.4.TMIN	BITSLICE24.PHY2CLB_FIFO_EMPTY
CELL29.OUT.5.TMIN	BITSLICE24.RX_Q0
CELL29.OUT.6.TMIN	BITSLICE24.RX_Q1
CELL29.OUT.7.TMIN	BITSLICE24.RX_Q2
CELL29.OUT.8.TMIN	BITSLICE24.RX_Q3
CELL29.OUT.9.TMIN	BITSLICE24.RX_Q4
CELL29.OUT.10.TMIN	BITSLICE24.RX_Q5
CELL29.OUT.11.TMIN	BITSLICE24.RX_Q6
CELL29.OUT.12.TMIN	BITSLICE24.RX_Q7
CELL29.OUT.13.TMIN	BITSLICE24.TX_CNTVALUEOUT0
CELL29.OUT.14.TMIN	BITSLICE24.TX_CNTVALUEOUT1
CELL29.OUT.15.TMIN	BITSLICE24.TX_CNTVALUEOUT2
CELL29.OUT.16.TMIN	BITSLICE24.TX_CNTVALUEOUT3
CELL29.OUT.17.TMIN	BITSLICE24.TX_CNTVALUEOUT4
CELL29.OUT.18.TMIN	BITSLICE24.TX_CNTVALUEOUT5
CELL29.OUT.19.TMIN	BITSLICE24.TX_CNTVALUEOUT6
CELL29.OUT.20.TMIN	BITSLICE24.TX_CNTVALUEOUT7
CELL29.OUT.21.TMIN	BITSLICE24.TX_CNTVALUEOUT8
CELL29.OUT.23.TMIN	BITSLICE24.RX_CNTVALUEOUT0
CELL29.OUT.24.TMIN	BITSLICE24.RX_CNTVALUEOUT1
CELL29.OUT.25.TMIN	BITSLICE24.RX_CNTVALUEOUT2
CELL29.OUT.26.TMIN	BITSLICE24.RX_CNTVALUEOUT3
CELL29.OUT.27.TMIN	BITSLICE24.RX_CNTVALUEOUT4
CELL29.OUT.28.TMIN	BITSLICE24.RX_CNTVALUEOUT5
CELL29.OUT.29.TMIN	BITSLICE24.RX_CNTVALUEOUT6
CELL29.OUT.30.TMIN	BITSLICE24.RX_CNTVALUEOUT7
CELL29.OUT.31.TMIN	BITSLICE24.RX_CNTVALUEOUT8
CELL29.IMUX.CTRL.2	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK10
CELL29.IMUX.CTRL.3	XIPHY_FEEDTHROUGH1.TXBIT_RST_B11
CELL29.IMUX.CTRL.4	XIPHY_FEEDTHROUGH1.RXBIT_RST_B11
CELL29.IMUX.CTRL.5	XIPHY_FEEDTHROUGH1.ODELAY_RST_B11
CELL29.IMUX.CTRL.6	XIPHY_FEEDTHROUGH1.IDELAY_RST_B11
CELL29.IMUX.CTRL.7	XIPHY_FEEDTHROUGH1.CLB2PHY_FIFO_CLK11
CELL29.IMUX.BYP.6	BITSLICE23.DYN_DCI_OUT_INT
CELL29.IMUX.BYP.7	BITSLICE24.TX_LD
CELL29.IMUX.BYP.8	BITSLICE24.TX_INC
CELL29.IMUX.BYP.9	BITSLICE24.TX_EN_VTC
CELL29.IMUX.BYP.10	BITSLICE24.TX_CE_ODELAY
CELL29.IMUX.BYP.11	BITSLICE24.RX_LD
CELL29.IMUX.BYP.12	BITSLICE24.RX_INC
CELL29.IMUX.BYP.13	BITSLICE24.RX_EN_VTC
CELL29.IMUX.BYP.14	BITSLICE24.RX_CE_IDELAY
CELL29.IMUX.BYP.15	BITSLICE24.DYN_DCI_OUT_INT
CELL29.IMUX.IMUX.0.DELAY	BUFGCE_DIV1.RST_PRE_OPTINV
CELL29.IMUX.IMUX.6.DELAY	BITSLICE24.TX_CNTVALUEIN8
CELL29.IMUX.IMUX.7.DELAY	BITSLICE24.RX_CNTVALUEIN0
CELL29.IMUX.IMUX.8.DELAY	BITSLICE24.RX_CNTVALUEIN1
CELL29.IMUX.IMUX.9.DELAY	BITSLICE24.RX_CNTVALUEIN2
CELL29.IMUX.IMUX.10.DELAY	BITSLICE24.RX_CNTVALUEIN3
CELL29.IMUX.IMUX.11.DELAY	BITSLICE24.RX_CNTVALUEIN4
CELL29.IMUX.IMUX.12.DELAY	BITSLICE24.RX_CNTVALUEIN5
CELL29.IMUX.IMUX.13.DELAY	BITSLICE24.RX_CNTVALUEIN6
CELL29.IMUX.IMUX.14.DELAY	BITSLICE24.RX_CNTVALUEIN7
CELL29.IMUX.IMUX.15.DELAY	BITSLICE24.RX_CNTVALUEIN8
CELL29.IMUX.IMUX.16.DELAY	BITSLICE24.TX_CNTVALUEIN7
CELL29.IMUX.IMUX.17.DELAY	BUFGCTRL3.SEL1_PRE_OPTINV
CELL29.IMUX.IMUX.18.DELAY	BUFGCTRL4.SEL1_PRE_OPTINV
CELL29.IMUX.IMUX.19.DELAY	BUFGCTRL5.SEL1_PRE_OPTINV
CELL29.IMUX.IMUX.20.DELAY	BUFGCTRL6.SEL1_PRE_OPTINV
CELL29.IMUX.IMUX.21.DELAY	BUFGCTRL7.SEL1_PRE_OPTINV
CELL29.IMUX.IMUX.22.DELAY	BUFGCTRL0.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.23.DELAY	BUFGCTRL1.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.24.DELAY	BUFGCTRL2.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.25.DELAY	BUFGCTRL3.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.26.DELAY	BUFGCTRL4.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.27.DELAY	BUFGCTRL5.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.28.DELAY	BUFGCTRL6.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.29.DELAY	BUFGCTRL7.SEL0_PRE_OPTINV
CELL29.IMUX.IMUX.30.DELAY	BUFGCTRL0.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.31.DELAY	BUFGCTRL1.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.32.DELAY	BUFGCTRL2.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.33.DELAY	BUFGCTRL3.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.34.DELAY	BUFGCTRL4.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.35.DELAY	BUFGCTRL5.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.36.DELAY	BUFGCTRL6.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.37.DELAY	BUFGCTRL7.IGNORE1_PRE_OPTINV
CELL29.IMUX.IMUX.38.DELAY	BUFGCTRL0.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.39.DELAY	BUFGCTRL1.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.40.DELAY	BUFGCTRL2.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.41.DELAY	BUFGCTRL3.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.42.DELAY	BUFGCTRL4.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.43.DELAY	BUFGCTRL5.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.44.DELAY	BUFGCTRL6.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.45.DELAY	BUFGCTRL7.IGNORE0_PRE_OPTINV
CELL29.IMUX.IMUX.46.DELAY	BUFGCTRL0.CE1_PRE_OPTINV
CELL29.IMUX.IMUX.47.DELAY	BUFGCTRL1.CE1_PRE_OPTINV
CELL30.OUT.4.TMIN	BITSLICE26.PHY2CLB_FIFO_EMPTY
CELL30.OUT.5.TMIN	BITSLICE26.RX_Q0
CELL30.OUT.6.TMIN	BITSLICE26.RX_Q1
CELL30.OUT.7.TMIN	BITSLICE26.RX_Q2
CELL30.OUT.8.TMIN	BITSLICE26.RX_Q3
CELL30.OUT.9.TMIN	BITSLICE26.RX_Q4
CELL30.OUT.10.TMIN	BITSLICE26.RX_Q5
CELL30.OUT.11.TMIN	BITSLICE26.RX_Q6
CELL30.OUT.12.TMIN	BITSLICE26.RX_Q7
CELL30.OUT.13.TMIN	BITSLICE26.TX_CNTVALUEOUT0
CELL30.OUT.14.TMIN	BITSLICE26.TX_CNTVALUEOUT1
CELL30.OUT.15.TMIN	BITSLICE26.TX_CNTVALUEOUT2
CELL30.OUT.16.TMIN	BITSLICE26.TX_CNTVALUEOUT3
CELL30.OUT.17.TMIN	BITSLICE26.TX_CNTVALUEOUT4
CELL30.OUT.18.TMIN	BITSLICE26.TX_CNTVALUEOUT5
CELL30.OUT.19.TMIN	BITSLICE26.TX_CNTVALUEOUT6
CELL30.OUT.20.TMIN	BITSLICE26.TX_CNTVALUEOUT7
CELL30.OUT.21.TMIN	BITSLICE26.TX_CNTVALUEOUT8
CELL30.OUT.22.TMIN	BITSLICE26.TX_T_OUT
CELL30.OUT.23.TMIN	BITSLICE26.RX_CNTVALUEOUT0
CELL30.OUT.24.TMIN	BITSLICE26.RX_CNTVALUEOUT1
CELL30.OUT.25.TMIN	BITSLICE26.RX_CNTVALUEOUT2
CELL30.OUT.26.TMIN	BITSLICE26.RX_CNTVALUEOUT3
CELL30.OUT.27.TMIN	BITSLICE26.RX_CNTVALUEOUT4
CELL30.OUT.28.TMIN	BITSLICE26.RX_CNTVALUEOUT5
CELL30.OUT.29.TMIN	BITSLICE26.RX_CNTVALUEOUT6
CELL30.OUT.30.TMIN	BITSLICE26.RX_CNTVALUEOUT7
CELL30.OUT.31.TMIN	BITSLICE26.RX_CNTVALUEOUT8
CELL30.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.TXBIT_TRI_RST_B0
CELL30.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.TXBIT_RST_B0
CELL30.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.RXBIT_RST_B0
CELL30.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.ODELAY_RST_B0
CELL30.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.IDELAY_RST_B0
CELL30.IMUX.BYP.6	BITSLICE_T4.EN_VTC
CELL30.IMUX.BYP.7	BITSLICE26.TX_LD
CELL30.IMUX.BYP.8	BITSLICE26.TX_INC
CELL30.IMUX.BYP.9	BITSLICE26.TX_EN_VTC
CELL30.IMUX.BYP.10	BITSLICE26.TX_CE_ODELAY
CELL30.IMUX.BYP.11	BITSLICE26.RX_LD
CELL30.IMUX.BYP.12	BITSLICE26.RX_INC
CELL30.IMUX.BYP.13	BITSLICE26.RX_EN_VTC
CELL30.IMUX.BYP.14	BITSLICE26.RX_CE_IDELAY
CELL30.IMUX.BYP.15	BITSLICE26.DYN_DCI_OUT_INT
CELL30.IMUX.IMUX.0.DELAY	BUFGCE_DIV2.RST_PRE_OPTINV
CELL30.IMUX.IMUX.6.DELAY	BITSLICE26.TX_CE_OFD
CELL30.IMUX.IMUX.7.DELAY	BITSLICE26.RX_CE_IFD
CELL30.IMUX.IMUX.8.DELAY	BITSLICE26.RX_DATAIN1
CELL30.IMUX.IMUX.9.DELAY	BITSLICE26.CLB2PHY_FIFO_RDEN
CELL30.IMUX.IMUX.10.DELAY	BITSLICE26.TX_D7
CELL30.IMUX.IMUX.11.DELAY	BITSLICE26.TX_D6
CELL30.IMUX.IMUX.12.DELAY	BITSLICE26.TX_D5
CELL30.IMUX.IMUX.13.DELAY	BITSLICE26.TX_D4
CELL30.IMUX.IMUX.14.DELAY	BITSLICE26.TX_D3
CELL30.IMUX.IMUX.15.DELAY	BITSLICE26.TX_D2
CELL30.IMUX.IMUX.16.DELAY	BITSLICE26.TX_T
CELL30.IMUX.IMUX.17.DELAY	BUFGCTRL2.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.18.DELAY	BUFGCTRL3.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.19.DELAY	BUFGCTRL4.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.20.DELAY	BUFGCTRL5.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.21.DELAY	BUFGCTRL6.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.22.DELAY	BUFGCTRL7.CE1_PRE_OPTINV
CELL30.IMUX.IMUX.23.DELAY	BUFGCTRL0.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.24.DELAY	BUFGCTRL1.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.25.DELAY	BUFGCTRL2.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.26.DELAY	BUFGCTRL3.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.27.DELAY	BUFGCTRL4.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.28.DELAY	BUFGCTRL5.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.29.DELAY	BUFGCTRL6.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.30.DELAY	BUFGCTRL7.CE0_PRE_OPTINV
CELL30.IMUX.IMUX.31.DELAY	BUFGCE0.CE_PRE_OPTINV
CELL30.IMUX.IMUX.32.DELAY	BUFGCE1.CE_PRE_OPTINV
CELL30.IMUX.IMUX.33.DELAY	BUFGCE2.CE_PRE_OPTINV
CELL30.IMUX.IMUX.34.DELAY	BUFGCE3.CE_PRE_OPTINV
CELL30.IMUX.IMUX.35.DELAY	BUFGCE4.CE_PRE_OPTINV
CELL30.IMUX.IMUX.36.DELAY	BUFGCE5.CE_PRE_OPTINV
CELL30.IMUX.IMUX.37.DELAY	BUFGCE6.CE_PRE_OPTINV
CELL30.IMUX.IMUX.38.DELAY	BUFGCE7.CE_PRE_OPTINV
CELL30.IMUX.IMUX.39.DELAY	BUFGCE8.CE_PRE_OPTINV
CELL30.IMUX.IMUX.40.DELAY	BUFGCE9.CE_PRE_OPTINV
CELL30.IMUX.IMUX.41.DELAY	BUFGCE10.CE_PRE_OPTINV
CELL30.IMUX.IMUX.42.DELAY	BUFGCE11.CE_PRE_OPTINV
CELL30.IMUX.IMUX.43.DELAY	BUFGCE12.CE_PRE_OPTINV
CELL30.IMUX.IMUX.44.DELAY	BUFGCE13.CE_PRE_OPTINV
CELL30.IMUX.IMUX.45.DELAY	BUFGCE14.CE_PRE_OPTINV
CELL30.IMUX.IMUX.46.DELAY	BUFGCE15.CE_PRE_OPTINV
CELL30.IMUX.IMUX.47.DELAY	BUFGCE16.CE_PRE_OPTINV
CELL30.RCLK.IMUX.0	BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0
CELL30.RCLK.IMUX.1	BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1
CELL30.RCLK.IMUX.2	BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2
CELL30.RCLK.IMUX.6	BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0
CELL30.RCLK.IMUX.7	BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1
CELL30.RCLK.IMUX.8	BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2
CELL31.OUT.4.TMIN	BITSLICE27.PHY2CLB_FIFO_EMPTY
CELL31.OUT.5.TMIN	BITSLICE27.RX_Q0
CELL31.OUT.6.TMIN	BITSLICE27.RX_Q1
CELL31.OUT.7.TMIN	BITSLICE27.RX_Q2
CELL31.OUT.8.TMIN	BITSLICE27.RX_Q3
CELL31.OUT.9.TMIN	BITSLICE27.RX_Q4
CELL31.OUT.10.TMIN	BITSLICE27.RX_Q5
CELL31.OUT.11.TMIN	BITSLICE27.RX_Q6
CELL31.OUT.12.TMIN	BITSLICE27.RX_Q7
CELL31.OUT.13.TMIN	BITSLICE27.TX_CNTVALUEOUT0
CELL31.OUT.14.TMIN	BITSLICE27.TX_CNTVALUEOUT1
CELL31.OUT.15.TMIN	BITSLICE27.TX_CNTVALUEOUT2
CELL31.OUT.16.TMIN	BITSLICE27.TX_CNTVALUEOUT3
CELL31.OUT.17.TMIN	BITSLICE27.TX_CNTVALUEOUT4
CELL31.OUT.18.TMIN	BITSLICE27.TX_CNTVALUEOUT5
CELL31.OUT.19.TMIN	BITSLICE27.TX_CNTVALUEOUT6
CELL31.OUT.20.TMIN	BITSLICE27.TX_CNTVALUEOUT7
CELL31.OUT.21.TMIN	BITSLICE27.TX_CNTVALUEOUT8
CELL31.OUT.22.TMIN	BITSLICE27.TX_T_OUT
CELL31.OUT.23.TMIN	BITSLICE27.RX_CNTVALUEOUT0
CELL31.OUT.24.TMIN	BITSLICE27.RX_CNTVALUEOUT1
CELL31.OUT.25.TMIN	BITSLICE27.RX_CNTVALUEOUT2
CELL31.OUT.26.TMIN	BITSLICE27.RX_CNTVALUEOUT3
CELL31.OUT.27.TMIN	BITSLICE27.RX_CNTVALUEOUT4
CELL31.OUT.28.TMIN	BITSLICE27.RX_CNTVALUEOUT5
CELL31.OUT.29.TMIN	BITSLICE27.RX_CNTVALUEOUT6
CELL31.OUT.30.TMIN	BITSLICE27.RX_CNTVALUEOUT7
CELL31.OUT.31.TMIN	BITSLICE27.RX_CNTVALUEOUT8
CELL31.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK0
CELL31.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.TXBIT_TRI_RST_B1
CELL31.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.TXBIT_RST_B1
CELL31.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.RXBIT_RST_B1
CELL31.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.ODELAY_RST_B1
CELL31.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.IDELAY_RST_B1
CELL31.IMUX.BYP.6	BITSLICE_T5.EN_VTC
CELL31.IMUX.BYP.7	BITSLICE27.TX_LD
CELL31.IMUX.BYP.8	BITSLICE27.TX_INC
CELL31.IMUX.BYP.9	BITSLICE27.TX_EN_VTC
CELL31.IMUX.BYP.10	BITSLICE27.TX_CE_ODELAY
CELL31.IMUX.BYP.11	BITSLICE27.RX_LD
CELL31.IMUX.BYP.12	BITSLICE27.RX_INC
CELL31.IMUX.BYP.13	BITSLICE27.RX_EN_VTC
CELL31.IMUX.BYP.14	BITSLICE27.RX_CE_IDELAY
CELL31.IMUX.BYP.15	BITSLICE27.DYN_DCI_OUT_INT
CELL31.IMUX.IMUX.0.DELAY	BUFGCE_DIV3.RST_PRE_OPTINV
CELL31.IMUX.IMUX.6.DELAY	BITSLICE26.TX_D1
CELL31.IMUX.IMUX.7.DELAY	BITSLICE26.TX_CNTVALUEIN0
CELL31.IMUX.IMUX.8.DELAY	BITSLICE26.TX_CNTVALUEIN1
CELL31.IMUX.IMUX.9.DELAY	BITSLICE26.TX_CNTVALUEIN2
CELL31.IMUX.IMUX.10.DELAY	BITSLICE26.TX_CNTVALUEIN3
CELL31.IMUX.IMUX.11.DELAY	BITSLICE26.TX_CNTVALUEIN4
CELL31.IMUX.IMUX.12.DELAY	BITSLICE26.TX_CNTVALUEIN5
CELL31.IMUX.IMUX.13.DELAY	BITSLICE26.TX_CNTVALUEIN6
CELL31.IMUX.IMUX.14.DELAY	BITSLICE26.TX_CNTVALUEIN7
CELL31.IMUX.IMUX.15.DELAY	BITSLICE26.TX_CNTVALUEIN8
CELL31.IMUX.IMUX.16.DELAY	BITSLICE26.TX_D0
CELL31.IMUX.IMUX.17.DELAY	BUFGCE17.CE_PRE_OPTINV
CELL31.IMUX.IMUX.18.DELAY	BUFGCE18.CE_PRE_OPTINV
CELL31.IMUX.IMUX.19.DELAY	BUFGCE19.CE_PRE_OPTINV
CELL31.IMUX.IMUX.20.DELAY	BUFGCE20.CE_PRE_OPTINV
CELL31.IMUX.IMUX.21.DELAY	BUFGCE21.CE_PRE_OPTINV
CELL31.IMUX.IMUX.22.DELAY	BUFGCE22.CE_PRE_OPTINV
CELL31.IMUX.IMUX.23.DELAY	BUFGCE23.CE_PRE_OPTINV
CELL31.IMUX.IMUX.24.DELAY	BUFGCE0.CLK_IN_CKINT
CELL31.IMUX.IMUX.25.DELAY	BUFGCE1.CLK_IN_CKINT
CELL31.IMUX.IMUX.26.DELAY	BUFGCE2.CLK_IN_CKINT
CELL31.IMUX.IMUX.27.DELAY	BUFGCE3.CLK_IN_CKINT
CELL31.IMUX.IMUX.28.DELAY	BUFGCE4.CLK_IN_CKINT
CELL31.IMUX.IMUX.29.DELAY	BUFGCE5.CLK_IN_CKINT
CELL31.IMUX.IMUX.30.DELAY	BUFGCE6.CLK_IN_CKINT
CELL31.IMUX.IMUX.31.DELAY	BUFGCE7.CLK_IN_CKINT
CELL31.IMUX.IMUX.32.DELAY	BUFGCE8.CLK_IN_CKINT
CELL31.IMUX.IMUX.33.DELAY	BUFGCE9.CLK_IN_CKINT
CELL31.IMUX.IMUX.34.DELAY	BUFGCE10.CLK_IN_CKINT
CELL31.IMUX.IMUX.35.DELAY	BUFGCE11.CLK_IN_CKINT
CELL31.IMUX.IMUX.36.DELAY	BUFGCE12.CLK_IN_CKINT
CELL31.IMUX.IMUX.37.DELAY	BUFGCE13.CLK_IN_CKINT
CELL31.IMUX.IMUX.38.DELAY	BUFGCE14.CLK_IN_CKINT
CELL31.IMUX.IMUX.39.DELAY	BUFGCE15.CLK_IN_CKINT
CELL31.IMUX.IMUX.40.DELAY	BUFGCE16.CLK_IN_CKINT
CELL31.IMUX.IMUX.41.DELAY	BUFGCE17.CLK_IN_CKINT
CELL31.IMUX.IMUX.42.DELAY	BUFGCE18.CLK_IN_CKINT
CELL31.IMUX.IMUX.43.DELAY	BUFGCE19.CLK_IN_CKINT
CELL31.IMUX.IMUX.44.DELAY	BUFGCE20.CLK_IN_CKINT
CELL31.IMUX.IMUX.45.DELAY	BUFGCE21.CLK_IN_CKINT
CELL31.IMUX.IMUX.46.DELAY	BUFGCE22.CLK_IN_CKINT
CELL31.IMUX.IMUX.47.DELAY	BUFGCE23.CLK_IN_CKINT
CELL32.OUT.4.TMIN	BITSLICE28.PHY2CLB_FIFO_EMPTY
CELL32.OUT.5.TMIN	BITSLICE28.RX_Q0
CELL32.OUT.6.TMIN	BITSLICE28.RX_Q1
CELL32.OUT.7.TMIN	BITSLICE28.RX_Q2
CELL32.OUT.8.TMIN	BITSLICE28.RX_Q3
CELL32.OUT.9.TMIN	BITSLICE28.RX_Q4
CELL32.OUT.10.TMIN	BITSLICE28.RX_Q5
CELL32.OUT.11.TMIN	BITSLICE28.RX_Q6
CELL32.OUT.12.TMIN	BITSLICE28.RX_Q7
CELL32.OUT.13.TMIN	BITSLICE28.TX_CNTVALUEOUT0
CELL32.OUT.14.TMIN	BITSLICE28.TX_CNTVALUEOUT1
CELL32.OUT.15.TMIN	BITSLICE28.TX_CNTVALUEOUT2
CELL32.OUT.16.TMIN	BITSLICE28.TX_CNTVALUEOUT3
CELL32.OUT.17.TMIN	BITSLICE28.TX_CNTVALUEOUT4
CELL32.OUT.18.TMIN	BITSLICE28.TX_CNTVALUEOUT5
CELL32.OUT.19.TMIN	BITSLICE28.TX_CNTVALUEOUT6
CELL32.OUT.20.TMIN	BITSLICE28.TX_CNTVALUEOUT7
CELL32.OUT.21.TMIN	BITSLICE28.TX_CNTVALUEOUT8
CELL32.OUT.22.TMIN	BITSLICE28.TX_T_OUT
CELL32.OUT.23.TMIN	BITSLICE28.RX_CNTVALUEOUT0
CELL32.OUT.24.TMIN	BITSLICE28.RX_CNTVALUEOUT1
CELL32.OUT.25.TMIN	BITSLICE28.RX_CNTVALUEOUT2
CELL32.OUT.26.TMIN	BITSLICE28.RX_CNTVALUEOUT3
CELL32.OUT.27.TMIN	BITSLICE28.RX_CNTVALUEOUT4
CELL32.OUT.28.TMIN	BITSLICE28.RX_CNTVALUEOUT5
CELL32.OUT.29.TMIN	BITSLICE28.RX_CNTVALUEOUT6
CELL32.OUT.30.TMIN	BITSLICE28.RX_CNTVALUEOUT7
CELL32.OUT.31.TMIN	BITSLICE28.RX_CNTVALUEOUT8
CELL32.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK1
CELL32.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.TXBIT_RST_B2
CELL32.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.RXBIT_RST_B2
CELL32.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.ODELAY_RST_B2
CELL32.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.IDELAY_RST_B2
CELL32.IMUX.BYP.6	BITSLICE28.TX_LD
CELL32.IMUX.BYP.7	BITSLICE28.TX_INC
CELL32.IMUX.BYP.8	BITSLICE28.TX_EN_VTC
CELL32.IMUX.BYP.9	BITSLICE28.TX_CE_ODELAY
CELL32.IMUX.BYP.10	BITSLICE28.RX_LD
CELL32.IMUX.BYP.11	BITSLICE28.RX_INC
CELL32.IMUX.BYP.12	BITSLICE28.RX_EN_VTC
CELL32.IMUX.BYP.13	BITSLICE28.RX_CE_IDELAY
CELL32.IMUX.BYP.14	BITSLICE28.DYN_DCI_OUT_INT
CELL32.IMUX.BYP.15	BITSLICE_T4.CE_OFD
CELL32.IMUX.IMUX.6.DELAY	BITSLICE27.TX_D1
CELL32.IMUX.IMUX.7.DELAY	BITSLICE27.TX_D3
CELL32.IMUX.IMUX.8.DELAY	BITSLICE27.TX_D7
CELL32.IMUX.IMUX.9.DELAY	BITSLICE27.TX_CNTVALUEIN1
CELL32.IMUX.IMUX.10.DELAY	BITSLICE27.TX_CNTVALUEIN5
CELL32.IMUX.IMUX.11.DELAY	BITSLICE27.TX_CNTVALUEIN7
CELL32.IMUX.IMUX.12.DELAY	BITSLICE27.RX_CNTVALUEIN2
CELL32.IMUX.IMUX.13.DELAY	BITSLICE27.RX_CNTVALUEIN4
CELL32.IMUX.IMUX.14.DELAY	BITSLICE27.RX_CNTVALUEIN8
CELL32.IMUX.IMUX.15.DELAY	BITSLICE28.TX_CE_OFD
CELL32.IMUX.IMUX.16.DELAY	BITSLICE26.RX_CNTVALUEIN0
CELL32.IMUX.IMUX.17.DELAY	BITSLICE26.RX_CNTVALUEIN1
CELL32.IMUX.IMUX.18.DELAY	BITSLICE26.RX_CNTVALUEIN2
CELL32.IMUX.IMUX.19.DELAY	BITSLICE26.RX_CNTVALUEIN3
CELL32.IMUX.IMUX.20.DELAY	BITSLICE26.RX_CNTVALUEIN4
CELL32.IMUX.IMUX.21.DELAY	BITSLICE26.RX_CNTVALUEIN5
CELL32.IMUX.IMUX.22.DELAY	BITSLICE26.RX_CNTVALUEIN6
CELL32.IMUX.IMUX.23.DELAY	BITSLICE26.RX_CNTVALUEIN7
CELL32.IMUX.IMUX.24.DELAY	BITSLICE26.RX_CNTVALUEIN8
CELL32.IMUX.IMUX.25.DELAY	BITSLICE27.TX_T
CELL32.IMUX.IMUX.26.DELAY	BITSLICE27.TX_CE_OFD
CELL32.IMUX.IMUX.27.DELAY	BITSLICE27.RX_CE_IFD
CELL32.IMUX.IMUX.28.DELAY	BITSLICE27.RX_DATAIN1
CELL32.IMUX.IMUX.29.DELAY	BITSLICE27.CLB2PHY_FIFO_RDEN
CELL32.IMUX.IMUX.30.DELAY	BITSLICE27.TX_D0
CELL32.IMUX.IMUX.31.DELAY	BITSLICE27.TX_D2
CELL32.IMUX.IMUX.32.DELAY	BITSLICE27.TX_D4
CELL32.IMUX.IMUX.33.DELAY	BITSLICE27.TX_D5
CELL32.IMUX.IMUX.34.DELAY	BITSLICE27.TX_D6
CELL32.IMUX.IMUX.35.DELAY	BITSLICE27.TX_CNTVALUEIN0
CELL32.IMUX.IMUX.36.DELAY	BITSLICE27.TX_CNTVALUEIN2
CELL32.IMUX.IMUX.37.DELAY	BITSLICE27.TX_CNTVALUEIN3
CELL32.IMUX.IMUX.38.DELAY	BITSLICE27.TX_CNTVALUEIN4
CELL32.IMUX.IMUX.39.DELAY	BITSLICE27.TX_CNTVALUEIN6
CELL32.IMUX.IMUX.40.DELAY	BITSLICE27.TX_CNTVALUEIN8
CELL32.IMUX.IMUX.41.DELAY	BITSLICE27.RX_CNTVALUEIN0
CELL32.IMUX.IMUX.42.DELAY	BITSLICE27.RX_CNTVALUEIN1
CELL32.IMUX.IMUX.43.DELAY	BITSLICE27.RX_CNTVALUEIN3
CELL32.IMUX.IMUX.44.DELAY	BITSLICE27.RX_CNTVALUEIN5
CELL32.IMUX.IMUX.45.DELAY	BITSLICE27.RX_CNTVALUEIN6
CELL32.IMUX.IMUX.46.DELAY	BITSLICE27.RX_CNTVALUEIN7
CELL32.IMUX.IMUX.47.DELAY	BITSLICE28.TX_T
CELL33.OUT.4.TMIN	BITSLICE_T4.CNTVALUEOUT0
CELL33.OUT.5.TMIN	BITSLICE_T4.CNTVALUEOUT1
CELL33.OUT.6.TMIN	BITSLICE_T4.CNTVALUEOUT2
CELL33.OUT.7.TMIN	BITSLICE_T4.CNTVALUEOUT3
CELL33.OUT.8.TMIN	BITSLICE_T4.CNTVALUEOUT4
CELL33.OUT.9.TMIN	BITSLICE_T4.CNTVALUEOUT5
CELL33.OUT.10.TMIN	BITSLICE_T4.CNTVALUEOUT6
CELL33.OUT.11.TMIN	BITSLICE_T4.CNTVALUEOUT7
CELL33.OUT.12.TMIN	BITSLICE_T4.CNTVALUEOUT8
CELL33.OUT.13.TMIN	BITSLICE29.TX_T_OUT
CELL33.OUT.14.TMIN	BITSLICE_CONTROL4.PHY2CLB_PHY_RDY
CELL33.OUT.15.TMIN	BITSLICE_CONTROL4.MASTER_PD_OUT
CELL33.OUT.16.TMIN	BITSLICE_CONTROL4.PHY2CLB_FIXDLY_RDY
CELL33.OUT.17.TMIN	BITSLICE_CONTROL4.CTRL_DLY_TEST_OUT
CELL33.OUT.18.TMIN	BITSLICE29.PHY2CLB_FIFO_EMPTY
CELL33.OUT.19.TMIN	BITSLICE29.RX_Q0
CELL33.OUT.20.TMIN	BITSLICE29.RX_Q1
CELL33.OUT.21.TMIN	BITSLICE29.RX_Q2
CELL33.OUT.22.TMIN	BITSLICE29.RX_Q3
CELL33.OUT.23.TMIN	BITSLICE29.RX_Q4
CELL33.OUT.24.TMIN	BITSLICE29.RX_Q5
CELL33.OUT.25.TMIN	BITSLICE29.RX_Q6
CELL33.OUT.26.TMIN	BITSLICE29.RX_Q7
CELL33.OUT.27.TMIN	BITSLICE29.TX_CNTVALUEOUT0
CELL33.OUT.28.TMIN	BITSLICE29.TX_CNTVALUEOUT1
CELL33.OUT.29.TMIN	BITSLICE29.TX_CNTVALUEOUT2
CELL33.OUT.30.TMIN	BITSLICE29.TX_CNTVALUEOUT3
CELL33.OUT.31.TMIN	BITSLICE29.TX_CNTVALUEOUT4
CELL33.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK2
CELL33.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.TRISTATE_ODELAY_RST_B0
CELL33.IMUX.CTRL.5	BITSLICE_CONTROL4.REFCLK
CELL33.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.CTRL_RST_B_LOW
CELL33.IMUX.CTRL.7	BITSLICE_CONTROL4.RIU_CLK, XIPHY_FEEDTHROUGH2.CLB2PHY_CTRL_CLK_LOW
CELL33.IMUX.BYP.6	BITSLICE_T4.LD
CELL33.IMUX.BYP.7	BITSLICE_T4.INC
CELL33.IMUX.BYP.8	BITSLICE_T4.CE_ODELAY
CELL33.IMUX.BYP.9	BITSLICE_CONTROL4.EN_VTC
CELL33.IMUX.BYP.10	BITSLICE_CONTROL4.CTRL_DLY_TEST_IN
CELL33.IMUX.BYP.12	BITSLICE29.TX_LD
CELL33.IMUX.BYP.13	BITSLICE29.TX_INC
CELL33.IMUX.BYP.14	BITSLICE29.TX_EN_VTC
CELL33.IMUX.BYP.15	BITSLICE29.TX_CE_ODELAY
CELL33.IMUX.IMUX.6.DELAY	BITSLICE28.TX_CNTVALUEIN3
CELL33.IMUX.IMUX.7.DELAY	BITSLICE28.TX_CNTVALUEIN5
CELL33.IMUX.IMUX.8.DELAY	BITSLICE28.RX_CNTVALUEIN0
CELL33.IMUX.IMUX.9.DELAY	BITSLICE28.RX_CNTVALUEIN2
CELL33.IMUX.IMUX.10.DELAY	BITSLICE28.RX_CNTVALUEIN6
CELL33.IMUX.IMUX.11.DELAY	BITSLICE28.RX_CNTVALUEIN8
CELL33.IMUX.IMUX.12.DELAY	BITSLICE_T4.CNTVALUEIN3
CELL33.IMUX.IMUX.13.DELAY	BITSLICE_T4.CNTVALUEIN5
CELL33.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL4.CLB2RIU_NIBBLE_SEL
CELL33.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS1_1
CELL33.IMUX.IMUX.16.DELAY	BITSLICE28.RX_CE_IFD
CELL33.IMUX.IMUX.17.DELAY	BITSLICE28.RX_DATAIN1
CELL33.IMUX.IMUX.18.DELAY	BITSLICE28.CLB2PHY_FIFO_RDEN
CELL33.IMUX.IMUX.20.DELAY	BITSLICE28.TX_D0
CELL33.IMUX.IMUX.21.DELAY	BITSLICE28.TX_D1
CELL33.IMUX.IMUX.22.DELAY	BITSLICE28.TX_D2
CELL33.IMUX.IMUX.23.DELAY	BITSLICE28.TX_D3
CELL33.IMUX.IMUX.24.DELAY	BITSLICE28.TX_D4
CELL33.IMUX.IMUX.25.DELAY	BITSLICE28.TX_D5
CELL33.IMUX.IMUX.26.DELAY	BITSLICE28.TX_D6
CELL33.IMUX.IMUX.27.DELAY	BITSLICE28.TX_D7
CELL33.IMUX.IMUX.28.DELAY	BITSLICE28.TX_CNTVALUEIN0
CELL33.IMUX.IMUX.29.DELAY	BITSLICE28.TX_CNTVALUEIN1
CELL33.IMUX.IMUX.30.DELAY	BITSLICE28.TX_CNTVALUEIN2
CELL33.IMUX.IMUX.31.DELAY	BITSLICE28.TX_CNTVALUEIN4
CELL33.IMUX.IMUX.32.DELAY	BITSLICE28.TX_CNTVALUEIN6
CELL33.IMUX.IMUX.33.DELAY	BITSLICE28.TX_CNTVALUEIN7
CELL33.IMUX.IMUX.34.DELAY	BITSLICE28.TX_CNTVALUEIN8
CELL33.IMUX.IMUX.35.DELAY	BITSLICE28.RX_CNTVALUEIN1
CELL33.IMUX.IMUX.36.DELAY	BITSLICE28.RX_CNTVALUEIN3
CELL33.IMUX.IMUX.37.DELAY	BITSLICE28.RX_CNTVALUEIN4
CELL33.IMUX.IMUX.38.DELAY	BITSLICE28.RX_CNTVALUEIN5
CELL33.IMUX.IMUX.39.DELAY	BITSLICE28.RX_CNTVALUEIN7
CELL33.IMUX.IMUX.40.DELAY	BITSLICE_T4.CNTVALUEIN0
CELL33.IMUX.IMUX.41.DELAY	BITSLICE_T4.CNTVALUEIN1
CELL33.IMUX.IMUX.42.DELAY	BITSLICE_T4.CNTVALUEIN2
CELL33.IMUX.IMUX.43.DELAY	BITSLICE_T4.CNTVALUEIN4
CELL33.IMUX.IMUX.44.DELAY	BITSLICE_T4.CNTVALUEIN6
CELL33.IMUX.IMUX.45.DELAY	BITSLICE_T4.CNTVALUEIN7
CELL33.IMUX.IMUX.46.DELAY	BITSLICE_T4.CNTVALUEIN8
CELL33.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS1_0
CELL34.OUT.4.TMIN	BITSLICE29.TX_CNTVALUEOUT5
CELL34.OUT.5.TMIN	BITSLICE29.TX_CNTVALUEOUT6
CELL34.OUT.6.TMIN	BITSLICE29.TX_CNTVALUEOUT7
CELL34.OUT.7.TMIN	BITSLICE29.TX_CNTVALUEOUT8
CELL34.OUT.8.TMIN	BITSLICE30.TX_T_OUT
CELL34.OUT.9.TMIN	BITSLICE29.RX_CNTVALUEOUT0
CELL34.OUT.10.TMIN	BITSLICE29.RX_CNTVALUEOUT1
CELL34.OUT.11.TMIN	BITSLICE29.RX_CNTVALUEOUT2
CELL34.OUT.12.TMIN	BITSLICE29.RX_CNTVALUEOUT3
CELL34.OUT.13.TMIN	BITSLICE29.RX_CNTVALUEOUT4
CELL34.OUT.14.TMIN	BITSLICE29.RX_CNTVALUEOUT5
CELL34.OUT.15.TMIN	BITSLICE29.RX_CNTVALUEOUT6
CELL34.OUT.16.TMIN	BITSLICE29.RX_CNTVALUEOUT7
CELL34.OUT.17.TMIN	BITSLICE29.RX_CNTVALUEOUT8
CELL34.OUT.18.TMIN	BITSLICE30.PHY2CLB_FIFO_EMPTY
CELL34.OUT.19.TMIN	BITSLICE30.RX_Q0
CELL34.OUT.20.TMIN	BITSLICE30.RX_Q1
CELL34.OUT.21.TMIN	BITSLICE30.RX_Q2
CELL34.OUT.22.TMIN	BITSLICE30.RX_Q3
CELL34.OUT.23.TMIN	BITSLICE30.RX_Q4
CELL34.OUT.24.TMIN	BITSLICE30.RX_Q5
CELL34.OUT.25.TMIN	BITSLICE30.RX_Q6
CELL34.OUT.26.TMIN	BITSLICE30.RX_Q7
CELL34.OUT.27.TMIN	BITSLICE30.TX_CNTVALUEOUT0
CELL34.OUT.28.TMIN	BITSLICE30.TX_CNTVALUEOUT1
CELL34.OUT.29.TMIN	BITSLICE30.TX_CNTVALUEOUT2
CELL34.OUT.30.TMIN	BITSLICE30.TX_CNTVALUEOUT3
CELL34.OUT.31.TMIN	BITSLICE30.TX_CNTVALUEOUT4
CELL34.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.TXBIT_RST_B3
CELL34.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.RXBIT_RST_B3
CELL34.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.ODELAY_RST_B3
CELL34.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.IDELAY_RST_B3
CELL34.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK3
CELL34.IMUX.BYP.6	BITSLICE29.RX_LD
CELL34.IMUX.BYP.7	BITSLICE29.RX_INC
CELL34.IMUX.BYP.8	BITSLICE29.RX_EN_VTC
CELL34.IMUX.BYP.9	BITSLICE29.RX_CE_IDELAY
CELL34.IMUX.BYP.10	BITSLICE29.DYN_DCI_OUT_INT
CELL34.IMUX.BYP.11	BITSLICE30.TX_LD
CELL34.IMUX.BYP.12	BITSLICE30.TX_INC
CELL34.IMUX.BYP.13	BITSLICE30.TX_EN_VTC
CELL34.IMUX.BYP.14	BITSLICE30.TX_CE_ODELAY
CELL34.IMUX.BYP.15	BITSLICE30.RX_LD
CELL34.IMUX.IMUX.6.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS1_1
CELL34.IMUX.IMUX.7.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS1_3
CELL34.IMUX.IMUX.8.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS0_3
CELL34.IMUX.IMUX.9.DELAY	BITSLICE29.TX_CE_OFD
CELL34.IMUX.IMUX.10.DELAY	BITSLICE29.TX_D0
CELL34.IMUX.IMUX.11.DELAY	BITSLICE29.TX_D2
CELL34.IMUX.IMUX.12.DELAY	BITSLICE29.TX_D6
CELL34.IMUX.IMUX.13.DELAY	BITSLICE29.TX_D7
CELL34.IMUX.IMUX.14.DELAY	BITSLICE29.TX_CNTVALUEIN3
CELL34.IMUX.IMUX.15.DELAY	BITSLICE29.TX_CNTVALUEIN5
CELL34.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS1_2
CELL34.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS1_3
CELL34.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS0_0
CELL34.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS0_1
CELL34.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS0_2
CELL34.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL4.CLB2PHY_WRCS0_3
CELL34.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL4.CLB2PHY_T_B0
CELL34.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL4.CLB2PHY_T_B1
CELL34.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL4.CLB2PHY_T_B2
CELL34.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL4.CLB2PHY_T_B3
CELL34.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDEN0
CELL34.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDEN1
CELL34.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDEN2
CELL34.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDEN3
CELL34.IMUX.IMUX.30.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS1_0
CELL34.IMUX.IMUX.31.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS1_2
CELL34.IMUX.IMUX.32.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS0_0
CELL34.IMUX.IMUX.33.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS0_1
CELL34.IMUX.IMUX.34.DELAY	BITSLICE_CONTROL4.CLB2PHY_RDCS0_2
CELL34.IMUX.IMUX.35.DELAY	BITSLICE29.TX_T
CELL34.IMUX.IMUX.36.DELAY	BITSLICE29.RX_CE_IFD
CELL34.IMUX.IMUX.37.DELAY	BITSLICE29.RX_DATAIN1
CELL34.IMUX.IMUX.38.DELAY	BITSLICE29.CLB2PHY_FIFO_RDEN
CELL34.IMUX.IMUX.39.DELAY	BITSLICE29.TX_D1
CELL34.IMUX.IMUX.40.DELAY	BITSLICE29.TX_D3
CELL34.IMUX.IMUX.41.DELAY	BITSLICE29.TX_D4
CELL34.IMUX.IMUX.42.DELAY	BITSLICE29.TX_D5
CELL34.IMUX.IMUX.44.DELAY	BITSLICE29.TX_CNTVALUEIN0
CELL34.IMUX.IMUX.45.DELAY	BITSLICE29.TX_CNTVALUEIN1
CELL34.IMUX.IMUX.46.DELAY	BITSLICE29.TX_CNTVALUEIN2
CELL34.IMUX.IMUX.47.DELAY	BITSLICE29.TX_CNTVALUEIN4
CELL35.OUT.4.TMIN	BITSLICE30.TX_CNTVALUEOUT5
CELL35.OUT.5.TMIN	BITSLICE30.TX_CNTVALUEOUT6
CELL35.OUT.6.TMIN	BITSLICE30.TX_CNTVALUEOUT7
CELL35.OUT.7.TMIN	BITSLICE30.TX_CNTVALUEOUT8
CELL35.OUT.8.TMIN	BITSLICE31.TX_T_OUT
CELL35.OUT.9.TMIN	BITSLICE30.RX_CNTVALUEOUT0
CELL35.OUT.10.TMIN	BITSLICE30.RX_CNTVALUEOUT1
CELL35.OUT.11.TMIN	BITSLICE30.RX_CNTVALUEOUT2
CELL35.OUT.12.TMIN	BITSLICE30.RX_CNTVALUEOUT3
CELL35.OUT.13.TMIN	BITSLICE30.RX_CNTVALUEOUT4
CELL35.OUT.14.TMIN	BITSLICE30.RX_CNTVALUEOUT5
CELL35.OUT.15.TMIN	BITSLICE30.RX_CNTVALUEOUT6
CELL35.OUT.16.TMIN	BITSLICE30.RX_CNTVALUEOUT7
CELL35.OUT.17.TMIN	BITSLICE30.RX_CNTVALUEOUT8
CELL35.OUT.18.TMIN	BITSLICE31.PHY2CLB_FIFO_EMPTY
CELL35.OUT.19.TMIN	BITSLICE31.RX_Q0
CELL35.OUT.20.TMIN	BITSLICE31.RX_Q1
CELL35.OUT.21.TMIN	BITSLICE31.RX_Q2
CELL35.OUT.22.TMIN	BITSLICE31.RX_Q3
CELL35.OUT.23.TMIN	BITSLICE31.RX_Q4
CELL35.OUT.24.TMIN	BITSLICE31.RX_Q5
CELL35.OUT.25.TMIN	BITSLICE31.RX_Q6
CELL35.OUT.26.TMIN	BITSLICE31.RX_Q7
CELL35.OUT.27.TMIN	BITSLICE31.TX_CNTVALUEOUT0
CELL35.OUT.28.TMIN	BITSLICE31.TX_CNTVALUEOUT1
CELL35.OUT.29.TMIN	BITSLICE31.TX_CNTVALUEOUT2
CELL35.OUT.30.TMIN	BITSLICE31.TX_CNTVALUEOUT3
CELL35.OUT.31.TMIN	BITSLICE31.TX_CNTVALUEOUT4
CELL35.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.TXBIT_RST_B4
CELL35.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.RXBIT_RST_B4
CELL35.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.ODELAY_RST_B4
CELL35.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.IDELAY_RST_B4
CELL35.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK4
CELL35.IMUX.BYP.6	BITSLICE30.RX_INC
CELL35.IMUX.BYP.7	BITSLICE30.RX_EN_VTC
CELL35.IMUX.BYP.8	BITSLICE30.RX_CE_IDELAY
CELL35.IMUX.BYP.9	BITSLICE30.DYN_DCI_OUT_INT
CELL35.IMUX.BYP.10	BITSLICE31.TX_LD
CELL35.IMUX.BYP.11	BITSLICE31.TX_INC
CELL35.IMUX.BYP.12	BITSLICE31.TX_EN_VTC
CELL35.IMUX.BYP.13	BITSLICE31.TX_CE_ODELAY
CELL35.IMUX.BYP.14	BITSLICE31.RX_LD
CELL35.IMUX.BYP.15	BITSLICE31.RX_INC
CELL35.IMUX.IMUX.6.DELAY	BITSLICE30.RX_DATAIN1
CELL35.IMUX.IMUX.7.DELAY	BITSLICE30.TX_D0
CELL35.IMUX.IMUX.8.DELAY	BITSLICE30.TX_D4
CELL35.IMUX.IMUX.9.DELAY	BITSLICE30.TX_D6
CELL35.IMUX.IMUX.10.DELAY	BITSLICE30.TX_CNTVALUEIN2
CELL35.IMUX.IMUX.11.DELAY	BITSLICE30.TX_CNTVALUEIN4
CELL35.IMUX.IMUX.12.DELAY	BITSLICE30.TX_CNTVALUEIN8
CELL35.IMUX.IMUX.13.DELAY	BITSLICE30.RX_CNTVALUEIN1
CELL35.IMUX.IMUX.14.DELAY	BITSLICE30.RX_CNTVALUEIN5
CELL35.IMUX.IMUX.15.DELAY	BITSLICE30.RX_CNTVALUEIN7
CELL35.IMUX.IMUX.16.DELAY	BITSLICE29.TX_CNTVALUEIN6
CELL35.IMUX.IMUX.17.DELAY	BITSLICE29.TX_CNTVALUEIN7
CELL35.IMUX.IMUX.18.DELAY	BITSLICE29.TX_CNTVALUEIN8
CELL35.IMUX.IMUX.19.DELAY	BITSLICE29.RX_CNTVALUEIN0
CELL35.IMUX.IMUX.20.DELAY	BITSLICE29.RX_CNTVALUEIN1
CELL35.IMUX.IMUX.21.DELAY	BITSLICE29.RX_CNTVALUEIN2
CELL35.IMUX.IMUX.22.DELAY	BITSLICE29.RX_CNTVALUEIN3
CELL35.IMUX.IMUX.23.DELAY	BITSLICE29.RX_CNTVALUEIN4
CELL35.IMUX.IMUX.24.DELAY	BITSLICE29.RX_CNTVALUEIN5
CELL35.IMUX.IMUX.25.DELAY	BITSLICE29.RX_CNTVALUEIN6
CELL35.IMUX.IMUX.26.DELAY	BITSLICE29.RX_CNTVALUEIN7
CELL35.IMUX.IMUX.27.DELAY	BITSLICE29.RX_CNTVALUEIN8
CELL35.IMUX.IMUX.28.DELAY	BITSLICE30.TX_T
CELL35.IMUX.IMUX.29.DELAY	BITSLICE30.TX_CE_OFD
CELL35.IMUX.IMUX.30.DELAY	BITSLICE30.RX_CE_IFD
CELL35.IMUX.IMUX.31.DELAY	BITSLICE30.CLB2PHY_FIFO_RDEN
CELL35.IMUX.IMUX.32.DELAY	BITSLICE30.TX_D1
CELL35.IMUX.IMUX.33.DELAY	BITSLICE30.TX_D2
CELL35.IMUX.IMUX.34.DELAY	BITSLICE30.TX_D3
CELL35.IMUX.IMUX.35.DELAY	BITSLICE30.TX_D5
CELL35.IMUX.IMUX.36.DELAY	BITSLICE30.TX_D7
CELL35.IMUX.IMUX.37.DELAY	BITSLICE30.TX_CNTVALUEIN0
CELL35.IMUX.IMUX.38.DELAY	BITSLICE30.TX_CNTVALUEIN1
CELL35.IMUX.IMUX.39.DELAY	BITSLICE30.TX_CNTVALUEIN3
CELL35.IMUX.IMUX.40.DELAY	BITSLICE30.TX_CNTVALUEIN5
CELL35.IMUX.IMUX.41.DELAY	BITSLICE30.TX_CNTVALUEIN6
CELL35.IMUX.IMUX.42.DELAY	BITSLICE30.TX_CNTVALUEIN7
CELL35.IMUX.IMUX.43.DELAY	BITSLICE30.RX_CNTVALUEIN0
CELL35.IMUX.IMUX.44.DELAY	BITSLICE30.RX_CNTVALUEIN2
CELL35.IMUX.IMUX.45.DELAY	BITSLICE30.RX_CNTVALUEIN3
CELL35.IMUX.IMUX.46.DELAY	BITSLICE30.RX_CNTVALUEIN4
CELL35.IMUX.IMUX.47.DELAY	BITSLICE30.RX_CNTVALUEIN6
CELL36.OUT.4.TMIN	BITSLICE31.TX_CNTVALUEOUT5
CELL36.OUT.5.TMIN	BITSLICE31.TX_CNTVALUEOUT6
CELL36.OUT.6.TMIN	BITSLICE31.TX_CNTVALUEOUT7
CELL36.OUT.7.TMIN	BITSLICE31.TX_CNTVALUEOUT8
CELL36.OUT.8.TMIN	BITSLICE32.TX_T_OUT
CELL36.OUT.9.TMIN	BITSLICE31.RX_CNTVALUEOUT0
CELL36.OUT.10.TMIN	BITSLICE31.RX_CNTVALUEOUT1
CELL36.OUT.11.TMIN	BITSLICE31.RX_CNTVALUEOUT2
CELL36.OUT.12.TMIN	BITSLICE31.RX_CNTVALUEOUT3
CELL36.OUT.13.TMIN	BITSLICE31.RX_CNTVALUEOUT4
CELL36.OUT.14.TMIN	BITSLICE31.RX_CNTVALUEOUT5
CELL36.OUT.15.TMIN	BITSLICE31.RX_CNTVALUEOUT6
CELL36.OUT.16.TMIN	BITSLICE31.RX_CNTVALUEOUT7
CELL36.OUT.17.TMIN	BITSLICE31.RX_CNTVALUEOUT8
CELL36.OUT.18.TMIN	RIU_OR2.RIU_RD_VALID
CELL36.OUT.19.TMIN	RIU_OR2.RIU_RD_DATA0
CELL36.OUT.20.TMIN	RIU_OR2.RIU_RD_DATA1
CELL36.OUT.21.TMIN	RIU_OR2.RIU_RD_DATA2
CELL36.OUT.22.TMIN	RIU_OR2.RIU_RD_DATA3
CELL36.OUT.23.TMIN	RIU_OR2.RIU_RD_DATA4
CELL36.OUT.24.TMIN	RIU_OR2.RIU_RD_DATA5
CELL36.OUT.25.TMIN	RIU_OR2.RIU_RD_DATA6
CELL36.OUT.26.TMIN	RIU_OR2.RIU_RD_DATA7
CELL36.OUT.27.TMIN	RIU_OR2.RIU_RD_DATA8
CELL36.OUT.28.TMIN	RIU_OR2.RIU_RD_DATA9
CELL36.OUT.29.TMIN	RIU_OR2.RIU_RD_DATA10
CELL36.OUT.30.TMIN	RIU_OR2.RIU_RD_DATA11
CELL36.OUT.31.TMIN	RIU_OR2.RIU_RD_DATA12
CELL36.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.TXBIT_RST_B5
CELL36.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.RXBIT_RST_B5
CELL36.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.ODELAY_RST_B5
CELL36.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.IDELAY_RST_B5
CELL36.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK5
CELL36.IMUX.BYP.6	BITSLICE31.RX_EN_VTC
CELL36.IMUX.BYP.7	BITSLICE31.RX_CE_IDELAY
CELL36.IMUX.BYP.8	BITSLICE31.DYN_DCI_OUT_INT
CELL36.IMUX.BYP.9	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B0
CELL36.IMUX.BYP.10	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B1
CELL36.IMUX.BYP.11	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B2
CELL36.IMUX.BYP.12	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SPARE_B3
CELL36.IMUX.BYP.13	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_RST_MASK_B
CELL36.IMUX.BYP.14	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_MODE_B
CELL36.IMUX.BYP.15	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN0
CELL36.IMUX.IMUX.6.DELAY	BITSLICE31.TX_CNTVALUEIN1
CELL36.IMUX.IMUX.7.DELAY	BITSLICE31.TX_CNTVALUEIN3
CELL36.IMUX.IMUX.8.DELAY	BITSLICE31.TX_CNTVALUEIN7
CELL36.IMUX.IMUX.10.DELAY	BITSLICE31.RX_CNTVALUEIN3
CELL36.IMUX.IMUX.11.DELAY	BITSLICE31.RX_CNTVALUEIN5
CELL36.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_EN, BITSLICE_CONTROL5.CLB2RIU_WR_EN
CELL36.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA1, BITSLICE_CONTROL5.CLB2RIU_WR_DATA1
CELL36.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA5, BITSLICE_CONTROL5.CLB2RIU_WR_DATA5
CELL36.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA7, BITSLICE_CONTROL5.CLB2RIU_WR_DATA7
CELL36.IMUX.IMUX.16.DELAY	BITSLICE30.RX_CNTVALUEIN8
CELL36.IMUX.IMUX.17.DELAY	BITSLICE31.TX_T
CELL36.IMUX.IMUX.18.DELAY	BITSLICE31.TX_CE_OFD
CELL36.IMUX.IMUX.19.DELAY	BITSLICE31.RX_CE_IFD
CELL36.IMUX.IMUX.20.DELAY	BITSLICE31.RX_DATAIN1
CELL36.IMUX.IMUX.21.DELAY	BITSLICE31.CLB2PHY_FIFO_RDEN
CELL36.IMUX.IMUX.22.DELAY	BITSLICE31.TX_D0
CELL36.IMUX.IMUX.23.DELAY	BITSLICE31.TX_D1
CELL36.IMUX.IMUX.24.DELAY	BITSLICE31.TX_D2
CELL36.IMUX.IMUX.25.DELAY	BITSLICE31.TX_D3
CELL36.IMUX.IMUX.26.DELAY	BITSLICE31.TX_D4
CELL36.IMUX.IMUX.27.DELAY	BITSLICE31.TX_D5
CELL36.IMUX.IMUX.28.DELAY	BITSLICE31.TX_D6
CELL36.IMUX.IMUX.29.DELAY	BITSLICE31.TX_D7
CELL36.IMUX.IMUX.30.DELAY	BITSLICE31.TX_CNTVALUEIN0
CELL36.IMUX.IMUX.31.DELAY	BITSLICE31.TX_CNTVALUEIN2
CELL36.IMUX.IMUX.32.DELAY	BITSLICE31.TX_CNTVALUEIN4
CELL36.IMUX.IMUX.33.DELAY	BITSLICE31.TX_CNTVALUEIN5
CELL36.IMUX.IMUX.34.DELAY	BITSLICE31.TX_CNTVALUEIN6
CELL36.IMUX.IMUX.35.DELAY	BITSLICE31.TX_CNTVALUEIN8
CELL36.IMUX.IMUX.36.DELAY	BITSLICE31.RX_CNTVALUEIN0
CELL36.IMUX.IMUX.37.DELAY	BITSLICE31.RX_CNTVALUEIN1
CELL36.IMUX.IMUX.38.DELAY	BITSLICE31.RX_CNTVALUEIN2
CELL36.IMUX.IMUX.39.DELAY	BITSLICE31.RX_CNTVALUEIN4
CELL36.IMUX.IMUX.40.DELAY	BITSLICE31.RX_CNTVALUEIN6
CELL36.IMUX.IMUX.41.DELAY	BITSLICE31.RX_CNTVALUEIN7
CELL36.IMUX.IMUX.42.DELAY	BITSLICE31.RX_CNTVALUEIN8
CELL36.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA0, BITSLICE_CONTROL5.CLB2RIU_WR_DATA0
CELL36.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA2, BITSLICE_CONTROL5.CLB2RIU_WR_DATA2
CELL36.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA3, BITSLICE_CONTROL5.CLB2RIU_WR_DATA3
CELL36.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA4, BITSLICE_CONTROL5.CLB2RIU_WR_DATA4
CELL36.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA6, BITSLICE_CONTROL5.CLB2RIU_WR_DATA6
CELL37.OUT.4.TMIN	RIU_OR2.RIU_RD_DATA13
CELL37.OUT.5.TMIN	RIU_OR2.RIU_RD_DATA14
CELL37.OUT.6.TMIN	RIU_OR2.RIU_RD_DATA15
CELL37.OUT.7.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT0
CELL37.OUT.8.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT1
CELL37.OUT.9.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT2
CELL37.OUT.10.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT3
CELL37.OUT.11.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT4
CELL37.OUT.12.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT5
CELL37.OUT.13.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT6
CELL37.OUT.14.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_SCAN_OUT7
CELL37.OUT.15.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_OUT
CELL37.OUT.16.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_FLG_OUT
CELL37.OUT.17.TMIN	XIPHY_FEEDTHROUGH2.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
CELL37.OUT.18.TMIN	BITSLICE38.PHY2CLB_FIFO_EMPTY
CELL37.OUT.19.TMIN	BITSLICE38.RX_Q0
CELL37.OUT.20.TMIN	BITSLICE38.RX_Q1
CELL37.OUT.21.TMIN	BITSLICE38.RX_Q2
CELL37.OUT.22.TMIN	BITSLICE38.RX_Q3
CELL37.OUT.23.TMIN	BITSLICE38.RX_Q4
CELL37.OUT.24.TMIN	BITSLICE38.RX_Q5
CELL37.OUT.25.TMIN	BITSLICE38.RX_Q6
CELL37.OUT.26.TMIN	BITSLICE38.RX_Q7
CELL37.OUT.27.TMIN	BITSLICE38.TX_CNTVALUEOUT0
CELL37.OUT.28.TMIN	BITSLICE38.TX_CNTVALUEOUT1
CELL37.OUT.29.TMIN	BITSLICE38.TX_CNTVALUEOUT2
CELL37.OUT.30.TMIN	BITSLICE38.TX_CNTVALUEOUT3
CELL37.OUT.31.TMIN	BITSLICE38.TX_CNTVALUEOUT4
CELL37.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_SDR
CELL37.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_DIV4
CELL37.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_CLK_DIV2
CELL37.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.TXBIT_RST_B12
CELL37.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.RXBIT_RST_B12
CELL37.IMUX.BYP.6	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN1
CELL37.IMUX.BYP.7	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN2
CELL37.IMUX.BYP.8	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN3
CELL37.IMUX.BYP.10	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN4
CELL37.IMUX.BYP.11	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN5
CELL37.IMUX.BYP.12	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN6
CELL37.IMUX.BYP.13	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_IN7
CELL37.IMUX.BYP.14	XIPHY_FEEDTHROUGH2.CLB2PHY_SCAN_EN_B
CELL37.IMUX.BYP.15	BITSLICE38.TX_LD
CELL37.IMUX.IMUX.6.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_DIV4_CLK_SEL_B
CELL37.IMUX.IMUX.7.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CT_START_EN
CELL37.IMUX.IMUX.8.DELAY	BITSLICE38.TX_CE_OFD
CELL37.IMUX.IMUX.9.DELAY	BITSLICE38.RX_DATAIN1
CELL37.IMUX.IMUX.10.DELAY	BITSLICE38.TX_D2
CELL37.IMUX.IMUX.11.DELAY	BITSLICE38.TX_D4
CELL37.IMUX.IMUX.12.DELAY	BITSLICE38.TX_CNTVALUEIN0
CELL37.IMUX.IMUX.13.DELAY	BITSLICE38.TX_CNTVALUEIN2
CELL37.IMUX.IMUX.14.DELAY	BITSLICE38.TX_CNTVALUEIN6
CELL37.IMUX.IMUX.15.DELAY	BITSLICE38.TX_CNTVALUEIN8
CELL37.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA8, BITSLICE_CONTROL5.CLB2RIU_WR_DATA8
CELL37.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA9, BITSLICE_CONTROL5.CLB2RIU_WR_DATA9
CELL37.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA10, BITSLICE_CONTROL5.CLB2RIU_WR_DATA10
CELL37.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA11, BITSLICE_CONTROL5.CLB2RIU_WR_DATA11
CELL37.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA12, BITSLICE_CONTROL5.CLB2RIU_WR_DATA12
CELL37.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA13, BITSLICE_CONTROL5.CLB2RIU_WR_DATA13
CELL37.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA14, BITSLICE_CONTROL5.CLB2RIU_WR_DATA14
CELL37.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL4.CLB2RIU_WR_DATA15, BITSLICE_CONTROL5.CLB2RIU_WR_DATA15
CELL37.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR0, BITSLICE_CONTROL5.CLB2RIU_ADDR0
CELL37.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR1, BITSLICE_CONTROL5.CLB2RIU_ADDR1
CELL37.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR2, BITSLICE_CONTROL5.CLB2RIU_ADDR2
CELL37.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR3, BITSLICE_CONTROL5.CLB2RIU_ADDR3
CELL37.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR4, BITSLICE_CONTROL5.CLB2RIU_ADDR4
CELL37.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL4.CLB2RIU_ADDR5, BITSLICE_CONTROL5.CLB2RIU_ADDR5
CELL37.IMUX.IMUX.30.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_SDR_CLK_SEL_B
CELL37.IMUX.IMUX.31.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_TEST_DIV2_CLK_SEL_B
CELL37.IMUX.IMUX.32.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CLK_STOP_FLG_OUT
CELL37.IMUX.IMUX.33.DELAY	XIPHY_FEEDTHROUGH2.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
CELL37.IMUX.IMUX.34.DELAY	BITSLICE38.TX_T
CELL37.IMUX.IMUX.35.DELAY	BITSLICE38.RX_CE_IFD
CELL37.IMUX.IMUX.36.DELAY	BITSLICE38.CLB2PHY_FIFO_RDEN
CELL37.IMUX.IMUX.37.DELAY	BITSLICE38.TX_D0
CELL37.IMUX.IMUX.38.DELAY	BITSLICE38.TX_D1
CELL37.IMUX.IMUX.39.DELAY	BITSLICE38.TX_D3
CELL37.IMUX.IMUX.40.DELAY	BITSLICE38.TX_D5
CELL37.IMUX.IMUX.41.DELAY	BITSLICE38.TX_D6
CELL37.IMUX.IMUX.42.DELAY	BITSLICE38.TX_D7
CELL37.IMUX.IMUX.43.DELAY	BITSLICE38.TX_CNTVALUEIN1
CELL37.IMUX.IMUX.44.DELAY	BITSLICE38.TX_CNTVALUEIN3
CELL37.IMUX.IMUX.45.DELAY	BITSLICE38.TX_CNTVALUEIN4
CELL37.IMUX.IMUX.46.DELAY	BITSLICE38.TX_CNTVALUEIN5
CELL37.IMUX.IMUX.47.DELAY	BITSLICE38.TX_CNTVALUEIN7
CELL38.OUT.4.TMIN	BITSLICE38.TX_CNTVALUEOUT5
CELL38.OUT.5.TMIN	BITSLICE38.TX_CNTVALUEOUT6
CELL38.OUT.6.TMIN	BITSLICE38.TX_CNTVALUEOUT7
CELL38.OUT.7.TMIN	BITSLICE38.TX_CNTVALUEOUT8
CELL38.OUT.8.TMIN	BITSLICE33.TX_T_OUT
CELL38.OUT.9.TMIN	BITSLICE38.RX_CNTVALUEOUT0
CELL38.OUT.10.TMIN	BITSLICE38.RX_CNTVALUEOUT1
CELL38.OUT.11.TMIN	BITSLICE38.RX_CNTVALUEOUT2
CELL38.OUT.12.TMIN	BITSLICE38.RX_CNTVALUEOUT3
CELL38.OUT.13.TMIN	BITSLICE38.RX_CNTVALUEOUT4
CELL38.OUT.14.TMIN	BITSLICE38.RX_CNTVALUEOUT5
CELL38.OUT.15.TMIN	BITSLICE38.RX_CNTVALUEOUT6
CELL38.OUT.16.TMIN	BITSLICE38.RX_CNTVALUEOUT7
CELL38.OUT.17.TMIN	BITSLICE38.RX_CNTVALUEOUT8
CELL38.OUT.18.TMIN	BITSLICE32.PHY2CLB_FIFO_EMPTY
CELL38.OUT.19.TMIN	BITSLICE32.RX_Q0
CELL38.OUT.20.TMIN	BITSLICE32.RX_Q1
CELL38.OUT.21.TMIN	BITSLICE32.RX_Q2
CELL38.OUT.22.TMIN	BITSLICE32.RX_Q3
CELL38.OUT.23.TMIN	BITSLICE32.RX_Q4
CELL38.OUT.24.TMIN	BITSLICE32.RX_Q5
CELL38.OUT.25.TMIN	BITSLICE32.RX_Q6
CELL38.OUT.26.TMIN	BITSLICE32.RX_Q7
CELL38.OUT.27.TMIN	BITSLICE32.TX_CNTVALUEOUT0
CELL38.OUT.28.TMIN	BITSLICE32.TX_CNTVALUEOUT1
CELL38.OUT.29.TMIN	BITSLICE32.TX_CNTVALUEOUT2
CELL38.OUT.30.TMIN	BITSLICE32.TX_CNTVALUEOUT3
CELL38.OUT.31.TMIN	BITSLICE32.TX_CNTVALUEOUT4
CELL38.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.ODELAY_RST_B12
CELL38.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.IDELAY_RST_B12
CELL38.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK12
CELL38.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.TXBIT_RST_B6
CELL38.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.RXBIT_RST_B6
CELL38.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.ODELAY_RST_B6
CELL38.IMUX.BYP.6	BITSLICE38.TX_INC
CELL38.IMUX.BYP.7	BITSLICE38.TX_EN_VTC
CELL38.IMUX.BYP.8	BITSLICE38.TX_CE_ODELAY
CELL38.IMUX.BYP.9	BITSLICE38.RX_LD
CELL38.IMUX.BYP.10	BITSLICE38.RX_INC
CELL38.IMUX.BYP.11	BITSLICE38.RX_EN_VTC
CELL38.IMUX.BYP.12	BITSLICE38.RX_CE_IDELAY
CELL38.IMUX.BYP.13	BITSLICE38.DYN_DCI_OUT_INT
CELL38.IMUX.BYP.14	BITSLICE32.TX_LD
CELL38.IMUX.BYP.15	BITSLICE32.TX_INC
CELL38.IMUX.IMUX.6.DELAY	BITSLICE32.TX_D0
CELL38.IMUX.IMUX.7.DELAY	BITSLICE32.TX_D2
CELL38.IMUX.IMUX.8.DELAY	BITSLICE32.TX_D6
CELL38.IMUX.IMUX.9.DELAY	BITSLICE32.TX_CNTVALUEIN0
CELL38.IMUX.IMUX.10.DELAY	BITSLICE32.TX_CNTVALUEIN4
CELL38.IMUX.IMUX.11.DELAY	BITSLICE32.TX_CNTVALUEIN6
CELL38.IMUX.IMUX.12.DELAY	BITSLICE32.RX_CNTVALUEIN1
CELL38.IMUX.IMUX.13.DELAY	BITSLICE32.RX_CNTVALUEIN3
CELL38.IMUX.IMUX.14.DELAY	BITSLICE32.RX_CNTVALUEIN7
CELL38.IMUX.IMUX.15.DELAY	BITSLICE33.TX_T
CELL38.IMUX.IMUX.16.DELAY	BITSLICE38.RX_CNTVALUEIN0
CELL38.IMUX.IMUX.17.DELAY	BITSLICE38.RX_CNTVALUEIN1
CELL38.IMUX.IMUX.18.DELAY	BITSLICE38.RX_CNTVALUEIN2
CELL38.IMUX.IMUX.19.DELAY	BITSLICE38.RX_CNTVALUEIN3
CELL38.IMUX.IMUX.20.DELAY	BITSLICE38.RX_CNTVALUEIN4
CELL38.IMUX.IMUX.21.DELAY	BITSLICE38.RX_CNTVALUEIN5
CELL38.IMUX.IMUX.22.DELAY	BITSLICE38.RX_CNTVALUEIN6
CELL38.IMUX.IMUX.23.DELAY	BITSLICE38.RX_CNTVALUEIN7
CELL38.IMUX.IMUX.24.DELAY	BITSLICE38.RX_CNTVALUEIN8
CELL38.IMUX.IMUX.25.DELAY	BITSLICE32.TX_T
CELL38.IMUX.IMUX.26.DELAY	BITSLICE32.TX_CE_OFD
CELL38.IMUX.IMUX.27.DELAY	BITSLICE32.RX_CE_IFD
CELL38.IMUX.IMUX.29.DELAY	BITSLICE32.RX_DATAIN1
CELL38.IMUX.IMUX.30.DELAY	BITSLICE32.CLB2PHY_FIFO_RDEN
CELL38.IMUX.IMUX.31.DELAY	BITSLICE32.TX_D1
CELL38.IMUX.IMUX.32.DELAY	BITSLICE32.TX_D3
CELL38.IMUX.IMUX.33.DELAY	BITSLICE32.TX_D4
CELL38.IMUX.IMUX.34.DELAY	BITSLICE32.TX_D5
CELL38.IMUX.IMUX.35.DELAY	BITSLICE32.TX_D7
CELL38.IMUX.IMUX.36.DELAY	BITSLICE32.TX_CNTVALUEIN1
CELL38.IMUX.IMUX.37.DELAY	BITSLICE32.TX_CNTVALUEIN2
CELL38.IMUX.IMUX.38.DELAY	BITSLICE32.TX_CNTVALUEIN3
CELL38.IMUX.IMUX.39.DELAY	BITSLICE32.TX_CNTVALUEIN5
CELL38.IMUX.IMUX.40.DELAY	BITSLICE32.TX_CNTVALUEIN7
CELL38.IMUX.IMUX.41.DELAY	BITSLICE32.TX_CNTVALUEIN8
CELL38.IMUX.IMUX.42.DELAY	BITSLICE32.RX_CNTVALUEIN0
CELL38.IMUX.IMUX.43.DELAY	BITSLICE32.RX_CNTVALUEIN2
CELL38.IMUX.IMUX.44.DELAY	BITSLICE32.RX_CNTVALUEIN4
CELL38.IMUX.IMUX.45.DELAY	BITSLICE32.RX_CNTVALUEIN5
CELL38.IMUX.IMUX.46.DELAY	BITSLICE32.RX_CNTVALUEIN6
CELL38.IMUX.IMUX.47.DELAY	BITSLICE32.RX_CNTVALUEIN8
CELL39.OUT.4.TMIN	BITSLICE32.TX_CNTVALUEOUT5
CELL39.OUT.5.TMIN	BITSLICE32.TX_CNTVALUEOUT6
CELL39.OUT.6.TMIN	BITSLICE32.TX_CNTVALUEOUT7
CELL39.OUT.7.TMIN	BITSLICE32.TX_CNTVALUEOUT8
CELL39.OUT.8.TMIN	BITSLICE34.TX_T_OUT
CELL39.OUT.9.TMIN	BITSLICE32.RX_CNTVALUEOUT0
CELL39.OUT.10.TMIN	BITSLICE32.RX_CNTVALUEOUT1
CELL39.OUT.11.TMIN	BITSLICE32.RX_CNTVALUEOUT2
CELL39.OUT.12.TMIN	BITSLICE32.RX_CNTVALUEOUT3
CELL39.OUT.13.TMIN	BITSLICE32.RX_CNTVALUEOUT4
CELL39.OUT.14.TMIN	BITSLICE32.RX_CNTVALUEOUT5
CELL39.OUT.15.TMIN	BITSLICE32.RX_CNTVALUEOUT6
CELL39.OUT.16.TMIN	BITSLICE32.RX_CNTVALUEOUT7
CELL39.OUT.17.TMIN	BITSLICE32.RX_CNTVALUEOUT8
CELL39.OUT.18.TMIN	BITSLICE33.PHY2CLB_FIFO_EMPTY
CELL39.OUT.19.TMIN	BITSLICE33.RX_Q0
CELL39.OUT.20.TMIN	BITSLICE33.RX_Q1
CELL39.OUT.21.TMIN	BITSLICE33.RX_Q2
CELL39.OUT.22.TMIN	BITSLICE33.RX_Q3
CELL39.OUT.23.TMIN	BITSLICE33.RX_Q4
CELL39.OUT.24.TMIN	BITSLICE33.RX_Q5
CELL39.OUT.25.TMIN	BITSLICE33.RX_Q6
CELL39.OUT.26.TMIN	BITSLICE33.RX_Q7
CELL39.OUT.27.TMIN	BITSLICE33.TX_CNTVALUEOUT0
CELL39.OUT.28.TMIN	BITSLICE33.TX_CNTVALUEOUT1
CELL39.OUT.29.TMIN	BITSLICE33.TX_CNTVALUEOUT2
CELL39.OUT.30.TMIN	BITSLICE33.TX_CNTVALUEOUT3
CELL39.OUT.31.TMIN	BITSLICE33.TX_CNTVALUEOUT4
CELL39.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.IDELAY_RST_B6
CELL39.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK6
CELL39.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.TXBIT_RST_B7
CELL39.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.RXBIT_RST_B7
CELL39.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.ODELAY_RST_B7
CELL39.IMUX.BYP.6	BITSLICE32.TX_EN_VTC
CELL39.IMUX.BYP.7	BITSLICE32.TX_CE_ODELAY
CELL39.IMUX.BYP.8	BITSLICE32.RX_LD
CELL39.IMUX.BYP.9	BITSLICE32.RX_INC
CELL39.IMUX.BYP.10	BITSLICE32.RX_EN_VTC
CELL39.IMUX.BYP.11	BITSLICE32.RX_CE_IDELAY
CELL39.IMUX.BYP.12	BITSLICE32.DYN_DCI_OUT_INT
CELL39.IMUX.BYP.14	BITSLICE33.TX_LD
CELL39.IMUX.BYP.15	BITSLICE33.TX_INC
CELL39.IMUX.IMUX.6.DELAY	BITSLICE33.TX_CNTVALUEIN3
CELL39.IMUX.IMUX.7.DELAY	BITSLICE33.TX_CNTVALUEIN5
CELL39.IMUX.IMUX.8.DELAY	BITSLICE33.RX_CNTVALUEIN0
CELL39.IMUX.IMUX.9.DELAY	BITSLICE33.RX_CNTVALUEIN2
CELL39.IMUX.IMUX.10.DELAY	BITSLICE33.RX_CNTVALUEIN6
CELL39.IMUX.IMUX.11.DELAY	BITSLICE33.RX_CNTVALUEIN8
CELL39.IMUX.IMUX.12.DELAY	BITSLICE34.RX_DATAIN1
CELL39.IMUX.IMUX.13.DELAY	BITSLICE34.TX_D0
CELL39.IMUX.IMUX.14.DELAY	BITSLICE34.TX_D4
CELL39.IMUX.IMUX.15.DELAY	BITSLICE34.TX_D6
CELL39.IMUX.IMUX.16.DELAY	BITSLICE33.TX_CE_OFD
CELL39.IMUX.IMUX.17.DELAY	BITSLICE33.RX_CE_IFD
CELL39.IMUX.IMUX.18.DELAY	BITSLICE33.RX_DATAIN1
CELL39.IMUX.IMUX.19.DELAY	BITSLICE33.CLB2PHY_FIFO_RDEN
CELL39.IMUX.IMUX.20.DELAY	BITSLICE33.TX_D0
CELL39.IMUX.IMUX.21.DELAY	BITSLICE33.TX_D1
CELL39.IMUX.IMUX.22.DELAY	BITSLICE33.TX_D2
CELL39.IMUX.IMUX.23.DELAY	BITSLICE33.TX_D3
CELL39.IMUX.IMUX.24.DELAY	BITSLICE33.TX_D4
CELL39.IMUX.IMUX.25.DELAY	BITSLICE33.TX_D5
CELL39.IMUX.IMUX.26.DELAY	BITSLICE33.TX_D6
CELL39.IMUX.IMUX.27.DELAY	BITSLICE33.TX_D7
CELL39.IMUX.IMUX.28.DELAY	BITSLICE33.TX_CNTVALUEIN0
CELL39.IMUX.IMUX.29.DELAY	BITSLICE33.TX_CNTVALUEIN1
CELL39.IMUX.IMUX.30.DELAY	BITSLICE33.TX_CNTVALUEIN2
CELL39.IMUX.IMUX.31.DELAY	BITSLICE33.TX_CNTVALUEIN4
CELL39.IMUX.IMUX.32.DELAY	BITSLICE33.TX_CNTVALUEIN6
CELL39.IMUX.IMUX.33.DELAY	BITSLICE33.TX_CNTVALUEIN7
CELL39.IMUX.IMUX.34.DELAY	BITSLICE33.TX_CNTVALUEIN8
CELL39.IMUX.IMUX.35.DELAY	BITSLICE33.RX_CNTVALUEIN1
CELL39.IMUX.IMUX.36.DELAY	BITSLICE33.RX_CNTVALUEIN3
CELL39.IMUX.IMUX.37.DELAY	BITSLICE33.RX_CNTVALUEIN4
CELL39.IMUX.IMUX.38.DELAY	BITSLICE33.RX_CNTVALUEIN5
CELL39.IMUX.IMUX.39.DELAY	BITSLICE33.RX_CNTVALUEIN7
CELL39.IMUX.IMUX.40.DELAY	BITSLICE34.TX_T
CELL39.IMUX.IMUX.41.DELAY	BITSLICE34.TX_CE_OFD
CELL39.IMUX.IMUX.42.DELAY	BITSLICE34.RX_CE_IFD
CELL39.IMUX.IMUX.43.DELAY	BITSLICE34.CLB2PHY_FIFO_RDEN
CELL39.IMUX.IMUX.44.DELAY	BITSLICE34.TX_D1
CELL39.IMUX.IMUX.45.DELAY	BITSLICE34.TX_D2
CELL39.IMUX.IMUX.46.DELAY	BITSLICE34.TX_D3
CELL39.IMUX.IMUX.47.DELAY	BITSLICE34.TX_D5
CELL40.OUT.4.TMIN	BITSLICE33.TX_CNTVALUEOUT5
CELL40.OUT.5.TMIN	BITSLICE33.TX_CNTVALUEOUT6
CELL40.OUT.6.TMIN	BITSLICE33.TX_CNTVALUEOUT7
CELL40.OUT.7.TMIN	BITSLICE33.TX_CNTVALUEOUT8
CELL40.OUT.8.TMIN	BITSLICE35.TX_T_OUT
CELL40.OUT.9.TMIN	BITSLICE33.RX_CNTVALUEOUT0
CELL40.OUT.10.TMIN	BITSLICE33.RX_CNTVALUEOUT1
CELL40.OUT.11.TMIN	BITSLICE33.RX_CNTVALUEOUT2
CELL40.OUT.12.TMIN	BITSLICE33.RX_CNTVALUEOUT3
CELL40.OUT.13.TMIN	BITSLICE33.RX_CNTVALUEOUT4
CELL40.OUT.14.TMIN	BITSLICE33.RX_CNTVALUEOUT5
CELL40.OUT.15.TMIN	BITSLICE33.RX_CNTVALUEOUT6
CELL40.OUT.16.TMIN	BITSLICE33.RX_CNTVALUEOUT7
CELL40.OUT.17.TMIN	BITSLICE33.RX_CNTVALUEOUT8
CELL40.OUT.18.TMIN	BITSLICE34.PHY2CLB_FIFO_EMPTY
CELL40.OUT.19.TMIN	BITSLICE34.RX_Q0
CELL40.OUT.20.TMIN	BITSLICE34.RX_Q1
CELL40.OUT.21.TMIN	BITSLICE34.RX_Q2
CELL40.OUT.22.TMIN	BITSLICE34.RX_Q3
CELL40.OUT.23.TMIN	BITSLICE34.RX_Q4
CELL40.OUT.24.TMIN	BITSLICE34.RX_Q5
CELL40.OUT.25.TMIN	BITSLICE34.RX_Q6
CELL40.OUT.26.TMIN	BITSLICE34.RX_Q7
CELL40.OUT.27.TMIN	BITSLICE34.TX_CNTVALUEOUT0
CELL40.OUT.28.TMIN	BITSLICE34.TX_CNTVALUEOUT1
CELL40.OUT.29.TMIN	BITSLICE34.TX_CNTVALUEOUT2
CELL40.OUT.30.TMIN	BITSLICE34.TX_CNTVALUEOUT3
CELL40.OUT.31.TMIN	BITSLICE34.TX_CNTVALUEOUT4
CELL40.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.IDELAY_RST_B7
CELL40.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK7
CELL40.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.TXBIT_RST_B8
CELL40.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.RXBIT_RST_B8
CELL40.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.ODELAY_RST_B8
CELL40.IMUX.BYP.6	BITSLICE33.TX_EN_VTC
CELL40.IMUX.BYP.7	BITSLICE33.TX_CE_ODELAY
CELL40.IMUX.BYP.8	BITSLICE33.RX_LD
CELL40.IMUX.BYP.9	BITSLICE33.RX_INC
CELL40.IMUX.BYP.10	BITSLICE33.RX_EN_VTC
CELL40.IMUX.BYP.11	BITSLICE33.RX_CE_IDELAY
CELL40.IMUX.BYP.12	BITSLICE33.DYN_DCI_OUT_INT
CELL40.IMUX.BYP.13	BITSLICE34.TX_LD
CELL40.IMUX.BYP.14	BITSLICE34.TX_INC
CELL40.IMUX.BYP.15	BITSLICE34.TX_EN_VTC
CELL40.IMUX.IMUX.6.DELAY	BITSLICE34.RX_CNTVALUEIN4
CELL40.IMUX.IMUX.7.DELAY	BITSLICE34.RX_CNTVALUEIN6
CELL40.IMUX.IMUX.8.DELAY	BITSLICE_T5.CNTVALUEIN1
CELL40.IMUX.IMUX.9.DELAY	BITSLICE_T5.CNTVALUEIN3
CELL40.IMUX.IMUX.10.DELAY	BITSLICE_T5.CNTVALUEIN7
CELL40.IMUX.IMUX.11.DELAY	BITSLICE_CONTROL5.CLB2RIU_NIBBLE_SEL
CELL40.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS1_3
CELL40.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS0_1
CELL40.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL5.CLB2PHY_T_B1
CELL40.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL5.CLB2PHY_T_B3
CELL40.IMUX.IMUX.16.DELAY	BITSLICE34.TX_D7
CELL40.IMUX.IMUX.18.DELAY	BITSLICE34.TX_CNTVALUEIN0
CELL40.IMUX.IMUX.19.DELAY	BITSLICE34.TX_CNTVALUEIN1
CELL40.IMUX.IMUX.20.DELAY	BITSLICE34.TX_CNTVALUEIN2
CELL40.IMUX.IMUX.21.DELAY	BITSLICE34.TX_CNTVALUEIN3
CELL40.IMUX.IMUX.22.DELAY	BITSLICE34.TX_CNTVALUEIN4
CELL40.IMUX.IMUX.23.DELAY	BITSLICE34.TX_CNTVALUEIN5
CELL40.IMUX.IMUX.24.DELAY	BITSLICE34.TX_CNTVALUEIN6
CELL40.IMUX.IMUX.25.DELAY	BITSLICE34.TX_CNTVALUEIN7
CELL40.IMUX.IMUX.26.DELAY	BITSLICE34.TX_CNTVALUEIN8
CELL40.IMUX.IMUX.27.DELAY	BITSLICE34.RX_CNTVALUEIN0
CELL40.IMUX.IMUX.28.DELAY	BITSLICE34.RX_CNTVALUEIN1
CELL40.IMUX.IMUX.29.DELAY	BITSLICE34.RX_CNTVALUEIN2
CELL40.IMUX.IMUX.30.DELAY	BITSLICE34.RX_CNTVALUEIN3
CELL40.IMUX.IMUX.31.DELAY	BITSLICE34.RX_CNTVALUEIN5
CELL40.IMUX.IMUX.32.DELAY	BITSLICE34.RX_CNTVALUEIN7
CELL40.IMUX.IMUX.33.DELAY	BITSLICE34.RX_CNTVALUEIN8
CELL40.IMUX.IMUX.34.DELAY	BITSLICE_T5.CNTVALUEIN0
CELL40.IMUX.IMUX.35.DELAY	BITSLICE_T5.CNTVALUEIN2
CELL40.IMUX.IMUX.36.DELAY	BITSLICE_T5.CNTVALUEIN4
CELL40.IMUX.IMUX.37.DELAY	BITSLICE_T5.CNTVALUEIN5
CELL40.IMUX.IMUX.38.DELAY	BITSLICE_T5.CNTVALUEIN6
CELL40.IMUX.IMUX.39.DELAY	BITSLICE_T5.CNTVALUEIN8
CELL40.IMUX.IMUX.40.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS1_0
CELL40.IMUX.IMUX.41.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS1_1
CELL40.IMUX.IMUX.42.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS1_2
CELL40.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS0_0
CELL40.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS0_2
CELL40.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL5.CLB2PHY_WRCS0_3
CELL40.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL5.CLB2PHY_T_B0
CELL40.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL5.CLB2PHY_T_B2
CELL41.OUT.0.TMIN	MMCM.TESTOUT32
CELL41.OUT.1.TMIN	MMCM.TESTOUT33
CELL41.OUT.2.TMIN	MMCM.TESTOUT34
CELL41.OUT.3.TMIN	MMCM.TESTOUT35
CELL41.OUT.4.TMIN	BITSLICE34.TX_CNTVALUEOUT5
CELL41.OUT.5.TMIN	BITSLICE34.TX_CNTVALUEOUT6
CELL41.OUT.6.TMIN	BITSLICE34.TX_CNTVALUEOUT7
CELL41.OUT.7.TMIN	BITSLICE34.TX_CNTVALUEOUT8
CELL41.OUT.8.TMIN	BITSLICE36.TX_T_OUT
CELL41.OUT.9.TMIN	BITSLICE34.RX_CNTVALUEOUT0
CELL41.OUT.10.TMIN	BITSLICE34.RX_CNTVALUEOUT1
CELL41.OUT.11.TMIN	BITSLICE34.RX_CNTVALUEOUT2
CELL41.OUT.12.TMIN	BITSLICE34.RX_CNTVALUEOUT3
CELL41.OUT.13.TMIN	BITSLICE34.RX_CNTVALUEOUT4
CELL41.OUT.14.TMIN	BITSLICE34.RX_CNTVALUEOUT5
CELL41.OUT.15.TMIN	BITSLICE34.RX_CNTVALUEOUT6
CELL41.OUT.16.TMIN	BITSLICE34.RX_CNTVALUEOUT7
CELL41.OUT.17.TMIN	BITSLICE34.RX_CNTVALUEOUT8
CELL41.OUT.18.TMIN	BITSLICE_T5.CNTVALUEOUT0
CELL41.OUT.19.TMIN	BITSLICE_T5.CNTVALUEOUT1
CELL41.OUT.20.TMIN	BITSLICE_T5.CNTVALUEOUT2
CELL41.OUT.21.TMIN	BITSLICE_T5.CNTVALUEOUT3
CELL41.OUT.22.TMIN	BITSLICE_T5.CNTVALUEOUT4
CELL41.OUT.23.TMIN	BITSLICE_T5.CNTVALUEOUT5
CELL41.OUT.24.TMIN	BITSLICE_T5.CNTVALUEOUT6
CELL41.OUT.25.TMIN	BITSLICE_T5.CNTVALUEOUT7
CELL41.OUT.26.TMIN	BITSLICE_T5.CNTVALUEOUT8
CELL41.OUT.27.TMIN	BITSLICE_CONTROL5.PHY2CLB_PHY_RDY
CELL41.OUT.28.TMIN	BITSLICE_CONTROL5.MASTER_PD_OUT
CELL41.OUT.29.TMIN	BITSLICE_CONTROL5.PHY2CLB_FIXDLY_RDY
CELL41.OUT.30.TMIN	BITSLICE_CONTROL5.CTRL_DLY_TEST_OUT
CELL41.OUT.31.TMIN	BITSLICE37.TX_T_OUT
CELL41.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.IDELAY_RST_B8
CELL41.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK8
CELL41.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.TRISTATE_ODELAY_RST_B1
CELL41.IMUX.CTRL.6	BITSLICE_CONTROL5.REFCLK
CELL41.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.CTRL_RST_B_UPP
CELL41.IMUX.BYP.0	MMCM.TESTIN28
CELL41.IMUX.BYP.1	MMCM.TESTIN29
CELL41.IMUX.BYP.2	MMCM.TESTIN30
CELL41.IMUX.BYP.3	MMCM.TESTIN31
CELL41.IMUX.BYP.6	BITSLICE34.TX_CE_ODELAY
CELL41.IMUX.BYP.8	BITSLICE34.RX_LD
CELL41.IMUX.BYP.9	BITSLICE34.RX_INC
CELL41.IMUX.BYP.10	BITSLICE34.RX_EN_VTC
CELL41.IMUX.BYP.11	BITSLICE34.RX_CE_IDELAY
CELL41.IMUX.BYP.12	BITSLICE34.DYN_DCI_OUT_INT
CELL41.IMUX.BYP.13	BITSLICE_T5.CE_OFD
CELL41.IMUX.BYP.14	BITSLICE_T5.LD
CELL41.IMUX.BYP.15	BITSLICE_T5.INC
CELL41.IMUX.IMUX.0.DELAY	MMCM.CLKINSEL
CELL41.IMUX.IMUX.6.DELAY	BITSLICE35.RX_DATAIN1
CELL41.IMUX.IMUX.7.DELAY	BITSLICE35.TX_D0
CELL41.IMUX.IMUX.8.DELAY	BITSLICE35.TX_D4
CELL41.IMUX.IMUX.9.DELAY	BITSLICE35.TX_D6
CELL41.IMUX.IMUX.10.DELAY	BITSLICE35.TX_CNTVALUEIN2
CELL41.IMUX.IMUX.11.DELAY	BITSLICE35.TX_CNTVALUEIN4
CELL41.IMUX.IMUX.12.DELAY	BITSLICE35.TX_CNTVALUEIN7
CELL41.IMUX.IMUX.13.DELAY	BITSLICE35.RX_CNTVALUEIN0
CELL41.IMUX.IMUX.14.DELAY	BITSLICE35.RX_CNTVALUEIN4
CELL41.IMUX.IMUX.15.DELAY	BITSLICE35.RX_CNTVALUEIN6
CELL41.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDEN0
CELL41.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDEN1
CELL41.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDEN2
CELL41.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDEN3
CELL41.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS1_0
CELL41.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS1_1
CELL41.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS1_2
CELL41.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS1_3
CELL41.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS0_0
CELL41.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS0_1
CELL41.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS0_2
CELL41.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL5.CLB2PHY_RDCS0_3
CELL41.IMUX.IMUX.28.DELAY	BITSLICE35.TX_T
CELL41.IMUX.IMUX.29.DELAY	BITSLICE35.TX_CE_OFD
CELL41.IMUX.IMUX.30.DELAY	BITSLICE35.RX_CE_IFD
CELL41.IMUX.IMUX.31.DELAY	BITSLICE35.CLB2PHY_FIFO_RDEN
CELL41.IMUX.IMUX.32.DELAY	BITSLICE35.TX_D1
CELL41.IMUX.IMUX.33.DELAY	BITSLICE35.TX_D2
CELL41.IMUX.IMUX.34.DELAY	BITSLICE35.TX_D3
CELL41.IMUX.IMUX.35.DELAY	BITSLICE35.TX_D5
CELL41.IMUX.IMUX.36.DELAY	BITSLICE35.TX_D7
CELL41.IMUX.IMUX.37.DELAY	BITSLICE35.TX_CNTVALUEIN0
CELL41.IMUX.IMUX.38.DELAY	BITSLICE35.TX_CNTVALUEIN1
CELL41.IMUX.IMUX.39.DELAY	BITSLICE35.TX_CNTVALUEIN3
CELL41.IMUX.IMUX.40.DELAY	BITSLICE35.TX_CNTVALUEIN5
CELL41.IMUX.IMUX.41.DELAY	BITSLICE35.TX_CNTVALUEIN6
CELL41.IMUX.IMUX.43.DELAY	BITSLICE35.TX_CNTVALUEIN8
CELL41.IMUX.IMUX.44.DELAY	BITSLICE35.RX_CNTVALUEIN1
CELL41.IMUX.IMUX.45.DELAY	BITSLICE35.RX_CNTVALUEIN2
CELL41.IMUX.IMUX.46.DELAY	BITSLICE35.RX_CNTVALUEIN3
CELL41.IMUX.IMUX.47.DELAY	BITSLICE35.RX_CNTVALUEIN5
CELL42.OUT.0.TMIN	MMCM.TESTOUT28
CELL42.OUT.1.TMIN	MMCM.TESTOUT29
CELL42.OUT.2.TMIN	MMCM.TESTOUT30
CELL42.OUT.3.TMIN	MMCM.TESTOUT31
CELL42.OUT.4.TMIN	BITSLICE35.PHY2CLB_FIFO_EMPTY
CELL42.OUT.5.TMIN	BITSLICE35.RX_Q0
CELL42.OUT.6.TMIN	BITSLICE35.RX_Q1
CELL42.OUT.7.TMIN	BITSLICE35.RX_Q2
CELL42.OUT.8.TMIN	BITSLICE35.RX_Q3
CELL42.OUT.9.TMIN	BITSLICE35.RX_Q4
CELL42.OUT.10.TMIN	BITSLICE35.RX_Q5
CELL42.OUT.11.TMIN	BITSLICE35.RX_Q6
CELL42.OUT.12.TMIN	BITSLICE35.RX_Q7
CELL42.OUT.13.TMIN	BITSLICE35.TX_CNTVALUEOUT0
CELL42.OUT.14.TMIN	BITSLICE35.TX_CNTVALUEOUT1
CELL42.OUT.15.TMIN	BITSLICE35.TX_CNTVALUEOUT2
CELL42.OUT.16.TMIN	BITSLICE35.TX_CNTVALUEOUT3
CELL42.OUT.17.TMIN	BITSLICE35.TX_CNTVALUEOUT4
CELL42.OUT.18.TMIN	BITSLICE35.TX_CNTVALUEOUT5
CELL42.OUT.19.TMIN	BITSLICE35.TX_CNTVALUEOUT6
CELL42.OUT.20.TMIN	BITSLICE35.TX_CNTVALUEOUT7
CELL42.OUT.21.TMIN	BITSLICE35.TX_CNTVALUEOUT8
CELL42.OUT.22.TMIN	BITSLICE38.TX_T_OUT
CELL42.OUT.23.TMIN	BITSLICE35.RX_CNTVALUEOUT0
CELL42.OUT.24.TMIN	BITSLICE35.RX_CNTVALUEOUT1
CELL42.OUT.25.TMIN	BITSLICE35.RX_CNTVALUEOUT2
CELL42.OUT.26.TMIN	BITSLICE35.RX_CNTVALUEOUT3
CELL42.OUT.27.TMIN	BITSLICE35.RX_CNTVALUEOUT4
CELL42.OUT.28.TMIN	BITSLICE35.RX_CNTVALUEOUT5
CELL42.OUT.29.TMIN	BITSLICE35.RX_CNTVALUEOUT6
CELL42.OUT.30.TMIN	BITSLICE35.RX_CNTVALUEOUT7
CELL42.OUT.31.TMIN	BITSLICE35.RX_CNTVALUEOUT8
CELL42.IMUX.CTRL.2	BITSLICE_CONTROL5.RIU_CLK, XIPHY_FEEDTHROUGH2.CLB2PHY_CTRL_CLK_UPP
CELL42.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.TXBIT_RST_B9
CELL42.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.RXBIT_RST_B9
CELL42.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.ODELAY_RST_B9
CELL42.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.IDELAY_RST_B9
CELL42.IMUX.BYP.0	MMCM.TESTIN24
CELL42.IMUX.BYP.1	MMCM.TESTIN25
CELL42.IMUX.BYP.2	MMCM.TESTIN26
CELL42.IMUX.BYP.3	MMCM.TESTIN27
CELL42.IMUX.BYP.6	BITSLICE_T5.CE_ODELAY
CELL42.IMUX.BYP.7	BITSLICE_CONTROL5.EN_VTC
CELL42.IMUX.BYP.8	BITSLICE_CONTROL5.CTRL_DLY_TEST_IN
CELL42.IMUX.BYP.9	BITSLICE35.TX_LD
CELL42.IMUX.BYP.10	BITSLICE35.TX_INC
CELL42.IMUX.BYP.11	BITSLICE35.TX_EN_VTC
CELL42.IMUX.BYP.12	BITSLICE35.TX_CE_ODELAY
CELL42.IMUX.BYP.13	BITSLICE35.RX_LD
CELL42.IMUX.BYP.14	BITSLICE35.RX_INC
CELL42.IMUX.BYP.15	BITSLICE35.RX_EN_VTC
CELL42.IMUX.IMUX.6.DELAY	BITSLICE36.TX_CNTVALUEIN0
CELL42.IMUX.IMUX.7.DELAY	BITSLICE36.TX_CNTVALUEIN2
CELL42.IMUX.IMUX.8.DELAY	BITSLICE36.TX_CNTVALUEIN6
CELL42.IMUX.IMUX.9.DELAY	BITSLICE36.TX_CNTVALUEIN8
CELL42.IMUX.IMUX.10.DELAY	BITSLICE36.RX_CNTVALUEIN3
CELL42.IMUX.IMUX.11.DELAY	BITSLICE36.RX_CNTVALUEIN5
CELL42.IMUX.IMUX.12.DELAY	BITSLICE37.TX_T
CELL42.IMUX.IMUX.13.DELAY	BITSLICE37.RX_CE_IFD
CELL42.IMUX.IMUX.14.DELAY	BITSLICE37.TX_D1
CELL42.IMUX.IMUX.15.DELAY	BITSLICE37.TX_D3
CELL42.IMUX.IMUX.16.DELAY	BITSLICE35.RX_CNTVALUEIN7
CELL42.IMUX.IMUX.17.DELAY	BITSLICE35.RX_CNTVALUEIN8
CELL42.IMUX.IMUX.18.DELAY	BITSLICE36.TX_T
CELL42.IMUX.IMUX.19.DELAY	BITSLICE36.TX_CE_OFD
CELL42.IMUX.IMUX.20.DELAY	BITSLICE36.RX_CE_IFD
CELL42.IMUX.IMUX.21.DELAY	BITSLICE36.RX_DATAIN1
CELL42.IMUX.IMUX.22.DELAY	BITSLICE36.CLB2PHY_FIFO_RDEN
CELL42.IMUX.IMUX.23.DELAY	BITSLICE36.TX_D5
CELL42.IMUX.IMUX.24.DELAY	BITSLICE36.TX_D4
CELL42.IMUX.IMUX.25.DELAY	BITSLICE36.TX_D3
CELL42.IMUX.IMUX.26.DELAY	BITSLICE36.TX_D2
CELL42.IMUX.IMUX.27.DELAY	BITSLICE36.TX_D1
CELL42.IMUX.IMUX.28.DELAY	BITSLICE36.TX_D0
CELL42.IMUX.IMUX.29.DELAY	BITSLICE36.TX_D6
CELL42.IMUX.IMUX.30.DELAY	BITSLICE36.TX_D7
CELL42.IMUX.IMUX.31.DELAY	BITSLICE36.TX_CNTVALUEIN1
CELL42.IMUX.IMUX.32.DELAY	BITSLICE36.TX_CNTVALUEIN3
CELL42.IMUX.IMUX.33.DELAY	BITSLICE36.TX_CNTVALUEIN4
CELL42.IMUX.IMUX.34.DELAY	BITSLICE36.TX_CNTVALUEIN5
CELL42.IMUX.IMUX.35.DELAY	BITSLICE36.TX_CNTVALUEIN7
CELL42.IMUX.IMUX.36.DELAY	BITSLICE36.RX_CNTVALUEIN0
CELL42.IMUX.IMUX.37.DELAY	BITSLICE36.RX_CNTVALUEIN1
CELL42.IMUX.IMUX.38.DELAY	BITSLICE36.RX_CNTVALUEIN2
CELL42.IMUX.IMUX.39.DELAY	BITSLICE36.RX_CNTVALUEIN4
CELL42.IMUX.IMUX.40.DELAY	BITSLICE36.RX_CNTVALUEIN6
CELL42.IMUX.IMUX.41.DELAY	BITSLICE36.RX_CNTVALUEIN7
CELL42.IMUX.IMUX.42.DELAY	BITSLICE36.RX_CNTVALUEIN8
CELL42.IMUX.IMUX.43.DELAY	BITSLICE37.TX_CE_OFD
CELL42.IMUX.IMUX.44.DELAY	BITSLICE37.RX_DATAIN1
CELL42.IMUX.IMUX.45.DELAY	BITSLICE37.CLB2PHY_FIFO_RDEN
CELL42.IMUX.IMUX.46.DELAY	BITSLICE37.TX_D0
CELL42.IMUX.IMUX.47.DELAY	BITSLICE37.TX_D2
CELL43.OUT.0.TMIN	MMCM.TESTOUT24
CELL43.OUT.1.TMIN	MMCM.TESTOUT25
CELL43.OUT.2.TMIN	MMCM.TESTOUT26
CELL43.OUT.3.TMIN	MMCM.TESTOUT27
CELL43.OUT.4.TMIN	BITSLICE36.PHY2CLB_FIFO_EMPTY
CELL43.OUT.5.TMIN	BITSLICE36.RX_Q0
CELL43.OUT.6.TMIN	BITSLICE36.RX_Q1
CELL43.OUT.7.TMIN	BITSLICE36.RX_Q2
CELL43.OUT.8.TMIN	BITSLICE36.RX_Q3
CELL43.OUT.9.TMIN	BITSLICE36.RX_Q4
CELL43.OUT.10.TMIN	BITSLICE36.RX_Q5
CELL43.OUT.11.TMIN	BITSLICE36.RX_Q6
CELL43.OUT.12.TMIN	BITSLICE36.RX_Q7
CELL43.OUT.13.TMIN	BITSLICE36.TX_CNTVALUEOUT0
CELL43.OUT.14.TMIN	BITSLICE36.TX_CNTVALUEOUT1
CELL43.OUT.15.TMIN	BITSLICE36.TX_CNTVALUEOUT2
CELL43.OUT.16.TMIN	BITSLICE36.TX_CNTVALUEOUT3
CELL43.OUT.17.TMIN	BITSLICE36.TX_CNTVALUEOUT4
CELL43.OUT.18.TMIN	BITSLICE36.TX_CNTVALUEOUT5
CELL43.OUT.19.TMIN	BITSLICE36.TX_CNTVALUEOUT6
CELL43.OUT.20.TMIN	BITSLICE36.TX_CNTVALUEOUT7
CELL43.OUT.21.TMIN	BITSLICE36.TX_CNTVALUEOUT8
CELL43.OUT.23.TMIN	BITSLICE36.RX_CNTVALUEOUT0
CELL43.OUT.24.TMIN	BITSLICE36.RX_CNTVALUEOUT1
CELL43.OUT.25.TMIN	BITSLICE36.RX_CNTVALUEOUT2
CELL43.OUT.26.TMIN	BITSLICE36.RX_CNTVALUEOUT3
CELL43.OUT.27.TMIN	BITSLICE36.RX_CNTVALUEOUT4
CELL43.OUT.28.TMIN	BITSLICE36.RX_CNTVALUEOUT5
CELL43.OUT.29.TMIN	BITSLICE36.RX_CNTVALUEOUT6
CELL43.OUT.30.TMIN	BITSLICE36.RX_CNTVALUEOUT7
CELL43.OUT.31.TMIN	BITSLICE36.RX_CNTVALUEOUT8
CELL43.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK9
CELL43.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.TXBIT_RST_B10
CELL43.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.RXBIT_RST_B10
CELL43.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.ODELAY_RST_B10
CELL43.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.IDELAY_RST_B10
CELL43.IMUX.BYP.0	MMCM.TESTIN20
CELL43.IMUX.BYP.1	MMCM.TESTIN21
CELL43.IMUX.BYP.2	MMCM.TESTIN22
CELL43.IMUX.BYP.3	MMCM.TESTIN23
CELL43.IMUX.BYP.6	BITSLICE35.RX_CE_IDELAY
CELL43.IMUX.BYP.7	BITSLICE35.DYN_DCI_OUT_INT
CELL43.IMUX.BYP.8	BITSLICE36.TX_LD
CELL43.IMUX.BYP.9	BITSLICE36.TX_INC
CELL43.IMUX.BYP.10	BITSLICE36.TX_EN_VTC
CELL43.IMUX.BYP.11	BITSLICE36.TX_CE_ODELAY
CELL43.IMUX.BYP.12	BITSLICE36.RX_LD
CELL43.IMUX.BYP.13	BITSLICE36.RX_INC
CELL43.IMUX.BYP.14	BITSLICE36.RX_EN_VTC
CELL43.IMUX.BYP.15	BITSLICE36.RX_CE_IDELAY
CELL43.IMUX.IMUX.6.DELAY	BITSLICE37.TX_D5
CELL43.IMUX.IMUX.7.DELAY	BITSLICE37.TX_D6
CELL43.IMUX.IMUX.8.DELAY	BITSLICE37.TX_D7
CELL43.IMUX.IMUX.9.DELAY	BITSLICE37.TX_CNTVALUEIN0
CELL43.IMUX.IMUX.10.DELAY	BITSLICE37.TX_CNTVALUEIN1
CELL43.IMUX.IMUX.11.DELAY	BITSLICE37.TX_CNTVALUEIN2
CELL43.IMUX.IMUX.12.DELAY	BITSLICE37.TX_CNTVALUEIN3
CELL43.IMUX.IMUX.13.DELAY	BITSLICE37.TX_CNTVALUEIN4
CELL43.IMUX.IMUX.14.DELAY	BITSLICE37.TX_CNTVALUEIN5
CELL43.IMUX.IMUX.15.DELAY	BITSLICE37.TX_CNTVALUEIN6
CELL43.IMUX.IMUX.16.DELAY	BITSLICE37.TX_D4
CELL44.OUT.0.TMIN	MMCM.TESTOUT20
CELL44.OUT.1.TMIN	MMCM.TESTOUT21
CELL44.OUT.2.TMIN	MMCM.TESTOUT22
CELL44.OUT.3.TMIN	MMCM.TESTOUT23
CELL44.OUT.4.TMIN	BITSLICE37.PHY2CLB_FIFO_EMPTY
CELL44.OUT.5.TMIN	BITSLICE37.RX_Q0
CELL44.OUT.6.TMIN	BITSLICE37.RX_Q1
CELL44.OUT.7.TMIN	BITSLICE37.RX_Q2
CELL44.OUT.8.TMIN	BITSLICE37.RX_Q3
CELL44.OUT.9.TMIN	BITSLICE37.RX_Q4
CELL44.OUT.10.TMIN	BITSLICE37.RX_Q5
CELL44.OUT.11.TMIN	BITSLICE37.RX_Q6
CELL44.OUT.12.TMIN	BITSLICE37.RX_Q7
CELL44.OUT.13.TMIN	BITSLICE37.TX_CNTVALUEOUT0
CELL44.OUT.14.TMIN	BITSLICE37.TX_CNTVALUEOUT1
CELL44.OUT.15.TMIN	BITSLICE37.TX_CNTVALUEOUT2
CELL44.OUT.16.TMIN	BITSLICE37.TX_CNTVALUEOUT3
CELL44.OUT.17.TMIN	BITSLICE37.TX_CNTVALUEOUT4
CELL44.OUT.18.TMIN	BITSLICE37.TX_CNTVALUEOUT5
CELL44.OUT.19.TMIN	BITSLICE37.TX_CNTVALUEOUT6
CELL44.OUT.20.TMIN	BITSLICE37.TX_CNTVALUEOUT7
CELL44.OUT.21.TMIN	BITSLICE37.TX_CNTVALUEOUT8
CELL44.OUT.23.TMIN	BITSLICE37.RX_CNTVALUEOUT0
CELL44.OUT.24.TMIN	BITSLICE37.RX_CNTVALUEOUT1
CELL44.OUT.25.TMIN	BITSLICE37.RX_CNTVALUEOUT2
CELL44.OUT.26.TMIN	BITSLICE37.RX_CNTVALUEOUT3
CELL44.OUT.27.TMIN	BITSLICE37.RX_CNTVALUEOUT4
CELL44.OUT.28.TMIN	BITSLICE37.RX_CNTVALUEOUT5
CELL44.OUT.29.TMIN	BITSLICE37.RX_CNTVALUEOUT6
CELL44.OUT.30.TMIN	BITSLICE37.RX_CNTVALUEOUT7
CELL44.OUT.31.TMIN	BITSLICE37.RX_CNTVALUEOUT8
CELL44.IMUX.CTRL.2	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK10
CELL44.IMUX.CTRL.3	XIPHY_FEEDTHROUGH2.TXBIT_RST_B11
CELL44.IMUX.CTRL.4	XIPHY_FEEDTHROUGH2.RXBIT_RST_B11
CELL44.IMUX.CTRL.5	XIPHY_FEEDTHROUGH2.ODELAY_RST_B11
CELL44.IMUX.CTRL.6	XIPHY_FEEDTHROUGH2.IDELAY_RST_B11
CELL44.IMUX.CTRL.7	XIPHY_FEEDTHROUGH2.CLB2PHY_FIFO_CLK11
CELL44.IMUX.BYP.0	MMCM.TESTIN16
CELL44.IMUX.BYP.1	MMCM.TESTIN17
CELL44.IMUX.BYP.2	MMCM.TESTIN18
CELL44.IMUX.BYP.3	MMCM.TESTIN19
CELL44.IMUX.BYP.6	BITSLICE36.DYN_DCI_OUT_INT
CELL44.IMUX.BYP.7	BITSLICE37.TX_LD
CELL44.IMUX.BYP.8	BITSLICE37.TX_INC
CELL44.IMUX.BYP.9	BITSLICE37.TX_EN_VTC
CELL44.IMUX.BYP.10	BITSLICE37.TX_CE_ODELAY
CELL44.IMUX.BYP.11	BITSLICE37.RX_LD
CELL44.IMUX.BYP.12	BITSLICE37.RX_INC
CELL44.IMUX.BYP.13	BITSLICE37.RX_EN_VTC
CELL44.IMUX.BYP.14	BITSLICE37.RX_CE_IDELAY
CELL44.IMUX.BYP.15	BITSLICE37.DYN_DCI_OUT_INT
CELL44.IMUX.IMUX.6.DELAY	BITSLICE37.TX_CNTVALUEIN8
CELL44.IMUX.IMUX.7.DELAY	BITSLICE37.RX_CNTVALUEIN0
CELL44.IMUX.IMUX.8.DELAY	BITSLICE37.RX_CNTVALUEIN1
CELL44.IMUX.IMUX.9.DELAY	BITSLICE37.RX_CNTVALUEIN2
CELL44.IMUX.IMUX.10.DELAY	BITSLICE37.RX_CNTVALUEIN3
CELL44.IMUX.IMUX.11.DELAY	BITSLICE37.RX_CNTVALUEIN4
CELL44.IMUX.IMUX.12.DELAY	BITSLICE37.RX_CNTVALUEIN5
CELL44.IMUX.IMUX.13.DELAY	BITSLICE37.RX_CNTVALUEIN6
CELL44.IMUX.IMUX.14.DELAY	BITSLICE37.RX_CNTVALUEIN7
CELL44.IMUX.IMUX.15.DELAY	BITSLICE37.RX_CNTVALUEIN8
CELL44.IMUX.IMUX.16.DELAY	BITSLICE37.TX_CNTVALUEIN7
CELL45.OUT.0.TMIN	MMCM.TESTOUT16
CELL45.OUT.1.TMIN	MMCM.TESTOUT17
CELL45.OUT.2.TMIN	MMCM.TESTOUT18
CELL45.OUT.3.TMIN	MMCM.TESTOUT19
CELL45.OUT.4.TMIN	BITSLICE39.PHY2CLB_FIFO_EMPTY
CELL45.OUT.5.TMIN	BITSLICE39.RX_Q0
CELL45.OUT.6.TMIN	BITSLICE39.RX_Q1
CELL45.OUT.7.TMIN	BITSLICE39.RX_Q2
CELL45.OUT.8.TMIN	BITSLICE39.RX_Q3
CELL45.OUT.9.TMIN	BITSLICE39.RX_Q4
CELL45.OUT.10.TMIN	BITSLICE39.RX_Q5
CELL45.OUT.11.TMIN	BITSLICE39.RX_Q6
CELL45.OUT.12.TMIN	BITSLICE39.RX_Q7
CELL45.OUT.13.TMIN	BITSLICE39.TX_CNTVALUEOUT0
CELL45.OUT.14.TMIN	BITSLICE39.TX_CNTVALUEOUT1
CELL45.OUT.15.TMIN	BITSLICE39.TX_CNTVALUEOUT2
CELL45.OUT.16.TMIN	BITSLICE39.TX_CNTVALUEOUT3
CELL45.OUT.17.TMIN	BITSLICE39.TX_CNTVALUEOUT4
CELL45.OUT.18.TMIN	BITSLICE39.TX_CNTVALUEOUT5
CELL45.OUT.19.TMIN	BITSLICE39.TX_CNTVALUEOUT6
CELL45.OUT.20.TMIN	BITSLICE39.TX_CNTVALUEOUT7
CELL45.OUT.21.TMIN	BITSLICE39.TX_CNTVALUEOUT8
CELL45.OUT.22.TMIN	BITSLICE39.TX_T_OUT
CELL45.OUT.23.TMIN	BITSLICE39.RX_CNTVALUEOUT0
CELL45.OUT.24.TMIN	BITSLICE39.RX_CNTVALUEOUT1
CELL45.OUT.25.TMIN	BITSLICE39.RX_CNTVALUEOUT2
CELL45.OUT.26.TMIN	BITSLICE39.RX_CNTVALUEOUT3
CELL45.OUT.27.TMIN	BITSLICE39.RX_CNTVALUEOUT4
CELL45.OUT.28.TMIN	BITSLICE39.RX_CNTVALUEOUT5
CELL45.OUT.29.TMIN	BITSLICE39.RX_CNTVALUEOUT6
CELL45.OUT.30.TMIN	BITSLICE39.RX_CNTVALUEOUT7
CELL45.OUT.31.TMIN	BITSLICE39.RX_CNTVALUEOUT8
CELL45.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.TXBIT_TRI_RST_B0
CELL45.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.TXBIT_RST_B0
CELL45.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.RXBIT_RST_B0
CELL45.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.ODELAY_RST_B0
CELL45.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.IDELAY_RST_B0
CELL45.IMUX.BYP.0	MMCM.TESTIN12
CELL45.IMUX.BYP.1	MMCM.TESTIN13
CELL45.IMUX.BYP.2	MMCM.TESTIN14
CELL45.IMUX.BYP.3	MMCM.TESTIN15
CELL45.IMUX.BYP.6	BITSLICE_T6.EN_VTC
CELL45.IMUX.BYP.7	BITSLICE39.TX_LD
CELL45.IMUX.BYP.8	BITSLICE39.TX_INC
CELL45.IMUX.BYP.9	BITSLICE39.TX_EN_VTC
CELL45.IMUX.BYP.10	BITSLICE39.TX_CE_ODELAY
CELL45.IMUX.BYP.11	BITSLICE39.RX_LD
CELL45.IMUX.BYP.12	BITSLICE39.RX_INC
CELL45.IMUX.BYP.13	BITSLICE39.RX_EN_VTC
CELL45.IMUX.BYP.14	BITSLICE39.RX_CE_IDELAY
CELL45.IMUX.BYP.15	BITSLICE39.DYN_DCI_OUT_INT
CELL45.IMUX.IMUX.6.DELAY	BITSLICE39.TX_CE_OFD
CELL45.IMUX.IMUX.7.DELAY	BITSLICE39.RX_CE_IFD
CELL45.IMUX.IMUX.8.DELAY	BITSLICE39.RX_DATAIN1
CELL45.IMUX.IMUX.9.DELAY	BITSLICE39.CLB2PHY_FIFO_RDEN
CELL45.IMUX.IMUX.10.DELAY	BITSLICE39.TX_D7
CELL45.IMUX.IMUX.11.DELAY	BITSLICE39.TX_D6
CELL45.IMUX.IMUX.12.DELAY	BITSLICE39.TX_D5
CELL45.IMUX.IMUX.13.DELAY	BITSLICE39.TX_D4
CELL45.IMUX.IMUX.14.DELAY	BITSLICE39.TX_D3
CELL45.IMUX.IMUX.15.DELAY	BITSLICE39.TX_D2
CELL45.IMUX.IMUX.16.DELAY	BITSLICE39.TX_T
CELL46.OUT.0.TMIN	MMCM.TESTOUT12
CELL46.OUT.1.TMIN	MMCM.TESTOUT13
CELL46.OUT.2.TMIN	MMCM.TESTOUT14
CELL46.OUT.3.TMIN	MMCM.TESTOUT15
CELL46.OUT.4.TMIN	BITSLICE40.PHY2CLB_FIFO_EMPTY
CELL46.OUT.5.TMIN	BITSLICE40.RX_Q0
CELL46.OUT.6.TMIN	BITSLICE40.RX_Q1
CELL46.OUT.7.TMIN	BITSLICE40.RX_Q2
CELL46.OUT.8.TMIN	BITSLICE40.RX_Q3
CELL46.OUT.9.TMIN	BITSLICE40.RX_Q4
CELL46.OUT.10.TMIN	BITSLICE40.RX_Q5
CELL46.OUT.11.TMIN	BITSLICE40.RX_Q6
CELL46.OUT.12.TMIN	BITSLICE40.RX_Q7
CELL46.OUT.13.TMIN	BITSLICE40.TX_CNTVALUEOUT0
CELL46.OUT.14.TMIN	BITSLICE40.TX_CNTVALUEOUT1
CELL46.OUT.15.TMIN	BITSLICE40.TX_CNTVALUEOUT2
CELL46.OUT.16.TMIN	BITSLICE40.TX_CNTVALUEOUT3
CELL46.OUT.17.TMIN	BITSLICE40.TX_CNTVALUEOUT4
CELL46.OUT.18.TMIN	BITSLICE40.TX_CNTVALUEOUT5
CELL46.OUT.19.TMIN	BITSLICE40.TX_CNTVALUEOUT6
CELL46.OUT.20.TMIN	BITSLICE40.TX_CNTVALUEOUT7
CELL46.OUT.21.TMIN	BITSLICE40.TX_CNTVALUEOUT8
CELL46.OUT.22.TMIN	BITSLICE40.TX_T_OUT
CELL46.OUT.23.TMIN	BITSLICE40.RX_CNTVALUEOUT0
CELL46.OUT.24.TMIN	BITSLICE40.RX_CNTVALUEOUT1
CELL46.OUT.25.TMIN	BITSLICE40.RX_CNTVALUEOUT2
CELL46.OUT.26.TMIN	BITSLICE40.RX_CNTVALUEOUT3
CELL46.OUT.27.TMIN	BITSLICE40.RX_CNTVALUEOUT4
CELL46.OUT.28.TMIN	BITSLICE40.RX_CNTVALUEOUT5
CELL46.OUT.29.TMIN	BITSLICE40.RX_CNTVALUEOUT6
CELL46.OUT.30.TMIN	BITSLICE40.RX_CNTVALUEOUT7
CELL46.OUT.31.TMIN	BITSLICE40.RX_CNTVALUEOUT8
CELL46.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK0
CELL46.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.TXBIT_TRI_RST_B1
CELL46.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.TXBIT_RST_B1
CELL46.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.RXBIT_RST_B1
CELL46.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.ODELAY_RST_B1
CELL46.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.IDELAY_RST_B1
CELL46.IMUX.BYP.0	MMCM.TESTIN8
CELL46.IMUX.BYP.1	MMCM.TESTIN9
CELL46.IMUX.BYP.2	MMCM.TESTIN10
CELL46.IMUX.BYP.3	MMCM.TESTIN11
CELL46.IMUX.BYP.6	BITSLICE_T7.EN_VTC
CELL46.IMUX.BYP.7	BITSLICE40.TX_LD
CELL46.IMUX.BYP.8	BITSLICE40.TX_INC
CELL46.IMUX.BYP.9	BITSLICE40.TX_EN_VTC
CELL46.IMUX.BYP.10	BITSLICE40.TX_CE_ODELAY
CELL46.IMUX.BYP.11	BITSLICE40.RX_LD
CELL46.IMUX.BYP.12	BITSLICE40.RX_INC
CELL46.IMUX.BYP.13	BITSLICE40.RX_EN_VTC
CELL46.IMUX.BYP.14	BITSLICE40.RX_CE_IDELAY
CELL46.IMUX.BYP.15	BITSLICE40.DYN_DCI_OUT_INT
CELL46.IMUX.IMUX.6.DELAY	BITSLICE39.TX_D1
CELL46.IMUX.IMUX.7.DELAY	BITSLICE39.TX_CNTVALUEIN0
CELL46.IMUX.IMUX.8.DELAY	BITSLICE39.TX_CNTVALUEIN1
CELL46.IMUX.IMUX.9.DELAY	BITSLICE39.TX_CNTVALUEIN2
CELL46.IMUX.IMUX.10.DELAY	BITSLICE39.TX_CNTVALUEIN3
CELL46.IMUX.IMUX.11.DELAY	BITSLICE39.TX_CNTVALUEIN4
CELL46.IMUX.IMUX.12.DELAY	BITSLICE39.TX_CNTVALUEIN5
CELL46.IMUX.IMUX.13.DELAY	BITSLICE39.TX_CNTVALUEIN6
CELL46.IMUX.IMUX.14.DELAY	BITSLICE39.TX_CNTVALUEIN7
CELL46.IMUX.IMUX.15.DELAY	BITSLICE39.TX_CNTVALUEIN8
CELL46.IMUX.IMUX.16.DELAY	BITSLICE39.TX_D0
CELL47.OUT.0.TMIN	MMCM.TESTOUT8
CELL47.OUT.1.TMIN	MMCM.TESTOUT9
CELL47.OUT.2.TMIN	MMCM.TESTOUT10
CELL47.OUT.3.TMIN	MMCM.TESTOUT11
CELL47.OUT.4.TMIN	BITSLICE41.PHY2CLB_FIFO_EMPTY
CELL47.OUT.5.TMIN	BITSLICE41.RX_Q0
CELL47.OUT.6.TMIN	BITSLICE41.RX_Q1
CELL47.OUT.7.TMIN	BITSLICE41.RX_Q2
CELL47.OUT.8.TMIN	BITSLICE41.RX_Q3
CELL47.OUT.9.TMIN	BITSLICE41.RX_Q4
CELL47.OUT.10.TMIN	BITSLICE41.RX_Q5
CELL47.OUT.11.TMIN	BITSLICE41.RX_Q6
CELL47.OUT.12.TMIN	BITSLICE41.RX_Q7
CELL47.OUT.13.TMIN	BITSLICE41.TX_CNTVALUEOUT0
CELL47.OUT.14.TMIN	BITSLICE41.TX_CNTVALUEOUT1
CELL47.OUT.15.TMIN	BITSLICE41.TX_CNTVALUEOUT2
CELL47.OUT.16.TMIN	BITSLICE41.TX_CNTVALUEOUT3
CELL47.OUT.17.TMIN	BITSLICE41.TX_CNTVALUEOUT4
CELL47.OUT.18.TMIN	BITSLICE41.TX_CNTVALUEOUT5
CELL47.OUT.19.TMIN	BITSLICE41.TX_CNTVALUEOUT6
CELL47.OUT.20.TMIN	BITSLICE41.TX_CNTVALUEOUT7
CELL47.OUT.21.TMIN	BITSLICE41.TX_CNTVALUEOUT8
CELL47.OUT.22.TMIN	BITSLICE41.TX_T_OUT
CELL47.OUT.23.TMIN	BITSLICE41.RX_CNTVALUEOUT0
CELL47.OUT.24.TMIN	BITSLICE41.RX_CNTVALUEOUT1
CELL47.OUT.25.TMIN	BITSLICE41.RX_CNTVALUEOUT2
CELL47.OUT.26.TMIN	BITSLICE41.RX_CNTVALUEOUT3
CELL47.OUT.27.TMIN	BITSLICE41.RX_CNTVALUEOUT4
CELL47.OUT.28.TMIN	BITSLICE41.RX_CNTVALUEOUT5
CELL47.OUT.29.TMIN	BITSLICE41.RX_CNTVALUEOUT6
CELL47.OUT.30.TMIN	BITSLICE41.RX_CNTVALUEOUT7
CELL47.OUT.31.TMIN	BITSLICE41.RX_CNTVALUEOUT8
CELL47.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK1
CELL47.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.TXBIT_RST_B2
CELL47.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.RXBIT_RST_B2
CELL47.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.ODELAY_RST_B2
CELL47.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.IDELAY_RST_B2
CELL47.IMUX.BYP.0	MMCM.TESTIN4
CELL47.IMUX.BYP.1	MMCM.TESTIN5
CELL47.IMUX.BYP.2	MMCM.TESTIN6
CELL47.IMUX.BYP.3	MMCM.TESTIN7
CELL47.IMUX.BYP.6	BITSLICE41.TX_LD
CELL47.IMUX.BYP.7	BITSLICE41.TX_INC
CELL47.IMUX.BYP.8	BITSLICE41.TX_EN_VTC
CELL47.IMUX.BYP.9	BITSLICE41.TX_CE_ODELAY
CELL47.IMUX.BYP.10	BITSLICE41.RX_LD
CELL47.IMUX.BYP.11	BITSLICE41.RX_INC
CELL47.IMUX.BYP.12	BITSLICE41.RX_EN_VTC
CELL47.IMUX.BYP.13	BITSLICE41.RX_CE_IDELAY
CELL47.IMUX.BYP.14	BITSLICE41.DYN_DCI_OUT_INT
CELL47.IMUX.BYP.15	BITSLICE_T6.CE_OFD
CELL47.IMUX.IMUX.0.DELAY	MMCM.SCANMODEB
CELL47.IMUX.IMUX.6.DELAY	BITSLICE40.TX_D1
CELL47.IMUX.IMUX.7.DELAY	BITSLICE40.TX_D3
CELL47.IMUX.IMUX.8.DELAY	BITSLICE40.TX_D7
CELL47.IMUX.IMUX.9.DELAY	BITSLICE40.TX_CNTVALUEIN1
CELL47.IMUX.IMUX.10.DELAY	BITSLICE40.TX_CNTVALUEIN5
CELL47.IMUX.IMUX.11.DELAY	BITSLICE40.TX_CNTVALUEIN7
CELL47.IMUX.IMUX.12.DELAY	BITSLICE40.RX_CNTVALUEIN2
CELL47.IMUX.IMUX.13.DELAY	BITSLICE40.RX_CNTVALUEIN4
CELL47.IMUX.IMUX.14.DELAY	BITSLICE40.RX_CNTVALUEIN8
CELL47.IMUX.IMUX.15.DELAY	BITSLICE41.TX_CE_OFD
CELL47.IMUX.IMUX.16.DELAY	BITSLICE39.RX_CNTVALUEIN0
CELL47.IMUX.IMUX.17.DELAY	BITSLICE39.RX_CNTVALUEIN1
CELL47.IMUX.IMUX.18.DELAY	BITSLICE39.RX_CNTVALUEIN2
CELL47.IMUX.IMUX.19.DELAY	BITSLICE39.RX_CNTVALUEIN3
CELL47.IMUX.IMUX.20.DELAY	BITSLICE39.RX_CNTVALUEIN4
CELL47.IMUX.IMUX.21.DELAY	BITSLICE39.RX_CNTVALUEIN5
CELL47.IMUX.IMUX.22.DELAY	BITSLICE39.RX_CNTVALUEIN6
CELL47.IMUX.IMUX.23.DELAY	BITSLICE39.RX_CNTVALUEIN7
CELL47.IMUX.IMUX.24.DELAY	BITSLICE39.RX_CNTVALUEIN8
CELL47.IMUX.IMUX.25.DELAY	BITSLICE40.TX_T
CELL47.IMUX.IMUX.26.DELAY	BITSLICE40.TX_CE_OFD
CELL47.IMUX.IMUX.27.DELAY	BITSLICE40.RX_CE_IFD
CELL47.IMUX.IMUX.28.DELAY	BITSLICE40.RX_DATAIN1
CELL47.IMUX.IMUX.29.DELAY	BITSLICE40.CLB2PHY_FIFO_RDEN
CELL47.IMUX.IMUX.30.DELAY	BITSLICE40.TX_D0
CELL47.IMUX.IMUX.31.DELAY	BITSLICE40.TX_D2
CELL47.IMUX.IMUX.32.DELAY	BITSLICE40.TX_D4
CELL47.IMUX.IMUX.33.DELAY	BITSLICE40.TX_D5
CELL47.IMUX.IMUX.34.DELAY	BITSLICE40.TX_D6
CELL47.IMUX.IMUX.35.DELAY	BITSLICE40.TX_CNTVALUEIN0
CELL47.IMUX.IMUX.36.DELAY	BITSLICE40.TX_CNTVALUEIN2
CELL47.IMUX.IMUX.37.DELAY	BITSLICE40.TX_CNTVALUEIN3
CELL47.IMUX.IMUX.38.DELAY	BITSLICE40.TX_CNTVALUEIN4
CELL47.IMUX.IMUX.39.DELAY	BITSLICE40.TX_CNTVALUEIN6
CELL47.IMUX.IMUX.40.DELAY	BITSLICE40.TX_CNTVALUEIN8
CELL47.IMUX.IMUX.41.DELAY	BITSLICE40.RX_CNTVALUEIN0
CELL47.IMUX.IMUX.42.DELAY	BITSLICE40.RX_CNTVALUEIN1
CELL47.IMUX.IMUX.43.DELAY	BITSLICE40.RX_CNTVALUEIN3
CELL47.IMUX.IMUX.44.DELAY	BITSLICE40.RX_CNTVALUEIN5
CELL47.IMUX.IMUX.45.DELAY	BITSLICE40.RX_CNTVALUEIN6
CELL47.IMUX.IMUX.46.DELAY	BITSLICE40.RX_CNTVALUEIN7
CELL47.IMUX.IMUX.47.DELAY	BITSLICE41.TX_T
CELL48.OUT.0.TMIN	MMCM.TESTOUT4
CELL48.OUT.1.TMIN	MMCM.TESTOUT5
CELL48.OUT.2.TMIN	MMCM.TESTOUT6
CELL48.OUT.3.TMIN	MMCM.TESTOUT7
CELL48.OUT.4.TMIN	BITSLICE_T6.CNTVALUEOUT0
CELL48.OUT.5.TMIN	BITSLICE_T6.CNTVALUEOUT1
CELL48.OUT.6.TMIN	BITSLICE_T6.CNTVALUEOUT2
CELL48.OUT.7.TMIN	BITSLICE_T6.CNTVALUEOUT3
CELL48.OUT.8.TMIN	BITSLICE_T6.CNTVALUEOUT4
CELL48.OUT.9.TMIN	BITSLICE_T6.CNTVALUEOUT5
CELL48.OUT.10.TMIN	BITSLICE_T6.CNTVALUEOUT6
CELL48.OUT.11.TMIN	BITSLICE_T6.CNTVALUEOUT7
CELL48.OUT.12.TMIN	BITSLICE_T6.CNTVALUEOUT8
CELL48.OUT.13.TMIN	BITSLICE42.TX_T_OUT
CELL48.OUT.14.TMIN	BITSLICE_CONTROL6.PHY2CLB_PHY_RDY
CELL48.OUT.15.TMIN	BITSLICE_CONTROL6.MASTER_PD_OUT
CELL48.OUT.16.TMIN	BITSLICE_CONTROL6.PHY2CLB_FIXDLY_RDY
CELL48.OUT.17.TMIN	BITSLICE_CONTROL6.CTRL_DLY_TEST_OUT
CELL48.OUT.18.TMIN	BITSLICE42.PHY2CLB_FIFO_EMPTY
CELL48.OUT.19.TMIN	BITSLICE42.RX_Q0
CELL48.OUT.20.TMIN	BITSLICE42.RX_Q1
CELL48.OUT.21.TMIN	BITSLICE42.RX_Q2
CELL48.OUT.22.TMIN	BITSLICE42.RX_Q3
CELL48.OUT.23.TMIN	BITSLICE42.RX_Q4
CELL48.OUT.24.TMIN	BITSLICE42.RX_Q5
CELL48.OUT.25.TMIN	BITSLICE42.RX_Q6
CELL48.OUT.26.TMIN	BITSLICE42.RX_Q7
CELL48.OUT.27.TMIN	BITSLICE42.TX_CNTVALUEOUT0
CELL48.OUT.28.TMIN	BITSLICE42.TX_CNTVALUEOUT1
CELL48.OUT.29.TMIN	BITSLICE42.TX_CNTVALUEOUT2
CELL48.OUT.30.TMIN	BITSLICE42.TX_CNTVALUEOUT3
CELL48.OUT.31.TMIN	BITSLICE42.TX_CNTVALUEOUT4
CELL48.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK2
CELL48.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.TRISTATE_ODELAY_RST_B0
CELL48.IMUX.CTRL.5	BITSLICE_CONTROL6.REFCLK
CELL48.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.CTRL_RST_B_LOW
CELL48.IMUX.CTRL.7	BITSLICE_CONTROL6.RIU_CLK, XIPHY_FEEDTHROUGH3.CLB2PHY_CTRL_CLK_LOW
CELL48.IMUX.BYP.0	MMCM.TESTIN0
CELL48.IMUX.BYP.1	MMCM.TESTIN1
CELL48.IMUX.BYP.2	MMCM.TESTIN2
CELL48.IMUX.BYP.3	MMCM.TESTIN3
CELL48.IMUX.BYP.6	BITSLICE_T6.LD
CELL48.IMUX.BYP.7	BITSLICE_T6.INC
CELL48.IMUX.BYP.8	BITSLICE_T6.CE_ODELAY
CELL48.IMUX.BYP.9	BITSLICE_CONTROL6.EN_VTC
CELL48.IMUX.BYP.10	BITSLICE_CONTROL6.CTRL_DLY_TEST_IN
CELL48.IMUX.BYP.12	BITSLICE42.TX_LD
CELL48.IMUX.BYP.13	BITSLICE42.TX_INC
CELL48.IMUX.BYP.14	BITSLICE42.TX_EN_VTC
CELL48.IMUX.BYP.15	BITSLICE42.TX_CE_ODELAY
CELL48.IMUX.IMUX.0.DELAY	MMCM.SCANENB
CELL48.IMUX.IMUX.6.DELAY	BITSLICE41.TX_CNTVALUEIN3
CELL48.IMUX.IMUX.7.DELAY	BITSLICE41.TX_CNTVALUEIN5
CELL48.IMUX.IMUX.8.DELAY	BITSLICE41.RX_CNTVALUEIN0
CELL48.IMUX.IMUX.9.DELAY	BITSLICE41.RX_CNTVALUEIN2
CELL48.IMUX.IMUX.10.DELAY	BITSLICE41.RX_CNTVALUEIN6
CELL48.IMUX.IMUX.11.DELAY	BITSLICE41.RX_CNTVALUEIN8
CELL48.IMUX.IMUX.12.DELAY	BITSLICE_T6.CNTVALUEIN3
CELL48.IMUX.IMUX.13.DELAY	BITSLICE_T6.CNTVALUEIN5
CELL48.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL6.CLB2RIU_NIBBLE_SEL
CELL48.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS1_1
CELL48.IMUX.IMUX.16.DELAY	BITSLICE41.RX_CE_IFD
CELL48.IMUX.IMUX.17.DELAY	BITSLICE41.RX_DATAIN1
CELL48.IMUX.IMUX.18.DELAY	BITSLICE41.CLB2PHY_FIFO_RDEN
CELL48.IMUX.IMUX.20.DELAY	BITSLICE41.TX_D0
CELL48.IMUX.IMUX.21.DELAY	BITSLICE41.TX_D1
CELL48.IMUX.IMUX.22.DELAY	BITSLICE41.TX_D2
CELL48.IMUX.IMUX.23.DELAY	BITSLICE41.TX_D3
CELL48.IMUX.IMUX.24.DELAY	BITSLICE41.TX_D4
CELL48.IMUX.IMUX.25.DELAY	BITSLICE41.TX_D5
CELL48.IMUX.IMUX.26.DELAY	BITSLICE41.TX_D6
CELL48.IMUX.IMUX.27.DELAY	BITSLICE41.TX_D7
CELL48.IMUX.IMUX.28.DELAY	BITSLICE41.TX_CNTVALUEIN0
CELL48.IMUX.IMUX.29.DELAY	BITSLICE41.TX_CNTVALUEIN1
CELL48.IMUX.IMUX.30.DELAY	BITSLICE41.TX_CNTVALUEIN2
CELL48.IMUX.IMUX.31.DELAY	BITSLICE41.TX_CNTVALUEIN4
CELL48.IMUX.IMUX.32.DELAY	BITSLICE41.TX_CNTVALUEIN6
CELL48.IMUX.IMUX.33.DELAY	BITSLICE41.TX_CNTVALUEIN7
CELL48.IMUX.IMUX.34.DELAY	BITSLICE41.TX_CNTVALUEIN8
CELL48.IMUX.IMUX.35.DELAY	BITSLICE41.RX_CNTVALUEIN1
CELL48.IMUX.IMUX.36.DELAY	BITSLICE41.RX_CNTVALUEIN3
CELL48.IMUX.IMUX.37.DELAY	BITSLICE41.RX_CNTVALUEIN4
CELL48.IMUX.IMUX.38.DELAY	BITSLICE41.RX_CNTVALUEIN5
CELL48.IMUX.IMUX.39.DELAY	BITSLICE41.RX_CNTVALUEIN7
CELL48.IMUX.IMUX.40.DELAY	BITSLICE_T6.CNTVALUEIN0
CELL48.IMUX.IMUX.41.DELAY	BITSLICE_T6.CNTVALUEIN1
CELL48.IMUX.IMUX.42.DELAY	BITSLICE_T6.CNTVALUEIN2
CELL48.IMUX.IMUX.43.DELAY	BITSLICE_T6.CNTVALUEIN4
CELL48.IMUX.IMUX.44.DELAY	BITSLICE_T6.CNTVALUEIN6
CELL48.IMUX.IMUX.45.DELAY	BITSLICE_T6.CNTVALUEIN7
CELL48.IMUX.IMUX.46.DELAY	BITSLICE_T6.CNTVALUEIN8
CELL48.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS1_0
CELL49.OUT.0.TMIN	MMCM.TESTOUT0
CELL49.OUT.1.TMIN	MMCM.TESTOUT1
CELL49.OUT.2.TMIN	MMCM.TESTOUT2
CELL49.OUT.3.TMIN	MMCM.TESTOUT3
CELL49.OUT.4.TMIN	BITSLICE42.TX_CNTVALUEOUT5
CELL49.OUT.5.TMIN	BITSLICE42.TX_CNTVALUEOUT6
CELL49.OUT.6.TMIN	BITSLICE42.TX_CNTVALUEOUT7
CELL49.OUT.7.TMIN	BITSLICE42.TX_CNTVALUEOUT8
CELL49.OUT.8.TMIN	BITSLICE43.TX_T_OUT
CELL49.OUT.9.TMIN	BITSLICE42.RX_CNTVALUEOUT0
CELL49.OUT.10.TMIN	BITSLICE42.RX_CNTVALUEOUT1
CELL49.OUT.11.TMIN	BITSLICE42.RX_CNTVALUEOUT2
CELL49.OUT.12.TMIN	BITSLICE42.RX_CNTVALUEOUT3
CELL49.OUT.13.TMIN	BITSLICE42.RX_CNTVALUEOUT4
CELL49.OUT.14.TMIN	BITSLICE42.RX_CNTVALUEOUT5
CELL49.OUT.15.TMIN	BITSLICE42.RX_CNTVALUEOUT6
CELL49.OUT.16.TMIN	BITSLICE42.RX_CNTVALUEOUT7
CELL49.OUT.17.TMIN	BITSLICE42.RX_CNTVALUEOUT8
CELL49.OUT.18.TMIN	BITSLICE43.PHY2CLB_FIFO_EMPTY
CELL49.OUT.19.TMIN	BITSLICE43.RX_Q0
CELL49.OUT.20.TMIN	BITSLICE43.RX_Q1
CELL49.OUT.21.TMIN	BITSLICE43.RX_Q2
CELL49.OUT.22.TMIN	BITSLICE43.RX_Q3
CELL49.OUT.23.TMIN	BITSLICE43.RX_Q4
CELL49.OUT.24.TMIN	BITSLICE43.RX_Q5
CELL49.OUT.25.TMIN	BITSLICE43.RX_Q6
CELL49.OUT.26.TMIN	BITSLICE43.RX_Q7
CELL49.OUT.27.TMIN	BITSLICE43.TX_CNTVALUEOUT0
CELL49.OUT.28.TMIN	BITSLICE43.TX_CNTVALUEOUT1
CELL49.OUT.29.TMIN	BITSLICE43.TX_CNTVALUEOUT2
CELL49.OUT.30.TMIN	BITSLICE43.TX_CNTVALUEOUT3
CELL49.OUT.31.TMIN	BITSLICE43.TX_CNTVALUEOUT4
CELL49.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.TXBIT_RST_B3
CELL49.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.RXBIT_RST_B3
CELL49.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.ODELAY_RST_B3
CELL49.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.IDELAY_RST_B3
CELL49.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK3
CELL49.IMUX.BYP.0	MMCM.DADDR4
CELL49.IMUX.BYP.1	MMCM.DADDR5
CELL49.IMUX.BYP.2	MMCM.DADDR6
CELL49.IMUX.BYP.6	BITSLICE42.RX_LD
CELL49.IMUX.BYP.7	BITSLICE42.RX_INC
CELL49.IMUX.BYP.8	BITSLICE42.RX_EN_VTC
CELL49.IMUX.BYP.9	BITSLICE42.RX_CE_IDELAY
CELL49.IMUX.BYP.10	BITSLICE42.DYN_DCI_OUT_INT
CELL49.IMUX.BYP.11	BITSLICE43.TX_LD
CELL49.IMUX.BYP.12	BITSLICE43.TX_INC
CELL49.IMUX.BYP.13	BITSLICE43.TX_EN_VTC
CELL49.IMUX.BYP.14	BITSLICE43.TX_CE_ODELAY
CELL49.IMUX.BYP.15	BITSLICE43.RX_LD
CELL49.IMUX.IMUX.0.DELAY	MMCM.SCANIN
CELL49.IMUX.IMUX.6.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS1_1
CELL49.IMUX.IMUX.7.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS1_3
CELL49.IMUX.IMUX.8.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS0_3
CELL49.IMUX.IMUX.9.DELAY	BITSLICE42.TX_CE_OFD
CELL49.IMUX.IMUX.10.DELAY	BITSLICE42.TX_D0
CELL49.IMUX.IMUX.11.DELAY	BITSLICE42.TX_D2
CELL49.IMUX.IMUX.12.DELAY	BITSLICE42.TX_D6
CELL49.IMUX.IMUX.13.DELAY	BITSLICE42.TX_D7
CELL49.IMUX.IMUX.14.DELAY	BITSLICE42.TX_CNTVALUEIN3
CELL49.IMUX.IMUX.15.DELAY	BITSLICE42.TX_CNTVALUEIN5
CELL49.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS1_2
CELL49.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS1_3
CELL49.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS0_0
CELL49.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS0_1
CELL49.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS0_2
CELL49.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL6.CLB2PHY_WRCS0_3
CELL49.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL6.CLB2PHY_T_B0
CELL49.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL6.CLB2PHY_T_B1
CELL49.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL6.CLB2PHY_T_B2
CELL49.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL6.CLB2PHY_T_B3
CELL49.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDEN0
CELL49.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDEN1
CELL49.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDEN2
CELL49.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDEN3
CELL49.IMUX.IMUX.30.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS1_0
CELL49.IMUX.IMUX.31.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS1_2
CELL49.IMUX.IMUX.32.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS0_0
CELL49.IMUX.IMUX.33.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS0_1
CELL49.IMUX.IMUX.34.DELAY	BITSLICE_CONTROL6.CLB2PHY_RDCS0_2
CELL49.IMUX.IMUX.35.DELAY	BITSLICE42.TX_T
CELL49.IMUX.IMUX.36.DELAY	BITSLICE42.RX_CE_IFD
CELL49.IMUX.IMUX.37.DELAY	BITSLICE42.RX_DATAIN1
CELL49.IMUX.IMUX.38.DELAY	BITSLICE42.CLB2PHY_FIFO_RDEN
CELL49.IMUX.IMUX.39.DELAY	BITSLICE42.TX_D1
CELL49.IMUX.IMUX.40.DELAY	BITSLICE42.TX_D3
CELL49.IMUX.IMUX.41.DELAY	BITSLICE42.TX_D4
CELL49.IMUX.IMUX.42.DELAY	BITSLICE42.TX_D5
CELL49.IMUX.IMUX.44.DELAY	BITSLICE42.TX_CNTVALUEIN0
CELL49.IMUX.IMUX.45.DELAY	BITSLICE42.TX_CNTVALUEIN1
CELL49.IMUX.IMUX.46.DELAY	BITSLICE42.TX_CNTVALUEIN2
CELL49.IMUX.IMUX.47.DELAY	BITSLICE42.TX_CNTVALUEIN4
CELL50.OUT.0.TMIN	MMCM.DOUT12
CELL50.OUT.1.TMIN	MMCM.DOUT13
CELL50.OUT.2.TMIN	MMCM.DOUT14
CELL50.OUT.3.TMIN	MMCM.DOUT15
CELL50.OUT.4.TMIN	BITSLICE43.TX_CNTVALUEOUT5
CELL50.OUT.5.TMIN	BITSLICE43.TX_CNTVALUEOUT6
CELL50.OUT.6.TMIN	BITSLICE43.TX_CNTVALUEOUT7
CELL50.OUT.7.TMIN	BITSLICE43.TX_CNTVALUEOUT8
CELL50.OUT.8.TMIN	BITSLICE44.TX_T_OUT
CELL50.OUT.9.TMIN	BITSLICE43.RX_CNTVALUEOUT0
CELL50.OUT.10.TMIN	BITSLICE43.RX_CNTVALUEOUT1
CELL50.OUT.11.TMIN	BITSLICE43.RX_CNTVALUEOUT2
CELL50.OUT.12.TMIN	BITSLICE43.RX_CNTVALUEOUT3
CELL50.OUT.13.TMIN	BITSLICE43.RX_CNTVALUEOUT4
CELL50.OUT.14.TMIN	BITSLICE43.RX_CNTVALUEOUT5
CELL50.OUT.15.TMIN	BITSLICE43.RX_CNTVALUEOUT6
CELL50.OUT.16.TMIN	BITSLICE43.RX_CNTVALUEOUT7
CELL50.OUT.17.TMIN	BITSLICE43.RX_CNTVALUEOUT8
CELL50.OUT.18.TMIN	BITSLICE44.PHY2CLB_FIFO_EMPTY
CELL50.OUT.19.TMIN	BITSLICE44.RX_Q0
CELL50.OUT.20.TMIN	BITSLICE44.RX_Q1
CELL50.OUT.21.TMIN	BITSLICE44.RX_Q2
CELL50.OUT.22.TMIN	BITSLICE44.RX_Q3
CELL50.OUT.23.TMIN	BITSLICE44.RX_Q4
CELL50.OUT.24.TMIN	BITSLICE44.RX_Q5
CELL50.OUT.25.TMIN	BITSLICE44.RX_Q6
CELL50.OUT.26.TMIN	BITSLICE44.RX_Q7
CELL50.OUT.27.TMIN	BITSLICE44.TX_CNTVALUEOUT0
CELL50.OUT.28.TMIN	BITSLICE44.TX_CNTVALUEOUT1
CELL50.OUT.29.TMIN	BITSLICE44.TX_CNTVALUEOUT2
CELL50.OUT.30.TMIN	BITSLICE44.TX_CNTVALUEOUT3
CELL50.OUT.31.TMIN	BITSLICE44.TX_CNTVALUEOUT4
CELL50.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.TXBIT_RST_B4
CELL50.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.RXBIT_RST_B4
CELL50.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.ODELAY_RST_B4
CELL50.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.IDELAY_RST_B4
CELL50.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK4
CELL50.IMUX.BYP.0	MMCM.DADDR0
CELL50.IMUX.BYP.1	MMCM.DADDR1
CELL50.IMUX.BYP.2	MMCM.DADDR2
CELL50.IMUX.BYP.3	MMCM.DADDR3
CELL50.IMUX.BYP.6	BITSLICE43.RX_INC
CELL50.IMUX.BYP.7	BITSLICE43.RX_EN_VTC
CELL50.IMUX.BYP.8	BITSLICE43.RX_CE_IDELAY
CELL50.IMUX.BYP.9	BITSLICE43.DYN_DCI_OUT_INT
CELL50.IMUX.BYP.10	BITSLICE44.TX_LD
CELL50.IMUX.BYP.11	BITSLICE44.TX_INC
CELL50.IMUX.BYP.12	BITSLICE44.TX_EN_VTC
CELL50.IMUX.BYP.13	BITSLICE44.TX_CE_ODELAY
CELL50.IMUX.BYP.14	BITSLICE44.RX_LD
CELL50.IMUX.BYP.15	BITSLICE44.RX_INC
CELL50.IMUX.IMUX.0.DELAY	MMCM.CDDCREQ
CELL50.IMUX.IMUX.6.DELAY	BITSLICE43.RX_DATAIN1
CELL50.IMUX.IMUX.7.DELAY	BITSLICE43.TX_D0
CELL50.IMUX.IMUX.8.DELAY	BITSLICE43.TX_D4
CELL50.IMUX.IMUX.9.DELAY	BITSLICE43.TX_D6
CELL50.IMUX.IMUX.10.DELAY	BITSLICE43.TX_CNTVALUEIN2
CELL50.IMUX.IMUX.11.DELAY	BITSLICE43.TX_CNTVALUEIN4
CELL50.IMUX.IMUX.12.DELAY	BITSLICE43.TX_CNTVALUEIN8
CELL50.IMUX.IMUX.13.DELAY	BITSLICE43.RX_CNTVALUEIN1
CELL50.IMUX.IMUX.14.DELAY	BITSLICE43.RX_CNTVALUEIN5
CELL50.IMUX.IMUX.15.DELAY	BITSLICE43.RX_CNTVALUEIN7
CELL50.IMUX.IMUX.16.DELAY	BITSLICE42.TX_CNTVALUEIN6
CELL50.IMUX.IMUX.17.DELAY	BITSLICE42.TX_CNTVALUEIN7
CELL50.IMUX.IMUX.18.DELAY	BITSLICE42.TX_CNTVALUEIN8
CELL50.IMUX.IMUX.19.DELAY	BITSLICE42.RX_CNTVALUEIN0
CELL50.IMUX.IMUX.20.DELAY	BITSLICE42.RX_CNTVALUEIN1
CELL50.IMUX.IMUX.21.DELAY	BITSLICE42.RX_CNTVALUEIN2
CELL50.IMUX.IMUX.22.DELAY	BITSLICE42.RX_CNTVALUEIN3
CELL50.IMUX.IMUX.23.DELAY	BITSLICE42.RX_CNTVALUEIN4
CELL50.IMUX.IMUX.24.DELAY	BITSLICE42.RX_CNTVALUEIN5
CELL50.IMUX.IMUX.25.DELAY	BITSLICE42.RX_CNTVALUEIN6
CELL50.IMUX.IMUX.26.DELAY	BITSLICE42.RX_CNTVALUEIN7
CELL50.IMUX.IMUX.27.DELAY	BITSLICE42.RX_CNTVALUEIN8
CELL50.IMUX.IMUX.28.DELAY	BITSLICE43.TX_T
CELL50.IMUX.IMUX.29.DELAY	BITSLICE43.TX_CE_OFD
CELL50.IMUX.IMUX.30.DELAY	BITSLICE43.RX_CE_IFD
CELL50.IMUX.IMUX.31.DELAY	BITSLICE43.CLB2PHY_FIFO_RDEN
CELL50.IMUX.IMUX.32.DELAY	BITSLICE43.TX_D1
CELL50.IMUX.IMUX.33.DELAY	BITSLICE43.TX_D2
CELL50.IMUX.IMUX.34.DELAY	BITSLICE43.TX_D3
CELL50.IMUX.IMUX.35.DELAY	BITSLICE43.TX_D5
CELL50.IMUX.IMUX.36.DELAY	BITSLICE43.TX_D7
CELL50.IMUX.IMUX.37.DELAY	BITSLICE43.TX_CNTVALUEIN0
CELL50.IMUX.IMUX.38.DELAY	BITSLICE43.TX_CNTVALUEIN1
CELL50.IMUX.IMUX.39.DELAY	BITSLICE43.TX_CNTVALUEIN3
CELL50.IMUX.IMUX.40.DELAY	BITSLICE43.TX_CNTVALUEIN5
CELL50.IMUX.IMUX.41.DELAY	BITSLICE43.TX_CNTVALUEIN6
CELL50.IMUX.IMUX.42.DELAY	BITSLICE43.TX_CNTVALUEIN7
CELL50.IMUX.IMUX.43.DELAY	BITSLICE43.RX_CNTVALUEIN0
CELL50.IMUX.IMUX.44.DELAY	BITSLICE43.RX_CNTVALUEIN2
CELL50.IMUX.IMUX.45.DELAY	BITSLICE43.RX_CNTVALUEIN3
CELL50.IMUX.IMUX.46.DELAY	BITSLICE43.RX_CNTVALUEIN4
CELL50.IMUX.IMUX.47.DELAY	BITSLICE43.RX_CNTVALUEIN6
CELL51.OUT.0.TMIN	MMCM.DOUT8
CELL51.OUT.1.TMIN	MMCM.DOUT9
CELL51.OUT.2.TMIN	MMCM.DOUT10
CELL51.OUT.3.TMIN	MMCM.DOUT11
CELL51.OUT.4.TMIN	BITSLICE44.TX_CNTVALUEOUT5
CELL51.OUT.5.TMIN	BITSLICE44.TX_CNTVALUEOUT6
CELL51.OUT.6.TMIN	BITSLICE44.TX_CNTVALUEOUT7
CELL51.OUT.7.TMIN	BITSLICE44.TX_CNTVALUEOUT8
CELL51.OUT.8.TMIN	BITSLICE45.TX_T_OUT
CELL51.OUT.9.TMIN	BITSLICE44.RX_CNTVALUEOUT0
CELL51.OUT.10.TMIN	BITSLICE44.RX_CNTVALUEOUT1
CELL51.OUT.11.TMIN	BITSLICE44.RX_CNTVALUEOUT2
CELL51.OUT.12.TMIN	BITSLICE44.RX_CNTVALUEOUT3
CELL51.OUT.13.TMIN	BITSLICE44.RX_CNTVALUEOUT4
CELL51.OUT.14.TMIN	BITSLICE44.RX_CNTVALUEOUT5
CELL51.OUT.15.TMIN	BITSLICE44.RX_CNTVALUEOUT6
CELL51.OUT.16.TMIN	BITSLICE44.RX_CNTVALUEOUT7
CELL51.OUT.17.TMIN	BITSLICE44.RX_CNTVALUEOUT8
CELL51.OUT.18.TMIN	RIU_OR3.RIU_RD_VALID
CELL51.OUT.19.TMIN	RIU_OR3.RIU_RD_DATA0
CELL51.OUT.20.TMIN	RIU_OR3.RIU_RD_DATA1
CELL51.OUT.21.TMIN	RIU_OR3.RIU_RD_DATA2
CELL51.OUT.22.TMIN	RIU_OR3.RIU_RD_DATA3
CELL51.OUT.23.TMIN	RIU_OR3.RIU_RD_DATA4
CELL51.OUT.24.TMIN	RIU_OR3.RIU_RD_DATA5
CELL51.OUT.25.TMIN	RIU_OR3.RIU_RD_DATA6
CELL51.OUT.26.TMIN	RIU_OR3.RIU_RD_DATA7
CELL51.OUT.27.TMIN	RIU_OR3.RIU_RD_DATA8
CELL51.OUT.28.TMIN	RIU_OR3.RIU_RD_DATA9
CELL51.OUT.29.TMIN	RIU_OR3.RIU_RD_DATA10
CELL51.OUT.30.TMIN	RIU_OR3.RIU_RD_DATA11
CELL51.OUT.31.TMIN	RIU_OR3.RIU_RD_DATA12
CELL51.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.TXBIT_RST_B5
CELL51.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.RXBIT_RST_B5
CELL51.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.ODELAY_RST_B5
CELL51.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.IDELAY_RST_B5
CELL51.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK5
CELL51.IMUX.BYP.0	MMCM.DI12
CELL51.IMUX.BYP.1	MMCM.DI13
CELL51.IMUX.BYP.2	MMCM.DI14
CELL51.IMUX.BYP.3	MMCM.DI15
CELL51.IMUX.BYP.6	BITSLICE44.RX_EN_VTC
CELL51.IMUX.BYP.7	BITSLICE44.RX_CE_IDELAY
CELL51.IMUX.BYP.8	BITSLICE44.DYN_DCI_OUT_INT
CELL51.IMUX.BYP.9	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B0
CELL51.IMUX.BYP.10	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B1
CELL51.IMUX.BYP.11	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B2
CELL51.IMUX.BYP.12	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SPARE_B3
CELL51.IMUX.BYP.13	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_RST_MASK_B
CELL51.IMUX.BYP.14	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_MODE_B
CELL51.IMUX.BYP.15	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN0
CELL51.IMUX.IMUX.0.DELAY	MMCM.DWE
CELL51.IMUX.IMUX.6.DELAY	BITSLICE44.TX_CNTVALUEIN1
CELL51.IMUX.IMUX.7.DELAY	BITSLICE44.TX_CNTVALUEIN3
CELL51.IMUX.IMUX.8.DELAY	BITSLICE44.TX_CNTVALUEIN7
CELL51.IMUX.IMUX.10.DELAY	BITSLICE44.RX_CNTVALUEIN3
CELL51.IMUX.IMUX.11.DELAY	BITSLICE44.RX_CNTVALUEIN5
CELL51.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_EN, BITSLICE_CONTROL7.CLB2RIU_WR_EN
CELL51.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA1, BITSLICE_CONTROL7.CLB2RIU_WR_DATA1
CELL51.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA5, BITSLICE_CONTROL7.CLB2RIU_WR_DATA5
CELL51.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA7, BITSLICE_CONTROL7.CLB2RIU_WR_DATA7
CELL51.IMUX.IMUX.16.DELAY	BITSLICE43.RX_CNTVALUEIN8
CELL51.IMUX.IMUX.17.DELAY	BITSLICE44.TX_T
CELL51.IMUX.IMUX.18.DELAY	BITSLICE44.TX_CE_OFD
CELL51.IMUX.IMUX.19.DELAY	BITSLICE44.RX_CE_IFD
CELL51.IMUX.IMUX.20.DELAY	BITSLICE44.RX_DATAIN1
CELL51.IMUX.IMUX.21.DELAY	BITSLICE44.CLB2PHY_FIFO_RDEN
CELL51.IMUX.IMUX.22.DELAY	BITSLICE44.TX_D0
CELL51.IMUX.IMUX.23.DELAY	BITSLICE44.TX_D1
CELL51.IMUX.IMUX.24.DELAY	BITSLICE44.TX_D2
CELL51.IMUX.IMUX.25.DELAY	BITSLICE44.TX_D3
CELL51.IMUX.IMUX.26.DELAY	BITSLICE44.TX_D4
CELL51.IMUX.IMUX.27.DELAY	BITSLICE44.TX_D5
CELL51.IMUX.IMUX.28.DELAY	BITSLICE44.TX_D6
CELL51.IMUX.IMUX.29.DELAY	BITSLICE44.TX_D7
CELL51.IMUX.IMUX.30.DELAY	BITSLICE44.TX_CNTVALUEIN0
CELL51.IMUX.IMUX.31.DELAY	BITSLICE44.TX_CNTVALUEIN2
CELL51.IMUX.IMUX.32.DELAY	BITSLICE44.TX_CNTVALUEIN4
CELL51.IMUX.IMUX.33.DELAY	BITSLICE44.TX_CNTVALUEIN5
CELL51.IMUX.IMUX.34.DELAY	BITSLICE44.TX_CNTVALUEIN6
CELL51.IMUX.IMUX.35.DELAY	BITSLICE44.TX_CNTVALUEIN8
CELL51.IMUX.IMUX.36.DELAY	BITSLICE44.RX_CNTVALUEIN0
CELL51.IMUX.IMUX.37.DELAY	BITSLICE44.RX_CNTVALUEIN1
CELL51.IMUX.IMUX.38.DELAY	BITSLICE44.RX_CNTVALUEIN2
CELL51.IMUX.IMUX.39.DELAY	BITSLICE44.RX_CNTVALUEIN4
CELL51.IMUX.IMUX.40.DELAY	BITSLICE44.RX_CNTVALUEIN6
CELL51.IMUX.IMUX.41.DELAY	BITSLICE44.RX_CNTVALUEIN7
CELL51.IMUX.IMUX.42.DELAY	BITSLICE44.RX_CNTVALUEIN8
CELL51.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA0, BITSLICE_CONTROL7.CLB2RIU_WR_DATA0
CELL51.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA2, BITSLICE_CONTROL7.CLB2RIU_WR_DATA2
CELL51.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA3, BITSLICE_CONTROL7.CLB2RIU_WR_DATA3
CELL51.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA4, BITSLICE_CONTROL7.CLB2RIU_WR_DATA4
CELL51.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA6, BITSLICE_CONTROL7.CLB2RIU_WR_DATA6
CELL52.OUT.0.TMIN	MMCM.DOUT4
CELL52.OUT.1.TMIN	MMCM.DOUT5
CELL52.OUT.2.TMIN	MMCM.DOUT6
CELL52.OUT.3.TMIN	MMCM.DOUT7
CELL52.OUT.4.TMIN	RIU_OR3.RIU_RD_DATA13
CELL52.OUT.5.TMIN	RIU_OR3.RIU_RD_DATA14
CELL52.OUT.6.TMIN	RIU_OR3.RIU_RD_DATA15
CELL52.OUT.7.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT0
CELL52.OUT.8.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT1
CELL52.OUT.9.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT2
CELL52.OUT.10.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT3
CELL52.OUT.11.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT4
CELL52.OUT.12.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT5
CELL52.OUT.13.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT6
CELL52.OUT.14.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_SCAN_OUT7
CELL52.OUT.15.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_OUT
CELL52.OUT.16.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_FLG_OUT
CELL52.OUT.17.TMIN	XIPHY_FEEDTHROUGH3.PHY2CLB_DBG_CLK_STOP_FLG_DLY_OUT
CELL52.OUT.18.TMIN	BITSLICE51.PHY2CLB_FIFO_EMPTY
CELL52.OUT.19.TMIN	BITSLICE51.RX_Q0
CELL52.OUT.20.TMIN	BITSLICE51.RX_Q1
CELL52.OUT.21.TMIN	BITSLICE51.RX_Q2
CELL52.OUT.22.TMIN	BITSLICE51.RX_Q3
CELL52.OUT.23.TMIN	BITSLICE51.RX_Q4
CELL52.OUT.24.TMIN	BITSLICE51.RX_Q5
CELL52.OUT.25.TMIN	BITSLICE51.RX_Q6
CELL52.OUT.26.TMIN	BITSLICE51.RX_Q7
CELL52.OUT.27.TMIN	BITSLICE51.TX_CNTVALUEOUT0
CELL52.OUT.28.TMIN	BITSLICE51.TX_CNTVALUEOUT1
CELL52.OUT.29.TMIN	BITSLICE51.TX_CNTVALUEOUT2
CELL52.OUT.30.TMIN	BITSLICE51.TX_CNTVALUEOUT3
CELL52.OUT.31.TMIN	BITSLICE51.TX_CNTVALUEOUT4
CELL52.IMUX.CTRL.0	MMCM.DCLK_B
CELL52.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_SDR
CELL52.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_DIV4
CELL52.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_CLK_DIV2
CELL52.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.TXBIT_RST_B12
CELL52.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.RXBIT_RST_B12
CELL52.IMUX.BYP.0	MMCM.DI8
CELL52.IMUX.BYP.1	MMCM.DI9
CELL52.IMUX.BYP.2	MMCM.DI10
CELL52.IMUX.BYP.3	MMCM.DI11
CELL52.IMUX.BYP.6	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN1
CELL52.IMUX.BYP.7	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN2
CELL52.IMUX.BYP.8	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN3
CELL52.IMUX.BYP.10	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN4
CELL52.IMUX.BYP.11	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN5
CELL52.IMUX.BYP.12	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN6
CELL52.IMUX.BYP.13	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_IN7
CELL52.IMUX.BYP.14	XIPHY_FEEDTHROUGH3.CLB2PHY_SCAN_EN_B
CELL52.IMUX.BYP.15	BITSLICE51.TX_LD
CELL52.IMUX.IMUX.0.DELAY	MMCM.DEN
CELL52.IMUX.IMUX.6.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_DIV4_CLK_SEL_B
CELL52.IMUX.IMUX.7.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CT_START_EN
CELL52.IMUX.IMUX.8.DELAY	BITSLICE51.TX_CE_OFD
CELL52.IMUX.IMUX.9.DELAY	BITSLICE51.RX_DATAIN1
CELL52.IMUX.IMUX.10.DELAY	BITSLICE51.TX_D2
CELL52.IMUX.IMUX.11.DELAY	BITSLICE51.TX_D4
CELL52.IMUX.IMUX.12.DELAY	BITSLICE51.TX_CNTVALUEIN0
CELL52.IMUX.IMUX.13.DELAY	BITSLICE51.TX_CNTVALUEIN2
CELL52.IMUX.IMUX.14.DELAY	BITSLICE51.TX_CNTVALUEIN6
CELL52.IMUX.IMUX.15.DELAY	BITSLICE51.TX_CNTVALUEIN8
CELL52.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA8, BITSLICE_CONTROL7.CLB2RIU_WR_DATA8
CELL52.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA9, BITSLICE_CONTROL7.CLB2RIU_WR_DATA9
CELL52.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA10, BITSLICE_CONTROL7.CLB2RIU_WR_DATA10
CELL52.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA11, BITSLICE_CONTROL7.CLB2RIU_WR_DATA11
CELL52.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA12, BITSLICE_CONTROL7.CLB2RIU_WR_DATA12
CELL52.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA13, BITSLICE_CONTROL7.CLB2RIU_WR_DATA13
CELL52.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA14, BITSLICE_CONTROL7.CLB2RIU_WR_DATA14
CELL52.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL6.CLB2RIU_WR_DATA15, BITSLICE_CONTROL7.CLB2RIU_WR_DATA15
CELL52.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR0, BITSLICE_CONTROL7.CLB2RIU_ADDR0
CELL52.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR1, BITSLICE_CONTROL7.CLB2RIU_ADDR1
CELL52.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR2, BITSLICE_CONTROL7.CLB2RIU_ADDR2
CELL52.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR3, BITSLICE_CONTROL7.CLB2RIU_ADDR3
CELL52.IMUX.IMUX.28.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR4, BITSLICE_CONTROL7.CLB2RIU_ADDR4
CELL52.IMUX.IMUX.29.DELAY	BITSLICE_CONTROL6.CLB2RIU_ADDR5, BITSLICE_CONTROL7.CLB2RIU_ADDR5
CELL52.IMUX.IMUX.30.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_SDR_CLK_SEL_B
CELL52.IMUX.IMUX.31.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_TEST_DIV2_CLK_SEL_B
CELL52.IMUX.IMUX.32.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CLK_STOP_FLG_OUT
CELL52.IMUX.IMUX.33.DELAY	XIPHY_FEEDTHROUGH3.CLB2PHY_DBG_CLK_STOP_FLG_DLY_OUT
CELL52.IMUX.IMUX.34.DELAY	BITSLICE51.TX_T
CELL52.IMUX.IMUX.35.DELAY	BITSLICE51.RX_CE_IFD
CELL52.IMUX.IMUX.36.DELAY	BITSLICE51.CLB2PHY_FIFO_RDEN
CELL52.IMUX.IMUX.37.DELAY	BITSLICE51.TX_D0
CELL52.IMUX.IMUX.38.DELAY	BITSLICE51.TX_D1
CELL52.IMUX.IMUX.39.DELAY	BITSLICE51.TX_D3
CELL52.IMUX.IMUX.40.DELAY	BITSLICE51.TX_D5
CELL52.IMUX.IMUX.41.DELAY	BITSLICE51.TX_D6
CELL52.IMUX.IMUX.42.DELAY	BITSLICE51.TX_D7
CELL52.IMUX.IMUX.43.DELAY	BITSLICE51.TX_CNTVALUEIN1
CELL52.IMUX.IMUX.44.DELAY	BITSLICE51.TX_CNTVALUEIN3
CELL52.IMUX.IMUX.45.DELAY	BITSLICE51.TX_CNTVALUEIN4
CELL52.IMUX.IMUX.46.DELAY	BITSLICE51.TX_CNTVALUEIN5
CELL52.IMUX.IMUX.47.DELAY	BITSLICE51.TX_CNTVALUEIN7
CELL53.OUT.0.TMIN	MMCM.DOUT0
CELL53.OUT.1.TMIN	MMCM.DOUT1
CELL53.OUT.2.TMIN	MMCM.DOUT2
CELL53.OUT.3.TMIN	MMCM.DOUT3
CELL53.OUT.4.TMIN	BITSLICE51.TX_CNTVALUEOUT5
CELL53.OUT.5.TMIN	BITSLICE51.TX_CNTVALUEOUT6
CELL53.OUT.6.TMIN	BITSLICE51.TX_CNTVALUEOUT7
CELL53.OUT.7.TMIN	BITSLICE51.TX_CNTVALUEOUT8
CELL53.OUT.8.TMIN	BITSLICE46.TX_T_OUT
CELL53.OUT.9.TMIN	BITSLICE51.RX_CNTVALUEOUT0
CELL53.OUT.10.TMIN	BITSLICE51.RX_CNTVALUEOUT1
CELL53.OUT.11.TMIN	BITSLICE51.RX_CNTVALUEOUT2
CELL53.OUT.12.TMIN	BITSLICE51.RX_CNTVALUEOUT3
CELL53.OUT.13.TMIN	BITSLICE51.RX_CNTVALUEOUT4
CELL53.OUT.14.TMIN	BITSLICE51.RX_CNTVALUEOUT5
CELL53.OUT.15.TMIN	BITSLICE51.RX_CNTVALUEOUT6
CELL53.OUT.16.TMIN	BITSLICE51.RX_CNTVALUEOUT7
CELL53.OUT.17.TMIN	BITSLICE51.RX_CNTVALUEOUT8
CELL53.OUT.18.TMIN	BITSLICE45.PHY2CLB_FIFO_EMPTY
CELL53.OUT.19.TMIN	BITSLICE45.RX_Q0
CELL53.OUT.20.TMIN	BITSLICE45.RX_Q1
CELL53.OUT.21.TMIN	BITSLICE45.RX_Q2
CELL53.OUT.22.TMIN	BITSLICE45.RX_Q3
CELL53.OUT.23.TMIN	BITSLICE45.RX_Q4
CELL53.OUT.24.TMIN	BITSLICE45.RX_Q5
CELL53.OUT.25.TMIN	BITSLICE45.RX_Q6
CELL53.OUT.26.TMIN	BITSLICE45.RX_Q7
CELL53.OUT.27.TMIN	BITSLICE45.TX_CNTVALUEOUT0
CELL53.OUT.28.TMIN	BITSLICE45.TX_CNTVALUEOUT1
CELL53.OUT.29.TMIN	BITSLICE45.TX_CNTVALUEOUT2
CELL53.OUT.30.TMIN	BITSLICE45.TX_CNTVALUEOUT3
CELL53.OUT.31.TMIN	BITSLICE45.TX_CNTVALUEOUT4
CELL53.IMUX.CTRL.0	MMCM.PSCLK_B
CELL53.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.ODELAY_RST_B12
CELL53.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.IDELAY_RST_B12
CELL53.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK12
CELL53.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.TXBIT_RST_B6
CELL53.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.RXBIT_RST_B6
CELL53.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.ODELAY_RST_B6
CELL53.IMUX.BYP.0	MMCM.DI4
CELL53.IMUX.BYP.1	MMCM.DI5
CELL53.IMUX.BYP.2	MMCM.DI6
CELL53.IMUX.BYP.3	MMCM.DI7
CELL53.IMUX.BYP.6	BITSLICE51.TX_INC
CELL53.IMUX.BYP.7	BITSLICE51.TX_EN_VTC
CELL53.IMUX.BYP.8	BITSLICE51.TX_CE_ODELAY
CELL53.IMUX.BYP.9	BITSLICE51.RX_LD
CELL53.IMUX.BYP.10	BITSLICE51.RX_INC
CELL53.IMUX.BYP.11	BITSLICE51.RX_EN_VTC
CELL53.IMUX.BYP.12	BITSLICE51.RX_CE_IDELAY
CELL53.IMUX.BYP.13	BITSLICE51.DYN_DCI_OUT_INT
CELL53.IMUX.BYP.14	BITSLICE45.TX_LD
CELL53.IMUX.BYP.15	BITSLICE45.TX_INC
CELL53.IMUX.IMUX.0.DELAY	MMCM.PWRDWN
CELL53.IMUX.IMUX.6.DELAY	BITSLICE45.TX_D0
CELL53.IMUX.IMUX.7.DELAY	BITSLICE45.TX_D2
CELL53.IMUX.IMUX.8.DELAY	BITSLICE45.TX_D6
CELL53.IMUX.IMUX.9.DELAY	BITSLICE45.TX_CNTVALUEIN0
CELL53.IMUX.IMUX.10.DELAY	BITSLICE45.TX_CNTVALUEIN4
CELL53.IMUX.IMUX.11.DELAY	BITSLICE45.TX_CNTVALUEIN6
CELL53.IMUX.IMUX.12.DELAY	BITSLICE45.RX_CNTVALUEIN1
CELL53.IMUX.IMUX.13.DELAY	BITSLICE45.RX_CNTVALUEIN3
CELL53.IMUX.IMUX.14.DELAY	BITSLICE45.RX_CNTVALUEIN7
CELL53.IMUX.IMUX.15.DELAY	BITSLICE46.TX_T
CELL53.IMUX.IMUX.16.DELAY	BITSLICE51.RX_CNTVALUEIN0
CELL53.IMUX.IMUX.17.DELAY	BITSLICE51.RX_CNTVALUEIN1
CELL53.IMUX.IMUX.18.DELAY	BITSLICE51.RX_CNTVALUEIN2
CELL53.IMUX.IMUX.19.DELAY	BITSLICE51.RX_CNTVALUEIN3
CELL53.IMUX.IMUX.20.DELAY	BITSLICE51.RX_CNTVALUEIN4
CELL53.IMUX.IMUX.21.DELAY	BITSLICE51.RX_CNTVALUEIN5
CELL53.IMUX.IMUX.22.DELAY	BITSLICE51.RX_CNTVALUEIN6
CELL53.IMUX.IMUX.23.DELAY	BITSLICE51.RX_CNTVALUEIN7
CELL53.IMUX.IMUX.24.DELAY	BITSLICE51.RX_CNTVALUEIN8
CELL53.IMUX.IMUX.25.DELAY	BITSLICE45.TX_T
CELL53.IMUX.IMUX.26.DELAY	BITSLICE45.TX_CE_OFD
CELL53.IMUX.IMUX.27.DELAY	BITSLICE45.RX_CE_IFD
CELL53.IMUX.IMUX.29.DELAY	BITSLICE45.RX_DATAIN1
CELL53.IMUX.IMUX.30.DELAY	BITSLICE45.CLB2PHY_FIFO_RDEN
CELL53.IMUX.IMUX.31.DELAY	BITSLICE45.TX_D1
CELL53.IMUX.IMUX.32.DELAY	BITSLICE45.TX_D3
CELL53.IMUX.IMUX.33.DELAY	BITSLICE45.TX_D4
CELL53.IMUX.IMUX.34.DELAY	BITSLICE45.TX_D5
CELL53.IMUX.IMUX.35.DELAY	BITSLICE45.TX_D7
CELL53.IMUX.IMUX.36.DELAY	BITSLICE45.TX_CNTVALUEIN1
CELL53.IMUX.IMUX.37.DELAY	BITSLICE45.TX_CNTVALUEIN2
CELL53.IMUX.IMUX.38.DELAY	BITSLICE45.TX_CNTVALUEIN3
CELL53.IMUX.IMUX.39.DELAY	BITSLICE45.TX_CNTVALUEIN5
CELL53.IMUX.IMUX.40.DELAY	BITSLICE45.TX_CNTVALUEIN7
CELL53.IMUX.IMUX.41.DELAY	BITSLICE45.TX_CNTVALUEIN8
CELL53.IMUX.IMUX.42.DELAY	BITSLICE45.RX_CNTVALUEIN0
CELL53.IMUX.IMUX.43.DELAY	BITSLICE45.RX_CNTVALUEIN2
CELL53.IMUX.IMUX.44.DELAY	BITSLICE45.RX_CNTVALUEIN4
CELL53.IMUX.IMUX.45.DELAY	BITSLICE45.RX_CNTVALUEIN5
CELL53.IMUX.IMUX.46.DELAY	BITSLICE45.RX_CNTVALUEIN6
CELL53.IMUX.IMUX.47.DELAY	BITSLICE45.RX_CNTVALUEIN8
CELL54.OUT.0.TMIN	MMCM.DRDY
CELL54.OUT.1.TMIN	MMCM.LOCKED
CELL54.OUT.2.TMIN	MMCM.TESTOUT36
CELL54.OUT.3.TMIN	MMCM.SCANOUT
CELL54.OUT.4.TMIN	BITSLICE45.TX_CNTVALUEOUT5
CELL54.OUT.5.TMIN	BITSLICE45.TX_CNTVALUEOUT6
CELL54.OUT.6.TMIN	BITSLICE45.TX_CNTVALUEOUT7
CELL54.OUT.7.TMIN	BITSLICE45.TX_CNTVALUEOUT8
CELL54.OUT.8.TMIN	BITSLICE47.TX_T_OUT
CELL54.OUT.9.TMIN	BITSLICE45.RX_CNTVALUEOUT0
CELL54.OUT.10.TMIN	BITSLICE45.RX_CNTVALUEOUT1
CELL54.OUT.11.TMIN	BITSLICE45.RX_CNTVALUEOUT2
CELL54.OUT.12.TMIN	BITSLICE45.RX_CNTVALUEOUT3
CELL54.OUT.13.TMIN	BITSLICE45.RX_CNTVALUEOUT4
CELL54.OUT.14.TMIN	BITSLICE45.RX_CNTVALUEOUT5
CELL54.OUT.15.TMIN	BITSLICE45.RX_CNTVALUEOUT6
CELL54.OUT.16.TMIN	BITSLICE45.RX_CNTVALUEOUT7
CELL54.OUT.17.TMIN	BITSLICE45.RX_CNTVALUEOUT8
CELL54.OUT.18.TMIN	BITSLICE46.PHY2CLB_FIFO_EMPTY
CELL54.OUT.19.TMIN	BITSLICE46.RX_Q0
CELL54.OUT.20.TMIN	BITSLICE46.RX_Q1
CELL54.OUT.21.TMIN	BITSLICE46.RX_Q2
CELL54.OUT.22.TMIN	BITSLICE46.RX_Q3
CELL54.OUT.23.TMIN	BITSLICE46.RX_Q4
CELL54.OUT.24.TMIN	BITSLICE46.RX_Q5
CELL54.OUT.25.TMIN	BITSLICE46.RX_Q6
CELL54.OUT.26.TMIN	BITSLICE46.RX_Q7
CELL54.OUT.27.TMIN	BITSLICE46.TX_CNTVALUEOUT0
CELL54.OUT.28.TMIN	BITSLICE46.TX_CNTVALUEOUT1
CELL54.OUT.29.TMIN	BITSLICE46.TX_CNTVALUEOUT2
CELL54.OUT.30.TMIN	BITSLICE46.TX_CNTVALUEOUT3
CELL54.OUT.31.TMIN	BITSLICE46.TX_CNTVALUEOUT4
CELL54.IMUX.CTRL.0	MMCM.SCANCLK_B
CELL54.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.IDELAY_RST_B6
CELL54.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK6
CELL54.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.TXBIT_RST_B7
CELL54.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.RXBIT_RST_B7
CELL54.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.ODELAY_RST_B7
CELL54.IMUX.BYP.0	MMCM.DI0
CELL54.IMUX.BYP.1	MMCM.DI1
CELL54.IMUX.BYP.2	MMCM.DI2
CELL54.IMUX.BYP.3	MMCM.DI3
CELL54.IMUX.BYP.6	BITSLICE45.TX_EN_VTC
CELL54.IMUX.BYP.7	BITSLICE45.TX_CE_ODELAY
CELL54.IMUX.BYP.8	BITSLICE45.RX_LD
CELL54.IMUX.BYP.9	BITSLICE45.RX_INC
CELL54.IMUX.BYP.10	BITSLICE45.RX_EN_VTC
CELL54.IMUX.BYP.11	BITSLICE45.RX_CE_IDELAY
CELL54.IMUX.BYP.12	BITSLICE45.DYN_DCI_OUT_INT
CELL54.IMUX.BYP.14	BITSLICE46.TX_LD
CELL54.IMUX.BYP.15	BITSLICE46.TX_INC
CELL54.IMUX.IMUX.0.DELAY	MMCM.RST
CELL54.IMUX.IMUX.6.DELAY	BITSLICE46.TX_CNTVALUEIN3
CELL54.IMUX.IMUX.7.DELAY	BITSLICE46.TX_CNTVALUEIN5
CELL54.IMUX.IMUX.8.DELAY	BITSLICE46.RX_CNTVALUEIN0
CELL54.IMUX.IMUX.9.DELAY	BITSLICE46.RX_CNTVALUEIN2
CELL54.IMUX.IMUX.10.DELAY	BITSLICE46.RX_CNTVALUEIN6
CELL54.IMUX.IMUX.11.DELAY	BITSLICE46.RX_CNTVALUEIN8
CELL54.IMUX.IMUX.12.DELAY	BITSLICE47.RX_DATAIN1
CELL54.IMUX.IMUX.13.DELAY	BITSLICE47.TX_D0
CELL54.IMUX.IMUX.14.DELAY	BITSLICE47.TX_D4
CELL54.IMUX.IMUX.15.DELAY	BITSLICE47.TX_D6
CELL54.IMUX.IMUX.16.DELAY	BITSLICE46.TX_CE_OFD
CELL54.IMUX.IMUX.17.DELAY	BITSLICE46.RX_CE_IFD
CELL54.IMUX.IMUX.18.DELAY	BITSLICE46.RX_DATAIN1
CELL54.IMUX.IMUX.19.DELAY	BITSLICE46.CLB2PHY_FIFO_RDEN
CELL54.IMUX.IMUX.20.DELAY	BITSLICE46.TX_D0
CELL54.IMUX.IMUX.21.DELAY	BITSLICE46.TX_D1
CELL54.IMUX.IMUX.22.DELAY	BITSLICE46.TX_D2
CELL54.IMUX.IMUX.23.DELAY	BITSLICE46.TX_D3
CELL54.IMUX.IMUX.24.DELAY	BITSLICE46.TX_D4
CELL54.IMUX.IMUX.25.DELAY	BITSLICE46.TX_D5
CELL54.IMUX.IMUX.26.DELAY	BITSLICE46.TX_D6
CELL54.IMUX.IMUX.27.DELAY	BITSLICE46.TX_D7
CELL54.IMUX.IMUX.28.DELAY	BITSLICE46.TX_CNTVALUEIN0
CELL54.IMUX.IMUX.29.DELAY	BITSLICE46.TX_CNTVALUEIN1
CELL54.IMUX.IMUX.30.DELAY	BITSLICE46.TX_CNTVALUEIN2
CELL54.IMUX.IMUX.31.DELAY	BITSLICE46.TX_CNTVALUEIN4
CELL54.IMUX.IMUX.32.DELAY	BITSLICE46.TX_CNTVALUEIN6
CELL54.IMUX.IMUX.33.DELAY	BITSLICE46.TX_CNTVALUEIN7
CELL54.IMUX.IMUX.34.DELAY	BITSLICE46.TX_CNTVALUEIN8
CELL54.IMUX.IMUX.35.DELAY	BITSLICE46.RX_CNTVALUEIN1
CELL54.IMUX.IMUX.36.DELAY	BITSLICE46.RX_CNTVALUEIN3
CELL54.IMUX.IMUX.37.DELAY	BITSLICE46.RX_CNTVALUEIN4
CELL54.IMUX.IMUX.38.DELAY	BITSLICE46.RX_CNTVALUEIN5
CELL54.IMUX.IMUX.39.DELAY	BITSLICE46.RX_CNTVALUEIN7
CELL54.IMUX.IMUX.40.DELAY	BITSLICE47.TX_T
CELL54.IMUX.IMUX.41.DELAY	BITSLICE47.TX_CE_OFD
CELL54.IMUX.IMUX.42.DELAY	BITSLICE47.RX_CE_IFD
CELL54.IMUX.IMUX.43.DELAY	BITSLICE47.CLB2PHY_FIFO_RDEN
CELL54.IMUX.IMUX.44.DELAY	BITSLICE47.TX_D1
CELL54.IMUX.IMUX.45.DELAY	BITSLICE47.TX_D2
CELL54.IMUX.IMUX.46.DELAY	BITSLICE47.TX_D3
CELL54.IMUX.IMUX.47.DELAY	BITSLICE47.TX_D5
CELL55.OUT.0.TMIN	MMCM.CLKFBSTOPPED
CELL55.OUT.1.TMIN	MMCM.CLKINSTOPPED
CELL55.OUT.2.TMIN	MMCM.PSDONE
CELL55.OUT.3.TMIN	MMCM.CDDCDONE
CELL55.OUT.4.TMIN	BITSLICE46.TX_CNTVALUEOUT5
CELL55.OUT.5.TMIN	BITSLICE46.TX_CNTVALUEOUT6
CELL55.OUT.6.TMIN	BITSLICE46.TX_CNTVALUEOUT7
CELL55.OUT.7.TMIN	BITSLICE46.TX_CNTVALUEOUT8
CELL55.OUT.8.TMIN	BITSLICE48.TX_T_OUT
CELL55.OUT.9.TMIN	BITSLICE46.RX_CNTVALUEOUT0
CELL55.OUT.10.TMIN	BITSLICE46.RX_CNTVALUEOUT1
CELL55.OUT.11.TMIN	BITSLICE46.RX_CNTVALUEOUT2
CELL55.OUT.12.TMIN	BITSLICE46.RX_CNTVALUEOUT3
CELL55.OUT.13.TMIN	BITSLICE46.RX_CNTVALUEOUT4
CELL55.OUT.14.TMIN	BITSLICE46.RX_CNTVALUEOUT5
CELL55.OUT.15.TMIN	BITSLICE46.RX_CNTVALUEOUT6
CELL55.OUT.16.TMIN	BITSLICE46.RX_CNTVALUEOUT7
CELL55.OUT.17.TMIN	BITSLICE46.RX_CNTVALUEOUT8
CELL55.OUT.18.TMIN	BITSLICE47.PHY2CLB_FIFO_EMPTY
CELL55.OUT.19.TMIN	BITSLICE47.RX_Q0
CELL55.OUT.20.TMIN	BITSLICE47.RX_Q1
CELL55.OUT.21.TMIN	BITSLICE47.RX_Q2
CELL55.OUT.22.TMIN	BITSLICE47.RX_Q3
CELL55.OUT.23.TMIN	BITSLICE47.RX_Q4
CELL55.OUT.24.TMIN	BITSLICE47.RX_Q5
CELL55.OUT.25.TMIN	BITSLICE47.RX_Q6
CELL55.OUT.26.TMIN	BITSLICE47.RX_Q7
CELL55.OUT.27.TMIN	BITSLICE47.TX_CNTVALUEOUT0
CELL55.OUT.28.TMIN	BITSLICE47.TX_CNTVALUEOUT1
CELL55.OUT.29.TMIN	BITSLICE47.TX_CNTVALUEOUT2
CELL55.OUT.30.TMIN	BITSLICE47.TX_CNTVALUEOUT3
CELL55.OUT.31.TMIN	BITSLICE47.TX_CNTVALUEOUT4
CELL55.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.IDELAY_RST_B7
CELL55.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK7
CELL55.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.TXBIT_RST_B8
CELL55.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.RXBIT_RST_B8
CELL55.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.ODELAY_RST_B8
CELL55.IMUX.BYP.6	BITSLICE46.TX_EN_VTC
CELL55.IMUX.BYP.7	BITSLICE46.TX_CE_ODELAY
CELL55.IMUX.BYP.8	BITSLICE46.RX_LD
CELL55.IMUX.BYP.9	BITSLICE46.RX_INC
CELL55.IMUX.BYP.10	BITSLICE46.RX_EN_VTC
CELL55.IMUX.BYP.11	BITSLICE46.RX_CE_IDELAY
CELL55.IMUX.BYP.12	BITSLICE46.DYN_DCI_OUT_INT
CELL55.IMUX.BYP.13	BITSLICE47.TX_LD
CELL55.IMUX.BYP.14	BITSLICE47.TX_INC
CELL55.IMUX.BYP.15	BITSLICE47.TX_EN_VTC
CELL55.IMUX.IMUX.0.DELAY	MMCM.PSINCDEC
CELL55.IMUX.IMUX.6.DELAY	BITSLICE47.RX_CNTVALUEIN4
CELL55.IMUX.IMUX.7.DELAY	BITSLICE47.RX_CNTVALUEIN6
CELL55.IMUX.IMUX.8.DELAY	BITSLICE_T7.CNTVALUEIN1
CELL55.IMUX.IMUX.9.DELAY	BITSLICE_T7.CNTVALUEIN3
CELL55.IMUX.IMUX.10.DELAY	BITSLICE_T7.CNTVALUEIN7
CELL55.IMUX.IMUX.11.DELAY	BITSLICE_CONTROL7.CLB2RIU_NIBBLE_SEL
CELL55.IMUX.IMUX.12.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS1_3
CELL55.IMUX.IMUX.13.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS0_1
CELL55.IMUX.IMUX.14.DELAY	BITSLICE_CONTROL7.CLB2PHY_T_B1
CELL55.IMUX.IMUX.15.DELAY	BITSLICE_CONTROL7.CLB2PHY_T_B3
CELL55.IMUX.IMUX.16.DELAY	BITSLICE47.TX_D7
CELL55.IMUX.IMUX.18.DELAY	BITSLICE47.TX_CNTVALUEIN0
CELL55.IMUX.IMUX.19.DELAY	BITSLICE47.TX_CNTVALUEIN1
CELL55.IMUX.IMUX.20.DELAY	BITSLICE47.TX_CNTVALUEIN2
CELL55.IMUX.IMUX.21.DELAY	BITSLICE47.TX_CNTVALUEIN3
CELL55.IMUX.IMUX.22.DELAY	BITSLICE47.TX_CNTVALUEIN4
CELL55.IMUX.IMUX.23.DELAY	BITSLICE47.TX_CNTVALUEIN5
CELL55.IMUX.IMUX.24.DELAY	BITSLICE47.TX_CNTVALUEIN6
CELL55.IMUX.IMUX.25.DELAY	BITSLICE47.TX_CNTVALUEIN7
CELL55.IMUX.IMUX.26.DELAY	BITSLICE47.TX_CNTVALUEIN8
CELL55.IMUX.IMUX.27.DELAY	BITSLICE47.RX_CNTVALUEIN0
CELL55.IMUX.IMUX.28.DELAY	BITSLICE47.RX_CNTVALUEIN1
CELL55.IMUX.IMUX.29.DELAY	BITSLICE47.RX_CNTVALUEIN2
CELL55.IMUX.IMUX.30.DELAY	BITSLICE47.RX_CNTVALUEIN3
CELL55.IMUX.IMUX.31.DELAY	BITSLICE47.RX_CNTVALUEIN5
CELL55.IMUX.IMUX.32.DELAY	BITSLICE47.RX_CNTVALUEIN7
CELL55.IMUX.IMUX.33.DELAY	BITSLICE47.RX_CNTVALUEIN8
CELL55.IMUX.IMUX.34.DELAY	BITSLICE_T7.CNTVALUEIN0
CELL55.IMUX.IMUX.35.DELAY	BITSLICE_T7.CNTVALUEIN2
CELL55.IMUX.IMUX.36.DELAY	BITSLICE_T7.CNTVALUEIN4
CELL55.IMUX.IMUX.37.DELAY	BITSLICE_T7.CNTVALUEIN5
CELL55.IMUX.IMUX.38.DELAY	BITSLICE_T7.CNTVALUEIN6
CELL55.IMUX.IMUX.39.DELAY	BITSLICE_T7.CNTVALUEIN8
CELL55.IMUX.IMUX.40.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS1_0
CELL55.IMUX.IMUX.41.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS1_1
CELL55.IMUX.IMUX.42.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS1_2
CELL55.IMUX.IMUX.43.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS0_0
CELL55.IMUX.IMUX.44.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS0_2
CELL55.IMUX.IMUX.45.DELAY	BITSLICE_CONTROL7.CLB2PHY_WRCS0_3
CELL55.IMUX.IMUX.46.DELAY	BITSLICE_CONTROL7.CLB2PHY_T_B0
CELL55.IMUX.IMUX.47.DELAY	BITSLICE_CONTROL7.CLB2PHY_T_B2
CELL56.OUT.4.TMIN	BITSLICE47.TX_CNTVALUEOUT5
CELL56.OUT.5.TMIN	BITSLICE47.TX_CNTVALUEOUT6
CELL56.OUT.6.TMIN	BITSLICE47.TX_CNTVALUEOUT7
CELL56.OUT.7.TMIN	BITSLICE47.TX_CNTVALUEOUT8
CELL56.OUT.8.TMIN	BITSLICE49.TX_T_OUT
CELL56.OUT.9.TMIN	BITSLICE47.RX_CNTVALUEOUT0
CELL56.OUT.10.TMIN	BITSLICE47.RX_CNTVALUEOUT1
CELL56.OUT.11.TMIN	BITSLICE47.RX_CNTVALUEOUT2
CELL56.OUT.12.TMIN	BITSLICE47.RX_CNTVALUEOUT3
CELL56.OUT.13.TMIN	BITSLICE47.RX_CNTVALUEOUT4
CELL56.OUT.14.TMIN	BITSLICE47.RX_CNTVALUEOUT5
CELL56.OUT.15.TMIN	BITSLICE47.RX_CNTVALUEOUT6
CELL56.OUT.16.TMIN	BITSLICE47.RX_CNTVALUEOUT7
CELL56.OUT.17.TMIN	BITSLICE47.RX_CNTVALUEOUT8
CELL56.OUT.18.TMIN	BITSLICE_T7.CNTVALUEOUT0
CELL56.OUT.19.TMIN	BITSLICE_T7.CNTVALUEOUT1
CELL56.OUT.20.TMIN	BITSLICE_T7.CNTVALUEOUT2
CELL56.OUT.21.TMIN	BITSLICE_T7.CNTVALUEOUT3
CELL56.OUT.22.TMIN	BITSLICE_T7.CNTVALUEOUT4
CELL56.OUT.23.TMIN	BITSLICE_T7.CNTVALUEOUT5
CELL56.OUT.24.TMIN	BITSLICE_T7.CNTVALUEOUT6
CELL56.OUT.25.TMIN	BITSLICE_T7.CNTVALUEOUT7
CELL56.OUT.26.TMIN	BITSLICE_T7.CNTVALUEOUT8
CELL56.OUT.27.TMIN	BITSLICE_CONTROL7.PHY2CLB_PHY_RDY
CELL56.OUT.28.TMIN	BITSLICE_CONTROL7.MASTER_PD_OUT
CELL56.OUT.29.TMIN	BITSLICE_CONTROL7.PHY2CLB_FIXDLY_RDY
CELL56.OUT.30.TMIN	BITSLICE_CONTROL7.CTRL_DLY_TEST_OUT
CELL56.OUT.31.TMIN	BITSLICE50.TX_T_OUT
CELL56.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.IDELAY_RST_B8
CELL56.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK8
CELL56.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.TRISTATE_ODELAY_RST_B1
CELL56.IMUX.CTRL.6	BITSLICE_CONTROL7.REFCLK
CELL56.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.CTRL_RST_B_UPP
CELL56.IMUX.BYP.6	BITSLICE47.TX_CE_ODELAY
CELL56.IMUX.BYP.8	BITSLICE47.RX_LD
CELL56.IMUX.BYP.9	BITSLICE47.RX_INC
CELL56.IMUX.BYP.10	BITSLICE47.RX_EN_VTC
CELL56.IMUX.BYP.11	BITSLICE47.RX_CE_IDELAY
CELL56.IMUX.BYP.12	BITSLICE47.DYN_DCI_OUT_INT
CELL56.IMUX.BYP.13	BITSLICE_T7.CE_OFD
CELL56.IMUX.BYP.14	BITSLICE_T7.LD
CELL56.IMUX.BYP.15	BITSLICE_T7.INC
CELL56.IMUX.IMUX.0.DELAY	MMCM.PSEN
CELL56.IMUX.IMUX.6.DELAY	BITSLICE48.RX_DATAIN1
CELL56.IMUX.IMUX.7.DELAY	BITSLICE48.TX_D0
CELL56.IMUX.IMUX.8.DELAY	BITSLICE48.TX_D4
CELL56.IMUX.IMUX.9.DELAY	BITSLICE48.TX_D6
CELL56.IMUX.IMUX.10.DELAY	BITSLICE48.TX_CNTVALUEIN2
CELL56.IMUX.IMUX.11.DELAY	BITSLICE48.TX_CNTVALUEIN4
CELL56.IMUX.IMUX.12.DELAY	BITSLICE48.TX_CNTVALUEIN7
CELL56.IMUX.IMUX.13.DELAY	BITSLICE48.RX_CNTVALUEIN0
CELL56.IMUX.IMUX.14.DELAY	BITSLICE48.RX_CNTVALUEIN4
CELL56.IMUX.IMUX.15.DELAY	BITSLICE48.RX_CNTVALUEIN6
CELL56.IMUX.IMUX.16.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDEN0
CELL56.IMUX.IMUX.17.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDEN1
CELL56.IMUX.IMUX.18.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDEN2
CELL56.IMUX.IMUX.19.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDEN3
CELL56.IMUX.IMUX.20.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS1_0
CELL56.IMUX.IMUX.21.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS1_1
CELL56.IMUX.IMUX.22.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS1_2
CELL56.IMUX.IMUX.23.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS1_3
CELL56.IMUX.IMUX.24.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS0_0
CELL56.IMUX.IMUX.25.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS0_1
CELL56.IMUX.IMUX.26.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS0_2
CELL56.IMUX.IMUX.27.DELAY	BITSLICE_CONTROL7.CLB2PHY_RDCS0_3
CELL56.IMUX.IMUX.28.DELAY	BITSLICE48.TX_T
CELL56.IMUX.IMUX.29.DELAY	BITSLICE48.TX_CE_OFD
CELL56.IMUX.IMUX.30.DELAY	BITSLICE48.RX_CE_IFD
CELL56.IMUX.IMUX.31.DELAY	BITSLICE48.CLB2PHY_FIFO_RDEN
CELL56.IMUX.IMUX.32.DELAY	BITSLICE48.TX_D1
CELL56.IMUX.IMUX.33.DELAY	BITSLICE48.TX_D2
CELL56.IMUX.IMUX.34.DELAY	BITSLICE48.TX_D3
CELL56.IMUX.IMUX.35.DELAY	BITSLICE48.TX_D5
CELL56.IMUX.IMUX.36.DELAY	BITSLICE48.TX_D7
CELL56.IMUX.IMUX.37.DELAY	BITSLICE48.TX_CNTVALUEIN0
CELL56.IMUX.IMUX.38.DELAY	BITSLICE48.TX_CNTVALUEIN1
CELL56.IMUX.IMUX.39.DELAY	BITSLICE48.TX_CNTVALUEIN3
CELL56.IMUX.IMUX.40.DELAY	BITSLICE48.TX_CNTVALUEIN5
CELL56.IMUX.IMUX.41.DELAY	BITSLICE48.TX_CNTVALUEIN6
CELL56.IMUX.IMUX.43.DELAY	BITSLICE48.TX_CNTVALUEIN8
CELL56.IMUX.IMUX.44.DELAY	BITSLICE48.RX_CNTVALUEIN1
CELL56.IMUX.IMUX.45.DELAY	BITSLICE48.RX_CNTVALUEIN2
CELL56.IMUX.IMUX.46.DELAY	BITSLICE48.RX_CNTVALUEIN3
CELL56.IMUX.IMUX.47.DELAY	BITSLICE48.RX_CNTVALUEIN5
CELL57.OUT.4.TMIN	BITSLICE48.PHY2CLB_FIFO_EMPTY
CELL57.OUT.5.TMIN	BITSLICE48.RX_Q0
CELL57.OUT.6.TMIN	BITSLICE48.RX_Q1
CELL57.OUT.7.TMIN	BITSLICE48.RX_Q2
CELL57.OUT.8.TMIN	BITSLICE48.RX_Q3
CELL57.OUT.9.TMIN	BITSLICE48.RX_Q4
CELL57.OUT.10.TMIN	BITSLICE48.RX_Q5
CELL57.OUT.11.TMIN	BITSLICE48.RX_Q6
CELL57.OUT.12.TMIN	BITSLICE48.RX_Q7
CELL57.OUT.13.TMIN	BITSLICE48.TX_CNTVALUEOUT0
CELL57.OUT.14.TMIN	BITSLICE48.TX_CNTVALUEOUT1
CELL57.OUT.15.TMIN	BITSLICE48.TX_CNTVALUEOUT2
CELL57.OUT.16.TMIN	BITSLICE48.TX_CNTVALUEOUT3
CELL57.OUT.17.TMIN	BITSLICE48.TX_CNTVALUEOUT4
CELL57.OUT.18.TMIN	BITSLICE48.TX_CNTVALUEOUT5
CELL57.OUT.19.TMIN	BITSLICE48.TX_CNTVALUEOUT6
CELL57.OUT.20.TMIN	BITSLICE48.TX_CNTVALUEOUT7
CELL57.OUT.21.TMIN	BITSLICE48.TX_CNTVALUEOUT8
CELL57.OUT.22.TMIN	BITSLICE51.TX_T_OUT
CELL57.OUT.23.TMIN	BITSLICE48.RX_CNTVALUEOUT0
CELL57.OUT.24.TMIN	BITSLICE48.RX_CNTVALUEOUT1
CELL57.OUT.25.TMIN	BITSLICE48.RX_CNTVALUEOUT2
CELL57.OUT.26.TMIN	BITSLICE48.RX_CNTVALUEOUT3
CELL57.OUT.27.TMIN	BITSLICE48.RX_CNTVALUEOUT4
CELL57.OUT.28.TMIN	BITSLICE48.RX_CNTVALUEOUT5
CELL57.OUT.29.TMIN	BITSLICE48.RX_CNTVALUEOUT6
CELL57.OUT.30.TMIN	BITSLICE48.RX_CNTVALUEOUT7
CELL57.OUT.31.TMIN	BITSLICE48.RX_CNTVALUEOUT8
CELL57.IMUX.CTRL.2	BITSLICE_CONTROL7.RIU_CLK, XIPHY_FEEDTHROUGH3.CLB2PHY_CTRL_CLK_UPP
CELL57.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.TXBIT_RST_B9
CELL57.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.RXBIT_RST_B9
CELL57.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.ODELAY_RST_B9
CELL57.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.IDELAY_RST_B9
CELL57.IMUX.BYP.6	BITSLICE_T7.CE_ODELAY
CELL57.IMUX.BYP.7	BITSLICE_CONTROL7.EN_VTC
CELL57.IMUX.BYP.8	BITSLICE_CONTROL7.CTRL_DLY_TEST_IN
CELL57.IMUX.BYP.9	BITSLICE48.TX_LD
CELL57.IMUX.BYP.10	BITSLICE48.TX_INC
CELL57.IMUX.BYP.11	BITSLICE48.TX_EN_VTC
CELL57.IMUX.BYP.12	BITSLICE48.TX_CE_ODELAY
CELL57.IMUX.BYP.13	BITSLICE48.RX_LD
CELL57.IMUX.BYP.14	BITSLICE48.RX_INC
CELL57.IMUX.BYP.15	BITSLICE48.RX_EN_VTC
CELL57.IMUX.IMUX.6.DELAY	BITSLICE49.TX_CNTVALUEIN0
CELL57.IMUX.IMUX.7.DELAY	BITSLICE49.TX_CNTVALUEIN2
CELL57.IMUX.IMUX.8.DELAY	BITSLICE49.TX_CNTVALUEIN6
CELL57.IMUX.IMUX.9.DELAY	BITSLICE49.TX_CNTVALUEIN8
CELL57.IMUX.IMUX.10.DELAY	BITSLICE49.RX_CNTVALUEIN3
CELL57.IMUX.IMUX.11.DELAY	BITSLICE49.RX_CNTVALUEIN5
CELL57.IMUX.IMUX.12.DELAY	BITSLICE50.TX_T
CELL57.IMUX.IMUX.13.DELAY	BITSLICE50.RX_CE_IFD
CELL57.IMUX.IMUX.14.DELAY	BITSLICE50.TX_D1
CELL57.IMUX.IMUX.15.DELAY	BITSLICE50.TX_D3
CELL57.IMUX.IMUX.16.DELAY	BITSLICE48.RX_CNTVALUEIN7
CELL57.IMUX.IMUX.17.DELAY	BITSLICE48.RX_CNTVALUEIN8
CELL57.IMUX.IMUX.18.DELAY	BITSLICE49.TX_T
CELL57.IMUX.IMUX.19.DELAY	BITSLICE49.TX_CE_OFD
CELL57.IMUX.IMUX.20.DELAY	BITSLICE49.RX_CE_IFD
CELL57.IMUX.IMUX.21.DELAY	BITSLICE49.RX_DATAIN1
CELL57.IMUX.IMUX.22.DELAY	BITSLICE49.CLB2PHY_FIFO_RDEN
CELL57.IMUX.IMUX.23.DELAY	BITSLICE49.TX_D5
CELL57.IMUX.IMUX.24.DELAY	BITSLICE49.TX_D4
CELL57.IMUX.IMUX.25.DELAY	BITSLICE49.TX_D3
CELL57.IMUX.IMUX.26.DELAY	BITSLICE49.TX_D2
CELL57.IMUX.IMUX.27.DELAY	BITSLICE49.TX_D1
CELL57.IMUX.IMUX.28.DELAY	BITSLICE49.TX_D0
CELL57.IMUX.IMUX.29.DELAY	BITSLICE49.TX_D6
CELL57.IMUX.IMUX.30.DELAY	BITSLICE49.TX_D7
CELL57.IMUX.IMUX.31.DELAY	BITSLICE49.TX_CNTVALUEIN1
CELL57.IMUX.IMUX.32.DELAY	BITSLICE49.TX_CNTVALUEIN3
CELL57.IMUX.IMUX.33.DELAY	BITSLICE49.TX_CNTVALUEIN4
CELL57.IMUX.IMUX.34.DELAY	BITSLICE49.TX_CNTVALUEIN5
CELL57.IMUX.IMUX.35.DELAY	BITSLICE49.TX_CNTVALUEIN7
CELL57.IMUX.IMUX.36.DELAY	BITSLICE49.RX_CNTVALUEIN0
CELL57.IMUX.IMUX.37.DELAY	BITSLICE49.RX_CNTVALUEIN1
CELL57.IMUX.IMUX.38.DELAY	BITSLICE49.RX_CNTVALUEIN2
CELL57.IMUX.IMUX.39.DELAY	BITSLICE49.RX_CNTVALUEIN4
CELL57.IMUX.IMUX.40.DELAY	BITSLICE49.RX_CNTVALUEIN6
CELL57.IMUX.IMUX.41.DELAY	BITSLICE49.RX_CNTVALUEIN7
CELL57.IMUX.IMUX.42.DELAY	BITSLICE49.RX_CNTVALUEIN8
CELL57.IMUX.IMUX.43.DELAY	BITSLICE50.TX_CE_OFD
CELL57.IMUX.IMUX.44.DELAY	BITSLICE50.RX_DATAIN1
CELL57.IMUX.IMUX.45.DELAY	BITSLICE50.CLB2PHY_FIFO_RDEN
CELL57.IMUX.IMUX.46.DELAY	BITSLICE50.TX_D0
CELL57.IMUX.IMUX.47.DELAY	BITSLICE50.TX_D2
CELL58.OUT.4.TMIN	BITSLICE49.PHY2CLB_FIFO_EMPTY
CELL58.OUT.5.TMIN	BITSLICE49.RX_Q0
CELL58.OUT.6.TMIN	BITSLICE49.RX_Q1
CELL58.OUT.7.TMIN	BITSLICE49.RX_Q2
CELL58.OUT.8.TMIN	BITSLICE49.RX_Q3
CELL58.OUT.9.TMIN	BITSLICE49.RX_Q4
CELL58.OUT.10.TMIN	BITSLICE49.RX_Q5
CELL58.OUT.11.TMIN	BITSLICE49.RX_Q6
CELL58.OUT.12.TMIN	BITSLICE49.RX_Q7
CELL58.OUT.13.TMIN	BITSLICE49.TX_CNTVALUEOUT0
CELL58.OUT.14.TMIN	BITSLICE49.TX_CNTVALUEOUT1
CELL58.OUT.15.TMIN	BITSLICE49.TX_CNTVALUEOUT2
CELL58.OUT.16.TMIN	BITSLICE49.TX_CNTVALUEOUT3
CELL58.OUT.17.TMIN	BITSLICE49.TX_CNTVALUEOUT4
CELL58.OUT.18.TMIN	BITSLICE49.TX_CNTVALUEOUT5
CELL58.OUT.19.TMIN	BITSLICE49.TX_CNTVALUEOUT6
CELL58.OUT.20.TMIN	BITSLICE49.TX_CNTVALUEOUT7
CELL58.OUT.21.TMIN	BITSLICE49.TX_CNTVALUEOUT8
CELL58.OUT.23.TMIN	BITSLICE49.RX_CNTVALUEOUT0
CELL58.OUT.24.TMIN	BITSLICE49.RX_CNTVALUEOUT1
CELL58.OUT.25.TMIN	BITSLICE49.RX_CNTVALUEOUT2
CELL58.OUT.26.TMIN	BITSLICE49.RX_CNTVALUEOUT3
CELL58.OUT.27.TMIN	BITSLICE49.RX_CNTVALUEOUT4
CELL58.OUT.28.TMIN	BITSLICE49.RX_CNTVALUEOUT5
CELL58.OUT.29.TMIN	BITSLICE49.RX_CNTVALUEOUT6
CELL58.OUT.30.TMIN	BITSLICE49.RX_CNTVALUEOUT7
CELL58.OUT.31.TMIN	BITSLICE49.RX_CNTVALUEOUT8
CELL58.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK9
CELL58.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.TXBIT_RST_B10
CELL58.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.RXBIT_RST_B10
CELL58.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.ODELAY_RST_B10
CELL58.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.IDELAY_RST_B10
CELL58.IMUX.BYP.6	BITSLICE48.RX_CE_IDELAY
CELL58.IMUX.BYP.7	BITSLICE48.DYN_DCI_OUT_INT
CELL58.IMUX.BYP.8	BITSLICE49.TX_LD
CELL58.IMUX.BYP.9	BITSLICE49.TX_INC
CELL58.IMUX.BYP.10	BITSLICE49.TX_EN_VTC
CELL58.IMUX.BYP.11	BITSLICE49.TX_CE_ODELAY
CELL58.IMUX.BYP.12	BITSLICE49.RX_LD
CELL58.IMUX.BYP.13	BITSLICE49.RX_INC
CELL58.IMUX.BYP.14	BITSLICE49.RX_EN_VTC
CELL58.IMUX.BYP.15	BITSLICE49.RX_CE_IDELAY
CELL58.IMUX.IMUX.6.DELAY	BITSLICE50.TX_D5
CELL58.IMUX.IMUX.7.DELAY	BITSLICE50.TX_D6
CELL58.IMUX.IMUX.8.DELAY	BITSLICE50.TX_D7
CELL58.IMUX.IMUX.9.DELAY	BITSLICE50.TX_CNTVALUEIN0
CELL58.IMUX.IMUX.10.DELAY	BITSLICE50.TX_CNTVALUEIN1
CELL58.IMUX.IMUX.11.DELAY	BITSLICE50.TX_CNTVALUEIN2
CELL58.IMUX.IMUX.12.DELAY	BITSLICE50.TX_CNTVALUEIN3
CELL58.IMUX.IMUX.13.DELAY	BITSLICE50.TX_CNTVALUEIN4
CELL58.IMUX.IMUX.14.DELAY	BITSLICE50.TX_CNTVALUEIN5
CELL58.IMUX.IMUX.15.DELAY	BITSLICE50.TX_CNTVALUEIN6
CELL58.IMUX.IMUX.16.DELAY	BITSLICE50.TX_D4
CELL59.OUT.4.TMIN	BITSLICE50.PHY2CLB_FIFO_EMPTY
CELL59.OUT.5.TMIN	BITSLICE50.RX_Q0
CELL59.OUT.6.TMIN	BITSLICE50.RX_Q1
CELL59.OUT.7.TMIN	BITSLICE50.RX_Q2
CELL59.OUT.8.TMIN	BITSLICE50.RX_Q3
CELL59.OUT.9.TMIN	BITSLICE50.RX_Q4
CELL59.OUT.10.TMIN	BITSLICE50.RX_Q5
CELL59.OUT.11.TMIN	BITSLICE50.RX_Q6
CELL59.OUT.12.TMIN	BITSLICE50.RX_Q7
CELL59.OUT.13.TMIN	BITSLICE50.TX_CNTVALUEOUT0
CELL59.OUT.14.TMIN	BITSLICE50.TX_CNTVALUEOUT1
CELL59.OUT.15.TMIN	BITSLICE50.TX_CNTVALUEOUT2
CELL59.OUT.16.TMIN	BITSLICE50.TX_CNTVALUEOUT3
CELL59.OUT.17.TMIN	BITSLICE50.TX_CNTVALUEOUT4
CELL59.OUT.18.TMIN	BITSLICE50.TX_CNTVALUEOUT5
CELL59.OUT.19.TMIN	BITSLICE50.TX_CNTVALUEOUT6
CELL59.OUT.20.TMIN	BITSLICE50.TX_CNTVALUEOUT7
CELL59.OUT.21.TMIN	BITSLICE50.TX_CNTVALUEOUT8
CELL59.OUT.23.TMIN	BITSLICE50.RX_CNTVALUEOUT0
CELL59.OUT.24.TMIN	BITSLICE50.RX_CNTVALUEOUT1
CELL59.OUT.25.TMIN	BITSLICE50.RX_CNTVALUEOUT2
CELL59.OUT.26.TMIN	BITSLICE50.RX_CNTVALUEOUT3
CELL59.OUT.27.TMIN	BITSLICE50.RX_CNTVALUEOUT4
CELL59.OUT.28.TMIN	BITSLICE50.RX_CNTVALUEOUT5
CELL59.OUT.29.TMIN	BITSLICE50.RX_CNTVALUEOUT6
CELL59.OUT.30.TMIN	BITSLICE50.RX_CNTVALUEOUT7
CELL59.OUT.31.TMIN	BITSLICE50.RX_CNTVALUEOUT8
CELL59.IMUX.CTRL.2	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK10
CELL59.IMUX.CTRL.3	XIPHY_FEEDTHROUGH3.TXBIT_RST_B11
CELL59.IMUX.CTRL.4	XIPHY_FEEDTHROUGH3.RXBIT_RST_B11
CELL59.IMUX.CTRL.5	XIPHY_FEEDTHROUGH3.ODELAY_RST_B11
CELL59.IMUX.CTRL.6	XIPHY_FEEDTHROUGH3.IDELAY_RST_B11
CELL59.IMUX.CTRL.7	XIPHY_FEEDTHROUGH3.CLB2PHY_FIFO_CLK11
CELL59.IMUX.BYP.6	BITSLICE49.DYN_DCI_OUT_INT
CELL59.IMUX.BYP.7	BITSLICE50.TX_LD
CELL59.IMUX.BYP.8	BITSLICE50.TX_INC
CELL59.IMUX.BYP.9	BITSLICE50.TX_EN_VTC
CELL59.IMUX.BYP.10	BITSLICE50.TX_CE_ODELAY
CELL59.IMUX.BYP.11	BITSLICE50.RX_LD
CELL59.IMUX.BYP.12	BITSLICE50.RX_INC
CELL59.IMUX.BYP.13	BITSLICE50.RX_EN_VTC
CELL59.IMUX.BYP.14	BITSLICE50.RX_CE_IDELAY
CELL59.IMUX.BYP.15	BITSLICE50.DYN_DCI_OUT_INT
CELL59.IMUX.IMUX.6.DELAY	BITSLICE50.TX_CNTVALUEIN8
CELL59.IMUX.IMUX.7.DELAY	BITSLICE50.RX_CNTVALUEIN0
CELL59.IMUX.IMUX.8.DELAY	BITSLICE50.RX_CNTVALUEIN1
CELL59.IMUX.IMUX.9.DELAY	BITSLICE50.RX_CNTVALUEIN2
CELL59.IMUX.IMUX.10.DELAY	BITSLICE50.RX_CNTVALUEIN3
CELL59.IMUX.IMUX.11.DELAY	BITSLICE50.RX_CNTVALUEIN4
CELL59.IMUX.IMUX.12.DELAY	BITSLICE50.RX_CNTVALUEIN5
CELL59.IMUX.IMUX.13.DELAY	BITSLICE50.RX_CNTVALUEIN6
CELL59.IMUX.IMUX.14.DELAY	BITSLICE50.RX_CNTVALUEIN7
CELL59.IMUX.IMUX.15.DELAY	BITSLICE50.RX_CNTVALUEIN8
CELL59.IMUX.IMUX.16.DELAY	BITSLICE50.TX_CNTVALUEIN7

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