Clock Management Tile

Tile CMT

Cells: 60

Bel BUFCE_ROW_CMT[0]

ultrascale CMT bel BUFCE_ROW_CMT[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[17]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[1]

ultrascale CMT bel BUFCE_ROW_CMT[1]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[18]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[2]

ultrascale CMT bel BUFCE_ROW_CMT[2]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[19]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[3]

ultrascale CMT bel BUFCE_ROW_CMT[3]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[20]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[4]

ultrascale CMT bel BUFCE_ROW_CMT[4]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[21]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[5]

ultrascale CMT bel BUFCE_ROW_CMT[5]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[22]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[6]

ultrascale CMT bel BUFCE_ROW_CMT[6]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[23]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[7]

ultrascale CMT bel BUFCE_ROW_CMT[7]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[24]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[8]

ultrascale CMT bel BUFCE_ROW_CMT[8]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[25]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[9]

ultrascale CMT bel BUFCE_ROW_CMT[9]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[26]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[10]

ultrascale CMT bel BUFCE_ROW_CMT[10]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[27]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[11]

ultrascale CMT bel BUFCE_ROW_CMT[11]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[28]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[12]

ultrascale CMT bel BUFCE_ROW_CMT[12]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[29]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[13]

ultrascale CMT bel BUFCE_ROW_CMT[13]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[30]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[14]

ultrascale CMT bel BUFCE_ROW_CMT[14]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[31]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[15]

ultrascale CMT bel BUFCE_ROW_CMT[15]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[32]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[16]

ultrascale CMT bel BUFCE_ROW_CMT[16]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[33]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[17]

ultrascale CMT bel BUFCE_ROW_CMT[17]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[34]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[18]

ultrascale CMT bel BUFCE_ROW_CMT[18]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[35]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[19]

ultrascale CMT bel BUFCE_ROW_CMT[19]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[36]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[20]

ultrascale CMT bel BUFCE_ROW_CMT[20]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[37]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[0]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[1]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[2]

Bel BUFCE_ROW_CMT[21]

ultrascale CMT bel BUFCE_ROW_CMT[21]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[38]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[22]

ultrascale CMT bel BUFCE_ROW_CMT[22]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[39]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel BUFCE_ROW_CMT[23]

ultrascale CMT bel BUFCE_ROW_CMT[23]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[40]
OPT_DELAY_TEST0	input	CELL[30].IMUX_RCLK[6]
OPT_DELAY_TEST1	input	CELL[30].IMUX_RCLK[7]
OPT_DELAY_TEST2	input	CELL[30].IMUX_RCLK[8]

Bel GCLK_TEST_BUF_CMT[0]

ultrascale CMT bel GCLK_TEST_BUF_CMT[0]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[1]

ultrascale CMT bel GCLK_TEST_BUF_CMT[1]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[2]

ultrascale CMT bel GCLK_TEST_BUF_CMT[2]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[3]

ultrascale CMT bel GCLK_TEST_BUF_CMT[3]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[4]

ultrascale CMT bel GCLK_TEST_BUF_CMT[4]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[5]

ultrascale CMT bel GCLK_TEST_BUF_CMT[5]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[6]

ultrascale CMT bel GCLK_TEST_BUF_CMT[6]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[7]

ultrascale CMT bel GCLK_TEST_BUF_CMT[7]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[8]

ultrascale CMT bel GCLK_TEST_BUF_CMT[8]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[9]

ultrascale CMT bel GCLK_TEST_BUF_CMT[9]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[10]

ultrascale CMT bel GCLK_TEST_BUF_CMT[10]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[11]

ultrascale CMT bel GCLK_TEST_BUF_CMT[11]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[12]

ultrascale CMT bel GCLK_TEST_BUF_CMT[12]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[13]

ultrascale CMT bel GCLK_TEST_BUF_CMT[13]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[14]

ultrascale CMT bel GCLK_TEST_BUF_CMT[14]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[15]

ultrascale CMT bel GCLK_TEST_BUF_CMT[15]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[16]

ultrascale CMT bel GCLK_TEST_BUF_CMT[16]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[17]

ultrascale CMT bel GCLK_TEST_BUF_CMT[17]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[18]

ultrascale CMT bel GCLK_TEST_BUF_CMT[18]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[19]

ultrascale CMT bel GCLK_TEST_BUF_CMT[19]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[20]

ultrascale CMT bel GCLK_TEST_BUF_CMT[20]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[21]

ultrascale CMT bel GCLK_TEST_BUF_CMT[21]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[22]

ultrascale CMT bel GCLK_TEST_BUF_CMT[22]
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT[23]

ultrascale CMT bel GCLK_TEST_BUF_CMT[23]
Pin	Direction	Wires

Bel BUFGCE[0]

ultrascale CMT bel BUFGCE[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[31]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[24]

Bel BUFGCE[1]

ultrascale CMT bel BUFGCE[1]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[32]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[25]

Bel BUFGCE[2]

ultrascale CMT bel BUFGCE[2]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[33]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[26]

Bel BUFGCE[3]

ultrascale CMT bel BUFGCE[3]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[34]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[27]

Bel BUFGCE[4]

ultrascale CMT bel BUFGCE[4]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[35]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[28]

Bel BUFGCE[5]

ultrascale CMT bel BUFGCE[5]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[36]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[29]

Bel BUFGCE[6]

ultrascale CMT bel BUFGCE[6]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[37]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[30]

Bel BUFGCE[7]

ultrascale CMT bel BUFGCE[7]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[38]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[31]

Bel BUFGCE[8]

ultrascale CMT bel BUFGCE[8]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[39]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[32]

Bel BUFGCE[9]

ultrascale CMT bel BUFGCE[9]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[40]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[33]

Bel BUFGCE[10]

ultrascale CMT bel BUFGCE[10]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[41]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[34]

Bel BUFGCE[11]

ultrascale CMT bel BUFGCE[11]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[42]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[35]

Bel BUFGCE[12]

ultrascale CMT bel BUFGCE[12]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[43]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[36]

Bel BUFGCE[13]

ultrascale CMT bel BUFGCE[13]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[44]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[37]

Bel BUFGCE[14]

ultrascale CMT bel BUFGCE[14]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[45]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[38]

Bel BUFGCE[15]

ultrascale CMT bel BUFGCE[15]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[46]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[39]

Bel BUFGCE[16]

ultrascale CMT bel BUFGCE[16]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[47]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[40]

Bel BUFGCE[17]

ultrascale CMT bel BUFGCE[17]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[17]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[41]

Bel BUFGCE[18]

ultrascale CMT bel BUFGCE[18]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[18]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[42]

Bel BUFGCE[19]

ultrascale CMT bel BUFGCE[19]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[19]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[43]

Bel BUFGCE[20]

ultrascale CMT bel BUFGCE[20]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[20]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[44]

Bel BUFGCE[21]

ultrascale CMT bel BUFGCE[21]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[21]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[45]

Bel BUFGCE[22]

ultrascale CMT bel BUFGCE[22]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[22]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[46]

Bel BUFGCE[23]

ultrascale CMT bel BUFGCE[23]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[23]
CLK_IN_CKINT	input	CELL[31].IMUX_IMUX_DELAY[47]

Bel BUFGCTRL[0]

ultrascale CMT bel BUFGCTRL[0]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[23]
CE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[46]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[38]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[30]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[22]
SEL1_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[45]

Bel BUFGCTRL[1]

ultrascale CMT bel BUFGCTRL[1]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[24]
CE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[47]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[39]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[31]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[23]
SEL1_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[46]

Bel BUFGCTRL[2]

ultrascale CMT bel BUFGCTRL[2]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[25]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[17]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[40]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[32]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[24]
SEL1_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[47]

Bel BUFGCTRL[3]

ultrascale CMT bel BUFGCTRL[3]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[26]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[18]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[41]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[33]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[25]
SEL1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[17]

Bel BUFGCTRL[4]

ultrascale CMT bel BUFGCTRL[4]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[27]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[19]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[42]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[34]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[26]
SEL1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[18]

Bel BUFGCTRL[5]

ultrascale CMT bel BUFGCTRL[5]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[28]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[20]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[43]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[35]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[27]
SEL1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[19]

Bel BUFGCTRL[6]

ultrascale CMT bel BUFGCTRL[6]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[29]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[21]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[44]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[36]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[28]
SEL1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[20]

Bel BUFGCTRL[7]

ultrascale CMT bel BUFGCTRL[7]
Pin	Direction	Wires
CE0_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[30]
CE1_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[22]
IGNORE0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[45]
IGNORE1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[37]
SEL0_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[29]
SEL1_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[21]

Bel BUFGCE_DIV[0]

ultrascale CMT bel BUFGCE_DIV[0]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[41]
RST_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[0]

Bel BUFGCE_DIV[1]

ultrascale CMT bel BUFGCE_DIV[1]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[42]
RST_PRE_OPTINV	input	CELL[29].IMUX_IMUX_DELAY[0]

Bel BUFGCE_DIV[2]

ultrascale CMT bel BUFGCE_DIV[2]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[43]
RST_PRE_OPTINV	input	CELL[30].IMUX_IMUX_DELAY[0]

Bel BUFGCE_DIV[3]

ultrascale CMT bel BUFGCE_DIV[3]
Pin	Direction	Wires
CE_PRE_OPTINV	input	CELL[28].IMUX_IMUX_DELAY[44]
RST_PRE_OPTINV	input	CELL[31].IMUX_IMUX_DELAY[0]

Bel PLL[0]

ultrascale CMT bel PLL[0]
Pin	Direction	Wires
CLKOUTPHY_EN	input	CELL[1].IMUX_IMUX_DELAY[0]
DADDR0	input	CELL[9].IMUX_BYP[0]
DADDR1	input	CELL[9].IMUX_BYP[1]
DADDR2	input	CELL[9].IMUX_BYP[2]
DADDR3	input	CELL[9].IMUX_BYP[3]
DADDR4	input	CELL[8].IMUX_BYP[0]
DADDR5	input	CELL[8].IMUX_BYP[1]
DADDR6	input	CELL[8].IMUX_BYP[2]
DCLK_B	input	CELL[11].IMUX_CTRL[0]
DEN	input	CELL[11].IMUX_IMUX_DELAY[0]
DI0	input	CELL[13].IMUX_BYP[0]
DI1	input	CELL[13].IMUX_BYP[1]
DI10	input	CELL[11].IMUX_BYP[2]
DI11	input	CELL[11].IMUX_BYP[3]
DI12	input	CELL[10].IMUX_BYP[0]
DI13	input	CELL[10].IMUX_BYP[1]
DI14	input	CELL[10].IMUX_BYP[2]
DI15	input	CELL[10].IMUX_BYP[3]
DI2	input	CELL[13].IMUX_BYP[2]
DI3	input	CELL[13].IMUX_BYP[3]
DI4	input	CELL[12].IMUX_BYP[0]
DI5	input	CELL[12].IMUX_BYP[1]
DI6	input	CELL[12].IMUX_BYP[2]
DI7	input	CELL[12].IMUX_BYP[3]
DI8	input	CELL[11].IMUX_BYP[0]
DI9	input	CELL[11].IMUX_BYP[1]
DOUT0	output	CELL[12].OUT_BEL[0]
DOUT1	output	CELL[12].OUT_BEL[1]
DOUT10	output	CELL[10].OUT_BEL[2]
DOUT11	output	CELL[10].OUT_BEL[3]
DOUT12	output	CELL[9].OUT_BEL[0]
DOUT13	output	CELL[9].OUT_BEL[1]
DOUT14	output	CELL[9].OUT_BEL[2]
DOUT15	output	CELL[9].OUT_BEL[3]
DOUT2	output	CELL[12].OUT_BEL[2]
DOUT3	output	CELL[12].OUT_BEL[3]
DOUT4	output	CELL[11].OUT_BEL[0]
DOUT5	output	CELL[11].OUT_BEL[1]
DOUT6	output	CELL[11].OUT_BEL[2]
DOUT7	output	CELL[11].OUT_BEL[3]
DOUT8	output	CELL[10].OUT_BEL[0]
DOUT9	output	CELL[10].OUT_BEL[1]
DRDY	output	CELL[13].OUT_BEL[0]
DWE	input	CELL[10].IMUX_IMUX_DELAY[0]
LOCKED	output	CELL[13].OUT_BEL[1]
PWRDWN	input	CELL[12].IMUX_IMUX_DELAY[0]
RST	input	CELL[13].IMUX_IMUX_DELAY[0]
SCANCLK_B	input	CELL[13].IMUX_CTRL[0]
SCANENB	input	CELL[7].IMUX_IMUX_DELAY[0]
SCANIN	input	CELL[8].IMUX_IMUX_DELAY[0]
SCANMODEB	input	CELL[6].IMUX_IMUX_DELAY[0]
SCANOUT	output	CELL[13].OUT_BEL[3]
TESTIN0	input	CELL[7].IMUX_BYP[0]
TESTIN1	input	CELL[7].IMUX_BYP[1]
TESTIN10	input	CELL[5].IMUX_BYP[2]
TESTIN11	input	CELL[5].IMUX_BYP[3]
TESTIN12	input	CELL[4].IMUX_BYP[0]
TESTIN13	input	CELL[4].IMUX_BYP[1]
TESTIN14	input	CELL[4].IMUX_BYP[2]
TESTIN15	input	CELL[4].IMUX_BYP[3]
TESTIN16	input	CELL[3].IMUX_BYP[0]
TESTIN17	input	CELL[3].IMUX_BYP[1]
TESTIN18	input	CELL[3].IMUX_BYP[2]
TESTIN19	input	CELL[3].IMUX_BYP[3]
TESTIN2	input	CELL[7].IMUX_BYP[2]
TESTIN20	input	CELL[2].IMUX_BYP[0]
TESTIN21	input	CELL[2].IMUX_BYP[1]
TESTIN22	input	CELL[2].IMUX_BYP[2]
TESTIN23	input	CELL[2].IMUX_BYP[3]
TESTIN24	input	CELL[1].IMUX_BYP[0]
TESTIN25	input	CELL[1].IMUX_BYP[1]
TESTIN26	input	CELL[1].IMUX_BYP[2]
TESTIN27	input	CELL[1].IMUX_BYP[3]
TESTIN28	input	CELL[0].IMUX_BYP[0]
TESTIN29	input	CELL[0].IMUX_BYP[1]
TESTIN3	input	CELL[7].IMUX_BYP[3]
TESTIN30	input	CELL[0].IMUX_BYP[2]
TESTIN31	input	CELL[0].IMUX_BYP[3]
TESTIN4	input	CELL[6].IMUX_BYP[0]
TESTIN5	input	CELL[6].IMUX_BYP[1]
TESTIN6	input	CELL[6].IMUX_BYP[2]
TESTIN7	input	CELL[6].IMUX_BYP[3]
TESTIN8	input	CELL[5].IMUX_BYP[0]
TESTIN9	input	CELL[5].IMUX_BYP[1]
TESTOUT0	output	CELL[8].OUT_BEL[0]
TESTOUT1	output	CELL[8].OUT_BEL[1]
TESTOUT10	output	CELL[6].OUT_BEL[2]
TESTOUT11	output	CELL[6].OUT_BEL[3]
TESTOUT12	output	CELL[5].OUT_BEL[0]
TESTOUT13	output	CELL[5].OUT_BEL[1]
TESTOUT14	output	CELL[5].OUT_BEL[2]
TESTOUT15	output	CELL[5].OUT_BEL[3]
TESTOUT16	output	CELL[4].OUT_BEL[0]
TESTOUT17	output	CELL[4].OUT_BEL[1]
TESTOUT18	output	CELL[4].OUT_BEL[2]
TESTOUT19	output	CELL[4].OUT_BEL[3]
TESTOUT2	output	CELL[8].OUT_BEL[2]
TESTOUT20	output	CELL[3].OUT_BEL[0]
TESTOUT21	output	CELL[3].OUT_BEL[1]
TESTOUT22	output	CELL[3].OUT_BEL[2]
TESTOUT23	output	CELL[3].OUT_BEL[3]
TESTOUT24	output	CELL[2].OUT_BEL[0]
TESTOUT25	output	CELL[2].OUT_BEL[1]
TESTOUT26	output	CELL[2].OUT_BEL[2]
TESTOUT27	output	CELL[2].OUT_BEL[3]
TESTOUT28	output	CELL[1].OUT_BEL[0]
TESTOUT29	output	CELL[1].OUT_BEL[1]
TESTOUT3	output	CELL[8].OUT_BEL[3]
TESTOUT30	output	CELL[1].OUT_BEL[2]
TESTOUT31	output	CELL[1].OUT_BEL[3]
TESTOUT32	output	CELL[0].OUT_BEL[0]
TESTOUT33	output	CELL[0].OUT_BEL[1]
TESTOUT34	output	CELL[0].OUT_BEL[2]
TESTOUT35	output	CELL[0].OUT_BEL[3]
TESTOUT36	output	CELL[13].OUT_BEL[2]
TESTOUT4	output	CELL[7].OUT_BEL[0]
TESTOUT5	output	CELL[7].OUT_BEL[1]
TESTOUT6	output	CELL[7].OUT_BEL[2]
TESTOUT7	output	CELL[7].OUT_BEL[3]
TESTOUT8	output	CELL[6].OUT_BEL[0]
TESTOUT9	output	CELL[6].OUT_BEL[1]

Bel PLL[1]

ultrascale CMT bel PLL[1]
Pin	Direction	Wires
CLKOUTPHY_EN	input	CELL[15].IMUX_IMUX_DELAY[0]
DADDR0	input	CELL[23].IMUX_BYP[0]
DADDR1	input	CELL[23].IMUX_BYP[1]
DADDR2	input	CELL[23].IMUX_BYP[2]
DADDR3	input	CELL[23].IMUX_BYP[3]
DADDR4	input	CELL[22].IMUX_BYP[0]
DADDR5	input	CELL[22].IMUX_BYP[1]
DADDR6	input	CELL[22].IMUX_BYP[2]
DCLK_B	input	CELL[25].IMUX_CTRL[0]
DEN	input	CELL[25].IMUX_IMUX_DELAY[0]
DI0	input	CELL[27].IMUX_BYP[0]
DI1	input	CELL[27].IMUX_BYP[1]
DI10	input	CELL[25].IMUX_BYP[2]
DI11	input	CELL[25].IMUX_BYP[3]
DI12	input	CELL[24].IMUX_BYP[0]
DI13	input	CELL[24].IMUX_BYP[1]
DI14	input	CELL[24].IMUX_BYP[2]
DI15	input	CELL[24].IMUX_BYP[3]
DI2	input	CELL[27].IMUX_BYP[2]
DI3	input	CELL[27].IMUX_BYP[3]
DI4	input	CELL[26].IMUX_BYP[0]
DI5	input	CELL[26].IMUX_BYP[1]
DI6	input	CELL[26].IMUX_BYP[2]
DI7	input	CELL[26].IMUX_BYP[3]
DI8	input	CELL[25].IMUX_BYP[0]
DI9	input	CELL[25].IMUX_BYP[1]
DOUT0	output	CELL[26].OUT_BEL[0]
DOUT1	output	CELL[26].OUT_BEL[1]
DOUT10	output	CELL[24].OUT_BEL[2]
DOUT11	output	CELL[24].OUT_BEL[3]
DOUT12	output	CELL[23].OUT_BEL[0]
DOUT13	output	CELL[23].OUT_BEL[1]
DOUT14	output	CELL[23].OUT_BEL[2]
DOUT15	output	CELL[23].OUT_BEL[3]
DOUT2	output	CELL[26].OUT_BEL[2]
DOUT3	output	CELL[26].OUT_BEL[3]
DOUT4	output	CELL[25].OUT_BEL[0]
DOUT5	output	CELL[25].OUT_BEL[1]
DOUT6	output	CELL[25].OUT_BEL[2]
DOUT7	output	CELL[25].OUT_BEL[3]
DOUT8	output	CELL[24].OUT_BEL[0]
DOUT9	output	CELL[24].OUT_BEL[1]
DRDY	output	CELL[27].OUT_BEL[0]
DWE	input	CELL[24].IMUX_IMUX_DELAY[0]
LOCKED	output	CELL[27].OUT_BEL[1]
PWRDWN	input	CELL[26].IMUX_IMUX_DELAY[0]
RST	input	CELL[27].IMUX_IMUX_DELAY[0]
SCANCLK_B	input	CELL[27].IMUX_CTRL[0]
SCANENB	input	CELL[21].IMUX_IMUX_DELAY[0]
SCANIN	input	CELL[22].IMUX_IMUX_DELAY[0]
SCANMODEB	input	CELL[20].IMUX_IMUX_DELAY[0]
SCANOUT	output	CELL[27].OUT_BEL[3]
TESTIN0	input	CELL[21].IMUX_BYP[0]
TESTIN1	input	CELL[21].IMUX_BYP[1]
TESTIN10	input	CELL[19].IMUX_BYP[2]
TESTIN11	input	CELL[19].IMUX_BYP[3]
TESTIN12	input	CELL[18].IMUX_BYP[0]
TESTIN13	input	CELL[18].IMUX_BYP[1]
TESTIN14	input	CELL[18].IMUX_BYP[2]
TESTIN15	input	CELL[18].IMUX_BYP[3]
TESTIN16	input	CELL[17].IMUX_BYP[0]
TESTIN17	input	CELL[17].IMUX_BYP[1]
TESTIN18	input	CELL[17].IMUX_BYP[2]
TESTIN19	input	CELL[17].IMUX_BYP[3]
TESTIN2	input	CELL[21].IMUX_BYP[2]
TESTIN20	input	CELL[16].IMUX_BYP[0]
TESTIN21	input	CELL[16].IMUX_BYP[1]
TESTIN22	input	CELL[16].IMUX_BYP[2]
TESTIN23	input	CELL[16].IMUX_BYP[3]
TESTIN24	input	CELL[15].IMUX_BYP[0]
TESTIN25	input	CELL[15].IMUX_BYP[1]
TESTIN26	input	CELL[15].IMUX_BYP[2]
TESTIN27	input	CELL[15].IMUX_BYP[3]
TESTIN28	input	CELL[14].IMUX_BYP[0]
TESTIN29	input	CELL[14].IMUX_BYP[1]
TESTIN3	input	CELL[21].IMUX_BYP[3]
TESTIN30	input	CELL[14].IMUX_BYP[2]
TESTIN31	input	CELL[14].IMUX_BYP[3]
TESTIN4	input	CELL[20].IMUX_BYP[0]
TESTIN5	input	CELL[20].IMUX_BYP[1]
TESTIN6	input	CELL[20].IMUX_BYP[2]
TESTIN7	input	CELL[20].IMUX_BYP[3]
TESTIN8	input	CELL[19].IMUX_BYP[0]
TESTIN9	input	CELL[19].IMUX_BYP[1]
TESTOUT0	output	CELL[22].OUT_BEL[0]
TESTOUT1	output	CELL[22].OUT_BEL[1]
TESTOUT10	output	CELL[20].OUT_BEL[2]
TESTOUT11	output	CELL[20].OUT_BEL[3]
TESTOUT12	output	CELL[19].OUT_BEL[0]
TESTOUT13	output	CELL[19].OUT_BEL[1]
TESTOUT14	output	CELL[19].OUT_BEL[2]
TESTOUT15	output	CELL[19].OUT_BEL[3]
TESTOUT16	output	CELL[18].OUT_BEL[0]
TESTOUT17	output	CELL[18].OUT_BEL[1]
TESTOUT18	output	CELL[18].OUT_BEL[2]
TESTOUT19	output	CELL[18].OUT_BEL[3]
TESTOUT2	output	CELL[22].OUT_BEL[2]
TESTOUT20	output	CELL[17].OUT_BEL[0]
TESTOUT21	output	CELL[17].OUT_BEL[1]
TESTOUT22	output	CELL[17].OUT_BEL[2]
TESTOUT23	output	CELL[17].OUT_BEL[3]
TESTOUT24	output	CELL[16].OUT_BEL[0]
TESTOUT25	output	CELL[16].OUT_BEL[1]
TESTOUT26	output	CELL[16].OUT_BEL[2]
TESTOUT27	output	CELL[16].OUT_BEL[3]
TESTOUT28	output	CELL[15].OUT_BEL[0]
TESTOUT29	output	CELL[15].OUT_BEL[1]
TESTOUT3	output	CELL[22].OUT_BEL[3]
TESTOUT30	output	CELL[15].OUT_BEL[2]
TESTOUT31	output	CELL[15].OUT_BEL[3]
TESTOUT32	output	CELL[14].OUT_BEL[0]
TESTOUT33	output	CELL[14].OUT_BEL[1]
TESTOUT34	output	CELL[14].OUT_BEL[2]
TESTOUT35	output	CELL[14].OUT_BEL[3]
TESTOUT36	output	CELL[27].OUT_BEL[2]
TESTOUT4	output	CELL[21].OUT_BEL[0]
TESTOUT5	output	CELL[21].OUT_BEL[1]
TESTOUT6	output	CELL[21].OUT_BEL[2]
TESTOUT7	output	CELL[21].OUT_BEL[3]
TESTOUT8	output	CELL[20].OUT_BEL[0]
TESTOUT9	output	CELL[20].OUT_BEL[1]

Bel MMCM

ultrascale CMT bel MMCM
Pin	Direction	Wires
CDDCDONE	output	CELL[55].OUT_BEL[3]
CDDCREQ	input	CELL[50].IMUX_IMUX_DELAY[0]
CLKFBSTOPPED	output	CELL[55].OUT_BEL[0]
CLKINSEL	input	CELL[41].IMUX_IMUX_DELAY[0]
CLKINSTOPPED	output	CELL[55].OUT_BEL[1]
DADDR0	input	CELL[50].IMUX_BYP[0]
DADDR1	input	CELL[50].IMUX_BYP[1]
DADDR2	input	CELL[50].IMUX_BYP[2]
DADDR3	input	CELL[50].IMUX_BYP[3]
DADDR4	input	CELL[49].IMUX_BYP[0]
DADDR5	input	CELL[49].IMUX_BYP[1]
DADDR6	input	CELL[49].IMUX_BYP[2]
DCLK_B	input	CELL[52].IMUX_CTRL[0]
DEN	input	CELL[52].IMUX_IMUX_DELAY[0]
DI0	input	CELL[54].IMUX_BYP[0]
DI1	input	CELL[54].IMUX_BYP[1]
DI10	input	CELL[52].IMUX_BYP[2]
DI11	input	CELL[52].IMUX_BYP[3]
DI12	input	CELL[51].IMUX_BYP[0]
DI13	input	CELL[51].IMUX_BYP[1]
DI14	input	CELL[51].IMUX_BYP[2]
DI15	input	CELL[51].IMUX_BYP[3]
DI2	input	CELL[54].IMUX_BYP[2]
DI3	input	CELL[54].IMUX_BYP[3]
DI4	input	CELL[53].IMUX_BYP[0]
DI5	input	CELL[53].IMUX_BYP[1]
DI6	input	CELL[53].IMUX_BYP[2]
DI7	input	CELL[53].IMUX_BYP[3]
DI8	input	CELL[52].IMUX_BYP[0]
DI9	input	CELL[52].IMUX_BYP[1]
DOUT0	output	CELL[53].OUT_BEL[0]
DOUT1	output	CELL[53].OUT_BEL[1]
DOUT10	output	CELL[51].OUT_BEL[2]
DOUT11	output	CELL[51].OUT_BEL[3]
DOUT12	output	CELL[50].OUT_BEL[0]
DOUT13	output	CELL[50].OUT_BEL[1]
DOUT14	output	CELL[50].OUT_BEL[2]
DOUT15	output	CELL[50].OUT_BEL[3]
DOUT2	output	CELL[53].OUT_BEL[2]
DOUT3	output	CELL[53].OUT_BEL[3]
DOUT4	output	CELL[52].OUT_BEL[0]
DOUT5	output	CELL[52].OUT_BEL[1]
DOUT6	output	CELL[52].OUT_BEL[2]
DOUT7	output	CELL[52].OUT_BEL[3]
DOUT8	output	CELL[51].OUT_BEL[0]
DOUT9	output	CELL[51].OUT_BEL[1]
DRDY	output	CELL[54].OUT_BEL[0]
DWE	input	CELL[51].IMUX_IMUX_DELAY[0]
LOCKED	output	CELL[54].OUT_BEL[1]
PSCLK_B	input	CELL[53].IMUX_CTRL[0]
PSDONE	output	CELL[55].OUT_BEL[2]
PSEN	input	CELL[56].IMUX_IMUX_DELAY[0]
PSINCDEC	input	CELL[55].IMUX_IMUX_DELAY[0]
PWRDWN	input	CELL[53].IMUX_IMUX_DELAY[0]
RST	input	CELL[54].IMUX_IMUX_DELAY[0]
SCANCLK_B	input	CELL[54].IMUX_CTRL[0]
SCANENB	input	CELL[48].IMUX_IMUX_DELAY[0]
SCANIN	input	CELL[49].IMUX_IMUX_DELAY[0]
SCANMODEB	input	CELL[47].IMUX_IMUX_DELAY[0]
SCANOUT	output	CELL[54].OUT_BEL[3]
TESTIN0	input	CELL[48].IMUX_BYP[0]
TESTIN1	input	CELL[48].IMUX_BYP[1]
TESTIN10	input	CELL[46].IMUX_BYP[2]
TESTIN11	input	CELL[46].IMUX_BYP[3]
TESTIN12	input	CELL[45].IMUX_BYP[0]
TESTIN13	input	CELL[45].IMUX_BYP[1]
TESTIN14	input	CELL[45].IMUX_BYP[2]
TESTIN15	input	CELL[45].IMUX_BYP[3]
TESTIN16	input	CELL[44].IMUX_BYP[0]
TESTIN17	input	CELL[44].IMUX_BYP[1]
TESTIN18	input	CELL[44].IMUX_BYP[2]
TESTIN19	input	CELL[44].IMUX_BYP[3]
TESTIN2	input	CELL[48].IMUX_BYP[2]
TESTIN20	input	CELL[43].IMUX_BYP[0]
TESTIN21	input	CELL[43].IMUX_BYP[1]
TESTIN22	input	CELL[43].IMUX_BYP[2]
TESTIN23	input	CELL[43].IMUX_BYP[3]
TESTIN24	input	CELL[42].IMUX_BYP[0]
TESTIN25	input	CELL[42].IMUX_BYP[1]
TESTIN26	input	CELL[42].IMUX_BYP[2]
TESTIN27	input	CELL[42].IMUX_BYP[3]
TESTIN28	input	CELL[41].IMUX_BYP[0]
TESTIN29	input	CELL[41].IMUX_BYP[1]
TESTIN3	input	CELL[48].IMUX_BYP[3]
TESTIN30	input	CELL[41].IMUX_BYP[2]
TESTIN31	input	CELL[41].IMUX_BYP[3]
TESTIN4	input	CELL[47].IMUX_BYP[0]
TESTIN5	input	CELL[47].IMUX_BYP[1]
TESTIN6	input	CELL[47].IMUX_BYP[2]
TESTIN7	input	CELL[47].IMUX_BYP[3]
TESTIN8	input	CELL[46].IMUX_BYP[0]
TESTIN9	input	CELL[46].IMUX_BYP[1]
TESTOUT0	output	CELL[49].OUT_BEL[0]
TESTOUT1	output	CELL[49].OUT_BEL[1]
TESTOUT10	output	CELL[47].OUT_BEL[2]
TESTOUT11	output	CELL[47].OUT_BEL[3]
TESTOUT12	output	CELL[46].OUT_BEL[0]
TESTOUT13	output	CELL[46].OUT_BEL[1]
TESTOUT14	output	CELL[46].OUT_BEL[2]
TESTOUT15	output	CELL[46].OUT_BEL[3]
TESTOUT16	output	CELL[45].OUT_BEL[0]
TESTOUT17	output	CELL[45].OUT_BEL[1]
TESTOUT18	output	CELL[45].OUT_BEL[2]
TESTOUT19	output	CELL[45].OUT_BEL[3]
TESTOUT2	output	CELL[49].OUT_BEL[2]
TESTOUT20	output	CELL[44].OUT_BEL[0]
TESTOUT21	output	CELL[44].OUT_BEL[1]
TESTOUT22	output	CELL[44].OUT_BEL[2]
TESTOUT23	output	CELL[44].OUT_BEL[3]
TESTOUT24	output	CELL[43].OUT_BEL[0]
TESTOUT25	output	CELL[43].OUT_BEL[1]
TESTOUT26	output	CELL[43].OUT_BEL[2]
TESTOUT27	output	CELL[43].OUT_BEL[3]
TESTOUT28	output	CELL[42].OUT_BEL[0]
TESTOUT29	output	CELL[42].OUT_BEL[1]
TESTOUT3	output	CELL[49].OUT_BEL[3]
TESTOUT30	output	CELL[42].OUT_BEL[2]
TESTOUT31	output	CELL[42].OUT_BEL[3]
TESTOUT32	output	CELL[41].OUT_BEL[0]
TESTOUT33	output	CELL[41].OUT_BEL[1]
TESTOUT34	output	CELL[41].OUT_BEL[2]
TESTOUT35	output	CELL[41].OUT_BEL[3]
TESTOUT36	output	CELL[54].OUT_BEL[2]
TESTOUT4	output	CELL[48].OUT_BEL[0]
TESTOUT5	output	CELL[48].OUT_BEL[1]
TESTOUT6	output	CELL[48].OUT_BEL[2]
TESTOUT7	output	CELL[48].OUT_BEL[3]
TESTOUT8	output	CELL[47].OUT_BEL[0]
TESTOUT9	output	CELL[47].OUT_BEL[1]

Bel CMT

ultrascale CMT bel CMT
Pin	Direction	Wires

Bel VCC_CMT

ultrascale CMT bel VCC_CMT
Pin	Direction	Wires

Bel ABUS_SWITCH_CMT

ultrascale CMT bel ABUS_SWITCH_CMT
Pin	Direction	Wires

Bel wires

ultrascale CMT bel wires
Wire	Pins
CELL[0].OUT_BEL[0]	PLL[0].TESTOUT32
CELL[0].OUT_BEL[1]	PLL[0].TESTOUT33
CELL[0].OUT_BEL[2]	PLL[0].TESTOUT34
CELL[0].OUT_BEL[3]	PLL[0].TESTOUT35
CELL[0].IMUX_BYP[0]	PLL[0].TESTIN28
CELL[0].IMUX_BYP[1]	PLL[0].TESTIN29
CELL[0].IMUX_BYP[2]	PLL[0].TESTIN30
CELL[0].IMUX_BYP[3]	PLL[0].TESTIN31
CELL[1].OUT_BEL[0]	PLL[0].TESTOUT28
CELL[1].OUT_BEL[1]	PLL[0].TESTOUT29
CELL[1].OUT_BEL[2]	PLL[0].TESTOUT30
CELL[1].OUT_BEL[3]	PLL[0].TESTOUT31
CELL[1].IMUX_BYP[0]	PLL[0].TESTIN24
CELL[1].IMUX_BYP[1]	PLL[0].TESTIN25
CELL[1].IMUX_BYP[2]	PLL[0].TESTIN26
CELL[1].IMUX_BYP[3]	PLL[0].TESTIN27
CELL[1].IMUX_IMUX_DELAY[0]	PLL[0].CLKOUTPHY_EN
CELL[2].OUT_BEL[0]	PLL[0].TESTOUT24
CELL[2].OUT_BEL[1]	PLL[0].TESTOUT25
CELL[2].OUT_BEL[2]	PLL[0].TESTOUT26
CELL[2].OUT_BEL[3]	PLL[0].TESTOUT27
CELL[2].IMUX_BYP[0]	PLL[0].TESTIN20
CELL[2].IMUX_BYP[1]	PLL[0].TESTIN21
CELL[2].IMUX_BYP[2]	PLL[0].TESTIN22
CELL[2].IMUX_BYP[3]	PLL[0].TESTIN23
CELL[3].OUT_BEL[0]	PLL[0].TESTOUT20
CELL[3].OUT_BEL[1]	PLL[0].TESTOUT21
CELL[3].OUT_BEL[2]	PLL[0].TESTOUT22
CELL[3].OUT_BEL[3]	PLL[0].TESTOUT23
CELL[3].IMUX_BYP[0]	PLL[0].TESTIN16
CELL[3].IMUX_BYP[1]	PLL[0].TESTIN17
CELL[3].IMUX_BYP[2]	PLL[0].TESTIN18
CELL[3].IMUX_BYP[3]	PLL[0].TESTIN19
CELL[4].OUT_BEL[0]	PLL[0].TESTOUT16
CELL[4].OUT_BEL[1]	PLL[0].TESTOUT17
CELL[4].OUT_BEL[2]	PLL[0].TESTOUT18
CELL[4].OUT_BEL[3]	PLL[0].TESTOUT19
CELL[4].IMUX_BYP[0]	PLL[0].TESTIN12
CELL[4].IMUX_BYP[1]	PLL[0].TESTIN13
CELL[4].IMUX_BYP[2]	PLL[0].TESTIN14
CELL[4].IMUX_BYP[3]	PLL[0].TESTIN15
CELL[5].OUT_BEL[0]	PLL[0].TESTOUT12
CELL[5].OUT_BEL[1]	PLL[0].TESTOUT13
CELL[5].OUT_BEL[2]	PLL[0].TESTOUT14
CELL[5].OUT_BEL[3]	PLL[0].TESTOUT15
CELL[5].IMUX_BYP[0]	PLL[0].TESTIN8
CELL[5].IMUX_BYP[1]	PLL[0].TESTIN9
CELL[5].IMUX_BYP[2]	PLL[0].TESTIN10
CELL[5].IMUX_BYP[3]	PLL[0].TESTIN11
CELL[6].OUT_BEL[0]	PLL[0].TESTOUT8
CELL[6].OUT_BEL[1]	PLL[0].TESTOUT9
CELL[6].OUT_BEL[2]	PLL[0].TESTOUT10
CELL[6].OUT_BEL[3]	PLL[0].TESTOUT11
CELL[6].IMUX_BYP[0]	PLL[0].TESTIN4
CELL[6].IMUX_BYP[1]	PLL[0].TESTIN5
CELL[6].IMUX_BYP[2]	PLL[0].TESTIN6
CELL[6].IMUX_BYP[3]	PLL[0].TESTIN7
CELL[6].IMUX_IMUX_DELAY[0]	PLL[0].SCANMODEB
CELL[7].OUT_BEL[0]	PLL[0].TESTOUT4
CELL[7].OUT_BEL[1]	PLL[0].TESTOUT5
CELL[7].OUT_BEL[2]	PLL[0].TESTOUT6
CELL[7].OUT_BEL[3]	PLL[0].TESTOUT7
CELL[7].IMUX_BYP[0]	PLL[0].TESTIN0
CELL[7].IMUX_BYP[1]	PLL[0].TESTIN1
CELL[7].IMUX_BYP[2]	PLL[0].TESTIN2
CELL[7].IMUX_BYP[3]	PLL[0].TESTIN3
CELL[7].IMUX_IMUX_DELAY[0]	PLL[0].SCANENB
CELL[8].OUT_BEL[0]	PLL[0].TESTOUT0
CELL[8].OUT_BEL[1]	PLL[0].TESTOUT1
CELL[8].OUT_BEL[2]	PLL[0].TESTOUT2
CELL[8].OUT_BEL[3]	PLL[0].TESTOUT3
CELL[8].IMUX_BYP[0]	PLL[0].DADDR4
CELL[8].IMUX_BYP[1]	PLL[0].DADDR5
CELL[8].IMUX_BYP[2]	PLL[0].DADDR6
CELL[8].IMUX_IMUX_DELAY[0]	PLL[0].SCANIN
CELL[9].OUT_BEL[0]	PLL[0].DOUT12
CELL[9].OUT_BEL[1]	PLL[0].DOUT13
CELL[9].OUT_BEL[2]	PLL[0].DOUT14
CELL[9].OUT_BEL[3]	PLL[0].DOUT15
CELL[9].IMUX_BYP[0]	PLL[0].DADDR0
CELL[9].IMUX_BYP[1]	PLL[0].DADDR1
CELL[9].IMUX_BYP[2]	PLL[0].DADDR2
CELL[9].IMUX_BYP[3]	PLL[0].DADDR3
CELL[10].OUT_BEL[0]	PLL[0].DOUT8
CELL[10].OUT_BEL[1]	PLL[0].DOUT9
CELL[10].OUT_BEL[2]	PLL[0].DOUT10
CELL[10].OUT_BEL[3]	PLL[0].DOUT11
CELL[10].IMUX_BYP[0]	PLL[0].DI12
CELL[10].IMUX_BYP[1]	PLL[0].DI13
CELL[10].IMUX_BYP[2]	PLL[0].DI14
CELL[10].IMUX_BYP[3]	PLL[0].DI15
CELL[10].IMUX_IMUX_DELAY[0]	PLL[0].DWE
CELL[11].OUT_BEL[0]	PLL[0].DOUT4
CELL[11].OUT_BEL[1]	PLL[0].DOUT5
CELL[11].OUT_BEL[2]	PLL[0].DOUT6
CELL[11].OUT_BEL[3]	PLL[0].DOUT7
CELL[11].IMUX_CTRL[0]	PLL[0].DCLK_B
CELL[11].IMUX_BYP[0]	PLL[0].DI8
CELL[11].IMUX_BYP[1]	PLL[0].DI9
CELL[11].IMUX_BYP[2]	PLL[0].DI10
CELL[11].IMUX_BYP[3]	PLL[0].DI11
CELL[11].IMUX_IMUX_DELAY[0]	PLL[0].DEN
CELL[12].OUT_BEL[0]	PLL[0].DOUT0
CELL[12].OUT_BEL[1]	PLL[0].DOUT1
CELL[12].OUT_BEL[2]	PLL[0].DOUT2
CELL[12].OUT_BEL[3]	PLL[0].DOUT3
CELL[12].IMUX_BYP[0]	PLL[0].DI4
CELL[12].IMUX_BYP[1]	PLL[0].DI5
CELL[12].IMUX_BYP[2]	PLL[0].DI6
CELL[12].IMUX_BYP[3]	PLL[0].DI7
CELL[12].IMUX_IMUX_DELAY[0]	PLL[0].PWRDWN
CELL[13].OUT_BEL[0]	PLL[0].DRDY
CELL[13].OUT_BEL[1]	PLL[0].LOCKED
CELL[13].OUT_BEL[2]	PLL[0].TESTOUT36
CELL[13].OUT_BEL[3]	PLL[0].SCANOUT
CELL[13].IMUX_CTRL[0]	PLL[0].SCANCLK_B
CELL[13].IMUX_BYP[0]	PLL[0].DI0
CELL[13].IMUX_BYP[1]	PLL[0].DI1
CELL[13].IMUX_BYP[2]	PLL[0].DI2
CELL[13].IMUX_BYP[3]	PLL[0].DI3
CELL[13].IMUX_IMUX_DELAY[0]	PLL[0].RST
CELL[14].OUT_BEL[0]	PLL[1].TESTOUT32
CELL[14].OUT_BEL[1]	PLL[1].TESTOUT33
CELL[14].OUT_BEL[2]	PLL[1].TESTOUT34
CELL[14].OUT_BEL[3]	PLL[1].TESTOUT35
CELL[14].IMUX_BYP[0]	PLL[1].TESTIN28
CELL[14].IMUX_BYP[1]	PLL[1].TESTIN29
CELL[14].IMUX_BYP[2]	PLL[1].TESTIN30
CELL[14].IMUX_BYP[3]	PLL[1].TESTIN31
CELL[15].OUT_BEL[0]	PLL[1].TESTOUT28
CELL[15].OUT_BEL[1]	PLL[1].TESTOUT29
CELL[15].OUT_BEL[2]	PLL[1].TESTOUT30
CELL[15].OUT_BEL[3]	PLL[1].TESTOUT31
CELL[15].IMUX_BYP[0]	PLL[1].TESTIN24
CELL[15].IMUX_BYP[1]	PLL[1].TESTIN25
CELL[15].IMUX_BYP[2]	PLL[1].TESTIN26
CELL[15].IMUX_BYP[3]	PLL[1].TESTIN27
CELL[15].IMUX_IMUX_DELAY[0]	PLL[1].CLKOUTPHY_EN
CELL[16].OUT_BEL[0]	PLL[1].TESTOUT24
CELL[16].OUT_BEL[1]	PLL[1].TESTOUT25
CELL[16].OUT_BEL[2]	PLL[1].TESTOUT26
CELL[16].OUT_BEL[3]	PLL[1].TESTOUT27
CELL[16].IMUX_BYP[0]	PLL[1].TESTIN20
CELL[16].IMUX_BYP[1]	PLL[1].TESTIN21
CELL[16].IMUX_BYP[2]	PLL[1].TESTIN22
CELL[16].IMUX_BYP[3]	PLL[1].TESTIN23
CELL[17].OUT_BEL[0]	PLL[1].TESTOUT20
CELL[17].OUT_BEL[1]	PLL[1].TESTOUT21
CELL[17].OUT_BEL[2]	PLL[1].TESTOUT22
CELL[17].OUT_BEL[3]	PLL[1].TESTOUT23
CELL[17].IMUX_BYP[0]	PLL[1].TESTIN16
CELL[17].IMUX_BYP[1]	PLL[1].TESTIN17
CELL[17].IMUX_BYP[2]	PLL[1].TESTIN18
CELL[17].IMUX_BYP[3]	PLL[1].TESTIN19
CELL[18].OUT_BEL[0]	PLL[1].TESTOUT16
CELL[18].OUT_BEL[1]	PLL[1].TESTOUT17
CELL[18].OUT_BEL[2]	PLL[1].TESTOUT18
CELL[18].OUT_BEL[3]	PLL[1].TESTOUT19
CELL[18].IMUX_BYP[0]	PLL[1].TESTIN12
CELL[18].IMUX_BYP[1]	PLL[1].TESTIN13
CELL[18].IMUX_BYP[2]	PLL[1].TESTIN14
CELL[18].IMUX_BYP[3]	PLL[1].TESTIN15
CELL[19].OUT_BEL[0]	PLL[1].TESTOUT12
CELL[19].OUT_BEL[1]	PLL[1].TESTOUT13
CELL[19].OUT_BEL[2]	PLL[1].TESTOUT14
CELL[19].OUT_BEL[3]	PLL[1].TESTOUT15
CELL[19].IMUX_BYP[0]	PLL[1].TESTIN8
CELL[19].IMUX_BYP[1]	PLL[1].TESTIN9
CELL[19].IMUX_BYP[2]	PLL[1].TESTIN10
CELL[19].IMUX_BYP[3]	PLL[1].TESTIN11
CELL[20].OUT_BEL[0]	PLL[1].TESTOUT8
CELL[20].OUT_BEL[1]	PLL[1].TESTOUT9
CELL[20].OUT_BEL[2]	PLL[1].TESTOUT10
CELL[20].OUT_BEL[3]	PLL[1].TESTOUT11
CELL[20].IMUX_BYP[0]	PLL[1].TESTIN4
CELL[20].IMUX_BYP[1]	PLL[1].TESTIN5
CELL[20].IMUX_BYP[2]	PLL[1].TESTIN6
CELL[20].IMUX_BYP[3]	PLL[1].TESTIN7
CELL[20].IMUX_IMUX_DELAY[0]	PLL[1].SCANMODEB
CELL[21].OUT_BEL[0]	PLL[1].TESTOUT4
CELL[21].OUT_BEL[1]	PLL[1].TESTOUT5
CELL[21].OUT_BEL[2]	PLL[1].TESTOUT6
CELL[21].OUT_BEL[3]	PLL[1].TESTOUT7
CELL[21].IMUX_BYP[0]	PLL[1].TESTIN0
CELL[21].IMUX_BYP[1]	PLL[1].TESTIN1
CELL[21].IMUX_BYP[2]	PLL[1].TESTIN2
CELL[21].IMUX_BYP[3]	PLL[1].TESTIN3
CELL[21].IMUX_IMUX_DELAY[0]	PLL[1].SCANENB
CELL[22].OUT_BEL[0]	PLL[1].TESTOUT0
CELL[22].OUT_BEL[1]	PLL[1].TESTOUT1
CELL[22].OUT_BEL[2]	PLL[1].TESTOUT2
CELL[22].OUT_BEL[3]	PLL[1].TESTOUT3
CELL[22].IMUX_BYP[0]	PLL[1].DADDR4
CELL[22].IMUX_BYP[1]	PLL[1].DADDR5
CELL[22].IMUX_BYP[2]	PLL[1].DADDR6
CELL[22].IMUX_IMUX_DELAY[0]	PLL[1].SCANIN
CELL[23].OUT_BEL[0]	PLL[1].DOUT12
CELL[23].OUT_BEL[1]	PLL[1].DOUT13
CELL[23].OUT_BEL[2]	PLL[1].DOUT14
CELL[23].OUT_BEL[3]	PLL[1].DOUT15
CELL[23].IMUX_BYP[0]	PLL[1].DADDR0
CELL[23].IMUX_BYP[1]	PLL[1].DADDR1
CELL[23].IMUX_BYP[2]	PLL[1].DADDR2
CELL[23].IMUX_BYP[3]	PLL[1].DADDR3
CELL[24].OUT_BEL[0]	PLL[1].DOUT8
CELL[24].OUT_BEL[1]	PLL[1].DOUT9
CELL[24].OUT_BEL[2]	PLL[1].DOUT10
CELL[24].OUT_BEL[3]	PLL[1].DOUT11
CELL[24].IMUX_BYP[0]	PLL[1].DI12
CELL[24].IMUX_BYP[1]	PLL[1].DI13
CELL[24].IMUX_BYP[2]	PLL[1].DI14
CELL[24].IMUX_BYP[3]	PLL[1].DI15
CELL[24].IMUX_IMUX_DELAY[0]	PLL[1].DWE
CELL[25].OUT_BEL[0]	PLL[1].DOUT4
CELL[25].OUT_BEL[1]	PLL[1].DOUT5
CELL[25].OUT_BEL[2]	PLL[1].DOUT6
CELL[25].OUT_BEL[3]	PLL[1].DOUT7
CELL[25].IMUX_CTRL[0]	PLL[1].DCLK_B
CELL[25].IMUX_BYP[0]	PLL[1].DI8
CELL[25].IMUX_BYP[1]	PLL[1].DI9
CELL[25].IMUX_BYP[2]	PLL[1].DI10
CELL[25].IMUX_BYP[3]	PLL[1].DI11
CELL[25].IMUX_IMUX_DELAY[0]	PLL[1].DEN
CELL[26].OUT_BEL[0]	PLL[1].DOUT0
CELL[26].OUT_BEL[1]	PLL[1].DOUT1
CELL[26].OUT_BEL[2]	PLL[1].DOUT2
CELL[26].OUT_BEL[3]	PLL[1].DOUT3
CELL[26].IMUX_BYP[0]	PLL[1].DI4
CELL[26].IMUX_BYP[1]	PLL[1].DI5
CELL[26].IMUX_BYP[2]	PLL[1].DI6
CELL[26].IMUX_BYP[3]	PLL[1].DI7
CELL[26].IMUX_IMUX_DELAY[0]	PLL[1].PWRDWN
CELL[27].OUT_BEL[0]	PLL[1].DRDY
CELL[27].OUT_BEL[1]	PLL[1].LOCKED
CELL[27].OUT_BEL[2]	PLL[1].TESTOUT36
CELL[27].OUT_BEL[3]	PLL[1].SCANOUT
CELL[27].IMUX_CTRL[0]	PLL[1].SCANCLK_B
CELL[27].IMUX_BYP[0]	PLL[1].DI0
CELL[27].IMUX_BYP[1]	PLL[1].DI1
CELL[27].IMUX_BYP[2]	PLL[1].DI2
CELL[27].IMUX_BYP[3]	PLL[1].DI3
CELL[27].IMUX_IMUX_DELAY[0]	PLL[1].RST
CELL[28].IMUX_IMUX_DELAY[0]	BUFGCE_DIV[0].RST_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[17]	BUFCE_ROW_CMT[0].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[18]	BUFCE_ROW_CMT[1].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[19]	BUFCE_ROW_CMT[2].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[20]	BUFCE_ROW_CMT[3].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[21]	BUFCE_ROW_CMT[4].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[22]	BUFCE_ROW_CMT[5].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[23]	BUFCE_ROW_CMT[6].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[24]	BUFCE_ROW_CMT[7].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[25]	BUFCE_ROW_CMT[8].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[26]	BUFCE_ROW_CMT[9].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[27]	BUFCE_ROW_CMT[10].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[28]	BUFCE_ROW_CMT[11].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[29]	BUFCE_ROW_CMT[12].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[30]	BUFCE_ROW_CMT[13].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[31]	BUFCE_ROW_CMT[14].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[32]	BUFCE_ROW_CMT[15].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[33]	BUFCE_ROW_CMT[16].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[34]	BUFCE_ROW_CMT[17].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[35]	BUFCE_ROW_CMT[18].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[36]	BUFCE_ROW_CMT[19].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[37]	BUFCE_ROW_CMT[20].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[38]	BUFCE_ROW_CMT[21].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[39]	BUFCE_ROW_CMT[22].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[40]	BUFCE_ROW_CMT[23].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[41]	BUFGCE_DIV[0].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[42]	BUFGCE_DIV[1].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[43]	BUFGCE_DIV[2].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[44]	BUFGCE_DIV[3].CE_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[45]	BUFGCTRL[0].SEL1_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[46]	BUFGCTRL[1].SEL1_PRE_OPTINV
CELL[28].IMUX_IMUX_DELAY[47]	BUFGCTRL[2].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[0]	BUFGCE_DIV[1].RST_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[17]	BUFGCTRL[3].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[18]	BUFGCTRL[4].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[19]	BUFGCTRL[5].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[20]	BUFGCTRL[6].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[21]	BUFGCTRL[7].SEL1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[22]	BUFGCTRL[0].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[23]	BUFGCTRL[1].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[24]	BUFGCTRL[2].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[25]	BUFGCTRL[3].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[26]	BUFGCTRL[4].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[27]	BUFGCTRL[5].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[28]	BUFGCTRL[6].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[29]	BUFGCTRL[7].SEL0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[30]	BUFGCTRL[0].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[31]	BUFGCTRL[1].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[32]	BUFGCTRL[2].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[33]	BUFGCTRL[3].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[34]	BUFGCTRL[4].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[35]	BUFGCTRL[5].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[36]	BUFGCTRL[6].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[37]	BUFGCTRL[7].IGNORE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[38]	BUFGCTRL[0].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[39]	BUFGCTRL[1].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[40]	BUFGCTRL[2].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[41]	BUFGCTRL[3].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[42]	BUFGCTRL[4].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[43]	BUFGCTRL[5].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[44]	BUFGCTRL[6].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[45]	BUFGCTRL[7].IGNORE0_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[46]	BUFGCTRL[0].CE1_PRE_OPTINV
CELL[29].IMUX_IMUX_DELAY[47]	BUFGCTRL[1].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[0]	BUFGCE_DIV[2].RST_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[17]	BUFGCTRL[2].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[18]	BUFGCTRL[3].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[19]	BUFGCTRL[4].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[20]	BUFGCTRL[5].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[21]	BUFGCTRL[6].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[22]	BUFGCTRL[7].CE1_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[23]	BUFGCTRL[0].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[24]	BUFGCTRL[1].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[25]	BUFGCTRL[2].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[26]	BUFGCTRL[3].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[27]	BUFGCTRL[4].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[28]	BUFGCTRL[5].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[29]	BUFGCTRL[6].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[30]	BUFGCTRL[7].CE0_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[31]	BUFGCE[0].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[32]	BUFGCE[1].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[33]	BUFGCE[2].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[34]	BUFGCE[3].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[35]	BUFGCE[4].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[36]	BUFGCE[5].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[37]	BUFGCE[6].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[38]	BUFGCE[7].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[39]	BUFGCE[8].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[40]	BUFGCE[9].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[41]	BUFGCE[10].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[42]	BUFGCE[11].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[43]	BUFGCE[12].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[44]	BUFGCE[13].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[45]	BUFGCE[14].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[46]	BUFGCE[15].CE_PRE_OPTINV
CELL[30].IMUX_IMUX_DELAY[47]	BUFGCE[16].CE_PRE_OPTINV
CELL[30].IMUX_RCLK[0]	BUFCE_ROW_CMT[0].OPT_DELAY_TEST0, BUFCE_ROW_CMT[1].OPT_DELAY_TEST0, BUFCE_ROW_CMT[2].OPT_DELAY_TEST0, BUFCE_ROW_CMT[6].OPT_DELAY_TEST0, BUFCE_ROW_CMT[7].OPT_DELAY_TEST0, BUFCE_ROW_CMT[8].OPT_DELAY_TEST0, BUFCE_ROW_CMT[12].OPT_DELAY_TEST0, BUFCE_ROW_CMT[13].OPT_DELAY_TEST0, BUFCE_ROW_CMT[14].OPT_DELAY_TEST0, BUFCE_ROW_CMT[18].OPT_DELAY_TEST0, BUFCE_ROW_CMT[19].OPT_DELAY_TEST0, BUFCE_ROW_CMT[20].OPT_DELAY_TEST0
CELL[30].IMUX_RCLK[1]	BUFCE_ROW_CMT[0].OPT_DELAY_TEST1, BUFCE_ROW_CMT[1].OPT_DELAY_TEST1, BUFCE_ROW_CMT[2].OPT_DELAY_TEST1, BUFCE_ROW_CMT[6].OPT_DELAY_TEST1, BUFCE_ROW_CMT[7].OPT_DELAY_TEST1, BUFCE_ROW_CMT[8].OPT_DELAY_TEST1, BUFCE_ROW_CMT[12].OPT_DELAY_TEST1, BUFCE_ROW_CMT[13].OPT_DELAY_TEST1, BUFCE_ROW_CMT[14].OPT_DELAY_TEST1, BUFCE_ROW_CMT[18].OPT_DELAY_TEST1, BUFCE_ROW_CMT[19].OPT_DELAY_TEST1, BUFCE_ROW_CMT[20].OPT_DELAY_TEST1
CELL[30].IMUX_RCLK[2]	BUFCE_ROW_CMT[0].OPT_DELAY_TEST2, BUFCE_ROW_CMT[1].OPT_DELAY_TEST2, BUFCE_ROW_CMT[2].OPT_DELAY_TEST2, BUFCE_ROW_CMT[6].OPT_DELAY_TEST2, BUFCE_ROW_CMT[7].OPT_DELAY_TEST2, BUFCE_ROW_CMT[8].OPT_DELAY_TEST2, BUFCE_ROW_CMT[12].OPT_DELAY_TEST2, BUFCE_ROW_CMT[13].OPT_DELAY_TEST2, BUFCE_ROW_CMT[14].OPT_DELAY_TEST2, BUFCE_ROW_CMT[18].OPT_DELAY_TEST2, BUFCE_ROW_CMT[19].OPT_DELAY_TEST2, BUFCE_ROW_CMT[20].OPT_DELAY_TEST2
CELL[30].IMUX_RCLK[6]	BUFCE_ROW_CMT[3].OPT_DELAY_TEST0, BUFCE_ROW_CMT[4].OPT_DELAY_TEST0, BUFCE_ROW_CMT[5].OPT_DELAY_TEST0, BUFCE_ROW_CMT[9].OPT_DELAY_TEST0, BUFCE_ROW_CMT[10].OPT_DELAY_TEST0, BUFCE_ROW_CMT[11].OPT_DELAY_TEST0, BUFCE_ROW_CMT[15].OPT_DELAY_TEST0, BUFCE_ROW_CMT[16].OPT_DELAY_TEST0, BUFCE_ROW_CMT[17].OPT_DELAY_TEST0, BUFCE_ROW_CMT[21].OPT_DELAY_TEST0, BUFCE_ROW_CMT[22].OPT_DELAY_TEST0, BUFCE_ROW_CMT[23].OPT_DELAY_TEST0
CELL[30].IMUX_RCLK[7]	BUFCE_ROW_CMT[3].OPT_DELAY_TEST1, BUFCE_ROW_CMT[4].OPT_DELAY_TEST1, BUFCE_ROW_CMT[5].OPT_DELAY_TEST1, BUFCE_ROW_CMT[9].OPT_DELAY_TEST1, BUFCE_ROW_CMT[10].OPT_DELAY_TEST1, BUFCE_ROW_CMT[11].OPT_DELAY_TEST1, BUFCE_ROW_CMT[15].OPT_DELAY_TEST1, BUFCE_ROW_CMT[16].OPT_DELAY_TEST1, BUFCE_ROW_CMT[17].OPT_DELAY_TEST1, BUFCE_ROW_CMT[21].OPT_DELAY_TEST1, BUFCE_ROW_CMT[22].OPT_DELAY_TEST1, BUFCE_ROW_CMT[23].OPT_DELAY_TEST1
CELL[30].IMUX_RCLK[8]	BUFCE_ROW_CMT[3].OPT_DELAY_TEST2, BUFCE_ROW_CMT[4].OPT_DELAY_TEST2, BUFCE_ROW_CMT[5].OPT_DELAY_TEST2, BUFCE_ROW_CMT[9].OPT_DELAY_TEST2, BUFCE_ROW_CMT[10].OPT_DELAY_TEST2, BUFCE_ROW_CMT[11].OPT_DELAY_TEST2, BUFCE_ROW_CMT[15].OPT_DELAY_TEST2, BUFCE_ROW_CMT[16].OPT_DELAY_TEST2, BUFCE_ROW_CMT[17].OPT_DELAY_TEST2, BUFCE_ROW_CMT[21].OPT_DELAY_TEST2, BUFCE_ROW_CMT[22].OPT_DELAY_TEST2, BUFCE_ROW_CMT[23].OPT_DELAY_TEST2
CELL[31].IMUX_IMUX_DELAY[0]	BUFGCE_DIV[3].RST_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[17]	BUFGCE[17].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[18]	BUFGCE[18].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[19]	BUFGCE[19].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[20]	BUFGCE[20].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[21]	BUFGCE[21].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[22]	BUFGCE[22].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[23]	BUFGCE[23].CE_PRE_OPTINV
CELL[31].IMUX_IMUX_DELAY[24]	BUFGCE[0].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[25]	BUFGCE[1].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[26]	BUFGCE[2].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[27]	BUFGCE[3].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[28]	BUFGCE[4].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[29]	BUFGCE[5].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[30]	BUFGCE[6].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[31]	BUFGCE[7].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[32]	BUFGCE[8].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[33]	BUFGCE[9].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[34]	BUFGCE[10].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[35]	BUFGCE[11].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[36]	BUFGCE[12].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[37]	BUFGCE[13].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[38]	BUFGCE[14].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[39]	BUFGCE[15].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[40]	BUFGCE[16].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[41]	BUFGCE[17].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[42]	BUFGCE[18].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[43]	BUFGCE[19].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[44]	BUFGCE[20].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[45]	BUFGCE[21].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[46]	BUFGCE[22].CLK_IN_CKINT
CELL[31].IMUX_IMUX_DELAY[47]	BUFGCE[23].CLK_IN_CKINT
CELL[41].OUT_BEL[0]	MMCM.TESTOUT32
CELL[41].OUT_BEL[1]	MMCM.TESTOUT33
CELL[41].OUT_BEL[2]	MMCM.TESTOUT34
CELL[41].OUT_BEL[3]	MMCM.TESTOUT35
CELL[41].IMUX_BYP[0]	MMCM.TESTIN28
CELL[41].IMUX_BYP[1]	MMCM.TESTIN29
CELL[41].IMUX_BYP[2]	MMCM.TESTIN30
CELL[41].IMUX_BYP[3]	MMCM.TESTIN31
CELL[41].IMUX_IMUX_DELAY[0]	MMCM.CLKINSEL
CELL[42].OUT_BEL[0]	MMCM.TESTOUT28
CELL[42].OUT_BEL[1]	MMCM.TESTOUT29
CELL[42].OUT_BEL[2]	MMCM.TESTOUT30
CELL[42].OUT_BEL[3]	MMCM.TESTOUT31
CELL[42].IMUX_BYP[0]	MMCM.TESTIN24
CELL[42].IMUX_BYP[1]	MMCM.TESTIN25
CELL[42].IMUX_BYP[2]	MMCM.TESTIN26
CELL[42].IMUX_BYP[3]	MMCM.TESTIN27
CELL[43].OUT_BEL[0]	MMCM.TESTOUT24
CELL[43].OUT_BEL[1]	MMCM.TESTOUT25
CELL[43].OUT_BEL[2]	MMCM.TESTOUT26
CELL[43].OUT_BEL[3]	MMCM.TESTOUT27
CELL[43].IMUX_BYP[0]	MMCM.TESTIN20
CELL[43].IMUX_BYP[1]	MMCM.TESTIN21
CELL[43].IMUX_BYP[2]	MMCM.TESTIN22
CELL[43].IMUX_BYP[3]	MMCM.TESTIN23
CELL[44].OUT_BEL[0]	MMCM.TESTOUT20
CELL[44].OUT_BEL[1]	MMCM.TESTOUT21
CELL[44].OUT_BEL[2]	MMCM.TESTOUT22
CELL[44].OUT_BEL[3]	MMCM.TESTOUT23
CELL[44].IMUX_BYP[0]	MMCM.TESTIN16
CELL[44].IMUX_BYP[1]	MMCM.TESTIN17
CELL[44].IMUX_BYP[2]	MMCM.TESTIN18
CELL[44].IMUX_BYP[3]	MMCM.TESTIN19
CELL[45].OUT_BEL[0]	MMCM.TESTOUT16
CELL[45].OUT_BEL[1]	MMCM.TESTOUT17
CELL[45].OUT_BEL[2]	MMCM.TESTOUT18
CELL[45].OUT_BEL[3]	MMCM.TESTOUT19
CELL[45].IMUX_BYP[0]	MMCM.TESTIN12
CELL[45].IMUX_BYP[1]	MMCM.TESTIN13
CELL[45].IMUX_BYP[2]	MMCM.TESTIN14
CELL[45].IMUX_BYP[3]	MMCM.TESTIN15
CELL[46].OUT_BEL[0]	MMCM.TESTOUT12
CELL[46].OUT_BEL[1]	MMCM.TESTOUT13
CELL[46].OUT_BEL[2]	MMCM.TESTOUT14
CELL[46].OUT_BEL[3]	MMCM.TESTOUT15
CELL[46].IMUX_BYP[0]	MMCM.TESTIN8
CELL[46].IMUX_BYP[1]	MMCM.TESTIN9
CELL[46].IMUX_BYP[2]	MMCM.TESTIN10
CELL[46].IMUX_BYP[3]	MMCM.TESTIN11
CELL[47].OUT_BEL[0]	MMCM.TESTOUT8
CELL[47].OUT_BEL[1]	MMCM.TESTOUT9
CELL[47].OUT_BEL[2]	MMCM.TESTOUT10
CELL[47].OUT_BEL[3]	MMCM.TESTOUT11
CELL[47].IMUX_BYP[0]	MMCM.TESTIN4
CELL[47].IMUX_BYP[1]	MMCM.TESTIN5
CELL[47].IMUX_BYP[2]	MMCM.TESTIN6
CELL[47].IMUX_BYP[3]	MMCM.TESTIN7
CELL[47].IMUX_IMUX_DELAY[0]	MMCM.SCANMODEB
CELL[48].OUT_BEL[0]	MMCM.TESTOUT4
CELL[48].OUT_BEL[1]	MMCM.TESTOUT5
CELL[48].OUT_BEL[2]	MMCM.TESTOUT6
CELL[48].OUT_BEL[3]	MMCM.TESTOUT7
CELL[48].IMUX_BYP[0]	MMCM.TESTIN0
CELL[48].IMUX_BYP[1]	MMCM.TESTIN1
CELL[48].IMUX_BYP[2]	MMCM.TESTIN2
CELL[48].IMUX_BYP[3]	MMCM.TESTIN3
CELL[48].IMUX_IMUX_DELAY[0]	MMCM.SCANENB
CELL[49].OUT_BEL[0]	MMCM.TESTOUT0
CELL[49].OUT_BEL[1]	MMCM.TESTOUT1
CELL[49].OUT_BEL[2]	MMCM.TESTOUT2
CELL[49].OUT_BEL[3]	MMCM.TESTOUT3
CELL[49].IMUX_BYP[0]	MMCM.DADDR4
CELL[49].IMUX_BYP[1]	MMCM.DADDR5
CELL[49].IMUX_BYP[2]	MMCM.DADDR6
CELL[49].IMUX_IMUX_DELAY[0]	MMCM.SCANIN
CELL[50].OUT_BEL[0]	MMCM.DOUT12
CELL[50].OUT_BEL[1]	MMCM.DOUT13
CELL[50].OUT_BEL[2]	MMCM.DOUT14
CELL[50].OUT_BEL[3]	MMCM.DOUT15
CELL[50].IMUX_BYP[0]	MMCM.DADDR0
CELL[50].IMUX_BYP[1]	MMCM.DADDR1
CELL[50].IMUX_BYP[2]	MMCM.DADDR2
CELL[50].IMUX_BYP[3]	MMCM.DADDR3
CELL[50].IMUX_IMUX_DELAY[0]	MMCM.CDDCREQ
CELL[51].OUT_BEL[0]	MMCM.DOUT8
CELL[51].OUT_BEL[1]	MMCM.DOUT9
CELL[51].OUT_BEL[2]	MMCM.DOUT10
CELL[51].OUT_BEL[3]	MMCM.DOUT11
CELL[51].IMUX_BYP[0]	MMCM.DI12
CELL[51].IMUX_BYP[1]	MMCM.DI13
CELL[51].IMUX_BYP[2]	MMCM.DI14
CELL[51].IMUX_BYP[3]	MMCM.DI15
CELL[51].IMUX_IMUX_DELAY[0]	MMCM.DWE
CELL[52].OUT_BEL[0]	MMCM.DOUT4
CELL[52].OUT_BEL[1]	MMCM.DOUT5
CELL[52].OUT_BEL[2]	MMCM.DOUT6
CELL[52].OUT_BEL[3]	MMCM.DOUT7
CELL[52].IMUX_CTRL[0]	MMCM.DCLK_B
CELL[52].IMUX_BYP[0]	MMCM.DI8
CELL[52].IMUX_BYP[1]	MMCM.DI9
CELL[52].IMUX_BYP[2]	MMCM.DI10
CELL[52].IMUX_BYP[3]	MMCM.DI11
CELL[52].IMUX_IMUX_DELAY[0]	MMCM.DEN
CELL[53].OUT_BEL[0]	MMCM.DOUT0
CELL[53].OUT_BEL[1]	MMCM.DOUT1
CELL[53].OUT_BEL[2]	MMCM.DOUT2
CELL[53].OUT_BEL[3]	MMCM.DOUT3
CELL[53].IMUX_CTRL[0]	MMCM.PSCLK_B
CELL[53].IMUX_BYP[0]	MMCM.DI4
CELL[53].IMUX_BYP[1]	MMCM.DI5
CELL[53].IMUX_BYP[2]	MMCM.DI6
CELL[53].IMUX_BYP[3]	MMCM.DI7
CELL[53].IMUX_IMUX_DELAY[0]	MMCM.PWRDWN
CELL[54].OUT_BEL[0]	MMCM.DRDY
CELL[54].OUT_BEL[1]	MMCM.LOCKED
CELL[54].OUT_BEL[2]	MMCM.TESTOUT36
CELL[54].OUT_BEL[3]	MMCM.SCANOUT
CELL[54].IMUX_CTRL[0]	MMCM.SCANCLK_B
CELL[54].IMUX_BYP[0]	MMCM.DI0
CELL[54].IMUX_BYP[1]	MMCM.DI1
CELL[54].IMUX_BYP[2]	MMCM.DI2
CELL[54].IMUX_BYP[3]	MMCM.DI3
CELL[54].IMUX_IMUX_DELAY[0]	MMCM.RST
CELL[55].OUT_BEL[0]	MMCM.CLKFBSTOPPED
CELL[55].OUT_BEL[1]	MMCM.CLKINSTOPPED
CELL[55].OUT_BEL[2]	MMCM.PSDONE
CELL[55].OUT_BEL[3]	MMCM.CDDCDONE
CELL[55].IMUX_IMUX_DELAY[0]	MMCM.PSINCDEC
CELL[56].IMUX_IMUX_DELAY[0]	MMCM.PSEN

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