Block RAM
Tile BRAM
Cells: 5 IRIs: 0
Bel BRAM_F
Pin | Direction | Wires |
---|---|---|
ADDRAL0 | input | TCELL0:IMUX.IMUX.8 |
ADDRAL1 | input | TCELL0:IMUX.IMUX.42 |
ADDRAL10 | input | TCELL3:IMUX.IMUX.32 |
ADDRAL11 | input | TCELL3:IMUX.IMUX.42 |
ADDRAL12 | input | TCELL4:IMUX.IMUX.16 |
ADDRAL13 | input | TCELL4:IMUX.IMUX.4 |
ADDRAL14 | input | TCELL4:IMUX.IMUX.32 |
ADDRAL2 | input | TCELL1:IMUX.IMUX.16 |
ADDRAL3 | input | TCELL1:IMUX.IMUX.4 |
ADDRAL4 | input | TCELL1:IMUX.IMUX.8 |
ADDRAL5 | input | TCELL1:IMUX.IMUX.43 |
ADDRAL6 | input | TCELL2:IMUX.IMUX.17 |
ADDRAL7 | input | TCELL2:IMUX.IMUX.42 |
ADDRAL8 | input | TCELL3:IMUX.IMUX.17 |
ADDRAL9 | input | TCELL3:IMUX.IMUX.4 |
ADDRAU0 | input | TCELL0:IMUX.IMUX.33 |
ADDRAU1 | input | TCELL0:IMUX.IMUX.13 |
ADDRAU10 | input | TCELL3:IMUX.IMUX.9 |
ADDRAU11 | input | TCELL3:IMUX.IMUX.13 |
ADDRAU12 | input | TCELL4:IMUX.IMUX.1 |
ADDRAU13 | input | TCELL4:IMUX.IMUX.5 |
ADDRAU14 | input | TCELL4:IMUX.IMUX.9 |
ADDRAU2 | input | TCELL1:IMUX.IMUX.1 |
ADDRAU3 | input | TCELL1:IMUX.IMUX.5 |
ADDRAU4 | input | TCELL1:IMUX.IMUX.33 |
ADDRAU5 | input | TCELL1:IMUX.IMUX.13 |
ADDRAU6 | input | TCELL2:IMUX.IMUX.1 |
ADDRAU7 | input | TCELL2:IMUX.IMUX.13 |
ADDRAU8 | input | TCELL3:IMUX.IMUX.1 |
ADDRAU9 | input | TCELL3:IMUX.IMUX.25 |
ADDRBL0 | input | TCELL0:IMUX.IMUX.10 |
ADDRBL1 | input | TCELL0:IMUX.IMUX.45 |
ADDRBL10 | input | TCELL3:IMUX.IMUX.10 |
ADDRBL11 | input | TCELL3:IMUX.IMUX.45 |
ADDRBL12 | input | TCELL4:IMUX.IMUX.20 |
ADDRBL13 | input | TCELL4:IMUX.IMUX.30 |
ADDRBL14 | input | TCELL4:IMUX.IMUX.10 |
ADDRBL2 | input | TCELL1:IMUX.IMUX.20 |
ADDRBL3 | input | TCELL1:IMUX.IMUX.30 |
ADDRBL4 | input | TCELL1:IMUX.IMUX.10 |
ADDRBL5 | input | TCELL1:IMUX.IMUX.46 |
ADDRBL6 | input | TCELL2:IMUX.IMUX.21 |
ADDRBL7 | input | TCELL2:IMUX.IMUX.45 |
ADDRBL8 | input | TCELL3:IMUX.IMUX.21 |
ADDRBL9 | input | TCELL3:IMUX.IMUX.31 |
ADDRBU0 | input | TCELL0:IMUX.IMUX.11 |
ADDRBU1 | input | TCELL0:IMUX.IMUX.15 |
ADDRBU10 | input | TCELL3:IMUX.IMUX.11 |
ADDRBU11 | input | TCELL3:IMUX.IMUX.15 |
ADDRBU12 | input | TCELL4:IMUX.IMUX.3 |
ADDRBU13 | input | TCELL4:IMUX.IMUX.7 |
ADDRBU14 | input | TCELL4:IMUX.IMUX.11 |
ADDRBU2 | input | TCELL1:IMUX.IMUX.3 |
ADDRBU3 | input | TCELL1:IMUX.IMUX.7 |
ADDRBU4 | input | TCELL1:IMUX.IMUX.11 |
ADDRBU5 | input | TCELL1:IMUX.IMUX.15 |
ADDRBU6 | input | TCELL2:IMUX.IMUX.3 |
ADDRBU7 | input | TCELL2:IMUX.IMUX.15 |
ADDRBU8 | input | TCELL3:IMUX.IMUX.3 |
ADDRBU9 | input | TCELL3:IMUX.IMUX.7 |
ADDRENAL | input | TCELL2:IMUX.IMUX.44 |
ADDRENAU | input | TCELL2:IMUX.IMUX.46 |
ADDRENBL | input | TCELL1:IMUX.IMUX.44 |
ADDRENBU | input | TCELL1:IMUX.IMUX.45 |
CASDIMUXAL | input | TCELL2:IMUX.IMUX.32 |
CASDIMUXAU | input | TCELL2:IMUX.IMUX.33 |
CASDIMUXBL | input | TCELL2:IMUX.IMUX.7 |
CASDIMUXBU | input | TCELL2:IMUX.IMUX.31 |
CASDOMUXAL | input | TCELL3:IMUX.IMUX.27 |
CASDOMUXAU | input | TCELL3:IMUX.IMUX.26 |
CASDOMUXBL | input | TCELL2:IMUX.IMUX.20 |
CASDOMUXBU | input | TCELL2:IMUX.IMUX.22 |
CASDOMUXENAL | input | TCELL1:IMUX.IMUX.40 |
CASDOMUXENAU | input | TCELL1:IMUX.IMUX.41 |
CASDOMUXENBL | input | TCELL3:IMUX.IMUX.20 |
CASDOMUXENBU | input | TCELL3:IMUX.IMUX.22 |
CASOREGIMUXAL | input | TCELL3:IMUX.IMUX.28 |
CASOREGIMUXAU | input | TCELL3:IMUX.IMUX.29 |
CASOREGIMUXBL | input | TCELL0:IMUX.IMUX.30 |
CASOREGIMUXBU | input | TCELL0:IMUX.IMUX.7 |
CASOREGIMUXENAL | input | TCELL0:IMUX.IMUX.44 |
CASOREGIMUXENAU | input | TCELL0:IMUX.IMUX.46 |
CASOREGIMUXENBL | input | TCELL1:IMUX.IMUX.39 |
CASOREGIMUXENBU | input | TCELL1:IMUX.IMUX.38 |
CLKAL | input | TCELL1:IMUX.CTRL.5 |
CLKAU | input | TCELL3:IMUX.CTRL.5 |
CLKBL | input | TCELL1:IMUX.CTRL.4 |
CLKBU | input | TCELL3:IMUX.CTRL.4 |
DBITERR | output | TCELL2:OUT.16 |
DIAL0 | input | TCELL0:IMUX.IMUX.17 |
DIAL1 | input | TCELL0:IMUX.IMUX.25 |
DIAL10 | input | TCELL0:IMUX.IMUX.37 |
DIAL11 | input | TCELL0:IMUX.IMUX.14 |
DIAL12 | input | TCELL1:IMUX.IMUX.29 |
DIAL13 | input | TCELL1:IMUX.IMUX.37 |
DIAL14 | input | TCELL1:IMUX.IMUX.14 |
DIAL15 | input | TCELL2:IMUX.IMUX.2 |
DIAL2 | input | TCELL0:IMUX.IMUX.9 |
DIAL3 | input | TCELL0:IMUX.IMUX.41 |
DIAL4 | input | TCELL1:IMUX.IMUX.25 |
DIAL5 | input | TCELL1:IMUX.IMUX.9 |
DIAL6 | input | TCELL1:IMUX.IMUX.42 |
DIAL7 | input | TCELL2:IMUX.IMUX.0 |
DIAL8 | input | TCELL0:IMUX.IMUX.21 |
DIAL9 | input | TCELL0:IMUX.IMUX.29 |
DIAU0 | input | TCELL2:IMUX.IMUX.43 |
DIAU1 | input | TCELL3:IMUX.IMUX.19 |
DIAU10 | input | TCELL3:IMUX.IMUX.30 |
DIAU11 | input | TCELL3:IMUX.IMUX.39 |
DIAU12 | input | TCELL4:IMUX.IMUX.23 |
DIAU13 | input | TCELL4:IMUX.IMUX.31 |
DIAU14 | input | TCELL4:IMUX.IMUX.39 |
DIAU15 | input | TCELL4:IMUX.IMUX.47 |
DIAU2 | input | TCELL3:IMUX.IMUX.24 |
DIAU3 | input | TCELL3:IMUX.IMUX.35 |
DIAU4 | input | TCELL4:IMUX.IMUX.19 |
DIAU5 | input | TCELL4:IMUX.IMUX.27 |
DIAU6 | input | TCELL4:IMUX.IMUX.35 |
DIAU7 | input | TCELL4:IMUX.IMUX.43 |
DIAU8 | input | TCELL2:IMUX.IMUX.47 |
DIAU9 | input | TCELL3:IMUX.IMUX.23 |
DIBL0 | input | TCELL0:IMUX.IMUX.19 |
DIBL1 | input | TCELL0:IMUX.IMUX.27 |
DIBL10 | input | TCELL0:IMUX.IMUX.39 |
DIBL11 | input | TCELL0:IMUX.IMUX.47 |
DIBL12 | input | TCELL1:IMUX.IMUX.31 |
DIBL13 | input | TCELL1:IMUX.IMUX.36 |
DIBL14 | input | TCELL1:IMUX.IMUX.47 |
DIBL15 | input | TCELL2:IMUX.IMUX.28 |
DIBL2 | input | TCELL0:IMUX.IMUX.35 |
DIBL3 | input | TCELL0:IMUX.IMUX.43 |
DIBL4 | input | TCELL1:IMUX.IMUX.27 |
DIBL5 | input | TCELL1:IMUX.IMUX.35 |
DIBL6 | input | TCELL1:IMUX.IMUX.12 |
DIBL7 | input | TCELL2:IMUX.IMUX.19 |
DIBL8 | input | TCELL0:IMUX.IMUX.23 |
DIBL9 | input | TCELL0:IMUX.IMUX.31 |
DIBU0 | input | TCELL2:IMUX.IMUX.41 |
DIBU1 | input | TCELL3:IMUX.IMUX.0 |
DIBU10 | input | TCELL3:IMUX.IMUX.6 |
DIBU11 | input | TCELL3:IMUX.IMUX.37 |
DIBU12 | input | TCELL4:IMUX.IMUX.21 |
DIBU13 | input | TCELL4:IMUX.IMUX.29 |
DIBU14 | input | TCELL4:IMUX.IMUX.37 |
DIBU15 | input | TCELL4:IMUX.IMUX.14 |
DIBU2 | input | TCELL3:IMUX.IMUX.5 |
DIBU3 | input | TCELL3:IMUX.IMUX.33 |
DIBU4 | input | TCELL4:IMUX.IMUX.17 |
DIBU5 | input | TCELL4:IMUX.IMUX.25 |
DIBU6 | input | TCELL4:IMUX.IMUX.33 |
DIBU7 | input | TCELL4:IMUX.IMUX.41 |
DIBU8 | input | TCELL2:IMUX.IMUX.14 |
DIBU9 | input | TCELL3:IMUX.IMUX.2 |
DIPAL0 | input | TCELL1:IMUX.IMUX.17 |
DIPAL1 | input | TCELL1:IMUX.IMUX.21 |
DIPAU0 | input | TCELL3:IMUX.IMUX.43 |
DIPAU1 | input | TCELL3:IMUX.IMUX.47 |
DIPBL0 | input | TCELL1:IMUX.IMUX.19 |
DIPBL1 | input | TCELL1:IMUX.IMUX.23 |
DIPBU0 | input | TCELL3:IMUX.IMUX.41 |
DIPBU1 | input | TCELL3:IMUX.IMUX.14 |
DOAL0 | output | TCELL0:OUT.0 |
DOAL1 | output | TCELL0:OUT.8 |
DOAL10 | output | TCELL0:OUT.20 |
DOAL11 | output | TCELL0:OUT.28 |
DOAL12 | output | TCELL1:OUT.12 |
DOAL13 | output | TCELL1:OUT.20 |
DOAL14 | output | TCELL1:OUT.28 |
DOAL15 | output | TCELL2:OUT.4 |
DOAL2 | output | TCELL0:OUT.16 |
DOAL3 | output | TCELL0:OUT.24 |
DOAL4 | output | TCELL1:OUT.8 |
DOAL5 | output | TCELL1:OUT.16 |
DOAL6 | output | TCELL1:OUT.24 |
DOAL7 | output | TCELL2:OUT.0 |
DOAL8 | output | TCELL0:OUT.4 |
DOAL9 | output | TCELL0:OUT.12 |
DOAU0 | output | TCELL2:OUT.27 |
DOAU1 | output | TCELL3:OUT.3 |
DOAU10 | output | TCELL3:OUT.15 |
DOAU11 | output | TCELL3:OUT.23 |
DOAU12 | output | TCELL4:OUT.7 |
DOAU13 | output | TCELL4:OUT.15 |
DOAU14 | output | TCELL4:OUT.23 |
DOAU15 | output | TCELL4:OUT.31 |
DOAU2 | output | TCELL3:OUT.11 |
DOAU3 | output | TCELL3:OUT.19 |
DOAU4 | output | TCELL4:OUT.3 |
DOAU5 | output | TCELL4:OUT.11 |
DOAU6 | output | TCELL4:OUT.19 |
DOAU7 | output | TCELL4:OUT.27 |
DOAU8 | output | TCELL2:OUT.31 |
DOAU9 | output | TCELL3:OUT.7 |
DOBL0 | output | TCELL0:OUT.3 |
DOBL1 | output | TCELL0:OUT.11 |
DOBL10 | output | TCELL0:OUT.23 |
DOBL11 | output | TCELL0:OUT.31 |
DOBL12 | output | TCELL1:OUT.15 |
DOBL13 | output | TCELL1:OUT.23 |
DOBL14 | output | TCELL1:OUT.31 |
DOBL15 | output | TCELL2:OUT.7 |
DOBL2 | output | TCELL0:OUT.19 |
DOBL3 | output | TCELL0:OUT.27 |
DOBL4 | output | TCELL1:OUT.11 |
DOBL5 | output | TCELL1:OUT.19 |
DOBL6 | output | TCELL1:OUT.27 |
DOBL7 | output | TCELL2:OUT.3 |
DOBL8 | output | TCELL0:OUT.7 |
DOBL9 | output | TCELL0:OUT.15 |
DOBU0 | output | TCELL2:OUT.24 |
DOBU1 | output | TCELL3:OUT.0 |
DOBU10 | output | TCELL3:OUT.12 |
DOBU11 | output | TCELL3:OUT.20 |
DOBU12 | output | TCELL4:OUT.4 |
DOBU13 | output | TCELL4:OUT.12 |
DOBU14 | output | TCELL4:OUT.20 |
DOBU15 | output | TCELL4:OUT.28 |
DOBU2 | output | TCELL3:OUT.8 |
DOBU3 | output | TCELL3:OUT.16 |
DOBU4 | output | TCELL4:OUT.0 |
DOBU5 | output | TCELL4:OUT.8 |
DOBU6 | output | TCELL4:OUT.16 |
DOBU7 | output | TCELL4:OUT.24 |
DOBU8 | output | TCELL2:OUT.28 |
DOBU9 | output | TCELL3:OUT.4 |
DOPAL0 | output | TCELL1:OUT.0 |
DOPAL1 | output | TCELL1:OUT.4 |
DOPAU0 | output | TCELL3:OUT.27 |
DOPAU1 | output | TCELL3:OUT.31 |
DOPBL0 | output | TCELL1:OUT.3 |
DOPBL1 | output | TCELL1:OUT.7 |
DOPBU0 | output | TCELL3:OUT.24 |
DOPBU1 | output | TCELL3:OUT.28 |
ECCPARITY0 | output | TCELL4:OUT.2 |
ECCPARITY1 | output | TCELL4:OUT.5 |
ECCPARITY2 | output | TCELL4:OUT.6 |
ECCPARITY3 | output | TCELL4:OUT.10 |
ECCPARITY4 | output | TCELL4:OUT.13 |
ECCPARITY5 | output | TCELL4:OUT.14 |
ECCPARITY6 | output | TCELL4:OUT.17 |
ECCPARITY7 | output | TCELL4:OUT.18 |
ECCPIPECE | input | TCELL2:IMUX.IMUX.29 |
EMPTY | output | TCELL2:OUT.6 |
ENAL | input | TCELL2:IMUX.CTRL.2 |
ENAU | input | TCELL2:IMUX.CTRL.3 |
ENBL | input | TCELL1:IMUX.CTRL.6 |
ENBU | input | TCELL1:IMUX.CTRL.7 |
FULL | output | TCELL2:OUT.5 |
INJECTDBITERR | input | TCELL2:IMUX.IMUX.12 |
INJECTSBITERR | input | TCELL2:IMUX.IMUX.8 |
PROGEMPTY | output | TCELL2:OUT.2 |
PROGFULL | output | TCELL2:OUT.1 |
RDADDRECC0 | output | TCELL0:OUT.13 |
RDADDRECC1 | output | TCELL0:OUT.14 |
RDADDRECC2 | output | TCELL0:OUT.17 |
RDADDRECC3 | output | TCELL0:OUT.18 |
RDADDRECC4 | output | TCELL0:OUT.21 |
RDADDRECC5 | output | TCELL0:OUT.22 |
RDADDRECC6 | output | TCELL0:OUT.25 |
RDADDRECC7 | output | TCELL0:OUT.26 |
RDADDRECC8 | output | TCELL0:OUT.29 |
RDCOUNT0 | output | TCELL3:OUT.30 |
RDCOUNT1 | output | TCELL3:OUT.29 |
RDCOUNT10 | output | TCELL3:OUT.10 |
RDCOUNT11 | output | TCELL3:OUT.9 |
RDCOUNT12 | output | TCELL3:OUT.6 |
RDCOUNT13 | output | TCELL3:OUT.5 |
RDCOUNT2 | output | TCELL3:OUT.26 |
RDCOUNT3 | output | TCELL3:OUT.25 |
RDCOUNT4 | output | TCELL3:OUT.22 |
RDCOUNT5 | output | TCELL3:OUT.21 |
RDCOUNT6 | output | TCELL3:OUT.18 |
RDCOUNT7 | output | TCELL3:OUT.17 |
RDCOUNT8 | output | TCELL3:OUT.14 |
RDCOUNT9 | output | TCELL3:OUT.13 |
RDERR | output | TCELL2:OUT.14 |
RDRSTBUSY | output | TCELL4:OUT.1 |
REGCEAL | input | TCELL2:IMUX.CTRL.7 |
REGCEAU | input | TCELL2:IMUX.CTRL.6 |
REGCEBL | input | TCELL1:IMUX.CTRL.2 |
REGCEBU | input | TCELL1:IMUX.CTRL.3 |
RSTFIFO | input | TCELL4:IMUX.CTRL.1 |
RSTRAMAL | input | TCELL3:IMUX.CTRL.3 |
RSTRAMAU | input | TCELL3:IMUX.CTRL.2 |
RSTRAMBL | input | TCELL1:IMUX.CTRL.0 |
RSTRAMBU | input | TCELL1:IMUX.CTRL.1 |
RSTREGAL | input | TCELL3:IMUX.CTRL.1 |
RSTREGAU | input | TCELL3:IMUX.CTRL.0 |
RSTREGBL | input | TCELL2:IMUX.CTRL.0 |
RSTREGBU | input | TCELL2:IMUX.CTRL.1 |
SBITERR | output | TCELL2:OUT.9 |
SLEEPL | input | TCELL4:IMUX.IMUX.45 |
SLEEPU | input | TCELL4:IMUX.IMUX.15 |
TSTBRAMRST | input | TCELL2:IMUX.IMUX.30 |
TSTCNT0 | input | TCELL0:IMUX.IMUX.20 |
TSTCNT1 | input | TCELL0:IMUX.IMUX.6 |
TSTCNT10 | input | TCELL4:IMUX.IMUX.26 |
TSTCNT11 | input | TCELL4:IMUX.IMUX.8 |
TSTCNT12 | input | TCELL4:IMUX.IMUX.38 |
TSTCNT2 | input | TCELL0:IMUX.IMUX.36 |
TSTCNT3 | input | TCELL0:IMUX.IMUX.12 |
TSTCNT4 | input | TCELL1:IMUX.IMUX.2 |
TSTCNT5 | input | TCELL1:IMUX.IMUX.26 |
TSTCNT6 | input | TCELL3:IMUX.IMUX.34 |
TSTCNT7 | input | TCELL3:IMUX.IMUX.40 |
TSTCNT8 | input | TCELL4:IMUX.IMUX.13 |
TSTCNT9 | input | TCELL4:IMUX.IMUX.2 |
TSTFLAGIN | input | TCELL3:IMUX.IMUX.8 |
TSTOFF | input | TCELL1:IMUX.IMUX.32 |
TSTRDCNTOFF | input | TCELL3:IMUX.IMUX.36 |
TSTRDOS0 | input | TCELL3:IMUX.IMUX.38 |
TSTRDOS1 | input | TCELL3:IMUX.IMUX.12 |
TSTRDOS10 | input | TCELL4:IMUX.IMUX.40 |
TSTRDOS11 | input | TCELL4:IMUX.IMUX.42 |
TSTRDOS12 | input | TCELL4:IMUX.IMUX.12 |
TSTRDOS2 | input | TCELL4:IMUX.IMUX.0 |
TSTRDOS3 | input | TCELL4:IMUX.IMUX.18 |
TSTRDOS4 | input | TCELL4:IMUX.IMUX.22 |
TSTRDOS5 | input | TCELL4:IMUX.IMUX.24 |
TSTRDOS6 | input | TCELL4:IMUX.IMUX.28 |
TSTRDOS7 | input | TCELL4:IMUX.IMUX.6 |
TSTRDOS8 | input | TCELL4:IMUX.IMUX.34 |
TSTRDOS9 | input | TCELL4:IMUX.IMUX.36 |
TSTRINGEN_X | input | TCELL2:IMUX.IMUX.40 |
TSTRINGOUTDIV4 | output | TCELL1:OUT.30 |
TSTRINGSTART_X | input | TCELL3:IMUX.IMUX.18 |
TSTSTAGEVALID | output | TCELL1:OUT.29 |
TSTWRCNTOFF | input | TCELL1:IMUX.IMUX.6 |
TSTWROS0 | input | TCELL0:IMUX.IMUX.22 |
TSTWROS1 | input | TCELL0:IMUX.IMUX.24 |
TSTWROS10 | input | TCELL1:IMUX.IMUX.22 |
TSTWROS11 | input | TCELL1:IMUX.IMUX.24 |
TSTWROS12 | input | TCELL1:IMUX.IMUX.28 |
TSTWROS2 | input | TCELL0:IMUX.IMUX.4 |
TSTWROS3 | input | TCELL0:IMUX.IMUX.5 |
TSTWROS4 | input | TCELL0:IMUX.IMUX.32 |
TSTWROS5 | input | TCELL0:IMUX.IMUX.34 |
TSTWROS6 | input | TCELL0:IMUX.IMUX.38 |
TSTWROS7 | input | TCELL0:IMUX.IMUX.40 |
TSTWROS8 | input | TCELL1:IMUX.IMUX.0 |
TSTWROS9 | input | TCELL1:IMUX.IMUX.18 |
TST_QUIETENAL | output | TCELL2:OUT.10 |
TST_QUIETENAU | output | TCELL3:OUT.2 |
TST_QUIETENBL | output | TCELL2:OUT.8 |
TST_QUIETENBU | output | TCELL3:OUT.1 |
TST_SLEEP_CNTL | output | TCELL4:OUT.9 |
WEAL0 | input | TCELL2:IMUX.IMUX.23 |
WEAL1 | input | TCELL2:IMUX.IMUX.24 |
WEAL2 | input | TCELL2:IMUX.IMUX.5 |
WEAL3 | input | TCELL2:IMUX.IMUX.27 |
WEAU0 | input | TCELL2:IMUX.IMUX.4 |
WEAU1 | input | TCELL2:IMUX.IMUX.25 |
WEAU2 | input | TCELL2:IMUX.IMUX.26 |
WEAU3 | input | TCELL2:IMUX.IMUX.6 |
WEBL0 | input | TCELL2:IMUX.IMUX.34 |
WEBL1 | input | TCELL2:IMUX.IMUX.10 |
WEBL2 | input | TCELL2:IMUX.IMUX.37 |
WEBL3 | input | TCELL2:IMUX.IMUX.39 |
WEBU0 | input | TCELL2:IMUX.IMUX.35 |
WEBU1 | input | TCELL2:IMUX.IMUX.36 |
WEBU2 | input | TCELL2:IMUX.IMUX.11 |
WEBU3 | input | TCELL2:IMUX.IMUX.38 |
WRCOUNT0 | output | TCELL1:OUT.26 |
WRCOUNT1 | output | TCELL1:OUT.25 |
WRCOUNT10 | output | TCELL1:OUT.6 |
WRCOUNT11 | output | TCELL1:OUT.5 |
WRCOUNT12 | output | TCELL1:OUT.2 |
WRCOUNT13 | output | TCELL1:OUT.1 |
WRCOUNT2 | output | TCELL1:OUT.22 |
WRCOUNT3 | output | TCELL1:OUT.21 |
WRCOUNT4 | output | TCELL1:OUT.18 |
WRCOUNT5 | output | TCELL1:OUT.17 |
WRCOUNT6 | output | TCELL1:OUT.14 |
WRCOUNT7 | output | TCELL1:OUT.13 |
WRCOUNT8 | output | TCELL1:OUT.10 |
WRCOUNT9 | output | TCELL1:OUT.9 |
WRERR | output | TCELL2:OUT.23 |
WRRSTBUSY | output | TCELL0:OUT.30 |
Bel BRAM_H0
Pin | Direction | Wires |
---|---|---|
ADDRAL1 | input | TCELL0:IMUX.IMUX.42 |
ADDRAL10 | input | TCELL3:IMUX.IMUX.32 |
ADDRAL11 | input | TCELL3:IMUX.IMUX.42 |
ADDRAL12 | input | TCELL4:IMUX.IMUX.16 |
ADDRAL13 | input | TCELL4:IMUX.IMUX.4 |
ADDRAL14 | input | TCELL4:IMUX.IMUX.32 |
ADDRAL2 | input | TCELL1:IMUX.IMUX.16 |
ADDRAL3 | input | TCELL1:IMUX.IMUX.4 |
ADDRAL4 | input | TCELL1:IMUX.IMUX.8 |
ADDRAL5 | input | TCELL1:IMUX.IMUX.43 |
ADDRAL6 | input | TCELL2:IMUX.IMUX.17 |
ADDRAL7 | input | TCELL2:IMUX.IMUX.42 |
ADDRAL8 | input | TCELL3:IMUX.IMUX.17 |
ADDRAL9 | input | TCELL3:IMUX.IMUX.4 |
ADDRBL1 | input | TCELL0:IMUX.IMUX.45 |
ADDRBL10 | input | TCELL3:IMUX.IMUX.10 |
ADDRBL11 | input | TCELL3:IMUX.IMUX.45 |
ADDRBL12 | input | TCELL4:IMUX.IMUX.20 |
ADDRBL13 | input | TCELL4:IMUX.IMUX.30 |
ADDRBL14 | input | TCELL4:IMUX.IMUX.10 |
ADDRBL2 | input | TCELL1:IMUX.IMUX.20 |
ADDRBL3 | input | TCELL1:IMUX.IMUX.30 |
ADDRBL4 | input | TCELL1:IMUX.IMUX.10 |
ADDRBL5 | input | TCELL1:IMUX.IMUX.46 |
ADDRBL6 | input | TCELL2:IMUX.IMUX.21 |
ADDRBL7 | input | TCELL2:IMUX.IMUX.45 |
ADDRBL8 | input | TCELL3:IMUX.IMUX.21 |
ADDRBL9 | input | TCELL3:IMUX.IMUX.31 |
ADDRENAL | input | TCELL2:IMUX.IMUX.44 |
ADDRENBL | input | TCELL1:IMUX.IMUX.44 |
CASDIMUXAL | input | TCELL2:IMUX.IMUX.32 |
CASDIMUXBL | input | TCELL2:IMUX.IMUX.7 |
CASDOMUXAL | input | TCELL3:IMUX.IMUX.27 |
CASDOMUXBL | input | TCELL2:IMUX.IMUX.20 |
CASDOMUXENAL | input | TCELL1:IMUX.IMUX.40 |
CASDOMUXENBL | input | TCELL3:IMUX.IMUX.20 |
CASOREGIMUXAL | input | TCELL3:IMUX.IMUX.28 |
CASOREGIMUXBL | input | TCELL0:IMUX.IMUX.30 |
CASOREGIMUXENAL | input | TCELL0:IMUX.IMUX.44 |
CASOREGIMUXENBL | input | TCELL1:IMUX.IMUX.39 |
CLKAL | input | TCELL1:IMUX.CTRL.5 |
CLKBL | input | TCELL1:IMUX.CTRL.4 |
DIAL0 | input | TCELL0:IMUX.IMUX.17 |
DIAL1 | input | TCELL0:IMUX.IMUX.25 |
DIAL10 | input | TCELL0:IMUX.IMUX.37 |
DIAL11 | input | TCELL0:IMUX.IMUX.14 |
DIAL12 | input | TCELL1:IMUX.IMUX.29 |
DIAL13 | input | TCELL1:IMUX.IMUX.37 |
DIAL14 | input | TCELL1:IMUX.IMUX.14 |
DIAL15 | input | TCELL2:IMUX.IMUX.2 |
DIAL2 | input | TCELL0:IMUX.IMUX.9 |
DIAL3 | input | TCELL0:IMUX.IMUX.41 |
DIAL4 | input | TCELL1:IMUX.IMUX.25 |
DIAL5 | input | TCELL1:IMUX.IMUX.9 |
DIAL6 | input | TCELL1:IMUX.IMUX.42 |
DIAL7 | input | TCELL2:IMUX.IMUX.0 |
DIAL8 | input | TCELL0:IMUX.IMUX.21 |
DIAL9 | input | TCELL0:IMUX.IMUX.29 |
DIBL0 | input | TCELL0:IMUX.IMUX.19 |
DIBL1 | input | TCELL0:IMUX.IMUX.27 |
DIBL10 | input | TCELL0:IMUX.IMUX.39 |
DIBL11 | input | TCELL0:IMUX.IMUX.47 |
DIBL12 | input | TCELL1:IMUX.IMUX.31 |
DIBL13 | input | TCELL1:IMUX.IMUX.36 |
DIBL14 | input | TCELL1:IMUX.IMUX.47 |
DIBL15 | input | TCELL2:IMUX.IMUX.28 |
DIBL2 | input | TCELL0:IMUX.IMUX.35 |
DIBL3 | input | TCELL0:IMUX.IMUX.43 |
DIBL4 | input | TCELL1:IMUX.IMUX.27 |
DIBL5 | input | TCELL1:IMUX.IMUX.35 |
DIBL6 | input | TCELL1:IMUX.IMUX.12 |
DIBL7 | input | TCELL2:IMUX.IMUX.19 |
DIBL8 | input | TCELL0:IMUX.IMUX.23 |
DIBL9 | input | TCELL0:IMUX.IMUX.31 |
DIPAL0 | input | TCELL1:IMUX.IMUX.17 |
DIPAL1 | input | TCELL1:IMUX.IMUX.21 |
DIPBL0 | input | TCELL1:IMUX.IMUX.19 |
DIPBL1 | input | TCELL1:IMUX.IMUX.23 |
DOAL0 | output | TCELL0:OUT.0 |
DOAL1 | output | TCELL0:OUT.8 |
DOAL10 | output | TCELL0:OUT.20 |
DOAL11 | output | TCELL0:OUT.28 |
DOAL12 | output | TCELL1:OUT.12 |
DOAL13 | output | TCELL1:OUT.20 |
DOAL14 | output | TCELL1:OUT.28 |
DOAL15 | output | TCELL2:OUT.4 |
DOAL2 | output | TCELL0:OUT.16 |
DOAL3 | output | TCELL0:OUT.24 |
DOAL4 | output | TCELL1:OUT.8 |
DOAL5 | output | TCELL1:OUT.16 |
DOAL6 | output | TCELL1:OUT.24 |
DOAL7 | output | TCELL2:OUT.0 |
DOAL8 | output | TCELL0:OUT.4 |
DOAL9 | output | TCELL0:OUT.12 |
DOBL0 | output | TCELL0:OUT.3 |
DOBL1 | output | TCELL0:OUT.11 |
DOBL10 | output | TCELL0:OUT.23 |
DOBL11 | output | TCELL0:OUT.31 |
DOBL12 | output | TCELL1:OUT.15 |
DOBL13 | output | TCELL1:OUT.23 |
DOBL14 | output | TCELL1:OUT.31 |
DOBL15 | output | TCELL2:OUT.7 |
DOBL2 | output | TCELL0:OUT.19 |
DOBL3 | output | TCELL0:OUT.27 |
DOBL4 | output | TCELL1:OUT.11 |
DOBL5 | output | TCELL1:OUT.19 |
DOBL6 | output | TCELL1:OUT.27 |
DOBL7 | output | TCELL2:OUT.3 |
DOBL8 | output | TCELL0:OUT.7 |
DOBL9 | output | TCELL0:OUT.15 |
DOPAL0 | output | TCELL1:OUT.0 |
DOPAL1 | output | TCELL1:OUT.4 |
DOPBL0 | output | TCELL1:OUT.3 |
DOPBL1 | output | TCELL1:OUT.7 |
EMPTY | output | TCELL2:OUT.6 |
ENAL | input | TCELL2:IMUX.CTRL.2 |
ENBL | input | TCELL1:IMUX.CTRL.6 |
FULL | output | TCELL2:OUT.5 |
PROGEMPTY | output | TCELL2:OUT.2 |
PROGFULL | output | TCELL2:OUT.1 |
RDCOUNT0 | output | TCELL3:OUT.30 |
RDCOUNT1 | output | TCELL3:OUT.29 |
RDCOUNT10 | output | TCELL3:OUT.10 |
RDCOUNT11 | output | TCELL3:OUT.9 |
RDCOUNT12 | output | TCELL3:OUT.6 |
RDCOUNT2 | output | TCELL3:OUT.26 |
RDCOUNT3 | output | TCELL3:OUT.25 |
RDCOUNT4 | output | TCELL3:OUT.22 |
RDCOUNT5 | output | TCELL3:OUT.21 |
RDCOUNT6 | output | TCELL3:OUT.18 |
RDCOUNT7 | output | TCELL3:OUT.17 |
RDCOUNT8 | output | TCELL3:OUT.14 |
RDCOUNT9 | output | TCELL3:OUT.13 |
RDERR | output | TCELL2:OUT.14 |
RDRSTBUSY | output | TCELL4:OUT.1 |
REGCEAL | input | TCELL2:IMUX.CTRL.7 |
REGCEBL | input | TCELL1:IMUX.CTRL.2 |
RSTFIFO | input | TCELL4:IMUX.CTRL.1 |
RSTRAMAL | input | TCELL3:IMUX.CTRL.3 |
RSTRAMBL | input | TCELL1:IMUX.CTRL.0 |
RSTREGAL | input | TCELL3:IMUX.CTRL.1 |
RSTREGBL | input | TCELL2:IMUX.CTRL.0 |
SLEEPL | input | TCELL4:IMUX.IMUX.45 |
WEAL0 | input | TCELL2:IMUX.IMUX.23 |
WEAL1 | input | TCELL2:IMUX.IMUX.24 |
WEAL2 | input | TCELL2:IMUX.IMUX.5 |
WEAL3 | input | TCELL2:IMUX.IMUX.27 |
WEBL0 | input | TCELL2:IMUX.IMUX.34 |
WEBL1 | input | TCELL2:IMUX.IMUX.10 |
WEBL2 | input | TCELL2:IMUX.IMUX.37 |
WEBL3 | input | TCELL2:IMUX.IMUX.39 |
WRCOUNT0 | output | TCELL1:OUT.26 |
WRCOUNT1 | output | TCELL1:OUT.25 |
WRCOUNT10 | output | TCELL1:OUT.6 |
WRCOUNT11 | output | TCELL1:OUT.5 |
WRCOUNT12 | output | TCELL1:OUT.2 |
WRCOUNT2 | output | TCELL1:OUT.22 |
WRCOUNT3 | output | TCELL1:OUT.21 |
WRCOUNT4 | output | TCELL1:OUT.18 |
WRCOUNT5 | output | TCELL1:OUT.17 |
WRCOUNT6 | output | TCELL1:OUT.14 |
WRCOUNT7 | output | TCELL1:OUT.13 |
WRCOUNT8 | output | TCELL1:OUT.10 |
WRCOUNT9 | output | TCELL1:OUT.9 |
WRERR | output | TCELL2:OUT.23 |
WRRSTBUSY | output | TCELL0:OUT.30 |
Bel BRAM_H1
Pin | Direction | Wires |
---|---|---|
ADDRAU1 | input | TCELL0:IMUX.IMUX.13 |
ADDRAU10 | input | TCELL3:IMUX.IMUX.9 |
ADDRAU11 | input | TCELL3:IMUX.IMUX.13 |
ADDRAU12 | input | TCELL4:IMUX.IMUX.1 |
ADDRAU13 | input | TCELL4:IMUX.IMUX.5 |
ADDRAU14 | input | TCELL4:IMUX.IMUX.9 |
ADDRAU2 | input | TCELL1:IMUX.IMUX.1 |
ADDRAU3 | input | TCELL1:IMUX.IMUX.5 |
ADDRAU4 | input | TCELL1:IMUX.IMUX.33 |
ADDRAU5 | input | TCELL1:IMUX.IMUX.13 |
ADDRAU6 | input | TCELL2:IMUX.IMUX.1 |
ADDRAU7 | input | TCELL2:IMUX.IMUX.13 |
ADDRAU8 | input | TCELL3:IMUX.IMUX.1 |
ADDRAU9 | input | TCELL3:IMUX.IMUX.25 |
ADDRBU1 | input | TCELL0:IMUX.IMUX.15 |
ADDRBU10 | input | TCELL3:IMUX.IMUX.11 |
ADDRBU11 | input | TCELL3:IMUX.IMUX.15 |
ADDRBU12 | input | TCELL4:IMUX.IMUX.3 |
ADDRBU13 | input | TCELL4:IMUX.IMUX.7 |
ADDRBU14 | input | TCELL4:IMUX.IMUX.11 |
ADDRBU2 | input | TCELL1:IMUX.IMUX.3 |
ADDRBU3 | input | TCELL1:IMUX.IMUX.7 |
ADDRBU4 | input | TCELL1:IMUX.IMUX.11 |
ADDRBU5 | input | TCELL1:IMUX.IMUX.15 |
ADDRBU6 | input | TCELL2:IMUX.IMUX.3 |
ADDRBU7 | input | TCELL2:IMUX.IMUX.15 |
ADDRBU8 | input | TCELL3:IMUX.IMUX.3 |
ADDRBU9 | input | TCELL3:IMUX.IMUX.7 |
ADDRENAU | input | TCELL2:IMUX.IMUX.46 |
ADDRENBU | input | TCELL1:IMUX.IMUX.45 |
CASDIMUXAU | input | TCELL2:IMUX.IMUX.33 |
CASDIMUXBU | input | TCELL2:IMUX.IMUX.31 |
CASDOMUXAU | input | TCELL3:IMUX.IMUX.26 |
CASDOMUXBU | input | TCELL2:IMUX.IMUX.22 |
CASDOMUXENAU | input | TCELL1:IMUX.IMUX.41 |
CASDOMUXENBU | input | TCELL3:IMUX.IMUX.22 |
CASOREGIMUXAU | input | TCELL3:IMUX.IMUX.29 |
CASOREGIMUXBU | input | TCELL0:IMUX.IMUX.7 |
CASOREGIMUXENAU | input | TCELL0:IMUX.IMUX.46 |
CASOREGIMUXENBU | input | TCELL1:IMUX.IMUX.38 |
CLKAU | input | TCELL3:IMUX.CTRL.5 |
CLKBU | input | TCELL3:IMUX.CTRL.4 |
DIAU0 | input | TCELL2:IMUX.IMUX.43 |
DIAU1 | input | TCELL3:IMUX.IMUX.19 |
DIAU10 | input | TCELL3:IMUX.IMUX.30 |
DIAU11 | input | TCELL3:IMUX.IMUX.39 |
DIAU12 | input | TCELL4:IMUX.IMUX.23 |
DIAU13 | input | TCELL4:IMUX.IMUX.31 |
DIAU14 | input | TCELL4:IMUX.IMUX.39 |
DIAU15 | input | TCELL4:IMUX.IMUX.47 |
DIAU2 | input | TCELL3:IMUX.IMUX.24 |
DIAU3 | input | TCELL3:IMUX.IMUX.35 |
DIAU4 | input | TCELL4:IMUX.IMUX.19 |
DIAU5 | input | TCELL4:IMUX.IMUX.27 |
DIAU6 | input | TCELL4:IMUX.IMUX.35 |
DIAU7 | input | TCELL4:IMUX.IMUX.43 |
DIAU8 | input | TCELL2:IMUX.IMUX.47 |
DIAU9 | input | TCELL3:IMUX.IMUX.23 |
DIBU0 | input | TCELL2:IMUX.IMUX.41 |
DIBU1 | input | TCELL3:IMUX.IMUX.0 |
DIBU10 | input | TCELL3:IMUX.IMUX.6 |
DIBU11 | input | TCELL3:IMUX.IMUX.37 |
DIBU12 | input | TCELL4:IMUX.IMUX.21 |
DIBU13 | input | TCELL4:IMUX.IMUX.29 |
DIBU14 | input | TCELL4:IMUX.IMUX.37 |
DIBU15 | input | TCELL4:IMUX.IMUX.14 |
DIBU2 | input | TCELL3:IMUX.IMUX.5 |
DIBU3 | input | TCELL3:IMUX.IMUX.33 |
DIBU4 | input | TCELL4:IMUX.IMUX.17 |
DIBU5 | input | TCELL4:IMUX.IMUX.25 |
DIBU6 | input | TCELL4:IMUX.IMUX.33 |
DIBU7 | input | TCELL4:IMUX.IMUX.41 |
DIBU8 | input | TCELL2:IMUX.IMUX.14 |
DIBU9 | input | TCELL3:IMUX.IMUX.2 |
DIPAU0 | input | TCELL3:IMUX.IMUX.43 |
DIPAU1 | input | TCELL3:IMUX.IMUX.47 |
DIPBU0 | input | TCELL3:IMUX.IMUX.41 |
DIPBU1 | input | TCELL3:IMUX.IMUX.14 |
DOAU0 | output | TCELL2:OUT.27 |
DOAU1 | output | TCELL3:OUT.3 |
DOAU10 | output | TCELL3:OUT.15 |
DOAU11 | output | TCELL3:OUT.23 |
DOAU12 | output | TCELL4:OUT.7 |
DOAU13 | output | TCELL4:OUT.15 |
DOAU14 | output | TCELL4:OUT.23 |
DOAU15 | output | TCELL4:OUT.31 |
DOAU2 | output | TCELL3:OUT.11 |
DOAU3 | output | TCELL3:OUT.19 |
DOAU4 | output | TCELL4:OUT.3 |
DOAU5 | output | TCELL4:OUT.11 |
DOAU6 | output | TCELL4:OUT.19 |
DOAU7 | output | TCELL4:OUT.27 |
DOAU8 | output | TCELL2:OUT.31 |
DOAU9 | output | TCELL3:OUT.7 |
DOBU0 | output | TCELL2:OUT.24 |
DOBU1 | output | TCELL3:OUT.0 |
DOBU10 | output | TCELL3:OUT.12 |
DOBU11 | output | TCELL3:OUT.20 |
DOBU12 | output | TCELL4:OUT.4 |
DOBU13 | output | TCELL4:OUT.12 |
DOBU14 | output | TCELL4:OUT.20 |
DOBU15 | output | TCELL4:OUT.28 |
DOBU2 | output | TCELL3:OUT.8 |
DOBU3 | output | TCELL3:OUT.16 |
DOBU4 | output | TCELL4:OUT.0 |
DOBU5 | output | TCELL4:OUT.8 |
DOBU6 | output | TCELL4:OUT.16 |
DOBU7 | output | TCELL4:OUT.24 |
DOBU8 | output | TCELL2:OUT.28 |
DOBU9 | output | TCELL3:OUT.4 |
DOPAU0 | output | TCELL3:OUT.27 |
DOPAU1 | output | TCELL3:OUT.31 |
DOPBU0 | output | TCELL3:OUT.24 |
DOPBU1 | output | TCELL3:OUT.28 |
ENAU | input | TCELL2:IMUX.CTRL.3 |
ENBU | input | TCELL1:IMUX.CTRL.7 |
REGCEAU | input | TCELL2:IMUX.CTRL.6 |
REGCEBU | input | TCELL1:IMUX.CTRL.3 |
RSTRAMAU | input | TCELL3:IMUX.CTRL.2 |
RSTRAMBU | input | TCELL1:IMUX.CTRL.1 |
RSTREGAU | input | TCELL3:IMUX.CTRL.0 |
RSTREGBU | input | TCELL2:IMUX.CTRL.1 |
SLEEPU | input | TCELL4:IMUX.IMUX.15 |
WEAU0 | input | TCELL2:IMUX.IMUX.4 |
WEAU1 | input | TCELL2:IMUX.IMUX.25 |
WEAU2 | input | TCELL2:IMUX.IMUX.26 |
WEAU3 | input | TCELL2:IMUX.IMUX.6 |
WEBU0 | input | TCELL2:IMUX.IMUX.35 |
WEBU1 | input | TCELL2:IMUX.IMUX.36 |
WEBU2 | input | TCELL2:IMUX.IMUX.11 |
WEBU3 | input | TCELL2:IMUX.IMUX.38 |
Bel wires
Wire | Pins |
---|---|
TCELL0:OUT.0 | BRAM_F.DOAL0, BRAM_H0.DOAL0 |
TCELL0:OUT.3 | BRAM_F.DOBL0, BRAM_H0.DOBL0 |
TCELL0:OUT.4 | BRAM_F.DOAL8, BRAM_H0.DOAL8 |
TCELL0:OUT.7 | BRAM_F.DOBL8, BRAM_H0.DOBL8 |
TCELL0:OUT.8 | BRAM_F.DOAL1, BRAM_H0.DOAL1 |
TCELL0:OUT.11 | BRAM_F.DOBL1, BRAM_H0.DOBL1 |
TCELL0:OUT.12 | BRAM_F.DOAL9, BRAM_H0.DOAL9 |
TCELL0:OUT.13 | BRAM_F.RDADDRECC0 |
TCELL0:OUT.14 | BRAM_F.RDADDRECC1 |
TCELL0:OUT.15 | BRAM_F.DOBL9, BRAM_H0.DOBL9 |
TCELL0:OUT.16 | BRAM_F.DOAL2, BRAM_H0.DOAL2 |
TCELL0:OUT.17 | BRAM_F.RDADDRECC2 |
TCELL0:OUT.18 | BRAM_F.RDADDRECC3 |
TCELL0:OUT.19 | BRAM_F.DOBL2, BRAM_H0.DOBL2 |
TCELL0:OUT.20 | BRAM_F.DOAL10, BRAM_H0.DOAL10 |
TCELL0:OUT.21 | BRAM_F.RDADDRECC4 |
TCELL0:OUT.22 | BRAM_F.RDADDRECC5 |
TCELL0:OUT.23 | BRAM_F.DOBL10, BRAM_H0.DOBL10 |
TCELL0:OUT.24 | BRAM_F.DOAL3, BRAM_H0.DOAL3 |
TCELL0:OUT.25 | BRAM_F.RDADDRECC6 |
TCELL0:OUT.26 | BRAM_F.RDADDRECC7 |
TCELL0:OUT.27 | BRAM_F.DOBL3, BRAM_H0.DOBL3 |
TCELL0:OUT.28 | BRAM_F.DOAL11, BRAM_H0.DOAL11 |
TCELL0:OUT.29 | BRAM_F.RDADDRECC8 |
TCELL0:OUT.30 | BRAM_F.WRRSTBUSY, BRAM_H0.WRRSTBUSY |
TCELL0:OUT.31 | BRAM_F.DOBL11, BRAM_H0.DOBL11 |
TCELL0:IMUX.IMUX.4 | BRAM_F.TSTWROS2 |
TCELL0:IMUX.IMUX.5 | BRAM_F.TSTWROS3 |
TCELL0:IMUX.IMUX.6 | BRAM_F.TSTCNT1 |
TCELL0:IMUX.IMUX.7 | BRAM_F.CASOREGIMUXBU, BRAM_H1.CASOREGIMUXBU |
TCELL0:IMUX.IMUX.8 | BRAM_F.ADDRAL0 |
TCELL0:IMUX.IMUX.9 | BRAM_F.DIAL2, BRAM_H0.DIAL2 |
TCELL0:IMUX.IMUX.10 | BRAM_F.ADDRBL0 |
TCELL0:IMUX.IMUX.11 | BRAM_F.ADDRBU0 |
TCELL0:IMUX.IMUX.12 | BRAM_F.TSTCNT3 |
TCELL0:IMUX.IMUX.13 | BRAM_F.ADDRAU1, BRAM_H1.ADDRAU1 |
TCELL0:IMUX.IMUX.14 | BRAM_F.DIAL11, BRAM_H0.DIAL11 |
TCELL0:IMUX.IMUX.15 | BRAM_F.ADDRBU1, BRAM_H1.ADDRBU1 |
TCELL0:IMUX.IMUX.17 | BRAM_F.DIAL0, BRAM_H0.DIAL0 |
TCELL0:IMUX.IMUX.19 | BRAM_F.DIBL0, BRAM_H0.DIBL0 |
TCELL0:IMUX.IMUX.20 | BRAM_F.TSTCNT0 |
TCELL0:IMUX.IMUX.21 | BRAM_F.DIAL8, BRAM_H0.DIAL8 |
TCELL0:IMUX.IMUX.22 | BRAM_F.TSTWROS0 |
TCELL0:IMUX.IMUX.23 | BRAM_F.DIBL8, BRAM_H0.DIBL8 |
TCELL0:IMUX.IMUX.24 | BRAM_F.TSTWROS1 |
TCELL0:IMUX.IMUX.25 | BRAM_F.DIAL1, BRAM_H0.DIAL1 |
TCELL0:IMUX.IMUX.27 | BRAM_F.DIBL1, BRAM_H0.DIBL1 |
TCELL0:IMUX.IMUX.29 | BRAM_F.DIAL9, BRAM_H0.DIAL9 |
TCELL0:IMUX.IMUX.30 | BRAM_F.CASOREGIMUXBL, BRAM_H0.CASOREGIMUXBL |
TCELL0:IMUX.IMUX.31 | BRAM_F.DIBL9, BRAM_H0.DIBL9 |
TCELL0:IMUX.IMUX.32 | BRAM_F.TSTWROS4 |
TCELL0:IMUX.IMUX.33 | BRAM_F.ADDRAU0 |
TCELL0:IMUX.IMUX.34 | BRAM_F.TSTWROS5 |
TCELL0:IMUX.IMUX.35 | BRAM_F.DIBL2, BRAM_H0.DIBL2 |
TCELL0:IMUX.IMUX.36 | BRAM_F.TSTCNT2 |
TCELL0:IMUX.IMUX.37 | BRAM_F.DIAL10, BRAM_H0.DIAL10 |
TCELL0:IMUX.IMUX.38 | BRAM_F.TSTWROS6 |
TCELL0:IMUX.IMUX.39 | BRAM_F.DIBL10, BRAM_H0.DIBL10 |
TCELL0:IMUX.IMUX.40 | BRAM_F.TSTWROS7 |
TCELL0:IMUX.IMUX.41 | BRAM_F.DIAL3, BRAM_H0.DIAL3 |
TCELL0:IMUX.IMUX.42 | BRAM_F.ADDRAL1, BRAM_H0.ADDRAL1 |
TCELL0:IMUX.IMUX.43 | BRAM_F.DIBL3, BRAM_H0.DIBL3 |
TCELL0:IMUX.IMUX.44 | BRAM_F.CASOREGIMUXENAL, BRAM_H0.CASOREGIMUXENAL |
TCELL0:IMUX.IMUX.45 | BRAM_F.ADDRBL1, BRAM_H0.ADDRBL1 |
TCELL0:IMUX.IMUX.46 | BRAM_F.CASOREGIMUXENAU, BRAM_H1.CASOREGIMUXENAU |
TCELL0:IMUX.IMUX.47 | BRAM_F.DIBL11, BRAM_H0.DIBL11 |
TCELL1:OUT.0 | BRAM_F.DOPAL0, BRAM_H0.DOPAL0 |
TCELL1:OUT.1 | BRAM_F.WRCOUNT13 |
TCELL1:OUT.2 | BRAM_F.WRCOUNT12, BRAM_H0.WRCOUNT12 |
TCELL1:OUT.3 | BRAM_F.DOPBL0, BRAM_H0.DOPBL0 |
TCELL1:OUT.4 | BRAM_F.DOPAL1, BRAM_H0.DOPAL1 |
TCELL1:OUT.5 | BRAM_F.WRCOUNT11, BRAM_H0.WRCOUNT11 |
TCELL1:OUT.6 | BRAM_F.WRCOUNT10, BRAM_H0.WRCOUNT10 |
TCELL1:OUT.7 | BRAM_F.DOPBL1, BRAM_H0.DOPBL1 |
TCELL1:OUT.8 | BRAM_F.DOAL4, BRAM_H0.DOAL4 |
TCELL1:OUT.9 | BRAM_F.WRCOUNT9, BRAM_H0.WRCOUNT9 |
TCELL1:OUT.10 | BRAM_F.WRCOUNT8, BRAM_H0.WRCOUNT8 |
TCELL1:OUT.11 | BRAM_F.DOBL4, BRAM_H0.DOBL4 |
TCELL1:OUT.12 | BRAM_F.DOAL12, BRAM_H0.DOAL12 |
TCELL1:OUT.13 | BRAM_F.WRCOUNT7, BRAM_H0.WRCOUNT7 |
TCELL1:OUT.14 | BRAM_F.WRCOUNT6, BRAM_H0.WRCOUNT6 |
TCELL1:OUT.15 | BRAM_F.DOBL12, BRAM_H0.DOBL12 |
TCELL1:OUT.16 | BRAM_F.DOAL5, BRAM_H0.DOAL5 |
TCELL1:OUT.17 | BRAM_F.WRCOUNT5, BRAM_H0.WRCOUNT5 |
TCELL1:OUT.18 | BRAM_F.WRCOUNT4, BRAM_H0.WRCOUNT4 |
TCELL1:OUT.19 | BRAM_F.DOBL5, BRAM_H0.DOBL5 |
TCELL1:OUT.20 | BRAM_F.DOAL13, BRAM_H0.DOAL13 |
TCELL1:OUT.21 | BRAM_F.WRCOUNT3, BRAM_H0.WRCOUNT3 |
TCELL1:OUT.22 | BRAM_F.WRCOUNT2, BRAM_H0.WRCOUNT2 |
TCELL1:OUT.23 | BRAM_F.DOBL13, BRAM_H0.DOBL13 |
TCELL1:OUT.24 | BRAM_F.DOAL6, BRAM_H0.DOAL6 |
TCELL1:OUT.25 | BRAM_F.WRCOUNT1, BRAM_H0.WRCOUNT1 |
TCELL1:OUT.26 | BRAM_F.WRCOUNT0, BRAM_H0.WRCOUNT0 |
TCELL1:OUT.27 | BRAM_F.DOBL6, BRAM_H0.DOBL6 |
TCELL1:OUT.28 | BRAM_F.DOAL14, BRAM_H0.DOAL14 |
TCELL1:OUT.29 | BRAM_F.TSTSTAGEVALID |
TCELL1:OUT.30 | BRAM_F.TSTRINGOUTDIV4 |
TCELL1:OUT.31 | BRAM_F.DOBL14, BRAM_H0.DOBL14 |
TCELL1:IMUX.CTRL.0 | BRAM_F.RSTRAMBL, BRAM_H0.RSTRAMBL |
TCELL1:IMUX.CTRL.1 | BRAM_F.RSTRAMBU, BRAM_H1.RSTRAMBU |
TCELL1:IMUX.CTRL.2 | BRAM_F.REGCEBL, BRAM_H0.REGCEBL |
TCELL1:IMUX.CTRL.3 | BRAM_F.REGCEBU, BRAM_H1.REGCEBU |
TCELL1:IMUX.CTRL.4 | BRAM_F.CLKBL, BRAM_H0.CLKBL |
TCELL1:IMUX.CTRL.5 | BRAM_F.CLKAL, BRAM_H0.CLKAL |
TCELL1:IMUX.CTRL.6 | BRAM_F.ENBL, BRAM_H0.ENBL |
TCELL1:IMUX.CTRL.7 | BRAM_F.ENBU, BRAM_H1.ENBU |
TCELL1:IMUX.IMUX.0 | BRAM_F.TSTWROS8 |
TCELL1:IMUX.IMUX.1 | BRAM_F.ADDRAU2, BRAM_H1.ADDRAU2 |
TCELL1:IMUX.IMUX.2 | BRAM_F.TSTCNT4 |
TCELL1:IMUX.IMUX.3 | BRAM_F.ADDRBU2, BRAM_H1.ADDRBU2 |
TCELL1:IMUX.IMUX.4 | BRAM_F.ADDRAL3, BRAM_H0.ADDRAL3 |
TCELL1:IMUX.IMUX.5 | BRAM_F.ADDRAU3, BRAM_H1.ADDRAU3 |
TCELL1:IMUX.IMUX.6 | BRAM_F.TSTWRCNTOFF |
TCELL1:IMUX.IMUX.7 | BRAM_F.ADDRBU3, BRAM_H1.ADDRBU3 |
TCELL1:IMUX.IMUX.8 | BRAM_F.ADDRAL4, BRAM_H0.ADDRAL4 |
TCELL1:IMUX.IMUX.9 | BRAM_F.DIAL5, BRAM_H0.DIAL5 |
TCELL1:IMUX.IMUX.10 | BRAM_F.ADDRBL4, BRAM_H0.ADDRBL4 |
TCELL1:IMUX.IMUX.11 | BRAM_F.ADDRBU4, BRAM_H1.ADDRBU4 |
TCELL1:IMUX.IMUX.12 | BRAM_F.DIBL6, BRAM_H0.DIBL6 |
TCELL1:IMUX.IMUX.13 | BRAM_F.ADDRAU5, BRAM_H1.ADDRAU5 |
TCELL1:IMUX.IMUX.14 | BRAM_F.DIAL14, BRAM_H0.DIAL14 |
TCELL1:IMUX.IMUX.15 | BRAM_F.ADDRBU5, BRAM_H1.ADDRBU5 |
TCELL1:IMUX.IMUX.16 | BRAM_F.ADDRAL2, BRAM_H0.ADDRAL2 |
TCELL1:IMUX.IMUX.17 | BRAM_F.DIPAL0, BRAM_H0.DIPAL0 |
TCELL1:IMUX.IMUX.18 | BRAM_F.TSTWROS9 |
TCELL1:IMUX.IMUX.19 | BRAM_F.DIPBL0, BRAM_H0.DIPBL0 |
TCELL1:IMUX.IMUX.20 | BRAM_F.ADDRBL2, BRAM_H0.ADDRBL2 |
TCELL1:IMUX.IMUX.21 | BRAM_F.DIPAL1, BRAM_H0.DIPAL1 |
TCELL1:IMUX.IMUX.22 | BRAM_F.TSTWROS10 |
TCELL1:IMUX.IMUX.23 | BRAM_F.DIPBL1, BRAM_H0.DIPBL1 |
TCELL1:IMUX.IMUX.24 | BRAM_F.TSTWROS11 |
TCELL1:IMUX.IMUX.25 | BRAM_F.DIAL4, BRAM_H0.DIAL4 |
TCELL1:IMUX.IMUX.26 | BRAM_F.TSTCNT5 |
TCELL1:IMUX.IMUX.27 | BRAM_F.DIBL4, BRAM_H0.DIBL4 |
TCELL1:IMUX.IMUX.28 | BRAM_F.TSTWROS12 |
TCELL1:IMUX.IMUX.29 | BRAM_F.DIAL12, BRAM_H0.DIAL12 |
TCELL1:IMUX.IMUX.30 | BRAM_F.ADDRBL3, BRAM_H0.ADDRBL3 |
TCELL1:IMUX.IMUX.31 | BRAM_F.DIBL12, BRAM_H0.DIBL12 |
TCELL1:IMUX.IMUX.32 | BRAM_F.TSTOFF |
TCELL1:IMUX.IMUX.33 | BRAM_F.ADDRAU4, BRAM_H1.ADDRAU4 |
TCELL1:IMUX.IMUX.35 | BRAM_F.DIBL5, BRAM_H0.DIBL5 |
TCELL1:IMUX.IMUX.36 | BRAM_F.DIBL13, BRAM_H0.DIBL13 |
TCELL1:IMUX.IMUX.37 | BRAM_F.DIAL13, BRAM_H0.DIAL13 |
TCELL1:IMUX.IMUX.38 | BRAM_F.CASOREGIMUXENBU, BRAM_H1.CASOREGIMUXENBU |
TCELL1:IMUX.IMUX.39 | BRAM_F.CASOREGIMUXENBL, BRAM_H0.CASOREGIMUXENBL |
TCELL1:IMUX.IMUX.40 | BRAM_F.CASDOMUXENAL, BRAM_H0.CASDOMUXENAL |
TCELL1:IMUX.IMUX.41 | BRAM_F.CASDOMUXENAU, BRAM_H1.CASDOMUXENAU |
TCELL1:IMUX.IMUX.42 | BRAM_F.DIAL6, BRAM_H0.DIAL6 |
TCELL1:IMUX.IMUX.43 | BRAM_F.ADDRAL5, BRAM_H0.ADDRAL5 |
TCELL1:IMUX.IMUX.44 | BRAM_F.ADDRENBL, BRAM_H0.ADDRENBL |
TCELL1:IMUX.IMUX.45 | BRAM_F.ADDRENBU, BRAM_H1.ADDRENBU |
TCELL1:IMUX.IMUX.46 | BRAM_F.ADDRBL5, BRAM_H0.ADDRBL5 |
TCELL1:IMUX.IMUX.47 | BRAM_F.DIBL14, BRAM_H0.DIBL14 |
TCELL2:OUT.0 | BRAM_F.DOAL7, BRAM_H0.DOAL7 |
TCELL2:OUT.1 | BRAM_F.PROGFULL, BRAM_H0.PROGFULL |
TCELL2:OUT.2 | BRAM_F.PROGEMPTY, BRAM_H0.PROGEMPTY |
TCELL2:OUT.3 | BRAM_F.DOBL7, BRAM_H0.DOBL7 |
TCELL2:OUT.4 | BRAM_F.DOAL15, BRAM_H0.DOAL15 |
TCELL2:OUT.5 | BRAM_F.FULL, BRAM_H0.FULL |
TCELL2:OUT.6 | BRAM_F.EMPTY, BRAM_H0.EMPTY |
TCELL2:OUT.7 | BRAM_F.DOBL15, BRAM_H0.DOBL15 |
TCELL2:OUT.8 | BRAM_F.TST_QUIETENBL |
TCELL2:OUT.9 | BRAM_F.SBITERR |
TCELL2:OUT.10 | BRAM_F.TST_QUIETENAL |
TCELL2:OUT.14 | BRAM_F.RDERR, BRAM_H0.RDERR |
TCELL2:OUT.16 | BRAM_F.DBITERR |
TCELL2:OUT.23 | BRAM_F.WRERR, BRAM_H0.WRERR |
TCELL2:OUT.24 | BRAM_F.DOBU0, BRAM_H1.DOBU0 |
TCELL2:OUT.27 | BRAM_F.DOAU0, BRAM_H1.DOAU0 |
TCELL2:OUT.28 | BRAM_F.DOBU8, BRAM_H1.DOBU8 |
TCELL2:OUT.31 | BRAM_F.DOAU8, BRAM_H1.DOAU8 |
TCELL2:IMUX.CTRL.0 | BRAM_F.RSTREGBL, BRAM_H0.RSTREGBL |
TCELL2:IMUX.CTRL.1 | BRAM_F.RSTREGBU, BRAM_H1.RSTREGBU |
TCELL2:IMUX.CTRL.2 | BRAM_F.ENAL, BRAM_H0.ENAL |
TCELL2:IMUX.CTRL.3 | BRAM_F.ENAU, BRAM_H1.ENAU |
TCELL2:IMUX.CTRL.6 | BRAM_F.REGCEAU, BRAM_H1.REGCEAU |
TCELL2:IMUX.CTRL.7 | BRAM_F.REGCEAL, BRAM_H0.REGCEAL |
TCELL2:IMUX.IMUX.0 | BRAM_F.DIAL7, BRAM_H0.DIAL7 |
TCELL2:IMUX.IMUX.1 | BRAM_F.ADDRAU6, BRAM_H1.ADDRAU6 |
TCELL2:IMUX.IMUX.2 | BRAM_F.DIAL15, BRAM_H0.DIAL15 |
TCELL2:IMUX.IMUX.3 | BRAM_F.ADDRBU6, BRAM_H1.ADDRBU6 |
TCELL2:IMUX.IMUX.4 | BRAM_F.WEAU0, BRAM_H1.WEAU0 |
TCELL2:IMUX.IMUX.5 | BRAM_F.WEAL2, BRAM_H0.WEAL2 |
TCELL2:IMUX.IMUX.6 | BRAM_F.WEAU3, BRAM_H1.WEAU3 |
TCELL2:IMUX.IMUX.7 | BRAM_F.CASDIMUXBL, BRAM_H0.CASDIMUXBL |
TCELL2:IMUX.IMUX.8 | BRAM_F.INJECTSBITERR |
TCELL2:IMUX.IMUX.10 | BRAM_F.WEBL1, BRAM_H0.WEBL1 |
TCELL2:IMUX.IMUX.11 | BRAM_F.WEBU2, BRAM_H1.WEBU2 |
TCELL2:IMUX.IMUX.12 | BRAM_F.INJECTDBITERR |
TCELL2:IMUX.IMUX.13 | BRAM_F.ADDRAU7, BRAM_H1.ADDRAU7 |
TCELL2:IMUX.IMUX.14 | BRAM_F.DIBU8, BRAM_H1.DIBU8 |
TCELL2:IMUX.IMUX.15 | BRAM_F.ADDRBU7, BRAM_H1.ADDRBU7 |
TCELL2:IMUX.IMUX.17 | BRAM_F.ADDRAL6, BRAM_H0.ADDRAL6 |
TCELL2:IMUX.IMUX.19 | BRAM_F.DIBL7, BRAM_H0.DIBL7 |
TCELL2:IMUX.IMUX.20 | BRAM_F.CASDOMUXBL, BRAM_H0.CASDOMUXBL |
TCELL2:IMUX.IMUX.21 | BRAM_F.ADDRBL6, BRAM_H0.ADDRBL6 |
TCELL2:IMUX.IMUX.22 | BRAM_F.CASDOMUXBU, BRAM_H1.CASDOMUXBU |
TCELL2:IMUX.IMUX.23 | BRAM_F.WEAL0, BRAM_H0.WEAL0 |
TCELL2:IMUX.IMUX.24 | BRAM_F.WEAL1, BRAM_H0.WEAL1 |
TCELL2:IMUX.IMUX.25 | BRAM_F.WEAU1, BRAM_H1.WEAU1 |
TCELL2:IMUX.IMUX.26 | BRAM_F.WEAU2, BRAM_H1.WEAU2 |
TCELL2:IMUX.IMUX.27 | BRAM_F.WEAL3, BRAM_H0.WEAL3 |
TCELL2:IMUX.IMUX.28 | BRAM_F.DIBL15, BRAM_H0.DIBL15 |
TCELL2:IMUX.IMUX.29 | BRAM_F.ECCPIPECE |
TCELL2:IMUX.IMUX.30 | BRAM_F.TSTBRAMRST |
TCELL2:IMUX.IMUX.31 | BRAM_F.CASDIMUXBU, BRAM_H1.CASDIMUXBU |
TCELL2:IMUX.IMUX.32 | BRAM_F.CASDIMUXAL, BRAM_H0.CASDIMUXAL |
TCELL2:IMUX.IMUX.33 | BRAM_F.CASDIMUXAU, BRAM_H1.CASDIMUXAU |
TCELL2:IMUX.IMUX.34 | BRAM_F.WEBL0, BRAM_H0.WEBL0 |
TCELL2:IMUX.IMUX.35 | BRAM_F.WEBU0, BRAM_H1.WEBU0 |
TCELL2:IMUX.IMUX.36 | BRAM_F.WEBU1, BRAM_H1.WEBU1 |
TCELL2:IMUX.IMUX.37 | BRAM_F.WEBL2, BRAM_H0.WEBL2 |
TCELL2:IMUX.IMUX.38 | BRAM_F.WEBU3, BRAM_H1.WEBU3 |
TCELL2:IMUX.IMUX.39 | BRAM_F.WEBL3, BRAM_H0.WEBL3 |
TCELL2:IMUX.IMUX.40 | BRAM_F.TSTRINGEN_X |
TCELL2:IMUX.IMUX.41 | BRAM_F.DIBU0, BRAM_H1.DIBU0 |
TCELL2:IMUX.IMUX.42 | BRAM_F.ADDRAL7, BRAM_H0.ADDRAL7 |
TCELL2:IMUX.IMUX.43 | BRAM_F.DIAU0, BRAM_H1.DIAU0 |
TCELL2:IMUX.IMUX.44 | BRAM_F.ADDRENAL, BRAM_H0.ADDRENAL |
TCELL2:IMUX.IMUX.45 | BRAM_F.ADDRBL7, BRAM_H0.ADDRBL7 |
TCELL2:IMUX.IMUX.46 | BRAM_F.ADDRENAU, BRAM_H1.ADDRENAU |
TCELL2:IMUX.IMUX.47 | BRAM_F.DIAU8, BRAM_H1.DIAU8 |
TCELL3:OUT.0 | BRAM_F.DOBU1, BRAM_H1.DOBU1 |
TCELL3:OUT.1 | BRAM_F.TST_QUIETENBU |
TCELL3:OUT.2 | BRAM_F.TST_QUIETENAU |
TCELL3:OUT.3 | BRAM_F.DOAU1, BRAM_H1.DOAU1 |
TCELL3:OUT.4 | BRAM_F.DOBU9, BRAM_H1.DOBU9 |
TCELL3:OUT.5 | BRAM_F.RDCOUNT13 |
TCELL3:OUT.6 | BRAM_F.RDCOUNT12, BRAM_H0.RDCOUNT12 |
TCELL3:OUT.7 | BRAM_F.DOAU9, BRAM_H1.DOAU9 |
TCELL3:OUT.8 | BRAM_F.DOBU2, BRAM_H1.DOBU2 |
TCELL3:OUT.9 | BRAM_F.RDCOUNT11, BRAM_H0.RDCOUNT11 |
TCELL3:OUT.10 | BRAM_F.RDCOUNT10, BRAM_H0.RDCOUNT10 |
TCELL3:OUT.11 | BRAM_F.DOAU2, BRAM_H1.DOAU2 |
TCELL3:OUT.12 | BRAM_F.DOBU10, BRAM_H1.DOBU10 |
TCELL3:OUT.13 | BRAM_F.RDCOUNT9, BRAM_H0.RDCOUNT9 |
TCELL3:OUT.14 | BRAM_F.RDCOUNT8, BRAM_H0.RDCOUNT8 |
TCELL3:OUT.15 | BRAM_F.DOAU10, BRAM_H1.DOAU10 |
TCELL3:OUT.16 | BRAM_F.DOBU3, BRAM_H1.DOBU3 |
TCELL3:OUT.17 | BRAM_F.RDCOUNT7, BRAM_H0.RDCOUNT7 |
TCELL3:OUT.18 | BRAM_F.RDCOUNT6, BRAM_H0.RDCOUNT6 |
TCELL3:OUT.19 | BRAM_F.DOAU3, BRAM_H1.DOAU3 |
TCELL3:OUT.20 | BRAM_F.DOBU11, BRAM_H1.DOBU11 |
TCELL3:OUT.21 | BRAM_F.RDCOUNT5, BRAM_H0.RDCOUNT5 |
TCELL3:OUT.22 | BRAM_F.RDCOUNT4, BRAM_H0.RDCOUNT4 |
TCELL3:OUT.23 | BRAM_F.DOAU11, BRAM_H1.DOAU11 |
TCELL3:OUT.24 | BRAM_F.DOPBU0, BRAM_H1.DOPBU0 |
TCELL3:OUT.25 | BRAM_F.RDCOUNT3, BRAM_H0.RDCOUNT3 |
TCELL3:OUT.26 | BRAM_F.RDCOUNT2, BRAM_H0.RDCOUNT2 |
TCELL3:OUT.27 | BRAM_F.DOPAU0, BRAM_H1.DOPAU0 |
TCELL3:OUT.28 | BRAM_F.DOPBU1, BRAM_H1.DOPBU1 |
TCELL3:OUT.29 | BRAM_F.RDCOUNT1, BRAM_H0.RDCOUNT1 |
TCELL3:OUT.30 | BRAM_F.RDCOUNT0, BRAM_H0.RDCOUNT0 |
TCELL3:OUT.31 | BRAM_F.DOPAU1, BRAM_H1.DOPAU1 |
TCELL3:IMUX.CTRL.0 | BRAM_F.RSTREGAU, BRAM_H1.RSTREGAU |
TCELL3:IMUX.CTRL.1 | BRAM_F.RSTREGAL, BRAM_H0.RSTREGAL |
TCELL3:IMUX.CTRL.2 | BRAM_F.RSTRAMAU, BRAM_H1.RSTRAMAU |
TCELL3:IMUX.CTRL.3 | BRAM_F.RSTRAMAL, BRAM_H0.RSTRAMAL |
TCELL3:IMUX.CTRL.4 | BRAM_F.CLKBU, BRAM_H1.CLKBU |
TCELL3:IMUX.CTRL.5 | BRAM_F.CLKAU, BRAM_H1.CLKAU |
TCELL3:IMUX.IMUX.0 | BRAM_F.DIBU1, BRAM_H1.DIBU1 |
TCELL3:IMUX.IMUX.1 | BRAM_F.ADDRAU8, BRAM_H1.ADDRAU8 |
TCELL3:IMUX.IMUX.2 | BRAM_F.DIBU9, BRAM_H1.DIBU9 |
TCELL3:IMUX.IMUX.3 | BRAM_F.ADDRBU8, BRAM_H1.ADDRBU8 |
TCELL3:IMUX.IMUX.4 | BRAM_F.ADDRAL9, BRAM_H0.ADDRAL9 |
TCELL3:IMUX.IMUX.5 | BRAM_F.DIBU2, BRAM_H1.DIBU2 |
TCELL3:IMUX.IMUX.6 | BRAM_F.DIBU10, BRAM_H1.DIBU10 |
TCELL3:IMUX.IMUX.7 | BRAM_F.ADDRBU9, BRAM_H1.ADDRBU9 |
TCELL3:IMUX.IMUX.8 | BRAM_F.TSTFLAGIN |
TCELL3:IMUX.IMUX.9 | BRAM_F.ADDRAU10, BRAM_H1.ADDRAU10 |
TCELL3:IMUX.IMUX.10 | BRAM_F.ADDRBL10, BRAM_H0.ADDRBL10 |
TCELL3:IMUX.IMUX.11 | BRAM_F.ADDRBU10, BRAM_H1.ADDRBU10 |
TCELL3:IMUX.IMUX.12 | BRAM_F.TSTRDOS1 |
TCELL3:IMUX.IMUX.13 | BRAM_F.ADDRAU11, BRAM_H1.ADDRAU11 |
TCELL3:IMUX.IMUX.14 | BRAM_F.DIPBU1, BRAM_H1.DIPBU1 |
TCELL3:IMUX.IMUX.15 | BRAM_F.ADDRBU11, BRAM_H1.ADDRBU11 |
TCELL3:IMUX.IMUX.17 | BRAM_F.ADDRAL8, BRAM_H0.ADDRAL8 |
TCELL3:IMUX.IMUX.18 | BRAM_F.TSTRINGSTART_X |
TCELL3:IMUX.IMUX.19 | BRAM_F.DIAU1, BRAM_H1.DIAU1 |
TCELL3:IMUX.IMUX.20 | BRAM_F.CASDOMUXENBL, BRAM_H0.CASDOMUXENBL |
TCELL3:IMUX.IMUX.21 | BRAM_F.ADDRBL8, BRAM_H0.ADDRBL8 |
TCELL3:IMUX.IMUX.22 | BRAM_F.CASDOMUXENBU, BRAM_H1.CASDOMUXENBU |
TCELL3:IMUX.IMUX.23 | BRAM_F.DIAU9, BRAM_H1.DIAU9 |
TCELL3:IMUX.IMUX.24 | BRAM_F.DIAU2, BRAM_H1.DIAU2 |
TCELL3:IMUX.IMUX.25 | BRAM_F.ADDRAU9, BRAM_H1.ADDRAU9 |
TCELL3:IMUX.IMUX.26 | BRAM_F.CASDOMUXAU, BRAM_H1.CASDOMUXAU |
TCELL3:IMUX.IMUX.27 | BRAM_F.CASDOMUXAL, BRAM_H0.CASDOMUXAL |
TCELL3:IMUX.IMUX.28 | BRAM_F.CASOREGIMUXAL, BRAM_H0.CASOREGIMUXAL |
TCELL3:IMUX.IMUX.29 | BRAM_F.CASOREGIMUXAU, BRAM_H1.CASOREGIMUXAU |
TCELL3:IMUX.IMUX.30 | BRAM_F.DIAU10, BRAM_H1.DIAU10 |
TCELL3:IMUX.IMUX.31 | BRAM_F.ADDRBL9, BRAM_H0.ADDRBL9 |
TCELL3:IMUX.IMUX.32 | BRAM_F.ADDRAL10, BRAM_H0.ADDRAL10 |
TCELL3:IMUX.IMUX.33 | BRAM_F.DIBU3, BRAM_H1.DIBU3 |
TCELL3:IMUX.IMUX.34 | BRAM_F.TSTCNT6 |
TCELL3:IMUX.IMUX.35 | BRAM_F.DIAU3, BRAM_H1.DIAU3 |
TCELL3:IMUX.IMUX.36 | BRAM_F.TSTRDCNTOFF |
TCELL3:IMUX.IMUX.37 | BRAM_F.DIBU11, BRAM_H1.DIBU11 |
TCELL3:IMUX.IMUX.38 | BRAM_F.TSTRDOS0 |
TCELL3:IMUX.IMUX.39 | BRAM_F.DIAU11, BRAM_H1.DIAU11 |
TCELL3:IMUX.IMUX.40 | BRAM_F.TSTCNT7 |
TCELL3:IMUX.IMUX.41 | BRAM_F.DIPBU0, BRAM_H1.DIPBU0 |
TCELL3:IMUX.IMUX.42 | BRAM_F.ADDRAL11, BRAM_H0.ADDRAL11 |
TCELL3:IMUX.IMUX.43 | BRAM_F.DIPAU0, BRAM_H1.DIPAU0 |
TCELL3:IMUX.IMUX.45 | BRAM_F.ADDRBL11, BRAM_H0.ADDRBL11 |
TCELL3:IMUX.IMUX.47 | BRAM_F.DIPAU1, BRAM_H1.DIPAU1 |
TCELL4:OUT.0 | BRAM_F.DOBU4, BRAM_H1.DOBU4 |
TCELL4:OUT.1 | BRAM_F.RDRSTBUSY, BRAM_H0.RDRSTBUSY |
TCELL4:OUT.2 | BRAM_F.ECCPARITY0 |
TCELL4:OUT.3 | BRAM_F.DOAU4, BRAM_H1.DOAU4 |
TCELL4:OUT.4 | BRAM_F.DOBU12, BRAM_H1.DOBU12 |
TCELL4:OUT.5 | BRAM_F.ECCPARITY1 |
TCELL4:OUT.6 | BRAM_F.ECCPARITY2 |
TCELL4:OUT.7 | BRAM_F.DOAU12, BRAM_H1.DOAU12 |
TCELL4:OUT.8 | BRAM_F.DOBU5, BRAM_H1.DOBU5 |
TCELL4:OUT.9 | BRAM_F.TST_SLEEP_CNTL |
TCELL4:OUT.10 | BRAM_F.ECCPARITY3 |
TCELL4:OUT.11 | BRAM_F.DOAU5, BRAM_H1.DOAU5 |
TCELL4:OUT.12 | BRAM_F.DOBU13, BRAM_H1.DOBU13 |
TCELL4:OUT.13 | BRAM_F.ECCPARITY4 |
TCELL4:OUT.14 | BRAM_F.ECCPARITY5 |
TCELL4:OUT.15 | BRAM_F.DOAU13, BRAM_H1.DOAU13 |
TCELL4:OUT.16 | BRAM_F.DOBU6, BRAM_H1.DOBU6 |
TCELL4:OUT.17 | BRAM_F.ECCPARITY6 |
TCELL4:OUT.18 | BRAM_F.ECCPARITY7 |
TCELL4:OUT.19 | BRAM_F.DOAU6, BRAM_H1.DOAU6 |
TCELL4:OUT.20 | BRAM_F.DOBU14, BRAM_H1.DOBU14 |
TCELL4:OUT.23 | BRAM_F.DOAU14, BRAM_H1.DOAU14 |
TCELL4:OUT.24 | BRAM_F.DOBU7, BRAM_H1.DOBU7 |
TCELL4:OUT.27 | BRAM_F.DOAU7, BRAM_H1.DOAU7 |
TCELL4:OUT.28 | BRAM_F.DOBU15, BRAM_H1.DOBU15 |
TCELL4:OUT.31 | BRAM_F.DOAU15, BRAM_H1.DOAU15 |
TCELL4:IMUX.CTRL.1 | BRAM_F.RSTFIFO, BRAM_H0.RSTFIFO |
TCELL4:IMUX.IMUX.0 | BRAM_F.TSTRDOS2 |
TCELL4:IMUX.IMUX.1 | BRAM_F.ADDRAU12, BRAM_H1.ADDRAU12 |
TCELL4:IMUX.IMUX.2 | BRAM_F.TSTCNT9 |
TCELL4:IMUX.IMUX.3 | BRAM_F.ADDRBU12, BRAM_H1.ADDRBU12 |
TCELL4:IMUX.IMUX.4 | BRAM_F.ADDRAL13, BRAM_H0.ADDRAL13 |
TCELL4:IMUX.IMUX.5 | BRAM_F.ADDRAU13, BRAM_H1.ADDRAU13 |
TCELL4:IMUX.IMUX.6 | BRAM_F.TSTRDOS7 |
TCELL4:IMUX.IMUX.7 | BRAM_F.ADDRBU13, BRAM_H1.ADDRBU13 |
TCELL4:IMUX.IMUX.8 | BRAM_F.TSTCNT11 |
TCELL4:IMUX.IMUX.9 | BRAM_F.ADDRAU14, BRAM_H1.ADDRAU14 |
TCELL4:IMUX.IMUX.10 | BRAM_F.ADDRBL14, BRAM_H0.ADDRBL14 |
TCELL4:IMUX.IMUX.11 | BRAM_F.ADDRBU14, BRAM_H1.ADDRBU14 |
TCELL4:IMUX.IMUX.12 | BRAM_F.TSTRDOS12 |
TCELL4:IMUX.IMUX.13 | BRAM_F.TSTCNT8 |
TCELL4:IMUX.IMUX.14 | BRAM_F.DIBU15, BRAM_H1.DIBU15 |
TCELL4:IMUX.IMUX.15 | BRAM_F.SLEEPU, BRAM_H1.SLEEPU |
TCELL4:IMUX.IMUX.16 | BRAM_F.ADDRAL12, BRAM_H0.ADDRAL12 |
TCELL4:IMUX.IMUX.17 | BRAM_F.DIBU4, BRAM_H1.DIBU4 |
TCELL4:IMUX.IMUX.18 | BRAM_F.TSTRDOS3 |
TCELL4:IMUX.IMUX.19 | BRAM_F.DIAU4, BRAM_H1.DIAU4 |
TCELL4:IMUX.IMUX.20 | BRAM_F.ADDRBL12, BRAM_H0.ADDRBL12 |
TCELL4:IMUX.IMUX.21 | BRAM_F.DIBU12, BRAM_H1.DIBU12 |
TCELL4:IMUX.IMUX.22 | BRAM_F.TSTRDOS4 |
TCELL4:IMUX.IMUX.23 | BRAM_F.DIAU12, BRAM_H1.DIAU12 |
TCELL4:IMUX.IMUX.24 | BRAM_F.TSTRDOS5 |
TCELL4:IMUX.IMUX.25 | BRAM_F.DIBU5, BRAM_H1.DIBU5 |
TCELL4:IMUX.IMUX.26 | BRAM_F.TSTCNT10 |
TCELL4:IMUX.IMUX.27 | BRAM_F.DIAU5, BRAM_H1.DIAU5 |
TCELL4:IMUX.IMUX.28 | BRAM_F.TSTRDOS6 |
TCELL4:IMUX.IMUX.29 | BRAM_F.DIBU13, BRAM_H1.DIBU13 |
TCELL4:IMUX.IMUX.30 | BRAM_F.ADDRBL13, BRAM_H0.ADDRBL13 |
TCELL4:IMUX.IMUX.31 | BRAM_F.DIAU13, BRAM_H1.DIAU13 |
TCELL4:IMUX.IMUX.32 | BRAM_F.ADDRAL14, BRAM_H0.ADDRAL14 |
TCELL4:IMUX.IMUX.33 | BRAM_F.DIBU6, BRAM_H1.DIBU6 |
TCELL4:IMUX.IMUX.34 | BRAM_F.TSTRDOS8 |
TCELL4:IMUX.IMUX.35 | BRAM_F.DIAU6, BRAM_H1.DIAU6 |
TCELL4:IMUX.IMUX.36 | BRAM_F.TSTRDOS9 |
TCELL4:IMUX.IMUX.37 | BRAM_F.DIBU14, BRAM_H1.DIBU14 |
TCELL4:IMUX.IMUX.38 | BRAM_F.TSTCNT12 |
TCELL4:IMUX.IMUX.39 | BRAM_F.DIAU14, BRAM_H1.DIAU14 |
TCELL4:IMUX.IMUX.40 | BRAM_F.TSTRDOS10 |
TCELL4:IMUX.IMUX.41 | BRAM_F.DIBU7, BRAM_H1.DIBU7 |
TCELL4:IMUX.IMUX.42 | BRAM_F.TSTRDOS11 |
TCELL4:IMUX.IMUX.43 | BRAM_F.DIAU7, BRAM_H1.DIAU7 |
TCELL4:IMUX.IMUX.45 | BRAM_F.SLEEPL, BRAM_H0.SLEEPL |
TCELL4:IMUX.IMUX.47 | BRAM_F.DIAU15, BRAM_H1.DIAU15 |
Tile HARD_SYNC
Cells: 1 IRIs: 0
Bel HARD_SYNC0
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX.CTRL.2 |
DIN | input | IMUX.IMUX.16 |
DOUT | output | OUT.1 |
SR | input | IMUX.IMUX.0 |
Bel HARD_SYNC1
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX.CTRL.3 |
DIN | input | IMUX.IMUX.18 |
DOUT | output | OUT.2 |
SR | input | IMUX.IMUX.1 |
Bel HARD_SYNC2
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX.CTRL.4 |
DIN | input | IMUX.IMUX.26 |
DOUT | output | OUT.5 |
SR | input | IMUX.IMUX.2 |
Bel HARD_SYNC3
Pin | Direction | Wires |
---|---|---|
CLK | input | IMUX.CTRL.5 |
DIN | input | IMUX.IMUX.28 |
DOUT | output | OUT.6 |
SR | input | IMUX.IMUX.3 |
Bel wires
Wire | Pins |
---|---|
OUT.1 | HARD_SYNC0.DOUT |
OUT.2 | HARD_SYNC1.DOUT |
OUT.5 | HARD_SYNC2.DOUT |
OUT.6 | HARD_SYNC3.DOUT |
IMUX.CTRL.2 | HARD_SYNC0.CLK |
IMUX.CTRL.3 | HARD_SYNC1.CLK |
IMUX.CTRL.4 | HARD_SYNC2.CLK |
IMUX.CTRL.5 | HARD_SYNC3.CLK |
IMUX.IMUX.0 | HARD_SYNC0.SR |
IMUX.IMUX.1 | HARD_SYNC1.SR |
IMUX.IMUX.2 | HARD_SYNC2.SR |
IMUX.IMUX.3 | HARD_SYNC3.SR |
IMUX.IMUX.16 | HARD_SYNC0.DIN |
IMUX.IMUX.18 | HARD_SYNC1.DIN |
IMUX.IMUX.26 | HARD_SYNC2.DIN |
IMUX.IMUX.28 | HARD_SYNC3.DIN |