Configuration center
Tile CFG
Cells: 60 IRIs: 0
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| BSCAN_CDR1 | output | TCELL42:OUT.4 |
| BSCAN_CDR2 | output | TCELL42:OUT.6 |
| BSCAN_CDR3 | output | TCELL54:OUT.18 |
| BSCAN_CDR4 | output | TCELL54:OUT.20 |
| BSCAN_CLKDR1 | output | TCELL42:OUT.8 |
| BSCAN_CLKDR2 | output | TCELL42:OUT.10 |
| BSCAN_CLKDR3 | output | TCELL54:OUT.22 |
| BSCAN_CLKDR4 | output | TCELL54:OUT.24 |
| BSCAN_RTI1 | output | TCELL42:OUT.12 |
| BSCAN_RTI2 | output | TCELL42:OUT.14 |
| BSCAN_RTI3 | output | TCELL54:OUT.26 |
| BSCAN_RTI4 | output | TCELL54:OUT.28 |
| BSCAN_SDR1 | output | TCELL42:OUT.16 |
| BSCAN_SDR2 | output | TCELL42:OUT.18 |
| BSCAN_SDR3 | output | TCELL53:OUT.0 |
| BSCAN_SDR4 | output | TCELL53:OUT.2 |
| BSCAN_SEL1 | output | TCELL42:OUT.20 |
| BSCAN_SEL2 | output | TCELL42:OUT.22 |
| BSCAN_SEL3 | output | TCELL53:OUT.4 |
| BSCAN_SEL4 | output | TCELL53:OUT.6 |
| BSCAN_TCK1 | output | TCELL43:OUT.6 |
| BSCAN_TCK2 | output | TCELL43:OUT.8 |
| BSCAN_TCK3 | output | TCELL54:OUT.6 |
| BSCAN_TCK4 | output | TCELL54:OUT.8 |
| BSCAN_TDI1 | output | TCELL43:OUT.14 |
| BSCAN_TDI2 | output | TCELL43:OUT.16 |
| BSCAN_TDI3 | output | TCELL54:OUT.14 |
| BSCAN_TDI4 | output | TCELL54:OUT.16 |
| BSCAN_TDO1 | input | TCELL43:IMUX.IMUX.2 |
| BSCAN_TDO2 | input | TCELL43:IMUX.IMUX.3 |
| BSCAN_TDO3 | input | TCELL54:IMUX.IMUX.2 |
| BSCAN_TDO4 | input | TCELL54:IMUX.IMUX.3 |
| BSCAN_TLR1 | output | TCELL42:OUT.24 |
| BSCAN_TLR2 | output | TCELL42:OUT.26 |
| BSCAN_TLR3 | output | TCELL53:OUT.8 |
| BSCAN_TLR4 | output | TCELL53:OUT.10 |
| BSCAN_TMS1 | output | TCELL43:OUT.10 |
| BSCAN_TMS2 | output | TCELL43:OUT.12 |
| BSCAN_TMS3 | output | TCELL54:OUT.10 |
| BSCAN_TMS4 | output | TCELL54:OUT.12 |
| BSCAN_UDR1 | output | TCELL42:OUT.28 |
| BSCAN_UDR2 | output | TCELL42:OUT.30 |
| BSCAN_UDR3 | output | TCELL53:OUT.12 |
| BSCAN_UDR4 | output | TCELL53:OUT.14 |
| DCI_LOCK | output | TCELL42:OUT.2 |
| DCI_USR_RESET_IN | input | TCELL42:IMUX.IMUX.3 |
| ECC_END_OF_FRAME | output | TCELL51:OUT.26 |
| ECC_END_OF_SCAN | output | TCELL51:OUT.28 |
| ECC_ERROR_NOTSINGLE | output | TCELL51:OUT.22 |
| ECC_ERROR_SINGLE | output | TCELL51:OUT.24 |
| ECC_FAR0 | output | TCELL52:OUT.0 |
| ECC_FAR1 | output | TCELL52:OUT.2 |
| ECC_FAR10 | output | TCELL52:OUT.20 |
| ECC_FAR11 | output | TCELL52:OUT.22 |
| ECC_FAR12 | output | TCELL52:OUT.24 |
| ECC_FAR13 | output | TCELL52:OUT.26 |
| ECC_FAR14 | output | TCELL52:OUT.28 |
| ECC_FAR15 | output | TCELL52:OUT.30 |
| ECC_FAR16 | output | TCELL51:OUT.0 |
| ECC_FAR17 | output | TCELL51:OUT.2 |
| ECC_FAR18 | output | TCELL51:OUT.4 |
| ECC_FAR19 | output | TCELL51:OUT.6 |
| ECC_FAR2 | output | TCELL52:OUT.4 |
| ECC_FAR20 | output | TCELL51:OUT.8 |
| ECC_FAR21 | output | TCELL51:OUT.10 |
| ECC_FAR22 | output | TCELL51:OUT.12 |
| ECC_FAR23 | output | TCELL51:OUT.14 |
| ECC_FAR24 | output | TCELL51:OUT.16 |
| ECC_FAR25 | output | TCELL51:OUT.18 |
| ECC_FAR26 | output | TCELL52:OUT.31 |
| ECC_FAR3 | output | TCELL52:OUT.6 |
| ECC_FAR4 | output | TCELL52:OUT.8 |
| ECC_FAR5 | output | TCELL52:OUT.10 |
| ECC_FAR6 | output | TCELL52:OUT.12 |
| ECC_FAR7 | output | TCELL52:OUT.14 |
| ECC_FAR8 | output | TCELL52:OUT.16 |
| ECC_FAR9 | output | TCELL52:OUT.18 |
| ECC_FAR_SEL0 | input | TCELL51:IMUX.IMUX.15 |
| ECC_FAR_SEL1 | input | TCELL51:IMUX.IMUX.16 |
| EOS | output | TCELL47:OUT.10 |
| ICAP_AVAIL_BOT | output | TCELL43:OUT.4 |
| ICAP_AVAIL_TOP | output | TCELL54:OUT.4 |
| ICAP_CLK_BOT | input | TCELL45:IMUX.CTRL.0 |
| ICAP_CLK_TOP | input | TCELL56:IMUX.CTRL.0 |
| ICAP_CS_B_BOT | input | TCELL43:IMUX.IMUX.1 |
| ICAP_CS_B_TOP | input | TCELL54:IMUX.IMUX.1 |
| ICAP_DATA_BOT0 | input | TCELL44:IMUX.IMUX.0 |
| ICAP_DATA_BOT1 | input | TCELL44:IMUX.IMUX.1 |
| ICAP_DATA_BOT10 | input | TCELL44:IMUX.IMUX.10 |
| ICAP_DATA_BOT11 | input | TCELL44:IMUX.IMUX.11 |
| ICAP_DATA_BOT12 | input | TCELL44:IMUX.IMUX.12 |
| ICAP_DATA_BOT13 | input | TCELL44:IMUX.IMUX.13 |
| ICAP_DATA_BOT14 | input | TCELL44:IMUX.IMUX.14 |
| ICAP_DATA_BOT15 | input | TCELL44:IMUX.IMUX.15 |
| ICAP_DATA_BOT16 | input | TCELL45:IMUX.IMUX.0 |
| ICAP_DATA_BOT17 | input | TCELL45:IMUX.IMUX.1 |
| ICAP_DATA_BOT18 | input | TCELL45:IMUX.IMUX.2 |
| ICAP_DATA_BOT19 | input | TCELL45:IMUX.IMUX.3 |
| ICAP_DATA_BOT2 | input | TCELL44:IMUX.IMUX.2 |
| ICAP_DATA_BOT20 | input | TCELL45:IMUX.IMUX.4 |
| ICAP_DATA_BOT21 | input | TCELL45:IMUX.IMUX.5 |
| ICAP_DATA_BOT22 | input | TCELL45:IMUX.IMUX.6 |
| ICAP_DATA_BOT23 | input | TCELL45:IMUX.IMUX.7 |
| ICAP_DATA_BOT24 | input | TCELL45:IMUX.IMUX.8 |
| ICAP_DATA_BOT25 | input | TCELL45:IMUX.IMUX.9 |
| ICAP_DATA_BOT26 | input | TCELL45:IMUX.IMUX.10 |
| ICAP_DATA_BOT27 | input | TCELL45:IMUX.IMUX.11 |
| ICAP_DATA_BOT28 | input | TCELL45:IMUX.IMUX.12 |
| ICAP_DATA_BOT29 | input | TCELL45:IMUX.IMUX.13 |
| ICAP_DATA_BOT3 | input | TCELL44:IMUX.IMUX.3 |
| ICAP_DATA_BOT30 | input | TCELL45:IMUX.IMUX.14 |
| ICAP_DATA_BOT31 | input | TCELL45:IMUX.IMUX.15 |
| ICAP_DATA_BOT4 | input | TCELL44:IMUX.IMUX.4 |
| ICAP_DATA_BOT5 | input | TCELL44:IMUX.IMUX.5 |
| ICAP_DATA_BOT6 | input | TCELL44:IMUX.IMUX.6 |
| ICAP_DATA_BOT7 | input | TCELL44:IMUX.IMUX.7 |
| ICAP_DATA_BOT8 | input | TCELL44:IMUX.IMUX.8 |
| ICAP_DATA_BOT9 | input | TCELL44:IMUX.IMUX.9 |
| ICAP_DATA_TOP0 | input | TCELL55:IMUX.IMUX.0 |
| ICAP_DATA_TOP1 | input | TCELL55:IMUX.IMUX.1 |
| ICAP_DATA_TOP10 | input | TCELL55:IMUX.IMUX.10 |
| ICAP_DATA_TOP11 | input | TCELL55:IMUX.IMUX.11 |
| ICAP_DATA_TOP12 | input | TCELL55:IMUX.IMUX.12 |
| ICAP_DATA_TOP13 | input | TCELL55:IMUX.IMUX.13 |
| ICAP_DATA_TOP14 | input | TCELL55:IMUX.IMUX.14 |
| ICAP_DATA_TOP15 | input | TCELL55:IMUX.IMUX.15 |
| ICAP_DATA_TOP16 | input | TCELL56:IMUX.IMUX.0 |
| ICAP_DATA_TOP17 | input | TCELL56:IMUX.IMUX.1 |
| ICAP_DATA_TOP18 | input | TCELL56:IMUX.IMUX.2 |
| ICAP_DATA_TOP19 | input | TCELL56:IMUX.IMUX.3 |
| ICAP_DATA_TOP2 | input | TCELL55:IMUX.IMUX.2 |
| ICAP_DATA_TOP20 | input | TCELL56:IMUX.IMUX.4 |
| ICAP_DATA_TOP21 | input | TCELL56:IMUX.IMUX.5 |
| ICAP_DATA_TOP22 | input | TCELL56:IMUX.IMUX.6 |
| ICAP_DATA_TOP23 | input | TCELL56:IMUX.IMUX.7 |
| ICAP_DATA_TOP24 | input | TCELL56:IMUX.IMUX.8 |
| ICAP_DATA_TOP25 | input | TCELL56:IMUX.IMUX.9 |
| ICAP_DATA_TOP26 | input | TCELL56:IMUX.IMUX.10 |
| ICAP_DATA_TOP27 | input | TCELL56:IMUX.IMUX.11 |
| ICAP_DATA_TOP28 | input | TCELL56:IMUX.IMUX.12 |
| ICAP_DATA_TOP29 | input | TCELL56:IMUX.IMUX.13 |
| ICAP_DATA_TOP3 | input | TCELL55:IMUX.IMUX.3 |
| ICAP_DATA_TOP30 | input | TCELL56:IMUX.IMUX.14 |
| ICAP_DATA_TOP31 | input | TCELL56:IMUX.IMUX.15 |
| ICAP_DATA_TOP4 | input | TCELL55:IMUX.IMUX.4 |
| ICAP_DATA_TOP5 | input | TCELL55:IMUX.IMUX.5 |
| ICAP_DATA_TOP6 | input | TCELL55:IMUX.IMUX.6 |
| ICAP_DATA_TOP7 | input | TCELL55:IMUX.IMUX.7 |
| ICAP_DATA_TOP8 | input | TCELL55:IMUX.IMUX.8 |
| ICAP_DATA_TOP9 | input | TCELL55:IMUX.IMUX.9 |
| ICAP_OUT_BOT0 | output | TCELL44:OUT.0 |
| ICAP_OUT_BOT1 | output | TCELL44:OUT.2 |
| ICAP_OUT_BOT10 | output | TCELL44:OUT.20 |
| ICAP_OUT_BOT11 | output | TCELL44:OUT.22 |
| ICAP_OUT_BOT12 | output | TCELL44:OUT.24 |
| ICAP_OUT_BOT13 | output | TCELL44:OUT.26 |
| ICAP_OUT_BOT14 | output | TCELL44:OUT.28 |
| ICAP_OUT_BOT15 | output | TCELL44:OUT.30 |
| ICAP_OUT_BOT16 | output | TCELL45:OUT.0 |
| ICAP_OUT_BOT17 | output | TCELL45:OUT.2 |
| ICAP_OUT_BOT18 | output | TCELL45:OUT.4 |
| ICAP_OUT_BOT19 | output | TCELL45:OUT.6 |
| ICAP_OUT_BOT2 | output | TCELL44:OUT.4 |
| ICAP_OUT_BOT20 | output | TCELL45:OUT.8 |
| ICAP_OUT_BOT21 | output | TCELL45:OUT.10 |
| ICAP_OUT_BOT22 | output | TCELL45:OUT.12 |
| ICAP_OUT_BOT23 | output | TCELL45:OUT.14 |
| ICAP_OUT_BOT24 | output | TCELL45:OUT.16 |
| ICAP_OUT_BOT25 | output | TCELL45:OUT.18 |
| ICAP_OUT_BOT26 | output | TCELL45:OUT.20 |
| ICAP_OUT_BOT27 | output | TCELL45:OUT.22 |
| ICAP_OUT_BOT28 | output | TCELL45:OUT.24 |
| ICAP_OUT_BOT29 | output | TCELL45:OUT.26 |
| ICAP_OUT_BOT3 | output | TCELL44:OUT.6 |
| ICAP_OUT_BOT30 | output | TCELL45:OUT.28 |
| ICAP_OUT_BOT31 | output | TCELL45:OUT.30 |
| ICAP_OUT_BOT4 | output | TCELL44:OUT.8 |
| ICAP_OUT_BOT5 | output | TCELL44:OUT.10 |
| ICAP_OUT_BOT6 | output | TCELL44:OUT.12 |
| ICAP_OUT_BOT7 | output | TCELL44:OUT.14 |
| ICAP_OUT_BOT8 | output | TCELL44:OUT.16 |
| ICAP_OUT_BOT9 | output | TCELL44:OUT.18 |
| ICAP_OUT_TOP0 | output | TCELL55:OUT.0 |
| ICAP_OUT_TOP1 | output | TCELL55:OUT.2 |
| ICAP_OUT_TOP10 | output | TCELL55:OUT.20 |
| ICAP_OUT_TOP11 | output | TCELL55:OUT.22 |
| ICAP_OUT_TOP12 | output | TCELL55:OUT.24 |
| ICAP_OUT_TOP13 | output | TCELL55:OUT.26 |
| ICAP_OUT_TOP14 | output | TCELL55:OUT.28 |
| ICAP_OUT_TOP15 | output | TCELL55:OUT.30 |
| ICAP_OUT_TOP16 | output | TCELL56:OUT.0 |
| ICAP_OUT_TOP17 | output | TCELL56:OUT.2 |
| ICAP_OUT_TOP18 | output | TCELL56:OUT.4 |
| ICAP_OUT_TOP19 | output | TCELL56:OUT.6 |
| ICAP_OUT_TOP2 | output | TCELL55:OUT.4 |
| ICAP_OUT_TOP20 | output | TCELL56:OUT.8 |
| ICAP_OUT_TOP21 | output | TCELL56:OUT.10 |
| ICAP_OUT_TOP22 | output | TCELL56:OUT.12 |
| ICAP_OUT_TOP23 | output | TCELL56:OUT.14 |
| ICAP_OUT_TOP24 | output | TCELL56:OUT.16 |
| ICAP_OUT_TOP25 | output | TCELL56:OUT.18 |
| ICAP_OUT_TOP26 | output | TCELL56:OUT.20 |
| ICAP_OUT_TOP27 | output | TCELL56:OUT.22 |
| ICAP_OUT_TOP28 | output | TCELL56:OUT.24 |
| ICAP_OUT_TOP29 | output | TCELL56:OUT.26 |
| ICAP_OUT_TOP3 | output | TCELL55:OUT.6 |
| ICAP_OUT_TOP30 | output | TCELL56:OUT.28 |
| ICAP_OUT_TOP31 | output | TCELL56:OUT.30 |
| ICAP_OUT_TOP4 | output | TCELL55:OUT.8 |
| ICAP_OUT_TOP5 | output | TCELL55:OUT.10 |
| ICAP_OUT_TOP6 | output | TCELL55:OUT.12 |
| ICAP_OUT_TOP7 | output | TCELL55:OUT.14 |
| ICAP_OUT_TOP8 | output | TCELL55:OUT.16 |
| ICAP_OUT_TOP9 | output | TCELL55:OUT.18 |
| ICAP_PR_DONE_BOT | output | TCELL43:OUT.0 |
| ICAP_PR_DONE_TOP | output | TCELL54:OUT.0 |
| ICAP_PR_ERROR_BOT | output | TCELL43:OUT.2 |
| ICAP_PR_ERROR_TOP | output | TCELL54:OUT.2 |
| ICAP_RDWR_B_BOT | input | TCELL43:IMUX.IMUX.0 |
| ICAP_RDWR_B_TOP | input | TCELL54:IMUX.IMUX.0 |
| IOX_CCLK | output | TCELL50:OUT.0 |
| IOX_CFGDATA0 | output | TCELL48:OUT.0 |
| IOX_CFGDATA1 | output | TCELL48:OUT.2 |
| IOX_CFGDATA10 | output | TCELL48:OUT.20 |
| IOX_CFGDATA11 | output | TCELL48:OUT.22 |
| IOX_CFGDATA12 | output | TCELL48:OUT.24 |
| IOX_CFGDATA13 | output | TCELL48:OUT.26 |
| IOX_CFGDATA14 | output | TCELL48:OUT.28 |
| IOX_CFGDATA15 | output | TCELL48:OUT.30 |
| IOX_CFGDATA16 | output | TCELL49:OUT.0 |
| IOX_CFGDATA17 | output | TCELL49:OUT.2 |
| IOX_CFGDATA18 | output | TCELL49:OUT.4 |
| IOX_CFGDATA19 | output | TCELL49:OUT.6 |
| IOX_CFGDATA2 | output | TCELL48:OUT.4 |
| IOX_CFGDATA20 | output | TCELL49:OUT.8 |
| IOX_CFGDATA21 | output | TCELL49:OUT.10 |
| IOX_CFGDATA22 | output | TCELL49:OUT.12 |
| IOX_CFGDATA23 | output | TCELL49:OUT.14 |
| IOX_CFGDATA24 | output | TCELL49:OUT.16 |
| IOX_CFGDATA25 | output | TCELL49:OUT.18 |
| IOX_CFGDATA26 | output | TCELL49:OUT.20 |
| IOX_CFGDATA27 | output | TCELL49:OUT.22 |
| IOX_CFGDATA28 | output | TCELL49:OUT.24 |
| IOX_CFGDATA29 | output | TCELL49:OUT.26 |
| IOX_CFGDATA3 | output | TCELL48:OUT.6 |
| IOX_CFGDATA30 | output | TCELL49:OUT.28 |
| IOX_CFGDATA31 | output | TCELL49:OUT.30 |
| IOX_CFGDATA4 | output | TCELL48:OUT.8 |
| IOX_CFGDATA5 | output | TCELL48:OUT.10 |
| IOX_CFGDATA6 | output | TCELL48:OUT.12 |
| IOX_CFGDATA7 | output | TCELL48:OUT.14 |
| IOX_CFGDATA8 | output | TCELL48:OUT.16 |
| IOX_CFGDATA9 | output | TCELL48:OUT.18 |
| IOX_CFGMASTER | output | TCELL50:OUT.2 |
| IOX_INITBI | output | TCELL50:OUT.6 |
| IOX_INITBO | input | TCELL48:IMUX.IMUX.1 |
| IOX_MODE0 | output | TCELL50:OUT.12 |
| IOX_MODE1 | output | TCELL50:OUT.14 |
| IOX_MODE2 | output | TCELL50:OUT.16 |
| IOX_PUDCB | output | TCELL50:OUT.8 |
| IOX_RDWRB | output | TCELL50:OUT.10 |
| IOX_TDO | input | TCELL48:IMUX.IMUX.0 |
| IOX_VGG_COMP_OUT | output | TCELL50:OUT.4 |
| KEY_CLEAR | input | TCELL47:IMUX.IMUX.0 |
| PROG_ACK | input | TCELL47:IMUX.IMUX.1 |
| PROG_REQ | output | TCELL47:OUT.8 |
| RBCRC_ERROR | output | TCELL51:OUT.20 |
| START_CFG_CLK | output | TCELL47:OUT.14 |
| START_CFG_MCLK | output | TCELL47:OUT.12 |
| USR_ACCESS_CLK | output | TCELL57:OUT.2 |
| USR_ACCESS_DATA0 | output | TCELL58:OUT.0 |
| USR_ACCESS_DATA1 | output | TCELL58:OUT.2 |
| USR_ACCESS_DATA10 | output | TCELL58:OUT.20 |
| USR_ACCESS_DATA11 | output | TCELL58:OUT.22 |
| USR_ACCESS_DATA12 | output | TCELL58:OUT.24 |
| USR_ACCESS_DATA13 | output | TCELL58:OUT.26 |
| USR_ACCESS_DATA14 | output | TCELL58:OUT.28 |
| USR_ACCESS_DATA15 | output | TCELL58:OUT.30 |
| USR_ACCESS_DATA16 | output | TCELL59:OUT.0 |
| USR_ACCESS_DATA17 | output | TCELL59:OUT.2 |
| USR_ACCESS_DATA18 | output | TCELL59:OUT.4 |
| USR_ACCESS_DATA19 | output | TCELL59:OUT.6 |
| USR_ACCESS_DATA2 | output | TCELL58:OUT.4 |
| USR_ACCESS_DATA20 | output | TCELL59:OUT.8 |
| USR_ACCESS_DATA21 | output | TCELL59:OUT.10 |
| USR_ACCESS_DATA22 | output | TCELL59:OUT.12 |
| USR_ACCESS_DATA23 | output | TCELL59:OUT.14 |
| USR_ACCESS_DATA24 | output | TCELL59:OUT.16 |
| USR_ACCESS_DATA25 | output | TCELL59:OUT.18 |
| USR_ACCESS_DATA26 | output | TCELL59:OUT.20 |
| USR_ACCESS_DATA27 | output | TCELL59:OUT.22 |
| USR_ACCESS_DATA28 | output | TCELL59:OUT.24 |
| USR_ACCESS_DATA29 | output | TCELL59:OUT.26 |
| USR_ACCESS_DATA3 | output | TCELL58:OUT.6 |
| USR_ACCESS_DATA30 | output | TCELL59:OUT.28 |
| USR_ACCESS_DATA31 | output | TCELL59:OUT.30 |
| USR_ACCESS_DATA4 | output | TCELL58:OUT.8 |
| USR_ACCESS_DATA5 | output | TCELL58:OUT.10 |
| USR_ACCESS_DATA6 | output | TCELL58:OUT.12 |
| USR_ACCESS_DATA7 | output | TCELL58:OUT.14 |
| USR_ACCESS_DATA8 | output | TCELL58:OUT.16 |
| USR_ACCESS_DATA9 | output | TCELL58:OUT.18 |
| USR_ACCESS_VALID | output | TCELL57:OUT.0 |
| USR_CCLK_O | input | TCELL47:IMUX.CTRL.0 |
| USR_CCLK_TS | input | TCELL47:IMUX.IMUX.2 |
| USR_DNA_CLK | input | TCELL42:IMUX.CTRL.0 |
| USR_DNA_DIN | input | TCELL42:IMUX.IMUX.0 |
| USR_DNA_OUT | output | TCELL42:OUT.0 |
| USR_DNA_READ | input | TCELL42:IMUX.IMUX.1 |
| USR_DNA_SHIFT | input | TCELL42:IMUX.IMUX.2 |
| USR_DONE_O | input | TCELL47:IMUX.IMUX.3 |
| USR_DONE_TS | input | TCELL47:IMUX.IMUX.4 |
| USR_D_O_CFGIO0 | input | TCELL47:IMUX.IMUX.9 |
| USR_D_O_CFGIO1 | input | TCELL47:IMUX.IMUX.10 |
| USR_D_O_CFGIO2 | input | TCELL47:IMUX.IMUX.11 |
| USR_D_O_CFGIO3 | input | TCELL47:IMUX.IMUX.12 |
| USR_D_PIN_CFGIO0 | output | TCELL47:OUT.0 |
| USR_D_PIN_CFGIO1 | output | TCELL47:OUT.2 |
| USR_D_PIN_CFGIO2 | output | TCELL47:OUT.4 |
| USR_D_PIN_CFGIO3 | output | TCELL47:OUT.6 |
| USR_D_TS_CFGIO0 | input | TCELL47:IMUX.IMUX.13 |
| USR_D_TS_CFGIO1 | input | TCELL47:IMUX.IMUX.14 |
| USR_D_TS_CFGIO2 | input | TCELL47:IMUX.IMUX.15 |
| USR_D_TS_CFGIO3 | input | TCELL47:IMUX.IMUX.16 |
| USR_EFUSE0 | output | TCELL46:OUT.0 |
| USR_EFUSE1 | output | TCELL46:OUT.2 |
| USR_EFUSE10 | output | TCELL46:OUT.20 |
| USR_EFUSE11 | output | TCELL46:OUT.22 |
| USR_EFUSE12 | output | TCELL46:OUT.24 |
| USR_EFUSE13 | output | TCELL46:OUT.26 |
| USR_EFUSE14 | output | TCELL46:OUT.28 |
| USR_EFUSE15 | output | TCELL46:OUT.30 |
| USR_EFUSE16 | output | TCELL41:OUT.0 |
| USR_EFUSE17 | output | TCELL41:OUT.2 |
| USR_EFUSE18 | output | TCELL41:OUT.4 |
| USR_EFUSE19 | output | TCELL41:OUT.6 |
| USR_EFUSE2 | output | TCELL46:OUT.4 |
| USR_EFUSE20 | output | TCELL41:OUT.8 |
| USR_EFUSE21 | output | TCELL41:OUT.10 |
| USR_EFUSE22 | output | TCELL41:OUT.12 |
| USR_EFUSE23 | output | TCELL41:OUT.14 |
| USR_EFUSE24 | output | TCELL41:OUT.16 |
| USR_EFUSE25 | output | TCELL41:OUT.18 |
| USR_EFUSE26 | output | TCELL41:OUT.20 |
| USR_EFUSE27 | output | TCELL41:OUT.22 |
| USR_EFUSE28 | output | TCELL41:OUT.24 |
| USR_EFUSE29 | output | TCELL41:OUT.26 |
| USR_EFUSE3 | output | TCELL46:OUT.6 |
| USR_EFUSE30 | output | TCELL41:OUT.28 |
| USR_EFUSE31 | output | TCELL41:OUT.30 |
| USR_EFUSE4 | output | TCELL46:OUT.8 |
| USR_EFUSE5 | output | TCELL46:OUT.10 |
| USR_EFUSE6 | output | TCELL46:OUT.12 |
| USR_EFUSE7 | output | TCELL46:OUT.14 |
| USR_EFUSE8 | output | TCELL46:OUT.16 |
| USR_EFUSE9 | output | TCELL46:OUT.18 |
| USR_FCS_B_O | input | TCELL47:IMUX.IMUX.7 |
| USR_FCS_B_TS | input | TCELL47:IMUX.IMUX.8 |
| USR_GSR | input | TCELL47:IMUX.IMUX.5 |
| USR_GTS | input | TCELL47:IMUX.IMUX.6 |
| USR_TCK | input | TCELL43:IMUX.CTRL.1 |
| USR_TDI | input | TCELL43:IMUX.IMUX.6 |
| USR_TDO | output | TCELL43:OUT.18 |
| USR_TMS | input | TCELL43:IMUX.IMUX.5 |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL41:OUT.0 | CFG.USR_EFUSE16 |
| TCELL41:OUT.2 | CFG.USR_EFUSE17 |
| TCELL41:OUT.4 | CFG.USR_EFUSE18 |
| TCELL41:OUT.6 | CFG.USR_EFUSE19 |
| TCELL41:OUT.8 | CFG.USR_EFUSE20 |
| TCELL41:OUT.10 | CFG.USR_EFUSE21 |
| TCELL41:OUT.12 | CFG.USR_EFUSE22 |
| TCELL41:OUT.14 | CFG.USR_EFUSE23 |
| TCELL41:OUT.16 | CFG.USR_EFUSE24 |
| TCELL41:OUT.18 | CFG.USR_EFUSE25 |
| TCELL41:OUT.20 | CFG.USR_EFUSE26 |
| TCELL41:OUT.22 | CFG.USR_EFUSE27 |
| TCELL41:OUT.24 | CFG.USR_EFUSE28 |
| TCELL41:OUT.26 | CFG.USR_EFUSE29 |
| TCELL41:OUT.28 | CFG.USR_EFUSE30 |
| TCELL41:OUT.30 | CFG.USR_EFUSE31 |
| TCELL42:OUT.0 | CFG.USR_DNA_OUT |
| TCELL42:OUT.2 | CFG.DCI_LOCK |
| TCELL42:OUT.4 | CFG.BSCAN_CDR1 |
| TCELL42:OUT.6 | CFG.BSCAN_CDR2 |
| TCELL42:OUT.8 | CFG.BSCAN_CLKDR1 |
| TCELL42:OUT.10 | CFG.BSCAN_CLKDR2 |
| TCELL42:OUT.12 | CFG.BSCAN_RTI1 |
| TCELL42:OUT.14 | CFG.BSCAN_RTI2 |
| TCELL42:OUT.16 | CFG.BSCAN_SDR1 |
| TCELL42:OUT.18 | CFG.BSCAN_SDR2 |
| TCELL42:OUT.20 | CFG.BSCAN_SEL1 |
| TCELL42:OUT.22 | CFG.BSCAN_SEL2 |
| TCELL42:OUT.24 | CFG.BSCAN_TLR1 |
| TCELL42:OUT.26 | CFG.BSCAN_TLR2 |
| TCELL42:OUT.28 | CFG.BSCAN_UDR1 |
| TCELL42:OUT.30 | CFG.BSCAN_UDR2 |
| TCELL42:IMUX.CTRL.0 | CFG.USR_DNA_CLK |
| TCELL42:IMUX.IMUX.0 | CFG.USR_DNA_DIN |
| TCELL42:IMUX.IMUX.1 | CFG.USR_DNA_READ |
| TCELL42:IMUX.IMUX.2 | CFG.USR_DNA_SHIFT |
| TCELL42:IMUX.IMUX.3 | CFG.DCI_USR_RESET_IN |
| TCELL43:OUT.0 | CFG.ICAP_PR_DONE_BOT |
| TCELL43:OUT.2 | CFG.ICAP_PR_ERROR_BOT |
| TCELL43:OUT.4 | CFG.ICAP_AVAIL_BOT |
| TCELL43:OUT.6 | CFG.BSCAN_TCK1 |
| TCELL43:OUT.8 | CFG.BSCAN_TCK2 |
| TCELL43:OUT.10 | CFG.BSCAN_TMS1 |
| TCELL43:OUT.12 | CFG.BSCAN_TMS2 |
| TCELL43:OUT.14 | CFG.BSCAN_TDI1 |
| TCELL43:OUT.16 | CFG.BSCAN_TDI2 |
| TCELL43:OUT.18 | CFG.USR_TDO |
| TCELL43:IMUX.CTRL.1 | CFG.USR_TCK |
| TCELL43:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_BOT |
| TCELL43:IMUX.IMUX.1 | CFG.ICAP_CS_B_BOT |
| TCELL43:IMUX.IMUX.2 | CFG.BSCAN_TDO1 |
| TCELL43:IMUX.IMUX.3 | CFG.BSCAN_TDO2 |
| TCELL43:IMUX.IMUX.5 | CFG.USR_TMS |
| TCELL43:IMUX.IMUX.6 | CFG.USR_TDI |
| TCELL44:OUT.0 | CFG.ICAP_OUT_BOT0 |
| TCELL44:OUT.2 | CFG.ICAP_OUT_BOT1 |
| TCELL44:OUT.4 | CFG.ICAP_OUT_BOT2 |
| TCELL44:OUT.6 | CFG.ICAP_OUT_BOT3 |
| TCELL44:OUT.8 | CFG.ICAP_OUT_BOT4 |
| TCELL44:OUT.10 | CFG.ICAP_OUT_BOT5 |
| TCELL44:OUT.12 | CFG.ICAP_OUT_BOT6 |
| TCELL44:OUT.14 | CFG.ICAP_OUT_BOT7 |
| TCELL44:OUT.16 | CFG.ICAP_OUT_BOT8 |
| TCELL44:OUT.18 | CFG.ICAP_OUT_BOT9 |
| TCELL44:OUT.20 | CFG.ICAP_OUT_BOT10 |
| TCELL44:OUT.22 | CFG.ICAP_OUT_BOT11 |
| TCELL44:OUT.24 | CFG.ICAP_OUT_BOT12 |
| TCELL44:OUT.26 | CFG.ICAP_OUT_BOT13 |
| TCELL44:OUT.28 | CFG.ICAP_OUT_BOT14 |
| TCELL44:OUT.30 | CFG.ICAP_OUT_BOT15 |
| TCELL44:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT0 |
| TCELL44:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT1 |
| TCELL44:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT2 |
| TCELL44:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT3 |
| TCELL44:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT4 |
| TCELL44:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT5 |
| TCELL44:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT6 |
| TCELL44:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT7 |
| TCELL44:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT8 |
| TCELL44:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT9 |
| TCELL44:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT10 |
| TCELL44:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT11 |
| TCELL44:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT12 |
| TCELL44:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT13 |
| TCELL44:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT14 |
| TCELL44:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT15 |
| TCELL45:OUT.0 | CFG.ICAP_OUT_BOT16 |
| TCELL45:OUT.2 | CFG.ICAP_OUT_BOT17 |
| TCELL45:OUT.4 | CFG.ICAP_OUT_BOT18 |
| TCELL45:OUT.6 | CFG.ICAP_OUT_BOT19 |
| TCELL45:OUT.8 | CFG.ICAP_OUT_BOT20 |
| TCELL45:OUT.10 | CFG.ICAP_OUT_BOT21 |
| TCELL45:OUT.12 | CFG.ICAP_OUT_BOT22 |
| TCELL45:OUT.14 | CFG.ICAP_OUT_BOT23 |
| TCELL45:OUT.16 | CFG.ICAP_OUT_BOT24 |
| TCELL45:OUT.18 | CFG.ICAP_OUT_BOT25 |
| TCELL45:OUT.20 | CFG.ICAP_OUT_BOT26 |
| TCELL45:OUT.22 | CFG.ICAP_OUT_BOT27 |
| TCELL45:OUT.24 | CFG.ICAP_OUT_BOT28 |
| TCELL45:OUT.26 | CFG.ICAP_OUT_BOT29 |
| TCELL45:OUT.28 | CFG.ICAP_OUT_BOT30 |
| TCELL45:OUT.30 | CFG.ICAP_OUT_BOT31 |
| TCELL45:IMUX.CTRL.0 | CFG.ICAP_CLK_BOT |
| TCELL45:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT16 |
| TCELL45:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT17 |
| TCELL45:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT18 |
| TCELL45:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT19 |
| TCELL45:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT20 |
| TCELL45:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT21 |
| TCELL45:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT22 |
| TCELL45:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT23 |
| TCELL45:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT24 |
| TCELL45:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT25 |
| TCELL45:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT26 |
| TCELL45:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT27 |
| TCELL45:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT28 |
| TCELL45:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT29 |
| TCELL45:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT30 |
| TCELL45:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT31 |
| TCELL46:OUT.0 | CFG.USR_EFUSE0 |
| TCELL46:OUT.2 | CFG.USR_EFUSE1 |
| TCELL46:OUT.4 | CFG.USR_EFUSE2 |
| TCELL46:OUT.6 | CFG.USR_EFUSE3 |
| TCELL46:OUT.8 | CFG.USR_EFUSE4 |
| TCELL46:OUT.10 | CFG.USR_EFUSE5 |
| TCELL46:OUT.12 | CFG.USR_EFUSE6 |
| TCELL46:OUT.14 | CFG.USR_EFUSE7 |
| TCELL46:OUT.16 | CFG.USR_EFUSE8 |
| TCELL46:OUT.18 | CFG.USR_EFUSE9 |
| TCELL46:OUT.20 | CFG.USR_EFUSE10 |
| TCELL46:OUT.22 | CFG.USR_EFUSE11 |
| TCELL46:OUT.24 | CFG.USR_EFUSE12 |
| TCELL46:OUT.26 | CFG.USR_EFUSE13 |
| TCELL46:OUT.28 | CFG.USR_EFUSE14 |
| TCELL46:OUT.30 | CFG.USR_EFUSE15 |
| TCELL47:OUT.0 | CFG.USR_D_PIN_CFGIO0 |
| TCELL47:OUT.2 | CFG.USR_D_PIN_CFGIO1 |
| TCELL47:OUT.4 | CFG.USR_D_PIN_CFGIO2 |
| TCELL47:OUT.6 | CFG.USR_D_PIN_CFGIO3 |
| TCELL47:OUT.8 | CFG.PROG_REQ |
| TCELL47:OUT.10 | CFG.EOS |
| TCELL47:OUT.12 | CFG.START_CFG_MCLK |
| TCELL47:OUT.14 | CFG.START_CFG_CLK |
| TCELL47:IMUX.CTRL.0 | CFG.USR_CCLK_O |
| TCELL47:IMUX.IMUX.0 | CFG.KEY_CLEAR |
| TCELL47:IMUX.IMUX.1 | CFG.PROG_ACK |
| TCELL47:IMUX.IMUX.2 | CFG.USR_CCLK_TS |
| TCELL47:IMUX.IMUX.3 | CFG.USR_DONE_O |
| TCELL47:IMUX.IMUX.4 | CFG.USR_DONE_TS |
| TCELL47:IMUX.IMUX.5 | CFG.USR_GSR |
| TCELL47:IMUX.IMUX.6 | CFG.USR_GTS |
| TCELL47:IMUX.IMUX.7 | CFG.USR_FCS_B_O |
| TCELL47:IMUX.IMUX.8 | CFG.USR_FCS_B_TS |
| TCELL47:IMUX.IMUX.9 | CFG.USR_D_O_CFGIO0 |
| TCELL47:IMUX.IMUX.10 | CFG.USR_D_O_CFGIO1 |
| TCELL47:IMUX.IMUX.11 | CFG.USR_D_O_CFGIO2 |
| TCELL47:IMUX.IMUX.12 | CFG.USR_D_O_CFGIO3 |
| TCELL47:IMUX.IMUX.13 | CFG.USR_D_TS_CFGIO0 |
| TCELL47:IMUX.IMUX.14 | CFG.USR_D_TS_CFGIO1 |
| TCELL47:IMUX.IMUX.15 | CFG.USR_D_TS_CFGIO2 |
| TCELL47:IMUX.IMUX.16 | CFG.USR_D_TS_CFGIO3 |
| TCELL48:OUT.0 | CFG.IOX_CFGDATA0 |
| TCELL48:OUT.2 | CFG.IOX_CFGDATA1 |
| TCELL48:OUT.4 | CFG.IOX_CFGDATA2 |
| TCELL48:OUT.6 | CFG.IOX_CFGDATA3 |
| TCELL48:OUT.8 | CFG.IOX_CFGDATA4 |
| TCELL48:OUT.10 | CFG.IOX_CFGDATA5 |
| TCELL48:OUT.12 | CFG.IOX_CFGDATA6 |
| TCELL48:OUT.14 | CFG.IOX_CFGDATA7 |
| TCELL48:OUT.16 | CFG.IOX_CFGDATA8 |
| TCELL48:OUT.18 | CFG.IOX_CFGDATA9 |
| TCELL48:OUT.20 | CFG.IOX_CFGDATA10 |
| TCELL48:OUT.22 | CFG.IOX_CFGDATA11 |
| TCELL48:OUT.24 | CFG.IOX_CFGDATA12 |
| TCELL48:OUT.26 | CFG.IOX_CFGDATA13 |
| TCELL48:OUT.28 | CFG.IOX_CFGDATA14 |
| TCELL48:OUT.30 | CFG.IOX_CFGDATA15 |
| TCELL48:IMUX.IMUX.0 | CFG.IOX_TDO |
| TCELL48:IMUX.IMUX.1 | CFG.IOX_INITBO |
| TCELL49:OUT.0 | CFG.IOX_CFGDATA16 |
| TCELL49:OUT.2 | CFG.IOX_CFGDATA17 |
| TCELL49:OUT.4 | CFG.IOX_CFGDATA18 |
| TCELL49:OUT.6 | CFG.IOX_CFGDATA19 |
| TCELL49:OUT.8 | CFG.IOX_CFGDATA20 |
| TCELL49:OUT.10 | CFG.IOX_CFGDATA21 |
| TCELL49:OUT.12 | CFG.IOX_CFGDATA22 |
| TCELL49:OUT.14 | CFG.IOX_CFGDATA23 |
| TCELL49:OUT.16 | CFG.IOX_CFGDATA24 |
| TCELL49:OUT.18 | CFG.IOX_CFGDATA25 |
| TCELL49:OUT.20 | CFG.IOX_CFGDATA26 |
| TCELL49:OUT.22 | CFG.IOX_CFGDATA27 |
| TCELL49:OUT.24 | CFG.IOX_CFGDATA28 |
| TCELL49:OUT.26 | CFG.IOX_CFGDATA29 |
| TCELL49:OUT.28 | CFG.IOX_CFGDATA30 |
| TCELL49:OUT.30 | CFG.IOX_CFGDATA31 |
| TCELL50:OUT.0 | CFG.IOX_CCLK |
| TCELL50:OUT.2 | CFG.IOX_CFGMASTER |
| TCELL50:OUT.4 | CFG.IOX_VGG_COMP_OUT |
| TCELL50:OUT.6 | CFG.IOX_INITBI |
| TCELL50:OUT.8 | CFG.IOX_PUDCB |
| TCELL50:OUT.10 | CFG.IOX_RDWRB |
| TCELL50:OUT.12 | CFG.IOX_MODE0 |
| TCELL50:OUT.14 | CFG.IOX_MODE1 |
| TCELL50:OUT.16 | CFG.IOX_MODE2 |
| TCELL51:OUT.0 | CFG.ECC_FAR16 |
| TCELL51:OUT.2 | CFG.ECC_FAR17 |
| TCELL51:OUT.4 | CFG.ECC_FAR18 |
| TCELL51:OUT.6 | CFG.ECC_FAR19 |
| TCELL51:OUT.8 | CFG.ECC_FAR20 |
| TCELL51:OUT.10 | CFG.ECC_FAR21 |
| TCELL51:OUT.12 | CFG.ECC_FAR22 |
| TCELL51:OUT.14 | CFG.ECC_FAR23 |
| TCELL51:OUT.16 | CFG.ECC_FAR24 |
| TCELL51:OUT.18 | CFG.ECC_FAR25 |
| TCELL51:OUT.20 | CFG.RBCRC_ERROR |
| TCELL51:OUT.22 | CFG.ECC_ERROR_NOTSINGLE |
| TCELL51:OUT.24 | CFG.ECC_ERROR_SINGLE |
| TCELL51:OUT.26 | CFG.ECC_END_OF_FRAME |
| TCELL51:OUT.28 | CFG.ECC_END_OF_SCAN |
| TCELL51:IMUX.IMUX.15 | CFG.ECC_FAR_SEL0 |
| TCELL51:IMUX.IMUX.16 | CFG.ECC_FAR_SEL1 |
| TCELL52:OUT.0 | CFG.ECC_FAR0 |
| TCELL52:OUT.2 | CFG.ECC_FAR1 |
| TCELL52:OUT.4 | CFG.ECC_FAR2 |
| TCELL52:OUT.6 | CFG.ECC_FAR3 |
| TCELL52:OUT.8 | CFG.ECC_FAR4 |
| TCELL52:OUT.10 | CFG.ECC_FAR5 |
| TCELL52:OUT.12 | CFG.ECC_FAR6 |
| TCELL52:OUT.14 | CFG.ECC_FAR7 |
| TCELL52:OUT.16 | CFG.ECC_FAR8 |
| TCELL52:OUT.18 | CFG.ECC_FAR9 |
| TCELL52:OUT.20 | CFG.ECC_FAR10 |
| TCELL52:OUT.22 | CFG.ECC_FAR11 |
| TCELL52:OUT.24 | CFG.ECC_FAR12 |
| TCELL52:OUT.26 | CFG.ECC_FAR13 |
| TCELL52:OUT.28 | CFG.ECC_FAR14 |
| TCELL52:OUT.30 | CFG.ECC_FAR15 |
| TCELL52:OUT.31 | CFG.ECC_FAR26 |
| TCELL53:OUT.0 | CFG.BSCAN_SDR3 |
| TCELL53:OUT.2 | CFG.BSCAN_SDR4 |
| TCELL53:OUT.4 | CFG.BSCAN_SEL3 |
| TCELL53:OUT.6 | CFG.BSCAN_SEL4 |
| TCELL53:OUT.8 | CFG.BSCAN_TLR3 |
| TCELL53:OUT.10 | CFG.BSCAN_TLR4 |
| TCELL53:OUT.12 | CFG.BSCAN_UDR3 |
| TCELL53:OUT.14 | CFG.BSCAN_UDR4 |
| TCELL54:OUT.0 | CFG.ICAP_PR_DONE_TOP |
| TCELL54:OUT.2 | CFG.ICAP_PR_ERROR_TOP |
| TCELL54:OUT.4 | CFG.ICAP_AVAIL_TOP |
| TCELL54:OUT.6 | CFG.BSCAN_TCK3 |
| TCELL54:OUT.8 | CFG.BSCAN_TCK4 |
| TCELL54:OUT.10 | CFG.BSCAN_TMS3 |
| TCELL54:OUT.12 | CFG.BSCAN_TMS4 |
| TCELL54:OUT.14 | CFG.BSCAN_TDI3 |
| TCELL54:OUT.16 | CFG.BSCAN_TDI4 |
| TCELL54:OUT.18 | CFG.BSCAN_CDR3 |
| TCELL54:OUT.20 | CFG.BSCAN_CDR4 |
| TCELL54:OUT.22 | CFG.BSCAN_CLKDR3 |
| TCELL54:OUT.24 | CFG.BSCAN_CLKDR4 |
| TCELL54:OUT.26 | CFG.BSCAN_RTI3 |
| TCELL54:OUT.28 | CFG.BSCAN_RTI4 |
| TCELL54:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_TOP |
| TCELL54:IMUX.IMUX.1 | CFG.ICAP_CS_B_TOP |
| TCELL54:IMUX.IMUX.2 | CFG.BSCAN_TDO3 |
| TCELL54:IMUX.IMUX.3 | CFG.BSCAN_TDO4 |
| TCELL55:OUT.0 | CFG.ICAP_OUT_TOP0 |
| TCELL55:OUT.2 | CFG.ICAP_OUT_TOP1 |
| TCELL55:OUT.4 | CFG.ICAP_OUT_TOP2 |
| TCELL55:OUT.6 | CFG.ICAP_OUT_TOP3 |
| TCELL55:OUT.8 | CFG.ICAP_OUT_TOP4 |
| TCELL55:OUT.10 | CFG.ICAP_OUT_TOP5 |
| TCELL55:OUT.12 | CFG.ICAP_OUT_TOP6 |
| TCELL55:OUT.14 | CFG.ICAP_OUT_TOP7 |
| TCELL55:OUT.16 | CFG.ICAP_OUT_TOP8 |
| TCELL55:OUT.18 | CFG.ICAP_OUT_TOP9 |
| TCELL55:OUT.20 | CFG.ICAP_OUT_TOP10 |
| TCELL55:OUT.22 | CFG.ICAP_OUT_TOP11 |
| TCELL55:OUT.24 | CFG.ICAP_OUT_TOP12 |
| TCELL55:OUT.26 | CFG.ICAP_OUT_TOP13 |
| TCELL55:OUT.28 | CFG.ICAP_OUT_TOP14 |
| TCELL55:OUT.30 | CFG.ICAP_OUT_TOP15 |
| TCELL55:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP0 |
| TCELL55:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP1 |
| TCELL55:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP2 |
| TCELL55:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP3 |
| TCELL55:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP4 |
| TCELL55:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP5 |
| TCELL55:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP6 |
| TCELL55:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP7 |
| TCELL55:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP8 |
| TCELL55:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP9 |
| TCELL55:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP10 |
| TCELL55:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP11 |
| TCELL55:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP12 |
| TCELL55:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP13 |
| TCELL55:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP14 |
| TCELL55:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP15 |
| TCELL56:OUT.0 | CFG.ICAP_OUT_TOP16 |
| TCELL56:OUT.2 | CFG.ICAP_OUT_TOP17 |
| TCELL56:OUT.4 | CFG.ICAP_OUT_TOP18 |
| TCELL56:OUT.6 | CFG.ICAP_OUT_TOP19 |
| TCELL56:OUT.8 | CFG.ICAP_OUT_TOP20 |
| TCELL56:OUT.10 | CFG.ICAP_OUT_TOP21 |
| TCELL56:OUT.12 | CFG.ICAP_OUT_TOP22 |
| TCELL56:OUT.14 | CFG.ICAP_OUT_TOP23 |
| TCELL56:OUT.16 | CFG.ICAP_OUT_TOP24 |
| TCELL56:OUT.18 | CFG.ICAP_OUT_TOP25 |
| TCELL56:OUT.20 | CFG.ICAP_OUT_TOP26 |
| TCELL56:OUT.22 | CFG.ICAP_OUT_TOP27 |
| TCELL56:OUT.24 | CFG.ICAP_OUT_TOP28 |
| TCELL56:OUT.26 | CFG.ICAP_OUT_TOP29 |
| TCELL56:OUT.28 | CFG.ICAP_OUT_TOP30 |
| TCELL56:OUT.30 | CFG.ICAP_OUT_TOP31 |
| TCELL56:IMUX.CTRL.0 | CFG.ICAP_CLK_TOP |
| TCELL56:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP16 |
| TCELL56:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP17 |
| TCELL56:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP18 |
| TCELL56:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP19 |
| TCELL56:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP20 |
| TCELL56:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP21 |
| TCELL56:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP22 |
| TCELL56:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP23 |
| TCELL56:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP24 |
| TCELL56:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP25 |
| TCELL56:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP26 |
| TCELL56:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP27 |
| TCELL56:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP28 |
| TCELL56:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP29 |
| TCELL56:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP30 |
| TCELL56:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP31 |
| TCELL57:OUT.0 | CFG.USR_ACCESS_VALID |
| TCELL57:OUT.2 | CFG.USR_ACCESS_CLK |
| TCELL58:OUT.0 | CFG.USR_ACCESS_DATA0 |
| TCELL58:OUT.2 | CFG.USR_ACCESS_DATA1 |
| TCELL58:OUT.4 | CFG.USR_ACCESS_DATA2 |
| TCELL58:OUT.6 | CFG.USR_ACCESS_DATA3 |
| TCELL58:OUT.8 | CFG.USR_ACCESS_DATA4 |
| TCELL58:OUT.10 | CFG.USR_ACCESS_DATA5 |
| TCELL58:OUT.12 | CFG.USR_ACCESS_DATA6 |
| TCELL58:OUT.14 | CFG.USR_ACCESS_DATA7 |
| TCELL58:OUT.16 | CFG.USR_ACCESS_DATA8 |
| TCELL58:OUT.18 | CFG.USR_ACCESS_DATA9 |
| TCELL58:OUT.20 | CFG.USR_ACCESS_DATA10 |
| TCELL58:OUT.22 | CFG.USR_ACCESS_DATA11 |
| TCELL58:OUT.24 | CFG.USR_ACCESS_DATA12 |
| TCELL58:OUT.26 | CFG.USR_ACCESS_DATA13 |
| TCELL58:OUT.28 | CFG.USR_ACCESS_DATA14 |
| TCELL58:OUT.30 | CFG.USR_ACCESS_DATA15 |
| TCELL59:OUT.0 | CFG.USR_ACCESS_DATA16 |
| TCELL59:OUT.2 | CFG.USR_ACCESS_DATA17 |
| TCELL59:OUT.4 | CFG.USR_ACCESS_DATA18 |
| TCELL59:OUT.6 | CFG.USR_ACCESS_DATA19 |
| TCELL59:OUT.8 | CFG.USR_ACCESS_DATA20 |
| TCELL59:OUT.10 | CFG.USR_ACCESS_DATA21 |
| TCELL59:OUT.12 | CFG.USR_ACCESS_DATA22 |
| TCELL59:OUT.14 | CFG.USR_ACCESS_DATA23 |
| TCELL59:OUT.16 | CFG.USR_ACCESS_DATA24 |
| TCELL59:OUT.18 | CFG.USR_ACCESS_DATA25 |
| TCELL59:OUT.20 | CFG.USR_ACCESS_DATA26 |
| TCELL59:OUT.22 | CFG.USR_ACCESS_DATA27 |
| TCELL59:OUT.24 | CFG.USR_ACCESS_DATA28 |
| TCELL59:OUT.26 | CFG.USR_ACCESS_DATA29 |
| TCELL59:OUT.28 | CFG.USR_ACCESS_DATA30 |
| TCELL59:OUT.30 | CFG.USR_ACCESS_DATA31 |
Tile CFG_CSEC
Cells: 60 IRIs: 0
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| ARADDR0 | input | TCELL20:IMUX.IMUX.9 |
| ARADDR1 | input | TCELL20:IMUX.IMUX.10 |
| ARADDR10 | input | TCELL21:IMUX.IMUX.3 |
| ARADDR11 | input | TCELL21:IMUX.IMUX.4 |
| ARADDR12 | input | TCELL21:IMUX.IMUX.5 |
| ARADDR13 | input | TCELL21:IMUX.IMUX.6 |
| ARADDR14 | input | TCELL21:IMUX.IMUX.7 |
| ARADDR15 | input | TCELL21:IMUX.IMUX.8 |
| ARADDR16 | input | TCELL21:IMUX.IMUX.9 |
| ARADDR17 | input | TCELL21:IMUX.IMUX.10 |
| ARADDR18 | input | TCELL21:IMUX.IMUX.11 |
| ARADDR19 | input | TCELL21:IMUX.IMUX.12 |
| ARADDR2 | input | TCELL20:IMUX.IMUX.11 |
| ARADDR20 | input | TCELL21:IMUX.IMUX.13 |
| ARADDR21 | input | TCELL21:IMUX.IMUX.14 |
| ARADDR22 | input | TCELL20:IMUX.IMUX.3 |
| ARADDR23 | input | TCELL20:IMUX.IMUX.4 |
| ARADDR24 | input | TCELL20:IMUX.IMUX.5 |
| ARADDR25 | input | TCELL20:IMUX.IMUX.6 |
| ARADDR26 | input | TCELL20:IMUX.IMUX.7 |
| ARADDR27 | input | TCELL20:IMUX.IMUX.8 |
| ARADDR3 | input | TCELL20:IMUX.IMUX.12 |
| ARADDR4 | input | TCELL20:IMUX.IMUX.13 |
| ARADDR5 | input | TCELL20:IMUX.IMUX.14 |
| ARADDR6 | input | TCELL20:IMUX.IMUX.15 |
| ARADDR7 | input | TCELL21:IMUX.IMUX.0 |
| ARADDR8 | input | TCELL21:IMUX.IMUX.1 |
| ARADDR9 | input | TCELL21:IMUX.IMUX.2 |
| ARBURST0 | input | TCELL22:IMUX.IMUX.6 |
| ARBURST1 | input | TCELL22:IMUX.IMUX.7 |
| ARCACHE0 | input | TCELL22:IMUX.IMUX.9 |
| ARCACHE1 | input | TCELL22:IMUX.IMUX.10 |
| ARCACHE2 | input | TCELL22:IMUX.IMUX.11 |
| ARCACHE3 | input | TCELL22:IMUX.IMUX.12 |
| ARID0 | input | TCELL31:IMUX.IMUX.1 |
| ARID1 | input | TCELL31:IMUX.IMUX.2 |
| ARID2 | input | TCELL31:IMUX.IMUX.3 |
| ARID3 | input | TCELL31:IMUX.IMUX.4 |
| ARID4 | input | TCELL31:IMUX.IMUX.5 |
| ARID5 | input | TCELL31:IMUX.IMUX.6 |
| ARID6 | input | TCELL31:IMUX.IMUX.7 |
| ARID7 | input | TCELL31:IMUX.IMUX.8 |
| ARLEN0 | input | TCELL21:IMUX.IMUX.15 |
| ARLEN1 | input | TCELL22:IMUX.IMUX.0 |
| ARLEN2 | input | TCELL22:IMUX.IMUX.1 |
| ARLEN3 | input | TCELL22:IMUX.IMUX.2 |
| ARLOCK | input | TCELL22:IMUX.IMUX.8 |
| ARPROT0 | input | TCELL22:IMUX.IMUX.13 |
| ARPROT1 | input | TCELL22:IMUX.IMUX.14 |
| ARPROT2 | input | TCELL22:IMUX.IMUX.15 |
| ARQOS0 | input | TCELL23:IMUX.IMUX.0 |
| ARQOS1 | input | TCELL23:IMUX.IMUX.1 |
| ARQOS2 | input | TCELL23:IMUX.IMUX.2 |
| ARQOS3 | input | TCELL23:IMUX.IMUX.3 |
| ARREADY | output | TCELL20:OUT.0 |
| ARSIZE0 | input | TCELL22:IMUX.IMUX.3 |
| ARSIZE1 | input | TCELL22:IMUX.IMUX.4 |
| ARSIZE2 | input | TCELL22:IMUX.IMUX.5 |
| ARVALID | input | TCELL20:IMUX.IMUX.0 |
| AWADDR0 | input | TCELL24:IMUX.IMUX.9 |
| AWADDR1 | input | TCELL24:IMUX.IMUX.10 |
| AWADDR10 | input | TCELL25:IMUX.IMUX.3 |
| AWADDR11 | input | TCELL25:IMUX.IMUX.4 |
| AWADDR12 | input | TCELL25:IMUX.IMUX.5 |
| AWADDR13 | input | TCELL25:IMUX.IMUX.6 |
| AWADDR14 | input | TCELL25:IMUX.IMUX.7 |
| AWADDR15 | input | TCELL25:IMUX.IMUX.8 |
| AWADDR16 | input | TCELL25:IMUX.IMUX.9 |
| AWADDR17 | input | TCELL25:IMUX.IMUX.10 |
| AWADDR18 | input | TCELL25:IMUX.IMUX.11 |
| AWADDR19 | input | TCELL25:IMUX.IMUX.12 |
| AWADDR2 | input | TCELL24:IMUX.IMUX.11 |
| AWADDR20 | input | TCELL25:IMUX.IMUX.13 |
| AWADDR21 | input | TCELL25:IMUX.IMUX.14 |
| AWADDR22 | input | TCELL24:IMUX.IMUX.3 |
| AWADDR23 | input | TCELL24:IMUX.IMUX.4 |
| AWADDR24 | input | TCELL24:IMUX.IMUX.5 |
| AWADDR25 | input | TCELL24:IMUX.IMUX.6 |
| AWADDR26 | input | TCELL24:IMUX.IMUX.7 |
| AWADDR27 | input | TCELL24:IMUX.IMUX.8 |
| AWADDR3 | input | TCELL24:IMUX.IMUX.12 |
| AWADDR4 | input | TCELL24:IMUX.IMUX.13 |
| AWADDR5 | input | TCELL24:IMUX.IMUX.14 |
| AWADDR6 | input | TCELL24:IMUX.IMUX.15 |
| AWADDR7 | input | TCELL25:IMUX.IMUX.0 |
| AWADDR8 | input | TCELL25:IMUX.IMUX.1 |
| AWADDR9 | input | TCELL25:IMUX.IMUX.2 |
| AWBURST0 | input | TCELL26:IMUX.IMUX.6 |
| AWBURST1 | input | TCELL26:IMUX.IMUX.7 |
| AWCACHE0 | input | TCELL26:IMUX.IMUX.9 |
| AWCACHE1 | input | TCELL26:IMUX.IMUX.10 |
| AWCACHE2 | input | TCELL26:IMUX.IMUX.11 |
| AWCACHE3 | input | TCELL26:IMUX.IMUX.12 |
| AWID0 | input | TCELL32:IMUX.IMUX.1 |
| AWID1 | input | TCELL32:IMUX.IMUX.2 |
| AWID2 | input | TCELL32:IMUX.IMUX.3 |
| AWID3 | input | TCELL32:IMUX.IMUX.4 |
| AWID4 | input | TCELL32:IMUX.IMUX.5 |
| AWID5 | input | TCELL32:IMUX.IMUX.6 |
| AWID6 | input | TCELL32:IMUX.IMUX.7 |
| AWID7 | input | TCELL32:IMUX.IMUX.8 |
| AWLEN0 | input | TCELL25:IMUX.IMUX.15 |
| AWLEN1 | input | TCELL26:IMUX.IMUX.0 |
| AWLEN2 | input | TCELL26:IMUX.IMUX.1 |
| AWLEN3 | input | TCELL26:IMUX.IMUX.2 |
| AWLOCK | input | TCELL26:IMUX.IMUX.8 |
| AWPROT0 | input | TCELL26:IMUX.IMUX.13 |
| AWPROT1 | input | TCELL26:IMUX.IMUX.14 |
| AWPROT2 | input | TCELL26:IMUX.IMUX.15 |
| AWQOS0 | input | TCELL27:IMUX.IMUX.0 |
| AWQOS1 | input | TCELL27:IMUX.IMUX.1 |
| AWQOS2 | input | TCELL27:IMUX.IMUX.2 |
| AWQOS3 | input | TCELL27:IMUX.IMUX.3 |
| AWREADY | output | TCELL24:OUT.0 |
| AWSIZE0 | input | TCELL26:IMUX.IMUX.3 |
| AWSIZE1 | input | TCELL26:IMUX.IMUX.4 |
| AWSIZE2 | input | TCELL26:IMUX.IMUX.5 |
| AWVALID | input | TCELL24:IMUX.IMUX.0 |
| AXI_CLK | input | TCELL20:IMUX.CTRL.0 |
| BID0 | output | TCELL34:OUT.2 |
| BID1 | output | TCELL34:OUT.4 |
| BID2 | output | TCELL34:OUT.6 |
| BID3 | output | TCELL34:OUT.8 |
| BID4 | output | TCELL34:OUT.10 |
| BID5 | output | TCELL34:OUT.12 |
| BID6 | output | TCELL34:OUT.14 |
| BID7 | output | TCELL34:OUT.16 |
| BREADY | input | TCELL34:IMUX.IMUX.0 |
| BRESP0 | output | TCELL34:OUT.18 |
| BRESP1 | output | TCELL34:OUT.20 |
| BSCAN_CDR1 | output | TCELL42:OUT.4 |
| BSCAN_CDR2 | output | TCELL42:OUT.6 |
| BSCAN_CDR3 | output | TCELL54:OUT.18 |
| BSCAN_CDR4 | output | TCELL54:OUT.20 |
| BSCAN_CLKDR1 | output | TCELL42:OUT.8 |
| BSCAN_CLKDR2 | output | TCELL42:OUT.10 |
| BSCAN_CLKDR3 | output | TCELL54:OUT.22 |
| BSCAN_CLKDR4 | output | TCELL54:OUT.24 |
| BSCAN_RTI1 | output | TCELL42:OUT.12 |
| BSCAN_RTI2 | output | TCELL42:OUT.14 |
| BSCAN_RTI3 | output | TCELL54:OUT.26 |
| BSCAN_RTI4 | output | TCELL54:OUT.28 |
| BSCAN_SDR1 | output | TCELL42:OUT.16 |
| BSCAN_SDR2 | output | TCELL42:OUT.18 |
| BSCAN_SDR3 | output | TCELL53:OUT.0 |
| BSCAN_SDR4 | output | TCELL53:OUT.2 |
| BSCAN_SEL1 | output | TCELL42:OUT.20 |
| BSCAN_SEL2 | output | TCELL42:OUT.22 |
| BSCAN_SEL3 | output | TCELL53:OUT.4 |
| BSCAN_SEL4 | output | TCELL53:OUT.6 |
| BSCAN_TCK1 | output | TCELL43:OUT.6 |
| BSCAN_TCK2 | output | TCELL43:OUT.8 |
| BSCAN_TCK3 | output | TCELL54:OUT.6 |
| BSCAN_TCK4 | output | TCELL54:OUT.8 |
| BSCAN_TDI1 | output | TCELL43:OUT.14 |
| BSCAN_TDI2 | output | TCELL43:OUT.16 |
| BSCAN_TDI3 | output | TCELL54:OUT.14 |
| BSCAN_TDI4 | output | TCELL54:OUT.16 |
| BSCAN_TDO1 | input | TCELL43:IMUX.IMUX.2 |
| BSCAN_TDO2 | input | TCELL43:IMUX.IMUX.3 |
| BSCAN_TDO3 | input | TCELL54:IMUX.IMUX.2 |
| BSCAN_TDO4 | input | TCELL54:IMUX.IMUX.3 |
| BSCAN_TLR1 | output | TCELL42:OUT.24 |
| BSCAN_TLR2 | output | TCELL42:OUT.26 |
| BSCAN_TLR3 | output | TCELL53:OUT.8 |
| BSCAN_TLR4 | output | TCELL53:OUT.10 |
| BSCAN_TMS1 | output | TCELL43:OUT.10 |
| BSCAN_TMS2 | output | TCELL43:OUT.12 |
| BSCAN_TMS3 | output | TCELL54:OUT.10 |
| BSCAN_TMS4 | output | TCELL54:OUT.12 |
| BSCAN_UDR1 | output | TCELL42:OUT.28 |
| BSCAN_UDR2 | output | TCELL42:OUT.30 |
| BSCAN_UDR3 | output | TCELL53:OUT.12 |
| BSCAN_UDR4 | output | TCELL53:OUT.14 |
| BVALID | output | TCELL34:OUT.0 |
| DCI_LOCK | output | TCELL42:OUT.2 |
| DCI_USR_RESET_IN | input | TCELL42:IMUX.IMUX.3 |
| ECC_END_OF_FRAME | output | TCELL51:OUT.26 |
| ECC_END_OF_SCAN | output | TCELL51:OUT.28 |
| ECC_ERROR_NOTSINGLE | output | TCELL51:OUT.22 |
| ECC_ERROR_SINGLE | output | TCELL51:OUT.24 |
| ECC_FAR0 | output | TCELL52:OUT.0 |
| ECC_FAR1 | output | TCELL52:OUT.2 |
| ECC_FAR10 | output | TCELL52:OUT.20 |
| ECC_FAR11 | output | TCELL52:OUT.22 |
| ECC_FAR12 | output | TCELL52:OUT.24 |
| ECC_FAR13 | output | TCELL52:OUT.26 |
| ECC_FAR14 | output | TCELL52:OUT.28 |
| ECC_FAR15 | output | TCELL52:OUT.30 |
| ECC_FAR16 | output | TCELL51:OUT.0 |
| ECC_FAR17 | output | TCELL51:OUT.2 |
| ECC_FAR18 | output | TCELL51:OUT.4 |
| ECC_FAR19 | output | TCELL51:OUT.6 |
| ECC_FAR2 | output | TCELL52:OUT.4 |
| ECC_FAR20 | output | TCELL51:OUT.8 |
| ECC_FAR21 | output | TCELL51:OUT.10 |
| ECC_FAR22 | output | TCELL51:OUT.12 |
| ECC_FAR23 | output | TCELL51:OUT.14 |
| ECC_FAR24 | output | TCELL51:OUT.16 |
| ECC_FAR25 | output | TCELL51:OUT.18 |
| ECC_FAR26 | output | TCELL52:OUT.31 |
| ECC_FAR3 | output | TCELL52:OUT.6 |
| ECC_FAR4 | output | TCELL52:OUT.8 |
| ECC_FAR5 | output | TCELL52:OUT.10 |
| ECC_FAR6 | output | TCELL52:OUT.12 |
| ECC_FAR7 | output | TCELL52:OUT.14 |
| ECC_FAR8 | output | TCELL52:OUT.16 |
| ECC_FAR9 | output | TCELL52:OUT.18 |
| ECC_FAR_SEL0 | input | TCELL51:IMUX.IMUX.15 |
| ECC_FAR_SEL1 | input | TCELL51:IMUX.IMUX.16 |
| EOS | output | TCELL47:OUT.10 |
| ICAP_AVAIL_BOT | output | TCELL43:OUT.4 |
| ICAP_AVAIL_TOP | output | TCELL54:OUT.4 |
| ICAP_CLK_BOT | input | TCELL45:IMUX.CTRL.0 |
| ICAP_CLK_TOP | input | TCELL56:IMUX.CTRL.0 |
| ICAP_CS_B_BOT | input | TCELL43:IMUX.IMUX.1 |
| ICAP_CS_B_TOP | input | TCELL54:IMUX.IMUX.1 |
| ICAP_DATA_BOT0 | input | TCELL44:IMUX.IMUX.0 |
| ICAP_DATA_BOT1 | input | TCELL44:IMUX.IMUX.1 |
| ICAP_DATA_BOT10 | input | TCELL44:IMUX.IMUX.10 |
| ICAP_DATA_BOT11 | input | TCELL44:IMUX.IMUX.11 |
| ICAP_DATA_BOT12 | input | TCELL44:IMUX.IMUX.12 |
| ICAP_DATA_BOT13 | input | TCELL44:IMUX.IMUX.13 |
| ICAP_DATA_BOT14 | input | TCELL44:IMUX.IMUX.14 |
| ICAP_DATA_BOT15 | input | TCELL44:IMUX.IMUX.15 |
| ICAP_DATA_BOT16 | input | TCELL45:IMUX.IMUX.0 |
| ICAP_DATA_BOT17 | input | TCELL45:IMUX.IMUX.1 |
| ICAP_DATA_BOT18 | input | TCELL45:IMUX.IMUX.2 |
| ICAP_DATA_BOT19 | input | TCELL45:IMUX.IMUX.3 |
| ICAP_DATA_BOT2 | input | TCELL44:IMUX.IMUX.2 |
| ICAP_DATA_BOT20 | input | TCELL45:IMUX.IMUX.4 |
| ICAP_DATA_BOT21 | input | TCELL45:IMUX.IMUX.5 |
| ICAP_DATA_BOT22 | input | TCELL45:IMUX.IMUX.6 |
| ICAP_DATA_BOT23 | input | TCELL45:IMUX.IMUX.7 |
| ICAP_DATA_BOT24 | input | TCELL45:IMUX.IMUX.8 |
| ICAP_DATA_BOT25 | input | TCELL45:IMUX.IMUX.9 |
| ICAP_DATA_BOT26 | input | TCELL45:IMUX.IMUX.10 |
| ICAP_DATA_BOT27 | input | TCELL45:IMUX.IMUX.11 |
| ICAP_DATA_BOT28 | input | TCELL45:IMUX.IMUX.12 |
| ICAP_DATA_BOT29 | input | TCELL45:IMUX.IMUX.13 |
| ICAP_DATA_BOT3 | input | TCELL44:IMUX.IMUX.3 |
| ICAP_DATA_BOT30 | input | TCELL45:IMUX.IMUX.14 |
| ICAP_DATA_BOT31 | input | TCELL45:IMUX.IMUX.15 |
| ICAP_DATA_BOT4 | input | TCELL44:IMUX.IMUX.4 |
| ICAP_DATA_BOT5 | input | TCELL44:IMUX.IMUX.5 |
| ICAP_DATA_BOT6 | input | TCELL44:IMUX.IMUX.6 |
| ICAP_DATA_BOT7 | input | TCELL44:IMUX.IMUX.7 |
| ICAP_DATA_BOT8 | input | TCELL44:IMUX.IMUX.8 |
| ICAP_DATA_BOT9 | input | TCELL44:IMUX.IMUX.9 |
| ICAP_DATA_TOP0 | input | TCELL55:IMUX.IMUX.0 |
| ICAP_DATA_TOP1 | input | TCELL55:IMUX.IMUX.1 |
| ICAP_DATA_TOP10 | input | TCELL55:IMUX.IMUX.10 |
| ICAP_DATA_TOP11 | input | TCELL55:IMUX.IMUX.11 |
| ICAP_DATA_TOP12 | input | TCELL55:IMUX.IMUX.12 |
| ICAP_DATA_TOP13 | input | TCELL55:IMUX.IMUX.13 |
| ICAP_DATA_TOP14 | input | TCELL55:IMUX.IMUX.14 |
| ICAP_DATA_TOP15 | input | TCELL55:IMUX.IMUX.15 |
| ICAP_DATA_TOP16 | input | TCELL56:IMUX.IMUX.0 |
| ICAP_DATA_TOP17 | input | TCELL56:IMUX.IMUX.1 |
| ICAP_DATA_TOP18 | input | TCELL56:IMUX.IMUX.2 |
| ICAP_DATA_TOP19 | input | TCELL56:IMUX.IMUX.3 |
| ICAP_DATA_TOP2 | input | TCELL55:IMUX.IMUX.2 |
| ICAP_DATA_TOP20 | input | TCELL56:IMUX.IMUX.4 |
| ICAP_DATA_TOP21 | input | TCELL56:IMUX.IMUX.5 |
| ICAP_DATA_TOP22 | input | TCELL56:IMUX.IMUX.6 |
| ICAP_DATA_TOP23 | input | TCELL56:IMUX.IMUX.7 |
| ICAP_DATA_TOP24 | input | TCELL56:IMUX.IMUX.8 |
| ICAP_DATA_TOP25 | input | TCELL56:IMUX.IMUX.9 |
| ICAP_DATA_TOP26 | input | TCELL56:IMUX.IMUX.10 |
| ICAP_DATA_TOP27 | input | TCELL56:IMUX.IMUX.11 |
| ICAP_DATA_TOP28 | input | TCELL56:IMUX.IMUX.12 |
| ICAP_DATA_TOP29 | input | TCELL56:IMUX.IMUX.13 |
| ICAP_DATA_TOP3 | input | TCELL55:IMUX.IMUX.3 |
| ICAP_DATA_TOP30 | input | TCELL56:IMUX.IMUX.14 |
| ICAP_DATA_TOP31 | input | TCELL56:IMUX.IMUX.15 |
| ICAP_DATA_TOP4 | input | TCELL55:IMUX.IMUX.4 |
| ICAP_DATA_TOP5 | input | TCELL55:IMUX.IMUX.5 |
| ICAP_DATA_TOP6 | input | TCELL55:IMUX.IMUX.6 |
| ICAP_DATA_TOP7 | input | TCELL55:IMUX.IMUX.7 |
| ICAP_DATA_TOP8 | input | TCELL55:IMUX.IMUX.8 |
| ICAP_DATA_TOP9 | input | TCELL55:IMUX.IMUX.9 |
| ICAP_OUT_BOT0 | output | TCELL44:OUT.0 |
| ICAP_OUT_BOT1 | output | TCELL44:OUT.2 |
| ICAP_OUT_BOT10 | output | TCELL44:OUT.20 |
| ICAP_OUT_BOT11 | output | TCELL44:OUT.22 |
| ICAP_OUT_BOT12 | output | TCELL44:OUT.24 |
| ICAP_OUT_BOT13 | output | TCELL44:OUT.26 |
| ICAP_OUT_BOT14 | output | TCELL44:OUT.28 |
| ICAP_OUT_BOT15 | output | TCELL44:OUT.30 |
| ICAP_OUT_BOT16 | output | TCELL45:OUT.0 |
| ICAP_OUT_BOT17 | output | TCELL45:OUT.2 |
| ICAP_OUT_BOT18 | output | TCELL45:OUT.4 |
| ICAP_OUT_BOT19 | output | TCELL45:OUT.6 |
| ICAP_OUT_BOT2 | output | TCELL44:OUT.4 |
| ICAP_OUT_BOT20 | output | TCELL45:OUT.8 |
| ICAP_OUT_BOT21 | output | TCELL45:OUT.10 |
| ICAP_OUT_BOT22 | output | TCELL45:OUT.12 |
| ICAP_OUT_BOT23 | output | TCELL45:OUT.14 |
| ICAP_OUT_BOT24 | output | TCELL45:OUT.16 |
| ICAP_OUT_BOT25 | output | TCELL45:OUT.18 |
| ICAP_OUT_BOT26 | output | TCELL45:OUT.20 |
| ICAP_OUT_BOT27 | output | TCELL45:OUT.22 |
| ICAP_OUT_BOT28 | output | TCELL45:OUT.24 |
| ICAP_OUT_BOT29 | output | TCELL45:OUT.26 |
| ICAP_OUT_BOT3 | output | TCELL44:OUT.6 |
| ICAP_OUT_BOT30 | output | TCELL45:OUT.28 |
| ICAP_OUT_BOT31 | output | TCELL45:OUT.30 |
| ICAP_OUT_BOT4 | output | TCELL44:OUT.8 |
| ICAP_OUT_BOT5 | output | TCELL44:OUT.10 |
| ICAP_OUT_BOT6 | output | TCELL44:OUT.12 |
| ICAP_OUT_BOT7 | output | TCELL44:OUT.14 |
| ICAP_OUT_BOT8 | output | TCELL44:OUT.16 |
| ICAP_OUT_BOT9 | output | TCELL44:OUT.18 |
| ICAP_OUT_TOP0 | output | TCELL55:OUT.0 |
| ICAP_OUT_TOP1 | output | TCELL55:OUT.2 |
| ICAP_OUT_TOP10 | output | TCELL55:OUT.20 |
| ICAP_OUT_TOP11 | output | TCELL55:OUT.22 |
| ICAP_OUT_TOP12 | output | TCELL55:OUT.24 |
| ICAP_OUT_TOP13 | output | TCELL55:OUT.26 |
| ICAP_OUT_TOP14 | output | TCELL55:OUT.28 |
| ICAP_OUT_TOP15 | output | TCELL55:OUT.30 |
| ICAP_OUT_TOP16 | output | TCELL56:OUT.0 |
| ICAP_OUT_TOP17 | output | TCELL56:OUT.2 |
| ICAP_OUT_TOP18 | output | TCELL56:OUT.4 |
| ICAP_OUT_TOP19 | output | TCELL56:OUT.6 |
| ICAP_OUT_TOP2 | output | TCELL55:OUT.4 |
| ICAP_OUT_TOP20 | output | TCELL56:OUT.8 |
| ICAP_OUT_TOP21 | output | TCELL56:OUT.10 |
| ICAP_OUT_TOP22 | output | TCELL56:OUT.12 |
| ICAP_OUT_TOP23 | output | TCELL56:OUT.14 |
| ICAP_OUT_TOP24 | output | TCELL56:OUT.16 |
| ICAP_OUT_TOP25 | output | TCELL56:OUT.18 |
| ICAP_OUT_TOP26 | output | TCELL56:OUT.20 |
| ICAP_OUT_TOP27 | output | TCELL56:OUT.22 |
| ICAP_OUT_TOP28 | output | TCELL56:OUT.24 |
| ICAP_OUT_TOP29 | output | TCELL56:OUT.26 |
| ICAP_OUT_TOP3 | output | TCELL55:OUT.6 |
| ICAP_OUT_TOP30 | output | TCELL56:OUT.28 |
| ICAP_OUT_TOP31 | output | TCELL56:OUT.30 |
| ICAP_OUT_TOP4 | output | TCELL55:OUT.8 |
| ICAP_OUT_TOP5 | output | TCELL55:OUT.10 |
| ICAP_OUT_TOP6 | output | TCELL55:OUT.12 |
| ICAP_OUT_TOP7 | output | TCELL55:OUT.14 |
| ICAP_OUT_TOP8 | output | TCELL55:OUT.16 |
| ICAP_OUT_TOP9 | output | TCELL55:OUT.18 |
| ICAP_PR_DONE_BOT | output | TCELL43:OUT.0 |
| ICAP_PR_DONE_TOP | output | TCELL54:OUT.0 |
| ICAP_PR_ERROR_BOT | output | TCELL43:OUT.2 |
| ICAP_PR_ERROR_TOP | output | TCELL54:OUT.2 |
| ICAP_RDWR_B_BOT | input | TCELL43:IMUX.IMUX.0 |
| ICAP_RDWR_B_TOP | input | TCELL54:IMUX.IMUX.0 |
| IOX_CCLK | output | TCELL50:OUT.0 |
| IOX_CFGDATA0 | output | TCELL48:OUT.0 |
| IOX_CFGDATA1 | output | TCELL48:OUT.2 |
| IOX_CFGDATA10 | output | TCELL48:OUT.20 |
| IOX_CFGDATA11 | output | TCELL48:OUT.22 |
| IOX_CFGDATA12 | output | TCELL48:OUT.24 |
| IOX_CFGDATA13 | output | TCELL48:OUT.26 |
| IOX_CFGDATA14 | output | TCELL48:OUT.28 |
| IOX_CFGDATA15 | output | TCELL48:OUT.30 |
| IOX_CFGDATA16 | output | TCELL49:OUT.0 |
| IOX_CFGDATA17 | output | TCELL49:OUT.2 |
| IOX_CFGDATA18 | output | TCELL49:OUT.4 |
| IOX_CFGDATA19 | output | TCELL49:OUT.6 |
| IOX_CFGDATA2 | output | TCELL48:OUT.4 |
| IOX_CFGDATA20 | output | TCELL49:OUT.8 |
| IOX_CFGDATA21 | output | TCELL49:OUT.10 |
| IOX_CFGDATA22 | output | TCELL49:OUT.12 |
| IOX_CFGDATA23 | output | TCELL49:OUT.14 |
| IOX_CFGDATA24 | output | TCELL49:OUT.16 |
| IOX_CFGDATA25 | output | TCELL49:OUT.18 |
| IOX_CFGDATA26 | output | TCELL49:OUT.20 |
| IOX_CFGDATA27 | output | TCELL49:OUT.22 |
| IOX_CFGDATA28 | output | TCELL49:OUT.24 |
| IOX_CFGDATA29 | output | TCELL49:OUT.26 |
| IOX_CFGDATA3 | output | TCELL48:OUT.6 |
| IOX_CFGDATA30 | output | TCELL49:OUT.28 |
| IOX_CFGDATA31 | output | TCELL49:OUT.30 |
| IOX_CFGDATA4 | output | TCELL48:OUT.8 |
| IOX_CFGDATA5 | output | TCELL48:OUT.10 |
| IOX_CFGDATA6 | output | TCELL48:OUT.12 |
| IOX_CFGDATA7 | output | TCELL48:OUT.14 |
| IOX_CFGDATA8 | output | TCELL48:OUT.16 |
| IOX_CFGDATA9 | output | TCELL48:OUT.18 |
| IOX_CFGMASTER | output | TCELL50:OUT.2 |
| IOX_INITBI | output | TCELL50:OUT.6 |
| IOX_INITBO | input | TCELL48:IMUX.IMUX.1 |
| IOX_MODE0 | output | TCELL50:OUT.12 |
| IOX_MODE1 | output | TCELL50:OUT.14 |
| IOX_MODE2 | output | TCELL50:OUT.16 |
| IOX_PUDCB | output | TCELL50:OUT.8 |
| IOX_RDWRB | output | TCELL50:OUT.10 |
| IOX_TDO | input | TCELL48:IMUX.IMUX.0 |
| IOX_VGG_COMP_OUT | output | TCELL50:OUT.4 |
| KEY_CLEAR_B | input | TCELL47:IMUX.IMUX.0 |
| PROG_ACK | input | TCELL47:IMUX.IMUX.1 |
| PROG_REQ | output | TCELL47:OUT.8 |
| RBCRC_ERROR | output | TCELL51:OUT.20 |
| RDATA0 | output | TCELL31:OUT.24 |
| RDATA1 | output | TCELL31:OUT.26 |
| RDATA10 | output | TCELL32:OUT.12 |
| RDATA11 | output | TCELL32:OUT.14 |
| RDATA12 | output | TCELL32:OUT.16 |
| RDATA13 | output | TCELL32:OUT.18 |
| RDATA14 | output | TCELL32:OUT.20 |
| RDATA15 | output | TCELL32:OUT.22 |
| RDATA16 | output | TCELL32:OUT.24 |
| RDATA17 | output | TCELL32:OUT.26 |
| RDATA18 | output | TCELL32:OUT.28 |
| RDATA19 | output | TCELL32:OUT.30 |
| RDATA2 | output | TCELL31:OUT.28 |
| RDATA20 | output | TCELL33:OUT.0 |
| RDATA21 | output | TCELL33:OUT.2 |
| RDATA22 | output | TCELL33:OUT.4 |
| RDATA23 | output | TCELL33:OUT.6 |
| RDATA24 | output | TCELL33:OUT.8 |
| RDATA25 | output | TCELL33:OUT.10 |
| RDATA26 | output | TCELL33:OUT.12 |
| RDATA27 | output | TCELL33:OUT.14 |
| RDATA28 | output | TCELL33:OUT.16 |
| RDATA29 | output | TCELL33:OUT.18 |
| RDATA3 | output | TCELL31:OUT.30 |
| RDATA30 | output | TCELL33:OUT.20 |
| RDATA31 | output | TCELL33:OUT.22 |
| RDATA4 | output | TCELL32:OUT.0 |
| RDATA5 | output | TCELL32:OUT.2 |
| RDATA6 | output | TCELL32:OUT.4 |
| RDATA7 | output | TCELL32:OUT.6 |
| RDATA8 | output | TCELL32:OUT.8 |
| RDATA9 | output | TCELL32:OUT.10 |
| RID0 | output | TCELL31:OUT.4 |
| RID1 | output | TCELL31:OUT.6 |
| RID2 | output | TCELL31:OUT.8 |
| RID3 | output | TCELL31:OUT.10 |
| RID4 | output | TCELL31:OUT.12 |
| RID5 | output | TCELL31:OUT.14 |
| RID6 | output | TCELL31:OUT.16 |
| RID7 | output | TCELL31:OUT.18 |
| RLAST | output | TCELL31:OUT.2 |
| RREADY | input | TCELL31:IMUX.IMUX.0 |
| RRESP0 | output | TCELL31:OUT.20 |
| RRESP1 | output | TCELL31:OUT.22 |
| RVALID | output | TCELL31:OUT.0 |
| START_CFG_CLK | output | TCELL47:OUT.14 |
| START_CFG_MCLK | output | TCELL47:OUT.12 |
| USR_ACCESS_CLK | output | TCELL57:OUT.2 |
| USR_ACCESS_DATA0 | output | TCELL58:OUT.0 |
| USR_ACCESS_DATA1 | output | TCELL58:OUT.2 |
| USR_ACCESS_DATA10 | output | TCELL58:OUT.20 |
| USR_ACCESS_DATA11 | output | TCELL58:OUT.22 |
| USR_ACCESS_DATA12 | output | TCELL58:OUT.24 |
| USR_ACCESS_DATA13 | output | TCELL58:OUT.26 |
| USR_ACCESS_DATA14 | output | TCELL58:OUT.28 |
| USR_ACCESS_DATA15 | output | TCELL58:OUT.30 |
| USR_ACCESS_DATA16 | output | TCELL59:OUT.0 |
| USR_ACCESS_DATA17 | output | TCELL59:OUT.2 |
| USR_ACCESS_DATA18 | output | TCELL59:OUT.4 |
| USR_ACCESS_DATA19 | output | TCELL59:OUT.6 |
| USR_ACCESS_DATA2 | output | TCELL58:OUT.4 |
| USR_ACCESS_DATA20 | output | TCELL59:OUT.8 |
| USR_ACCESS_DATA21 | output | TCELL59:OUT.10 |
| USR_ACCESS_DATA22 | output | TCELL59:OUT.12 |
| USR_ACCESS_DATA23 | output | TCELL59:OUT.14 |
| USR_ACCESS_DATA24 | output | TCELL59:OUT.16 |
| USR_ACCESS_DATA25 | output | TCELL59:OUT.18 |
| USR_ACCESS_DATA26 | output | TCELL59:OUT.20 |
| USR_ACCESS_DATA27 | output | TCELL59:OUT.22 |
| USR_ACCESS_DATA28 | output | TCELL59:OUT.24 |
| USR_ACCESS_DATA29 | output | TCELL59:OUT.26 |
| USR_ACCESS_DATA3 | output | TCELL58:OUT.6 |
| USR_ACCESS_DATA30 | output | TCELL59:OUT.28 |
| USR_ACCESS_DATA31 | output | TCELL59:OUT.30 |
| USR_ACCESS_DATA4 | output | TCELL58:OUT.8 |
| USR_ACCESS_DATA5 | output | TCELL58:OUT.10 |
| USR_ACCESS_DATA6 | output | TCELL58:OUT.12 |
| USR_ACCESS_DATA7 | output | TCELL58:OUT.14 |
| USR_ACCESS_DATA8 | output | TCELL58:OUT.16 |
| USR_ACCESS_DATA9 | output | TCELL58:OUT.18 |
| USR_ACCESS_VALID | output | TCELL57:OUT.0 |
| USR_CCLK_O | input | TCELL47:IMUX.CTRL.0 |
| USR_CCLK_TS | input | TCELL47:IMUX.IMUX.2 |
| USR_DNA_CLK | input | TCELL42:IMUX.CTRL.0 |
| USR_DNA_DIN | input | TCELL42:IMUX.IMUX.0 |
| USR_DNA_OUT | output | TCELL42:OUT.0 |
| USR_DNA_READ | input | TCELL42:IMUX.IMUX.1 |
| USR_DNA_SHIFT | input | TCELL42:IMUX.IMUX.2 |
| USR_DONE_O | input | TCELL47:IMUX.IMUX.3 |
| USR_DONE_TS | input | TCELL47:IMUX.IMUX.4 |
| USR_D_O_CFGIO0 | input | TCELL47:IMUX.IMUX.9 |
| USR_D_O_CFGIO1 | input | TCELL47:IMUX.IMUX.10 |
| USR_D_O_CFGIO2 | input | TCELL47:IMUX.IMUX.11 |
| USR_D_O_CFGIO3 | input | TCELL47:IMUX.IMUX.12 |
| USR_D_PIN_CFGIO0 | output | TCELL47:OUT.0 |
| USR_D_PIN_CFGIO1 | output | TCELL47:OUT.2 |
| USR_D_PIN_CFGIO2 | output | TCELL47:OUT.4 |
| USR_D_PIN_CFGIO3 | output | TCELL47:OUT.6 |
| USR_D_TS_CFGIO0 | input | TCELL47:IMUX.IMUX.13 |
| USR_D_TS_CFGIO1 | input | TCELL47:IMUX.IMUX.14 |
| USR_D_TS_CFGIO2 | input | TCELL47:IMUX.IMUX.15 |
| USR_D_TS_CFGIO3 | input | TCELL47:IMUX.IMUX.16 |
| USR_EFUSE0 | output | TCELL46:OUT.0 |
| USR_EFUSE1 | output | TCELL46:OUT.2 |
| USR_EFUSE10 | output | TCELL46:OUT.20 |
| USR_EFUSE11 | output | TCELL46:OUT.22 |
| USR_EFUSE12 | output | TCELL46:OUT.24 |
| USR_EFUSE13 | output | TCELL46:OUT.26 |
| USR_EFUSE14 | output | TCELL46:OUT.28 |
| USR_EFUSE15 | output | TCELL46:OUT.30 |
| USR_EFUSE16 | output | TCELL41:OUT.0 |
| USR_EFUSE17 | output | TCELL41:OUT.2 |
| USR_EFUSE18 | output | TCELL41:OUT.4 |
| USR_EFUSE19 | output | TCELL41:OUT.6 |
| USR_EFUSE2 | output | TCELL46:OUT.4 |
| USR_EFUSE20 | output | TCELL41:OUT.8 |
| USR_EFUSE21 | output | TCELL41:OUT.10 |
| USR_EFUSE22 | output | TCELL41:OUT.12 |
| USR_EFUSE23 | output | TCELL41:OUT.14 |
| USR_EFUSE24 | output | TCELL41:OUT.16 |
| USR_EFUSE25 | output | TCELL41:OUT.18 |
| USR_EFUSE26 | output | TCELL41:OUT.20 |
| USR_EFUSE27 | output | TCELL41:OUT.22 |
| USR_EFUSE28 | output | TCELL41:OUT.24 |
| USR_EFUSE29 | output | TCELL41:OUT.26 |
| USR_EFUSE3 | output | TCELL46:OUT.6 |
| USR_EFUSE30 | output | TCELL41:OUT.28 |
| USR_EFUSE31 | output | TCELL41:OUT.30 |
| USR_EFUSE4 | output | TCELL46:OUT.8 |
| USR_EFUSE5 | output | TCELL46:OUT.10 |
| USR_EFUSE6 | output | TCELL46:OUT.12 |
| USR_EFUSE7 | output | TCELL46:OUT.14 |
| USR_EFUSE8 | output | TCELL46:OUT.16 |
| USR_EFUSE9 | output | TCELL46:OUT.18 |
| USR_FCS_B_O | input | TCELL47:IMUX.IMUX.7 |
| USR_FCS_B_TS | input | TCELL47:IMUX.IMUX.8 |
| USR_GSR | input | TCELL47:IMUX.IMUX.5 |
| USR_GTS | input | TCELL47:IMUX.IMUX.6 |
| USR_TCK | input | TCELL43:IMUX.CTRL.1 |
| USR_TDI | input | TCELL43:IMUX.IMUX.6 |
| USR_TDO | output | TCELL43:OUT.18 |
| USR_TMS | input | TCELL43:IMUX.IMUX.5 |
| WDATA0 | input | TCELL28:IMUX.IMUX.10 |
| WDATA1 | input | TCELL28:IMUX.IMUX.11 |
| WDATA10 | input | TCELL29:IMUX.IMUX.4 |
| WDATA11 | input | TCELL29:IMUX.IMUX.5 |
| WDATA12 | input | TCELL29:IMUX.IMUX.6 |
| WDATA13 | input | TCELL29:IMUX.IMUX.7 |
| WDATA14 | input | TCELL29:IMUX.IMUX.8 |
| WDATA15 | input | TCELL29:IMUX.IMUX.9 |
| WDATA16 | input | TCELL29:IMUX.IMUX.10 |
| WDATA17 | input | TCELL29:IMUX.IMUX.11 |
| WDATA18 | input | TCELL29:IMUX.IMUX.12 |
| WDATA19 | input | TCELL29:IMUX.IMUX.13 |
| WDATA2 | input | TCELL28:IMUX.IMUX.12 |
| WDATA20 | input | TCELL29:IMUX.IMUX.14 |
| WDATA21 | input | TCELL29:IMUX.IMUX.15 |
| WDATA22 | input | TCELL30:IMUX.IMUX.0 |
| WDATA23 | input | TCELL30:IMUX.IMUX.1 |
| WDATA24 | input | TCELL30:IMUX.IMUX.2 |
| WDATA25 | input | TCELL30:IMUX.IMUX.3 |
| WDATA26 | input | TCELL30:IMUX.IMUX.4 |
| WDATA27 | input | TCELL30:IMUX.IMUX.5 |
| WDATA28 | input | TCELL30:IMUX.IMUX.6 |
| WDATA29 | input | TCELL30:IMUX.IMUX.7 |
| WDATA3 | input | TCELL28:IMUX.IMUX.13 |
| WDATA30 | input | TCELL30:IMUX.IMUX.8 |
| WDATA31 | input | TCELL30:IMUX.IMUX.9 |
| WDATA4 | input | TCELL28:IMUX.IMUX.14 |
| WDATA5 | input | TCELL28:IMUX.IMUX.15 |
| WDATA6 | input | TCELL29:IMUX.IMUX.0 |
| WDATA7 | input | TCELL29:IMUX.IMUX.1 |
| WDATA8 | input | TCELL29:IMUX.IMUX.2 |
| WDATA9 | input | TCELL29:IMUX.IMUX.3 |
| WID0 | input | TCELL28:IMUX.IMUX.2 |
| WID1 | input | TCELL28:IMUX.IMUX.3 |
| WID2 | input | TCELL28:IMUX.IMUX.4 |
| WID3 | input | TCELL28:IMUX.IMUX.5 |
| WID4 | input | TCELL28:IMUX.IMUX.6 |
| WID5 | input | TCELL28:IMUX.IMUX.7 |
| WID6 | input | TCELL28:IMUX.IMUX.8 |
| WID7 | input | TCELL28:IMUX.IMUX.9 |
| WLAST | input | TCELL28:IMUX.IMUX.1 |
| WREADY | output | TCELL28:OUT.0 |
| WSTRB0 | input | TCELL30:IMUX.IMUX.10 |
| WSTRB1 | input | TCELL30:IMUX.IMUX.11 |
| WSTRB2 | input | TCELL30:IMUX.IMUX.12 |
| WSTRB3 | input | TCELL30:IMUX.IMUX.13 |
| WVALID | input | TCELL28:IMUX.IMUX.0 |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL20:OUT.0 | CFG.ARREADY |
| TCELL20:IMUX.CTRL.0 | CFG.AXI_CLK |
| TCELL20:IMUX.IMUX.0 | CFG.ARVALID |
| TCELL20:IMUX.IMUX.3 | CFG.ARADDR22 |
| TCELL20:IMUX.IMUX.4 | CFG.ARADDR23 |
| TCELL20:IMUX.IMUX.5 | CFG.ARADDR24 |
| TCELL20:IMUX.IMUX.6 | CFG.ARADDR25 |
| TCELL20:IMUX.IMUX.7 | CFG.ARADDR26 |
| TCELL20:IMUX.IMUX.8 | CFG.ARADDR27 |
| TCELL20:IMUX.IMUX.9 | CFG.ARADDR0 |
| TCELL20:IMUX.IMUX.10 | CFG.ARADDR1 |
| TCELL20:IMUX.IMUX.11 | CFG.ARADDR2 |
| TCELL20:IMUX.IMUX.12 | CFG.ARADDR3 |
| TCELL20:IMUX.IMUX.13 | CFG.ARADDR4 |
| TCELL20:IMUX.IMUX.14 | CFG.ARADDR5 |
| TCELL20:IMUX.IMUX.15 | CFG.ARADDR6 |
| TCELL21:IMUX.IMUX.0 | CFG.ARADDR7 |
| TCELL21:IMUX.IMUX.1 | CFG.ARADDR8 |
| TCELL21:IMUX.IMUX.2 | CFG.ARADDR9 |
| TCELL21:IMUX.IMUX.3 | CFG.ARADDR10 |
| TCELL21:IMUX.IMUX.4 | CFG.ARADDR11 |
| TCELL21:IMUX.IMUX.5 | CFG.ARADDR12 |
| TCELL21:IMUX.IMUX.6 | CFG.ARADDR13 |
| TCELL21:IMUX.IMUX.7 | CFG.ARADDR14 |
| TCELL21:IMUX.IMUX.8 | CFG.ARADDR15 |
| TCELL21:IMUX.IMUX.9 | CFG.ARADDR16 |
| TCELL21:IMUX.IMUX.10 | CFG.ARADDR17 |
| TCELL21:IMUX.IMUX.11 | CFG.ARADDR18 |
| TCELL21:IMUX.IMUX.12 | CFG.ARADDR19 |
| TCELL21:IMUX.IMUX.13 | CFG.ARADDR20 |
| TCELL21:IMUX.IMUX.14 | CFG.ARADDR21 |
| TCELL21:IMUX.IMUX.15 | CFG.ARLEN0 |
| TCELL22:IMUX.IMUX.0 | CFG.ARLEN1 |
| TCELL22:IMUX.IMUX.1 | CFG.ARLEN2 |
| TCELL22:IMUX.IMUX.2 | CFG.ARLEN3 |
| TCELL22:IMUX.IMUX.3 | CFG.ARSIZE0 |
| TCELL22:IMUX.IMUX.4 | CFG.ARSIZE1 |
| TCELL22:IMUX.IMUX.5 | CFG.ARSIZE2 |
| TCELL22:IMUX.IMUX.6 | CFG.ARBURST0 |
| TCELL22:IMUX.IMUX.7 | CFG.ARBURST1 |
| TCELL22:IMUX.IMUX.8 | CFG.ARLOCK |
| TCELL22:IMUX.IMUX.9 | CFG.ARCACHE0 |
| TCELL22:IMUX.IMUX.10 | CFG.ARCACHE1 |
| TCELL22:IMUX.IMUX.11 | CFG.ARCACHE2 |
| TCELL22:IMUX.IMUX.12 | CFG.ARCACHE3 |
| TCELL22:IMUX.IMUX.13 | CFG.ARPROT0 |
| TCELL22:IMUX.IMUX.14 | CFG.ARPROT1 |
| TCELL22:IMUX.IMUX.15 | CFG.ARPROT2 |
| TCELL23:IMUX.IMUX.0 | CFG.ARQOS0 |
| TCELL23:IMUX.IMUX.1 | CFG.ARQOS1 |
| TCELL23:IMUX.IMUX.2 | CFG.ARQOS2 |
| TCELL23:IMUX.IMUX.3 | CFG.ARQOS3 |
| TCELL24:OUT.0 | CFG.AWREADY |
| TCELL24:IMUX.IMUX.0 | CFG.AWVALID |
| TCELL24:IMUX.IMUX.3 | CFG.AWADDR22 |
| TCELL24:IMUX.IMUX.4 | CFG.AWADDR23 |
| TCELL24:IMUX.IMUX.5 | CFG.AWADDR24 |
| TCELL24:IMUX.IMUX.6 | CFG.AWADDR25 |
| TCELL24:IMUX.IMUX.7 | CFG.AWADDR26 |
| TCELL24:IMUX.IMUX.8 | CFG.AWADDR27 |
| TCELL24:IMUX.IMUX.9 | CFG.AWADDR0 |
| TCELL24:IMUX.IMUX.10 | CFG.AWADDR1 |
| TCELL24:IMUX.IMUX.11 | CFG.AWADDR2 |
| TCELL24:IMUX.IMUX.12 | CFG.AWADDR3 |
| TCELL24:IMUX.IMUX.13 | CFG.AWADDR4 |
| TCELL24:IMUX.IMUX.14 | CFG.AWADDR5 |
| TCELL24:IMUX.IMUX.15 | CFG.AWADDR6 |
| TCELL25:IMUX.IMUX.0 | CFG.AWADDR7 |
| TCELL25:IMUX.IMUX.1 | CFG.AWADDR8 |
| TCELL25:IMUX.IMUX.2 | CFG.AWADDR9 |
| TCELL25:IMUX.IMUX.3 | CFG.AWADDR10 |
| TCELL25:IMUX.IMUX.4 | CFG.AWADDR11 |
| TCELL25:IMUX.IMUX.5 | CFG.AWADDR12 |
| TCELL25:IMUX.IMUX.6 | CFG.AWADDR13 |
| TCELL25:IMUX.IMUX.7 | CFG.AWADDR14 |
| TCELL25:IMUX.IMUX.8 | CFG.AWADDR15 |
| TCELL25:IMUX.IMUX.9 | CFG.AWADDR16 |
| TCELL25:IMUX.IMUX.10 | CFG.AWADDR17 |
| TCELL25:IMUX.IMUX.11 | CFG.AWADDR18 |
| TCELL25:IMUX.IMUX.12 | CFG.AWADDR19 |
| TCELL25:IMUX.IMUX.13 | CFG.AWADDR20 |
| TCELL25:IMUX.IMUX.14 | CFG.AWADDR21 |
| TCELL25:IMUX.IMUX.15 | CFG.AWLEN0 |
| TCELL26:IMUX.IMUX.0 | CFG.AWLEN1 |
| TCELL26:IMUX.IMUX.1 | CFG.AWLEN2 |
| TCELL26:IMUX.IMUX.2 | CFG.AWLEN3 |
| TCELL26:IMUX.IMUX.3 | CFG.AWSIZE0 |
| TCELL26:IMUX.IMUX.4 | CFG.AWSIZE1 |
| TCELL26:IMUX.IMUX.5 | CFG.AWSIZE2 |
| TCELL26:IMUX.IMUX.6 | CFG.AWBURST0 |
| TCELL26:IMUX.IMUX.7 | CFG.AWBURST1 |
| TCELL26:IMUX.IMUX.8 | CFG.AWLOCK |
| TCELL26:IMUX.IMUX.9 | CFG.AWCACHE0 |
| TCELL26:IMUX.IMUX.10 | CFG.AWCACHE1 |
| TCELL26:IMUX.IMUX.11 | CFG.AWCACHE2 |
| TCELL26:IMUX.IMUX.12 | CFG.AWCACHE3 |
| TCELL26:IMUX.IMUX.13 | CFG.AWPROT0 |
| TCELL26:IMUX.IMUX.14 | CFG.AWPROT1 |
| TCELL26:IMUX.IMUX.15 | CFG.AWPROT2 |
| TCELL27:IMUX.IMUX.0 | CFG.AWQOS0 |
| TCELL27:IMUX.IMUX.1 | CFG.AWQOS1 |
| TCELL27:IMUX.IMUX.2 | CFG.AWQOS2 |
| TCELL27:IMUX.IMUX.3 | CFG.AWQOS3 |
| TCELL28:OUT.0 | CFG.WREADY |
| TCELL28:IMUX.IMUX.0 | CFG.WVALID |
| TCELL28:IMUX.IMUX.1 | CFG.WLAST |
| TCELL28:IMUX.IMUX.2 | CFG.WID0 |
| TCELL28:IMUX.IMUX.3 | CFG.WID1 |
| TCELL28:IMUX.IMUX.4 | CFG.WID2 |
| TCELL28:IMUX.IMUX.5 | CFG.WID3 |
| TCELL28:IMUX.IMUX.6 | CFG.WID4 |
| TCELL28:IMUX.IMUX.7 | CFG.WID5 |
| TCELL28:IMUX.IMUX.8 | CFG.WID6 |
| TCELL28:IMUX.IMUX.9 | CFG.WID7 |
| TCELL28:IMUX.IMUX.10 | CFG.WDATA0 |
| TCELL28:IMUX.IMUX.11 | CFG.WDATA1 |
| TCELL28:IMUX.IMUX.12 | CFG.WDATA2 |
| TCELL28:IMUX.IMUX.13 | CFG.WDATA3 |
| TCELL28:IMUX.IMUX.14 | CFG.WDATA4 |
| TCELL28:IMUX.IMUX.15 | CFG.WDATA5 |
| TCELL29:IMUX.IMUX.0 | CFG.WDATA6 |
| TCELL29:IMUX.IMUX.1 | CFG.WDATA7 |
| TCELL29:IMUX.IMUX.2 | CFG.WDATA8 |
| TCELL29:IMUX.IMUX.3 | CFG.WDATA9 |
| TCELL29:IMUX.IMUX.4 | CFG.WDATA10 |
| TCELL29:IMUX.IMUX.5 | CFG.WDATA11 |
| TCELL29:IMUX.IMUX.6 | CFG.WDATA12 |
| TCELL29:IMUX.IMUX.7 | CFG.WDATA13 |
| TCELL29:IMUX.IMUX.8 | CFG.WDATA14 |
| TCELL29:IMUX.IMUX.9 | CFG.WDATA15 |
| TCELL29:IMUX.IMUX.10 | CFG.WDATA16 |
| TCELL29:IMUX.IMUX.11 | CFG.WDATA17 |
| TCELL29:IMUX.IMUX.12 | CFG.WDATA18 |
| TCELL29:IMUX.IMUX.13 | CFG.WDATA19 |
| TCELL29:IMUX.IMUX.14 | CFG.WDATA20 |
| TCELL29:IMUX.IMUX.15 | CFG.WDATA21 |
| TCELL30:IMUX.IMUX.0 | CFG.WDATA22 |
| TCELL30:IMUX.IMUX.1 | CFG.WDATA23 |
| TCELL30:IMUX.IMUX.2 | CFG.WDATA24 |
| TCELL30:IMUX.IMUX.3 | CFG.WDATA25 |
| TCELL30:IMUX.IMUX.4 | CFG.WDATA26 |
| TCELL30:IMUX.IMUX.5 | CFG.WDATA27 |
| TCELL30:IMUX.IMUX.6 | CFG.WDATA28 |
| TCELL30:IMUX.IMUX.7 | CFG.WDATA29 |
| TCELL30:IMUX.IMUX.8 | CFG.WDATA30 |
| TCELL30:IMUX.IMUX.9 | CFG.WDATA31 |
| TCELL30:IMUX.IMUX.10 | CFG.WSTRB0 |
| TCELL30:IMUX.IMUX.11 | CFG.WSTRB1 |
| TCELL30:IMUX.IMUX.12 | CFG.WSTRB2 |
| TCELL30:IMUX.IMUX.13 | CFG.WSTRB3 |
| TCELL31:OUT.0 | CFG.RVALID |
| TCELL31:OUT.2 | CFG.RLAST |
| TCELL31:OUT.4 | CFG.RID0 |
| TCELL31:OUT.6 | CFG.RID1 |
| TCELL31:OUT.8 | CFG.RID2 |
| TCELL31:OUT.10 | CFG.RID3 |
| TCELL31:OUT.12 | CFG.RID4 |
| TCELL31:OUT.14 | CFG.RID5 |
| TCELL31:OUT.16 | CFG.RID6 |
| TCELL31:OUT.18 | CFG.RID7 |
| TCELL31:OUT.20 | CFG.RRESP0 |
| TCELL31:OUT.22 | CFG.RRESP1 |
| TCELL31:OUT.24 | CFG.RDATA0 |
| TCELL31:OUT.26 | CFG.RDATA1 |
| TCELL31:OUT.28 | CFG.RDATA2 |
| TCELL31:OUT.30 | CFG.RDATA3 |
| TCELL31:IMUX.IMUX.0 | CFG.RREADY |
| TCELL31:IMUX.IMUX.1 | CFG.ARID0 |
| TCELL31:IMUX.IMUX.2 | CFG.ARID1 |
| TCELL31:IMUX.IMUX.3 | CFG.ARID2 |
| TCELL31:IMUX.IMUX.4 | CFG.ARID3 |
| TCELL31:IMUX.IMUX.5 | CFG.ARID4 |
| TCELL31:IMUX.IMUX.6 | CFG.ARID5 |
| TCELL31:IMUX.IMUX.7 | CFG.ARID6 |
| TCELL31:IMUX.IMUX.8 | CFG.ARID7 |
| TCELL32:OUT.0 | CFG.RDATA4 |
| TCELL32:OUT.2 | CFG.RDATA5 |
| TCELL32:OUT.4 | CFG.RDATA6 |
| TCELL32:OUT.6 | CFG.RDATA7 |
| TCELL32:OUT.8 | CFG.RDATA8 |
| TCELL32:OUT.10 | CFG.RDATA9 |
| TCELL32:OUT.12 | CFG.RDATA10 |
| TCELL32:OUT.14 | CFG.RDATA11 |
| TCELL32:OUT.16 | CFG.RDATA12 |
| TCELL32:OUT.18 | CFG.RDATA13 |
| TCELL32:OUT.20 | CFG.RDATA14 |
| TCELL32:OUT.22 | CFG.RDATA15 |
| TCELL32:OUT.24 | CFG.RDATA16 |
| TCELL32:OUT.26 | CFG.RDATA17 |
| TCELL32:OUT.28 | CFG.RDATA18 |
| TCELL32:OUT.30 | CFG.RDATA19 |
| TCELL32:IMUX.IMUX.1 | CFG.AWID0 |
| TCELL32:IMUX.IMUX.2 | CFG.AWID1 |
| TCELL32:IMUX.IMUX.3 | CFG.AWID2 |
| TCELL32:IMUX.IMUX.4 | CFG.AWID3 |
| TCELL32:IMUX.IMUX.5 | CFG.AWID4 |
| TCELL32:IMUX.IMUX.6 | CFG.AWID5 |
| TCELL32:IMUX.IMUX.7 | CFG.AWID6 |
| TCELL32:IMUX.IMUX.8 | CFG.AWID7 |
| TCELL33:OUT.0 | CFG.RDATA20 |
| TCELL33:OUT.2 | CFG.RDATA21 |
| TCELL33:OUT.4 | CFG.RDATA22 |
| TCELL33:OUT.6 | CFG.RDATA23 |
| TCELL33:OUT.8 | CFG.RDATA24 |
| TCELL33:OUT.10 | CFG.RDATA25 |
| TCELL33:OUT.12 | CFG.RDATA26 |
| TCELL33:OUT.14 | CFG.RDATA27 |
| TCELL33:OUT.16 | CFG.RDATA28 |
| TCELL33:OUT.18 | CFG.RDATA29 |
| TCELL33:OUT.20 | CFG.RDATA30 |
| TCELL33:OUT.22 | CFG.RDATA31 |
| TCELL34:OUT.0 | CFG.BVALID |
| TCELL34:OUT.2 | CFG.BID0 |
| TCELL34:OUT.4 | CFG.BID1 |
| TCELL34:OUT.6 | CFG.BID2 |
| TCELL34:OUT.8 | CFG.BID3 |
| TCELL34:OUT.10 | CFG.BID4 |
| TCELL34:OUT.12 | CFG.BID5 |
| TCELL34:OUT.14 | CFG.BID6 |
| TCELL34:OUT.16 | CFG.BID7 |
| TCELL34:OUT.18 | CFG.BRESP0 |
| TCELL34:OUT.20 | CFG.BRESP1 |
| TCELL34:IMUX.IMUX.0 | CFG.BREADY |
| TCELL41:OUT.0 | CFG.USR_EFUSE16 |
| TCELL41:OUT.2 | CFG.USR_EFUSE17 |
| TCELL41:OUT.4 | CFG.USR_EFUSE18 |
| TCELL41:OUT.6 | CFG.USR_EFUSE19 |
| TCELL41:OUT.8 | CFG.USR_EFUSE20 |
| TCELL41:OUT.10 | CFG.USR_EFUSE21 |
| TCELL41:OUT.12 | CFG.USR_EFUSE22 |
| TCELL41:OUT.14 | CFG.USR_EFUSE23 |
| TCELL41:OUT.16 | CFG.USR_EFUSE24 |
| TCELL41:OUT.18 | CFG.USR_EFUSE25 |
| TCELL41:OUT.20 | CFG.USR_EFUSE26 |
| TCELL41:OUT.22 | CFG.USR_EFUSE27 |
| TCELL41:OUT.24 | CFG.USR_EFUSE28 |
| TCELL41:OUT.26 | CFG.USR_EFUSE29 |
| TCELL41:OUT.28 | CFG.USR_EFUSE30 |
| TCELL41:OUT.30 | CFG.USR_EFUSE31 |
| TCELL42:OUT.0 | CFG.USR_DNA_OUT |
| TCELL42:OUT.2 | CFG.DCI_LOCK |
| TCELL42:OUT.4 | CFG.BSCAN_CDR1 |
| TCELL42:OUT.6 | CFG.BSCAN_CDR2 |
| TCELL42:OUT.8 | CFG.BSCAN_CLKDR1 |
| TCELL42:OUT.10 | CFG.BSCAN_CLKDR2 |
| TCELL42:OUT.12 | CFG.BSCAN_RTI1 |
| TCELL42:OUT.14 | CFG.BSCAN_RTI2 |
| TCELL42:OUT.16 | CFG.BSCAN_SDR1 |
| TCELL42:OUT.18 | CFG.BSCAN_SDR2 |
| TCELL42:OUT.20 | CFG.BSCAN_SEL1 |
| TCELL42:OUT.22 | CFG.BSCAN_SEL2 |
| TCELL42:OUT.24 | CFG.BSCAN_TLR1 |
| TCELL42:OUT.26 | CFG.BSCAN_TLR2 |
| TCELL42:OUT.28 | CFG.BSCAN_UDR1 |
| TCELL42:OUT.30 | CFG.BSCAN_UDR2 |
| TCELL42:IMUX.CTRL.0 | CFG.USR_DNA_CLK |
| TCELL42:IMUX.IMUX.0 | CFG.USR_DNA_DIN |
| TCELL42:IMUX.IMUX.1 | CFG.USR_DNA_READ |
| TCELL42:IMUX.IMUX.2 | CFG.USR_DNA_SHIFT |
| TCELL42:IMUX.IMUX.3 | CFG.DCI_USR_RESET_IN |
| TCELL43:OUT.0 | CFG.ICAP_PR_DONE_BOT |
| TCELL43:OUT.2 | CFG.ICAP_PR_ERROR_BOT |
| TCELL43:OUT.4 | CFG.ICAP_AVAIL_BOT |
| TCELL43:OUT.6 | CFG.BSCAN_TCK1 |
| TCELL43:OUT.8 | CFG.BSCAN_TCK2 |
| TCELL43:OUT.10 | CFG.BSCAN_TMS1 |
| TCELL43:OUT.12 | CFG.BSCAN_TMS2 |
| TCELL43:OUT.14 | CFG.BSCAN_TDI1 |
| TCELL43:OUT.16 | CFG.BSCAN_TDI2 |
| TCELL43:OUT.18 | CFG.USR_TDO |
| TCELL43:IMUX.CTRL.1 | CFG.USR_TCK |
| TCELL43:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_BOT |
| TCELL43:IMUX.IMUX.1 | CFG.ICAP_CS_B_BOT |
| TCELL43:IMUX.IMUX.2 | CFG.BSCAN_TDO1 |
| TCELL43:IMUX.IMUX.3 | CFG.BSCAN_TDO2 |
| TCELL43:IMUX.IMUX.5 | CFG.USR_TMS |
| TCELL43:IMUX.IMUX.6 | CFG.USR_TDI |
| TCELL44:OUT.0 | CFG.ICAP_OUT_BOT0 |
| TCELL44:OUT.2 | CFG.ICAP_OUT_BOT1 |
| TCELL44:OUT.4 | CFG.ICAP_OUT_BOT2 |
| TCELL44:OUT.6 | CFG.ICAP_OUT_BOT3 |
| TCELL44:OUT.8 | CFG.ICAP_OUT_BOT4 |
| TCELL44:OUT.10 | CFG.ICAP_OUT_BOT5 |
| TCELL44:OUT.12 | CFG.ICAP_OUT_BOT6 |
| TCELL44:OUT.14 | CFG.ICAP_OUT_BOT7 |
| TCELL44:OUT.16 | CFG.ICAP_OUT_BOT8 |
| TCELL44:OUT.18 | CFG.ICAP_OUT_BOT9 |
| TCELL44:OUT.20 | CFG.ICAP_OUT_BOT10 |
| TCELL44:OUT.22 | CFG.ICAP_OUT_BOT11 |
| TCELL44:OUT.24 | CFG.ICAP_OUT_BOT12 |
| TCELL44:OUT.26 | CFG.ICAP_OUT_BOT13 |
| TCELL44:OUT.28 | CFG.ICAP_OUT_BOT14 |
| TCELL44:OUT.30 | CFG.ICAP_OUT_BOT15 |
| TCELL44:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT0 |
| TCELL44:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT1 |
| TCELL44:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT2 |
| TCELL44:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT3 |
| TCELL44:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT4 |
| TCELL44:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT5 |
| TCELL44:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT6 |
| TCELL44:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT7 |
| TCELL44:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT8 |
| TCELL44:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT9 |
| TCELL44:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT10 |
| TCELL44:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT11 |
| TCELL44:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT12 |
| TCELL44:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT13 |
| TCELL44:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT14 |
| TCELL44:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT15 |
| TCELL45:OUT.0 | CFG.ICAP_OUT_BOT16 |
| TCELL45:OUT.2 | CFG.ICAP_OUT_BOT17 |
| TCELL45:OUT.4 | CFG.ICAP_OUT_BOT18 |
| TCELL45:OUT.6 | CFG.ICAP_OUT_BOT19 |
| TCELL45:OUT.8 | CFG.ICAP_OUT_BOT20 |
| TCELL45:OUT.10 | CFG.ICAP_OUT_BOT21 |
| TCELL45:OUT.12 | CFG.ICAP_OUT_BOT22 |
| TCELL45:OUT.14 | CFG.ICAP_OUT_BOT23 |
| TCELL45:OUT.16 | CFG.ICAP_OUT_BOT24 |
| TCELL45:OUT.18 | CFG.ICAP_OUT_BOT25 |
| TCELL45:OUT.20 | CFG.ICAP_OUT_BOT26 |
| TCELL45:OUT.22 | CFG.ICAP_OUT_BOT27 |
| TCELL45:OUT.24 | CFG.ICAP_OUT_BOT28 |
| TCELL45:OUT.26 | CFG.ICAP_OUT_BOT29 |
| TCELL45:OUT.28 | CFG.ICAP_OUT_BOT30 |
| TCELL45:OUT.30 | CFG.ICAP_OUT_BOT31 |
| TCELL45:IMUX.CTRL.0 | CFG.ICAP_CLK_BOT |
| TCELL45:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT16 |
| TCELL45:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT17 |
| TCELL45:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT18 |
| TCELL45:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT19 |
| TCELL45:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT20 |
| TCELL45:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT21 |
| TCELL45:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT22 |
| TCELL45:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT23 |
| TCELL45:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT24 |
| TCELL45:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT25 |
| TCELL45:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT26 |
| TCELL45:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT27 |
| TCELL45:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT28 |
| TCELL45:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT29 |
| TCELL45:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT30 |
| TCELL45:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT31 |
| TCELL46:OUT.0 | CFG.USR_EFUSE0 |
| TCELL46:OUT.2 | CFG.USR_EFUSE1 |
| TCELL46:OUT.4 | CFG.USR_EFUSE2 |
| TCELL46:OUT.6 | CFG.USR_EFUSE3 |
| TCELL46:OUT.8 | CFG.USR_EFUSE4 |
| TCELL46:OUT.10 | CFG.USR_EFUSE5 |
| TCELL46:OUT.12 | CFG.USR_EFUSE6 |
| TCELL46:OUT.14 | CFG.USR_EFUSE7 |
| TCELL46:OUT.16 | CFG.USR_EFUSE8 |
| TCELL46:OUT.18 | CFG.USR_EFUSE9 |
| TCELL46:OUT.20 | CFG.USR_EFUSE10 |
| TCELL46:OUT.22 | CFG.USR_EFUSE11 |
| TCELL46:OUT.24 | CFG.USR_EFUSE12 |
| TCELL46:OUT.26 | CFG.USR_EFUSE13 |
| TCELL46:OUT.28 | CFG.USR_EFUSE14 |
| TCELL46:OUT.30 | CFG.USR_EFUSE15 |
| TCELL47:OUT.0 | CFG.USR_D_PIN_CFGIO0 |
| TCELL47:OUT.2 | CFG.USR_D_PIN_CFGIO1 |
| TCELL47:OUT.4 | CFG.USR_D_PIN_CFGIO2 |
| TCELL47:OUT.6 | CFG.USR_D_PIN_CFGIO3 |
| TCELL47:OUT.8 | CFG.PROG_REQ |
| TCELL47:OUT.10 | CFG.EOS |
| TCELL47:OUT.12 | CFG.START_CFG_MCLK |
| TCELL47:OUT.14 | CFG.START_CFG_CLK |
| TCELL47:IMUX.CTRL.0 | CFG.USR_CCLK_O |
| TCELL47:IMUX.IMUX.0 | CFG.KEY_CLEAR_B |
| TCELL47:IMUX.IMUX.1 | CFG.PROG_ACK |
| TCELL47:IMUX.IMUX.2 | CFG.USR_CCLK_TS |
| TCELL47:IMUX.IMUX.3 | CFG.USR_DONE_O |
| TCELL47:IMUX.IMUX.4 | CFG.USR_DONE_TS |
| TCELL47:IMUX.IMUX.5 | CFG.USR_GSR |
| TCELL47:IMUX.IMUX.6 | CFG.USR_GTS |
| TCELL47:IMUX.IMUX.7 | CFG.USR_FCS_B_O |
| TCELL47:IMUX.IMUX.8 | CFG.USR_FCS_B_TS |
| TCELL47:IMUX.IMUX.9 | CFG.USR_D_O_CFGIO0 |
| TCELL47:IMUX.IMUX.10 | CFG.USR_D_O_CFGIO1 |
| TCELL47:IMUX.IMUX.11 | CFG.USR_D_O_CFGIO2 |
| TCELL47:IMUX.IMUX.12 | CFG.USR_D_O_CFGIO3 |
| TCELL47:IMUX.IMUX.13 | CFG.USR_D_TS_CFGIO0 |
| TCELL47:IMUX.IMUX.14 | CFG.USR_D_TS_CFGIO1 |
| TCELL47:IMUX.IMUX.15 | CFG.USR_D_TS_CFGIO2 |
| TCELL47:IMUX.IMUX.16 | CFG.USR_D_TS_CFGIO3 |
| TCELL48:OUT.0 | CFG.IOX_CFGDATA0 |
| TCELL48:OUT.2 | CFG.IOX_CFGDATA1 |
| TCELL48:OUT.4 | CFG.IOX_CFGDATA2 |
| TCELL48:OUT.6 | CFG.IOX_CFGDATA3 |
| TCELL48:OUT.8 | CFG.IOX_CFGDATA4 |
| TCELL48:OUT.10 | CFG.IOX_CFGDATA5 |
| TCELL48:OUT.12 | CFG.IOX_CFGDATA6 |
| TCELL48:OUT.14 | CFG.IOX_CFGDATA7 |
| TCELL48:OUT.16 | CFG.IOX_CFGDATA8 |
| TCELL48:OUT.18 | CFG.IOX_CFGDATA9 |
| TCELL48:OUT.20 | CFG.IOX_CFGDATA10 |
| TCELL48:OUT.22 | CFG.IOX_CFGDATA11 |
| TCELL48:OUT.24 | CFG.IOX_CFGDATA12 |
| TCELL48:OUT.26 | CFG.IOX_CFGDATA13 |
| TCELL48:OUT.28 | CFG.IOX_CFGDATA14 |
| TCELL48:OUT.30 | CFG.IOX_CFGDATA15 |
| TCELL48:IMUX.IMUX.0 | CFG.IOX_TDO |
| TCELL48:IMUX.IMUX.1 | CFG.IOX_INITBO |
| TCELL49:OUT.0 | CFG.IOX_CFGDATA16 |
| TCELL49:OUT.2 | CFG.IOX_CFGDATA17 |
| TCELL49:OUT.4 | CFG.IOX_CFGDATA18 |
| TCELL49:OUT.6 | CFG.IOX_CFGDATA19 |
| TCELL49:OUT.8 | CFG.IOX_CFGDATA20 |
| TCELL49:OUT.10 | CFG.IOX_CFGDATA21 |
| TCELL49:OUT.12 | CFG.IOX_CFGDATA22 |
| TCELL49:OUT.14 | CFG.IOX_CFGDATA23 |
| TCELL49:OUT.16 | CFG.IOX_CFGDATA24 |
| TCELL49:OUT.18 | CFG.IOX_CFGDATA25 |
| TCELL49:OUT.20 | CFG.IOX_CFGDATA26 |
| TCELL49:OUT.22 | CFG.IOX_CFGDATA27 |
| TCELL49:OUT.24 | CFG.IOX_CFGDATA28 |
| TCELL49:OUT.26 | CFG.IOX_CFGDATA29 |
| TCELL49:OUT.28 | CFG.IOX_CFGDATA30 |
| TCELL49:OUT.30 | CFG.IOX_CFGDATA31 |
| TCELL50:OUT.0 | CFG.IOX_CCLK |
| TCELL50:OUT.2 | CFG.IOX_CFGMASTER |
| TCELL50:OUT.4 | CFG.IOX_VGG_COMP_OUT |
| TCELL50:OUT.6 | CFG.IOX_INITBI |
| TCELL50:OUT.8 | CFG.IOX_PUDCB |
| TCELL50:OUT.10 | CFG.IOX_RDWRB |
| TCELL50:OUT.12 | CFG.IOX_MODE0 |
| TCELL50:OUT.14 | CFG.IOX_MODE1 |
| TCELL50:OUT.16 | CFG.IOX_MODE2 |
| TCELL51:OUT.0 | CFG.ECC_FAR16 |
| TCELL51:OUT.2 | CFG.ECC_FAR17 |
| TCELL51:OUT.4 | CFG.ECC_FAR18 |
| TCELL51:OUT.6 | CFG.ECC_FAR19 |
| TCELL51:OUT.8 | CFG.ECC_FAR20 |
| TCELL51:OUT.10 | CFG.ECC_FAR21 |
| TCELL51:OUT.12 | CFG.ECC_FAR22 |
| TCELL51:OUT.14 | CFG.ECC_FAR23 |
| TCELL51:OUT.16 | CFG.ECC_FAR24 |
| TCELL51:OUT.18 | CFG.ECC_FAR25 |
| TCELL51:OUT.20 | CFG.RBCRC_ERROR |
| TCELL51:OUT.22 | CFG.ECC_ERROR_NOTSINGLE |
| TCELL51:OUT.24 | CFG.ECC_ERROR_SINGLE |
| TCELL51:OUT.26 | CFG.ECC_END_OF_FRAME |
| TCELL51:OUT.28 | CFG.ECC_END_OF_SCAN |
| TCELL51:IMUX.IMUX.15 | CFG.ECC_FAR_SEL0 |
| TCELL51:IMUX.IMUX.16 | CFG.ECC_FAR_SEL1 |
| TCELL52:OUT.0 | CFG.ECC_FAR0 |
| TCELL52:OUT.2 | CFG.ECC_FAR1 |
| TCELL52:OUT.4 | CFG.ECC_FAR2 |
| TCELL52:OUT.6 | CFG.ECC_FAR3 |
| TCELL52:OUT.8 | CFG.ECC_FAR4 |
| TCELL52:OUT.10 | CFG.ECC_FAR5 |
| TCELL52:OUT.12 | CFG.ECC_FAR6 |
| TCELL52:OUT.14 | CFG.ECC_FAR7 |
| TCELL52:OUT.16 | CFG.ECC_FAR8 |
| TCELL52:OUT.18 | CFG.ECC_FAR9 |
| TCELL52:OUT.20 | CFG.ECC_FAR10 |
| TCELL52:OUT.22 | CFG.ECC_FAR11 |
| TCELL52:OUT.24 | CFG.ECC_FAR12 |
| TCELL52:OUT.26 | CFG.ECC_FAR13 |
| TCELL52:OUT.28 | CFG.ECC_FAR14 |
| TCELL52:OUT.30 | CFG.ECC_FAR15 |
| TCELL52:OUT.31 | CFG.ECC_FAR26 |
| TCELL53:OUT.0 | CFG.BSCAN_SDR3 |
| TCELL53:OUT.2 | CFG.BSCAN_SDR4 |
| TCELL53:OUT.4 | CFG.BSCAN_SEL3 |
| TCELL53:OUT.6 | CFG.BSCAN_SEL4 |
| TCELL53:OUT.8 | CFG.BSCAN_TLR3 |
| TCELL53:OUT.10 | CFG.BSCAN_TLR4 |
| TCELL53:OUT.12 | CFG.BSCAN_UDR3 |
| TCELL53:OUT.14 | CFG.BSCAN_UDR4 |
| TCELL54:OUT.0 | CFG.ICAP_PR_DONE_TOP |
| TCELL54:OUT.2 | CFG.ICAP_PR_ERROR_TOP |
| TCELL54:OUT.4 | CFG.ICAP_AVAIL_TOP |
| TCELL54:OUT.6 | CFG.BSCAN_TCK3 |
| TCELL54:OUT.8 | CFG.BSCAN_TCK4 |
| TCELL54:OUT.10 | CFG.BSCAN_TMS3 |
| TCELL54:OUT.12 | CFG.BSCAN_TMS4 |
| TCELL54:OUT.14 | CFG.BSCAN_TDI3 |
| TCELL54:OUT.16 | CFG.BSCAN_TDI4 |
| TCELL54:OUT.18 | CFG.BSCAN_CDR3 |
| TCELL54:OUT.20 | CFG.BSCAN_CDR4 |
| TCELL54:OUT.22 | CFG.BSCAN_CLKDR3 |
| TCELL54:OUT.24 | CFG.BSCAN_CLKDR4 |
| TCELL54:OUT.26 | CFG.BSCAN_RTI3 |
| TCELL54:OUT.28 | CFG.BSCAN_RTI4 |
| TCELL54:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_TOP |
| TCELL54:IMUX.IMUX.1 | CFG.ICAP_CS_B_TOP |
| TCELL54:IMUX.IMUX.2 | CFG.BSCAN_TDO3 |
| TCELL54:IMUX.IMUX.3 | CFG.BSCAN_TDO4 |
| TCELL55:OUT.0 | CFG.ICAP_OUT_TOP0 |
| TCELL55:OUT.2 | CFG.ICAP_OUT_TOP1 |
| TCELL55:OUT.4 | CFG.ICAP_OUT_TOP2 |
| TCELL55:OUT.6 | CFG.ICAP_OUT_TOP3 |
| TCELL55:OUT.8 | CFG.ICAP_OUT_TOP4 |
| TCELL55:OUT.10 | CFG.ICAP_OUT_TOP5 |
| TCELL55:OUT.12 | CFG.ICAP_OUT_TOP6 |
| TCELL55:OUT.14 | CFG.ICAP_OUT_TOP7 |
| TCELL55:OUT.16 | CFG.ICAP_OUT_TOP8 |
| TCELL55:OUT.18 | CFG.ICAP_OUT_TOP9 |
| TCELL55:OUT.20 | CFG.ICAP_OUT_TOP10 |
| TCELL55:OUT.22 | CFG.ICAP_OUT_TOP11 |
| TCELL55:OUT.24 | CFG.ICAP_OUT_TOP12 |
| TCELL55:OUT.26 | CFG.ICAP_OUT_TOP13 |
| TCELL55:OUT.28 | CFG.ICAP_OUT_TOP14 |
| TCELL55:OUT.30 | CFG.ICAP_OUT_TOP15 |
| TCELL55:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP0 |
| TCELL55:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP1 |
| TCELL55:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP2 |
| TCELL55:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP3 |
| TCELL55:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP4 |
| TCELL55:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP5 |
| TCELL55:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP6 |
| TCELL55:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP7 |
| TCELL55:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP8 |
| TCELL55:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP9 |
| TCELL55:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP10 |
| TCELL55:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP11 |
| TCELL55:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP12 |
| TCELL55:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP13 |
| TCELL55:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP14 |
| TCELL55:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP15 |
| TCELL56:OUT.0 | CFG.ICAP_OUT_TOP16 |
| TCELL56:OUT.2 | CFG.ICAP_OUT_TOP17 |
| TCELL56:OUT.4 | CFG.ICAP_OUT_TOP18 |
| TCELL56:OUT.6 | CFG.ICAP_OUT_TOP19 |
| TCELL56:OUT.8 | CFG.ICAP_OUT_TOP20 |
| TCELL56:OUT.10 | CFG.ICAP_OUT_TOP21 |
| TCELL56:OUT.12 | CFG.ICAP_OUT_TOP22 |
| TCELL56:OUT.14 | CFG.ICAP_OUT_TOP23 |
| TCELL56:OUT.16 | CFG.ICAP_OUT_TOP24 |
| TCELL56:OUT.18 | CFG.ICAP_OUT_TOP25 |
| TCELL56:OUT.20 | CFG.ICAP_OUT_TOP26 |
| TCELL56:OUT.22 | CFG.ICAP_OUT_TOP27 |
| TCELL56:OUT.24 | CFG.ICAP_OUT_TOP28 |
| TCELL56:OUT.26 | CFG.ICAP_OUT_TOP29 |
| TCELL56:OUT.28 | CFG.ICAP_OUT_TOP30 |
| TCELL56:OUT.30 | CFG.ICAP_OUT_TOP31 |
| TCELL56:IMUX.CTRL.0 | CFG.ICAP_CLK_TOP |
| TCELL56:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP16 |
| TCELL56:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP17 |
| TCELL56:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP18 |
| TCELL56:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP19 |
| TCELL56:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP20 |
| TCELL56:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP21 |
| TCELL56:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP22 |
| TCELL56:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP23 |
| TCELL56:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP24 |
| TCELL56:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP25 |
| TCELL56:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP26 |
| TCELL56:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP27 |
| TCELL56:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP28 |
| TCELL56:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP29 |
| TCELL56:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP30 |
| TCELL56:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP31 |
| TCELL57:OUT.0 | CFG.USR_ACCESS_VALID |
| TCELL57:OUT.2 | CFG.USR_ACCESS_CLK |
| TCELL58:OUT.0 | CFG.USR_ACCESS_DATA0 |
| TCELL58:OUT.2 | CFG.USR_ACCESS_DATA1 |
| TCELL58:OUT.4 | CFG.USR_ACCESS_DATA2 |
| TCELL58:OUT.6 | CFG.USR_ACCESS_DATA3 |
| TCELL58:OUT.8 | CFG.USR_ACCESS_DATA4 |
| TCELL58:OUT.10 | CFG.USR_ACCESS_DATA5 |
| TCELL58:OUT.12 | CFG.USR_ACCESS_DATA6 |
| TCELL58:OUT.14 | CFG.USR_ACCESS_DATA7 |
| TCELL58:OUT.16 | CFG.USR_ACCESS_DATA8 |
| TCELL58:OUT.18 | CFG.USR_ACCESS_DATA9 |
| TCELL58:OUT.20 | CFG.USR_ACCESS_DATA10 |
| TCELL58:OUT.22 | CFG.USR_ACCESS_DATA11 |
| TCELL58:OUT.24 | CFG.USR_ACCESS_DATA12 |
| TCELL58:OUT.26 | CFG.USR_ACCESS_DATA13 |
| TCELL58:OUT.28 | CFG.USR_ACCESS_DATA14 |
| TCELL58:OUT.30 | CFG.USR_ACCESS_DATA15 |
| TCELL59:OUT.0 | CFG.USR_ACCESS_DATA16 |
| TCELL59:OUT.2 | CFG.USR_ACCESS_DATA17 |
| TCELL59:OUT.4 | CFG.USR_ACCESS_DATA18 |
| TCELL59:OUT.6 | CFG.USR_ACCESS_DATA19 |
| TCELL59:OUT.8 | CFG.USR_ACCESS_DATA20 |
| TCELL59:OUT.10 | CFG.USR_ACCESS_DATA21 |
| TCELL59:OUT.12 | CFG.USR_ACCESS_DATA22 |
| TCELL59:OUT.14 | CFG.USR_ACCESS_DATA23 |
| TCELL59:OUT.16 | CFG.USR_ACCESS_DATA24 |
| TCELL59:OUT.18 | CFG.USR_ACCESS_DATA25 |
| TCELL59:OUT.20 | CFG.USR_ACCESS_DATA26 |
| TCELL59:OUT.22 | CFG.USR_ACCESS_DATA27 |
| TCELL59:OUT.24 | CFG.USR_ACCESS_DATA28 |
| TCELL59:OUT.26 | CFG.USR_ACCESS_DATA29 |
| TCELL59:OUT.28 | CFG.USR_ACCESS_DATA30 |
| TCELL59:OUT.30 | CFG.USR_ACCESS_DATA31 |
Tile CFG_CSEC_V2
Cells: 60 IRIs: 0
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| ARADDR0 | input | TCELL20:IMUX.IMUX.9 |
| ARADDR1 | input | TCELL20:IMUX.IMUX.10 |
| ARADDR10 | input | TCELL21:IMUX.IMUX.3 |
| ARADDR11 | input | TCELL21:IMUX.IMUX.4 |
| ARADDR12 | input | TCELL21:IMUX.IMUX.5 |
| ARADDR13 | input | TCELL21:IMUX.IMUX.6 |
| ARADDR14 | input | TCELL21:IMUX.IMUX.7 |
| ARADDR15 | input | TCELL21:IMUX.IMUX.8 |
| ARADDR16 | input | TCELL21:IMUX.IMUX.9 |
| ARADDR17 | input | TCELL21:IMUX.IMUX.10 |
| ARADDR18 | input | TCELL21:IMUX.IMUX.11 |
| ARADDR19 | input | TCELL21:IMUX.IMUX.12 |
| ARADDR2 | input | TCELL20:IMUX.IMUX.11 |
| ARADDR20 | input | TCELL21:IMUX.IMUX.13 |
| ARADDR21 | input | TCELL21:IMUX.IMUX.14 |
| ARADDR22 | input | TCELL20:IMUX.IMUX.3 |
| ARADDR23 | input | TCELL20:IMUX.IMUX.4 |
| ARADDR24 | input | TCELL20:IMUX.IMUX.5 |
| ARADDR25 | input | TCELL20:IMUX.IMUX.6 |
| ARADDR26 | input | TCELL20:IMUX.IMUX.7 |
| ARADDR27 | input | TCELL20:IMUX.IMUX.8 |
| ARADDR3 | input | TCELL20:IMUX.IMUX.12 |
| ARADDR4 | input | TCELL20:IMUX.IMUX.13 |
| ARADDR5 | input | TCELL20:IMUX.IMUX.14 |
| ARADDR6 | input | TCELL20:IMUX.IMUX.15 |
| ARADDR7 | input | TCELL21:IMUX.IMUX.0 |
| ARADDR8 | input | TCELL21:IMUX.IMUX.1 |
| ARADDR9 | input | TCELL21:IMUX.IMUX.2 |
| ARBURST0 | input | TCELL22:IMUX.IMUX.6 |
| ARBURST1 | input | TCELL22:IMUX.IMUX.7 |
| ARCACHE0 | input | TCELL22:IMUX.IMUX.9 |
| ARCACHE1 | input | TCELL22:IMUX.IMUX.10 |
| ARCACHE2 | input | TCELL22:IMUX.IMUX.11 |
| ARCACHE3 | input | TCELL22:IMUX.IMUX.12 |
| ARID0 | input | TCELL31:IMUX.IMUX.1 |
| ARID1 | input | TCELL31:IMUX.IMUX.2 |
| ARID2 | input | TCELL31:IMUX.IMUX.3 |
| ARID3 | input | TCELL31:IMUX.IMUX.4 |
| ARID4 | input | TCELL31:IMUX.IMUX.5 |
| ARID5 | input | TCELL31:IMUX.IMUX.6 |
| ARID6 | input | TCELL31:IMUX.IMUX.7 |
| ARID7 | input | TCELL31:IMUX.IMUX.8 |
| ARLEN0 | input | TCELL21:IMUX.IMUX.15 |
| ARLEN1 | input | TCELL22:IMUX.IMUX.0 |
| ARLEN2 | input | TCELL22:IMUX.IMUX.1 |
| ARLEN3 | input | TCELL22:IMUX.IMUX.2 |
| ARLOCK | input | TCELL22:IMUX.IMUX.8 |
| ARPROT0 | input | TCELL22:IMUX.IMUX.13 |
| ARPROT1 | input | TCELL22:IMUX.IMUX.14 |
| ARPROT2 | input | TCELL22:IMUX.IMUX.15 |
| ARQOS0 | input | TCELL23:IMUX.IMUX.0 |
| ARQOS1 | input | TCELL23:IMUX.IMUX.1 |
| ARQOS2 | input | TCELL23:IMUX.IMUX.2 |
| ARQOS3 | input | TCELL23:IMUX.IMUX.3 |
| ARREADY | output | TCELL20:OUT.0 |
| ARSIZE0 | input | TCELL22:IMUX.IMUX.3 |
| ARSIZE1 | input | TCELL22:IMUX.IMUX.4 |
| ARSIZE2 | input | TCELL22:IMUX.IMUX.5 |
| ARVALID | input | TCELL20:IMUX.IMUX.0 |
| AWADDR0 | input | TCELL24:IMUX.IMUX.9 |
| AWADDR1 | input | TCELL24:IMUX.IMUX.10 |
| AWADDR10 | input | TCELL25:IMUX.IMUX.3 |
| AWADDR11 | input | TCELL25:IMUX.IMUX.4 |
| AWADDR12 | input | TCELL25:IMUX.IMUX.5 |
| AWADDR13 | input | TCELL25:IMUX.IMUX.6 |
| AWADDR14 | input | TCELL25:IMUX.IMUX.7 |
| AWADDR15 | input | TCELL25:IMUX.IMUX.8 |
| AWADDR16 | input | TCELL25:IMUX.IMUX.9 |
| AWADDR17 | input | TCELL25:IMUX.IMUX.10 |
| AWADDR18 | input | TCELL25:IMUX.IMUX.11 |
| AWADDR19 | input | TCELL25:IMUX.IMUX.12 |
| AWADDR2 | input | TCELL24:IMUX.IMUX.11 |
| AWADDR20 | input | TCELL25:IMUX.IMUX.13 |
| AWADDR21 | input | TCELL25:IMUX.IMUX.14 |
| AWADDR22 | input | TCELL24:IMUX.IMUX.3 |
| AWADDR23 | input | TCELL24:IMUX.IMUX.4 |
| AWADDR24 | input | TCELL24:IMUX.IMUX.5 |
| AWADDR25 | input | TCELL24:IMUX.IMUX.6 |
| AWADDR26 | input | TCELL24:IMUX.IMUX.7 |
| AWADDR27 | input | TCELL24:IMUX.IMUX.8 |
| AWADDR3 | input | TCELL24:IMUX.IMUX.12 |
| AWADDR4 | input | TCELL24:IMUX.IMUX.13 |
| AWADDR5 | input | TCELL24:IMUX.IMUX.14 |
| AWADDR6 | input | TCELL24:IMUX.IMUX.15 |
| AWADDR7 | input | TCELL25:IMUX.IMUX.0 |
| AWADDR8 | input | TCELL25:IMUX.IMUX.1 |
| AWADDR9 | input | TCELL25:IMUX.IMUX.2 |
| AWBURST0 | input | TCELL26:IMUX.IMUX.6 |
| AWBURST1 | input | TCELL26:IMUX.IMUX.7 |
| AWCACHE0 | input | TCELL26:IMUX.IMUX.9 |
| AWCACHE1 | input | TCELL26:IMUX.IMUX.10 |
| AWCACHE2 | input | TCELL26:IMUX.IMUX.11 |
| AWCACHE3 | input | TCELL26:IMUX.IMUX.12 |
| AWID0 | input | TCELL32:IMUX.IMUX.1 |
| AWID1 | input | TCELL32:IMUX.IMUX.2 |
| AWID2 | input | TCELL32:IMUX.IMUX.3 |
| AWID3 | input | TCELL32:IMUX.IMUX.4 |
| AWID4 | input | TCELL32:IMUX.IMUX.5 |
| AWID5 | input | TCELL32:IMUX.IMUX.6 |
| AWID6 | input | TCELL32:IMUX.IMUX.7 |
| AWID7 | input | TCELL32:IMUX.IMUX.8 |
| AWLEN0 | input | TCELL25:IMUX.IMUX.15 |
| AWLEN1 | input | TCELL26:IMUX.IMUX.0 |
| AWLEN2 | input | TCELL26:IMUX.IMUX.1 |
| AWLEN3 | input | TCELL26:IMUX.IMUX.2 |
| AWLOCK | input | TCELL26:IMUX.IMUX.8 |
| AWPROT0 | input | TCELL26:IMUX.IMUX.13 |
| AWPROT1 | input | TCELL26:IMUX.IMUX.14 |
| AWPROT2 | input | TCELL26:IMUX.IMUX.15 |
| AWQOS0 | input | TCELL27:IMUX.IMUX.0 |
| AWQOS1 | input | TCELL27:IMUX.IMUX.1 |
| AWQOS2 | input | TCELL27:IMUX.IMUX.2 |
| AWQOS3 | input | TCELL27:IMUX.IMUX.3 |
| AWREADY | output | TCELL24:OUT.0 |
| AWSIZE0 | input | TCELL26:IMUX.IMUX.3 |
| AWSIZE1 | input | TCELL26:IMUX.IMUX.4 |
| AWSIZE2 | input | TCELL26:IMUX.IMUX.5 |
| AWVALID | input | TCELL24:IMUX.IMUX.0 |
| AXI_CLK | input | TCELL20:IMUX.CTRL.0 |
| BID0 | output | TCELL34:OUT.2 |
| BID1 | output | TCELL34:OUT.4 |
| BID2 | output | TCELL34:OUT.6 |
| BID3 | output | TCELL34:OUT.8 |
| BID4 | output | TCELL34:OUT.10 |
| BID5 | output | TCELL34:OUT.12 |
| BID6 | output | TCELL34:OUT.14 |
| BID7 | output | TCELL34:OUT.16 |
| BREADY | input | TCELL34:IMUX.IMUX.0 |
| BRESP0 | output | TCELL34:OUT.18 |
| BRESP1 | output | TCELL34:OUT.20 |
| BSCAN_CDR1 | output | TCELL42:OUT.4 |
| BSCAN_CDR2 | output | TCELL42:OUT.6 |
| BSCAN_CDR3 | output | TCELL54:OUT.18 |
| BSCAN_CDR4 | output | TCELL54:OUT.20 |
| BSCAN_CLKDR1 | output | TCELL42:OUT.8 |
| BSCAN_CLKDR2 | output | TCELL42:OUT.10 |
| BSCAN_CLKDR3 | output | TCELL54:OUT.22 |
| BSCAN_CLKDR4 | output | TCELL54:OUT.24 |
| BSCAN_RTI1 | output | TCELL42:OUT.12 |
| BSCAN_RTI2 | output | TCELL42:OUT.14 |
| BSCAN_RTI3 | output | TCELL54:OUT.26 |
| BSCAN_RTI4 | output | TCELL54:OUT.28 |
| BSCAN_SDR1 | output | TCELL42:OUT.16 |
| BSCAN_SDR2 | output | TCELL42:OUT.18 |
| BSCAN_SDR3 | output | TCELL53:OUT.0 |
| BSCAN_SDR4 | output | TCELL53:OUT.2 |
| BSCAN_SEL1 | output | TCELL42:OUT.20 |
| BSCAN_SEL2 | output | TCELL42:OUT.22 |
| BSCAN_SEL3 | output | TCELL53:OUT.4 |
| BSCAN_SEL4 | output | TCELL53:OUT.6 |
| BSCAN_TCK1 | output | TCELL43:OUT.6 |
| BSCAN_TCK2 | output | TCELL43:OUT.8 |
| BSCAN_TCK3 | output | TCELL54:OUT.6 |
| BSCAN_TCK4 | output | TCELL54:OUT.8 |
| BSCAN_TDI1 | output | TCELL43:OUT.14 |
| BSCAN_TDI2 | output | TCELL43:OUT.16 |
| BSCAN_TDI3 | output | TCELL54:OUT.14 |
| BSCAN_TDI4 | output | TCELL54:OUT.16 |
| BSCAN_TDO1 | input | TCELL43:IMUX.IMUX.2 |
| BSCAN_TDO2 | input | TCELL43:IMUX.IMUX.3 |
| BSCAN_TDO3 | input | TCELL54:IMUX.IMUX.2 |
| BSCAN_TDO4 | input | TCELL54:IMUX.IMUX.3 |
| BSCAN_TLR1 | output | TCELL42:OUT.24 |
| BSCAN_TLR2 | output | TCELL42:OUT.26 |
| BSCAN_TLR3 | output | TCELL53:OUT.8 |
| BSCAN_TLR4 | output | TCELL53:OUT.10 |
| BSCAN_TMS1 | output | TCELL43:OUT.10 |
| BSCAN_TMS2 | output | TCELL43:OUT.12 |
| BSCAN_TMS3 | output | TCELL54:OUT.10 |
| BSCAN_TMS4 | output | TCELL54:OUT.12 |
| BSCAN_UDR1 | output | TCELL42:OUT.28 |
| BSCAN_UDR2 | output | TCELL42:OUT.30 |
| BSCAN_UDR3 | output | TCELL53:OUT.12 |
| BSCAN_UDR4 | output | TCELL53:OUT.14 |
| BVALID | output | TCELL34:OUT.0 |
| DCI_LOCK | output | TCELL42:OUT.2 |
| DCI_USR_RESET_IN | input | TCELL42:IMUX.IMUX.3 |
| ECC_END_OF_FRAME | output | TCELL51:OUT.26 |
| ECC_END_OF_SCAN | output | TCELL51:OUT.28 |
| ECC_ERROR_NOTSINGLE | output | TCELL51:OUT.22 |
| ECC_ERROR_SINGLE | output | TCELL51:OUT.24 |
| ECC_FAR0 | output | TCELL52:OUT.0 |
| ECC_FAR1 | output | TCELL52:OUT.2 |
| ECC_FAR10 | output | TCELL52:OUT.20 |
| ECC_FAR11 | output | TCELL52:OUT.22 |
| ECC_FAR12 | output | TCELL52:OUT.24 |
| ECC_FAR13 | output | TCELL52:OUT.26 |
| ECC_FAR14 | output | TCELL52:OUT.28 |
| ECC_FAR15 | output | TCELL52:OUT.30 |
| ECC_FAR16 | output | TCELL51:OUT.0 |
| ECC_FAR17 | output | TCELL51:OUT.2 |
| ECC_FAR18 | output | TCELL51:OUT.4 |
| ECC_FAR19 | output | TCELL51:OUT.6 |
| ECC_FAR2 | output | TCELL52:OUT.4 |
| ECC_FAR20 | output | TCELL51:OUT.8 |
| ECC_FAR21 | output | TCELL51:OUT.10 |
| ECC_FAR22 | output | TCELL51:OUT.12 |
| ECC_FAR23 | output | TCELL51:OUT.14 |
| ECC_FAR24 | output | TCELL51:OUT.16 |
| ECC_FAR25 | output | TCELL51:OUT.18 |
| ECC_FAR26 | output | TCELL52:OUT.31 |
| ECC_FAR3 | output | TCELL52:OUT.6 |
| ECC_FAR4 | output | TCELL52:OUT.8 |
| ECC_FAR5 | output | TCELL52:OUT.10 |
| ECC_FAR6 | output | TCELL52:OUT.12 |
| ECC_FAR7 | output | TCELL52:OUT.14 |
| ECC_FAR8 | output | TCELL52:OUT.16 |
| ECC_FAR9 | output | TCELL52:OUT.18 |
| ECC_FAR_SEL0 | input | TCELL51:IMUX.IMUX.15 |
| ECC_FAR_SEL1 | input | TCELL51:IMUX.IMUX.16 |
| EOS | output | TCELL47:OUT.10 |
| ICAP_AVAIL_BOT | output | TCELL43:OUT.4 |
| ICAP_AVAIL_TOP | output | TCELL54:OUT.4 |
| ICAP_CLK_BOT | input | TCELL45:IMUX.CTRL.0 |
| ICAP_CLK_TOP | input | TCELL56:IMUX.CTRL.0 |
| ICAP_CS_B_BOT | input | TCELL43:IMUX.IMUX.1 |
| ICAP_CS_B_TOP | input | TCELL54:IMUX.IMUX.1 |
| ICAP_DATA_BOT0 | input | TCELL44:IMUX.IMUX.0 |
| ICAP_DATA_BOT1 | input | TCELL44:IMUX.IMUX.1 |
| ICAP_DATA_BOT10 | input | TCELL44:IMUX.IMUX.10 |
| ICAP_DATA_BOT11 | input | TCELL44:IMUX.IMUX.11 |
| ICAP_DATA_BOT12 | input | TCELL44:IMUX.IMUX.12 |
| ICAP_DATA_BOT13 | input | TCELL44:IMUX.IMUX.13 |
| ICAP_DATA_BOT14 | input | TCELL44:IMUX.IMUX.14 |
| ICAP_DATA_BOT15 | input | TCELL44:IMUX.IMUX.15 |
| ICAP_DATA_BOT16 | input | TCELL45:IMUX.IMUX.0 |
| ICAP_DATA_BOT17 | input | TCELL45:IMUX.IMUX.1 |
| ICAP_DATA_BOT18 | input | TCELL45:IMUX.IMUX.2 |
| ICAP_DATA_BOT19 | input | TCELL45:IMUX.IMUX.3 |
| ICAP_DATA_BOT2 | input | TCELL44:IMUX.IMUX.2 |
| ICAP_DATA_BOT20 | input | TCELL45:IMUX.IMUX.4 |
| ICAP_DATA_BOT21 | input | TCELL45:IMUX.IMUX.5 |
| ICAP_DATA_BOT22 | input | TCELL45:IMUX.IMUX.6 |
| ICAP_DATA_BOT23 | input | TCELL45:IMUX.IMUX.7 |
| ICAP_DATA_BOT24 | input | TCELL45:IMUX.IMUX.8 |
| ICAP_DATA_BOT25 | input | TCELL45:IMUX.IMUX.9 |
| ICAP_DATA_BOT26 | input | TCELL45:IMUX.IMUX.10 |
| ICAP_DATA_BOT27 | input | TCELL45:IMUX.IMUX.11 |
| ICAP_DATA_BOT28 | input | TCELL45:IMUX.IMUX.12 |
| ICAP_DATA_BOT29 | input | TCELL45:IMUX.IMUX.13 |
| ICAP_DATA_BOT3 | input | TCELL44:IMUX.IMUX.3 |
| ICAP_DATA_BOT30 | input | TCELL45:IMUX.IMUX.14 |
| ICAP_DATA_BOT31 | input | TCELL45:IMUX.IMUX.15 |
| ICAP_DATA_BOT4 | input | TCELL44:IMUX.IMUX.4 |
| ICAP_DATA_BOT5 | input | TCELL44:IMUX.IMUX.5 |
| ICAP_DATA_BOT6 | input | TCELL44:IMUX.IMUX.6 |
| ICAP_DATA_BOT7 | input | TCELL44:IMUX.IMUX.7 |
| ICAP_DATA_BOT8 | input | TCELL44:IMUX.IMUX.8 |
| ICAP_DATA_BOT9 | input | TCELL44:IMUX.IMUX.9 |
| ICAP_DATA_TOP0 | input | TCELL55:IMUX.IMUX.0 |
| ICAP_DATA_TOP1 | input | TCELL55:IMUX.IMUX.1 |
| ICAP_DATA_TOP10 | input | TCELL55:IMUX.IMUX.10 |
| ICAP_DATA_TOP11 | input | TCELL55:IMUX.IMUX.11 |
| ICAP_DATA_TOP12 | input | TCELL55:IMUX.IMUX.12 |
| ICAP_DATA_TOP13 | input | TCELL55:IMUX.IMUX.13 |
| ICAP_DATA_TOP14 | input | TCELL55:IMUX.IMUX.14 |
| ICAP_DATA_TOP15 | input | TCELL55:IMUX.IMUX.15 |
| ICAP_DATA_TOP16 | input | TCELL56:IMUX.IMUX.0 |
| ICAP_DATA_TOP17 | input | TCELL56:IMUX.IMUX.1 |
| ICAP_DATA_TOP18 | input | TCELL56:IMUX.IMUX.2 |
| ICAP_DATA_TOP19 | input | TCELL56:IMUX.IMUX.3 |
| ICAP_DATA_TOP2 | input | TCELL55:IMUX.IMUX.2 |
| ICAP_DATA_TOP20 | input | TCELL56:IMUX.IMUX.4 |
| ICAP_DATA_TOP21 | input | TCELL56:IMUX.IMUX.5 |
| ICAP_DATA_TOP22 | input | TCELL56:IMUX.IMUX.6 |
| ICAP_DATA_TOP23 | input | TCELL56:IMUX.IMUX.7 |
| ICAP_DATA_TOP24 | input | TCELL56:IMUX.IMUX.8 |
| ICAP_DATA_TOP25 | input | TCELL56:IMUX.IMUX.9 |
| ICAP_DATA_TOP26 | input | TCELL56:IMUX.IMUX.10 |
| ICAP_DATA_TOP27 | input | TCELL56:IMUX.IMUX.11 |
| ICAP_DATA_TOP28 | input | TCELL56:IMUX.IMUX.12 |
| ICAP_DATA_TOP29 | input | TCELL56:IMUX.IMUX.13 |
| ICAP_DATA_TOP3 | input | TCELL55:IMUX.IMUX.3 |
| ICAP_DATA_TOP30 | input | TCELL56:IMUX.IMUX.14 |
| ICAP_DATA_TOP31 | input | TCELL56:IMUX.IMUX.15 |
| ICAP_DATA_TOP4 | input | TCELL55:IMUX.IMUX.4 |
| ICAP_DATA_TOP5 | input | TCELL55:IMUX.IMUX.5 |
| ICAP_DATA_TOP6 | input | TCELL55:IMUX.IMUX.6 |
| ICAP_DATA_TOP7 | input | TCELL55:IMUX.IMUX.7 |
| ICAP_DATA_TOP8 | input | TCELL55:IMUX.IMUX.8 |
| ICAP_DATA_TOP9 | input | TCELL55:IMUX.IMUX.9 |
| ICAP_OUT_BOT0 | output | TCELL44:OUT.0 |
| ICAP_OUT_BOT1 | output | TCELL44:OUT.2 |
| ICAP_OUT_BOT10 | output | TCELL44:OUT.20 |
| ICAP_OUT_BOT11 | output | TCELL44:OUT.22 |
| ICAP_OUT_BOT12 | output | TCELL44:OUT.24 |
| ICAP_OUT_BOT13 | output | TCELL44:OUT.26 |
| ICAP_OUT_BOT14 | output | TCELL44:OUT.28 |
| ICAP_OUT_BOT15 | output | TCELL44:OUT.30 |
| ICAP_OUT_BOT16 | output | TCELL45:OUT.0 |
| ICAP_OUT_BOT17 | output | TCELL45:OUT.2 |
| ICAP_OUT_BOT18 | output | TCELL45:OUT.4 |
| ICAP_OUT_BOT19 | output | TCELL45:OUT.6 |
| ICAP_OUT_BOT2 | output | TCELL44:OUT.4 |
| ICAP_OUT_BOT20 | output | TCELL45:OUT.8 |
| ICAP_OUT_BOT21 | output | TCELL45:OUT.10 |
| ICAP_OUT_BOT22 | output | TCELL45:OUT.12 |
| ICAP_OUT_BOT23 | output | TCELL45:OUT.14 |
| ICAP_OUT_BOT24 | output | TCELL45:OUT.16 |
| ICAP_OUT_BOT25 | output | TCELL45:OUT.18 |
| ICAP_OUT_BOT26 | output | TCELL45:OUT.20 |
| ICAP_OUT_BOT27 | output | TCELL45:OUT.22 |
| ICAP_OUT_BOT28 | output | TCELL45:OUT.24 |
| ICAP_OUT_BOT29 | output | TCELL45:OUT.26 |
| ICAP_OUT_BOT3 | output | TCELL44:OUT.6 |
| ICAP_OUT_BOT30 | output | TCELL45:OUT.28 |
| ICAP_OUT_BOT31 | output | TCELL45:OUT.30 |
| ICAP_OUT_BOT4 | output | TCELL44:OUT.8 |
| ICAP_OUT_BOT5 | output | TCELL44:OUT.10 |
| ICAP_OUT_BOT6 | output | TCELL44:OUT.12 |
| ICAP_OUT_BOT7 | output | TCELL44:OUT.14 |
| ICAP_OUT_BOT8 | output | TCELL44:OUT.16 |
| ICAP_OUT_BOT9 | output | TCELL44:OUT.18 |
| ICAP_OUT_TOP0 | output | TCELL55:OUT.0 |
| ICAP_OUT_TOP1 | output | TCELL55:OUT.2 |
| ICAP_OUT_TOP10 | output | TCELL55:OUT.20 |
| ICAP_OUT_TOP11 | output | TCELL55:OUT.22 |
| ICAP_OUT_TOP12 | output | TCELL55:OUT.24 |
| ICAP_OUT_TOP13 | output | TCELL55:OUT.26 |
| ICAP_OUT_TOP14 | output | TCELL55:OUT.28 |
| ICAP_OUT_TOP15 | output | TCELL55:OUT.30 |
| ICAP_OUT_TOP16 | output | TCELL56:OUT.0 |
| ICAP_OUT_TOP17 | output | TCELL56:OUT.2 |
| ICAP_OUT_TOP18 | output | TCELL56:OUT.4 |
| ICAP_OUT_TOP19 | output | TCELL56:OUT.6 |
| ICAP_OUT_TOP2 | output | TCELL55:OUT.4 |
| ICAP_OUT_TOP20 | output | TCELL56:OUT.8 |
| ICAP_OUT_TOP21 | output | TCELL56:OUT.10 |
| ICAP_OUT_TOP22 | output | TCELL56:OUT.12 |
| ICAP_OUT_TOP23 | output | TCELL56:OUT.14 |
| ICAP_OUT_TOP24 | output | TCELL56:OUT.16 |
| ICAP_OUT_TOP25 | output | TCELL56:OUT.18 |
| ICAP_OUT_TOP26 | output | TCELL56:OUT.20 |
| ICAP_OUT_TOP27 | output | TCELL56:OUT.22 |
| ICAP_OUT_TOP28 | output | TCELL56:OUT.24 |
| ICAP_OUT_TOP29 | output | TCELL56:OUT.26 |
| ICAP_OUT_TOP3 | output | TCELL55:OUT.6 |
| ICAP_OUT_TOP30 | output | TCELL56:OUT.28 |
| ICAP_OUT_TOP31 | output | TCELL56:OUT.30 |
| ICAP_OUT_TOP4 | output | TCELL55:OUT.8 |
| ICAP_OUT_TOP5 | output | TCELL55:OUT.10 |
| ICAP_OUT_TOP6 | output | TCELL55:OUT.12 |
| ICAP_OUT_TOP7 | output | TCELL55:OUT.14 |
| ICAP_OUT_TOP8 | output | TCELL55:OUT.16 |
| ICAP_OUT_TOP9 | output | TCELL55:OUT.18 |
| ICAP_PR_DONE_BOT | output | TCELL43:OUT.0 |
| ICAP_PR_DONE_TOP | output | TCELL54:OUT.0 |
| ICAP_PR_ERROR_BOT | output | TCELL43:OUT.2 |
| ICAP_PR_ERROR_TOP | output | TCELL54:OUT.2 |
| ICAP_RDWR_B_BOT | input | TCELL43:IMUX.IMUX.0 |
| ICAP_RDWR_B_TOP | input | TCELL54:IMUX.IMUX.0 |
| IOX_CCLK | output | TCELL50:OUT.0 |
| IOX_CFGDATA0 | output | TCELL48:OUT.0 |
| IOX_CFGDATA1 | output | TCELL48:OUT.2 |
| IOX_CFGDATA10 | output | TCELL48:OUT.20 |
| IOX_CFGDATA11 | output | TCELL48:OUT.22 |
| IOX_CFGDATA12 | output | TCELL48:OUT.24 |
| IOX_CFGDATA13 | output | TCELL48:OUT.26 |
| IOX_CFGDATA14 | output | TCELL48:OUT.28 |
| IOX_CFGDATA15 | output | TCELL48:OUT.30 |
| IOX_CFGDATA16 | output | TCELL49:OUT.0 |
| IOX_CFGDATA17 | output | TCELL49:OUT.2 |
| IOX_CFGDATA18 | output | TCELL49:OUT.4 |
| IOX_CFGDATA19 | output | TCELL49:OUT.6 |
| IOX_CFGDATA2 | output | TCELL48:OUT.4 |
| IOX_CFGDATA20 | output | TCELL49:OUT.8 |
| IOX_CFGDATA21 | output | TCELL49:OUT.10 |
| IOX_CFGDATA22 | output | TCELL49:OUT.12 |
| IOX_CFGDATA23 | output | TCELL49:OUT.14 |
| IOX_CFGDATA24 | output | TCELL49:OUT.16 |
| IOX_CFGDATA25 | output | TCELL49:OUT.18 |
| IOX_CFGDATA26 | output | TCELL49:OUT.20 |
| IOX_CFGDATA27 | output | TCELL49:OUT.22 |
| IOX_CFGDATA28 | output | TCELL49:OUT.24 |
| IOX_CFGDATA29 | output | TCELL49:OUT.26 |
| IOX_CFGDATA3 | output | TCELL48:OUT.6 |
| IOX_CFGDATA30 | output | TCELL49:OUT.28 |
| IOX_CFGDATA31 | output | TCELL49:OUT.30 |
| IOX_CFGDATA4 | output | TCELL48:OUT.8 |
| IOX_CFGDATA5 | output | TCELL48:OUT.10 |
| IOX_CFGDATA6 | output | TCELL48:OUT.12 |
| IOX_CFGDATA7 | output | TCELL48:OUT.14 |
| IOX_CFGDATA8 | output | TCELL48:OUT.16 |
| IOX_CFGDATA9 | output | TCELL48:OUT.18 |
| IOX_CFGMASTER | output | TCELL50:OUT.2 |
| IOX_INITBI | output | TCELL50:OUT.6 |
| IOX_INITBO | input | TCELL48:IMUX.IMUX.1 |
| IOX_MODE0 | output | TCELL50:OUT.12 |
| IOX_MODE1 | output | TCELL50:OUT.14 |
| IOX_MODE2 | output | TCELL50:OUT.16 |
| IOX_PUDCB | output | TCELL50:OUT.8 |
| IOX_RDWRB | output | TCELL50:OUT.10 |
| IOX_TDO | input | TCELL48:IMUX.IMUX.0 |
| IOX_VGG_COMP_OUT | output | TCELL50:OUT.4 |
| KEY_CLEAR_B | input | TCELL47:IMUX.IMUX.0 |
| PROG_ACK | input | TCELL47:IMUX.IMUX.1 |
| PROG_REQ | output | TCELL47:OUT.8 |
| RBCRC_ERROR | output | TCELL51:OUT.20 |
| RDATA0 | output | TCELL31:OUT.24 |
| RDATA1 | output | TCELL31:OUT.26 |
| RDATA10 | output | TCELL32:OUT.12 |
| RDATA11 | output | TCELL32:OUT.14 |
| RDATA12 | output | TCELL32:OUT.16 |
| RDATA13 | output | TCELL32:OUT.18 |
| RDATA14 | output | TCELL32:OUT.20 |
| RDATA15 | output | TCELL32:OUT.22 |
| RDATA16 | output | TCELL32:OUT.24 |
| RDATA17 | output | TCELL32:OUT.26 |
| RDATA18 | output | TCELL32:OUT.28 |
| RDATA19 | output | TCELL32:OUT.30 |
| RDATA2 | output | TCELL31:OUT.28 |
| RDATA20 | output | TCELL33:OUT.0 |
| RDATA21 | output | TCELL33:OUT.2 |
| RDATA22 | output | TCELL33:OUT.4 |
| RDATA23 | output | TCELL33:OUT.6 |
| RDATA24 | output | TCELL33:OUT.8 |
| RDATA25 | output | TCELL33:OUT.10 |
| RDATA26 | output | TCELL33:OUT.12 |
| RDATA27 | output | TCELL33:OUT.14 |
| RDATA28 | output | TCELL33:OUT.16 |
| RDATA29 | output | TCELL33:OUT.18 |
| RDATA3 | output | TCELL31:OUT.30 |
| RDATA30 | output | TCELL33:OUT.20 |
| RDATA31 | output | TCELL33:OUT.22 |
| RDATA4 | output | TCELL32:OUT.0 |
| RDATA5 | output | TCELL32:OUT.2 |
| RDATA6 | output | TCELL32:OUT.4 |
| RDATA7 | output | TCELL32:OUT.6 |
| RDATA8 | output | TCELL32:OUT.8 |
| RDATA9 | output | TCELL32:OUT.10 |
| RID0 | output | TCELL31:OUT.4 |
| RID1 | output | TCELL31:OUT.6 |
| RID2 | output | TCELL31:OUT.8 |
| RID3 | output | TCELL31:OUT.10 |
| RID4 | output | TCELL31:OUT.12 |
| RID5 | output | TCELL31:OUT.14 |
| RID6 | output | TCELL31:OUT.16 |
| RID7 | output | TCELL31:OUT.18 |
| RLAST | output | TCELL31:OUT.2 |
| RREADY | input | TCELL31:IMUX.IMUX.0 |
| RRESP0 | output | TCELL31:OUT.20 |
| RRESP1 | output | TCELL31:OUT.22 |
| RVALID | output | TCELL31:OUT.0 |
| START_CFG_CLK | output | TCELL47:OUT.14 |
| START_CFG_MCLK | output | TCELL47:OUT.12 |
| USR_ACCESS_CLK | output | TCELL57:OUT.2 |
| USR_ACCESS_DATA0 | output | TCELL58:OUT.0 |
| USR_ACCESS_DATA1 | output | TCELL58:OUT.2 |
| USR_ACCESS_DATA10 | output | TCELL58:OUT.20 |
| USR_ACCESS_DATA11 | output | TCELL58:OUT.22 |
| USR_ACCESS_DATA12 | output | TCELL58:OUT.24 |
| USR_ACCESS_DATA13 | output | TCELL58:OUT.26 |
| USR_ACCESS_DATA14 | output | TCELL58:OUT.28 |
| USR_ACCESS_DATA15 | output | TCELL58:OUT.30 |
| USR_ACCESS_DATA16 | output | TCELL59:OUT.0 |
| USR_ACCESS_DATA17 | output | TCELL59:OUT.2 |
| USR_ACCESS_DATA18 | output | TCELL59:OUT.4 |
| USR_ACCESS_DATA19 | output | TCELL59:OUT.6 |
| USR_ACCESS_DATA2 | output | TCELL58:OUT.4 |
| USR_ACCESS_DATA20 | output | TCELL59:OUT.8 |
| USR_ACCESS_DATA21 | output | TCELL59:OUT.10 |
| USR_ACCESS_DATA22 | output | TCELL59:OUT.12 |
| USR_ACCESS_DATA23 | output | TCELL59:OUT.14 |
| USR_ACCESS_DATA24 | output | TCELL59:OUT.16 |
| USR_ACCESS_DATA25 | output | TCELL59:OUT.18 |
| USR_ACCESS_DATA26 | output | TCELL59:OUT.20 |
| USR_ACCESS_DATA27 | output | TCELL59:OUT.22 |
| USR_ACCESS_DATA28 | output | TCELL59:OUT.24 |
| USR_ACCESS_DATA29 | output | TCELL59:OUT.26 |
| USR_ACCESS_DATA3 | output | TCELL58:OUT.6 |
| USR_ACCESS_DATA30 | output | TCELL59:OUT.28 |
| USR_ACCESS_DATA31 | output | TCELL59:OUT.30 |
| USR_ACCESS_DATA4 | output | TCELL58:OUT.8 |
| USR_ACCESS_DATA5 | output | TCELL58:OUT.10 |
| USR_ACCESS_DATA6 | output | TCELL58:OUT.12 |
| USR_ACCESS_DATA7 | output | TCELL58:OUT.14 |
| USR_ACCESS_DATA8 | output | TCELL58:OUT.16 |
| USR_ACCESS_DATA9 | output | TCELL58:OUT.18 |
| USR_ACCESS_VALID | output | TCELL57:OUT.0 |
| USR_CCLK_O | input | TCELL47:IMUX.CTRL.0 |
| USR_CCLK_TS | input | TCELL47:IMUX.IMUX.2 |
| USR_DNA_CLK | input | TCELL42:IMUX.CTRL.0 |
| USR_DNA_DIN | input | TCELL42:IMUX.IMUX.0 |
| USR_DNA_OUT | output | TCELL42:OUT.0 |
| USR_DNA_READ | input | TCELL42:IMUX.IMUX.1 |
| USR_DNA_SHIFT | input | TCELL42:IMUX.IMUX.2 |
| USR_DONE_O | input | TCELL47:IMUX.IMUX.3 |
| USR_DONE_TS | input | TCELL47:IMUX.IMUX.4 |
| USR_D_O_CFGIO0 | input | TCELL47:IMUX.IMUX.9 |
| USR_D_O_CFGIO1 | input | TCELL47:IMUX.IMUX.10 |
| USR_D_O_CFGIO2 | input | TCELL47:IMUX.IMUX.11 |
| USR_D_O_CFGIO3 | input | TCELL47:IMUX.IMUX.12 |
| USR_D_PIN_CFGIO0 | output | TCELL47:OUT.0 |
| USR_D_PIN_CFGIO1 | output | TCELL47:OUT.2 |
| USR_D_PIN_CFGIO2 | output | TCELL47:OUT.4 |
| USR_D_PIN_CFGIO3 | output | TCELL47:OUT.6 |
| USR_D_TS_CFGIO0 | input | TCELL47:IMUX.IMUX.13 |
| USR_D_TS_CFGIO1 | input | TCELL47:IMUX.IMUX.14 |
| USR_D_TS_CFGIO2 | input | TCELL47:IMUX.IMUX.15 |
| USR_D_TS_CFGIO3 | input | TCELL47:IMUX.IMUX.16 |
| USR_EFUSE0 | output | TCELL46:OUT.0 |
| USR_EFUSE1 | output | TCELL46:OUT.2 |
| USR_EFUSE10 | output | TCELL46:OUT.20 |
| USR_EFUSE11 | output | TCELL46:OUT.22 |
| USR_EFUSE12 | output | TCELL46:OUT.24 |
| USR_EFUSE13 | output | TCELL46:OUT.26 |
| USR_EFUSE14 | output | TCELL46:OUT.28 |
| USR_EFUSE15 | output | TCELL46:OUT.30 |
| USR_EFUSE16 | output | TCELL41:OUT.0 |
| USR_EFUSE17 | output | TCELL41:OUT.2 |
| USR_EFUSE18 | output | TCELL41:OUT.4 |
| USR_EFUSE19 | output | TCELL41:OUT.6 |
| USR_EFUSE2 | output | TCELL46:OUT.4 |
| USR_EFUSE20 | output | TCELL41:OUT.8 |
| USR_EFUSE21 | output | TCELL41:OUT.10 |
| USR_EFUSE22 | output | TCELL41:OUT.12 |
| USR_EFUSE23 | output | TCELL41:OUT.14 |
| USR_EFUSE24 | output | TCELL41:OUT.16 |
| USR_EFUSE25 | output | TCELL41:OUT.18 |
| USR_EFUSE26 | output | TCELL41:OUT.20 |
| USR_EFUSE27 | output | TCELL41:OUT.22 |
| USR_EFUSE28 | output | TCELL41:OUT.24 |
| USR_EFUSE29 | output | TCELL41:OUT.26 |
| USR_EFUSE3 | output | TCELL46:OUT.6 |
| USR_EFUSE30 | output | TCELL41:OUT.28 |
| USR_EFUSE31 | output | TCELL41:OUT.30 |
| USR_EFUSE4 | output | TCELL46:OUT.8 |
| USR_EFUSE5 | output | TCELL46:OUT.10 |
| USR_EFUSE6 | output | TCELL46:OUT.12 |
| USR_EFUSE7 | output | TCELL46:OUT.14 |
| USR_EFUSE8 | output | TCELL46:OUT.16 |
| USR_EFUSE9 | output | TCELL46:OUT.18 |
| USR_FCS_B_O | input | TCELL47:IMUX.IMUX.7 |
| USR_FCS_B_TS | input | TCELL47:IMUX.IMUX.8 |
| USR_GSR | input | TCELL47:IMUX.IMUX.5 |
| USR_GTS | input | TCELL47:IMUX.IMUX.6 |
| USR_TCK | input | TCELL43:IMUX.CTRL.1 |
| USR_TDI | input | TCELL43:IMUX.IMUX.6 |
| USR_TDO | output | TCELL43:OUT.18 |
| USR_TMS | input | TCELL43:IMUX.IMUX.5 |
| WDATA0 | input | TCELL28:IMUX.IMUX.10 |
| WDATA1 | input | TCELL28:IMUX.IMUX.11 |
| WDATA10 | input | TCELL29:IMUX.IMUX.4 |
| WDATA11 | input | TCELL29:IMUX.IMUX.5 |
| WDATA12 | input | TCELL29:IMUX.IMUX.6 |
| WDATA13 | input | TCELL29:IMUX.IMUX.7 |
| WDATA14 | input | TCELL29:IMUX.IMUX.8 |
| WDATA15 | input | TCELL29:IMUX.IMUX.9 |
| WDATA16 | input | TCELL29:IMUX.IMUX.10 |
| WDATA17 | input | TCELL29:IMUX.IMUX.11 |
| WDATA18 | input | TCELL29:IMUX.IMUX.12 |
| WDATA19 | input | TCELL29:IMUX.IMUX.13 |
| WDATA2 | input | TCELL28:IMUX.IMUX.12 |
| WDATA20 | input | TCELL29:IMUX.IMUX.14 |
| WDATA21 | input | TCELL29:IMUX.IMUX.15 |
| WDATA22 | input | TCELL30:IMUX.IMUX.0 |
| WDATA23 | input | TCELL30:IMUX.IMUX.1 |
| WDATA24 | input | TCELL30:IMUX.IMUX.2 |
| WDATA25 | input | TCELL30:IMUX.IMUX.3 |
| WDATA26 | input | TCELL30:IMUX.IMUX.4 |
| WDATA27 | input | TCELL30:IMUX.IMUX.5 |
| WDATA28 | input | TCELL30:IMUX.IMUX.6 |
| WDATA29 | input | TCELL30:IMUX.IMUX.7 |
| WDATA3 | input | TCELL28:IMUX.IMUX.13 |
| WDATA30 | input | TCELL30:IMUX.IMUX.8 |
| WDATA31 | input | TCELL30:IMUX.IMUX.9 |
| WDATA4 | input | TCELL28:IMUX.IMUX.14 |
| WDATA5 | input | TCELL28:IMUX.IMUX.15 |
| WDATA6 | input | TCELL29:IMUX.IMUX.0 |
| WDATA7 | input | TCELL29:IMUX.IMUX.1 |
| WDATA8 | input | TCELL29:IMUX.IMUX.2 |
| WDATA9 | input | TCELL29:IMUX.IMUX.3 |
| WID0 | input | TCELL28:IMUX.IMUX.2 |
| WID1 | input | TCELL28:IMUX.IMUX.3 |
| WID2 | input | TCELL28:IMUX.IMUX.4 |
| WID3 | input | TCELL28:IMUX.IMUX.5 |
| WID4 | input | TCELL28:IMUX.IMUX.6 |
| WID5 | input | TCELL28:IMUX.IMUX.7 |
| WID6 | input | TCELL28:IMUX.IMUX.8 |
| WID7 | input | TCELL28:IMUX.IMUX.9 |
| WLAST | input | TCELL28:IMUX.IMUX.1 |
| WREADY | output | TCELL28:OUT.0 |
| WSTRB0 | input | TCELL30:IMUX.IMUX.10 |
| WSTRB1 | input | TCELL30:IMUX.IMUX.11 |
| WSTRB2 | input | TCELL30:IMUX.IMUX.12 |
| WSTRB3 | input | TCELL30:IMUX.IMUX.13 |
| WVALID | input | TCELL28:IMUX.IMUX.0 |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL20:OUT.0 | CFG.ARREADY |
| TCELL20:IMUX.CTRL.0 | CFG.AXI_CLK |
| TCELL20:IMUX.IMUX.0 | CFG.ARVALID |
| TCELL20:IMUX.IMUX.3 | CFG.ARADDR22 |
| TCELL20:IMUX.IMUX.4 | CFG.ARADDR23 |
| TCELL20:IMUX.IMUX.5 | CFG.ARADDR24 |
| TCELL20:IMUX.IMUX.6 | CFG.ARADDR25 |
| TCELL20:IMUX.IMUX.7 | CFG.ARADDR26 |
| TCELL20:IMUX.IMUX.8 | CFG.ARADDR27 |
| TCELL20:IMUX.IMUX.9 | CFG.ARADDR0 |
| TCELL20:IMUX.IMUX.10 | CFG.ARADDR1 |
| TCELL20:IMUX.IMUX.11 | CFG.ARADDR2 |
| TCELL20:IMUX.IMUX.12 | CFG.ARADDR3 |
| TCELL20:IMUX.IMUX.13 | CFG.ARADDR4 |
| TCELL20:IMUX.IMUX.14 | CFG.ARADDR5 |
| TCELL20:IMUX.IMUX.15 | CFG.ARADDR6 |
| TCELL21:IMUX.IMUX.0 | CFG.ARADDR7 |
| TCELL21:IMUX.IMUX.1 | CFG.ARADDR8 |
| TCELL21:IMUX.IMUX.2 | CFG.ARADDR9 |
| TCELL21:IMUX.IMUX.3 | CFG.ARADDR10 |
| TCELL21:IMUX.IMUX.4 | CFG.ARADDR11 |
| TCELL21:IMUX.IMUX.5 | CFG.ARADDR12 |
| TCELL21:IMUX.IMUX.6 | CFG.ARADDR13 |
| TCELL21:IMUX.IMUX.7 | CFG.ARADDR14 |
| TCELL21:IMUX.IMUX.8 | CFG.ARADDR15 |
| TCELL21:IMUX.IMUX.9 | CFG.ARADDR16 |
| TCELL21:IMUX.IMUX.10 | CFG.ARADDR17 |
| TCELL21:IMUX.IMUX.11 | CFG.ARADDR18 |
| TCELL21:IMUX.IMUX.12 | CFG.ARADDR19 |
| TCELL21:IMUX.IMUX.13 | CFG.ARADDR20 |
| TCELL21:IMUX.IMUX.14 | CFG.ARADDR21 |
| TCELL21:IMUX.IMUX.15 | CFG.ARLEN0 |
| TCELL22:IMUX.IMUX.0 | CFG.ARLEN1 |
| TCELL22:IMUX.IMUX.1 | CFG.ARLEN2 |
| TCELL22:IMUX.IMUX.2 | CFG.ARLEN3 |
| TCELL22:IMUX.IMUX.3 | CFG.ARSIZE0 |
| TCELL22:IMUX.IMUX.4 | CFG.ARSIZE1 |
| TCELL22:IMUX.IMUX.5 | CFG.ARSIZE2 |
| TCELL22:IMUX.IMUX.6 | CFG.ARBURST0 |
| TCELL22:IMUX.IMUX.7 | CFG.ARBURST1 |
| TCELL22:IMUX.IMUX.8 | CFG.ARLOCK |
| TCELL22:IMUX.IMUX.9 | CFG.ARCACHE0 |
| TCELL22:IMUX.IMUX.10 | CFG.ARCACHE1 |
| TCELL22:IMUX.IMUX.11 | CFG.ARCACHE2 |
| TCELL22:IMUX.IMUX.12 | CFG.ARCACHE3 |
| TCELL22:IMUX.IMUX.13 | CFG.ARPROT0 |
| TCELL22:IMUX.IMUX.14 | CFG.ARPROT1 |
| TCELL22:IMUX.IMUX.15 | CFG.ARPROT2 |
| TCELL23:IMUX.IMUX.0 | CFG.ARQOS0 |
| TCELL23:IMUX.IMUX.1 | CFG.ARQOS1 |
| TCELL23:IMUX.IMUX.2 | CFG.ARQOS2 |
| TCELL23:IMUX.IMUX.3 | CFG.ARQOS3 |
| TCELL24:OUT.0 | CFG.AWREADY |
| TCELL24:IMUX.IMUX.0 | CFG.AWVALID |
| TCELL24:IMUX.IMUX.3 | CFG.AWADDR22 |
| TCELL24:IMUX.IMUX.4 | CFG.AWADDR23 |
| TCELL24:IMUX.IMUX.5 | CFG.AWADDR24 |
| TCELL24:IMUX.IMUX.6 | CFG.AWADDR25 |
| TCELL24:IMUX.IMUX.7 | CFG.AWADDR26 |
| TCELL24:IMUX.IMUX.8 | CFG.AWADDR27 |
| TCELL24:IMUX.IMUX.9 | CFG.AWADDR0 |
| TCELL24:IMUX.IMUX.10 | CFG.AWADDR1 |
| TCELL24:IMUX.IMUX.11 | CFG.AWADDR2 |
| TCELL24:IMUX.IMUX.12 | CFG.AWADDR3 |
| TCELL24:IMUX.IMUX.13 | CFG.AWADDR4 |
| TCELL24:IMUX.IMUX.14 | CFG.AWADDR5 |
| TCELL24:IMUX.IMUX.15 | CFG.AWADDR6 |
| TCELL25:IMUX.IMUX.0 | CFG.AWADDR7 |
| TCELL25:IMUX.IMUX.1 | CFG.AWADDR8 |
| TCELL25:IMUX.IMUX.2 | CFG.AWADDR9 |
| TCELL25:IMUX.IMUX.3 | CFG.AWADDR10 |
| TCELL25:IMUX.IMUX.4 | CFG.AWADDR11 |
| TCELL25:IMUX.IMUX.5 | CFG.AWADDR12 |
| TCELL25:IMUX.IMUX.6 | CFG.AWADDR13 |
| TCELL25:IMUX.IMUX.7 | CFG.AWADDR14 |
| TCELL25:IMUX.IMUX.8 | CFG.AWADDR15 |
| TCELL25:IMUX.IMUX.9 | CFG.AWADDR16 |
| TCELL25:IMUX.IMUX.10 | CFG.AWADDR17 |
| TCELL25:IMUX.IMUX.11 | CFG.AWADDR18 |
| TCELL25:IMUX.IMUX.12 | CFG.AWADDR19 |
| TCELL25:IMUX.IMUX.13 | CFG.AWADDR20 |
| TCELL25:IMUX.IMUX.14 | CFG.AWADDR21 |
| TCELL25:IMUX.IMUX.15 | CFG.AWLEN0 |
| TCELL26:IMUX.IMUX.0 | CFG.AWLEN1 |
| TCELL26:IMUX.IMUX.1 | CFG.AWLEN2 |
| TCELL26:IMUX.IMUX.2 | CFG.AWLEN3 |
| TCELL26:IMUX.IMUX.3 | CFG.AWSIZE0 |
| TCELL26:IMUX.IMUX.4 | CFG.AWSIZE1 |
| TCELL26:IMUX.IMUX.5 | CFG.AWSIZE2 |
| TCELL26:IMUX.IMUX.6 | CFG.AWBURST0 |
| TCELL26:IMUX.IMUX.7 | CFG.AWBURST1 |
| TCELL26:IMUX.IMUX.8 | CFG.AWLOCK |
| TCELL26:IMUX.IMUX.9 | CFG.AWCACHE0 |
| TCELL26:IMUX.IMUX.10 | CFG.AWCACHE1 |
| TCELL26:IMUX.IMUX.11 | CFG.AWCACHE2 |
| TCELL26:IMUX.IMUX.12 | CFG.AWCACHE3 |
| TCELL26:IMUX.IMUX.13 | CFG.AWPROT0 |
| TCELL26:IMUX.IMUX.14 | CFG.AWPROT1 |
| TCELL26:IMUX.IMUX.15 | CFG.AWPROT2 |
| TCELL27:IMUX.IMUX.0 | CFG.AWQOS0 |
| TCELL27:IMUX.IMUX.1 | CFG.AWQOS1 |
| TCELL27:IMUX.IMUX.2 | CFG.AWQOS2 |
| TCELL27:IMUX.IMUX.3 | CFG.AWQOS3 |
| TCELL28:OUT.0 | CFG.WREADY |
| TCELL28:IMUX.IMUX.0 | CFG.WVALID |
| TCELL28:IMUX.IMUX.1 | CFG.WLAST |
| TCELL28:IMUX.IMUX.2 | CFG.WID0 |
| TCELL28:IMUX.IMUX.3 | CFG.WID1 |
| TCELL28:IMUX.IMUX.4 | CFG.WID2 |
| TCELL28:IMUX.IMUX.5 | CFG.WID3 |
| TCELL28:IMUX.IMUX.6 | CFG.WID4 |
| TCELL28:IMUX.IMUX.7 | CFG.WID5 |
| TCELL28:IMUX.IMUX.8 | CFG.WID6 |
| TCELL28:IMUX.IMUX.9 | CFG.WID7 |
| TCELL28:IMUX.IMUX.10 | CFG.WDATA0 |
| TCELL28:IMUX.IMUX.11 | CFG.WDATA1 |
| TCELL28:IMUX.IMUX.12 | CFG.WDATA2 |
| TCELL28:IMUX.IMUX.13 | CFG.WDATA3 |
| TCELL28:IMUX.IMUX.14 | CFG.WDATA4 |
| TCELL28:IMUX.IMUX.15 | CFG.WDATA5 |
| TCELL29:IMUX.IMUX.0 | CFG.WDATA6 |
| TCELL29:IMUX.IMUX.1 | CFG.WDATA7 |
| TCELL29:IMUX.IMUX.2 | CFG.WDATA8 |
| TCELL29:IMUX.IMUX.3 | CFG.WDATA9 |
| TCELL29:IMUX.IMUX.4 | CFG.WDATA10 |
| TCELL29:IMUX.IMUX.5 | CFG.WDATA11 |
| TCELL29:IMUX.IMUX.6 | CFG.WDATA12 |
| TCELL29:IMUX.IMUX.7 | CFG.WDATA13 |
| TCELL29:IMUX.IMUX.8 | CFG.WDATA14 |
| TCELL29:IMUX.IMUX.9 | CFG.WDATA15 |
| TCELL29:IMUX.IMUX.10 | CFG.WDATA16 |
| TCELL29:IMUX.IMUX.11 | CFG.WDATA17 |
| TCELL29:IMUX.IMUX.12 | CFG.WDATA18 |
| TCELL29:IMUX.IMUX.13 | CFG.WDATA19 |
| TCELL29:IMUX.IMUX.14 | CFG.WDATA20 |
| TCELL29:IMUX.IMUX.15 | CFG.WDATA21 |
| TCELL30:IMUX.IMUX.0 | CFG.WDATA22 |
| TCELL30:IMUX.IMUX.1 | CFG.WDATA23 |
| TCELL30:IMUX.IMUX.2 | CFG.WDATA24 |
| TCELL30:IMUX.IMUX.3 | CFG.WDATA25 |
| TCELL30:IMUX.IMUX.4 | CFG.WDATA26 |
| TCELL30:IMUX.IMUX.5 | CFG.WDATA27 |
| TCELL30:IMUX.IMUX.6 | CFG.WDATA28 |
| TCELL30:IMUX.IMUX.7 | CFG.WDATA29 |
| TCELL30:IMUX.IMUX.8 | CFG.WDATA30 |
| TCELL30:IMUX.IMUX.9 | CFG.WDATA31 |
| TCELL30:IMUX.IMUX.10 | CFG.WSTRB0 |
| TCELL30:IMUX.IMUX.11 | CFG.WSTRB1 |
| TCELL30:IMUX.IMUX.12 | CFG.WSTRB2 |
| TCELL30:IMUX.IMUX.13 | CFG.WSTRB3 |
| TCELL31:OUT.0 | CFG.RVALID |
| TCELL31:OUT.2 | CFG.RLAST |
| TCELL31:OUT.4 | CFG.RID0 |
| TCELL31:OUT.6 | CFG.RID1 |
| TCELL31:OUT.8 | CFG.RID2 |
| TCELL31:OUT.10 | CFG.RID3 |
| TCELL31:OUT.12 | CFG.RID4 |
| TCELL31:OUT.14 | CFG.RID5 |
| TCELL31:OUT.16 | CFG.RID6 |
| TCELL31:OUT.18 | CFG.RID7 |
| TCELL31:OUT.20 | CFG.RRESP0 |
| TCELL31:OUT.22 | CFG.RRESP1 |
| TCELL31:OUT.24 | CFG.RDATA0 |
| TCELL31:OUT.26 | CFG.RDATA1 |
| TCELL31:OUT.28 | CFG.RDATA2 |
| TCELL31:OUT.30 | CFG.RDATA3 |
| TCELL31:IMUX.IMUX.0 | CFG.RREADY |
| TCELL31:IMUX.IMUX.1 | CFG.ARID0 |
| TCELL31:IMUX.IMUX.2 | CFG.ARID1 |
| TCELL31:IMUX.IMUX.3 | CFG.ARID2 |
| TCELL31:IMUX.IMUX.4 | CFG.ARID3 |
| TCELL31:IMUX.IMUX.5 | CFG.ARID4 |
| TCELL31:IMUX.IMUX.6 | CFG.ARID5 |
| TCELL31:IMUX.IMUX.7 | CFG.ARID6 |
| TCELL31:IMUX.IMUX.8 | CFG.ARID7 |
| TCELL32:OUT.0 | CFG.RDATA4 |
| TCELL32:OUT.2 | CFG.RDATA5 |
| TCELL32:OUT.4 | CFG.RDATA6 |
| TCELL32:OUT.6 | CFG.RDATA7 |
| TCELL32:OUT.8 | CFG.RDATA8 |
| TCELL32:OUT.10 | CFG.RDATA9 |
| TCELL32:OUT.12 | CFG.RDATA10 |
| TCELL32:OUT.14 | CFG.RDATA11 |
| TCELL32:OUT.16 | CFG.RDATA12 |
| TCELL32:OUT.18 | CFG.RDATA13 |
| TCELL32:OUT.20 | CFG.RDATA14 |
| TCELL32:OUT.22 | CFG.RDATA15 |
| TCELL32:OUT.24 | CFG.RDATA16 |
| TCELL32:OUT.26 | CFG.RDATA17 |
| TCELL32:OUT.28 | CFG.RDATA18 |
| TCELL32:OUT.30 | CFG.RDATA19 |
| TCELL32:IMUX.IMUX.1 | CFG.AWID0 |
| TCELL32:IMUX.IMUX.2 | CFG.AWID1 |
| TCELL32:IMUX.IMUX.3 | CFG.AWID2 |
| TCELL32:IMUX.IMUX.4 | CFG.AWID3 |
| TCELL32:IMUX.IMUX.5 | CFG.AWID4 |
| TCELL32:IMUX.IMUX.6 | CFG.AWID5 |
| TCELL32:IMUX.IMUX.7 | CFG.AWID6 |
| TCELL32:IMUX.IMUX.8 | CFG.AWID7 |
| TCELL33:OUT.0 | CFG.RDATA20 |
| TCELL33:OUT.2 | CFG.RDATA21 |
| TCELL33:OUT.4 | CFG.RDATA22 |
| TCELL33:OUT.6 | CFG.RDATA23 |
| TCELL33:OUT.8 | CFG.RDATA24 |
| TCELL33:OUT.10 | CFG.RDATA25 |
| TCELL33:OUT.12 | CFG.RDATA26 |
| TCELL33:OUT.14 | CFG.RDATA27 |
| TCELL33:OUT.16 | CFG.RDATA28 |
| TCELL33:OUT.18 | CFG.RDATA29 |
| TCELL33:OUT.20 | CFG.RDATA30 |
| TCELL33:OUT.22 | CFG.RDATA31 |
| TCELL34:OUT.0 | CFG.BVALID |
| TCELL34:OUT.2 | CFG.BID0 |
| TCELL34:OUT.4 | CFG.BID1 |
| TCELL34:OUT.6 | CFG.BID2 |
| TCELL34:OUT.8 | CFG.BID3 |
| TCELL34:OUT.10 | CFG.BID4 |
| TCELL34:OUT.12 | CFG.BID5 |
| TCELL34:OUT.14 | CFG.BID6 |
| TCELL34:OUT.16 | CFG.BID7 |
| TCELL34:OUT.18 | CFG.BRESP0 |
| TCELL34:OUT.20 | CFG.BRESP1 |
| TCELL34:IMUX.IMUX.0 | CFG.BREADY |
| TCELL41:OUT.0 | CFG.USR_EFUSE16 |
| TCELL41:OUT.2 | CFG.USR_EFUSE17 |
| TCELL41:OUT.4 | CFG.USR_EFUSE18 |
| TCELL41:OUT.6 | CFG.USR_EFUSE19 |
| TCELL41:OUT.8 | CFG.USR_EFUSE20 |
| TCELL41:OUT.10 | CFG.USR_EFUSE21 |
| TCELL41:OUT.12 | CFG.USR_EFUSE22 |
| TCELL41:OUT.14 | CFG.USR_EFUSE23 |
| TCELL41:OUT.16 | CFG.USR_EFUSE24 |
| TCELL41:OUT.18 | CFG.USR_EFUSE25 |
| TCELL41:OUT.20 | CFG.USR_EFUSE26 |
| TCELL41:OUT.22 | CFG.USR_EFUSE27 |
| TCELL41:OUT.24 | CFG.USR_EFUSE28 |
| TCELL41:OUT.26 | CFG.USR_EFUSE29 |
| TCELL41:OUT.28 | CFG.USR_EFUSE30 |
| TCELL41:OUT.30 | CFG.USR_EFUSE31 |
| TCELL42:OUT.0 | CFG.USR_DNA_OUT |
| TCELL42:OUT.2 | CFG.DCI_LOCK |
| TCELL42:OUT.4 | CFG.BSCAN_CDR1 |
| TCELL42:OUT.6 | CFG.BSCAN_CDR2 |
| TCELL42:OUT.8 | CFG.BSCAN_CLKDR1 |
| TCELL42:OUT.10 | CFG.BSCAN_CLKDR2 |
| TCELL42:OUT.12 | CFG.BSCAN_RTI1 |
| TCELL42:OUT.14 | CFG.BSCAN_RTI2 |
| TCELL42:OUT.16 | CFG.BSCAN_SDR1 |
| TCELL42:OUT.18 | CFG.BSCAN_SDR2 |
| TCELL42:OUT.20 | CFG.BSCAN_SEL1 |
| TCELL42:OUT.22 | CFG.BSCAN_SEL2 |
| TCELL42:OUT.24 | CFG.BSCAN_TLR1 |
| TCELL42:OUT.26 | CFG.BSCAN_TLR2 |
| TCELL42:OUT.28 | CFG.BSCAN_UDR1 |
| TCELL42:OUT.30 | CFG.BSCAN_UDR2 |
| TCELL42:IMUX.CTRL.0 | CFG.USR_DNA_CLK |
| TCELL42:IMUX.IMUX.0 | CFG.USR_DNA_DIN |
| TCELL42:IMUX.IMUX.1 | CFG.USR_DNA_READ |
| TCELL42:IMUX.IMUX.2 | CFG.USR_DNA_SHIFT |
| TCELL42:IMUX.IMUX.3 | CFG.DCI_USR_RESET_IN |
| TCELL43:OUT.0 | CFG.ICAP_PR_DONE_BOT |
| TCELL43:OUT.2 | CFG.ICAP_PR_ERROR_BOT |
| TCELL43:OUT.4 | CFG.ICAP_AVAIL_BOT |
| TCELL43:OUT.6 | CFG.BSCAN_TCK1 |
| TCELL43:OUT.8 | CFG.BSCAN_TCK2 |
| TCELL43:OUT.10 | CFG.BSCAN_TMS1 |
| TCELL43:OUT.12 | CFG.BSCAN_TMS2 |
| TCELL43:OUT.14 | CFG.BSCAN_TDI1 |
| TCELL43:OUT.16 | CFG.BSCAN_TDI2 |
| TCELL43:OUT.18 | CFG.USR_TDO |
| TCELL43:IMUX.CTRL.1 | CFG.USR_TCK |
| TCELL43:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_BOT |
| TCELL43:IMUX.IMUX.1 | CFG.ICAP_CS_B_BOT |
| TCELL43:IMUX.IMUX.2 | CFG.BSCAN_TDO1 |
| TCELL43:IMUX.IMUX.3 | CFG.BSCAN_TDO2 |
| TCELL43:IMUX.IMUX.5 | CFG.USR_TMS |
| TCELL43:IMUX.IMUX.6 | CFG.USR_TDI |
| TCELL44:OUT.0 | CFG.ICAP_OUT_BOT0 |
| TCELL44:OUT.2 | CFG.ICAP_OUT_BOT1 |
| TCELL44:OUT.4 | CFG.ICAP_OUT_BOT2 |
| TCELL44:OUT.6 | CFG.ICAP_OUT_BOT3 |
| TCELL44:OUT.8 | CFG.ICAP_OUT_BOT4 |
| TCELL44:OUT.10 | CFG.ICAP_OUT_BOT5 |
| TCELL44:OUT.12 | CFG.ICAP_OUT_BOT6 |
| TCELL44:OUT.14 | CFG.ICAP_OUT_BOT7 |
| TCELL44:OUT.16 | CFG.ICAP_OUT_BOT8 |
| TCELL44:OUT.18 | CFG.ICAP_OUT_BOT9 |
| TCELL44:OUT.20 | CFG.ICAP_OUT_BOT10 |
| TCELL44:OUT.22 | CFG.ICAP_OUT_BOT11 |
| TCELL44:OUT.24 | CFG.ICAP_OUT_BOT12 |
| TCELL44:OUT.26 | CFG.ICAP_OUT_BOT13 |
| TCELL44:OUT.28 | CFG.ICAP_OUT_BOT14 |
| TCELL44:OUT.30 | CFG.ICAP_OUT_BOT15 |
| TCELL44:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT0 |
| TCELL44:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT1 |
| TCELL44:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT2 |
| TCELL44:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT3 |
| TCELL44:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT4 |
| TCELL44:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT5 |
| TCELL44:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT6 |
| TCELL44:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT7 |
| TCELL44:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT8 |
| TCELL44:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT9 |
| TCELL44:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT10 |
| TCELL44:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT11 |
| TCELL44:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT12 |
| TCELL44:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT13 |
| TCELL44:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT14 |
| TCELL44:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT15 |
| TCELL45:OUT.0 | CFG.ICAP_OUT_BOT16 |
| TCELL45:OUT.2 | CFG.ICAP_OUT_BOT17 |
| TCELL45:OUT.4 | CFG.ICAP_OUT_BOT18 |
| TCELL45:OUT.6 | CFG.ICAP_OUT_BOT19 |
| TCELL45:OUT.8 | CFG.ICAP_OUT_BOT20 |
| TCELL45:OUT.10 | CFG.ICAP_OUT_BOT21 |
| TCELL45:OUT.12 | CFG.ICAP_OUT_BOT22 |
| TCELL45:OUT.14 | CFG.ICAP_OUT_BOT23 |
| TCELL45:OUT.16 | CFG.ICAP_OUT_BOT24 |
| TCELL45:OUT.18 | CFG.ICAP_OUT_BOT25 |
| TCELL45:OUT.20 | CFG.ICAP_OUT_BOT26 |
| TCELL45:OUT.22 | CFG.ICAP_OUT_BOT27 |
| TCELL45:OUT.24 | CFG.ICAP_OUT_BOT28 |
| TCELL45:OUT.26 | CFG.ICAP_OUT_BOT29 |
| TCELL45:OUT.28 | CFG.ICAP_OUT_BOT30 |
| TCELL45:OUT.30 | CFG.ICAP_OUT_BOT31 |
| TCELL45:IMUX.CTRL.0 | CFG.ICAP_CLK_BOT |
| TCELL45:IMUX.IMUX.0 | CFG.ICAP_DATA_BOT16 |
| TCELL45:IMUX.IMUX.1 | CFG.ICAP_DATA_BOT17 |
| TCELL45:IMUX.IMUX.2 | CFG.ICAP_DATA_BOT18 |
| TCELL45:IMUX.IMUX.3 | CFG.ICAP_DATA_BOT19 |
| TCELL45:IMUX.IMUX.4 | CFG.ICAP_DATA_BOT20 |
| TCELL45:IMUX.IMUX.5 | CFG.ICAP_DATA_BOT21 |
| TCELL45:IMUX.IMUX.6 | CFG.ICAP_DATA_BOT22 |
| TCELL45:IMUX.IMUX.7 | CFG.ICAP_DATA_BOT23 |
| TCELL45:IMUX.IMUX.8 | CFG.ICAP_DATA_BOT24 |
| TCELL45:IMUX.IMUX.9 | CFG.ICAP_DATA_BOT25 |
| TCELL45:IMUX.IMUX.10 | CFG.ICAP_DATA_BOT26 |
| TCELL45:IMUX.IMUX.11 | CFG.ICAP_DATA_BOT27 |
| TCELL45:IMUX.IMUX.12 | CFG.ICAP_DATA_BOT28 |
| TCELL45:IMUX.IMUX.13 | CFG.ICAP_DATA_BOT29 |
| TCELL45:IMUX.IMUX.14 | CFG.ICAP_DATA_BOT30 |
| TCELL45:IMUX.IMUX.15 | CFG.ICAP_DATA_BOT31 |
| TCELL46:OUT.0 | CFG.USR_EFUSE0 |
| TCELL46:OUT.2 | CFG.USR_EFUSE1 |
| TCELL46:OUT.4 | CFG.USR_EFUSE2 |
| TCELL46:OUT.6 | CFG.USR_EFUSE3 |
| TCELL46:OUT.8 | CFG.USR_EFUSE4 |
| TCELL46:OUT.10 | CFG.USR_EFUSE5 |
| TCELL46:OUT.12 | CFG.USR_EFUSE6 |
| TCELL46:OUT.14 | CFG.USR_EFUSE7 |
| TCELL46:OUT.16 | CFG.USR_EFUSE8 |
| TCELL46:OUT.18 | CFG.USR_EFUSE9 |
| TCELL46:OUT.20 | CFG.USR_EFUSE10 |
| TCELL46:OUT.22 | CFG.USR_EFUSE11 |
| TCELL46:OUT.24 | CFG.USR_EFUSE12 |
| TCELL46:OUT.26 | CFG.USR_EFUSE13 |
| TCELL46:OUT.28 | CFG.USR_EFUSE14 |
| TCELL46:OUT.30 | CFG.USR_EFUSE15 |
| TCELL47:OUT.0 | CFG.USR_D_PIN_CFGIO0 |
| TCELL47:OUT.2 | CFG.USR_D_PIN_CFGIO1 |
| TCELL47:OUT.4 | CFG.USR_D_PIN_CFGIO2 |
| TCELL47:OUT.6 | CFG.USR_D_PIN_CFGIO3 |
| TCELL47:OUT.8 | CFG.PROG_REQ |
| TCELL47:OUT.10 | CFG.EOS |
| TCELL47:OUT.12 | CFG.START_CFG_MCLK |
| TCELL47:OUT.14 | CFG.START_CFG_CLK |
| TCELL47:IMUX.CTRL.0 | CFG.USR_CCLK_O |
| TCELL47:IMUX.IMUX.0 | CFG.KEY_CLEAR_B |
| TCELL47:IMUX.IMUX.1 | CFG.PROG_ACK |
| TCELL47:IMUX.IMUX.2 | CFG.USR_CCLK_TS |
| TCELL47:IMUX.IMUX.3 | CFG.USR_DONE_O |
| TCELL47:IMUX.IMUX.4 | CFG.USR_DONE_TS |
| TCELL47:IMUX.IMUX.5 | CFG.USR_GSR |
| TCELL47:IMUX.IMUX.6 | CFG.USR_GTS |
| TCELL47:IMUX.IMUX.7 | CFG.USR_FCS_B_O |
| TCELL47:IMUX.IMUX.8 | CFG.USR_FCS_B_TS |
| TCELL47:IMUX.IMUX.9 | CFG.USR_D_O_CFGIO0 |
| TCELL47:IMUX.IMUX.10 | CFG.USR_D_O_CFGIO1 |
| TCELL47:IMUX.IMUX.11 | CFG.USR_D_O_CFGIO2 |
| TCELL47:IMUX.IMUX.12 | CFG.USR_D_O_CFGIO3 |
| TCELL47:IMUX.IMUX.13 | CFG.USR_D_TS_CFGIO0 |
| TCELL47:IMUX.IMUX.14 | CFG.USR_D_TS_CFGIO1 |
| TCELL47:IMUX.IMUX.15 | CFG.USR_D_TS_CFGIO2 |
| TCELL47:IMUX.IMUX.16 | CFG.USR_D_TS_CFGIO3 |
| TCELL48:OUT.0 | CFG.IOX_CFGDATA0 |
| TCELL48:OUT.2 | CFG.IOX_CFGDATA1 |
| TCELL48:OUT.4 | CFG.IOX_CFGDATA2 |
| TCELL48:OUT.6 | CFG.IOX_CFGDATA3 |
| TCELL48:OUT.8 | CFG.IOX_CFGDATA4 |
| TCELL48:OUT.10 | CFG.IOX_CFGDATA5 |
| TCELL48:OUT.12 | CFG.IOX_CFGDATA6 |
| TCELL48:OUT.14 | CFG.IOX_CFGDATA7 |
| TCELL48:OUT.16 | CFG.IOX_CFGDATA8 |
| TCELL48:OUT.18 | CFG.IOX_CFGDATA9 |
| TCELL48:OUT.20 | CFG.IOX_CFGDATA10 |
| TCELL48:OUT.22 | CFG.IOX_CFGDATA11 |
| TCELL48:OUT.24 | CFG.IOX_CFGDATA12 |
| TCELL48:OUT.26 | CFG.IOX_CFGDATA13 |
| TCELL48:OUT.28 | CFG.IOX_CFGDATA14 |
| TCELL48:OUT.30 | CFG.IOX_CFGDATA15 |
| TCELL48:IMUX.IMUX.0 | CFG.IOX_TDO |
| TCELL48:IMUX.IMUX.1 | CFG.IOX_INITBO |
| TCELL49:OUT.0 | CFG.IOX_CFGDATA16 |
| TCELL49:OUT.2 | CFG.IOX_CFGDATA17 |
| TCELL49:OUT.4 | CFG.IOX_CFGDATA18 |
| TCELL49:OUT.6 | CFG.IOX_CFGDATA19 |
| TCELL49:OUT.8 | CFG.IOX_CFGDATA20 |
| TCELL49:OUT.10 | CFG.IOX_CFGDATA21 |
| TCELL49:OUT.12 | CFG.IOX_CFGDATA22 |
| TCELL49:OUT.14 | CFG.IOX_CFGDATA23 |
| TCELL49:OUT.16 | CFG.IOX_CFGDATA24 |
| TCELL49:OUT.18 | CFG.IOX_CFGDATA25 |
| TCELL49:OUT.20 | CFG.IOX_CFGDATA26 |
| TCELL49:OUT.22 | CFG.IOX_CFGDATA27 |
| TCELL49:OUT.24 | CFG.IOX_CFGDATA28 |
| TCELL49:OUT.26 | CFG.IOX_CFGDATA29 |
| TCELL49:OUT.28 | CFG.IOX_CFGDATA30 |
| TCELL49:OUT.30 | CFG.IOX_CFGDATA31 |
| TCELL50:OUT.0 | CFG.IOX_CCLK |
| TCELL50:OUT.2 | CFG.IOX_CFGMASTER |
| TCELL50:OUT.4 | CFG.IOX_VGG_COMP_OUT |
| TCELL50:OUT.6 | CFG.IOX_INITBI |
| TCELL50:OUT.8 | CFG.IOX_PUDCB |
| TCELL50:OUT.10 | CFG.IOX_RDWRB |
| TCELL50:OUT.12 | CFG.IOX_MODE0 |
| TCELL50:OUT.14 | CFG.IOX_MODE1 |
| TCELL50:OUT.16 | CFG.IOX_MODE2 |
| TCELL51:OUT.0 | CFG.ECC_FAR16 |
| TCELL51:OUT.2 | CFG.ECC_FAR17 |
| TCELL51:OUT.4 | CFG.ECC_FAR18 |
| TCELL51:OUT.6 | CFG.ECC_FAR19 |
| TCELL51:OUT.8 | CFG.ECC_FAR20 |
| TCELL51:OUT.10 | CFG.ECC_FAR21 |
| TCELL51:OUT.12 | CFG.ECC_FAR22 |
| TCELL51:OUT.14 | CFG.ECC_FAR23 |
| TCELL51:OUT.16 | CFG.ECC_FAR24 |
| TCELL51:OUT.18 | CFG.ECC_FAR25 |
| TCELL51:OUT.20 | CFG.RBCRC_ERROR |
| TCELL51:OUT.22 | CFG.ECC_ERROR_NOTSINGLE |
| TCELL51:OUT.24 | CFG.ECC_ERROR_SINGLE |
| TCELL51:OUT.26 | CFG.ECC_END_OF_FRAME |
| TCELL51:OUT.28 | CFG.ECC_END_OF_SCAN |
| TCELL51:IMUX.IMUX.15 | CFG.ECC_FAR_SEL0 |
| TCELL51:IMUX.IMUX.16 | CFG.ECC_FAR_SEL1 |
| TCELL52:OUT.0 | CFG.ECC_FAR0 |
| TCELL52:OUT.2 | CFG.ECC_FAR1 |
| TCELL52:OUT.4 | CFG.ECC_FAR2 |
| TCELL52:OUT.6 | CFG.ECC_FAR3 |
| TCELL52:OUT.8 | CFG.ECC_FAR4 |
| TCELL52:OUT.10 | CFG.ECC_FAR5 |
| TCELL52:OUT.12 | CFG.ECC_FAR6 |
| TCELL52:OUT.14 | CFG.ECC_FAR7 |
| TCELL52:OUT.16 | CFG.ECC_FAR8 |
| TCELL52:OUT.18 | CFG.ECC_FAR9 |
| TCELL52:OUT.20 | CFG.ECC_FAR10 |
| TCELL52:OUT.22 | CFG.ECC_FAR11 |
| TCELL52:OUT.24 | CFG.ECC_FAR12 |
| TCELL52:OUT.26 | CFG.ECC_FAR13 |
| TCELL52:OUT.28 | CFG.ECC_FAR14 |
| TCELL52:OUT.30 | CFG.ECC_FAR15 |
| TCELL52:OUT.31 | CFG.ECC_FAR26 |
| TCELL53:OUT.0 | CFG.BSCAN_SDR3 |
| TCELL53:OUT.2 | CFG.BSCAN_SDR4 |
| TCELL53:OUT.4 | CFG.BSCAN_SEL3 |
| TCELL53:OUT.6 | CFG.BSCAN_SEL4 |
| TCELL53:OUT.8 | CFG.BSCAN_TLR3 |
| TCELL53:OUT.10 | CFG.BSCAN_TLR4 |
| TCELL53:OUT.12 | CFG.BSCAN_UDR3 |
| TCELL53:OUT.14 | CFG.BSCAN_UDR4 |
| TCELL54:OUT.0 | CFG.ICAP_PR_DONE_TOP |
| TCELL54:OUT.2 | CFG.ICAP_PR_ERROR_TOP |
| TCELL54:OUT.4 | CFG.ICAP_AVAIL_TOP |
| TCELL54:OUT.6 | CFG.BSCAN_TCK3 |
| TCELL54:OUT.8 | CFG.BSCAN_TCK4 |
| TCELL54:OUT.10 | CFG.BSCAN_TMS3 |
| TCELL54:OUT.12 | CFG.BSCAN_TMS4 |
| TCELL54:OUT.14 | CFG.BSCAN_TDI3 |
| TCELL54:OUT.16 | CFG.BSCAN_TDI4 |
| TCELL54:OUT.18 | CFG.BSCAN_CDR3 |
| TCELL54:OUT.20 | CFG.BSCAN_CDR4 |
| TCELL54:OUT.22 | CFG.BSCAN_CLKDR3 |
| TCELL54:OUT.24 | CFG.BSCAN_CLKDR4 |
| TCELL54:OUT.26 | CFG.BSCAN_RTI3 |
| TCELL54:OUT.28 | CFG.BSCAN_RTI4 |
| TCELL54:IMUX.IMUX.0 | CFG.ICAP_RDWR_B_TOP |
| TCELL54:IMUX.IMUX.1 | CFG.ICAP_CS_B_TOP |
| TCELL54:IMUX.IMUX.2 | CFG.BSCAN_TDO3 |
| TCELL54:IMUX.IMUX.3 | CFG.BSCAN_TDO4 |
| TCELL55:OUT.0 | CFG.ICAP_OUT_TOP0 |
| TCELL55:OUT.2 | CFG.ICAP_OUT_TOP1 |
| TCELL55:OUT.4 | CFG.ICAP_OUT_TOP2 |
| TCELL55:OUT.6 | CFG.ICAP_OUT_TOP3 |
| TCELL55:OUT.8 | CFG.ICAP_OUT_TOP4 |
| TCELL55:OUT.10 | CFG.ICAP_OUT_TOP5 |
| TCELL55:OUT.12 | CFG.ICAP_OUT_TOP6 |
| TCELL55:OUT.14 | CFG.ICAP_OUT_TOP7 |
| TCELL55:OUT.16 | CFG.ICAP_OUT_TOP8 |
| TCELL55:OUT.18 | CFG.ICAP_OUT_TOP9 |
| TCELL55:OUT.20 | CFG.ICAP_OUT_TOP10 |
| TCELL55:OUT.22 | CFG.ICAP_OUT_TOP11 |
| TCELL55:OUT.24 | CFG.ICAP_OUT_TOP12 |
| TCELL55:OUT.26 | CFG.ICAP_OUT_TOP13 |
| TCELL55:OUT.28 | CFG.ICAP_OUT_TOP14 |
| TCELL55:OUT.30 | CFG.ICAP_OUT_TOP15 |
| TCELL55:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP0 |
| TCELL55:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP1 |
| TCELL55:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP2 |
| TCELL55:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP3 |
| TCELL55:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP4 |
| TCELL55:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP5 |
| TCELL55:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP6 |
| TCELL55:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP7 |
| TCELL55:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP8 |
| TCELL55:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP9 |
| TCELL55:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP10 |
| TCELL55:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP11 |
| TCELL55:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP12 |
| TCELL55:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP13 |
| TCELL55:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP14 |
| TCELL55:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP15 |
| TCELL56:OUT.0 | CFG.ICAP_OUT_TOP16 |
| TCELL56:OUT.2 | CFG.ICAP_OUT_TOP17 |
| TCELL56:OUT.4 | CFG.ICAP_OUT_TOP18 |
| TCELL56:OUT.6 | CFG.ICAP_OUT_TOP19 |
| TCELL56:OUT.8 | CFG.ICAP_OUT_TOP20 |
| TCELL56:OUT.10 | CFG.ICAP_OUT_TOP21 |
| TCELL56:OUT.12 | CFG.ICAP_OUT_TOP22 |
| TCELL56:OUT.14 | CFG.ICAP_OUT_TOP23 |
| TCELL56:OUT.16 | CFG.ICAP_OUT_TOP24 |
| TCELL56:OUT.18 | CFG.ICAP_OUT_TOP25 |
| TCELL56:OUT.20 | CFG.ICAP_OUT_TOP26 |
| TCELL56:OUT.22 | CFG.ICAP_OUT_TOP27 |
| TCELL56:OUT.24 | CFG.ICAP_OUT_TOP28 |
| TCELL56:OUT.26 | CFG.ICAP_OUT_TOP29 |
| TCELL56:OUT.28 | CFG.ICAP_OUT_TOP30 |
| TCELL56:OUT.30 | CFG.ICAP_OUT_TOP31 |
| TCELL56:IMUX.CTRL.0 | CFG.ICAP_CLK_TOP |
| TCELL56:IMUX.IMUX.0 | CFG.ICAP_DATA_TOP16 |
| TCELL56:IMUX.IMUX.1 | CFG.ICAP_DATA_TOP17 |
| TCELL56:IMUX.IMUX.2 | CFG.ICAP_DATA_TOP18 |
| TCELL56:IMUX.IMUX.3 | CFG.ICAP_DATA_TOP19 |
| TCELL56:IMUX.IMUX.4 | CFG.ICAP_DATA_TOP20 |
| TCELL56:IMUX.IMUX.5 | CFG.ICAP_DATA_TOP21 |
| TCELL56:IMUX.IMUX.6 | CFG.ICAP_DATA_TOP22 |
| TCELL56:IMUX.IMUX.7 | CFG.ICAP_DATA_TOP23 |
| TCELL56:IMUX.IMUX.8 | CFG.ICAP_DATA_TOP24 |
| TCELL56:IMUX.IMUX.9 | CFG.ICAP_DATA_TOP25 |
| TCELL56:IMUX.IMUX.10 | CFG.ICAP_DATA_TOP26 |
| TCELL56:IMUX.IMUX.11 | CFG.ICAP_DATA_TOP27 |
| TCELL56:IMUX.IMUX.12 | CFG.ICAP_DATA_TOP28 |
| TCELL56:IMUX.IMUX.13 | CFG.ICAP_DATA_TOP29 |
| TCELL56:IMUX.IMUX.14 | CFG.ICAP_DATA_TOP30 |
| TCELL56:IMUX.IMUX.15 | CFG.ICAP_DATA_TOP31 |
| TCELL57:OUT.0 | CFG.USR_ACCESS_VALID |
| TCELL57:OUT.2 | CFG.USR_ACCESS_CLK |
| TCELL58:OUT.0 | CFG.USR_ACCESS_DATA0 |
| TCELL58:OUT.2 | CFG.USR_ACCESS_DATA1 |
| TCELL58:OUT.4 | CFG.USR_ACCESS_DATA2 |
| TCELL58:OUT.6 | CFG.USR_ACCESS_DATA3 |
| TCELL58:OUT.8 | CFG.USR_ACCESS_DATA4 |
| TCELL58:OUT.10 | CFG.USR_ACCESS_DATA5 |
| TCELL58:OUT.12 | CFG.USR_ACCESS_DATA6 |
| TCELL58:OUT.14 | CFG.USR_ACCESS_DATA7 |
| TCELL58:OUT.16 | CFG.USR_ACCESS_DATA8 |
| TCELL58:OUT.18 | CFG.USR_ACCESS_DATA9 |
| TCELL58:OUT.20 | CFG.USR_ACCESS_DATA10 |
| TCELL58:OUT.22 | CFG.USR_ACCESS_DATA11 |
| TCELL58:OUT.24 | CFG.USR_ACCESS_DATA12 |
| TCELL58:OUT.26 | CFG.USR_ACCESS_DATA13 |
| TCELL58:OUT.28 | CFG.USR_ACCESS_DATA14 |
| TCELL58:OUT.30 | CFG.USR_ACCESS_DATA15 |
| TCELL59:OUT.0 | CFG.USR_ACCESS_DATA16 |
| TCELL59:OUT.2 | CFG.USR_ACCESS_DATA17 |
| TCELL59:OUT.4 | CFG.USR_ACCESS_DATA18 |
| TCELL59:OUT.6 | CFG.USR_ACCESS_DATA19 |
| TCELL59:OUT.8 | CFG.USR_ACCESS_DATA20 |
| TCELL59:OUT.10 | CFG.USR_ACCESS_DATA21 |
| TCELL59:OUT.12 | CFG.USR_ACCESS_DATA22 |
| TCELL59:OUT.14 | CFG.USR_ACCESS_DATA23 |
| TCELL59:OUT.16 | CFG.USR_ACCESS_DATA24 |
| TCELL59:OUT.18 | CFG.USR_ACCESS_DATA25 |
| TCELL59:OUT.20 | CFG.USR_ACCESS_DATA26 |
| TCELL59:OUT.22 | CFG.USR_ACCESS_DATA27 |
| TCELL59:OUT.24 | CFG.USR_ACCESS_DATA28 |
| TCELL59:OUT.26 | CFG.USR_ACCESS_DATA29 |
| TCELL59:OUT.28 | CFG.USR_ACCESS_DATA30 |
| TCELL59:OUT.30 | CFG.USR_ACCESS_DATA31 |
Tile CFGIO
Cells: 30 IRIs: 0
Bel PMV
| Pin | Direction | Wires |
|---|---|---|
| OUT1_INTOP | output | TCELL29:OUT.18 |
| OUT2_INTOP | output | TCELL29:OUT.17 |
| OUT3_INTOP | output | TCELL29:OUT.21 |
| OUT4_INTOP | output | TCELL29:OUT.20 |
| PMV_EN1_INTIP | input | TCELL29:IMUX.IMUX.43 |
| SPARE_IN1_INTIP0 | input | TCELL29:IMUX.IMUX.44 |
| SPARE_IN1_INTIP1 | input | TCELL29:IMUX.IMUX.13 |
| SPARE_IN1_INTIP2 | input | TCELL29:IMUX.IMUX.45 |
| SPARE_IN1_INTIP3 | input | TCELL29:IMUX.IMUX.46 |
| SPARE_IN1_INTIP4 | input | TCELL29:IMUX.IMUX.47 |
| SPARE_IN1_INTIP5 | input | TCELL29:IMUX.IMUX.14 |
Bel PMV2
| Pin | Direction | Wires |
|---|---|---|
| IMUX_IN_INT0 | input | TCELL28:IMUX.IMUX.38 |
| IMUX_IN_INT1 | input | TCELL28:IMUX.IMUX.41 |
| IMUX_IN_INT2 | input | TCELL28:IMUX.IMUX.40 |
| IMUX_IN_INT3 | input | TCELL28:IMUX.IMUX.39 |
| OUTS_INT0 | output | TCELL28:OUT.8 |
| OUTS_INT1 | output | TCELL28:OUT.4 |
| OUTS_INT2 | output | TCELL28:OUT.3 |
Bel PMVIOB
| Pin | Direction | Wires |
|---|---|---|
| OUT_DIV2_HPIO_INTOP | output | TCELL27:OUT.1 |
| OUT_DIV4_HPIO_INTOP | output | TCELL27:OUT.0 |
| OUT_HPIO_INTOP | output | TCELL27:OUT.2 |
| PMV_A_HPIO_INTIP0 | input | TCELL27:IMUX.IMUX.0 |
| PMV_A_HPIO_INTIP1 | input | TCELL27:IMUX.IMUX.1 |
| PMV_EN_HPIO_INTIP | input | TCELL27:IMUX.IMUX.2 |
Bel MTBF3
| Pin | Direction | Wires |
|---|---|---|
| CAPTURE_CLK_INTIP | input | TCELL27:IMUX.IMUX.24 |
| CAPTURE_Q_INTOP0 | output | TCELL27:OUT.27 |
| CAPTURE_Q_INTOP1 | output | TCELL27:OUT.28 |
| CAPTURE_Q_INTOP2 | output | TCELL27:OUT.29 |
| CAPTURE_Q_INTOP3 | output | TCELL27:OUT.30 |
| CAPTURE_Q_INTOP4 | output | TCELL27:OUT.31 |
| DATAIN_INTIP | input | TCELL27:IMUX.IMUX.26 |
| FF_CLK_INTIP | input | TCELL27:IMUX.IMUX.25 |
| FF_Q_INTOP0 | output | TCELL27:OUT.22 |
| FF_Q_INTOP1 | output | TCELL27:OUT.23 |
| FF_Q_INTOP2 | output | TCELL27:OUT.24 |
| FF_Q_INTOP3 | output | TCELL27:OUT.25 |
| FF_Q_INTOP4 | output | TCELL27:OUT.26 |
| OUTPUT_SEL_INTIP0 | input | TCELL27:IMUX.IMUX.28 |
| OUTPUT_SEL_INTIP1 | input | TCELL27:IMUX.IMUX.29 |
| OUTPUT_SEL_INTIP2 | input | TCELL27:IMUX.IMUX.30 |
| OUTPUT_SEL_INTIP3 | input | TCELL27:IMUX.IMUX.31 |
| RESET_INTIP | input | TCELL27:IMUX.IMUX.27 |
| SYNC_ENABLE_INTIP | input | TCELL27:IMUX.IMUX.5 |
| TOGGLE_SEL_INTIP | input | TCELL27:IMUX.IMUX.4 |
Bel CFGIO
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL27:OUT.0 | PMVIOB.OUT_DIV4_HPIO_INTOP |
| TCELL27:OUT.1 | PMVIOB.OUT_DIV2_HPIO_INTOP |
| TCELL27:OUT.2 | PMVIOB.OUT_HPIO_INTOP |
| TCELL27:OUT.22 | MTBF3.FF_Q_INTOP0 |
| TCELL27:OUT.23 | MTBF3.FF_Q_INTOP1 |
| TCELL27:OUT.24 | MTBF3.FF_Q_INTOP2 |
| TCELL27:OUT.25 | MTBF3.FF_Q_INTOP3 |
| TCELL27:OUT.26 | MTBF3.FF_Q_INTOP4 |
| TCELL27:OUT.27 | MTBF3.CAPTURE_Q_INTOP0 |
| TCELL27:OUT.28 | MTBF3.CAPTURE_Q_INTOP1 |
| TCELL27:OUT.29 | MTBF3.CAPTURE_Q_INTOP2 |
| TCELL27:OUT.30 | MTBF3.CAPTURE_Q_INTOP3 |
| TCELL27:OUT.31 | MTBF3.CAPTURE_Q_INTOP4 |
| TCELL27:IMUX.IMUX.0 | PMVIOB.PMV_A_HPIO_INTIP0 |
| TCELL27:IMUX.IMUX.1 | PMVIOB.PMV_A_HPIO_INTIP1 |
| TCELL27:IMUX.IMUX.2 | PMVIOB.PMV_EN_HPIO_INTIP |
| TCELL27:IMUX.IMUX.4 | MTBF3.TOGGLE_SEL_INTIP |
| TCELL27:IMUX.IMUX.5 | MTBF3.SYNC_ENABLE_INTIP |
| TCELL27:IMUX.IMUX.24 | MTBF3.CAPTURE_CLK_INTIP |
| TCELL27:IMUX.IMUX.25 | MTBF3.FF_CLK_INTIP |
| TCELL27:IMUX.IMUX.26 | MTBF3.DATAIN_INTIP |
| TCELL27:IMUX.IMUX.27 | MTBF3.RESET_INTIP |
| TCELL27:IMUX.IMUX.28 | MTBF3.OUTPUT_SEL_INTIP0 |
| TCELL27:IMUX.IMUX.29 | MTBF3.OUTPUT_SEL_INTIP1 |
| TCELL27:IMUX.IMUX.30 | MTBF3.OUTPUT_SEL_INTIP2 |
| TCELL27:IMUX.IMUX.31 | MTBF3.OUTPUT_SEL_INTIP3 |
| TCELL28:OUT.3 | PMV2.OUTS_INT2 |
| TCELL28:OUT.4 | PMV2.OUTS_INT1 |
| TCELL28:OUT.8 | PMV2.OUTS_INT0 |
| TCELL28:IMUX.IMUX.38 | PMV2.IMUX_IN_INT0 |
| TCELL28:IMUX.IMUX.39 | PMV2.IMUX_IN_INT3 |
| TCELL28:IMUX.IMUX.40 | PMV2.IMUX_IN_INT2 |
| TCELL28:IMUX.IMUX.41 | PMV2.IMUX_IN_INT1 |
| TCELL29:OUT.17 | PMV.OUT2_INTOP |
| TCELL29:OUT.18 | PMV.OUT1_INTOP |
| TCELL29:OUT.20 | PMV.OUT4_INTOP |
| TCELL29:OUT.21 | PMV.OUT3_INTOP |
| TCELL29:IMUX.IMUX.13 | PMV.SPARE_IN1_INTIP1 |
| TCELL29:IMUX.IMUX.14 | PMV.SPARE_IN1_INTIP5 |
| TCELL29:IMUX.IMUX.43 | PMV.PMV_EN1_INTIP |
| TCELL29:IMUX.IMUX.44 | PMV.SPARE_IN1_INTIP0 |
| TCELL29:IMUX.IMUX.45 | PMV.SPARE_IN1_INTIP2 |
| TCELL29:IMUX.IMUX.46 | PMV.SPARE_IN1_INTIP3 |
| TCELL29:IMUX.IMUX.47 | PMV.SPARE_IN1_INTIP4 |
Tile AMS
Cells: 30 IRIs: 0
Bel SYSMON
| Pin | Direction | Wires |
|---|---|---|
| ADC_DATA0 | output | TCELL6:OUT.21 |
| ADC_DATA1 | output | TCELL6:OUT.23 |
| ADC_DATA10 | output | TCELL7:OUT.9 |
| ADC_DATA11 | output | TCELL7:OUT.11 |
| ADC_DATA12 | output | TCELL7:OUT.13 |
| ADC_DATA13 | output | TCELL7:OUT.15 |
| ADC_DATA14 | output | TCELL7:OUT.17 |
| ADC_DATA15 | output | TCELL7:OUT.19 |
| ADC_DATA2 | output | TCELL6:OUT.25 |
| ADC_DATA3 | output | TCELL6:OUT.27 |
| ADC_DATA4 | output | TCELL6:OUT.29 |
| ADC_DATA5 | output | TCELL6:OUT.31 |
| ADC_DATA6 | output | TCELL7:OUT.1 |
| ADC_DATA7 | output | TCELL7:OUT.3 |
| ADC_DATA8 | output | TCELL7:OUT.5 |
| ADC_DATA9 | output | TCELL7:OUT.7 |
| ALM0 | output | TCELL5:OUT.21 |
| ALM1 | output | TCELL5:OUT.23 |
| ALM10 | output | TCELL6:OUT.9 |
| ALM11 | output | TCELL6:OUT.11 |
| ALM12 | output | TCELL6:OUT.13 |
| ALM13 | output | TCELL6:OUT.15 |
| ALM14 | output | TCELL6:OUT.17 |
| ALM15 | output | TCELL6:OUT.19 |
| ALM2 | output | TCELL5:OUT.25 |
| ALM3 | output | TCELL5:OUT.27 |
| ALM4 | output | TCELL5:OUT.29 |
| ALM5 | output | TCELL5:OUT.31 |
| ALM6 | output | TCELL6:OUT.1 |
| ALM7 | output | TCELL6:OUT.3 |
| ALM8 | output | TCELL6:OUT.5 |
| ALM9 | output | TCELL6:OUT.7 |
| BUSY | output | TCELL5:OUT.19 |
| CHANNEL0 | output | TCELL5:OUT.7 |
| CHANNEL1 | output | TCELL5:OUT.9 |
| CHANNEL2 | output | TCELL5:OUT.11 |
| CHANNEL3 | output | TCELL5:OUT.13 |
| CHANNEL4 | output | TCELL5:OUT.15 |
| CHANNEL5 | output | TCELL5:OUT.17 |
| CONVST | input | TCELL6:IMUX.IMUX.47 |
| CONVST_CLK | input | TCELL5:IMUX.CTRL.4 |
| DADDR0 | input | TCELL6:IMUX.IMUX.23 |
| DADDR1 | input | TCELL6:IMUX.IMUX.25 |
| DADDR2 | input | TCELL6:IMUX.IMUX.27 |
| DADDR3 | input | TCELL6:IMUX.IMUX.29 |
| DADDR4 | input | TCELL6:IMUX.IMUX.31 |
| DADDR5 | input | TCELL6:IMUX.IMUX.33 |
| DADDR6 | input | TCELL6:IMUX.IMUX.35 |
| DADDR7 | input | TCELL6:IMUX.IMUX.37 |
| DATA_READY_ADC_F | input | TCELL5:IMUX.IMUX.37 |
| DCLK | input | TCELL5:IMUX.CTRL.1 |
| DEC_OUT_ADC_F0 | input | TCELL5:IMUX.IMUX.5 |
| DEC_OUT_ADC_F1 | input | TCELL5:IMUX.IMUX.7 |
| DEC_OUT_ADC_F10 | input | TCELL5:IMUX.IMUX.25 |
| DEC_OUT_ADC_F11 | input | TCELL5:IMUX.IMUX.27 |
| DEC_OUT_ADC_F12 | input | TCELL5:IMUX.IMUX.29 |
| DEC_OUT_ADC_F13 | input | TCELL5:IMUX.IMUX.31 |
| DEC_OUT_ADC_F14 | input | TCELL5:IMUX.IMUX.33 |
| DEC_OUT_ADC_F15 | input | TCELL5:IMUX.IMUX.35 |
| DEC_OUT_ADC_F2 | input | TCELL5:IMUX.IMUX.9 |
| DEC_OUT_ADC_F3 | input | TCELL5:IMUX.IMUX.11 |
| DEC_OUT_ADC_F4 | input | TCELL5:IMUX.IMUX.13 |
| DEC_OUT_ADC_F5 | input | TCELL5:IMUX.IMUX.15 |
| DEC_OUT_ADC_F6 | input | TCELL5:IMUX.IMUX.17 |
| DEC_OUT_ADC_F7 | input | TCELL5:IMUX.IMUX.19 |
| DEC_OUT_ADC_F8 | input | TCELL5:IMUX.IMUX.21 |
| DEC_OUT_ADC_F9 | input | TCELL5:IMUX.IMUX.23 |
| DEN | input | TCELL6:IMUX.IMUX.41 |
| DI0 | input | TCELL5:IMUX.IMUX.39 |
| DI1 | input | TCELL5:IMUX.IMUX.41 |
| DI10 | input | TCELL6:IMUX.IMUX.11 |
| DI11 | input | TCELL6:IMUX.IMUX.13 |
| DI12 | input | TCELL6:IMUX.IMUX.15 |
| DI13 | input | TCELL6:IMUX.IMUX.17 |
| DI14 | input | TCELL6:IMUX.IMUX.19 |
| DI15 | input | TCELL6:IMUX.IMUX.21 |
| DI2 | input | TCELL5:IMUX.IMUX.43 |
| DI3 | input | TCELL5:IMUX.IMUX.45 |
| DI4 | input | TCELL5:IMUX.IMUX.47 |
| DI5 | input | TCELL6:IMUX.IMUX.1 |
| DI6 | input | TCELL6:IMUX.IMUX.3 |
| DI7 | input | TCELL6:IMUX.IMUX.5 |
| DI8 | input | TCELL6:IMUX.IMUX.7 |
| DI9 | input | TCELL6:IMUX.IMUX.9 |
| DOUT0 | output | TCELL4:OUT.7 |
| DOUT1 | output | TCELL4:OUT.9 |
| DOUT10 | output | TCELL4:OUT.27 |
| DOUT11 | output | TCELL4:OUT.29 |
| DOUT12 | output | TCELL4:OUT.31 |
| DOUT13 | output | TCELL5:OUT.1 |
| DOUT14 | output | TCELL5:OUT.3 |
| DOUT15 | output | TCELL5:OUT.5 |
| DOUT2 | output | TCELL4:OUT.11 |
| DOUT3 | output | TCELL4:OUT.13 |
| DOUT4 | output | TCELL4:OUT.15 |
| DOUT5 | output | TCELL4:OUT.17 |
| DOUT6 | output | TCELL4:OUT.19 |
| DOUT7 | output | TCELL4:OUT.21 |
| DOUT8 | output | TCELL4:OUT.23 |
| DOUT9 | output | TCELL4:OUT.25 |
| DRDY | output | TCELL4:OUT.5 |
| DWE | input | TCELL6:IMUX.IMUX.39 |
| EOC | output | TCELL4:OUT.3 |
| EOS | output | TCELL4:OUT.1 |
| I2C_SCLK_IN | input | TCELL6:IMUX.IMUX.45 |
| I2C_SCLK_TS | output | TCELL3:OUT.13 |
| I2C_SDA_IN | input | TCELL6:IMUX.IMUX.43 |
| I2C_SDA_TS | output | TCELL3:OUT.11 |
| JTAG_BUSY | output | TCELL3:OUT.31 |
| JTAG_LOCKED | output | TCELL3:OUT.29 |
| JTAG_MODIFIED | output | TCELL3:OUT.27 |
| MUX_ADDR0 | output | TCELL3:OUT.17 |
| MUX_ADDR1 | output | TCELL3:OUT.19 |
| MUX_ADDR2 | output | TCELL3:OUT.21 |
| MUX_ADDR3 | output | TCELL3:OUT.23 |
| MUX_ADDR4 | output | TCELL3:OUT.25 |
| OT | output | TCELL3:OUT.15 |
| RESET_USER | input | TCELL5:IMUX.CTRL.7 |
| SMBALERT_TS | output | TCELL3:OUT.9 |
| TEST_ADC_CLK0 | input | TCELL3:IMUX.CTRL.7 |
| TEST_ADC_CLK1 | input | TCELL4:IMUX.CTRL.1 |
| TEST_ADC_CLK2 | input | TCELL4:IMUX.CTRL.4 |
| TEST_ADC_CLK3 | input | TCELL4:IMUX.CTRL.7 |
| TEST_ADC_IN0 | input | TCELL3:IMUX.IMUX.37 |
| TEST_ADC_IN1 | input | TCELL3:IMUX.IMUX.39 |
| TEST_ADC_IN10 | input | TCELL4:IMUX.IMUX.9 |
| TEST_ADC_IN11 | input | TCELL4:IMUX.IMUX.11 |
| TEST_ADC_IN12 | input | TCELL4:IMUX.IMUX.13 |
| TEST_ADC_IN13 | input | TCELL4:IMUX.IMUX.15 |
| TEST_ADC_IN14 | input | TCELL4:IMUX.IMUX.17 |
| TEST_ADC_IN15 | input | TCELL4:IMUX.IMUX.19 |
| TEST_ADC_IN16 | input | TCELL4:IMUX.IMUX.21 |
| TEST_ADC_IN17 | input | TCELL4:IMUX.IMUX.23 |
| TEST_ADC_IN18 | input | TCELL4:IMUX.IMUX.25 |
| TEST_ADC_IN19 | input | TCELL4:IMUX.IMUX.27 |
| TEST_ADC_IN2 | input | TCELL3:IMUX.IMUX.41 |
| TEST_ADC_IN20 | input | TCELL4:IMUX.IMUX.29 |
| TEST_ADC_IN21 | input | TCELL4:IMUX.IMUX.31 |
| TEST_ADC_IN22 | input | TCELL4:IMUX.IMUX.33 |
| TEST_ADC_IN23 | input | TCELL4:IMUX.IMUX.35 |
| TEST_ADC_IN24 | input | TCELL4:IMUX.IMUX.37 |
| TEST_ADC_IN25 | input | TCELL4:IMUX.IMUX.39 |
| TEST_ADC_IN26 | input | TCELL4:IMUX.IMUX.41 |
| TEST_ADC_IN27 | input | TCELL4:IMUX.IMUX.43 |
| TEST_ADC_IN28 | input | TCELL4:IMUX.IMUX.45 |
| TEST_ADC_IN29 | input | TCELL4:IMUX.IMUX.47 |
| TEST_ADC_IN2_0 | input | TCELL2:IMUX.IMUX.21 |
| TEST_ADC_IN2_1 | input | TCELL2:IMUX.IMUX.23 |
| TEST_ADC_IN2_10 | input | TCELL2:IMUX.IMUX.41 |
| TEST_ADC_IN2_11 | input | TCELL2:IMUX.IMUX.43 |
| TEST_ADC_IN2_12 | input | TCELL2:IMUX.IMUX.45 |
| TEST_ADC_IN2_13 | input | TCELL2:IMUX.IMUX.47 |
| TEST_ADC_IN2_14 | input | TCELL3:IMUX.IMUX.1 |
| TEST_ADC_IN2_15 | input | TCELL3:IMUX.IMUX.3 |
| TEST_ADC_IN2_16 | input | TCELL3:IMUX.IMUX.5 |
| TEST_ADC_IN2_17 | input | TCELL3:IMUX.IMUX.7 |
| TEST_ADC_IN2_18 | input | TCELL3:IMUX.IMUX.9 |
| TEST_ADC_IN2_19 | input | TCELL3:IMUX.IMUX.11 |
| TEST_ADC_IN2_2 | input | TCELL2:IMUX.IMUX.25 |
| TEST_ADC_IN2_20 | input | TCELL3:IMUX.IMUX.13 |
| TEST_ADC_IN2_21 | input | TCELL3:IMUX.IMUX.15 |
| TEST_ADC_IN2_22 | input | TCELL3:IMUX.IMUX.17 |
| TEST_ADC_IN2_23 | input | TCELL3:IMUX.IMUX.19 |
| TEST_ADC_IN2_24 | input | TCELL3:IMUX.IMUX.21 |
| TEST_ADC_IN2_25 | input | TCELL3:IMUX.IMUX.23 |
| TEST_ADC_IN2_26 | input | TCELL3:IMUX.IMUX.25 |
| TEST_ADC_IN2_27 | input | TCELL3:IMUX.IMUX.27 |
| TEST_ADC_IN2_28 | input | TCELL3:IMUX.IMUX.29 |
| TEST_ADC_IN2_29 | input | TCELL3:IMUX.IMUX.31 |
| TEST_ADC_IN2_3 | input | TCELL2:IMUX.IMUX.27 |
| TEST_ADC_IN2_30 | input | TCELL3:IMUX.IMUX.33 |
| TEST_ADC_IN2_31 | input | TCELL3:IMUX.IMUX.35 |
| TEST_ADC_IN2_4 | input | TCELL2:IMUX.IMUX.29 |
| TEST_ADC_IN2_5 | input | TCELL2:IMUX.IMUX.31 |
| TEST_ADC_IN2_6 | input | TCELL2:IMUX.IMUX.33 |
| TEST_ADC_IN2_7 | input | TCELL2:IMUX.IMUX.35 |
| TEST_ADC_IN2_8 | input | TCELL2:IMUX.IMUX.37 |
| TEST_ADC_IN2_9 | input | TCELL2:IMUX.IMUX.39 |
| TEST_ADC_IN3 | input | TCELL3:IMUX.IMUX.43 |
| TEST_ADC_IN30 | input | TCELL5:IMUX.IMUX.1 |
| TEST_ADC_IN31 | input | TCELL5:IMUX.IMUX.3 |
| TEST_ADC_IN4 | input | TCELL3:IMUX.IMUX.45 |
| TEST_ADC_IN5 | input | TCELL3:IMUX.IMUX.47 |
| TEST_ADC_IN6 | input | TCELL4:IMUX.IMUX.1 |
| TEST_ADC_IN7 | input | TCELL4:IMUX.IMUX.3 |
| TEST_ADC_IN8 | input | TCELL4:IMUX.IMUX.5 |
| TEST_ADC_IN9 | input | TCELL4:IMUX.IMUX.7 |
| TEST_ADC_OUT0 | output | TCELL0:OUT.13 |
| TEST_ADC_OUT1 | output | TCELL0:OUT.15 |
| TEST_ADC_OUT10 | output | TCELL1:OUT.1 |
| TEST_ADC_OUT11 | output | TCELL1:OUT.3 |
| TEST_ADC_OUT12 | output | TCELL1:OUT.5 |
| TEST_ADC_OUT13 | output | TCELL1:OUT.7 |
| TEST_ADC_OUT14 | output | TCELL1:OUT.9 |
| TEST_ADC_OUT15 | output | TCELL1:OUT.11 |
| TEST_ADC_OUT16 | output | TCELL1:OUT.13 |
| TEST_ADC_OUT17 | output | TCELL1:OUT.15 |
| TEST_ADC_OUT18 | output | TCELL1:OUT.17 |
| TEST_ADC_OUT19 | output | TCELL1:OUT.19 |
| TEST_ADC_OUT2 | output | TCELL0:OUT.17 |
| TEST_ADC_OUT3 | output | TCELL0:OUT.19 |
| TEST_ADC_OUT4 | output | TCELL0:OUT.21 |
| TEST_ADC_OUT5 | output | TCELL0:OUT.23 |
| TEST_ADC_OUT6 | output | TCELL0:OUT.25 |
| TEST_ADC_OUT7 | output | TCELL0:OUT.27 |
| TEST_ADC_OUT8 | output | TCELL0:OUT.29 |
| TEST_ADC_OUT9 | output | TCELL0:OUT.31 |
| TEST_CAPTURE | input | TCELL2:IMUX.IMUX.19 |
| TEST_DB0 | output | TCELL1:OUT.21 |
| TEST_DB1 | output | TCELL1:OUT.23 |
| TEST_DB10 | output | TCELL2:OUT.9 |
| TEST_DB11 | output | TCELL2:OUT.11 |
| TEST_DB12 | output | TCELL2:OUT.13 |
| TEST_DB13 | output | TCELL2:OUT.15 |
| TEST_DB14 | output | TCELL2:OUT.17 |
| TEST_DB15 | output | TCELL2:OUT.19 |
| TEST_DB2 | output | TCELL1:OUT.25 |
| TEST_DB3 | output | TCELL1:OUT.27 |
| TEST_DB4 | output | TCELL1:OUT.29 |
| TEST_DB5 | output | TCELL1:OUT.31 |
| TEST_DB6 | output | TCELL2:OUT.1 |
| TEST_DB7 | output | TCELL2:OUT.3 |
| TEST_DB8 | output | TCELL2:OUT.5 |
| TEST_DB9 | output | TCELL2:OUT.7 |
| TEST_DRCK | input | TCELL2:IMUX.IMUX.17 |
| TEST_EN_JTAG | input | TCELL2:IMUX.IMUX.15 |
| TEST_RST | input | TCELL2:IMUX.IMUX.13 |
| TEST_SCAN_CLK0 | input | TCELL2:IMUX.CTRL.1 |
| TEST_SCAN_CLK1 | input | TCELL2:IMUX.CTRL.4 |
| TEST_SCAN_CLK2 | input | TCELL2:IMUX.CTRL.7 |
| TEST_SCAN_CLK3 | input | TCELL3:IMUX.CTRL.1 |
| TEST_SCAN_CLK4 | input | TCELL3:IMUX.CTRL.4 |
| TEST_SCAN_MODE0 | input | TCELL2:IMUX.IMUX.3 |
| TEST_SCAN_MODE1 | input | TCELL2:IMUX.IMUX.5 |
| TEST_SCAN_MODE2 | input | TCELL2:IMUX.IMUX.7 |
| TEST_SCAN_MODE3 | input | TCELL2:IMUX.IMUX.9 |
| TEST_SCAN_MODE4 | input | TCELL2:IMUX.IMUX.11 |
| TEST_SCAN_RESET | input | TCELL2:IMUX.IMUX.1 |
| TEST_SE0 | input | TCELL1:IMUX.IMUX.39 |
| TEST_SE1 | input | TCELL1:IMUX.IMUX.41 |
| TEST_SE2 | input | TCELL1:IMUX.IMUX.43 |
| TEST_SE3 | input | TCELL1:IMUX.IMUX.45 |
| TEST_SE4 | input | TCELL1:IMUX.IMUX.47 |
| TEST_SEL | input | TCELL1:IMUX.IMUX.37 |
| TEST_SHIFT | input | TCELL1:IMUX.IMUX.35 |
| TEST_SI0 | input | TCELL1:IMUX.IMUX.15 |
| TEST_SI1 | input | TCELL1:IMUX.IMUX.17 |
| TEST_SI2 | input | TCELL1:IMUX.IMUX.19 |
| TEST_SI3 | input | TCELL1:IMUX.IMUX.21 |
| TEST_SI4 | input | TCELL1:IMUX.IMUX.23 |
| TEST_SI5 | input | TCELL1:IMUX.IMUX.25 |
| TEST_SI6 | input | TCELL1:IMUX.IMUX.27 |
| TEST_SI7 | input | TCELL1:IMUX.IMUX.29 |
| TEST_SI8 | input | TCELL1:IMUX.IMUX.31 |
| TEST_SI9 | input | TCELL1:IMUX.IMUX.33 |
| TEST_SO0 | output | TCELL2:OUT.21 |
| TEST_SO1 | output | TCELL2:OUT.23 |
| TEST_SO2 | output | TCELL2:OUT.25 |
| TEST_SO3 | output | TCELL2:OUT.27 |
| TEST_SO4 | output | TCELL2:OUT.29 |
| TEST_SO5 | output | TCELL2:OUT.31 |
| TEST_SO6 | output | TCELL3:OUT.1 |
| TEST_SO7 | output | TCELL3:OUT.3 |
| TEST_SO8 | output | TCELL3:OUT.5 |
| TEST_SO9 | output | TCELL3:OUT.7 |
| TEST_TDI | input | TCELL1:IMUX.IMUX.13 |
| TEST_TDO | output | TCELL0:OUT.11 |
| TEST_UPDATE | input | TCELL1:IMUX.IMUX.11 |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:OUT.11 | SYSMON.TEST_TDO |
| TCELL0:OUT.13 | SYSMON.TEST_ADC_OUT0 |
| TCELL0:OUT.15 | SYSMON.TEST_ADC_OUT1 |
| TCELL0:OUT.17 | SYSMON.TEST_ADC_OUT2 |
| TCELL0:OUT.19 | SYSMON.TEST_ADC_OUT3 |
| TCELL0:OUT.21 | SYSMON.TEST_ADC_OUT4 |
| TCELL0:OUT.23 | SYSMON.TEST_ADC_OUT5 |
| TCELL0:OUT.25 | SYSMON.TEST_ADC_OUT6 |
| TCELL0:OUT.27 | SYSMON.TEST_ADC_OUT7 |
| TCELL0:OUT.29 | SYSMON.TEST_ADC_OUT8 |
| TCELL0:OUT.31 | SYSMON.TEST_ADC_OUT9 |
| TCELL1:OUT.1 | SYSMON.TEST_ADC_OUT10 |
| TCELL1:OUT.3 | SYSMON.TEST_ADC_OUT11 |
| TCELL1:OUT.5 | SYSMON.TEST_ADC_OUT12 |
| TCELL1:OUT.7 | SYSMON.TEST_ADC_OUT13 |
| TCELL1:OUT.9 | SYSMON.TEST_ADC_OUT14 |
| TCELL1:OUT.11 | SYSMON.TEST_ADC_OUT15 |
| TCELL1:OUT.13 | SYSMON.TEST_ADC_OUT16 |
| TCELL1:OUT.15 | SYSMON.TEST_ADC_OUT17 |
| TCELL1:OUT.17 | SYSMON.TEST_ADC_OUT18 |
| TCELL1:OUT.19 | SYSMON.TEST_ADC_OUT19 |
| TCELL1:OUT.21 | SYSMON.TEST_DB0 |
| TCELL1:OUT.23 | SYSMON.TEST_DB1 |
| TCELL1:OUT.25 | SYSMON.TEST_DB2 |
| TCELL1:OUT.27 | SYSMON.TEST_DB3 |
| TCELL1:OUT.29 | SYSMON.TEST_DB4 |
| TCELL1:OUT.31 | SYSMON.TEST_DB5 |
| TCELL1:IMUX.IMUX.11 | SYSMON.TEST_UPDATE |
| TCELL1:IMUX.IMUX.13 | SYSMON.TEST_TDI |
| TCELL1:IMUX.IMUX.15 | SYSMON.TEST_SI0 |
| TCELL1:IMUX.IMUX.17 | SYSMON.TEST_SI1 |
| TCELL1:IMUX.IMUX.19 | SYSMON.TEST_SI2 |
| TCELL1:IMUX.IMUX.21 | SYSMON.TEST_SI3 |
| TCELL1:IMUX.IMUX.23 | SYSMON.TEST_SI4 |
| TCELL1:IMUX.IMUX.25 | SYSMON.TEST_SI5 |
| TCELL1:IMUX.IMUX.27 | SYSMON.TEST_SI6 |
| TCELL1:IMUX.IMUX.29 | SYSMON.TEST_SI7 |
| TCELL1:IMUX.IMUX.31 | SYSMON.TEST_SI8 |
| TCELL1:IMUX.IMUX.33 | SYSMON.TEST_SI9 |
| TCELL1:IMUX.IMUX.35 | SYSMON.TEST_SHIFT |
| TCELL1:IMUX.IMUX.37 | SYSMON.TEST_SEL |
| TCELL1:IMUX.IMUX.39 | SYSMON.TEST_SE0 |
| TCELL1:IMUX.IMUX.41 | SYSMON.TEST_SE1 |
| TCELL1:IMUX.IMUX.43 | SYSMON.TEST_SE2 |
| TCELL1:IMUX.IMUX.45 | SYSMON.TEST_SE3 |
| TCELL1:IMUX.IMUX.47 | SYSMON.TEST_SE4 |
| TCELL2:OUT.1 | SYSMON.TEST_DB6 |
| TCELL2:OUT.3 | SYSMON.TEST_DB7 |
| TCELL2:OUT.5 | SYSMON.TEST_DB8 |
| TCELL2:OUT.7 | SYSMON.TEST_DB9 |
| TCELL2:OUT.9 | SYSMON.TEST_DB10 |
| TCELL2:OUT.11 | SYSMON.TEST_DB11 |
| TCELL2:OUT.13 | SYSMON.TEST_DB12 |
| TCELL2:OUT.15 | SYSMON.TEST_DB13 |
| TCELL2:OUT.17 | SYSMON.TEST_DB14 |
| TCELL2:OUT.19 | SYSMON.TEST_DB15 |
| TCELL2:OUT.21 | SYSMON.TEST_SO0 |
| TCELL2:OUT.23 | SYSMON.TEST_SO1 |
| TCELL2:OUT.25 | SYSMON.TEST_SO2 |
| TCELL2:OUT.27 | SYSMON.TEST_SO3 |
| TCELL2:OUT.29 | SYSMON.TEST_SO4 |
| TCELL2:OUT.31 | SYSMON.TEST_SO5 |
| TCELL2:IMUX.CTRL.1 | SYSMON.TEST_SCAN_CLK0 |
| TCELL2:IMUX.CTRL.4 | SYSMON.TEST_SCAN_CLK1 |
| TCELL2:IMUX.CTRL.7 | SYSMON.TEST_SCAN_CLK2 |
| TCELL2:IMUX.IMUX.1 | SYSMON.TEST_SCAN_RESET |
| TCELL2:IMUX.IMUX.3 | SYSMON.TEST_SCAN_MODE0 |
| TCELL2:IMUX.IMUX.5 | SYSMON.TEST_SCAN_MODE1 |
| TCELL2:IMUX.IMUX.7 | SYSMON.TEST_SCAN_MODE2 |
| TCELL2:IMUX.IMUX.9 | SYSMON.TEST_SCAN_MODE3 |
| TCELL2:IMUX.IMUX.11 | SYSMON.TEST_SCAN_MODE4 |
| TCELL2:IMUX.IMUX.13 | SYSMON.TEST_RST |
| TCELL2:IMUX.IMUX.15 | SYSMON.TEST_EN_JTAG |
| TCELL2:IMUX.IMUX.17 | SYSMON.TEST_DRCK |
| TCELL2:IMUX.IMUX.19 | SYSMON.TEST_CAPTURE |
| TCELL2:IMUX.IMUX.21 | SYSMON.TEST_ADC_IN2_0 |
| TCELL2:IMUX.IMUX.23 | SYSMON.TEST_ADC_IN2_1 |
| TCELL2:IMUX.IMUX.25 | SYSMON.TEST_ADC_IN2_2 |
| TCELL2:IMUX.IMUX.27 | SYSMON.TEST_ADC_IN2_3 |
| TCELL2:IMUX.IMUX.29 | SYSMON.TEST_ADC_IN2_4 |
| TCELL2:IMUX.IMUX.31 | SYSMON.TEST_ADC_IN2_5 |
| TCELL2:IMUX.IMUX.33 | SYSMON.TEST_ADC_IN2_6 |
| TCELL2:IMUX.IMUX.35 | SYSMON.TEST_ADC_IN2_7 |
| TCELL2:IMUX.IMUX.37 | SYSMON.TEST_ADC_IN2_8 |
| TCELL2:IMUX.IMUX.39 | SYSMON.TEST_ADC_IN2_9 |
| TCELL2:IMUX.IMUX.41 | SYSMON.TEST_ADC_IN2_10 |
| TCELL2:IMUX.IMUX.43 | SYSMON.TEST_ADC_IN2_11 |
| TCELL2:IMUX.IMUX.45 | SYSMON.TEST_ADC_IN2_12 |
| TCELL2:IMUX.IMUX.47 | SYSMON.TEST_ADC_IN2_13 |
| TCELL3:OUT.1 | SYSMON.TEST_SO6 |
| TCELL3:OUT.3 | SYSMON.TEST_SO7 |
| TCELL3:OUT.5 | SYSMON.TEST_SO8 |
| TCELL3:OUT.7 | SYSMON.TEST_SO9 |
| TCELL3:OUT.9 | SYSMON.SMBALERT_TS |
| TCELL3:OUT.11 | SYSMON.I2C_SDA_TS |
| TCELL3:OUT.13 | SYSMON.I2C_SCLK_TS |
| TCELL3:OUT.15 | SYSMON.OT |
| TCELL3:OUT.17 | SYSMON.MUX_ADDR0 |
| TCELL3:OUT.19 | SYSMON.MUX_ADDR1 |
| TCELL3:OUT.21 | SYSMON.MUX_ADDR2 |
| TCELL3:OUT.23 | SYSMON.MUX_ADDR3 |
| TCELL3:OUT.25 | SYSMON.MUX_ADDR4 |
| TCELL3:OUT.27 | SYSMON.JTAG_MODIFIED |
| TCELL3:OUT.29 | SYSMON.JTAG_LOCKED |
| TCELL3:OUT.31 | SYSMON.JTAG_BUSY |
| TCELL3:IMUX.CTRL.1 | SYSMON.TEST_SCAN_CLK3 |
| TCELL3:IMUX.CTRL.4 | SYSMON.TEST_SCAN_CLK4 |
| TCELL3:IMUX.CTRL.7 | SYSMON.TEST_ADC_CLK0 |
| TCELL3:IMUX.IMUX.1 | SYSMON.TEST_ADC_IN2_14 |
| TCELL3:IMUX.IMUX.3 | SYSMON.TEST_ADC_IN2_15 |
| TCELL3:IMUX.IMUX.5 | SYSMON.TEST_ADC_IN2_16 |
| TCELL3:IMUX.IMUX.7 | SYSMON.TEST_ADC_IN2_17 |
| TCELL3:IMUX.IMUX.9 | SYSMON.TEST_ADC_IN2_18 |
| TCELL3:IMUX.IMUX.11 | SYSMON.TEST_ADC_IN2_19 |
| TCELL3:IMUX.IMUX.13 | SYSMON.TEST_ADC_IN2_20 |
| TCELL3:IMUX.IMUX.15 | SYSMON.TEST_ADC_IN2_21 |
| TCELL3:IMUX.IMUX.17 | SYSMON.TEST_ADC_IN2_22 |
| TCELL3:IMUX.IMUX.19 | SYSMON.TEST_ADC_IN2_23 |
| TCELL3:IMUX.IMUX.21 | SYSMON.TEST_ADC_IN2_24 |
| TCELL3:IMUX.IMUX.23 | SYSMON.TEST_ADC_IN2_25 |
| TCELL3:IMUX.IMUX.25 | SYSMON.TEST_ADC_IN2_26 |
| TCELL3:IMUX.IMUX.27 | SYSMON.TEST_ADC_IN2_27 |
| TCELL3:IMUX.IMUX.29 | SYSMON.TEST_ADC_IN2_28 |
| TCELL3:IMUX.IMUX.31 | SYSMON.TEST_ADC_IN2_29 |
| TCELL3:IMUX.IMUX.33 | SYSMON.TEST_ADC_IN2_30 |
| TCELL3:IMUX.IMUX.35 | SYSMON.TEST_ADC_IN2_31 |
| TCELL3:IMUX.IMUX.37 | SYSMON.TEST_ADC_IN0 |
| TCELL3:IMUX.IMUX.39 | SYSMON.TEST_ADC_IN1 |
| TCELL3:IMUX.IMUX.41 | SYSMON.TEST_ADC_IN2 |
| TCELL3:IMUX.IMUX.43 | SYSMON.TEST_ADC_IN3 |
| TCELL3:IMUX.IMUX.45 | SYSMON.TEST_ADC_IN4 |
| TCELL3:IMUX.IMUX.47 | SYSMON.TEST_ADC_IN5 |
| TCELL4:OUT.1 | SYSMON.EOS |
| TCELL4:OUT.3 | SYSMON.EOC |
| TCELL4:OUT.5 | SYSMON.DRDY |
| TCELL4:OUT.7 | SYSMON.DOUT0 |
| TCELL4:OUT.9 | SYSMON.DOUT1 |
| TCELL4:OUT.11 | SYSMON.DOUT2 |
| TCELL4:OUT.13 | SYSMON.DOUT3 |
| TCELL4:OUT.15 | SYSMON.DOUT4 |
| TCELL4:OUT.17 | SYSMON.DOUT5 |
| TCELL4:OUT.19 | SYSMON.DOUT6 |
| TCELL4:OUT.21 | SYSMON.DOUT7 |
| TCELL4:OUT.23 | SYSMON.DOUT8 |
| TCELL4:OUT.25 | SYSMON.DOUT9 |
| TCELL4:OUT.27 | SYSMON.DOUT10 |
| TCELL4:OUT.29 | SYSMON.DOUT11 |
| TCELL4:OUT.31 | SYSMON.DOUT12 |
| TCELL4:IMUX.CTRL.1 | SYSMON.TEST_ADC_CLK1 |
| TCELL4:IMUX.CTRL.4 | SYSMON.TEST_ADC_CLK2 |
| TCELL4:IMUX.CTRL.7 | SYSMON.TEST_ADC_CLK3 |
| TCELL4:IMUX.IMUX.1 | SYSMON.TEST_ADC_IN6 |
| TCELL4:IMUX.IMUX.3 | SYSMON.TEST_ADC_IN7 |
| TCELL4:IMUX.IMUX.5 | SYSMON.TEST_ADC_IN8 |
| TCELL4:IMUX.IMUX.7 | SYSMON.TEST_ADC_IN9 |
| TCELL4:IMUX.IMUX.9 | SYSMON.TEST_ADC_IN10 |
| TCELL4:IMUX.IMUX.11 | SYSMON.TEST_ADC_IN11 |
| TCELL4:IMUX.IMUX.13 | SYSMON.TEST_ADC_IN12 |
| TCELL4:IMUX.IMUX.15 | SYSMON.TEST_ADC_IN13 |
| TCELL4:IMUX.IMUX.17 | SYSMON.TEST_ADC_IN14 |
| TCELL4:IMUX.IMUX.19 | SYSMON.TEST_ADC_IN15 |
| TCELL4:IMUX.IMUX.21 | SYSMON.TEST_ADC_IN16 |
| TCELL4:IMUX.IMUX.23 | SYSMON.TEST_ADC_IN17 |
| TCELL4:IMUX.IMUX.25 | SYSMON.TEST_ADC_IN18 |
| TCELL4:IMUX.IMUX.27 | SYSMON.TEST_ADC_IN19 |
| TCELL4:IMUX.IMUX.29 | SYSMON.TEST_ADC_IN20 |
| TCELL4:IMUX.IMUX.31 | SYSMON.TEST_ADC_IN21 |
| TCELL4:IMUX.IMUX.33 | SYSMON.TEST_ADC_IN22 |
| TCELL4:IMUX.IMUX.35 | SYSMON.TEST_ADC_IN23 |
| TCELL4:IMUX.IMUX.37 | SYSMON.TEST_ADC_IN24 |
| TCELL4:IMUX.IMUX.39 | SYSMON.TEST_ADC_IN25 |
| TCELL4:IMUX.IMUX.41 | SYSMON.TEST_ADC_IN26 |
| TCELL4:IMUX.IMUX.43 | SYSMON.TEST_ADC_IN27 |
| TCELL4:IMUX.IMUX.45 | SYSMON.TEST_ADC_IN28 |
| TCELL4:IMUX.IMUX.47 | SYSMON.TEST_ADC_IN29 |
| TCELL5:OUT.1 | SYSMON.DOUT13 |
| TCELL5:OUT.3 | SYSMON.DOUT14 |
| TCELL5:OUT.5 | SYSMON.DOUT15 |
| TCELL5:OUT.7 | SYSMON.CHANNEL0 |
| TCELL5:OUT.9 | SYSMON.CHANNEL1 |
| TCELL5:OUT.11 | SYSMON.CHANNEL2 |
| TCELL5:OUT.13 | SYSMON.CHANNEL3 |
| TCELL5:OUT.15 | SYSMON.CHANNEL4 |
| TCELL5:OUT.17 | SYSMON.CHANNEL5 |
| TCELL5:OUT.19 | SYSMON.BUSY |
| TCELL5:OUT.21 | SYSMON.ALM0 |
| TCELL5:OUT.23 | SYSMON.ALM1 |
| TCELL5:OUT.25 | SYSMON.ALM2 |
| TCELL5:OUT.27 | SYSMON.ALM3 |
| TCELL5:OUT.29 | SYSMON.ALM4 |
| TCELL5:OUT.31 | SYSMON.ALM5 |
| TCELL5:IMUX.CTRL.1 | SYSMON.DCLK |
| TCELL5:IMUX.CTRL.4 | SYSMON.CONVST_CLK |
| TCELL5:IMUX.CTRL.7 | SYSMON.RESET_USER |
| TCELL5:IMUX.IMUX.1 | SYSMON.TEST_ADC_IN30 |
| TCELL5:IMUX.IMUX.3 | SYSMON.TEST_ADC_IN31 |
| TCELL5:IMUX.IMUX.5 | SYSMON.DEC_OUT_ADC_F0 |
| TCELL5:IMUX.IMUX.7 | SYSMON.DEC_OUT_ADC_F1 |
| TCELL5:IMUX.IMUX.9 | SYSMON.DEC_OUT_ADC_F2 |
| TCELL5:IMUX.IMUX.11 | SYSMON.DEC_OUT_ADC_F3 |
| TCELL5:IMUX.IMUX.13 | SYSMON.DEC_OUT_ADC_F4 |
| TCELL5:IMUX.IMUX.15 | SYSMON.DEC_OUT_ADC_F5 |
| TCELL5:IMUX.IMUX.17 | SYSMON.DEC_OUT_ADC_F6 |
| TCELL5:IMUX.IMUX.19 | SYSMON.DEC_OUT_ADC_F7 |
| TCELL5:IMUX.IMUX.21 | SYSMON.DEC_OUT_ADC_F8 |
| TCELL5:IMUX.IMUX.23 | SYSMON.DEC_OUT_ADC_F9 |
| TCELL5:IMUX.IMUX.25 | SYSMON.DEC_OUT_ADC_F10 |
| TCELL5:IMUX.IMUX.27 | SYSMON.DEC_OUT_ADC_F11 |
| TCELL5:IMUX.IMUX.29 | SYSMON.DEC_OUT_ADC_F12 |
| TCELL5:IMUX.IMUX.31 | SYSMON.DEC_OUT_ADC_F13 |
| TCELL5:IMUX.IMUX.33 | SYSMON.DEC_OUT_ADC_F14 |
| TCELL5:IMUX.IMUX.35 | SYSMON.DEC_OUT_ADC_F15 |
| TCELL5:IMUX.IMUX.37 | SYSMON.DATA_READY_ADC_F |
| TCELL5:IMUX.IMUX.39 | SYSMON.DI0 |
| TCELL5:IMUX.IMUX.41 | SYSMON.DI1 |
| TCELL5:IMUX.IMUX.43 | SYSMON.DI2 |
| TCELL5:IMUX.IMUX.45 | SYSMON.DI3 |
| TCELL5:IMUX.IMUX.47 | SYSMON.DI4 |
| TCELL6:OUT.1 | SYSMON.ALM6 |
| TCELL6:OUT.3 | SYSMON.ALM7 |
| TCELL6:OUT.5 | SYSMON.ALM8 |
| TCELL6:OUT.7 | SYSMON.ALM9 |
| TCELL6:OUT.9 | SYSMON.ALM10 |
| TCELL6:OUT.11 | SYSMON.ALM11 |
| TCELL6:OUT.13 | SYSMON.ALM12 |
| TCELL6:OUT.15 | SYSMON.ALM13 |
| TCELL6:OUT.17 | SYSMON.ALM14 |
| TCELL6:OUT.19 | SYSMON.ALM15 |
| TCELL6:OUT.21 | SYSMON.ADC_DATA0 |
| TCELL6:OUT.23 | SYSMON.ADC_DATA1 |
| TCELL6:OUT.25 | SYSMON.ADC_DATA2 |
| TCELL6:OUT.27 | SYSMON.ADC_DATA3 |
| TCELL6:OUT.29 | SYSMON.ADC_DATA4 |
| TCELL6:OUT.31 | SYSMON.ADC_DATA5 |
| TCELL6:IMUX.IMUX.1 | SYSMON.DI5 |
| TCELL6:IMUX.IMUX.3 | SYSMON.DI6 |
| TCELL6:IMUX.IMUX.5 | SYSMON.DI7 |
| TCELL6:IMUX.IMUX.7 | SYSMON.DI8 |
| TCELL6:IMUX.IMUX.9 | SYSMON.DI9 |
| TCELL6:IMUX.IMUX.11 | SYSMON.DI10 |
| TCELL6:IMUX.IMUX.13 | SYSMON.DI11 |
| TCELL6:IMUX.IMUX.15 | SYSMON.DI12 |
| TCELL6:IMUX.IMUX.17 | SYSMON.DI13 |
| TCELL6:IMUX.IMUX.19 | SYSMON.DI14 |
| TCELL6:IMUX.IMUX.21 | SYSMON.DI15 |
| TCELL6:IMUX.IMUX.23 | SYSMON.DADDR0 |
| TCELL6:IMUX.IMUX.25 | SYSMON.DADDR1 |
| TCELL6:IMUX.IMUX.27 | SYSMON.DADDR2 |
| TCELL6:IMUX.IMUX.29 | SYSMON.DADDR3 |
| TCELL6:IMUX.IMUX.31 | SYSMON.DADDR4 |
| TCELL6:IMUX.IMUX.33 | SYSMON.DADDR5 |
| TCELL6:IMUX.IMUX.35 | SYSMON.DADDR6 |
| TCELL6:IMUX.IMUX.37 | SYSMON.DADDR7 |
| TCELL6:IMUX.IMUX.39 | SYSMON.DWE |
| TCELL6:IMUX.IMUX.41 | SYSMON.DEN |
| TCELL6:IMUX.IMUX.43 | SYSMON.I2C_SDA_IN |
| TCELL6:IMUX.IMUX.45 | SYSMON.I2C_SCLK_IN |
| TCELL6:IMUX.IMUX.47 | SYSMON.CONVST |
| TCELL7:OUT.1 | SYSMON.ADC_DATA6 |
| TCELL7:OUT.3 | SYSMON.ADC_DATA7 |
| TCELL7:OUT.5 | SYSMON.ADC_DATA8 |
| TCELL7:OUT.7 | SYSMON.ADC_DATA9 |
| TCELL7:OUT.9 | SYSMON.ADC_DATA10 |
| TCELL7:OUT.11 | SYSMON.ADC_DATA11 |
| TCELL7:OUT.13 | SYSMON.ADC_DATA12 |
| TCELL7:OUT.15 | SYSMON.ADC_DATA13 |
| TCELL7:OUT.17 | SYSMON.ADC_DATA14 |
| TCELL7:OUT.19 | SYSMON.ADC_DATA15 |