Configuration center
Tile CFG
Cells: 60
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| BSCAN_CDR1 | output | CELL[42].OUT_BEL[4] |
| BSCAN_CDR2 | output | CELL[42].OUT_BEL[6] |
| BSCAN_CDR3 | output | CELL[54].OUT_BEL[18] |
| BSCAN_CDR4 | output | CELL[54].OUT_BEL[20] |
| BSCAN_CLKDR1 | output | CELL[42].OUT_BEL[8] |
| BSCAN_CLKDR2 | output | CELL[42].OUT_BEL[10] |
| BSCAN_CLKDR3 | output | CELL[54].OUT_BEL[22] |
| BSCAN_CLKDR4 | output | CELL[54].OUT_BEL[24] |
| BSCAN_RTI1 | output | CELL[42].OUT_BEL[12] |
| BSCAN_RTI2 | output | CELL[42].OUT_BEL[14] |
| BSCAN_RTI3 | output | CELL[54].OUT_BEL[26] |
| BSCAN_RTI4 | output | CELL[54].OUT_BEL[28] |
| BSCAN_SDR1 | output | CELL[42].OUT_BEL[16] |
| BSCAN_SDR2 | output | CELL[42].OUT_BEL[18] |
| BSCAN_SDR3 | output | CELL[53].OUT_BEL[0] |
| BSCAN_SDR4 | output | CELL[53].OUT_BEL[2] |
| BSCAN_SEL1 | output | CELL[42].OUT_BEL[20] |
| BSCAN_SEL2 | output | CELL[42].OUT_BEL[22] |
| BSCAN_SEL3 | output | CELL[53].OUT_BEL[4] |
| BSCAN_SEL4 | output | CELL[53].OUT_BEL[6] |
| BSCAN_TCK1 | output | CELL[43].OUT_BEL[6] |
| BSCAN_TCK2 | output | CELL[43].OUT_BEL[8] |
| BSCAN_TCK3 | output | CELL[54].OUT_BEL[6] |
| BSCAN_TCK4 | output | CELL[54].OUT_BEL[8] |
| BSCAN_TDI1 | output | CELL[43].OUT_BEL[14] |
| BSCAN_TDI2 | output | CELL[43].OUT_BEL[16] |
| BSCAN_TDI3 | output | CELL[54].OUT_BEL[14] |
| BSCAN_TDI4 | output | CELL[54].OUT_BEL[16] |
| BSCAN_TDO1 | input | CELL[43].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO2 | input | CELL[43].IMUX_IMUX_DELAY[3] |
| BSCAN_TDO3 | input | CELL[54].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO4 | input | CELL[54].IMUX_IMUX_DELAY[3] |
| BSCAN_TLR1 | output | CELL[42].OUT_BEL[24] |
| BSCAN_TLR2 | output | CELL[42].OUT_BEL[26] |
| BSCAN_TLR3 | output | CELL[53].OUT_BEL[8] |
| BSCAN_TLR4 | output | CELL[53].OUT_BEL[10] |
| BSCAN_TMS1 | output | CELL[43].OUT_BEL[10] |
| BSCAN_TMS2 | output | CELL[43].OUT_BEL[12] |
| BSCAN_TMS3 | output | CELL[54].OUT_BEL[10] |
| BSCAN_TMS4 | output | CELL[54].OUT_BEL[12] |
| BSCAN_UDR1 | output | CELL[42].OUT_BEL[28] |
| BSCAN_UDR2 | output | CELL[42].OUT_BEL[30] |
| BSCAN_UDR3 | output | CELL[53].OUT_BEL[12] |
| BSCAN_UDR4 | output | CELL[53].OUT_BEL[14] |
| DCI_LOCK | output | CELL[42].OUT_BEL[2] |
| DCI_USR_RESET_IN | input | CELL[42].IMUX_IMUX_DELAY[3] |
| ECC_END_OF_FRAME | output | CELL[51].OUT_BEL[26] |
| ECC_END_OF_SCAN | output | CELL[51].OUT_BEL[28] |
| ECC_ERROR_NOTSINGLE | output | CELL[51].OUT_BEL[22] |
| ECC_ERROR_SINGLE | output | CELL[51].OUT_BEL[24] |
| ECC_FAR0 | output | CELL[52].OUT_BEL[0] |
| ECC_FAR1 | output | CELL[52].OUT_BEL[2] |
| ECC_FAR10 | output | CELL[52].OUT_BEL[20] |
| ECC_FAR11 | output | CELL[52].OUT_BEL[22] |
| ECC_FAR12 | output | CELL[52].OUT_BEL[24] |
| ECC_FAR13 | output | CELL[52].OUT_BEL[26] |
| ECC_FAR14 | output | CELL[52].OUT_BEL[28] |
| ECC_FAR15 | output | CELL[52].OUT_BEL[30] |
| ECC_FAR16 | output | CELL[51].OUT_BEL[0] |
| ECC_FAR17 | output | CELL[51].OUT_BEL[2] |
| ECC_FAR18 | output | CELL[51].OUT_BEL[4] |
| ECC_FAR19 | output | CELL[51].OUT_BEL[6] |
| ECC_FAR2 | output | CELL[52].OUT_BEL[4] |
| ECC_FAR20 | output | CELL[51].OUT_BEL[8] |
| ECC_FAR21 | output | CELL[51].OUT_BEL[10] |
| ECC_FAR22 | output | CELL[51].OUT_BEL[12] |
| ECC_FAR23 | output | CELL[51].OUT_BEL[14] |
| ECC_FAR24 | output | CELL[51].OUT_BEL[16] |
| ECC_FAR25 | output | CELL[51].OUT_BEL[18] |
| ECC_FAR26 | output | CELL[52].OUT_BEL[31] |
| ECC_FAR3 | output | CELL[52].OUT_BEL[6] |
| ECC_FAR4 | output | CELL[52].OUT_BEL[8] |
| ECC_FAR5 | output | CELL[52].OUT_BEL[10] |
| ECC_FAR6 | output | CELL[52].OUT_BEL[12] |
| ECC_FAR7 | output | CELL[52].OUT_BEL[14] |
| ECC_FAR8 | output | CELL[52].OUT_BEL[16] |
| ECC_FAR9 | output | CELL[52].OUT_BEL[18] |
| ECC_FAR_SEL0 | input | CELL[51].IMUX_IMUX_DELAY[15] |
| ECC_FAR_SEL1 | input | CELL[51].IMUX_IMUX_DELAY[16] |
| EOS | output | CELL[47].OUT_BEL[10] |
| ICAP_AVAIL_BOT | output | CELL[43].OUT_BEL[4] |
| ICAP_AVAIL_TOP | output | CELL[54].OUT_BEL[4] |
| ICAP_CLK_BOT | input | CELL[45].IMUX_CTRL[0] |
| ICAP_CLK_TOP | input | CELL[56].IMUX_CTRL[0] |
| ICAP_CS_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[1] |
| ICAP_CS_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT0 | input | CELL[44].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT1 | input | CELL[44].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT10 | input | CELL[44].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT11 | input | CELL[44].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT12 | input | CELL[44].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT13 | input | CELL[44].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT14 | input | CELL[44].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT15 | input | CELL[44].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT16 | input | CELL[45].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT17 | input | CELL[45].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT18 | input | CELL[45].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT19 | input | CELL[45].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT2 | input | CELL[44].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT20 | input | CELL[45].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT21 | input | CELL[45].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT22 | input | CELL[45].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT23 | input | CELL[45].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT24 | input | CELL[45].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT25 | input | CELL[45].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_BOT26 | input | CELL[45].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT27 | input | CELL[45].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT28 | input | CELL[45].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT29 | input | CELL[45].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT3 | input | CELL[44].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT30 | input | CELL[45].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT31 | input | CELL[45].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT4 | input | CELL[44].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT5 | input | CELL[44].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT6 | input | CELL[44].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT7 | input | CELL[44].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT8 | input | CELL[44].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT9 | input | CELL[44].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP0 | input | CELL[55].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP1 | input | CELL[55].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP10 | input | CELL[55].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP11 | input | CELL[55].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP12 | input | CELL[55].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP13 | input | CELL[55].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP14 | input | CELL[55].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP15 | input | CELL[55].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP16 | input | CELL[56].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP17 | input | CELL[56].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP18 | input | CELL[56].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP19 | input | CELL[56].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP2 | input | CELL[55].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP20 | input | CELL[56].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP21 | input | CELL[56].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP22 | input | CELL[56].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP23 | input | CELL[56].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP24 | input | CELL[56].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP25 | input | CELL[56].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP26 | input | CELL[56].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP27 | input | CELL[56].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP28 | input | CELL[56].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP29 | input | CELL[56].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP3 | input | CELL[55].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP30 | input | CELL[56].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP31 | input | CELL[56].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP4 | input | CELL[55].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP5 | input | CELL[55].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP6 | input | CELL[55].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP7 | input | CELL[55].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP8 | input | CELL[55].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP9 | input | CELL[55].IMUX_IMUX_DELAY[9] |
| ICAP_OUT_BOT0 | output | CELL[44].OUT_BEL[0] |
| ICAP_OUT_BOT1 | output | CELL[44].OUT_BEL[2] |
| ICAP_OUT_BOT10 | output | CELL[44].OUT_BEL[20] |
| ICAP_OUT_BOT11 | output | CELL[44].OUT_BEL[22] |
| ICAP_OUT_BOT12 | output | CELL[44].OUT_BEL[24] |
| ICAP_OUT_BOT13 | output | CELL[44].OUT_BEL[26] |
| ICAP_OUT_BOT14 | output | CELL[44].OUT_BEL[28] |
| ICAP_OUT_BOT15 | output | CELL[44].OUT_BEL[30] |
| ICAP_OUT_BOT16 | output | CELL[45].OUT_BEL[0] |
| ICAP_OUT_BOT17 | output | CELL[45].OUT_BEL[2] |
| ICAP_OUT_BOT18 | output | CELL[45].OUT_BEL[4] |
| ICAP_OUT_BOT19 | output | CELL[45].OUT_BEL[6] |
| ICAP_OUT_BOT2 | output | CELL[44].OUT_BEL[4] |
| ICAP_OUT_BOT20 | output | CELL[45].OUT_BEL[8] |
| ICAP_OUT_BOT21 | output | CELL[45].OUT_BEL[10] |
| ICAP_OUT_BOT22 | output | CELL[45].OUT_BEL[12] |
| ICAP_OUT_BOT23 | output | CELL[45].OUT_BEL[14] |
| ICAP_OUT_BOT24 | output | CELL[45].OUT_BEL[16] |
| ICAP_OUT_BOT25 | output | CELL[45].OUT_BEL[18] |
| ICAP_OUT_BOT26 | output | CELL[45].OUT_BEL[20] |
| ICAP_OUT_BOT27 | output | CELL[45].OUT_BEL[22] |
| ICAP_OUT_BOT28 | output | CELL[45].OUT_BEL[24] |
| ICAP_OUT_BOT29 | output | CELL[45].OUT_BEL[26] |
| ICAP_OUT_BOT3 | output | CELL[44].OUT_BEL[6] |
| ICAP_OUT_BOT30 | output | CELL[45].OUT_BEL[28] |
| ICAP_OUT_BOT31 | output | CELL[45].OUT_BEL[30] |
| ICAP_OUT_BOT4 | output | CELL[44].OUT_BEL[8] |
| ICAP_OUT_BOT5 | output | CELL[44].OUT_BEL[10] |
| ICAP_OUT_BOT6 | output | CELL[44].OUT_BEL[12] |
| ICAP_OUT_BOT7 | output | CELL[44].OUT_BEL[14] |
| ICAP_OUT_BOT8 | output | CELL[44].OUT_BEL[16] |
| ICAP_OUT_BOT9 | output | CELL[44].OUT_BEL[18] |
| ICAP_OUT_TOP0 | output | CELL[55].OUT_BEL[0] |
| ICAP_OUT_TOP1 | output | CELL[55].OUT_BEL[2] |
| ICAP_OUT_TOP10 | output | CELL[55].OUT_BEL[20] |
| ICAP_OUT_TOP11 | output | CELL[55].OUT_BEL[22] |
| ICAP_OUT_TOP12 | output | CELL[55].OUT_BEL[24] |
| ICAP_OUT_TOP13 | output | CELL[55].OUT_BEL[26] |
| ICAP_OUT_TOP14 | output | CELL[55].OUT_BEL[28] |
| ICAP_OUT_TOP15 | output | CELL[55].OUT_BEL[30] |
| ICAP_OUT_TOP16 | output | CELL[56].OUT_BEL[0] |
| ICAP_OUT_TOP17 | output | CELL[56].OUT_BEL[2] |
| ICAP_OUT_TOP18 | output | CELL[56].OUT_BEL[4] |
| ICAP_OUT_TOP19 | output | CELL[56].OUT_BEL[6] |
| ICAP_OUT_TOP2 | output | CELL[55].OUT_BEL[4] |
| ICAP_OUT_TOP20 | output | CELL[56].OUT_BEL[8] |
| ICAP_OUT_TOP21 | output | CELL[56].OUT_BEL[10] |
| ICAP_OUT_TOP22 | output | CELL[56].OUT_BEL[12] |
| ICAP_OUT_TOP23 | output | CELL[56].OUT_BEL[14] |
| ICAP_OUT_TOP24 | output | CELL[56].OUT_BEL[16] |
| ICAP_OUT_TOP25 | output | CELL[56].OUT_BEL[18] |
| ICAP_OUT_TOP26 | output | CELL[56].OUT_BEL[20] |
| ICAP_OUT_TOP27 | output | CELL[56].OUT_BEL[22] |
| ICAP_OUT_TOP28 | output | CELL[56].OUT_BEL[24] |
| ICAP_OUT_TOP29 | output | CELL[56].OUT_BEL[26] |
| ICAP_OUT_TOP3 | output | CELL[55].OUT_BEL[6] |
| ICAP_OUT_TOP30 | output | CELL[56].OUT_BEL[28] |
| ICAP_OUT_TOP31 | output | CELL[56].OUT_BEL[30] |
| ICAP_OUT_TOP4 | output | CELL[55].OUT_BEL[8] |
| ICAP_OUT_TOP5 | output | CELL[55].OUT_BEL[10] |
| ICAP_OUT_TOP6 | output | CELL[55].OUT_BEL[12] |
| ICAP_OUT_TOP7 | output | CELL[55].OUT_BEL[14] |
| ICAP_OUT_TOP8 | output | CELL[55].OUT_BEL[16] |
| ICAP_OUT_TOP9 | output | CELL[55].OUT_BEL[18] |
| ICAP_PR_DONE_BOT | output | CELL[43].OUT_BEL[0] |
| ICAP_PR_DONE_TOP | output | CELL[54].OUT_BEL[0] |
| ICAP_PR_ERROR_BOT | output | CELL[43].OUT_BEL[2] |
| ICAP_PR_ERROR_TOP | output | CELL[54].OUT_BEL[2] |
| ICAP_RDWR_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[0] |
| ICAP_RDWR_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[0] |
| IOX_CCLK | output | CELL[50].OUT_BEL[0] |
| IOX_CFGDATA0 | output | CELL[48].OUT_BEL[0] |
| IOX_CFGDATA1 | output | CELL[48].OUT_BEL[2] |
| IOX_CFGDATA10 | output | CELL[48].OUT_BEL[20] |
| IOX_CFGDATA11 | output | CELL[48].OUT_BEL[22] |
| IOX_CFGDATA12 | output | CELL[48].OUT_BEL[24] |
| IOX_CFGDATA13 | output | CELL[48].OUT_BEL[26] |
| IOX_CFGDATA14 | output | CELL[48].OUT_BEL[28] |
| IOX_CFGDATA15 | output | CELL[48].OUT_BEL[30] |
| IOX_CFGDATA16 | output | CELL[49].OUT_BEL[0] |
| IOX_CFGDATA17 | output | CELL[49].OUT_BEL[2] |
| IOX_CFGDATA18 | output | CELL[49].OUT_BEL[4] |
| IOX_CFGDATA19 | output | CELL[49].OUT_BEL[6] |
| IOX_CFGDATA2 | output | CELL[48].OUT_BEL[4] |
| IOX_CFGDATA20 | output | CELL[49].OUT_BEL[8] |
| IOX_CFGDATA21 | output | CELL[49].OUT_BEL[10] |
| IOX_CFGDATA22 | output | CELL[49].OUT_BEL[12] |
| IOX_CFGDATA23 | output | CELL[49].OUT_BEL[14] |
| IOX_CFGDATA24 | output | CELL[49].OUT_BEL[16] |
| IOX_CFGDATA25 | output | CELL[49].OUT_BEL[18] |
| IOX_CFGDATA26 | output | CELL[49].OUT_BEL[20] |
| IOX_CFGDATA27 | output | CELL[49].OUT_BEL[22] |
| IOX_CFGDATA28 | output | CELL[49].OUT_BEL[24] |
| IOX_CFGDATA29 | output | CELL[49].OUT_BEL[26] |
| IOX_CFGDATA3 | output | CELL[48].OUT_BEL[6] |
| IOX_CFGDATA30 | output | CELL[49].OUT_BEL[28] |
| IOX_CFGDATA31 | output | CELL[49].OUT_BEL[30] |
| IOX_CFGDATA4 | output | CELL[48].OUT_BEL[8] |
| IOX_CFGDATA5 | output | CELL[48].OUT_BEL[10] |
| IOX_CFGDATA6 | output | CELL[48].OUT_BEL[12] |
| IOX_CFGDATA7 | output | CELL[48].OUT_BEL[14] |
| IOX_CFGDATA8 | output | CELL[48].OUT_BEL[16] |
| IOX_CFGDATA9 | output | CELL[48].OUT_BEL[18] |
| IOX_CFGMASTER | output | CELL[50].OUT_BEL[2] |
| IOX_INITBI | output | CELL[50].OUT_BEL[6] |
| IOX_INITBO | input | CELL[48].IMUX_IMUX_DELAY[1] |
| IOX_MODE0 | output | CELL[50].OUT_BEL[12] |
| IOX_MODE1 | output | CELL[50].OUT_BEL[14] |
| IOX_MODE2 | output | CELL[50].OUT_BEL[16] |
| IOX_PUDCB | output | CELL[50].OUT_BEL[8] |
| IOX_RDWRB | output | CELL[50].OUT_BEL[10] |
| IOX_TDO | input | CELL[48].IMUX_IMUX_DELAY[0] |
| IOX_VGG_COMP_OUT | output | CELL[50].OUT_BEL[4] |
| KEY_CLEAR | input | CELL[47].IMUX_IMUX_DELAY[0] |
| PROG_ACK | input | CELL[47].IMUX_IMUX_DELAY[1] |
| PROG_REQ | output | CELL[47].OUT_BEL[8] |
| RBCRC_ERROR | output | CELL[51].OUT_BEL[20] |
| START_CFG_CLK | output | CELL[47].OUT_BEL[14] |
| START_CFG_MCLK | output | CELL[47].OUT_BEL[12] |
| USR_ACCESS_CLK | output | CELL[57].OUT_BEL[2] |
| USR_ACCESS_DATA0 | output | CELL[58].OUT_BEL[0] |
| USR_ACCESS_DATA1 | output | CELL[58].OUT_BEL[2] |
| USR_ACCESS_DATA10 | output | CELL[58].OUT_BEL[20] |
| USR_ACCESS_DATA11 | output | CELL[58].OUT_BEL[22] |
| USR_ACCESS_DATA12 | output | CELL[58].OUT_BEL[24] |
| USR_ACCESS_DATA13 | output | CELL[58].OUT_BEL[26] |
| USR_ACCESS_DATA14 | output | CELL[58].OUT_BEL[28] |
| USR_ACCESS_DATA15 | output | CELL[58].OUT_BEL[30] |
| USR_ACCESS_DATA16 | output | CELL[59].OUT_BEL[0] |
| USR_ACCESS_DATA17 | output | CELL[59].OUT_BEL[2] |
| USR_ACCESS_DATA18 | output | CELL[59].OUT_BEL[4] |
| USR_ACCESS_DATA19 | output | CELL[59].OUT_BEL[6] |
| USR_ACCESS_DATA2 | output | CELL[58].OUT_BEL[4] |
| USR_ACCESS_DATA20 | output | CELL[59].OUT_BEL[8] |
| USR_ACCESS_DATA21 | output | CELL[59].OUT_BEL[10] |
| USR_ACCESS_DATA22 | output | CELL[59].OUT_BEL[12] |
| USR_ACCESS_DATA23 | output | CELL[59].OUT_BEL[14] |
| USR_ACCESS_DATA24 | output | CELL[59].OUT_BEL[16] |
| USR_ACCESS_DATA25 | output | CELL[59].OUT_BEL[18] |
| USR_ACCESS_DATA26 | output | CELL[59].OUT_BEL[20] |
| USR_ACCESS_DATA27 | output | CELL[59].OUT_BEL[22] |
| USR_ACCESS_DATA28 | output | CELL[59].OUT_BEL[24] |
| USR_ACCESS_DATA29 | output | CELL[59].OUT_BEL[26] |
| USR_ACCESS_DATA3 | output | CELL[58].OUT_BEL[6] |
| USR_ACCESS_DATA30 | output | CELL[59].OUT_BEL[28] |
| USR_ACCESS_DATA31 | output | CELL[59].OUT_BEL[30] |
| USR_ACCESS_DATA4 | output | CELL[58].OUT_BEL[8] |
| USR_ACCESS_DATA5 | output | CELL[58].OUT_BEL[10] |
| USR_ACCESS_DATA6 | output | CELL[58].OUT_BEL[12] |
| USR_ACCESS_DATA7 | output | CELL[58].OUT_BEL[14] |
| USR_ACCESS_DATA8 | output | CELL[58].OUT_BEL[16] |
| USR_ACCESS_DATA9 | output | CELL[58].OUT_BEL[18] |
| USR_ACCESS_VALID | output | CELL[57].OUT_BEL[0] |
| USR_CCLK_O | input | CELL[47].IMUX_CTRL[0] |
| USR_CCLK_TS | input | CELL[47].IMUX_IMUX_DELAY[2] |
| USR_DNA_CLK | input | CELL[42].IMUX_CTRL[0] |
| USR_DNA_DIN | input | CELL[42].IMUX_IMUX_DELAY[0] |
| USR_DNA_OUT | output | CELL[42].OUT_BEL[0] |
| USR_DNA_READ | input | CELL[42].IMUX_IMUX_DELAY[1] |
| USR_DNA_SHIFT | input | CELL[42].IMUX_IMUX_DELAY[2] |
| USR_DONE_O | input | CELL[47].IMUX_IMUX_DELAY[3] |
| USR_DONE_TS | input | CELL[47].IMUX_IMUX_DELAY[4] |
| USR_D_O_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[9] |
| USR_D_O_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[10] |
| USR_D_O_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[11] |
| USR_D_O_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[12] |
| USR_D_PIN_CFGIO0 | output | CELL[47].OUT_BEL[0] |
| USR_D_PIN_CFGIO1 | output | CELL[47].OUT_BEL[2] |
| USR_D_PIN_CFGIO2 | output | CELL[47].OUT_BEL[4] |
| USR_D_PIN_CFGIO3 | output | CELL[47].OUT_BEL[6] |
| USR_D_TS_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[13] |
| USR_D_TS_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[14] |
| USR_D_TS_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[15] |
| USR_D_TS_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[16] |
| USR_EFUSE0 | output | CELL[46].OUT_BEL[0] |
| USR_EFUSE1 | output | CELL[46].OUT_BEL[2] |
| USR_EFUSE10 | output | CELL[46].OUT_BEL[20] |
| USR_EFUSE11 | output | CELL[46].OUT_BEL[22] |
| USR_EFUSE12 | output | CELL[46].OUT_BEL[24] |
| USR_EFUSE13 | output | CELL[46].OUT_BEL[26] |
| USR_EFUSE14 | output | CELL[46].OUT_BEL[28] |
| USR_EFUSE15 | output | CELL[46].OUT_BEL[30] |
| USR_EFUSE16 | output | CELL[41].OUT_BEL[0] |
| USR_EFUSE17 | output | CELL[41].OUT_BEL[2] |
| USR_EFUSE18 | output | CELL[41].OUT_BEL[4] |
| USR_EFUSE19 | output | CELL[41].OUT_BEL[6] |
| USR_EFUSE2 | output | CELL[46].OUT_BEL[4] |
| USR_EFUSE20 | output | CELL[41].OUT_BEL[8] |
| USR_EFUSE21 | output | CELL[41].OUT_BEL[10] |
| USR_EFUSE22 | output | CELL[41].OUT_BEL[12] |
| USR_EFUSE23 | output | CELL[41].OUT_BEL[14] |
| USR_EFUSE24 | output | CELL[41].OUT_BEL[16] |
| USR_EFUSE25 | output | CELL[41].OUT_BEL[18] |
| USR_EFUSE26 | output | CELL[41].OUT_BEL[20] |
| USR_EFUSE27 | output | CELL[41].OUT_BEL[22] |
| USR_EFUSE28 | output | CELL[41].OUT_BEL[24] |
| USR_EFUSE29 | output | CELL[41].OUT_BEL[26] |
| USR_EFUSE3 | output | CELL[46].OUT_BEL[6] |
| USR_EFUSE30 | output | CELL[41].OUT_BEL[28] |
| USR_EFUSE31 | output | CELL[41].OUT_BEL[30] |
| USR_EFUSE4 | output | CELL[46].OUT_BEL[8] |
| USR_EFUSE5 | output | CELL[46].OUT_BEL[10] |
| USR_EFUSE6 | output | CELL[46].OUT_BEL[12] |
| USR_EFUSE7 | output | CELL[46].OUT_BEL[14] |
| USR_EFUSE8 | output | CELL[46].OUT_BEL[16] |
| USR_EFUSE9 | output | CELL[46].OUT_BEL[18] |
| USR_FCS_B_O | input | CELL[47].IMUX_IMUX_DELAY[7] |
| USR_FCS_B_TS | input | CELL[47].IMUX_IMUX_DELAY[8] |
| USR_GSR | input | CELL[47].IMUX_IMUX_DELAY[5] |
| USR_GTS | input | CELL[47].IMUX_IMUX_DELAY[6] |
| USR_TCK | input | CELL[43].IMUX_CTRL[1] |
| USR_TDI | input | CELL[43].IMUX_IMUX_DELAY[6] |
| USR_TDO | output | CELL[43].OUT_BEL[18] |
| USR_TMS | input | CELL[43].IMUX_IMUX_DELAY[5] |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| CELL[41].OUT_BEL[0] | CFG.USR_EFUSE16 |
| CELL[41].OUT_BEL[2] | CFG.USR_EFUSE17 |
| CELL[41].OUT_BEL[4] | CFG.USR_EFUSE18 |
| CELL[41].OUT_BEL[6] | CFG.USR_EFUSE19 |
| CELL[41].OUT_BEL[8] | CFG.USR_EFUSE20 |
| CELL[41].OUT_BEL[10] | CFG.USR_EFUSE21 |
| CELL[41].OUT_BEL[12] | CFG.USR_EFUSE22 |
| CELL[41].OUT_BEL[14] | CFG.USR_EFUSE23 |
| CELL[41].OUT_BEL[16] | CFG.USR_EFUSE24 |
| CELL[41].OUT_BEL[18] | CFG.USR_EFUSE25 |
| CELL[41].OUT_BEL[20] | CFG.USR_EFUSE26 |
| CELL[41].OUT_BEL[22] | CFG.USR_EFUSE27 |
| CELL[41].OUT_BEL[24] | CFG.USR_EFUSE28 |
| CELL[41].OUT_BEL[26] | CFG.USR_EFUSE29 |
| CELL[41].OUT_BEL[28] | CFG.USR_EFUSE30 |
| CELL[41].OUT_BEL[30] | CFG.USR_EFUSE31 |
| CELL[42].OUT_BEL[0] | CFG.USR_DNA_OUT |
| CELL[42].OUT_BEL[2] | CFG.DCI_LOCK |
| CELL[42].OUT_BEL[4] | CFG.BSCAN_CDR1 |
| CELL[42].OUT_BEL[6] | CFG.BSCAN_CDR2 |
| CELL[42].OUT_BEL[8] | CFG.BSCAN_CLKDR1 |
| CELL[42].OUT_BEL[10] | CFG.BSCAN_CLKDR2 |
| CELL[42].OUT_BEL[12] | CFG.BSCAN_RTI1 |
| CELL[42].OUT_BEL[14] | CFG.BSCAN_RTI2 |
| CELL[42].OUT_BEL[16] | CFG.BSCAN_SDR1 |
| CELL[42].OUT_BEL[18] | CFG.BSCAN_SDR2 |
| CELL[42].OUT_BEL[20] | CFG.BSCAN_SEL1 |
| CELL[42].OUT_BEL[22] | CFG.BSCAN_SEL2 |
| CELL[42].OUT_BEL[24] | CFG.BSCAN_TLR1 |
| CELL[42].OUT_BEL[26] | CFG.BSCAN_TLR2 |
| CELL[42].OUT_BEL[28] | CFG.BSCAN_UDR1 |
| CELL[42].OUT_BEL[30] | CFG.BSCAN_UDR2 |
| CELL[42].IMUX_CTRL[0] | CFG.USR_DNA_CLK |
| CELL[42].IMUX_IMUX_DELAY[0] | CFG.USR_DNA_DIN |
| CELL[42].IMUX_IMUX_DELAY[1] | CFG.USR_DNA_READ |
| CELL[42].IMUX_IMUX_DELAY[2] | CFG.USR_DNA_SHIFT |
| CELL[42].IMUX_IMUX_DELAY[3] | CFG.DCI_USR_RESET_IN |
| CELL[43].OUT_BEL[0] | CFG.ICAP_PR_DONE_BOT |
| CELL[43].OUT_BEL[2] | CFG.ICAP_PR_ERROR_BOT |
| CELL[43].OUT_BEL[4] | CFG.ICAP_AVAIL_BOT |
| CELL[43].OUT_BEL[6] | CFG.BSCAN_TCK1 |
| CELL[43].OUT_BEL[8] | CFG.BSCAN_TCK2 |
| CELL[43].OUT_BEL[10] | CFG.BSCAN_TMS1 |
| CELL[43].OUT_BEL[12] | CFG.BSCAN_TMS2 |
| CELL[43].OUT_BEL[14] | CFG.BSCAN_TDI1 |
| CELL[43].OUT_BEL[16] | CFG.BSCAN_TDI2 |
| CELL[43].OUT_BEL[18] | CFG.USR_TDO |
| CELL[43].IMUX_CTRL[1] | CFG.USR_TCK |
| CELL[43].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO1 |
| CELL[43].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO2 |
| CELL[43].IMUX_IMUX_DELAY[5] | CFG.USR_TMS |
| CELL[43].IMUX_IMUX_DELAY[6] | CFG.USR_TDI |
| CELL[44].OUT_BEL[0] | CFG.ICAP_OUT_BOT0 |
| CELL[44].OUT_BEL[2] | CFG.ICAP_OUT_BOT1 |
| CELL[44].OUT_BEL[4] | CFG.ICAP_OUT_BOT2 |
| CELL[44].OUT_BEL[6] | CFG.ICAP_OUT_BOT3 |
| CELL[44].OUT_BEL[8] | CFG.ICAP_OUT_BOT4 |
| CELL[44].OUT_BEL[10] | CFG.ICAP_OUT_BOT5 |
| CELL[44].OUT_BEL[12] | CFG.ICAP_OUT_BOT6 |
| CELL[44].OUT_BEL[14] | CFG.ICAP_OUT_BOT7 |
| CELL[44].OUT_BEL[16] | CFG.ICAP_OUT_BOT8 |
| CELL[44].OUT_BEL[18] | CFG.ICAP_OUT_BOT9 |
| CELL[44].OUT_BEL[20] | CFG.ICAP_OUT_BOT10 |
| CELL[44].OUT_BEL[22] | CFG.ICAP_OUT_BOT11 |
| CELL[44].OUT_BEL[24] | CFG.ICAP_OUT_BOT12 |
| CELL[44].OUT_BEL[26] | CFG.ICAP_OUT_BOT13 |
| CELL[44].OUT_BEL[28] | CFG.ICAP_OUT_BOT14 |
| CELL[44].OUT_BEL[30] | CFG.ICAP_OUT_BOT15 |
| CELL[44].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT0 |
| CELL[44].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT1 |
| CELL[44].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT2 |
| CELL[44].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT3 |
| CELL[44].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT4 |
| CELL[44].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT5 |
| CELL[44].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT6 |
| CELL[44].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT7 |
| CELL[44].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT8 |
| CELL[44].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT9 |
| CELL[44].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT10 |
| CELL[44].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT11 |
| CELL[44].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT12 |
| CELL[44].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT13 |
| CELL[44].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT14 |
| CELL[44].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT15 |
| CELL[45].OUT_BEL[0] | CFG.ICAP_OUT_BOT16 |
| CELL[45].OUT_BEL[2] | CFG.ICAP_OUT_BOT17 |
| CELL[45].OUT_BEL[4] | CFG.ICAP_OUT_BOT18 |
| CELL[45].OUT_BEL[6] | CFG.ICAP_OUT_BOT19 |
| CELL[45].OUT_BEL[8] | CFG.ICAP_OUT_BOT20 |
| CELL[45].OUT_BEL[10] | CFG.ICAP_OUT_BOT21 |
| CELL[45].OUT_BEL[12] | CFG.ICAP_OUT_BOT22 |
| CELL[45].OUT_BEL[14] | CFG.ICAP_OUT_BOT23 |
| CELL[45].OUT_BEL[16] | CFG.ICAP_OUT_BOT24 |
| CELL[45].OUT_BEL[18] | CFG.ICAP_OUT_BOT25 |
| CELL[45].OUT_BEL[20] | CFG.ICAP_OUT_BOT26 |
| CELL[45].OUT_BEL[22] | CFG.ICAP_OUT_BOT27 |
| CELL[45].OUT_BEL[24] | CFG.ICAP_OUT_BOT28 |
| CELL[45].OUT_BEL[26] | CFG.ICAP_OUT_BOT29 |
| CELL[45].OUT_BEL[28] | CFG.ICAP_OUT_BOT30 |
| CELL[45].OUT_BEL[30] | CFG.ICAP_OUT_BOT31 |
| CELL[45].IMUX_CTRL[0] | CFG.ICAP_CLK_BOT |
| CELL[45].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT16 |
| CELL[45].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT17 |
| CELL[45].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT18 |
| CELL[45].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT19 |
| CELL[45].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT20 |
| CELL[45].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT21 |
| CELL[45].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT22 |
| CELL[45].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT23 |
| CELL[45].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT24 |
| CELL[45].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT25 |
| CELL[45].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT26 |
| CELL[45].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT27 |
| CELL[45].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT28 |
| CELL[45].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT29 |
| CELL[45].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT30 |
| CELL[45].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT31 |
| CELL[46].OUT_BEL[0] | CFG.USR_EFUSE0 |
| CELL[46].OUT_BEL[2] | CFG.USR_EFUSE1 |
| CELL[46].OUT_BEL[4] | CFG.USR_EFUSE2 |
| CELL[46].OUT_BEL[6] | CFG.USR_EFUSE3 |
| CELL[46].OUT_BEL[8] | CFG.USR_EFUSE4 |
| CELL[46].OUT_BEL[10] | CFG.USR_EFUSE5 |
| CELL[46].OUT_BEL[12] | CFG.USR_EFUSE6 |
| CELL[46].OUT_BEL[14] | CFG.USR_EFUSE7 |
| CELL[46].OUT_BEL[16] | CFG.USR_EFUSE8 |
| CELL[46].OUT_BEL[18] | CFG.USR_EFUSE9 |
| CELL[46].OUT_BEL[20] | CFG.USR_EFUSE10 |
| CELL[46].OUT_BEL[22] | CFG.USR_EFUSE11 |
| CELL[46].OUT_BEL[24] | CFG.USR_EFUSE12 |
| CELL[46].OUT_BEL[26] | CFG.USR_EFUSE13 |
| CELL[46].OUT_BEL[28] | CFG.USR_EFUSE14 |
| CELL[46].OUT_BEL[30] | CFG.USR_EFUSE15 |
| CELL[47].OUT_BEL[0] | CFG.USR_D_PIN_CFGIO0 |
| CELL[47].OUT_BEL[2] | CFG.USR_D_PIN_CFGIO1 |
| CELL[47].OUT_BEL[4] | CFG.USR_D_PIN_CFGIO2 |
| CELL[47].OUT_BEL[6] | CFG.USR_D_PIN_CFGIO3 |
| CELL[47].OUT_BEL[8] | CFG.PROG_REQ |
| CELL[47].OUT_BEL[10] | CFG.EOS |
| CELL[47].OUT_BEL[12] | CFG.START_CFG_MCLK |
| CELL[47].OUT_BEL[14] | CFG.START_CFG_CLK |
| CELL[47].IMUX_CTRL[0] | CFG.USR_CCLK_O |
| CELL[47].IMUX_IMUX_DELAY[0] | CFG.KEY_CLEAR |
| CELL[47].IMUX_IMUX_DELAY[1] | CFG.PROG_ACK |
| CELL[47].IMUX_IMUX_DELAY[2] | CFG.USR_CCLK_TS |
| CELL[47].IMUX_IMUX_DELAY[3] | CFG.USR_DONE_O |
| CELL[47].IMUX_IMUX_DELAY[4] | CFG.USR_DONE_TS |
| CELL[47].IMUX_IMUX_DELAY[5] | CFG.USR_GSR |
| CELL[47].IMUX_IMUX_DELAY[6] | CFG.USR_GTS |
| CELL[47].IMUX_IMUX_DELAY[7] | CFG.USR_FCS_B_O |
| CELL[47].IMUX_IMUX_DELAY[8] | CFG.USR_FCS_B_TS |
| CELL[47].IMUX_IMUX_DELAY[9] | CFG.USR_D_O_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[10] | CFG.USR_D_O_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[11] | CFG.USR_D_O_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[12] | CFG.USR_D_O_CFGIO3 |
| CELL[47].IMUX_IMUX_DELAY[13] | CFG.USR_D_TS_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[14] | CFG.USR_D_TS_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[15] | CFG.USR_D_TS_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[16] | CFG.USR_D_TS_CFGIO3 |
| CELL[48].OUT_BEL[0] | CFG.IOX_CFGDATA0 |
| CELL[48].OUT_BEL[2] | CFG.IOX_CFGDATA1 |
| CELL[48].OUT_BEL[4] | CFG.IOX_CFGDATA2 |
| CELL[48].OUT_BEL[6] | CFG.IOX_CFGDATA3 |
| CELL[48].OUT_BEL[8] | CFG.IOX_CFGDATA4 |
| CELL[48].OUT_BEL[10] | CFG.IOX_CFGDATA5 |
| CELL[48].OUT_BEL[12] | CFG.IOX_CFGDATA6 |
| CELL[48].OUT_BEL[14] | CFG.IOX_CFGDATA7 |
| CELL[48].OUT_BEL[16] | CFG.IOX_CFGDATA8 |
| CELL[48].OUT_BEL[18] | CFG.IOX_CFGDATA9 |
| CELL[48].OUT_BEL[20] | CFG.IOX_CFGDATA10 |
| CELL[48].OUT_BEL[22] | CFG.IOX_CFGDATA11 |
| CELL[48].OUT_BEL[24] | CFG.IOX_CFGDATA12 |
| CELL[48].OUT_BEL[26] | CFG.IOX_CFGDATA13 |
| CELL[48].OUT_BEL[28] | CFG.IOX_CFGDATA14 |
| CELL[48].OUT_BEL[30] | CFG.IOX_CFGDATA15 |
| CELL[48].IMUX_IMUX_DELAY[0] | CFG.IOX_TDO |
| CELL[48].IMUX_IMUX_DELAY[1] | CFG.IOX_INITBO |
| CELL[49].OUT_BEL[0] | CFG.IOX_CFGDATA16 |
| CELL[49].OUT_BEL[2] | CFG.IOX_CFGDATA17 |
| CELL[49].OUT_BEL[4] | CFG.IOX_CFGDATA18 |
| CELL[49].OUT_BEL[6] | CFG.IOX_CFGDATA19 |
| CELL[49].OUT_BEL[8] | CFG.IOX_CFGDATA20 |
| CELL[49].OUT_BEL[10] | CFG.IOX_CFGDATA21 |
| CELL[49].OUT_BEL[12] | CFG.IOX_CFGDATA22 |
| CELL[49].OUT_BEL[14] | CFG.IOX_CFGDATA23 |
| CELL[49].OUT_BEL[16] | CFG.IOX_CFGDATA24 |
| CELL[49].OUT_BEL[18] | CFG.IOX_CFGDATA25 |
| CELL[49].OUT_BEL[20] | CFG.IOX_CFGDATA26 |
| CELL[49].OUT_BEL[22] | CFG.IOX_CFGDATA27 |
| CELL[49].OUT_BEL[24] | CFG.IOX_CFGDATA28 |
| CELL[49].OUT_BEL[26] | CFG.IOX_CFGDATA29 |
| CELL[49].OUT_BEL[28] | CFG.IOX_CFGDATA30 |
| CELL[49].OUT_BEL[30] | CFG.IOX_CFGDATA31 |
| CELL[50].OUT_BEL[0] | CFG.IOX_CCLK |
| CELL[50].OUT_BEL[2] | CFG.IOX_CFGMASTER |
| CELL[50].OUT_BEL[4] | CFG.IOX_VGG_COMP_OUT |
| CELL[50].OUT_BEL[6] | CFG.IOX_INITBI |
| CELL[50].OUT_BEL[8] | CFG.IOX_PUDCB |
| CELL[50].OUT_BEL[10] | CFG.IOX_RDWRB |
| CELL[50].OUT_BEL[12] | CFG.IOX_MODE0 |
| CELL[50].OUT_BEL[14] | CFG.IOX_MODE1 |
| CELL[50].OUT_BEL[16] | CFG.IOX_MODE2 |
| CELL[51].OUT_BEL[0] | CFG.ECC_FAR16 |
| CELL[51].OUT_BEL[2] | CFG.ECC_FAR17 |
| CELL[51].OUT_BEL[4] | CFG.ECC_FAR18 |
| CELL[51].OUT_BEL[6] | CFG.ECC_FAR19 |
| CELL[51].OUT_BEL[8] | CFG.ECC_FAR20 |
| CELL[51].OUT_BEL[10] | CFG.ECC_FAR21 |
| CELL[51].OUT_BEL[12] | CFG.ECC_FAR22 |
| CELL[51].OUT_BEL[14] | CFG.ECC_FAR23 |
| CELL[51].OUT_BEL[16] | CFG.ECC_FAR24 |
| CELL[51].OUT_BEL[18] | CFG.ECC_FAR25 |
| CELL[51].OUT_BEL[20] | CFG.RBCRC_ERROR |
| CELL[51].OUT_BEL[22] | CFG.ECC_ERROR_NOTSINGLE |
| CELL[51].OUT_BEL[24] | CFG.ECC_ERROR_SINGLE |
| CELL[51].OUT_BEL[26] | CFG.ECC_END_OF_FRAME |
| CELL[51].OUT_BEL[28] | CFG.ECC_END_OF_SCAN |
| CELL[51].IMUX_IMUX_DELAY[15] | CFG.ECC_FAR_SEL0 |
| CELL[51].IMUX_IMUX_DELAY[16] | CFG.ECC_FAR_SEL1 |
| CELL[52].OUT_BEL[0] | CFG.ECC_FAR0 |
| CELL[52].OUT_BEL[2] | CFG.ECC_FAR1 |
| CELL[52].OUT_BEL[4] | CFG.ECC_FAR2 |
| CELL[52].OUT_BEL[6] | CFG.ECC_FAR3 |
| CELL[52].OUT_BEL[8] | CFG.ECC_FAR4 |
| CELL[52].OUT_BEL[10] | CFG.ECC_FAR5 |
| CELL[52].OUT_BEL[12] | CFG.ECC_FAR6 |
| CELL[52].OUT_BEL[14] | CFG.ECC_FAR7 |
| CELL[52].OUT_BEL[16] | CFG.ECC_FAR8 |
| CELL[52].OUT_BEL[18] | CFG.ECC_FAR9 |
| CELL[52].OUT_BEL[20] | CFG.ECC_FAR10 |
| CELL[52].OUT_BEL[22] | CFG.ECC_FAR11 |
| CELL[52].OUT_BEL[24] | CFG.ECC_FAR12 |
| CELL[52].OUT_BEL[26] | CFG.ECC_FAR13 |
| CELL[52].OUT_BEL[28] | CFG.ECC_FAR14 |
| CELL[52].OUT_BEL[30] | CFG.ECC_FAR15 |
| CELL[52].OUT_BEL[31] | CFG.ECC_FAR26 |
| CELL[53].OUT_BEL[0] | CFG.BSCAN_SDR3 |
| CELL[53].OUT_BEL[2] | CFG.BSCAN_SDR4 |
| CELL[53].OUT_BEL[4] | CFG.BSCAN_SEL3 |
| CELL[53].OUT_BEL[6] | CFG.BSCAN_SEL4 |
| CELL[53].OUT_BEL[8] | CFG.BSCAN_TLR3 |
| CELL[53].OUT_BEL[10] | CFG.BSCAN_TLR4 |
| CELL[53].OUT_BEL[12] | CFG.BSCAN_UDR3 |
| CELL[53].OUT_BEL[14] | CFG.BSCAN_UDR4 |
| CELL[54].OUT_BEL[0] | CFG.ICAP_PR_DONE_TOP |
| CELL[54].OUT_BEL[2] | CFG.ICAP_PR_ERROR_TOP |
| CELL[54].OUT_BEL[4] | CFG.ICAP_AVAIL_TOP |
| CELL[54].OUT_BEL[6] | CFG.BSCAN_TCK3 |
| CELL[54].OUT_BEL[8] | CFG.BSCAN_TCK4 |
| CELL[54].OUT_BEL[10] | CFG.BSCAN_TMS3 |
| CELL[54].OUT_BEL[12] | CFG.BSCAN_TMS4 |
| CELL[54].OUT_BEL[14] | CFG.BSCAN_TDI3 |
| CELL[54].OUT_BEL[16] | CFG.BSCAN_TDI4 |
| CELL[54].OUT_BEL[18] | CFG.BSCAN_CDR3 |
| CELL[54].OUT_BEL[20] | CFG.BSCAN_CDR4 |
| CELL[54].OUT_BEL[22] | CFG.BSCAN_CLKDR3 |
| CELL[54].OUT_BEL[24] | CFG.BSCAN_CLKDR4 |
| CELL[54].OUT_BEL[26] | CFG.BSCAN_RTI3 |
| CELL[54].OUT_BEL[28] | CFG.BSCAN_RTI4 |
| CELL[54].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO3 |
| CELL[54].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO4 |
| CELL[55].OUT_BEL[0] | CFG.ICAP_OUT_TOP0 |
| CELL[55].OUT_BEL[2] | CFG.ICAP_OUT_TOP1 |
| CELL[55].OUT_BEL[4] | CFG.ICAP_OUT_TOP2 |
| CELL[55].OUT_BEL[6] | CFG.ICAP_OUT_TOP3 |
| CELL[55].OUT_BEL[8] | CFG.ICAP_OUT_TOP4 |
| CELL[55].OUT_BEL[10] | CFG.ICAP_OUT_TOP5 |
| CELL[55].OUT_BEL[12] | CFG.ICAP_OUT_TOP6 |
| CELL[55].OUT_BEL[14] | CFG.ICAP_OUT_TOP7 |
| CELL[55].OUT_BEL[16] | CFG.ICAP_OUT_TOP8 |
| CELL[55].OUT_BEL[18] | CFG.ICAP_OUT_TOP9 |
| CELL[55].OUT_BEL[20] | CFG.ICAP_OUT_TOP10 |
| CELL[55].OUT_BEL[22] | CFG.ICAP_OUT_TOP11 |
| CELL[55].OUT_BEL[24] | CFG.ICAP_OUT_TOP12 |
| CELL[55].OUT_BEL[26] | CFG.ICAP_OUT_TOP13 |
| CELL[55].OUT_BEL[28] | CFG.ICAP_OUT_TOP14 |
| CELL[55].OUT_BEL[30] | CFG.ICAP_OUT_TOP15 |
| CELL[55].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP0 |
| CELL[55].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP1 |
| CELL[55].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP2 |
| CELL[55].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP3 |
| CELL[55].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP4 |
| CELL[55].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP5 |
| CELL[55].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP6 |
| CELL[55].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP7 |
| CELL[55].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP8 |
| CELL[55].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP9 |
| CELL[55].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP10 |
| CELL[55].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP11 |
| CELL[55].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP12 |
| CELL[55].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP13 |
| CELL[55].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP14 |
| CELL[55].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP15 |
| CELL[56].OUT_BEL[0] | CFG.ICAP_OUT_TOP16 |
| CELL[56].OUT_BEL[2] | CFG.ICAP_OUT_TOP17 |
| CELL[56].OUT_BEL[4] | CFG.ICAP_OUT_TOP18 |
| CELL[56].OUT_BEL[6] | CFG.ICAP_OUT_TOP19 |
| CELL[56].OUT_BEL[8] | CFG.ICAP_OUT_TOP20 |
| CELL[56].OUT_BEL[10] | CFG.ICAP_OUT_TOP21 |
| CELL[56].OUT_BEL[12] | CFG.ICAP_OUT_TOP22 |
| CELL[56].OUT_BEL[14] | CFG.ICAP_OUT_TOP23 |
| CELL[56].OUT_BEL[16] | CFG.ICAP_OUT_TOP24 |
| CELL[56].OUT_BEL[18] | CFG.ICAP_OUT_TOP25 |
| CELL[56].OUT_BEL[20] | CFG.ICAP_OUT_TOP26 |
| CELL[56].OUT_BEL[22] | CFG.ICAP_OUT_TOP27 |
| CELL[56].OUT_BEL[24] | CFG.ICAP_OUT_TOP28 |
| CELL[56].OUT_BEL[26] | CFG.ICAP_OUT_TOP29 |
| CELL[56].OUT_BEL[28] | CFG.ICAP_OUT_TOP30 |
| CELL[56].OUT_BEL[30] | CFG.ICAP_OUT_TOP31 |
| CELL[56].IMUX_CTRL[0] | CFG.ICAP_CLK_TOP |
| CELL[56].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP16 |
| CELL[56].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP17 |
| CELL[56].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP18 |
| CELL[56].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP19 |
| CELL[56].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP20 |
| CELL[56].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP21 |
| CELL[56].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP22 |
| CELL[56].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP23 |
| CELL[56].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP24 |
| CELL[56].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP25 |
| CELL[56].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP26 |
| CELL[56].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP27 |
| CELL[56].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP28 |
| CELL[56].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP29 |
| CELL[56].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP30 |
| CELL[56].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP31 |
| CELL[57].OUT_BEL[0] | CFG.USR_ACCESS_VALID |
| CELL[57].OUT_BEL[2] | CFG.USR_ACCESS_CLK |
| CELL[58].OUT_BEL[0] | CFG.USR_ACCESS_DATA0 |
| CELL[58].OUT_BEL[2] | CFG.USR_ACCESS_DATA1 |
| CELL[58].OUT_BEL[4] | CFG.USR_ACCESS_DATA2 |
| CELL[58].OUT_BEL[6] | CFG.USR_ACCESS_DATA3 |
| CELL[58].OUT_BEL[8] | CFG.USR_ACCESS_DATA4 |
| CELL[58].OUT_BEL[10] | CFG.USR_ACCESS_DATA5 |
| CELL[58].OUT_BEL[12] | CFG.USR_ACCESS_DATA6 |
| CELL[58].OUT_BEL[14] | CFG.USR_ACCESS_DATA7 |
| CELL[58].OUT_BEL[16] | CFG.USR_ACCESS_DATA8 |
| CELL[58].OUT_BEL[18] | CFG.USR_ACCESS_DATA9 |
| CELL[58].OUT_BEL[20] | CFG.USR_ACCESS_DATA10 |
| CELL[58].OUT_BEL[22] | CFG.USR_ACCESS_DATA11 |
| CELL[58].OUT_BEL[24] | CFG.USR_ACCESS_DATA12 |
| CELL[58].OUT_BEL[26] | CFG.USR_ACCESS_DATA13 |
| CELL[58].OUT_BEL[28] | CFG.USR_ACCESS_DATA14 |
| CELL[58].OUT_BEL[30] | CFG.USR_ACCESS_DATA15 |
| CELL[59].OUT_BEL[0] | CFG.USR_ACCESS_DATA16 |
| CELL[59].OUT_BEL[2] | CFG.USR_ACCESS_DATA17 |
| CELL[59].OUT_BEL[4] | CFG.USR_ACCESS_DATA18 |
| CELL[59].OUT_BEL[6] | CFG.USR_ACCESS_DATA19 |
| CELL[59].OUT_BEL[8] | CFG.USR_ACCESS_DATA20 |
| CELL[59].OUT_BEL[10] | CFG.USR_ACCESS_DATA21 |
| CELL[59].OUT_BEL[12] | CFG.USR_ACCESS_DATA22 |
| CELL[59].OUT_BEL[14] | CFG.USR_ACCESS_DATA23 |
| CELL[59].OUT_BEL[16] | CFG.USR_ACCESS_DATA24 |
| CELL[59].OUT_BEL[18] | CFG.USR_ACCESS_DATA25 |
| CELL[59].OUT_BEL[20] | CFG.USR_ACCESS_DATA26 |
| CELL[59].OUT_BEL[22] | CFG.USR_ACCESS_DATA27 |
| CELL[59].OUT_BEL[24] | CFG.USR_ACCESS_DATA28 |
| CELL[59].OUT_BEL[26] | CFG.USR_ACCESS_DATA29 |
| CELL[59].OUT_BEL[28] | CFG.USR_ACCESS_DATA30 |
| CELL[59].OUT_BEL[30] | CFG.USR_ACCESS_DATA31 |
Tile CFG_CSEC
Cells: 60
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| ARADDR0 | input | CELL[20].IMUX_IMUX_DELAY[9] |
| ARADDR1 | input | CELL[20].IMUX_IMUX_DELAY[10] |
| ARADDR10 | input | CELL[21].IMUX_IMUX_DELAY[3] |
| ARADDR11 | input | CELL[21].IMUX_IMUX_DELAY[4] |
| ARADDR12 | input | CELL[21].IMUX_IMUX_DELAY[5] |
| ARADDR13 | input | CELL[21].IMUX_IMUX_DELAY[6] |
| ARADDR14 | input | CELL[21].IMUX_IMUX_DELAY[7] |
| ARADDR15 | input | CELL[21].IMUX_IMUX_DELAY[8] |
| ARADDR16 | input | CELL[21].IMUX_IMUX_DELAY[9] |
| ARADDR17 | input | CELL[21].IMUX_IMUX_DELAY[10] |
| ARADDR18 | input | CELL[21].IMUX_IMUX_DELAY[11] |
| ARADDR19 | input | CELL[21].IMUX_IMUX_DELAY[12] |
| ARADDR2 | input | CELL[20].IMUX_IMUX_DELAY[11] |
| ARADDR20 | input | CELL[21].IMUX_IMUX_DELAY[13] |
| ARADDR21 | input | CELL[21].IMUX_IMUX_DELAY[14] |
| ARADDR22 | input | CELL[20].IMUX_IMUX_DELAY[3] |
| ARADDR23 | input | CELL[20].IMUX_IMUX_DELAY[4] |
| ARADDR24 | input | CELL[20].IMUX_IMUX_DELAY[5] |
| ARADDR25 | input | CELL[20].IMUX_IMUX_DELAY[6] |
| ARADDR26 | input | CELL[20].IMUX_IMUX_DELAY[7] |
| ARADDR27 | input | CELL[20].IMUX_IMUX_DELAY[8] |
| ARADDR3 | input | CELL[20].IMUX_IMUX_DELAY[12] |
| ARADDR4 | input | CELL[20].IMUX_IMUX_DELAY[13] |
| ARADDR5 | input | CELL[20].IMUX_IMUX_DELAY[14] |
| ARADDR6 | input | CELL[20].IMUX_IMUX_DELAY[15] |
| ARADDR7 | input | CELL[21].IMUX_IMUX_DELAY[0] |
| ARADDR8 | input | CELL[21].IMUX_IMUX_DELAY[1] |
| ARADDR9 | input | CELL[21].IMUX_IMUX_DELAY[2] |
| ARBURST0 | input | CELL[22].IMUX_IMUX_DELAY[6] |
| ARBURST1 | input | CELL[22].IMUX_IMUX_DELAY[7] |
| ARCACHE0 | input | CELL[22].IMUX_IMUX_DELAY[9] |
| ARCACHE1 | input | CELL[22].IMUX_IMUX_DELAY[10] |
| ARCACHE2 | input | CELL[22].IMUX_IMUX_DELAY[11] |
| ARCACHE3 | input | CELL[22].IMUX_IMUX_DELAY[12] |
| ARID0 | input | CELL[31].IMUX_IMUX_DELAY[1] |
| ARID1 | input | CELL[31].IMUX_IMUX_DELAY[2] |
| ARID2 | input | CELL[31].IMUX_IMUX_DELAY[3] |
| ARID3 | input | CELL[31].IMUX_IMUX_DELAY[4] |
| ARID4 | input | CELL[31].IMUX_IMUX_DELAY[5] |
| ARID5 | input | CELL[31].IMUX_IMUX_DELAY[6] |
| ARID6 | input | CELL[31].IMUX_IMUX_DELAY[7] |
| ARID7 | input | CELL[31].IMUX_IMUX_DELAY[8] |
| ARLEN0 | input | CELL[21].IMUX_IMUX_DELAY[15] |
| ARLEN1 | input | CELL[22].IMUX_IMUX_DELAY[0] |
| ARLEN2 | input | CELL[22].IMUX_IMUX_DELAY[1] |
| ARLEN3 | input | CELL[22].IMUX_IMUX_DELAY[2] |
| ARLOCK | input | CELL[22].IMUX_IMUX_DELAY[8] |
| ARPROT0 | input | CELL[22].IMUX_IMUX_DELAY[13] |
| ARPROT1 | input | CELL[22].IMUX_IMUX_DELAY[14] |
| ARPROT2 | input | CELL[22].IMUX_IMUX_DELAY[15] |
| ARQOS0 | input | CELL[23].IMUX_IMUX_DELAY[0] |
| ARQOS1 | input | CELL[23].IMUX_IMUX_DELAY[1] |
| ARQOS2 | input | CELL[23].IMUX_IMUX_DELAY[2] |
| ARQOS3 | input | CELL[23].IMUX_IMUX_DELAY[3] |
| ARREADY | output | CELL[20].OUT_BEL[0] |
| ARSIZE0 | input | CELL[22].IMUX_IMUX_DELAY[3] |
| ARSIZE1 | input | CELL[22].IMUX_IMUX_DELAY[4] |
| ARSIZE2 | input | CELL[22].IMUX_IMUX_DELAY[5] |
| ARVALID | input | CELL[20].IMUX_IMUX_DELAY[0] |
| AWADDR0 | input | CELL[24].IMUX_IMUX_DELAY[9] |
| AWADDR1 | input | CELL[24].IMUX_IMUX_DELAY[10] |
| AWADDR10 | input | CELL[25].IMUX_IMUX_DELAY[3] |
| AWADDR11 | input | CELL[25].IMUX_IMUX_DELAY[4] |
| AWADDR12 | input | CELL[25].IMUX_IMUX_DELAY[5] |
| AWADDR13 | input | CELL[25].IMUX_IMUX_DELAY[6] |
| AWADDR14 | input | CELL[25].IMUX_IMUX_DELAY[7] |
| AWADDR15 | input | CELL[25].IMUX_IMUX_DELAY[8] |
| AWADDR16 | input | CELL[25].IMUX_IMUX_DELAY[9] |
| AWADDR17 | input | CELL[25].IMUX_IMUX_DELAY[10] |
| AWADDR18 | input | CELL[25].IMUX_IMUX_DELAY[11] |
| AWADDR19 | input | CELL[25].IMUX_IMUX_DELAY[12] |
| AWADDR2 | input | CELL[24].IMUX_IMUX_DELAY[11] |
| AWADDR20 | input | CELL[25].IMUX_IMUX_DELAY[13] |
| AWADDR21 | input | CELL[25].IMUX_IMUX_DELAY[14] |
| AWADDR22 | input | CELL[24].IMUX_IMUX_DELAY[3] |
| AWADDR23 | input | CELL[24].IMUX_IMUX_DELAY[4] |
| AWADDR24 | input | CELL[24].IMUX_IMUX_DELAY[5] |
| AWADDR25 | input | CELL[24].IMUX_IMUX_DELAY[6] |
| AWADDR26 | input | CELL[24].IMUX_IMUX_DELAY[7] |
| AWADDR27 | input | CELL[24].IMUX_IMUX_DELAY[8] |
| AWADDR3 | input | CELL[24].IMUX_IMUX_DELAY[12] |
| AWADDR4 | input | CELL[24].IMUX_IMUX_DELAY[13] |
| AWADDR5 | input | CELL[24].IMUX_IMUX_DELAY[14] |
| AWADDR6 | input | CELL[24].IMUX_IMUX_DELAY[15] |
| AWADDR7 | input | CELL[25].IMUX_IMUX_DELAY[0] |
| AWADDR8 | input | CELL[25].IMUX_IMUX_DELAY[1] |
| AWADDR9 | input | CELL[25].IMUX_IMUX_DELAY[2] |
| AWBURST0 | input | CELL[26].IMUX_IMUX_DELAY[6] |
| AWBURST1 | input | CELL[26].IMUX_IMUX_DELAY[7] |
| AWCACHE0 | input | CELL[26].IMUX_IMUX_DELAY[9] |
| AWCACHE1 | input | CELL[26].IMUX_IMUX_DELAY[10] |
| AWCACHE2 | input | CELL[26].IMUX_IMUX_DELAY[11] |
| AWCACHE3 | input | CELL[26].IMUX_IMUX_DELAY[12] |
| AWID0 | input | CELL[32].IMUX_IMUX_DELAY[1] |
| AWID1 | input | CELL[32].IMUX_IMUX_DELAY[2] |
| AWID2 | input | CELL[32].IMUX_IMUX_DELAY[3] |
| AWID3 | input | CELL[32].IMUX_IMUX_DELAY[4] |
| AWID4 | input | CELL[32].IMUX_IMUX_DELAY[5] |
| AWID5 | input | CELL[32].IMUX_IMUX_DELAY[6] |
| AWID6 | input | CELL[32].IMUX_IMUX_DELAY[7] |
| AWID7 | input | CELL[32].IMUX_IMUX_DELAY[8] |
| AWLEN0 | input | CELL[25].IMUX_IMUX_DELAY[15] |
| AWLEN1 | input | CELL[26].IMUX_IMUX_DELAY[0] |
| AWLEN2 | input | CELL[26].IMUX_IMUX_DELAY[1] |
| AWLEN3 | input | CELL[26].IMUX_IMUX_DELAY[2] |
| AWLOCK | input | CELL[26].IMUX_IMUX_DELAY[8] |
| AWPROT0 | input | CELL[26].IMUX_IMUX_DELAY[13] |
| AWPROT1 | input | CELL[26].IMUX_IMUX_DELAY[14] |
| AWPROT2 | input | CELL[26].IMUX_IMUX_DELAY[15] |
| AWQOS0 | input | CELL[27].IMUX_IMUX_DELAY[0] |
| AWQOS1 | input | CELL[27].IMUX_IMUX_DELAY[1] |
| AWQOS2 | input | CELL[27].IMUX_IMUX_DELAY[2] |
| AWQOS3 | input | CELL[27].IMUX_IMUX_DELAY[3] |
| AWREADY | output | CELL[24].OUT_BEL[0] |
| AWSIZE0 | input | CELL[26].IMUX_IMUX_DELAY[3] |
| AWSIZE1 | input | CELL[26].IMUX_IMUX_DELAY[4] |
| AWSIZE2 | input | CELL[26].IMUX_IMUX_DELAY[5] |
| AWVALID | input | CELL[24].IMUX_IMUX_DELAY[0] |
| AXI_CLK | input | CELL[20].IMUX_CTRL[0] |
| BID0 | output | CELL[34].OUT_BEL[2] |
| BID1 | output | CELL[34].OUT_BEL[4] |
| BID2 | output | CELL[34].OUT_BEL[6] |
| BID3 | output | CELL[34].OUT_BEL[8] |
| BID4 | output | CELL[34].OUT_BEL[10] |
| BID5 | output | CELL[34].OUT_BEL[12] |
| BID6 | output | CELL[34].OUT_BEL[14] |
| BID7 | output | CELL[34].OUT_BEL[16] |
| BREADY | input | CELL[34].IMUX_IMUX_DELAY[0] |
| BRESP0 | output | CELL[34].OUT_BEL[18] |
| BRESP1 | output | CELL[34].OUT_BEL[20] |
| BSCAN_CDR1 | output | CELL[42].OUT_BEL[4] |
| BSCAN_CDR2 | output | CELL[42].OUT_BEL[6] |
| BSCAN_CDR3 | output | CELL[54].OUT_BEL[18] |
| BSCAN_CDR4 | output | CELL[54].OUT_BEL[20] |
| BSCAN_CLKDR1 | output | CELL[42].OUT_BEL[8] |
| BSCAN_CLKDR2 | output | CELL[42].OUT_BEL[10] |
| BSCAN_CLKDR3 | output | CELL[54].OUT_BEL[22] |
| BSCAN_CLKDR4 | output | CELL[54].OUT_BEL[24] |
| BSCAN_RTI1 | output | CELL[42].OUT_BEL[12] |
| BSCAN_RTI2 | output | CELL[42].OUT_BEL[14] |
| BSCAN_RTI3 | output | CELL[54].OUT_BEL[26] |
| BSCAN_RTI4 | output | CELL[54].OUT_BEL[28] |
| BSCAN_SDR1 | output | CELL[42].OUT_BEL[16] |
| BSCAN_SDR2 | output | CELL[42].OUT_BEL[18] |
| BSCAN_SDR3 | output | CELL[53].OUT_BEL[0] |
| BSCAN_SDR4 | output | CELL[53].OUT_BEL[2] |
| BSCAN_SEL1 | output | CELL[42].OUT_BEL[20] |
| BSCAN_SEL2 | output | CELL[42].OUT_BEL[22] |
| BSCAN_SEL3 | output | CELL[53].OUT_BEL[4] |
| BSCAN_SEL4 | output | CELL[53].OUT_BEL[6] |
| BSCAN_TCK1 | output | CELL[43].OUT_BEL[6] |
| BSCAN_TCK2 | output | CELL[43].OUT_BEL[8] |
| BSCAN_TCK3 | output | CELL[54].OUT_BEL[6] |
| BSCAN_TCK4 | output | CELL[54].OUT_BEL[8] |
| BSCAN_TDI1 | output | CELL[43].OUT_BEL[14] |
| BSCAN_TDI2 | output | CELL[43].OUT_BEL[16] |
| BSCAN_TDI3 | output | CELL[54].OUT_BEL[14] |
| BSCAN_TDI4 | output | CELL[54].OUT_BEL[16] |
| BSCAN_TDO1 | input | CELL[43].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO2 | input | CELL[43].IMUX_IMUX_DELAY[3] |
| BSCAN_TDO3 | input | CELL[54].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO4 | input | CELL[54].IMUX_IMUX_DELAY[3] |
| BSCAN_TLR1 | output | CELL[42].OUT_BEL[24] |
| BSCAN_TLR2 | output | CELL[42].OUT_BEL[26] |
| BSCAN_TLR3 | output | CELL[53].OUT_BEL[8] |
| BSCAN_TLR4 | output | CELL[53].OUT_BEL[10] |
| BSCAN_TMS1 | output | CELL[43].OUT_BEL[10] |
| BSCAN_TMS2 | output | CELL[43].OUT_BEL[12] |
| BSCAN_TMS3 | output | CELL[54].OUT_BEL[10] |
| BSCAN_TMS4 | output | CELL[54].OUT_BEL[12] |
| BSCAN_UDR1 | output | CELL[42].OUT_BEL[28] |
| BSCAN_UDR2 | output | CELL[42].OUT_BEL[30] |
| BSCAN_UDR3 | output | CELL[53].OUT_BEL[12] |
| BSCAN_UDR4 | output | CELL[53].OUT_BEL[14] |
| BVALID | output | CELL[34].OUT_BEL[0] |
| DCI_LOCK | output | CELL[42].OUT_BEL[2] |
| DCI_USR_RESET_IN | input | CELL[42].IMUX_IMUX_DELAY[3] |
| ECC_END_OF_FRAME | output | CELL[51].OUT_BEL[26] |
| ECC_END_OF_SCAN | output | CELL[51].OUT_BEL[28] |
| ECC_ERROR_NOTSINGLE | output | CELL[51].OUT_BEL[22] |
| ECC_ERROR_SINGLE | output | CELL[51].OUT_BEL[24] |
| ECC_FAR0 | output | CELL[52].OUT_BEL[0] |
| ECC_FAR1 | output | CELL[52].OUT_BEL[2] |
| ECC_FAR10 | output | CELL[52].OUT_BEL[20] |
| ECC_FAR11 | output | CELL[52].OUT_BEL[22] |
| ECC_FAR12 | output | CELL[52].OUT_BEL[24] |
| ECC_FAR13 | output | CELL[52].OUT_BEL[26] |
| ECC_FAR14 | output | CELL[52].OUT_BEL[28] |
| ECC_FAR15 | output | CELL[52].OUT_BEL[30] |
| ECC_FAR16 | output | CELL[51].OUT_BEL[0] |
| ECC_FAR17 | output | CELL[51].OUT_BEL[2] |
| ECC_FAR18 | output | CELL[51].OUT_BEL[4] |
| ECC_FAR19 | output | CELL[51].OUT_BEL[6] |
| ECC_FAR2 | output | CELL[52].OUT_BEL[4] |
| ECC_FAR20 | output | CELL[51].OUT_BEL[8] |
| ECC_FAR21 | output | CELL[51].OUT_BEL[10] |
| ECC_FAR22 | output | CELL[51].OUT_BEL[12] |
| ECC_FAR23 | output | CELL[51].OUT_BEL[14] |
| ECC_FAR24 | output | CELL[51].OUT_BEL[16] |
| ECC_FAR25 | output | CELL[51].OUT_BEL[18] |
| ECC_FAR26 | output | CELL[52].OUT_BEL[31] |
| ECC_FAR3 | output | CELL[52].OUT_BEL[6] |
| ECC_FAR4 | output | CELL[52].OUT_BEL[8] |
| ECC_FAR5 | output | CELL[52].OUT_BEL[10] |
| ECC_FAR6 | output | CELL[52].OUT_BEL[12] |
| ECC_FAR7 | output | CELL[52].OUT_BEL[14] |
| ECC_FAR8 | output | CELL[52].OUT_BEL[16] |
| ECC_FAR9 | output | CELL[52].OUT_BEL[18] |
| ECC_FAR_SEL0 | input | CELL[51].IMUX_IMUX_DELAY[15] |
| ECC_FAR_SEL1 | input | CELL[51].IMUX_IMUX_DELAY[16] |
| EOS | output | CELL[47].OUT_BEL[10] |
| ICAP_AVAIL_BOT | output | CELL[43].OUT_BEL[4] |
| ICAP_AVAIL_TOP | output | CELL[54].OUT_BEL[4] |
| ICAP_CLK_BOT | input | CELL[45].IMUX_CTRL[0] |
| ICAP_CLK_TOP | input | CELL[56].IMUX_CTRL[0] |
| ICAP_CS_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[1] |
| ICAP_CS_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT0 | input | CELL[44].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT1 | input | CELL[44].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT10 | input | CELL[44].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT11 | input | CELL[44].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT12 | input | CELL[44].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT13 | input | CELL[44].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT14 | input | CELL[44].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT15 | input | CELL[44].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT16 | input | CELL[45].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT17 | input | CELL[45].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT18 | input | CELL[45].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT19 | input | CELL[45].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT2 | input | CELL[44].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT20 | input | CELL[45].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT21 | input | CELL[45].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT22 | input | CELL[45].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT23 | input | CELL[45].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT24 | input | CELL[45].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT25 | input | CELL[45].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_BOT26 | input | CELL[45].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT27 | input | CELL[45].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT28 | input | CELL[45].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT29 | input | CELL[45].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT3 | input | CELL[44].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT30 | input | CELL[45].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT31 | input | CELL[45].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT4 | input | CELL[44].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT5 | input | CELL[44].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT6 | input | CELL[44].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT7 | input | CELL[44].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT8 | input | CELL[44].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT9 | input | CELL[44].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP0 | input | CELL[55].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP1 | input | CELL[55].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP10 | input | CELL[55].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP11 | input | CELL[55].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP12 | input | CELL[55].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP13 | input | CELL[55].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP14 | input | CELL[55].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP15 | input | CELL[55].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP16 | input | CELL[56].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP17 | input | CELL[56].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP18 | input | CELL[56].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP19 | input | CELL[56].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP2 | input | CELL[55].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP20 | input | CELL[56].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP21 | input | CELL[56].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP22 | input | CELL[56].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP23 | input | CELL[56].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP24 | input | CELL[56].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP25 | input | CELL[56].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP26 | input | CELL[56].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP27 | input | CELL[56].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP28 | input | CELL[56].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP29 | input | CELL[56].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP3 | input | CELL[55].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP30 | input | CELL[56].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP31 | input | CELL[56].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP4 | input | CELL[55].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP5 | input | CELL[55].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP6 | input | CELL[55].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP7 | input | CELL[55].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP8 | input | CELL[55].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP9 | input | CELL[55].IMUX_IMUX_DELAY[9] |
| ICAP_OUT_BOT0 | output | CELL[44].OUT_BEL[0] |
| ICAP_OUT_BOT1 | output | CELL[44].OUT_BEL[2] |
| ICAP_OUT_BOT10 | output | CELL[44].OUT_BEL[20] |
| ICAP_OUT_BOT11 | output | CELL[44].OUT_BEL[22] |
| ICAP_OUT_BOT12 | output | CELL[44].OUT_BEL[24] |
| ICAP_OUT_BOT13 | output | CELL[44].OUT_BEL[26] |
| ICAP_OUT_BOT14 | output | CELL[44].OUT_BEL[28] |
| ICAP_OUT_BOT15 | output | CELL[44].OUT_BEL[30] |
| ICAP_OUT_BOT16 | output | CELL[45].OUT_BEL[0] |
| ICAP_OUT_BOT17 | output | CELL[45].OUT_BEL[2] |
| ICAP_OUT_BOT18 | output | CELL[45].OUT_BEL[4] |
| ICAP_OUT_BOT19 | output | CELL[45].OUT_BEL[6] |
| ICAP_OUT_BOT2 | output | CELL[44].OUT_BEL[4] |
| ICAP_OUT_BOT20 | output | CELL[45].OUT_BEL[8] |
| ICAP_OUT_BOT21 | output | CELL[45].OUT_BEL[10] |
| ICAP_OUT_BOT22 | output | CELL[45].OUT_BEL[12] |
| ICAP_OUT_BOT23 | output | CELL[45].OUT_BEL[14] |
| ICAP_OUT_BOT24 | output | CELL[45].OUT_BEL[16] |
| ICAP_OUT_BOT25 | output | CELL[45].OUT_BEL[18] |
| ICAP_OUT_BOT26 | output | CELL[45].OUT_BEL[20] |
| ICAP_OUT_BOT27 | output | CELL[45].OUT_BEL[22] |
| ICAP_OUT_BOT28 | output | CELL[45].OUT_BEL[24] |
| ICAP_OUT_BOT29 | output | CELL[45].OUT_BEL[26] |
| ICAP_OUT_BOT3 | output | CELL[44].OUT_BEL[6] |
| ICAP_OUT_BOT30 | output | CELL[45].OUT_BEL[28] |
| ICAP_OUT_BOT31 | output | CELL[45].OUT_BEL[30] |
| ICAP_OUT_BOT4 | output | CELL[44].OUT_BEL[8] |
| ICAP_OUT_BOT5 | output | CELL[44].OUT_BEL[10] |
| ICAP_OUT_BOT6 | output | CELL[44].OUT_BEL[12] |
| ICAP_OUT_BOT7 | output | CELL[44].OUT_BEL[14] |
| ICAP_OUT_BOT8 | output | CELL[44].OUT_BEL[16] |
| ICAP_OUT_BOT9 | output | CELL[44].OUT_BEL[18] |
| ICAP_OUT_TOP0 | output | CELL[55].OUT_BEL[0] |
| ICAP_OUT_TOP1 | output | CELL[55].OUT_BEL[2] |
| ICAP_OUT_TOP10 | output | CELL[55].OUT_BEL[20] |
| ICAP_OUT_TOP11 | output | CELL[55].OUT_BEL[22] |
| ICAP_OUT_TOP12 | output | CELL[55].OUT_BEL[24] |
| ICAP_OUT_TOP13 | output | CELL[55].OUT_BEL[26] |
| ICAP_OUT_TOP14 | output | CELL[55].OUT_BEL[28] |
| ICAP_OUT_TOP15 | output | CELL[55].OUT_BEL[30] |
| ICAP_OUT_TOP16 | output | CELL[56].OUT_BEL[0] |
| ICAP_OUT_TOP17 | output | CELL[56].OUT_BEL[2] |
| ICAP_OUT_TOP18 | output | CELL[56].OUT_BEL[4] |
| ICAP_OUT_TOP19 | output | CELL[56].OUT_BEL[6] |
| ICAP_OUT_TOP2 | output | CELL[55].OUT_BEL[4] |
| ICAP_OUT_TOP20 | output | CELL[56].OUT_BEL[8] |
| ICAP_OUT_TOP21 | output | CELL[56].OUT_BEL[10] |
| ICAP_OUT_TOP22 | output | CELL[56].OUT_BEL[12] |
| ICAP_OUT_TOP23 | output | CELL[56].OUT_BEL[14] |
| ICAP_OUT_TOP24 | output | CELL[56].OUT_BEL[16] |
| ICAP_OUT_TOP25 | output | CELL[56].OUT_BEL[18] |
| ICAP_OUT_TOP26 | output | CELL[56].OUT_BEL[20] |
| ICAP_OUT_TOP27 | output | CELL[56].OUT_BEL[22] |
| ICAP_OUT_TOP28 | output | CELL[56].OUT_BEL[24] |
| ICAP_OUT_TOP29 | output | CELL[56].OUT_BEL[26] |
| ICAP_OUT_TOP3 | output | CELL[55].OUT_BEL[6] |
| ICAP_OUT_TOP30 | output | CELL[56].OUT_BEL[28] |
| ICAP_OUT_TOP31 | output | CELL[56].OUT_BEL[30] |
| ICAP_OUT_TOP4 | output | CELL[55].OUT_BEL[8] |
| ICAP_OUT_TOP5 | output | CELL[55].OUT_BEL[10] |
| ICAP_OUT_TOP6 | output | CELL[55].OUT_BEL[12] |
| ICAP_OUT_TOP7 | output | CELL[55].OUT_BEL[14] |
| ICAP_OUT_TOP8 | output | CELL[55].OUT_BEL[16] |
| ICAP_OUT_TOP9 | output | CELL[55].OUT_BEL[18] |
| ICAP_PR_DONE_BOT | output | CELL[43].OUT_BEL[0] |
| ICAP_PR_DONE_TOP | output | CELL[54].OUT_BEL[0] |
| ICAP_PR_ERROR_BOT | output | CELL[43].OUT_BEL[2] |
| ICAP_PR_ERROR_TOP | output | CELL[54].OUT_BEL[2] |
| ICAP_RDWR_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[0] |
| ICAP_RDWR_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[0] |
| IOX_CCLK | output | CELL[50].OUT_BEL[0] |
| IOX_CFGDATA0 | output | CELL[48].OUT_BEL[0] |
| IOX_CFGDATA1 | output | CELL[48].OUT_BEL[2] |
| IOX_CFGDATA10 | output | CELL[48].OUT_BEL[20] |
| IOX_CFGDATA11 | output | CELL[48].OUT_BEL[22] |
| IOX_CFGDATA12 | output | CELL[48].OUT_BEL[24] |
| IOX_CFGDATA13 | output | CELL[48].OUT_BEL[26] |
| IOX_CFGDATA14 | output | CELL[48].OUT_BEL[28] |
| IOX_CFGDATA15 | output | CELL[48].OUT_BEL[30] |
| IOX_CFGDATA16 | output | CELL[49].OUT_BEL[0] |
| IOX_CFGDATA17 | output | CELL[49].OUT_BEL[2] |
| IOX_CFGDATA18 | output | CELL[49].OUT_BEL[4] |
| IOX_CFGDATA19 | output | CELL[49].OUT_BEL[6] |
| IOX_CFGDATA2 | output | CELL[48].OUT_BEL[4] |
| IOX_CFGDATA20 | output | CELL[49].OUT_BEL[8] |
| IOX_CFGDATA21 | output | CELL[49].OUT_BEL[10] |
| IOX_CFGDATA22 | output | CELL[49].OUT_BEL[12] |
| IOX_CFGDATA23 | output | CELL[49].OUT_BEL[14] |
| IOX_CFGDATA24 | output | CELL[49].OUT_BEL[16] |
| IOX_CFGDATA25 | output | CELL[49].OUT_BEL[18] |
| IOX_CFGDATA26 | output | CELL[49].OUT_BEL[20] |
| IOX_CFGDATA27 | output | CELL[49].OUT_BEL[22] |
| IOX_CFGDATA28 | output | CELL[49].OUT_BEL[24] |
| IOX_CFGDATA29 | output | CELL[49].OUT_BEL[26] |
| IOX_CFGDATA3 | output | CELL[48].OUT_BEL[6] |
| IOX_CFGDATA30 | output | CELL[49].OUT_BEL[28] |
| IOX_CFGDATA31 | output | CELL[49].OUT_BEL[30] |
| IOX_CFGDATA4 | output | CELL[48].OUT_BEL[8] |
| IOX_CFGDATA5 | output | CELL[48].OUT_BEL[10] |
| IOX_CFGDATA6 | output | CELL[48].OUT_BEL[12] |
| IOX_CFGDATA7 | output | CELL[48].OUT_BEL[14] |
| IOX_CFGDATA8 | output | CELL[48].OUT_BEL[16] |
| IOX_CFGDATA9 | output | CELL[48].OUT_BEL[18] |
| IOX_CFGMASTER | output | CELL[50].OUT_BEL[2] |
| IOX_INITBI | output | CELL[50].OUT_BEL[6] |
| IOX_INITBO | input | CELL[48].IMUX_IMUX_DELAY[1] |
| IOX_MODE0 | output | CELL[50].OUT_BEL[12] |
| IOX_MODE1 | output | CELL[50].OUT_BEL[14] |
| IOX_MODE2 | output | CELL[50].OUT_BEL[16] |
| IOX_PUDCB | output | CELL[50].OUT_BEL[8] |
| IOX_RDWRB | output | CELL[50].OUT_BEL[10] |
| IOX_TDO | input | CELL[48].IMUX_IMUX_DELAY[0] |
| IOX_VGG_COMP_OUT | output | CELL[50].OUT_BEL[4] |
| KEY_CLEAR_B | input | CELL[47].IMUX_IMUX_DELAY[0] |
| PROG_ACK | input | CELL[47].IMUX_IMUX_DELAY[1] |
| PROG_REQ | output | CELL[47].OUT_BEL[8] |
| RBCRC_ERROR | output | CELL[51].OUT_BEL[20] |
| RDATA0 | output | CELL[31].OUT_BEL[24] |
| RDATA1 | output | CELL[31].OUT_BEL[26] |
| RDATA10 | output | CELL[32].OUT_BEL[12] |
| RDATA11 | output | CELL[32].OUT_BEL[14] |
| RDATA12 | output | CELL[32].OUT_BEL[16] |
| RDATA13 | output | CELL[32].OUT_BEL[18] |
| RDATA14 | output | CELL[32].OUT_BEL[20] |
| RDATA15 | output | CELL[32].OUT_BEL[22] |
| RDATA16 | output | CELL[32].OUT_BEL[24] |
| RDATA17 | output | CELL[32].OUT_BEL[26] |
| RDATA18 | output | CELL[32].OUT_BEL[28] |
| RDATA19 | output | CELL[32].OUT_BEL[30] |
| RDATA2 | output | CELL[31].OUT_BEL[28] |
| RDATA20 | output | CELL[33].OUT_BEL[0] |
| RDATA21 | output | CELL[33].OUT_BEL[2] |
| RDATA22 | output | CELL[33].OUT_BEL[4] |
| RDATA23 | output | CELL[33].OUT_BEL[6] |
| RDATA24 | output | CELL[33].OUT_BEL[8] |
| RDATA25 | output | CELL[33].OUT_BEL[10] |
| RDATA26 | output | CELL[33].OUT_BEL[12] |
| RDATA27 | output | CELL[33].OUT_BEL[14] |
| RDATA28 | output | CELL[33].OUT_BEL[16] |
| RDATA29 | output | CELL[33].OUT_BEL[18] |
| RDATA3 | output | CELL[31].OUT_BEL[30] |
| RDATA30 | output | CELL[33].OUT_BEL[20] |
| RDATA31 | output | CELL[33].OUT_BEL[22] |
| RDATA4 | output | CELL[32].OUT_BEL[0] |
| RDATA5 | output | CELL[32].OUT_BEL[2] |
| RDATA6 | output | CELL[32].OUT_BEL[4] |
| RDATA7 | output | CELL[32].OUT_BEL[6] |
| RDATA8 | output | CELL[32].OUT_BEL[8] |
| RDATA9 | output | CELL[32].OUT_BEL[10] |
| RID0 | output | CELL[31].OUT_BEL[4] |
| RID1 | output | CELL[31].OUT_BEL[6] |
| RID2 | output | CELL[31].OUT_BEL[8] |
| RID3 | output | CELL[31].OUT_BEL[10] |
| RID4 | output | CELL[31].OUT_BEL[12] |
| RID5 | output | CELL[31].OUT_BEL[14] |
| RID6 | output | CELL[31].OUT_BEL[16] |
| RID7 | output | CELL[31].OUT_BEL[18] |
| RLAST | output | CELL[31].OUT_BEL[2] |
| RREADY | input | CELL[31].IMUX_IMUX_DELAY[0] |
| RRESP0 | output | CELL[31].OUT_BEL[20] |
| RRESP1 | output | CELL[31].OUT_BEL[22] |
| RVALID | output | CELL[31].OUT_BEL[0] |
| START_CFG_CLK | output | CELL[47].OUT_BEL[14] |
| START_CFG_MCLK | output | CELL[47].OUT_BEL[12] |
| USR_ACCESS_CLK | output | CELL[57].OUT_BEL[2] |
| USR_ACCESS_DATA0 | output | CELL[58].OUT_BEL[0] |
| USR_ACCESS_DATA1 | output | CELL[58].OUT_BEL[2] |
| USR_ACCESS_DATA10 | output | CELL[58].OUT_BEL[20] |
| USR_ACCESS_DATA11 | output | CELL[58].OUT_BEL[22] |
| USR_ACCESS_DATA12 | output | CELL[58].OUT_BEL[24] |
| USR_ACCESS_DATA13 | output | CELL[58].OUT_BEL[26] |
| USR_ACCESS_DATA14 | output | CELL[58].OUT_BEL[28] |
| USR_ACCESS_DATA15 | output | CELL[58].OUT_BEL[30] |
| USR_ACCESS_DATA16 | output | CELL[59].OUT_BEL[0] |
| USR_ACCESS_DATA17 | output | CELL[59].OUT_BEL[2] |
| USR_ACCESS_DATA18 | output | CELL[59].OUT_BEL[4] |
| USR_ACCESS_DATA19 | output | CELL[59].OUT_BEL[6] |
| USR_ACCESS_DATA2 | output | CELL[58].OUT_BEL[4] |
| USR_ACCESS_DATA20 | output | CELL[59].OUT_BEL[8] |
| USR_ACCESS_DATA21 | output | CELL[59].OUT_BEL[10] |
| USR_ACCESS_DATA22 | output | CELL[59].OUT_BEL[12] |
| USR_ACCESS_DATA23 | output | CELL[59].OUT_BEL[14] |
| USR_ACCESS_DATA24 | output | CELL[59].OUT_BEL[16] |
| USR_ACCESS_DATA25 | output | CELL[59].OUT_BEL[18] |
| USR_ACCESS_DATA26 | output | CELL[59].OUT_BEL[20] |
| USR_ACCESS_DATA27 | output | CELL[59].OUT_BEL[22] |
| USR_ACCESS_DATA28 | output | CELL[59].OUT_BEL[24] |
| USR_ACCESS_DATA29 | output | CELL[59].OUT_BEL[26] |
| USR_ACCESS_DATA3 | output | CELL[58].OUT_BEL[6] |
| USR_ACCESS_DATA30 | output | CELL[59].OUT_BEL[28] |
| USR_ACCESS_DATA31 | output | CELL[59].OUT_BEL[30] |
| USR_ACCESS_DATA4 | output | CELL[58].OUT_BEL[8] |
| USR_ACCESS_DATA5 | output | CELL[58].OUT_BEL[10] |
| USR_ACCESS_DATA6 | output | CELL[58].OUT_BEL[12] |
| USR_ACCESS_DATA7 | output | CELL[58].OUT_BEL[14] |
| USR_ACCESS_DATA8 | output | CELL[58].OUT_BEL[16] |
| USR_ACCESS_DATA9 | output | CELL[58].OUT_BEL[18] |
| USR_ACCESS_VALID | output | CELL[57].OUT_BEL[0] |
| USR_CCLK_O | input | CELL[47].IMUX_CTRL[0] |
| USR_CCLK_TS | input | CELL[47].IMUX_IMUX_DELAY[2] |
| USR_DNA_CLK | input | CELL[42].IMUX_CTRL[0] |
| USR_DNA_DIN | input | CELL[42].IMUX_IMUX_DELAY[0] |
| USR_DNA_OUT | output | CELL[42].OUT_BEL[0] |
| USR_DNA_READ | input | CELL[42].IMUX_IMUX_DELAY[1] |
| USR_DNA_SHIFT | input | CELL[42].IMUX_IMUX_DELAY[2] |
| USR_DONE_O | input | CELL[47].IMUX_IMUX_DELAY[3] |
| USR_DONE_TS | input | CELL[47].IMUX_IMUX_DELAY[4] |
| USR_D_O_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[9] |
| USR_D_O_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[10] |
| USR_D_O_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[11] |
| USR_D_O_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[12] |
| USR_D_PIN_CFGIO0 | output | CELL[47].OUT_BEL[0] |
| USR_D_PIN_CFGIO1 | output | CELL[47].OUT_BEL[2] |
| USR_D_PIN_CFGIO2 | output | CELL[47].OUT_BEL[4] |
| USR_D_PIN_CFGIO3 | output | CELL[47].OUT_BEL[6] |
| USR_D_TS_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[13] |
| USR_D_TS_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[14] |
| USR_D_TS_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[15] |
| USR_D_TS_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[16] |
| USR_EFUSE0 | output | CELL[46].OUT_BEL[0] |
| USR_EFUSE1 | output | CELL[46].OUT_BEL[2] |
| USR_EFUSE10 | output | CELL[46].OUT_BEL[20] |
| USR_EFUSE11 | output | CELL[46].OUT_BEL[22] |
| USR_EFUSE12 | output | CELL[46].OUT_BEL[24] |
| USR_EFUSE13 | output | CELL[46].OUT_BEL[26] |
| USR_EFUSE14 | output | CELL[46].OUT_BEL[28] |
| USR_EFUSE15 | output | CELL[46].OUT_BEL[30] |
| USR_EFUSE16 | output | CELL[41].OUT_BEL[0] |
| USR_EFUSE17 | output | CELL[41].OUT_BEL[2] |
| USR_EFUSE18 | output | CELL[41].OUT_BEL[4] |
| USR_EFUSE19 | output | CELL[41].OUT_BEL[6] |
| USR_EFUSE2 | output | CELL[46].OUT_BEL[4] |
| USR_EFUSE20 | output | CELL[41].OUT_BEL[8] |
| USR_EFUSE21 | output | CELL[41].OUT_BEL[10] |
| USR_EFUSE22 | output | CELL[41].OUT_BEL[12] |
| USR_EFUSE23 | output | CELL[41].OUT_BEL[14] |
| USR_EFUSE24 | output | CELL[41].OUT_BEL[16] |
| USR_EFUSE25 | output | CELL[41].OUT_BEL[18] |
| USR_EFUSE26 | output | CELL[41].OUT_BEL[20] |
| USR_EFUSE27 | output | CELL[41].OUT_BEL[22] |
| USR_EFUSE28 | output | CELL[41].OUT_BEL[24] |
| USR_EFUSE29 | output | CELL[41].OUT_BEL[26] |
| USR_EFUSE3 | output | CELL[46].OUT_BEL[6] |
| USR_EFUSE30 | output | CELL[41].OUT_BEL[28] |
| USR_EFUSE31 | output | CELL[41].OUT_BEL[30] |
| USR_EFUSE4 | output | CELL[46].OUT_BEL[8] |
| USR_EFUSE5 | output | CELL[46].OUT_BEL[10] |
| USR_EFUSE6 | output | CELL[46].OUT_BEL[12] |
| USR_EFUSE7 | output | CELL[46].OUT_BEL[14] |
| USR_EFUSE8 | output | CELL[46].OUT_BEL[16] |
| USR_EFUSE9 | output | CELL[46].OUT_BEL[18] |
| USR_FCS_B_O | input | CELL[47].IMUX_IMUX_DELAY[7] |
| USR_FCS_B_TS | input | CELL[47].IMUX_IMUX_DELAY[8] |
| USR_GSR | input | CELL[47].IMUX_IMUX_DELAY[5] |
| USR_GTS | input | CELL[47].IMUX_IMUX_DELAY[6] |
| USR_TCK | input | CELL[43].IMUX_CTRL[1] |
| USR_TDI | input | CELL[43].IMUX_IMUX_DELAY[6] |
| USR_TDO | output | CELL[43].OUT_BEL[18] |
| USR_TMS | input | CELL[43].IMUX_IMUX_DELAY[5] |
| WDATA0 | input | CELL[28].IMUX_IMUX_DELAY[10] |
| WDATA1 | input | CELL[28].IMUX_IMUX_DELAY[11] |
| WDATA10 | input | CELL[29].IMUX_IMUX_DELAY[4] |
| WDATA11 | input | CELL[29].IMUX_IMUX_DELAY[5] |
| WDATA12 | input | CELL[29].IMUX_IMUX_DELAY[6] |
| WDATA13 | input | CELL[29].IMUX_IMUX_DELAY[7] |
| WDATA14 | input | CELL[29].IMUX_IMUX_DELAY[8] |
| WDATA15 | input | CELL[29].IMUX_IMUX_DELAY[9] |
| WDATA16 | input | CELL[29].IMUX_IMUX_DELAY[10] |
| WDATA17 | input | CELL[29].IMUX_IMUX_DELAY[11] |
| WDATA18 | input | CELL[29].IMUX_IMUX_DELAY[12] |
| WDATA19 | input | CELL[29].IMUX_IMUX_DELAY[13] |
| WDATA2 | input | CELL[28].IMUX_IMUX_DELAY[12] |
| WDATA20 | input | CELL[29].IMUX_IMUX_DELAY[14] |
| WDATA21 | input | CELL[29].IMUX_IMUX_DELAY[15] |
| WDATA22 | input | CELL[30].IMUX_IMUX_DELAY[0] |
| WDATA23 | input | CELL[30].IMUX_IMUX_DELAY[1] |
| WDATA24 | input | CELL[30].IMUX_IMUX_DELAY[2] |
| WDATA25 | input | CELL[30].IMUX_IMUX_DELAY[3] |
| WDATA26 | input | CELL[30].IMUX_IMUX_DELAY[4] |
| WDATA27 | input | CELL[30].IMUX_IMUX_DELAY[5] |
| WDATA28 | input | CELL[30].IMUX_IMUX_DELAY[6] |
| WDATA29 | input | CELL[30].IMUX_IMUX_DELAY[7] |
| WDATA3 | input | CELL[28].IMUX_IMUX_DELAY[13] |
| WDATA30 | input | CELL[30].IMUX_IMUX_DELAY[8] |
| WDATA31 | input | CELL[30].IMUX_IMUX_DELAY[9] |
| WDATA4 | input | CELL[28].IMUX_IMUX_DELAY[14] |
| WDATA5 | input | CELL[28].IMUX_IMUX_DELAY[15] |
| WDATA6 | input | CELL[29].IMUX_IMUX_DELAY[0] |
| WDATA7 | input | CELL[29].IMUX_IMUX_DELAY[1] |
| WDATA8 | input | CELL[29].IMUX_IMUX_DELAY[2] |
| WDATA9 | input | CELL[29].IMUX_IMUX_DELAY[3] |
| WID0 | input | CELL[28].IMUX_IMUX_DELAY[2] |
| WID1 | input | CELL[28].IMUX_IMUX_DELAY[3] |
| WID2 | input | CELL[28].IMUX_IMUX_DELAY[4] |
| WID3 | input | CELL[28].IMUX_IMUX_DELAY[5] |
| WID4 | input | CELL[28].IMUX_IMUX_DELAY[6] |
| WID5 | input | CELL[28].IMUX_IMUX_DELAY[7] |
| WID6 | input | CELL[28].IMUX_IMUX_DELAY[8] |
| WID7 | input | CELL[28].IMUX_IMUX_DELAY[9] |
| WLAST | input | CELL[28].IMUX_IMUX_DELAY[1] |
| WREADY | output | CELL[28].OUT_BEL[0] |
| WSTRB0 | input | CELL[30].IMUX_IMUX_DELAY[10] |
| WSTRB1 | input | CELL[30].IMUX_IMUX_DELAY[11] |
| WSTRB2 | input | CELL[30].IMUX_IMUX_DELAY[12] |
| WSTRB3 | input | CELL[30].IMUX_IMUX_DELAY[13] |
| WVALID | input | CELL[28].IMUX_IMUX_DELAY[0] |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| CELL[20].OUT_BEL[0] | CFG.ARREADY |
| CELL[20].IMUX_CTRL[0] | CFG.AXI_CLK |
| CELL[20].IMUX_IMUX_DELAY[0] | CFG.ARVALID |
| CELL[20].IMUX_IMUX_DELAY[3] | CFG.ARADDR22 |
| CELL[20].IMUX_IMUX_DELAY[4] | CFG.ARADDR23 |
| CELL[20].IMUX_IMUX_DELAY[5] | CFG.ARADDR24 |
| CELL[20].IMUX_IMUX_DELAY[6] | CFG.ARADDR25 |
| CELL[20].IMUX_IMUX_DELAY[7] | CFG.ARADDR26 |
| CELL[20].IMUX_IMUX_DELAY[8] | CFG.ARADDR27 |
| CELL[20].IMUX_IMUX_DELAY[9] | CFG.ARADDR0 |
| CELL[20].IMUX_IMUX_DELAY[10] | CFG.ARADDR1 |
| CELL[20].IMUX_IMUX_DELAY[11] | CFG.ARADDR2 |
| CELL[20].IMUX_IMUX_DELAY[12] | CFG.ARADDR3 |
| CELL[20].IMUX_IMUX_DELAY[13] | CFG.ARADDR4 |
| CELL[20].IMUX_IMUX_DELAY[14] | CFG.ARADDR5 |
| CELL[20].IMUX_IMUX_DELAY[15] | CFG.ARADDR6 |
| CELL[21].IMUX_IMUX_DELAY[0] | CFG.ARADDR7 |
| CELL[21].IMUX_IMUX_DELAY[1] | CFG.ARADDR8 |
| CELL[21].IMUX_IMUX_DELAY[2] | CFG.ARADDR9 |
| CELL[21].IMUX_IMUX_DELAY[3] | CFG.ARADDR10 |
| CELL[21].IMUX_IMUX_DELAY[4] | CFG.ARADDR11 |
| CELL[21].IMUX_IMUX_DELAY[5] | CFG.ARADDR12 |
| CELL[21].IMUX_IMUX_DELAY[6] | CFG.ARADDR13 |
| CELL[21].IMUX_IMUX_DELAY[7] | CFG.ARADDR14 |
| CELL[21].IMUX_IMUX_DELAY[8] | CFG.ARADDR15 |
| CELL[21].IMUX_IMUX_DELAY[9] | CFG.ARADDR16 |
| CELL[21].IMUX_IMUX_DELAY[10] | CFG.ARADDR17 |
| CELL[21].IMUX_IMUX_DELAY[11] | CFG.ARADDR18 |
| CELL[21].IMUX_IMUX_DELAY[12] | CFG.ARADDR19 |
| CELL[21].IMUX_IMUX_DELAY[13] | CFG.ARADDR20 |
| CELL[21].IMUX_IMUX_DELAY[14] | CFG.ARADDR21 |
| CELL[21].IMUX_IMUX_DELAY[15] | CFG.ARLEN0 |
| CELL[22].IMUX_IMUX_DELAY[0] | CFG.ARLEN1 |
| CELL[22].IMUX_IMUX_DELAY[1] | CFG.ARLEN2 |
| CELL[22].IMUX_IMUX_DELAY[2] | CFG.ARLEN3 |
| CELL[22].IMUX_IMUX_DELAY[3] | CFG.ARSIZE0 |
| CELL[22].IMUX_IMUX_DELAY[4] | CFG.ARSIZE1 |
| CELL[22].IMUX_IMUX_DELAY[5] | CFG.ARSIZE2 |
| CELL[22].IMUX_IMUX_DELAY[6] | CFG.ARBURST0 |
| CELL[22].IMUX_IMUX_DELAY[7] | CFG.ARBURST1 |
| CELL[22].IMUX_IMUX_DELAY[8] | CFG.ARLOCK |
| CELL[22].IMUX_IMUX_DELAY[9] | CFG.ARCACHE0 |
| CELL[22].IMUX_IMUX_DELAY[10] | CFG.ARCACHE1 |
| CELL[22].IMUX_IMUX_DELAY[11] | CFG.ARCACHE2 |
| CELL[22].IMUX_IMUX_DELAY[12] | CFG.ARCACHE3 |
| CELL[22].IMUX_IMUX_DELAY[13] | CFG.ARPROT0 |
| CELL[22].IMUX_IMUX_DELAY[14] | CFG.ARPROT1 |
| CELL[22].IMUX_IMUX_DELAY[15] | CFG.ARPROT2 |
| CELL[23].IMUX_IMUX_DELAY[0] | CFG.ARQOS0 |
| CELL[23].IMUX_IMUX_DELAY[1] | CFG.ARQOS1 |
| CELL[23].IMUX_IMUX_DELAY[2] | CFG.ARQOS2 |
| CELL[23].IMUX_IMUX_DELAY[3] | CFG.ARQOS3 |
| CELL[24].OUT_BEL[0] | CFG.AWREADY |
| CELL[24].IMUX_IMUX_DELAY[0] | CFG.AWVALID |
| CELL[24].IMUX_IMUX_DELAY[3] | CFG.AWADDR22 |
| CELL[24].IMUX_IMUX_DELAY[4] | CFG.AWADDR23 |
| CELL[24].IMUX_IMUX_DELAY[5] | CFG.AWADDR24 |
| CELL[24].IMUX_IMUX_DELAY[6] | CFG.AWADDR25 |
| CELL[24].IMUX_IMUX_DELAY[7] | CFG.AWADDR26 |
| CELL[24].IMUX_IMUX_DELAY[8] | CFG.AWADDR27 |
| CELL[24].IMUX_IMUX_DELAY[9] | CFG.AWADDR0 |
| CELL[24].IMUX_IMUX_DELAY[10] | CFG.AWADDR1 |
| CELL[24].IMUX_IMUX_DELAY[11] | CFG.AWADDR2 |
| CELL[24].IMUX_IMUX_DELAY[12] | CFG.AWADDR3 |
| CELL[24].IMUX_IMUX_DELAY[13] | CFG.AWADDR4 |
| CELL[24].IMUX_IMUX_DELAY[14] | CFG.AWADDR5 |
| CELL[24].IMUX_IMUX_DELAY[15] | CFG.AWADDR6 |
| CELL[25].IMUX_IMUX_DELAY[0] | CFG.AWADDR7 |
| CELL[25].IMUX_IMUX_DELAY[1] | CFG.AWADDR8 |
| CELL[25].IMUX_IMUX_DELAY[2] | CFG.AWADDR9 |
| CELL[25].IMUX_IMUX_DELAY[3] | CFG.AWADDR10 |
| CELL[25].IMUX_IMUX_DELAY[4] | CFG.AWADDR11 |
| CELL[25].IMUX_IMUX_DELAY[5] | CFG.AWADDR12 |
| CELL[25].IMUX_IMUX_DELAY[6] | CFG.AWADDR13 |
| CELL[25].IMUX_IMUX_DELAY[7] | CFG.AWADDR14 |
| CELL[25].IMUX_IMUX_DELAY[8] | CFG.AWADDR15 |
| CELL[25].IMUX_IMUX_DELAY[9] | CFG.AWADDR16 |
| CELL[25].IMUX_IMUX_DELAY[10] | CFG.AWADDR17 |
| CELL[25].IMUX_IMUX_DELAY[11] | CFG.AWADDR18 |
| CELL[25].IMUX_IMUX_DELAY[12] | CFG.AWADDR19 |
| CELL[25].IMUX_IMUX_DELAY[13] | CFG.AWADDR20 |
| CELL[25].IMUX_IMUX_DELAY[14] | CFG.AWADDR21 |
| CELL[25].IMUX_IMUX_DELAY[15] | CFG.AWLEN0 |
| CELL[26].IMUX_IMUX_DELAY[0] | CFG.AWLEN1 |
| CELL[26].IMUX_IMUX_DELAY[1] | CFG.AWLEN2 |
| CELL[26].IMUX_IMUX_DELAY[2] | CFG.AWLEN3 |
| CELL[26].IMUX_IMUX_DELAY[3] | CFG.AWSIZE0 |
| CELL[26].IMUX_IMUX_DELAY[4] | CFG.AWSIZE1 |
| CELL[26].IMUX_IMUX_DELAY[5] | CFG.AWSIZE2 |
| CELL[26].IMUX_IMUX_DELAY[6] | CFG.AWBURST0 |
| CELL[26].IMUX_IMUX_DELAY[7] | CFG.AWBURST1 |
| CELL[26].IMUX_IMUX_DELAY[8] | CFG.AWLOCK |
| CELL[26].IMUX_IMUX_DELAY[9] | CFG.AWCACHE0 |
| CELL[26].IMUX_IMUX_DELAY[10] | CFG.AWCACHE1 |
| CELL[26].IMUX_IMUX_DELAY[11] | CFG.AWCACHE2 |
| CELL[26].IMUX_IMUX_DELAY[12] | CFG.AWCACHE3 |
| CELL[26].IMUX_IMUX_DELAY[13] | CFG.AWPROT0 |
| CELL[26].IMUX_IMUX_DELAY[14] | CFG.AWPROT1 |
| CELL[26].IMUX_IMUX_DELAY[15] | CFG.AWPROT2 |
| CELL[27].IMUX_IMUX_DELAY[0] | CFG.AWQOS0 |
| CELL[27].IMUX_IMUX_DELAY[1] | CFG.AWQOS1 |
| CELL[27].IMUX_IMUX_DELAY[2] | CFG.AWQOS2 |
| CELL[27].IMUX_IMUX_DELAY[3] | CFG.AWQOS3 |
| CELL[28].OUT_BEL[0] | CFG.WREADY |
| CELL[28].IMUX_IMUX_DELAY[0] | CFG.WVALID |
| CELL[28].IMUX_IMUX_DELAY[1] | CFG.WLAST |
| CELL[28].IMUX_IMUX_DELAY[2] | CFG.WID0 |
| CELL[28].IMUX_IMUX_DELAY[3] | CFG.WID1 |
| CELL[28].IMUX_IMUX_DELAY[4] | CFG.WID2 |
| CELL[28].IMUX_IMUX_DELAY[5] | CFG.WID3 |
| CELL[28].IMUX_IMUX_DELAY[6] | CFG.WID4 |
| CELL[28].IMUX_IMUX_DELAY[7] | CFG.WID5 |
| CELL[28].IMUX_IMUX_DELAY[8] | CFG.WID6 |
| CELL[28].IMUX_IMUX_DELAY[9] | CFG.WID7 |
| CELL[28].IMUX_IMUX_DELAY[10] | CFG.WDATA0 |
| CELL[28].IMUX_IMUX_DELAY[11] | CFG.WDATA1 |
| CELL[28].IMUX_IMUX_DELAY[12] | CFG.WDATA2 |
| CELL[28].IMUX_IMUX_DELAY[13] | CFG.WDATA3 |
| CELL[28].IMUX_IMUX_DELAY[14] | CFG.WDATA4 |
| CELL[28].IMUX_IMUX_DELAY[15] | CFG.WDATA5 |
| CELL[29].IMUX_IMUX_DELAY[0] | CFG.WDATA6 |
| CELL[29].IMUX_IMUX_DELAY[1] | CFG.WDATA7 |
| CELL[29].IMUX_IMUX_DELAY[2] | CFG.WDATA8 |
| CELL[29].IMUX_IMUX_DELAY[3] | CFG.WDATA9 |
| CELL[29].IMUX_IMUX_DELAY[4] | CFG.WDATA10 |
| CELL[29].IMUX_IMUX_DELAY[5] | CFG.WDATA11 |
| CELL[29].IMUX_IMUX_DELAY[6] | CFG.WDATA12 |
| CELL[29].IMUX_IMUX_DELAY[7] | CFG.WDATA13 |
| CELL[29].IMUX_IMUX_DELAY[8] | CFG.WDATA14 |
| CELL[29].IMUX_IMUX_DELAY[9] | CFG.WDATA15 |
| CELL[29].IMUX_IMUX_DELAY[10] | CFG.WDATA16 |
| CELL[29].IMUX_IMUX_DELAY[11] | CFG.WDATA17 |
| CELL[29].IMUX_IMUX_DELAY[12] | CFG.WDATA18 |
| CELL[29].IMUX_IMUX_DELAY[13] | CFG.WDATA19 |
| CELL[29].IMUX_IMUX_DELAY[14] | CFG.WDATA20 |
| CELL[29].IMUX_IMUX_DELAY[15] | CFG.WDATA21 |
| CELL[30].IMUX_IMUX_DELAY[0] | CFG.WDATA22 |
| CELL[30].IMUX_IMUX_DELAY[1] | CFG.WDATA23 |
| CELL[30].IMUX_IMUX_DELAY[2] | CFG.WDATA24 |
| CELL[30].IMUX_IMUX_DELAY[3] | CFG.WDATA25 |
| CELL[30].IMUX_IMUX_DELAY[4] | CFG.WDATA26 |
| CELL[30].IMUX_IMUX_DELAY[5] | CFG.WDATA27 |
| CELL[30].IMUX_IMUX_DELAY[6] | CFG.WDATA28 |
| CELL[30].IMUX_IMUX_DELAY[7] | CFG.WDATA29 |
| CELL[30].IMUX_IMUX_DELAY[8] | CFG.WDATA30 |
| CELL[30].IMUX_IMUX_DELAY[9] | CFG.WDATA31 |
| CELL[30].IMUX_IMUX_DELAY[10] | CFG.WSTRB0 |
| CELL[30].IMUX_IMUX_DELAY[11] | CFG.WSTRB1 |
| CELL[30].IMUX_IMUX_DELAY[12] | CFG.WSTRB2 |
| CELL[30].IMUX_IMUX_DELAY[13] | CFG.WSTRB3 |
| CELL[31].OUT_BEL[0] | CFG.RVALID |
| CELL[31].OUT_BEL[2] | CFG.RLAST |
| CELL[31].OUT_BEL[4] | CFG.RID0 |
| CELL[31].OUT_BEL[6] | CFG.RID1 |
| CELL[31].OUT_BEL[8] | CFG.RID2 |
| CELL[31].OUT_BEL[10] | CFG.RID3 |
| CELL[31].OUT_BEL[12] | CFG.RID4 |
| CELL[31].OUT_BEL[14] | CFG.RID5 |
| CELL[31].OUT_BEL[16] | CFG.RID6 |
| CELL[31].OUT_BEL[18] | CFG.RID7 |
| CELL[31].OUT_BEL[20] | CFG.RRESP0 |
| CELL[31].OUT_BEL[22] | CFG.RRESP1 |
| CELL[31].OUT_BEL[24] | CFG.RDATA0 |
| CELL[31].OUT_BEL[26] | CFG.RDATA1 |
| CELL[31].OUT_BEL[28] | CFG.RDATA2 |
| CELL[31].OUT_BEL[30] | CFG.RDATA3 |
| CELL[31].IMUX_IMUX_DELAY[0] | CFG.RREADY |
| CELL[31].IMUX_IMUX_DELAY[1] | CFG.ARID0 |
| CELL[31].IMUX_IMUX_DELAY[2] | CFG.ARID1 |
| CELL[31].IMUX_IMUX_DELAY[3] | CFG.ARID2 |
| CELL[31].IMUX_IMUX_DELAY[4] | CFG.ARID3 |
| CELL[31].IMUX_IMUX_DELAY[5] | CFG.ARID4 |
| CELL[31].IMUX_IMUX_DELAY[6] | CFG.ARID5 |
| CELL[31].IMUX_IMUX_DELAY[7] | CFG.ARID6 |
| CELL[31].IMUX_IMUX_DELAY[8] | CFG.ARID7 |
| CELL[32].OUT_BEL[0] | CFG.RDATA4 |
| CELL[32].OUT_BEL[2] | CFG.RDATA5 |
| CELL[32].OUT_BEL[4] | CFG.RDATA6 |
| CELL[32].OUT_BEL[6] | CFG.RDATA7 |
| CELL[32].OUT_BEL[8] | CFG.RDATA8 |
| CELL[32].OUT_BEL[10] | CFG.RDATA9 |
| CELL[32].OUT_BEL[12] | CFG.RDATA10 |
| CELL[32].OUT_BEL[14] | CFG.RDATA11 |
| CELL[32].OUT_BEL[16] | CFG.RDATA12 |
| CELL[32].OUT_BEL[18] | CFG.RDATA13 |
| CELL[32].OUT_BEL[20] | CFG.RDATA14 |
| CELL[32].OUT_BEL[22] | CFG.RDATA15 |
| CELL[32].OUT_BEL[24] | CFG.RDATA16 |
| CELL[32].OUT_BEL[26] | CFG.RDATA17 |
| CELL[32].OUT_BEL[28] | CFG.RDATA18 |
| CELL[32].OUT_BEL[30] | CFG.RDATA19 |
| CELL[32].IMUX_IMUX_DELAY[1] | CFG.AWID0 |
| CELL[32].IMUX_IMUX_DELAY[2] | CFG.AWID1 |
| CELL[32].IMUX_IMUX_DELAY[3] | CFG.AWID2 |
| CELL[32].IMUX_IMUX_DELAY[4] | CFG.AWID3 |
| CELL[32].IMUX_IMUX_DELAY[5] | CFG.AWID4 |
| CELL[32].IMUX_IMUX_DELAY[6] | CFG.AWID5 |
| CELL[32].IMUX_IMUX_DELAY[7] | CFG.AWID6 |
| CELL[32].IMUX_IMUX_DELAY[8] | CFG.AWID7 |
| CELL[33].OUT_BEL[0] | CFG.RDATA20 |
| CELL[33].OUT_BEL[2] | CFG.RDATA21 |
| CELL[33].OUT_BEL[4] | CFG.RDATA22 |
| CELL[33].OUT_BEL[6] | CFG.RDATA23 |
| CELL[33].OUT_BEL[8] | CFG.RDATA24 |
| CELL[33].OUT_BEL[10] | CFG.RDATA25 |
| CELL[33].OUT_BEL[12] | CFG.RDATA26 |
| CELL[33].OUT_BEL[14] | CFG.RDATA27 |
| CELL[33].OUT_BEL[16] | CFG.RDATA28 |
| CELL[33].OUT_BEL[18] | CFG.RDATA29 |
| CELL[33].OUT_BEL[20] | CFG.RDATA30 |
| CELL[33].OUT_BEL[22] | CFG.RDATA31 |
| CELL[34].OUT_BEL[0] | CFG.BVALID |
| CELL[34].OUT_BEL[2] | CFG.BID0 |
| CELL[34].OUT_BEL[4] | CFG.BID1 |
| CELL[34].OUT_BEL[6] | CFG.BID2 |
| CELL[34].OUT_BEL[8] | CFG.BID3 |
| CELL[34].OUT_BEL[10] | CFG.BID4 |
| CELL[34].OUT_BEL[12] | CFG.BID5 |
| CELL[34].OUT_BEL[14] | CFG.BID6 |
| CELL[34].OUT_BEL[16] | CFG.BID7 |
| CELL[34].OUT_BEL[18] | CFG.BRESP0 |
| CELL[34].OUT_BEL[20] | CFG.BRESP1 |
| CELL[34].IMUX_IMUX_DELAY[0] | CFG.BREADY |
| CELL[41].OUT_BEL[0] | CFG.USR_EFUSE16 |
| CELL[41].OUT_BEL[2] | CFG.USR_EFUSE17 |
| CELL[41].OUT_BEL[4] | CFG.USR_EFUSE18 |
| CELL[41].OUT_BEL[6] | CFG.USR_EFUSE19 |
| CELL[41].OUT_BEL[8] | CFG.USR_EFUSE20 |
| CELL[41].OUT_BEL[10] | CFG.USR_EFUSE21 |
| CELL[41].OUT_BEL[12] | CFG.USR_EFUSE22 |
| CELL[41].OUT_BEL[14] | CFG.USR_EFUSE23 |
| CELL[41].OUT_BEL[16] | CFG.USR_EFUSE24 |
| CELL[41].OUT_BEL[18] | CFG.USR_EFUSE25 |
| CELL[41].OUT_BEL[20] | CFG.USR_EFUSE26 |
| CELL[41].OUT_BEL[22] | CFG.USR_EFUSE27 |
| CELL[41].OUT_BEL[24] | CFG.USR_EFUSE28 |
| CELL[41].OUT_BEL[26] | CFG.USR_EFUSE29 |
| CELL[41].OUT_BEL[28] | CFG.USR_EFUSE30 |
| CELL[41].OUT_BEL[30] | CFG.USR_EFUSE31 |
| CELL[42].OUT_BEL[0] | CFG.USR_DNA_OUT |
| CELL[42].OUT_BEL[2] | CFG.DCI_LOCK |
| CELL[42].OUT_BEL[4] | CFG.BSCAN_CDR1 |
| CELL[42].OUT_BEL[6] | CFG.BSCAN_CDR2 |
| CELL[42].OUT_BEL[8] | CFG.BSCAN_CLKDR1 |
| CELL[42].OUT_BEL[10] | CFG.BSCAN_CLKDR2 |
| CELL[42].OUT_BEL[12] | CFG.BSCAN_RTI1 |
| CELL[42].OUT_BEL[14] | CFG.BSCAN_RTI2 |
| CELL[42].OUT_BEL[16] | CFG.BSCAN_SDR1 |
| CELL[42].OUT_BEL[18] | CFG.BSCAN_SDR2 |
| CELL[42].OUT_BEL[20] | CFG.BSCAN_SEL1 |
| CELL[42].OUT_BEL[22] | CFG.BSCAN_SEL2 |
| CELL[42].OUT_BEL[24] | CFG.BSCAN_TLR1 |
| CELL[42].OUT_BEL[26] | CFG.BSCAN_TLR2 |
| CELL[42].OUT_BEL[28] | CFG.BSCAN_UDR1 |
| CELL[42].OUT_BEL[30] | CFG.BSCAN_UDR2 |
| CELL[42].IMUX_CTRL[0] | CFG.USR_DNA_CLK |
| CELL[42].IMUX_IMUX_DELAY[0] | CFG.USR_DNA_DIN |
| CELL[42].IMUX_IMUX_DELAY[1] | CFG.USR_DNA_READ |
| CELL[42].IMUX_IMUX_DELAY[2] | CFG.USR_DNA_SHIFT |
| CELL[42].IMUX_IMUX_DELAY[3] | CFG.DCI_USR_RESET_IN |
| CELL[43].OUT_BEL[0] | CFG.ICAP_PR_DONE_BOT |
| CELL[43].OUT_BEL[2] | CFG.ICAP_PR_ERROR_BOT |
| CELL[43].OUT_BEL[4] | CFG.ICAP_AVAIL_BOT |
| CELL[43].OUT_BEL[6] | CFG.BSCAN_TCK1 |
| CELL[43].OUT_BEL[8] | CFG.BSCAN_TCK2 |
| CELL[43].OUT_BEL[10] | CFG.BSCAN_TMS1 |
| CELL[43].OUT_BEL[12] | CFG.BSCAN_TMS2 |
| CELL[43].OUT_BEL[14] | CFG.BSCAN_TDI1 |
| CELL[43].OUT_BEL[16] | CFG.BSCAN_TDI2 |
| CELL[43].OUT_BEL[18] | CFG.USR_TDO |
| CELL[43].IMUX_CTRL[1] | CFG.USR_TCK |
| CELL[43].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO1 |
| CELL[43].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO2 |
| CELL[43].IMUX_IMUX_DELAY[5] | CFG.USR_TMS |
| CELL[43].IMUX_IMUX_DELAY[6] | CFG.USR_TDI |
| CELL[44].OUT_BEL[0] | CFG.ICAP_OUT_BOT0 |
| CELL[44].OUT_BEL[2] | CFG.ICAP_OUT_BOT1 |
| CELL[44].OUT_BEL[4] | CFG.ICAP_OUT_BOT2 |
| CELL[44].OUT_BEL[6] | CFG.ICAP_OUT_BOT3 |
| CELL[44].OUT_BEL[8] | CFG.ICAP_OUT_BOT4 |
| CELL[44].OUT_BEL[10] | CFG.ICAP_OUT_BOT5 |
| CELL[44].OUT_BEL[12] | CFG.ICAP_OUT_BOT6 |
| CELL[44].OUT_BEL[14] | CFG.ICAP_OUT_BOT7 |
| CELL[44].OUT_BEL[16] | CFG.ICAP_OUT_BOT8 |
| CELL[44].OUT_BEL[18] | CFG.ICAP_OUT_BOT9 |
| CELL[44].OUT_BEL[20] | CFG.ICAP_OUT_BOT10 |
| CELL[44].OUT_BEL[22] | CFG.ICAP_OUT_BOT11 |
| CELL[44].OUT_BEL[24] | CFG.ICAP_OUT_BOT12 |
| CELL[44].OUT_BEL[26] | CFG.ICAP_OUT_BOT13 |
| CELL[44].OUT_BEL[28] | CFG.ICAP_OUT_BOT14 |
| CELL[44].OUT_BEL[30] | CFG.ICAP_OUT_BOT15 |
| CELL[44].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT0 |
| CELL[44].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT1 |
| CELL[44].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT2 |
| CELL[44].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT3 |
| CELL[44].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT4 |
| CELL[44].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT5 |
| CELL[44].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT6 |
| CELL[44].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT7 |
| CELL[44].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT8 |
| CELL[44].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT9 |
| CELL[44].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT10 |
| CELL[44].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT11 |
| CELL[44].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT12 |
| CELL[44].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT13 |
| CELL[44].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT14 |
| CELL[44].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT15 |
| CELL[45].OUT_BEL[0] | CFG.ICAP_OUT_BOT16 |
| CELL[45].OUT_BEL[2] | CFG.ICAP_OUT_BOT17 |
| CELL[45].OUT_BEL[4] | CFG.ICAP_OUT_BOT18 |
| CELL[45].OUT_BEL[6] | CFG.ICAP_OUT_BOT19 |
| CELL[45].OUT_BEL[8] | CFG.ICAP_OUT_BOT20 |
| CELL[45].OUT_BEL[10] | CFG.ICAP_OUT_BOT21 |
| CELL[45].OUT_BEL[12] | CFG.ICAP_OUT_BOT22 |
| CELL[45].OUT_BEL[14] | CFG.ICAP_OUT_BOT23 |
| CELL[45].OUT_BEL[16] | CFG.ICAP_OUT_BOT24 |
| CELL[45].OUT_BEL[18] | CFG.ICAP_OUT_BOT25 |
| CELL[45].OUT_BEL[20] | CFG.ICAP_OUT_BOT26 |
| CELL[45].OUT_BEL[22] | CFG.ICAP_OUT_BOT27 |
| CELL[45].OUT_BEL[24] | CFG.ICAP_OUT_BOT28 |
| CELL[45].OUT_BEL[26] | CFG.ICAP_OUT_BOT29 |
| CELL[45].OUT_BEL[28] | CFG.ICAP_OUT_BOT30 |
| CELL[45].OUT_BEL[30] | CFG.ICAP_OUT_BOT31 |
| CELL[45].IMUX_CTRL[0] | CFG.ICAP_CLK_BOT |
| CELL[45].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT16 |
| CELL[45].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT17 |
| CELL[45].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT18 |
| CELL[45].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT19 |
| CELL[45].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT20 |
| CELL[45].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT21 |
| CELL[45].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT22 |
| CELL[45].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT23 |
| CELL[45].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT24 |
| CELL[45].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT25 |
| CELL[45].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT26 |
| CELL[45].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT27 |
| CELL[45].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT28 |
| CELL[45].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT29 |
| CELL[45].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT30 |
| CELL[45].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT31 |
| CELL[46].OUT_BEL[0] | CFG.USR_EFUSE0 |
| CELL[46].OUT_BEL[2] | CFG.USR_EFUSE1 |
| CELL[46].OUT_BEL[4] | CFG.USR_EFUSE2 |
| CELL[46].OUT_BEL[6] | CFG.USR_EFUSE3 |
| CELL[46].OUT_BEL[8] | CFG.USR_EFUSE4 |
| CELL[46].OUT_BEL[10] | CFG.USR_EFUSE5 |
| CELL[46].OUT_BEL[12] | CFG.USR_EFUSE6 |
| CELL[46].OUT_BEL[14] | CFG.USR_EFUSE7 |
| CELL[46].OUT_BEL[16] | CFG.USR_EFUSE8 |
| CELL[46].OUT_BEL[18] | CFG.USR_EFUSE9 |
| CELL[46].OUT_BEL[20] | CFG.USR_EFUSE10 |
| CELL[46].OUT_BEL[22] | CFG.USR_EFUSE11 |
| CELL[46].OUT_BEL[24] | CFG.USR_EFUSE12 |
| CELL[46].OUT_BEL[26] | CFG.USR_EFUSE13 |
| CELL[46].OUT_BEL[28] | CFG.USR_EFUSE14 |
| CELL[46].OUT_BEL[30] | CFG.USR_EFUSE15 |
| CELL[47].OUT_BEL[0] | CFG.USR_D_PIN_CFGIO0 |
| CELL[47].OUT_BEL[2] | CFG.USR_D_PIN_CFGIO1 |
| CELL[47].OUT_BEL[4] | CFG.USR_D_PIN_CFGIO2 |
| CELL[47].OUT_BEL[6] | CFG.USR_D_PIN_CFGIO3 |
| CELL[47].OUT_BEL[8] | CFG.PROG_REQ |
| CELL[47].OUT_BEL[10] | CFG.EOS |
| CELL[47].OUT_BEL[12] | CFG.START_CFG_MCLK |
| CELL[47].OUT_BEL[14] | CFG.START_CFG_CLK |
| CELL[47].IMUX_CTRL[0] | CFG.USR_CCLK_O |
| CELL[47].IMUX_IMUX_DELAY[0] | CFG.KEY_CLEAR_B |
| CELL[47].IMUX_IMUX_DELAY[1] | CFG.PROG_ACK |
| CELL[47].IMUX_IMUX_DELAY[2] | CFG.USR_CCLK_TS |
| CELL[47].IMUX_IMUX_DELAY[3] | CFG.USR_DONE_O |
| CELL[47].IMUX_IMUX_DELAY[4] | CFG.USR_DONE_TS |
| CELL[47].IMUX_IMUX_DELAY[5] | CFG.USR_GSR |
| CELL[47].IMUX_IMUX_DELAY[6] | CFG.USR_GTS |
| CELL[47].IMUX_IMUX_DELAY[7] | CFG.USR_FCS_B_O |
| CELL[47].IMUX_IMUX_DELAY[8] | CFG.USR_FCS_B_TS |
| CELL[47].IMUX_IMUX_DELAY[9] | CFG.USR_D_O_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[10] | CFG.USR_D_O_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[11] | CFG.USR_D_O_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[12] | CFG.USR_D_O_CFGIO3 |
| CELL[47].IMUX_IMUX_DELAY[13] | CFG.USR_D_TS_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[14] | CFG.USR_D_TS_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[15] | CFG.USR_D_TS_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[16] | CFG.USR_D_TS_CFGIO3 |
| CELL[48].OUT_BEL[0] | CFG.IOX_CFGDATA0 |
| CELL[48].OUT_BEL[2] | CFG.IOX_CFGDATA1 |
| CELL[48].OUT_BEL[4] | CFG.IOX_CFGDATA2 |
| CELL[48].OUT_BEL[6] | CFG.IOX_CFGDATA3 |
| CELL[48].OUT_BEL[8] | CFG.IOX_CFGDATA4 |
| CELL[48].OUT_BEL[10] | CFG.IOX_CFGDATA5 |
| CELL[48].OUT_BEL[12] | CFG.IOX_CFGDATA6 |
| CELL[48].OUT_BEL[14] | CFG.IOX_CFGDATA7 |
| CELL[48].OUT_BEL[16] | CFG.IOX_CFGDATA8 |
| CELL[48].OUT_BEL[18] | CFG.IOX_CFGDATA9 |
| CELL[48].OUT_BEL[20] | CFG.IOX_CFGDATA10 |
| CELL[48].OUT_BEL[22] | CFG.IOX_CFGDATA11 |
| CELL[48].OUT_BEL[24] | CFG.IOX_CFGDATA12 |
| CELL[48].OUT_BEL[26] | CFG.IOX_CFGDATA13 |
| CELL[48].OUT_BEL[28] | CFG.IOX_CFGDATA14 |
| CELL[48].OUT_BEL[30] | CFG.IOX_CFGDATA15 |
| CELL[48].IMUX_IMUX_DELAY[0] | CFG.IOX_TDO |
| CELL[48].IMUX_IMUX_DELAY[1] | CFG.IOX_INITBO |
| CELL[49].OUT_BEL[0] | CFG.IOX_CFGDATA16 |
| CELL[49].OUT_BEL[2] | CFG.IOX_CFGDATA17 |
| CELL[49].OUT_BEL[4] | CFG.IOX_CFGDATA18 |
| CELL[49].OUT_BEL[6] | CFG.IOX_CFGDATA19 |
| CELL[49].OUT_BEL[8] | CFG.IOX_CFGDATA20 |
| CELL[49].OUT_BEL[10] | CFG.IOX_CFGDATA21 |
| CELL[49].OUT_BEL[12] | CFG.IOX_CFGDATA22 |
| CELL[49].OUT_BEL[14] | CFG.IOX_CFGDATA23 |
| CELL[49].OUT_BEL[16] | CFG.IOX_CFGDATA24 |
| CELL[49].OUT_BEL[18] | CFG.IOX_CFGDATA25 |
| CELL[49].OUT_BEL[20] | CFG.IOX_CFGDATA26 |
| CELL[49].OUT_BEL[22] | CFG.IOX_CFGDATA27 |
| CELL[49].OUT_BEL[24] | CFG.IOX_CFGDATA28 |
| CELL[49].OUT_BEL[26] | CFG.IOX_CFGDATA29 |
| CELL[49].OUT_BEL[28] | CFG.IOX_CFGDATA30 |
| CELL[49].OUT_BEL[30] | CFG.IOX_CFGDATA31 |
| CELL[50].OUT_BEL[0] | CFG.IOX_CCLK |
| CELL[50].OUT_BEL[2] | CFG.IOX_CFGMASTER |
| CELL[50].OUT_BEL[4] | CFG.IOX_VGG_COMP_OUT |
| CELL[50].OUT_BEL[6] | CFG.IOX_INITBI |
| CELL[50].OUT_BEL[8] | CFG.IOX_PUDCB |
| CELL[50].OUT_BEL[10] | CFG.IOX_RDWRB |
| CELL[50].OUT_BEL[12] | CFG.IOX_MODE0 |
| CELL[50].OUT_BEL[14] | CFG.IOX_MODE1 |
| CELL[50].OUT_BEL[16] | CFG.IOX_MODE2 |
| CELL[51].OUT_BEL[0] | CFG.ECC_FAR16 |
| CELL[51].OUT_BEL[2] | CFG.ECC_FAR17 |
| CELL[51].OUT_BEL[4] | CFG.ECC_FAR18 |
| CELL[51].OUT_BEL[6] | CFG.ECC_FAR19 |
| CELL[51].OUT_BEL[8] | CFG.ECC_FAR20 |
| CELL[51].OUT_BEL[10] | CFG.ECC_FAR21 |
| CELL[51].OUT_BEL[12] | CFG.ECC_FAR22 |
| CELL[51].OUT_BEL[14] | CFG.ECC_FAR23 |
| CELL[51].OUT_BEL[16] | CFG.ECC_FAR24 |
| CELL[51].OUT_BEL[18] | CFG.ECC_FAR25 |
| CELL[51].OUT_BEL[20] | CFG.RBCRC_ERROR |
| CELL[51].OUT_BEL[22] | CFG.ECC_ERROR_NOTSINGLE |
| CELL[51].OUT_BEL[24] | CFG.ECC_ERROR_SINGLE |
| CELL[51].OUT_BEL[26] | CFG.ECC_END_OF_FRAME |
| CELL[51].OUT_BEL[28] | CFG.ECC_END_OF_SCAN |
| CELL[51].IMUX_IMUX_DELAY[15] | CFG.ECC_FAR_SEL0 |
| CELL[51].IMUX_IMUX_DELAY[16] | CFG.ECC_FAR_SEL1 |
| CELL[52].OUT_BEL[0] | CFG.ECC_FAR0 |
| CELL[52].OUT_BEL[2] | CFG.ECC_FAR1 |
| CELL[52].OUT_BEL[4] | CFG.ECC_FAR2 |
| CELL[52].OUT_BEL[6] | CFG.ECC_FAR3 |
| CELL[52].OUT_BEL[8] | CFG.ECC_FAR4 |
| CELL[52].OUT_BEL[10] | CFG.ECC_FAR5 |
| CELL[52].OUT_BEL[12] | CFG.ECC_FAR6 |
| CELL[52].OUT_BEL[14] | CFG.ECC_FAR7 |
| CELL[52].OUT_BEL[16] | CFG.ECC_FAR8 |
| CELL[52].OUT_BEL[18] | CFG.ECC_FAR9 |
| CELL[52].OUT_BEL[20] | CFG.ECC_FAR10 |
| CELL[52].OUT_BEL[22] | CFG.ECC_FAR11 |
| CELL[52].OUT_BEL[24] | CFG.ECC_FAR12 |
| CELL[52].OUT_BEL[26] | CFG.ECC_FAR13 |
| CELL[52].OUT_BEL[28] | CFG.ECC_FAR14 |
| CELL[52].OUT_BEL[30] | CFG.ECC_FAR15 |
| CELL[52].OUT_BEL[31] | CFG.ECC_FAR26 |
| CELL[53].OUT_BEL[0] | CFG.BSCAN_SDR3 |
| CELL[53].OUT_BEL[2] | CFG.BSCAN_SDR4 |
| CELL[53].OUT_BEL[4] | CFG.BSCAN_SEL3 |
| CELL[53].OUT_BEL[6] | CFG.BSCAN_SEL4 |
| CELL[53].OUT_BEL[8] | CFG.BSCAN_TLR3 |
| CELL[53].OUT_BEL[10] | CFG.BSCAN_TLR4 |
| CELL[53].OUT_BEL[12] | CFG.BSCAN_UDR3 |
| CELL[53].OUT_BEL[14] | CFG.BSCAN_UDR4 |
| CELL[54].OUT_BEL[0] | CFG.ICAP_PR_DONE_TOP |
| CELL[54].OUT_BEL[2] | CFG.ICAP_PR_ERROR_TOP |
| CELL[54].OUT_BEL[4] | CFG.ICAP_AVAIL_TOP |
| CELL[54].OUT_BEL[6] | CFG.BSCAN_TCK3 |
| CELL[54].OUT_BEL[8] | CFG.BSCAN_TCK4 |
| CELL[54].OUT_BEL[10] | CFG.BSCAN_TMS3 |
| CELL[54].OUT_BEL[12] | CFG.BSCAN_TMS4 |
| CELL[54].OUT_BEL[14] | CFG.BSCAN_TDI3 |
| CELL[54].OUT_BEL[16] | CFG.BSCAN_TDI4 |
| CELL[54].OUT_BEL[18] | CFG.BSCAN_CDR3 |
| CELL[54].OUT_BEL[20] | CFG.BSCAN_CDR4 |
| CELL[54].OUT_BEL[22] | CFG.BSCAN_CLKDR3 |
| CELL[54].OUT_BEL[24] | CFG.BSCAN_CLKDR4 |
| CELL[54].OUT_BEL[26] | CFG.BSCAN_RTI3 |
| CELL[54].OUT_BEL[28] | CFG.BSCAN_RTI4 |
| CELL[54].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO3 |
| CELL[54].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO4 |
| CELL[55].OUT_BEL[0] | CFG.ICAP_OUT_TOP0 |
| CELL[55].OUT_BEL[2] | CFG.ICAP_OUT_TOP1 |
| CELL[55].OUT_BEL[4] | CFG.ICAP_OUT_TOP2 |
| CELL[55].OUT_BEL[6] | CFG.ICAP_OUT_TOP3 |
| CELL[55].OUT_BEL[8] | CFG.ICAP_OUT_TOP4 |
| CELL[55].OUT_BEL[10] | CFG.ICAP_OUT_TOP5 |
| CELL[55].OUT_BEL[12] | CFG.ICAP_OUT_TOP6 |
| CELL[55].OUT_BEL[14] | CFG.ICAP_OUT_TOP7 |
| CELL[55].OUT_BEL[16] | CFG.ICAP_OUT_TOP8 |
| CELL[55].OUT_BEL[18] | CFG.ICAP_OUT_TOP9 |
| CELL[55].OUT_BEL[20] | CFG.ICAP_OUT_TOP10 |
| CELL[55].OUT_BEL[22] | CFG.ICAP_OUT_TOP11 |
| CELL[55].OUT_BEL[24] | CFG.ICAP_OUT_TOP12 |
| CELL[55].OUT_BEL[26] | CFG.ICAP_OUT_TOP13 |
| CELL[55].OUT_BEL[28] | CFG.ICAP_OUT_TOP14 |
| CELL[55].OUT_BEL[30] | CFG.ICAP_OUT_TOP15 |
| CELL[55].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP0 |
| CELL[55].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP1 |
| CELL[55].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP2 |
| CELL[55].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP3 |
| CELL[55].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP4 |
| CELL[55].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP5 |
| CELL[55].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP6 |
| CELL[55].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP7 |
| CELL[55].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP8 |
| CELL[55].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP9 |
| CELL[55].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP10 |
| CELL[55].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP11 |
| CELL[55].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP12 |
| CELL[55].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP13 |
| CELL[55].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP14 |
| CELL[55].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP15 |
| CELL[56].OUT_BEL[0] | CFG.ICAP_OUT_TOP16 |
| CELL[56].OUT_BEL[2] | CFG.ICAP_OUT_TOP17 |
| CELL[56].OUT_BEL[4] | CFG.ICAP_OUT_TOP18 |
| CELL[56].OUT_BEL[6] | CFG.ICAP_OUT_TOP19 |
| CELL[56].OUT_BEL[8] | CFG.ICAP_OUT_TOP20 |
| CELL[56].OUT_BEL[10] | CFG.ICAP_OUT_TOP21 |
| CELL[56].OUT_BEL[12] | CFG.ICAP_OUT_TOP22 |
| CELL[56].OUT_BEL[14] | CFG.ICAP_OUT_TOP23 |
| CELL[56].OUT_BEL[16] | CFG.ICAP_OUT_TOP24 |
| CELL[56].OUT_BEL[18] | CFG.ICAP_OUT_TOP25 |
| CELL[56].OUT_BEL[20] | CFG.ICAP_OUT_TOP26 |
| CELL[56].OUT_BEL[22] | CFG.ICAP_OUT_TOP27 |
| CELL[56].OUT_BEL[24] | CFG.ICAP_OUT_TOP28 |
| CELL[56].OUT_BEL[26] | CFG.ICAP_OUT_TOP29 |
| CELL[56].OUT_BEL[28] | CFG.ICAP_OUT_TOP30 |
| CELL[56].OUT_BEL[30] | CFG.ICAP_OUT_TOP31 |
| CELL[56].IMUX_CTRL[0] | CFG.ICAP_CLK_TOP |
| CELL[56].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP16 |
| CELL[56].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP17 |
| CELL[56].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP18 |
| CELL[56].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP19 |
| CELL[56].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP20 |
| CELL[56].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP21 |
| CELL[56].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP22 |
| CELL[56].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP23 |
| CELL[56].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP24 |
| CELL[56].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP25 |
| CELL[56].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP26 |
| CELL[56].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP27 |
| CELL[56].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP28 |
| CELL[56].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP29 |
| CELL[56].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP30 |
| CELL[56].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP31 |
| CELL[57].OUT_BEL[0] | CFG.USR_ACCESS_VALID |
| CELL[57].OUT_BEL[2] | CFG.USR_ACCESS_CLK |
| CELL[58].OUT_BEL[0] | CFG.USR_ACCESS_DATA0 |
| CELL[58].OUT_BEL[2] | CFG.USR_ACCESS_DATA1 |
| CELL[58].OUT_BEL[4] | CFG.USR_ACCESS_DATA2 |
| CELL[58].OUT_BEL[6] | CFG.USR_ACCESS_DATA3 |
| CELL[58].OUT_BEL[8] | CFG.USR_ACCESS_DATA4 |
| CELL[58].OUT_BEL[10] | CFG.USR_ACCESS_DATA5 |
| CELL[58].OUT_BEL[12] | CFG.USR_ACCESS_DATA6 |
| CELL[58].OUT_BEL[14] | CFG.USR_ACCESS_DATA7 |
| CELL[58].OUT_BEL[16] | CFG.USR_ACCESS_DATA8 |
| CELL[58].OUT_BEL[18] | CFG.USR_ACCESS_DATA9 |
| CELL[58].OUT_BEL[20] | CFG.USR_ACCESS_DATA10 |
| CELL[58].OUT_BEL[22] | CFG.USR_ACCESS_DATA11 |
| CELL[58].OUT_BEL[24] | CFG.USR_ACCESS_DATA12 |
| CELL[58].OUT_BEL[26] | CFG.USR_ACCESS_DATA13 |
| CELL[58].OUT_BEL[28] | CFG.USR_ACCESS_DATA14 |
| CELL[58].OUT_BEL[30] | CFG.USR_ACCESS_DATA15 |
| CELL[59].OUT_BEL[0] | CFG.USR_ACCESS_DATA16 |
| CELL[59].OUT_BEL[2] | CFG.USR_ACCESS_DATA17 |
| CELL[59].OUT_BEL[4] | CFG.USR_ACCESS_DATA18 |
| CELL[59].OUT_BEL[6] | CFG.USR_ACCESS_DATA19 |
| CELL[59].OUT_BEL[8] | CFG.USR_ACCESS_DATA20 |
| CELL[59].OUT_BEL[10] | CFG.USR_ACCESS_DATA21 |
| CELL[59].OUT_BEL[12] | CFG.USR_ACCESS_DATA22 |
| CELL[59].OUT_BEL[14] | CFG.USR_ACCESS_DATA23 |
| CELL[59].OUT_BEL[16] | CFG.USR_ACCESS_DATA24 |
| CELL[59].OUT_BEL[18] | CFG.USR_ACCESS_DATA25 |
| CELL[59].OUT_BEL[20] | CFG.USR_ACCESS_DATA26 |
| CELL[59].OUT_BEL[22] | CFG.USR_ACCESS_DATA27 |
| CELL[59].OUT_BEL[24] | CFG.USR_ACCESS_DATA28 |
| CELL[59].OUT_BEL[26] | CFG.USR_ACCESS_DATA29 |
| CELL[59].OUT_BEL[28] | CFG.USR_ACCESS_DATA30 |
| CELL[59].OUT_BEL[30] | CFG.USR_ACCESS_DATA31 |
Tile CFG_CSEC_V2
Cells: 60
Bel CFG
| Pin | Direction | Wires |
|---|---|---|
| ARADDR0 | input | CELL[20].IMUX_IMUX_DELAY[9] |
| ARADDR1 | input | CELL[20].IMUX_IMUX_DELAY[10] |
| ARADDR10 | input | CELL[21].IMUX_IMUX_DELAY[3] |
| ARADDR11 | input | CELL[21].IMUX_IMUX_DELAY[4] |
| ARADDR12 | input | CELL[21].IMUX_IMUX_DELAY[5] |
| ARADDR13 | input | CELL[21].IMUX_IMUX_DELAY[6] |
| ARADDR14 | input | CELL[21].IMUX_IMUX_DELAY[7] |
| ARADDR15 | input | CELL[21].IMUX_IMUX_DELAY[8] |
| ARADDR16 | input | CELL[21].IMUX_IMUX_DELAY[9] |
| ARADDR17 | input | CELL[21].IMUX_IMUX_DELAY[10] |
| ARADDR18 | input | CELL[21].IMUX_IMUX_DELAY[11] |
| ARADDR19 | input | CELL[21].IMUX_IMUX_DELAY[12] |
| ARADDR2 | input | CELL[20].IMUX_IMUX_DELAY[11] |
| ARADDR20 | input | CELL[21].IMUX_IMUX_DELAY[13] |
| ARADDR21 | input | CELL[21].IMUX_IMUX_DELAY[14] |
| ARADDR22 | input | CELL[20].IMUX_IMUX_DELAY[3] |
| ARADDR23 | input | CELL[20].IMUX_IMUX_DELAY[4] |
| ARADDR24 | input | CELL[20].IMUX_IMUX_DELAY[5] |
| ARADDR25 | input | CELL[20].IMUX_IMUX_DELAY[6] |
| ARADDR26 | input | CELL[20].IMUX_IMUX_DELAY[7] |
| ARADDR27 | input | CELL[20].IMUX_IMUX_DELAY[8] |
| ARADDR3 | input | CELL[20].IMUX_IMUX_DELAY[12] |
| ARADDR4 | input | CELL[20].IMUX_IMUX_DELAY[13] |
| ARADDR5 | input | CELL[20].IMUX_IMUX_DELAY[14] |
| ARADDR6 | input | CELL[20].IMUX_IMUX_DELAY[15] |
| ARADDR7 | input | CELL[21].IMUX_IMUX_DELAY[0] |
| ARADDR8 | input | CELL[21].IMUX_IMUX_DELAY[1] |
| ARADDR9 | input | CELL[21].IMUX_IMUX_DELAY[2] |
| ARBURST0 | input | CELL[22].IMUX_IMUX_DELAY[6] |
| ARBURST1 | input | CELL[22].IMUX_IMUX_DELAY[7] |
| ARCACHE0 | input | CELL[22].IMUX_IMUX_DELAY[9] |
| ARCACHE1 | input | CELL[22].IMUX_IMUX_DELAY[10] |
| ARCACHE2 | input | CELL[22].IMUX_IMUX_DELAY[11] |
| ARCACHE3 | input | CELL[22].IMUX_IMUX_DELAY[12] |
| ARID0 | input | CELL[31].IMUX_IMUX_DELAY[1] |
| ARID1 | input | CELL[31].IMUX_IMUX_DELAY[2] |
| ARID2 | input | CELL[31].IMUX_IMUX_DELAY[3] |
| ARID3 | input | CELL[31].IMUX_IMUX_DELAY[4] |
| ARID4 | input | CELL[31].IMUX_IMUX_DELAY[5] |
| ARID5 | input | CELL[31].IMUX_IMUX_DELAY[6] |
| ARID6 | input | CELL[31].IMUX_IMUX_DELAY[7] |
| ARID7 | input | CELL[31].IMUX_IMUX_DELAY[8] |
| ARLEN0 | input | CELL[21].IMUX_IMUX_DELAY[15] |
| ARLEN1 | input | CELL[22].IMUX_IMUX_DELAY[0] |
| ARLEN2 | input | CELL[22].IMUX_IMUX_DELAY[1] |
| ARLEN3 | input | CELL[22].IMUX_IMUX_DELAY[2] |
| ARLOCK | input | CELL[22].IMUX_IMUX_DELAY[8] |
| ARPROT0 | input | CELL[22].IMUX_IMUX_DELAY[13] |
| ARPROT1 | input | CELL[22].IMUX_IMUX_DELAY[14] |
| ARPROT2 | input | CELL[22].IMUX_IMUX_DELAY[15] |
| ARQOS0 | input | CELL[23].IMUX_IMUX_DELAY[0] |
| ARQOS1 | input | CELL[23].IMUX_IMUX_DELAY[1] |
| ARQOS2 | input | CELL[23].IMUX_IMUX_DELAY[2] |
| ARQOS3 | input | CELL[23].IMUX_IMUX_DELAY[3] |
| ARREADY | output | CELL[20].OUT_BEL[0] |
| ARSIZE0 | input | CELL[22].IMUX_IMUX_DELAY[3] |
| ARSIZE1 | input | CELL[22].IMUX_IMUX_DELAY[4] |
| ARSIZE2 | input | CELL[22].IMUX_IMUX_DELAY[5] |
| ARVALID | input | CELL[20].IMUX_IMUX_DELAY[0] |
| AWADDR0 | input | CELL[24].IMUX_IMUX_DELAY[9] |
| AWADDR1 | input | CELL[24].IMUX_IMUX_DELAY[10] |
| AWADDR10 | input | CELL[25].IMUX_IMUX_DELAY[3] |
| AWADDR11 | input | CELL[25].IMUX_IMUX_DELAY[4] |
| AWADDR12 | input | CELL[25].IMUX_IMUX_DELAY[5] |
| AWADDR13 | input | CELL[25].IMUX_IMUX_DELAY[6] |
| AWADDR14 | input | CELL[25].IMUX_IMUX_DELAY[7] |
| AWADDR15 | input | CELL[25].IMUX_IMUX_DELAY[8] |
| AWADDR16 | input | CELL[25].IMUX_IMUX_DELAY[9] |
| AWADDR17 | input | CELL[25].IMUX_IMUX_DELAY[10] |
| AWADDR18 | input | CELL[25].IMUX_IMUX_DELAY[11] |
| AWADDR19 | input | CELL[25].IMUX_IMUX_DELAY[12] |
| AWADDR2 | input | CELL[24].IMUX_IMUX_DELAY[11] |
| AWADDR20 | input | CELL[25].IMUX_IMUX_DELAY[13] |
| AWADDR21 | input | CELL[25].IMUX_IMUX_DELAY[14] |
| AWADDR22 | input | CELL[24].IMUX_IMUX_DELAY[3] |
| AWADDR23 | input | CELL[24].IMUX_IMUX_DELAY[4] |
| AWADDR24 | input | CELL[24].IMUX_IMUX_DELAY[5] |
| AWADDR25 | input | CELL[24].IMUX_IMUX_DELAY[6] |
| AWADDR26 | input | CELL[24].IMUX_IMUX_DELAY[7] |
| AWADDR27 | input | CELL[24].IMUX_IMUX_DELAY[8] |
| AWADDR3 | input | CELL[24].IMUX_IMUX_DELAY[12] |
| AWADDR4 | input | CELL[24].IMUX_IMUX_DELAY[13] |
| AWADDR5 | input | CELL[24].IMUX_IMUX_DELAY[14] |
| AWADDR6 | input | CELL[24].IMUX_IMUX_DELAY[15] |
| AWADDR7 | input | CELL[25].IMUX_IMUX_DELAY[0] |
| AWADDR8 | input | CELL[25].IMUX_IMUX_DELAY[1] |
| AWADDR9 | input | CELL[25].IMUX_IMUX_DELAY[2] |
| AWBURST0 | input | CELL[26].IMUX_IMUX_DELAY[6] |
| AWBURST1 | input | CELL[26].IMUX_IMUX_DELAY[7] |
| AWCACHE0 | input | CELL[26].IMUX_IMUX_DELAY[9] |
| AWCACHE1 | input | CELL[26].IMUX_IMUX_DELAY[10] |
| AWCACHE2 | input | CELL[26].IMUX_IMUX_DELAY[11] |
| AWCACHE3 | input | CELL[26].IMUX_IMUX_DELAY[12] |
| AWID0 | input | CELL[32].IMUX_IMUX_DELAY[1] |
| AWID1 | input | CELL[32].IMUX_IMUX_DELAY[2] |
| AWID2 | input | CELL[32].IMUX_IMUX_DELAY[3] |
| AWID3 | input | CELL[32].IMUX_IMUX_DELAY[4] |
| AWID4 | input | CELL[32].IMUX_IMUX_DELAY[5] |
| AWID5 | input | CELL[32].IMUX_IMUX_DELAY[6] |
| AWID6 | input | CELL[32].IMUX_IMUX_DELAY[7] |
| AWID7 | input | CELL[32].IMUX_IMUX_DELAY[8] |
| AWLEN0 | input | CELL[25].IMUX_IMUX_DELAY[15] |
| AWLEN1 | input | CELL[26].IMUX_IMUX_DELAY[0] |
| AWLEN2 | input | CELL[26].IMUX_IMUX_DELAY[1] |
| AWLEN3 | input | CELL[26].IMUX_IMUX_DELAY[2] |
| AWLOCK | input | CELL[26].IMUX_IMUX_DELAY[8] |
| AWPROT0 | input | CELL[26].IMUX_IMUX_DELAY[13] |
| AWPROT1 | input | CELL[26].IMUX_IMUX_DELAY[14] |
| AWPROT2 | input | CELL[26].IMUX_IMUX_DELAY[15] |
| AWQOS0 | input | CELL[27].IMUX_IMUX_DELAY[0] |
| AWQOS1 | input | CELL[27].IMUX_IMUX_DELAY[1] |
| AWQOS2 | input | CELL[27].IMUX_IMUX_DELAY[2] |
| AWQOS3 | input | CELL[27].IMUX_IMUX_DELAY[3] |
| AWREADY | output | CELL[24].OUT_BEL[0] |
| AWSIZE0 | input | CELL[26].IMUX_IMUX_DELAY[3] |
| AWSIZE1 | input | CELL[26].IMUX_IMUX_DELAY[4] |
| AWSIZE2 | input | CELL[26].IMUX_IMUX_DELAY[5] |
| AWVALID | input | CELL[24].IMUX_IMUX_DELAY[0] |
| AXI_CLK | input | CELL[20].IMUX_CTRL[0] |
| BID0 | output | CELL[34].OUT_BEL[2] |
| BID1 | output | CELL[34].OUT_BEL[4] |
| BID2 | output | CELL[34].OUT_BEL[6] |
| BID3 | output | CELL[34].OUT_BEL[8] |
| BID4 | output | CELL[34].OUT_BEL[10] |
| BID5 | output | CELL[34].OUT_BEL[12] |
| BID6 | output | CELL[34].OUT_BEL[14] |
| BID7 | output | CELL[34].OUT_BEL[16] |
| BREADY | input | CELL[34].IMUX_IMUX_DELAY[0] |
| BRESP0 | output | CELL[34].OUT_BEL[18] |
| BRESP1 | output | CELL[34].OUT_BEL[20] |
| BSCAN_CDR1 | output | CELL[42].OUT_BEL[4] |
| BSCAN_CDR2 | output | CELL[42].OUT_BEL[6] |
| BSCAN_CDR3 | output | CELL[54].OUT_BEL[18] |
| BSCAN_CDR4 | output | CELL[54].OUT_BEL[20] |
| BSCAN_CLKDR1 | output | CELL[42].OUT_BEL[8] |
| BSCAN_CLKDR2 | output | CELL[42].OUT_BEL[10] |
| BSCAN_CLKDR3 | output | CELL[54].OUT_BEL[22] |
| BSCAN_CLKDR4 | output | CELL[54].OUT_BEL[24] |
| BSCAN_RTI1 | output | CELL[42].OUT_BEL[12] |
| BSCAN_RTI2 | output | CELL[42].OUT_BEL[14] |
| BSCAN_RTI3 | output | CELL[54].OUT_BEL[26] |
| BSCAN_RTI4 | output | CELL[54].OUT_BEL[28] |
| BSCAN_SDR1 | output | CELL[42].OUT_BEL[16] |
| BSCAN_SDR2 | output | CELL[42].OUT_BEL[18] |
| BSCAN_SDR3 | output | CELL[53].OUT_BEL[0] |
| BSCAN_SDR4 | output | CELL[53].OUT_BEL[2] |
| BSCAN_SEL1 | output | CELL[42].OUT_BEL[20] |
| BSCAN_SEL2 | output | CELL[42].OUT_BEL[22] |
| BSCAN_SEL3 | output | CELL[53].OUT_BEL[4] |
| BSCAN_SEL4 | output | CELL[53].OUT_BEL[6] |
| BSCAN_TCK1 | output | CELL[43].OUT_BEL[6] |
| BSCAN_TCK2 | output | CELL[43].OUT_BEL[8] |
| BSCAN_TCK3 | output | CELL[54].OUT_BEL[6] |
| BSCAN_TCK4 | output | CELL[54].OUT_BEL[8] |
| BSCAN_TDI1 | output | CELL[43].OUT_BEL[14] |
| BSCAN_TDI2 | output | CELL[43].OUT_BEL[16] |
| BSCAN_TDI3 | output | CELL[54].OUT_BEL[14] |
| BSCAN_TDI4 | output | CELL[54].OUT_BEL[16] |
| BSCAN_TDO1 | input | CELL[43].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO2 | input | CELL[43].IMUX_IMUX_DELAY[3] |
| BSCAN_TDO3 | input | CELL[54].IMUX_IMUX_DELAY[2] |
| BSCAN_TDO4 | input | CELL[54].IMUX_IMUX_DELAY[3] |
| BSCAN_TLR1 | output | CELL[42].OUT_BEL[24] |
| BSCAN_TLR2 | output | CELL[42].OUT_BEL[26] |
| BSCAN_TLR3 | output | CELL[53].OUT_BEL[8] |
| BSCAN_TLR4 | output | CELL[53].OUT_BEL[10] |
| BSCAN_TMS1 | output | CELL[43].OUT_BEL[10] |
| BSCAN_TMS2 | output | CELL[43].OUT_BEL[12] |
| BSCAN_TMS3 | output | CELL[54].OUT_BEL[10] |
| BSCAN_TMS4 | output | CELL[54].OUT_BEL[12] |
| BSCAN_UDR1 | output | CELL[42].OUT_BEL[28] |
| BSCAN_UDR2 | output | CELL[42].OUT_BEL[30] |
| BSCAN_UDR3 | output | CELL[53].OUT_BEL[12] |
| BSCAN_UDR4 | output | CELL[53].OUT_BEL[14] |
| BVALID | output | CELL[34].OUT_BEL[0] |
| DCI_LOCK | output | CELL[42].OUT_BEL[2] |
| DCI_USR_RESET_IN | input | CELL[42].IMUX_IMUX_DELAY[3] |
| ECC_END_OF_FRAME | output | CELL[51].OUT_BEL[26] |
| ECC_END_OF_SCAN | output | CELL[51].OUT_BEL[28] |
| ECC_ERROR_NOTSINGLE | output | CELL[51].OUT_BEL[22] |
| ECC_ERROR_SINGLE | output | CELL[51].OUT_BEL[24] |
| ECC_FAR0 | output | CELL[52].OUT_BEL[0] |
| ECC_FAR1 | output | CELL[52].OUT_BEL[2] |
| ECC_FAR10 | output | CELL[52].OUT_BEL[20] |
| ECC_FAR11 | output | CELL[52].OUT_BEL[22] |
| ECC_FAR12 | output | CELL[52].OUT_BEL[24] |
| ECC_FAR13 | output | CELL[52].OUT_BEL[26] |
| ECC_FAR14 | output | CELL[52].OUT_BEL[28] |
| ECC_FAR15 | output | CELL[52].OUT_BEL[30] |
| ECC_FAR16 | output | CELL[51].OUT_BEL[0] |
| ECC_FAR17 | output | CELL[51].OUT_BEL[2] |
| ECC_FAR18 | output | CELL[51].OUT_BEL[4] |
| ECC_FAR19 | output | CELL[51].OUT_BEL[6] |
| ECC_FAR2 | output | CELL[52].OUT_BEL[4] |
| ECC_FAR20 | output | CELL[51].OUT_BEL[8] |
| ECC_FAR21 | output | CELL[51].OUT_BEL[10] |
| ECC_FAR22 | output | CELL[51].OUT_BEL[12] |
| ECC_FAR23 | output | CELL[51].OUT_BEL[14] |
| ECC_FAR24 | output | CELL[51].OUT_BEL[16] |
| ECC_FAR25 | output | CELL[51].OUT_BEL[18] |
| ECC_FAR26 | output | CELL[52].OUT_BEL[31] |
| ECC_FAR3 | output | CELL[52].OUT_BEL[6] |
| ECC_FAR4 | output | CELL[52].OUT_BEL[8] |
| ECC_FAR5 | output | CELL[52].OUT_BEL[10] |
| ECC_FAR6 | output | CELL[52].OUT_BEL[12] |
| ECC_FAR7 | output | CELL[52].OUT_BEL[14] |
| ECC_FAR8 | output | CELL[52].OUT_BEL[16] |
| ECC_FAR9 | output | CELL[52].OUT_BEL[18] |
| ECC_FAR_SEL0 | input | CELL[51].IMUX_IMUX_DELAY[15] |
| ECC_FAR_SEL1 | input | CELL[51].IMUX_IMUX_DELAY[16] |
| EOS | output | CELL[47].OUT_BEL[10] |
| ICAP_AVAIL_BOT | output | CELL[43].OUT_BEL[4] |
| ICAP_AVAIL_TOP | output | CELL[54].OUT_BEL[4] |
| ICAP_CLK_BOT | input | CELL[45].IMUX_CTRL[0] |
| ICAP_CLK_TOP | input | CELL[56].IMUX_CTRL[0] |
| ICAP_CS_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[1] |
| ICAP_CS_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT0 | input | CELL[44].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT1 | input | CELL[44].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT10 | input | CELL[44].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT11 | input | CELL[44].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT12 | input | CELL[44].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT13 | input | CELL[44].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT14 | input | CELL[44].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT15 | input | CELL[44].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT16 | input | CELL[45].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_BOT17 | input | CELL[45].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_BOT18 | input | CELL[45].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT19 | input | CELL[45].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT2 | input | CELL[44].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_BOT20 | input | CELL[45].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT21 | input | CELL[45].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT22 | input | CELL[45].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT23 | input | CELL[45].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT24 | input | CELL[45].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT25 | input | CELL[45].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_BOT26 | input | CELL[45].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_BOT27 | input | CELL[45].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_BOT28 | input | CELL[45].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_BOT29 | input | CELL[45].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_BOT3 | input | CELL[44].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_BOT30 | input | CELL[45].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_BOT31 | input | CELL[45].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_BOT4 | input | CELL[44].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_BOT5 | input | CELL[44].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_BOT6 | input | CELL[44].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_BOT7 | input | CELL[44].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_BOT8 | input | CELL[44].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_BOT9 | input | CELL[44].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP0 | input | CELL[55].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP1 | input | CELL[55].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP10 | input | CELL[55].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP11 | input | CELL[55].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP12 | input | CELL[55].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP13 | input | CELL[55].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP14 | input | CELL[55].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP15 | input | CELL[55].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP16 | input | CELL[56].IMUX_IMUX_DELAY[0] |
| ICAP_DATA_TOP17 | input | CELL[56].IMUX_IMUX_DELAY[1] |
| ICAP_DATA_TOP18 | input | CELL[56].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP19 | input | CELL[56].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP2 | input | CELL[55].IMUX_IMUX_DELAY[2] |
| ICAP_DATA_TOP20 | input | CELL[56].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP21 | input | CELL[56].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP22 | input | CELL[56].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP23 | input | CELL[56].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP24 | input | CELL[56].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP25 | input | CELL[56].IMUX_IMUX_DELAY[9] |
| ICAP_DATA_TOP26 | input | CELL[56].IMUX_IMUX_DELAY[10] |
| ICAP_DATA_TOP27 | input | CELL[56].IMUX_IMUX_DELAY[11] |
| ICAP_DATA_TOP28 | input | CELL[56].IMUX_IMUX_DELAY[12] |
| ICAP_DATA_TOP29 | input | CELL[56].IMUX_IMUX_DELAY[13] |
| ICAP_DATA_TOP3 | input | CELL[55].IMUX_IMUX_DELAY[3] |
| ICAP_DATA_TOP30 | input | CELL[56].IMUX_IMUX_DELAY[14] |
| ICAP_DATA_TOP31 | input | CELL[56].IMUX_IMUX_DELAY[15] |
| ICAP_DATA_TOP4 | input | CELL[55].IMUX_IMUX_DELAY[4] |
| ICAP_DATA_TOP5 | input | CELL[55].IMUX_IMUX_DELAY[5] |
| ICAP_DATA_TOP6 | input | CELL[55].IMUX_IMUX_DELAY[6] |
| ICAP_DATA_TOP7 | input | CELL[55].IMUX_IMUX_DELAY[7] |
| ICAP_DATA_TOP8 | input | CELL[55].IMUX_IMUX_DELAY[8] |
| ICAP_DATA_TOP9 | input | CELL[55].IMUX_IMUX_DELAY[9] |
| ICAP_OUT_BOT0 | output | CELL[44].OUT_BEL[0] |
| ICAP_OUT_BOT1 | output | CELL[44].OUT_BEL[2] |
| ICAP_OUT_BOT10 | output | CELL[44].OUT_BEL[20] |
| ICAP_OUT_BOT11 | output | CELL[44].OUT_BEL[22] |
| ICAP_OUT_BOT12 | output | CELL[44].OUT_BEL[24] |
| ICAP_OUT_BOT13 | output | CELL[44].OUT_BEL[26] |
| ICAP_OUT_BOT14 | output | CELL[44].OUT_BEL[28] |
| ICAP_OUT_BOT15 | output | CELL[44].OUT_BEL[30] |
| ICAP_OUT_BOT16 | output | CELL[45].OUT_BEL[0] |
| ICAP_OUT_BOT17 | output | CELL[45].OUT_BEL[2] |
| ICAP_OUT_BOT18 | output | CELL[45].OUT_BEL[4] |
| ICAP_OUT_BOT19 | output | CELL[45].OUT_BEL[6] |
| ICAP_OUT_BOT2 | output | CELL[44].OUT_BEL[4] |
| ICAP_OUT_BOT20 | output | CELL[45].OUT_BEL[8] |
| ICAP_OUT_BOT21 | output | CELL[45].OUT_BEL[10] |
| ICAP_OUT_BOT22 | output | CELL[45].OUT_BEL[12] |
| ICAP_OUT_BOT23 | output | CELL[45].OUT_BEL[14] |
| ICAP_OUT_BOT24 | output | CELL[45].OUT_BEL[16] |
| ICAP_OUT_BOT25 | output | CELL[45].OUT_BEL[18] |
| ICAP_OUT_BOT26 | output | CELL[45].OUT_BEL[20] |
| ICAP_OUT_BOT27 | output | CELL[45].OUT_BEL[22] |
| ICAP_OUT_BOT28 | output | CELL[45].OUT_BEL[24] |
| ICAP_OUT_BOT29 | output | CELL[45].OUT_BEL[26] |
| ICAP_OUT_BOT3 | output | CELL[44].OUT_BEL[6] |
| ICAP_OUT_BOT30 | output | CELL[45].OUT_BEL[28] |
| ICAP_OUT_BOT31 | output | CELL[45].OUT_BEL[30] |
| ICAP_OUT_BOT4 | output | CELL[44].OUT_BEL[8] |
| ICAP_OUT_BOT5 | output | CELL[44].OUT_BEL[10] |
| ICAP_OUT_BOT6 | output | CELL[44].OUT_BEL[12] |
| ICAP_OUT_BOT7 | output | CELL[44].OUT_BEL[14] |
| ICAP_OUT_BOT8 | output | CELL[44].OUT_BEL[16] |
| ICAP_OUT_BOT9 | output | CELL[44].OUT_BEL[18] |
| ICAP_OUT_TOP0 | output | CELL[55].OUT_BEL[0] |
| ICAP_OUT_TOP1 | output | CELL[55].OUT_BEL[2] |
| ICAP_OUT_TOP10 | output | CELL[55].OUT_BEL[20] |
| ICAP_OUT_TOP11 | output | CELL[55].OUT_BEL[22] |
| ICAP_OUT_TOP12 | output | CELL[55].OUT_BEL[24] |
| ICAP_OUT_TOP13 | output | CELL[55].OUT_BEL[26] |
| ICAP_OUT_TOP14 | output | CELL[55].OUT_BEL[28] |
| ICAP_OUT_TOP15 | output | CELL[55].OUT_BEL[30] |
| ICAP_OUT_TOP16 | output | CELL[56].OUT_BEL[0] |
| ICAP_OUT_TOP17 | output | CELL[56].OUT_BEL[2] |
| ICAP_OUT_TOP18 | output | CELL[56].OUT_BEL[4] |
| ICAP_OUT_TOP19 | output | CELL[56].OUT_BEL[6] |
| ICAP_OUT_TOP2 | output | CELL[55].OUT_BEL[4] |
| ICAP_OUT_TOP20 | output | CELL[56].OUT_BEL[8] |
| ICAP_OUT_TOP21 | output | CELL[56].OUT_BEL[10] |
| ICAP_OUT_TOP22 | output | CELL[56].OUT_BEL[12] |
| ICAP_OUT_TOP23 | output | CELL[56].OUT_BEL[14] |
| ICAP_OUT_TOP24 | output | CELL[56].OUT_BEL[16] |
| ICAP_OUT_TOP25 | output | CELL[56].OUT_BEL[18] |
| ICAP_OUT_TOP26 | output | CELL[56].OUT_BEL[20] |
| ICAP_OUT_TOP27 | output | CELL[56].OUT_BEL[22] |
| ICAP_OUT_TOP28 | output | CELL[56].OUT_BEL[24] |
| ICAP_OUT_TOP29 | output | CELL[56].OUT_BEL[26] |
| ICAP_OUT_TOP3 | output | CELL[55].OUT_BEL[6] |
| ICAP_OUT_TOP30 | output | CELL[56].OUT_BEL[28] |
| ICAP_OUT_TOP31 | output | CELL[56].OUT_BEL[30] |
| ICAP_OUT_TOP4 | output | CELL[55].OUT_BEL[8] |
| ICAP_OUT_TOP5 | output | CELL[55].OUT_BEL[10] |
| ICAP_OUT_TOP6 | output | CELL[55].OUT_BEL[12] |
| ICAP_OUT_TOP7 | output | CELL[55].OUT_BEL[14] |
| ICAP_OUT_TOP8 | output | CELL[55].OUT_BEL[16] |
| ICAP_OUT_TOP9 | output | CELL[55].OUT_BEL[18] |
| ICAP_PR_DONE_BOT | output | CELL[43].OUT_BEL[0] |
| ICAP_PR_DONE_TOP | output | CELL[54].OUT_BEL[0] |
| ICAP_PR_ERROR_BOT | output | CELL[43].OUT_BEL[2] |
| ICAP_PR_ERROR_TOP | output | CELL[54].OUT_BEL[2] |
| ICAP_RDWR_B_BOT | input | CELL[43].IMUX_IMUX_DELAY[0] |
| ICAP_RDWR_B_TOP | input | CELL[54].IMUX_IMUX_DELAY[0] |
| IOX_CCLK | output | CELL[50].OUT_BEL[0] |
| IOX_CFGDATA0 | output | CELL[48].OUT_BEL[0] |
| IOX_CFGDATA1 | output | CELL[48].OUT_BEL[2] |
| IOX_CFGDATA10 | output | CELL[48].OUT_BEL[20] |
| IOX_CFGDATA11 | output | CELL[48].OUT_BEL[22] |
| IOX_CFGDATA12 | output | CELL[48].OUT_BEL[24] |
| IOX_CFGDATA13 | output | CELL[48].OUT_BEL[26] |
| IOX_CFGDATA14 | output | CELL[48].OUT_BEL[28] |
| IOX_CFGDATA15 | output | CELL[48].OUT_BEL[30] |
| IOX_CFGDATA16 | output | CELL[49].OUT_BEL[0] |
| IOX_CFGDATA17 | output | CELL[49].OUT_BEL[2] |
| IOX_CFGDATA18 | output | CELL[49].OUT_BEL[4] |
| IOX_CFGDATA19 | output | CELL[49].OUT_BEL[6] |
| IOX_CFGDATA2 | output | CELL[48].OUT_BEL[4] |
| IOX_CFGDATA20 | output | CELL[49].OUT_BEL[8] |
| IOX_CFGDATA21 | output | CELL[49].OUT_BEL[10] |
| IOX_CFGDATA22 | output | CELL[49].OUT_BEL[12] |
| IOX_CFGDATA23 | output | CELL[49].OUT_BEL[14] |
| IOX_CFGDATA24 | output | CELL[49].OUT_BEL[16] |
| IOX_CFGDATA25 | output | CELL[49].OUT_BEL[18] |
| IOX_CFGDATA26 | output | CELL[49].OUT_BEL[20] |
| IOX_CFGDATA27 | output | CELL[49].OUT_BEL[22] |
| IOX_CFGDATA28 | output | CELL[49].OUT_BEL[24] |
| IOX_CFGDATA29 | output | CELL[49].OUT_BEL[26] |
| IOX_CFGDATA3 | output | CELL[48].OUT_BEL[6] |
| IOX_CFGDATA30 | output | CELL[49].OUT_BEL[28] |
| IOX_CFGDATA31 | output | CELL[49].OUT_BEL[30] |
| IOX_CFGDATA4 | output | CELL[48].OUT_BEL[8] |
| IOX_CFGDATA5 | output | CELL[48].OUT_BEL[10] |
| IOX_CFGDATA6 | output | CELL[48].OUT_BEL[12] |
| IOX_CFGDATA7 | output | CELL[48].OUT_BEL[14] |
| IOX_CFGDATA8 | output | CELL[48].OUT_BEL[16] |
| IOX_CFGDATA9 | output | CELL[48].OUT_BEL[18] |
| IOX_CFGMASTER | output | CELL[50].OUT_BEL[2] |
| IOX_INITBI | output | CELL[50].OUT_BEL[6] |
| IOX_INITBO | input | CELL[48].IMUX_IMUX_DELAY[1] |
| IOX_MODE0 | output | CELL[50].OUT_BEL[12] |
| IOX_MODE1 | output | CELL[50].OUT_BEL[14] |
| IOX_MODE2 | output | CELL[50].OUT_BEL[16] |
| IOX_PUDCB | output | CELL[50].OUT_BEL[8] |
| IOX_RDWRB | output | CELL[50].OUT_BEL[10] |
| IOX_TDO | input | CELL[48].IMUX_IMUX_DELAY[0] |
| IOX_VGG_COMP_OUT | output | CELL[50].OUT_BEL[4] |
| KEY_CLEAR_B | input | CELL[47].IMUX_IMUX_DELAY[0] |
| PROG_ACK | input | CELL[47].IMUX_IMUX_DELAY[1] |
| PROG_REQ | output | CELL[47].OUT_BEL[8] |
| RBCRC_ERROR | output | CELL[51].OUT_BEL[20] |
| RDATA0 | output | CELL[31].OUT_BEL[24] |
| RDATA1 | output | CELL[31].OUT_BEL[26] |
| RDATA10 | output | CELL[32].OUT_BEL[12] |
| RDATA11 | output | CELL[32].OUT_BEL[14] |
| RDATA12 | output | CELL[32].OUT_BEL[16] |
| RDATA13 | output | CELL[32].OUT_BEL[18] |
| RDATA14 | output | CELL[32].OUT_BEL[20] |
| RDATA15 | output | CELL[32].OUT_BEL[22] |
| RDATA16 | output | CELL[32].OUT_BEL[24] |
| RDATA17 | output | CELL[32].OUT_BEL[26] |
| RDATA18 | output | CELL[32].OUT_BEL[28] |
| RDATA19 | output | CELL[32].OUT_BEL[30] |
| RDATA2 | output | CELL[31].OUT_BEL[28] |
| RDATA20 | output | CELL[33].OUT_BEL[0] |
| RDATA21 | output | CELL[33].OUT_BEL[2] |
| RDATA22 | output | CELL[33].OUT_BEL[4] |
| RDATA23 | output | CELL[33].OUT_BEL[6] |
| RDATA24 | output | CELL[33].OUT_BEL[8] |
| RDATA25 | output | CELL[33].OUT_BEL[10] |
| RDATA26 | output | CELL[33].OUT_BEL[12] |
| RDATA27 | output | CELL[33].OUT_BEL[14] |
| RDATA28 | output | CELL[33].OUT_BEL[16] |
| RDATA29 | output | CELL[33].OUT_BEL[18] |
| RDATA3 | output | CELL[31].OUT_BEL[30] |
| RDATA30 | output | CELL[33].OUT_BEL[20] |
| RDATA31 | output | CELL[33].OUT_BEL[22] |
| RDATA4 | output | CELL[32].OUT_BEL[0] |
| RDATA5 | output | CELL[32].OUT_BEL[2] |
| RDATA6 | output | CELL[32].OUT_BEL[4] |
| RDATA7 | output | CELL[32].OUT_BEL[6] |
| RDATA8 | output | CELL[32].OUT_BEL[8] |
| RDATA9 | output | CELL[32].OUT_BEL[10] |
| RID0 | output | CELL[31].OUT_BEL[4] |
| RID1 | output | CELL[31].OUT_BEL[6] |
| RID2 | output | CELL[31].OUT_BEL[8] |
| RID3 | output | CELL[31].OUT_BEL[10] |
| RID4 | output | CELL[31].OUT_BEL[12] |
| RID5 | output | CELL[31].OUT_BEL[14] |
| RID6 | output | CELL[31].OUT_BEL[16] |
| RID7 | output | CELL[31].OUT_BEL[18] |
| RLAST | output | CELL[31].OUT_BEL[2] |
| RREADY | input | CELL[31].IMUX_IMUX_DELAY[0] |
| RRESP0 | output | CELL[31].OUT_BEL[20] |
| RRESP1 | output | CELL[31].OUT_BEL[22] |
| RVALID | output | CELL[31].OUT_BEL[0] |
| START_CFG_CLK | output | CELL[47].OUT_BEL[14] |
| START_CFG_MCLK | output | CELL[47].OUT_BEL[12] |
| USR_ACCESS_CLK | output | CELL[57].OUT_BEL[2] |
| USR_ACCESS_DATA0 | output | CELL[58].OUT_BEL[0] |
| USR_ACCESS_DATA1 | output | CELL[58].OUT_BEL[2] |
| USR_ACCESS_DATA10 | output | CELL[58].OUT_BEL[20] |
| USR_ACCESS_DATA11 | output | CELL[58].OUT_BEL[22] |
| USR_ACCESS_DATA12 | output | CELL[58].OUT_BEL[24] |
| USR_ACCESS_DATA13 | output | CELL[58].OUT_BEL[26] |
| USR_ACCESS_DATA14 | output | CELL[58].OUT_BEL[28] |
| USR_ACCESS_DATA15 | output | CELL[58].OUT_BEL[30] |
| USR_ACCESS_DATA16 | output | CELL[59].OUT_BEL[0] |
| USR_ACCESS_DATA17 | output | CELL[59].OUT_BEL[2] |
| USR_ACCESS_DATA18 | output | CELL[59].OUT_BEL[4] |
| USR_ACCESS_DATA19 | output | CELL[59].OUT_BEL[6] |
| USR_ACCESS_DATA2 | output | CELL[58].OUT_BEL[4] |
| USR_ACCESS_DATA20 | output | CELL[59].OUT_BEL[8] |
| USR_ACCESS_DATA21 | output | CELL[59].OUT_BEL[10] |
| USR_ACCESS_DATA22 | output | CELL[59].OUT_BEL[12] |
| USR_ACCESS_DATA23 | output | CELL[59].OUT_BEL[14] |
| USR_ACCESS_DATA24 | output | CELL[59].OUT_BEL[16] |
| USR_ACCESS_DATA25 | output | CELL[59].OUT_BEL[18] |
| USR_ACCESS_DATA26 | output | CELL[59].OUT_BEL[20] |
| USR_ACCESS_DATA27 | output | CELL[59].OUT_BEL[22] |
| USR_ACCESS_DATA28 | output | CELL[59].OUT_BEL[24] |
| USR_ACCESS_DATA29 | output | CELL[59].OUT_BEL[26] |
| USR_ACCESS_DATA3 | output | CELL[58].OUT_BEL[6] |
| USR_ACCESS_DATA30 | output | CELL[59].OUT_BEL[28] |
| USR_ACCESS_DATA31 | output | CELL[59].OUT_BEL[30] |
| USR_ACCESS_DATA4 | output | CELL[58].OUT_BEL[8] |
| USR_ACCESS_DATA5 | output | CELL[58].OUT_BEL[10] |
| USR_ACCESS_DATA6 | output | CELL[58].OUT_BEL[12] |
| USR_ACCESS_DATA7 | output | CELL[58].OUT_BEL[14] |
| USR_ACCESS_DATA8 | output | CELL[58].OUT_BEL[16] |
| USR_ACCESS_DATA9 | output | CELL[58].OUT_BEL[18] |
| USR_ACCESS_VALID | output | CELL[57].OUT_BEL[0] |
| USR_CCLK_O | input | CELL[47].IMUX_CTRL[0] |
| USR_CCLK_TS | input | CELL[47].IMUX_IMUX_DELAY[2] |
| USR_DNA_CLK | input | CELL[42].IMUX_CTRL[0] |
| USR_DNA_DIN | input | CELL[42].IMUX_IMUX_DELAY[0] |
| USR_DNA_OUT | output | CELL[42].OUT_BEL[0] |
| USR_DNA_READ | input | CELL[42].IMUX_IMUX_DELAY[1] |
| USR_DNA_SHIFT | input | CELL[42].IMUX_IMUX_DELAY[2] |
| USR_DONE_O | input | CELL[47].IMUX_IMUX_DELAY[3] |
| USR_DONE_TS | input | CELL[47].IMUX_IMUX_DELAY[4] |
| USR_D_O_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[9] |
| USR_D_O_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[10] |
| USR_D_O_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[11] |
| USR_D_O_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[12] |
| USR_D_PIN_CFGIO0 | output | CELL[47].OUT_BEL[0] |
| USR_D_PIN_CFGIO1 | output | CELL[47].OUT_BEL[2] |
| USR_D_PIN_CFGIO2 | output | CELL[47].OUT_BEL[4] |
| USR_D_PIN_CFGIO3 | output | CELL[47].OUT_BEL[6] |
| USR_D_TS_CFGIO0 | input | CELL[47].IMUX_IMUX_DELAY[13] |
| USR_D_TS_CFGIO1 | input | CELL[47].IMUX_IMUX_DELAY[14] |
| USR_D_TS_CFGIO2 | input | CELL[47].IMUX_IMUX_DELAY[15] |
| USR_D_TS_CFGIO3 | input | CELL[47].IMUX_IMUX_DELAY[16] |
| USR_EFUSE0 | output | CELL[46].OUT_BEL[0] |
| USR_EFUSE1 | output | CELL[46].OUT_BEL[2] |
| USR_EFUSE10 | output | CELL[46].OUT_BEL[20] |
| USR_EFUSE11 | output | CELL[46].OUT_BEL[22] |
| USR_EFUSE12 | output | CELL[46].OUT_BEL[24] |
| USR_EFUSE13 | output | CELL[46].OUT_BEL[26] |
| USR_EFUSE14 | output | CELL[46].OUT_BEL[28] |
| USR_EFUSE15 | output | CELL[46].OUT_BEL[30] |
| USR_EFUSE16 | output | CELL[41].OUT_BEL[0] |
| USR_EFUSE17 | output | CELL[41].OUT_BEL[2] |
| USR_EFUSE18 | output | CELL[41].OUT_BEL[4] |
| USR_EFUSE19 | output | CELL[41].OUT_BEL[6] |
| USR_EFUSE2 | output | CELL[46].OUT_BEL[4] |
| USR_EFUSE20 | output | CELL[41].OUT_BEL[8] |
| USR_EFUSE21 | output | CELL[41].OUT_BEL[10] |
| USR_EFUSE22 | output | CELL[41].OUT_BEL[12] |
| USR_EFUSE23 | output | CELL[41].OUT_BEL[14] |
| USR_EFUSE24 | output | CELL[41].OUT_BEL[16] |
| USR_EFUSE25 | output | CELL[41].OUT_BEL[18] |
| USR_EFUSE26 | output | CELL[41].OUT_BEL[20] |
| USR_EFUSE27 | output | CELL[41].OUT_BEL[22] |
| USR_EFUSE28 | output | CELL[41].OUT_BEL[24] |
| USR_EFUSE29 | output | CELL[41].OUT_BEL[26] |
| USR_EFUSE3 | output | CELL[46].OUT_BEL[6] |
| USR_EFUSE30 | output | CELL[41].OUT_BEL[28] |
| USR_EFUSE31 | output | CELL[41].OUT_BEL[30] |
| USR_EFUSE4 | output | CELL[46].OUT_BEL[8] |
| USR_EFUSE5 | output | CELL[46].OUT_BEL[10] |
| USR_EFUSE6 | output | CELL[46].OUT_BEL[12] |
| USR_EFUSE7 | output | CELL[46].OUT_BEL[14] |
| USR_EFUSE8 | output | CELL[46].OUT_BEL[16] |
| USR_EFUSE9 | output | CELL[46].OUT_BEL[18] |
| USR_FCS_B_O | input | CELL[47].IMUX_IMUX_DELAY[7] |
| USR_FCS_B_TS | input | CELL[47].IMUX_IMUX_DELAY[8] |
| USR_GSR | input | CELL[47].IMUX_IMUX_DELAY[5] |
| USR_GTS | input | CELL[47].IMUX_IMUX_DELAY[6] |
| USR_TCK | input | CELL[43].IMUX_CTRL[1] |
| USR_TDI | input | CELL[43].IMUX_IMUX_DELAY[6] |
| USR_TDO | output | CELL[43].OUT_BEL[18] |
| USR_TMS | input | CELL[43].IMUX_IMUX_DELAY[5] |
| WDATA0 | input | CELL[28].IMUX_IMUX_DELAY[10] |
| WDATA1 | input | CELL[28].IMUX_IMUX_DELAY[11] |
| WDATA10 | input | CELL[29].IMUX_IMUX_DELAY[4] |
| WDATA11 | input | CELL[29].IMUX_IMUX_DELAY[5] |
| WDATA12 | input | CELL[29].IMUX_IMUX_DELAY[6] |
| WDATA13 | input | CELL[29].IMUX_IMUX_DELAY[7] |
| WDATA14 | input | CELL[29].IMUX_IMUX_DELAY[8] |
| WDATA15 | input | CELL[29].IMUX_IMUX_DELAY[9] |
| WDATA16 | input | CELL[29].IMUX_IMUX_DELAY[10] |
| WDATA17 | input | CELL[29].IMUX_IMUX_DELAY[11] |
| WDATA18 | input | CELL[29].IMUX_IMUX_DELAY[12] |
| WDATA19 | input | CELL[29].IMUX_IMUX_DELAY[13] |
| WDATA2 | input | CELL[28].IMUX_IMUX_DELAY[12] |
| WDATA20 | input | CELL[29].IMUX_IMUX_DELAY[14] |
| WDATA21 | input | CELL[29].IMUX_IMUX_DELAY[15] |
| WDATA22 | input | CELL[30].IMUX_IMUX_DELAY[0] |
| WDATA23 | input | CELL[30].IMUX_IMUX_DELAY[1] |
| WDATA24 | input | CELL[30].IMUX_IMUX_DELAY[2] |
| WDATA25 | input | CELL[30].IMUX_IMUX_DELAY[3] |
| WDATA26 | input | CELL[30].IMUX_IMUX_DELAY[4] |
| WDATA27 | input | CELL[30].IMUX_IMUX_DELAY[5] |
| WDATA28 | input | CELL[30].IMUX_IMUX_DELAY[6] |
| WDATA29 | input | CELL[30].IMUX_IMUX_DELAY[7] |
| WDATA3 | input | CELL[28].IMUX_IMUX_DELAY[13] |
| WDATA30 | input | CELL[30].IMUX_IMUX_DELAY[8] |
| WDATA31 | input | CELL[30].IMUX_IMUX_DELAY[9] |
| WDATA4 | input | CELL[28].IMUX_IMUX_DELAY[14] |
| WDATA5 | input | CELL[28].IMUX_IMUX_DELAY[15] |
| WDATA6 | input | CELL[29].IMUX_IMUX_DELAY[0] |
| WDATA7 | input | CELL[29].IMUX_IMUX_DELAY[1] |
| WDATA8 | input | CELL[29].IMUX_IMUX_DELAY[2] |
| WDATA9 | input | CELL[29].IMUX_IMUX_DELAY[3] |
| WID0 | input | CELL[28].IMUX_IMUX_DELAY[2] |
| WID1 | input | CELL[28].IMUX_IMUX_DELAY[3] |
| WID2 | input | CELL[28].IMUX_IMUX_DELAY[4] |
| WID3 | input | CELL[28].IMUX_IMUX_DELAY[5] |
| WID4 | input | CELL[28].IMUX_IMUX_DELAY[6] |
| WID5 | input | CELL[28].IMUX_IMUX_DELAY[7] |
| WID6 | input | CELL[28].IMUX_IMUX_DELAY[8] |
| WID7 | input | CELL[28].IMUX_IMUX_DELAY[9] |
| WLAST | input | CELL[28].IMUX_IMUX_DELAY[1] |
| WREADY | output | CELL[28].OUT_BEL[0] |
| WSTRB0 | input | CELL[30].IMUX_IMUX_DELAY[10] |
| WSTRB1 | input | CELL[30].IMUX_IMUX_DELAY[11] |
| WSTRB2 | input | CELL[30].IMUX_IMUX_DELAY[12] |
| WSTRB3 | input | CELL[30].IMUX_IMUX_DELAY[13] |
| WVALID | input | CELL[28].IMUX_IMUX_DELAY[0] |
Bel ABUS_SWITCH_CFG
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| CELL[20].OUT_BEL[0] | CFG.ARREADY |
| CELL[20].IMUX_CTRL[0] | CFG.AXI_CLK |
| CELL[20].IMUX_IMUX_DELAY[0] | CFG.ARVALID |
| CELL[20].IMUX_IMUX_DELAY[3] | CFG.ARADDR22 |
| CELL[20].IMUX_IMUX_DELAY[4] | CFG.ARADDR23 |
| CELL[20].IMUX_IMUX_DELAY[5] | CFG.ARADDR24 |
| CELL[20].IMUX_IMUX_DELAY[6] | CFG.ARADDR25 |
| CELL[20].IMUX_IMUX_DELAY[7] | CFG.ARADDR26 |
| CELL[20].IMUX_IMUX_DELAY[8] | CFG.ARADDR27 |
| CELL[20].IMUX_IMUX_DELAY[9] | CFG.ARADDR0 |
| CELL[20].IMUX_IMUX_DELAY[10] | CFG.ARADDR1 |
| CELL[20].IMUX_IMUX_DELAY[11] | CFG.ARADDR2 |
| CELL[20].IMUX_IMUX_DELAY[12] | CFG.ARADDR3 |
| CELL[20].IMUX_IMUX_DELAY[13] | CFG.ARADDR4 |
| CELL[20].IMUX_IMUX_DELAY[14] | CFG.ARADDR5 |
| CELL[20].IMUX_IMUX_DELAY[15] | CFG.ARADDR6 |
| CELL[21].IMUX_IMUX_DELAY[0] | CFG.ARADDR7 |
| CELL[21].IMUX_IMUX_DELAY[1] | CFG.ARADDR8 |
| CELL[21].IMUX_IMUX_DELAY[2] | CFG.ARADDR9 |
| CELL[21].IMUX_IMUX_DELAY[3] | CFG.ARADDR10 |
| CELL[21].IMUX_IMUX_DELAY[4] | CFG.ARADDR11 |
| CELL[21].IMUX_IMUX_DELAY[5] | CFG.ARADDR12 |
| CELL[21].IMUX_IMUX_DELAY[6] | CFG.ARADDR13 |
| CELL[21].IMUX_IMUX_DELAY[7] | CFG.ARADDR14 |
| CELL[21].IMUX_IMUX_DELAY[8] | CFG.ARADDR15 |
| CELL[21].IMUX_IMUX_DELAY[9] | CFG.ARADDR16 |
| CELL[21].IMUX_IMUX_DELAY[10] | CFG.ARADDR17 |
| CELL[21].IMUX_IMUX_DELAY[11] | CFG.ARADDR18 |
| CELL[21].IMUX_IMUX_DELAY[12] | CFG.ARADDR19 |
| CELL[21].IMUX_IMUX_DELAY[13] | CFG.ARADDR20 |
| CELL[21].IMUX_IMUX_DELAY[14] | CFG.ARADDR21 |
| CELL[21].IMUX_IMUX_DELAY[15] | CFG.ARLEN0 |
| CELL[22].IMUX_IMUX_DELAY[0] | CFG.ARLEN1 |
| CELL[22].IMUX_IMUX_DELAY[1] | CFG.ARLEN2 |
| CELL[22].IMUX_IMUX_DELAY[2] | CFG.ARLEN3 |
| CELL[22].IMUX_IMUX_DELAY[3] | CFG.ARSIZE0 |
| CELL[22].IMUX_IMUX_DELAY[4] | CFG.ARSIZE1 |
| CELL[22].IMUX_IMUX_DELAY[5] | CFG.ARSIZE2 |
| CELL[22].IMUX_IMUX_DELAY[6] | CFG.ARBURST0 |
| CELL[22].IMUX_IMUX_DELAY[7] | CFG.ARBURST1 |
| CELL[22].IMUX_IMUX_DELAY[8] | CFG.ARLOCK |
| CELL[22].IMUX_IMUX_DELAY[9] | CFG.ARCACHE0 |
| CELL[22].IMUX_IMUX_DELAY[10] | CFG.ARCACHE1 |
| CELL[22].IMUX_IMUX_DELAY[11] | CFG.ARCACHE2 |
| CELL[22].IMUX_IMUX_DELAY[12] | CFG.ARCACHE3 |
| CELL[22].IMUX_IMUX_DELAY[13] | CFG.ARPROT0 |
| CELL[22].IMUX_IMUX_DELAY[14] | CFG.ARPROT1 |
| CELL[22].IMUX_IMUX_DELAY[15] | CFG.ARPROT2 |
| CELL[23].IMUX_IMUX_DELAY[0] | CFG.ARQOS0 |
| CELL[23].IMUX_IMUX_DELAY[1] | CFG.ARQOS1 |
| CELL[23].IMUX_IMUX_DELAY[2] | CFG.ARQOS2 |
| CELL[23].IMUX_IMUX_DELAY[3] | CFG.ARQOS3 |
| CELL[24].OUT_BEL[0] | CFG.AWREADY |
| CELL[24].IMUX_IMUX_DELAY[0] | CFG.AWVALID |
| CELL[24].IMUX_IMUX_DELAY[3] | CFG.AWADDR22 |
| CELL[24].IMUX_IMUX_DELAY[4] | CFG.AWADDR23 |
| CELL[24].IMUX_IMUX_DELAY[5] | CFG.AWADDR24 |
| CELL[24].IMUX_IMUX_DELAY[6] | CFG.AWADDR25 |
| CELL[24].IMUX_IMUX_DELAY[7] | CFG.AWADDR26 |
| CELL[24].IMUX_IMUX_DELAY[8] | CFG.AWADDR27 |
| CELL[24].IMUX_IMUX_DELAY[9] | CFG.AWADDR0 |
| CELL[24].IMUX_IMUX_DELAY[10] | CFG.AWADDR1 |
| CELL[24].IMUX_IMUX_DELAY[11] | CFG.AWADDR2 |
| CELL[24].IMUX_IMUX_DELAY[12] | CFG.AWADDR3 |
| CELL[24].IMUX_IMUX_DELAY[13] | CFG.AWADDR4 |
| CELL[24].IMUX_IMUX_DELAY[14] | CFG.AWADDR5 |
| CELL[24].IMUX_IMUX_DELAY[15] | CFG.AWADDR6 |
| CELL[25].IMUX_IMUX_DELAY[0] | CFG.AWADDR7 |
| CELL[25].IMUX_IMUX_DELAY[1] | CFG.AWADDR8 |
| CELL[25].IMUX_IMUX_DELAY[2] | CFG.AWADDR9 |
| CELL[25].IMUX_IMUX_DELAY[3] | CFG.AWADDR10 |
| CELL[25].IMUX_IMUX_DELAY[4] | CFG.AWADDR11 |
| CELL[25].IMUX_IMUX_DELAY[5] | CFG.AWADDR12 |
| CELL[25].IMUX_IMUX_DELAY[6] | CFG.AWADDR13 |
| CELL[25].IMUX_IMUX_DELAY[7] | CFG.AWADDR14 |
| CELL[25].IMUX_IMUX_DELAY[8] | CFG.AWADDR15 |
| CELL[25].IMUX_IMUX_DELAY[9] | CFG.AWADDR16 |
| CELL[25].IMUX_IMUX_DELAY[10] | CFG.AWADDR17 |
| CELL[25].IMUX_IMUX_DELAY[11] | CFG.AWADDR18 |
| CELL[25].IMUX_IMUX_DELAY[12] | CFG.AWADDR19 |
| CELL[25].IMUX_IMUX_DELAY[13] | CFG.AWADDR20 |
| CELL[25].IMUX_IMUX_DELAY[14] | CFG.AWADDR21 |
| CELL[25].IMUX_IMUX_DELAY[15] | CFG.AWLEN0 |
| CELL[26].IMUX_IMUX_DELAY[0] | CFG.AWLEN1 |
| CELL[26].IMUX_IMUX_DELAY[1] | CFG.AWLEN2 |
| CELL[26].IMUX_IMUX_DELAY[2] | CFG.AWLEN3 |
| CELL[26].IMUX_IMUX_DELAY[3] | CFG.AWSIZE0 |
| CELL[26].IMUX_IMUX_DELAY[4] | CFG.AWSIZE1 |
| CELL[26].IMUX_IMUX_DELAY[5] | CFG.AWSIZE2 |
| CELL[26].IMUX_IMUX_DELAY[6] | CFG.AWBURST0 |
| CELL[26].IMUX_IMUX_DELAY[7] | CFG.AWBURST1 |
| CELL[26].IMUX_IMUX_DELAY[8] | CFG.AWLOCK |
| CELL[26].IMUX_IMUX_DELAY[9] | CFG.AWCACHE0 |
| CELL[26].IMUX_IMUX_DELAY[10] | CFG.AWCACHE1 |
| CELL[26].IMUX_IMUX_DELAY[11] | CFG.AWCACHE2 |
| CELL[26].IMUX_IMUX_DELAY[12] | CFG.AWCACHE3 |
| CELL[26].IMUX_IMUX_DELAY[13] | CFG.AWPROT0 |
| CELL[26].IMUX_IMUX_DELAY[14] | CFG.AWPROT1 |
| CELL[26].IMUX_IMUX_DELAY[15] | CFG.AWPROT2 |
| CELL[27].IMUX_IMUX_DELAY[0] | CFG.AWQOS0 |
| CELL[27].IMUX_IMUX_DELAY[1] | CFG.AWQOS1 |
| CELL[27].IMUX_IMUX_DELAY[2] | CFG.AWQOS2 |
| CELL[27].IMUX_IMUX_DELAY[3] | CFG.AWQOS3 |
| CELL[28].OUT_BEL[0] | CFG.WREADY |
| CELL[28].IMUX_IMUX_DELAY[0] | CFG.WVALID |
| CELL[28].IMUX_IMUX_DELAY[1] | CFG.WLAST |
| CELL[28].IMUX_IMUX_DELAY[2] | CFG.WID0 |
| CELL[28].IMUX_IMUX_DELAY[3] | CFG.WID1 |
| CELL[28].IMUX_IMUX_DELAY[4] | CFG.WID2 |
| CELL[28].IMUX_IMUX_DELAY[5] | CFG.WID3 |
| CELL[28].IMUX_IMUX_DELAY[6] | CFG.WID4 |
| CELL[28].IMUX_IMUX_DELAY[7] | CFG.WID5 |
| CELL[28].IMUX_IMUX_DELAY[8] | CFG.WID6 |
| CELL[28].IMUX_IMUX_DELAY[9] | CFG.WID7 |
| CELL[28].IMUX_IMUX_DELAY[10] | CFG.WDATA0 |
| CELL[28].IMUX_IMUX_DELAY[11] | CFG.WDATA1 |
| CELL[28].IMUX_IMUX_DELAY[12] | CFG.WDATA2 |
| CELL[28].IMUX_IMUX_DELAY[13] | CFG.WDATA3 |
| CELL[28].IMUX_IMUX_DELAY[14] | CFG.WDATA4 |
| CELL[28].IMUX_IMUX_DELAY[15] | CFG.WDATA5 |
| CELL[29].IMUX_IMUX_DELAY[0] | CFG.WDATA6 |
| CELL[29].IMUX_IMUX_DELAY[1] | CFG.WDATA7 |
| CELL[29].IMUX_IMUX_DELAY[2] | CFG.WDATA8 |
| CELL[29].IMUX_IMUX_DELAY[3] | CFG.WDATA9 |
| CELL[29].IMUX_IMUX_DELAY[4] | CFG.WDATA10 |
| CELL[29].IMUX_IMUX_DELAY[5] | CFG.WDATA11 |
| CELL[29].IMUX_IMUX_DELAY[6] | CFG.WDATA12 |
| CELL[29].IMUX_IMUX_DELAY[7] | CFG.WDATA13 |
| CELL[29].IMUX_IMUX_DELAY[8] | CFG.WDATA14 |
| CELL[29].IMUX_IMUX_DELAY[9] | CFG.WDATA15 |
| CELL[29].IMUX_IMUX_DELAY[10] | CFG.WDATA16 |
| CELL[29].IMUX_IMUX_DELAY[11] | CFG.WDATA17 |
| CELL[29].IMUX_IMUX_DELAY[12] | CFG.WDATA18 |
| CELL[29].IMUX_IMUX_DELAY[13] | CFG.WDATA19 |
| CELL[29].IMUX_IMUX_DELAY[14] | CFG.WDATA20 |
| CELL[29].IMUX_IMUX_DELAY[15] | CFG.WDATA21 |
| CELL[30].IMUX_IMUX_DELAY[0] | CFG.WDATA22 |
| CELL[30].IMUX_IMUX_DELAY[1] | CFG.WDATA23 |
| CELL[30].IMUX_IMUX_DELAY[2] | CFG.WDATA24 |
| CELL[30].IMUX_IMUX_DELAY[3] | CFG.WDATA25 |
| CELL[30].IMUX_IMUX_DELAY[4] | CFG.WDATA26 |
| CELL[30].IMUX_IMUX_DELAY[5] | CFG.WDATA27 |
| CELL[30].IMUX_IMUX_DELAY[6] | CFG.WDATA28 |
| CELL[30].IMUX_IMUX_DELAY[7] | CFG.WDATA29 |
| CELL[30].IMUX_IMUX_DELAY[8] | CFG.WDATA30 |
| CELL[30].IMUX_IMUX_DELAY[9] | CFG.WDATA31 |
| CELL[30].IMUX_IMUX_DELAY[10] | CFG.WSTRB0 |
| CELL[30].IMUX_IMUX_DELAY[11] | CFG.WSTRB1 |
| CELL[30].IMUX_IMUX_DELAY[12] | CFG.WSTRB2 |
| CELL[30].IMUX_IMUX_DELAY[13] | CFG.WSTRB3 |
| CELL[31].OUT_BEL[0] | CFG.RVALID |
| CELL[31].OUT_BEL[2] | CFG.RLAST |
| CELL[31].OUT_BEL[4] | CFG.RID0 |
| CELL[31].OUT_BEL[6] | CFG.RID1 |
| CELL[31].OUT_BEL[8] | CFG.RID2 |
| CELL[31].OUT_BEL[10] | CFG.RID3 |
| CELL[31].OUT_BEL[12] | CFG.RID4 |
| CELL[31].OUT_BEL[14] | CFG.RID5 |
| CELL[31].OUT_BEL[16] | CFG.RID6 |
| CELL[31].OUT_BEL[18] | CFG.RID7 |
| CELL[31].OUT_BEL[20] | CFG.RRESP0 |
| CELL[31].OUT_BEL[22] | CFG.RRESP1 |
| CELL[31].OUT_BEL[24] | CFG.RDATA0 |
| CELL[31].OUT_BEL[26] | CFG.RDATA1 |
| CELL[31].OUT_BEL[28] | CFG.RDATA2 |
| CELL[31].OUT_BEL[30] | CFG.RDATA3 |
| CELL[31].IMUX_IMUX_DELAY[0] | CFG.RREADY |
| CELL[31].IMUX_IMUX_DELAY[1] | CFG.ARID0 |
| CELL[31].IMUX_IMUX_DELAY[2] | CFG.ARID1 |
| CELL[31].IMUX_IMUX_DELAY[3] | CFG.ARID2 |
| CELL[31].IMUX_IMUX_DELAY[4] | CFG.ARID3 |
| CELL[31].IMUX_IMUX_DELAY[5] | CFG.ARID4 |
| CELL[31].IMUX_IMUX_DELAY[6] | CFG.ARID5 |
| CELL[31].IMUX_IMUX_DELAY[7] | CFG.ARID6 |
| CELL[31].IMUX_IMUX_DELAY[8] | CFG.ARID7 |
| CELL[32].OUT_BEL[0] | CFG.RDATA4 |
| CELL[32].OUT_BEL[2] | CFG.RDATA5 |
| CELL[32].OUT_BEL[4] | CFG.RDATA6 |
| CELL[32].OUT_BEL[6] | CFG.RDATA7 |
| CELL[32].OUT_BEL[8] | CFG.RDATA8 |
| CELL[32].OUT_BEL[10] | CFG.RDATA9 |
| CELL[32].OUT_BEL[12] | CFG.RDATA10 |
| CELL[32].OUT_BEL[14] | CFG.RDATA11 |
| CELL[32].OUT_BEL[16] | CFG.RDATA12 |
| CELL[32].OUT_BEL[18] | CFG.RDATA13 |
| CELL[32].OUT_BEL[20] | CFG.RDATA14 |
| CELL[32].OUT_BEL[22] | CFG.RDATA15 |
| CELL[32].OUT_BEL[24] | CFG.RDATA16 |
| CELL[32].OUT_BEL[26] | CFG.RDATA17 |
| CELL[32].OUT_BEL[28] | CFG.RDATA18 |
| CELL[32].OUT_BEL[30] | CFG.RDATA19 |
| CELL[32].IMUX_IMUX_DELAY[1] | CFG.AWID0 |
| CELL[32].IMUX_IMUX_DELAY[2] | CFG.AWID1 |
| CELL[32].IMUX_IMUX_DELAY[3] | CFG.AWID2 |
| CELL[32].IMUX_IMUX_DELAY[4] | CFG.AWID3 |
| CELL[32].IMUX_IMUX_DELAY[5] | CFG.AWID4 |
| CELL[32].IMUX_IMUX_DELAY[6] | CFG.AWID5 |
| CELL[32].IMUX_IMUX_DELAY[7] | CFG.AWID6 |
| CELL[32].IMUX_IMUX_DELAY[8] | CFG.AWID7 |
| CELL[33].OUT_BEL[0] | CFG.RDATA20 |
| CELL[33].OUT_BEL[2] | CFG.RDATA21 |
| CELL[33].OUT_BEL[4] | CFG.RDATA22 |
| CELL[33].OUT_BEL[6] | CFG.RDATA23 |
| CELL[33].OUT_BEL[8] | CFG.RDATA24 |
| CELL[33].OUT_BEL[10] | CFG.RDATA25 |
| CELL[33].OUT_BEL[12] | CFG.RDATA26 |
| CELL[33].OUT_BEL[14] | CFG.RDATA27 |
| CELL[33].OUT_BEL[16] | CFG.RDATA28 |
| CELL[33].OUT_BEL[18] | CFG.RDATA29 |
| CELL[33].OUT_BEL[20] | CFG.RDATA30 |
| CELL[33].OUT_BEL[22] | CFG.RDATA31 |
| CELL[34].OUT_BEL[0] | CFG.BVALID |
| CELL[34].OUT_BEL[2] | CFG.BID0 |
| CELL[34].OUT_BEL[4] | CFG.BID1 |
| CELL[34].OUT_BEL[6] | CFG.BID2 |
| CELL[34].OUT_BEL[8] | CFG.BID3 |
| CELL[34].OUT_BEL[10] | CFG.BID4 |
| CELL[34].OUT_BEL[12] | CFG.BID5 |
| CELL[34].OUT_BEL[14] | CFG.BID6 |
| CELL[34].OUT_BEL[16] | CFG.BID7 |
| CELL[34].OUT_BEL[18] | CFG.BRESP0 |
| CELL[34].OUT_BEL[20] | CFG.BRESP1 |
| CELL[34].IMUX_IMUX_DELAY[0] | CFG.BREADY |
| CELL[41].OUT_BEL[0] | CFG.USR_EFUSE16 |
| CELL[41].OUT_BEL[2] | CFG.USR_EFUSE17 |
| CELL[41].OUT_BEL[4] | CFG.USR_EFUSE18 |
| CELL[41].OUT_BEL[6] | CFG.USR_EFUSE19 |
| CELL[41].OUT_BEL[8] | CFG.USR_EFUSE20 |
| CELL[41].OUT_BEL[10] | CFG.USR_EFUSE21 |
| CELL[41].OUT_BEL[12] | CFG.USR_EFUSE22 |
| CELL[41].OUT_BEL[14] | CFG.USR_EFUSE23 |
| CELL[41].OUT_BEL[16] | CFG.USR_EFUSE24 |
| CELL[41].OUT_BEL[18] | CFG.USR_EFUSE25 |
| CELL[41].OUT_BEL[20] | CFG.USR_EFUSE26 |
| CELL[41].OUT_BEL[22] | CFG.USR_EFUSE27 |
| CELL[41].OUT_BEL[24] | CFG.USR_EFUSE28 |
| CELL[41].OUT_BEL[26] | CFG.USR_EFUSE29 |
| CELL[41].OUT_BEL[28] | CFG.USR_EFUSE30 |
| CELL[41].OUT_BEL[30] | CFG.USR_EFUSE31 |
| CELL[42].OUT_BEL[0] | CFG.USR_DNA_OUT |
| CELL[42].OUT_BEL[2] | CFG.DCI_LOCK |
| CELL[42].OUT_BEL[4] | CFG.BSCAN_CDR1 |
| CELL[42].OUT_BEL[6] | CFG.BSCAN_CDR2 |
| CELL[42].OUT_BEL[8] | CFG.BSCAN_CLKDR1 |
| CELL[42].OUT_BEL[10] | CFG.BSCAN_CLKDR2 |
| CELL[42].OUT_BEL[12] | CFG.BSCAN_RTI1 |
| CELL[42].OUT_BEL[14] | CFG.BSCAN_RTI2 |
| CELL[42].OUT_BEL[16] | CFG.BSCAN_SDR1 |
| CELL[42].OUT_BEL[18] | CFG.BSCAN_SDR2 |
| CELL[42].OUT_BEL[20] | CFG.BSCAN_SEL1 |
| CELL[42].OUT_BEL[22] | CFG.BSCAN_SEL2 |
| CELL[42].OUT_BEL[24] | CFG.BSCAN_TLR1 |
| CELL[42].OUT_BEL[26] | CFG.BSCAN_TLR2 |
| CELL[42].OUT_BEL[28] | CFG.BSCAN_UDR1 |
| CELL[42].OUT_BEL[30] | CFG.BSCAN_UDR2 |
| CELL[42].IMUX_CTRL[0] | CFG.USR_DNA_CLK |
| CELL[42].IMUX_IMUX_DELAY[0] | CFG.USR_DNA_DIN |
| CELL[42].IMUX_IMUX_DELAY[1] | CFG.USR_DNA_READ |
| CELL[42].IMUX_IMUX_DELAY[2] | CFG.USR_DNA_SHIFT |
| CELL[42].IMUX_IMUX_DELAY[3] | CFG.DCI_USR_RESET_IN |
| CELL[43].OUT_BEL[0] | CFG.ICAP_PR_DONE_BOT |
| CELL[43].OUT_BEL[2] | CFG.ICAP_PR_ERROR_BOT |
| CELL[43].OUT_BEL[4] | CFG.ICAP_AVAIL_BOT |
| CELL[43].OUT_BEL[6] | CFG.BSCAN_TCK1 |
| CELL[43].OUT_BEL[8] | CFG.BSCAN_TCK2 |
| CELL[43].OUT_BEL[10] | CFG.BSCAN_TMS1 |
| CELL[43].OUT_BEL[12] | CFG.BSCAN_TMS2 |
| CELL[43].OUT_BEL[14] | CFG.BSCAN_TDI1 |
| CELL[43].OUT_BEL[16] | CFG.BSCAN_TDI2 |
| CELL[43].OUT_BEL[18] | CFG.USR_TDO |
| CELL[43].IMUX_CTRL[1] | CFG.USR_TCK |
| CELL[43].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_BOT |
| CELL[43].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO1 |
| CELL[43].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO2 |
| CELL[43].IMUX_IMUX_DELAY[5] | CFG.USR_TMS |
| CELL[43].IMUX_IMUX_DELAY[6] | CFG.USR_TDI |
| CELL[44].OUT_BEL[0] | CFG.ICAP_OUT_BOT0 |
| CELL[44].OUT_BEL[2] | CFG.ICAP_OUT_BOT1 |
| CELL[44].OUT_BEL[4] | CFG.ICAP_OUT_BOT2 |
| CELL[44].OUT_BEL[6] | CFG.ICAP_OUT_BOT3 |
| CELL[44].OUT_BEL[8] | CFG.ICAP_OUT_BOT4 |
| CELL[44].OUT_BEL[10] | CFG.ICAP_OUT_BOT5 |
| CELL[44].OUT_BEL[12] | CFG.ICAP_OUT_BOT6 |
| CELL[44].OUT_BEL[14] | CFG.ICAP_OUT_BOT7 |
| CELL[44].OUT_BEL[16] | CFG.ICAP_OUT_BOT8 |
| CELL[44].OUT_BEL[18] | CFG.ICAP_OUT_BOT9 |
| CELL[44].OUT_BEL[20] | CFG.ICAP_OUT_BOT10 |
| CELL[44].OUT_BEL[22] | CFG.ICAP_OUT_BOT11 |
| CELL[44].OUT_BEL[24] | CFG.ICAP_OUT_BOT12 |
| CELL[44].OUT_BEL[26] | CFG.ICAP_OUT_BOT13 |
| CELL[44].OUT_BEL[28] | CFG.ICAP_OUT_BOT14 |
| CELL[44].OUT_BEL[30] | CFG.ICAP_OUT_BOT15 |
| CELL[44].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT0 |
| CELL[44].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT1 |
| CELL[44].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT2 |
| CELL[44].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT3 |
| CELL[44].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT4 |
| CELL[44].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT5 |
| CELL[44].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT6 |
| CELL[44].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT7 |
| CELL[44].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT8 |
| CELL[44].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT9 |
| CELL[44].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT10 |
| CELL[44].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT11 |
| CELL[44].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT12 |
| CELL[44].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT13 |
| CELL[44].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT14 |
| CELL[44].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT15 |
| CELL[45].OUT_BEL[0] | CFG.ICAP_OUT_BOT16 |
| CELL[45].OUT_BEL[2] | CFG.ICAP_OUT_BOT17 |
| CELL[45].OUT_BEL[4] | CFG.ICAP_OUT_BOT18 |
| CELL[45].OUT_BEL[6] | CFG.ICAP_OUT_BOT19 |
| CELL[45].OUT_BEL[8] | CFG.ICAP_OUT_BOT20 |
| CELL[45].OUT_BEL[10] | CFG.ICAP_OUT_BOT21 |
| CELL[45].OUT_BEL[12] | CFG.ICAP_OUT_BOT22 |
| CELL[45].OUT_BEL[14] | CFG.ICAP_OUT_BOT23 |
| CELL[45].OUT_BEL[16] | CFG.ICAP_OUT_BOT24 |
| CELL[45].OUT_BEL[18] | CFG.ICAP_OUT_BOT25 |
| CELL[45].OUT_BEL[20] | CFG.ICAP_OUT_BOT26 |
| CELL[45].OUT_BEL[22] | CFG.ICAP_OUT_BOT27 |
| CELL[45].OUT_BEL[24] | CFG.ICAP_OUT_BOT28 |
| CELL[45].OUT_BEL[26] | CFG.ICAP_OUT_BOT29 |
| CELL[45].OUT_BEL[28] | CFG.ICAP_OUT_BOT30 |
| CELL[45].OUT_BEL[30] | CFG.ICAP_OUT_BOT31 |
| CELL[45].IMUX_CTRL[0] | CFG.ICAP_CLK_BOT |
| CELL[45].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_BOT16 |
| CELL[45].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_BOT17 |
| CELL[45].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_BOT18 |
| CELL[45].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_BOT19 |
| CELL[45].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_BOT20 |
| CELL[45].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_BOT21 |
| CELL[45].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_BOT22 |
| CELL[45].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_BOT23 |
| CELL[45].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_BOT24 |
| CELL[45].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_BOT25 |
| CELL[45].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_BOT26 |
| CELL[45].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_BOT27 |
| CELL[45].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_BOT28 |
| CELL[45].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_BOT29 |
| CELL[45].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_BOT30 |
| CELL[45].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_BOT31 |
| CELL[46].OUT_BEL[0] | CFG.USR_EFUSE0 |
| CELL[46].OUT_BEL[2] | CFG.USR_EFUSE1 |
| CELL[46].OUT_BEL[4] | CFG.USR_EFUSE2 |
| CELL[46].OUT_BEL[6] | CFG.USR_EFUSE3 |
| CELL[46].OUT_BEL[8] | CFG.USR_EFUSE4 |
| CELL[46].OUT_BEL[10] | CFG.USR_EFUSE5 |
| CELL[46].OUT_BEL[12] | CFG.USR_EFUSE6 |
| CELL[46].OUT_BEL[14] | CFG.USR_EFUSE7 |
| CELL[46].OUT_BEL[16] | CFG.USR_EFUSE8 |
| CELL[46].OUT_BEL[18] | CFG.USR_EFUSE9 |
| CELL[46].OUT_BEL[20] | CFG.USR_EFUSE10 |
| CELL[46].OUT_BEL[22] | CFG.USR_EFUSE11 |
| CELL[46].OUT_BEL[24] | CFG.USR_EFUSE12 |
| CELL[46].OUT_BEL[26] | CFG.USR_EFUSE13 |
| CELL[46].OUT_BEL[28] | CFG.USR_EFUSE14 |
| CELL[46].OUT_BEL[30] | CFG.USR_EFUSE15 |
| CELL[47].OUT_BEL[0] | CFG.USR_D_PIN_CFGIO0 |
| CELL[47].OUT_BEL[2] | CFG.USR_D_PIN_CFGIO1 |
| CELL[47].OUT_BEL[4] | CFG.USR_D_PIN_CFGIO2 |
| CELL[47].OUT_BEL[6] | CFG.USR_D_PIN_CFGIO3 |
| CELL[47].OUT_BEL[8] | CFG.PROG_REQ |
| CELL[47].OUT_BEL[10] | CFG.EOS |
| CELL[47].OUT_BEL[12] | CFG.START_CFG_MCLK |
| CELL[47].OUT_BEL[14] | CFG.START_CFG_CLK |
| CELL[47].IMUX_CTRL[0] | CFG.USR_CCLK_O |
| CELL[47].IMUX_IMUX_DELAY[0] | CFG.KEY_CLEAR_B |
| CELL[47].IMUX_IMUX_DELAY[1] | CFG.PROG_ACK |
| CELL[47].IMUX_IMUX_DELAY[2] | CFG.USR_CCLK_TS |
| CELL[47].IMUX_IMUX_DELAY[3] | CFG.USR_DONE_O |
| CELL[47].IMUX_IMUX_DELAY[4] | CFG.USR_DONE_TS |
| CELL[47].IMUX_IMUX_DELAY[5] | CFG.USR_GSR |
| CELL[47].IMUX_IMUX_DELAY[6] | CFG.USR_GTS |
| CELL[47].IMUX_IMUX_DELAY[7] | CFG.USR_FCS_B_O |
| CELL[47].IMUX_IMUX_DELAY[8] | CFG.USR_FCS_B_TS |
| CELL[47].IMUX_IMUX_DELAY[9] | CFG.USR_D_O_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[10] | CFG.USR_D_O_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[11] | CFG.USR_D_O_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[12] | CFG.USR_D_O_CFGIO3 |
| CELL[47].IMUX_IMUX_DELAY[13] | CFG.USR_D_TS_CFGIO0 |
| CELL[47].IMUX_IMUX_DELAY[14] | CFG.USR_D_TS_CFGIO1 |
| CELL[47].IMUX_IMUX_DELAY[15] | CFG.USR_D_TS_CFGIO2 |
| CELL[47].IMUX_IMUX_DELAY[16] | CFG.USR_D_TS_CFGIO3 |
| CELL[48].OUT_BEL[0] | CFG.IOX_CFGDATA0 |
| CELL[48].OUT_BEL[2] | CFG.IOX_CFGDATA1 |
| CELL[48].OUT_BEL[4] | CFG.IOX_CFGDATA2 |
| CELL[48].OUT_BEL[6] | CFG.IOX_CFGDATA3 |
| CELL[48].OUT_BEL[8] | CFG.IOX_CFGDATA4 |
| CELL[48].OUT_BEL[10] | CFG.IOX_CFGDATA5 |
| CELL[48].OUT_BEL[12] | CFG.IOX_CFGDATA6 |
| CELL[48].OUT_BEL[14] | CFG.IOX_CFGDATA7 |
| CELL[48].OUT_BEL[16] | CFG.IOX_CFGDATA8 |
| CELL[48].OUT_BEL[18] | CFG.IOX_CFGDATA9 |
| CELL[48].OUT_BEL[20] | CFG.IOX_CFGDATA10 |
| CELL[48].OUT_BEL[22] | CFG.IOX_CFGDATA11 |
| CELL[48].OUT_BEL[24] | CFG.IOX_CFGDATA12 |
| CELL[48].OUT_BEL[26] | CFG.IOX_CFGDATA13 |
| CELL[48].OUT_BEL[28] | CFG.IOX_CFGDATA14 |
| CELL[48].OUT_BEL[30] | CFG.IOX_CFGDATA15 |
| CELL[48].IMUX_IMUX_DELAY[0] | CFG.IOX_TDO |
| CELL[48].IMUX_IMUX_DELAY[1] | CFG.IOX_INITBO |
| CELL[49].OUT_BEL[0] | CFG.IOX_CFGDATA16 |
| CELL[49].OUT_BEL[2] | CFG.IOX_CFGDATA17 |
| CELL[49].OUT_BEL[4] | CFG.IOX_CFGDATA18 |
| CELL[49].OUT_BEL[6] | CFG.IOX_CFGDATA19 |
| CELL[49].OUT_BEL[8] | CFG.IOX_CFGDATA20 |
| CELL[49].OUT_BEL[10] | CFG.IOX_CFGDATA21 |
| CELL[49].OUT_BEL[12] | CFG.IOX_CFGDATA22 |
| CELL[49].OUT_BEL[14] | CFG.IOX_CFGDATA23 |
| CELL[49].OUT_BEL[16] | CFG.IOX_CFGDATA24 |
| CELL[49].OUT_BEL[18] | CFG.IOX_CFGDATA25 |
| CELL[49].OUT_BEL[20] | CFG.IOX_CFGDATA26 |
| CELL[49].OUT_BEL[22] | CFG.IOX_CFGDATA27 |
| CELL[49].OUT_BEL[24] | CFG.IOX_CFGDATA28 |
| CELL[49].OUT_BEL[26] | CFG.IOX_CFGDATA29 |
| CELL[49].OUT_BEL[28] | CFG.IOX_CFGDATA30 |
| CELL[49].OUT_BEL[30] | CFG.IOX_CFGDATA31 |
| CELL[50].OUT_BEL[0] | CFG.IOX_CCLK |
| CELL[50].OUT_BEL[2] | CFG.IOX_CFGMASTER |
| CELL[50].OUT_BEL[4] | CFG.IOX_VGG_COMP_OUT |
| CELL[50].OUT_BEL[6] | CFG.IOX_INITBI |
| CELL[50].OUT_BEL[8] | CFG.IOX_PUDCB |
| CELL[50].OUT_BEL[10] | CFG.IOX_RDWRB |
| CELL[50].OUT_BEL[12] | CFG.IOX_MODE0 |
| CELL[50].OUT_BEL[14] | CFG.IOX_MODE1 |
| CELL[50].OUT_BEL[16] | CFG.IOX_MODE2 |
| CELL[51].OUT_BEL[0] | CFG.ECC_FAR16 |
| CELL[51].OUT_BEL[2] | CFG.ECC_FAR17 |
| CELL[51].OUT_BEL[4] | CFG.ECC_FAR18 |
| CELL[51].OUT_BEL[6] | CFG.ECC_FAR19 |
| CELL[51].OUT_BEL[8] | CFG.ECC_FAR20 |
| CELL[51].OUT_BEL[10] | CFG.ECC_FAR21 |
| CELL[51].OUT_BEL[12] | CFG.ECC_FAR22 |
| CELL[51].OUT_BEL[14] | CFG.ECC_FAR23 |
| CELL[51].OUT_BEL[16] | CFG.ECC_FAR24 |
| CELL[51].OUT_BEL[18] | CFG.ECC_FAR25 |
| CELL[51].OUT_BEL[20] | CFG.RBCRC_ERROR |
| CELL[51].OUT_BEL[22] | CFG.ECC_ERROR_NOTSINGLE |
| CELL[51].OUT_BEL[24] | CFG.ECC_ERROR_SINGLE |
| CELL[51].OUT_BEL[26] | CFG.ECC_END_OF_FRAME |
| CELL[51].OUT_BEL[28] | CFG.ECC_END_OF_SCAN |
| CELL[51].IMUX_IMUX_DELAY[15] | CFG.ECC_FAR_SEL0 |
| CELL[51].IMUX_IMUX_DELAY[16] | CFG.ECC_FAR_SEL1 |
| CELL[52].OUT_BEL[0] | CFG.ECC_FAR0 |
| CELL[52].OUT_BEL[2] | CFG.ECC_FAR1 |
| CELL[52].OUT_BEL[4] | CFG.ECC_FAR2 |
| CELL[52].OUT_BEL[6] | CFG.ECC_FAR3 |
| CELL[52].OUT_BEL[8] | CFG.ECC_FAR4 |
| CELL[52].OUT_BEL[10] | CFG.ECC_FAR5 |
| CELL[52].OUT_BEL[12] | CFG.ECC_FAR6 |
| CELL[52].OUT_BEL[14] | CFG.ECC_FAR7 |
| CELL[52].OUT_BEL[16] | CFG.ECC_FAR8 |
| CELL[52].OUT_BEL[18] | CFG.ECC_FAR9 |
| CELL[52].OUT_BEL[20] | CFG.ECC_FAR10 |
| CELL[52].OUT_BEL[22] | CFG.ECC_FAR11 |
| CELL[52].OUT_BEL[24] | CFG.ECC_FAR12 |
| CELL[52].OUT_BEL[26] | CFG.ECC_FAR13 |
| CELL[52].OUT_BEL[28] | CFG.ECC_FAR14 |
| CELL[52].OUT_BEL[30] | CFG.ECC_FAR15 |
| CELL[52].OUT_BEL[31] | CFG.ECC_FAR26 |
| CELL[53].OUT_BEL[0] | CFG.BSCAN_SDR3 |
| CELL[53].OUT_BEL[2] | CFG.BSCAN_SDR4 |
| CELL[53].OUT_BEL[4] | CFG.BSCAN_SEL3 |
| CELL[53].OUT_BEL[6] | CFG.BSCAN_SEL4 |
| CELL[53].OUT_BEL[8] | CFG.BSCAN_TLR3 |
| CELL[53].OUT_BEL[10] | CFG.BSCAN_TLR4 |
| CELL[53].OUT_BEL[12] | CFG.BSCAN_UDR3 |
| CELL[53].OUT_BEL[14] | CFG.BSCAN_UDR4 |
| CELL[54].OUT_BEL[0] | CFG.ICAP_PR_DONE_TOP |
| CELL[54].OUT_BEL[2] | CFG.ICAP_PR_ERROR_TOP |
| CELL[54].OUT_BEL[4] | CFG.ICAP_AVAIL_TOP |
| CELL[54].OUT_BEL[6] | CFG.BSCAN_TCK3 |
| CELL[54].OUT_BEL[8] | CFG.BSCAN_TCK4 |
| CELL[54].OUT_BEL[10] | CFG.BSCAN_TMS3 |
| CELL[54].OUT_BEL[12] | CFG.BSCAN_TMS4 |
| CELL[54].OUT_BEL[14] | CFG.BSCAN_TDI3 |
| CELL[54].OUT_BEL[16] | CFG.BSCAN_TDI4 |
| CELL[54].OUT_BEL[18] | CFG.BSCAN_CDR3 |
| CELL[54].OUT_BEL[20] | CFG.BSCAN_CDR4 |
| CELL[54].OUT_BEL[22] | CFG.BSCAN_CLKDR3 |
| CELL[54].OUT_BEL[24] | CFG.BSCAN_CLKDR4 |
| CELL[54].OUT_BEL[26] | CFG.BSCAN_RTI3 |
| CELL[54].OUT_BEL[28] | CFG.BSCAN_RTI4 |
| CELL[54].IMUX_IMUX_DELAY[0] | CFG.ICAP_RDWR_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[1] | CFG.ICAP_CS_B_TOP |
| CELL[54].IMUX_IMUX_DELAY[2] | CFG.BSCAN_TDO3 |
| CELL[54].IMUX_IMUX_DELAY[3] | CFG.BSCAN_TDO4 |
| CELL[55].OUT_BEL[0] | CFG.ICAP_OUT_TOP0 |
| CELL[55].OUT_BEL[2] | CFG.ICAP_OUT_TOP1 |
| CELL[55].OUT_BEL[4] | CFG.ICAP_OUT_TOP2 |
| CELL[55].OUT_BEL[6] | CFG.ICAP_OUT_TOP3 |
| CELL[55].OUT_BEL[8] | CFG.ICAP_OUT_TOP4 |
| CELL[55].OUT_BEL[10] | CFG.ICAP_OUT_TOP5 |
| CELL[55].OUT_BEL[12] | CFG.ICAP_OUT_TOP6 |
| CELL[55].OUT_BEL[14] | CFG.ICAP_OUT_TOP7 |
| CELL[55].OUT_BEL[16] | CFG.ICAP_OUT_TOP8 |
| CELL[55].OUT_BEL[18] | CFG.ICAP_OUT_TOP9 |
| CELL[55].OUT_BEL[20] | CFG.ICAP_OUT_TOP10 |
| CELL[55].OUT_BEL[22] | CFG.ICAP_OUT_TOP11 |
| CELL[55].OUT_BEL[24] | CFG.ICAP_OUT_TOP12 |
| CELL[55].OUT_BEL[26] | CFG.ICAP_OUT_TOP13 |
| CELL[55].OUT_BEL[28] | CFG.ICAP_OUT_TOP14 |
| CELL[55].OUT_BEL[30] | CFG.ICAP_OUT_TOP15 |
| CELL[55].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP0 |
| CELL[55].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP1 |
| CELL[55].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP2 |
| CELL[55].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP3 |
| CELL[55].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP4 |
| CELL[55].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP5 |
| CELL[55].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP6 |
| CELL[55].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP7 |
| CELL[55].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP8 |
| CELL[55].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP9 |
| CELL[55].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP10 |
| CELL[55].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP11 |
| CELL[55].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP12 |
| CELL[55].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP13 |
| CELL[55].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP14 |
| CELL[55].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP15 |
| CELL[56].OUT_BEL[0] | CFG.ICAP_OUT_TOP16 |
| CELL[56].OUT_BEL[2] | CFG.ICAP_OUT_TOP17 |
| CELL[56].OUT_BEL[4] | CFG.ICAP_OUT_TOP18 |
| CELL[56].OUT_BEL[6] | CFG.ICAP_OUT_TOP19 |
| CELL[56].OUT_BEL[8] | CFG.ICAP_OUT_TOP20 |
| CELL[56].OUT_BEL[10] | CFG.ICAP_OUT_TOP21 |
| CELL[56].OUT_BEL[12] | CFG.ICAP_OUT_TOP22 |
| CELL[56].OUT_BEL[14] | CFG.ICAP_OUT_TOP23 |
| CELL[56].OUT_BEL[16] | CFG.ICAP_OUT_TOP24 |
| CELL[56].OUT_BEL[18] | CFG.ICAP_OUT_TOP25 |
| CELL[56].OUT_BEL[20] | CFG.ICAP_OUT_TOP26 |
| CELL[56].OUT_BEL[22] | CFG.ICAP_OUT_TOP27 |
| CELL[56].OUT_BEL[24] | CFG.ICAP_OUT_TOP28 |
| CELL[56].OUT_BEL[26] | CFG.ICAP_OUT_TOP29 |
| CELL[56].OUT_BEL[28] | CFG.ICAP_OUT_TOP30 |
| CELL[56].OUT_BEL[30] | CFG.ICAP_OUT_TOP31 |
| CELL[56].IMUX_CTRL[0] | CFG.ICAP_CLK_TOP |
| CELL[56].IMUX_IMUX_DELAY[0] | CFG.ICAP_DATA_TOP16 |
| CELL[56].IMUX_IMUX_DELAY[1] | CFG.ICAP_DATA_TOP17 |
| CELL[56].IMUX_IMUX_DELAY[2] | CFG.ICAP_DATA_TOP18 |
| CELL[56].IMUX_IMUX_DELAY[3] | CFG.ICAP_DATA_TOP19 |
| CELL[56].IMUX_IMUX_DELAY[4] | CFG.ICAP_DATA_TOP20 |
| CELL[56].IMUX_IMUX_DELAY[5] | CFG.ICAP_DATA_TOP21 |
| CELL[56].IMUX_IMUX_DELAY[6] | CFG.ICAP_DATA_TOP22 |
| CELL[56].IMUX_IMUX_DELAY[7] | CFG.ICAP_DATA_TOP23 |
| CELL[56].IMUX_IMUX_DELAY[8] | CFG.ICAP_DATA_TOP24 |
| CELL[56].IMUX_IMUX_DELAY[9] | CFG.ICAP_DATA_TOP25 |
| CELL[56].IMUX_IMUX_DELAY[10] | CFG.ICAP_DATA_TOP26 |
| CELL[56].IMUX_IMUX_DELAY[11] | CFG.ICAP_DATA_TOP27 |
| CELL[56].IMUX_IMUX_DELAY[12] | CFG.ICAP_DATA_TOP28 |
| CELL[56].IMUX_IMUX_DELAY[13] | CFG.ICAP_DATA_TOP29 |
| CELL[56].IMUX_IMUX_DELAY[14] | CFG.ICAP_DATA_TOP30 |
| CELL[56].IMUX_IMUX_DELAY[15] | CFG.ICAP_DATA_TOP31 |
| CELL[57].OUT_BEL[0] | CFG.USR_ACCESS_VALID |
| CELL[57].OUT_BEL[2] | CFG.USR_ACCESS_CLK |
| CELL[58].OUT_BEL[0] | CFG.USR_ACCESS_DATA0 |
| CELL[58].OUT_BEL[2] | CFG.USR_ACCESS_DATA1 |
| CELL[58].OUT_BEL[4] | CFG.USR_ACCESS_DATA2 |
| CELL[58].OUT_BEL[6] | CFG.USR_ACCESS_DATA3 |
| CELL[58].OUT_BEL[8] | CFG.USR_ACCESS_DATA4 |
| CELL[58].OUT_BEL[10] | CFG.USR_ACCESS_DATA5 |
| CELL[58].OUT_BEL[12] | CFG.USR_ACCESS_DATA6 |
| CELL[58].OUT_BEL[14] | CFG.USR_ACCESS_DATA7 |
| CELL[58].OUT_BEL[16] | CFG.USR_ACCESS_DATA8 |
| CELL[58].OUT_BEL[18] | CFG.USR_ACCESS_DATA9 |
| CELL[58].OUT_BEL[20] | CFG.USR_ACCESS_DATA10 |
| CELL[58].OUT_BEL[22] | CFG.USR_ACCESS_DATA11 |
| CELL[58].OUT_BEL[24] | CFG.USR_ACCESS_DATA12 |
| CELL[58].OUT_BEL[26] | CFG.USR_ACCESS_DATA13 |
| CELL[58].OUT_BEL[28] | CFG.USR_ACCESS_DATA14 |
| CELL[58].OUT_BEL[30] | CFG.USR_ACCESS_DATA15 |
| CELL[59].OUT_BEL[0] | CFG.USR_ACCESS_DATA16 |
| CELL[59].OUT_BEL[2] | CFG.USR_ACCESS_DATA17 |
| CELL[59].OUT_BEL[4] | CFG.USR_ACCESS_DATA18 |
| CELL[59].OUT_BEL[6] | CFG.USR_ACCESS_DATA19 |
| CELL[59].OUT_BEL[8] | CFG.USR_ACCESS_DATA20 |
| CELL[59].OUT_BEL[10] | CFG.USR_ACCESS_DATA21 |
| CELL[59].OUT_BEL[12] | CFG.USR_ACCESS_DATA22 |
| CELL[59].OUT_BEL[14] | CFG.USR_ACCESS_DATA23 |
| CELL[59].OUT_BEL[16] | CFG.USR_ACCESS_DATA24 |
| CELL[59].OUT_BEL[18] | CFG.USR_ACCESS_DATA25 |
| CELL[59].OUT_BEL[20] | CFG.USR_ACCESS_DATA26 |
| CELL[59].OUT_BEL[22] | CFG.USR_ACCESS_DATA27 |
| CELL[59].OUT_BEL[24] | CFG.USR_ACCESS_DATA28 |
| CELL[59].OUT_BEL[26] | CFG.USR_ACCESS_DATA29 |
| CELL[59].OUT_BEL[28] | CFG.USR_ACCESS_DATA30 |
| CELL[59].OUT_BEL[30] | CFG.USR_ACCESS_DATA31 |
Tile CFGIO
Cells: 30
Bel PMV
| Pin | Direction | Wires |
|---|---|---|
| OUT1_INTOP | output | CELL[29].OUT_BEL[18] |
| OUT2_INTOP | output | CELL[29].OUT_BEL[17] |
| OUT3_INTOP | output | CELL[29].OUT_BEL[21] |
| OUT4_INTOP | output | CELL[29].OUT_BEL[20] |
| PMV_EN1_INTIP | input | CELL[29].IMUX_IMUX_DELAY[43] |
| SPARE_IN1_INTIP0 | input | CELL[29].IMUX_IMUX_DELAY[44] |
| SPARE_IN1_INTIP1 | input | CELL[29].IMUX_IMUX_DELAY[13] |
| SPARE_IN1_INTIP2 | input | CELL[29].IMUX_IMUX_DELAY[45] |
| SPARE_IN1_INTIP3 | input | CELL[29].IMUX_IMUX_DELAY[46] |
| SPARE_IN1_INTIP4 | input | CELL[29].IMUX_IMUX_DELAY[47] |
| SPARE_IN1_INTIP5 | input | CELL[29].IMUX_IMUX_DELAY[14] |
Bel PMV2
| Pin | Direction | Wires |
|---|---|---|
| IMUX_IN_INT0 | input | CELL[28].IMUX_IMUX_DELAY[38] |
| IMUX_IN_INT1 | input | CELL[28].IMUX_IMUX_DELAY[41] |
| IMUX_IN_INT2 | input | CELL[28].IMUX_IMUX_DELAY[40] |
| IMUX_IN_INT3 | input | CELL[28].IMUX_IMUX_DELAY[39] |
| OUTS_INT0 | output | CELL[28].OUT_BEL[8] |
| OUTS_INT1 | output | CELL[28].OUT_BEL[4] |
| OUTS_INT2 | output | CELL[28].OUT_BEL[3] |
Bel PMVIOB
| Pin | Direction | Wires |
|---|---|---|
| OUT_DIV2_HPIO_INTOP | output | CELL[27].OUT_BEL[1] |
| OUT_DIV4_HPIO_INTOP | output | CELL[27].OUT_BEL[0] |
| OUT_HPIO_INTOP | output | CELL[27].OUT_BEL[2] |
| PMV_A_HPIO_INTIP0 | input | CELL[27].IMUX_IMUX_DELAY[0] |
| PMV_A_HPIO_INTIP1 | input | CELL[27].IMUX_IMUX_DELAY[1] |
| PMV_EN_HPIO_INTIP | input | CELL[27].IMUX_IMUX_DELAY[2] |
Bel MTBF3
| Pin | Direction | Wires |
|---|---|---|
| CAPTURE_CLK_INTIP | input | CELL[27].IMUX_IMUX_DELAY[24] |
| CAPTURE_Q_INTOP0 | output | CELL[27].OUT_BEL[27] |
| CAPTURE_Q_INTOP1 | output | CELL[27].OUT_BEL[28] |
| CAPTURE_Q_INTOP2 | output | CELL[27].OUT_BEL[29] |
| CAPTURE_Q_INTOP3 | output | CELL[27].OUT_BEL[30] |
| CAPTURE_Q_INTOP4 | output | CELL[27].OUT_BEL[31] |
| DATAIN_INTIP | input | CELL[27].IMUX_IMUX_DELAY[26] |
| FF_CLK_INTIP | input | CELL[27].IMUX_IMUX_DELAY[25] |
| FF_Q_INTOP0 | output | CELL[27].OUT_BEL[22] |
| FF_Q_INTOP1 | output | CELL[27].OUT_BEL[23] |
| FF_Q_INTOP2 | output | CELL[27].OUT_BEL[24] |
| FF_Q_INTOP3 | output | CELL[27].OUT_BEL[25] |
| FF_Q_INTOP4 | output | CELL[27].OUT_BEL[26] |
| OUTPUT_SEL_INTIP0 | input | CELL[27].IMUX_IMUX_DELAY[28] |
| OUTPUT_SEL_INTIP1 | input | CELL[27].IMUX_IMUX_DELAY[29] |
| OUTPUT_SEL_INTIP2 | input | CELL[27].IMUX_IMUX_DELAY[30] |
| OUTPUT_SEL_INTIP3 | input | CELL[27].IMUX_IMUX_DELAY[31] |
| RESET_INTIP | input | CELL[27].IMUX_IMUX_DELAY[27] |
| SYNC_ENABLE_INTIP | input | CELL[27].IMUX_IMUX_DELAY[5] |
| TOGGLE_SEL_INTIP | input | CELL[27].IMUX_IMUX_DELAY[4] |
Bel CFGIO
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| CELL[27].OUT_BEL[0] | PMVIOB.OUT_DIV4_HPIO_INTOP |
| CELL[27].OUT_BEL[1] | PMVIOB.OUT_DIV2_HPIO_INTOP |
| CELL[27].OUT_BEL[2] | PMVIOB.OUT_HPIO_INTOP |
| CELL[27].OUT_BEL[22] | MTBF3.FF_Q_INTOP0 |
| CELL[27].OUT_BEL[23] | MTBF3.FF_Q_INTOP1 |
| CELL[27].OUT_BEL[24] | MTBF3.FF_Q_INTOP2 |
| CELL[27].OUT_BEL[25] | MTBF3.FF_Q_INTOP3 |
| CELL[27].OUT_BEL[26] | MTBF3.FF_Q_INTOP4 |
| CELL[27].OUT_BEL[27] | MTBF3.CAPTURE_Q_INTOP0 |
| CELL[27].OUT_BEL[28] | MTBF3.CAPTURE_Q_INTOP1 |
| CELL[27].OUT_BEL[29] | MTBF3.CAPTURE_Q_INTOP2 |
| CELL[27].OUT_BEL[30] | MTBF3.CAPTURE_Q_INTOP3 |
| CELL[27].OUT_BEL[31] | MTBF3.CAPTURE_Q_INTOP4 |
| CELL[27].IMUX_IMUX_DELAY[0] | PMVIOB.PMV_A_HPIO_INTIP0 |
| CELL[27].IMUX_IMUX_DELAY[1] | PMVIOB.PMV_A_HPIO_INTIP1 |
| CELL[27].IMUX_IMUX_DELAY[2] | PMVIOB.PMV_EN_HPIO_INTIP |
| CELL[27].IMUX_IMUX_DELAY[4] | MTBF3.TOGGLE_SEL_INTIP |
| CELL[27].IMUX_IMUX_DELAY[5] | MTBF3.SYNC_ENABLE_INTIP |
| CELL[27].IMUX_IMUX_DELAY[24] | MTBF3.CAPTURE_CLK_INTIP |
| CELL[27].IMUX_IMUX_DELAY[25] | MTBF3.FF_CLK_INTIP |
| CELL[27].IMUX_IMUX_DELAY[26] | MTBF3.DATAIN_INTIP |
| CELL[27].IMUX_IMUX_DELAY[27] | MTBF3.RESET_INTIP |
| CELL[27].IMUX_IMUX_DELAY[28] | MTBF3.OUTPUT_SEL_INTIP0 |
| CELL[27].IMUX_IMUX_DELAY[29] | MTBF3.OUTPUT_SEL_INTIP1 |
| CELL[27].IMUX_IMUX_DELAY[30] | MTBF3.OUTPUT_SEL_INTIP2 |
| CELL[27].IMUX_IMUX_DELAY[31] | MTBF3.OUTPUT_SEL_INTIP3 |
| CELL[28].OUT_BEL[3] | PMV2.OUTS_INT2 |
| CELL[28].OUT_BEL[4] | PMV2.OUTS_INT1 |
| CELL[28].OUT_BEL[8] | PMV2.OUTS_INT0 |
| CELL[28].IMUX_IMUX_DELAY[38] | PMV2.IMUX_IN_INT0 |
| CELL[28].IMUX_IMUX_DELAY[39] | PMV2.IMUX_IN_INT3 |
| CELL[28].IMUX_IMUX_DELAY[40] | PMV2.IMUX_IN_INT2 |
| CELL[28].IMUX_IMUX_DELAY[41] | PMV2.IMUX_IN_INT1 |
| CELL[29].OUT_BEL[17] | PMV.OUT2_INTOP |
| CELL[29].OUT_BEL[18] | PMV.OUT1_INTOP |
| CELL[29].OUT_BEL[20] | PMV.OUT4_INTOP |
| CELL[29].OUT_BEL[21] | PMV.OUT3_INTOP |
| CELL[29].IMUX_IMUX_DELAY[13] | PMV.SPARE_IN1_INTIP1 |
| CELL[29].IMUX_IMUX_DELAY[14] | PMV.SPARE_IN1_INTIP5 |
| CELL[29].IMUX_IMUX_DELAY[43] | PMV.PMV_EN1_INTIP |
| CELL[29].IMUX_IMUX_DELAY[44] | PMV.SPARE_IN1_INTIP0 |
| CELL[29].IMUX_IMUX_DELAY[45] | PMV.SPARE_IN1_INTIP2 |
| CELL[29].IMUX_IMUX_DELAY[46] | PMV.SPARE_IN1_INTIP3 |
| CELL[29].IMUX_IMUX_DELAY[47] | PMV.SPARE_IN1_INTIP4 |
Tile AMS
Cells: 30
Bel SYSMON
| Pin | Direction | Wires |
|---|---|---|
| ADC_DATA0 | output | CELL[6].OUT_BEL[21] |
| ADC_DATA1 | output | CELL[6].OUT_BEL[23] |
| ADC_DATA10 | output | CELL[7].OUT_BEL[9] |
| ADC_DATA11 | output | CELL[7].OUT_BEL[11] |
| ADC_DATA12 | output | CELL[7].OUT_BEL[13] |
| ADC_DATA13 | output | CELL[7].OUT_BEL[15] |
| ADC_DATA14 | output | CELL[7].OUT_BEL[17] |
| ADC_DATA15 | output | CELL[7].OUT_BEL[19] |
| ADC_DATA2 | output | CELL[6].OUT_BEL[25] |
| ADC_DATA3 | output | CELL[6].OUT_BEL[27] |
| ADC_DATA4 | output | CELL[6].OUT_BEL[29] |
| ADC_DATA5 | output | CELL[6].OUT_BEL[31] |
| ADC_DATA6 | output | CELL[7].OUT_BEL[1] |
| ADC_DATA7 | output | CELL[7].OUT_BEL[3] |
| ADC_DATA8 | output | CELL[7].OUT_BEL[5] |
| ADC_DATA9 | output | CELL[7].OUT_BEL[7] |
| ALM0 | output | CELL[5].OUT_BEL[21] |
| ALM1 | output | CELL[5].OUT_BEL[23] |
| ALM10 | output | CELL[6].OUT_BEL[9] |
| ALM11 | output | CELL[6].OUT_BEL[11] |
| ALM12 | output | CELL[6].OUT_BEL[13] |
| ALM13 | output | CELL[6].OUT_BEL[15] |
| ALM14 | output | CELL[6].OUT_BEL[17] |
| ALM15 | output | CELL[6].OUT_BEL[19] |
| ALM2 | output | CELL[5].OUT_BEL[25] |
| ALM3 | output | CELL[5].OUT_BEL[27] |
| ALM4 | output | CELL[5].OUT_BEL[29] |
| ALM5 | output | CELL[5].OUT_BEL[31] |
| ALM6 | output | CELL[6].OUT_BEL[1] |
| ALM7 | output | CELL[6].OUT_BEL[3] |
| ALM8 | output | CELL[6].OUT_BEL[5] |
| ALM9 | output | CELL[6].OUT_BEL[7] |
| BUSY | output | CELL[5].OUT_BEL[19] |
| CHANNEL0 | output | CELL[5].OUT_BEL[7] |
| CHANNEL1 | output | CELL[5].OUT_BEL[9] |
| CHANNEL2 | output | CELL[5].OUT_BEL[11] |
| CHANNEL3 | output | CELL[5].OUT_BEL[13] |
| CHANNEL4 | output | CELL[5].OUT_BEL[15] |
| CHANNEL5 | output | CELL[5].OUT_BEL[17] |
| CONVST | input | CELL[6].IMUX_IMUX_DELAY[47] |
| CONVST_CLK | input | CELL[5].IMUX_CTRL[4] |
| DADDR0 | input | CELL[6].IMUX_IMUX_DELAY[23] |
| DADDR1 | input | CELL[6].IMUX_IMUX_DELAY[25] |
| DADDR2 | input | CELL[6].IMUX_IMUX_DELAY[27] |
| DADDR3 | input | CELL[6].IMUX_IMUX_DELAY[29] |
| DADDR4 | input | CELL[6].IMUX_IMUX_DELAY[31] |
| DADDR5 | input | CELL[6].IMUX_IMUX_DELAY[33] |
| DADDR6 | input | CELL[6].IMUX_IMUX_DELAY[35] |
| DADDR7 | input | CELL[6].IMUX_IMUX_DELAY[37] |
| DATA_READY_ADC_F | input | CELL[5].IMUX_IMUX_DELAY[37] |
| DCLK | input | CELL[5].IMUX_CTRL[1] |
| DEC_OUT_ADC_F0 | input | CELL[5].IMUX_IMUX_DELAY[5] |
| DEC_OUT_ADC_F1 | input | CELL[5].IMUX_IMUX_DELAY[7] |
| DEC_OUT_ADC_F10 | input | CELL[5].IMUX_IMUX_DELAY[25] |
| DEC_OUT_ADC_F11 | input | CELL[5].IMUX_IMUX_DELAY[27] |
| DEC_OUT_ADC_F12 | input | CELL[5].IMUX_IMUX_DELAY[29] |
| DEC_OUT_ADC_F13 | input | CELL[5].IMUX_IMUX_DELAY[31] |
| DEC_OUT_ADC_F14 | input | CELL[5].IMUX_IMUX_DELAY[33] |
| DEC_OUT_ADC_F15 | input | CELL[5].IMUX_IMUX_DELAY[35] |
| DEC_OUT_ADC_F2 | input | CELL[5].IMUX_IMUX_DELAY[9] |
| DEC_OUT_ADC_F3 | input | CELL[5].IMUX_IMUX_DELAY[11] |
| DEC_OUT_ADC_F4 | input | CELL[5].IMUX_IMUX_DELAY[13] |
| DEC_OUT_ADC_F5 | input | CELL[5].IMUX_IMUX_DELAY[15] |
| DEC_OUT_ADC_F6 | input | CELL[5].IMUX_IMUX_DELAY[17] |
| DEC_OUT_ADC_F7 | input | CELL[5].IMUX_IMUX_DELAY[19] |
| DEC_OUT_ADC_F8 | input | CELL[5].IMUX_IMUX_DELAY[21] |
| DEC_OUT_ADC_F9 | input | CELL[5].IMUX_IMUX_DELAY[23] |
| DEN | input | CELL[6].IMUX_IMUX_DELAY[41] |
| DI0 | input | CELL[5].IMUX_IMUX_DELAY[39] |
| DI1 | input | CELL[5].IMUX_IMUX_DELAY[41] |
| DI10 | input | CELL[6].IMUX_IMUX_DELAY[11] |
| DI11 | input | CELL[6].IMUX_IMUX_DELAY[13] |
| DI12 | input | CELL[6].IMUX_IMUX_DELAY[15] |
| DI13 | input | CELL[6].IMUX_IMUX_DELAY[17] |
| DI14 | input | CELL[6].IMUX_IMUX_DELAY[19] |
| DI15 | input | CELL[6].IMUX_IMUX_DELAY[21] |
| DI2 | input | CELL[5].IMUX_IMUX_DELAY[43] |
| DI3 | input | CELL[5].IMUX_IMUX_DELAY[45] |
| DI4 | input | CELL[5].IMUX_IMUX_DELAY[47] |
| DI5 | input | CELL[6].IMUX_IMUX_DELAY[1] |
| DI6 | input | CELL[6].IMUX_IMUX_DELAY[3] |
| DI7 | input | CELL[6].IMUX_IMUX_DELAY[5] |
| DI8 | input | CELL[6].IMUX_IMUX_DELAY[7] |
| DI9 | input | CELL[6].IMUX_IMUX_DELAY[9] |
| DOUT0 | output | CELL[4].OUT_BEL[7] |
| DOUT1 | output | CELL[4].OUT_BEL[9] |
| DOUT10 | output | CELL[4].OUT_BEL[27] |
| DOUT11 | output | CELL[4].OUT_BEL[29] |
| DOUT12 | output | CELL[4].OUT_BEL[31] |
| DOUT13 | output | CELL[5].OUT_BEL[1] |
| DOUT14 | output | CELL[5].OUT_BEL[3] |
| DOUT15 | output | CELL[5].OUT_BEL[5] |
| DOUT2 | output | CELL[4].OUT_BEL[11] |
| DOUT3 | output | CELL[4].OUT_BEL[13] |
| DOUT4 | output | CELL[4].OUT_BEL[15] |
| DOUT5 | output | CELL[4].OUT_BEL[17] |
| DOUT6 | output | CELL[4].OUT_BEL[19] |
| DOUT7 | output | CELL[4].OUT_BEL[21] |
| DOUT8 | output | CELL[4].OUT_BEL[23] |
| DOUT9 | output | CELL[4].OUT_BEL[25] |
| DRDY | output | CELL[4].OUT_BEL[5] |
| DWE | input | CELL[6].IMUX_IMUX_DELAY[39] |
| EOC | output | CELL[4].OUT_BEL[3] |
| EOS | output | CELL[4].OUT_BEL[1] |
| I2C_SCLK_IN | input | CELL[6].IMUX_IMUX_DELAY[45] |
| I2C_SCLK_TS | output | CELL[3].OUT_BEL[13] |
| I2C_SDA_IN | input | CELL[6].IMUX_IMUX_DELAY[43] |
| I2C_SDA_TS | output | CELL[3].OUT_BEL[11] |
| JTAG_BUSY | output | CELL[3].OUT_BEL[31] |
| JTAG_LOCKED | output | CELL[3].OUT_BEL[29] |
| JTAG_MODIFIED | output | CELL[3].OUT_BEL[27] |
| MUX_ADDR0 | output | CELL[3].OUT_BEL[17] |
| MUX_ADDR1 | output | CELL[3].OUT_BEL[19] |
| MUX_ADDR2 | output | CELL[3].OUT_BEL[21] |
| MUX_ADDR3 | output | CELL[3].OUT_BEL[23] |
| MUX_ADDR4 | output | CELL[3].OUT_BEL[25] |
| OT | output | CELL[3].OUT_BEL[15] |
| RESET_USER | input | CELL[5].IMUX_CTRL[7] |
| SMBALERT_TS | output | CELL[3].OUT_BEL[9] |
| TEST_ADC_CLK0 | input | CELL[3].IMUX_CTRL[7] |
| TEST_ADC_CLK1 | input | CELL[4].IMUX_CTRL[1] |
| TEST_ADC_CLK2 | input | CELL[4].IMUX_CTRL[4] |
| TEST_ADC_CLK3 | input | CELL[4].IMUX_CTRL[7] |
| TEST_ADC_IN0 | input | CELL[3].IMUX_IMUX_DELAY[37] |
| TEST_ADC_IN1 | input | CELL[3].IMUX_IMUX_DELAY[39] |
| TEST_ADC_IN10 | input | CELL[4].IMUX_IMUX_DELAY[9] |
| TEST_ADC_IN11 | input | CELL[4].IMUX_IMUX_DELAY[11] |
| TEST_ADC_IN12 | input | CELL[4].IMUX_IMUX_DELAY[13] |
| TEST_ADC_IN13 | input | CELL[4].IMUX_IMUX_DELAY[15] |
| TEST_ADC_IN14 | input | CELL[4].IMUX_IMUX_DELAY[17] |
| TEST_ADC_IN15 | input | CELL[4].IMUX_IMUX_DELAY[19] |
| TEST_ADC_IN16 | input | CELL[4].IMUX_IMUX_DELAY[21] |
| TEST_ADC_IN17 | input | CELL[4].IMUX_IMUX_DELAY[23] |
| TEST_ADC_IN18 | input | CELL[4].IMUX_IMUX_DELAY[25] |
| TEST_ADC_IN19 | input | CELL[4].IMUX_IMUX_DELAY[27] |
| TEST_ADC_IN2 | input | CELL[3].IMUX_IMUX_DELAY[41] |
| TEST_ADC_IN20 | input | CELL[4].IMUX_IMUX_DELAY[29] |
| TEST_ADC_IN21 | input | CELL[4].IMUX_IMUX_DELAY[31] |
| TEST_ADC_IN22 | input | CELL[4].IMUX_IMUX_DELAY[33] |
| TEST_ADC_IN23 | input | CELL[4].IMUX_IMUX_DELAY[35] |
| TEST_ADC_IN24 | input | CELL[4].IMUX_IMUX_DELAY[37] |
| TEST_ADC_IN25 | input | CELL[4].IMUX_IMUX_DELAY[39] |
| TEST_ADC_IN26 | input | CELL[4].IMUX_IMUX_DELAY[41] |
| TEST_ADC_IN27 | input | CELL[4].IMUX_IMUX_DELAY[43] |
| TEST_ADC_IN28 | input | CELL[4].IMUX_IMUX_DELAY[45] |
| TEST_ADC_IN29 | input | CELL[4].IMUX_IMUX_DELAY[47] |
| TEST_ADC_IN2_0 | input | CELL[2].IMUX_IMUX_DELAY[21] |
| TEST_ADC_IN2_1 | input | CELL[2].IMUX_IMUX_DELAY[23] |
| TEST_ADC_IN2_10 | input | CELL[2].IMUX_IMUX_DELAY[41] |
| TEST_ADC_IN2_11 | input | CELL[2].IMUX_IMUX_DELAY[43] |
| TEST_ADC_IN2_12 | input | CELL[2].IMUX_IMUX_DELAY[45] |
| TEST_ADC_IN2_13 | input | CELL[2].IMUX_IMUX_DELAY[47] |
| TEST_ADC_IN2_14 | input | CELL[3].IMUX_IMUX_DELAY[1] |
| TEST_ADC_IN2_15 | input | CELL[3].IMUX_IMUX_DELAY[3] |
| TEST_ADC_IN2_16 | input | CELL[3].IMUX_IMUX_DELAY[5] |
| TEST_ADC_IN2_17 | input | CELL[3].IMUX_IMUX_DELAY[7] |
| TEST_ADC_IN2_18 | input | CELL[3].IMUX_IMUX_DELAY[9] |
| TEST_ADC_IN2_19 | input | CELL[3].IMUX_IMUX_DELAY[11] |
| TEST_ADC_IN2_2 | input | CELL[2].IMUX_IMUX_DELAY[25] |
| TEST_ADC_IN2_20 | input | CELL[3].IMUX_IMUX_DELAY[13] |
| TEST_ADC_IN2_21 | input | CELL[3].IMUX_IMUX_DELAY[15] |
| TEST_ADC_IN2_22 | input | CELL[3].IMUX_IMUX_DELAY[17] |
| TEST_ADC_IN2_23 | input | CELL[3].IMUX_IMUX_DELAY[19] |
| TEST_ADC_IN2_24 | input | CELL[3].IMUX_IMUX_DELAY[21] |
| TEST_ADC_IN2_25 | input | CELL[3].IMUX_IMUX_DELAY[23] |
| TEST_ADC_IN2_26 | input | CELL[3].IMUX_IMUX_DELAY[25] |
| TEST_ADC_IN2_27 | input | CELL[3].IMUX_IMUX_DELAY[27] |
| TEST_ADC_IN2_28 | input | CELL[3].IMUX_IMUX_DELAY[29] |
| TEST_ADC_IN2_29 | input | CELL[3].IMUX_IMUX_DELAY[31] |
| TEST_ADC_IN2_3 | input | CELL[2].IMUX_IMUX_DELAY[27] |
| TEST_ADC_IN2_30 | input | CELL[3].IMUX_IMUX_DELAY[33] |
| TEST_ADC_IN2_31 | input | CELL[3].IMUX_IMUX_DELAY[35] |
| TEST_ADC_IN2_4 | input | CELL[2].IMUX_IMUX_DELAY[29] |
| TEST_ADC_IN2_5 | input | CELL[2].IMUX_IMUX_DELAY[31] |
| TEST_ADC_IN2_6 | input | CELL[2].IMUX_IMUX_DELAY[33] |
| TEST_ADC_IN2_7 | input | CELL[2].IMUX_IMUX_DELAY[35] |
| TEST_ADC_IN2_8 | input | CELL[2].IMUX_IMUX_DELAY[37] |
| TEST_ADC_IN2_9 | input | CELL[2].IMUX_IMUX_DELAY[39] |
| TEST_ADC_IN3 | input | CELL[3].IMUX_IMUX_DELAY[43] |
| TEST_ADC_IN30 | input | CELL[5].IMUX_IMUX_DELAY[1] |
| TEST_ADC_IN31 | input | CELL[5].IMUX_IMUX_DELAY[3] |
| TEST_ADC_IN4 | input | CELL[3].IMUX_IMUX_DELAY[45] |
| TEST_ADC_IN5 | input | CELL[3].IMUX_IMUX_DELAY[47] |
| TEST_ADC_IN6 | input | CELL[4].IMUX_IMUX_DELAY[1] |
| TEST_ADC_IN7 | input | CELL[4].IMUX_IMUX_DELAY[3] |
| TEST_ADC_IN8 | input | CELL[4].IMUX_IMUX_DELAY[5] |
| TEST_ADC_IN9 | input | CELL[4].IMUX_IMUX_DELAY[7] |
| TEST_ADC_OUT0 | output | CELL[0].OUT_BEL[13] |
| TEST_ADC_OUT1 | output | CELL[0].OUT_BEL[15] |
| TEST_ADC_OUT10 | output | CELL[1].OUT_BEL[1] |
| TEST_ADC_OUT11 | output | CELL[1].OUT_BEL[3] |
| TEST_ADC_OUT12 | output | CELL[1].OUT_BEL[5] |
| TEST_ADC_OUT13 | output | CELL[1].OUT_BEL[7] |
| TEST_ADC_OUT14 | output | CELL[1].OUT_BEL[9] |
| TEST_ADC_OUT15 | output | CELL[1].OUT_BEL[11] |
| TEST_ADC_OUT16 | output | CELL[1].OUT_BEL[13] |
| TEST_ADC_OUT17 | output | CELL[1].OUT_BEL[15] |
| TEST_ADC_OUT18 | output | CELL[1].OUT_BEL[17] |
| TEST_ADC_OUT19 | output | CELL[1].OUT_BEL[19] |
| TEST_ADC_OUT2 | output | CELL[0].OUT_BEL[17] |
| TEST_ADC_OUT3 | output | CELL[0].OUT_BEL[19] |
| TEST_ADC_OUT4 | output | CELL[0].OUT_BEL[21] |
| TEST_ADC_OUT5 | output | CELL[0].OUT_BEL[23] |
| TEST_ADC_OUT6 | output | CELL[0].OUT_BEL[25] |
| TEST_ADC_OUT7 | output | CELL[0].OUT_BEL[27] |
| TEST_ADC_OUT8 | output | CELL[0].OUT_BEL[29] |
| TEST_ADC_OUT9 | output | CELL[0].OUT_BEL[31] |
| TEST_CAPTURE | input | CELL[2].IMUX_IMUX_DELAY[19] |
| TEST_DB0 | output | CELL[1].OUT_BEL[21] |
| TEST_DB1 | output | CELL[1].OUT_BEL[23] |
| TEST_DB10 | output | CELL[2].OUT_BEL[9] |
| TEST_DB11 | output | CELL[2].OUT_BEL[11] |
| TEST_DB12 | output | CELL[2].OUT_BEL[13] |
| TEST_DB13 | output | CELL[2].OUT_BEL[15] |
| TEST_DB14 | output | CELL[2].OUT_BEL[17] |
| TEST_DB15 | output | CELL[2].OUT_BEL[19] |
| TEST_DB2 | output | CELL[1].OUT_BEL[25] |
| TEST_DB3 | output | CELL[1].OUT_BEL[27] |
| TEST_DB4 | output | CELL[1].OUT_BEL[29] |
| TEST_DB5 | output | CELL[1].OUT_BEL[31] |
| TEST_DB6 | output | CELL[2].OUT_BEL[1] |
| TEST_DB7 | output | CELL[2].OUT_BEL[3] |
| TEST_DB8 | output | CELL[2].OUT_BEL[5] |
| TEST_DB9 | output | CELL[2].OUT_BEL[7] |
| TEST_DRCK | input | CELL[2].IMUX_IMUX_DELAY[17] |
| TEST_EN_JTAG | input | CELL[2].IMUX_IMUX_DELAY[15] |
| TEST_RST | input | CELL[2].IMUX_IMUX_DELAY[13] |
| TEST_SCAN_CLK0 | input | CELL[2].IMUX_CTRL[1] |
| TEST_SCAN_CLK1 | input | CELL[2].IMUX_CTRL[4] |
| TEST_SCAN_CLK2 | input | CELL[2].IMUX_CTRL[7] |
| TEST_SCAN_CLK3 | input | CELL[3].IMUX_CTRL[1] |
| TEST_SCAN_CLK4 | input | CELL[3].IMUX_CTRL[4] |
| TEST_SCAN_MODE0 | input | CELL[2].IMUX_IMUX_DELAY[3] |
| TEST_SCAN_MODE1 | input | CELL[2].IMUX_IMUX_DELAY[5] |
| TEST_SCAN_MODE2 | input | CELL[2].IMUX_IMUX_DELAY[7] |
| TEST_SCAN_MODE3 | input | CELL[2].IMUX_IMUX_DELAY[9] |
| TEST_SCAN_MODE4 | input | CELL[2].IMUX_IMUX_DELAY[11] |
| TEST_SCAN_RESET | input | CELL[2].IMUX_IMUX_DELAY[1] |
| TEST_SE0 | input | CELL[1].IMUX_IMUX_DELAY[39] |
| TEST_SE1 | input | CELL[1].IMUX_IMUX_DELAY[41] |
| TEST_SE2 | input | CELL[1].IMUX_IMUX_DELAY[43] |
| TEST_SE3 | input | CELL[1].IMUX_IMUX_DELAY[45] |
| TEST_SE4 | input | CELL[1].IMUX_IMUX_DELAY[47] |
| TEST_SEL | input | CELL[1].IMUX_IMUX_DELAY[37] |
| TEST_SHIFT | input | CELL[1].IMUX_IMUX_DELAY[35] |
| TEST_SI0 | input | CELL[1].IMUX_IMUX_DELAY[15] |
| TEST_SI1 | input | CELL[1].IMUX_IMUX_DELAY[17] |
| TEST_SI2 | input | CELL[1].IMUX_IMUX_DELAY[19] |
| TEST_SI3 | input | CELL[1].IMUX_IMUX_DELAY[21] |
| TEST_SI4 | input | CELL[1].IMUX_IMUX_DELAY[23] |
| TEST_SI5 | input | CELL[1].IMUX_IMUX_DELAY[25] |
| TEST_SI6 | input | CELL[1].IMUX_IMUX_DELAY[27] |
| TEST_SI7 | input | CELL[1].IMUX_IMUX_DELAY[29] |
| TEST_SI8 | input | CELL[1].IMUX_IMUX_DELAY[31] |
| TEST_SI9 | input | CELL[1].IMUX_IMUX_DELAY[33] |
| TEST_SO0 | output | CELL[2].OUT_BEL[21] |
| TEST_SO1 | output | CELL[2].OUT_BEL[23] |
| TEST_SO2 | output | CELL[2].OUT_BEL[25] |
| TEST_SO3 | output | CELL[2].OUT_BEL[27] |
| TEST_SO4 | output | CELL[2].OUT_BEL[29] |
| TEST_SO5 | output | CELL[2].OUT_BEL[31] |
| TEST_SO6 | output | CELL[3].OUT_BEL[1] |
| TEST_SO7 | output | CELL[3].OUT_BEL[3] |
| TEST_SO8 | output | CELL[3].OUT_BEL[5] |
| TEST_SO9 | output | CELL[3].OUT_BEL[7] |
| TEST_TDI | input | CELL[1].IMUX_IMUX_DELAY[13] |
| TEST_TDO | output | CELL[0].OUT_BEL[11] |
| TEST_UPDATE | input | CELL[1].IMUX_IMUX_DELAY[11] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[0].OUT_BEL[11] | SYSMON.TEST_TDO |
| CELL[0].OUT_BEL[13] | SYSMON.TEST_ADC_OUT0 |
| CELL[0].OUT_BEL[15] | SYSMON.TEST_ADC_OUT1 |
| CELL[0].OUT_BEL[17] | SYSMON.TEST_ADC_OUT2 |
| CELL[0].OUT_BEL[19] | SYSMON.TEST_ADC_OUT3 |
| CELL[0].OUT_BEL[21] | SYSMON.TEST_ADC_OUT4 |
| CELL[0].OUT_BEL[23] | SYSMON.TEST_ADC_OUT5 |
| CELL[0].OUT_BEL[25] | SYSMON.TEST_ADC_OUT6 |
| CELL[0].OUT_BEL[27] | SYSMON.TEST_ADC_OUT7 |
| CELL[0].OUT_BEL[29] | SYSMON.TEST_ADC_OUT8 |
| CELL[0].OUT_BEL[31] | SYSMON.TEST_ADC_OUT9 |
| CELL[1].OUT_BEL[1] | SYSMON.TEST_ADC_OUT10 |
| CELL[1].OUT_BEL[3] | SYSMON.TEST_ADC_OUT11 |
| CELL[1].OUT_BEL[5] | SYSMON.TEST_ADC_OUT12 |
| CELL[1].OUT_BEL[7] | SYSMON.TEST_ADC_OUT13 |
| CELL[1].OUT_BEL[9] | SYSMON.TEST_ADC_OUT14 |
| CELL[1].OUT_BEL[11] | SYSMON.TEST_ADC_OUT15 |
| CELL[1].OUT_BEL[13] | SYSMON.TEST_ADC_OUT16 |
| CELL[1].OUT_BEL[15] | SYSMON.TEST_ADC_OUT17 |
| CELL[1].OUT_BEL[17] | SYSMON.TEST_ADC_OUT18 |
| CELL[1].OUT_BEL[19] | SYSMON.TEST_ADC_OUT19 |
| CELL[1].OUT_BEL[21] | SYSMON.TEST_DB0 |
| CELL[1].OUT_BEL[23] | SYSMON.TEST_DB1 |
| CELL[1].OUT_BEL[25] | SYSMON.TEST_DB2 |
| CELL[1].OUT_BEL[27] | SYSMON.TEST_DB3 |
| CELL[1].OUT_BEL[29] | SYSMON.TEST_DB4 |
| CELL[1].OUT_BEL[31] | SYSMON.TEST_DB5 |
| CELL[1].IMUX_IMUX_DELAY[11] | SYSMON.TEST_UPDATE |
| CELL[1].IMUX_IMUX_DELAY[13] | SYSMON.TEST_TDI |
| CELL[1].IMUX_IMUX_DELAY[15] | SYSMON.TEST_SI0 |
| CELL[1].IMUX_IMUX_DELAY[17] | SYSMON.TEST_SI1 |
| CELL[1].IMUX_IMUX_DELAY[19] | SYSMON.TEST_SI2 |
| CELL[1].IMUX_IMUX_DELAY[21] | SYSMON.TEST_SI3 |
| CELL[1].IMUX_IMUX_DELAY[23] | SYSMON.TEST_SI4 |
| CELL[1].IMUX_IMUX_DELAY[25] | SYSMON.TEST_SI5 |
| CELL[1].IMUX_IMUX_DELAY[27] | SYSMON.TEST_SI6 |
| CELL[1].IMUX_IMUX_DELAY[29] | SYSMON.TEST_SI7 |
| CELL[1].IMUX_IMUX_DELAY[31] | SYSMON.TEST_SI8 |
| CELL[1].IMUX_IMUX_DELAY[33] | SYSMON.TEST_SI9 |
| CELL[1].IMUX_IMUX_DELAY[35] | SYSMON.TEST_SHIFT |
| CELL[1].IMUX_IMUX_DELAY[37] | SYSMON.TEST_SEL |
| CELL[1].IMUX_IMUX_DELAY[39] | SYSMON.TEST_SE0 |
| CELL[1].IMUX_IMUX_DELAY[41] | SYSMON.TEST_SE1 |
| CELL[1].IMUX_IMUX_DELAY[43] | SYSMON.TEST_SE2 |
| CELL[1].IMUX_IMUX_DELAY[45] | SYSMON.TEST_SE3 |
| CELL[1].IMUX_IMUX_DELAY[47] | SYSMON.TEST_SE4 |
| CELL[2].OUT_BEL[1] | SYSMON.TEST_DB6 |
| CELL[2].OUT_BEL[3] | SYSMON.TEST_DB7 |
| CELL[2].OUT_BEL[5] | SYSMON.TEST_DB8 |
| CELL[2].OUT_BEL[7] | SYSMON.TEST_DB9 |
| CELL[2].OUT_BEL[9] | SYSMON.TEST_DB10 |
| CELL[2].OUT_BEL[11] | SYSMON.TEST_DB11 |
| CELL[2].OUT_BEL[13] | SYSMON.TEST_DB12 |
| CELL[2].OUT_BEL[15] | SYSMON.TEST_DB13 |
| CELL[2].OUT_BEL[17] | SYSMON.TEST_DB14 |
| CELL[2].OUT_BEL[19] | SYSMON.TEST_DB15 |
| CELL[2].OUT_BEL[21] | SYSMON.TEST_SO0 |
| CELL[2].OUT_BEL[23] | SYSMON.TEST_SO1 |
| CELL[2].OUT_BEL[25] | SYSMON.TEST_SO2 |
| CELL[2].OUT_BEL[27] | SYSMON.TEST_SO3 |
| CELL[2].OUT_BEL[29] | SYSMON.TEST_SO4 |
| CELL[2].OUT_BEL[31] | SYSMON.TEST_SO5 |
| CELL[2].IMUX_CTRL[1] | SYSMON.TEST_SCAN_CLK0 |
| CELL[2].IMUX_CTRL[4] | SYSMON.TEST_SCAN_CLK1 |
| CELL[2].IMUX_CTRL[7] | SYSMON.TEST_SCAN_CLK2 |
| CELL[2].IMUX_IMUX_DELAY[1] | SYSMON.TEST_SCAN_RESET |
| CELL[2].IMUX_IMUX_DELAY[3] | SYSMON.TEST_SCAN_MODE0 |
| CELL[2].IMUX_IMUX_DELAY[5] | SYSMON.TEST_SCAN_MODE1 |
| CELL[2].IMUX_IMUX_DELAY[7] | SYSMON.TEST_SCAN_MODE2 |
| CELL[2].IMUX_IMUX_DELAY[9] | SYSMON.TEST_SCAN_MODE3 |
| CELL[2].IMUX_IMUX_DELAY[11] | SYSMON.TEST_SCAN_MODE4 |
| CELL[2].IMUX_IMUX_DELAY[13] | SYSMON.TEST_RST |
| CELL[2].IMUX_IMUX_DELAY[15] | SYSMON.TEST_EN_JTAG |
| CELL[2].IMUX_IMUX_DELAY[17] | SYSMON.TEST_DRCK |
| CELL[2].IMUX_IMUX_DELAY[19] | SYSMON.TEST_CAPTURE |
| CELL[2].IMUX_IMUX_DELAY[21] | SYSMON.TEST_ADC_IN2_0 |
| CELL[2].IMUX_IMUX_DELAY[23] | SYSMON.TEST_ADC_IN2_1 |
| CELL[2].IMUX_IMUX_DELAY[25] | SYSMON.TEST_ADC_IN2_2 |
| CELL[2].IMUX_IMUX_DELAY[27] | SYSMON.TEST_ADC_IN2_3 |
| CELL[2].IMUX_IMUX_DELAY[29] | SYSMON.TEST_ADC_IN2_4 |
| CELL[2].IMUX_IMUX_DELAY[31] | SYSMON.TEST_ADC_IN2_5 |
| CELL[2].IMUX_IMUX_DELAY[33] | SYSMON.TEST_ADC_IN2_6 |
| CELL[2].IMUX_IMUX_DELAY[35] | SYSMON.TEST_ADC_IN2_7 |
| CELL[2].IMUX_IMUX_DELAY[37] | SYSMON.TEST_ADC_IN2_8 |
| CELL[2].IMUX_IMUX_DELAY[39] | SYSMON.TEST_ADC_IN2_9 |
| CELL[2].IMUX_IMUX_DELAY[41] | SYSMON.TEST_ADC_IN2_10 |
| CELL[2].IMUX_IMUX_DELAY[43] | SYSMON.TEST_ADC_IN2_11 |
| CELL[2].IMUX_IMUX_DELAY[45] | SYSMON.TEST_ADC_IN2_12 |
| CELL[2].IMUX_IMUX_DELAY[47] | SYSMON.TEST_ADC_IN2_13 |
| CELL[3].OUT_BEL[1] | SYSMON.TEST_SO6 |
| CELL[3].OUT_BEL[3] | SYSMON.TEST_SO7 |
| CELL[3].OUT_BEL[5] | SYSMON.TEST_SO8 |
| CELL[3].OUT_BEL[7] | SYSMON.TEST_SO9 |
| CELL[3].OUT_BEL[9] | SYSMON.SMBALERT_TS |
| CELL[3].OUT_BEL[11] | SYSMON.I2C_SDA_TS |
| CELL[3].OUT_BEL[13] | SYSMON.I2C_SCLK_TS |
| CELL[3].OUT_BEL[15] | SYSMON.OT |
| CELL[3].OUT_BEL[17] | SYSMON.MUX_ADDR0 |
| CELL[3].OUT_BEL[19] | SYSMON.MUX_ADDR1 |
| CELL[3].OUT_BEL[21] | SYSMON.MUX_ADDR2 |
| CELL[3].OUT_BEL[23] | SYSMON.MUX_ADDR3 |
| CELL[3].OUT_BEL[25] | SYSMON.MUX_ADDR4 |
| CELL[3].OUT_BEL[27] | SYSMON.JTAG_MODIFIED |
| CELL[3].OUT_BEL[29] | SYSMON.JTAG_LOCKED |
| CELL[3].OUT_BEL[31] | SYSMON.JTAG_BUSY |
| CELL[3].IMUX_CTRL[1] | SYSMON.TEST_SCAN_CLK3 |
| CELL[3].IMUX_CTRL[4] | SYSMON.TEST_SCAN_CLK4 |
| CELL[3].IMUX_CTRL[7] | SYSMON.TEST_ADC_CLK0 |
| CELL[3].IMUX_IMUX_DELAY[1] | SYSMON.TEST_ADC_IN2_14 |
| CELL[3].IMUX_IMUX_DELAY[3] | SYSMON.TEST_ADC_IN2_15 |
| CELL[3].IMUX_IMUX_DELAY[5] | SYSMON.TEST_ADC_IN2_16 |
| CELL[3].IMUX_IMUX_DELAY[7] | SYSMON.TEST_ADC_IN2_17 |
| CELL[3].IMUX_IMUX_DELAY[9] | SYSMON.TEST_ADC_IN2_18 |
| CELL[3].IMUX_IMUX_DELAY[11] | SYSMON.TEST_ADC_IN2_19 |
| CELL[3].IMUX_IMUX_DELAY[13] | SYSMON.TEST_ADC_IN2_20 |
| CELL[3].IMUX_IMUX_DELAY[15] | SYSMON.TEST_ADC_IN2_21 |
| CELL[3].IMUX_IMUX_DELAY[17] | SYSMON.TEST_ADC_IN2_22 |
| CELL[3].IMUX_IMUX_DELAY[19] | SYSMON.TEST_ADC_IN2_23 |
| CELL[3].IMUX_IMUX_DELAY[21] | SYSMON.TEST_ADC_IN2_24 |
| CELL[3].IMUX_IMUX_DELAY[23] | SYSMON.TEST_ADC_IN2_25 |
| CELL[3].IMUX_IMUX_DELAY[25] | SYSMON.TEST_ADC_IN2_26 |
| CELL[3].IMUX_IMUX_DELAY[27] | SYSMON.TEST_ADC_IN2_27 |
| CELL[3].IMUX_IMUX_DELAY[29] | SYSMON.TEST_ADC_IN2_28 |
| CELL[3].IMUX_IMUX_DELAY[31] | SYSMON.TEST_ADC_IN2_29 |
| CELL[3].IMUX_IMUX_DELAY[33] | SYSMON.TEST_ADC_IN2_30 |
| CELL[3].IMUX_IMUX_DELAY[35] | SYSMON.TEST_ADC_IN2_31 |
| CELL[3].IMUX_IMUX_DELAY[37] | SYSMON.TEST_ADC_IN0 |
| CELL[3].IMUX_IMUX_DELAY[39] | SYSMON.TEST_ADC_IN1 |
| CELL[3].IMUX_IMUX_DELAY[41] | SYSMON.TEST_ADC_IN2 |
| CELL[3].IMUX_IMUX_DELAY[43] | SYSMON.TEST_ADC_IN3 |
| CELL[3].IMUX_IMUX_DELAY[45] | SYSMON.TEST_ADC_IN4 |
| CELL[3].IMUX_IMUX_DELAY[47] | SYSMON.TEST_ADC_IN5 |
| CELL[4].OUT_BEL[1] | SYSMON.EOS |
| CELL[4].OUT_BEL[3] | SYSMON.EOC |
| CELL[4].OUT_BEL[5] | SYSMON.DRDY |
| CELL[4].OUT_BEL[7] | SYSMON.DOUT0 |
| CELL[4].OUT_BEL[9] | SYSMON.DOUT1 |
| CELL[4].OUT_BEL[11] | SYSMON.DOUT2 |
| CELL[4].OUT_BEL[13] | SYSMON.DOUT3 |
| CELL[4].OUT_BEL[15] | SYSMON.DOUT4 |
| CELL[4].OUT_BEL[17] | SYSMON.DOUT5 |
| CELL[4].OUT_BEL[19] | SYSMON.DOUT6 |
| CELL[4].OUT_BEL[21] | SYSMON.DOUT7 |
| CELL[4].OUT_BEL[23] | SYSMON.DOUT8 |
| CELL[4].OUT_BEL[25] | SYSMON.DOUT9 |
| CELL[4].OUT_BEL[27] | SYSMON.DOUT10 |
| CELL[4].OUT_BEL[29] | SYSMON.DOUT11 |
| CELL[4].OUT_BEL[31] | SYSMON.DOUT12 |
| CELL[4].IMUX_CTRL[1] | SYSMON.TEST_ADC_CLK1 |
| CELL[4].IMUX_CTRL[4] | SYSMON.TEST_ADC_CLK2 |
| CELL[4].IMUX_CTRL[7] | SYSMON.TEST_ADC_CLK3 |
| CELL[4].IMUX_IMUX_DELAY[1] | SYSMON.TEST_ADC_IN6 |
| CELL[4].IMUX_IMUX_DELAY[3] | SYSMON.TEST_ADC_IN7 |
| CELL[4].IMUX_IMUX_DELAY[5] | SYSMON.TEST_ADC_IN8 |
| CELL[4].IMUX_IMUX_DELAY[7] | SYSMON.TEST_ADC_IN9 |
| CELL[4].IMUX_IMUX_DELAY[9] | SYSMON.TEST_ADC_IN10 |
| CELL[4].IMUX_IMUX_DELAY[11] | SYSMON.TEST_ADC_IN11 |
| CELL[4].IMUX_IMUX_DELAY[13] | SYSMON.TEST_ADC_IN12 |
| CELL[4].IMUX_IMUX_DELAY[15] | SYSMON.TEST_ADC_IN13 |
| CELL[4].IMUX_IMUX_DELAY[17] | SYSMON.TEST_ADC_IN14 |
| CELL[4].IMUX_IMUX_DELAY[19] | SYSMON.TEST_ADC_IN15 |
| CELL[4].IMUX_IMUX_DELAY[21] | SYSMON.TEST_ADC_IN16 |
| CELL[4].IMUX_IMUX_DELAY[23] | SYSMON.TEST_ADC_IN17 |
| CELL[4].IMUX_IMUX_DELAY[25] | SYSMON.TEST_ADC_IN18 |
| CELL[4].IMUX_IMUX_DELAY[27] | SYSMON.TEST_ADC_IN19 |
| CELL[4].IMUX_IMUX_DELAY[29] | SYSMON.TEST_ADC_IN20 |
| CELL[4].IMUX_IMUX_DELAY[31] | SYSMON.TEST_ADC_IN21 |
| CELL[4].IMUX_IMUX_DELAY[33] | SYSMON.TEST_ADC_IN22 |
| CELL[4].IMUX_IMUX_DELAY[35] | SYSMON.TEST_ADC_IN23 |
| CELL[4].IMUX_IMUX_DELAY[37] | SYSMON.TEST_ADC_IN24 |
| CELL[4].IMUX_IMUX_DELAY[39] | SYSMON.TEST_ADC_IN25 |
| CELL[4].IMUX_IMUX_DELAY[41] | SYSMON.TEST_ADC_IN26 |
| CELL[4].IMUX_IMUX_DELAY[43] | SYSMON.TEST_ADC_IN27 |
| CELL[4].IMUX_IMUX_DELAY[45] | SYSMON.TEST_ADC_IN28 |
| CELL[4].IMUX_IMUX_DELAY[47] | SYSMON.TEST_ADC_IN29 |
| CELL[5].OUT_BEL[1] | SYSMON.DOUT13 |
| CELL[5].OUT_BEL[3] | SYSMON.DOUT14 |
| CELL[5].OUT_BEL[5] | SYSMON.DOUT15 |
| CELL[5].OUT_BEL[7] | SYSMON.CHANNEL0 |
| CELL[5].OUT_BEL[9] | SYSMON.CHANNEL1 |
| CELL[5].OUT_BEL[11] | SYSMON.CHANNEL2 |
| CELL[5].OUT_BEL[13] | SYSMON.CHANNEL3 |
| CELL[5].OUT_BEL[15] | SYSMON.CHANNEL4 |
| CELL[5].OUT_BEL[17] | SYSMON.CHANNEL5 |
| CELL[5].OUT_BEL[19] | SYSMON.BUSY |
| CELL[5].OUT_BEL[21] | SYSMON.ALM0 |
| CELL[5].OUT_BEL[23] | SYSMON.ALM1 |
| CELL[5].OUT_BEL[25] | SYSMON.ALM2 |
| CELL[5].OUT_BEL[27] | SYSMON.ALM3 |
| CELL[5].OUT_BEL[29] | SYSMON.ALM4 |
| CELL[5].OUT_BEL[31] | SYSMON.ALM5 |
| CELL[5].IMUX_CTRL[1] | SYSMON.DCLK |
| CELL[5].IMUX_CTRL[4] | SYSMON.CONVST_CLK |
| CELL[5].IMUX_CTRL[7] | SYSMON.RESET_USER |
| CELL[5].IMUX_IMUX_DELAY[1] | SYSMON.TEST_ADC_IN30 |
| CELL[5].IMUX_IMUX_DELAY[3] | SYSMON.TEST_ADC_IN31 |
| CELL[5].IMUX_IMUX_DELAY[5] | SYSMON.DEC_OUT_ADC_F0 |
| CELL[5].IMUX_IMUX_DELAY[7] | SYSMON.DEC_OUT_ADC_F1 |
| CELL[5].IMUX_IMUX_DELAY[9] | SYSMON.DEC_OUT_ADC_F2 |
| CELL[5].IMUX_IMUX_DELAY[11] | SYSMON.DEC_OUT_ADC_F3 |
| CELL[5].IMUX_IMUX_DELAY[13] | SYSMON.DEC_OUT_ADC_F4 |
| CELL[5].IMUX_IMUX_DELAY[15] | SYSMON.DEC_OUT_ADC_F5 |
| CELL[5].IMUX_IMUX_DELAY[17] | SYSMON.DEC_OUT_ADC_F6 |
| CELL[5].IMUX_IMUX_DELAY[19] | SYSMON.DEC_OUT_ADC_F7 |
| CELL[5].IMUX_IMUX_DELAY[21] | SYSMON.DEC_OUT_ADC_F8 |
| CELL[5].IMUX_IMUX_DELAY[23] | SYSMON.DEC_OUT_ADC_F9 |
| CELL[5].IMUX_IMUX_DELAY[25] | SYSMON.DEC_OUT_ADC_F10 |
| CELL[5].IMUX_IMUX_DELAY[27] | SYSMON.DEC_OUT_ADC_F11 |
| CELL[5].IMUX_IMUX_DELAY[29] | SYSMON.DEC_OUT_ADC_F12 |
| CELL[5].IMUX_IMUX_DELAY[31] | SYSMON.DEC_OUT_ADC_F13 |
| CELL[5].IMUX_IMUX_DELAY[33] | SYSMON.DEC_OUT_ADC_F14 |
| CELL[5].IMUX_IMUX_DELAY[35] | SYSMON.DEC_OUT_ADC_F15 |
| CELL[5].IMUX_IMUX_DELAY[37] | SYSMON.DATA_READY_ADC_F |
| CELL[5].IMUX_IMUX_DELAY[39] | SYSMON.DI0 |
| CELL[5].IMUX_IMUX_DELAY[41] | SYSMON.DI1 |
| CELL[5].IMUX_IMUX_DELAY[43] | SYSMON.DI2 |
| CELL[5].IMUX_IMUX_DELAY[45] | SYSMON.DI3 |
| CELL[5].IMUX_IMUX_DELAY[47] | SYSMON.DI4 |
| CELL[6].OUT_BEL[1] | SYSMON.ALM6 |
| CELL[6].OUT_BEL[3] | SYSMON.ALM7 |
| CELL[6].OUT_BEL[5] | SYSMON.ALM8 |
| CELL[6].OUT_BEL[7] | SYSMON.ALM9 |
| CELL[6].OUT_BEL[9] | SYSMON.ALM10 |
| CELL[6].OUT_BEL[11] | SYSMON.ALM11 |
| CELL[6].OUT_BEL[13] | SYSMON.ALM12 |
| CELL[6].OUT_BEL[15] | SYSMON.ALM13 |
| CELL[6].OUT_BEL[17] | SYSMON.ALM14 |
| CELL[6].OUT_BEL[19] | SYSMON.ALM15 |
| CELL[6].OUT_BEL[21] | SYSMON.ADC_DATA0 |
| CELL[6].OUT_BEL[23] | SYSMON.ADC_DATA1 |
| CELL[6].OUT_BEL[25] | SYSMON.ADC_DATA2 |
| CELL[6].OUT_BEL[27] | SYSMON.ADC_DATA3 |
| CELL[6].OUT_BEL[29] | SYSMON.ADC_DATA4 |
| CELL[6].OUT_BEL[31] | SYSMON.ADC_DATA5 |
| CELL[6].IMUX_IMUX_DELAY[1] | SYSMON.DI5 |
| CELL[6].IMUX_IMUX_DELAY[3] | SYSMON.DI6 |
| CELL[6].IMUX_IMUX_DELAY[5] | SYSMON.DI7 |
| CELL[6].IMUX_IMUX_DELAY[7] | SYSMON.DI8 |
| CELL[6].IMUX_IMUX_DELAY[9] | SYSMON.DI9 |
| CELL[6].IMUX_IMUX_DELAY[11] | SYSMON.DI10 |
| CELL[6].IMUX_IMUX_DELAY[13] | SYSMON.DI11 |
| CELL[6].IMUX_IMUX_DELAY[15] | SYSMON.DI12 |
| CELL[6].IMUX_IMUX_DELAY[17] | SYSMON.DI13 |
| CELL[6].IMUX_IMUX_DELAY[19] | SYSMON.DI14 |
| CELL[6].IMUX_IMUX_DELAY[21] | SYSMON.DI15 |
| CELL[6].IMUX_IMUX_DELAY[23] | SYSMON.DADDR0 |
| CELL[6].IMUX_IMUX_DELAY[25] | SYSMON.DADDR1 |
| CELL[6].IMUX_IMUX_DELAY[27] | SYSMON.DADDR2 |
| CELL[6].IMUX_IMUX_DELAY[29] | SYSMON.DADDR3 |
| CELL[6].IMUX_IMUX_DELAY[31] | SYSMON.DADDR4 |
| CELL[6].IMUX_IMUX_DELAY[33] | SYSMON.DADDR5 |
| CELL[6].IMUX_IMUX_DELAY[35] | SYSMON.DADDR6 |
| CELL[6].IMUX_IMUX_DELAY[37] | SYSMON.DADDR7 |
| CELL[6].IMUX_IMUX_DELAY[39] | SYSMON.DWE |
| CELL[6].IMUX_IMUX_DELAY[41] | SYSMON.DEN |
| CELL[6].IMUX_IMUX_DELAY[43] | SYSMON.I2C_SDA_IN |
| CELL[6].IMUX_IMUX_DELAY[45] | SYSMON.I2C_SCLK_IN |
| CELL[6].IMUX_IMUX_DELAY[47] | SYSMON.CONVST |
| CELL[7].OUT_BEL[1] | SYSMON.ADC_DATA6 |
| CELL[7].OUT_BEL[3] | SYSMON.ADC_DATA7 |
| CELL[7].OUT_BEL[5] | SYSMON.ADC_DATA8 |
| CELL[7].OUT_BEL[7] | SYSMON.ADC_DATA9 |
| CELL[7].OUT_BEL[9] | SYSMON.ADC_DATA10 |
| CELL[7].OUT_BEL[11] | SYSMON.ADC_DATA11 |
| CELL[7].OUT_BEL[13] | SYSMON.ADC_DATA12 |
| CELL[7].OUT_BEL[15] | SYSMON.ADC_DATA13 |
| CELL[7].OUT_BEL[17] | SYSMON.ADC_DATA14 |
| CELL[7].OUT_BEL[19] | SYSMON.ADC_DATA15 |