Clock Management Tile
Tile CMT
Cells: 60
Bel BUFCE_ROW_CMT0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.17.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.18.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.19.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.20.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.21.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.22.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.23.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.24.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.25.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.26.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.27.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.28.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.29.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.30.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.31.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.32.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.33.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.34.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.35.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.36.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.37.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.38.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.39.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.40.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel GCLK_TEST_BUF_CMT0
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT1
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT2
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT3
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT4
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT5
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT6
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT7
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT8
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT9
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT10
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT11
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT12
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT13
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT14
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT15
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT16
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT17
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT18
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT19
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT20
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT21
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT22
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT23
| Pin | Direction | Wires |
|---|
Bel BUFGCE0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.31.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.24.DELAY |
Bel BUFGCE1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.32.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.25.DELAY |
Bel BUFGCE2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.33.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.26.DELAY |
Bel BUFGCE3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.34.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.27.DELAY |
Bel BUFGCE4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.35.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.28.DELAY |
Bel BUFGCE5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.36.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.29.DELAY |
Bel BUFGCE6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.37.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.30.DELAY |
Bel BUFGCE7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.38.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.31.DELAY |
Bel BUFGCE8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.39.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.32.DELAY |
Bel BUFGCE9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.40.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.33.DELAY |
Bel BUFGCE10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.41.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.34.DELAY |
Bel BUFGCE11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.42.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.35.DELAY |
Bel BUFGCE12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.43.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.36.DELAY |
Bel BUFGCE13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.44.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.37.DELAY |
Bel BUFGCE14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.45.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.38.DELAY |
Bel BUFGCE15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.46.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.39.DELAY |
Bel BUFGCE16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.47.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.40.DELAY |
Bel BUFGCE17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.17.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.41.DELAY |
Bel BUFGCE18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.18.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.42.DELAY |
Bel BUFGCE19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.19.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.43.DELAY |
Bel BUFGCE20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.20.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.44.DELAY |
Bel BUFGCE21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.21.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.45.DELAY |
Bel BUFGCE22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.22.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.46.DELAY |
Bel BUFGCE23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.23.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL0
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.23.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.46.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.38.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.30.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.22.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.45.DELAY |
Bel BUFGCTRL1
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.24.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.47.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.39.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.31.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.23.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.46.DELAY |
Bel BUFGCTRL2
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.25.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.17.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.40.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.32.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.24.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL3
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.26.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.18.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.41.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.33.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.25.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.17.DELAY |
Bel BUFGCTRL4
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.27.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.19.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.42.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.34.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.26.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.18.DELAY |
Bel BUFGCTRL5
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.28.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.20.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.43.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.35.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.27.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.19.DELAY |
Bel BUFGCTRL6
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.29.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.21.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.44.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.36.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.28.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.20.DELAY |
Bel BUFGCTRL7
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.30.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.22.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.45.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.37.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.29.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.21.DELAY |
Bel BUFGCE_DIV0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.41.DELAY |
| RST_PRE_OPTINV | input | TCELL28:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.42.DELAY |
| RST_PRE_OPTINV | input | TCELL29:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.43.DELAY |
| RST_PRE_OPTINV | input | TCELL30:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.44.DELAY |
| RST_PRE_OPTINV | input | TCELL31:IMUX.IMUX.0.DELAY |
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL1:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL9:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL9:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL9:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL9:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL8:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL8:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL8:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL11:IMUX.CTRL.0 |
| DEN | input | TCELL11:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL13:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL13:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL11:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL11:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL10:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL10:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL10:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL10:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL13:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL13:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL12:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL12:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL12:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL12:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL11:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL11:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL12:OUT.0 |
| DOUT1 | output | TCELL12:OUT.1 |
| DOUT10 | output | TCELL9:OUT.1 |
| DOUT11 | output | TCELL9:OUT.2 |
| DOUT12 | output | TCELL8:OUT.0 |
| DOUT13 | output | TCELL8:OUT.1 |
| DOUT14 | output | TCELL8:OUT.2 |
| DOUT15 | output | TCELL7:OUT.0 |
| DOUT2 | output | TCELL12:OUT.2 |
| DOUT3 | output | TCELL11:OUT.0 |
| DOUT4 | output | TCELL11:OUT.1 |
| DOUT5 | output | TCELL11:OUT.2 |
| DOUT6 | output | TCELL10:OUT.0 |
| DOUT7 | output | TCELL10:OUT.1 |
| DOUT8 | output | TCELL10:OUT.2 |
| DOUT9 | output | TCELL9:OUT.0 |
| DRDY | output | TCELL13:OUT.1 |
| DWE | input | TCELL10:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL13:OUT.0 |
| PWRDWN | input | TCELL12:IMUX.IMUX.0.DELAY |
| RST | input | TCELL13:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL13:IMUX.CTRL.0 |
| SCANENB | input | TCELL7:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL8:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL6:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL13:OUT.2 |
| TESTIN0 | input | TCELL7:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL7:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL5:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL5:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL4:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL4:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL4:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL4:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL3:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL3:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL3:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL3:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL7:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL2:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL2:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL2:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL2:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL1:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL1:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL1:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL1:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL0:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL0:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL7:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL0:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL0:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL6:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL6:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL6:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL6:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL5:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL5:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL7:OUT.1 |
| TESTOUT1 | output | TCELL7:OUT.2 |
| TESTOUT10 | output | TCELL4:OUT.2 |
| TESTOUT11 | output | TCELL3:OUT.0 |
| TESTOUT12 | output | TCELL3:OUT.1 |
| TESTOUT13 | output | TCELL3:OUT.2 |
| TESTOUT14 | output | TCELL2:OUT.0 |
| TESTOUT15 | output | TCELL2:OUT.1 |
| TESTOUT2 | output | TCELL6:OUT.0 |
| TESTOUT3 | output | TCELL6:OUT.1 |
| TESTOUT4 | output | TCELL6:OUT.2 |
| TESTOUT5 | output | TCELL5:OUT.0 |
| TESTOUT6 | output | TCELL5:OUT.1 |
| TESTOUT7 | output | TCELL5:OUT.2 |
| TESTOUT8 | output | TCELL4:OUT.0 |
| TESTOUT9 | output | TCELL4:OUT.1 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL15:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL23:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL23:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL23:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL23:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL22:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL22:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL22:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL25:IMUX.CTRL.0 |
| DEN | input | TCELL25:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL27:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL27:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL25:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL25:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL24:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL24:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL24:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL24:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL27:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL27:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL26:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL26:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL26:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL26:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL25:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL25:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL26:OUT.0 |
| DOUT1 | output | TCELL26:OUT.1 |
| DOUT10 | output | TCELL23:OUT.1 |
| DOUT11 | output | TCELL23:OUT.2 |
| DOUT12 | output | TCELL22:OUT.0 |
| DOUT13 | output | TCELL22:OUT.1 |
| DOUT14 | output | TCELL22:OUT.2 |
| DOUT15 | output | TCELL21:OUT.0 |
| DOUT2 | output | TCELL26:OUT.2 |
| DOUT3 | output | TCELL25:OUT.0 |
| DOUT4 | output | TCELL25:OUT.1 |
| DOUT5 | output | TCELL25:OUT.2 |
| DOUT6 | output | TCELL24:OUT.0 |
| DOUT7 | output | TCELL24:OUT.1 |
| DOUT8 | output | TCELL24:OUT.2 |
| DOUT9 | output | TCELL23:OUT.0 |
| DRDY | output | TCELL27:OUT.1 |
| DWE | input | TCELL24:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL27:OUT.0 |
| PWRDWN | input | TCELL26:IMUX.IMUX.0.DELAY |
| RST | input | TCELL27:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL27:IMUX.CTRL.0 |
| SCANENB | input | TCELL21:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL22:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL20:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL27:OUT.2 |
| TESTIN0 | input | TCELL21:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL21:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL19:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL19:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL18:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL18:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL18:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL18:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL17:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL17:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL17:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL17:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL21:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL16:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL16:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL16:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL16:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL15:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL15:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL15:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL15:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL14:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL14:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL21:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL14:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL14:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL20:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL20:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL20:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL20:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL19:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL19:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL21:OUT.1 |
| TESTOUT1 | output | TCELL21:OUT.2 |
| TESTOUT10 | output | TCELL18:OUT.2 |
| TESTOUT11 | output | TCELL17:OUT.0 |
| TESTOUT12 | output | TCELL17:OUT.1 |
| TESTOUT13 | output | TCELL17:OUT.2 |
| TESTOUT14 | output | TCELL16:OUT.0 |
| TESTOUT15 | output | TCELL16:OUT.1 |
| TESTOUT2 | output | TCELL20:OUT.0 |
| TESTOUT3 | output | TCELL20:OUT.1 |
| TESTOUT4 | output | TCELL20:OUT.2 |
| TESTOUT5 | output | TCELL19:OUT.0 |
| TESTOUT6 | output | TCELL19:OUT.1 |
| TESTOUT7 | output | TCELL19:OUT.2 |
| TESTOUT8 | output | TCELL18:OUT.0 |
| TESTOUT9 | output | TCELL18:OUT.1 |
Bel MMCM
| Pin | Direction | Wires |
|---|---|---|
| CDDCDONE | output | TCELL56:OUT.0 |
| CDDCREQ | input | TCELL50:IMUX.IMUX.0.DELAY |
| CLKFBSTOPPED | output | TCELL55:OUT.0 |
| CLKINSEL | input | TCELL41:IMUX.IMUX.0.DELAY |
| CLKINSTOPPED | output | TCELL55:OUT.1 |
| DADDR0 | input | TCELL50:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL50:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL50:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL50:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL49:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL49:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL49:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL52:IMUX.CTRL.0 |
| DEN | input | TCELL52:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL54:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL54:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL52:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL52:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL51:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL51:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL51:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL51:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL54:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL54:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL53:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL53:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL53:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL53:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL52:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL52:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL53:OUT.0 |
| DOUT1 | output | TCELL53:OUT.1 |
| DOUT10 | output | TCELL50:OUT.1 |
| DOUT11 | output | TCELL50:OUT.2 |
| DOUT12 | output | TCELL49:OUT.0 |
| DOUT13 | output | TCELL49:OUT.1 |
| DOUT14 | output | TCELL49:OUT.2 |
| DOUT15 | output | TCELL48:OUT.0 |
| DOUT2 | output | TCELL53:OUT.2 |
| DOUT3 | output | TCELL52:OUT.0 |
| DOUT4 | output | TCELL52:OUT.1 |
| DOUT5 | output | TCELL52:OUT.2 |
| DOUT6 | output | TCELL51:OUT.0 |
| DOUT7 | output | TCELL51:OUT.1 |
| DOUT8 | output | TCELL51:OUT.2 |
| DOUT9 | output | TCELL50:OUT.0 |
| DRDY | output | TCELL54:OUT.1 |
| DWE | input | TCELL51:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL54:OUT.0 |
| PSCLK | input | TCELL53:IMUX.CTRL.0 |
| PSDONE | output | TCELL55:OUT.2 |
| PSEN | input | TCELL56:IMUX.IMUX.0.DELAY |
| PSINCDEC | input | TCELL55:IMUX.IMUX.0.DELAY |
| PWRDWN | input | TCELL53:IMUX.IMUX.0.DELAY |
| RST | input | TCELL54:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL54:IMUX.CTRL.0 |
| SCANENB | input | TCELL48:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL49:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL47:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL54:OUT.2 |
| TESTIN0 | input | TCELL48:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL48:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL46:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL46:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL45:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL45:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL45:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL45:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL44:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL44:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL44:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL44:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL48:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL43:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL43:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL43:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL43:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL42:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL42:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL42:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL42:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL41:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL41:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL48:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL41:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL41:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL47:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL47:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL47:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL47:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL46:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL46:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL48:OUT.1 |
| TESTOUT1 | output | TCELL48:OUT.2 |
| TESTOUT10 | output | TCELL45:OUT.2 |
| TESTOUT11 | output | TCELL44:OUT.0 |
| TESTOUT12 | output | TCELL44:OUT.1 |
| TESTOUT13 | output | TCELL44:OUT.2 |
| TESTOUT14 | output | TCELL43:OUT.0 |
| TESTOUT15 | output | TCELL43:OUT.1 |
| TESTOUT2 | output | TCELL47:OUT.0 |
| TESTOUT3 | output | TCELL47:OUT.1 |
| TESTOUT4 | output | TCELL47:OUT.2 |
| TESTOUT5 | output | TCELL46:OUT.0 |
| TESTOUT6 | output | TCELL46:OUT.1 |
| TESTOUT7 | output | TCELL46:OUT.2 |
| TESTOUT8 | output | TCELL45:OUT.0 |
| TESTOUT9 | output | TCELL45:OUT.1 |
Bel CMT
| Pin | Direction | Wires |
|---|
Bel VCC_CMT
| Pin | Direction | Wires |
|---|
Bel ABUS_SWITCH_CMT
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL32:IMUX.IMUX.0.DELAY |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.BYP.0.DELAY | PLL0.TESTIN28 |
| TCELL0:IMUX.BYP.1.DELAY | PLL0.TESTIN29 |
| TCELL0:IMUX.BYP.2.DELAY | PLL0.TESTIN30 |
| TCELL0:IMUX.BYP.3.DELAY | PLL0.TESTIN31 |
| TCELL1:IMUX.BYP.0.DELAY | PLL0.TESTIN24 |
| TCELL1:IMUX.BYP.1.DELAY | PLL0.TESTIN25 |
| TCELL1:IMUX.BYP.2.DELAY | PLL0.TESTIN26 |
| TCELL1:IMUX.BYP.3.DELAY | PLL0.TESTIN27 |
| TCELL1:IMUX.IMUX.0.DELAY | PLL0.CLKOUTPHY_EN |
| TCELL2:OUT.0 | PLL0.TESTOUT14 |
| TCELL2:OUT.1 | PLL0.TESTOUT15 |
| TCELL2:IMUX.BYP.0.DELAY | PLL0.TESTIN20 |
| TCELL2:IMUX.BYP.1.DELAY | PLL0.TESTIN21 |
| TCELL2:IMUX.BYP.2.DELAY | PLL0.TESTIN22 |
| TCELL2:IMUX.BYP.3.DELAY | PLL0.TESTIN23 |
| TCELL3:OUT.0 | PLL0.TESTOUT11 |
| TCELL3:OUT.1 | PLL0.TESTOUT12 |
| TCELL3:OUT.2 | PLL0.TESTOUT13 |
| TCELL3:IMUX.BYP.0.DELAY | PLL0.TESTIN16 |
| TCELL3:IMUX.BYP.1.DELAY | PLL0.TESTIN17 |
| TCELL3:IMUX.BYP.2.DELAY | PLL0.TESTIN18 |
| TCELL3:IMUX.BYP.3.DELAY | PLL0.TESTIN19 |
| TCELL4:OUT.0 | PLL0.TESTOUT8 |
| TCELL4:OUT.1 | PLL0.TESTOUT9 |
| TCELL4:OUT.2 | PLL0.TESTOUT10 |
| TCELL4:IMUX.BYP.0.DELAY | PLL0.TESTIN12 |
| TCELL4:IMUX.BYP.1.DELAY | PLL0.TESTIN13 |
| TCELL4:IMUX.BYP.2.DELAY | PLL0.TESTIN14 |
| TCELL4:IMUX.BYP.3.DELAY | PLL0.TESTIN15 |
| TCELL5:OUT.0 | PLL0.TESTOUT5 |
| TCELL5:OUT.1 | PLL0.TESTOUT6 |
| TCELL5:OUT.2 | PLL0.TESTOUT7 |
| TCELL5:IMUX.BYP.0.DELAY | PLL0.TESTIN8 |
| TCELL5:IMUX.BYP.1.DELAY | PLL0.TESTIN9 |
| TCELL5:IMUX.BYP.2.DELAY | PLL0.TESTIN10 |
| TCELL5:IMUX.BYP.3.DELAY | PLL0.TESTIN11 |
| TCELL6:OUT.0 | PLL0.TESTOUT2 |
| TCELL6:OUT.1 | PLL0.TESTOUT3 |
| TCELL6:OUT.2 | PLL0.TESTOUT4 |
| TCELL6:IMUX.BYP.0.DELAY | PLL0.TESTIN4 |
| TCELL6:IMUX.BYP.1.DELAY | PLL0.TESTIN5 |
| TCELL6:IMUX.BYP.2.DELAY | PLL0.TESTIN6 |
| TCELL6:IMUX.BYP.3.DELAY | PLL0.TESTIN7 |
| TCELL6:IMUX.IMUX.0.DELAY | PLL0.SCANMODEB |
| TCELL7:OUT.0 | PLL0.DOUT15 |
| TCELL7:OUT.1 | PLL0.TESTOUT0 |
| TCELL7:OUT.2 | PLL0.TESTOUT1 |
| TCELL7:IMUX.BYP.0.DELAY | PLL0.TESTIN0 |
| TCELL7:IMUX.BYP.1.DELAY | PLL0.TESTIN1 |
| TCELL7:IMUX.BYP.2.DELAY | PLL0.TESTIN2 |
| TCELL7:IMUX.BYP.3.DELAY | PLL0.TESTIN3 |
| TCELL7:IMUX.IMUX.0.DELAY | PLL0.SCANENB |
| TCELL8:OUT.0 | PLL0.DOUT12 |
| TCELL8:OUT.1 | PLL0.DOUT13 |
| TCELL8:OUT.2 | PLL0.DOUT14 |
| TCELL8:IMUX.BYP.0.DELAY | PLL0.DADDR4 |
| TCELL8:IMUX.BYP.1.DELAY | PLL0.DADDR5 |
| TCELL8:IMUX.BYP.2.DELAY | PLL0.DADDR6 |
| TCELL8:IMUX.IMUX.0.DELAY | PLL0.SCANIN |
| TCELL9:OUT.0 | PLL0.DOUT9 |
| TCELL9:OUT.1 | PLL0.DOUT10 |
| TCELL9:OUT.2 | PLL0.DOUT11 |
| TCELL9:IMUX.BYP.0.DELAY | PLL0.DADDR0 |
| TCELL9:IMUX.BYP.1.DELAY | PLL0.DADDR1 |
| TCELL9:IMUX.BYP.2.DELAY | PLL0.DADDR2 |
| TCELL9:IMUX.BYP.3.DELAY | PLL0.DADDR3 |
| TCELL10:OUT.0 | PLL0.DOUT6 |
| TCELL10:OUT.1 | PLL0.DOUT7 |
| TCELL10:OUT.2 | PLL0.DOUT8 |
| TCELL10:IMUX.BYP.0.DELAY | PLL0.DI12 |
| TCELL10:IMUX.BYP.1.DELAY | PLL0.DI13 |
| TCELL10:IMUX.BYP.2.DELAY | PLL0.DI14 |
| TCELL10:IMUX.BYP.3.DELAY | PLL0.DI15 |
| TCELL10:IMUX.IMUX.0.DELAY | PLL0.DWE |
| TCELL11:OUT.0 | PLL0.DOUT3 |
| TCELL11:OUT.1 | PLL0.DOUT4 |
| TCELL11:OUT.2 | PLL0.DOUT5 |
| TCELL11:IMUX.CTRL.0 | PLL0.DCLK |
| TCELL11:IMUX.BYP.0.DELAY | PLL0.DI8 |
| TCELL11:IMUX.BYP.1.DELAY | PLL0.DI9 |
| TCELL11:IMUX.BYP.2.DELAY | PLL0.DI10 |
| TCELL11:IMUX.BYP.3.DELAY | PLL0.DI11 |
| TCELL11:IMUX.IMUX.0.DELAY | PLL0.DEN |
| TCELL12:OUT.0 | PLL0.DOUT0 |
| TCELL12:OUT.1 | PLL0.DOUT1 |
| TCELL12:OUT.2 | PLL0.DOUT2 |
| TCELL12:IMUX.BYP.0.DELAY | PLL0.DI4 |
| TCELL12:IMUX.BYP.1.DELAY | PLL0.DI5 |
| TCELL12:IMUX.BYP.2.DELAY | PLL0.DI6 |
| TCELL12:IMUX.BYP.3.DELAY | PLL0.DI7 |
| TCELL12:IMUX.IMUX.0.DELAY | PLL0.PWRDWN |
| TCELL13:OUT.0 | PLL0.LOCKED |
| TCELL13:OUT.1 | PLL0.DRDY |
| TCELL13:OUT.2 | PLL0.SCANOUT |
| TCELL13:IMUX.CTRL.0 | PLL0.SCANCLK |
| TCELL13:IMUX.BYP.0.DELAY | PLL0.DI0 |
| TCELL13:IMUX.BYP.1.DELAY | PLL0.DI1 |
| TCELL13:IMUX.BYP.2.DELAY | PLL0.DI2 |
| TCELL13:IMUX.BYP.3.DELAY | PLL0.DI3 |
| TCELL13:IMUX.IMUX.0.DELAY | PLL0.RST |
| TCELL14:IMUX.BYP.0.DELAY | PLL1.TESTIN28 |
| TCELL14:IMUX.BYP.1.DELAY | PLL1.TESTIN29 |
| TCELL14:IMUX.BYP.2.DELAY | PLL1.TESTIN30 |
| TCELL14:IMUX.BYP.3.DELAY | PLL1.TESTIN31 |
| TCELL15:IMUX.BYP.0.DELAY | PLL1.TESTIN24 |
| TCELL15:IMUX.BYP.1.DELAY | PLL1.TESTIN25 |
| TCELL15:IMUX.BYP.2.DELAY | PLL1.TESTIN26 |
| TCELL15:IMUX.BYP.3.DELAY | PLL1.TESTIN27 |
| TCELL15:IMUX.IMUX.0.DELAY | PLL1.CLKOUTPHY_EN |
| TCELL16:OUT.0 | PLL1.TESTOUT14 |
| TCELL16:OUT.1 | PLL1.TESTOUT15 |
| TCELL16:IMUX.BYP.0.DELAY | PLL1.TESTIN20 |
| TCELL16:IMUX.BYP.1.DELAY | PLL1.TESTIN21 |
| TCELL16:IMUX.BYP.2.DELAY | PLL1.TESTIN22 |
| TCELL16:IMUX.BYP.3.DELAY | PLL1.TESTIN23 |
| TCELL17:OUT.0 | PLL1.TESTOUT11 |
| TCELL17:OUT.1 | PLL1.TESTOUT12 |
| TCELL17:OUT.2 | PLL1.TESTOUT13 |
| TCELL17:IMUX.BYP.0.DELAY | PLL1.TESTIN16 |
| TCELL17:IMUX.BYP.1.DELAY | PLL1.TESTIN17 |
| TCELL17:IMUX.BYP.2.DELAY | PLL1.TESTIN18 |
| TCELL17:IMUX.BYP.3.DELAY | PLL1.TESTIN19 |
| TCELL18:OUT.0 | PLL1.TESTOUT8 |
| TCELL18:OUT.1 | PLL1.TESTOUT9 |
| TCELL18:OUT.2 | PLL1.TESTOUT10 |
| TCELL18:IMUX.BYP.0.DELAY | PLL1.TESTIN12 |
| TCELL18:IMUX.BYP.1.DELAY | PLL1.TESTIN13 |
| TCELL18:IMUX.BYP.2.DELAY | PLL1.TESTIN14 |
| TCELL18:IMUX.BYP.3.DELAY | PLL1.TESTIN15 |
| TCELL19:OUT.0 | PLL1.TESTOUT5 |
| TCELL19:OUT.1 | PLL1.TESTOUT6 |
| TCELL19:OUT.2 | PLL1.TESTOUT7 |
| TCELL19:IMUX.BYP.0.DELAY | PLL1.TESTIN8 |
| TCELL19:IMUX.BYP.1.DELAY | PLL1.TESTIN9 |
| TCELL19:IMUX.BYP.2.DELAY | PLL1.TESTIN10 |
| TCELL19:IMUX.BYP.3.DELAY | PLL1.TESTIN11 |
| TCELL20:OUT.0 | PLL1.TESTOUT2 |
| TCELL20:OUT.1 | PLL1.TESTOUT3 |
| TCELL20:OUT.2 | PLL1.TESTOUT4 |
| TCELL20:IMUX.BYP.0.DELAY | PLL1.TESTIN4 |
| TCELL20:IMUX.BYP.1.DELAY | PLL1.TESTIN5 |
| TCELL20:IMUX.BYP.2.DELAY | PLL1.TESTIN6 |
| TCELL20:IMUX.BYP.3.DELAY | PLL1.TESTIN7 |
| TCELL20:IMUX.IMUX.0.DELAY | PLL1.SCANMODEB |
| TCELL21:OUT.0 | PLL1.DOUT15 |
| TCELL21:OUT.1 | PLL1.TESTOUT0 |
| TCELL21:OUT.2 | PLL1.TESTOUT1 |
| TCELL21:IMUX.BYP.0.DELAY | PLL1.TESTIN0 |
| TCELL21:IMUX.BYP.1.DELAY | PLL1.TESTIN1 |
| TCELL21:IMUX.BYP.2.DELAY | PLL1.TESTIN2 |
| TCELL21:IMUX.BYP.3.DELAY | PLL1.TESTIN3 |
| TCELL21:IMUX.IMUX.0.DELAY | PLL1.SCANENB |
| TCELL22:OUT.0 | PLL1.DOUT12 |
| TCELL22:OUT.1 | PLL1.DOUT13 |
| TCELL22:OUT.2 | PLL1.DOUT14 |
| TCELL22:IMUX.BYP.0.DELAY | PLL1.DADDR4 |
| TCELL22:IMUX.BYP.1.DELAY | PLL1.DADDR5 |
| TCELL22:IMUX.BYP.2.DELAY | PLL1.DADDR6 |
| TCELL22:IMUX.IMUX.0.DELAY | PLL1.SCANIN |
| TCELL23:OUT.0 | PLL1.DOUT9 |
| TCELL23:OUT.1 | PLL1.DOUT10 |
| TCELL23:OUT.2 | PLL1.DOUT11 |
| TCELL23:IMUX.BYP.0.DELAY | PLL1.DADDR0 |
| TCELL23:IMUX.BYP.1.DELAY | PLL1.DADDR1 |
| TCELL23:IMUX.BYP.2.DELAY | PLL1.DADDR2 |
| TCELL23:IMUX.BYP.3.DELAY | PLL1.DADDR3 |
| TCELL24:OUT.0 | PLL1.DOUT6 |
| TCELL24:OUT.1 | PLL1.DOUT7 |
| TCELL24:OUT.2 | PLL1.DOUT8 |
| TCELL24:IMUX.BYP.0.DELAY | PLL1.DI12 |
| TCELL24:IMUX.BYP.1.DELAY | PLL1.DI13 |
| TCELL24:IMUX.BYP.2.DELAY | PLL1.DI14 |
| TCELL24:IMUX.BYP.3.DELAY | PLL1.DI15 |
| TCELL24:IMUX.IMUX.0.DELAY | PLL1.DWE |
| TCELL25:OUT.0 | PLL1.DOUT3 |
| TCELL25:OUT.1 | PLL1.DOUT4 |
| TCELL25:OUT.2 | PLL1.DOUT5 |
| TCELL25:IMUX.CTRL.0 | PLL1.DCLK |
| TCELL25:IMUX.BYP.0.DELAY | PLL1.DI8 |
| TCELL25:IMUX.BYP.1.DELAY | PLL1.DI9 |
| TCELL25:IMUX.BYP.2.DELAY | PLL1.DI10 |
| TCELL25:IMUX.BYP.3.DELAY | PLL1.DI11 |
| TCELL25:IMUX.IMUX.0.DELAY | PLL1.DEN |
| TCELL26:OUT.0 | PLL1.DOUT0 |
| TCELL26:OUT.1 | PLL1.DOUT1 |
| TCELL26:OUT.2 | PLL1.DOUT2 |
| TCELL26:IMUX.BYP.0.DELAY | PLL1.DI4 |
| TCELL26:IMUX.BYP.1.DELAY | PLL1.DI5 |
| TCELL26:IMUX.BYP.2.DELAY | PLL1.DI6 |
| TCELL26:IMUX.BYP.3.DELAY | PLL1.DI7 |
| TCELL26:IMUX.IMUX.0.DELAY | PLL1.PWRDWN |
| TCELL27:OUT.0 | PLL1.LOCKED |
| TCELL27:OUT.1 | PLL1.DRDY |
| TCELL27:OUT.2 | PLL1.SCANOUT |
| TCELL27:IMUX.CTRL.0 | PLL1.SCANCLK |
| TCELL27:IMUX.BYP.0.DELAY | PLL1.DI0 |
| TCELL27:IMUX.BYP.1.DELAY | PLL1.DI1 |
| TCELL27:IMUX.BYP.2.DELAY | PLL1.DI2 |
| TCELL27:IMUX.BYP.3.DELAY | PLL1.DI3 |
| TCELL27:IMUX.IMUX.0.DELAY | PLL1.RST |
| TCELL28:IMUX.IMUX.0.DELAY | BUFGCE_DIV0.RST_PRE_OPTINV |
| TCELL28:IMUX.IMUX.17.DELAY | BUFCE_ROW_CMT0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.18.DELAY | BUFCE_ROW_CMT1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.19.DELAY | BUFCE_ROW_CMT2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.20.DELAY | BUFCE_ROW_CMT3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.21.DELAY | BUFCE_ROW_CMT4.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.22.DELAY | BUFCE_ROW_CMT5.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.23.DELAY | BUFCE_ROW_CMT6.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.24.DELAY | BUFCE_ROW_CMT7.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.25.DELAY | BUFCE_ROW_CMT8.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.26.DELAY | BUFCE_ROW_CMT9.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.27.DELAY | BUFCE_ROW_CMT10.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.28.DELAY | BUFCE_ROW_CMT11.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.29.DELAY | BUFCE_ROW_CMT12.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.30.DELAY | BUFCE_ROW_CMT13.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.31.DELAY | BUFCE_ROW_CMT14.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.32.DELAY | BUFCE_ROW_CMT15.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.33.DELAY | BUFCE_ROW_CMT16.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.34.DELAY | BUFCE_ROW_CMT17.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.35.DELAY | BUFCE_ROW_CMT18.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.36.DELAY | BUFCE_ROW_CMT19.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.37.DELAY | BUFCE_ROW_CMT20.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.38.DELAY | BUFCE_ROW_CMT21.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.39.DELAY | BUFCE_ROW_CMT22.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.40.DELAY | BUFCE_ROW_CMT23.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.41.DELAY | BUFGCE_DIV0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.42.DELAY | BUFGCE_DIV1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.43.DELAY | BUFGCE_DIV2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.44.DELAY | BUFGCE_DIV3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.45.DELAY | BUFGCTRL0.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.46.DELAY | BUFGCTRL1.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.47.DELAY | BUFGCTRL2.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.0.DELAY | BUFGCE_DIV1.RST_PRE_OPTINV |
| TCELL29:IMUX.IMUX.17.DELAY | BUFGCTRL3.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.18.DELAY | BUFGCTRL4.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.19.DELAY | BUFGCTRL5.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.20.DELAY | BUFGCTRL6.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.21.DELAY | BUFGCTRL7.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.22.DELAY | BUFGCTRL0.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.23.DELAY | BUFGCTRL1.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.24.DELAY | BUFGCTRL2.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.25.DELAY | BUFGCTRL3.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.26.DELAY | BUFGCTRL4.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.27.DELAY | BUFGCTRL5.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.28.DELAY | BUFGCTRL6.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.29.DELAY | BUFGCTRL7.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.30.DELAY | BUFGCTRL0.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.31.DELAY | BUFGCTRL1.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.32.DELAY | BUFGCTRL2.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.33.DELAY | BUFGCTRL3.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.34.DELAY | BUFGCTRL4.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.35.DELAY | BUFGCTRL5.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.36.DELAY | BUFGCTRL6.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.37.DELAY | BUFGCTRL7.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.38.DELAY | BUFGCTRL0.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.39.DELAY | BUFGCTRL1.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.40.DELAY | BUFGCTRL2.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.41.DELAY | BUFGCTRL3.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.42.DELAY | BUFGCTRL4.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.43.DELAY | BUFGCTRL5.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.44.DELAY | BUFGCTRL6.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.45.DELAY | BUFGCTRL7.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.46.DELAY | BUFGCTRL0.CE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.47.DELAY | BUFGCTRL1.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.0.DELAY | BUFGCE_DIV2.RST_PRE_OPTINV |
| TCELL30:IMUX.IMUX.17.DELAY | BUFGCTRL2.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.18.DELAY | BUFGCTRL3.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.19.DELAY | BUFGCTRL4.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.20.DELAY | BUFGCTRL5.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.21.DELAY | BUFGCTRL6.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.22.DELAY | BUFGCTRL7.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.23.DELAY | BUFGCTRL0.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.24.DELAY | BUFGCTRL1.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.25.DELAY | BUFGCTRL2.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.26.DELAY | BUFGCTRL3.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.27.DELAY | BUFGCTRL4.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.28.DELAY | BUFGCTRL5.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.29.DELAY | BUFGCTRL6.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.30.DELAY | BUFGCTRL7.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.31.DELAY | BUFGCE0.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.32.DELAY | BUFGCE1.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.33.DELAY | BUFGCE2.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.34.DELAY | BUFGCE3.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.35.DELAY | BUFGCE4.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.36.DELAY | BUFGCE5.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.37.DELAY | BUFGCE6.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.38.DELAY | BUFGCE7.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.39.DELAY | BUFGCE8.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.40.DELAY | BUFGCE9.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.41.DELAY | BUFGCE10.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.42.DELAY | BUFGCE11.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.43.DELAY | BUFGCE12.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.44.DELAY | BUFGCE13.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.45.DELAY | BUFGCE14.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.46.DELAY | BUFGCE15.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.47.DELAY | BUFGCE16.CE_PRE_OPTINV |
| TCELL30:RCLK.IMUX.16 | BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.17 | BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.18 | BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.19 | BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.20 | BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2 |
| TCELL30:RCLK.IMUX.21 | BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2 |
| TCELL31:IMUX.IMUX.0.DELAY | BUFGCE_DIV3.RST_PRE_OPTINV |
| TCELL31:IMUX.IMUX.17.DELAY | BUFGCE17.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.18.DELAY | BUFGCE18.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.19.DELAY | BUFGCE19.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.20.DELAY | BUFGCE20.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.21.DELAY | BUFGCE21.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.22.DELAY | BUFGCE22.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.23.DELAY | BUFGCE23.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.24.DELAY | BUFGCE0.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.25.DELAY | BUFGCE1.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.26.DELAY | BUFGCE2.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.27.DELAY | BUFGCE3.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.28.DELAY | BUFGCE4.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.29.DELAY | BUFGCE5.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.30.DELAY | BUFGCE6.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.31.DELAY | BUFGCE7.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.32.DELAY | BUFGCE8.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.33.DELAY | BUFGCE9.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.34.DELAY | BUFGCE10.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.35.DELAY | BUFGCE11.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.36.DELAY | BUFGCE12.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.37.DELAY | BUFGCE13.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.38.DELAY | BUFGCE14.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.39.DELAY | BUFGCE15.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.40.DELAY | BUFGCE16.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.41.DELAY | BUFGCE17.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.42.DELAY | BUFGCE18.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.43.DELAY | BUFGCE19.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.44.DELAY | BUFGCE20.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.45.DELAY | BUFGCE21.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.46.DELAY | BUFGCE22.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.47.DELAY | BUFGCE23.CLK_IN_CKINT |
| TCELL32:IMUX.IMUX.0.DELAY | ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B |
| TCELL41:IMUX.BYP.0.DELAY | MMCM.TESTIN28 |
| TCELL41:IMUX.BYP.1.DELAY | MMCM.TESTIN29 |
| TCELL41:IMUX.BYP.2.DELAY | MMCM.TESTIN30 |
| TCELL41:IMUX.BYP.3.DELAY | MMCM.TESTIN31 |
| TCELL41:IMUX.IMUX.0.DELAY | MMCM.CLKINSEL |
| TCELL42:IMUX.BYP.0.DELAY | MMCM.TESTIN24 |
| TCELL42:IMUX.BYP.1.DELAY | MMCM.TESTIN25 |
| TCELL42:IMUX.BYP.2.DELAY | MMCM.TESTIN26 |
| TCELL42:IMUX.BYP.3.DELAY | MMCM.TESTIN27 |
| TCELL43:OUT.0 | MMCM.TESTOUT14 |
| TCELL43:OUT.1 | MMCM.TESTOUT15 |
| TCELL43:IMUX.BYP.0.DELAY | MMCM.TESTIN20 |
| TCELL43:IMUX.BYP.1.DELAY | MMCM.TESTIN21 |
| TCELL43:IMUX.BYP.2.DELAY | MMCM.TESTIN22 |
| TCELL43:IMUX.BYP.3.DELAY | MMCM.TESTIN23 |
| TCELL44:OUT.0 | MMCM.TESTOUT11 |
| TCELL44:OUT.1 | MMCM.TESTOUT12 |
| TCELL44:OUT.2 | MMCM.TESTOUT13 |
| TCELL44:IMUX.BYP.0.DELAY | MMCM.TESTIN16 |
| TCELL44:IMUX.BYP.1.DELAY | MMCM.TESTIN17 |
| TCELL44:IMUX.BYP.2.DELAY | MMCM.TESTIN18 |
| TCELL44:IMUX.BYP.3.DELAY | MMCM.TESTIN19 |
| TCELL45:OUT.0 | MMCM.TESTOUT8 |
| TCELL45:OUT.1 | MMCM.TESTOUT9 |
| TCELL45:OUT.2 | MMCM.TESTOUT10 |
| TCELL45:IMUX.BYP.0.DELAY | MMCM.TESTIN12 |
| TCELL45:IMUX.BYP.1.DELAY | MMCM.TESTIN13 |
| TCELL45:IMUX.BYP.2.DELAY | MMCM.TESTIN14 |
| TCELL45:IMUX.BYP.3.DELAY | MMCM.TESTIN15 |
| TCELL46:OUT.0 | MMCM.TESTOUT5 |
| TCELL46:OUT.1 | MMCM.TESTOUT6 |
| TCELL46:OUT.2 | MMCM.TESTOUT7 |
| TCELL46:IMUX.BYP.0.DELAY | MMCM.TESTIN8 |
| TCELL46:IMUX.BYP.1.DELAY | MMCM.TESTIN9 |
| TCELL46:IMUX.BYP.2.DELAY | MMCM.TESTIN10 |
| TCELL46:IMUX.BYP.3.DELAY | MMCM.TESTIN11 |
| TCELL47:OUT.0 | MMCM.TESTOUT2 |
| TCELL47:OUT.1 | MMCM.TESTOUT3 |
| TCELL47:OUT.2 | MMCM.TESTOUT4 |
| TCELL47:IMUX.BYP.0.DELAY | MMCM.TESTIN4 |
| TCELL47:IMUX.BYP.1.DELAY | MMCM.TESTIN5 |
| TCELL47:IMUX.BYP.2.DELAY | MMCM.TESTIN6 |
| TCELL47:IMUX.BYP.3.DELAY | MMCM.TESTIN7 |
| TCELL47:IMUX.IMUX.0.DELAY | MMCM.SCANMODEB |
| TCELL48:OUT.0 | MMCM.DOUT15 |
| TCELL48:OUT.1 | MMCM.TESTOUT0 |
| TCELL48:OUT.2 | MMCM.TESTOUT1 |
| TCELL48:IMUX.BYP.0.DELAY | MMCM.TESTIN0 |
| TCELL48:IMUX.BYP.1.DELAY | MMCM.TESTIN1 |
| TCELL48:IMUX.BYP.2.DELAY | MMCM.TESTIN2 |
| TCELL48:IMUX.BYP.3.DELAY | MMCM.TESTIN3 |
| TCELL48:IMUX.IMUX.0.DELAY | MMCM.SCANENB |
| TCELL49:OUT.0 | MMCM.DOUT12 |
| TCELL49:OUT.1 | MMCM.DOUT13 |
| TCELL49:OUT.2 | MMCM.DOUT14 |
| TCELL49:IMUX.BYP.0.DELAY | MMCM.DADDR4 |
| TCELL49:IMUX.BYP.1.DELAY | MMCM.DADDR5 |
| TCELL49:IMUX.BYP.2.DELAY | MMCM.DADDR6 |
| TCELL49:IMUX.IMUX.0.DELAY | MMCM.SCANIN |
| TCELL50:OUT.0 | MMCM.DOUT9 |
| TCELL50:OUT.1 | MMCM.DOUT10 |
| TCELL50:OUT.2 | MMCM.DOUT11 |
| TCELL50:IMUX.BYP.0.DELAY | MMCM.DADDR0 |
| TCELL50:IMUX.BYP.1.DELAY | MMCM.DADDR1 |
| TCELL50:IMUX.BYP.2.DELAY | MMCM.DADDR2 |
| TCELL50:IMUX.BYP.3.DELAY | MMCM.DADDR3 |
| TCELL50:IMUX.IMUX.0.DELAY | MMCM.CDDCREQ |
| TCELL51:OUT.0 | MMCM.DOUT6 |
| TCELL51:OUT.1 | MMCM.DOUT7 |
| TCELL51:OUT.2 | MMCM.DOUT8 |
| TCELL51:IMUX.BYP.0.DELAY | MMCM.DI12 |
| TCELL51:IMUX.BYP.1.DELAY | MMCM.DI13 |
| TCELL51:IMUX.BYP.2.DELAY | MMCM.DI14 |
| TCELL51:IMUX.BYP.3.DELAY | MMCM.DI15 |
| TCELL51:IMUX.IMUX.0.DELAY | MMCM.DWE |
| TCELL52:OUT.0 | MMCM.DOUT3 |
| TCELL52:OUT.1 | MMCM.DOUT4 |
| TCELL52:OUT.2 | MMCM.DOUT5 |
| TCELL52:IMUX.CTRL.0 | MMCM.DCLK |
| TCELL52:IMUX.BYP.0.DELAY | MMCM.DI8 |
| TCELL52:IMUX.BYP.1.DELAY | MMCM.DI9 |
| TCELL52:IMUX.BYP.2.DELAY | MMCM.DI10 |
| TCELL52:IMUX.BYP.3.DELAY | MMCM.DI11 |
| TCELL52:IMUX.IMUX.0.DELAY | MMCM.DEN |
| TCELL53:OUT.0 | MMCM.DOUT0 |
| TCELL53:OUT.1 | MMCM.DOUT1 |
| TCELL53:OUT.2 | MMCM.DOUT2 |
| TCELL53:IMUX.CTRL.0 | MMCM.PSCLK |
| TCELL53:IMUX.BYP.0.DELAY | MMCM.DI4 |
| TCELL53:IMUX.BYP.1.DELAY | MMCM.DI5 |
| TCELL53:IMUX.BYP.2.DELAY | MMCM.DI6 |
| TCELL53:IMUX.BYP.3.DELAY | MMCM.DI7 |
| TCELL53:IMUX.IMUX.0.DELAY | MMCM.PWRDWN |
| TCELL54:OUT.0 | MMCM.LOCKED |
| TCELL54:OUT.1 | MMCM.DRDY |
| TCELL54:OUT.2 | MMCM.SCANOUT |
| TCELL54:IMUX.CTRL.0 | MMCM.SCANCLK |
| TCELL54:IMUX.BYP.0.DELAY | MMCM.DI0 |
| TCELL54:IMUX.BYP.1.DELAY | MMCM.DI1 |
| TCELL54:IMUX.BYP.2.DELAY | MMCM.DI2 |
| TCELL54:IMUX.BYP.3.DELAY | MMCM.DI3 |
| TCELL54:IMUX.IMUX.0.DELAY | MMCM.RST |
| TCELL55:OUT.0 | MMCM.CLKFBSTOPPED |
| TCELL55:OUT.1 | MMCM.CLKINSTOPPED |
| TCELL55:OUT.2 | MMCM.PSDONE |
| TCELL55:IMUX.IMUX.0.DELAY | MMCM.PSINCDEC |
| TCELL56:OUT.0 | MMCM.CDDCDONE |
| TCELL56:IMUX.IMUX.0.DELAY | MMCM.PSEN |
Tile CMT_HBM
Cells: 60
Bel BUFCE_ROW_CMT0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.17.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.18.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.19.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.20.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.21.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.22.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.23.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.24.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.25.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.26.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.27.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.28.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.29.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.30.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.31.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.32.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.33.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.34.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.35.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.36.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.37.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.38.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.39.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.40.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel GCLK_TEST_BUF_CMT0
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT1
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT2
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT3
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT4
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT5
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT6
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT7
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT8
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT9
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT10
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT11
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT12
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT13
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT14
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT15
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT16
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT17
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT18
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT19
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT20
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT21
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT22
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT23
| Pin | Direction | Wires |
|---|
Bel BUFGCE0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.31.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.24.DELAY |
Bel BUFGCE1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.32.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.25.DELAY |
Bel BUFGCE2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.33.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.26.DELAY |
Bel BUFGCE3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.34.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.27.DELAY |
Bel BUFGCE4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.35.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.28.DELAY |
Bel BUFGCE5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.36.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.29.DELAY |
Bel BUFGCE6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.37.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.30.DELAY |
Bel BUFGCE7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.38.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.31.DELAY |
Bel BUFGCE8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.39.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.32.DELAY |
Bel BUFGCE9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.40.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.33.DELAY |
Bel BUFGCE10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.41.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.34.DELAY |
Bel BUFGCE11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.42.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.35.DELAY |
Bel BUFGCE12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.43.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.36.DELAY |
Bel BUFGCE13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.44.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.37.DELAY |
Bel BUFGCE14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.45.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.38.DELAY |
Bel BUFGCE15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.46.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.39.DELAY |
Bel BUFGCE16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.47.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.40.DELAY |
Bel BUFGCE17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.17.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.41.DELAY |
Bel BUFGCE18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.18.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.42.DELAY |
Bel BUFGCE19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.19.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.43.DELAY |
Bel BUFGCE20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.20.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.44.DELAY |
Bel BUFGCE21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.21.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.45.DELAY |
Bel BUFGCE22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.22.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.46.DELAY |
Bel BUFGCE23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.23.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL0
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.23.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.46.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.38.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.30.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.22.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.45.DELAY |
Bel BUFGCTRL1
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.24.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.47.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.39.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.31.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.23.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.46.DELAY |
Bel BUFGCTRL2
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.25.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.17.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.40.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.32.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.24.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL3
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.26.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.18.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.41.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.33.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.25.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.17.DELAY |
Bel BUFGCTRL4
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.27.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.19.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.42.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.34.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.26.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.18.DELAY |
Bel BUFGCTRL5
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.28.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.20.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.43.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.35.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.27.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.19.DELAY |
Bel BUFGCTRL6
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.29.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.21.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.44.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.36.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.28.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.20.DELAY |
Bel BUFGCTRL7
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.30.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.22.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.45.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.37.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.29.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.21.DELAY |
Bel BUFGCE_DIV0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.41.DELAY |
| RST_PRE_OPTINV | input | TCELL28:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.42.DELAY |
| RST_PRE_OPTINV | input | TCELL29:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.43.DELAY |
| RST_PRE_OPTINV | input | TCELL30:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.44.DELAY |
| RST_PRE_OPTINV | input | TCELL31:IMUX.IMUX.0.DELAY |
Bel PLL0
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL1:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL9:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL9:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL9:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL9:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL8:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL8:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL8:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL11:IMUX.CTRL.0 |
| DEN | input | TCELL11:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL13:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL13:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL11:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL11:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL10:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL10:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL10:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL10:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL13:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL13:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL12:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL12:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL12:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL12:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL11:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL11:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL12:OUT.0 |
| DOUT1 | output | TCELL12:OUT.1 |
| DOUT10 | output | TCELL9:OUT.1 |
| DOUT11 | output | TCELL9:OUT.2 |
| DOUT12 | output | TCELL8:OUT.0 |
| DOUT13 | output | TCELL8:OUT.1 |
| DOUT14 | output | TCELL8:OUT.2 |
| DOUT15 | output | TCELL7:OUT.0 |
| DOUT2 | output | TCELL12:OUT.2 |
| DOUT3 | output | TCELL11:OUT.0 |
| DOUT4 | output | TCELL11:OUT.1 |
| DOUT5 | output | TCELL11:OUT.2 |
| DOUT6 | output | TCELL10:OUT.0 |
| DOUT7 | output | TCELL10:OUT.1 |
| DOUT8 | output | TCELL10:OUT.2 |
| DOUT9 | output | TCELL9:OUT.0 |
| DRDY | output | TCELL13:OUT.1 |
| DWE | input | TCELL10:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL13:OUT.0 |
| PWRDWN | input | TCELL12:IMUX.IMUX.0.DELAY |
| RST | input | TCELL13:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL13:IMUX.CTRL.0 |
| SCANENB | input | TCELL7:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL8:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL6:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL13:OUT.2 |
| TESTIN0 | input | TCELL7:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL7:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL5:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL5:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL4:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL4:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL4:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL4:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL3:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL3:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL3:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL3:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL7:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL2:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL2:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL2:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL2:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL1:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL1:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL1:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL1:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL0:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL0:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL7:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL0:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL0:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL6:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL6:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL6:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL6:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL5:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL5:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL7:OUT.1 |
| TESTOUT1 | output | TCELL7:OUT.2 |
| TESTOUT10 | output | TCELL4:OUT.2 |
| TESTOUT11 | output | TCELL3:OUT.0 |
| TESTOUT12 | output | TCELL3:OUT.1 |
| TESTOUT13 | output | TCELL3:OUT.2 |
| TESTOUT14 | output | TCELL2:OUT.0 |
| TESTOUT15 | output | TCELL2:OUT.1 |
| TESTOUT2 | output | TCELL6:OUT.0 |
| TESTOUT3 | output | TCELL6:OUT.1 |
| TESTOUT4 | output | TCELL6:OUT.2 |
| TESTOUT5 | output | TCELL5:OUT.0 |
| TESTOUT6 | output | TCELL5:OUT.1 |
| TESTOUT7 | output | TCELL5:OUT.2 |
| TESTOUT8 | output | TCELL4:OUT.0 |
| TESTOUT9 | output | TCELL4:OUT.1 |
Bel PLL1
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL15:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL23:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL23:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL23:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL23:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL22:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL22:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL22:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL25:IMUX.CTRL.0 |
| DEN | input | TCELL25:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL27:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL27:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL25:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL25:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL24:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL24:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL24:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL24:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL27:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL27:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL26:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL26:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL26:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL26:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL25:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL25:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL26:OUT.0 |
| DOUT1 | output | TCELL26:OUT.1 |
| DOUT10 | output | TCELL23:OUT.1 |
| DOUT11 | output | TCELL23:OUT.2 |
| DOUT12 | output | TCELL22:OUT.0 |
| DOUT13 | output | TCELL22:OUT.1 |
| DOUT14 | output | TCELL22:OUT.2 |
| DOUT15 | output | TCELL21:OUT.0 |
| DOUT2 | output | TCELL26:OUT.2 |
| DOUT3 | output | TCELL25:OUT.0 |
| DOUT4 | output | TCELL25:OUT.1 |
| DOUT5 | output | TCELL25:OUT.2 |
| DOUT6 | output | TCELL24:OUT.0 |
| DOUT7 | output | TCELL24:OUT.1 |
| DOUT8 | output | TCELL24:OUT.2 |
| DOUT9 | output | TCELL23:OUT.0 |
| DRDY | output | TCELL27:OUT.1 |
| DWE | input | TCELL24:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL27:OUT.0 |
| PWRDWN | input | TCELL26:IMUX.IMUX.0.DELAY |
| RST | input | TCELL27:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL27:IMUX.CTRL.0 |
| SCANENB | input | TCELL21:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL22:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL20:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL27:OUT.2 |
| TESTIN0 | input | TCELL21:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL21:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL19:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL19:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL18:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL18:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL18:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL18:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL17:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL17:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL17:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL17:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL21:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL16:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL16:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL16:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL16:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL15:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL15:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL15:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL15:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL14:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL14:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL21:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL14:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL14:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL20:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL20:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL20:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL20:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL19:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL19:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL21:OUT.1 |
| TESTOUT1 | output | TCELL21:OUT.2 |
| TESTOUT10 | output | TCELL18:OUT.2 |
| TESTOUT11 | output | TCELL17:OUT.0 |
| TESTOUT12 | output | TCELL17:OUT.1 |
| TESTOUT13 | output | TCELL17:OUT.2 |
| TESTOUT14 | output | TCELL16:OUT.0 |
| TESTOUT15 | output | TCELL16:OUT.1 |
| TESTOUT2 | output | TCELL20:OUT.0 |
| TESTOUT3 | output | TCELL20:OUT.1 |
| TESTOUT4 | output | TCELL20:OUT.2 |
| TESTOUT5 | output | TCELL19:OUT.0 |
| TESTOUT6 | output | TCELL19:OUT.1 |
| TESTOUT7 | output | TCELL19:OUT.2 |
| TESTOUT8 | output | TCELL18:OUT.0 |
| TESTOUT9 | output | TCELL18:OUT.1 |
Bel MMCM
| Pin | Direction | Wires |
|---|---|---|
| CDDCDONE | output | TCELL56:OUT.0 |
| CDDCREQ | input | TCELL50:IMUX.IMUX.0.DELAY |
| CLKFBSTOPPED | output | TCELL55:OUT.0 |
| CLKINSEL | input | TCELL41:IMUX.IMUX.0.DELAY |
| CLKINSTOPPED | output | TCELL55:OUT.1 |
| DADDR0 | input | TCELL50:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL50:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL50:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL50:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL49:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL49:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL49:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL52:IMUX.CTRL.0 |
| DEN | input | TCELL52:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL54:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL54:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL52:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL52:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL51:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL51:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL51:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL51:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL54:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL54:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL53:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL53:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL53:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL53:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL52:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL52:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL53:OUT.0 |
| DOUT1 | output | TCELL53:OUT.1 |
| DOUT10 | output | TCELL50:OUT.1 |
| DOUT11 | output | TCELL50:OUT.2 |
| DOUT12 | output | TCELL49:OUT.0 |
| DOUT13 | output | TCELL49:OUT.1 |
| DOUT14 | output | TCELL49:OUT.2 |
| DOUT15 | output | TCELL48:OUT.0 |
| DOUT2 | output | TCELL53:OUT.2 |
| DOUT3 | output | TCELL52:OUT.0 |
| DOUT4 | output | TCELL52:OUT.1 |
| DOUT5 | output | TCELL52:OUT.2 |
| DOUT6 | output | TCELL51:OUT.0 |
| DOUT7 | output | TCELL51:OUT.1 |
| DOUT8 | output | TCELL51:OUT.2 |
| DOUT9 | output | TCELL50:OUT.0 |
| DRDY | output | TCELL54:OUT.1 |
| DWE | input | TCELL51:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL54:OUT.0 |
| PSCLK | input | TCELL53:IMUX.CTRL.0 |
| PSDONE | output | TCELL55:OUT.2 |
| PSEN | input | TCELL56:IMUX.IMUX.0.DELAY |
| PSINCDEC | input | TCELL55:IMUX.IMUX.0.DELAY |
| PWRDWN | input | TCELL53:IMUX.IMUX.0.DELAY |
| RST | input | TCELL54:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL54:IMUX.CTRL.0 |
| SCANENB | input | TCELL48:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL49:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL47:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL54:OUT.2 |
| TESTIN0 | input | TCELL48:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL48:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL46:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL46:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL45:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL45:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL45:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL45:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL44:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL44:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL44:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL44:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL48:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL43:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL43:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL43:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL43:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL42:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL42:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL42:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL42:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL41:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL41:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL48:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL41:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL41:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL47:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL47:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL47:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL47:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL46:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL46:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL48:OUT.1 |
| TESTOUT1 | output | TCELL48:OUT.2 |
| TESTOUT10 | output | TCELL45:OUT.2 |
| TESTOUT11 | output | TCELL44:OUT.0 |
| TESTOUT12 | output | TCELL44:OUT.1 |
| TESTOUT13 | output | TCELL44:OUT.2 |
| TESTOUT14 | output | TCELL43:OUT.0 |
| TESTOUT15 | output | TCELL43:OUT.1 |
| TESTOUT2 | output | TCELL47:OUT.0 |
| TESTOUT3 | output | TCELL47:OUT.1 |
| TESTOUT4 | output | TCELL47:OUT.2 |
| TESTOUT5 | output | TCELL46:OUT.0 |
| TESTOUT6 | output | TCELL46:OUT.1 |
| TESTOUT7 | output | TCELL46:OUT.2 |
| TESTOUT8 | output | TCELL45:OUT.0 |
| TESTOUT9 | output | TCELL45:OUT.1 |
Bel CMT
| Pin | Direction | Wires |
|---|
Bel VCC_CMT
| Pin | Direction | Wires |
|---|
Bel ABUS_SWITCH_CMT
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL32:IMUX.IMUX.0.DELAY |
Bel HBM_REF_CLK0
| Pin | Direction | Wires |
|---|
Bel HBM_REF_CLK1
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.BYP.0.DELAY | PLL0.TESTIN28 |
| TCELL0:IMUX.BYP.1.DELAY | PLL0.TESTIN29 |
| TCELL0:IMUX.BYP.2.DELAY | PLL0.TESTIN30 |
| TCELL0:IMUX.BYP.3.DELAY | PLL0.TESTIN31 |
| TCELL1:IMUX.BYP.0.DELAY | PLL0.TESTIN24 |
| TCELL1:IMUX.BYP.1.DELAY | PLL0.TESTIN25 |
| TCELL1:IMUX.BYP.2.DELAY | PLL0.TESTIN26 |
| TCELL1:IMUX.BYP.3.DELAY | PLL0.TESTIN27 |
| TCELL1:IMUX.IMUX.0.DELAY | PLL0.CLKOUTPHY_EN |
| TCELL2:OUT.0 | PLL0.TESTOUT14 |
| TCELL2:OUT.1 | PLL0.TESTOUT15 |
| TCELL2:IMUX.BYP.0.DELAY | PLL0.TESTIN20 |
| TCELL2:IMUX.BYP.1.DELAY | PLL0.TESTIN21 |
| TCELL2:IMUX.BYP.2.DELAY | PLL0.TESTIN22 |
| TCELL2:IMUX.BYP.3.DELAY | PLL0.TESTIN23 |
| TCELL3:OUT.0 | PLL0.TESTOUT11 |
| TCELL3:OUT.1 | PLL0.TESTOUT12 |
| TCELL3:OUT.2 | PLL0.TESTOUT13 |
| TCELL3:IMUX.BYP.0.DELAY | PLL0.TESTIN16 |
| TCELL3:IMUX.BYP.1.DELAY | PLL0.TESTIN17 |
| TCELL3:IMUX.BYP.2.DELAY | PLL0.TESTIN18 |
| TCELL3:IMUX.BYP.3.DELAY | PLL0.TESTIN19 |
| TCELL4:OUT.0 | PLL0.TESTOUT8 |
| TCELL4:OUT.1 | PLL0.TESTOUT9 |
| TCELL4:OUT.2 | PLL0.TESTOUT10 |
| TCELL4:IMUX.BYP.0.DELAY | PLL0.TESTIN12 |
| TCELL4:IMUX.BYP.1.DELAY | PLL0.TESTIN13 |
| TCELL4:IMUX.BYP.2.DELAY | PLL0.TESTIN14 |
| TCELL4:IMUX.BYP.3.DELAY | PLL0.TESTIN15 |
| TCELL5:OUT.0 | PLL0.TESTOUT5 |
| TCELL5:OUT.1 | PLL0.TESTOUT6 |
| TCELL5:OUT.2 | PLL0.TESTOUT7 |
| TCELL5:IMUX.BYP.0.DELAY | PLL0.TESTIN8 |
| TCELL5:IMUX.BYP.1.DELAY | PLL0.TESTIN9 |
| TCELL5:IMUX.BYP.2.DELAY | PLL0.TESTIN10 |
| TCELL5:IMUX.BYP.3.DELAY | PLL0.TESTIN11 |
| TCELL6:OUT.0 | PLL0.TESTOUT2 |
| TCELL6:OUT.1 | PLL0.TESTOUT3 |
| TCELL6:OUT.2 | PLL0.TESTOUT4 |
| TCELL6:IMUX.BYP.0.DELAY | PLL0.TESTIN4 |
| TCELL6:IMUX.BYP.1.DELAY | PLL0.TESTIN5 |
| TCELL6:IMUX.BYP.2.DELAY | PLL0.TESTIN6 |
| TCELL6:IMUX.BYP.3.DELAY | PLL0.TESTIN7 |
| TCELL6:IMUX.IMUX.0.DELAY | PLL0.SCANMODEB |
| TCELL7:OUT.0 | PLL0.DOUT15 |
| TCELL7:OUT.1 | PLL0.TESTOUT0 |
| TCELL7:OUT.2 | PLL0.TESTOUT1 |
| TCELL7:IMUX.BYP.0.DELAY | PLL0.TESTIN0 |
| TCELL7:IMUX.BYP.1.DELAY | PLL0.TESTIN1 |
| TCELL7:IMUX.BYP.2.DELAY | PLL0.TESTIN2 |
| TCELL7:IMUX.BYP.3.DELAY | PLL0.TESTIN3 |
| TCELL7:IMUX.IMUX.0.DELAY | PLL0.SCANENB |
| TCELL8:OUT.0 | PLL0.DOUT12 |
| TCELL8:OUT.1 | PLL0.DOUT13 |
| TCELL8:OUT.2 | PLL0.DOUT14 |
| TCELL8:IMUX.BYP.0.DELAY | PLL0.DADDR4 |
| TCELL8:IMUX.BYP.1.DELAY | PLL0.DADDR5 |
| TCELL8:IMUX.BYP.2.DELAY | PLL0.DADDR6 |
| TCELL8:IMUX.IMUX.0.DELAY | PLL0.SCANIN |
| TCELL9:OUT.0 | PLL0.DOUT9 |
| TCELL9:OUT.1 | PLL0.DOUT10 |
| TCELL9:OUT.2 | PLL0.DOUT11 |
| TCELL9:IMUX.BYP.0.DELAY | PLL0.DADDR0 |
| TCELL9:IMUX.BYP.1.DELAY | PLL0.DADDR1 |
| TCELL9:IMUX.BYP.2.DELAY | PLL0.DADDR2 |
| TCELL9:IMUX.BYP.3.DELAY | PLL0.DADDR3 |
| TCELL10:OUT.0 | PLL0.DOUT6 |
| TCELL10:OUT.1 | PLL0.DOUT7 |
| TCELL10:OUT.2 | PLL0.DOUT8 |
| TCELL10:IMUX.BYP.0.DELAY | PLL0.DI12 |
| TCELL10:IMUX.BYP.1.DELAY | PLL0.DI13 |
| TCELL10:IMUX.BYP.2.DELAY | PLL0.DI14 |
| TCELL10:IMUX.BYP.3.DELAY | PLL0.DI15 |
| TCELL10:IMUX.IMUX.0.DELAY | PLL0.DWE |
| TCELL11:OUT.0 | PLL0.DOUT3 |
| TCELL11:OUT.1 | PLL0.DOUT4 |
| TCELL11:OUT.2 | PLL0.DOUT5 |
| TCELL11:IMUX.CTRL.0 | PLL0.DCLK |
| TCELL11:IMUX.BYP.0.DELAY | PLL0.DI8 |
| TCELL11:IMUX.BYP.1.DELAY | PLL0.DI9 |
| TCELL11:IMUX.BYP.2.DELAY | PLL0.DI10 |
| TCELL11:IMUX.BYP.3.DELAY | PLL0.DI11 |
| TCELL11:IMUX.IMUX.0.DELAY | PLL0.DEN |
| TCELL12:OUT.0 | PLL0.DOUT0 |
| TCELL12:OUT.1 | PLL0.DOUT1 |
| TCELL12:OUT.2 | PLL0.DOUT2 |
| TCELL12:IMUX.BYP.0.DELAY | PLL0.DI4 |
| TCELL12:IMUX.BYP.1.DELAY | PLL0.DI5 |
| TCELL12:IMUX.BYP.2.DELAY | PLL0.DI6 |
| TCELL12:IMUX.BYP.3.DELAY | PLL0.DI7 |
| TCELL12:IMUX.IMUX.0.DELAY | PLL0.PWRDWN |
| TCELL13:OUT.0 | PLL0.LOCKED |
| TCELL13:OUT.1 | PLL0.DRDY |
| TCELL13:OUT.2 | PLL0.SCANOUT |
| TCELL13:IMUX.CTRL.0 | PLL0.SCANCLK |
| TCELL13:IMUX.BYP.0.DELAY | PLL0.DI0 |
| TCELL13:IMUX.BYP.1.DELAY | PLL0.DI1 |
| TCELL13:IMUX.BYP.2.DELAY | PLL0.DI2 |
| TCELL13:IMUX.BYP.3.DELAY | PLL0.DI3 |
| TCELL13:IMUX.IMUX.0.DELAY | PLL0.RST |
| TCELL14:IMUX.BYP.0.DELAY | PLL1.TESTIN28 |
| TCELL14:IMUX.BYP.1.DELAY | PLL1.TESTIN29 |
| TCELL14:IMUX.BYP.2.DELAY | PLL1.TESTIN30 |
| TCELL14:IMUX.BYP.3.DELAY | PLL1.TESTIN31 |
| TCELL15:IMUX.BYP.0.DELAY | PLL1.TESTIN24 |
| TCELL15:IMUX.BYP.1.DELAY | PLL1.TESTIN25 |
| TCELL15:IMUX.BYP.2.DELAY | PLL1.TESTIN26 |
| TCELL15:IMUX.BYP.3.DELAY | PLL1.TESTIN27 |
| TCELL15:IMUX.IMUX.0.DELAY | PLL1.CLKOUTPHY_EN |
| TCELL16:OUT.0 | PLL1.TESTOUT14 |
| TCELL16:OUT.1 | PLL1.TESTOUT15 |
| TCELL16:IMUX.BYP.0.DELAY | PLL1.TESTIN20 |
| TCELL16:IMUX.BYP.1.DELAY | PLL1.TESTIN21 |
| TCELL16:IMUX.BYP.2.DELAY | PLL1.TESTIN22 |
| TCELL16:IMUX.BYP.3.DELAY | PLL1.TESTIN23 |
| TCELL17:OUT.0 | PLL1.TESTOUT11 |
| TCELL17:OUT.1 | PLL1.TESTOUT12 |
| TCELL17:OUT.2 | PLL1.TESTOUT13 |
| TCELL17:IMUX.BYP.0.DELAY | PLL1.TESTIN16 |
| TCELL17:IMUX.BYP.1.DELAY | PLL1.TESTIN17 |
| TCELL17:IMUX.BYP.2.DELAY | PLL1.TESTIN18 |
| TCELL17:IMUX.BYP.3.DELAY | PLL1.TESTIN19 |
| TCELL18:OUT.0 | PLL1.TESTOUT8 |
| TCELL18:OUT.1 | PLL1.TESTOUT9 |
| TCELL18:OUT.2 | PLL1.TESTOUT10 |
| TCELL18:IMUX.BYP.0.DELAY | PLL1.TESTIN12 |
| TCELL18:IMUX.BYP.1.DELAY | PLL1.TESTIN13 |
| TCELL18:IMUX.BYP.2.DELAY | PLL1.TESTIN14 |
| TCELL18:IMUX.BYP.3.DELAY | PLL1.TESTIN15 |
| TCELL19:OUT.0 | PLL1.TESTOUT5 |
| TCELL19:OUT.1 | PLL1.TESTOUT6 |
| TCELL19:OUT.2 | PLL1.TESTOUT7 |
| TCELL19:IMUX.BYP.0.DELAY | PLL1.TESTIN8 |
| TCELL19:IMUX.BYP.1.DELAY | PLL1.TESTIN9 |
| TCELL19:IMUX.BYP.2.DELAY | PLL1.TESTIN10 |
| TCELL19:IMUX.BYP.3.DELAY | PLL1.TESTIN11 |
| TCELL20:OUT.0 | PLL1.TESTOUT2 |
| TCELL20:OUT.1 | PLL1.TESTOUT3 |
| TCELL20:OUT.2 | PLL1.TESTOUT4 |
| TCELL20:IMUX.BYP.0.DELAY | PLL1.TESTIN4 |
| TCELL20:IMUX.BYP.1.DELAY | PLL1.TESTIN5 |
| TCELL20:IMUX.BYP.2.DELAY | PLL1.TESTIN6 |
| TCELL20:IMUX.BYP.3.DELAY | PLL1.TESTIN7 |
| TCELL20:IMUX.IMUX.0.DELAY | PLL1.SCANMODEB |
| TCELL21:OUT.0 | PLL1.DOUT15 |
| TCELL21:OUT.1 | PLL1.TESTOUT0 |
| TCELL21:OUT.2 | PLL1.TESTOUT1 |
| TCELL21:IMUX.BYP.0.DELAY | PLL1.TESTIN0 |
| TCELL21:IMUX.BYP.1.DELAY | PLL1.TESTIN1 |
| TCELL21:IMUX.BYP.2.DELAY | PLL1.TESTIN2 |
| TCELL21:IMUX.BYP.3.DELAY | PLL1.TESTIN3 |
| TCELL21:IMUX.IMUX.0.DELAY | PLL1.SCANENB |
| TCELL22:OUT.0 | PLL1.DOUT12 |
| TCELL22:OUT.1 | PLL1.DOUT13 |
| TCELL22:OUT.2 | PLL1.DOUT14 |
| TCELL22:IMUX.BYP.0.DELAY | PLL1.DADDR4 |
| TCELL22:IMUX.BYP.1.DELAY | PLL1.DADDR5 |
| TCELL22:IMUX.BYP.2.DELAY | PLL1.DADDR6 |
| TCELL22:IMUX.IMUX.0.DELAY | PLL1.SCANIN |
| TCELL23:OUT.0 | PLL1.DOUT9 |
| TCELL23:OUT.1 | PLL1.DOUT10 |
| TCELL23:OUT.2 | PLL1.DOUT11 |
| TCELL23:IMUX.BYP.0.DELAY | PLL1.DADDR0 |
| TCELL23:IMUX.BYP.1.DELAY | PLL1.DADDR1 |
| TCELL23:IMUX.BYP.2.DELAY | PLL1.DADDR2 |
| TCELL23:IMUX.BYP.3.DELAY | PLL1.DADDR3 |
| TCELL24:OUT.0 | PLL1.DOUT6 |
| TCELL24:OUT.1 | PLL1.DOUT7 |
| TCELL24:OUT.2 | PLL1.DOUT8 |
| TCELL24:IMUX.BYP.0.DELAY | PLL1.DI12 |
| TCELL24:IMUX.BYP.1.DELAY | PLL1.DI13 |
| TCELL24:IMUX.BYP.2.DELAY | PLL1.DI14 |
| TCELL24:IMUX.BYP.3.DELAY | PLL1.DI15 |
| TCELL24:IMUX.IMUX.0.DELAY | PLL1.DWE |
| TCELL25:OUT.0 | PLL1.DOUT3 |
| TCELL25:OUT.1 | PLL1.DOUT4 |
| TCELL25:OUT.2 | PLL1.DOUT5 |
| TCELL25:IMUX.CTRL.0 | PLL1.DCLK |
| TCELL25:IMUX.BYP.0.DELAY | PLL1.DI8 |
| TCELL25:IMUX.BYP.1.DELAY | PLL1.DI9 |
| TCELL25:IMUX.BYP.2.DELAY | PLL1.DI10 |
| TCELL25:IMUX.BYP.3.DELAY | PLL1.DI11 |
| TCELL25:IMUX.IMUX.0.DELAY | PLL1.DEN |
| TCELL26:OUT.0 | PLL1.DOUT0 |
| TCELL26:OUT.1 | PLL1.DOUT1 |
| TCELL26:OUT.2 | PLL1.DOUT2 |
| TCELL26:IMUX.BYP.0.DELAY | PLL1.DI4 |
| TCELL26:IMUX.BYP.1.DELAY | PLL1.DI5 |
| TCELL26:IMUX.BYP.2.DELAY | PLL1.DI6 |
| TCELL26:IMUX.BYP.3.DELAY | PLL1.DI7 |
| TCELL26:IMUX.IMUX.0.DELAY | PLL1.PWRDWN |
| TCELL27:OUT.0 | PLL1.LOCKED |
| TCELL27:OUT.1 | PLL1.DRDY |
| TCELL27:OUT.2 | PLL1.SCANOUT |
| TCELL27:IMUX.CTRL.0 | PLL1.SCANCLK |
| TCELL27:IMUX.BYP.0.DELAY | PLL1.DI0 |
| TCELL27:IMUX.BYP.1.DELAY | PLL1.DI1 |
| TCELL27:IMUX.BYP.2.DELAY | PLL1.DI2 |
| TCELL27:IMUX.BYP.3.DELAY | PLL1.DI3 |
| TCELL27:IMUX.IMUX.0.DELAY | PLL1.RST |
| TCELL28:IMUX.IMUX.0.DELAY | BUFGCE_DIV0.RST_PRE_OPTINV |
| TCELL28:IMUX.IMUX.17.DELAY | BUFCE_ROW_CMT0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.18.DELAY | BUFCE_ROW_CMT1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.19.DELAY | BUFCE_ROW_CMT2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.20.DELAY | BUFCE_ROW_CMT3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.21.DELAY | BUFCE_ROW_CMT4.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.22.DELAY | BUFCE_ROW_CMT5.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.23.DELAY | BUFCE_ROW_CMT6.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.24.DELAY | BUFCE_ROW_CMT7.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.25.DELAY | BUFCE_ROW_CMT8.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.26.DELAY | BUFCE_ROW_CMT9.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.27.DELAY | BUFCE_ROW_CMT10.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.28.DELAY | BUFCE_ROW_CMT11.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.29.DELAY | BUFCE_ROW_CMT12.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.30.DELAY | BUFCE_ROW_CMT13.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.31.DELAY | BUFCE_ROW_CMT14.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.32.DELAY | BUFCE_ROW_CMT15.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.33.DELAY | BUFCE_ROW_CMT16.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.34.DELAY | BUFCE_ROW_CMT17.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.35.DELAY | BUFCE_ROW_CMT18.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.36.DELAY | BUFCE_ROW_CMT19.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.37.DELAY | BUFCE_ROW_CMT20.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.38.DELAY | BUFCE_ROW_CMT21.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.39.DELAY | BUFCE_ROW_CMT22.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.40.DELAY | BUFCE_ROW_CMT23.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.41.DELAY | BUFGCE_DIV0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.42.DELAY | BUFGCE_DIV1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.43.DELAY | BUFGCE_DIV2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.44.DELAY | BUFGCE_DIV3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.45.DELAY | BUFGCTRL0.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.46.DELAY | BUFGCTRL1.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.47.DELAY | BUFGCTRL2.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.0.DELAY | BUFGCE_DIV1.RST_PRE_OPTINV |
| TCELL29:IMUX.IMUX.17.DELAY | BUFGCTRL3.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.18.DELAY | BUFGCTRL4.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.19.DELAY | BUFGCTRL5.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.20.DELAY | BUFGCTRL6.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.21.DELAY | BUFGCTRL7.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.22.DELAY | BUFGCTRL0.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.23.DELAY | BUFGCTRL1.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.24.DELAY | BUFGCTRL2.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.25.DELAY | BUFGCTRL3.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.26.DELAY | BUFGCTRL4.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.27.DELAY | BUFGCTRL5.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.28.DELAY | BUFGCTRL6.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.29.DELAY | BUFGCTRL7.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.30.DELAY | BUFGCTRL0.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.31.DELAY | BUFGCTRL1.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.32.DELAY | BUFGCTRL2.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.33.DELAY | BUFGCTRL3.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.34.DELAY | BUFGCTRL4.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.35.DELAY | BUFGCTRL5.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.36.DELAY | BUFGCTRL6.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.37.DELAY | BUFGCTRL7.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.38.DELAY | BUFGCTRL0.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.39.DELAY | BUFGCTRL1.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.40.DELAY | BUFGCTRL2.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.41.DELAY | BUFGCTRL3.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.42.DELAY | BUFGCTRL4.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.43.DELAY | BUFGCTRL5.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.44.DELAY | BUFGCTRL6.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.45.DELAY | BUFGCTRL7.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.46.DELAY | BUFGCTRL0.CE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.47.DELAY | BUFGCTRL1.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.0.DELAY | BUFGCE_DIV2.RST_PRE_OPTINV |
| TCELL30:IMUX.IMUX.17.DELAY | BUFGCTRL2.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.18.DELAY | BUFGCTRL3.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.19.DELAY | BUFGCTRL4.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.20.DELAY | BUFGCTRL5.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.21.DELAY | BUFGCTRL6.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.22.DELAY | BUFGCTRL7.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.23.DELAY | BUFGCTRL0.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.24.DELAY | BUFGCTRL1.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.25.DELAY | BUFGCTRL2.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.26.DELAY | BUFGCTRL3.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.27.DELAY | BUFGCTRL4.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.28.DELAY | BUFGCTRL5.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.29.DELAY | BUFGCTRL6.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.30.DELAY | BUFGCTRL7.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.31.DELAY | BUFGCE0.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.32.DELAY | BUFGCE1.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.33.DELAY | BUFGCE2.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.34.DELAY | BUFGCE3.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.35.DELAY | BUFGCE4.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.36.DELAY | BUFGCE5.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.37.DELAY | BUFGCE6.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.38.DELAY | BUFGCE7.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.39.DELAY | BUFGCE8.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.40.DELAY | BUFGCE9.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.41.DELAY | BUFGCE10.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.42.DELAY | BUFGCE11.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.43.DELAY | BUFGCE12.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.44.DELAY | BUFGCE13.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.45.DELAY | BUFGCE14.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.46.DELAY | BUFGCE15.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.47.DELAY | BUFGCE16.CE_PRE_OPTINV |
| TCELL30:RCLK.IMUX.16 | BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.17 | BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.18 | BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.19 | BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.20 | BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2 |
| TCELL30:RCLK.IMUX.21 | BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2 |
| TCELL31:IMUX.IMUX.0.DELAY | BUFGCE_DIV3.RST_PRE_OPTINV |
| TCELL31:IMUX.IMUX.17.DELAY | BUFGCE17.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.18.DELAY | BUFGCE18.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.19.DELAY | BUFGCE19.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.20.DELAY | BUFGCE20.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.21.DELAY | BUFGCE21.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.22.DELAY | BUFGCE22.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.23.DELAY | BUFGCE23.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.24.DELAY | BUFGCE0.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.25.DELAY | BUFGCE1.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.26.DELAY | BUFGCE2.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.27.DELAY | BUFGCE3.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.28.DELAY | BUFGCE4.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.29.DELAY | BUFGCE5.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.30.DELAY | BUFGCE6.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.31.DELAY | BUFGCE7.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.32.DELAY | BUFGCE8.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.33.DELAY | BUFGCE9.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.34.DELAY | BUFGCE10.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.35.DELAY | BUFGCE11.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.36.DELAY | BUFGCE12.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.37.DELAY | BUFGCE13.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.38.DELAY | BUFGCE14.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.39.DELAY | BUFGCE15.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.40.DELAY | BUFGCE16.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.41.DELAY | BUFGCE17.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.42.DELAY | BUFGCE18.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.43.DELAY | BUFGCE19.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.44.DELAY | BUFGCE20.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.45.DELAY | BUFGCE21.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.46.DELAY | BUFGCE22.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.47.DELAY | BUFGCE23.CLK_IN_CKINT |
| TCELL32:IMUX.IMUX.0.DELAY | ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B |
| TCELL41:IMUX.BYP.0.DELAY | MMCM.TESTIN28 |
| TCELL41:IMUX.BYP.1.DELAY | MMCM.TESTIN29 |
| TCELL41:IMUX.BYP.2.DELAY | MMCM.TESTIN30 |
| TCELL41:IMUX.BYP.3.DELAY | MMCM.TESTIN31 |
| TCELL41:IMUX.IMUX.0.DELAY | MMCM.CLKINSEL |
| TCELL42:IMUX.BYP.0.DELAY | MMCM.TESTIN24 |
| TCELL42:IMUX.BYP.1.DELAY | MMCM.TESTIN25 |
| TCELL42:IMUX.BYP.2.DELAY | MMCM.TESTIN26 |
| TCELL42:IMUX.BYP.3.DELAY | MMCM.TESTIN27 |
| TCELL43:OUT.0 | MMCM.TESTOUT14 |
| TCELL43:OUT.1 | MMCM.TESTOUT15 |
| TCELL43:IMUX.BYP.0.DELAY | MMCM.TESTIN20 |
| TCELL43:IMUX.BYP.1.DELAY | MMCM.TESTIN21 |
| TCELL43:IMUX.BYP.2.DELAY | MMCM.TESTIN22 |
| TCELL43:IMUX.BYP.3.DELAY | MMCM.TESTIN23 |
| TCELL44:OUT.0 | MMCM.TESTOUT11 |
| TCELL44:OUT.1 | MMCM.TESTOUT12 |
| TCELL44:OUT.2 | MMCM.TESTOUT13 |
| TCELL44:IMUX.BYP.0.DELAY | MMCM.TESTIN16 |
| TCELL44:IMUX.BYP.1.DELAY | MMCM.TESTIN17 |
| TCELL44:IMUX.BYP.2.DELAY | MMCM.TESTIN18 |
| TCELL44:IMUX.BYP.3.DELAY | MMCM.TESTIN19 |
| TCELL45:OUT.0 | MMCM.TESTOUT8 |
| TCELL45:OUT.1 | MMCM.TESTOUT9 |
| TCELL45:OUT.2 | MMCM.TESTOUT10 |
| TCELL45:IMUX.BYP.0.DELAY | MMCM.TESTIN12 |
| TCELL45:IMUX.BYP.1.DELAY | MMCM.TESTIN13 |
| TCELL45:IMUX.BYP.2.DELAY | MMCM.TESTIN14 |
| TCELL45:IMUX.BYP.3.DELAY | MMCM.TESTIN15 |
| TCELL46:OUT.0 | MMCM.TESTOUT5 |
| TCELL46:OUT.1 | MMCM.TESTOUT6 |
| TCELL46:OUT.2 | MMCM.TESTOUT7 |
| TCELL46:IMUX.BYP.0.DELAY | MMCM.TESTIN8 |
| TCELL46:IMUX.BYP.1.DELAY | MMCM.TESTIN9 |
| TCELL46:IMUX.BYP.2.DELAY | MMCM.TESTIN10 |
| TCELL46:IMUX.BYP.3.DELAY | MMCM.TESTIN11 |
| TCELL47:OUT.0 | MMCM.TESTOUT2 |
| TCELL47:OUT.1 | MMCM.TESTOUT3 |
| TCELL47:OUT.2 | MMCM.TESTOUT4 |
| TCELL47:IMUX.BYP.0.DELAY | MMCM.TESTIN4 |
| TCELL47:IMUX.BYP.1.DELAY | MMCM.TESTIN5 |
| TCELL47:IMUX.BYP.2.DELAY | MMCM.TESTIN6 |
| TCELL47:IMUX.BYP.3.DELAY | MMCM.TESTIN7 |
| TCELL47:IMUX.IMUX.0.DELAY | MMCM.SCANMODEB |
| TCELL48:OUT.0 | MMCM.DOUT15 |
| TCELL48:OUT.1 | MMCM.TESTOUT0 |
| TCELL48:OUT.2 | MMCM.TESTOUT1 |
| TCELL48:IMUX.BYP.0.DELAY | MMCM.TESTIN0 |
| TCELL48:IMUX.BYP.1.DELAY | MMCM.TESTIN1 |
| TCELL48:IMUX.BYP.2.DELAY | MMCM.TESTIN2 |
| TCELL48:IMUX.BYP.3.DELAY | MMCM.TESTIN3 |
| TCELL48:IMUX.IMUX.0.DELAY | MMCM.SCANENB |
| TCELL49:OUT.0 | MMCM.DOUT12 |
| TCELL49:OUT.1 | MMCM.DOUT13 |
| TCELL49:OUT.2 | MMCM.DOUT14 |
| TCELL49:IMUX.BYP.0.DELAY | MMCM.DADDR4 |
| TCELL49:IMUX.BYP.1.DELAY | MMCM.DADDR5 |
| TCELL49:IMUX.BYP.2.DELAY | MMCM.DADDR6 |
| TCELL49:IMUX.IMUX.0.DELAY | MMCM.SCANIN |
| TCELL50:OUT.0 | MMCM.DOUT9 |
| TCELL50:OUT.1 | MMCM.DOUT10 |
| TCELL50:OUT.2 | MMCM.DOUT11 |
| TCELL50:IMUX.BYP.0.DELAY | MMCM.DADDR0 |
| TCELL50:IMUX.BYP.1.DELAY | MMCM.DADDR1 |
| TCELL50:IMUX.BYP.2.DELAY | MMCM.DADDR2 |
| TCELL50:IMUX.BYP.3.DELAY | MMCM.DADDR3 |
| TCELL50:IMUX.IMUX.0.DELAY | MMCM.CDDCREQ |
| TCELL51:OUT.0 | MMCM.DOUT6 |
| TCELL51:OUT.1 | MMCM.DOUT7 |
| TCELL51:OUT.2 | MMCM.DOUT8 |
| TCELL51:IMUX.BYP.0.DELAY | MMCM.DI12 |
| TCELL51:IMUX.BYP.1.DELAY | MMCM.DI13 |
| TCELL51:IMUX.BYP.2.DELAY | MMCM.DI14 |
| TCELL51:IMUX.BYP.3.DELAY | MMCM.DI15 |
| TCELL51:IMUX.IMUX.0.DELAY | MMCM.DWE |
| TCELL52:OUT.0 | MMCM.DOUT3 |
| TCELL52:OUT.1 | MMCM.DOUT4 |
| TCELL52:OUT.2 | MMCM.DOUT5 |
| TCELL52:IMUX.CTRL.0 | MMCM.DCLK |
| TCELL52:IMUX.BYP.0.DELAY | MMCM.DI8 |
| TCELL52:IMUX.BYP.1.DELAY | MMCM.DI9 |
| TCELL52:IMUX.BYP.2.DELAY | MMCM.DI10 |
| TCELL52:IMUX.BYP.3.DELAY | MMCM.DI11 |
| TCELL52:IMUX.IMUX.0.DELAY | MMCM.DEN |
| TCELL53:OUT.0 | MMCM.DOUT0 |
| TCELL53:OUT.1 | MMCM.DOUT1 |
| TCELL53:OUT.2 | MMCM.DOUT2 |
| TCELL53:IMUX.CTRL.0 | MMCM.PSCLK |
| TCELL53:IMUX.BYP.0.DELAY | MMCM.DI4 |
| TCELL53:IMUX.BYP.1.DELAY | MMCM.DI5 |
| TCELL53:IMUX.BYP.2.DELAY | MMCM.DI6 |
| TCELL53:IMUX.BYP.3.DELAY | MMCM.DI7 |
| TCELL53:IMUX.IMUX.0.DELAY | MMCM.PWRDWN |
| TCELL54:OUT.0 | MMCM.LOCKED |
| TCELL54:OUT.1 | MMCM.DRDY |
| TCELL54:OUT.2 | MMCM.SCANOUT |
| TCELL54:IMUX.CTRL.0 | MMCM.SCANCLK |
| TCELL54:IMUX.BYP.0.DELAY | MMCM.DI0 |
| TCELL54:IMUX.BYP.1.DELAY | MMCM.DI1 |
| TCELL54:IMUX.BYP.2.DELAY | MMCM.DI2 |
| TCELL54:IMUX.BYP.3.DELAY | MMCM.DI3 |
| TCELL54:IMUX.IMUX.0.DELAY | MMCM.RST |
| TCELL55:OUT.0 | MMCM.CLKFBSTOPPED |
| TCELL55:OUT.1 | MMCM.CLKINSTOPPED |
| TCELL55:OUT.2 | MMCM.PSDONE |
| TCELL55:IMUX.IMUX.0.DELAY | MMCM.PSINCDEC |
| TCELL56:OUT.0 | MMCM.CDDCDONE |
| TCELL56:IMUX.IMUX.0.DELAY | MMCM.PSEN |
Tile CMTXP
Cells: 60
Bel BUFCE_ROW_CMT0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.17.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.18.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.19.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.20.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.21.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.22.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.23.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.24.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.25.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.26.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.27.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.28.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.29.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.30.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.31.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.32.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.33.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.34.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.35.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.36.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.37.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.16 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.18 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.20 |
Bel BUFCE_ROW_CMT21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.38.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.39.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel BUFCE_ROW_CMT23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.40.DELAY |
| OPT_DELAY_TEST0 | input | TCELL30:RCLK.IMUX.17 |
| OPT_DELAY_TEST1 | input | TCELL30:RCLK.IMUX.19 |
| OPT_DELAY_TEST2 | input | TCELL30:RCLK.IMUX.21 |
Bel GCLK_TEST_BUF_CMT0
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT1
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT2
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT3
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT4
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT5
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT6
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT7
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT8
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT9
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT10
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT11
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT12
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT13
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT14
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT15
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT16
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT17
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT18
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT19
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT20
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT21
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT22
| Pin | Direction | Wires |
|---|
Bel GCLK_TEST_BUF_CMT23
| Pin | Direction | Wires |
|---|
Bel BUFGCE0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.31.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.24.DELAY |
Bel BUFGCE1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.32.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.25.DELAY |
Bel BUFGCE2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.33.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.26.DELAY |
Bel BUFGCE3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.34.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.27.DELAY |
Bel BUFGCE4
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.35.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.28.DELAY |
Bel BUFGCE5
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.36.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.29.DELAY |
Bel BUFGCE6
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.37.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.30.DELAY |
Bel BUFGCE7
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.38.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.31.DELAY |
Bel BUFGCE8
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.39.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.32.DELAY |
Bel BUFGCE9
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.40.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.33.DELAY |
Bel BUFGCE10
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.41.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.34.DELAY |
Bel BUFGCE11
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.42.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.35.DELAY |
Bel BUFGCE12
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.43.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.36.DELAY |
Bel BUFGCE13
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.44.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.37.DELAY |
Bel BUFGCE14
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.45.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.38.DELAY |
Bel BUFGCE15
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.46.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.39.DELAY |
Bel BUFGCE16
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL30:IMUX.IMUX.47.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.40.DELAY |
Bel BUFGCE17
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.17.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.41.DELAY |
Bel BUFGCE18
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.18.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.42.DELAY |
Bel BUFGCE19
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.19.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.43.DELAY |
Bel BUFGCE20
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.20.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.44.DELAY |
Bel BUFGCE21
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.21.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.45.DELAY |
Bel BUFGCE22
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.22.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.46.DELAY |
Bel BUFGCE23
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL31:IMUX.IMUX.23.DELAY |
| CLK_IN_CKINT | input | TCELL31:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL0
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.23.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.46.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.38.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.30.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.22.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.45.DELAY |
Bel BUFGCTRL1
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.24.DELAY |
| CE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.47.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.39.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.31.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.23.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.46.DELAY |
Bel BUFGCTRL2
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.25.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.17.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.40.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.32.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.24.DELAY |
| SEL1_PRE_OPTINV | input | TCELL28:IMUX.IMUX.47.DELAY |
Bel BUFGCTRL3
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.26.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.18.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.41.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.33.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.25.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.17.DELAY |
Bel BUFGCTRL4
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.27.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.19.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.42.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.34.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.26.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.18.DELAY |
Bel BUFGCTRL5
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.28.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.20.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.43.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.35.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.27.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.19.DELAY |
Bel BUFGCTRL6
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.29.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.21.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.44.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.36.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.28.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.20.DELAY |
Bel BUFGCTRL7
| Pin | Direction | Wires |
|---|---|---|
| CE0_PRE_OPTINV | input | TCELL30:IMUX.IMUX.30.DELAY |
| CE1_PRE_OPTINV | input | TCELL30:IMUX.IMUX.22.DELAY |
| IGNORE0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.45.DELAY |
| IGNORE1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.37.DELAY |
| SEL0_PRE_OPTINV | input | TCELL29:IMUX.IMUX.29.DELAY |
| SEL1_PRE_OPTINV | input | TCELL29:IMUX.IMUX.21.DELAY |
Bel BUFGCE_DIV0
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.41.DELAY |
| RST_PRE_OPTINV | input | TCELL28:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV1
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.42.DELAY |
| RST_PRE_OPTINV | input | TCELL29:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV2
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.43.DELAY |
| RST_PRE_OPTINV | input | TCELL30:IMUX.IMUX.0.DELAY |
Bel BUFGCE_DIV3
| Pin | Direction | Wires |
|---|---|---|
| CE_PRE_OPTINV | input | TCELL28:IMUX.IMUX.44.DELAY |
| RST_PRE_OPTINV | input | TCELL31:IMUX.IMUX.0.DELAY |
Bel PLLXP0
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL1:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL9:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL9:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL9:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL9:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL8:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL8:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL8:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL11:IMUX.CTRL.0 |
| DEN | input | TCELL11:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL13:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL13:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL11:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL11:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL10:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL10:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL10:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL10:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL13:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL13:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL12:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL12:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL12:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL12:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL11:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL11:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL12:OUT.0 |
| DOUT1 | output | TCELL12:OUT.1 |
| DOUT10 | output | TCELL9:OUT.1 |
| DOUT11 | output | TCELL9:OUT.2 |
| DOUT12 | output | TCELL8:OUT.0 |
| DOUT13 | output | TCELL8:OUT.1 |
| DOUT14 | output | TCELL8:OUT.2 |
| DOUT15 | output | TCELL7:OUT.0 |
| DOUT2 | output | TCELL12:OUT.2 |
| DOUT3 | output | TCELL11:OUT.0 |
| DOUT4 | output | TCELL11:OUT.1 |
| DOUT5 | output | TCELL11:OUT.2 |
| DOUT6 | output | TCELL10:OUT.0 |
| DOUT7 | output | TCELL10:OUT.1 |
| DOUT8 | output | TCELL10:OUT.2 |
| DOUT9 | output | TCELL9:OUT.0 |
| DRDY | output | TCELL13:OUT.1 |
| DWE | input | TCELL10:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL13:OUT.0 |
| PWRDWN | input | TCELL12:IMUX.IMUX.0.DELAY |
| RST | input | TCELL13:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL13:IMUX.CTRL.0 |
| SCANENB | input | TCELL7:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL8:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL6:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL13:OUT.2 |
| TESTIN0 | input | TCELL7:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL7:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL5:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL5:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL4:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL4:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL4:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL4:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL3:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL3:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL3:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL3:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL7:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL2:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL2:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL2:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL2:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL1:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL1:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL1:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL1:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL0:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL0:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL7:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL0:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL0:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL6:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL6:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL6:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL6:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL5:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL5:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL7:OUT.1 |
| TESTOUT1 | output | TCELL7:OUT.2 |
| TESTOUT10 | output | TCELL4:OUT.2 |
| TESTOUT11 | output | TCELL3:OUT.0 |
| TESTOUT12 | output | TCELL3:OUT.1 |
| TESTOUT13 | output | TCELL3:OUT.2 |
| TESTOUT14 | output | TCELL2:OUT.0 |
| TESTOUT15 | output | TCELL2:OUT.1 |
| TESTOUT2 | output | TCELL6:OUT.0 |
| TESTOUT3 | output | TCELL6:OUT.1 |
| TESTOUT4 | output | TCELL6:OUT.2 |
| TESTOUT5 | output | TCELL5:OUT.0 |
| TESTOUT6 | output | TCELL5:OUT.1 |
| TESTOUT7 | output | TCELL5:OUT.2 |
| TESTOUT8 | output | TCELL4:OUT.0 |
| TESTOUT9 | output | TCELL4:OUT.1 |
Bel PLLXP1
| Pin | Direction | Wires |
|---|---|---|
| CLKOUTPHY_EN | input | TCELL15:IMUX.IMUX.0.DELAY |
| DADDR0 | input | TCELL23:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL23:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL23:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL23:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL22:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL22:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL22:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL25:IMUX.CTRL.0 |
| DEN | input | TCELL25:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL27:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL27:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL25:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL25:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL24:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL24:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL24:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL24:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL27:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL27:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL26:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL26:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL26:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL26:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL25:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL25:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL26:OUT.0 |
| DOUT1 | output | TCELL26:OUT.1 |
| DOUT10 | output | TCELL23:OUT.1 |
| DOUT11 | output | TCELL23:OUT.2 |
| DOUT12 | output | TCELL22:OUT.0 |
| DOUT13 | output | TCELL22:OUT.1 |
| DOUT14 | output | TCELL22:OUT.2 |
| DOUT15 | output | TCELL21:OUT.0 |
| DOUT2 | output | TCELL26:OUT.2 |
| DOUT3 | output | TCELL25:OUT.0 |
| DOUT4 | output | TCELL25:OUT.1 |
| DOUT5 | output | TCELL25:OUT.2 |
| DOUT6 | output | TCELL24:OUT.0 |
| DOUT7 | output | TCELL24:OUT.1 |
| DOUT8 | output | TCELL24:OUT.2 |
| DOUT9 | output | TCELL23:OUT.0 |
| DRDY | output | TCELL27:OUT.1 |
| DWE | input | TCELL24:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL27:OUT.0 |
| PWRDWN | input | TCELL26:IMUX.IMUX.0.DELAY |
| RST | input | TCELL27:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL27:IMUX.CTRL.0 |
| SCANENB | input | TCELL21:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL22:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL20:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL27:OUT.2 |
| TESTIN0 | input | TCELL21:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL21:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL19:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL19:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL18:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL18:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL18:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL18:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL17:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL17:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL17:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL17:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL21:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL16:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL16:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL16:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL16:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL15:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL15:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL15:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL15:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL14:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL14:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL21:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL14:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL14:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL20:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL20:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL20:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL20:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL19:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL19:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL21:OUT.1 |
| TESTOUT1 | output | TCELL21:OUT.2 |
| TESTOUT10 | output | TCELL18:OUT.2 |
| TESTOUT11 | output | TCELL17:OUT.0 |
| TESTOUT12 | output | TCELL17:OUT.1 |
| TESTOUT13 | output | TCELL17:OUT.2 |
| TESTOUT14 | output | TCELL16:OUT.0 |
| TESTOUT15 | output | TCELL16:OUT.1 |
| TESTOUT2 | output | TCELL20:OUT.0 |
| TESTOUT3 | output | TCELL20:OUT.1 |
| TESTOUT4 | output | TCELL20:OUT.2 |
| TESTOUT5 | output | TCELL19:OUT.0 |
| TESTOUT6 | output | TCELL19:OUT.1 |
| TESTOUT7 | output | TCELL19:OUT.2 |
| TESTOUT8 | output | TCELL18:OUT.0 |
| TESTOUT9 | output | TCELL18:OUT.1 |
Bel MMCM
| Pin | Direction | Wires |
|---|---|---|
| CDDCDONE | output | TCELL56:OUT.0 |
| CDDCREQ | input | TCELL50:IMUX.IMUX.0.DELAY |
| CLKFBSTOPPED | output | TCELL55:OUT.0 |
| CLKINSEL | input | TCELL41:IMUX.IMUX.0.DELAY |
| CLKINSTOPPED | output | TCELL55:OUT.1 |
| DADDR0 | input | TCELL50:IMUX.BYP.0.DELAY |
| DADDR1 | input | TCELL50:IMUX.BYP.1.DELAY |
| DADDR2 | input | TCELL50:IMUX.BYP.2.DELAY |
| DADDR3 | input | TCELL50:IMUX.BYP.3.DELAY |
| DADDR4 | input | TCELL49:IMUX.BYP.0.DELAY |
| DADDR5 | input | TCELL49:IMUX.BYP.1.DELAY |
| DADDR6 | input | TCELL49:IMUX.BYP.2.DELAY |
| DCLK | input | TCELL52:IMUX.CTRL.0 |
| DEN | input | TCELL52:IMUX.IMUX.0.DELAY |
| DI0 | input | TCELL54:IMUX.BYP.0.DELAY |
| DI1 | input | TCELL54:IMUX.BYP.1.DELAY |
| DI10 | input | TCELL52:IMUX.BYP.2.DELAY |
| DI11 | input | TCELL52:IMUX.BYP.3.DELAY |
| DI12 | input | TCELL51:IMUX.BYP.0.DELAY |
| DI13 | input | TCELL51:IMUX.BYP.1.DELAY |
| DI14 | input | TCELL51:IMUX.BYP.2.DELAY |
| DI15 | input | TCELL51:IMUX.BYP.3.DELAY |
| DI2 | input | TCELL54:IMUX.BYP.2.DELAY |
| DI3 | input | TCELL54:IMUX.BYP.3.DELAY |
| DI4 | input | TCELL53:IMUX.BYP.0.DELAY |
| DI5 | input | TCELL53:IMUX.BYP.1.DELAY |
| DI6 | input | TCELL53:IMUX.BYP.2.DELAY |
| DI7 | input | TCELL53:IMUX.BYP.3.DELAY |
| DI8 | input | TCELL52:IMUX.BYP.0.DELAY |
| DI9 | input | TCELL52:IMUX.BYP.1.DELAY |
| DOUT0 | output | TCELL53:OUT.0 |
| DOUT1 | output | TCELL53:OUT.1 |
| DOUT10 | output | TCELL50:OUT.1 |
| DOUT11 | output | TCELL50:OUT.2 |
| DOUT12 | output | TCELL49:OUT.0 |
| DOUT13 | output | TCELL49:OUT.1 |
| DOUT14 | output | TCELL49:OUT.2 |
| DOUT15 | output | TCELL48:OUT.0 |
| DOUT2 | output | TCELL53:OUT.2 |
| DOUT3 | output | TCELL52:OUT.0 |
| DOUT4 | output | TCELL52:OUT.1 |
| DOUT5 | output | TCELL52:OUT.2 |
| DOUT6 | output | TCELL51:OUT.0 |
| DOUT7 | output | TCELL51:OUT.1 |
| DOUT8 | output | TCELL51:OUT.2 |
| DOUT9 | output | TCELL50:OUT.0 |
| DRDY | output | TCELL54:OUT.1 |
| DWE | input | TCELL51:IMUX.IMUX.0.DELAY |
| LOCKED | output | TCELL54:OUT.0 |
| PSCLK | input | TCELL53:IMUX.CTRL.0 |
| PSDONE | output | TCELL55:OUT.2 |
| PSEN | input | TCELL56:IMUX.IMUX.0.DELAY |
| PSINCDEC | input | TCELL55:IMUX.IMUX.0.DELAY |
| PWRDWN | input | TCELL53:IMUX.IMUX.0.DELAY |
| RST | input | TCELL54:IMUX.IMUX.0.DELAY |
| SCANCLK | input | TCELL54:IMUX.CTRL.0 |
| SCANENB | input | TCELL48:IMUX.IMUX.0.DELAY |
| SCANIN | input | TCELL49:IMUX.IMUX.0.DELAY |
| SCANMODEB | input | TCELL47:IMUX.IMUX.0.DELAY |
| SCANOUT | output | TCELL54:OUT.2 |
| TESTIN0 | input | TCELL48:IMUX.BYP.0.DELAY |
| TESTIN1 | input | TCELL48:IMUX.BYP.1.DELAY |
| TESTIN10 | input | TCELL46:IMUX.BYP.2.DELAY |
| TESTIN11 | input | TCELL46:IMUX.BYP.3.DELAY |
| TESTIN12 | input | TCELL45:IMUX.BYP.0.DELAY |
| TESTIN13 | input | TCELL45:IMUX.BYP.1.DELAY |
| TESTIN14 | input | TCELL45:IMUX.BYP.2.DELAY |
| TESTIN15 | input | TCELL45:IMUX.BYP.3.DELAY |
| TESTIN16 | input | TCELL44:IMUX.BYP.0.DELAY |
| TESTIN17 | input | TCELL44:IMUX.BYP.1.DELAY |
| TESTIN18 | input | TCELL44:IMUX.BYP.2.DELAY |
| TESTIN19 | input | TCELL44:IMUX.BYP.3.DELAY |
| TESTIN2 | input | TCELL48:IMUX.BYP.2.DELAY |
| TESTIN20 | input | TCELL43:IMUX.BYP.0.DELAY |
| TESTIN21 | input | TCELL43:IMUX.BYP.1.DELAY |
| TESTIN22 | input | TCELL43:IMUX.BYP.2.DELAY |
| TESTIN23 | input | TCELL43:IMUX.BYP.3.DELAY |
| TESTIN24 | input | TCELL42:IMUX.BYP.0.DELAY |
| TESTIN25 | input | TCELL42:IMUX.BYP.1.DELAY |
| TESTIN26 | input | TCELL42:IMUX.BYP.2.DELAY |
| TESTIN27 | input | TCELL42:IMUX.BYP.3.DELAY |
| TESTIN28 | input | TCELL41:IMUX.BYP.0.DELAY |
| TESTIN29 | input | TCELL41:IMUX.BYP.1.DELAY |
| TESTIN3 | input | TCELL48:IMUX.BYP.3.DELAY |
| TESTIN30 | input | TCELL41:IMUX.BYP.2.DELAY |
| TESTIN31 | input | TCELL41:IMUX.BYP.3.DELAY |
| TESTIN4 | input | TCELL47:IMUX.BYP.0.DELAY |
| TESTIN5 | input | TCELL47:IMUX.BYP.1.DELAY |
| TESTIN6 | input | TCELL47:IMUX.BYP.2.DELAY |
| TESTIN7 | input | TCELL47:IMUX.BYP.3.DELAY |
| TESTIN8 | input | TCELL46:IMUX.BYP.0.DELAY |
| TESTIN9 | input | TCELL46:IMUX.BYP.1.DELAY |
| TESTOUT0 | output | TCELL48:OUT.1 |
| TESTOUT1 | output | TCELL48:OUT.2 |
| TESTOUT10 | output | TCELL45:OUT.2 |
| TESTOUT11 | output | TCELL44:OUT.0 |
| TESTOUT12 | output | TCELL44:OUT.1 |
| TESTOUT13 | output | TCELL44:OUT.2 |
| TESTOUT14 | output | TCELL43:OUT.0 |
| TESTOUT15 | output | TCELL43:OUT.1 |
| TESTOUT2 | output | TCELL47:OUT.0 |
| TESTOUT3 | output | TCELL47:OUT.1 |
| TESTOUT4 | output | TCELL47:OUT.2 |
| TESTOUT5 | output | TCELL46:OUT.0 |
| TESTOUT6 | output | TCELL46:OUT.1 |
| TESTOUT7 | output | TCELL46:OUT.2 |
| TESTOUT8 | output | TCELL45:OUT.0 |
| TESTOUT9 | output | TCELL45:OUT.1 |
Bel CMTXP
| Pin | Direction | Wires |
|---|
Bel VCC_CMT
| Pin | Direction | Wires |
|---|
Bel ABUS_SWITCH_CMT
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL32:IMUX.IMUX.0.DELAY |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.BYP.0.DELAY | PLLXP0.TESTIN28 |
| TCELL0:IMUX.BYP.1.DELAY | PLLXP0.TESTIN29 |
| TCELL0:IMUX.BYP.2.DELAY | PLLXP0.TESTIN30 |
| TCELL0:IMUX.BYP.3.DELAY | PLLXP0.TESTIN31 |
| TCELL1:IMUX.BYP.0.DELAY | PLLXP0.TESTIN24 |
| TCELL1:IMUX.BYP.1.DELAY | PLLXP0.TESTIN25 |
| TCELL1:IMUX.BYP.2.DELAY | PLLXP0.TESTIN26 |
| TCELL1:IMUX.BYP.3.DELAY | PLLXP0.TESTIN27 |
| TCELL1:IMUX.IMUX.0.DELAY | PLLXP0.CLKOUTPHY_EN |
| TCELL2:OUT.0 | PLLXP0.TESTOUT14 |
| TCELL2:OUT.1 | PLLXP0.TESTOUT15 |
| TCELL2:IMUX.BYP.0.DELAY | PLLXP0.TESTIN20 |
| TCELL2:IMUX.BYP.1.DELAY | PLLXP0.TESTIN21 |
| TCELL2:IMUX.BYP.2.DELAY | PLLXP0.TESTIN22 |
| TCELL2:IMUX.BYP.3.DELAY | PLLXP0.TESTIN23 |
| TCELL3:OUT.0 | PLLXP0.TESTOUT11 |
| TCELL3:OUT.1 | PLLXP0.TESTOUT12 |
| TCELL3:OUT.2 | PLLXP0.TESTOUT13 |
| TCELL3:IMUX.BYP.0.DELAY | PLLXP0.TESTIN16 |
| TCELL3:IMUX.BYP.1.DELAY | PLLXP0.TESTIN17 |
| TCELL3:IMUX.BYP.2.DELAY | PLLXP0.TESTIN18 |
| TCELL3:IMUX.BYP.3.DELAY | PLLXP0.TESTIN19 |
| TCELL4:OUT.0 | PLLXP0.TESTOUT8 |
| TCELL4:OUT.1 | PLLXP0.TESTOUT9 |
| TCELL4:OUT.2 | PLLXP0.TESTOUT10 |
| TCELL4:IMUX.BYP.0.DELAY | PLLXP0.TESTIN12 |
| TCELL4:IMUX.BYP.1.DELAY | PLLXP0.TESTIN13 |
| TCELL4:IMUX.BYP.2.DELAY | PLLXP0.TESTIN14 |
| TCELL4:IMUX.BYP.3.DELAY | PLLXP0.TESTIN15 |
| TCELL5:OUT.0 | PLLXP0.TESTOUT5 |
| TCELL5:OUT.1 | PLLXP0.TESTOUT6 |
| TCELL5:OUT.2 | PLLXP0.TESTOUT7 |
| TCELL5:IMUX.BYP.0.DELAY | PLLXP0.TESTIN8 |
| TCELL5:IMUX.BYP.1.DELAY | PLLXP0.TESTIN9 |
| TCELL5:IMUX.BYP.2.DELAY | PLLXP0.TESTIN10 |
| TCELL5:IMUX.BYP.3.DELAY | PLLXP0.TESTIN11 |
| TCELL6:OUT.0 | PLLXP0.TESTOUT2 |
| TCELL6:OUT.1 | PLLXP0.TESTOUT3 |
| TCELL6:OUT.2 | PLLXP0.TESTOUT4 |
| TCELL6:IMUX.BYP.0.DELAY | PLLXP0.TESTIN4 |
| TCELL6:IMUX.BYP.1.DELAY | PLLXP0.TESTIN5 |
| TCELL6:IMUX.BYP.2.DELAY | PLLXP0.TESTIN6 |
| TCELL6:IMUX.BYP.3.DELAY | PLLXP0.TESTIN7 |
| TCELL6:IMUX.IMUX.0.DELAY | PLLXP0.SCANMODEB |
| TCELL7:OUT.0 | PLLXP0.DOUT15 |
| TCELL7:OUT.1 | PLLXP0.TESTOUT0 |
| TCELL7:OUT.2 | PLLXP0.TESTOUT1 |
| TCELL7:IMUX.BYP.0.DELAY | PLLXP0.TESTIN0 |
| TCELL7:IMUX.BYP.1.DELAY | PLLXP0.TESTIN1 |
| TCELL7:IMUX.BYP.2.DELAY | PLLXP0.TESTIN2 |
| TCELL7:IMUX.BYP.3.DELAY | PLLXP0.TESTIN3 |
| TCELL7:IMUX.IMUX.0.DELAY | PLLXP0.SCANENB |
| TCELL8:OUT.0 | PLLXP0.DOUT12 |
| TCELL8:OUT.1 | PLLXP0.DOUT13 |
| TCELL8:OUT.2 | PLLXP0.DOUT14 |
| TCELL8:IMUX.BYP.0.DELAY | PLLXP0.DADDR4 |
| TCELL8:IMUX.BYP.1.DELAY | PLLXP0.DADDR5 |
| TCELL8:IMUX.BYP.2.DELAY | PLLXP0.DADDR6 |
| TCELL8:IMUX.IMUX.0.DELAY | PLLXP0.SCANIN |
| TCELL9:OUT.0 | PLLXP0.DOUT9 |
| TCELL9:OUT.1 | PLLXP0.DOUT10 |
| TCELL9:OUT.2 | PLLXP0.DOUT11 |
| TCELL9:IMUX.BYP.0.DELAY | PLLXP0.DADDR0 |
| TCELL9:IMUX.BYP.1.DELAY | PLLXP0.DADDR1 |
| TCELL9:IMUX.BYP.2.DELAY | PLLXP0.DADDR2 |
| TCELL9:IMUX.BYP.3.DELAY | PLLXP0.DADDR3 |
| TCELL10:OUT.0 | PLLXP0.DOUT6 |
| TCELL10:OUT.1 | PLLXP0.DOUT7 |
| TCELL10:OUT.2 | PLLXP0.DOUT8 |
| TCELL10:IMUX.BYP.0.DELAY | PLLXP0.DI12 |
| TCELL10:IMUX.BYP.1.DELAY | PLLXP0.DI13 |
| TCELL10:IMUX.BYP.2.DELAY | PLLXP0.DI14 |
| TCELL10:IMUX.BYP.3.DELAY | PLLXP0.DI15 |
| TCELL10:IMUX.IMUX.0.DELAY | PLLXP0.DWE |
| TCELL11:OUT.0 | PLLXP0.DOUT3 |
| TCELL11:OUT.1 | PLLXP0.DOUT4 |
| TCELL11:OUT.2 | PLLXP0.DOUT5 |
| TCELL11:IMUX.CTRL.0 | PLLXP0.DCLK |
| TCELL11:IMUX.BYP.0.DELAY | PLLXP0.DI8 |
| TCELL11:IMUX.BYP.1.DELAY | PLLXP0.DI9 |
| TCELL11:IMUX.BYP.2.DELAY | PLLXP0.DI10 |
| TCELL11:IMUX.BYP.3.DELAY | PLLXP0.DI11 |
| TCELL11:IMUX.IMUX.0.DELAY | PLLXP0.DEN |
| TCELL12:OUT.0 | PLLXP0.DOUT0 |
| TCELL12:OUT.1 | PLLXP0.DOUT1 |
| TCELL12:OUT.2 | PLLXP0.DOUT2 |
| TCELL12:IMUX.BYP.0.DELAY | PLLXP0.DI4 |
| TCELL12:IMUX.BYP.1.DELAY | PLLXP0.DI5 |
| TCELL12:IMUX.BYP.2.DELAY | PLLXP0.DI6 |
| TCELL12:IMUX.BYP.3.DELAY | PLLXP0.DI7 |
| TCELL12:IMUX.IMUX.0.DELAY | PLLXP0.PWRDWN |
| TCELL13:OUT.0 | PLLXP0.LOCKED |
| TCELL13:OUT.1 | PLLXP0.DRDY |
| TCELL13:OUT.2 | PLLXP0.SCANOUT |
| TCELL13:IMUX.CTRL.0 | PLLXP0.SCANCLK |
| TCELL13:IMUX.BYP.0.DELAY | PLLXP0.DI0 |
| TCELL13:IMUX.BYP.1.DELAY | PLLXP0.DI1 |
| TCELL13:IMUX.BYP.2.DELAY | PLLXP0.DI2 |
| TCELL13:IMUX.BYP.3.DELAY | PLLXP0.DI3 |
| TCELL13:IMUX.IMUX.0.DELAY | PLLXP0.RST |
| TCELL14:IMUX.BYP.0.DELAY | PLLXP1.TESTIN28 |
| TCELL14:IMUX.BYP.1.DELAY | PLLXP1.TESTIN29 |
| TCELL14:IMUX.BYP.2.DELAY | PLLXP1.TESTIN30 |
| TCELL14:IMUX.BYP.3.DELAY | PLLXP1.TESTIN31 |
| TCELL15:IMUX.BYP.0.DELAY | PLLXP1.TESTIN24 |
| TCELL15:IMUX.BYP.1.DELAY | PLLXP1.TESTIN25 |
| TCELL15:IMUX.BYP.2.DELAY | PLLXP1.TESTIN26 |
| TCELL15:IMUX.BYP.3.DELAY | PLLXP1.TESTIN27 |
| TCELL15:IMUX.IMUX.0.DELAY | PLLXP1.CLKOUTPHY_EN |
| TCELL16:OUT.0 | PLLXP1.TESTOUT14 |
| TCELL16:OUT.1 | PLLXP1.TESTOUT15 |
| TCELL16:IMUX.BYP.0.DELAY | PLLXP1.TESTIN20 |
| TCELL16:IMUX.BYP.1.DELAY | PLLXP1.TESTIN21 |
| TCELL16:IMUX.BYP.2.DELAY | PLLXP1.TESTIN22 |
| TCELL16:IMUX.BYP.3.DELAY | PLLXP1.TESTIN23 |
| TCELL17:OUT.0 | PLLXP1.TESTOUT11 |
| TCELL17:OUT.1 | PLLXP1.TESTOUT12 |
| TCELL17:OUT.2 | PLLXP1.TESTOUT13 |
| TCELL17:IMUX.BYP.0.DELAY | PLLXP1.TESTIN16 |
| TCELL17:IMUX.BYP.1.DELAY | PLLXP1.TESTIN17 |
| TCELL17:IMUX.BYP.2.DELAY | PLLXP1.TESTIN18 |
| TCELL17:IMUX.BYP.3.DELAY | PLLXP1.TESTIN19 |
| TCELL18:OUT.0 | PLLXP1.TESTOUT8 |
| TCELL18:OUT.1 | PLLXP1.TESTOUT9 |
| TCELL18:OUT.2 | PLLXP1.TESTOUT10 |
| TCELL18:IMUX.BYP.0.DELAY | PLLXP1.TESTIN12 |
| TCELL18:IMUX.BYP.1.DELAY | PLLXP1.TESTIN13 |
| TCELL18:IMUX.BYP.2.DELAY | PLLXP1.TESTIN14 |
| TCELL18:IMUX.BYP.3.DELAY | PLLXP1.TESTIN15 |
| TCELL19:OUT.0 | PLLXP1.TESTOUT5 |
| TCELL19:OUT.1 | PLLXP1.TESTOUT6 |
| TCELL19:OUT.2 | PLLXP1.TESTOUT7 |
| TCELL19:IMUX.BYP.0.DELAY | PLLXP1.TESTIN8 |
| TCELL19:IMUX.BYP.1.DELAY | PLLXP1.TESTIN9 |
| TCELL19:IMUX.BYP.2.DELAY | PLLXP1.TESTIN10 |
| TCELL19:IMUX.BYP.3.DELAY | PLLXP1.TESTIN11 |
| TCELL20:OUT.0 | PLLXP1.TESTOUT2 |
| TCELL20:OUT.1 | PLLXP1.TESTOUT3 |
| TCELL20:OUT.2 | PLLXP1.TESTOUT4 |
| TCELL20:IMUX.BYP.0.DELAY | PLLXP1.TESTIN4 |
| TCELL20:IMUX.BYP.1.DELAY | PLLXP1.TESTIN5 |
| TCELL20:IMUX.BYP.2.DELAY | PLLXP1.TESTIN6 |
| TCELL20:IMUX.BYP.3.DELAY | PLLXP1.TESTIN7 |
| TCELL20:IMUX.IMUX.0.DELAY | PLLXP1.SCANMODEB |
| TCELL21:OUT.0 | PLLXP1.DOUT15 |
| TCELL21:OUT.1 | PLLXP1.TESTOUT0 |
| TCELL21:OUT.2 | PLLXP1.TESTOUT1 |
| TCELL21:IMUX.BYP.0.DELAY | PLLXP1.TESTIN0 |
| TCELL21:IMUX.BYP.1.DELAY | PLLXP1.TESTIN1 |
| TCELL21:IMUX.BYP.2.DELAY | PLLXP1.TESTIN2 |
| TCELL21:IMUX.BYP.3.DELAY | PLLXP1.TESTIN3 |
| TCELL21:IMUX.IMUX.0.DELAY | PLLXP1.SCANENB |
| TCELL22:OUT.0 | PLLXP1.DOUT12 |
| TCELL22:OUT.1 | PLLXP1.DOUT13 |
| TCELL22:OUT.2 | PLLXP1.DOUT14 |
| TCELL22:IMUX.BYP.0.DELAY | PLLXP1.DADDR4 |
| TCELL22:IMUX.BYP.1.DELAY | PLLXP1.DADDR5 |
| TCELL22:IMUX.BYP.2.DELAY | PLLXP1.DADDR6 |
| TCELL22:IMUX.IMUX.0.DELAY | PLLXP1.SCANIN |
| TCELL23:OUT.0 | PLLXP1.DOUT9 |
| TCELL23:OUT.1 | PLLXP1.DOUT10 |
| TCELL23:OUT.2 | PLLXP1.DOUT11 |
| TCELL23:IMUX.BYP.0.DELAY | PLLXP1.DADDR0 |
| TCELL23:IMUX.BYP.1.DELAY | PLLXP1.DADDR1 |
| TCELL23:IMUX.BYP.2.DELAY | PLLXP1.DADDR2 |
| TCELL23:IMUX.BYP.3.DELAY | PLLXP1.DADDR3 |
| TCELL24:OUT.0 | PLLXP1.DOUT6 |
| TCELL24:OUT.1 | PLLXP1.DOUT7 |
| TCELL24:OUT.2 | PLLXP1.DOUT8 |
| TCELL24:IMUX.BYP.0.DELAY | PLLXP1.DI12 |
| TCELL24:IMUX.BYP.1.DELAY | PLLXP1.DI13 |
| TCELL24:IMUX.BYP.2.DELAY | PLLXP1.DI14 |
| TCELL24:IMUX.BYP.3.DELAY | PLLXP1.DI15 |
| TCELL24:IMUX.IMUX.0.DELAY | PLLXP1.DWE |
| TCELL25:OUT.0 | PLLXP1.DOUT3 |
| TCELL25:OUT.1 | PLLXP1.DOUT4 |
| TCELL25:OUT.2 | PLLXP1.DOUT5 |
| TCELL25:IMUX.CTRL.0 | PLLXP1.DCLK |
| TCELL25:IMUX.BYP.0.DELAY | PLLXP1.DI8 |
| TCELL25:IMUX.BYP.1.DELAY | PLLXP1.DI9 |
| TCELL25:IMUX.BYP.2.DELAY | PLLXP1.DI10 |
| TCELL25:IMUX.BYP.3.DELAY | PLLXP1.DI11 |
| TCELL25:IMUX.IMUX.0.DELAY | PLLXP1.DEN |
| TCELL26:OUT.0 | PLLXP1.DOUT0 |
| TCELL26:OUT.1 | PLLXP1.DOUT1 |
| TCELL26:OUT.2 | PLLXP1.DOUT2 |
| TCELL26:IMUX.BYP.0.DELAY | PLLXP1.DI4 |
| TCELL26:IMUX.BYP.1.DELAY | PLLXP1.DI5 |
| TCELL26:IMUX.BYP.2.DELAY | PLLXP1.DI6 |
| TCELL26:IMUX.BYP.3.DELAY | PLLXP1.DI7 |
| TCELL26:IMUX.IMUX.0.DELAY | PLLXP1.PWRDWN |
| TCELL27:OUT.0 | PLLXP1.LOCKED |
| TCELL27:OUT.1 | PLLXP1.DRDY |
| TCELL27:OUT.2 | PLLXP1.SCANOUT |
| TCELL27:IMUX.CTRL.0 | PLLXP1.SCANCLK |
| TCELL27:IMUX.BYP.0.DELAY | PLLXP1.DI0 |
| TCELL27:IMUX.BYP.1.DELAY | PLLXP1.DI1 |
| TCELL27:IMUX.BYP.2.DELAY | PLLXP1.DI2 |
| TCELL27:IMUX.BYP.3.DELAY | PLLXP1.DI3 |
| TCELL27:IMUX.IMUX.0.DELAY | PLLXP1.RST |
| TCELL28:IMUX.IMUX.0.DELAY | BUFGCE_DIV0.RST_PRE_OPTINV |
| TCELL28:IMUX.IMUX.17.DELAY | BUFCE_ROW_CMT0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.18.DELAY | BUFCE_ROW_CMT1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.19.DELAY | BUFCE_ROW_CMT2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.20.DELAY | BUFCE_ROW_CMT3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.21.DELAY | BUFCE_ROW_CMT4.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.22.DELAY | BUFCE_ROW_CMT5.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.23.DELAY | BUFCE_ROW_CMT6.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.24.DELAY | BUFCE_ROW_CMT7.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.25.DELAY | BUFCE_ROW_CMT8.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.26.DELAY | BUFCE_ROW_CMT9.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.27.DELAY | BUFCE_ROW_CMT10.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.28.DELAY | BUFCE_ROW_CMT11.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.29.DELAY | BUFCE_ROW_CMT12.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.30.DELAY | BUFCE_ROW_CMT13.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.31.DELAY | BUFCE_ROW_CMT14.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.32.DELAY | BUFCE_ROW_CMT15.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.33.DELAY | BUFCE_ROW_CMT16.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.34.DELAY | BUFCE_ROW_CMT17.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.35.DELAY | BUFCE_ROW_CMT18.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.36.DELAY | BUFCE_ROW_CMT19.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.37.DELAY | BUFCE_ROW_CMT20.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.38.DELAY | BUFCE_ROW_CMT21.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.39.DELAY | BUFCE_ROW_CMT22.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.40.DELAY | BUFCE_ROW_CMT23.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.41.DELAY | BUFGCE_DIV0.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.42.DELAY | BUFGCE_DIV1.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.43.DELAY | BUFGCE_DIV2.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.44.DELAY | BUFGCE_DIV3.CE_PRE_OPTINV |
| TCELL28:IMUX.IMUX.45.DELAY | BUFGCTRL0.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.46.DELAY | BUFGCTRL1.SEL1_PRE_OPTINV |
| TCELL28:IMUX.IMUX.47.DELAY | BUFGCTRL2.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.0.DELAY | BUFGCE_DIV1.RST_PRE_OPTINV |
| TCELL29:IMUX.IMUX.17.DELAY | BUFGCTRL3.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.18.DELAY | BUFGCTRL4.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.19.DELAY | BUFGCTRL5.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.20.DELAY | BUFGCTRL6.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.21.DELAY | BUFGCTRL7.SEL1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.22.DELAY | BUFGCTRL0.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.23.DELAY | BUFGCTRL1.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.24.DELAY | BUFGCTRL2.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.25.DELAY | BUFGCTRL3.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.26.DELAY | BUFGCTRL4.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.27.DELAY | BUFGCTRL5.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.28.DELAY | BUFGCTRL6.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.29.DELAY | BUFGCTRL7.SEL0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.30.DELAY | BUFGCTRL0.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.31.DELAY | BUFGCTRL1.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.32.DELAY | BUFGCTRL2.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.33.DELAY | BUFGCTRL3.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.34.DELAY | BUFGCTRL4.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.35.DELAY | BUFGCTRL5.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.36.DELAY | BUFGCTRL6.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.37.DELAY | BUFGCTRL7.IGNORE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.38.DELAY | BUFGCTRL0.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.39.DELAY | BUFGCTRL1.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.40.DELAY | BUFGCTRL2.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.41.DELAY | BUFGCTRL3.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.42.DELAY | BUFGCTRL4.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.43.DELAY | BUFGCTRL5.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.44.DELAY | BUFGCTRL6.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.45.DELAY | BUFGCTRL7.IGNORE0_PRE_OPTINV |
| TCELL29:IMUX.IMUX.46.DELAY | BUFGCTRL0.CE1_PRE_OPTINV |
| TCELL29:IMUX.IMUX.47.DELAY | BUFGCTRL1.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.0.DELAY | BUFGCE_DIV2.RST_PRE_OPTINV |
| TCELL30:IMUX.IMUX.17.DELAY | BUFGCTRL2.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.18.DELAY | BUFGCTRL3.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.19.DELAY | BUFGCTRL4.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.20.DELAY | BUFGCTRL5.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.21.DELAY | BUFGCTRL6.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.22.DELAY | BUFGCTRL7.CE1_PRE_OPTINV |
| TCELL30:IMUX.IMUX.23.DELAY | BUFGCTRL0.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.24.DELAY | BUFGCTRL1.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.25.DELAY | BUFGCTRL2.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.26.DELAY | BUFGCTRL3.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.27.DELAY | BUFGCTRL4.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.28.DELAY | BUFGCTRL5.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.29.DELAY | BUFGCTRL6.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.30.DELAY | BUFGCTRL7.CE0_PRE_OPTINV |
| TCELL30:IMUX.IMUX.31.DELAY | BUFGCE0.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.32.DELAY | BUFGCE1.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.33.DELAY | BUFGCE2.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.34.DELAY | BUFGCE3.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.35.DELAY | BUFGCE4.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.36.DELAY | BUFGCE5.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.37.DELAY | BUFGCE6.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.38.DELAY | BUFGCE7.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.39.DELAY | BUFGCE8.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.40.DELAY | BUFGCE9.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.41.DELAY | BUFGCE10.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.42.DELAY | BUFGCE11.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.43.DELAY | BUFGCE12.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.44.DELAY | BUFGCE13.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.45.DELAY | BUFGCE14.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.46.DELAY | BUFGCE15.CE_PRE_OPTINV |
| TCELL30:IMUX.IMUX.47.DELAY | BUFGCE16.CE_PRE_OPTINV |
| TCELL30:RCLK.IMUX.16 | BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.17 | BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0 |
| TCELL30:RCLK.IMUX.18 | BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.19 | BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1 |
| TCELL30:RCLK.IMUX.20 | BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2 |
| TCELL30:RCLK.IMUX.21 | BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2 |
| TCELL31:IMUX.IMUX.0.DELAY | BUFGCE_DIV3.RST_PRE_OPTINV |
| TCELL31:IMUX.IMUX.17.DELAY | BUFGCE17.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.18.DELAY | BUFGCE18.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.19.DELAY | BUFGCE19.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.20.DELAY | BUFGCE20.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.21.DELAY | BUFGCE21.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.22.DELAY | BUFGCE22.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.23.DELAY | BUFGCE23.CE_PRE_OPTINV |
| TCELL31:IMUX.IMUX.24.DELAY | BUFGCE0.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.25.DELAY | BUFGCE1.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.26.DELAY | BUFGCE2.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.27.DELAY | BUFGCE3.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.28.DELAY | BUFGCE4.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.29.DELAY | BUFGCE5.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.30.DELAY | BUFGCE6.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.31.DELAY | BUFGCE7.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.32.DELAY | BUFGCE8.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.33.DELAY | BUFGCE9.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.34.DELAY | BUFGCE10.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.35.DELAY | BUFGCE11.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.36.DELAY | BUFGCE12.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.37.DELAY | BUFGCE13.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.38.DELAY | BUFGCE14.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.39.DELAY | BUFGCE15.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.40.DELAY | BUFGCE16.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.41.DELAY | BUFGCE17.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.42.DELAY | BUFGCE18.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.43.DELAY | BUFGCE19.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.44.DELAY | BUFGCE20.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.45.DELAY | BUFGCE21.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.46.DELAY | BUFGCE22.CLK_IN_CKINT |
| TCELL31:IMUX.IMUX.47.DELAY | BUFGCE23.CLK_IN_CKINT |
| TCELL32:IMUX.IMUX.0.DELAY | ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B |
| TCELL41:IMUX.BYP.0.DELAY | MMCM.TESTIN28 |
| TCELL41:IMUX.BYP.1.DELAY | MMCM.TESTIN29 |
| TCELL41:IMUX.BYP.2.DELAY | MMCM.TESTIN30 |
| TCELL41:IMUX.BYP.3.DELAY | MMCM.TESTIN31 |
| TCELL41:IMUX.IMUX.0.DELAY | MMCM.CLKINSEL |
| TCELL42:IMUX.BYP.0.DELAY | MMCM.TESTIN24 |
| TCELL42:IMUX.BYP.1.DELAY | MMCM.TESTIN25 |
| TCELL42:IMUX.BYP.2.DELAY | MMCM.TESTIN26 |
| TCELL42:IMUX.BYP.3.DELAY | MMCM.TESTIN27 |
| TCELL43:OUT.0 | MMCM.TESTOUT14 |
| TCELL43:OUT.1 | MMCM.TESTOUT15 |
| TCELL43:IMUX.BYP.0.DELAY | MMCM.TESTIN20 |
| TCELL43:IMUX.BYP.1.DELAY | MMCM.TESTIN21 |
| TCELL43:IMUX.BYP.2.DELAY | MMCM.TESTIN22 |
| TCELL43:IMUX.BYP.3.DELAY | MMCM.TESTIN23 |
| TCELL44:OUT.0 | MMCM.TESTOUT11 |
| TCELL44:OUT.1 | MMCM.TESTOUT12 |
| TCELL44:OUT.2 | MMCM.TESTOUT13 |
| TCELL44:IMUX.BYP.0.DELAY | MMCM.TESTIN16 |
| TCELL44:IMUX.BYP.1.DELAY | MMCM.TESTIN17 |
| TCELL44:IMUX.BYP.2.DELAY | MMCM.TESTIN18 |
| TCELL44:IMUX.BYP.3.DELAY | MMCM.TESTIN19 |
| TCELL45:OUT.0 | MMCM.TESTOUT8 |
| TCELL45:OUT.1 | MMCM.TESTOUT9 |
| TCELL45:OUT.2 | MMCM.TESTOUT10 |
| TCELL45:IMUX.BYP.0.DELAY | MMCM.TESTIN12 |
| TCELL45:IMUX.BYP.1.DELAY | MMCM.TESTIN13 |
| TCELL45:IMUX.BYP.2.DELAY | MMCM.TESTIN14 |
| TCELL45:IMUX.BYP.3.DELAY | MMCM.TESTIN15 |
| TCELL46:OUT.0 | MMCM.TESTOUT5 |
| TCELL46:OUT.1 | MMCM.TESTOUT6 |
| TCELL46:OUT.2 | MMCM.TESTOUT7 |
| TCELL46:IMUX.BYP.0.DELAY | MMCM.TESTIN8 |
| TCELL46:IMUX.BYP.1.DELAY | MMCM.TESTIN9 |
| TCELL46:IMUX.BYP.2.DELAY | MMCM.TESTIN10 |
| TCELL46:IMUX.BYP.3.DELAY | MMCM.TESTIN11 |
| TCELL47:OUT.0 | MMCM.TESTOUT2 |
| TCELL47:OUT.1 | MMCM.TESTOUT3 |
| TCELL47:OUT.2 | MMCM.TESTOUT4 |
| TCELL47:IMUX.BYP.0.DELAY | MMCM.TESTIN4 |
| TCELL47:IMUX.BYP.1.DELAY | MMCM.TESTIN5 |
| TCELL47:IMUX.BYP.2.DELAY | MMCM.TESTIN6 |
| TCELL47:IMUX.BYP.3.DELAY | MMCM.TESTIN7 |
| TCELL47:IMUX.IMUX.0.DELAY | MMCM.SCANMODEB |
| TCELL48:OUT.0 | MMCM.DOUT15 |
| TCELL48:OUT.1 | MMCM.TESTOUT0 |
| TCELL48:OUT.2 | MMCM.TESTOUT1 |
| TCELL48:IMUX.BYP.0.DELAY | MMCM.TESTIN0 |
| TCELL48:IMUX.BYP.1.DELAY | MMCM.TESTIN1 |
| TCELL48:IMUX.BYP.2.DELAY | MMCM.TESTIN2 |
| TCELL48:IMUX.BYP.3.DELAY | MMCM.TESTIN3 |
| TCELL48:IMUX.IMUX.0.DELAY | MMCM.SCANENB |
| TCELL49:OUT.0 | MMCM.DOUT12 |
| TCELL49:OUT.1 | MMCM.DOUT13 |
| TCELL49:OUT.2 | MMCM.DOUT14 |
| TCELL49:IMUX.BYP.0.DELAY | MMCM.DADDR4 |
| TCELL49:IMUX.BYP.1.DELAY | MMCM.DADDR5 |
| TCELL49:IMUX.BYP.2.DELAY | MMCM.DADDR6 |
| TCELL49:IMUX.IMUX.0.DELAY | MMCM.SCANIN |
| TCELL50:OUT.0 | MMCM.DOUT9 |
| TCELL50:OUT.1 | MMCM.DOUT10 |
| TCELL50:OUT.2 | MMCM.DOUT11 |
| TCELL50:IMUX.BYP.0.DELAY | MMCM.DADDR0 |
| TCELL50:IMUX.BYP.1.DELAY | MMCM.DADDR1 |
| TCELL50:IMUX.BYP.2.DELAY | MMCM.DADDR2 |
| TCELL50:IMUX.BYP.3.DELAY | MMCM.DADDR3 |
| TCELL50:IMUX.IMUX.0.DELAY | MMCM.CDDCREQ |
| TCELL51:OUT.0 | MMCM.DOUT6 |
| TCELL51:OUT.1 | MMCM.DOUT7 |
| TCELL51:OUT.2 | MMCM.DOUT8 |
| TCELL51:IMUX.BYP.0.DELAY | MMCM.DI12 |
| TCELL51:IMUX.BYP.1.DELAY | MMCM.DI13 |
| TCELL51:IMUX.BYP.2.DELAY | MMCM.DI14 |
| TCELL51:IMUX.BYP.3.DELAY | MMCM.DI15 |
| TCELL51:IMUX.IMUX.0.DELAY | MMCM.DWE |
| TCELL52:OUT.0 | MMCM.DOUT3 |
| TCELL52:OUT.1 | MMCM.DOUT4 |
| TCELL52:OUT.2 | MMCM.DOUT5 |
| TCELL52:IMUX.CTRL.0 | MMCM.DCLK |
| TCELL52:IMUX.BYP.0.DELAY | MMCM.DI8 |
| TCELL52:IMUX.BYP.1.DELAY | MMCM.DI9 |
| TCELL52:IMUX.BYP.2.DELAY | MMCM.DI10 |
| TCELL52:IMUX.BYP.3.DELAY | MMCM.DI11 |
| TCELL52:IMUX.IMUX.0.DELAY | MMCM.DEN |
| TCELL53:OUT.0 | MMCM.DOUT0 |
| TCELL53:OUT.1 | MMCM.DOUT1 |
| TCELL53:OUT.2 | MMCM.DOUT2 |
| TCELL53:IMUX.CTRL.0 | MMCM.PSCLK |
| TCELL53:IMUX.BYP.0.DELAY | MMCM.DI4 |
| TCELL53:IMUX.BYP.1.DELAY | MMCM.DI5 |
| TCELL53:IMUX.BYP.2.DELAY | MMCM.DI6 |
| TCELL53:IMUX.BYP.3.DELAY | MMCM.DI7 |
| TCELL53:IMUX.IMUX.0.DELAY | MMCM.PWRDWN |
| TCELL54:OUT.0 | MMCM.LOCKED |
| TCELL54:OUT.1 | MMCM.DRDY |
| TCELL54:OUT.2 | MMCM.SCANOUT |
| TCELL54:IMUX.CTRL.0 | MMCM.SCANCLK |
| TCELL54:IMUX.BYP.0.DELAY | MMCM.DI0 |
| TCELL54:IMUX.BYP.1.DELAY | MMCM.DI1 |
| TCELL54:IMUX.BYP.2.DELAY | MMCM.DI2 |
| TCELL54:IMUX.BYP.3.DELAY | MMCM.DI3 |
| TCELL54:IMUX.IMUX.0.DELAY | MMCM.RST |
| TCELL55:OUT.0 | MMCM.CLKFBSTOPPED |
| TCELL55:OUT.1 | MMCM.CLKINSTOPPED |
| TCELL55:OUT.2 | MMCM.PSDONE |
| TCELL55:IMUX.IMUX.0.DELAY | MMCM.PSINCDEC |
| TCELL56:OUT.0 | MMCM.CDDCDONE |
| TCELL56:IMUX.IMUX.0.DELAY | MMCM.PSEN |