Clock Management Tile

Tile CMT

Cells: 60 IRIs: 0

Bel BUFCE_ROW_CMT0

ultrascaleplus CMT bel BUFCE_ROW_CMT0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.17
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT1

ultrascaleplus CMT bel BUFCE_ROW_CMT1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.18
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT2

ultrascaleplus CMT bel BUFCE_ROW_CMT2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.19
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT3

ultrascaleplus CMT bel BUFCE_ROW_CMT3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.20
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT4

ultrascaleplus CMT bel BUFCE_ROW_CMT4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.21
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT5

ultrascaleplus CMT bel BUFCE_ROW_CMT5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.22
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT6

ultrascaleplus CMT bel BUFCE_ROW_CMT6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.23
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT7

ultrascaleplus CMT bel BUFCE_ROW_CMT7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.24
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT8

ultrascaleplus CMT bel BUFCE_ROW_CMT8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.25
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT9

ultrascaleplus CMT bel BUFCE_ROW_CMT9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.26
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT10

ultrascaleplus CMT bel BUFCE_ROW_CMT10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.27
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT11

ultrascaleplus CMT bel BUFCE_ROW_CMT11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.28
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT12

ultrascaleplus CMT bel BUFCE_ROW_CMT12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.29
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT13

ultrascaleplus CMT bel BUFCE_ROW_CMT13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.30
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT14

ultrascaleplus CMT bel BUFCE_ROW_CMT14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.31
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT15

ultrascaleplus CMT bel BUFCE_ROW_CMT15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.32
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT16

ultrascaleplus CMT bel BUFCE_ROW_CMT16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.33
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT17

ultrascaleplus CMT bel BUFCE_ROW_CMT17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.34
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT18

ultrascaleplus CMT bel BUFCE_ROW_CMT18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.35
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT19

ultrascaleplus CMT bel BUFCE_ROW_CMT19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.36
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT20

ultrascaleplus CMT bel BUFCE_ROW_CMT20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.37
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT21

ultrascaleplus CMT bel BUFCE_ROW_CMT21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.38
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT22

ultrascaleplus CMT bel BUFCE_ROW_CMT22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.39
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT23

ultrascaleplus CMT bel BUFCE_ROW_CMT23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.40
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel GCLK_TEST_BUF_CMT0

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT1

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT1
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT2

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT2
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT3

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT3
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT4

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT4
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT5

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT5
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT6

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT6
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT7

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT7
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT8

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT8
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT9

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT9
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT10

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT10
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT11

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT11
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT12

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT12
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT13

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT13
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT14

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT14
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT15

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT15
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT16

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT16
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT17

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT17
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT18

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT18
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT19

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT19
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT20

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT20
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT21

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT21
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT22

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT22
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT23

ultrascaleplus CMT bel GCLK_TEST_BUF_CMT23
Pin	Direction	Wires

Bel BUFGCE0

ultrascaleplus CMT bel BUFGCE0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.31
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.24

Bel BUFGCE1

ultrascaleplus CMT bel BUFGCE1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.32
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.25

Bel BUFGCE2

ultrascaleplus CMT bel BUFGCE2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.33
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.26

Bel BUFGCE3

ultrascaleplus CMT bel BUFGCE3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.34
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.27

Bel BUFGCE4

ultrascaleplus CMT bel BUFGCE4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.35
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.28

Bel BUFGCE5

ultrascaleplus CMT bel BUFGCE5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.36
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.29

Bel BUFGCE6

ultrascaleplus CMT bel BUFGCE6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.37
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.30

Bel BUFGCE7

ultrascaleplus CMT bel BUFGCE7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.38
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.31

Bel BUFGCE8

ultrascaleplus CMT bel BUFGCE8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.39
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.32

Bel BUFGCE9

ultrascaleplus CMT bel BUFGCE9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.40
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.33

Bel BUFGCE10

ultrascaleplus CMT bel BUFGCE10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.41
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.34

Bel BUFGCE11

ultrascaleplus CMT bel BUFGCE11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.42
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.35

Bel BUFGCE12

ultrascaleplus CMT bel BUFGCE12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.43
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.36

Bel BUFGCE13

ultrascaleplus CMT bel BUFGCE13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.44
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.37

Bel BUFGCE14

ultrascaleplus CMT bel BUFGCE14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.45
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.38

Bel BUFGCE15

ultrascaleplus CMT bel BUFGCE15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.46
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.39

Bel BUFGCE16

ultrascaleplus CMT bel BUFGCE16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.47
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.40

Bel BUFGCE17

ultrascaleplus CMT bel BUFGCE17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.17
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.41

Bel BUFGCE18

ultrascaleplus CMT bel BUFGCE18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.18
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.42

Bel BUFGCE19

ultrascaleplus CMT bel BUFGCE19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.19
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.43

Bel BUFGCE20

ultrascaleplus CMT bel BUFGCE20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.20
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.44

Bel BUFGCE21

ultrascaleplus CMT bel BUFGCE21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.21
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.45

Bel BUFGCE22

ultrascaleplus CMT bel BUFGCE22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.22
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.46

Bel BUFGCE23

ultrascaleplus CMT bel BUFGCE23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.23
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.47

Bel BUFGCTRL0

ultrascaleplus CMT bel BUFGCTRL0
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.23
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.46
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.38
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.30
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.22
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.45

Bel BUFGCTRL1

ultrascaleplus CMT bel BUFGCTRL1
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.24
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.47
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.39
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.31
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.23
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.46

Bel BUFGCTRL2

ultrascaleplus CMT bel BUFGCTRL2
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.25
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.17
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.40
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.32
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.24
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.47

Bel BUFGCTRL3

ultrascaleplus CMT bel BUFGCTRL3
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.26
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.18
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.41
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.33
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.25
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.17

Bel BUFGCTRL4

ultrascaleplus CMT bel BUFGCTRL4
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.27
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.19
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.42
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.34
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.26
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.18

Bel BUFGCTRL5

ultrascaleplus CMT bel BUFGCTRL5
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.28
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.20
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.43
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.35
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.27
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.19

Bel BUFGCTRL6

ultrascaleplus CMT bel BUFGCTRL6
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.29
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.21
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.44
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.36
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.28
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.20

Bel BUFGCTRL7

ultrascaleplus CMT bel BUFGCTRL7
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.30
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.22
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.45
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.37
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.29
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.21

Bel BUFGCE_DIV0

ultrascaleplus CMT bel BUFGCE_DIV0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.41
RST_PRE_OPTINV	input	TCELL28:IMUX.IMUX.0

Bel BUFGCE_DIV1

ultrascaleplus CMT bel BUFGCE_DIV1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.42
RST_PRE_OPTINV	input	TCELL29:IMUX.IMUX.0

Bel BUFGCE_DIV2

ultrascaleplus CMT bel BUFGCE_DIV2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.43
RST_PRE_OPTINV	input	TCELL30:IMUX.IMUX.0

Bel BUFGCE_DIV3

ultrascaleplus CMT bel BUFGCE_DIV3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.44
RST_PRE_OPTINV	input	TCELL31:IMUX.IMUX.0

Bel PLL0

ultrascaleplus CMT bel PLL0
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL1:IMUX.IMUX.0
DADDR0	input	TCELL9:IMUX.BYP.0
DADDR1	input	TCELL9:IMUX.BYP.1
DADDR2	input	TCELL9:IMUX.BYP.2
DADDR3	input	TCELL9:IMUX.BYP.3
DADDR4	input	TCELL8:IMUX.BYP.0
DADDR5	input	TCELL8:IMUX.BYP.1
DADDR6	input	TCELL8:IMUX.BYP.2
DCLK	input	TCELL11:IMUX.CTRL.0
DEN	input	TCELL11:IMUX.IMUX.0
DI0	input	TCELL13:IMUX.BYP.0
DI1	input	TCELL13:IMUX.BYP.1
DI10	input	TCELL11:IMUX.BYP.2
DI11	input	TCELL11:IMUX.BYP.3
DI12	input	TCELL10:IMUX.BYP.0
DI13	input	TCELL10:IMUX.BYP.1
DI14	input	TCELL10:IMUX.BYP.2
DI15	input	TCELL10:IMUX.BYP.3
DI2	input	TCELL13:IMUX.BYP.2
DI3	input	TCELL13:IMUX.BYP.3
DI4	input	TCELL12:IMUX.BYP.0
DI5	input	TCELL12:IMUX.BYP.1
DI6	input	TCELL12:IMUX.BYP.2
DI7	input	TCELL12:IMUX.BYP.3
DI8	input	TCELL11:IMUX.BYP.0
DI9	input	TCELL11:IMUX.BYP.1
DOUT0	output	TCELL12:OUT.0
DOUT1	output	TCELL12:OUT.1
DOUT10	output	TCELL9:OUT.1
DOUT11	output	TCELL9:OUT.2
DOUT12	output	TCELL8:OUT.0
DOUT13	output	TCELL8:OUT.1
DOUT14	output	TCELL8:OUT.2
DOUT15	output	TCELL7:OUT.0
DOUT2	output	TCELL12:OUT.2
DOUT3	output	TCELL11:OUT.0
DOUT4	output	TCELL11:OUT.1
DOUT5	output	TCELL11:OUT.2
DOUT6	output	TCELL10:OUT.0
DOUT7	output	TCELL10:OUT.1
DOUT8	output	TCELL10:OUT.2
DOUT9	output	TCELL9:OUT.0
DRDY	output	TCELL13:OUT.1
DWE	input	TCELL10:IMUX.IMUX.0
LOCKED	output	TCELL13:OUT.0
PWRDWN	input	TCELL12:IMUX.IMUX.0
RST	input	TCELL13:IMUX.IMUX.0
SCANCLK	input	TCELL13:IMUX.CTRL.0
SCANENB	input	TCELL7:IMUX.IMUX.0
SCANIN	input	TCELL8:IMUX.IMUX.0
SCANMODEB	input	TCELL6:IMUX.IMUX.0
SCANOUT	output	TCELL13:OUT.2
TESTIN0	input	TCELL7:IMUX.BYP.0
TESTIN1	input	TCELL7:IMUX.BYP.1
TESTIN10	input	TCELL5:IMUX.BYP.2
TESTIN11	input	TCELL5:IMUX.BYP.3
TESTIN12	input	TCELL4:IMUX.BYP.0
TESTIN13	input	TCELL4:IMUX.BYP.1
TESTIN14	input	TCELL4:IMUX.BYP.2
TESTIN15	input	TCELL4:IMUX.BYP.3
TESTIN16	input	TCELL3:IMUX.BYP.0
TESTIN17	input	TCELL3:IMUX.BYP.1
TESTIN18	input	TCELL3:IMUX.BYP.2
TESTIN19	input	TCELL3:IMUX.BYP.3
TESTIN2	input	TCELL7:IMUX.BYP.2
TESTIN20	input	TCELL2:IMUX.BYP.0
TESTIN21	input	TCELL2:IMUX.BYP.1
TESTIN22	input	TCELL2:IMUX.BYP.2
TESTIN23	input	TCELL2:IMUX.BYP.3
TESTIN24	input	TCELL1:IMUX.BYP.0
TESTIN25	input	TCELL1:IMUX.BYP.1
TESTIN26	input	TCELL1:IMUX.BYP.2
TESTIN27	input	TCELL1:IMUX.BYP.3
TESTIN28	input	TCELL0:IMUX.BYP.0
TESTIN29	input	TCELL0:IMUX.BYP.1
TESTIN3	input	TCELL7:IMUX.BYP.3
TESTIN30	input	TCELL0:IMUX.BYP.2
TESTIN31	input	TCELL0:IMUX.BYP.3
TESTIN4	input	TCELL6:IMUX.BYP.0
TESTIN5	input	TCELL6:IMUX.BYP.1
TESTIN6	input	TCELL6:IMUX.BYP.2
TESTIN7	input	TCELL6:IMUX.BYP.3
TESTIN8	input	TCELL5:IMUX.BYP.0
TESTIN9	input	TCELL5:IMUX.BYP.1
TESTOUT0	output	TCELL7:OUT.1
TESTOUT1	output	TCELL7:OUT.2
TESTOUT10	output	TCELL4:OUT.2
TESTOUT11	output	TCELL3:OUT.0
TESTOUT12	output	TCELL3:OUT.1
TESTOUT13	output	TCELL3:OUT.2
TESTOUT14	output	TCELL2:OUT.0
TESTOUT15	output	TCELL2:OUT.1
TESTOUT2	output	TCELL6:OUT.0
TESTOUT3	output	TCELL6:OUT.1
TESTOUT4	output	TCELL6:OUT.2
TESTOUT5	output	TCELL5:OUT.0
TESTOUT6	output	TCELL5:OUT.1
TESTOUT7	output	TCELL5:OUT.2
TESTOUT8	output	TCELL4:OUT.0
TESTOUT9	output	TCELL4:OUT.1

Bel PLL1

ultrascaleplus CMT bel PLL1
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL15:IMUX.IMUX.0
DADDR0	input	TCELL23:IMUX.BYP.0
DADDR1	input	TCELL23:IMUX.BYP.1
DADDR2	input	TCELL23:IMUX.BYP.2
DADDR3	input	TCELL23:IMUX.BYP.3
DADDR4	input	TCELL22:IMUX.BYP.0
DADDR5	input	TCELL22:IMUX.BYP.1
DADDR6	input	TCELL22:IMUX.BYP.2
DCLK	input	TCELL25:IMUX.CTRL.0
DEN	input	TCELL25:IMUX.IMUX.0
DI0	input	TCELL27:IMUX.BYP.0
DI1	input	TCELL27:IMUX.BYP.1
DI10	input	TCELL25:IMUX.BYP.2
DI11	input	TCELL25:IMUX.BYP.3
DI12	input	TCELL24:IMUX.BYP.0
DI13	input	TCELL24:IMUX.BYP.1
DI14	input	TCELL24:IMUX.BYP.2
DI15	input	TCELL24:IMUX.BYP.3
DI2	input	TCELL27:IMUX.BYP.2
DI3	input	TCELL27:IMUX.BYP.3
DI4	input	TCELL26:IMUX.BYP.0
DI5	input	TCELL26:IMUX.BYP.1
DI6	input	TCELL26:IMUX.BYP.2
DI7	input	TCELL26:IMUX.BYP.3
DI8	input	TCELL25:IMUX.BYP.0
DI9	input	TCELL25:IMUX.BYP.1
DOUT0	output	TCELL26:OUT.0
DOUT1	output	TCELL26:OUT.1
DOUT10	output	TCELL23:OUT.1
DOUT11	output	TCELL23:OUT.2
DOUT12	output	TCELL22:OUT.0
DOUT13	output	TCELL22:OUT.1
DOUT14	output	TCELL22:OUT.2
DOUT15	output	TCELL21:OUT.0
DOUT2	output	TCELL26:OUT.2
DOUT3	output	TCELL25:OUT.0
DOUT4	output	TCELL25:OUT.1
DOUT5	output	TCELL25:OUT.2
DOUT6	output	TCELL24:OUT.0
DOUT7	output	TCELL24:OUT.1
DOUT8	output	TCELL24:OUT.2
DOUT9	output	TCELL23:OUT.0
DRDY	output	TCELL27:OUT.1
DWE	input	TCELL24:IMUX.IMUX.0
LOCKED	output	TCELL27:OUT.0
PWRDWN	input	TCELL26:IMUX.IMUX.0
RST	input	TCELL27:IMUX.IMUX.0
SCANCLK	input	TCELL27:IMUX.CTRL.0
SCANENB	input	TCELL21:IMUX.IMUX.0
SCANIN	input	TCELL22:IMUX.IMUX.0
SCANMODEB	input	TCELL20:IMUX.IMUX.0
SCANOUT	output	TCELL27:OUT.2
TESTIN0	input	TCELL21:IMUX.BYP.0
TESTIN1	input	TCELL21:IMUX.BYP.1
TESTIN10	input	TCELL19:IMUX.BYP.2
TESTIN11	input	TCELL19:IMUX.BYP.3
TESTIN12	input	TCELL18:IMUX.BYP.0
TESTIN13	input	TCELL18:IMUX.BYP.1
TESTIN14	input	TCELL18:IMUX.BYP.2
TESTIN15	input	TCELL18:IMUX.BYP.3
TESTIN16	input	TCELL17:IMUX.BYP.0
TESTIN17	input	TCELL17:IMUX.BYP.1
TESTIN18	input	TCELL17:IMUX.BYP.2
TESTIN19	input	TCELL17:IMUX.BYP.3
TESTIN2	input	TCELL21:IMUX.BYP.2
TESTIN20	input	TCELL16:IMUX.BYP.0
TESTIN21	input	TCELL16:IMUX.BYP.1
TESTIN22	input	TCELL16:IMUX.BYP.2
TESTIN23	input	TCELL16:IMUX.BYP.3
TESTIN24	input	TCELL15:IMUX.BYP.0
TESTIN25	input	TCELL15:IMUX.BYP.1
TESTIN26	input	TCELL15:IMUX.BYP.2
TESTIN27	input	TCELL15:IMUX.BYP.3
TESTIN28	input	TCELL14:IMUX.BYP.0
TESTIN29	input	TCELL14:IMUX.BYP.1
TESTIN3	input	TCELL21:IMUX.BYP.3
TESTIN30	input	TCELL14:IMUX.BYP.2
TESTIN31	input	TCELL14:IMUX.BYP.3
TESTIN4	input	TCELL20:IMUX.BYP.0
TESTIN5	input	TCELL20:IMUX.BYP.1
TESTIN6	input	TCELL20:IMUX.BYP.2
TESTIN7	input	TCELL20:IMUX.BYP.3
TESTIN8	input	TCELL19:IMUX.BYP.0
TESTIN9	input	TCELL19:IMUX.BYP.1
TESTOUT0	output	TCELL21:OUT.1
TESTOUT1	output	TCELL21:OUT.2
TESTOUT10	output	TCELL18:OUT.2
TESTOUT11	output	TCELL17:OUT.0
TESTOUT12	output	TCELL17:OUT.1
TESTOUT13	output	TCELL17:OUT.2
TESTOUT14	output	TCELL16:OUT.0
TESTOUT15	output	TCELL16:OUT.1
TESTOUT2	output	TCELL20:OUT.0
TESTOUT3	output	TCELL20:OUT.1
TESTOUT4	output	TCELL20:OUT.2
TESTOUT5	output	TCELL19:OUT.0
TESTOUT6	output	TCELL19:OUT.1
TESTOUT7	output	TCELL19:OUT.2
TESTOUT8	output	TCELL18:OUT.0
TESTOUT9	output	TCELL18:OUT.1

Bel MMCM

ultrascaleplus CMT bel MMCM
Pin	Direction	Wires
CDDCDONE	output	TCELL56:OUT.0
CDDCREQ	input	TCELL50:IMUX.IMUX.0
CLKFBSTOPPED	output	TCELL55:OUT.0
CLKINSEL	input	TCELL41:IMUX.IMUX.0
CLKINSTOPPED	output	TCELL55:OUT.1
DADDR0	input	TCELL50:IMUX.BYP.0
DADDR1	input	TCELL50:IMUX.BYP.1
DADDR2	input	TCELL50:IMUX.BYP.2
DADDR3	input	TCELL50:IMUX.BYP.3
DADDR4	input	TCELL49:IMUX.BYP.0
DADDR5	input	TCELL49:IMUX.BYP.1
DADDR6	input	TCELL49:IMUX.BYP.2
DCLK	input	TCELL52:IMUX.CTRL.0
DEN	input	TCELL52:IMUX.IMUX.0
DI0	input	TCELL54:IMUX.BYP.0
DI1	input	TCELL54:IMUX.BYP.1
DI10	input	TCELL52:IMUX.BYP.2
DI11	input	TCELL52:IMUX.BYP.3
DI12	input	TCELL51:IMUX.BYP.0
DI13	input	TCELL51:IMUX.BYP.1
DI14	input	TCELL51:IMUX.BYP.2
DI15	input	TCELL51:IMUX.BYP.3
DI2	input	TCELL54:IMUX.BYP.2
DI3	input	TCELL54:IMUX.BYP.3
DI4	input	TCELL53:IMUX.BYP.0
DI5	input	TCELL53:IMUX.BYP.1
DI6	input	TCELL53:IMUX.BYP.2
DI7	input	TCELL53:IMUX.BYP.3
DI8	input	TCELL52:IMUX.BYP.0
DI9	input	TCELL52:IMUX.BYP.1
DOUT0	output	TCELL53:OUT.0
DOUT1	output	TCELL53:OUT.1
DOUT10	output	TCELL50:OUT.1
DOUT11	output	TCELL50:OUT.2
DOUT12	output	TCELL49:OUT.0
DOUT13	output	TCELL49:OUT.1
DOUT14	output	TCELL49:OUT.2
DOUT15	output	TCELL48:OUT.0
DOUT2	output	TCELL53:OUT.2
DOUT3	output	TCELL52:OUT.0
DOUT4	output	TCELL52:OUT.1
DOUT5	output	TCELL52:OUT.2
DOUT6	output	TCELL51:OUT.0
DOUT7	output	TCELL51:OUT.1
DOUT8	output	TCELL51:OUT.2
DOUT9	output	TCELL50:OUT.0
DRDY	output	TCELL54:OUT.1
DWE	input	TCELL51:IMUX.IMUX.0
LOCKED	output	TCELL54:OUT.0
PSCLK	input	TCELL53:IMUX.CTRL.0
PSDONE	output	TCELL55:OUT.2
PSEN	input	TCELL56:IMUX.IMUX.0
PSINCDEC	input	TCELL55:IMUX.IMUX.0
PWRDWN	input	TCELL53:IMUX.IMUX.0
RST	input	TCELL54:IMUX.IMUX.0
SCANCLK	input	TCELL54:IMUX.CTRL.0
SCANENB	input	TCELL48:IMUX.IMUX.0
SCANIN	input	TCELL49:IMUX.IMUX.0
SCANMODEB	input	TCELL47:IMUX.IMUX.0
SCANOUT	output	TCELL54:OUT.2
TESTIN0	input	TCELL48:IMUX.BYP.0
TESTIN1	input	TCELL48:IMUX.BYP.1
TESTIN10	input	TCELL46:IMUX.BYP.2
TESTIN11	input	TCELL46:IMUX.BYP.3
TESTIN12	input	TCELL45:IMUX.BYP.0
TESTIN13	input	TCELL45:IMUX.BYP.1
TESTIN14	input	TCELL45:IMUX.BYP.2
TESTIN15	input	TCELL45:IMUX.BYP.3
TESTIN16	input	TCELL44:IMUX.BYP.0
TESTIN17	input	TCELL44:IMUX.BYP.1
TESTIN18	input	TCELL44:IMUX.BYP.2
TESTIN19	input	TCELL44:IMUX.BYP.3
TESTIN2	input	TCELL48:IMUX.BYP.2
TESTIN20	input	TCELL43:IMUX.BYP.0
TESTIN21	input	TCELL43:IMUX.BYP.1
TESTIN22	input	TCELL43:IMUX.BYP.2
TESTIN23	input	TCELL43:IMUX.BYP.3
TESTIN24	input	TCELL42:IMUX.BYP.0
TESTIN25	input	TCELL42:IMUX.BYP.1
TESTIN26	input	TCELL42:IMUX.BYP.2
TESTIN27	input	TCELL42:IMUX.BYP.3
TESTIN28	input	TCELL41:IMUX.BYP.0
TESTIN29	input	TCELL41:IMUX.BYP.1
TESTIN3	input	TCELL48:IMUX.BYP.3
TESTIN30	input	TCELL41:IMUX.BYP.2
TESTIN31	input	TCELL41:IMUX.BYP.3
TESTIN4	input	TCELL47:IMUX.BYP.0
TESTIN5	input	TCELL47:IMUX.BYP.1
TESTIN6	input	TCELL47:IMUX.BYP.2
TESTIN7	input	TCELL47:IMUX.BYP.3
TESTIN8	input	TCELL46:IMUX.BYP.0
TESTIN9	input	TCELL46:IMUX.BYP.1
TESTOUT0	output	TCELL48:OUT.1
TESTOUT1	output	TCELL48:OUT.2
TESTOUT10	output	TCELL45:OUT.2
TESTOUT11	output	TCELL44:OUT.0
TESTOUT12	output	TCELL44:OUT.1
TESTOUT13	output	TCELL44:OUT.2
TESTOUT14	output	TCELL43:OUT.0
TESTOUT15	output	TCELL43:OUT.1
TESTOUT2	output	TCELL47:OUT.0
TESTOUT3	output	TCELL47:OUT.1
TESTOUT4	output	TCELL47:OUT.2
TESTOUT5	output	TCELL46:OUT.0
TESTOUT6	output	TCELL46:OUT.1
TESTOUT7	output	TCELL46:OUT.2
TESTOUT8	output	TCELL45:OUT.0
TESTOUT9	output	TCELL45:OUT.1

Bel CMT

ultrascaleplus CMT bel CMT
Pin	Direction	Wires

Bel VCC_CMT

ultrascaleplus CMT bel VCC_CMT
Pin	Direction	Wires

Bel ABUS_SWITCH_CMT

ultrascaleplus CMT bel ABUS_SWITCH_CMT
Pin	Direction	Wires
TEST_ANALOGBUS_SEL_B	input	TCELL32:IMUX.IMUX.0

Bel wires

ultrascaleplus CMT bel wires
Wire	Pins
TCELL0:IMUX.BYP.0	PLL0.TESTIN28
TCELL0:IMUX.BYP.1	PLL0.TESTIN29
TCELL0:IMUX.BYP.2	PLL0.TESTIN30
TCELL0:IMUX.BYP.3	PLL0.TESTIN31
TCELL1:IMUX.BYP.0	PLL0.TESTIN24
TCELL1:IMUX.BYP.1	PLL0.TESTIN25
TCELL1:IMUX.BYP.2	PLL0.TESTIN26
TCELL1:IMUX.BYP.3	PLL0.TESTIN27
TCELL1:IMUX.IMUX.0	PLL0.CLKOUTPHY_EN
TCELL2:OUT.0	PLL0.TESTOUT14
TCELL2:OUT.1	PLL0.TESTOUT15
TCELL2:IMUX.BYP.0	PLL0.TESTIN20
TCELL2:IMUX.BYP.1	PLL0.TESTIN21
TCELL2:IMUX.BYP.2	PLL0.TESTIN22
TCELL2:IMUX.BYP.3	PLL0.TESTIN23
TCELL3:OUT.0	PLL0.TESTOUT11
TCELL3:OUT.1	PLL0.TESTOUT12
TCELL3:OUT.2	PLL0.TESTOUT13
TCELL3:IMUX.BYP.0	PLL0.TESTIN16
TCELL3:IMUX.BYP.1	PLL0.TESTIN17
TCELL3:IMUX.BYP.2	PLL0.TESTIN18
TCELL3:IMUX.BYP.3	PLL0.TESTIN19
TCELL4:OUT.0	PLL0.TESTOUT8
TCELL4:OUT.1	PLL0.TESTOUT9
TCELL4:OUT.2	PLL0.TESTOUT10
TCELL4:IMUX.BYP.0	PLL0.TESTIN12
TCELL4:IMUX.BYP.1	PLL0.TESTIN13
TCELL4:IMUX.BYP.2	PLL0.TESTIN14
TCELL4:IMUX.BYP.3	PLL0.TESTIN15
TCELL5:OUT.0	PLL0.TESTOUT5
TCELL5:OUT.1	PLL0.TESTOUT6
TCELL5:OUT.2	PLL0.TESTOUT7
TCELL5:IMUX.BYP.0	PLL0.TESTIN8
TCELL5:IMUX.BYP.1	PLL0.TESTIN9
TCELL5:IMUX.BYP.2	PLL0.TESTIN10
TCELL5:IMUX.BYP.3	PLL0.TESTIN11
TCELL6:OUT.0	PLL0.TESTOUT2
TCELL6:OUT.1	PLL0.TESTOUT3
TCELL6:OUT.2	PLL0.TESTOUT4
TCELL6:IMUX.BYP.0	PLL0.TESTIN4
TCELL6:IMUX.BYP.1	PLL0.TESTIN5
TCELL6:IMUX.BYP.2	PLL0.TESTIN6
TCELL6:IMUX.BYP.3	PLL0.TESTIN7
TCELL6:IMUX.IMUX.0	PLL0.SCANMODEB
TCELL7:OUT.0	PLL0.DOUT15
TCELL7:OUT.1	PLL0.TESTOUT0
TCELL7:OUT.2	PLL0.TESTOUT1
TCELL7:IMUX.BYP.0	PLL0.TESTIN0
TCELL7:IMUX.BYP.1	PLL0.TESTIN1
TCELL7:IMUX.BYP.2	PLL0.TESTIN2
TCELL7:IMUX.BYP.3	PLL0.TESTIN3
TCELL7:IMUX.IMUX.0	PLL0.SCANENB
TCELL8:OUT.0	PLL0.DOUT12
TCELL8:OUT.1	PLL0.DOUT13
TCELL8:OUT.2	PLL0.DOUT14
TCELL8:IMUX.BYP.0	PLL0.DADDR4
TCELL8:IMUX.BYP.1	PLL0.DADDR5
TCELL8:IMUX.BYP.2	PLL0.DADDR6
TCELL8:IMUX.IMUX.0	PLL0.SCANIN
TCELL9:OUT.0	PLL0.DOUT9
TCELL9:OUT.1	PLL0.DOUT10
TCELL9:OUT.2	PLL0.DOUT11
TCELL9:IMUX.BYP.0	PLL0.DADDR0
TCELL9:IMUX.BYP.1	PLL0.DADDR1
TCELL9:IMUX.BYP.2	PLL0.DADDR2
TCELL9:IMUX.BYP.3	PLL0.DADDR3
TCELL10:OUT.0	PLL0.DOUT6
TCELL10:OUT.1	PLL0.DOUT7
TCELL10:OUT.2	PLL0.DOUT8
TCELL10:IMUX.BYP.0	PLL0.DI12
TCELL10:IMUX.BYP.1	PLL0.DI13
TCELL10:IMUX.BYP.2	PLL0.DI14
TCELL10:IMUX.BYP.3	PLL0.DI15
TCELL10:IMUX.IMUX.0	PLL0.DWE
TCELL11:OUT.0	PLL0.DOUT3
TCELL11:OUT.1	PLL0.DOUT4
TCELL11:OUT.2	PLL0.DOUT5
TCELL11:IMUX.CTRL.0	PLL0.DCLK
TCELL11:IMUX.BYP.0	PLL0.DI8
TCELL11:IMUX.BYP.1	PLL0.DI9
TCELL11:IMUX.BYP.2	PLL0.DI10
TCELL11:IMUX.BYP.3	PLL0.DI11
TCELL11:IMUX.IMUX.0	PLL0.DEN
TCELL12:OUT.0	PLL0.DOUT0
TCELL12:OUT.1	PLL0.DOUT1
TCELL12:OUT.2	PLL0.DOUT2
TCELL12:IMUX.BYP.0	PLL0.DI4
TCELL12:IMUX.BYP.1	PLL0.DI5
TCELL12:IMUX.BYP.2	PLL0.DI6
TCELL12:IMUX.BYP.3	PLL0.DI7
TCELL12:IMUX.IMUX.0	PLL0.PWRDWN
TCELL13:OUT.0	PLL0.LOCKED
TCELL13:OUT.1	PLL0.DRDY
TCELL13:OUT.2	PLL0.SCANOUT
TCELL13:IMUX.CTRL.0	PLL0.SCANCLK
TCELL13:IMUX.BYP.0	PLL0.DI0
TCELL13:IMUX.BYP.1	PLL0.DI1
TCELL13:IMUX.BYP.2	PLL0.DI2
TCELL13:IMUX.BYP.3	PLL0.DI3
TCELL13:IMUX.IMUX.0	PLL0.RST
TCELL14:IMUX.BYP.0	PLL1.TESTIN28
TCELL14:IMUX.BYP.1	PLL1.TESTIN29
TCELL14:IMUX.BYP.2	PLL1.TESTIN30
TCELL14:IMUX.BYP.3	PLL1.TESTIN31
TCELL15:IMUX.BYP.0	PLL1.TESTIN24
TCELL15:IMUX.BYP.1	PLL1.TESTIN25
TCELL15:IMUX.BYP.2	PLL1.TESTIN26
TCELL15:IMUX.BYP.3	PLL1.TESTIN27
TCELL15:IMUX.IMUX.0	PLL1.CLKOUTPHY_EN
TCELL16:OUT.0	PLL1.TESTOUT14
TCELL16:OUT.1	PLL1.TESTOUT15
TCELL16:IMUX.BYP.0	PLL1.TESTIN20
TCELL16:IMUX.BYP.1	PLL1.TESTIN21
TCELL16:IMUX.BYP.2	PLL1.TESTIN22
TCELL16:IMUX.BYP.3	PLL1.TESTIN23
TCELL17:OUT.0	PLL1.TESTOUT11
TCELL17:OUT.1	PLL1.TESTOUT12
TCELL17:OUT.2	PLL1.TESTOUT13
TCELL17:IMUX.BYP.0	PLL1.TESTIN16
TCELL17:IMUX.BYP.1	PLL1.TESTIN17
TCELL17:IMUX.BYP.2	PLL1.TESTIN18
TCELL17:IMUX.BYP.3	PLL1.TESTIN19
TCELL18:OUT.0	PLL1.TESTOUT8
TCELL18:OUT.1	PLL1.TESTOUT9
TCELL18:OUT.2	PLL1.TESTOUT10
TCELL18:IMUX.BYP.0	PLL1.TESTIN12
TCELL18:IMUX.BYP.1	PLL1.TESTIN13
TCELL18:IMUX.BYP.2	PLL1.TESTIN14
TCELL18:IMUX.BYP.3	PLL1.TESTIN15
TCELL19:OUT.0	PLL1.TESTOUT5
TCELL19:OUT.1	PLL1.TESTOUT6
TCELL19:OUT.2	PLL1.TESTOUT7
TCELL19:IMUX.BYP.0	PLL1.TESTIN8
TCELL19:IMUX.BYP.1	PLL1.TESTIN9
TCELL19:IMUX.BYP.2	PLL1.TESTIN10
TCELL19:IMUX.BYP.3	PLL1.TESTIN11
TCELL20:OUT.0	PLL1.TESTOUT2
TCELL20:OUT.1	PLL1.TESTOUT3
TCELL20:OUT.2	PLL1.TESTOUT4
TCELL20:IMUX.BYP.0	PLL1.TESTIN4
TCELL20:IMUX.BYP.1	PLL1.TESTIN5
TCELL20:IMUX.BYP.2	PLL1.TESTIN6
TCELL20:IMUX.BYP.3	PLL1.TESTIN7
TCELL20:IMUX.IMUX.0	PLL1.SCANMODEB
TCELL21:OUT.0	PLL1.DOUT15
TCELL21:OUT.1	PLL1.TESTOUT0
TCELL21:OUT.2	PLL1.TESTOUT1
TCELL21:IMUX.BYP.0	PLL1.TESTIN0
TCELL21:IMUX.BYP.1	PLL1.TESTIN1
TCELL21:IMUX.BYP.2	PLL1.TESTIN2
TCELL21:IMUX.BYP.3	PLL1.TESTIN3
TCELL21:IMUX.IMUX.0	PLL1.SCANENB
TCELL22:OUT.0	PLL1.DOUT12
TCELL22:OUT.1	PLL1.DOUT13
TCELL22:OUT.2	PLL1.DOUT14
TCELL22:IMUX.BYP.0	PLL1.DADDR4
TCELL22:IMUX.BYP.1	PLL1.DADDR5
TCELL22:IMUX.BYP.2	PLL1.DADDR6
TCELL22:IMUX.IMUX.0	PLL1.SCANIN
TCELL23:OUT.0	PLL1.DOUT9
TCELL23:OUT.1	PLL1.DOUT10
TCELL23:OUT.2	PLL1.DOUT11
TCELL23:IMUX.BYP.0	PLL1.DADDR0
TCELL23:IMUX.BYP.1	PLL1.DADDR1
TCELL23:IMUX.BYP.2	PLL1.DADDR2
TCELL23:IMUX.BYP.3	PLL1.DADDR3
TCELL24:OUT.0	PLL1.DOUT6
TCELL24:OUT.1	PLL1.DOUT7
TCELL24:OUT.2	PLL1.DOUT8
TCELL24:IMUX.BYP.0	PLL1.DI12
TCELL24:IMUX.BYP.1	PLL1.DI13
TCELL24:IMUX.BYP.2	PLL1.DI14
TCELL24:IMUX.BYP.3	PLL1.DI15
TCELL24:IMUX.IMUX.0	PLL1.DWE
TCELL25:OUT.0	PLL1.DOUT3
TCELL25:OUT.1	PLL1.DOUT4
TCELL25:OUT.2	PLL1.DOUT5
TCELL25:IMUX.CTRL.0	PLL1.DCLK
TCELL25:IMUX.BYP.0	PLL1.DI8
TCELL25:IMUX.BYP.1	PLL1.DI9
TCELL25:IMUX.BYP.2	PLL1.DI10
TCELL25:IMUX.BYP.3	PLL1.DI11
TCELL25:IMUX.IMUX.0	PLL1.DEN
TCELL26:OUT.0	PLL1.DOUT0
TCELL26:OUT.1	PLL1.DOUT1
TCELL26:OUT.2	PLL1.DOUT2
TCELL26:IMUX.BYP.0	PLL1.DI4
TCELL26:IMUX.BYP.1	PLL1.DI5
TCELL26:IMUX.BYP.2	PLL1.DI6
TCELL26:IMUX.BYP.3	PLL1.DI7
TCELL26:IMUX.IMUX.0	PLL1.PWRDWN
TCELL27:OUT.0	PLL1.LOCKED
TCELL27:OUT.1	PLL1.DRDY
TCELL27:OUT.2	PLL1.SCANOUT
TCELL27:IMUX.CTRL.0	PLL1.SCANCLK
TCELL27:IMUX.BYP.0	PLL1.DI0
TCELL27:IMUX.BYP.1	PLL1.DI1
TCELL27:IMUX.BYP.2	PLL1.DI2
TCELL27:IMUX.BYP.3	PLL1.DI3
TCELL27:IMUX.IMUX.0	PLL1.RST
TCELL28:IMUX.IMUX.0	BUFGCE_DIV0.RST_PRE_OPTINV
TCELL28:IMUX.IMUX.17	BUFCE_ROW_CMT0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.18	BUFCE_ROW_CMT1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.19	BUFCE_ROW_CMT2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.20	BUFCE_ROW_CMT3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.21	BUFCE_ROW_CMT4.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.22	BUFCE_ROW_CMT5.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.23	BUFCE_ROW_CMT6.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.24	BUFCE_ROW_CMT7.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.25	BUFCE_ROW_CMT8.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.26	BUFCE_ROW_CMT9.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.27	BUFCE_ROW_CMT10.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.28	BUFCE_ROW_CMT11.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.29	BUFCE_ROW_CMT12.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.30	BUFCE_ROW_CMT13.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.31	BUFCE_ROW_CMT14.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.32	BUFCE_ROW_CMT15.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.33	BUFCE_ROW_CMT16.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.34	BUFCE_ROW_CMT17.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.35	BUFCE_ROW_CMT18.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.36	BUFCE_ROW_CMT19.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.37	BUFCE_ROW_CMT20.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.38	BUFCE_ROW_CMT21.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.39	BUFCE_ROW_CMT22.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.40	BUFCE_ROW_CMT23.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.41	BUFGCE_DIV0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.42	BUFGCE_DIV1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.43	BUFGCE_DIV2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.44	BUFGCE_DIV3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.45	BUFGCTRL0.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.46	BUFGCTRL1.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.47	BUFGCTRL2.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.0	BUFGCE_DIV1.RST_PRE_OPTINV
TCELL29:IMUX.IMUX.17	BUFGCTRL3.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.18	BUFGCTRL4.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.19	BUFGCTRL5.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.20	BUFGCTRL6.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.21	BUFGCTRL7.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.22	BUFGCTRL0.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.23	BUFGCTRL1.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.24	BUFGCTRL2.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.25	BUFGCTRL3.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.26	BUFGCTRL4.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.27	BUFGCTRL5.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.28	BUFGCTRL6.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.29	BUFGCTRL7.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.30	BUFGCTRL0.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.31	BUFGCTRL1.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.32	BUFGCTRL2.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.33	BUFGCTRL3.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.34	BUFGCTRL4.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.35	BUFGCTRL5.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.36	BUFGCTRL6.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.37	BUFGCTRL7.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.38	BUFGCTRL0.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.39	BUFGCTRL1.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.40	BUFGCTRL2.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.41	BUFGCTRL3.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.42	BUFGCTRL4.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.43	BUFGCTRL5.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.44	BUFGCTRL6.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.45	BUFGCTRL7.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.46	BUFGCTRL0.CE1_PRE_OPTINV
TCELL29:IMUX.IMUX.47	BUFGCTRL1.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.0	BUFGCE_DIV2.RST_PRE_OPTINV
TCELL30:IMUX.IMUX.17	BUFGCTRL2.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.18	BUFGCTRL3.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.19	BUFGCTRL4.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.20	BUFGCTRL5.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.21	BUFGCTRL6.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.22	BUFGCTRL7.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.23	BUFGCTRL0.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.24	BUFGCTRL1.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.25	BUFGCTRL2.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.26	BUFGCTRL3.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.27	BUFGCTRL4.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.28	BUFGCTRL5.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.29	BUFGCTRL6.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.30	BUFGCTRL7.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.31	BUFGCE0.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.32	BUFGCE1.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.33	BUFGCE2.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.34	BUFGCE3.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.35	BUFGCE4.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.36	BUFGCE5.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.37	BUFGCE6.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.38	BUFGCE7.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.39	BUFGCE8.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.40	BUFGCE9.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.41	BUFGCE10.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.42	BUFGCE11.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.43	BUFGCE12.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.44	BUFGCE13.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.45	BUFGCE14.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.46	BUFGCE15.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.47	BUFGCE16.CE_PRE_OPTINV
TCELL30:RCLK.IMUX.16	BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.17	BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.18	BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.19	BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.20	BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2
TCELL30:RCLK.IMUX.21	BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2
TCELL31:IMUX.IMUX.0	BUFGCE_DIV3.RST_PRE_OPTINV
TCELL31:IMUX.IMUX.17	BUFGCE17.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.18	BUFGCE18.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.19	BUFGCE19.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.20	BUFGCE20.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.21	BUFGCE21.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.22	BUFGCE22.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.23	BUFGCE23.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.24	BUFGCE0.CLK_IN_CKINT
TCELL31:IMUX.IMUX.25	BUFGCE1.CLK_IN_CKINT
TCELL31:IMUX.IMUX.26	BUFGCE2.CLK_IN_CKINT
TCELL31:IMUX.IMUX.27	BUFGCE3.CLK_IN_CKINT
TCELL31:IMUX.IMUX.28	BUFGCE4.CLK_IN_CKINT
TCELL31:IMUX.IMUX.29	BUFGCE5.CLK_IN_CKINT
TCELL31:IMUX.IMUX.30	BUFGCE6.CLK_IN_CKINT
TCELL31:IMUX.IMUX.31	BUFGCE7.CLK_IN_CKINT
TCELL31:IMUX.IMUX.32	BUFGCE8.CLK_IN_CKINT
TCELL31:IMUX.IMUX.33	BUFGCE9.CLK_IN_CKINT
TCELL31:IMUX.IMUX.34	BUFGCE10.CLK_IN_CKINT
TCELL31:IMUX.IMUX.35	BUFGCE11.CLK_IN_CKINT
TCELL31:IMUX.IMUX.36	BUFGCE12.CLK_IN_CKINT
TCELL31:IMUX.IMUX.37	BUFGCE13.CLK_IN_CKINT
TCELL31:IMUX.IMUX.38	BUFGCE14.CLK_IN_CKINT
TCELL31:IMUX.IMUX.39	BUFGCE15.CLK_IN_CKINT
TCELL31:IMUX.IMUX.40	BUFGCE16.CLK_IN_CKINT
TCELL31:IMUX.IMUX.41	BUFGCE17.CLK_IN_CKINT
TCELL31:IMUX.IMUX.42	BUFGCE18.CLK_IN_CKINT
TCELL31:IMUX.IMUX.43	BUFGCE19.CLK_IN_CKINT
TCELL31:IMUX.IMUX.44	BUFGCE20.CLK_IN_CKINT
TCELL31:IMUX.IMUX.45	BUFGCE21.CLK_IN_CKINT
TCELL31:IMUX.IMUX.46	BUFGCE22.CLK_IN_CKINT
TCELL31:IMUX.IMUX.47	BUFGCE23.CLK_IN_CKINT
TCELL32:IMUX.IMUX.0	ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B
TCELL41:IMUX.BYP.0	MMCM.TESTIN28
TCELL41:IMUX.BYP.1	MMCM.TESTIN29
TCELL41:IMUX.BYP.2	MMCM.TESTIN30
TCELL41:IMUX.BYP.3	MMCM.TESTIN31
TCELL41:IMUX.IMUX.0	MMCM.CLKINSEL
TCELL42:IMUX.BYP.0	MMCM.TESTIN24
TCELL42:IMUX.BYP.1	MMCM.TESTIN25
TCELL42:IMUX.BYP.2	MMCM.TESTIN26
TCELL42:IMUX.BYP.3	MMCM.TESTIN27
TCELL43:OUT.0	MMCM.TESTOUT14
TCELL43:OUT.1	MMCM.TESTOUT15
TCELL43:IMUX.BYP.0	MMCM.TESTIN20
TCELL43:IMUX.BYP.1	MMCM.TESTIN21
TCELL43:IMUX.BYP.2	MMCM.TESTIN22
TCELL43:IMUX.BYP.3	MMCM.TESTIN23
TCELL44:OUT.0	MMCM.TESTOUT11
TCELL44:OUT.1	MMCM.TESTOUT12
TCELL44:OUT.2	MMCM.TESTOUT13
TCELL44:IMUX.BYP.0	MMCM.TESTIN16
TCELL44:IMUX.BYP.1	MMCM.TESTIN17
TCELL44:IMUX.BYP.2	MMCM.TESTIN18
TCELL44:IMUX.BYP.3	MMCM.TESTIN19
TCELL45:OUT.0	MMCM.TESTOUT8
TCELL45:OUT.1	MMCM.TESTOUT9
TCELL45:OUT.2	MMCM.TESTOUT10
TCELL45:IMUX.BYP.0	MMCM.TESTIN12
TCELL45:IMUX.BYP.1	MMCM.TESTIN13
TCELL45:IMUX.BYP.2	MMCM.TESTIN14
TCELL45:IMUX.BYP.3	MMCM.TESTIN15
TCELL46:OUT.0	MMCM.TESTOUT5
TCELL46:OUT.1	MMCM.TESTOUT6
TCELL46:OUT.2	MMCM.TESTOUT7
TCELL46:IMUX.BYP.0	MMCM.TESTIN8
TCELL46:IMUX.BYP.1	MMCM.TESTIN9
TCELL46:IMUX.BYP.2	MMCM.TESTIN10
TCELL46:IMUX.BYP.3	MMCM.TESTIN11
TCELL47:OUT.0	MMCM.TESTOUT2
TCELL47:OUT.1	MMCM.TESTOUT3
TCELL47:OUT.2	MMCM.TESTOUT4
TCELL47:IMUX.BYP.0	MMCM.TESTIN4
TCELL47:IMUX.BYP.1	MMCM.TESTIN5
TCELL47:IMUX.BYP.2	MMCM.TESTIN6
TCELL47:IMUX.BYP.3	MMCM.TESTIN7
TCELL47:IMUX.IMUX.0	MMCM.SCANMODEB
TCELL48:OUT.0	MMCM.DOUT15
TCELL48:OUT.1	MMCM.TESTOUT0
TCELL48:OUT.2	MMCM.TESTOUT1
TCELL48:IMUX.BYP.0	MMCM.TESTIN0
TCELL48:IMUX.BYP.1	MMCM.TESTIN1
TCELL48:IMUX.BYP.2	MMCM.TESTIN2
TCELL48:IMUX.BYP.3	MMCM.TESTIN3
TCELL48:IMUX.IMUX.0	MMCM.SCANENB
TCELL49:OUT.0	MMCM.DOUT12
TCELL49:OUT.1	MMCM.DOUT13
TCELL49:OUT.2	MMCM.DOUT14
TCELL49:IMUX.BYP.0	MMCM.DADDR4
TCELL49:IMUX.BYP.1	MMCM.DADDR5
TCELL49:IMUX.BYP.2	MMCM.DADDR6
TCELL49:IMUX.IMUX.0	MMCM.SCANIN
TCELL50:OUT.0	MMCM.DOUT9
TCELL50:OUT.1	MMCM.DOUT10
TCELL50:OUT.2	MMCM.DOUT11
TCELL50:IMUX.BYP.0	MMCM.DADDR0
TCELL50:IMUX.BYP.1	MMCM.DADDR1
TCELL50:IMUX.BYP.2	MMCM.DADDR2
TCELL50:IMUX.BYP.3	MMCM.DADDR3
TCELL50:IMUX.IMUX.0	MMCM.CDDCREQ
TCELL51:OUT.0	MMCM.DOUT6
TCELL51:OUT.1	MMCM.DOUT7
TCELL51:OUT.2	MMCM.DOUT8
TCELL51:IMUX.BYP.0	MMCM.DI12
TCELL51:IMUX.BYP.1	MMCM.DI13
TCELL51:IMUX.BYP.2	MMCM.DI14
TCELL51:IMUX.BYP.3	MMCM.DI15
TCELL51:IMUX.IMUX.0	MMCM.DWE
TCELL52:OUT.0	MMCM.DOUT3
TCELL52:OUT.1	MMCM.DOUT4
TCELL52:OUT.2	MMCM.DOUT5
TCELL52:IMUX.CTRL.0	MMCM.DCLK
TCELL52:IMUX.BYP.0	MMCM.DI8
TCELL52:IMUX.BYP.1	MMCM.DI9
TCELL52:IMUX.BYP.2	MMCM.DI10
TCELL52:IMUX.BYP.3	MMCM.DI11
TCELL52:IMUX.IMUX.0	MMCM.DEN
TCELL53:OUT.0	MMCM.DOUT0
TCELL53:OUT.1	MMCM.DOUT1
TCELL53:OUT.2	MMCM.DOUT2
TCELL53:IMUX.CTRL.0	MMCM.PSCLK
TCELL53:IMUX.BYP.0	MMCM.DI4
TCELL53:IMUX.BYP.1	MMCM.DI5
TCELL53:IMUX.BYP.2	MMCM.DI6
TCELL53:IMUX.BYP.3	MMCM.DI7
TCELL53:IMUX.IMUX.0	MMCM.PWRDWN
TCELL54:OUT.0	MMCM.LOCKED
TCELL54:OUT.1	MMCM.DRDY
TCELL54:OUT.2	MMCM.SCANOUT
TCELL54:IMUX.CTRL.0	MMCM.SCANCLK
TCELL54:IMUX.BYP.0	MMCM.DI0
TCELL54:IMUX.BYP.1	MMCM.DI1
TCELL54:IMUX.BYP.2	MMCM.DI2
TCELL54:IMUX.BYP.3	MMCM.DI3
TCELL54:IMUX.IMUX.0	MMCM.RST
TCELL55:OUT.0	MMCM.CLKFBSTOPPED
TCELL55:OUT.1	MMCM.CLKINSTOPPED
TCELL55:OUT.2	MMCM.PSDONE
TCELL55:IMUX.IMUX.0	MMCM.PSINCDEC
TCELL56:OUT.0	MMCM.CDDCDONE
TCELL56:IMUX.IMUX.0	MMCM.PSEN

Tile CMT_HBM

Cells: 60 IRIs: 0

Bel BUFCE_ROW_CMT0

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.17
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT1

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.18
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT2

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.19
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT3

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.20
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT4

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.21
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT5

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.22
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT6

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.23
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT7

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.24
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT8

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.25
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT9

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.26
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT10

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.27
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT11

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.28
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT12

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.29
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT13

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.30
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT14

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.31
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT15

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.32
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT16

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.33
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT17

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.34
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT18

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.35
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT19

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.36
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT20

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.37
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT21

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.38
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT22

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.39
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT23

ultrascaleplus CMT_HBM bel BUFCE_ROW_CMT23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.40
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel GCLK_TEST_BUF_CMT0

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT1

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT1
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT2

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT2
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT3

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT3
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT4

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT4
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT5

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT5
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT6

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT6
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT7

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT7
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT8

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT8
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT9

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT9
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT10

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT10
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT11

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT11
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT12

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT12
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT13

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT13
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT14

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT14
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT15

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT15
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT16

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT16
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT17

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT17
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT18

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT18
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT19

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT19
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT20

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT20
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT21

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT21
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT22

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT22
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT23

ultrascaleplus CMT_HBM bel GCLK_TEST_BUF_CMT23
Pin	Direction	Wires

Bel BUFGCE0

ultrascaleplus CMT_HBM bel BUFGCE0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.31
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.24

Bel BUFGCE1

ultrascaleplus CMT_HBM bel BUFGCE1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.32
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.25

Bel BUFGCE2

ultrascaleplus CMT_HBM bel BUFGCE2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.33
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.26

Bel BUFGCE3

ultrascaleplus CMT_HBM bel BUFGCE3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.34
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.27

Bel BUFGCE4

ultrascaleplus CMT_HBM bel BUFGCE4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.35
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.28

Bel BUFGCE5

ultrascaleplus CMT_HBM bel BUFGCE5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.36
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.29

Bel BUFGCE6

ultrascaleplus CMT_HBM bel BUFGCE6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.37
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.30

Bel BUFGCE7

ultrascaleplus CMT_HBM bel BUFGCE7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.38
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.31

Bel BUFGCE8

ultrascaleplus CMT_HBM bel BUFGCE8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.39
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.32

Bel BUFGCE9

ultrascaleplus CMT_HBM bel BUFGCE9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.40
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.33

Bel BUFGCE10

ultrascaleplus CMT_HBM bel BUFGCE10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.41
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.34

Bel BUFGCE11

ultrascaleplus CMT_HBM bel BUFGCE11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.42
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.35

Bel BUFGCE12

ultrascaleplus CMT_HBM bel BUFGCE12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.43
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.36

Bel BUFGCE13

ultrascaleplus CMT_HBM bel BUFGCE13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.44
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.37

Bel BUFGCE14

ultrascaleplus CMT_HBM bel BUFGCE14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.45
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.38

Bel BUFGCE15

ultrascaleplus CMT_HBM bel BUFGCE15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.46
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.39

Bel BUFGCE16

ultrascaleplus CMT_HBM bel BUFGCE16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.47
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.40

Bel BUFGCE17

ultrascaleplus CMT_HBM bel BUFGCE17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.17
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.41

Bel BUFGCE18

ultrascaleplus CMT_HBM bel BUFGCE18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.18
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.42

Bel BUFGCE19

ultrascaleplus CMT_HBM bel BUFGCE19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.19
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.43

Bel BUFGCE20

ultrascaleplus CMT_HBM bel BUFGCE20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.20
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.44

Bel BUFGCE21

ultrascaleplus CMT_HBM bel BUFGCE21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.21
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.45

Bel BUFGCE22

ultrascaleplus CMT_HBM bel BUFGCE22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.22
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.46

Bel BUFGCE23

ultrascaleplus CMT_HBM bel BUFGCE23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.23
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.47

Bel BUFGCTRL0

ultrascaleplus CMT_HBM bel BUFGCTRL0
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.23
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.46
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.38
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.30
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.22
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.45

Bel BUFGCTRL1

ultrascaleplus CMT_HBM bel BUFGCTRL1
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.24
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.47
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.39
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.31
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.23
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.46

Bel BUFGCTRL2

ultrascaleplus CMT_HBM bel BUFGCTRL2
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.25
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.17
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.40
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.32
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.24
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.47

Bel BUFGCTRL3

ultrascaleplus CMT_HBM bel BUFGCTRL3
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.26
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.18
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.41
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.33
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.25
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.17

Bel BUFGCTRL4

ultrascaleplus CMT_HBM bel BUFGCTRL4
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.27
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.19
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.42
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.34
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.26
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.18

Bel BUFGCTRL5

ultrascaleplus CMT_HBM bel BUFGCTRL5
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.28
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.20
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.43
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.35
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.27
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.19

Bel BUFGCTRL6

ultrascaleplus CMT_HBM bel BUFGCTRL6
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.29
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.21
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.44
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.36
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.28
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.20

Bel BUFGCTRL7

ultrascaleplus CMT_HBM bel BUFGCTRL7
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.30
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.22
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.45
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.37
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.29
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.21

Bel BUFGCE_DIV0

ultrascaleplus CMT_HBM bel BUFGCE_DIV0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.41
RST_PRE_OPTINV	input	TCELL28:IMUX.IMUX.0

Bel BUFGCE_DIV1

ultrascaleplus CMT_HBM bel BUFGCE_DIV1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.42
RST_PRE_OPTINV	input	TCELL29:IMUX.IMUX.0

Bel BUFGCE_DIV2

ultrascaleplus CMT_HBM bel BUFGCE_DIV2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.43
RST_PRE_OPTINV	input	TCELL30:IMUX.IMUX.0

Bel BUFGCE_DIV3

ultrascaleplus CMT_HBM bel BUFGCE_DIV3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.44
RST_PRE_OPTINV	input	TCELL31:IMUX.IMUX.0

Bel PLL0

ultrascaleplus CMT_HBM bel PLL0
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL1:IMUX.IMUX.0
DADDR0	input	TCELL9:IMUX.BYP.0
DADDR1	input	TCELL9:IMUX.BYP.1
DADDR2	input	TCELL9:IMUX.BYP.2
DADDR3	input	TCELL9:IMUX.BYP.3
DADDR4	input	TCELL8:IMUX.BYP.0
DADDR5	input	TCELL8:IMUX.BYP.1
DADDR6	input	TCELL8:IMUX.BYP.2
DCLK	input	TCELL11:IMUX.CTRL.0
DEN	input	TCELL11:IMUX.IMUX.0
DI0	input	TCELL13:IMUX.BYP.0
DI1	input	TCELL13:IMUX.BYP.1
DI10	input	TCELL11:IMUX.BYP.2
DI11	input	TCELL11:IMUX.BYP.3
DI12	input	TCELL10:IMUX.BYP.0
DI13	input	TCELL10:IMUX.BYP.1
DI14	input	TCELL10:IMUX.BYP.2
DI15	input	TCELL10:IMUX.BYP.3
DI2	input	TCELL13:IMUX.BYP.2
DI3	input	TCELL13:IMUX.BYP.3
DI4	input	TCELL12:IMUX.BYP.0
DI5	input	TCELL12:IMUX.BYP.1
DI6	input	TCELL12:IMUX.BYP.2
DI7	input	TCELL12:IMUX.BYP.3
DI8	input	TCELL11:IMUX.BYP.0
DI9	input	TCELL11:IMUX.BYP.1
DOUT0	output	TCELL12:OUT.0
DOUT1	output	TCELL12:OUT.1
DOUT10	output	TCELL9:OUT.1
DOUT11	output	TCELL9:OUT.2
DOUT12	output	TCELL8:OUT.0
DOUT13	output	TCELL8:OUT.1
DOUT14	output	TCELL8:OUT.2
DOUT15	output	TCELL7:OUT.0
DOUT2	output	TCELL12:OUT.2
DOUT3	output	TCELL11:OUT.0
DOUT4	output	TCELL11:OUT.1
DOUT5	output	TCELL11:OUT.2
DOUT6	output	TCELL10:OUT.0
DOUT7	output	TCELL10:OUT.1
DOUT8	output	TCELL10:OUT.2
DOUT9	output	TCELL9:OUT.0
DRDY	output	TCELL13:OUT.1
DWE	input	TCELL10:IMUX.IMUX.0
LOCKED	output	TCELL13:OUT.0
PWRDWN	input	TCELL12:IMUX.IMUX.0
RST	input	TCELL13:IMUX.IMUX.0
SCANCLK	input	TCELL13:IMUX.CTRL.0
SCANENB	input	TCELL7:IMUX.IMUX.0
SCANIN	input	TCELL8:IMUX.IMUX.0
SCANMODEB	input	TCELL6:IMUX.IMUX.0
SCANOUT	output	TCELL13:OUT.2
TESTIN0	input	TCELL7:IMUX.BYP.0
TESTIN1	input	TCELL7:IMUX.BYP.1
TESTIN10	input	TCELL5:IMUX.BYP.2
TESTIN11	input	TCELL5:IMUX.BYP.3
TESTIN12	input	TCELL4:IMUX.BYP.0
TESTIN13	input	TCELL4:IMUX.BYP.1
TESTIN14	input	TCELL4:IMUX.BYP.2
TESTIN15	input	TCELL4:IMUX.BYP.3
TESTIN16	input	TCELL3:IMUX.BYP.0
TESTIN17	input	TCELL3:IMUX.BYP.1
TESTIN18	input	TCELL3:IMUX.BYP.2
TESTIN19	input	TCELL3:IMUX.BYP.3
TESTIN2	input	TCELL7:IMUX.BYP.2
TESTIN20	input	TCELL2:IMUX.BYP.0
TESTIN21	input	TCELL2:IMUX.BYP.1
TESTIN22	input	TCELL2:IMUX.BYP.2
TESTIN23	input	TCELL2:IMUX.BYP.3
TESTIN24	input	TCELL1:IMUX.BYP.0
TESTIN25	input	TCELL1:IMUX.BYP.1
TESTIN26	input	TCELL1:IMUX.BYP.2
TESTIN27	input	TCELL1:IMUX.BYP.3
TESTIN28	input	TCELL0:IMUX.BYP.0
TESTIN29	input	TCELL0:IMUX.BYP.1
TESTIN3	input	TCELL7:IMUX.BYP.3
TESTIN30	input	TCELL0:IMUX.BYP.2
TESTIN31	input	TCELL0:IMUX.BYP.3
TESTIN4	input	TCELL6:IMUX.BYP.0
TESTIN5	input	TCELL6:IMUX.BYP.1
TESTIN6	input	TCELL6:IMUX.BYP.2
TESTIN7	input	TCELL6:IMUX.BYP.3
TESTIN8	input	TCELL5:IMUX.BYP.0
TESTIN9	input	TCELL5:IMUX.BYP.1
TESTOUT0	output	TCELL7:OUT.1
TESTOUT1	output	TCELL7:OUT.2
TESTOUT10	output	TCELL4:OUT.2
TESTOUT11	output	TCELL3:OUT.0
TESTOUT12	output	TCELL3:OUT.1
TESTOUT13	output	TCELL3:OUT.2
TESTOUT14	output	TCELL2:OUT.0
TESTOUT15	output	TCELL2:OUT.1
TESTOUT2	output	TCELL6:OUT.0
TESTOUT3	output	TCELL6:OUT.1
TESTOUT4	output	TCELL6:OUT.2
TESTOUT5	output	TCELL5:OUT.0
TESTOUT6	output	TCELL5:OUT.1
TESTOUT7	output	TCELL5:OUT.2
TESTOUT8	output	TCELL4:OUT.0
TESTOUT9	output	TCELL4:OUT.1

Bel PLL1

ultrascaleplus CMT_HBM bel PLL1
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL15:IMUX.IMUX.0
DADDR0	input	TCELL23:IMUX.BYP.0
DADDR1	input	TCELL23:IMUX.BYP.1
DADDR2	input	TCELL23:IMUX.BYP.2
DADDR3	input	TCELL23:IMUX.BYP.3
DADDR4	input	TCELL22:IMUX.BYP.0
DADDR5	input	TCELL22:IMUX.BYP.1
DADDR6	input	TCELL22:IMUX.BYP.2
DCLK	input	TCELL25:IMUX.CTRL.0
DEN	input	TCELL25:IMUX.IMUX.0
DI0	input	TCELL27:IMUX.BYP.0
DI1	input	TCELL27:IMUX.BYP.1
DI10	input	TCELL25:IMUX.BYP.2
DI11	input	TCELL25:IMUX.BYP.3
DI12	input	TCELL24:IMUX.BYP.0
DI13	input	TCELL24:IMUX.BYP.1
DI14	input	TCELL24:IMUX.BYP.2
DI15	input	TCELL24:IMUX.BYP.3
DI2	input	TCELL27:IMUX.BYP.2
DI3	input	TCELL27:IMUX.BYP.3
DI4	input	TCELL26:IMUX.BYP.0
DI5	input	TCELL26:IMUX.BYP.1
DI6	input	TCELL26:IMUX.BYP.2
DI7	input	TCELL26:IMUX.BYP.3
DI8	input	TCELL25:IMUX.BYP.0
DI9	input	TCELL25:IMUX.BYP.1
DOUT0	output	TCELL26:OUT.0
DOUT1	output	TCELL26:OUT.1
DOUT10	output	TCELL23:OUT.1
DOUT11	output	TCELL23:OUT.2
DOUT12	output	TCELL22:OUT.0
DOUT13	output	TCELL22:OUT.1
DOUT14	output	TCELL22:OUT.2
DOUT15	output	TCELL21:OUT.0
DOUT2	output	TCELL26:OUT.2
DOUT3	output	TCELL25:OUT.0
DOUT4	output	TCELL25:OUT.1
DOUT5	output	TCELL25:OUT.2
DOUT6	output	TCELL24:OUT.0
DOUT7	output	TCELL24:OUT.1
DOUT8	output	TCELL24:OUT.2
DOUT9	output	TCELL23:OUT.0
DRDY	output	TCELL27:OUT.1
DWE	input	TCELL24:IMUX.IMUX.0
LOCKED	output	TCELL27:OUT.0
PWRDWN	input	TCELL26:IMUX.IMUX.0
RST	input	TCELL27:IMUX.IMUX.0
SCANCLK	input	TCELL27:IMUX.CTRL.0
SCANENB	input	TCELL21:IMUX.IMUX.0
SCANIN	input	TCELL22:IMUX.IMUX.0
SCANMODEB	input	TCELL20:IMUX.IMUX.0
SCANOUT	output	TCELL27:OUT.2
TESTIN0	input	TCELL21:IMUX.BYP.0
TESTIN1	input	TCELL21:IMUX.BYP.1
TESTIN10	input	TCELL19:IMUX.BYP.2
TESTIN11	input	TCELL19:IMUX.BYP.3
TESTIN12	input	TCELL18:IMUX.BYP.0
TESTIN13	input	TCELL18:IMUX.BYP.1
TESTIN14	input	TCELL18:IMUX.BYP.2
TESTIN15	input	TCELL18:IMUX.BYP.3
TESTIN16	input	TCELL17:IMUX.BYP.0
TESTIN17	input	TCELL17:IMUX.BYP.1
TESTIN18	input	TCELL17:IMUX.BYP.2
TESTIN19	input	TCELL17:IMUX.BYP.3
TESTIN2	input	TCELL21:IMUX.BYP.2
TESTIN20	input	TCELL16:IMUX.BYP.0
TESTIN21	input	TCELL16:IMUX.BYP.1
TESTIN22	input	TCELL16:IMUX.BYP.2
TESTIN23	input	TCELL16:IMUX.BYP.3
TESTIN24	input	TCELL15:IMUX.BYP.0
TESTIN25	input	TCELL15:IMUX.BYP.1
TESTIN26	input	TCELL15:IMUX.BYP.2
TESTIN27	input	TCELL15:IMUX.BYP.3
TESTIN28	input	TCELL14:IMUX.BYP.0
TESTIN29	input	TCELL14:IMUX.BYP.1
TESTIN3	input	TCELL21:IMUX.BYP.3
TESTIN30	input	TCELL14:IMUX.BYP.2
TESTIN31	input	TCELL14:IMUX.BYP.3
TESTIN4	input	TCELL20:IMUX.BYP.0
TESTIN5	input	TCELL20:IMUX.BYP.1
TESTIN6	input	TCELL20:IMUX.BYP.2
TESTIN7	input	TCELL20:IMUX.BYP.3
TESTIN8	input	TCELL19:IMUX.BYP.0
TESTIN9	input	TCELL19:IMUX.BYP.1
TESTOUT0	output	TCELL21:OUT.1
TESTOUT1	output	TCELL21:OUT.2
TESTOUT10	output	TCELL18:OUT.2
TESTOUT11	output	TCELL17:OUT.0
TESTOUT12	output	TCELL17:OUT.1
TESTOUT13	output	TCELL17:OUT.2
TESTOUT14	output	TCELL16:OUT.0
TESTOUT15	output	TCELL16:OUT.1
TESTOUT2	output	TCELL20:OUT.0
TESTOUT3	output	TCELL20:OUT.1
TESTOUT4	output	TCELL20:OUT.2
TESTOUT5	output	TCELL19:OUT.0
TESTOUT6	output	TCELL19:OUT.1
TESTOUT7	output	TCELL19:OUT.2
TESTOUT8	output	TCELL18:OUT.0
TESTOUT9	output	TCELL18:OUT.1

Bel MMCM

ultrascaleplus CMT_HBM bel MMCM
Pin	Direction	Wires
CDDCDONE	output	TCELL56:OUT.0
CDDCREQ	input	TCELL50:IMUX.IMUX.0
CLKFBSTOPPED	output	TCELL55:OUT.0
CLKINSEL	input	TCELL41:IMUX.IMUX.0
CLKINSTOPPED	output	TCELL55:OUT.1
DADDR0	input	TCELL50:IMUX.BYP.0
DADDR1	input	TCELL50:IMUX.BYP.1
DADDR2	input	TCELL50:IMUX.BYP.2
DADDR3	input	TCELL50:IMUX.BYP.3
DADDR4	input	TCELL49:IMUX.BYP.0
DADDR5	input	TCELL49:IMUX.BYP.1
DADDR6	input	TCELL49:IMUX.BYP.2
DCLK	input	TCELL52:IMUX.CTRL.0
DEN	input	TCELL52:IMUX.IMUX.0
DI0	input	TCELL54:IMUX.BYP.0
DI1	input	TCELL54:IMUX.BYP.1
DI10	input	TCELL52:IMUX.BYP.2
DI11	input	TCELL52:IMUX.BYP.3
DI12	input	TCELL51:IMUX.BYP.0
DI13	input	TCELL51:IMUX.BYP.1
DI14	input	TCELL51:IMUX.BYP.2
DI15	input	TCELL51:IMUX.BYP.3
DI2	input	TCELL54:IMUX.BYP.2
DI3	input	TCELL54:IMUX.BYP.3
DI4	input	TCELL53:IMUX.BYP.0
DI5	input	TCELL53:IMUX.BYP.1
DI6	input	TCELL53:IMUX.BYP.2
DI7	input	TCELL53:IMUX.BYP.3
DI8	input	TCELL52:IMUX.BYP.0
DI9	input	TCELL52:IMUX.BYP.1
DOUT0	output	TCELL53:OUT.0
DOUT1	output	TCELL53:OUT.1
DOUT10	output	TCELL50:OUT.1
DOUT11	output	TCELL50:OUT.2
DOUT12	output	TCELL49:OUT.0
DOUT13	output	TCELL49:OUT.1
DOUT14	output	TCELL49:OUT.2
DOUT15	output	TCELL48:OUT.0
DOUT2	output	TCELL53:OUT.2
DOUT3	output	TCELL52:OUT.0
DOUT4	output	TCELL52:OUT.1
DOUT5	output	TCELL52:OUT.2
DOUT6	output	TCELL51:OUT.0
DOUT7	output	TCELL51:OUT.1
DOUT8	output	TCELL51:OUT.2
DOUT9	output	TCELL50:OUT.0
DRDY	output	TCELL54:OUT.1
DWE	input	TCELL51:IMUX.IMUX.0
LOCKED	output	TCELL54:OUT.0
PSCLK	input	TCELL53:IMUX.CTRL.0
PSDONE	output	TCELL55:OUT.2
PSEN	input	TCELL56:IMUX.IMUX.0
PSINCDEC	input	TCELL55:IMUX.IMUX.0
PWRDWN	input	TCELL53:IMUX.IMUX.0
RST	input	TCELL54:IMUX.IMUX.0
SCANCLK	input	TCELL54:IMUX.CTRL.0
SCANENB	input	TCELL48:IMUX.IMUX.0
SCANIN	input	TCELL49:IMUX.IMUX.0
SCANMODEB	input	TCELL47:IMUX.IMUX.0
SCANOUT	output	TCELL54:OUT.2
TESTIN0	input	TCELL48:IMUX.BYP.0
TESTIN1	input	TCELL48:IMUX.BYP.1
TESTIN10	input	TCELL46:IMUX.BYP.2
TESTIN11	input	TCELL46:IMUX.BYP.3
TESTIN12	input	TCELL45:IMUX.BYP.0
TESTIN13	input	TCELL45:IMUX.BYP.1
TESTIN14	input	TCELL45:IMUX.BYP.2
TESTIN15	input	TCELL45:IMUX.BYP.3
TESTIN16	input	TCELL44:IMUX.BYP.0
TESTIN17	input	TCELL44:IMUX.BYP.1
TESTIN18	input	TCELL44:IMUX.BYP.2
TESTIN19	input	TCELL44:IMUX.BYP.3
TESTIN2	input	TCELL48:IMUX.BYP.2
TESTIN20	input	TCELL43:IMUX.BYP.0
TESTIN21	input	TCELL43:IMUX.BYP.1
TESTIN22	input	TCELL43:IMUX.BYP.2
TESTIN23	input	TCELL43:IMUX.BYP.3
TESTIN24	input	TCELL42:IMUX.BYP.0
TESTIN25	input	TCELL42:IMUX.BYP.1
TESTIN26	input	TCELL42:IMUX.BYP.2
TESTIN27	input	TCELL42:IMUX.BYP.3
TESTIN28	input	TCELL41:IMUX.BYP.0
TESTIN29	input	TCELL41:IMUX.BYP.1
TESTIN3	input	TCELL48:IMUX.BYP.3
TESTIN30	input	TCELL41:IMUX.BYP.2
TESTIN31	input	TCELL41:IMUX.BYP.3
TESTIN4	input	TCELL47:IMUX.BYP.0
TESTIN5	input	TCELL47:IMUX.BYP.1
TESTIN6	input	TCELL47:IMUX.BYP.2
TESTIN7	input	TCELL47:IMUX.BYP.3
TESTIN8	input	TCELL46:IMUX.BYP.0
TESTIN9	input	TCELL46:IMUX.BYP.1
TESTOUT0	output	TCELL48:OUT.1
TESTOUT1	output	TCELL48:OUT.2
TESTOUT10	output	TCELL45:OUT.2
TESTOUT11	output	TCELL44:OUT.0
TESTOUT12	output	TCELL44:OUT.1
TESTOUT13	output	TCELL44:OUT.2
TESTOUT14	output	TCELL43:OUT.0
TESTOUT15	output	TCELL43:OUT.1
TESTOUT2	output	TCELL47:OUT.0
TESTOUT3	output	TCELL47:OUT.1
TESTOUT4	output	TCELL47:OUT.2
TESTOUT5	output	TCELL46:OUT.0
TESTOUT6	output	TCELL46:OUT.1
TESTOUT7	output	TCELL46:OUT.2
TESTOUT8	output	TCELL45:OUT.0
TESTOUT9	output	TCELL45:OUT.1

Bel CMT

ultrascaleplus CMT_HBM bel CMT
Pin	Direction	Wires

Bel VCC_CMT

ultrascaleplus CMT_HBM bel VCC_CMT
Pin	Direction	Wires

Bel ABUS_SWITCH_CMT

ultrascaleplus CMT_HBM bel ABUS_SWITCH_CMT
Pin	Direction	Wires
TEST_ANALOGBUS_SEL_B	input	TCELL32:IMUX.IMUX.0

Bel HBM_REF_CLK0

ultrascaleplus CMT_HBM bel HBM_REF_CLK0
Pin	Direction	Wires

Bel HBM_REF_CLK1

ultrascaleplus CMT_HBM bel HBM_REF_CLK1
Pin	Direction	Wires

Bel wires

ultrascaleplus CMT_HBM bel wires
Wire	Pins
TCELL0:IMUX.BYP.0	PLL0.TESTIN28
TCELL0:IMUX.BYP.1	PLL0.TESTIN29
TCELL0:IMUX.BYP.2	PLL0.TESTIN30
TCELL0:IMUX.BYP.3	PLL0.TESTIN31
TCELL1:IMUX.BYP.0	PLL0.TESTIN24
TCELL1:IMUX.BYP.1	PLL0.TESTIN25
TCELL1:IMUX.BYP.2	PLL0.TESTIN26
TCELL1:IMUX.BYP.3	PLL0.TESTIN27
TCELL1:IMUX.IMUX.0	PLL0.CLKOUTPHY_EN
TCELL2:OUT.0	PLL0.TESTOUT14
TCELL2:OUT.1	PLL0.TESTOUT15
TCELL2:IMUX.BYP.0	PLL0.TESTIN20
TCELL2:IMUX.BYP.1	PLL0.TESTIN21
TCELL2:IMUX.BYP.2	PLL0.TESTIN22
TCELL2:IMUX.BYP.3	PLL0.TESTIN23
TCELL3:OUT.0	PLL0.TESTOUT11
TCELL3:OUT.1	PLL0.TESTOUT12
TCELL3:OUT.2	PLL0.TESTOUT13
TCELL3:IMUX.BYP.0	PLL0.TESTIN16
TCELL3:IMUX.BYP.1	PLL0.TESTIN17
TCELL3:IMUX.BYP.2	PLL0.TESTIN18
TCELL3:IMUX.BYP.3	PLL0.TESTIN19
TCELL4:OUT.0	PLL0.TESTOUT8
TCELL4:OUT.1	PLL0.TESTOUT9
TCELL4:OUT.2	PLL0.TESTOUT10
TCELL4:IMUX.BYP.0	PLL0.TESTIN12
TCELL4:IMUX.BYP.1	PLL0.TESTIN13
TCELL4:IMUX.BYP.2	PLL0.TESTIN14
TCELL4:IMUX.BYP.3	PLL0.TESTIN15
TCELL5:OUT.0	PLL0.TESTOUT5
TCELL5:OUT.1	PLL0.TESTOUT6
TCELL5:OUT.2	PLL0.TESTOUT7
TCELL5:IMUX.BYP.0	PLL0.TESTIN8
TCELL5:IMUX.BYP.1	PLL0.TESTIN9
TCELL5:IMUX.BYP.2	PLL0.TESTIN10
TCELL5:IMUX.BYP.3	PLL0.TESTIN11
TCELL6:OUT.0	PLL0.TESTOUT2
TCELL6:OUT.1	PLL0.TESTOUT3
TCELL6:OUT.2	PLL0.TESTOUT4
TCELL6:IMUX.BYP.0	PLL0.TESTIN4
TCELL6:IMUX.BYP.1	PLL0.TESTIN5
TCELL6:IMUX.BYP.2	PLL0.TESTIN6
TCELL6:IMUX.BYP.3	PLL0.TESTIN7
TCELL6:IMUX.IMUX.0	PLL0.SCANMODEB
TCELL7:OUT.0	PLL0.DOUT15
TCELL7:OUT.1	PLL0.TESTOUT0
TCELL7:OUT.2	PLL0.TESTOUT1
TCELL7:IMUX.BYP.0	PLL0.TESTIN0
TCELL7:IMUX.BYP.1	PLL0.TESTIN1
TCELL7:IMUX.BYP.2	PLL0.TESTIN2
TCELL7:IMUX.BYP.3	PLL0.TESTIN3
TCELL7:IMUX.IMUX.0	PLL0.SCANENB
TCELL8:OUT.0	PLL0.DOUT12
TCELL8:OUT.1	PLL0.DOUT13
TCELL8:OUT.2	PLL0.DOUT14
TCELL8:IMUX.BYP.0	PLL0.DADDR4
TCELL8:IMUX.BYP.1	PLL0.DADDR5
TCELL8:IMUX.BYP.2	PLL0.DADDR6
TCELL8:IMUX.IMUX.0	PLL0.SCANIN
TCELL9:OUT.0	PLL0.DOUT9
TCELL9:OUT.1	PLL0.DOUT10
TCELL9:OUT.2	PLL0.DOUT11
TCELL9:IMUX.BYP.0	PLL0.DADDR0
TCELL9:IMUX.BYP.1	PLL0.DADDR1
TCELL9:IMUX.BYP.2	PLL0.DADDR2
TCELL9:IMUX.BYP.3	PLL0.DADDR3
TCELL10:OUT.0	PLL0.DOUT6
TCELL10:OUT.1	PLL0.DOUT7
TCELL10:OUT.2	PLL0.DOUT8
TCELL10:IMUX.BYP.0	PLL0.DI12
TCELL10:IMUX.BYP.1	PLL0.DI13
TCELL10:IMUX.BYP.2	PLL0.DI14
TCELL10:IMUX.BYP.3	PLL0.DI15
TCELL10:IMUX.IMUX.0	PLL0.DWE
TCELL11:OUT.0	PLL0.DOUT3
TCELL11:OUT.1	PLL0.DOUT4
TCELL11:OUT.2	PLL0.DOUT5
TCELL11:IMUX.CTRL.0	PLL0.DCLK
TCELL11:IMUX.BYP.0	PLL0.DI8
TCELL11:IMUX.BYP.1	PLL0.DI9
TCELL11:IMUX.BYP.2	PLL0.DI10
TCELL11:IMUX.BYP.3	PLL0.DI11
TCELL11:IMUX.IMUX.0	PLL0.DEN
TCELL12:OUT.0	PLL0.DOUT0
TCELL12:OUT.1	PLL0.DOUT1
TCELL12:OUT.2	PLL0.DOUT2
TCELL12:IMUX.BYP.0	PLL0.DI4
TCELL12:IMUX.BYP.1	PLL0.DI5
TCELL12:IMUX.BYP.2	PLL0.DI6
TCELL12:IMUX.BYP.3	PLL0.DI7
TCELL12:IMUX.IMUX.0	PLL0.PWRDWN
TCELL13:OUT.0	PLL0.LOCKED
TCELL13:OUT.1	PLL0.DRDY
TCELL13:OUT.2	PLL0.SCANOUT
TCELL13:IMUX.CTRL.0	PLL0.SCANCLK
TCELL13:IMUX.BYP.0	PLL0.DI0
TCELL13:IMUX.BYP.1	PLL0.DI1
TCELL13:IMUX.BYP.2	PLL0.DI2
TCELL13:IMUX.BYP.3	PLL0.DI3
TCELL13:IMUX.IMUX.0	PLL0.RST
TCELL14:IMUX.BYP.0	PLL1.TESTIN28
TCELL14:IMUX.BYP.1	PLL1.TESTIN29
TCELL14:IMUX.BYP.2	PLL1.TESTIN30
TCELL14:IMUX.BYP.3	PLL1.TESTIN31
TCELL15:IMUX.BYP.0	PLL1.TESTIN24
TCELL15:IMUX.BYP.1	PLL1.TESTIN25
TCELL15:IMUX.BYP.2	PLL1.TESTIN26
TCELL15:IMUX.BYP.3	PLL1.TESTIN27
TCELL15:IMUX.IMUX.0	PLL1.CLKOUTPHY_EN
TCELL16:OUT.0	PLL1.TESTOUT14
TCELL16:OUT.1	PLL1.TESTOUT15
TCELL16:IMUX.BYP.0	PLL1.TESTIN20
TCELL16:IMUX.BYP.1	PLL1.TESTIN21
TCELL16:IMUX.BYP.2	PLL1.TESTIN22
TCELL16:IMUX.BYP.3	PLL1.TESTIN23
TCELL17:OUT.0	PLL1.TESTOUT11
TCELL17:OUT.1	PLL1.TESTOUT12
TCELL17:OUT.2	PLL1.TESTOUT13
TCELL17:IMUX.BYP.0	PLL1.TESTIN16
TCELL17:IMUX.BYP.1	PLL1.TESTIN17
TCELL17:IMUX.BYP.2	PLL1.TESTIN18
TCELL17:IMUX.BYP.3	PLL1.TESTIN19
TCELL18:OUT.0	PLL1.TESTOUT8
TCELL18:OUT.1	PLL1.TESTOUT9
TCELL18:OUT.2	PLL1.TESTOUT10
TCELL18:IMUX.BYP.0	PLL1.TESTIN12
TCELL18:IMUX.BYP.1	PLL1.TESTIN13
TCELL18:IMUX.BYP.2	PLL1.TESTIN14
TCELL18:IMUX.BYP.3	PLL1.TESTIN15
TCELL19:OUT.0	PLL1.TESTOUT5
TCELL19:OUT.1	PLL1.TESTOUT6
TCELL19:OUT.2	PLL1.TESTOUT7
TCELL19:IMUX.BYP.0	PLL1.TESTIN8
TCELL19:IMUX.BYP.1	PLL1.TESTIN9
TCELL19:IMUX.BYP.2	PLL1.TESTIN10
TCELL19:IMUX.BYP.3	PLL1.TESTIN11
TCELL20:OUT.0	PLL1.TESTOUT2
TCELL20:OUT.1	PLL1.TESTOUT3
TCELL20:OUT.2	PLL1.TESTOUT4
TCELL20:IMUX.BYP.0	PLL1.TESTIN4
TCELL20:IMUX.BYP.1	PLL1.TESTIN5
TCELL20:IMUX.BYP.2	PLL1.TESTIN6
TCELL20:IMUX.BYP.3	PLL1.TESTIN7
TCELL20:IMUX.IMUX.0	PLL1.SCANMODEB
TCELL21:OUT.0	PLL1.DOUT15
TCELL21:OUT.1	PLL1.TESTOUT0
TCELL21:OUT.2	PLL1.TESTOUT1
TCELL21:IMUX.BYP.0	PLL1.TESTIN0
TCELL21:IMUX.BYP.1	PLL1.TESTIN1
TCELL21:IMUX.BYP.2	PLL1.TESTIN2
TCELL21:IMUX.BYP.3	PLL1.TESTIN3
TCELL21:IMUX.IMUX.0	PLL1.SCANENB
TCELL22:OUT.0	PLL1.DOUT12
TCELL22:OUT.1	PLL1.DOUT13
TCELL22:OUT.2	PLL1.DOUT14
TCELL22:IMUX.BYP.0	PLL1.DADDR4
TCELL22:IMUX.BYP.1	PLL1.DADDR5
TCELL22:IMUX.BYP.2	PLL1.DADDR6
TCELL22:IMUX.IMUX.0	PLL1.SCANIN
TCELL23:OUT.0	PLL1.DOUT9
TCELL23:OUT.1	PLL1.DOUT10
TCELL23:OUT.2	PLL1.DOUT11
TCELL23:IMUX.BYP.0	PLL1.DADDR0
TCELL23:IMUX.BYP.1	PLL1.DADDR1
TCELL23:IMUX.BYP.2	PLL1.DADDR2
TCELL23:IMUX.BYP.3	PLL1.DADDR3
TCELL24:OUT.0	PLL1.DOUT6
TCELL24:OUT.1	PLL1.DOUT7
TCELL24:OUT.2	PLL1.DOUT8
TCELL24:IMUX.BYP.0	PLL1.DI12
TCELL24:IMUX.BYP.1	PLL1.DI13
TCELL24:IMUX.BYP.2	PLL1.DI14
TCELL24:IMUX.BYP.3	PLL1.DI15
TCELL24:IMUX.IMUX.0	PLL1.DWE
TCELL25:OUT.0	PLL1.DOUT3
TCELL25:OUT.1	PLL1.DOUT4
TCELL25:OUT.2	PLL1.DOUT5
TCELL25:IMUX.CTRL.0	PLL1.DCLK
TCELL25:IMUX.BYP.0	PLL1.DI8
TCELL25:IMUX.BYP.1	PLL1.DI9
TCELL25:IMUX.BYP.2	PLL1.DI10
TCELL25:IMUX.BYP.3	PLL1.DI11
TCELL25:IMUX.IMUX.0	PLL1.DEN
TCELL26:OUT.0	PLL1.DOUT0
TCELL26:OUT.1	PLL1.DOUT1
TCELL26:OUT.2	PLL1.DOUT2
TCELL26:IMUX.BYP.0	PLL1.DI4
TCELL26:IMUX.BYP.1	PLL1.DI5
TCELL26:IMUX.BYP.2	PLL1.DI6
TCELL26:IMUX.BYP.3	PLL1.DI7
TCELL26:IMUX.IMUX.0	PLL1.PWRDWN
TCELL27:OUT.0	PLL1.LOCKED
TCELL27:OUT.1	PLL1.DRDY
TCELL27:OUT.2	PLL1.SCANOUT
TCELL27:IMUX.CTRL.0	PLL1.SCANCLK
TCELL27:IMUX.BYP.0	PLL1.DI0
TCELL27:IMUX.BYP.1	PLL1.DI1
TCELL27:IMUX.BYP.2	PLL1.DI2
TCELL27:IMUX.BYP.3	PLL1.DI3
TCELL27:IMUX.IMUX.0	PLL1.RST
TCELL28:IMUX.IMUX.0	BUFGCE_DIV0.RST_PRE_OPTINV
TCELL28:IMUX.IMUX.17	BUFCE_ROW_CMT0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.18	BUFCE_ROW_CMT1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.19	BUFCE_ROW_CMT2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.20	BUFCE_ROW_CMT3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.21	BUFCE_ROW_CMT4.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.22	BUFCE_ROW_CMT5.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.23	BUFCE_ROW_CMT6.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.24	BUFCE_ROW_CMT7.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.25	BUFCE_ROW_CMT8.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.26	BUFCE_ROW_CMT9.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.27	BUFCE_ROW_CMT10.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.28	BUFCE_ROW_CMT11.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.29	BUFCE_ROW_CMT12.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.30	BUFCE_ROW_CMT13.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.31	BUFCE_ROW_CMT14.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.32	BUFCE_ROW_CMT15.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.33	BUFCE_ROW_CMT16.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.34	BUFCE_ROW_CMT17.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.35	BUFCE_ROW_CMT18.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.36	BUFCE_ROW_CMT19.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.37	BUFCE_ROW_CMT20.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.38	BUFCE_ROW_CMT21.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.39	BUFCE_ROW_CMT22.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.40	BUFCE_ROW_CMT23.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.41	BUFGCE_DIV0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.42	BUFGCE_DIV1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.43	BUFGCE_DIV2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.44	BUFGCE_DIV3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.45	BUFGCTRL0.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.46	BUFGCTRL1.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.47	BUFGCTRL2.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.0	BUFGCE_DIV1.RST_PRE_OPTINV
TCELL29:IMUX.IMUX.17	BUFGCTRL3.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.18	BUFGCTRL4.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.19	BUFGCTRL5.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.20	BUFGCTRL6.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.21	BUFGCTRL7.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.22	BUFGCTRL0.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.23	BUFGCTRL1.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.24	BUFGCTRL2.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.25	BUFGCTRL3.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.26	BUFGCTRL4.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.27	BUFGCTRL5.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.28	BUFGCTRL6.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.29	BUFGCTRL7.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.30	BUFGCTRL0.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.31	BUFGCTRL1.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.32	BUFGCTRL2.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.33	BUFGCTRL3.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.34	BUFGCTRL4.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.35	BUFGCTRL5.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.36	BUFGCTRL6.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.37	BUFGCTRL7.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.38	BUFGCTRL0.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.39	BUFGCTRL1.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.40	BUFGCTRL2.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.41	BUFGCTRL3.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.42	BUFGCTRL4.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.43	BUFGCTRL5.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.44	BUFGCTRL6.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.45	BUFGCTRL7.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.46	BUFGCTRL0.CE1_PRE_OPTINV
TCELL29:IMUX.IMUX.47	BUFGCTRL1.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.0	BUFGCE_DIV2.RST_PRE_OPTINV
TCELL30:IMUX.IMUX.17	BUFGCTRL2.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.18	BUFGCTRL3.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.19	BUFGCTRL4.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.20	BUFGCTRL5.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.21	BUFGCTRL6.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.22	BUFGCTRL7.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.23	BUFGCTRL0.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.24	BUFGCTRL1.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.25	BUFGCTRL2.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.26	BUFGCTRL3.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.27	BUFGCTRL4.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.28	BUFGCTRL5.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.29	BUFGCTRL6.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.30	BUFGCTRL7.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.31	BUFGCE0.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.32	BUFGCE1.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.33	BUFGCE2.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.34	BUFGCE3.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.35	BUFGCE4.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.36	BUFGCE5.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.37	BUFGCE6.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.38	BUFGCE7.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.39	BUFGCE8.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.40	BUFGCE9.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.41	BUFGCE10.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.42	BUFGCE11.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.43	BUFGCE12.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.44	BUFGCE13.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.45	BUFGCE14.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.46	BUFGCE15.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.47	BUFGCE16.CE_PRE_OPTINV
TCELL30:RCLK.IMUX.16	BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.17	BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.18	BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.19	BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.20	BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2
TCELL30:RCLK.IMUX.21	BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2
TCELL31:IMUX.IMUX.0	BUFGCE_DIV3.RST_PRE_OPTINV
TCELL31:IMUX.IMUX.17	BUFGCE17.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.18	BUFGCE18.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.19	BUFGCE19.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.20	BUFGCE20.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.21	BUFGCE21.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.22	BUFGCE22.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.23	BUFGCE23.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.24	BUFGCE0.CLK_IN_CKINT
TCELL31:IMUX.IMUX.25	BUFGCE1.CLK_IN_CKINT
TCELL31:IMUX.IMUX.26	BUFGCE2.CLK_IN_CKINT
TCELL31:IMUX.IMUX.27	BUFGCE3.CLK_IN_CKINT
TCELL31:IMUX.IMUX.28	BUFGCE4.CLK_IN_CKINT
TCELL31:IMUX.IMUX.29	BUFGCE5.CLK_IN_CKINT
TCELL31:IMUX.IMUX.30	BUFGCE6.CLK_IN_CKINT
TCELL31:IMUX.IMUX.31	BUFGCE7.CLK_IN_CKINT
TCELL31:IMUX.IMUX.32	BUFGCE8.CLK_IN_CKINT
TCELL31:IMUX.IMUX.33	BUFGCE9.CLK_IN_CKINT
TCELL31:IMUX.IMUX.34	BUFGCE10.CLK_IN_CKINT
TCELL31:IMUX.IMUX.35	BUFGCE11.CLK_IN_CKINT
TCELL31:IMUX.IMUX.36	BUFGCE12.CLK_IN_CKINT
TCELL31:IMUX.IMUX.37	BUFGCE13.CLK_IN_CKINT
TCELL31:IMUX.IMUX.38	BUFGCE14.CLK_IN_CKINT
TCELL31:IMUX.IMUX.39	BUFGCE15.CLK_IN_CKINT
TCELL31:IMUX.IMUX.40	BUFGCE16.CLK_IN_CKINT
TCELL31:IMUX.IMUX.41	BUFGCE17.CLK_IN_CKINT
TCELL31:IMUX.IMUX.42	BUFGCE18.CLK_IN_CKINT
TCELL31:IMUX.IMUX.43	BUFGCE19.CLK_IN_CKINT
TCELL31:IMUX.IMUX.44	BUFGCE20.CLK_IN_CKINT
TCELL31:IMUX.IMUX.45	BUFGCE21.CLK_IN_CKINT
TCELL31:IMUX.IMUX.46	BUFGCE22.CLK_IN_CKINT
TCELL31:IMUX.IMUX.47	BUFGCE23.CLK_IN_CKINT
TCELL32:IMUX.IMUX.0	ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B
TCELL41:IMUX.BYP.0	MMCM.TESTIN28
TCELL41:IMUX.BYP.1	MMCM.TESTIN29
TCELL41:IMUX.BYP.2	MMCM.TESTIN30
TCELL41:IMUX.BYP.3	MMCM.TESTIN31
TCELL41:IMUX.IMUX.0	MMCM.CLKINSEL
TCELL42:IMUX.BYP.0	MMCM.TESTIN24
TCELL42:IMUX.BYP.1	MMCM.TESTIN25
TCELL42:IMUX.BYP.2	MMCM.TESTIN26
TCELL42:IMUX.BYP.3	MMCM.TESTIN27
TCELL43:OUT.0	MMCM.TESTOUT14
TCELL43:OUT.1	MMCM.TESTOUT15
TCELL43:IMUX.BYP.0	MMCM.TESTIN20
TCELL43:IMUX.BYP.1	MMCM.TESTIN21
TCELL43:IMUX.BYP.2	MMCM.TESTIN22
TCELL43:IMUX.BYP.3	MMCM.TESTIN23
TCELL44:OUT.0	MMCM.TESTOUT11
TCELL44:OUT.1	MMCM.TESTOUT12
TCELL44:OUT.2	MMCM.TESTOUT13
TCELL44:IMUX.BYP.0	MMCM.TESTIN16
TCELL44:IMUX.BYP.1	MMCM.TESTIN17
TCELL44:IMUX.BYP.2	MMCM.TESTIN18
TCELL44:IMUX.BYP.3	MMCM.TESTIN19
TCELL45:OUT.0	MMCM.TESTOUT8
TCELL45:OUT.1	MMCM.TESTOUT9
TCELL45:OUT.2	MMCM.TESTOUT10
TCELL45:IMUX.BYP.0	MMCM.TESTIN12
TCELL45:IMUX.BYP.1	MMCM.TESTIN13
TCELL45:IMUX.BYP.2	MMCM.TESTIN14
TCELL45:IMUX.BYP.3	MMCM.TESTIN15
TCELL46:OUT.0	MMCM.TESTOUT5
TCELL46:OUT.1	MMCM.TESTOUT6
TCELL46:OUT.2	MMCM.TESTOUT7
TCELL46:IMUX.BYP.0	MMCM.TESTIN8
TCELL46:IMUX.BYP.1	MMCM.TESTIN9
TCELL46:IMUX.BYP.2	MMCM.TESTIN10
TCELL46:IMUX.BYP.3	MMCM.TESTIN11
TCELL47:OUT.0	MMCM.TESTOUT2
TCELL47:OUT.1	MMCM.TESTOUT3
TCELL47:OUT.2	MMCM.TESTOUT4
TCELL47:IMUX.BYP.0	MMCM.TESTIN4
TCELL47:IMUX.BYP.1	MMCM.TESTIN5
TCELL47:IMUX.BYP.2	MMCM.TESTIN6
TCELL47:IMUX.BYP.3	MMCM.TESTIN7
TCELL47:IMUX.IMUX.0	MMCM.SCANMODEB
TCELL48:OUT.0	MMCM.DOUT15
TCELL48:OUT.1	MMCM.TESTOUT0
TCELL48:OUT.2	MMCM.TESTOUT1
TCELL48:IMUX.BYP.0	MMCM.TESTIN0
TCELL48:IMUX.BYP.1	MMCM.TESTIN1
TCELL48:IMUX.BYP.2	MMCM.TESTIN2
TCELL48:IMUX.BYP.3	MMCM.TESTIN3
TCELL48:IMUX.IMUX.0	MMCM.SCANENB
TCELL49:OUT.0	MMCM.DOUT12
TCELL49:OUT.1	MMCM.DOUT13
TCELL49:OUT.2	MMCM.DOUT14
TCELL49:IMUX.BYP.0	MMCM.DADDR4
TCELL49:IMUX.BYP.1	MMCM.DADDR5
TCELL49:IMUX.BYP.2	MMCM.DADDR6
TCELL49:IMUX.IMUX.0	MMCM.SCANIN
TCELL50:OUT.0	MMCM.DOUT9
TCELL50:OUT.1	MMCM.DOUT10
TCELL50:OUT.2	MMCM.DOUT11
TCELL50:IMUX.BYP.0	MMCM.DADDR0
TCELL50:IMUX.BYP.1	MMCM.DADDR1
TCELL50:IMUX.BYP.2	MMCM.DADDR2
TCELL50:IMUX.BYP.3	MMCM.DADDR3
TCELL50:IMUX.IMUX.0	MMCM.CDDCREQ
TCELL51:OUT.0	MMCM.DOUT6
TCELL51:OUT.1	MMCM.DOUT7
TCELL51:OUT.2	MMCM.DOUT8
TCELL51:IMUX.BYP.0	MMCM.DI12
TCELL51:IMUX.BYP.1	MMCM.DI13
TCELL51:IMUX.BYP.2	MMCM.DI14
TCELL51:IMUX.BYP.3	MMCM.DI15
TCELL51:IMUX.IMUX.0	MMCM.DWE
TCELL52:OUT.0	MMCM.DOUT3
TCELL52:OUT.1	MMCM.DOUT4
TCELL52:OUT.2	MMCM.DOUT5
TCELL52:IMUX.CTRL.0	MMCM.DCLK
TCELL52:IMUX.BYP.0	MMCM.DI8
TCELL52:IMUX.BYP.1	MMCM.DI9
TCELL52:IMUX.BYP.2	MMCM.DI10
TCELL52:IMUX.BYP.3	MMCM.DI11
TCELL52:IMUX.IMUX.0	MMCM.DEN
TCELL53:OUT.0	MMCM.DOUT0
TCELL53:OUT.1	MMCM.DOUT1
TCELL53:OUT.2	MMCM.DOUT2
TCELL53:IMUX.CTRL.0	MMCM.PSCLK
TCELL53:IMUX.BYP.0	MMCM.DI4
TCELL53:IMUX.BYP.1	MMCM.DI5
TCELL53:IMUX.BYP.2	MMCM.DI6
TCELL53:IMUX.BYP.3	MMCM.DI7
TCELL53:IMUX.IMUX.0	MMCM.PWRDWN
TCELL54:OUT.0	MMCM.LOCKED
TCELL54:OUT.1	MMCM.DRDY
TCELL54:OUT.2	MMCM.SCANOUT
TCELL54:IMUX.CTRL.0	MMCM.SCANCLK
TCELL54:IMUX.BYP.0	MMCM.DI0
TCELL54:IMUX.BYP.1	MMCM.DI1
TCELL54:IMUX.BYP.2	MMCM.DI2
TCELL54:IMUX.BYP.3	MMCM.DI3
TCELL54:IMUX.IMUX.0	MMCM.RST
TCELL55:OUT.0	MMCM.CLKFBSTOPPED
TCELL55:OUT.1	MMCM.CLKINSTOPPED
TCELL55:OUT.2	MMCM.PSDONE
TCELL55:IMUX.IMUX.0	MMCM.PSINCDEC
TCELL56:OUT.0	MMCM.CDDCDONE
TCELL56:IMUX.IMUX.0	MMCM.PSEN

Tile CMTXP

Cells: 60 IRIs: 0

Bel BUFCE_ROW_CMT0

ultrascaleplus CMTXP bel BUFCE_ROW_CMT0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.17
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT1

ultrascaleplus CMTXP bel BUFCE_ROW_CMT1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.18
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT2

ultrascaleplus CMTXP bel BUFCE_ROW_CMT2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.19
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT3

ultrascaleplus CMTXP bel BUFCE_ROW_CMT3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.20
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT4

ultrascaleplus CMTXP bel BUFCE_ROW_CMT4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.21
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT5

ultrascaleplus CMTXP bel BUFCE_ROW_CMT5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.22
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT6

ultrascaleplus CMTXP bel BUFCE_ROW_CMT6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.23
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT7

ultrascaleplus CMTXP bel BUFCE_ROW_CMT7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.24
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT8

ultrascaleplus CMTXP bel BUFCE_ROW_CMT8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.25
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT9

ultrascaleplus CMTXP bel BUFCE_ROW_CMT9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.26
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT10

ultrascaleplus CMTXP bel BUFCE_ROW_CMT10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.27
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT11

ultrascaleplus CMTXP bel BUFCE_ROW_CMT11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.28
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT12

ultrascaleplus CMTXP bel BUFCE_ROW_CMT12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.29
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT13

ultrascaleplus CMTXP bel BUFCE_ROW_CMT13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.30
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT14

ultrascaleplus CMTXP bel BUFCE_ROW_CMT14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.31
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT15

ultrascaleplus CMTXP bel BUFCE_ROW_CMT15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.32
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT16

ultrascaleplus CMTXP bel BUFCE_ROW_CMT16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.33
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT17

ultrascaleplus CMTXP bel BUFCE_ROW_CMT17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.34
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT18

ultrascaleplus CMTXP bel BUFCE_ROW_CMT18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.35
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT19

ultrascaleplus CMTXP bel BUFCE_ROW_CMT19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.36
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT20

ultrascaleplus CMTXP bel BUFCE_ROW_CMT20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.37
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.16
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.18
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.20

Bel BUFCE_ROW_CMT21

ultrascaleplus CMTXP bel BUFCE_ROW_CMT21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.38
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT22

ultrascaleplus CMTXP bel BUFCE_ROW_CMT22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.39
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel BUFCE_ROW_CMT23

ultrascaleplus CMTXP bel BUFCE_ROW_CMT23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.40
OPT_DELAY_TEST0	input	TCELL30:RCLK.IMUX.17
OPT_DELAY_TEST1	input	TCELL30:RCLK.IMUX.19
OPT_DELAY_TEST2	input	TCELL30:RCLK.IMUX.21

Bel GCLK_TEST_BUF_CMT0

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT0
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT1

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT1
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT2

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT2
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT3

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT3
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT4

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT4
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT5

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT5
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT6

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT6
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT7

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT7
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT8

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT8
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT9

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT9
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT10

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT10
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT11

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT11
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT12

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT12
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT13

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT13
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT14

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT14
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT15

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT15
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT16

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT16
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT17

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT17
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT18

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT18
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT19

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT19
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT20

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT20
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT21

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT21
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT22

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT22
Pin	Direction	Wires

Bel GCLK_TEST_BUF_CMT23

ultrascaleplus CMTXP bel GCLK_TEST_BUF_CMT23
Pin	Direction	Wires

Bel BUFGCE0

ultrascaleplus CMTXP bel BUFGCE0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.31
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.24

Bel BUFGCE1

ultrascaleplus CMTXP bel BUFGCE1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.32
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.25

Bel BUFGCE2

ultrascaleplus CMTXP bel BUFGCE2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.33
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.26

Bel BUFGCE3

ultrascaleplus CMTXP bel BUFGCE3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.34
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.27

Bel BUFGCE4

ultrascaleplus CMTXP bel BUFGCE4
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.35
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.28

Bel BUFGCE5

ultrascaleplus CMTXP bel BUFGCE5
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.36
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.29

Bel BUFGCE6

ultrascaleplus CMTXP bel BUFGCE6
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.37
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.30

Bel BUFGCE7

ultrascaleplus CMTXP bel BUFGCE7
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.38
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.31

Bel BUFGCE8

ultrascaleplus CMTXP bel BUFGCE8
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.39
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.32

Bel BUFGCE9

ultrascaleplus CMTXP bel BUFGCE9
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.40
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.33

Bel BUFGCE10

ultrascaleplus CMTXP bel BUFGCE10
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.41
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.34

Bel BUFGCE11

ultrascaleplus CMTXP bel BUFGCE11
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.42
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.35

Bel BUFGCE12

ultrascaleplus CMTXP bel BUFGCE12
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.43
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.36

Bel BUFGCE13

ultrascaleplus CMTXP bel BUFGCE13
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.44
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.37

Bel BUFGCE14

ultrascaleplus CMTXP bel BUFGCE14
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.45
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.38

Bel BUFGCE15

ultrascaleplus CMTXP bel BUFGCE15
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.46
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.39

Bel BUFGCE16

ultrascaleplus CMTXP bel BUFGCE16
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL30:IMUX.IMUX.47
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.40

Bel BUFGCE17

ultrascaleplus CMTXP bel BUFGCE17
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.17
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.41

Bel BUFGCE18

ultrascaleplus CMTXP bel BUFGCE18
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.18
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.42

Bel BUFGCE19

ultrascaleplus CMTXP bel BUFGCE19
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.19
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.43

Bel BUFGCE20

ultrascaleplus CMTXP bel BUFGCE20
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.20
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.44

Bel BUFGCE21

ultrascaleplus CMTXP bel BUFGCE21
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.21
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.45

Bel BUFGCE22

ultrascaleplus CMTXP bel BUFGCE22
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.22
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.46

Bel BUFGCE23

ultrascaleplus CMTXP bel BUFGCE23
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL31:IMUX.IMUX.23
CLK_IN_CKINT	input	TCELL31:IMUX.IMUX.47

Bel BUFGCTRL0

ultrascaleplus CMTXP bel BUFGCTRL0
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.23
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.46
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.38
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.30
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.22
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.45

Bel BUFGCTRL1

ultrascaleplus CMTXP bel BUFGCTRL1
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.24
CE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.47
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.39
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.31
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.23
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.46

Bel BUFGCTRL2

ultrascaleplus CMTXP bel BUFGCTRL2
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.25
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.17
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.40
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.32
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.24
SEL1_PRE_OPTINV	input	TCELL28:IMUX.IMUX.47

Bel BUFGCTRL3

ultrascaleplus CMTXP bel BUFGCTRL3
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.26
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.18
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.41
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.33
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.25
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.17

Bel BUFGCTRL4

ultrascaleplus CMTXP bel BUFGCTRL4
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.27
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.19
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.42
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.34
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.26
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.18

Bel BUFGCTRL5

ultrascaleplus CMTXP bel BUFGCTRL5
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.28
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.20
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.43
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.35
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.27
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.19

Bel BUFGCTRL6

ultrascaleplus CMTXP bel BUFGCTRL6
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.29
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.21
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.44
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.36
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.28
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.20

Bel BUFGCTRL7

ultrascaleplus CMTXP bel BUFGCTRL7
Pin	Direction	Wires
CE0_PRE_OPTINV	input	TCELL30:IMUX.IMUX.30
CE1_PRE_OPTINV	input	TCELL30:IMUX.IMUX.22
IGNORE0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.45
IGNORE1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.37
SEL0_PRE_OPTINV	input	TCELL29:IMUX.IMUX.29
SEL1_PRE_OPTINV	input	TCELL29:IMUX.IMUX.21

Bel BUFGCE_DIV0

ultrascaleplus CMTXP bel BUFGCE_DIV0
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.41
RST_PRE_OPTINV	input	TCELL28:IMUX.IMUX.0

Bel BUFGCE_DIV1

ultrascaleplus CMTXP bel BUFGCE_DIV1
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.42
RST_PRE_OPTINV	input	TCELL29:IMUX.IMUX.0

Bel BUFGCE_DIV2

ultrascaleplus CMTXP bel BUFGCE_DIV2
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.43
RST_PRE_OPTINV	input	TCELL30:IMUX.IMUX.0

Bel BUFGCE_DIV3

ultrascaleplus CMTXP bel BUFGCE_DIV3
Pin	Direction	Wires
CE_PRE_OPTINV	input	TCELL28:IMUX.IMUX.44
RST_PRE_OPTINV	input	TCELL31:IMUX.IMUX.0

Bel PLLXP0

ultrascaleplus CMTXP bel PLLXP0
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL1:IMUX.IMUX.0
DADDR0	input	TCELL9:IMUX.BYP.0
DADDR1	input	TCELL9:IMUX.BYP.1
DADDR2	input	TCELL9:IMUX.BYP.2
DADDR3	input	TCELL9:IMUX.BYP.3
DADDR4	input	TCELL8:IMUX.BYP.0
DADDR5	input	TCELL8:IMUX.BYP.1
DADDR6	input	TCELL8:IMUX.BYP.2
DCLK	input	TCELL11:IMUX.CTRL.0
DEN	input	TCELL11:IMUX.IMUX.0
DI0	input	TCELL13:IMUX.BYP.0
DI1	input	TCELL13:IMUX.BYP.1
DI10	input	TCELL11:IMUX.BYP.2
DI11	input	TCELL11:IMUX.BYP.3
DI12	input	TCELL10:IMUX.BYP.0
DI13	input	TCELL10:IMUX.BYP.1
DI14	input	TCELL10:IMUX.BYP.2
DI15	input	TCELL10:IMUX.BYP.3
DI2	input	TCELL13:IMUX.BYP.2
DI3	input	TCELL13:IMUX.BYP.3
DI4	input	TCELL12:IMUX.BYP.0
DI5	input	TCELL12:IMUX.BYP.1
DI6	input	TCELL12:IMUX.BYP.2
DI7	input	TCELL12:IMUX.BYP.3
DI8	input	TCELL11:IMUX.BYP.0
DI9	input	TCELL11:IMUX.BYP.1
DOUT0	output	TCELL12:OUT.0
DOUT1	output	TCELL12:OUT.1
DOUT10	output	TCELL9:OUT.1
DOUT11	output	TCELL9:OUT.2
DOUT12	output	TCELL8:OUT.0
DOUT13	output	TCELL8:OUT.1
DOUT14	output	TCELL8:OUT.2
DOUT15	output	TCELL7:OUT.0
DOUT2	output	TCELL12:OUT.2
DOUT3	output	TCELL11:OUT.0
DOUT4	output	TCELL11:OUT.1
DOUT5	output	TCELL11:OUT.2
DOUT6	output	TCELL10:OUT.0
DOUT7	output	TCELL10:OUT.1
DOUT8	output	TCELL10:OUT.2
DOUT9	output	TCELL9:OUT.0
DRDY	output	TCELL13:OUT.1
DWE	input	TCELL10:IMUX.IMUX.0
LOCKED	output	TCELL13:OUT.0
PWRDWN	input	TCELL12:IMUX.IMUX.0
RST	input	TCELL13:IMUX.IMUX.0
SCANCLK	input	TCELL13:IMUX.CTRL.0
SCANENB	input	TCELL7:IMUX.IMUX.0
SCANIN	input	TCELL8:IMUX.IMUX.0
SCANMODEB	input	TCELL6:IMUX.IMUX.0
SCANOUT	output	TCELL13:OUT.2
TESTIN0	input	TCELL7:IMUX.BYP.0
TESTIN1	input	TCELL7:IMUX.BYP.1
TESTIN10	input	TCELL5:IMUX.BYP.2
TESTIN11	input	TCELL5:IMUX.BYP.3
TESTIN12	input	TCELL4:IMUX.BYP.0
TESTIN13	input	TCELL4:IMUX.BYP.1
TESTIN14	input	TCELL4:IMUX.BYP.2
TESTIN15	input	TCELL4:IMUX.BYP.3
TESTIN16	input	TCELL3:IMUX.BYP.0
TESTIN17	input	TCELL3:IMUX.BYP.1
TESTIN18	input	TCELL3:IMUX.BYP.2
TESTIN19	input	TCELL3:IMUX.BYP.3
TESTIN2	input	TCELL7:IMUX.BYP.2
TESTIN20	input	TCELL2:IMUX.BYP.0
TESTIN21	input	TCELL2:IMUX.BYP.1
TESTIN22	input	TCELL2:IMUX.BYP.2
TESTIN23	input	TCELL2:IMUX.BYP.3
TESTIN24	input	TCELL1:IMUX.BYP.0
TESTIN25	input	TCELL1:IMUX.BYP.1
TESTIN26	input	TCELL1:IMUX.BYP.2
TESTIN27	input	TCELL1:IMUX.BYP.3
TESTIN28	input	TCELL0:IMUX.BYP.0
TESTIN29	input	TCELL0:IMUX.BYP.1
TESTIN3	input	TCELL7:IMUX.BYP.3
TESTIN30	input	TCELL0:IMUX.BYP.2
TESTIN31	input	TCELL0:IMUX.BYP.3
TESTIN4	input	TCELL6:IMUX.BYP.0
TESTIN5	input	TCELL6:IMUX.BYP.1
TESTIN6	input	TCELL6:IMUX.BYP.2
TESTIN7	input	TCELL6:IMUX.BYP.3
TESTIN8	input	TCELL5:IMUX.BYP.0
TESTIN9	input	TCELL5:IMUX.BYP.1
TESTOUT0	output	TCELL7:OUT.1
TESTOUT1	output	TCELL7:OUT.2
TESTOUT10	output	TCELL4:OUT.2
TESTOUT11	output	TCELL3:OUT.0
TESTOUT12	output	TCELL3:OUT.1
TESTOUT13	output	TCELL3:OUT.2
TESTOUT14	output	TCELL2:OUT.0
TESTOUT15	output	TCELL2:OUT.1
TESTOUT2	output	TCELL6:OUT.0
TESTOUT3	output	TCELL6:OUT.1
TESTOUT4	output	TCELL6:OUT.2
TESTOUT5	output	TCELL5:OUT.0
TESTOUT6	output	TCELL5:OUT.1
TESTOUT7	output	TCELL5:OUT.2
TESTOUT8	output	TCELL4:OUT.0
TESTOUT9	output	TCELL4:OUT.1

Bel PLLXP1

ultrascaleplus CMTXP bel PLLXP1
Pin	Direction	Wires
CLKOUTPHY_EN	input	TCELL15:IMUX.IMUX.0
DADDR0	input	TCELL23:IMUX.BYP.0
DADDR1	input	TCELL23:IMUX.BYP.1
DADDR2	input	TCELL23:IMUX.BYP.2
DADDR3	input	TCELL23:IMUX.BYP.3
DADDR4	input	TCELL22:IMUX.BYP.0
DADDR5	input	TCELL22:IMUX.BYP.1
DADDR6	input	TCELL22:IMUX.BYP.2
DCLK	input	TCELL25:IMUX.CTRL.0
DEN	input	TCELL25:IMUX.IMUX.0
DI0	input	TCELL27:IMUX.BYP.0
DI1	input	TCELL27:IMUX.BYP.1
DI10	input	TCELL25:IMUX.BYP.2
DI11	input	TCELL25:IMUX.BYP.3
DI12	input	TCELL24:IMUX.BYP.0
DI13	input	TCELL24:IMUX.BYP.1
DI14	input	TCELL24:IMUX.BYP.2
DI15	input	TCELL24:IMUX.BYP.3
DI2	input	TCELL27:IMUX.BYP.2
DI3	input	TCELL27:IMUX.BYP.3
DI4	input	TCELL26:IMUX.BYP.0
DI5	input	TCELL26:IMUX.BYP.1
DI6	input	TCELL26:IMUX.BYP.2
DI7	input	TCELL26:IMUX.BYP.3
DI8	input	TCELL25:IMUX.BYP.0
DI9	input	TCELL25:IMUX.BYP.1
DOUT0	output	TCELL26:OUT.0
DOUT1	output	TCELL26:OUT.1
DOUT10	output	TCELL23:OUT.1
DOUT11	output	TCELL23:OUT.2
DOUT12	output	TCELL22:OUT.0
DOUT13	output	TCELL22:OUT.1
DOUT14	output	TCELL22:OUT.2
DOUT15	output	TCELL21:OUT.0
DOUT2	output	TCELL26:OUT.2
DOUT3	output	TCELL25:OUT.0
DOUT4	output	TCELL25:OUT.1
DOUT5	output	TCELL25:OUT.2
DOUT6	output	TCELL24:OUT.0
DOUT7	output	TCELL24:OUT.1
DOUT8	output	TCELL24:OUT.2
DOUT9	output	TCELL23:OUT.0
DRDY	output	TCELL27:OUT.1
DWE	input	TCELL24:IMUX.IMUX.0
LOCKED	output	TCELL27:OUT.0
PWRDWN	input	TCELL26:IMUX.IMUX.0
RST	input	TCELL27:IMUX.IMUX.0
SCANCLK	input	TCELL27:IMUX.CTRL.0
SCANENB	input	TCELL21:IMUX.IMUX.0
SCANIN	input	TCELL22:IMUX.IMUX.0
SCANMODEB	input	TCELL20:IMUX.IMUX.0
SCANOUT	output	TCELL27:OUT.2
TESTIN0	input	TCELL21:IMUX.BYP.0
TESTIN1	input	TCELL21:IMUX.BYP.1
TESTIN10	input	TCELL19:IMUX.BYP.2
TESTIN11	input	TCELL19:IMUX.BYP.3
TESTIN12	input	TCELL18:IMUX.BYP.0
TESTIN13	input	TCELL18:IMUX.BYP.1
TESTIN14	input	TCELL18:IMUX.BYP.2
TESTIN15	input	TCELL18:IMUX.BYP.3
TESTIN16	input	TCELL17:IMUX.BYP.0
TESTIN17	input	TCELL17:IMUX.BYP.1
TESTIN18	input	TCELL17:IMUX.BYP.2
TESTIN19	input	TCELL17:IMUX.BYP.3
TESTIN2	input	TCELL21:IMUX.BYP.2
TESTIN20	input	TCELL16:IMUX.BYP.0
TESTIN21	input	TCELL16:IMUX.BYP.1
TESTIN22	input	TCELL16:IMUX.BYP.2
TESTIN23	input	TCELL16:IMUX.BYP.3
TESTIN24	input	TCELL15:IMUX.BYP.0
TESTIN25	input	TCELL15:IMUX.BYP.1
TESTIN26	input	TCELL15:IMUX.BYP.2
TESTIN27	input	TCELL15:IMUX.BYP.3
TESTIN28	input	TCELL14:IMUX.BYP.0
TESTIN29	input	TCELL14:IMUX.BYP.1
TESTIN3	input	TCELL21:IMUX.BYP.3
TESTIN30	input	TCELL14:IMUX.BYP.2
TESTIN31	input	TCELL14:IMUX.BYP.3
TESTIN4	input	TCELL20:IMUX.BYP.0
TESTIN5	input	TCELL20:IMUX.BYP.1
TESTIN6	input	TCELL20:IMUX.BYP.2
TESTIN7	input	TCELL20:IMUX.BYP.3
TESTIN8	input	TCELL19:IMUX.BYP.0
TESTIN9	input	TCELL19:IMUX.BYP.1
TESTOUT0	output	TCELL21:OUT.1
TESTOUT1	output	TCELL21:OUT.2
TESTOUT10	output	TCELL18:OUT.2
TESTOUT11	output	TCELL17:OUT.0
TESTOUT12	output	TCELL17:OUT.1
TESTOUT13	output	TCELL17:OUT.2
TESTOUT14	output	TCELL16:OUT.0
TESTOUT15	output	TCELL16:OUT.1
TESTOUT2	output	TCELL20:OUT.0
TESTOUT3	output	TCELL20:OUT.1
TESTOUT4	output	TCELL20:OUT.2
TESTOUT5	output	TCELL19:OUT.0
TESTOUT6	output	TCELL19:OUT.1
TESTOUT7	output	TCELL19:OUT.2
TESTOUT8	output	TCELL18:OUT.0
TESTOUT9	output	TCELL18:OUT.1

Bel MMCM

ultrascaleplus CMTXP bel MMCM
Pin	Direction	Wires
CDDCDONE	output	TCELL56:OUT.0
CDDCREQ	input	TCELL50:IMUX.IMUX.0
CLKFBSTOPPED	output	TCELL55:OUT.0
CLKINSEL	input	TCELL41:IMUX.IMUX.0
CLKINSTOPPED	output	TCELL55:OUT.1
DADDR0	input	TCELL50:IMUX.BYP.0
DADDR1	input	TCELL50:IMUX.BYP.1
DADDR2	input	TCELL50:IMUX.BYP.2
DADDR3	input	TCELL50:IMUX.BYP.3
DADDR4	input	TCELL49:IMUX.BYP.0
DADDR5	input	TCELL49:IMUX.BYP.1
DADDR6	input	TCELL49:IMUX.BYP.2
DCLK	input	TCELL52:IMUX.CTRL.0
DEN	input	TCELL52:IMUX.IMUX.0
DI0	input	TCELL54:IMUX.BYP.0
DI1	input	TCELL54:IMUX.BYP.1
DI10	input	TCELL52:IMUX.BYP.2
DI11	input	TCELL52:IMUX.BYP.3
DI12	input	TCELL51:IMUX.BYP.0
DI13	input	TCELL51:IMUX.BYP.1
DI14	input	TCELL51:IMUX.BYP.2
DI15	input	TCELL51:IMUX.BYP.3
DI2	input	TCELL54:IMUX.BYP.2
DI3	input	TCELL54:IMUX.BYP.3
DI4	input	TCELL53:IMUX.BYP.0
DI5	input	TCELL53:IMUX.BYP.1
DI6	input	TCELL53:IMUX.BYP.2
DI7	input	TCELL53:IMUX.BYP.3
DI8	input	TCELL52:IMUX.BYP.0
DI9	input	TCELL52:IMUX.BYP.1
DOUT0	output	TCELL53:OUT.0
DOUT1	output	TCELL53:OUT.1
DOUT10	output	TCELL50:OUT.1
DOUT11	output	TCELL50:OUT.2
DOUT12	output	TCELL49:OUT.0
DOUT13	output	TCELL49:OUT.1
DOUT14	output	TCELL49:OUT.2
DOUT15	output	TCELL48:OUT.0
DOUT2	output	TCELL53:OUT.2
DOUT3	output	TCELL52:OUT.0
DOUT4	output	TCELL52:OUT.1
DOUT5	output	TCELL52:OUT.2
DOUT6	output	TCELL51:OUT.0
DOUT7	output	TCELL51:OUT.1
DOUT8	output	TCELL51:OUT.2
DOUT9	output	TCELL50:OUT.0
DRDY	output	TCELL54:OUT.1
DWE	input	TCELL51:IMUX.IMUX.0
LOCKED	output	TCELL54:OUT.0
PSCLK	input	TCELL53:IMUX.CTRL.0
PSDONE	output	TCELL55:OUT.2
PSEN	input	TCELL56:IMUX.IMUX.0
PSINCDEC	input	TCELL55:IMUX.IMUX.0
PWRDWN	input	TCELL53:IMUX.IMUX.0
RST	input	TCELL54:IMUX.IMUX.0
SCANCLK	input	TCELL54:IMUX.CTRL.0
SCANENB	input	TCELL48:IMUX.IMUX.0
SCANIN	input	TCELL49:IMUX.IMUX.0
SCANMODEB	input	TCELL47:IMUX.IMUX.0
SCANOUT	output	TCELL54:OUT.2
TESTIN0	input	TCELL48:IMUX.BYP.0
TESTIN1	input	TCELL48:IMUX.BYP.1
TESTIN10	input	TCELL46:IMUX.BYP.2
TESTIN11	input	TCELL46:IMUX.BYP.3
TESTIN12	input	TCELL45:IMUX.BYP.0
TESTIN13	input	TCELL45:IMUX.BYP.1
TESTIN14	input	TCELL45:IMUX.BYP.2
TESTIN15	input	TCELL45:IMUX.BYP.3
TESTIN16	input	TCELL44:IMUX.BYP.0
TESTIN17	input	TCELL44:IMUX.BYP.1
TESTIN18	input	TCELL44:IMUX.BYP.2
TESTIN19	input	TCELL44:IMUX.BYP.3
TESTIN2	input	TCELL48:IMUX.BYP.2
TESTIN20	input	TCELL43:IMUX.BYP.0
TESTIN21	input	TCELL43:IMUX.BYP.1
TESTIN22	input	TCELL43:IMUX.BYP.2
TESTIN23	input	TCELL43:IMUX.BYP.3
TESTIN24	input	TCELL42:IMUX.BYP.0
TESTIN25	input	TCELL42:IMUX.BYP.1
TESTIN26	input	TCELL42:IMUX.BYP.2
TESTIN27	input	TCELL42:IMUX.BYP.3
TESTIN28	input	TCELL41:IMUX.BYP.0
TESTIN29	input	TCELL41:IMUX.BYP.1
TESTIN3	input	TCELL48:IMUX.BYP.3
TESTIN30	input	TCELL41:IMUX.BYP.2
TESTIN31	input	TCELL41:IMUX.BYP.3
TESTIN4	input	TCELL47:IMUX.BYP.0
TESTIN5	input	TCELL47:IMUX.BYP.1
TESTIN6	input	TCELL47:IMUX.BYP.2
TESTIN7	input	TCELL47:IMUX.BYP.3
TESTIN8	input	TCELL46:IMUX.BYP.0
TESTIN9	input	TCELL46:IMUX.BYP.1
TESTOUT0	output	TCELL48:OUT.1
TESTOUT1	output	TCELL48:OUT.2
TESTOUT10	output	TCELL45:OUT.2
TESTOUT11	output	TCELL44:OUT.0
TESTOUT12	output	TCELL44:OUT.1
TESTOUT13	output	TCELL44:OUT.2
TESTOUT14	output	TCELL43:OUT.0
TESTOUT15	output	TCELL43:OUT.1
TESTOUT2	output	TCELL47:OUT.0
TESTOUT3	output	TCELL47:OUT.1
TESTOUT4	output	TCELL47:OUT.2
TESTOUT5	output	TCELL46:OUT.0
TESTOUT6	output	TCELL46:OUT.1
TESTOUT7	output	TCELL46:OUT.2
TESTOUT8	output	TCELL45:OUT.0
TESTOUT9	output	TCELL45:OUT.1

Bel CMTXP

ultrascaleplus CMTXP bel CMTXP
Pin	Direction	Wires

Bel VCC_CMT

ultrascaleplus CMTXP bel VCC_CMT
Pin	Direction	Wires

Bel ABUS_SWITCH_CMT

ultrascaleplus CMTXP bel ABUS_SWITCH_CMT
Pin	Direction	Wires
TEST_ANALOGBUS_SEL_B	input	TCELL32:IMUX.IMUX.0

Bel wires

ultrascaleplus CMTXP bel wires
Wire	Pins
TCELL0:IMUX.BYP.0	PLLXP0.TESTIN28
TCELL0:IMUX.BYP.1	PLLXP0.TESTIN29
TCELL0:IMUX.BYP.2	PLLXP0.TESTIN30
TCELL0:IMUX.BYP.3	PLLXP0.TESTIN31
TCELL1:IMUX.BYP.0	PLLXP0.TESTIN24
TCELL1:IMUX.BYP.1	PLLXP0.TESTIN25
TCELL1:IMUX.BYP.2	PLLXP0.TESTIN26
TCELL1:IMUX.BYP.3	PLLXP0.TESTIN27
TCELL1:IMUX.IMUX.0	PLLXP0.CLKOUTPHY_EN
TCELL2:OUT.0	PLLXP0.TESTOUT14
TCELL2:OUT.1	PLLXP0.TESTOUT15
TCELL2:IMUX.BYP.0	PLLXP0.TESTIN20
TCELL2:IMUX.BYP.1	PLLXP0.TESTIN21
TCELL2:IMUX.BYP.2	PLLXP0.TESTIN22
TCELL2:IMUX.BYP.3	PLLXP0.TESTIN23
TCELL3:OUT.0	PLLXP0.TESTOUT11
TCELL3:OUT.1	PLLXP0.TESTOUT12
TCELL3:OUT.2	PLLXP0.TESTOUT13
TCELL3:IMUX.BYP.0	PLLXP0.TESTIN16
TCELL3:IMUX.BYP.1	PLLXP0.TESTIN17
TCELL3:IMUX.BYP.2	PLLXP0.TESTIN18
TCELL3:IMUX.BYP.3	PLLXP0.TESTIN19
TCELL4:OUT.0	PLLXP0.TESTOUT8
TCELL4:OUT.1	PLLXP0.TESTOUT9
TCELL4:OUT.2	PLLXP0.TESTOUT10
TCELL4:IMUX.BYP.0	PLLXP0.TESTIN12
TCELL4:IMUX.BYP.1	PLLXP0.TESTIN13
TCELL4:IMUX.BYP.2	PLLXP0.TESTIN14
TCELL4:IMUX.BYP.3	PLLXP0.TESTIN15
TCELL5:OUT.0	PLLXP0.TESTOUT5
TCELL5:OUT.1	PLLXP0.TESTOUT6
TCELL5:OUT.2	PLLXP0.TESTOUT7
TCELL5:IMUX.BYP.0	PLLXP0.TESTIN8
TCELL5:IMUX.BYP.1	PLLXP0.TESTIN9
TCELL5:IMUX.BYP.2	PLLXP0.TESTIN10
TCELL5:IMUX.BYP.3	PLLXP0.TESTIN11
TCELL6:OUT.0	PLLXP0.TESTOUT2
TCELL6:OUT.1	PLLXP0.TESTOUT3
TCELL6:OUT.2	PLLXP0.TESTOUT4
TCELL6:IMUX.BYP.0	PLLXP0.TESTIN4
TCELL6:IMUX.BYP.1	PLLXP0.TESTIN5
TCELL6:IMUX.BYP.2	PLLXP0.TESTIN6
TCELL6:IMUX.BYP.3	PLLXP0.TESTIN7
TCELL6:IMUX.IMUX.0	PLLXP0.SCANMODEB
TCELL7:OUT.0	PLLXP0.DOUT15
TCELL7:OUT.1	PLLXP0.TESTOUT0
TCELL7:OUT.2	PLLXP0.TESTOUT1
TCELL7:IMUX.BYP.0	PLLXP0.TESTIN0
TCELL7:IMUX.BYP.1	PLLXP0.TESTIN1
TCELL7:IMUX.BYP.2	PLLXP0.TESTIN2
TCELL7:IMUX.BYP.3	PLLXP0.TESTIN3
TCELL7:IMUX.IMUX.0	PLLXP0.SCANENB
TCELL8:OUT.0	PLLXP0.DOUT12
TCELL8:OUT.1	PLLXP0.DOUT13
TCELL8:OUT.2	PLLXP0.DOUT14
TCELL8:IMUX.BYP.0	PLLXP0.DADDR4
TCELL8:IMUX.BYP.1	PLLXP0.DADDR5
TCELL8:IMUX.BYP.2	PLLXP0.DADDR6
TCELL8:IMUX.IMUX.0	PLLXP0.SCANIN
TCELL9:OUT.0	PLLXP0.DOUT9
TCELL9:OUT.1	PLLXP0.DOUT10
TCELL9:OUT.2	PLLXP0.DOUT11
TCELL9:IMUX.BYP.0	PLLXP0.DADDR0
TCELL9:IMUX.BYP.1	PLLXP0.DADDR1
TCELL9:IMUX.BYP.2	PLLXP0.DADDR2
TCELL9:IMUX.BYP.3	PLLXP0.DADDR3
TCELL10:OUT.0	PLLXP0.DOUT6
TCELL10:OUT.1	PLLXP0.DOUT7
TCELL10:OUT.2	PLLXP0.DOUT8
TCELL10:IMUX.BYP.0	PLLXP0.DI12
TCELL10:IMUX.BYP.1	PLLXP0.DI13
TCELL10:IMUX.BYP.2	PLLXP0.DI14
TCELL10:IMUX.BYP.3	PLLXP0.DI15
TCELL10:IMUX.IMUX.0	PLLXP0.DWE
TCELL11:OUT.0	PLLXP0.DOUT3
TCELL11:OUT.1	PLLXP0.DOUT4
TCELL11:OUT.2	PLLXP0.DOUT5
TCELL11:IMUX.CTRL.0	PLLXP0.DCLK
TCELL11:IMUX.BYP.0	PLLXP0.DI8
TCELL11:IMUX.BYP.1	PLLXP0.DI9
TCELL11:IMUX.BYP.2	PLLXP0.DI10
TCELL11:IMUX.BYP.3	PLLXP0.DI11
TCELL11:IMUX.IMUX.0	PLLXP0.DEN
TCELL12:OUT.0	PLLXP0.DOUT0
TCELL12:OUT.1	PLLXP0.DOUT1
TCELL12:OUT.2	PLLXP0.DOUT2
TCELL12:IMUX.BYP.0	PLLXP0.DI4
TCELL12:IMUX.BYP.1	PLLXP0.DI5
TCELL12:IMUX.BYP.2	PLLXP0.DI6
TCELL12:IMUX.BYP.3	PLLXP0.DI7
TCELL12:IMUX.IMUX.0	PLLXP0.PWRDWN
TCELL13:OUT.0	PLLXP0.LOCKED
TCELL13:OUT.1	PLLXP0.DRDY
TCELL13:OUT.2	PLLXP0.SCANOUT
TCELL13:IMUX.CTRL.0	PLLXP0.SCANCLK
TCELL13:IMUX.BYP.0	PLLXP0.DI0
TCELL13:IMUX.BYP.1	PLLXP0.DI1
TCELL13:IMUX.BYP.2	PLLXP0.DI2
TCELL13:IMUX.BYP.3	PLLXP0.DI3
TCELL13:IMUX.IMUX.0	PLLXP0.RST
TCELL14:IMUX.BYP.0	PLLXP1.TESTIN28
TCELL14:IMUX.BYP.1	PLLXP1.TESTIN29
TCELL14:IMUX.BYP.2	PLLXP1.TESTIN30
TCELL14:IMUX.BYP.3	PLLXP1.TESTIN31
TCELL15:IMUX.BYP.0	PLLXP1.TESTIN24
TCELL15:IMUX.BYP.1	PLLXP1.TESTIN25
TCELL15:IMUX.BYP.2	PLLXP1.TESTIN26
TCELL15:IMUX.BYP.3	PLLXP1.TESTIN27
TCELL15:IMUX.IMUX.0	PLLXP1.CLKOUTPHY_EN
TCELL16:OUT.0	PLLXP1.TESTOUT14
TCELL16:OUT.1	PLLXP1.TESTOUT15
TCELL16:IMUX.BYP.0	PLLXP1.TESTIN20
TCELL16:IMUX.BYP.1	PLLXP1.TESTIN21
TCELL16:IMUX.BYP.2	PLLXP1.TESTIN22
TCELL16:IMUX.BYP.3	PLLXP1.TESTIN23
TCELL17:OUT.0	PLLXP1.TESTOUT11
TCELL17:OUT.1	PLLXP1.TESTOUT12
TCELL17:OUT.2	PLLXP1.TESTOUT13
TCELL17:IMUX.BYP.0	PLLXP1.TESTIN16
TCELL17:IMUX.BYP.1	PLLXP1.TESTIN17
TCELL17:IMUX.BYP.2	PLLXP1.TESTIN18
TCELL17:IMUX.BYP.3	PLLXP1.TESTIN19
TCELL18:OUT.0	PLLXP1.TESTOUT8
TCELL18:OUT.1	PLLXP1.TESTOUT9
TCELL18:OUT.2	PLLXP1.TESTOUT10
TCELL18:IMUX.BYP.0	PLLXP1.TESTIN12
TCELL18:IMUX.BYP.1	PLLXP1.TESTIN13
TCELL18:IMUX.BYP.2	PLLXP1.TESTIN14
TCELL18:IMUX.BYP.3	PLLXP1.TESTIN15
TCELL19:OUT.0	PLLXP1.TESTOUT5
TCELL19:OUT.1	PLLXP1.TESTOUT6
TCELL19:OUT.2	PLLXP1.TESTOUT7
TCELL19:IMUX.BYP.0	PLLXP1.TESTIN8
TCELL19:IMUX.BYP.1	PLLXP1.TESTIN9
TCELL19:IMUX.BYP.2	PLLXP1.TESTIN10
TCELL19:IMUX.BYP.3	PLLXP1.TESTIN11
TCELL20:OUT.0	PLLXP1.TESTOUT2
TCELL20:OUT.1	PLLXP1.TESTOUT3
TCELL20:OUT.2	PLLXP1.TESTOUT4
TCELL20:IMUX.BYP.0	PLLXP1.TESTIN4
TCELL20:IMUX.BYP.1	PLLXP1.TESTIN5
TCELL20:IMUX.BYP.2	PLLXP1.TESTIN6
TCELL20:IMUX.BYP.3	PLLXP1.TESTIN7
TCELL20:IMUX.IMUX.0	PLLXP1.SCANMODEB
TCELL21:OUT.0	PLLXP1.DOUT15
TCELL21:OUT.1	PLLXP1.TESTOUT0
TCELL21:OUT.2	PLLXP1.TESTOUT1
TCELL21:IMUX.BYP.0	PLLXP1.TESTIN0
TCELL21:IMUX.BYP.1	PLLXP1.TESTIN1
TCELL21:IMUX.BYP.2	PLLXP1.TESTIN2
TCELL21:IMUX.BYP.3	PLLXP1.TESTIN3
TCELL21:IMUX.IMUX.0	PLLXP1.SCANENB
TCELL22:OUT.0	PLLXP1.DOUT12
TCELL22:OUT.1	PLLXP1.DOUT13
TCELL22:OUT.2	PLLXP1.DOUT14
TCELL22:IMUX.BYP.0	PLLXP1.DADDR4
TCELL22:IMUX.BYP.1	PLLXP1.DADDR5
TCELL22:IMUX.BYP.2	PLLXP1.DADDR6
TCELL22:IMUX.IMUX.0	PLLXP1.SCANIN
TCELL23:OUT.0	PLLXP1.DOUT9
TCELL23:OUT.1	PLLXP1.DOUT10
TCELL23:OUT.2	PLLXP1.DOUT11
TCELL23:IMUX.BYP.0	PLLXP1.DADDR0
TCELL23:IMUX.BYP.1	PLLXP1.DADDR1
TCELL23:IMUX.BYP.2	PLLXP1.DADDR2
TCELL23:IMUX.BYP.3	PLLXP1.DADDR3
TCELL24:OUT.0	PLLXP1.DOUT6
TCELL24:OUT.1	PLLXP1.DOUT7
TCELL24:OUT.2	PLLXP1.DOUT8
TCELL24:IMUX.BYP.0	PLLXP1.DI12
TCELL24:IMUX.BYP.1	PLLXP1.DI13
TCELL24:IMUX.BYP.2	PLLXP1.DI14
TCELL24:IMUX.BYP.3	PLLXP1.DI15
TCELL24:IMUX.IMUX.0	PLLXP1.DWE
TCELL25:OUT.0	PLLXP1.DOUT3
TCELL25:OUT.1	PLLXP1.DOUT4
TCELL25:OUT.2	PLLXP1.DOUT5
TCELL25:IMUX.CTRL.0	PLLXP1.DCLK
TCELL25:IMUX.BYP.0	PLLXP1.DI8
TCELL25:IMUX.BYP.1	PLLXP1.DI9
TCELL25:IMUX.BYP.2	PLLXP1.DI10
TCELL25:IMUX.BYP.3	PLLXP1.DI11
TCELL25:IMUX.IMUX.0	PLLXP1.DEN
TCELL26:OUT.0	PLLXP1.DOUT0
TCELL26:OUT.1	PLLXP1.DOUT1
TCELL26:OUT.2	PLLXP1.DOUT2
TCELL26:IMUX.BYP.0	PLLXP1.DI4
TCELL26:IMUX.BYP.1	PLLXP1.DI5
TCELL26:IMUX.BYP.2	PLLXP1.DI6
TCELL26:IMUX.BYP.3	PLLXP1.DI7
TCELL26:IMUX.IMUX.0	PLLXP1.PWRDWN
TCELL27:OUT.0	PLLXP1.LOCKED
TCELL27:OUT.1	PLLXP1.DRDY
TCELL27:OUT.2	PLLXP1.SCANOUT
TCELL27:IMUX.CTRL.0	PLLXP1.SCANCLK
TCELL27:IMUX.BYP.0	PLLXP1.DI0
TCELL27:IMUX.BYP.1	PLLXP1.DI1
TCELL27:IMUX.BYP.2	PLLXP1.DI2
TCELL27:IMUX.BYP.3	PLLXP1.DI3
TCELL27:IMUX.IMUX.0	PLLXP1.RST
TCELL28:IMUX.IMUX.0	BUFGCE_DIV0.RST_PRE_OPTINV
TCELL28:IMUX.IMUX.17	BUFCE_ROW_CMT0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.18	BUFCE_ROW_CMT1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.19	BUFCE_ROW_CMT2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.20	BUFCE_ROW_CMT3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.21	BUFCE_ROW_CMT4.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.22	BUFCE_ROW_CMT5.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.23	BUFCE_ROW_CMT6.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.24	BUFCE_ROW_CMT7.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.25	BUFCE_ROW_CMT8.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.26	BUFCE_ROW_CMT9.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.27	BUFCE_ROW_CMT10.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.28	BUFCE_ROW_CMT11.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.29	BUFCE_ROW_CMT12.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.30	BUFCE_ROW_CMT13.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.31	BUFCE_ROW_CMT14.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.32	BUFCE_ROW_CMT15.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.33	BUFCE_ROW_CMT16.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.34	BUFCE_ROW_CMT17.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.35	BUFCE_ROW_CMT18.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.36	BUFCE_ROW_CMT19.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.37	BUFCE_ROW_CMT20.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.38	BUFCE_ROW_CMT21.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.39	BUFCE_ROW_CMT22.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.40	BUFCE_ROW_CMT23.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.41	BUFGCE_DIV0.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.42	BUFGCE_DIV1.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.43	BUFGCE_DIV2.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.44	BUFGCE_DIV3.CE_PRE_OPTINV
TCELL28:IMUX.IMUX.45	BUFGCTRL0.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.46	BUFGCTRL1.SEL1_PRE_OPTINV
TCELL28:IMUX.IMUX.47	BUFGCTRL2.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.0	BUFGCE_DIV1.RST_PRE_OPTINV
TCELL29:IMUX.IMUX.17	BUFGCTRL3.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.18	BUFGCTRL4.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.19	BUFGCTRL5.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.20	BUFGCTRL6.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.21	BUFGCTRL7.SEL1_PRE_OPTINV
TCELL29:IMUX.IMUX.22	BUFGCTRL0.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.23	BUFGCTRL1.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.24	BUFGCTRL2.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.25	BUFGCTRL3.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.26	BUFGCTRL4.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.27	BUFGCTRL5.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.28	BUFGCTRL6.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.29	BUFGCTRL7.SEL0_PRE_OPTINV
TCELL29:IMUX.IMUX.30	BUFGCTRL0.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.31	BUFGCTRL1.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.32	BUFGCTRL2.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.33	BUFGCTRL3.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.34	BUFGCTRL4.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.35	BUFGCTRL5.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.36	BUFGCTRL6.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.37	BUFGCTRL7.IGNORE1_PRE_OPTINV
TCELL29:IMUX.IMUX.38	BUFGCTRL0.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.39	BUFGCTRL1.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.40	BUFGCTRL2.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.41	BUFGCTRL3.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.42	BUFGCTRL4.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.43	BUFGCTRL5.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.44	BUFGCTRL6.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.45	BUFGCTRL7.IGNORE0_PRE_OPTINV
TCELL29:IMUX.IMUX.46	BUFGCTRL0.CE1_PRE_OPTINV
TCELL29:IMUX.IMUX.47	BUFGCTRL1.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.0	BUFGCE_DIV2.RST_PRE_OPTINV
TCELL30:IMUX.IMUX.17	BUFGCTRL2.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.18	BUFGCTRL3.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.19	BUFGCTRL4.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.20	BUFGCTRL5.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.21	BUFGCTRL6.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.22	BUFGCTRL7.CE1_PRE_OPTINV
TCELL30:IMUX.IMUX.23	BUFGCTRL0.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.24	BUFGCTRL1.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.25	BUFGCTRL2.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.26	BUFGCTRL3.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.27	BUFGCTRL4.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.28	BUFGCTRL5.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.29	BUFGCTRL6.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.30	BUFGCTRL7.CE0_PRE_OPTINV
TCELL30:IMUX.IMUX.31	BUFGCE0.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.32	BUFGCE1.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.33	BUFGCE2.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.34	BUFGCE3.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.35	BUFGCE4.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.36	BUFGCE5.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.37	BUFGCE6.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.38	BUFGCE7.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.39	BUFGCE8.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.40	BUFGCE9.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.41	BUFGCE10.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.42	BUFGCE11.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.43	BUFGCE12.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.44	BUFGCE13.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.45	BUFGCE14.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.46	BUFGCE15.CE_PRE_OPTINV
TCELL30:IMUX.IMUX.47	BUFGCE16.CE_PRE_OPTINV
TCELL30:RCLK.IMUX.16	BUFCE_ROW_CMT0.OPT_DELAY_TEST0, BUFCE_ROW_CMT1.OPT_DELAY_TEST0, BUFCE_ROW_CMT2.OPT_DELAY_TEST0, BUFCE_ROW_CMT6.OPT_DELAY_TEST0, BUFCE_ROW_CMT7.OPT_DELAY_TEST0, BUFCE_ROW_CMT8.OPT_DELAY_TEST0, BUFCE_ROW_CMT12.OPT_DELAY_TEST0, BUFCE_ROW_CMT13.OPT_DELAY_TEST0, BUFCE_ROW_CMT14.OPT_DELAY_TEST0, BUFCE_ROW_CMT18.OPT_DELAY_TEST0, BUFCE_ROW_CMT19.OPT_DELAY_TEST0, BUFCE_ROW_CMT20.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.17	BUFCE_ROW_CMT3.OPT_DELAY_TEST0, BUFCE_ROW_CMT4.OPT_DELAY_TEST0, BUFCE_ROW_CMT5.OPT_DELAY_TEST0, BUFCE_ROW_CMT9.OPT_DELAY_TEST0, BUFCE_ROW_CMT10.OPT_DELAY_TEST0, BUFCE_ROW_CMT11.OPT_DELAY_TEST0, BUFCE_ROW_CMT15.OPT_DELAY_TEST0, BUFCE_ROW_CMT16.OPT_DELAY_TEST0, BUFCE_ROW_CMT17.OPT_DELAY_TEST0, BUFCE_ROW_CMT21.OPT_DELAY_TEST0, BUFCE_ROW_CMT22.OPT_DELAY_TEST0, BUFCE_ROW_CMT23.OPT_DELAY_TEST0
TCELL30:RCLK.IMUX.18	BUFCE_ROW_CMT0.OPT_DELAY_TEST1, BUFCE_ROW_CMT1.OPT_DELAY_TEST1, BUFCE_ROW_CMT2.OPT_DELAY_TEST1, BUFCE_ROW_CMT6.OPT_DELAY_TEST1, BUFCE_ROW_CMT7.OPT_DELAY_TEST1, BUFCE_ROW_CMT8.OPT_DELAY_TEST1, BUFCE_ROW_CMT12.OPT_DELAY_TEST1, BUFCE_ROW_CMT13.OPT_DELAY_TEST1, BUFCE_ROW_CMT14.OPT_DELAY_TEST1, BUFCE_ROW_CMT18.OPT_DELAY_TEST1, BUFCE_ROW_CMT19.OPT_DELAY_TEST1, BUFCE_ROW_CMT20.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.19	BUFCE_ROW_CMT3.OPT_DELAY_TEST1, BUFCE_ROW_CMT4.OPT_DELAY_TEST1, BUFCE_ROW_CMT5.OPT_DELAY_TEST1, BUFCE_ROW_CMT9.OPT_DELAY_TEST1, BUFCE_ROW_CMT10.OPT_DELAY_TEST1, BUFCE_ROW_CMT11.OPT_DELAY_TEST1, BUFCE_ROW_CMT15.OPT_DELAY_TEST1, BUFCE_ROW_CMT16.OPT_DELAY_TEST1, BUFCE_ROW_CMT17.OPT_DELAY_TEST1, BUFCE_ROW_CMT21.OPT_DELAY_TEST1, BUFCE_ROW_CMT22.OPT_DELAY_TEST1, BUFCE_ROW_CMT23.OPT_DELAY_TEST1
TCELL30:RCLK.IMUX.20	BUFCE_ROW_CMT0.OPT_DELAY_TEST2, BUFCE_ROW_CMT1.OPT_DELAY_TEST2, BUFCE_ROW_CMT2.OPT_DELAY_TEST2, BUFCE_ROW_CMT6.OPT_DELAY_TEST2, BUFCE_ROW_CMT7.OPT_DELAY_TEST2, BUFCE_ROW_CMT8.OPT_DELAY_TEST2, BUFCE_ROW_CMT12.OPT_DELAY_TEST2, BUFCE_ROW_CMT13.OPT_DELAY_TEST2, BUFCE_ROW_CMT14.OPT_DELAY_TEST2, BUFCE_ROW_CMT18.OPT_DELAY_TEST2, BUFCE_ROW_CMT19.OPT_DELAY_TEST2, BUFCE_ROW_CMT20.OPT_DELAY_TEST2
TCELL30:RCLK.IMUX.21	BUFCE_ROW_CMT3.OPT_DELAY_TEST2, BUFCE_ROW_CMT4.OPT_DELAY_TEST2, BUFCE_ROW_CMT5.OPT_DELAY_TEST2, BUFCE_ROW_CMT9.OPT_DELAY_TEST2, BUFCE_ROW_CMT10.OPT_DELAY_TEST2, BUFCE_ROW_CMT11.OPT_DELAY_TEST2, BUFCE_ROW_CMT15.OPT_DELAY_TEST2, BUFCE_ROW_CMT16.OPT_DELAY_TEST2, BUFCE_ROW_CMT17.OPT_DELAY_TEST2, BUFCE_ROW_CMT21.OPT_DELAY_TEST2, BUFCE_ROW_CMT22.OPT_DELAY_TEST2, BUFCE_ROW_CMT23.OPT_DELAY_TEST2
TCELL31:IMUX.IMUX.0	BUFGCE_DIV3.RST_PRE_OPTINV
TCELL31:IMUX.IMUX.17	BUFGCE17.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.18	BUFGCE18.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.19	BUFGCE19.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.20	BUFGCE20.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.21	BUFGCE21.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.22	BUFGCE22.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.23	BUFGCE23.CE_PRE_OPTINV
TCELL31:IMUX.IMUX.24	BUFGCE0.CLK_IN_CKINT
TCELL31:IMUX.IMUX.25	BUFGCE1.CLK_IN_CKINT
TCELL31:IMUX.IMUX.26	BUFGCE2.CLK_IN_CKINT
TCELL31:IMUX.IMUX.27	BUFGCE3.CLK_IN_CKINT
TCELL31:IMUX.IMUX.28	BUFGCE4.CLK_IN_CKINT
TCELL31:IMUX.IMUX.29	BUFGCE5.CLK_IN_CKINT
TCELL31:IMUX.IMUX.30	BUFGCE6.CLK_IN_CKINT
TCELL31:IMUX.IMUX.31	BUFGCE7.CLK_IN_CKINT
TCELL31:IMUX.IMUX.32	BUFGCE8.CLK_IN_CKINT
TCELL31:IMUX.IMUX.33	BUFGCE9.CLK_IN_CKINT
TCELL31:IMUX.IMUX.34	BUFGCE10.CLK_IN_CKINT
TCELL31:IMUX.IMUX.35	BUFGCE11.CLK_IN_CKINT
TCELL31:IMUX.IMUX.36	BUFGCE12.CLK_IN_CKINT
TCELL31:IMUX.IMUX.37	BUFGCE13.CLK_IN_CKINT
TCELL31:IMUX.IMUX.38	BUFGCE14.CLK_IN_CKINT
TCELL31:IMUX.IMUX.39	BUFGCE15.CLK_IN_CKINT
TCELL31:IMUX.IMUX.40	BUFGCE16.CLK_IN_CKINT
TCELL31:IMUX.IMUX.41	BUFGCE17.CLK_IN_CKINT
TCELL31:IMUX.IMUX.42	BUFGCE18.CLK_IN_CKINT
TCELL31:IMUX.IMUX.43	BUFGCE19.CLK_IN_CKINT
TCELL31:IMUX.IMUX.44	BUFGCE20.CLK_IN_CKINT
TCELL31:IMUX.IMUX.45	BUFGCE21.CLK_IN_CKINT
TCELL31:IMUX.IMUX.46	BUFGCE22.CLK_IN_CKINT
TCELL31:IMUX.IMUX.47	BUFGCE23.CLK_IN_CKINT
TCELL32:IMUX.IMUX.0	ABUS_SWITCH_CMT.TEST_ANALOGBUS_SEL_B
TCELL41:IMUX.BYP.0	MMCM.TESTIN28
TCELL41:IMUX.BYP.1	MMCM.TESTIN29
TCELL41:IMUX.BYP.2	MMCM.TESTIN30
TCELL41:IMUX.BYP.3	MMCM.TESTIN31
TCELL41:IMUX.IMUX.0	MMCM.CLKINSEL
TCELL42:IMUX.BYP.0	MMCM.TESTIN24
TCELL42:IMUX.BYP.1	MMCM.TESTIN25
TCELL42:IMUX.BYP.2	MMCM.TESTIN26
TCELL42:IMUX.BYP.3	MMCM.TESTIN27
TCELL43:OUT.0	MMCM.TESTOUT14
TCELL43:OUT.1	MMCM.TESTOUT15
TCELL43:IMUX.BYP.0	MMCM.TESTIN20
TCELL43:IMUX.BYP.1	MMCM.TESTIN21
TCELL43:IMUX.BYP.2	MMCM.TESTIN22
TCELL43:IMUX.BYP.3	MMCM.TESTIN23
TCELL44:OUT.0	MMCM.TESTOUT11
TCELL44:OUT.1	MMCM.TESTOUT12
TCELL44:OUT.2	MMCM.TESTOUT13
TCELL44:IMUX.BYP.0	MMCM.TESTIN16
TCELL44:IMUX.BYP.1	MMCM.TESTIN17
TCELL44:IMUX.BYP.2	MMCM.TESTIN18
TCELL44:IMUX.BYP.3	MMCM.TESTIN19
TCELL45:OUT.0	MMCM.TESTOUT8
TCELL45:OUT.1	MMCM.TESTOUT9
TCELL45:OUT.2	MMCM.TESTOUT10
TCELL45:IMUX.BYP.0	MMCM.TESTIN12
TCELL45:IMUX.BYP.1	MMCM.TESTIN13
TCELL45:IMUX.BYP.2	MMCM.TESTIN14
TCELL45:IMUX.BYP.3	MMCM.TESTIN15
TCELL46:OUT.0	MMCM.TESTOUT5
TCELL46:OUT.1	MMCM.TESTOUT6
TCELL46:OUT.2	MMCM.TESTOUT7
TCELL46:IMUX.BYP.0	MMCM.TESTIN8
TCELL46:IMUX.BYP.1	MMCM.TESTIN9
TCELL46:IMUX.BYP.2	MMCM.TESTIN10
TCELL46:IMUX.BYP.3	MMCM.TESTIN11
TCELL47:OUT.0	MMCM.TESTOUT2
TCELL47:OUT.1	MMCM.TESTOUT3
TCELL47:OUT.2	MMCM.TESTOUT4
TCELL47:IMUX.BYP.0	MMCM.TESTIN4
TCELL47:IMUX.BYP.1	MMCM.TESTIN5
TCELL47:IMUX.BYP.2	MMCM.TESTIN6
TCELL47:IMUX.BYP.3	MMCM.TESTIN7
TCELL47:IMUX.IMUX.0	MMCM.SCANMODEB
TCELL48:OUT.0	MMCM.DOUT15
TCELL48:OUT.1	MMCM.TESTOUT0
TCELL48:OUT.2	MMCM.TESTOUT1
TCELL48:IMUX.BYP.0	MMCM.TESTIN0
TCELL48:IMUX.BYP.1	MMCM.TESTIN1
TCELL48:IMUX.BYP.2	MMCM.TESTIN2
TCELL48:IMUX.BYP.3	MMCM.TESTIN3
TCELL48:IMUX.IMUX.0	MMCM.SCANENB
TCELL49:OUT.0	MMCM.DOUT12
TCELL49:OUT.1	MMCM.DOUT13
TCELL49:OUT.2	MMCM.DOUT14
TCELL49:IMUX.BYP.0	MMCM.DADDR4
TCELL49:IMUX.BYP.1	MMCM.DADDR5
TCELL49:IMUX.BYP.2	MMCM.DADDR6
TCELL49:IMUX.IMUX.0	MMCM.SCANIN
TCELL50:OUT.0	MMCM.DOUT9
TCELL50:OUT.1	MMCM.DOUT10
TCELL50:OUT.2	MMCM.DOUT11
TCELL50:IMUX.BYP.0	MMCM.DADDR0
TCELL50:IMUX.BYP.1	MMCM.DADDR1
TCELL50:IMUX.BYP.2	MMCM.DADDR2
TCELL50:IMUX.BYP.3	MMCM.DADDR3
TCELL50:IMUX.IMUX.0	MMCM.CDDCREQ
TCELL51:OUT.0	MMCM.DOUT6
TCELL51:OUT.1	MMCM.DOUT7
TCELL51:OUT.2	MMCM.DOUT8
TCELL51:IMUX.BYP.0	MMCM.DI12
TCELL51:IMUX.BYP.1	MMCM.DI13
TCELL51:IMUX.BYP.2	MMCM.DI14
TCELL51:IMUX.BYP.3	MMCM.DI15
TCELL51:IMUX.IMUX.0	MMCM.DWE
TCELL52:OUT.0	MMCM.DOUT3
TCELL52:OUT.1	MMCM.DOUT4
TCELL52:OUT.2	MMCM.DOUT5
TCELL52:IMUX.CTRL.0	MMCM.DCLK
TCELL52:IMUX.BYP.0	MMCM.DI8
TCELL52:IMUX.BYP.1	MMCM.DI9
TCELL52:IMUX.BYP.2	MMCM.DI10
TCELL52:IMUX.BYP.3	MMCM.DI11
TCELL52:IMUX.IMUX.0	MMCM.DEN
TCELL53:OUT.0	MMCM.DOUT0
TCELL53:OUT.1	MMCM.DOUT1
TCELL53:OUT.2	MMCM.DOUT2
TCELL53:IMUX.CTRL.0	MMCM.PSCLK
TCELL53:IMUX.BYP.0	MMCM.DI4
TCELL53:IMUX.BYP.1	MMCM.DI5
TCELL53:IMUX.BYP.2	MMCM.DI6
TCELL53:IMUX.BYP.3	MMCM.DI7
TCELL53:IMUX.IMUX.0	MMCM.PWRDWN
TCELL54:OUT.0	MMCM.LOCKED
TCELL54:OUT.1	MMCM.DRDY
TCELL54:OUT.2	MMCM.SCANOUT
TCELL54:IMUX.CTRL.0	MMCM.SCANCLK
TCELL54:IMUX.BYP.0	MMCM.DI0
TCELL54:IMUX.BYP.1	MMCM.DI1
TCELL54:IMUX.BYP.2	MMCM.DI2
TCELL54:IMUX.BYP.3	MMCM.DI3
TCELL54:IMUX.IMUX.0	MMCM.RST
TCELL55:OUT.0	MMCM.CLKFBSTOPPED
TCELL55:OUT.1	MMCM.CLKINSTOPPED
TCELL55:OUT.2	MMCM.PSDONE
TCELL55:IMUX.IMUX.0	MMCM.PSINCDEC
TCELL56:OUT.0	MMCM.CDDCDONE
TCELL56:IMUX.IMUX.0	MMCM.PSEN

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