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Clock vertical nodes

Tile RCLK_V_SINGLE.CLE

Cells: 1 IRIs: 0

Bel BUFCE_ROW_RCLK0

ultrascaleplus RCLK_V_SINGLE.CLE bel BUFCE_ROW_RCLK0
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.22
OPT_DELAY_TEST0inputRCLK.IMUX.16
OPT_DELAY_TEST1inputRCLK.IMUX.18
OPT_DELAY_TEST2inputRCLK.IMUX.20

Bel GCLK_TEST_BUF_RCLK0

ultrascaleplus RCLK_V_SINGLE.CLE bel GCLK_TEST_BUF_RCLK0
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_SINGLE.CLE bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_SINGLE.CLE bel wires
WirePins
RCLK.IMUX.16BUFCE_ROW_RCLK0.OPT_DELAY_TEST0
RCLK.IMUX.18BUFCE_ROW_RCLK0.OPT_DELAY_TEST1
RCLK.IMUX.20BUFCE_ROW_RCLK0.OPT_DELAY_TEST2
RCLK.IMUX.22BUFCE_ROW_RCLK0.CE_PRE_OPTINV

Tile RCLK_V_SINGLE.LAG

Cells: 1 IRIs: 0

Bel BUFCE_ROW_RCLK0

ultrascaleplus RCLK_V_SINGLE.LAG bel BUFCE_ROW_RCLK0
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.22
OPT_DELAY_TEST0inputRCLK.IMUX.16
OPT_DELAY_TEST1inputRCLK.IMUX.18
OPT_DELAY_TEST2inputRCLK.IMUX.20

Bel GCLK_TEST_BUF_RCLK0

ultrascaleplus RCLK_V_SINGLE.LAG bel GCLK_TEST_BUF_RCLK0
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_SINGLE.LAG bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_SINGLE.LAG bel wires
WirePins
RCLK.IMUX.16BUFCE_ROW_RCLK0.OPT_DELAY_TEST0
RCLK.IMUX.18BUFCE_ROW_RCLK0.OPT_DELAY_TEST1
RCLK.IMUX.20BUFCE_ROW_RCLK0.OPT_DELAY_TEST2
RCLK.IMUX.22BUFCE_ROW_RCLK0.CE_PRE_OPTINV

Tile RCLK_V_DOUBLE.DSP

Cells: 1 IRIs: 0

Bel BUFCE_ROW_RCLK0

ultrascaleplus RCLK_V_DOUBLE.DSP bel BUFCE_ROW_RCLK0
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.17
OPT_DELAY_TEST0inputRCLK.IMUX.16
OPT_DELAY_TEST1inputRCLK.IMUX.18
OPT_DELAY_TEST2inputRCLK.IMUX.20

Bel BUFCE_ROW_RCLK1

ultrascaleplus RCLK_V_DOUBLE.DSP bel BUFCE_ROW_RCLK1
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.19
OPT_DELAY_TEST0inputRCLK.IMUX.16
OPT_DELAY_TEST1inputRCLK.IMUX.18
OPT_DELAY_TEST2inputRCLK.IMUX.20

Bel GCLK_TEST_BUF_RCLK0

ultrascaleplus RCLK_V_DOUBLE.DSP bel GCLK_TEST_BUF_RCLK0
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK1

ultrascaleplus RCLK_V_DOUBLE.DSP bel GCLK_TEST_BUF_RCLK1
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_DOUBLE.DSP bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_DOUBLE.DSP bel wires
WirePins
RCLK.IMUX.16BUFCE_ROW_RCLK0.OPT_DELAY_TEST0, BUFCE_ROW_RCLK1.OPT_DELAY_TEST0
RCLK.IMUX.17BUFCE_ROW_RCLK0.CE_PRE_OPTINV
RCLK.IMUX.18BUFCE_ROW_RCLK0.OPT_DELAY_TEST1, BUFCE_ROW_RCLK1.OPT_DELAY_TEST1
RCLK.IMUX.19BUFCE_ROW_RCLK1.CE_PRE_OPTINV
RCLK.IMUX.20BUFCE_ROW_RCLK0.OPT_DELAY_TEST2, BUFCE_ROW_RCLK1.OPT_DELAY_TEST2

Tile RCLK_V_QUAD.BRAM

Cells: 1 IRIs: 0

Bel BUFCE_ROW_RCLK0

ultrascaleplus RCLK_V_QUAD.BRAM bel BUFCE_ROW_RCLK0
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.16
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK1

ultrascaleplus RCLK_V_QUAD.BRAM bel BUFCE_ROW_RCLK1
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.18
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK2

ultrascaleplus RCLK_V_QUAD.BRAM bel BUFCE_ROW_RCLK2
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.20
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK3

ultrascaleplus RCLK_V_QUAD.BRAM bel BUFCE_ROW_RCLK3
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.22
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel GCLK_TEST_BUF_RCLK0

ultrascaleplus RCLK_V_QUAD.BRAM bel GCLK_TEST_BUF_RCLK0
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK1

ultrascaleplus RCLK_V_QUAD.BRAM bel GCLK_TEST_BUF_RCLK1
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK2

ultrascaleplus RCLK_V_QUAD.BRAM bel GCLK_TEST_BUF_RCLK2
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK3

ultrascaleplus RCLK_V_QUAD.BRAM bel GCLK_TEST_BUF_RCLK3
PinDirectionWires

Bel VBUS_SWITCH0

ultrascaleplus RCLK_V_QUAD.BRAM bel VBUS_SWITCH0
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VBUS_SWITCH1

ultrascaleplus RCLK_V_QUAD.BRAM bel VBUS_SWITCH1
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VBUS_SWITCH2

ultrascaleplus RCLK_V_QUAD.BRAM bel VBUS_SWITCH2
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_QUAD.BRAM bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_QUAD.BRAM bel wires
WirePins
RCLK.IMUX.16BUFCE_ROW_RCLK0.CE_PRE_OPTINV
RCLK.IMUX.17BUFCE_ROW_RCLK0.OPT_DELAY_TEST0, BUFCE_ROW_RCLK1.OPT_DELAY_TEST0, BUFCE_ROW_RCLK2.OPT_DELAY_TEST0, BUFCE_ROW_RCLK3.OPT_DELAY_TEST0
RCLK.IMUX.18BUFCE_ROW_RCLK1.CE_PRE_OPTINV
RCLK.IMUX.19BUFCE_ROW_RCLK0.OPT_DELAY_TEST1, BUFCE_ROW_RCLK1.OPT_DELAY_TEST1, BUFCE_ROW_RCLK2.OPT_DELAY_TEST1, BUFCE_ROW_RCLK3.OPT_DELAY_TEST1
RCLK.IMUX.20BUFCE_ROW_RCLK2.CE_PRE_OPTINV
RCLK.IMUX.21BUFCE_ROW_RCLK0.OPT_DELAY_TEST2, BUFCE_ROW_RCLK1.OPT_DELAY_TEST2, BUFCE_ROW_RCLK2.OPT_DELAY_TEST2, BUFCE_ROW_RCLK3.OPT_DELAY_TEST2
RCLK.IMUX.22BUFCE_ROW_RCLK3.CE_PRE_OPTINV
RCLK.IMUX.23VBUS_SWITCH0.TEST_ANALOGBUS_SEL_B, VBUS_SWITCH1.TEST_ANALOGBUS_SEL_B, VBUS_SWITCH2.TEST_ANALOGBUS_SEL_B

Tile RCLK_V_QUAD.URAM

Cells: 1 IRIs: 0

Bel BUFCE_ROW_RCLK0

ultrascaleplus RCLK_V_QUAD.URAM bel BUFCE_ROW_RCLK0
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.16
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK1

ultrascaleplus RCLK_V_QUAD.URAM bel BUFCE_ROW_RCLK1
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.18
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK2

ultrascaleplus RCLK_V_QUAD.URAM bel BUFCE_ROW_RCLK2
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.20
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel BUFCE_ROW_RCLK3

ultrascaleplus RCLK_V_QUAD.URAM bel BUFCE_ROW_RCLK3
PinDirectionWires
CE_PRE_OPTINVinputRCLK.IMUX.22
OPT_DELAY_TEST0inputRCLK.IMUX.17
OPT_DELAY_TEST1inputRCLK.IMUX.19
OPT_DELAY_TEST2inputRCLK.IMUX.21

Bel GCLK_TEST_BUF_RCLK0

ultrascaleplus RCLK_V_QUAD.URAM bel GCLK_TEST_BUF_RCLK0
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK1

ultrascaleplus RCLK_V_QUAD.URAM bel GCLK_TEST_BUF_RCLK1
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK2

ultrascaleplus RCLK_V_QUAD.URAM bel GCLK_TEST_BUF_RCLK2
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK3

ultrascaleplus RCLK_V_QUAD.URAM bel GCLK_TEST_BUF_RCLK3
PinDirectionWires

Bel VBUS_SWITCH0

ultrascaleplus RCLK_V_QUAD.URAM bel VBUS_SWITCH0
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VBUS_SWITCH1

ultrascaleplus RCLK_V_QUAD.URAM bel VBUS_SWITCH1
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VBUS_SWITCH2

ultrascaleplus RCLK_V_QUAD.URAM bel VBUS_SWITCH2
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputRCLK.IMUX.23

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_QUAD.URAM bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_QUAD.URAM bel wires
WirePins
RCLK.IMUX.16BUFCE_ROW_RCLK0.CE_PRE_OPTINV
RCLK.IMUX.17BUFCE_ROW_RCLK0.OPT_DELAY_TEST0, BUFCE_ROW_RCLK1.OPT_DELAY_TEST0, BUFCE_ROW_RCLK2.OPT_DELAY_TEST0, BUFCE_ROW_RCLK3.OPT_DELAY_TEST0
RCLK.IMUX.18BUFCE_ROW_RCLK1.CE_PRE_OPTINV
RCLK.IMUX.19BUFCE_ROW_RCLK0.OPT_DELAY_TEST1, BUFCE_ROW_RCLK1.OPT_DELAY_TEST1, BUFCE_ROW_RCLK2.OPT_DELAY_TEST1, BUFCE_ROW_RCLK3.OPT_DELAY_TEST1
RCLK.IMUX.20BUFCE_ROW_RCLK2.CE_PRE_OPTINV
RCLK.IMUX.21BUFCE_ROW_RCLK0.OPT_DELAY_TEST2, BUFCE_ROW_RCLK1.OPT_DELAY_TEST2, BUFCE_ROW_RCLK2.OPT_DELAY_TEST2, BUFCE_ROW_RCLK3.OPT_DELAY_TEST2
RCLK.IMUX.22BUFCE_ROW_RCLK3.CE_PRE_OPTINV
RCLK.IMUX.23VBUS_SWITCH0.TEST_ANALOGBUS_SEL_B, VBUS_SWITCH1.TEST_ANALOGBUS_SEL_B, VBUS_SWITCH2.TEST_ANALOGBUS_SEL_B