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Clock vertical nodes

Tile RCLK_V_SINGLE_CLE

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascaleplus RCLK_V_SINGLE_CLE bel BUFCE_ROW_RCLK[0]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[22]
OPT_DELAY_TEST0inputIMUX_RCLK[16]
OPT_DELAY_TEST1inputIMUX_RCLK[18]
OPT_DELAY_TEST2inputIMUX_RCLK[20]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascaleplus RCLK_V_SINGLE_CLE bel GCLK_TEST_BUF_RCLK[0]
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_SINGLE_CLE bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_SINGLE_CLE bel wires
WirePins
IMUX_RCLK[16]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0
IMUX_RCLK[18]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1
IMUX_RCLK[20]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2
IMUX_RCLK[22]BUFCE_ROW_RCLK[0].CE_PRE_OPTINV

Tile RCLK_V_SINGLE_LAG

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascaleplus RCLK_V_SINGLE_LAG bel BUFCE_ROW_RCLK[0]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[22]
OPT_DELAY_TEST0inputIMUX_RCLK[16]
OPT_DELAY_TEST1inputIMUX_RCLK[18]
OPT_DELAY_TEST2inputIMUX_RCLK[20]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascaleplus RCLK_V_SINGLE_LAG bel GCLK_TEST_BUF_RCLK[0]
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_SINGLE_LAG bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_SINGLE_LAG bel wires
WirePins
IMUX_RCLK[16]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0
IMUX_RCLK[18]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1
IMUX_RCLK[20]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2
IMUX_RCLK[22]BUFCE_ROW_RCLK[0].CE_PRE_OPTINV

Tile RCLK_V_DOUBLE_DSP

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascaleplus RCLK_V_DOUBLE_DSP bel BUFCE_ROW_RCLK[0]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[17]
OPT_DELAY_TEST0inputIMUX_RCLK[16]
OPT_DELAY_TEST1inputIMUX_RCLK[18]
OPT_DELAY_TEST2inputIMUX_RCLK[20]

Bel BUFCE_ROW_RCLK[1]

ultrascaleplus RCLK_V_DOUBLE_DSP bel BUFCE_ROW_RCLK[1]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[19]
OPT_DELAY_TEST0inputIMUX_RCLK[16]
OPT_DELAY_TEST1inputIMUX_RCLK[18]
OPT_DELAY_TEST2inputIMUX_RCLK[20]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascaleplus RCLK_V_DOUBLE_DSP bel GCLK_TEST_BUF_RCLK[0]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[1]

ultrascaleplus RCLK_V_DOUBLE_DSP bel GCLK_TEST_BUF_RCLK[1]
PinDirectionWires

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_DOUBLE_DSP bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_DOUBLE_DSP bel wires
WirePins
IMUX_RCLK[16]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST0
IMUX_RCLK[17]BUFCE_ROW_RCLK[0].CE_PRE_OPTINV
IMUX_RCLK[18]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST1
IMUX_RCLK[19]BUFCE_ROW_RCLK[1].CE_PRE_OPTINV
IMUX_RCLK[20]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST2

Tile RCLK_V_QUAD_BRAM

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascaleplus RCLK_V_QUAD_BRAM bel BUFCE_ROW_RCLK[0]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[16]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[1]

ultrascaleplus RCLK_V_QUAD_BRAM bel BUFCE_ROW_RCLK[1]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[18]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[2]

ultrascaleplus RCLK_V_QUAD_BRAM bel BUFCE_ROW_RCLK[2]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[20]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[3]

ultrascaleplus RCLK_V_QUAD_BRAM bel BUFCE_ROW_RCLK[3]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[22]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascaleplus RCLK_V_QUAD_BRAM bel GCLK_TEST_BUF_RCLK[0]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[1]

ultrascaleplus RCLK_V_QUAD_BRAM bel GCLK_TEST_BUF_RCLK[1]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[2]

ultrascaleplus RCLK_V_QUAD_BRAM bel GCLK_TEST_BUF_RCLK[2]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[3]

ultrascaleplus RCLK_V_QUAD_BRAM bel GCLK_TEST_BUF_RCLK[3]
PinDirectionWires

Bel VBUS_SWITCH[0]

ultrascaleplus RCLK_V_QUAD_BRAM bel VBUS_SWITCH[0]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VBUS_SWITCH[1]

ultrascaleplus RCLK_V_QUAD_BRAM bel VBUS_SWITCH[1]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VBUS_SWITCH[2]

ultrascaleplus RCLK_V_QUAD_BRAM bel VBUS_SWITCH[2]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_QUAD_BRAM bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_QUAD_BRAM bel wires
WirePins
IMUX_RCLK[16]BUFCE_ROW_RCLK[0].CE_PRE_OPTINV
IMUX_RCLK[17]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST0
IMUX_RCLK[18]BUFCE_ROW_RCLK[1].CE_PRE_OPTINV
IMUX_RCLK[19]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST1
IMUX_RCLK[20]BUFCE_ROW_RCLK[2].CE_PRE_OPTINV
IMUX_RCLK[21]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST2
IMUX_RCLK[22]BUFCE_ROW_RCLK[3].CE_PRE_OPTINV
IMUX_RCLK[23]VBUS_SWITCH[0].TEST_ANALOGBUS_SEL_B, VBUS_SWITCH[1].TEST_ANALOGBUS_SEL_B, VBUS_SWITCH[2].TEST_ANALOGBUS_SEL_B

Tile RCLK_V_QUAD_URAM

Cells: 1

Bel BUFCE_ROW_RCLK[0]

ultrascaleplus RCLK_V_QUAD_URAM bel BUFCE_ROW_RCLK[0]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[16]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[1]

ultrascaleplus RCLK_V_QUAD_URAM bel BUFCE_ROW_RCLK[1]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[18]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[2]

ultrascaleplus RCLK_V_QUAD_URAM bel BUFCE_ROW_RCLK[2]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[20]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel BUFCE_ROW_RCLK[3]

ultrascaleplus RCLK_V_QUAD_URAM bel BUFCE_ROW_RCLK[3]
PinDirectionWires
CE_PRE_OPTINVinputIMUX_RCLK[22]
OPT_DELAY_TEST0inputIMUX_RCLK[17]
OPT_DELAY_TEST1inputIMUX_RCLK[19]
OPT_DELAY_TEST2inputIMUX_RCLK[21]

Bel GCLK_TEST_BUF_RCLK[0]

ultrascaleplus RCLK_V_QUAD_URAM bel GCLK_TEST_BUF_RCLK[0]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[1]

ultrascaleplus RCLK_V_QUAD_URAM bel GCLK_TEST_BUF_RCLK[1]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[2]

ultrascaleplus RCLK_V_QUAD_URAM bel GCLK_TEST_BUF_RCLK[2]
PinDirectionWires

Bel GCLK_TEST_BUF_RCLK[3]

ultrascaleplus RCLK_V_QUAD_URAM bel GCLK_TEST_BUF_RCLK[3]
PinDirectionWires

Bel VBUS_SWITCH[0]

ultrascaleplus RCLK_V_QUAD_URAM bel VBUS_SWITCH[0]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VBUS_SWITCH[1]

ultrascaleplus RCLK_V_QUAD_URAM bel VBUS_SWITCH[1]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VBUS_SWITCH[2]

ultrascaleplus RCLK_V_QUAD_URAM bel VBUS_SWITCH[2]
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputIMUX_RCLK[23]

Bel VCC_RCLK_V

ultrascaleplus RCLK_V_QUAD_URAM bel VCC_RCLK_V
PinDirectionWires

Bel wires

ultrascaleplus RCLK_V_QUAD_URAM bel wires
WirePins
IMUX_RCLK[16]BUFCE_ROW_RCLK[0].CE_PRE_OPTINV
IMUX_RCLK[17]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST0, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST0
IMUX_RCLK[18]BUFCE_ROW_RCLK[1].CE_PRE_OPTINV
IMUX_RCLK[19]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST1, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST1
IMUX_RCLK[20]BUFCE_ROW_RCLK[2].CE_PRE_OPTINV
IMUX_RCLK[21]BUFCE_ROW_RCLK[0].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[1].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[2].OPT_DELAY_TEST2, BUFCE_ROW_RCLK[3].OPT_DELAY_TEST2
IMUX_RCLK[22]BUFCE_ROW_RCLK[3].CE_PRE_OPTINV
IMUX_RCLK[23]VBUS_SWITCH[0].TEST_ANALOGBUS_SEL_B, VBUS_SWITCH[1].TEST_ANALOGBUS_SEL_B, VBUS_SWITCH[2].TEST_ANALOGBUS_SEL_B