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GTM transceivers

Tile GTM

Cells: 60 IRIs: 0

Bel BUFG_GT0

ultrascaleplus GTM bel BUFG_GT0
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.1
DIV0inputTCELL27:IMUX.IMUX.0
DIV1inputTCELL27:IMUX.IMUX.16
DIV2inputTCELL27:IMUX.IMUX.18
RSTMASKinputTCELL27:IMUX.IMUX.23

Bel BUFG_GT1

ultrascaleplus GTM bel BUFG_GT1
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.3
DIV0inputTCELL27:IMUX.IMUX.19
DIV1inputTCELL27:IMUX.IMUX.2
DIV2inputTCELL27:IMUX.IMUX.21
RSTMASKinputTCELL27:IMUX.IMUX.39

Bel BUFG_GT2

ultrascaleplus GTM bel BUFG_GT2
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.26
DIV0inputTCELL27:IMUX.IMUX.22
DIV1inputTCELL27:IMUX.IMUX.4
DIV2inputTCELL27:IMUX.IMUX.24
RSTMASKinputTCELL28:IMUX.IMUX.16

Bel BUFG_GT3

ultrascaleplus GTM bel BUFG_GT3
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.31
DIV0inputTCELL27:IMUX.IMUX.27
DIV1inputTCELL27:IMUX.IMUX.6
DIV2inputTCELL27:IMUX.IMUX.28
RSTMASKinputTCELL28:IMUX.IMUX.18

Bel BUFG_GT4

ultrascaleplus GTM bel BUFG_GT4
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.10
DIV0inputTCELL27:IMUX.IMUX.7
DIV1inputTCELL27:IMUX.IMUX.30
DIV2inputTCELL27:IMUX.IMUX.32
RSTMASKinputTCELL28:IMUX.IMUX.3

Bel BUFG_GT5

ultrascaleplus GTM bel BUFG_GT5
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.41
DIV0inputTCELL27:IMUX.IMUX.33
DIV1inputTCELL27:IMUX.IMUX.34
DIV2inputTCELL27:IMUX.IMUX.35
RSTMASKinputTCELL28:IMUX.IMUX.24

Bel BUFG_GT6

ultrascaleplus GTM bel BUFG_GT6
PinDirectionWires
CEMASKinputTCELL27:IMUX.IMUX.45
DIV0inputTCELL27:IMUX.IMUX.11
DIV1inputTCELL27:IMUX.IMUX.38
DIV2inputTCELL27:IMUX.IMUX.12
RSTMASKinputTCELL28:IMUX.IMUX.27

Bel BUFG_GT7

ultrascaleplus GTM bel BUFG_GT7
PinDirectionWires
CEMASKinputTCELL28:IMUX.IMUX.31
DIV0inputTCELL27:IMUX.IMUX.40
DIV1inputTCELL27:IMUX.IMUX.42
DIV2inputTCELL27:IMUX.IMUX.43
RSTMASKinputTCELL28:IMUX.IMUX.7

Bel BUFG_GT8

ultrascaleplus GTM bel BUFG_GT8
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.0
DIV0inputTCELL27:IMUX.IMUX.14
DIV1inputTCELL27:IMUX.IMUX.44
DIV2inputTCELL27:IMUX.IMUX.46
RSTMASKinputTCELL28:IMUX.IMUX.34

Bel BUFG_GT9

ultrascaleplus GTM bel BUFG_GT9
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.1
DIV0inputTCELL28:IMUX.IMUX.0
DIV1inputTCELL28:IMUX.IMUX.1
DIV2inputTCELL28:IMUX.IMUX.2
RSTMASKinputTCELL28:IMUX.IMUX.37

Bel BUFG_GT10

ultrascaleplus GTM bel BUFG_GT10
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.2
DIV0inputTCELL28:IMUX.IMUX.21
DIV1inputTCELL28:IMUX.IMUX.4
DIV2inputTCELL28:IMUX.IMUX.5
RSTMASKinputTCELL28:IMUX.IMUX.12

Bel BUFG_GT11

ultrascaleplus GTM bel BUFG_GT11
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.23
DIV0inputTCELL28:IMUX.IMUX.6
DIV1inputTCELL28:IMUX.IMUX.28
DIV2inputTCELL28:IMUX.IMUX.33
RSTMASKinputTCELL28:IMUX.IMUX.43

Bel BUFG_GT12

ultrascaleplus GTM bel BUFG_GT12
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.25
DIV0inputTCELL28:IMUX.IMUX.35
DIV1inputTCELL28:IMUX.IMUX.36
DIV2inputTCELL28:IMUX.IMUX.11
RSTMASKinputTCELL28:IMUX.IMUX.15

Bel BUFG_GT13

ultrascaleplus GTM bel BUFG_GT13
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.26
DIV0inputTCELL28:IMUX.IMUX.40
DIV1inputTCELL28:IMUX.IMUX.42
DIV2inputTCELL28:IMUX.IMUX.44
RSTMASKinputTCELL29:IMUX.IMUX.17

Bel BUFG_GT14

ultrascaleplus GTM bel BUFG_GT14
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.29
DIV0inputTCELL28:IMUX.IMUX.45
DIV1inputTCELL29:IMUX.IMUX.16
DIV2inputTCELL29:IMUX.IMUX.19
RSTMASKinputTCELL29:IMUX.IMUX.21

Bel BUFG_GT15

ultrascaleplus GTM bel BUFG_GT15
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.9
DIV0inputTCELL29:IMUX.IMUX.22
DIV1inputTCELL29:IMUX.IMUX.5
DIV2inputTCELL29:IMUX.IMUX.28
RSTMASKinputTCELL29:IMUX.IMUX.4

Bel BUFG_GT16

ultrascaleplus GTM bel BUFG_GT16
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.37
DIV0inputTCELL29:IMUX.IMUX.34
DIV1inputTCELL29:IMUX.IMUX.36
DIV2inputTCELL29:IMUX.IMUX.12
RSTMASKinputTCELL29:IMUX.IMUX.27

Bel BUFG_GT17

ultrascaleplus GTM bel BUFG_GT17
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.11
DIV0inputTCELL29:IMUX.IMUX.43
DIV1inputTCELL29:IMUX.IMUX.46
DIV2inputTCELL30:IMUX.IMUX.17
RSTMASKinputTCELL29:IMUX.IMUX.33

Bel BUFG_GT18

ultrascaleplus GTM bel BUFG_GT18
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.40
DIV0inputTCELL30:IMUX.IMUX.22
DIV1inputTCELL30:IMUX.IMUX.5
DIV2inputTCELL30:IMUX.IMUX.35
RSTMASKinputTCELL29:IMUX.IMUX.10

Bel BUFG_GT19

ultrascaleplus GTM bel BUFG_GT19
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.14
DIV0inputTCELL30:IMUX.IMUX.11
DIV1inputTCELL30:IMUX.IMUX.41
DIV2inputTCELL30:IMUX.IMUX.46
RSTMASKinputTCELL29:IMUX.IMUX.39

Bel BUFG_GT20

ultrascaleplus GTM bel BUFG_GT20
PinDirectionWires
CEMASKinputTCELL29:IMUX.IMUX.45
DIV0inputTCELL32:IMUX.IMUX.16
DIV1inputTCELL32:IMUX.IMUX.18
DIV2inputTCELL32:IMUX.IMUX.21
RSTMASKinputTCELL29:IMUX.IMUX.13

Bel BUFG_GT21

ultrascaleplus GTM bel BUFG_GT21
PinDirectionWires
CEMASKinputTCELL30:IMUX.IMUX.33
DIV0inputTCELL32:IMUX.IMUX.24
DIV1inputTCELL32:IMUX.IMUX.27
DIV2inputTCELL32:IMUX.IMUX.29
RSTMASKinputTCELL29:IMUX.IMUX.15

Bel BUFG_GT22

ultrascaleplus GTM bel BUFG_GT22
PinDirectionWires
CEMASKinputTCELL32:IMUX.IMUX.23
DIV0inputTCELL32:IMUX.IMUX.32
DIV1inputTCELL32:IMUX.IMUX.35
DIV2inputTCELL32:IMUX.IMUX.11
RSTMASKinputTCELL30:IMUX.IMUX.32

Bel BUFG_GT23

ultrascaleplus GTM bel BUFG_GT23
PinDirectionWires
CEMASKinputTCELL32:IMUX.IMUX.39
DIV0inputTCELL32:IMUX.IMUX.40
DIV1inputTCELL32:IMUX.IMUX.43
DIV2inputTCELL32:IMUX.IMUX.15
RSTMASKinputTCELL32:IMUX.IMUX.8

Bel BUFG_GT_SYNC0

ultrascaleplus GTM bel BUFG_GT_SYNC0
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.17
RST_INinputTCELL27:IMUX.IMUX.8

Bel BUFG_GT_SYNC1

ultrascaleplus GTM bel BUFG_GT_SYNC1
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.20
RST_INinputTCELL28:IMUX.IMUX.20

Bel BUFG_GT_SYNC2

ultrascaleplus GTM bel BUFG_GT_SYNC2
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.25
RST_INinputTCELL28:IMUX.IMUX.30

Bel BUFG_GT_SYNC3

ultrascaleplus GTM bel BUFG_GT_SYNC3
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.29
RST_INinputTCELL28:IMUX.IMUX.13

Bel BUFG_GT_SYNC4

ultrascaleplus GTM bel BUFG_GT_SYNC4
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.9
RST_INinputTCELL29:IMUX.IMUX.20

Bel BUFG_GT_SYNC5

ultrascaleplus GTM bel BUFG_GT_SYNC5
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.37
RST_INinputTCELL29:IMUX.IMUX.30

Bel BUFG_GT_SYNC6

ultrascaleplus GTM bel BUFG_GT_SYNC6
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.13
RST_INinputTCELL29:IMUX.IMUX.42

Bel BUFG_GT_SYNC7

ultrascaleplus GTM bel BUFG_GT_SYNC7
PinDirectionWires
CE_INinputTCELL27:IMUX.IMUX.15
RST_INinputTCELL30:IMUX.IMUX.1

Bel BUFG_GT_SYNC8

ultrascaleplus GTM bel BUFG_GT_SYNC8
PinDirectionWires
CE_INinputTCELL28:IMUX.IMUX.8
RST_INinputTCELL30:IMUX.IMUX.4

Bel BUFG_GT_SYNC9

ultrascaleplus GTM bel BUFG_GT_SYNC9
PinDirectionWires
CE_INinputTCELL29:IMUX.IMUX.18
RST_INinputTCELL30:IMUX.IMUX.28

Bel BUFG_GT_SYNC10

ultrascaleplus GTM bel BUFG_GT_SYNC10
PinDirectionWires
CE_INinputTCELL29:IMUX.IMUX.24
RST_INinputTCELL30:IMUX.IMUX.38

Bel BUFG_GT_SYNC11

ultrascaleplus GTM bel BUFG_GT_SYNC11
PinDirectionWires
CE_INinputTCELL29:IMUX.IMUX.7
RST_INinputTCELL30:IMUX.IMUX.45

Bel BUFG_GT_SYNC12

ultrascaleplus GTM bel BUFG_GT_SYNC12
PinDirectionWires
CE_INinputTCELL29:IMUX.IMUX.38
RST_INinputTCELL31:IMUX.IMUX.20

Bel BUFG_GT_SYNC13

ultrascaleplus GTM bel BUFG_GT_SYNC13
PinDirectionWires
CE_INinputTCELL29:IMUX.IMUX.44
RST_INinputTCELL31:IMUX.IMUX.30

Bel BUFG_GT_SYNC14

ultrascaleplus GTM bel BUFG_GT_SYNC14
PinDirectionWires
CE_INinputTCELL30:IMUX.IMUX.30
CLK_INinputTCELL30:RCLK.IMUX.17
RST_INinputTCELL31:IMUX.IMUX.13

Bel ABUS_SWITCH_GT0

ultrascaleplus GTM bel ABUS_SWITCH_GT0
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputTCELL29:IMUX.IMUX.8

Bel ABUS_SWITCH_GT1

ultrascaleplus GTM bel ABUS_SWITCH_GT1
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputTCELL29:IMUX.IMUX.8

Bel ABUS_SWITCH_GT2

ultrascaleplus GTM bel ABUS_SWITCH_GT2
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputTCELL29:IMUX.IMUX.8

Bel ABUS_SWITCH_GT3

ultrascaleplus GTM bel ABUS_SWITCH_GT3
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputTCELL29:IMUX.IMUX.8

Bel ABUS_SWITCH_GT4

ultrascaleplus GTM bel ABUS_SWITCH_GT4
PinDirectionWires
TEST_ANALOGBUS_SEL_BinputTCELL30:IMUX.IMUX.8

Bel GTM_REFCLK

ultrascaleplus GTM bel GTM_REFCLK
PinDirectionWires

Bel GTM_DUAL

ultrascaleplus GTM bel GTM_DUAL
PinDirectionWires
AXIS_EYESCANRST_CH0_FSinputTCELL3:IMUX.IMUX.13
AXIS_EYESCANRST_CH1_FSinputTCELL56:IMUX.IMUX.21
AXIS_STREAMEN_CH0_FSinputTCELL13:IMUX.IMUX.8
AXIS_STREAMEN_CH1_FSinputTCELL46:IMUX.IMUX.31
AXIS_TDATA_CH0_SF0outputTCELL23:OUT.2
AXIS_TDATA_CH0_SF1outputTCELL23:OUT.18
AXIS_TDATA_CH0_SF10outputTCELL27:OUT.15
AXIS_TDATA_CH0_SF11outputTCELL27:OUT.0
AXIS_TDATA_CH0_SF12outputTCELL27:OUT.18
AXIS_TDATA_CH0_SF13outputTCELL27:OUT.4
AXIS_TDATA_CH0_SF14outputTCELL27:OUT.2
AXIS_TDATA_CH0_SF15outputTCELL27:OUT.5
AXIS_TDATA_CH0_SF16outputTCELL27:OUT.10
AXIS_TDATA_CH0_SF17outputTCELL27:OUT.14
AXIS_TDATA_CH0_SF18outputTCELL27:OUT.7
AXIS_TDATA_CH0_SF19outputTCELL27:OUT.16
AXIS_TDATA_CH0_SF2outputTCELL23:OUT.28
AXIS_TDATA_CH0_SF20outputTCELL28:OUT.11
AXIS_TDATA_CH0_SF21outputTCELL28:OUT.12
AXIS_TDATA_CH0_SF22outputTCELL28:OUT.23
AXIS_TDATA_CH0_SF23outputTCELL28:OUT.3
AXIS_TDATA_CH0_SF24outputTCELL29:OUT.11
AXIS_TDATA_CH0_SF25outputTCELL29:OUT.28
AXIS_TDATA_CH0_SF26outputTCELL29:OUT.0
AXIS_TDATA_CH0_SF27outputTCELL29:OUT.13
AXIS_TDATA_CH0_SF3outputTCELL23:OUT.24
AXIS_TDATA_CH0_SF4outputTCELL23:OUT.6
AXIS_TDATA_CH0_SF5outputTCELL23:OUT.20
AXIS_TDATA_CH0_SF6outputTCELL23:OUT.1
AXIS_TDATA_CH0_SF7outputTCELL23:OUT.8
AXIS_TDATA_CH0_SF8outputTCELL27:OUT.19
AXIS_TDATA_CH0_SF9outputTCELL27:OUT.11
AXIS_TDATA_CH1_SF0outputTCELL36:OUT.29
AXIS_TDATA_CH1_SF1outputTCELL36:OUT.13
AXIS_TDATA_CH1_SF10outputTCELL32:OUT.16
AXIS_TDATA_CH1_SF11outputTCELL32:OUT.31
AXIS_TDATA_CH1_SF12outputTCELL32:OUT.13
AXIS_TDATA_CH1_SF13outputTCELL32:OUT.27
AXIS_TDATA_CH1_SF14outputTCELL32:OUT.29
AXIS_TDATA_CH1_SF15outputTCELL32:OUT.26
AXIS_TDATA_CH1_SF16outputTCELL32:OUT.21
AXIS_TDATA_CH1_SF17outputTCELL32:OUT.17
AXIS_TDATA_CH1_SF18outputTCELL32:OUT.24
AXIS_TDATA_CH1_SF19outputTCELL32:OUT.15
AXIS_TDATA_CH1_SF2outputTCELL36:OUT.3
AXIS_TDATA_CH1_SF20outputTCELL31:OUT.20
AXIS_TDATA_CH1_SF21outputTCELL31:OUT.19
AXIS_TDATA_CH1_SF22outputTCELL31:OUT.8
AXIS_TDATA_CH1_SF23outputTCELL31:OUT.28
AXIS_TDATA_CH1_SF24outputTCELL30:OUT.20
AXIS_TDATA_CH1_SF25outputTCELL30:OUT.3
AXIS_TDATA_CH1_SF26outputTCELL30:OUT.31
AXIS_TDATA_CH1_SF27outputTCELL30:OUT.18
AXIS_TDATA_CH1_SF3outputTCELL36:OUT.7
AXIS_TDATA_CH1_SF4outputTCELL36:OUT.25
AXIS_TDATA_CH1_SF5outputTCELL36:OUT.11
AXIS_TDATA_CH1_SF6outputTCELL36:OUT.30
AXIS_TDATA_CH1_SF7outputTCELL36:OUT.23
AXIS_TDATA_CH1_SF8outputTCELL32:OUT.12
AXIS_TDATA_CH1_SF9outputTCELL32:OUT.20
AXIS_TLAST_CH0_SFoutputTCELL19:OUT.24
AXIS_TLAST_CH1_SFoutputTCELL40:OUT.7
AXIS_TREADY_CH0_FSinputTCELL17:IMUX.IMUX.2
AXIS_TREADY_CH1_FSinputTCELL42:IMUX.IMUX.43
AXIS_TVALID_CH0_SFoutputTCELL26:OUT.21
AXIS_TVALID_CH1_SFoutputTCELL33:OUT.10
BGBYPASSB_FSinputTCELL59:IMUX.IMUX.2
BGPWRDNB_FSinputTCELL59:IMUX.IMUX.5
BGRCALCTL_FS0inputTCELL58:IMUX.IMUX.18
BGRCALCTL_FS1inputTCELL58:IMUX.IMUX.25
BGRCALCTL_FS2inputTCELL58:IMUX.IMUX.31
BGRCALCTL_FS3inputTCELL58:IMUX.IMUX.11
BGRCALCTL_FS4inputTCELL58:IMUX.IMUX.14
BGRCALOVRDENB_FSinputTCELL59:IMUX.IMUX.32
BGTESTEN_FSinputTCELL58:IMUX.IMUX.32
BSR_SERIAL_CH0_FSinputTCELL14:IMUX.IMUX.12
BSR_SERIAL_CH1_FSinputTCELL45:IMUX.IMUX.23
CDR_EXHOLD_CH0_FSinputTCELL17:IMUX.IMUX.16
CDR_EXHOLD_CH1_FSinputTCELL42:IMUX.IMUX.46
CDR_FREQOS_CH0_FSinputTCELL21:IMUX.IMUX.19
CDR_FREQOS_CH1_FSinputTCELL38:IMUX.IMUX.14
CDR_INCPCTRL_CH0_FSinputTCELL17:IMUX.IMUX.10
CDR_INCPCTRL_CH1_FSinputTCELL42:IMUX.IMUX.27
CDR_OVWREN_CH0_FSinputTCELL22:IMUX.IMUX.24
CDR_OVWREN_CH1_FSinputTCELL37:IMUX.IMUX.38
CFGRESET_CH0_FSinputTCELL22:IMUX.IMUX.0
CFGRESET_CH1_FSinputTCELL37:IMUX.IMUX.47
COREREFCLK_FSinputTCELL30:IMUX.CTRL.4
CTRL_RX0_BITSLIP_FSinputTCELL29:IMUX.IMUX.6
CTRL_RX1_BITSLIP_FSinputTCELL31:IMUX.IMUX.21
DADDR_FS0inputTCELL17:IMUX.IMUX.21
DADDR_FS1inputTCELL17:IMUX.IMUX.31
DADDR_FS10inputTCELL19:IMUX.IMUX.40
DADDR_FS2inputTCELL17:IMUX.IMUX.42
DADDR_FS3inputTCELL18:IMUX.IMUX.18
DADDR_FS4inputTCELL18:IMUX.IMUX.23
DADDR_FS5inputTCELL18:IMUX.IMUX.29
DADDR_FS6inputTCELL18:IMUX.IMUX.9
DADDR_FS7inputTCELL18:IMUX.IMUX.38
DADDR_FS8inputTCELL18:IMUX.IMUX.44
DADDR_FS9inputTCELL19:IMUX.IMUX.25
DCLK_FSinputTCELL15:IMUX.CTRL.4
DEN_FSinputTCELL18:IMUX.IMUX.21
DI_FS0inputTCELL15:IMUX.IMUX.20
DI_FS1inputTCELL15:IMUX.IMUX.29
DI_FS10inputTCELL19:IMUX.IMUX.32
DI_FS11inputTCELL19:IMUX.IMUX.34
DI_FS12inputTCELL19:IMUX.IMUX.37
DI_FS13inputTCELL19:IMUX.IMUX.12
DI_FS14inputTCELL19:IMUX.IMUX.43
DI_FS15inputTCELL19:IMUX.IMUX.15
DI_FS2inputTCELL15:IMUX.IMUX.40
DI_FS3inputTCELL16:IMUX.IMUX.4
DI_FS4inputTCELL16:IMUX.IMUX.39
DI_FS5inputTCELL19:IMUX.IMUX.16
DI_FS6inputTCELL19:IMUX.IMUX.2
DI_FS7inputTCELL19:IMUX.IMUX.22
DI_FS8inputTCELL19:IMUX.IMUX.27
DI_FS9inputTCELL19:IMUX.IMUX.7
DMONCLK_CH0_FSinputTCELL22:IMUX.IMUX.12
DMONCLK_CH1_FSinputTCELL37:IMUX.IMUX.23
DMONFIFORESET_CH0_FSinputTCELL19:IMUX.IMUX.19
DMONFIFORESET_CH1_FSinputTCELL40:IMUX.IMUX.14
DMONOUT_CH0_SF0outputTCELL0:OUT.27
DMONOUT_CH0_SF1outputTCELL1:OUT.10
DMONOUT_CH0_SF10outputTCELL3:OUT.2
DMONOUT_CH0_SF11outputTCELL3:OUT.28
DMONOUT_CH0_SF12outputTCELL3:OUT.29
DMONOUT_CH0_SF13outputTCELL5:OUT.6
DMONOUT_CH0_SF14outputTCELL5:OUT.19
DMONOUT_CH0_SF15outputTCELL5:OUT.25
DMONOUT_CH0_SF16outputTCELL6:OUT.13
DMONOUT_CH0_SF17outputTCELL6:OUT.6
DMONOUT_CH0_SF18outputTCELL6:OUT.3
DMONOUT_CH0_SF19outputTCELL6:OUT.8
DMONOUT_CH0_SF2outputTCELL1:OUT.29
DMONOUT_CH0_SF20outputTCELL7:OUT.28
DMONOUT_CH0_SF21outputTCELL7:OUT.18
DMONOUT_CH0_SF22outputTCELL7:OUT.7
DMONOUT_CH0_SF23outputTCELL7:OUT.6
DMONOUT_CH0_SF24outputTCELL8:OUT.26
DMONOUT_CH0_SF25outputTCELL19:OUT.19
DMONOUT_CH0_SF26outputTCELL19:OUT.9
DMONOUT_CH0_SF27outputTCELL19:OUT.16
DMONOUT_CH0_SF28outputTCELL21:OUT.13
DMONOUT_CH0_SF29outputTCELL27:OUT.30
DMONOUT_CH0_SF3outputTCELL1:OUT.20
DMONOUT_CH0_SF30outputTCELL27:OUT.9
DMONOUT_CH0_SF31outputTCELL29:OUT.1
DMONOUT_CH0_SF4outputTCELL1:OUT.26
DMONOUT_CH0_SF5outputTCELL3:OUT.20
DMONOUT_CH0_SF6outputTCELL3:OUT.17
DMONOUT_CH0_SF7outputTCELL3:OUT.14
DMONOUT_CH0_SF8outputTCELL3:OUT.11
DMONOUT_CH0_SF9outputTCELL3:OUT.12
DMONOUT_CH1_SF0outputTCELL59:OUT.4
DMONOUT_CH1_SF1outputTCELL58:OUT.21
DMONOUT_CH1_SF10outputTCELL56:OUT.29
DMONOUT_CH1_SF11outputTCELL56:OUT.3
DMONOUT_CH1_SF12outputTCELL56:OUT.2
DMONOUT_CH1_SF13outputTCELL54:OUT.25
DMONOUT_CH1_SF14outputTCELL54:OUT.12
DMONOUT_CH1_SF15outputTCELL54:OUT.6
DMONOUT_CH1_SF16outputTCELL53:OUT.18
DMONOUT_CH1_SF17outputTCELL53:OUT.25
DMONOUT_CH1_SF18outputTCELL53:OUT.28
DMONOUT_CH1_SF19outputTCELL53:OUT.23
DMONOUT_CH1_SF2outputTCELL58:OUT.2
DMONOUT_CH1_SF20outputTCELL52:OUT.3
DMONOUT_CH1_SF21outputTCELL52:OUT.13
DMONOUT_CH1_SF22outputTCELL52:OUT.24
DMONOUT_CH1_SF23outputTCELL52:OUT.25
DMONOUT_CH1_SF24outputTCELL51:OUT.5
DMONOUT_CH1_SF25outputTCELL40:OUT.12
DMONOUT_CH1_SF26outputTCELL40:OUT.22
DMONOUT_CH1_SF27outputTCELL40:OUT.15
DMONOUT_CH1_SF28outputTCELL38:OUT.18
DMONOUT_CH1_SF29outputTCELL32:OUT.1
DMONOUT_CH1_SF3outputTCELL58:OUT.11
DMONOUT_CH1_SF30outputTCELL32:OUT.22
DMONOUT_CH1_SF31outputTCELL30:OUT.30
DMONOUT_CH1_SF4outputTCELL58:OUT.5
DMONOUT_CH1_SF5outputTCELL56:OUT.11
DMONOUT_CH1_SF6outputTCELL56:OUT.14
DMONOUT_CH1_SF7outputTCELL56:OUT.17
DMONOUT_CH1_SF8outputTCELL56:OUT.20
DMONOUT_CH1_SF9outputTCELL56:OUT.19
DRDY_SFoutputTCELL19:OUT.23
DRPDO_SF0outputTCELL19:OUT.0
DRPDO_SF1outputTCELL19:OUT.1
DRPDO_SF10outputTCELL19:OUT.18
DRPDO_SF11outputTCELL19:OUT.25
DRPDO_SF12outputTCELL19:OUT.26
DRPDO_SF13outputTCELL19:OUT.27
DRPDO_SF14outputTCELL19:OUT.29
DRPDO_SF15outputTCELL19:OUT.30
DRPDO_SF2outputTCELL19:OUT.3
DRPDO_SF3outputTCELL19:OUT.5
DRPDO_SF4outputTCELL19:OUT.6
DRPDO_SF5outputTCELL19:OUT.7
DRPDO_SF6outputTCELL19:OUT.11
DRPDO_SF7outputTCELL19:OUT.13
DRPDO_SF8outputTCELL19:OUT.15
DRPDO_SF9outputTCELL19:OUT.17
DRSTB_FSinputTCELL18:IMUX.IMUX.8
DWE_FSinputTCELL18:IMUX.IMUX.42
FEC_SCANCLK_FSinputTCELL0:IMUX.CTRL.4
FEC_SCANENB_FSinputTCELL44:IMUX.IMUX.9
FEC_SCANIN_FS0inputTCELL0:IMUX.IMUX.20
FEC_SCANIN_FS1inputTCELL0:IMUX.IMUX.24
FEC_SCANIN_FS10inputTCELL1:IMUX.IMUX.1
FEC_SCANIN_FS100inputTCELL4:IMUX.IMUX.31
FEC_SCANIN_FS101inputTCELL4:IMUX.IMUX.33
FEC_SCANIN_FS102inputTCELL4:IMUX.IMUX.35
FEC_SCANIN_FS103inputTCELL4:IMUX.IMUX.11
FEC_SCANIN_FS104inputTCELL4:IMUX.IMUX.12
FEC_SCANIN_FS105inputTCELL4:IMUX.IMUX.13
FEC_SCANIN_FS106inputTCELL4:IMUX.IMUX.14
FEC_SCANIN_FS107inputTCELL4:IMUX.IMUX.15
FEC_SCANIN_FS108inputTCELL12:IMUX.IMUX.1
FEC_SCANIN_FS109inputTCELL12:IMUX.IMUX.23
FEC_SCANIN_FS11inputTCELL1:IMUX.IMUX.19
FEC_SCANIN_FS110inputTCELL12:IMUX.IMUX.27
FEC_SCANIN_FS111inputTCELL12:IMUX.IMUX.31
FEC_SCANIN_FS112inputTCELL12:IMUX.IMUX.35
FEC_SCANIN_FS113inputTCELL12:IMUX.IMUX.39
FEC_SCANIN_FS114inputTCELL12:IMUX.IMUX.44
FEC_SCANIN_FS115inputTCELL14:IMUX.IMUX.3
FEC_SCANIN_FS116inputTCELL14:IMUX.IMUX.32
FEC_SCANIN_FS117inputTCELL14:IMUX.IMUX.43
FEC_SCANIN_FS118inputTCELL40:IMUX.IMUX.17
FEC_SCANIN_FS119inputTCELL40:IMUX.IMUX.2
FEC_SCANIN_FS12inputTCELL1:IMUX.IMUX.2
FEC_SCANIN_FS120inputTCELL40:IMUX.IMUX.22
FEC_SCANIN_FS121inputTCELL40:IMUX.IMUX.25
FEC_SCANIN_FS122inputTCELL40:IMUX.IMUX.6
FEC_SCANIN_FS123inputTCELL40:IMUX.IMUX.30
FEC_SCANIN_FS124inputTCELL40:IMUX.IMUX.33
FEC_SCANIN_FS125inputTCELL40:IMUX.IMUX.10
FEC_SCANIN_FS126inputTCELL40:IMUX.IMUX.12
FEC_SCANIN_FS127inputTCELL40:IMUX.IMUX.42
FEC_SCANIN_FS128inputTCELL40:IMUX.IMUX.46
FEC_SCANIN_FS129inputTCELL41:IMUX.IMUX.17
FEC_SCANIN_FS13inputTCELL1:IMUX.IMUX.20
FEC_SCANIN_FS130inputTCELL41:IMUX.IMUX.20
FEC_SCANIN_FS131inputTCELL41:IMUX.IMUX.25
FEC_SCANIN_FS132inputTCELL41:IMUX.IMUX.28
FEC_SCANIN_FS133inputTCELL41:IMUX.IMUX.31
FEC_SCANIN_FS134inputTCELL41:IMUX.IMUX.34
FEC_SCANIN_FS135inputTCELL41:IMUX.IMUX.39
FEC_SCANIN_FS136inputTCELL41:IMUX.IMUX.13
FEC_SCANIN_FS137inputTCELL41:IMUX.IMUX.45
FEC_SCANIN_FS138inputTCELL42:IMUX.IMUX.21
FEC_SCANIN_FS139inputTCELL42:IMUX.IMUX.32
FEC_SCANIN_FS14inputTCELL1:IMUX.IMUX.21
FEC_SCANIN_FS140inputTCELL42:IMUX.IMUX.42
FEC_SCANIN_FS141inputTCELL43:IMUX.IMUX.23
FEC_SCANIN_FS142inputTCELL43:IMUX.IMUX.38
FEC_SCANIN_FS143inputTCELL45:IMUX.IMUX.20
FEC_SCANIN_FS144inputTCELL45:IMUX.IMUX.31
FEC_SCANIN_FS145inputTCELL45:IMUX.IMUX.13
FEC_SCANIN_FS146inputTCELL47:IMUX.IMUX.1
FEC_SCANIN_FS147inputTCELL47:IMUX.IMUX.21
FEC_SCANIN_FS148inputTCELL47:IMUX.IMUX.26
FEC_SCANIN_FS149inputTCELL47:IMUX.IMUX.30
FEC_SCANIN_FS15inputTCELL1:IMUX.IMUX.22
FEC_SCANIN_FS150inputTCELL47:IMUX.IMUX.34
FEC_SCANIN_FS151inputTCELL47:IMUX.IMUX.38
FEC_SCANIN_FS152inputTCELL47:IMUX.IMUX.14
FEC_SCANIN_FS153inputTCELL55:IMUX.IMUX.16
FEC_SCANIN_FS154inputTCELL55:IMUX.IMUX.18
FEC_SCANIN_FS155inputTCELL55:IMUX.IMUX.20
FEC_SCANIN_FS156inputTCELL55:IMUX.IMUX.22
FEC_SCANIN_FS157inputTCELL55:IMUX.IMUX.24
FEC_SCANIN_FS158inputTCELL55:IMUX.IMUX.27
FEC_SCANIN_FS159inputTCELL55:IMUX.IMUX.29
FEC_SCANIN_FS16inputTCELL1:IMUX.IMUX.23
FEC_SCANIN_FS160inputTCELL55:IMUX.IMUX.31
FEC_SCANIN_FS161inputTCELL55:IMUX.IMUX.33
FEC_SCANIN_FS162inputTCELL55:IMUX.IMUX.35
FEC_SCANIN_FS163inputTCELL55:IMUX.IMUX.11
FEC_SCANIN_FS164inputTCELL55:IMUX.IMUX.12
FEC_SCANIN_FS165inputTCELL55:IMUX.IMUX.13
FEC_SCANIN_FS166inputTCELL55:IMUX.IMUX.14
FEC_SCANIN_FS167inputTCELL55:IMUX.IMUX.15
FEC_SCANIN_FS168inputTCELL56:IMUX.IMUX.1
FEC_SCANIN_FS169inputTCELL56:IMUX.IMUX.3
FEC_SCANIN_FS17inputTCELL1:IMUX.IMUX.4
FEC_SCANIN_FS170inputTCELL56:IMUX.IMUX.27
FEC_SCANIN_FS171inputTCELL56:IMUX.IMUX.32
FEC_SCANIN_FS172inputTCELL56:IMUX.IMUX.36
FEC_SCANIN_FS173inputTCELL56:IMUX.IMUX.40
FEC_SCANIN_FS174inputTCELL56:IMUX.IMUX.44
FEC_SCANIN_FS175inputTCELL57:IMUX.IMUX.16
FEC_SCANIN_FS176inputTCELL57:IMUX.IMUX.18
FEC_SCANIN_FS177inputTCELL57:IMUX.IMUX.20
FEC_SCANIN_FS178inputTCELL57:IMUX.IMUX.23
FEC_SCANIN_FS179inputTCELL57:IMUX.IMUX.25
FEC_SCANIN_FS18inputTCELL1:IMUX.IMUX.24
FEC_SCANIN_FS180inputTCELL57:IMUX.IMUX.6
FEC_SCANIN_FS181inputTCELL57:IMUX.IMUX.7
FEC_SCANIN_FS182inputTCELL57:IMUX.IMUX.32
FEC_SCANIN_FS183inputTCELL57:IMUX.IMUX.34
FEC_SCANIN_FS184inputTCELL57:IMUX.IMUX.36
FEC_SCANIN_FS185inputTCELL57:IMUX.IMUX.39
FEC_SCANIN_FS186inputTCELL57:IMUX.IMUX.41
FEC_SCANIN_FS187inputTCELL57:IMUX.IMUX.14
FEC_SCANIN_FS188inputTCELL57:IMUX.IMUX.15
FEC_SCANIN_FS189inputTCELL58:IMUX.IMUX.17
FEC_SCANIN_FS19inputTCELL1:IMUX.IMUX.5
FEC_SCANIN_FS190inputTCELL58:IMUX.IMUX.21
FEC_SCANIN_FS191inputTCELL58:IMUX.IMUX.5
FEC_SCANIN_FS192inputTCELL58:IMUX.IMUX.29
FEC_SCANIN_FS193inputTCELL58:IMUX.IMUX.9
FEC_SCANIN_FS194inputTCELL58:IMUX.IMUX.37
FEC_SCANIN_FS195inputTCELL58:IMUX.IMUX.41
FEC_SCANIN_FS196inputTCELL58:IMUX.IMUX.45
FEC_SCANIN_FS197inputTCELL59:IMUX.IMUX.3
FEC_SCANIN_FS198inputTCELL59:IMUX.IMUX.7
FEC_SCANIN_FS199inputTCELL59:IMUX.IMUX.38
FEC_SCANIN_FS2inputTCELL0:IMUX.IMUX.28
FEC_SCANIN_FS20inputTCELL1:IMUX.IMUX.26
FEC_SCANIN_FS21inputTCELL1:IMUX.IMUX.27
FEC_SCANIN_FS22inputTCELL1:IMUX.IMUX.28
FEC_SCANIN_FS23inputTCELL1:IMUX.IMUX.29
FEC_SCANIN_FS24inputTCELL1:IMUX.IMUX.7
FEC_SCANIN_FS25inputTCELL1:IMUX.IMUX.30
FEC_SCANIN_FS26inputTCELL1:IMUX.IMUX.8
FEC_SCANIN_FS27inputTCELL1:IMUX.IMUX.32
FEC_SCANIN_FS28inputTCELL1:IMUX.IMUX.33
FEC_SCANIN_FS29inputTCELL1:IMUX.IMUX.9
FEC_SCANIN_FS3inputTCELL0:IMUX.IMUX.32
FEC_SCANIN_FS30inputTCELL1:IMUX.IMUX.35
FEC_SCANIN_FS31inputTCELL1:IMUX.IMUX.10
FEC_SCANIN_FS32inputTCELL1:IMUX.IMUX.36
FEC_SCANIN_FS33inputTCELL1:IMUX.IMUX.11
FEC_SCANIN_FS34inputTCELL1:IMUX.IMUX.39
FEC_SCANIN_FS35inputTCELL1:IMUX.IMUX.12
FEC_SCANIN_FS36inputTCELL1:IMUX.IMUX.40
FEC_SCANIN_FS37inputTCELL1:IMUX.IMUX.13
FEC_SCANIN_FS38inputTCELL1:IMUX.IMUX.42
FEC_SCANIN_FS39inputTCELL1:IMUX.IMUX.43
FEC_SCANIN_FS4inputTCELL0:IMUX.IMUX.36
FEC_SCANIN_FS40inputTCELL1:IMUX.IMUX.14
FEC_SCANIN_FS41inputTCELL1:IMUX.IMUX.45
FEC_SCANIN_FS42inputTCELL1:IMUX.IMUX.15
FEC_SCANIN_FS43inputTCELL1:IMUX.IMUX.46
FEC_SCANIN_FS44inputTCELL2:IMUX.IMUX.0
FEC_SCANIN_FS45inputTCELL2:IMUX.IMUX.16
FEC_SCANIN_FS46inputTCELL2:IMUX.IMUX.17
FEC_SCANIN_FS47inputTCELL2:IMUX.IMUX.1
FEC_SCANIN_FS48inputTCELL2:IMUX.IMUX.18
FEC_SCANIN_FS49inputTCELL2:IMUX.IMUX.19
FEC_SCANIN_FS5inputTCELL0:IMUX.IMUX.12
FEC_SCANIN_FS50inputTCELL2:IMUX.IMUX.2
FEC_SCANIN_FS51inputTCELL2:IMUX.IMUX.21
FEC_SCANIN_FS52inputTCELL2:IMUX.IMUX.3
FEC_SCANIN_FS53inputTCELL2:IMUX.IMUX.22
FEC_SCANIN_FS54inputTCELL2:IMUX.IMUX.23
FEC_SCANIN_FS55inputTCELL2:IMUX.IMUX.4
FEC_SCANIN_FS56inputTCELL2:IMUX.IMUX.24
FEC_SCANIN_FS57inputTCELL2:IMUX.IMUX.25
FEC_SCANIN_FS58inputTCELL2:IMUX.IMUX.26
FEC_SCANIN_FS59inputTCELL2:IMUX.IMUX.27
FEC_SCANIN_FS6inputTCELL0:IMUX.IMUX.14
FEC_SCANIN_FS60inputTCELL2:IMUX.IMUX.6
FEC_SCANIN_FS61inputTCELL2:IMUX.IMUX.28
FEC_SCANIN_FS62inputTCELL2:IMUX.IMUX.29
FEC_SCANIN_FS63inputTCELL2:IMUX.IMUX.7
FEC_SCANIN_FS64inputTCELL2:IMUX.IMUX.30
FEC_SCANIN_FS65inputTCELL2:IMUX.IMUX.8
FEC_SCANIN_FS66inputTCELL2:IMUX.IMUX.32
FEC_SCANIN_FS67inputTCELL2:IMUX.IMUX.33
FEC_SCANIN_FS68inputTCELL2:IMUX.IMUX.9
FEC_SCANIN_FS69inputTCELL2:IMUX.IMUX.34
FEC_SCANIN_FS7inputTCELL1:IMUX.IMUX.0
FEC_SCANIN_FS70inputTCELL2:IMUX.IMUX.35
FEC_SCANIN_FS71inputTCELL2:IMUX.IMUX.10
FEC_SCANIN_FS72inputTCELL2:IMUX.IMUX.37
FEC_SCANIN_FS73inputTCELL2:IMUX.IMUX.11
FEC_SCANIN_FS74inputTCELL2:IMUX.IMUX.38
FEC_SCANIN_FS75inputTCELL2:IMUX.IMUX.39
FEC_SCANIN_FS76inputTCELL2:IMUX.IMUX.12
FEC_SCANIN_FS77inputTCELL2:IMUX.IMUX.40
FEC_SCANIN_FS78inputTCELL2:IMUX.IMUX.41
FEC_SCANIN_FS79inputTCELL2:IMUX.IMUX.42
FEC_SCANIN_FS8inputTCELL1:IMUX.IMUX.16
FEC_SCANIN_FS80inputTCELL2:IMUX.IMUX.43
FEC_SCANIN_FS81inputTCELL2:IMUX.IMUX.14
FEC_SCANIN_FS82inputTCELL2:IMUX.IMUX.44
FEC_SCANIN_FS83inputTCELL2:IMUX.IMUX.45
FEC_SCANIN_FS84inputTCELL2:IMUX.IMUX.15
FEC_SCANIN_FS85inputTCELL2:IMUX.IMUX.46
FEC_SCANIN_FS86inputTCELL3:IMUX.IMUX.1
FEC_SCANIN_FS87inputTCELL3:IMUX.IMUX.21
FEC_SCANIN_FS88inputTCELL3:IMUX.IMUX.25
FEC_SCANIN_FS89inputTCELL3:IMUX.IMUX.7
FEC_SCANIN_FS9inputTCELL1:IMUX.IMUX.17
FEC_SCANIN_FS90inputTCELL3:IMUX.IMUX.34
FEC_SCANIN_FS91inputTCELL3:IMUX.IMUX.38
FEC_SCANIN_FS92inputTCELL3:IMUX.IMUX.44
FEC_SCANIN_FS93inputTCELL4:IMUX.IMUX.16
FEC_SCANIN_FS94inputTCELL4:IMUX.IMUX.18
FEC_SCANIN_FS95inputTCELL4:IMUX.IMUX.20
FEC_SCANIN_FS96inputTCELL4:IMUX.IMUX.22
FEC_SCANIN_FS97inputTCELL4:IMUX.IMUX.24
FEC_SCANIN_FS98inputTCELL4:IMUX.IMUX.27
FEC_SCANIN_FS99inputTCELL4:IMUX.IMUX.29
FEC_SCANMODEB_FSinputTCELL57:IMUX.IMUX.8
FEC_SCANOUT_SF0outputTCELL0:OUT.0
FEC_SCANOUT_SF1outputTCELL0:OUT.1
FEC_SCANOUT_SF10outputTCELL0:OUT.13
FEC_SCANOUT_SF100outputTCELL4:OUT.6
FEC_SCANOUT_SF101outputTCELL4:OUT.8
FEC_SCANOUT_SF102outputTCELL4:OUT.9
FEC_SCANOUT_SF103outputTCELL4:OUT.10
FEC_SCANOUT_SF104outputTCELL4:OUT.11
FEC_SCANOUT_SF105outputTCELL4:OUT.12
FEC_SCANOUT_SF106outputTCELL4:OUT.13
FEC_SCANOUT_SF107outputTCELL4:OUT.14
FEC_SCANOUT_SF108outputTCELL4:OUT.16
FEC_SCANOUT_SF109outputTCELL4:OUT.17
FEC_SCANOUT_SF11outputTCELL0:OUT.14
FEC_SCANOUT_SF110outputTCELL4:OUT.18
FEC_SCANOUT_SF111outputTCELL4:OUT.19
FEC_SCANOUT_SF112outputTCELL4:OUT.20
FEC_SCANOUT_SF113outputTCELL4:OUT.21
FEC_SCANOUT_SF114outputTCELL4:OUT.22
FEC_SCANOUT_SF115outputTCELL4:OUT.25
FEC_SCANOUT_SF116outputTCELL4:OUT.26
FEC_SCANOUT_SF117outputTCELL4:OUT.27
FEC_SCANOUT_SF118outputTCELL4:OUT.28
FEC_SCANOUT_SF119outputTCELL4:OUT.29
FEC_SCANOUT_SF12outputTCELL0:OUT.16
FEC_SCANOUT_SF120outputTCELL4:OUT.30
FEC_SCANOUT_SF121outputTCELL5:OUT.0
FEC_SCANOUT_SF122outputTCELL5:OUT.1
FEC_SCANOUT_SF123outputTCELL5:OUT.2
FEC_SCANOUT_SF124outputTCELL5:OUT.3
FEC_SCANOUT_SF125outputTCELL5:OUT.4
FEC_SCANOUT_SF126outputTCELL5:OUT.5
FEC_SCANOUT_SF127outputTCELL5:OUT.7
FEC_SCANOUT_SF128outputTCELL5:OUT.9
FEC_SCANOUT_SF129outputTCELL5:OUT.10
FEC_SCANOUT_SF13outputTCELL0:OUT.17
FEC_SCANOUT_SF130outputTCELL5:OUT.11
FEC_SCANOUT_SF131outputTCELL5:OUT.12
FEC_SCANOUT_SF132outputTCELL5:OUT.13
FEC_SCANOUT_SF133outputTCELL5:OUT.14
FEC_SCANOUT_SF134outputTCELL5:OUT.16
FEC_SCANOUT_SF135outputTCELL5:OUT.17
FEC_SCANOUT_SF136outputTCELL5:OUT.18
FEC_SCANOUT_SF137outputTCELL5:OUT.20
FEC_SCANOUT_SF138outputTCELL5:OUT.21
FEC_SCANOUT_SF139outputTCELL5:OUT.22
FEC_SCANOUT_SF14outputTCELL0:OUT.19
FEC_SCANOUT_SF140outputTCELL5:OUT.24
FEC_SCANOUT_SF141outputTCELL5:OUT.26
FEC_SCANOUT_SF142outputTCELL5:OUT.27
FEC_SCANOUT_SF143outputTCELL5:OUT.28
FEC_SCANOUT_SF144outputTCELL5:OUT.29
FEC_SCANOUT_SF145outputTCELL5:OUT.30
FEC_SCANOUT_SF146outputTCELL6:OUT.0
FEC_SCANOUT_SF147outputTCELL6:OUT.2
FEC_SCANOUT_SF148outputTCELL6:OUT.4
FEC_SCANOUT_SF149outputTCELL6:OUT.5
FEC_SCANOUT_SF15outputTCELL0:OUT.20
FEC_SCANOUT_SF150outputTCELL6:OUT.7
FEC_SCANOUT_SF151outputTCELL6:OUT.10
FEC_SCANOUT_SF152outputTCELL6:OUT.11
FEC_SCANOUT_SF153outputTCELL6:OUT.12
FEC_SCANOUT_SF154outputTCELL6:OUT.14
FEC_SCANOUT_SF155outputTCELL6:OUT.15
FEC_SCANOUT_SF156outputTCELL6:OUT.17
FEC_SCANOUT_SF157outputTCELL6:OUT.18
FEC_SCANOUT_SF158outputTCELL6:OUT.19
FEC_SCANOUT_SF159outputTCELL6:OUT.20
FEC_SCANOUT_SF16outputTCELL0:OUT.21
FEC_SCANOUT_SF160outputTCELL6:OUT.21
FEC_SCANOUT_SF161outputTCELL6:OUT.25
FEC_SCANOUT_SF162outputTCELL6:OUT.26
FEC_SCANOUT_SF163outputTCELL6:OUT.28
FEC_SCANOUT_SF164outputTCELL6:OUT.29
FEC_SCANOUT_SF165outputTCELL6:OUT.30
FEC_SCANOUT_SF166outputTCELL53:OUT.14
FEC_SCANOUT_SF167outputTCELL54:OUT.4
FEC_SCANOUT_SF168outputTCELL54:OUT.15
FEC_SCANOUT_SF169outputTCELL54:OUT.27
FEC_SCANOUT_SF17outputTCELL0:OUT.22
FEC_SCANOUT_SF170outputTCELL55:OUT.1
FEC_SCANOUT_SF171outputTCELL55:OUT.4
FEC_SCANOUT_SF172outputTCELL55:OUT.7
FEC_SCANOUT_SF173outputTCELL55:OUT.12
FEC_SCANOUT_SF174outputTCELL55:OUT.15
FEC_SCANOUT_SF175outputTCELL55:OUT.19
FEC_SCANOUT_SF176outputTCELL55:OUT.22
FEC_SCANOUT_SF177outputTCELL55:OUT.26
FEC_SCANOUT_SF178outputTCELL55:OUT.29
FEC_SCANOUT_SF179outputTCELL56:OUT.16
FEC_SCANOUT_SF18outputTCELL0:OUT.24
FEC_SCANOUT_SF180outputTCELL57:OUT.1
FEC_SCANOUT_SF181outputTCELL57:OUT.3
FEC_SCANOUT_SF182outputTCELL57:OUT.6
FEC_SCANOUT_SF183outputTCELL57:OUT.9
FEC_SCANOUT_SF184outputTCELL57:OUT.12
FEC_SCANOUT_SF185outputTCELL57:OUT.15
FEC_SCANOUT_SF186outputTCELL57:OUT.18
FEC_SCANOUT_SF187outputTCELL57:OUT.21
FEC_SCANOUT_SF188outputTCELL57:OUT.24
FEC_SCANOUT_SF189outputTCELL57:OUT.27
FEC_SCANOUT_SF19outputTCELL0:OUT.26
FEC_SCANOUT_SF190outputTCELL57:OUT.30
FEC_SCANOUT_SF191outputTCELL58:OUT.1
FEC_SCANOUT_SF192outputTCELL58:OUT.6
FEC_SCANOUT_SF193outputTCELL58:OUT.10
FEC_SCANOUT_SF194outputTCELL58:OUT.15
FEC_SCANOUT_SF195outputTCELL58:OUT.20
FEC_SCANOUT_SF196outputTCELL58:OUT.25
FEC_SCANOUT_SF197outputTCELL58:OUT.29
FEC_SCANOUT_SF198outputTCELL59:OUT.8
FEC_SCANOUT_SF199outputTCELL59:OUT.22
FEC_SCANOUT_SF2outputTCELL0:OUT.2
FEC_SCANOUT_SF20outputTCELL0:OUT.28
FEC_SCANOUT_SF21outputTCELL0:OUT.29
FEC_SCANOUT_SF22outputTCELL0:OUT.30
FEC_SCANOUT_SF23outputTCELL1:OUT.0
FEC_SCANOUT_SF24outputTCELL1:OUT.1
FEC_SCANOUT_SF25outputTCELL1:OUT.2
FEC_SCANOUT_SF26outputTCELL1:OUT.3
FEC_SCANOUT_SF27outputTCELL1:OUT.4
FEC_SCANOUT_SF28outputTCELL1:OUT.5
FEC_SCANOUT_SF29outputTCELL1:OUT.7
FEC_SCANOUT_SF3outputTCELL0:OUT.3
FEC_SCANOUT_SF30outputTCELL1:OUT.8
FEC_SCANOUT_SF31outputTCELL1:OUT.9
FEC_SCANOUT_SF32outputTCELL1:OUT.11
FEC_SCANOUT_SF33outputTCELL1:OUT.12
FEC_SCANOUT_SF34outputTCELL1:OUT.13
FEC_SCANOUT_SF35outputTCELL1:OUT.15
FEC_SCANOUT_SF36outputTCELL1:OUT.16
FEC_SCANOUT_SF37outputTCELL1:OUT.17
FEC_SCANOUT_SF38outputTCELL1:OUT.18
FEC_SCANOUT_SF39outputTCELL1:OUT.19
FEC_SCANOUT_SF4outputTCELL0:OUT.5
FEC_SCANOUT_SF40outputTCELL1:OUT.21
FEC_SCANOUT_SF41outputTCELL1:OUT.23
FEC_SCANOUT_SF42outputTCELL1:OUT.24
FEC_SCANOUT_SF43outputTCELL1:OUT.25
FEC_SCANOUT_SF44outputTCELL1:OUT.27
FEC_SCANOUT_SF45outputTCELL1:OUT.28
FEC_SCANOUT_SF46outputTCELL1:OUT.30
FEC_SCANOUT_SF47outputTCELL2:OUT.0
FEC_SCANOUT_SF48outputTCELL2:OUT.1
FEC_SCANOUT_SF49outputTCELL2:OUT.2
FEC_SCANOUT_SF5outputTCELL0:OUT.6
FEC_SCANOUT_SF50outputTCELL2:OUT.3
FEC_SCANOUT_SF51outputTCELL2:OUT.4
FEC_SCANOUT_SF52outputTCELL2:OUT.5
FEC_SCANOUT_SF53outputTCELL2:OUT.6
FEC_SCANOUT_SF54outputTCELL2:OUT.8
FEC_SCANOUT_SF55outputTCELL2:OUT.9
FEC_SCANOUT_SF56outputTCELL2:OUT.10
FEC_SCANOUT_SF57outputTCELL2:OUT.11
FEC_SCANOUT_SF58outputTCELL2:OUT.12
FEC_SCANOUT_SF59outputTCELL2:OUT.13
FEC_SCANOUT_SF6outputTCELL0:OUT.9
FEC_SCANOUT_SF60outputTCELL2:OUT.14
FEC_SCANOUT_SF61outputTCELL2:OUT.16
FEC_SCANOUT_SF62outputTCELL2:OUT.17
FEC_SCANOUT_SF63outputTCELL2:OUT.18
FEC_SCANOUT_SF64outputTCELL2:OUT.19
FEC_SCANOUT_SF65outputTCELL2:OUT.20
FEC_SCANOUT_SF66outputTCELL2:OUT.21
FEC_SCANOUT_SF67outputTCELL2:OUT.22
FEC_SCANOUT_SF68outputTCELL2:OUT.24
FEC_SCANOUT_SF69outputTCELL2:OUT.25
FEC_SCANOUT_SF7outputTCELL0:OUT.10
FEC_SCANOUT_SF70outputTCELL2:OUT.26
FEC_SCANOUT_SF71outputTCELL2:OUT.27
FEC_SCANOUT_SF72outputTCELL2:OUT.28
FEC_SCANOUT_SF73outputTCELL2:OUT.29
FEC_SCANOUT_SF74outputTCELL2:OUT.30
FEC_SCANOUT_SF75outputTCELL3:OUT.0
FEC_SCANOUT_SF76outputTCELL3:OUT.1
FEC_SCANOUT_SF77outputTCELL3:OUT.3
FEC_SCANOUT_SF78outputTCELL3:OUT.4
FEC_SCANOUT_SF79outputTCELL3:OUT.5
FEC_SCANOUT_SF8outputTCELL0:OUT.11
FEC_SCANOUT_SF80outputTCELL3:OUT.7
FEC_SCANOUT_SF81outputTCELL3:OUT.8
FEC_SCANOUT_SF82outputTCELL3:OUT.9
FEC_SCANOUT_SF83outputTCELL3:OUT.10
FEC_SCANOUT_SF84outputTCELL3:OUT.13
FEC_SCANOUT_SF85outputTCELL3:OUT.16
FEC_SCANOUT_SF86outputTCELL3:OUT.18
FEC_SCANOUT_SF87outputTCELL3:OUT.19
FEC_SCANOUT_SF88outputTCELL3:OUT.21
FEC_SCANOUT_SF89outputTCELL3:OUT.22
FEC_SCANOUT_SF9outputTCELL0:OUT.12
FEC_SCANOUT_SF90outputTCELL3:OUT.25
FEC_SCANOUT_SF91outputTCELL3:OUT.26
FEC_SCANOUT_SF92outputTCELL3:OUT.27
FEC_SCANOUT_SF93outputTCELL3:OUT.30
FEC_SCANOUT_SF94outputTCELL4:OUT.0
FEC_SCANOUT_SF95outputTCELL4:OUT.1
FEC_SCANOUT_SF96outputTCELL4:OUT.2
FEC_SCANOUT_SF97outputTCELL4:OUT.3
FEC_SCANOUT_SF98outputTCELL4:OUT.4
FEC_SCANOUT_SF99outputTCELL4:OUT.5
FEC_SCANRSTB_FSinputTCELL0:IMUX.CTRL.6
GTPOWERGOOD_SFoutputTCELL54:OUT.17
GTRXRESET_CH0_FSinputTCELL21:IMUX.IMUX.42
GTRXRESET_CH1_FSinputTCELL38:IMUX.IMUX.20
GTTXRESET_CH0_FSinputTCELL17:IMUX.IMUX.46
GTTXRESET_CH1_FSinputTCELL42:IMUX.IMUX.16
HROW_TEST_CK_FSinputTCELL29:IMUX.CTRL.4
LOOPBACK_CH0_FS0inputTCELL16:IMUX.IMUX.43
LOOPBACK_CH0_FS1inputTCELL18:IMUX.IMUX.17
LOOPBACK_CH0_FS2inputTCELL21:IMUX.IMUX.33
LOOPBACK_CH1_FS0inputTCELL43:IMUX.IMUX.2
LOOPBACK_CH1_FS1inputTCELL41:IMUX.IMUX.15
LOOPBACK_CH1_FS2inputTCELL38:IMUX.IMUX.7
MGTREFCLKFA_SFoutputTCELL29:OUT.18
PCS_RSVDIN_CH0_FS0inputTCELL13:IMUX.IMUX.17
PCS_RSVDIN_CH0_FS1inputTCELL13:IMUX.IMUX.40
PCS_RSVDIN_CH0_FS10inputTCELL16:IMUX.IMUX.0
PCS_RSVDIN_CH0_FS11inputTCELL16:IMUX.IMUX.37
PCS_RSVDIN_CH0_FS12inputTCELL16:IMUX.IMUX.29
PCS_RSVDIN_CH0_FS13inputTCELL17:IMUX.IMUX.29
PCS_RSVDIN_CH0_FS14inputTCELL19:IMUX.IMUX.18
PCS_RSVDIN_CH0_FS15inputTCELL22:IMUX.IMUX.7
PCS_RSVDIN_CH0_FS2inputTCELL13:IMUX.IMUX.37
PCS_RSVDIN_CH0_FS3inputTCELL13:IMUX.IMUX.29
PCS_RSVDIN_CH0_FS4inputTCELL13:IMUX.IMUX.5
PCS_RSVDIN_CH0_FS5inputTCELL13:IMUX.IMUX.33
PCS_RSVDIN_CH0_FS6inputTCELL13:IMUX.IMUX.25
PCS_RSVDIN_CH0_FS7inputTCELL14:IMUX.IMUX.1
PCS_RSVDIN_CH0_FS8inputTCELL15:IMUX.IMUX.14
PCS_RSVDIN_CH0_FS9inputTCELL16:IMUX.IMUX.25
PCS_RSVDIN_CH1_FS0inputTCELL46:IMUX.IMUX.15
PCS_RSVDIN_CH1_FS1inputTCELL46:IMUX.IMUX.22
PCS_RSVDIN_CH1_FS10inputTCELL43:IMUX.IMUX.47
PCS_RSVDIN_CH1_FS11inputTCELL43:IMUX.IMUX.5
PCS_RSVDIN_CH1_FS12inputTCELL43:IMUX.IMUX.9
PCS_RSVDIN_CH1_FS13inputTCELL42:IMUX.IMUX.9
PCS_RSVDIN_CH1_FS14inputTCELL40:IMUX.IMUX.44
PCS_RSVDIN_CH1_FS15inputTCELL37:IMUX.IMUX.33
PCS_RSVDIN_CH1_FS2inputTCELL46:IMUX.IMUX.5
PCS_RSVDIN_CH1_FS3inputTCELL46:IMUX.IMUX.9
PCS_RSVDIN_CH1_FS4inputTCELL46:IMUX.IMUX.37
PCS_RSVDIN_CH1_FS5inputTCELL46:IMUX.IMUX.7
PCS_RSVDIN_CH1_FS6inputTCELL46:IMUX.IMUX.11
PCS_RSVDIN_CH1_FS7inputTCELL45:IMUX.IMUX.45
PCS_RSVDIN_CH1_FS8inputTCELL44:IMUX.IMUX.19
PCS_RSVDIN_CH1_FS9inputTCELL43:IMUX.IMUX.11
PCS_RSVDOUT_CH0_SF0outputTCELL3:OUT.24
PCS_RSVDOUT_CH0_SF1outputTCELL7:OUT.9
PCS_RSVDOUT_CH0_SF10outputTCELL24:OUT.4
PCS_RSVDOUT_CH0_SF11outputTCELL24:OUT.20
PCS_RSVDOUT_CH0_SF12outputTCELL26:OUT.11
PCS_RSVDOUT_CH0_SF13outputTCELL27:OUT.23
PCS_RSVDOUT_CH0_SF14outputTCELL27:OUT.3
PCS_RSVDOUT_CH0_SF15outputTCELL29:OUT.24
PCS_RSVDOUT_CH0_SF2outputTCELL7:OUT.29
PCS_RSVDOUT_CH0_SF3outputTCELL7:OUT.15
PCS_RSVDOUT_CH0_SF4outputTCELL7:OUT.13
PCS_RSVDOUT_CH0_SF5outputTCELL7:OUT.20
PCS_RSVDOUT_CH0_SF6outputTCELL7:OUT.10
PCS_RSVDOUT_CH0_SF7outputTCELL7:OUT.27
PCS_RSVDOUT_CH0_SF8outputTCELL7:OUT.0
PCS_RSVDOUT_CH0_SF9outputTCELL20:OUT.17
PCS_RSVDOUT_CH1_SF0outputTCELL56:OUT.7
PCS_RSVDOUT_CH1_SF1outputTCELL52:OUT.22
PCS_RSVDOUT_CH1_SF10outputTCELL35:OUT.27
PCS_RSVDOUT_CH1_SF11outputTCELL35:OUT.11
PCS_RSVDOUT_CH1_SF12outputTCELL33:OUT.20
PCS_RSVDOUT_CH1_SF13outputTCELL32:OUT.8
PCS_RSVDOUT_CH1_SF14outputTCELL32:OUT.28
PCS_RSVDOUT_CH1_SF15outputTCELL30:OUT.7
PCS_RSVDOUT_CH1_SF2outputTCELL52:OUT.2
PCS_RSVDOUT_CH1_SF3outputTCELL52:OUT.16
PCS_RSVDOUT_CH1_SF4outputTCELL52:OUT.18
PCS_RSVDOUT_CH1_SF5outputTCELL52:OUT.11
PCS_RSVDOUT_CH1_SF6outputTCELL52:OUT.21
PCS_RSVDOUT_CH1_SF7outputTCELL52:OUT.4
PCS_RSVDOUT_CH1_SF8outputTCELL52:OUT.31
PCS_RSVDOUT_CH1_SF9outputTCELL39:OUT.14
PCS_SCANCLK_CH0_FS0inputTCELL17:IMUX.IMUX.38
PCS_SCANCLK_CH0_FS1inputTCELL17:IMUX.IMUX.7
PCS_SCANCLK_CH1_FS0inputTCELL42:IMUX.IMUX.24
PCS_SCANCLK_CH1_FS1inputTCELL42:IMUX.IMUX.33
PCS_SCANENB_CH0_FSinputTCELL17:IMUX.IMUX.8
PCS_SCANENB_CH1_FSinputTCELL42:IMUX.IMUX.31
PCS_SCANIN_CH0_FS0inputTCELL14:IMUX.IMUX.27
PCS_SCANIN_CH0_FS1inputTCELL14:IMUX.IMUX.30
PCS_SCANIN_CH0_FS10inputTCELL16:IMUX.IMUX.15
PCS_SCANIN_CH0_FS11inputTCELL16:IMUX.IMUX.21
PCS_SCANIN_CH0_FS12inputTCELL21:IMUX.IMUX.16
PCS_SCANIN_CH0_FS13inputTCELL22:IMUX.IMUX.2
PCS_SCANIN_CH0_FS14inputTCELL22:IMUX.IMUX.5
PCS_SCANIN_CH0_FS2inputTCELL15:IMUX.IMUX.6
PCS_SCANIN_CH0_FS3inputTCELL15:IMUX.IMUX.26
PCS_SCANIN_CH0_FS4inputTCELL15:IMUX.IMUX.37
PCS_SCANIN_CH0_FS5inputTCELL15:IMUX.IMUX.7
PCS_SCANIN_CH0_FS6inputTCELL15:IMUX.IMUX.39
PCS_SCANIN_CH0_FS7inputTCELL15:IMUX.IMUX.32
PCS_SCANIN_CH0_FS8inputTCELL16:IMUX.IMUX.13
PCS_SCANIN_CH0_FS9inputTCELL16:IMUX.IMUX.19
PCS_SCANIN_CH1_FS0inputTCELL45:IMUX.IMUX.10
PCS_SCANIN_CH1_FS1inputTCELL45:IMUX.IMUX.32
PCS_SCANIN_CH1_FS10inputTCELL43:IMUX.IMUX.17
PCS_SCANIN_CH1_FS11inputTCELL43:IMUX.IMUX.13
PCS_SCANIN_CH1_FS12inputTCELL38:IMUX.IMUX.46
PCS_SCANIN_CH1_FS13inputTCELL37:IMUX.IMUX.43
PCS_SCANIN_CH1_FS14inputTCELL37:IMUX.IMUX.37
PCS_SCANIN_CH1_FS2inputTCELL44:IMUX.IMUX.35
PCS_SCANIN_CH1_FS3inputTCELL44:IMUX.IMUX.36
PCS_SCANIN_CH1_FS4inputTCELL44:IMUX.IMUX.5
PCS_SCANIN_CH1_FS5inputTCELL44:IMUX.IMUX.33
PCS_SCANIN_CH1_FS6inputTCELL44:IMUX.IMUX.4
PCS_SCANIN_CH1_FS7inputTCELL44:IMUX.IMUX.30
PCS_SCANIN_CH1_FS8inputTCELL43:IMUX.IMUX.21
PCS_SCANIN_CH1_FS9inputTCELL43:IMUX.IMUX.14
PCS_SCANMODEB_CH0_FSinputTCELL20:IMUX.IMUX.26
PCS_SCANMODEB_CH1_FSinputTCELL39:IMUX.IMUX.36
PCS_SCANOUT_CH0_SF0outputTCELL0:OUT.18
PCS_SCANOUT_CH0_SF1outputTCELL0:OUT.7
PCS_SCANOUT_CH0_SF10outputTCELL25:OUT.28
PCS_SCANOUT_CH0_SF11outputTCELL25:OUT.21
PCS_SCANOUT_CH0_SF12outputTCELL25:OUT.4
PCS_SCANOUT_CH0_SF13outputTCELL26:OUT.9
PCS_SCANOUT_CH0_SF14outputTCELL27:OUT.24
PCS_SCANOUT_CH0_SF2outputTCELL23:OUT.31
PCS_SCANOUT_CH0_SF3outputTCELL23:OUT.10
PCS_SCANOUT_CH0_SF4outputTCELL23:OUT.29
PCS_SCANOUT_CH0_SF5outputTCELL23:OUT.25
PCS_SCANOUT_CH0_SF6outputTCELL24:OUT.30
PCS_SCANOUT_CH0_SF7outputTCELL24:OUT.0
PCS_SCANOUT_CH0_SF8outputTCELL24:OUT.19
PCS_SCANOUT_CH0_SF9outputTCELL24:OUT.14
PCS_SCANOUT_CH1_SF0outputTCELL59:OUT.13
PCS_SCANOUT_CH1_SF1outputTCELL59:OUT.24
PCS_SCANOUT_CH1_SF10outputTCELL34:OUT.3
PCS_SCANOUT_CH1_SF11outputTCELL34:OUT.10
PCS_SCANOUT_CH1_SF12outputTCELL34:OUT.27
PCS_SCANOUT_CH1_SF13outputTCELL33:OUT.22
PCS_SCANOUT_CH1_SF14outputTCELL32:OUT.7
PCS_SCANOUT_CH1_SF2outputTCELL36:OUT.0
PCS_SCANOUT_CH1_SF3outputTCELL36:OUT.21
PCS_SCANOUT_CH1_SF4outputTCELL36:OUT.2
PCS_SCANOUT_CH1_SF5outputTCELL36:OUT.6
PCS_SCANOUT_CH1_SF6outputTCELL35:OUT.1
PCS_SCANOUT_CH1_SF7outputTCELL35:OUT.31
PCS_SCANOUT_CH1_SF8outputTCELL35:OUT.12
PCS_SCANOUT_CH1_SF9outputTCELL35:OUT.17
PCS_SCANRSTB_CH0_FSinputTCELL14:IMUX.CTRL.3
PCS_SCANRSTB_CH1_FSinputTCELL45:IMUX.CTRL.4
PCS_SCANRSTEN_CH0_FSinputTCELL22:IMUX.IMUX.17
PCS_SCANRSTEN_CH1_FSinputTCELL37:IMUX.IMUX.15
PLLRESET_MASK_FS0inputTCELL30:IMUX.IMUX.7
PLLRESET_MASK_FS1inputTCELL31:IMUX.IMUX.8
PLL_FBDIV_FS0inputTCELL29:IMUX.IMUX.31
PLL_FBDIV_FS1inputTCELL30:IMUX.IMUX.31
PLL_FBDIV_FS2inputTCELL31:IMUX.IMUX.17
PLL_FBDIV_FS3inputTCELL31:IMUX.IMUX.22
PLL_FBDIV_FS4inputTCELL31:IMUX.IMUX.6
PLL_FBDIV_FS5inputTCELL31:IMUX.IMUX.9
PLL_FBDIV_FS6inputTCELL31:IMUX.IMUX.39
PLL_FBDIV_FS7inputTCELL31:IMUX.IMUX.44
PLL_FBLOSS_SFoutputTCELL31:OUT.4
PLL_FREQLOCK_SFoutputTCELL31:OUT.14
PLL_MONCLK_FSinputTCELL28:IMUX.CTRL.4
PLL_PWRDN_FSinputTCELL31:IMUX.IMUX.7
PLL_REFDYN_FS0inputTCELL30:IMUX.IMUX.21
PLL_REFDYN_FS1inputTCELL30:IMUX.IMUX.34
PLL_REFDYN_FS2inputTCELL30:IMUX.IMUX.14
PLL_REFLOSS_SFoutputTCELL28:OUT.18
PLL_RESETDONE_SFoutputTCELL31:OUT.25
PLL_RESET_FSinputTCELL28:IMUX.CTRL.6
PLL_RSVDIN_FS0inputTCELL30:IMUX.IMUX.2
PLL_RSVDIN_FS1inputTCELL30:IMUX.IMUX.29
PLL_RSVDIN_FS10inputTCELL31:IMUX.IMUX.34
PLL_RSVDIN_FS11inputTCELL31:IMUX.IMUX.36
PLL_RSVDIN_FS12inputTCELL31:IMUX.IMUX.12
PLL_RSVDIN_FS13inputTCELL31:IMUX.IMUX.41
PLL_RSVDIN_FS14inputTCELL31:IMUX.IMUX.43
PLL_RSVDIN_FS15inputTCELL31:IMUX.IMUX.46
PLL_RSVDIN_FS2inputTCELL30:IMUX.IMUX.42
PLL_RSVDIN_FS3inputTCELL31:IMUX.IMUX.16
PLL_RSVDIN_FS4inputTCELL31:IMUX.IMUX.2
PLL_RSVDIN_FS5inputTCELL31:IMUX.IMUX.3
PLL_RSVDIN_FS6inputTCELL31:IMUX.IMUX.4
PLL_RSVDIN_FS7inputTCELL31:IMUX.IMUX.5
PLL_RSVDIN_FS8inputTCELL31:IMUX.IMUX.29
PLL_RSVDIN_FS9inputTCELL31:IMUX.IMUX.31
PLL_RSVDOUT_SF0outputTCELL28:OUT.2
PLL_RSVDOUT_SF1outputTCELL28:OUT.8
PLL_RSVDOUT_SF10outputTCELL30:OUT.15
PLL_RSVDOUT_SF11outputTCELL30:OUT.17
PLL_RSVDOUT_SF12outputTCELL30:OUT.22
PLL_RSVDOUT_SF13outputTCELL30:OUT.25
PLL_RSVDOUT_SF14outputTCELL30:OUT.27
PLL_RSVDOUT_SF15outputTCELL30:OUT.29
PLL_RSVDOUT_SF2outputTCELL28:OUT.15
PLL_RSVDOUT_SF3outputTCELL28:OUT.22
PLL_RSVDOUT_SF4outputTCELL28:OUT.28
PLL_RSVDOUT_SF5outputTCELL30:OUT.1
PLL_RSVDOUT_SF6outputTCELL30:OUT.4
PLL_RSVDOUT_SF7outputTCELL30:OUT.6
PLL_RSVDOUT_SF8outputTCELL30:OUT.9
PLL_RSVDOUT_SF9outputTCELL30:OUT.11
PLL_SCANCLK_FS0inputTCELL31:IMUX.CTRL.1
PLL_SCANCLK_FS1inputTCELL31:IMUX.CTRL.3
PLL_SCANCLK_FS2inputTCELL31:IMUX.CTRL.5
PLL_SCANCLK_FS3inputTCELL31:IMUX.CTRL.7
PLL_SCANENB_FSinputTCELL31:IMUX.IMUX.40
PLL_SCANIN_FS0inputTCELL29:IMUX.IMUX.32
PLL_SCANIN_FS1inputTCELL30:IMUX.IMUX.20
PLL_SCANIN_FS2inputTCELL30:IMUX.IMUX.9
PLL_SCANIN_FS3inputTCELL30:IMUX.IMUX.43
PLL_SCANIN_FS4inputTCELL31:IMUX.IMUX.19
PLL_SCANIN_FS5inputTCELL31:IMUX.IMUX.27
PLL_SCANIN_FS6inputTCELL31:IMUX.IMUX.10
PLL_SCANIN_FS7inputTCELL31:IMUX.IMUX.14
PLL_SCANMODEB_FSinputTCELL30:IMUX.IMUX.3
PLL_SCANOUT_SF0outputTCELL28:OUT.17
PLL_SCANOUT_SF1outputTCELL30:OUT.13
PLL_SCANOUT_SF2outputTCELL31:OUT.2
PLL_SCANOUT_SF3outputTCELL31:OUT.6
PLL_SCANOUT_SF4outputTCELL31:OUT.12
PLL_SCANOUT_SF5outputTCELL31:OUT.17
PLL_SCANOUT_SF6outputTCELL31:OUT.23
PLL_SCANOUT_SF7outputTCELL31:OUT.29
PLL_SCANRSTEN_FSinputTCELL28:IMUX.CTRL.0
PMA_RSVDIN_CH0_FS0inputTCELL3:IMUX.IMUX.8
PMA_RSVDIN_CH0_FS1inputTCELL3:IMUX.IMUX.32
PMA_RSVDIN_CH0_FS10inputTCELL18:IMUX.IMUX.45
PMA_RSVDIN_CH0_FS11inputTCELL18:IMUX.IMUX.13
PMA_RSVDIN_CH0_FS12inputTCELL20:IMUX.IMUX.3
PMA_RSVDIN_CH0_FS13inputTCELL20:IMUX.IMUX.0
PMA_RSVDIN_CH0_FS14inputTCELL20:IMUX.IMUX.36
PMA_RSVDIN_CH0_FS15inputTCELL22:IMUX.IMUX.46
PMA_RSVDIN_CH0_FS2inputTCELL12:IMUX.IMUX.22
PMA_RSVDIN_CH0_FS3inputTCELL12:IMUX.IMUX.16
PMA_RSVDIN_CH0_FS4inputTCELL14:IMUX.IMUX.4
PMA_RSVDIN_CH0_FS5inputTCELL14:IMUX.IMUX.19
PMA_RSVDIN_CH0_FS6inputTCELL15:IMUX.IMUX.47
PMA_RSVDIN_CH0_FS7inputTCELL15:IMUX.IMUX.33
PMA_RSVDIN_CH0_FS8inputTCELL15:IMUX.IMUX.13
PMA_RSVDIN_CH0_FS9inputTCELL15:IMUX.IMUX.45
PMA_RSVDIN_CH1_FS0inputTCELL56:IMUX.IMUX.31
PMA_RSVDIN_CH1_FS1inputTCELL56:IMUX.IMUX.30
PMA_RSVDIN_CH1_FS10inputTCELL41:IMUX.IMUX.1
PMA_RSVDIN_CH1_FS11inputTCELL41:IMUX.IMUX.21
PMA_RSVDIN_CH1_FS12inputTCELL39:IMUX.IMUX.41
PMA_RSVDIN_CH1_FS13inputTCELL39:IMUX.IMUX.47
PMA_RSVDIN_CH1_FS14inputTCELL39:IMUX.IMUX.26
PMA_RSVDIN_CH1_FS15inputTCELL37:IMUX.IMUX.16
PMA_RSVDIN_CH1_FS2inputTCELL47:IMUX.IMUX.40
PMA_RSVDIN_CH1_FS3inputTCELL47:IMUX.IMUX.46
PMA_RSVDIN_CH1_FS4inputTCELL45:IMUX.IMUX.39
PMA_RSVDIN_CH1_FS5inputTCELL45:IMUX.IMUX.14
PMA_RSVDIN_CH1_FS6inputTCELL44:IMUX.IMUX.0
PMA_RSVDIN_CH1_FS7inputTCELL44:IMUX.IMUX.7
PMA_RSVDIN_CH1_FS8inputTCELL44:IMUX.IMUX.21
PMA_RSVDIN_CH1_FS9inputTCELL44:IMUX.IMUX.1
PMA_RSVDOUT_CH0_SF0outputTCELL6:OUT.27
PMA_RSVDOUT_CH0_SF1outputTCELL7:OUT.31
PMA_RSVDOUT_CH0_SF10outputTCELL21:OUT.22
PMA_RSVDOUT_CH0_SF11outputTCELL24:OUT.12
PMA_RSVDOUT_CH0_SF12outputTCELL26:OUT.20
PMA_RSVDOUT_CH0_SF13outputTCELL29:OUT.8
PMA_RSVDOUT_CH0_SF14outputTCELL29:OUT.17
PMA_RSVDOUT_CH0_SF15outputTCELL29:OUT.12
PMA_RSVDOUT_CH0_SF2outputTCELL8:OUT.8
PMA_RSVDOUT_CH0_SF3outputTCELL8:OUT.13
PMA_RSVDOUT_CH0_SF4outputTCELL8:OUT.18
PMA_RSVDOUT_CH0_SF5outputTCELL8:OUT.6
PMA_RSVDOUT_CH0_SF6outputTCELL8:OUT.30
PMA_RSVDOUT_CH0_SF7outputTCELL8:OUT.1
PMA_RSVDOUT_CH0_SF8outputTCELL14:OUT.24
PMA_RSVDOUT_CH0_SF9outputTCELL19:OUT.12
PMA_RSVDOUT_CH1_SF0outputTCELL53:OUT.4
PMA_RSVDOUT_CH1_SF1outputTCELL52:OUT.0
PMA_RSVDOUT_CH1_SF10outputTCELL38:OUT.9
PMA_RSVDOUT_CH1_SF11outputTCELL35:OUT.19
PMA_RSVDOUT_CH1_SF12outputTCELL33:OUT.11
PMA_RSVDOUT_CH1_SF13outputTCELL30:OUT.23
PMA_RSVDOUT_CH1_SF14outputTCELL30:OUT.14
PMA_RSVDOUT_CH1_SF15outputTCELL30:OUT.19
PMA_RSVDOUT_CH1_SF2outputTCELL51:OUT.23
PMA_RSVDOUT_CH1_SF3outputTCELL51:OUT.18
PMA_RSVDOUT_CH1_SF4outputTCELL51:OUT.13
PMA_RSVDOUT_CH1_SF5outputTCELL51:OUT.25
PMA_RSVDOUT_CH1_SF6outputTCELL51:OUT.1
PMA_RSVDOUT_CH1_SF7outputTCELL51:OUT.30
PMA_RSVDOUT_CH1_SF8outputTCELL45:OUT.7
PMA_RSVDOUT_CH1_SF9outputTCELL40:OUT.19
PMA_SCANCLK_CH0_FS0inputTCELL0:IMUX.IMUX.27
PMA_SCANCLK_CH0_FS1inputTCELL0:IMUX.IMUX.3
PMA_SCANCLK_CH0_FS2inputTCELL18:IMUX.IMUX.6
PMA_SCANCLK_CH0_FS3inputTCELL18:IMUX.IMUX.24
PMA_SCANCLK_CH0_FS4inputTCELL19:IMUX.IMUX.5
PMA_SCANCLK_CH0_FS5inputTCELL19:IMUX.IMUX.24
PMA_SCANCLK_CH0_FS6inputTCELL20:IMUX.IMUX.11
PMA_SCANCLK_CH0_FS7inputTCELL20:IMUX.IMUX.28
PMA_SCANCLK_CH0_FS8inputTCELL26:IMUX.IMUX.19
PMA_SCANCLK_CH1_FS0inputTCELL59:IMUX.IMUX.10
PMA_SCANCLK_CH1_FS1inputTCELL59:IMUX.IMUX.41
PMA_SCANCLK_CH1_FS2inputTCELL41:IMUX.IMUX.35
PMA_SCANCLK_CH1_FS3inputTCELL41:IMUX.IMUX.38
PMA_SCANCLK_CH1_FS4inputTCELL40:IMUX.IMUX.37
PMA_SCANCLK_CH1_FS5inputTCELL40:IMUX.IMUX.38
PMA_SCANCLK_CH1_FS6inputTCELL39:IMUX.IMUX.25
PMA_SCANCLK_CH1_FS7inputTCELL39:IMUX.IMUX.34
PMA_SCANCLK_CH1_FS8inputTCELL33:IMUX.IMUX.14
PMA_SCANENB_CH0_FSinputTCELL22:IMUX.IMUX.18
PMA_SCANENB_CH1_FSinputTCELL37:IMUX.IMUX.44
PMA_SCANIN_CH0_FS0inputTCELL0:IMUX.IMUX.10
PMA_SCANIN_CH0_FS1inputTCELL0:IMUX.IMUX.19
PMA_SCANIN_CH0_FS10inputTCELL3:IMUX.IMUX.40
PMA_SCANIN_CH0_FS11inputTCELL3:IMUX.IMUX.12
PMA_SCANIN_CH0_FS12inputTCELL12:IMUX.IMUX.8
PMA_SCANIN_CH0_FS13inputTCELL12:IMUX.IMUX.18
PMA_SCANIN_CH0_FS14inputTCELL12:IMUX.IMUX.21
PMA_SCANIN_CH0_FS15inputTCELL12:IMUX.IMUX.46
PMA_SCANIN_CH0_FS16inputTCELL12:IMUX.IMUX.12
PMA_SCANIN_CH0_FS17inputTCELL12:IMUX.IMUX.40
PMA_SCANIN_CH0_FS18inputTCELL13:IMUX.IMUX.38
PMA_SCANIN_CH0_FS19inputTCELL13:IMUX.IMUX.28
PMA_SCANIN_CH0_FS2inputTCELL0:IMUX.IMUX.42
PMA_SCANIN_CH0_FS20inputTCELL13:IMUX.IMUX.11
PMA_SCANIN_CH0_FS21inputTCELL14:IMUX.IMUX.45
PMA_SCANIN_CH0_FS22inputTCELL14:IMUX.IMUX.34
PMA_SCANIN_CH0_FS23inputTCELL14:IMUX.IMUX.9
PMA_SCANIN_CH0_FS24inputTCELL17:IMUX.IMUX.12
PMA_SCANIN_CH0_FS3inputTCELL0:IMUX.IMUX.29
PMA_SCANIN_CH0_FS4inputTCELL0:IMUX.IMUX.2
PMA_SCANIN_CH0_FS5inputTCELL0:IMUX.IMUX.22
PMA_SCANIN_CH0_FS6inputTCELL1:IMUX.IMUX.38
PMA_SCANIN_CH0_FS7inputTCELL3:IMUX.IMUX.28
PMA_SCANIN_CH0_FS8inputTCELL3:IMUX.IMUX.47
PMA_SCANIN_CH0_FS9inputTCELL3:IMUX.IMUX.0
PMA_SCANIN_CH1_FS0inputTCELL59:IMUX.IMUX.27
PMA_SCANIN_CH1_FS1inputTCELL59:IMUX.IMUX.14
PMA_SCANIN_CH1_FS10inputTCELL56:IMUX.IMUX.22
PMA_SCANIN_CH1_FS11inputTCELL56:IMUX.IMUX.23
PMA_SCANIN_CH1_FS12inputTCELL47:IMUX.IMUX.31
PMA_SCANIN_CH1_FS13inputTCELL47:IMUX.IMUX.44
PMA_SCANIN_CH1_FS14inputTCELL47:IMUX.IMUX.13
PMA_SCANIN_CH1_FS15inputTCELL47:IMUX.IMUX.16
PMA_SCANIN_CH1_FS16inputTCELL47:IMUX.IMUX.23
PMA_SCANIN_CH1_FS17inputTCELL47:IMUX.IMUX.22
PMA_SCANIN_CH1_FS18inputTCELL46:IMUX.IMUX.24
PMA_SCANIN_CH1_FS19inputTCELL46:IMUX.IMUX.34
PMA_SCANIN_CH1_FS2inputTCELL59:IMUX.IMUX.20
PMA_SCANIN_CH1_FS20inputTCELL46:IMUX.IMUX.25
PMA_SCANIN_CH1_FS21inputTCELL45:IMUX.IMUX.1
PMA_SCANIN_CH1_FS22inputTCELL45:IMUX.IMUX.28
PMA_SCANIN_CH1_FS23inputTCELL45:IMUX.IMUX.29
PMA_SCANIN_CH1_FS24inputTCELL42:IMUX.IMUX.23
PMA_SCANIN_CH1_FS3inputTCELL59:IMUX.IMUX.9
PMA_SCANIN_CH1_FS4inputTCELL59:IMUX.IMUX.43
PMA_SCANIN_CH1_FS5inputTCELL59:IMUX.IMUX.40
PMA_SCANIN_CH1_FS6inputTCELL58:IMUX.IMUX.24
PMA_SCANIN_CH1_FS7inputTCELL56:IMUX.IMUX.34
PMA_SCANIN_CH1_FS8inputTCELL56:IMUX.IMUX.0
PMA_SCANIN_CH1_FS9inputTCELL56:IMUX.IMUX.47
PMA_SCANMODEB_CH0_FSinputTCELL20:IMUX.IMUX.19
PMA_SCANMODEB_CH1_FSinputTCELL39:IMUX.IMUX.14
PMA_SCANOUT_CH0_SF0outputTCELL0:OUT.4
PMA_SCANOUT_CH0_SF1outputTCELL0:OUT.25
PMA_SCANOUT_CH0_SF10outputTCELL19:OUT.10
PMA_SCANOUT_CH0_SF11outputTCELL20:OUT.26
PMA_SCANOUT_CH0_SF12outputTCELL20:OUT.7
PMA_SCANOUT_CH0_SF13outputTCELL20:OUT.6
PMA_SCANOUT_CH0_SF14outputTCELL20:OUT.28
PMA_SCANOUT_CH0_SF15outputTCELL20:OUT.2
PMA_SCANOUT_CH0_SF16outputTCELL22:OUT.29
PMA_SCANOUT_CH0_SF17outputTCELL23:OUT.22
PMA_SCANOUT_CH0_SF18outputTCELL24:OUT.22
PMA_SCANOUT_CH0_SF19outputTCELL25:OUT.24
PMA_SCANOUT_CH0_SF2outputTCELL6:OUT.23
PMA_SCANOUT_CH0_SF20outputTCELL25:OUT.31
PMA_SCANOUT_CH0_SF21outputTCELL25:OUT.7
PMA_SCANOUT_CH0_SF22outputTCELL25:OUT.18
PMA_SCANOUT_CH0_SF23outputTCELL25:OUT.9
PMA_SCANOUT_CH0_SF24outputTCELL26:OUT.16
PMA_SCANOUT_CH0_SF3outputTCELL6:OUT.1
PMA_SCANOUT_CH0_SF4outputTCELL6:OUT.22
PMA_SCANOUT_CH0_SF5outputTCELL7:OUT.1
PMA_SCANOUT_CH0_SF6outputTCELL7:OUT.8
PMA_SCANOUT_CH0_SF7outputTCELL7:OUT.30
PMA_SCANOUT_CH0_SF8outputTCELL8:OUT.15
PMA_SCANOUT_CH0_SF9outputTCELL8:OUT.31
PMA_SCANOUT_CH1_SF0outputTCELL59:OUT.27
PMA_SCANOUT_CH1_SF1outputTCELL59:OUT.6
PMA_SCANOUT_CH1_SF10outputTCELL40:OUT.21
PMA_SCANOUT_CH1_SF11outputTCELL39:OUT.5
PMA_SCANOUT_CH1_SF12outputTCELL39:OUT.24
PMA_SCANOUT_CH1_SF13outputTCELL39:OUT.25
PMA_SCANOUT_CH1_SF14outputTCELL39:OUT.3
PMA_SCANOUT_CH1_SF15outputTCELL39:OUT.29
PMA_SCANOUT_CH1_SF16outputTCELL37:OUT.2
PMA_SCANOUT_CH1_SF17outputTCELL36:OUT.9
PMA_SCANOUT_CH1_SF18outputTCELL35:OUT.9
PMA_SCANOUT_CH1_SF19outputTCELL34:OUT.7
PMA_SCANOUT_CH1_SF2outputTCELL53:OUT.8
PMA_SCANOUT_CH1_SF20outputTCELL34:OUT.0
PMA_SCANOUT_CH1_SF21outputTCELL34:OUT.24
PMA_SCANOUT_CH1_SF22outputTCELL34:OUT.13
PMA_SCANOUT_CH1_SF23outputTCELL34:OUT.22
PMA_SCANOUT_CH1_SF24outputTCELL33:OUT.15
PMA_SCANOUT_CH1_SF3outputTCELL53:OUT.30
PMA_SCANOUT_CH1_SF4outputTCELL53:OUT.9
PMA_SCANOUT_CH1_SF5outputTCELL52:OUT.30
PMA_SCANOUT_CH1_SF6outputTCELL52:OUT.23
PMA_SCANOUT_CH1_SF7outputTCELL52:OUT.1
PMA_SCANOUT_CH1_SF8outputTCELL51:OUT.16
PMA_SCANOUT_CH1_SF9outputTCELL51:OUT.0
PMA_SCANRSTEN_CH0_FSinputTCELL20:IMUX.IMUX.18
PMA_SCANRSTEN_CH1_FSinputTCELL39:IMUX.IMUX.44
RCALENB_FSinputTCELL59:IMUX.IMUX.12
RCAL_CMP_SFoutputTCELL59:OUT.16
RCAL_SF0outputTCELL58:OUT.17
RCAL_SF1outputTCELL59:OUT.3
RCAL_SF2outputTCELL59:OUT.12
RCAL_SF3outputTCELL59:OUT.19
RCAL_SF4outputTCELL59:OUT.28
REFCLKPD_FSinputTCELL30:IMUX.IMUX.10
RESETOVRD_CH0_FSinputTCELL21:IMUX.IMUX.38
RESETOVRD_CH1_FSinputTCELL38:IMUX.IMUX.24
RESET_BYPASS_MODE_FSinputTCELL30:IMUX.IMUX.44
RESET_EXCEPTION_CH0_SFoutputTCELL4:OUT.23
RESET_EXCEPTION_CH1_SFoutputTCELL55:OUT.8
RXBUFSTATUS_CH0_SF0outputTCELL26:OUT.28
RXBUFSTATUS_CH0_SF1outputTCELL26:OUT.19
RXBUFSTATUS_CH0_SF2outputTCELL26:OUT.3
RXBUFSTATUS_CH1_SF0outputTCELL33:OUT.3
RXBUFSTATUS_CH1_SF1outputTCELL33:OUT.12
RXBUFSTATUS_CH1_SF2outputTCELL33:OUT.28
RXDATA_CH0_SF0outputTCELL9:OUT.22
RXDATA_CH0_SF1outputTCELL9:OUT.12
RXDATA_CH0_SF10outputTCELL9:OUT.11
RXDATA_CH0_SF100outputTCELL13:OUT.11
RXDATA_CH0_SF101outputTCELL13:OUT.21
RXDATA_CH0_SF102outputTCELL13:OUT.3
RXDATA_CH0_SF103outputTCELL13:OUT.2
RXDATA_CH0_SF104outputTCELL13:OUT.5
RXDATA_CH0_SF105outputTCELL13:OUT.10
RXDATA_CH0_SF106outputTCELL13:OUT.6
RXDATA_CH0_SF107outputTCELL13:OUT.9
RXDATA_CH0_SF108outputTCELL13:OUT.28
RXDATA_CH0_SF109outputTCELL14:OUT.26
RXDATA_CH0_SF11outputTCELL9:OUT.20
RXDATA_CH0_SF110outputTCELL14:OUT.12
RXDATA_CH0_SF111outputTCELL14:OUT.15
RXDATA_CH0_SF112outputTCELL14:OUT.5
RXDATA_CH0_SF113outputTCELL14:OUT.29
RXDATA_CH0_SF114outputTCELL14:OUT.11
RXDATA_CH0_SF115outputTCELL14:OUT.1
RXDATA_CH0_SF116outputTCELL14:OUT.10
RXDATA_CH0_SF117outputTCELL14:OUT.3
RXDATA_CH0_SF118outputTCELL14:OUT.27
RXDATA_CH0_SF119outputTCELL14:OUT.28
RXDATA_CH0_SF12outputTCELL9:OUT.28
RXDATA_CH0_SF120outputTCELL14:OUT.22
RXDATA_CH0_SF121outputTCELL14:OUT.7
RXDATA_CH0_SF122outputTCELL14:OUT.2
RXDATA_CH0_SF123outputTCELL14:OUT.30
RXDATA_CH0_SF124outputTCELL14:OUT.21
RXDATA_CH0_SF125outputTCELL14:OUT.4
RXDATA_CH0_SF126outputTCELL15:OUT.25
RXDATA_CH0_SF127outputTCELL15:OUT.4
RXDATA_CH0_SF128outputTCELL15:OUT.14
RXDATA_CH0_SF129outputTCELL15:OUT.15
RXDATA_CH0_SF13outputTCELL9:OUT.18
RXDATA_CH0_SF130outputTCELL15:OUT.17
RXDATA_CH0_SF131outputTCELL15:OUT.8
RXDATA_CH0_SF132outputTCELL15:OUT.13
RXDATA_CH0_SF133outputTCELL15:OUT.24
RXDATA_CH0_SF134outputTCELL15:OUT.23
RXDATA_CH0_SF135outputTCELL15:OUT.21
RXDATA_CH0_SF136outputTCELL15:OUT.27
RXDATA_CH0_SF137outputTCELL15:OUT.11
RXDATA_CH0_SF138outputTCELL15:OUT.19
RXDATA_CH0_SF139outputTCELL15:OUT.7
RXDATA_CH0_SF14outputTCELL9:OUT.29
RXDATA_CH0_SF140outputTCELL15:OUT.30
RXDATA_CH0_SF141outputTCELL15:OUT.5
RXDATA_CH0_SF142outputTCELL15:OUT.2
RXDATA_CH0_SF143outputTCELL16:OUT.15
RXDATA_CH0_SF144outputTCELL16:OUT.31
RXDATA_CH0_SF145outputTCELL16:OUT.11
RXDATA_CH0_SF146outputTCELL16:OUT.10
RXDATA_CH0_SF147outputTCELL16:OUT.16
RXDATA_CH0_SF148outputTCELL16:OUT.4
RXDATA_CH0_SF149outputTCELL16:OUT.2
RXDATA_CH0_SF15outputTCELL9:OUT.26
RXDATA_CH0_SF150outputTCELL16:OUT.29
RXDATA_CH0_SF151outputTCELL16:OUT.6
RXDATA_CH0_SF152outputTCELL16:OUT.9
RXDATA_CH0_SF153outputTCELL16:OUT.7
RXDATA_CH0_SF154outputTCELL16:OUT.28
RXDATA_CH0_SF155outputTCELL17:OUT.24
RXDATA_CH0_SF156outputTCELL17:OUT.28
RXDATA_CH0_SF157outputTCELL17:OUT.14
RXDATA_CH0_SF158outputTCELL17:OUT.25
RXDATA_CH0_SF159outputTCELL17:OUT.13
RXDATA_CH0_SF16outputTCELL9:OUT.6
RXDATA_CH0_SF160outputTCELL17:OUT.19
RXDATA_CH0_SF161outputTCELL17:OUT.26
RXDATA_CH0_SF162outputTCELL17:OUT.11
RXDATA_CH0_SF163outputTCELL17:OUT.15
RXDATA_CH0_SF164outputTCELL17:OUT.20
RXDATA_CH0_SF165outputTCELL17:OUT.8
RXDATA_CH0_SF166outputTCELL17:OUT.31
RXDATA_CH0_SF167outputTCELL17:OUT.9
RXDATA_CH0_SF168outputTCELL17:OUT.0
RXDATA_CH0_SF169outputTCELL17:OUT.16
RXDATA_CH0_SF17outputTCELL9:OUT.24
RXDATA_CH0_SF170outputTCELL17:OUT.7
RXDATA_CH0_SF171outputTCELL17:OUT.30
RXDATA_CH0_SF172outputTCELL17:OUT.4
RXDATA_CH0_SF173outputTCELL17:OUT.29
RXDATA_CH0_SF174outputTCELL18:OUT.15
RXDATA_CH0_SF175outputTCELL18:OUT.14
RXDATA_CH0_SF176outputTCELL18:OUT.7
RXDATA_CH0_SF177outputTCELL18:OUT.9
RXDATA_CH0_SF178outputTCELL18:OUT.20
RXDATA_CH0_SF179outputTCELL18:OUT.24
RXDATA_CH0_SF18outputTCELL9:OUT.16
RXDATA_CH0_SF180outputTCELL18:OUT.21
RXDATA_CH0_SF181outputTCELL18:OUT.26
RXDATA_CH0_SF182outputTCELL18:OUT.16
RXDATA_CH0_SF183outputTCELL18:OUT.10
RXDATA_CH0_SF184outputTCELL18:OUT.1
RXDATA_CH0_SF185outputTCELL18:OUT.22
RXDATA_CH0_SF186outputTCELL18:OUT.6
RXDATA_CH0_SF187outputTCELL18:OUT.19
RXDATA_CH0_SF188outputTCELL18:OUT.5
RXDATA_CH0_SF189outputTCELL18:OUT.13
RXDATA_CH0_SF19outputTCELL9:OUT.31
RXDATA_CH0_SF190outputTCELL18:OUT.27
RXDATA_CH0_SF191outputTCELL18:OUT.2
RXDATA_CH0_SF192outputTCELL18:OUT.17
RXDATA_CH0_SF193outputTCELL18:OUT.29
RXDATA_CH0_SF194outputTCELL18:OUT.12
RXDATA_CH0_SF195outputTCELL18:OUT.30
RXDATA_CH0_SF196outputTCELL18:OUT.8
RXDATA_CH0_SF197outputTCELL18:OUT.18
RXDATA_CH0_SF198outputTCELL18:OUT.23
RXDATA_CH0_SF199outputTCELL18:OUT.11
RXDATA_CH0_SF2outputTCELL9:OUT.30
RXDATA_CH0_SF20outputTCELL9:OUT.23
RXDATA_CH0_SF200outputTCELL18:OUT.3
RXDATA_CH0_SF201outputTCELL18:OUT.28
RXDATA_CH0_SF202outputTCELL19:OUT.22
RXDATA_CH0_SF203outputTCELL20:OUT.15
RXDATA_CH0_SF204outputTCELL20:OUT.4
RXDATA_CH0_SF205outputTCELL20:OUT.20
RXDATA_CH0_SF206outputTCELL20:OUT.19
RXDATA_CH0_SF207outputTCELL20:OUT.18
RXDATA_CH0_SF208outputTCELL20:OUT.0
RXDATA_CH0_SF209outputTCELL20:OUT.24
RXDATA_CH0_SF21outputTCELL9:OUT.7
RXDATA_CH0_SF210outputTCELL21:OUT.14
RXDATA_CH0_SF211outputTCELL21:OUT.15
RXDATA_CH0_SF212outputTCELL21:OUT.10
RXDATA_CH0_SF213outputTCELL21:OUT.25
RXDATA_CH0_SF214outputTCELL21:OUT.20
RXDATA_CH0_SF215outputTCELL21:OUT.27
RXDATA_CH0_SF216outputTCELL21:OUT.12
RXDATA_CH0_SF217outputTCELL21:OUT.1
RXDATA_CH0_SF218outputTCELL21:OUT.17
RXDATA_CH0_SF219outputTCELL21:OUT.5
RXDATA_CH0_SF22outputTCELL9:OUT.1
RXDATA_CH0_SF220outputTCELL21:OUT.28
RXDATA_CH0_SF221outputTCELL21:OUT.31
RXDATA_CH0_SF222outputTCELL21:OUT.19
RXDATA_CH0_SF223outputTCELL21:OUT.30
RXDATA_CH0_SF224outputTCELL21:OUT.21
RXDATA_CH0_SF225outputTCELL21:OUT.29
RXDATA_CH0_SF226outputTCELL21:OUT.8
RXDATA_CH0_SF227outputTCELL21:OUT.7
RXDATA_CH0_SF228outputTCELL21:OUT.6
RXDATA_CH0_SF229outputTCELL21:OUT.4
RXDATA_CH0_SF23outputTCELL9:OUT.17
RXDATA_CH0_SF230outputTCELL22:OUT.7
RXDATA_CH0_SF231outputTCELL22:OUT.11
RXDATA_CH0_SF232outputTCELL22:OUT.3
RXDATA_CH0_SF233outputTCELL22:OUT.1
RXDATA_CH0_SF234outputTCELL22:OUT.15
RXDATA_CH0_SF235outputTCELL22:OUT.8
RXDATA_CH0_SF236outputTCELL22:OUT.27
RXDATA_CH0_SF237outputTCELL22:OUT.6
RXDATA_CH0_SF238outputTCELL22:OUT.31
RXDATA_CH0_SF239outputTCELL22:OUT.9
RXDATA_CH0_SF24outputTCELL9:OUT.25
RXDATA_CH0_SF240outputTCELL22:OUT.16
RXDATA_CH0_SF241outputTCELL22:OUT.24
RXDATA_CH0_SF242outputTCELL22:OUT.5
RXDATA_CH0_SF243outputTCELL22:OUT.10
RXDATA_CH0_SF244outputTCELL22:OUT.0
RXDATA_CH0_SF245outputTCELL22:OUT.25
RXDATA_CH0_SF246outputTCELL22:OUT.26
RXDATA_CH0_SF247outputTCELL22:OUT.14
RXDATA_CH0_SF248outputTCELL22:OUT.28
RXDATA_CH0_SF249outputTCELL22:OUT.20
RXDATA_CH0_SF25outputTCELL9:OUT.2
RXDATA_CH0_SF250outputTCELL22:OUT.13
RXDATA_CH0_SF251outputTCELL22:OUT.2
RXDATA_CH0_SF252outputTCELL22:OUT.18
RXDATA_CH0_SF253outputTCELL22:OUT.23
RXDATA_CH0_SF254outputTCELL22:OUT.22
RXDATA_CH0_SF255outputTCELL22:OUT.12
RXDATA_CH0_SF26outputTCELL9:OUT.4
RXDATA_CH0_SF27outputTCELL10:OUT.3
RXDATA_CH0_SF28outputTCELL10:OUT.15
RXDATA_CH0_SF29outputTCELL10:OUT.4
RXDATA_CH0_SF3outputTCELL9:OUT.15
RXDATA_CH0_SF30outputTCELL10:OUT.17
RXDATA_CH0_SF31outputTCELL10:OUT.18
RXDATA_CH0_SF32outputTCELL10:OUT.19
RXDATA_CH0_SF33outputTCELL10:OUT.21
RXDATA_CH0_SF34outputTCELL10:OUT.27
RXDATA_CH0_SF35outputTCELL10:OUT.10
RXDATA_CH0_SF36outputTCELL10:OUT.5
RXDATA_CH0_SF37outputTCELL10:OUT.2
RXDATA_CH0_SF38outputTCELL10:OUT.22
RXDATA_CH0_SF39outputTCELL10:OUT.6
RXDATA_CH0_SF4outputTCELL9:OUT.14
RXDATA_CH0_SF40outputTCELL10:OUT.26
RXDATA_CH0_SF41outputTCELL10:OUT.0
RXDATA_CH0_SF42outputTCELL10:OUT.1
RXDATA_CH0_SF43outputTCELL10:OUT.23
RXDATA_CH0_SF44outputTCELL10:OUT.11
RXDATA_CH0_SF45outputTCELL10:OUT.9
RXDATA_CH0_SF46outputTCELL10:OUT.25
RXDATA_CH0_SF47outputTCELL10:OUT.29
RXDATA_CH0_SF48outputTCELL10:OUT.7
RXDATA_CH0_SF49outputTCELL10:OUT.30
RXDATA_CH0_SF5outputTCELL9:OUT.19
RXDATA_CH0_SF50outputTCELL10:OUT.24
RXDATA_CH0_SF51outputTCELL10:OUT.12
RXDATA_CH0_SF52outputTCELL10:OUT.28
RXDATA_CH0_SF53outputTCELL10:OUT.14
RXDATA_CH0_SF54outputTCELL10:OUT.8
RXDATA_CH0_SF55outputTCELL11:OUT.22
RXDATA_CH0_SF56outputTCELL11:OUT.20
RXDATA_CH0_SF57outputTCELL11:OUT.1
RXDATA_CH0_SF58outputTCELL11:OUT.0
RXDATA_CH0_SF59outputTCELL11:OUT.7
RXDATA_CH0_SF6outputTCELL9:OUT.8
RXDATA_CH0_SF60outputTCELL11:OUT.16
RXDATA_CH0_SF61outputTCELL11:OUT.12
RXDATA_CH0_SF62outputTCELL11:OUT.8
RXDATA_CH0_SF63outputTCELL11:OUT.11
RXDATA_CH0_SF64outputTCELL11:OUT.19
RXDATA_CH0_SF65outputTCELL11:OUT.9
RXDATA_CH0_SF66outputTCELL11:OUT.13
RXDATA_CH0_SF67outputTCELL11:OUT.30
RXDATA_CH0_SF68outputTCELL11:OUT.21
RXDATA_CH0_SF69outputTCELL11:OUT.29
RXDATA_CH0_SF7outputTCELL9:OUT.13
RXDATA_CH0_SF70outputTCELL11:OUT.18
RXDATA_CH0_SF71outputTCELL11:OUT.2
RXDATA_CH0_SF72outputTCELL11:OUT.4
RXDATA_CH0_SF73outputTCELL11:OUT.6
RXDATA_CH0_SF74outputTCELL11:OUT.15
RXDATA_CH0_SF75outputTCELL11:OUT.23
RXDATA_CH0_SF76outputTCELL11:OUT.31
RXDATA_CH0_SF77outputTCELL11:OUT.17
RXDATA_CH0_SF78outputTCELL11:OUT.14
RXDATA_CH0_SF79outputTCELL12:OUT.0
RXDATA_CH0_SF8outputTCELL9:OUT.10
RXDATA_CH0_SF80outputTCELL12:OUT.13
RXDATA_CH0_SF81outputTCELL12:OUT.9
RXDATA_CH0_SF82outputTCELL12:OUT.20
RXDATA_CH0_SF83outputTCELL12:OUT.1
RXDATA_CH0_SF84outputTCELL12:OUT.18
RXDATA_CH0_SF85outputTCELL12:OUT.19
RXDATA_CH0_SF86outputTCELL12:OUT.10
RXDATA_CH0_SF87outputTCELL12:OUT.27
RXDATA_CH0_SF88outputTCELL12:OUT.22
RXDATA_CH0_SF89outputTCELL12:OUT.15
RXDATA_CH0_SF9outputTCELL9:OUT.5
RXDATA_CH0_SF90outputTCELL12:OUT.21
RXDATA_CH0_SF91outputTCELL12:OUT.17
RXDATA_CH0_SF92outputTCELL12:OUT.11
RXDATA_CH0_SF93outputTCELL12:OUT.7
RXDATA_CH0_SF94outputTCELL12:OUT.26
RXDATA_CH0_SF95outputTCELL12:OUT.5
RXDATA_CH0_SF96outputTCELL13:OUT.30
RXDATA_CH0_SF97outputTCELL13:OUT.31
RXDATA_CH0_SF98outputTCELL13:OUT.18
RXDATA_CH0_SF99outputTCELL13:OUT.16
RXDATA_CH1_SF0outputTCELL50:OUT.9
RXDATA_CH1_SF1outputTCELL50:OUT.19
RXDATA_CH1_SF10outputTCELL50:OUT.20
RXDATA_CH1_SF100outputTCELL46:OUT.20
RXDATA_CH1_SF101outputTCELL46:OUT.10
RXDATA_CH1_SF102outputTCELL46:OUT.28
RXDATA_CH1_SF103outputTCELL46:OUT.29
RXDATA_CH1_SF104outputTCELL46:OUT.26
RXDATA_CH1_SF105outputTCELL46:OUT.21
RXDATA_CH1_SF106outputTCELL46:OUT.25
RXDATA_CH1_SF107outputTCELL46:OUT.22
RXDATA_CH1_SF108outputTCELL46:OUT.3
RXDATA_CH1_SF109outputTCELL45:OUT.5
RXDATA_CH1_SF11outputTCELL50:OUT.11
RXDATA_CH1_SF110outputTCELL45:OUT.19
RXDATA_CH1_SF111outputTCELL45:OUT.16
RXDATA_CH1_SF112outputTCELL45:OUT.26
RXDATA_CH1_SF113outputTCELL45:OUT.2
RXDATA_CH1_SF114outputTCELL45:OUT.20
RXDATA_CH1_SF115outputTCELL45:OUT.30
RXDATA_CH1_SF116outputTCELL45:OUT.21
RXDATA_CH1_SF117outputTCELL45:OUT.28
RXDATA_CH1_SF118outputTCELL45:OUT.4
RXDATA_CH1_SF119outputTCELL45:OUT.3
RXDATA_CH1_SF12outputTCELL50:OUT.3
RXDATA_CH1_SF120outputTCELL45:OUT.9
RXDATA_CH1_SF121outputTCELL45:OUT.24
RXDATA_CH1_SF122outputTCELL45:OUT.29
RXDATA_CH1_SF123outputTCELL45:OUT.1
RXDATA_CH1_SF124outputTCELL45:OUT.10
RXDATA_CH1_SF125outputTCELL45:OUT.27
RXDATA_CH1_SF126outputTCELL44:OUT.6
RXDATA_CH1_SF127outputTCELL44:OUT.27
RXDATA_CH1_SF128outputTCELL44:OUT.17
RXDATA_CH1_SF129outputTCELL44:OUT.16
RXDATA_CH1_SF13outputTCELL50:OUT.13
RXDATA_CH1_SF130outputTCELL44:OUT.14
RXDATA_CH1_SF131outputTCELL44:OUT.23
RXDATA_CH1_SF132outputTCELL44:OUT.18
RXDATA_CH1_SF133outputTCELL44:OUT.7
RXDATA_CH1_SF134outputTCELL44:OUT.8
RXDATA_CH1_SF135outputTCELL44:OUT.10
RXDATA_CH1_SF136outputTCELL44:OUT.4
RXDATA_CH1_SF137outputTCELL44:OUT.20
RXDATA_CH1_SF138outputTCELL44:OUT.12
RXDATA_CH1_SF139outputTCELL44:OUT.24
RXDATA_CH1_SF14outputTCELL50:OUT.2
RXDATA_CH1_SF140outputTCELL44:OUT.1
RXDATA_CH1_SF141outputTCELL44:OUT.26
RXDATA_CH1_SF142outputTCELL44:OUT.29
RXDATA_CH1_SF143outputTCELL43:OUT.16
RXDATA_CH1_SF144outputTCELL43:OUT.0
RXDATA_CH1_SF145outputTCELL43:OUT.20
RXDATA_CH1_SF146outputTCELL43:OUT.21
RXDATA_CH1_SF147outputTCELL43:OUT.15
RXDATA_CH1_SF148outputTCELL43:OUT.27
RXDATA_CH1_SF149outputTCELL43:OUT.29
RXDATA_CH1_SF15outputTCELL50:OUT.5
RXDATA_CH1_SF150outputTCELL43:OUT.2
RXDATA_CH1_SF151outputTCELL43:OUT.25
RXDATA_CH1_SF152outputTCELL43:OUT.22
RXDATA_CH1_SF153outputTCELL43:OUT.24
RXDATA_CH1_SF154outputTCELL43:OUT.3
RXDATA_CH1_SF155outputTCELL42:OUT.7
RXDATA_CH1_SF156outputTCELL42:OUT.3
RXDATA_CH1_SF157outputTCELL42:OUT.17
RXDATA_CH1_SF158outputTCELL42:OUT.6
RXDATA_CH1_SF159outputTCELL42:OUT.18
RXDATA_CH1_SF16outputTCELL50:OUT.25
RXDATA_CH1_SF160outputTCELL42:OUT.12
RXDATA_CH1_SF161outputTCELL42:OUT.5
RXDATA_CH1_SF162outputTCELL42:OUT.20
RXDATA_CH1_SF163outputTCELL42:OUT.16
RXDATA_CH1_SF164outputTCELL42:OUT.11
RXDATA_CH1_SF165outputTCELL42:OUT.23
RXDATA_CH1_SF166outputTCELL42:OUT.0
RXDATA_CH1_SF167outputTCELL42:OUT.22
RXDATA_CH1_SF168outputTCELL42:OUT.31
RXDATA_CH1_SF169outputTCELL42:OUT.15
RXDATA_CH1_SF17outputTCELL50:OUT.7
RXDATA_CH1_SF170outputTCELL42:OUT.24
RXDATA_CH1_SF171outputTCELL42:OUT.1
RXDATA_CH1_SF172outputTCELL42:OUT.27
RXDATA_CH1_SF173outputTCELL42:OUT.2
RXDATA_CH1_SF174outputTCELL41:OUT.16
RXDATA_CH1_SF175outputTCELL41:OUT.17
RXDATA_CH1_SF176outputTCELL41:OUT.24
RXDATA_CH1_SF177outputTCELL41:OUT.22
RXDATA_CH1_SF178outputTCELL41:OUT.11
RXDATA_CH1_SF179outputTCELL41:OUT.7
RXDATA_CH1_SF18outputTCELL50:OUT.15
RXDATA_CH1_SF180outputTCELL41:OUT.10
RXDATA_CH1_SF181outputTCELL41:OUT.5
RXDATA_CH1_SF182outputTCELL41:OUT.15
RXDATA_CH1_SF183outputTCELL41:OUT.21
RXDATA_CH1_SF184outputTCELL41:OUT.30
RXDATA_CH1_SF185outputTCELL41:OUT.9
RXDATA_CH1_SF186outputTCELL41:OUT.25
RXDATA_CH1_SF187outputTCELL41:OUT.12
RXDATA_CH1_SF188outputTCELL41:OUT.26
RXDATA_CH1_SF189outputTCELL41:OUT.18
RXDATA_CH1_SF19outputTCELL50:OUT.0
RXDATA_CH1_SF190outputTCELL41:OUT.4
RXDATA_CH1_SF191outputTCELL41:OUT.29
RXDATA_CH1_SF192outputTCELL41:OUT.14
RXDATA_CH1_SF193outputTCELL41:OUT.2
RXDATA_CH1_SF194outputTCELL41:OUT.19
RXDATA_CH1_SF195outputTCELL41:OUT.1
RXDATA_CH1_SF196outputTCELL41:OUT.23
RXDATA_CH1_SF197outputTCELL41:OUT.13
RXDATA_CH1_SF198outputTCELL41:OUT.8
RXDATA_CH1_SF199outputTCELL41:OUT.20
RXDATA_CH1_SF2outputTCELL50:OUT.1
RXDATA_CH1_SF20outputTCELL50:OUT.8
RXDATA_CH1_SF200outputTCELL41:OUT.28
RXDATA_CH1_SF201outputTCELL41:OUT.3
RXDATA_CH1_SF202outputTCELL40:OUT.9
RXDATA_CH1_SF203outputTCELL39:OUT.16
RXDATA_CH1_SF204outputTCELL39:OUT.27
RXDATA_CH1_SF205outputTCELL39:OUT.11
RXDATA_CH1_SF206outputTCELL39:OUT.12
RXDATA_CH1_SF207outputTCELL39:OUT.13
RXDATA_CH1_SF208outputTCELL39:OUT.31
RXDATA_CH1_SF209outputTCELL39:OUT.7
RXDATA_CH1_SF21outputTCELL50:OUT.24
RXDATA_CH1_SF210outputTCELL38:OUT.17
RXDATA_CH1_SF211outputTCELL38:OUT.16
RXDATA_CH1_SF212outputTCELL38:OUT.21
RXDATA_CH1_SF213outputTCELL38:OUT.6
RXDATA_CH1_SF214outputTCELL38:OUT.11
RXDATA_CH1_SF215outputTCELL38:OUT.4
RXDATA_CH1_SF216outputTCELL38:OUT.19
RXDATA_CH1_SF217outputTCELL38:OUT.30
RXDATA_CH1_SF218outputTCELL38:OUT.14
RXDATA_CH1_SF219outputTCELL38:OUT.26
RXDATA_CH1_SF22outputTCELL50:OUT.30
RXDATA_CH1_SF220outputTCELL38:OUT.3
RXDATA_CH1_SF221outputTCELL38:OUT.0
RXDATA_CH1_SF222outputTCELL38:OUT.12
RXDATA_CH1_SF223outputTCELL38:OUT.1
RXDATA_CH1_SF224outputTCELL38:OUT.10
RXDATA_CH1_SF225outputTCELL38:OUT.2
RXDATA_CH1_SF226outputTCELL38:OUT.23
RXDATA_CH1_SF227outputTCELL38:OUT.24
RXDATA_CH1_SF228outputTCELL38:OUT.25
RXDATA_CH1_SF229outputTCELL38:OUT.27
RXDATA_CH1_SF23outputTCELL50:OUT.14
RXDATA_CH1_SF230outputTCELL37:OUT.24
RXDATA_CH1_SF231outputTCELL37:OUT.20
RXDATA_CH1_SF232outputTCELL37:OUT.28
RXDATA_CH1_SF233outputTCELL37:OUT.30
RXDATA_CH1_SF234outputTCELL37:OUT.16
RXDATA_CH1_SF235outputTCELL37:OUT.23
RXDATA_CH1_SF236outputTCELL37:OUT.4
RXDATA_CH1_SF237outputTCELL37:OUT.25
RXDATA_CH1_SF238outputTCELL37:OUT.0
RXDATA_CH1_SF239outputTCELL37:OUT.22
RXDATA_CH1_SF24outputTCELL50:OUT.6
RXDATA_CH1_SF240outputTCELL37:OUT.15
RXDATA_CH1_SF241outputTCELL37:OUT.7
RXDATA_CH1_SF242outputTCELL37:OUT.26
RXDATA_CH1_SF243outputTCELL37:OUT.21
RXDATA_CH1_SF244outputTCELL37:OUT.31
RXDATA_CH1_SF245outputTCELL37:OUT.6
RXDATA_CH1_SF246outputTCELL37:OUT.5
RXDATA_CH1_SF247outputTCELL37:OUT.17
RXDATA_CH1_SF248outputTCELL37:OUT.3
RXDATA_CH1_SF249outputTCELL37:OUT.11
RXDATA_CH1_SF25outputTCELL50:OUT.29
RXDATA_CH1_SF250outputTCELL37:OUT.18
RXDATA_CH1_SF251outputTCELL37:OUT.29
RXDATA_CH1_SF252outputTCELL37:OUT.13
RXDATA_CH1_SF253outputTCELL37:OUT.8
RXDATA_CH1_SF254outputTCELL37:OUT.9
RXDATA_CH1_SF255outputTCELL37:OUT.19
RXDATA_CH1_SF26outputTCELL50:OUT.27
RXDATA_CH1_SF27outputTCELL49:OUT.28
RXDATA_CH1_SF28outputTCELL49:OUT.16
RXDATA_CH1_SF29outputTCELL49:OUT.27
RXDATA_CH1_SF3outputTCELL50:OUT.16
RXDATA_CH1_SF30outputTCELL49:OUT.14
RXDATA_CH1_SF31outputTCELL49:OUT.13
RXDATA_CH1_SF32outputTCELL49:OUT.12
RXDATA_CH1_SF33outputTCELL49:OUT.10
RXDATA_CH1_SF34outputTCELL49:OUT.4
RXDATA_CH1_SF35outputTCELL49:OUT.21
RXDATA_CH1_SF36outputTCELL49:OUT.26
RXDATA_CH1_SF37outputTCELL49:OUT.29
RXDATA_CH1_SF38outputTCELL49:OUT.9
RXDATA_CH1_SF39outputTCELL49:OUT.25
RXDATA_CH1_SF4outputTCELL50:OUT.17
RXDATA_CH1_SF40outputTCELL49:OUT.5
RXDATA_CH1_SF41outputTCELL49:OUT.31
RXDATA_CH1_SF42outputTCELL49:OUT.30
RXDATA_CH1_SF43outputTCELL49:OUT.8
RXDATA_CH1_SF44outputTCELL49:OUT.20
RXDATA_CH1_SF45outputTCELL49:OUT.22
RXDATA_CH1_SF46outputTCELL49:OUT.6
RXDATA_CH1_SF47outputTCELL49:OUT.2
RXDATA_CH1_SF48outputTCELL49:OUT.24
RXDATA_CH1_SF49outputTCELL49:OUT.1
RXDATA_CH1_SF5outputTCELL50:OUT.12
RXDATA_CH1_SF50outputTCELL49:OUT.7
RXDATA_CH1_SF51outputTCELL49:OUT.19
RXDATA_CH1_SF52outputTCELL49:OUT.3
RXDATA_CH1_SF53outputTCELL49:OUT.17
RXDATA_CH1_SF54outputTCELL49:OUT.23
RXDATA_CH1_SF55outputTCELL48:OUT.9
RXDATA_CH1_SF56outputTCELL48:OUT.11
RXDATA_CH1_SF57outputTCELL48:OUT.30
RXDATA_CH1_SF58outputTCELL48:OUT.31
RXDATA_CH1_SF59outputTCELL48:OUT.24
RXDATA_CH1_SF6outputTCELL50:OUT.23
RXDATA_CH1_SF60outputTCELL48:OUT.15
RXDATA_CH1_SF61outputTCELL48:OUT.19
RXDATA_CH1_SF62outputTCELL48:OUT.23
RXDATA_CH1_SF63outputTCELL48:OUT.20
RXDATA_CH1_SF64outputTCELL48:OUT.12
RXDATA_CH1_SF65outputTCELL48:OUT.22
RXDATA_CH1_SF66outputTCELL48:OUT.18
RXDATA_CH1_SF67outputTCELL48:OUT.1
RXDATA_CH1_SF68outputTCELL48:OUT.10
RXDATA_CH1_SF69outputTCELL48:OUT.2
RXDATA_CH1_SF7outputTCELL50:OUT.18
RXDATA_CH1_SF70outputTCELL48:OUT.13
RXDATA_CH1_SF71outputTCELL48:OUT.29
RXDATA_CH1_SF72outputTCELL48:OUT.27
RXDATA_CH1_SF73outputTCELL48:OUT.25
RXDATA_CH1_SF74outputTCELL48:OUT.16
RXDATA_CH1_SF75outputTCELL48:OUT.8
RXDATA_CH1_SF76outputTCELL48:OUT.0
RXDATA_CH1_SF77outputTCELL48:OUT.14
RXDATA_CH1_SF78outputTCELL48:OUT.17
RXDATA_CH1_SF79outputTCELL47:OUT.31
RXDATA_CH1_SF8outputTCELL50:OUT.21
RXDATA_CH1_SF80outputTCELL47:OUT.18
RXDATA_CH1_SF81outputTCELL47:OUT.22
RXDATA_CH1_SF82outputTCELL47:OUT.11
RXDATA_CH1_SF83outputTCELL47:OUT.30
RXDATA_CH1_SF84outputTCELL47:OUT.13
RXDATA_CH1_SF85outputTCELL47:OUT.12
RXDATA_CH1_SF86outputTCELL47:OUT.21
RXDATA_CH1_SF87outputTCELL47:OUT.4
RXDATA_CH1_SF88outputTCELL47:OUT.9
RXDATA_CH1_SF89outputTCELL47:OUT.16
RXDATA_CH1_SF9outputTCELL50:OUT.26
RXDATA_CH1_SF90outputTCELL47:OUT.10
RXDATA_CH1_SF91outputTCELL47:OUT.14
RXDATA_CH1_SF92outputTCELL47:OUT.20
RXDATA_CH1_SF93outputTCELL47:OUT.24
RXDATA_CH1_SF94outputTCELL47:OUT.5
RXDATA_CH1_SF95outputTCELL47:OUT.26
RXDATA_CH1_SF96outputTCELL46:OUT.1
RXDATA_CH1_SF97outputTCELL46:OUT.0
RXDATA_CH1_SF98outputTCELL46:OUT.13
RXDATA_CH1_SF99outputTCELL46:OUT.15
RXDATA_FLAGS_CH0_SF0outputTCELL9:OUT.3
RXDATA_FLAGS_CH0_SF1outputTCELL21:OUT.18
RXDATA_FLAGS_CH0_SF2outputTCELL21:OUT.2
RXDATA_FLAGS_CH0_SF3outputTCELL22:OUT.30
RXDATA_FLAGS_CH1_SF0outputTCELL50:OUT.28
RXDATA_FLAGS_CH1_SF1outputTCELL38:OUT.13
RXDATA_FLAGS_CH1_SF2outputTCELL38:OUT.29
RXDATA_FLAGS_CH1_SF3outputTCELL37:OUT.1
RXDATA_IS_AM_CH0_SFoutputTCELL19:OUT.20
RXDATA_IS_AM_CH1_SFoutputTCELL40:OUT.11
RXDATA_START_CH0_SFoutputTCELL19:OUT.2
RXDATA_START_CH1_SFoutputTCELL40:OUT.29
RXEQTRAINING_CH0_FSinputTCELL22:IMUX.IMUX.3
RXEQTRAINING_CH1_FSinputTCELL37:IMUX.IMUX.41
RXOUTCKCTL_CH0_FS0inputTCELL20:IMUX.IMUX.44
RXOUTCKCTL_CH0_FS1inputTCELL20:IMUX.IMUX.32
RXOUTCKCTL_CH0_FS2inputTCELL20:IMUX.IMUX.25
RXOUTCKCTL_CH1_FS0inputTCELL39:IMUX.IMUX.18
RXOUTCKCTL_CH1_FS1inputTCELL39:IMUX.IMUX.30
RXOUTCKCTL_CH1_FS2inputTCELL39:IMUX.IMUX.11
RXPMARESETDONE_CH0_SFoutputTCELL26:OUT.18
RXPMARESETDONE_CH1_SFoutputTCELL33:OUT.13
RXPOLARITY_CH0_FSinputTCELL16:IMUX.IMUX.18
RXPOLARITY_CH1_FSinputTCELL43:IMUX.IMUX.44
RXPRBSCNTRST_CH0_FSinputTCELL18:IMUX.IMUX.40
RXPRBSCNTRST_CH1_FSinputTCELL41:IMUX.IMUX.22
RXPRBSERR_CH0_SFoutputTCELL23:OUT.4
RXPRBSERR_CH1_SFoutputTCELL36:OUT.27
RXPRBSLOCKED_CH0_SFoutputTCELL24:OUT.25
RXPRBSLOCKED_CH1_SFoutputTCELL35:OUT.6
RXPRBSPTN_CH0_FS0inputTCELL13:IMUX.IMUX.27
RXPRBSPTN_CH0_FS1inputTCELL21:IMUX.IMUX.15
RXPRBSPTN_CH0_FS2inputTCELL21:IMUX.IMUX.32
RXPRBSPTN_CH0_FS3inputTCELL22:IMUX.IMUX.41
RXPRBSPTN_CH1_FS0inputTCELL46:IMUX.IMUX.10
RXPRBSPTN_CH1_FS1inputTCELL38:IMUX.IMUX.17
RXPRBSPTN_CH1_FS2inputTCELL38:IMUX.IMUX.30
RXPRBSPTN_CH1_FS3inputTCELL37:IMUX.IMUX.3
RXPRBS_CNT_STOP_CH0_FSinputTCELL22:IMUX.IMUX.31
RXPRBS_CNT_STOP_CH1_FSinputTCELL37:IMUX.IMUX.8
RXPROGDIVRESETDONE_CH0_SFoutputTCELL19:OUT.21
RXPROGDIVRESETDONE_CH1_SFoutputTCELL40:OUT.10
RXQPRBS_ENA_CH0_FSinputTCELL16:IMUX.IMUX.30
RXQPRBS_ENA_CH1_FSinputTCELL43:IMUX.IMUX.32
RXRESETDONE_CH0_SFoutputTCELL8:OUT.11
RXRESETDONE_CH1_SFoutputTCELL51:OUT.20
RXUSRCLK2_CH0_FSinputTCELL17:IMUX.CTRL.0
RXUSRCLK2_CH1_FSinputTCELL42:IMUX.CTRL.7
RXUSRCLK_CH0_FSinputTCELL15:IMUX.CTRL.3
RXUSRCLK_CH1_FSinputTCELL44:IMUX.CTRL.4
RXUSRRDY_CH0_FSinputTCELL14:IMUX.IMUX.23
RXUSRRDY_CH1_FSinputTCELL45:IMUX.IMUX.12
RX_ADAPTRESET_CH0_FSinputTCELL21:IMUX.IMUX.13
RX_ADAPTRESET_CH1_FSinputTCELL38:IMUX.IMUX.21
RX_ADC_CALRESET_CH0_FSinputTCELL22:IMUX.IMUX.27
RX_ADC_CALRESET_CH1_FSinputTCELL37:IMUX.IMUX.10
RX_ADC_CLKGENRESET_CH0_FSinputTCELL20:IMUX.IMUX.29
RX_ADC_CLKGENRESET_CH1_FSinputTCELL39:IMUX.IMUX.9
RX_BUFRESET_CH0_FSinputTCELL26:IMUX.IMUX.17
RX_BUFRESET_CH1_FSinputTCELL33:IMUX.IMUX.15
RX_CDRFRRESET_CH0_FSinputTCELL26:IMUX.IMUX.15
RX_CDRFRRESET_CH1_FSinputTCELL33:IMUX.IMUX.17
RX_CDRPHRESET_CH0_FSinputTCELL17:IMUX.IMUX.9
RX_CDRPHRESET_CH1_FSinputTCELL42:IMUX.IMUX.29
RX_DFERESET_CH0_FSinputTCELL20:IMUX.IMUX.39
RX_DFERESET_CH1_FSinputTCELL39:IMUX.IMUX.4
RX_DSPRESET_CH0_FSinputTCELL21:IMUX.IMUX.10
RX_DSPRESET_CH1_FSinputTCELL38:IMUX.IMUX.27
RX_FECRESET_CH0_FSinputTCELL16:IMUX.IMUX.32
RX_FECRESET_CH1_FSinputTCELL43:IMUX.IMUX.30
RX_ISCANRESET_CH0_FSinputTCELL22:IMUX.IMUX.21
RX_ISCANRESET_CH1_FSinputTCELL37:IMUX.IMUX.13
RX_PCSRESET_CH0_FSinputTCELL21:IMUX.IMUX.29
RX_PCSRESET_CH1_FSinputTCELL38:IMUX.IMUX.9
RX_PCS_RESETMASK_CH0_FS0inputTCELL21:IMUX.IMUX.25
RX_PCS_RESETMASK_CH0_FS1inputTCELL21:IMUX.IMUX.37
RX_PCS_RESETMASK_CH0_FS2inputTCELL21:IMUX.IMUX.9
RX_PCS_RESETMASK_CH0_FS3inputTCELL22:IMUX.IMUX.23
RX_PCS_RESETMASK_CH1_FS0inputTCELL38:IMUX.IMUX.11
RX_PCS_RESETMASK_CH1_FS1inputTCELL38:IMUX.IMUX.5
RX_PCS_RESETMASK_CH1_FS2inputTCELL38:IMUX.IMUX.29
RX_PCS_RESETMASK_CH1_FS3inputTCELL37:IMUX.IMUX.12
RX_PCS_SEQ_ADVANCE_CH0_FSinputTCELL17:IMUX.IMUX.5
RX_PCS_SEQ_ADVANCE_CH1_FSinputTCELL42:IMUX.IMUX.37
RX_PMARESET_CH0_FSinputTCELL21:IMUX.IMUX.14
RX_PMARESET_CH1_FSinputTCELL38:IMUX.IMUX.19
RX_PMA_RESETMASK_CH0_FS0inputTCELL13:IMUX.IMUX.44
RX_PMA_RESETMASK_CH0_FS1inputTCELL13:IMUX.IMUX.43
RX_PMA_RESETMASK_CH0_FS2inputTCELL13:IMUX.IMUX.16
RX_PMA_RESETMASK_CH0_FS3inputTCELL14:IMUX.IMUX.39
RX_PMA_RESETMASK_CH0_FS4inputTCELL15:IMUX.IMUX.1
RX_PMA_RESETMASK_CH0_FS5inputTCELL15:IMUX.IMUX.17
RX_PMA_RESETMASK_CH0_FS6inputTCELL15:IMUX.IMUX.34
RX_PMA_RESETMASK_CH0_FS7inputTCELL21:IMUX.IMUX.26
RX_PMA_RESETMASK_CH1_FS0inputTCELL46:IMUX.IMUX.18
RX_PMA_RESETMASK_CH1_FS1inputTCELL46:IMUX.IMUX.2
RX_PMA_RESETMASK_CH1_FS2inputTCELL46:IMUX.IMUX.46
RX_PMA_RESETMASK_CH1_FS3inputTCELL45:IMUX.IMUX.4
RX_PMA_RESETMASK_CH1_FS4inputTCELL44:IMUX.IMUX.45
RX_PMA_RESETMASK_CH1_FS5inputTCELL44:IMUX.IMUX.15
RX_PMA_RESETMASK_CH1_FS6inputTCELL44:IMUX.IMUX.28
RX_PMA_RESETMASK_CH1_FS7inputTCELL38:IMUX.IMUX.36
RX_PROGDIVRESET_CH0_FSinputTCELL20:IMUX.IMUX.31
RX_PROGDIVRESET_CH1_FSinputTCELL39:IMUX.IMUX.8
RX_RESETMODE_CH0_FS0inputTCELL14:IMUX.IMUX.20
RX_RESETMODE_CH0_FS1inputTCELL16:IMUX.IMUX.9
RX_RESETMODE_CH1_FS0inputTCELL45:IMUX.IMUX.42
RX_RESETMODE_CH1_FS1inputTCELL43:IMUX.IMUX.29
RX_USRSTART_CH0_FSinputTCELL20:IMUX.IMUX.15
RX_USRSTART_CH1_FSinputTCELL39:IMUX.IMUX.17
RX_USRSTOP_CH0_FSinputTCELL17:IMUX.IMUX.43
RX_USRSTOP_CH1_FSinputTCELL42:IMUX.IMUX.2
SDM_DATA_FS0inputTCELL28:IMUX.IMUX.17
SDM_DATA_FS1inputTCELL28:IMUX.IMUX.19
SDM_DATA_FS10inputTCELL28:IMUX.IMUX.14
SDM_DATA_FS11inputTCELL28:IMUX.IMUX.46
SDM_DATA_FS12inputTCELL30:IMUX.IMUX.16
SDM_DATA_FS13inputTCELL30:IMUX.IMUX.19
SDM_DATA_FS14inputTCELL30:IMUX.IMUX.23
SDM_DATA_FS15inputTCELL30:IMUX.IMUX.26
SDM_DATA_FS16inputTCELL30:IMUX.IMUX.6
SDM_DATA_FS17inputTCELL30:IMUX.IMUX.36
SDM_DATA_FS18inputTCELL30:IMUX.IMUX.12
SDM_DATA_FS19inputTCELL30:IMUX.IMUX.13
SDM_DATA_FS2inputTCELL28:IMUX.IMUX.22
SDM_DATA_FS20inputTCELL30:IMUX.IMUX.15
SDM_DATA_FS21inputTCELL31:IMUX.IMUX.18
SDM_DATA_FS22inputTCELL31:IMUX.IMUX.25
SDM_DATA_FS23inputTCELL31:IMUX.IMUX.32
SDM_DATA_FS24inputTCELL31:IMUX.IMUX.38
SDM_DATA_FS25inputTCELL31:IMUX.IMUX.45
SDM_DATA_FS3inputTCELL28:IMUX.IMUX.25
SDM_DATA_FS4inputTCELL28:IMUX.IMUX.26
SDM_DATA_FS5inputTCELL28:IMUX.IMUX.29
SDM_DATA_FS6inputTCELL28:IMUX.IMUX.9
SDM_DATA_FS7inputTCELL28:IMUX.IMUX.10
SDM_DATA_FS8inputTCELL28:IMUX.IMUX.38
SDM_DATA_FS9inputTCELL28:IMUX.IMUX.41
SDM_TOGGLE_FSinputTCELL29:IMUX.IMUX.41
ST_RX0_CORR_CW_INC_SFoutputTCELL11:OUT.5
ST_RX0_CW_INC_SFoutputTCELL11:OUT.24
ST_RX0_FEC_ALIGNED_SFoutputTCELL11:OUT.26
ST_RX0_UNCORR_CW_INC_SFoutputTCELL11:OUT.28
ST_RX1_CORR_CW_INC_SFoutputTCELL48:OUT.4
ST_RX1_CW_INC_SFoutputTCELL48:OUT.6
ST_RX1_FEC_ALIGNED_SFoutputTCELL48:OUT.21
ST_RX1_UNCORR_CW_INC_SFoutputTCELL48:OUT.28
ST_RX_LN0_BIT_ERR_0TO1_INC_SF0outputTCELL12:OUT.2
ST_RX_LN0_BIT_ERR_0TO1_INC_SF1outputTCELL12:OUT.3
ST_RX_LN0_BIT_ERR_0TO1_INC_SF2outputTCELL12:OUT.8
ST_RX_LN0_BIT_ERR_0TO1_INC_SF3outputTCELL12:OUT.12
ST_RX_LN0_BIT_ERR_0TO1_INC_SF4outputTCELL12:OUT.16
ST_RX_LN0_BIT_ERR_0TO1_INC_SF5outputTCELL12:OUT.24
ST_RX_LN0_BIT_ERR_0TO1_INC_SF6outputTCELL12:OUT.28
ST_RX_LN0_BIT_ERR_0TO1_INC_SF7outputTCELL12:OUT.30
ST_RX_LN0_BIT_ERR_1TO0_INC_SF0outputTCELL14:OUT.0
ST_RX_LN0_BIT_ERR_1TO0_INC_SF1outputTCELL14:OUT.6
ST_RX_LN0_BIT_ERR_1TO0_INC_SF2outputTCELL14:OUT.13
ST_RX_LN0_BIT_ERR_1TO0_INC_SF3outputTCELL14:OUT.14
ST_RX_LN0_BIT_ERR_1TO0_INC_SF4outputTCELL14:OUT.17
ST_RX_LN0_BIT_ERR_1TO0_INC_SF5outputTCELL14:OUT.18
ST_RX_LN0_BIT_ERR_1TO0_INC_SF6outputTCELL14:OUT.23
ST_RX_LN0_BIT_ERR_1TO0_INC_SF7outputTCELL14:OUT.25
ST_RX_LN0_DELAY_SF0outputTCELL13:OUT.0
ST_RX_LN0_DELAY_SF1outputTCELL13:OUT.1
ST_RX_LN0_DELAY_SF10outputTCELL13:OUT.22
ST_RX_LN0_DELAY_SF11outputTCELL13:OUT.23
ST_RX_LN0_DELAY_SF12outputTCELL13:OUT.25
ST_RX_LN0_DELAY_SF13outputTCELL13:OUT.26
ST_RX_LN0_DELAY_SF14outputTCELL13:OUT.27
ST_RX_LN0_DELAY_SF2outputTCELL13:OUT.4
ST_RX_LN0_DELAY_SF3outputTCELL13:OUT.7
ST_RX_LN0_DELAY_SF4outputTCELL13:OUT.12
ST_RX_LN0_DELAY_SF5outputTCELL13:OUT.13
ST_RX_LN0_DELAY_SF6outputTCELL13:OUT.14
ST_RX_LN0_DELAY_SF7outputTCELL13:OUT.15
ST_RX_LN0_DELAY_SF8outputTCELL13:OUT.19
ST_RX_LN0_DELAY_SF9outputTCELL13:OUT.20
ST_RX_LN0_ERR_CNT_INC_SF0outputTCELL12:OUT.6
ST_RX_LN0_ERR_CNT_INC_SF1outputTCELL12:OUT.25
ST_RX_LN0_ERR_CNT_INC_SF2outputTCELL14:OUT.9
ST_RX_LN0_ERR_CNT_INC_SF3outputTCELL14:OUT.20
ST_RX_LN0_FEC_LOCK_SFoutputTCELL12:OUT.23
ST_RX_LN0_MAPPING_SF0outputTCELL54:OUT.8
ST_RX_LN0_MAPPING_SF1outputTCELL54:OUT.24
ST_RX_LN1_BIT_ERR_0TO1_INC_SF0outputTCELL15:OUT.0
ST_RX_LN1_BIT_ERR_0TO1_INC_SF1outputTCELL15:OUT.1
ST_RX_LN1_BIT_ERR_0TO1_INC_SF2outputTCELL15:OUT.9
ST_RX_LN1_BIT_ERR_0TO1_INC_SF3outputTCELL15:OUT.10
ST_RX_LN1_BIT_ERR_0TO1_INC_SF4outputTCELL15:OUT.18
ST_RX_LN1_BIT_ERR_0TO1_INC_SF5outputTCELL15:OUT.20
ST_RX_LN1_BIT_ERR_0TO1_INC_SF6outputTCELL15:OUT.26
ST_RX_LN1_BIT_ERR_0TO1_INC_SF7outputTCELL15:OUT.29
ST_RX_LN1_BIT_ERR_1TO0_INC_SF0outputTCELL17:OUT.1
ST_RX_LN1_BIT_ERR_1TO0_INC_SF1outputTCELL17:OUT.2
ST_RX_LN1_BIT_ERR_1TO0_INC_SF2outputTCELL17:OUT.5
ST_RX_LN1_BIT_ERR_1TO0_INC_SF3outputTCELL17:OUT.6
ST_RX_LN1_BIT_ERR_1TO0_INC_SF4outputTCELL17:OUT.12
ST_RX_LN1_BIT_ERR_1TO0_INC_SF5outputTCELL17:OUT.18
ST_RX_LN1_BIT_ERR_1TO0_INC_SF6outputTCELL17:OUT.21
ST_RX_LN1_BIT_ERR_1TO0_INC_SF7outputTCELL17:OUT.23
ST_RX_LN1_DELAY_SF0outputTCELL16:OUT.0
ST_RX_LN1_DELAY_SF1outputTCELL16:OUT.1
ST_RX_LN1_DELAY_SF10outputTCELL16:OUT.22
ST_RX_LN1_DELAY_SF11outputTCELL16:OUT.23
ST_RX_LN1_DELAY_SF12outputTCELL16:OUT.25
ST_RX_LN1_DELAY_SF13outputTCELL16:OUT.26
ST_RX_LN1_DELAY_SF14outputTCELL16:OUT.27
ST_RX_LN1_DELAY_SF2outputTCELL16:OUT.3
ST_RX_LN1_DELAY_SF3outputTCELL16:OUT.5
ST_RX_LN1_DELAY_SF4outputTCELL16:OUT.12
ST_RX_LN1_DELAY_SF5outputTCELL16:OUT.13
ST_RX_LN1_DELAY_SF6outputTCELL16:OUT.14
ST_RX_LN1_DELAY_SF7outputTCELL16:OUT.17
ST_RX_LN1_DELAY_SF8outputTCELL16:OUT.20
ST_RX_LN1_DELAY_SF9outputTCELL16:OUT.21
ST_RX_LN1_ERR_CNT_INC_SF0outputTCELL15:OUT.3
ST_RX_LN1_ERR_CNT_INC_SF1outputTCELL15:OUT.16
ST_RX_LN1_ERR_CNT_INC_SF2outputTCELL15:OUT.28
ST_RX_LN1_ERR_CNT_INC_SF3outputTCELL16:OUT.19
ST_RX_LN1_FEC_LOCK_SFoutputTCELL17:OUT.17
ST_RX_LN1_MAPPING_SF0outputTCELL32:OUT.10
ST_RX_LN1_MAPPING_SF1outputTCELL35:OUT.18
ST_RX_LN2_BIT_ERR_0TO1_INC_SF0outputTCELL42:OUT.4
ST_RX_LN2_BIT_ERR_0TO1_INC_SF1outputTCELL42:OUT.8
ST_RX_LN2_BIT_ERR_0TO1_INC_SF2outputTCELL42:OUT.10
ST_RX_LN2_BIT_ERR_0TO1_INC_SF3outputTCELL42:OUT.13
ST_RX_LN2_BIT_ERR_0TO1_INC_SF4outputTCELL42:OUT.19
ST_RX_LN2_BIT_ERR_0TO1_INC_SF5outputTCELL42:OUT.25
ST_RX_LN2_BIT_ERR_0TO1_INC_SF6outputTCELL42:OUT.26
ST_RX_LN2_BIT_ERR_0TO1_INC_SF7outputTCELL42:OUT.29
ST_RX_LN2_BIT_ERR_1TO0_INC_SF0outputTCELL44:OUT.0
ST_RX_LN2_BIT_ERR_1TO0_INC_SF1outputTCELL44:OUT.2
ST_RX_LN2_BIT_ERR_1TO0_INC_SF2outputTCELL44:OUT.9
ST_RX_LN2_BIT_ERR_1TO0_INC_SF3outputTCELL44:OUT.11
ST_RX_LN2_BIT_ERR_1TO0_INC_SF4outputTCELL44:OUT.19
ST_RX_LN2_BIT_ERR_1TO0_INC_SF5outputTCELL44:OUT.21
ST_RX_LN2_BIT_ERR_1TO0_INC_SF6outputTCELL44:OUT.25
ST_RX_LN2_BIT_ERR_1TO0_INC_SF7outputTCELL44:OUT.30
ST_RX_LN2_DELAY_SF0outputTCELL43:OUT.1
ST_RX_LN2_DELAY_SF1outputTCELL43:OUT.4
ST_RX_LN2_DELAY_SF10outputTCELL43:OUT.18
ST_RX_LN2_DELAY_SF11outputTCELL43:OUT.19
ST_RX_LN2_DELAY_SF12outputTCELL43:OUT.26
ST_RX_LN2_DELAY_SF13outputTCELL43:OUT.28
ST_RX_LN2_DELAY_SF14outputTCELL43:OUT.30
ST_RX_LN2_DELAY_SF2outputTCELL43:OUT.5
ST_RX_LN2_DELAY_SF3outputTCELL43:OUT.6
ST_RX_LN2_DELAY_SF4outputTCELL43:OUT.8
ST_RX_LN2_DELAY_SF5outputTCELL43:OUT.9
ST_RX_LN2_DELAY_SF6outputTCELL43:OUT.10
ST_RX_LN2_DELAY_SF7outputTCELL43:OUT.11
ST_RX_LN2_DELAY_SF8outputTCELL43:OUT.14
ST_RX_LN2_DELAY_SF9outputTCELL43:OUT.17
ST_RX_LN2_ERR_CNT_INC_SF0outputTCELL43:OUT.13
ST_RX_LN2_ERR_CNT_INC_SF1outputTCELL44:OUT.3
ST_RX_LN2_ERR_CNT_INC_SF2outputTCELL44:OUT.15
ST_RX_LN2_ERR_CNT_INC_SF3outputTCELL44:OUT.28
ST_RX_LN2_FEC_LOCK_SFoutputTCELL42:OUT.21
ST_RX_LN2_MAPPING_SF0outputTCELL24:OUT.13
ST_RX_LN2_MAPPING_SF1outputTCELL53:OUT.15
ST_RX_LN3_BIT_ERR_0TO1_INC_SF0outputTCELL45:OUT.0
ST_RX_LN3_BIT_ERR_0TO1_INC_SF1outputTCELL45:OUT.6
ST_RX_LN3_BIT_ERR_0TO1_INC_SF2outputTCELL45:OUT.12
ST_RX_LN3_BIT_ERR_0TO1_INC_SF3outputTCELL45:OUT.13
ST_RX_LN3_BIT_ERR_0TO1_INC_SF4outputTCELL45:OUT.15
ST_RX_LN3_BIT_ERR_0TO1_INC_SF5outputTCELL45:OUT.17
ST_RX_LN3_BIT_ERR_0TO1_INC_SF6outputTCELL45:OUT.23
ST_RX_LN3_BIT_ERR_0TO1_INC_SF7outputTCELL45:OUT.25
ST_RX_LN3_BIT_ERR_1TO0_INC_SF0outputTCELL47:OUT.0
ST_RX_LN3_BIT_ERR_1TO0_INC_SF1outputTCELL47:OUT.1
ST_RX_LN3_BIT_ERR_1TO0_INC_SF2outputTCELL47:OUT.6
ST_RX_LN3_BIT_ERR_1TO0_INC_SF3outputTCELL47:OUT.7
ST_RX_LN3_BIT_ERR_1TO0_INC_SF4outputTCELL47:OUT.15
ST_RX_LN3_BIT_ERR_1TO0_INC_SF5outputTCELL47:OUT.19
ST_RX_LN3_BIT_ERR_1TO0_INC_SF6outputTCELL47:OUT.25
ST_RX_LN3_BIT_ERR_1TO0_INC_SF7outputTCELL47:OUT.28
ST_RX_LN3_DELAY_SF0outputTCELL46:OUT.2
ST_RX_LN3_DELAY_SF1outputTCELL46:OUT.4
ST_RX_LN3_DELAY_SF10outputTCELL46:OUT.18
ST_RX_LN3_DELAY_SF11outputTCELL46:OUT.19
ST_RX_LN3_DELAY_SF12outputTCELL46:OUT.24
ST_RX_LN3_DELAY_SF13outputTCELL46:OUT.27
ST_RX_LN3_DELAY_SF14outputTCELL46:OUT.30
ST_RX_LN3_DELAY_SF2outputTCELL46:OUT.5
ST_RX_LN3_DELAY_SF3outputTCELL46:OUT.6
ST_RX_LN3_DELAY_SF4outputTCELL46:OUT.8
ST_RX_LN3_DELAY_SF5outputTCELL46:OUT.9
ST_RX_LN3_DELAY_SF6outputTCELL46:OUT.11
ST_RX_LN3_DELAY_SF7outputTCELL46:OUT.12
ST_RX_LN3_DELAY_SF8outputTCELL46:OUT.16
ST_RX_LN3_DELAY_SF9outputTCELL46:OUT.17
ST_RX_LN3_ERR_CNT_INC_SF0outputTCELL45:OUT.11
ST_RX_LN3_ERR_CNT_INC_SF1outputTCELL45:OUT.22
ST_RX_LN3_ERR_CNT_INC_SF2outputTCELL47:OUT.3
ST_RX_LN3_ERR_CNT_INC_SF3outputTCELL47:OUT.23
ST_RX_LN3_FEC_LOCK_SFoutputTCELL47:OUT.17
ST_RX_LN3_MAPPING_SF0outputTCELL25:OUT.14
ST_RX_LN3_MAPPING_SF1outputTCELL54:OUT.16
TSTCLK0_CH0_FSinputTCELL6:IMUX.CTRL.7
TSTCLK0_CH1_FSinputTCELL53:IMUX.CTRL.0
TSTCLK1_CH0_FSinputTCELL8:IMUX.CTRL.3
TSTCLK1_CH1_FSinputTCELL51:IMUX.CTRL.4
TXBUFSTATUS_CH0_SF0outputTCELL24:OUT.24
TXBUFSTATUS_CH0_SF1outputTCELL26:OUT.8
TXBUFSTATUS_CH1_SF0outputTCELL35:OUT.7
TXBUFSTATUS_CH1_SF1outputTCELL33:OUT.23
TXCTLFIRDAT_CH0_FS0inputTCELL23:IMUX.IMUX.30
TXCTLFIRDAT_CH0_FS1inputTCELL23:IMUX.IMUX.46
TXCTLFIRDAT_CH0_FS2inputTCELL23:IMUX.IMUX.11
TXCTLFIRDAT_CH0_FS3inputTCELL23:IMUX.IMUX.39
TXCTLFIRDAT_CH0_FS4inputTCELL23:IMUX.IMUX.36
TXCTLFIRDAT_CH0_FS5inputTCELL23:IMUX.IMUX.22
TXCTLFIRDAT_CH1_FS0inputTCELL36:IMUX.IMUX.32
TXCTLFIRDAT_CH1_FS1inputTCELL36:IMUX.IMUX.16
TXCTLFIRDAT_CH1_FS2inputTCELL36:IMUX.IMUX.25
TXCTLFIRDAT_CH1_FS3inputTCELL36:IMUX.IMUX.4
TXCTLFIRDAT_CH1_FS4inputTCELL36:IMUX.IMUX.26
TXCTLFIRDAT_CH1_FS5inputTCELL36:IMUX.IMUX.40
TXDATA_CH0_FS0inputTCELL5:IMUX.IMUX.47
TXDATA_CH0_FS1inputTCELL5:IMUX.IMUX.39
TXDATA_CH0_FS10inputTCELL5:IMUX.IMUX.31
TXDATA_CH0_FS100inputTCELL7:IMUX.IMUX.5
TXDATA_CH0_FS101inputTCELL7:IMUX.IMUX.9
TXDATA_CH0_FS102inputTCELL7:IMUX.IMUX.18
TXDATA_CH0_FS103inputTCELL7:IMUX.IMUX.45
TXDATA_CH0_FS104inputTCELL7:IMUX.IMUX.3
TXDATA_CH0_FS105inputTCELL7:IMUX.IMUX.14
TXDATA_CH0_FS106inputTCELL7:IMUX.IMUX.38
TXDATA_CH0_FS107inputTCELL7:IMUX.IMUX.2
TXDATA_CH0_FS108inputTCELL7:IMUX.IMUX.43
TXDATA_CH0_FS109inputTCELL7:IMUX.IMUX.30
TXDATA_CH0_FS11inputTCELL5:IMUX.IMUX.36
TXDATA_CH0_FS110inputTCELL7:IMUX.IMUX.10
TXDATA_CH0_FS111inputTCELL8:IMUX.IMUX.10
TXDATA_CH0_FS112inputTCELL8:IMUX.IMUX.19
TXDATA_CH0_FS113inputTCELL8:IMUX.IMUX.3
TXDATA_CH0_FS114inputTCELL8:IMUX.IMUX.23
TXDATA_CH0_FS115inputTCELL8:IMUX.IMUX.27
TXDATA_CH0_FS116inputTCELL8:IMUX.IMUX.16
TXDATA_CH0_FS117inputTCELL8:IMUX.IMUX.31
TXDATA_CH0_FS118inputTCELL8:IMUX.IMUX.24
TXDATA_CH0_FS119inputTCELL8:IMUX.IMUX.9
TXDATA_CH0_FS12inputTCELL5:IMUX.IMUX.38
TXDATA_CH0_FS120inputTCELL8:IMUX.IMUX.11
TXDATA_CH0_FS121inputTCELL8:IMUX.IMUX.17
TXDATA_CH0_FS122inputTCELL8:IMUX.IMUX.0
TXDATA_CH0_FS123inputTCELL8:IMUX.IMUX.28
TXDATA_CH0_FS124inputTCELL8:IMUX.IMUX.42
TXDATA_CH0_FS125inputTCELL8:IMUX.IMUX.33
TXDATA_CH0_FS126inputTCELL8:IMUX.IMUX.6
TXDATA_CH0_FS127inputTCELL8:IMUX.IMUX.13
TXDATA_CH0_FS128inputTCELL8:IMUX.IMUX.12
TXDATA_CH0_FS129inputTCELL8:IMUX.IMUX.4
TXDATA_CH0_FS13inputTCELL5:IMUX.IMUX.8
TXDATA_CH0_FS130inputTCELL8:IMUX.IMUX.46
TXDATA_CH0_FS131inputTCELL8:IMUX.IMUX.15
TXDATA_CH0_FS132inputTCELL8:IMUX.IMUX.1
TXDATA_CH0_FS133inputTCELL8:IMUX.IMUX.38
TXDATA_CH0_FS134inputTCELL8:IMUX.IMUX.43
TXDATA_CH0_FS135inputTCELL8:IMUX.IMUX.41
TXDATA_CH0_FS136inputTCELL8:IMUX.IMUX.32
TXDATA_CH0_FS137inputTCELL8:IMUX.IMUX.20
TXDATA_CH0_FS138inputTCELL8:IMUX.IMUX.25
TXDATA_CH0_FS139inputTCELL8:IMUX.IMUX.22
TXDATA_CH0_FS14inputTCELL5:IMUX.IMUX.32
TXDATA_CH0_FS140inputTCELL8:IMUX.IMUX.30
TXDATA_CH0_FS141inputTCELL8:IMUX.IMUX.37
TXDATA_CH0_FS142inputTCELL8:IMUX.IMUX.18
TXDATA_CH0_FS143inputTCELL8:IMUX.IMUX.44
TXDATA_CH0_FS144inputTCELL8:IMUX.IMUX.47
TXDATA_CH0_FS145inputTCELL8:IMUX.IMUX.45
TXDATA_CH0_FS146inputTCELL8:IMUX.IMUX.34
TXDATA_CH0_FS147inputTCELL8:IMUX.IMUX.26
TXDATA_CH0_FS148inputTCELL8:IMUX.IMUX.7
TXDATA_CH0_FS149inputTCELL9:IMUX.IMUX.25
TXDATA_CH0_FS15inputTCELL5:IMUX.IMUX.12
TXDATA_CH0_FS150inputTCELL9:IMUX.IMUX.37
TXDATA_CH0_FS151inputTCELL9:IMUX.IMUX.9
TXDATA_CH0_FS152inputTCELL9:IMUX.IMUX.45
TXDATA_CH0_FS153inputTCELL9:IMUX.IMUX.29
TXDATA_CH0_FS154inputTCELL9:IMUX.IMUX.28
TXDATA_CH0_FS155inputTCELL9:IMUX.IMUX.14
TXDATA_CH0_FS156inputTCELL9:IMUX.IMUX.1
TXDATA_CH0_FS157inputTCELL9:IMUX.IMUX.27
TXDATA_CH0_FS158inputTCELL9:IMUX.IMUX.22
TXDATA_CH0_FS159inputTCELL9:IMUX.IMUX.5
TXDATA_CH0_FS16inputTCELL5:IMUX.IMUX.43
TXDATA_CH0_FS160inputTCELL9:IMUX.IMUX.41
TXDATA_CH0_FS161inputTCELL9:IMUX.IMUX.0
TXDATA_CH0_FS162inputTCELL9:IMUX.IMUX.11
TXDATA_CH0_FS163inputTCELL9:IMUX.IMUX.12
TXDATA_CH0_FS164inputTCELL9:IMUX.IMUX.35
TXDATA_CH0_FS165inputTCELL9:IMUX.IMUX.8
TXDATA_CH0_FS166inputTCELL9:IMUX.IMUX.10
TXDATA_CH0_FS167inputTCELL9:IMUX.IMUX.47
TXDATA_CH0_FS168inputTCELL9:IMUX.IMUX.21
TXDATA_CH0_FS169inputTCELL9:IMUX.IMUX.26
TXDATA_CH0_FS17inputTCELL5:IMUX.IMUX.22
TXDATA_CH0_FS170inputTCELL9:IMUX.IMUX.34
TXDATA_CH0_FS171inputTCELL9:IMUX.IMUX.16
TXDATA_CH0_FS172inputTCELL9:IMUX.IMUX.24
TXDATA_CH0_FS173inputTCELL9:IMUX.IMUX.6
TXDATA_CH0_FS174inputTCELL9:IMUX.IMUX.7
TXDATA_CH0_FS175inputTCELL9:IMUX.IMUX.43
TXDATA_CH0_FS176inputTCELL9:IMUX.IMUX.39
TXDATA_CH0_FS177inputTCELL9:IMUX.IMUX.13
TXDATA_CH0_FS178inputTCELL9:IMUX.IMUX.33
TXDATA_CH0_FS179inputTCELL9:IMUX.IMUX.31
TXDATA_CH0_FS18inputTCELL5:IMUX.IMUX.24
TXDATA_CH0_FS180inputTCELL9:IMUX.IMUX.3
TXDATA_CH0_FS181inputTCELL9:IMUX.IMUX.18
TXDATA_CH0_FS182inputTCELL9:IMUX.IMUX.32
TXDATA_CH0_FS183inputTCELL10:IMUX.IMUX.5
TXDATA_CH0_FS184inputTCELL10:IMUX.IMUX.31
TXDATA_CH0_FS185inputTCELL10:IMUX.IMUX.20
TXDATA_CH0_FS186inputTCELL10:IMUX.IMUX.30
TXDATA_CH0_FS187inputTCELL10:IMUX.IMUX.21
TXDATA_CH0_FS188inputTCELL10:IMUX.IMUX.40
TXDATA_CH0_FS189inputTCELL10:IMUX.IMUX.2
TXDATA_CH0_FS19inputTCELL5:IMUX.IMUX.3
TXDATA_CH0_FS190inputTCELL10:IMUX.IMUX.16
TXDATA_CH0_FS191inputTCELL10:IMUX.IMUX.6
TXDATA_CH0_FS192inputTCELL10:IMUX.IMUX.22
TXDATA_CH0_FS193inputTCELL10:IMUX.IMUX.23
TXDATA_CH0_FS194inputTCELL10:IMUX.IMUX.41
TXDATA_CH0_FS195inputTCELL10:IMUX.IMUX.27
TXDATA_CH0_FS196inputTCELL10:IMUX.IMUX.33
TXDATA_CH0_FS197inputTCELL10:IMUX.IMUX.34
TXDATA_CH0_FS198inputTCELL10:IMUX.IMUX.9
TXDATA_CH0_FS199inputTCELL10:IMUX.IMUX.10
TXDATA_CH0_FS2inputTCELL5:IMUX.IMUX.17
TXDATA_CH0_FS20inputTCELL5:IMUX.IMUX.33
TXDATA_CH0_FS200inputTCELL10:IMUX.IMUX.32
TXDATA_CH0_FS201inputTCELL10:IMUX.IMUX.29
TXDATA_CH0_FS202inputTCELL10:IMUX.IMUX.0
TXDATA_CH0_FS203inputTCELL10:IMUX.IMUX.1
TXDATA_CH0_FS204inputTCELL10:IMUX.IMUX.35
TXDATA_CH0_FS205inputTCELL10:IMUX.IMUX.8
TXDATA_CH0_FS206inputTCELL10:IMUX.IMUX.44
TXDATA_CH0_FS207inputTCELL10:IMUX.IMUX.28
TXDATA_CH0_FS208inputTCELL10:IMUX.IMUX.17
TXDATA_CH0_FS209inputTCELL10:IMUX.IMUX.19
TXDATA_CH0_FS21inputTCELL5:IMUX.IMUX.5
TXDATA_CH0_FS210inputTCELL10:IMUX.IMUX.43
TXDATA_CH0_FS211inputTCELL10:IMUX.IMUX.25
TXDATA_CH0_FS212inputTCELL10:IMUX.IMUX.26
TXDATA_CH0_FS213inputTCELL10:IMUX.IMUX.14
TXDATA_CH0_FS214inputTCELL10:IMUX.IMUX.42
TXDATA_CH0_FS215inputTCELL10:IMUX.IMUX.12
TXDATA_CH0_FS216inputTCELL10:IMUX.IMUX.7
TXDATA_CH0_FS217inputTCELL10:IMUX.IMUX.15
TXDATA_CH0_FS218inputTCELL11:IMUX.IMUX.10
TXDATA_CH0_FS219inputTCELL11:IMUX.IMUX.31
TXDATA_CH0_FS22inputTCELL5:IMUX.IMUX.20
TXDATA_CH0_FS220inputTCELL11:IMUX.IMUX.4
TXDATA_CH0_FS221inputTCELL11:IMUX.IMUX.39
TXDATA_CH0_FS222inputTCELL11:IMUX.IMUX.3
TXDATA_CH0_FS223inputTCELL11:IMUX.IMUX.44
TXDATA_CH0_FS224inputTCELL11:IMUX.IMUX.46
TXDATA_CH0_FS225inputTCELL11:IMUX.IMUX.0
TXDATA_CH0_FS226inputTCELL11:IMUX.IMUX.2
TXDATA_CH0_FS227inputTCELL11:IMUX.IMUX.27
TXDATA_CH0_FS228inputTCELL11:IMUX.IMUX.8
TXDATA_CH0_FS229inputTCELL11:IMUX.IMUX.16
TXDATA_CH0_FS23inputTCELL5:IMUX.IMUX.18
TXDATA_CH0_FS230inputTCELL11:IMUX.IMUX.17
TXDATA_CH0_FS231inputTCELL11:IMUX.IMUX.11
TXDATA_CH0_FS232inputTCELL11:IMUX.IMUX.18
TXDATA_CH0_FS233inputTCELL11:IMUX.IMUX.41
TXDATA_CH0_FS234inputTCELL11:IMUX.IMUX.30
TXDATA_CH0_FS235inputTCELL11:IMUX.IMUX.40
TXDATA_CH0_FS236inputTCELL11:IMUX.IMUX.37
TXDATA_CH0_FS237inputTCELL11:IMUX.IMUX.28
TXDATA_CH0_FS238inputTCELL11:IMUX.IMUX.38
TXDATA_CH0_FS239inputTCELL11:IMUX.IMUX.20
TXDATA_CH0_FS24inputTCELL5:IMUX.IMUX.42
TXDATA_CH0_FS240inputTCELL11:IMUX.IMUX.43
TXDATA_CH0_FS241inputTCELL11:IMUX.IMUX.33
TXDATA_CH0_FS242inputTCELL11:IMUX.IMUX.24
TXDATA_CH0_FS243inputTCELL11:IMUX.IMUX.21
TXDATA_CH0_FS244inputTCELL11:IMUX.IMUX.7
TXDATA_CH0_FS245inputTCELL11:IMUX.IMUX.42
TXDATA_CH0_FS246inputTCELL11:IMUX.IMUX.12
TXDATA_CH0_FS247inputTCELL11:IMUX.IMUX.14
TXDATA_CH0_FS248inputTCELL11:IMUX.IMUX.22
TXDATA_CH0_FS249inputTCELL11:IMUX.IMUX.1
TXDATA_CH0_FS25inputTCELL5:IMUX.IMUX.11
TXDATA_CH0_FS250inputTCELL11:IMUX.IMUX.26
TXDATA_CH0_FS251inputTCELL11:IMUX.IMUX.32
TXDATA_CH0_FS252inputTCELL11:IMUX.IMUX.15
TXDATA_CH0_FS253inputTCELL11:IMUX.IMUX.5
TXDATA_CH0_FS254inputTCELL11:IMUX.IMUX.29
TXDATA_CH0_FS255inputTCELL11:IMUX.IMUX.25
TXDATA_CH0_FS26inputTCELL5:IMUX.IMUX.37
TXDATA_CH0_FS27inputTCELL5:IMUX.IMUX.7
TXDATA_CH0_FS28inputTCELL5:IMUX.IMUX.46
TXDATA_CH0_FS29inputTCELL5:IMUX.IMUX.23
TXDATA_CH0_FS3inputTCELL5:IMUX.IMUX.26
TXDATA_CH0_FS30inputTCELL5:IMUX.IMUX.4
TXDATA_CH0_FS31inputTCELL5:IMUX.IMUX.9
TXDATA_CH0_FS32inputTCELL5:IMUX.IMUX.44
TXDATA_CH0_FS33inputTCELL5:IMUX.IMUX.6
TXDATA_CH0_FS34inputTCELL5:IMUX.IMUX.35
TXDATA_CH0_FS35inputTCELL5:IMUX.IMUX.41
TXDATA_CH0_FS36inputTCELL6:IMUX.IMUX.30
TXDATA_CH0_FS37inputTCELL6:IMUX.IMUX.27
TXDATA_CH0_FS38inputTCELL6:IMUX.IMUX.24
TXDATA_CH0_FS39inputTCELL6:IMUX.IMUX.10
TXDATA_CH0_FS4inputTCELL5:IMUX.IMUX.2
TXDATA_CH0_FS40inputTCELL6:IMUX.IMUX.46
TXDATA_CH0_FS41inputTCELL6:IMUX.IMUX.23
TXDATA_CH0_FS42inputTCELL6:IMUX.IMUX.20
TXDATA_CH0_FS43inputTCELL6:IMUX.IMUX.7
TXDATA_CH0_FS44inputTCELL6:IMUX.IMUX.22
TXDATA_CH0_FS45inputTCELL6:IMUX.IMUX.40
TXDATA_CH0_FS46inputTCELL6:IMUX.IMUX.5
TXDATA_CH0_FS47inputTCELL6:IMUX.IMUX.25
TXDATA_CH0_FS48inputTCELL6:IMUX.IMUX.18
TXDATA_CH0_FS49inputTCELL6:IMUX.IMUX.44
TXDATA_CH0_FS5inputTCELL5:IMUX.IMUX.0
TXDATA_CH0_FS50inputTCELL6:IMUX.IMUX.37
TXDATA_CH0_FS51inputTCELL6:IMUX.IMUX.1
TXDATA_CH0_FS52inputTCELL6:IMUX.IMUX.26
TXDATA_CH0_FS53inputTCELL6:IMUX.IMUX.29
TXDATA_CH0_FS54inputTCELL6:IMUX.IMUX.17
TXDATA_CH0_FS55inputTCELL6:IMUX.IMUX.9
TXDATA_CH0_FS56inputTCELL6:IMUX.IMUX.39
TXDATA_CH0_FS57inputTCELL6:IMUX.IMUX.6
TXDATA_CH0_FS58inputTCELL6:IMUX.IMUX.11
TXDATA_CH0_FS59inputTCELL6:IMUX.IMUX.45
TXDATA_CH0_FS6inputTCELL5:IMUX.IMUX.16
TXDATA_CH0_FS60inputTCELL6:IMUX.IMUX.2
TXDATA_CH0_FS61inputTCELL6:IMUX.IMUX.16
TXDATA_CH0_FS62inputTCELL6:IMUX.IMUX.32
TXDATA_CH0_FS63inputTCELL6:IMUX.IMUX.36
TXDATA_CH0_FS64inputTCELL6:IMUX.IMUX.34
TXDATA_CH0_FS65inputTCELL6:IMUX.IMUX.28
TXDATA_CH0_FS66inputTCELL6:IMUX.IMUX.38
TXDATA_CH0_FS67inputTCELL6:IMUX.IMUX.21
TXDATA_CH0_FS68inputTCELL6:IMUX.IMUX.42
TXDATA_CH0_FS69inputTCELL6:IMUX.IMUX.31
TXDATA_CH0_FS7inputTCELL5:IMUX.IMUX.25
TXDATA_CH0_FS70inputTCELL6:IMUX.IMUX.43
TXDATA_CH0_FS71inputTCELL6:IMUX.IMUX.19
TXDATA_CH0_FS72inputTCELL6:IMUX.IMUX.13
TXDATA_CH0_FS73inputTCELL7:IMUX.IMUX.37
TXDATA_CH0_FS74inputTCELL7:IMUX.IMUX.42
TXDATA_CH0_FS75inputTCELL7:IMUX.IMUX.28
TXDATA_CH0_FS76inputTCELL7:IMUX.IMUX.44
TXDATA_CH0_FS77inputTCELL7:IMUX.IMUX.1
TXDATA_CH0_FS78inputTCELL7:IMUX.IMUX.8
TXDATA_CH0_FS79inputTCELL7:IMUX.IMUX.29
TXDATA_CH0_FS8inputTCELL5:IMUX.IMUX.13
TXDATA_CH0_FS80inputTCELL7:IMUX.IMUX.6
TXDATA_CH0_FS81inputTCELL7:IMUX.IMUX.16
TXDATA_CH0_FS82inputTCELL7:IMUX.IMUX.31
TXDATA_CH0_FS83inputTCELL7:IMUX.IMUX.4
TXDATA_CH0_FS84inputTCELL7:IMUX.IMUX.15
TXDATA_CH0_FS85inputTCELL7:IMUX.IMUX.47
TXDATA_CH0_FS86inputTCELL7:IMUX.IMUX.25
TXDATA_CH0_FS87inputTCELL7:IMUX.IMUX.35
TXDATA_CH0_FS88inputTCELL7:IMUX.IMUX.27
TXDATA_CH0_FS89inputTCELL7:IMUX.IMUX.33
TXDATA_CH0_FS9inputTCELL5:IMUX.IMUX.19
TXDATA_CH0_FS90inputTCELL7:IMUX.IMUX.17
TXDATA_CH0_FS91inputTCELL7:IMUX.IMUX.34
TXDATA_CH0_FS92inputTCELL7:IMUX.IMUX.20
TXDATA_CH0_FS93inputTCELL7:IMUX.IMUX.41
TXDATA_CH0_FS94inputTCELL7:IMUX.IMUX.21
TXDATA_CH0_FS95inputTCELL7:IMUX.IMUX.22
TXDATA_CH0_FS96inputTCELL7:IMUX.IMUX.24
TXDATA_CH0_FS97inputTCELL7:IMUX.IMUX.46
TXDATA_CH0_FS98inputTCELL7:IMUX.IMUX.26
TXDATA_CH0_FS99inputTCELL7:IMUX.IMUX.40
TXDATA_CH1_FS0inputTCELL54:IMUX.IMUX.0
TXDATA_CH1_FS1inputTCELL54:IMUX.IMUX.4
TXDATA_CH1_FS10inputTCELL54:IMUX.IMUX.8
TXDATA_CH1_FS100inputTCELL52:IMUX.IMUX.37
TXDATA_CH1_FS101inputTCELL52:IMUX.IMUX.29
TXDATA_CH1_FS102inputTCELL52:IMUX.IMUX.44
TXDATA_CH1_FS103inputTCELL52:IMUX.IMUX.1
TXDATA_CH1_FS104inputTCELL52:IMUX.IMUX.41
TXDATA_CH1_FS105inputTCELL52:IMUX.IMUX.19
TXDATA_CH1_FS106inputTCELL52:IMUX.IMUX.24
TXDATA_CH1_FS107inputTCELL52:IMUX.IMUX.43
TXDATA_CH1_FS108inputTCELL52:IMUX.IMUX.2
TXDATA_CH1_FS109inputTCELL52:IMUX.IMUX.32
TXDATA_CH1_FS11inputTCELL54:IMUX.IMUX.26
TXDATA_CH1_FS110inputTCELL52:IMUX.IMUX.27
TXDATA_CH1_FS111inputTCELL51:IMUX.IMUX.27
TXDATA_CH1_FS112inputTCELL51:IMUX.IMUX.14
TXDATA_CH1_FS113inputTCELL51:IMUX.IMUX.41
TXDATA_CH1_FS114inputTCELL51:IMUX.IMUX.12
TXDATA_CH1_FS115inputTCELL51:IMUX.IMUX.10
TXDATA_CH1_FS116inputTCELL51:IMUX.IMUX.46
TXDATA_CH1_FS117inputTCELL51:IMUX.IMUX.8
TXDATA_CH1_FS118inputTCELL51:IMUX.IMUX.38
TXDATA_CH1_FS119inputTCELL51:IMUX.IMUX.29
TXDATA_CH1_FS12inputTCELL54:IMUX.IMUX.24
TXDATA_CH1_FS120inputTCELL51:IMUX.IMUX.25
TXDATA_CH1_FS121inputTCELL51:IMUX.IMUX.15
TXDATA_CH1_FS122inputTCELL51:IMUX.IMUX.47
TXDATA_CH1_FS123inputTCELL51:IMUX.IMUX.34
TXDATA_CH1_FS124inputTCELL51:IMUX.IMUX.20
TXDATA_CH1_FS125inputTCELL51:IMUX.IMUX.7
TXDATA_CH1_FS126inputTCELL51:IMUX.IMUX.35
TXDATA_CH1_FS127inputTCELL51:IMUX.IMUX.21
TXDATA_CH1_FS128inputTCELL51:IMUX.IMUX.23
TXDATA_CH1_FS129inputTCELL51:IMUX.IMUX.39
TXDATA_CH1_FS13inputTCELL54:IMUX.IMUX.31
TXDATA_CH1_FS130inputTCELL51:IMUX.IMUX.16
TXDATA_CH1_FS131inputTCELL51:IMUX.IMUX.17
TXDATA_CH1_FS132inputTCELL51:IMUX.IMUX.45
TXDATA_CH1_FS133inputTCELL51:IMUX.IMUX.24
TXDATA_CH1_FS134inputTCELL51:IMUX.IMUX.2
TXDATA_CH1_FS135inputTCELL51:IMUX.IMUX.3
TXDATA_CH1_FS136inputTCELL51:IMUX.IMUX.30
TXDATA_CH1_FS137inputTCELL51:IMUX.IMUX.42
TXDATA_CH1_FS138inputTCELL51:IMUX.IMUX.11
TXDATA_CH1_FS139inputTCELL51:IMUX.IMUX.40
TXDATA_CH1_FS14inputTCELL54:IMUX.IMUX.30
TXDATA_CH1_FS140inputTCELL51:IMUX.IMUX.32
TXDATA_CH1_FS141inputTCELL51:IMUX.IMUX.5
TXDATA_CH1_FS142inputTCELL51:IMUX.IMUX.44
TXDATA_CH1_FS143inputTCELL51:IMUX.IMUX.18
TXDATA_CH1_FS144inputTCELL51:IMUX.IMUX.0
TXDATA_CH1_FS145inputTCELL51:IMUX.IMUX.1
TXDATA_CH1_FS146inputTCELL51:IMUX.IMUX.28
TXDATA_CH1_FS147inputTCELL51:IMUX.IMUX.36
TXDATA_CH1_FS148inputTCELL51:IMUX.IMUX.33
TXDATA_CH1_FS149inputTCELL50:IMUX.IMUX.11
TXDATA_CH1_FS15inputTCELL54:IMUX.IMUX.23
TXDATA_CH1_FS150inputTCELL50:IMUX.IMUX.5
TXDATA_CH1_FS151inputTCELL50:IMUX.IMUX.29
TXDATA_CH1_FS152inputTCELL50:IMUX.IMUX.1
TXDATA_CH1_FS153inputTCELL50:IMUX.IMUX.9
TXDATA_CH1_FS154inputTCELL50:IMUX.IMUX.34
TXDATA_CH1_FS155inputTCELL50:IMUX.IMUX.19
TXDATA_CH1_FS156inputTCELL50:IMUX.IMUX.45
TXDATA_CH1_FS157inputTCELL50:IMUX.IMUX.10
TXDATA_CH1_FS158inputTCELL50:IMUX.IMUX.40
TXDATA_CH1_FS159inputTCELL50:IMUX.IMUX.37
TXDATA_CH1_FS16inputTCELL54:IMUX.IMUX.2
TXDATA_CH1_FS160inputTCELL50:IMUX.IMUX.3
TXDATA_CH1_FS161inputTCELL50:IMUX.IMUX.47
TXDATA_CH1_FS162inputTCELL50:IMUX.IMUX.25
TXDATA_CH1_FS163inputTCELL50:IMUX.IMUX.23
TXDATA_CH1_FS164inputTCELL50:IMUX.IMUX.6
TXDATA_CH1_FS165inputTCELL50:IMUX.IMUX.31
TXDATA_CH1_FS166inputTCELL50:IMUX.IMUX.27
TXDATA_CH1_FS167inputTCELL50:IMUX.IMUX.0
TXDATA_CH1_FS168inputTCELL50:IMUX.IMUX.13
TXDATA_CH1_FS169inputTCELL50:IMUX.IMUX.36
TXDATA_CH1_FS17inputTCELL54:IMUX.IMUX.40
TXDATA_CH1_FS170inputTCELL50:IMUX.IMUX.28
TXDATA_CH1_FS171inputTCELL50:IMUX.IMUX.46
TXDATA_CH1_FS172inputTCELL50:IMUX.IMUX.38
TXDATA_CH1_FS173inputTCELL50:IMUX.IMUX.35
TXDATA_CH1_FS174inputTCELL50:IMUX.IMUX.33
TXDATA_CH1_FS175inputTCELL50:IMUX.IMUX.2
TXDATA_CH1_FS176inputTCELL50:IMUX.IMUX.4
TXDATA_CH1_FS177inputTCELL50:IMUX.IMUX.21
TXDATA_CH1_FS178inputTCELL50:IMUX.IMUX.7
TXDATA_CH1_FS179inputTCELL50:IMUX.IMUX.8
TXDATA_CH1_FS18inputTCELL54:IMUX.IMUX.38
TXDATA_CH1_FS180inputTCELL50:IMUX.IMUX.41
TXDATA_CH1_FS181inputTCELL50:IMUX.IMUX.44
TXDATA_CH1_FS182inputTCELL50:IMUX.IMUX.30
TXDATA_CH1_FS183inputTCELL49:IMUX.IMUX.37
TXDATA_CH1_FS184inputTCELL49:IMUX.IMUX.8
TXDATA_CH1_FS185inputTCELL49:IMUX.IMUX.42
TXDATA_CH1_FS186inputTCELL49:IMUX.IMUX.32
TXDATA_CH1_FS187inputTCELL49:IMUX.IMUX.13
TXDATA_CH1_FS188inputTCELL49:IMUX.IMUX.22
TXDATA_CH1_FS189inputTCELL49:IMUX.IMUX.43
TXDATA_CH1_FS19inputTCELL54:IMUX.IMUX.41
TXDATA_CH1_FS190inputTCELL49:IMUX.IMUX.46
TXDATA_CH1_FS191inputTCELL49:IMUX.IMUX.35
TXDATA_CH1_FS192inputTCELL49:IMUX.IMUX.40
TXDATA_CH1_FS193inputTCELL49:IMUX.IMUX.12
TXDATA_CH1_FS194inputTCELL49:IMUX.IMUX.3
TXDATA_CH1_FS195inputTCELL49:IMUX.IMUX.10
TXDATA_CH1_FS196inputTCELL49:IMUX.IMUX.7
TXDATA_CH1_FS197inputTCELL49:IMUX.IMUX.28
TXDATA_CH1_FS198inputTCELL49:IMUX.IMUX.29
TXDATA_CH1_FS199inputTCELL49:IMUX.IMUX.27
TXDATA_CH1_FS2inputTCELL54:IMUX.IMUX.15
TXDATA_CH1_FS20inputTCELL54:IMUX.IMUX.7
TXDATA_CH1_FS200inputTCELL49:IMUX.IMUX.30
TXDATA_CH1_FS201inputTCELL49:IMUX.IMUX.9
TXDATA_CH1_FS202inputTCELL49:IMUX.IMUX.47
TXDATA_CH1_FS203inputTCELL49:IMUX.IMUX.45
TXDATA_CH1_FS204inputTCELL49:IMUX.IMUX.6
TXDATA_CH1_FS205inputTCELL49:IMUX.IMUX.31
TXDATA_CH1_FS206inputTCELL49:IMUX.IMUX.18
TXDATA_CH1_FS207inputTCELL49:IMUX.IMUX.34
TXDATA_CH1_FS208inputTCELL49:IMUX.IMUX.15
TXDATA_CH1_FS209inputTCELL49:IMUX.IMUX.14
TXDATA_CH1_FS21inputTCELL54:IMUX.IMUX.37
TXDATA_CH1_FS210inputTCELL49:IMUX.IMUX.2
TXDATA_CH1_FS211inputTCELL49:IMUX.IMUX.11
TXDATA_CH1_FS212inputTCELL49:IMUX.IMUX.36
TXDATA_CH1_FS213inputTCELL49:IMUX.IMUX.19
TXDATA_CH1_FS214inputTCELL49:IMUX.IMUX.20
TXDATA_CH1_FS215inputTCELL49:IMUX.IMUX.23
TXDATA_CH1_FS216inputTCELL49:IMUX.IMUX.33
TXDATA_CH1_FS217inputTCELL49:IMUX.IMUX.17
TXDATA_CH1_FS218inputTCELL48:IMUX.IMUX.27
TXDATA_CH1_FS219inputTCELL48:IMUX.IMUX.8
TXDATA_CH1_FS22inputTCELL54:IMUX.IMUX.42
TXDATA_CH1_FS220inputTCELL48:IMUX.IMUX.39
TXDATA_CH1_FS221inputTCELL48:IMUX.IMUX.4
TXDATA_CH1_FS222inputTCELL48:IMUX.IMUX.41
TXDATA_CH1_FS223inputTCELL48:IMUX.IMUX.18
TXDATA_CH1_FS224inputTCELL48:IMUX.IMUX.16
TXDATA_CH1_FS225inputTCELL48:IMUX.IMUX.47
TXDATA_CH1_FS226inputTCELL48:IMUX.IMUX.43
TXDATA_CH1_FS227inputTCELL48:IMUX.IMUX.10
TXDATA_CH1_FS228inputTCELL48:IMUX.IMUX.31
TXDATA_CH1_FS229inputTCELL48:IMUX.IMUX.46
TXDATA_CH1_FS23inputTCELL54:IMUX.IMUX.44
TXDATA_CH1_FS230inputTCELL48:IMUX.IMUX.15
TXDATA_CH1_FS231inputTCELL48:IMUX.IMUX.25
TXDATA_CH1_FS232inputTCELL48:IMUX.IMUX.44
TXDATA_CH1_FS233inputTCELL48:IMUX.IMUX.3
TXDATA_CH1_FS234inputTCELL48:IMUX.IMUX.32
TXDATA_CH1_FS235inputTCELL48:IMUX.IMUX.22
TXDATA_CH1_FS236inputTCELL48:IMUX.IMUX.5
TXDATA_CH1_FS237inputTCELL48:IMUX.IMUX.34
TXDATA_CH1_FS238inputTCELL48:IMUX.IMUX.24
TXDATA_CH1_FS239inputTCELL48:IMUX.IMUX.42
TXDATA_CH1_FS24inputTCELL54:IMUX.IMUX.20
TXDATA_CH1_FS240inputTCELL48:IMUX.IMUX.2
TXDATA_CH1_FS241inputTCELL48:IMUX.IMUX.7
TXDATA_CH1_FS242inputTCELL48:IMUX.IMUX.38
TXDATA_CH1_FS243inputTCELL48:IMUX.IMUX.13
TXDATA_CH1_FS244inputTCELL48:IMUX.IMUX.33
TXDATA_CH1_FS245inputTCELL48:IMUX.IMUX.20
TXDATA_CH1_FS246inputTCELL48:IMUX.IMUX.23
TXDATA_CH1_FS247inputTCELL48:IMUX.IMUX.19
TXDATA_CH1_FS248inputTCELL48:IMUX.IMUX.40
TXDATA_CH1_FS249inputTCELL48:IMUX.IMUX.45
TXDATA_CH1_FS25inputTCELL54:IMUX.IMUX.25
TXDATA_CH1_FS250inputTCELL48:IMUX.IMUX.36
TXDATA_CH1_FS251inputTCELL48:IMUX.IMUX.30
TXDATA_CH1_FS252inputTCELL48:IMUX.IMUX.17
TXDATA_CH1_FS253inputTCELL48:IMUX.IMUX.37
TXDATA_CH1_FS254inputTCELL48:IMUX.IMUX.9
TXDATA_CH1_FS255inputTCELL48:IMUX.IMUX.11
TXDATA_CH1_FS26inputTCELL54:IMUX.IMUX.5
TXDATA_CH1_FS27inputTCELL54:IMUX.IMUX.33
TXDATA_CH1_FS28inputTCELL54:IMUX.IMUX.16
TXDATA_CH1_FS29inputTCELL54:IMUX.IMUX.12
TXDATA_CH1_FS3inputTCELL54:IMUX.IMUX.36
TXDATA_CH1_FS30inputTCELL54:IMUX.IMUX.39
TXDATA_CH1_FS31inputTCELL54:IMUX.IMUX.29
TXDATA_CH1_FS32inputTCELL54:IMUX.IMUX.18
TXDATA_CH1_FS33inputTCELL54:IMUX.IMUX.35
TXDATA_CH1_FS34inputTCELL54:IMUX.IMUX.6
TXDATA_CH1_FS35inputTCELL54:IMUX.IMUX.3
TXDATA_CH1_FS36inputTCELL53:IMUX.IMUX.32
TXDATA_CH1_FS37inputTCELL53:IMUX.IMUX.10
TXDATA_CH1_FS38inputTCELL53:IMUX.IMUX.38
TXDATA_CH1_FS39inputTCELL53:IMUX.IMUX.27
TXDATA_CH1_FS4inputTCELL54:IMUX.IMUX.43
TXDATA_CH1_FS40inputTCELL53:IMUX.IMUX.16
TXDATA_CH1_FS41inputTCELL53:IMUX.IMUX.12
TXDATA_CH1_FS42inputTCELL53:IMUX.IMUX.42
TXDATA_CH1_FS43inputTCELL53:IMUX.IMUX.33
TXDATA_CH1_FS44inputTCELL53:IMUX.IMUX.40
TXDATA_CH1_FS45inputTCELL53:IMUX.IMUX.22
TXDATA_CH1_FS46inputTCELL53:IMUX.IMUX.37
TXDATA_CH1_FS47inputTCELL53:IMUX.IMUX.11
TXDATA_CH1_FS48inputTCELL53:IMUX.IMUX.44
TXDATA_CH1_FS49inputTCELL53:IMUX.IMUX.18
TXDATA_CH1_FS5inputTCELL54:IMUX.IMUX.47
TXDATA_CH1_FS50inputTCELL53:IMUX.IMUX.5
TXDATA_CH1_FS51inputTCELL53:IMUX.IMUX.45
TXDATA_CH1_FS52inputTCELL53:IMUX.IMUX.36
TXDATA_CH1_FS53inputTCELL53:IMUX.IMUX.9
TXDATA_CH1_FS54inputTCELL53:IMUX.IMUX.15
TXDATA_CH1_FS55inputTCELL53:IMUX.IMUX.29
TXDATA_CH1_FS56inputTCELL53:IMUX.IMUX.4
TXDATA_CH1_FS57inputTCELL53:IMUX.IMUX.35
TXDATA_CH1_FS58inputTCELL53:IMUX.IMUX.25
TXDATA_CH1_FS59inputTCELL53:IMUX.IMUX.1
TXDATA_CH1_FS6inputTCELL54:IMUX.IMUX.46
TXDATA_CH1_FS60inputTCELL53:IMUX.IMUX.43
TXDATA_CH1_FS61inputTCELL53:IMUX.IMUX.46
TXDATA_CH1_FS62inputTCELL53:IMUX.IMUX.30
TXDATA_CH1_FS63inputTCELL53:IMUX.IMUX.26
TXDATA_CH1_FS64inputTCELL53:IMUX.IMUX.28
TXDATA_CH1_FS65inputTCELL53:IMUX.IMUX.34
TXDATA_CH1_FS66inputTCELL53:IMUX.IMUX.24
TXDATA_CH1_FS67inputTCELL53:IMUX.IMUX.13
TXDATA_CH1_FS68inputTCELL53:IMUX.IMUX.20
TXDATA_CH1_FS69inputTCELL53:IMUX.IMUX.8
TXDATA_CH1_FS7inputTCELL54:IMUX.IMUX.11
TXDATA_CH1_FS70inputTCELL53:IMUX.IMUX.2
TXDATA_CH1_FS71inputTCELL53:IMUX.IMUX.14
TXDATA_CH1_FS72inputTCELL53:IMUX.IMUX.21
TXDATA_CH1_FS73inputTCELL52:IMUX.IMUX.5
TXDATA_CH1_FS74inputTCELL52:IMUX.IMUX.20
TXDATA_CH1_FS75inputTCELL52:IMUX.IMUX.34
TXDATA_CH1_FS76inputTCELL52:IMUX.IMUX.18
TXDATA_CH1_FS77inputTCELL52:IMUX.IMUX.45
TXDATA_CH1_FS78inputTCELL52:IMUX.IMUX.31
TXDATA_CH1_FS79inputTCELL52:IMUX.IMUX.9
TXDATA_CH1_FS8inputTCELL54:IMUX.IMUX.21
TXDATA_CH1_FS80inputTCELL52:IMUX.IMUX.35
TXDATA_CH1_FS81inputTCELL52:IMUX.IMUX.46
TXDATA_CH1_FS82inputTCELL52:IMUX.IMUX.8
TXDATA_CH1_FS83inputTCELL52:IMUX.IMUX.39
TXDATA_CH1_FS84inputTCELL52:IMUX.IMUX.17
TXDATA_CH1_FS85inputTCELL52:IMUX.IMUX.0
TXDATA_CH1_FS86inputTCELL52:IMUX.IMUX.11
TXDATA_CH1_FS87inputTCELL52:IMUX.IMUX.6
TXDATA_CH1_FS88inputTCELL52:IMUX.IMUX.10
TXDATA_CH1_FS89inputTCELL52:IMUX.IMUX.7
TXDATA_CH1_FS9inputTCELL54:IMUX.IMUX.14
TXDATA_CH1_FS90inputTCELL52:IMUX.IMUX.15
TXDATA_CH1_FS91inputTCELL52:IMUX.IMUX.28
TXDATA_CH1_FS92inputTCELL52:IMUX.IMUX.42
TXDATA_CH1_FS93inputTCELL52:IMUX.IMUX.3
TXDATA_CH1_FS94inputTCELL52:IMUX.IMUX.13
TXDATA_CH1_FS95inputTCELL52:IMUX.IMUX.40
TXDATA_CH1_FS96inputTCELL52:IMUX.IMUX.38
TXDATA_CH1_FS97inputTCELL52:IMUX.IMUX.16
TXDATA_CH1_FS98inputTCELL52:IMUX.IMUX.36
TXDATA_CH1_FS99inputTCELL52:IMUX.IMUX.22
TXDATA_START_CH0_FSinputTCELL5:IMUX.IMUX.15
TXDATA_START_CH1_FSinputTCELL54:IMUX.IMUX.17
TXDRVAMP_CH0_FS0inputTCELL23:IMUX.IMUX.23
TXDRVAMP_CH0_FS1inputTCELL24:IMUX.IMUX.5
TXDRVAMP_CH0_FS2inputTCELL24:IMUX.IMUX.36
TXDRVAMP_CH0_FS3inputTCELL25:IMUX.IMUX.13
TXDRVAMP_CH0_FS4inputTCELL25:IMUX.IMUX.16
TXDRVAMP_CH1_FS0inputTCELL36:IMUX.IMUX.12
TXDRVAMP_CH1_FS1inputTCELL35:IMUX.IMUX.37
TXDRVAMP_CH1_FS2inputTCELL35:IMUX.IMUX.26
TXDRVAMP_CH1_FS3inputTCELL34:IMUX.IMUX.21
TXDRVAMP_CH1_FS4inputTCELL34:IMUX.IMUX.46
TXEMPMAIN_CH0_FS0inputTCELL23:IMUX.IMUX.19
TXEMPMAIN_CH0_FS1inputTCELL23:IMUX.IMUX.25
TXEMPMAIN_CH0_FS2inputTCELL23:IMUX.IMUX.4
TXEMPMAIN_CH0_FS3inputTCELL26:IMUX.IMUX.40
TXEMPMAIN_CH0_FS4inputTCELL26:IMUX.IMUX.46
TXEMPMAIN_CH0_FS5inputTCELL26:IMUX.IMUX.22
TXEMPMAIN_CH1_FS0inputTCELL36:IMUX.IMUX.14
TXEMPMAIN_CH1_FS1inputTCELL36:IMUX.IMUX.11
TXEMPMAIN_CH1_FS2inputTCELL36:IMUX.IMUX.39
TXEMPMAIN_CH1_FS3inputTCELL33:IMUX.IMUX.22
TXEMPMAIN_CH1_FS4inputTCELL33:IMUX.IMUX.16
TXEMPMAIN_CH1_FS5inputTCELL33:IMUX.IMUX.40
TXEMPPOS_CH0_FS0inputTCELL23:IMUX.IMUX.29
TXEMPPOS_CH0_FS1inputTCELL23:IMUX.IMUX.34
TXEMPPOS_CH0_FS2inputTCELL23:IMUX.IMUX.41
TXEMPPOS_CH0_FS3inputTCELL24:IMUX.IMUX.13
TXEMPPOS_CH0_FS4inputTCELL24:IMUX.IMUX.45
TXEMPPOS_CH1_FS0inputTCELL36:IMUX.IMUX.9
TXEMPPOS_CH1_FS1inputTCELL36:IMUX.IMUX.28
TXEMPPOS_CH1_FS2inputTCELL36:IMUX.IMUX.3
TXEMPPOS_CH1_FS3inputTCELL35:IMUX.IMUX.21
TXEMPPOS_CH1_FS4inputTCELL35:IMUX.IMUX.1
TXEMPPRE2_CH0_FS0inputTCELL23:IMUX.IMUX.45
TXEMPPRE2_CH0_FS1inputTCELL26:IMUX.IMUX.5
TXEMPPRE2_CH0_FS2inputTCELL26:IMUX.IMUX.41
TXEMPPRE2_CH0_FS3inputTCELL26:IMUX.IMUX.9
TXEMPPRE2_CH1_FS0inputTCELL36:IMUX.IMUX.1
TXEMPPRE2_CH1_FS1inputTCELL33:IMUX.IMUX.37
TXEMPPRE2_CH1_FS2inputTCELL33:IMUX.IMUX.3
TXEMPPRE2_CH1_FS3inputTCELL33:IMUX.IMUX.29
TXEMPPRE_CH0_FS0inputTCELL24:IMUX.IMUX.26
TXEMPPRE_CH0_FS1inputTCELL24:IMUX.IMUX.17
TXEMPPRE_CH0_FS2inputTCELL25:IMUX.IMUX.2
TXEMPPRE_CH0_FS3inputTCELL25:IMUX.IMUX.6
TXEMPPRE_CH0_FS4inputTCELL26:IMUX.IMUX.2
TXEMPPRE_CH1_FS0inputTCELL35:IMUX.IMUX.36
TXEMPPRE_CH1_FS1inputTCELL35:IMUX.IMUX.15
TXEMPPRE_CH1_FS2inputTCELL34:IMUX.IMUX.43
TXEMPPRE_CH1_FS3inputTCELL34:IMUX.IMUX.35
TXEMPPRE_CH1_FS4inputTCELL33:IMUX.IMUX.43
TXINHIBIT_CH0_FSinputTCELL26:IMUX.IMUX.45
TXINHIBIT_CH1_FSinputTCELL33:IMUX.IMUX.1
TXMUXDCDEXHOLD_CH0_FSinputTCELL26:IMUX.IMUX.4
TXMUXDCDEXHOLD_CH1_FSinputTCELL33:IMUX.IMUX.39
TXMUXDCDORWREN_CH0_FSinputTCELL25:IMUX.IMUX.12
TXMUXDCDORWREN_CH1_FSinputTCELL34:IMUX.IMUX.23
TXOUTCKCTL_CH0_FS0inputTCELL24:IMUX.IMUX.34
TXOUTCKCTL_CH0_FS1inputTCELL25:IMUX.IMUX.34
TXOUTCKCTL_CH0_FS2inputTCELL26:IMUX.IMUX.30
TXOUTCKCTL_CH1_FS0inputTCELL35:IMUX.IMUX.28
TXOUTCKCTL_CH1_FS1inputTCELL34:IMUX.IMUX.28
TXOUTCKCTL_CH1_FS2inputTCELL33:IMUX.IMUX.32
TXPMARESETDONE_CH0_SFoutputTCELL25:OUT.26
TXPMARESETDONE_CH1_SFoutputTCELL34:OUT.5
TXPOLARITY_CH0_FSinputTCELL25:IMUX.IMUX.30
TXPOLARITY_CH1_FSinputTCELL34:IMUX.IMUX.32
TXPRBSINERR_CH0_FSinputTCELL25:IMUX.IMUX.40
TXPRBSINERR_CH1_FSinputTCELL34:IMUX.IMUX.22
TXPRBSPTN_CH0_FS0inputTCELL24:IMUX.IMUX.11
TXPRBSPTN_CH0_FS1inputTCELL24:IMUX.IMUX.2
TXPRBSPTN_CH0_FS2inputTCELL24:IMUX.IMUX.41
TXPRBSPTN_CH0_FS3inputTCELL24:IMUX.IMUX.47
TXPRBSPTN_CH1_FS0inputTCELL35:IMUX.IMUX.25
TXPRBSPTN_CH1_FS1inputTCELL35:IMUX.IMUX.43
TXPRBSPTN_CH1_FS2inputTCELL35:IMUX.IMUX.3
TXPRBSPTN_CH1_FS3inputTCELL35:IMUX.IMUX.0
TXPROGDIVRESETDONE_CH0_SFoutputTCELL25:OUT.17
TXPROGDIVRESETDONE_CH1_SFoutputTCELL34:OUT.14
TXQPRBS_ENA_CH0_FSinputTCELL26:IMUX.IMUX.11
TXQPRBS_ENA_CH1_FSinputTCELL33:IMUX.IMUX.25
TXRESETDONE_CH0_SFoutputTCELL24:OUT.16
TXRESETDONE_CH1_SFoutputTCELL35:OUT.15
TXUSRCLK2_CH0_FSinputTCELL23:IMUX.CTRL.1
TXUSRCLK2_CH1_FSinputTCELL36:IMUX.CTRL.6
TXUSRCLK_CH0_FSinputTCELL23:IMUX.CTRL.5
TXUSRCLK_CH1_FSinputTCELL36:IMUX.CTRL.2
TXUSRRDY_CH0_FSinputTCELL25:IMUX.IMUX.27
TXUSRRDY_CH1_FSinputTCELL34:IMUX.IMUX.10
TX_CKALRESET_CH0_FSinputTCELL25:IMUX.IMUX.35
TX_CKALRESET_CH1_FSinputTCELL34:IMUX.IMUX.6
TX_FECRESET_CH0_FSinputTCELL25:IMUX.IMUX.39
TX_FECRESET_CH1_FSinputTCELL34:IMUX.IMUX.4
TX_PCSRESET_CH0_FSinputTCELL25:IMUX.IMUX.28
TX_PCSRESET_CH1_FSinputTCELL34:IMUX.IMUX.34
TX_PCS_RESETMASK_CH0_FS0inputTCELL25:IMUX.IMUX.7
TX_PCS_RESETMASK_CH0_FS1inputTCELL26:IMUX.IMUX.23
TX_PCS_RESETMASK_CH1_FS0inputTCELL34:IMUX.IMUX.33
TX_PCS_RESETMASK_CH1_FS1inputTCELL33:IMUX.IMUX.12
TX_PCS_SEQ_ADVANCE_CH0_FSinputTCELL23:IMUX.IMUX.17
TX_PCS_SEQ_ADVANCE_CH1_FSinputTCELL36:IMUX.IMUX.15
TX_PMARESET_CH0_FSinputTCELL25:IMUX.IMUX.47
TX_PMARESET_CH1_FSinputTCELL34:IMUX.IMUX.0
TX_PMA_RESETMASK_CH0_FS0inputTCELL24:IMUX.IMUX.37
TX_PMA_RESETMASK_CH0_FS1inputTCELL24:IMUX.IMUX.22
TX_PMA_RESETMASK_CH1_FS0inputTCELL35:IMUX.IMUX.5
TX_PMA_RESETMASK_CH1_FS1inputTCELL35:IMUX.IMUX.40
TX_PROGDIVRESET_CH0_FSinputTCELL25:IMUX.IMUX.42
TX_PROGDIVRESET_CH1_FSinputTCELL34:IMUX.IMUX.20
TX_RESETMODE_CH0_FS0inputTCELL24:IMUX.IMUX.24
TX_RESETMODE_CH0_FS1inputTCELL24:IMUX.IMUX.8
TX_RESETMODE_CH1_FS0inputTCELL35:IMUX.IMUX.38
TX_RESETMODE_CH1_FS1inputTCELL35:IMUX.IMUX.31

Bel RCLK_GT

ultrascaleplus GTM bel RCLK_GT
PinDirectionWires

Bel VCC_GT

ultrascaleplus GTM bel VCC_GT
PinDirectionWires

Bel wires

ultrascaleplus GTM bel wires
WirePins
TCELL0:OUT.0GTM_DUAL.FEC_SCANOUT_SF0
TCELL0:OUT.1GTM_DUAL.FEC_SCANOUT_SF1
TCELL0:OUT.2GTM_DUAL.FEC_SCANOUT_SF2
TCELL0:OUT.3GTM_DUAL.FEC_SCANOUT_SF3
TCELL0:OUT.4GTM_DUAL.PMA_SCANOUT_CH0_SF0
TCELL0:OUT.5GTM_DUAL.FEC_SCANOUT_SF4
TCELL0:OUT.6GTM_DUAL.FEC_SCANOUT_SF5
TCELL0:OUT.7GTM_DUAL.PCS_SCANOUT_CH0_SF1
TCELL0:OUT.9GTM_DUAL.FEC_SCANOUT_SF6
TCELL0:OUT.10GTM_DUAL.FEC_SCANOUT_SF7
TCELL0:OUT.11GTM_DUAL.FEC_SCANOUT_SF8
TCELL0:OUT.12GTM_DUAL.FEC_SCANOUT_SF9
TCELL0:OUT.13GTM_DUAL.FEC_SCANOUT_SF10
TCELL0:OUT.14GTM_DUAL.FEC_SCANOUT_SF11
TCELL0:OUT.16GTM_DUAL.FEC_SCANOUT_SF12
TCELL0:OUT.17GTM_DUAL.FEC_SCANOUT_SF13
TCELL0:OUT.18GTM_DUAL.PCS_SCANOUT_CH0_SF0
TCELL0:OUT.19GTM_DUAL.FEC_SCANOUT_SF14
TCELL0:OUT.20GTM_DUAL.FEC_SCANOUT_SF15
TCELL0:OUT.21GTM_DUAL.FEC_SCANOUT_SF16
TCELL0:OUT.22GTM_DUAL.FEC_SCANOUT_SF17
TCELL0:OUT.24GTM_DUAL.FEC_SCANOUT_SF18
TCELL0:OUT.25GTM_DUAL.PMA_SCANOUT_CH0_SF1
TCELL0:OUT.26GTM_DUAL.FEC_SCANOUT_SF19
TCELL0:OUT.27GTM_DUAL.DMONOUT_CH0_SF0
TCELL0:OUT.28GTM_DUAL.FEC_SCANOUT_SF20
TCELL0:OUT.29GTM_DUAL.FEC_SCANOUT_SF21
TCELL0:OUT.30GTM_DUAL.FEC_SCANOUT_SF22
TCELL0:IMUX.CTRL.4GTM_DUAL.FEC_SCANCLK_FS
TCELL0:IMUX.CTRL.6GTM_DUAL.FEC_SCANRSTB_FS
TCELL0:IMUX.IMUX.2GTM_DUAL.PMA_SCANIN_CH0_FS4
TCELL0:IMUX.IMUX.3GTM_DUAL.PMA_SCANCLK_CH0_FS1
TCELL0:IMUX.IMUX.10GTM_DUAL.PMA_SCANIN_CH0_FS0
TCELL0:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS5
TCELL0:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS6
TCELL0:IMUX.IMUX.19GTM_DUAL.PMA_SCANIN_CH0_FS1
TCELL0:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS0
TCELL0:IMUX.IMUX.22GTM_DUAL.PMA_SCANIN_CH0_FS5
TCELL0:IMUX.IMUX.24GTM_DUAL.FEC_SCANIN_FS1
TCELL0:IMUX.IMUX.27GTM_DUAL.PMA_SCANCLK_CH0_FS0
TCELL0:IMUX.IMUX.28GTM_DUAL.FEC_SCANIN_FS2
TCELL0:IMUX.IMUX.29GTM_DUAL.PMA_SCANIN_CH0_FS3
TCELL0:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS3
TCELL0:IMUX.IMUX.36GTM_DUAL.FEC_SCANIN_FS4
TCELL0:IMUX.IMUX.42GTM_DUAL.PMA_SCANIN_CH0_FS2
TCELL1:OUT.0GTM_DUAL.FEC_SCANOUT_SF23
TCELL1:OUT.1GTM_DUAL.FEC_SCANOUT_SF24
TCELL1:OUT.2GTM_DUAL.FEC_SCANOUT_SF25
TCELL1:OUT.3GTM_DUAL.FEC_SCANOUT_SF26
TCELL1:OUT.4GTM_DUAL.FEC_SCANOUT_SF27
TCELL1:OUT.5GTM_DUAL.FEC_SCANOUT_SF28
TCELL1:OUT.7GTM_DUAL.FEC_SCANOUT_SF29
TCELL1:OUT.8GTM_DUAL.FEC_SCANOUT_SF30
TCELL1:OUT.9GTM_DUAL.FEC_SCANOUT_SF31
TCELL1:OUT.10GTM_DUAL.DMONOUT_CH0_SF1
TCELL1:OUT.11GTM_DUAL.FEC_SCANOUT_SF32
TCELL1:OUT.12GTM_DUAL.FEC_SCANOUT_SF33
TCELL1:OUT.13GTM_DUAL.FEC_SCANOUT_SF34
TCELL1:OUT.15GTM_DUAL.FEC_SCANOUT_SF35
TCELL1:OUT.16GTM_DUAL.FEC_SCANOUT_SF36
TCELL1:OUT.17GTM_DUAL.FEC_SCANOUT_SF37
TCELL1:OUT.18GTM_DUAL.FEC_SCANOUT_SF38
TCELL1:OUT.19GTM_DUAL.FEC_SCANOUT_SF39
TCELL1:OUT.20GTM_DUAL.DMONOUT_CH0_SF3
TCELL1:OUT.21GTM_DUAL.FEC_SCANOUT_SF40
TCELL1:OUT.23GTM_DUAL.FEC_SCANOUT_SF41
TCELL1:OUT.24GTM_DUAL.FEC_SCANOUT_SF42
TCELL1:OUT.25GTM_DUAL.FEC_SCANOUT_SF43
TCELL1:OUT.26GTM_DUAL.DMONOUT_CH0_SF4
TCELL1:OUT.27GTM_DUAL.FEC_SCANOUT_SF44
TCELL1:OUT.28GTM_DUAL.FEC_SCANOUT_SF45
TCELL1:OUT.29GTM_DUAL.DMONOUT_CH0_SF2
TCELL1:OUT.30GTM_DUAL.FEC_SCANOUT_SF46
TCELL1:IMUX.IMUX.0GTM_DUAL.FEC_SCANIN_FS7
TCELL1:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS10
TCELL1:IMUX.IMUX.2GTM_DUAL.FEC_SCANIN_FS12
TCELL1:IMUX.IMUX.4GTM_DUAL.FEC_SCANIN_FS17
TCELL1:IMUX.IMUX.5GTM_DUAL.FEC_SCANIN_FS19
TCELL1:IMUX.IMUX.7GTM_DUAL.FEC_SCANIN_FS24
TCELL1:IMUX.IMUX.8GTM_DUAL.FEC_SCANIN_FS26
TCELL1:IMUX.IMUX.9GTM_DUAL.FEC_SCANIN_FS29
TCELL1:IMUX.IMUX.10GTM_DUAL.FEC_SCANIN_FS31
TCELL1:IMUX.IMUX.11GTM_DUAL.FEC_SCANIN_FS33
TCELL1:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS35
TCELL1:IMUX.IMUX.13GTM_DUAL.FEC_SCANIN_FS37
TCELL1:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS40
TCELL1:IMUX.IMUX.15GTM_DUAL.FEC_SCANIN_FS42
TCELL1:IMUX.IMUX.16GTM_DUAL.FEC_SCANIN_FS8
TCELL1:IMUX.IMUX.17GTM_DUAL.FEC_SCANIN_FS9
TCELL1:IMUX.IMUX.19GTM_DUAL.FEC_SCANIN_FS11
TCELL1:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS13
TCELL1:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS14
TCELL1:IMUX.IMUX.22GTM_DUAL.FEC_SCANIN_FS15
TCELL1:IMUX.IMUX.23GTM_DUAL.FEC_SCANIN_FS16
TCELL1:IMUX.IMUX.24GTM_DUAL.FEC_SCANIN_FS18
TCELL1:IMUX.IMUX.26GTM_DUAL.FEC_SCANIN_FS20
TCELL1:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS21
TCELL1:IMUX.IMUX.28GTM_DUAL.FEC_SCANIN_FS22
TCELL1:IMUX.IMUX.29GTM_DUAL.FEC_SCANIN_FS23
TCELL1:IMUX.IMUX.30GTM_DUAL.FEC_SCANIN_FS25
TCELL1:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS27
TCELL1:IMUX.IMUX.33GTM_DUAL.FEC_SCANIN_FS28
TCELL1:IMUX.IMUX.35GTM_DUAL.FEC_SCANIN_FS30
TCELL1:IMUX.IMUX.36GTM_DUAL.FEC_SCANIN_FS32
TCELL1:IMUX.IMUX.38GTM_DUAL.PMA_SCANIN_CH0_FS6
TCELL1:IMUX.IMUX.39GTM_DUAL.FEC_SCANIN_FS34
TCELL1:IMUX.IMUX.40GTM_DUAL.FEC_SCANIN_FS36
TCELL1:IMUX.IMUX.42GTM_DUAL.FEC_SCANIN_FS38
TCELL1:IMUX.IMUX.43GTM_DUAL.FEC_SCANIN_FS39
TCELL1:IMUX.IMUX.45GTM_DUAL.FEC_SCANIN_FS41
TCELL1:IMUX.IMUX.46GTM_DUAL.FEC_SCANIN_FS43
TCELL2:OUT.0GTM_DUAL.FEC_SCANOUT_SF47
TCELL2:OUT.1GTM_DUAL.FEC_SCANOUT_SF48
TCELL2:OUT.2GTM_DUAL.FEC_SCANOUT_SF49
TCELL2:OUT.3GTM_DUAL.FEC_SCANOUT_SF50
TCELL2:OUT.4GTM_DUAL.FEC_SCANOUT_SF51
TCELL2:OUT.5GTM_DUAL.FEC_SCANOUT_SF52
TCELL2:OUT.6GTM_DUAL.FEC_SCANOUT_SF53
TCELL2:OUT.8GTM_DUAL.FEC_SCANOUT_SF54
TCELL2:OUT.9GTM_DUAL.FEC_SCANOUT_SF55
TCELL2:OUT.10GTM_DUAL.FEC_SCANOUT_SF56
TCELL2:OUT.11GTM_DUAL.FEC_SCANOUT_SF57
TCELL2:OUT.12GTM_DUAL.FEC_SCANOUT_SF58
TCELL2:OUT.13GTM_DUAL.FEC_SCANOUT_SF59
TCELL2:OUT.14GTM_DUAL.FEC_SCANOUT_SF60
TCELL2:OUT.16GTM_DUAL.FEC_SCANOUT_SF61
TCELL2:OUT.17GTM_DUAL.FEC_SCANOUT_SF62
TCELL2:OUT.18GTM_DUAL.FEC_SCANOUT_SF63
TCELL2:OUT.19GTM_DUAL.FEC_SCANOUT_SF64
TCELL2:OUT.20GTM_DUAL.FEC_SCANOUT_SF65
TCELL2:OUT.21GTM_DUAL.FEC_SCANOUT_SF66
TCELL2:OUT.22GTM_DUAL.FEC_SCANOUT_SF67
TCELL2:OUT.24GTM_DUAL.FEC_SCANOUT_SF68
TCELL2:OUT.25GTM_DUAL.FEC_SCANOUT_SF69
TCELL2:OUT.26GTM_DUAL.FEC_SCANOUT_SF70
TCELL2:OUT.27GTM_DUAL.FEC_SCANOUT_SF71
TCELL2:OUT.28GTM_DUAL.FEC_SCANOUT_SF72
TCELL2:OUT.29GTM_DUAL.FEC_SCANOUT_SF73
TCELL2:OUT.30GTM_DUAL.FEC_SCANOUT_SF74
TCELL2:IMUX.IMUX.0GTM_DUAL.FEC_SCANIN_FS44
TCELL2:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS47
TCELL2:IMUX.IMUX.2GTM_DUAL.FEC_SCANIN_FS50
TCELL2:IMUX.IMUX.3GTM_DUAL.FEC_SCANIN_FS52
TCELL2:IMUX.IMUX.4GTM_DUAL.FEC_SCANIN_FS55
TCELL2:IMUX.IMUX.6GTM_DUAL.FEC_SCANIN_FS60
TCELL2:IMUX.IMUX.7GTM_DUAL.FEC_SCANIN_FS63
TCELL2:IMUX.IMUX.8GTM_DUAL.FEC_SCANIN_FS65
TCELL2:IMUX.IMUX.9GTM_DUAL.FEC_SCANIN_FS68
TCELL2:IMUX.IMUX.10GTM_DUAL.FEC_SCANIN_FS71
TCELL2:IMUX.IMUX.11GTM_DUAL.FEC_SCANIN_FS73
TCELL2:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS76
TCELL2:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS81
TCELL2:IMUX.IMUX.15GTM_DUAL.FEC_SCANIN_FS84
TCELL2:IMUX.IMUX.16GTM_DUAL.FEC_SCANIN_FS45
TCELL2:IMUX.IMUX.17GTM_DUAL.FEC_SCANIN_FS46
TCELL2:IMUX.IMUX.18GTM_DUAL.FEC_SCANIN_FS48
TCELL2:IMUX.IMUX.19GTM_DUAL.FEC_SCANIN_FS49
TCELL2:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS51
TCELL2:IMUX.IMUX.22GTM_DUAL.FEC_SCANIN_FS53
TCELL2:IMUX.IMUX.23GTM_DUAL.FEC_SCANIN_FS54
TCELL2:IMUX.IMUX.24GTM_DUAL.FEC_SCANIN_FS56
TCELL2:IMUX.IMUX.25GTM_DUAL.FEC_SCANIN_FS57
TCELL2:IMUX.IMUX.26GTM_DUAL.FEC_SCANIN_FS58
TCELL2:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS59
TCELL2:IMUX.IMUX.28GTM_DUAL.FEC_SCANIN_FS61
TCELL2:IMUX.IMUX.29GTM_DUAL.FEC_SCANIN_FS62
TCELL2:IMUX.IMUX.30GTM_DUAL.FEC_SCANIN_FS64
TCELL2:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS66
TCELL2:IMUX.IMUX.33GTM_DUAL.FEC_SCANIN_FS67
TCELL2:IMUX.IMUX.34GTM_DUAL.FEC_SCANIN_FS69
TCELL2:IMUX.IMUX.35GTM_DUAL.FEC_SCANIN_FS70
TCELL2:IMUX.IMUX.37GTM_DUAL.FEC_SCANIN_FS72
TCELL2:IMUX.IMUX.38GTM_DUAL.FEC_SCANIN_FS74
TCELL2:IMUX.IMUX.39GTM_DUAL.FEC_SCANIN_FS75
TCELL2:IMUX.IMUX.40GTM_DUAL.FEC_SCANIN_FS77
TCELL2:IMUX.IMUX.41GTM_DUAL.FEC_SCANIN_FS78
TCELL2:IMUX.IMUX.42GTM_DUAL.FEC_SCANIN_FS79
TCELL2:IMUX.IMUX.43GTM_DUAL.FEC_SCANIN_FS80
TCELL2:IMUX.IMUX.44GTM_DUAL.FEC_SCANIN_FS82
TCELL2:IMUX.IMUX.45GTM_DUAL.FEC_SCANIN_FS83
TCELL2:IMUX.IMUX.46GTM_DUAL.FEC_SCANIN_FS85
TCELL3:OUT.0GTM_DUAL.FEC_SCANOUT_SF75
TCELL3:OUT.1GTM_DUAL.FEC_SCANOUT_SF76
TCELL3:OUT.2GTM_DUAL.DMONOUT_CH0_SF10
TCELL3:OUT.3GTM_DUAL.FEC_SCANOUT_SF77
TCELL3:OUT.4GTM_DUAL.FEC_SCANOUT_SF78
TCELL3:OUT.5GTM_DUAL.FEC_SCANOUT_SF79
TCELL3:OUT.7GTM_DUAL.FEC_SCANOUT_SF80
TCELL3:OUT.8GTM_DUAL.FEC_SCANOUT_SF81
TCELL3:OUT.9GTM_DUAL.FEC_SCANOUT_SF82
TCELL3:OUT.10GTM_DUAL.FEC_SCANOUT_SF83
TCELL3:OUT.11GTM_DUAL.DMONOUT_CH0_SF8
TCELL3:OUT.12GTM_DUAL.DMONOUT_CH0_SF9
TCELL3:OUT.13GTM_DUAL.FEC_SCANOUT_SF84
TCELL3:OUT.14GTM_DUAL.DMONOUT_CH0_SF7
TCELL3:OUT.16GTM_DUAL.FEC_SCANOUT_SF85
TCELL3:OUT.17GTM_DUAL.DMONOUT_CH0_SF6
TCELL3:OUT.18GTM_DUAL.FEC_SCANOUT_SF86
TCELL3:OUT.19GTM_DUAL.FEC_SCANOUT_SF87
TCELL3:OUT.20GTM_DUAL.DMONOUT_CH0_SF5
TCELL3:OUT.21GTM_DUAL.FEC_SCANOUT_SF88
TCELL3:OUT.22GTM_DUAL.FEC_SCANOUT_SF89
TCELL3:OUT.24GTM_DUAL.PCS_RSVDOUT_CH0_SF0
TCELL3:OUT.25GTM_DUAL.FEC_SCANOUT_SF90
TCELL3:OUT.26GTM_DUAL.FEC_SCANOUT_SF91
TCELL3:OUT.27GTM_DUAL.FEC_SCANOUT_SF92
TCELL3:OUT.28GTM_DUAL.DMONOUT_CH0_SF11
TCELL3:OUT.29GTM_DUAL.DMONOUT_CH0_SF12
TCELL3:OUT.30GTM_DUAL.FEC_SCANOUT_SF93
TCELL3:IMUX.IMUX.0GTM_DUAL.PMA_SCANIN_CH0_FS9
TCELL3:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS86
TCELL3:IMUX.IMUX.7GTM_DUAL.FEC_SCANIN_FS89
TCELL3:IMUX.IMUX.8GTM_DUAL.PMA_RSVDIN_CH0_FS0
TCELL3:IMUX.IMUX.12GTM_DUAL.PMA_SCANIN_CH0_FS11
TCELL3:IMUX.IMUX.13GTM_DUAL.AXIS_EYESCANRST_CH0_FS
TCELL3:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS87
TCELL3:IMUX.IMUX.25GTM_DUAL.FEC_SCANIN_FS88
TCELL3:IMUX.IMUX.28GTM_DUAL.PMA_SCANIN_CH0_FS7
TCELL3:IMUX.IMUX.32GTM_DUAL.PMA_RSVDIN_CH0_FS1
TCELL3:IMUX.IMUX.34GTM_DUAL.FEC_SCANIN_FS90
TCELL3:IMUX.IMUX.38GTM_DUAL.FEC_SCANIN_FS91
TCELL3:IMUX.IMUX.40GTM_DUAL.PMA_SCANIN_CH0_FS10
TCELL3:IMUX.IMUX.44GTM_DUAL.FEC_SCANIN_FS92
TCELL3:IMUX.IMUX.47GTM_DUAL.PMA_SCANIN_CH0_FS8
TCELL4:OUT.0GTM_DUAL.FEC_SCANOUT_SF94
TCELL4:OUT.1GTM_DUAL.FEC_SCANOUT_SF95
TCELL4:OUT.2GTM_DUAL.FEC_SCANOUT_SF96
TCELL4:OUT.3GTM_DUAL.FEC_SCANOUT_SF97
TCELL4:OUT.4GTM_DUAL.FEC_SCANOUT_SF98
TCELL4:OUT.5GTM_DUAL.FEC_SCANOUT_SF99
TCELL4:OUT.6GTM_DUAL.FEC_SCANOUT_SF100
TCELL4:OUT.8GTM_DUAL.FEC_SCANOUT_SF101
TCELL4:OUT.9GTM_DUAL.FEC_SCANOUT_SF102
TCELL4:OUT.10GTM_DUAL.FEC_SCANOUT_SF103
TCELL4:OUT.11GTM_DUAL.FEC_SCANOUT_SF104
TCELL4:OUT.12GTM_DUAL.FEC_SCANOUT_SF105
TCELL4:OUT.13GTM_DUAL.FEC_SCANOUT_SF106
TCELL4:OUT.14GTM_DUAL.FEC_SCANOUT_SF107
TCELL4:OUT.16GTM_DUAL.FEC_SCANOUT_SF108
TCELL4:OUT.17GTM_DUAL.FEC_SCANOUT_SF109
TCELL4:OUT.18GTM_DUAL.FEC_SCANOUT_SF110
TCELL4:OUT.19GTM_DUAL.FEC_SCANOUT_SF111
TCELL4:OUT.20GTM_DUAL.FEC_SCANOUT_SF112
TCELL4:OUT.21GTM_DUAL.FEC_SCANOUT_SF113
TCELL4:OUT.22GTM_DUAL.FEC_SCANOUT_SF114
TCELL4:OUT.23GTM_DUAL.RESET_EXCEPTION_CH0_SF
TCELL4:OUT.25GTM_DUAL.FEC_SCANOUT_SF115
TCELL4:OUT.26GTM_DUAL.FEC_SCANOUT_SF116
TCELL4:OUT.27GTM_DUAL.FEC_SCANOUT_SF117
TCELL4:OUT.28GTM_DUAL.FEC_SCANOUT_SF118
TCELL4:OUT.29GTM_DUAL.FEC_SCANOUT_SF119
TCELL4:OUT.30GTM_DUAL.FEC_SCANOUT_SF120
TCELL4:IMUX.IMUX.11GTM_DUAL.FEC_SCANIN_FS103
TCELL4:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS104
TCELL4:IMUX.IMUX.13GTM_DUAL.FEC_SCANIN_FS105
TCELL4:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS106
TCELL4:IMUX.IMUX.15GTM_DUAL.FEC_SCANIN_FS107
TCELL4:IMUX.IMUX.16GTM_DUAL.FEC_SCANIN_FS93
TCELL4:IMUX.IMUX.18GTM_DUAL.FEC_SCANIN_FS94
TCELL4:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS95
TCELL4:IMUX.IMUX.22GTM_DUAL.FEC_SCANIN_FS96
TCELL4:IMUX.IMUX.24GTM_DUAL.FEC_SCANIN_FS97
TCELL4:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS98
TCELL4:IMUX.IMUX.29GTM_DUAL.FEC_SCANIN_FS99
TCELL4:IMUX.IMUX.31GTM_DUAL.FEC_SCANIN_FS100
TCELL4:IMUX.IMUX.33GTM_DUAL.FEC_SCANIN_FS101
TCELL4:IMUX.IMUX.35GTM_DUAL.FEC_SCANIN_FS102
TCELL5:OUT.0GTM_DUAL.FEC_SCANOUT_SF121
TCELL5:OUT.1GTM_DUAL.FEC_SCANOUT_SF122
TCELL5:OUT.2GTM_DUAL.FEC_SCANOUT_SF123
TCELL5:OUT.3GTM_DUAL.FEC_SCANOUT_SF124
TCELL5:OUT.4GTM_DUAL.FEC_SCANOUT_SF125
TCELL5:OUT.5GTM_DUAL.FEC_SCANOUT_SF126
TCELL5:OUT.6GTM_DUAL.DMONOUT_CH0_SF13
TCELL5:OUT.7GTM_DUAL.FEC_SCANOUT_SF127
TCELL5:OUT.9GTM_DUAL.FEC_SCANOUT_SF128
TCELL5:OUT.10GTM_DUAL.FEC_SCANOUT_SF129
TCELL5:OUT.11GTM_DUAL.FEC_SCANOUT_SF130
TCELL5:OUT.12GTM_DUAL.FEC_SCANOUT_SF131
TCELL5:OUT.13GTM_DUAL.FEC_SCANOUT_SF132
TCELL5:OUT.14GTM_DUAL.FEC_SCANOUT_SF133
TCELL5:OUT.16GTM_DUAL.FEC_SCANOUT_SF134
TCELL5:OUT.17GTM_DUAL.FEC_SCANOUT_SF135
TCELL5:OUT.18GTM_DUAL.FEC_SCANOUT_SF136
TCELL5:OUT.19GTM_DUAL.DMONOUT_CH0_SF14
TCELL5:OUT.20GTM_DUAL.FEC_SCANOUT_SF137
TCELL5:OUT.21GTM_DUAL.FEC_SCANOUT_SF138
TCELL5:OUT.22GTM_DUAL.FEC_SCANOUT_SF139
TCELL5:OUT.24GTM_DUAL.FEC_SCANOUT_SF140
TCELL5:OUT.25GTM_DUAL.DMONOUT_CH0_SF15
TCELL5:OUT.26GTM_DUAL.FEC_SCANOUT_SF141
TCELL5:OUT.27GTM_DUAL.FEC_SCANOUT_SF142
TCELL5:OUT.28GTM_DUAL.FEC_SCANOUT_SF143
TCELL5:OUT.29GTM_DUAL.FEC_SCANOUT_SF144
TCELL5:OUT.30GTM_DUAL.FEC_SCANOUT_SF145
TCELL5:IMUX.IMUX.0GTM_DUAL.TXDATA_CH0_FS5
TCELL5:IMUX.IMUX.2GTM_DUAL.TXDATA_CH0_FS4
TCELL5:IMUX.IMUX.3GTM_DUAL.TXDATA_CH0_FS19
TCELL5:IMUX.IMUX.4GTM_DUAL.TXDATA_CH0_FS30
TCELL5:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS21
TCELL5:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS33
TCELL5:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS27
TCELL5:IMUX.IMUX.8GTM_DUAL.TXDATA_CH0_FS13
TCELL5:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS31
TCELL5:IMUX.IMUX.11GTM_DUAL.TXDATA_CH0_FS25
TCELL5:IMUX.IMUX.12GTM_DUAL.TXDATA_CH0_FS15
TCELL5:IMUX.IMUX.13GTM_DUAL.TXDATA_CH0_FS8
TCELL5:IMUX.IMUX.15GTM_DUAL.TXDATA_START_CH0_FS
TCELL5:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS6
TCELL5:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS2
TCELL5:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS23
TCELL5:IMUX.IMUX.19GTM_DUAL.TXDATA_CH0_FS9
TCELL5:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS22
TCELL5:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS17
TCELL5:IMUX.IMUX.23GTM_DUAL.TXDATA_CH0_FS29
TCELL5:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS18
TCELL5:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS7
TCELL5:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS3
TCELL5:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS10
TCELL5:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS14
TCELL5:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS20
TCELL5:IMUX.IMUX.35GTM_DUAL.TXDATA_CH0_FS34
TCELL5:IMUX.IMUX.36GTM_DUAL.TXDATA_CH0_FS11
TCELL5:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS26
TCELL5:IMUX.IMUX.38GTM_DUAL.TXDATA_CH0_FS12
TCELL5:IMUX.IMUX.39GTM_DUAL.TXDATA_CH0_FS1
TCELL5:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS35
TCELL5:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS24
TCELL5:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS16
TCELL5:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS32
TCELL5:IMUX.IMUX.46GTM_DUAL.TXDATA_CH0_FS28
TCELL5:IMUX.IMUX.47GTM_DUAL.TXDATA_CH0_FS0
TCELL6:OUT.0GTM_DUAL.FEC_SCANOUT_SF146
TCELL6:OUT.1GTM_DUAL.PMA_SCANOUT_CH0_SF3
TCELL6:OUT.2GTM_DUAL.FEC_SCANOUT_SF147
TCELL6:OUT.3GTM_DUAL.DMONOUT_CH0_SF18
TCELL6:OUT.4GTM_DUAL.FEC_SCANOUT_SF148
TCELL6:OUT.5GTM_DUAL.FEC_SCANOUT_SF149
TCELL6:OUT.6GTM_DUAL.DMONOUT_CH0_SF17
TCELL6:OUT.7GTM_DUAL.FEC_SCANOUT_SF150
TCELL6:OUT.8GTM_DUAL.DMONOUT_CH0_SF19
TCELL6:OUT.10GTM_DUAL.FEC_SCANOUT_SF151
TCELL6:OUT.11GTM_DUAL.FEC_SCANOUT_SF152
TCELL6:OUT.12GTM_DUAL.FEC_SCANOUT_SF153
TCELL6:OUT.13GTM_DUAL.DMONOUT_CH0_SF16
TCELL6:OUT.14GTM_DUAL.FEC_SCANOUT_SF154
TCELL6:OUT.15GTM_DUAL.FEC_SCANOUT_SF155
TCELL6:OUT.17GTM_DUAL.FEC_SCANOUT_SF156
TCELL6:OUT.18GTM_DUAL.FEC_SCANOUT_SF157
TCELL6:OUT.19GTM_DUAL.FEC_SCANOUT_SF158
TCELL6:OUT.20GTM_DUAL.FEC_SCANOUT_SF159
TCELL6:OUT.21GTM_DUAL.FEC_SCANOUT_SF160
TCELL6:OUT.22GTM_DUAL.PMA_SCANOUT_CH0_SF4
TCELL6:OUT.23GTM_DUAL.PMA_SCANOUT_CH0_SF2
TCELL6:OUT.25GTM_DUAL.FEC_SCANOUT_SF161
TCELL6:OUT.26GTM_DUAL.FEC_SCANOUT_SF162
TCELL6:OUT.27GTM_DUAL.PMA_RSVDOUT_CH0_SF0
TCELL6:OUT.28GTM_DUAL.FEC_SCANOUT_SF163
TCELL6:OUT.29GTM_DUAL.FEC_SCANOUT_SF164
TCELL6:OUT.30GTM_DUAL.FEC_SCANOUT_SF165
TCELL6:IMUX.CTRL.7GTM_DUAL.TSTCLK0_CH0_FS
TCELL6:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS51
TCELL6:IMUX.IMUX.2GTM_DUAL.TXDATA_CH0_FS60
TCELL6:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS46
TCELL6:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS57
TCELL6:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS43
TCELL6:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS55
TCELL6:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS39
TCELL6:IMUX.IMUX.11GTM_DUAL.TXDATA_CH0_FS58
TCELL6:IMUX.IMUX.13GTM_DUAL.TXDATA_CH0_FS72
TCELL6:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS61
TCELL6:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS54
TCELL6:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS48
TCELL6:IMUX.IMUX.19GTM_DUAL.TXDATA_CH0_FS71
TCELL6:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS42
TCELL6:IMUX.IMUX.21GTM_DUAL.TXDATA_CH0_FS67
TCELL6:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS44
TCELL6:IMUX.IMUX.23GTM_DUAL.TXDATA_CH0_FS41
TCELL6:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS38
TCELL6:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS47
TCELL6:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS52
TCELL6:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS37
TCELL6:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS65
TCELL6:IMUX.IMUX.29GTM_DUAL.TXDATA_CH0_FS53
TCELL6:IMUX.IMUX.30GTM_DUAL.TXDATA_CH0_FS36
TCELL6:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS69
TCELL6:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS62
TCELL6:IMUX.IMUX.34GTM_DUAL.TXDATA_CH0_FS64
TCELL6:IMUX.IMUX.36GTM_DUAL.TXDATA_CH0_FS63
TCELL6:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS50
TCELL6:IMUX.IMUX.38GTM_DUAL.TXDATA_CH0_FS66
TCELL6:IMUX.IMUX.39GTM_DUAL.TXDATA_CH0_FS56
TCELL6:IMUX.IMUX.40GTM_DUAL.TXDATA_CH0_FS45
TCELL6:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS68
TCELL6:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS70
TCELL6:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS49
TCELL6:IMUX.IMUX.45GTM_DUAL.TXDATA_CH0_FS59
TCELL6:IMUX.IMUX.46GTM_DUAL.TXDATA_CH0_FS40
TCELL7:OUT.0GTM_DUAL.PCS_RSVDOUT_CH0_SF8
TCELL7:OUT.1GTM_DUAL.PMA_SCANOUT_CH0_SF5
TCELL7:OUT.6GTM_DUAL.DMONOUT_CH0_SF23
TCELL7:OUT.7GTM_DUAL.DMONOUT_CH0_SF22
TCELL7:OUT.8GTM_DUAL.PMA_SCANOUT_CH0_SF6
TCELL7:OUT.9GTM_DUAL.PCS_RSVDOUT_CH0_SF1
TCELL7:OUT.10GTM_DUAL.PCS_RSVDOUT_CH0_SF6
TCELL7:OUT.13GTM_DUAL.PCS_RSVDOUT_CH0_SF4
TCELL7:OUT.15GTM_DUAL.PCS_RSVDOUT_CH0_SF3
TCELL7:OUT.18GTM_DUAL.DMONOUT_CH0_SF21
TCELL7:OUT.20GTM_DUAL.PCS_RSVDOUT_CH0_SF5
TCELL7:OUT.27GTM_DUAL.PCS_RSVDOUT_CH0_SF7
TCELL7:OUT.28GTM_DUAL.DMONOUT_CH0_SF20
TCELL7:OUT.29GTM_DUAL.PCS_RSVDOUT_CH0_SF2
TCELL7:OUT.30GTM_DUAL.PMA_SCANOUT_CH0_SF7
TCELL7:OUT.31GTM_DUAL.PMA_RSVDOUT_CH0_SF1
TCELL7:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS77
TCELL7:IMUX.IMUX.2GTM_DUAL.TXDATA_CH0_FS107
TCELL7:IMUX.IMUX.3GTM_DUAL.TXDATA_CH0_FS104
TCELL7:IMUX.IMUX.4GTM_DUAL.TXDATA_CH0_FS83
TCELL7:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS100
TCELL7:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS80
TCELL7:IMUX.IMUX.8GTM_DUAL.TXDATA_CH0_FS78
TCELL7:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS101
TCELL7:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS110
TCELL7:IMUX.IMUX.14GTM_DUAL.TXDATA_CH0_FS105
TCELL7:IMUX.IMUX.15GTM_DUAL.TXDATA_CH0_FS84
TCELL7:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS81
TCELL7:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS90
TCELL7:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS102
TCELL7:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS92
TCELL7:IMUX.IMUX.21GTM_DUAL.TXDATA_CH0_FS94
TCELL7:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS95
TCELL7:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS96
TCELL7:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS86
TCELL7:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS98
TCELL7:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS88
TCELL7:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS75
TCELL7:IMUX.IMUX.29GTM_DUAL.TXDATA_CH0_FS79
TCELL7:IMUX.IMUX.30GTM_DUAL.TXDATA_CH0_FS109
TCELL7:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS82
TCELL7:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS89
TCELL7:IMUX.IMUX.34GTM_DUAL.TXDATA_CH0_FS91
TCELL7:IMUX.IMUX.35GTM_DUAL.TXDATA_CH0_FS87
TCELL7:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS73
TCELL7:IMUX.IMUX.38GTM_DUAL.TXDATA_CH0_FS106
TCELL7:IMUX.IMUX.40GTM_DUAL.TXDATA_CH0_FS99
TCELL7:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS93
TCELL7:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS74
TCELL7:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS108
TCELL7:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS76
TCELL7:IMUX.IMUX.45GTM_DUAL.TXDATA_CH0_FS103
TCELL7:IMUX.IMUX.46GTM_DUAL.TXDATA_CH0_FS97
TCELL7:IMUX.IMUX.47GTM_DUAL.TXDATA_CH0_FS85
TCELL8:OUT.1GTM_DUAL.PMA_RSVDOUT_CH0_SF7
TCELL8:OUT.6GTM_DUAL.PMA_RSVDOUT_CH0_SF5
TCELL8:OUT.8GTM_DUAL.PMA_RSVDOUT_CH0_SF2
TCELL8:OUT.11GTM_DUAL.RXRESETDONE_CH0_SF
TCELL8:OUT.13GTM_DUAL.PMA_RSVDOUT_CH0_SF3
TCELL8:OUT.15GTM_DUAL.PMA_SCANOUT_CH0_SF8
TCELL8:OUT.18GTM_DUAL.PMA_RSVDOUT_CH0_SF4
TCELL8:OUT.26GTM_DUAL.DMONOUT_CH0_SF24
TCELL8:OUT.30GTM_DUAL.PMA_RSVDOUT_CH0_SF6
TCELL8:OUT.31GTM_DUAL.PMA_SCANOUT_CH0_SF9
TCELL8:IMUX.CTRL.3GTM_DUAL.TSTCLK1_CH0_FS
TCELL8:IMUX.IMUX.0GTM_DUAL.TXDATA_CH0_FS122
TCELL8:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS132
TCELL8:IMUX.IMUX.3GTM_DUAL.TXDATA_CH0_FS113
TCELL8:IMUX.IMUX.4GTM_DUAL.TXDATA_CH0_FS129
TCELL8:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS126
TCELL8:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS148
TCELL8:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS119
TCELL8:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS111
TCELL8:IMUX.IMUX.11GTM_DUAL.TXDATA_CH0_FS120
TCELL8:IMUX.IMUX.12GTM_DUAL.TXDATA_CH0_FS128
TCELL8:IMUX.IMUX.13GTM_DUAL.TXDATA_CH0_FS127
TCELL8:IMUX.IMUX.15GTM_DUAL.TXDATA_CH0_FS131
TCELL8:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS116
TCELL8:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS121
TCELL8:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS142
TCELL8:IMUX.IMUX.19GTM_DUAL.TXDATA_CH0_FS112
TCELL8:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS137
TCELL8:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS139
TCELL8:IMUX.IMUX.23GTM_DUAL.TXDATA_CH0_FS114
TCELL8:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS118
TCELL8:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS138
TCELL8:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS147
TCELL8:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS115
TCELL8:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS123
TCELL8:IMUX.IMUX.30GTM_DUAL.TXDATA_CH0_FS140
TCELL8:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS117
TCELL8:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS136
TCELL8:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS125
TCELL8:IMUX.IMUX.34GTM_DUAL.TXDATA_CH0_FS146
TCELL8:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS141
TCELL8:IMUX.IMUX.38GTM_DUAL.TXDATA_CH0_FS133
TCELL8:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS135
TCELL8:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS124
TCELL8:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS134
TCELL8:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS143
TCELL8:IMUX.IMUX.45GTM_DUAL.TXDATA_CH0_FS145
TCELL8:IMUX.IMUX.46GTM_DUAL.TXDATA_CH0_FS130
TCELL8:IMUX.IMUX.47GTM_DUAL.TXDATA_CH0_FS144
TCELL9:OUT.1GTM_DUAL.RXDATA_CH0_SF22
TCELL9:OUT.2GTM_DUAL.RXDATA_CH0_SF25
TCELL9:OUT.3GTM_DUAL.RXDATA_FLAGS_CH0_SF0
TCELL9:OUT.4GTM_DUAL.RXDATA_CH0_SF26
TCELL9:OUT.5GTM_DUAL.RXDATA_CH0_SF9
TCELL9:OUT.6GTM_DUAL.RXDATA_CH0_SF16
TCELL9:OUT.7GTM_DUAL.RXDATA_CH0_SF21
TCELL9:OUT.8GTM_DUAL.RXDATA_CH0_SF6
TCELL9:OUT.10GTM_DUAL.RXDATA_CH0_SF8
TCELL9:OUT.11GTM_DUAL.RXDATA_CH0_SF10
TCELL9:OUT.12GTM_DUAL.RXDATA_CH0_SF1
TCELL9:OUT.13GTM_DUAL.RXDATA_CH0_SF7
TCELL9:OUT.14GTM_DUAL.RXDATA_CH0_SF4
TCELL9:OUT.15GTM_DUAL.RXDATA_CH0_SF3
TCELL9:OUT.16GTM_DUAL.RXDATA_CH0_SF18
TCELL9:OUT.17GTM_DUAL.RXDATA_CH0_SF23
TCELL9:OUT.18GTM_DUAL.RXDATA_CH0_SF13
TCELL9:OUT.19GTM_DUAL.RXDATA_CH0_SF5
TCELL9:OUT.20GTM_DUAL.RXDATA_CH0_SF11
TCELL9:OUT.22GTM_DUAL.RXDATA_CH0_SF0
TCELL9:OUT.23GTM_DUAL.RXDATA_CH0_SF20
TCELL9:OUT.24GTM_DUAL.RXDATA_CH0_SF17
TCELL9:OUT.25GTM_DUAL.RXDATA_CH0_SF24
TCELL9:OUT.26GTM_DUAL.RXDATA_CH0_SF15
TCELL9:OUT.28GTM_DUAL.RXDATA_CH0_SF12
TCELL9:OUT.29GTM_DUAL.RXDATA_CH0_SF14
TCELL9:OUT.30GTM_DUAL.RXDATA_CH0_SF2
TCELL9:OUT.31GTM_DUAL.RXDATA_CH0_SF19
TCELL9:IMUX.IMUX.0GTM_DUAL.TXDATA_CH0_FS161
TCELL9:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS156
TCELL9:IMUX.IMUX.3GTM_DUAL.TXDATA_CH0_FS180
TCELL9:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS159
TCELL9:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS173
TCELL9:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS174
TCELL9:IMUX.IMUX.8GTM_DUAL.TXDATA_CH0_FS165
TCELL9:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS151
TCELL9:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS166
TCELL9:IMUX.IMUX.11GTM_DUAL.TXDATA_CH0_FS162
TCELL9:IMUX.IMUX.12GTM_DUAL.TXDATA_CH0_FS163
TCELL9:IMUX.IMUX.13GTM_DUAL.TXDATA_CH0_FS177
TCELL9:IMUX.IMUX.14GTM_DUAL.TXDATA_CH0_FS155
TCELL9:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS171
TCELL9:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS181
TCELL9:IMUX.IMUX.21GTM_DUAL.TXDATA_CH0_FS168
TCELL9:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS158
TCELL9:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS172
TCELL9:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS149
TCELL9:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS169
TCELL9:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS157
TCELL9:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS154
TCELL9:IMUX.IMUX.29GTM_DUAL.TXDATA_CH0_FS153
TCELL9:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS179
TCELL9:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS182
TCELL9:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS178
TCELL9:IMUX.IMUX.34GTM_DUAL.TXDATA_CH0_FS170
TCELL9:IMUX.IMUX.35GTM_DUAL.TXDATA_CH0_FS164
TCELL9:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS150
TCELL9:IMUX.IMUX.39GTM_DUAL.TXDATA_CH0_FS176
TCELL9:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS160
TCELL9:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS175
TCELL9:IMUX.IMUX.45GTM_DUAL.TXDATA_CH0_FS152
TCELL9:IMUX.IMUX.47GTM_DUAL.TXDATA_CH0_FS167
TCELL10:OUT.0GTM_DUAL.RXDATA_CH0_SF41
TCELL10:OUT.1GTM_DUAL.RXDATA_CH0_SF42
TCELL10:OUT.2GTM_DUAL.RXDATA_CH0_SF37
TCELL10:OUT.3GTM_DUAL.RXDATA_CH0_SF27
TCELL10:OUT.4GTM_DUAL.RXDATA_CH0_SF29
TCELL10:OUT.5GTM_DUAL.RXDATA_CH0_SF36
TCELL10:OUT.6GTM_DUAL.RXDATA_CH0_SF39
TCELL10:OUT.7GTM_DUAL.RXDATA_CH0_SF48
TCELL10:OUT.8GTM_DUAL.RXDATA_CH0_SF54
TCELL10:OUT.9GTM_DUAL.RXDATA_CH0_SF45
TCELL10:OUT.10GTM_DUAL.RXDATA_CH0_SF35
TCELL10:OUT.11GTM_DUAL.RXDATA_CH0_SF44
TCELL10:OUT.12GTM_DUAL.RXDATA_CH0_SF51
TCELL10:OUT.14GTM_DUAL.RXDATA_CH0_SF53
TCELL10:OUT.15GTM_DUAL.RXDATA_CH0_SF28
TCELL10:OUT.17GTM_DUAL.RXDATA_CH0_SF30
TCELL10:OUT.18GTM_DUAL.RXDATA_CH0_SF31
TCELL10:OUT.19GTM_DUAL.RXDATA_CH0_SF32
TCELL10:OUT.21GTM_DUAL.RXDATA_CH0_SF33
TCELL10:OUT.22GTM_DUAL.RXDATA_CH0_SF38
TCELL10:OUT.23GTM_DUAL.RXDATA_CH0_SF43
TCELL10:OUT.24GTM_DUAL.RXDATA_CH0_SF50
TCELL10:OUT.25GTM_DUAL.RXDATA_CH0_SF46
TCELL10:OUT.26GTM_DUAL.RXDATA_CH0_SF40
TCELL10:OUT.27GTM_DUAL.RXDATA_CH0_SF34
TCELL10:OUT.28GTM_DUAL.RXDATA_CH0_SF52
TCELL10:OUT.29GTM_DUAL.RXDATA_CH0_SF47
TCELL10:OUT.30GTM_DUAL.RXDATA_CH0_SF49
TCELL10:IMUX.IMUX.0GTM_DUAL.TXDATA_CH0_FS202
TCELL10:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS203
TCELL10:IMUX.IMUX.2GTM_DUAL.TXDATA_CH0_FS189
TCELL10:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS183
TCELL10:IMUX.IMUX.6GTM_DUAL.TXDATA_CH0_FS191
TCELL10:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS216
TCELL10:IMUX.IMUX.8GTM_DUAL.TXDATA_CH0_FS205
TCELL10:IMUX.IMUX.9GTM_DUAL.TXDATA_CH0_FS198
TCELL10:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS199
TCELL10:IMUX.IMUX.12GTM_DUAL.TXDATA_CH0_FS215
TCELL10:IMUX.IMUX.14GTM_DUAL.TXDATA_CH0_FS213
TCELL10:IMUX.IMUX.15GTM_DUAL.TXDATA_CH0_FS217
TCELL10:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS190
TCELL10:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS208
TCELL10:IMUX.IMUX.19GTM_DUAL.TXDATA_CH0_FS209
TCELL10:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS185
TCELL10:IMUX.IMUX.21GTM_DUAL.TXDATA_CH0_FS187
TCELL10:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS192
TCELL10:IMUX.IMUX.23GTM_DUAL.TXDATA_CH0_FS193
TCELL10:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS211
TCELL10:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS212
TCELL10:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS195
TCELL10:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS207
TCELL10:IMUX.IMUX.29GTM_DUAL.TXDATA_CH0_FS201
TCELL10:IMUX.IMUX.30GTM_DUAL.TXDATA_CH0_FS186
TCELL10:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS184
TCELL10:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS200
TCELL10:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS196
TCELL10:IMUX.IMUX.34GTM_DUAL.TXDATA_CH0_FS197
TCELL10:IMUX.IMUX.35GTM_DUAL.TXDATA_CH0_FS204
TCELL10:IMUX.IMUX.40GTM_DUAL.TXDATA_CH0_FS188
TCELL10:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS194
TCELL10:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS214
TCELL10:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS210
TCELL10:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS206
TCELL11:OUT.0GTM_DUAL.RXDATA_CH0_SF58
TCELL11:OUT.1GTM_DUAL.RXDATA_CH0_SF57
TCELL11:OUT.2GTM_DUAL.RXDATA_CH0_SF71
TCELL11:OUT.4GTM_DUAL.RXDATA_CH0_SF72
TCELL11:OUT.5GTM_DUAL.ST_RX0_CORR_CW_INC_SF
TCELL11:OUT.6GTM_DUAL.RXDATA_CH0_SF73
TCELL11:OUT.7GTM_DUAL.RXDATA_CH0_SF59
TCELL11:OUT.8GTM_DUAL.RXDATA_CH0_SF62
TCELL11:OUT.9GTM_DUAL.RXDATA_CH0_SF65
TCELL11:OUT.11GTM_DUAL.RXDATA_CH0_SF63
TCELL11:OUT.12GTM_DUAL.RXDATA_CH0_SF61
TCELL11:OUT.13GTM_DUAL.RXDATA_CH0_SF66
TCELL11:OUT.14GTM_DUAL.RXDATA_CH0_SF78
TCELL11:OUT.15GTM_DUAL.RXDATA_CH0_SF74
TCELL11:OUT.16GTM_DUAL.RXDATA_CH0_SF60
TCELL11:OUT.17GTM_DUAL.RXDATA_CH0_SF77
TCELL11:OUT.18GTM_DUAL.RXDATA_CH0_SF70
TCELL11:OUT.19GTM_DUAL.RXDATA_CH0_SF64
TCELL11:OUT.20GTM_DUAL.RXDATA_CH0_SF56
TCELL11:OUT.21GTM_DUAL.RXDATA_CH0_SF68
TCELL11:OUT.22GTM_DUAL.RXDATA_CH0_SF55
TCELL11:OUT.23GTM_DUAL.RXDATA_CH0_SF75
TCELL11:OUT.24GTM_DUAL.ST_RX0_CW_INC_SF
TCELL11:OUT.26GTM_DUAL.ST_RX0_FEC_ALIGNED_SF
TCELL11:OUT.28GTM_DUAL.ST_RX0_UNCORR_CW_INC_SF
TCELL11:OUT.29GTM_DUAL.RXDATA_CH0_SF69
TCELL11:OUT.30GTM_DUAL.RXDATA_CH0_SF67
TCELL11:OUT.31GTM_DUAL.RXDATA_CH0_SF76
TCELL11:IMUX.IMUX.0GTM_DUAL.TXDATA_CH0_FS225
TCELL11:IMUX.IMUX.1GTM_DUAL.TXDATA_CH0_FS249
TCELL11:IMUX.IMUX.2GTM_DUAL.TXDATA_CH0_FS226
TCELL11:IMUX.IMUX.3GTM_DUAL.TXDATA_CH0_FS222
TCELL11:IMUX.IMUX.4GTM_DUAL.TXDATA_CH0_FS220
TCELL11:IMUX.IMUX.5GTM_DUAL.TXDATA_CH0_FS253
TCELL11:IMUX.IMUX.7GTM_DUAL.TXDATA_CH0_FS244
TCELL11:IMUX.IMUX.8GTM_DUAL.TXDATA_CH0_FS228
TCELL11:IMUX.IMUX.10GTM_DUAL.TXDATA_CH0_FS218
TCELL11:IMUX.IMUX.11GTM_DUAL.TXDATA_CH0_FS231
TCELL11:IMUX.IMUX.12GTM_DUAL.TXDATA_CH0_FS246
TCELL11:IMUX.IMUX.14GTM_DUAL.TXDATA_CH0_FS247
TCELL11:IMUX.IMUX.15GTM_DUAL.TXDATA_CH0_FS252
TCELL11:IMUX.IMUX.16GTM_DUAL.TXDATA_CH0_FS229
TCELL11:IMUX.IMUX.17GTM_DUAL.TXDATA_CH0_FS230
TCELL11:IMUX.IMUX.18GTM_DUAL.TXDATA_CH0_FS232
TCELL11:IMUX.IMUX.20GTM_DUAL.TXDATA_CH0_FS239
TCELL11:IMUX.IMUX.21GTM_DUAL.TXDATA_CH0_FS243
TCELL11:IMUX.IMUX.22GTM_DUAL.TXDATA_CH0_FS248
TCELL11:IMUX.IMUX.24GTM_DUAL.TXDATA_CH0_FS242
TCELL11:IMUX.IMUX.25GTM_DUAL.TXDATA_CH0_FS255
TCELL11:IMUX.IMUX.26GTM_DUAL.TXDATA_CH0_FS250
TCELL11:IMUX.IMUX.27GTM_DUAL.TXDATA_CH0_FS227
TCELL11:IMUX.IMUX.28GTM_DUAL.TXDATA_CH0_FS237
TCELL11:IMUX.IMUX.29GTM_DUAL.TXDATA_CH0_FS254
TCELL11:IMUX.IMUX.30GTM_DUAL.TXDATA_CH0_FS234
TCELL11:IMUX.IMUX.31GTM_DUAL.TXDATA_CH0_FS219
TCELL11:IMUX.IMUX.32GTM_DUAL.TXDATA_CH0_FS251
TCELL11:IMUX.IMUX.33GTM_DUAL.TXDATA_CH0_FS241
TCELL11:IMUX.IMUX.37GTM_DUAL.TXDATA_CH0_FS236
TCELL11:IMUX.IMUX.38GTM_DUAL.TXDATA_CH0_FS238
TCELL11:IMUX.IMUX.39GTM_DUAL.TXDATA_CH0_FS221
TCELL11:IMUX.IMUX.40GTM_DUAL.TXDATA_CH0_FS235
TCELL11:IMUX.IMUX.41GTM_DUAL.TXDATA_CH0_FS233
TCELL11:IMUX.IMUX.42GTM_DUAL.TXDATA_CH0_FS245
TCELL11:IMUX.IMUX.43GTM_DUAL.TXDATA_CH0_FS240
TCELL11:IMUX.IMUX.44GTM_DUAL.TXDATA_CH0_FS223
TCELL11:IMUX.IMUX.46GTM_DUAL.TXDATA_CH0_FS224
TCELL12:OUT.0GTM_DUAL.RXDATA_CH0_SF79
TCELL12:OUT.1GTM_DUAL.RXDATA_CH0_SF83
TCELL12:OUT.2GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF0
TCELL12:OUT.3GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF1
TCELL12:OUT.5GTM_DUAL.RXDATA_CH0_SF95
TCELL12:OUT.6GTM_DUAL.ST_RX_LN0_ERR_CNT_INC_SF0
TCELL12:OUT.7GTM_DUAL.RXDATA_CH0_SF93
TCELL12:OUT.8GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF2
TCELL12:OUT.9GTM_DUAL.RXDATA_CH0_SF81
TCELL12:OUT.10GTM_DUAL.RXDATA_CH0_SF86
TCELL12:OUT.11GTM_DUAL.RXDATA_CH0_SF92
TCELL12:OUT.12GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF3
TCELL12:OUT.13GTM_DUAL.RXDATA_CH0_SF80
TCELL12:OUT.15GTM_DUAL.RXDATA_CH0_SF89
TCELL12:OUT.16GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF4
TCELL12:OUT.17GTM_DUAL.RXDATA_CH0_SF91
TCELL12:OUT.18GTM_DUAL.RXDATA_CH0_SF84
TCELL12:OUT.19GTM_DUAL.RXDATA_CH0_SF85
TCELL12:OUT.20GTM_DUAL.RXDATA_CH0_SF82
TCELL12:OUT.21GTM_DUAL.RXDATA_CH0_SF90
TCELL12:OUT.22GTM_DUAL.RXDATA_CH0_SF88
TCELL12:OUT.23GTM_DUAL.ST_RX_LN0_FEC_LOCK_SF
TCELL12:OUT.24GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF5
TCELL12:OUT.25GTM_DUAL.ST_RX_LN0_ERR_CNT_INC_SF1
TCELL12:OUT.26GTM_DUAL.RXDATA_CH0_SF94
TCELL12:OUT.27GTM_DUAL.RXDATA_CH0_SF87
TCELL12:OUT.28GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF6
TCELL12:OUT.30GTM_DUAL.ST_RX_LN0_BIT_ERR_0TO1_INC_SF7
TCELL12:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS108
TCELL12:IMUX.IMUX.8GTM_DUAL.PMA_SCANIN_CH0_FS12
TCELL12:IMUX.IMUX.12GTM_DUAL.PMA_SCANIN_CH0_FS16
TCELL12:IMUX.IMUX.16GTM_DUAL.PMA_RSVDIN_CH0_FS3
TCELL12:IMUX.IMUX.18GTM_DUAL.PMA_SCANIN_CH0_FS13
TCELL12:IMUX.IMUX.21GTM_DUAL.PMA_SCANIN_CH0_FS14
TCELL12:IMUX.IMUX.22GTM_DUAL.PMA_RSVDIN_CH0_FS2
TCELL12:IMUX.IMUX.23GTM_DUAL.FEC_SCANIN_FS109
TCELL12:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS110
TCELL12:IMUX.IMUX.31GTM_DUAL.FEC_SCANIN_FS111
TCELL12:IMUX.IMUX.35GTM_DUAL.FEC_SCANIN_FS112
TCELL12:IMUX.IMUX.39GTM_DUAL.FEC_SCANIN_FS113
TCELL12:IMUX.IMUX.40GTM_DUAL.PMA_SCANIN_CH0_FS17
TCELL12:IMUX.IMUX.44GTM_DUAL.FEC_SCANIN_FS114
TCELL12:IMUX.IMUX.46GTM_DUAL.PMA_SCANIN_CH0_FS15
TCELL13:OUT.0GTM_DUAL.ST_RX_LN0_DELAY_SF0
TCELL13:OUT.1GTM_DUAL.ST_RX_LN0_DELAY_SF1
TCELL13:OUT.2GTM_DUAL.RXDATA_CH0_SF103
TCELL13:OUT.3GTM_DUAL.RXDATA_CH0_SF102
TCELL13:OUT.4GTM_DUAL.ST_RX_LN0_DELAY_SF2
TCELL13:OUT.5GTM_DUAL.RXDATA_CH0_SF104
TCELL13:OUT.6GTM_DUAL.RXDATA_CH0_SF106
TCELL13:OUT.7GTM_DUAL.ST_RX_LN0_DELAY_SF3
TCELL13:OUT.9GTM_DUAL.RXDATA_CH0_SF107
TCELL13:OUT.10GTM_DUAL.RXDATA_CH0_SF105
TCELL13:OUT.11GTM_DUAL.RXDATA_CH0_SF100
TCELL13:OUT.12GTM_DUAL.ST_RX_LN0_DELAY_SF4
TCELL13:OUT.13GTM_DUAL.ST_RX_LN0_DELAY_SF5
TCELL13:OUT.14GTM_DUAL.ST_RX_LN0_DELAY_SF6
TCELL13:OUT.15GTM_DUAL.ST_RX_LN0_DELAY_SF7
TCELL13:OUT.16GTM_DUAL.RXDATA_CH0_SF99
TCELL13:OUT.18GTM_DUAL.RXDATA_CH0_SF98
TCELL13:OUT.19GTM_DUAL.ST_RX_LN0_DELAY_SF8
TCELL13:OUT.20GTM_DUAL.ST_RX_LN0_DELAY_SF9
TCELL13:OUT.21GTM_DUAL.RXDATA_CH0_SF101
TCELL13:OUT.22GTM_DUAL.ST_RX_LN0_DELAY_SF10
TCELL13:OUT.23GTM_DUAL.ST_RX_LN0_DELAY_SF11
TCELL13:OUT.25GTM_DUAL.ST_RX_LN0_DELAY_SF12
TCELL13:OUT.26GTM_DUAL.ST_RX_LN0_DELAY_SF13
TCELL13:OUT.27GTM_DUAL.ST_RX_LN0_DELAY_SF14
TCELL13:OUT.28GTM_DUAL.RXDATA_CH0_SF108
TCELL13:OUT.30GTM_DUAL.RXDATA_CH0_SF96
TCELL13:OUT.31GTM_DUAL.RXDATA_CH0_SF97
TCELL13:IMUX.IMUX.5GTM_DUAL.PCS_RSVDIN_CH0_FS4
TCELL13:IMUX.IMUX.8GTM_DUAL.AXIS_STREAMEN_CH0_FS
TCELL13:IMUX.IMUX.11GTM_DUAL.PMA_SCANIN_CH0_FS20
TCELL13:IMUX.IMUX.16GTM_DUAL.RX_PMA_RESETMASK_CH0_FS2
TCELL13:IMUX.IMUX.17GTM_DUAL.PCS_RSVDIN_CH0_FS0
TCELL13:IMUX.IMUX.25GTM_DUAL.PCS_RSVDIN_CH0_FS6
TCELL13:IMUX.IMUX.27GTM_DUAL.RXPRBSPTN_CH0_FS0
TCELL13:IMUX.IMUX.28GTM_DUAL.PMA_SCANIN_CH0_FS19
TCELL13:IMUX.IMUX.29GTM_DUAL.PCS_RSVDIN_CH0_FS3
TCELL13:IMUX.IMUX.33GTM_DUAL.PCS_RSVDIN_CH0_FS5
TCELL13:IMUX.IMUX.37GTM_DUAL.PCS_RSVDIN_CH0_FS2
TCELL13:IMUX.IMUX.38GTM_DUAL.PMA_SCANIN_CH0_FS18
TCELL13:IMUX.IMUX.40GTM_DUAL.PCS_RSVDIN_CH0_FS1
TCELL13:IMUX.IMUX.43GTM_DUAL.RX_PMA_RESETMASK_CH0_FS1
TCELL13:IMUX.IMUX.44GTM_DUAL.RX_PMA_RESETMASK_CH0_FS0
TCELL14:OUT.0GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF0
TCELL14:OUT.1GTM_DUAL.RXDATA_CH0_SF115
TCELL14:OUT.2GTM_DUAL.RXDATA_CH0_SF122
TCELL14:OUT.3GTM_DUAL.RXDATA_CH0_SF117
TCELL14:OUT.4GTM_DUAL.RXDATA_CH0_SF125
TCELL14:OUT.5GTM_DUAL.RXDATA_CH0_SF112
TCELL14:OUT.6GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF1
TCELL14:OUT.7GTM_DUAL.RXDATA_CH0_SF121
TCELL14:OUT.9GTM_DUAL.ST_RX_LN0_ERR_CNT_INC_SF2
TCELL14:OUT.10GTM_DUAL.RXDATA_CH0_SF116
TCELL14:OUT.11GTM_DUAL.RXDATA_CH0_SF114
TCELL14:OUT.12GTM_DUAL.RXDATA_CH0_SF110
TCELL14:OUT.13GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF2
TCELL14:OUT.14GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF3
TCELL14:OUT.15GTM_DUAL.RXDATA_CH0_SF111
TCELL14:OUT.17GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF4
TCELL14:OUT.18GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF5
TCELL14:OUT.20GTM_DUAL.ST_RX_LN0_ERR_CNT_INC_SF3
TCELL14:OUT.21GTM_DUAL.RXDATA_CH0_SF124
TCELL14:OUT.22GTM_DUAL.RXDATA_CH0_SF120
TCELL14:OUT.23GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF6
TCELL14:OUT.24GTM_DUAL.PMA_RSVDOUT_CH0_SF8
TCELL14:OUT.25GTM_DUAL.ST_RX_LN0_BIT_ERR_1TO0_INC_SF7
TCELL14:OUT.26GTM_DUAL.RXDATA_CH0_SF109
TCELL14:OUT.27GTM_DUAL.RXDATA_CH0_SF118
TCELL14:OUT.28GTM_DUAL.RXDATA_CH0_SF119
TCELL14:OUT.29GTM_DUAL.RXDATA_CH0_SF113
TCELL14:OUT.30GTM_DUAL.RXDATA_CH0_SF123
TCELL14:IMUX.CTRL.3GTM_DUAL.PCS_SCANRSTB_CH0_FS
TCELL14:IMUX.IMUX.1GTM_DUAL.PCS_RSVDIN_CH0_FS7
TCELL14:IMUX.IMUX.3GTM_DUAL.FEC_SCANIN_FS115
TCELL14:IMUX.IMUX.4GTM_DUAL.PMA_RSVDIN_CH0_FS4
TCELL14:IMUX.IMUX.9GTM_DUAL.PMA_SCANIN_CH0_FS23
TCELL14:IMUX.IMUX.12GTM_DUAL.BSR_SERIAL_CH0_FS
TCELL14:IMUX.IMUX.19GTM_DUAL.PMA_RSVDIN_CH0_FS5
TCELL14:IMUX.IMUX.20GTM_DUAL.RX_RESETMODE_CH0_FS0
TCELL14:IMUX.IMUX.23GTM_DUAL.RXUSRRDY_CH0_FS
TCELL14:IMUX.IMUX.27GTM_DUAL.PCS_SCANIN_CH0_FS0
TCELL14:IMUX.IMUX.30GTM_DUAL.PCS_SCANIN_CH0_FS1
TCELL14:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS116
TCELL14:IMUX.IMUX.34GTM_DUAL.PMA_SCANIN_CH0_FS22
TCELL14:IMUX.IMUX.39GTM_DUAL.RX_PMA_RESETMASK_CH0_FS3
TCELL14:IMUX.IMUX.43GTM_DUAL.FEC_SCANIN_FS117
TCELL14:IMUX.IMUX.45GTM_DUAL.PMA_SCANIN_CH0_FS21
TCELL15:OUT.0GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF0
TCELL15:OUT.1GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF1
TCELL15:OUT.2GTM_DUAL.RXDATA_CH0_SF142
TCELL15:OUT.3GTM_DUAL.ST_RX_LN1_ERR_CNT_INC_SF0
TCELL15:OUT.4GTM_DUAL.RXDATA_CH0_SF127
TCELL15:OUT.5GTM_DUAL.RXDATA_CH0_SF141
TCELL15:OUT.7GTM_DUAL.RXDATA_CH0_SF139
TCELL15:OUT.8GTM_DUAL.RXDATA_CH0_SF131
TCELL15:OUT.9GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF2
TCELL15:OUT.10GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF3
TCELL15:OUT.11GTM_DUAL.RXDATA_CH0_SF137
TCELL15:OUT.13GTM_DUAL.RXDATA_CH0_SF132
TCELL15:OUT.14GTM_DUAL.RXDATA_CH0_SF128
TCELL15:OUT.15GTM_DUAL.RXDATA_CH0_SF129
TCELL15:OUT.16GTM_DUAL.ST_RX_LN1_ERR_CNT_INC_SF1
TCELL15:OUT.17GTM_DUAL.RXDATA_CH0_SF130
TCELL15:OUT.18GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF4
TCELL15:OUT.19GTM_DUAL.RXDATA_CH0_SF138
TCELL15:OUT.20GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF5
TCELL15:OUT.21GTM_DUAL.RXDATA_CH0_SF135
TCELL15:OUT.23GTM_DUAL.RXDATA_CH0_SF134
TCELL15:OUT.24GTM_DUAL.RXDATA_CH0_SF133
TCELL15:OUT.25GTM_DUAL.RXDATA_CH0_SF126
TCELL15:OUT.26GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF6
TCELL15:OUT.27GTM_DUAL.RXDATA_CH0_SF136
TCELL15:OUT.28GTM_DUAL.ST_RX_LN1_ERR_CNT_INC_SF2
TCELL15:OUT.29GTM_DUAL.ST_RX_LN1_BIT_ERR_0TO1_INC_SF7
TCELL15:OUT.30GTM_DUAL.RXDATA_CH0_SF140
TCELL15:IMUX.CTRL.3GTM_DUAL.RXUSRCLK_CH0_FS
TCELL15:IMUX.CTRL.4GTM_DUAL.DCLK_FS
TCELL15:IMUX.IMUX.1GTM_DUAL.RX_PMA_RESETMASK_CH0_FS4
TCELL15:IMUX.IMUX.6GTM_DUAL.PCS_SCANIN_CH0_FS2
TCELL15:IMUX.IMUX.7GTM_DUAL.PCS_SCANIN_CH0_FS5
TCELL15:IMUX.IMUX.13GTM_DUAL.PMA_RSVDIN_CH0_FS8
TCELL15:IMUX.IMUX.14GTM_DUAL.PCS_RSVDIN_CH0_FS8
TCELL15:IMUX.IMUX.17GTM_DUAL.RX_PMA_RESETMASK_CH0_FS5
TCELL15:IMUX.IMUX.20GTM_DUAL.DI_FS0
TCELL15:IMUX.IMUX.26GTM_DUAL.PCS_SCANIN_CH0_FS3
TCELL15:IMUX.IMUX.29GTM_DUAL.DI_FS1
TCELL15:IMUX.IMUX.32GTM_DUAL.PCS_SCANIN_CH0_FS7
TCELL15:IMUX.IMUX.33GTM_DUAL.PMA_RSVDIN_CH0_FS7
TCELL15:IMUX.IMUX.34GTM_DUAL.RX_PMA_RESETMASK_CH0_FS6
TCELL15:IMUX.IMUX.37GTM_DUAL.PCS_SCANIN_CH0_FS4
TCELL15:IMUX.IMUX.39GTM_DUAL.PCS_SCANIN_CH0_FS6
TCELL15:IMUX.IMUX.40GTM_DUAL.DI_FS2
TCELL15:IMUX.IMUX.45GTM_DUAL.PMA_RSVDIN_CH0_FS9
TCELL15:IMUX.IMUX.47GTM_DUAL.PMA_RSVDIN_CH0_FS6
TCELL16:OUT.0GTM_DUAL.ST_RX_LN1_DELAY_SF0
TCELL16:OUT.1GTM_DUAL.ST_RX_LN1_DELAY_SF1
TCELL16:OUT.2GTM_DUAL.RXDATA_CH0_SF149
TCELL16:OUT.3GTM_DUAL.ST_RX_LN1_DELAY_SF2
TCELL16:OUT.4GTM_DUAL.RXDATA_CH0_SF148
TCELL16:OUT.5GTM_DUAL.ST_RX_LN1_DELAY_SF3
TCELL16:OUT.6GTM_DUAL.RXDATA_CH0_SF151
TCELL16:OUT.7GTM_DUAL.RXDATA_CH0_SF153
TCELL16:OUT.9GTM_DUAL.RXDATA_CH0_SF152
TCELL16:OUT.10GTM_DUAL.RXDATA_CH0_SF146
TCELL16:OUT.11GTM_DUAL.RXDATA_CH0_SF145
TCELL16:OUT.12GTM_DUAL.ST_RX_LN1_DELAY_SF4
TCELL16:OUT.13GTM_DUAL.ST_RX_LN1_DELAY_SF5
TCELL16:OUT.14GTM_DUAL.ST_RX_LN1_DELAY_SF6
TCELL16:OUT.15GTM_DUAL.RXDATA_CH0_SF143
TCELL16:OUT.16GTM_DUAL.RXDATA_CH0_SF147
TCELL16:OUT.17GTM_DUAL.ST_RX_LN1_DELAY_SF7
TCELL16:OUT.19GTM_DUAL.ST_RX_LN1_ERR_CNT_INC_SF3
TCELL16:OUT.20GTM_DUAL.ST_RX_LN1_DELAY_SF8
TCELL16:OUT.21GTM_DUAL.ST_RX_LN1_DELAY_SF9
TCELL16:OUT.22GTM_DUAL.ST_RX_LN1_DELAY_SF10
TCELL16:OUT.23GTM_DUAL.ST_RX_LN1_DELAY_SF11
TCELL16:OUT.25GTM_DUAL.ST_RX_LN1_DELAY_SF12
TCELL16:OUT.26GTM_DUAL.ST_RX_LN1_DELAY_SF13
TCELL16:OUT.27GTM_DUAL.ST_RX_LN1_DELAY_SF14
TCELL16:OUT.28GTM_DUAL.RXDATA_CH0_SF154
TCELL16:OUT.29GTM_DUAL.RXDATA_CH0_SF150
TCELL16:OUT.31GTM_DUAL.RXDATA_CH0_SF144
TCELL16:IMUX.IMUX.0GTM_DUAL.PCS_RSVDIN_CH0_FS10
TCELL16:IMUX.IMUX.4GTM_DUAL.DI_FS3
TCELL16:IMUX.IMUX.9GTM_DUAL.RX_RESETMODE_CH0_FS1
TCELL16:IMUX.IMUX.13GTM_DUAL.PCS_SCANIN_CH0_FS8
TCELL16:IMUX.IMUX.15GTM_DUAL.PCS_SCANIN_CH0_FS10
TCELL16:IMUX.IMUX.18GTM_DUAL.RXPOLARITY_CH0_FS
TCELL16:IMUX.IMUX.19GTM_DUAL.PCS_SCANIN_CH0_FS9
TCELL16:IMUX.IMUX.21GTM_DUAL.PCS_SCANIN_CH0_FS11
TCELL16:IMUX.IMUX.25GTM_DUAL.PCS_RSVDIN_CH0_FS9
TCELL16:IMUX.IMUX.29GTM_DUAL.PCS_RSVDIN_CH0_FS12
TCELL16:IMUX.IMUX.30GTM_DUAL.RXQPRBS_ENA_CH0_FS
TCELL16:IMUX.IMUX.32GTM_DUAL.RX_FECRESET_CH0_FS
TCELL16:IMUX.IMUX.37GTM_DUAL.PCS_RSVDIN_CH0_FS11
TCELL16:IMUX.IMUX.39GTM_DUAL.DI_FS4
TCELL16:IMUX.IMUX.43GTM_DUAL.LOOPBACK_CH0_FS0
TCELL17:OUT.0GTM_DUAL.RXDATA_CH0_SF168
TCELL17:OUT.1GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF0
TCELL17:OUT.2GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF1
TCELL17:OUT.4GTM_DUAL.RXDATA_CH0_SF172
TCELL17:OUT.5GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF2
TCELL17:OUT.6GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF3
TCELL17:OUT.7GTM_DUAL.RXDATA_CH0_SF170
TCELL17:OUT.8GTM_DUAL.RXDATA_CH0_SF165
TCELL17:OUT.9GTM_DUAL.RXDATA_CH0_SF167
TCELL17:OUT.11GTM_DUAL.RXDATA_CH0_SF162
TCELL17:OUT.12GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF4
TCELL17:OUT.13GTM_DUAL.RXDATA_CH0_SF159
TCELL17:OUT.14GTM_DUAL.RXDATA_CH0_SF157
TCELL17:OUT.15GTM_DUAL.RXDATA_CH0_SF163
TCELL17:OUT.16GTM_DUAL.RXDATA_CH0_SF169
TCELL17:OUT.17GTM_DUAL.ST_RX_LN1_FEC_LOCK_SF
TCELL17:OUT.18GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF5
TCELL17:OUT.19GTM_DUAL.RXDATA_CH0_SF160
TCELL17:OUT.20GTM_DUAL.RXDATA_CH0_SF164
TCELL17:OUT.21GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF6
TCELL17:OUT.23GTM_DUAL.ST_RX_LN1_BIT_ERR_1TO0_INC_SF7
TCELL17:OUT.24GTM_DUAL.RXDATA_CH0_SF155
TCELL17:OUT.25GTM_DUAL.RXDATA_CH0_SF158
TCELL17:OUT.26GTM_DUAL.RXDATA_CH0_SF161
TCELL17:OUT.28GTM_DUAL.RXDATA_CH0_SF156
TCELL17:OUT.29GTM_DUAL.RXDATA_CH0_SF173
TCELL17:OUT.30GTM_DUAL.RXDATA_CH0_SF171
TCELL17:OUT.31GTM_DUAL.RXDATA_CH0_SF166
TCELL17:IMUX.CTRL.0GTM_DUAL.RXUSRCLK2_CH0_FS
TCELL17:IMUX.IMUX.2GTM_DUAL.AXIS_TREADY_CH0_FS
TCELL17:IMUX.IMUX.5GTM_DUAL.RX_PCS_SEQ_ADVANCE_CH0_FS
TCELL17:IMUX.IMUX.7GTM_DUAL.PCS_SCANCLK_CH0_FS1
TCELL17:IMUX.IMUX.8GTM_DUAL.PCS_SCANENB_CH0_FS
TCELL17:IMUX.IMUX.9GTM_DUAL.RX_CDRPHRESET_CH0_FS
TCELL17:IMUX.IMUX.10GTM_DUAL.CDR_INCPCTRL_CH0_FS
TCELL17:IMUX.IMUX.12GTM_DUAL.PMA_SCANIN_CH0_FS24
TCELL17:IMUX.IMUX.16GTM_DUAL.CDR_EXHOLD_CH0_FS
TCELL17:IMUX.IMUX.21GTM_DUAL.DADDR_FS0
TCELL17:IMUX.IMUX.29GTM_DUAL.PCS_RSVDIN_CH0_FS13
TCELL17:IMUX.IMUX.31GTM_DUAL.DADDR_FS1
TCELL17:IMUX.IMUX.38GTM_DUAL.PCS_SCANCLK_CH0_FS0
TCELL17:IMUX.IMUX.42GTM_DUAL.DADDR_FS2
TCELL17:IMUX.IMUX.43GTM_DUAL.RX_USRSTOP_CH0_FS
TCELL17:IMUX.IMUX.46GTM_DUAL.GTTXRESET_CH0_FS
TCELL18:OUT.1GTM_DUAL.RXDATA_CH0_SF184
TCELL18:OUT.2GTM_DUAL.RXDATA_CH0_SF191
TCELL18:OUT.3GTM_DUAL.RXDATA_CH0_SF200
TCELL18:OUT.5GTM_DUAL.RXDATA_CH0_SF188
TCELL18:OUT.6GTM_DUAL.RXDATA_CH0_SF186
TCELL18:OUT.7GTM_DUAL.RXDATA_CH0_SF176
TCELL18:OUT.8GTM_DUAL.RXDATA_CH0_SF196
TCELL18:OUT.9GTM_DUAL.RXDATA_CH0_SF177
TCELL18:OUT.10GTM_DUAL.RXDATA_CH0_SF183
TCELL18:OUT.11GTM_DUAL.RXDATA_CH0_SF199
TCELL18:OUT.12GTM_DUAL.RXDATA_CH0_SF194
TCELL18:OUT.13GTM_DUAL.RXDATA_CH0_SF189
TCELL18:OUT.14GTM_DUAL.RXDATA_CH0_SF175
TCELL18:OUT.15GTM_DUAL.RXDATA_CH0_SF174
TCELL18:OUT.16GTM_DUAL.RXDATA_CH0_SF182
TCELL18:OUT.17GTM_DUAL.RXDATA_CH0_SF192
TCELL18:OUT.18GTM_DUAL.RXDATA_CH0_SF197
TCELL18:OUT.19GTM_DUAL.RXDATA_CH0_SF187
TCELL18:OUT.20GTM_DUAL.RXDATA_CH0_SF178
TCELL18:OUT.21GTM_DUAL.RXDATA_CH0_SF180
TCELL18:OUT.22GTM_DUAL.RXDATA_CH0_SF185
TCELL18:OUT.23GTM_DUAL.RXDATA_CH0_SF198
TCELL18:OUT.24GTM_DUAL.RXDATA_CH0_SF179
TCELL18:OUT.26GTM_DUAL.RXDATA_CH0_SF181
TCELL18:OUT.27GTM_DUAL.RXDATA_CH0_SF190
TCELL18:OUT.28GTM_DUAL.RXDATA_CH0_SF201
TCELL18:OUT.29GTM_DUAL.RXDATA_CH0_SF193
TCELL18:OUT.30GTM_DUAL.RXDATA_CH0_SF195
TCELL18:IMUX.IMUX.6GTM_DUAL.PMA_SCANCLK_CH0_FS2
TCELL18:IMUX.IMUX.8GTM_DUAL.DRSTB_FS
TCELL18:IMUX.IMUX.9GTM_DUAL.DADDR_FS6
TCELL18:IMUX.IMUX.13GTM_DUAL.PMA_RSVDIN_CH0_FS11
TCELL18:IMUX.IMUX.17GTM_DUAL.LOOPBACK_CH0_FS1
TCELL18:IMUX.IMUX.18GTM_DUAL.DADDR_FS3
TCELL18:IMUX.IMUX.21GTM_DUAL.DEN_FS
TCELL18:IMUX.IMUX.23GTM_DUAL.DADDR_FS4
TCELL18:IMUX.IMUX.24GTM_DUAL.PMA_SCANCLK_CH0_FS3
TCELL18:IMUX.IMUX.29GTM_DUAL.DADDR_FS5
TCELL18:IMUX.IMUX.38GTM_DUAL.DADDR_FS7
TCELL18:IMUX.IMUX.40GTM_DUAL.RXPRBSCNTRST_CH0_FS
TCELL18:IMUX.IMUX.42GTM_DUAL.DWE_FS
TCELL18:IMUX.IMUX.44GTM_DUAL.DADDR_FS8
TCELL18:IMUX.IMUX.45GTM_DUAL.PMA_RSVDIN_CH0_FS10
TCELL19:OUT.0GTM_DUAL.DRPDO_SF0
TCELL19:OUT.1GTM_DUAL.DRPDO_SF1
TCELL19:OUT.2GTM_DUAL.RXDATA_START_CH0_SF
TCELL19:OUT.3GTM_DUAL.DRPDO_SF2
TCELL19:OUT.5GTM_DUAL.DRPDO_SF3
TCELL19:OUT.6GTM_DUAL.DRPDO_SF4
TCELL19:OUT.7GTM_DUAL.DRPDO_SF5
TCELL19:OUT.9GTM_DUAL.DMONOUT_CH0_SF26
TCELL19:OUT.10GTM_DUAL.PMA_SCANOUT_CH0_SF10
TCELL19:OUT.11GTM_DUAL.DRPDO_SF6
TCELL19:OUT.12GTM_DUAL.PMA_RSVDOUT_CH0_SF9
TCELL19:OUT.13GTM_DUAL.DRPDO_SF7
TCELL19:OUT.15GTM_DUAL.DRPDO_SF8
TCELL19:OUT.16GTM_DUAL.DMONOUT_CH0_SF27
TCELL19:OUT.17GTM_DUAL.DRPDO_SF9
TCELL19:OUT.18GTM_DUAL.DRPDO_SF10
TCELL19:OUT.19GTM_DUAL.DMONOUT_CH0_SF25
TCELL19:OUT.20GTM_DUAL.RXDATA_IS_AM_CH0_SF
TCELL19:OUT.21GTM_DUAL.RXPROGDIVRESETDONE_CH0_SF
TCELL19:OUT.22GTM_DUAL.RXDATA_CH0_SF202
TCELL19:OUT.23GTM_DUAL.DRDY_SF
TCELL19:OUT.24GTM_DUAL.AXIS_TLAST_CH0_SF
TCELL19:OUT.25GTM_DUAL.DRPDO_SF11
TCELL19:OUT.26GTM_DUAL.DRPDO_SF12
TCELL19:OUT.27GTM_DUAL.DRPDO_SF13
TCELL19:OUT.29GTM_DUAL.DRPDO_SF14
TCELL19:OUT.30GTM_DUAL.DRPDO_SF15
TCELL19:IMUX.IMUX.2GTM_DUAL.DI_FS6
TCELL19:IMUX.IMUX.5GTM_DUAL.PMA_SCANCLK_CH0_FS4
TCELL19:IMUX.IMUX.7GTM_DUAL.DI_FS9
TCELL19:IMUX.IMUX.12GTM_DUAL.DI_FS13
TCELL19:IMUX.IMUX.15GTM_DUAL.DI_FS15
TCELL19:IMUX.IMUX.16GTM_DUAL.DI_FS5
TCELL19:IMUX.IMUX.18GTM_DUAL.PCS_RSVDIN_CH0_FS14
TCELL19:IMUX.IMUX.19GTM_DUAL.DMONFIFORESET_CH0_FS
TCELL19:IMUX.IMUX.22GTM_DUAL.DI_FS7
TCELL19:IMUX.IMUX.24GTM_DUAL.PMA_SCANCLK_CH0_FS5
TCELL19:IMUX.IMUX.25GTM_DUAL.DADDR_FS9
TCELL19:IMUX.IMUX.27GTM_DUAL.DI_FS8
TCELL19:IMUX.IMUX.32GTM_DUAL.DI_FS10
TCELL19:IMUX.IMUX.34GTM_DUAL.DI_FS11
TCELL19:IMUX.IMUX.37GTM_DUAL.DI_FS12
TCELL19:IMUX.IMUX.40GTM_DUAL.DADDR_FS10
TCELL19:IMUX.IMUX.43GTM_DUAL.DI_FS14
TCELL20:OUT.0GTM_DUAL.RXDATA_CH0_SF208
TCELL20:OUT.2GTM_DUAL.PMA_SCANOUT_CH0_SF15
TCELL20:OUT.4GTM_DUAL.RXDATA_CH0_SF204
TCELL20:OUT.6GTM_DUAL.PMA_SCANOUT_CH0_SF13
TCELL20:OUT.7GTM_DUAL.PMA_SCANOUT_CH0_SF12
TCELL20:OUT.15GTM_DUAL.RXDATA_CH0_SF203
TCELL20:OUT.17GTM_DUAL.PCS_RSVDOUT_CH0_SF9
TCELL20:OUT.18GTM_DUAL.RXDATA_CH0_SF207
TCELL20:OUT.19GTM_DUAL.RXDATA_CH0_SF206
TCELL20:OUT.20GTM_DUAL.RXDATA_CH0_SF205
TCELL20:OUT.24GTM_DUAL.RXDATA_CH0_SF209
TCELL20:OUT.26GTM_DUAL.PMA_SCANOUT_CH0_SF11
TCELL20:OUT.28GTM_DUAL.PMA_SCANOUT_CH0_SF14
TCELL20:IMUX.IMUX.0GTM_DUAL.PMA_RSVDIN_CH0_FS13
TCELL20:IMUX.IMUX.3GTM_DUAL.PMA_RSVDIN_CH0_FS12
TCELL20:IMUX.IMUX.11GTM_DUAL.PMA_SCANCLK_CH0_FS6
TCELL20:IMUX.IMUX.15GTM_DUAL.RX_USRSTART_CH0_FS
TCELL20:IMUX.IMUX.18GTM_DUAL.PMA_SCANRSTEN_CH0_FS
TCELL20:IMUX.IMUX.19GTM_DUAL.PMA_SCANMODEB_CH0_FS
TCELL20:IMUX.IMUX.25GTM_DUAL.RXOUTCKCTL_CH0_FS2
TCELL20:IMUX.IMUX.26GTM_DUAL.PCS_SCANMODEB_CH0_FS
TCELL20:IMUX.IMUX.28GTM_DUAL.PMA_SCANCLK_CH0_FS7
TCELL20:IMUX.IMUX.29GTM_DUAL.RX_ADC_CLKGENRESET_CH0_FS
TCELL20:IMUX.IMUX.31GTM_DUAL.RX_PROGDIVRESET_CH0_FS
TCELL20:IMUX.IMUX.32GTM_DUAL.RXOUTCKCTL_CH0_FS1
TCELL20:IMUX.IMUX.36GTM_DUAL.PMA_RSVDIN_CH0_FS14
TCELL20:IMUX.IMUX.39GTM_DUAL.RX_DFERESET_CH0_FS
TCELL20:IMUX.IMUX.44GTM_DUAL.RXOUTCKCTL_CH0_FS0
TCELL21:OUT.1GTM_DUAL.RXDATA_CH0_SF217
TCELL21:OUT.2GTM_DUAL.RXDATA_FLAGS_CH0_SF2
TCELL21:OUT.4GTM_DUAL.RXDATA_CH0_SF229
TCELL21:OUT.5GTM_DUAL.RXDATA_CH0_SF219
TCELL21:OUT.6GTM_DUAL.RXDATA_CH0_SF228
TCELL21:OUT.7GTM_DUAL.RXDATA_CH0_SF227
TCELL21:OUT.8GTM_DUAL.RXDATA_CH0_SF226
TCELL21:OUT.10GTM_DUAL.RXDATA_CH0_SF212
TCELL21:OUT.12GTM_DUAL.RXDATA_CH0_SF216
TCELL21:OUT.13GTM_DUAL.DMONOUT_CH0_SF28
TCELL21:OUT.14GTM_DUAL.RXDATA_CH0_SF210
TCELL21:OUT.15GTM_DUAL.RXDATA_CH0_SF211
TCELL21:OUT.17GTM_DUAL.RXDATA_CH0_SF218
TCELL21:OUT.18GTM_DUAL.RXDATA_FLAGS_CH0_SF1
TCELL21:OUT.19GTM_DUAL.RXDATA_CH0_SF222
TCELL21:OUT.20GTM_DUAL.RXDATA_CH0_SF214
TCELL21:OUT.21GTM_DUAL.RXDATA_CH0_SF224
TCELL21:OUT.22GTM_DUAL.PMA_RSVDOUT_CH0_SF10
TCELL21:OUT.25GTM_DUAL.RXDATA_CH0_SF213
TCELL21:OUT.27GTM_DUAL.RXDATA_CH0_SF215
TCELL21:OUT.28GTM_DUAL.RXDATA_CH0_SF220
TCELL21:OUT.29GTM_DUAL.RXDATA_CH0_SF225
TCELL21:OUT.30GTM_DUAL.RXDATA_CH0_SF223
TCELL21:OUT.31GTM_DUAL.RXDATA_CH0_SF221
TCELL21:IMUX.IMUX.9GTM_DUAL.RX_PCS_RESETMASK_CH0_FS2
TCELL21:IMUX.IMUX.10GTM_DUAL.RX_DSPRESET_CH0_FS
TCELL21:IMUX.IMUX.13GTM_DUAL.RX_ADAPTRESET_CH0_FS
TCELL21:IMUX.IMUX.14GTM_DUAL.RX_PMARESET_CH0_FS
TCELL21:IMUX.IMUX.15GTM_DUAL.RXPRBSPTN_CH0_FS1
TCELL21:IMUX.IMUX.16GTM_DUAL.PCS_SCANIN_CH0_FS12
TCELL21:IMUX.IMUX.19GTM_DUAL.CDR_FREQOS_CH0_FS
TCELL21:IMUX.IMUX.25GTM_DUAL.RX_PCS_RESETMASK_CH0_FS0
TCELL21:IMUX.IMUX.26GTM_DUAL.RX_PMA_RESETMASK_CH0_FS7
TCELL21:IMUX.IMUX.29GTM_DUAL.RX_PCSRESET_CH0_FS
TCELL21:IMUX.IMUX.32GTM_DUAL.RXPRBSPTN_CH0_FS2
TCELL21:IMUX.IMUX.33GTM_DUAL.LOOPBACK_CH0_FS2
TCELL21:IMUX.IMUX.37GTM_DUAL.RX_PCS_RESETMASK_CH0_FS1
TCELL21:IMUX.IMUX.38GTM_DUAL.RESETOVRD_CH0_FS
TCELL21:IMUX.IMUX.42GTM_DUAL.GTRXRESET_CH0_FS
TCELL22:OUT.0GTM_DUAL.RXDATA_CH0_SF244
TCELL22:OUT.1GTM_DUAL.RXDATA_CH0_SF233
TCELL22:OUT.2GTM_DUAL.RXDATA_CH0_SF251
TCELL22:OUT.3GTM_DUAL.RXDATA_CH0_SF232
TCELL22:OUT.5GTM_DUAL.RXDATA_CH0_SF242
TCELL22:OUT.6GTM_DUAL.RXDATA_CH0_SF237
TCELL22:OUT.7GTM_DUAL.RXDATA_CH0_SF230
TCELL22:OUT.8GTM_DUAL.RXDATA_CH0_SF235
TCELL22:OUT.9GTM_DUAL.RXDATA_CH0_SF239
TCELL22:OUT.10GTM_DUAL.RXDATA_CH0_SF243
TCELL22:OUT.11GTM_DUAL.RXDATA_CH0_SF231
TCELL22:OUT.12GTM_DUAL.RXDATA_CH0_SF255
TCELL22:OUT.13GTM_DUAL.RXDATA_CH0_SF250
TCELL22:OUT.14GTM_DUAL.RXDATA_CH0_SF247
TCELL22:OUT.15GTM_DUAL.RXDATA_CH0_SF234
TCELL22:OUT.16GTM_DUAL.RXDATA_CH0_SF240
TCELL22:OUT.18GTM_DUAL.RXDATA_CH0_SF252
TCELL22:OUT.20GTM_DUAL.RXDATA_CH0_SF249
TCELL22:OUT.22GTM_DUAL.RXDATA_CH0_SF254
TCELL22:OUT.23GTM_DUAL.RXDATA_CH0_SF253
TCELL22:OUT.24GTM_DUAL.RXDATA_CH0_SF241
TCELL22:OUT.25GTM_DUAL.RXDATA_CH0_SF245
TCELL22:OUT.26GTM_DUAL.RXDATA_CH0_SF246
TCELL22:OUT.27GTM_DUAL.RXDATA_CH0_SF236
TCELL22:OUT.28GTM_DUAL.RXDATA_CH0_SF248
TCELL22:OUT.29GTM_DUAL.PMA_SCANOUT_CH0_SF16
TCELL22:OUT.30GTM_DUAL.RXDATA_FLAGS_CH0_SF3
TCELL22:OUT.31GTM_DUAL.RXDATA_CH0_SF238
TCELL22:IMUX.IMUX.0GTM_DUAL.CFGRESET_CH0_FS
TCELL22:IMUX.IMUX.2GTM_DUAL.PCS_SCANIN_CH0_FS13
TCELL22:IMUX.IMUX.3GTM_DUAL.RXEQTRAINING_CH0_FS
TCELL22:IMUX.IMUX.5GTM_DUAL.PCS_SCANIN_CH0_FS14
TCELL22:IMUX.IMUX.7GTM_DUAL.PCS_RSVDIN_CH0_FS15
TCELL22:IMUX.IMUX.12GTM_DUAL.DMONCLK_CH0_FS
TCELL22:IMUX.IMUX.17GTM_DUAL.PCS_SCANRSTEN_CH0_FS
TCELL22:IMUX.IMUX.18GTM_DUAL.PMA_SCANENB_CH0_FS
TCELL22:IMUX.IMUX.21GTM_DUAL.RX_ISCANRESET_CH0_FS
TCELL22:IMUX.IMUX.23GTM_DUAL.RX_PCS_RESETMASK_CH0_FS3
TCELL22:IMUX.IMUX.24GTM_DUAL.CDR_OVWREN_CH0_FS
TCELL22:IMUX.IMUX.27GTM_DUAL.RX_ADC_CALRESET_CH0_FS
TCELL22:IMUX.IMUX.31GTM_DUAL.RXPRBS_CNT_STOP_CH0_FS
TCELL22:IMUX.IMUX.41GTM_DUAL.RXPRBSPTN_CH0_FS3
TCELL22:IMUX.IMUX.46GTM_DUAL.PMA_RSVDIN_CH0_FS15
TCELL23:OUT.1GTM_DUAL.AXIS_TDATA_CH0_SF6
TCELL23:OUT.2GTM_DUAL.AXIS_TDATA_CH0_SF0
TCELL23:OUT.4GTM_DUAL.RXPRBSERR_CH0_SF
TCELL23:OUT.6GTM_DUAL.AXIS_TDATA_CH0_SF4
TCELL23:OUT.8GTM_DUAL.AXIS_TDATA_CH0_SF7
TCELL23:OUT.10GTM_DUAL.PCS_SCANOUT_CH0_SF3
TCELL23:OUT.18GTM_DUAL.AXIS_TDATA_CH0_SF1
TCELL23:OUT.20GTM_DUAL.AXIS_TDATA_CH0_SF5
TCELL23:OUT.22GTM_DUAL.PMA_SCANOUT_CH0_SF17
TCELL23:OUT.24GTM_DUAL.AXIS_TDATA_CH0_SF3
TCELL23:OUT.25GTM_DUAL.PCS_SCANOUT_CH0_SF5
TCELL23:OUT.28GTM_DUAL.AXIS_TDATA_CH0_SF2
TCELL23:OUT.29GTM_DUAL.PCS_SCANOUT_CH0_SF4
TCELL23:OUT.31GTM_DUAL.PCS_SCANOUT_CH0_SF2
TCELL23:IMUX.CTRL.1GTM_DUAL.TXUSRCLK2_CH0_FS
TCELL23:IMUX.CTRL.5GTM_DUAL.TXUSRCLK_CH0_FS
TCELL23:IMUX.IMUX.4GTM_DUAL.TXEMPMAIN_CH0_FS2
TCELL23:IMUX.IMUX.11GTM_DUAL.TXCTLFIRDAT_CH0_FS2
TCELL23:IMUX.IMUX.17GTM_DUAL.TX_PCS_SEQ_ADVANCE_CH0_FS
TCELL23:IMUX.IMUX.19GTM_DUAL.TXEMPMAIN_CH0_FS0
TCELL23:IMUX.IMUX.22GTM_DUAL.TXCTLFIRDAT_CH0_FS5
TCELL23:IMUX.IMUX.23GTM_DUAL.TXDRVAMP_CH0_FS0
TCELL23:IMUX.IMUX.25GTM_DUAL.TXEMPMAIN_CH0_FS1
TCELL23:IMUX.IMUX.29GTM_DUAL.TXEMPPOS_CH0_FS0
TCELL23:IMUX.IMUX.30GTM_DUAL.TXCTLFIRDAT_CH0_FS0
TCELL23:IMUX.IMUX.34GTM_DUAL.TXEMPPOS_CH0_FS1
TCELL23:IMUX.IMUX.36GTM_DUAL.TXCTLFIRDAT_CH0_FS4
TCELL23:IMUX.IMUX.39GTM_DUAL.TXCTLFIRDAT_CH0_FS3
TCELL23:IMUX.IMUX.41GTM_DUAL.TXEMPPOS_CH0_FS2
TCELL23:IMUX.IMUX.45GTM_DUAL.TXEMPPRE2_CH0_FS0
TCELL23:IMUX.IMUX.46GTM_DUAL.TXCTLFIRDAT_CH0_FS1
TCELL24:OUT.0GTM_DUAL.PCS_SCANOUT_CH0_SF7
TCELL24:OUT.4GTM_DUAL.PCS_RSVDOUT_CH0_SF10
TCELL24:OUT.12GTM_DUAL.PMA_RSVDOUT_CH0_SF11
TCELL24:OUT.13GTM_DUAL.ST_RX_LN2_MAPPING_SF0
TCELL24:OUT.14GTM_DUAL.PCS_SCANOUT_CH0_SF9
TCELL24:OUT.16GTM_DUAL.TXRESETDONE_CH0_SF
TCELL24:OUT.19GTM_DUAL.PCS_SCANOUT_CH0_SF8
TCELL24:OUT.20GTM_DUAL.PCS_RSVDOUT_CH0_SF11
TCELL24:OUT.22GTM_DUAL.PMA_SCANOUT_CH0_SF18
TCELL24:OUT.24GTM_DUAL.TXBUFSTATUS_CH0_SF0
TCELL24:OUT.25GTM_DUAL.RXPRBSLOCKED_CH0_SF
TCELL24:OUT.30GTM_DUAL.PCS_SCANOUT_CH0_SF6
TCELL24:IMUX.IMUX.2GTM_DUAL.TXPRBSPTN_CH0_FS1
TCELL24:IMUX.IMUX.5GTM_DUAL.TXDRVAMP_CH0_FS1
TCELL24:IMUX.IMUX.8GTM_DUAL.TX_RESETMODE_CH0_FS1
TCELL24:IMUX.IMUX.11GTM_DUAL.TXPRBSPTN_CH0_FS0
TCELL24:IMUX.IMUX.13GTM_DUAL.TXEMPPOS_CH0_FS3
TCELL24:IMUX.IMUX.17GTM_DUAL.TXEMPPRE_CH0_FS1
TCELL24:IMUX.IMUX.22GTM_DUAL.TX_PMA_RESETMASK_CH0_FS1
TCELL24:IMUX.IMUX.24GTM_DUAL.TX_RESETMODE_CH0_FS0
TCELL24:IMUX.IMUX.26GTM_DUAL.TXEMPPRE_CH0_FS0
TCELL24:IMUX.IMUX.34GTM_DUAL.TXOUTCKCTL_CH0_FS0
TCELL24:IMUX.IMUX.36GTM_DUAL.TXDRVAMP_CH0_FS2
TCELL24:IMUX.IMUX.37GTM_DUAL.TX_PMA_RESETMASK_CH0_FS0
TCELL24:IMUX.IMUX.41GTM_DUAL.TXPRBSPTN_CH0_FS2
TCELL24:IMUX.IMUX.45GTM_DUAL.TXEMPPOS_CH0_FS4
TCELL24:IMUX.IMUX.47GTM_DUAL.TXPRBSPTN_CH0_FS3
TCELL25:OUT.4GTM_DUAL.PCS_SCANOUT_CH0_SF12
TCELL25:OUT.7GTM_DUAL.PMA_SCANOUT_CH0_SF21
TCELL25:OUT.9GTM_DUAL.PMA_SCANOUT_CH0_SF23
TCELL25:OUT.14GTM_DUAL.ST_RX_LN3_MAPPING_SF0
TCELL25:OUT.17GTM_DUAL.TXPROGDIVRESETDONE_CH0_SF
TCELL25:OUT.18GTM_DUAL.PMA_SCANOUT_CH0_SF22
TCELL25:OUT.21GTM_DUAL.PCS_SCANOUT_CH0_SF11
TCELL25:OUT.24GTM_DUAL.PMA_SCANOUT_CH0_SF19
TCELL25:OUT.26GTM_DUAL.TXPMARESETDONE_CH0_SF
TCELL25:OUT.28GTM_DUAL.PCS_SCANOUT_CH0_SF10
TCELL25:OUT.31GTM_DUAL.PMA_SCANOUT_CH0_SF20
TCELL25:IMUX.IMUX.2GTM_DUAL.TXEMPPRE_CH0_FS2
TCELL25:IMUX.IMUX.6GTM_DUAL.TXEMPPRE_CH0_FS3
TCELL25:IMUX.IMUX.7GTM_DUAL.TX_PCS_RESETMASK_CH0_FS0
TCELL25:IMUX.IMUX.12GTM_DUAL.TXMUXDCDORWREN_CH0_FS
TCELL25:IMUX.IMUX.13GTM_DUAL.TXDRVAMP_CH0_FS3
TCELL25:IMUX.IMUX.16GTM_DUAL.TXDRVAMP_CH0_FS4
TCELL25:IMUX.IMUX.27GTM_DUAL.TXUSRRDY_CH0_FS
TCELL25:IMUX.IMUX.28GTM_DUAL.TX_PCSRESET_CH0_FS
TCELL25:IMUX.IMUX.30GTM_DUAL.TXPOLARITY_CH0_FS
TCELL25:IMUX.IMUX.34GTM_DUAL.TXOUTCKCTL_CH0_FS1
TCELL25:IMUX.IMUX.35GTM_DUAL.TX_CKALRESET_CH0_FS
TCELL25:IMUX.IMUX.39GTM_DUAL.TX_FECRESET_CH0_FS
TCELL25:IMUX.IMUX.40GTM_DUAL.TXPRBSINERR_CH0_FS
TCELL25:IMUX.IMUX.42GTM_DUAL.TX_PROGDIVRESET_CH0_FS
TCELL25:IMUX.IMUX.47GTM_DUAL.TX_PMARESET_CH0_FS
TCELL26:OUT.3GTM_DUAL.RXBUFSTATUS_CH0_SF2
TCELL26:OUT.8GTM_DUAL.TXBUFSTATUS_CH0_SF1
TCELL26:OUT.9GTM_DUAL.PCS_SCANOUT_CH0_SF13
TCELL26:OUT.11GTM_DUAL.PCS_RSVDOUT_CH0_SF12
TCELL26:OUT.16GTM_DUAL.PMA_SCANOUT_CH0_SF24
TCELL26:OUT.18GTM_DUAL.RXPMARESETDONE_CH0_SF
TCELL26:OUT.19GTM_DUAL.RXBUFSTATUS_CH0_SF1
TCELL26:OUT.20GTM_DUAL.PMA_RSVDOUT_CH0_SF12
TCELL26:OUT.21GTM_DUAL.AXIS_TVALID_CH0_SF
TCELL26:OUT.28GTM_DUAL.RXBUFSTATUS_CH0_SF0
TCELL26:IMUX.IMUX.2GTM_DUAL.TXEMPPRE_CH0_FS4
TCELL26:IMUX.IMUX.4GTM_DUAL.TXMUXDCDEXHOLD_CH0_FS
TCELL26:IMUX.IMUX.5GTM_DUAL.TXEMPPRE2_CH0_FS1
TCELL26:IMUX.IMUX.9GTM_DUAL.TXEMPPRE2_CH0_FS3
TCELL26:IMUX.IMUX.11GTM_DUAL.TXQPRBS_ENA_CH0_FS
TCELL26:IMUX.IMUX.15GTM_DUAL.RX_CDRFRRESET_CH0_FS
TCELL26:IMUX.IMUX.17GTM_DUAL.RX_BUFRESET_CH0_FS
TCELL26:IMUX.IMUX.19GTM_DUAL.PMA_SCANCLK_CH0_FS8
TCELL26:IMUX.IMUX.22GTM_DUAL.TXEMPMAIN_CH0_FS5
TCELL26:IMUX.IMUX.23GTM_DUAL.TX_PCS_RESETMASK_CH0_FS1
TCELL26:IMUX.IMUX.30GTM_DUAL.TXOUTCKCTL_CH0_FS2
TCELL26:IMUX.IMUX.40GTM_DUAL.TXEMPMAIN_CH0_FS3
TCELL26:IMUX.IMUX.41GTM_DUAL.TXEMPPRE2_CH0_FS2
TCELL26:IMUX.IMUX.45GTM_DUAL.TXINHIBIT_CH0_FS
TCELL26:IMUX.IMUX.46GTM_DUAL.TXEMPMAIN_CH0_FS4
TCELL27:OUT.0GTM_DUAL.AXIS_TDATA_CH0_SF11
TCELL27:OUT.2GTM_DUAL.AXIS_TDATA_CH0_SF14
TCELL27:OUT.3GTM_DUAL.PCS_RSVDOUT_CH0_SF14
TCELL27:OUT.4GTM_DUAL.AXIS_TDATA_CH0_SF13
TCELL27:OUT.5GTM_DUAL.AXIS_TDATA_CH0_SF15
TCELL27:OUT.7GTM_DUAL.AXIS_TDATA_CH0_SF18
TCELL27:OUT.9GTM_DUAL.DMONOUT_CH0_SF30
TCELL27:OUT.10GTM_DUAL.AXIS_TDATA_CH0_SF16
TCELL27:OUT.11GTM_DUAL.AXIS_TDATA_CH0_SF9
TCELL27:OUT.14GTM_DUAL.AXIS_TDATA_CH0_SF17
TCELL27:OUT.15GTM_DUAL.AXIS_TDATA_CH0_SF10
TCELL27:OUT.16GTM_DUAL.AXIS_TDATA_CH0_SF19
TCELL27:OUT.18GTM_DUAL.AXIS_TDATA_CH0_SF12
TCELL27:OUT.19GTM_DUAL.AXIS_TDATA_CH0_SF8
TCELL27:OUT.23GTM_DUAL.PCS_RSVDOUT_CH0_SF13
TCELL27:OUT.24GTM_DUAL.PCS_SCANOUT_CH0_SF14
TCELL27:OUT.30GTM_DUAL.DMONOUT_CH0_SF29
TCELL27:IMUX.IMUX.0BUFG_GT0.DIV0
TCELL27:IMUX.IMUX.1BUFG_GT0.CEMASK
TCELL27:IMUX.IMUX.2BUFG_GT1.DIV1
TCELL27:IMUX.IMUX.3BUFG_GT1.CEMASK
TCELL27:IMUX.IMUX.4BUFG_GT2.DIV1
TCELL27:IMUX.IMUX.6BUFG_GT3.DIV1
TCELL27:IMUX.IMUX.7BUFG_GT4.DIV0
TCELL27:IMUX.IMUX.8BUFG_GT_SYNC0.RST_IN
TCELL27:IMUX.IMUX.9BUFG_GT_SYNC4.CE_IN
TCELL27:IMUX.IMUX.10BUFG_GT4.CEMASK
TCELL27:IMUX.IMUX.11BUFG_GT6.DIV0
TCELL27:IMUX.IMUX.12BUFG_GT6.DIV2
TCELL27:IMUX.IMUX.13BUFG_GT_SYNC6.CE_IN
TCELL27:IMUX.IMUX.14BUFG_GT8.DIV0
TCELL27:IMUX.IMUX.15BUFG_GT_SYNC7.CE_IN
TCELL27:IMUX.IMUX.16BUFG_GT0.DIV1
TCELL27:IMUX.IMUX.17BUFG_GT_SYNC0.CE_IN
TCELL27:IMUX.IMUX.18BUFG_GT0.DIV2
TCELL27:IMUX.IMUX.19BUFG_GT1.DIV0
TCELL27:IMUX.IMUX.20BUFG_GT_SYNC1.CE_IN
TCELL27:IMUX.IMUX.21BUFG_GT1.DIV2
TCELL27:IMUX.IMUX.22BUFG_GT2.DIV0
TCELL27:IMUX.IMUX.23BUFG_GT0.RSTMASK
TCELL27:IMUX.IMUX.24BUFG_GT2.DIV2
TCELL27:IMUX.IMUX.25BUFG_GT_SYNC2.CE_IN
TCELL27:IMUX.IMUX.26BUFG_GT2.CEMASK
TCELL27:IMUX.IMUX.27BUFG_GT3.DIV0
TCELL27:IMUX.IMUX.28BUFG_GT3.DIV2
TCELL27:IMUX.IMUX.29BUFG_GT_SYNC3.CE_IN
TCELL27:IMUX.IMUX.30BUFG_GT4.DIV1
TCELL27:IMUX.IMUX.31BUFG_GT3.CEMASK
TCELL27:IMUX.IMUX.32BUFG_GT4.DIV2
TCELL27:IMUX.IMUX.33BUFG_GT5.DIV0
TCELL27:IMUX.IMUX.34BUFG_GT5.DIV1
TCELL27:IMUX.IMUX.35BUFG_GT5.DIV2
TCELL27:IMUX.IMUX.37BUFG_GT_SYNC5.CE_IN
TCELL27:IMUX.IMUX.38BUFG_GT6.DIV1
TCELL27:IMUX.IMUX.39BUFG_GT1.RSTMASK
TCELL27:IMUX.IMUX.40BUFG_GT7.DIV0
TCELL27:IMUX.IMUX.41BUFG_GT5.CEMASK
TCELL27:IMUX.IMUX.42BUFG_GT7.DIV1
TCELL27:IMUX.IMUX.43BUFG_GT7.DIV2
TCELL27:IMUX.IMUX.44BUFG_GT8.DIV1
TCELL27:IMUX.IMUX.45BUFG_GT6.CEMASK
TCELL27:IMUX.IMUX.46BUFG_GT8.DIV2
TCELL28:OUT.2GTM_DUAL.PLL_RSVDOUT_SF0
TCELL28:OUT.3GTM_DUAL.AXIS_TDATA_CH0_SF23
TCELL28:OUT.8GTM_DUAL.PLL_RSVDOUT_SF1
TCELL28:OUT.11GTM_DUAL.AXIS_TDATA_CH0_SF20
TCELL28:OUT.12GTM_DUAL.AXIS_TDATA_CH0_SF21
TCELL28:OUT.15GTM_DUAL.PLL_RSVDOUT_SF2
TCELL28:OUT.17GTM_DUAL.PLL_SCANOUT_SF0
TCELL28:OUT.18GTM_DUAL.PLL_REFLOSS_SF
TCELL28:OUT.22GTM_DUAL.PLL_RSVDOUT_SF3
TCELL28:OUT.23GTM_DUAL.AXIS_TDATA_CH0_SF22
TCELL28:OUT.28GTM_DUAL.PLL_RSVDOUT_SF4
TCELL28:IMUX.CTRL.0GTM_DUAL.PLL_SCANRSTEN_FS
TCELL28:IMUX.CTRL.4GTM_DUAL.PLL_MONCLK_FS
TCELL28:IMUX.CTRL.6GTM_DUAL.PLL_RESET_FS
TCELL28:IMUX.IMUX.0BUFG_GT9.DIV0
TCELL28:IMUX.IMUX.1BUFG_GT9.DIV1
TCELL28:IMUX.IMUX.2BUFG_GT9.DIV2
TCELL28:IMUX.IMUX.3BUFG_GT4.RSTMASK
TCELL28:IMUX.IMUX.4BUFG_GT10.DIV1
TCELL28:IMUX.IMUX.5BUFG_GT10.DIV2
TCELL28:IMUX.IMUX.6BUFG_GT11.DIV0
TCELL28:IMUX.IMUX.7BUFG_GT7.RSTMASK
TCELL28:IMUX.IMUX.8BUFG_GT_SYNC8.CE_IN
TCELL28:IMUX.IMUX.9GTM_DUAL.SDM_DATA_FS6
TCELL28:IMUX.IMUX.10GTM_DUAL.SDM_DATA_FS7
TCELL28:IMUX.IMUX.11BUFG_GT12.DIV2
TCELL28:IMUX.IMUX.12BUFG_GT10.RSTMASK
TCELL28:IMUX.IMUX.13BUFG_GT_SYNC3.RST_IN
TCELL28:IMUX.IMUX.14GTM_DUAL.SDM_DATA_FS10
TCELL28:IMUX.IMUX.15BUFG_GT12.RSTMASK
TCELL28:IMUX.IMUX.16BUFG_GT2.RSTMASK
TCELL28:IMUX.IMUX.17GTM_DUAL.SDM_DATA_FS0
TCELL28:IMUX.IMUX.18BUFG_GT3.RSTMASK
TCELL28:IMUX.IMUX.19GTM_DUAL.SDM_DATA_FS1
TCELL28:IMUX.IMUX.20BUFG_GT_SYNC1.RST_IN
TCELL28:IMUX.IMUX.21BUFG_GT10.DIV0
TCELL28:IMUX.IMUX.22GTM_DUAL.SDM_DATA_FS2
TCELL28:IMUX.IMUX.24BUFG_GT5.RSTMASK
TCELL28:IMUX.IMUX.25GTM_DUAL.SDM_DATA_FS3
TCELL28:IMUX.IMUX.26GTM_DUAL.SDM_DATA_FS4
TCELL28:IMUX.IMUX.27BUFG_GT6.RSTMASK
TCELL28:IMUX.IMUX.28BUFG_GT11.DIV1
TCELL28:IMUX.IMUX.29GTM_DUAL.SDM_DATA_FS5
TCELL28:IMUX.IMUX.30BUFG_GT_SYNC2.RST_IN
TCELL28:IMUX.IMUX.31BUFG_GT7.CEMASK
TCELL28:IMUX.IMUX.33BUFG_GT11.DIV2
TCELL28:IMUX.IMUX.34BUFG_GT8.RSTMASK
TCELL28:IMUX.IMUX.35BUFG_GT12.DIV0
TCELL28:IMUX.IMUX.36BUFG_GT12.DIV1
TCELL28:IMUX.IMUX.37BUFG_GT9.RSTMASK
TCELL28:IMUX.IMUX.38GTM_DUAL.SDM_DATA_FS8
TCELL28:IMUX.IMUX.40BUFG_GT13.DIV0
TCELL28:IMUX.IMUX.41GTM_DUAL.SDM_DATA_FS9
TCELL28:IMUX.IMUX.42BUFG_GT13.DIV1
TCELL28:IMUX.IMUX.43BUFG_GT11.RSTMASK
TCELL28:IMUX.IMUX.44BUFG_GT13.DIV2
TCELL28:IMUX.IMUX.45BUFG_GT14.DIV0
TCELL28:IMUX.IMUX.46GTM_DUAL.SDM_DATA_FS11
TCELL29:OUT.0GTM_DUAL.AXIS_TDATA_CH0_SF26
TCELL29:OUT.1GTM_DUAL.DMONOUT_CH0_SF31
TCELL29:OUT.8GTM_DUAL.PMA_RSVDOUT_CH0_SF13
TCELL29:OUT.11GTM_DUAL.AXIS_TDATA_CH0_SF24
TCELL29:OUT.12GTM_DUAL.PMA_RSVDOUT_CH0_SF15
TCELL29:OUT.13GTM_DUAL.AXIS_TDATA_CH0_SF27
TCELL29:OUT.17GTM_DUAL.PMA_RSVDOUT_CH0_SF14
TCELL29:OUT.18GTM_DUAL.MGTREFCLKFA_SF
TCELL29:OUT.24GTM_DUAL.PCS_RSVDOUT_CH0_SF15
TCELL29:OUT.28GTM_DUAL.AXIS_TDATA_CH0_SF25
TCELL29:IMUX.CTRL.4GTM_DUAL.HROW_TEST_CK_FS
TCELL29:IMUX.IMUX.0BUFG_GT8.CEMASK
TCELL29:IMUX.IMUX.1BUFG_GT9.CEMASK
TCELL29:IMUX.IMUX.2BUFG_GT10.CEMASK
TCELL29:IMUX.IMUX.4BUFG_GT15.RSTMASK
TCELL29:IMUX.IMUX.5BUFG_GT15.DIV1
TCELL29:IMUX.IMUX.6GTM_DUAL.CTRL_RX0_BITSLIP_FS
TCELL29:IMUX.IMUX.7BUFG_GT_SYNC11.CE_IN
TCELL29:IMUX.IMUX.8ABUS_SWITCH_GT0.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT1.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT2.TEST_ANALOGBUS_SEL_B, ABUS_SWITCH_GT3.TEST_ANALOGBUS_SEL_B
TCELL29:IMUX.IMUX.9BUFG_GT15.CEMASK
TCELL29:IMUX.IMUX.10BUFG_GT18.RSTMASK
TCELL29:IMUX.IMUX.11BUFG_GT17.CEMASK
TCELL29:IMUX.IMUX.12BUFG_GT16.DIV2
TCELL29:IMUX.IMUX.13BUFG_GT20.RSTMASK
TCELL29:IMUX.IMUX.14BUFG_GT19.CEMASK
TCELL29:IMUX.IMUX.15BUFG_GT21.RSTMASK
TCELL29:IMUX.IMUX.16BUFG_GT14.DIV1
TCELL29:IMUX.IMUX.17BUFG_GT13.RSTMASK
TCELL29:IMUX.IMUX.18BUFG_GT_SYNC9.CE_IN
TCELL29:IMUX.IMUX.19BUFG_GT14.DIV2
TCELL29:IMUX.IMUX.20BUFG_GT_SYNC4.RST_IN
TCELL29:IMUX.IMUX.21BUFG_GT14.RSTMASK
TCELL29:IMUX.IMUX.22BUFG_GT15.DIV0
TCELL29:IMUX.IMUX.23BUFG_GT11.CEMASK
TCELL29:IMUX.IMUX.24BUFG_GT_SYNC10.CE_IN
TCELL29:IMUX.IMUX.25BUFG_GT12.CEMASK
TCELL29:IMUX.IMUX.26BUFG_GT13.CEMASK
TCELL29:IMUX.IMUX.27BUFG_GT16.RSTMASK
TCELL29:IMUX.IMUX.28BUFG_GT15.DIV2
TCELL29:IMUX.IMUX.29BUFG_GT14.CEMASK
TCELL29:IMUX.IMUX.30BUFG_GT_SYNC5.RST_IN
TCELL29:IMUX.IMUX.31GTM_DUAL.PLL_FBDIV_FS0
TCELL29:IMUX.IMUX.32GTM_DUAL.PLL_SCANIN_FS0
TCELL29:IMUX.IMUX.33BUFG_GT17.RSTMASK
TCELL29:IMUX.IMUX.34BUFG_GT16.DIV0
TCELL29:IMUX.IMUX.36BUFG_GT16.DIV1
TCELL29:IMUX.IMUX.37BUFG_GT16.CEMASK
TCELL29:IMUX.IMUX.38BUFG_GT_SYNC12.CE_IN
TCELL29:IMUX.IMUX.39BUFG_GT19.RSTMASK
TCELL29:IMUX.IMUX.40BUFG_GT18.CEMASK
TCELL29:IMUX.IMUX.41GTM_DUAL.SDM_TOGGLE_FS
TCELL29:IMUX.IMUX.42BUFG_GT_SYNC6.RST_IN
TCELL29:IMUX.IMUX.43BUFG_GT17.DIV0
TCELL29:IMUX.IMUX.44BUFG_GT_SYNC13.CE_IN
TCELL29:IMUX.IMUX.45BUFG_GT20.CEMASK
TCELL29:IMUX.IMUX.46BUFG_GT17.DIV1
TCELL30:OUT.1GTM_DUAL.PLL_RSVDOUT_SF5
TCELL30:OUT.3GTM_DUAL.AXIS_TDATA_CH1_SF25
TCELL30:OUT.4GTM_DUAL.PLL_RSVDOUT_SF6
TCELL30:OUT.6GTM_DUAL.PLL_RSVDOUT_SF7
TCELL30:OUT.7GTM_DUAL.PCS_RSVDOUT_CH1_SF15
TCELL30:OUT.9GTM_DUAL.PLL_RSVDOUT_SF8
TCELL30:OUT.11GTM_DUAL.PLL_RSVDOUT_SF9
TCELL30:OUT.13GTM_DUAL.PLL_SCANOUT_SF1
TCELL30:OUT.14GTM_DUAL.PMA_RSVDOUT_CH1_SF14
TCELL30:OUT.15GTM_DUAL.PLL_RSVDOUT_SF10
TCELL30:OUT.17GTM_DUAL.PLL_RSVDOUT_SF11
TCELL30:OUT.18GTM_DUAL.AXIS_TDATA_CH1_SF27
TCELL30:OUT.19GTM_DUAL.PMA_RSVDOUT_CH1_SF15
TCELL30:OUT.20GTM_DUAL.AXIS_TDATA_CH1_SF24
TCELL30:OUT.22GTM_DUAL.PLL_RSVDOUT_SF12
TCELL30:OUT.23GTM_DUAL.PMA_RSVDOUT_CH1_SF13
TCELL30:OUT.25GTM_DUAL.PLL_RSVDOUT_SF13
TCELL30:OUT.27GTM_DUAL.PLL_RSVDOUT_SF14
TCELL30:OUT.29GTM_DUAL.PLL_RSVDOUT_SF15
TCELL30:OUT.30GTM_DUAL.DMONOUT_CH1_SF31
TCELL30:OUT.31GTM_DUAL.AXIS_TDATA_CH1_SF26
TCELL30:IMUX.CTRL.4GTM_DUAL.COREREFCLK_FS
TCELL30:IMUX.IMUX.1BUFG_GT_SYNC7.RST_IN
TCELL30:IMUX.IMUX.2GTM_DUAL.PLL_RSVDIN_FS0
TCELL30:IMUX.IMUX.3GTM_DUAL.PLL_SCANMODEB_FS
TCELL30:IMUX.IMUX.4BUFG_GT_SYNC8.RST_IN
TCELL30:IMUX.IMUX.5BUFG_GT18.DIV1
TCELL30:IMUX.IMUX.6GTM_DUAL.SDM_DATA_FS16
TCELL30:IMUX.IMUX.7GTM_DUAL.PLLRESET_MASK_FS0
TCELL30:IMUX.IMUX.8ABUS_SWITCH_GT4.TEST_ANALOGBUS_SEL_B
TCELL30:IMUX.IMUX.9GTM_DUAL.PLL_SCANIN_FS2
TCELL30:IMUX.IMUX.10GTM_DUAL.REFCLKPD_FS
TCELL30:IMUX.IMUX.11BUFG_GT19.DIV0
TCELL30:IMUX.IMUX.12GTM_DUAL.SDM_DATA_FS18
TCELL30:IMUX.IMUX.13GTM_DUAL.SDM_DATA_FS19
TCELL30:IMUX.IMUX.14GTM_DUAL.PLL_REFDYN_FS2
TCELL30:IMUX.IMUX.15GTM_DUAL.SDM_DATA_FS20
TCELL30:IMUX.IMUX.16GTM_DUAL.SDM_DATA_FS12
TCELL30:IMUX.IMUX.17BUFG_GT17.DIV2
TCELL30:IMUX.IMUX.19GTM_DUAL.SDM_DATA_FS13
TCELL30:IMUX.IMUX.20GTM_DUAL.PLL_SCANIN_FS1
TCELL30:IMUX.IMUX.21GTM_DUAL.PLL_REFDYN_FS0
TCELL30:IMUX.IMUX.22BUFG_GT18.DIV0
TCELL30:IMUX.IMUX.23GTM_DUAL.SDM_DATA_FS14
TCELL30:IMUX.IMUX.26GTM_DUAL.SDM_DATA_FS15
TCELL30:IMUX.IMUX.28BUFG_GT_SYNC9.RST_IN
TCELL30:IMUX.IMUX.29GTM_DUAL.PLL_RSVDIN_FS1
TCELL30:IMUX.IMUX.30BUFG_GT_SYNC14.CE_IN
TCELL30:IMUX.IMUX.31GTM_DUAL.PLL_FBDIV_FS1
TCELL30:IMUX.IMUX.32BUFG_GT22.RSTMASK
TCELL30:IMUX.IMUX.33BUFG_GT21.CEMASK
TCELL30:IMUX.IMUX.34GTM_DUAL.PLL_REFDYN_FS1
TCELL30:IMUX.IMUX.35BUFG_GT18.DIV2
TCELL30:IMUX.IMUX.36GTM_DUAL.SDM_DATA_FS17
TCELL30:IMUX.IMUX.38BUFG_GT_SYNC10.RST_IN
TCELL30:IMUX.IMUX.41BUFG_GT19.DIV1
TCELL30:IMUX.IMUX.42GTM_DUAL.PLL_RSVDIN_FS2
TCELL30:IMUX.IMUX.43GTM_DUAL.PLL_SCANIN_FS3
TCELL30:IMUX.IMUX.44GTM_DUAL.RESET_BYPASS_MODE_FS
TCELL30:IMUX.IMUX.45BUFG_GT_SYNC11.RST_IN
TCELL30:IMUX.IMUX.46BUFG_GT19.DIV2
TCELL30:RCLK.IMUX.17BUFG_GT_SYNC14.CLK_IN
TCELL31:OUT.2GTM_DUAL.PLL_SCANOUT_SF2
TCELL31:OUT.4GTM_DUAL.PLL_FBLOSS_SF
TCELL31:OUT.6GTM_DUAL.PLL_SCANOUT_SF3
TCELL31:OUT.8GTM_DUAL.AXIS_TDATA_CH1_SF22
TCELL31:OUT.12GTM_DUAL.PLL_SCANOUT_SF4
TCELL31:OUT.14GTM_DUAL.PLL_FREQLOCK_SF
TCELL31:OUT.17GTM_DUAL.PLL_SCANOUT_SF5
TCELL31:OUT.19GTM_DUAL.AXIS_TDATA_CH1_SF21
TCELL31:OUT.20GTM_DUAL.AXIS_TDATA_CH1_SF20
TCELL31:OUT.23GTM_DUAL.PLL_SCANOUT_SF6
TCELL31:OUT.25GTM_DUAL.PLL_RESETDONE_SF
TCELL31:OUT.28GTM_DUAL.AXIS_TDATA_CH1_SF23
TCELL31:OUT.29GTM_DUAL.PLL_SCANOUT_SF7
TCELL31:IMUX.CTRL.1GTM_DUAL.PLL_SCANCLK_FS0
TCELL31:IMUX.CTRL.3GTM_DUAL.PLL_SCANCLK_FS1
TCELL31:IMUX.CTRL.5GTM_DUAL.PLL_SCANCLK_FS2
TCELL31:IMUX.CTRL.7GTM_DUAL.PLL_SCANCLK_FS3
TCELL31:IMUX.IMUX.2GTM_DUAL.PLL_RSVDIN_FS4
TCELL31:IMUX.IMUX.3GTM_DUAL.PLL_RSVDIN_FS5
TCELL31:IMUX.IMUX.4GTM_DUAL.PLL_RSVDIN_FS6
TCELL31:IMUX.IMUX.5GTM_DUAL.PLL_RSVDIN_FS7
TCELL31:IMUX.IMUX.6GTM_DUAL.PLL_FBDIV_FS4
TCELL31:IMUX.IMUX.7GTM_DUAL.PLL_PWRDN_FS
TCELL31:IMUX.IMUX.8GTM_DUAL.PLLRESET_MASK_FS1
TCELL31:IMUX.IMUX.9GTM_DUAL.PLL_FBDIV_FS5
TCELL31:IMUX.IMUX.10GTM_DUAL.PLL_SCANIN_FS6
TCELL31:IMUX.IMUX.12GTM_DUAL.PLL_RSVDIN_FS12
TCELL31:IMUX.IMUX.13BUFG_GT_SYNC14.RST_IN
TCELL31:IMUX.IMUX.14GTM_DUAL.PLL_SCANIN_FS7
TCELL31:IMUX.IMUX.16GTM_DUAL.PLL_RSVDIN_FS3
TCELL31:IMUX.IMUX.17GTM_DUAL.PLL_FBDIV_FS2
TCELL31:IMUX.IMUX.18GTM_DUAL.SDM_DATA_FS21
TCELL31:IMUX.IMUX.19GTM_DUAL.PLL_SCANIN_FS4
TCELL31:IMUX.IMUX.20BUFG_GT_SYNC12.RST_IN
TCELL31:IMUX.IMUX.21GTM_DUAL.CTRL_RX1_BITSLIP_FS
TCELL31:IMUX.IMUX.22GTM_DUAL.PLL_FBDIV_FS3
TCELL31:IMUX.IMUX.25GTM_DUAL.SDM_DATA_FS22
TCELL31:IMUX.IMUX.27GTM_DUAL.PLL_SCANIN_FS5
TCELL31:IMUX.IMUX.29GTM_DUAL.PLL_RSVDIN_FS8
TCELL31:IMUX.IMUX.30BUFG_GT_SYNC13.RST_IN
TCELL31:IMUX.IMUX.31GTM_DUAL.PLL_RSVDIN_FS9
TCELL31:IMUX.IMUX.32GTM_DUAL.SDM_DATA_FS23
TCELL31:IMUX.IMUX.34GTM_DUAL.PLL_RSVDIN_FS10
TCELL31:IMUX.IMUX.36GTM_DUAL.PLL_RSVDIN_FS11
TCELL31:IMUX.IMUX.38GTM_DUAL.SDM_DATA_FS24
TCELL31:IMUX.IMUX.39GTM_DUAL.PLL_FBDIV_FS6
TCELL31:IMUX.IMUX.40GTM_DUAL.PLL_SCANENB_FS
TCELL31:IMUX.IMUX.41GTM_DUAL.PLL_RSVDIN_FS13
TCELL31:IMUX.IMUX.43GTM_DUAL.PLL_RSVDIN_FS14
TCELL31:IMUX.IMUX.44GTM_DUAL.PLL_FBDIV_FS7
TCELL31:IMUX.IMUX.45GTM_DUAL.SDM_DATA_FS25
TCELL31:IMUX.IMUX.46GTM_DUAL.PLL_RSVDIN_FS15
TCELL32:OUT.1GTM_DUAL.DMONOUT_CH1_SF29
TCELL32:OUT.7GTM_DUAL.PCS_SCANOUT_CH1_SF14
TCELL32:OUT.8GTM_DUAL.PCS_RSVDOUT_CH1_SF13
TCELL32:OUT.10GTM_DUAL.ST_RX_LN1_MAPPING_SF0
TCELL32:OUT.12GTM_DUAL.AXIS_TDATA_CH1_SF8
TCELL32:OUT.13GTM_DUAL.AXIS_TDATA_CH1_SF12
TCELL32:OUT.15GTM_DUAL.AXIS_TDATA_CH1_SF19
TCELL32:OUT.16GTM_DUAL.AXIS_TDATA_CH1_SF10
TCELL32:OUT.17GTM_DUAL.AXIS_TDATA_CH1_SF17
TCELL32:OUT.20GTM_DUAL.AXIS_TDATA_CH1_SF9
TCELL32:OUT.21GTM_DUAL.AXIS_TDATA_CH1_SF16
TCELL32:OUT.22GTM_DUAL.DMONOUT_CH1_SF30
TCELL32:OUT.24GTM_DUAL.AXIS_TDATA_CH1_SF18
TCELL32:OUT.26GTM_DUAL.AXIS_TDATA_CH1_SF15
TCELL32:OUT.27GTM_DUAL.AXIS_TDATA_CH1_SF13
TCELL32:OUT.28GTM_DUAL.PCS_RSVDOUT_CH1_SF14
TCELL32:OUT.29GTM_DUAL.AXIS_TDATA_CH1_SF14
TCELL32:OUT.31GTM_DUAL.AXIS_TDATA_CH1_SF11
TCELL32:IMUX.IMUX.8BUFG_GT23.RSTMASK
TCELL32:IMUX.IMUX.11BUFG_GT22.DIV2
TCELL32:IMUX.IMUX.15BUFG_GT23.DIV2
TCELL32:IMUX.IMUX.16BUFG_GT20.DIV0
TCELL32:IMUX.IMUX.18BUFG_GT20.DIV1
TCELL32:IMUX.IMUX.21BUFG_GT20.DIV2
TCELL32:IMUX.IMUX.23BUFG_GT22.CEMASK
TCELL32:IMUX.IMUX.24BUFG_GT21.DIV0
TCELL32:IMUX.IMUX.27BUFG_GT21.DIV1
TCELL32:IMUX.IMUX.29BUFG_GT21.DIV2
TCELL32:IMUX.IMUX.32BUFG_GT22.DIV0
TCELL32:IMUX.IMUX.35BUFG_GT22.DIV1
TCELL32:IMUX.IMUX.39BUFG_GT23.CEMASK
TCELL32:IMUX.IMUX.40BUFG_GT23.DIV0
TCELL32:IMUX.IMUX.43BUFG_GT23.DIV1
TCELL33:OUT.3GTM_DUAL.RXBUFSTATUS_CH1_SF0
TCELL33:OUT.10GTM_DUAL.AXIS_TVALID_CH1_SF
TCELL33:OUT.11GTM_DUAL.PMA_RSVDOUT_CH1_SF12
TCELL33:OUT.12GTM_DUAL.RXBUFSTATUS_CH1_SF1
TCELL33:OUT.13GTM_DUAL.RXPMARESETDONE_CH1_SF
TCELL33:OUT.15GTM_DUAL.PMA_SCANOUT_CH1_SF24
TCELL33:OUT.20GTM_DUAL.PCS_RSVDOUT_CH1_SF12
TCELL33:OUT.22GTM_DUAL.PCS_SCANOUT_CH1_SF13
TCELL33:OUT.23GTM_DUAL.TXBUFSTATUS_CH1_SF1
TCELL33:OUT.28GTM_DUAL.RXBUFSTATUS_CH1_SF2
TCELL33:IMUX.IMUX.1GTM_DUAL.TXINHIBIT_CH1_FS
TCELL33:IMUX.IMUX.3GTM_DUAL.TXEMPPRE2_CH1_FS2
TCELL33:IMUX.IMUX.12GTM_DUAL.TX_PCS_RESETMASK_CH1_FS1
TCELL33:IMUX.IMUX.14GTM_DUAL.PMA_SCANCLK_CH1_FS8
TCELL33:IMUX.IMUX.15GTM_DUAL.RX_BUFRESET_CH1_FS
TCELL33:IMUX.IMUX.16GTM_DUAL.TXEMPMAIN_CH1_FS4
TCELL33:IMUX.IMUX.17GTM_DUAL.RX_CDRFRRESET_CH1_FS
TCELL33:IMUX.IMUX.22GTM_DUAL.TXEMPMAIN_CH1_FS3
TCELL33:IMUX.IMUX.25GTM_DUAL.TXQPRBS_ENA_CH1_FS
TCELL33:IMUX.IMUX.29GTM_DUAL.TXEMPPRE2_CH1_FS3
TCELL33:IMUX.IMUX.32GTM_DUAL.TXOUTCKCTL_CH1_FS2
TCELL33:IMUX.IMUX.37GTM_DUAL.TXEMPPRE2_CH1_FS1
TCELL33:IMUX.IMUX.39GTM_DUAL.TXMUXDCDEXHOLD_CH1_FS
TCELL33:IMUX.IMUX.40GTM_DUAL.TXEMPMAIN_CH1_FS5
TCELL33:IMUX.IMUX.43GTM_DUAL.TXEMPPRE_CH1_FS4
TCELL34:OUT.0GTM_DUAL.PMA_SCANOUT_CH1_SF20
TCELL34:OUT.3GTM_DUAL.PCS_SCANOUT_CH1_SF10
TCELL34:OUT.5GTM_DUAL.TXPMARESETDONE_CH1_SF
TCELL34:OUT.7GTM_DUAL.PMA_SCANOUT_CH1_SF19
TCELL34:OUT.10GTM_DUAL.PCS_SCANOUT_CH1_SF11
TCELL34:OUT.13GTM_DUAL.PMA_SCANOUT_CH1_SF22
TCELL34:OUT.14GTM_DUAL.TXPROGDIVRESETDONE_CH1_SF
TCELL34:OUT.22GTM_DUAL.PMA_SCANOUT_CH1_SF23
TCELL34:OUT.24GTM_DUAL.PMA_SCANOUT_CH1_SF21
TCELL34:OUT.27GTM_DUAL.PCS_SCANOUT_CH1_SF12
TCELL34:IMUX.IMUX.0GTM_DUAL.TX_PMARESET_CH1_FS
TCELL34:IMUX.IMUX.4GTM_DUAL.TX_FECRESET_CH1_FS
TCELL34:IMUX.IMUX.6GTM_DUAL.TX_CKALRESET_CH1_FS
TCELL34:IMUX.IMUX.10GTM_DUAL.TXUSRRDY_CH1_FS
TCELL34:IMUX.IMUX.20GTM_DUAL.TX_PROGDIVRESET_CH1_FS
TCELL34:IMUX.IMUX.21GTM_DUAL.TXDRVAMP_CH1_FS3
TCELL34:IMUX.IMUX.22GTM_DUAL.TXPRBSINERR_CH1_FS
TCELL34:IMUX.IMUX.23GTM_DUAL.TXMUXDCDORWREN_CH1_FS
TCELL34:IMUX.IMUX.28GTM_DUAL.TXOUTCKCTL_CH1_FS1
TCELL34:IMUX.IMUX.32GTM_DUAL.TXPOLARITY_CH1_FS
TCELL34:IMUX.IMUX.33GTM_DUAL.TX_PCS_RESETMASK_CH1_FS0
TCELL34:IMUX.IMUX.34GTM_DUAL.TX_PCSRESET_CH1_FS
TCELL34:IMUX.IMUX.35GTM_DUAL.TXEMPPRE_CH1_FS3
TCELL34:IMUX.IMUX.43GTM_DUAL.TXEMPPRE_CH1_FS2
TCELL34:IMUX.IMUX.46GTM_DUAL.TXDRVAMP_CH1_FS4
TCELL35:OUT.1GTM_DUAL.PCS_SCANOUT_CH1_SF6
TCELL35:OUT.6GTM_DUAL.RXPRBSLOCKED_CH1_SF
TCELL35:OUT.7GTM_DUAL.TXBUFSTATUS_CH1_SF0
TCELL35:OUT.9GTM_DUAL.PMA_SCANOUT_CH1_SF18
TCELL35:OUT.11GTM_DUAL.PCS_RSVDOUT_CH1_SF11
TCELL35:OUT.12GTM_DUAL.PCS_SCANOUT_CH1_SF8
TCELL35:OUT.15GTM_DUAL.TXRESETDONE_CH1_SF
TCELL35:OUT.17GTM_DUAL.PCS_SCANOUT_CH1_SF9
TCELL35:OUT.18GTM_DUAL.ST_RX_LN1_MAPPING_SF1
TCELL35:OUT.19GTM_DUAL.PMA_RSVDOUT_CH1_SF11
TCELL35:OUT.27GTM_DUAL.PCS_RSVDOUT_CH1_SF10
TCELL35:OUT.31GTM_DUAL.PCS_SCANOUT_CH1_SF7
TCELL35:IMUX.IMUX.0GTM_DUAL.TXPRBSPTN_CH1_FS3
TCELL35:IMUX.IMUX.1GTM_DUAL.TXEMPPOS_CH1_FS4
TCELL35:IMUX.IMUX.3GTM_DUAL.TXPRBSPTN_CH1_FS2
TCELL35:IMUX.IMUX.5GTM_DUAL.TX_PMA_RESETMASK_CH1_FS0
TCELL35:IMUX.IMUX.15GTM_DUAL.TXEMPPRE_CH1_FS1
TCELL35:IMUX.IMUX.21GTM_DUAL.TXEMPPOS_CH1_FS3
TCELL35:IMUX.IMUX.25GTM_DUAL.TXPRBSPTN_CH1_FS0
TCELL35:IMUX.IMUX.26GTM_DUAL.TXDRVAMP_CH1_FS2
TCELL35:IMUX.IMUX.28GTM_DUAL.TXOUTCKCTL_CH1_FS0
TCELL35:IMUX.IMUX.31GTM_DUAL.TX_RESETMODE_CH1_FS1
TCELL35:IMUX.IMUX.36GTM_DUAL.TXEMPPRE_CH1_FS0
TCELL35:IMUX.IMUX.37GTM_DUAL.TXDRVAMP_CH1_FS1
TCELL35:IMUX.IMUX.38GTM_DUAL.TX_RESETMODE_CH1_FS0
TCELL35:IMUX.IMUX.40GTM_DUAL.TX_PMA_RESETMASK_CH1_FS1
TCELL35:IMUX.IMUX.43GTM_DUAL.TXPRBSPTN_CH1_FS1
TCELL36:OUT.0GTM_DUAL.PCS_SCANOUT_CH1_SF2
TCELL36:OUT.2GTM_DUAL.PCS_SCANOUT_CH1_SF4
TCELL36:OUT.3GTM_DUAL.AXIS_TDATA_CH1_SF2
TCELL36:OUT.6GTM_DUAL.PCS_SCANOUT_CH1_SF5
TCELL36:OUT.7GTM_DUAL.AXIS_TDATA_CH1_SF3
TCELL36:OUT.9GTM_DUAL.PMA_SCANOUT_CH1_SF17
TCELL36:OUT.11GTM_DUAL.AXIS_TDATA_CH1_SF5
TCELL36:OUT.13GTM_DUAL.AXIS_TDATA_CH1_SF1
TCELL36:OUT.21GTM_DUAL.PCS_SCANOUT_CH1_SF3
TCELL36:OUT.23GTM_DUAL.AXIS_TDATA_CH1_SF7
TCELL36:OUT.25GTM_DUAL.AXIS_TDATA_CH1_SF4
TCELL36:OUT.27GTM_DUAL.RXPRBSERR_CH1_SF
TCELL36:OUT.29GTM_DUAL.AXIS_TDATA_CH1_SF0
TCELL36:OUT.30GTM_DUAL.AXIS_TDATA_CH1_SF6
TCELL36:IMUX.CTRL.2GTM_DUAL.TXUSRCLK_CH1_FS
TCELL36:IMUX.CTRL.6GTM_DUAL.TXUSRCLK2_CH1_FS
TCELL36:IMUX.IMUX.1GTM_DUAL.TXEMPPRE2_CH1_FS0
TCELL36:IMUX.IMUX.3GTM_DUAL.TXEMPPOS_CH1_FS2
TCELL36:IMUX.IMUX.4GTM_DUAL.TXCTLFIRDAT_CH1_FS3
TCELL36:IMUX.IMUX.9GTM_DUAL.TXEMPPOS_CH1_FS0
TCELL36:IMUX.IMUX.11GTM_DUAL.TXEMPMAIN_CH1_FS1
TCELL36:IMUX.IMUX.12GTM_DUAL.TXDRVAMP_CH1_FS0
TCELL36:IMUX.IMUX.14GTM_DUAL.TXEMPMAIN_CH1_FS0
TCELL36:IMUX.IMUX.15GTM_DUAL.TX_PCS_SEQ_ADVANCE_CH1_FS
TCELL36:IMUX.IMUX.16GTM_DUAL.TXCTLFIRDAT_CH1_FS1
TCELL36:IMUX.IMUX.25GTM_DUAL.TXCTLFIRDAT_CH1_FS2
TCELL36:IMUX.IMUX.26GTM_DUAL.TXCTLFIRDAT_CH1_FS4
TCELL36:IMUX.IMUX.28GTM_DUAL.TXEMPPOS_CH1_FS1
TCELL36:IMUX.IMUX.32GTM_DUAL.TXCTLFIRDAT_CH1_FS0
TCELL36:IMUX.IMUX.39GTM_DUAL.TXEMPMAIN_CH1_FS2
TCELL36:IMUX.IMUX.40GTM_DUAL.TXCTLFIRDAT_CH1_FS5
TCELL37:OUT.0GTM_DUAL.RXDATA_CH1_SF238
TCELL37:OUT.1GTM_DUAL.RXDATA_FLAGS_CH1_SF3
TCELL37:OUT.2GTM_DUAL.PMA_SCANOUT_CH1_SF16
TCELL37:OUT.3GTM_DUAL.RXDATA_CH1_SF248
TCELL37:OUT.4GTM_DUAL.RXDATA_CH1_SF236
TCELL37:OUT.5GTM_DUAL.RXDATA_CH1_SF246
TCELL37:OUT.6GTM_DUAL.RXDATA_CH1_SF245
TCELL37:OUT.7GTM_DUAL.RXDATA_CH1_SF241
TCELL37:OUT.8GTM_DUAL.RXDATA_CH1_SF253
TCELL37:OUT.9GTM_DUAL.RXDATA_CH1_SF254
TCELL37:OUT.11GTM_DUAL.RXDATA_CH1_SF249
TCELL37:OUT.13GTM_DUAL.RXDATA_CH1_SF252
TCELL37:OUT.15GTM_DUAL.RXDATA_CH1_SF240
TCELL37:OUT.16GTM_DUAL.RXDATA_CH1_SF234
TCELL37:OUT.17GTM_DUAL.RXDATA_CH1_SF247
TCELL37:OUT.18GTM_DUAL.RXDATA_CH1_SF250
TCELL37:OUT.19GTM_DUAL.RXDATA_CH1_SF255
TCELL37:OUT.20GTM_DUAL.RXDATA_CH1_SF231
TCELL37:OUT.21GTM_DUAL.RXDATA_CH1_SF243
TCELL37:OUT.22GTM_DUAL.RXDATA_CH1_SF239
TCELL37:OUT.23GTM_DUAL.RXDATA_CH1_SF235
TCELL37:OUT.24GTM_DUAL.RXDATA_CH1_SF230
TCELL37:OUT.25GTM_DUAL.RXDATA_CH1_SF237
TCELL37:OUT.26GTM_DUAL.RXDATA_CH1_SF242
TCELL37:OUT.28GTM_DUAL.RXDATA_CH1_SF232
TCELL37:OUT.29GTM_DUAL.RXDATA_CH1_SF251
TCELL37:OUT.30GTM_DUAL.RXDATA_CH1_SF233
TCELL37:OUT.31GTM_DUAL.RXDATA_CH1_SF244
TCELL37:IMUX.IMUX.3GTM_DUAL.RXPRBSPTN_CH1_FS3
TCELL37:IMUX.IMUX.8GTM_DUAL.RXPRBS_CNT_STOP_CH1_FS
TCELL37:IMUX.IMUX.10GTM_DUAL.RX_ADC_CALRESET_CH1_FS
TCELL37:IMUX.IMUX.12GTM_DUAL.RX_PCS_RESETMASK_CH1_FS3
TCELL37:IMUX.IMUX.13GTM_DUAL.RX_ISCANRESET_CH1_FS
TCELL37:IMUX.IMUX.15GTM_DUAL.PCS_SCANRSTEN_CH1_FS
TCELL37:IMUX.IMUX.16GTM_DUAL.PMA_RSVDIN_CH1_FS15
TCELL37:IMUX.IMUX.23GTM_DUAL.DMONCLK_CH1_FS
TCELL37:IMUX.IMUX.33GTM_DUAL.PCS_RSVDIN_CH1_FS15
TCELL37:IMUX.IMUX.37GTM_DUAL.PCS_SCANIN_CH1_FS14
TCELL37:IMUX.IMUX.38GTM_DUAL.CDR_OVWREN_CH1_FS
TCELL37:IMUX.IMUX.41GTM_DUAL.RXEQTRAINING_CH1_FS
TCELL37:IMUX.IMUX.43GTM_DUAL.PCS_SCANIN_CH1_FS13
TCELL37:IMUX.IMUX.44GTM_DUAL.PMA_SCANENB_CH1_FS
TCELL37:IMUX.IMUX.47GTM_DUAL.CFGRESET_CH1_FS
TCELL38:OUT.0GTM_DUAL.RXDATA_CH1_SF221
TCELL38:OUT.1GTM_DUAL.RXDATA_CH1_SF223
TCELL38:OUT.2GTM_DUAL.RXDATA_CH1_SF225
TCELL38:OUT.3GTM_DUAL.RXDATA_CH1_SF220
TCELL38:OUT.4GTM_DUAL.RXDATA_CH1_SF215
TCELL38:OUT.6GTM_DUAL.RXDATA_CH1_SF213
TCELL38:OUT.9GTM_DUAL.PMA_RSVDOUT_CH1_SF10
TCELL38:OUT.10GTM_DUAL.RXDATA_CH1_SF224
TCELL38:OUT.11GTM_DUAL.RXDATA_CH1_SF214
TCELL38:OUT.12GTM_DUAL.RXDATA_CH1_SF222
TCELL38:OUT.13GTM_DUAL.RXDATA_FLAGS_CH1_SF1
TCELL38:OUT.14GTM_DUAL.RXDATA_CH1_SF218
TCELL38:OUT.16GTM_DUAL.RXDATA_CH1_SF211
TCELL38:OUT.17GTM_DUAL.RXDATA_CH1_SF210
TCELL38:OUT.18GTM_DUAL.DMONOUT_CH1_SF28
TCELL38:OUT.19GTM_DUAL.RXDATA_CH1_SF216
TCELL38:OUT.21GTM_DUAL.RXDATA_CH1_SF212
TCELL38:OUT.23GTM_DUAL.RXDATA_CH1_SF226
TCELL38:OUT.24GTM_DUAL.RXDATA_CH1_SF227
TCELL38:OUT.25GTM_DUAL.RXDATA_CH1_SF228
TCELL38:OUT.26GTM_DUAL.RXDATA_CH1_SF219
TCELL38:OUT.27GTM_DUAL.RXDATA_CH1_SF229
TCELL38:OUT.29GTM_DUAL.RXDATA_FLAGS_CH1_SF2
TCELL38:OUT.30GTM_DUAL.RXDATA_CH1_SF217
TCELL38:IMUX.IMUX.5GTM_DUAL.RX_PCS_RESETMASK_CH1_FS1
TCELL38:IMUX.IMUX.7GTM_DUAL.LOOPBACK_CH1_FS2
TCELL38:IMUX.IMUX.9GTM_DUAL.RX_PCSRESET_CH1_FS
TCELL38:IMUX.IMUX.11GTM_DUAL.RX_PCS_RESETMASK_CH1_FS0
TCELL38:IMUX.IMUX.14GTM_DUAL.CDR_FREQOS_CH1_FS
TCELL38:IMUX.IMUX.17GTM_DUAL.RXPRBSPTN_CH1_FS1
TCELL38:IMUX.IMUX.19GTM_DUAL.RX_PMARESET_CH1_FS
TCELL38:IMUX.IMUX.20GTM_DUAL.GTRXRESET_CH1_FS
TCELL38:IMUX.IMUX.21GTM_DUAL.RX_ADAPTRESET_CH1_FS
TCELL38:IMUX.IMUX.24GTM_DUAL.RESETOVRD_CH1_FS
TCELL38:IMUX.IMUX.27GTM_DUAL.RX_DSPRESET_CH1_FS
TCELL38:IMUX.IMUX.29GTM_DUAL.RX_PCS_RESETMASK_CH1_FS2
TCELL38:IMUX.IMUX.30GTM_DUAL.RXPRBSPTN_CH1_FS2
TCELL38:IMUX.IMUX.36GTM_DUAL.RX_PMA_RESETMASK_CH1_FS7
TCELL38:IMUX.IMUX.46GTM_DUAL.PCS_SCANIN_CH1_FS12
TCELL39:OUT.3GTM_DUAL.PMA_SCANOUT_CH1_SF14
TCELL39:OUT.5GTM_DUAL.PMA_SCANOUT_CH1_SF11
TCELL39:OUT.7GTM_DUAL.RXDATA_CH1_SF209
TCELL39:OUT.11GTM_DUAL.RXDATA_CH1_SF205
TCELL39:OUT.12GTM_DUAL.RXDATA_CH1_SF206
TCELL39:OUT.13GTM_DUAL.RXDATA_CH1_SF207
TCELL39:OUT.14GTM_DUAL.PCS_RSVDOUT_CH1_SF9
TCELL39:OUT.16GTM_DUAL.RXDATA_CH1_SF203
TCELL39:OUT.24GTM_DUAL.PMA_SCANOUT_CH1_SF12
TCELL39:OUT.25GTM_DUAL.PMA_SCANOUT_CH1_SF13
TCELL39:OUT.27GTM_DUAL.RXDATA_CH1_SF204
TCELL39:OUT.29GTM_DUAL.PMA_SCANOUT_CH1_SF15
TCELL39:OUT.31GTM_DUAL.RXDATA_CH1_SF208
TCELL39:IMUX.IMUX.4GTM_DUAL.RX_DFERESET_CH1_FS
TCELL39:IMUX.IMUX.8GTM_DUAL.RX_PROGDIVRESET_CH1_FS
TCELL39:IMUX.IMUX.9GTM_DUAL.RX_ADC_CLKGENRESET_CH1_FS
TCELL39:IMUX.IMUX.11GTM_DUAL.RXOUTCKCTL_CH1_FS2
TCELL39:IMUX.IMUX.14GTM_DUAL.PMA_SCANMODEB_CH1_FS
TCELL39:IMUX.IMUX.17GTM_DUAL.RX_USRSTART_CH1_FS
TCELL39:IMUX.IMUX.18GTM_DUAL.RXOUTCKCTL_CH1_FS0
TCELL39:IMUX.IMUX.25GTM_DUAL.PMA_SCANCLK_CH1_FS6
TCELL39:IMUX.IMUX.26GTM_DUAL.PMA_RSVDIN_CH1_FS14
TCELL39:IMUX.IMUX.30GTM_DUAL.RXOUTCKCTL_CH1_FS1
TCELL39:IMUX.IMUX.34GTM_DUAL.PMA_SCANCLK_CH1_FS7
TCELL39:IMUX.IMUX.36GTM_DUAL.PCS_SCANMODEB_CH1_FS
TCELL39:IMUX.IMUX.41GTM_DUAL.PMA_RSVDIN_CH1_FS12
TCELL39:IMUX.IMUX.44GTM_DUAL.PMA_SCANRSTEN_CH1_FS
TCELL39:IMUX.IMUX.47GTM_DUAL.PMA_RSVDIN_CH1_FS13
TCELL40:OUT.7GTM_DUAL.AXIS_TLAST_CH1_SF
TCELL40:OUT.9GTM_DUAL.RXDATA_CH1_SF202
TCELL40:OUT.10GTM_DUAL.RXPROGDIVRESETDONE_CH1_SF
TCELL40:OUT.11GTM_DUAL.RXDATA_IS_AM_CH1_SF
TCELL40:OUT.12GTM_DUAL.DMONOUT_CH1_SF25
TCELL40:OUT.15GTM_DUAL.DMONOUT_CH1_SF27
TCELL40:OUT.19GTM_DUAL.PMA_RSVDOUT_CH1_SF9
TCELL40:OUT.21GTM_DUAL.PMA_SCANOUT_CH1_SF10
TCELL40:OUT.22GTM_DUAL.DMONOUT_CH1_SF26
TCELL40:OUT.29GTM_DUAL.RXDATA_START_CH1_SF
TCELL40:IMUX.IMUX.2GTM_DUAL.FEC_SCANIN_FS119
TCELL40:IMUX.IMUX.6GTM_DUAL.FEC_SCANIN_FS122
TCELL40:IMUX.IMUX.10GTM_DUAL.FEC_SCANIN_FS125
TCELL40:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS126
TCELL40:IMUX.IMUX.14GTM_DUAL.DMONFIFORESET_CH1_FS
TCELL40:IMUX.IMUX.17GTM_DUAL.FEC_SCANIN_FS118
TCELL40:IMUX.IMUX.22GTM_DUAL.FEC_SCANIN_FS120
TCELL40:IMUX.IMUX.25GTM_DUAL.FEC_SCANIN_FS121
TCELL40:IMUX.IMUX.30GTM_DUAL.FEC_SCANIN_FS123
TCELL40:IMUX.IMUX.33GTM_DUAL.FEC_SCANIN_FS124
TCELL40:IMUX.IMUX.37GTM_DUAL.PMA_SCANCLK_CH1_FS4
TCELL40:IMUX.IMUX.38GTM_DUAL.PMA_SCANCLK_CH1_FS5
TCELL40:IMUX.IMUX.42GTM_DUAL.FEC_SCANIN_FS127
TCELL40:IMUX.IMUX.44GTM_DUAL.PCS_RSVDIN_CH1_FS14
TCELL40:IMUX.IMUX.46GTM_DUAL.FEC_SCANIN_FS128
TCELL41:OUT.1GTM_DUAL.RXDATA_CH1_SF195
TCELL41:OUT.2GTM_DUAL.RXDATA_CH1_SF193
TCELL41:OUT.3GTM_DUAL.RXDATA_CH1_SF201
TCELL41:OUT.4GTM_DUAL.RXDATA_CH1_SF190
TCELL41:OUT.5GTM_DUAL.RXDATA_CH1_SF181
TCELL41:OUT.7GTM_DUAL.RXDATA_CH1_SF179
TCELL41:OUT.8GTM_DUAL.RXDATA_CH1_SF198
TCELL41:OUT.9GTM_DUAL.RXDATA_CH1_SF185
TCELL41:OUT.10GTM_DUAL.RXDATA_CH1_SF180
TCELL41:OUT.11GTM_DUAL.RXDATA_CH1_SF178
TCELL41:OUT.12GTM_DUAL.RXDATA_CH1_SF187
TCELL41:OUT.13GTM_DUAL.RXDATA_CH1_SF197
TCELL41:OUT.14GTM_DUAL.RXDATA_CH1_SF192
TCELL41:OUT.15GTM_DUAL.RXDATA_CH1_SF182
TCELL41:OUT.16GTM_DUAL.RXDATA_CH1_SF174
TCELL41:OUT.17GTM_DUAL.RXDATA_CH1_SF175
TCELL41:OUT.18GTM_DUAL.RXDATA_CH1_SF189
TCELL41:OUT.19GTM_DUAL.RXDATA_CH1_SF194
TCELL41:OUT.20GTM_DUAL.RXDATA_CH1_SF199
TCELL41:OUT.21GTM_DUAL.RXDATA_CH1_SF183
TCELL41:OUT.22GTM_DUAL.RXDATA_CH1_SF177
TCELL41:OUT.23GTM_DUAL.RXDATA_CH1_SF196
TCELL41:OUT.24GTM_DUAL.RXDATA_CH1_SF176
TCELL41:OUT.25GTM_DUAL.RXDATA_CH1_SF186
TCELL41:OUT.26GTM_DUAL.RXDATA_CH1_SF188
TCELL41:OUT.28GTM_DUAL.RXDATA_CH1_SF200
TCELL41:OUT.29GTM_DUAL.RXDATA_CH1_SF191
TCELL41:OUT.30GTM_DUAL.RXDATA_CH1_SF184
TCELL41:IMUX.IMUX.1GTM_DUAL.PMA_RSVDIN_CH1_FS10
TCELL41:IMUX.IMUX.13GTM_DUAL.FEC_SCANIN_FS136
TCELL41:IMUX.IMUX.15GTM_DUAL.LOOPBACK_CH1_FS1
TCELL41:IMUX.IMUX.17GTM_DUAL.FEC_SCANIN_FS129
TCELL41:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS130
TCELL41:IMUX.IMUX.21GTM_DUAL.PMA_RSVDIN_CH1_FS11
TCELL41:IMUX.IMUX.22GTM_DUAL.RXPRBSCNTRST_CH1_FS
TCELL41:IMUX.IMUX.25GTM_DUAL.FEC_SCANIN_FS131
TCELL41:IMUX.IMUX.28GTM_DUAL.FEC_SCANIN_FS132
TCELL41:IMUX.IMUX.31GTM_DUAL.FEC_SCANIN_FS133
TCELL41:IMUX.IMUX.34GTM_DUAL.FEC_SCANIN_FS134
TCELL41:IMUX.IMUX.35GTM_DUAL.PMA_SCANCLK_CH1_FS2
TCELL41:IMUX.IMUX.38GTM_DUAL.PMA_SCANCLK_CH1_FS3
TCELL41:IMUX.IMUX.39GTM_DUAL.FEC_SCANIN_FS135
TCELL41:IMUX.IMUX.45GTM_DUAL.FEC_SCANIN_FS137
TCELL42:OUT.0GTM_DUAL.RXDATA_CH1_SF166
TCELL42:OUT.1GTM_DUAL.RXDATA_CH1_SF171
TCELL42:OUT.2GTM_DUAL.RXDATA_CH1_SF173
TCELL42:OUT.3GTM_DUAL.RXDATA_CH1_SF156
TCELL42:OUT.4GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF0
TCELL42:OUT.5GTM_DUAL.RXDATA_CH1_SF161
TCELL42:OUT.6GTM_DUAL.RXDATA_CH1_SF158
TCELL42:OUT.7GTM_DUAL.RXDATA_CH1_SF155
TCELL42:OUT.8GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF1
TCELL42:OUT.10GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF2
TCELL42:OUT.11GTM_DUAL.RXDATA_CH1_SF164
TCELL42:OUT.12GTM_DUAL.RXDATA_CH1_SF160
TCELL42:OUT.13GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF3
TCELL42:OUT.15GTM_DUAL.RXDATA_CH1_SF169
TCELL42:OUT.16GTM_DUAL.RXDATA_CH1_SF163
TCELL42:OUT.17GTM_DUAL.RXDATA_CH1_SF157
TCELL42:OUT.18GTM_DUAL.RXDATA_CH1_SF159
TCELL42:OUT.19GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF4
TCELL42:OUT.20GTM_DUAL.RXDATA_CH1_SF162
TCELL42:OUT.21GTM_DUAL.ST_RX_LN2_FEC_LOCK_SF
TCELL42:OUT.22GTM_DUAL.RXDATA_CH1_SF167
TCELL42:OUT.23GTM_DUAL.RXDATA_CH1_SF165
TCELL42:OUT.24GTM_DUAL.RXDATA_CH1_SF170
TCELL42:OUT.25GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF5
TCELL42:OUT.26GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF6
TCELL42:OUT.27GTM_DUAL.RXDATA_CH1_SF172
TCELL42:OUT.29GTM_DUAL.ST_RX_LN2_BIT_ERR_0TO1_INC_SF7
TCELL42:OUT.31GTM_DUAL.RXDATA_CH1_SF168
TCELL42:IMUX.CTRL.7GTM_DUAL.RXUSRCLK2_CH1_FS
TCELL42:IMUX.IMUX.2GTM_DUAL.RX_USRSTOP_CH1_FS
TCELL42:IMUX.IMUX.9GTM_DUAL.PCS_RSVDIN_CH1_FS13
TCELL42:IMUX.IMUX.16GTM_DUAL.GTTXRESET_CH1_FS
TCELL42:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS138
TCELL42:IMUX.IMUX.23GTM_DUAL.PMA_SCANIN_CH1_FS24
TCELL42:IMUX.IMUX.24GTM_DUAL.PCS_SCANCLK_CH1_FS0
TCELL42:IMUX.IMUX.27GTM_DUAL.CDR_INCPCTRL_CH1_FS
TCELL42:IMUX.IMUX.29GTM_DUAL.RX_CDRPHRESET_CH1_FS
TCELL42:IMUX.IMUX.31GTM_DUAL.PCS_SCANENB_CH1_FS
TCELL42:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS139
TCELL42:IMUX.IMUX.33GTM_DUAL.PCS_SCANCLK_CH1_FS1
TCELL42:IMUX.IMUX.37GTM_DUAL.RX_PCS_SEQ_ADVANCE_CH1_FS
TCELL42:IMUX.IMUX.42GTM_DUAL.FEC_SCANIN_FS140
TCELL42:IMUX.IMUX.43GTM_DUAL.AXIS_TREADY_CH1_FS
TCELL42:IMUX.IMUX.46GTM_DUAL.CDR_EXHOLD_CH1_FS
TCELL43:OUT.0GTM_DUAL.RXDATA_CH1_SF144
TCELL43:OUT.1GTM_DUAL.ST_RX_LN2_DELAY_SF0
TCELL43:OUT.2GTM_DUAL.RXDATA_CH1_SF150
TCELL43:OUT.3GTM_DUAL.RXDATA_CH1_SF154
TCELL43:OUT.4GTM_DUAL.ST_RX_LN2_DELAY_SF1
TCELL43:OUT.5GTM_DUAL.ST_RX_LN2_DELAY_SF2
TCELL43:OUT.6GTM_DUAL.ST_RX_LN2_DELAY_SF3
TCELL43:OUT.8GTM_DUAL.ST_RX_LN2_DELAY_SF4
TCELL43:OUT.9GTM_DUAL.ST_RX_LN2_DELAY_SF5
TCELL43:OUT.10GTM_DUAL.ST_RX_LN2_DELAY_SF6
TCELL43:OUT.11GTM_DUAL.ST_RX_LN2_DELAY_SF7
TCELL43:OUT.13GTM_DUAL.ST_RX_LN2_ERR_CNT_INC_SF0
TCELL43:OUT.14GTM_DUAL.ST_RX_LN2_DELAY_SF8
TCELL43:OUT.15GTM_DUAL.RXDATA_CH1_SF147
TCELL43:OUT.16GTM_DUAL.RXDATA_CH1_SF143
TCELL43:OUT.17GTM_DUAL.ST_RX_LN2_DELAY_SF9
TCELL43:OUT.18GTM_DUAL.ST_RX_LN2_DELAY_SF10
TCELL43:OUT.19GTM_DUAL.ST_RX_LN2_DELAY_SF11
TCELL43:OUT.20GTM_DUAL.RXDATA_CH1_SF145
TCELL43:OUT.21GTM_DUAL.RXDATA_CH1_SF146
TCELL43:OUT.22GTM_DUAL.RXDATA_CH1_SF152
TCELL43:OUT.24GTM_DUAL.RXDATA_CH1_SF153
TCELL43:OUT.25GTM_DUAL.RXDATA_CH1_SF151
TCELL43:OUT.26GTM_DUAL.ST_RX_LN2_DELAY_SF12
TCELL43:OUT.27GTM_DUAL.RXDATA_CH1_SF148
TCELL43:OUT.28GTM_DUAL.ST_RX_LN2_DELAY_SF13
TCELL43:OUT.29GTM_DUAL.RXDATA_CH1_SF149
TCELL43:OUT.30GTM_DUAL.ST_RX_LN2_DELAY_SF14
TCELL43:IMUX.IMUX.2GTM_DUAL.LOOPBACK_CH1_FS0
TCELL43:IMUX.IMUX.5GTM_DUAL.PCS_RSVDIN_CH1_FS11
TCELL43:IMUX.IMUX.9GTM_DUAL.PCS_RSVDIN_CH1_FS12
TCELL43:IMUX.IMUX.11GTM_DUAL.PCS_RSVDIN_CH1_FS9
TCELL43:IMUX.IMUX.13GTM_DUAL.PCS_SCANIN_CH1_FS11
TCELL43:IMUX.IMUX.14GTM_DUAL.PCS_SCANIN_CH1_FS9
TCELL43:IMUX.IMUX.17GTM_DUAL.PCS_SCANIN_CH1_FS10
TCELL43:IMUX.IMUX.21GTM_DUAL.PCS_SCANIN_CH1_FS8
TCELL43:IMUX.IMUX.23GTM_DUAL.FEC_SCANIN_FS141
TCELL43:IMUX.IMUX.29GTM_DUAL.RX_RESETMODE_CH1_FS1
TCELL43:IMUX.IMUX.30GTM_DUAL.RX_FECRESET_CH1_FS
TCELL43:IMUX.IMUX.32GTM_DUAL.RXQPRBS_ENA_CH1_FS
TCELL43:IMUX.IMUX.38GTM_DUAL.FEC_SCANIN_FS142
TCELL43:IMUX.IMUX.44GTM_DUAL.RXPOLARITY_CH1_FS
TCELL43:IMUX.IMUX.47GTM_DUAL.PCS_RSVDIN_CH1_FS10
TCELL44:OUT.0GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF0
TCELL44:OUT.1GTM_DUAL.RXDATA_CH1_SF140
TCELL44:OUT.2GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF1
TCELL44:OUT.3GTM_DUAL.ST_RX_LN2_ERR_CNT_INC_SF1
TCELL44:OUT.4GTM_DUAL.RXDATA_CH1_SF136
TCELL44:OUT.6GTM_DUAL.RXDATA_CH1_SF126
TCELL44:OUT.7GTM_DUAL.RXDATA_CH1_SF133
TCELL44:OUT.8GTM_DUAL.RXDATA_CH1_SF134
TCELL44:OUT.9GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF2
TCELL44:OUT.10GTM_DUAL.RXDATA_CH1_SF135
TCELL44:OUT.11GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF3
TCELL44:OUT.12GTM_DUAL.RXDATA_CH1_SF138
TCELL44:OUT.14GTM_DUAL.RXDATA_CH1_SF130
TCELL44:OUT.15GTM_DUAL.ST_RX_LN2_ERR_CNT_INC_SF2
TCELL44:OUT.16GTM_DUAL.RXDATA_CH1_SF129
TCELL44:OUT.17GTM_DUAL.RXDATA_CH1_SF128
TCELL44:OUT.18GTM_DUAL.RXDATA_CH1_SF132
TCELL44:OUT.19GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF4
TCELL44:OUT.20GTM_DUAL.RXDATA_CH1_SF137
TCELL44:OUT.21GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF5
TCELL44:OUT.23GTM_DUAL.RXDATA_CH1_SF131
TCELL44:OUT.24GTM_DUAL.RXDATA_CH1_SF139
TCELL44:OUT.25GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF6
TCELL44:OUT.26GTM_DUAL.RXDATA_CH1_SF141
TCELL44:OUT.27GTM_DUAL.RXDATA_CH1_SF127
TCELL44:OUT.28GTM_DUAL.ST_RX_LN2_ERR_CNT_INC_SF3
TCELL44:OUT.29GTM_DUAL.RXDATA_CH1_SF142
TCELL44:OUT.30GTM_DUAL.ST_RX_LN2_BIT_ERR_1TO0_INC_SF7
TCELL44:IMUX.CTRL.4GTM_DUAL.RXUSRCLK_CH1_FS
TCELL44:IMUX.IMUX.0GTM_DUAL.PMA_RSVDIN_CH1_FS6
TCELL44:IMUX.IMUX.1GTM_DUAL.PMA_RSVDIN_CH1_FS9
TCELL44:IMUX.IMUX.4GTM_DUAL.PCS_SCANIN_CH1_FS6
TCELL44:IMUX.IMUX.5GTM_DUAL.PCS_SCANIN_CH1_FS4
TCELL44:IMUX.IMUX.7GTM_DUAL.PMA_RSVDIN_CH1_FS7
TCELL44:IMUX.IMUX.9GTM_DUAL.FEC_SCANENB_FS
TCELL44:IMUX.IMUX.15GTM_DUAL.RX_PMA_RESETMASK_CH1_FS5
TCELL44:IMUX.IMUX.19GTM_DUAL.PCS_RSVDIN_CH1_FS8
TCELL44:IMUX.IMUX.21GTM_DUAL.PMA_RSVDIN_CH1_FS8
TCELL44:IMUX.IMUX.28GTM_DUAL.RX_PMA_RESETMASK_CH1_FS6
TCELL44:IMUX.IMUX.30GTM_DUAL.PCS_SCANIN_CH1_FS7
TCELL44:IMUX.IMUX.33GTM_DUAL.PCS_SCANIN_CH1_FS5
TCELL44:IMUX.IMUX.35GTM_DUAL.PCS_SCANIN_CH1_FS2
TCELL44:IMUX.IMUX.36GTM_DUAL.PCS_SCANIN_CH1_FS3
TCELL44:IMUX.IMUX.45GTM_DUAL.RX_PMA_RESETMASK_CH1_FS4
TCELL45:OUT.0GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF0
TCELL45:OUT.1GTM_DUAL.RXDATA_CH1_SF123
TCELL45:OUT.2GTM_DUAL.RXDATA_CH1_SF113
TCELL45:OUT.3GTM_DUAL.RXDATA_CH1_SF119
TCELL45:OUT.4GTM_DUAL.RXDATA_CH1_SF118
TCELL45:OUT.5GTM_DUAL.RXDATA_CH1_SF109
TCELL45:OUT.6GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF1
TCELL45:OUT.7GTM_DUAL.PMA_RSVDOUT_CH1_SF8
TCELL45:OUT.9GTM_DUAL.RXDATA_CH1_SF120
TCELL45:OUT.10GTM_DUAL.RXDATA_CH1_SF124
TCELL45:OUT.11GTM_DUAL.ST_RX_LN3_ERR_CNT_INC_SF0
TCELL45:OUT.12GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF2
TCELL45:OUT.13GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF3
TCELL45:OUT.15GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF4
TCELL45:OUT.16GTM_DUAL.RXDATA_CH1_SF111
TCELL45:OUT.17GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF5
TCELL45:OUT.19GTM_DUAL.RXDATA_CH1_SF110
TCELL45:OUT.20GTM_DUAL.RXDATA_CH1_SF114
TCELL45:OUT.21GTM_DUAL.RXDATA_CH1_SF116
TCELL45:OUT.22GTM_DUAL.ST_RX_LN3_ERR_CNT_INC_SF1
TCELL45:OUT.23GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF6
TCELL45:OUT.24GTM_DUAL.RXDATA_CH1_SF121
TCELL45:OUT.25GTM_DUAL.ST_RX_LN3_BIT_ERR_0TO1_INC_SF7
TCELL45:OUT.26GTM_DUAL.RXDATA_CH1_SF112
TCELL45:OUT.27GTM_DUAL.RXDATA_CH1_SF125
TCELL45:OUT.28GTM_DUAL.RXDATA_CH1_SF117
TCELL45:OUT.29GTM_DUAL.RXDATA_CH1_SF122
TCELL45:OUT.30GTM_DUAL.RXDATA_CH1_SF115
TCELL45:IMUX.CTRL.4GTM_DUAL.PCS_SCANRSTB_CH1_FS
TCELL45:IMUX.IMUX.1GTM_DUAL.PMA_SCANIN_CH1_FS21
TCELL45:IMUX.IMUX.4GTM_DUAL.RX_PMA_RESETMASK_CH1_FS3
TCELL45:IMUX.IMUX.10GTM_DUAL.PCS_SCANIN_CH1_FS0
TCELL45:IMUX.IMUX.12GTM_DUAL.RXUSRRDY_CH1_FS
TCELL45:IMUX.IMUX.13GTM_DUAL.FEC_SCANIN_FS145
TCELL45:IMUX.IMUX.14GTM_DUAL.PMA_RSVDIN_CH1_FS5
TCELL45:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS143
TCELL45:IMUX.IMUX.23GTM_DUAL.BSR_SERIAL_CH1_FS
TCELL45:IMUX.IMUX.28GTM_DUAL.PMA_SCANIN_CH1_FS22
TCELL45:IMUX.IMUX.29GTM_DUAL.PMA_SCANIN_CH1_FS23
TCELL45:IMUX.IMUX.31GTM_DUAL.FEC_SCANIN_FS144
TCELL45:IMUX.IMUX.32GTM_DUAL.PCS_SCANIN_CH1_FS1
TCELL45:IMUX.IMUX.39GTM_DUAL.PMA_RSVDIN_CH1_FS4
TCELL45:IMUX.IMUX.42GTM_DUAL.RX_RESETMODE_CH1_FS0
TCELL45:IMUX.IMUX.45GTM_DUAL.PCS_RSVDIN_CH1_FS7
TCELL46:OUT.0GTM_DUAL.RXDATA_CH1_SF97
TCELL46:OUT.1GTM_DUAL.RXDATA_CH1_SF96
TCELL46:OUT.2GTM_DUAL.ST_RX_LN3_DELAY_SF0
TCELL46:OUT.3GTM_DUAL.RXDATA_CH1_SF108
TCELL46:OUT.4GTM_DUAL.ST_RX_LN3_DELAY_SF1
TCELL46:OUT.5GTM_DUAL.ST_RX_LN3_DELAY_SF2
TCELL46:OUT.6GTM_DUAL.ST_RX_LN3_DELAY_SF3
TCELL46:OUT.8GTM_DUAL.ST_RX_LN3_DELAY_SF4
TCELL46:OUT.9GTM_DUAL.ST_RX_LN3_DELAY_SF5
TCELL46:OUT.10GTM_DUAL.RXDATA_CH1_SF101
TCELL46:OUT.11GTM_DUAL.ST_RX_LN3_DELAY_SF6
TCELL46:OUT.12GTM_DUAL.ST_RX_LN3_DELAY_SF7
TCELL46:OUT.13GTM_DUAL.RXDATA_CH1_SF98
TCELL46:OUT.15GTM_DUAL.RXDATA_CH1_SF99
TCELL46:OUT.16GTM_DUAL.ST_RX_LN3_DELAY_SF8
TCELL46:OUT.17GTM_DUAL.ST_RX_LN3_DELAY_SF9
TCELL46:OUT.18GTM_DUAL.ST_RX_LN3_DELAY_SF10
TCELL46:OUT.19GTM_DUAL.ST_RX_LN3_DELAY_SF11
TCELL46:OUT.20GTM_DUAL.RXDATA_CH1_SF100
TCELL46:OUT.21GTM_DUAL.RXDATA_CH1_SF105
TCELL46:OUT.22GTM_DUAL.RXDATA_CH1_SF107
TCELL46:OUT.24GTM_DUAL.ST_RX_LN3_DELAY_SF12
TCELL46:OUT.25GTM_DUAL.RXDATA_CH1_SF106
TCELL46:OUT.26GTM_DUAL.RXDATA_CH1_SF104
TCELL46:OUT.27GTM_DUAL.ST_RX_LN3_DELAY_SF13
TCELL46:OUT.28GTM_DUAL.RXDATA_CH1_SF102
TCELL46:OUT.29GTM_DUAL.RXDATA_CH1_SF103
TCELL46:OUT.30GTM_DUAL.ST_RX_LN3_DELAY_SF14
TCELL46:IMUX.IMUX.2GTM_DUAL.RX_PMA_RESETMASK_CH1_FS1
TCELL46:IMUX.IMUX.5GTM_DUAL.PCS_RSVDIN_CH1_FS2
TCELL46:IMUX.IMUX.7GTM_DUAL.PCS_RSVDIN_CH1_FS5
TCELL46:IMUX.IMUX.9GTM_DUAL.PCS_RSVDIN_CH1_FS3
TCELL46:IMUX.IMUX.10GTM_DUAL.RXPRBSPTN_CH1_FS0
TCELL46:IMUX.IMUX.11GTM_DUAL.PCS_RSVDIN_CH1_FS6
TCELL46:IMUX.IMUX.15GTM_DUAL.PCS_RSVDIN_CH1_FS0
TCELL46:IMUX.IMUX.18GTM_DUAL.RX_PMA_RESETMASK_CH1_FS0
TCELL46:IMUX.IMUX.22GTM_DUAL.PCS_RSVDIN_CH1_FS1
TCELL46:IMUX.IMUX.24GTM_DUAL.PMA_SCANIN_CH1_FS18
TCELL46:IMUX.IMUX.25GTM_DUAL.PMA_SCANIN_CH1_FS20
TCELL46:IMUX.IMUX.31GTM_DUAL.AXIS_STREAMEN_CH1_FS
TCELL46:IMUX.IMUX.34GTM_DUAL.PMA_SCANIN_CH1_FS19
TCELL46:IMUX.IMUX.37GTM_DUAL.PCS_RSVDIN_CH1_FS4
TCELL46:IMUX.IMUX.46GTM_DUAL.RX_PMA_RESETMASK_CH1_FS2
TCELL47:OUT.0GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF0
TCELL47:OUT.1GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF1
TCELL47:OUT.3GTM_DUAL.ST_RX_LN3_ERR_CNT_INC_SF2
TCELL47:OUT.4GTM_DUAL.RXDATA_CH1_SF87
TCELL47:OUT.5GTM_DUAL.RXDATA_CH1_SF94
TCELL47:OUT.6GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF2
TCELL47:OUT.7GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF3
TCELL47:OUT.9GTM_DUAL.RXDATA_CH1_SF88
TCELL47:OUT.10GTM_DUAL.RXDATA_CH1_SF90
TCELL47:OUT.11GTM_DUAL.RXDATA_CH1_SF82
TCELL47:OUT.12GTM_DUAL.RXDATA_CH1_SF85
TCELL47:OUT.13GTM_DUAL.RXDATA_CH1_SF84
TCELL47:OUT.14GTM_DUAL.RXDATA_CH1_SF91
TCELL47:OUT.15GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF4
TCELL47:OUT.16GTM_DUAL.RXDATA_CH1_SF89
TCELL47:OUT.17GTM_DUAL.ST_RX_LN3_FEC_LOCK_SF
TCELL47:OUT.18GTM_DUAL.RXDATA_CH1_SF80
TCELL47:OUT.19GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF5
TCELL47:OUT.20GTM_DUAL.RXDATA_CH1_SF92
TCELL47:OUT.21GTM_DUAL.RXDATA_CH1_SF86
TCELL47:OUT.22GTM_DUAL.RXDATA_CH1_SF81
TCELL47:OUT.23GTM_DUAL.ST_RX_LN3_ERR_CNT_INC_SF3
TCELL47:OUT.24GTM_DUAL.RXDATA_CH1_SF93
TCELL47:OUT.25GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF6
TCELL47:OUT.26GTM_DUAL.RXDATA_CH1_SF95
TCELL47:OUT.28GTM_DUAL.ST_RX_LN3_BIT_ERR_1TO0_INC_SF7
TCELL47:OUT.30GTM_DUAL.RXDATA_CH1_SF83
TCELL47:OUT.31GTM_DUAL.RXDATA_CH1_SF79
TCELL47:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS146
TCELL47:IMUX.IMUX.13GTM_DUAL.PMA_SCANIN_CH1_FS14
TCELL47:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS152
TCELL47:IMUX.IMUX.16GTM_DUAL.PMA_SCANIN_CH1_FS15
TCELL47:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS147
TCELL47:IMUX.IMUX.22GTM_DUAL.PMA_SCANIN_CH1_FS17
TCELL47:IMUX.IMUX.23GTM_DUAL.PMA_SCANIN_CH1_FS16
TCELL47:IMUX.IMUX.26GTM_DUAL.FEC_SCANIN_FS148
TCELL47:IMUX.IMUX.30GTM_DUAL.FEC_SCANIN_FS149
TCELL47:IMUX.IMUX.31GTM_DUAL.PMA_SCANIN_CH1_FS12
TCELL47:IMUX.IMUX.34GTM_DUAL.FEC_SCANIN_FS150
TCELL47:IMUX.IMUX.38GTM_DUAL.FEC_SCANIN_FS151
TCELL47:IMUX.IMUX.40GTM_DUAL.PMA_RSVDIN_CH1_FS2
TCELL47:IMUX.IMUX.44GTM_DUAL.PMA_SCANIN_CH1_FS13
TCELL47:IMUX.IMUX.46GTM_DUAL.PMA_RSVDIN_CH1_FS3
TCELL48:OUT.0GTM_DUAL.RXDATA_CH1_SF76
TCELL48:OUT.1GTM_DUAL.RXDATA_CH1_SF67
TCELL48:OUT.2GTM_DUAL.RXDATA_CH1_SF69
TCELL48:OUT.4GTM_DUAL.ST_RX1_CORR_CW_INC_SF
TCELL48:OUT.6GTM_DUAL.ST_RX1_CW_INC_SF
TCELL48:OUT.8GTM_DUAL.RXDATA_CH1_SF75
TCELL48:OUT.9GTM_DUAL.RXDATA_CH1_SF55
TCELL48:OUT.10GTM_DUAL.RXDATA_CH1_SF68
TCELL48:OUT.11GTM_DUAL.RXDATA_CH1_SF56
TCELL48:OUT.12GTM_DUAL.RXDATA_CH1_SF64
TCELL48:OUT.13GTM_DUAL.RXDATA_CH1_SF70
TCELL48:OUT.14GTM_DUAL.RXDATA_CH1_SF77
TCELL48:OUT.15GTM_DUAL.RXDATA_CH1_SF60
TCELL48:OUT.16GTM_DUAL.RXDATA_CH1_SF74
TCELL48:OUT.17GTM_DUAL.RXDATA_CH1_SF78
TCELL48:OUT.18GTM_DUAL.RXDATA_CH1_SF66
TCELL48:OUT.19GTM_DUAL.RXDATA_CH1_SF61
TCELL48:OUT.20GTM_DUAL.RXDATA_CH1_SF63
TCELL48:OUT.21GTM_DUAL.ST_RX1_FEC_ALIGNED_SF
TCELL48:OUT.22GTM_DUAL.RXDATA_CH1_SF65
TCELL48:OUT.23GTM_DUAL.RXDATA_CH1_SF62
TCELL48:OUT.24GTM_DUAL.RXDATA_CH1_SF59
TCELL48:OUT.25GTM_DUAL.RXDATA_CH1_SF73
TCELL48:OUT.27GTM_DUAL.RXDATA_CH1_SF72
TCELL48:OUT.28GTM_DUAL.ST_RX1_UNCORR_CW_INC_SF
TCELL48:OUT.29GTM_DUAL.RXDATA_CH1_SF71
TCELL48:OUT.30GTM_DUAL.RXDATA_CH1_SF57
TCELL48:OUT.31GTM_DUAL.RXDATA_CH1_SF58
TCELL48:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS240
TCELL48:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS233
TCELL48:IMUX.IMUX.4GTM_DUAL.TXDATA_CH1_FS221
TCELL48:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS236
TCELL48:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS241
TCELL48:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS219
TCELL48:IMUX.IMUX.9GTM_DUAL.TXDATA_CH1_FS254
TCELL48:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS227
TCELL48:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS255
TCELL48:IMUX.IMUX.13GTM_DUAL.TXDATA_CH1_FS243
TCELL48:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS230
TCELL48:IMUX.IMUX.16GTM_DUAL.TXDATA_CH1_FS224
TCELL48:IMUX.IMUX.17GTM_DUAL.TXDATA_CH1_FS252
TCELL48:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS223
TCELL48:IMUX.IMUX.19GTM_DUAL.TXDATA_CH1_FS247
TCELL48:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS245
TCELL48:IMUX.IMUX.22GTM_DUAL.TXDATA_CH1_FS235
TCELL48:IMUX.IMUX.23GTM_DUAL.TXDATA_CH1_FS246
TCELL48:IMUX.IMUX.24GTM_DUAL.TXDATA_CH1_FS238
TCELL48:IMUX.IMUX.25GTM_DUAL.TXDATA_CH1_FS231
TCELL48:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS218
TCELL48:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS251
TCELL48:IMUX.IMUX.31GTM_DUAL.TXDATA_CH1_FS228
TCELL48:IMUX.IMUX.32GTM_DUAL.TXDATA_CH1_FS234
TCELL48:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS244
TCELL48:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS237
TCELL48:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS250
TCELL48:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS253
TCELL48:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS242
TCELL48:IMUX.IMUX.39GTM_DUAL.TXDATA_CH1_FS220
TCELL48:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS248
TCELL48:IMUX.IMUX.41GTM_DUAL.TXDATA_CH1_FS222
TCELL48:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS239
TCELL48:IMUX.IMUX.43GTM_DUAL.TXDATA_CH1_FS226
TCELL48:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS232
TCELL48:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS249
TCELL48:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS229
TCELL48:IMUX.IMUX.47GTM_DUAL.TXDATA_CH1_FS225
TCELL49:OUT.1GTM_DUAL.RXDATA_CH1_SF49
TCELL49:OUT.2GTM_DUAL.RXDATA_CH1_SF47
TCELL49:OUT.3GTM_DUAL.RXDATA_CH1_SF52
TCELL49:OUT.4GTM_DUAL.RXDATA_CH1_SF34
TCELL49:OUT.5GTM_DUAL.RXDATA_CH1_SF40
TCELL49:OUT.6GTM_DUAL.RXDATA_CH1_SF46
TCELL49:OUT.7GTM_DUAL.RXDATA_CH1_SF50
TCELL49:OUT.8GTM_DUAL.RXDATA_CH1_SF43
TCELL49:OUT.9GTM_DUAL.RXDATA_CH1_SF38
TCELL49:OUT.10GTM_DUAL.RXDATA_CH1_SF33
TCELL49:OUT.12GTM_DUAL.RXDATA_CH1_SF32
TCELL49:OUT.13GTM_DUAL.RXDATA_CH1_SF31
TCELL49:OUT.14GTM_DUAL.RXDATA_CH1_SF30
TCELL49:OUT.16GTM_DUAL.RXDATA_CH1_SF28
TCELL49:OUT.17GTM_DUAL.RXDATA_CH1_SF53
TCELL49:OUT.19GTM_DUAL.RXDATA_CH1_SF51
TCELL49:OUT.20GTM_DUAL.RXDATA_CH1_SF44
TCELL49:OUT.21GTM_DUAL.RXDATA_CH1_SF35
TCELL49:OUT.22GTM_DUAL.RXDATA_CH1_SF45
TCELL49:OUT.23GTM_DUAL.RXDATA_CH1_SF54
TCELL49:OUT.24GTM_DUAL.RXDATA_CH1_SF48
TCELL49:OUT.25GTM_DUAL.RXDATA_CH1_SF39
TCELL49:OUT.26GTM_DUAL.RXDATA_CH1_SF36
TCELL49:OUT.27GTM_DUAL.RXDATA_CH1_SF29
TCELL49:OUT.28GTM_DUAL.RXDATA_CH1_SF27
TCELL49:OUT.29GTM_DUAL.RXDATA_CH1_SF37
TCELL49:OUT.30GTM_DUAL.RXDATA_CH1_SF42
TCELL49:OUT.31GTM_DUAL.RXDATA_CH1_SF41
TCELL49:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS210
TCELL49:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS194
TCELL49:IMUX.IMUX.6GTM_DUAL.TXDATA_CH1_FS204
TCELL49:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS196
TCELL49:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS184
TCELL49:IMUX.IMUX.9GTM_DUAL.TXDATA_CH1_FS201
TCELL49:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS195
TCELL49:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS211
TCELL49:IMUX.IMUX.12GTM_DUAL.TXDATA_CH1_FS193
TCELL49:IMUX.IMUX.13GTM_DUAL.TXDATA_CH1_FS187
TCELL49:IMUX.IMUX.14GTM_DUAL.TXDATA_CH1_FS209
TCELL49:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS208
TCELL49:IMUX.IMUX.17GTM_DUAL.TXDATA_CH1_FS217
TCELL49:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS206
TCELL49:IMUX.IMUX.19GTM_DUAL.TXDATA_CH1_FS213
TCELL49:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS214
TCELL49:IMUX.IMUX.22GTM_DUAL.TXDATA_CH1_FS188
TCELL49:IMUX.IMUX.23GTM_DUAL.TXDATA_CH1_FS215
TCELL49:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS199
TCELL49:IMUX.IMUX.28GTM_DUAL.TXDATA_CH1_FS197
TCELL49:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS198
TCELL49:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS200
TCELL49:IMUX.IMUX.31GTM_DUAL.TXDATA_CH1_FS205
TCELL49:IMUX.IMUX.32GTM_DUAL.TXDATA_CH1_FS186
TCELL49:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS216
TCELL49:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS207
TCELL49:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS191
TCELL49:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS212
TCELL49:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS183
TCELL49:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS192
TCELL49:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS185
TCELL49:IMUX.IMUX.43GTM_DUAL.TXDATA_CH1_FS189
TCELL49:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS203
TCELL49:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS190
TCELL49:IMUX.IMUX.47GTM_DUAL.TXDATA_CH1_FS202
TCELL50:OUT.0GTM_DUAL.RXDATA_CH1_SF19
TCELL50:OUT.1GTM_DUAL.RXDATA_CH1_SF2
TCELL50:OUT.2GTM_DUAL.RXDATA_CH1_SF14
TCELL50:OUT.3GTM_DUAL.RXDATA_CH1_SF12
TCELL50:OUT.5GTM_DUAL.RXDATA_CH1_SF15
TCELL50:OUT.6GTM_DUAL.RXDATA_CH1_SF24
TCELL50:OUT.7GTM_DUAL.RXDATA_CH1_SF17
TCELL50:OUT.8GTM_DUAL.RXDATA_CH1_SF20
TCELL50:OUT.9GTM_DUAL.RXDATA_CH1_SF0
TCELL50:OUT.11GTM_DUAL.RXDATA_CH1_SF11
TCELL50:OUT.12GTM_DUAL.RXDATA_CH1_SF5
TCELL50:OUT.13GTM_DUAL.RXDATA_CH1_SF13
TCELL50:OUT.14GTM_DUAL.RXDATA_CH1_SF23
TCELL50:OUT.15GTM_DUAL.RXDATA_CH1_SF18
TCELL50:OUT.16GTM_DUAL.RXDATA_CH1_SF3
TCELL50:OUT.17GTM_DUAL.RXDATA_CH1_SF4
TCELL50:OUT.18GTM_DUAL.RXDATA_CH1_SF7
TCELL50:OUT.19GTM_DUAL.RXDATA_CH1_SF1
TCELL50:OUT.20GTM_DUAL.RXDATA_CH1_SF10
TCELL50:OUT.21GTM_DUAL.RXDATA_CH1_SF8
TCELL50:OUT.23GTM_DUAL.RXDATA_CH1_SF6
TCELL50:OUT.24GTM_DUAL.RXDATA_CH1_SF21
TCELL50:OUT.25GTM_DUAL.RXDATA_CH1_SF16
TCELL50:OUT.26GTM_DUAL.RXDATA_CH1_SF9
TCELL50:OUT.27GTM_DUAL.RXDATA_CH1_SF26
TCELL50:OUT.28GTM_DUAL.RXDATA_FLAGS_CH1_SF0
TCELL50:OUT.29GTM_DUAL.RXDATA_CH1_SF25
TCELL50:OUT.30GTM_DUAL.RXDATA_CH1_SF22
TCELL50:IMUX.IMUX.0GTM_DUAL.TXDATA_CH1_FS167
TCELL50:IMUX.IMUX.1GTM_DUAL.TXDATA_CH1_FS152
TCELL50:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS175
TCELL50:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS160
TCELL50:IMUX.IMUX.4GTM_DUAL.TXDATA_CH1_FS176
TCELL50:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS150
TCELL50:IMUX.IMUX.6GTM_DUAL.TXDATA_CH1_FS164
TCELL50:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS178
TCELL50:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS179
TCELL50:IMUX.IMUX.9GTM_DUAL.TXDATA_CH1_FS153
TCELL50:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS157
TCELL50:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS149
TCELL50:IMUX.IMUX.13GTM_DUAL.TXDATA_CH1_FS168
TCELL50:IMUX.IMUX.19GTM_DUAL.TXDATA_CH1_FS155
TCELL50:IMUX.IMUX.21GTM_DUAL.TXDATA_CH1_FS177
TCELL50:IMUX.IMUX.23GTM_DUAL.TXDATA_CH1_FS163
TCELL50:IMUX.IMUX.25GTM_DUAL.TXDATA_CH1_FS162
TCELL50:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS166
TCELL50:IMUX.IMUX.28GTM_DUAL.TXDATA_CH1_FS170
TCELL50:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS151
TCELL50:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS182
TCELL50:IMUX.IMUX.31GTM_DUAL.TXDATA_CH1_FS165
TCELL50:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS174
TCELL50:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS154
TCELL50:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS173
TCELL50:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS169
TCELL50:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS159
TCELL50:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS172
TCELL50:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS158
TCELL50:IMUX.IMUX.41GTM_DUAL.TXDATA_CH1_FS180
TCELL50:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS181
TCELL50:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS156
TCELL50:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS171
TCELL50:IMUX.IMUX.47GTM_DUAL.TXDATA_CH1_FS161
TCELL51:OUT.0GTM_DUAL.PMA_SCANOUT_CH1_SF9
TCELL51:OUT.1GTM_DUAL.PMA_RSVDOUT_CH1_SF6
TCELL51:OUT.5GTM_DUAL.DMONOUT_CH1_SF24
TCELL51:OUT.13GTM_DUAL.PMA_RSVDOUT_CH1_SF4
TCELL51:OUT.16GTM_DUAL.PMA_SCANOUT_CH1_SF8
TCELL51:OUT.18GTM_DUAL.PMA_RSVDOUT_CH1_SF3
TCELL51:OUT.20GTM_DUAL.RXRESETDONE_CH1_SF
TCELL51:OUT.23GTM_DUAL.PMA_RSVDOUT_CH1_SF2
TCELL51:OUT.25GTM_DUAL.PMA_RSVDOUT_CH1_SF5
TCELL51:OUT.30GTM_DUAL.PMA_RSVDOUT_CH1_SF7
TCELL51:IMUX.CTRL.4GTM_DUAL.TSTCLK1_CH1_FS
TCELL51:IMUX.IMUX.0GTM_DUAL.TXDATA_CH1_FS144
TCELL51:IMUX.IMUX.1GTM_DUAL.TXDATA_CH1_FS145
TCELL51:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS134
TCELL51:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS135
TCELL51:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS141
TCELL51:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS125
TCELL51:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS117
TCELL51:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS115
TCELL51:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS138
TCELL51:IMUX.IMUX.12GTM_DUAL.TXDATA_CH1_FS114
TCELL51:IMUX.IMUX.14GTM_DUAL.TXDATA_CH1_FS112
TCELL51:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS121
TCELL51:IMUX.IMUX.16GTM_DUAL.TXDATA_CH1_FS130
TCELL51:IMUX.IMUX.17GTM_DUAL.TXDATA_CH1_FS131
TCELL51:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS143
TCELL51:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS124
TCELL51:IMUX.IMUX.21GTM_DUAL.TXDATA_CH1_FS127
TCELL51:IMUX.IMUX.23GTM_DUAL.TXDATA_CH1_FS128
TCELL51:IMUX.IMUX.24GTM_DUAL.TXDATA_CH1_FS133
TCELL51:IMUX.IMUX.25GTM_DUAL.TXDATA_CH1_FS120
TCELL51:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS111
TCELL51:IMUX.IMUX.28GTM_DUAL.TXDATA_CH1_FS146
TCELL51:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS119
TCELL51:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS136
TCELL51:IMUX.IMUX.32GTM_DUAL.TXDATA_CH1_FS140
TCELL51:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS148
TCELL51:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS123
TCELL51:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS126
TCELL51:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS147
TCELL51:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS118
TCELL51:IMUX.IMUX.39GTM_DUAL.TXDATA_CH1_FS129
TCELL51:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS139
TCELL51:IMUX.IMUX.41GTM_DUAL.TXDATA_CH1_FS113
TCELL51:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS137
TCELL51:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS142
TCELL51:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS132
TCELL51:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS116
TCELL51:IMUX.IMUX.47GTM_DUAL.TXDATA_CH1_FS122
TCELL52:OUT.0GTM_DUAL.PMA_RSVDOUT_CH1_SF1
TCELL52:OUT.1GTM_DUAL.PMA_SCANOUT_CH1_SF7
TCELL52:OUT.2GTM_DUAL.PCS_RSVDOUT_CH1_SF2
TCELL52:OUT.3GTM_DUAL.DMONOUT_CH1_SF20
TCELL52:OUT.4GTM_DUAL.PCS_RSVDOUT_CH1_SF7
TCELL52:OUT.11GTM_DUAL.PCS_RSVDOUT_CH1_SF5
TCELL52:OUT.13GTM_DUAL.DMONOUT_CH1_SF21
TCELL52:OUT.16GTM_DUAL.PCS_RSVDOUT_CH1_SF3
TCELL52:OUT.18GTM_DUAL.PCS_RSVDOUT_CH1_SF4
TCELL52:OUT.21GTM_DUAL.PCS_RSVDOUT_CH1_SF6
TCELL52:OUT.22GTM_DUAL.PCS_RSVDOUT_CH1_SF1
TCELL52:OUT.23GTM_DUAL.PMA_SCANOUT_CH1_SF6
TCELL52:OUT.24GTM_DUAL.DMONOUT_CH1_SF22
TCELL52:OUT.25GTM_DUAL.DMONOUT_CH1_SF23
TCELL52:OUT.30GTM_DUAL.PMA_SCANOUT_CH1_SF5
TCELL52:OUT.31GTM_DUAL.PCS_RSVDOUT_CH1_SF8
TCELL52:IMUX.IMUX.0GTM_DUAL.TXDATA_CH1_FS85
TCELL52:IMUX.IMUX.1GTM_DUAL.TXDATA_CH1_FS103
TCELL52:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS108
TCELL52:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS93
TCELL52:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS73
TCELL52:IMUX.IMUX.6GTM_DUAL.TXDATA_CH1_FS87
TCELL52:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS89
TCELL52:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS82
TCELL52:IMUX.IMUX.9GTM_DUAL.TXDATA_CH1_FS79
TCELL52:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS88
TCELL52:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS86
TCELL52:IMUX.IMUX.13GTM_DUAL.TXDATA_CH1_FS94
TCELL52:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS90
TCELL52:IMUX.IMUX.16GTM_DUAL.TXDATA_CH1_FS97
TCELL52:IMUX.IMUX.17GTM_DUAL.TXDATA_CH1_FS84
TCELL52:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS76
TCELL52:IMUX.IMUX.19GTM_DUAL.TXDATA_CH1_FS105
TCELL52:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS74
TCELL52:IMUX.IMUX.22GTM_DUAL.TXDATA_CH1_FS99
TCELL52:IMUX.IMUX.24GTM_DUAL.TXDATA_CH1_FS106
TCELL52:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS110
TCELL52:IMUX.IMUX.28GTM_DUAL.TXDATA_CH1_FS91
TCELL52:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS101
TCELL52:IMUX.IMUX.31GTM_DUAL.TXDATA_CH1_FS78
TCELL52:IMUX.IMUX.32GTM_DUAL.TXDATA_CH1_FS109
TCELL52:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS75
TCELL52:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS80
TCELL52:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS98
TCELL52:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS100
TCELL52:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS96
TCELL52:IMUX.IMUX.39GTM_DUAL.TXDATA_CH1_FS83
TCELL52:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS95
TCELL52:IMUX.IMUX.41GTM_DUAL.TXDATA_CH1_FS104
TCELL52:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS92
TCELL52:IMUX.IMUX.43GTM_DUAL.TXDATA_CH1_FS107
TCELL52:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS102
TCELL52:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS77
TCELL52:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS81
TCELL53:OUT.4GTM_DUAL.PMA_RSVDOUT_CH1_SF0
TCELL53:OUT.8GTM_DUAL.PMA_SCANOUT_CH1_SF2
TCELL53:OUT.9GTM_DUAL.PMA_SCANOUT_CH1_SF4
TCELL53:OUT.14GTM_DUAL.FEC_SCANOUT_SF166
TCELL53:OUT.15GTM_DUAL.ST_RX_LN2_MAPPING_SF1
TCELL53:OUT.18GTM_DUAL.DMONOUT_CH1_SF16
TCELL53:OUT.23GTM_DUAL.DMONOUT_CH1_SF19
TCELL53:OUT.25GTM_DUAL.DMONOUT_CH1_SF17
TCELL53:OUT.28GTM_DUAL.DMONOUT_CH1_SF18
TCELL53:OUT.30GTM_DUAL.PMA_SCANOUT_CH1_SF3
TCELL53:IMUX.CTRL.0GTM_DUAL.TSTCLK0_CH1_FS
TCELL53:IMUX.IMUX.1GTM_DUAL.TXDATA_CH1_FS59
TCELL53:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS70
TCELL53:IMUX.IMUX.4GTM_DUAL.TXDATA_CH1_FS56
TCELL53:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS50
TCELL53:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS69
TCELL53:IMUX.IMUX.9GTM_DUAL.TXDATA_CH1_FS53
TCELL53:IMUX.IMUX.10GTM_DUAL.TXDATA_CH1_FS37
TCELL53:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS47
TCELL53:IMUX.IMUX.12GTM_DUAL.TXDATA_CH1_FS41
TCELL53:IMUX.IMUX.13GTM_DUAL.TXDATA_CH1_FS67
TCELL53:IMUX.IMUX.14GTM_DUAL.TXDATA_CH1_FS71
TCELL53:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS54
TCELL53:IMUX.IMUX.16GTM_DUAL.TXDATA_CH1_FS40
TCELL53:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS49
TCELL53:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS68
TCELL53:IMUX.IMUX.21GTM_DUAL.TXDATA_CH1_FS72
TCELL53:IMUX.IMUX.22GTM_DUAL.TXDATA_CH1_FS45
TCELL53:IMUX.IMUX.24GTM_DUAL.TXDATA_CH1_FS66
TCELL53:IMUX.IMUX.25GTM_DUAL.TXDATA_CH1_FS58
TCELL53:IMUX.IMUX.26GTM_DUAL.TXDATA_CH1_FS63
TCELL53:IMUX.IMUX.27GTM_DUAL.TXDATA_CH1_FS39
TCELL53:IMUX.IMUX.28GTM_DUAL.TXDATA_CH1_FS64
TCELL53:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS55
TCELL53:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS62
TCELL53:IMUX.IMUX.32GTM_DUAL.TXDATA_CH1_FS36
TCELL53:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS43
TCELL53:IMUX.IMUX.34GTM_DUAL.TXDATA_CH1_FS65
TCELL53:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS57
TCELL53:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS52
TCELL53:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS46
TCELL53:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS38
TCELL53:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS44
TCELL53:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS42
TCELL53:IMUX.IMUX.43GTM_DUAL.TXDATA_CH1_FS60
TCELL53:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS48
TCELL53:IMUX.IMUX.45GTM_DUAL.TXDATA_CH1_FS51
TCELL53:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS61
TCELL54:OUT.4GTM_DUAL.FEC_SCANOUT_SF167
TCELL54:OUT.6GTM_DUAL.DMONOUT_CH1_SF15
TCELL54:OUT.8GTM_DUAL.ST_RX_LN0_MAPPING_SF0
TCELL54:OUT.12GTM_DUAL.DMONOUT_CH1_SF14
TCELL54:OUT.15GTM_DUAL.FEC_SCANOUT_SF168
TCELL54:OUT.16GTM_DUAL.ST_RX_LN3_MAPPING_SF1
TCELL54:OUT.17GTM_DUAL.GTPOWERGOOD_SF
TCELL54:OUT.24GTM_DUAL.ST_RX_LN0_MAPPING_SF1
TCELL54:OUT.25GTM_DUAL.DMONOUT_CH1_SF13
TCELL54:OUT.27GTM_DUAL.FEC_SCANOUT_SF169
TCELL54:IMUX.IMUX.0GTM_DUAL.TXDATA_CH1_FS0
TCELL54:IMUX.IMUX.2GTM_DUAL.TXDATA_CH1_FS16
TCELL54:IMUX.IMUX.3GTM_DUAL.TXDATA_CH1_FS35
TCELL54:IMUX.IMUX.4GTM_DUAL.TXDATA_CH1_FS1
TCELL54:IMUX.IMUX.5GTM_DUAL.TXDATA_CH1_FS26
TCELL54:IMUX.IMUX.6GTM_DUAL.TXDATA_CH1_FS34
TCELL54:IMUX.IMUX.7GTM_DUAL.TXDATA_CH1_FS20
TCELL54:IMUX.IMUX.8GTM_DUAL.TXDATA_CH1_FS10
TCELL54:IMUX.IMUX.11GTM_DUAL.TXDATA_CH1_FS7
TCELL54:IMUX.IMUX.12GTM_DUAL.TXDATA_CH1_FS29
TCELL54:IMUX.IMUX.14GTM_DUAL.TXDATA_CH1_FS9
TCELL54:IMUX.IMUX.15GTM_DUAL.TXDATA_CH1_FS2
TCELL54:IMUX.IMUX.16GTM_DUAL.TXDATA_CH1_FS28
TCELL54:IMUX.IMUX.17GTM_DUAL.TXDATA_START_CH1_FS
TCELL54:IMUX.IMUX.18GTM_DUAL.TXDATA_CH1_FS32
TCELL54:IMUX.IMUX.20GTM_DUAL.TXDATA_CH1_FS24
TCELL54:IMUX.IMUX.21GTM_DUAL.TXDATA_CH1_FS8
TCELL54:IMUX.IMUX.23GTM_DUAL.TXDATA_CH1_FS15
TCELL54:IMUX.IMUX.24GTM_DUAL.TXDATA_CH1_FS12
TCELL54:IMUX.IMUX.25GTM_DUAL.TXDATA_CH1_FS25
TCELL54:IMUX.IMUX.26GTM_DUAL.TXDATA_CH1_FS11
TCELL54:IMUX.IMUX.29GTM_DUAL.TXDATA_CH1_FS31
TCELL54:IMUX.IMUX.30GTM_DUAL.TXDATA_CH1_FS14
TCELL54:IMUX.IMUX.31GTM_DUAL.TXDATA_CH1_FS13
TCELL54:IMUX.IMUX.33GTM_DUAL.TXDATA_CH1_FS27
TCELL54:IMUX.IMUX.35GTM_DUAL.TXDATA_CH1_FS33
TCELL54:IMUX.IMUX.36GTM_DUAL.TXDATA_CH1_FS3
TCELL54:IMUX.IMUX.37GTM_DUAL.TXDATA_CH1_FS21
TCELL54:IMUX.IMUX.38GTM_DUAL.TXDATA_CH1_FS18
TCELL54:IMUX.IMUX.39GTM_DUAL.TXDATA_CH1_FS30
TCELL54:IMUX.IMUX.40GTM_DUAL.TXDATA_CH1_FS17
TCELL54:IMUX.IMUX.41GTM_DUAL.TXDATA_CH1_FS19
TCELL54:IMUX.IMUX.42GTM_DUAL.TXDATA_CH1_FS22
TCELL54:IMUX.IMUX.43GTM_DUAL.TXDATA_CH1_FS4
TCELL54:IMUX.IMUX.44GTM_DUAL.TXDATA_CH1_FS23
TCELL54:IMUX.IMUX.46GTM_DUAL.TXDATA_CH1_FS6
TCELL54:IMUX.IMUX.47GTM_DUAL.TXDATA_CH1_FS5
TCELL55:OUT.1GTM_DUAL.FEC_SCANOUT_SF170
TCELL55:OUT.4GTM_DUAL.FEC_SCANOUT_SF171
TCELL55:OUT.7GTM_DUAL.FEC_SCANOUT_SF172
TCELL55:OUT.8GTM_DUAL.RESET_EXCEPTION_CH1_SF
TCELL55:OUT.12GTM_DUAL.FEC_SCANOUT_SF173
TCELL55:OUT.15GTM_DUAL.FEC_SCANOUT_SF174
TCELL55:OUT.19GTM_DUAL.FEC_SCANOUT_SF175
TCELL55:OUT.22GTM_DUAL.FEC_SCANOUT_SF176
TCELL55:OUT.26GTM_DUAL.FEC_SCANOUT_SF177
TCELL55:OUT.29GTM_DUAL.FEC_SCANOUT_SF178
TCELL55:IMUX.IMUX.11GTM_DUAL.FEC_SCANIN_FS163
TCELL55:IMUX.IMUX.12GTM_DUAL.FEC_SCANIN_FS164
TCELL55:IMUX.IMUX.13GTM_DUAL.FEC_SCANIN_FS165
TCELL55:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS166
TCELL55:IMUX.IMUX.15GTM_DUAL.FEC_SCANIN_FS167
TCELL55:IMUX.IMUX.16GTM_DUAL.FEC_SCANIN_FS153
TCELL55:IMUX.IMUX.18GTM_DUAL.FEC_SCANIN_FS154
TCELL55:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS155
TCELL55:IMUX.IMUX.22GTM_DUAL.FEC_SCANIN_FS156
TCELL55:IMUX.IMUX.24GTM_DUAL.FEC_SCANIN_FS157
TCELL55:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS158
TCELL55:IMUX.IMUX.29GTM_DUAL.FEC_SCANIN_FS159
TCELL55:IMUX.IMUX.31GTM_DUAL.FEC_SCANIN_FS160
TCELL55:IMUX.IMUX.33GTM_DUAL.FEC_SCANIN_FS161
TCELL55:IMUX.IMUX.35GTM_DUAL.FEC_SCANIN_FS162
TCELL56:OUT.2GTM_DUAL.DMONOUT_CH1_SF12
TCELL56:OUT.3GTM_DUAL.DMONOUT_CH1_SF11
TCELL56:OUT.7GTM_DUAL.PCS_RSVDOUT_CH1_SF0
TCELL56:OUT.11GTM_DUAL.DMONOUT_CH1_SF5
TCELL56:OUT.14GTM_DUAL.DMONOUT_CH1_SF6
TCELL56:OUT.16GTM_DUAL.FEC_SCANOUT_SF179
TCELL56:OUT.17GTM_DUAL.DMONOUT_CH1_SF7
TCELL56:OUT.19GTM_DUAL.DMONOUT_CH1_SF9
TCELL56:OUT.20GTM_DUAL.DMONOUT_CH1_SF8
TCELL56:OUT.29GTM_DUAL.DMONOUT_CH1_SF10
TCELL56:IMUX.IMUX.0GTM_DUAL.PMA_SCANIN_CH1_FS8
TCELL56:IMUX.IMUX.1GTM_DUAL.FEC_SCANIN_FS168
TCELL56:IMUX.IMUX.3GTM_DUAL.FEC_SCANIN_FS169
TCELL56:IMUX.IMUX.21GTM_DUAL.AXIS_EYESCANRST_CH1_FS
TCELL56:IMUX.IMUX.22GTM_DUAL.PMA_SCANIN_CH1_FS10
TCELL56:IMUX.IMUX.23GTM_DUAL.PMA_SCANIN_CH1_FS11
TCELL56:IMUX.IMUX.27GTM_DUAL.FEC_SCANIN_FS170
TCELL56:IMUX.IMUX.30GTM_DUAL.PMA_RSVDIN_CH1_FS1
TCELL56:IMUX.IMUX.31GTM_DUAL.PMA_RSVDIN_CH1_FS0
TCELL56:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS171
TCELL56:IMUX.IMUX.34GTM_DUAL.PMA_SCANIN_CH1_FS7
TCELL56:IMUX.IMUX.36GTM_DUAL.FEC_SCANIN_FS172
TCELL56:IMUX.IMUX.40GTM_DUAL.FEC_SCANIN_FS173
TCELL56:IMUX.IMUX.44GTM_DUAL.FEC_SCANIN_FS174
TCELL56:IMUX.IMUX.47GTM_DUAL.PMA_SCANIN_CH1_FS9
TCELL57:OUT.1GTM_DUAL.FEC_SCANOUT_SF180
TCELL57:OUT.3GTM_DUAL.FEC_SCANOUT_SF181
TCELL57:OUT.6GTM_DUAL.FEC_SCANOUT_SF182
TCELL57:OUT.9GTM_DUAL.FEC_SCANOUT_SF183
TCELL57:OUT.12GTM_DUAL.FEC_SCANOUT_SF184
TCELL57:OUT.15GTM_DUAL.FEC_SCANOUT_SF185
TCELL57:OUT.18GTM_DUAL.FEC_SCANOUT_SF186
TCELL57:OUT.21GTM_DUAL.FEC_SCANOUT_SF187
TCELL57:OUT.24GTM_DUAL.FEC_SCANOUT_SF188
TCELL57:OUT.27GTM_DUAL.FEC_SCANOUT_SF189
TCELL57:OUT.30GTM_DUAL.FEC_SCANOUT_SF190
TCELL57:IMUX.IMUX.6GTM_DUAL.FEC_SCANIN_FS180
TCELL57:IMUX.IMUX.7GTM_DUAL.FEC_SCANIN_FS181
TCELL57:IMUX.IMUX.8GTM_DUAL.FEC_SCANMODEB_FS
TCELL57:IMUX.IMUX.14GTM_DUAL.FEC_SCANIN_FS187
TCELL57:IMUX.IMUX.15GTM_DUAL.FEC_SCANIN_FS188
TCELL57:IMUX.IMUX.16GTM_DUAL.FEC_SCANIN_FS175
TCELL57:IMUX.IMUX.18GTM_DUAL.FEC_SCANIN_FS176
TCELL57:IMUX.IMUX.20GTM_DUAL.FEC_SCANIN_FS177
TCELL57:IMUX.IMUX.23GTM_DUAL.FEC_SCANIN_FS178
TCELL57:IMUX.IMUX.25GTM_DUAL.FEC_SCANIN_FS179
TCELL57:IMUX.IMUX.32GTM_DUAL.FEC_SCANIN_FS182
TCELL57:IMUX.IMUX.34GTM_DUAL.FEC_SCANIN_FS183
TCELL57:IMUX.IMUX.36GTM_DUAL.FEC_SCANIN_FS184
TCELL57:IMUX.IMUX.39GTM_DUAL.FEC_SCANIN_FS185
TCELL57:IMUX.IMUX.41GTM_DUAL.FEC_SCANIN_FS186
TCELL58:OUT.1GTM_DUAL.FEC_SCANOUT_SF191
TCELL58:OUT.2GTM_DUAL.DMONOUT_CH1_SF2
TCELL58:OUT.5GTM_DUAL.DMONOUT_CH1_SF4
TCELL58:OUT.6GTM_DUAL.FEC_SCANOUT_SF192
TCELL58:OUT.10GTM_DUAL.FEC_SCANOUT_SF193
TCELL58:OUT.11GTM_DUAL.DMONOUT_CH1_SF3
TCELL58:OUT.15GTM_DUAL.FEC_SCANOUT_SF194
TCELL58:OUT.17GTM_DUAL.RCAL_SF0
TCELL58:OUT.20GTM_DUAL.FEC_SCANOUT_SF195
TCELL58:OUT.21GTM_DUAL.DMONOUT_CH1_SF1
TCELL58:OUT.25GTM_DUAL.FEC_SCANOUT_SF196
TCELL58:OUT.29GTM_DUAL.FEC_SCANOUT_SF197
TCELL58:IMUX.IMUX.5GTM_DUAL.FEC_SCANIN_FS191
TCELL58:IMUX.IMUX.9GTM_DUAL.FEC_SCANIN_FS193
TCELL58:IMUX.IMUX.11GTM_DUAL.BGRCALCTL_FS3
TCELL58:IMUX.IMUX.14GTM_DUAL.BGRCALCTL_FS4
TCELL58:IMUX.IMUX.17GTM_DUAL.FEC_SCANIN_FS189
TCELL58:IMUX.IMUX.18GTM_DUAL.BGRCALCTL_FS0
TCELL58:IMUX.IMUX.21GTM_DUAL.FEC_SCANIN_FS190
TCELL58:IMUX.IMUX.24GTM_DUAL.PMA_SCANIN_CH1_FS6
TCELL58:IMUX.IMUX.25GTM_DUAL.BGRCALCTL_FS1
TCELL58:IMUX.IMUX.29GTM_DUAL.FEC_SCANIN_FS192
TCELL58:IMUX.IMUX.31GTM_DUAL.BGRCALCTL_FS2
TCELL58:IMUX.IMUX.32GTM_DUAL.BGTESTEN_FS
TCELL58:IMUX.IMUX.37GTM_DUAL.FEC_SCANIN_FS194
TCELL58:IMUX.IMUX.41GTM_DUAL.FEC_SCANIN_FS195
TCELL58:IMUX.IMUX.45GTM_DUAL.FEC_SCANIN_FS196
TCELL59:OUT.3GTM_DUAL.RCAL_SF1
TCELL59:OUT.4GTM_DUAL.DMONOUT_CH1_SF0
TCELL59:OUT.6GTM_DUAL.PMA_SCANOUT_CH1_SF1
TCELL59:OUT.8GTM_DUAL.FEC_SCANOUT_SF198
TCELL59:OUT.12GTM_DUAL.RCAL_SF2
TCELL59:OUT.13GTM_DUAL.PCS_SCANOUT_CH1_SF0
TCELL59:OUT.16GTM_DUAL.RCAL_CMP_SF
TCELL59:OUT.19GTM_DUAL.RCAL_SF3
TCELL59:OUT.22GTM_DUAL.FEC_SCANOUT_SF199
TCELL59:OUT.24GTM_DUAL.PCS_SCANOUT_CH1_SF1
TCELL59:OUT.27GTM_DUAL.PMA_SCANOUT_CH1_SF0
TCELL59:OUT.28GTM_DUAL.RCAL_SF4
TCELL59:IMUX.IMUX.2GTM_DUAL.BGBYPASSB_FS
TCELL59:IMUX.IMUX.3GTM_DUAL.FEC_SCANIN_FS197
TCELL59:IMUX.IMUX.5GTM_DUAL.BGPWRDNB_FS
TCELL59:IMUX.IMUX.7GTM_DUAL.FEC_SCANIN_FS198
TCELL59:IMUX.IMUX.9GTM_DUAL.PMA_SCANIN_CH1_FS3
TCELL59:IMUX.IMUX.10GTM_DUAL.PMA_SCANCLK_CH1_FS0
TCELL59:IMUX.IMUX.12GTM_DUAL.RCALENB_FS
TCELL59:IMUX.IMUX.14GTM_DUAL.PMA_SCANIN_CH1_FS1
TCELL59:IMUX.IMUX.20GTM_DUAL.PMA_SCANIN_CH1_FS2
TCELL59:IMUX.IMUX.27GTM_DUAL.PMA_SCANIN_CH1_FS0
TCELL59:IMUX.IMUX.32GTM_DUAL.BGRCALOVRDENB_FS
TCELL59:IMUX.IMUX.38GTM_DUAL.FEC_SCANIN_FS199
TCELL59:IMUX.IMUX.40GTM_DUAL.PMA_SCANIN_CH1_FS5
TCELL59:IMUX.IMUX.41GTM_DUAL.PMA_SCANCLK_CH1_FS1
TCELL59:IMUX.IMUX.43GTM_DUAL.PMA_SCANIN_CH1_FS4