XP5IO
Tile XP5IO
Cells: 60
Bel LPDDRMC
| Pin | Direction | Wires |
|---|---|---|
| AXI0_ARADDR_10_NIB0_CLB2PHY_DLYCTL_EN_VTC | input | TCELL58:IMUX.IMUX.12.DELAY |
| AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN0 | input | TCELL54:IMUX.IMUX.19.DELAY |
| AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN1 | input | TCELL54:IMUX.IMUX.18.DELAY |
| AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN2 | input | TCELL54:IMUX.IMUX.1.DELAY |
| AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN3 | input | TCELL54:IMUX.IMUX.17.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL0 | input | TCELL54:IMUX.IMUX.23.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL1 | input | TCELL54:IMUX.IMUX.22.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL2 | input | TCELL54:IMUX.IMUX.3.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL3 | input | TCELL54:IMUX.IMUX.21.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL4 | input | TCELL54:IMUX.IMUX.20.DELAY |
| AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL5 | input | TCELL54:IMUX.IMUX.2.DELAY |
| AXI0_ARADDR_21_NIB1_CLB2PHY_DLYCTL_EN_VTC | input | TCELL54:IMUX.IMUX.4.DELAY |
| AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN0 | input | TCELL45:IMUX.IMUX.31.DELAY |
| AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN1 | input | TCELL45:IMUX.IMUX.30.DELAY |
| AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN2 | input | TCELL45:IMUX.IMUX.7.DELAY |
| AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN3 | input | TCELL45:IMUX.IMUX.29.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL0 | input | TCELL45:IMUX.IMUX.35.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL1 | input | TCELL45:IMUX.IMUX.34.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL2 | input | TCELL45:IMUX.IMUX.9.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL3 | input | TCELL45:IMUX.IMUX.33.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL4 | input | TCELL45:IMUX.IMUX.32.DELAY |
| AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL5 | input | TCELL45:IMUX.IMUX.8.DELAY |
| AXI0_ARADDR_32_NIB2_CLB2PHY_DLYCTL_EN_VTC | input | TCELL45:IMUX.IMUX.10.DELAY |
| AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN0 | input | TCELL43:IMUX.IMUX.11.DELAY |
| AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN1 | input | TCELL43:IMUX.IMUX.37.DELAY |
| AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN2 | input | TCELL43:IMUX.IMUX.36.DELAY |
| AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN3 | input | TCELL43:IMUX.IMUX.10.DELAY |
| AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN0 | input | TCELL58:IMUX.IMUX.35.DELAY |
| AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN1 | input | TCELL58:IMUX.IMUX.34.DELAY |
| AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN2 | input | TCELL58:IMUX.IMUX.9.DELAY |
| AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN3 | input | TCELL58:IMUX.IMUX.33.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL0 | input | TCELL43:IMUX.IMUX.13.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL1 | input | TCELL43:IMUX.IMUX.41.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL2 | input | TCELL43:IMUX.IMUX.40.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL3 | input | TCELL43:IMUX.IMUX.12.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL4 | input | TCELL43:IMUX.IMUX.39.DELAY |
| AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL5 | input | TCELL43:IMUX.IMUX.38.DELAY |
| AXI0_ARADDR_43_NIB3_CLB2PHY_DLYCTL_EN_VTC | input | TCELL43:IMUX.IMUX.42.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL0 | input | TCELL58:IMUX.IMUX.39.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL1 | input | TCELL58:IMUX.IMUX.38.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL2 | input | TCELL58:IMUX.IMUX.11.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL3 | input | TCELL58:IMUX.IMUX.37.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL4 | input | TCELL58:IMUX.IMUX.36.DELAY |
| AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL5 | input | TCELL58:IMUX.IMUX.10.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL45:IMUX.IMUX.41.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL45:IMUX.IMUX.40.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL45:IMUX.IMUX.12.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL45:IMUX.IMUX.39.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL45:IMUX.IMUX.38.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL45:IMUX.IMUX.11.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL45:IMUX.IMUX.37.DELAY |
| AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL45:IMUX.IMUX.36.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL45:IMUX.IMUX.46.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL45:IMUX.IMUX.15.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL45:IMUX.IMUX.45.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL45:IMUX.IMUX.44.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL45:IMUX.IMUX.14.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL45:IMUX.IMUX.43.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL45:IMUX.IMUX.42.DELAY |
| AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL45:IMUX.IMUX.13.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL46:IMUX.IMUX.3.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL46:IMUX.IMUX.21.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL45:IMUX.IMUX.47.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL46:IMUX.IMUX.20.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL46:IMUX.IMUX.2.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL46:IMUX.IMUX.19.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL46:IMUX.IMUX.18.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL46:IMUX.IMUX.1.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL46:IMUX.IMUX.17.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL46:IMUX.IMUX.16.DELAY |
| AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL46:IMUX.IMUX.0.DELAY |
| AXI0_AWADDR_10_NIB0_CLB2PHY_FIFO_RDEN | input | TCELL58:IMUX.IMUX.32.DELAY |
| AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN0 | input | TCELL53:IMUX.IMUX.43.DELAY |
| AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN1 | input | TCELL53:IMUX.IMUX.42.DELAY |
| AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN2 | input | TCELL53:IMUX.IMUX.13.DELAY |
| AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN3 | input | TCELL53:IMUX.IMUX.41.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT0 | input | TCELL53:IMUX.IMUX.47.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT1 | input | TCELL53:IMUX.IMUX.46.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT2 | input | TCELL53:IMUX.IMUX.15.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT3 | input | TCELL53:IMUX.IMUX.45.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT4 | input | TCELL53:IMUX.IMUX.44.DELAY |
| AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT5 | input | TCELL53:IMUX.IMUX.14.DELAY |
| AXI0_AWADDR_21_NIB1_CLB2PHY_FIFO_RDEN | input | TCELL54:IMUX.IMUX.16.DELAY |
| AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN0 | input | TCELL45:IMUX.IMUX.4.DELAY |
| AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN1 | input | TCELL45:IMUX.IMUX.23.DELAY |
| AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN2 | input | TCELL45:IMUX.IMUX.22.DELAY |
| AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN3 | input | TCELL45:IMUX.IMUX.3.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT0 | input | TCELL45:IMUX.IMUX.6.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT1 | input | TCELL45:IMUX.IMUX.27.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT2 | input | TCELL45:IMUX.IMUX.26.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT3 | input | TCELL45:IMUX.IMUX.5.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT4 | input | TCELL45:IMUX.IMUX.25.DELAY |
| AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT5 | input | TCELL45:IMUX.IMUX.24.DELAY |
| AXI0_AWADDR_32_NIB2_CLB2PHY_FIFO_RDEN | input | TCELL45:IMUX.IMUX.28.DELAY |
| AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN0 | input | TCELL43:IMUX.IMUX.30.DELAY |
| AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN1 | input | TCELL43:IMUX.IMUX.7.DELAY |
| AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN2 | input | TCELL43:IMUX.IMUX.29.DELAY |
| AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN3 | input | TCELL43:IMUX.IMUX.28.DELAY |
| AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN0 | input | TCELL58:IMUX.IMUX.6.DELAY |
| AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN1 | input | TCELL58:IMUX.IMUX.27.DELAY |
| AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN2 | input | TCELL58:IMUX.IMUX.26.DELAY |
| AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN3 | input | TCELL58:IMUX.IMUX.5.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT0 | input | TCELL43:IMUX.IMUX.34.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT1 | input | TCELL43:IMUX.IMUX.9.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT2 | input | TCELL43:IMUX.IMUX.33.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT3 | input | TCELL43:IMUX.IMUX.32.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT4 | input | TCELL43:IMUX.IMUX.8.DELAY |
| AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT5 | input | TCELL43:IMUX.IMUX.31.DELAY |
| AXI0_AWADDR_43_NIB3_CLB2PHY_FIFO_RDEN | input | TCELL43:IMUX.IMUX.35.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT0 | input | TCELL58:IMUX.IMUX.8.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT1 | input | TCELL58:IMUX.IMUX.31.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT2 | input | TCELL58:IMUX.IMUX.30.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT3 | input | TCELL58:IMUX.IMUX.7.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT4 | input | TCELL58:IMUX.IMUX.29.DELAY |
| AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT5 | input | TCELL58:IMUX.IMUX.28.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL46:IMUX.IMUX.27.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL46:IMUX.IMUX.26.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL46:IMUX.IMUX.5.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL46:IMUX.IMUX.25.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL46:IMUX.IMUX.24.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL46:IMUX.IMUX.4.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL46:IMUX.IMUX.23.DELAY |
| AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL46:IMUX.IMUX.22.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL46:IMUX.IMUX.32.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL46:IMUX.IMUX.8.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL46:IMUX.IMUX.31.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL46:IMUX.IMUX.30.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL46:IMUX.IMUX.7.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL46:IMUX.IMUX.29.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL46:IMUX.IMUX.28.DELAY |
| AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL46:IMUX.IMUX.6.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL46:IMUX.IMUX.12.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL46:IMUX.IMUX.39.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL46:IMUX.IMUX.33.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL46:IMUX.IMUX.38.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL46:IMUX.IMUX.11.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL46:IMUX.IMUX.37.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL46:IMUX.IMUX.36.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL46:IMUX.IMUX.10.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL46:IMUX.IMUX.35.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL46:IMUX.IMUX.34.DELAY |
| AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL46:IMUX.IMUX.9.DELAY |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_0 | output | TCELL50:OUT.17.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_1 | output | TCELL50:OUT.16.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_2 | output | TCELL50:OUT.18.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_3 | output | TCELL50:OUT.15.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_4 | output | TCELL50:OUT.19.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_5 | output | TCELL50:OUT.14.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_6 | output | TCELL50:OUT.20.TMIN |
| AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_7 | output | TCELL50:OUT.13.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_0 | output | TCELL50:OUT.25.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_1 | output | TCELL50:OUT.24.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_2 | output | TCELL50:OUT.26.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_3 | output | TCELL50:OUT.23.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_4 | output | TCELL50:OUT.27.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_5 | output | TCELL50:OUT.22.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_6 | output | TCELL50:OUT.28.TMIN |
| AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_7 | output | TCELL50:OUT.21.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_0 | output | TCELL51:OUT.4.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_1 | output | TCELL51:OUT.3.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_2 | output | TCELL51:OUT.5.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_3 | output | TCELL50:OUT.31.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_4 | output | TCELL51:OUT.6.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_5 | output | TCELL50:OUT.30.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_6 | output | TCELL51:OUT.7.TMIN |
| AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_7 | output | TCELL50:OUT.29.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_0 | output | TCELL52:OUT.4.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_1 | output | TCELL52:OUT.3.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_2 | output | TCELL52:OUT.5.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_3 | output | TCELL51:OUT.31.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_4 | output | TCELL52:OUT.6.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_5 | output | TCELL51:OUT.30.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_6 | output | TCELL52:OUT.7.TMIN |
| AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_7 | output | TCELL51:OUT.29.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA0 | output | TCELL48:OUT.6.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA1 | output | TCELL48:OUT.5.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA10 | output | TCELL47:OUT.25.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA11 | output | TCELL47:OUT.24.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA12 | output | TCELL47:OUT.23.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA13 | output | TCELL47:OUT.22.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA14 | output | TCELL47:OUT.21.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA15 | output | TCELL47:OUT.20.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA2 | output | TCELL48:OUT.4.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA3 | output | TCELL48:OUT.3.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA4 | output | TCELL47:OUT.31.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA5 | output | TCELL47:OUT.30.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA6 | output | TCELL47:OUT.29.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA7 | output | TCELL47:OUT.28.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA8 | output | TCELL47:OUT.27.TMIN |
| AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA9 | output | TCELL47:OUT.26.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_0 | output | TCELL49:OUT.21.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_1 | output | TCELL49:OUT.22.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_2 | output | TCELL49:OUT.20.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_3 | output | TCELL49:OUT.23.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_4 | output | TCELL49:OUT.19.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_5 | output | TCELL49:OUT.24.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_6 | output | TCELL49:OUT.18.TMIN |
| AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_7 | output | TCELL49:OUT.25.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_0 | output | TCELL49:OUT.13.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_1 | output | TCELL49:OUT.14.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_2 | output | TCELL49:OUT.12.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_3 | output | TCELL49:OUT.15.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_4 | output | TCELL49:OUT.11.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_5 | output | TCELL49:OUT.16.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_6 | output | TCELL49:OUT.10.TMIN |
| AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_7 | output | TCELL49:OUT.17.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA0 | output | TCELL58:OUT.15.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA1 | output | TCELL58:OUT.14.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA10 | output | TCELL58:OUT.5.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA11 | output | TCELL58:OUT.4.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA12 | output | TCELL58:OUT.3.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA13 | output | TCELL58:OUT.2.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA14 | output | TCELL58:OUT.1.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA15 | output | TCELL58:OUT.0.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA2 | output | TCELL58:OUT.13.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA3 | output | TCELL58:OUT.12.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA4 | output | TCELL58:OUT.11.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA5 | output | TCELL58:OUT.10.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA6 | output | TCELL58:OUT.9.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA7 | output | TCELL58:OUT.8.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA8 | output | TCELL58:OUT.7.TMIN |
| AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA9 | output | TCELL58:OUT.6.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_0 | output | TCELL49:OUT.5.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_1 | output | TCELL49:OUT.6.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_2 | output | TCELL49:OUT.4.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_3 | output | TCELL49:OUT.7.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_4 | output | TCELL49:OUT.3.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_5 | output | TCELL49:OUT.8.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_6 | output | TCELL48:OUT.31.TMIN |
| AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_7 | output | TCELL49:OUT.9.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_0 | output | TCELL48:OUT.26.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_1 | output | TCELL48:OUT.27.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_2 | output | TCELL48:OUT.25.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_3 | output | TCELL48:OUT.28.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_4 | output | TCELL48:OUT.24.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_5 | output | TCELL48:OUT.29.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_6 | output | TCELL48:OUT.23.TMIN |
| AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_7 | output | TCELL48:OUT.30.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_0 | output | TCELL48:OUT.18.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_1 | output | TCELL48:OUT.19.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_2 | output | TCELL48:OUT.17.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_3 | output | TCELL48:OUT.20.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_4 | output | TCELL48:OUT.16.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_5 | output | TCELL48:OUT.21.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_6 | output | TCELL48:OUT.15.TMIN |
| AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_7 | output | TCELL48:OUT.22.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_0 | output | TCELL48:OUT.10.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_1 | output | TCELL48:OUT.11.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_2 | output | TCELL48:OUT.9.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_3 | output | TCELL48:OUT.12.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_4 | output | TCELL48:OUT.8.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_5 | output | TCELL48:OUT.13.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_6 | output | TCELL48:OUT.7.TMIN |
| AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_7 | output | TCELL48:OUT.14.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA0 | output | TCELL44:OUT.5.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA1 | output | TCELL44:OUT.4.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA10 | output | TCELL43:OUT.24.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA11 | output | TCELL43:OUT.23.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA12 | output | TCELL43:OUT.22.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA13 | output | TCELL43:OUT.21.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA14 | output | TCELL43:OUT.20.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA15 | output | TCELL43:OUT.19.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA2 | output | TCELL44:OUT.3.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA3 | output | TCELL43:OUT.31.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA4 | output | TCELL43:OUT.30.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA5 | output | TCELL43:OUT.29.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA6 | output | TCELL43:OUT.28.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA7 | output | TCELL43:OUT.27.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA8 | output | TCELL43:OUT.26.TMIN |
| AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA9 | output | TCELL43:OUT.25.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_0 | output | TCELL39:OUT.29.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_1 | output | TCELL39:OUT.28.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_2 | output | TCELL39:OUT.30.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_3 | output | TCELL39:OUT.27.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_4 | output | TCELL39:OUT.31.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_5 | output | TCELL39:OUT.26.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_6 | output | TCELL40:OUT.0.TMIN |
| AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_7 | output | TCELL39:OUT.25.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_0 | output | TCELL40:OUT.5.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_1 | output | TCELL40:OUT.4.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_2 | output | TCELL40:OUT.6.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_3 | output | TCELL40:OUT.3.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_4 | output | TCELL40:OUT.7.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_5 | output | TCELL40:OUT.2.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_6 | output | TCELL40:OUT.8.TMIN |
| AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_7 | output | TCELL40:OUT.1.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_0 | output | TCELL40:OUT.13.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_1 | output | TCELL40:OUT.12.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_2 | output | TCELL40:OUT.14.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_3 | output | TCELL40:OUT.11.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_4 | output | TCELL40:OUT.15.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_5 | output | TCELL40:OUT.10.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_6 | output | TCELL40:OUT.16.TMIN |
| AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_7 | output | TCELL40:OUT.9.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_0 | output | TCELL40:OUT.21.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_1 | output | TCELL40:OUT.20.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_2 | output | TCELL40:OUT.22.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_3 | output | TCELL40:OUT.19.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_4 | output | TCELL40:OUT.23.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_5 | output | TCELL40:OUT.18.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_6 | output | TCELL40:OUT.24.TMIN |
| AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_7 | output | TCELL40:OUT.17.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_0 | output | TCELL59:OUT.27.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_1 | output | TCELL59:OUT.28.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_2 | output | TCELL59:OUT.26.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_3 | output | TCELL59:OUT.29.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_4 | output | TCELL59:OUT.25.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_5 | output | TCELL59:OUT.30.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_6 | output | TCELL59:OUT.24.TMIN |
| AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_7 | output | TCELL59:OUT.31.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_0 | output | TCELL41:OUT.15.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_1 | output | TCELL41:OUT.14.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_2 | output | TCELL41:OUT.16.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_3 | output | TCELL41:OUT.13.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_4 | output | TCELL41:OUT.17.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_5 | output | TCELL41:OUT.12.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_6 | output | TCELL41:OUT.18.TMIN |
| AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_7 | output | TCELL41:OUT.11.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_0 | output | TCELL41:OUT.23.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_1 | output | TCELL41:OUT.22.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_2 | output | TCELL41:OUT.24.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_3 | output | TCELL41:OUT.21.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_4 | output | TCELL41:OUT.25.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_5 | output | TCELL41:OUT.20.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_6 | output | TCELL41:OUT.26.TMIN |
| AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_7 | output | TCELL41:OUT.19.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_0 | output | TCELL59:OUT.19.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_1 | output | TCELL59:OUT.20.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_2 | output | TCELL59:OUT.18.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_3 | output | TCELL59:OUT.21.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_4 | output | TCELL59:OUT.17.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_5 | output | TCELL59:OUT.22.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_6 | output | TCELL59:OUT.16.TMIN |
| AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_7 | output | TCELL59:OUT.23.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_0 | output | TCELL59:OUT.11.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_1 | output | TCELL59:OUT.12.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_2 | output | TCELL59:OUT.10.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_3 | output | TCELL59:OUT.13.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_4 | output | TCELL59:OUT.9.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_5 | output | TCELL59:OUT.14.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_6 | output | TCELL59:OUT.8.TMIN |
| AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_7 | output | TCELL59:OUT.15.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_0 | output | TCELL59:OUT.3.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_1 | output | TCELL59:OUT.4.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_2 | output | TCELL59:OUT.2.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_3 | output | TCELL59:OUT.5.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_4 | output | TCELL59:OUT.1.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_5 | output | TCELL59:OUT.6.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_6 | output | TCELL59:OUT.0.TMIN |
| AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_7 | output | TCELL59:OUT.7.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_0 | output | TCELL58:OUT.27.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_1 | output | TCELL58:OUT.28.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_2 | output | TCELL58:OUT.26.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_3 | output | TCELL58:OUT.29.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_4 | output | TCELL58:OUT.25.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_5 | output | TCELL58:OUT.30.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_6 | output | TCELL58:OUT.24.TMIN |
| AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_7 | output | TCELL58:OUT.31.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_0 | output | TCELL58:OUT.19.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_1 | output | TCELL58:OUT.20.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_2 | output | TCELL58:OUT.18.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_3 | output | TCELL58:OUT.21.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_4 | output | TCELL58:OUT.17.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_5 | output | TCELL58:OUT.22.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_6 | output | TCELL58:OUT.16.TMIN |
| AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_7 | output | TCELL58:OUT.23.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA0 | output | TCELL54:OUT.16.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA1 | output | TCELL54:OUT.15.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA10 | output | TCELL54:OUT.6.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA11 | output | TCELL54:OUT.5.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA12 | output | TCELL54:OUT.4.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA13 | output | TCELL54:OUT.3.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA14 | output | TCELL53:OUT.31.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA15 | output | TCELL53:OUT.30.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA2 | output | TCELL54:OUT.14.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA3 | output | TCELL54:OUT.13.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA4 | output | TCELL54:OUT.12.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA5 | output | TCELL54:OUT.11.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA6 | output | TCELL54:OUT.10.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA7 | output | TCELL54:OUT.9.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA8 | output | TCELL54:OUT.8.TMIN |
| AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA9 | output | TCELL54:OUT.7.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_0 | output | TCELL49:OUT.30.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_1 | output | TCELL49:OUT.29.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_2 | output | TCELL49:OUT.31.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_3 | output | TCELL49:OUT.28.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_4 | output | TCELL50:OUT.3.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_5 | output | TCELL49:OUT.27.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_6 | output | TCELL50:OUT.4.TMIN |
| AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_7 | output | TCELL49:OUT.26.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_0 | output | TCELL50:OUT.9.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_1 | output | TCELL50:OUT.8.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_2 | output | TCELL50:OUT.10.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_3 | output | TCELL50:OUT.7.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_4 | output | TCELL50:OUT.11.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_5 | output | TCELL50:OUT.6.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_6 | output | TCELL50:OUT.12.TMIN |
| AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_7 | output | TCELL50:OUT.5.TMIN |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_0 | input | TCELL50:IMUX.IMUX.13.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_1 | input | TCELL50:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_2 | input | TCELL50:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_3 | input | TCELL50:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_4 | input | TCELL50:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_5 | input | TCELL50:IMUX.IMUX.12.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_6 | input | TCELL50:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_7 | input | TCELL50:IMUX.IMUX.39.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_0 | input | TCELL51:IMUX.IMUX.35.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_1 | input | TCELL51:IMUX.IMUX.34.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_2 | input | TCELL51:IMUX.IMUX.10.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_3 | input | TCELL51:IMUX.IMUX.9.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_4 | input | TCELL51:IMUX.IMUX.36.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_5 | input | TCELL51:IMUX.IMUX.33.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_6 | input | TCELL51:IMUX.IMUX.37.DELAY |
| AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_7 | input | TCELL51:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_0 | input | TCELL51:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_1 | input | TCELL51:IMUX.IMUX.12.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_2 | input | TCELL51:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_3 | input | TCELL51:IMUX.IMUX.39.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_4 | input | TCELL51:IMUX.IMUX.13.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_5 | input | TCELL51:IMUX.IMUX.38.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_6 | input | TCELL51:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_7 | input | TCELL51:IMUX.IMUX.11.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_0 | input | TCELL51:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_1 | input | TCELL51:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_2 | input | TCELL51:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_3 | input | TCELL51:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_4 | input | TCELL51:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_5 | input | TCELL51:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_6 | input | TCELL52:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_7 | input | TCELL51:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA0 | input | TCELL45:IMUX.IMUX.0.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA1 | input | TCELL44:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA10 | input | TCELL44:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA11 | input | TCELL44:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA12 | input | TCELL44:IMUX.IMUX.12.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA13 | input | TCELL44:IMUX.IMUX.39.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA14 | input | TCELL44:IMUX.IMUX.38.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA15 | input | TCELL44:IMUX.IMUX.11.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA2 | input | TCELL44:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA3 | input | TCELL44:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA4 | input | TCELL44:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA5 | input | TCELL44:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA6 | input | TCELL44:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA7 | input | TCELL44:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA8 | input | TCELL44:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA9 | input | TCELL44:IMUX.IMUX.13.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_0 | input | TCELL49:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_1 | input | TCELL49:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_2 | input | TCELL49:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_3 | input | TCELL49:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_4 | input | TCELL49:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_5 | input | TCELL49:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_6 | input | TCELL49:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_7 | input | TCELL49:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_0 | input | TCELL48:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_1 | input | TCELL48:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_2 | input | TCELL48:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_3 | input | TCELL48:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_4 | input | TCELL48:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_5 | input | TCELL48:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_6 | input | TCELL48:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_7 | input | TCELL48:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA0 | input | TCELL55:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA1 | input | TCELL55:IMUX.IMUX.3.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA10 | input | TCELL54:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA11 | input | TCELL54:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA12 | input | TCELL54:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA13 | input | TCELL54:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA14 | input | TCELL54:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA15 | input | TCELL54:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA2 | input | TCELL55:IMUX.IMUX.21.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA3 | input | TCELL55:IMUX.IMUX.20.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA4 | input | TCELL55:IMUX.IMUX.2.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA5 | input | TCELL55:IMUX.IMUX.19.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA6 | input | TCELL55:IMUX.IMUX.18.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA7 | input | TCELL55:IMUX.IMUX.1.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA8 | input | TCELL55:IMUX.IMUX.17.DELAY |
| AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA9 | input | TCELL55:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_0 | input | TCELL48:IMUX.IMUX.38.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_1 | input | TCELL48:IMUX.IMUX.39.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_2 | input | TCELL48:IMUX.IMUX.11.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_3 | input | TCELL48:IMUX.IMUX.12.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_4 | input | TCELL48:IMUX.IMUX.37.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_5 | input | TCELL48:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_6 | input | TCELL48:IMUX.IMUX.36.DELAY |
| AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_7 | input | TCELL48:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_0 | input | TCELL48:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_1 | input | TCELL48:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_2 | input | TCELL48:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_3 | input | TCELL48:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_4 | input | TCELL48:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_5 | input | TCELL48:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_6 | input | TCELL48:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_7 | input | TCELL48:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_0 | input | TCELL48:IMUX.IMUX.4.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_1 | input | TCELL48:IMUX.IMUX.24.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_2 | input | TCELL48:IMUX.IMUX.23.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_3 | input | TCELL48:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_4 | input | TCELL48:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_5 | input | TCELL48:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_6 | input | TCELL48:IMUX.IMUX.3.DELAY |
| AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_7 | input | TCELL48:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_0 | input | TCELL47:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_1 | input | TCELL47:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_2 | input | TCELL47:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_3 | input | TCELL47:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_4 | input | TCELL47:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_5 | input | TCELL48:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_6 | input | TCELL47:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_7 | input | TCELL48:IMUX.IMUX.17.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA0 | input | TCELL43:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA1 | input | TCELL43:IMUX.IMUX.3.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA10 | input | TCELL42:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA11 | input | TCELL42:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA12 | input | TCELL42:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA13 | input | TCELL42:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA14 | input | TCELL42:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA15 | input | TCELL42:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA2 | input | TCELL43:IMUX.IMUX.21.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA3 | input | TCELL43:IMUX.IMUX.20.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA4 | input | TCELL43:IMUX.IMUX.2.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA5 | input | TCELL43:IMUX.IMUX.19.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA6 | input | TCELL43:IMUX.IMUX.18.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA7 | input | TCELL43:IMUX.IMUX.1.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA8 | input | TCELL43:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA9 | input | TCELL43:IMUX.IMUX.0.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_0 | input | TCELL39:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_1 | input | TCELL39:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_2 | input | TCELL39:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_3 | input | TCELL39:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_4 | input | TCELL39:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_5 | input | TCELL39:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_6 | input | TCELL39:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_7 | input | TCELL39:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_0 | input | TCELL39:IMUX.IMUX.34.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_1 | input | TCELL39:IMUX.IMUX.9.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_2 | input | TCELL39:IMUX.IMUX.35.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_3 | input | TCELL39:IMUX.IMUX.33.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_4 | input | TCELL39:IMUX.IMUX.10.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_5 | input | TCELL39:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_6 | input | TCELL39:IMUX.IMUX.36.DELAY |
| AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_7 | input | TCELL39:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_0 | input | TCELL40:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_1 | input | TCELL40:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_2 | input | TCELL40:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_3 | input | TCELL40:IMUX.IMUX.24.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_4 | input | TCELL40:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_5 | input | TCELL40:IMUX.IMUX.4.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_6 | input | TCELL40:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_7 | input | TCELL40:IMUX.IMUX.23.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_0 | input | TCELL41:IMUX.IMUX.19.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_1 | input | TCELL41:IMUX.IMUX.18.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_2 | input | TCELL41:IMUX.IMUX.2.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_3 | input | TCELL41:IMUX.IMUX.1.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_4 | input | TCELL41:IMUX.IMUX.20.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_5 | input | TCELL41:IMUX.IMUX.17.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_6 | input | TCELL41:IMUX.IMUX.21.DELAY |
| AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_7 | input | TCELL41:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_0 | input | TCELL59:IMUX.IMUX.34.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_1 | input | TCELL59:IMUX.IMUX.35.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_2 | input | TCELL59:IMUX.IMUX.9.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_3 | input | TCELL59:IMUX.IMUX.10.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_4 | input | TCELL59:IMUX.IMUX.33.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_5 | input | TCELL59:IMUX.IMUX.36.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_6 | input | TCELL59:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_7 | input | TCELL59:IMUX.IMUX.37.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_0 | input | TCELL41:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_1 | input | TCELL41:IMUX.IMUX.24.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_2 | input | TCELL41:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_3 | input | TCELL41:IMUX.IMUX.4.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_4 | input | TCELL41:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_5 | input | TCELL41:IMUX.IMUX.23.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_6 | input | TCELL41:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_7 | input | TCELL41:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_0 | input | TCELL41:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_1 | input | TCELL41:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_2 | input | TCELL41:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_3 | input | TCELL41:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_4 | input | TCELL41:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_5 | input | TCELL41:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_6 | input | TCELL41:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_7 | input | TCELL41:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_0 | input | TCELL59:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_1 | input | TCELL59:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_2 | input | TCELL59:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_3 | input | TCELL59:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_4 | input | TCELL59:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_5 | input | TCELL59:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_6 | input | TCELL59:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_7 | input | TCELL59:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_0 | input | TCELL59:IMUX.IMUX.23.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_1 | input | TCELL59:IMUX.IMUX.4.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_2 | input | TCELL59:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_3 | input | TCELL59:IMUX.IMUX.24.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_4 | input | TCELL59:IMUX.IMUX.3.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_5 | input | TCELL59:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_6 | input | TCELL59:IMUX.IMUX.21.DELAY |
| AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_7 | input | TCELL59:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_0 | input | TCELL59:IMUX.IMUX.1.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_1 | input | TCELL59:IMUX.IMUX.18.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_2 | input | TCELL58:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_3 | input | TCELL59:IMUX.IMUX.19.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_4 | input | TCELL58:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_5 | input | TCELL59:IMUX.IMUX.2.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_6 | input | TCELL58:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_7 | input | TCELL59:IMUX.IMUX.20.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_0 | input | TCELL58:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_1 | input | TCELL58:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_2 | input | TCELL58:IMUX.IMUX.13.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_3 | input | TCELL58:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_4 | input | TCELL58:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_5 | input | TCELL58:IMUX.IMUX.44.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_6 | input | TCELL58:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_7 | input | TCELL58:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_0 | input | TCELL58:IMUX.IMUX.22.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_1 | input | TCELL58:IMUX.IMUX.23.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_2 | input | TCELL58:IMUX.IMUX.3.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_3 | input | TCELL58:IMUX.IMUX.4.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_4 | input | TCELL58:IMUX.IMUX.21.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_5 | input | TCELL58:IMUX.IMUX.24.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_6 | input | TCELL58:IMUX.IMUX.20.DELAY |
| AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_7 | input | TCELL58:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA0 | input | TCELL53:IMUX.IMUX.35.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA1 | input | TCELL53:IMUX.IMUX.34.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA10 | input | TCELL53:IMUX.IMUX.28.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA11 | input | TCELL53:IMUX.IMUX.6.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA12 | input | TCELL53:IMUX.IMUX.27.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA13 | input | TCELL53:IMUX.IMUX.26.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA14 | input | TCELL53:IMUX.IMUX.5.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA15 | input | TCELL53:IMUX.IMUX.25.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA2 | input | TCELL53:IMUX.IMUX.9.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA3 | input | TCELL53:IMUX.IMUX.33.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA4 | input | TCELL53:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA5 | input | TCELL53:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA6 | input | TCELL53:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA7 | input | TCELL53:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA8 | input | TCELL53:IMUX.IMUX.7.DELAY |
| AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA9 | input | TCELL53:IMUX.IMUX.29.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_0 | input | TCELL49:IMUX.IMUX.33.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_1 | input | TCELL49:IMUX.IMUX.32.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_2 | input | TCELL49:IMUX.IMUX.9.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_3 | input | TCELL49:IMUX.IMUX.8.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_4 | input | TCELL49:IMUX.IMUX.34.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_5 | input | TCELL49:IMUX.IMUX.31.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_6 | input | TCELL49:IMUX.IMUX.35.DELAY |
| AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_7 | input | TCELL49:IMUX.IMUX.30.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_0 | input | TCELL50:IMUX.IMUX.16.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_1 | input | TCELL49:IMUX.IMUX.47.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_2 | input | TCELL50:IMUX.IMUX.17.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_3 | input | TCELL49:IMUX.IMUX.46.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_4 | input | TCELL50:IMUX.IMUX.1.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_5 | input | TCELL49:IMUX.IMUX.15.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_6 | input | TCELL50:IMUX.IMUX.18.DELAY |
| AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_7 | input | TCELL49:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN0 | input | TCELL46:IMUX.IMUX.14.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN1 | input | TCELL46:IMUX.IMUX.43.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN2 | input | TCELL46:IMUX.IMUX.42.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN3 | input | TCELL46:IMUX.IMUX.13.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN4 | input | TCELL46:IMUX.IMUX.41.DELAY |
| AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN5 | input | TCELL46:IMUX.IMUX.40.DELAY |
| AXI0_WDATA_PAR_7_6_NIB2_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL46:IMUX.IMUX.45.DELAY |
| AXI0_WDATA_PAR_7_6_NIB2_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL46:IMUX.IMUX.44.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR0 | input | TCELL53:IMUX.IMUX.40.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR1 | input | TCELL53:IMUX.IMUX.12.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR2 | input | TCELL53:IMUX.IMUX.39.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR3 | input | TCELL53:IMUX.IMUX.38.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR4 | input | TCELL53:IMUX.IMUX.11.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR5 | input | TCELL53:IMUX.IMUX.37.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR6 | input | TCELL53:IMUX.IMUX.36.DELAY |
| AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR7 | input | TCELL53:IMUX.IMUX.10.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR0 | input | TCELL45:IMUX.IMUX.21.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR1 | input | TCELL45:IMUX.IMUX.20.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR2 | input | TCELL45:IMUX.IMUX.2.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR3 | input | TCELL45:IMUX.IMUX.19.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR4 | input | TCELL45:IMUX.IMUX.18.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR5 | input | TCELL45:IMUX.IMUX.1.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR6 | input | TCELL45:IMUX.IMUX.17.DELAY |
| AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR7 | input | TCELL45:IMUX.IMUX.16.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR0 | input | TCELL43:IMUX.IMUX.6.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR1 | input | TCELL43:IMUX.IMUX.27.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR2 | input | TCELL43:IMUX.IMUX.26.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR3 | input | TCELL43:IMUX.IMUX.5.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR4 | input | TCELL43:IMUX.IMUX.25.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR5 | input | TCELL43:IMUX.IMUX.24.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR6 | input | TCELL43:IMUX.IMUX.4.DELAY |
| AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR7 | input | TCELL43:IMUX.IMUX.23.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR0 | input | TCELL55:IMUX.IMUX.6.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR1 | input | TCELL55:IMUX.IMUX.27.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR2 | input | TCELL55:IMUX.IMUX.26.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR3 | input | TCELL55:IMUX.IMUX.5.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR4 | input | TCELL55:IMUX.IMUX.25.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR5 | input | TCELL55:IMUX.IMUX.24.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR6 | input | TCELL55:IMUX.IMUX.4.DELAY |
| AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR7 | input | TCELL55:IMUX.IMUX.23.DELAY |
| AXI1_ARADDR_10_NIB6_CLB2PHY_DLYCTL_EN_VTC | input | TCELL16:IMUX.IMUX.12.DELAY |
| AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN0 | input | TCELL14:IMUX.IMUX.4.DELAY |
| AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN1 | input | TCELL14:IMUX.IMUX.23.DELAY |
| AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN2 | input | TCELL14:IMUX.IMUX.22.DELAY |
| AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN3 | input | TCELL14:IMUX.IMUX.3.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL0 | input | TCELL14:IMUX.IMUX.6.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL1 | input | TCELL14:IMUX.IMUX.27.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL2 | input | TCELL14:IMUX.IMUX.26.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL3 | input | TCELL14:IMUX.IMUX.5.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL4 | input | TCELL14:IMUX.IMUX.25.DELAY |
| AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL5 | input | TCELL14:IMUX.IMUX.24.DELAY |
| AXI1_ARADDR_21_NIB7_CLB2PHY_DLYCTL_EN_VTC | input | TCELL14:IMUX.IMUX.28.DELAY |
| AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN0 | input | TCELL5:IMUX.IMUX.36.DELAY |
| AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN1 | input | TCELL5:IMUX.IMUX.10.DELAY |
| AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN2 | input | TCELL5:IMUX.IMUX.35.DELAY |
| AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN3 | input | TCELL5:IMUX.IMUX.34.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL0 | input | TCELL5:IMUX.IMUX.40.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL1 | input | TCELL5:IMUX.IMUX.12.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL2 | input | TCELL5:IMUX.IMUX.39.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL3 | input | TCELL5:IMUX.IMUX.38.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL4 | input | TCELL5:IMUX.IMUX.11.DELAY |
| AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL5 | input | TCELL5:IMUX.IMUX.37.DELAY |
| AXI1_ARADDR_32_NIB8_CLB2PHY_DLYCTL_EN_VTC | input | TCELL5:IMUX.IMUX.41.DELAY |
| AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN0 | input | TCELL2:IMUX.IMUX.36.DELAY |
| AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN1 | input | TCELL2:IMUX.IMUX.10.DELAY |
| AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN2 | input | TCELL2:IMUX.IMUX.35.DELAY |
| AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN3 | input | TCELL2:IMUX.IMUX.34.DELAY |
| AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN0 | input | TCELL16:IMUX.IMUX.35.DELAY |
| AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN1 | input | TCELL16:IMUX.IMUX.34.DELAY |
| AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN2 | input | TCELL16:IMUX.IMUX.9.DELAY |
| AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN3 | input | TCELL16:IMUX.IMUX.33.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL0 | input | TCELL2:IMUX.IMUX.40.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL1 | input | TCELL2:IMUX.IMUX.12.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL2 | input | TCELL2:IMUX.IMUX.39.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL3 | input | TCELL2:IMUX.IMUX.38.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL4 | input | TCELL2:IMUX.IMUX.11.DELAY |
| AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL5 | input | TCELL2:IMUX.IMUX.37.DELAY |
| AXI1_ARADDR_43_NIB9_CLB2PHY_DLYCTL_EN_VTC | input | TCELL2:IMUX.IMUX.41.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL0 | input | TCELL16:IMUX.IMUX.39.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL1 | input | TCELL16:IMUX.IMUX.38.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL2 | input | TCELL16:IMUX.IMUX.11.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL3 | input | TCELL16:IMUX.IMUX.37.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL4 | input | TCELL16:IMUX.IMUX.36.DELAY |
| AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL5 | input | TCELL16:IMUX.IMUX.10.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL16:IMUX.IMUX.45.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL16:IMUX.IMUX.44.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL16:IMUX.IMUX.14.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL16:IMUX.IMUX.43.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL16:IMUX.IMUX.42.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL16:IMUX.IMUX.13.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL16:IMUX.IMUX.41.DELAY |
| AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL16:IMUX.IMUX.40.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL17:IMUX.IMUX.18.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL17:IMUX.IMUX.1.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL17:IMUX.IMUX.17.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL17:IMUX.IMUX.16.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL17:IMUX.IMUX.0.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL16:IMUX.IMUX.47.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL16:IMUX.IMUX.46.DELAY |
| AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL16:IMUX.IMUX.15.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL17:IMUX.IMUX.5.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL17:IMUX.IMUX.25.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL17:IMUX.IMUX.19.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL17:IMUX.IMUX.24.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL17:IMUX.IMUX.4.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL17:IMUX.IMUX.23.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL17:IMUX.IMUX.22.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL17:IMUX.IMUX.3.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL17:IMUX.IMUX.21.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL17:IMUX.IMUX.20.DELAY |
| AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL17:IMUX.IMUX.2.DELAY |
| AXI1_AWADDR_10_NIB6_CLB2PHY_FIFO_RDEN | input | TCELL16:IMUX.IMUX.32.DELAY |
| AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN0 | input | TCELL14:IMUX.IMUX.16.DELAY |
| AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN1 | input | TCELL14:IMUX.IMUX.0.DELAY |
| AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN2 | input | TCELL13:IMUX.IMUX.47.DELAY |
| AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN3 | input | TCELL13:IMUX.IMUX.46.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT0 | input | TCELL14:IMUX.IMUX.20.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT1 | input | TCELL14:IMUX.IMUX.2.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT2 | input | TCELL14:IMUX.IMUX.19.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT3 | input | TCELL14:IMUX.IMUX.18.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT4 | input | TCELL14:IMUX.IMUX.1.DELAY |
| AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT5 | input | TCELL14:IMUX.IMUX.17.DELAY |
| AXI1_AWADDR_21_NIB7_CLB2PHY_FIFO_RDEN | input | TCELL14:IMUX.IMUX.21.DELAY |
| AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN0 | input | TCELL5:IMUX.IMUX.29.DELAY |
| AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN1 | input | TCELL5:IMUX.IMUX.28.DELAY |
| AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN2 | input | TCELL5:IMUX.IMUX.6.DELAY |
| AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN3 | input | TCELL5:IMUX.IMUX.27.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT0 | input | TCELL5:IMUX.IMUX.33.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT1 | input | TCELL5:IMUX.IMUX.32.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT2 | input | TCELL5:IMUX.IMUX.8.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT3 | input | TCELL5:IMUX.IMUX.31.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT4 | input | TCELL5:IMUX.IMUX.30.DELAY |
| AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT5 | input | TCELL5:IMUX.IMUX.7.DELAY |
| AXI1_AWADDR_32_NIB8_CLB2PHY_FIFO_RDEN | input | TCELL5:IMUX.IMUX.9.DELAY |
| AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN0 | input | TCELL2:IMUX.IMUX.29.DELAY |
| AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN1 | input | TCELL2:IMUX.IMUX.28.DELAY |
| AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN2 | input | TCELL2:IMUX.IMUX.6.DELAY |
| AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN3 | input | TCELL2:IMUX.IMUX.27.DELAY |
| AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN0 | input | TCELL16:IMUX.IMUX.27.DELAY |
| AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN1 | input | TCELL16:IMUX.IMUX.26.DELAY |
| AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN2 | input | TCELL16:IMUX.IMUX.5.DELAY |
| AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN3 | input | TCELL16:IMUX.IMUX.25.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT0 | input | TCELL2:IMUX.IMUX.33.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT1 | input | TCELL2:IMUX.IMUX.32.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT2 | input | TCELL2:IMUX.IMUX.8.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT3 | input | TCELL2:IMUX.IMUX.31.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT4 | input | TCELL2:IMUX.IMUX.30.DELAY |
| AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT5 | input | TCELL2:IMUX.IMUX.7.DELAY |
| AXI1_AWADDR_43_NIB9_CLB2PHY_FIFO_RDEN | input | TCELL2:IMUX.IMUX.9.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT0 | input | TCELL16:IMUX.IMUX.31.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT1 | input | TCELL16:IMUX.IMUX.30.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT2 | input | TCELL16:IMUX.IMUX.7.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT3 | input | TCELL16:IMUX.IMUX.29.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT4 | input | TCELL16:IMUX.IMUX.28.DELAY |
| AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT5 | input | TCELL16:IMUX.IMUX.6.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL17:IMUX.IMUX.31.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL17:IMUX.IMUX.30.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL17:IMUX.IMUX.7.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL17:IMUX.IMUX.29.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL17:IMUX.IMUX.28.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL17:IMUX.IMUX.6.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL17:IMUX.IMUX.27.DELAY |
| AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL17:IMUX.IMUX.26.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL17:IMUX.IMUX.36.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL17:IMUX.IMUX.10.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL17:IMUX.IMUX.35.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL17:IMUX.IMUX.34.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL17:IMUX.IMUX.9.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL17:IMUX.IMUX.33.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL17:IMUX.IMUX.32.DELAY |
| AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL17:IMUX.IMUX.8.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL17:IMUX.IMUX.14.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL17:IMUX.IMUX.43.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL17:IMUX.IMUX.37.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL17:IMUX.IMUX.42.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL17:IMUX.IMUX.13.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL17:IMUX.IMUX.41.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL17:IMUX.IMUX.40.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL17:IMUX.IMUX.12.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL17:IMUX.IMUX.39.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL17:IMUX.IMUX.38.DELAY |
| AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL17:IMUX.IMUX.11.DELAY |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_0 | output | TCELL10:OUT.9.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_1 | output | TCELL10:OUT.8.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_2 | output | TCELL10:OUT.10.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_3 | output | TCELL10:OUT.7.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_4 | output | TCELL10:OUT.11.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_5 | output | TCELL10:OUT.6.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_6 | output | TCELL10:OUT.12.TMIN |
| AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_7 | output | TCELL10:OUT.5.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_0 | output | TCELL10:OUT.17.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_1 | output | TCELL10:OUT.16.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_2 | output | TCELL10:OUT.18.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_3 | output | TCELL10:OUT.15.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_4 | output | TCELL10:OUT.19.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_5 | output | TCELL10:OUT.14.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_6 | output | TCELL10:OUT.20.TMIN |
| AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_7 | output | TCELL10:OUT.13.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_0 | output | TCELL10:OUT.25.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_1 | output | TCELL10:OUT.24.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_2 | output | TCELL10:OUT.26.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_3 | output | TCELL10:OUT.23.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_4 | output | TCELL10:OUT.27.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_5 | output | TCELL10:OUT.22.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_6 | output | TCELL10:OUT.28.TMIN |
| AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_7 | output | TCELL10:OUT.21.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_0 | output | TCELL11:OUT.4.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_1 | output | TCELL11:OUT.3.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_2 | output | TCELL11:OUT.5.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_3 | output | TCELL10:OUT.31.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_4 | output | TCELL11:OUT.6.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_5 | output | TCELL10:OUT.30.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_6 | output | TCELL11:OUT.7.TMIN |
| AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_7 | output | TCELL10:OUT.29.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA0 | output | TCELL7:OUT.27.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA1 | output | TCELL7:OUT.26.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA10 | output | TCELL7:OUT.17.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA11 | output | TCELL7:OUT.16.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA12 | output | TCELL7:OUT.15.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA13 | output | TCELL7:OUT.14.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA14 | output | TCELL7:OUT.13.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA15 | output | TCELL7:OUT.12.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA2 | output | TCELL7:OUT.25.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA3 | output | TCELL7:OUT.24.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA4 | output | TCELL7:OUT.23.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA5 | output | TCELL7:OUT.22.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA6 | output | TCELL7:OUT.21.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA7 | output | TCELL7:OUT.20.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA8 | output | TCELL7:OUT.19.TMIN |
| AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA9 | output | TCELL7:OUT.18.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_0 | output | TCELL9:OUT.13.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_1 | output | TCELL9:OUT.14.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_2 | output | TCELL9:OUT.12.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_3 | output | TCELL9:OUT.15.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_4 | output | TCELL9:OUT.11.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_5 | output | TCELL9:OUT.16.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_6 | output | TCELL9:OUT.10.TMIN |
| AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_7 | output | TCELL9:OUT.17.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_0 | output | TCELL9:OUT.5.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_1 | output | TCELL9:OUT.6.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_2 | output | TCELL9:OUT.4.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_3 | output | TCELL9:OUT.7.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_4 | output | TCELL9:OUT.3.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_5 | output | TCELL9:OUT.8.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_6 | output | TCELL8:OUT.31.TMIN |
| AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_7 | output | TCELL9:OUT.9.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA0 | output | TCELL19:OUT.19.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA1 | output | TCELL19:OUT.18.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA10 | output | TCELL19:OUT.9.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA11 | output | TCELL19:OUT.8.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA12 | output | TCELL19:OUT.7.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA13 | output | TCELL19:OUT.6.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA14 | output | TCELL19:OUT.5.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA15 | output | TCELL19:OUT.4.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA2 | output | TCELL19:OUT.17.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA3 | output | TCELL19:OUT.16.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA4 | output | TCELL19:OUT.15.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA5 | output | TCELL19:OUT.14.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA6 | output | TCELL19:OUT.13.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA7 | output | TCELL19:OUT.12.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA8 | output | TCELL19:OUT.11.TMIN |
| AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA9 | output | TCELL19:OUT.10.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_0 | output | TCELL8:OUT.26.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_1 | output | TCELL8:OUT.27.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_2 | output | TCELL8:OUT.25.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_3 | output | TCELL8:OUT.28.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_4 | output | TCELL8:OUT.24.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_5 | output | TCELL8:OUT.29.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_6 | output | TCELL8:OUT.23.TMIN |
| AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_7 | output | TCELL8:OUT.30.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_0 | output | TCELL8:OUT.18.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_1 | output | TCELL8:OUT.19.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_2 | output | TCELL8:OUT.17.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_3 | output | TCELL8:OUT.20.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_4 | output | TCELL8:OUT.16.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_5 | output | TCELL8:OUT.21.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_6 | output | TCELL8:OUT.15.TMIN |
| AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_7 | output | TCELL8:OUT.22.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_0 | output | TCELL8:OUT.10.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_1 | output | TCELL8:OUT.11.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_2 | output | TCELL8:OUT.9.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_3 | output | TCELL8:OUT.12.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_4 | output | TCELL8:OUT.8.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_5 | output | TCELL8:OUT.13.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_6 | output | TCELL8:OUT.7.TMIN |
| AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_7 | output | TCELL8:OUT.14.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_0 | output | TCELL7:OUT.31.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_1 | output | TCELL8:OUT.3.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_2 | output | TCELL7:OUT.30.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_3 | output | TCELL8:OUT.4.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_4 | output | TCELL7:OUT.29.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_5 | output | TCELL8:OUT.5.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_6 | output | TCELL7:OUT.28.TMIN |
| AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_7 | output | TCELL8:OUT.6.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA0 | output | TCELL4:OUT.26.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA1 | output | TCELL4:OUT.25.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA10 | output | TCELL4:OUT.16.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA11 | output | TCELL4:OUT.15.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA12 | output | TCELL4:OUT.14.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA13 | output | TCELL4:OUT.13.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA14 | output | TCELL4:OUT.12.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA15 | output | TCELL4:OUT.11.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA2 | output | TCELL4:OUT.24.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA3 | output | TCELL4:OUT.23.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA4 | output | TCELL4:OUT.22.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA5 | output | TCELL4:OUT.21.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA6 | output | TCELL4:OUT.20.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA7 | output | TCELL4:OUT.19.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA8 | output | TCELL4:OUT.18.TMIN |
| AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA9 | output | TCELL4:OUT.17.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_0 | output | TCELL0:OUT.15.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_1 | output | TCELL0:OUT.14.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_2 | output | TCELL0:OUT.16.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_3 | output | TCELL0:OUT.13.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_4 | output | TCELL0:OUT.17.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_5 | output | TCELL0:OUT.12.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_6 | output | TCELL0:OUT.18.TMIN |
| AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_7 | output | TCELL0:OUT.11.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_0 | output | TCELL0:OUT.23.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_1 | output | TCELL0:OUT.22.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_2 | output | TCELL0:OUT.24.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_3 | output | TCELL0:OUT.21.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_4 | output | TCELL0:OUT.25.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_5 | output | TCELL0:OUT.20.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_6 | output | TCELL0:OUT.26.TMIN |
| AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_7 | output | TCELL0:OUT.19.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_0 | output | TCELL0:OUT.31.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_1 | output | TCELL0:OUT.30.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_2 | output | TCELL1:OUT.0.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_3 | output | TCELL0:OUT.29.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_4 | output | TCELL1:OUT.1.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_5 | output | TCELL0:OUT.28.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_6 | output | TCELL1:OUT.2.TMIN |
| AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_7 | output | TCELL0:OUT.27.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_0 | output | TCELL1:OUT.7.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_1 | output | TCELL1:OUT.6.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_2 | output | TCELL1:OUT.8.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_3 | output | TCELL1:OUT.5.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_4 | output | TCELL1:OUT.9.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_5 | output | TCELL1:OUT.4.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_6 | output | TCELL1:OUT.10.TMIN |
| AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_7 | output | TCELL1:OUT.3.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_0 | output | TCELL21:OUT.15.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_1 | output | TCELL21:OUT.16.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_2 | output | TCELL21:OUT.14.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_3 | output | TCELL21:OUT.17.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_4 | output | TCELL21:OUT.13.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_5 | output | TCELL21:OUT.18.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_6 | output | TCELL21:OUT.12.TMIN |
| AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_7 | output | TCELL21:OUT.19.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_0 | output | TCELL1:OUT.15.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_1 | output | TCELL1:OUT.14.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_2 | output | TCELL1:OUT.16.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_3 | output | TCELL1:OUT.13.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_4 | output | TCELL1:OUT.17.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_5 | output | TCELL1:OUT.12.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_6 | output | TCELL1:OUT.18.TMIN |
| AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_7 | output | TCELL1:OUT.11.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_0 | output | TCELL1:OUT.23.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_1 | output | TCELL1:OUT.22.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_2 | output | TCELL1:OUT.24.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_3 | output | TCELL1:OUT.21.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_4 | output | TCELL1:OUT.25.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_5 | output | TCELL1:OUT.20.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_6 | output | TCELL1:OUT.26.TMIN |
| AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_7 | output | TCELL1:OUT.19.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_0 | output | TCELL21:OUT.5.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_1 | output | TCELL21:OUT.6.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_2 | output | TCELL21:OUT.4.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_3 | output | TCELL21:OUT.7.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_4 | output | TCELL21:OUT.3.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_5 | output | TCELL21:OUT.8.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_6 | output | TCELL20:OUT.31.TMIN |
| AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_7 | output | TCELL21:OUT.9.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_0 | output | TCELL20:OUT.26.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_1 | output | TCELL20:OUT.27.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_2 | output | TCELL20:OUT.25.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_3 | output | TCELL20:OUT.28.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_4 | output | TCELL20:OUT.24.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_5 | output | TCELL20:OUT.29.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_6 | output | TCELL20:OUT.23.TMIN |
| AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_7 | output | TCELL20:OUT.30.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_0 | output | TCELL20:OUT.18.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_1 | output | TCELL20:OUT.19.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_2 | output | TCELL20:OUT.17.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_3 | output | TCELL20:OUT.20.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_4 | output | TCELL20:OUT.16.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_5 | output | TCELL20:OUT.21.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_6 | output | TCELL20:OUT.15.TMIN |
| AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_7 | output | TCELL20:OUT.22.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_0 | output | TCELL20:OUT.10.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_1 | output | TCELL20:OUT.11.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_2 | output | TCELL20:OUT.9.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_3 | output | TCELL20:OUT.12.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_4 | output | TCELL20:OUT.8.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_5 | output | TCELL20:OUT.13.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_6 | output | TCELL20:OUT.7.TMIN |
| AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_7 | output | TCELL20:OUT.14.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_0 | output | TCELL19:OUT.31.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_1 | output | TCELL20:OUT.3.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_2 | output | TCELL19:OUT.30.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_3 | output | TCELL20:OUT.4.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_4 | output | TCELL19:OUT.29.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_5 | output | TCELL20:OUT.5.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_6 | output | TCELL19:OUT.28.TMIN |
| AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_7 | output | TCELL20:OUT.6.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA0 | output | TCELL14:OUT.8.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA1 | output | TCELL14:OUT.7.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA10 | output | TCELL13:OUT.28.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA11 | output | TCELL13:OUT.27.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA12 | output | TCELL13:OUT.26.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA13 | output | TCELL13:OUT.25.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA14 | output | TCELL13:OUT.24.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA15 | output | TCELL13:OUT.22.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA2 | output | TCELL14:OUT.5.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA3 | output | TCELL14:OUT.4.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA4 | output | TCELL14:OUT.3.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA5 | output | TCELL14:OUT.2.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA6 | output | TCELL14:OUT.1.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA7 | output | TCELL14:OUT.0.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA8 | output | TCELL13:OUT.30.TMIN |
| AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA9 | output | TCELL13:OUT.29.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_0 | output | TCELL9:OUT.22.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_1 | output | TCELL9:OUT.21.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_2 | output | TCELL9:OUT.23.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_3 | output | TCELL9:OUT.20.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_4 | output | TCELL9:OUT.24.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_5 | output | TCELL9:OUT.19.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_6 | output | TCELL9:OUT.25.TMIN |
| AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_7 | output | TCELL9:OUT.18.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_0 | output | TCELL9:OUT.30.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_1 | output | TCELL9:OUT.29.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_2 | output | TCELL9:OUT.31.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_3 | output | TCELL9:OUT.28.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_4 | output | TCELL10:OUT.3.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_5 | output | TCELL9:OUT.27.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_6 | output | TCELL10:OUT.4.TMIN |
| AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_7 | output | TCELL9:OUT.26.TMIN |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_0 | input | TCELL10:IMUX.IMUX.31.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_1 | input | TCELL10:IMUX.IMUX.30.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_2 | input | TCELL10:IMUX.IMUX.8.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_3 | input | TCELL10:IMUX.IMUX.7.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_4 | input | TCELL10:IMUX.IMUX.32.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_5 | input | TCELL10:IMUX.IMUX.29.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_6 | input | TCELL10:IMUX.IMUX.33.DELAY |
| AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_7 | input | TCELL10:IMUX.IMUX.28.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_0 | input | TCELL11:IMUX.IMUX.24.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_1 | input | TCELL11:IMUX.IMUX.4.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_2 | input | TCELL11:IMUX.IMUX.25.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_3 | input | TCELL11:IMUX.IMUX.23.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_4 | input | TCELL11:IMUX.IMUX.5.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_5 | input | TCELL11:IMUX.IMUX.22.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_6 | input | TCELL11:IMUX.IMUX.26.DELAY |
| AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_7 | input | TCELL11:IMUX.IMUX.3.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_0 | input | TCELL12:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_1 | input | TCELL11:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_2 | input | TCELL12:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_3 | input | TCELL11:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_4 | input | TCELL12:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_5 | input | TCELL11:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_6 | input | TCELL12:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_7 | input | TCELL11:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_0 | input | TCELL12:IMUX.IMUX.40.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_1 | input | TCELL12:IMUX.IMUX.12.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_2 | input | TCELL12:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_3 | input | TCELL12:IMUX.IMUX.39.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_4 | input | TCELL12:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_5 | input | TCELL12:IMUX.IMUX.38.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_6 | input | TCELL12:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_7 | input | TCELL12:IMUX.IMUX.11.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA0 | input | TCELL5:IMUX.IMUX.21.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA1 | input | TCELL5:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA10 | input | TCELL4:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA11 | input | TCELL4:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA12 | input | TCELL4:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA13 | input | TCELL4:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA14 | input | TCELL4:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA15 | input | TCELL4:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA2 | input | TCELL5:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA3 | input | TCELL5:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA4 | input | TCELL5:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA5 | input | TCELL5:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA6 | input | TCELL5:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA7 | input | TCELL5:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA8 | input | TCELL5:IMUX.IMUX.0.DELAY |
| AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA9 | input | TCELL4:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_0 | input | TCELL9:IMUX.IMUX.29.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_1 | input | TCELL9:IMUX.IMUX.7.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_2 | input | TCELL9:IMUX.IMUX.28.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_3 | input | TCELL9:IMUX.IMUX.30.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_4 | input | TCELL9:IMUX.IMUX.6.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_5 | input | TCELL9:IMUX.IMUX.31.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_6 | input | TCELL9:IMUX.IMUX.27.DELAY |
| AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_7 | input | TCELL9:IMUX.IMUX.8.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_0 | input | TCELL8:IMUX.IMUX.8.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_1 | input | TCELL8:IMUX.IMUX.32.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_2 | input | TCELL8:IMUX.IMUX.31.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_3 | input | TCELL8:IMUX.IMUX.33.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_4 | input | TCELL8:IMUX.IMUX.30.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_5 | input | TCELL8:IMUX.IMUX.9.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_6 | input | TCELL8:IMUX.IMUX.7.DELAY |
| AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_7 | input | TCELL8:IMUX.IMUX.34.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA0 | input | TCELL16:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA1 | input | TCELL16:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA10 | input | TCELL15:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA11 | input | TCELL15:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA12 | input | TCELL15:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA13 | input | TCELL15:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA14 | input | TCELL15:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA15 | input | TCELL15:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA2 | input | TCELL16:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA3 | input | TCELL16:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA4 | input | TCELL16:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA5 | input | TCELL16:IMUX.IMUX.0.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA6 | input | TCELL15:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA7 | input | TCELL15:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA8 | input | TCELL15:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA9 | input | TCELL15:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_0 | input | TCELL8:IMUX.IMUX.26.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_1 | input | TCELL8:IMUX.IMUX.27.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_2 | input | TCELL8:IMUX.IMUX.5.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_3 | input | TCELL8:IMUX.IMUX.6.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_4 | input | TCELL8:IMUX.IMUX.25.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_5 | input | TCELL8:IMUX.IMUX.28.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_6 | input | TCELL8:IMUX.IMUX.24.DELAY |
| AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_7 | input | TCELL8:IMUX.IMUX.29.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_0 | input | TCELL8:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_1 | input | TCELL8:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_2 | input | TCELL8:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_3 | input | TCELL8:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_4 | input | TCELL7:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_5 | input | TCELL8:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_6 | input | TCELL7:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_7 | input | TCELL8:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_0 | input | TCELL7:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_1 | input | TCELL7:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_2 | input | TCELL7:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_3 | input | TCELL7:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_4 | input | TCELL7:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_5 | input | TCELL7:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_6 | input | TCELL7:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_7 | input | TCELL7:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_0 | input | TCELL7:IMUX.IMUX.34.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_1 | input | TCELL7:IMUX.IMUX.35.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_2 | input | TCELL7:IMUX.IMUX.9.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_3 | input | TCELL7:IMUX.IMUX.10.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_4 | input | TCELL7:IMUX.IMUX.33.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_5 | input | TCELL7:IMUX.IMUX.36.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_6 | input | TCELL7:IMUX.IMUX.32.DELAY |
| AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_7 | input | TCELL7:IMUX.IMUX.37.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA0 | input | TCELL2:IMUX.IMUX.21.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA1 | input | TCELL2:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA10 | input | TCELL1:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA11 | input | TCELL1:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA12 | input | TCELL1:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA13 | input | TCELL1:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA14 | input | TCELL1:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA15 | input | TCELL1:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA2 | input | TCELL2:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA3 | input | TCELL2:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA4 | input | TCELL2:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA5 | input | TCELL2:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA6 | input | TCELL2:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA7 | input | TCELL2:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA8 | input | TCELL2:IMUX.IMUX.0.DELAY |
| AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA9 | input | TCELL1:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_0 | input | TCELL0:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_1 | input | TCELL0:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_2 | input | TCELL0:IMUX.IMUX.21.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_3 | input | TCELL0:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_4 | input | TCELL0:IMUX.IMUX.3.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_5 | input | TCELL0:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_6 | input | TCELL0:IMUX.IMUX.22.DELAY |
| AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_7 | input | TCELL0:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_0 | input | TCELL0:IMUX.IMUX.5.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_1 | input | TCELL0:IMUX.IMUX.25.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_2 | input | TCELL0:IMUX.IMUX.26.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_3 | input | TCELL0:IMUX.IMUX.24.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_4 | input | TCELL0:IMUX.IMUX.27.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_5 | input | TCELL0:IMUX.IMUX.4.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_6 | input | TCELL0:IMUX.IMUX.6.DELAY |
| AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_7 | input | TCELL0:IMUX.IMUX.23.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_0 | input | TCELL0:IMUX.IMUX.8.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_1 | input | TCELL0:IMUX.IMUX.31.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_2 | input | TCELL0:IMUX.IMUX.32.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_3 | input | TCELL0:IMUX.IMUX.30.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_4 | input | TCELL0:IMUX.IMUX.33.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_5 | input | TCELL0:IMUX.IMUX.7.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_6 | input | TCELL0:IMUX.IMUX.9.DELAY |
| AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_7 | input | TCELL0:IMUX.IMUX.29.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_0 | input | TCELL0:IMUX.IMUX.37.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_1 | input | TCELL0:IMUX.IMUX.36.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_2 | input | TCELL0:IMUX.IMUX.11.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_3 | input | TCELL0:IMUX.IMUX.10.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_4 | input | TCELL0:IMUX.IMUX.38.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_5 | input | TCELL0:IMUX.IMUX.35.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_6 | input | TCELL0:IMUX.IMUX.39.DELAY |
| AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_7 | input | TCELL0:IMUX.IMUX.34.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_0 | input | TCELL21:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_1 | input | TCELL21:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_2 | input | TCELL21:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_3 | input | TCELL21:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_4 | input | TCELL21:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_5 | input | TCELL21:IMUX.IMUX.21.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_6 | input | TCELL21:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_7 | input | TCELL21:IMUX.IMUX.3.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_0 | input | TCELL0:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_1 | input | TCELL0:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_2 | input | TCELL0:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_3 | input | TCELL0:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_4 | input | TCELL0:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_5 | input | TCELL0:IMUX.IMUX.40.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_6 | input | TCELL0:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_7 | input | TCELL0:IMUX.IMUX.12.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_0 | input | TCELL1:IMUX.IMUX.18.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_1 | input | TCELL1:IMUX.IMUX.1.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_2 | input | TCELL1:IMUX.IMUX.19.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_3 | input | TCELL1:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_4 | input | TCELL1:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_5 | input | TCELL1:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_6 | input | TCELL1:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_7 | input | TCELL0:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_0 | input | TCELL20:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_1 | input | TCELL20:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_2 | input | TCELL20:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_3 | input | TCELL20:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_4 | input | TCELL20:IMUX.IMUX.40.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_5 | input | TCELL20:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_6 | input | TCELL20:IMUX.IMUX.12.DELAY |
| AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_7 | input | TCELL20:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_0 | input | TCELL20:IMUX.IMUX.36.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_1 | input | TCELL20:IMUX.IMUX.37.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_2 | input | TCELL20:IMUX.IMUX.10.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_3 | input | TCELL20:IMUX.IMUX.11.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_4 | input | TCELL20:IMUX.IMUX.35.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_5 | input | TCELL20:IMUX.IMUX.38.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_6 | input | TCELL20:IMUX.IMUX.34.DELAY |
| AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_7 | input | TCELL20:IMUX.IMUX.39.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_0 | input | TCELL20:IMUX.IMUX.27.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_1 | input | TCELL20:IMUX.IMUX.6.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_2 | input | TCELL20:IMUX.IMUX.26.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_3 | input | TCELL20:IMUX.IMUX.28.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_4 | input | TCELL20:IMUX.IMUX.5.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_5 | input | TCELL20:IMUX.IMUX.29.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_6 | input | TCELL20:IMUX.IMUX.25.DELAY |
| AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_7 | input | TCELL20:IMUX.IMUX.7.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_0 | input | TCELL20:IMUX.IMUX.3.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_1 | input | TCELL20:IMUX.IMUX.22.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_2 | input | TCELL20:IMUX.IMUX.21.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_3 | input | TCELL20:IMUX.IMUX.23.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_4 | input | TCELL20:IMUX.IMUX.20.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_5 | input | TCELL20:IMUX.IMUX.4.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_6 | input | TCELL20:IMUX.IMUX.2.DELAY |
| AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_7 | input | TCELL20:IMUX.IMUX.24.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_0 | input | TCELL19:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_1 | input | TCELL19:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_2 | input | TCELL19:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_3 | input | TCELL19:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_4 | input | TCELL19:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_5 | input | TCELL19:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_6 | input | TCELL19:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_7 | input | TCELL20:IMUX.IMUX.16.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA0 | input | TCELL13:IMUX.IMUX.40.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA1 | input | TCELL13:IMUX.IMUX.12.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA10 | input | TCELL13:IMUX.IMUX.9.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA11 | input | TCELL13:IMUX.IMUX.33.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA12 | input | TCELL13:IMUX.IMUX.32.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA13 | input | TCELL13:IMUX.IMUX.8.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA14 | input | TCELL13:IMUX.IMUX.31.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA15 | input | TCELL13:IMUX.IMUX.30.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA2 | input | TCELL13:IMUX.IMUX.39.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA3 | input | TCELL13:IMUX.IMUX.38.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA4 | input | TCELL13:IMUX.IMUX.11.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA5 | input | TCELL13:IMUX.IMUX.37.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA6 | input | TCELL13:IMUX.IMUX.36.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA7 | input | TCELL13:IMUX.IMUX.10.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA8 | input | TCELL13:IMUX.IMUX.35.DELAY |
| AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA9 | input | TCELL13:IMUX.IMUX.34.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_0 | input | TCELL9:IMUX.IMUX.38.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_1 | input | TCELL9:IMUX.IMUX.11.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_2 | input | TCELL9:IMUX.IMUX.39.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_3 | input | TCELL9:IMUX.IMUX.37.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_4 | input | TCELL9:IMUX.IMUX.12.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_5 | input | TCELL9:IMUX.IMUX.36.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_6 | input | TCELL9:IMUX.IMUX.40.DELAY |
| AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_7 | input | TCELL9:IMUX.IMUX.10.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_0 | input | TCELL9:IMUX.IMUX.14.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_1 | input | TCELL9:IMUX.IMUX.43.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_2 | input | TCELL9:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_3 | input | TCELL9:IMUX.IMUX.42.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_4 | input | TCELL9:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_5 | input | TCELL9:IMUX.IMUX.13.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_6 | input | TCELL9:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_7 | input | TCELL9:IMUX.IMUX.41.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN0 | input | TCELL18:IMUX.IMUX.0.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN1 | input | TCELL17:IMUX.IMUX.47.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN2 | input | TCELL17:IMUX.IMUX.46.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN3 | input | TCELL17:IMUX.IMUX.15.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN4 | input | TCELL17:IMUX.IMUX.45.DELAY |
| AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN5 | input | TCELL17:IMUX.IMUX.44.DELAY |
| AXI1_WDATA_PAR_7_6_NIB6_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL18:IMUX.IMUX.17.DELAY |
| AXI1_WDATA_PAR_7_6_NIB6_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL18:IMUX.IMUX.16.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR0 | input | TCELL13:IMUX.IMUX.15.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR1 | input | TCELL13:IMUX.IMUX.45.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR2 | input | TCELL13:IMUX.IMUX.44.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR3 | input | TCELL13:IMUX.IMUX.14.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR4 | input | TCELL13:IMUX.IMUX.43.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR5 | input | TCELL13:IMUX.IMUX.42.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR6 | input | TCELL13:IMUX.IMUX.13.DELAY |
| AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR7 | input | TCELL13:IMUX.IMUX.41.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR0 | input | TCELL5:IMUX.IMUX.26.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR1 | input | TCELL5:IMUX.IMUX.5.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR2 | input | TCELL5:IMUX.IMUX.25.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR3 | input | TCELL5:IMUX.IMUX.24.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR4 | input | TCELL5:IMUX.IMUX.4.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR5 | input | TCELL5:IMUX.IMUX.23.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR6 | input | TCELL5:IMUX.IMUX.22.DELAY |
| AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR7 | input | TCELL5:IMUX.IMUX.3.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR0 | input | TCELL2:IMUX.IMUX.26.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR1 | input | TCELL2:IMUX.IMUX.5.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR2 | input | TCELL2:IMUX.IMUX.25.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR3 | input | TCELL2:IMUX.IMUX.24.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR4 | input | TCELL2:IMUX.IMUX.4.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR5 | input | TCELL2:IMUX.IMUX.23.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR6 | input | TCELL2:IMUX.IMUX.22.DELAY |
| AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR7 | input | TCELL2:IMUX.IMUX.3.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR0 | input | TCELL16:IMUX.IMUX.24.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR1 | input | TCELL16:IMUX.IMUX.4.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR2 | input | TCELL16:IMUX.IMUX.23.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR3 | input | TCELL16:IMUX.IMUX.22.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR4 | input | TCELL16:IMUX.IMUX.3.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR5 | input | TCELL16:IMUX.IMUX.21.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR6 | input | TCELL16:IMUX.IMUX.20.DELAY |
| AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR7 | input | TCELL16:IMUX.IMUX.2.DELAY |
| AXIA0_CLK | input | TCELL48:IMUX.CTRL.0 |
| AXIA1_CLK | input | TCELL10:IMUX.CTRL.0 |
| CAPTURE_DR | input | TCELL34:IMUX.IMUX.30.DELAY |
| CAPTURE_DR_O | output | TCELL33:OUT.21.TMIN |
| CFG2IOB_PUDC_B | input | TCELL34:IMUX.IMUX.27.DELAY |
| CFG2IOB_PUDC_B_O | output | TCELL33:OUT.16.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS0 | output | TCELL18:OUT.22.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS1 | output | TCELL18:OUT.21.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS10 | output | TCELL18:OUT.12.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS11 | output | TCELL18:OUT.11.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS12 | output | TCELL18:OUT.10.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS13 | output | TCELL18:OUT.9.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS14 | output | TCELL18:OUT.8.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS15 | output | TCELL18:OUT.7.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS2 | output | TCELL18:OUT.20.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS3 | output | TCELL18:OUT.19.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS4 | output | TCELL18:OUT.18.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS5 | output | TCELL18:OUT.17.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS6 | output | TCELL18:OUT.16.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS7 | output | TCELL18:OUT.15.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS8 | output | TCELL18:OUT.14.TMIN |
| CFI_NPI_BRIDGE_TO_FABRIC_STATUS9 | output | TCELL18:OUT.13.TMIN |
| FABRIC_APB_RST_N | input | TCELL1:IMUX.BYP.10.DELAY |
| FABRIC_MUX_SELECT_EN | input | TCELL15:IMUX.IMUX.40.DELAY |
| IFABRIC_APB_CLK | input | TCELL18:IMUX.CTRL.0 |
| IF_APB_FABRIC2BRIDGE_PADDR0 | input | TCELL15:IMUX.IMUX.11.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR1 | input | TCELL15:IMUX.IMUX.37.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR10 | input | TCELL15:IMUX.IMUX.31.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR11 | input | TCELL15:IMUX.IMUX.30.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR12 | input | TCELL15:IMUX.IMUX.7.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR13 | input | TCELL15:IMUX.IMUX.29.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR14 | input | TCELL15:IMUX.IMUX.28.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR15 | input | TCELL15:IMUX.IMUX.6.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR16 | input | TCELL15:IMUX.IMUX.27.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR17 | input | TCELL15:IMUX.IMUX.26.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR18 | input | TCELL15:IMUX.IMUX.5.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR19 | input | TCELL15:IMUX.IMUX.25.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR2 | input | TCELL15:IMUX.IMUX.36.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR20 | input | TCELL15:IMUX.IMUX.24.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR21 | input | TCELL15:IMUX.IMUX.4.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR22 | input | TCELL15:IMUX.IMUX.23.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR23 | input | TCELL15:IMUX.IMUX.22.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR24 | input | TCELL15:IMUX.IMUX.3.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR25 | input | TCELL15:IMUX.IMUX.21.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR26 | input | TCELL15:IMUX.IMUX.20.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR27 | input | TCELL15:IMUX.IMUX.2.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR28 | input | TCELL15:IMUX.IMUX.19.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR29 | input | TCELL15:IMUX.IMUX.18.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR3 | input | TCELL15:IMUX.IMUX.10.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR30 | input | TCELL15:IMUX.IMUX.1.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR31 | input | TCELL15:IMUX.IMUX.17.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR4 | input | TCELL15:IMUX.IMUX.35.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR5 | input | TCELL15:IMUX.IMUX.34.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR6 | input | TCELL15:IMUX.IMUX.9.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR7 | input | TCELL15:IMUX.IMUX.33.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR8 | input | TCELL15:IMUX.IMUX.32.DELAY |
| IF_APB_FABRIC2BRIDGE_PADDR9 | input | TCELL15:IMUX.IMUX.8.DELAY |
| IF_APB_FABRIC2BRIDGE_PENABLE | input | TCELL15:IMUX.IMUX.39.DELAY |
| IF_APB_FABRIC2BRIDGE_PRDATA0 | output | TCELL19:OUT.27.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA1 | output | TCELL19:OUT.26.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA10 | output | TCELL18:OUT.30.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA11 | output | TCELL18:OUT.29.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA12 | output | TCELL18:OUT.28.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA13 | output | TCELL18:OUT.27.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA14 | output | TCELL18:OUT.26.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA15 | output | TCELL18:OUT.25.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA16 | output | TCELL18:OUT.24.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA17 | output | TCELL18:OUT.23.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA18 | output | TCELL18:OUT.6.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA19 | output | TCELL18:OUT.5.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA2 | output | TCELL19:OUT.25.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA20 | output | TCELL18:OUT.4.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA21 | output | TCELL18:OUT.3.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA22 | output | TCELL17:OUT.31.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA23 | output | TCELL17:OUT.30.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA24 | output | TCELL17:OUT.29.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA25 | output | TCELL17:OUT.28.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA26 | output | TCELL17:OUT.27.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA27 | output | TCELL17:OUT.26.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA28 | output | TCELL17:OUT.25.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA29 | output | TCELL17:OUT.24.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA3 | output | TCELL19:OUT.24.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA30 | output | TCELL17:OUT.23.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA31 | output | TCELL17:OUT.22.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA4 | output | TCELL19:OUT.23.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA5 | output | TCELL19:OUT.22.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA6 | output | TCELL19:OUT.21.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA7 | output | TCELL19:OUT.20.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA8 | output | TCELL19:OUT.3.TMIN |
| IF_APB_FABRIC2BRIDGE_PRDATA9 | output | TCELL18:OUT.31.TMIN |
| IF_APB_FABRIC2BRIDGE_PREADY | output | TCELL21:OUT.10.TMIN |
| IF_APB_FABRIC2BRIDGE_PSELX | input | TCELL15:IMUX.IMUX.38.DELAY |
| IF_APB_FABRIC2BRIDGE_PSLVERR | output | TCELL21:OUT.11.TMIN |
| IF_APB_FABRIC2BRIDGE_PWDATA0 | input | TCELL21:IMUX.IMUX.16.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA1 | input | TCELL20:IMUX.IMUX.47.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA10 | input | TCELL20:IMUX.IMUX.30.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA11 | input | TCELL20:IMUX.IMUX.19.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA12 | input | TCELL20:IMUX.IMUX.18.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA13 | input | TCELL20:IMUX.IMUX.1.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA14 | input | TCELL20:IMUX.IMUX.17.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA15 | input | TCELL19:IMUX.IMUX.42.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA16 | input | TCELL19:IMUX.IMUX.13.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA17 | input | TCELL19:IMUX.IMUX.41.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA18 | input | TCELL19:IMUX.IMUX.40.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA19 | input | TCELL19:IMUX.IMUX.12.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA2 | input | TCELL20:IMUX.IMUX.46.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA20 | input | TCELL19:IMUX.IMUX.39.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA21 | input | TCELL19:IMUX.IMUX.38.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA22 | input | TCELL19:IMUX.IMUX.11.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA23 | input | TCELL19:IMUX.IMUX.37.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA24 | input | TCELL19:IMUX.IMUX.36.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA25 | input | TCELL19:IMUX.IMUX.10.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA26 | input | TCELL19:IMUX.IMUX.35.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA27 | input | TCELL19:IMUX.IMUX.34.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA28 | input | TCELL19:IMUX.IMUX.9.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA29 | input | TCELL19:IMUX.IMUX.33.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA3 | input | TCELL20:IMUX.IMUX.15.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA30 | input | TCELL19:IMUX.IMUX.32.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA31 | input | TCELL19:IMUX.IMUX.8.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA4 | input | TCELL20:IMUX.IMUX.45.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA5 | input | TCELL20:IMUX.IMUX.9.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA6 | input | TCELL20:IMUX.IMUX.33.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA7 | input | TCELL20:IMUX.IMUX.32.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA8 | input | TCELL20:IMUX.IMUX.8.DELAY |
| IF_APB_FABRIC2BRIDGE_PWDATA9 | input | TCELL20:IMUX.IMUX.31.DELAY |
| IF_APB_FABRIC2BRIDGE_PWRITE | input | TCELL15:IMUX.IMUX.12.DELAY |
| IF_DMC_FABRIC_BLI2ILA_ACK | input | TCELL26:IMUX.IMUX.25.DELAY |
| IF_DMC_FABRIC_BLI2ILA_TRIG | input | TCELL26:IMUX.IMUX.24.DELAY |
| IF_DMC_FABRIC_BLI2UB_ACK | input | TCELL26:IMUX.IMUX.21.DELAY |
| IF_DMC_FABRIC_BLI2UB_TRACE_CLK | input | TCELL26:IMUX.CTRL.0 |
| IF_DMC_FABRIC_BLI2UB_TRACE_RST_N | input | TCELL26:IMUX.IMUX.22.DELAY |
| IF_DMC_FABRIC_BLI2UB_TRACE_TREADY | input | TCELL26:IMUX.IMUX.3.DELAY |
| IF_DMC_FABRIC_BLI2UB_TRIG | input | TCELL26:IMUX.IMUX.20.DELAY |
| IF_DMC_FABRIC_BLI2UB_UART_RX | input | TCELL26:IMUX.IMUX.23.DELAY |
| IF_DMC_FABRIC_BLOCK_PERIODIC_CAL | input | TCELL26:IMUX.IMUX.4.DELAY |
| IF_DMC_FABRIC_CAL_BUSY | output | TCELL26:OUT.18.TMIN |
| IF_DMC_FABRIC_CAL_DONE | output | TCELL26:OUT.19.TMIN |
| IF_DMC_FABRIC_CSSD_CLKSTP_BCAST | output | TCELL27:OUT.3.TMIN |
| IF_DMC_FABRIC_CSSD_TRIG_IN_N_EXT | input | TCELL26:IMUX.IMUX.5.DELAY |
| IF_DMC_FABRIC_EXMON_CLEAR_IN | input | TCELL26:IMUX.IMUX.19.DELAY |
| IF_DMC_FABRIC_EXMON_CLEAR_OUT | output | TCELL27:OUT.4.TMIN |
| IF_DMC_FABRIC_ILA2BLI_ACK | output | TCELL27:OUT.26.TMIN |
| IF_DMC_FABRIC_ILA2BLI_TRIG | output | TCELL27:OUT.27.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_0 | output | TCELL0:OUT.0.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_1 | output | TCELL0:OUT.1.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_2 | output | TCELL0:OUT.2.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_3 | output | TCELL0:OUT.3.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_4 | output | TCELL0:OUT.4.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE0_5 | output | TCELL0:OUT.5.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE1 | output | TCELL27:OUT.5.TMIN |
| IF_DMC_FABRIC_LPDDRMC_SPARE2 | input | TCELL14:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_REF_ACK_0_0 | output | TCELL26:OUT.15.TMIN |
| IF_DMC_FABRIC_REF_ACK_0_1 | output | TCELL26:OUT.14.TMIN |
| IF_DMC_FABRIC_REF_ACK_0_2 | output | TCELL26:OUT.13.TMIN |
| IF_DMC_FABRIC_REF_ACK_0_3 | output | TCELL26:OUT.12.TMIN |
| IF_DMC_FABRIC_REF_ACK_1_0 | output | TCELL26:OUT.17.TMIN |
| IF_DMC_FABRIC_REF_ACK_1_1 | output | TCELL26:OUT.16.TMIN |
| IF_DMC_FABRIC_REF_RANK_EN_0_0 | input | TCELL26:IMUX.IMUX.17.DELAY |
| IF_DMC_FABRIC_REF_RANK_EN_0_1 | input | TCELL26:IMUX.IMUX.16.DELAY |
| IF_DMC_FABRIC_REF_RANK_EN_0_2 | input | TCELL25:IMUX.IMUX.47.DELAY |
| IF_DMC_FABRIC_REF_RANK_EN_0_3 | input | TCELL25:IMUX.IMUX.46.DELAY |
| IF_DMC_FABRIC_REF_RANK_EN_1_0 | input | TCELL26:IMUX.IMUX.18.DELAY |
| IF_DMC_FABRIC_REF_RANK_EN_1_1 | input | TCELL26:IMUX.IMUX.1.DELAY |
| IF_DMC_FABRIC_REF_USR_PORT_AVAILABLE | output | TCELL26:OUT.11.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT0 | input | TCELL32:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT1 | input | TCELL15:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT10 | input | TCELL48:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT11 | input | TCELL44:IMUX.BYP.11.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT12 | input | TCELL45:IMUX.BYP.8.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT2 | input | TCELL59:IMUX.BYP.7.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT3 | input | TCELL21:IMUX.BYP.6.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT4 | input | TCELL21:IMUX.BYP.12.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT5 | input | TCELL2:IMUX.BYP.11.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT6 | input | TCELL39:IMUX.BYP.7.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT7 | input | TCELL10:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT8 | input | TCELL5:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_IN_EXT9 | input | TCELL31:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT0 | input | TCELL29:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT1 | input | TCELL58:IMUX.BYP.7.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT10 | input | TCELL54:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT11 | input | TCELL18:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT12 | input | TCELL2:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT2 | input | TCELL24:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT3 | input | TCELL17:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT4 | input | TCELL35:IMUX.BYP.8.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT5 | input | TCELL11:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT6 | input | TCELL51:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT7 | input | TCELL45:IMUX.BYP.11.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT8 | input | TCELL23:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT9 | input | TCELL26:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC0 | output | TCELL26:OUT.29.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC1 | output | TCELL26:OUT.28.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC2 | output | TCELL26:OUT.27.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC3 | output | TCELL26:OUT.26.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC4 | output | TCELL26:OUT.25.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC5 | output | TCELL26:OUT.24.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC6 | output | TCELL26:OUT.23.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC7 | output | TCELL26:OUT.22.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC8 | output | TCELL26:OUT.21.TMIN |
| IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC9 | output | TCELL26:OUT.20.TMIN |
| IF_DMC_FABRIC_SCAN_CLK_N_EXT | input | TCELL49:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_CNTRL_CHNL_IN_EXT_DDRMC0 | input | TCELL6:IMUX.BYP.9.DELAY |
| IF_DMC_FABRIC_SCAN_CNTRL_CHNL_IN_EXT_DDRMC1 | input | TCELL37:IMUX.BYP.7.DELAY |
| IF_DMC_FABRIC_SCAN_CNTRL_CHNL_OUT_EXT_DDRMC0 | output | TCELL26:OUT.31.TMIN |
| IF_DMC_FABRIC_SCAN_CNTRL_CHNL_OUT_EXT_DDRMC1 | output | TCELL26:OUT.30.TMIN |
| IF_DMC_FABRIC_SCAN_EDT_UPDT_N_EXT | input | TCELL27:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_EN_N_EXT | input | TCELL3:IMUX.BYP.10.DELAY |
| IF_DMC_FABRIC_SCAN_MODE_RST_N_EXT | input | TCELL38:IMUX.BYP.8.DELAY |
| IF_DMC_FABRIC_UB2BLI_ACK | output | TCELL27:OUT.6.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA0 | output | TCELL27:OUT.23.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA1 | output | TCELL27:OUT.22.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA10 | output | TCELL27:OUT.13.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA11 | output | TCELL27:OUT.12.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA12 | output | TCELL27:OUT.11.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA13 | output | TCELL27:OUT.10.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA14 | output | TCELL27:OUT.9.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA15 | output | TCELL27:OUT.8.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA2 | output | TCELL27:OUT.21.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA3 | output | TCELL27:OUT.20.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA4 | output | TCELL27:OUT.19.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA5 | output | TCELL27:OUT.18.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA6 | output | TCELL27:OUT.17.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA7 | output | TCELL27:OUT.16.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA8 | output | TCELL27:OUT.15.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TDATA9 | output | TCELL27:OUT.14.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRACE_TVALID | output | TCELL27:OUT.24.TMIN |
| IF_DMC_FABRIC_UB2BLI_TRIG | output | TCELL27:OUT.7.TMIN |
| IF_DMC_FABRIC_UB2BLI_UART_TX | output | TCELL27:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P0_CLB2MC_DIV_CLK | input | TCELL56:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P0_CLB2PHY_CTRL_CLK | input | TCELL56:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL55:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL55:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL55:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL55:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL55:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL55:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_FIFO_CLK | input | TCELL56:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE0 | input | TCELL55:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE1 | input | TCELL55:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE2 | input | TCELL55:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE3 | input | TCELL55:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE4 | input | TCELL55:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE5 | input | TCELL55:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL57:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL57:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL57:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL57:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL57:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL57:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE0 | input | TCELL56:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE1 | input | TCELL56:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE2 | input | TCELL55:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE3 | input | TCELL55:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE4 | input | TCELL55:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE5 | input | TCELL55:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL57:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL57:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL57:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL57:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL57:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL57:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL57:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL57:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL57:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL57:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL57:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL57:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL57:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL57:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL56:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL56:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL56:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL56:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL56:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL56:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL56:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL56:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL56:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL57:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL56:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL56:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL56:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL56:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL56:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL56:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL56:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL56:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL56:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL56:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL57:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL56:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL56:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL56:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL56:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL56:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL56:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL56:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL56:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL56:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL56:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL57:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL56:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL56:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL56:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL56:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL57:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL57:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL57:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL57:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC0 | input | TCELL56:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC1 | input | TCELL56:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC2 | input | TCELL56:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC3 | input | TCELL56:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC4 | input | TCELL56:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC5 | input | TCELL56:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD0 | input | TCELL56:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD1 | input | TCELL56:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD2 | input | TCELL56:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD3 | input | TCELL56:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD4 | input | TCELL56:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD5 | input | TCELL56:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN0 | input | TCELL58:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN1 | input | TCELL58:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN2 | input | TCELL58:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN3 | input | TCELL58:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN4 | input | TCELL58:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN5 | input | TCELL58:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL57:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL57:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL57:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL57:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL57:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL57:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL57:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL57:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL57:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL57:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL57:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL57:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL57:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL57:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL57:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL57:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL57:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL57:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_0 | input | TCELL57:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_1 | input | TCELL57:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_2 | input | TCELL57:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RST | input | TCELL55:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST0 | input | TCELL55:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST1 | input | TCELL55:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST2 | input | TCELL55:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST3 | input | TCELL55:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST4 | input | TCELL55:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST5 | input | TCELL55:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST0 | input | TCELL55:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST1 | input | TCELL55:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST2 | input | TCELL55:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST3 | input | TCELL55:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST4 | input | TCELL55:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST5 | input | TCELL55:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2RIU_NIBBLE_SEL | input | TCELL59:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P0_CLB2RIU_WR_EN | input | TCELL58:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT0 | output | TCELL57:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT1 | output | TCELL57:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT2 | output | TCELL57:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT3 | output | TCELL57:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT4 | output | TCELL57:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P0_IOB2CLB_DFT5 | output | TCELL57:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_FIFO_EMPTY | output | TCELL55:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_FIXDLY_RDY | output | TCELL55:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_GT_STATUS | output | TCELL55:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL57:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL57:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL57:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL57:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL57:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL57:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL57:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL57:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL57:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL57:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL57:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL56:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL57:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL56:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL56:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL56:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL56:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL56:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL56:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL56:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL56:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL56:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL56:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL57:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL56:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL56:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL56:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL56:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL56:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL56:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL56:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL56:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL56:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL56:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL57:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL56:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL56:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL56:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL56:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL56:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL56:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL56:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL56:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL56:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL56:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL57:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL55:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL55:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL55:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL55:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL57:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL57:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL57:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL57:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_0 | output | TCELL57:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_1 | output | TCELL57:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_2 | output | TCELL57:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_0 | output | TCELL57:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_1 | output | TCELL57:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_2 | output | TCELL57:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_MASTER_PD | output | TCELL55:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P0_PHY2CLB_PHY_RDY | output | TCELL55:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P0_RIU2CLB_VALID | output | TCELL57:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_CLB2MC_DIV_CLK | input | TCELL22:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P10_CLB2PHY_CTRL_CLK | input | TCELL22:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DLYCTL_EN_VTC | input | TCELL22:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL22:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL22:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL22:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL22:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL22:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL22:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_FIFO_CLK | input | TCELL22:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P10_CLB2PHY_FIFO_RDEN | input | TCELL22:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE0 | input | TCELL22:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE1 | input | TCELL22:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE2 | input | TCELL22:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE3 | input | TCELL22:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE4 | input | TCELL22:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE5 | input | TCELL22:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL24:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL24:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL24:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL24:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL24:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL24:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE0 | input | TCELL23:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE1 | input | TCELL23:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE2 | input | TCELL22:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE3 | input | TCELL22:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE4 | input | TCELL22:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE5 | input | TCELL22:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL24:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL24:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL24:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL24:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL24:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL24:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL24:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL24:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL24:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL24:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL24:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL24:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL24:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL24:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL24:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL24:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL24:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL24:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL24:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL24:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL24:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL23:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL23:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL24:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL23:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL23:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL23:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL23:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL23:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL23:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL23:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL23:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL23:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL23:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL24:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL23:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL23:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL23:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL23:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL23:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL23:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL23:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL23:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL23:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL23:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL24:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL23:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL23:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL23:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL23:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL24:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL24:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL24:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL24:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC0 | input | TCELL23:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC1 | input | TCELL23:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC2 | input | TCELL23:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC3 | input | TCELL23:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC4 | input | TCELL23:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC5 | input | TCELL23:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD0 | input | TCELL23:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD1 | input | TCELL23:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD2 | input | TCELL23:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD3 | input | TCELL23:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD4 | input | TCELL23:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD5 | input | TCELL23:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL0 | input | TCELL24:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL1 | input | TCELL24:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL2 | input | TCELL24:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL3 | input | TCELL24:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL4 | input | TCELL24:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL5 | input | TCELL24:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN0 | input | TCELL25:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN1 | input | TCELL25:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN2 | input | TCELL25:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN3 | input | TCELL25:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN4 | input | TCELL25:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN5 | input | TCELL25:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL25:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL25:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL24:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL25:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL25:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL25:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL25:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL25:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL25:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL25:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL25:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL25:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL24:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL24:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL24:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL24:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL24:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL24:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_0 | input | TCELL25:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_1 | input | TCELL25:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_2 | input | TCELL25:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN0 | input | TCELL22:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN1 | input | TCELL22:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN2 | input | TCELL22:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN3 | input | TCELL22:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RST | input | TCELL21:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST0 | input | TCELL22:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST1 | input | TCELL22:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST2 | input | TCELL22:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST3 | input | TCELL22:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST4 | input | TCELL22:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST5 | input | TCELL22:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST0 | input | TCELL22:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST1 | input | TCELL21:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST2 | input | TCELL21:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST3 | input | TCELL21:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST4 | input | TCELL21:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST5 | input | TCELL21:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT0 | input | TCELL22:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT1 | input | TCELL22:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT2 | input | TCELL22:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT3 | input | TCELL22:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT4 | input | TCELL22:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT5 | input | TCELL22:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WREN0 | input | TCELL22:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WREN1 | input | TCELL22:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WREN2 | input | TCELL22:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WREN3 | input | TCELL22:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_0 | input | TCELL21:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_1 | input | TCELL21:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_2 | input | TCELL21:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_3 | input | TCELL21:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_4 | input | TCELL21:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_5 | input | TCELL21:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_6 | input | TCELL21:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_7 | input | TCELL21:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_0 | input | TCELL21:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_1 | input | TCELL21:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_2 | input | TCELL21:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_3 | input | TCELL21:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_4 | input | TCELL21:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_5 | input | TCELL21:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_6 | input | TCELL21:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_7 | input | TCELL21:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_0 | input | TCELL21:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_1 | input | TCELL21:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_2 | input | TCELL21:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_3 | input | TCELL21:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_4 | input | TCELL21:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_5 | input | TCELL21:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_6 | input | TCELL21:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_7 | input | TCELL21:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_0 | input | TCELL21:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_1 | input | TCELL21:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_2 | input | TCELL21:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_3 | input | TCELL21:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_4 | input | TCELL21:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_5 | input | TCELL21:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_6 | input | TCELL21:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_7 | input | TCELL21:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_0 | input | TCELL22:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_1 | input | TCELL22:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_2 | input | TCELL22:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_3 | input | TCELL22:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_4 | input | TCELL22:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_5 | input | TCELL22:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_6 | input | TCELL22:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_7 | input | TCELL22:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_0 | input | TCELL23:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_1 | input | TCELL23:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_2 | input | TCELL23:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_3 | input | TCELL23:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_4 | input | TCELL23:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_5 | input | TCELL23:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_6 | input | TCELL23:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_7 | input | TCELL23:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR0 | input | TCELL25:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR1 | input | TCELL25:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR2 | input | TCELL25:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR3 | input | TCELL25:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR4 | input | TCELL25:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR5 | input | TCELL25:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR6 | input | TCELL25:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR7 | input | TCELL25:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_NIBBLE_SEL | input | TCELL26:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA0 | input | TCELL25:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA1 | input | TCELL25:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA10 | input | TCELL25:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA11 | input | TCELL25:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA12 | input | TCELL25:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA13 | input | TCELL25:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA14 | input | TCELL25:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA15 | input | TCELL25:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA2 | input | TCELL25:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA3 | input | TCELL25:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA4 | input | TCELL25:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA5 | input | TCELL25:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA6 | input | TCELL25:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA7 | input | TCELL25:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA8 | input | TCELL25:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA9 | input | TCELL25:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P10_CLB2RIU_WR_EN | input | TCELL25:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT0 | output | TCELL25:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT1 | output | TCELL25:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT2 | output | TCELL25:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT3 | output | TCELL25:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT4 | output | TCELL25:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P10_IOB2CLB_DFT5 | output | TCELL25:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_FIFO_EMPTY | output | TCELL23:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_FIXDLY_RDY | output | TCELL23:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_GT_STATUS | output | TCELL23:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL25:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL25:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL24:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL24:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL24:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL24:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL24:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL24:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL24:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL24:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL24:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL24:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL25:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL24:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL24:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL24:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL24:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL24:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL24:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL24:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL24:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL24:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL24:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL25:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL24:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL24:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL24:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL24:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL24:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL24:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL24:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL23:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL23:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL23:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL25:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL23:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL23:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL23:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL23:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL23:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL23:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL23:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL23:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL23:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL23:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL25:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL23:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL23:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL23:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL23:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL25:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL25:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL24:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL24:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_0 | output | TCELL25:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_1 | output | TCELL25:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_2 | output | TCELL25:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_0 | output | TCELL25:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_1 | output | TCELL25:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_2 | output | TCELL25:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_MASTER_PD | output | TCELL23:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_PHY_RDY | output | TCELL23:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_0 | output | TCELL21:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_1 | output | TCELL21:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_2 | output | TCELL21:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_3 | output | TCELL21:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_4 | output | TCELL21:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_5 | output | TCELL21:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_6 | output | TCELL21:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_7 | output | TCELL21:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_0 | output | TCELL22:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_1 | output | TCELL21:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_2 | output | TCELL22:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_3 | output | TCELL21:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_4 | output | TCELL22:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_5 | output | TCELL21:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_6 | output | TCELL22:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_7 | output | TCELL21:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_0 | output | TCELL22:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_1 | output | TCELL22:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_2 | output | TCELL22:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_3 | output | TCELL22:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_4 | output | TCELL22:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_5 | output | TCELL22:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_6 | output | TCELL22:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_7 | output | TCELL22:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_0 | output | TCELL22:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_1 | output | TCELL22:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_2 | output | TCELL22:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_3 | output | TCELL22:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_4 | output | TCELL22:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_5 | output | TCELL22:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_6 | output | TCELL22:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_7 | output | TCELL22:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_0 | output | TCELL22:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_1 | output | TCELL22:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_2 | output | TCELL22:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_3 | output | TCELL22:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_4 | output | TCELL22:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_5 | output | TCELL22:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_6 | output | TCELL22:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_7 | output | TCELL22:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_0 | output | TCELL23:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_1 | output | TCELL23:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_2 | output | TCELL23:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_3 | output | TCELL23:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_4 | output | TCELL23:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_5 | output | TCELL23:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_6 | output | TCELL23:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_7 | output | TCELL22:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA0 | output | TCELL26:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA1 | output | TCELL26:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA10 | output | TCELL25:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA11 | output | TCELL25:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA12 | output | TCELL25:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA13 | output | TCELL25:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA14 | output | TCELL25:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA15 | output | TCELL25:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA2 | output | TCELL26:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA3 | output | TCELL26:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA4 | output | TCELL26:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA5 | output | TCELL26:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA6 | output | TCELL26:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA7 | output | TCELL25:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA8 | output | TCELL25:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA9 | output | TCELL25:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P10_RIU2CLB_VALID | output | TCELL26:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P1_CLB2MC_DIV_CLK | input | TCELL49:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P1_CLB2PHY_CTRL_CLK | input | TCELL49:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL50:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL50:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL50:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL50:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL50:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL49:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_FIFO_CLK | input | TCELL49:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE0 | input | TCELL50:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE1 | input | TCELL50:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE2 | input | TCELL50:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE3 | input | TCELL50:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE4 | input | TCELL50:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE5 | input | TCELL50:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL52:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL52:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL52:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL52:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL52:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL52:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE0 | input | TCELL50:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE1 | input | TCELL50:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE2 | input | TCELL50:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE3 | input | TCELL50:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE4 | input | TCELL50:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE5 | input | TCELL50:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL52:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL52:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL52:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL52:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL52:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL52:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL52:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL52:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL52:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL52:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL52:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL52:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL52:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL52:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL52:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL52:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL52:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL51:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL51:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL51:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL51:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL51:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL51:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL52:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL51:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL51:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL51:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL51:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL51:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL51:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL51:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL51:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL51:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL51:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL52:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL51:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL51:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL51:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL51:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL51:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL51:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL51:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL51:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL50:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL50:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL52:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL50:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL50:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL50:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL50:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL52:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL52:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL52:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL52:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC0 | input | TCELL50:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC1 | input | TCELL50:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC2 | input | TCELL50:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC3 | input | TCELL50:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC4 | input | TCELL50:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC5 | input | TCELL50:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD0 | input | TCELL50:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD1 | input | TCELL50:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD2 | input | TCELL50:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD3 | input | TCELL50:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD4 | input | TCELL50:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD5 | input | TCELL50:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN0 | input | TCELL53:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN1 | input | TCELL53:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN2 | input | TCELL53:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN3 | input | TCELL53:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN4 | input | TCELL53:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN5 | input | TCELL53:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL52:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL52:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL52:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL53:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL53:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL52:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL53:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL53:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL53:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL52:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL52:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL52:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL52:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL52:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL52:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL52:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL52:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL52:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_0 | input | TCELL52:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_1 | input | TCELL52:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_2 | input | TCELL52:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RST | input | TCELL49:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST0 | input | TCELL49:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST1 | input | TCELL49:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST2 | input | TCELL49:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST3 | input | TCELL49:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST4 | input | TCELL49:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST5 | input | TCELL49:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST0 | input | TCELL49:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST1 | input | TCELL49:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST2 | input | TCELL49:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST3 | input | TCELL49:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST4 | input | TCELL49:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST5 | input | TCELL49:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2RIU_NIBBLE_SEL | input | TCELL53:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P1_CLB2RIU_WR_EN | input | TCELL53:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT0 | output | TCELL53:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT1 | output | TCELL53:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT2 | output | TCELL53:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT3 | output | TCELL53:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT4 | output | TCELL53:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P1_IOB2CLB_DFT5 | output | TCELL53:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_FIFO_EMPTY | output | TCELL51:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_FIXDLY_RDY | output | TCELL51:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_GT_STATUS | output | TCELL51:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL53:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL53:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL53:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL53:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL53:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL53:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL52:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL52:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL52:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL52:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL52:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL52:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL53:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL52:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL52:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL52:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL52:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL52:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL52:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL52:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL52:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL52:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL52:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL53:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL52:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL52:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL52:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL52:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL52:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL52:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL52:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL52:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL51:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL51:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL53:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL51:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL51:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL51:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL51:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL51:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL51:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL51:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL51:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL51:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL51:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL53:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL51:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL51:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL51:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL51:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL53:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL53:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL53:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL53:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_0 | output | TCELL53:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_1 | output | TCELL53:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_2 | output | TCELL53:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_0 | output | TCELL53:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_1 | output | TCELL53:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_2 | output | TCELL53:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_MASTER_PD | output | TCELL51:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P1_PHY2CLB_PHY_RDY | output | TCELL51:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P1_RIU2CLB_VALID | output | TCELL53:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P2_CLB2MC_DIV_CLK | input | TCELL46:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P2_CLB2PHY_CTRL_CLK | input | TCELL46:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL47:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL47:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL47:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL47:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL47:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL47:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_FIFO_CLK | input | TCELL46:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE0 | input | TCELL47:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE1 | input | TCELL47:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE2 | input | TCELL47:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE3 | input | TCELL47:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE4 | input | TCELL47:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE5 | input | TCELL47:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL48:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL48:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL48:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL48:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL48:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL47:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE0 | input | TCELL47:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE1 | input | TCELL47:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE2 | input | TCELL47:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE3 | input | TCELL47:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE4 | input | TCELL47:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE5 | input | TCELL47:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC0 | input | TCELL47:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC1 | input | TCELL47:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC2 | input | TCELL47:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC3 | input | TCELL47:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC4 | input | TCELL47:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC5 | input | TCELL47:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD0 | input | TCELL47:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD1 | input | TCELL47:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD2 | input | TCELL47:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD3 | input | TCELL47:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD4 | input | TCELL47:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD5 | input | TCELL47:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL49:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL49:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL48:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_0_BIT2 | input | TCELL49:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL49:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL49:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL49:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL49:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL49:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL49:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL48:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL48:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL48:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL48:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL48:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL48:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_0 | input | TCELL49:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_1 | input | TCELL49:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_2 | input | TCELL49:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RST | input | TCELL46:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST0 | input | TCELL47:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST1 | input | TCELL47:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST2 | input | TCELL47:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST3 | input | TCELL47:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST4 | input | TCELL47:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST5 | input | TCELL47:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST0 | input | TCELL47:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST1 | input | TCELL47:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST2 | input | TCELL47:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST3 | input | TCELL47:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST4 | input | TCELL46:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST5 | input | TCELL46:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2RIU_NIBBLE_SEL | input | TCELL48:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P2_CLB2RIU_WR_EN | input | TCELL49:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT0 | output | TCELL45:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT1 | output | TCELL45:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT2 | output | TCELL45:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT3 | output | TCELL45:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT4 | output | TCELL45:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P2_IOB2CLB_DFT5 | output | TCELL45:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_FIFO_EMPTY | output | TCELL44:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_FIXDLY_RDY | output | TCELL44:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_GT_STATUS | output | TCELL44:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_0 | output | TCELL45:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_1 | output | TCELL45:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_2 | output | TCELL45:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_0 | output | TCELL45:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_1 | output | TCELL45:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_2 | output | TCELL45:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_MASTER_PD | output | TCELL45:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P2_PHY2CLB_PHY_RDY | output | TCELL44:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P2_RIU2CLB_VALID | output | TCELL45:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P3_CLB2MC_DIV_CLK | input | TCELL38:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P3_CLB2PHY_CTRL_CLK | input | TCELL38:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL40:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL40:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL40:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL39:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL39:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL39:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_FIFO_CLK | input | TCELL38:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE0 | input | TCELL40:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE1 | input | TCELL40:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE2 | input | TCELL40:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE3 | input | TCELL40:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE4 | input | TCELL40:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE5 | input | TCELL40:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE0 | input | TCELL40:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE1 | input | TCELL40:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE2 | input | TCELL40:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE3 | input | TCELL40:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE4 | input | TCELL40:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE5 | input | TCELL40:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC0 | input | TCELL40:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC1 | input | TCELL40:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC2 | input | TCELL40:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC3 | input | TCELL40:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC4 | input | TCELL40:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC5 | input | TCELL40:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD0 | input | TCELL40:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD1 | input | TCELL40:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD2 | input | TCELL40:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD3 | input | TCELL40:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD4 | input | TCELL40:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD5 | input | TCELL40:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN0 | input | TCELL44:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN1 | input | TCELL44:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN2 | input | TCELL44:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN3 | input | TCELL43:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN4 | input | TCELL43:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN5 | input | TCELL43:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL40:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL40:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL40:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL43:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL41:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL40:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL43:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL43:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL43:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL40:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL40:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL40:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL40:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL40:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL40:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL40:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL40:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL40:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RST | input | TCELL39:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST0 | input | TCELL39:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST1 | input | TCELL39:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST2 | input | TCELL39:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST3 | input | TCELL39:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST4 | input | TCELL39:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST5 | input | TCELL39:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST0 | input | TCELL39:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST1 | input | TCELL39:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST2 | input | TCELL39:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST3 | input | TCELL39:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST4 | input | TCELL39:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST5 | input | TCELL39:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P3_CLB2RIU_NIBBLE_SEL | input | TCELL43:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT0 | output | TCELL41:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT1 | output | TCELL41:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT2 | output | TCELL41:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT3 | output | TCELL41:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT4 | output | TCELL40:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P3_IOB2CLB_DFT5 | output | TCELL40:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_FIFO_EMPTY | output | TCELL40:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_FIXDLY_RDY | output | TCELL40:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_GT_STATUS | output | TCELL40:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_0 | output | TCELL41:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_1 | output | TCELL41:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_2 | output | TCELL41:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_0 | output | TCELL41:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_1 | output | TCELL41:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_2 | output | TCELL41:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_MASTER_PD | output | TCELL40:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P3_PHY2CLB_PHY_RDY | output | TCELL40:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P3_RIU2CLB_VALID | output | TCELL41:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P4_CLB2MC_DIV_CLK | input | TCELL34:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P4_CLB2PHY_CTRL_CLK | input | TCELL34:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DLYCTL_EN_VTC | input | TCELL35:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL35:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL35:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL35:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL35:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL35:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL35:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_FIFO_CLK | input | TCELL34:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P4_CLB2PHY_FIFO_RDEN | input | TCELL35:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE0 | input | TCELL35:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE1 | input | TCELL35:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE2 | input | TCELL35:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE3 | input | TCELL35:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE4 | input | TCELL35:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE5 | input | TCELL35:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL37:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL37:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL37:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL37:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL37:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL37:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE0 | input | TCELL35:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE1 | input | TCELL35:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE2 | input | TCELL35:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE3 | input | TCELL35:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE4 | input | TCELL35:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE5 | input | TCELL35:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL36:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL36:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL36:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL36:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL36:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL36:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL36:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL36:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL36:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL36:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL36:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL36:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL36:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL36:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL36:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL36:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL36:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL36:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL36:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL36:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL36:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL36:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL36:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL36:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL36:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL36:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL36:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL36:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL36:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL36:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL36:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL36:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL36:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL36:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL36:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL36:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL36:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL36:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL36:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL36:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL36:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL35:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL35:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL35:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL35:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL36:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL35:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL35:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL35:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL35:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL36:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL36:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL36:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL36:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC0 | input | TCELL35:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC1 | input | TCELL35:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC2 | input | TCELL35:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC3 | input | TCELL35:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC4 | input | TCELL35:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC5 | input | TCELL35:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD0 | input | TCELL35:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD1 | input | TCELL35:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD2 | input | TCELL35:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD3 | input | TCELL35:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD4 | input | TCELL35:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD5 | input | TCELL35:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL0 | input | TCELL37:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL1 | input | TCELL37:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL2 | input | TCELL37:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL3 | input | TCELL37:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL4 | input | TCELL37:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL5 | input | TCELL36:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN0 | input | TCELL38:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN1 | input | TCELL38:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN2 | input | TCELL38:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN3 | input | TCELL38:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN4 | input | TCELL38:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN5 | input | TCELL38:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL37:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL37:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL37:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL38:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL38:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL38:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL38:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL38:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL38:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL37:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL37:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL37:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL37:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL37:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL37:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL37:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL37:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL37:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_0 | input | TCELL38:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_1 | input | TCELL38:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_2 | input | TCELL37:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN0 | input | TCELL35:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN1 | input | TCELL35:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN2 | input | TCELL35:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN3 | input | TCELL35:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RST | input | TCELL34:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST0 | input | TCELL34:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST1 | input | TCELL34:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST2 | input | TCELL34:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST3 | input | TCELL34:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST4 | input | TCELL34:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST5 | input | TCELL34:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST0 | input | TCELL34:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST1 | input | TCELL34:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST2 | input | TCELL34:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST3 | input | TCELL34:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST4 | input | TCELL34:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST5 | input | TCELL34:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT0 | input | TCELL35:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT1 | input | TCELL35:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT2 | input | TCELL35:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT3 | input | TCELL35:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT4 | input | TCELL34:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT5 | input | TCELL34:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WREN0 | input | TCELL34:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WREN1 | input | TCELL34:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WREN2 | input | TCELL34:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WREN3 | input | TCELL34:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_0 | input | TCELL39:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_1 | input | TCELL39:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_2 | input | TCELL39:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_3 | input | TCELL39:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_4 | input | TCELL39:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_5 | input | TCELL39:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_6 | input | TCELL39:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_7 | input | TCELL39:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_0 | input | TCELL39:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_1 | input | TCELL39:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_2 | input | TCELL39:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_3 | input | TCELL39:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_4 | input | TCELL39:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_5 | input | TCELL39:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_6 | input | TCELL39:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_7 | input | TCELL39:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_0 | input | TCELL38:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_1 | input | TCELL38:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_2 | input | TCELL38:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_3 | input | TCELL38:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_4 | input | TCELL38:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_5 | input | TCELL38:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_6 | input | TCELL38:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_7 | input | TCELL38:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_0 | input | TCELL37:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_1 | input | TCELL37:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_2 | input | TCELL37:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_3 | input | TCELL37:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_4 | input | TCELL37:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_5 | input | TCELL37:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_6 | input | TCELL37:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_7 | input | TCELL38:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_0 | input | TCELL37:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_1 | input | TCELL37:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_2 | input | TCELL37:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_3 | input | TCELL37:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_4 | input | TCELL37:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_5 | input | TCELL37:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_6 | input | TCELL37:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_7 | input | TCELL37:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_0 | input | TCELL37:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_1 | input | TCELL37:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_2 | input | TCELL37:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_3 | input | TCELL37:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_4 | input | TCELL37:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_5 | input | TCELL37:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_6 | input | TCELL37:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_7 | input | TCELL37:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR0 | input | TCELL38:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR1 | input | TCELL38:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR2 | input | TCELL38:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR3 | input | TCELL38:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR4 | input | TCELL38:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR5 | input | TCELL38:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR6 | input | TCELL38:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR7 | input | TCELL38:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_NIBBLE_SEL | input | TCELL37:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA0 | input | TCELL38:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA1 | input | TCELL38:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA10 | input | TCELL38:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA11 | input | TCELL38:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA12 | input | TCELL38:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA13 | input | TCELL38:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA14 | input | TCELL38:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA15 | input | TCELL38:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA2 | input | TCELL38:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA3 | input | TCELL38:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA4 | input | TCELL38:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA5 | input | TCELL38:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA6 | input | TCELL38:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA7 | input | TCELL38:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA8 | input | TCELL38:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA9 | input | TCELL38:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P4_CLB2RIU_WR_EN | input | TCELL38:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT0 | output | TCELL37:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT1 | output | TCELL37:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT2 | output | TCELL37:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT3 | output | TCELL37:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT4 | output | TCELL37:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P4_IOB2CLB_DFT5 | output | TCELL37:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_FIFO_EMPTY | output | TCELL35:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_FIXDLY_RDY | output | TCELL35:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_GT_STATUS | output | TCELL35:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL37:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL37:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL37:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL37:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL36:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL36:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL36:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL36:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL36:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL36:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL36:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL36:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL37:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL36:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL36:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL36:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL36:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL36:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL36:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL36:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL36:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL36:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL36:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL37:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL36:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL36:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL36:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL36:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL36:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL36:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL36:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL36:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL36:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL36:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL37:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL36:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL36:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL36:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL35:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL35:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL35:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL35:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL35:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL35:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL35:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL37:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL35:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL35:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL35:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL35:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL37:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL37:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL37:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL37:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_0 | output | TCELL37:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_1 | output | TCELL37:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_2 | output | TCELL37:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_0 | output | TCELL37:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_1 | output | TCELL37:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_2 | output | TCELL37:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_MASTER_PD | output | TCELL35:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_PHY_RDY | output | TCELL35:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_0 | output | TCELL39:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_1 | output | TCELL39:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_2 | output | TCELL39:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_3 | output | TCELL39:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_4 | output | TCELL39:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_5 | output | TCELL39:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_6 | output | TCELL39:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_7 | output | TCELL39:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_0 | output | TCELL39:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_1 | output | TCELL39:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_2 | output | TCELL39:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_3 | output | TCELL39:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_4 | output | TCELL39:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_5 | output | TCELL39:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_6 | output | TCELL39:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_7 | output | TCELL39:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_0 | output | TCELL39:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_1 | output | TCELL39:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_2 | output | TCELL39:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_3 | output | TCELL39:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_4 | output | TCELL39:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_5 | output | TCELL39:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_6 | output | TCELL39:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_7 | output | TCELL39:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_0 | output | TCELL38:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_1 | output | TCELL38:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_2 | output | TCELL38:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_3 | output | TCELL38:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_4 | output | TCELL38:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_5 | output | TCELL38:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_6 | output | TCELL38:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_7 | output | TCELL39:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_0 | output | TCELL38:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_1 | output | TCELL38:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_2 | output | TCELL38:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_3 | output | TCELL38:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_4 | output | TCELL38:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_5 | output | TCELL38:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_6 | output | TCELL38:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_7 | output | TCELL38:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_0 | output | TCELL38:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_1 | output | TCELL38:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_2 | output | TCELL38:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_3 | output | TCELL38:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_4 | output | TCELL38:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_5 | output | TCELL38:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_6 | output | TCELL38:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_7 | output | TCELL38:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA0 | output | TCELL38:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA1 | output | TCELL38:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA10 | output | TCELL37:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA11 | output | TCELL37:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA12 | output | TCELL37:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA13 | output | TCELL37:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA14 | output | TCELL37:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA15 | output | TCELL37:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA2 | output | TCELL38:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA3 | output | TCELL38:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA4 | output | TCELL38:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA5 | output | TCELL38:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA6 | output | TCELL38:OUT.1.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA7 | output | TCELL38:OUT.0.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA8 | output | TCELL37:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA9 | output | TCELL37:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P4_RIU2CLB_VALID | output | TCELL38:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_CLB2MC_DIV_CLK | input | TCELL30:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P5_CLB2PHY_CTRL_CLK | input | TCELL30:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DLYCTL_EN_VTC | input | TCELL27:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL27:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL27:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL27:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL27:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL32:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL32:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_FIFO_CLK | input | TCELL30:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P5_CLB2PHY_FIFO_RDEN | input | TCELL32:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE0 | input | TCELL27:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE1 | input | TCELL27:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE2 | input | TCELL27:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE3 | input | TCELL27:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE4 | input | TCELL27:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE5 | input | TCELL27:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL33:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL33:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL33:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL33:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL33:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL33:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE0 | input | TCELL28:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE1 | input | TCELL28:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE2 | input | TCELL28:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE3 | input | TCELL28:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE4 | input | TCELL28:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE5 | input | TCELL27:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL32:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL32:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL32:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL32:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL32:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL32:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL32:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL32:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL32:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL32:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL32:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL32:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL32:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL32:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL32:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL32:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL32:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL32:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL32:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL32:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL32:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL32:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL32:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL32:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL32:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL32:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL32:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL32:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL32:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL32:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL32:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL32:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL31:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL31:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL32:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL31:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL31:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL31:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL31:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL31:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL31:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL30:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL30:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL30:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL30:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL32:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL30:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL30:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL30:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL30:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL32:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL32:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL32:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL32:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC0 | input | TCELL29:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC1 | input | TCELL29:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC2 | input | TCELL29:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC3 | input | TCELL28:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC4 | input | TCELL28:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC5 | input | TCELL28:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD0 | input | TCELL29:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD1 | input | TCELL29:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD2 | input | TCELL29:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD3 | input | TCELL29:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD4 | input | TCELL29:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD5 | input | TCELL29:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL0 | input | TCELL33:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL1 | input | TCELL33:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL2 | input | TCELL33:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL3 | input | TCELL33:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL4 | input | TCELL32:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL5 | input | TCELL32:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN0 | input | TCELL33:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN1 | input | TCELL33:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN2 | input | TCELL33:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN3 | input | TCELL33:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN4 | input | TCELL33:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN5 | input | TCELL33:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL33:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL33:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL33:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL33:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL33:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL33:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL33:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL33:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL33:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL33:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL33:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL33:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL33:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL33:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL33:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL33:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL33:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL33:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_0 | input | TCELL33:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_1 | input | TCELL33:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_2 | input | TCELL33:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN0 | input | TCELL32:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN1 | input | TCELL32:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN2 | input | TCELL32:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN3 | input | TCELL32:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RST | input | TCELL29:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST0 | input | TCELL30:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST1 | input | TCELL30:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST2 | input | TCELL30:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST3 | input | TCELL30:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST4 | input | TCELL30:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST5 | input | TCELL30:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST0 | input | TCELL29:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST1 | input | TCELL29:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST2 | input | TCELL29:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST3 | input | TCELL29:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST4 | input | TCELL29:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST5 | input | TCELL29:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT0 | input | TCELL31:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT1 | input | TCELL31:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT2 | input | TCELL31:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT3 | input | TCELL31:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT4 | input | TCELL31:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT5 | input | TCELL31:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WREN0 | input | TCELL31:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WREN1 | input | TCELL31:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WREN2 | input | TCELL30:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WREN3 | input | TCELL30:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_0 | input | TCELL26:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_1 | input | TCELL26:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_2 | input | TCELL27:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_3 | input | TCELL26:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_4 | input | TCELL27:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_5 | input | TCELL26:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_6 | input | TCELL27:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_7 | input | TCELL26:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_0 | input | TCELL27:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_1 | input | TCELL27:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_2 | input | TCELL27:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_3 | input | TCELL27:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_4 | input | TCELL27:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_5 | input | TCELL27:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_6 | input | TCELL27:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_7 | input | TCELL27:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_0 | input | TCELL27:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_1 | input | TCELL27:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_2 | input | TCELL27:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_3 | input | TCELL27:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_4 | input | TCELL27:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_5 | input | TCELL27:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_6 | input | TCELL27:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_7 | input | TCELL27:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_0 | input | TCELL27:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_1 | input | TCELL27:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_2 | input | TCELL27:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_3 | input | TCELL27:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_4 | input | TCELL27:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_5 | input | TCELL27:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_6 | input | TCELL27:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_7 | input | TCELL27:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_0 | input | TCELL27:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_1 | input | TCELL27:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_2 | input | TCELL27:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_3 | input | TCELL27:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_4 | input | TCELL27:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_5 | input | TCELL27:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_6 | input | TCELL27:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_7 | input | TCELL27:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_0 | input | TCELL28:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_1 | input | TCELL28:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_2 | input | TCELL28:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_3 | input | TCELL28:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_4 | input | TCELL28:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_5 | input | TCELL28:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_6 | input | TCELL28:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_7 | input | TCELL28:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR0 | input | TCELL33:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR1 | input | TCELL33:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR2 | input | TCELL33:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR3 | input | TCELL33:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR4 | input | TCELL33:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR5 | input | TCELL33:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR6 | input | TCELL33:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR7 | input | TCELL33:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_NIBBLE_SEL | input | TCELL34:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA0 | input | TCELL34:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA1 | input | TCELL34:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA10 | input | TCELL34:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA11 | input | TCELL34:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA12 | input | TCELL34:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA13 | input | TCELL34:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA14 | input | TCELL33:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA15 | input | TCELL33:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA2 | input | TCELL34:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA3 | input | TCELL34:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA4 | input | TCELL34:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA5 | input | TCELL34:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA6 | input | TCELL34:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA7 | input | TCELL34:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA8 | input | TCELL34:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA9 | input | TCELL34:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P5_CLB2RIU_WR_EN | input | TCELL34:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT0 | output | TCELL32:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT1 | output | TCELL32:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT2 | output | TCELL32:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT3 | output | TCELL32:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT4 | output | TCELL32:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P5_IOB2CLB_DFT5 | output | TCELL32:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_FIFO_EMPTY | output | TCELL29:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_FIXDLY_RDY | output | TCELL29:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_GT_STATUS | output | TCELL28:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL32:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL32:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL31:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL31:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL31:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL31:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL31:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL31:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL31:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL31:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL32:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL32:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL32:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL32:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL32:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL31:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL31:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL31:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL31:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL31:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL31:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL31:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL31:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL32:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL31:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL30:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL30:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL30:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL30:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL30:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL30:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL30:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL30:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL30:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL32:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL30:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL29:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL29:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL29:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL29:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL29:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL29:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL29:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL29:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL29:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL32:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL29:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL29:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL28:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL28:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL32:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL32:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL32:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL31:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_0 | output | TCELL32:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_1 | output | TCELL32:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_2 | output | TCELL32:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_0 | output | TCELL32:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_1 | output | TCELL32:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_2 | output | TCELL32:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_MASTER_PD | output | TCELL28:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_PHY_RDY | output | TCELL28:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_0 | output | TCELL29:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_1 | output | TCELL29:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_2 | output | TCELL29:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_3 | output | TCELL29:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_4 | output | TCELL29:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_5 | output | TCELL28:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_6 | output | TCELL29:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_7 | output | TCELL28:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_0 | output | TCELL29:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_1 | output | TCELL29:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_2 | output | TCELL29:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_3 | output | TCELL29:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_4 | output | TCELL29:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_5 | output | TCELL29:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_6 | output | TCELL29:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_7 | output | TCELL29:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_0 | output | TCELL30:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_1 | output | TCELL30:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_2 | output | TCELL30:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_3 | output | TCELL30:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_4 | output | TCELL30:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_5 | output | TCELL29:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_6 | output | TCELL30:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_7 | output | TCELL29:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_0 | output | TCELL30:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_1 | output | TCELL30:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_2 | output | TCELL30:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_3 | output | TCELL30:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_4 | output | TCELL30:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_5 | output | TCELL30:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_6 | output | TCELL30:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_7 | output | TCELL30:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_0 | output | TCELL30:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_1 | output | TCELL30:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_2 | output | TCELL31:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_3 | output | TCELL30:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_4 | output | TCELL31:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_5 | output | TCELL30:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_6 | output | TCELL31:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_7 | output | TCELL30:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_0 | output | TCELL31:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_1 | output | TCELL31:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_2 | output | TCELL31:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_3 | output | TCELL31:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_4 | output | TCELL31:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_5 | output | TCELL31:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_6 | output | TCELL31:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_7 | output | TCELL31:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA0 | output | TCELL33:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA1 | output | TCELL33:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA10 | output | TCELL33:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA11 | output | TCELL33:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA12 | output | TCELL33:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA13 | output | TCELL32:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA14 | output | TCELL32:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA15 | output | TCELL32:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA2 | output | TCELL33:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA3 | output | TCELL33:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA4 | output | TCELL33:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA5 | output | TCELL33:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA6 | output | TCELL33:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA7 | output | TCELL33:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA8 | output | TCELL33:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA9 | output | TCELL33:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P5_RIU2CLB_VALID | output | TCELL32:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P6_CLB2MC_DIV_CLK | input | TCELL18:IMUX.CTRL.3 |
| IF_HSM_CLB2PHY_P6_CLB2PHY_CTRL_CLK | input | TCELL18:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL18:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL18:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL18:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL18:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL18:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL18:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_FIFO_CLK | input | TCELL18:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE0 | input | TCELL18:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE1 | input | TCELL18:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE2 | input | TCELL18:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE3 | input | TCELL18:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE4 | input | TCELL18:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE5 | input | TCELL18:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL19:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL19:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL19:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL19:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL18:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL18:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE0 | input | TCELL18:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE1 | input | TCELL18:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE2 | input | TCELL18:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE3 | input | TCELL18:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE4 | input | TCELL18:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE5 | input | TCELL18:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC0 | input | TCELL18:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC1 | input | TCELL18:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC2 | input | TCELL18:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC3 | input | TCELL18:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC4 | input | TCELL18:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC5 | input | TCELL18:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD0 | input | TCELL18:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD1 | input | TCELL18:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD2 | input | TCELL18:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD3 | input | TCELL18:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD4 | input | TCELL18:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD5 | input | TCELL18:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL19:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL19:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL19:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_0_BIT2 | input | TCELL19:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL19:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL19:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL19:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL19:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL19:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL19:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL19:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL19:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL19:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL19:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL19:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL19:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_0 | input | TCELL19:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_1 | input | TCELL19:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_2 | input | TCELL19:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RST | input | TCELL18:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST0 | input | TCELL18:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST1 | input | TCELL18:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST2 | input | TCELL18:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST3 | input | TCELL18:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST4 | input | TCELL18:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST5 | input | TCELL18:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST0 | input | TCELL18:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST1 | input | TCELL18:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST2 | input | TCELL18:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST3 | input | TCELL18:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST4 | input | TCELL18:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST5 | input | TCELL18:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2RIU_NIBBLE_SEL | input | TCELL16:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P6_CLB2RIU_WR_EN | input | TCELL19:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT0 | output | TCELL17:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT1 | output | TCELL17:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT2 | output | TCELL17:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT3 | output | TCELL17:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT4 | output | TCELL17:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P6_IOB2CLB_DFT5 | output | TCELL17:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_FIFO_EMPTY | output | TCELL15:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_FIXDLY_RDY | output | TCELL15:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_GT_STATUS | output | TCELL15:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL17:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL17:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL16:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL16:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL16:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL16:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL16:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL16:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL16:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL16:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL16:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL16:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL17:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL16:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL16:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL16:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL16:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL16:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL16:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL16:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL16:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL16:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL16:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL17:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL16:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL16:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL16:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL16:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL16:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL16:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL15:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL15:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL15:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL15:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL17:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL15:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL15:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL15:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL15:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL15:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL15:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL15:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL15:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL15:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL15:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL17:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL15:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL15:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL15:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL15:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL16:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL16:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL16:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL16:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_0 | output | TCELL17:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_1 | output | TCELL17:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_2 | output | TCELL17:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_0 | output | TCELL17:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_1 | output | TCELL17:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_2 | output | TCELL17:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_MASTER_PD | output | TCELL15:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P6_PHY2CLB_PHY_RDY | output | TCELL15:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P6_RIU2CLB_VALID | output | TCELL17:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P7_CLB2MC_DIV_CLK | input | TCELL11:IMUX.CTRL.3 |
| IF_HSM_CLB2PHY_P7_CLB2PHY_CTRL_CLK | input | TCELL11:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL10:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL10:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL10:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL10:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL10:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL10:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_FIFO_CLK | input | TCELL11:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE0 | input | TCELL10:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE1 | input | TCELL10:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE2 | input | TCELL10:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE3 | input | TCELL10:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE4 | input | TCELL10:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE5 | input | TCELL10:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL12:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL12:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL12:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL12:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL12:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL12:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE0 | input | TCELL10:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE1 | input | TCELL10:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE2 | input | TCELL10:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE3 | input | TCELL10:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE4 | input | TCELL10:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE5 | input | TCELL10:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL12:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL12:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL12:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL12:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL12:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL12:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL12:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL12:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL12:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL12:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL12:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL12:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL12:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL12:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL11:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL11:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL11:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL11:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL11:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL11:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL11:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL11:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL11:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL12:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL11:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL11:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL11:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL11:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL11:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL11:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL11:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL11:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL11:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL11:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL12:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL11:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL11:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL11:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL11:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL11:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL11:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL11:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL11:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL11:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL11:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL12:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL11:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL11:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL11:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL11:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL12:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL12:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL12:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL12:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC0 | input | TCELL10:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC1 | input | TCELL10:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC2 | input | TCELL10:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC3 | input | TCELL10:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC4 | input | TCELL10:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC5 | input | TCELL10:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD0 | input | TCELL11:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD1 | input | TCELL11:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD2 | input | TCELL10:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD3 | input | TCELL10:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD4 | input | TCELL10:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD5 | input | TCELL10:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN0 | input | TCELL13:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN1 | input | TCELL13:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN2 | input | TCELL13:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN3 | input | TCELL13:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN4 | input | TCELL13:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN5 | input | TCELL13:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL13:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL12:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL12:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL13:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL13:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL13:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL13:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL13:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL13:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL13:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL13:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL13:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL12:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL12:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL12:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL12:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL12:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL12:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_0 | input | TCELL13:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_1 | input | TCELL13:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_2 | input | TCELL13:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RST | input | TCELL9:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST0 | input | TCELL10:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST1 | input | TCELL10:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST2 | input | TCELL10:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST3 | input | TCELL10:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST4 | input | TCELL10:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST5 | input | TCELL10:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST0 | input | TCELL10:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST1 | input | TCELL10:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST2 | input | TCELL10:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST3 | input | TCELL10:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST4 | input | TCELL10:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST5 | input | TCELL9:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2RIU_NIBBLE_SEL | input | TCELL13:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P7_CLB2RIU_WR_EN | input | TCELL13:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT0 | output | TCELL13:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT1 | output | TCELL13:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT2 | output | TCELL13:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT3 | output | TCELL13:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT4 | output | TCELL13:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P7_IOB2CLB_DFT5 | output | TCELL13:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_FIFO_EMPTY | output | TCELL11:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_FIXDLY_RDY | output | TCELL11:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_GT_STATUS | output | TCELL11:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL13:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL13:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL12:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL12:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL12:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL12:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL12:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL12:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL12:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL12:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL12:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL12:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL13:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL12:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL12:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL12:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL12:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL12:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL12:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL12:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL12:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL12:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL12:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL13:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL12:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL12:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL12:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL12:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL12:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL11:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL11:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL11:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL11:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL11:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL13:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL11:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL11:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL11:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL11:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL11:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL11:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL11:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL11:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL11:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL11:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL13:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL11:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL11:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL11:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL11:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL12:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL12:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL12:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL12:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_0 | output | TCELL13:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_1 | output | TCELL13:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_2 | output | TCELL13:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_0 | output | TCELL13:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_1 | output | TCELL13:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_2 | output | TCELL13:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_MASTER_PD | output | TCELL11:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P7_PHY2CLB_PHY_RDY | output | TCELL11:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P7_RIU2CLB_VALID | output | TCELL13:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P8_CLB2MC_DIV_CLK | input | TCELL6:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P8_CLB2PHY_CTRL_CLK | input | TCELL6:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL6:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL6:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL6:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL6:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL6:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL6:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_FIFO_CLK | input | TCELL6:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE0 | input | TCELL6:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE1 | input | TCELL6:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE2 | input | TCELL6:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE3 | input | TCELL6:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE4 | input | TCELL6:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE5 | input | TCELL6:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL8:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL8:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL8:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL8:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL8:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL8:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE0 | input | TCELL6:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE1 | input | TCELL6:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE2 | input | TCELL6:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE3 | input | TCELL6:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE4 | input | TCELL6:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE5 | input | TCELL6:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL8:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL8:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL8:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL8:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL8:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL7:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL7:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL7:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL7:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL7:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL7:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL7:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL8:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL7:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL7:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL7:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL7:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL7:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL7:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL7:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL7:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL7:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL7:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL8:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL7:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL7:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL7:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL7:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL7:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL7:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL7:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL7:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL7:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL7:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL8:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL7:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL7:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL6:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL6:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL6:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL6:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL6:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL6:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL6:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL6:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL8:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL6:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL6:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL6:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL6:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL8:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL8:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL8:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL8:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC0 | input | TCELL6:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC1 | input | TCELL6:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC2 | input | TCELL6:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC3 | input | TCELL6:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC4 | input | TCELL6:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC5 | input | TCELL6:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD0 | input | TCELL6:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD1 | input | TCELL6:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD2 | input | TCELL6:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD3 | input | TCELL6:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD4 | input | TCELL6:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD5 | input | TCELL6:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN0 | input | TCELL9:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN1 | input | TCELL9:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN2 | input | TCELL9:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN3 | input | TCELL9:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN4 | input | TCELL9:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN5 | input | TCELL9:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL9:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL9:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL9:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL9:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL9:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL9:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL9:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL9:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL9:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL9:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL9:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL9:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL8:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL8:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL8:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL8:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL8:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL8:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_0 | input | TCELL9:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_1 | input | TCELL9:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_2 | input | TCELL9:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RST | input | TCELL5:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST0 | input | TCELL6:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST1 | input | TCELL6:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST2 | input | TCELL6:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST3 | input | TCELL6:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST4 | input | TCELL6:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST5 | input | TCELL5:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST0 | input | TCELL5:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST1 | input | TCELL5:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST2 | input | TCELL5:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST3 | input | TCELL5:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST4 | input | TCELL5:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST5 | input | TCELL5:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2RIU_NIBBLE_SEL | input | TCELL5:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P8_CLB2RIU_WR_EN | input | TCELL9:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT0 | output | TCELL7:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT1 | output | TCELL7:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT2 | output | TCELL6:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT3 | output | TCELL6:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT4 | output | TCELL6:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P8_IOB2CLB_DFT5 | output | TCELL6:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_FIFO_EMPTY | output | TCELL4:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_FIXDLY_RDY | output | TCELL4:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_GT_STATUS | output | TCELL4:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL6:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL6:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL6:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL6:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL6:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL6:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL6:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL6:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL6:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL6:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL6:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL6:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL6:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL6:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL6:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL6:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL6:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL6:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL5:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL5:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL5:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL5:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL5:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL6:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL5:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL5:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL5:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL5:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL5:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL5:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL5:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL5:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL5:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL5:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL6:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL5:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL5:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL5:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL5:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL5:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL5:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL5:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL5:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL5:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL5:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL6:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL5:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL5:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL5:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL5:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL6:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL6:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL6:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL6:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_0 | output | TCELL7:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_1 | output | TCELL7:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_2 | output | TCELL7:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_0 | output | TCELL7:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_1 | output | TCELL7:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_2 | output | TCELL7:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_MASTER_PD | output | TCELL4:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P8_PHY2CLB_PHY_RDY | output | TCELL4:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P8_RIU2CLB_VALID | output | TCELL7:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P9_CLB2MC_DIV_CLK | input | TCELL1:IMUX.CTRL.0 |
| IF_HSM_CLB2PHY_P9_CLB2PHY_CTRL_CLK | input | TCELL1:IMUX.CTRL.1 |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS0 | input | TCELL1:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS1 | input | TCELL1:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS2 | input | TCELL1:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS3 | input | TCELL1:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS4 | input | TCELL1:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS5 | input | TCELL1:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_FIFO_CLK | input | TCELL1:IMUX.CTRL.2 |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE0 | input | TCELL1:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE1 | input | TCELL1:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE2 | input | TCELL1:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE3 | input | TCELL1:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE4 | input | TCELL1:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE5 | input | TCELL1:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL4:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL4:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL4:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL4:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL4:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL4:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE0 | input | TCELL1:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE1 | input | TCELL1:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE2 | input | TCELL1:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE3 | input | TCELL1:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE4 | input | TCELL1:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE5 | input | TCELL1:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL4:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL4:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL3:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL3:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL3:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL3:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL3:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL3:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL3:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL3:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL3:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL3:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL4:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL3:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL3:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL3:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL3:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL3:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL3:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL3:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL3:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL3:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL3:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL4:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL3:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL3:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN32 | input | TCELL3:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN33 | input | TCELL3:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN34 | input | TCELL3:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN35 | input | TCELL3:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN36 | input | TCELL3:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN37 | input | TCELL3:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN38 | input | TCELL3:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN39 | input | TCELL3:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL4:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN40 | input | TCELL3:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN41 | input | TCELL3:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN42 | input | TCELL3:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN43 | input | TCELL3:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN44 | input | TCELL3:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN45 | input | TCELL3:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN46 | input | TCELL3:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN47 | input | TCELL3:IMUX.IMUX.20.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN48 | input | TCELL3:IMUX.IMUX.2.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN49 | input | TCELL3:IMUX.IMUX.19.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL4:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN50 | input | TCELL3:IMUX.IMUX.18.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN51 | input | TCELL3:IMUX.IMUX.1.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN52 | input | TCELL3:IMUX.IMUX.17.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN53 | input | TCELL3:IMUX.IMUX.16.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL4:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL3:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL3:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL3:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC0 | input | TCELL2:IMUX.IMUX.14.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC1 | input | TCELL2:IMUX.IMUX.43.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC2 | input | TCELL2:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC3 | input | TCELL2:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC4 | input | TCELL1:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC5 | input | TCELL1:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD0 | input | TCELL3:IMUX.IMUX.0.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD1 | input | TCELL2:IMUX.IMUX.47.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD2 | input | TCELL2:IMUX.IMUX.46.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD3 | input | TCELL2:IMUX.IMUX.15.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD4 | input | TCELL2:IMUX.IMUX.45.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD5 | input | TCELL2:IMUX.IMUX.44.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN0 | input | TCELL4:IMUX.IMUX.13.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN1 | input | TCELL4:IMUX.IMUX.41.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN2 | input | TCELL4:IMUX.IMUX.40.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN3 | input | TCELL4:IMUX.IMUX.12.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN4 | input | TCELL4:IMUX.IMUX.39.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN5 | input | TCELL4:IMUX.IMUX.38.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 | input | TCELL4:IMUX.IMUX.7.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 | input | TCELL4:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 | input | TCELL4:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 | input | TCELL4:IMUX.IMUX.10.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 | input | TCELL4:IMUX.IMUX.35.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 | input | TCELL4:IMUX.IMUX.34.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 | input | TCELL4:IMUX.IMUX.11.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 | input | TCELL4:IMUX.IMUX.37.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 | input | TCELL4:IMUX.IMUX.36.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 | input | TCELL4:IMUX.IMUX.8.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 | input | TCELL4:IMUX.IMUX.31.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 | input | TCELL4:IMUX.IMUX.30.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC0 | input | TCELL4:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC1 | input | TCELL4:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC2 | input | TCELL4:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC3 | input | TCELL4:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC4 | input | TCELL4:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC5 | input | TCELL4:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_0 | input | TCELL4:IMUX.IMUX.9.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_1 | input | TCELL4:IMUX.IMUX.33.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_2 | input | TCELL4:IMUX.IMUX.32.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RST | input | TCELL1:IMUX.IMUX.21.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST0 | input | TCELL1:IMUX.IMUX.29.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST1 | input | TCELL1:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST2 | input | TCELL1:IMUX.IMUX.6.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST3 | input | TCELL1:IMUX.IMUX.27.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST4 | input | TCELL1:IMUX.IMUX.26.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST5 | input | TCELL1:IMUX.IMUX.5.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST0 | input | TCELL1:IMUX.IMUX.25.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST1 | input | TCELL1:IMUX.IMUX.24.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST2 | input | TCELL1:IMUX.IMUX.4.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST3 | input | TCELL1:IMUX.IMUX.23.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST4 | input | TCELL1:IMUX.IMUX.22.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST5 | input | TCELL1:IMUX.IMUX.3.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2RIU_NIBBLE_SEL | input | TCELL0:IMUX.IMUX.28.DELAY |
| IF_HSM_CLB2PHY_P9_CLB2RIU_WR_EN | input | TCELL4:IMUX.IMUX.42.DELAY |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT0 | output | TCELL4:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT1 | output | TCELL3:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT2 | output | TCELL3:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT3 | output | TCELL3:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT4 | output | TCELL3:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P9_IOB2CLB_DFT5 | output | TCELL3:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_FIFO_EMPTY | output | TCELL1:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_FIXDLY_RDY | output | TCELL1:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_GT_STATUS | output | TCELL1:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL3:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL3:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL3:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL3:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL3:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL3:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL3:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL3:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL3:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL3:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL3:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL3:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL3:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL3:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL3:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL3:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL3:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL2:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL2:OUT.30.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL2:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL2:OUT.28.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL2:OUT.27.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL2:OUT.26.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL3:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL2:OUT.25.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL2:OUT.24.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT32 | output | TCELL2:OUT.23.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT33 | output | TCELL2:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT34 | output | TCELL2:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT35 | output | TCELL2:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT36 | output | TCELL2:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT37 | output | TCELL2:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT38 | output | TCELL2:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT39 | output | TCELL2:OUT.16.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL3:OUT.22.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT40 | output | TCELL2:OUT.15.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT41 | output | TCELL2:OUT.14.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT42 | output | TCELL2:OUT.13.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT43 | output | TCELL2:OUT.12.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT44 | output | TCELL2:OUT.11.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT45 | output | TCELL2:OUT.10.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT46 | output | TCELL2:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT47 | output | TCELL2:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT48 | output | TCELL2:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT49 | output | TCELL2:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL3:OUT.21.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT50 | output | TCELL2:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT51 | output | TCELL2:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT52 | output | TCELL2:OUT.3.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT53 | output | TCELL2:OUT.2.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL3:OUT.20.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL3:OUT.19.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL3:OUT.18.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL3:OUT.17.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_0 | output | TCELL4:OUT.6.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_1 | output | TCELL4:OUT.5.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_2 | output | TCELL4:OUT.4.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_0 | output | TCELL4:OUT.9.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_1 | output | TCELL4:OUT.8.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_2 | output | TCELL4:OUT.7.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_MASTER_PD | output | TCELL1:OUT.31.TMIN |
| IF_HSM_CLB2PHY_P9_PHY2CLB_PHY_RDY | output | TCELL1:OUT.29.TMIN |
| IF_HSM_CLB2PHY_P9_RIU2CLB_VALID | output | TCELL4:OUT.10.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARADDR_PAR0 | input | TCELL54:IMUX.IMUX.8.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARADDR_PAR1 | input | TCELL54:IMUX.IMUX.31.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARBURST0 | input | TCELL54:IMUX.IMUX.6.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARBURST1 | input | TCELL54:IMUX.IMUX.27.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARLOCK | input | TCELL54:IMUX.IMUX.28.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT0 | input | TCELL54:IMUX.IMUX.30.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT1 | input | TCELL54:IMUX.IMUX.7.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT2 | input | TCELL54:IMUX.IMUX.29.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARREADY | output | TCELL54:OUT.17.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE0 | input | TCELL54:IMUX.IMUX.26.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE1 | input | TCELL54:IMUX.IMUX.5.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE2 | input | TCELL54:IMUX.IMUX.25.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARVALID | input | TCELL54:IMUX.IMUX.24.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWADDR_PAR0 | input | TCELL54:IMUX.IMUX.12.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWADDR_PAR1 | input | TCELL54:IMUX.IMUX.39.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWBURST0 | input | TCELL54:IMUX.IMUX.10.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWBURST1 | input | TCELL54:IMUX.IMUX.35.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWLOCK | input | TCELL54:IMUX.IMUX.36.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT0 | input | TCELL54:IMUX.IMUX.38.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT1 | input | TCELL54:IMUX.IMUX.11.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT2 | input | TCELL54:IMUX.IMUX.37.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWREADY | output | TCELL54:OUT.18.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE0 | input | TCELL54:IMUX.IMUX.34.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE1 | input | TCELL54:IMUX.IMUX.9.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE2 | input | TCELL54:IMUX.IMUX.33.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWVALID | input | TCELL54:IMUX.IMUX.32.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID0 | output | TCELL55:OUT.20.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID1 | output | TCELL55:OUT.19.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID2 | output | TCELL55:OUT.18.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID3 | output | TCELL55:OUT.17.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID4 | output | TCELL55:OUT.16.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID5 | output | TCELL55:OUT.15.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID6 | output | TCELL55:OUT.14.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID7 | output | TCELL55:OUT.13.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BREADY | input | TCELL54:IMUX.IMUX.43.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BRESP0 | output | TCELL55:OUT.22.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BRESP1 | output | TCELL55:OUT.21.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BVALID | output | TCELL55:OUT.12.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR0 | output | TCELL55:OUT.11.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR1 | output | TCELL55:OUT.10.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR2 | output | TCELL55:OUT.9.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR3 | output | TCELL55:OUT.8.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR4 | output | TCELL55:OUT.7.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR5 | output | TCELL55:OUT.6.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR6 | output | TCELL55:OUT.5.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR7 | output | TCELL55:OUT.4.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID0 | output | TCELL54:OUT.29.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID1 | output | TCELL54:OUT.28.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID2 | output | TCELL54:OUT.27.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID3 | output | TCELL54:OUT.26.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID4 | output | TCELL54:OUT.25.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID5 | output | TCELL54:OUT.24.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID6 | output | TCELL54:OUT.23.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID7 | output | TCELL54:OUT.22.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RLAST | output | TCELL54:OUT.21.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RPOISON | output | TCELL55:OUT.3.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RREADY | input | TCELL54:IMUX.IMUX.42.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RRESP0 | output | TCELL54:OUT.31.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RRESP1 | output | TCELL54:OUT.30.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RVALID | output | TCELL54:OUT.20.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WLAST | input | TCELL54:IMUX.IMUX.41.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WPOISON | input | TCELL54:IMUX.IMUX.13.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WREADY | output | TCELL54:OUT.19.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WVALID | input | TCELL54:IMUX.IMUX.40.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARADDR_PAR0 | input | TCELL14:IMUX.IMUX.36.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARADDR_PAR1 | input | TCELL14:IMUX.IMUX.10.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARBURST0 | input | TCELL14:IMUX.IMUX.32.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARBURST1 | input | TCELL14:IMUX.IMUX.8.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARLOCK | input | TCELL14:IMUX.IMUX.33.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT0 | input | TCELL14:IMUX.IMUX.35.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT1 | input | TCELL14:IMUX.IMUX.34.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT2 | input | TCELL14:IMUX.IMUX.9.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARREADY | output | TCELL13:OUT.23.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE0 | input | TCELL14:IMUX.IMUX.31.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE1 | input | TCELL14:IMUX.IMUX.30.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE2 | input | TCELL14:IMUX.IMUX.7.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARVALID | input | TCELL14:IMUX.IMUX.29.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWADDR_PAR0 | input | TCELL14:IMUX.IMUX.44.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWADDR_PAR1 | input | TCELL14:IMUX.IMUX.14.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWBURST0 | input | TCELL14:IMUX.IMUX.40.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWBURST1 | input | TCELL14:IMUX.IMUX.12.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWLOCK | input | TCELL14:IMUX.IMUX.41.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT0 | input | TCELL14:IMUX.IMUX.43.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT1 | input | TCELL14:IMUX.IMUX.42.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT2 | input | TCELL14:IMUX.IMUX.13.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWREADY | output | TCELL13:OUT.31.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE0 | input | TCELL14:IMUX.IMUX.39.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE1 | input | TCELL14:IMUX.IMUX.38.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE2 | input | TCELL14:IMUX.IMUX.11.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWVALID | input | TCELL14:IMUX.IMUX.37.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID0 | output | TCELL15:OUT.6.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID1 | output | TCELL15:OUT.5.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID2 | output | TCELL15:OUT.4.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID3 | output | TCELL15:OUT.3.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID4 | output | TCELL15:OUT.2.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID5 | output | TCELL15:OUT.1.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID6 | output | TCELL15:OUT.0.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID7 | output | TCELL14:OUT.31.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BREADY | input | TCELL15:IMUX.IMUX.16.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BRESP0 | output | TCELL15:OUT.8.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BRESP1 | output | TCELL15:OUT.7.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BVALID | output | TCELL14:OUT.30.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR0 | output | TCELL14:OUT.29.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR1 | output | TCELL14:OUT.28.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR2 | output | TCELL14:OUT.27.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR3 | output | TCELL14:OUT.26.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR4 | output | TCELL14:OUT.25.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR5 | output | TCELL14:OUT.24.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR6 | output | TCELL14:OUT.23.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR7 | output | TCELL14:OUT.22.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID0 | output | TCELL14:OUT.18.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID1 | output | TCELL14:OUT.17.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID2 | output | TCELL14:OUT.16.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID3 | output | TCELL14:OUT.15.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID4 | output | TCELL14:OUT.14.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID5 | output | TCELL14:OUT.13.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID6 | output | TCELL14:OUT.12.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID7 | output | TCELL14:OUT.11.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RLAST | output | TCELL14:OUT.10.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RPOISON | output | TCELL14:OUT.21.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RREADY | input | TCELL14:IMUX.IMUX.47.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RRESP0 | output | TCELL14:OUT.20.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RRESP1 | output | TCELL14:OUT.19.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RVALID | output | TCELL14:OUT.9.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WLAST | input | TCELL14:IMUX.IMUX.15.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WPOISON | input | TCELL14:IMUX.IMUX.46.DELAY |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WREADY | output | TCELL14:OUT.6.TMIN |
| IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WVALID | input | TCELL14:IMUX.IMUX.45.DELAY |
| IF_UBLAZE_FABRIC_BLI2UB_CLK | input | TCELL43:IMUX.CTRL.0 |
| IF_UBLAZE_FABRIC_BLI2UB_DRAM_POWER_OFF_REQ | input | TCELL44:IMUX.IMUX.31.DELAY |
| IF_UBLAZE_FABRIC_BLI2UB_RST | input | TCELL44:IMUX.IMUX.6.DELAY |
| IF_UBLAZE_FABRIC_BLI2UB_SELF_REF_REQ | input | TCELL44:IMUX.IMUX.30.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_CAPTURE | input | TCELL44:IMUX.IMUX.8.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_DRCK | input | TCELL44:IMUX.IMUX.32.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_RESET | input | TCELL44:IMUX.IMUX.33.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_SEL | input | TCELL44:IMUX.IMUX.9.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_SHIFT | input | TCELL44:IMUX.IMUX.34.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_TCK | input | TCELL44:IMUX.IMUX.35.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_TDI | input | TCELL44:IMUX.IMUX.10.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_TDO | output | TCELL44:OUT.25.TMIN |
| IF_UBLAZE_FABRIC_BSCAN_EXT_TMS | input | TCELL44:IMUX.IMUX.36.DELAY |
| IF_UBLAZE_FABRIC_BSCAN_EXT_UPDATE | input | TCELL44:IMUX.IMUX.37.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARBURST0 | output | TCELL44:OUT.28.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARBURST1 | output | TCELL44:OUT.16.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARREADY | input | TCELL44:IMUX.IMUX.24.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE0 | output | TCELL44:OUT.29.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE1 | output | TCELL44:OUT.15.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE2 | output | TCELL44:OUT.30.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_ARVALID | output | TCELL44:OUT.17.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_AWREADY | input | TCELL44:IMUX.IMUX.21.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE0 | output | TCELL44:OUT.31.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE1 | output | TCELL44:OUT.10.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE2 | output | TCELL45:OUT.3.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_AWVALID | output | TCELL44:OUT.11.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_BREADY | output | TCELL44:OUT.14.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_BRESP0 | input | TCELL44:IMUX.IMUX.23.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_BRESP1 | input | TCELL44:IMUX.IMUX.22.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_BVALID | input | TCELL44:IMUX.IMUX.4.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_RLAST | input | TCELL44:IMUX.IMUX.25.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_RREADY | output | TCELL44:OUT.18.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_RRESP0 | input | TCELL44:IMUX.IMUX.26.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_RRESP1 | input | TCELL44:IMUX.IMUX.5.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_RVALID | input | TCELL44:IMUX.IMUX.27.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_WLAST | output | TCELL44:OUT.12.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_DC_WREADY | input | TCELL44:IMUX.IMUX.3.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_DC_WVALID | output | TCELL44:OUT.13.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN0 | output | TCELL44:OUT.8.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN1 | output | TCELL44:OUT.7.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN2 | output | TCELL44:OUT.6.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN3 | output | TCELL45:OUT.4.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN4 | output | TCELL45:OUT.5.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN5 | output | TCELL45:OUT.6.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN6 | output | TCELL45:OUT.7.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN7 | output | TCELL45:OUT.8.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_ARREADY | input | TCELL44:IMUX.IMUX.1.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_IC_RLAST | input | TCELL44:IMUX.IMUX.18.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_IC_RREADY | output | TCELL44:OUT.9.TMIN |
| IF_UBLAZE_FABRIC_M_AXI_IC_RRESP0 | input | TCELL44:IMUX.IMUX.2.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_IC_RRESP1 | input | TCELL44:IMUX.IMUX.19.DELAY |
| IF_UBLAZE_FABRIC_M_AXI_IC_RVALID | input | TCELL44:IMUX.IMUX.20.DELAY |
| IF_UBLAZE_FABRIC_UB2BLI_DRAM_POWER_OFF_DONE | output | TCELL44:OUT.22.TMIN |
| IF_UBLAZE_FABRIC_UB2BLI_SELF_REF_DONE | output | TCELL44:OUT.21.TMIN |
| IF_UBLAZE_FABRIC_UB_MISC_IN0 | input | TCELL44:IMUX.IMUX.7.DELAY |
| IF_UBLAZE_FABRIC_UB_MISC_IN1 | input | TCELL44:IMUX.IMUX.29.DELAY |
| IF_UBLAZE_FABRIC_UB_MISC_IN2 | input | TCELL44:IMUX.IMUX.28.DELAY |
| IF_UBLAZE_FABRIC_UB_MISC_OUT0 | output | TCELL44:OUT.20.TMIN |
| IF_UBLAZE_FABRIC_UB_MISC_OUT1 | output | TCELL44:OUT.19.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTRDCI_USR_RST | input | TCELL26:IMUX.IMUX.14.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_RST_N | input | TCELL26:IMUX.IMUX.27.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I1 | input | TCELL26:IMUX.IMUX.42.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I10 | input | TCELL26:IMUX.IMUX.36.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I11 | input | TCELL26:IMUX.IMUX.10.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I12 | input | TCELL26:IMUX.IMUX.35.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I13 | input | TCELL26:IMUX.IMUX.34.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I14 | input | TCELL26:IMUX.IMUX.9.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I15 | input | TCELL26:IMUX.IMUX.33.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I16 | input | TCELL26:IMUX.IMUX.32.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I17 | input | TCELL26:IMUX.IMUX.8.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I18 | input | TCELL26:IMUX.IMUX.31.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I19 | input | TCELL26:IMUX.IMUX.30.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I2 | input | TCELL26:IMUX.IMUX.13.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I20 | input | TCELL26:IMUX.IMUX.7.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I21 | input | TCELL26:IMUX.IMUX.29.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I22 | input | TCELL26:IMUX.IMUX.28.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I23 | input | TCELL26:IMUX.IMUX.6.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I3 | input | TCELL26:IMUX.IMUX.41.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I4 | input | TCELL26:IMUX.IMUX.40.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I5 | input | TCELL26:IMUX.IMUX.12.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I6 | input | TCELL26:IMUX.IMUX.39.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I7 | input | TCELL26:IMUX.IMUX.38.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I8 | input | TCELL26:IMUX.IMUX.11.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I9 | input | TCELL26:IMUX.IMUX.37.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I_CLOCK | input | TCELL26:IMUX.IMUX.43.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2IOB_PUDC_B | input | TCELL26:IMUX.IMUX.26.DELAY |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_LOCK | output | TCELL28:OUT.3.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O0 | output | TCELL28:OUT.24.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O1 | output | TCELL28:OUT.23.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O10 | output | TCELL28:OUT.14.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O11 | output | TCELL28:OUT.13.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O12 | output | TCELL28:OUT.12.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O13 | output | TCELL28:OUT.11.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O14 | output | TCELL28:OUT.10.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O15 | output | TCELL28:OUT.9.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O16 | output | TCELL28:OUT.8.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O17 | output | TCELL28:OUT.7.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O18 | output | TCELL28:OUT.6.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O19 | output | TCELL28:OUT.5.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O2 | output | TCELL28:OUT.22.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O20 | output | TCELL28:OUT.4.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O21 | output | TCELL27:OUT.29.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O22 | output | TCELL27:OUT.31.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O23 | output | TCELL27:OUT.30.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O3 | output | TCELL28:OUT.21.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O4 | output | TCELL28:OUT.20.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O5 | output | TCELL28:OUT.19.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O6 | output | TCELL28:OUT.18.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O7 | output | TCELL28:OUT.17.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O8 | output | TCELL28:OUT.16.TMIN |
| IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O9 | output | TCELL28:OUT.15.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG0 | input | TCELL2:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG1 | input | TCELL39:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG10 | input | TCELL57:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG2 | input | TCELL52:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG3 | input | TCELL58:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG4 | input | TCELL30:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG5 | input | TCELL49:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG6 | input | TCELL40:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG7 | input | TCELL33:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG8 | input | TCELL13:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG9 | input | TCELL24:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CLK_B | input | TCELL40:IMUX.BYP.7.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN0 | input | TCELL13:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN1 | input | TCELL19:IMUX.BYP.6.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN10 | input | TCELL19:IMUX.BYP.14.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN2 | input | TCELL45:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN3 | input | TCELL15:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN4 | input | TCELL41:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN5 | input | TCELL42:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN6 | input | TCELL44:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN7 | input | TCELL19:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN8 | input | TCELL48:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN9 | input | TCELL30:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN0 | input | TCELL59:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN1 | input | TCELL34:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN10 | input | TCELL8:IMUX.BYP.12.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN2 | input | TCELL8:IMUX.BYP.6.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN3 | input | TCELL28:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN4 | input | TCELL44:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN5 | input | TCELL37:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN6 | input | TCELL43:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN7 | input | TCELL11:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN8 | input | TCELL52:IMUX.BYP.6.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN9 | input | TCELL52:IMUX.BYP.13.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_EDT_UPDT_B | input | TCELL45:IMUX.BYP.12.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_EN_B | input | TCELL55:IMUX.BYP.7.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN0 | input | TCELL52:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN1 | input | TCELL57:IMUX.BYP.7.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN10 | input | TCELL13:IMUX.BYP.13.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN2 | input | TCELL22:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN3 | input | TCELL6:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN4 | input | TCELL13:IMUX.BYP.6.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN5 | input | TCELL21:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN6 | input | TCELL7:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN7 | input | TCELL55:IMUX.BYP.8.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN8 | input | TCELL45:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN9 | input | TCELL26:IMUX.BYP.10.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_MODE_RST_B | input | TCELL39:IMUX.BYP.9.DELAY |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION0 | output | TCELL34:OUT.12.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION1 | output | TCELL34:OUT.29.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION10 | output | TCELL34:OUT.14.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION11 | output | TCELL34:OUT.25.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION2 | output | TCELL34:OUT.9.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION3 | output | TCELL34:OUT.28.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION4 | output | TCELL34:OUT.7.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION5 | output | TCELL34:OUT.27.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION6 | output | TCELL34:OUT.6.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION7 | output | TCELL34:OUT.30.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION8 | output | TCELL34:OUT.13.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION9 | output | TCELL34:OUT.26.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT0 | output | TCELL34:OUT.4.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT1 | output | TCELL35:OUT.11.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT10 | output | TCELL34:OUT.11.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT2 | output | TCELL33:OUT.28.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT3 | output | TCELL35:OUT.12.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT4 | output | TCELL34:OUT.3.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT5 | output | TCELL35:OUT.13.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT6 | output | TCELL33:OUT.29.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT7 | output | TCELL35:OUT.14.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT8 | output | TCELL34:OUT.21.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT9 | output | TCELL35:OUT.15.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT0 | output | TCELL34:OUT.15.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT1 | output | TCELL34:OUT.24.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT10 | output | TCELL33:OUT.30.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT2 | output | TCELL34:OUT.16.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT3 | output | TCELL34:OUT.23.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT4 | output | TCELL34:OUT.20.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT5 | output | TCELL34:OUT.31.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT6 | output | TCELL34:OUT.22.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT7 | output | TCELL35:OUT.3.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT8 | output | TCELL34:OUT.8.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT9 | output | TCELL35:OUT.4.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT0 | output | TCELL35:OUT.5.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT1 | output | TCELL34:OUT.17.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT10 | output | TCELL35:OUT.10.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT2 | output | TCELL35:OUT.6.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT3 | output | TCELL34:OUT.19.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT4 | output | TCELL35:OUT.7.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT5 | output | TCELL34:OUT.18.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT6 | output | TCELL35:OUT.8.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT7 | output | TCELL34:OUT.5.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT8 | output | TCELL35:OUT.9.TMIN |
| IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT9 | output | TCELL34:OUT.10.TMIN |
| IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK0 | output | TCELL0:OUT.10.TMIN |
| IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK10 | output | TCELL0:OUT.9.TMIN |
| IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK9 | output | TCELL0:OUT.8.TMIN |
| IJTAG_RESET_TAP | input | TCELL34:IMUX.IMUX.28.DELAY |
| IJTAG_RESET_TAP_O | output | TCELL33:OUT.18.TMIN |
| IJTAG_TDI_EXT | input | TCELL34:IMUX.IMUX.9.DELAY |
| IJTAG_TDI_RETURN_EXT | input | TCELL34:IMUX.IMUX.34.DELAY |
| IJTAG_TDO_OABUT | output | TCELL33:OUT.26.TMIN |
| IJTAG_TDO_RETURN_EXT | output | TCELL33:OUT.27.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL46:OUT.26.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL46:OUT.25.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL46:OUT.16.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL46:OUT.15.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL46:OUT.14.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL46:OUT.13.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL46:OUT.12.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL46:OUT.11.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL46:OUT.24.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL46:OUT.23.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL46:OUT.22.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL46:OUT.21.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL46:OUT.20.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL46:OUT.19.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL46:OUT.18.TMIN |
| MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL46:OUT.17.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL47:OUT.13.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL47:OUT.12.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL47:OUT.11.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL47:OUT.10.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL47:OUT.9.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL47:OUT.8.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL47:OUT.7.TMIN |
| MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL47:OUT.6.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL46:OUT.10.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL46:OUT.9.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL45:OUT.29.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL45:OUT.28.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL45:OUT.27.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL45:OUT.26.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL45:OUT.25.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL45:OUT.24.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL46:OUT.8.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL46:OUT.7.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL46:OUT.6.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL46:OUT.5.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL46:OUT.4.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL46:OUT.3.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL45:OUT.31.TMIN |
| MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL45:OUT.30.TMIN |
| MAXI_DCAWBURST_1_0_NIB2_53_52_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL47:OUT.19.TMIN |
| MAXI_DCAWBURST_1_0_NIB2_53_52_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL47:OUT.18.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL47:OUT.5.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL47:OUT.4.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL47:OUT.3.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL46:OUT.31.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL46:OUT.30.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL46:OUT.29.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL46:OUT.28.TMIN |
| MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL46:OUT.27.TMIN |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL42:IMUX.IMUX.3.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL42:IMUX.IMUX.21.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL41:IMUX.IMUX.47.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL41:IMUX.IMUX.46.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL41:IMUX.IMUX.15.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL41:IMUX.IMUX.45.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL41:IMUX.IMUX.44.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL41:IMUX.IMUX.14.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL41:IMUX.IMUX.43.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL41:IMUX.IMUX.42.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL41:IMUX.IMUX.13.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL41:IMUX.IMUX.41.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL42:IMUX.IMUX.20.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL41:IMUX.IMUX.40.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL41:IMUX.IMUX.12.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN22 | input | TCELL41:IMUX.IMUX.39.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN23 | input | TCELL41:IMUX.IMUX.38.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN24 | input | TCELL41:IMUX.IMUX.11.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN25 | input | TCELL41:IMUX.IMUX.37.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN26 | input | TCELL41:IMUX.IMUX.36.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN27 | input | TCELL41:IMUX.IMUX.10.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN28 | input | TCELL41:IMUX.IMUX.35.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN29 | input | TCELL41:IMUX.IMUX.34.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL42:IMUX.IMUX.2.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN30 | input | TCELL41:IMUX.IMUX.9.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN31 | input | TCELL41:IMUX.IMUX.33.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL42:IMUX.IMUX.19.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL42:IMUX.IMUX.18.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL42:IMUX.IMUX.1.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL42:IMUX.IMUX.17.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL42:IMUX.IMUX.16.DELAY |
| MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL42:IMUX.IMUX.0.DELAY |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL42:OUT.26.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL42:OUT.25.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL42:OUT.16.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL42:OUT.15.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL42:OUT.14.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL42:OUT.13.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL42:OUT.12.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL42:OUT.11.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT16 | output | TCELL42:OUT.10.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT17 | output | TCELL42:OUT.9.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT18 | output | TCELL42:OUT.8.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT19 | output | TCELL42:OUT.7.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL42:OUT.24.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT20 | output | TCELL42:OUT.6.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT21 | output | TCELL42:OUT.5.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT22 | output | TCELL42:OUT.4.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT23 | output | TCELL42:OUT.3.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT24 | output | TCELL42:OUT.2.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT25 | output | TCELL42:OUT.1.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT26 | output | TCELL42:OUT.0.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT27 | output | TCELL41:OUT.31.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT28 | output | TCELL41:OUT.30.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT29 | output | TCELL41:OUT.29.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL42:OUT.23.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT30 | output | TCELL41:OUT.28.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT31 | output | TCELL41:OUT.27.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL42:OUT.22.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL42:OUT.21.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL42:OUT.20.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL42:OUT.19.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL42:OUT.18.TMIN |
| MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL42:OUT.17.TMIN |
| MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL47:OUT.17.TMIN |
| MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL47:OUT.16.TMIN |
| MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL47:OUT.15.TMIN |
| MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL47:OUT.14.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL43:OUT.12.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL43:OUT.11.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT10 | output | TCELL43:OUT.2.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT11 | output | TCELL42:OUT.31.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT12 | output | TCELL42:OUT.30.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT13 | output | TCELL42:OUT.29.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT14 | output | TCELL42:OUT.28.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT15 | output | TCELL42:OUT.27.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL43:OUT.10.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT3 | output | TCELL43:OUT.9.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT4 | output | TCELL43:OUT.8.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT5 | output | TCELL43:OUT.7.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT6 | output | TCELL43:OUT.6.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT7 | output | TCELL43:OUT.5.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT8 | output | TCELL43:OUT.4.TMIN |
| MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT9 | output | TCELL43:OUT.3.TMIN |
| MAXI_ICARBURST_1_0_NIB3_52_51_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL43:OUT.17.TMIN |
| MAXI_ICARBURST_1_0_NIB3_52_51_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL43:OUT.16.TMIN |
| MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT0 | output | TCELL43:OUT.15.TMIN |
| MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT1 | output | TCELL43:OUT.14.TMIN |
| MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT2 | output | TCELL43:OUT.13.TMIN |
| MAXI_ICARVALID_NIB3_53_PHY2CLB_IODELAY_CNTVALUEOUT | output | TCELL43:OUT.18.TMIN |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN0 | input | TCELL42:IMUX.IMUX.36.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN1 | input | TCELL42:IMUX.IMUX.10.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN10 | input | TCELL42:IMUX.IMUX.7.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN11 | input | TCELL42:IMUX.IMUX.29.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN12 | input | TCELL42:IMUX.IMUX.28.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN13 | input | TCELL42:IMUX.IMUX.6.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN14 | input | TCELL42:IMUX.IMUX.27.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN15 | input | TCELL42:IMUX.IMUX.26.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN16 | input | TCELL42:IMUX.IMUX.5.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN17 | input | TCELL42:IMUX.IMUX.25.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN18 | input | TCELL42:IMUX.IMUX.24.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN19 | input | TCELL42:IMUX.IMUX.4.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN2 | input | TCELL42:IMUX.IMUX.35.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN20 | input | TCELL42:IMUX.IMUX.23.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN21 | input | TCELL42:IMUX.IMUX.22.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN3 | input | TCELL42:IMUX.IMUX.34.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN4 | input | TCELL42:IMUX.IMUX.9.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN5 | input | TCELL42:IMUX.IMUX.33.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN6 | input | TCELL42:IMUX.IMUX.32.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN7 | input | TCELL42:IMUX.IMUX.8.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN8 | input | TCELL42:IMUX.IMUX.31.DELAY |
| MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN9 | input | TCELL42:IMUX.IMUX.30.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC0 | input | TCELL42:IMUX.IMUX.40.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC1 | input | TCELL42:IMUX.IMUX.12.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC2 | input | TCELL42:IMUX.IMUX.39.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC3 | input | TCELL42:IMUX.IMUX.38.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC4 | input | TCELL42:IMUX.IMUX.11.DELAY |
| MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC5 | input | TCELL42:IMUX.IMUX.37.DELAY |
| MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_0 | input | TCELL42:IMUX.IMUX.42.DELAY |
| MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_1 | input | TCELL42:IMUX.IMUX.13.DELAY |
| MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_2 | input | TCELL42:IMUX.IMUX.41.DELAY |
| MAXI_ICRDATA_31_NIB3_CLB2RIU_WR_EN | input | TCELL42:IMUX.IMUX.43.DELAY |
| SELECT_DR | input | TCELL34:IMUX.IMUX.31.DELAY |
| SELECT_DR_O | output | TCELL33:OUT.22.TMIN |
| TEST_CLK_OUT0 | output | TCELL0:OUT.7.TMIN |
| TEST_CLK_OUT1 | output | TCELL0:OUT.6.TMIN |
Bel XP5IOB0
| Pin | Direction | Wires |
|---|
Bel XP5IOB1
| Pin | Direction | Wires |
|---|
Bel XP5IOB2
| Pin | Direction | Wires |
|---|
Bel XP5IOB3
| Pin | Direction | Wires |
|---|
Bel XP5IOB4
| Pin | Direction | Wires |
|---|
Bel XP5IOB5
| Pin | Direction | Wires |
|---|
Bel XP5IOB6
| Pin | Direction | Wires |
|---|
Bel XP5IOB7
| Pin | Direction | Wires |
|---|
Bel XP5IOB8
| Pin | Direction | Wires |
|---|
Bel XP5IOB9
| Pin | Direction | Wires |
|---|
Bel XP5IOB10
| Pin | Direction | Wires |
|---|
Bel XP5IOB11
| Pin | Direction | Wires |
|---|
Bel XP5IOB12
| Pin | Direction | Wires |
|---|
Bel XP5IOB13
| Pin | Direction | Wires |
|---|
Bel XP5IOB14
| Pin | Direction | Wires |
|---|
Bel XP5IOB15
| Pin | Direction | Wires |
|---|
Bel XP5IOB16
| Pin | Direction | Wires |
|---|
Bel XP5IOB17
| Pin | Direction | Wires |
|---|
Bel XP5IOB18
| Pin | Direction | Wires |
|---|
Bel XP5IOB19
| Pin | Direction | Wires |
|---|
Bel XP5IOB20
| Pin | Direction | Wires |
|---|
Bel XP5IOB21
| Pin | Direction | Wires |
|---|
Bel XP5IOB22
| Pin | Direction | Wires |
|---|
Bel XP5IOB23
| Pin | Direction | Wires |
|---|
Bel XP5IOB24
| Pin | Direction | Wires |
|---|
Bel XP5IOB25
| Pin | Direction | Wires |
|---|
Bel XP5IOB26
| Pin | Direction | Wires |
|---|
Bel XP5IOB27
| Pin | Direction | Wires |
|---|
Bel XP5IOB28
| Pin | Direction | Wires |
|---|
Bel XP5IOB29
| Pin | Direction | Wires |
|---|
Bel XP5IOB30
| Pin | Direction | Wires |
|---|
Bel XP5IOB31
| Pin | Direction | Wires |
|---|
Bel XP5IOB32
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF0
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF1
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF2
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF3
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF4
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF5
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF6
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF7
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF8
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF9
| Pin | Direction | Wires |
|---|
Bel XP5IO_VREF10
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS0
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS1
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS2
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS3
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS4
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS5
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS6
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS7
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS8
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS9
| Pin | Direction | Wires |
|---|
Bel X5PHY_LS10
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS0
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS1
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS2
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS3
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS4
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS5
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS6
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS7
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS8
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS9
| Pin | Direction | Wires |
|---|
Bel X5PHY_HS10
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT0
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT1
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT2
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT3
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT4
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT5
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT6
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT7
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT8
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT9
| Pin | Direction | Wires |
|---|
Bel X5PHY_PLL_SELECT10
| Pin | Direction | Wires |
|---|
Bel XP5PIO_CMU_ANA
| Pin | Direction | Wires |
|---|
Bel XP5PIO_CMU_DIG_TOP
| Pin | Direction | Wires |
|---|
Bel ABUS_SWITCH_XP5IO0
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL33:IMUX.IMUX.0.DELAY |
Bel ABUS_SWITCH_XP5IO1
| Pin | Direction | Wires |
|---|---|---|
| TEST_ANALOGBUS_SEL_B | input | TCELL34:IMUX.IMUX.0.DELAY |
Bel VCC_XP5IO
| Pin | Direction | Wires |
|---|
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:OUT.0.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_0 |
| TCELL0:OUT.1.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_1 |
| TCELL0:OUT.2.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_2 |
| TCELL0:OUT.3.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_3 |
| TCELL0:OUT.4.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_4 |
| TCELL0:OUT.5.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE0_5 |
| TCELL0:OUT.6.TMIN | LPDDRMC.TEST_CLK_OUT1 |
| TCELL0:OUT.7.TMIN | LPDDRMC.TEST_CLK_OUT0 |
| TCELL0:OUT.8.TMIN | LPDDRMC.IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK9 |
| TCELL0:OUT.9.TMIN | LPDDRMC.IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK10 |
| TCELL0:OUT.10.TMIN | LPDDRMC.IF_XPIO_MMCM_DMC_OABUT_XPIO_PHY_CLK0 |
| TCELL0:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_7 |
| TCELL0:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_5 |
| TCELL0:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_3 |
| TCELL0:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_1 |
| TCELL0:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_0 |
| TCELL0:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_2 |
| TCELL0:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_4 |
| TCELL0:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_215_208_NIB9_PHY2CLB_RD_DQ0_6 |
| TCELL0:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_7 |
| TCELL0:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_5 |
| TCELL0:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_3 |
| TCELL0:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_1 |
| TCELL0:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_0 |
| TCELL0:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_2 |
| TCELL0:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_4 |
| TCELL0:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_223_216_NIB9_PHY2CLB_RD_DQ1_6 |
| TCELL0:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_7 |
| TCELL0:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_5 |
| TCELL0:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_3 |
| TCELL0:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_1 |
| TCELL0:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_0 |
| TCELL0:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_7 |
| TCELL0:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_1 |
| TCELL0:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_4 |
| TCELL0:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_5 |
| TCELL0:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_0 |
| TCELL0:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_6 |
| TCELL0:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_5 |
| TCELL0:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_0 |
| TCELL0:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_6 |
| TCELL0:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_3 |
| TCELL0:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_2 |
| TCELL0:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_7 |
| TCELL0:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_1 |
| TCELL0:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_4 |
| TCELL0:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_5 |
| TCELL0:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_3 |
| TCELL0:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_0 |
| TCELL0:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_2 |
| TCELL0:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WDATA_215_208_NIB9_CLB2PHY_WR_DQ0_6 |
| TCELL0:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_7 |
| TCELL0:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_3 |
| TCELL0:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_1 |
| TCELL0:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_2 |
| TCELL0:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_WDATA_223_216_NIB9_CLB2PHY_WR_DQ1_4 |
| TCELL0:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2RIU_NIBBLE_SEL |
| TCELL0:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_7 |
| TCELL0:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_3 |
| TCELL0:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_1 |
| TCELL0:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_2 |
| TCELL0:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_WDATA_231_224_NIB9_CLB2PHY_WR_DQ2_4 |
| TCELL0:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_7 |
| TCELL0:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_5 |
| TCELL0:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_1 |
| TCELL0:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_0 |
| TCELL0:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_4 |
| TCELL0:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_WDATA_239_232_NIB9_CLB2PHY_WR_DQ3_6 |
| TCELL0:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_5 |
| TCELL0:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_3 |
| TCELL0:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_0 |
| TCELL0:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_2 |
| TCELL0:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_247_240_NIB9_CLB2PHY_WR_DQ4_6 |
| TCELL0:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_7 |
| TCELL1:OUT.0.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_2 |
| TCELL1:OUT.1.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_4 |
| TCELL1:OUT.2.TMIN | LPDDRMC.AXI1_RDATA_231_224_NIB9_PHY2CLB_RD_DQ2_6 |
| TCELL1:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_7 |
| TCELL1:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_5 |
| TCELL1:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_3 |
| TCELL1:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_1 |
| TCELL1:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_0 |
| TCELL1:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_2 |
| TCELL1:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_4 |
| TCELL1:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_239_232_NIB9_PHY2CLB_RD_DQ3_6 |
| TCELL1:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_7 |
| TCELL1:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_5 |
| TCELL1:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_3 |
| TCELL1:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_1 |
| TCELL1:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_0 |
| TCELL1:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_2 |
| TCELL1:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_4 |
| TCELL1:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_247_240_NIB9_PHY2CLB_RD_DQ4_6 |
| TCELL1:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_7 |
| TCELL1:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_5 |
| TCELL1:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_3 |
| TCELL1:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_1 |
| TCELL1:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_0 |
| TCELL1:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_2 |
| TCELL1:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_4 |
| TCELL1:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_255_248_NIB9_PHY2CLB_RD_DQ5_6 |
| TCELL1:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_FIFO_EMPTY |
| TCELL1:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_FIXDLY_RDY |
| TCELL1:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_PHY_RDY |
| TCELL1:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_GT_STATUS |
| TCELL1:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_MASTER_PD |
| TCELL1:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2MC_DIV_CLK |
| TCELL1:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_CTRL_CLK |
| TCELL1:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_FIFO_CLK |
| TCELL1:IMUX.BYP.10.DELAY | LPDDRMC.FABRIC_APB_RST_N |
| TCELL1:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_1 |
| TCELL1:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_4 |
| TCELL1:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST5 |
| TCELL1:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST2 |
| TCELL1:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST5 |
| TCELL1:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST2 |
| TCELL1:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL1:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL1:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE5 |
| TCELL1:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE2 |
| TCELL1:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE5 |
| TCELL1:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE2 |
| TCELL1:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC5 |
| TCELL1:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA14 |
| TCELL1:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA11 |
| TCELL1:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_5 |
| TCELL1:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_3 |
| TCELL1:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_0 |
| TCELL1:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_2 |
| TCELL1:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_255_248_NIB9_CLB2PHY_WR_DQ5_6 |
| TCELL1:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RST |
| TCELL1:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST4 |
| TCELL1:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST3 |
| TCELL1:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST1 |
| TCELL1:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_TXBIT_RST0 |
| TCELL1:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST4 |
| TCELL1:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST3 |
| TCELL1:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST1 |
| TCELL1:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_RXBIT_RST0 |
| TCELL1:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL1:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL1:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL1:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL1:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE4 |
| TCELL1:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE3 |
| TCELL1:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE1 |
| TCELL1:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IBUF_DISABLE0 |
| TCELL1:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE4 |
| TCELL1:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE3 |
| TCELL1:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE1 |
| TCELL1:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CE0 |
| TCELL1:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC4 |
| TCELL1:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA15 |
| TCELL1:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA13 |
| TCELL1:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA12 |
| TCELL1:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA10 |
| TCELL1:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA9 |
| TCELL2:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL2:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL2:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL2:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL2:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL2:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL2:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL2:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL2:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL2:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL2:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL2:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL2:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL2:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL2:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL2:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL2:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL2:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL2:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL2:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL2:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL2:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL2:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL2:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL2:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL2:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL2:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL2:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL2:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL2:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL2:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT12 |
| TCELL2:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG0 |
| TCELL2:IMUX.BYP.11.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT5 |
| TCELL2:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA8 |
| TCELL2:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA5 |
| TCELL2:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA2 |
| TCELL2:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR7 |
| TCELL2:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR4 |
| TCELL2:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR1 |
| TCELL2:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN2 |
| TCELL2:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT5 |
| TCELL2:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT2 |
| TCELL2:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_AWADDR_43_NIB9_CLB2PHY_FIFO_RDEN |
| TCELL2:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN1 |
| TCELL2:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL4 |
| TCELL2:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL1 |
| TCELL2:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC3 |
| TCELL2:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC0 |
| TCELL2:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD3 |
| TCELL2:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA7 |
| TCELL2:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA6 |
| TCELL2:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA4 |
| TCELL2:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA3 |
| TCELL2:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA1 |
| TCELL2:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WDATA_207_192_NIB9_CLB2RIU_WR_DATA0 |
| TCELL2:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR6 |
| TCELL2:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR5 |
| TCELL2:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR3 |
| TCELL2:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR2 |
| TCELL2:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WSTRB_31_24_NIB9_CLB2RIU_ADDR0 |
| TCELL2:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN3 |
| TCELL2:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN1 |
| TCELL2:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_AWADDR_36_33_NIB9_CLB2PHY_WREN0 |
| TCELL2:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT4 |
| TCELL2:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT3 |
| TCELL2:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT1 |
| TCELL2:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_AWADDR_42_37_NIB9_CLB2PHY_T_TXBIT0 |
| TCELL2:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN3 |
| TCELL2:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN2 |
| TCELL2:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_ARADDR_36_33_NIB9_CLB2PHY_RDEN0 |
| TCELL2:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL5 |
| TCELL2:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL3 |
| TCELL2:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL2 |
| TCELL2:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_ARADDR_42_37_NIB9_CLB2PHY_IODELAY_SEL0 |
| TCELL2:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_ARADDR_43_NIB9_CLB2PHY_DLYCTL_EN_VTC |
| TCELL2:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC2 |
| TCELL2:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_INC1 |
| TCELL2:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD5 |
| TCELL2:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD4 |
| TCELL2:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD2 |
| TCELL2:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD1 |
| TCELL3:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL3:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL3:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL3:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL3:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL3:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL3:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL3:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL3:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL3:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL3:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL3:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL3:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL3:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL3:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL3:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL3:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL3:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL3:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL3:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL3:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL3:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL3:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL3:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL3:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT5 |
| TCELL3:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT4 |
| TCELL3:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT3 |
| TCELL3:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT2 |
| TCELL3:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT1 |
| TCELL3:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_EN_N_EXT |
| TCELL3:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_LD0 |
| TCELL3:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL3:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL3:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL3:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL3:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL3:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL3:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL3:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL3:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL3:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL3:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL3:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL3:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL3:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL3:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL3:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL3:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL3:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL3:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL3:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL3:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL3:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL3:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL3:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL3:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL3:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL3:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL3:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL3:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL3:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL3:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL3:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL3:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL3:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL3:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL3:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL3:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL3:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL3:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL3:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL3:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL3:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL3:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL3:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL3:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL3:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL3:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL4:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_IOB2CLB_DFT0 |
| TCELL4:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_2 |
| TCELL4:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_1 |
| TCELL4:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_0_0 |
| TCELL4:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_2 |
| TCELL4:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_1 |
| TCELL4:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_PHY2CLB_LP_I_1_0 |
| TCELL4:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P9_RIU2CLB_VALID |
| TCELL4:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA15 |
| TCELL4:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA14 |
| TCELL4:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA13 |
| TCELL4:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA12 |
| TCELL4:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA11 |
| TCELL4:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA10 |
| TCELL4:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA9 |
| TCELL4:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA8 |
| TCELL4:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA7 |
| TCELL4:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA6 |
| TCELL4:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA5 |
| TCELL4:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA4 |
| TCELL4:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA3 |
| TCELL4:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA2 |
| TCELL4:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA1 |
| TCELL4:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_207_192_NIB9_RIU2CLB_RD_DATA0 |
| TCELL4:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_FIFO_EMPTY |
| TCELL4:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_FIXDLY_RDY |
| TCELL4:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_PHY_RDY |
| TCELL4:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_GT_STATUS |
| TCELL4:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_MASTER_PD |
| TCELL4:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL4:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL4:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL4:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL4:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL4:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL4:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL4:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL4:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL4:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_0 |
| TCELL4:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL4:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL4:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN3 |
| TCELL4:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN0 |
| TCELL4:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA14 |
| TCELL4:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA11 |
| TCELL4:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL4:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL4:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL4:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL4:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL4:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL4:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL4:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL4:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL4:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL4:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL4:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL4:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL4:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL4:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL4:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL4:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_2 |
| TCELL4:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_PD_EN_1_1 |
| TCELL4:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL4:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL4:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL4:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL4:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN5 |
| TCELL4:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN4 |
| TCELL4:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN2 |
| TCELL4:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2PHY_KEEPER_EN1 |
| TCELL4:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P9_CLB2RIU_WR_EN |
| TCELL4:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA15 |
| TCELL4:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA13 |
| TCELL4:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA12 |
| TCELL4:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA10 |
| TCELL4:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA9 |
| TCELL5:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL5:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL5:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL5:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL5:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL5:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL5:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL5:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL5:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL5:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL5:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL5:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL5:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL5:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL5:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL5:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL5:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL5:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL5:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL5:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL5:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL5:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL5:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL5:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL5:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL5:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL5:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL5:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL5:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL5:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT8 |
| TCELL5:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA8 |
| TCELL5:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA5 |
| TCELL5:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA2 |
| TCELL5:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR7 |
| TCELL5:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR4 |
| TCELL5:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR1 |
| TCELL5:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN2 |
| TCELL5:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT5 |
| TCELL5:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT2 |
| TCELL5:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_AWADDR_32_NIB8_CLB2PHY_FIFO_RDEN |
| TCELL5:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN1 |
| TCELL5:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL4 |
| TCELL5:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL1 |
| TCELL5:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2RIU_NIBBLE_SEL |
| TCELL5:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST4 |
| TCELL5:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST1 |
| TCELL5:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA7 |
| TCELL5:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA6 |
| TCELL5:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA4 |
| TCELL5:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA3 |
| TCELL5:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA1 |
| TCELL5:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WDATA_143_128_NIB8_CLB2RIU_WR_DATA0 |
| TCELL5:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR6 |
| TCELL5:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR5 |
| TCELL5:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR3 |
| TCELL5:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR2 |
| TCELL5:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WSTRB_23_16_NIB8_CLB2RIU_ADDR0 |
| TCELL5:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN3 |
| TCELL5:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN1 |
| TCELL5:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_AWADDR_25_22_NIB8_CLB2PHY_WREN0 |
| TCELL5:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT4 |
| TCELL5:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT3 |
| TCELL5:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT1 |
| TCELL5:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_AWADDR_31_26_NIB8_CLB2PHY_T_TXBIT0 |
| TCELL5:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN3 |
| TCELL5:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN2 |
| TCELL5:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_ARADDR_25_22_NIB8_CLB2PHY_RDEN0 |
| TCELL5:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL5 |
| TCELL5:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL3 |
| TCELL5:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL2 |
| TCELL5:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_ARADDR_31_26_NIB8_CLB2PHY_IODELAY_SEL0 |
| TCELL5:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_ARADDR_32_NIB8_CLB2PHY_DLYCTL_EN_VTC |
| TCELL5:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RST |
| TCELL5:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST5 |
| TCELL5:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST3 |
| TCELL5:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST2 |
| TCELL5:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_TXBIT_RST0 |
| TCELL5:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST5 |
| TCELL6:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL6:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL6:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL6:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL6:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL6:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL6:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL6:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL6:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL6:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL6:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL6:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL6:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL6:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL6:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL6:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL6:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL6:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL6:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL6:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL6:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL6:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL6:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL6:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL6:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL6:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT5 |
| TCELL6:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT4 |
| TCELL6:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT3 |
| TCELL6:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT2 |
| TCELL6:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_FIFO_CLK |
| TCELL6:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2MC_DIV_CLK |
| TCELL6:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_CTRL_CLK |
| TCELL6:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CNTRL_CHNL_IN_EXT_DDRMC0 |
| TCELL6:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN3 |
| TCELL6:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST2 |
| TCELL6:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL6:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL6:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE5 |
| TCELL6:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE2 |
| TCELL6:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE5 |
| TCELL6:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE2 |
| TCELL6:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC5 |
| TCELL6:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC2 |
| TCELL6:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD5 |
| TCELL6:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD2 |
| TCELL6:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL6:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL6:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL6:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL6:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST4 |
| TCELL6:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST3 |
| TCELL6:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST1 |
| TCELL6:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_RXBIT_RST0 |
| TCELL6:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL6:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL6:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL6:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL6:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE4 |
| TCELL6:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE3 |
| TCELL6:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE1 |
| TCELL6:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IBUF_DISABLE0 |
| TCELL6:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE4 |
| TCELL6:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE3 |
| TCELL6:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE1 |
| TCELL6:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CE0 |
| TCELL6:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC4 |
| TCELL6:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC3 |
| TCELL6:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC1 |
| TCELL6:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_INC0 |
| TCELL6:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD4 |
| TCELL6:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD3 |
| TCELL6:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD1 |
| TCELL6:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_LD0 |
| TCELL6:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL6:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL6:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL6:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL6:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL6:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL6:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL6:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL7:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT1 |
| TCELL7:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_IOB2CLB_DFT0 |
| TCELL7:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_2 |
| TCELL7:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_1 |
| TCELL7:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_0_0 |
| TCELL7:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_2 |
| TCELL7:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_1 |
| TCELL7:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_PHY2CLB_LP_I_1_0 |
| TCELL7:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P8_RIU2CLB_VALID |
| TCELL7:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA15 |
| TCELL7:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA14 |
| TCELL7:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA13 |
| TCELL7:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA12 |
| TCELL7:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA11 |
| TCELL7:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA10 |
| TCELL7:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA9 |
| TCELL7:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA8 |
| TCELL7:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA7 |
| TCELL7:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA6 |
| TCELL7:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA5 |
| TCELL7:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA4 |
| TCELL7:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA3 |
| TCELL7:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA2 |
| TCELL7:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA1 |
| TCELL7:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_143_128_NIB8_RIU2CLB_RD_DATA0 |
| TCELL7:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_6 |
| TCELL7:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_4 |
| TCELL7:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_2 |
| TCELL7:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_0 |
| TCELL7:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN6 |
| TCELL7:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL7:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL7:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL7:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL7:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL7:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL7:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL7:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL7:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_2 |
| TCELL7:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_3 |
| TCELL7:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL7:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL7:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_4 |
| TCELL7:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_1 |
| TCELL7:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_7 |
| TCELL7:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL7:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL7:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL7:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL7:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL7:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL7:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL7:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL7:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL7:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL7:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL7:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL7:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL7:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL7:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL7:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL7:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_6 |
| TCELL7:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_4 |
| TCELL7:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_0 |
| TCELL7:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_1 |
| TCELL7:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_5 |
| TCELL7:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_WDATA_191_184_NIB8_CLB2PHY_WR_DQ5_7 |
| TCELL7:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL7:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL7:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL7:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_6 |
| TCELL7:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_2 |
| TCELL7:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_0 |
| TCELL7:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_3 |
| TCELL7:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_183_176_NIB8_CLB2PHY_WR_DQ4_5 |
| TCELL7:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_6 |
| TCELL7:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_4 |
| TCELL8:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_1 |
| TCELL8:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_3 |
| TCELL8:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_5 |
| TCELL8:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_191_184_NIB8_PHY2CLB_RD_DQ5_7 |
| TCELL8:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_6 |
| TCELL8:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_4 |
| TCELL8:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_2 |
| TCELL8:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_0 |
| TCELL8:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_1 |
| TCELL8:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_3 |
| TCELL8:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_5 |
| TCELL8:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_183_176_NIB8_PHY2CLB_RD_DQ4_7 |
| TCELL8:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_6 |
| TCELL8:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_4 |
| TCELL8:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_2 |
| TCELL8:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_0 |
| TCELL8:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_1 |
| TCELL8:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_3 |
| TCELL8:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_5 |
| TCELL8:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_175_168_NIB8_PHY2CLB_RD_DQ3_7 |
| TCELL8:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_6 |
| TCELL8:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_4 |
| TCELL8:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_2 |
| TCELL8:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_0 |
| TCELL8:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_1 |
| TCELL8:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_3 |
| TCELL8:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_5 |
| TCELL8:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_167_160_NIB8_PHY2CLB_RD_DQ2_7 |
| TCELL8:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_6 |
| TCELL8:IMUX.BYP.6.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN2 |
| TCELL8:IMUX.BYP.12.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN10 |
| TCELL8:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_1 |
| TCELL8:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_7 |
| TCELL8:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL8:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL8:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_2 |
| TCELL8:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_3 |
| TCELL8:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_6 |
| TCELL8:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_0 |
| TCELL8:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_5 |
| TCELL8:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL8:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL8:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL8:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL8:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL8:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL8:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_2 |
| TCELL8:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_0 |
| TCELL8:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_3 |
| TCELL8:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_175_168_NIB8_CLB2PHY_WR_DQ3_5 |
| TCELL8:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL8:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL8:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL8:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL8:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_6 |
| TCELL8:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_4 |
| TCELL8:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_0 |
| TCELL8:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_1 |
| TCELL8:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_5 |
| TCELL8:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_WDATA_167_160_NIB8_CLB2PHY_WR_DQ2_7 |
| TCELL8:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_4 |
| TCELL8:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_2 |
| TCELL8:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_1 |
| TCELL8:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_3 |
| TCELL8:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_WDATA_159_152_NIB8_CLB2PHY_WR_DQ1_7 |
| TCELL8:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL8:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL8:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL8:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL8:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL8:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL8:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL8:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL8:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL8:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL8:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL8:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL8:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL9:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_4 |
| TCELL9:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_2 |
| TCELL9:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_0 |
| TCELL9:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_1 |
| TCELL9:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_3 |
| TCELL9:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_5 |
| TCELL9:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_159_152_NIB8_PHY2CLB_RD_DQ1_7 |
| TCELL9:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_6 |
| TCELL9:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_4 |
| TCELL9:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_2 |
| TCELL9:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_0 |
| TCELL9:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_1 |
| TCELL9:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_3 |
| TCELL9:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_5 |
| TCELL9:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_151_144_NIB8_PHY2CLB_RD_DQ0_7 |
| TCELL9:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_7 |
| TCELL9:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_5 |
| TCELL9:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_3 |
| TCELL9:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_1 |
| TCELL9:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_0 |
| TCELL9:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_2 |
| TCELL9:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_4 |
| TCELL9:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_87_80_NIB7_PHY2CLB_RD_DQ0_6 |
| TCELL9:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_7 |
| TCELL9:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_5 |
| TCELL9:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_3 |
| TCELL9:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_1 |
| TCELL9:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_0 |
| TCELL9:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_2 |
| TCELL9:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL9:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL9:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_2 |
| TCELL9:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL9:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL9:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN5 |
| TCELL9:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_4 |
| TCELL9:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_1 |
| TCELL9:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_7 |
| TCELL9:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN1 |
| TCELL9:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_7 |
| TCELL9:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_1 |
| TCELL9:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_4 |
| TCELL9:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_5 |
| TCELL9:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_0 |
| TCELL9:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_6 |
| TCELL9:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL9:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL9:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL9:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL9:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_1 |
| TCELL9:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_PD_EN_1_0 |
| TCELL9:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL9:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL9:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL9:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL9:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN4 |
| TCELL9:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_6 |
| TCELL9:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_2 |
| TCELL9:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_0 |
| TCELL9:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_3 |
| TCELL9:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_WDATA_151_144_NIB8_CLB2PHY_WR_DQ0_5 |
| TCELL9:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN3 |
| TCELL9:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN2 |
| TCELL9:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2PHY_KEEPER_EN0 |
| TCELL9:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P8_CLB2RIU_WR_EN |
| TCELL9:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_5 |
| TCELL9:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_3 |
| TCELL9:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_0 |
| TCELL9:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_2 |
| TCELL9:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_WDATA_87_80_NIB7_CLB2PHY_WR_DQ0_6 |
| TCELL9:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_7 |
| TCELL9:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_3 |
| TCELL9:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_1 |
| TCELL9:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_2 |
| TCELL9:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_95_88_NIB7_CLB2PHY_WR_DQ1_4 |
| TCELL9:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RST |
| TCELL9:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST5 |
| TCELL10:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_4 |
| TCELL10:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_95_88_NIB7_PHY2CLB_RD_DQ1_6 |
| TCELL10:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_7 |
| TCELL10:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_5 |
| TCELL10:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_3 |
| TCELL10:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_1 |
| TCELL10:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_0 |
| TCELL10:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_2 |
| TCELL10:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_4 |
| TCELL10:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_103_96_NIB7_PHY2CLB_RD_DQ2_6 |
| TCELL10:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_7 |
| TCELL10:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_5 |
| TCELL10:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_3 |
| TCELL10:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_1 |
| TCELL10:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_0 |
| TCELL10:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_2 |
| TCELL10:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_4 |
| TCELL10:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_111_104_NIB7_PHY2CLB_RD_DQ3_6 |
| TCELL10:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_7 |
| TCELL10:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_5 |
| TCELL10:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_3 |
| TCELL10:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_1 |
| TCELL10:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_0 |
| TCELL10:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_2 |
| TCELL10:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_4 |
| TCELL10:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_119_112_NIB7_PHY2CLB_RD_DQ4_6 |
| TCELL10:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_7 |
| TCELL10:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_5 |
| TCELL10:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_3 |
| TCELL10:IMUX.CTRL.0 | LPDDRMC.AXIA1_CLK |
| TCELL10:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT7 |
| TCELL10:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST2 |
| TCELL10:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST5 |
| TCELL10:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST2 |
| TCELL10:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL10:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL10:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE5 |
| TCELL10:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_3 |
| TCELL10:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_2 |
| TCELL10:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE4 |
| TCELL10:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE1 |
| TCELL10:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE4 |
| TCELL10:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE1 |
| TCELL10:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC4 |
| TCELL10:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC1 |
| TCELL10:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD4 |
| TCELL10:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST4 |
| TCELL10:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST3 |
| TCELL10:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST1 |
| TCELL10:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_TXBIT_RST0 |
| TCELL10:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST4 |
| TCELL10:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST3 |
| TCELL10:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST1 |
| TCELL10:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_RXBIT_RST0 |
| TCELL10:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL10:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL10:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL10:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL10:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_7 |
| TCELL10:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_5 |
| TCELL10:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_1 |
| TCELL10:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_0 |
| TCELL10:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_4 |
| TCELL10:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_WDATA_103_96_NIB7_CLB2PHY_WR_DQ2_6 |
| TCELL10:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE3 |
| TCELL10:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE2 |
| TCELL10:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IBUF_DISABLE0 |
| TCELL10:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE5 |
| TCELL10:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE3 |
| TCELL10:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE2 |
| TCELL10:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CE0 |
| TCELL10:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC5 |
| TCELL10:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC3 |
| TCELL10:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC2 |
| TCELL10:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_INC0 |
| TCELL10:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD5 |
| TCELL10:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD3 |
| TCELL10:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD2 |
| TCELL11:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_1 |
| TCELL11:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_0 |
| TCELL11:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_2 |
| TCELL11:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_4 |
| TCELL11:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_127_120_NIB7_PHY2CLB_RD_DQ5_6 |
| TCELL11:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_FIFO_EMPTY |
| TCELL11:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_FIXDLY_RDY |
| TCELL11:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_PHY_RDY |
| TCELL11:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_GT_STATUS |
| TCELL11:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_MASTER_PD |
| TCELL11:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL11:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL11:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL11:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL11:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL11:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL11:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL11:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL11:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL11:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL11:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL11:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL11:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL11:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL11:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL11:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL11:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL11:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL11:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL11:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_CTRL_CLK |
| TCELL11:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_FIFO_CLK |
| TCELL11:IMUX.CTRL.3 | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2MC_DIV_CLK |
| TCELL11:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT5 |
| TCELL11:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN7 |
| TCELL11:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL11:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL11:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_7 |
| TCELL11:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_1 |
| TCELL11:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_4 |
| TCELL11:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL11:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL11:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL11:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL11:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL11:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL11:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL11:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL11:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL11:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_5 |
| TCELL11:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD1 |
| TCELL11:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_LD0 |
| TCELL11:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL11:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL11:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL11:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL11:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_5 |
| TCELL11:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_3 |
| TCELL11:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_0 |
| TCELL11:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_2 |
| TCELL11:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WDATA_111_104_NIB7_CLB2PHY_WR_DQ3_6 |
| TCELL11:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL11:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL11:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL11:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL11:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL11:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL11:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL11:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL11:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL11:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL11:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL11:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL11:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL11:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL11:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL11:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL11:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL11:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL11:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_7 |
| TCELL11:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_3 |
| TCELL11:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_1 |
| TCELL12:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL12:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL12:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL12:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL12:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL12:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL12:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL12:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL12:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL12:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL12:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL12:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL12:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL12:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL12:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL12:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL12:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL12:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL12:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL12:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL12:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL12:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL12:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL12:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL12:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL12:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL12:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL12:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL12:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL12:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_4 |
| TCELL12:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL12:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL12:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL12:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL12:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL12:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL12:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL12:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL12:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL12:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_7 |
| TCELL12:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_1 |
| TCELL12:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_4 |
| TCELL12:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL12:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL12:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_0 |
| TCELL12:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_2 |
| TCELL12:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_119_112_NIB7_CLB2PHY_WR_DQ4_6 |
| TCELL12:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL12:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL12:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL12:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL12:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL12:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL12:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL12:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL12:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL12:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL12:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL12:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL12:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL12:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL12:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL12:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL12:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL12:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL12:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL12:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_5 |
| TCELL12:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_3 |
| TCELL12:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_0 |
| TCELL12:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_2 |
| TCELL12:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_127_120_NIB7_CLB2PHY_WR_DQ5_6 |
| TCELL12:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL12:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL12:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL12:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL12:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL13:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL13:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL13:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL13:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL13:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL13:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL13:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT5 |
| TCELL13:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT4 |
| TCELL13:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT3 |
| TCELL13:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT2 |
| TCELL13:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT1 |
| TCELL13:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_IOB2CLB_DFT0 |
| TCELL13:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_2 |
| TCELL13:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_1 |
| TCELL13:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_0_0 |
| TCELL13:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_2 |
| TCELL13:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_1 |
| TCELL13:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_PHY2CLB_LP_I_1_0 |
| TCELL13:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P7_RIU2CLB_VALID |
| TCELL13:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA15 |
| TCELL13:OUT.23.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARREADY |
| TCELL13:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA14 |
| TCELL13:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA13 |
| TCELL13:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA12 |
| TCELL13:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA11 |
| TCELL13:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA10 |
| TCELL13:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA9 |
| TCELL13:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA8 |
| TCELL13:OUT.31.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWREADY |
| TCELL13:IMUX.BYP.6.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN4 |
| TCELL13:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN0 |
| TCELL13:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG8 |
| TCELL13:IMUX.BYP.13.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN10 |
| TCELL13:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL13:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_1 |
| TCELL13:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL13:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL13:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN4 |
| TCELL13:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN1 |
| TCELL13:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2RIU_NIBBLE_SEL |
| TCELL13:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA13 |
| TCELL13:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA10 |
| TCELL13:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA7 |
| TCELL13:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA4 |
| TCELL13:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA1 |
| TCELL13:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR6 |
| TCELL13:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR3 |
| TCELL13:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR0 |
| TCELL13:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL13:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL13:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL13:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_2 |
| TCELL13:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_PD_EN_1_0 |
| TCELL13:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL13:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL13:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL13:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL13:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN5 |
| TCELL13:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN3 |
| TCELL13:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN2 |
| TCELL13:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2PHY_KEEPER_EN0 |
| TCELL13:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P7_CLB2RIU_WR_EN |
| TCELL13:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA15 |
| TCELL13:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA14 |
| TCELL13:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA12 |
| TCELL13:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA11 |
| TCELL13:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA9 |
| TCELL13:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA8 |
| TCELL13:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA6 |
| TCELL13:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA5 |
| TCELL13:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA3 |
| TCELL13:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA2 |
| TCELL13:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_WDATA_79_64_NIB7_CLB2RIU_WR_DATA0 |
| TCELL13:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR7 |
| TCELL13:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR5 |
| TCELL13:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR4 |
| TCELL13:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR2 |
| TCELL13:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WSTRB_15_8_NIB7_CLB2RIU_ADDR1 |
| TCELL13:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN3 |
| TCELL13:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN2 |
| TCELL14:OUT.0.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA7 |
| TCELL14:OUT.1.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA6 |
| TCELL14:OUT.2.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA5 |
| TCELL14:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA4 |
| TCELL14:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA3 |
| TCELL14:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA2 |
| TCELL14:OUT.6.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WREADY |
| TCELL14:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA1 |
| TCELL14:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_79_64_NIB7_RIU2CLB_RD_DATA0 |
| TCELL14:OUT.9.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RVALID |
| TCELL14:OUT.10.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RLAST |
| TCELL14:OUT.11.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID7 |
| TCELL14:OUT.12.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID6 |
| TCELL14:OUT.13.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID5 |
| TCELL14:OUT.14.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID4 |
| TCELL14:OUT.15.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID3 |
| TCELL14:OUT.16.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID2 |
| TCELL14:OUT.17.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID1 |
| TCELL14:OUT.18.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RID0 |
| TCELL14:OUT.19.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RRESP1 |
| TCELL14:OUT.20.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RRESP0 |
| TCELL14:OUT.21.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RPOISON |
| TCELL14:OUT.22.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR7 |
| TCELL14:OUT.23.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR6 |
| TCELL14:OUT.24.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR5 |
| TCELL14:OUT.25.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR4 |
| TCELL14:OUT.26.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR3 |
| TCELL14:OUT.27.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR2 |
| TCELL14:OUT.28.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR1 |
| TCELL14:OUT.29.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RDATA_PAR0 |
| TCELL14:OUT.30.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BVALID |
| TCELL14:OUT.31.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID7 |
| TCELL14:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE2 |
| TCELL14:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN1 |
| TCELL14:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT4 |
| TCELL14:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT1 |
| TCELL14:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN3 |
| TCELL14:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN0 |
| TCELL14:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL3 |
| TCELL14:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL0 |
| TCELL14:IMUX.IMUX.7.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE2 |
| TCELL14:IMUX.IMUX.8.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARBURST1 |
| TCELL14:IMUX.IMUX.9.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT2 |
| TCELL14:IMUX.IMUX.10.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARADDR_PAR1 |
| TCELL14:IMUX.IMUX.11.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE2 |
| TCELL14:IMUX.IMUX.12.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWBURST1 |
| TCELL14:IMUX.IMUX.13.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT2 |
| TCELL14:IMUX.IMUX.14.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWADDR_PAR1 |
| TCELL14:IMUX.IMUX.15.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WLAST |
| TCELL14:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_AWADDR_14_11_NIB7_CLB2PHY_WREN0 |
| TCELL14:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT5 |
| TCELL14:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT3 |
| TCELL14:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT2 |
| TCELL14:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_AWADDR_20_15_NIB7_CLB2PHY_T_TXBIT0 |
| TCELL14:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_AWADDR_21_NIB7_CLB2PHY_FIFO_RDEN |
| TCELL14:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN2 |
| TCELL14:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_ARADDR_14_11_NIB7_CLB2PHY_RDEN1 |
| TCELL14:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL5 |
| TCELL14:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL4 |
| TCELL14:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL2 |
| TCELL14:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_ARADDR_20_15_NIB7_CLB2PHY_IODELAY_SEL1 |
| TCELL14:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_ARADDR_21_NIB7_CLB2PHY_DLYCTL_EN_VTC |
| TCELL14:IMUX.IMUX.29.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARVALID |
| TCELL14:IMUX.IMUX.30.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE1 |
| TCELL14:IMUX.IMUX.31.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARSIZE0 |
| TCELL14:IMUX.IMUX.32.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARBURST0 |
| TCELL14:IMUX.IMUX.33.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARLOCK |
| TCELL14:IMUX.IMUX.34.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT1 |
| TCELL14:IMUX.IMUX.35.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARPROT0 |
| TCELL14:IMUX.IMUX.36.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_ARADDR_PAR0 |
| TCELL14:IMUX.IMUX.37.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWVALID |
| TCELL14:IMUX.IMUX.38.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE1 |
| TCELL14:IMUX.IMUX.39.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWSIZE0 |
| TCELL14:IMUX.IMUX.40.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWBURST0 |
| TCELL14:IMUX.IMUX.41.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWLOCK |
| TCELL14:IMUX.IMUX.42.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT1 |
| TCELL14:IMUX.IMUX.43.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWPROT0 |
| TCELL14:IMUX.IMUX.44.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_AWADDR_PAR0 |
| TCELL14:IMUX.IMUX.45.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WVALID |
| TCELL14:IMUX.IMUX.46.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_WPOISON |
| TCELL14:IMUX.IMUX.47.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_RREADY |
| TCELL15:OUT.0.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID6 |
| TCELL15:OUT.1.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID5 |
| TCELL15:OUT.2.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID4 |
| TCELL15:OUT.3.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID3 |
| TCELL15:OUT.4.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID2 |
| TCELL15:OUT.5.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID1 |
| TCELL15:OUT.6.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BID0 |
| TCELL15:OUT.7.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BRESP1 |
| TCELL15:OUT.8.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BRESP0 |
| TCELL15:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_FIFO_EMPTY |
| TCELL15:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_FIXDLY_RDY |
| TCELL15:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_PHY_RDY |
| TCELL15:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_GT_STATUS |
| TCELL15:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_MASTER_PD |
| TCELL15:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL15:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL15:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL15:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL15:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL15:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL15:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL15:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL15:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL15:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL15:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL15:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL15:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL15:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL15:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL15:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL15:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL15:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL15:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT1 |
| TCELL15:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN3 |
| TCELL15:IMUX.IMUX.1.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR30 |
| TCELL15:IMUX.IMUX.2.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR27 |
| TCELL15:IMUX.IMUX.3.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR24 |
| TCELL15:IMUX.IMUX.4.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR21 |
| TCELL15:IMUX.IMUX.5.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR18 |
| TCELL15:IMUX.IMUX.6.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR15 |
| TCELL15:IMUX.IMUX.7.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR12 |
| TCELL15:IMUX.IMUX.8.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR9 |
| TCELL15:IMUX.IMUX.9.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR6 |
| TCELL15:IMUX.IMUX.10.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR3 |
| TCELL15:IMUX.IMUX.11.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR0 |
| TCELL15:IMUX.IMUX.12.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWRITE |
| TCELL15:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA14 |
| TCELL15:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA11 |
| TCELL15:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA8 |
| TCELL15:IMUX.IMUX.16.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P1_BREADY |
| TCELL15:IMUX.IMUX.17.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR31 |
| TCELL15:IMUX.IMUX.18.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR29 |
| TCELL15:IMUX.IMUX.19.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR28 |
| TCELL15:IMUX.IMUX.20.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR26 |
| TCELL15:IMUX.IMUX.21.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR25 |
| TCELL15:IMUX.IMUX.22.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR23 |
| TCELL15:IMUX.IMUX.23.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR22 |
| TCELL15:IMUX.IMUX.24.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR20 |
| TCELL15:IMUX.IMUX.25.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR19 |
| TCELL15:IMUX.IMUX.26.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR17 |
| TCELL15:IMUX.IMUX.27.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR16 |
| TCELL15:IMUX.IMUX.28.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR14 |
| TCELL15:IMUX.IMUX.29.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR13 |
| TCELL15:IMUX.IMUX.30.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR11 |
| TCELL15:IMUX.IMUX.31.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR10 |
| TCELL15:IMUX.IMUX.32.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR8 |
| TCELL15:IMUX.IMUX.33.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR7 |
| TCELL15:IMUX.IMUX.34.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR5 |
| TCELL15:IMUX.IMUX.35.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR4 |
| TCELL15:IMUX.IMUX.36.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR2 |
| TCELL15:IMUX.IMUX.37.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PADDR1 |
| TCELL15:IMUX.IMUX.38.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PSELX |
| TCELL15:IMUX.IMUX.39.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PENABLE |
| TCELL15:IMUX.IMUX.40.DELAY | LPDDRMC.FABRIC_MUX_SELECT_EN |
| TCELL15:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA15 |
| TCELL15:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA13 |
| TCELL15:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA12 |
| TCELL15:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA10 |
| TCELL15:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA9 |
| TCELL15:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA7 |
| TCELL15:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA6 |
| TCELL16:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL16:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL16:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL16:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL16:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL16:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL16:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL16:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL16:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL16:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL16:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL16:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL16:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL16:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL16:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL16:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL16:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL16:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL16:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL16:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL16:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL16:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL16:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL16:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL16:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL16:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL16:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL16:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL16:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL16:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL16:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA5 |
| TCELL16:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA2 |
| TCELL16:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR7 |
| TCELL16:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR4 |
| TCELL16:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR1 |
| TCELL16:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN2 |
| TCELL16:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT5 |
| TCELL16:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT2 |
| TCELL16:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2RIU_NIBBLE_SEL |
| TCELL16:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN2 |
| TCELL16:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL5 |
| TCELL16:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL2 |
| TCELL16:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_ARADDR_10_NIB6_CLB2PHY_DLYCTL_EN_VTC |
| TCELL16:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL16:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL16:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL16:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA4 |
| TCELL16:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA3 |
| TCELL16:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA1 |
| TCELL16:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_15_0_NIB6_CLB2RIU_WR_DATA0 |
| TCELL16:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR6 |
| TCELL16:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR5 |
| TCELL16:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR3 |
| TCELL16:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR2 |
| TCELL16:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WSTRB_7_0_NIB6_CLB2RIU_ADDR0 |
| TCELL16:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN3 |
| TCELL16:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN1 |
| TCELL16:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_AWADDR_3_0_NIB6_CLB2PHY_WREN0 |
| TCELL16:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT4 |
| TCELL16:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT3 |
| TCELL16:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT1 |
| TCELL16:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_AWADDR_9_4_NIB6_CLB2PHY_T_TXBIT0 |
| TCELL16:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_AWADDR_10_NIB6_CLB2PHY_FIFO_RDEN |
| TCELL16:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN3 |
| TCELL16:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN1 |
| TCELL16:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_ARADDR_3_0_NIB6_CLB2PHY_RDEN0 |
| TCELL16:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL4 |
| TCELL16:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL3 |
| TCELL16:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL1 |
| TCELL16:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_ARADDR_9_4_NIB6_CLB2PHY_IODELAY_SEL0 |
| TCELL16:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL16:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL16:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL16:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL16:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL16:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_ARID_7_0_NIB6_7_0_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL16:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL16:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL17:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL17:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL17:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL17:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL17:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL17:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL17:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT5 |
| TCELL17:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT4 |
| TCELL17:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT3 |
| TCELL17:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT2 |
| TCELL17:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT1 |
| TCELL17:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_IOB2CLB_DFT0 |
| TCELL17:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_2 |
| TCELL17:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_1 |
| TCELL17:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_0_0 |
| TCELL17:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_2 |
| TCELL17:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_1 |
| TCELL17:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_PHY2CLB_LP_I_1_0 |
| TCELL17:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P6_RIU2CLB_VALID |
| TCELL17:OUT.22.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA31 |
| TCELL17:OUT.23.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA30 |
| TCELL17:OUT.24.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA29 |
| TCELL17:OUT.25.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA28 |
| TCELL17:OUT.26.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA27 |
| TCELL17:OUT.27.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA26 |
| TCELL17:OUT.28.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA25 |
| TCELL17:OUT.29.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA24 |
| TCELL17:OUT.30.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA23 |
| TCELL17:OUT.31.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA22 |
| TCELL17:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT3 |
| TCELL17:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL17:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL17:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL17:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL17:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL17:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL17:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL17:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL17:IMUX.IMUX.8.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL17:IMUX.IMUX.9.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL17:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL17:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL17:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL17:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL17:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL17:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN3 |
| TCELL17:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL17:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL17:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_ARLEN_7_0_NIB6_15_8_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL17:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL17:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL17:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL17:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL17:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL17:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL17:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_ARUSER_10_0_NIB6_26_16_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL17:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL17:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL17:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL17:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL17:IMUX.IMUX.30.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL17:IMUX.IMUX.31.DELAY | LPDDRMC.AXI1_AWID_7_0_NIB6_34_27_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL17:IMUX.IMUX.32.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL17:IMUX.IMUX.33.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL17:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL17:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL17:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_AWLEN_7_0_NIB6_42_35_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL17:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL17:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL17:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL17:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL17:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL17:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL17:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_AWUSER_10_0_NIB6_53_43_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL17:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN5 |
| TCELL17:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN4 |
| TCELL17:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN2 |
| TCELL17:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN1 |
| TCELL18:OUT.3.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA21 |
| TCELL18:OUT.4.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA20 |
| TCELL18:OUT.5.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA19 |
| TCELL18:OUT.6.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA18 |
| TCELL18:OUT.7.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS15 |
| TCELL18:OUT.8.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS14 |
| TCELL18:OUT.9.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS13 |
| TCELL18:OUT.10.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS12 |
| TCELL18:OUT.11.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS11 |
| TCELL18:OUT.12.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS10 |
| TCELL18:OUT.13.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS9 |
| TCELL18:OUT.14.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS8 |
| TCELL18:OUT.15.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS7 |
| TCELL18:OUT.16.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS6 |
| TCELL18:OUT.17.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS5 |
| TCELL18:OUT.18.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS4 |
| TCELL18:OUT.19.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS3 |
| TCELL18:OUT.20.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS2 |
| TCELL18:OUT.21.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS1 |
| TCELL18:OUT.22.TMIN | LPDDRMC.CFI_NPI_BRIDGE_TO_FABRIC_STATUS0 |
| TCELL18:OUT.23.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA17 |
| TCELL18:OUT.24.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA16 |
| TCELL18:OUT.25.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA15 |
| TCELL18:OUT.26.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA14 |
| TCELL18:OUT.27.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA13 |
| TCELL18:OUT.28.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA12 |
| TCELL18:OUT.29.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA11 |
| TCELL18:OUT.30.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA10 |
| TCELL18:OUT.31.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA9 |
| TCELL18:IMUX.CTRL.0 | LPDDRMC.IFABRIC_APB_CLK |
| TCELL18:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_FIFO_CLK |
| TCELL18:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_CTRL_CLK |
| TCELL18:IMUX.CTRL.3 | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2MC_DIV_CLK |
| TCELL18:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT11 |
| TCELL18:IMUX.IMUX.0.DELAY | LPDDRMC.AXI1_WDATA_PAR_5_0_NIB6_CLB2PHY_KEEPER_EN0 |
| TCELL18:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RST |
| TCELL18:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST3 |
| TCELL18:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST0 |
| TCELL18:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST3 |
| TCELL18:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST0 |
| TCELL18:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL18:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL18:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE3 |
| TCELL18:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE0 |
| TCELL18:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE3 |
| TCELL18:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE0 |
| TCELL18:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC3 |
| TCELL18:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC0 |
| TCELL18:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD3 |
| TCELL18:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD0 |
| TCELL18:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_PAR_7_6_NIB6_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL18:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_PAR_7_6_NIB6_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL18:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST5 |
| TCELL18:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST4 |
| TCELL18:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST2 |
| TCELL18:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_TXBIT_RST1 |
| TCELL18:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST5 |
| TCELL18:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST4 |
| TCELL18:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST2 |
| TCELL18:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_RXBIT_RST1 |
| TCELL18:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL18:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL18:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL18:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL18:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE5 |
| TCELL18:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE4 |
| TCELL18:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE2 |
| TCELL18:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IBUF_DISABLE1 |
| TCELL18:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE5 |
| TCELL18:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE4 |
| TCELL18:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE2 |
| TCELL18:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_CE1 |
| TCELL18:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC5 |
| TCELL18:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC4 |
| TCELL18:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC2 |
| TCELL18:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_INC1 |
| TCELL18:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD5 |
| TCELL18:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD4 |
| TCELL18:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD2 |
| TCELL18:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IODELAY_LD1 |
| TCELL18:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL18:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL19:OUT.3.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA8 |
| TCELL19:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA15 |
| TCELL19:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA14 |
| TCELL19:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA13 |
| TCELL19:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA12 |
| TCELL19:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA11 |
| TCELL19:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA10 |
| TCELL19:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA9 |
| TCELL19:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA8 |
| TCELL19:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA7 |
| TCELL19:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA6 |
| TCELL19:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA5 |
| TCELL19:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA4 |
| TCELL19:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA3 |
| TCELL19:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA2 |
| TCELL19:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA1 |
| TCELL19:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_15_0_NIB6_RIU2CLB_RD_DATA0 |
| TCELL19:OUT.20.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA7 |
| TCELL19:OUT.21.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA6 |
| TCELL19:OUT.22.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA5 |
| TCELL19:OUT.23.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA4 |
| TCELL19:OUT.24.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA3 |
| TCELL19:OUT.25.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA2 |
| TCELL19:OUT.26.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA1 |
| TCELL19:OUT.27.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PRDATA0 |
| TCELL19:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_6 |
| TCELL19:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_4 |
| TCELL19:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_2 |
| TCELL19:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_0 |
| TCELL19:IMUX.BYP.6.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN1 |
| TCELL19:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN7 |
| TCELL19:IMUX.BYP.14.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN10 |
| TCELL19:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL19:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL19:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL19:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL19:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL19:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL19:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_0 |
| TCELL19:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL19:IMUX.IMUX.8.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA31 |
| TCELL19:IMUX.IMUX.9.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA28 |
| TCELL19:IMUX.IMUX.10.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA25 |
| TCELL19:IMUX.IMUX.11.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA22 |
| TCELL19:IMUX.IMUX.12.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA19 |
| TCELL19:IMUX.IMUX.13.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA16 |
| TCELL19:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_4 |
| TCELL19:IMUX.IMUX.15.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_1 |
| TCELL19:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL19:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL19:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL19:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL19:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL19:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL19:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL19:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL19:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL19:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL19:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_2 |
| TCELL19:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_PD_EN_1_1 |
| TCELL19:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_0_BIT2 |
| TCELL19:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL19:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL19:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P6_CLB2RIU_WR_EN |
| TCELL19:IMUX.IMUX.32.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA30 |
| TCELL19:IMUX.IMUX.33.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA29 |
| TCELL19:IMUX.IMUX.34.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA27 |
| TCELL19:IMUX.IMUX.35.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA26 |
| TCELL19:IMUX.IMUX.36.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA24 |
| TCELL19:IMUX.IMUX.37.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA23 |
| TCELL19:IMUX.IMUX.38.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA21 |
| TCELL19:IMUX.IMUX.39.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA20 |
| TCELL19:IMUX.IMUX.40.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA18 |
| TCELL19:IMUX.IMUX.41.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA17 |
| TCELL19:IMUX.IMUX.42.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA15 |
| TCELL19:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_6 |
| TCELL19:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_2 |
| TCELL19:IMUX.IMUX.45.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_0 |
| TCELL19:IMUX.IMUX.46.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_3 |
| TCELL19:IMUX.IMUX.47.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_5 |
| TCELL20:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_1 |
| TCELL20:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_3 |
| TCELL20:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_5 |
| TCELL20:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_63_56_NIB6_PHY2CLB_RD_DQ5_7 |
| TCELL20:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_6 |
| TCELL20:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_4 |
| TCELL20:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_2 |
| TCELL20:OUT.10.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_0 |
| TCELL20:OUT.11.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_1 |
| TCELL20:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_3 |
| TCELL20:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_5 |
| TCELL20:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_55_48_NIB6_PHY2CLB_RD_DQ4_7 |
| TCELL20:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_6 |
| TCELL20:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_4 |
| TCELL20:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_2 |
| TCELL20:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_0 |
| TCELL20:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_1 |
| TCELL20:OUT.20.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_3 |
| TCELL20:OUT.21.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_5 |
| TCELL20:OUT.22.TMIN | LPDDRMC.AXI1_RDATA_47_40_NIB6_PHY2CLB_RD_DQ3_7 |
| TCELL20:OUT.23.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_6 |
| TCELL20:OUT.24.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_4 |
| TCELL20:OUT.25.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_2 |
| TCELL20:OUT.26.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_0 |
| TCELL20:OUT.27.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_1 |
| TCELL20:OUT.28.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_3 |
| TCELL20:OUT.29.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_5 |
| TCELL20:OUT.30.TMIN | LPDDRMC.AXI1_RDATA_39_32_NIB6_PHY2CLB_RD_DQ2_7 |
| TCELL20:OUT.31.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_6 |
| TCELL20:IMUX.IMUX.1.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA13 |
| TCELL20:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_6 |
| TCELL20:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_0 |
| TCELL20:IMUX.IMUX.4.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_5 |
| TCELL20:IMUX.IMUX.5.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_4 |
| TCELL20:IMUX.IMUX.6.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_1 |
| TCELL20:IMUX.IMUX.7.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_7 |
| TCELL20:IMUX.IMUX.8.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA8 |
| TCELL20:IMUX.IMUX.9.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA5 |
| TCELL20:IMUX.IMUX.10.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_2 |
| TCELL20:IMUX.IMUX.11.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_3 |
| TCELL20:IMUX.IMUX.12.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_6 |
| TCELL20:IMUX.IMUX.13.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_0 |
| TCELL20:IMUX.IMUX.14.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_5 |
| TCELL20:IMUX.IMUX.15.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA3 |
| TCELL20:IMUX.IMUX.16.DELAY | LPDDRMC.AXI1_WDATA_63_56_NIB6_CLB2PHY_WR_DQ5_7 |
| TCELL20:IMUX.IMUX.17.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA14 |
| TCELL20:IMUX.IMUX.18.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA12 |
| TCELL20:IMUX.IMUX.19.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA11 |
| TCELL20:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_4 |
| TCELL20:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_2 |
| TCELL20:IMUX.IMUX.22.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_1 |
| TCELL20:IMUX.IMUX.23.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_3 |
| TCELL20:IMUX.IMUX.24.DELAY | LPDDRMC.AXI1_WDATA_55_48_NIB6_CLB2PHY_WR_DQ4_7 |
| TCELL20:IMUX.IMUX.25.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_6 |
| TCELL20:IMUX.IMUX.26.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_2 |
| TCELL20:IMUX.IMUX.27.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_0 |
| TCELL20:IMUX.IMUX.28.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_3 |
| TCELL20:IMUX.IMUX.29.DELAY | LPDDRMC.AXI1_WDATA_47_40_NIB6_CLB2PHY_WR_DQ3_5 |
| TCELL20:IMUX.IMUX.30.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA10 |
| TCELL20:IMUX.IMUX.31.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA9 |
| TCELL20:IMUX.IMUX.32.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA7 |
| TCELL20:IMUX.IMUX.33.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA6 |
| TCELL20:IMUX.IMUX.34.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_6 |
| TCELL20:IMUX.IMUX.35.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_4 |
| TCELL20:IMUX.IMUX.36.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_0 |
| TCELL20:IMUX.IMUX.37.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_1 |
| TCELL20:IMUX.IMUX.38.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_5 |
| TCELL20:IMUX.IMUX.39.DELAY | LPDDRMC.AXI1_WDATA_39_32_NIB6_CLB2PHY_WR_DQ2_7 |
| TCELL20:IMUX.IMUX.40.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_4 |
| TCELL20:IMUX.IMUX.41.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_2 |
| TCELL20:IMUX.IMUX.42.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_1 |
| TCELL20:IMUX.IMUX.43.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_3 |
| TCELL20:IMUX.IMUX.44.DELAY | LPDDRMC.AXI1_WDATA_31_24_NIB6_CLB2PHY_WR_DQ1_7 |
| TCELL20:IMUX.IMUX.45.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA4 |
| TCELL20:IMUX.IMUX.46.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA2 |
| TCELL20:IMUX.IMUX.47.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA1 |
| TCELL21:OUT.3.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_4 |
| TCELL21:OUT.4.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_2 |
| TCELL21:OUT.5.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_0 |
| TCELL21:OUT.6.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_1 |
| TCELL21:OUT.7.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_3 |
| TCELL21:OUT.8.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_5 |
| TCELL21:OUT.9.TMIN | LPDDRMC.AXI1_RDATA_31_24_NIB6_PHY2CLB_RD_DQ1_7 |
| TCELL21:OUT.10.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PREADY |
| TCELL21:OUT.11.TMIN | LPDDRMC.IF_APB_FABRIC2BRIDGE_PSLVERR |
| TCELL21:OUT.12.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_6 |
| TCELL21:OUT.13.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_4 |
| TCELL21:OUT.14.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_2 |
| TCELL21:OUT.15.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_0 |
| TCELL21:OUT.16.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_1 |
| TCELL21:OUT.17.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_3 |
| TCELL21:OUT.18.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_5 |
| TCELL21:OUT.19.TMIN | LPDDRMC.AXI1_RDATA_23_16_NIB6_PHY2CLB_RD_DQ0_7 |
| TCELL21:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_7 |
| TCELL21:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_5 |
| TCELL21:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_3 |
| TCELL21:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_1 |
| TCELL21:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_0 |
| TCELL21:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_2 |
| TCELL21:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_4 |
| TCELL21:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ0_6 |
| TCELL21:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_7 |
| TCELL21:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_5 |
| TCELL21:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_3 |
| TCELL21:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_1 |
| TCELL21:IMUX.BYP.6.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT3 |
| TCELL21:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN5 |
| TCELL21:IMUX.BYP.12.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT4 |
| TCELL21:IMUX.IMUX.1.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_4 |
| TCELL21:IMUX.IMUX.2.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_1 |
| TCELL21:IMUX.IMUX.3.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_7 |
| TCELL21:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_3 |
| TCELL21:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_2 |
| TCELL21:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_7 |
| TCELL21:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_1 |
| TCELL21:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_4 |
| TCELL21:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_5 |
| TCELL21:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_0 |
| TCELL21:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_6 |
| TCELL21:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_3 |
| TCELL21:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_2 |
| TCELL21:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RST |
| TCELL21:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST3 |
| TCELL21:IMUX.IMUX.16.DELAY | LPDDRMC.IF_APB_FABRIC2BRIDGE_PWDATA0 |
| TCELL21:IMUX.IMUX.17.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_6 |
| TCELL21:IMUX.IMUX.18.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_2 |
| TCELL21:IMUX.IMUX.19.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_0 |
| TCELL21:IMUX.IMUX.20.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_3 |
| TCELL21:IMUX.IMUX.21.DELAY | LPDDRMC.AXI1_WDATA_23_16_NIB6_CLB2PHY_WR_DQ0_5 |
| TCELL21:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_7 |
| TCELL21:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_5 |
| TCELL21:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_1 |
| TCELL21:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_0 |
| TCELL21:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_4 |
| TCELL21:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ0_6 |
| TCELL21:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_5 |
| TCELL21:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_3 |
| TCELL21:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_0 |
| TCELL21:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_2 |
| TCELL21:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ1_6 |
| TCELL21:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_7 |
| TCELL21:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_3 |
| TCELL21:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_1 |
| TCELL21:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_2 |
| TCELL21:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ2_4 |
| TCELL21:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_7 |
| TCELL21:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_5 |
| TCELL21:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_1 |
| TCELL21:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_0 |
| TCELL21:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_4 |
| TCELL21:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ3_6 |
| TCELL21:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST5 |
| TCELL21:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST4 |
| TCELL21:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST2 |
| TCELL21:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST1 |
| TCELL22:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_0 |
| TCELL22:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_2 |
| TCELL22:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_4 |
| TCELL22:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ1_6 |
| TCELL22:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_7 |
| TCELL22:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_5 |
| TCELL22:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_3 |
| TCELL22:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_1 |
| TCELL22:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_0 |
| TCELL22:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_2 |
| TCELL22:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_4 |
| TCELL22:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ2_6 |
| TCELL22:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_7 |
| TCELL22:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_5 |
| TCELL22:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_3 |
| TCELL22:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_1 |
| TCELL22:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_0 |
| TCELL22:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_2 |
| TCELL22:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_4 |
| TCELL22:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ3_6 |
| TCELL22:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_7 |
| TCELL22:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_5 |
| TCELL22:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_3 |
| TCELL22:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_1 |
| TCELL22:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_0 |
| TCELL22:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_2 |
| TCELL22:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_4 |
| TCELL22:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ4_6 |
| TCELL22:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_7 |
| TCELL22:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2MC_DIV_CLK |
| TCELL22:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_CTRL_CLK |
| TCELL22:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_FIFO_CLK |
| TCELL22:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN2 |
| TCELL22:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST4 |
| TCELL22:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST1 |
| TCELL22:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WREN2 |
| TCELL22:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT5 |
| TCELL22:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT2 |
| TCELL22:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN3 |
| TCELL22:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_7 |
| TCELL22:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_1 |
| TCELL22:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_4 |
| TCELL22:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_FIFO_RDEN |
| TCELL22:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL22:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL22:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE3 |
| TCELL22:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE0 |
| TCELL22:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE4 |
| TCELL22:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_TXBIT_RST0 |
| TCELL22:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST5 |
| TCELL22:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST3 |
| TCELL22:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST2 |
| TCELL22:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RXBIT_RST0 |
| TCELL22:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WREN3 |
| TCELL22:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WREN1 |
| TCELL22:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WREN0 |
| TCELL22:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT4 |
| TCELL22:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT3 |
| TCELL22:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT1 |
| TCELL22:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_T_TXBIT0 |
| TCELL22:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN2 |
| TCELL22:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN1 |
| TCELL22:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_5 |
| TCELL22:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_3 |
| TCELL22:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_0 |
| TCELL22:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_2 |
| TCELL22:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ4_6 |
| TCELL22:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_RDEN0 |
| TCELL22:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL22:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL22:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL22:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL22:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE5 |
| TCELL22:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE4 |
| TCELL22:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE2 |
| TCELL22:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IBUF_DISABLE1 |
| TCELL22:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_DLYCTL_EN_VTC |
| TCELL22:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE5 |
| TCELL22:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE3 |
| TCELL22:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE2 |
| TCELL23:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_5 |
| TCELL23:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_3 |
| TCELL23:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_1 |
| TCELL23:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_0 |
| TCELL23:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_2 |
| TCELL23:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_4 |
| TCELL23:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_RD_DQ5_6 |
| TCELL23:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_FIFO_EMPTY |
| TCELL23:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_FIXDLY_RDY |
| TCELL23:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_PHY_RDY |
| TCELL23:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_GT_STATUS |
| TCELL23:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_MASTER_PD |
| TCELL23:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL23:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL23:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL23:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL23:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL23:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL23:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL23:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL23:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL23:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL23:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL23:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL23:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL23:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL23:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL23:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL23:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL23:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT8 |
| TCELL23:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE1 |
| TCELL23:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC4 |
| TCELL23:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC1 |
| TCELL23:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_7 |
| TCELL23:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_1 |
| TCELL23:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_4 |
| TCELL23:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD3 |
| TCELL23:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD0 |
| TCELL23:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL23:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL23:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL23:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL23:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL23:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL23:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL23:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL23:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CE0 |
| TCELL23:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC5 |
| TCELL23:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC3 |
| TCELL23:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC2 |
| TCELL23:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_INC0 |
| TCELL23:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD5 |
| TCELL23:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_5 |
| TCELL23:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_3 |
| TCELL23:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_0 |
| TCELL23:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_2 |
| TCELL23:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_WR_DQ5_6 |
| TCELL23:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD4 |
| TCELL23:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD2 |
| TCELL23:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_LD1 |
| TCELL23:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL23:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL23:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL23:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL23:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL23:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL23:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL23:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL23:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL23:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL23:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL23:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL23:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL23:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL23:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL23:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL23:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL23:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL24:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL24:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL24:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL24:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL24:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL24:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL24:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL24:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL24:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL24:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL24:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL24:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL24:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL24:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL24:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL24:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL24:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL24:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL24:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL24:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL24:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL24:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL24:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL24:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL24:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL24:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL24:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL24:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL24:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL24:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT2 |
| TCELL24:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG9 |
| TCELL24:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL24:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL24:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL24:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL24:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL24:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL24:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL24:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL24:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL24:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL4 |
| TCELL24:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL1 |
| TCELL24:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL24:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL24:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL24:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL24:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL24:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL24:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL24:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL24:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL24:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL24:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL24:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL24:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL24:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL24:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL24:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL24:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL24:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL24:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL24:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL24:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL24:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL24:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL24:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL5 |
| TCELL24:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL3 |
| TCELL24:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL2 |
| TCELL24:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IODELAY_SEL0 |
| TCELL24:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL24:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL24:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL24:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL24:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL24:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL24:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL24:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL24:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL25:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL25:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL25:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL25:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL25:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL25:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL25:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL25:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL25:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT5 |
| TCELL25:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT4 |
| TCELL25:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT3 |
| TCELL25:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT2 |
| TCELL25:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT1 |
| TCELL25:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_IOB2CLB_DFT0 |
| TCELL25:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_2 |
| TCELL25:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_1 |
| TCELL25:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_0_0 |
| TCELL25:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_2 |
| TCELL25:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_1 |
| TCELL25:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_PHY2CLB_LP_I_1_0 |
| TCELL25:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA15 |
| TCELL25:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA14 |
| TCELL25:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA13 |
| TCELL25:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA12 |
| TCELL25:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA11 |
| TCELL25:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA10 |
| TCELL25:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA9 |
| TCELL25:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA8 |
| TCELL25:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA7 |
| TCELL25:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL25:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_2 |
| TCELL25:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL25:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL25:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN5 |
| TCELL25:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN2 |
| TCELL25:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR7 |
| TCELL25:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR4 |
| TCELL25:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR1 |
| TCELL25:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA14 |
| TCELL25:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA11 |
| TCELL25:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA8 |
| TCELL25:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA5 |
| TCELL25:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA2 |
| TCELL25:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_EN |
| TCELL25:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL25:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL25:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL25:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL25:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_1 |
| TCELL25:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_PD_EN_1_0 |
| TCELL25:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL25:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL25:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL25:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL25:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN4 |
| TCELL25:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN3 |
| TCELL25:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN1 |
| TCELL25:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2PHY_KEEPER_EN0 |
| TCELL25:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR6 |
| TCELL25:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR5 |
| TCELL25:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR3 |
| TCELL25:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR2 |
| TCELL25:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_ADDR0 |
| TCELL25:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA15 |
| TCELL25:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA13 |
| TCELL25:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA12 |
| TCELL25:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA10 |
| TCELL25:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA9 |
| TCELL25:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA7 |
| TCELL25:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA6 |
| TCELL25:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA4 |
| TCELL25:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA3 |
| TCELL25:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA1 |
| TCELL25:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_WR_DATA0 |
| TCELL25:IMUX.IMUX.46.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_0_3 |
| TCELL25:IMUX.IMUX.47.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_0_2 |
| TCELL26:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA6 |
| TCELL26:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA5 |
| TCELL26:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA4 |
| TCELL26:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA3 |
| TCELL26:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA2 |
| TCELL26:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA1 |
| TCELL26:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_RD_DATA0 |
| TCELL26:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P10_RIU2CLB_VALID |
| TCELL26:OUT.11.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_USR_PORT_AVAILABLE |
| TCELL26:OUT.12.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_0_3 |
| TCELL26:OUT.13.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_0_2 |
| TCELL26:OUT.14.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_0_1 |
| TCELL26:OUT.15.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_0_0 |
| TCELL26:OUT.16.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_1_1 |
| TCELL26:OUT.17.TMIN | LPDDRMC.IF_DMC_FABRIC_REF_ACK_1_0 |
| TCELL26:OUT.18.TMIN | LPDDRMC.IF_DMC_FABRIC_CAL_BUSY |
| TCELL26:OUT.19.TMIN | LPDDRMC.IF_DMC_FABRIC_CAL_DONE |
| TCELL26:OUT.20.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC9 |
| TCELL26:OUT.21.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC8 |
| TCELL26:OUT.22.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC7 |
| TCELL26:OUT.23.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC6 |
| TCELL26:OUT.24.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC5 |
| TCELL26:OUT.25.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC4 |
| TCELL26:OUT.26.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC3 |
| TCELL26:OUT.27.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC2 |
| TCELL26:OUT.28.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC1 |
| TCELL26:OUT.29.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_OUT_EXT_DDRMC0 |
| TCELL26:OUT.30.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CNTRL_CHNL_OUT_EXT_DDRMC1 |
| TCELL26:OUT.31.TMIN | LPDDRMC.IF_DMC_FABRIC_SCAN_CNTRL_CHNL_OUT_EXT_DDRMC0 |
| TCELL26:IMUX.CTRL.0 | LPDDRMC.IF_DMC_FABRIC_BLI2UB_TRACE_CLK |
| TCELL26:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT9 |
| TCELL26:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN9 |
| TCELL26:IMUX.IMUX.1.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_1_1 |
| TCELL26:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P10_CLB2RIU_NIBBLE_SEL |
| TCELL26:IMUX.IMUX.3.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2UB_TRACE_TREADY |
| TCELL26:IMUX.IMUX.4.DELAY | LPDDRMC.IF_DMC_FABRIC_BLOCK_PERIODIC_CAL |
| TCELL26:IMUX.IMUX.5.DELAY | LPDDRMC.IF_DMC_FABRIC_CSSD_TRIG_IN_N_EXT |
| TCELL26:IMUX.IMUX.6.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I23 |
| TCELL26:IMUX.IMUX.7.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I20 |
| TCELL26:IMUX.IMUX.8.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I17 |
| TCELL26:IMUX.IMUX.9.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I14 |
| TCELL26:IMUX.IMUX.10.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I11 |
| TCELL26:IMUX.IMUX.11.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I8 |
| TCELL26:IMUX.IMUX.12.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I5 |
| TCELL26:IMUX.IMUX.13.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I2 |
| TCELL26:IMUX.IMUX.14.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTRDCI_USR_RST |
| TCELL26:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_3 |
| TCELL26:IMUX.IMUX.16.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_0_1 |
| TCELL26:IMUX.IMUX.17.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_0_0 |
| TCELL26:IMUX.IMUX.18.DELAY | LPDDRMC.IF_DMC_FABRIC_REF_RANK_EN_1_0 |
| TCELL26:IMUX.IMUX.19.DELAY | LPDDRMC.IF_DMC_FABRIC_EXMON_CLEAR_IN |
| TCELL26:IMUX.IMUX.20.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2UB_TRIG |
| TCELL26:IMUX.IMUX.21.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2UB_ACK |
| TCELL26:IMUX.IMUX.22.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2UB_TRACE_RST_N |
| TCELL26:IMUX.IMUX.23.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2UB_UART_RX |
| TCELL26:IMUX.IMUX.24.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2ILA_TRIG |
| TCELL26:IMUX.IMUX.25.DELAY | LPDDRMC.IF_DMC_FABRIC_BLI2ILA_ACK |
| TCELL26:IMUX.IMUX.26.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2IOB_PUDC_B |
| TCELL26:IMUX.IMUX.27.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_RST_N |
| TCELL26:IMUX.IMUX.28.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I22 |
| TCELL26:IMUX.IMUX.29.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I21 |
| TCELL26:IMUX.IMUX.30.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I19 |
| TCELL26:IMUX.IMUX.31.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I18 |
| TCELL26:IMUX.IMUX.32.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I16 |
| TCELL26:IMUX.IMUX.33.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I15 |
| TCELL26:IMUX.IMUX.34.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I13 |
| TCELL26:IMUX.IMUX.35.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I12 |
| TCELL26:IMUX.IMUX.36.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I10 |
| TCELL26:IMUX.IMUX.37.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I9 |
| TCELL26:IMUX.IMUX.38.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I7 |
| TCELL26:IMUX.IMUX.39.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I6 |
| TCELL26:IMUX.IMUX.40.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I4 |
| TCELL26:IMUX.IMUX.41.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I3 |
| TCELL26:IMUX.IMUX.42.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I1 |
| TCELL26:IMUX.IMUX.43.DELAY | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CLB2CTR_DCI_TEST_I_CLOCK |
| TCELL26:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_7 |
| TCELL26:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_5 |
| TCELL26:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_1 |
| TCELL26:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_0 |
| TCELL27:OUT.3.TMIN | LPDDRMC.IF_DMC_FABRIC_CSSD_CLKSTP_BCAST |
| TCELL27:OUT.4.TMIN | LPDDRMC.IF_DMC_FABRIC_EXMON_CLEAR_OUT |
| TCELL27:OUT.5.TMIN | LPDDRMC.IF_DMC_FABRIC_LPDDRMC_SPARE1 |
| TCELL27:OUT.6.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_ACK |
| TCELL27:OUT.7.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRIG |
| TCELL27:OUT.8.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA15 |
| TCELL27:OUT.9.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA14 |
| TCELL27:OUT.10.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA13 |
| TCELL27:OUT.11.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA12 |
| TCELL27:OUT.12.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA11 |
| TCELL27:OUT.13.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA10 |
| TCELL27:OUT.14.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA9 |
| TCELL27:OUT.15.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA8 |
| TCELL27:OUT.16.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA7 |
| TCELL27:OUT.17.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA6 |
| TCELL27:OUT.18.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA5 |
| TCELL27:OUT.19.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA4 |
| TCELL27:OUT.20.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA3 |
| TCELL27:OUT.21.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA2 |
| TCELL27:OUT.22.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA1 |
| TCELL27:OUT.23.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TDATA0 |
| TCELL27:OUT.24.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_TRACE_TVALID |
| TCELL27:OUT.25.TMIN | LPDDRMC.IF_DMC_FABRIC_UB2BLI_UART_TX |
| TCELL27:OUT.26.TMIN | LPDDRMC.IF_DMC_FABRIC_ILA2BLI_ACK |
| TCELL27:OUT.27.TMIN | LPDDRMC.IF_DMC_FABRIC_ILA2BLI_TRIG |
| TCELL27:OUT.29.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O21 |
| TCELL27:OUT.30.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O23 |
| TCELL27:OUT.31.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O22 |
| TCELL27:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_EDT_UPDT_N_EXT |
| TCELL27:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_6 |
| TCELL27:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_3 |
| TCELL27:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_2 |
| TCELL27:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_7 |
| TCELL27:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_1 |
| TCELL27:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_4 |
| TCELL27:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_5 |
| TCELL27:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_0 |
| TCELL27:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_6 |
| TCELL27:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_3 |
| TCELL27:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_2 |
| TCELL27:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL27:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL27:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE3 |
| TCELL27:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE0 |
| TCELL27:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_2 |
| TCELL27:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ0_4 |
| TCELL27:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_7 |
| TCELL27:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_5 |
| TCELL27:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_1 |
| TCELL27:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_0 |
| TCELL27:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_4 |
| TCELL27:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ1_6 |
| TCELL27:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_5 |
| TCELL27:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_3 |
| TCELL27:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_0 |
| TCELL27:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_2 |
| TCELL27:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ2_6 |
| TCELL27:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_7 |
| TCELL27:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_3 |
| TCELL27:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_1 |
| TCELL27:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_2 |
| TCELL27:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ3_4 |
| TCELL27:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_7 |
| TCELL27:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_5 |
| TCELL27:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_1 |
| TCELL27:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_0 |
| TCELL27:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_4 |
| TCELL27:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ4_6 |
| TCELL27:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL27:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL27:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE5 |
| TCELL27:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE4 |
| TCELL27:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE2 |
| TCELL27:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IBUF_DISABLE1 |
| TCELL27:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DLYCTL_EN_VTC |
| TCELL27:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE5 |
| TCELL28:OUT.3.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_LOCK |
| TCELL28:OUT.4.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O20 |
| TCELL28:OUT.5.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O19 |
| TCELL28:OUT.6.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O18 |
| TCELL28:OUT.7.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O17 |
| TCELL28:OUT.8.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O16 |
| TCELL28:OUT.9.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O15 |
| TCELL28:OUT.10.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O14 |
| TCELL28:OUT.11.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O13 |
| TCELL28:OUT.12.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O12 |
| TCELL28:OUT.13.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O11 |
| TCELL28:OUT.14.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O10 |
| TCELL28:OUT.15.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O9 |
| TCELL28:OUT.16.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O8 |
| TCELL28:OUT.17.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O7 |
| TCELL28:OUT.18.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O6 |
| TCELL28:OUT.19.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O5 |
| TCELL28:OUT.20.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O4 |
| TCELL28:OUT.21.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O3 |
| TCELL28:OUT.22.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O2 |
| TCELL28:OUT.23.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O1 |
| TCELL28:OUT.24.TMIN | LPDDRMC.IF_XPIO_DCI_FABRIC_DMC_OABUT_CTR2CLB_DCI_TEST_O0 |
| TCELL28:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_PHY_RDY |
| TCELL28:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_GT_STATUS |
| TCELL28:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_MASTER_PD |
| TCELL28:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL28:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL28:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_7 |
| TCELL28:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_5 |
| TCELL28:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN3 |
| TCELL28:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE4 |
| TCELL28:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_5 |
| TCELL28:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_3 |
| TCELL28:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE3 |
| TCELL28:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_1 |
| TCELL28:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE2 |
| TCELL28:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE1 |
| TCELL28:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CE0 |
| TCELL28:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_0 |
| TCELL28:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC5 |
| TCELL28:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_2 |
| TCELL28:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_4 |
| TCELL28:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC4 |
| TCELL28:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_6 |
| TCELL28:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC3 |
| TCELL28:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WR_DQ5_7 |
| TCELL29:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_3 |
| TCELL29:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_1 |
| TCELL29:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_0 |
| TCELL29:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_2 |
| TCELL29:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_4 |
| TCELL29:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ0_6 |
| TCELL29:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL29:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL29:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL29:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL29:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL29:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL29:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_7 |
| TCELL29:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_5 |
| TCELL29:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_3 |
| TCELL29:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_1 |
| TCELL29:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_0 |
| TCELL29:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_2 |
| TCELL29:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_4 |
| TCELL29:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ1_6 |
| TCELL29:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL29:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL29:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL29:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL29:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL29:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_7 |
| TCELL29:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_FIFO_EMPTY |
| TCELL29:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_FIXDLY_RDY |
| TCELL29:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_5 |
| TCELL29:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT0 |
| TCELL29:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RST |
| TCELL29:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC1 |
| TCELL29:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC0 |
| TCELL29:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST5 |
| TCELL29:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD5 |
| TCELL29:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST4 |
| TCELL29:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD4 |
| TCELL29:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST3 |
| TCELL29:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD3 |
| TCELL29:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST2 |
| TCELL29:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD2 |
| TCELL29:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST1 |
| TCELL29:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD1 |
| TCELL29:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_TXBIT_RST0 |
| TCELL29:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_LD0 |
| TCELL29:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_INC2 |
| TCELL30:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_3 |
| TCELL30:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_1 |
| TCELL30:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_0 |
| TCELL30:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_2 |
| TCELL30:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_4 |
| TCELL30:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ2_6 |
| TCELL30:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL30:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL30:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL30:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL30:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL30:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_7 |
| TCELL30:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_5 |
| TCELL30:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_3 |
| TCELL30:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_1 |
| TCELL30:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_0 |
| TCELL30:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_2 |
| TCELL30:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_4 |
| TCELL30:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ3_6 |
| TCELL30:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL30:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL30:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL30:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL30:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL30:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_7 |
| TCELL30:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_5 |
| TCELL30:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_3 |
| TCELL30:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_1 |
| TCELL30:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_0 |
| TCELL30:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2MC_DIV_CLK |
| TCELL30:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_CTRL_CLK |
| TCELL30:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_FIFO_CLK |
| TCELL30:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN9 |
| TCELL30:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG4 |
| TCELL30:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL30:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST4 |
| TCELL30:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL30:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST3 |
| TCELL30:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL30:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST2 |
| TCELL30:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL30:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST1 |
| TCELL30:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL30:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST0 |
| TCELL30:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL30:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WREN3 |
| TCELL30:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL30:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WREN2 |
| TCELL30:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL30:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RXBIT_RST5 |
| TCELL31:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_2 |
| TCELL31:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_4 |
| TCELL31:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ4_6 |
| TCELL31:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL31:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL31:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL31:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL31:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL31:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL31:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL31:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL31:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_7 |
| TCELL31:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_5 |
| TCELL31:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_3 |
| TCELL31:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL31:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_1 |
| TCELL31:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_0 |
| TCELL31:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_2 |
| TCELL31:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_4 |
| TCELL31:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_RD_DQ5_6 |
| TCELL31:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL31:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL31:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL31:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL31:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL31:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL31:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL31:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL31:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL31:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT9 |
| TCELL31:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL31:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WREN0 |
| TCELL31:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL31:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT5 |
| TCELL31:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL31:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT4 |
| TCELL31:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL31:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT3 |
| TCELL31:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL31:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT2 |
| TCELL31:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL31:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT1 |
| TCELL31:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL31:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_T_TXBIT0 |
| TCELL31:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL31:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_WREN1 |
| TCELL32:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL32:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL32:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL32:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL32:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL32:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL32:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL32:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL32:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL32:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL32:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL32:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL32:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL32:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT5 |
| TCELL32:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT4 |
| TCELL32:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT3 |
| TCELL32:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT2 |
| TCELL32:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT1 |
| TCELL32:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_IOB2CLB_DFT0 |
| TCELL32:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_2 |
| TCELL32:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_1 |
| TCELL32:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_0_0 |
| TCELL32:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_2 |
| TCELL32:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_1 |
| TCELL32:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_PHY2CLB_LP_I_1_0 |
| TCELL32:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA15 |
| TCELL32:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA14 |
| TCELL32:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA13 |
| TCELL32:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_VALID |
| TCELL32:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT0 |
| TCELL32:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN2 |
| TCELL32:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL32:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_FIFO_RDEN |
| TCELL32:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL32:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL32:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL32:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL32:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL32:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL32:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL32:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL32:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL32:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL32:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL32:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL32:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN3 |
| TCELL32:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL32:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL32:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN1 |
| TCELL32:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_RDEN0 |
| TCELL32:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL32:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL32:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL32:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL32:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL32:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL32:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL32:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL32:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL32:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL32:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL32:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL32:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL32:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL32:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL32:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL32:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL32:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL32:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL32:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL32:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL32:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL32:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL32:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL32:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL32:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL5 |
| TCELL32:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL4 |
| TCELL33:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA12 |
| TCELL33:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA11 |
| TCELL33:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA10 |
| TCELL33:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA9 |
| TCELL33:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA8 |
| TCELL33:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA7 |
| TCELL33:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA6 |
| TCELL33:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA5 |
| TCELL33:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA4 |
| TCELL33:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA3 |
| TCELL33:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA2 |
| TCELL33:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA1 |
| TCELL33:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P5_RIU2CLB_RD_DATA0 |
| TCELL33:OUT.16.TMIN | LPDDRMC.CFG2IOB_PUDC_B_O |
| TCELL33:OUT.18.TMIN | LPDDRMC.IJTAG_RESET_TAP_O |
| TCELL33:OUT.21.TMIN | LPDDRMC.CAPTURE_DR_O |
| TCELL33:OUT.22.TMIN | LPDDRMC.SELECT_DR_O |
| TCELL33:OUT.26.TMIN | LPDDRMC.IJTAG_TDO_OABUT |
| TCELL33:OUT.27.TMIN | LPDDRMC.IJTAG_TDO_RETURN_EXT |
| TCELL33:OUT.28.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT2 |
| TCELL33:OUT.29.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT6 |
| TCELL33:OUT.30.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT10 |
| TCELL33:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG7 |
| TCELL33:IMUX.IMUX.0.DELAY | ABUS_SWITCH_XP5IO0.TEST_ANALOGBUS_SEL_B |
| TCELL33:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL1 |
| TCELL33:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL33:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL33:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL33:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL33:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL33:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL33:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_1 |
| TCELL33:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL33:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL33:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN4 |
| TCELL33:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN1 |
| TCELL33:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR6 |
| TCELL33:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR3 |
| TCELL33:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR0 |
| TCELL33:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL3 |
| TCELL33:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL2 |
| TCELL33:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IODELAY_SEL0 |
| TCELL33:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL33:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL33:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL33:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL33:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL33:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL33:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL33:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL33:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL33:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL33:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL33:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL33:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_2 |
| TCELL33:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_PD_EN_1_0 |
| TCELL33:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL33:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL33:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL33:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL33:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN5 |
| TCELL33:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN3 |
| TCELL33:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN2 |
| TCELL33:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2PHY_KEEPER_EN0 |
| TCELL33:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR7 |
| TCELL33:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR5 |
| TCELL33:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR4 |
| TCELL33:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR2 |
| TCELL33:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_ADDR1 |
| TCELL33:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA15 |
| TCELL33:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA14 |
| TCELL34:OUT.3.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT4 |
| TCELL34:OUT.4.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT0 |
| TCELL34:OUT.5.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT7 |
| TCELL34:OUT.6.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION6 |
| TCELL34:OUT.7.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION4 |
| TCELL34:OUT.8.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT8 |
| TCELL34:OUT.9.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION2 |
| TCELL34:OUT.10.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT9 |
| TCELL34:OUT.11.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT10 |
| TCELL34:OUT.12.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION0 |
| TCELL34:OUT.13.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION8 |
| TCELL34:OUT.14.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION10 |
| TCELL34:OUT.15.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT0 |
| TCELL34:OUT.16.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT2 |
| TCELL34:OUT.17.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT1 |
| TCELL34:OUT.18.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT5 |
| TCELL34:OUT.19.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT3 |
| TCELL34:OUT.20.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT4 |
| TCELL34:OUT.21.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT8 |
| TCELL34:OUT.22.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT6 |
| TCELL34:OUT.23.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT3 |
| TCELL34:OUT.24.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT1 |
| TCELL34:OUT.25.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION11 |
| TCELL34:OUT.26.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION9 |
| TCELL34:OUT.27.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION5 |
| TCELL34:OUT.28.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION3 |
| TCELL34:OUT.29.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION1 |
| TCELL34:OUT.30.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_DFX_UNEXPECTED_ACTIVATION7 |
| TCELL34:OUT.31.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT5 |
| TCELL34:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_FIFO_CLK |
| TCELL34:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_CTRL_CLK |
| TCELL34:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2MC_DIV_CLK |
| TCELL34:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN1 |
| TCELL34:IMUX.IMUX.0.DELAY | ABUS_SWITCH_XP5IO1.TEST_ANALOGBUS_SEL_B |
| TCELL34:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA11 |
| TCELL34:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA8 |
| TCELL34:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA5 |
| TCELL34:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA2 |
| TCELL34:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_EN |
| TCELL34:IMUX.IMUX.9.DELAY | LPDDRMC.IJTAG_TDI_EXT |
| TCELL34:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST5 |
| TCELL34:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST2 |
| TCELL34:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST5 |
| TCELL34:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST2 |
| TCELL34:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WREN3 |
| TCELL34:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WREN0 |
| TCELL34:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA13 |
| TCELL34:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA12 |
| TCELL34:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA10 |
| TCELL34:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA9 |
| TCELL34:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA7 |
| TCELL34:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA6 |
| TCELL34:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA4 |
| TCELL34:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA3 |
| TCELL34:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA1 |
| TCELL34:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_WR_DATA0 |
| TCELL34:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P5_CLB2RIU_NIBBLE_SEL |
| TCELL34:IMUX.IMUX.27.DELAY | LPDDRMC.CFG2IOB_PUDC_B |
| TCELL34:IMUX.IMUX.28.DELAY | LPDDRMC.IJTAG_RESET_TAP |
| TCELL34:IMUX.IMUX.30.DELAY | LPDDRMC.CAPTURE_DR |
| TCELL34:IMUX.IMUX.31.DELAY | LPDDRMC.SELECT_DR |
| TCELL34:IMUX.IMUX.34.DELAY | LPDDRMC.IJTAG_TDI_RETURN_EXT |
| TCELL34:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RST |
| TCELL34:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST4 |
| TCELL34:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST3 |
| TCELL34:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST1 |
| TCELL34:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_TXBIT_RST0 |
| TCELL34:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST4 |
| TCELL34:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST3 |
| TCELL34:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST1 |
| TCELL34:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RXBIT_RST0 |
| TCELL34:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WREN2 |
| TCELL34:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WREN1 |
| TCELL34:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT5 |
| TCELL34:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT4 |
| TCELL35:OUT.3.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT7 |
| TCELL35:OUT.4.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_COMP_OUT9 |
| TCELL35:OUT.5.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT0 |
| TCELL35:OUT.6.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT2 |
| TCELL35:OUT.7.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT4 |
| TCELL35:OUT.8.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT6 |
| TCELL35:OUT.9.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT8 |
| TCELL35:OUT.10.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_OUT10 |
| TCELL35:OUT.11.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT1 |
| TCELL35:OUT.12.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT3 |
| TCELL35:OUT.13.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT5 |
| TCELL35:OUT.14.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT7 |
| TCELL35:OUT.15.TMIN | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_PHY2CLB_SCAN_CNTRL_CHNL_OUT9 |
| TCELL35:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_FIFO_EMPTY |
| TCELL35:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_FIXDLY_RDY |
| TCELL35:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_PHY_RDY |
| TCELL35:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_GT_STATUS |
| TCELL35:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_MASTER_PD |
| TCELL35:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL35:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL35:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL35:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL35:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL35:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL35:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL35:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL35:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL35:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL35:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL35:IMUX.BYP.8.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT4 |
| TCELL35:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT3 |
| TCELL35:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT0 |
| TCELL35:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN1 |
| TCELL35:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL35:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL35:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE5 |
| TCELL35:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE2 |
| TCELL35:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DLYCTL_EN_VTC |
| TCELL35:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE3 |
| TCELL35:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE0 |
| TCELL35:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC3 |
| TCELL35:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC0 |
| TCELL35:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD3 |
| TCELL35:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD0 |
| TCELL35:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL35:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL35:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT2 |
| TCELL35:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_T_TXBIT1 |
| TCELL35:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN3 |
| TCELL35:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN2 |
| TCELL35:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_RDEN0 |
| TCELL35:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_FIFO_RDEN |
| TCELL35:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL35:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL35:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL35:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL35:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE4 |
| TCELL35:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE3 |
| TCELL35:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE1 |
| TCELL35:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IBUF_DISABLE0 |
| TCELL35:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE5 |
| TCELL35:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE4 |
| TCELL35:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE2 |
| TCELL35:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CE1 |
| TCELL35:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC5 |
| TCELL35:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC4 |
| TCELL35:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC2 |
| TCELL35:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_INC1 |
| TCELL35:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD5 |
| TCELL35:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD4 |
| TCELL35:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD2 |
| TCELL35:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_LD1 |
| TCELL35:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL35:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL35:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL35:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL35:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL35:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL36:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL36:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL36:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL36:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL36:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL36:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL36:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL36:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL36:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL36:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL36:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL36:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL36:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL36:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL36:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL36:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL36:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL36:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL36:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL36:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL36:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL36:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL36:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL36:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL36:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL36:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL36:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL36:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL36:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL36:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL36:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL36:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL36:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL36:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL36:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL36:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL36:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL36:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL36:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL36:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL36:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL36:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL36:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL36:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL36:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL36:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL36:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL36:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL36:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL36:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL36:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL36:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL36:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL36:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL36:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL36:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL36:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL36:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL36:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL36:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL36:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL36:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL36:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL36:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL36:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL36:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL36:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL36:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL36:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL36:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL36:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL36:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL36:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL36:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL36:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL36:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL36:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL36:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL5 |
| TCELL37:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL37:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL37:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL37:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL37:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL37:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL37:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL37:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL37:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL37:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL37:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL37:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL37:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT5 |
| TCELL37:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT4 |
| TCELL37:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT3 |
| TCELL37:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT2 |
| TCELL37:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT1 |
| TCELL37:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_IOB2CLB_DFT0 |
| TCELL37:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_2 |
| TCELL37:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_1 |
| TCELL37:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_0_0 |
| TCELL37:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_2 |
| TCELL37:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_1 |
| TCELL37:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_LP_I_1_0 |
| TCELL37:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA15 |
| TCELL37:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA14 |
| TCELL37:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA13 |
| TCELL37:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA12 |
| TCELL37:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA11 |
| TCELL37:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA10 |
| TCELL37:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA9 |
| TCELL37:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA8 |
| TCELL37:IMUX.BYP.7.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CNTRL_CHNL_IN_EXT_DDRMC1 |
| TCELL37:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN5 |
| TCELL37:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL4 |
| TCELL37:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL1 |
| TCELL37:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL37:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL37:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL37:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL37:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL37:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL37:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_6 |
| TCELL37:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_0 |
| TCELL37:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_5 |
| TCELL37:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_4 |
| TCELL37:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_1 |
| TCELL37:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_7 |
| TCELL37:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_4 |
| TCELL37:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_1 |
| TCELL37:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL3 |
| TCELL37:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL2 |
| TCELL37:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IODELAY_SEL0 |
| TCELL37:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL37:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL37:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL37:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL37:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL37:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL37:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL37:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL37:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL37:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL37:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL37:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL37:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_NIBBLE_SEL |
| TCELL37:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_4 |
| TCELL37:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_2 |
| TCELL37:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_1 |
| TCELL37:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_3 |
| TCELL37:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ5_7 |
| TCELL37:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_6 |
| TCELL37:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_2 |
| TCELL37:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_0 |
| TCELL37:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_3 |
| TCELL37:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ4_5 |
| TCELL37:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_2 |
| TCELL37:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_6 |
| TCELL37:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_2 |
| TCELL37:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_0 |
| TCELL37:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_3 |
| TCELL37:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_5 |
| TCELL38:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA7 |
| TCELL38:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA6 |
| TCELL38:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA5 |
| TCELL38:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA4 |
| TCELL38:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA3 |
| TCELL38:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA2 |
| TCELL38:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA1 |
| TCELL38:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_RD_DATA0 |
| TCELL38:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_RIU2CLB_VALID |
| TCELL38:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_6 |
| TCELL38:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_4 |
| TCELL38:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_2 |
| TCELL38:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_0 |
| TCELL38:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_1 |
| TCELL38:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_3 |
| TCELL38:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_5 |
| TCELL38:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ5_7 |
| TCELL38:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_6 |
| TCELL38:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_4 |
| TCELL38:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_2 |
| TCELL38:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_0 |
| TCELL38:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_1 |
| TCELL38:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_3 |
| TCELL38:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_5 |
| TCELL38:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ4_7 |
| TCELL38:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_6 |
| TCELL38:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_4 |
| TCELL38:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_2 |
| TCELL38:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_0 |
| TCELL38:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_1 |
| TCELL38:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_3 |
| TCELL38:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_5 |
| TCELL38:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2MC_DIV_CLK |
| TCELL38:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_FIFO_CLK |
| TCELL38:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_CTRL_CLK |
| TCELL38:IMUX.BYP.8.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_MODE_RST_N_EXT |
| TCELL38:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ3_7 |
| TCELL38:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL38:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL38:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN5 |
| TCELL38:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_6 |
| TCELL38:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_0 |
| TCELL38:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_5 |
| TCELL38:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN1 |
| TCELL38:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR6 |
| TCELL38:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR3 |
| TCELL38:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR0 |
| TCELL38:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA13 |
| TCELL38:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA10 |
| TCELL38:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA7 |
| TCELL38:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA4 |
| TCELL38:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA1 |
| TCELL38:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_1 |
| TCELL38:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_PD_EN_1_0 |
| TCELL38:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL38:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL38:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL38:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL38:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN4 |
| TCELL38:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN3 |
| TCELL38:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_4 |
| TCELL38:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_2 |
| TCELL38:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_1 |
| TCELL38:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_3 |
| TCELL38:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ2_7 |
| TCELL38:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN2 |
| TCELL38:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_KEEPER_EN0 |
| TCELL38:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR7 |
| TCELL38:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR5 |
| TCELL38:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR4 |
| TCELL38:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR2 |
| TCELL38:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_ADDR1 |
| TCELL38:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA15 |
| TCELL38:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA14 |
| TCELL38:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA12 |
| TCELL38:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA11 |
| TCELL38:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA9 |
| TCELL38:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA8 |
| TCELL38:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA6 |
| TCELL38:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA5 |
| TCELL38:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA3 |
| TCELL38:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA2 |
| TCELL38:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_DATA0 |
| TCELL38:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2RIU_WR_EN |
| TCELL39:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ3_7 |
| TCELL39:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_6 |
| TCELL39:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_4 |
| TCELL39:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_2 |
| TCELL39:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_0 |
| TCELL39:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_1 |
| TCELL39:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_3 |
| TCELL39:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_5 |
| TCELL39:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ2_7 |
| TCELL39:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_6 |
| TCELL39:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_4 |
| TCELL39:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_2 |
| TCELL39:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_0 |
| TCELL39:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_1 |
| TCELL39:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_3 |
| TCELL39:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_5 |
| TCELL39:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ1_7 |
| TCELL39:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_6 |
| TCELL39:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_4 |
| TCELL39:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_2 |
| TCELL39:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_0 |
| TCELL39:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_1 |
| TCELL39:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_3 |
| TCELL39:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_5 |
| TCELL39:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P4_PHY2CLB_RD_DQ0_7 |
| TCELL39:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_7 |
| TCELL39:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_5 |
| TCELL39:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_3 |
| TCELL39:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_1 |
| TCELL39:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_0 |
| TCELL39:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_2 |
| TCELL39:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_4 |
| TCELL39:IMUX.BYP.7.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT6 |
| TCELL39:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG1 |
| TCELL39:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_MODE_RST_B |
| TCELL39:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_6 |
| TCELL39:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_0 |
| TCELL39:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_5 |
| TCELL39:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_4 |
| TCELL39:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_1 |
| TCELL39:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_7 |
| TCELL39:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_3 |
| TCELL39:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_2 |
| TCELL39:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_7 |
| TCELL39:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_1 |
| TCELL39:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_4 |
| TCELL39:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST5 |
| TCELL39:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST2 |
| TCELL39:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST5 |
| TCELL39:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST2 |
| TCELL39:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL39:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_4 |
| TCELL39:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_2 |
| TCELL39:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_1 |
| TCELL39:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_3 |
| TCELL39:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ1_7 |
| TCELL39:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_6 |
| TCELL39:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_2 |
| TCELL39:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_0 |
| TCELL39:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_3 |
| TCELL39:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P4_CLB2PHY_WR_DQ0_5 |
| TCELL39:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_7 |
| TCELL39:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_5 |
| TCELL39:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_1 |
| TCELL39:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_0 |
| TCELL39:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_4 |
| TCELL39:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_215_208_NIB3_CLB2PHY_WR_DQ0_6 |
| TCELL39:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_5 |
| TCELL39:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_3 |
| TCELL39:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_0 |
| TCELL39:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_2 |
| TCELL39:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_WDATA_223_216_NIB3_CLB2PHY_WR_DQ1_6 |
| TCELL39:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RST |
| TCELL39:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST4 |
| TCELL39:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST3 |
| TCELL39:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST1 |
| TCELL39:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_TXBIT_RST0 |
| TCELL39:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST4 |
| TCELL39:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST3 |
| TCELL39:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST1 |
| TCELL39:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_RXBIT_RST0 |
| TCELL39:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL39:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL40:OUT.0.TMIN | LPDDRMC.AXI0_RDATA_215_208_NIB3_PHY2CLB_RD_DQ0_6 |
| TCELL40:OUT.1.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_7 |
| TCELL40:OUT.2.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_5 |
| TCELL40:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_3 |
| TCELL40:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_1 |
| TCELL40:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_0 |
| TCELL40:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_2 |
| TCELL40:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_4 |
| TCELL40:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_223_216_NIB3_PHY2CLB_RD_DQ1_6 |
| TCELL40:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_7 |
| TCELL40:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_5 |
| TCELL40:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_3 |
| TCELL40:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_1 |
| TCELL40:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_0 |
| TCELL40:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_2 |
| TCELL40:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_4 |
| TCELL40:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_231_224_NIB3_PHY2CLB_RD_DQ2_6 |
| TCELL40:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_7 |
| TCELL40:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_5 |
| TCELL40:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_3 |
| TCELL40:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_1 |
| TCELL40:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_0 |
| TCELL40:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_2 |
| TCELL40:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_4 |
| TCELL40:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_239_232_NIB3_PHY2CLB_RD_DQ3_6 |
| TCELL40:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_FIFO_EMPTY |
| TCELL40:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_FIXDLY_RDY |
| TCELL40:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_PHY_RDY |
| TCELL40:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_GT_STATUS |
| TCELL40:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_MASTER_PD |
| TCELL40:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT5 |
| TCELL40:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT4 |
| TCELL40:IMUX.BYP.7.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CLK_B |
| TCELL40:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG6 |
| TCELL40:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL40:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE5 |
| TCELL40:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE2 |
| TCELL40:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE5 |
| TCELL40:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_5 |
| TCELL40:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_0 |
| TCELL40:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_6 |
| TCELL40:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE1 |
| TCELL40:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC4 |
| TCELL40:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC1 |
| TCELL40:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD4 |
| TCELL40:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD1 |
| TCELL40:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL40:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL40:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL40:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL40:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL40:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL40:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE4 |
| TCELL40:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE3 |
| TCELL40:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE1 |
| TCELL40:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IBUF_DISABLE0 |
| TCELL40:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE4 |
| TCELL40:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_7 |
| TCELL40:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_3 |
| TCELL40:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_1 |
| TCELL40:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_2 |
| TCELL40:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_231_224_NIB3_CLB2PHY_WR_DQ2_4 |
| TCELL40:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE3 |
| TCELL40:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE2 |
| TCELL40:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_CE0 |
| TCELL40:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC5 |
| TCELL40:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC3 |
| TCELL40:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC2 |
| TCELL40:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_INC0 |
| TCELL40:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD5 |
| TCELL40:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD3 |
| TCELL40:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD2 |
| TCELL40:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_IODELAY_LD0 |
| TCELL40:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL40:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL40:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL40:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL40:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL40:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL40:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL40:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL40:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL41:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT3 |
| TCELL41:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT2 |
| TCELL41:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT1 |
| TCELL41:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_IOB2CLB_DFT0 |
| TCELL41:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_2 |
| TCELL41:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_1 |
| TCELL41:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_0_0 |
| TCELL41:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_2 |
| TCELL41:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_1 |
| TCELL41:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_PHY2CLB_LP_I_1_0 |
| TCELL41:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P3_RIU2CLB_VALID |
| TCELL41:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_7 |
| TCELL41:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_5 |
| TCELL41:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_3 |
| TCELL41:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_1 |
| TCELL41:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_0 |
| TCELL41:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_2 |
| TCELL41:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_4 |
| TCELL41:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_247_240_NIB3_PHY2CLB_RD_DQ4_6 |
| TCELL41:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_7 |
| TCELL41:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_5 |
| TCELL41:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_3 |
| TCELL41:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_1 |
| TCELL41:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_0 |
| TCELL41:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_2 |
| TCELL41:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_4 |
| TCELL41:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_255_248_NIB3_PHY2CLB_RD_DQ5_6 |
| TCELL41:OUT.27.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL41:OUT.28.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL41:OUT.29.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL41:OUT.30.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL41:OUT.31.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL41:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN4 |
| TCELL41:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_3 |
| TCELL41:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_2 |
| TCELL41:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL41:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_3 |
| TCELL41:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_2 |
| TCELL41:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_7 |
| TCELL41:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_1 |
| TCELL41:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_4 |
| TCELL41:IMUX.IMUX.9.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL41:IMUX.IMUX.10.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL41:IMUX.IMUX.11.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL41:IMUX.IMUX.12.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL41:IMUX.IMUX.13.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL41:IMUX.IMUX.14.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL41:IMUX.IMUX.15.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL41:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_7 |
| TCELL41:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_5 |
| TCELL41:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_1 |
| TCELL41:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_0 |
| TCELL41:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_4 |
| TCELL41:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WDATA_239_232_NIB3_CLB2PHY_WR_DQ3_6 |
| TCELL41:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_7 |
| TCELL41:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_5 |
| TCELL41:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_1 |
| TCELL41:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_0 |
| TCELL41:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_4 |
| TCELL41:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_247_240_NIB3_CLB2PHY_WR_DQ4_6 |
| TCELL41:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_5 |
| TCELL41:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_3 |
| TCELL41:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_0 |
| TCELL41:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_2 |
| TCELL41:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_255_248_NIB3_CLB2PHY_WR_DQ5_6 |
| TCELL41:IMUX.IMUX.33.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL41:IMUX.IMUX.34.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL41:IMUX.IMUX.35.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL41:IMUX.IMUX.36.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL41:IMUX.IMUX.37.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL41:IMUX.IMUX.38.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL41:IMUX.IMUX.39.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL41:IMUX.IMUX.40.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL41:IMUX.IMUX.41.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL41:IMUX.IMUX.42.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL41:IMUX.IMUX.43.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL41:IMUX.IMUX.44.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL41:IMUX.IMUX.45.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL41:IMUX.IMUX.46.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL41:IMUX.IMUX.47.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL42:OUT.0.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL42:OUT.1.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL42:OUT.2.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL42:OUT.3.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL42:OUT.4.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL42:OUT.5.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL42:OUT.6.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL42:OUT.7.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL42:OUT.8.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL42:OUT.9.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL42:OUT.10.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL42:OUT.11.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL42:OUT.12.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL42:OUT.13.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL42:OUT.14.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL42:OUT.15.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL42:OUT.16.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL42:OUT.17.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL42:OUT.18.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL42:OUT.19.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL42:OUT.20.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL42:OUT.21.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL42:OUT.22.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL42:OUT.23.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL42:OUT.24.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL42:OUT.25.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL42:OUT.26.TMIN | LPDDRMC.MAXI_DCWDATA_31_0_NIB3_31_0_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL42:OUT.27.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL42:OUT.28.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL42:OUT.29.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL42:OUT.30.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL42:OUT.31.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL42:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN5 |
| TCELL42:IMUX.IMUX.0.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL42:IMUX.IMUX.1.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL42:IMUX.IMUX.2.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL42:IMUX.IMUX.3.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL42:IMUX.IMUX.4.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL42:IMUX.IMUX.5.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL42:IMUX.IMUX.6.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL42:IMUX.IMUX.7.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL42:IMUX.IMUX.8.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL42:IMUX.IMUX.9.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL42:IMUX.IMUX.10.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL42:IMUX.IMUX.11.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL42:IMUX.IMUX.12.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL42:IMUX.IMUX.13.DELAY | LPDDRMC.MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_1 |
| TCELL42:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA15 |
| TCELL42:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA12 |
| TCELL42:IMUX.IMUX.16.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL42:IMUX.IMUX.17.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL42:IMUX.IMUX.18.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL42:IMUX.IMUX.19.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL42:IMUX.IMUX.20.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL42:IMUX.IMUX.21.DELAY | LPDDRMC.MAXI_DCRDATA_31_0_NIB3_31_0_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL42:IMUX.IMUX.22.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL42:IMUX.IMUX.23.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL42:IMUX.IMUX.24.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL42:IMUX.IMUX.25.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL42:IMUX.IMUX.26.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL42:IMUX.IMUX.27.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL42:IMUX.IMUX.28.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL42:IMUX.IMUX.29.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL42:IMUX.IMUX.30.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL42:IMUX.IMUX.31.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL42:IMUX.IMUX.32.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL42:IMUX.IMUX.33.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL42:IMUX.IMUX.34.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL42:IMUX.IMUX.35.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL42:IMUX.IMUX.36.DELAY | LPDDRMC.MAXI_ICRDATA_21_0_NIB3_53_32_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL42:IMUX.IMUX.37.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL42:IMUX.IMUX.38.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL42:IMUX.IMUX.39.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL42:IMUX.IMUX.40.DELAY | LPDDRMC.MAXI_ICRDATA_27_22_NIB3_5_0_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL42:IMUX.IMUX.41.DELAY | LPDDRMC.MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_2 |
| TCELL42:IMUX.IMUX.42.DELAY | LPDDRMC.MAXI_ICRDATA_30_28_NIB3_2_0_CLB2PHY_PD_EN_1_0 |
| TCELL42:IMUX.IMUX.43.DELAY | LPDDRMC.MAXI_ICRDATA_31_NIB3_CLB2RIU_WR_EN |
| TCELL42:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA14 |
| TCELL42:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA13 |
| TCELL42:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA11 |
| TCELL42:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA10 |
| TCELL43:OUT.2.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL43:OUT.3.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL43:OUT.4.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL43:OUT.5.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL43:OUT.6.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL43:OUT.7.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL43:OUT.8.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL43:OUT.9.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL43:OUT.10.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL43:OUT.11.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL43:OUT.12.TMIN | LPDDRMC.MAXI_ICARADDR_15_0_NIB3_47_32_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL43:OUT.13.TMIN | LPDDRMC.MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL43:OUT.14.TMIN | LPDDRMC.MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL43:OUT.15.TMIN | LPDDRMC.MAXI_ICARSIZE_2_0_NIB3_50_48_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL43:OUT.16.TMIN | LPDDRMC.MAXI_ICARBURST_1_0_NIB3_52_51_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL43:OUT.17.TMIN | LPDDRMC.MAXI_ICARBURST_1_0_NIB3_52_51_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL43:OUT.18.TMIN | LPDDRMC.MAXI_ICARVALID_NIB3_53_PHY2CLB_IODELAY_CNTVALUEOUT |
| TCELL43:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA15 |
| TCELL43:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA14 |
| TCELL43:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA13 |
| TCELL43:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA12 |
| TCELL43:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA11 |
| TCELL43:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA10 |
| TCELL43:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA9 |
| TCELL43:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA8 |
| TCELL43:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA7 |
| TCELL43:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA6 |
| TCELL43:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA5 |
| TCELL43:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA4 |
| TCELL43:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA3 |
| TCELL43:IMUX.CTRL.0 | LPDDRMC.IF_UBLAZE_FABRIC_BLI2UB_CLK |
| TCELL43:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN6 |
| TCELL43:IMUX.IMUX.0.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA9 |
| TCELL43:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA7 |
| TCELL43:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA4 |
| TCELL43:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA1 |
| TCELL43:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR6 |
| TCELL43:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR3 |
| TCELL43:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR0 |
| TCELL43:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN1 |
| TCELL43:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT4 |
| TCELL43:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT1 |
| TCELL43:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN3 |
| TCELL43:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN0 |
| TCELL43:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL3 |
| TCELL43:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL0 |
| TCELL43:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL43:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN5 |
| TCELL43:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA8 |
| TCELL43:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2RIU_NIBBLE_SEL |
| TCELL43:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA6 |
| TCELL43:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA5 |
| TCELL43:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA3 |
| TCELL43:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA2 |
| TCELL43:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_207_192_NIB3_CLB2RIU_WR_DATA0 |
| TCELL43:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR7 |
| TCELL43:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR5 |
| TCELL43:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR4 |
| TCELL43:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR2 |
| TCELL43:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WSTRB_31_24_NIB3_CLB2RIU_ADDR1 |
| TCELL43:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN3 |
| TCELL43:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN2 |
| TCELL43:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_AWADDR_36_33_NIB3_CLB2PHY_WREN0 |
| TCELL43:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT5 |
| TCELL43:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT3 |
| TCELL43:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT2 |
| TCELL43:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_AWADDR_42_37_NIB3_CLB2PHY_T_TXBIT0 |
| TCELL43:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_AWADDR_43_NIB3_CLB2PHY_FIFO_RDEN |
| TCELL43:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN2 |
| TCELL43:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_ARADDR_36_33_NIB3_CLB2PHY_RDEN1 |
| TCELL43:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL5 |
| TCELL43:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL4 |
| TCELL43:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL2 |
| TCELL43:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_ARADDR_42_37_NIB3_CLB2PHY_IODELAY_SEL1 |
| TCELL43:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_ARADDR_43_NIB3_CLB2PHY_DLYCTL_EN_VTC |
| TCELL43:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL43:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL43:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL43:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN4 |
| TCELL43:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN3 |
| TCELL44:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA2 |
| TCELL44:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA1 |
| TCELL44:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_207_192_NIB3_RIU2CLB_RD_DATA0 |
| TCELL44:OUT.6.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN2 |
| TCELL44:OUT.7.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN1 |
| TCELL44:OUT.8.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN0 |
| TCELL44:OUT.9.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_RREADY |
| TCELL44:OUT.10.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE1 |
| TCELL44:OUT.11.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_AWVALID |
| TCELL44:OUT.12.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_WLAST |
| TCELL44:OUT.13.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_WVALID |
| TCELL44:OUT.14.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_BREADY |
| TCELL44:OUT.15.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE1 |
| TCELL44:OUT.16.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARBURST1 |
| TCELL44:OUT.17.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARVALID |
| TCELL44:OUT.18.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_RREADY |
| TCELL44:OUT.19.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_UB_MISC_OUT1 |
| TCELL44:OUT.20.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_UB_MISC_OUT0 |
| TCELL44:OUT.21.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_UB2BLI_SELF_REF_DONE |
| TCELL44:OUT.22.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_UB2BLI_DRAM_POWER_OFF_DONE |
| TCELL44:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_FIFO_EMPTY |
| TCELL44:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_FIXDLY_RDY |
| TCELL44:OUT.25.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_TDO |
| TCELL44:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_PHY_RDY |
| TCELL44:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_GT_STATUS |
| TCELL44:OUT.28.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARBURST0 |
| TCELL44:OUT.29.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE0 |
| TCELL44:OUT.30.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARSIZE2 |
| TCELL44:OUT.31.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE0 |
| TCELL44:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN6 |
| TCELL44:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN4 |
| TCELL44:IMUX.BYP.11.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT11 |
| TCELL44:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN2 |
| TCELL44:IMUX.IMUX.1.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARREADY |
| TCELL44:IMUX.IMUX.2.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_RRESP0 |
| TCELL44:IMUX.IMUX.3.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_WREADY |
| TCELL44:IMUX.IMUX.4.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_BVALID |
| TCELL44:IMUX.IMUX.5.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_RRESP1 |
| TCELL44:IMUX.IMUX.6.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BLI2UB_RST |
| TCELL44:IMUX.IMUX.7.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_UB_MISC_IN0 |
| TCELL44:IMUX.IMUX.8.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_CAPTURE |
| TCELL44:IMUX.IMUX.9.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_SEL |
| TCELL44:IMUX.IMUX.10.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_TDI |
| TCELL44:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA15 |
| TCELL44:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA12 |
| TCELL44:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA9 |
| TCELL44:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA6 |
| TCELL44:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA3 |
| TCELL44:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN1 |
| TCELL44:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P3_CLB2PHY_KEEPER_EN0 |
| TCELL44:IMUX.IMUX.18.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_RLAST |
| TCELL44:IMUX.IMUX.19.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_RRESP1 |
| TCELL44:IMUX.IMUX.20.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_RVALID |
| TCELL44:IMUX.IMUX.21.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_AWREADY |
| TCELL44:IMUX.IMUX.22.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_BRESP1 |
| TCELL44:IMUX.IMUX.23.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_BRESP0 |
| TCELL44:IMUX.IMUX.24.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_ARREADY |
| TCELL44:IMUX.IMUX.25.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_RLAST |
| TCELL44:IMUX.IMUX.26.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_RRESP0 |
| TCELL44:IMUX.IMUX.27.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_RVALID |
| TCELL44:IMUX.IMUX.28.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_UB_MISC_IN2 |
| TCELL44:IMUX.IMUX.29.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_UB_MISC_IN1 |
| TCELL44:IMUX.IMUX.30.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BLI2UB_SELF_REF_REQ |
| TCELL44:IMUX.IMUX.31.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BLI2UB_DRAM_POWER_OFF_REQ |
| TCELL44:IMUX.IMUX.32.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_DRCK |
| TCELL44:IMUX.IMUX.33.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_RESET |
| TCELL44:IMUX.IMUX.34.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_SHIFT |
| TCELL44:IMUX.IMUX.35.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_TCK |
| TCELL44:IMUX.IMUX.36.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_TMS |
| TCELL44:IMUX.IMUX.37.DELAY | LPDDRMC.IF_UBLAZE_FABRIC_BSCAN_EXT_UPDATE |
| TCELL44:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA14 |
| TCELL44:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA13 |
| TCELL44:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA11 |
| TCELL44:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA10 |
| TCELL44:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA8 |
| TCELL44:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA7 |
| TCELL44:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA5 |
| TCELL44:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA4 |
| TCELL44:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA2 |
| TCELL44:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA1 |
| TCELL45:OUT.3.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_DC_AWSIZE2 |
| TCELL45:OUT.4.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN3 |
| TCELL45:OUT.5.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN4 |
| TCELL45:OUT.6.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN5 |
| TCELL45:OUT.7.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN6 |
| TCELL45:OUT.8.TMIN | LPDDRMC.IF_UBLAZE_FABRIC_M_AXI_IC_ARLEN7 |
| TCELL45:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_MASTER_PD |
| TCELL45:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT5 |
| TCELL45:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT4 |
| TCELL45:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT3 |
| TCELL45:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT2 |
| TCELL45:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT1 |
| TCELL45:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_IOB2CLB_DFT0 |
| TCELL45:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_2 |
| TCELL45:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_1 |
| TCELL45:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_0_0 |
| TCELL45:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_2 |
| TCELL45:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_1 |
| TCELL45:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_PHY2CLB_LP_I_1_0 |
| TCELL45:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P2_RIU2CLB_VALID |
| TCELL45:OUT.24.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL45:OUT.25.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL45:OUT.26.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL45:OUT.27.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL45:OUT.28.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL45:OUT.29.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL45:OUT.30.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL45:OUT.31.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL45:IMUX.BYP.8.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT12 |
| TCELL45:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN2 |
| TCELL45:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN8 |
| TCELL45:IMUX.BYP.11.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT7 |
| TCELL45:IMUX.BYP.12.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_EDT_UPDT_B |
| TCELL45:IMUX.IMUX.0.DELAY | LPDDRMC.AXI0_WDATA_143_128_NIB2_CLB2RIU_WR_DATA0 |
| TCELL45:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR5 |
| TCELL45:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR2 |
| TCELL45:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN3 |
| TCELL45:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN0 |
| TCELL45:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT3 |
| TCELL45:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT0 |
| TCELL45:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN2 |
| TCELL45:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL5 |
| TCELL45:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL2 |
| TCELL45:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_ARADDR_32_NIB2_CLB2PHY_DLYCTL_EN_VTC |
| TCELL45:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL45:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL45:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL45:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL45:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL45:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR7 |
| TCELL45:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR6 |
| TCELL45:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR4 |
| TCELL45:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR3 |
| TCELL45:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR1 |
| TCELL45:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WSTRB_23_16_NIB2_CLB2RIU_ADDR0 |
| TCELL45:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN2 |
| TCELL45:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_AWADDR_25_22_NIB2_CLB2PHY_WREN1 |
| TCELL45:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT5 |
| TCELL45:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT4 |
| TCELL45:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT2 |
| TCELL45:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_AWADDR_31_26_NIB2_CLB2PHY_T_TXBIT1 |
| TCELL45:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_AWADDR_32_NIB2_CLB2PHY_FIFO_RDEN |
| TCELL45:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN3 |
| TCELL45:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN1 |
| TCELL45:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_ARADDR_25_22_NIB2_CLB2PHY_RDEN0 |
| TCELL45:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL4 |
| TCELL45:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL3 |
| TCELL45:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL1 |
| TCELL45:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_ARADDR_31_26_NIB2_CLB2PHY_IODELAY_SEL0 |
| TCELL45:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL45:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL45:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL45:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL45:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL45:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_ARID_7_0_NIB2_7_0_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL45:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL45:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL45:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL45:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL45:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_ARLEN_7_0_NIB2_15_8_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL45:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL46:OUT.3.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL46:OUT.4.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL46:OUT.5.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL46:OUT.6.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL46:OUT.7.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL46:OUT.8.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL46:OUT.9.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL46:OUT.10.TMIN | LPDDRMC.MAXI_DCAWADDR_15_0_NIB2_15_0_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL46:OUT.11.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL46:OUT.12.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL46:OUT.13.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL46:OUT.14.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL46:OUT.15.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL46:OUT.16.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL46:OUT.17.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL46:OUT.18.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL46:OUT.19.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL46:OUT.20.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL46:OUT.21.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL46:OUT.22.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL46:OUT.23.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL46:OUT.24.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL46:OUT.25.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL46:OUT.26.TMIN | LPDDRMC.MAXI_DCARADDR_15_0_NIB2_31_16_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL46:OUT.27.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL46:OUT.28.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL46:OUT.29.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL46:OUT.30.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL46:OUT.31.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL46:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2MC_DIV_CLK |
| TCELL46:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_FIFO_CLK |
| TCELL46:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_CTRL_CLK |
| TCELL46:IMUX.IMUX.0.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL46:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL46:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL46:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL46:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL46:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL46:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL46:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL46:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL46:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL46:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL46:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL46:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL46:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN3 |
| TCELL46:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN0 |
| TCELL46:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RST |
| TCELL46:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL46:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL46:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL46:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL46:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL46:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_ARUSER_10_0_NIB2_26_16_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL46:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL46:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL46:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL46:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL46:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL46:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_AWID_7_0_NIB2_34_27_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL46:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL46:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL46:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL46:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL46:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_AWLEN_7_0_NIB2_42_35_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL46:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL46:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL46:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL46:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL46:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL46:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL46:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_AWUSER_10_0_NIB2_53_43_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL46:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN5 |
| TCELL46:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN4 |
| TCELL46:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN2 |
| TCELL46:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_PAR_5_0_NIB2_CLB2PHY_KEEPER_EN1 |
| TCELL46:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_PAR_7_6_NIB2_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL46:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_PAR_7_6_NIB2_1_0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL46:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST5 |
| TCELL46:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST4 |
| TCELL47:OUT.3.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL47:OUT.4.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL47:OUT.5.TMIN | LPDDRMC.MAXI_DCAWLEN_7_0_NIB2_39_32_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL47:OUT.6.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL47:OUT.7.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL47:OUT.8.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL47:OUT.9.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL47:OUT.10.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL47:OUT.11.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL47:OUT.12.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL47:OUT.13.TMIN | LPDDRMC.MAXI_DCARLEN_7_0_NIB2_47_40_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL47:OUT.14.TMIN | LPDDRMC.MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL47:OUT.15.TMIN | LPDDRMC.MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL47:OUT.16.TMIN | LPDDRMC.MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL47:OUT.17.TMIN | LPDDRMC.MAXI_DCWSTRB_3_0_NIB2_51_48_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL47:OUT.18.TMIN | LPDDRMC.MAXI_DCAWBURST_1_0_NIB2_53_52_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL47:OUT.19.TMIN | LPDDRMC.MAXI_DCAWBURST_1_0_NIB2_53_52_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL47:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA15 |
| TCELL47:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA14 |
| TCELL47:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA13 |
| TCELL47:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA12 |
| TCELL47:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA11 |
| TCELL47:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA10 |
| TCELL47:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA9 |
| TCELL47:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA8 |
| TCELL47:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA7 |
| TCELL47:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA6 |
| TCELL47:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA5 |
| TCELL47:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA4 |
| TCELL47:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST1 |
| TCELL47:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST4 |
| TCELL47:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST1 |
| TCELL47:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL47:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL47:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE4 |
| TCELL47:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE1 |
| TCELL47:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE4 |
| TCELL47:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE1 |
| TCELL47:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC4 |
| TCELL47:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC1 |
| TCELL47:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD4 |
| TCELL47:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD1 |
| TCELL47:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_6 |
| TCELL47:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_0 |
| TCELL47:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST3 |
| TCELL47:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST2 |
| TCELL47:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_TXBIT_RST0 |
| TCELL47:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST5 |
| TCELL47:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST3 |
| TCELL47:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST2 |
| TCELL47:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_RXBIT_RST0 |
| TCELL47:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL47:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL47:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL47:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL47:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE5 |
| TCELL47:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE3 |
| TCELL47:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE2 |
| TCELL47:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IBUF_DISABLE0 |
| TCELL47:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE5 |
| TCELL47:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE3 |
| TCELL47:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE2 |
| TCELL47:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_CE0 |
| TCELL47:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC5 |
| TCELL47:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC3 |
| TCELL47:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC2 |
| TCELL47:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_INC0 |
| TCELL47:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD5 |
| TCELL47:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD3 |
| TCELL47:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD2 |
| TCELL47:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IODELAY_LD0 |
| TCELL47:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL47:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_4 |
| TCELL47:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_2 |
| TCELL47:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_1 |
| TCELL47:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_3 |
| TCELL48:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA3 |
| TCELL48:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA2 |
| TCELL48:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA1 |
| TCELL48:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_143_128_NIB2_RIU2CLB_RD_DATA0 |
| TCELL48:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_6 |
| TCELL48:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_4 |
| TCELL48:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_2 |
| TCELL48:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_0 |
| TCELL48:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_1 |
| TCELL48:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_3 |
| TCELL48:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_5 |
| TCELL48:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_191_184_NIB2_PHY2CLB_RD_DQ5_7 |
| TCELL48:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_6 |
| TCELL48:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_4 |
| TCELL48:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_2 |
| TCELL48:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_0 |
| TCELL48:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_1 |
| TCELL48:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_3 |
| TCELL48:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_5 |
| TCELL48:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_183_176_NIB2_PHY2CLB_RD_DQ4_7 |
| TCELL48:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_6 |
| TCELL48:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_4 |
| TCELL48:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_2 |
| TCELL48:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_0 |
| TCELL48:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_1 |
| TCELL48:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_3 |
| TCELL48:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_5 |
| TCELL48:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_175_168_NIB2_PHY2CLB_RD_DQ3_7 |
| TCELL48:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_6 |
| TCELL48:IMUX.CTRL.0 | LPDDRMC.AXIA0_CLK |
| TCELL48:IMUX.BYP.9.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT10 |
| TCELL48:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_CNTRL_CHNL_IN8 |
| TCELL48:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL48:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL48:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_6 |
| TCELL48:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_0 |
| TCELL48:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_5 |
| TCELL48:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_4 |
| TCELL48:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_1 |
| TCELL48:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_7 |
| TCELL48:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL48:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL48:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_2 |
| TCELL48:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_3 |
| TCELL48:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2RIU_NIBBLE_SEL |
| TCELL48:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_2 |
| TCELL48:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_3 |
| TCELL48:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_5 |
| TCELL48:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_WDATA_191_184_NIB2_CLB2PHY_WR_DQ5_7 |
| TCELL48:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL48:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL48:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL48:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL48:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_4 |
| TCELL48:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_2 |
| TCELL48:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_1 |
| TCELL48:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_3 |
| TCELL48:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_183_176_NIB2_CLB2PHY_WR_DQ4_7 |
| TCELL48:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_6 |
| TCELL48:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_2 |
| TCELL48:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_0 |
| TCELL48:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_3 |
| TCELL48:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_175_168_NIB2_CLB2PHY_WR_DQ3_5 |
| TCELL48:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL48:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL48:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL48:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL48:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_6 |
| TCELL48:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_4 |
| TCELL48:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_0 |
| TCELL48:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_1 |
| TCELL48:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_5 |
| TCELL48:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_167_160_NIB2_CLB2PHY_WR_DQ2_7 |
| TCELL48:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_6 |
| TCELL48:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_4 |
| TCELL48:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_0 |
| TCELL48:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_1 |
| TCELL48:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_5 |
| TCELL48:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_159_152_NIB2_CLB2PHY_WR_DQ1_7 |
| TCELL49:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_4 |
| TCELL49:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_2 |
| TCELL49:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_0 |
| TCELL49:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_1 |
| TCELL49:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_3 |
| TCELL49:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_5 |
| TCELL49:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_167_160_NIB2_PHY2CLB_RD_DQ2_7 |
| TCELL49:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_6 |
| TCELL49:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_4 |
| TCELL49:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_2 |
| TCELL49:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_0 |
| TCELL49:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_1 |
| TCELL49:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_3 |
| TCELL49:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_5 |
| TCELL49:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_159_152_NIB2_PHY2CLB_RD_DQ1_7 |
| TCELL49:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_6 |
| TCELL49:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_4 |
| TCELL49:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_2 |
| TCELL49:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_0 |
| TCELL49:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_1 |
| TCELL49:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_3 |
| TCELL49:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_5 |
| TCELL49:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_151_144_NIB2_PHY2CLB_RD_DQ0_7 |
| TCELL49:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_7 |
| TCELL49:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_5 |
| TCELL49:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_3 |
| TCELL49:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_1 |
| TCELL49:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_0 |
| TCELL49:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_2 |
| TCELL49:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2MC_DIV_CLK |
| TCELL49:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_CTRL_CLK |
| TCELL49:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_FIFO_CLK |
| TCELL49:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG5 |
| TCELL49:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CLK_N_EXT |
| TCELL49:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL49:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_2 |
| TCELL49:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_0_BIT2 |
| TCELL49:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL49:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_4 |
| TCELL49:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_1 |
| TCELL49:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_7 |
| TCELL49:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_3 |
| TCELL49:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_2 |
| TCELL49:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RST |
| TCELL49:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST3 |
| TCELL49:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST0 |
| TCELL49:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST3 |
| TCELL49:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST0 |
| TCELL49:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_5 |
| TCELL49:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL49:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL49:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL49:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL49:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_1 |
| TCELL49:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_PD_EN_1_0 |
| TCELL49:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL49:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL49:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P2_CLB2RIU_WR_EN |
| TCELL49:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_6 |
| TCELL49:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_2 |
| TCELL49:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_0 |
| TCELL49:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_3 |
| TCELL49:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_151_144_NIB2_CLB2PHY_WR_DQ0_5 |
| TCELL49:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_7 |
| TCELL49:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_5 |
| TCELL49:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_1 |
| TCELL49:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_0 |
| TCELL49:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_4 |
| TCELL49:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_WDATA_87_80_NIB1_CLB2PHY_WR_DQ0_6 |
| TCELL49:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST5 |
| TCELL49:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST4 |
| TCELL49:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST2 |
| TCELL49:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_TXBIT_RST1 |
| TCELL49:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST5 |
| TCELL49:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST4 |
| TCELL49:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST2 |
| TCELL49:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_RXBIT_RST1 |
| TCELL49:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL49:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_7 |
| TCELL49:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_3 |
| TCELL49:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_1 |
| TCELL50:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_4 |
| TCELL50:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_87_80_NIB1_PHY2CLB_RD_DQ0_6 |
| TCELL50:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_7 |
| TCELL50:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_5 |
| TCELL50:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_3 |
| TCELL50:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_1 |
| TCELL50:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_0 |
| TCELL50:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_2 |
| TCELL50:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_4 |
| TCELL50:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_95_88_NIB1_PHY2CLB_RD_DQ1_6 |
| TCELL50:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_7 |
| TCELL50:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_5 |
| TCELL50:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_3 |
| TCELL50:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_1 |
| TCELL50:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_0 |
| TCELL50:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_2 |
| TCELL50:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_4 |
| TCELL50:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_103_96_NIB1_PHY2CLB_RD_DQ2_6 |
| TCELL50:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_7 |
| TCELL50:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_5 |
| TCELL50:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_3 |
| TCELL50:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_1 |
| TCELL50:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_0 |
| TCELL50:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_2 |
| TCELL50:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_4 |
| TCELL50:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_111_104_NIB1_PHY2CLB_RD_DQ3_6 |
| TCELL50:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_7 |
| TCELL50:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_5 |
| TCELL50:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_3 |
| TCELL50:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_4 |
| TCELL50:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL50:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL50:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE3 |
| TCELL50:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE0 |
| TCELL50:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE3 |
| TCELL50:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE0 |
| TCELL50:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC3 |
| TCELL50:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC0 |
| TCELL50:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD3 |
| TCELL50:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD0 |
| TCELL50:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_5 |
| TCELL50:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_0 |
| TCELL50:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_6 |
| TCELL50:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL50:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_0 |
| TCELL50:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_2 |
| TCELL50:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WDATA_95_88_NIB1_CLB2PHY_WR_DQ1_6 |
| TCELL50:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL50:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL50:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL50:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE5 |
| TCELL50:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE4 |
| TCELL50:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE2 |
| TCELL50:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IBUF_DISABLE1 |
| TCELL50:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE5 |
| TCELL50:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE4 |
| TCELL50:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE2 |
| TCELL50:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CE1 |
| TCELL50:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC5 |
| TCELL50:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC4 |
| TCELL50:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC2 |
| TCELL50:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_INC1 |
| TCELL50:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD5 |
| TCELL50:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD4 |
| TCELL50:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD2 |
| TCELL50:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_LD1 |
| TCELL50:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL50:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_7 |
| TCELL50:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_3 |
| TCELL50:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_1 |
| TCELL50:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_2 |
| TCELL50:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_103_96_NIB1_CLB2PHY_WR_DQ2_4 |
| TCELL50:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL50:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL50:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL50:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL51:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_1 |
| TCELL51:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_0 |
| TCELL51:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_2 |
| TCELL51:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_4 |
| TCELL51:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_119_112_NIB1_PHY2CLB_RD_DQ4_6 |
| TCELL51:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_FIFO_EMPTY |
| TCELL51:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_FIXDLY_RDY |
| TCELL51:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_PHY_RDY |
| TCELL51:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_GT_STATUS |
| TCELL51:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_MASTER_PD |
| TCELL51:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL51:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL51:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL51:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL51:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL51:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL51:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL51:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL51:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL51:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL51:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL51:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL51:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL51:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL51:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL51:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL51:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_7 |
| TCELL51:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_5 |
| TCELL51:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_3 |
| TCELL51:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT6 |
| TCELL51:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL51:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL51:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL51:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL51:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL51:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL51:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL51:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL51:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_3 |
| TCELL51:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_2 |
| TCELL51:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_7 |
| TCELL51:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_1 |
| TCELL51:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_4 |
| TCELL51:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_5 |
| TCELL51:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_0 |
| TCELL51:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL51:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL51:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL51:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL51:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL51:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL51:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL51:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL51:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL51:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL51:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL51:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL51:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL51:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL51:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL51:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL51:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_7 |
| TCELL51:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_5 |
| TCELL51:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_1 |
| TCELL51:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_0 |
| TCELL51:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_4 |
| TCELL51:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_WDATA_111_104_NIB1_CLB2PHY_WR_DQ3_6 |
| TCELL51:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_5 |
| TCELL51:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_3 |
| TCELL51:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_0 |
| TCELL51:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_2 |
| TCELL51:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_119_112_NIB1_CLB2PHY_WR_DQ4_6 |
| TCELL51:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_7 |
| TCELL51:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_3 |
| TCELL51:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_1 |
| TCELL51:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_2 |
| TCELL51:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_4 |
| TCELL52:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_1 |
| TCELL52:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_0 |
| TCELL52:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_2 |
| TCELL52:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_4 |
| TCELL52:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_127_120_NIB1_PHY2CLB_RD_DQ5_6 |
| TCELL52:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL52:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL52:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL52:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL52:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL52:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL52:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL52:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL52:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL52:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL52:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL52:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL52:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL52:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL52:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL52:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL52:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL52:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL52:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL52:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL52:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL52:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL52:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL52:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL52:IMUX.BYP.6.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN8 |
| TCELL52:IMUX.BYP.9.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN0 |
| TCELL52:IMUX.BYP.10.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG2 |
| TCELL52:IMUX.BYP.13.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN9 |
| TCELL52:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL52:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL52:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL52:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL52:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL52:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL52:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL52:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL52:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL52:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL52:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL52:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL52:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL52:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL52:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_1 |
| TCELL52:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_127_120_NIB1_CLB2PHY_WR_DQ5_6 |
| TCELL52:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL52:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL52:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL52:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL52:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL52:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL52:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL52:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL52:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL52:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL52:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL52:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL52:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL52:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL52:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL52:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL52:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL52:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL52:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL52:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL52:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL52:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL52:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL52:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL52:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL52:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL52:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL52:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL52:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_2 |
| TCELL52:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_PD_EN_1_0 |
| TCELL52:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL53:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL53:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL53:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL53:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL53:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL53:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL53:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL53:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL53:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL53:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL53:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL53:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL53:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL53:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL53:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT5 |
| TCELL53:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT4 |
| TCELL53:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT3 |
| TCELL53:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT2 |
| TCELL53:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT1 |
| TCELL53:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_IOB2CLB_DFT0 |
| TCELL53:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_2 |
| TCELL53:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_1 |
| TCELL53:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_0_0 |
| TCELL53:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_2 |
| TCELL53:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_1 |
| TCELL53:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_PHY2CLB_LP_I_1_0 |
| TCELL53:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P1_RIU2CLB_VALID |
| TCELL53:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA15 |
| TCELL53:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA14 |
| TCELL53:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL53:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN5 |
| TCELL53:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN2 |
| TCELL53:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2RIU_WR_EN |
| TCELL53:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA14 |
| TCELL53:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA11 |
| TCELL53:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA8 |
| TCELL53:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA5 |
| TCELL53:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA2 |
| TCELL53:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR7 |
| TCELL53:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR4 |
| TCELL53:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR1 |
| TCELL53:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN2 |
| TCELL53:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT5 |
| TCELL53:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT2 |
| TCELL53:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL53:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL53:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL53:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL53:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN4 |
| TCELL53:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN3 |
| TCELL53:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN1 |
| TCELL53:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2PHY_KEEPER_EN0 |
| TCELL53:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P1_CLB2RIU_NIBBLE_SEL |
| TCELL53:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA15 |
| TCELL53:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA13 |
| TCELL53:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA12 |
| TCELL53:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA10 |
| TCELL53:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA9 |
| TCELL53:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA7 |
| TCELL53:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA6 |
| TCELL53:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA4 |
| TCELL53:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA3 |
| TCELL53:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA1 |
| TCELL53:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_WDATA_79_64_NIB1_CLB2RIU_WR_DATA0 |
| TCELL53:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR6 |
| TCELL53:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR5 |
| TCELL53:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR3 |
| TCELL53:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR2 |
| TCELL53:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WSTRB_15_8_NIB1_CLB2RIU_ADDR0 |
| TCELL53:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN3 |
| TCELL53:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN1 |
| TCELL53:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_AWADDR_14_11_NIB1_CLB2PHY_WREN0 |
| TCELL53:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT4 |
| TCELL53:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT3 |
| TCELL53:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT1 |
| TCELL53:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_AWADDR_20_15_NIB1_CLB2PHY_T_TXBIT0 |
| TCELL54:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA13 |
| TCELL54:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA12 |
| TCELL54:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA11 |
| TCELL54:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA10 |
| TCELL54:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA9 |
| TCELL54:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA8 |
| TCELL54:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA7 |
| TCELL54:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA6 |
| TCELL54:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA5 |
| TCELL54:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA4 |
| TCELL54:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA3 |
| TCELL54:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA2 |
| TCELL54:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA1 |
| TCELL54:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_79_64_NIB1_RIU2CLB_RD_DATA0 |
| TCELL54:OUT.17.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARREADY |
| TCELL54:OUT.18.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWREADY |
| TCELL54:OUT.19.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WREADY |
| TCELL54:OUT.20.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RVALID |
| TCELL54:OUT.21.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RLAST |
| TCELL54:OUT.22.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID7 |
| TCELL54:OUT.23.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID6 |
| TCELL54:OUT.24.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID5 |
| TCELL54:OUT.25.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID4 |
| TCELL54:OUT.26.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID3 |
| TCELL54:OUT.27.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID2 |
| TCELL54:OUT.28.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID1 |
| TCELL54:OUT.29.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RID0 |
| TCELL54:OUT.30.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RRESP1 |
| TCELL54:OUT.31.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RRESP0 |
| TCELL54:IMUX.BYP.10.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT10 |
| TCELL54:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN2 |
| TCELL54:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL5 |
| TCELL54:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL2 |
| TCELL54:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_ARADDR_21_NIB1_CLB2PHY_DLYCTL_EN_VTC |
| TCELL54:IMUX.IMUX.5.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE1 |
| TCELL54:IMUX.IMUX.6.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARBURST0 |
| TCELL54:IMUX.IMUX.7.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT1 |
| TCELL54:IMUX.IMUX.8.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARADDR_PAR0 |
| TCELL54:IMUX.IMUX.9.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE1 |
| TCELL54:IMUX.IMUX.10.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWBURST0 |
| TCELL54:IMUX.IMUX.11.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT1 |
| TCELL54:IMUX.IMUX.12.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWADDR_PAR0 |
| TCELL54:IMUX.IMUX.13.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WPOISON |
| TCELL54:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA15 |
| TCELL54:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA12 |
| TCELL54:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_AWADDR_21_NIB1_CLB2PHY_FIFO_RDEN |
| TCELL54:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN3 |
| TCELL54:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN1 |
| TCELL54:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_ARADDR_14_11_NIB1_CLB2PHY_RDEN0 |
| TCELL54:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL4 |
| TCELL54:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL3 |
| TCELL54:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL1 |
| TCELL54:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_ARADDR_20_15_NIB1_CLB2PHY_IODELAY_SEL0 |
| TCELL54:IMUX.IMUX.24.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARVALID |
| TCELL54:IMUX.IMUX.25.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE2 |
| TCELL54:IMUX.IMUX.26.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARSIZE0 |
| TCELL54:IMUX.IMUX.27.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARBURST1 |
| TCELL54:IMUX.IMUX.28.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARLOCK |
| TCELL54:IMUX.IMUX.29.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT2 |
| TCELL54:IMUX.IMUX.30.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARPROT0 |
| TCELL54:IMUX.IMUX.31.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_ARADDR_PAR1 |
| TCELL54:IMUX.IMUX.32.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWVALID |
| TCELL54:IMUX.IMUX.33.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE2 |
| TCELL54:IMUX.IMUX.34.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWSIZE0 |
| TCELL54:IMUX.IMUX.35.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWBURST1 |
| TCELL54:IMUX.IMUX.36.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWLOCK |
| TCELL54:IMUX.IMUX.37.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT2 |
| TCELL54:IMUX.IMUX.38.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWPROT0 |
| TCELL54:IMUX.IMUX.39.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_AWADDR_PAR1 |
| TCELL54:IMUX.IMUX.40.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WVALID |
| TCELL54:IMUX.IMUX.41.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_WLAST |
| TCELL54:IMUX.IMUX.42.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RREADY |
| TCELL54:IMUX.IMUX.43.DELAY | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BREADY |
| TCELL54:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA14 |
| TCELL54:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA13 |
| TCELL54:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA11 |
| TCELL54:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA10 |
| TCELL55:OUT.3.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RPOISON |
| TCELL55:OUT.4.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR7 |
| TCELL55:OUT.5.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR6 |
| TCELL55:OUT.6.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR5 |
| TCELL55:OUT.7.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR4 |
| TCELL55:OUT.8.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR3 |
| TCELL55:OUT.9.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR2 |
| TCELL55:OUT.10.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR1 |
| TCELL55:OUT.11.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_RDATA_PAR0 |
| TCELL55:OUT.12.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BVALID |
| TCELL55:OUT.13.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID7 |
| TCELL55:OUT.14.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID6 |
| TCELL55:OUT.15.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID5 |
| TCELL55:OUT.16.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID4 |
| TCELL55:OUT.17.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID3 |
| TCELL55:OUT.18.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID2 |
| TCELL55:OUT.19.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID1 |
| TCELL55:OUT.20.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BID0 |
| TCELL55:OUT.21.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BRESP1 |
| TCELL55:OUT.22.TMIN | LPDDRMC.IF_LPDDRMC_RMUX_AXI_DC_TOP_P0_BRESP0 |
| TCELL55:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_FIFO_EMPTY |
| TCELL55:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_FIXDLY_RDY |
| TCELL55:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_PHY_RDY |
| TCELL55:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_GT_STATUS |
| TCELL55:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_MASTER_PD |
| TCELL55:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT53 |
| TCELL55:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT52 |
| TCELL55:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT51 |
| TCELL55:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT50 |
| TCELL55:IMUX.BYP.7.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_EN_B |
| TCELL55:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN7 |
| TCELL55:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA7 |
| TCELL55:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA4 |
| TCELL55:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA1 |
| TCELL55:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR6 |
| TCELL55:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR3 |
| TCELL55:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR0 |
| TCELL55:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST4 |
| TCELL55:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST1 |
| TCELL55:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST4 |
| TCELL55:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST1 |
| TCELL55:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS4 |
| TCELL55:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS1 |
| TCELL55:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE4 |
| TCELL55:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE1 |
| TCELL55:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE4 |
| TCELL55:IMUX.IMUX.16.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA9 |
| TCELL55:IMUX.IMUX.17.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA8 |
| TCELL55:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA6 |
| TCELL55:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA5 |
| TCELL55:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA3 |
| TCELL55:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA2 |
| TCELL55:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_15_0_NIB0_CLB2RIU_WR_DATA0 |
| TCELL55:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR7 |
| TCELL55:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR5 |
| TCELL55:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR4 |
| TCELL55:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR2 |
| TCELL55:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WSTRB_7_0_NIB0_CLB2RIU_ADDR1 |
| TCELL55:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RST |
| TCELL55:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST5 |
| TCELL55:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST3 |
| TCELL55:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST2 |
| TCELL55:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_TXBIT_RST0 |
| TCELL55:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST5 |
| TCELL55:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST3 |
| TCELL55:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST2 |
| TCELL55:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_RXBIT_RST0 |
| TCELL55:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS5 |
| TCELL55:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS3 |
| TCELL55:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS2 |
| TCELL55:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_DYNAMIC_DCI_TS0 |
| TCELL55:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE5 |
| TCELL55:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE3 |
| TCELL55:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE2 |
| TCELL55:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IBUF_DISABLE0 |
| TCELL55:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE5 |
| TCELL55:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE3 |
| TCELL55:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE2 |
| TCELL56:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT49 |
| TCELL56:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT48 |
| TCELL56:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT47 |
| TCELL56:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT46 |
| TCELL56:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT45 |
| TCELL56:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT44 |
| TCELL56:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT43 |
| TCELL56:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT42 |
| TCELL56:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT41 |
| TCELL56:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT40 |
| TCELL56:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT39 |
| TCELL56:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT38 |
| TCELL56:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT37 |
| TCELL56:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT36 |
| TCELL56:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT35 |
| TCELL56:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT34 |
| TCELL56:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT33 |
| TCELL56:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT32 |
| TCELL56:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT31 |
| TCELL56:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT30 |
| TCELL56:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT29 |
| TCELL56:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT28 |
| TCELL56:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT27 |
| TCELL56:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT26 |
| TCELL56:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT25 |
| TCELL56:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT24 |
| TCELL56:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT23 |
| TCELL56:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT22 |
| TCELL56:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT21 |
| TCELL56:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT20 |
| TCELL56:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT19 |
| TCELL56:IMUX.CTRL.0 | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2MC_DIV_CLK |
| TCELL56:IMUX.CTRL.1 | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_CTRL_CLK |
| TCELL56:IMUX.CTRL.2 | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_FIFO_CLK |
| TCELL56:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC5 |
| TCELL56:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC2 |
| TCELL56:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD5 |
| TCELL56:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD2 |
| TCELL56:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN53 |
| TCELL56:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN50 |
| TCELL56:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN47 |
| TCELL56:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN44 |
| TCELL56:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN41 |
| TCELL56:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN38 |
| TCELL56:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN35 |
| TCELL56:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN32 |
| TCELL56:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN29 |
| TCELL56:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN26 |
| TCELL56:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN23 |
| TCELL56:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE1 |
| TCELL56:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CE0 |
| TCELL56:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC4 |
| TCELL56:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC3 |
| TCELL56:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC1 |
| TCELL56:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_INC0 |
| TCELL56:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD4 |
| TCELL56:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD3 |
| TCELL56:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD1 |
| TCELL56:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_LD0 |
| TCELL56:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN52 |
| TCELL56:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN51 |
| TCELL56:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN49 |
| TCELL56:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN48 |
| TCELL56:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN46 |
| TCELL56:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN45 |
| TCELL56:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN43 |
| TCELL56:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN42 |
| TCELL56:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN40 |
| TCELL56:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN39 |
| TCELL56:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN37 |
| TCELL56:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN36 |
| TCELL56:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN34 |
| TCELL56:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN33 |
| TCELL56:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN31 |
| TCELL56:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN30 |
| TCELL56:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN28 |
| TCELL56:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN27 |
| TCELL56:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN25 |
| TCELL56:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN24 |
| TCELL56:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN22 |
| TCELL56:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN21 |
| TCELL57:OUT.0.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT18 |
| TCELL57:OUT.1.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT17 |
| TCELL57:OUT.2.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT16 |
| TCELL57:OUT.3.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT15 |
| TCELL57:OUT.4.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT14 |
| TCELL57:OUT.5.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT13 |
| TCELL57:OUT.6.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT12 |
| TCELL57:OUT.7.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT11 |
| TCELL57:OUT.8.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT10 |
| TCELL57:OUT.9.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT9 |
| TCELL57:OUT.10.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT8 |
| TCELL57:OUT.11.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT7 |
| TCELL57:OUT.12.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT6 |
| TCELL57:OUT.13.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT5 |
| TCELL57:OUT.14.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT4 |
| TCELL57:OUT.15.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT3 |
| TCELL57:OUT.16.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT2 |
| TCELL57:OUT.17.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT1 |
| TCELL57:OUT.18.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_IODELAY_CNTVALUEOUT0 |
| TCELL57:OUT.19.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT5 |
| TCELL57:OUT.20.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT4 |
| TCELL57:OUT.21.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT3 |
| TCELL57:OUT.22.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT2 |
| TCELL57:OUT.23.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT1 |
| TCELL57:OUT.24.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_IOB2CLB_DFT0 |
| TCELL57:OUT.25.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_2 |
| TCELL57:OUT.26.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_1 |
| TCELL57:OUT.27.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_0_0 |
| TCELL57:OUT.28.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_2 |
| TCELL57:OUT.29.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_1 |
| TCELL57:OUT.30.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_PHY2CLB_LP_I_1_0 |
| TCELL57:OUT.31.TMIN | LPDDRMC.IF_HSM_CLB2PHY_P0_RIU2CLB_VALID |
| TCELL57:IMUX.BYP.7.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_IN1 |
| TCELL57:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG10 |
| TCELL57:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN20 |
| TCELL57:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN17 |
| TCELL57:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN14 |
| TCELL57:IMUX.IMUX.3.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN11 |
| TCELL57:IMUX.IMUX.4.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN8 |
| TCELL57:IMUX.IMUX.5.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN5 |
| TCELL57:IMUX.IMUX.6.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN2 |
| TCELL57:IMUX.IMUX.7.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC5 |
| TCELL57:IMUX.IMUX.8.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC2 |
| TCELL57:IMUX.IMUX.9.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC5 |
| TCELL57:IMUX.IMUX.10.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC2 |
| TCELL57:IMUX.IMUX.11.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN2 |
| TCELL57:IMUX.IMUX.12.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_2 |
| TCELL57:IMUX.IMUX.13.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_2 |
| TCELL57:IMUX.IMUX.14.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_2 |
| TCELL57:IMUX.IMUX.15.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_2 |
| TCELL57:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN19 |
| TCELL57:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN18 |
| TCELL57:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN16 |
| TCELL57:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN15 |
| TCELL57:IMUX.IMUX.20.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN13 |
| TCELL57:IMUX.IMUX.21.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN12 |
| TCELL57:IMUX.IMUX.22.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN10 |
| TCELL57:IMUX.IMUX.23.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN9 |
| TCELL57:IMUX.IMUX.24.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN7 |
| TCELL57:IMUX.IMUX.25.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN6 |
| TCELL57:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN4 |
| TCELL57:IMUX.IMUX.27.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN3 |
| TCELL57:IMUX.IMUX.28.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN1 |
| TCELL57:IMUX.IMUX.29.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IODELAY_CNTVALUEIN0 |
| TCELL57:IMUX.IMUX.30.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC4 |
| TCELL57:IMUX.IMUX.31.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC3 |
| TCELL57:IMUX.IMUX.32.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC1 |
| TCELL57:IMUX.IMUX.33.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_IDELAY_EN_VTC0 |
| TCELL57:IMUX.IMUX.34.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC4 |
| TCELL57:IMUX.IMUX.35.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC3 |
| TCELL57:IMUX.IMUX.36.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC1 |
| TCELL57:IMUX.IMUX.37.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_ODELAY_EN_VTC0 |
| TCELL57:IMUX.IMUX.38.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN1 |
| TCELL57:IMUX.IMUX.39.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_RX_DIS_OR_TERM_EN0 |
| TCELL57:IMUX.IMUX.40.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_1 |
| TCELL57:IMUX.IMUX.41.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_T_OR_PD_EN_0_0 |
| TCELL57:IMUX.IMUX.42.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_1 |
| TCELL57:IMUX.IMUX.43.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_PD_EN_1_0 |
| TCELL57:IMUX.IMUX.44.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_1 |
| TCELL57:IMUX.IMUX.45.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_0_0 |
| TCELL57:IMUX.IMUX.46.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_1 |
| TCELL57:IMUX.IMUX.47.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_LP_TX_O_OR_PU_EN_1_0 |
| TCELL58:OUT.0.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA15 |
| TCELL58:OUT.1.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA14 |
| TCELL58:OUT.2.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA13 |
| TCELL58:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA12 |
| TCELL58:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA11 |
| TCELL58:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA10 |
| TCELL58:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA9 |
| TCELL58:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA8 |
| TCELL58:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA7 |
| TCELL58:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA6 |
| TCELL58:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA5 |
| TCELL58:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA4 |
| TCELL58:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA3 |
| TCELL58:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA2 |
| TCELL58:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA1 |
| TCELL58:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_15_0_NIB0_RIU2CLB_RD_DATA0 |
| TCELL58:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_6 |
| TCELL58:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_4 |
| TCELL58:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_2 |
| TCELL58:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_0 |
| TCELL58:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_1 |
| TCELL58:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_3 |
| TCELL58:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_5 |
| TCELL58:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_63_56_NIB0_PHY2CLB_RD_DQ5_7 |
| TCELL58:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_6 |
| TCELL58:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_4 |
| TCELL58:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_2 |
| TCELL58:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_0 |
| TCELL58:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_1 |
| TCELL58:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_3 |
| TCELL58:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_5 |
| TCELL58:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_55_48_NIB0_PHY2CLB_RD_DQ4_7 |
| TCELL58:IMUX.BYP.7.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_MASK_IN_EXT1 |
| TCELL58:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_CSSD_TRIG3 |
| TCELL58:IMUX.IMUX.0.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN5 |
| TCELL58:IMUX.IMUX.1.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN2 |
| TCELL58:IMUX.IMUX.2.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2RIU_WR_EN |
| TCELL58:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_2 |
| TCELL58:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_3 |
| TCELL58:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN3 |
| TCELL58:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN0 |
| TCELL58:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT3 |
| TCELL58:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT0 |
| TCELL58:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN2 |
| TCELL58:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL5 |
| TCELL58:IMUX.IMUX.11.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL2 |
| TCELL58:IMUX.IMUX.12.DELAY | LPDDRMC.AXI0_ARADDR_10_NIB0_CLB2PHY_DLYCTL_EN_VTC |
| TCELL58:IMUX.IMUX.13.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_2 |
| TCELL58:IMUX.IMUX.14.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_3 |
| TCELL58:IMUX.IMUX.15.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_6 |
| TCELL58:IMUX.IMUX.16.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN4 |
| TCELL58:IMUX.IMUX.17.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN3 |
| TCELL58:IMUX.IMUX.18.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN1 |
| TCELL58:IMUX.IMUX.19.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2PHY_KEEPER_EN0 |
| TCELL58:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_6 |
| TCELL58:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_4 |
| TCELL58:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_0 |
| TCELL58:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_1 |
| TCELL58:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_5 |
| TCELL58:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_63_56_NIB0_CLB2PHY_WR_DQ5_7 |
| TCELL58:IMUX.IMUX.26.DELAY | LPDDRMC.AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN2 |
| TCELL58:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_AWADDR_3_0_NIB0_CLB2PHY_WREN1 |
| TCELL58:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT5 |
| TCELL58:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT4 |
| TCELL58:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT2 |
| TCELL58:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_AWADDR_9_4_NIB0_CLB2PHY_T_TXBIT1 |
| TCELL58:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_AWADDR_10_NIB0_CLB2PHY_FIFO_RDEN |
| TCELL58:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN3 |
| TCELL58:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN1 |
| TCELL58:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_ARADDR_3_0_NIB0_CLB2PHY_RDEN0 |
| TCELL58:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL4 |
| TCELL58:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL3 |
| TCELL58:IMUX.IMUX.38.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL1 |
| TCELL58:IMUX.IMUX.39.DELAY | LPDDRMC.AXI0_ARADDR_9_4_NIB0_CLB2PHY_IODELAY_SEL0 |
| TCELL58:IMUX.IMUX.40.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_6 |
| TCELL58:IMUX.IMUX.41.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_4 |
| TCELL58:IMUX.IMUX.42.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_0 |
| TCELL58:IMUX.IMUX.43.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_1 |
| TCELL58:IMUX.IMUX.44.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_5 |
| TCELL58:IMUX.IMUX.45.DELAY | LPDDRMC.AXI0_WDATA_55_48_NIB0_CLB2PHY_WR_DQ4_7 |
| TCELL58:IMUX.IMUX.46.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_4 |
| TCELL58:IMUX.IMUX.47.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_2 |
| TCELL59:OUT.0.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_6 |
| TCELL59:OUT.1.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_4 |
| TCELL59:OUT.2.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_2 |
| TCELL59:OUT.3.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_0 |
| TCELL59:OUT.4.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_1 |
| TCELL59:OUT.5.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_3 |
| TCELL59:OUT.6.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_5 |
| TCELL59:OUT.7.TMIN | LPDDRMC.AXI0_RDATA_47_40_NIB0_PHY2CLB_RD_DQ3_7 |
| TCELL59:OUT.8.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_6 |
| TCELL59:OUT.9.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_4 |
| TCELL59:OUT.10.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_2 |
| TCELL59:OUT.11.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_0 |
| TCELL59:OUT.12.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_1 |
| TCELL59:OUT.13.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_3 |
| TCELL59:OUT.14.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_5 |
| TCELL59:OUT.15.TMIN | LPDDRMC.AXI0_RDATA_39_32_NIB0_PHY2CLB_RD_DQ2_7 |
| TCELL59:OUT.16.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_6 |
| TCELL59:OUT.17.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_4 |
| TCELL59:OUT.18.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_2 |
| TCELL59:OUT.19.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_0 |
| TCELL59:OUT.20.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_1 |
| TCELL59:OUT.21.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_3 |
| TCELL59:OUT.22.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_5 |
| TCELL59:OUT.23.TMIN | LPDDRMC.AXI0_RDATA_31_24_NIB0_PHY2CLB_RD_DQ1_7 |
| TCELL59:OUT.24.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_6 |
| TCELL59:OUT.25.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_4 |
| TCELL59:OUT.26.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_2 |
| TCELL59:OUT.27.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_0 |
| TCELL59:OUT.28.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_1 |
| TCELL59:OUT.29.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_3 |
| TCELL59:OUT.30.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_5 |
| TCELL59:OUT.31.TMIN | LPDDRMC.AXI0_RDATA_23_16_NIB0_PHY2CLB_RD_DQ0_7 |
| TCELL59:IMUX.BYP.7.DELAY | LPDDRMC.IF_DMC_FABRIC_SCAN_CHNL_IN_EXT2 |
| TCELL59:IMUX.BYP.8.DELAY | LPDDRMC.IF_XPIO_DFX_DFXCNTRL_DMC_OABUT_CLB2PHY_SCAN_COMP_IN0 |
| TCELL59:IMUX.IMUX.1.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_0 |
| TCELL59:IMUX.IMUX.2.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_5 |
| TCELL59:IMUX.IMUX.3.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_4 |
| TCELL59:IMUX.IMUX.4.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_1 |
| TCELL59:IMUX.IMUX.5.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_7 |
| TCELL59:IMUX.IMUX.6.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_4 |
| TCELL59:IMUX.IMUX.7.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_1 |
| TCELL59:IMUX.IMUX.8.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_7 |
| TCELL59:IMUX.IMUX.9.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_2 |
| TCELL59:IMUX.IMUX.10.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_3 |
| TCELL59:IMUX.IMUX.18.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_1 |
| TCELL59:IMUX.IMUX.19.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_3 |
| TCELL59:IMUX.IMUX.20.DELAY | LPDDRMC.AXI0_WDATA_47_40_NIB0_CLB2PHY_WR_DQ3_7 |
| TCELL59:IMUX.IMUX.21.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_6 |
| TCELL59:IMUX.IMUX.22.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_2 |
| TCELL59:IMUX.IMUX.23.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_0 |
| TCELL59:IMUX.IMUX.24.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_3 |
| TCELL59:IMUX.IMUX.25.DELAY | LPDDRMC.AXI0_WDATA_39_32_NIB0_CLB2PHY_WR_DQ2_5 |
| TCELL59:IMUX.IMUX.26.DELAY | LPDDRMC.IF_HSM_CLB2PHY_P0_CLB2RIU_NIBBLE_SEL |
| TCELL59:IMUX.IMUX.27.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_6 |
| TCELL59:IMUX.IMUX.28.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_2 |
| TCELL59:IMUX.IMUX.29.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_0 |
| TCELL59:IMUX.IMUX.30.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_3 |
| TCELL59:IMUX.IMUX.31.DELAY | LPDDRMC.AXI0_WDATA_31_24_NIB0_CLB2PHY_WR_DQ1_5 |
| TCELL59:IMUX.IMUX.32.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_6 |
| TCELL59:IMUX.IMUX.33.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_4 |
| TCELL59:IMUX.IMUX.34.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_0 |
| TCELL59:IMUX.IMUX.35.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_1 |
| TCELL59:IMUX.IMUX.36.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_5 |
| TCELL59:IMUX.IMUX.37.DELAY | LPDDRMC.AXI0_WDATA_23_16_NIB0_CLB2PHY_WR_DQ0_7 |