Delay-locked loop
Tile DLL_S
Cells: 3
Switchbox DLL_INT
| Bits | Destination | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][6] | MAIN[5][4] | MAIN[7][6] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][4] | MAIN[5][6] | MAIN[0][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[4][13] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |
Bitstream
Tile DLLP_S
Cells: 4
Switchbox DLL_INT
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][6] | MAIN[5][4] | MAIN[7][6] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[10][6] | MAIN[9][6] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | DLLS.OUT_DLL_CLK2X |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][4] | MAIN[5][6] | MAIN[0][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[12][6] | MAIN[13][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| ENABLE | !MAIN[15][12] |
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[12][1] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |
Bitstream
Tile DLLS_S
Cells: 3
Switchbox DLL_INT
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][6] | MAIN[5][4] | MAIN[7][6] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[10][6] | MAIN[9][6] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[6][4] | MAIN[5][6] | MAIN[0][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[12][6] | MAIN[13][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.OUT_DLL_CLK2X |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| ENABLE | !MAIN[15][12] |
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[12][1] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |
Bitstream
Tile DLL_N
Cells: 3
Switchbox DLL_INT
| Bits | Destination | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[7][6] | MAIN[6][6] | MAIN[5][4] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[0][6] | MAIN[6][4] | MAIN[5][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[4][13] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |
Bitstream
Tile DLLP_N
Cells: 4
Switchbox DLL_INT
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[7][6] | MAIN[6][6] | MAIN[5][4] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[10][6] | MAIN[9][6] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | DLLS.OUT_DLL_CLK2X |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[0][6] | MAIN[6][4] | MAIN[5][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[12][6] | MAIN[13][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| ENABLE | !MAIN[15][12] |
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[12][1] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |
Bitstream
Tile DLLS_N
Cells: 3
Switchbox DLL_INT
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[7][6] | MAIN[6][6] | MAIN[5][4] | MAIN[4][6] | MAIN[3][4] | MAIN[2][6] | MAIN[1][4] | MAIN[10][6] | MAIN[9][6] | MAIN[7][3] | MAIN[4][3] | MAIN[9][3] | MAIN[8][3] | MAIN[0][3] | CELL.IMUX_DLL_CLKIN |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MAIN[0][6] | MAIN[6][4] | MAIN[5][6] | MAIN[4][4] | MAIN[3][6] | MAIN[2][4] | MAIN[1][6] | MAIN[12][6] | MAIN[13][6] | MAIN[6][3] | MAIN[3][3] | MAIN[5][3] | MAIN[2][3] | MAIN[1][3] | CELL.IMUX_DLL_CLKFB |
| Source | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | CLK.OUT_CLKPAD[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | CLK.OUT_CLKPAD[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | CLK.OUT_IOFB[1] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[0] |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[1] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[0] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[0] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.GCLK_LEAF[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[0] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL.OUT_DLL_CLK2X |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[4] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[0] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[5] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[0] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[11] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H0[1] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[10] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H1[1] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[9] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[1] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[8] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H3[1] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[7] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H4[1] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL.LV[6] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H5[1] |
| Bits | Destination | ||||||
|---|---|---|---|---|---|---|---|
| MAIN[4][0] | MAIN[1][0] | MAIN[2][0] | MAIN[6][0] | MAIN[6][1] | MAIN[3][1] | MAIN[2][1] | CELL.IMUX_DLL_RST |
| Source | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | CELL.PULLUP |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[2] |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[2] |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[2] |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[2] |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[2] |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[2] |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | CELL_W.HEX_H0[3] |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 | CELL_W.HEX_H1[3] |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | CELL_W.HEX_H2[3] |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | CELL_W.HEX_H3[3] |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | CELL_W.HEX_H4[3] |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | CELL_W.HEX_H5[3] |
Bels DLL
| Pin | Direction | DLL |
|---|---|---|
| CLKIN | in | CELL.IMUX_DLL_CLKIN |
| CLKFB | in | CELL.IMUX_DLL_CLKFB |
| RST | in | CELL.IMUX_DLL_RST invert by MAIN[15][0] |
| CLK0 | out | CELL.OUT_DLL_CLK0 |
| CLK90 | out | CELL.OUT_DLL_CLK90 |
| CLK180 | out | CELL.OUT_DLL_CLK180 |
| CLK270 | out | CELL.OUT_DLL_CLK270 |
| CLK2X | out | CELL.OUT_DLL_CLK2X |
| CLK2X90 | out | CELL.OUT_DLL_CLK2X90 |
| CLKDV | out | CELL.OUT_DLL_CLKDV |
| LOCKED | out | CELL.OUT_DLL_LOCKED |
| Attribute | DLL |
|---|---|
| ENABLE | !MAIN[15][12] |
| CLK_FEEDBACK_2X | MAIN[16][10] |
| DUTY_CYCLE_CORRECTION bit 0 | MAIN[18][0] |
| DUTY_CYCLE_CORRECTION bit 1 | MAIN[18][1] |
| DUTY_CYCLE_CORRECTION bit 2 | MAIN[18][2] |
| DUTY_CYCLE_CORRECTION bit 3 | MAIN[18][3] |
| CLKIN_PAD | MAIN[8][4] |
| CLKFB_PAD | MAIN[8][6] |
| HIGH_FREQUENCY | MAIN[16][0] |
| CLKDV_COUNT_MAX bit 0 | MAIN[18][4] |
| CLKDV_COUNT_MAX bit 1 | MAIN[18][5] |
| CLKDV_COUNT_MAX bit 2 | MAIN[18][6] |
| CLKDV_COUNT_MAX bit 3 | MAIN[18][7] |
| CLKDV_COUNT_FALL bit 0 | MAIN[18][8] |
| CLKDV_COUNT_FALL bit 1 | MAIN[18][9] |
| CLKDV_COUNT_FALL bit 2 | MAIN[18][10] |
| CLKDV_COUNT_FALL bit 3 | MAIN[18][11] |
| CLKDV_COUNT_FALL_2 bit 0 | MAIN[18][12] |
| CLKDV_COUNT_FALL_2 bit 1 | MAIN[18][13] |
| CLKDV_COUNT_FALL_2 bit 2 | MAIN[18][14] |
| CLKDV_COUNT_FALL_2 bit 3 | MAIN[18][15] |
| CLKDV_PHASE_RISE bit 0 | MAIN[16][1] |
| CLKDV_PHASE_RISE bit 1 | MAIN[16][2] |
| CLKDV_PHASE_FALL bit 0 | MAIN[16][3] |
| CLKDV_PHASE_FALL bit 1 | MAIN[16][4] |
| CLKDV_MODE | [enum: DLL_CLKDV_MODE] |
| FACTORY_JF1 bit 0 | MAIN[17][8] |
| FACTORY_JF1 bit 1 | MAIN[17][9] |
| FACTORY_JF1 bit 2 | MAIN[17][10] |
| FACTORY_JF1 bit 3 | MAIN[17][11] |
| FACTORY_JF1 bit 4 | MAIN[17][12] |
| FACTORY_JF1 bit 5 | MAIN[17][13] |
| FACTORY_JF1 bit 6 | MAIN[17][14] |
| FACTORY_JF1 bit 7 | MAIN[17][15] |
| FACTORY_JF2 bit 0 | MAIN[17][0] |
| FACTORY_JF2 bit 1 | MAIN[17][1] |
| FACTORY_JF2 bit 2 | MAIN[17][2] |
| FACTORY_JF2 bit 3 | MAIN[17][3] |
| FACTORY_JF2 bit 4 | MAIN[17][4] |
| FACTORY_JF2 bit 5 | MAIN[17][5] |
| FACTORY_JF2 bit 6 | MAIN[17][6] |
| FACTORY_JF2 bit 7 | MAIN[17][7] |
| CFG_O_14 bit 0 | MAIN[16][14] |
| LVL1_MUX_20 bit 0 | MAIN[15][6] |
| LVL1_MUX_21 bit 0 | MAIN[14][6] |
| LVL1_MUX_22 bit 0 | MAIN[15][4] |
| LVL1_MUX_23 bit 0 | MAIN[14][4] |
| LVL1_MUX_24 bit 0 | MAIN[11][6] |
| TESTDLL bit 0 | MAIN[7][1] |
| TESTDLL bit 1 | MAIN[8][1] |
| TESTDLL bit 2 | MAIN[9][1] |
| TESTDLL bit 3 | MAIN[11][1] |
| TESTDLL bit 4 | MAIN[13][1] |
| TESTDLL bit 5 | MAIN[14][1] |
| TESTZD2OSC | MAIN[12][1] |
| TEST_OSC | [enum: DLL_TEST_OSC] |
| DLL.CLKDV_MODE | MAIN[16][15] |
|---|---|
| HALF | 0 |
| INT | 1 |
| DLL.TEST_OSC | MAIN[16][6] | MAIN[16][5] |
|---|---|---|
| _90 | 0 | 0 |
| _180 | 0 | 1 |
| _270 | 1 | 0 |
| _360 | 1 | 1 |
Bel wires
| Wire | Pins |
|---|---|
| CELL.IMUX_DLL_CLKIN | DLL.CLKIN |
| CELL.IMUX_DLL_CLKFB | DLL.CLKFB |
| CELL.IMUX_DLL_RST | DLL.RST |
| CELL.OUT_DLL_CLK0 | DLL.CLK0 |
| CELL.OUT_DLL_CLK90 | DLL.CLK90 |
| CELL.OUT_DLL_CLK180 | DLL.CLK180 |
| CELL.OUT_DLL_CLK270 | DLL.CLK270 |
| CELL.OUT_DLL_CLK2X | DLL.CLK2X |
| CELL.OUT_DLL_CLK2X90 | DLL.CLK2X90 |
| CELL.OUT_DLL_CLKDV | DLL.CLKDV |
| CELL.OUT_DLL_LOCKED | DLL.LOCKED |