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Hard PCI logic

Tile CLKL

Cells: 1 IRIs: 0

Muxes

virtex CLKL muxes
DestinationSources
PCI.IMUX.I1HEX.V2.3, HEX.V2.2, HEX.V2.1, HEX.V2.4, HEX.V2.5, HEX.V2.6, HEX.V3.3, HEX.V3.2, HEX.V3.1, HEX.V3.4, HEX.V3.5, HEX.V3.6
PCI.IMUX.I2HEX.V2.3, HEX.V2.2, HEX.V2.1, HEX.V2.4, HEX.V2.5, HEX.V2.6, HEX.V3.3, HEX.V3.2, HEX.V3.1, HEX.V3.4, HEX.V3.5, HEX.V3.6
PCI.IMUX.I3HEX.V1.3, HEX.V1.2, HEX.V1.1, HEX.V1.4, HEX.V1.5, HEX.V1.6

Bel PCILOGIC

virtex CLKL bel PCILOGIC
PinDirectionWires
I1inputPCI.IMUX.I1
I2inputPCI.IMUX.I2
I3inputPCI.IMUX.I3
PCI_CEoutputPCI_CE

Bel wires

virtex CLKL bel wires
WirePins
PCI_CEPCILOGIC.PCI_CE
PCI.IMUX.I1PCILOGIC.I1
PCI.IMUX.I2PCILOGIC.I2
PCI.IMUX.I3PCILOGIC.I3

Bitstream

virtex CLKL bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
4 - - - - - INT:MUX.PCI.IMUX.I3[0] INT:MUX.PCI.IMUX.I3[1] - - INT:MUX.PCI.IMUX.I3[3] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT:MUX.PCI.IMUX.I3[2] - - - - -
3 INT:MUX.PCI.IMUX.I2[3] INT:MUX.PCI.IMUX.I2[0] INT:MUX.PCI.IMUX.I1[0] INT:MUX.PCI.IMUX.I1[1] INT:MUX.PCI.IMUX.I1[3] INT:MUX.PCI.IMUX.I1[4] INT:MUX.PCI.IMUX.I2[5] INT:MUX.PCI.IMUX.I2[6] INT:MUX.PCI.IMUX.I2[1] INT:MUX.PCI.IMUX.I2[2] PCILOGIC:PCI_DELAY[0] PCILOGIC:PCI_DELAY[1] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT:MUX.PCI.IMUX.I2[4] INT:MUX.PCI.IMUX.I1[2] INT:MUX.PCI.IMUX.I1[5] INT:MUX.PCI.IMUX.I1[6] ~INT:INV.PCI.IMUX.I1 ~INT:INV.PCI.IMUX.I2
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
INT:INV.PCI.IMUX.I1 0.52.3
INT:INV.PCI.IMUX.I2 0.53.3
inverted ~[0]
INT:MUX.PCI.IMUX.I1 0.51.3 0.50.3 0.5.3 0.4.3 0.49.3 0.3.3 0.2.3
INT:MUX.PCI.IMUX.I2 0.7.3 0.6.3 0.48.3 0.0.3 0.9.3 0.8.3 0.1.3
NONE 0 0 0 0 0 0 0
HEX.V2.3 0 0 0 0 0 0 1
HEX.V2.2 0 0 0 0 0 1 0
HEX.V2.1 0 0 0 0 1 0 0
HEX.V2.4 0 0 0 1 0 0 0
HEX.V2.5 0 0 1 0 0 0 0
HEX.V2.6 0 1 0 0 0 0 0
HEX.V3.3 1 0 0 0 0 0 1
HEX.V3.2 1 0 0 0 0 1 0
HEX.V3.1 1 0 0 0 1 0 0
HEX.V3.4 1 0 0 1 0 0 0
HEX.V3.5 1 0 1 0 0 0 0
HEX.V3.6 1 1 0 0 0 0 0
INT:MUX.PCI.IMUX.I3 0.9.4 0.48.4 0.6.4 0.5.4
NONE 0 0 0 0
HEX.V1.6 0 0 0 1
HEX.V1.5 0 0 1 0
HEX.V1.4 0 1 0 0
HEX.V1.3 1 0 0 1
HEX.V1.2 1 0 1 0
HEX.V1.1 1 1 0 0
PCILOGIC:PCI_DELAY 0.11.3 0.10.3
non-inverted [1] [0]

Tile CLKR

Cells: 1 IRIs: 0

Muxes

virtex CLKR muxes
DestinationSources
PCI.IMUX.I1HEX.V2.3, HEX.V2.2, HEX.V2.1, HEX.V2.4, HEX.V2.5, HEX.V2.6, HEX.V3.3, HEX.V3.2, HEX.V3.1, HEX.V3.4, HEX.V3.5, HEX.V3.6
PCI.IMUX.I2HEX.V2.3, HEX.V2.2, HEX.V2.1, HEX.V2.4, HEX.V2.5, HEX.V2.6, HEX.V3.3, HEX.V3.2, HEX.V3.1, HEX.V3.4, HEX.V3.5, HEX.V3.6
PCI.IMUX.I3HEX.V1.3, HEX.V1.2, HEX.V1.1, HEX.V1.4, HEX.V1.5, HEX.V1.6

Bel PCILOGIC

virtex CLKR bel PCILOGIC
PinDirectionWires
I1inputPCI.IMUX.I1
I2inputPCI.IMUX.I2
I3inputPCI.IMUX.I3
PCI_CEoutputPCI_CE

Bel wires

virtex CLKR bel wires
WirePins
PCI_CEPCILOGIC.PCI_CE
PCI.IMUX.I1PCILOGIC.I1
PCI.IMUX.I2PCILOGIC.I2
PCI.IMUX.I3PCILOGIC.I3

Bitstream

virtex CLKR bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - INT:MUX.PCI.IMUX.I3[3] - - INT:MUX.PCI.IMUX.I3[1] INT:MUX.PCI.IMUX.I3[0] - - - - - INT:MUX.PCI.IMUX.I3[2] - - - - -
3 - - - - - - - - - - PCILOGIC:PCI_DELAY[0] PCILOGIC:PCI_DELAY[1] - - - - - - - - - - - - - - - - - - - - - - - - - - INT:MUX.PCI.IMUX.I2[2] INT:MUX.PCI.IMUX.I1[1] INT:MUX.PCI.IMUX.I1[0] INT:MUX.PCI.IMUX.I1[3] INT:MUX.PCI.IMUX.I2[5] INT:MUX.PCI.IMUX.I2[6] ~INT:INV.PCI.IMUX.I1 ~INT:INV.PCI.IMUX.I2 INT:MUX.PCI.IMUX.I1[4] INT:MUX.PCI.IMUX.I1[5] INT:MUX.PCI.IMUX.I1[6] INT:MUX.PCI.IMUX.I1[2] INT:MUX.PCI.IMUX.I2[4] INT:MUX.PCI.IMUX.I2[3] INT:MUX.PCI.IMUX.I2[0] INT:MUX.PCI.IMUX.I2[1]
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
INT:INV.PCI.IMUX.I1 0.44.3
INT:INV.PCI.IMUX.I2 0.45.3
inverted ~[0]
INT:MUX.PCI.IMUX.I1 0.48.3 0.47.3 0.46.3 0.41.3 0.49.3 0.39.3 0.40.3
INT:MUX.PCI.IMUX.I2 0.43.3 0.42.3 0.50.3 0.51.3 0.38.3 0.53.3 0.52.3
NONE 0 0 0 0 0 0 0
HEX.V2.3 0 0 0 0 0 0 1
HEX.V2.2 0 0 0 0 0 1 0
HEX.V2.1 0 0 0 0 1 0 0
HEX.V2.4 0 0 0 1 0 0 0
HEX.V2.5 0 0 1 0 0 0 0
HEX.V2.6 0 1 0 0 0 0 0
HEX.V3.3 1 0 0 0 0 0 1
HEX.V3.2 1 0 0 0 0 1 0
HEX.V3.1 1 0 0 0 1 0 0
HEX.V3.4 1 0 0 1 0 0 0
HEX.V3.5 1 0 1 0 0 0 0
HEX.V3.6 1 1 0 0 0 0 0
INT:MUX.PCI.IMUX.I3 0.38.4 0.48.4 0.41.4 0.42.4
NONE 0 0 0 0
HEX.V1.6 0 0 0 1
HEX.V1.5 0 0 1 0
HEX.V1.4 0 1 0 0
HEX.V1.3 1 0 0 1
HEX.V1.2 1 0 1 0
HEX.V1.1 1 1 0 0
PCILOGIC:PCI_DELAY 0.11.3 0.10.3
non-inverted [1] [0]