Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Configurable Logic Block

The main logic resource in Virtex 2 devices is the CLB (Configurable Logic Block). It corresponds one-to-one with the INT.CLB interconnect tile. Every CLB has:

  • four SLICEs, numbered SLICE0 through SLICE3
  • four horizontal tristate buses, going horizontally through the whole row of CLBs
  • two tristate buffers, TBUF0 and TBUF1, driving the tristate buses

The slices are organized as follows:

  • SLICE0 is on the bottom left of the CLB
  • SLICE1 is above SLICE0
  • SLICE2 is to the right of SLICE0
  • SLICE3 is above SLICE2 and to the right of SLICE1

Every slice has:

  • two 4-input LUTs, named F and G
    • each of them has four inputs, named F[1-4] and G[1-4]
    • every LUT can be used as LUT RAM or shift register
  • two "bypass inputs" used for various purposes
    • BX, associated with the F LUT
    • BY, associated with the G LUT
  • two wide multiplexers
    • F5, associated with the F LUT, multiplexing F and G
    • FX, associated with the G LUT, multiplexing F5 and FX outputs of this and other SLICEs
  • carry logic with a carry chain, going vertically upwards through the CLB column
  • sum of products logic, going horizontally rightwards through the CLB row
  • two main combinational outputs
    • X, associated with the F LUT
    • Y, associated with the G LUT
  • two "bypass" combinational outputs, used for long shift registers and carry chains
    • XB, associated with the F LUT
    • YB, associated with the G LUT
  • two registers and their outputs
    • FFX and XQ, associated with the F LUT
    • FFY and YQ, associated with the G LUT
  • shared control inputs:
    • CLK, the clock input
    • SR, the set/reset input (also used as LUT RAM write enable)
    • CE, the clock enable input

In summary, a single SLICE has the following pins:

  • F[1-4] and G[1-4]: general interconnect inputs, used as LUT inputs and LUT RAM write address
  • BX and BY: general interconnect freely-invertible inputs, used for various purposes
  • CLK, SR, CE: general interconnect freely-invertible inputs
  • X, Y, XQ, YQ, XB, YB: general interconnect outputs
  • COUT: dedicated output (carry output)
  • CIN: dedicated input (carry input), routed from COUT of the slice below
  • SHIFTOUT: dedicated output (shift register output)
  • SHIFTIN: dedicated input (shift register input), routed from SHIFTOUT of the previous slice in sequence
  • SOPOUT: dedicated output (sum of products output)
  • SOPIN: dedicated output (sum of products input), routed from SOPOUT of the slice to the left
  • F5 and FX: dedicated outputs (wide multiplexer outputs)
  • FXINA and FXINB: dedicated inputs (wide multiplexer inputs), routed from F5 and FX of neighbouring slices
  • DIG: dedicated output
  • ALTDIG: dedicated input

Additionally, some pins and circuitry are shared between SLICEs within the same CLB.

The CLK, CE, SR, BX, and BY inputs are invertible on the interconnect level. The CE and SR inputs are further inverted once within the CLB, which should be compensated for with interconnect inversion.

LUTs

There are two 4-input LUTs in each slice, F and G. The F LUT has inputs F[1-4], with F1 being the LSB and F4 being the MSB. The G LUT likewise has inputs G[1-4].

The initial LUT contents are determined by the F and G attributes in the bitstream.

The LUT outputs go to:

  • the FXMUX and GYMUX multiplexers
  • the carry logic
  • the F5 wide multiplexer

LUT RAM

The F_RAM and G_RAM attributes, when set, turn F and G (respectively) into LUT RAM mode.

The signals used in RAM mode are:

  • CLK is the write clock
  • SR is the write enable
  • WF[1-4] and WG[1-4] are write address for the F and G LUTs, respectively
  • DIF and DIG are the data input for the F and G LUTs, respectively
  • SLICEWE0: bit 4 of the write address, when enabled
  • SLICEWE1: bit 5 of the write address, when enabled
  • SLICEWE2: bit 6 of the write address, when enabled

The write address is routed as follows:

  • SLICE0.W[FG][1-4] is routed from SLICE0.[FG][1-4]
  • SLICE1.W[FG][1-4] is routed from SLICE1.[FG][1-4]
  • SLICE2.W[FG][1-4] is routed from SLICE0.[FG][1-4]
  • SLICE3.W[FG][1-4] is routed from SLICE1.[FG][1-4]

Thus, SLICE[01] can be used alone to implement single-port RAM, or together with SLICE[23] to implement dual port or larger RAM.

The DIF_MUX determines the value of DIF:

  • BX: use the BX pin (used for 16×X RAMs)
  • ALT: use the DIG value (used for 32×X and larger RAMs)

The DIG_MUX determines the value of DIG:

  • BY: use the BY pin
  • ALT: use the ALTDIG value

ALTDIG is determined as follows:

  • SLICE0.ALTDIG is connected to SLICE1.DIG
  • SLICE1.ALTDIG is connected to SLICE3.DIG
  • SLICE2.ALTDIG is connected to SLICE3.DIG
  • SLICE3.ALTDIG is connected to SLICE3.DIG of the CLB above

Note that DI[FG]_MUX attributes are also used in the shift register mode, but with different meaning.

The SLICEWE0 signals are routed as follows:

  • SLICE0.SLICEWE0 = SLICE0.BX
  • SLICE1.SLICEWE0 = SLICE1.BX
  • SLICE2.SLICEWE0 = SLICE0.BX
  • SLICE3.SLICEWE0 = SLICE1.BX

When SLICEWE0USED is set, the SLICEWE0 signal is used within the slice. The F LUT is written when it is 1, the G LUT is written when it is 0. Otherwise, the signal is ignored, and both LUTs are written at the same time.

The SLICEWE1 and SLICEWE2 signals are routed as follows:

  • SLICE0.SLICEWE1 = SLICE0.BY
  • SLICE1.SLICEWE1 = !SLICE0.BY
  • SLICE2.SLICEWE1 = SLICE0.BY
  • SLICE3.SLICEWE1 = !SLICE0.BY
  • SLICE0.SLICEWE2 = SLICE1.BY
  • SLICE1.SLICEWE2 = SLICE1.BY
  • SLICE2.SLICEWE2 = !SLICE1.BY
  • SLICE3.SLICEWE2 = !SLICE1.BY

If SLICE0.BYOUTUSED is set, all SLICEs within the CLB will use their SLICEWE1 signal as a write enable — the LUTs are only written when SLICEWE1 is 1. Otherwise, all SLICEWE1 signals are ignored.

If SLICE1.BYOUTUSED is set, all SLICEs within the CLB will use their SLICEWE2 signal as a write enable — the LUTs are only written when SLICEWE2 is 1. Otherwise, all SLICEWE2 signals are ignored.

TODO: SLICE2 and SLICE3 also have BYOUTUSED bits — what do they do, if anything?

Single-port 16×X RAM

Single-port 16×X RAM can be implemented as follows:

  • pick a slice
    • SLICE0 and SLICE1 can always be used
    • SLICE2 can be used if SLICE0 is also used with the same address
    • SLICE3 can be used if SLICE1 is also used with the same address
  • connect CLK to write clock
  • connect SR to write enable
  • for the 16×1 slice in F LUT:
    • connect F[1-4] to the read/write address
    • connect BX to write data
    • set DIF_MUX to BX
    • use F output as read data
  • for the 16×1 slice in G LUT:
    • connect G[1-4] to the read/write address
    • connect BY to write data
    • set DIG_MUX to BY
    • use G output as read data

Dual-port 16×X RAM

Dual-port 16×X RAM can be implemented as follows:

  • pick a pair of slices: either SLICE0 and SLICE2 or SLICE1 and SLICE3
  • connect CLK to write clock
  • connect SR to write enable
  • for the 16×1 slice in F LUTs:
    • connect F[1-4] on SLICE[01] to the write address
    • connect F[1-4] on SLICE[23] to the read address
    • connect BX of both slices to write data
    • set DIF_MUX to BX
    • use F outputs as read data
  • for the 16×1 slice in G LUTs:
    • connect G[1-4] on SLICE[01] to the write address
    • connect G[1-4] on SLICE[23] to the read address
    • connect BY of both slices to write data
    • set DIG_MUX to BY
    • use G outputs as read data

Single-port 32×X RAM

Single-port 32×X RAM can be implemented as follows:

  • pick a slice
    • SLICE0 and SLICE1 can always be used
    • SLICE2 can be used if SLICE0 is also used with the same address
    • SLICE3 can be used if SLICE1 is also used with the same address
  • connect CLK to write clock
  • connect SR to write enable
  • F LUT corresponds to addresses 0x1X
  • G LUT corresponds to addresses 0x0X
  • connect F[1-4] and G[1-4] to low 4 bits of the read/write address
  • connect BX to bit 4 of read/write address
  • set SLICEWE0USED
  • connect BY to write data
  • set DIF_MUX to ALT
  • set DIG_MUX to BY
  • use F5 output as read data

Dual-port 32×X RAM

Dual-port 32×X RAM can be implemented as follows:

  • pick a pair of slices: either SLICE0+SLICE2 or SLICE1+SLICE3
  • connect CLK to write clock
  • connect SR to write enable
  • F LUTs correspond to addresses 0x1X
  • G LUTs correspond to addresses 0x0X
  • connect F[1-4] and G[1-4] of SLICE[01] to low 4 bits of the write address
  • connect F[1-4] and G[1-4] of SLICE[23] to low 4 bits of the read address
  • connect SLICE[01].BX to bit 4 of write address
  • connect SLICE[23].BX to bit 4 of read address
  • set SLICEWE0USED
  • connect BY of both slices to write data
  • set DIF_MUX to ALT
  • set DIG_MUX to BY
  • use F5 outputs as read data

Single-port 64×X RAM

  • pick a pair of slices
    • SLICE0+SLICE1 can always be used
    • SLICE2+SLICE3 can also be used if SLICE0+SLICE1 is used with the same address
  • connect CLK to write clock
  • connect SR to write enable
  • SLICE[13].G corresponds to addresses 0x0X
  • SLICE[13].F corresponds to addresses 0x1X
  • SLICE[02].G corresponds to addresses 0x2X
  • SLICE[02].F corresponds to addresses 0x3X
  • connect F[1-4] and G[1-4] to low 4 bits of the address
  • connect BX to bit 4 of the address
  • set SLICEWE0USED
  • connect SLICE[02].BY to bit 5 of the address
  • set SLICE0.BYOUTUSED
  • connect SLICE[13].BY to write data
  • set DIF_MUX to ALT
  • set SLICE[02].DIG_MUX to ALT
  • set SLICE[13].DIG_MUX to BY
  • use SLICE[02].FX as read data

Dual-port 64×1 RAM

  • use the whole CLB
  • connect CLK to write clock
  • connect SR to write enable
  • SLICE[13].G corresponds to addresses 0x0X
  • SLICE[13].F corresponds to addresses 0x1X
  • SLICE[02].G corresponds to addresses 0x2X
  • SLICE[02].F corresponds to addresses 0x3X
  • connect SLICE[01].F[1-4] and SLICE[01].G[1-4] to low 4 bits of the write address
  • connect SLICE[23].F[1-4] and SLICE[23].G[1-4] to low 4 bits of the read address
  • connect SLICE[01].BX to bit 4 of the write address
  • connect SLICE[23].BX to bit 4 of the read address
  • set SLICEWE0USED
  • connect SLICE0.BY to bit 5 of the write address
  • connect SLICE2.BY to bit 5 of the read address
  • set SLICE0.BYOUTUSED
  • connect SLICE[13].BY to write data
  • set DIF_MUX to ALT
  • set SLICE[02].DIG_MUX to ALT
  • set SLICE[13].DIG_MUX to BY
  • use SLICE[02].FX as read data

Single-port 128×1 RAM

  • use the whole CLB
  • connect CLK to write clock
  • connect SR to write enable
  • SLICE3.G corresponds to addresses 0x0X
  • SLICE3.F corresponds to addresses 0x1X
  • SLICE2.G corresponds to addresses 0x2X
  • SLICE2.F corresponds to addresses 0x3X
  • SLICE1.G corresponds to addresses 0x4X
  • SLICE1.F corresponds to addresses 0x5X
  • SLICE0.G corresponds to addresses 0x6X
  • SLICE0.F corresponds to addresses 0x7X
  • connect F[1-4] and G[1-4] to low 4 bits of the address
  • connect BX to bit 4 of the address
  • set SLICEWE0USED
  • connect SLICE[02].BY to bit 5 of the address
  • set SLICE0.BYOUTUSED
  • connect SLICE1.BY to bit 6 of the address
  • set SLICE1.BYOUTUSED
  • connect SLICE3.BY to write data
  • set DIF_MUX to ALT
  • set SLICE[012].DIG_MUX to ALT
  • set SLICE3.DIG_MUX to BY
  • use SLICE1.FX as read data

Shift registers

The F_SHIFT and G_SHIFT attributes, when set, turn F and G (respectively) into shift register mode.

The signals used in shift register mode are:

  • CLK is the write clock
  • SR is the write enable
  • DIF and DIG are the data input for the F and G LUTs, respectively

The LUTs in shift register mode have shift-out outputs, FMC15 and GMC15, which are the next bit to be shifted out. They can be connected to another LUT's data input to assemble larger shift registers.

The DIF_MUX determines the value of DIF:

  • BX: use the BX pin
  • ALT: use the GMC15 value

The DIG_MUX determines the value of DIG:

  • BY: use the BY pin
  • ALT: use the SHIFTIN pin

SHIFTIN is routed as follows:

  • SLICE0.SHIFTIN = SLICE1.SHIFTOUT = SLICE1.FMC15
  • SLICE1.SHIFTIN = SLICE2.SHIFTOUT = SLICE2.FMC15
  • SLICE2.SHIFTIN = SLICE3.SHIFTOUT = SLICE3.FMC15

SLICE3.SHIFTIN is indeterminate.

Note that DI[FG]_MUX attributes are also used in the LUT RAM mode, but with different meaning.

The external write data is written to bit 0 of the LUT. Bit 15 is shifted out.

TODO: do LUT RAM and shift register modes interfere within a SLICE?

Wide multiplexers

Every SLICE has two wide multiplexers: F5 and FX, used to combine smaller LUTs into larger LUTs. Their function is hardwired:

  • F5 = BX ? F : G
  • FX = BY ? FXINA : FXINB

The F5 output goes to the FXMUX multiplexer, and further wide multiplexers. The FX output goes to the GYMUX multiplexer, and further wide multiplexers.

The FXINA and FXINB inputs are routed as follows:

SLICEFXINAFXINBeffective primitive
SLICE0SLICE0.F5SLICE1.F5MUXF6
SLICE1SLICE0.FXSLICE2.FXMUXF7
SLICE2SLICE2.F5SLICE3.F5MUXF6
SLICE3SLICE1.FXSLICE1.FX, from CLB aboveMUXF8

The FX output isn't connected across the PowerPC hole — a MUXF8 cannot be made of two CLBs separated by a PowerPC.

Carry logic

The carry logic implements the MUXCY and XORCY primitives described in Xilinx documentation. There are several bitstream attributes controlling carry logic operation.

The CYINIT mux determines the start of the carry chain in the slice:

  • CIN: connected from COUT of the SLICE below
  • BX

The CYSELF mux determines the "propagate" (or select) input of the lower MUXCY:

  • F: propagate is connected to F LUT output
  • 1: propagate is connected to const-1 (ie. the MUXCY is effectively skipped from the chain)

The CY0F mux determines the "generate" input of the lower MUXCY:

  • 0 (constant)
  • 1 (constant)
  • F1
  • F2
  • BX
  • PROD: equal to F1 & F2, implementing the MULT_AND primitive

The CYSELG mux determines the "propagate" (or select) input of the upper MUXCY:

  • G: propagate is connected to G LUT output
  • 1: propagate is connected to const-1 (ie. the MUXCY is effectively skipped from the chain)

The CY0G mux determines the "generate" input of the upper MUXCY:

  • 0 (constant)
  • 1 (constant)
  • G1
  • G2
  • BY
  • PROD: equal to G1 & G2, implementing the MULT_AND primitive

The hardwired logic implemented is:

  • FCY = CYSELF ? CY0F : CIN (lower MUXCY)
  • COUT = GCY = CYSELG ? CY0G : FCY (upper MUXCY)
  • FXOR = F ^ CIN (lower XORCY)
  • GXOR = G ^ FCY (upper XORCY)

The dedicated CIN input is routed from:

  • SLICE0.CIN: from SLICE1.COUT of CLB below
  • SLICE1.CIN: from SLICE0.COUT
  • SLICE2.CIN: from SLICE3.COUT of CLB below
  • SLICE3.CIN: from SLICE2.COUT

The carry chains are not connected over PowerPC holes. The SLICE[02].CIN inputs in the row above bottom IOI and in tiles directly above PowerPC are indeterminate.

Sum of products

The carry logic can be used to implement fast wide AND gates (ie. products). Each SLICE also contains a dedicated ORCY primitive that allows combining multiple carry chains into a sum-of-products function.

The SOPEXTSEL mux determines the starting point of the ORCY chain:

  • 0: const 0 (this is the first SLICE in the chain)
  • SOPIN (this is not the first SLICE)

The dedicated ORCY primitive implements simple hardwired logic:

  • SOPOUT = SOPEXTSEL | COUT

The SOPIN pin is routed as follows:

  • SLICE0.SOPIN: SLICE2.SOPOUT of the CLB to the left
  • SLICE1.SOPIN: SLICE3.SOPOUT of the CLB to the left
  • SLICE2.SOPIN: SLICE0.SOPOUT
  • SLICE3.SOPIN: SLICE1.SOPOUT

The SOPOUT chain is connected across BRAM columns, but is not connected over PowerPC holes.

Output multiplexers

The FXMUX multiplexer controls the X output. It has three inputs:

  • F (the LUT output)
  • F5
  • FXOR

The GYMUX multiplexer controls the Y output. It has four inputs:

  • G (the LUT output)
  • FX
  • GXOR
  • SOPOUT

The XBMUX multiplexer controls the XB output. It has two inputs:

  • FCY
  • FMC15: shift register output of F

The YBMUX multiplexer controls the YB output. It has two inputs:

  • GCY (equal to COUT)
  • GMC15: shift register output of G

The DXMUX mulitplexer controls the FFX data input. It has two inputs:

  • X (the FXMUX output)
  • BX

The DYMUX mulitplexer controls the FFY data input. It has two inputs:

  • Y (the GYMUX output)
  • BY

Registers

A SLICE contains two registers:

  • FFX, with input determined by DXMUX and output connected to XQ
  • FFY, with input determined by DYMUX and output connected to YQ

Both registers share the same control signals:

  • CLK: posedge-triggered clock in FF mode or active-low gate in latch mode
  • CE: active-high clock or gate enable
  • SR: if FF_SR_EN, the set/reset signal
  • BY: if FF_REV_EN, the alternate set/reset signal

The following attributes determine register function:

  • FF_LATCH: if set, the registers are latches and CLK behaves as active-low gate; otherwise, the registers are flip-flops and CLK is a posedge-triggered clock
  • FF_SYNC: if set, the SR and BY (if enabled) implement synchronous set/reset (with priority over CE); otherwise, they implement asynchronous set/reset; should not be set together with FF_LATCH
  • FF[XY]_INIT: determines the initial or captured value of given register
    • when the global GSR signal is pulsed (for example, as part of the configuration process), the register is set to the value of this bit
    • when the global GCAP signal is pulsed (for example, by the CAPTURE primitive), this bit captures the current state of the register
  • FF[XY]_SRVAL: determines the set/reset value of given register
  • FF_SR_EN: if set, SR is used as the set/reset signal for both registers, setting them to their FF[XY]_SRVAL
  • FF_REV_EN: if set, BY behaves as secondary set/reset signal for both registers, setting them to the opposite of their FF[XY]_SRVAL

Tristate buses and TBUFs

TODO: document this insanity

Bitstream

The data for a CLB is located in the same bitstream tile as the associated INT.CLB tile.

Tile CLB

Cells: 1

Bel SLICE0

virtex2 CLB bel SLICE0
PinDirectionWires
BXinputIMUX.S0.BX
BYinputIMUX.S0.BY
CEinputIMUX.CE0
CLKinputIMUX.CLK0
F1inputIMUX.S0.F1
F2inputIMUX.S0.F2
F3inputIMUX.S0.F3
F4inputIMUX.S0.F4
G1inputIMUX.S0.G1
G2inputIMUX.S0.G2
G3inputIMUX.S0.G3
G4inputIMUX.S0.G4
SRinputIMUX.SR0
WF1inputIMUX.S0.F1
WF2inputIMUX.S0.F2
WF3inputIMUX.S0.F3
WF4inputIMUX.S0.F4
WG1inputIMUX.S0.G1
WG2inputIMUX.S0.G2
WG3inputIMUX.S0.G3
WG4inputIMUX.S0.G4
XoutputOUT.FAN0
XBoutputOUT.SEC17
XQoutputOUT.SEC20
YoutputOUT.FAN4
YBoutputOUT.SEC8
YQoutputOUT.SEC15

Bel SLICE1

virtex2 CLB bel SLICE1
PinDirectionWires
BXinputIMUX.S1.BX
BYinputIMUX.S1.BY
CEinputIMUX.CE1
CLKinputIMUX.CLK1
F1inputIMUX.S1.F1
F2inputIMUX.S1.F2
F3inputIMUX.S1.F3
F4inputIMUX.S1.F4
G1inputIMUX.S1.G1
G2inputIMUX.S1.G2
G3inputIMUX.S1.G3
G4inputIMUX.S1.G4
SRinputIMUX.SR1
WF1inputIMUX.S1.F1
WF2inputIMUX.S1.F2
WF3inputIMUX.S1.F3
WF4inputIMUX.S1.F4
WG1inputIMUX.S1.G1
WG2inputIMUX.S1.G2
WG3inputIMUX.S1.G3
WG4inputIMUX.S1.G4
XoutputOUT.FAN1
XBoutputOUT.SEC12
XQoutputOUT.SEC21
YoutputOUT.FAN5
YBoutputOUT.SEC9
YQoutputOUT.SEC16

Bel SLICE2

virtex2 CLB bel SLICE2
PinDirectionWires
BXinputIMUX.S2.BX
BYinputIMUX.S2.BY
CEinputIMUX.CE2
CLKinputIMUX.CLK2
F1inputIMUX.S2.F1
F2inputIMUX.S2.F2
F3inputIMUX.S2.F3
F4inputIMUX.S2.F4
G1inputIMUX.S2.G1
G2inputIMUX.S2.G2
G3inputIMUX.S2.G3
G4inputIMUX.S2.G4
SRinputIMUX.SR2
WF1inputIMUX.S0.F1
WF2inputIMUX.S0.F2
WF3inputIMUX.S0.F3
WF4inputIMUX.S0.F4
WG1inputIMUX.S0.G1
WG2inputIMUX.S0.G2
WG3inputIMUX.S0.G3
WG4inputIMUX.S0.G4
XoutputOUT.FAN2
XBoutputOUT.SEC13
XQoutputOUT.SEC22
YoutputOUT.FAN6
YBoutputOUT.SEC11
YQoutputOUT.SEC18

Bel SLICE3

virtex2 CLB bel SLICE3
PinDirectionWires
BXinputIMUX.S3.BX
BYinputIMUX.S3.BY
CEinputIMUX.CE3
CLKinputIMUX.CLK3
F1inputIMUX.S3.F1
F2inputIMUX.S3.F2
F3inputIMUX.S3.F3
F4inputIMUX.S3.F4
G1inputIMUX.S3.G1
G2inputIMUX.S3.G2
G3inputIMUX.S3.G3
G4inputIMUX.S3.G4
SRinputIMUX.SR3
WF1inputIMUX.S1.F1
WF2inputIMUX.S1.F2
WF3inputIMUX.S1.F3
WF4inputIMUX.S1.F4
WG1inputIMUX.S1.G1
WG2inputIMUX.S1.G2
WG3inputIMUX.S1.G3
WG4inputIMUX.S1.G4
XoutputOUT.FAN3
XBoutputOUT.SEC14
XQoutputOUT.SEC23
YoutputOUT.FAN7
YBoutputOUT.SEC10
YQoutputOUT.SEC19

Bel TBUF0

virtex2 CLB bel TBUF0
PinDirectionWires
IinputIMUX.TI0
TinputIMUX.TS0

Bel TBUF1

virtex2 CLB bel TBUF1
PinDirectionWires
IinputIMUX.TI1
TinputIMUX.TS1

Bel TBUS

virtex2 CLB bel TBUS
PinDirectionWires
OUToutputOUT.TBUS

Bel wires

virtex2 CLB bel wires
WirePins
IMUX.CLK0SLICE0.CLK
IMUX.CLK1SLICE1.CLK
IMUX.CLK2SLICE2.CLK
IMUX.CLK3SLICE3.CLK
IMUX.SR0SLICE0.SR
IMUX.SR1SLICE1.SR
IMUX.SR2SLICE2.SR
IMUX.SR3SLICE3.SR
IMUX.CE0SLICE0.CE
IMUX.CE1SLICE1.CE
IMUX.CE2SLICE2.CE
IMUX.CE3SLICE3.CE
IMUX.TI0TBUF0.I
IMUX.TI1TBUF1.I
IMUX.TS0TBUF0.T
IMUX.TS1TBUF1.T
IMUX.S0.F1SLICE0.F1, SLICE0.WF1, SLICE2.WF1
IMUX.S0.F2SLICE0.F2, SLICE0.WF2, SLICE2.WF2
IMUX.S0.F3SLICE0.F3, SLICE0.WF3, SLICE2.WF3
IMUX.S0.F4SLICE0.F4, SLICE0.WF4, SLICE2.WF4
IMUX.S0.G1SLICE0.G1, SLICE0.WG1, SLICE2.WG1
IMUX.S0.G2SLICE0.G2, SLICE0.WG2, SLICE2.WG2
IMUX.S0.G3SLICE0.G3, SLICE0.WG3, SLICE2.WG3
IMUX.S0.G4SLICE0.G4, SLICE0.WG4, SLICE2.WG4
IMUX.S0.BXSLICE0.BX
IMUX.S0.BYSLICE0.BY
IMUX.S1.F1SLICE1.F1, SLICE1.WF1, SLICE3.WF1
IMUX.S1.F2SLICE1.F2, SLICE1.WF2, SLICE3.WF2
IMUX.S1.F3SLICE1.F3, SLICE1.WF3, SLICE3.WF3
IMUX.S1.F4SLICE1.F4, SLICE1.WF4, SLICE3.WF4
IMUX.S1.G1SLICE1.G1, SLICE1.WG1, SLICE3.WG1
IMUX.S1.G2SLICE1.G2, SLICE1.WG2, SLICE3.WG2
IMUX.S1.G3SLICE1.G3, SLICE1.WG3, SLICE3.WG3
IMUX.S1.G4SLICE1.G4, SLICE1.WG4, SLICE3.WG4
IMUX.S1.BXSLICE1.BX
IMUX.S1.BYSLICE1.BY
IMUX.S2.F1SLICE2.F1
IMUX.S2.F2SLICE2.F2
IMUX.S2.F3SLICE2.F3
IMUX.S2.F4SLICE2.F4
IMUX.S2.G1SLICE2.G1
IMUX.S2.G2SLICE2.G2
IMUX.S2.G3SLICE2.G3
IMUX.S2.G4SLICE2.G4
IMUX.S2.BXSLICE2.BX
IMUX.S2.BYSLICE2.BY
IMUX.S3.F1SLICE3.F1
IMUX.S3.F2SLICE3.F2
IMUX.S3.F3SLICE3.F3
IMUX.S3.F4SLICE3.F4
IMUX.S3.G1SLICE3.G1
IMUX.S3.G2SLICE3.G2
IMUX.S3.G3SLICE3.G3
IMUX.S3.G4SLICE3.G4
IMUX.S3.BXSLICE3.BX
IMUX.S3.BYSLICE3.BY
OUT.FAN0SLICE0.X
OUT.FAN1SLICE1.X
OUT.FAN2SLICE2.X
OUT.FAN3SLICE3.X
OUT.FAN4SLICE0.Y
OUT.FAN5SLICE1.Y
OUT.FAN6SLICE2.Y
OUT.FAN7SLICE3.Y
OUT.SEC8SLICE0.YB
OUT.SEC9SLICE1.YB
OUT.SEC10SLICE3.YB
OUT.SEC11SLICE2.YB
OUT.SEC12SLICE1.XB
OUT.SEC13SLICE2.XB
OUT.SEC14SLICE3.XB
OUT.SEC15SLICE0.YQ
OUT.SEC16SLICE1.YQ
OUT.SEC17SLICE0.XB
OUT.SEC18SLICE2.YQ
OUT.SEC19SLICE3.YQ
OUT.SEC20SLICE0.XQ
OUT.SEC21SLICE1.XQ
OUT.SEC22SLICE2.XQ
OUT.SEC23SLICE3.XQ
OUT.TBUSTBUS.OUT

Bitstream

virtex2 CLB bittile 0
BitFrame
0 1 2 3
79 ~SLICE3:FFX_SRVAL ~SLICE1:G[15] ~SLICE3:G[15] -
78 SLICE1:DIG_MUX[0] ~SLICE1:G[14] ~SLICE3:G[14] SLICE3:DIG_MUX[0]
77 - ~SLICE1:G[13] ~SLICE3:G[13] -
76 SLICE3:DXMUX[0] ~SLICE1:G[12] ~SLICE3:G[12] -
75 SLICE3:FF_LATCH ~SLICE1:G[11] ~SLICE3:G[11] -
74 SLICE1:YBMUX[0] ~SLICE1:G[10] ~SLICE3:G[10] SLICE3:YBMUX[0]
73 SLICE1:GYMUX[0] ~SLICE1:G[9] ~SLICE3:G[9] SLICE3:GYMUX[0]
72 SLICE1:SOPEXTSEL[0] ~SLICE1:G[8] ~SLICE3:G[8] -
71 SLICE3:SOPEXTSEL[0] ~SLICE1:G[7] ~SLICE3:G[7] -
70 SLICE1:CY0G[1] ~SLICE1:G[6] ~SLICE3:G[6] SLICE3:CY0G[1]
69 SLICE1:CY0G[2] ~SLICE1:G[5] ~SLICE3:G[5] SLICE3:CY0G[2]
68 SLICE3:FF_REV_ENABLE ~SLICE1:G[4] ~SLICE3:G[4] -
67 SLICE3:DYMUX[0] ~SLICE1:G[3] ~SLICE3:G[3] -
66 SLICE1:CY0G[0] ~SLICE1:G[2] ~SLICE3:G[2] SLICE3:CY0G[0]
65 SLICE1:GYMUX[1] ~SLICE1:G[1] ~SLICE3:G[1] SLICE3:GYMUX[1]
64 ~SLICE3:FFY_SRVAL ~SLICE1:G[0] ~SLICE3:G[0] -
63 SLICE3:FF_SR_SYNC - - -
62 SLICE1:BYOUTUSED ~SLICE1:FF_SR_ENABLE ~SLICE3:FF_SR_ENABLE SLICE3:BYOUTUSED
61 SLICE1:XBMUX[0] SLICE1:G_SHIFT SLICE3:G_SHIFT SLICE3:XBMUX[0]
60 TBUS:JOINER_R SLICE1:G_RAM SLICE3:G_RAM -
59 TBUF0:OUT_B ~SLICE3:FFX_INIT ~SLICE3:FFY_INIT -
58 SLICE1:CYSELG[0] SLICE1:F_RAM SLICE3:F_RAM SLICE3:CYSELG[0]
57 SLICE1:SLICEWE0USED ~SLICE1:FFX_INIT ~SLICE1:FFY_INIT SLICE3:SLICEWE0USED
56 SLICE1:FF_SR_SYNC SLICE1:F_SHIFT SLICE3:F_SHIFT -
55 ~SLICE1:FFY_SRVAL ~SLICE1:F[0] ~SLICE3:F[0] -
54 SLICE1:FXMUX[1] ~SLICE1:F[1] ~SLICE3:F[1] SLICE3:FXMUX[1]
53 SLICE1:CY0F[0] ~SLICE1:F[2] ~SLICE3:F[2] SLICE3:CY0F[0]
52 SLICE1:DYMUX[0] ~SLICE1:F[3] ~SLICE3:F[3] -
51 SLICE1:FF_REV_ENABLE ~SLICE1:F[4] ~SLICE3:F[4] -
50 SLICE1:CY0F[2] ~SLICE1:F[5] ~SLICE3:F[5] SLICE3:CY0F[2]
49 SLICE1:CY0F[1] ~SLICE1:F[6] ~SLICE3:F[6] SLICE3:CY0F[1]
48 - ~SLICE1:F[7] ~SLICE3:F[7] -
47 - ~SLICE1:F[8] ~SLICE3:F[8] -
46 SLICE1:FXMUX[0] ~SLICE1:F[9] ~SLICE3:F[9] SLICE3:FXMUX[0]
45 SLICE1:CYSELF[0] ~SLICE1:F[10] ~SLICE3:F[10] SLICE3:CYSELF[0]
44 SLICE1:FF_LATCH ~SLICE1:F[11] ~SLICE3:F[11] -
43 SLICE1:DXMUX[0] ~SLICE1:F[12] ~SLICE3:F[12] -
42 SLICE1:CYINIT[0] ~SLICE1:F[13] ~SLICE3:F[13] SLICE3:CYINIT[0]
41 SLICE1:DIF_MUX[0] ~SLICE1:F[14] ~SLICE3:F[14] SLICE3:DIF_MUX[0]
40 ~SLICE1:FFX_SRVAL ~SLICE1:F[15] ~SLICE3:F[15] -
39 ~SLICE2:FFX_SRVAL ~SLICE0:G[15] ~SLICE2:G[15] -
38 SLICE0:DIG_MUX[0] ~SLICE0:G[14] ~SLICE2:G[14] SLICE2:DIG_MUX[0]
37 TBUF1:OUT_B ~SLICE0:G[13] ~SLICE2:G[13] -
36 SLICE2:DXMUX[0] ~SLICE0:G[12] ~SLICE2:G[12] -
35 SLICE2:FF_LATCH ~SLICE0:G[11] ~SLICE2:G[11] -
34 SLICE0:YBMUX[0] ~SLICE0:G[10] ~SLICE2:G[10] SLICE2:YBMUX[0]
33 SLICE0:GYMUX[0] ~SLICE0:G[9] ~SLICE2:G[9] SLICE2:GYMUX[0]
32 SLICE0:SOPEXTSEL[0] ~SLICE0:G[8] ~SLICE2:G[8] -
31 SLICE2:SOPEXTSEL[0] ~SLICE0:G[7] ~SLICE2:G[7] -
30 SLICE0:CY0G[1] ~SLICE0:G[6] ~SLICE2:G[6] SLICE2:CY0G[1]
29 SLICE0:CY0G[2] ~SLICE0:G[5] ~SLICE2:G[5] SLICE2:CY0G[2]
28 SLICE2:FF_REV_ENABLE ~SLICE0:G[4] ~SLICE2:G[4] -
27 SLICE2:DYMUX[0] ~SLICE0:G[3] ~SLICE2:G[3] -
26 SLICE0:CY0G[0] ~SLICE0:G[2] ~SLICE2:G[2] SLICE2:CY0G[0]
25 SLICE0:GYMUX[1] ~SLICE0:G[1] ~SLICE2:G[1] SLICE2:GYMUX[1]
24 ~SLICE2:FFY_SRVAL ~SLICE0:G[0] ~SLICE2:G[0] -
23 SLICE2:FF_SR_SYNC - - -
22 SLICE0:BYOUTUSED ~SLICE0:FF_SR_ENABLE ~SLICE2:FF_SR_ENABLE SLICE2:BYOUTUSED
21 SLICE0:XBMUX[0] SLICE0:G_SHIFT SLICE2:G_SHIFT SLICE2:XBMUX[0]
20 TBUF1:OUT_A SLICE0:G_RAM SLICE2:G_RAM -
19 TBUF0:OUT_A ~SLICE2:FFX_INIT ~SLICE2:FFY_INIT -
18 SLICE0:CYSELG[0] SLICE0:F_RAM SLICE2:F_RAM SLICE2:CYSELG[0]
17 SLICE0:SLICEWE0USED ~SLICE0:FFX_INIT ~SLICE0:FFY_INIT SLICE2:SLICEWE0USED
16 SLICE0:FF_SR_SYNC SLICE0:F_SHIFT SLICE2:F_SHIFT -
15 ~SLICE0:FFY_SRVAL ~SLICE0:F[0] ~SLICE2:F[0] -
14 SLICE0:FXMUX[1] ~SLICE0:F[1] ~SLICE2:F[1] SLICE2:FXMUX[1]
13 SLICE0:CY0F[0] ~SLICE0:F[2] ~SLICE2:F[2] SLICE2:CY0F[0]
12 SLICE0:DYMUX[0] ~SLICE0:F[3] ~SLICE2:F[3] -
11 SLICE0:FF_REV_ENABLE ~SLICE0:F[4] ~SLICE2:F[4] -
10 SLICE0:CY0F[2] ~SLICE0:F[5] ~SLICE2:F[5] SLICE2:CY0F[2]
9 SLICE0:CY0F[1] ~SLICE0:F[6] ~SLICE2:F[6] SLICE2:CY0F[1]
8 - ~SLICE0:F[7] ~SLICE2:F[7] -
7 - ~SLICE0:F[8] ~SLICE2:F[8] -
6 SLICE0:FXMUX[0] ~SLICE0:F[9] ~SLICE2:F[9] SLICE2:FXMUX[0]
5 SLICE0:CYSELF[0] ~SLICE0:F[10] ~SLICE2:F[10] SLICE2:CYSELF[0]
4 SLICE0:FF_LATCH ~SLICE0:F[11] ~SLICE2:F[11] -
3 SLICE0:DXMUX[0] ~SLICE0:F[12] ~SLICE2:F[12] -
2 SLICE0:CYINIT[0] ~SLICE0:F[13] ~SLICE2:F[13] SLICE2:CYINIT[0]
1 SLICE0:DIF_MUX[0] ~SLICE0:F[14] ~SLICE2:F[14] SLICE2:DIF_MUX[0]
0 ~SLICE0:FFX_SRVAL ~SLICE0:F[15] ~SLICE2:F[15] -
SLICE0:BYOUTUSED 0.0.22
SLICE0:FF_LATCH 0.0.4
SLICE0:FF_REV_ENABLE 0.0.11
SLICE0:FF_SR_SYNC 0.0.16
SLICE0:F_RAM 0.1.18
SLICE0:F_SHIFT 0.1.16
SLICE0:G_RAM 0.1.20
SLICE0:G_SHIFT 0.1.21
SLICE0:SLICEWE0USED 0.0.17
SLICE1:BYOUTUSED 0.0.62
SLICE1:FF_LATCH 0.0.44
SLICE1:FF_REV_ENABLE 0.0.51
SLICE1:FF_SR_SYNC 0.0.56
SLICE1:F_RAM 0.1.58
SLICE1:F_SHIFT 0.1.56
SLICE1:G_RAM 0.1.60
SLICE1:G_SHIFT 0.1.61
SLICE1:SLICEWE0USED 0.0.57
SLICE2:BYOUTUSED 0.3.22
SLICE2:FF_LATCH 0.0.35
SLICE2:FF_REV_ENABLE 0.0.28
SLICE2:FF_SR_SYNC 0.0.23
SLICE2:F_RAM 0.2.18
SLICE2:F_SHIFT 0.2.16
SLICE2:G_RAM 0.2.20
SLICE2:G_SHIFT 0.2.21
SLICE2:SLICEWE0USED 0.3.17
SLICE3:BYOUTUSED 0.3.62
SLICE3:FF_LATCH 0.0.75
SLICE3:FF_REV_ENABLE 0.0.68
SLICE3:FF_SR_SYNC 0.0.63
SLICE3:F_RAM 0.2.58
SLICE3:F_SHIFT 0.2.56
SLICE3:G_RAM 0.2.60
SLICE3:G_SHIFT 0.2.61
SLICE3:SLICEWE0USED 0.3.57
TBUF0:OUT_A 0.0.19
TBUF0:OUT_B 0.0.59
TBUF1:OUT_A 0.0.20
TBUF1:OUT_B 0.0.37
TBUS:JOINER_R 0.0.60
non-inverted [0]
SLICE0:CY0F 0.0.10 0.0.9 0.0.13
SLICE1:CY0F 0.0.50 0.0.49 0.0.53
SLICE2:CY0F 0.3.10 0.3.9 0.3.13
SLICE3:CY0F 0.3.50 0.3.49 0.3.53
BX 0 0 0
F2 0 0 1
F1 0 1 1
PROD 1 0 0
1 1 0 1
0 1 1 1
SLICE0:CY0G 0.0.29 0.0.30 0.0.26
SLICE1:CY0G 0.0.69 0.0.70 0.0.66
SLICE2:CY0G 0.3.29 0.3.30 0.3.26
SLICE3:CY0G 0.3.69 0.3.70 0.3.66
BY 0 0 0
G2 0 0 1
G1 0 1 1
PROD 1 0 0
1 1 0 1
0 1 1 1
SLICE0:CYINIT 0.0.2
SLICE1:CYINIT 0.0.42
SLICE2:CYINIT 0.3.2
SLICE3:CYINIT 0.3.42
BX 0
CIN 1
SLICE0:CYSELF 0.0.5
SLICE1:CYSELF 0.0.45
SLICE2:CYSELF 0.3.5
SLICE3:CYSELF 0.3.45
1 0
F 1
SLICE0:CYSELG 0.0.18
SLICE1:CYSELG 0.0.58
SLICE2:CYSELG 0.3.18
SLICE3:CYSELG 0.3.58
1 0
G 1
SLICE0:DIF_MUX 0.0.1
SLICE1:DIF_MUX 0.0.41
SLICE2:DIF_MUX 0.3.1
SLICE3:DIF_MUX 0.3.41
ALT 0
BX 1
SLICE0:DIG_MUX 0.0.38
SLICE1:DIG_MUX 0.0.78
SLICE2:DIG_MUX 0.3.38
SLICE3:DIG_MUX 0.3.78
ALT 0
BY 1
SLICE0:DXMUX 0.0.3
SLICE1:DXMUX 0.0.43
SLICE2:DXMUX 0.0.36
SLICE3:DXMUX 0.0.76
BX 0
X 1
SLICE0:DYMUX 0.0.12
SLICE1:DYMUX 0.0.52
SLICE2:DYMUX 0.0.27
SLICE3:DYMUX 0.0.67
BY 0
Y 1
SLICE0:F 0.1.0 0.1.1 0.1.2 0.1.3 0.1.4 0.1.5 0.1.6 0.1.7 0.1.8 0.1.9 0.1.10 0.1.11 0.1.12 0.1.13 0.1.14 0.1.15
SLICE0:G 0.1.39 0.1.38 0.1.37 0.1.36 0.1.35 0.1.34 0.1.33 0.1.32 0.1.31 0.1.30 0.1.29 0.1.28 0.1.27 0.1.26 0.1.25 0.1.24
SLICE1:F 0.1.40 0.1.41 0.1.42 0.1.43 0.1.44 0.1.45 0.1.46 0.1.47 0.1.48 0.1.49 0.1.50 0.1.51 0.1.52 0.1.53 0.1.54 0.1.55
SLICE1:G 0.1.79 0.1.78 0.1.77 0.1.76 0.1.75 0.1.74 0.1.73 0.1.72 0.1.71 0.1.70 0.1.69 0.1.68 0.1.67 0.1.66 0.1.65 0.1.64
SLICE2:F 0.2.0 0.2.1 0.2.2 0.2.3 0.2.4 0.2.5 0.2.6 0.2.7 0.2.8 0.2.9 0.2.10 0.2.11 0.2.12 0.2.13 0.2.14 0.2.15
SLICE2:G 0.2.39 0.2.38 0.2.37 0.2.36 0.2.35 0.2.34 0.2.33 0.2.32 0.2.31 0.2.30 0.2.29 0.2.28 0.2.27 0.2.26 0.2.25 0.2.24
SLICE3:F 0.2.40 0.2.41 0.2.42 0.2.43 0.2.44 0.2.45 0.2.46 0.2.47 0.2.48 0.2.49 0.2.50 0.2.51 0.2.52 0.2.53 0.2.54 0.2.55
SLICE3:G 0.2.79 0.2.78 0.2.77 0.2.76 0.2.75 0.2.74 0.2.73 0.2.72 0.2.71 0.2.70 0.2.69 0.2.68 0.2.67 0.2.66 0.2.65 0.2.64
inverted ~[15] ~[14] ~[13] ~[12] ~[11] ~[10] ~[9] ~[8] ~[7] ~[6] ~[5] ~[4] ~[3] ~[2] ~[1] ~[0]
SLICE0:FFX_INIT 0.1.17
SLICE0:FFX_SRVAL 0.0.0
SLICE0:FFY_INIT 0.2.17
SLICE0:FFY_SRVAL 0.0.15
SLICE0:FF_SR_ENABLE 0.1.22
SLICE1:FFX_INIT 0.1.57
SLICE1:FFX_SRVAL 0.0.40
SLICE1:FFY_INIT 0.2.57
SLICE1:FFY_SRVAL 0.0.55
SLICE1:FF_SR_ENABLE 0.1.62
SLICE2:FFX_INIT 0.1.19
SLICE2:FFX_SRVAL 0.0.39
SLICE2:FFY_INIT 0.2.19
SLICE2:FFY_SRVAL 0.0.24
SLICE2:FF_SR_ENABLE 0.2.22
SLICE3:FFX_INIT 0.1.59
SLICE3:FFX_SRVAL 0.0.79
SLICE3:FFY_INIT 0.2.59
SLICE3:FFY_SRVAL 0.0.64
SLICE3:FF_SR_ENABLE 0.2.62
inverted ~[0]
SLICE0:FXMUX 0.0.14 0.0.6
SLICE1:FXMUX 0.0.54 0.0.46
SLICE2:FXMUX 0.3.14 0.3.6
SLICE3:FXMUX 0.3.54 0.3.46
F 0 0
F5 0 1
FXOR 1 1
SLICE0:GYMUX 0.0.25 0.0.33
SLICE1:GYMUX 0.0.65 0.0.73
SLICE2:GYMUX 0.3.25 0.3.33
SLICE3:GYMUX 0.3.65 0.3.73
G 0 0
FX 0 1
SOPOUT 1 0
GXOR 1 1
SLICE0:SOPEXTSEL 0.0.32
SLICE1:SOPEXTSEL 0.0.72
SLICE2:SOPEXTSEL 0.0.31
SLICE3:SOPEXTSEL 0.0.71
0 0
SOPIN 1
SLICE0:XBMUX 0.0.21
SLICE1:XBMUX 0.0.61
SLICE2:XBMUX 0.3.21
SLICE3:XBMUX 0.3.61
FCY 0
FMC15 1
SLICE0:YBMUX 0.0.34
SLICE1:YBMUX 0.0.74
SLICE2:YBMUX 0.3.34
SLICE3:YBMUX 0.3.74
GCY 0
GMC15 1