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Clock column buffer

TODO: document

Tile GCLKH

Cells: 2 IRIs: 0

Bel GCLKH

virtex2 GCLKH bel GCLKH
PinDirectionWires
OUT_B0outputTCELL0:GCLK0
OUT_B1outputTCELL0:GCLK1
OUT_B2outputTCELL0:GCLK2
OUT_B3outputTCELL0:GCLK3
OUT_B4outputTCELL0:GCLK4
OUT_B5outputTCELL0:GCLK5
OUT_B6outputTCELL0:GCLK6
OUT_B7outputTCELL0:GCLK7
OUT_T0outputTCELL1:GCLK0
OUT_T1outputTCELL1:GCLK1
OUT_T2outputTCELL1:GCLK2
OUT_T3outputTCELL1:GCLK3
OUT_T4outputTCELL1:GCLK4
OUT_T5outputTCELL1:GCLK5
OUT_T6outputTCELL1:GCLK6
OUT_T7outputTCELL1:GCLK7

Bel GLOBALSIG

virtex2 GCLKH bel GLOBALSIG
PinDirectionWires

Bel wires

virtex2 GCLKH bel wires
WirePins
TCELL0:GCLK0GCLKH.OUT_B0
TCELL0:GCLK1GCLKH.OUT_B1
TCELL0:GCLK2GCLKH.OUT_B2
TCELL0:GCLK3GCLKH.OUT_B3
TCELL0:GCLK4GCLKH.OUT_B4
TCELL0:GCLK5GCLKH.OUT_B5
TCELL0:GCLK6GCLKH.OUT_B6
TCELL0:GCLK7GCLKH.OUT_B7
TCELL1:GCLK0GCLKH.OUT_T0
TCELL1:GCLK1GCLKH.OUT_T1
TCELL1:GCLK2GCLKH.OUT_T2
TCELL1:GCLK3GCLKH.OUT_T3
TCELL1:GCLK4GCLKH.OUT_T4
TCELL1:GCLK5GCLKH.OUT_T5
TCELL1:GCLK6GCLKH.OUT_T6
TCELL1:GCLK7GCLKH.OUT_T7

Bitstream

virtex2 GCLKH bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 GCLKH:BUF.OUT_T0 - - GCLKH:BUF.OUT_B0 GCLKH:BUF.OUT_T1 GCLKH:BUF.OUT_B1 GCLKH:BUF.OUT_T2 GCLKH:BUF.OUT_B2 GCLKH:BUF.OUT_T3 GCLKH:BUF.OUT_B3 GCLKH:BUF.OUT_T4 GCLKH:BUF.OUT_B4 GCLKH:BUF.OUT_T5 GCLKH:BUF.OUT_B5 GCLKH:BUF.OUT_T6 GCLKH:BUF.OUT_B6 GCLKH:BUF.OUT_T7 GCLKH:BUF.OUT_B7
GCLKH:BUF.OUT_B0 0.3.0
GCLKH:BUF.OUT_B1 0.5.0
GCLKH:BUF.OUT_B2 0.7.0
GCLKH:BUF.OUT_B3 0.9.0
GCLKH:BUF.OUT_B4 0.11.0
GCLKH:BUF.OUT_B5 0.13.0
GCLKH:BUF.OUT_B6 0.15.0
GCLKH:BUF.OUT_B7 0.17.0
GCLKH:BUF.OUT_T0 0.0.0
GCLKH:BUF.OUT_T1 0.4.0
GCLKH:BUF.OUT_T2 0.6.0
GCLKH:BUF.OUT_T3 0.8.0
GCLKH:BUF.OUT_T4 0.10.0
GCLKH:BUF.OUT_T5 0.12.0
GCLKH:BUF.OUT_T6 0.14.0
GCLKH:BUF.OUT_T7 0.16.0
non-inverted [0]