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Clock column buffer

TODO: document

Tile HCLK

Cells: 2

Bel HCLK

virtex2 HCLK bel HCLK
PinDirectionWires
OUT_B0outputS.GCLK[0]
OUT_B1outputS.GCLK[1]
OUT_B2outputS.GCLK[2]
OUT_B3outputS.GCLK[3]
OUT_B4outputS.GCLK[4]
OUT_B5outputS.GCLK[5]
OUT_B6outputS.GCLK[6]
OUT_B7outputS.GCLK[7]
OUT_T0outputN.GCLK[0]
OUT_T1outputN.GCLK[1]
OUT_T2outputN.GCLK[2]
OUT_T3outputN.GCLK[3]
OUT_T4outputN.GCLK[4]
OUT_T5outputN.GCLK[5]
OUT_T6outputN.GCLK[6]
OUT_T7outputN.GCLK[7]

Bel GLOBALSIG

virtex2 HCLK bel GLOBALSIG
PinDirectionWires

Bel wires

virtex2 HCLK bel wires
WirePins
S.GCLK[0]HCLK.OUT_B0
S.GCLK[1]HCLK.OUT_B1
S.GCLK[2]HCLK.OUT_B2
S.GCLK[3]HCLK.OUT_B3
S.GCLK[4]HCLK.OUT_B4
S.GCLK[5]HCLK.OUT_B5
S.GCLK[6]HCLK.OUT_B6
S.GCLK[7]HCLK.OUT_B7
N.GCLK[0]HCLK.OUT_T0
N.GCLK[1]HCLK.OUT_T1
N.GCLK[2]HCLK.OUT_T2
N.GCLK[3]HCLK.OUT_T3
N.GCLK[4]HCLK.OUT_T4
N.GCLK[5]HCLK.OUT_T5
N.GCLK[6]HCLK.OUT_T6
N.GCLK[7]HCLK.OUT_T7

Bitstream

virtex2 HCLK rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B0 - - - - - - - - - - - - - - - - - - - - - -
### Bitstream
virtex2 HCLK rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17
B0 HCLK:BUF.OUT_T0 - - HCLK:BUF.OUT_B0 HCLK:BUF.OUT_T1 HCLK:BUF.OUT_B1 HCLK:BUF.OUT_T2 HCLK:BUF.OUT_B2 HCLK:BUF.OUT_T3 HCLK:BUF.OUT_B3 HCLK:BUF.OUT_T4 HCLK:BUF.OUT_B4 HCLK:BUF.OUT_T5 HCLK:BUF.OUT_B5 HCLK:BUF.OUT_T6 HCLK:BUF.OUT_B6 HCLK:BUF.OUT_T7 HCLK:BUF.OUT_B7
HCLK:BUF.OUT_B0 0.F3.B0
HCLK:BUF.OUT_B1 0.F5.B0
HCLK:BUF.OUT_B2 0.F7.B0
HCLK:BUF.OUT_B3 0.F9.B0
HCLK:BUF.OUT_B4 0.F11.B0
HCLK:BUF.OUT_B5 0.F13.B0
HCLK:BUF.OUT_B6 0.F15.B0
HCLK:BUF.OUT_B7 0.F17.B0
HCLK:BUF.OUT_T0 0.F0.B0
HCLK:BUF.OUT_T1 0.F4.B0
HCLK:BUF.OUT_T2 0.F6.B0
HCLK:BUF.OUT_T3 0.F8.B0
HCLK:BUF.OUT_T4 0.F10.B0
HCLK:BUF.OUT_T5 0.F12.B0
HCLK:BUF.OUT_T6 0.F14.B0
HCLK:BUF.OUT_T7 0.F16.B0
non-inverted [0]