Clock column buffer

TODO: document

Tile HCLK

Cells: 2

Switchbox HCLK

virtex2 HCLK switchbox HCLK programmable buffers
Destination	Source	Bit
S.GCLK[0]	N.GCLK_ROW[0]	MAIN[3][0]
S.GCLK[1]	N.GCLK_ROW[1]	MAIN[5][0]
S.GCLK[2]	N.GCLK_ROW[2]	MAIN[7][0]
S.GCLK[3]	N.GCLK_ROW[3]	MAIN[9][0]
S.GCLK[4]	N.GCLK_ROW[4]	MAIN[11][0]
S.GCLK[5]	N.GCLK_ROW[5]	MAIN[13][0]
S.GCLK[6]	N.GCLK_ROW[6]	MAIN[15][0]
S.GCLK[7]	N.GCLK_ROW[7]	MAIN[17][0]
N.GCLK[0]	N.GCLK_ROW[0]	MAIN[0][0]
N.GCLK[1]	N.GCLK_ROW[1]	MAIN[4][0]
N.GCLK[2]	N.GCLK_ROW[2]	MAIN[6][0]
N.GCLK[3]	N.GCLK_ROW[3]	MAIN[8][0]
N.GCLK[4]	N.GCLK_ROW[4]	MAIN[10][0]
N.GCLK[5]	N.GCLK_ROW[5]	MAIN[12][0]
N.GCLK[6]	N.GCLK_ROW[6]	MAIN[14][0]
N.GCLK[7]	N.GCLK_ROW[7]	MAIN[16][0]

Bels GLOBALSIG_HCLK_V2

virtex2 HCLK bel GLOBALSIG_HCLK_V2 pins
Pin	Direction	GLOBALSIG_HCLK

virtex2 HCLK bel GLOBALSIG_HCLK_V2 attribute bits
Attribute	GLOBALSIG_HCLK
GWE_GHIGH_S_ENABLE	!MAIN[19][0]
GWE_GHIGH_N_ENABLE	!MAIN[18][0]
GSR_S_ENABLE	!MAIN[21][0]
GSR_N_ENABLE	!MAIN[20][0]

Bitstream

virtex2 HCLK rect MAIN
Bit	Frame
Bit	F21	F20	F19	F18	F17	F16	F15	F14	F13	F12	F11	F10	F9	F8	F7	F6	F5	F4	F3	F2	F1	F0
B0	GLOBALSIG_HCLK: ! GSR_S_ENABLE	GLOBALSIG_HCLK: ! GSR_N_ENABLE	GLOBALSIG_HCLK: ! GWE_GHIGH_S_ENABLE	GLOBALSIG_HCLK: ! GWE_GHIGH_N_ENABLE	HCLK: buffer S.GCLK[7] ← N.GCLK_ROW[7]	HCLK: buffer N.GCLK[7] ← N.GCLK_ROW[7]	HCLK: buffer S.GCLK[6] ← N.GCLK_ROW[6]	HCLK: buffer N.GCLK[6] ← N.GCLK_ROW[6]	HCLK: buffer S.GCLK[5] ← N.GCLK_ROW[5]	HCLK: buffer N.GCLK[5] ← N.GCLK_ROW[5]	HCLK: buffer S.GCLK[4] ← N.GCLK_ROW[4]	HCLK: buffer N.GCLK[4] ← N.GCLK_ROW[4]	HCLK: buffer S.GCLK[3] ← N.GCLK_ROW[3]	HCLK: buffer N.GCLK[3] ← N.GCLK_ROW[3]	HCLK: buffer S.GCLK[2] ← N.GCLK_ROW[2]	HCLK: buffer N.GCLK[2] ← N.GCLK_ROW[2]	HCLK: buffer S.GCLK[1] ← N.GCLK_ROW[1]	HCLK: buffer N.GCLK[1] ← N.GCLK_ROW[1]	HCLK: buffer S.GCLK[0] ← N.GCLK_ROW[0]	-	-	HCLK: buffer N.GCLK[0] ← N.GCLK_ROW[0]