Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Northeast

TODO: document

Tile CNR_NE_V2

Cells: 1

Bel DCI[0]

virtex2 CNR_NE_V2 bel DCI[0]
PinDirectionWires
ADDRESS0outputOUT_HALF0[14]
ADDRESS1outputOUT_HALF1[14]
ADDRESS2outputOUT_HALF0[13]
DATAoutputOUT_HALF1[15]
DCI_CLKinputIMUX_G2_DATA[7]
DCI_DONEoutputOUT_HALF0[15]
DCI_RESETinputIMUX_G2_DATA[6]
HI_LO_NinputIMUX_G2_DATA[5]
HI_LO_PinputIMUX_G2_DATA[4]
N_OR_PoutputOUT_HALF1[16]
SCLKoutputOUT_HALF0[16]
UPDATEoutputOUT_HALF1[17]

Bel DCI[1]

virtex2 CNR_NE_V2 bel DCI[1]
PinDirectionWires
ADDRESS0outputOUT_HALF0[9]
ADDRESS1outputOUT_HALF1[9]
ADDRESS2outputOUT_HALF0[8]
DATAoutputOUT_HALF1[10]
DCI_CLKinputIMUX_G1_DATA[7]
DCI_DONEoutputOUT_HALF0[10]
DCI_RESETinputIMUX_G1_DATA[6]
HI_LO_NinputIMUX_G1_DATA[5]
HI_LO_PinputIMUX_G1_DATA[4]
N_OR_PoutputOUT_HALF1[11]
SCLKoutputOUT_HALF0[11]
UPDATEoutputOUT_HALF1[12]

Bel BSCAN

virtex2 CNR_NE_V2 bel BSCAN
PinDirectionWires
CAPTUREoutputOUT_FAN[7]
DRCK1outputOUT_FAN[0]
DRCK2outputOUT_FAN[1]
RESEToutputOUT_HALF0[17]
SEL1outputOUT_FAN[2]
SEL2outputOUT_FAN[3]
SHIFToutputOUT_FAN[4]
TDIoutputOUT_FAN[5]
TDO1inputIMUX_G0_DATA[0]
TDO2inputIMUX_G0_DATA[1]
UPDATEoutputOUT_FAN[6]

Bel wires

virtex2 CNR_NE_V2 bel wires
WirePins
IMUX_G0_DATA[0]BSCAN.TDO1
IMUX_G0_DATA[1]BSCAN.TDO2
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_FAN[0]BSCAN.DRCK1
OUT_FAN[1]BSCAN.DRCK2
OUT_FAN[2]BSCAN.SEL1
OUT_FAN[3]BSCAN.SEL2
OUT_FAN[4]BSCAN.SHIFT
OUT_FAN[5]BSCAN.TDI
OUT_FAN[6]BSCAN.UPDATE
OUT_FAN[7]BSCAN.CAPTURE
OUT_HALF0[8]DCI[1].ADDRESS2
OUT_HALF0[9]DCI[1].ADDRESS0
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[13]DCI[0].ADDRESS2
OUT_HALF0[14]DCI[0].ADDRESS0
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF0[17]BSCAN.RESET
OUT_HALF1[9]DCI[1].ADDRESS1
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[14]DCI[0].ADDRESS1
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_NE_V2 rect TERM_H
BitFrame
F0 F1 F2 F3
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2 rect TERM_V
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B11 - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -
### Bitstream
virtex2 CNR_NE_V2 rect R0
BitFrame
F0 F1 F2 F3
B48 - - DCI[0]:LVDSBIAS[1] DCI[0]:LVDSBIAS[0]
B47 - - DCI[0]:LVDSBIAS[3] DCI[0]:LVDSBIAS[2]
B46 - - DCI[0]:LVDSBIAS[5] DCI[0]:LVDSBIAS[4]
B45 - - DCI[0]:LVDSBIAS[7] DCI[0]:LVDSBIAS[6]
B44 - - - DCI[0]:LVDSBIAS[8]
B43 - - - -
B42 - - DCI[0]:ENABLE -
B41 - - - -
B40 - - - -
B39 - - DCI[0]:NMASK_TERM_SPLIT[0] -
B38 - - DCI[0]:NMASK_TERM_SPLIT[2] DCI[0]:NMASK_TERM_SPLIT[1]
B37 - - DCI[0]:NMASK_TERM_SPLIT[4] DCI[0]:NMASK_TERM_SPLIT[3]
B36 - - DCI[0]:PMASK_TERM_VCC[1] DCI[0]:PMASK_TERM_VCC[0]
B35 - - DCI[0]:PMASK_TERM_VCC[3] DCI[0]:PMASK_TERM_VCC[2]
B34 - - DCI[0]:PMASK_TERM_SPLIT[0] DCI[0]:PMASK_TERM_VCC[4]
B33 - - DCI[0]:PMASK_TERM_SPLIT[2] DCI[0]:PMASK_TERM_SPLIT[1]
B32 - - DCI[0]:PMASK_TERM_SPLIT[4] DCI[0]:PMASK_TERM_SPLIT[3]
B31 - - DCI[0]:TEST_ENABLE DCI[0]:FORCE_DONE_HIGH
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - BSCAN:TDO_ENABLE[0] BSCAN:TDO_ENABLE[1]
B19 - - ~BSCAN:USERID[30] ~BSCAN:USERID[31]
B18 - - ~BSCAN:USERID[28] ~BSCAN:USERID[29]
B17 - - ~BSCAN:USERID[26] ~BSCAN:USERID[27]
B16 - - ~BSCAN:USERID[24] ~BSCAN:USERID[25]
B15 - - ~BSCAN:USERID[22] ~BSCAN:USERID[23]
B14 - - ~BSCAN:USERID[20] ~BSCAN:USERID[21]
B13 - - ~BSCAN:USERID[18] ~BSCAN:USERID[19]
B12 - - ~BSCAN:USERID[16] ~BSCAN:USERID[17]
B11 - - ~BSCAN:USERID[14] ~BSCAN:USERID[15]
B10 - - ~BSCAN:USERID[12] ~BSCAN:USERID[13]
B9 - - ~BSCAN:USERID[10] ~BSCAN:USERID[11]
B8 - - ~BSCAN:USERID[8] ~BSCAN:USERID[9]
B7 - - ~BSCAN:USERID[6] ~BSCAN:USERID[7]
B6 - - ~BSCAN:USERID[4] ~BSCAN:USERID[5]
B5 - - ~BSCAN:USERID[2] ~BSCAN:USERID[3]
B4 - - ~BSCAN:USERID[0] ~BSCAN:USERID[1]
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2 rect R1
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13
B11 - - - MISC:TDOPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[3] DCI[1]:PMASK_TERM_SPLIT[2] - DCI[1]:NMASK_TERM_SPLIT[0] DCI[1]:LVDSBIAS[4] DCI[1]:LVDSBIAS[7]
B10 - - - MISC:TCKPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[4] DCI[1]:PMASK_TERM_SPLIT[4] - DCI[1]:NMASK_TERM_SPLIT[2] DCI[1]:LVDSBIAS[3] -
B9 - - - MISC:TDOPIN[1] - - MISC:TEST_LL - DCI[1]:PMASK_TERM_SPLIT[0] DCI[1]:PMASK_TERM_SPLIT[1] - - DCI[1]:LVDSBIAS[5] DCI[1]:LVDSBIAS[6]
B8 - - - MISC:TMSPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[0] DCI[1]:FORCE_DONE_HIGH - DCI[1]:NMASK_TERM_SPLIT[3] DCI[1]:LVDSBIAS[0] -
B7 - - - MISC:TCKPIN[1] - - - - DCI[1]:PMASK_TERM_VCC[2] DCI[1]:PMASK_TERM_SPLIT[3] DCI[1]:ENABLE DCI[1]:NMASK_TERM_SPLIT[1] DCI[1]:LVDSBIAS[2] DCI[1]:LVDSBIAS[8]
B6 - - - MISC:TMSPIN[1] - - - - DCI[1]:PMASK_TERM_VCC[1] DCI[1]:TEST_ENABLE - DCI[1]:NMASK_TERM_SPLIT[4] DCI[1]:LVDSBIAS[1] -
B5 - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - -
BSCAN:TDO_ENABLE 0.F3.B20 0.F2.B20
non-inverted [1] [0]
BSCAN:USERID 0.F3.B19 0.F2.B19 0.F3.B18 0.F2.B18 0.F3.B17 0.F2.B17 0.F3.B16 0.F2.B16 0.F3.B15 0.F2.B15 0.F3.B14 0.F2.B14 0.F3.B13 0.F2.B13 0.F3.B12 0.F2.B12 0.F3.B11 0.F2.B11 0.F3.B10 0.F2.B10 0.F3.B9 0.F2.B9 0.F3.B8 0.F2.B8 0.F3.B7 0.F2.B7 0.F3.B6 0.F2.B6 0.F3.B5 0.F2.B5 0.F3.B4 0.F2.B4
inverted ~[31] ~[30] ~[29] ~[28] ~[27] ~[26] ~[25] ~[24] ~[23] ~[22] ~[21] ~[20] ~[19] ~[18] ~[17] ~[16] ~[15] ~[14] ~[13] ~[12] ~[11] ~[10] ~[9] ~[8] ~[7] ~[6] ~[5] ~[4] ~[3] ~[2] ~[1] ~[0]
DCI[0]:ENABLE 0.F2.B42
DCI[0]:FORCE_DONE_HIGH 0.F3.B31
DCI[0]:TEST_ENABLE 0.F2.B31
DCI[1]:ENABLE 1.F10.B7
DCI[1]:FORCE_DONE_HIGH 1.F9.B8
DCI[1]:TEST_ENABLE 1.F9.B6
MISC:TEST_LL 1.F6.B9
non-inverted [0]
DCI[0]:LVDSBIAS 0.F3.B44 0.F2.B45 0.F3.B45 0.F2.B46 0.F3.B46 0.F2.B47 0.F3.B47 0.F2.B48 0.F3.B48
DCI[1]:LVDSBIAS 1.F13.B7 1.F13.B11 1.F13.B9 1.F12.B9 1.F12.B11 1.F12.B10 1.F12.B7 1.F12.B6 1.F12.B8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI[0]:NMASK_TERM_SPLIT 0.F2.B37 0.F3.B37 0.F2.B38 0.F3.B38 0.F2.B39
DCI[0]:PMASK_TERM_SPLIT 0.F2.B32 0.F3.B32 0.F2.B33 0.F3.B33 0.F2.B34
DCI[0]:PMASK_TERM_VCC 0.F3.B34 0.F2.B35 0.F3.B35 0.F2.B36 0.F3.B36
DCI[1]:NMASK_TERM_SPLIT 1.F11.B6 1.F11.B8 1.F11.B10 1.F11.B7 1.F11.B11
DCI[1]:PMASK_TERM_SPLIT 1.F9.B10 1.F9.B7 1.F9.B11 1.F9.B9 1.F8.B9
DCI[1]:PMASK_TERM_VCC 1.F8.B10 1.F8.B11 1.F8.B7 1.F8.B6 1.F8.B8
non-inverted [4] [3] [2] [1] [0]
MISC:TCKPIN 1.F3.B7 1.F3.B10
MISC:TDOPIN 1.F3.B9 1.F3.B11
MISC:TMSPIN 1.F3.B6 1.F3.B8
PULLUP 0 0
PULLDOWN 0 1
PULLNONE 1 0

Tile CNR_NE_V2P

Cells: 1

Bel DCI[0]

virtex2 CNR_NE_V2P bel DCI[0]
PinDirectionWires
ADDRESS0outputOUT_HALF0[14]
ADDRESS1outputOUT_HALF1[14]
ADDRESS2outputOUT_HALF0[13]
DATAoutputOUT_HALF1[15]
DCI_CLKinputIMUX_G2_DATA[7]
DCI_DONEoutputOUT_HALF0[15]
DCI_RESETinputIMUX_G2_DATA[6]
HI_LO_NinputIMUX_G2_DATA[5]
HI_LO_PinputIMUX_G2_DATA[4]
N_OR_PoutputOUT_HALF1[16]
SCLKoutputOUT_HALF0[16]
UPDATEoutputOUT_HALF1[17]

Bel DCI[1]

virtex2 CNR_NE_V2P bel DCI[1]
PinDirectionWires
ADDRESS0outputOUT_HALF0[9]
ADDRESS1outputOUT_HALF1[9]
ADDRESS2outputOUT_HALF0[8]
DATAoutputOUT_HALF1[10]
DCI_CLKinputIMUX_G1_DATA[7]
DCI_DONEoutputOUT_HALF0[10]
DCI_RESETinputIMUX_G1_DATA[6]
HI_LO_NinputIMUX_G1_DATA[5]
HI_LO_PinputIMUX_G1_DATA[4]
N_OR_PoutputOUT_HALF1[11]
SCLKoutputOUT_HALF0[11]
UPDATEoutputOUT_HALF1[12]

Bel BSCAN

virtex2 CNR_NE_V2P bel BSCAN
PinDirectionWires
CAPTUREoutputOUT_FAN[7]
DRCK1outputOUT_FAN[0]
DRCK2outputOUT_FAN[1]
RESEToutputOUT_HALF0[17]
SEL1outputOUT_FAN[2]
SEL2outputOUT_FAN[3]
SHIFToutputOUT_FAN[4]
TDIoutputOUT_FAN[5]
TDO1inputIMUX_G0_DATA[0]
TDO2inputIMUX_G0_DATA[1]
UPDATEoutputOUT_FAN[6]

Bel JTAGPPC

virtex2 CNR_NE_V2P bel JTAGPPC
PinDirectionWires
TCKoutputOUT_HALF0[12]
TDIPPCoutputOUT_HALF1[8]
TDOPPCinputIMUX_G0_DATA[2]
TDOTSPPCinputIMUX_G0_DATA[3]
TMSoutputOUT_HALF1[13]

Bel wires

virtex2 CNR_NE_V2P bel wires
WirePins
IMUX_G0_DATA[0]BSCAN.TDO1
IMUX_G0_DATA[1]BSCAN.TDO2
IMUX_G0_DATA[2]JTAGPPC.TDOPPC
IMUX_G0_DATA[3]JTAGPPC.TDOTSPPC
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_FAN[0]BSCAN.DRCK1
OUT_FAN[1]BSCAN.DRCK2
OUT_FAN[2]BSCAN.SEL1
OUT_FAN[3]BSCAN.SEL2
OUT_FAN[4]BSCAN.SHIFT
OUT_FAN[5]BSCAN.TDI
OUT_FAN[6]BSCAN.UPDATE
OUT_FAN[7]BSCAN.CAPTURE
OUT_HALF0[8]DCI[1].ADDRESS2
OUT_HALF0[9]DCI[1].ADDRESS0
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[12]JTAGPPC.TCK
OUT_HALF0[13]DCI[0].ADDRESS2
OUT_HALF0[14]DCI[0].ADDRESS0
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF0[17]BSCAN.RESET
OUT_HALF1[8]JTAGPPC.TDIPPC
OUT_HALF1[9]DCI[1].ADDRESS1
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[13]JTAGPPC.TMS
OUT_HALF1[14]DCI[0].ADDRESS1
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_NE_V2P rect TERM_H
BitFrame
F0 F1 F2 F3
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2P rect TERM_V
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21
B11 - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -
### Bitstream
virtex2 CNR_NE_V2P rect R0
BitFrame
F0 F1 F2 F3
B48 - - DCI[0]:LVDSBIAS[1] DCI[0]:LVDSBIAS[0]
B47 - - DCI[0]:LVDSBIAS[3] DCI[0]:LVDSBIAS[2]
B46 - - DCI[0]:LVDSBIAS[5] DCI[0]:LVDSBIAS[4]
B45 - - DCI[0]:LVDSBIAS[7] DCI[0]:LVDSBIAS[6]
B44 - - - DCI[0]:LVDSBIAS[8]
B43 - - - -
B42 - - DCI[0]:ENABLE JTAGPPC:ENABLE
B41 - - - -
B40 - - - -
B39 - - DCI[0]:NMASK_TERM_SPLIT[0] DCI[0]:QUIET
B38 - - DCI[0]:NMASK_TERM_SPLIT[2] DCI[0]:NMASK_TERM_SPLIT[1]
B37 - - DCI[0]:NMASK_TERM_SPLIT[4] DCI[0]:NMASK_TERM_SPLIT[3]
B36 - - DCI[0]:PMASK_TERM_VCC[1] DCI[0]:PMASK_TERM_VCC[0]
B35 - - DCI[0]:PMASK_TERM_VCC[3] DCI[0]:PMASK_TERM_VCC[2]
B34 - - DCI[0]:PMASK_TERM_SPLIT[0] DCI[0]:PMASK_TERM_VCC[4]
B33 - - DCI[0]:PMASK_TERM_SPLIT[2] DCI[0]:PMASK_TERM_SPLIT[1]
B32 - - DCI[0]:PMASK_TERM_SPLIT[4] DCI[0]:PMASK_TERM_SPLIT[3]
B31 - - DCI[0]:TEST_ENABLE DCI[0]:FORCE_DONE_HIGH
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - BSCAN:TDO_ENABLE[0] BSCAN:TDO_ENABLE[1]
B19 - - ~BSCAN:USERID[30] ~BSCAN:USERID[31]
B18 - - ~BSCAN:USERID[28] ~BSCAN:USERID[29]
B17 - - ~BSCAN:USERID[26] ~BSCAN:USERID[27]
B16 - - ~BSCAN:USERID[24] ~BSCAN:USERID[25]
B15 - - ~BSCAN:USERID[22] ~BSCAN:USERID[23]
B14 - - ~BSCAN:USERID[20] ~BSCAN:USERID[21]
B13 - - ~BSCAN:USERID[18] ~BSCAN:USERID[19]
B12 - - ~BSCAN:USERID[16] ~BSCAN:USERID[17]
B11 - - ~BSCAN:USERID[14] ~BSCAN:USERID[15]
B10 - - ~BSCAN:USERID[12] ~BSCAN:USERID[13]
B9 - - ~BSCAN:USERID[10] ~BSCAN:USERID[11]
B8 - - ~BSCAN:USERID[8] ~BSCAN:USERID[9]
B7 - - ~BSCAN:USERID[6] ~BSCAN:USERID[7]
B6 - - ~BSCAN:USERID[4] ~BSCAN:USERID[5]
B5 - - ~BSCAN:USERID[2] ~BSCAN:USERID[3]
B4 - - ~BSCAN:USERID[0] ~BSCAN:USERID[1]
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2P rect R1
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13
B11 - - - MISC:TDOPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[3] DCI[1]:PMASK_TERM_SPLIT[2] - DCI[1]:NMASK_TERM_SPLIT[0] DCI[1]:LVDSBIAS[4] DCI[1]:LVDSBIAS[7]
B10 - - - MISC:TCKPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[4] DCI[1]:PMASK_TERM_SPLIT[4] - DCI[1]:NMASK_TERM_SPLIT[2] DCI[1]:LVDSBIAS[3] -
B9 - - - MISC:TDOPIN[1] - - MISC:TEST_LL - DCI[1]:PMASK_TERM_SPLIT[0] DCI[1]:PMASK_TERM_SPLIT[1] - DCI[1]:QUIET DCI[1]:LVDSBIAS[5] DCI[1]:LVDSBIAS[6]
B8 - - - MISC:TMSPIN[0] - - - - DCI[1]:PMASK_TERM_VCC[0] DCI[1]:FORCE_DONE_HIGH - DCI[1]:NMASK_TERM_SPLIT[3] DCI[1]:LVDSBIAS[0] -
B7 - - - MISC:TCKPIN[1] - - - - DCI[1]:PMASK_TERM_VCC[2] DCI[1]:PMASK_TERM_SPLIT[3] DCI[1]:ENABLE DCI[1]:NMASK_TERM_SPLIT[1] DCI[1]:LVDSBIAS[2] DCI[1]:LVDSBIAS[8]
B6 - - - MISC:TMSPIN[1] - - - - DCI[1]:PMASK_TERM_VCC[1] DCI[1]:TEST_ENABLE - DCI[1]:NMASK_TERM_SPLIT[4] DCI[1]:LVDSBIAS[1] -
B5 - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - -
BSCAN:TDO_ENABLE 0.F3.B20 0.F2.B20
non-inverted [1] [0]
BSCAN:USERID 0.F3.B19 0.F2.B19 0.F3.B18 0.F2.B18 0.F3.B17 0.F2.B17 0.F3.B16 0.F2.B16 0.F3.B15 0.F2.B15 0.F3.B14 0.F2.B14 0.F3.B13 0.F2.B13 0.F3.B12 0.F2.B12 0.F3.B11 0.F2.B11 0.F3.B10 0.F2.B10 0.F3.B9 0.F2.B9 0.F3.B8 0.F2.B8 0.F3.B7 0.F2.B7 0.F3.B6 0.F2.B6 0.F3.B5 0.F2.B5 0.F3.B4 0.F2.B4
inverted ~[31] ~[30] ~[29] ~[28] ~[27] ~[26] ~[25] ~[24] ~[23] ~[22] ~[21] ~[20] ~[19] ~[18] ~[17] ~[16] ~[15] ~[14] ~[13] ~[12] ~[11] ~[10] ~[9] ~[8] ~[7] ~[6] ~[5] ~[4] ~[3] ~[2] ~[1] ~[0]
DCI[0]:ENABLE 0.F2.B42
DCI[0]:FORCE_DONE_HIGH 0.F3.B31
DCI[0]:QUIET 0.F3.B39
DCI[0]:TEST_ENABLE 0.F2.B31
DCI[1]:ENABLE 1.F10.B7
DCI[1]:FORCE_DONE_HIGH 1.F9.B8
DCI[1]:QUIET 1.F11.B9
DCI[1]:TEST_ENABLE 1.F9.B6
JTAGPPC:ENABLE 0.F3.B42
MISC:TEST_LL 1.F6.B9
non-inverted [0]
DCI[0]:LVDSBIAS 0.F3.B44 0.F2.B45 0.F3.B45 0.F2.B46 0.F3.B46 0.F2.B47 0.F3.B47 0.F2.B48 0.F3.B48
DCI[1]:LVDSBIAS 1.F13.B7 1.F13.B11 1.F13.B9 1.F12.B9 1.F12.B11 1.F12.B10 1.F12.B7 1.F12.B6 1.F12.B8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI[0]:NMASK_TERM_SPLIT 0.F2.B37 0.F3.B37 0.F2.B38 0.F3.B38 0.F2.B39
DCI[0]:PMASK_TERM_SPLIT 0.F2.B32 0.F3.B32 0.F2.B33 0.F3.B33 0.F2.B34
DCI[0]:PMASK_TERM_VCC 0.F3.B34 0.F2.B35 0.F3.B35 0.F2.B36 0.F3.B36
DCI[1]:NMASK_TERM_SPLIT 1.F11.B6 1.F11.B8 1.F11.B10 1.F11.B7 1.F11.B11
DCI[1]:PMASK_TERM_SPLIT 1.F9.B10 1.F9.B7 1.F9.B11 1.F9.B9 1.F8.B9
DCI[1]:PMASK_TERM_VCC 1.F8.B10 1.F8.B11 1.F8.B7 1.F8.B6 1.F8.B8
non-inverted [4] [3] [2] [1] [0]
MISC:TCKPIN 1.F3.B7 1.F3.B10
MISC:TDOPIN 1.F3.B9 1.F3.B11
MISC:TMSPIN 1.F3.B6 1.F3.B8
PULLUP 0 0
PULLDOWN 0 1
PULLNONE 1 0