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Northeast

TODO: document

Tile CNR_NE_V2

Cells: 1

Bels DCI

virtex2 CNR_NE_V2 bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_G2_DATA[7]IMUX_G1_DATA[7]
DCI_RESETinIMUX_G2_DATA[6]IMUX_G1_DATA[6]
HI_LO_PinIMUX_G2_DATA[4]IMUX_G1_DATA[4]
HI_LO_NinIMUX_G2_DATA[5]IMUX_G1_DATA[5]
SCLKoutOUT_HALF0[16]OUT_HALF0[11]
ADDRESS[0]outOUT_HALF0[14]OUT_HALF0[9]
ADDRESS[1]outOUT_HALF1[14]OUT_HALF1[9]
ADDRESS[2]outOUT_HALF0[13]OUT_HALF0[8]
DATAoutOUT_HALF1[15]OUT_HALF1[10]
N_OR_PoutOUT_HALF1[16]OUT_HALF1[11]
UPDATEoutOUT_HALF1[17]OUT_HALF1[12]
DCI_DONEoutOUT_HALF0[15]OUT_HALF0[10]
virtex2 CNR_NE_V2 bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[2][42]TERM_V[10][7]
TEST_ENABLETERM_H[2][31]TERM_V[9][6]
FORCE_DONE_HIGHTERM_H[3][31]TERM_V[9][8]
V2_PMASK_TERM_SPLIT bit 0TERM_H[2][34]TERM_V[8][9]
V2_PMASK_TERM_SPLIT bit 1TERM_H[3][33]TERM_V[9][9]
V2_PMASK_TERM_SPLIT bit 2TERM_H[2][33]TERM_V[9][11]
V2_PMASK_TERM_SPLIT bit 3TERM_H[3][32]TERM_V[9][7]
V2_PMASK_TERM_SPLIT bit 4TERM_H[2][32]TERM_V[9][10]
V2_NMASK_TERM_SPLIT bit 0TERM_H[2][39]TERM_V[11][11]
V2_NMASK_TERM_SPLIT bit 1TERM_H[3][38]TERM_V[11][7]
V2_NMASK_TERM_SPLIT bit 2TERM_H[2][38]TERM_V[11][10]
V2_NMASK_TERM_SPLIT bit 3TERM_H[3][37]TERM_V[11][8]
V2_NMASK_TERM_SPLIT bit 4TERM_H[2][37]TERM_V[11][6]
V2_PMASK_TERM_VCC bit 0TERM_H[3][36]TERM_V[8][8]
V2_PMASK_TERM_VCC bit 1TERM_H[2][36]TERM_V[8][6]
V2_PMASK_TERM_VCC bit 2TERM_H[3][35]TERM_V[8][7]
V2_PMASK_TERM_VCC bit 3TERM_H[2][35]TERM_V[8][11]
V2_PMASK_TERM_VCC bit 4TERM_H[3][34]TERM_V[8][10]
V2_LVDSBIAS bit 0TERM_H[3][48]TERM_V[12][8]
V2_LVDSBIAS bit 1TERM_H[2][48]TERM_V[12][6]
V2_LVDSBIAS bit 2TERM_H[3][47]TERM_V[12][7]
V2_LVDSBIAS bit 3TERM_H[2][47]TERM_V[12][10]
V2_LVDSBIAS bit 4TERM_H[3][46]TERM_V[12][11]
V2_LVDSBIAS bit 5TERM_H[2][46]TERM_V[12][9]
V2_LVDSBIAS bit 6TERM_H[3][45]TERM_V[13][9]
V2_LVDSBIAS bit 7TERM_H[2][45]TERM_V[13][11]
V2_LVDSBIAS bit 8TERM_H[3][44]TERM_V[13][7]

Bels BSCAN

virtex2 CNR_NE_V2 bel BSCAN pins
PinDirectionBSCAN
TDO1inIMUX_G0_DATA[0]
TDO2inIMUX_G0_DATA[1]
DRCK1outOUT_FAN[0]
DRCK2outOUT_FAN[1]
SEL1outOUT_FAN[2]
SEL2outOUT_FAN[3]
TDIoutOUT_FAN[5]
RESEToutOUT_HALF0[17]
CAPTUREoutOUT_FAN[7]
SHIFToutOUT_FAN[4]
UPDATEoutOUT_FAN[6]
virtex2 CNR_NE_V2 bel BSCAN attribute bits
AttributeBSCAN
USER_TDO_ENABLE bit 0TERM_H[2][20]
USER_TDO_ENABLE bit 1TERM_H[3][20]
USERCODE bit 0!TERM_H[2][4]
USERCODE bit 1!TERM_H[3][4]
USERCODE bit 2!TERM_H[2][5]
USERCODE bit 3!TERM_H[3][5]
USERCODE bit 4!TERM_H[2][6]
USERCODE bit 5!TERM_H[3][6]
USERCODE bit 6!TERM_H[2][7]
USERCODE bit 7!TERM_H[3][7]
USERCODE bit 8!TERM_H[2][8]
USERCODE bit 9!TERM_H[3][8]
USERCODE bit 10!TERM_H[2][9]
USERCODE bit 11!TERM_H[3][9]
USERCODE bit 12!TERM_H[2][10]
USERCODE bit 13!TERM_H[3][10]
USERCODE bit 14!TERM_H[2][11]
USERCODE bit 15!TERM_H[3][11]
USERCODE bit 16!TERM_H[2][12]
USERCODE bit 17!TERM_H[3][12]
USERCODE bit 18!TERM_H[2][13]
USERCODE bit 19!TERM_H[3][13]
USERCODE bit 20!TERM_H[2][14]
USERCODE bit 21!TERM_H[3][14]
USERCODE bit 22!TERM_H[2][15]
USERCODE bit 23!TERM_H[3][15]
USERCODE bit 24!TERM_H[2][16]
USERCODE bit 25!TERM_H[3][16]
USERCODE bit 26!TERM_H[2][17]
USERCODE bit 27!TERM_H[3][17]
USERCODE bit 28!TERM_H[2][18]
USERCODE bit 29!TERM_H[3][18]
USERCODE bit 30!TERM_H[2][19]
USERCODE bit 31!TERM_H[3][19]

Bels MISC_NE

virtex2 CNR_NE_V2 bel MISC_NE pins
PinDirectionMISC_NE
virtex2 CNR_NE_V2 bel MISC_NE attribute bits
AttributeMISC_NE
TCK_PULL[enum: IOB_PULL]
TMS_PULL[enum: IOB_PULL]
TDO_PULL[enum: IOB_PULL]
TEST_LLTERM_V[6][9]
virtex2 CNR_NE_V2 enum IOB_PULL
MISC_NE.TCK_PULLTERM_V[3][10]TERM_V[3][7]
MISC_NE.TMS_PULLTERM_V[3][8]TERM_V[3][6]
MISC_NE.TDO_PULLTERM_V[3][11]TERM_V[3][9]
NONE01
PULLUP00
PULLDOWN10

Bel wires

virtex2 CNR_NE_V2 bel wires
WirePins
IMUX_G0_DATA[0]BSCAN.TDO1
IMUX_G0_DATA[1]BSCAN.TDO2
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_FAN[0]BSCAN.DRCK1
OUT_FAN[1]BSCAN.DRCK2
OUT_FAN[2]BSCAN.SEL1
OUT_FAN[3]BSCAN.SEL2
OUT_FAN[4]BSCAN.SHIFT
OUT_FAN[5]BSCAN.TDI
OUT_FAN[6]BSCAN.UPDATE
OUT_FAN[7]BSCAN.CAPTURE
OUT_HALF0[8]DCI[1].ADDRESS[2]
OUT_HALF0[9]DCI[1].ADDRESS[0]
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[13]DCI[0].ADDRESS[2]
OUT_HALF0[14]DCI[0].ADDRESS[0]
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF0[17]BSCAN.RESET
OUT_HALF1[9]DCI[1].ADDRESS[1]
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[14]DCI[0].ADDRESS[1]
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_NE_V2 rect TERM_H
BitFrame
F3 F2 F1 F0
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 DCI[0]: V2_LVDSBIAS bit 0 DCI[0]: V2_LVDSBIAS bit 1 - -
B47 DCI[0]: V2_LVDSBIAS bit 2 DCI[0]: V2_LVDSBIAS bit 3 - -
B46 DCI[0]: V2_LVDSBIAS bit 4 DCI[0]: V2_LVDSBIAS bit 5 - -
B45 DCI[0]: V2_LVDSBIAS bit 6 DCI[0]: V2_LVDSBIAS bit 7 - -
B44 DCI[0]: V2_LVDSBIAS bit 8 - - -
B43 - - - -
B42 - DCI[0]: ENABLE - -
B41 - - - -
B40 - - - -
B39 - DCI[0]: V2_NMASK_TERM_SPLIT bit 0 - -
B38 DCI[0]: V2_NMASK_TERM_SPLIT bit 1 DCI[0]: V2_NMASK_TERM_SPLIT bit 2 - -
B37 DCI[0]: V2_NMASK_TERM_SPLIT bit 3 DCI[0]: V2_NMASK_TERM_SPLIT bit 4 - -
B36 DCI[0]: V2_PMASK_TERM_VCC bit 0 DCI[0]: V2_PMASK_TERM_VCC bit 1 - -
B35 DCI[0]: V2_PMASK_TERM_VCC bit 2 DCI[0]: V2_PMASK_TERM_VCC bit 3 - -
B34 DCI[0]: V2_PMASK_TERM_VCC bit 4 DCI[0]: V2_PMASK_TERM_SPLIT bit 0 - -
B33 DCI[0]: V2_PMASK_TERM_SPLIT bit 1 DCI[0]: V2_PMASK_TERM_SPLIT bit 2 - -
B32 DCI[0]: V2_PMASK_TERM_SPLIT bit 3 DCI[0]: V2_PMASK_TERM_SPLIT bit 4 - -
B31 DCI[0]: FORCE_DONE_HIGH DCI[0]: TEST_ENABLE - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 BSCAN: USER_TDO_ENABLE bit 1 BSCAN: USER_TDO_ENABLE bit 0 - -
B19 BSCAN: ! USERCODE bit 31 BSCAN: ! USERCODE bit 30 - -
B18 BSCAN: ! USERCODE bit 29 BSCAN: ! USERCODE bit 28 - -
B17 BSCAN: ! USERCODE bit 27 BSCAN: ! USERCODE bit 26 - -
B16 BSCAN: ! USERCODE bit 25 BSCAN: ! USERCODE bit 24 - -
B15 BSCAN: ! USERCODE bit 23 BSCAN: ! USERCODE bit 22 - -
B14 BSCAN: ! USERCODE bit 21 BSCAN: ! USERCODE bit 20 - -
B13 BSCAN: ! USERCODE bit 19 BSCAN: ! USERCODE bit 18 - -
B12 BSCAN: ! USERCODE bit 17 BSCAN: ! USERCODE bit 16 - -
B11 BSCAN: ! USERCODE bit 15 BSCAN: ! USERCODE bit 14 - -
B10 BSCAN: ! USERCODE bit 13 BSCAN: ! USERCODE bit 12 - -
B9 BSCAN: ! USERCODE bit 11 BSCAN: ! USERCODE bit 10 - -
B8 BSCAN: ! USERCODE bit 9 BSCAN: ! USERCODE bit 8 - -
B7 BSCAN: ! USERCODE bit 7 BSCAN: ! USERCODE bit 6 - -
B6 BSCAN: ! USERCODE bit 5 BSCAN: ! USERCODE bit 4 - -
B5 BSCAN: ! USERCODE bit 3 BSCAN: ! USERCODE bit 2 - -
B4 BSCAN: ! USERCODE bit 1 BSCAN: ! USERCODE bit 0 - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2 rect TERM_V
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 7 DCI[1]: V2_LVDSBIAS bit 4 DCI[1]: V2_NMASK_TERM_SPLIT bit 0 - DCI[1]: V2_PMASK_TERM_SPLIT bit 2 DCI[1]: V2_PMASK_TERM_VCC bit 3 - - - - MISC_NE: TDO_PULL bit 1 - - -
B10 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 3 DCI[1]: V2_NMASK_TERM_SPLIT bit 2 - DCI[1]: V2_PMASK_TERM_SPLIT bit 4 DCI[1]: V2_PMASK_TERM_VCC bit 4 - - - - MISC_NE: TCK_PULL bit 1 - - -
B9 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 6 DCI[1]: V2_LVDSBIAS bit 5 - - DCI[1]: V2_PMASK_TERM_SPLIT bit 1 DCI[1]: V2_PMASK_TERM_SPLIT bit 0 - MISC_NE: TEST_LL - - MISC_NE: TDO_PULL bit 0 - - -
B8 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 0 DCI[1]: V2_NMASK_TERM_SPLIT bit 3 - DCI[1]: FORCE_DONE_HIGH DCI[1]: V2_PMASK_TERM_VCC bit 0 - - - - MISC_NE: TMS_PULL bit 1 - - -
B7 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 8 DCI[1]: V2_LVDSBIAS bit 2 DCI[1]: V2_NMASK_TERM_SPLIT bit 1 DCI[1]: ENABLE DCI[1]: V2_PMASK_TERM_SPLIT bit 3 DCI[1]: V2_PMASK_TERM_VCC bit 2 - - - - MISC_NE: TCK_PULL bit 0 - - -
B6 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 1 DCI[1]: V2_NMASK_TERM_SPLIT bit 4 - DCI[1]: TEST_ENABLE DCI[1]: V2_PMASK_TERM_VCC bit 1 - - - - MISC_NE: TMS_PULL bit 0 - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -

Tile CNR_NE_V2P

Cells: 1

Bels DCI

virtex2 CNR_NE_V2P bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_G2_DATA[7]IMUX_G1_DATA[7]
DCI_RESETinIMUX_G2_DATA[6]IMUX_G1_DATA[6]
HI_LO_PinIMUX_G2_DATA[4]IMUX_G1_DATA[4]
HI_LO_NinIMUX_G2_DATA[5]IMUX_G1_DATA[5]
SCLKoutOUT_HALF0[16]OUT_HALF0[11]
ADDRESS[0]outOUT_HALF0[14]OUT_HALF0[9]
ADDRESS[1]outOUT_HALF1[14]OUT_HALF1[9]
ADDRESS[2]outOUT_HALF0[13]OUT_HALF0[8]
DATAoutOUT_HALF1[15]OUT_HALF1[10]
N_OR_PoutOUT_HALF1[16]OUT_HALF1[11]
UPDATEoutOUT_HALF1[17]OUT_HALF1[12]
DCI_DONEoutOUT_HALF0[15]OUT_HALF0[10]
virtex2 CNR_NE_V2P bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[2][42]TERM_V[10][7]
TEST_ENABLETERM_H[2][31]TERM_V[9][6]
FORCE_DONE_HIGHTERM_H[3][31]TERM_V[9][8]
V2_PMASK_TERM_SPLIT bit 0TERM_H[2][34]TERM_V[8][9]
V2_PMASK_TERM_SPLIT bit 1TERM_H[3][33]TERM_V[9][9]
V2_PMASK_TERM_SPLIT bit 2TERM_H[2][33]TERM_V[9][11]
V2_PMASK_TERM_SPLIT bit 3TERM_H[3][32]TERM_V[9][7]
V2_PMASK_TERM_SPLIT bit 4TERM_H[2][32]TERM_V[9][10]
V2_NMASK_TERM_SPLIT bit 0TERM_H[2][39]TERM_V[11][11]
V2_NMASK_TERM_SPLIT bit 1TERM_H[3][38]TERM_V[11][7]
V2_NMASK_TERM_SPLIT bit 2TERM_H[2][38]TERM_V[11][10]
V2_NMASK_TERM_SPLIT bit 3TERM_H[3][37]TERM_V[11][8]
V2_NMASK_TERM_SPLIT bit 4TERM_H[2][37]TERM_V[11][6]
V2_PMASK_TERM_VCC bit 0TERM_H[3][36]TERM_V[8][8]
V2_PMASK_TERM_VCC bit 1TERM_H[2][36]TERM_V[8][6]
V2_PMASK_TERM_VCC bit 2TERM_H[3][35]TERM_V[8][7]
V2_PMASK_TERM_VCC bit 3TERM_H[2][35]TERM_V[8][11]
V2_PMASK_TERM_VCC bit 4TERM_H[3][34]TERM_V[8][10]
V2_LVDSBIAS bit 0TERM_H[3][48]TERM_V[12][8]
V2_LVDSBIAS bit 1TERM_H[2][48]TERM_V[12][6]
V2_LVDSBIAS bit 2TERM_H[3][47]TERM_V[12][7]
V2_LVDSBIAS bit 3TERM_H[2][47]TERM_V[12][10]
V2_LVDSBIAS bit 4TERM_H[3][46]TERM_V[12][11]
V2_LVDSBIAS bit 5TERM_H[2][46]TERM_V[12][9]
V2_LVDSBIAS bit 6TERM_H[3][45]TERM_V[13][9]
V2_LVDSBIAS bit 7TERM_H[2][45]TERM_V[13][11]
V2_LVDSBIAS bit 8TERM_H[3][44]TERM_V[13][7]
QUIETTERM_H[3][39]TERM_V[11][9]

Bels BSCAN

virtex2 CNR_NE_V2P bel BSCAN pins
PinDirectionBSCAN
TDO1inIMUX_G0_DATA[0]
TDO2inIMUX_G0_DATA[1]
DRCK1outOUT_FAN[0]
DRCK2outOUT_FAN[1]
SEL1outOUT_FAN[2]
SEL2outOUT_FAN[3]
TDIoutOUT_FAN[5]
RESEToutOUT_HALF0[17]
CAPTUREoutOUT_FAN[7]
SHIFToutOUT_FAN[4]
UPDATEoutOUT_FAN[6]
virtex2 CNR_NE_V2P bel BSCAN attribute bits
AttributeBSCAN
USER_TDO_ENABLE bit 0TERM_H[2][20]
USER_TDO_ENABLE bit 1TERM_H[3][20]
USERCODE bit 0!TERM_H[2][4]
USERCODE bit 1!TERM_H[3][4]
USERCODE bit 2!TERM_H[2][5]
USERCODE bit 3!TERM_H[3][5]
USERCODE bit 4!TERM_H[2][6]
USERCODE bit 5!TERM_H[3][6]
USERCODE bit 6!TERM_H[2][7]
USERCODE bit 7!TERM_H[3][7]
USERCODE bit 8!TERM_H[2][8]
USERCODE bit 9!TERM_H[3][8]
USERCODE bit 10!TERM_H[2][9]
USERCODE bit 11!TERM_H[3][9]
USERCODE bit 12!TERM_H[2][10]
USERCODE bit 13!TERM_H[3][10]
USERCODE bit 14!TERM_H[2][11]
USERCODE bit 15!TERM_H[3][11]
USERCODE bit 16!TERM_H[2][12]
USERCODE bit 17!TERM_H[3][12]
USERCODE bit 18!TERM_H[2][13]
USERCODE bit 19!TERM_H[3][13]
USERCODE bit 20!TERM_H[2][14]
USERCODE bit 21!TERM_H[3][14]
USERCODE bit 22!TERM_H[2][15]
USERCODE bit 23!TERM_H[3][15]
USERCODE bit 24!TERM_H[2][16]
USERCODE bit 25!TERM_H[3][16]
USERCODE bit 26!TERM_H[2][17]
USERCODE bit 27!TERM_H[3][17]
USERCODE bit 28!TERM_H[2][18]
USERCODE bit 29!TERM_H[3][18]
USERCODE bit 30!TERM_H[2][19]
USERCODE bit 31!TERM_H[3][19]

Bels JTAGPPC

virtex2 CNR_NE_V2P bel JTAGPPC pins
PinDirectionJTAGPPC
TDOPPCinIMUX_G0_DATA[2]
TDOTSPPCinIMUX_G0_DATA[3]
TCKoutOUT_HALF0[12]
TMSoutOUT_HALF1[13]
TDIPPCoutOUT_HALF1[8]
virtex2 CNR_NE_V2P bel JTAGPPC attribute bits
AttributeJTAGPPC
ENABLETERM_H[3][42]

Bels MISC_NE

virtex2 CNR_NE_V2P bel MISC_NE pins
PinDirectionMISC_NE
virtex2 CNR_NE_V2P bel MISC_NE attribute bits
AttributeMISC_NE
TCK_PULL[enum: IOB_PULL]
TMS_PULL[enum: IOB_PULL]
TDO_PULL[enum: IOB_PULL]
TEST_LLTERM_V[6][9]
virtex2 CNR_NE_V2P enum IOB_PULL
MISC_NE.TCK_PULLTERM_V[3][10]TERM_V[3][7]
MISC_NE.TMS_PULLTERM_V[3][8]TERM_V[3][6]
MISC_NE.TDO_PULLTERM_V[3][11]TERM_V[3][9]
NONE01
PULLUP00
PULLDOWN10

Bel wires

virtex2 CNR_NE_V2P bel wires
WirePins
IMUX_G0_DATA[0]BSCAN.TDO1
IMUX_G0_DATA[1]BSCAN.TDO2
IMUX_G0_DATA[2]JTAGPPC.TDOPPC
IMUX_G0_DATA[3]JTAGPPC.TDOTSPPC
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_FAN[0]BSCAN.DRCK1
OUT_FAN[1]BSCAN.DRCK2
OUT_FAN[2]BSCAN.SEL1
OUT_FAN[3]BSCAN.SEL2
OUT_FAN[4]BSCAN.SHIFT
OUT_FAN[5]BSCAN.TDI
OUT_FAN[6]BSCAN.UPDATE
OUT_FAN[7]BSCAN.CAPTURE
OUT_HALF0[8]DCI[1].ADDRESS[2]
OUT_HALF0[9]DCI[1].ADDRESS[0]
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[12]JTAGPPC.TCK
OUT_HALF0[13]DCI[0].ADDRESS[2]
OUT_HALF0[14]DCI[0].ADDRESS[0]
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF0[17]BSCAN.RESET
OUT_HALF1[8]JTAGPPC.TDIPPC
OUT_HALF1[9]DCI[1].ADDRESS[1]
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[13]JTAGPPC.TMS
OUT_HALF1[14]DCI[0].ADDRESS[1]
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_NE_V2P rect TERM_H
BitFrame
F3 F2 F1 F0
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 DCI[0]: V2_LVDSBIAS bit 0 DCI[0]: V2_LVDSBIAS bit 1 - -
B47 DCI[0]: V2_LVDSBIAS bit 2 DCI[0]: V2_LVDSBIAS bit 3 - -
B46 DCI[0]: V2_LVDSBIAS bit 4 DCI[0]: V2_LVDSBIAS bit 5 - -
B45 DCI[0]: V2_LVDSBIAS bit 6 DCI[0]: V2_LVDSBIAS bit 7 - -
B44 DCI[0]: V2_LVDSBIAS bit 8 - - -
B43 - - - -
B42 JTAGPPC: ENABLE DCI[0]: ENABLE - -
B41 - - - -
B40 - - - -
B39 DCI[0]: QUIET DCI[0]: V2_NMASK_TERM_SPLIT bit 0 - -
B38 DCI[0]: V2_NMASK_TERM_SPLIT bit 1 DCI[0]: V2_NMASK_TERM_SPLIT bit 2 - -
B37 DCI[0]: V2_NMASK_TERM_SPLIT bit 3 DCI[0]: V2_NMASK_TERM_SPLIT bit 4 - -
B36 DCI[0]: V2_PMASK_TERM_VCC bit 0 DCI[0]: V2_PMASK_TERM_VCC bit 1 - -
B35 DCI[0]: V2_PMASK_TERM_VCC bit 2 DCI[0]: V2_PMASK_TERM_VCC bit 3 - -
B34 DCI[0]: V2_PMASK_TERM_VCC bit 4 DCI[0]: V2_PMASK_TERM_SPLIT bit 0 - -
B33 DCI[0]: V2_PMASK_TERM_SPLIT bit 1 DCI[0]: V2_PMASK_TERM_SPLIT bit 2 - -
B32 DCI[0]: V2_PMASK_TERM_SPLIT bit 3 DCI[0]: V2_PMASK_TERM_SPLIT bit 4 - -
B31 DCI[0]: FORCE_DONE_HIGH DCI[0]: TEST_ENABLE - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 BSCAN: USER_TDO_ENABLE bit 1 BSCAN: USER_TDO_ENABLE bit 0 - -
B19 BSCAN: ! USERCODE bit 31 BSCAN: ! USERCODE bit 30 - -
B18 BSCAN: ! USERCODE bit 29 BSCAN: ! USERCODE bit 28 - -
B17 BSCAN: ! USERCODE bit 27 BSCAN: ! USERCODE bit 26 - -
B16 BSCAN: ! USERCODE bit 25 BSCAN: ! USERCODE bit 24 - -
B15 BSCAN: ! USERCODE bit 23 BSCAN: ! USERCODE bit 22 - -
B14 BSCAN: ! USERCODE bit 21 BSCAN: ! USERCODE bit 20 - -
B13 BSCAN: ! USERCODE bit 19 BSCAN: ! USERCODE bit 18 - -
B12 BSCAN: ! USERCODE bit 17 BSCAN: ! USERCODE bit 16 - -
B11 BSCAN: ! USERCODE bit 15 BSCAN: ! USERCODE bit 14 - -
B10 BSCAN: ! USERCODE bit 13 BSCAN: ! USERCODE bit 12 - -
B9 BSCAN: ! USERCODE bit 11 BSCAN: ! USERCODE bit 10 - -
B8 BSCAN: ! USERCODE bit 9 BSCAN: ! USERCODE bit 8 - -
B7 BSCAN: ! USERCODE bit 7 BSCAN: ! USERCODE bit 6 - -
B6 BSCAN: ! USERCODE bit 5 BSCAN: ! USERCODE bit 4 - -
B5 BSCAN: ! USERCODE bit 3 BSCAN: ! USERCODE bit 2 - -
B4 BSCAN: ! USERCODE bit 1 BSCAN: ! USERCODE bit 0 - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_NE_V2P rect TERM_V
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 7 DCI[1]: V2_LVDSBIAS bit 4 DCI[1]: V2_NMASK_TERM_SPLIT bit 0 - DCI[1]: V2_PMASK_TERM_SPLIT bit 2 DCI[1]: V2_PMASK_TERM_VCC bit 3 - - - - MISC_NE: TDO_PULL bit 1 - - -
B10 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 3 DCI[1]: V2_NMASK_TERM_SPLIT bit 2 - DCI[1]: V2_PMASK_TERM_SPLIT bit 4 DCI[1]: V2_PMASK_TERM_VCC bit 4 - - - - MISC_NE: TCK_PULL bit 1 - - -
B9 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 6 DCI[1]: V2_LVDSBIAS bit 5 DCI[1]: QUIET - DCI[1]: V2_PMASK_TERM_SPLIT bit 1 DCI[1]: V2_PMASK_TERM_SPLIT bit 0 - MISC_NE: TEST_LL - - MISC_NE: TDO_PULL bit 0 - - -
B8 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 0 DCI[1]: V2_NMASK_TERM_SPLIT bit 3 - DCI[1]: FORCE_DONE_HIGH DCI[1]: V2_PMASK_TERM_VCC bit 0 - - - - MISC_NE: TMS_PULL bit 1 - - -
B7 - - - - - - - - DCI[1]: V2_LVDSBIAS bit 8 DCI[1]: V2_LVDSBIAS bit 2 DCI[1]: V2_NMASK_TERM_SPLIT bit 1 DCI[1]: ENABLE DCI[1]: V2_PMASK_TERM_SPLIT bit 3 DCI[1]: V2_PMASK_TERM_VCC bit 2 - - - - MISC_NE: TCK_PULL bit 0 - - -
B6 - - - - - - - - - DCI[1]: V2_LVDSBIAS bit 1 DCI[1]: V2_NMASK_TERM_SPLIT bit 4 - DCI[1]: TEST_ENABLE DCI[1]: V2_PMASK_TERM_VCC bit 1 - - - - MISC_NE: TMS_PULL bit 0 - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -