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TODO: document

Tile LR.V2

Cells: 1 IRIs: 0

Bel DCI0

virtex2 LR.V2 bel DCI0
PinDirectionWires
ADDRESS0outputOUT.HALF14.0
ADDRESS1outputOUT.HALF14.1
ADDRESS2outputOUT.HALF13.0
DATAoutputOUT.HALF15.1
DCI_CLKinputIMUX.G2.DATA7
DCI_DONEoutputOUT.HALF15.0
DCI_RESETinputIMUX.G2.DATA6
HI_LO_NinputIMUX.G2.DATA5
HI_LO_PinputIMUX.G2.DATA4
N_OR_PoutputOUT.HALF16.1
SCLKoutputOUT.HALF16.0
UPDATEoutputOUT.HALF17.1

Bel DCI1

virtex2 LR.V2 bel DCI1
PinDirectionWires
ADDRESS0outputOUT.HALF9.0
ADDRESS1outputOUT.HALF9.1
ADDRESS2outputOUT.HALF8.0
DATAoutputOUT.HALF10.1
DCI_CLKinputIMUX.G1.DATA7
DCI_DONEoutputOUT.HALF10.0
DCI_RESETinputIMUX.G1.DATA6
HI_LO_NinputIMUX.G1.DATA5
HI_LO_PinputIMUX.G1.DATA4
N_OR_PoutputOUT.HALF11.1
SCLKoutputOUT.HALF11.0
UPDATEoutputOUT.HALF12.1

Bel STARTUP

virtex2 LR.V2 bel STARTUP
PinDirectionWires
CLKinputIMUX.CLK0
GSRinputIMUX.SR0
GTSinputIMUX.TS0

Bel CAPTURE

virtex2 LR.V2 bel CAPTURE
PinDirectionWires
CAPinputIMUX.SR1
CLKinputIMUX.CLK2

Bel ICAP

virtex2 LR.V2 bel ICAP
PinDirectionWires
BUSYoutputOUT.HALF17.0
CEinputIMUX.CE1
CLKinputIMUX.CLK1
I0inputIMUX.G0.DATA0
I1inputIMUX.G0.DATA1
I2inputIMUX.G0.DATA2
I3inputIMUX.G0.DATA3
I4inputIMUX.G0.DATA4
I5inputIMUX.G0.DATA5
I6inputIMUX.G0.DATA6
I7inputIMUX.G0.DATA7
O0outputOUT.FAN0
O1outputOUT.FAN1
O2outputOUT.FAN2
O3outputOUT.FAN3
O4outputOUT.FAN4
O5outputOUT.FAN5
O6outputOUT.FAN6
O7outputOUT.FAN7
WRITEinputIMUX.TI0

Bel wires

virtex2 LR.V2 bel wires
WirePins
IMUX.CLK0STARTUP.CLK
IMUX.CLK1ICAP.CLK
IMUX.CLK2CAPTURE.CLK
IMUX.SR0STARTUP.GSR
IMUX.SR1CAPTURE.CAP
IMUX.CE1ICAP.CE
IMUX.TI0ICAP.WRITE
IMUX.TS0STARTUP.GTS
IMUX.G0.DATA0ICAP.I0
IMUX.G0.DATA1ICAP.I1
IMUX.G0.DATA2ICAP.I2
IMUX.G0.DATA3ICAP.I3
IMUX.G0.DATA4ICAP.I4
IMUX.G0.DATA5ICAP.I5
IMUX.G0.DATA6ICAP.I6
IMUX.G0.DATA7ICAP.I7
IMUX.G1.DATA4DCI1.HI_LO_P
IMUX.G1.DATA5DCI1.HI_LO_N
IMUX.G1.DATA6DCI1.DCI_RESET
IMUX.G1.DATA7DCI1.DCI_CLK
IMUX.G2.DATA4DCI0.HI_LO_P
IMUX.G2.DATA5DCI0.HI_LO_N
IMUX.G2.DATA6DCI0.DCI_RESET
IMUX.G2.DATA7DCI0.DCI_CLK
OUT.FAN0ICAP.O0
OUT.FAN1ICAP.O1
OUT.FAN2ICAP.O2
OUT.FAN3ICAP.O3
OUT.FAN4ICAP.O4
OUT.FAN5ICAP.O5
OUT.FAN6ICAP.O6
OUT.FAN7ICAP.O7
OUT.HALF8.0DCI1.ADDRESS2
OUT.HALF9.0DCI1.ADDRESS0
OUT.HALF9.1DCI1.ADDRESS1
OUT.HALF10.0DCI1.DCI_DONE
OUT.HALF10.1DCI1.DATA
OUT.HALF11.0DCI1.SCLK
OUT.HALF11.1DCI1.N_OR_P
OUT.HALF12.1DCI1.UPDATE
OUT.HALF13.0DCI0.ADDRESS2
OUT.HALF14.0DCI0.ADDRESS0
OUT.HALF14.1DCI0.ADDRESS1
OUT.HALF15.0DCI0.DCI_DONE
OUT.HALF15.1DCI0.DATA
OUT.HALF16.0DCI0.SCLK
OUT.HALF16.1DCI0.N_OR_P
OUT.HALF17.0ICAP.BUSY
OUT.HALF17.1DCI0.UPDATE

Bitstream

virtex2 LR.V2 bittile 0
BitFrame
0 1 2 3
48 - - DCI0:LVDSBIAS[1] DCI0:LVDSBIAS[0]
47 - - DCI0:LVDSBIAS[3] DCI0:LVDSBIAS[2]
46 - - DCI0:LVDSBIAS[5] DCI0:LVDSBIAS[4]
45 - - DCI0:LVDSBIAS[7] DCI0:LVDSBIAS[6]
44 - - - DCI0:LVDSBIAS[8]
43 - - - -
42 - - DCI0:ENABLE -
41 - - - -
40 - - - -
39 - - DCI0:NMASK_TERM_SPLIT[0] -
38 - - DCI0:NMASK_TERM_SPLIT[2] DCI0:NMASK_TERM_SPLIT[1]
37 - - DCI0:NMASK_TERM_SPLIT[4] DCI0:NMASK_TERM_SPLIT[3]
36 - - DCI0:PMASK_TERM_VCC[1] DCI0:PMASK_TERM_VCC[0]
35 - - DCI0:PMASK_TERM_VCC[3] DCI0:PMASK_TERM_VCC[2]
34 - - DCI0:PMASK_TERM_SPLIT[0] DCI0:PMASK_TERM_VCC[4]
33 - - DCI0:PMASK_TERM_SPLIT[2] DCI0:PMASK_TERM_SPLIT[1]
32 - - DCI0:PMASK_TERM_SPLIT[4] DCI0:PMASK_TERM_SPLIT[3]
31 - - DCI0:TEST_ENABLE DCI0:FORCE_DONE_HIGH
30 - - - -
29 - - - -
28 - - - -
27 - - - -
26 - - - -
25 - - - -
24 - - - -
23 - - - -
22 - - - -
21 - - - -
20 - - - -
19 - - - -
18 - - - -
17 - - - -
16 - - - -
15 - - - -
14 - - - -
13 - - - -
12 - - - -
11 - - - -
10 - - - -
9 - - - -
8 - - - -
7 - - MISC:POWERDOWNPIN[0] MISC:CCLKPIN[0]
6 - - ICAP:ENABLE MISC:DONEPIN[0]
5 - - STARTUP:GTS_SYNC STARTUP:GSR_SYNC
4 - - STARTUP:GTS_GSR_ENABLE STARTUP:GWE_SYNC
3 - - - -
2 - - - -
1 - - - -
0 - - - -
virtex2 LR.V2 bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13
11 - - - - - - - - DCI1:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_SPLIT[2] - DCI1:NMASK_TERM_SPLIT[0] DCI1:LVDSBIAS[4] DCI1:LVDSBIAS[7]
10 - - - - - - - - DCI1:PMASK_TERM_VCC[4] DCI1:PMASK_TERM_SPLIT[4] - DCI1:NMASK_TERM_SPLIT[2] DCI1:LVDSBIAS[3] -
9 - - - - - - - - DCI1:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[1] - - DCI1:LVDSBIAS[5] DCI1:LVDSBIAS[6]
8 - - - - - - - - DCI1:PMASK_TERM_VCC[0] DCI1:FORCE_DONE_HIGH - DCI1:NMASK_TERM_SPLIT[3] DCI1:LVDSBIAS[0] -
7 - - - - - - - - DCI1:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_SPLIT[3] DCI1:ENABLE DCI1:NMASK_TERM_SPLIT[1] DCI1:LVDSBIAS[2] DCI1:LVDSBIAS[8]
6 - - - - - - - - DCI1:PMASK_TERM_VCC[1] DCI1:TEST_ENABLE - DCI1:NMASK_TERM_SPLIT[4] DCI1:LVDSBIAS[1] -
5 - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - -
DCI0:ENABLE 0.2.42
DCI0:FORCE_DONE_HIGH 0.3.31
DCI0:TEST_ENABLE 0.2.31
DCI1:ENABLE 1.10.7
DCI1:FORCE_DONE_HIGH 1.9.8
DCI1:TEST_ENABLE 1.9.6
ICAP:ENABLE 0.2.6
STARTUP:GSR_SYNC 0.3.5
STARTUP:GTS_GSR_ENABLE 0.2.4
STARTUP:GTS_SYNC 0.2.5
STARTUP:GWE_SYNC 0.3.4
non-inverted [0]
DCI0:LVDSBIAS 0.3.44 0.2.45 0.3.45 0.2.46 0.3.46 0.2.47 0.3.47 0.2.48 0.3.48
DCI1:LVDSBIAS 1.13.7 1.13.11 1.13.9 1.12.9 1.12.11 1.12.10 1.12.7 1.12.6 1.12.8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.2.37 0.3.37 0.2.38 0.3.38 0.2.39
DCI0:PMASK_TERM_SPLIT 0.2.32 0.3.32 0.2.33 0.3.33 0.2.34
DCI0:PMASK_TERM_VCC 0.3.34 0.2.35 0.3.35 0.2.36 0.3.36
DCI1:NMASK_TERM_SPLIT 1.11.6 1.11.8 1.11.10 1.11.7 1.11.11
DCI1:PMASK_TERM_SPLIT 1.9.10 1.9.7 1.9.11 1.9.9 1.8.9
DCI1:PMASK_TERM_VCC 1.8.10 1.8.11 1.8.7 1.8.6 1.8.8
non-inverted [4] [3] [2] [1] [0]
MISC:CCLKPIN 0.3.7
MISC:DONEPIN 0.3.6
MISC:POWERDOWNPIN 0.2.7
PULLUP 0
PULLNONE 1

Tile LR.V2P

Cells: 1 IRIs: 0

Bel DCI0

virtex2 LR.V2P bel DCI0
PinDirectionWires
ADDRESS0outputOUT.HALF14.0
ADDRESS1outputOUT.HALF14.1
ADDRESS2outputOUT.HALF13.0
DATAoutputOUT.HALF15.1
DCI_CLKinputIMUX.G2.DATA7
DCI_DONEoutputOUT.HALF15.0
DCI_RESETinputIMUX.G2.DATA6
HI_LO_NinputIMUX.G2.DATA5
HI_LO_PinputIMUX.G2.DATA4
N_OR_PoutputOUT.HALF16.1
SCLKoutputOUT.HALF16.0
UPDATEoutputOUT.HALF17.1

Bel DCI1

virtex2 LR.V2P bel DCI1
PinDirectionWires
ADDRESS0outputOUT.HALF9.0
ADDRESS1outputOUT.HALF9.1
ADDRESS2outputOUT.HALF8.0
DATAoutputOUT.HALF10.1
DCI_CLKinputIMUX.G1.DATA7
DCI_DONEoutputOUT.HALF10.0
DCI_RESETinputIMUX.G1.DATA6
HI_LO_NinputIMUX.G1.DATA5
HI_LO_PinputIMUX.G1.DATA4
N_OR_PoutputOUT.HALF11.1
SCLKoutputOUT.HALF11.0
UPDATEoutputOUT.HALF12.1

Bel STARTUP

virtex2 LR.V2P bel STARTUP
PinDirectionWires
CLKinputIMUX.CLK0
GSRinputIMUX.SR0
GTSinputIMUX.TS0

Bel CAPTURE

virtex2 LR.V2P bel CAPTURE
PinDirectionWires
CAPinputIMUX.SR1
CLKinputIMUX.CLK2

Bel ICAP

virtex2 LR.V2P bel ICAP
PinDirectionWires
BUSYoutputOUT.HALF17.0
CEinputIMUX.CE1
CLKinputIMUX.CLK1
I0inputIMUX.G0.DATA0
I1inputIMUX.G0.DATA1
I2inputIMUX.G0.DATA2
I3inputIMUX.G0.DATA3
I4inputIMUX.G0.DATA4
I5inputIMUX.G0.DATA5
I6inputIMUX.G0.DATA6
I7inputIMUX.G0.DATA7
O0outputOUT.FAN0
O1outputOUT.FAN1
O2outputOUT.FAN2
O3outputOUT.FAN3
O4outputOUT.FAN4
O5outputOUT.FAN5
O6outputOUT.FAN6
O7outputOUT.FAN7
WRITEinputIMUX.TI0

Bel wires

virtex2 LR.V2P bel wires
WirePins
IMUX.CLK0STARTUP.CLK
IMUX.CLK1ICAP.CLK
IMUX.CLK2CAPTURE.CLK
IMUX.SR0STARTUP.GSR
IMUX.SR1CAPTURE.CAP
IMUX.CE1ICAP.CE
IMUX.TI0ICAP.WRITE
IMUX.TS0STARTUP.GTS
IMUX.G0.DATA0ICAP.I0
IMUX.G0.DATA1ICAP.I1
IMUX.G0.DATA2ICAP.I2
IMUX.G0.DATA3ICAP.I3
IMUX.G0.DATA4ICAP.I4
IMUX.G0.DATA5ICAP.I5
IMUX.G0.DATA6ICAP.I6
IMUX.G0.DATA7ICAP.I7
IMUX.G1.DATA4DCI1.HI_LO_P
IMUX.G1.DATA5DCI1.HI_LO_N
IMUX.G1.DATA6DCI1.DCI_RESET
IMUX.G1.DATA7DCI1.DCI_CLK
IMUX.G2.DATA4DCI0.HI_LO_P
IMUX.G2.DATA5DCI0.HI_LO_N
IMUX.G2.DATA6DCI0.DCI_RESET
IMUX.G2.DATA7DCI0.DCI_CLK
OUT.FAN0ICAP.O0
OUT.FAN1ICAP.O1
OUT.FAN2ICAP.O2
OUT.FAN3ICAP.O3
OUT.FAN4ICAP.O4
OUT.FAN5ICAP.O5
OUT.FAN6ICAP.O6
OUT.FAN7ICAP.O7
OUT.HALF8.0DCI1.ADDRESS2
OUT.HALF9.0DCI1.ADDRESS0
OUT.HALF9.1DCI1.ADDRESS1
OUT.HALF10.0DCI1.DCI_DONE
OUT.HALF10.1DCI1.DATA
OUT.HALF11.0DCI1.SCLK
OUT.HALF11.1DCI1.N_OR_P
OUT.HALF12.1DCI1.UPDATE
OUT.HALF13.0DCI0.ADDRESS2
OUT.HALF14.0DCI0.ADDRESS0
OUT.HALF14.1DCI0.ADDRESS1
OUT.HALF15.0DCI0.DCI_DONE
OUT.HALF15.1DCI0.DATA
OUT.HALF16.0DCI0.SCLK
OUT.HALF16.1DCI0.N_OR_P
OUT.HALF17.0ICAP.BUSY
OUT.HALF17.1DCI0.UPDATE

Bitstream

virtex2 LR.V2P bittile 0
BitFrame
0 1 2 3
48 - - DCI0:LVDSBIAS[1] DCI0:LVDSBIAS[0]
47 - - DCI0:LVDSBIAS[3] DCI0:LVDSBIAS[2]
46 - - DCI0:LVDSBIAS[5] DCI0:LVDSBIAS[4]
45 - - DCI0:LVDSBIAS[7] DCI0:LVDSBIAS[6]
44 - - - DCI0:LVDSBIAS[8]
43 - - - -
42 - - DCI0:ENABLE -
41 - - - -
40 - - - -
39 - - DCI0:NMASK_TERM_SPLIT[0] DCI0:QUIET
38 - - DCI0:NMASK_TERM_SPLIT[2] DCI0:NMASK_TERM_SPLIT[1]
37 - - DCI0:NMASK_TERM_SPLIT[4] DCI0:NMASK_TERM_SPLIT[3]
36 - - DCI0:PMASK_TERM_VCC[1] DCI0:PMASK_TERM_VCC[0]
35 - - DCI0:PMASK_TERM_VCC[3] DCI0:PMASK_TERM_VCC[2]
34 - - DCI0:PMASK_TERM_SPLIT[0] DCI0:PMASK_TERM_VCC[4]
33 - - DCI0:PMASK_TERM_SPLIT[2] DCI0:PMASK_TERM_SPLIT[1]
32 - - DCI0:PMASK_TERM_SPLIT[4] DCI0:PMASK_TERM_SPLIT[3]
31 - - DCI0:TEST_ENABLE DCI0:FORCE_DONE_HIGH
30 - - - -
29 - - - -
28 - - - -
27 - - - -
26 - - - -
25 - - - -
24 - - - -
23 - - - -
22 - - - -
21 - - - -
20 - - - -
19 - - - -
18 - - - -
17 - - - -
16 - - - -
15 - - - -
14 - - - -
13 - - - -
12 - - - -
11 - - - -
10 - - - -
9 - - - -
8 - - - -
7 - - MISC:POWERDOWNPIN[0] MISC:CCLKPIN[0]
6 - - ICAP:ENABLE MISC:DONEPIN[0]
5 - - STARTUP:GTS_SYNC STARTUP:GSR_SYNC
4 - - STARTUP:GTS_GSR_ENABLE STARTUP:GWE_SYNC
3 - - - -
2 - - - -
1 - - - -
0 - - - -
virtex2 LR.V2P bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13
11 - - - - - - - - DCI1:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_SPLIT[2] - DCI1:NMASK_TERM_SPLIT[0] DCI1:LVDSBIAS[4] DCI1:LVDSBIAS[7]
10 - - - - - - - - DCI1:PMASK_TERM_VCC[4] DCI1:PMASK_TERM_SPLIT[4] - DCI1:NMASK_TERM_SPLIT[2] DCI1:LVDSBIAS[3] -
9 - - - - - - - - DCI1:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[1] - DCI1:QUIET DCI1:LVDSBIAS[5] DCI1:LVDSBIAS[6]
8 - - - - - - - - DCI1:PMASK_TERM_VCC[0] DCI1:FORCE_DONE_HIGH - DCI1:NMASK_TERM_SPLIT[3] DCI1:LVDSBIAS[0] -
7 - - - - - - - - DCI1:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_SPLIT[3] DCI1:ENABLE DCI1:NMASK_TERM_SPLIT[1] DCI1:LVDSBIAS[2] DCI1:LVDSBIAS[8]
6 - - - - - - - - DCI1:PMASK_TERM_VCC[1] DCI1:TEST_ENABLE - DCI1:NMASK_TERM_SPLIT[4] DCI1:LVDSBIAS[1] -
5 - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - -
DCI0:ENABLE 0.2.42
DCI0:FORCE_DONE_HIGH 0.3.31
DCI0:QUIET 0.3.39
DCI0:TEST_ENABLE 0.2.31
DCI1:ENABLE 1.10.7
DCI1:FORCE_DONE_HIGH 1.9.8
DCI1:QUIET 1.11.9
DCI1:TEST_ENABLE 1.9.6
ICAP:ENABLE 0.2.6
STARTUP:GSR_SYNC 0.3.5
STARTUP:GTS_GSR_ENABLE 0.2.4
STARTUP:GTS_SYNC 0.2.5
STARTUP:GWE_SYNC 0.3.4
non-inverted [0]
DCI0:LVDSBIAS 0.3.44 0.2.45 0.3.45 0.2.46 0.3.46 0.2.47 0.3.47 0.2.48 0.3.48
DCI1:LVDSBIAS 1.13.7 1.13.11 1.13.9 1.12.9 1.12.11 1.12.10 1.12.7 1.12.6 1.12.8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.2.37 0.3.37 0.2.38 0.3.38 0.2.39
DCI0:PMASK_TERM_SPLIT 0.2.32 0.3.32 0.2.33 0.3.33 0.2.34
DCI0:PMASK_TERM_VCC 0.3.34 0.2.35 0.3.35 0.2.36 0.3.36
DCI1:NMASK_TERM_SPLIT 1.11.6 1.11.8 1.11.10 1.11.7 1.11.11
DCI1:PMASK_TERM_SPLIT 1.9.10 1.9.7 1.9.11 1.9.9 1.8.9
DCI1:PMASK_TERM_VCC 1.8.10 1.8.11 1.8.7 1.8.6 1.8.8
non-inverted [4] [3] [2] [1] [0]
MISC:CCLKPIN 0.3.7
MISC:DONEPIN 0.3.6
MISC:POWERDOWNPIN 0.2.7
PULLUP 0
PULLNONE 1