Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

South-west

TODO: document

Tile CNR_SW_V2

Cells: 1

Bels DCI

virtex2 CNR_SW_V2 bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_G2_DATA[7]IMUX_G1_DATA[7]
DCI_RESETinIMUX_G2_DATA[6]IMUX_G1_DATA[6]
HI_LO_PinIMUX_G2_DATA[4]IMUX_G1_DATA[4]
HI_LO_NinIMUX_G2_DATA[5]IMUX_G1_DATA[5]
SCLKoutOUT_HALF0[16]OUT_HALF0[11]
ADDRESS[0]outOUT_HALF0[14]OUT_HALF0[9]
ADDRESS[1]outOUT_HALF1[14]OUT_HALF1[9]
ADDRESS[2]outOUT_HALF0[13]OUT_HALF0[8]
DATAoutOUT_HALF1[15]OUT_HALF1[10]
N_OR_PoutOUT_HALF1[16]OUT_HALF1[11]
UPDATEoutOUT_HALF1[17]OUT_HALF1[12]
DCI_DONEoutOUT_HALF0[15]OUT_HALF0[10]
virtex2 CNR_SW_V2 bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[2][42]TERM_V[10][7]
TEST_ENABLETERM_H[2][31]TERM_V[9][6]
FORCE_DONE_HIGHTERM_H[3][31]TERM_V[9][8]
V2_PMASK_TERM_SPLIT bit 0TERM_H[2][34]TERM_V[8][9]
V2_PMASK_TERM_SPLIT bit 1TERM_H[3][33]TERM_V[9][9]
V2_PMASK_TERM_SPLIT bit 2TERM_H[2][33]TERM_V[9][11]
V2_PMASK_TERM_SPLIT bit 3TERM_H[3][32]TERM_V[9][7]
V2_PMASK_TERM_SPLIT bit 4TERM_H[2][32]TERM_V[9][10]
V2_NMASK_TERM_SPLIT bit 0TERM_H[2][39]TERM_V[11][11]
V2_NMASK_TERM_SPLIT bit 1TERM_H[3][38]TERM_V[11][7]
V2_NMASK_TERM_SPLIT bit 2TERM_H[2][38]TERM_V[11][10]
V2_NMASK_TERM_SPLIT bit 3TERM_H[3][37]TERM_V[11][8]
V2_NMASK_TERM_SPLIT bit 4TERM_H[2][37]TERM_V[11][6]
V2_PMASK_TERM_VCC bit 0TERM_H[3][36]TERM_V[8][8]
V2_PMASK_TERM_VCC bit 1TERM_H[2][36]TERM_V[8][6]
V2_PMASK_TERM_VCC bit 2TERM_H[3][35]TERM_V[8][7]
V2_PMASK_TERM_VCC bit 3TERM_H[2][35]TERM_V[8][11]
V2_PMASK_TERM_VCC bit 4TERM_H[3][34]TERM_V[8][10]
V2_LVDSBIAS bit 0TERM_H[3][48]TERM_V[12][8]
V2_LVDSBIAS bit 1TERM_H[2][48]TERM_V[12][6]
V2_LVDSBIAS bit 2TERM_H[3][47]TERM_V[12][7]
V2_LVDSBIAS bit 3TERM_H[2][47]TERM_V[12][10]
V2_LVDSBIAS bit 4TERM_H[3][46]TERM_V[12][11]
V2_LVDSBIAS bit 5TERM_H[2][46]TERM_V[12][9]
V2_LVDSBIAS bit 6TERM_H[3][45]TERM_V[13][9]
V2_LVDSBIAS bit 7TERM_H[2][45]TERM_V[13][11]
V2_LVDSBIAS bit 8TERM_H[3][44]TERM_V[13][7]

Bels MISC_SW

virtex2 CNR_SW_V2 bel MISC_SW pins
PinDirectionMISC_SW
virtex2 CNR_SW_V2 bel MISC_SW attribute bits
AttributeMISC_SW
M0_PULL[enum: IOB_PULL]
M1_PULL[enum: IOB_PULL]
M2_PULL[enum: IOB_PULL]
DCI_CLK_ENABLETERM_V[18][10]
DCI_ALTVRTERM_V[18][9]
BCLK_N_DIV2 bit 0TERM_V[17][10]
BCLK_N_DIV2 bit 1TERM_V[17][9]
BCLK_N_DIV2 bit 2TERM_V[17][6]
BCLK_N_DIV2 bit 3TERM_V[17][7]
BCLK_N_DIV2 bit 4TERM_V[17][8]
ZCLK_N_DIV2 bit 0TERM_V[18][11]
ZCLK_N_DIV2 bit 1TERM_V[19][9]
ZCLK_N_DIV2 bit 2TERM_V[19][11]
ZCLK_N_DIV2 bit 3TERM_V[19][7]
ZCLK_N_DIV2 bit 4TERM_V[19][10]
DISABLE_BANDGAPTERM_V[16][6]
RAISE_VGG bit 0TERM_V[19][6]
RAISE_VGG bit 1TERM_V[19][8]
virtex2 CNR_SW_V2 enum IOB_PULL
MISC_SW.M0_PULLTERM_V[16][10]TERM_V[16][11]
MISC_SW.M1_PULLTERM_V[16][9]TERM_V[17][11]
MISC_SW.M2_PULLTERM_V[16][7]TERM_V[16][8]
NONE01
PULLUP00
PULLDOWN10

Bel wires

virtex2 CNR_SW_V2 bel wires
WirePins
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_HALF0[8]DCI[1].ADDRESS[2]
OUT_HALF0[9]DCI[1].ADDRESS[0]
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[13]DCI[0].ADDRESS[2]
OUT_HALF0[14]DCI[0].ADDRESS[0]
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF1[9]DCI[1].ADDRESS[1]
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[14]DCI[0].ADDRESS[1]
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_SW_V2 rect TERM_H
BitFrame
F3 F2 F1 F0
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 DCI[0]: V2_LVDSBIAS bit 0 DCI[0]: V2_LVDSBIAS bit 1 - -
B47 DCI[0]: V2_LVDSBIAS bit 2 DCI[0]: V2_LVDSBIAS bit 3 - -
B46 DCI[0]: V2_LVDSBIAS bit 4 DCI[0]: V2_LVDSBIAS bit 5 - -
B45 DCI[0]: V2_LVDSBIAS bit 6 DCI[0]: V2_LVDSBIAS bit 7 - -
B44 DCI[0]: V2_LVDSBIAS bit 8 - - -
B43 - - - -
B42 - DCI[0]: ENABLE - -
B41 - - - -
B40 - - - -
B39 - DCI[0]: V2_NMASK_TERM_SPLIT bit 0 - -
B38 DCI[0]: V2_NMASK_TERM_SPLIT bit 1 DCI[0]: V2_NMASK_TERM_SPLIT bit 2 - -
B37 DCI[0]: V2_NMASK_TERM_SPLIT bit 3 DCI[0]: V2_NMASK_TERM_SPLIT bit 4 - -
B36 DCI[0]: V2_PMASK_TERM_VCC bit 0 DCI[0]: V2_PMASK_TERM_VCC bit 1 - -
B35 DCI[0]: V2_PMASK_TERM_VCC bit 2 DCI[0]: V2_PMASK_TERM_VCC bit 3 - -
B34 DCI[0]: V2_PMASK_TERM_VCC bit 4 DCI[0]: V2_PMASK_TERM_SPLIT bit 0 - -
B33 DCI[0]: V2_PMASK_TERM_SPLIT bit 1 DCI[0]: V2_PMASK_TERM_SPLIT bit 2 - -
B32 DCI[0]: V2_PMASK_TERM_SPLIT bit 3 DCI[0]: V2_PMASK_TERM_SPLIT bit 4 - -
B31 DCI[0]: FORCE_DONE_HIGH DCI[0]: TEST_ENABLE - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_SW_V2 rect TERM_V
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - MISC_SW: ZCLK_N_DIV2 bit 2 MISC_SW: ZCLK_N_DIV2 bit 0 MISC_SW: M1_PULL bit 0 MISC_SW: M0_PULL bit 0 - - DCI[1]: V2_LVDSBIAS bit 7 DCI[1]: V2_LVDSBIAS bit 4 DCI[1]: V2_NMASK_TERM_SPLIT bit 0 - DCI[1]: V2_PMASK_TERM_SPLIT bit 2 DCI[1]: V2_PMASK_TERM_VCC bit 3 - - - - - - - -
B10 - - MISC_SW: ZCLK_N_DIV2 bit 4 MISC_SW: DCI_CLK_ENABLE MISC_SW: BCLK_N_DIV2 bit 0 MISC_SW: M0_PULL bit 1 - - - DCI[1]: V2_LVDSBIAS bit 3 DCI[1]: V2_NMASK_TERM_SPLIT bit 2 - DCI[1]: V2_PMASK_TERM_SPLIT bit 4 DCI[1]: V2_PMASK_TERM_VCC bit 4 - - - - - - - -
B9 - - MISC_SW: ZCLK_N_DIV2 bit 1 MISC_SW: DCI_ALTVR MISC_SW: BCLK_N_DIV2 bit 1 MISC_SW: M1_PULL bit 1 - - DCI[1]: V2_LVDSBIAS bit 6 DCI[1]: V2_LVDSBIAS bit 5 - - DCI[1]: V2_PMASK_TERM_SPLIT bit 1 DCI[1]: V2_PMASK_TERM_SPLIT bit 0 - - - - - - - -
B8 - - MISC_SW: RAISE_VGG bit 1 - MISC_SW: BCLK_N_DIV2 bit 4 MISC_SW: M2_PULL bit 0 - - - DCI[1]: V2_LVDSBIAS bit 0 DCI[1]: V2_NMASK_TERM_SPLIT bit 3 - DCI[1]: FORCE_DONE_HIGH DCI[1]: V2_PMASK_TERM_VCC bit 0 - - - - - - - -
B7 - - MISC_SW: ZCLK_N_DIV2 bit 3 - MISC_SW: BCLK_N_DIV2 bit 3 MISC_SW: M2_PULL bit 1 - - DCI[1]: V2_LVDSBIAS bit 8 DCI[1]: V2_LVDSBIAS bit 2 DCI[1]: V2_NMASK_TERM_SPLIT bit 1 DCI[1]: ENABLE DCI[1]: V2_PMASK_TERM_SPLIT bit 3 DCI[1]: V2_PMASK_TERM_VCC bit 2 - - - - - - - -
B6 - - MISC_SW: RAISE_VGG bit 0 - MISC_SW: BCLK_N_DIV2 bit 2 MISC_SW: DISABLE_BANDGAP - - - DCI[1]: V2_LVDSBIAS bit 1 DCI[1]: V2_NMASK_TERM_SPLIT bit 4 - DCI[1]: TEST_ENABLE DCI[1]: V2_PMASK_TERM_VCC bit 1 - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -

Tile CNR_SW_V2P

Cells: 1

Bels DCI

virtex2 CNR_SW_V2P bel DCI pins
PinDirectionDCI[0]DCI[1]
DCI_CLKinIMUX_G2_DATA[7]IMUX_G1_DATA[7]
DCI_RESETinIMUX_G2_DATA[6]IMUX_G1_DATA[6]
HI_LO_PinIMUX_G2_DATA[4]IMUX_G1_DATA[4]
HI_LO_NinIMUX_G2_DATA[5]IMUX_G1_DATA[5]
SCLKoutOUT_HALF0[16]OUT_HALF0[11]
ADDRESS[0]outOUT_HALF0[14]OUT_HALF0[9]
ADDRESS[1]outOUT_HALF1[14]OUT_HALF1[9]
ADDRESS[2]outOUT_HALF0[13]OUT_HALF0[8]
DATAoutOUT_HALF1[15]OUT_HALF1[10]
N_OR_PoutOUT_HALF1[16]OUT_HALF1[11]
UPDATEoutOUT_HALF1[17]OUT_HALF1[12]
DCI_DONEoutOUT_HALF0[15]OUT_HALF0[10]
virtex2 CNR_SW_V2P bel DCI attribute bits
AttributeDCI[0]DCI[1]
ENABLETERM_H[2][42]TERM_V[10][7]
TEST_ENABLETERM_H[2][31]TERM_V[9][6]
FORCE_DONE_HIGHTERM_H[3][31]TERM_V[9][8]
V2_PMASK_TERM_SPLIT bit 0TERM_H[2][34]TERM_V[8][9]
V2_PMASK_TERM_SPLIT bit 1TERM_H[3][33]TERM_V[9][9]
V2_PMASK_TERM_SPLIT bit 2TERM_H[2][33]TERM_V[9][11]
V2_PMASK_TERM_SPLIT bit 3TERM_H[3][32]TERM_V[9][7]
V2_PMASK_TERM_SPLIT bit 4TERM_H[2][32]TERM_V[9][10]
V2_NMASK_TERM_SPLIT bit 0TERM_H[2][39]TERM_V[11][11]
V2_NMASK_TERM_SPLIT bit 1TERM_H[3][38]TERM_V[11][7]
V2_NMASK_TERM_SPLIT bit 2TERM_H[2][38]TERM_V[11][10]
V2_NMASK_TERM_SPLIT bit 3TERM_H[3][37]TERM_V[11][8]
V2_NMASK_TERM_SPLIT bit 4TERM_H[2][37]TERM_V[11][6]
V2_PMASK_TERM_VCC bit 0TERM_H[3][36]TERM_V[8][8]
V2_PMASK_TERM_VCC bit 1TERM_H[2][36]TERM_V[8][6]
V2_PMASK_TERM_VCC bit 2TERM_H[3][35]TERM_V[8][7]
V2_PMASK_TERM_VCC bit 3TERM_H[2][35]TERM_V[8][11]
V2_PMASK_TERM_VCC bit 4TERM_H[3][34]TERM_V[8][10]
V2_LVDSBIAS bit 0TERM_H[3][48]TERM_V[12][8]
V2_LVDSBIAS bit 1TERM_H[2][48]TERM_V[12][6]
V2_LVDSBIAS bit 2TERM_H[3][47]TERM_V[12][7]
V2_LVDSBIAS bit 3TERM_H[2][47]TERM_V[12][10]
V2_LVDSBIAS bit 4TERM_H[3][46]TERM_V[12][11]
V2_LVDSBIAS bit 5TERM_H[2][46]TERM_V[12][9]
V2_LVDSBIAS bit 6TERM_H[3][45]TERM_V[13][9]
V2_LVDSBIAS bit 7TERM_H[2][45]TERM_V[13][11]
V2_LVDSBIAS bit 8TERM_H[3][44]TERM_V[13][7]
QUIETTERM_H[3][39]TERM_V[11][9]

Bels MISC_SW

virtex2 CNR_SW_V2P bel MISC_SW pins
PinDirectionMISC_SW
virtex2 CNR_SW_V2P bel MISC_SW attribute bits
AttributeMISC_SW
M0_PULL[enum: IOB_PULL]
M1_PULL[enum: IOB_PULL]
M2_PULL[enum: IOB_PULL]
DCI_CLK_ENABLETERM_V[18][10]
BCLK_N_DIV2 bit 0TERM_V[17][10]
BCLK_N_DIV2 bit 1TERM_V[17][9]
BCLK_N_DIV2 bit 2TERM_V[17][6]
BCLK_N_DIV2 bit 3TERM_V[17][7]
BCLK_N_DIV2 bit 4TERM_V[17][8]
ZCLK_N_DIV2 bit 0TERM_V[18][11]
ZCLK_N_DIV2 bit 1TERM_V[19][9]
ZCLK_N_DIV2 bit 2TERM_V[19][11]
ZCLK_N_DIV2 bit 3TERM_V[19][7]
ZCLK_N_DIV2 bit 4TERM_V[19][10]
DISABLE_BANDGAPTERM_V[16][6]
DISABLE_VGG_GENERATIONTERM_V[18][8]
RAISE_VGG bit 0TERM_V[19][6]
RAISE_VGG bit 1TERM_V[19][8]
virtex2 CNR_SW_V2P enum IOB_PULL
MISC_SW.M0_PULLTERM_V[16][10]TERM_V[16][11]
MISC_SW.M1_PULLTERM_V[16][9]TERM_V[17][11]
MISC_SW.M2_PULLTERM_V[16][7]TERM_V[16][8]
NONE01
PULLUP00
PULLDOWN10

Bel wires

virtex2 CNR_SW_V2P bel wires
WirePins
IMUX_G1_DATA[4]DCI[1].HI_LO_P
IMUX_G1_DATA[5]DCI[1].HI_LO_N
IMUX_G1_DATA[6]DCI[1].DCI_RESET
IMUX_G1_DATA[7]DCI[1].DCI_CLK
IMUX_G2_DATA[4]DCI[0].HI_LO_P
IMUX_G2_DATA[5]DCI[0].HI_LO_N
IMUX_G2_DATA[6]DCI[0].DCI_RESET
IMUX_G2_DATA[7]DCI[0].DCI_CLK
OUT_HALF0[8]DCI[1].ADDRESS[2]
OUT_HALF0[9]DCI[1].ADDRESS[0]
OUT_HALF0[10]DCI[1].DCI_DONE
OUT_HALF0[11]DCI[1].SCLK
OUT_HALF0[13]DCI[0].ADDRESS[2]
OUT_HALF0[14]DCI[0].ADDRESS[0]
OUT_HALF0[15]DCI[0].DCI_DONE
OUT_HALF0[16]DCI[0].SCLK
OUT_HALF1[9]DCI[1].ADDRESS[1]
OUT_HALF1[10]DCI[1].DATA
OUT_HALF1[11]DCI[1].N_OR_P
OUT_HALF1[12]DCI[1].UPDATE
OUT_HALF1[14]DCI[0].ADDRESS[1]
OUT_HALF1[15]DCI[0].DATA
OUT_HALF1[16]DCI[0].N_OR_P
OUT_HALF1[17]DCI[0].UPDATE

Bitstream

virtex2 CNR_SW_V2P rect TERM_H
BitFrame
F3 F2 F1 F0
B79 - - - -
B78 - - - -
B77 - - - -
B76 - - - -
B75 - - - -
B74 - - - -
B73 - - - -
B72 - - - -
B71 - - - -
B70 - - - -
B69 - - - -
B68 - - - -
B67 - - - -
B66 - - - -
B65 - - - -
B64 - - - -
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 DCI[0]: V2_LVDSBIAS bit 0 DCI[0]: V2_LVDSBIAS bit 1 - -
B47 DCI[0]: V2_LVDSBIAS bit 2 DCI[0]: V2_LVDSBIAS bit 3 - -
B46 DCI[0]: V2_LVDSBIAS bit 4 DCI[0]: V2_LVDSBIAS bit 5 - -
B45 DCI[0]: V2_LVDSBIAS bit 6 DCI[0]: V2_LVDSBIAS bit 7 - -
B44 DCI[0]: V2_LVDSBIAS bit 8 - - -
B43 - - - -
B42 - DCI[0]: ENABLE - -
B41 - - - -
B40 - - - -
B39 DCI[0]: QUIET DCI[0]: V2_NMASK_TERM_SPLIT bit 0 - -
B38 DCI[0]: V2_NMASK_TERM_SPLIT bit 1 DCI[0]: V2_NMASK_TERM_SPLIT bit 2 - -
B37 DCI[0]: V2_NMASK_TERM_SPLIT bit 3 DCI[0]: V2_NMASK_TERM_SPLIT bit 4 - -
B36 DCI[0]: V2_PMASK_TERM_VCC bit 0 DCI[0]: V2_PMASK_TERM_VCC bit 1 - -
B35 DCI[0]: V2_PMASK_TERM_VCC bit 2 DCI[0]: V2_PMASK_TERM_VCC bit 3 - -
B34 DCI[0]: V2_PMASK_TERM_VCC bit 4 DCI[0]: V2_PMASK_TERM_SPLIT bit 0 - -
B33 DCI[0]: V2_PMASK_TERM_SPLIT bit 1 DCI[0]: V2_PMASK_TERM_SPLIT bit 2 - -
B32 DCI[0]: V2_PMASK_TERM_SPLIT bit 3 DCI[0]: V2_PMASK_TERM_SPLIT bit 4 - -
B31 DCI[0]: FORCE_DONE_HIGH DCI[0]: TEST_ENABLE - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex2 CNR_SW_V2P rect TERM_V
BitFrame
F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
B11 - - MISC_SW: ZCLK_N_DIV2 bit 2 MISC_SW: ZCLK_N_DIV2 bit 0 MISC_SW: M1_PULL bit 0 MISC_SW: M0_PULL bit 0 - - DCI[1]: V2_LVDSBIAS bit 7 DCI[1]: V2_LVDSBIAS bit 4 DCI[1]: V2_NMASK_TERM_SPLIT bit 0 - DCI[1]: V2_PMASK_TERM_SPLIT bit 2 DCI[1]: V2_PMASK_TERM_VCC bit 3 - - - - - - - -
B10 - - MISC_SW: ZCLK_N_DIV2 bit 4 MISC_SW: DCI_CLK_ENABLE MISC_SW: BCLK_N_DIV2 bit 0 MISC_SW: M0_PULL bit 1 - - - DCI[1]: V2_LVDSBIAS bit 3 DCI[1]: V2_NMASK_TERM_SPLIT bit 2 - DCI[1]: V2_PMASK_TERM_SPLIT bit 4 DCI[1]: V2_PMASK_TERM_VCC bit 4 - - - - - - - -
B9 - - MISC_SW: ZCLK_N_DIV2 bit 1 - MISC_SW: BCLK_N_DIV2 bit 1 MISC_SW: M1_PULL bit 1 - - DCI[1]: V2_LVDSBIAS bit 6 DCI[1]: V2_LVDSBIAS bit 5 DCI[1]: QUIET - DCI[1]: V2_PMASK_TERM_SPLIT bit 1 DCI[1]: V2_PMASK_TERM_SPLIT bit 0 - - - - - - - -
B8 - - MISC_SW: RAISE_VGG bit 1 MISC_SW: DISABLE_VGG_GENERATION MISC_SW: BCLK_N_DIV2 bit 4 MISC_SW: M2_PULL bit 0 - - - DCI[1]: V2_LVDSBIAS bit 0 DCI[1]: V2_NMASK_TERM_SPLIT bit 3 - DCI[1]: FORCE_DONE_HIGH DCI[1]: V2_PMASK_TERM_VCC bit 0 - - - - - - - -
B7 - - MISC_SW: ZCLK_N_DIV2 bit 3 - MISC_SW: BCLK_N_DIV2 bit 3 MISC_SW: M2_PULL bit 1 - - DCI[1]: V2_LVDSBIAS bit 8 DCI[1]: V2_LVDSBIAS bit 2 DCI[1]: V2_NMASK_TERM_SPLIT bit 1 DCI[1]: ENABLE DCI[1]: V2_PMASK_TERM_SPLIT bit 3 DCI[1]: V2_PMASK_TERM_VCC bit 2 - - - - - - - -
B6 - - MISC_SW: RAISE_VGG bit 0 - MISC_SW: BCLK_N_DIV2 bit 2 MISC_SW: DISABLE_BANDGAP - - - DCI[1]: V2_LVDSBIAS bit 1 DCI[1]: V2_NMASK_TERM_SPLIT bit 4 - DCI[1]: TEST_ENABLE DCI[1]: V2_PMASK_TERM_VCC bit 1 - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - -