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South-west

TODO: document

Tile LL.V2

Cells: 1

Bel DCI0

virtex2 LL.V2 bel DCI0
PinDirectionWires
ADDRESS0outputOUT.HALF14.0
ADDRESS1outputOUT.HALF14.1
ADDRESS2outputOUT.HALF13.0
DATAoutputOUT.HALF15.1
DCI_CLKinputIMUX.G2.DATA7
DCI_DONEoutputOUT.HALF15.0
DCI_RESETinputIMUX.G2.DATA6
HI_LO_NinputIMUX.G2.DATA5
HI_LO_PinputIMUX.G2.DATA4
N_OR_PoutputOUT.HALF16.1
SCLKoutputOUT.HALF16.0
UPDATEoutputOUT.HALF17.1

Bel DCI1

virtex2 LL.V2 bel DCI1
PinDirectionWires
ADDRESS0outputOUT.HALF9.0
ADDRESS1outputOUT.HALF9.1
ADDRESS2outputOUT.HALF8.0
DATAoutputOUT.HALF10.1
DCI_CLKinputIMUX.G1.DATA7
DCI_DONEoutputOUT.HALF10.0
DCI_RESETinputIMUX.G1.DATA6
HI_LO_NinputIMUX.G1.DATA5
HI_LO_PinputIMUX.G1.DATA4
N_OR_PoutputOUT.HALF11.1
SCLKoutputOUT.HALF11.0
UPDATEoutputOUT.HALF12.1

Bel wires

virtex2 LL.V2 bel wires
WirePins
IMUX.G1.DATA4DCI1.HI_LO_P
IMUX.G1.DATA5DCI1.HI_LO_N
IMUX.G1.DATA6DCI1.DCI_RESET
IMUX.G1.DATA7DCI1.DCI_CLK
IMUX.G2.DATA4DCI0.HI_LO_P
IMUX.G2.DATA5DCI0.HI_LO_N
IMUX.G2.DATA6DCI0.DCI_RESET
IMUX.G2.DATA7DCI0.DCI_CLK
OUT.HALF8.0DCI1.ADDRESS2
OUT.HALF9.0DCI1.ADDRESS0
OUT.HALF9.1DCI1.ADDRESS1
OUT.HALF10.0DCI1.DCI_DONE
OUT.HALF10.1DCI1.DATA
OUT.HALF11.0DCI1.SCLK
OUT.HALF11.1DCI1.N_OR_P
OUT.HALF12.1DCI1.UPDATE
OUT.HALF13.0DCI0.ADDRESS2
OUT.HALF14.0DCI0.ADDRESS0
OUT.HALF14.1DCI0.ADDRESS1
OUT.HALF15.0DCI0.DCI_DONE
OUT.HALF15.1DCI0.DATA
OUT.HALF16.0DCI0.SCLK
OUT.HALF16.1DCI0.N_OR_P
OUT.HALF17.1DCI0.UPDATE

Bitstream

virtex2 LL.V2 bittile 0
BitFrame
0 1 2 3
48 - - DCI0:LVDSBIAS[1] DCI0:LVDSBIAS[0]
47 - - DCI0:LVDSBIAS[3] DCI0:LVDSBIAS[2]
46 - - DCI0:LVDSBIAS[5] DCI0:LVDSBIAS[4]
45 - - DCI0:LVDSBIAS[7] DCI0:LVDSBIAS[6]
44 - - - DCI0:LVDSBIAS[8]
43 - - - -
42 - - DCI0:ENABLE -
41 - - - -
40 - - - -
39 - - DCI0:NMASK_TERM_SPLIT[0] -
38 - - DCI0:NMASK_TERM_SPLIT[2] DCI0:NMASK_TERM_SPLIT[1]
37 - - DCI0:NMASK_TERM_SPLIT[4] DCI0:NMASK_TERM_SPLIT[3]
36 - - DCI0:PMASK_TERM_VCC[1] DCI0:PMASK_TERM_VCC[0]
35 - - DCI0:PMASK_TERM_VCC[3] DCI0:PMASK_TERM_VCC[2]
34 - - DCI0:PMASK_TERM_SPLIT[0] DCI0:PMASK_TERM_VCC[4]
33 - - DCI0:PMASK_TERM_SPLIT[2] DCI0:PMASK_TERM_SPLIT[1]
32 - - DCI0:PMASK_TERM_SPLIT[4] DCI0:PMASK_TERM_SPLIT[3]
31 - - DCI0:TEST_ENABLE DCI0:FORCE_DONE_HIGH
30 - - - -
29 - - - -
28 - - - -
27 - - - -
26 - - - -
25 - - - -
24 - - - -
23 - - - -
22 - - - -
21 - - - -
20 - - - -
19 - - - -
18 - - - -
17 - - - -
16 - - - -
15 - - - -
14 - - - -
13 - - - -
12 - - - -
11 - - - -
10 - - - -
9 - - - -
8 - - - -
7 - - - -
6 - - - -
5 - - - -
4 - - - -
3 - - - -
2 - - - -
1 - - - -
0 - - - -
virtex2 LL.V2 bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
11 - - - - - - - - DCI1:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_SPLIT[2] - DCI1:NMASK_TERM_SPLIT[0] DCI1:LVDSBIAS[4] DCI1:LVDSBIAS[7] - - MISC:M0PIN[1] MISC:M1PIN[1] MISC:ZCLK_DIV2[0] MISC:ZCLK_DIV2[2]
10 - - - - - - - - DCI1:PMASK_TERM_VCC[4] DCI1:PMASK_TERM_SPLIT[4] - DCI1:NMASK_TERM_SPLIT[2] DCI1:LVDSBIAS[3] - - - MISC:M0PIN[0] MISC:BCLK_DIV2[0] MISC:DCI_CLK_ENABLE MISC:ZCLK_DIV2[4]
9 - - - - - - - - DCI1:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[1] - - DCI1:LVDSBIAS[5] DCI1:LVDSBIAS[6] - - MISC:M1PIN[0] MISC:BCLK_DIV2[1] MISC:DCI_ALTVR MISC:ZCLK_DIV2[1]
8 - - - - - - - - DCI1:PMASK_TERM_VCC[0] DCI1:FORCE_DONE_HIGH - DCI1:NMASK_TERM_SPLIT[3] DCI1:LVDSBIAS[0] - - - MISC:M2PIN[1] MISC:BCLK_DIV2[4] - MISC:RAISEVGG[1]
7 - - - - - - - - DCI1:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_SPLIT[3] DCI1:ENABLE DCI1:NMASK_TERM_SPLIT[1] DCI1:LVDSBIAS[2] DCI1:LVDSBIAS[8] - - MISC:M2PIN[0] MISC:BCLK_DIV2[3] - MISC:ZCLK_DIV2[3]
6 - - - - - - - - DCI1:PMASK_TERM_VCC[1] DCI1:TEST_ENABLE - DCI1:NMASK_TERM_SPLIT[4] DCI1:LVDSBIAS[1] - - - MISC:DISABLEBANDGAP MISC:BCLK_DIV2[2] - MISC:RAISEVGG[0]
5 - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - -
DCI0:ENABLE 0.2.42
DCI0:FORCE_DONE_HIGH 0.3.31
DCI0:TEST_ENABLE 0.2.31
DCI1:ENABLE 1.10.7
DCI1:FORCE_DONE_HIGH 1.9.8
DCI1:TEST_ENABLE 1.9.6
MISC:DCI_ALTVR 1.18.9
MISC:DCI_CLK_ENABLE 1.18.10
MISC:DISABLEBANDGAP 1.16.6
non-inverted [0]
DCI0:LVDSBIAS 0.3.44 0.2.45 0.3.45 0.2.46 0.3.46 0.2.47 0.3.47 0.2.48 0.3.48
DCI1:LVDSBIAS 1.13.7 1.13.11 1.13.9 1.12.9 1.12.11 1.12.10 1.12.7 1.12.6 1.12.8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.2.37 0.3.37 0.2.38 0.3.38 0.2.39
DCI0:PMASK_TERM_SPLIT 0.2.32 0.3.32 0.2.33 0.3.33 0.2.34
DCI0:PMASK_TERM_VCC 0.3.34 0.2.35 0.3.35 0.2.36 0.3.36
DCI1:NMASK_TERM_SPLIT 1.11.6 1.11.8 1.11.10 1.11.7 1.11.11
DCI1:PMASK_TERM_SPLIT 1.9.10 1.9.7 1.9.11 1.9.9 1.8.9
DCI1:PMASK_TERM_VCC 1.8.10 1.8.11 1.8.7 1.8.6 1.8.8
MISC:BCLK_DIV2 1.17.8 1.17.7 1.17.6 1.17.9 1.17.10
MISC:ZCLK_DIV2 1.19.10 1.19.7 1.19.11 1.19.9 1.18.11
non-inverted [4] [3] [2] [1] [0]
MISC:M0PIN 1.16.11 1.16.10
MISC:M1PIN 1.17.11 1.16.9
MISC:M2PIN 1.16.8 1.16.7
PULLUP 0 0
PULLDOWN 0 1
PULLNONE 1 0
MISC:RAISEVGG 1.19.8 1.19.6
non-inverted [1] [0]

Tile LL.V2P

Cells: 1

Bel DCI0

virtex2 LL.V2P bel DCI0
PinDirectionWires
ADDRESS0outputOUT.HALF14.0
ADDRESS1outputOUT.HALF14.1
ADDRESS2outputOUT.HALF13.0
DATAoutputOUT.HALF15.1
DCI_CLKinputIMUX.G2.DATA7
DCI_DONEoutputOUT.HALF15.0
DCI_RESETinputIMUX.G2.DATA6
HI_LO_NinputIMUX.G2.DATA5
HI_LO_PinputIMUX.G2.DATA4
N_OR_PoutputOUT.HALF16.1
SCLKoutputOUT.HALF16.0
UPDATEoutputOUT.HALF17.1

Bel DCI1

virtex2 LL.V2P bel DCI1
PinDirectionWires
ADDRESS0outputOUT.HALF9.0
ADDRESS1outputOUT.HALF9.1
ADDRESS2outputOUT.HALF8.0
DATAoutputOUT.HALF10.1
DCI_CLKinputIMUX.G1.DATA7
DCI_DONEoutputOUT.HALF10.0
DCI_RESETinputIMUX.G1.DATA6
HI_LO_NinputIMUX.G1.DATA5
HI_LO_PinputIMUX.G1.DATA4
N_OR_PoutputOUT.HALF11.1
SCLKoutputOUT.HALF11.0
UPDATEoutputOUT.HALF12.1

Bel wires

virtex2 LL.V2P bel wires
WirePins
IMUX.G1.DATA4DCI1.HI_LO_P
IMUX.G1.DATA5DCI1.HI_LO_N
IMUX.G1.DATA6DCI1.DCI_RESET
IMUX.G1.DATA7DCI1.DCI_CLK
IMUX.G2.DATA4DCI0.HI_LO_P
IMUX.G2.DATA5DCI0.HI_LO_N
IMUX.G2.DATA6DCI0.DCI_RESET
IMUX.G2.DATA7DCI0.DCI_CLK
OUT.HALF8.0DCI1.ADDRESS2
OUT.HALF9.0DCI1.ADDRESS0
OUT.HALF9.1DCI1.ADDRESS1
OUT.HALF10.0DCI1.DCI_DONE
OUT.HALF10.1DCI1.DATA
OUT.HALF11.0DCI1.SCLK
OUT.HALF11.1DCI1.N_OR_P
OUT.HALF12.1DCI1.UPDATE
OUT.HALF13.0DCI0.ADDRESS2
OUT.HALF14.0DCI0.ADDRESS0
OUT.HALF14.1DCI0.ADDRESS1
OUT.HALF15.0DCI0.DCI_DONE
OUT.HALF15.1DCI0.DATA
OUT.HALF16.0DCI0.SCLK
OUT.HALF16.1DCI0.N_OR_P
OUT.HALF17.1DCI0.UPDATE

Bitstream

virtex2 LL.V2P bittile 0
BitFrame
0 1 2 3
48 - - DCI0:LVDSBIAS[1] DCI0:LVDSBIAS[0]
47 - - DCI0:LVDSBIAS[3] DCI0:LVDSBIAS[2]
46 - - DCI0:LVDSBIAS[5] DCI0:LVDSBIAS[4]
45 - - DCI0:LVDSBIAS[7] DCI0:LVDSBIAS[6]
44 - - - DCI0:LVDSBIAS[8]
43 - - - -
42 - - DCI0:ENABLE -
41 - - - -
40 - - - -
39 - - DCI0:NMASK_TERM_SPLIT[0] DCI0:QUIET
38 - - DCI0:NMASK_TERM_SPLIT[2] DCI0:NMASK_TERM_SPLIT[1]
37 - - DCI0:NMASK_TERM_SPLIT[4] DCI0:NMASK_TERM_SPLIT[3]
36 - - DCI0:PMASK_TERM_VCC[1] DCI0:PMASK_TERM_VCC[0]
35 - - DCI0:PMASK_TERM_VCC[3] DCI0:PMASK_TERM_VCC[2]
34 - - DCI0:PMASK_TERM_SPLIT[0] DCI0:PMASK_TERM_VCC[4]
33 - - DCI0:PMASK_TERM_SPLIT[2] DCI0:PMASK_TERM_SPLIT[1]
32 - - DCI0:PMASK_TERM_SPLIT[4] DCI0:PMASK_TERM_SPLIT[3]
31 - - DCI0:TEST_ENABLE DCI0:FORCE_DONE_HIGH
30 - - - -
29 - - - -
28 - - - -
27 - - - -
26 - - - -
25 - - - -
24 - - - -
23 - - - -
22 - - - -
21 - - - -
20 - - - -
19 - - - -
18 - - - -
17 - - - -
16 - - - -
15 - - - -
14 - - - -
13 - - - -
12 - - - -
11 - - - -
10 - - - -
9 - - - -
8 - - - -
7 - - - -
6 - - - -
5 - - - -
4 - - - -
3 - - - -
2 - - - -
1 - - - -
0 - - - -
virtex2 LL.V2P bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
11 - - - - - - - - DCI1:PMASK_TERM_VCC[3] DCI1:PMASK_TERM_SPLIT[2] - DCI1:NMASK_TERM_SPLIT[0] DCI1:LVDSBIAS[4] DCI1:LVDSBIAS[7] - - MISC:M0PIN[1] MISC:M1PIN[1] MISC:ZCLK_DIV2[0] MISC:ZCLK_DIV2[2]
10 - - - - - - - - DCI1:PMASK_TERM_VCC[4] DCI1:PMASK_TERM_SPLIT[4] - DCI1:NMASK_TERM_SPLIT[2] DCI1:LVDSBIAS[3] - - - MISC:M0PIN[0] MISC:BCLK_DIV2[0] MISC:DCI_CLK_ENABLE MISC:ZCLK_DIV2[4]
9 - - - - - - - - DCI1:PMASK_TERM_SPLIT[0] DCI1:PMASK_TERM_SPLIT[1] - DCI1:QUIET DCI1:LVDSBIAS[5] DCI1:LVDSBIAS[6] - - MISC:M1PIN[0] MISC:BCLK_DIV2[1] - MISC:ZCLK_DIV2[1]
8 - - - - - - - - DCI1:PMASK_TERM_VCC[0] DCI1:FORCE_DONE_HIGH - DCI1:NMASK_TERM_SPLIT[3] DCI1:LVDSBIAS[0] - - - MISC:M2PIN[1] MISC:BCLK_DIV2[4] MISC:DISABLEVGGGENERATION MISC:RAISEVGG[1]
7 - - - - - - - - DCI1:PMASK_TERM_VCC[2] DCI1:PMASK_TERM_SPLIT[3] DCI1:ENABLE DCI1:NMASK_TERM_SPLIT[1] DCI1:LVDSBIAS[2] DCI1:LVDSBIAS[8] - - MISC:M2PIN[0] MISC:BCLK_DIV2[3] - MISC:ZCLK_DIV2[3]
6 - - - - - - - - DCI1:PMASK_TERM_VCC[1] DCI1:TEST_ENABLE - DCI1:NMASK_TERM_SPLIT[4] DCI1:LVDSBIAS[1] - - - MISC:DISABLEBANDGAP MISC:BCLK_DIV2[2] - MISC:RAISEVGG[0]
5 - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - -
DCI0:ENABLE 0.2.42
DCI0:FORCE_DONE_HIGH 0.3.31
DCI0:QUIET 0.3.39
DCI0:TEST_ENABLE 0.2.31
DCI1:ENABLE 1.10.7
DCI1:FORCE_DONE_HIGH 1.9.8
DCI1:QUIET 1.11.9
DCI1:TEST_ENABLE 1.9.6
MISC:DCI_CLK_ENABLE 1.18.10
MISC:DISABLEBANDGAP 1.16.6
MISC:DISABLEVGGGENERATION 1.18.8
non-inverted [0]
DCI0:LVDSBIAS 0.3.44 0.2.45 0.3.45 0.2.46 0.3.46 0.2.47 0.3.47 0.2.48 0.3.48
DCI1:LVDSBIAS 1.13.7 1.13.11 1.13.9 1.12.9 1.12.11 1.12.10 1.12.7 1.12.6 1.12.8
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
DCI0:NMASK_TERM_SPLIT 0.2.37 0.3.37 0.2.38 0.3.38 0.2.39
DCI0:PMASK_TERM_SPLIT 0.2.32 0.3.32 0.2.33 0.3.33 0.2.34
DCI0:PMASK_TERM_VCC 0.3.34 0.2.35 0.3.35 0.2.36 0.3.36
DCI1:NMASK_TERM_SPLIT 1.11.6 1.11.8 1.11.10 1.11.7 1.11.11
DCI1:PMASK_TERM_SPLIT 1.9.10 1.9.7 1.9.11 1.9.9 1.8.9
DCI1:PMASK_TERM_VCC 1.8.10 1.8.11 1.8.7 1.8.6 1.8.8
MISC:BCLK_DIV2 1.17.8 1.17.7 1.17.6 1.17.9 1.17.10
MISC:ZCLK_DIV2 1.19.10 1.19.7 1.19.11 1.19.9 1.18.11
non-inverted [4] [3] [2] [1] [0]
MISC:M0PIN 1.16.11 1.16.10
MISC:M1PIN 1.17.11 1.16.9
MISC:M2PIN 1.16.8 1.16.7
PULLUP 0 0
PULLDOWN 0 1
PULLNONE 1 0
MISC:RAISEVGG 1.19.8 1.19.6
non-inverted [1] [0]