Hard PCI logic

TODO: reverse, document

Tile PCI_W

Cells: 4

Bels PCILOGIC

virtex2 PCI_W bel PCILOGIC pins
Pin	Direction	PCILOGIC
FI[0]	in	CELL[1].OMUX[14]
FI[1]	in	CELL[1].OMUX[9]
FI[2]	in	CELL[2].OMUX[1]
FI[3]	in	CELL[2].OMUX[6]
SI[0]	in	CELL[1].DBL_E2[5]
SI[1]	in	CELL[1].DBL_E2[6]
SI[2]	in	CELL[1].DBL_E2[7]
SI[3]	in	CELL[1].DBL_E2[8]
SI[4]	in	CELL[1].DBL_E2[9]
SI[5]	in	CELL[1].DBL_E2_S[0]
SI[6]	in	CELL[1].DBL_E2_S[1]
SI[7]	in	CELL[2].DBL_E2[2]
SI[8]	in	CELL[2].DBL_E2[3]
SI[9]	in	CELL[2].DBL_E2[4]
OUT[0]	out	CELL[1].OUT_PCI[0]
OUT[1]	out	CELL[1].OUT_PCI[1]
OUT[2]	out	CELL[0].OUT_PCI[0]
OUT[3]	out	CELL[2].OUT_PCI[0]
OUT[4]	out	CELL[2].OUT_PCI[1]
OUT[5]	out	CELL[3].OUT_PCI[0]

Bel wires

virtex2 PCI_W bel wires
Wire	Pins
CELL[0].OUT_PCI[0]	PCILOGIC.OUT[2]
CELL[1].OMUX[9]	PCILOGIC.FI[1]
CELL[1].OMUX[14]	PCILOGIC.FI[0]
CELL[1].DBL_E2[5]	PCILOGIC.SI[0]
CELL[1].DBL_E2[6]	PCILOGIC.SI[1]
CELL[1].DBL_E2[7]	PCILOGIC.SI[2]
CELL[1].DBL_E2[8]	PCILOGIC.SI[3]
CELL[1].DBL_E2[9]	PCILOGIC.SI[4]
CELL[1].DBL_E2_S[0]	PCILOGIC.SI[5]
CELL[1].DBL_E2_S[1]	PCILOGIC.SI[6]
CELL[1].OUT_PCI[0]	PCILOGIC.OUT[0]
CELL[1].OUT_PCI[1]	PCILOGIC.OUT[1]
CELL[2].OMUX[1]	PCILOGIC.FI[2]
CELL[2].OMUX[6]	PCILOGIC.FI[3]
CELL[2].DBL_E2[2]	PCILOGIC.SI[7]
CELL[2].DBL_E2[3]	PCILOGIC.SI[8]
CELL[2].DBL_E2[4]	PCILOGIC.SI[9]
CELL[2].OUT_PCI[0]	PCILOGIC.OUT[3]
CELL[2].OUT_PCI[1]	PCILOGIC.OUT[4]
CELL[3].OUT_PCI[0]	PCILOGIC.OUT[5]

Tile PCI_E

Cells: 4

Bels PCILOGIC

virtex2 PCI_E bel PCILOGIC pins
Pin	Direction	PCILOGIC
FI[0]	in	CELL[1].OMUX[8]
FI[1]	in	CELL[1].OMUX[13]
FI[2]	in	CELL[2].OMUX[2]
FI[3]	in	CELL[2].OMUX[7]
SI[0]	in	CELL[1].DBL_W2[5]
SI[1]	in	CELL[1].DBL_W2[6]
SI[2]	in	CELL[1].DBL_W2[7]
SI[3]	in	CELL[1].DBL_W2[8]
SI[4]	in	CELL[1].DBL_W2[9]
SI[5]	in	CELL[2].DBL_W2[0]
SI[6]	in	CELL[2].DBL_W2[1]
SI[7]	in	CELL[2].DBL_W2[2]
SI[8]	in	CELL[2].DBL_W2[3]
SI[9]	in	CELL[2].DBL_W2[4]
OUT[0]	out	CELL[1].OUT_PCI[0]
OUT[1]	out	CELL[1].OUT_PCI[1]
OUT[2]	out	CELL[0].OUT_PCI[0]
OUT[3]	out	CELL[2].OUT_PCI[0]
OUT[4]	out	CELL[2].OUT_PCI[1]
OUT[5]	out	CELL[3].OUT_PCI[0]

Bel wires

virtex2 PCI_E bel wires
Wire	Pins
CELL[0].OUT_PCI[0]	PCILOGIC.OUT[2]
CELL[1].OMUX[8]	PCILOGIC.FI[0]
CELL[1].OMUX[13]	PCILOGIC.FI[1]
CELL[1].DBL_W2[5]	PCILOGIC.SI[0]
CELL[1].DBL_W2[6]	PCILOGIC.SI[1]
CELL[1].DBL_W2[7]	PCILOGIC.SI[2]
CELL[1].DBL_W2[8]	PCILOGIC.SI[3]
CELL[1].DBL_W2[9]	PCILOGIC.SI[4]
CELL[1].OUT_PCI[0]	PCILOGIC.OUT[0]
CELL[1].OUT_PCI[1]	PCILOGIC.OUT[1]
CELL[2].OMUX[2]	PCILOGIC.FI[2]
CELL[2].OMUX[7]	PCILOGIC.FI[3]
CELL[2].DBL_W2[0]	PCILOGIC.SI[5]
CELL[2].DBL_W2[1]	PCILOGIC.SI[6]
CELL[2].DBL_W2[2]	PCILOGIC.SI[7]
CELL[2].DBL_W2[3]	PCILOGIC.SI[8]
CELL[2].DBL_W2[4]	PCILOGIC.SI[9]
CELL[2].OUT_PCI[0]	PCILOGIC.OUT[3]
CELL[2].OUT_PCI[1]	PCILOGIC.OUT[4]
CELL[3].OUT_PCI[0]	PCILOGIC.OUT[5]