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Hard PCI logic

TODO: reverse, document

Tile REG_L

Cells: 4

Bel PCILOGIC

virtex2 REG_L bel PCILOGIC
PinDirectionWires
FI0inputTCELL1:OMUX14
FI1inputTCELL1:OMUX9
FI2inputTCELL2:OMUX1
FI3inputTCELL2:OMUX6
OUT0outputTCELL1:OUT.PCI0
OUT1outputTCELL1:OUT.PCI1
OUT2outputTCELL0:OUT.PCI0
OUT3outputTCELL2:OUT.PCI0
OUT4outputTCELL2:OUT.PCI1
OUT5outputTCELL3:OUT.PCI0
SI0inputTCELL1:DBL.E5.2
SI1inputTCELL1:DBL.E6.2
SI2inputTCELL1:DBL.E7.2
SI3inputTCELL1:DBL.E8.2
SI4inputTCELL1:DBL.E9.2
SI5inputTCELL1:DBL.E0.3
SI6inputTCELL1:DBL.E1.3
SI7inputTCELL2:DBL.E2.2
SI8inputTCELL2:DBL.E3.2
SI9inputTCELL2:DBL.E4.2

Bel wires

virtex2 REG_L bel wires
WirePins
TCELL0:OUT.PCI0PCILOGIC.OUT2
TCELL1:OMUX9PCILOGIC.FI1
TCELL1:OMUX14PCILOGIC.FI0
TCELL1:DBL.E0.3PCILOGIC.SI5
TCELL1:DBL.E1.3PCILOGIC.SI6
TCELL1:DBL.E5.2PCILOGIC.SI0
TCELL1:DBL.E6.2PCILOGIC.SI1
TCELL1:DBL.E7.2PCILOGIC.SI2
TCELL1:DBL.E8.2PCILOGIC.SI3
TCELL1:DBL.E9.2PCILOGIC.SI4
TCELL1:OUT.PCI0PCILOGIC.OUT0
TCELL1:OUT.PCI1PCILOGIC.OUT1
TCELL2:OMUX1PCILOGIC.FI2
TCELL2:OMUX6PCILOGIC.FI3
TCELL2:DBL.E2.2PCILOGIC.SI7
TCELL2:DBL.E3.2PCILOGIC.SI8
TCELL2:DBL.E4.2PCILOGIC.SI9
TCELL2:OUT.PCI0PCILOGIC.OUT3
TCELL2:OUT.PCI1PCILOGIC.OUT4
TCELL3:OUT.PCI0PCILOGIC.OUT5

Tile REG_R

Cells: 4

Bel PCILOGIC

virtex2 REG_R bel PCILOGIC
PinDirectionWires
FI0inputTCELL1:OMUX8
FI1inputTCELL1:OMUX13
FI2inputTCELL2:OMUX2
FI3inputTCELL2:OMUX7
OUT0outputTCELL1:OUT.PCI0
OUT1outputTCELL1:OUT.PCI1
OUT2outputTCELL0:OUT.PCI0
OUT3outputTCELL2:OUT.PCI0
OUT4outputTCELL2:OUT.PCI1
OUT5outputTCELL3:OUT.PCI0
SI0inputTCELL1:DBL.W5.2
SI1inputTCELL1:DBL.W6.2
SI2inputTCELL1:DBL.W7.2
SI3inputTCELL1:DBL.W8.2
SI4inputTCELL1:DBL.W9.2
SI5inputTCELL2:DBL.W0.2
SI6inputTCELL2:DBL.W1.2
SI7inputTCELL2:DBL.W2.2
SI8inputTCELL2:DBL.W3.2
SI9inputTCELL2:DBL.W4.2

Bel wires

virtex2 REG_R bel wires
WirePins
TCELL0:OUT.PCI0PCILOGIC.OUT2
TCELL1:OMUX8PCILOGIC.FI0
TCELL1:OMUX13PCILOGIC.FI1
TCELL1:DBL.W5.2PCILOGIC.SI0
TCELL1:DBL.W6.2PCILOGIC.SI1
TCELL1:DBL.W7.2PCILOGIC.SI2
TCELL1:DBL.W8.2PCILOGIC.SI3
TCELL1:DBL.W9.2PCILOGIC.SI4
TCELL1:OUT.PCI0PCILOGIC.OUT0
TCELL1:OUT.PCI1PCILOGIC.OUT1
TCELL2:OMUX2PCILOGIC.FI2
TCELL2:OMUX7PCILOGIC.FI3
TCELL2:DBL.W0.2PCILOGIC.SI5
TCELL2:DBL.W1.2PCILOGIC.SI6
TCELL2:DBL.W2.2PCILOGIC.SI7
TCELL2:DBL.W3.2PCILOGIC.SI8
TCELL2:DBL.W4.2PCILOGIC.SI9
TCELL2:OUT.PCI0PCILOGIC.OUT3
TCELL2:OUT.PCI1PCILOGIC.OUT4
TCELL3:OUT.PCI0PCILOGIC.OUT5