TODO: reverse, document
Cells: 4
IRIs: 0
virtex2 REG_L bel PCILOGIC
| Pin | Direction | Wires |
|---|
| FI0 | input | TCELL1:OMUX14 |
| FI1 | input | TCELL1:OMUX9 |
| FI2 | input | TCELL2:OMUX1 |
| FI3 | input | TCELL2:OMUX6 |
| OUT0 | output | TCELL1:OUT.PCI0 |
| OUT1 | output | TCELL1:OUT.PCI1 |
| OUT2 | output | TCELL0:OUT.PCI0 |
| OUT3 | output | TCELL2:OUT.PCI0 |
| OUT4 | output | TCELL2:OUT.PCI1 |
| OUT5 | output | TCELL3:OUT.PCI0 |
| SI0 | input | TCELL1:DBL.E5.2 |
| SI1 | input | TCELL1:DBL.E6.2 |
| SI2 | input | TCELL1:DBL.E7.2 |
| SI3 | input | TCELL1:DBL.E8.2 |
| SI4 | input | TCELL1:DBL.E9.2 |
| SI5 | input | TCELL1:DBL.E0.3 |
| SI6 | input | TCELL1:DBL.E1.3 |
| SI7 | input | TCELL2:DBL.E2.2 |
| SI8 | input | TCELL2:DBL.E3.2 |
| SI9 | input | TCELL2:DBL.E4.2 |
virtex2 REG_L bel wires
| Wire | Pins |
|---|
| TCELL0:OUT.PCI0 | PCILOGIC.OUT2 |
| TCELL1:OMUX9 | PCILOGIC.FI1 |
| TCELL1:OMUX14 | PCILOGIC.FI0 |
| TCELL1:DBL.E0.3 | PCILOGIC.SI5 |
| TCELL1:DBL.E1.3 | PCILOGIC.SI6 |
| TCELL1:DBL.E5.2 | PCILOGIC.SI0 |
| TCELL1:DBL.E6.2 | PCILOGIC.SI1 |
| TCELL1:DBL.E7.2 | PCILOGIC.SI2 |
| TCELL1:DBL.E8.2 | PCILOGIC.SI3 |
| TCELL1:DBL.E9.2 | PCILOGIC.SI4 |
| TCELL1:OUT.PCI0 | PCILOGIC.OUT0 |
| TCELL1:OUT.PCI1 | PCILOGIC.OUT1 |
| TCELL2:OMUX1 | PCILOGIC.FI2 |
| TCELL2:OMUX6 | PCILOGIC.FI3 |
| TCELL2:DBL.E2.2 | PCILOGIC.SI7 |
| TCELL2:DBL.E3.2 | PCILOGIC.SI8 |
| TCELL2:DBL.E4.2 | PCILOGIC.SI9 |
| TCELL2:OUT.PCI0 | PCILOGIC.OUT3 |
| TCELL2:OUT.PCI1 | PCILOGIC.OUT4 |
| TCELL3:OUT.PCI0 | PCILOGIC.OUT5 |
Cells: 4
IRIs: 0
virtex2 REG_R bel PCILOGIC
| Pin | Direction | Wires |
|---|
| FI0 | input | TCELL1:OMUX8 |
| FI1 | input | TCELL1:OMUX13 |
| FI2 | input | TCELL2:OMUX2 |
| FI3 | input | TCELL2:OMUX7 |
| OUT0 | output | TCELL1:OUT.PCI0 |
| OUT1 | output | TCELL1:OUT.PCI1 |
| OUT2 | output | TCELL0:OUT.PCI0 |
| OUT3 | output | TCELL2:OUT.PCI0 |
| OUT4 | output | TCELL2:OUT.PCI1 |
| OUT5 | output | TCELL3:OUT.PCI0 |
| SI0 | input | TCELL1:DBL.W5.2 |
| SI1 | input | TCELL1:DBL.W6.2 |
| SI2 | input | TCELL1:DBL.W7.2 |
| SI3 | input | TCELL1:DBL.W8.2 |
| SI4 | input | TCELL1:DBL.W9.2 |
| SI5 | input | TCELL2:DBL.W0.2 |
| SI6 | input | TCELL2:DBL.W1.2 |
| SI7 | input | TCELL2:DBL.W2.2 |
| SI8 | input | TCELL2:DBL.W3.2 |
| SI9 | input | TCELL2:DBL.W4.2 |
virtex2 REG_R bel wires
| Wire | Pins |
|---|
| TCELL0:OUT.PCI0 | PCILOGIC.OUT2 |
| TCELL1:OMUX8 | PCILOGIC.FI0 |
| TCELL1:OMUX13 | PCILOGIC.FI1 |
| TCELL1:DBL.W5.2 | PCILOGIC.SI0 |
| TCELL1:DBL.W6.2 | PCILOGIC.SI1 |
| TCELL1:DBL.W7.2 | PCILOGIC.SI2 |
| TCELL1:DBL.W8.2 | PCILOGIC.SI3 |
| TCELL1:DBL.W9.2 | PCILOGIC.SI4 |
| TCELL1:OUT.PCI0 | PCILOGIC.OUT0 |
| TCELL1:OUT.PCI1 | PCILOGIC.OUT1 |
| TCELL2:OMUX2 | PCILOGIC.FI2 |
| TCELL2:OMUX7 | PCILOGIC.FI3 |
| TCELL2:DBL.W0.2 | PCILOGIC.SI5 |
| TCELL2:DBL.W1.2 | PCILOGIC.SI6 |
| TCELL2:DBL.W2.2 | PCILOGIC.SI7 |
| TCELL2:DBL.W3.2 | PCILOGIC.SI8 |
| TCELL2:DBL.W4.2 | PCILOGIC.SI9 |
| TCELL2:OUT.PCI0 | PCILOGIC.OUT3 |
| TCELL2:OUT.PCI1 | PCILOGIC.OUT4 |
| TCELL3:OUT.PCI0 | PCILOGIC.OUT5 |