Multi-gigabit transceivers — Virtex 2 Pro X

TODO: document

Tile GIGABIT10.B

Cells: 9 IRIs: 0

Bel GT10

virtex2 GIGABIT10.B bel GT10
Pin	Direction	Wires
CHBONDDONE	output	TCELL0:OUT.FAN0
CHBONDI0	input	TCELL0:IMUX.G0.DATA0
CHBONDI1	input	TCELL0:IMUX.G1.DATA0
CHBONDI2	input	TCELL0:IMUX.G2.DATA0
CHBONDI3	input	TCELL0:IMUX.G3.DATA0
CHBONDI4	input	TCELL0:IMUX.G0.DATA1
CHBONDO0	output	TCELL0:OUT.FAN2
CHBONDO1	output	TCELL0:OUT.FAN3
CHBONDO2	output	TCELL0:OUT.FAN4
CHBONDO3	output	TCELL0:OUT.FAN5
CHBONDO4	output	TCELL0:OUT.FAN6
ENCHANSYNC	input	TCELL0:IMUX.G1.DATA1
ENMCOMMAALIGN	input	TCELL1:IMUX.G1.DATA7
ENPCOMMAALIGN	input	TCELL1:IMUX.G1.DATA4
LOOPBACK0	input	TCELL0:IMUX.G0.DATA3
LOOPBACK1	input	TCELL0:IMUX.G1.DATA3
PMAINIT	input	TCELL0:IMUX.G3.DATA1
PMAREGADDR0	input	TCELL6:IMUX.G0.DATA6
PMAREGADDR1	input	TCELL6:IMUX.G1.DATA6
PMAREGADDR2	input	TCELL6:IMUX.G2.DATA6
PMAREGADDR3	input	TCELL6:IMUX.G3.DATA6
PMAREGADDR4	input	TCELL6:IMUX.G0.DATA7
PMAREGADDR5	input	TCELL6:IMUX.G1.DATA7
PMAREGDATAIN0	input	TCELL6:IMUX.G0.DATA4
PMAREGDATAIN1	input	TCELL6:IMUX.G1.DATA4
PMAREGDATAIN2	input	TCELL6:IMUX.G2.DATA4
PMAREGDATAIN3	input	TCELL6:IMUX.G3.DATA4
PMAREGDATAIN4	input	TCELL6:IMUX.G0.DATA5
PMAREGDATAIN5	input	TCELL6:IMUX.G1.DATA5
PMAREGDATAIN6	input	TCELL6:IMUX.G2.DATA5
PMAREGDATAIN7	input	TCELL6:IMUX.G3.DATA5
PMAREGRW	input	TCELL6:IMUX.G1.DATA3
PMAREGSTROBE	input	TCELL6:IMUX.G2.DATA3
PMARXLOCK	output	TCELL0:OUT.SEC8
PMARXLOCKSEL0	input	TCELL0:IMUX.G3.DATA6
PMARXLOCKSEL1	input	TCELL0:IMUX.G0.DATA7
POWERDOWN	input	TCELL0:IMUX.G0.DATA2
REFCLK	input	TCELL0:IMUX.DCMCLK2
REFCLK2	input	TCELL0:IMUX.DCMCLK3
REFCLKBSEL	input	TCELL0:IMUX.G3.DATA4
REFCLKSEL	input	TCELL0:IMUX.G2.DATA1
RXBLOCKSYNC64B66BUSE	input	TCELL4:IMUX.G1.DATA6
RXBUFSTATUS0	output	TCELL0:OUT.SEC15
RXBUFSTATUS1	output	TCELL0:OUT.SEC14
RXCHARISCOMMA0	output	TCELL1:OUT.SEC11
RXCHARISCOMMA1	output	TCELL2:OUT.SEC11
RXCHARISCOMMA2	output	TCELL3:OUT.SEC11
RXCHARISCOMMA3	output	TCELL4:OUT.SEC11
RXCHARISCOMMA4	output	TCELL5:OUT.SEC11
RXCHARISCOMMA5	output	TCELL6:OUT.SEC11
RXCHARISCOMMA6	output	TCELL7:OUT.SEC11
RXCHARISCOMMA7	output	TCELL8:OUT.SEC11
RXCHARISK0	output	TCELL1:OUT.SEC12
RXCHARISK1	output	TCELL2:OUT.SEC12
RXCHARISK2	output	TCELL3:OUT.SEC12
RXCHARISK3	output	TCELL4:OUT.SEC12
RXCHARISK4	output	TCELL5:OUT.SEC12
RXCHARISK5	output	TCELL6:OUT.SEC12
RXCHARISK6	output	TCELL7:OUT.SEC12
RXCHARISK7	output	TCELL8:OUT.SEC12
RXCHECKINGCRC	output	TCELL4:OUT.SEC8
RXCLKCORCNT0	output	TCELL0:OUT.SEC11
RXCLKCORCNT1	output	TCELL0:OUT.SEC10
RXCLKCORCNT2	output	TCELL0:OUT.SEC9
RXCOMMADET	output	TCELL0:OUT.SEC12
RXCOMMADETUSE	input	TCELL4:IMUX.G2.DATA6
RXCRCERR	output	TCELL3:OUT.SEC8
RXDATA0	output	TCELL1:OUT.FAN0
RXDATA1	output	TCELL1:OUT.FAN1
RXDATA10	output	TCELL3:OUT.FAN2
RXDATA11	output	TCELL3:OUT.FAN3
RXDATA12	output	TCELL4:OUT.FAN0
RXDATA13	output	TCELL4:OUT.FAN1
RXDATA14	output	TCELL4:OUT.FAN2
RXDATA15	output	TCELL4:OUT.FAN3
RXDATA16	output	TCELL5:OUT.FAN0
RXDATA17	output	TCELL5:OUT.FAN1
RXDATA18	output	TCELL5:OUT.FAN2
RXDATA19	output	TCELL5:OUT.FAN3
RXDATA2	output	TCELL1:OUT.FAN2
RXDATA20	output	TCELL6:OUT.FAN0
RXDATA21	output	TCELL6:OUT.FAN1
RXDATA22	output	TCELL6:OUT.FAN2
RXDATA23	output	TCELL6:OUT.FAN3
RXDATA24	output	TCELL7:OUT.FAN0
RXDATA25	output	TCELL7:OUT.FAN1
RXDATA26	output	TCELL7:OUT.FAN2
RXDATA27	output	TCELL7:OUT.FAN3
RXDATA28	output	TCELL8:OUT.FAN0
RXDATA29	output	TCELL8:OUT.FAN1
RXDATA3	output	TCELL1:OUT.FAN3
RXDATA30	output	TCELL8:OUT.FAN2
RXDATA31	output	TCELL8:OUT.FAN3
RXDATA32	output	TCELL1:OUT.FAN4
RXDATA33	output	TCELL1:OUT.FAN5
RXDATA34	output	TCELL1:OUT.FAN6
RXDATA35	output	TCELL1:OUT.FAN7
RXDATA36	output	TCELL2:OUT.FAN4
RXDATA37	output	TCELL2:OUT.FAN5
RXDATA38	output	TCELL2:OUT.FAN6
RXDATA39	output	TCELL2:OUT.FAN7
RXDATA4	output	TCELL2:OUT.FAN0
RXDATA40	output	TCELL3:OUT.FAN4
RXDATA41	output	TCELL3:OUT.FAN5
RXDATA42	output	TCELL3:OUT.FAN6
RXDATA43	output	TCELL3:OUT.FAN7
RXDATA44	output	TCELL4:OUT.FAN4
RXDATA45	output	TCELL4:OUT.FAN5
RXDATA46	output	TCELL4:OUT.FAN6
RXDATA47	output	TCELL4:OUT.FAN7
RXDATA48	output	TCELL5:OUT.FAN4
RXDATA49	output	TCELL5:OUT.FAN5
RXDATA5	output	TCELL2:OUT.FAN1
RXDATA50	output	TCELL5:OUT.FAN6
RXDATA51	output	TCELL5:OUT.FAN7
RXDATA52	output	TCELL6:OUT.FAN4
RXDATA53	output	TCELL6:OUT.FAN5
RXDATA54	output	TCELL6:OUT.FAN6
RXDATA55	output	TCELL6:OUT.FAN7
RXDATA56	output	TCELL7:OUT.FAN4
RXDATA57	output	TCELL7:OUT.FAN5
RXDATA58	output	TCELL7:OUT.FAN6
RXDATA59	output	TCELL7:OUT.FAN7
RXDATA6	output	TCELL2:OUT.FAN2
RXDATA60	output	TCELL8:OUT.FAN4
RXDATA61	output	TCELL8:OUT.FAN5
RXDATA62	output	TCELL8:OUT.FAN6
RXDATA63	output	TCELL8:OUT.FAN7
RXDATA7	output	TCELL2:OUT.FAN3
RXDATA8	output	TCELL3:OUT.FAN0
RXDATA9	output	TCELL3:OUT.FAN1
RXDATAWIDTH0	input	TCELL4:IMUX.G2.DATA4
RXDATAWIDTH1	input	TCELL4:IMUX.G3.DATA4
RXDEC64B66BUSE	input	TCELL5:IMUX.G0.DATA4
RXDEC8B10BUSE	input	TCELL6:IMUX.G0.DATA3
RXDESCRAM64B66BUSE	input	TCELL4:IMUX.G0.DATA6
RXDISPERR0	output	TCELL1:OUT.SEC14
RXDISPERR1	output	TCELL2:OUT.SEC14
RXDISPERR2	output	TCELL3:OUT.SEC14
RXDISPERR3	output	TCELL4:OUT.SEC14
RXDISPERR4	output	TCELL5:OUT.SEC14
RXDISPERR5	output	TCELL6:OUT.SEC14
RXDISPERR6	output	TCELL7:OUT.SEC14
RXDISPERR7	output	TCELL8:OUT.SEC14
RXIGNOREBTF	input	TCELL5:IMUX.G1.DATA3
RXINTDATAWIDTH0	input	TCELL4:IMUX.G2.DATA5
RXINTDATAWIDTH1	input	TCELL4:IMUX.G3.DATA5
RXLOSSOFSYNC0	output	TCELL1:OUT.SEC8
RXLOSSOFSYNC1	output	TCELL2:OUT.SEC8
RXNOTINTABLE0	output	TCELL1:OUT.SEC13
RXNOTINTABLE1	output	TCELL2:OUT.SEC13
RXNOTINTABLE2	output	TCELL3:OUT.SEC13
RXNOTINTABLE3	output	TCELL4:OUT.SEC13
RXNOTINTABLE4	output	TCELL5:OUT.SEC13
RXNOTINTABLE5	output	TCELL6:OUT.SEC13
RXNOTINTABLE6	output	TCELL7:OUT.SEC13
RXNOTINTABLE7	output	TCELL8:OUT.SEC13
RXPOLARITY	input	TCELL0:IMUX.G1.DATA2
RXREALIGN	output	TCELL0:OUT.SEC13
RXRECCLK	output	TCELL0:OUT.FAN1
RXRESET	input	TCELL0:IMUX.SR0
RXRUNDISP0	output	TCELL1:OUT.SEC15
RXRUNDISP1	output	TCELL2:OUT.SEC15
RXRUNDISP2	output	TCELL3:OUT.SEC15
RXRUNDISP3	output	TCELL4:OUT.SEC15
RXRUNDISP4	output	TCELL5:OUT.SEC15
RXRUNDISP5	output	TCELL6:OUT.SEC15
RXRUNDISP6	output	TCELL7:OUT.SEC15
RXRUNDISP7	output	TCELL8:OUT.SEC15
RXSLIDE	input	TCELL4:IMUX.G3.DATA6
RXUSRCLK	input	TCELL0:IMUX.DCMCLK0
RXUSRCLK2	input	TCELL0:IMUX.DCMCLK1
SCANEN	input	TCELL5:IMUX.G1.DATA6
SCANIN	input	TCELL5:IMUX.G0.DATA6
SCANMODE	input	TCELL5:IMUX.G2.DATA6
SCANOUT	output	TCELL5:OUT.SEC8
TESTMEMORY	input	TCELL5:IMUX.G0.DATA3
TXBUFERR	output	TCELL8:OUT.SEC8
TXBYPASS8B10B0	input	TCELL1:IMUX.G0.DATA2
TXBYPASS8B10B1	input	TCELL2:IMUX.G0.DATA2
TXBYPASS8B10B2	input	TCELL3:IMUX.G0.DATA2
TXBYPASS8B10B3	input	TCELL4:IMUX.G0.DATA2
TXBYPASS8B10B4	input	TCELL5:IMUX.G0.DATA2
TXBYPASS8B10B5	input	TCELL6:IMUX.G0.DATA2
TXBYPASS8B10B6	input	TCELL7:IMUX.G0.DATA2
TXBYPASS8B10B7	input	TCELL8:IMUX.G0.DATA2
TXCHARDISPMODE0	input	TCELL1:IMUX.G2.DATA2
TXCHARDISPMODE1	input	TCELL2:IMUX.G2.DATA2
TXCHARDISPMODE2	input	TCELL3:IMUX.G2.DATA2
TXCHARDISPMODE3	input	TCELL4:IMUX.G2.DATA2
TXCHARDISPMODE4	input	TCELL5:IMUX.G2.DATA2
TXCHARDISPMODE5	input	TCELL6:IMUX.G2.DATA2
TXCHARDISPMODE6	input	TCELL7:IMUX.G2.DATA2
TXCHARDISPMODE7	input	TCELL8:IMUX.G2.DATA2
TXCHARDISPVAL0	input	TCELL1:IMUX.G3.DATA2
TXCHARDISPVAL1	input	TCELL2:IMUX.G3.DATA2
TXCHARDISPVAL2	input	TCELL3:IMUX.G3.DATA2
TXCHARDISPVAL3	input	TCELL4:IMUX.G3.DATA2
TXCHARDISPVAL4	input	TCELL5:IMUX.G3.DATA2
TXCHARDISPVAL5	input	TCELL6:IMUX.G3.DATA2
TXCHARDISPVAL6	input	TCELL7:IMUX.G3.DATA2
TXCHARDISPVAL7	input	TCELL8:IMUX.G3.DATA2
TXCHARISK0	input	TCELL1:IMUX.G1.DATA2
TXCHARISK1	input	TCELL2:IMUX.G1.DATA2
TXCHARISK2	input	TCELL3:IMUX.G1.DATA2
TXCHARISK3	input	TCELL4:IMUX.G1.DATA2
TXCHARISK4	input	TCELL5:IMUX.G1.DATA2
TXCHARISK5	input	TCELL6:IMUX.G1.DATA2
TXCHARISK6	input	TCELL7:IMUX.G1.DATA2
TXCHARISK7	input	TCELL8:IMUX.G1.DATA2
TXDATA0	input	TCELL1:IMUX.G0.DATA0
TXDATA1	input	TCELL1:IMUX.G1.DATA0
TXDATA10	input	TCELL3:IMUX.G2.DATA0
TXDATA11	input	TCELL3:IMUX.G3.DATA0
TXDATA12	input	TCELL4:IMUX.G0.DATA0
TXDATA13	input	TCELL4:IMUX.G1.DATA0
TXDATA14	input	TCELL4:IMUX.G2.DATA0
TXDATA15	input	TCELL4:IMUX.G3.DATA0
TXDATA16	input	TCELL5:IMUX.G0.DATA0
TXDATA17	input	TCELL5:IMUX.G1.DATA0
TXDATA18	input	TCELL5:IMUX.G2.DATA0
TXDATA19	input	TCELL5:IMUX.G3.DATA0
TXDATA2	input	TCELL1:IMUX.G2.DATA0
TXDATA20	input	TCELL6:IMUX.G0.DATA0
TXDATA21	input	TCELL6:IMUX.G1.DATA0
TXDATA22	input	TCELL6:IMUX.G2.DATA0
TXDATA23	input	TCELL6:IMUX.G3.DATA0
TXDATA24	input	TCELL7:IMUX.G0.DATA0
TXDATA25	input	TCELL7:IMUX.G1.DATA0
TXDATA26	input	TCELL7:IMUX.G2.DATA0
TXDATA27	input	TCELL7:IMUX.G3.DATA0
TXDATA28	input	TCELL8:IMUX.G0.DATA0
TXDATA29	input	TCELL8:IMUX.G1.DATA0
TXDATA3	input	TCELL1:IMUX.G3.DATA0
TXDATA30	input	TCELL8:IMUX.G2.DATA0
TXDATA31	input	TCELL8:IMUX.G3.DATA0
TXDATA32	input	TCELL1:IMUX.G0.DATA1
TXDATA33	input	TCELL1:IMUX.G1.DATA1
TXDATA34	input	TCELL1:IMUX.G2.DATA1
TXDATA35	input	TCELL1:IMUX.G3.DATA1
TXDATA36	input	TCELL2:IMUX.G0.DATA1
TXDATA37	input	TCELL2:IMUX.G1.DATA1
TXDATA38	input	TCELL2:IMUX.G2.DATA1
TXDATA39	input	TCELL2:IMUX.G3.DATA1
TXDATA4	input	TCELL2:IMUX.G0.DATA0
TXDATA40	input	TCELL3:IMUX.G0.DATA1
TXDATA41	input	TCELL3:IMUX.G1.DATA1
TXDATA42	input	TCELL3:IMUX.G2.DATA1
TXDATA43	input	TCELL3:IMUX.G3.DATA1
TXDATA44	input	TCELL4:IMUX.G0.DATA1
TXDATA45	input	TCELL4:IMUX.G1.DATA1
TXDATA46	input	TCELL4:IMUX.G2.DATA1
TXDATA47	input	TCELL4:IMUX.G3.DATA1
TXDATA48	input	TCELL5:IMUX.G0.DATA1
TXDATA49	input	TCELL5:IMUX.G1.DATA1
TXDATA5	input	TCELL2:IMUX.G1.DATA0
TXDATA50	input	TCELL5:IMUX.G2.DATA1
TXDATA51	input	TCELL5:IMUX.G3.DATA1
TXDATA52	input	TCELL6:IMUX.G0.DATA1
TXDATA53	input	TCELL6:IMUX.G1.DATA1
TXDATA54	input	TCELL6:IMUX.G2.DATA1
TXDATA55	input	TCELL6:IMUX.G3.DATA1
TXDATA56	input	TCELL7:IMUX.G0.DATA1
TXDATA57	input	TCELL7:IMUX.G1.DATA1
TXDATA58	input	TCELL7:IMUX.G2.DATA1
TXDATA59	input	TCELL7:IMUX.G3.DATA1
TXDATA6	input	TCELL2:IMUX.G2.DATA0
TXDATA60	input	TCELL8:IMUX.G0.DATA1
TXDATA61	input	TCELL8:IMUX.G1.DATA1
TXDATA62	input	TCELL8:IMUX.G2.DATA1
TXDATA63	input	TCELL8:IMUX.G3.DATA1
TXDATA7	input	TCELL2:IMUX.G3.DATA0
TXDATA8	input	TCELL3:IMUX.G0.DATA0
TXDATA9	input	TCELL3:IMUX.G1.DATA0
TXDATAWIDTH0	input	TCELL4:IMUX.G0.DATA4
TXDATAWIDTH1	input	TCELL4:IMUX.G1.DATA4
TXENC64B66BUSE	input	TCELL5:IMUX.G3.DATA3
TXENC8B10BUSE	input	TCELL5:IMUX.G2.DATA3
TXFORCECRCERR	input	TCELL4:IMUX.G3.DATA3
TXGEARBOX64B66BUSE	input	TCELL5:IMUX.G2.DATA4
TXINHIBIT	input	TCELL0:IMUX.G3.DATA3
TXINTDATAWIDTH0	input	TCELL4:IMUX.G0.DATA5
TXINTDATAWIDTH1	input	TCELL4:IMUX.G1.DATA5
TXKERR0	output	TCELL1:OUT.SEC9
TXKERR1	output	TCELL2:OUT.SEC9
TXKERR2	output	TCELL3:OUT.SEC9
TXKERR3	output	TCELL4:OUT.SEC9
TXKERR4	output	TCELL5:OUT.SEC9
TXKERR5	output	TCELL6:OUT.SEC9
TXKERR6	output	TCELL7:OUT.SEC9
TXKERR7	output	TCELL8:OUT.SEC9
TXOUTCLK	output	TCELL0:OUT.FAN7
TXPOLARITY	input	TCELL0:IMUX.G2.DATA3
TXRESET	input	TCELL1:IMUX.SR0
TXRUNDISP0	output	TCELL1:OUT.SEC10
TXRUNDISP1	output	TCELL2:OUT.SEC10
TXRUNDISP2	output	TCELL3:OUT.SEC10
TXRUNDISP3	output	TCELL4:OUT.SEC10
TXRUNDISP4	output	TCELL5:OUT.SEC10
TXRUNDISP5	output	TCELL6:OUT.SEC10
TXRUNDISP6	output	TCELL7:OUT.SEC10
TXRUNDISP7	output	TCELL8:OUT.SEC10
TXSCRAM64B66BUSE	input	TCELL5:IMUX.G1.DATA4
TXUSRCLK	input	TCELL1:IMUX.CLK0
TXUSRCLK2	input	TCELL1:IMUX.CLK1

Bel IPAD_RXP

virtex2 GIGABIT10.B bel IPAD_RXP
Pin	Direction	Wires

Bel IPAD_RXN

virtex2 GIGABIT10.B bel IPAD_RXN
Pin	Direction	Wires

Bel OPAD_TXP

virtex2 GIGABIT10.B bel OPAD_TXP
Pin	Direction	Wires

Bel OPAD_TXN

virtex2 GIGABIT10.B bel OPAD_TXN
Pin	Direction	Wires

Bel wires

virtex2 GIGABIT10.B bel wires
Wire	Pins
TCELL0:IMUX.DCMCLK0	GT10.RXUSRCLK
TCELL0:IMUX.DCMCLK1	GT10.RXUSRCLK2
TCELL0:IMUX.DCMCLK2	GT10.REFCLK
TCELL0:IMUX.DCMCLK3	GT10.REFCLK2
TCELL0:IMUX.SR0	GT10.RXRESET
TCELL0:IMUX.G0.DATA0	GT10.CHBONDI0
TCELL0:IMUX.G0.DATA1	GT10.CHBONDI4
TCELL0:IMUX.G0.DATA2	GT10.POWERDOWN
TCELL0:IMUX.G0.DATA3	GT10.LOOPBACK0
TCELL0:IMUX.G0.DATA7	GT10.PMARXLOCKSEL1
TCELL0:IMUX.G1.DATA0	GT10.CHBONDI1
TCELL0:IMUX.G1.DATA1	GT10.ENCHANSYNC
TCELL0:IMUX.G1.DATA2	GT10.RXPOLARITY
TCELL0:IMUX.G1.DATA3	GT10.LOOPBACK1
TCELL0:IMUX.G2.DATA0	GT10.CHBONDI2
TCELL0:IMUX.G2.DATA1	GT10.REFCLKSEL
TCELL0:IMUX.G2.DATA3	GT10.TXPOLARITY
TCELL0:IMUX.G3.DATA0	GT10.CHBONDI3
TCELL0:IMUX.G3.DATA1	GT10.PMAINIT
TCELL0:IMUX.G3.DATA3	GT10.TXINHIBIT
TCELL0:IMUX.G3.DATA4	GT10.REFCLKBSEL
TCELL0:IMUX.G3.DATA6	GT10.PMARXLOCKSEL0
TCELL0:OUT.FAN0	GT10.CHBONDDONE
TCELL0:OUT.FAN1	GT10.RXRECCLK
TCELL0:OUT.FAN2	GT10.CHBONDO0
TCELL0:OUT.FAN3	GT10.CHBONDO1
TCELL0:OUT.FAN4	GT10.CHBONDO2
TCELL0:OUT.FAN5	GT10.CHBONDO3
TCELL0:OUT.FAN6	GT10.CHBONDO4
TCELL0:OUT.FAN7	GT10.TXOUTCLK
TCELL0:OUT.SEC8	GT10.PMARXLOCK
TCELL0:OUT.SEC9	GT10.RXCLKCORCNT2
TCELL0:OUT.SEC10	GT10.RXCLKCORCNT1
TCELL0:OUT.SEC11	GT10.RXCLKCORCNT0
TCELL0:OUT.SEC12	GT10.RXCOMMADET
TCELL0:OUT.SEC13	GT10.RXREALIGN
TCELL0:OUT.SEC14	GT10.RXBUFSTATUS1
TCELL0:OUT.SEC15	GT10.RXBUFSTATUS0
TCELL1:IMUX.CLK0	GT10.TXUSRCLK
TCELL1:IMUX.CLK1	GT10.TXUSRCLK2
TCELL1:IMUX.SR0	GT10.TXRESET
TCELL1:IMUX.G0.DATA0	GT10.TXDATA0
TCELL1:IMUX.G0.DATA1	GT10.TXDATA32
TCELL1:IMUX.G0.DATA2	GT10.TXBYPASS8B10B0
TCELL1:IMUX.G1.DATA0	GT10.TXDATA1
TCELL1:IMUX.G1.DATA1	GT10.TXDATA33
TCELL1:IMUX.G1.DATA2	GT10.TXCHARISK0
TCELL1:IMUX.G1.DATA4	GT10.ENPCOMMAALIGN
TCELL1:IMUX.G1.DATA7	GT10.ENMCOMMAALIGN
TCELL1:IMUX.G2.DATA0	GT10.TXDATA2
TCELL1:IMUX.G2.DATA1	GT10.TXDATA34
TCELL1:IMUX.G2.DATA2	GT10.TXCHARDISPMODE0
TCELL1:IMUX.G3.DATA0	GT10.TXDATA3
TCELL1:IMUX.G3.DATA1	GT10.TXDATA35
TCELL1:IMUX.G3.DATA2	GT10.TXCHARDISPVAL0
TCELL1:OUT.FAN0	GT10.RXDATA0
TCELL1:OUT.FAN1	GT10.RXDATA1
TCELL1:OUT.FAN2	GT10.RXDATA2
TCELL1:OUT.FAN3	GT10.RXDATA3
TCELL1:OUT.FAN4	GT10.RXDATA32
TCELL1:OUT.FAN5	GT10.RXDATA33
TCELL1:OUT.FAN6	GT10.RXDATA34
TCELL1:OUT.FAN7	GT10.RXDATA35
TCELL1:OUT.SEC8	GT10.RXLOSSOFSYNC0
TCELL1:OUT.SEC9	GT10.TXKERR0
TCELL1:OUT.SEC10	GT10.TXRUNDISP0
TCELL1:OUT.SEC11	GT10.RXCHARISCOMMA0
TCELL1:OUT.SEC12	GT10.RXCHARISK0
TCELL1:OUT.SEC13	GT10.RXNOTINTABLE0
TCELL1:OUT.SEC14	GT10.RXDISPERR0
TCELL1:OUT.SEC15	GT10.RXRUNDISP0
TCELL2:IMUX.G0.DATA0	GT10.TXDATA4
TCELL2:IMUX.G0.DATA1	GT10.TXDATA36
TCELL2:IMUX.G0.DATA2	GT10.TXBYPASS8B10B1
TCELL2:IMUX.G1.DATA0	GT10.TXDATA5
TCELL2:IMUX.G1.DATA1	GT10.TXDATA37
TCELL2:IMUX.G1.DATA2	GT10.TXCHARISK1
TCELL2:IMUX.G2.DATA0	GT10.TXDATA6
TCELL2:IMUX.G2.DATA1	GT10.TXDATA38
TCELL2:IMUX.G2.DATA2	GT10.TXCHARDISPMODE1
TCELL2:IMUX.G3.DATA0	GT10.TXDATA7
TCELL2:IMUX.G3.DATA1	GT10.TXDATA39
TCELL2:IMUX.G3.DATA2	GT10.TXCHARDISPVAL1
TCELL2:OUT.FAN0	GT10.RXDATA4
TCELL2:OUT.FAN1	GT10.RXDATA5
TCELL2:OUT.FAN2	GT10.RXDATA6
TCELL2:OUT.FAN3	GT10.RXDATA7
TCELL2:OUT.FAN4	GT10.RXDATA36
TCELL2:OUT.FAN5	GT10.RXDATA37
TCELL2:OUT.FAN6	GT10.RXDATA38
TCELL2:OUT.FAN7	GT10.RXDATA39
TCELL2:OUT.SEC8	GT10.RXLOSSOFSYNC1
TCELL2:OUT.SEC9	GT10.TXKERR1
TCELL2:OUT.SEC10	GT10.TXRUNDISP1
TCELL2:OUT.SEC11	GT10.RXCHARISCOMMA1
TCELL2:OUT.SEC12	GT10.RXCHARISK1
TCELL2:OUT.SEC13	GT10.RXNOTINTABLE1
TCELL2:OUT.SEC14	GT10.RXDISPERR1
TCELL2:OUT.SEC15	GT10.RXRUNDISP1
TCELL3:IMUX.G0.DATA0	GT10.TXDATA8
TCELL3:IMUX.G0.DATA1	GT10.TXDATA40
TCELL3:IMUX.G0.DATA2	GT10.TXBYPASS8B10B2
TCELL3:IMUX.G1.DATA0	GT10.TXDATA9
TCELL3:IMUX.G1.DATA1	GT10.TXDATA41
TCELL3:IMUX.G1.DATA2	GT10.TXCHARISK2
TCELL3:IMUX.G2.DATA0	GT10.TXDATA10
TCELL3:IMUX.G2.DATA1	GT10.TXDATA42
TCELL3:IMUX.G2.DATA2	GT10.TXCHARDISPMODE2
TCELL3:IMUX.G3.DATA0	GT10.TXDATA11
TCELL3:IMUX.G3.DATA1	GT10.TXDATA43
TCELL3:IMUX.G3.DATA2	GT10.TXCHARDISPVAL2
TCELL3:OUT.FAN0	GT10.RXDATA8
TCELL3:OUT.FAN1	GT10.RXDATA9
TCELL3:OUT.FAN2	GT10.RXDATA10
TCELL3:OUT.FAN3	GT10.RXDATA11
TCELL3:OUT.FAN4	GT10.RXDATA40
TCELL3:OUT.FAN5	GT10.RXDATA41
TCELL3:OUT.FAN6	GT10.RXDATA42
TCELL3:OUT.FAN7	GT10.RXDATA43
TCELL3:OUT.SEC8	GT10.RXCRCERR
TCELL3:OUT.SEC9	GT10.TXKERR2
TCELL3:OUT.SEC10	GT10.TXRUNDISP2
TCELL3:OUT.SEC11	GT10.RXCHARISCOMMA2
TCELL3:OUT.SEC12	GT10.RXCHARISK2
TCELL3:OUT.SEC13	GT10.RXNOTINTABLE2
TCELL3:OUT.SEC14	GT10.RXDISPERR2
TCELL3:OUT.SEC15	GT10.RXRUNDISP2
TCELL4:IMUX.G0.DATA0	GT10.TXDATA12
TCELL4:IMUX.G0.DATA1	GT10.TXDATA44
TCELL4:IMUX.G0.DATA2	GT10.TXBYPASS8B10B3
TCELL4:IMUX.G0.DATA4	GT10.TXDATAWIDTH0
TCELL4:IMUX.G0.DATA5	GT10.TXINTDATAWIDTH0
TCELL4:IMUX.G0.DATA6	GT10.RXDESCRAM64B66BUSE
TCELL4:IMUX.G1.DATA0	GT10.TXDATA13
TCELL4:IMUX.G1.DATA1	GT10.TXDATA45
TCELL4:IMUX.G1.DATA2	GT10.TXCHARISK3
TCELL4:IMUX.G1.DATA4	GT10.TXDATAWIDTH1
TCELL4:IMUX.G1.DATA5	GT10.TXINTDATAWIDTH1
TCELL4:IMUX.G1.DATA6	GT10.RXBLOCKSYNC64B66BUSE
TCELL4:IMUX.G2.DATA0	GT10.TXDATA14
TCELL4:IMUX.G2.DATA1	GT10.TXDATA46
TCELL4:IMUX.G2.DATA2	GT10.TXCHARDISPMODE3
TCELL4:IMUX.G2.DATA4	GT10.RXDATAWIDTH0
TCELL4:IMUX.G2.DATA5	GT10.RXINTDATAWIDTH0
TCELL4:IMUX.G2.DATA6	GT10.RXCOMMADETUSE
TCELL4:IMUX.G3.DATA0	GT10.TXDATA15
TCELL4:IMUX.G3.DATA1	GT10.TXDATA47
TCELL4:IMUX.G3.DATA2	GT10.TXCHARDISPVAL3
TCELL4:IMUX.G3.DATA3	GT10.TXFORCECRCERR
TCELL4:IMUX.G3.DATA4	GT10.RXDATAWIDTH1
TCELL4:IMUX.G3.DATA5	GT10.RXINTDATAWIDTH1
TCELL4:IMUX.G3.DATA6	GT10.RXSLIDE
TCELL4:OUT.FAN0	GT10.RXDATA12
TCELL4:OUT.FAN1	GT10.RXDATA13
TCELL4:OUT.FAN2	GT10.RXDATA14
TCELL4:OUT.FAN3	GT10.RXDATA15
TCELL4:OUT.FAN4	GT10.RXDATA44
TCELL4:OUT.FAN5	GT10.RXDATA45
TCELL4:OUT.FAN6	GT10.RXDATA46
TCELL4:OUT.FAN7	GT10.RXDATA47
TCELL4:OUT.SEC8	GT10.RXCHECKINGCRC
TCELL4:OUT.SEC9	GT10.TXKERR3
TCELL4:OUT.SEC10	GT10.TXRUNDISP3
TCELL4:OUT.SEC11	GT10.RXCHARISCOMMA3
TCELL4:OUT.SEC12	GT10.RXCHARISK3
TCELL4:OUT.SEC13	GT10.RXNOTINTABLE3
TCELL4:OUT.SEC14	GT10.RXDISPERR3
TCELL4:OUT.SEC15	GT10.RXRUNDISP3
TCELL5:IMUX.G0.DATA0	GT10.TXDATA16
TCELL5:IMUX.G0.DATA1	GT10.TXDATA48
TCELL5:IMUX.G0.DATA2	GT10.TXBYPASS8B10B4
TCELL5:IMUX.G0.DATA3	GT10.TESTMEMORY
TCELL5:IMUX.G0.DATA4	GT10.RXDEC64B66BUSE
TCELL5:IMUX.G0.DATA6	GT10.SCANIN
TCELL5:IMUX.G1.DATA0	GT10.TXDATA17
TCELL5:IMUX.G1.DATA1	GT10.TXDATA49
TCELL5:IMUX.G1.DATA2	GT10.TXCHARISK4
TCELL5:IMUX.G1.DATA3	GT10.RXIGNOREBTF
TCELL5:IMUX.G1.DATA4	GT10.TXSCRAM64B66BUSE
TCELL5:IMUX.G1.DATA6	GT10.SCANEN
TCELL5:IMUX.G2.DATA0	GT10.TXDATA18
TCELL5:IMUX.G2.DATA1	GT10.TXDATA50
TCELL5:IMUX.G2.DATA2	GT10.TXCHARDISPMODE4
TCELL5:IMUX.G2.DATA3	GT10.TXENC8B10BUSE
TCELL5:IMUX.G2.DATA4	GT10.TXGEARBOX64B66BUSE
TCELL5:IMUX.G2.DATA6	GT10.SCANMODE
TCELL5:IMUX.G3.DATA0	GT10.TXDATA19
TCELL5:IMUX.G3.DATA1	GT10.TXDATA51
TCELL5:IMUX.G3.DATA2	GT10.TXCHARDISPVAL4
TCELL5:IMUX.G3.DATA3	GT10.TXENC64B66BUSE
TCELL5:OUT.FAN0	GT10.RXDATA16
TCELL5:OUT.FAN1	GT10.RXDATA17
TCELL5:OUT.FAN2	GT10.RXDATA18
TCELL5:OUT.FAN3	GT10.RXDATA19
TCELL5:OUT.FAN4	GT10.RXDATA48
TCELL5:OUT.FAN5	GT10.RXDATA49
TCELL5:OUT.FAN6	GT10.RXDATA50
TCELL5:OUT.FAN7	GT10.RXDATA51
TCELL5:OUT.SEC8	GT10.SCANOUT
TCELL5:OUT.SEC9	GT10.TXKERR4
TCELL5:OUT.SEC10	GT10.TXRUNDISP4
TCELL5:OUT.SEC11	GT10.RXCHARISCOMMA4
TCELL5:OUT.SEC12	GT10.RXCHARISK4
TCELL5:OUT.SEC13	GT10.RXNOTINTABLE4
TCELL5:OUT.SEC14	GT10.RXDISPERR4
TCELL5:OUT.SEC15	GT10.RXRUNDISP4
TCELL6:IMUX.G0.DATA0	GT10.TXDATA20
TCELL6:IMUX.G0.DATA1	GT10.TXDATA52
TCELL6:IMUX.G0.DATA2	GT10.TXBYPASS8B10B5
TCELL6:IMUX.G0.DATA3	GT10.RXDEC8B10BUSE
TCELL6:IMUX.G0.DATA4	GT10.PMAREGDATAIN0
TCELL6:IMUX.G0.DATA5	GT10.PMAREGDATAIN4
TCELL6:IMUX.G0.DATA6	GT10.PMAREGADDR0
TCELL6:IMUX.G0.DATA7	GT10.PMAREGADDR4
TCELL6:IMUX.G1.DATA0	GT10.TXDATA21
TCELL6:IMUX.G1.DATA1	GT10.TXDATA53
TCELL6:IMUX.G1.DATA2	GT10.TXCHARISK5
TCELL6:IMUX.G1.DATA3	GT10.PMAREGRW
TCELL6:IMUX.G1.DATA4	GT10.PMAREGDATAIN1
TCELL6:IMUX.G1.DATA5	GT10.PMAREGDATAIN5
TCELL6:IMUX.G1.DATA6	GT10.PMAREGADDR1
TCELL6:IMUX.G1.DATA7	GT10.PMAREGADDR5
TCELL6:IMUX.G2.DATA0	GT10.TXDATA22
TCELL6:IMUX.G2.DATA1	GT10.TXDATA54
TCELL6:IMUX.G2.DATA2	GT10.TXCHARDISPMODE5
TCELL6:IMUX.G2.DATA3	GT10.PMAREGSTROBE
TCELL6:IMUX.G2.DATA4	GT10.PMAREGDATAIN2
TCELL6:IMUX.G2.DATA5	GT10.PMAREGDATAIN6
TCELL6:IMUX.G2.DATA6	GT10.PMAREGADDR2
TCELL6:IMUX.G3.DATA0	GT10.TXDATA23
TCELL6:IMUX.G3.DATA1	GT10.TXDATA55
TCELL6:IMUX.G3.DATA2	GT10.TXCHARDISPVAL5
TCELL6:IMUX.G3.DATA4	GT10.PMAREGDATAIN3
TCELL6:IMUX.G3.DATA5	GT10.PMAREGDATAIN7
TCELL6:IMUX.G3.DATA6	GT10.PMAREGADDR3
TCELL6:OUT.FAN0	GT10.RXDATA20
TCELL6:OUT.FAN1	GT10.RXDATA21
TCELL6:OUT.FAN2	GT10.RXDATA22
TCELL6:OUT.FAN3	GT10.RXDATA23
TCELL6:OUT.FAN4	GT10.RXDATA52
TCELL6:OUT.FAN5	GT10.RXDATA53
TCELL6:OUT.FAN6	GT10.RXDATA54
TCELL6:OUT.FAN7	GT10.RXDATA55
TCELL6:OUT.SEC9	GT10.TXKERR5
TCELL6:OUT.SEC10	GT10.TXRUNDISP5
TCELL6:OUT.SEC11	GT10.RXCHARISCOMMA5
TCELL6:OUT.SEC12	GT10.RXCHARISK5
TCELL6:OUT.SEC13	GT10.RXNOTINTABLE5
TCELL6:OUT.SEC14	GT10.RXDISPERR5
TCELL6:OUT.SEC15	GT10.RXRUNDISP5
TCELL7:IMUX.G0.DATA0	GT10.TXDATA24
TCELL7:IMUX.G0.DATA1	GT10.TXDATA56
TCELL7:IMUX.G0.DATA2	GT10.TXBYPASS8B10B6
TCELL7:IMUX.G1.DATA0	GT10.TXDATA25
TCELL7:IMUX.G1.DATA1	GT10.TXDATA57
TCELL7:IMUX.G1.DATA2	GT10.TXCHARISK6
TCELL7:IMUX.G2.DATA0	GT10.TXDATA26
TCELL7:IMUX.G2.DATA1	GT10.TXDATA58
TCELL7:IMUX.G2.DATA2	GT10.TXCHARDISPMODE6
TCELL7:IMUX.G3.DATA0	GT10.TXDATA27
TCELL7:IMUX.G3.DATA1	GT10.TXDATA59
TCELL7:IMUX.G3.DATA2	GT10.TXCHARDISPVAL6
TCELL7:OUT.FAN0	GT10.RXDATA24
TCELL7:OUT.FAN1	GT10.RXDATA25
TCELL7:OUT.FAN2	GT10.RXDATA26
TCELL7:OUT.FAN3	GT10.RXDATA27
TCELL7:OUT.FAN4	GT10.RXDATA56
TCELL7:OUT.FAN5	GT10.RXDATA57
TCELL7:OUT.FAN6	GT10.RXDATA58
TCELL7:OUT.FAN7	GT10.RXDATA59
TCELL7:OUT.SEC9	GT10.TXKERR6
TCELL7:OUT.SEC10	GT10.TXRUNDISP6
TCELL7:OUT.SEC11	GT10.RXCHARISCOMMA6
TCELL7:OUT.SEC12	GT10.RXCHARISK6
TCELL7:OUT.SEC13	GT10.RXNOTINTABLE6
TCELL7:OUT.SEC14	GT10.RXDISPERR6
TCELL7:OUT.SEC15	GT10.RXRUNDISP6
TCELL8:IMUX.G0.DATA0	GT10.TXDATA28
TCELL8:IMUX.G0.DATA1	GT10.TXDATA60
TCELL8:IMUX.G0.DATA2	GT10.TXBYPASS8B10B7
TCELL8:IMUX.G1.DATA0	GT10.TXDATA29
TCELL8:IMUX.G1.DATA1	GT10.TXDATA61
TCELL8:IMUX.G1.DATA2	GT10.TXCHARISK7
TCELL8:IMUX.G2.DATA0	GT10.TXDATA30
TCELL8:IMUX.G2.DATA1	GT10.TXDATA62
TCELL8:IMUX.G2.DATA2	GT10.TXCHARDISPMODE7
TCELL8:IMUX.G3.DATA0	GT10.TXDATA31
TCELL8:IMUX.G3.DATA1	GT10.TXDATA63
TCELL8:IMUX.G3.DATA2	GT10.TXCHARDISPVAL7
TCELL8:OUT.FAN0	GT10.RXDATA28
TCELL8:OUT.FAN1	GT10.RXDATA29
TCELL8:OUT.FAN2	GT10.RXDATA30
TCELL8:OUT.FAN3	GT10.RXDATA31
TCELL8:OUT.FAN4	GT10.RXDATA60
TCELL8:OUT.FAN5	GT10.RXDATA61
TCELL8:OUT.FAN6	GT10.RXDATA62
TCELL8:OUT.FAN7	GT10.RXDATA63
TCELL8:OUT.SEC8	GT10.TXBUFERR
TCELL8:OUT.SEC9	GT10.TXKERR7
TCELL8:OUT.SEC10	GT10.TXRUNDISP7
TCELL8:OUT.SEC11	GT10.RXCHARISCOMMA7
TCELL8:OUT.SEC12	GT10.RXCHARISK7
TCELL8:OUT.SEC13	GT10.RXNOTINTABLE7
TCELL8:OUT.SEC14	GT10.RXDISPERR7
TCELL8:OUT.SEC15	GT10.RXRUNDISP7

Bitstream

virtex2 GIGABIT10.B bittile 0
Bit	Frame
Bit	0	1	2	3
77	-	-	-	GT10:CRC_END_OF_PKT[6]
76	-	-	-	GT10:CRC_END_OF_PKT[5]
75	-	-	-	GT10:CRC_END_OF_PKT[4]
74	-	-	-	GT10:ENABLE
73	-	-	-	GT10:CRC_END_OF_PKT[3]
72	-	-	-	GT10:CRC_END_OF_PKT[2]
71	-	-	-	GT10:CRC_END_OF_PKT[1]
70	-	-	-	GT10:CRC_END_OF_PKT[0]
69	-	-	-	-
68	-	-	-	-
67	-	-	-	-
66	-	-	-	-
65	-	-	-	-
64	-	-	-	-
63	-	-	-	-
62	-	-	-	-
61	-	-	-	-
60	-	-	-	-
59	-	-	-	-
58	-	-	-	-
57	-	-	-	-
56	-	-	-	-
55	-	-	-	-
54	-	-	-	-
53	-	-	-	-
52	-	-	-	-
51	-	-	-	-
50	-	-	-	-
49	-	-	-	-
48	-	-	-	-
47	-	-	-	-
46	-	-	-	-
45	-	-	-	GT10:TX_CRC_FORCE_VALUE[7]
44	-	-	-	GT10:TX_CRC_FORCE_VALUE[6]
43	-	-	-	GT10:TX_CRC_FORCE_VALUE[5]
42	-	-	-	GT10:TX_CRC_FORCE_VALUE[4]
41	-	-	-	GT10:TX_CRC_FORCE_VALUE[3]
40	-	-	-	GT10:TX_CRC_FORCE_VALUE[2]
39	-	-	-	GT10:TX_CRC_FORCE_VALUE[1]
38	-	-	-	GT10:TX_CRC_FORCE_VALUE[0]
37	-	-	-	GT10:TX_CRC_USE
36	-	-	-	GT10:TX_BUFFER_USE
35	-	-	-	-
34	-	-	-	-
33	-	-	-	-
32	-	-	-	-
31	-	-	-	-
30	-	-	-	-
29	-	-	-	-
28	-	-	-	-
27	-	-	-	-
26	-	-	-	-
25	-	-	-	-
24	-	-	-	-
23	-	-	-	-
22	-	-	-	-
21	-	-	-	-
20	-	-	-	GT10:CRC_START_OF_PKT[7]
19	-	-	-	GT10:CRC_START_OF_PKT[6]
18	-	-	-	GT10:CRC_START_OF_PKT[5]
17	-	-	-	GT10:CRC_START_OF_PKT[4]
16	-	-	-	GT10:CRC_START_OF_PKT[3]
15	-	-	-	GT10:CRC_START_OF_PKT[2]
14	-	-	-	GT10:CRC_START_OF_PKT[1]
13	-	-	-	GT10:CRC_START_OF_PKT[0]
12	-	-	-	-
11	-	-	-	-
10	-	-	-	-
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	GT10:CRC_FORMAT[1]
3	-	-	-	GT10:CRC_FORMAT[0]
2	-	-	-	-
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT10.B bittile 1
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:CLK_COR_SEQ_1_1[10]
78	-	-	-	GT10:CLK_COR_SEQ_1_1[9]
77	-	-	-	GT10:CLK_COR_SEQ_1_1[8]
76	-	-	-	GT10:CLK_COR_SEQ_1_1[7]
75	-	-	-	GT10:CLK_COR_SEQ_1_1[6]
74	-	-	-	GT10:CLK_COR_SEQ_1_1[5]
73	-	-	-	GT10:CLK_COR_SEQ_1_1[4]
72	-	-	-	GT10:CLK_COR_SEQ_1_1[3]
71	-	-	-	GT10:CLK_COR_SEQ_1_1[2]
70	-	-	-	GT10:CLK_COR_SEQ_1_1[1]
69	-	-	-	GT10:CLK_COR_SEQ_1_1[0]
68	-	-	-	GT10:CLK_COR_SEQ_1_2[10]
67	-	-	-	GT10:CLK_COR_SEQ_1_2[9]
66	-	-	-	GT10:CLK_COR_SEQ_1_2[8]
65	-	-	-	GT10:CLK_COR_SEQ_1_2[7]
64	-	-	-	GT10:CLK_COR_SEQ_1_2[6]
63	-	-	-	GT10:CLK_COR_SEQ_1_2[5]
62	-	-	-	GT10:CLK_COR_SEQ_1_2[4]
61	-	-	-	GT10:CLK_COR_SEQ_1_2[3]
60	-	-	-	GT10:CLK_COR_SEQ_1_2[2]
59	-	-	-	GT10:CLK_COR_SEQ_1_2[1]
58	-	-	-	GT10:CLK_COR_SEQ_1_2[0]
57	-	-	-	GT10:CLK_COR_SEQ_1_3[10]
56	-	-	-	GT10:CLK_COR_SEQ_1_3[9]
55	-	-	-	GT10:CLK_COR_SEQ_1_3[8]
54	-	-	-	GT10:CLK_COR_SEQ_1_3[7]
53	-	-	-	GT10:CLK_COR_SEQ_1_3[6]
52	-	-	-	GT10:CLK_COR_SEQ_1_3[5]
51	-	-	-	GT10:CLK_COR_SEQ_1_3[4]
50	-	-	-	GT10:CLK_COR_SEQ_1_3[3]
49	-	-	-	GT10:CLK_COR_SEQ_1_3[2]
48	-	-	-	GT10:CLK_COR_SEQ_1_3[1]
47	-	-	-	GT10:CLK_COR_SEQ_1_3[0]
46	-	-	-	GT10:CLK_COR_SEQ_1_4[10]
45	-	-	-	GT10:CLK_COR_SEQ_1_4[9]
44	-	-	-	GT10:CLK_COR_SEQ_1_4[8]
43	-	-	-	GT10:CLK_COR_SEQ_1_4[7]
42	-	-	-	GT10:CLK_COR_SEQ_1_4[6]
41	-	-	-	GT10:CLK_COR_SEQ_1_4[5]
40	-	-	-	GT10:CLK_COR_SEQ_1_4[4]
39	-	-	-	GT10:CLK_COR_SEQ_1_4[3]
38	-	-	-	GT10:CLK_COR_SEQ_1_4[2]
37	-	-	-	GT10:CLK_COR_SEQ_1_4[1]
36	-	-	-	GT10:CLK_COR_SEQ_1_4[0]
35	-	-	-	-
34	-	-	-	GT10:PCOMMA_DETECT
33	-	-	-	-
32	-	-	-	GT10:PCOMMA_10B_VALUE[9]
31	-	-	-	GT10:PCOMMA_10B_VALUE[8]
30	-	-	-	GT10:PCOMMA_10B_VALUE[7]
29	-	-	-	GT10:PCOMMA_10B_VALUE[6]
28	-	-	-	GT10:PCOMMA_10B_VALUE[5]
27	-	-	-	GT10:PCOMMA_10B_VALUE[4]
26	-	-	-	GT10:PCOMMA_10B_VALUE[3]
25	-	-	-	GT10:PCOMMA_10B_VALUE[2]
24	-	-	-	GT10:PCOMMA_10B_VALUE[1]
23	-	-	-	GT10:PCOMMA_10B_VALUE[0]
22	-	-	-	GT10:MCOMMA_DETECT
21	-	-	-	-
20	-	-	-	GT10:MCOMMA_10B_VALUE[9]
19	-	-	-	GT10:MCOMMA_10B_VALUE[8]
18	-	-	-	GT10:MCOMMA_10B_VALUE[7]
17	-	-	-	GT10:MCOMMA_10B_VALUE[6]
16	-	-	-	GT10:MCOMMA_10B_VALUE[5]
15	-	-	-	GT10:MCOMMA_10B_VALUE[4]
14	-	-	-	GT10:MCOMMA_10B_VALUE[3]
13	-	-	-	GT10:MCOMMA_10B_VALUE[2]
12	-	-	-	GT10:MCOMMA_10B_VALUE[1]
11	-	-	-	GT10:MCOMMA_10B_VALUE[0]
10	-	-	-	GT10:COMMA_10B_MASK[9]
9	-	-	-	GT10:COMMA_10B_MASK[8]
8	-	-	-	GT10:COMMA_10B_MASK[7]
7	-	-	-	GT10:COMMA_10B_MASK[6]
6	-	-	-	GT10:COMMA_10B_MASK[5]
5	-	-	-	GT10:COMMA_10B_MASK[4]
4	-	-	-	GT10:COMMA_10B_MASK[3]
3	-	-	-	GT10:COMMA_10B_MASK[2]
2	-	-	-	GT10:COMMA_10B_MASK[1]
1	-	-	-	GT10:COMMA_10B_MASK[0]
0	-	-	-	-

virtex2 GIGABIT10.B bittile 2
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:CLK_COR_SEQ_2_1[10]
78	-	-	-	GT10:CLK_COR_SEQ_2_1[9]
77	-	-	-	GT10:CLK_COR_SEQ_2_1[8]
76	-	-	-	GT10:CLK_COR_SEQ_2_1[7]
75	-	-	-	GT10:CLK_COR_SEQ_2_1[6]
74	-	-	-	GT10:CLK_COR_SEQ_2_1[5]
73	-	-	-	GT10:CLK_COR_SEQ_2_1[4]
72	-	-	-	GT10:CLK_COR_SEQ_2_1[3]
71	-	-	-	GT10:CLK_COR_SEQ_2_1[2]
70	-	-	-	GT10:CLK_COR_SEQ_2_1[1]
69	-	-	-	GT10:CLK_COR_SEQ_2_1[0]
68	-	-	-	GT10:CLK_COR_SEQ_2_2[10]
67	-	-	-	GT10:CLK_COR_SEQ_2_2[9]
66	-	-	-	GT10:CLK_COR_SEQ_2_2[8]
65	-	-	-	GT10:CLK_COR_SEQ_2_2[7]
64	-	-	-	GT10:CLK_COR_SEQ_2_2[6]
63	-	-	-	GT10:CLK_COR_SEQ_2_2[5]
62	-	-	-	GT10:CLK_COR_SEQ_2_2[4]
61	-	-	-	GT10:CLK_COR_SEQ_2_2[3]
60	-	-	-	GT10:CLK_COR_SEQ_2_2[2]
59	-	-	-	GT10:CLK_COR_SEQ_2_2[1]
58	-	-	-	GT10:CLK_COR_SEQ_2_2[0]
57	-	-	-	GT10:CLK_COR_SEQ_2_3[10]
56	-	-	-	GT10:CLK_COR_SEQ_2_3[9]
55	-	-	-	GT10:CLK_COR_SEQ_2_3[8]
54	-	-	-	GT10:CLK_COR_SEQ_2_3[7]
53	-	-	-	GT10:CLK_COR_SEQ_2_3[6]
52	-	-	-	GT10:CLK_COR_SEQ_2_3[5]
51	-	-	-	GT10:CLK_COR_SEQ_2_3[4]
50	-	-	-	GT10:CLK_COR_SEQ_2_3[3]
49	-	-	-	GT10:CLK_COR_SEQ_2_3[2]
48	-	-	-	GT10:CLK_COR_SEQ_2_3[1]
47	-	-	-	GT10:CLK_COR_SEQ_2_3[0]
46	-	-	-	GT10:CLK_COR_SEQ_2_4[10]
45	-	-	-	GT10:CLK_COR_SEQ_2_4[9]
44	-	-	-	GT10:CLK_COR_SEQ_2_4[8]
43	-	-	-	GT10:CLK_COR_SEQ_2_4[7]
42	-	-	-	GT10:CLK_COR_SEQ_2_4[6]
41	-	-	-	GT10:CLK_COR_SEQ_2_4[5]
40	-	-	-	GT10:CLK_COR_SEQ_2_4[4]
39	-	-	-	GT10:CLK_COR_SEQ_2_4[3]
38	-	-	-	GT10:CLK_COR_SEQ_2_4[2]
37	-	-	-	GT10:CLK_COR_SEQ_2_4[1]
36	-	-	-	GT10:CLK_COR_SEQ_2_4[0]
35	-	-	-	GT10:CLK_COR_SEQ_2_USE
34	-	-	-	-
33	-	-	-	-
32	-	-	-	GT10:DEC_MCOMMA_DETECT
31	-	-	-	GT10:DEC_PCOMMA_DETECT
30	-	-	-	GT10:DEC_VALID_COMMA_ONLY
29	-	-	-	-
28	-	-	-	-
27	-	-	-	-
26	-	-	-	-
25	-	-	-	GT10:RX_BUFFER_USE
24	-	-	-	-
23	-	-	-	GT10:CHAN_BOND_ONE_SHOT
22	-	-	-	-
21	-	-	-	-
20	-	-	-	-
19	-	-	-	-
18	-	-	-	-
17	-	-	-	GT10:CLK_COR_REPEAT_WAIT[4]
16	-	-	-	GT10:CLK_COR_REPEAT_WAIT[3]
15	-	-	-	GT10:CLK_COR_REPEAT_WAIT[2]
14	-	-	-	GT10:CLK_COR_REPEAT_WAIT[1]
13	-	-	-	GT10:CLK_COR_REPEAT_WAIT[0]
12	-	-	-	GT10:CLK_COR_KEEP_IDLE
11	-	-	-	GT10:CLK_COR_INSERT_IDLE_FLAG
10	-	-	-	GT10:CLK_CORRECT_USE
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	GT10:CHAN_BOND_MODE[1]
3	-	-	-	-
2	-	-	-	GT10:CHAN_BOND_MODE[0]
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT10.B bittile 3
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:CHAN_BOND_SEQ_1_1[10]
78	-	-	-	GT10:CHAN_BOND_SEQ_1_1[9]
77	-	-	-	GT10:CHAN_BOND_SEQ_1_1[8]
76	-	-	-	GT10:CHAN_BOND_SEQ_1_1[7]
75	-	-	-	GT10:CHAN_BOND_SEQ_1_1[6]
74	-	-	-	GT10:CHAN_BOND_SEQ_1_1[5]
73	-	-	-	GT10:CHAN_BOND_SEQ_1_1[4]
72	-	-	-	GT10:CHAN_BOND_SEQ_1_1[3]
71	-	-	-	GT10:CHAN_BOND_SEQ_1_1[2]
70	-	-	-	GT10:CHAN_BOND_SEQ_1_1[1]
69	-	-	-	GT10:CHAN_BOND_SEQ_1_1[0]
68	-	-	-	GT10:CHAN_BOND_SEQ_1_2[10]
67	-	-	-	GT10:CHAN_BOND_SEQ_1_2[9]
66	-	-	-	GT10:CHAN_BOND_SEQ_1_2[8]
65	-	-	-	GT10:CHAN_BOND_SEQ_1_2[7]
64	-	-	-	GT10:CHAN_BOND_SEQ_1_2[6]
63	-	-	-	GT10:CHAN_BOND_SEQ_1_2[5]
62	-	-	-	GT10:CHAN_BOND_SEQ_1_2[4]
61	-	-	-	GT10:CHAN_BOND_SEQ_1_2[3]
60	-	-	-	GT10:CHAN_BOND_SEQ_1_2[2]
59	-	-	-	GT10:CHAN_BOND_SEQ_1_2[1]
58	-	-	-	GT10:CHAN_BOND_SEQ_1_2[0]
57	-	-	-	GT10:CHAN_BOND_SEQ_1_3[10]
56	-	-	-	GT10:CHAN_BOND_SEQ_1_3[9]
55	-	-	-	GT10:CHAN_BOND_SEQ_1_3[8]
54	-	-	-	GT10:CHAN_BOND_SEQ_1_3[7]
53	-	-	-	GT10:CHAN_BOND_SEQ_1_3[6]
52	-	-	-	GT10:CHAN_BOND_SEQ_1_3[5]
51	-	-	-	GT10:CHAN_BOND_SEQ_1_3[4]
50	-	-	-	GT10:CHAN_BOND_SEQ_1_3[3]
49	-	-	-	GT10:CHAN_BOND_SEQ_1_3[2]
48	-	-	-	GT10:CHAN_BOND_SEQ_1_3[1]
47	-	-	-	GT10:CHAN_BOND_SEQ_1_3[0]
46	-	-	-	GT10:CHAN_BOND_SEQ_1_4[10]
45	-	-	-	GT10:CHAN_BOND_SEQ_1_4[9]
44	-	-	-	GT10:CHAN_BOND_SEQ_1_4[8]
43	-	-	-	GT10:CHAN_BOND_SEQ_1_4[7]
42	-	-	-	GT10:CHAN_BOND_SEQ_1_4[6]
41	-	-	-	GT10:CHAN_BOND_SEQ_1_4[5]
40	-	-	-	GT10:CHAN_BOND_SEQ_1_4[4]
39	-	-	-	GT10:CHAN_BOND_SEQ_1_4[3]
38	-	-	-	GT10:CHAN_BOND_SEQ_1_4[2]
37	-	-	-	GT10:CHAN_BOND_SEQ_1_4[1]
36	-	-	-	GT10:CHAN_BOND_SEQ_1_4[0]
35	-	-	-	GT10:RX_CRC_USE
34	-	-	-	-
33	-	-	-	-
32	-	-	-	-
31	-	-	-	-
30	-	-	-	-
29	-	-	-	-
28	-	-	-	GT10:CHAN_BOND_SEQ_LEN[2]
27	-	-	-	GT10:CHAN_BOND_SEQ_LEN[1]
26	-	-	-	GT10:CHAN_BOND_SEQ_LEN[0]
25	-	-	-	-
24	-	-	-	GT10:CLK_COR_SEQ_LEN[2]
23	-	-	-	GT10:CLK_COR_SEQ_LEN[1]
22	-	-	-	GT10:CLK_COR_SEQ_LEN[0]
21	-	-	-	-
20	-	-	-	-
19	-	-	-	-
18	-	-	-	-
17	-	-	-	-
16	-	-	-	GT10:TEST_MODE_6
15	-	-	-	GT10:TEST_MODE_5
14	-	-	-	GT10:TEST_MODE_4
13	-	-	-	GT10:TEST_MODE_3
12	-	-	-	GT10:TEST_MODE_2
11	-	-	-	GT10:TEST_MODE_1
10	-	-	-	-
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	-
3	-	-	-	-
2	-	-	-	-
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT10.B bittile 4
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:CHAN_BOND_SEQ_2_1[10]
78	-	-	-	GT10:CHAN_BOND_SEQ_2_1[9]
77	-	-	-	GT10:CHAN_BOND_SEQ_2_1[8]
76	-	-	-	GT10:CHAN_BOND_SEQ_2_1[7]
75	-	-	-	GT10:CHAN_BOND_SEQ_2_1[6]
74	-	-	-	GT10:CHAN_BOND_SEQ_2_1[5]
73	-	-	-	GT10:CHAN_BOND_SEQ_2_1[4]
72	-	-	-	GT10:CHAN_BOND_SEQ_2_1[3]
71	-	-	-	GT10:CHAN_BOND_SEQ_2_1[2]
70	-	-	-	GT10:CHAN_BOND_SEQ_2_1[1]
69	-	-	-	GT10:CHAN_BOND_SEQ_2_1[0]
68	-	-	-	GT10:CHAN_BOND_SEQ_2_2[10]
67	-	-	-	GT10:CHAN_BOND_SEQ_2_2[9]
66	-	-	-	GT10:CHAN_BOND_SEQ_2_2[8]
65	-	-	-	GT10:CHAN_BOND_SEQ_2_2[7]
64	-	-	-	GT10:CHAN_BOND_SEQ_2_2[6]
63	-	-	-	GT10:CHAN_BOND_SEQ_2_2[5]
62	-	-	-	GT10:CHAN_BOND_SEQ_2_2[4]
61	-	-	-	GT10:CHAN_BOND_SEQ_2_2[3]
60	-	-	-	GT10:CHAN_BOND_SEQ_2_2[2]
59	-	-	-	GT10:CHAN_BOND_SEQ_2_2[1]
58	-	-	-	GT10:CHAN_BOND_SEQ_2_2[0]
57	-	-	-	GT10:CHAN_BOND_SEQ_2_3[10]
56	-	-	-	GT10:CHAN_BOND_SEQ_2_3[9]
55	-	-	-	GT10:CHAN_BOND_SEQ_2_3[8]
54	-	-	-	GT10:CHAN_BOND_SEQ_2_3[7]
53	-	-	-	GT10:CHAN_BOND_SEQ_2_3[6]
52	-	-	-	GT10:CHAN_BOND_SEQ_2_3[5]
51	-	-	-	GT10:CHAN_BOND_SEQ_2_3[4]
50	-	-	-	GT10:CHAN_BOND_SEQ_2_3[3]
49	-	-	-	GT10:CHAN_BOND_SEQ_2_3[2]
48	-	-	-	GT10:CHAN_BOND_SEQ_2_3[1]
47	-	-	-	GT10:CHAN_BOND_SEQ_2_3[0]
46	-	-	-	GT10:CHAN_BOND_SEQ_2_4[10]
45	-	-	-	GT10:CHAN_BOND_SEQ_2_4[9]
44	-	-	-	GT10:CHAN_BOND_SEQ_2_4[8]
43	-	-	-	GT10:CHAN_BOND_SEQ_2_4[7]
42	-	-	-	GT10:CHAN_BOND_SEQ_2_4[6]
41	-	-	-	GT10:CHAN_BOND_SEQ_2_4[5]
40	-	-	-	GT10:CHAN_BOND_SEQ_2_4[4]
39	-	-	-	GT10:CHAN_BOND_SEQ_2_4[3]
38	-	-	-	GT10:CHAN_BOND_SEQ_2_4[2]
37	-	-	-	GT10:CHAN_BOND_SEQ_2_4[1]
36	-	-	-	GT10:CHAN_BOND_SEQ_2_4[0]
35	-	-	-	GT10:CHAN_BOND_SEQ_2_USE
34	-	-	-	-
33	-	-	-	-
32	-	-	-	-
31	-	-	-	-
30	-	-	-	GT10:RX_LOS_INVALID_INCR[7]
29	-	-	-	-
28	-	-	-	GT10:CHAN_BOND_LIMIT[4]
27	-	-	-	GT10:CHAN_BOND_LIMIT[3]
26	-	-	-	GT10:CHAN_BOND_LIMIT[2]
25	-	-	-	GT10:CHAN_BOND_LIMIT[1]
24	-	-	-	GT10:CHAN_BOND_LIMIT[0]
23	-	-	-	GT10:RX_LOSS_OF_SYNC_FSM
22	-	-	-	GT10:RX_LOS_INVALID_INCR[6]
21	-	-	-	GT10:RX_LOS_INVALID_INCR[5]
20	-	-	-	GT10:RX_LOS_INVALID_INCR[4]
19	-	-	-	GT10:RX_LOS_INVALID_INCR[3]
18	-	-	-	GT10:RX_LOS_INVALID_INCR[2]
17	-	-	-	GT10:RX_LOS_INVALID_INCR[1]
16	-	-	-	GT10:RX_LOS_INVALID_INCR[0]
15	-	-	-	GT10:RX_LOS_THRESHOLD[7]
14	-	-	-	GT10:RX_LOS_THRESHOLD[6]
13	-	-	-	GT10:RX_LOS_THRESHOLD[5]
12	-	-	-	GT10:RX_LOS_THRESHOLD[4]
11	-	-	-	GT10:RX_LOS_THRESHOLD[3]
10	-	-	-	GT10:RX_LOS_THRESHOLD[2]
9	-	-	-	GT10:RX_LOS_THRESHOLD[1]
8	-	-	-	GT10:RX_LOS_THRESHOLD[0]
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	-
3	-	-	-	-
2	-	-	-	-
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT10.B bittile 5
Bit	Frame
Bit	0	1	2	3
57	-	-	-	GT10:PMA_PWR_CNTRL[7]
56	-	-	-	GT10:PMA_PWR_CNTRL[6]
55	-	-	-	GT10:PMA_PWR_CNTRL[5]
54	-	-	-	GT10:PMA_PWR_CNTRL[4]
53	-	-	-	GT10:PMA_PWR_CNTRL[3]
52	-	-	-	GT10:PMA_PWR_CNTRL[2]
51	-	-	-	GT10:PMA_PWR_CNTRL[1]
50	-	-	-	GT10:PMA_PWR_CNTRL[0]
49	-	-	-	-
48	-	-	-	-
47	-	-	-	-
46	-	-	-	-
45	-	-	-	-
44	-	-	-	-
43	-	-	-	-
42	-	-	-	-
41	-	-	-	-
40	-	-	-	-
39	-	-	-	-
38	-	-	-	-
37	-	-	-	-
36	-	-	-	-
35	-	-	-	-
34	-	-	-	-
33	-	-	-	GT10:CHAN_BOND_64B66B_SV
32	-	-	-	GT10:CLK_COR_8B10B_DE
31	-	-	-	-
30	-	-	-	GT10:CLK_COR_MAX_LAT[5]
29	-	-	-	GT10:CLK_COR_MAX_LAT[4]
28	-	-	-	GT10:CLK_COR_MAX_LAT[3]
27	-	-	-	GT10:CLK_COR_MAX_LAT[2]
26	-	-	-	GT10:CLK_COR_MAX_LAT[1]
25	-	-	-	GT10:CLK_COR_MAX_LAT[0]
24	-	-	-	GT10:CLK_COR_MIN_LAT[5]
23	-	-	-	GT10:CLK_COR_MIN_LAT[4]
22	-	-	-	GT10:CLK_COR_MIN_LAT[3]
21	-	-	-	GT10:CLK_COR_MIN_LAT[2]
20	-	-	-	GT10:CLK_COR_MIN_LAT[1]
19	-	-	-	GT10:CLK_COR_MIN_LAT[0]
18	-	-	-	-
17	-	-	-	GT10:CLK_COR_ADJ_MAX[4]
16	-	-	-	GT10:CLK_COR_ADJ_MAX[3]
15	-	-	-	GT10:CLK_COR_ADJ_MAX[2]
14	-	-	-	GT10:CLK_COR_ADJ_MAX[1]
13	-	-	-	GT10:CLK_COR_ADJ_MAX[0]
12	-	-	-	-
11	-	-	-	GT10:CHAN_BOND_SEQ_2_MASK[3]
10	-	-	-	GT10:CHAN_BOND_SEQ_2_MASK[2]
9	-	-	-	GT10:CHAN_BOND_SEQ_2_MASK[1]
8	-	-	-	GT10:CHAN_BOND_SEQ_2_MASK[0]
7	-	-	-	-
6	-	-	-	GT10:CHAN_BOND_SEQ_1_MASK[3]
5	-	-	-	GT10:CHAN_BOND_SEQ_1_MASK[2]
4	-	-	-	GT10:CHAN_BOND_SEQ_1_MASK[1]
3	-	-	-	GT10:CHAN_BOND_SEQ_1_MASK[0]
2	-	-	-	-
1	-	-	-	GT10:ALIGN_COMMA_WORD[1]
0	-	-	-	GT10:ALIGN_COMMA_WORD[0]

virtex2 GIGABIT10.B bittile 6
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:PMA_SPEED[39]
78	-	-	-	GT10:PMA_SPEED[38]
77	-	-	-	GT10:PMA_SPEED[37]
76	-	-	-	GT10:PMA_SPEED[36]
75	-	-	-	GT10:PMA_SPEED[35]
74	-	-	-	GT10:PMA_SPEED[34]
73	-	-	-	GT10:PMA_SPEED[33]
72	-	-	-	GT10:PMA_SPEED[32]
71	-	-	-	GT10:PMA_SPEED[31]
70	-	-	-	GT10:PMA_SPEED[30]
69	-	-	-	GT10:PMA_SPEED[29]
68	-	-	-	GT10:PMA_SPEED[28]
67	-	-	-	GT10:PMA_SPEED[27]
66	-	-	-	GT10:PMA_SPEED[26]
65	-	-	-	GT10:PMA_SPEED[25]
64	-	-	-	GT10:PMA_SPEED[24]
63	-	-	-	GT10:PMA_SPEED[23]
62	-	-	-	GT10:PMA_SPEED[22]
61	-	-	-	GT10:PMA_SPEED[21]
60	-	-	-	GT10:PMA_SPEED[20]
59	-	-	-	GT10:PMA_SPEED[19]
58	-	-	-	GT10:PMA_SPEED[18]
57	-	-	-	GT10:PMA_SPEED[17]
56	-	-	-	GT10:PMA_SPEED[16]
55	-	-	-	GT10:PMA_SPEED[15]
54	-	-	-	GT10:PMA_SPEED[14]
53	-	-	-	GT10:PMA_SPEED[13]
52	-	-	-	GT10:PMA_SPEED[12]
51	-	-	-	GT10:PMA_SPEED[11]
50	-	-	-	GT10:PMA_SPEED[10]
49	-	-	-	GT10:PMA_SPEED[9]
48	-	-	-	GT10:PMA_SPEED[8]
47	-	-	-	GT10:PMA_SPEED[7]
46	-	-	-	GT10:PMA_SPEED[6]
45	-	-	-	GT10:PMA_SPEED[5]
44	-	-	-	GT10:PMA_SPEED[4]
43	-	-	-	GT10:PMA_SPEED[3]
42	-	-	-	GT10:PMA_SPEED[2]
41	-	-	-	GT10:PMA_SPEED[1]
40	-	-	-	GT10:PMA_SPEED[0]
39	-	-	-	-
38	-	-	-	-
37	-	-	-	-
36	-	-	-	-
35	-	-	-	-
34	-	-	-	-
33	-	-	-	-
32	-	-	-	-
31	-	-	-	-
30	-	-	-	-
29	-	-	-	-
28	-	-	-	-
27	-	-	-	-
26	-	-	-	-
25	-	-	-	-
24	-	-	-	-
23	-	-	-	-
22	-	-	-	-
21	-	-	-	-
20	-	-	-	-
19	-	-	-	-
18	-	-	-	-
17	-	-	-	-
16	-	-	-	-
15	-	-	-	-
14	-	-	-	-
13	-	-	-	GT10:CLK_COR_SEQ_DROP
12	-	-	-	-
11	-	-	-	GT10:CLK_COR_SEQ_2_MASK[3]
10	-	-	-	GT10:CLK_COR_SEQ_2_MASK[2]
9	-	-	-	GT10:CLK_COR_SEQ_2_MASK[1]
8	-	-	-	GT10:CLK_COR_SEQ_2_MASK[0]
7	-	-	-	-
6	-	-	-	GT10:CLK_COR_SEQ_1_MASK[3]
5	-	-	-	GT10:CLK_COR_SEQ_1_MASK[2]
4	-	-	-	GT10:CLK_COR_SEQ_1_MASK[1]
3	-	-	-	-
2	-	-	-	GT10:CLK_COR_SEQ_1_MASK[0]
1	-	-	-	-
0	-	-	-	-

virtex2 GIGABIT10.B bittile 7
Bit	Frame
Bit	0	1	2	3
79	-	-	-	GT10:PMA_SPEED[119]
78	-	-	-	GT10:PMA_SPEED[118]
77	-	-	-	GT10:PMA_SPEED[117]
76	-	-	-	GT10:PMA_SPEED[116]
75	-	-	-	GT10:PMA_SPEED[115]
74	-	-	-	GT10:PMA_SPEED[114]
73	-	-	-	GT10:PMA_SPEED[113]
72	-	-	-	GT10:PMA_SPEED[112]
71	-	-	-	GT10:PMA_SPEED[111]
70	-	-	-	GT10:PMA_SPEED[110]
69	-	-	-	GT10:PMA_SPEED[109]
68	-	-	-	GT10:PMA_SPEED[108]
67	-	-	-	GT10:PMA_SPEED[107]
66	-	-	-	GT10:PMA_SPEED[106]
65	-	-	-	GT10:PMA_SPEED[105]
64	-	-	-	GT10:PMA_SPEED[104]
63	-	-	-	GT10:PMA_SPEED[103]
62	-	-	-	GT10:PMA_SPEED[102]
61	-	-	-	GT10:PMA_SPEED[101]
60	-	-	-	GT10:PMA_SPEED[100]
59	-	-	-	GT10:PMA_SPEED[99]
58	-	-	-	GT10:PMA_SPEED[98]
57	-	-	-	GT10:PMA_SPEED[97]
56	-	-	-	GT10:PMA_SPEED[96]
55	-	-	-	GT10:PMA_SPEED[95]
54	-	-	-	GT10:PMA_SPEED[94]
53	-	-	-	GT10:PMA_SPEED[93]
52	-	-	-	GT10:PMA_SPEED[92]
51	-	-	-	GT10:PMA_SPEED[91]
50	-	-	-	GT10:PMA_SPEED[90]
49	-	-	-	GT10:PMA_SPEED[89]
48	-	-	-	GT10:PMA_SPEED[88]
47	-	-	-	GT10:PMA_SPEED[87]
46	-	-	-	GT10:PMA_SPEED[86]
45	-	-	-	GT10:PMA_SPEED[85]
44	-	-	-	GT10:PMA_SPEED[84]
43	-	-	-	GT10:PMA_SPEED[83]
42	-	-	-	GT10:PMA_SPEED[82]
41	-	-	-	GT10:PMA_SPEED[81]
40	-	-	-	GT10:PMA_SPEED[80]
39	-	-	-	GT10:PMA_SPEED[79]
38	-	-	-	GT10:PMA_SPEED[78]
37	-	-	-	GT10:PMA_SPEED[77]
36	-	-	-	GT10:PMA_SPEED[76]
35	-	-	-	GT10:PMA_SPEED[75]
34	-	-	-	GT10:PMA_SPEED[74]
33	-	-	-	GT10:PMA_SPEED[73]
32	-	-	-	GT10:PMA_SPEED[72]
31	-	-	-	GT10:PMA_SPEED[71]
30	-	-	-	GT10:PMA_SPEED[70]
29	-	-	-	GT10:PMA_SPEED[69]
28	-	-	-	GT10:PMA_SPEED[68]
27	-	-	-	GT10:PMA_SPEED[67]
26	-	-	-	GT10:PMA_SPEED[66]
25	-	-	-	GT10:PMA_SPEED[65]
24	-	-	-	GT10:PMA_SPEED[64]
23	-	-	-	GT10:PMA_SPEED[63]
22	-	-	-	GT10:PMA_SPEED[62]
21	-	-	-	GT10:PMA_SPEED[61]
20	-	-	-	GT10:PMA_SPEED[60]
19	-	-	-	GT10:PMA_SPEED[59]
18	-	-	-	GT10:PMA_SPEED[58]
17	-	-	-	GT10:PMA_SPEED[57]
16	-	-	-	GT10:PMA_SPEED[56]
15	-	-	-	GT10:PMA_SPEED[55]
14	-	-	-	GT10:PMA_SPEED[54]
13	-	-	-	GT10:PMA_SPEED[53]
12	-	-	-	GT10:PMA_SPEED[52]
11	-	-	-	GT10:PMA_SPEED[51]
10	-	-	-	GT10:PMA_SPEED[50]
9	-	-	-	GT10:PMA_SPEED[49]
8	-	-	-	GT10:PMA_SPEED[48]
7	-	-	-	GT10:PMA_SPEED[47]
6	-	-	-	GT10:PMA_SPEED[46]
5	-	-	-	GT10:PMA_SPEED[45]
4	-	-	-	GT10:PMA_SPEED[44]
3	-	-	-	-
2	-	-	-	GT10:PMA_SPEED[42]
1	-	-	-	GT10:PMA_SPEED[41]
0	-	-	-	GT10:PMA_SPEED[40]

virtex2 GIGABIT10.B bittile 8
Bit	Frame
Bit	0	1	2	3
30	-	-	-	GT10:SH_INVALID_CNT_MAX[7]
29	-	-	-	GT10:SH_INVALID_CNT_MAX[6]
28	-	-	-	GT10:SH_INVALID_CNT_MAX[5]
27	-	-	-	GT10:SH_INVALID_CNT_MAX[4]
26	-	-	-	GT10:SH_INVALID_CNT_MAX[3]
25	-	-	-	GT10:SH_INVALID_CNT_MAX[2]
24	-	-	-	GT10:SH_INVALID_CNT_MAX[1]
23	-	-	-	GT10:SH_INVALID_CNT_MAX[0]
22	-	-	-	GT10:SH_CNT_MAX[7]
21	-	-	-	GT10:SH_CNT_MAX[6]
20	-	-	-	GT10:SH_CNT_MAX[5]
19	-	-	-	GT10:SH_CNT_MAX[4]
18	-	-	-	GT10:SH_CNT_MAX[3]
17	-	-	-	GT10:SH_CNT_MAX[2]
16	-	-	-	GT10:SH_CNT_MAX[1]
15	-	-	-	GT10:SH_CNT_MAX[0]
14	-	-	-	-
13	-	-	-	-
12	-	-	-	-
11	-	-	-	-
10	-	-	-	-
9	-	-	-	-
8	-	-	-	-
7	-	-	-	-
6	-	-	-	-
5	-	-	-	-
4	-	-	-	-
3	-	-	-	-
2	-	-	-	GT10:PMA_SPEED[43]
1	-	-	-	-
0	-	-	-	-

GT10:ALIGN_COMMA_WORD	5.3.1	5.3.0
1	0	0
2	0	1
4	1	0

GT10:CHAN_BOND_64B66B_SV	5.3.33
GT10:CHAN_BOND_ONE_SHOT	2.3.23
GT10:CHAN_BOND_SEQ_2_USE	4.3.35
GT10:CLK_CORRECT_USE	2.3.10
GT10:CLK_COR_8B10B_DE	5.3.32
GT10:CLK_COR_INSERT_IDLE_FLAG	2.3.11
GT10:CLK_COR_KEEP_IDLE	2.3.12
GT10:CLK_COR_SEQ_2_USE	2.3.35
GT10:CLK_COR_SEQ_DROP	6.3.13
GT10:DEC_MCOMMA_DETECT	2.3.32
GT10:DEC_PCOMMA_DETECT	2.3.31
GT10:DEC_VALID_COMMA_ONLY	2.3.30
GT10:ENABLE	0.3.74
GT10:MCOMMA_DETECT	1.3.22
GT10:PCOMMA_DETECT	1.3.34
GT10:RX_BUFFER_USE	2.3.25
GT10:RX_CRC_USE	3.3.35
GT10:RX_LOSS_OF_SYNC_FSM	4.3.23
GT10:TEST_MODE_1	3.3.11
GT10:TEST_MODE_2	3.3.12
GT10:TEST_MODE_3	3.3.13
GT10:TEST_MODE_4	3.3.14
GT10:TEST_MODE_5	3.3.15
GT10:TEST_MODE_6	3.3.16
GT10:TX_BUFFER_USE	0.3.36
GT10:TX_CRC_USE	0.3.37
non-inverted	[0]

GT10:CHAN_BOND_LIMIT	4.3.28	4.3.27	4.3.26	4.3.25	4.3.24
GT10:CLK_COR_ADJ_MAX	5.3.17	5.3.16	5.3.15	5.3.14	5.3.13
GT10:CLK_COR_REPEAT_WAIT	2.3.17	2.3.16	2.3.15	2.3.14	2.3.13
non-inverted	[4]	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_MODE	2.3.4	2.3.2
NONE	0	0
MASTER	0	1
SLAVE_1_HOP	1	0
SLAVE_2_HOPS	1	1

GT10:CHAN_BOND_SEQ_1_1	3.3.79	3.3.78	3.3.77	3.3.76	3.3.75	3.3.74	3.3.73	3.3.72	3.3.71	3.3.70	3.3.69
GT10:CHAN_BOND_SEQ_1_2	3.3.68	3.3.67	3.3.66	3.3.65	3.3.64	3.3.63	3.3.62	3.3.61	3.3.60	3.3.59	3.3.58
GT10:CHAN_BOND_SEQ_1_3	3.3.57	3.3.56	3.3.55	3.3.54	3.3.53	3.3.52	3.3.51	3.3.50	3.3.49	3.3.48	3.3.47
GT10:CHAN_BOND_SEQ_1_4	3.3.46	3.3.45	3.3.44	3.3.43	3.3.42	3.3.41	3.3.40	3.3.39	3.3.38	3.3.37	3.3.36
GT10:CHAN_BOND_SEQ_2_1	4.3.79	4.3.78	4.3.77	4.3.76	4.3.75	4.3.74	4.3.73	4.3.72	4.3.71	4.3.70	4.3.69
GT10:CHAN_BOND_SEQ_2_2	4.3.68	4.3.67	4.3.66	4.3.65	4.3.64	4.3.63	4.3.62	4.3.61	4.3.60	4.3.59	4.3.58
GT10:CHAN_BOND_SEQ_2_3	4.3.57	4.3.56	4.3.55	4.3.54	4.3.53	4.3.52	4.3.51	4.3.50	4.3.49	4.3.48	4.3.47
GT10:CHAN_BOND_SEQ_2_4	4.3.46	4.3.45	4.3.44	4.3.43	4.3.42	4.3.41	4.3.40	4.3.39	4.3.38	4.3.37	4.3.36
GT10:CLK_COR_SEQ_1_1	1.3.79	1.3.78	1.3.77	1.3.76	1.3.75	1.3.74	1.3.73	1.3.72	1.3.71	1.3.70	1.3.69
GT10:CLK_COR_SEQ_1_2	1.3.68	1.3.67	1.3.66	1.3.65	1.3.64	1.3.63	1.3.62	1.3.61	1.3.60	1.3.59	1.3.58
GT10:CLK_COR_SEQ_1_3	1.3.57	1.3.56	1.3.55	1.3.54	1.3.53	1.3.52	1.3.51	1.3.50	1.3.49	1.3.48	1.3.47
GT10:CLK_COR_SEQ_1_4	1.3.46	1.3.45	1.3.44	1.3.43	1.3.42	1.3.41	1.3.40	1.3.39	1.3.38	1.3.37	1.3.36
GT10:CLK_COR_SEQ_2_1	2.3.79	2.3.78	2.3.77	2.3.76	2.3.75	2.3.74	2.3.73	2.3.72	2.3.71	2.3.70	2.3.69
GT10:CLK_COR_SEQ_2_2	2.3.68	2.3.67	2.3.66	2.3.65	2.3.64	2.3.63	2.3.62	2.3.61	2.3.60	2.3.59	2.3.58
GT10:CLK_COR_SEQ_2_3	2.3.57	2.3.56	2.3.55	2.3.54	2.3.53	2.3.52	2.3.51	2.3.50	2.3.49	2.3.48	2.3.47
GT10:CLK_COR_SEQ_2_4	2.3.46	2.3.45	2.3.44	2.3.43	2.3.42	2.3.41	2.3.40	2.3.39	2.3.38	2.3.37	2.3.36
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_SEQ_1_MASK	5.3.6	5.3.5	5.3.4	5.3.3
GT10:CHAN_BOND_SEQ_2_MASK	5.3.11	5.3.10	5.3.9	5.3.8
GT10:CLK_COR_SEQ_1_MASK	6.3.6	6.3.5	6.3.4	6.3.2
GT10:CLK_COR_SEQ_2_MASK	6.3.11	6.3.10	6.3.9	6.3.8
non-inverted	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_SEQ_LEN	3.3.28	3.3.27	3.3.26
GT10:CLK_COR_SEQ_LEN	3.3.24	3.3.23	3.3.22
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
8	1	1	1

GT10:CLK_COR_MAX_LAT	5.3.30	5.3.29	5.3.28	5.3.27	5.3.26	5.3.25
GT10:CLK_COR_MIN_LAT	5.3.24	5.3.23	5.3.22	5.3.21	5.3.20	5.3.19
non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

GT10:COMMA_10B_MASK	1.3.10	1.3.9	1.3.8	1.3.7	1.3.6	1.3.5	1.3.4	1.3.3	1.3.2	1.3.1
GT10:MCOMMA_10B_VALUE	1.3.20	1.3.19	1.3.18	1.3.17	1.3.16	1.3.15	1.3.14	1.3.13	1.3.12	1.3.11
GT10:PCOMMA_10B_VALUE	1.3.32	1.3.31	1.3.30	1.3.29	1.3.28	1.3.27	1.3.26	1.3.25	1.3.24	1.3.23
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:CRC_END_OF_PKT	0.3.77	0.3.76	0.3.75	0.3.73	0.3.72	0.3.71	0.3.70
K28_0	0	0	0	1	1	0	0
K28_1	0	0	1	1	1	0	0
K28_2	0	1	0	1	1	0	0
K28_3	0	1	1	1	1	0	0
K28_4	1	0	0	1	1	0	0
K28_5	1	0	1	1	1	0	0
K28_6	1	1	0	1	1	0	0
K23_7	1	1	1	0	1	1	1
K27_7	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	0

GT10:CRC_FORMAT	0.3.4	0.3.3
USER_MODE	0	0
ETHERNET	0	1
FIBRE_CHAN	1	0
INFINIBAND	1	1

GT10:CRC_START_OF_PKT	0.3.20	0.3.19	0.3.18	0.3.17	0.3.16	0.3.15	0.3.14	0.3.13
K28_0	0	0	0	1	1	1	0	0
K28_1	0	0	1	1	1	1	0	0
K28_2	0	1	0	1	1	1	0	0
K28_3	0	1	1	1	1	1	0	0
K28_4	1	0	0	1	1	1	0	0
K28_5	1	0	1	1	1	1	0	0
K28_6	1	1	0	1	1	1	0	0
K23_7	1	1	1	1	0	1	1	1
K27_7	1	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	1	0

GT10:PMA_PWR_CNTRL	5.3.57	5.3.56	5.3.55	5.3.54	5.3.53	5.3.52	5.3.51	5.3.50
GT10:SH_CNT_MAX	8.3.22	8.3.21	8.3.20	8.3.19	8.3.18	8.3.17	8.3.16	8.3.15
GT10:SH_INVALID_CNT_MAX	8.3.30	8.3.29	8.3.28	8.3.27	8.3.26	8.3.25	8.3.24	8.3.23
GT10:TX_CRC_FORCE_VALUE	0.3.45	0.3.44	0.3.43	0.3.42	0.3.41	0.3.40	0.3.39	0.3.38
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:PMA_SPEED	7.3.79	7.3.78	7.3.77	7.3.76	7.3.75	7.3.74	7.3.73	7.3.72	7.3.71	7.3.70	7.3.69	7.3.68	7.3.67	7.3.66	7.3.65	7.3.64	7.3.63	7.3.62	7.3.61	7.3.60	7.3.59	7.3.58	7.3.57	7.3.56	7.3.55	7.3.54	7.3.53	7.3.52	7.3.51	7.3.50	7.3.49	7.3.48	7.3.47	7.3.46	7.3.45	7.3.44	7.3.43	7.3.42	7.3.41	7.3.40	7.3.39	7.3.38	7.3.37	7.3.36	7.3.35	7.3.34	7.3.33	7.3.32	7.3.31	7.3.30	7.3.29	7.3.28	7.3.27	7.3.26	7.3.25	7.3.24	7.3.23	7.3.22	7.3.21	7.3.20	7.3.19	7.3.18	7.3.17	7.3.16	7.3.15	7.3.14	7.3.13	7.3.12	7.3.11	7.3.10	7.3.9	7.3.8	7.3.7	7.3.6	7.3.5	7.3.4	8.3.2	7.3.2	7.3.1	7.3.0	6.3.79	6.3.78	6.3.77	6.3.76	6.3.75	6.3.74	6.3.73	6.3.72	6.3.71	6.3.70	6.3.69	6.3.68	6.3.67	6.3.66	6.3.65	6.3.64	6.3.63	6.3.62	6.3.61	6.3.60	6.3.59	6.3.58	6.3.57	6.3.56	6.3.55	6.3.54	6.3.53	6.3.52	6.3.51	6.3.50	6.3.49	6.3.48	6.3.47	6.3.46	6.3.45	6.3.44	6.3.43	6.3.42	6.3.41	6.3.40
non-inverted	[119]	[118]	[117]	[116]	[115]	[114]	[113]	[112]	[111]	[110]	[109]	[108]	[107]	[106]	[105]	[104]	[103]	[102]	[101]	[100]	[99]	[98]	[97]	[96]	[95]	[94]	[93]	[92]	[91]	[90]	[89]	[88]	[87]	[86]	[85]	[84]	[83]	[82]	[81]	[80]	[79]	[78]	[77]	[76]	[75]	[74]	[73]	[72]	[71]	[70]	[69]	[68]	[67]	[66]	[65]	[64]	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:RX_LOS_INVALID_INCR	4.3.30	4.3.22	4.3.21	4.3.20	4.3.19	4.3.18	4.3.17	4.3.16
1	0	0	0	0	0	0	0	1
2	0	0	0	0	0	0	1	0
4	0	0	0	0	0	1	0	0
8	0	0	0	0	1	0	0	0
16	0	0	0	1	0	0	0	0
32	0	0	1	0	0	0	0	0
64	0	1	0	0	0	0	0	0
128	1	0	0	0	0	0	0	0

GT10:RX_LOS_THRESHOLD	4.3.15	4.3.14	4.3.13	4.3.12	4.3.11	4.3.10	4.3.9	4.3.8
4	0	0	0	0	0	0	0	1
8	0	0	0	0	0	0	1	0
16	0	0	0	0	0	1	0	0
32	0	0	0	0	1	0	0	0
64	0	0	0	1	0	0	0	0
128	0	0	1	0	0	0	0	0
256	0	1	0	0	0	0	0	0
512	1	0	0	0	0	0	0	0

Tile GIGABIT10.T

Cells: 9 IRIs: 0

Bel GT10

virtex2 GIGABIT10.T bel GT10
Pin	Direction	Wires
CHBONDDONE	output	TCELL0:OUT.FAN0
CHBONDI0	input	TCELL0:IMUX.G0.DATA0
CHBONDI1	input	TCELL0:IMUX.G1.DATA0
CHBONDI2	input	TCELL0:IMUX.G2.DATA0
CHBONDI3	input	TCELL0:IMUX.G3.DATA0
CHBONDI4	input	TCELL0:IMUX.G0.DATA1
CHBONDO0	output	TCELL0:OUT.FAN2
CHBONDO1	output	TCELL0:OUT.FAN3
CHBONDO2	output	TCELL0:OUT.FAN4
CHBONDO3	output	TCELL0:OUT.FAN5
CHBONDO4	output	TCELL0:OUT.FAN6
ENCHANSYNC	input	TCELL0:IMUX.G1.DATA1
ENMCOMMAALIGN	input	TCELL1:IMUX.G1.DATA7
ENPCOMMAALIGN	input	TCELL1:IMUX.G1.DATA4
LOOPBACK0	input	TCELL0:IMUX.G0.DATA3
LOOPBACK1	input	TCELL0:IMUX.G1.DATA3
PMAINIT	input	TCELL0:IMUX.G3.DATA1
PMAREGADDR0	input	TCELL6:IMUX.G0.DATA6
PMAREGADDR1	input	TCELL6:IMUX.G1.DATA6
PMAREGADDR2	input	TCELL6:IMUX.G2.DATA6
PMAREGADDR3	input	TCELL6:IMUX.G3.DATA6
PMAREGADDR4	input	TCELL6:IMUX.G0.DATA7
PMAREGADDR5	input	TCELL6:IMUX.G1.DATA7
PMAREGDATAIN0	input	TCELL6:IMUX.G0.DATA4
PMAREGDATAIN1	input	TCELL6:IMUX.G1.DATA4
PMAREGDATAIN2	input	TCELL6:IMUX.G2.DATA4
PMAREGDATAIN3	input	TCELL6:IMUX.G3.DATA4
PMAREGDATAIN4	input	TCELL6:IMUX.G0.DATA5
PMAREGDATAIN5	input	TCELL6:IMUX.G1.DATA5
PMAREGDATAIN6	input	TCELL6:IMUX.G2.DATA5
PMAREGDATAIN7	input	TCELL6:IMUX.G3.DATA5
PMAREGRW	input	TCELL6:IMUX.G1.DATA3
PMAREGSTROBE	input	TCELL6:IMUX.G2.DATA3
PMARXLOCK	output	TCELL0:OUT.SEC8
PMARXLOCKSEL0	input	TCELL0:IMUX.G3.DATA6
PMARXLOCKSEL1	input	TCELL0:IMUX.G0.DATA7
POWERDOWN	input	TCELL0:IMUX.G0.DATA2
REFCLK	input	TCELL0:IMUX.DCMCLK2
REFCLK2	input	TCELL0:IMUX.DCMCLK3
REFCLKBSEL	input	TCELL0:IMUX.G3.DATA4
REFCLKSEL	input	TCELL0:IMUX.G2.DATA1
RXBLOCKSYNC64B66BUSE	input	TCELL4:IMUX.G1.DATA6
RXBUFSTATUS0	output	TCELL0:OUT.SEC15
RXBUFSTATUS1	output	TCELL0:OUT.SEC14
RXCHARISCOMMA0	output	TCELL1:OUT.SEC11
RXCHARISCOMMA1	output	TCELL2:OUT.SEC11
RXCHARISCOMMA2	output	TCELL3:OUT.SEC11
RXCHARISCOMMA3	output	TCELL4:OUT.SEC11
RXCHARISCOMMA4	output	TCELL5:OUT.SEC11
RXCHARISCOMMA5	output	TCELL6:OUT.SEC11
RXCHARISCOMMA6	output	TCELL7:OUT.SEC11
RXCHARISCOMMA7	output	TCELL8:OUT.SEC11
RXCHARISK0	output	TCELL1:OUT.SEC12
RXCHARISK1	output	TCELL2:OUT.SEC12
RXCHARISK2	output	TCELL3:OUT.SEC12
RXCHARISK3	output	TCELL4:OUT.SEC12
RXCHARISK4	output	TCELL5:OUT.SEC12
RXCHARISK5	output	TCELL6:OUT.SEC12
RXCHARISK6	output	TCELL7:OUT.SEC12
RXCHARISK7	output	TCELL8:OUT.SEC12
RXCHECKINGCRC	output	TCELL4:OUT.SEC8
RXCLKCORCNT0	output	TCELL0:OUT.SEC11
RXCLKCORCNT1	output	TCELL0:OUT.SEC10
RXCLKCORCNT2	output	TCELL0:OUT.SEC9
RXCOMMADET	output	TCELL0:OUT.SEC12
RXCOMMADETUSE	input	TCELL4:IMUX.G2.DATA6
RXCRCERR	output	TCELL3:OUT.SEC8
RXDATA0	output	TCELL1:OUT.FAN0
RXDATA1	output	TCELL1:OUT.FAN1
RXDATA10	output	TCELL3:OUT.FAN2
RXDATA11	output	TCELL3:OUT.FAN3
RXDATA12	output	TCELL4:OUT.FAN0
RXDATA13	output	TCELL4:OUT.FAN1
RXDATA14	output	TCELL4:OUT.FAN2
RXDATA15	output	TCELL4:OUT.FAN3
RXDATA16	output	TCELL5:OUT.FAN0
RXDATA17	output	TCELL5:OUT.FAN1
RXDATA18	output	TCELL5:OUT.FAN2
RXDATA19	output	TCELL5:OUT.FAN3
RXDATA2	output	TCELL1:OUT.FAN2
RXDATA20	output	TCELL6:OUT.FAN0
RXDATA21	output	TCELL6:OUT.FAN1
RXDATA22	output	TCELL6:OUT.FAN2
RXDATA23	output	TCELL6:OUT.FAN3
RXDATA24	output	TCELL7:OUT.FAN0
RXDATA25	output	TCELL7:OUT.FAN1
RXDATA26	output	TCELL7:OUT.FAN2
RXDATA27	output	TCELL7:OUT.FAN3
RXDATA28	output	TCELL8:OUT.FAN0
RXDATA29	output	TCELL8:OUT.FAN1
RXDATA3	output	TCELL1:OUT.FAN3
RXDATA30	output	TCELL8:OUT.FAN2
RXDATA31	output	TCELL8:OUT.FAN3
RXDATA32	output	TCELL1:OUT.FAN4
RXDATA33	output	TCELL1:OUT.FAN5
RXDATA34	output	TCELL1:OUT.FAN6
RXDATA35	output	TCELL1:OUT.FAN7
RXDATA36	output	TCELL2:OUT.FAN4
RXDATA37	output	TCELL2:OUT.FAN5
RXDATA38	output	TCELL2:OUT.FAN6
RXDATA39	output	TCELL2:OUT.FAN7
RXDATA4	output	TCELL2:OUT.FAN0
RXDATA40	output	TCELL3:OUT.FAN4
RXDATA41	output	TCELL3:OUT.FAN5
RXDATA42	output	TCELL3:OUT.FAN6
RXDATA43	output	TCELL3:OUT.FAN7
RXDATA44	output	TCELL4:OUT.FAN4
RXDATA45	output	TCELL4:OUT.FAN5
RXDATA46	output	TCELL4:OUT.FAN6
RXDATA47	output	TCELL4:OUT.FAN7
RXDATA48	output	TCELL5:OUT.FAN4
RXDATA49	output	TCELL5:OUT.FAN5
RXDATA5	output	TCELL2:OUT.FAN1
RXDATA50	output	TCELL5:OUT.FAN6
RXDATA51	output	TCELL5:OUT.FAN7
RXDATA52	output	TCELL6:OUT.FAN4
RXDATA53	output	TCELL6:OUT.FAN5
RXDATA54	output	TCELL6:OUT.FAN6
RXDATA55	output	TCELL6:OUT.FAN7
RXDATA56	output	TCELL7:OUT.FAN4
RXDATA57	output	TCELL7:OUT.FAN5
RXDATA58	output	TCELL7:OUT.FAN6
RXDATA59	output	TCELL7:OUT.FAN7
RXDATA6	output	TCELL2:OUT.FAN2
RXDATA60	output	TCELL8:OUT.FAN4
RXDATA61	output	TCELL8:OUT.FAN5
RXDATA62	output	TCELL8:OUT.FAN6
RXDATA63	output	TCELL8:OUT.FAN7
RXDATA7	output	TCELL2:OUT.FAN3
RXDATA8	output	TCELL3:OUT.FAN0
RXDATA9	output	TCELL3:OUT.FAN1
RXDATAWIDTH0	input	TCELL4:IMUX.G2.DATA4
RXDATAWIDTH1	input	TCELL4:IMUX.G3.DATA4
RXDEC64B66BUSE	input	TCELL5:IMUX.G0.DATA4
RXDEC8B10BUSE	input	TCELL6:IMUX.G0.DATA3
RXDESCRAM64B66BUSE	input	TCELL4:IMUX.G0.DATA6
RXDISPERR0	output	TCELL1:OUT.SEC14
RXDISPERR1	output	TCELL2:OUT.SEC14
RXDISPERR2	output	TCELL3:OUT.SEC14
RXDISPERR3	output	TCELL4:OUT.SEC14
RXDISPERR4	output	TCELL5:OUT.SEC14
RXDISPERR5	output	TCELL6:OUT.SEC14
RXDISPERR6	output	TCELL7:OUT.SEC14
RXDISPERR7	output	TCELL8:OUT.SEC14
RXIGNOREBTF	input	TCELL5:IMUX.G1.DATA3
RXINTDATAWIDTH0	input	TCELL4:IMUX.G2.DATA5
RXINTDATAWIDTH1	input	TCELL4:IMUX.G3.DATA5
RXLOSSOFSYNC0	output	TCELL1:OUT.SEC8
RXLOSSOFSYNC1	output	TCELL2:OUT.SEC8
RXNOTINTABLE0	output	TCELL1:OUT.SEC13
RXNOTINTABLE1	output	TCELL2:OUT.SEC13
RXNOTINTABLE2	output	TCELL3:OUT.SEC13
RXNOTINTABLE3	output	TCELL4:OUT.SEC13
RXNOTINTABLE4	output	TCELL5:OUT.SEC13
RXNOTINTABLE5	output	TCELL6:OUT.SEC13
RXNOTINTABLE6	output	TCELL7:OUT.SEC13
RXNOTINTABLE7	output	TCELL8:OUT.SEC13
RXPOLARITY	input	TCELL0:IMUX.G1.DATA2
RXREALIGN	output	TCELL0:OUT.SEC13
RXRECCLK	output	TCELL0:OUT.FAN1
RXRESET	input	TCELL0:IMUX.SR0
RXRUNDISP0	output	TCELL1:OUT.SEC15
RXRUNDISP1	output	TCELL2:OUT.SEC15
RXRUNDISP2	output	TCELL3:OUT.SEC15
RXRUNDISP3	output	TCELL4:OUT.SEC15
RXRUNDISP4	output	TCELL5:OUT.SEC15
RXRUNDISP5	output	TCELL6:OUT.SEC15
RXRUNDISP6	output	TCELL7:OUT.SEC15
RXRUNDISP7	output	TCELL8:OUT.SEC15
RXSLIDE	input	TCELL4:IMUX.G3.DATA6
RXUSRCLK	input	TCELL0:IMUX.DCMCLK0
RXUSRCLK2	input	TCELL0:IMUX.DCMCLK1
SCANEN	input	TCELL5:IMUX.G1.DATA6
SCANIN	input	TCELL5:IMUX.G0.DATA6
SCANMODE	input	TCELL5:IMUX.G2.DATA6
SCANOUT	output	TCELL5:OUT.SEC8
TESTMEMORY	input	TCELL5:IMUX.G0.DATA3
TXBUFERR	output	TCELL8:OUT.SEC8
TXBYPASS8B10B0	input	TCELL1:IMUX.G0.DATA2
TXBYPASS8B10B1	input	TCELL2:IMUX.G0.DATA2
TXBYPASS8B10B2	input	TCELL3:IMUX.G0.DATA2
TXBYPASS8B10B3	input	TCELL4:IMUX.G0.DATA2
TXBYPASS8B10B4	input	TCELL5:IMUX.G0.DATA2
TXBYPASS8B10B5	input	TCELL6:IMUX.G0.DATA2
TXBYPASS8B10B6	input	TCELL7:IMUX.G0.DATA2
TXBYPASS8B10B7	input	TCELL8:IMUX.G0.DATA2
TXCHARDISPMODE0	input	TCELL1:IMUX.G2.DATA2
TXCHARDISPMODE1	input	TCELL2:IMUX.G2.DATA2
TXCHARDISPMODE2	input	TCELL3:IMUX.G2.DATA2
TXCHARDISPMODE3	input	TCELL4:IMUX.G2.DATA2
TXCHARDISPMODE4	input	TCELL5:IMUX.G2.DATA2
TXCHARDISPMODE5	input	TCELL6:IMUX.G2.DATA2
TXCHARDISPMODE6	input	TCELL7:IMUX.G2.DATA2
TXCHARDISPMODE7	input	TCELL8:IMUX.G2.DATA2
TXCHARDISPVAL0	input	TCELL1:IMUX.G3.DATA2
TXCHARDISPVAL1	input	TCELL2:IMUX.G3.DATA2
TXCHARDISPVAL2	input	TCELL3:IMUX.G3.DATA2
TXCHARDISPVAL3	input	TCELL4:IMUX.G3.DATA2
TXCHARDISPVAL4	input	TCELL5:IMUX.G3.DATA2
TXCHARDISPVAL5	input	TCELL6:IMUX.G3.DATA2
TXCHARDISPVAL6	input	TCELL7:IMUX.G3.DATA2
TXCHARDISPVAL7	input	TCELL8:IMUX.G3.DATA2
TXCHARISK0	input	TCELL1:IMUX.G1.DATA2
TXCHARISK1	input	TCELL2:IMUX.G1.DATA2
TXCHARISK2	input	TCELL3:IMUX.G1.DATA2
TXCHARISK3	input	TCELL4:IMUX.G1.DATA2
TXCHARISK4	input	TCELL5:IMUX.G1.DATA2
TXCHARISK5	input	TCELL6:IMUX.G1.DATA2
TXCHARISK6	input	TCELL7:IMUX.G1.DATA2
TXCHARISK7	input	TCELL8:IMUX.G1.DATA2
TXDATA0	input	TCELL1:IMUX.G0.DATA0
TXDATA1	input	TCELL1:IMUX.G1.DATA0
TXDATA10	input	TCELL3:IMUX.G2.DATA0
TXDATA11	input	TCELL3:IMUX.G3.DATA0
TXDATA12	input	TCELL4:IMUX.G0.DATA0
TXDATA13	input	TCELL4:IMUX.G1.DATA0
TXDATA14	input	TCELL4:IMUX.G2.DATA0
TXDATA15	input	TCELL4:IMUX.G3.DATA0
TXDATA16	input	TCELL5:IMUX.G0.DATA0
TXDATA17	input	TCELL5:IMUX.G1.DATA0
TXDATA18	input	TCELL5:IMUX.G2.DATA0
TXDATA19	input	TCELL5:IMUX.G3.DATA0
TXDATA2	input	TCELL1:IMUX.G2.DATA0
TXDATA20	input	TCELL6:IMUX.G0.DATA0
TXDATA21	input	TCELL6:IMUX.G1.DATA0
TXDATA22	input	TCELL6:IMUX.G2.DATA0
TXDATA23	input	TCELL6:IMUX.G3.DATA0
TXDATA24	input	TCELL7:IMUX.G0.DATA0
TXDATA25	input	TCELL7:IMUX.G1.DATA0
TXDATA26	input	TCELL7:IMUX.G2.DATA0
TXDATA27	input	TCELL7:IMUX.G3.DATA0
TXDATA28	input	TCELL8:IMUX.G0.DATA0
TXDATA29	input	TCELL8:IMUX.G1.DATA0
TXDATA3	input	TCELL1:IMUX.G3.DATA0
TXDATA30	input	TCELL8:IMUX.G2.DATA0
TXDATA31	input	TCELL8:IMUX.G3.DATA0
TXDATA32	input	TCELL1:IMUX.G0.DATA1
TXDATA33	input	TCELL1:IMUX.G1.DATA1
TXDATA34	input	TCELL1:IMUX.G2.DATA1
TXDATA35	input	TCELL1:IMUX.G3.DATA1
TXDATA36	input	TCELL2:IMUX.G0.DATA1
TXDATA37	input	TCELL2:IMUX.G1.DATA1
TXDATA38	input	TCELL2:IMUX.G2.DATA1
TXDATA39	input	TCELL2:IMUX.G3.DATA1
TXDATA4	input	TCELL2:IMUX.G0.DATA0
TXDATA40	input	TCELL3:IMUX.G0.DATA1
TXDATA41	input	TCELL3:IMUX.G1.DATA1
TXDATA42	input	TCELL3:IMUX.G2.DATA1
TXDATA43	input	TCELL3:IMUX.G3.DATA1
TXDATA44	input	TCELL4:IMUX.G0.DATA1
TXDATA45	input	TCELL4:IMUX.G1.DATA1
TXDATA46	input	TCELL4:IMUX.G2.DATA1
TXDATA47	input	TCELL4:IMUX.G3.DATA1
TXDATA48	input	TCELL5:IMUX.G0.DATA1
TXDATA49	input	TCELL5:IMUX.G1.DATA1
TXDATA5	input	TCELL2:IMUX.G1.DATA0
TXDATA50	input	TCELL5:IMUX.G2.DATA1
TXDATA51	input	TCELL5:IMUX.G3.DATA1
TXDATA52	input	TCELL6:IMUX.G0.DATA1
TXDATA53	input	TCELL6:IMUX.G1.DATA1
TXDATA54	input	TCELL6:IMUX.G2.DATA1
TXDATA55	input	TCELL6:IMUX.G3.DATA1
TXDATA56	input	TCELL7:IMUX.G0.DATA1
TXDATA57	input	TCELL7:IMUX.G1.DATA1
TXDATA58	input	TCELL7:IMUX.G2.DATA1
TXDATA59	input	TCELL7:IMUX.G3.DATA1
TXDATA6	input	TCELL2:IMUX.G2.DATA0
TXDATA60	input	TCELL8:IMUX.G0.DATA1
TXDATA61	input	TCELL8:IMUX.G1.DATA1
TXDATA62	input	TCELL8:IMUX.G2.DATA1
TXDATA63	input	TCELL8:IMUX.G3.DATA1
TXDATA7	input	TCELL2:IMUX.G3.DATA0
TXDATA8	input	TCELL3:IMUX.G0.DATA0
TXDATA9	input	TCELL3:IMUX.G1.DATA0
TXDATAWIDTH0	input	TCELL4:IMUX.G0.DATA4
TXDATAWIDTH1	input	TCELL4:IMUX.G1.DATA4
TXENC64B66BUSE	input	TCELL5:IMUX.G3.DATA3
TXENC8B10BUSE	input	TCELL5:IMUX.G2.DATA3
TXFORCECRCERR	input	TCELL4:IMUX.G3.DATA3
TXGEARBOX64B66BUSE	input	TCELL5:IMUX.G2.DATA4
TXINHIBIT	input	TCELL0:IMUX.G3.DATA3
TXINTDATAWIDTH0	input	TCELL4:IMUX.G0.DATA5
TXINTDATAWIDTH1	input	TCELL4:IMUX.G1.DATA5
TXKERR0	output	TCELL1:OUT.SEC9
TXKERR1	output	TCELL2:OUT.SEC9
TXKERR2	output	TCELL3:OUT.SEC9
TXKERR3	output	TCELL4:OUT.SEC9
TXKERR4	output	TCELL5:OUT.SEC9
TXKERR5	output	TCELL6:OUT.SEC9
TXKERR6	output	TCELL7:OUT.SEC9
TXKERR7	output	TCELL8:OUT.SEC9
TXOUTCLK	output	TCELL0:OUT.FAN7
TXPOLARITY	input	TCELL0:IMUX.G2.DATA3
TXRESET	input	TCELL1:IMUX.SR0
TXRUNDISP0	output	TCELL1:OUT.SEC10
TXRUNDISP1	output	TCELL2:OUT.SEC10
TXRUNDISP2	output	TCELL3:OUT.SEC10
TXRUNDISP3	output	TCELL4:OUT.SEC10
TXRUNDISP4	output	TCELL5:OUT.SEC10
TXRUNDISP5	output	TCELL6:OUT.SEC10
TXRUNDISP6	output	TCELL7:OUT.SEC10
TXRUNDISP7	output	TCELL8:OUT.SEC10
TXSCRAM64B66BUSE	input	TCELL5:IMUX.G1.DATA4
TXUSRCLK	input	TCELL1:IMUX.CLK0
TXUSRCLK2	input	TCELL1:IMUX.CLK1

Bel IPAD_RXP

virtex2 GIGABIT10.T bel IPAD_RXP
Pin	Direction	Wires

Bel IPAD_RXN

virtex2 GIGABIT10.T bel IPAD_RXN
Pin	Direction	Wires

Bel OPAD_TXP

virtex2 GIGABIT10.T bel OPAD_TXP
Pin	Direction	Wires

Bel OPAD_TXN

virtex2 GIGABIT10.T bel OPAD_TXN
Pin	Direction	Wires

Bel wires

virtex2 GIGABIT10.T bel wires
Wire	Pins
TCELL0:IMUX.DCMCLK0	GT10.RXUSRCLK
TCELL0:IMUX.DCMCLK1	GT10.RXUSRCLK2
TCELL0:IMUX.DCMCLK2	GT10.REFCLK
TCELL0:IMUX.DCMCLK3	GT10.REFCLK2
TCELL0:IMUX.SR0	GT10.RXRESET
TCELL0:IMUX.G0.DATA0	GT10.CHBONDI0
TCELL0:IMUX.G0.DATA1	GT10.CHBONDI4
TCELL0:IMUX.G0.DATA2	GT10.POWERDOWN
TCELL0:IMUX.G0.DATA3	GT10.LOOPBACK0
TCELL0:IMUX.G0.DATA7	GT10.PMARXLOCKSEL1
TCELL0:IMUX.G1.DATA0	GT10.CHBONDI1
TCELL0:IMUX.G1.DATA1	GT10.ENCHANSYNC
TCELL0:IMUX.G1.DATA2	GT10.RXPOLARITY
TCELL0:IMUX.G1.DATA3	GT10.LOOPBACK1
TCELL0:IMUX.G2.DATA0	GT10.CHBONDI2
TCELL0:IMUX.G2.DATA1	GT10.REFCLKSEL
TCELL0:IMUX.G2.DATA3	GT10.TXPOLARITY
TCELL0:IMUX.G3.DATA0	GT10.CHBONDI3
TCELL0:IMUX.G3.DATA1	GT10.PMAINIT
TCELL0:IMUX.G3.DATA3	GT10.TXINHIBIT
TCELL0:IMUX.G3.DATA4	GT10.REFCLKBSEL
TCELL0:IMUX.G3.DATA6	GT10.PMARXLOCKSEL0
TCELL0:OUT.FAN0	GT10.CHBONDDONE
TCELL0:OUT.FAN1	GT10.RXRECCLK
TCELL0:OUT.FAN2	GT10.CHBONDO0
TCELL0:OUT.FAN3	GT10.CHBONDO1
TCELL0:OUT.FAN4	GT10.CHBONDO2
TCELL0:OUT.FAN5	GT10.CHBONDO3
TCELL0:OUT.FAN6	GT10.CHBONDO4
TCELL0:OUT.FAN7	GT10.TXOUTCLK
TCELL0:OUT.SEC8	GT10.PMARXLOCK
TCELL0:OUT.SEC9	GT10.RXCLKCORCNT2
TCELL0:OUT.SEC10	GT10.RXCLKCORCNT1
TCELL0:OUT.SEC11	GT10.RXCLKCORCNT0
TCELL0:OUT.SEC12	GT10.RXCOMMADET
TCELL0:OUT.SEC13	GT10.RXREALIGN
TCELL0:OUT.SEC14	GT10.RXBUFSTATUS1
TCELL0:OUT.SEC15	GT10.RXBUFSTATUS0
TCELL1:IMUX.CLK0	GT10.TXUSRCLK
TCELL1:IMUX.CLK1	GT10.TXUSRCLK2
TCELL1:IMUX.SR0	GT10.TXRESET
TCELL1:IMUX.G0.DATA0	GT10.TXDATA0
TCELL1:IMUX.G0.DATA1	GT10.TXDATA32
TCELL1:IMUX.G0.DATA2	GT10.TXBYPASS8B10B0
TCELL1:IMUX.G1.DATA0	GT10.TXDATA1
TCELL1:IMUX.G1.DATA1	GT10.TXDATA33
TCELL1:IMUX.G1.DATA2	GT10.TXCHARISK0
TCELL1:IMUX.G1.DATA4	GT10.ENPCOMMAALIGN
TCELL1:IMUX.G1.DATA7	GT10.ENMCOMMAALIGN
TCELL1:IMUX.G2.DATA0	GT10.TXDATA2
TCELL1:IMUX.G2.DATA1	GT10.TXDATA34
TCELL1:IMUX.G2.DATA2	GT10.TXCHARDISPMODE0
TCELL1:IMUX.G3.DATA0	GT10.TXDATA3
TCELL1:IMUX.G3.DATA1	GT10.TXDATA35
TCELL1:IMUX.G3.DATA2	GT10.TXCHARDISPVAL0
TCELL1:OUT.FAN0	GT10.RXDATA0
TCELL1:OUT.FAN1	GT10.RXDATA1
TCELL1:OUT.FAN2	GT10.RXDATA2
TCELL1:OUT.FAN3	GT10.RXDATA3
TCELL1:OUT.FAN4	GT10.RXDATA32
TCELL1:OUT.FAN5	GT10.RXDATA33
TCELL1:OUT.FAN6	GT10.RXDATA34
TCELL1:OUT.FAN7	GT10.RXDATA35
TCELL1:OUT.SEC8	GT10.RXLOSSOFSYNC0
TCELL1:OUT.SEC9	GT10.TXKERR0
TCELL1:OUT.SEC10	GT10.TXRUNDISP0
TCELL1:OUT.SEC11	GT10.RXCHARISCOMMA0
TCELL1:OUT.SEC12	GT10.RXCHARISK0
TCELL1:OUT.SEC13	GT10.RXNOTINTABLE0
TCELL1:OUT.SEC14	GT10.RXDISPERR0
TCELL1:OUT.SEC15	GT10.RXRUNDISP0
TCELL2:IMUX.G0.DATA0	GT10.TXDATA4
TCELL2:IMUX.G0.DATA1	GT10.TXDATA36
TCELL2:IMUX.G0.DATA2	GT10.TXBYPASS8B10B1
TCELL2:IMUX.G1.DATA0	GT10.TXDATA5
TCELL2:IMUX.G1.DATA1	GT10.TXDATA37
TCELL2:IMUX.G1.DATA2	GT10.TXCHARISK1
TCELL2:IMUX.G2.DATA0	GT10.TXDATA6
TCELL2:IMUX.G2.DATA1	GT10.TXDATA38
TCELL2:IMUX.G2.DATA2	GT10.TXCHARDISPMODE1
TCELL2:IMUX.G3.DATA0	GT10.TXDATA7
TCELL2:IMUX.G3.DATA1	GT10.TXDATA39
TCELL2:IMUX.G3.DATA2	GT10.TXCHARDISPVAL1
TCELL2:OUT.FAN0	GT10.RXDATA4
TCELL2:OUT.FAN1	GT10.RXDATA5
TCELL2:OUT.FAN2	GT10.RXDATA6
TCELL2:OUT.FAN3	GT10.RXDATA7
TCELL2:OUT.FAN4	GT10.RXDATA36
TCELL2:OUT.FAN5	GT10.RXDATA37
TCELL2:OUT.FAN6	GT10.RXDATA38
TCELL2:OUT.FAN7	GT10.RXDATA39
TCELL2:OUT.SEC8	GT10.RXLOSSOFSYNC1
TCELL2:OUT.SEC9	GT10.TXKERR1
TCELL2:OUT.SEC10	GT10.TXRUNDISP1
TCELL2:OUT.SEC11	GT10.RXCHARISCOMMA1
TCELL2:OUT.SEC12	GT10.RXCHARISK1
TCELL2:OUT.SEC13	GT10.RXNOTINTABLE1
TCELL2:OUT.SEC14	GT10.RXDISPERR1
TCELL2:OUT.SEC15	GT10.RXRUNDISP1
TCELL3:IMUX.G0.DATA0	GT10.TXDATA8
TCELL3:IMUX.G0.DATA1	GT10.TXDATA40
TCELL3:IMUX.G0.DATA2	GT10.TXBYPASS8B10B2
TCELL3:IMUX.G1.DATA0	GT10.TXDATA9
TCELL3:IMUX.G1.DATA1	GT10.TXDATA41
TCELL3:IMUX.G1.DATA2	GT10.TXCHARISK2
TCELL3:IMUX.G2.DATA0	GT10.TXDATA10
TCELL3:IMUX.G2.DATA1	GT10.TXDATA42
TCELL3:IMUX.G2.DATA2	GT10.TXCHARDISPMODE2
TCELL3:IMUX.G3.DATA0	GT10.TXDATA11
TCELL3:IMUX.G3.DATA1	GT10.TXDATA43
TCELL3:IMUX.G3.DATA2	GT10.TXCHARDISPVAL2
TCELL3:OUT.FAN0	GT10.RXDATA8
TCELL3:OUT.FAN1	GT10.RXDATA9
TCELL3:OUT.FAN2	GT10.RXDATA10
TCELL3:OUT.FAN3	GT10.RXDATA11
TCELL3:OUT.FAN4	GT10.RXDATA40
TCELL3:OUT.FAN5	GT10.RXDATA41
TCELL3:OUT.FAN6	GT10.RXDATA42
TCELL3:OUT.FAN7	GT10.RXDATA43
TCELL3:OUT.SEC8	GT10.RXCRCERR
TCELL3:OUT.SEC9	GT10.TXKERR2
TCELL3:OUT.SEC10	GT10.TXRUNDISP2
TCELL3:OUT.SEC11	GT10.RXCHARISCOMMA2
TCELL3:OUT.SEC12	GT10.RXCHARISK2
TCELL3:OUT.SEC13	GT10.RXNOTINTABLE2
TCELL3:OUT.SEC14	GT10.RXDISPERR2
TCELL3:OUT.SEC15	GT10.RXRUNDISP2
TCELL4:IMUX.G0.DATA0	GT10.TXDATA12
TCELL4:IMUX.G0.DATA1	GT10.TXDATA44
TCELL4:IMUX.G0.DATA2	GT10.TXBYPASS8B10B3
TCELL4:IMUX.G0.DATA4	GT10.TXDATAWIDTH0
TCELL4:IMUX.G0.DATA5	GT10.TXINTDATAWIDTH0
TCELL4:IMUX.G0.DATA6	GT10.RXDESCRAM64B66BUSE
TCELL4:IMUX.G1.DATA0	GT10.TXDATA13
TCELL4:IMUX.G1.DATA1	GT10.TXDATA45
TCELL4:IMUX.G1.DATA2	GT10.TXCHARISK3
TCELL4:IMUX.G1.DATA4	GT10.TXDATAWIDTH1
TCELL4:IMUX.G1.DATA5	GT10.TXINTDATAWIDTH1
TCELL4:IMUX.G1.DATA6	GT10.RXBLOCKSYNC64B66BUSE
TCELL4:IMUX.G2.DATA0	GT10.TXDATA14
TCELL4:IMUX.G2.DATA1	GT10.TXDATA46
TCELL4:IMUX.G2.DATA2	GT10.TXCHARDISPMODE3
TCELL4:IMUX.G2.DATA4	GT10.RXDATAWIDTH0
TCELL4:IMUX.G2.DATA5	GT10.RXINTDATAWIDTH0
TCELL4:IMUX.G2.DATA6	GT10.RXCOMMADETUSE
TCELL4:IMUX.G3.DATA0	GT10.TXDATA15
TCELL4:IMUX.G3.DATA1	GT10.TXDATA47
TCELL4:IMUX.G3.DATA2	GT10.TXCHARDISPVAL3
TCELL4:IMUX.G3.DATA3	GT10.TXFORCECRCERR
TCELL4:IMUX.G3.DATA4	GT10.RXDATAWIDTH1
TCELL4:IMUX.G3.DATA5	GT10.RXINTDATAWIDTH1
TCELL4:IMUX.G3.DATA6	GT10.RXSLIDE
TCELL4:OUT.FAN0	GT10.RXDATA12
TCELL4:OUT.FAN1	GT10.RXDATA13
TCELL4:OUT.FAN2	GT10.RXDATA14
TCELL4:OUT.FAN3	GT10.RXDATA15
TCELL4:OUT.FAN4	GT10.RXDATA44
TCELL4:OUT.FAN5	GT10.RXDATA45
TCELL4:OUT.FAN6	GT10.RXDATA46
TCELL4:OUT.FAN7	GT10.RXDATA47
TCELL4:OUT.SEC8	GT10.RXCHECKINGCRC
TCELL4:OUT.SEC9	GT10.TXKERR3
TCELL4:OUT.SEC10	GT10.TXRUNDISP3
TCELL4:OUT.SEC11	GT10.RXCHARISCOMMA3
TCELL4:OUT.SEC12	GT10.RXCHARISK3
TCELL4:OUT.SEC13	GT10.RXNOTINTABLE3
TCELL4:OUT.SEC14	GT10.RXDISPERR3
TCELL4:OUT.SEC15	GT10.RXRUNDISP3
TCELL5:IMUX.G0.DATA0	GT10.TXDATA16
TCELL5:IMUX.G0.DATA1	GT10.TXDATA48
TCELL5:IMUX.G0.DATA2	GT10.TXBYPASS8B10B4
TCELL5:IMUX.G0.DATA3	GT10.TESTMEMORY
TCELL5:IMUX.G0.DATA4	GT10.RXDEC64B66BUSE
TCELL5:IMUX.G0.DATA6	GT10.SCANIN
TCELL5:IMUX.G1.DATA0	GT10.TXDATA17
TCELL5:IMUX.G1.DATA1	GT10.TXDATA49
TCELL5:IMUX.G1.DATA2	GT10.TXCHARISK4
TCELL5:IMUX.G1.DATA3	GT10.RXIGNOREBTF
TCELL5:IMUX.G1.DATA4	GT10.TXSCRAM64B66BUSE
TCELL5:IMUX.G1.DATA6	GT10.SCANEN
TCELL5:IMUX.G2.DATA0	GT10.TXDATA18
TCELL5:IMUX.G2.DATA1	GT10.TXDATA50
TCELL5:IMUX.G2.DATA2	GT10.TXCHARDISPMODE4
TCELL5:IMUX.G2.DATA3	GT10.TXENC8B10BUSE
TCELL5:IMUX.G2.DATA4	GT10.TXGEARBOX64B66BUSE
TCELL5:IMUX.G2.DATA6	GT10.SCANMODE
TCELL5:IMUX.G3.DATA0	GT10.TXDATA19
TCELL5:IMUX.G3.DATA1	GT10.TXDATA51
TCELL5:IMUX.G3.DATA2	GT10.TXCHARDISPVAL4
TCELL5:IMUX.G3.DATA3	GT10.TXENC64B66BUSE
TCELL5:OUT.FAN0	GT10.RXDATA16
TCELL5:OUT.FAN1	GT10.RXDATA17
TCELL5:OUT.FAN2	GT10.RXDATA18
TCELL5:OUT.FAN3	GT10.RXDATA19
TCELL5:OUT.FAN4	GT10.RXDATA48
TCELL5:OUT.FAN5	GT10.RXDATA49
TCELL5:OUT.FAN6	GT10.RXDATA50
TCELL5:OUT.FAN7	GT10.RXDATA51
TCELL5:OUT.SEC8	GT10.SCANOUT
TCELL5:OUT.SEC9	GT10.TXKERR4
TCELL5:OUT.SEC10	GT10.TXRUNDISP4
TCELL5:OUT.SEC11	GT10.RXCHARISCOMMA4
TCELL5:OUT.SEC12	GT10.RXCHARISK4
TCELL5:OUT.SEC13	GT10.RXNOTINTABLE4
TCELL5:OUT.SEC14	GT10.RXDISPERR4
TCELL5:OUT.SEC15	GT10.RXRUNDISP4
TCELL6:IMUX.G0.DATA0	GT10.TXDATA20
TCELL6:IMUX.G0.DATA1	GT10.TXDATA52
TCELL6:IMUX.G0.DATA2	GT10.TXBYPASS8B10B5
TCELL6:IMUX.G0.DATA3	GT10.RXDEC8B10BUSE
TCELL6:IMUX.G0.DATA4	GT10.PMAREGDATAIN0
TCELL6:IMUX.G0.DATA5	GT10.PMAREGDATAIN4
TCELL6:IMUX.G0.DATA6	GT10.PMAREGADDR0
TCELL6:IMUX.G0.DATA7	GT10.PMAREGADDR4
TCELL6:IMUX.G1.DATA0	GT10.TXDATA21
TCELL6:IMUX.G1.DATA1	GT10.TXDATA53
TCELL6:IMUX.G1.DATA2	GT10.TXCHARISK5
TCELL6:IMUX.G1.DATA3	GT10.PMAREGRW
TCELL6:IMUX.G1.DATA4	GT10.PMAREGDATAIN1
TCELL6:IMUX.G1.DATA5	GT10.PMAREGDATAIN5
TCELL6:IMUX.G1.DATA6	GT10.PMAREGADDR1
TCELL6:IMUX.G1.DATA7	GT10.PMAREGADDR5
TCELL6:IMUX.G2.DATA0	GT10.TXDATA22
TCELL6:IMUX.G2.DATA1	GT10.TXDATA54
TCELL6:IMUX.G2.DATA2	GT10.TXCHARDISPMODE5
TCELL6:IMUX.G2.DATA3	GT10.PMAREGSTROBE
TCELL6:IMUX.G2.DATA4	GT10.PMAREGDATAIN2
TCELL6:IMUX.G2.DATA5	GT10.PMAREGDATAIN6
TCELL6:IMUX.G2.DATA6	GT10.PMAREGADDR2
TCELL6:IMUX.G3.DATA0	GT10.TXDATA23
TCELL6:IMUX.G3.DATA1	GT10.TXDATA55
TCELL6:IMUX.G3.DATA2	GT10.TXCHARDISPVAL5
TCELL6:IMUX.G3.DATA4	GT10.PMAREGDATAIN3
TCELL6:IMUX.G3.DATA5	GT10.PMAREGDATAIN7
TCELL6:IMUX.G3.DATA6	GT10.PMAREGADDR3
TCELL6:OUT.FAN0	GT10.RXDATA20
TCELL6:OUT.FAN1	GT10.RXDATA21
TCELL6:OUT.FAN2	GT10.RXDATA22
TCELL6:OUT.FAN3	GT10.RXDATA23
TCELL6:OUT.FAN4	GT10.RXDATA52
TCELL6:OUT.FAN5	GT10.RXDATA53
TCELL6:OUT.FAN6	GT10.RXDATA54
TCELL6:OUT.FAN7	GT10.RXDATA55
TCELL6:OUT.SEC9	GT10.TXKERR5
TCELL6:OUT.SEC10	GT10.TXRUNDISP5
TCELL6:OUT.SEC11	GT10.RXCHARISCOMMA5
TCELL6:OUT.SEC12	GT10.RXCHARISK5
TCELL6:OUT.SEC13	GT10.RXNOTINTABLE5
TCELL6:OUT.SEC14	GT10.RXDISPERR5
TCELL6:OUT.SEC15	GT10.RXRUNDISP5
TCELL7:IMUX.G0.DATA0	GT10.TXDATA24
TCELL7:IMUX.G0.DATA1	GT10.TXDATA56
TCELL7:IMUX.G0.DATA2	GT10.TXBYPASS8B10B6
TCELL7:IMUX.G1.DATA0	GT10.TXDATA25
TCELL7:IMUX.G1.DATA1	GT10.TXDATA57
TCELL7:IMUX.G1.DATA2	GT10.TXCHARISK6
TCELL7:IMUX.G2.DATA0	GT10.TXDATA26
TCELL7:IMUX.G2.DATA1	GT10.TXDATA58
TCELL7:IMUX.G2.DATA2	GT10.TXCHARDISPMODE6
TCELL7:IMUX.G3.DATA0	GT10.TXDATA27
TCELL7:IMUX.G3.DATA1	GT10.TXDATA59
TCELL7:IMUX.G3.DATA2	GT10.TXCHARDISPVAL6
TCELL7:OUT.FAN0	GT10.RXDATA24
TCELL7:OUT.FAN1	GT10.RXDATA25
TCELL7:OUT.FAN2	GT10.RXDATA26
TCELL7:OUT.FAN3	GT10.RXDATA27
TCELL7:OUT.FAN4	GT10.RXDATA56
TCELL7:OUT.FAN5	GT10.RXDATA57
TCELL7:OUT.FAN6	GT10.RXDATA58
TCELL7:OUT.FAN7	GT10.RXDATA59
TCELL7:OUT.SEC9	GT10.TXKERR6
TCELL7:OUT.SEC10	GT10.TXRUNDISP6
TCELL7:OUT.SEC11	GT10.RXCHARISCOMMA6
TCELL7:OUT.SEC12	GT10.RXCHARISK6
TCELL7:OUT.SEC13	GT10.RXNOTINTABLE6
TCELL7:OUT.SEC14	GT10.RXDISPERR6
TCELL7:OUT.SEC15	GT10.RXRUNDISP6
TCELL8:IMUX.G0.DATA0	GT10.TXDATA28
TCELL8:IMUX.G0.DATA1	GT10.TXDATA60
TCELL8:IMUX.G0.DATA2	GT10.TXBYPASS8B10B7
TCELL8:IMUX.G1.DATA0	GT10.TXDATA29
TCELL8:IMUX.G1.DATA1	GT10.TXDATA61
TCELL8:IMUX.G1.DATA2	GT10.TXCHARISK7
TCELL8:IMUX.G2.DATA0	GT10.TXDATA30
TCELL8:IMUX.G2.DATA1	GT10.TXDATA62
TCELL8:IMUX.G2.DATA2	GT10.TXCHARDISPMODE7
TCELL8:IMUX.G3.DATA0	GT10.TXDATA31
TCELL8:IMUX.G3.DATA1	GT10.TXDATA63
TCELL8:IMUX.G3.DATA2	GT10.TXCHARDISPVAL7
TCELL8:OUT.FAN0	GT10.RXDATA28
TCELL8:OUT.FAN1	GT10.RXDATA29
TCELL8:OUT.FAN2	GT10.RXDATA30
TCELL8:OUT.FAN3	GT10.RXDATA31
TCELL8:OUT.FAN4	GT10.RXDATA60
TCELL8:OUT.FAN5	GT10.RXDATA61
TCELL8:OUT.FAN6	GT10.RXDATA62
TCELL8:OUT.FAN7	GT10.RXDATA63
TCELL8:OUT.SEC8	GT10.TXBUFERR
TCELL8:OUT.SEC9	GT10.TXKERR7
TCELL8:OUT.SEC10	GT10.TXRUNDISP7
TCELL8:OUT.SEC11	GT10.RXCHARISCOMMA7
TCELL8:OUT.SEC12	GT10.RXCHARISK7
TCELL8:OUT.SEC13	GT10.RXNOTINTABLE7
TCELL8:OUT.SEC14	GT10.RXDISPERR7
TCELL8:OUT.SEC15	GT10.RXRUNDISP7

Bitstream

virtex2 GIGABIT10.T bittile 0
Bit	Frame
Bit	0
77	GT10:CRC_END_OF_PKT[6]
76	GT10:CRC_END_OF_PKT[5]
75	GT10:CRC_END_OF_PKT[4]
74	GT10:ENABLE
73	GT10:CRC_END_OF_PKT[3]
72	GT10:CRC_END_OF_PKT[2]
71	GT10:CRC_END_OF_PKT[1]
70	GT10:CRC_END_OF_PKT[0]
69	-
68	-
67	-
66	-
65	-
64	-
63	-
62	-
61	-
60	-
59	-
58	-
57	-
56	-
55	-
54	-
53	-
52	-
51	-
50	-
49	-
48	-
47	-
46	-
45	GT10:TX_CRC_FORCE_VALUE[7]
44	GT10:TX_CRC_FORCE_VALUE[6]
43	GT10:TX_CRC_FORCE_VALUE[5]
42	GT10:TX_CRC_FORCE_VALUE[4]
41	GT10:TX_CRC_FORCE_VALUE[3]
40	GT10:TX_CRC_FORCE_VALUE[2]
39	GT10:TX_CRC_FORCE_VALUE[1]
38	GT10:TX_CRC_FORCE_VALUE[0]
37	GT10:TX_CRC_USE
36	GT10:TX_BUFFER_USE
35	-
34	-
33	-
32	-
31	-
30	-
29	-
28	-
27	-
26	-
25	-
24	-
23	-
22	-
21	-
20	GT10:CRC_START_OF_PKT[7]
19	GT10:CRC_START_OF_PKT[6]
18	GT10:CRC_START_OF_PKT[5]
17	GT10:CRC_START_OF_PKT[4]
16	GT10:CRC_START_OF_PKT[3]
15	GT10:CRC_START_OF_PKT[2]
14	GT10:CRC_START_OF_PKT[1]
13	GT10:CRC_START_OF_PKT[0]
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	GT10:CRC_FORMAT[1]
3	GT10:CRC_FORMAT[0]
2	-
1	-
0	-

virtex2 GIGABIT10.T bittile 1
Bit	Frame
Bit	0
79	GT10:CLK_COR_SEQ_1_1[10]
78	GT10:CLK_COR_SEQ_1_1[9]
77	GT10:CLK_COR_SEQ_1_1[8]
76	GT10:CLK_COR_SEQ_1_1[7]
75	GT10:CLK_COR_SEQ_1_1[6]
74	GT10:CLK_COR_SEQ_1_1[5]
73	GT10:CLK_COR_SEQ_1_1[4]
72	GT10:CLK_COR_SEQ_1_1[3]
71	GT10:CLK_COR_SEQ_1_1[2]
70	GT10:CLK_COR_SEQ_1_1[1]
69	GT10:CLK_COR_SEQ_1_1[0]
68	GT10:CLK_COR_SEQ_1_2[10]
67	GT10:CLK_COR_SEQ_1_2[9]
66	GT10:CLK_COR_SEQ_1_2[8]
65	GT10:CLK_COR_SEQ_1_2[7]
64	GT10:CLK_COR_SEQ_1_2[6]
63	GT10:CLK_COR_SEQ_1_2[5]
62	GT10:CLK_COR_SEQ_1_2[4]
61	GT10:CLK_COR_SEQ_1_2[3]
60	GT10:CLK_COR_SEQ_1_2[2]
59	GT10:CLK_COR_SEQ_1_2[1]
58	GT10:CLK_COR_SEQ_1_2[0]
57	GT10:CLK_COR_SEQ_1_3[10]
56	GT10:CLK_COR_SEQ_1_3[9]
55	GT10:CLK_COR_SEQ_1_3[8]
54	GT10:CLK_COR_SEQ_1_3[7]
53	GT10:CLK_COR_SEQ_1_3[6]
52	GT10:CLK_COR_SEQ_1_3[5]
51	GT10:CLK_COR_SEQ_1_3[4]
50	GT10:CLK_COR_SEQ_1_3[3]
49	GT10:CLK_COR_SEQ_1_3[2]
48	GT10:CLK_COR_SEQ_1_3[1]
47	GT10:CLK_COR_SEQ_1_3[0]
46	GT10:CLK_COR_SEQ_1_4[10]
45	GT10:CLK_COR_SEQ_1_4[9]
44	GT10:CLK_COR_SEQ_1_4[8]
43	GT10:CLK_COR_SEQ_1_4[7]
42	GT10:CLK_COR_SEQ_1_4[6]
41	GT10:CLK_COR_SEQ_1_4[5]
40	GT10:CLK_COR_SEQ_1_4[4]
39	GT10:CLK_COR_SEQ_1_4[3]
38	GT10:CLK_COR_SEQ_1_4[2]
37	GT10:CLK_COR_SEQ_1_4[1]
36	GT10:CLK_COR_SEQ_1_4[0]
35	-
34	GT10:PCOMMA_DETECT
33	-
32	GT10:PCOMMA_10B_VALUE[9]
31	GT10:PCOMMA_10B_VALUE[8]
30	GT10:PCOMMA_10B_VALUE[7]
29	GT10:PCOMMA_10B_VALUE[6]
28	GT10:PCOMMA_10B_VALUE[5]
27	GT10:PCOMMA_10B_VALUE[4]
26	GT10:PCOMMA_10B_VALUE[3]
25	GT10:PCOMMA_10B_VALUE[2]
24	GT10:PCOMMA_10B_VALUE[1]
23	GT10:PCOMMA_10B_VALUE[0]
22	GT10:MCOMMA_DETECT
21	-
20	GT10:MCOMMA_10B_VALUE[9]
19	GT10:MCOMMA_10B_VALUE[8]
18	GT10:MCOMMA_10B_VALUE[7]
17	GT10:MCOMMA_10B_VALUE[6]
16	GT10:MCOMMA_10B_VALUE[5]
15	GT10:MCOMMA_10B_VALUE[4]
14	GT10:MCOMMA_10B_VALUE[3]
13	GT10:MCOMMA_10B_VALUE[2]
12	GT10:MCOMMA_10B_VALUE[1]
11	GT10:MCOMMA_10B_VALUE[0]
10	GT10:COMMA_10B_MASK[9]
9	GT10:COMMA_10B_MASK[8]
8	GT10:COMMA_10B_MASK[7]
7	GT10:COMMA_10B_MASK[6]
6	GT10:COMMA_10B_MASK[5]
5	GT10:COMMA_10B_MASK[4]
4	GT10:COMMA_10B_MASK[3]
3	GT10:COMMA_10B_MASK[2]
2	GT10:COMMA_10B_MASK[1]
1	GT10:COMMA_10B_MASK[0]
0	-

virtex2 GIGABIT10.T bittile 2
Bit	Frame
Bit	0
79	GT10:CLK_COR_SEQ_2_1[10]
78	GT10:CLK_COR_SEQ_2_1[9]
77	GT10:CLK_COR_SEQ_2_1[8]
76	GT10:CLK_COR_SEQ_2_1[7]
75	GT10:CLK_COR_SEQ_2_1[6]
74	GT10:CLK_COR_SEQ_2_1[5]
73	GT10:CLK_COR_SEQ_2_1[4]
72	GT10:CLK_COR_SEQ_2_1[3]
71	GT10:CLK_COR_SEQ_2_1[2]
70	GT10:CLK_COR_SEQ_2_1[1]
69	GT10:CLK_COR_SEQ_2_1[0]
68	GT10:CLK_COR_SEQ_2_2[10]
67	GT10:CLK_COR_SEQ_2_2[9]
66	GT10:CLK_COR_SEQ_2_2[8]
65	GT10:CLK_COR_SEQ_2_2[7]
64	GT10:CLK_COR_SEQ_2_2[6]
63	GT10:CLK_COR_SEQ_2_2[5]
62	GT10:CLK_COR_SEQ_2_2[4]
61	GT10:CLK_COR_SEQ_2_2[3]
60	GT10:CLK_COR_SEQ_2_2[2]
59	GT10:CLK_COR_SEQ_2_2[1]
58	GT10:CLK_COR_SEQ_2_2[0]
57	GT10:CLK_COR_SEQ_2_3[10]
56	GT10:CLK_COR_SEQ_2_3[9]
55	GT10:CLK_COR_SEQ_2_3[8]
54	GT10:CLK_COR_SEQ_2_3[7]
53	GT10:CLK_COR_SEQ_2_3[6]
52	GT10:CLK_COR_SEQ_2_3[5]
51	GT10:CLK_COR_SEQ_2_3[4]
50	GT10:CLK_COR_SEQ_2_3[3]
49	GT10:CLK_COR_SEQ_2_3[2]
48	GT10:CLK_COR_SEQ_2_3[1]
47	GT10:CLK_COR_SEQ_2_3[0]
46	GT10:CLK_COR_SEQ_2_4[10]
45	GT10:CLK_COR_SEQ_2_4[9]
44	GT10:CLK_COR_SEQ_2_4[8]
43	GT10:CLK_COR_SEQ_2_4[7]
42	GT10:CLK_COR_SEQ_2_4[6]
41	GT10:CLK_COR_SEQ_2_4[5]
40	GT10:CLK_COR_SEQ_2_4[4]
39	GT10:CLK_COR_SEQ_2_4[3]
38	GT10:CLK_COR_SEQ_2_4[2]
37	GT10:CLK_COR_SEQ_2_4[1]
36	GT10:CLK_COR_SEQ_2_4[0]
35	GT10:CLK_COR_SEQ_2_USE
34	-
33	-
32	GT10:DEC_MCOMMA_DETECT
31	GT10:DEC_PCOMMA_DETECT
30	GT10:DEC_VALID_COMMA_ONLY
29	-
28	-
27	-
26	-
25	GT10:RX_BUFFER_USE
24	-
23	GT10:CHAN_BOND_ONE_SHOT
22	-
21	-
20	-
19	-
18	-
17	GT10:CLK_COR_REPEAT_WAIT[4]
16	GT10:CLK_COR_REPEAT_WAIT[3]
15	GT10:CLK_COR_REPEAT_WAIT[2]
14	GT10:CLK_COR_REPEAT_WAIT[1]
13	GT10:CLK_COR_REPEAT_WAIT[0]
12	GT10:CLK_COR_KEEP_IDLE
11	GT10:CLK_COR_INSERT_IDLE_FLAG
10	GT10:CLK_CORRECT_USE
9	-
8	-
7	-
6	-
5	-
4	GT10:CHAN_BOND_MODE[1]
3	-
2	GT10:CHAN_BOND_MODE[0]
1	-
0	-

virtex2 GIGABIT10.T bittile 3
Bit	Frame
Bit	0
79	GT10:CHAN_BOND_SEQ_1_1[10]
78	GT10:CHAN_BOND_SEQ_1_1[9]
77	GT10:CHAN_BOND_SEQ_1_1[8]
76	GT10:CHAN_BOND_SEQ_1_1[7]
75	GT10:CHAN_BOND_SEQ_1_1[6]
74	GT10:CHAN_BOND_SEQ_1_1[5]
73	GT10:CHAN_BOND_SEQ_1_1[4]
72	GT10:CHAN_BOND_SEQ_1_1[3]
71	GT10:CHAN_BOND_SEQ_1_1[2]
70	GT10:CHAN_BOND_SEQ_1_1[1]
69	GT10:CHAN_BOND_SEQ_1_1[0]
68	GT10:CHAN_BOND_SEQ_1_2[10]
67	GT10:CHAN_BOND_SEQ_1_2[9]
66	GT10:CHAN_BOND_SEQ_1_2[8]
65	GT10:CHAN_BOND_SEQ_1_2[7]
64	GT10:CHAN_BOND_SEQ_1_2[6]
63	GT10:CHAN_BOND_SEQ_1_2[5]
62	GT10:CHAN_BOND_SEQ_1_2[4]
61	GT10:CHAN_BOND_SEQ_1_2[3]
60	GT10:CHAN_BOND_SEQ_1_2[2]
59	GT10:CHAN_BOND_SEQ_1_2[1]
58	GT10:CHAN_BOND_SEQ_1_2[0]
57	GT10:CHAN_BOND_SEQ_1_3[10]
56	GT10:CHAN_BOND_SEQ_1_3[9]
55	GT10:CHAN_BOND_SEQ_1_3[8]
54	GT10:CHAN_BOND_SEQ_1_3[7]
53	GT10:CHAN_BOND_SEQ_1_3[6]
52	GT10:CHAN_BOND_SEQ_1_3[5]
51	GT10:CHAN_BOND_SEQ_1_3[4]
50	GT10:CHAN_BOND_SEQ_1_3[3]
49	GT10:CHAN_BOND_SEQ_1_3[2]
48	GT10:CHAN_BOND_SEQ_1_3[1]
47	GT10:CHAN_BOND_SEQ_1_3[0]
46	GT10:CHAN_BOND_SEQ_1_4[10]
45	GT10:CHAN_BOND_SEQ_1_4[9]
44	GT10:CHAN_BOND_SEQ_1_4[8]
43	GT10:CHAN_BOND_SEQ_1_4[7]
42	GT10:CHAN_BOND_SEQ_1_4[6]
41	GT10:CHAN_BOND_SEQ_1_4[5]
40	GT10:CHAN_BOND_SEQ_1_4[4]
39	GT10:CHAN_BOND_SEQ_1_4[3]
38	GT10:CHAN_BOND_SEQ_1_4[2]
37	GT10:CHAN_BOND_SEQ_1_4[1]
36	GT10:CHAN_BOND_SEQ_1_4[0]
35	GT10:RX_CRC_USE
34	-
33	-
32	-
31	-
30	-
29	-
28	GT10:CHAN_BOND_SEQ_LEN[2]
27	GT10:CHAN_BOND_SEQ_LEN[1]
26	GT10:CHAN_BOND_SEQ_LEN[0]
25	-
24	GT10:CLK_COR_SEQ_LEN[2]
23	GT10:CLK_COR_SEQ_LEN[1]
22	GT10:CLK_COR_SEQ_LEN[0]
21	-
20	-
19	-
18	-
17	-
16	GT10:TEST_MODE_6
15	GT10:TEST_MODE_5
14	GT10:TEST_MODE_4
13	GT10:TEST_MODE_3
12	GT10:TEST_MODE_2
11	GT10:TEST_MODE_1
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

virtex2 GIGABIT10.T bittile 4
Bit	Frame
Bit	0
79	GT10:CHAN_BOND_SEQ_2_1[10]
78	GT10:CHAN_BOND_SEQ_2_1[9]
77	GT10:CHAN_BOND_SEQ_2_1[8]
76	GT10:CHAN_BOND_SEQ_2_1[7]
75	GT10:CHAN_BOND_SEQ_2_1[6]
74	GT10:CHAN_BOND_SEQ_2_1[5]
73	GT10:CHAN_BOND_SEQ_2_1[4]
72	GT10:CHAN_BOND_SEQ_2_1[3]
71	GT10:CHAN_BOND_SEQ_2_1[2]
70	GT10:CHAN_BOND_SEQ_2_1[1]
69	GT10:CHAN_BOND_SEQ_2_1[0]
68	GT10:CHAN_BOND_SEQ_2_2[10]
67	GT10:CHAN_BOND_SEQ_2_2[9]
66	GT10:CHAN_BOND_SEQ_2_2[8]
65	GT10:CHAN_BOND_SEQ_2_2[7]
64	GT10:CHAN_BOND_SEQ_2_2[6]
63	GT10:CHAN_BOND_SEQ_2_2[5]
62	GT10:CHAN_BOND_SEQ_2_2[4]
61	GT10:CHAN_BOND_SEQ_2_2[3]
60	GT10:CHAN_BOND_SEQ_2_2[2]
59	GT10:CHAN_BOND_SEQ_2_2[1]
58	GT10:CHAN_BOND_SEQ_2_2[0]
57	GT10:CHAN_BOND_SEQ_2_3[10]
56	GT10:CHAN_BOND_SEQ_2_3[9]
55	GT10:CHAN_BOND_SEQ_2_3[8]
54	GT10:CHAN_BOND_SEQ_2_3[7]
53	GT10:CHAN_BOND_SEQ_2_3[6]
52	GT10:CHAN_BOND_SEQ_2_3[5]
51	GT10:CHAN_BOND_SEQ_2_3[4]
50	GT10:CHAN_BOND_SEQ_2_3[3]
49	GT10:CHAN_BOND_SEQ_2_3[2]
48	GT10:CHAN_BOND_SEQ_2_3[1]
47	GT10:CHAN_BOND_SEQ_2_3[0]
46	GT10:CHAN_BOND_SEQ_2_4[10]
45	GT10:CHAN_BOND_SEQ_2_4[9]
44	GT10:CHAN_BOND_SEQ_2_4[8]
43	GT10:CHAN_BOND_SEQ_2_4[7]
42	GT10:CHAN_BOND_SEQ_2_4[6]
41	GT10:CHAN_BOND_SEQ_2_4[5]
40	GT10:CHAN_BOND_SEQ_2_4[4]
39	GT10:CHAN_BOND_SEQ_2_4[3]
38	GT10:CHAN_BOND_SEQ_2_4[2]
37	GT10:CHAN_BOND_SEQ_2_4[1]
36	GT10:CHAN_BOND_SEQ_2_4[0]
35	GT10:CHAN_BOND_SEQ_2_USE
34	-
33	-
32	-
31	-
30	GT10:RX_LOS_INVALID_INCR[7]
29	-
28	GT10:CHAN_BOND_LIMIT[4]
27	GT10:CHAN_BOND_LIMIT[3]
26	GT10:CHAN_BOND_LIMIT[2]
25	GT10:CHAN_BOND_LIMIT[1]
24	GT10:CHAN_BOND_LIMIT[0]
23	GT10:RX_LOSS_OF_SYNC_FSM
22	GT10:RX_LOS_INVALID_INCR[6]
21	GT10:RX_LOS_INVALID_INCR[5]
20	GT10:RX_LOS_INVALID_INCR[4]
19	GT10:RX_LOS_INVALID_INCR[3]
18	GT10:RX_LOS_INVALID_INCR[2]
17	GT10:RX_LOS_INVALID_INCR[1]
16	GT10:RX_LOS_INVALID_INCR[0]
15	GT10:RX_LOS_THRESHOLD[7]
14	GT10:RX_LOS_THRESHOLD[6]
13	GT10:RX_LOS_THRESHOLD[5]
12	GT10:RX_LOS_THRESHOLD[4]
11	GT10:RX_LOS_THRESHOLD[3]
10	GT10:RX_LOS_THRESHOLD[2]
9	GT10:RX_LOS_THRESHOLD[1]
8	GT10:RX_LOS_THRESHOLD[0]
7	-
6	-
5	-
4	-
3	-
2	-
1	-
0	-

virtex2 GIGABIT10.T bittile 5
Bit	Frame
Bit	0
57	GT10:PMA_PWR_CNTRL[7]
56	GT10:PMA_PWR_CNTRL[6]
55	GT10:PMA_PWR_CNTRL[5]
54	GT10:PMA_PWR_CNTRL[4]
53	GT10:PMA_PWR_CNTRL[3]
52	GT10:PMA_PWR_CNTRL[2]
51	GT10:PMA_PWR_CNTRL[1]
50	GT10:PMA_PWR_CNTRL[0]
49	-
48	-
47	-
46	-
45	-
44	-
43	-
42	-
41	-
40	-
39	-
38	-
37	-
36	-
35	-
34	-
33	GT10:CHAN_BOND_64B66B_SV
32	GT10:CLK_COR_8B10B_DE
31	-
30	GT10:CLK_COR_MAX_LAT[5]
29	GT10:CLK_COR_MAX_LAT[4]
28	GT10:CLK_COR_MAX_LAT[3]
27	GT10:CLK_COR_MAX_LAT[2]
26	GT10:CLK_COR_MAX_LAT[1]
25	GT10:CLK_COR_MAX_LAT[0]
24	GT10:CLK_COR_MIN_LAT[5]
23	GT10:CLK_COR_MIN_LAT[4]
22	GT10:CLK_COR_MIN_LAT[3]
21	GT10:CLK_COR_MIN_LAT[2]
20	GT10:CLK_COR_MIN_LAT[1]
19	GT10:CLK_COR_MIN_LAT[0]
18	-
17	GT10:CLK_COR_ADJ_MAX[4]
16	GT10:CLK_COR_ADJ_MAX[3]
15	GT10:CLK_COR_ADJ_MAX[2]
14	GT10:CLK_COR_ADJ_MAX[1]
13	GT10:CLK_COR_ADJ_MAX[0]
12	-
11	GT10:CHAN_BOND_SEQ_2_MASK[3]
10	GT10:CHAN_BOND_SEQ_2_MASK[2]
9	GT10:CHAN_BOND_SEQ_2_MASK[1]
8	GT10:CHAN_BOND_SEQ_2_MASK[0]
7	-
6	GT10:CHAN_BOND_SEQ_1_MASK[3]
5	GT10:CHAN_BOND_SEQ_1_MASK[2]
4	GT10:CHAN_BOND_SEQ_1_MASK[1]
3	GT10:CHAN_BOND_SEQ_1_MASK[0]
2	-
1	GT10:ALIGN_COMMA_WORD[1]
0	GT10:ALIGN_COMMA_WORD[0]

virtex2 GIGABIT10.T bittile 6
Bit	Frame
Bit	0
79	GT10:PMA_SPEED[39]
78	GT10:PMA_SPEED[38]
77	GT10:PMA_SPEED[37]
76	GT10:PMA_SPEED[36]
75	GT10:PMA_SPEED[35]
74	GT10:PMA_SPEED[34]
73	GT10:PMA_SPEED[33]
72	GT10:PMA_SPEED[32]
71	GT10:PMA_SPEED[31]
70	GT10:PMA_SPEED[30]
69	GT10:PMA_SPEED[29]
68	GT10:PMA_SPEED[28]
67	GT10:PMA_SPEED[27]
66	GT10:PMA_SPEED[26]
65	GT10:PMA_SPEED[25]
64	GT10:PMA_SPEED[24]
63	GT10:PMA_SPEED[23]
62	GT10:PMA_SPEED[22]
61	GT10:PMA_SPEED[21]
60	GT10:PMA_SPEED[20]
59	GT10:PMA_SPEED[19]
58	GT10:PMA_SPEED[18]
57	GT10:PMA_SPEED[17]
56	GT10:PMA_SPEED[16]
55	GT10:PMA_SPEED[15]
54	GT10:PMA_SPEED[14]
53	GT10:PMA_SPEED[13]
52	GT10:PMA_SPEED[12]
51	GT10:PMA_SPEED[11]
50	GT10:PMA_SPEED[10]
49	GT10:PMA_SPEED[9]
48	GT10:PMA_SPEED[8]
47	GT10:PMA_SPEED[7]
46	GT10:PMA_SPEED[6]
45	GT10:PMA_SPEED[5]
44	GT10:PMA_SPEED[4]
43	GT10:PMA_SPEED[3]
42	GT10:PMA_SPEED[2]
41	GT10:PMA_SPEED[1]
40	GT10:PMA_SPEED[0]
39	-
38	-
37	-
36	-
35	-
34	-
33	-
32	-
31	-
30	-
29	-
28	-
27	-
26	-
25	-
24	-
23	-
22	-
21	-
20	-
19	-
18	-
17	-
16	-
15	-
14	-
13	GT10:CLK_COR_SEQ_DROP
12	-
11	GT10:CLK_COR_SEQ_2_MASK[3]
10	GT10:CLK_COR_SEQ_2_MASK[2]
9	GT10:CLK_COR_SEQ_2_MASK[1]
8	GT10:CLK_COR_SEQ_2_MASK[0]
7	-
6	GT10:CLK_COR_SEQ_1_MASK[3]
5	GT10:CLK_COR_SEQ_1_MASK[2]
4	GT10:CLK_COR_SEQ_1_MASK[1]
3	-
2	GT10:CLK_COR_SEQ_1_MASK[0]
1	-
0	-

virtex2 GIGABIT10.T bittile 7
Bit	Frame
Bit	0
79	GT10:PMA_SPEED[119]
78	GT10:PMA_SPEED[118]
77	GT10:PMA_SPEED[117]
76	GT10:PMA_SPEED[116]
75	GT10:PMA_SPEED[115]
74	GT10:PMA_SPEED[114]
73	GT10:PMA_SPEED[113]
72	GT10:PMA_SPEED[112]
71	GT10:PMA_SPEED[111]
70	GT10:PMA_SPEED[110]
69	GT10:PMA_SPEED[109]
68	GT10:PMA_SPEED[108]
67	GT10:PMA_SPEED[107]
66	GT10:PMA_SPEED[106]
65	GT10:PMA_SPEED[105]
64	GT10:PMA_SPEED[104]
63	GT10:PMA_SPEED[103]
62	GT10:PMA_SPEED[102]
61	GT10:PMA_SPEED[101]
60	GT10:PMA_SPEED[100]
59	GT10:PMA_SPEED[99]
58	GT10:PMA_SPEED[98]
57	GT10:PMA_SPEED[97]
56	GT10:PMA_SPEED[96]
55	GT10:PMA_SPEED[95]
54	GT10:PMA_SPEED[94]
53	GT10:PMA_SPEED[93]
52	GT10:PMA_SPEED[92]
51	GT10:PMA_SPEED[91]
50	GT10:PMA_SPEED[90]
49	GT10:PMA_SPEED[89]
48	GT10:PMA_SPEED[88]
47	GT10:PMA_SPEED[87]
46	GT10:PMA_SPEED[86]
45	GT10:PMA_SPEED[85]
44	GT10:PMA_SPEED[84]
43	GT10:PMA_SPEED[83]
42	GT10:PMA_SPEED[82]
41	GT10:PMA_SPEED[81]
40	GT10:PMA_SPEED[80]
39	GT10:PMA_SPEED[79]
38	GT10:PMA_SPEED[78]
37	GT10:PMA_SPEED[77]
36	GT10:PMA_SPEED[76]
35	GT10:PMA_SPEED[75]
34	GT10:PMA_SPEED[74]
33	GT10:PMA_SPEED[73]
32	GT10:PMA_SPEED[72]
31	GT10:PMA_SPEED[71]
30	GT10:PMA_SPEED[70]
29	GT10:PMA_SPEED[69]
28	GT10:PMA_SPEED[68]
27	GT10:PMA_SPEED[67]
26	GT10:PMA_SPEED[66]
25	GT10:PMA_SPEED[65]
24	GT10:PMA_SPEED[64]
23	GT10:PMA_SPEED[63]
22	GT10:PMA_SPEED[62]
21	GT10:PMA_SPEED[61]
20	GT10:PMA_SPEED[60]
19	GT10:PMA_SPEED[59]
18	GT10:PMA_SPEED[58]
17	GT10:PMA_SPEED[57]
16	GT10:PMA_SPEED[56]
15	GT10:PMA_SPEED[55]
14	GT10:PMA_SPEED[54]
13	GT10:PMA_SPEED[53]
12	GT10:PMA_SPEED[52]
11	GT10:PMA_SPEED[51]
10	GT10:PMA_SPEED[50]
9	GT10:PMA_SPEED[49]
8	GT10:PMA_SPEED[48]
7	GT10:PMA_SPEED[47]
6	GT10:PMA_SPEED[46]
5	GT10:PMA_SPEED[45]
4	GT10:PMA_SPEED[44]
3	-
2	GT10:PMA_SPEED[42]
1	GT10:PMA_SPEED[41]
0	GT10:PMA_SPEED[40]

virtex2 GIGABIT10.T bittile 8
Bit	Frame
Bit	0
30	GT10:SH_INVALID_CNT_MAX[7]
29	GT10:SH_INVALID_CNT_MAX[6]
28	GT10:SH_INVALID_CNT_MAX[5]
27	GT10:SH_INVALID_CNT_MAX[4]
26	GT10:SH_INVALID_CNT_MAX[3]
25	GT10:SH_INVALID_CNT_MAX[2]
24	GT10:SH_INVALID_CNT_MAX[1]
23	GT10:SH_INVALID_CNT_MAX[0]
22	GT10:SH_CNT_MAX[7]
21	GT10:SH_CNT_MAX[6]
20	GT10:SH_CNT_MAX[5]
19	GT10:SH_CNT_MAX[4]
18	GT10:SH_CNT_MAX[3]
17	GT10:SH_CNT_MAX[2]
16	GT10:SH_CNT_MAX[1]
15	GT10:SH_CNT_MAX[0]
14	-
13	-
12	-
11	-
10	-
9	-
8	-
7	-
6	-
5	-
4	-
3	-
2	GT10:PMA_SPEED[43]
1	-
0	-

GT10:ALIGN_COMMA_WORD	5.0.1	5.0.0
1	0	0
2	0	1
4	1	0

GT10:CHAN_BOND_64B66B_SV	5.0.33
GT10:CHAN_BOND_ONE_SHOT	2.0.23
GT10:CHAN_BOND_SEQ_2_USE	4.0.35
GT10:CLK_CORRECT_USE	2.0.10
GT10:CLK_COR_8B10B_DE	5.0.32
GT10:CLK_COR_INSERT_IDLE_FLAG	2.0.11
GT10:CLK_COR_KEEP_IDLE	2.0.12
GT10:CLK_COR_SEQ_2_USE	2.0.35
GT10:CLK_COR_SEQ_DROP	6.0.13
GT10:DEC_MCOMMA_DETECT	2.0.32
GT10:DEC_PCOMMA_DETECT	2.0.31
GT10:DEC_VALID_COMMA_ONLY	2.0.30
GT10:ENABLE	0.0.74
GT10:MCOMMA_DETECT	1.0.22
GT10:PCOMMA_DETECT	1.0.34
GT10:RX_BUFFER_USE	2.0.25
GT10:RX_CRC_USE	3.0.35
GT10:RX_LOSS_OF_SYNC_FSM	4.0.23
GT10:TEST_MODE_1	3.0.11
GT10:TEST_MODE_2	3.0.12
GT10:TEST_MODE_3	3.0.13
GT10:TEST_MODE_4	3.0.14
GT10:TEST_MODE_5	3.0.15
GT10:TEST_MODE_6	3.0.16
GT10:TX_BUFFER_USE	0.0.36
GT10:TX_CRC_USE	0.0.37
non-inverted	[0]

GT10:CHAN_BOND_LIMIT	4.0.28	4.0.27	4.0.26	4.0.25	4.0.24
GT10:CLK_COR_ADJ_MAX	5.0.17	5.0.16	5.0.15	5.0.14	5.0.13
GT10:CLK_COR_REPEAT_WAIT	2.0.17	2.0.16	2.0.15	2.0.14	2.0.13
non-inverted	[4]	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_MODE	2.0.4	2.0.2
NONE	0	0
MASTER	0	1
SLAVE_1_HOP	1	0
SLAVE_2_HOPS	1	1

GT10:CHAN_BOND_SEQ_1_1	3.0.79	3.0.78	3.0.77	3.0.76	3.0.75	3.0.74	3.0.73	3.0.72	3.0.71	3.0.70	3.0.69
GT10:CHAN_BOND_SEQ_1_2	3.0.68	3.0.67	3.0.66	3.0.65	3.0.64	3.0.63	3.0.62	3.0.61	3.0.60	3.0.59	3.0.58
GT10:CHAN_BOND_SEQ_1_3	3.0.57	3.0.56	3.0.55	3.0.54	3.0.53	3.0.52	3.0.51	3.0.50	3.0.49	3.0.48	3.0.47
GT10:CHAN_BOND_SEQ_1_4	3.0.46	3.0.45	3.0.44	3.0.43	3.0.42	3.0.41	3.0.40	3.0.39	3.0.38	3.0.37	3.0.36
GT10:CHAN_BOND_SEQ_2_1	4.0.79	4.0.78	4.0.77	4.0.76	4.0.75	4.0.74	4.0.73	4.0.72	4.0.71	4.0.70	4.0.69
GT10:CHAN_BOND_SEQ_2_2	4.0.68	4.0.67	4.0.66	4.0.65	4.0.64	4.0.63	4.0.62	4.0.61	4.0.60	4.0.59	4.0.58
GT10:CHAN_BOND_SEQ_2_3	4.0.57	4.0.56	4.0.55	4.0.54	4.0.53	4.0.52	4.0.51	4.0.50	4.0.49	4.0.48	4.0.47
GT10:CHAN_BOND_SEQ_2_4	4.0.46	4.0.45	4.0.44	4.0.43	4.0.42	4.0.41	4.0.40	4.0.39	4.0.38	4.0.37	4.0.36
GT10:CLK_COR_SEQ_1_1	1.0.79	1.0.78	1.0.77	1.0.76	1.0.75	1.0.74	1.0.73	1.0.72	1.0.71	1.0.70	1.0.69
GT10:CLK_COR_SEQ_1_2	1.0.68	1.0.67	1.0.66	1.0.65	1.0.64	1.0.63	1.0.62	1.0.61	1.0.60	1.0.59	1.0.58
GT10:CLK_COR_SEQ_1_3	1.0.57	1.0.56	1.0.55	1.0.54	1.0.53	1.0.52	1.0.51	1.0.50	1.0.49	1.0.48	1.0.47
GT10:CLK_COR_SEQ_1_4	1.0.46	1.0.45	1.0.44	1.0.43	1.0.42	1.0.41	1.0.40	1.0.39	1.0.38	1.0.37	1.0.36
GT10:CLK_COR_SEQ_2_1	2.0.79	2.0.78	2.0.77	2.0.76	2.0.75	2.0.74	2.0.73	2.0.72	2.0.71	2.0.70	2.0.69
GT10:CLK_COR_SEQ_2_2	2.0.68	2.0.67	2.0.66	2.0.65	2.0.64	2.0.63	2.0.62	2.0.61	2.0.60	2.0.59	2.0.58
GT10:CLK_COR_SEQ_2_3	2.0.57	2.0.56	2.0.55	2.0.54	2.0.53	2.0.52	2.0.51	2.0.50	2.0.49	2.0.48	2.0.47
GT10:CLK_COR_SEQ_2_4	2.0.46	2.0.45	2.0.44	2.0.43	2.0.42	2.0.41	2.0.40	2.0.39	2.0.38	2.0.37	2.0.36
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_SEQ_1_MASK	5.0.6	5.0.5	5.0.4	5.0.3
GT10:CHAN_BOND_SEQ_2_MASK	5.0.11	5.0.10	5.0.9	5.0.8
GT10:CLK_COR_SEQ_1_MASK	6.0.6	6.0.5	6.0.4	6.0.2
GT10:CLK_COR_SEQ_2_MASK	6.0.11	6.0.10	6.0.9	6.0.8
non-inverted	[3]	[2]	[1]	[0]

GT10:CHAN_BOND_SEQ_LEN	3.0.28	3.0.27	3.0.26
GT10:CLK_COR_SEQ_LEN	3.0.24	3.0.23	3.0.22
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
8	1	1	1

GT10:CLK_COR_MAX_LAT	5.0.30	5.0.29	5.0.28	5.0.27	5.0.26	5.0.25
GT10:CLK_COR_MIN_LAT	5.0.24	5.0.23	5.0.22	5.0.21	5.0.20	5.0.19
non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

GT10:COMMA_10B_MASK	1.0.10	1.0.9	1.0.8	1.0.7	1.0.6	1.0.5	1.0.4	1.0.3	1.0.2	1.0.1
GT10:MCOMMA_10B_VALUE	1.0.20	1.0.19	1.0.18	1.0.17	1.0.16	1.0.15	1.0.14	1.0.13	1.0.12	1.0.11
GT10:PCOMMA_10B_VALUE	1.0.32	1.0.31	1.0.30	1.0.29	1.0.28	1.0.27	1.0.26	1.0.25	1.0.24	1.0.23
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:CRC_END_OF_PKT	0.0.77	0.0.76	0.0.75	0.0.73	0.0.72	0.0.71	0.0.70
K28_0	0	0	0	1	1	0	0
K28_1	0	0	1	1	1	0	0
K28_2	0	1	0	1	1	0	0
K28_3	0	1	1	1	1	0	0
K28_4	1	0	0	1	1	0	0
K28_5	1	0	1	1	1	0	0
K28_6	1	1	0	1	1	0	0
K23_7	1	1	1	0	1	1	1
K27_7	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	0

GT10:CRC_FORMAT	0.0.4	0.0.3
USER_MODE	0	0
ETHERNET	0	1
FIBRE_CHAN	1	0
INFINIBAND	1	1

GT10:CRC_START_OF_PKT	0.0.20	0.0.19	0.0.18	0.0.17	0.0.16	0.0.15	0.0.14	0.0.13
K28_0	0	0	0	1	1	1	0	0
K28_1	0	0	1	1	1	1	0	0
K28_2	0	1	0	1	1	1	0	0
K28_3	0	1	1	1	1	1	0	0
K28_4	1	0	0	1	1	1	0	0
K28_5	1	0	1	1	1	1	0	0
K28_6	1	1	0	1	1	1	0	0
K23_7	1	1	1	1	0	1	1	1
K27_7	1	1	1	1	1	0	1	1
K28_7	1	1	1	1	1	1	0	0
K29_7	1	1	1	1	1	1	0	1
K30_7	1	1	1	1	1	1	1	0

GT10:PMA_PWR_CNTRL	5.0.57	5.0.56	5.0.55	5.0.54	5.0.53	5.0.52	5.0.51	5.0.50
GT10:SH_CNT_MAX	8.0.22	8.0.21	8.0.20	8.0.19	8.0.18	8.0.17	8.0.16	8.0.15
GT10:SH_INVALID_CNT_MAX	8.0.30	8.0.29	8.0.28	8.0.27	8.0.26	8.0.25	8.0.24	8.0.23
GT10:TX_CRC_FORCE_VALUE	0.0.45	0.0.44	0.0.43	0.0.42	0.0.41	0.0.40	0.0.39	0.0.38
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:PMA_SPEED	7.0.79	7.0.78	7.0.77	7.0.76	7.0.75	7.0.74	7.0.73	7.0.72	7.0.71	7.0.70	7.0.69	7.0.68	7.0.67	7.0.66	7.0.65	7.0.64	7.0.63	7.0.62	7.0.61	7.0.60	7.0.59	7.0.58	7.0.57	7.0.56	7.0.55	7.0.54	7.0.53	7.0.52	7.0.51	7.0.50	7.0.49	7.0.48	7.0.47	7.0.46	7.0.45	7.0.44	7.0.43	7.0.42	7.0.41	7.0.40	7.0.39	7.0.38	7.0.37	7.0.36	7.0.35	7.0.34	7.0.33	7.0.32	7.0.31	7.0.30	7.0.29	7.0.28	7.0.27	7.0.26	7.0.25	7.0.24	7.0.23	7.0.22	7.0.21	7.0.20	7.0.19	7.0.18	7.0.17	7.0.16	7.0.15	7.0.14	7.0.13	7.0.12	7.0.11	7.0.10	7.0.9	7.0.8	7.0.7	7.0.6	7.0.5	7.0.4	8.0.2	7.0.2	7.0.1	7.0.0	6.0.79	6.0.78	6.0.77	6.0.76	6.0.75	6.0.74	6.0.73	6.0.72	6.0.71	6.0.70	6.0.69	6.0.68	6.0.67	6.0.66	6.0.65	6.0.64	6.0.63	6.0.62	6.0.61	6.0.60	6.0.59	6.0.58	6.0.57	6.0.56	6.0.55	6.0.54	6.0.53	6.0.52	6.0.51	6.0.50	6.0.49	6.0.48	6.0.47	6.0.46	6.0.45	6.0.44	6.0.43	6.0.42	6.0.41	6.0.40
non-inverted	[119]	[118]	[117]	[116]	[115]	[114]	[113]	[112]	[111]	[110]	[109]	[108]	[107]	[106]	[105]	[104]	[103]	[102]	[101]	[100]	[99]	[98]	[97]	[96]	[95]	[94]	[93]	[92]	[91]	[90]	[89]	[88]	[87]	[86]	[85]	[84]	[83]	[82]	[81]	[80]	[79]	[78]	[77]	[76]	[75]	[74]	[73]	[72]	[71]	[70]	[69]	[68]	[67]	[66]	[65]	[64]	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT10:RX_LOS_INVALID_INCR	4.0.30	4.0.22	4.0.21	4.0.20	4.0.19	4.0.18	4.0.17	4.0.16
1	0	0	0	0	0	0	0	1
2	0	0	0	0	0	0	1	0
4	0	0	0	0	0	1	0	0
8	0	0	0	0	1	0	0	0
16	0	0	0	1	0	0	0	0
32	0	0	1	0	0	0	0	0
64	0	1	0	0	0	0	0	0
128	1	0	0	0	0	0	0	0

GT10:RX_LOS_THRESHOLD	4.0.15	4.0.14	4.0.13	4.0.12	4.0.11	4.0.10	4.0.9	4.0.8
4	0	0	0	0	0	0	0	1
8	0	0	0	0	0	0	1	0
16	0	0	0	0	0	1	0	0
32	0	0	0	0	1	0	0	0
64	0	0	0	1	0	0	0	0
128	0	0	1	0	0	0	0	0
256	0	1	0	0	0	0	0	0
512	1	0	0	0	0	0	0	0

`PMA_SPEED` values

Name	GT10:PMA_SPEED
Name	[119]	[118]	[117]	[116]	[115]	[114]	[113]	[112]	[111]	[110]	[109]	[108]	[107]	[106]	[105]	[104]	[103]	[102]	[101]	[100]	[99]	[98]	[97]	[96]	[95]	[94]	[93]	[92]	[91]	[90]	[89]	[88]	[87]	[86]	[85]	[84]	[83]	[82]	[81]	[80]	[79]	[78]	[77]	[76]	[75]	[74]	[73]	[72]	[71]	[70]	[69]	[68]	[67]	[66]	[65]	[64]	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]
0_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	1	0	0	0	0	0	0	0	1	1	0	1	0	0	0
0_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	1	0	0	0	0	0	0	0	1	1	0	1	0	0	0
10_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	0	1	1	0	1	0	0	0
10_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	0	0	1	1	0	1	0	0	0
11_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	1	0	1	1	0	1	0	0	0
11_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	1	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	0	1	0	0	1	0	0	1	0	1	1	0	1	0	0	0
12_40	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	1	0	1	1	1	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	0	1	0	0	1	1	0	1	0	0	0
12_80	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	1	0	1	1	1	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	0	1	0	0	1	1	0	1	0	0	0
13_40	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	0	0	0	1	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	0	0	0	0	0	1	1	0	1	1	1	0	0	1	1	0	0	0	0	1	0	0	1	0	0	0	1	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	1	1	0	0	1	1	0	1	0	0	0
13_80	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	0	0	0	1	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	0	0	0	0	0	1	1	0	1	1	1	0	0	1	1	0	0	0	0	1	0	0	1	0	0	0	1	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	1	1	0	0	1	1	0	1	0	0	0
14_40	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	1	0	1	1	1	0	1	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	1	0	1	0	1	0	1	0	0	1	1	0	1	0	0	0
14_80	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	1	0	1	1	1	0	1	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	1	1	0	1	1	0	1	0	1	0	1	0	0	1	1	0	1	0	0	0
15_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0
15_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	0
16_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	0	0	0	0	1	0	0	0	1	1	0	1	0	0	0
16_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	0	0	0	0	0	1	0	0	0	1	1	0	1	0	0	0
17_32	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	1	0	0	0	0	1	0	0	0	0	1	1	0	1	0	0	0
17_64	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	0	0	1	0	0	1	1	0	0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	1	0	0	0	0	1	0	0	0	0	1	1	0	1	0	0	0
18_40	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	1	0	0	0	1	0	0	0	0	0	1	1	0	1	1	1	0	0	0	1	0	0	0	0	1	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	1	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	0	1	0	0	0	1	0	1	0	0	0
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22_80	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	1	1	0	1	1	1	0	0	1	1	0	0	0	0	1	0	0	1	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	1	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
23_10	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	1	0	0	1	1	0	0	1	0	0	0	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
23_20	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	1	0	0	1	1	0	0	1	0	0	1	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
23_40	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	0	0	0	0	1	0	1	1	0	0	0	0	0	0	0	1	0	0	1	1	0	0	1	0	0	1	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
24_10	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	0	1	0	0	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	0	0	1	0	0	0	1	0	1	0	0	0
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24_40	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	1	1	0	0	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	0	1	0	0	0	1	0	1	0	0	0
25_10	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	0	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
25_20	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	1	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	0	0	1	0	1	0	0	0
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26_10	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	0	1	0	1	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	1	0	1	0	0	0	1	0	1	0	0	0
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27_10	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	0	1	0	0	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	0	0	1	0	0	0	1	0	0	0	0	0
27_20	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	1	1	0	0	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	0	1	0	0	0	1	0	0	0	0	0
27_40	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	1	1	0	0	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	0	0	1	0	0	0	1	0	0	0	0	0
28_10	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	0	1	0	0	1	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	1	0	1	0	0	1	1	0	0	0	1	0	0	0	0	0
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29_40	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	1	0	0	1	1	0	1	0	1	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	1	1	0	1	0	1	0	1	0	0	0	1	0	0	0	0	0
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30_8	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	1	1	0	0	1	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0	0
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