Global buffers

Tile CLK_BUFG

Cells: 18

Switchbox SPEC_INT

virtex4 CLK_BUFG switchbox SPEC_INT permanent buffers
Destination	Source
CELL[8].GCLK[0]	CELL[8].OUT_BUFG[0]
CELL[8].GCLK[1]	CELL[8].OUT_BUFG[1]
CELL[8].GCLK[2]	CELL[8].OUT_BUFG[2]
CELL[8].GCLK[3]	CELL[8].OUT_BUFG[3]
CELL[8].GCLK[4]	CELL[8].OUT_BUFG[4]
CELL[8].GCLK[5]	CELL[8].OUT_BUFG[5]
CELL[8].GCLK[6]	CELL[8].OUT_BUFG[6]
CELL[8].GCLK[7]	CELL[8].OUT_BUFG[7]
CELL[8].GCLK[8]	CELL[8].OUT_BUFG[8]
CELL[8].GCLK[9]	CELL[8].OUT_BUFG[9]
CELL[8].GCLK[10]	CELL[8].OUT_BUFG[10]
CELL[8].GCLK[11]	CELL[8].OUT_BUFG[11]
CELL[8].GCLK[12]	CELL[8].OUT_BUFG[12]
CELL[8].GCLK[13]	CELL[8].OUT_BUFG[13]
CELL[8].GCLK[14]	CELL[8].OUT_BUFG[14]
CELL[8].GCLK[15]	CELL[8].OUT_BUFG[15]
CELL[8].GCLK[16]	CELL[8].OUT_BUFG[16]
CELL[8].GCLK[17]	CELL[8].OUT_BUFG[17]
CELL[8].GCLK[18]	CELL[8].OUT_BUFG[18]
CELL[8].GCLK[19]	CELL[8].OUT_BUFG[19]
CELL[8].GCLK[20]	CELL[8].OUT_BUFG[20]
CELL[8].GCLK[21]	CELL[8].OUT_BUFG[21]
CELL[8].GCLK[22]	CELL[8].OUT_BUFG[22]
CELL[8].GCLK[23]	CELL[8].OUT_BUFG[23]
CELL[8].GCLK[24]	CELL[8].OUT_BUFG[24]
CELL[8].GCLK[25]	CELL[8].OUT_BUFG[25]
CELL[8].GCLK[26]	CELL[8].OUT_BUFG[26]
CELL[8].GCLK[27]	CELL[8].OUT_BUFG[27]
CELL[8].GCLK[28]	CELL[8].OUT_BUFG[28]
CELL[8].GCLK[29]	CELL[8].OUT_BUFG[29]
CELL[8].GCLK[30]	CELL[8].OUT_BUFG[30]
CELL[8].GCLK[31]	CELL[8].OUT_BUFG[31]

virtex4 CLK_BUFG switchbox SPEC_INT muxes IMUX_SPEC[0]
Bits												Destination
MAIN[1][1][28]	MAIN[1][1][29]	MAIN[1][1][26]	MAIN[1][0][30]	MAIN[1][1][27]	MAIN[1][1][22]	MAIN[1][1][23]	MAIN[1][1][24]	MAIN[1][1][25]	MAIN[1][0][31]	MAIN[1][1][20]	MAIN[1][1][21]	CELL[0].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[1][1][60]	MAIN[1][1][61]	MAIN[1][1][58]	MAIN[1][0][62]	MAIN[1][1][59]	MAIN[1][1][54]	MAIN[1][1][55]	MAIN[1][1][56]	MAIN[1][1][57]	MAIN[1][0][63]	MAIN[1][1][52]	MAIN[1][1][53]	-	CELL[1].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][1][28]	MAIN[2][1][29]	MAIN[2][1][26]	MAIN[2][0][30]	MAIN[2][1][27]	MAIN[2][1][22]	MAIN[2][1][23]	MAIN[2][1][24]	MAIN[2][1][25]	MAIN[2][0][31]	MAIN[2][1][20]	MAIN[2][1][21]	-	-	CELL[2].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][1][60]	MAIN[2][1][61]	MAIN[2][1][58]	MAIN[2][0][62]	MAIN[2][1][59]	MAIN[2][1][54]	MAIN[2][1][55]	MAIN[2][1][56]	MAIN[2][1][57]	MAIN[2][0][63]	MAIN[2][1][52]	MAIN[2][1][53]	-	-	-	CELL[3].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][1][28]	MAIN[3][1][29]	MAIN[3][1][26]	MAIN[3][0][30]	MAIN[3][1][27]	MAIN[3][1][22]	MAIN[3][1][23]	MAIN[3][1][24]	MAIN[3][1][25]	MAIN[3][0][31]	MAIN[3][1][20]	MAIN[3][1][21]	-	-	-	-	CELL[4].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][1][60]	MAIN[3][1][61]	MAIN[3][1][58]	MAIN[3][0][62]	MAIN[3][1][59]	MAIN[3][1][54]	MAIN[3][1][55]	MAIN[3][1][56]	MAIN[3][1][57]	MAIN[3][0][63]	MAIN[3][1][52]	MAIN[3][1][53]	-	-	-	-	-	CELL[5].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-	-
MAIN[4][1][28]	MAIN[4][1][29]	MAIN[4][1][26]	MAIN[4][0][30]	MAIN[4][1][27]	MAIN[4][1][22]	MAIN[4][1][23]	MAIN[4][1][24]	MAIN[4][1][25]	MAIN[4][0][31]	MAIN[4][1][20]	MAIN[4][1][21]	-	-	-	-	-	-	CELL[6].IMUX_SPEC[0]	-	-	-	-	-	-	-	-	-
MAIN[4][1][60]	MAIN[4][1][61]	MAIN[4][1][58]	MAIN[4][0][62]	MAIN[4][1][59]	MAIN[4][1][54]	MAIN[4][1][55]	MAIN[4][1][56]	MAIN[4][1][57]	MAIN[4][0][63]	MAIN[4][1][52]	MAIN[4][1][53]	-	-	-	-	-	-	-	CELL[7].IMUX_SPEC[0]	-	-	-	-	-	-	-	-
MAIN[11][1][5]	MAIN[11][0][0]	MAIN[11][1][3]	MAIN[11][1][2]	MAIN[11][1][4]	MAIN[11][0][1]	MAIN[11][1][9]	MAIN[11][1][8]	MAIN[11][1][7]	MAIN[11][1][6]	MAIN[11][1][11]	MAIN[11][1][10]	-	-	-	-	-	-	-	-	CELL[8].IMUX_SPEC[0]	-	-	-	-	-	-	-
MAIN[11][1][37]	MAIN[11][0][32]	MAIN[11][1][35]	MAIN[11][1][34]	MAIN[11][1][36]	MAIN[11][0][33]	MAIN[11][1][41]	MAIN[11][1][40]	MAIN[11][1][39]	MAIN[11][1][38]	MAIN[11][1][43]	MAIN[11][1][42]	-	-	-	-	-	-	-	-	-	CELL[9].IMUX_SPEC[0]	-	-	-	-	-	-
MAIN[12][1][5]	MAIN[12][0][0]	MAIN[12][1][3]	MAIN[12][1][2]	MAIN[12][1][4]	MAIN[12][0][1]	MAIN[12][1][9]	MAIN[12][1][8]	MAIN[12][1][7]	MAIN[12][1][6]	MAIN[12][1][11]	MAIN[12][1][10]	-	-	-	-	-	-	-	-	-	-	CELL[10].IMUX_SPEC[0]	-	-	-	-	-
MAIN[12][1][37]	MAIN[12][0][32]	MAIN[12][1][35]	MAIN[12][1][34]	MAIN[12][1][36]	MAIN[12][0][33]	MAIN[12][1][41]	MAIN[12][1][40]	MAIN[12][1][39]	MAIN[12][1][38]	MAIN[12][1][43]	MAIN[12][1][42]	-	-	-	-	-	-	-	-	-	-	-	CELL[11].IMUX_SPEC[0]	-	-	-	-
MAIN[13][1][5]	MAIN[13][0][0]	MAIN[13][1][3]	MAIN[13][1][2]	MAIN[13][1][4]	MAIN[13][0][1]	MAIN[13][1][9]	MAIN[13][1][8]	MAIN[13][1][7]	MAIN[13][1][6]	MAIN[13][1][11]	MAIN[13][1][10]	-	-	-	-	-	-	-	-	-	-	-	-	CELL[12].IMUX_SPEC[0]	-	-	-
MAIN[13][1][37]	MAIN[13][0][32]	MAIN[13][1][35]	MAIN[13][1][34]	MAIN[13][1][36]	MAIN[13][0][33]	MAIN[13][1][41]	MAIN[13][1][40]	MAIN[13][1][39]	MAIN[13][1][38]	MAIN[13][1][43]	MAIN[13][1][42]	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[13].IMUX_SPEC[0]	-	-
MAIN[14][1][5]	MAIN[14][0][0]	MAIN[14][1][3]	MAIN[14][1][2]	MAIN[14][1][4]	MAIN[14][0][1]	MAIN[14][1][9]	MAIN[14][1][8]	MAIN[14][1][7]	MAIN[14][1][6]	MAIN[14][1][11]	MAIN[14][1][10]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[14].IMUX_SPEC[0]	-
MAIN[14][1][37]	MAIN[14][0][32]	MAIN[14][1][35]	MAIN[14][1][34]	MAIN[14][1][36]	MAIN[14][0][33]	MAIN[14][1][41]	MAIN[14][1][40]	MAIN[14][1][39]	MAIN[14][1][38]	MAIN[14][1][43]	MAIN[14][1][42]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[15].IMUX_SPEC[0]
												Source
0	0	0	0	0	0	0	0	0	0	0	0	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off
0	0	0	0	1	0	0	0	0	0	0	1	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]
0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]
0	0	0	0	1	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]
0	0	0	0	1	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]
0	0	0	0	1	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]
0	0	0	0	1	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]
0	0	0	0	1	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	-	-	-	-	-	-	-	-
0	0	0	1	0	0	0	0	0	0	0	1	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]
0	0	0	1	0	0	0	0	0	0	1	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]
0	0	0	1	0	0	0	0	0	1	0	0	CELL[0].IMUX_BUFG_I[1]	CELL[0].IMUX_BUFG_I[5]	CELL[0].IMUX_BUFG_I[9]	CELL[0].IMUX_BUFG_I[13]	CELL[0].IMUX_BUFG_I[17]	CELL[0].IMUX_BUFG_I[21]	CELL[0].IMUX_BUFG_I[25]	CELL[0].IMUX_BUFG_I[29]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]
0	0	0	1	0	0	0	0	1	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]
0	0	0	1	0	0	0	1	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]
0	0	0	1	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]
0	0	1	0	0	0	0	0	0	0	0	1	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]
0	0	1	0	0	0	0	0	0	0	1	0	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]
0	0	1	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]
0	0	1	0	0	0	0	0	1	0	0	0	CELL[1].IMUX_IMUX[3]	CELL[1].IMUX_IMUX[19]	CELL[2].IMUX_IMUX[3]	CELL[2].IMUX_IMUX[19]	CELL[3].IMUX_IMUX[3]	CELL[3].IMUX_IMUX[19]	CELL[4].IMUX_IMUX[3]	CELL[4].IMUX_IMUX[19]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]
0	0	1	0	0	0	0	1	0	0	0	0	CELL[1].IMUX_IMUX[11]	CELL[1].IMUX_IMUX[27]	CELL[2].IMUX_IMUX[11]	CELL[2].IMUX_IMUX[27]	CELL[3].IMUX_IMUX[11]	CELL[3].IMUX_IMUX[27]	CELL[4].IMUX_IMUX[11]	CELL[4].IMUX_IMUX[27]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]
0	0	1	0	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]
0	1	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	-	-	-	-	-	-	-	-
0	1	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].IMUX_BUFG_I[31]	CELL[8].IMUX_BUFG_I[27]	CELL[8].IMUX_BUFG_I[23]	CELL[8].IMUX_BUFG_I[19]	CELL[8].IMUX_BUFG_I[15]	CELL[8].IMUX_BUFG_I[11]	CELL[8].IMUX_BUFG_I[7]	CELL[8].IMUX_BUFG_I[3]
1	0	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]
1	0	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]
1	0	0	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[11].IMUX_IMUX[3]	CELL[11].IMUX_IMUX[19]	CELL[12].IMUX_IMUX[3]	CELL[12].IMUX_IMUX[19]	CELL[13].IMUX_IMUX[3]	CELL[13].IMUX_IMUX[19]	CELL[14].IMUX_IMUX[3]	CELL[14].IMUX_IMUX[19]
1	0	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[11].IMUX_IMUX[11]	CELL[11].IMUX_IMUX[27]	CELL[12].IMUX_IMUX[11]	CELL[12].IMUX_IMUX[27]	CELL[13].IMUX_IMUX[11]	CELL[13].IMUX_IMUX[27]	CELL[14].IMUX_IMUX[11]	CELL[14].IMUX_IMUX[27]
1	0	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	-	-	-	-	-	-	-	-
1	0	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	-	-	-	-	-	-	-	-
1	0	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	-	-	-	-	-	-	-	-

virtex4 CLK_BUFG switchbox SPEC_INT muxes IMUX_SPEC[1]
Bits												Destination
MAIN[1][0][28]	MAIN[1][0][29]	MAIN[1][0][26]	MAIN[1][1][30]	MAIN[1][0][27]	MAIN[1][0][22]	MAIN[1][0][23]	MAIN[1][0][24]	MAIN[1][0][25]	MAIN[1][1][31]	MAIN[1][0][20]	MAIN[1][0][21]	CELL[0].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[1][0][60]	MAIN[1][0][61]	MAIN[1][0][58]	MAIN[1][1][62]	MAIN[1][0][59]	MAIN[1][0][54]	MAIN[1][0][55]	MAIN[1][0][56]	MAIN[1][0][57]	MAIN[1][1][63]	MAIN[1][0][52]	MAIN[1][0][53]	-	CELL[1].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][0][28]	MAIN[2][0][29]	MAIN[2][0][26]	MAIN[2][1][30]	MAIN[2][0][27]	MAIN[2][0][22]	MAIN[2][0][23]	MAIN[2][0][24]	MAIN[2][0][25]	MAIN[2][1][31]	MAIN[2][0][20]	MAIN[2][0][21]	-	-	CELL[2].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][0][60]	MAIN[2][0][61]	MAIN[2][0][58]	MAIN[2][1][62]	MAIN[2][0][59]	MAIN[2][0][54]	MAIN[2][0][55]	MAIN[2][0][56]	MAIN[2][0][57]	MAIN[2][1][63]	MAIN[2][0][52]	MAIN[2][0][53]	-	-	-	CELL[3].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][0][28]	MAIN[3][0][29]	MAIN[3][0][26]	MAIN[3][1][30]	MAIN[3][0][27]	MAIN[3][0][22]	MAIN[3][0][23]	MAIN[3][0][24]	MAIN[3][0][25]	MAIN[3][1][31]	MAIN[3][0][20]	MAIN[3][0][21]	-	-	-	-	CELL[4].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][0][60]	MAIN[3][0][61]	MAIN[3][0][58]	MAIN[3][1][62]	MAIN[3][0][59]	MAIN[3][0][54]	MAIN[3][0][55]	MAIN[3][0][56]	MAIN[3][0][57]	MAIN[3][1][63]	MAIN[3][0][52]	MAIN[3][0][53]	-	-	-	-	-	CELL[5].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-	-
MAIN[4][0][28]	MAIN[4][0][29]	MAIN[4][0][26]	MAIN[4][1][30]	MAIN[4][0][27]	MAIN[4][0][22]	MAIN[4][0][23]	MAIN[4][0][24]	MAIN[4][0][25]	MAIN[4][1][31]	MAIN[4][0][20]	MAIN[4][0][21]	-	-	-	-	-	-	CELL[6].IMUX_SPEC[1]	-	-	-	-	-	-	-	-	-
MAIN[4][0][60]	MAIN[4][0][61]	MAIN[4][0][58]	MAIN[4][1][62]	MAIN[4][0][59]	MAIN[4][0][54]	MAIN[4][0][55]	MAIN[4][0][56]	MAIN[4][0][57]	MAIN[4][1][63]	MAIN[4][0][52]	MAIN[4][0][53]	-	-	-	-	-	-	-	CELL[7].IMUX_SPEC[1]	-	-	-	-	-	-	-	-
MAIN[11][0][5]	MAIN[11][1][0]	MAIN[11][0][3]	MAIN[11][0][2]	MAIN[11][0][4]	MAIN[11][1][1]	MAIN[11][0][9]	MAIN[11][0][8]	MAIN[11][0][7]	MAIN[11][0][6]	MAIN[11][0][11]	MAIN[11][0][10]	-	-	-	-	-	-	-	-	CELL[8].IMUX_SPEC[1]	-	-	-	-	-	-	-
MAIN[11][0][37]	MAIN[11][1][32]	MAIN[11][0][35]	MAIN[11][0][34]	MAIN[11][0][36]	MAIN[11][1][33]	MAIN[11][0][41]	MAIN[11][0][40]	MAIN[11][0][39]	MAIN[11][0][38]	MAIN[11][0][43]	MAIN[11][0][42]	-	-	-	-	-	-	-	-	-	CELL[9].IMUX_SPEC[1]	-	-	-	-	-	-
MAIN[12][0][5]	MAIN[12][1][0]	MAIN[12][0][3]	MAIN[12][0][2]	MAIN[12][0][4]	MAIN[12][1][1]	MAIN[12][0][9]	MAIN[12][0][8]	MAIN[12][0][7]	MAIN[12][0][6]	MAIN[12][0][11]	MAIN[12][0][10]	-	-	-	-	-	-	-	-	-	-	CELL[10].IMUX_SPEC[1]	-	-	-	-	-
MAIN[12][0][37]	MAIN[12][1][32]	MAIN[12][0][35]	MAIN[12][0][34]	MAIN[12][0][36]	MAIN[12][1][33]	MAIN[12][0][41]	MAIN[12][0][40]	MAIN[12][0][39]	MAIN[12][0][38]	MAIN[12][0][43]	MAIN[12][0][42]	-	-	-	-	-	-	-	-	-	-	-	CELL[11].IMUX_SPEC[1]	-	-	-	-
MAIN[13][0][5]	MAIN[13][1][0]	MAIN[13][0][3]	MAIN[13][0][2]	MAIN[13][0][4]	MAIN[13][1][1]	MAIN[13][0][9]	MAIN[13][0][8]	MAIN[13][0][7]	MAIN[13][0][6]	MAIN[13][0][11]	MAIN[13][0][10]	-	-	-	-	-	-	-	-	-	-	-	-	CELL[12].IMUX_SPEC[1]	-	-	-
MAIN[13][0][37]	MAIN[13][1][32]	MAIN[13][0][35]	MAIN[13][0][34]	MAIN[13][0][36]	MAIN[13][1][33]	MAIN[13][0][41]	MAIN[13][0][40]	MAIN[13][0][39]	MAIN[13][0][38]	MAIN[13][0][43]	MAIN[13][0][42]	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[13].IMUX_SPEC[1]	-	-
MAIN[14][0][5]	MAIN[14][1][0]	MAIN[14][0][3]	MAIN[14][0][2]	MAIN[14][0][4]	MAIN[14][1][1]	MAIN[14][0][9]	MAIN[14][0][8]	MAIN[14][0][7]	MAIN[14][0][6]	MAIN[14][0][11]	MAIN[14][0][10]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[14].IMUX_SPEC[1]	-
MAIN[14][0][37]	MAIN[14][1][32]	MAIN[14][0][35]	MAIN[14][0][34]	MAIN[14][0][36]	MAIN[14][1][33]	MAIN[14][0][41]	MAIN[14][0][40]	MAIN[14][0][39]	MAIN[14][0][38]	MAIN[14][0][43]	MAIN[14][0][42]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[15].IMUX_SPEC[1]
												Source
0	0	0	0	0	0	0	0	0	0	0	0	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off
0	0	0	0	1	0	0	0	0	0	0	1	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]
0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]
0	0	0	0	1	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]
0	0	0	0	1	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]
0	0	0	0	1	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]
0	0	0	0	1	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]
0	0	0	0	1	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	-	-	-	-	-	-	-	-
0	0	0	1	0	0	0	0	0	0	0	1	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]
0	0	0	1	0	0	0	0	0	0	1	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]
0	0	0	1	0	0	0	0	0	1	0	0	CELL[0].IMUX_BUFG_I[0]	CELL[0].IMUX_BUFG_I[4]	CELL[0].IMUX_BUFG_I[8]	CELL[0].IMUX_BUFG_I[12]	CELL[0].IMUX_BUFG_I[16]	CELL[0].IMUX_BUFG_I[20]	CELL[0].IMUX_BUFG_I[24]	CELL[0].IMUX_BUFG_I[28]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]
0	0	0	1	0	0	0	0	1	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]
0	0	0	1	0	0	0	1	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]
0	0	0	1	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]
0	0	1	0	0	0	0	0	0	0	0	1	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]
0	0	1	0	0	0	0	0	0	0	1	0	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]
0	0	1	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]
0	0	1	0	0	0	0	0	1	0	0	0	CELL[1].IMUX_IMUX[3]	CELL[1].IMUX_IMUX[19]	CELL[2].IMUX_IMUX[3]	CELL[2].IMUX_IMUX[19]	CELL[3].IMUX_IMUX[3]	CELL[3].IMUX_IMUX[19]	CELL[4].IMUX_IMUX[3]	CELL[4].IMUX_IMUX[19]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]
0	0	1	0	0	0	0	1	0	0	0	0	CELL[1].IMUX_IMUX[11]	CELL[1].IMUX_IMUX[27]	CELL[2].IMUX_IMUX[11]	CELL[2].IMUX_IMUX[27]	CELL[3].IMUX_IMUX[11]	CELL[3].IMUX_IMUX[27]	CELL[4].IMUX_IMUX[11]	CELL[4].IMUX_IMUX[27]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]
0	0	1	0	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]
0	1	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	-	-	-	-	-	-	-	-
0	1	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].IMUX_BUFG_I[30]	CELL[8].IMUX_BUFG_I[26]	CELL[8].IMUX_BUFG_I[22]	CELL[8].IMUX_BUFG_I[18]	CELL[8].IMUX_BUFG_I[14]	CELL[8].IMUX_BUFG_I[10]	CELL[8].IMUX_BUFG_I[6]	CELL[8].IMUX_BUFG_I[2]
1	0	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]
1	0	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]
1	0	0	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[11].IMUX_IMUX[3]	CELL[11].IMUX_IMUX[19]	CELL[12].IMUX_IMUX[3]	CELL[12].IMUX_IMUX[19]	CELL[13].IMUX_IMUX[3]	CELL[13].IMUX_IMUX[19]	CELL[14].IMUX_IMUX[3]	CELL[14].IMUX_IMUX[19]
1	0	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[11].IMUX_IMUX[11]	CELL[11].IMUX_IMUX[27]	CELL[12].IMUX_IMUX[11]	CELL[12].IMUX_IMUX[27]	CELL[13].IMUX_IMUX[11]	CELL[13].IMUX_IMUX[27]	CELL[14].IMUX_IMUX[11]	CELL[14].IMUX_IMUX[27]
1	0	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	-	-	-	-	-	-	-	-
1	0	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	-	-	-	-	-	-	-	-
1	0	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	-	-	-	-	-	-	-	-

virtex4 CLK_BUFG switchbox SPEC_INT muxes IMUX_SPEC[2]
Bits												Destination
MAIN[1][1][44]	MAIN[1][1][45]	MAIN[1][1][42]	MAIN[1][0][46]	MAIN[1][1][43]	MAIN[1][1][38]	MAIN[1][1][39]	MAIN[1][1][40]	MAIN[1][1][41]	MAIN[1][0][47]	MAIN[1][1][36]	MAIN[1][1][37]	CELL[0].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[1][1][76]	MAIN[1][1][77]	MAIN[1][1][74]	MAIN[1][0][78]	MAIN[1][1][75]	MAIN[1][1][70]	MAIN[1][1][71]	MAIN[1][1][72]	MAIN[1][1][73]	MAIN[1][0][79]	MAIN[1][1][68]	MAIN[1][1][69]	-	CELL[1].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][1][44]	MAIN[2][1][45]	MAIN[2][1][42]	MAIN[2][0][46]	MAIN[2][1][43]	MAIN[2][1][38]	MAIN[2][1][39]	MAIN[2][1][40]	MAIN[2][1][41]	MAIN[2][0][47]	MAIN[2][1][36]	MAIN[2][1][37]	-	-	CELL[2].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][1][76]	MAIN[2][1][77]	MAIN[2][1][74]	MAIN[2][0][78]	MAIN[2][1][75]	MAIN[2][1][70]	MAIN[2][1][71]	MAIN[2][1][72]	MAIN[2][1][73]	MAIN[2][0][79]	MAIN[2][1][68]	MAIN[2][1][69]	-	-	-	CELL[3].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][1][44]	MAIN[3][1][45]	MAIN[3][1][42]	MAIN[3][0][46]	MAIN[3][1][43]	MAIN[3][1][38]	MAIN[3][1][39]	MAIN[3][1][40]	MAIN[3][1][41]	MAIN[3][0][47]	MAIN[3][1][36]	MAIN[3][1][37]	-	-	-	-	CELL[4].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][1][76]	MAIN[3][1][77]	MAIN[3][1][74]	MAIN[3][0][78]	MAIN[3][1][75]	MAIN[3][1][70]	MAIN[3][1][71]	MAIN[3][1][72]	MAIN[3][1][73]	MAIN[3][0][79]	MAIN[3][1][68]	MAIN[3][1][69]	-	-	-	-	-	CELL[5].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-	-
MAIN[4][1][44]	MAIN[4][1][45]	MAIN[4][1][42]	MAIN[4][0][46]	MAIN[4][1][43]	MAIN[4][1][38]	MAIN[4][1][39]	MAIN[4][1][40]	MAIN[4][1][41]	MAIN[4][0][47]	MAIN[4][1][36]	MAIN[4][1][37]	-	-	-	-	-	-	CELL[6].IMUX_SPEC[2]	-	-	-	-	-	-	-	-	-
MAIN[4][1][76]	MAIN[4][1][77]	MAIN[4][1][74]	MAIN[4][0][78]	MAIN[4][1][75]	MAIN[4][1][70]	MAIN[4][1][71]	MAIN[4][1][72]	MAIN[4][1][73]	MAIN[4][0][79]	MAIN[4][1][68]	MAIN[4][1][69]	-	-	-	-	-	-	-	CELL[7].IMUX_SPEC[2]	-	-	-	-	-	-	-	-
MAIN[11][1][21]	MAIN[11][0][16]	MAIN[11][1][19]	MAIN[11][1][18]	MAIN[11][1][20]	MAIN[11][0][17]	MAIN[11][1][25]	MAIN[11][1][24]	MAIN[11][1][23]	MAIN[11][1][22]	MAIN[11][1][27]	MAIN[11][1][26]	-	-	-	-	-	-	-	-	CELL[8].IMUX_SPEC[2]	-	-	-	-	-	-	-
MAIN[11][1][53]	MAIN[11][0][48]	MAIN[11][1][51]	MAIN[11][1][50]	MAIN[11][1][52]	MAIN[11][0][49]	MAIN[11][1][57]	MAIN[11][1][56]	MAIN[11][1][55]	MAIN[11][1][54]	MAIN[11][1][59]	MAIN[11][1][58]	-	-	-	-	-	-	-	-	-	CELL[9].IMUX_SPEC[2]	-	-	-	-	-	-
MAIN[12][1][21]	MAIN[12][0][16]	MAIN[12][1][19]	MAIN[12][1][18]	MAIN[12][1][20]	MAIN[12][0][17]	MAIN[12][1][25]	MAIN[12][1][24]	MAIN[12][1][23]	MAIN[12][1][22]	MAIN[12][1][27]	MAIN[12][1][26]	-	-	-	-	-	-	-	-	-	-	CELL[10].IMUX_SPEC[2]	-	-	-	-	-
MAIN[12][1][53]	MAIN[12][0][48]	MAIN[12][1][51]	MAIN[12][1][50]	MAIN[12][1][52]	MAIN[12][0][49]	MAIN[12][1][57]	MAIN[12][1][56]	MAIN[12][1][55]	MAIN[12][1][54]	MAIN[12][1][59]	MAIN[12][1][58]	-	-	-	-	-	-	-	-	-	-	-	CELL[11].IMUX_SPEC[2]	-	-	-	-
MAIN[13][1][21]	MAIN[13][0][16]	MAIN[13][1][19]	MAIN[13][1][18]	MAIN[13][1][20]	MAIN[13][0][17]	MAIN[13][1][25]	MAIN[13][1][24]	MAIN[13][1][23]	MAIN[13][1][22]	MAIN[13][1][27]	MAIN[13][1][26]	-	-	-	-	-	-	-	-	-	-	-	-	CELL[12].IMUX_SPEC[2]	-	-	-
MAIN[13][1][53]	MAIN[13][0][48]	MAIN[13][1][51]	MAIN[13][1][50]	MAIN[13][1][52]	MAIN[13][0][49]	MAIN[13][1][57]	MAIN[13][1][56]	MAIN[13][1][55]	MAIN[13][1][54]	MAIN[13][1][59]	MAIN[13][1][58]	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[13].IMUX_SPEC[2]	-	-
MAIN[14][1][21]	MAIN[14][0][16]	MAIN[14][1][19]	MAIN[14][1][18]	MAIN[14][1][20]	MAIN[14][0][17]	MAIN[14][1][25]	MAIN[14][1][24]	MAIN[14][1][23]	MAIN[14][1][22]	MAIN[14][1][27]	MAIN[14][1][26]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[14].IMUX_SPEC[2]	-
MAIN[14][1][53]	MAIN[14][0][48]	MAIN[14][1][51]	MAIN[14][1][50]	MAIN[14][1][52]	MAIN[14][0][49]	MAIN[14][1][57]	MAIN[14][1][56]	MAIN[14][1][55]	MAIN[14][1][54]	MAIN[14][1][59]	MAIN[14][1][58]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[15].IMUX_SPEC[2]
												Source
0	0	0	0	0	0	0	0	0	0	0	0	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off
0	0	0	0	1	0	0	0	0	0	0	1	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]
0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]
0	0	0	0	1	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]
0	0	0	0	1	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]
0	0	0	0	1	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]
0	0	0	0	1	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]
0	0	0	0	1	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	-	-	-	-	-	-	-	-
0	0	0	1	0	0	0	0	0	0	0	1	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]
0	0	0	1	0	0	0	0	0	0	1	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]
0	0	0	1	0	0	0	0	0	1	0	0	CELL[0].IMUX_BUFG_I[3]	CELL[0].IMUX_BUFG_I[7]	CELL[0].IMUX_BUFG_I[11]	CELL[0].IMUX_BUFG_I[15]	CELL[0].IMUX_BUFG_I[19]	CELL[0].IMUX_BUFG_I[23]	CELL[0].IMUX_BUFG_I[27]	CELL[0].IMUX_BUFG_I[31]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]
0	0	0	1	0	0	0	0	1	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]
0	0	0	1	0	0	0	1	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]
0	0	0	1	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]
0	0	1	0	0	0	0	0	0	0	0	1	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]
0	0	1	0	0	0	0	0	0	0	1	0	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]
0	0	1	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]
0	0	1	0	0	0	0	0	1	0	0	0	CELL[1].IMUX_IMUX[7]	CELL[1].IMUX_IMUX[23]	CELL[2].IMUX_IMUX[7]	CELL[2].IMUX_IMUX[23]	CELL[3].IMUX_IMUX[7]	CELL[3].IMUX_IMUX[23]	CELL[4].IMUX_IMUX[7]	CELL[4].IMUX_IMUX[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]
0	0	1	0	0	0	0	1	0	0	0	0	CELL[1].IMUX_IMUX[15]	CELL[1].IMUX_IMUX[31]	CELL[2].IMUX_IMUX[15]	CELL[2].IMUX_IMUX[31]	CELL[3].IMUX_IMUX[15]	CELL[3].IMUX_IMUX[31]	CELL[4].IMUX_IMUX[15]	CELL[4].IMUX_IMUX[31]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]
0	0	1	0	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]
0	1	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	-	-	-	-	-	-	-	-
0	1	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].IMUX_BUFG_I[29]	CELL[8].IMUX_BUFG_I[25]	CELL[8].IMUX_BUFG_I[21]	CELL[8].IMUX_BUFG_I[17]	CELL[8].IMUX_BUFG_I[13]	CELL[8].IMUX_BUFG_I[9]	CELL[8].IMUX_BUFG_I[5]	CELL[8].IMUX_BUFG_I[1]
1	0	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]
1	0	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]
1	0	0	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[11].IMUX_IMUX[7]	CELL[11].IMUX_IMUX[23]	CELL[12].IMUX_IMUX[7]	CELL[12].IMUX_IMUX[23]	CELL[13].IMUX_IMUX[7]	CELL[13].IMUX_IMUX[23]	CELL[14].IMUX_IMUX[7]	CELL[14].IMUX_IMUX[23]
1	0	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[11].IMUX_IMUX[15]	CELL[11].IMUX_IMUX[31]	CELL[12].IMUX_IMUX[15]	CELL[12].IMUX_IMUX[31]	CELL[13].IMUX_IMUX[15]	CELL[13].IMUX_IMUX[31]	CELL[14].IMUX_IMUX[15]	CELL[14].IMUX_IMUX[31]
1	0	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	-	-	-	-	-	-	-	-
1	0	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	-	-	-	-	-	-	-	-
1	0	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	-	-	-	-	-	-	-	-

virtex4 CLK_BUFG switchbox SPEC_INT muxes IMUX_SPEC[3]
Bits												Destination
MAIN[1][0][44]	MAIN[1][0][45]	MAIN[1][0][42]	MAIN[1][1][46]	MAIN[1][0][43]	MAIN[1][0][38]	MAIN[1][0][39]	MAIN[1][0][40]	MAIN[1][0][41]	MAIN[1][1][47]	MAIN[1][0][36]	MAIN[1][0][37]	CELL[0].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[1][0][76]	MAIN[1][0][77]	MAIN[1][0][74]	MAIN[1][1][78]	MAIN[1][0][75]	MAIN[1][0][70]	MAIN[1][0][71]	MAIN[1][0][72]	MAIN[1][0][73]	MAIN[1][1][79]	MAIN[1][0][68]	MAIN[1][0][69]	-	CELL[1].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][0][44]	MAIN[2][0][45]	MAIN[2][0][42]	MAIN[2][1][46]	MAIN[2][0][43]	MAIN[2][0][38]	MAIN[2][0][39]	MAIN[2][0][40]	MAIN[2][0][41]	MAIN[2][1][47]	MAIN[2][0][36]	MAIN[2][0][37]	-	-	CELL[2].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[2][0][76]	MAIN[2][0][77]	MAIN[2][0][74]	MAIN[2][1][78]	MAIN[2][0][75]	MAIN[2][0][70]	MAIN[2][0][71]	MAIN[2][0][72]	MAIN[2][0][73]	MAIN[2][1][79]	MAIN[2][0][68]	MAIN[2][0][69]	-	-	-	CELL[3].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][0][44]	MAIN[3][0][45]	MAIN[3][0][42]	MAIN[3][1][46]	MAIN[3][0][43]	MAIN[3][0][38]	MAIN[3][0][39]	MAIN[3][0][40]	MAIN[3][0][41]	MAIN[3][1][47]	MAIN[3][0][36]	MAIN[3][0][37]	-	-	-	-	CELL[4].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-	-
MAIN[3][0][76]	MAIN[3][0][77]	MAIN[3][0][74]	MAIN[3][1][78]	MAIN[3][0][75]	MAIN[3][0][70]	MAIN[3][0][71]	MAIN[3][0][72]	MAIN[3][0][73]	MAIN[3][1][79]	MAIN[3][0][68]	MAIN[3][0][69]	-	-	-	-	-	CELL[5].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-	-
MAIN[4][0][44]	MAIN[4][0][45]	MAIN[4][0][42]	MAIN[4][1][46]	MAIN[4][0][43]	MAIN[4][0][38]	MAIN[4][0][39]	MAIN[4][0][40]	MAIN[4][0][41]	MAIN[4][1][47]	MAIN[4][0][36]	MAIN[4][0][37]	-	-	-	-	-	-	CELL[6].IMUX_SPEC[3]	-	-	-	-	-	-	-	-	-
MAIN[4][0][76]	MAIN[4][0][77]	MAIN[4][0][74]	MAIN[4][1][78]	MAIN[4][0][75]	MAIN[4][0][70]	MAIN[4][0][71]	MAIN[4][0][72]	MAIN[4][0][73]	MAIN[4][1][79]	MAIN[4][0][68]	MAIN[4][0][69]	-	-	-	-	-	-	-	CELL[7].IMUX_SPEC[3]	-	-	-	-	-	-	-	-
MAIN[11][0][21]	MAIN[11][1][16]	MAIN[11][0][19]	MAIN[11][0][18]	MAIN[11][0][20]	MAIN[11][1][17]	MAIN[11][0][25]	MAIN[11][0][24]	MAIN[11][0][23]	MAIN[11][0][22]	MAIN[11][0][27]	MAIN[11][0][26]	-	-	-	-	-	-	-	-	CELL[8].IMUX_SPEC[3]	-	-	-	-	-	-	-
MAIN[11][0][53]	MAIN[11][1][48]	MAIN[11][0][51]	MAIN[11][0][50]	MAIN[11][0][52]	MAIN[11][1][49]	MAIN[11][0][57]	MAIN[11][0][56]	MAIN[11][0][55]	MAIN[11][0][54]	MAIN[11][0][59]	MAIN[11][0][58]	-	-	-	-	-	-	-	-	-	CELL[9].IMUX_SPEC[3]	-	-	-	-	-	-
MAIN[12][0][21]	MAIN[12][1][16]	MAIN[12][0][19]	MAIN[12][0][18]	MAIN[12][0][20]	MAIN[12][1][17]	MAIN[12][0][25]	MAIN[12][0][24]	MAIN[12][0][23]	MAIN[12][0][22]	MAIN[12][0][27]	MAIN[12][0][26]	-	-	-	-	-	-	-	-	-	-	CELL[10].IMUX_SPEC[3]	-	-	-	-	-
MAIN[12][0][53]	MAIN[12][1][48]	MAIN[12][0][51]	MAIN[12][0][50]	MAIN[12][0][52]	MAIN[12][1][49]	MAIN[12][0][57]	MAIN[12][0][56]	MAIN[12][0][55]	MAIN[12][0][54]	MAIN[12][0][59]	MAIN[12][0][58]	-	-	-	-	-	-	-	-	-	-	-	CELL[11].IMUX_SPEC[3]	-	-	-	-
MAIN[13][0][21]	MAIN[13][1][16]	MAIN[13][0][19]	MAIN[13][0][18]	MAIN[13][0][20]	MAIN[13][1][17]	MAIN[13][0][25]	MAIN[13][0][24]	MAIN[13][0][23]	MAIN[13][0][22]	MAIN[13][0][27]	MAIN[13][0][26]	-	-	-	-	-	-	-	-	-	-	-	-	CELL[12].IMUX_SPEC[3]	-	-	-
MAIN[13][0][53]	MAIN[13][1][48]	MAIN[13][0][51]	MAIN[13][0][50]	MAIN[13][0][52]	MAIN[13][1][49]	MAIN[13][0][57]	MAIN[13][0][56]	MAIN[13][0][55]	MAIN[13][0][54]	MAIN[13][0][59]	MAIN[13][0][58]	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[13].IMUX_SPEC[3]	-	-
MAIN[14][0][21]	MAIN[14][1][16]	MAIN[14][0][19]	MAIN[14][0][18]	MAIN[14][0][20]	MAIN[14][1][17]	MAIN[14][0][25]	MAIN[14][0][24]	MAIN[14][0][23]	MAIN[14][0][22]	MAIN[14][0][27]	MAIN[14][0][26]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[14].IMUX_SPEC[3]	-
MAIN[14][0][53]	MAIN[14][1][48]	MAIN[14][0][51]	MAIN[14][0][50]	MAIN[14][0][52]	MAIN[14][1][49]	MAIN[14][0][57]	MAIN[14][0][56]	MAIN[14][0][55]	MAIN[14][0][54]	MAIN[14][0][59]	MAIN[14][0][58]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CELL[15].IMUX_SPEC[3]
												Source
0	0	0	0	0	0	0	0	0	0	0	0	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off	off
0	0	0	0	1	0	0	0	0	0	0	1	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[0].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]	CELL[8].MGT_ROW[0]
0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[0].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]	CELL[8].MGT_ROW[1]
0	0	0	0	1	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[28]
0	0	0	0	1	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[29]
0	0	0	0	1	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[30]
0	0	0	0	1	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]	CELL[8].OUT_BUFG[31]
0	0	0	0	1	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[15]	-	-	-	-	-	-	-	-
0	0	0	1	0	0	0	0	0	0	0	1	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[20]
0	0	0	1	0	0	0	0	0	0	1	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[21]
0	0	0	1	0	0	0	0	0	1	0	0	CELL[0].IMUX_BUFG_I[2]	CELL[0].IMUX_BUFG_I[6]	CELL[0].IMUX_BUFG_I[10]	CELL[0].IMUX_BUFG_I[14]	CELL[0].IMUX_BUFG_I[18]	CELL[0].IMUX_BUFG_I[22]	CELL[0].IMUX_BUFG_I[26]	CELL[0].IMUX_BUFG_I[30]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[16]
0	0	0	1	0	0	0	0	1	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[17]
0	0	0	1	0	0	0	1	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[18]
0	0	0	1	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[19]
0	0	1	0	0	0	0	0	0	0	0	1	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL_E0.MGT_ROW[0]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[26]
0	0	1	0	0	0	0	0	0	0	1	0	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL_E0.MGT_ROW[1]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[27]
0	0	1	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[22]
0	0	1	0	0	0	0	0	1	0	0	0	CELL[1].IMUX_IMUX[7]	CELL[1].IMUX_IMUX[23]	CELL[2].IMUX_IMUX[7]	CELL[2].IMUX_IMUX[23]	CELL[3].IMUX_IMUX[7]	CELL[3].IMUX_IMUX[23]	CELL[4].IMUX_IMUX[7]	CELL[4].IMUX_IMUX[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[23]
0	0	1	0	0	0	0	1	0	0	0	0	CELL[1].IMUX_IMUX[15]	CELL[1].IMUX_IMUX[31]	CELL[2].IMUX_IMUX[15]	CELL[2].IMUX_IMUX[31]	CELL[3].IMUX_IMUX[15]	CELL[3].IMUX_IMUX[31]	CELL[4].IMUX_IMUX[15]	CELL[4].IMUX_IMUX[31]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[24]
0	0	1	0	0	0	1	0	0	0	0	0	-	-	-	-	-	-	-	-	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[25]
0	1	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[4]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[5]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[0]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[1]	-	-	-	-	-	-	-	-
0	1	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[2]	-	-	-	-	-	-	-	-
0	1	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[3]	CELL[8].IMUX_BUFG_I[28]	CELL[8].IMUX_BUFG_I[24]	CELL[8].IMUX_BUFG_I[20]	CELL[8].IMUX_BUFG_I[16]	CELL[8].IMUX_BUFG_I[12]	CELL[8].IMUX_BUFG_I[8]	CELL[8].IMUX_BUFG_I[4]	CELL[8].IMUX_BUFG_I[0]
1	0	0	0	0	0	0	0	0	0	0	1	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[10]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]	CELL_E8.MGT_ROW[0]
1	0	0	0	0	0	0	0	0	0	1	0	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[11]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]	CELL_E8.MGT_ROW[1]
1	0	0	0	0	0	0	0	0	1	0	0	-	-	-	-	-	-	-	-	CELL[11].IMUX_IMUX[7]	CELL[11].IMUX_IMUX[23]	CELL[12].IMUX_IMUX[7]	CELL[12].IMUX_IMUX[23]	CELL[13].IMUX_IMUX[7]	CELL[13].IMUX_IMUX[23]	CELL[14].IMUX_IMUX[7]	CELL[14].IMUX_IMUX[23]
1	0	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[6]	CELL[11].IMUX_IMUX[15]	CELL[11].IMUX_IMUX[31]	CELL[12].IMUX_IMUX[15]	CELL[12].IMUX_IMUX[31]	CELL[13].IMUX_IMUX[15]	CELL[13].IMUX_IMUX[31]	CELL[14].IMUX_IMUX[15]	CELL[14].IMUX_IMUX[31]
1	0	0	0	0	0	0	1	0	0	0	0	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[7]	-	-	-	-	-	-	-	-
1	0	0	0	0	0	1	0	0	0	0	0	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[8]	-	-	-	-	-	-	-	-
1	0	0	0	0	1	0	0	0	0	0	0	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[9]	-	-	-	-	-	-	-	-

virtex4 CLK_BUFG wire support CELL[0].IMUX_SPEC[0], CELL[0].IMUX_SPEC[1]
Bit
MAIN[1][1][19]

virtex4 CLK_BUFG wire support CELL[0].IMUX_SPEC[2], CELL[0].IMUX_SPEC[3]
Bit
MAIN[1][1][35]

virtex4 CLK_BUFG wire support CELL[0].MGT_ROW[0]
Bit
MAIN[1][0][15]

virtex4 CLK_BUFG wire support CELL[0].MGT_ROW[1]
Bit
MAIN[1][0][14]

virtex4 CLK_BUFG wire support CELL[1].IMUX_SPEC[0], CELL[1].IMUX_SPEC[1]
Bit
MAIN[1][1][51]

virtex4 CLK_BUFG wire support CELL[1].IMUX_SPEC[2], CELL[1].IMUX_SPEC[3]
Bit
MAIN[1][1][67]

virtex4 CLK_BUFG wire support CELL[2].IMUX_SPEC[0], CELL[2].IMUX_SPEC[1]
Bit
MAIN[2][1][19]

virtex4 CLK_BUFG wire support CELL[2].IMUX_SPEC[2], CELL[2].IMUX_SPEC[3]
Bit
MAIN[2][1][35]

virtex4 CLK_BUFG wire support CELL[3].IMUX_SPEC[0], CELL[3].IMUX_SPEC[1]
Bit
MAIN[2][1][51]

virtex4 CLK_BUFG wire support CELL[3].IMUX_SPEC[2], CELL[3].IMUX_SPEC[3]
Bit
MAIN[2][1][67]

virtex4 CLK_BUFG wire support CELL[4].IMUX_SPEC[0], CELL[4].IMUX_SPEC[1]
Bit
MAIN[3][1][19]

virtex4 CLK_BUFG wire support CELL[4].IMUX_SPEC[2], CELL[4].IMUX_SPEC[3]
Bit
MAIN[3][1][35]

virtex4 CLK_BUFG wire support CELL[5].IMUX_SPEC[0], CELL[5].IMUX_SPEC[1]
Bit
MAIN[3][1][51]

virtex4 CLK_BUFG wire support CELL[5].IMUX_SPEC[2], CELL[5].IMUX_SPEC[3]
Bit
MAIN[3][1][67]

virtex4 CLK_BUFG wire support CELL[6].IMUX_SPEC[0], CELL[6].IMUX_SPEC[1]
Bit
MAIN[4][1][19]

virtex4 CLK_BUFG wire support CELL[6].IMUX_SPEC[2], CELL[6].IMUX_SPEC[3]
Bit
MAIN[4][1][35]

virtex4 CLK_BUFG wire support CELL[7].IMUX_SPEC[0], CELL[7].IMUX_SPEC[1]
Bit
MAIN[4][1][51]

virtex4 CLK_BUFG wire support CELL[7].IMUX_SPEC[2], CELL[7].IMUX_SPEC[3]
Bit
MAIN[4][1][67]

virtex4 CLK_BUFG wire support CELL[8].IMUX_SPEC[0], CELL[8].IMUX_SPEC[1]
Bit
MAIN[11][1][12]

virtex4 CLK_BUFG wire support CELL[8].IMUX_SPEC[2], CELL[8].IMUX_SPEC[3]
Bit
MAIN[11][1][28]

virtex4 CLK_BUFG wire support CELL[8].MGT_ROW[0]
Bit
MAIN[14][0][64]

virtex4 CLK_BUFG wire support CELL[8].MGT_ROW[1]
Bit
MAIN[14][0][65]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[0]
Bit
MAIN[6][0][7]
MAIN[6][1][6]
MAIN[6][1][7]
MAIN[6][1][8]
MAIN[6][1][9]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[1]
Bit
MAIN[6][0][17]
MAIN[6][1][16]
MAIN[6][1][17]
MAIN[6][1][18]
MAIN[6][1][19]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[2]
Bit
MAIN[6][0][27]
MAIN[6][1][26]
MAIN[6][1][27]
MAIN[6][1][28]
MAIN[6][1][29]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[3]
Bit
MAIN[6][0][37]
MAIN[6][1][36]
MAIN[6][1][37]
MAIN[6][1][38]
MAIN[6][1][39]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[4]
Bit
MAIN[6][0][47]
MAIN[6][1][46]
MAIN[6][1][47]
MAIN[6][1][48]
MAIN[6][1][49]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[5]
Bit
MAIN[6][0][57]
MAIN[6][1][56]
MAIN[6][1][57]
MAIN[6][1][58]
MAIN[6][1][59]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[6]
Bit
MAIN[6][0][67]
MAIN[6][1][66]
MAIN[6][1][67]
MAIN[6][1][68]
MAIN[6][1][69]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[7]
Bit
MAIN[6][0][77]
MAIN[6][1][76]
MAIN[6][1][77]
MAIN[6][1][78]
MAIN[6][1][79]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[8]
Bit
MAIN[7][0][7]
MAIN[7][1][6]
MAIN[7][1][7]
MAIN[7][1][8]
MAIN[7][1][9]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[9]
Bit
MAIN[7][0][17]
MAIN[7][1][16]
MAIN[7][1][17]
MAIN[7][1][18]
MAIN[7][1][19]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[10]
Bit
MAIN[7][0][27]
MAIN[7][1][26]
MAIN[7][1][27]
MAIN[7][1][28]
MAIN[7][1][29]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[11]
Bit
MAIN[7][0][37]
MAIN[7][1][36]
MAIN[7][1][37]
MAIN[7][1][38]
MAIN[7][1][39]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[12]
Bit
MAIN[7][0][47]
MAIN[7][1][46]
MAIN[7][1][47]
MAIN[7][1][48]
MAIN[7][1][49]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[13]
Bit
MAIN[7][0][57]
MAIN[7][1][56]
MAIN[7][1][57]
MAIN[7][1][58]
MAIN[7][1][59]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[14]
Bit
MAIN[7][0][67]
MAIN[7][1][66]
MAIN[7][1][67]
MAIN[7][1][68]
MAIN[7][1][69]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[15]
Bit
MAIN[7][0][77]
MAIN[7][1][76]
MAIN[7][1][77]
MAIN[7][1][78]
MAIN[7][1][79]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[16]
Bit
MAIN[9][0][72]
MAIN[9][1][70]
MAIN[9][1][71]
MAIN[9][1][72]
MAIN[9][1][73]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[17]
Bit
MAIN[9][0][62]
MAIN[9][1][60]
MAIN[9][1][61]
MAIN[9][1][62]
MAIN[9][1][63]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[18]
Bit
MAIN[9][0][52]
MAIN[9][1][50]
MAIN[9][1][51]
MAIN[9][1][52]
MAIN[9][1][53]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[19]
Bit
MAIN[9][0][42]
MAIN[9][1][40]
MAIN[9][1][41]
MAIN[9][1][42]
MAIN[9][1][43]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[20]
Bit
MAIN[9][0][32]
MAIN[9][1][30]
MAIN[9][1][31]
MAIN[9][1][32]
MAIN[9][1][33]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[21]
Bit
MAIN[9][0][22]
MAIN[9][1][20]
MAIN[9][1][21]
MAIN[9][1][22]
MAIN[9][1][23]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[22]
Bit
MAIN[9][0][12]
MAIN[9][1][10]
MAIN[9][1][11]
MAIN[9][1][12]
MAIN[9][1][13]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[23]
Bit
MAIN[9][0][2]
MAIN[9][1][0]
MAIN[9][1][1]
MAIN[9][1][2]
MAIN[9][1][3]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[24]
Bit
MAIN[8][0][72]
MAIN[8][1][70]
MAIN[8][1][71]
MAIN[8][1][72]
MAIN[8][1][73]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[25]
Bit
MAIN[8][0][62]
MAIN[8][1][60]
MAIN[8][1][61]
MAIN[8][1][62]
MAIN[8][1][63]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[26]
Bit
MAIN[8][0][52]
MAIN[8][1][50]
MAIN[8][1][51]
MAIN[8][1][52]
MAIN[8][1][53]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[27]
Bit
MAIN[8][0][42]
MAIN[8][1][40]
MAIN[8][1][41]
MAIN[8][1][42]
MAIN[8][1][43]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[28]
Bit
MAIN[8][0][32]
MAIN[8][1][30]
MAIN[8][1][31]
MAIN[8][1][32]
MAIN[8][1][33]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[29]
Bit
MAIN[8][0][22]
MAIN[8][1][20]
MAIN[8][1][21]
MAIN[8][1][22]
MAIN[8][1][23]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[30]
Bit
MAIN[8][0][12]
MAIN[8][1][10]
MAIN[8][1][11]
MAIN[8][1][12]
MAIN[8][1][13]

virtex4 CLK_BUFG wire support CELL[8].OUT_BUFG[31]
Bit
MAIN[8][0][2]
MAIN[8][1][0]
MAIN[8][1][1]
MAIN[8][1][2]
MAIN[8][1][3]

virtex4 CLK_BUFG wire support CELL[9].IMUX_SPEC[0], CELL[9].IMUX_SPEC[1]
Bit
MAIN[11][1][44]

virtex4 CLK_BUFG wire support CELL[9].IMUX_SPEC[2], CELL[9].IMUX_SPEC[3]
Bit
MAIN[11][1][60]

virtex4 CLK_BUFG wire support CELL[10].IMUX_SPEC[0], CELL[10].IMUX_SPEC[1]
Bit
MAIN[12][1][12]

virtex4 CLK_BUFG wire support CELL[10].IMUX_SPEC[2], CELL[10].IMUX_SPEC[3]
Bit
MAIN[12][1][28]

virtex4 CLK_BUFG wire support CELL[11].IMUX_SPEC[0], CELL[11].IMUX_SPEC[1]
Bit
MAIN[12][1][44]

virtex4 CLK_BUFG wire support CELL[11].IMUX_SPEC[2], CELL[11].IMUX_SPEC[3]
Bit
MAIN[12][1][60]

virtex4 CLK_BUFG wire support CELL[12].IMUX_SPEC[0], CELL[12].IMUX_SPEC[1]
Bit
MAIN[13][1][12]

virtex4 CLK_BUFG wire support CELL[12].IMUX_SPEC[2], CELL[12].IMUX_SPEC[3]
Bit
MAIN[13][1][28]

virtex4 CLK_BUFG wire support CELL[13].IMUX_SPEC[0], CELL[13].IMUX_SPEC[1]
Bit
MAIN[13][1][44]

virtex4 CLK_BUFG wire support CELL[13].IMUX_SPEC[2], CELL[13].IMUX_SPEC[3]
Bit
MAIN[13][1][60]

virtex4 CLK_BUFG wire support CELL[14].IMUX_SPEC[0], CELL[14].IMUX_SPEC[1]
Bit
MAIN[14][1][12]

virtex4 CLK_BUFG wire support CELL[14].IMUX_SPEC[2], CELL[14].IMUX_SPEC[3]
Bit
MAIN[14][1][28]

virtex4 CLK_BUFG wire support CELL[15].IMUX_SPEC[0], CELL[15].IMUX_SPEC[1]
Bit
MAIN[14][1][44]

virtex4 CLK_BUFG wire support CELL[15].IMUX_SPEC[2], CELL[15].IMUX_SPEC[3]
Bit
MAIN[14][1][60]

virtex4 CLK_BUFG wire support CELL_E0.MGT_ROW[0]
Bit
MAIN[1][0][17]

virtex4 CLK_BUFG wire support CELL_E0.MGT_ROW[1]
Bit
MAIN[1][0][16]

virtex4 CLK_BUFG wire support CELL_E8.MGT_ROW[0]
Bit
MAIN[14][0][62]

virtex4 CLK_BUFG wire support CELL_E8.MGT_ROW[1]
Bit
MAIN[14][0][63]

Bels BUFGCTRL

virtex4 CLK_BUFG bel BUFGCTRL pins
Pin	Direction	BUFGCTRL[0]	BUFGCTRL[1]	BUFGCTRL[2]	BUFGCTRL[3]	BUFGCTRL[4]	BUFGCTRL[5]	BUFGCTRL[6]	BUFGCTRL[7]	BUFGCTRL[8]	BUFGCTRL[9]	BUFGCTRL[10]	BUFGCTRL[11]	BUFGCTRL[12]	BUFGCTRL[13]	BUFGCTRL[14]	BUFGCTRL[15]	BUFGCTRL[16]	BUFGCTRL[17]	BUFGCTRL[18]	BUFGCTRL[19]	BUFGCTRL[20]	BUFGCTRL[21]	BUFGCTRL[22]	BUFGCTRL[23]	BUFGCTRL[24]	BUFGCTRL[25]	BUFGCTRL[26]	BUFGCTRL[27]	BUFGCTRL[28]	BUFGCTRL[29]	BUFGCTRL[30]	BUFGCTRL[31]
I0	in	CELL[0].IMUX_SPEC[1]	CELL[0].IMUX_SPEC[3]	CELL[1].IMUX_SPEC[1]	CELL[1].IMUX_SPEC[3]	CELL[2].IMUX_SPEC[1]	CELL[2].IMUX_SPEC[3]	CELL[3].IMUX_SPEC[1]	CELL[3].IMUX_SPEC[3]	CELL[4].IMUX_SPEC[1]	CELL[4].IMUX_SPEC[3]	CELL[5].IMUX_SPEC[1]	CELL[5].IMUX_SPEC[3]	CELL[6].IMUX_SPEC[1]	CELL[6].IMUX_SPEC[3]	CELL[7].IMUX_SPEC[1]	CELL[7].IMUX_SPEC[3]	CELL[15].IMUX_SPEC[3]	CELL[15].IMUX_SPEC[1]	CELL[14].IMUX_SPEC[3]	CELL[14].IMUX_SPEC[1]	CELL[13].IMUX_SPEC[3]	CELL[13].IMUX_SPEC[1]	CELL[12].IMUX_SPEC[3]	CELL[12].IMUX_SPEC[1]	CELL[11].IMUX_SPEC[3]	CELL[11].IMUX_SPEC[1]	CELL[10].IMUX_SPEC[3]	CELL[10].IMUX_SPEC[1]	CELL[9].IMUX_SPEC[3]	CELL[9].IMUX_SPEC[1]	CELL[8].IMUX_SPEC[3]	CELL[8].IMUX_SPEC[1]
I1	in	CELL[0].IMUX_SPEC[0]	CELL[0].IMUX_SPEC[2]	CELL[1].IMUX_SPEC[0]	CELL[1].IMUX_SPEC[2]	CELL[2].IMUX_SPEC[0]	CELL[2].IMUX_SPEC[2]	CELL[3].IMUX_SPEC[0]	CELL[3].IMUX_SPEC[2]	CELL[4].IMUX_SPEC[0]	CELL[4].IMUX_SPEC[2]	CELL[5].IMUX_SPEC[0]	CELL[5].IMUX_SPEC[2]	CELL[6].IMUX_SPEC[0]	CELL[6].IMUX_SPEC[2]	CELL[7].IMUX_SPEC[0]	CELL[7].IMUX_SPEC[2]	CELL[15].IMUX_SPEC[2]	CELL[15].IMUX_SPEC[0]	CELL[14].IMUX_SPEC[2]	CELL[14].IMUX_SPEC[0]	CELL[13].IMUX_SPEC[2]	CELL[13].IMUX_SPEC[0]	CELL[12].IMUX_SPEC[2]	CELL[12].IMUX_SPEC[0]	CELL[11].IMUX_SPEC[2]	CELL[11].IMUX_SPEC[0]	CELL[10].IMUX_SPEC[2]	CELL[10].IMUX_SPEC[0]	CELL[9].IMUX_SPEC[2]	CELL[9].IMUX_SPEC[0]	CELL[8].IMUX_SPEC[2]	CELL[8].IMUX_SPEC[0]
S0	in	CELL[1].IMUX_IMUX[0] invert by !MAIN[5][0][9]	CELL[1].IMUX_IMUX[4] invert by !MAIN[5][0][4]	CELL[1].IMUX_IMUX[16] invert by !MAIN[5][0][19]	CELL[1].IMUX_IMUX[20] invert by !MAIN[5][0][14]	CELL[2].IMUX_IMUX[0] invert by !MAIN[5][0][29]	CELL[2].IMUX_IMUX[4] invert by !MAIN[5][0][24]	CELL[2].IMUX_IMUX[16] invert by !MAIN[5][0][39]	CELL[2].IMUX_IMUX[20] invert by !MAIN[5][0][34]	CELL[3].IMUX_IMUX[0] invert by !MAIN[5][0][49]	CELL[3].IMUX_IMUX[4] invert by !MAIN[5][0][44]	CELL[3].IMUX_IMUX[16] invert by !MAIN[5][0][59]	CELL[3].IMUX_IMUX[20] invert by !MAIN[5][0][54]	CELL[4].IMUX_IMUX[0] invert by !MAIN[5][0][69]	CELL[4].IMUX_IMUX[4] invert by !MAIN[5][0][64]	CELL[4].IMUX_IMUX[16] invert by !MAIN[5][0][79]	CELL[4].IMUX_IMUX[20] invert by !MAIN[5][0][74]	CELL[14].IMUX_IMUX[20] invert by !MAIN[10][0][70]	CELL[14].IMUX_IMUX[16] invert by !MAIN[10][0][75]	CELL[14].IMUX_IMUX[4] invert by !MAIN[10][0][60]	CELL[14].IMUX_IMUX[0] invert by !MAIN[10][0][65]	CELL[13].IMUX_IMUX[20] invert by !MAIN[10][0][50]	CELL[13].IMUX_IMUX[16] invert by !MAIN[10][0][55]	CELL[13].IMUX_IMUX[4] invert by !MAIN[10][0][40]	CELL[13].IMUX_IMUX[0] invert by !MAIN[10][0][45]	CELL[12].IMUX_IMUX[20] invert by !MAIN[10][0][30]	CELL[12].IMUX_IMUX[16] invert by !MAIN[10][0][35]	CELL[12].IMUX_IMUX[4] invert by !MAIN[10][0][20]	CELL[12].IMUX_IMUX[0] invert by !MAIN[10][0][25]	CELL[11].IMUX_IMUX[20] invert by !MAIN[10][0][10]	CELL[11].IMUX_IMUX[16] invert by !MAIN[10][0][15]	CELL[11].IMUX_IMUX[4] invert by !MAIN[10][0][0]	CELL[11].IMUX_IMUX[0] invert by !MAIN[10][0][5]
S1	in	CELL[1].IMUX_IMUX[8] invert by !MAIN[5][0][5]	CELL[1].IMUX_IMUX[12] invert by !MAIN[5][0][0]	CELL[1].IMUX_IMUX[24] invert by !MAIN[5][0][15]	CELL[1].IMUX_IMUX[28] invert by !MAIN[5][0][10]	CELL[2].IMUX_IMUX[8] invert by !MAIN[5][0][25]	CELL[2].IMUX_IMUX[12] invert by !MAIN[5][0][20]	CELL[2].IMUX_IMUX[24] invert by !MAIN[5][0][35]	CELL[2].IMUX_IMUX[28] invert by !MAIN[5][0][30]	CELL[3].IMUX_IMUX[8] invert by !MAIN[5][0][45]	CELL[3].IMUX_IMUX[12] invert by !MAIN[5][0][40]	CELL[3].IMUX_IMUX[24] invert by !MAIN[5][0][55]	CELL[3].IMUX_IMUX[28] invert by !MAIN[5][0][50]	CELL[4].IMUX_IMUX[8] invert by !MAIN[5][0][65]	CELL[4].IMUX_IMUX[12] invert by !MAIN[5][0][60]	CELL[4].IMUX_IMUX[24] invert by !MAIN[5][0][75]	CELL[4].IMUX_IMUX[28] invert by !MAIN[5][0][70]	CELL[14].IMUX_IMUX[28] invert by !MAIN[10][0][74]	CELL[14].IMUX_IMUX[24] invert by !MAIN[10][0][79]	CELL[14].IMUX_IMUX[12] invert by !MAIN[10][0][64]	CELL[14].IMUX_IMUX[8] invert by !MAIN[10][0][69]	CELL[13].IMUX_IMUX[28] invert by !MAIN[10][0][54]	CELL[13].IMUX_IMUX[24] invert by !MAIN[10][0][59]	CELL[13].IMUX_IMUX[12] invert by !MAIN[10][0][44]	CELL[13].IMUX_IMUX[8] invert by !MAIN[10][0][49]	CELL[12].IMUX_IMUX[28] invert by !MAIN[10][0][34]	CELL[12].IMUX_IMUX[24] invert by !MAIN[10][0][39]	CELL[12].IMUX_IMUX[12] invert by !MAIN[10][0][24]	CELL[12].IMUX_IMUX[8] invert by !MAIN[10][0][29]	CELL[11].IMUX_IMUX[28] invert by !MAIN[10][0][14]	CELL[11].IMUX_IMUX[24] invert by !MAIN[10][0][19]	CELL[11].IMUX_IMUX[12] invert by !MAIN[10][0][4]	CELL[11].IMUX_IMUX[8] invert by !MAIN[10][0][9]
CE0	in	CELL[1].IMUX_IMUX[1] invert by !MAIN[5][1][9]	CELL[1].IMUX_IMUX[5] invert by !MAIN[5][1][4]	CELL[1].IMUX_IMUX[17] invert by !MAIN[5][1][19]	CELL[1].IMUX_IMUX[21] invert by !MAIN[5][1][14]	CELL[2].IMUX_IMUX[1] invert by !MAIN[5][1][29]	CELL[2].IMUX_IMUX[5] invert by !MAIN[5][1][24]	CELL[2].IMUX_IMUX[17] invert by !MAIN[5][1][39]	CELL[2].IMUX_IMUX[21] invert by !MAIN[5][1][34]	CELL[3].IMUX_IMUX[1] invert by !MAIN[5][1][49]	CELL[3].IMUX_IMUX[5] invert by !MAIN[5][1][44]	CELL[3].IMUX_IMUX[17] invert by !MAIN[5][1][59]	CELL[3].IMUX_IMUX[21] invert by !MAIN[5][1][54]	CELL[4].IMUX_IMUX[1] invert by !MAIN[5][1][69]	CELL[4].IMUX_IMUX[5] invert by !MAIN[5][1][64]	CELL[4].IMUX_IMUX[17] invert by !MAIN[5][1][79]	CELL[4].IMUX_IMUX[21] invert by !MAIN[5][1][74]	CELL[14].IMUX_IMUX[21] invert by !MAIN[10][1][70]	CELL[14].IMUX_IMUX[17] invert by !MAIN[10][1][75]	CELL[14].IMUX_IMUX[5] invert by !MAIN[10][1][60]	CELL[14].IMUX_IMUX[1] invert by !MAIN[10][1][65]	CELL[13].IMUX_IMUX[21] invert by !MAIN[10][1][50]	CELL[13].IMUX_IMUX[17] invert by !MAIN[10][1][55]	CELL[13].IMUX_IMUX[5] invert by !MAIN[10][1][40]	CELL[13].IMUX_IMUX[1] invert by !MAIN[10][1][45]	CELL[12].IMUX_IMUX[21] invert by !MAIN[10][1][30]	CELL[12].IMUX_IMUX[17] invert by !MAIN[10][1][35]	CELL[12].IMUX_IMUX[5] invert by !MAIN[10][1][20]	CELL[12].IMUX_IMUX[1] invert by !MAIN[10][1][25]	CELL[11].IMUX_IMUX[21] invert by !MAIN[10][1][10]	CELL[11].IMUX_IMUX[17] invert by !MAIN[10][1][15]	CELL[11].IMUX_IMUX[5] invert by !MAIN[10][1][0]	CELL[11].IMUX_IMUX[1] invert by !MAIN[10][1][5]
CE1	in	CELL[1].IMUX_IMUX[9] invert by !MAIN[5][1][5]	CELL[1].IMUX_IMUX[13] invert by !MAIN[5][1][0]	CELL[1].IMUX_IMUX[25] invert by !MAIN[5][1][15]	CELL[1].IMUX_IMUX[29] invert by !MAIN[5][1][10]	CELL[2].IMUX_IMUX[9] invert by !MAIN[5][1][25]	CELL[2].IMUX_IMUX[13] invert by !MAIN[5][1][20]	CELL[2].IMUX_IMUX[25] invert by !MAIN[5][1][35]	CELL[2].IMUX_IMUX[29] invert by !MAIN[5][1][30]	CELL[3].IMUX_IMUX[9] invert by !MAIN[5][1][45]	CELL[3].IMUX_IMUX[13] invert by !MAIN[5][1][40]	CELL[3].IMUX_IMUX[25] invert by !MAIN[5][1][55]	CELL[3].IMUX_IMUX[29] invert by !MAIN[5][1][50]	CELL[4].IMUX_IMUX[9] invert by !MAIN[5][1][65]	CELL[4].IMUX_IMUX[13] invert by !MAIN[5][1][60]	CELL[4].IMUX_IMUX[25] invert by !MAIN[5][1][75]	CELL[4].IMUX_IMUX[29] invert by !MAIN[5][1][70]	CELL[14].IMUX_IMUX[29] invert by !MAIN[10][1][74]	CELL[14].IMUX_IMUX[25] invert by !MAIN[10][1][79]	CELL[14].IMUX_IMUX[13] invert by !MAIN[10][1][64]	CELL[14].IMUX_IMUX[9] invert by !MAIN[10][1][69]	CELL[13].IMUX_IMUX[29] invert by !MAIN[10][1][54]	CELL[13].IMUX_IMUX[25] invert by !MAIN[10][1][59]	CELL[13].IMUX_IMUX[13] invert by !MAIN[10][1][44]	CELL[13].IMUX_IMUX[9] invert by !MAIN[10][1][49]	CELL[12].IMUX_IMUX[29] invert by !MAIN[10][1][34]	CELL[12].IMUX_IMUX[25] invert by !MAIN[10][1][39]	CELL[12].IMUX_IMUX[13] invert by !MAIN[10][1][24]	CELL[12].IMUX_IMUX[9] invert by !MAIN[10][1][29]	CELL[11].IMUX_IMUX[29] invert by !MAIN[10][1][14]	CELL[11].IMUX_IMUX[25] invert by !MAIN[10][1][19]	CELL[11].IMUX_IMUX[13] invert by !MAIN[10][1][4]	CELL[11].IMUX_IMUX[9] invert by !MAIN[10][1][9]
IGNORE0	in	CELL[1].IMUX_IMUX[2] invert by !MAIN[5][1][7]	CELL[1].IMUX_IMUX[6] invert by !MAIN[5][1][2]	CELL[1].IMUX_IMUX[18] invert by !MAIN[5][1][17]	CELL[1].IMUX_IMUX[22] invert by !MAIN[5][1][12]	CELL[2].IMUX_IMUX[2] invert by !MAIN[5][1][27]	CELL[2].IMUX_IMUX[6] invert by !MAIN[5][1][22]	CELL[2].IMUX_IMUX[18] invert by !MAIN[5][1][37]	CELL[2].IMUX_IMUX[22] invert by !MAIN[5][1][32]	CELL[3].IMUX_IMUX[2] invert by !MAIN[5][1][47]	CELL[3].IMUX_IMUX[6] invert by !MAIN[5][1][42]	CELL[3].IMUX_IMUX[18] invert by !MAIN[5][1][57]	CELL[3].IMUX_IMUX[22] invert by !MAIN[5][1][52]	CELL[4].IMUX_IMUX[2] invert by !MAIN[5][1][67]	CELL[4].IMUX_IMUX[6] invert by !MAIN[5][1][62]	CELL[4].IMUX_IMUX[18] invert by !MAIN[5][1][77]	CELL[4].IMUX_IMUX[22] invert by !MAIN[5][1][72]	CELL[14].IMUX_IMUX[22] invert by !MAIN[10][1][72]	CELL[14].IMUX_IMUX[18] invert by !MAIN[10][1][77]	CELL[14].IMUX_IMUX[6] invert by !MAIN[10][1][62]	CELL[14].IMUX_IMUX[2] invert by !MAIN[10][1][67]	CELL[13].IMUX_IMUX[22] invert by !MAIN[10][1][52]	CELL[13].IMUX_IMUX[18] invert by !MAIN[10][1][57]	CELL[13].IMUX_IMUX[6] invert by !MAIN[10][1][42]	CELL[13].IMUX_IMUX[2] invert by !MAIN[10][1][47]	CELL[12].IMUX_IMUX[22] invert by !MAIN[10][1][32]	CELL[12].IMUX_IMUX[18] invert by !MAIN[10][1][37]	CELL[12].IMUX_IMUX[6] invert by !MAIN[10][1][22]	CELL[12].IMUX_IMUX[2] invert by !MAIN[10][1][27]	CELL[11].IMUX_IMUX[22] invert by !MAIN[10][1][12]	CELL[11].IMUX_IMUX[18] invert by !MAIN[10][1][17]	CELL[11].IMUX_IMUX[6] invert by !MAIN[10][1][2]	CELL[11].IMUX_IMUX[2] invert by !MAIN[10][1][7]
IGNORE1	in	CELL[1].IMUX_IMUX[10] invert by !MAIN[5][0][7]	CELL[1].IMUX_IMUX[14] invert by !MAIN[5][0][2]	CELL[1].IMUX_IMUX[26] invert by !MAIN[5][0][17]	CELL[1].IMUX_IMUX[30] invert by !MAIN[5][0][12]	CELL[2].IMUX_IMUX[10] invert by !MAIN[5][0][27]	CELL[2].IMUX_IMUX[14] invert by !MAIN[5][0][22]	CELL[2].IMUX_IMUX[26] invert by !MAIN[5][0][37]	CELL[2].IMUX_IMUX[30] invert by !MAIN[5][0][32]	CELL[3].IMUX_IMUX[10] invert by !MAIN[5][0][47]	CELL[3].IMUX_IMUX[14] invert by !MAIN[5][0][42]	CELL[3].IMUX_IMUX[26] invert by !MAIN[5][0][57]	CELL[3].IMUX_IMUX[30] invert by !MAIN[5][0][52]	CELL[4].IMUX_IMUX[10] invert by !MAIN[5][0][67]	CELL[4].IMUX_IMUX[14] invert by !MAIN[5][0][62]	CELL[4].IMUX_IMUX[26] invert by !MAIN[5][0][77]	CELL[4].IMUX_IMUX[30] invert by !MAIN[5][0][72]	CELL[14].IMUX_IMUX[30] invert by !MAIN[10][0][72]	CELL[14].IMUX_IMUX[26] invert by !MAIN[10][0][77]	CELL[14].IMUX_IMUX[14] invert by !MAIN[10][0][62]	CELL[14].IMUX_IMUX[10] invert by !MAIN[10][0][67]	CELL[13].IMUX_IMUX[30] invert by !MAIN[10][0][52]	CELL[13].IMUX_IMUX[26] invert by !MAIN[10][0][57]	CELL[13].IMUX_IMUX[14] invert by !MAIN[10][0][42]	CELL[13].IMUX_IMUX[10] invert by !MAIN[10][0][47]	CELL[12].IMUX_IMUX[30] invert by !MAIN[10][0][32]	CELL[12].IMUX_IMUX[26] invert by !MAIN[10][0][37]	CELL[12].IMUX_IMUX[14] invert by !MAIN[10][0][22]	CELL[12].IMUX_IMUX[10] invert by !MAIN[10][0][27]	CELL[11].IMUX_IMUX[30] invert by !MAIN[10][0][12]	CELL[11].IMUX_IMUX[26] invert by !MAIN[10][0][17]	CELL[11].IMUX_IMUX[14] invert by !MAIN[10][0][2]	CELL[11].IMUX_IMUX[10] invert by !MAIN[10][0][7]
O	out	CELL[8].OUT_BUFG[0]	CELL[8].OUT_BUFG[1]	CELL[8].OUT_BUFG[2]	CELL[8].OUT_BUFG[3]	CELL[8].OUT_BUFG[4]	CELL[8].OUT_BUFG[5]	CELL[8].OUT_BUFG[6]	CELL[8].OUT_BUFG[7]	CELL[8].OUT_BUFG[8]	CELL[8].OUT_BUFG[9]	CELL[8].OUT_BUFG[10]	CELL[8].OUT_BUFG[11]	CELL[8].OUT_BUFG[12]	CELL[8].OUT_BUFG[13]	CELL[8].OUT_BUFG[14]	CELL[8].OUT_BUFG[15]	CELL[8].OUT_BUFG[16]	CELL[8].OUT_BUFG[17]	CELL[8].OUT_BUFG[18]	CELL[8].OUT_BUFG[19]	CELL[8].OUT_BUFG[20]	CELL[8].OUT_BUFG[21]	CELL[8].OUT_BUFG[22]	CELL[8].OUT_BUFG[23]	CELL[8].OUT_BUFG[24]	CELL[8].OUT_BUFG[25]	CELL[8].OUT_BUFG[26]	CELL[8].OUT_BUFG[27]	CELL[8].OUT_BUFG[28]	CELL[8].OUT_BUFG[29]	CELL[8].OUT_BUFG[30]	CELL[8].OUT_BUFG[31]

virtex4 CLK_BUFG bel BUFGCTRL attribute bits
Attribute	BUFGCTRL[0]	BUFGCTRL[1]	BUFGCTRL[2]	BUFGCTRL[3]	BUFGCTRL[4]	BUFGCTRL[5]	BUFGCTRL[6]	BUFGCTRL[7]	BUFGCTRL[8]	BUFGCTRL[9]	BUFGCTRL[10]	BUFGCTRL[11]	BUFGCTRL[12]	BUFGCTRL[13]	BUFGCTRL[14]	BUFGCTRL[15]	BUFGCTRL[16]	BUFGCTRL[17]	BUFGCTRL[18]	BUFGCTRL[19]	BUFGCTRL[20]	BUFGCTRL[21]	BUFGCTRL[22]	BUFGCTRL[23]	BUFGCTRL[24]	BUFGCTRL[25]	BUFGCTRL[26]	BUFGCTRL[27]	BUFGCTRL[28]	BUFGCTRL[29]	BUFGCTRL[30]	BUFGCTRL[31]
CREATE_EDGE	!MAIN[5][0][6]	!MAIN[5][0][1]	!MAIN[5][0][16]	!MAIN[5][0][11]	!MAIN[5][0][26]	!MAIN[5][0][21]	!MAIN[5][0][36]	!MAIN[5][0][31]	!MAIN[5][0][46]	!MAIN[5][0][41]	!MAIN[5][0][56]	!MAIN[5][0][51]	!MAIN[5][0][66]	!MAIN[5][0][61]	!MAIN[5][0][76]	!MAIN[5][0][71]	!MAIN[10][0][73]	!MAIN[10][0][78]	!MAIN[10][0][63]	!MAIN[10][0][68]	!MAIN[10][0][53]	!MAIN[10][0][58]	!MAIN[10][0][43]	!MAIN[10][0][48]	!MAIN[10][0][33]	!MAIN[10][0][38]	!MAIN[10][0][23]	!MAIN[10][0][28]	!MAIN[10][0][13]	!MAIN[10][0][18]	!MAIN[10][0][3]	!MAIN[10][0][8]
INIT_OUT bit 0	MAIN[5][0][8]	MAIN[5][0][3]	MAIN[5][0][18]	MAIN[5][0][13]	MAIN[5][0][28]	MAIN[5][0][23]	MAIN[5][0][38]	MAIN[5][0][33]	MAIN[5][0][48]	MAIN[5][0][43]	MAIN[5][0][58]	MAIN[5][0][53]	MAIN[5][0][68]	MAIN[5][0][63]	MAIN[5][0][78]	MAIN[5][0][73]	MAIN[10][0][71]	MAIN[10][0][76]	MAIN[10][0][61]	MAIN[10][0][66]	MAIN[10][0][51]	MAIN[10][0][56]	MAIN[10][0][41]	MAIN[10][0][46]	MAIN[10][0][31]	MAIN[10][0][36]	MAIN[10][0][21]	MAIN[10][0][26]	MAIN[10][0][11]	MAIN[10][0][16]	MAIN[10][0][1]	MAIN[10][0][6]
PRESELECT_I0	MAIN[5][1][8]	MAIN[5][1][3]	MAIN[5][1][18]	MAIN[5][1][13]	MAIN[5][1][28]	MAIN[5][1][23]	MAIN[5][1][38]	MAIN[5][1][33]	MAIN[5][1][48]	MAIN[5][1][43]	MAIN[5][1][58]	MAIN[5][1][53]	MAIN[5][1][68]	MAIN[5][1][63]	MAIN[5][1][78]	MAIN[5][1][73]	MAIN[10][1][71]	MAIN[10][1][76]	MAIN[10][1][61]	MAIN[10][1][66]	MAIN[10][1][51]	MAIN[10][1][56]	MAIN[10][1][41]	MAIN[10][1][46]	MAIN[10][1][31]	MAIN[10][1][36]	MAIN[10][1][21]	MAIN[10][1][26]	MAIN[10][1][11]	MAIN[10][1][16]	MAIN[10][1][1]	MAIN[10][1][6]
PRESELECT_I1	MAIN[5][1][6]	MAIN[5][1][1]	MAIN[5][1][16]	MAIN[5][1][11]	MAIN[5][1][26]	MAIN[5][1][21]	MAIN[5][1][36]	MAIN[5][1][31]	MAIN[5][1][46]	MAIN[5][1][41]	MAIN[5][1][56]	MAIN[5][1][51]	MAIN[5][1][66]	MAIN[5][1][61]	MAIN[5][1][76]	MAIN[5][1][71]	MAIN[10][1][73]	MAIN[10][1][78]	MAIN[10][1][63]	MAIN[10][1][68]	MAIN[10][1][53]	MAIN[10][1][58]	MAIN[10][1][43]	MAIN[10][1][48]	MAIN[10][1][33]	MAIN[10][1][38]	MAIN[10][1][23]	MAIN[10][1][28]	MAIN[10][1][13]	MAIN[10][1][18]	MAIN[10][1][3]	MAIN[10][1][8]

Bel wires

virtex4 CLK_BUFG bel wires
Wire	Pins
CELL[0].IMUX_SPEC[0]	BUFGCTRL[0].I1
CELL[0].IMUX_SPEC[1]	BUFGCTRL[0].I0
CELL[0].IMUX_SPEC[2]	BUFGCTRL[1].I1
CELL[0].IMUX_SPEC[3]	BUFGCTRL[1].I0
CELL[1].IMUX_IMUX[0]	BUFGCTRL[0].S0
CELL[1].IMUX_IMUX[1]	BUFGCTRL[0].CE0
CELL[1].IMUX_IMUX[2]	BUFGCTRL[0].IGNORE0
CELL[1].IMUX_IMUX[4]	BUFGCTRL[1].S0
CELL[1].IMUX_IMUX[5]	BUFGCTRL[1].CE0
CELL[1].IMUX_IMUX[6]	BUFGCTRL[1].IGNORE0
CELL[1].IMUX_IMUX[8]	BUFGCTRL[0].S1
CELL[1].IMUX_IMUX[9]	BUFGCTRL[0].CE1
CELL[1].IMUX_IMUX[10]	BUFGCTRL[0].IGNORE1
CELL[1].IMUX_IMUX[12]	BUFGCTRL[1].S1
CELL[1].IMUX_IMUX[13]	BUFGCTRL[1].CE1
CELL[1].IMUX_IMUX[14]	BUFGCTRL[1].IGNORE1
CELL[1].IMUX_IMUX[16]	BUFGCTRL[2].S0
CELL[1].IMUX_IMUX[17]	BUFGCTRL[2].CE0
CELL[1].IMUX_IMUX[18]	BUFGCTRL[2].IGNORE0
CELL[1].IMUX_IMUX[20]	BUFGCTRL[3].S0
CELL[1].IMUX_IMUX[21]	BUFGCTRL[3].CE0
CELL[1].IMUX_IMUX[22]	BUFGCTRL[3].IGNORE0
CELL[1].IMUX_IMUX[24]	BUFGCTRL[2].S1
CELL[1].IMUX_IMUX[25]	BUFGCTRL[2].CE1
CELL[1].IMUX_IMUX[26]	BUFGCTRL[2].IGNORE1
CELL[1].IMUX_IMUX[28]	BUFGCTRL[3].S1
CELL[1].IMUX_IMUX[29]	BUFGCTRL[3].CE1
CELL[1].IMUX_IMUX[30]	BUFGCTRL[3].IGNORE1
CELL[1].IMUX_SPEC[0]	BUFGCTRL[2].I1
CELL[1].IMUX_SPEC[1]	BUFGCTRL[2].I0
CELL[1].IMUX_SPEC[2]	BUFGCTRL[3].I1
CELL[1].IMUX_SPEC[3]	BUFGCTRL[3].I0
CELL[2].IMUX_IMUX[0]	BUFGCTRL[4].S0
CELL[2].IMUX_IMUX[1]	BUFGCTRL[4].CE0
CELL[2].IMUX_IMUX[2]	BUFGCTRL[4].IGNORE0
CELL[2].IMUX_IMUX[4]	BUFGCTRL[5].S0
CELL[2].IMUX_IMUX[5]	BUFGCTRL[5].CE0
CELL[2].IMUX_IMUX[6]	BUFGCTRL[5].IGNORE0
CELL[2].IMUX_IMUX[8]	BUFGCTRL[4].S1
CELL[2].IMUX_IMUX[9]	BUFGCTRL[4].CE1
CELL[2].IMUX_IMUX[10]	BUFGCTRL[4].IGNORE1
CELL[2].IMUX_IMUX[12]	BUFGCTRL[5].S1
CELL[2].IMUX_IMUX[13]	BUFGCTRL[5].CE1
CELL[2].IMUX_IMUX[14]	BUFGCTRL[5].IGNORE1
CELL[2].IMUX_IMUX[16]	BUFGCTRL[6].S0
CELL[2].IMUX_IMUX[17]	BUFGCTRL[6].CE0
CELL[2].IMUX_IMUX[18]	BUFGCTRL[6].IGNORE0
CELL[2].IMUX_IMUX[20]	BUFGCTRL[7].S0
CELL[2].IMUX_IMUX[21]	BUFGCTRL[7].CE0
CELL[2].IMUX_IMUX[22]	BUFGCTRL[7].IGNORE0
CELL[2].IMUX_IMUX[24]	BUFGCTRL[6].S1
CELL[2].IMUX_IMUX[25]	BUFGCTRL[6].CE1
CELL[2].IMUX_IMUX[26]	BUFGCTRL[6].IGNORE1
CELL[2].IMUX_IMUX[28]	BUFGCTRL[7].S1
CELL[2].IMUX_IMUX[29]	BUFGCTRL[7].CE1
CELL[2].IMUX_IMUX[30]	BUFGCTRL[7].IGNORE1
CELL[2].IMUX_SPEC[0]	BUFGCTRL[4].I1
CELL[2].IMUX_SPEC[1]	BUFGCTRL[4].I0
CELL[2].IMUX_SPEC[2]	BUFGCTRL[5].I1
CELL[2].IMUX_SPEC[3]	BUFGCTRL[5].I0
CELL[3].IMUX_IMUX[0]	BUFGCTRL[8].S0
CELL[3].IMUX_IMUX[1]	BUFGCTRL[8].CE0
CELL[3].IMUX_IMUX[2]	BUFGCTRL[8].IGNORE0
CELL[3].IMUX_IMUX[4]	BUFGCTRL[9].S0
CELL[3].IMUX_IMUX[5]	BUFGCTRL[9].CE0
CELL[3].IMUX_IMUX[6]	BUFGCTRL[9].IGNORE0
CELL[3].IMUX_IMUX[8]	BUFGCTRL[8].S1
CELL[3].IMUX_IMUX[9]	BUFGCTRL[8].CE1
CELL[3].IMUX_IMUX[10]	BUFGCTRL[8].IGNORE1
CELL[3].IMUX_IMUX[12]	BUFGCTRL[9].S1
CELL[3].IMUX_IMUX[13]	BUFGCTRL[9].CE1
CELL[3].IMUX_IMUX[14]	BUFGCTRL[9].IGNORE1
CELL[3].IMUX_IMUX[16]	BUFGCTRL[10].S0
CELL[3].IMUX_IMUX[17]	BUFGCTRL[10].CE0
CELL[3].IMUX_IMUX[18]	BUFGCTRL[10].IGNORE0
CELL[3].IMUX_IMUX[20]	BUFGCTRL[11].S0
CELL[3].IMUX_IMUX[21]	BUFGCTRL[11].CE0
CELL[3].IMUX_IMUX[22]	BUFGCTRL[11].IGNORE0
CELL[3].IMUX_IMUX[24]	BUFGCTRL[10].S1
CELL[3].IMUX_IMUX[25]	BUFGCTRL[10].CE1
CELL[3].IMUX_IMUX[26]	BUFGCTRL[10].IGNORE1
CELL[3].IMUX_IMUX[28]	BUFGCTRL[11].S1
CELL[3].IMUX_IMUX[29]	BUFGCTRL[11].CE1
CELL[3].IMUX_IMUX[30]	BUFGCTRL[11].IGNORE1
CELL[3].IMUX_SPEC[0]	BUFGCTRL[6].I1
CELL[3].IMUX_SPEC[1]	BUFGCTRL[6].I0
CELL[3].IMUX_SPEC[2]	BUFGCTRL[7].I1
CELL[3].IMUX_SPEC[3]	BUFGCTRL[7].I0
CELL[4].IMUX_IMUX[0]	BUFGCTRL[12].S0
CELL[4].IMUX_IMUX[1]	BUFGCTRL[12].CE0
CELL[4].IMUX_IMUX[2]	BUFGCTRL[12].IGNORE0
CELL[4].IMUX_IMUX[4]	BUFGCTRL[13].S0
CELL[4].IMUX_IMUX[5]	BUFGCTRL[13].CE0
CELL[4].IMUX_IMUX[6]	BUFGCTRL[13].IGNORE0
CELL[4].IMUX_IMUX[8]	BUFGCTRL[12].S1
CELL[4].IMUX_IMUX[9]	BUFGCTRL[12].CE1
CELL[4].IMUX_IMUX[10]	BUFGCTRL[12].IGNORE1
CELL[4].IMUX_IMUX[12]	BUFGCTRL[13].S1
CELL[4].IMUX_IMUX[13]	BUFGCTRL[13].CE1
CELL[4].IMUX_IMUX[14]	BUFGCTRL[13].IGNORE1
CELL[4].IMUX_IMUX[16]	BUFGCTRL[14].S0
CELL[4].IMUX_IMUX[17]	BUFGCTRL[14].CE0
CELL[4].IMUX_IMUX[18]	BUFGCTRL[14].IGNORE0
CELL[4].IMUX_IMUX[20]	BUFGCTRL[15].S0
CELL[4].IMUX_IMUX[21]	BUFGCTRL[15].CE0
CELL[4].IMUX_IMUX[22]	BUFGCTRL[15].IGNORE0
CELL[4].IMUX_IMUX[24]	BUFGCTRL[14].S1
CELL[4].IMUX_IMUX[25]	BUFGCTRL[14].CE1
CELL[4].IMUX_IMUX[26]	BUFGCTRL[14].IGNORE1
CELL[4].IMUX_IMUX[28]	BUFGCTRL[15].S1
CELL[4].IMUX_IMUX[29]	BUFGCTRL[15].CE1
CELL[4].IMUX_IMUX[30]	BUFGCTRL[15].IGNORE1
CELL[4].IMUX_SPEC[0]	BUFGCTRL[8].I1
CELL[4].IMUX_SPEC[1]	BUFGCTRL[8].I0
CELL[4].IMUX_SPEC[2]	BUFGCTRL[9].I1
CELL[4].IMUX_SPEC[3]	BUFGCTRL[9].I0
CELL[5].IMUX_SPEC[0]	BUFGCTRL[10].I1
CELL[5].IMUX_SPEC[1]	BUFGCTRL[10].I0
CELL[5].IMUX_SPEC[2]	BUFGCTRL[11].I1
CELL[5].IMUX_SPEC[3]	BUFGCTRL[11].I0
CELL[6].IMUX_SPEC[0]	BUFGCTRL[12].I1
CELL[6].IMUX_SPEC[1]	BUFGCTRL[12].I0
CELL[6].IMUX_SPEC[2]	BUFGCTRL[13].I1
CELL[6].IMUX_SPEC[3]	BUFGCTRL[13].I0
CELL[7].IMUX_SPEC[0]	BUFGCTRL[14].I1
CELL[7].IMUX_SPEC[1]	BUFGCTRL[14].I0
CELL[7].IMUX_SPEC[2]	BUFGCTRL[15].I1
CELL[7].IMUX_SPEC[3]	BUFGCTRL[15].I0
CELL[8].IMUX_SPEC[0]	BUFGCTRL[31].I1
CELL[8].IMUX_SPEC[1]	BUFGCTRL[31].I0
CELL[8].IMUX_SPEC[2]	BUFGCTRL[30].I1
CELL[8].IMUX_SPEC[3]	BUFGCTRL[30].I0
CELL[8].OUT_BUFG[0]	BUFGCTRL[0].O
CELL[8].OUT_BUFG[1]	BUFGCTRL[1].O
CELL[8].OUT_BUFG[2]	BUFGCTRL[2].O
CELL[8].OUT_BUFG[3]	BUFGCTRL[3].O
CELL[8].OUT_BUFG[4]	BUFGCTRL[4].O
CELL[8].OUT_BUFG[5]	BUFGCTRL[5].O
CELL[8].OUT_BUFG[6]	BUFGCTRL[6].O
CELL[8].OUT_BUFG[7]	BUFGCTRL[7].O
CELL[8].OUT_BUFG[8]	BUFGCTRL[8].O
CELL[8].OUT_BUFG[9]	BUFGCTRL[9].O
CELL[8].OUT_BUFG[10]	BUFGCTRL[10].O
CELL[8].OUT_BUFG[11]	BUFGCTRL[11].O
CELL[8].OUT_BUFG[12]	BUFGCTRL[12].O
CELL[8].OUT_BUFG[13]	BUFGCTRL[13].O
CELL[8].OUT_BUFG[14]	BUFGCTRL[14].O
CELL[8].OUT_BUFG[15]	BUFGCTRL[15].O
CELL[8].OUT_BUFG[16]	BUFGCTRL[16].O
CELL[8].OUT_BUFG[17]	BUFGCTRL[17].O
CELL[8].OUT_BUFG[18]	BUFGCTRL[18].O
CELL[8].OUT_BUFG[19]	BUFGCTRL[19].O
CELL[8].OUT_BUFG[20]	BUFGCTRL[20].O
CELL[8].OUT_BUFG[21]	BUFGCTRL[21].O
CELL[8].OUT_BUFG[22]	BUFGCTRL[22].O
CELL[8].OUT_BUFG[23]	BUFGCTRL[23].O
CELL[8].OUT_BUFG[24]	BUFGCTRL[24].O
CELL[8].OUT_BUFG[25]	BUFGCTRL[25].O
CELL[8].OUT_BUFG[26]	BUFGCTRL[26].O
CELL[8].OUT_BUFG[27]	BUFGCTRL[27].O
CELL[8].OUT_BUFG[28]	BUFGCTRL[28].O
CELL[8].OUT_BUFG[29]	BUFGCTRL[29].O
CELL[8].OUT_BUFG[30]	BUFGCTRL[30].O
CELL[8].OUT_BUFG[31]	BUFGCTRL[31].O
CELL[9].IMUX_SPEC[0]	BUFGCTRL[29].I1
CELL[9].IMUX_SPEC[1]	BUFGCTRL[29].I0
CELL[9].IMUX_SPEC[2]	BUFGCTRL[28].I1
CELL[9].IMUX_SPEC[3]	BUFGCTRL[28].I0
CELL[10].IMUX_SPEC[0]	BUFGCTRL[27].I1
CELL[10].IMUX_SPEC[1]	BUFGCTRL[27].I0
CELL[10].IMUX_SPEC[2]	BUFGCTRL[26].I1
CELL[10].IMUX_SPEC[3]	BUFGCTRL[26].I0
CELL[11].IMUX_IMUX[0]	BUFGCTRL[31].S0
CELL[11].IMUX_IMUX[1]	BUFGCTRL[31].CE0
CELL[11].IMUX_IMUX[2]	BUFGCTRL[31].IGNORE0
CELL[11].IMUX_IMUX[4]	BUFGCTRL[30].S0
CELL[11].IMUX_IMUX[5]	BUFGCTRL[30].CE0
CELL[11].IMUX_IMUX[6]	BUFGCTRL[30].IGNORE0
CELL[11].IMUX_IMUX[8]	BUFGCTRL[31].S1
CELL[11].IMUX_IMUX[9]	BUFGCTRL[31].CE1
CELL[11].IMUX_IMUX[10]	BUFGCTRL[31].IGNORE1
CELL[11].IMUX_IMUX[12]	BUFGCTRL[30].S1
CELL[11].IMUX_IMUX[13]	BUFGCTRL[30].CE1
CELL[11].IMUX_IMUX[14]	BUFGCTRL[30].IGNORE1
CELL[11].IMUX_IMUX[16]	BUFGCTRL[29].S0
CELL[11].IMUX_IMUX[17]	BUFGCTRL[29].CE0
CELL[11].IMUX_IMUX[18]	BUFGCTRL[29].IGNORE0
CELL[11].IMUX_IMUX[20]	BUFGCTRL[28].S0
CELL[11].IMUX_IMUX[21]	BUFGCTRL[28].CE0
CELL[11].IMUX_IMUX[22]	BUFGCTRL[28].IGNORE0
CELL[11].IMUX_IMUX[24]	BUFGCTRL[29].S1
CELL[11].IMUX_IMUX[25]	BUFGCTRL[29].CE1
CELL[11].IMUX_IMUX[26]	BUFGCTRL[29].IGNORE1
CELL[11].IMUX_IMUX[28]	BUFGCTRL[28].S1
CELL[11].IMUX_IMUX[29]	BUFGCTRL[28].CE1
CELL[11].IMUX_IMUX[30]	BUFGCTRL[28].IGNORE1
CELL[11].IMUX_SPEC[0]	BUFGCTRL[25].I1
CELL[11].IMUX_SPEC[1]	BUFGCTRL[25].I0
CELL[11].IMUX_SPEC[2]	BUFGCTRL[24].I1
CELL[11].IMUX_SPEC[3]	BUFGCTRL[24].I0
CELL[12].IMUX_IMUX[0]	BUFGCTRL[27].S0
CELL[12].IMUX_IMUX[1]	BUFGCTRL[27].CE0
CELL[12].IMUX_IMUX[2]	BUFGCTRL[27].IGNORE0
CELL[12].IMUX_IMUX[4]	BUFGCTRL[26].S0
CELL[12].IMUX_IMUX[5]	BUFGCTRL[26].CE0
CELL[12].IMUX_IMUX[6]	BUFGCTRL[26].IGNORE0
CELL[12].IMUX_IMUX[8]	BUFGCTRL[27].S1
CELL[12].IMUX_IMUX[9]	BUFGCTRL[27].CE1
CELL[12].IMUX_IMUX[10]	BUFGCTRL[27].IGNORE1
CELL[12].IMUX_IMUX[12]	BUFGCTRL[26].S1
CELL[12].IMUX_IMUX[13]	BUFGCTRL[26].CE1
CELL[12].IMUX_IMUX[14]	BUFGCTRL[26].IGNORE1
CELL[12].IMUX_IMUX[16]	BUFGCTRL[25].S0
CELL[12].IMUX_IMUX[17]	BUFGCTRL[25].CE0
CELL[12].IMUX_IMUX[18]	BUFGCTRL[25].IGNORE0
CELL[12].IMUX_IMUX[20]	BUFGCTRL[24].S0
CELL[12].IMUX_IMUX[21]	BUFGCTRL[24].CE0
CELL[12].IMUX_IMUX[22]	BUFGCTRL[24].IGNORE0
CELL[12].IMUX_IMUX[24]	BUFGCTRL[25].S1
CELL[12].IMUX_IMUX[25]	BUFGCTRL[25].CE1
CELL[12].IMUX_IMUX[26]	BUFGCTRL[25].IGNORE1
CELL[12].IMUX_IMUX[28]	BUFGCTRL[24].S1
CELL[12].IMUX_IMUX[29]	BUFGCTRL[24].CE1
CELL[12].IMUX_IMUX[30]	BUFGCTRL[24].IGNORE1
CELL[12].IMUX_SPEC[0]	BUFGCTRL[23].I1
CELL[12].IMUX_SPEC[1]	BUFGCTRL[23].I0
CELL[12].IMUX_SPEC[2]	BUFGCTRL[22].I1
CELL[12].IMUX_SPEC[3]	BUFGCTRL[22].I0
CELL[13].IMUX_IMUX[0]	BUFGCTRL[23].S0
CELL[13].IMUX_IMUX[1]	BUFGCTRL[23].CE0
CELL[13].IMUX_IMUX[2]	BUFGCTRL[23].IGNORE0
CELL[13].IMUX_IMUX[4]	BUFGCTRL[22].S0
CELL[13].IMUX_IMUX[5]	BUFGCTRL[22].CE0
CELL[13].IMUX_IMUX[6]	BUFGCTRL[22].IGNORE0
CELL[13].IMUX_IMUX[8]	BUFGCTRL[23].S1
CELL[13].IMUX_IMUX[9]	BUFGCTRL[23].CE1
CELL[13].IMUX_IMUX[10]	BUFGCTRL[23].IGNORE1
CELL[13].IMUX_IMUX[12]	BUFGCTRL[22].S1
CELL[13].IMUX_IMUX[13]	BUFGCTRL[22].CE1
CELL[13].IMUX_IMUX[14]	BUFGCTRL[22].IGNORE1
CELL[13].IMUX_IMUX[16]	BUFGCTRL[21].S0
CELL[13].IMUX_IMUX[17]	BUFGCTRL[21].CE0
CELL[13].IMUX_IMUX[18]	BUFGCTRL[21].IGNORE0
CELL[13].IMUX_IMUX[20]	BUFGCTRL[20].S0
CELL[13].IMUX_IMUX[21]	BUFGCTRL[20].CE0
CELL[13].IMUX_IMUX[22]	BUFGCTRL[20].IGNORE0
CELL[13].IMUX_IMUX[24]	BUFGCTRL[21].S1
CELL[13].IMUX_IMUX[25]	BUFGCTRL[21].CE1
CELL[13].IMUX_IMUX[26]	BUFGCTRL[21].IGNORE1
CELL[13].IMUX_IMUX[28]	BUFGCTRL[20].S1
CELL[13].IMUX_IMUX[29]	BUFGCTRL[20].CE1
CELL[13].IMUX_IMUX[30]	BUFGCTRL[20].IGNORE1
CELL[13].IMUX_SPEC[0]	BUFGCTRL[21].I1
CELL[13].IMUX_SPEC[1]	BUFGCTRL[21].I0
CELL[13].IMUX_SPEC[2]	BUFGCTRL[20].I1
CELL[13].IMUX_SPEC[3]	BUFGCTRL[20].I0
CELL[14].IMUX_IMUX[0]	BUFGCTRL[19].S0
CELL[14].IMUX_IMUX[1]	BUFGCTRL[19].CE0
CELL[14].IMUX_IMUX[2]	BUFGCTRL[19].IGNORE0
CELL[14].IMUX_IMUX[4]	BUFGCTRL[18].S0
CELL[14].IMUX_IMUX[5]	BUFGCTRL[18].CE0
CELL[14].IMUX_IMUX[6]	BUFGCTRL[18].IGNORE0
CELL[14].IMUX_IMUX[8]	BUFGCTRL[19].S1
CELL[14].IMUX_IMUX[9]	BUFGCTRL[19].CE1
CELL[14].IMUX_IMUX[10]	BUFGCTRL[19].IGNORE1
CELL[14].IMUX_IMUX[12]	BUFGCTRL[18].S1
CELL[14].IMUX_IMUX[13]	BUFGCTRL[18].CE1
CELL[14].IMUX_IMUX[14]	BUFGCTRL[18].IGNORE1
CELL[14].IMUX_IMUX[16]	BUFGCTRL[17].S0
CELL[14].IMUX_IMUX[17]	BUFGCTRL[17].CE0
CELL[14].IMUX_IMUX[18]	BUFGCTRL[17].IGNORE0
CELL[14].IMUX_IMUX[20]	BUFGCTRL[16].S0
CELL[14].IMUX_IMUX[21]	BUFGCTRL[16].CE0
CELL[14].IMUX_IMUX[22]	BUFGCTRL[16].IGNORE0
CELL[14].IMUX_IMUX[24]	BUFGCTRL[17].S1
CELL[14].IMUX_IMUX[25]	BUFGCTRL[17].CE1
CELL[14].IMUX_IMUX[26]	BUFGCTRL[17].IGNORE1
CELL[14].IMUX_IMUX[28]	BUFGCTRL[16].S1
CELL[14].IMUX_IMUX[29]	BUFGCTRL[16].CE1
CELL[14].IMUX_IMUX[30]	BUFGCTRL[16].IGNORE1
CELL[14].IMUX_SPEC[0]	BUFGCTRL[19].I1
CELL[14].IMUX_SPEC[1]	BUFGCTRL[19].I0
CELL[14].IMUX_SPEC[2]	BUFGCTRL[18].I1
CELL[14].IMUX_SPEC[3]	BUFGCTRL[18].I0
CELL[15].IMUX_SPEC[0]	BUFGCTRL[17].I1
CELL[15].IMUX_SPEC[1]	BUFGCTRL[17].I0
CELL[15].IMUX_SPEC[2]	BUFGCTRL[16].I1
CELL[15].IMUX_SPEC[3]	BUFGCTRL[16].I0

Bitstream

virtex4 CLK_BUFG rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 2	-
B78	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 8	-
B77	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 10	-
B76	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 11	-
B75	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 7	-
B74	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 9	-
B73	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 3	-
B72	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 4	-
B71	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 5	-
B70	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 6	-
B69	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 0	-
B68	SPEC_INT: mux CELL[1].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[1].IMUX_SPEC[2] bit 1	-
B67	-	SPEC_INT: wire support (CELL[1].IMUX_SPEC[2], CELL[1].IMUX_SPEC[3]) bit 0	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 2	-
B62	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 8	-
B61	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 10	-
B60	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 11	-
B59	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 7	-
B58	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 9	-
B57	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 3	-
B56	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 4	-
B55	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 5	-
B54	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 6	-
B53	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 0	-
B52	SPEC_INT: mux CELL[1].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[1].IMUX_SPEC[0] bit 1	-
B51	-	SPEC_INT: wire support (CELL[1].IMUX_SPEC[0], CELL[1].IMUX_SPEC[1]) bit 0	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 2	-
B46	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 8	-
B45	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 10	-
B44	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 11	-
B43	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 7	-
B42	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 9	-
B41	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 3	-
B40	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 4	-
B39	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 5	-
B38	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 6	-
B37	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 0	-
B36	SPEC_INT: mux CELL[0].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[0].IMUX_SPEC[2] bit 1	-
B35	-	SPEC_INT: wire support (CELL[0].IMUX_SPEC[2], CELL[0].IMUX_SPEC[3]) bit 0	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 2	-
B30	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 8	-
B29	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 10	-
B28	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 11	-
B27	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 7	-
B26	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 9	-
B25	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 3	-
B24	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 4	-
B23	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 5	-
B22	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 6	-
B21	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 0	-
B20	SPEC_INT: mux CELL[0].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[0].IMUX_SPEC[0] bit 1	-
B19	-	SPEC_INT: wire support (CELL[0].IMUX_SPEC[0], CELL[0].IMUX_SPEC[1]) bit 0	-
B18	-	-	-
B17	SPEC_INT: wire support (CELL_E0.MGT_ROW[0]) bit 0	-	-
B16	SPEC_INT: wire support (CELL_E0.MGT_ROW[1]) bit 0	-	-
B15	SPEC_INT: wire support (CELL[0].MGT_ROW[0]) bit 0	-	-
B14	SPEC_INT: wire support (CELL[0].MGT_ROW[1]) bit 0	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2
B79	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 2	-
B78	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 8	-
B77	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 10	-
B76	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 11	-
B75	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 7	-
B74	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 9	-
B73	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 3	-
B72	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 4	-
B71	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 5	-
B70	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 6	-
B69	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 0	-
B68	SPEC_INT: mux CELL[3].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[3].IMUX_SPEC[2] bit 1	-
B67	-	SPEC_INT: wire support (CELL[3].IMUX_SPEC[2], CELL[3].IMUX_SPEC[3]) bit 0	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 2	-
B62	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 8	-
B61	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 10	-
B60	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 11	-
B59	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 7	-
B58	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 9	-
B57	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 3	-
B56	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 4	-
B55	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 5	-
B54	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 6	-
B53	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 0	-
B52	SPEC_INT: mux CELL[3].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[3].IMUX_SPEC[0] bit 1	-
B51	-	SPEC_INT: wire support (CELL[3].IMUX_SPEC[0], CELL[3].IMUX_SPEC[1]) bit 0	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 2	-
B46	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 8	-
B45	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 10	-
B44	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 11	-
B43	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 7	-
B42	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 9	-
B41	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 3	-
B40	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 4	-
B39	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 5	-
B38	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 6	-
B37	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 0	-
B36	SPEC_INT: mux CELL[2].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[2].IMUX_SPEC[2] bit 1	-
B35	-	SPEC_INT: wire support (CELL[2].IMUX_SPEC[2], CELL[2].IMUX_SPEC[3]) bit 0	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 2	-
B30	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 8	-
B29	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 10	-
B28	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 11	-
B27	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 7	-
B26	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 9	-
B25	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 3	-
B24	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 4	-
B23	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 5	-
B22	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 6	-
B21	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 0	-
B20	SPEC_INT: mux CELL[2].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[2].IMUX_SPEC[0] bit 1	-
B19	-	SPEC_INT: wire support (CELL[2].IMUX_SPEC[0], CELL[2].IMUX_SPEC[1]) bit 0	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2
B79	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 2	-
B78	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 8	-
B77	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 10	-
B76	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 11	-
B75	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 7	-
B74	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 9	-
B73	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 3	-
B72	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 4	-
B71	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 5	-
B70	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 6	-
B69	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 0	-
B68	SPEC_INT: mux CELL[5].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[5].IMUX_SPEC[2] bit 1	-
B67	-	SPEC_INT: wire support (CELL[5].IMUX_SPEC[2], CELL[5].IMUX_SPEC[3]) bit 0	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 2	-
B62	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 8	-
B61	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 10	-
B60	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 11	-
B59	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 7	-
B58	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 9	-
B57	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 3	-
B56	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 4	-
B55	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 5	-
B54	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 6	-
B53	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 0	-
B52	SPEC_INT: mux CELL[5].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[5].IMUX_SPEC[0] bit 1	-
B51	-	SPEC_INT: wire support (CELL[5].IMUX_SPEC[0], CELL[5].IMUX_SPEC[1]) bit 0	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 2	-
B46	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 8	-
B45	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 10	-
B44	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 11	-
B43	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 7	-
B42	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 9	-
B41	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 3	-
B40	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 4	-
B39	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 5	-
B38	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 6	-
B37	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 0	-
B36	SPEC_INT: mux CELL[4].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[4].IMUX_SPEC[2] bit 1	-
B35	-	SPEC_INT: wire support (CELL[4].IMUX_SPEC[2], CELL[4].IMUX_SPEC[3]) bit 0	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 2	-
B30	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 8	-
B29	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 10	-
B28	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 11	-
B27	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 7	-
B26	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 9	-
B25	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 3	-
B24	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 4	-
B23	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 5	-
B22	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 6	-
B21	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 0	-
B20	SPEC_INT: mux CELL[4].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[4].IMUX_SPEC[0] bit 1	-
B19	-	SPEC_INT: wire support (CELL[4].IMUX_SPEC[0], CELL[4].IMUX_SPEC[1]) bit 0	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2
B79	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 2	-
B78	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 8	-
B77	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 10	-
B76	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 11	-
B75	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 7	-
B74	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 9	-
B73	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 3	-
B72	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 4	-
B71	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 5	-
B70	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 6	-
B69	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 0	-
B68	SPEC_INT: mux CELL[7].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[7].IMUX_SPEC[2] bit 1	-
B67	-	SPEC_INT: wire support (CELL[7].IMUX_SPEC[2], CELL[7].IMUX_SPEC[3]) bit 0	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 2	-
B62	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 8	-
B61	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 10	-
B60	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 11	-
B59	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 7	-
B58	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 9	-
B57	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 3	-
B56	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 4	-
B55	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 5	-
B54	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 6	-
B53	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 0	-
B52	SPEC_INT: mux CELL[7].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[7].IMUX_SPEC[0] bit 1	-
B51	-	SPEC_INT: wire support (CELL[7].IMUX_SPEC[0], CELL[7].IMUX_SPEC[1]) bit 0	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 2	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 2	-
B46	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 8	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 8	-
B45	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 10	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 10	-
B44	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 11	-
B43	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 7	-
B42	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 9	-
B41	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 3	-
B40	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 4	-
B39	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 5	-
B38	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 6	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 6	-
B37	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 0	-
B36	SPEC_INT: mux CELL[6].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[6].IMUX_SPEC[2] bit 1	-
B35	-	SPEC_INT: wire support (CELL[6].IMUX_SPEC[2], CELL[6].IMUX_SPEC[3]) bit 0	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 2	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 2	-
B30	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 8	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 8	-
B29	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 10	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 10	-
B28	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 11	-
B27	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 7	-
B26	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 9	-
B25	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 3	-
B24	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 4	-
B23	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 5	-
B22	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 6	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 6	-
B21	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 0	-
B20	SPEC_INT: mux CELL[6].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[6].IMUX_SPEC[0] bit 1	-
B19	-	SPEC_INT: wire support (CELL[6].IMUX_SPEC[0], CELL[6].IMUX_SPEC[1]) bit 0	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2
B79	BUFGCTRL[14]: !invert S0	BUFGCTRL[14]: !invert CE0	-
B78	BUFGCTRL[14]: INIT_OUT bit 0	BUFGCTRL[14]: PRESELECT_I0	-
B77	BUFGCTRL[14]: !invert IGNORE1	BUFGCTRL[14]: !invert IGNORE0	-
B76	BUFGCTRL[14]: ! CREATE_EDGE	BUFGCTRL[14]: PRESELECT_I1	-
B75	BUFGCTRL[14]: !invert S1	BUFGCTRL[14]: !invert CE1	-
B74	BUFGCTRL[15]: !invert S0	BUFGCTRL[15]: !invert CE0	-
B73	BUFGCTRL[15]: INIT_OUT bit 0	BUFGCTRL[15]: PRESELECT_I0	-
B72	BUFGCTRL[15]: !invert IGNORE1	BUFGCTRL[15]: !invert IGNORE0	-
B71	BUFGCTRL[15]: ! CREATE_EDGE	BUFGCTRL[15]: PRESELECT_I1	-
B70	BUFGCTRL[15]: !invert S1	BUFGCTRL[15]: !invert CE1	-
B69	BUFGCTRL[12]: !invert S0	BUFGCTRL[12]: !invert CE0	-
B68	BUFGCTRL[12]: INIT_OUT bit 0	BUFGCTRL[12]: PRESELECT_I0	-
B67	BUFGCTRL[12]: !invert IGNORE1	BUFGCTRL[12]: !invert IGNORE0	-
B66	BUFGCTRL[12]: ! CREATE_EDGE	BUFGCTRL[12]: PRESELECT_I1	-
B65	BUFGCTRL[12]: !invert S1	BUFGCTRL[12]: !invert CE1	-
B64	BUFGCTRL[13]: !invert S0	BUFGCTRL[13]: !invert CE0	-
B63	BUFGCTRL[13]: INIT_OUT bit 0	BUFGCTRL[13]: PRESELECT_I0	-
B62	BUFGCTRL[13]: !invert IGNORE1	BUFGCTRL[13]: !invert IGNORE0	-
B61	BUFGCTRL[13]: ! CREATE_EDGE	BUFGCTRL[13]: PRESELECT_I1	-
B60	BUFGCTRL[13]: !invert S1	BUFGCTRL[13]: !invert CE1	-
B59	BUFGCTRL[10]: !invert S0	BUFGCTRL[10]: !invert CE0	-
B58	BUFGCTRL[10]: INIT_OUT bit 0	BUFGCTRL[10]: PRESELECT_I0	-
B57	BUFGCTRL[10]: !invert IGNORE1	BUFGCTRL[10]: !invert IGNORE0	-
B56	BUFGCTRL[10]: ! CREATE_EDGE	BUFGCTRL[10]: PRESELECT_I1	-
B55	BUFGCTRL[10]: !invert S1	BUFGCTRL[10]: !invert CE1	-
B54	BUFGCTRL[11]: !invert S0	BUFGCTRL[11]: !invert CE0	-
B53	BUFGCTRL[11]: INIT_OUT bit 0	BUFGCTRL[11]: PRESELECT_I0	-
B52	BUFGCTRL[11]: !invert IGNORE1	BUFGCTRL[11]: !invert IGNORE0	-
B51	BUFGCTRL[11]: ! CREATE_EDGE	BUFGCTRL[11]: PRESELECT_I1	-
B50	BUFGCTRL[11]: !invert S1	BUFGCTRL[11]: !invert CE1	-
B49	BUFGCTRL[8]: !invert S0	BUFGCTRL[8]: !invert CE0	-
B48	BUFGCTRL[8]: INIT_OUT bit 0	BUFGCTRL[8]: PRESELECT_I0	-
B47	BUFGCTRL[8]: !invert IGNORE1	BUFGCTRL[8]: !invert IGNORE0	-
B46	BUFGCTRL[8]: ! CREATE_EDGE	BUFGCTRL[8]: PRESELECT_I1	-
B45	BUFGCTRL[8]: !invert S1	BUFGCTRL[8]: !invert CE1	-
B44	BUFGCTRL[9]: !invert S0	BUFGCTRL[9]: !invert CE0	-
B43	BUFGCTRL[9]: INIT_OUT bit 0	BUFGCTRL[9]: PRESELECT_I0	-
B42	BUFGCTRL[9]: !invert IGNORE1	BUFGCTRL[9]: !invert IGNORE0	-
B41	BUFGCTRL[9]: ! CREATE_EDGE	BUFGCTRL[9]: PRESELECT_I1	-
B40	BUFGCTRL[9]: !invert S1	BUFGCTRL[9]: !invert CE1	-
B39	BUFGCTRL[6]: !invert S0	BUFGCTRL[6]: !invert CE0	-
B38	BUFGCTRL[6]: INIT_OUT bit 0	BUFGCTRL[6]: PRESELECT_I0	-
B37	BUFGCTRL[6]: !invert IGNORE1	BUFGCTRL[6]: !invert IGNORE0	-
B36	BUFGCTRL[6]: ! CREATE_EDGE	BUFGCTRL[6]: PRESELECT_I1	-
B35	BUFGCTRL[6]: !invert S1	BUFGCTRL[6]: !invert CE1	-
B34	BUFGCTRL[7]: !invert S0	BUFGCTRL[7]: !invert CE0	-
B33	BUFGCTRL[7]: INIT_OUT bit 0	BUFGCTRL[7]: PRESELECT_I0	-
B32	BUFGCTRL[7]: !invert IGNORE1	BUFGCTRL[7]: !invert IGNORE0	-
B31	BUFGCTRL[7]: ! CREATE_EDGE	BUFGCTRL[7]: PRESELECT_I1	-
B30	BUFGCTRL[7]: !invert S1	BUFGCTRL[7]: !invert CE1	-
B29	BUFGCTRL[4]: !invert S0	BUFGCTRL[4]: !invert CE0	-
B28	BUFGCTRL[4]: INIT_OUT bit 0	BUFGCTRL[4]: PRESELECT_I0	-
B27	BUFGCTRL[4]: !invert IGNORE1	BUFGCTRL[4]: !invert IGNORE0	-
B26	BUFGCTRL[4]: ! CREATE_EDGE	BUFGCTRL[4]: PRESELECT_I1	-
B25	BUFGCTRL[4]: !invert S1	BUFGCTRL[4]: !invert CE1	-
B24	BUFGCTRL[5]: !invert S0	BUFGCTRL[5]: !invert CE0	-
B23	BUFGCTRL[5]: INIT_OUT bit 0	BUFGCTRL[5]: PRESELECT_I0	-
B22	BUFGCTRL[5]: !invert IGNORE1	BUFGCTRL[5]: !invert IGNORE0	-
B21	BUFGCTRL[5]: ! CREATE_EDGE	BUFGCTRL[5]: PRESELECT_I1	-
B20	BUFGCTRL[5]: !invert S1	BUFGCTRL[5]: !invert CE1	-
B19	BUFGCTRL[2]: !invert S0	BUFGCTRL[2]: !invert CE0	-
B18	BUFGCTRL[2]: INIT_OUT bit 0	BUFGCTRL[2]: PRESELECT_I0	-
B17	BUFGCTRL[2]: !invert IGNORE1	BUFGCTRL[2]: !invert IGNORE0	-
B16	BUFGCTRL[2]: ! CREATE_EDGE	BUFGCTRL[2]: PRESELECT_I1	-
B15	BUFGCTRL[2]: !invert S1	BUFGCTRL[2]: !invert CE1	-
B14	BUFGCTRL[3]: !invert S0	BUFGCTRL[3]: !invert CE0	-
B13	BUFGCTRL[3]: INIT_OUT bit 0	BUFGCTRL[3]: PRESELECT_I0	-
B12	BUFGCTRL[3]: !invert IGNORE1	BUFGCTRL[3]: !invert IGNORE0	-
B11	BUFGCTRL[3]: ! CREATE_EDGE	BUFGCTRL[3]: PRESELECT_I1	-
B10	BUFGCTRL[3]: !invert S1	BUFGCTRL[3]: !invert CE1	-
B9	BUFGCTRL[0]: !invert S0	BUFGCTRL[0]: !invert CE0	-
B8	BUFGCTRL[0]: INIT_OUT bit 0	BUFGCTRL[0]: PRESELECT_I0	-
B7	BUFGCTRL[0]: !invert IGNORE1	BUFGCTRL[0]: !invert IGNORE0	-
B6	BUFGCTRL[0]: ! CREATE_EDGE	BUFGCTRL[0]: PRESELECT_I1	-
B5	BUFGCTRL[0]: !invert S1	BUFGCTRL[0]: !invert CE1	-
B4	BUFGCTRL[1]: !invert S0	BUFGCTRL[1]: !invert CE0	-
B3	BUFGCTRL[1]: INIT_OUT bit 0	BUFGCTRL[1]: PRESELECT_I0	-
B2	BUFGCTRL[1]: !invert IGNORE1	BUFGCTRL[1]: !invert IGNORE0	-
B1	BUFGCTRL[1]: ! CREATE_EDGE	BUFGCTRL[1]: PRESELECT_I1	-
B0	BUFGCTRL[1]: !invert S1	BUFGCTRL[1]: !invert CE1	-

virtex4 CLK_BUFG rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2
B79	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[7]) bit 4	-
B78	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[7]) bit 3	-
B77	SPEC_INT: wire support (CELL[8].OUT_BUFG[7]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[7]) bit 2	-
B76	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[7]) bit 1	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[6]) bit 4	-
B68	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[6]) bit 3	-
B67	SPEC_INT: wire support (CELL[8].OUT_BUFG[6]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[6]) bit 2	-
B66	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[6]) bit 1	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[5]) bit 4	-
B58	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[5]) bit 3	-
B57	SPEC_INT: wire support (CELL[8].OUT_BUFG[5]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[5]) bit 2	-
B56	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[5]) bit 1	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[4]) bit 4	-
B48	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[4]) bit 3	-
B47	SPEC_INT: wire support (CELL[8].OUT_BUFG[4]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[4]) bit 2	-
B46	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[4]) bit 1	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[3]) bit 4	-
B38	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[3]) bit 3	-
B37	SPEC_INT: wire support (CELL[8].OUT_BUFG[3]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[3]) bit 2	-
B36	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[3]) bit 1	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[2]) bit 4	-
B28	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[2]) bit 3	-
B27	SPEC_INT: wire support (CELL[8].OUT_BUFG[2]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[2]) bit 2	-
B26	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[2]) bit 1	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[1]) bit 4	-
B18	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[1]) bit 3	-
B17	SPEC_INT: wire support (CELL[8].OUT_BUFG[1]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[1]) bit 2	-
B16	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[1]) bit 1	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[0]) bit 4	-
B8	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[0]) bit 3	-
B7	SPEC_INT: wire support (CELL[8].OUT_BUFG[0]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[0]) bit 2	-
B6	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[0]) bit 1	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2
B79	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[15]) bit 4	-
B78	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[15]) bit 3	-
B77	SPEC_INT: wire support (CELL[8].OUT_BUFG[15]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[15]) bit 2	-
B76	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[15]) bit 1	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[14]) bit 4	-
B68	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[14]) bit 3	-
B67	SPEC_INT: wire support (CELL[8].OUT_BUFG[14]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[14]) bit 2	-
B66	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[14]) bit 1	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[13]) bit 4	-
B58	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[13]) bit 3	-
B57	SPEC_INT: wire support (CELL[8].OUT_BUFG[13]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[13]) bit 2	-
B56	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[13]) bit 1	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[12]) bit 4	-
B48	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[12]) bit 3	-
B47	SPEC_INT: wire support (CELL[8].OUT_BUFG[12]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[12]) bit 2	-
B46	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[12]) bit 1	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[11]) bit 4	-
B38	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[11]) bit 3	-
B37	SPEC_INT: wire support (CELL[8].OUT_BUFG[11]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[11]) bit 2	-
B36	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[11]) bit 1	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[10]) bit 4	-
B28	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[10]) bit 3	-
B27	SPEC_INT: wire support (CELL[8].OUT_BUFG[10]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[10]) bit 2	-
B26	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[10]) bit 1	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[9]) bit 4	-
B18	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[9]) bit 3	-
B17	SPEC_INT: wire support (CELL[8].OUT_BUFG[9]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[9]) bit 2	-
B16	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[9]) bit 1	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[8]) bit 4	-
B8	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[8]) bit 3	-
B7	SPEC_INT: wire support (CELL[8].OUT_BUFG[8]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[8]) bit 2	-
B6	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[8]) bit 1	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_BUFG rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[24]) bit 4	-
B72	SPEC_INT: wire support (CELL[8].OUT_BUFG[24]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[24]) bit 3	-
B71	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[24]) bit 2	-
B70	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[24]) bit 1	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[25]) bit 4	-
B62	SPEC_INT: wire support (CELL[8].OUT_BUFG[25]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[25]) bit 3	-
B61	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[25]) bit 2	-
B60	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[25]) bit 1	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[26]) bit 4	-
B52	SPEC_INT: wire support (CELL[8].OUT_BUFG[26]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[26]) bit 3	-
B51	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[26]) bit 2	-
B50	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[26]) bit 1	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[27]) bit 4	-
B42	SPEC_INT: wire support (CELL[8].OUT_BUFG[27]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[27]) bit 3	-
B41	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[27]) bit 2	-
B40	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[27]) bit 1	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[28]) bit 4	-
B32	SPEC_INT: wire support (CELL[8].OUT_BUFG[28]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[28]) bit 3	-
B31	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[28]) bit 2	-
B30	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[28]) bit 1	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[29]) bit 4	-
B22	SPEC_INT: wire support (CELL[8].OUT_BUFG[29]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[29]) bit 3	-
B21	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[29]) bit 2	-
B20	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[29]) bit 1	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[30]) bit 4	-
B12	SPEC_INT: wire support (CELL[8].OUT_BUFG[30]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[30]) bit 3	-
B11	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[30]) bit 2	-
B10	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[30]) bit 1	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[31]) bit 4	-
B2	SPEC_INT: wire support (CELL[8].OUT_BUFG[31]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[31]) bit 3	-
B1	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[31]) bit 2	-
B0	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[31]) bit 1	-

virtex4 CLK_BUFG rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[16]) bit 4	-
B72	SPEC_INT: wire support (CELL[8].OUT_BUFG[16]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[16]) bit 3	-
B71	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[16]) bit 2	-
B70	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[16]) bit 1	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[17]) bit 4	-
B62	SPEC_INT: wire support (CELL[8].OUT_BUFG[17]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[17]) bit 3	-
B61	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[17]) bit 2	-
B60	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[17]) bit 1	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[18]) bit 4	-
B52	SPEC_INT: wire support (CELL[8].OUT_BUFG[18]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[18]) bit 3	-
B51	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[18]) bit 2	-
B50	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[18]) bit 1	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[19]) bit 4	-
B42	SPEC_INT: wire support (CELL[8].OUT_BUFG[19]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[19]) bit 3	-
B41	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[19]) bit 2	-
B40	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[19]) bit 1	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[20]) bit 4	-
B32	SPEC_INT: wire support (CELL[8].OUT_BUFG[20]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[20]) bit 3	-
B31	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[20]) bit 2	-
B30	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[20]) bit 1	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[21]) bit 4	-
B22	SPEC_INT: wire support (CELL[8].OUT_BUFG[21]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[21]) bit 3	-
B21	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[21]) bit 2	-
B20	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[21]) bit 1	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[22]) bit 4	-
B12	SPEC_INT: wire support (CELL[8].OUT_BUFG[22]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[22]) bit 3	-
B11	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[22]) bit 2	-
B10	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[22]) bit 1	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[23]) bit 4	-
B2	SPEC_INT: wire support (CELL[8].OUT_BUFG[23]) bit 0	SPEC_INT: wire support (CELL[8].OUT_BUFG[23]) bit 3	-
B1	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[23]) bit 2	-
B0	-	SPEC_INT: wire support (CELL[8].OUT_BUFG[23]) bit 1	-

virtex4 CLK_BUFG rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2
B79	BUFGCTRL[17]: !invert S1	BUFGCTRL[17]: !invert CE1	-
B78	BUFGCTRL[17]: ! CREATE_EDGE	BUFGCTRL[17]: PRESELECT_I1	-
B77	BUFGCTRL[17]: !invert IGNORE1	BUFGCTRL[17]: !invert IGNORE0	-
B76	BUFGCTRL[17]: INIT_OUT bit 0	BUFGCTRL[17]: PRESELECT_I0	-
B75	BUFGCTRL[17]: !invert S0	BUFGCTRL[17]: !invert CE0	-
B74	BUFGCTRL[16]: !invert S1	BUFGCTRL[16]: !invert CE1	-
B73	BUFGCTRL[16]: ! CREATE_EDGE	BUFGCTRL[16]: PRESELECT_I1	-
B72	BUFGCTRL[16]: !invert IGNORE1	BUFGCTRL[16]: !invert IGNORE0	-
B71	BUFGCTRL[16]: INIT_OUT bit 0	BUFGCTRL[16]: PRESELECT_I0	-
B70	BUFGCTRL[16]: !invert S0	BUFGCTRL[16]: !invert CE0	-
B69	BUFGCTRL[19]: !invert S1	BUFGCTRL[19]: !invert CE1	-
B68	BUFGCTRL[19]: ! CREATE_EDGE	BUFGCTRL[19]: PRESELECT_I1	-
B67	BUFGCTRL[19]: !invert IGNORE1	BUFGCTRL[19]: !invert IGNORE0	-
B66	BUFGCTRL[19]: INIT_OUT bit 0	BUFGCTRL[19]: PRESELECT_I0	-
B65	BUFGCTRL[19]: !invert S0	BUFGCTRL[19]: !invert CE0	-
B64	BUFGCTRL[18]: !invert S1	BUFGCTRL[18]: !invert CE1	-
B63	BUFGCTRL[18]: ! CREATE_EDGE	BUFGCTRL[18]: PRESELECT_I1	-
B62	BUFGCTRL[18]: !invert IGNORE1	BUFGCTRL[18]: !invert IGNORE0	-
B61	BUFGCTRL[18]: INIT_OUT bit 0	BUFGCTRL[18]: PRESELECT_I0	-
B60	BUFGCTRL[18]: !invert S0	BUFGCTRL[18]: !invert CE0	-
B59	BUFGCTRL[21]: !invert S1	BUFGCTRL[21]: !invert CE1	-
B58	BUFGCTRL[21]: ! CREATE_EDGE	BUFGCTRL[21]: PRESELECT_I1	-
B57	BUFGCTRL[21]: !invert IGNORE1	BUFGCTRL[21]: !invert IGNORE0	-
B56	BUFGCTRL[21]: INIT_OUT bit 0	BUFGCTRL[21]: PRESELECT_I0	-
B55	BUFGCTRL[21]: !invert S0	BUFGCTRL[21]: !invert CE0	-
B54	BUFGCTRL[20]: !invert S1	BUFGCTRL[20]: !invert CE1	-
B53	BUFGCTRL[20]: ! CREATE_EDGE	BUFGCTRL[20]: PRESELECT_I1	-
B52	BUFGCTRL[20]: !invert IGNORE1	BUFGCTRL[20]: !invert IGNORE0	-
B51	BUFGCTRL[20]: INIT_OUT bit 0	BUFGCTRL[20]: PRESELECT_I0	-
B50	BUFGCTRL[20]: !invert S0	BUFGCTRL[20]: !invert CE0	-
B49	BUFGCTRL[23]: !invert S1	BUFGCTRL[23]: !invert CE1	-
B48	BUFGCTRL[23]: ! CREATE_EDGE	BUFGCTRL[23]: PRESELECT_I1	-
B47	BUFGCTRL[23]: !invert IGNORE1	BUFGCTRL[23]: !invert IGNORE0	-
B46	BUFGCTRL[23]: INIT_OUT bit 0	BUFGCTRL[23]: PRESELECT_I0	-
B45	BUFGCTRL[23]: !invert S0	BUFGCTRL[23]: !invert CE0	-
B44	BUFGCTRL[22]: !invert S1	BUFGCTRL[22]: !invert CE1	-
B43	BUFGCTRL[22]: ! CREATE_EDGE	BUFGCTRL[22]: PRESELECT_I1	-
B42	BUFGCTRL[22]: !invert IGNORE1	BUFGCTRL[22]: !invert IGNORE0	-
B41	BUFGCTRL[22]: INIT_OUT bit 0	BUFGCTRL[22]: PRESELECT_I0	-
B40	BUFGCTRL[22]: !invert S0	BUFGCTRL[22]: !invert CE0	-
B39	BUFGCTRL[25]: !invert S1	BUFGCTRL[25]: !invert CE1	-
B38	BUFGCTRL[25]: ! CREATE_EDGE	BUFGCTRL[25]: PRESELECT_I1	-
B37	BUFGCTRL[25]: !invert IGNORE1	BUFGCTRL[25]: !invert IGNORE0	-
B36	BUFGCTRL[25]: INIT_OUT bit 0	BUFGCTRL[25]: PRESELECT_I0	-
B35	BUFGCTRL[25]: !invert S0	BUFGCTRL[25]: !invert CE0	-
B34	BUFGCTRL[24]: !invert S1	BUFGCTRL[24]: !invert CE1	-
B33	BUFGCTRL[24]: ! CREATE_EDGE	BUFGCTRL[24]: PRESELECT_I1	-
B32	BUFGCTRL[24]: !invert IGNORE1	BUFGCTRL[24]: !invert IGNORE0	-
B31	BUFGCTRL[24]: INIT_OUT bit 0	BUFGCTRL[24]: PRESELECT_I0	-
B30	BUFGCTRL[24]: !invert S0	BUFGCTRL[24]: !invert CE0	-
B29	BUFGCTRL[27]: !invert S1	BUFGCTRL[27]: !invert CE1	-
B28	BUFGCTRL[27]: ! CREATE_EDGE	BUFGCTRL[27]: PRESELECT_I1	-
B27	BUFGCTRL[27]: !invert IGNORE1	BUFGCTRL[27]: !invert IGNORE0	-
B26	BUFGCTRL[27]: INIT_OUT bit 0	BUFGCTRL[27]: PRESELECT_I0	-
B25	BUFGCTRL[27]: !invert S0	BUFGCTRL[27]: !invert CE0	-
B24	BUFGCTRL[26]: !invert S1	BUFGCTRL[26]: !invert CE1	-
B23	BUFGCTRL[26]: ! CREATE_EDGE	BUFGCTRL[26]: PRESELECT_I1	-
B22	BUFGCTRL[26]: !invert IGNORE1	BUFGCTRL[26]: !invert IGNORE0	-
B21	BUFGCTRL[26]: INIT_OUT bit 0	BUFGCTRL[26]: PRESELECT_I0	-
B20	BUFGCTRL[26]: !invert S0	BUFGCTRL[26]: !invert CE0	-
B19	BUFGCTRL[29]: !invert S1	BUFGCTRL[29]: !invert CE1	-
B18	BUFGCTRL[29]: ! CREATE_EDGE	BUFGCTRL[29]: PRESELECT_I1	-
B17	BUFGCTRL[29]: !invert IGNORE1	BUFGCTRL[29]: !invert IGNORE0	-
B16	BUFGCTRL[29]: INIT_OUT bit 0	BUFGCTRL[29]: PRESELECT_I0	-
B15	BUFGCTRL[29]: !invert S0	BUFGCTRL[29]: !invert CE0	-
B14	BUFGCTRL[28]: !invert S1	BUFGCTRL[28]: !invert CE1	-
B13	BUFGCTRL[28]: ! CREATE_EDGE	BUFGCTRL[28]: PRESELECT_I1	-
B12	BUFGCTRL[28]: !invert IGNORE1	BUFGCTRL[28]: !invert IGNORE0	-
B11	BUFGCTRL[28]: INIT_OUT bit 0	BUFGCTRL[28]: PRESELECT_I0	-
B10	BUFGCTRL[28]: !invert S0	BUFGCTRL[28]: !invert CE0	-
B9	BUFGCTRL[31]: !invert S1	BUFGCTRL[31]: !invert CE1	-
B8	BUFGCTRL[31]: ! CREATE_EDGE	BUFGCTRL[31]: PRESELECT_I1	-
B7	BUFGCTRL[31]: !invert IGNORE1	BUFGCTRL[31]: !invert IGNORE0	-
B6	BUFGCTRL[31]: INIT_OUT bit 0	BUFGCTRL[31]: PRESELECT_I0	-
B5	BUFGCTRL[31]: !invert S0	BUFGCTRL[31]: !invert CE0	-
B4	BUFGCTRL[30]: !invert S1	BUFGCTRL[30]: !invert CE1	-
B3	BUFGCTRL[30]: ! CREATE_EDGE	BUFGCTRL[30]: PRESELECT_I1	-
B2	BUFGCTRL[30]: !invert IGNORE1	BUFGCTRL[30]: !invert IGNORE0	-
B1	BUFGCTRL[30]: INIT_OUT bit 0	BUFGCTRL[30]: PRESELECT_I0	-
B0	BUFGCTRL[30]: !invert S0	BUFGCTRL[30]: !invert CE0	-

virtex4 CLK_BUFG rect MAIN[11]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	SPEC_INT: wire support (CELL[9].IMUX_SPEC[2], CELL[9].IMUX_SPEC[3]) bit 0	-
B59	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 1	-
B58	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 0	-
B57	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 5	-
B56	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 4	-
B55	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 3	-
B54	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 2	-
B53	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 11	-
B52	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 7	-
B51	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 9	-
B50	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 8	-
B49	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 6	-
B48	SPEC_INT: mux CELL[9].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[9].IMUX_SPEC[3] bit 10	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	SPEC_INT: wire support (CELL[9].IMUX_SPEC[0], CELL[9].IMUX_SPEC[1]) bit 0	-
B43	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 1	-
B42	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 0	-
B41	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 5	-
B40	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 4	-
B39	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 3	-
B38	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 2	-
B37	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 11	-
B36	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 7	-
B35	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 9	-
B34	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 8	-
B33	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 6	-
B32	SPEC_INT: mux CELL[9].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[9].IMUX_SPEC[1] bit 10	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	SPEC_INT: wire support (CELL[8].IMUX_SPEC[2], CELL[8].IMUX_SPEC[3]) bit 0	-
B27	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 1	-
B26	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 0	-
B25	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 5	-
B24	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 4	-
B23	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 3	-
B22	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 2	-
B21	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 11	-
B20	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 7	-
B19	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 9	-
B18	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 8	-
B17	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 6	-
B16	SPEC_INT: mux CELL[8].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[8].IMUX_SPEC[3] bit 10	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	SPEC_INT: wire support (CELL[8].IMUX_SPEC[0], CELL[8].IMUX_SPEC[1]) bit 0	-
B11	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 1	-
B10	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 0	-
B9	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 5	-
B8	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 4	-
B7	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 3	-
B6	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 2	-
B5	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 11	-
B4	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 7	-
B3	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 9	-
B2	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 8	-
B1	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 6	-
B0	SPEC_INT: mux CELL[8].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[8].IMUX_SPEC[1] bit 10	-

virtex4 CLK_BUFG rect MAIN[12]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	SPEC_INT: wire support (CELL[11].IMUX_SPEC[2], CELL[11].IMUX_SPEC[3]) bit 0	-
B59	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 1	-
B58	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 0	-
B57	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 5	-
B56	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 4	-
B55	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 3	-
B54	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 2	-
B53	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 11	-
B52	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 7	-
B51	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 9	-
B50	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 8	-
B49	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 6	-
B48	SPEC_INT: mux CELL[11].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[11].IMUX_SPEC[3] bit 10	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	SPEC_INT: wire support (CELL[11].IMUX_SPEC[0], CELL[11].IMUX_SPEC[1]) bit 0	-
B43	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 1	-
B42	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 0	-
B41	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 5	-
B40	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 4	-
B39	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 3	-
B38	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 2	-
B37	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 11	-
B36	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 7	-
B35	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 9	-
B34	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 8	-
B33	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 6	-
B32	SPEC_INT: mux CELL[11].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[11].IMUX_SPEC[1] bit 10	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	SPEC_INT: wire support (CELL[10].IMUX_SPEC[2], CELL[10].IMUX_SPEC[3]) bit 0	-
B27	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 1	-
B26	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 0	-
B25	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 5	-
B24	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 4	-
B23	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 3	-
B22	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 2	-
B21	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 11	-
B20	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 7	-
B19	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 9	-
B18	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 8	-
B17	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 6	-
B16	SPEC_INT: mux CELL[10].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[10].IMUX_SPEC[3] bit 10	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	SPEC_INT: wire support (CELL[10].IMUX_SPEC[0], CELL[10].IMUX_SPEC[1]) bit 0	-
B11	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 1	-
B10	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 0	-
B9	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 5	-
B8	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 4	-
B7	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 3	-
B6	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 2	-
B5	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 11	-
B4	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 7	-
B3	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 9	-
B2	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 8	-
B1	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 6	-
B0	SPEC_INT: mux CELL[10].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[10].IMUX_SPEC[1] bit 10	-

virtex4 CLK_BUFG rect MAIN[13]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	SPEC_INT: wire support (CELL[13].IMUX_SPEC[2], CELL[13].IMUX_SPEC[3]) bit 0	-
B59	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 1	-
B58	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 0	-
B57	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 5	-
B56	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 4	-
B55	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 3	-
B54	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 2	-
B53	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 11	-
B52	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 7	-
B51	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 9	-
B50	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 8	-
B49	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 6	-
B48	SPEC_INT: mux CELL[13].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[13].IMUX_SPEC[3] bit 10	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	SPEC_INT: wire support (CELL[13].IMUX_SPEC[0], CELL[13].IMUX_SPEC[1]) bit 0	-
B43	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 1	-
B42	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 0	-
B41	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 5	-
B40	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 4	-
B39	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 3	-
B38	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 2	-
B37	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 11	-
B36	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 7	-
B35	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 9	-
B34	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 8	-
B33	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 6	-
B32	SPEC_INT: mux CELL[13].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[13].IMUX_SPEC[1] bit 10	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	SPEC_INT: wire support (CELL[12].IMUX_SPEC[2], CELL[12].IMUX_SPEC[3]) bit 0	-
B27	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 1	-
B26	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 0	-
B25	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 5	-
B24	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 4	-
B23	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 3	-
B22	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 2	-
B21	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 11	-
B20	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 7	-
B19	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 9	-
B18	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 8	-
B17	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 6	-
B16	SPEC_INT: mux CELL[12].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[12].IMUX_SPEC[3] bit 10	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	SPEC_INT: wire support (CELL[12].IMUX_SPEC[0], CELL[12].IMUX_SPEC[1]) bit 0	-
B11	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 1	-
B10	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 0	-
B9	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 5	-
B8	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 4	-
B7	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 3	-
B6	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 2	-
B5	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 11	-
B4	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 7	-
B3	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 9	-
B2	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 8	-
B1	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 6	-
B0	SPEC_INT: mux CELL[12].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[12].IMUX_SPEC[1] bit 10	-

virtex4 CLK_BUFG rect MAIN[14]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	SPEC_INT: wire support (CELL[8].MGT_ROW[1]) bit 0	-	-
B64	SPEC_INT: wire support (CELL[8].MGT_ROW[0]) bit 0	-	-
B63	SPEC_INT: wire support (CELL_E8.MGT_ROW[1]) bit 0	-	-
B62	SPEC_INT: wire support (CELL_E8.MGT_ROW[0]) bit 0	-	-
B61	-	-	-
B60	-	SPEC_INT: wire support (CELL[15].IMUX_SPEC[2], CELL[15].IMUX_SPEC[3]) bit 0	-
B59	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 1	-
B58	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 0	-
B57	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 5	-
B56	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 4	-
B55	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 3	-
B54	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 2	-
B53	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 11	-
B52	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 7	-
B51	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 9	-
B50	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 8	-
B49	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 6	-
B48	SPEC_INT: mux CELL[15].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[15].IMUX_SPEC[3] bit 10	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	SPEC_INT: wire support (CELL[15].IMUX_SPEC[0], CELL[15].IMUX_SPEC[1]) bit 0	-
B43	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 1	-
B42	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 0	-
B41	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 5	-
B40	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 4	-
B39	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 3	-
B38	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 2	-
B37	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 11	-
B36	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 7	-
B35	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 9	-
B34	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 8	-
B33	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 6	-
B32	SPEC_INT: mux CELL[15].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[15].IMUX_SPEC[1] bit 10	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	SPEC_INT: wire support (CELL[14].IMUX_SPEC[2], CELL[14].IMUX_SPEC[3]) bit 0	-
B27	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 1	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 1	-
B26	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 0	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 0	-
B25	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 5	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 5	-
B24	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 4	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 4	-
B23	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 3	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 3	-
B22	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 2	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 2	-
B21	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 11	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 11	-
B20	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 7	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 7	-
B19	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 9	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 9	-
B18	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 8	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 8	-
B17	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 6	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 6	-
B16	SPEC_INT: mux CELL[14].IMUX_SPEC[2] bit 10	SPEC_INT: mux CELL[14].IMUX_SPEC[3] bit 10	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	SPEC_INT: wire support (CELL[14].IMUX_SPEC[0], CELL[14].IMUX_SPEC[1]) bit 0	-
B11	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 1	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 1	-
B10	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 0	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 0	-
B9	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 5	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 5	-
B8	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 4	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 4	-
B7	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 3	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 3	-
B6	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 2	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 2	-
B5	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 11	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 11	-
B4	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 7	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 7	-
B3	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 9	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 9	-
B2	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 8	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 8	-
B1	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 6	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 6	-
B0	SPEC_INT: mux CELL[14].IMUX_SPEC[0] bit 10	SPEC_INT: mux CELL[14].IMUX_SPEC[1] bit 10	-

virtex4 CLK_BUFG rect MAIN[15]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

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