Clock row buffers

Tile CLK_HROW

Cells: 2

Switchbox HROW_INT

virtex4 CLK_HROW switchbox HROW_INT programmable buffers
Destination	Source	Bit
W.GCLK_BUF[0]	W.GCLK[0]	HCLK[0][12]
W.GCLK_BUF[1]	W.GCLK[1]	HCLK[1][12]
W.GCLK_BUF[2]	W.GCLK[2]	HCLK[0][13]
W.GCLK_BUF[3]	W.GCLK[3]	HCLK[1][13]
W.GCLK_BUF[4]	W.GCLK[4]	HCLK[0][14]
W.GCLK_BUF[5]	W.GCLK[5]	HCLK[1][14]
W.GCLK_BUF[6]	W.GCLK[6]	HCLK[0][15]
W.GCLK_BUF[7]	W.GCLK[7]	HCLK[1][15]
W.GCLK_BUF[8]	W.GCLK[8]	MAIN[0][0][5]
W.GCLK_BUF[9]	W.GCLK[9]	MAIN[0][0][6]
W.GCLK_BUF[10]	W.GCLK[10]	MAIN[0][0][7]
W.GCLK_BUF[11]	W.GCLK[11]	MAIN[0][0][8]
W.GCLK_BUF[12]	W.GCLK[12]	MAIN[1][0][8]
W.GCLK_BUF[13]	W.GCLK[13]	MAIN[1][0][7]
W.GCLK_BUF[14]	W.GCLK[14]	MAIN[1][0][6]
W.GCLK_BUF[15]	W.GCLK[15]	MAIN[1][0][5]
W.GCLK_BUF[16]	W.GCLK[16]	MAIN[0][0][9]
W.GCLK_BUF[17]	W.GCLK[17]	MAIN[0][0][4]
W.GCLK_BUF[18]	W.GCLK[18]	MAIN[0][0][3]
W.GCLK_BUF[19]	W.GCLK[19]	MAIN[0][0][2]
W.GCLK_BUF[20]	W.GCLK[20]	MAIN[1][0][2]
W.GCLK_BUF[21]	W.GCLK[21]	MAIN[1][0][3]
W.GCLK_BUF[22]	W.GCLK[22]	MAIN[1][0][4]
W.GCLK_BUF[23]	W.GCLK[23]	MAIN[1][0][9]
W.GCLK_BUF[24]	W.GCLK[24]	MAIN[0][0][0]
W.GCLK_BUF[25]	W.GCLK[25]	MAIN[0][0][1]
W.GCLK_BUF[26]	W.GCLK[26]	HCLK[2][12]
W.GCLK_BUF[27]	W.GCLK[27]	HCLK[2][13]
W.GCLK_BUF[28]	W.GCLK[28]	HCLK[2][14]
W.GCLK_BUF[29]	W.GCLK[29]	HCLK[2][15]
W.GCLK_BUF[30]	W.GCLK[30]	MAIN[1][0][1]
W.GCLK_BUF[31]	W.GCLK[31]	MAIN[1][0][0]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[0]
Bits																				Destination
MAIN[1][0][11]	MAIN[1][1][13]	MAIN[1][1][14]	MAIN[1][1][12]	MAIN[1][1][0]	MAIN[1][1][2]	MAIN[1][1][3]	MAIN[1][1][6]	MAIN[1][1][7]	MAIN[1][1][8]	MAIN[1][1][9]	MAIN[1][1][11]	MAIN[1][1][19]	MAIN[1][1][18]	MAIN[1][1][17]	MAIN[1][1][16]	MAIN[1][1][15]	MAIN[1][1][5]	MAIN[1][1][4]	MAIN[1][1][1]	W.HCLK_ROW[0]
MAIN[1][0][10]	MAIN[1][2][13]	MAIN[1][2][14]	MAIN[1][2][12]	MAIN[1][2][0]	MAIN[1][2][2]	MAIN[1][2][3]	MAIN[1][2][6]	MAIN[1][2][7]	MAIN[1][2][8]	MAIN[1][2][9]	MAIN[1][2][11]	MAIN[1][2][19]	MAIN[1][2][18]	MAIN[1][2][17]	MAIN[1][2][16]	MAIN[1][2][15]	MAIN[1][2][5]	MAIN[1][2][4]	MAIN[1][2][1]	E.HCLK_ROW[0]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[1]
Bits																				Destination
MAIN[0][0][71]	MAIN[0][1][73]	MAIN[0][1][74]	MAIN[0][1][72]	MAIN[0][1][60]	MAIN[0][1][62]	MAIN[0][1][63]	MAIN[0][1][66]	MAIN[0][1][67]	MAIN[0][1][68]	MAIN[0][1][69]	MAIN[0][1][71]	MAIN[0][1][79]	MAIN[0][1][78]	MAIN[0][1][77]	MAIN[0][1][76]	MAIN[0][1][75]	MAIN[0][1][65]	MAIN[0][1][64]	MAIN[0][1][61]	W.HCLK_ROW[1]
MAIN[0][0][70]	MAIN[0][2][73]	MAIN[0][2][74]	MAIN[0][2][72]	MAIN[0][2][60]	MAIN[0][2][62]	MAIN[0][2][63]	MAIN[0][2][66]	MAIN[0][2][67]	MAIN[0][2][68]	MAIN[0][2][69]	MAIN[0][2][71]	MAIN[0][2][79]	MAIN[0][2][78]	MAIN[0][2][77]	MAIN[0][2][76]	MAIN[0][2][75]	MAIN[0][2][65]	MAIN[0][2][64]	MAIN[0][2][61]	E.HCLK_ROW[1]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[2]
Bits																				Destination
MAIN[1][0][31]	MAIN[1][1][33]	MAIN[1][1][34]	MAIN[1][1][32]	MAIN[1][1][20]	MAIN[1][1][22]	MAIN[1][1][23]	MAIN[1][1][26]	MAIN[1][1][27]	MAIN[1][1][28]	MAIN[1][1][29]	MAIN[1][1][31]	MAIN[1][1][39]	MAIN[1][1][38]	MAIN[1][1][37]	MAIN[1][1][36]	MAIN[1][1][35]	MAIN[1][1][25]	MAIN[1][1][24]	MAIN[1][1][21]	W.HCLK_ROW[2]
MAIN[1][0][30]	MAIN[1][2][33]	MAIN[1][2][34]	MAIN[1][2][32]	MAIN[1][2][20]	MAIN[1][2][22]	MAIN[1][2][23]	MAIN[1][2][26]	MAIN[1][2][27]	MAIN[1][2][28]	MAIN[1][2][29]	MAIN[1][2][31]	MAIN[1][2][39]	MAIN[1][2][38]	MAIN[1][2][37]	MAIN[1][2][36]	MAIN[1][2][35]	MAIN[1][2][25]	MAIN[1][2][24]	MAIN[1][2][21]	E.HCLK_ROW[2]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[3]
Bits																				Destination
MAIN[0][0][51]	MAIN[0][1][53]	MAIN[0][1][54]	MAIN[0][1][52]	MAIN[0][1][40]	MAIN[0][1][42]	MAIN[0][1][43]	MAIN[0][1][46]	MAIN[0][1][47]	MAIN[0][1][48]	MAIN[0][1][49]	MAIN[0][1][51]	MAIN[0][1][59]	MAIN[0][1][58]	MAIN[0][1][57]	MAIN[0][1][56]	MAIN[0][1][55]	MAIN[0][1][45]	MAIN[0][1][44]	MAIN[0][1][41]	W.HCLK_ROW[3]
MAIN[0][0][50]	MAIN[0][2][53]	MAIN[0][2][54]	MAIN[0][2][52]	MAIN[0][2][40]	MAIN[0][2][42]	MAIN[0][2][43]	MAIN[0][2][46]	MAIN[0][2][47]	MAIN[0][2][48]	MAIN[0][2][49]	MAIN[0][2][51]	MAIN[0][2][59]	MAIN[0][2][58]	MAIN[0][2][57]	MAIN[0][2][56]	MAIN[0][2][55]	MAIN[0][2][45]	MAIN[0][2][44]	MAIN[0][2][41]	E.HCLK_ROW[3]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[4]
Bits																				Destination
MAIN[1][0][51]	MAIN[1][1][53]	MAIN[1][1][54]	MAIN[1][1][52]	MAIN[1][1][40]	MAIN[1][1][42]	MAIN[1][1][43]	MAIN[1][1][46]	MAIN[1][1][47]	MAIN[1][1][48]	MAIN[1][1][49]	MAIN[1][1][51]	MAIN[1][1][59]	MAIN[1][1][58]	MAIN[1][1][57]	MAIN[1][1][56]	MAIN[1][1][55]	MAIN[1][1][45]	MAIN[1][1][44]	MAIN[1][1][41]	W.HCLK_ROW[4]
MAIN[1][0][50]	MAIN[1][2][53]	MAIN[1][2][54]	MAIN[1][2][52]	MAIN[1][2][40]	MAIN[1][2][42]	MAIN[1][2][43]	MAIN[1][2][46]	MAIN[1][2][47]	MAIN[1][2][48]	MAIN[1][2][49]	MAIN[1][2][51]	MAIN[1][2][59]	MAIN[1][2][58]	MAIN[1][2][57]	MAIN[1][2][56]	MAIN[1][2][55]	MAIN[1][2][45]	MAIN[1][2][44]	MAIN[1][2][41]	E.HCLK_ROW[4]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[5]
Bits																				Destination
MAIN[0][0][31]	MAIN[0][1][33]	MAIN[0][1][34]	MAIN[0][1][32]	MAIN[0][1][20]	MAIN[0][1][22]	MAIN[0][1][23]	MAIN[0][1][26]	MAIN[0][1][27]	MAIN[0][1][28]	MAIN[0][1][29]	MAIN[0][1][31]	MAIN[0][1][39]	MAIN[0][1][38]	MAIN[0][1][37]	MAIN[0][1][36]	MAIN[0][1][35]	MAIN[0][1][25]	MAIN[0][1][24]	MAIN[0][1][21]	W.HCLK_ROW[5]
MAIN[0][0][30]	MAIN[0][2][33]	MAIN[0][2][34]	MAIN[0][2][32]	MAIN[0][2][20]	MAIN[0][2][22]	MAIN[0][2][23]	MAIN[0][2][26]	MAIN[0][2][27]	MAIN[0][2][28]	MAIN[0][2][29]	MAIN[0][2][31]	MAIN[0][2][39]	MAIN[0][2][38]	MAIN[0][2][37]	MAIN[0][2][36]	MAIN[0][2][35]	MAIN[0][2][25]	MAIN[0][2][24]	MAIN[0][2][21]	E.HCLK_ROW[5]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[6]
Bits																				Destination
MAIN[1][0][71]	MAIN[1][1][73]	MAIN[1][1][74]	MAIN[1][1][72]	MAIN[1][1][60]	MAIN[1][1][62]	MAIN[1][1][63]	MAIN[1][1][66]	MAIN[1][1][67]	MAIN[1][1][68]	MAIN[1][1][69]	MAIN[1][1][71]	MAIN[1][1][79]	MAIN[1][1][78]	MAIN[1][1][77]	MAIN[1][1][76]	MAIN[1][1][75]	MAIN[1][1][65]	MAIN[1][1][64]	MAIN[1][1][61]	W.HCLK_ROW[6]
MAIN[1][0][70]	MAIN[1][2][73]	MAIN[1][2][74]	MAIN[1][2][72]	MAIN[1][2][60]	MAIN[1][2][62]	MAIN[1][2][63]	MAIN[1][2][66]	MAIN[1][2][67]	MAIN[1][2][68]	MAIN[1][2][69]	MAIN[1][2][71]	MAIN[1][2][79]	MAIN[1][2][78]	MAIN[1][2][77]	MAIN[1][2][76]	MAIN[1][2][75]	MAIN[1][2][65]	MAIN[1][2][64]	MAIN[1][2][61]	E.HCLK_ROW[6]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

virtex4 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[7]
Bits																				Destination
MAIN[0][0][11]	MAIN[0][1][13]	MAIN[0][1][14]	MAIN[0][1][12]	MAIN[0][1][0]	MAIN[0][1][2]	MAIN[0][1][3]	MAIN[0][1][6]	MAIN[0][1][7]	MAIN[0][1][8]	MAIN[0][1][9]	MAIN[0][1][11]	MAIN[0][1][19]	MAIN[0][1][18]	MAIN[0][1][17]	MAIN[0][1][16]	MAIN[0][1][15]	MAIN[0][1][5]	MAIN[0][1][4]	MAIN[0][1][1]	W.HCLK_ROW[7]
MAIN[0][0][10]	MAIN[0][2][13]	MAIN[0][2][14]	MAIN[0][2][12]	MAIN[0][2][0]	MAIN[0][2][2]	MAIN[0][2][3]	MAIN[0][2][6]	MAIN[0][2][7]	MAIN[0][2][8]	MAIN[0][2][9]	MAIN[0][2][11]	MAIN[0][2][19]	MAIN[0][2][18]	MAIN[0][2][17]	MAIN[0][2][16]	MAIN[0][2][15]	MAIN[0][2][5]	MAIN[0][2][4]	MAIN[0][2][1]	E.HCLK_ROW[7]
																				Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[1]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[2]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[3]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[4]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[5]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[6]
0	0	0	1	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[7]
0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[8]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[9]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[10]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[11]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[12]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[13]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[14]
0	0	1	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[15]
0	1	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[16]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[17]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[18]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[19]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[20]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[21]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[22]
0	1	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[23]
1	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	W.GCLK_BUF[24]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[25]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[26]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[27]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[28]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[29]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[30]
1	0	0	0	1	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	W.GCLK_BUF[31]

Bitstream

virtex4 CLK_HROW rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	HROW_INT: mux W.HCLK_ROW[1] bit 7	HROW_INT: mux E.HCLK_ROW[1] bit 7
B78	-	HROW_INT: mux W.HCLK_ROW[1] bit 6	HROW_INT: mux E.HCLK_ROW[1] bit 6
B77	-	HROW_INT: mux W.HCLK_ROW[1] bit 5	HROW_INT: mux E.HCLK_ROW[1] bit 5
B76	-	HROW_INT: mux W.HCLK_ROW[1] bit 4	HROW_INT: mux E.HCLK_ROW[1] bit 4
B75	-	HROW_INT: mux W.HCLK_ROW[1] bit 3	HROW_INT: mux E.HCLK_ROW[1] bit 3
B74	-	HROW_INT: mux W.HCLK_ROW[1] bit 17	HROW_INT: mux E.HCLK_ROW[1] bit 17
B73	-	HROW_INT: mux W.HCLK_ROW[1] bit 18	HROW_INT: mux E.HCLK_ROW[1] bit 18
B72	-	HROW_INT: mux W.HCLK_ROW[1] bit 16	HROW_INT: mux E.HCLK_ROW[1] bit 16
B71	HROW_INT: mux W.HCLK_ROW[1] bit 19	HROW_INT: mux W.HCLK_ROW[1] bit 8	HROW_INT: mux E.HCLK_ROW[1] bit 8
B70	HROW_INT: mux E.HCLK_ROW[1] bit 19	-	-
B69	-	HROW_INT: mux W.HCLK_ROW[1] bit 9	HROW_INT: mux E.HCLK_ROW[1] bit 9
B68	-	HROW_INT: mux W.HCLK_ROW[1] bit 10	HROW_INT: mux E.HCLK_ROW[1] bit 10
B67	-	HROW_INT: mux W.HCLK_ROW[1] bit 11	HROW_INT: mux E.HCLK_ROW[1] bit 11
B66	-	HROW_INT: mux W.HCLK_ROW[1] bit 12	HROW_INT: mux E.HCLK_ROW[1] bit 12
B65	-	HROW_INT: mux W.HCLK_ROW[1] bit 2	HROW_INT: mux E.HCLK_ROW[1] bit 2
B64	-	HROW_INT: mux W.HCLK_ROW[1] bit 1	HROW_INT: mux E.HCLK_ROW[1] bit 1
B63	-	HROW_INT: mux W.HCLK_ROW[1] bit 13	HROW_INT: mux E.HCLK_ROW[1] bit 13
B62	-	HROW_INT: mux W.HCLK_ROW[1] bit 14	HROW_INT: mux E.HCLK_ROW[1] bit 14
B61	-	HROW_INT: mux W.HCLK_ROW[1] bit 0	HROW_INT: mux E.HCLK_ROW[1] bit 0
B60	-	HROW_INT: mux W.HCLK_ROW[1] bit 15	HROW_INT: mux E.HCLK_ROW[1] bit 15
B59	-	HROW_INT: mux W.HCLK_ROW[3] bit 7	HROW_INT: mux E.HCLK_ROW[3] bit 7
B58	-	HROW_INT: mux W.HCLK_ROW[3] bit 6	HROW_INT: mux E.HCLK_ROW[3] bit 6
B57	-	HROW_INT: mux W.HCLK_ROW[3] bit 5	HROW_INT: mux E.HCLK_ROW[3] bit 5
B56	-	HROW_INT: mux W.HCLK_ROW[3] bit 4	HROW_INT: mux E.HCLK_ROW[3] bit 4
B55	-	HROW_INT: mux W.HCLK_ROW[3] bit 3	HROW_INT: mux E.HCLK_ROW[3] bit 3
B54	-	HROW_INT: mux W.HCLK_ROW[3] bit 17	HROW_INT: mux E.HCLK_ROW[3] bit 17
B53	-	HROW_INT: mux W.HCLK_ROW[3] bit 18	HROW_INT: mux E.HCLK_ROW[3] bit 18
B52	-	HROW_INT: mux W.HCLK_ROW[3] bit 16	HROW_INT: mux E.HCLK_ROW[3] bit 16
B51	HROW_INT: mux W.HCLK_ROW[3] bit 19	HROW_INT: mux W.HCLK_ROW[3] bit 8	HROW_INT: mux E.HCLK_ROW[3] bit 8
B50	HROW_INT: mux E.HCLK_ROW[3] bit 19	-	-
B49	-	HROW_INT: mux W.HCLK_ROW[3] bit 9	HROW_INT: mux E.HCLK_ROW[3] bit 9
B48	-	HROW_INT: mux W.HCLK_ROW[3] bit 10	HROW_INT: mux E.HCLK_ROW[3] bit 10
B47	-	HROW_INT: mux W.HCLK_ROW[3] bit 11	HROW_INT: mux E.HCLK_ROW[3] bit 11
B46	-	HROW_INT: mux W.HCLK_ROW[3] bit 12	HROW_INT: mux E.HCLK_ROW[3] bit 12
B45	-	HROW_INT: mux W.HCLK_ROW[3] bit 2	HROW_INT: mux E.HCLK_ROW[3] bit 2
B44	-	HROW_INT: mux W.HCLK_ROW[3] bit 1	HROW_INT: mux E.HCLK_ROW[3] bit 1
B43	-	HROW_INT: mux W.HCLK_ROW[3] bit 13	HROW_INT: mux E.HCLK_ROW[3] bit 13
B42	-	HROW_INT: mux W.HCLK_ROW[3] bit 14	HROW_INT: mux E.HCLK_ROW[3] bit 14
B41	-	HROW_INT: mux W.HCLK_ROW[3] bit 0	HROW_INT: mux E.HCLK_ROW[3] bit 0
B40	-	HROW_INT: mux W.HCLK_ROW[3] bit 15	HROW_INT: mux E.HCLK_ROW[3] bit 15
B39	-	HROW_INT: mux W.HCLK_ROW[5] bit 7	HROW_INT: mux E.HCLK_ROW[5] bit 7
B38	-	HROW_INT: mux W.HCLK_ROW[5] bit 6	HROW_INT: mux E.HCLK_ROW[5] bit 6
B37	-	HROW_INT: mux W.HCLK_ROW[5] bit 5	HROW_INT: mux E.HCLK_ROW[5] bit 5
B36	-	HROW_INT: mux W.HCLK_ROW[5] bit 4	HROW_INT: mux E.HCLK_ROW[5] bit 4
B35	-	HROW_INT: mux W.HCLK_ROW[5] bit 3	HROW_INT: mux E.HCLK_ROW[5] bit 3
B34	-	HROW_INT: mux W.HCLK_ROW[5] bit 17	HROW_INT: mux E.HCLK_ROW[5] bit 17
B33	-	HROW_INT: mux W.HCLK_ROW[5] bit 18	HROW_INT: mux E.HCLK_ROW[5] bit 18
B32	-	HROW_INT: mux W.HCLK_ROW[5] bit 16	HROW_INT: mux E.HCLK_ROW[5] bit 16
B31	HROW_INT: mux W.HCLK_ROW[5] bit 19	HROW_INT: mux W.HCLK_ROW[5] bit 8	HROW_INT: mux E.HCLK_ROW[5] bit 8
B30	HROW_INT: mux E.HCLK_ROW[5] bit 19	-	-
B29	-	HROW_INT: mux W.HCLK_ROW[5] bit 9	HROW_INT: mux E.HCLK_ROW[5] bit 9
B28	-	HROW_INT: mux W.HCLK_ROW[5] bit 10	HROW_INT: mux E.HCLK_ROW[5] bit 10
B27	-	HROW_INT: mux W.HCLK_ROW[5] bit 11	HROW_INT: mux E.HCLK_ROW[5] bit 11
B26	-	HROW_INT: mux W.HCLK_ROW[5] bit 12	HROW_INT: mux E.HCLK_ROW[5] bit 12
B25	-	HROW_INT: mux W.HCLK_ROW[5] bit 2	HROW_INT: mux E.HCLK_ROW[5] bit 2
B24	-	HROW_INT: mux W.HCLK_ROW[5] bit 1	HROW_INT: mux E.HCLK_ROW[5] bit 1
B23	-	HROW_INT: mux W.HCLK_ROW[5] bit 13	HROW_INT: mux E.HCLK_ROW[5] bit 13
B22	-	HROW_INT: mux W.HCLK_ROW[5] bit 14	HROW_INT: mux E.HCLK_ROW[5] bit 14
B21	-	HROW_INT: mux W.HCLK_ROW[5] bit 0	HROW_INT: mux E.HCLK_ROW[5] bit 0
B20	-	HROW_INT: mux W.HCLK_ROW[5] bit 15	HROW_INT: mux E.HCLK_ROW[5] bit 15
B19	-	HROW_INT: mux W.HCLK_ROW[7] bit 7	HROW_INT: mux E.HCLK_ROW[7] bit 7
B18	-	HROW_INT: mux W.HCLK_ROW[7] bit 6	HROW_INT: mux E.HCLK_ROW[7] bit 6
B17	-	HROW_INT: mux W.HCLK_ROW[7] bit 5	HROW_INT: mux E.HCLK_ROW[7] bit 5
B16	-	HROW_INT: mux W.HCLK_ROW[7] bit 4	HROW_INT: mux E.HCLK_ROW[7] bit 4
B15	-	HROW_INT: mux W.HCLK_ROW[7] bit 3	HROW_INT: mux E.HCLK_ROW[7] bit 3
B14	-	HROW_INT: mux W.HCLK_ROW[7] bit 17	HROW_INT: mux E.HCLK_ROW[7] bit 17
B13	-	HROW_INT: mux W.HCLK_ROW[7] bit 18	HROW_INT: mux E.HCLK_ROW[7] bit 18
B12	-	HROW_INT: mux W.HCLK_ROW[7] bit 16	HROW_INT: mux E.HCLK_ROW[7] bit 16
B11	HROW_INT: mux W.HCLK_ROW[7] bit 19	HROW_INT: mux W.HCLK_ROW[7] bit 8	HROW_INT: mux E.HCLK_ROW[7] bit 8
B10	HROW_INT: mux E.HCLK_ROW[7] bit 19	-	-
B9	HROW_INT: buffer W.GCLK_BUF[16] ← W.GCLK[16]	HROW_INT: mux W.HCLK_ROW[7] bit 9	HROW_INT: mux E.HCLK_ROW[7] bit 9
B8	HROW_INT: buffer W.GCLK_BUF[11] ← W.GCLK[11]	HROW_INT: mux W.HCLK_ROW[7] bit 10	HROW_INT: mux E.HCLK_ROW[7] bit 10
B7	HROW_INT: buffer W.GCLK_BUF[10] ← W.GCLK[10]	HROW_INT: mux W.HCLK_ROW[7] bit 11	HROW_INT: mux E.HCLK_ROW[7] bit 11
B6	HROW_INT: buffer W.GCLK_BUF[9] ← W.GCLK[9]	HROW_INT: mux W.HCLK_ROW[7] bit 12	HROW_INT: mux E.HCLK_ROW[7] bit 12
B5	HROW_INT: buffer W.GCLK_BUF[8] ← W.GCLK[8]	HROW_INT: mux W.HCLK_ROW[7] bit 2	HROW_INT: mux E.HCLK_ROW[7] bit 2
B4	HROW_INT: buffer W.GCLK_BUF[17] ← W.GCLK[17]	HROW_INT: mux W.HCLK_ROW[7] bit 1	HROW_INT: mux E.HCLK_ROW[7] bit 1
B3	HROW_INT: buffer W.GCLK_BUF[18] ← W.GCLK[18]	HROW_INT: mux W.HCLK_ROW[7] bit 13	HROW_INT: mux E.HCLK_ROW[7] bit 13
B2	HROW_INT: buffer W.GCLK_BUF[19] ← W.GCLK[19]	HROW_INT: mux W.HCLK_ROW[7] bit 14	HROW_INT: mux E.HCLK_ROW[7] bit 14
B1	HROW_INT: buffer W.GCLK_BUF[25] ← W.GCLK[25]	HROW_INT: mux W.HCLK_ROW[7] bit 0	HROW_INT: mux E.HCLK_ROW[7] bit 0
B0	HROW_INT: buffer W.GCLK_BUF[24] ← W.GCLK[24]	HROW_INT: mux W.HCLK_ROW[7] bit 15	HROW_INT: mux E.HCLK_ROW[7] bit 15

virtex4 CLK_HROW rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	-	HROW_INT: mux W.HCLK_ROW[6] bit 7	HROW_INT: mux E.HCLK_ROW[6] bit 7
B78	-	HROW_INT: mux W.HCLK_ROW[6] bit 6	HROW_INT: mux E.HCLK_ROW[6] bit 6
B77	-	HROW_INT: mux W.HCLK_ROW[6] bit 5	HROW_INT: mux E.HCLK_ROW[6] bit 5
B76	-	HROW_INT: mux W.HCLK_ROW[6] bit 4	HROW_INT: mux E.HCLK_ROW[6] bit 4
B75	-	HROW_INT: mux W.HCLK_ROW[6] bit 3	HROW_INT: mux E.HCLK_ROW[6] bit 3
B74	-	HROW_INT: mux W.HCLK_ROW[6] bit 17	HROW_INT: mux E.HCLK_ROW[6] bit 17
B73	-	HROW_INT: mux W.HCLK_ROW[6] bit 18	HROW_INT: mux E.HCLK_ROW[6] bit 18
B72	-	HROW_INT: mux W.HCLK_ROW[6] bit 16	HROW_INT: mux E.HCLK_ROW[6] bit 16
B71	HROW_INT: mux W.HCLK_ROW[6] bit 19	HROW_INT: mux W.HCLK_ROW[6] bit 8	HROW_INT: mux E.HCLK_ROW[6] bit 8
B70	HROW_INT: mux E.HCLK_ROW[6] bit 19	-	-
B69	-	HROW_INT: mux W.HCLK_ROW[6] bit 9	HROW_INT: mux E.HCLK_ROW[6] bit 9
B68	-	HROW_INT: mux W.HCLK_ROW[6] bit 10	HROW_INT: mux E.HCLK_ROW[6] bit 10
B67	-	HROW_INT: mux W.HCLK_ROW[6] bit 11	HROW_INT: mux E.HCLK_ROW[6] bit 11
B66	-	HROW_INT: mux W.HCLK_ROW[6] bit 12	HROW_INT: mux E.HCLK_ROW[6] bit 12
B65	-	HROW_INT: mux W.HCLK_ROW[6] bit 2	HROW_INT: mux E.HCLK_ROW[6] bit 2
B64	-	HROW_INT: mux W.HCLK_ROW[6] bit 1	HROW_INT: mux E.HCLK_ROW[6] bit 1
B63	-	HROW_INT: mux W.HCLK_ROW[6] bit 13	HROW_INT: mux E.HCLK_ROW[6] bit 13
B62	-	HROW_INT: mux W.HCLK_ROW[6] bit 14	HROW_INT: mux E.HCLK_ROW[6] bit 14
B61	-	HROW_INT: mux W.HCLK_ROW[6] bit 0	HROW_INT: mux E.HCLK_ROW[6] bit 0
B60	-	HROW_INT: mux W.HCLK_ROW[6] bit 15	HROW_INT: mux E.HCLK_ROW[6] bit 15
B59	-	HROW_INT: mux W.HCLK_ROW[4] bit 7	HROW_INT: mux E.HCLK_ROW[4] bit 7
B58	-	HROW_INT: mux W.HCLK_ROW[4] bit 6	HROW_INT: mux E.HCLK_ROW[4] bit 6
B57	-	HROW_INT: mux W.HCLK_ROW[4] bit 5	HROW_INT: mux E.HCLK_ROW[4] bit 5
B56	-	HROW_INT: mux W.HCLK_ROW[4] bit 4	HROW_INT: mux E.HCLK_ROW[4] bit 4
B55	-	HROW_INT: mux W.HCLK_ROW[4] bit 3	HROW_INT: mux E.HCLK_ROW[4] bit 3
B54	-	HROW_INT: mux W.HCLK_ROW[4] bit 17	HROW_INT: mux E.HCLK_ROW[4] bit 17
B53	-	HROW_INT: mux W.HCLK_ROW[4] bit 18	HROW_INT: mux E.HCLK_ROW[4] bit 18
B52	-	HROW_INT: mux W.HCLK_ROW[4] bit 16	HROW_INT: mux E.HCLK_ROW[4] bit 16
B51	HROW_INT: mux W.HCLK_ROW[4] bit 19	HROW_INT: mux W.HCLK_ROW[4] bit 8	HROW_INT: mux E.HCLK_ROW[4] bit 8
B50	HROW_INT: mux E.HCLK_ROW[4] bit 19	-	-
B49	-	HROW_INT: mux W.HCLK_ROW[4] bit 9	HROW_INT: mux E.HCLK_ROW[4] bit 9
B48	-	HROW_INT: mux W.HCLK_ROW[4] bit 10	HROW_INT: mux E.HCLK_ROW[4] bit 10
B47	-	HROW_INT: mux W.HCLK_ROW[4] bit 11	HROW_INT: mux E.HCLK_ROW[4] bit 11
B46	-	HROW_INT: mux W.HCLK_ROW[4] bit 12	HROW_INT: mux E.HCLK_ROW[4] bit 12
B45	-	HROW_INT: mux W.HCLK_ROW[4] bit 2	HROW_INT: mux E.HCLK_ROW[4] bit 2
B44	-	HROW_INT: mux W.HCLK_ROW[4] bit 1	HROW_INT: mux E.HCLK_ROW[4] bit 1
B43	-	HROW_INT: mux W.HCLK_ROW[4] bit 13	HROW_INT: mux E.HCLK_ROW[4] bit 13
B42	-	HROW_INT: mux W.HCLK_ROW[4] bit 14	HROW_INT: mux E.HCLK_ROW[4] bit 14
B41	-	HROW_INT: mux W.HCLK_ROW[4] bit 0	HROW_INT: mux E.HCLK_ROW[4] bit 0
B40	-	HROW_INT: mux W.HCLK_ROW[4] bit 15	HROW_INT: mux E.HCLK_ROW[4] bit 15
B39	-	HROW_INT: mux W.HCLK_ROW[2] bit 7	HROW_INT: mux E.HCLK_ROW[2] bit 7
B38	-	HROW_INT: mux W.HCLK_ROW[2] bit 6	HROW_INT: mux E.HCLK_ROW[2] bit 6
B37	-	HROW_INT: mux W.HCLK_ROW[2] bit 5	HROW_INT: mux E.HCLK_ROW[2] bit 5
B36	-	HROW_INT: mux W.HCLK_ROW[2] bit 4	HROW_INT: mux E.HCLK_ROW[2] bit 4
B35	-	HROW_INT: mux W.HCLK_ROW[2] bit 3	HROW_INT: mux E.HCLK_ROW[2] bit 3
B34	-	HROW_INT: mux W.HCLK_ROW[2] bit 17	HROW_INT: mux E.HCLK_ROW[2] bit 17
B33	-	HROW_INT: mux W.HCLK_ROW[2] bit 18	HROW_INT: mux E.HCLK_ROW[2] bit 18
B32	-	HROW_INT: mux W.HCLK_ROW[2] bit 16	HROW_INT: mux E.HCLK_ROW[2] bit 16
B31	HROW_INT: mux W.HCLK_ROW[2] bit 19	HROW_INT: mux W.HCLK_ROW[2] bit 8	HROW_INT: mux E.HCLK_ROW[2] bit 8
B30	HROW_INT: mux E.HCLK_ROW[2] bit 19	-	-
B29	-	HROW_INT: mux W.HCLK_ROW[2] bit 9	HROW_INT: mux E.HCLK_ROW[2] bit 9
B28	-	HROW_INT: mux W.HCLK_ROW[2] bit 10	HROW_INT: mux E.HCLK_ROW[2] bit 10
B27	-	HROW_INT: mux W.HCLK_ROW[2] bit 11	HROW_INT: mux E.HCLK_ROW[2] bit 11
B26	-	HROW_INT: mux W.HCLK_ROW[2] bit 12	HROW_INT: mux E.HCLK_ROW[2] bit 12
B25	-	HROW_INT: mux W.HCLK_ROW[2] bit 2	HROW_INT: mux E.HCLK_ROW[2] bit 2
B24	-	HROW_INT: mux W.HCLK_ROW[2] bit 1	HROW_INT: mux E.HCLK_ROW[2] bit 1
B23	-	HROW_INT: mux W.HCLK_ROW[2] bit 13	HROW_INT: mux E.HCLK_ROW[2] bit 13
B22	-	HROW_INT: mux W.HCLK_ROW[2] bit 14	HROW_INT: mux E.HCLK_ROW[2] bit 14
B21	-	HROW_INT: mux W.HCLK_ROW[2] bit 0	HROW_INT: mux E.HCLK_ROW[2] bit 0
B20	-	HROW_INT: mux W.HCLK_ROW[2] bit 15	HROW_INT: mux E.HCLK_ROW[2] bit 15
B19	-	HROW_INT: mux W.HCLK_ROW[0] bit 7	HROW_INT: mux E.HCLK_ROW[0] bit 7
B18	-	HROW_INT: mux W.HCLK_ROW[0] bit 6	HROW_INT: mux E.HCLK_ROW[0] bit 6
B17	-	HROW_INT: mux W.HCLK_ROW[0] bit 5	HROW_INT: mux E.HCLK_ROW[0] bit 5
B16	-	HROW_INT: mux W.HCLK_ROW[0] bit 4	HROW_INT: mux E.HCLK_ROW[0] bit 4
B15	-	HROW_INT: mux W.HCLK_ROW[0] bit 3	HROW_INT: mux E.HCLK_ROW[0] bit 3
B14	-	HROW_INT: mux W.HCLK_ROW[0] bit 17	HROW_INT: mux E.HCLK_ROW[0] bit 17
B13	-	HROW_INT: mux W.HCLK_ROW[0] bit 18	HROW_INT: mux E.HCLK_ROW[0] bit 18
B12	-	HROW_INT: mux W.HCLK_ROW[0] bit 16	HROW_INT: mux E.HCLK_ROW[0] bit 16
B11	HROW_INT: mux W.HCLK_ROW[0] bit 19	HROW_INT: mux W.HCLK_ROW[0] bit 8	HROW_INT: mux E.HCLK_ROW[0] bit 8
B10	HROW_INT: mux E.HCLK_ROW[0] bit 19	-	-
B9	HROW_INT: buffer W.GCLK_BUF[23] ← W.GCLK[23]	HROW_INT: mux W.HCLK_ROW[0] bit 9	HROW_INT: mux E.HCLK_ROW[0] bit 9
B8	HROW_INT: buffer W.GCLK_BUF[12] ← W.GCLK[12]	HROW_INT: mux W.HCLK_ROW[0] bit 10	HROW_INT: mux E.HCLK_ROW[0] bit 10
B7	HROW_INT: buffer W.GCLK_BUF[13] ← W.GCLK[13]	HROW_INT: mux W.HCLK_ROW[0] bit 11	HROW_INT: mux E.HCLK_ROW[0] bit 11
B6	HROW_INT: buffer W.GCLK_BUF[14] ← W.GCLK[14]	HROW_INT: mux W.HCLK_ROW[0] bit 12	HROW_INT: mux E.HCLK_ROW[0] bit 12
B5	HROW_INT: buffer W.GCLK_BUF[15] ← W.GCLK[15]	HROW_INT: mux W.HCLK_ROW[0] bit 2	HROW_INT: mux E.HCLK_ROW[0] bit 2
B4	HROW_INT: buffer W.GCLK_BUF[22] ← W.GCLK[22]	HROW_INT: mux W.HCLK_ROW[0] bit 1	HROW_INT: mux E.HCLK_ROW[0] bit 1
B3	HROW_INT: buffer W.GCLK_BUF[21] ← W.GCLK[21]	HROW_INT: mux W.HCLK_ROW[0] bit 13	HROW_INT: mux E.HCLK_ROW[0] bit 13
B2	HROW_INT: buffer W.GCLK_BUF[20] ← W.GCLK[20]	HROW_INT: mux W.HCLK_ROW[0] bit 14	HROW_INT: mux E.HCLK_ROW[0] bit 14
B1	HROW_INT: buffer W.GCLK_BUF[30] ← W.GCLK[30]	HROW_INT: mux W.HCLK_ROW[0] bit 0	HROW_INT: mux E.HCLK_ROW[0] bit 0
B0	HROW_INT: buffer W.GCLK_BUF[31] ← W.GCLK[31]	HROW_INT: mux W.HCLK_ROW[0] bit 15	HROW_INT: mux E.HCLK_ROW[0] bit 15

virtex4 CLK_HROW rect HCLK
Bit	Frame
Bit	F0	F1	F2
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	HROW_INT: buffer W.GCLK_BUF[6] ← W.GCLK[6]	HROW_INT: buffer W.GCLK_BUF[7] ← W.GCLK[7]	HROW_INT: buffer W.GCLK_BUF[29] ← W.GCLK[29]
B14	HROW_INT: buffer W.GCLK_BUF[4] ← W.GCLK[4]	HROW_INT: buffer W.GCLK_BUF[5] ← W.GCLK[5]	HROW_INT: buffer W.GCLK_BUF[28] ← W.GCLK[28]
B13	HROW_INT: buffer W.GCLK_BUF[2] ← W.GCLK[2]	HROW_INT: buffer W.GCLK_BUF[3] ← W.GCLK[3]	HROW_INT: buffer W.GCLK_BUF[27] ← W.GCLK[27]
B12	HROW_INT: buffer W.GCLK_BUF[0] ← W.GCLK[0]	HROW_INT: buffer W.GCLK_BUF[1] ← W.GCLK[1]	HROW_INT: buffer W.GCLK_BUF[26] ← W.GCLK[26]
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

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Clock row buffers

Tile CLK_HROW

Switchbox HROW_INT

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