Keyboard shortcuts

Press ← or → to navigate between chapters

Press ? to show this help

Press Esc to hide this help

Clock I/O and DCM buffers

Tile HCLK_IOIS_LVDS

Cells: 3

Bel IOCLK

virtex4 HCLK_IOIS_LVDS bel IOCLK
PinDirectionWires

Bel RCLK

virtex4 HCLK_IOIS_LVDS bel RCLK
PinDirectionWires
CKINT0inputCELL1.IMUX.BYP4
CKINT1inputCELL2.IMUX.BYP4

Bel BUFR0

virtex4 HCLK_IOIS_LVDS bel BUFR0
PinDirectionWires
CEinputCELL2.IMUX.BYP0
CLRinputCELL2.IMUX.BYP2

Bel BUFR1

virtex4 HCLK_IOIS_LVDS bel BUFR1
PinDirectionWires
CEinputCELL1.IMUX.BYP0
CLRinputCELL1.IMUX.BYP2

Bel BUFIO0

virtex4 HCLK_IOIS_LVDS bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOIS_LVDS bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOIS_LVDS bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT.HALF.BOT0.TMIN, CELL1.OUT.HALT.TOP0.TMIN
OUTN1outputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
OUTN65outputCELL1.OUT.HALF.BOT2.TMIN, CELL1.OUT.HALT.TOP2.TMIN
RDYoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
RSTinputCELL1.IMUX.BYP7
UPPULSEOUToutputCELL1.OUT.HALF.BOT1.TMIN, CELL1.OUT.HALT.TOP1.TMIN

Bel wires

virtex4 HCLK_IOIS_LVDS bel wires
WirePins
CELL1.IMUX.BYP0BUFR1.CE
CELL1.IMUX.BYP2BUFR1.CLR
CELL1.IMUX.BYP4RCLK.CKINT0
CELL1.IMUX.BYP7IDELAYCTRL.RST
CELL1.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL2.IMUX.BYP0BUFR0.CE
CELL2.IMUX.BYP2BUFR0.CLR
CELL2.IMUX.BYP4RCLK.CKINT1

Bitstream

virtex4 HCLK_IOIS_LVDS rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25
B15 - - - LVDS:LVDSBIAS[2] - LVDS:LVDSBIAS[6] - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - - - - - BUFR0:BUFR_DIVIDE[0] IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - BUFR0:MUX.I[1] - IOCLK:BUF.RCLK0 BUFR1:BUFR_DIVIDE[0] RCLK:MUX.RCLK1[0] IOCLK:BUF.RCLK1 RCLK:MUX.RCLK0[0]
B14 - - LVDS:LVDSBIAS[7] LVDS:LVDSBIAS[4] - LVDS:LVDSBIAS[1] - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - - - - - BUFR0:BUFR_DIVIDE[3] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - BUFR0:MUX.I[0] - BUFR0:ENABLE BUFR1:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[2] IDELAYCTRL:MUX.REFCLK[2] RCLK:MUX.RCLK0[2]
B13 - - LVDS:LVDSBIAS[3] LVDS:LVDSBIAS[5] - - - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - - LVDS:LVDSBIAS[8] - - BUFR0:BUFR_DIVIDE[2] IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - BUFR1:MUX.I[0] IOCLK:VIOCLK_ENABLE[3] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[1] RCLK:MUX.RCLK0[1]
B12 - - - LVDS:LVDSBIAS[9] - LVDS:LVDSBIAS[0] - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - - IDELAYCTRL:ENABLE - - BUFR0:BUFR_DIVIDE[1] - - IOCLK:BUF.IOCLK_N1 - BUFR1:MUX.I[1] - - BUFR1:BUFR_DIVIDE[1] RCLK:MUX.RCLK1[3] IDELAYCTRL:MUX.REFCLK[0] RCLK:MUX.RCLK0[3]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFR0:BUFR_DIVIDE 0.F14.B14 0.F14.B13 0.F14.B12 0.F14.B15
BUFR1:BUFR_DIVIDE 0.F22.B14 0.F22.B13 0.F22.B12 0.F22.B15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:ENABLE 0.F21.B14
BUFR1:ENABLE 0.F21.B13
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
BUFR0:MUX.I 0.F19.B15 0.F19.B14
BUFR1:MUX.I 0.F19.B12 0.F19.B13
BUFIO0 0 0
CKINT0 0 1
CKINT1 1 0
BUFIO1 1 1
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
LVDS:LVDSBIAS 0.F3.B12 0.F11.B13 0.F2.B14 0.F5.B15 0.F3.B13 0.F3.B14 0.F2.B13 0.F3.B15 0.F5.B14 0.F5.B12
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
RCLK:MUX.RCLK0 0.F25.B12 0.F25.B14 0.F25.B13 0.F25.B15
RCLK:MUX.RCLK1 0.F23.B12 0.F23.B14 0.F23.B13 0.F23.B15
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_S0 0 1 0 1
VRCLK_N1 1 0 0 1
VRCLK1 1 0 1 1
VRCLK_S1 1 1 0 1

Tile HCLK_IOIS_DCI

Cells: 3

Bel IOCLK

virtex4 HCLK_IOIS_DCI bel IOCLK
PinDirectionWires

Bel RCLK

virtex4 HCLK_IOIS_DCI bel RCLK
PinDirectionWires
CKINT0inputCELL1.IMUX.BYP4
CKINT1inputCELL2.IMUX.BYP4

Bel BUFR0

virtex4 HCLK_IOIS_DCI bel BUFR0
PinDirectionWires
CEinputCELL2.IMUX.BYP0
CLRinputCELL2.IMUX.BYP2

Bel BUFR1

virtex4 HCLK_IOIS_DCI bel BUFR1
PinDirectionWires
CEinputCELL1.IMUX.BYP0
CLRinputCELL1.IMUX.BYP2

Bel BUFIO0

virtex4 HCLK_IOIS_DCI bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOIS_DCI bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOIS_DCI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT.HALF.BOT0.TMIN, CELL1.OUT.HALT.TOP0.TMIN
OUTN1outputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
OUTN65outputCELL1.OUT.HALF.BOT2.TMIN, CELL1.OUT.HALT.TOP2.TMIN
RDYoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
RSTinputCELL1.IMUX.BYP7
UPPULSEOUToutputCELL1.OUT.HALF.BOT1.TMIN, CELL1.OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_IOIS_DCI bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT.HALF.BOT5.TMIN, CELL1.OUT.HALT.TOP5.TMIN
DCIADDRESS1outputCELL1.OUT.HALF.BOT6.TMIN, CELL1.OUT.HALT.TOP6.TMIN
DCIADDRESS2outputCELL1.OUT.HALF.BOT7.TMIN, CELL1.OUT.HALT.TOP7.TMIN
DCIDATAoutputCELL0.OUT.HALF.BOT7.TMIN, CELL0.OUT.HALT.TOP7.TMIN
DCIDONEoutputCELL0.OUT.HALF.BOT3.TMIN, CELL0.OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputCELL0.OUT.HALF.BOT5.TMIN, CELL0.OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputCELL0.OUT.HALF.BOT4.TMIN, CELL0.OUT.HALT.TOP4.TMIN
DCISCLKoutputCELL0.OUT.HALF.BOT6.TMIN, CELL0.OUT.HALT.TOP6.TMIN
TSTCLKinputCELL0.IMUX.BYP0
TSTHLNinputCELL0.IMUX.BYP4
TSTHLPinputCELL0.IMUX.BYP7
TSTRSTinputCELL0.IMUX.BYP2

Bel wires

virtex4 HCLK_IOIS_DCI bel wires
WirePins
CELL0.IMUX.BYP0DCI.TSTCLK
CELL0.IMUX.BYP2DCI.TSTRST
CELL0.IMUX.BYP4DCI.TSTHLN
CELL0.IMUX.BYP7DCI.TSTHLP
CELL0.OUT.HALF.BOT3.TMINDCI.DCIDONE
CELL0.OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALF.BOT6.TMINDCI.DCISCLK
CELL0.OUT.HALF.BOT7.TMINDCI.DCIDATA
CELL0.OUT.HALT.TOP3.TMINDCI.DCIDONE
CELL0.OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALT.TOP6.TMINDCI.DCISCLK
CELL0.OUT.HALT.TOP7.TMINDCI.DCIDATA
CELL1.IMUX.BYP0BUFR1.CE
CELL1.IMUX.BYP2BUFR1.CLR
CELL1.IMUX.BYP4RCLK.CKINT0
CELL1.IMUX.BYP7IDELAYCTRL.RST
CELL1.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
CELL1.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
CELL2.IMUX.BYP0BUFR0.CE
CELL2.IMUX.BYP2BUFR0.CLR
CELL2.IMUX.BYP4RCLK.CKINT1

Bitstream

virtex4 HCLK_IOIS_DCI rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - BUFR0:BUFR_DIVIDE[0] IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - BUFR0:MUX.I[1] - IOCLK:BUF.RCLK0 BUFR1:BUFR_DIVIDE[0] RCLK:MUX.RCLK1[0] IOCLK:BUF.RCLK1 RCLK:MUX.RCLK0[0] - DCI:NREF[0]
B14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - BUFR0:BUFR_DIVIDE[3] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - BUFR0:MUX.I[0] - BUFR0:ENABLE BUFR1:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[2] IDELAYCTRL:MUX.REFCLK[2] RCLK:MUX.RCLK0[2] - DCI:LVDIV2[1]
B13 - DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - BUFR0:BUFR_DIVIDE[2] IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - BUFR1:MUX.I[0] IOCLK:VIOCLK_ENABLE[3] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[1] RCLK:MUX.RCLK0[1] - DCI:LVDIV2[0]
B12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - BUFR0:BUFR_DIVIDE[1] - - IOCLK:BUF.IOCLK_N1 - BUFR1:MUX.I[1] - - BUFR1:BUFR_DIVIDE[1] RCLK:MUX.RCLK1[3] IDELAYCTRL:MUX.REFCLK[0] RCLK:MUX.RCLK0[3] - DCI:NREF[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFR0:BUFR_DIVIDE 0.F14.B14 0.F14.B13 0.F14.B12 0.F14.B15
BUFR1:BUFR_DIVIDE 0.F22.B14 0.F22.B13 0.F22.B12 0.F22.B15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:ENABLE 0.F21.B14
BUFR1:ENABLE 0.F21.B13
DCI:ENABLE 0.F0.B14
DCI:QUIET 0.F5.B12
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
BUFR0:MUX.I 0.F19.B15 0.F19.B14
BUFR1:MUX.I 0.F19.B12 0.F19.B13
BUFIO0 0 0
CKINT0 0 1
CKINT1 1 0
BUFIO1 1 1
DCI:LVDIV2 0.F27.B14 0.F27.B13
DCI:NREF 0.F27.B12 0.F27.B15
DCI:TEST_ENABLE 0.F5.B13 0.F0.B15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.F10.B12 0.F12.B15 0.F12.B14 0.F12.B13 0.F12.B12
DCI:PMASK_TERM_SPLIT 0.F11.B15 0.F10.B15 0.F11.B14 0.F10.B14 0.F10.B13
DCI:PMASK_TERM_VCC 0.F2.B12 0.F4.B15 0.F4.B14 0.F4.B13 0.F4.B12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.F1.B12 0.F1.B13 0.F1.B14 0.F1.B15
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1
RCLK:MUX.RCLK0 0.F25.B12 0.F25.B14 0.F25.B13 0.F25.B15
RCLK:MUX.RCLK1 0.F23.B12 0.F23.B14 0.F23.B13 0.F23.B15
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_S0 0 1 0 1
VRCLK_N1 1 0 0 1
VRCLK1 1 0 1 1
VRCLK_S1 1 1 0 1

Tile HCLK_CENTER

Cells: 2

Bel IOCLK

virtex4 HCLK_CENTER bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_CENTER bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_CENTER bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_CENTER bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT.HALF.BOT0.TMIN, CELL1.OUT.HALT.TOP0.TMIN
OUTN1outputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
OUTN65outputCELL1.OUT.HALF.BOT2.TMIN, CELL1.OUT.HALT.TOP2.TMIN
RDYoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
RSTinputCELL1.IMUX.BYP7
UPPULSEOUToutputCELL1.OUT.HALF.BOT1.TMIN, CELL1.OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_CENTER bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT.HALF.BOT5.TMIN, CELL1.OUT.HALT.TOP5.TMIN
DCIADDRESS1outputCELL1.OUT.HALF.BOT6.TMIN, CELL1.OUT.HALT.TOP6.TMIN
DCIADDRESS2outputCELL1.OUT.HALF.BOT7.TMIN, CELL1.OUT.HALT.TOP7.TMIN
DCIDATAoutputCELL0.OUT.HALF.BOT7.TMIN, CELL0.OUT.HALT.TOP7.TMIN
DCIDONEoutputCELL0.OUT.HALF.BOT3.TMIN, CELL0.OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputCELL0.OUT.HALF.BOT5.TMIN, CELL0.OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputCELL0.OUT.HALF.BOT4.TMIN, CELL0.OUT.HALT.TOP4.TMIN
DCISCLKoutputCELL0.OUT.HALF.BOT6.TMIN, CELL0.OUT.HALT.TOP6.TMIN
TSTCLKinputCELL0.IMUX.BYP0
TSTHLNinputCELL0.IMUX.BYP4
TSTHLPinputCELL0.IMUX.BYP7
TSTRSTinputCELL0.IMUX.BYP2

Bel wires

virtex4 HCLK_CENTER bel wires
WirePins
CELL0.IMUX.BYP0DCI.TSTCLK
CELL0.IMUX.BYP2DCI.TSTRST
CELL0.IMUX.BYP4DCI.TSTHLN
CELL0.IMUX.BYP7DCI.TSTHLP
CELL0.OUT.HALF.BOT3.TMINDCI.DCIDONE
CELL0.OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALF.BOT6.TMINDCI.DCISCLK
CELL0.OUT.HALF.BOT7.TMINDCI.DCIDATA
CELL0.OUT.HALT.TOP3.TMINDCI.DCIDONE
CELL0.OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALT.TOP6.TMINDCI.DCISCLK
CELL0.OUT.HALT.TOP7.TMINDCI.DCIDATA
CELL1.IMUX.BYP7IDELAYCTRL.RST
CELL1.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
CELL1.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALT.TOP7.TMINDCI.DCIADDRESS2

Bitstream

virtex4 HCLK_CENTER rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - - IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - - - IOCLK:BUF.RCLK0 - - IOCLK:BUF.RCLK1 - - DCI:NREF[0]
B14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - - IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - - - - - - IDELAYCTRL:MUX.REFCLK[2] - - DCI:LVDIV2[1]
B13 DCI:CASCADE_FROM_ABOVE DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - - IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - - IOCLK:VIOCLK_ENABLE[3] - - - IDELAYCTRL:MUX.REFCLK[1] - - DCI:LVDIV2[0]
B12 DCI:CASCADE_FROM_BELOW DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - - IOCLK:BUF.IOCLK_N1 - - - - - - IDELAYCTRL:MUX.REFCLK[0] - - DCI:NREF[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:CASCADE_FROM_ABOVE 0.F0.B13
DCI:CASCADE_FROM_BELOW 0.F0.B12
DCI:ENABLE 0.F0.B14
DCI:QUIET 0.F5.B12
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
DCI:LVDIV2 0.F27.B14 0.F27.B13
DCI:NREF 0.F27.B12 0.F27.B15
DCI:TEST_ENABLE 0.F5.B13 0.F0.B15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.F10.B12 0.F12.B15 0.F12.B14 0.F12.B13 0.F12.B12
DCI:PMASK_TERM_SPLIT 0.F11.B15 0.F10.B15 0.F11.B14 0.F10.B14 0.F10.B13
DCI:PMASK_TERM_VCC 0.F2.B12 0.F4.B15 0.F4.B14 0.F4.B13 0.F4.B12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.F1.B12 0.F1.B13 0.F1.B14 0.F1.B15
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_CENTER_ABOVE_CFG

Cells: 2

Bel IOCLK

virtex4 HCLK_CENTER_ABOVE_CFG bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_CENTER_ABOVE_CFG bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_CENTER_ABOVE_CFG bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_CENTER_ABOVE_CFG bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL0.OUT.HALF.BOT0.TMIN, CELL0.OUT.HALT.TOP0.TMIN
OUTN1outputCELL0.OUT.HALF.BOT3.TMIN, CELL0.OUT.HALT.TOP3.TMIN
OUTN65outputCELL0.OUT.HALF.BOT2.TMIN, CELL0.OUT.HALT.TOP2.TMIN
RDYoutputCELL0.OUT.HALF.BOT4.TMIN, CELL0.OUT.HALT.TOP4.TMIN
RSTinputCELL0.IMUX.BYP7
UPPULSEOUToutputCELL0.OUT.HALF.BOT1.TMIN, CELL0.OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_CENTER_ABOVE_CFG bel DCI
PinDirectionWires
DCIADDRESS0outputCELL0.OUT.HALF.BOT5.TMIN, CELL0.OUT.HALT.TOP5.TMIN
DCIADDRESS1outputCELL0.OUT.HALF.BOT6.TMIN, CELL0.OUT.HALT.TOP6.TMIN
DCIADDRESS2outputCELL0.OUT.HALF.BOT7.TMIN, CELL0.OUT.HALT.TOP7.TMIN
DCIDATAoutputCELL1.OUT.HALF.BOT7.TMIN, CELL1.OUT.HALT.TOP7.TMIN
DCIDONEoutputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputCELL1.OUT.HALF.BOT5.TMIN, CELL1.OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
DCISCLKoutputCELL1.OUT.HALF.BOT6.TMIN, CELL1.OUT.HALT.TOP6.TMIN
TSTCLKinputCELL1.IMUX.BYP0
TSTHLNinputCELL1.IMUX.BYP7
TSTHLPinputCELL1.IMUX.BYP4
TSTRSTinputCELL1.IMUX.BYP2

Bel wires

virtex4 HCLK_CENTER_ABOVE_CFG bel wires
WirePins
CELL0.IMUX.BYP7IDELAYCTRL.RST
CELL0.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL0.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL0.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL0.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL0.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL0.OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
CELL0.OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
CELL0.OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
CELL0.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL0.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL0.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL0.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL0.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL0.OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
CELL0.OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
CELL0.OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
CELL1.IMUX.BYP0DCI.TSTCLK
CELL1.IMUX.BYP2DCI.TSTRST
CELL1.IMUX.BYP4DCI.TSTHLP
CELL1.IMUX.BYP7DCI.TSTHLN
CELL1.OUT.HALF.BOT3.TMINDCI.DCIDONE
CELL1.OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
CELL1.OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
CELL1.OUT.HALF.BOT6.TMINDCI.DCISCLK
CELL1.OUT.HALF.BOT7.TMINDCI.DCIDATA
CELL1.OUT.HALT.TOP3.TMINDCI.DCIDONE
CELL1.OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
CELL1.OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
CELL1.OUT.HALT.TOP6.TMINDCI.DCISCLK
CELL1.OUT.HALT.TOP7.TMINDCI.DCIDATA

Bitstream

virtex4 HCLK_CENTER_ABOVE_CFG rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - - IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - - - IOCLK:BUF.RCLK0 - - IOCLK:BUF.RCLK1 - - DCI:NREF[0]
B14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - - IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - - - - - - IDELAYCTRL:MUX.REFCLK[2] - - DCI:LVDIV2[1]
B13 DCI:CASCADE_FROM_ABOVE DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - - IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - - IOCLK:VIOCLK_ENABLE[3] - - - IDELAYCTRL:MUX.REFCLK[1] - - DCI:LVDIV2[0]
B12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - - IOCLK:BUF.IOCLK_N1 - - - - - - IDELAYCTRL:MUX.REFCLK[0] - - DCI:NREF[1]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:CASCADE_FROM_ABOVE 0.F0.B13
DCI:ENABLE 0.F0.B14
DCI:QUIET 0.F5.B12
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
DCI:LVDIV2 0.F27.B14 0.F27.B13
DCI:NREF 0.F27.B12 0.F27.B15
DCI:TEST_ENABLE 0.F5.B13 0.F0.B15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.F10.B12 0.F12.B15 0.F12.B14 0.F12.B13 0.F12.B12
DCI:PMASK_TERM_SPLIT 0.F11.B15 0.F10.B15 0.F11.B14 0.F10.B14 0.F10.B13
DCI:PMASK_TERM_VCC 0.F2.B12 0.F4.B15 0.F4.B14 0.F4.B13 0.F4.B12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.F1.B12 0.F1.B13 0.F1.B14 0.F1.B15
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_IOBDCM

Cells: 2

Bel IOCLK

virtex4 HCLK_IOBDCM bel IOCLK
PinDirectionWires

Bel HCLK_DCM_HROW

virtex4 HCLK_IOBDCM bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM_N

virtex4 HCLK_IOBDCM bel HCLK_DCM_N
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_IOBDCM bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOBDCM bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOBDCM bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL1.OUT.HALF.BOT0.TMIN, CELL1.OUT.HALT.TOP0.TMIN
OUTN1outputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
OUTN65outputCELL1.OUT.HALF.BOT2.TMIN, CELL1.OUT.HALT.TOP2.TMIN
RDYoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
RSTinputCELL1.IMUX.BYP7
UPPULSEOUToutputCELL1.OUT.HALF.BOT1.TMIN, CELL1.OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_IOBDCM bel DCI
PinDirectionWires
DCIADDRESS0outputCELL1.OUT.HALF.BOT5.TMIN, CELL1.OUT.HALT.TOP5.TMIN
DCIADDRESS1outputCELL1.OUT.HALF.BOT6.TMIN, CELL1.OUT.HALT.TOP6.TMIN
DCIADDRESS2outputCELL1.OUT.HALF.BOT7.TMIN, CELL1.OUT.HALT.TOP7.TMIN
DCIDATAoutputCELL0.OUT.HALF.BOT7.TMIN, CELL0.OUT.HALT.TOP7.TMIN
DCIDONEoutputCELL0.OUT.HALF.BOT3.TMIN, CELL0.OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputCELL0.OUT.HALF.BOT5.TMIN, CELL0.OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputCELL0.OUT.HALF.BOT4.TMIN, CELL0.OUT.HALT.TOP4.TMIN
DCISCLKoutputCELL0.OUT.HALF.BOT6.TMIN, CELL0.OUT.HALT.TOP6.TMIN
TSTCLKinputCELL0.IMUX.BYP0
TSTHLNinputCELL0.IMUX.BYP4
TSTHLPinputCELL0.IMUX.BYP7
TSTRSTinputCELL0.IMUX.BYP2

Bel wires

virtex4 HCLK_IOBDCM bel wires
WirePins
CELL0.IMUX.BYP0DCI.TSTCLK
CELL0.IMUX.BYP2DCI.TSTRST
CELL0.IMUX.BYP4DCI.TSTHLN
CELL0.IMUX.BYP7DCI.TSTHLP
CELL0.OUT.HALF.BOT3.TMINDCI.DCIDONE
CELL0.OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALF.BOT6.TMINDCI.DCISCLK
CELL0.OUT.HALF.BOT7.TMINDCI.DCIDATA
CELL0.OUT.HALT.TOP3.TMINDCI.DCIDONE
CELL0.OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
CELL0.OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
CELL0.OUT.HALT.TOP6.TMINDCI.DCISCLK
CELL0.OUT.HALT.TOP7.TMINDCI.DCIDATA
CELL1.IMUX.BYP7IDELAYCTRL.RST
CELL1.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
CELL1.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL1.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL1.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL1.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL1.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL1.OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
CELL1.OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
CELL1.OUT.HALT.TOP7.TMINDCI.DCIADDRESS2

Bitstream

virtex4 HCLK_IOBDCM rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28
B15 DCI:TEST_ENABLE[0] DCI:PREF[0] - HCLK_DCM_N:BUF.GIOB_U15 DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - HCLK_DCM_N:BUF.HCLK_U3 IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - HCLK_DCM_N:COMMON[1] - IOCLK:BUF.RCLK0 HCLK_DCM_N:BUF.HCLK_U2 HCLK_DCM_N:BUF.MGT_U3 IOCLK:BUF.RCLK1 HCLK_DCM_N:BUF.GIOB_U12 HCLK_DCM_N:BUF.MGT_U2 DCI:NREF[0] -
B14 DCI:ENABLE DCI:PREF[1] - HCLK_DCM_N:BUF.GIOB_U14 DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - HCLK_DCM_N:COMMON[0] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - HCLK_DCM_N:BUF.HCLK_U4 - HCLK_DCM_N:BUF.GIOB_U1 HCLK_DCM_N:BUF.HCLK_U6 HCLK_DCM_N:BUF.GIOB_U7 IDELAYCTRL:MUX.REFCLK[2] HCLK_DCM_N:BUF.GIOB_U11 HCLK_DCM_N:BUF.MGT_U1 DCI:LVDIV2[1] -
B13 - DCI:PREF[2] - HCLK_DCM_N:BUF.GIOB_U0 DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - HCLK_DCM_N:BUF.MGT_U0 IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - HCLK_DCM_N:BUF.GIOB_U3 IOCLK:VIOCLK_ENABLE[3] HCLK_DCM_N:COMMON[2] HCLK_DCM_N:BUF.GIOB_U2 HCLK_DCM_N:BUF.HCLK_U5 IDELAYCTRL:MUX.REFCLK[1] HCLK_DCM_N:BUF.HCLK_U1 HCLK_DCM_N:BUF.GIOB_U10 DCI:LVDIV2[0] HCLK_DCM_N:BUF.GIOB_U4
B12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - HCLK_DCM_N:COMMON_MGT IOCLK:BUF.IOCLK_N1 - HCLK_DCM_N:BUF.GIOB_U13 - HCLK_DCM_N:BUF.HCLK_U0 HCLK_DCM_N:BUF.GIOB_U9 HCLK_DCM_N:BUF.GIOB_U8 IDELAYCTRL:MUX.REFCLK[0] HCLK_DCM_N:BUF.GIOB_U6 HCLK_DCM_N:BUF.HCLK_U7 DCI:NREF[1] HCLK_DCM_N:BUF.GIOB_U5
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:ENABLE 0.F0.B14
DCI:QUIET 0.F5.B12
HCLK_DCM_N:BUF.GIOB_U0 0.F3.B13
HCLK_DCM_N:BUF.GIOB_U1 0.F21.B14
HCLK_DCM_N:BUF.GIOB_U10 0.F26.B13
HCLK_DCM_N:BUF.GIOB_U11 0.F25.B14
HCLK_DCM_N:BUF.GIOB_U12 0.F25.B15
HCLK_DCM_N:BUF.GIOB_U13 0.F19.B12
HCLK_DCM_N:BUF.GIOB_U14 0.F3.B14
HCLK_DCM_N:BUF.GIOB_U15 0.F3.B15
HCLK_DCM_N:BUF.GIOB_U2 0.F22.B13
HCLK_DCM_N:BUF.GIOB_U3 0.F19.B13
HCLK_DCM_N:BUF.GIOB_U4 0.F28.B13
HCLK_DCM_N:BUF.GIOB_U5 0.F28.B12
HCLK_DCM_N:BUF.GIOB_U6 0.F25.B12
HCLK_DCM_N:BUF.GIOB_U7 0.F23.B14
HCLK_DCM_N:BUF.GIOB_U8 0.F23.B12
HCLK_DCM_N:BUF.GIOB_U9 0.F22.B12
HCLK_DCM_N:BUF.HCLK_U0 0.F21.B12
HCLK_DCM_N:BUF.HCLK_U1 0.F25.B13
HCLK_DCM_N:BUF.HCLK_U2 0.F22.B15
HCLK_DCM_N:BUF.HCLK_U3 0.F14.B15
HCLK_DCM_N:BUF.HCLK_U4 0.F19.B14
HCLK_DCM_N:BUF.HCLK_U5 0.F23.B13
HCLK_DCM_N:BUF.HCLK_U6 0.F22.B14
HCLK_DCM_N:BUF.HCLK_U7 0.F26.B12
HCLK_DCM_N:BUF.MGT_U0 0.F14.B13
HCLK_DCM_N:BUF.MGT_U1 0.F26.B14
HCLK_DCM_N:BUF.MGT_U2 0.F26.B15
HCLK_DCM_N:BUF.MGT_U3 0.F23.B15
HCLK_DCM_N:COMMON_MGT 0.F16.B12
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
DCI:LVDIV2 0.F27.B14 0.F27.B13
DCI:NREF 0.F27.B12 0.F27.B15
DCI:TEST_ENABLE 0.F5.B13 0.F0.B15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.F10.B12 0.F12.B15 0.F12.B14 0.F12.B13 0.F12.B12
DCI:PMASK_TERM_SPLIT 0.F11.B15 0.F10.B15 0.F11.B14 0.F10.B14 0.F10.B13
DCI:PMASK_TERM_VCC 0.F2.B12 0.F4.B15 0.F4.B14 0.F4.B13 0.F4.B12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.F1.B12 0.F1.B13 0.F1.B14 0.F1.B15
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
HCLK_DCM_N:COMMON 0.F21.B13 0.F19.B15 0.F14.B14
non-inverted [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_DCMIOB

Cells: 2

Bel IOCLK

virtex4 HCLK_DCMIOB bel IOCLK
PinDirectionWires

Bel HCLK_DCM_HROW

virtex4 HCLK_DCMIOB bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM_S

virtex4 HCLK_DCMIOB bel HCLK_DCM_S
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_DCMIOB bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_DCMIOB bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_DCMIOB bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputCELL0.OUT.HALF.BOT0.TMIN, CELL0.OUT.HALT.TOP0.TMIN
OUTN1outputCELL0.OUT.HALF.BOT3.TMIN, CELL0.OUT.HALT.TOP3.TMIN
OUTN65outputCELL0.OUT.HALF.BOT2.TMIN, CELL0.OUT.HALT.TOP2.TMIN
RDYoutputCELL0.OUT.HALF.BOT4.TMIN, CELL0.OUT.HALT.TOP4.TMIN
RSTinputCELL0.IMUX.BYP7
UPPULSEOUToutputCELL0.OUT.HALF.BOT1.TMIN, CELL0.OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_DCMIOB bel DCI
PinDirectionWires
DCIADDRESS0outputCELL0.OUT.HALF.BOT5.TMIN, CELL0.OUT.HALT.TOP5.TMIN
DCIADDRESS1outputCELL0.OUT.HALF.BOT6.TMIN, CELL0.OUT.HALT.TOP6.TMIN
DCIADDRESS2outputCELL0.OUT.HALF.BOT7.TMIN, CELL0.OUT.HALT.TOP7.TMIN
DCIDATAoutputCELL1.OUT.HALF.BOT7.TMIN, CELL1.OUT.HALT.TOP7.TMIN
DCIDONEoutputCELL1.OUT.HALF.BOT3.TMIN, CELL1.OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputCELL1.OUT.HALF.BOT5.TMIN, CELL1.OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputCELL1.OUT.HALF.BOT4.TMIN, CELL1.OUT.HALT.TOP4.TMIN
DCISCLKoutputCELL1.OUT.HALF.BOT6.TMIN, CELL1.OUT.HALT.TOP6.TMIN
TSTCLKinputCELL1.IMUX.BYP0
TSTHLNinputCELL1.IMUX.BYP7
TSTHLPinputCELL1.IMUX.BYP4
TSTRSTinputCELL1.IMUX.BYP2

Bel wires

virtex4 HCLK_DCMIOB bel wires
WirePins
CELL0.IMUX.BYP7IDELAYCTRL.RST
CELL0.OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
CELL0.OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
CELL0.OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
CELL0.OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
CELL0.OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
CELL0.OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
CELL0.OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
CELL0.OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
CELL0.OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
CELL0.OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
CELL0.OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
CELL0.OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
CELL0.OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
CELL0.OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
CELL0.OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
CELL0.OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
CELL1.IMUX.BYP0DCI.TSTCLK
CELL1.IMUX.BYP2DCI.TSTRST
CELL1.IMUX.BYP4DCI.TSTHLP
CELL1.IMUX.BYP7DCI.TSTHLN
CELL1.OUT.HALF.BOT3.TMINDCI.DCIDONE
CELL1.OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
CELL1.OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
CELL1.OUT.HALF.BOT6.TMINDCI.DCISCLK
CELL1.OUT.HALF.BOT7.TMINDCI.DCIDATA
CELL1.OUT.HALT.TOP3.TMINDCI.DCIDONE
CELL1.OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
CELL1.OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
CELL1.OUT.HALT.TOP6.TMINDCI.DCISCLK
CELL1.OUT.HALT.TOP7.TMINDCI.DCIDATA

Bitstream

virtex4 HCLK_DCMIOB rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28
B15 DCI:TEST_ENABLE[0] DCI:PREF[0] - HCLK_DCM_S:BUF.GIOB_D15 DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - HCLK_DCM_S:BUF.HCLK_D3 IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - HCLK_DCM_S:COMMON[1] - IOCLK:BUF.RCLK0 HCLK_DCM_S:BUF.HCLK_D2 HCLK_DCM_S:BUF.MGT_D3 IOCLK:BUF.RCLK1 HCLK_DCM_S:BUF.GIOB_D12 HCLK_DCM_S:BUF.MGT_D2 DCI:NREF[0] -
B14 DCI:ENABLE DCI:PREF[1] - HCLK_DCM_S:BUF.GIOB_D14 DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - HCLK_DCM_S:COMMON[0] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - HCLK_DCM_S:BUF.HCLK_D4 - HCLK_DCM_S:BUF.GIOB_D1 HCLK_DCM_S:BUF.HCLK_D6 HCLK_DCM_S:BUF.GIOB_D7 IDELAYCTRL:MUX.REFCLK[2] HCLK_DCM_S:BUF.GIOB_D11 HCLK_DCM_S:BUF.MGT_D1 DCI:LVDIV2[1] -
B13 - DCI:PREF[2] - HCLK_DCM_S:BUF.GIOB_D0 DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - HCLK_DCM_S:BUF.MGT_D0 IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - HCLK_DCM_S:BUF.GIOB_D3 IOCLK:VIOCLK_ENABLE[3] HCLK_DCM_S:COMMON[2] HCLK_DCM_S:BUF.GIOB_D2 HCLK_DCM_S:BUF.HCLK_D5 IDELAYCTRL:MUX.REFCLK[1] HCLK_DCM_S:BUF.HCLK_D1 HCLK_DCM_S:BUF.GIOB_D10 DCI:LVDIV2[0] HCLK_DCM_S:BUF.GIOB_D4
B12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - HCLK_DCM_S:COMMON_MGT IOCLK:BUF.IOCLK_N1 - HCLK_DCM_S:BUF.GIOB_D13 - HCLK_DCM_S:BUF.HCLK_D0 HCLK_DCM_S:BUF.GIOB_D9 HCLK_DCM_S:BUF.GIOB_D8 IDELAYCTRL:MUX.REFCLK[0] HCLK_DCM_S:BUF.GIOB_D6 HCLK_DCM_S:BUF.HCLK_D7 DCI:NREF[1] HCLK_DCM_S:BUF.GIOB_D5
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:ENABLE 0.F0.B14
DCI:QUIET 0.F5.B12
HCLK_DCM_S:BUF.GIOB_D0 0.F3.B13
HCLK_DCM_S:BUF.GIOB_D1 0.F21.B14
HCLK_DCM_S:BUF.GIOB_D10 0.F26.B13
HCLK_DCM_S:BUF.GIOB_D11 0.F25.B14
HCLK_DCM_S:BUF.GIOB_D12 0.F25.B15
HCLK_DCM_S:BUF.GIOB_D13 0.F19.B12
HCLK_DCM_S:BUF.GIOB_D14 0.F3.B14
HCLK_DCM_S:BUF.GIOB_D15 0.F3.B15
HCLK_DCM_S:BUF.GIOB_D2 0.F22.B13
HCLK_DCM_S:BUF.GIOB_D3 0.F19.B13
HCLK_DCM_S:BUF.GIOB_D4 0.F28.B13
HCLK_DCM_S:BUF.GIOB_D5 0.F28.B12
HCLK_DCM_S:BUF.GIOB_D6 0.F25.B12
HCLK_DCM_S:BUF.GIOB_D7 0.F23.B14
HCLK_DCM_S:BUF.GIOB_D8 0.F23.B12
HCLK_DCM_S:BUF.GIOB_D9 0.F22.B12
HCLK_DCM_S:BUF.HCLK_D0 0.F21.B12
HCLK_DCM_S:BUF.HCLK_D1 0.F25.B13
HCLK_DCM_S:BUF.HCLK_D2 0.F22.B15
HCLK_DCM_S:BUF.HCLK_D3 0.F14.B15
HCLK_DCM_S:BUF.HCLK_D4 0.F19.B14
HCLK_DCM_S:BUF.HCLK_D5 0.F23.B13
HCLK_DCM_S:BUF.HCLK_D6 0.F22.B14
HCLK_DCM_S:BUF.HCLK_D7 0.F26.B12
HCLK_DCM_S:BUF.MGT_D0 0.F14.B13
HCLK_DCM_S:BUF.MGT_D1 0.F26.B14
HCLK_DCM_S:BUF.MGT_D2 0.F26.B15
HCLK_DCM_S:BUF.MGT_D3 0.F23.B15
HCLK_DCM_S:COMMON_MGT 0.F16.B12
IDELAYCTRL:ENABLE 0.F11.B12
IOCLK:BUF.HCLK0 0.F7.B12
IOCLK:BUF.HCLK1 0.F7.B13
IOCLK:BUF.HCLK2 0.F7.B14
IOCLK:BUF.HCLK3 0.F7.B15
IOCLK:BUF.HCLK4 0.F8.B12
IOCLK:BUF.HCLK5 0.F8.B13
IOCLK:BUF.HCLK6 0.F8.B14
IOCLK:BUF.HCLK7 0.F8.B15
IOCLK:BUF.IOCLK_N0 0.F17.B15
IOCLK:BUF.IOCLK_N1 0.F17.B12
IOCLK:BUF.IOCLK_S0 0.F17.B14
IOCLK:BUF.IOCLK_S1 0.F17.B13
IOCLK:BUF.RCLK0 0.F21.B15
IOCLK:BUF.RCLK1 0.F24.B15
IOCLK:BUF.VIOCLK0 0.F16.B14
IOCLK:BUF.VIOCLK1 0.F16.B15
non-inverted [0]
DCI:LVDIV2 0.F27.B14 0.F27.B13
DCI:NREF 0.F27.B12 0.F27.B15
DCI:TEST_ENABLE 0.F5.B13 0.F0.B15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.F10.B12 0.F12.B15 0.F12.B14 0.F12.B13 0.F12.B12
DCI:PMASK_TERM_SPLIT 0.F11.B15 0.F10.B15 0.F11.B14 0.F10.B14 0.F10.B13
DCI:PMASK_TERM_VCC 0.F2.B12 0.F4.B15 0.F4.B14 0.F4.B13 0.F4.B12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.F1.B12 0.F1.B13 0.F1.B14 0.F1.B15
IOCLK:VIOCLK_ENABLE 0.F20.B13 0.F15.B15 0.F15.B14 0.F15.B13
non-inverted [3] [2] [1] [0]
HCLK_DCM_S:COMMON 0.F21.B13 0.F19.B15 0.F14.B14
non-inverted [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.F24.B14 0.F24.B13 0.F24.B12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_DCM

Cells: 0

Bel HCLK_DCM_HROW

virtex4 HCLK_DCM bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM

virtex4 HCLK_DCM bel HCLK_DCM
PinDirectionWires

Bitstream

virtex4 HCLK_DCM rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27
B15 - - - HCLK_DCM:BUF.GIOB_D11 - HCLK_DCM:BUF.MGT_U1 - - - - HCLK_DCM:BUF.MGT_U0 HCLK_DCM:BUF.MGT_U2 HCLK_DCM:BUF.MGT_D0 - HCLK_DCM:BUF.HCLK_U2 - HCLK_DCM:BUF.MGT_U3 HCLK_DCM:BUF.GIOB_U0 - - HCLK_DCM:BUF.GIOB_D4 HCLK_DCM:BUF.HCLK_D3 HCLK_DCM:BUF.HCLK_D7 HCLK_DCM:BUF.GIOB_D2 HCLK_DCM:BUF.HCLK_D1 HCLK_DCM:BUF.GIOB_U5 HCLK_DCM:BUF.GIOB_U7 HCLK_DCM:COMMON
B14 - - - HCLK_DCM:BUF.MGT_D3 - HCLK_DCM:BUF.GIOB_U9 - - - - HCLK_DCM:BUF.GIOB_U12 HCLK_DCM:BUF.GIOB_U14 HCLK_DCM:BUF.GIOB_D8 - HCLK_DCM:BUF.HCLK_U6 - HCLK_DCM:BUF.GIOB_U11 HCLK_DCM:BUF.HCLK_U0 - - HCLK_DCM:BUF.GIOB_D0 - HCLK_DCM:BUF.GIOB_D7 HCLK_DCM:BUF.HCLK_D6 HCLK_DCM:BUF.HCLK_D5 HCLK_DCM:BUF.GIOB_U1 HCLK_DCM:BUF.HCLK_U3 HCLK_DCM:COMMON_MGT
B13 - - - HCLK_DCM:BUF.GIOB_D10 - HCLK_DCM:BUF.GIOB_U13 - - - - HCLK_DCM:BUF.GIOB_D12 HCLK_DCM:BUF.GIOB_D14 HCLK_DCM:BUF.MGT_D1 - HCLK_DCM:BUF.GIOB_U2 - HCLK_DCM:BUF.GIOB_U15 HCLK_DCM:BUF.HCLK_U4 - - HCLK_DCM:BUF.HCLK_D4 - HCLK_DCM:BUF.GIOB_D3 HCLK_DCM:BUF.HCLK_D2 HCLK_DCM:BUF.GIOB_D5 HCLK_DCM:BUF.HCLK_U5 HCLK_DCM:BUF.HCLK_U7 HCLK_DCM:COMMON_HCLK_GIOB[2]
B12 - - - HCLK_DCM:BUF.MGT_D2 - HCLK_DCM:BUF.GIOB_U8 - - - - HCLK_DCM:BUF.GIOB_D13 HCLK_DCM:BUF.GIOB_D15 HCLK_DCM:BUF.GIOB_D9 - HCLK_DCM:BUF.GIOB_U6 - HCLK_DCM:BUF.GIOB_U10 HCLK_DCM:BUF.GIOB_U4 - HCLK_DCM:COMMON_HCLK_GIOB[0] HCLK_DCM:BUF.HCLK_D0 HCLK_DCM:COMMON_HCLK_GIOB[1] HCLK_DCM:BUF.GIOB_D6 - HCLK_DCM:BUF.GIOB_D1 HCLK_DCM:BUF.HCLK_U1 HCLK_DCM:BUF.GIOB_U3 -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HCLK_DCM:BUF.GIOB_D0 0.F20.B14
HCLK_DCM:BUF.GIOB_D1 0.F24.B12
HCLK_DCM:BUF.GIOB_D10 0.F3.B13
HCLK_DCM:BUF.GIOB_D11 0.F3.B15
HCLK_DCM:BUF.GIOB_D12 0.F10.B13
HCLK_DCM:BUF.GIOB_D13 0.F10.B12
HCLK_DCM:BUF.GIOB_D14 0.F11.B13
HCLK_DCM:BUF.GIOB_D15 0.F11.B12
HCLK_DCM:BUF.GIOB_D2 0.F23.B15
HCLK_DCM:BUF.GIOB_D3 0.F22.B13
HCLK_DCM:BUF.GIOB_D4 0.F20.B15
HCLK_DCM:BUF.GIOB_D5 0.F24.B13
HCLK_DCM:BUF.GIOB_D6 0.F22.B12
HCLK_DCM:BUF.GIOB_D7 0.F22.B14
HCLK_DCM:BUF.GIOB_D8 0.F12.B14
HCLK_DCM:BUF.GIOB_D9 0.F12.B12
HCLK_DCM:BUF.GIOB_U0 0.F17.B15
HCLK_DCM:BUF.GIOB_U1 0.F25.B14
HCLK_DCM:BUF.GIOB_U10 0.F16.B12
HCLK_DCM:BUF.GIOB_U11 0.F16.B14
HCLK_DCM:BUF.GIOB_U12 0.F10.B14
HCLK_DCM:BUF.GIOB_U13 0.F5.B13
HCLK_DCM:BUF.GIOB_U14 0.F11.B14
HCLK_DCM:BUF.GIOB_U15 0.F16.B13
HCLK_DCM:BUF.GIOB_U2 0.F14.B13
HCLK_DCM:BUF.GIOB_U3 0.F26.B12
HCLK_DCM:BUF.GIOB_U4 0.F17.B12
HCLK_DCM:BUF.GIOB_U5 0.F25.B15
HCLK_DCM:BUF.GIOB_U6 0.F14.B12
HCLK_DCM:BUF.GIOB_U7 0.F26.B15
HCLK_DCM:BUF.GIOB_U8 0.F5.B12
HCLK_DCM:BUF.GIOB_U9 0.F5.B14
HCLK_DCM:BUF.HCLK_D0 0.F20.B12
HCLK_DCM:BUF.HCLK_D1 0.F24.B15
HCLK_DCM:BUF.HCLK_D2 0.F23.B13
HCLK_DCM:BUF.HCLK_D3 0.F21.B15
HCLK_DCM:BUF.HCLK_D4 0.F20.B13
HCLK_DCM:BUF.HCLK_D5 0.F24.B14
HCLK_DCM:BUF.HCLK_D6 0.F23.B14
HCLK_DCM:BUF.HCLK_D7 0.F22.B15
HCLK_DCM:BUF.HCLK_U0 0.F17.B14
HCLK_DCM:BUF.HCLK_U1 0.F25.B12
HCLK_DCM:BUF.HCLK_U2 0.F14.B15
HCLK_DCM:BUF.HCLK_U3 0.F26.B14
HCLK_DCM:BUF.HCLK_U4 0.F17.B13
HCLK_DCM:BUF.HCLK_U5 0.F25.B13
HCLK_DCM:BUF.HCLK_U6 0.F14.B14
HCLK_DCM:BUF.HCLK_U7 0.F26.B13
HCLK_DCM:BUF.MGT_D0 0.F12.B15
HCLK_DCM:BUF.MGT_D1 0.F12.B13
HCLK_DCM:BUF.MGT_D2 0.F3.B12
HCLK_DCM:BUF.MGT_D3 0.F3.B14
HCLK_DCM:BUF.MGT_U0 0.F10.B15
HCLK_DCM:BUF.MGT_U1 0.F5.B15
HCLK_DCM:BUF.MGT_U2 0.F11.B15
HCLK_DCM:BUF.MGT_U3 0.F16.B15
HCLK_DCM:COMMON 0.F27.B15
HCLK_DCM:COMMON_MGT 0.F27.B14
non-inverted [0]
HCLK_DCM:COMMON_HCLK_GIOB 0.F27.B13 0.F21.B12 0.F19.B12
non-inverted [2] [1] [0]