Clock I/O and DCM buffers
Tile HCLK_IO_LVDS
Cells: 4
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| Bits | Destination | |||
|---|---|---|---|---|
| MAIN[25][14] | MAIN[25][12] | MAIN[25][13] | MAIN[25][15] | CELL[2].RCLK_ROW[0] |
| Source | ||||
| 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 1 | CELL[2].VRCLK_N[0] |
| 0 | 0 | 1 | 1 | CELL[2].VRCLK[0] |
| 0 | 1 | 0 | 1 | CELL[2].VRCLK_N[1] |
| 0 | 1 | 1 | 1 | CELL[2].VRCLK[1] |
| 1 | 0 | 0 | 1 | CELL[2].VRCLK_S[0] |
| 1 | 1 | 0 | 1 | CELL[2].VRCLK_S[1] |
| Bits | Destination | |||
|---|---|---|---|---|
| MAIN[23][14] | MAIN[23][12] | MAIN[23][13] | MAIN[23][15] | CELL[2].RCLK_ROW[1] |
| Source | ||||
| 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 1 | CELL[2].VRCLK_N[0] |
| 0 | 0 | 1 | 1 | CELL[2].VRCLK[0] |
| 0 | 1 | 0 | 1 | CELL[2].VRCLK_N[1] |
| 0 | 1 | 1 | 1 | CELL[2].VRCLK[1] |
| 1 | 0 | 0 | 1 | CELL[2].VRCLK_S[0] |
| 1 | 1 | 0 | 1 | CELL[2].VRCLK_S[1] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bits | Destination | |
|---|---|---|
| MAIN[19][15] | MAIN[19][14] | CELL[2].IMUX_BUFR[0] |
| Source | ||
| 0 | 0 | CELL[2].OUT_CLKPAD |
| 0 | 1 | CELL[1].IMUX_BYP[4] |
| 1 | 0 | CELL[2].IMUX_BYP[4] |
| 1 | 1 | CELL[1].OUT_CLKPAD |
| Bits | Destination | |
|---|---|---|
| MAIN[19][12] | MAIN[19][13] | CELL[2].IMUX_BUFR[1] |
| Source | ||
| 0 | 0 | CELL[2].OUT_CLKPAD |
| 0 | 1 | CELL[1].IMUX_BYP[4] |
| 1 | 0 | CELL[2].IMUX_BYP[4] |
| 1 | 1 | CELL[1].OUT_CLKPAD |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
Bels BUFR
| Pin | Direction | BUFR[0] | BUFR[1] |
|---|---|---|---|
| I | in | CELL[2].IMUX_BUFR[0] | CELL[2].IMUX_BUFR[1] |
| CE | in | CELL[2].IMUX_BYP[0] | CELL[1].IMUX_BYP[0] |
| CLR | in | CELL[2].IMUX_BYP[2] | CELL[1].IMUX_BYP[2] |
| O | out | CELL[2].VRCLK[0] | CELL[2].VRCLK[1] |
| Attribute | BUFR[0] | BUFR[1] |
|---|---|---|
| ENABLE | MAIN[21][14] | MAIN[21][13] |
| DIVIDE | [enum: BUFR_DIVIDE] | [enum: BUFR_DIVIDE] |
| BUFR[0].DIVIDE | MAIN[14][14] | MAIN[14][13] | MAIN[14][12] | MAIN[14][15] |
|---|---|---|---|---|
| BUFR[1].DIVIDE | MAIN[22][14] | MAIN[22][13] | MAIN[22][12] | MAIN[22][15] |
| BYPASS | 0 | 0 | 0 | 0 |
| _1 | 0 | 0 | 0 | 1 |
| _2 | 0 | 0 | 1 | 1 |
| _3 | 0 | 1 | 0 | 1 |
| _4 | 0 | 1 | 1 | 1 |
| _5 | 1 | 0 | 0 | 1 |
| _6 | 1 | 0 | 1 | 1 |
| _7 | 1 | 1 | 0 | 1 |
| _8 | 1 | 1 | 1 | 1 |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[1].IMUX_BYP[7] |
| RDY | out | CELL[1].OUT_HALF0_BEL[4], CELL[1].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[1].OUT_HALF0_BEL[0], CELL[1].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[1].OUT_HALF0_BEL[1], CELL[1].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[1].OUT_HALF0_BEL[3], CELL[1].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[1].OUT_HALF0_BEL[2], CELL[1].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels LVDS_V4
| Pin | Direction | LVDS |
|---|
| Attribute | LVDS |
|---|---|
| LVDSBIAS bit 0 | MAIN[5][12] |
| LVDSBIAS bit 1 | MAIN[5][14] |
| LVDSBIAS bit 2 | MAIN[3][15] |
| LVDSBIAS bit 3 | MAIN[2][13] |
| LVDSBIAS bit 4 | MAIN[3][14] |
| LVDSBIAS bit 5 | MAIN[3][13] |
| LVDSBIAS bit 6 | MAIN[5][15] |
| LVDSBIAS bit 7 | MAIN[2][14] |
| LVDSBIAS bit 8 | MAIN[11][13] |
| LVDSBIAS bit 9 | MAIN[3][12] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[1].IMUX_BYP[0] | BUFR[1].CE |
| CELL[1].IMUX_BYP[2] | BUFR[1].CLR |
| CELL[1].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[1].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].IMUX_BYP[0] | BUFR[0].CE |
| CELL[2].IMUX_BYP[2] | BUFR[0].CLR |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IMUX_BUFR[0] | BUFR[0].I |
| CELL[2].IMUX_BUFR[1] | BUFR[1].I |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
| CELL[2].VRCLK[0] | BUFR[0].O |
| CELL[2].VRCLK[1] | BUFR[1].O |
Bitstream
Tile HCLK_IO_DCI
Cells: 4
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| Bits | Destination | |||
|---|---|---|---|---|
| MAIN[25][14] | MAIN[25][12] | MAIN[25][13] | MAIN[25][15] | CELL[2].RCLK_ROW[0] |
| Source | ||||
| 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 1 | CELL[2].VRCLK_N[0] |
| 0 | 0 | 1 | 1 | CELL[2].VRCLK[0] |
| 0 | 1 | 0 | 1 | CELL[2].VRCLK_N[1] |
| 0 | 1 | 1 | 1 | CELL[2].VRCLK[1] |
| 1 | 0 | 0 | 1 | CELL[2].VRCLK_S[0] |
| 1 | 1 | 0 | 1 | CELL[2].VRCLK_S[1] |
| Bits | Destination | |||
|---|---|---|---|---|
| MAIN[23][14] | MAIN[23][12] | MAIN[23][13] | MAIN[23][15] | CELL[2].RCLK_ROW[1] |
| Source | ||||
| 0 | 0 | 0 | 0 | off |
| 0 | 0 | 0 | 1 | CELL[2].VRCLK_N[0] |
| 0 | 0 | 1 | 1 | CELL[2].VRCLK[0] |
| 0 | 1 | 0 | 1 | CELL[2].VRCLK_N[1] |
| 0 | 1 | 1 | 1 | CELL[2].VRCLK[1] |
| 1 | 0 | 0 | 1 | CELL[2].VRCLK_S[0] |
| 1 | 1 | 0 | 1 | CELL[2].VRCLK_S[1] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bits | Destination | |
|---|---|---|
| MAIN[19][15] | MAIN[19][14] | CELL[2].IMUX_BUFR[0] |
| Source | ||
| 0 | 0 | CELL[2].OUT_CLKPAD |
| 0 | 1 | CELL[1].IMUX_BYP[4] |
| 1 | 0 | CELL[2].IMUX_BYP[4] |
| 1 | 1 | CELL[1].OUT_CLKPAD |
| Bits | Destination | |
|---|---|---|
| MAIN[19][12] | MAIN[19][13] | CELL[2].IMUX_BUFR[1] |
| Source | ||
| 0 | 0 | CELL[2].OUT_CLKPAD |
| 0 | 1 | CELL[1].IMUX_BYP[4] |
| 1 | 0 | CELL[2].IMUX_BYP[4] |
| 1 | 1 | CELL[1].OUT_CLKPAD |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
Bels BUFR
| Pin | Direction | BUFR[0] | BUFR[1] |
|---|---|---|---|
| I | in | CELL[2].IMUX_BUFR[0] | CELL[2].IMUX_BUFR[1] |
| CE | in | CELL[2].IMUX_BYP[0] | CELL[1].IMUX_BYP[0] |
| CLR | in | CELL[2].IMUX_BYP[2] | CELL[1].IMUX_BYP[2] |
| O | out | CELL[2].VRCLK[0] | CELL[2].VRCLK[1] |
| Attribute | BUFR[0] | BUFR[1] |
|---|---|---|
| ENABLE | MAIN[21][14] | MAIN[21][13] |
| DIVIDE | [enum: BUFR_DIVIDE] | [enum: BUFR_DIVIDE] |
| BUFR[0].DIVIDE | MAIN[14][14] | MAIN[14][13] | MAIN[14][12] | MAIN[14][15] |
|---|---|---|---|---|
| BUFR[1].DIVIDE | MAIN[22][14] | MAIN[22][13] | MAIN[22][12] | MAIN[22][15] |
| BYPASS | 0 | 0 | 0 | 0 |
| _1 | 0 | 0 | 0 | 1 |
| _2 | 0 | 0 | 1 | 1 |
| _3 | 0 | 1 | 0 | 1 |
| _4 | 0 | 1 | 1 | 1 |
| _5 | 1 | 0 | 0 | 1 |
| _6 | 1 | 0 | 1 | 1 |
| _7 | 1 | 1 | 0 | 1 |
| _8 | 1 | 1 | 1 | 1 |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[1].IMUX_BYP[7] |
| RDY | out | CELL[1].OUT_HALF0_BEL[4], CELL[1].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[1].OUT_HALF0_BEL[0], CELL[1].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[1].OUT_HALF0_BEL[1], CELL[1].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[1].OUT_HALF0_BEL[3], CELL[1].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[1].OUT_HALF0_BEL[2], CELL[1].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels DCI
| Pin | Direction | DCI |
|---|---|---|
| TSTCLK | in | CELL[0].IMUX_BYP[0] |
| TSTRST | in | CELL[0].IMUX_BYP[2] |
| TSTHLP | in | CELL[0].IMUX_BYP[7] |
| TSTHLN | in | CELL[0].IMUX_BYP[4] |
| DCISCLK | out | CELL[0].OUT_HALF0_BEL[6], CELL[0].OUT_HALF1_BEL[6] |
| DCIADDRESS[0] | out | CELL[1].OUT_HALF0_BEL[5], CELL[1].OUT_HALF1_BEL[5] |
| DCIADDRESS[1] | out | CELL[1].OUT_HALF0_BEL[6], CELL[1].OUT_HALF1_BEL[6] |
| DCIADDRESS[2] | out | CELL[1].OUT_HALF0_BEL[7], CELL[1].OUT_HALF1_BEL[7] |
| DCIDATA | out | CELL[0].OUT_HALF0_BEL[7], CELL[0].OUT_HALF1_BEL[7] |
| DCIIOUPDATE | out | CELL[0].OUT_HALF0_BEL[5], CELL[0].OUT_HALF1_BEL[5] |
| DCIREFIOUPDATE | out | CELL[0].OUT_HALF0_BEL[4], CELL[0].OUT_HALF1_BEL[4] |
| DCIDONE | out | CELL[0].OUT_HALF0_BEL[3], CELL[0].OUT_HALF1_BEL[3] |
| Attribute | DCI |
|---|---|
| ENABLE | MAIN[0][14] |
| QUIET | MAIN[5][12] |
| V4_LVDIV2 bit 0 | MAIN[27][13] |
| V4_LVDIV2 bit 1 | MAIN[27][14] |
| V4_PMASK_TERM_VCC bit 0 | MAIN[4][12] |
| V4_PMASK_TERM_VCC bit 1 | MAIN[4][13] |
| V4_PMASK_TERM_VCC bit 2 | MAIN[4][14] |
| V4_PMASK_TERM_VCC bit 3 | MAIN[4][15] |
| V4_PMASK_TERM_VCC bit 4 | MAIN[2][12] |
| V4_PMASK_TERM_SPLIT bit 0 | MAIN[10][13] |
| V4_PMASK_TERM_SPLIT bit 1 | MAIN[10][14] |
| V4_PMASK_TERM_SPLIT bit 2 | MAIN[11][14] |
| V4_PMASK_TERM_SPLIT bit 3 | MAIN[10][15] |
| V4_PMASK_TERM_SPLIT bit 4 | MAIN[11][15] |
| V4_NMASK_TERM_SPLIT bit 0 | MAIN[12][12] |
| V4_NMASK_TERM_SPLIT bit 1 | MAIN[12][13] |
| V4_NMASK_TERM_SPLIT bit 2 | MAIN[12][14] |
| V4_NMASK_TERM_SPLIT bit 3 | MAIN[12][15] |
| V4_NMASK_TERM_SPLIT bit 4 | MAIN[10][12] |
| NREF bit 0 | MAIN[27][15] |
| NREF bit 1 | MAIN[27][12] |
| PREF bit 0 | MAIN[1][15] |
| PREF bit 1 | MAIN[1][14] |
| PREF bit 2 | MAIN[1][13] |
| PREF bit 3 | MAIN[1][12] |
| TEST_ENABLE bit 0 | MAIN[0][15] |
| TEST_ENABLE bit 1 | MAIN[5][13] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[0].IMUX_BYP[0] | DCI.TSTCLK |
| CELL[0].IMUX_BYP[2] | DCI.TSTRST |
| CELL[0].IMUX_BYP[4] | DCI.TSTHLN |
| CELL[0].IMUX_BYP[7] | DCI.TSTHLP |
| CELL[0].OUT_HALF0_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF0_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF0_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF0_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF0_BEL[7] | DCI.DCIDATA |
| CELL[0].OUT_HALF1_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF1_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF1_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF1_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF1_BEL[7] | DCI.DCIDATA |
| CELL[1].IMUX_BYP[0] | BUFR[1].CE |
| CELL[1].IMUX_BYP[2] | BUFR[1].CLR |
| CELL[1].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[1].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF0_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF0_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF0_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF1_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF1_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF1_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].IMUX_BYP[0] | BUFR[0].CE |
| CELL[2].IMUX_BYP[2] | BUFR[0].CLR |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IMUX_BUFR[0] | BUFR[0].I |
| CELL[2].IMUX_BUFR[1] | BUFR[1].I |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
| CELL[2].VRCLK[0] | BUFR[0].O |
| CELL[2].VRCLK[1] | BUFR[1].O |
Bitstream
Tile HCLK_IO_CENTER
Cells: 4
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[1].IMUX_BYP[7] |
| RDY | out | CELL[1].OUT_HALF0_BEL[4], CELL[1].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[1].OUT_HALF0_BEL[0], CELL[1].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[1].OUT_HALF0_BEL[1], CELL[1].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[1].OUT_HALF0_BEL[3], CELL[1].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[1].OUT_HALF0_BEL[2], CELL[1].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels DCI
| Pin | Direction | DCI |
|---|---|---|
| TSTCLK | in | CELL[0].IMUX_BYP[0] |
| TSTRST | in | CELL[0].IMUX_BYP[2] |
| TSTHLP | in | CELL[0].IMUX_BYP[7] |
| TSTHLN | in | CELL[0].IMUX_BYP[4] |
| DCISCLK | out | CELL[0].OUT_HALF0_BEL[6], CELL[0].OUT_HALF1_BEL[6] |
| DCIADDRESS[0] | out | CELL[1].OUT_HALF0_BEL[5], CELL[1].OUT_HALF1_BEL[5] |
| DCIADDRESS[1] | out | CELL[1].OUT_HALF0_BEL[6], CELL[1].OUT_HALF1_BEL[6] |
| DCIADDRESS[2] | out | CELL[1].OUT_HALF0_BEL[7], CELL[1].OUT_HALF1_BEL[7] |
| DCIDATA | out | CELL[0].OUT_HALF0_BEL[7], CELL[0].OUT_HALF1_BEL[7] |
| DCIIOUPDATE | out | CELL[0].OUT_HALF0_BEL[5], CELL[0].OUT_HALF1_BEL[5] |
| DCIREFIOUPDATE | out | CELL[0].OUT_HALF0_BEL[4], CELL[0].OUT_HALF1_BEL[4] |
| DCIDONE | out | CELL[0].OUT_HALF0_BEL[3], CELL[0].OUT_HALF1_BEL[3] |
| Attribute | DCI |
|---|---|
| ENABLE | MAIN[0][14] |
| QUIET | MAIN[5][12] |
| V4_LVDIV2 bit 0 | MAIN[27][13] |
| V4_LVDIV2 bit 1 | MAIN[27][14] |
| V4_PMASK_TERM_VCC bit 0 | MAIN[4][12] |
| V4_PMASK_TERM_VCC bit 1 | MAIN[4][13] |
| V4_PMASK_TERM_VCC bit 2 | MAIN[4][14] |
| V4_PMASK_TERM_VCC bit 3 | MAIN[4][15] |
| V4_PMASK_TERM_VCC bit 4 | MAIN[2][12] |
| V4_PMASK_TERM_SPLIT bit 0 | MAIN[10][13] |
| V4_PMASK_TERM_SPLIT bit 1 | MAIN[10][14] |
| V4_PMASK_TERM_SPLIT bit 2 | MAIN[11][14] |
| V4_PMASK_TERM_SPLIT bit 3 | MAIN[10][15] |
| V4_PMASK_TERM_SPLIT bit 4 | MAIN[11][15] |
| V4_NMASK_TERM_SPLIT bit 0 | MAIN[12][12] |
| V4_NMASK_TERM_SPLIT bit 1 | MAIN[12][13] |
| V4_NMASK_TERM_SPLIT bit 2 | MAIN[12][14] |
| V4_NMASK_TERM_SPLIT bit 3 | MAIN[12][15] |
| V4_NMASK_TERM_SPLIT bit 4 | MAIN[10][12] |
| NREF bit 0 | MAIN[27][15] |
| NREF bit 1 | MAIN[27][12] |
| PREF bit 0 | MAIN[1][15] |
| PREF bit 1 | MAIN[1][14] |
| PREF bit 2 | MAIN[1][13] |
| PREF bit 3 | MAIN[1][12] |
| TEST_ENABLE bit 0 | MAIN[0][15] |
| TEST_ENABLE bit 1 | MAIN[5][13] |
| CASCADE_FROM_ABOVE | MAIN[0][13] |
| CASCADE_FROM_BELOW | MAIN[0][12] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[0].IMUX_BYP[0] | DCI.TSTCLK |
| CELL[0].IMUX_BYP[2] | DCI.TSTRST |
| CELL[0].IMUX_BYP[4] | DCI.TSTHLN |
| CELL[0].IMUX_BYP[7] | DCI.TSTHLP |
| CELL[0].OUT_HALF0_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF0_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF0_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF0_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF0_BEL[7] | DCI.DCIDATA |
| CELL[0].OUT_HALF1_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF1_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF1_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF1_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF1_BEL[7] | DCI.DCIDATA |
| CELL[1].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[1].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF0_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF0_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF0_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF1_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF1_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF1_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | DCI: TEST_ENABLE bit 0 | DCI: PREF bit 0 | - | - | DCI: V4_PMASK_TERM_VCC bit 3 | - | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7] | - | DCI: V4_PMASK_TERM_SPLIT bit 3 | DCI: V4_PMASK_TERM_SPLIT bit 4 | DCI: V4_NMASK_TERM_SPLIT bit 3 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 2 | BUFIO[1]: ENABLE | HCLK_IO_INT: buffer CELL[2].IOCLK_N_IO[0] ← CELL[2].IOCLK_N[0] | - | - | - | HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0] | - | - | HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1] | - | - | DCI: NREF bit 0 | - | - |
| B14 | DCI: ENABLE | DCI: PREF bit 1 | - | - | DCI: V4_PMASK_TERM_VCC bit 2 | - | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6] | - | DCI: V4_PMASK_TERM_SPLIT bit 1 | DCI: V4_PMASK_TERM_SPLIT bit 2 | DCI: V4_NMASK_TERM_SPLIT bit 2 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 1 | BUFIO[0]: ENABLE | HCLK_IO_INT: buffer CELL[2].IOCLK_S_IO[0] ← CELL[2].IOCLK_S[0] | - | - | - | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2 | - | - | DCI: V4_LVDIV2 bit 1 | - | - |
| B13 | DCI: CASCADE_FROM_ABOVE | DCI: PREF bit 2 | - | - | DCI: V4_PMASK_TERM_VCC bit 1 | DCI: TEST_ENABLE bit 1 | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5] | - | DCI: V4_PMASK_TERM_SPLIT bit 0 | - | DCI: V4_NMASK_TERM_SPLIT bit 1 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 0 | - | HCLK_IO_INT: buffer CELL[2].IOCLK_S_IO[1] ← CELL[2].IOCLK_S[1] | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 3 | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1 | - | - | DCI: V4_LVDIV2 bit 0 | - | - |
| B12 | DCI: CASCADE_FROM_BELOW | DCI: PREF bit 3 | DCI: V4_PMASK_TERM_VCC bit 4 | - | DCI: V4_PMASK_TERM_VCC bit 0 | DCI: QUIET | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4] | - | DCI: V4_NMASK_TERM_SPLIT bit 4 | IDELAYCTRL: DLL_ENABLE | DCI: V4_NMASK_TERM_SPLIT bit 0 | - | - | - | - | HCLK_IO_INT: buffer CELL[2].IOCLK_N_IO[1] ← CELL[2].IOCLK_N[1] | - | - | - | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0 | - | - | DCI: NREF bit 1 | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
Tile HCLK_IO_CFG_N
Cells: 4
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[2].IMUX_BYP[7] |
| RDY | out | CELL[2].OUT_HALF0_BEL[4], CELL[2].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[2].OUT_HALF0_BEL[0], CELL[2].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[2].OUT_HALF0_BEL[1], CELL[2].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[2].OUT_HALF0_BEL[3], CELL[2].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[2].OUT_HALF0_BEL[2], CELL[2].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels DCI
| Pin | Direction | DCI |
|---|---|---|
| TSTCLK | in | CELL[3].IMUX_BYP[0] |
| TSTRST | in | CELL[3].IMUX_BYP[2] |
| TSTHLP | in | CELL[3].IMUX_BYP[4] |
| TSTHLN | in | CELL[3].IMUX_BYP[7] |
| DCISCLK | out | CELL[3].OUT_HALF0_BEL[6], CELL[3].OUT_HALF1_BEL[6] |
| DCIADDRESS[0] | out | CELL[2].OUT_HALF0_BEL[5], CELL[2].OUT_HALF1_BEL[5] |
| DCIADDRESS[1] | out | CELL[2].OUT_HALF0_BEL[6], CELL[2].OUT_HALF1_BEL[6] |
| DCIADDRESS[2] | out | CELL[2].OUT_HALF0_BEL[7], CELL[2].OUT_HALF1_BEL[7] |
| DCIDATA | out | CELL[3].OUT_HALF0_BEL[7], CELL[3].OUT_HALF1_BEL[7] |
| DCIIOUPDATE | out | CELL[3].OUT_HALF0_BEL[5], CELL[3].OUT_HALF1_BEL[5] |
| DCIREFIOUPDATE | out | CELL[3].OUT_HALF0_BEL[4], CELL[3].OUT_HALF1_BEL[4] |
| DCIDONE | out | CELL[3].OUT_HALF0_BEL[3], CELL[3].OUT_HALF1_BEL[3] |
| Attribute | DCI |
|---|---|
| ENABLE | MAIN[0][14] |
| QUIET | MAIN[5][12] |
| V4_LVDIV2 bit 0 | MAIN[27][13] |
| V4_LVDIV2 bit 1 | MAIN[27][14] |
| V4_PMASK_TERM_VCC bit 0 | MAIN[4][12] |
| V4_PMASK_TERM_VCC bit 1 | MAIN[4][13] |
| V4_PMASK_TERM_VCC bit 2 | MAIN[4][14] |
| V4_PMASK_TERM_VCC bit 3 | MAIN[4][15] |
| V4_PMASK_TERM_VCC bit 4 | MAIN[2][12] |
| V4_PMASK_TERM_SPLIT bit 0 | MAIN[10][13] |
| V4_PMASK_TERM_SPLIT bit 1 | MAIN[10][14] |
| V4_PMASK_TERM_SPLIT bit 2 | MAIN[11][14] |
| V4_PMASK_TERM_SPLIT bit 3 | MAIN[10][15] |
| V4_PMASK_TERM_SPLIT bit 4 | MAIN[11][15] |
| V4_NMASK_TERM_SPLIT bit 0 | MAIN[12][12] |
| V4_NMASK_TERM_SPLIT bit 1 | MAIN[12][13] |
| V4_NMASK_TERM_SPLIT bit 2 | MAIN[12][14] |
| V4_NMASK_TERM_SPLIT bit 3 | MAIN[12][15] |
| V4_NMASK_TERM_SPLIT bit 4 | MAIN[10][12] |
| NREF bit 0 | MAIN[27][15] |
| NREF bit 1 | MAIN[27][12] |
| PREF bit 0 | MAIN[1][15] |
| PREF bit 1 | MAIN[1][14] |
| PREF bit 2 | MAIN[1][13] |
| PREF bit 3 | MAIN[1][12] |
| TEST_ENABLE bit 0 | MAIN[0][15] |
| TEST_ENABLE bit 1 | MAIN[5][13] |
| CASCADE_FROM_ABOVE | MAIN[0][13] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[2].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[2].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[2].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[2].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[2].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[2].OUT_HALF0_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[2].OUT_HALF0_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[2].OUT_HALF0_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[2].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[2].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[2].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[2].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[2].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[2].OUT_HALF1_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[2].OUT_HALF1_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[2].OUT_HALF1_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
| CELL[3].IMUX_BYP[0] | DCI.TSTCLK |
| CELL[3].IMUX_BYP[2] | DCI.TSTRST |
| CELL[3].IMUX_BYP[4] | DCI.TSTHLP |
| CELL[3].IMUX_BYP[7] | DCI.TSTHLN |
| CELL[3].OUT_HALF0_BEL[3] | DCI.DCIDONE |
| CELL[3].OUT_HALF0_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[3].OUT_HALF0_BEL[5] | DCI.DCIIOUPDATE |
| CELL[3].OUT_HALF0_BEL[6] | DCI.DCISCLK |
| CELL[3].OUT_HALF0_BEL[7] | DCI.DCIDATA |
| CELL[3].OUT_HALF1_BEL[3] | DCI.DCIDONE |
| CELL[3].OUT_HALF1_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[3].OUT_HALF1_BEL[5] | DCI.DCIIOUPDATE |
| CELL[3].OUT_HALF1_BEL[6] | DCI.DCISCLK |
| CELL[3].OUT_HALF1_BEL[7] | DCI.DCIDATA |
Bitstream
| Bit | Frame | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F0 | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 | F11 | F12 | F13 | F14 | F15 | F16 | F17 | F18 | F19 | F20 | F21 | F22 | F23 | F24 | F25 | F26 | F27 | F28 | F29 | |
| B31 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B30 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B29 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B28 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B27 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B26 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B25 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B24 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B23 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B22 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B21 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B20 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B19 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B18 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B17 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B16 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B15 | DCI: TEST_ENABLE bit 0 | DCI: PREF bit 0 | - | - | DCI: V4_PMASK_TERM_VCC bit 3 | - | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[3] ← CELL[2].HCLK_ROW[3] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[7] ← CELL[2].HCLK_ROW[7] | - | DCI: V4_PMASK_TERM_SPLIT bit 3 | DCI: V4_PMASK_TERM_SPLIT bit 4 | DCI: V4_NMASK_TERM_SPLIT bit 3 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 2 | BUFIO[1]: ENABLE | HCLK_IO_INT: buffer CELL[2].IOCLK_N_IO[0] ← CELL[2].IOCLK_N[0] | - | - | - | HCLK_IO_INT: buffer CELL[2].RCLK_IO[0] ← CELL[2].RCLK_ROW[0] | - | - | HCLK_IO_INT: buffer CELL[2].RCLK_IO[1] ← CELL[2].RCLK_ROW[1] | - | - | DCI: NREF bit 0 | - | - |
| B14 | DCI: ENABLE | DCI: PREF bit 1 | - | - | DCI: V4_PMASK_TERM_VCC bit 2 | - | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[2] ← CELL[2].HCLK_ROW[2] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[6] ← CELL[2].HCLK_ROW[6] | - | DCI: V4_PMASK_TERM_SPLIT bit 1 | DCI: V4_PMASK_TERM_SPLIT bit 2 | DCI: V4_NMASK_TERM_SPLIT bit 2 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 1 | BUFIO[0]: ENABLE | HCLK_IO_INT: buffer CELL[2].IOCLK_S_IO[0] ← CELL[2].IOCLK_S[0] | - | - | - | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 2 | - | - | DCI: V4_LVDIV2 bit 1 | - | - |
| B13 | DCI: CASCADE_FROM_ABOVE | DCI: PREF bit 2 | - | - | DCI: V4_PMASK_TERM_VCC bit 1 | DCI: TEST_ENABLE bit 1 | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[1] ← CELL[2].HCLK_ROW[1] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[5] ← CELL[2].HCLK_ROW[5] | - | DCI: V4_PMASK_TERM_SPLIT bit 0 | - | DCI: V4_NMASK_TERM_SPLIT bit 1 | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 0 | - | HCLK_IO_INT: buffer CELL[2].IOCLK_S_IO[1] ← CELL[2].IOCLK_S[1] | - | - | HCLK_IO_INT: wire support (CELL[2].IOCLK[0], CELL[2].IOCLK[1]) bit 3 | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 1 | - | - | DCI: V4_LVDIV2 bit 0 | - | - |
| B12 | - | DCI: PREF bit 3 | DCI: V4_PMASK_TERM_VCC bit 4 | - | DCI: V4_PMASK_TERM_VCC bit 0 | DCI: QUIET | - | HCLK_IO_INT: buffer CELL[2].HCLK_IO[0] ← CELL[2].HCLK_ROW[0] | HCLK_IO_INT: buffer CELL[2].HCLK_IO[4] ← CELL[2].HCLK_ROW[4] | - | DCI: V4_NMASK_TERM_SPLIT bit 4 | IDELAYCTRL: DLL_ENABLE | DCI: V4_NMASK_TERM_SPLIT bit 0 | - | - | - | - | HCLK_IO_INT: buffer CELL[2].IOCLK_N_IO[1] ← CELL[2].IOCLK_N[1] | - | - | - | - | - | - | HCLK_IO_INT: mux CELL[2].IMUX_IDELAYCTRL_REFCLK bit 0 | - | - | DCI: NREF bit 1 | - | - |
| B11 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B10 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B9 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B7 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B6 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B5 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B4 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B3 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| B0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
Tile HCLK_IO_DCM_S
Cells: 5
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| CELL[2].HCLK_DCM[0] | CELL[2].HCLK_ROW[0] | MAIN[21][12] |
| CELL[2].HCLK_DCM[1] | CELL[2].HCLK_ROW[1] | MAIN[25][13] |
| CELL[2].HCLK_DCM[2] | CELL[2].HCLK_ROW[2] | MAIN[22][15] |
| CELL[2].HCLK_DCM[3] | CELL[2].HCLK_ROW[3] | MAIN[14][15] |
| CELL[2].HCLK_DCM[4] | CELL[2].HCLK_ROW[4] | MAIN[19][14] |
| CELL[2].HCLK_DCM[5] | CELL[2].HCLK_ROW[5] | MAIN[23][13] |
| CELL[2].HCLK_DCM[6] | CELL[2].HCLK_ROW[6] | MAIN[22][14] |
| CELL[2].HCLK_DCM[7] | CELL[2].HCLK_ROW[7] | MAIN[26][12] |
| CELL[2].GIOB_DCM[0] | CELL[2].GIOB[0] | MAIN[3][13] |
| CELL[2].GIOB_DCM[1] | CELL[2].GIOB[1] | MAIN[21][14] |
| CELL[2].GIOB_DCM[2] | CELL[2].GIOB[2] | MAIN[22][13] |
| CELL[2].GIOB_DCM[3] | CELL[2].GIOB[3] | MAIN[19][13] |
| CELL[2].GIOB_DCM[4] | CELL[2].GIOB[4] | MAIN[28][13] |
| CELL[2].GIOB_DCM[5] | CELL[2].GIOB[5] | MAIN[28][12] |
| CELL[2].GIOB_DCM[6] | CELL[2].GIOB[6] | MAIN[25][12] |
| CELL[2].GIOB_DCM[7] | CELL[2].GIOB[7] | MAIN[23][14] |
| CELL[2].GIOB_DCM[8] | CELL[2].GIOB[8] | MAIN[23][12] |
| CELL[2].GIOB_DCM[9] | CELL[2].GIOB[9] | MAIN[22][12] |
| CELL[2].GIOB_DCM[10] | CELL[2].GIOB[10] | MAIN[26][13] |
| CELL[2].GIOB_DCM[11] | CELL[2].GIOB[11] | MAIN[25][14] |
| CELL[2].GIOB_DCM[12] | CELL[2].GIOB[12] | MAIN[25][15] |
| CELL[2].GIOB_DCM[13] | CELL[2].GIOB[13] | MAIN[19][12] |
| CELL[2].GIOB_DCM[14] | CELL[2].GIOB[14] | MAIN[3][14] |
| CELL[2].GIOB_DCM[15] | CELL[2].GIOB[15] | MAIN[3][15] |
| CELL[2].MGT_DCM[0] | CELL[2].MGT_ROW[0] | MAIN[14][13] |
| CELL[2].MGT_DCM[1] | CELL[2].MGT_ROW[1] | MAIN[26][14] |
| CELL[2].MGT_DCM[2] | CELL_E.MGT_ROW[0] | MAIN[26][15] |
| CELL[2].MGT_DCM[3] | CELL_E.MGT_ROW[1] | MAIN[23][15] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
| Bit |
|---|
| MAIN[14][14] |
| MAIN[19][15] |
| MAIN[21][13] |
| Bit |
|---|
| MAIN[16][12] |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[1].IMUX_BYP[7] |
| RDY | out | CELL[1].OUT_HALF0_BEL[4], CELL[1].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[1].OUT_HALF0_BEL[0], CELL[1].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[1].OUT_HALF0_BEL[1], CELL[1].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[1].OUT_HALF0_BEL[3], CELL[1].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[1].OUT_HALF0_BEL[2], CELL[1].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels DCI
| Pin | Direction | DCI |
|---|---|---|
| TSTCLK | in | CELL[0].IMUX_BYP[0] |
| TSTRST | in | CELL[0].IMUX_BYP[2] |
| TSTHLP | in | CELL[0].IMUX_BYP[7] |
| TSTHLN | in | CELL[0].IMUX_BYP[4] |
| DCISCLK | out | CELL[0].OUT_HALF0_BEL[6], CELL[0].OUT_HALF1_BEL[6] |
| DCIADDRESS[0] | out | CELL[1].OUT_HALF0_BEL[5], CELL[1].OUT_HALF1_BEL[5] |
| DCIADDRESS[1] | out | CELL[1].OUT_HALF0_BEL[6], CELL[1].OUT_HALF1_BEL[6] |
| DCIADDRESS[2] | out | CELL[1].OUT_HALF0_BEL[7], CELL[1].OUT_HALF1_BEL[7] |
| DCIDATA | out | CELL[0].OUT_HALF0_BEL[7], CELL[0].OUT_HALF1_BEL[7] |
| DCIIOUPDATE | out | CELL[0].OUT_HALF0_BEL[5], CELL[0].OUT_HALF1_BEL[5] |
| DCIREFIOUPDATE | out | CELL[0].OUT_HALF0_BEL[4], CELL[0].OUT_HALF1_BEL[4] |
| DCIDONE | out | CELL[0].OUT_HALF0_BEL[3], CELL[0].OUT_HALF1_BEL[3] |
| Attribute | DCI |
|---|---|
| ENABLE | MAIN[0][14] |
| QUIET | MAIN[5][12] |
| V4_LVDIV2 bit 0 | MAIN[27][13] |
| V4_LVDIV2 bit 1 | MAIN[27][14] |
| V4_PMASK_TERM_VCC bit 0 | MAIN[4][12] |
| V4_PMASK_TERM_VCC bit 1 | MAIN[4][13] |
| V4_PMASK_TERM_VCC bit 2 | MAIN[4][14] |
| V4_PMASK_TERM_VCC bit 3 | MAIN[4][15] |
| V4_PMASK_TERM_VCC bit 4 | MAIN[2][12] |
| V4_PMASK_TERM_SPLIT bit 0 | MAIN[10][13] |
| V4_PMASK_TERM_SPLIT bit 1 | MAIN[10][14] |
| V4_PMASK_TERM_SPLIT bit 2 | MAIN[11][14] |
| V4_PMASK_TERM_SPLIT bit 3 | MAIN[10][15] |
| V4_PMASK_TERM_SPLIT bit 4 | MAIN[11][15] |
| V4_NMASK_TERM_SPLIT bit 0 | MAIN[12][12] |
| V4_NMASK_TERM_SPLIT bit 1 | MAIN[12][13] |
| V4_NMASK_TERM_SPLIT bit 2 | MAIN[12][14] |
| V4_NMASK_TERM_SPLIT bit 3 | MAIN[12][15] |
| V4_NMASK_TERM_SPLIT bit 4 | MAIN[10][12] |
| NREF bit 0 | MAIN[27][15] |
| NREF bit 1 | MAIN[27][12] |
| PREF bit 0 | MAIN[1][15] |
| PREF bit 1 | MAIN[1][14] |
| PREF bit 2 | MAIN[1][13] |
| PREF bit 3 | MAIN[1][12] |
| TEST_ENABLE bit 0 | MAIN[0][15] |
| TEST_ENABLE bit 1 | MAIN[5][13] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[0].IMUX_BYP[0] | DCI.TSTCLK |
| CELL[0].IMUX_BYP[2] | DCI.TSTRST |
| CELL[0].IMUX_BYP[4] | DCI.TSTHLN |
| CELL[0].IMUX_BYP[7] | DCI.TSTHLP |
| CELL[0].OUT_HALF0_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF0_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF0_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF0_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF0_BEL[7] | DCI.DCIDATA |
| CELL[0].OUT_HALF1_BEL[3] | DCI.DCIDONE |
| CELL[0].OUT_HALF1_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[0].OUT_HALF1_BEL[5] | DCI.DCIIOUPDATE |
| CELL[0].OUT_HALF1_BEL[6] | DCI.DCISCLK |
| CELL[0].OUT_HALF1_BEL[7] | DCI.DCIDATA |
| CELL[1].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[1].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF0_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF0_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF0_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[1].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[1].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[1].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[1].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[1].OUT_HALF1_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[1].OUT_HALF1_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[1].OUT_HALF1_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
Bitstream
Tile HCLK_IO_DCM_N
Cells: 5
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[1].HCLK_DCM[0] | CELL[2].HCLK_ROW[0] | MAIN[21][12] |
| CELL[1].HCLK_DCM[1] | CELL[2].HCLK_ROW[1] | MAIN[25][13] |
| CELL[1].HCLK_DCM[2] | CELL[2].HCLK_ROW[2] | MAIN[22][15] |
| CELL[1].HCLK_DCM[3] | CELL[2].HCLK_ROW[3] | MAIN[14][15] |
| CELL[1].HCLK_DCM[4] | CELL[2].HCLK_ROW[4] | MAIN[19][14] |
| CELL[1].HCLK_DCM[5] | CELL[2].HCLK_ROW[5] | MAIN[23][13] |
| CELL[1].HCLK_DCM[6] | CELL[2].HCLK_ROW[6] | MAIN[22][14] |
| CELL[1].HCLK_DCM[7] | CELL[2].HCLK_ROW[7] | MAIN[26][12] |
| CELL[1].GIOB_DCM[0] | CELL[2].GIOB[0] | MAIN[3][13] |
| CELL[1].GIOB_DCM[1] | CELL[2].GIOB[1] | MAIN[21][14] |
| CELL[1].GIOB_DCM[2] | CELL[2].GIOB[2] | MAIN[22][13] |
| CELL[1].GIOB_DCM[3] | CELL[2].GIOB[3] | MAIN[19][13] |
| CELL[1].GIOB_DCM[4] | CELL[2].GIOB[4] | MAIN[28][13] |
| CELL[1].GIOB_DCM[5] | CELL[2].GIOB[5] | MAIN[28][12] |
| CELL[1].GIOB_DCM[6] | CELL[2].GIOB[6] | MAIN[25][12] |
| CELL[1].GIOB_DCM[7] | CELL[2].GIOB[7] | MAIN[23][14] |
| CELL[1].GIOB_DCM[8] | CELL[2].GIOB[8] | MAIN[23][12] |
| CELL[1].GIOB_DCM[9] | CELL[2].GIOB[9] | MAIN[22][12] |
| CELL[1].GIOB_DCM[10] | CELL[2].GIOB[10] | MAIN[26][13] |
| CELL[1].GIOB_DCM[11] | CELL[2].GIOB[11] | MAIN[25][14] |
| CELL[1].GIOB_DCM[12] | CELL[2].GIOB[12] | MAIN[25][15] |
| CELL[1].GIOB_DCM[13] | CELL[2].GIOB[13] | MAIN[19][12] |
| CELL[1].GIOB_DCM[14] | CELL[2].GIOB[14] | MAIN[3][14] |
| CELL[1].GIOB_DCM[15] | CELL[2].GIOB[15] | MAIN[3][15] |
| CELL[1].MGT_DCM[0] | CELL[2].MGT_ROW[0] | MAIN[14][13] |
| CELL[1].MGT_DCM[1] | CELL[2].MGT_ROW[1] | MAIN[26][14] |
| CELL[1].MGT_DCM[2] | CELL_E.MGT_ROW[0] | MAIN[26][15] |
| CELL[1].MGT_DCM[3] | CELL_E.MGT_ROW[1] | MAIN[23][15] |
| CELL[2].HCLK_IO[0] | CELL[2].HCLK_ROW[0] | MAIN[7][12] |
| CELL[2].HCLK_IO[1] | CELL[2].HCLK_ROW[1] | MAIN[7][13] |
| CELL[2].HCLK_IO[2] | CELL[2].HCLK_ROW[2] | MAIN[7][14] |
| CELL[2].HCLK_IO[3] | CELL[2].HCLK_ROW[3] | MAIN[7][15] |
| CELL[2].HCLK_IO[4] | CELL[2].HCLK_ROW[4] | MAIN[8][12] |
| CELL[2].HCLK_IO[5] | CELL[2].HCLK_ROW[5] | MAIN[8][13] |
| CELL[2].HCLK_IO[6] | CELL[2].HCLK_ROW[6] | MAIN[8][14] |
| CELL[2].HCLK_IO[7] | CELL[2].HCLK_ROW[7] | MAIN[8][15] |
| CELL[2].RCLK_IO[0] | CELL[2].RCLK_ROW[0] | MAIN[21][15] |
| CELL[2].RCLK_IO[1] | CELL[2].RCLK_ROW[1] | MAIN[24][15] |
| CELL[2].IOCLK_S_IO[0] | CELL[2].IOCLK_S[0] | MAIN[17][14] |
| CELL[2].IOCLK_S_IO[1] | CELL[2].IOCLK_S[1] | MAIN[17][13] |
| CELL[2].IOCLK_N_IO[0] | CELL[2].IOCLK_N[0] | MAIN[17][15] |
| CELL[2].IOCLK_N_IO[1] | CELL[2].IOCLK_N[1] | MAIN[17][12] |
| Bits | Destination | ||
|---|---|---|---|
| MAIN[24][14] | MAIN[24][13] | MAIN[24][12] | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| Source | |||
| 0 | 0 | 0 | CELL[2].HCLK_IO[0] |
| 0 | 0 | 1 | CELL[2].HCLK_IO[1] |
| 0 | 1 | 0 | CELL[2].HCLK_IO[2] |
| 0 | 1 | 1 | CELL[2].HCLK_IO[3] |
| 1 | 0 | 0 | CELL[2].HCLK_IO[4] |
| 1 | 0 | 1 | CELL[2].HCLK_IO[5] |
| 1 | 1 | 0 | CELL[2].HCLK_IO[6] |
| 1 | 1 | 1 | CELL[2].HCLK_IO[7] |
| Bit |
|---|
| MAIN[14][14] |
| MAIN[19][15] |
| MAIN[21][13] |
| Bit |
|---|
| MAIN[16][12] |
| Bit |
|---|
| MAIN[15][13] |
| MAIN[15][14] |
| MAIN[15][15] |
| MAIN[20][13] |
Bels BUFIO
| Pin | Direction | BUFIO[0] | BUFIO[1] |
|---|---|---|---|
| I | in | CELL[2].OUT_CLKPAD | CELL[1].OUT_CLKPAD |
| O | out | CELL[2].IOCLK[0] | CELL[2].IOCLK[1] |
| Attribute | BUFIO[0] | BUFIO[1] |
|---|---|---|
| ENABLE | MAIN[16][14] | MAIN[16][15] |
Bels IDELAYCTRL
| Pin | Direction | IDELAYCTRL |
|---|---|---|
| REFCLK | in | CELL[2].IMUX_IDELAYCTRL_REFCLK |
| RST | in | CELL[2].IMUX_BYP[7] |
| RDY | out | CELL[2].OUT_HALF0_BEL[4], CELL[2].OUT_HALF1_BEL[4] |
| DNPULSEOUT | out | CELL[2].OUT_HALF0_BEL[0], CELL[2].OUT_HALF1_BEL[0] |
| UPPULSEOUT | out | CELL[2].OUT_HALF0_BEL[1], CELL[2].OUT_HALF1_BEL[1] |
| OUTN1 | out | CELL[2].OUT_HALF0_BEL[3], CELL[2].OUT_HALF1_BEL[3] |
| OUTN65 | out | CELL[2].OUT_HALF0_BEL[2], CELL[2].OUT_HALF1_BEL[2] |
| Attribute | IDELAYCTRL |
|---|---|
| DLL_ENABLE | MAIN[11][12] |
Bels DCI
| Pin | Direction | DCI |
|---|---|---|
| TSTCLK | in | CELL[3].IMUX_BYP[0] |
| TSTRST | in | CELL[3].IMUX_BYP[2] |
| TSTHLP | in | CELL[3].IMUX_BYP[4] |
| TSTHLN | in | CELL[3].IMUX_BYP[7] |
| DCISCLK | out | CELL[3].OUT_HALF0_BEL[6], CELL[3].OUT_HALF1_BEL[6] |
| DCIADDRESS[0] | out | CELL[2].OUT_HALF0_BEL[5], CELL[2].OUT_HALF1_BEL[5] |
| DCIADDRESS[1] | out | CELL[2].OUT_HALF0_BEL[6], CELL[2].OUT_HALF1_BEL[6] |
| DCIADDRESS[2] | out | CELL[2].OUT_HALF0_BEL[7], CELL[2].OUT_HALF1_BEL[7] |
| DCIDATA | out | CELL[3].OUT_HALF0_BEL[7], CELL[3].OUT_HALF1_BEL[7] |
| DCIIOUPDATE | out | CELL[3].OUT_HALF0_BEL[5], CELL[3].OUT_HALF1_BEL[5] |
| DCIREFIOUPDATE | out | CELL[3].OUT_HALF0_BEL[4], CELL[3].OUT_HALF1_BEL[4] |
| DCIDONE | out | CELL[3].OUT_HALF0_BEL[3], CELL[3].OUT_HALF1_BEL[3] |
| Attribute | DCI |
|---|---|
| ENABLE | MAIN[0][14] |
| QUIET | MAIN[5][12] |
| V4_LVDIV2 bit 0 | MAIN[27][13] |
| V4_LVDIV2 bit 1 | MAIN[27][14] |
| V4_PMASK_TERM_VCC bit 0 | MAIN[4][12] |
| V4_PMASK_TERM_VCC bit 1 | MAIN[4][13] |
| V4_PMASK_TERM_VCC bit 2 | MAIN[4][14] |
| V4_PMASK_TERM_VCC bit 3 | MAIN[4][15] |
| V4_PMASK_TERM_VCC bit 4 | MAIN[2][12] |
| V4_PMASK_TERM_SPLIT bit 0 | MAIN[10][13] |
| V4_PMASK_TERM_SPLIT bit 1 | MAIN[10][14] |
| V4_PMASK_TERM_SPLIT bit 2 | MAIN[11][14] |
| V4_PMASK_TERM_SPLIT bit 3 | MAIN[10][15] |
| V4_PMASK_TERM_SPLIT bit 4 | MAIN[11][15] |
| V4_NMASK_TERM_SPLIT bit 0 | MAIN[12][12] |
| V4_NMASK_TERM_SPLIT bit 1 | MAIN[12][13] |
| V4_NMASK_TERM_SPLIT bit 2 | MAIN[12][14] |
| V4_NMASK_TERM_SPLIT bit 3 | MAIN[12][15] |
| V4_NMASK_TERM_SPLIT bit 4 | MAIN[10][12] |
| NREF bit 0 | MAIN[27][15] |
| NREF bit 1 | MAIN[27][12] |
| PREF bit 0 | MAIN[1][15] |
| PREF bit 1 | MAIN[1][14] |
| PREF bit 2 | MAIN[1][13] |
| PREF bit 3 | MAIN[1][12] |
| TEST_ENABLE bit 0 | MAIN[0][15] |
| TEST_ENABLE bit 1 | MAIN[5][13] |
Bel wires
| Wire | Pins |
|---|---|
| CELL[1].OUT_CLKPAD | BUFIO[1].I |
| CELL[2].IMUX_BYP[7] | IDELAYCTRL.RST |
| CELL[2].OUT_HALF0_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[2].OUT_HALF0_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[2].OUT_HALF0_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[2].OUT_HALF0_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[2].OUT_HALF0_BEL[4] | IDELAYCTRL.RDY |
| CELL[2].OUT_HALF0_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[2].OUT_HALF0_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[2].OUT_HALF0_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[2].OUT_HALF1_BEL[0] | IDELAYCTRL.DNPULSEOUT |
| CELL[2].OUT_HALF1_BEL[1] | IDELAYCTRL.UPPULSEOUT |
| CELL[2].OUT_HALF1_BEL[2] | IDELAYCTRL.OUTN65 |
| CELL[2].OUT_HALF1_BEL[3] | IDELAYCTRL.OUTN1 |
| CELL[2].OUT_HALF1_BEL[4] | IDELAYCTRL.RDY |
| CELL[2].OUT_HALF1_BEL[5] | DCI.DCIADDRESS[0] |
| CELL[2].OUT_HALF1_BEL[6] | DCI.DCIADDRESS[1] |
| CELL[2].OUT_HALF1_BEL[7] | DCI.DCIADDRESS[2] |
| CELL[2].OUT_CLKPAD | BUFIO[0].I |
| CELL[2].IMUX_IDELAYCTRL_REFCLK | IDELAYCTRL.REFCLK |
| CELL[2].IOCLK[0] | BUFIO[0].O |
| CELL[2].IOCLK[1] | BUFIO[1].O |
| CELL[3].IMUX_BYP[0] | DCI.TSTCLK |
| CELL[3].IMUX_BYP[2] | DCI.TSTRST |
| CELL[3].IMUX_BYP[4] | DCI.TSTHLP |
| CELL[3].IMUX_BYP[7] | DCI.TSTHLN |
| CELL[3].OUT_HALF0_BEL[3] | DCI.DCIDONE |
| CELL[3].OUT_HALF0_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[3].OUT_HALF0_BEL[5] | DCI.DCIIOUPDATE |
| CELL[3].OUT_HALF0_BEL[6] | DCI.DCISCLK |
| CELL[3].OUT_HALF0_BEL[7] | DCI.DCIDATA |
| CELL[3].OUT_HALF1_BEL[3] | DCI.DCIDONE |
| CELL[3].OUT_HALF1_BEL[4] | DCI.DCIREFIOUPDATE |
| CELL[3].OUT_HALF1_BEL[5] | DCI.DCIIOUPDATE |
| CELL[3].OUT_HALF1_BEL[6] | DCI.DCISCLK |
| CELL[3].OUT_HALF1_BEL[7] | DCI.DCIDATA |
Bitstream
Tile HCLK_DCM
Cells: 5
Switchbox HCLK_IO_INT
| Destination | Source | Bit |
|---|---|---|
| CELL[1].HCLK_DCM[0] | CELL[2].HCLK_ROW[0] | MAIN[20][12] |
| CELL[1].HCLK_DCM[1] | CELL[2].HCLK_ROW[1] | MAIN[24][15] |
| CELL[1].HCLK_DCM[2] | CELL[2].HCLK_ROW[2] | MAIN[23][13] |
| CELL[1].HCLK_DCM[3] | CELL[2].HCLK_ROW[3] | MAIN[21][15] |
| CELL[1].HCLK_DCM[4] | CELL[2].HCLK_ROW[4] | MAIN[20][13] |
| CELL[1].HCLK_DCM[5] | CELL[2].HCLK_ROW[5] | MAIN[24][14] |
| CELL[1].HCLK_DCM[6] | CELL[2].HCLK_ROW[6] | MAIN[23][14] |
| CELL[1].HCLK_DCM[7] | CELL[2].HCLK_ROW[7] | MAIN[22][15] |
| CELL[1].GIOB_DCM[0] | CELL[2].GIOB[0] | MAIN[20][14] |
| CELL[1].GIOB_DCM[1] | CELL[2].GIOB[1] | MAIN[24][12] |
| CELL[1].GIOB_DCM[2] | CELL[2].GIOB[2] | MAIN[23][15] |
| CELL[1].GIOB_DCM[3] | CELL[2].GIOB[3] | MAIN[22][13] |
| CELL[1].GIOB_DCM[4] | CELL[2].GIOB[4] | MAIN[20][15] |
| CELL[1].GIOB_DCM[5] | CELL[2].GIOB[5] | MAIN[24][13] |
| CELL[1].GIOB_DCM[6] | CELL[2].GIOB[6] | MAIN[22][12] |
| CELL[1].GIOB_DCM[7] | CELL[2].GIOB[7] | MAIN[22][14] |
| CELL[1].GIOB_DCM[8] | CELL[2].GIOB[8] | MAIN[12][14] |
| CELL[1].GIOB_DCM[9] | CELL[2].GIOB[9] | MAIN[12][12] |
| CELL[1].GIOB_DCM[10] | CELL[2].GIOB[10] | MAIN[3][13] |
| CELL[1].GIOB_DCM[11] | CELL[2].GIOB[11] | MAIN[3][15] |
| CELL[1].GIOB_DCM[12] | CELL[2].GIOB[12] | MAIN[10][13] |
| CELL[1].GIOB_DCM[13] | CELL[2].GIOB[13] | MAIN[10][12] |
| CELL[1].GIOB_DCM[14] | CELL[2].GIOB[14] | MAIN[11][13] |
| CELL[1].GIOB_DCM[15] | CELL[2].GIOB[15] | MAIN[11][12] |
| CELL[1].MGT_DCM[0] | CELL[2].MGT_ROW[0] | MAIN[12][15] |
| CELL[1].MGT_DCM[1] | CELL[2].MGT_ROW[1] | MAIN[12][13] |
| CELL[1].MGT_DCM[2] | CELL_E.MGT_ROW[0] | MAIN[3][12] |
| CELL[1].MGT_DCM[3] | CELL_E.MGT_ROW[1] | MAIN[3][14] |
| CELL[2].HCLK_DCM[0] | CELL[2].HCLK_ROW[0] | MAIN[17][14] |
| CELL[2].HCLK_DCM[1] | CELL[2].HCLK_ROW[1] | MAIN[25][12] |
| CELL[2].HCLK_DCM[2] | CELL[2].HCLK_ROW[2] | MAIN[14][15] |
| CELL[2].HCLK_DCM[3] | CELL[2].HCLK_ROW[3] | MAIN[26][14] |
| CELL[2].HCLK_DCM[4] | CELL[2].HCLK_ROW[4] | MAIN[17][13] |
| CELL[2].HCLK_DCM[5] | CELL[2].HCLK_ROW[5] | MAIN[25][13] |
| CELL[2].HCLK_DCM[6] | CELL[2].HCLK_ROW[6] | MAIN[14][14] |
| CELL[2].HCLK_DCM[7] | CELL[2].HCLK_ROW[7] | MAIN[26][13] |
| CELL[2].GIOB_DCM[0] | CELL[2].GIOB[0] | MAIN[17][15] |
| CELL[2].GIOB_DCM[1] | CELL[2].GIOB[1] | MAIN[25][14] |
| CELL[2].GIOB_DCM[2] | CELL[2].GIOB[2] | MAIN[14][13] |
| CELL[2].GIOB_DCM[3] | CELL[2].GIOB[3] | MAIN[26][12] |
| CELL[2].GIOB_DCM[4] | CELL[2].GIOB[4] | MAIN[17][12] |
| CELL[2].GIOB_DCM[5] | CELL[2].GIOB[5] | MAIN[25][15] |
| CELL[2].GIOB_DCM[6] | CELL[2].GIOB[6] | MAIN[14][12] |
| CELL[2].GIOB_DCM[7] | CELL[2].GIOB[7] | MAIN[26][15] |
| CELL[2].GIOB_DCM[8] | CELL[2].GIOB[8] | MAIN[5][12] |
| CELL[2].GIOB_DCM[9] | CELL[2].GIOB[9] | MAIN[5][14] |
| CELL[2].GIOB_DCM[10] | CELL[2].GIOB[10] | MAIN[16][12] |
| CELL[2].GIOB_DCM[11] | CELL[2].GIOB[11] | MAIN[16][14] |
| CELL[2].GIOB_DCM[12] | CELL[2].GIOB[12] | MAIN[10][14] |
| CELL[2].GIOB_DCM[13] | CELL[2].GIOB[13] | MAIN[5][13] |
| CELL[2].GIOB_DCM[14] | CELL[2].GIOB[14] | MAIN[11][14] |
| CELL[2].GIOB_DCM[15] | CELL[2].GIOB[15] | MAIN[16][13] |
| CELL[2].MGT_DCM[0] | CELL[2].MGT_ROW[0] | MAIN[10][15] |
| CELL[2].MGT_DCM[1] | CELL[2].MGT_ROW[1] | MAIN[5][15] |
| CELL[2].MGT_DCM[2] | CELL_E.MGT_ROW[0] | MAIN[11][15] |
| CELL[2].MGT_DCM[3] | CELL_E.MGT_ROW[1] | MAIN[16][15] |
| Bit |
|---|
| MAIN[27][15] |
| Bit |
|---|
| MAIN[19][12] |
| MAIN[21][12] |
| MAIN[27][13] |
| Bit |
|---|
| MAIN[27][14] |