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Clock I/O and DCM buffers

Tile HCLK_IOIS_LVDS

Cells: 3

Bel IOCLK

virtex4 HCLK_IOIS_LVDS bel IOCLK
PinDirectionWires

Bel RCLK

virtex4 HCLK_IOIS_LVDS bel RCLK
PinDirectionWires
CKINT0inputTCELL1:IMUX.BYP4
CKINT1inputTCELL2:IMUX.BYP4

Bel BUFR0

virtex4 HCLK_IOIS_LVDS bel BUFR0
PinDirectionWires
CEinputTCELL2:IMUX.BYP0
CLRinputTCELL2:IMUX.BYP2

Bel BUFR1

virtex4 HCLK_IOIS_LVDS bel BUFR1
PinDirectionWires
CEinputTCELL1:IMUX.BYP0
CLRinputTCELL1:IMUX.BYP2

Bel BUFIO0

virtex4 HCLK_IOIS_LVDS bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOIS_LVDS bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOIS_LVDS bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN
RDYoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
RSTinputTCELL1:IMUX.BYP7
UPPULSEOUToutputTCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN

Bel wires

virtex4 HCLK_IOIS_LVDS bel wires
WirePins
TCELL1:IMUX.BYP0BUFR1.CE
TCELL1:IMUX.BYP2BUFR1.CLR
TCELL1:IMUX.BYP4RCLK.CKINT0
TCELL1:IMUX.BYP7IDELAYCTRL.RST
TCELL1:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL2:IMUX.BYP0BUFR0.CE
TCELL2:IMUX.BYP2BUFR0.CLR
TCELL2:IMUX.BYP4RCLK.CKINT1

Bitstream

virtex4 HCLK_IOIS_LVDS bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
15 - - - LVDS:LVDSBIAS[2] - LVDS:LVDSBIAS[6] - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - - - - - BUFR0:BUFR_DIVIDE[0] IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - BUFR0:MUX.I[1] - IOCLK:BUF.RCLK0 BUFR1:BUFR_DIVIDE[0] RCLK:MUX.RCLK1[0] IOCLK:BUF.RCLK1 RCLK:MUX.RCLK0[0]
14 - - LVDS:LVDSBIAS[7] LVDS:LVDSBIAS[4] - LVDS:LVDSBIAS[1] - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - - - - - BUFR0:BUFR_DIVIDE[3] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - BUFR0:MUX.I[0] - BUFR0:ENABLE BUFR1:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[2] IDELAYCTRL:MUX.REFCLK[2] RCLK:MUX.RCLK0[2]
13 - - LVDS:LVDSBIAS[3] LVDS:LVDSBIAS[5] - - - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - - LVDS:LVDSBIAS[8] - - BUFR0:BUFR_DIVIDE[2] IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - BUFR1:MUX.I[0] IOCLK:VIOCLK_ENABLE[3] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[1] RCLK:MUX.RCLK0[1]
12 - - - LVDS:LVDSBIAS[9] - LVDS:LVDSBIAS[0] - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - - IDELAYCTRL:ENABLE - - BUFR0:BUFR_DIVIDE[1] - - IOCLK:BUF.IOCLK_N1 - BUFR1:MUX.I[1] - - BUFR1:BUFR_DIVIDE[1] RCLK:MUX.RCLK1[3] IDELAYCTRL:MUX.REFCLK[0] RCLK:MUX.RCLK0[3]
11 - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFR0:BUFR_DIVIDE 0.14.14 0.14.13 0.14.12 0.14.15
BUFR1:BUFR_DIVIDE 0.22.14 0.22.13 0.22.12 0.22.15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:ENABLE 0.21.14
BUFR1:ENABLE 0.21.13
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
BUFR0:MUX.I 0.19.15 0.19.14
BUFR1:MUX.I 0.19.12 0.19.13
BUFIO0 0 0
CKINT0 0 1
CKINT1 1 0
BUFIO1 1 1
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
LVDS:LVDSBIAS 0.3.12 0.11.13 0.2.14 0.5.15 0.3.13 0.3.14 0.2.13 0.3.15 0.5.14 0.5.12
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
RCLK:MUX.RCLK0 0.25.12 0.25.14 0.25.13 0.25.15
RCLK:MUX.RCLK1 0.23.12 0.23.14 0.23.13 0.23.15
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_S0 0 1 0 1
VRCLK_N1 1 0 0 1
VRCLK1 1 0 1 1
VRCLK_S1 1 1 0 1

Tile HCLK_IOIS_DCI

Cells: 3

Bel IOCLK

virtex4 HCLK_IOIS_DCI bel IOCLK
PinDirectionWires

Bel RCLK

virtex4 HCLK_IOIS_DCI bel RCLK
PinDirectionWires
CKINT0inputTCELL1:IMUX.BYP4
CKINT1inputTCELL2:IMUX.BYP4

Bel BUFR0

virtex4 HCLK_IOIS_DCI bel BUFR0
PinDirectionWires
CEinputTCELL2:IMUX.BYP0
CLRinputTCELL2:IMUX.BYP2

Bel BUFR1

virtex4 HCLK_IOIS_DCI bel BUFR1
PinDirectionWires
CEinputTCELL1:IMUX.BYP0
CLRinputTCELL1:IMUX.BYP2

Bel BUFIO0

virtex4 HCLK_IOIS_DCI bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOIS_DCI bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOIS_DCI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN
RDYoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
RSTinputTCELL1:IMUX.BYP7
UPPULSEOUToutputTCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_IOIS_DCI bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
DCIADDRESS1outputTCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
DCIADDRESS2outputTCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
DCIDATAoutputTCELL0:OUT.HALF.BOT7.TMIN, TCELL0:OUT.HALT.TOP7.TMIN
DCIDONEoutputTCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputTCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
DCISCLKoutputTCELL0:OUT.HALF.BOT6.TMIN, TCELL0:OUT.HALT.TOP6.TMIN
TSTCLKinputTCELL0:IMUX.BYP0
TSTHLNinputTCELL0:IMUX.BYP4
TSTHLPinputTCELL0:IMUX.BYP7
TSTRSTinputTCELL0:IMUX.BYP2

Bel wires

virtex4 HCLK_IOIS_DCI bel wires
WirePins
TCELL0:IMUX.BYP0DCI.TSTCLK
TCELL0:IMUX.BYP2DCI.TSTRST
TCELL0:IMUX.BYP4DCI.TSTHLN
TCELL0:IMUX.BYP7DCI.TSTHLP
TCELL0:OUT.HALF.BOT3.TMINDCI.DCIDONE
TCELL0:OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALF.BOT6.TMINDCI.DCISCLK
TCELL0:OUT.HALF.BOT7.TMINDCI.DCIDATA
TCELL0:OUT.HALT.TOP3.TMINDCI.DCIDONE
TCELL0:OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALT.TOP6.TMINDCI.DCISCLK
TCELL0:OUT.HALT.TOP7.TMINDCI.DCIDATA
TCELL1:IMUX.BYP0BUFR1.CE
TCELL1:IMUX.BYP2BUFR1.CLR
TCELL1:IMUX.BYP4RCLK.CKINT0
TCELL1:IMUX.BYP7IDELAYCTRL.RST
TCELL1:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
TCELL1:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
TCELL2:IMUX.BYP0BUFR0.CE
TCELL2:IMUX.BYP2BUFR0.CLR
TCELL2:IMUX.BYP4RCLK.CKINT1

Bitstream

virtex4 HCLK_IOIS_DCI bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - BUFR0:BUFR_DIVIDE[0] IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - BUFR0:MUX.I[1] - IOCLK:BUF.RCLK0 BUFR1:BUFR_DIVIDE[0] RCLK:MUX.RCLK1[0] IOCLK:BUF.RCLK1 RCLK:MUX.RCLK0[0] - DCI:NREF[0]
14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - BUFR0:BUFR_DIVIDE[3] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - BUFR0:MUX.I[0] - BUFR0:ENABLE BUFR1:BUFR_DIVIDE[3] RCLK:MUX.RCLK1[2] IDELAYCTRL:MUX.REFCLK[2] RCLK:MUX.RCLK0[2] - DCI:LVDIV2[1]
13 - DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - BUFR0:BUFR_DIVIDE[2] IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - BUFR1:MUX.I[0] IOCLK:VIOCLK_ENABLE[3] BUFR1:ENABLE BUFR1:BUFR_DIVIDE[2] RCLK:MUX.RCLK1[1] IDELAYCTRL:MUX.REFCLK[1] RCLK:MUX.RCLK0[1] - DCI:LVDIV2[0]
12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - BUFR0:BUFR_DIVIDE[1] - - IOCLK:BUF.IOCLK_N1 - BUFR1:MUX.I[1] - - BUFR1:BUFR_DIVIDE[1] RCLK:MUX.RCLK1[3] IDELAYCTRL:MUX.REFCLK[0] RCLK:MUX.RCLK0[3] - DCI:NREF[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFR0:BUFR_DIVIDE 0.14.14 0.14.13 0.14.12 0.14.15
BUFR1:BUFR_DIVIDE 0.22.14 0.22.13 0.22.12 0.22.15
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:ENABLE 0.21.14
BUFR1:ENABLE 0.21.13
DCI:ENABLE 0.0.14
DCI:QUIET 0.5.12
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
BUFR0:MUX.I 0.19.15 0.19.14
BUFR1:MUX.I 0.19.12 0.19.13
BUFIO0 0 0
CKINT0 0 1
CKINT1 1 0
BUFIO1 1 1
DCI:LVDIV2 0.27.14 0.27.13
DCI:NREF 0.27.12 0.27.15
DCI:TEST_ENABLE 0.5.13 0.0.15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.10.12 0.12.15 0.12.14 0.12.13 0.12.12
DCI:PMASK_TERM_SPLIT 0.11.15 0.10.15 0.11.14 0.10.14 0.10.13
DCI:PMASK_TERM_VCC 0.2.12 0.4.15 0.4.14 0.4.13 0.4.12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.1.12 0.1.13 0.1.14 0.1.15
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1
RCLK:MUX.RCLK0 0.25.12 0.25.14 0.25.13 0.25.15
RCLK:MUX.RCLK1 0.23.12 0.23.14 0.23.13 0.23.15
NONE 0 0 0 0
VRCLK_N0 0 0 0 1
VRCLK0 0 0 1 1
VRCLK_S0 0 1 0 1
VRCLK_N1 1 0 0 1
VRCLK1 1 0 1 1
VRCLK_S1 1 1 0 1

Tile HCLK_CENTER

Cells: 2

Bel IOCLK

virtex4 HCLK_CENTER bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_CENTER bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_CENTER bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_CENTER bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN
RDYoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
RSTinputTCELL1:IMUX.BYP7
UPPULSEOUToutputTCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_CENTER bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
DCIADDRESS1outputTCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
DCIADDRESS2outputTCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
DCIDATAoutputTCELL0:OUT.HALF.BOT7.TMIN, TCELL0:OUT.HALT.TOP7.TMIN
DCIDONEoutputTCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputTCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
DCISCLKoutputTCELL0:OUT.HALF.BOT6.TMIN, TCELL0:OUT.HALT.TOP6.TMIN
TSTCLKinputTCELL0:IMUX.BYP0
TSTHLNinputTCELL0:IMUX.BYP4
TSTHLPinputTCELL0:IMUX.BYP7
TSTRSTinputTCELL0:IMUX.BYP2

Bel wires

virtex4 HCLK_CENTER bel wires
WirePins
TCELL0:IMUX.BYP0DCI.TSTCLK
TCELL0:IMUX.BYP2DCI.TSTRST
TCELL0:IMUX.BYP4DCI.TSTHLN
TCELL0:IMUX.BYP7DCI.TSTHLP
TCELL0:OUT.HALF.BOT3.TMINDCI.DCIDONE
TCELL0:OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALF.BOT6.TMINDCI.DCISCLK
TCELL0:OUT.HALF.BOT7.TMINDCI.DCIDATA
TCELL0:OUT.HALT.TOP3.TMINDCI.DCIDONE
TCELL0:OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALT.TOP6.TMINDCI.DCISCLK
TCELL0:OUT.HALT.TOP7.TMINDCI.DCIDATA
TCELL1:IMUX.BYP7IDELAYCTRL.RST
TCELL1:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
TCELL1:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALT.TOP7.TMINDCI.DCIADDRESS2

Bitstream

virtex4 HCLK_CENTER bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - - IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - - - IOCLK:BUF.RCLK0 - - IOCLK:BUF.RCLK1 - - DCI:NREF[0]
14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - - IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - - - - - - IDELAYCTRL:MUX.REFCLK[2] - - DCI:LVDIV2[1]
13 DCI:CASCADE_FROM_ABOVE DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - - IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - - IOCLK:VIOCLK_ENABLE[3] - - - IDELAYCTRL:MUX.REFCLK[1] - - DCI:LVDIV2[0]
12 DCI:CASCADE_FROM_BELOW DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - - IOCLK:BUF.IOCLK_N1 - - - - - - IDELAYCTRL:MUX.REFCLK[0] - - DCI:NREF[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:CASCADE_FROM_ABOVE 0.0.13
DCI:CASCADE_FROM_BELOW 0.0.12
DCI:ENABLE 0.0.14
DCI:QUIET 0.5.12
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
DCI:LVDIV2 0.27.14 0.27.13
DCI:NREF 0.27.12 0.27.15
DCI:TEST_ENABLE 0.5.13 0.0.15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.10.12 0.12.15 0.12.14 0.12.13 0.12.12
DCI:PMASK_TERM_SPLIT 0.11.15 0.10.15 0.11.14 0.10.14 0.10.13
DCI:PMASK_TERM_VCC 0.2.12 0.4.15 0.4.14 0.4.13 0.4.12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.1.12 0.1.13 0.1.14 0.1.15
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_CENTER_ABOVE_CFG

Cells: 2

Bel IOCLK

virtex4 HCLK_CENTER_ABOVE_CFG bel IOCLK
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_CENTER_ABOVE_CFG bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_CENTER_ABOVE_CFG bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_CENTER_ABOVE_CFG bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL0:OUT.HALF.BOT0.TMIN, TCELL0:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL0:OUT.HALF.BOT2.TMIN, TCELL0:OUT.HALT.TOP2.TMIN
RDYoutputTCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
RSTinputTCELL0:IMUX.BYP7
UPPULSEOUToutputTCELL0:OUT.HALF.BOT1.TMIN, TCELL0:OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_CENTER_ABOVE_CFG bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN
DCIADDRESS1outputTCELL0:OUT.HALF.BOT6.TMIN, TCELL0:OUT.HALT.TOP6.TMIN
DCIADDRESS2outputTCELL0:OUT.HALF.BOT7.TMIN, TCELL0:OUT.HALT.TOP7.TMIN
DCIDATAoutputTCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
DCIDONEoutputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputTCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
DCISCLKoutputTCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
TSTCLKinputTCELL1:IMUX.BYP0
TSTHLNinputTCELL1:IMUX.BYP7
TSTHLPinputTCELL1:IMUX.BYP4
TSTRSTinputTCELL1:IMUX.BYP2

Bel wires

virtex4 HCLK_CENTER_ABOVE_CFG bel wires
WirePins
TCELL0:IMUX.BYP7IDELAYCTRL.RST
TCELL0:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL0:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL0:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL0:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL0:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL0:OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
TCELL0:OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
TCELL0:OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
TCELL0:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL0:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL0:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL0:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL0:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL0:OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
TCELL0:OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
TCELL0:OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
TCELL1:IMUX.BYP0DCI.TSTCLK
TCELL1:IMUX.BYP2DCI.TSTRST
TCELL1:IMUX.BYP4DCI.TSTHLP
TCELL1:IMUX.BYP7DCI.TSTHLN
TCELL1:OUT.HALF.BOT3.TMINDCI.DCIDONE
TCELL1:OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
TCELL1:OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
TCELL1:OUT.HALF.BOT6.TMINDCI.DCISCLK
TCELL1:OUT.HALF.BOT7.TMINDCI.DCIDATA
TCELL1:OUT.HALT.TOP3.TMINDCI.DCIDONE
TCELL1:OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
TCELL1:OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
TCELL1:OUT.HALT.TOP6.TMINDCI.DCISCLK
TCELL1:OUT.HALT.TOP7.TMINDCI.DCIDATA

Bitstream

virtex4 HCLK_CENTER_ABOVE_CFG bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
15 DCI:TEST_ENABLE[0] DCI:PREF[0] - - DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - - IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - - - IOCLK:BUF.RCLK0 - - IOCLK:BUF.RCLK1 - - DCI:NREF[0]
14 DCI:ENABLE DCI:PREF[1] - - DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - - IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - - - - - - IDELAYCTRL:MUX.REFCLK[2] - - DCI:LVDIV2[1]
13 DCI:CASCADE_FROM_ABOVE DCI:PREF[2] - - DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - - IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - - IOCLK:VIOCLK_ENABLE[3] - - - IDELAYCTRL:MUX.REFCLK[1] - - DCI:LVDIV2[0]
12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - - IOCLK:BUF.IOCLK_N1 - - - - - - IDELAYCTRL:MUX.REFCLK[0] - - DCI:NREF[1]
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:CASCADE_FROM_ABOVE 0.0.13
DCI:ENABLE 0.0.14
DCI:QUIET 0.5.12
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
DCI:LVDIV2 0.27.14 0.27.13
DCI:NREF 0.27.12 0.27.15
DCI:TEST_ENABLE 0.5.13 0.0.15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.10.12 0.12.15 0.12.14 0.12.13 0.12.12
DCI:PMASK_TERM_SPLIT 0.11.15 0.10.15 0.11.14 0.10.14 0.10.13
DCI:PMASK_TERM_VCC 0.2.12 0.4.15 0.4.14 0.4.13 0.4.12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.1.12 0.1.13 0.1.14 0.1.15
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_IOBDCM

Cells: 2

Bel IOCLK

virtex4 HCLK_IOBDCM bel IOCLK
PinDirectionWires

Bel HCLK_DCM_HROW

virtex4 HCLK_IOBDCM bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM_N

virtex4 HCLK_IOBDCM bel HCLK_DCM_N
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_IOBDCM bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_IOBDCM bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_IOBDCM bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN
RDYoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
RSTinputTCELL1:IMUX.BYP7
UPPULSEOUToutputTCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_IOBDCM bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
DCIADDRESS1outputTCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
DCIADDRESS2outputTCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
DCIDATAoutputTCELL0:OUT.HALF.BOT7.TMIN, TCELL0:OUT.HALT.TOP7.TMIN
DCIDONEoutputTCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputTCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputTCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
DCISCLKoutputTCELL0:OUT.HALF.BOT6.TMIN, TCELL0:OUT.HALT.TOP6.TMIN
TSTCLKinputTCELL0:IMUX.BYP0
TSTHLNinputTCELL0:IMUX.BYP4
TSTHLPinputTCELL0:IMUX.BYP7
TSTRSTinputTCELL0:IMUX.BYP2

Bel wires

virtex4 HCLK_IOBDCM bel wires
WirePins
TCELL0:IMUX.BYP0DCI.TSTCLK
TCELL0:IMUX.BYP2DCI.TSTRST
TCELL0:IMUX.BYP4DCI.TSTHLN
TCELL0:IMUX.BYP7DCI.TSTHLP
TCELL0:OUT.HALF.BOT3.TMINDCI.DCIDONE
TCELL0:OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALF.BOT6.TMINDCI.DCISCLK
TCELL0:OUT.HALF.BOT7.TMINDCI.DCIDATA
TCELL0:OUT.HALT.TOP3.TMINDCI.DCIDONE
TCELL0:OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
TCELL0:OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
TCELL0:OUT.HALT.TOP6.TMINDCI.DCISCLK
TCELL0:OUT.HALT.TOP7.TMINDCI.DCIDATA
TCELL1:IMUX.BYP7IDELAYCTRL.RST
TCELL1:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
TCELL1:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL1:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL1:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL1:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL1:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL1:OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
TCELL1:OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
TCELL1:OUT.HALT.TOP7.TMINDCI.DCIADDRESS2

Bitstream

virtex4 HCLK_IOBDCM bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
15 DCI:TEST_ENABLE[0] DCI:PREF[0] - HCLK_DCM_N:BUF.GIOB_U15 DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - HCLK_DCM_N:BUF.HCLK_U3 IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - HCLK_DCM_N:COMMON[1] - IOCLK:BUF.RCLK0 HCLK_DCM_N:BUF.HCLK_U2 HCLK_DCM_N:BUF.MGT_U3 IOCLK:BUF.RCLK1 HCLK_DCM_N:BUF.GIOB_U12 HCLK_DCM_N:BUF.MGT_U2 DCI:NREF[0] -
14 DCI:ENABLE DCI:PREF[1] - HCLK_DCM_N:BUF.GIOB_U14 DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - HCLK_DCM_N:COMMON[0] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - HCLK_DCM_N:BUF.HCLK_U4 - HCLK_DCM_N:BUF.GIOB_U1 HCLK_DCM_N:BUF.HCLK_U6 HCLK_DCM_N:BUF.GIOB_U7 IDELAYCTRL:MUX.REFCLK[2] HCLK_DCM_N:BUF.GIOB_U11 HCLK_DCM_N:BUF.MGT_U1 DCI:LVDIV2[1] -
13 - DCI:PREF[2] - HCLK_DCM_N:BUF.GIOB_U0 DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - HCLK_DCM_N:BUF.MGT_U0 IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - HCLK_DCM_N:BUF.GIOB_U3 IOCLK:VIOCLK_ENABLE[3] HCLK_DCM_N:COMMON[2] HCLK_DCM_N:BUF.GIOB_U2 HCLK_DCM_N:BUF.HCLK_U5 IDELAYCTRL:MUX.REFCLK[1] HCLK_DCM_N:BUF.HCLK_U1 HCLK_DCM_N:BUF.GIOB_U10 DCI:LVDIV2[0] HCLK_DCM_N:BUF.GIOB_U4
12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - HCLK_DCM_N:COMMON_MGT IOCLK:BUF.IOCLK_N1 - HCLK_DCM_N:BUF.GIOB_U13 - HCLK_DCM_N:BUF.HCLK_U0 HCLK_DCM_N:BUF.GIOB_U9 HCLK_DCM_N:BUF.GIOB_U8 IDELAYCTRL:MUX.REFCLK[0] HCLK_DCM_N:BUF.GIOB_U6 HCLK_DCM_N:BUF.HCLK_U7 DCI:NREF[1] HCLK_DCM_N:BUF.GIOB_U5
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:ENABLE 0.0.14
DCI:QUIET 0.5.12
HCLK_DCM_N:BUF.GIOB_U0 0.3.13
HCLK_DCM_N:BUF.GIOB_U1 0.21.14
HCLK_DCM_N:BUF.GIOB_U10 0.26.13
HCLK_DCM_N:BUF.GIOB_U11 0.25.14
HCLK_DCM_N:BUF.GIOB_U12 0.25.15
HCLK_DCM_N:BUF.GIOB_U13 0.19.12
HCLK_DCM_N:BUF.GIOB_U14 0.3.14
HCLK_DCM_N:BUF.GIOB_U15 0.3.15
HCLK_DCM_N:BUF.GIOB_U2 0.22.13
HCLK_DCM_N:BUF.GIOB_U3 0.19.13
HCLK_DCM_N:BUF.GIOB_U4 0.28.13
HCLK_DCM_N:BUF.GIOB_U5 0.28.12
HCLK_DCM_N:BUF.GIOB_U6 0.25.12
HCLK_DCM_N:BUF.GIOB_U7 0.23.14
HCLK_DCM_N:BUF.GIOB_U8 0.23.12
HCLK_DCM_N:BUF.GIOB_U9 0.22.12
HCLK_DCM_N:BUF.HCLK_U0 0.21.12
HCLK_DCM_N:BUF.HCLK_U1 0.25.13
HCLK_DCM_N:BUF.HCLK_U2 0.22.15
HCLK_DCM_N:BUF.HCLK_U3 0.14.15
HCLK_DCM_N:BUF.HCLK_U4 0.19.14
HCLK_DCM_N:BUF.HCLK_U5 0.23.13
HCLK_DCM_N:BUF.HCLK_U6 0.22.14
HCLK_DCM_N:BUF.HCLK_U7 0.26.12
HCLK_DCM_N:BUF.MGT_U0 0.14.13
HCLK_DCM_N:BUF.MGT_U1 0.26.14
HCLK_DCM_N:BUF.MGT_U2 0.26.15
HCLK_DCM_N:BUF.MGT_U3 0.23.15
HCLK_DCM_N:COMMON_MGT 0.16.12
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
DCI:LVDIV2 0.27.14 0.27.13
DCI:NREF 0.27.12 0.27.15
DCI:TEST_ENABLE 0.5.13 0.0.15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.10.12 0.12.15 0.12.14 0.12.13 0.12.12
DCI:PMASK_TERM_SPLIT 0.11.15 0.10.15 0.11.14 0.10.14 0.10.13
DCI:PMASK_TERM_VCC 0.2.12 0.4.15 0.4.14 0.4.13 0.4.12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.1.12 0.1.13 0.1.14 0.1.15
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
HCLK_DCM_N:COMMON 0.21.13 0.19.15 0.14.14
non-inverted [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_DCMIOB

Cells: 2

Bel IOCLK

virtex4 HCLK_DCMIOB bel IOCLK
PinDirectionWires

Bel HCLK_DCM_HROW

virtex4 HCLK_DCMIOB bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM_S

virtex4 HCLK_DCMIOB bel HCLK_DCM_S
PinDirectionWires

Bel BUFIO0

virtex4 HCLK_DCMIOB bel BUFIO0
PinDirectionWires

Bel BUFIO1

virtex4 HCLK_DCMIOB bel BUFIO1
PinDirectionWires

Bel IDELAYCTRL

virtex4 HCLK_DCMIOB bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL0:OUT.HALF.BOT0.TMIN, TCELL0:OUT.HALT.TOP0.TMIN
OUTN1outputTCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
OUTN65outputTCELL0:OUT.HALF.BOT2.TMIN, TCELL0:OUT.HALT.TOP2.TMIN
RDYoutputTCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
RSTinputTCELL0:IMUX.BYP7
UPPULSEOUToutputTCELL0:OUT.HALF.BOT1.TMIN, TCELL0:OUT.HALT.TOP1.TMIN

Bel DCI

virtex4 HCLK_DCMIOB bel DCI
PinDirectionWires
DCIADDRESS0outputTCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN
DCIADDRESS1outputTCELL0:OUT.HALF.BOT6.TMIN, TCELL0:OUT.HALT.TOP6.TMIN
DCIADDRESS2outputTCELL0:OUT.HALF.BOT7.TMIN, TCELL0:OUT.HALT.TOP7.TMIN
DCIDATAoutputTCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
DCIDONEoutputTCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
DCIIOUPDATEoutputTCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
DCIREFIOUPDATEoutputTCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
DCISCLKoutputTCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
TSTCLKinputTCELL1:IMUX.BYP0
TSTHLNinputTCELL1:IMUX.BYP7
TSTHLPinputTCELL1:IMUX.BYP4
TSTRSTinputTCELL1:IMUX.BYP2

Bel wires

virtex4 HCLK_DCMIOB bel wires
WirePins
TCELL0:IMUX.BYP7IDELAYCTRL.RST
TCELL0:OUT.HALF.BOT0.TMINIDELAYCTRL.DNPULSEOUT
TCELL0:OUT.HALF.BOT1.TMINIDELAYCTRL.UPPULSEOUT
TCELL0:OUT.HALF.BOT2.TMINIDELAYCTRL.OUTN65
TCELL0:OUT.HALF.BOT3.TMINIDELAYCTRL.OUTN1
TCELL0:OUT.HALF.BOT4.TMINIDELAYCTRL.RDY
TCELL0:OUT.HALF.BOT5.TMINDCI.DCIADDRESS0
TCELL0:OUT.HALF.BOT6.TMINDCI.DCIADDRESS1
TCELL0:OUT.HALF.BOT7.TMINDCI.DCIADDRESS2
TCELL0:OUT.HALT.TOP0.TMINIDELAYCTRL.DNPULSEOUT
TCELL0:OUT.HALT.TOP1.TMINIDELAYCTRL.UPPULSEOUT
TCELL0:OUT.HALT.TOP2.TMINIDELAYCTRL.OUTN65
TCELL0:OUT.HALT.TOP3.TMINIDELAYCTRL.OUTN1
TCELL0:OUT.HALT.TOP4.TMINIDELAYCTRL.RDY
TCELL0:OUT.HALT.TOP5.TMINDCI.DCIADDRESS0
TCELL0:OUT.HALT.TOP6.TMINDCI.DCIADDRESS1
TCELL0:OUT.HALT.TOP7.TMINDCI.DCIADDRESS2
TCELL1:IMUX.BYP0DCI.TSTCLK
TCELL1:IMUX.BYP2DCI.TSTRST
TCELL1:IMUX.BYP4DCI.TSTHLP
TCELL1:IMUX.BYP7DCI.TSTHLN
TCELL1:OUT.HALF.BOT3.TMINDCI.DCIDONE
TCELL1:OUT.HALF.BOT4.TMINDCI.DCIREFIOUPDATE
TCELL1:OUT.HALF.BOT5.TMINDCI.DCIIOUPDATE
TCELL1:OUT.HALF.BOT6.TMINDCI.DCISCLK
TCELL1:OUT.HALF.BOT7.TMINDCI.DCIDATA
TCELL1:OUT.HALT.TOP3.TMINDCI.DCIDONE
TCELL1:OUT.HALT.TOP4.TMINDCI.DCIREFIOUPDATE
TCELL1:OUT.HALT.TOP5.TMINDCI.DCIIOUPDATE
TCELL1:OUT.HALT.TOP6.TMINDCI.DCISCLK
TCELL1:OUT.HALT.TOP7.TMINDCI.DCIDATA

Bitstream

virtex4 HCLK_DCMIOB bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
15 DCI:TEST_ENABLE[0] DCI:PREF[0] - HCLK_DCM_S:BUF.GIOB_D15 DCI:PMASK_TERM_VCC[3] - - IOCLK:BUF.HCLK3 IOCLK:BUF.HCLK7 - DCI:PMASK_TERM_SPLIT[3] DCI:PMASK_TERM_SPLIT[4] DCI:NMASK_TERM_SPLIT[3] - HCLK_DCM_S:BUF.HCLK_D3 IOCLK:VIOCLK_ENABLE[2] IOCLK:BUF.VIOCLK1 IOCLK:BUF.IOCLK_N0 - HCLK_DCM_S:COMMON[1] - IOCLK:BUF.RCLK0 HCLK_DCM_S:BUF.HCLK_D2 HCLK_DCM_S:BUF.MGT_D3 IOCLK:BUF.RCLK1 HCLK_DCM_S:BUF.GIOB_D12 HCLK_DCM_S:BUF.MGT_D2 DCI:NREF[0] -
14 DCI:ENABLE DCI:PREF[1] - HCLK_DCM_S:BUF.GIOB_D14 DCI:PMASK_TERM_VCC[2] - - IOCLK:BUF.HCLK2 IOCLK:BUF.HCLK6 - DCI:PMASK_TERM_SPLIT[1] DCI:PMASK_TERM_SPLIT[2] DCI:NMASK_TERM_SPLIT[2] - HCLK_DCM_S:COMMON[0] IOCLK:VIOCLK_ENABLE[1] IOCLK:BUF.VIOCLK0 IOCLK:BUF.IOCLK_S0 - HCLK_DCM_S:BUF.HCLK_D4 - HCLK_DCM_S:BUF.GIOB_D1 HCLK_DCM_S:BUF.HCLK_D6 HCLK_DCM_S:BUF.GIOB_D7 IDELAYCTRL:MUX.REFCLK[2] HCLK_DCM_S:BUF.GIOB_D11 HCLK_DCM_S:BUF.MGT_D1 DCI:LVDIV2[1] -
13 - DCI:PREF[2] - HCLK_DCM_S:BUF.GIOB_D0 DCI:PMASK_TERM_VCC[1] DCI:TEST_ENABLE[1] - IOCLK:BUF.HCLK1 IOCLK:BUF.HCLK5 - DCI:PMASK_TERM_SPLIT[0] - DCI:NMASK_TERM_SPLIT[1] - HCLK_DCM_S:BUF.MGT_D0 IOCLK:VIOCLK_ENABLE[0] - IOCLK:BUF.IOCLK_S1 - HCLK_DCM_S:BUF.GIOB_D3 IOCLK:VIOCLK_ENABLE[3] HCLK_DCM_S:COMMON[2] HCLK_DCM_S:BUF.GIOB_D2 HCLK_DCM_S:BUF.HCLK_D5 IDELAYCTRL:MUX.REFCLK[1] HCLK_DCM_S:BUF.HCLK_D1 HCLK_DCM_S:BUF.GIOB_D10 DCI:LVDIV2[0] HCLK_DCM_S:BUF.GIOB_D4
12 - DCI:PREF[3] DCI:PMASK_TERM_VCC[4] - DCI:PMASK_TERM_VCC[0] DCI:QUIET - IOCLK:BUF.HCLK0 IOCLK:BUF.HCLK4 - DCI:NMASK_TERM_SPLIT[4] IDELAYCTRL:ENABLE DCI:NMASK_TERM_SPLIT[0] - - - HCLK_DCM_S:COMMON_MGT IOCLK:BUF.IOCLK_N1 - HCLK_DCM_S:BUF.GIOB_D13 - HCLK_DCM_S:BUF.HCLK_D0 HCLK_DCM_S:BUF.GIOB_D9 HCLK_DCM_S:BUF.GIOB_D8 IDELAYCTRL:MUX.REFCLK[0] HCLK_DCM_S:BUF.GIOB_D6 HCLK_DCM_S:BUF.HCLK_D7 DCI:NREF[1] HCLK_DCM_S:BUF.GIOB_D5
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
DCI:ENABLE 0.0.14
DCI:QUIET 0.5.12
HCLK_DCM_S:BUF.GIOB_D0 0.3.13
HCLK_DCM_S:BUF.GIOB_D1 0.21.14
HCLK_DCM_S:BUF.GIOB_D10 0.26.13
HCLK_DCM_S:BUF.GIOB_D11 0.25.14
HCLK_DCM_S:BUF.GIOB_D12 0.25.15
HCLK_DCM_S:BUF.GIOB_D13 0.19.12
HCLK_DCM_S:BUF.GIOB_D14 0.3.14
HCLK_DCM_S:BUF.GIOB_D15 0.3.15
HCLK_DCM_S:BUF.GIOB_D2 0.22.13
HCLK_DCM_S:BUF.GIOB_D3 0.19.13
HCLK_DCM_S:BUF.GIOB_D4 0.28.13
HCLK_DCM_S:BUF.GIOB_D5 0.28.12
HCLK_DCM_S:BUF.GIOB_D6 0.25.12
HCLK_DCM_S:BUF.GIOB_D7 0.23.14
HCLK_DCM_S:BUF.GIOB_D8 0.23.12
HCLK_DCM_S:BUF.GIOB_D9 0.22.12
HCLK_DCM_S:BUF.HCLK_D0 0.21.12
HCLK_DCM_S:BUF.HCLK_D1 0.25.13
HCLK_DCM_S:BUF.HCLK_D2 0.22.15
HCLK_DCM_S:BUF.HCLK_D3 0.14.15
HCLK_DCM_S:BUF.HCLK_D4 0.19.14
HCLK_DCM_S:BUF.HCLK_D5 0.23.13
HCLK_DCM_S:BUF.HCLK_D6 0.22.14
HCLK_DCM_S:BUF.HCLK_D7 0.26.12
HCLK_DCM_S:BUF.MGT_D0 0.14.13
HCLK_DCM_S:BUF.MGT_D1 0.26.14
HCLK_DCM_S:BUF.MGT_D2 0.26.15
HCLK_DCM_S:BUF.MGT_D3 0.23.15
HCLK_DCM_S:COMMON_MGT 0.16.12
IDELAYCTRL:ENABLE 0.11.12
IOCLK:BUF.HCLK0 0.7.12
IOCLK:BUF.HCLK1 0.7.13
IOCLK:BUF.HCLK2 0.7.14
IOCLK:BUF.HCLK3 0.7.15
IOCLK:BUF.HCLK4 0.8.12
IOCLK:BUF.HCLK5 0.8.13
IOCLK:BUF.HCLK6 0.8.14
IOCLK:BUF.HCLK7 0.8.15
IOCLK:BUF.IOCLK_N0 0.17.15
IOCLK:BUF.IOCLK_N1 0.17.12
IOCLK:BUF.IOCLK_S0 0.17.14
IOCLK:BUF.IOCLK_S1 0.17.13
IOCLK:BUF.RCLK0 0.21.15
IOCLK:BUF.RCLK1 0.24.15
IOCLK:BUF.VIOCLK0 0.16.14
IOCLK:BUF.VIOCLK1 0.16.15
non-inverted [0]
DCI:LVDIV2 0.27.14 0.27.13
DCI:NREF 0.27.12 0.27.15
DCI:TEST_ENABLE 0.5.13 0.0.15
non-inverted [1] [0]
DCI:NMASK_TERM_SPLIT 0.10.12 0.12.15 0.12.14 0.12.13 0.12.12
DCI:PMASK_TERM_SPLIT 0.11.15 0.10.15 0.11.14 0.10.14 0.10.13
DCI:PMASK_TERM_VCC 0.2.12 0.4.15 0.4.14 0.4.13 0.4.12
non-inverted [4] [3] [2] [1] [0]
DCI:PREF 0.1.12 0.1.13 0.1.14 0.1.15
IOCLK:VIOCLK_ENABLE 0.20.13 0.15.15 0.15.14 0.15.13
non-inverted [3] [2] [1] [0]
HCLK_DCM_S:COMMON 0.21.13 0.19.15 0.14.14
non-inverted [2] [1] [0]
IDELAYCTRL:MUX.REFCLK 0.24.14 0.24.13 0.24.12
HCLK0 0 0 0
HCLK1 0 0 1
HCLK2 0 1 0
HCLK3 0 1 1
HCLK4 1 0 0
HCLK5 1 0 1
HCLK6 1 1 0
HCLK7 1 1 1

Tile HCLK_DCM

Cells: 0

Bel HCLK_DCM_HROW

virtex4 HCLK_DCM bel HCLK_DCM_HROW
PinDirectionWires

Bel HCLK_DCM

virtex4 HCLK_DCM bel HCLK_DCM
PinDirectionWires

Bitstream

virtex4 HCLK_DCM bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
15 - - - HCLK_DCM:BUF.GIOB_D11 - HCLK_DCM:BUF.MGT_U1 - - - - HCLK_DCM:BUF.MGT_U0 HCLK_DCM:BUF.MGT_U2 HCLK_DCM:BUF.MGT_D0 - HCLK_DCM:BUF.HCLK_U2 - HCLK_DCM:BUF.MGT_U3 HCLK_DCM:BUF.GIOB_U0 - - HCLK_DCM:BUF.GIOB_D4 HCLK_DCM:BUF.HCLK_D3 HCLK_DCM:BUF.HCLK_D7 HCLK_DCM:BUF.GIOB_D2 HCLK_DCM:BUF.HCLK_D1 HCLK_DCM:BUF.GIOB_U5 HCLK_DCM:BUF.GIOB_U7 HCLK_DCM:COMMON
14 - - - HCLK_DCM:BUF.MGT_D3 - HCLK_DCM:BUF.GIOB_U9 - - - - HCLK_DCM:BUF.GIOB_U12 HCLK_DCM:BUF.GIOB_U14 HCLK_DCM:BUF.GIOB_D8 - HCLK_DCM:BUF.HCLK_U6 - HCLK_DCM:BUF.GIOB_U11 HCLK_DCM:BUF.HCLK_U0 - - HCLK_DCM:BUF.GIOB_D0 - HCLK_DCM:BUF.GIOB_D7 HCLK_DCM:BUF.HCLK_D6 HCLK_DCM:BUF.HCLK_D5 HCLK_DCM:BUF.GIOB_U1 HCLK_DCM:BUF.HCLK_U3 HCLK_DCM:COMMON_MGT
13 - - - HCLK_DCM:BUF.GIOB_D10 - HCLK_DCM:BUF.GIOB_U13 - - - - HCLK_DCM:BUF.GIOB_D12 HCLK_DCM:BUF.GIOB_D14 HCLK_DCM:BUF.MGT_D1 - HCLK_DCM:BUF.GIOB_U2 - HCLK_DCM:BUF.GIOB_U15 HCLK_DCM:BUF.HCLK_U4 - - HCLK_DCM:BUF.HCLK_D4 - HCLK_DCM:BUF.GIOB_D3 HCLK_DCM:BUF.HCLK_D2 HCLK_DCM:BUF.GIOB_D5 HCLK_DCM:BUF.HCLK_U5 HCLK_DCM:BUF.HCLK_U7 HCLK_DCM:COMMON_HCLK_GIOB[2]
12 - - - HCLK_DCM:BUF.MGT_D2 - HCLK_DCM:BUF.GIOB_U8 - - - - HCLK_DCM:BUF.GIOB_D13 HCLK_DCM:BUF.GIOB_D15 HCLK_DCM:BUF.GIOB_D9 - HCLK_DCM:BUF.GIOB_U6 - HCLK_DCM:BUF.GIOB_U10 HCLK_DCM:BUF.GIOB_U4 - HCLK_DCM:COMMON_HCLK_GIOB[0] HCLK_DCM:BUF.HCLK_D0 HCLK_DCM:COMMON_HCLK_GIOB[1] HCLK_DCM:BUF.GIOB_D6 - HCLK_DCM:BUF.GIOB_D1 HCLK_DCM:BUF.HCLK_U1 HCLK_DCM:BUF.GIOB_U3 -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HCLK_DCM:BUF.GIOB_D0 0.20.14
HCLK_DCM:BUF.GIOB_D1 0.24.12
HCLK_DCM:BUF.GIOB_D10 0.3.13
HCLK_DCM:BUF.GIOB_D11 0.3.15
HCLK_DCM:BUF.GIOB_D12 0.10.13
HCLK_DCM:BUF.GIOB_D13 0.10.12
HCLK_DCM:BUF.GIOB_D14 0.11.13
HCLK_DCM:BUF.GIOB_D15 0.11.12
HCLK_DCM:BUF.GIOB_D2 0.23.15
HCLK_DCM:BUF.GIOB_D3 0.22.13
HCLK_DCM:BUF.GIOB_D4 0.20.15
HCLK_DCM:BUF.GIOB_D5 0.24.13
HCLK_DCM:BUF.GIOB_D6 0.22.12
HCLK_DCM:BUF.GIOB_D7 0.22.14
HCLK_DCM:BUF.GIOB_D8 0.12.14
HCLK_DCM:BUF.GIOB_D9 0.12.12
HCLK_DCM:BUF.GIOB_U0 0.17.15
HCLK_DCM:BUF.GIOB_U1 0.25.14
HCLK_DCM:BUF.GIOB_U10 0.16.12
HCLK_DCM:BUF.GIOB_U11 0.16.14
HCLK_DCM:BUF.GIOB_U12 0.10.14
HCLK_DCM:BUF.GIOB_U13 0.5.13
HCLK_DCM:BUF.GIOB_U14 0.11.14
HCLK_DCM:BUF.GIOB_U15 0.16.13
HCLK_DCM:BUF.GIOB_U2 0.14.13
HCLK_DCM:BUF.GIOB_U3 0.26.12
HCLK_DCM:BUF.GIOB_U4 0.17.12
HCLK_DCM:BUF.GIOB_U5 0.25.15
HCLK_DCM:BUF.GIOB_U6 0.14.12
HCLK_DCM:BUF.GIOB_U7 0.26.15
HCLK_DCM:BUF.GIOB_U8 0.5.12
HCLK_DCM:BUF.GIOB_U9 0.5.14
HCLK_DCM:BUF.HCLK_D0 0.20.12
HCLK_DCM:BUF.HCLK_D1 0.24.15
HCLK_DCM:BUF.HCLK_D2 0.23.13
HCLK_DCM:BUF.HCLK_D3 0.21.15
HCLK_DCM:BUF.HCLK_D4 0.20.13
HCLK_DCM:BUF.HCLK_D5 0.24.14
HCLK_DCM:BUF.HCLK_D6 0.23.14
HCLK_DCM:BUF.HCLK_D7 0.22.15
HCLK_DCM:BUF.HCLK_U0 0.17.14
HCLK_DCM:BUF.HCLK_U1 0.25.12
HCLK_DCM:BUF.HCLK_U2 0.14.15
HCLK_DCM:BUF.HCLK_U3 0.26.14
HCLK_DCM:BUF.HCLK_U4 0.17.13
HCLK_DCM:BUF.HCLK_U5 0.25.13
HCLK_DCM:BUF.HCLK_U6 0.14.14
HCLK_DCM:BUF.HCLK_U7 0.26.13
HCLK_DCM:BUF.MGT_D0 0.12.15
HCLK_DCM:BUF.MGT_D1 0.12.13
HCLK_DCM:BUF.MGT_D2 0.3.12
HCLK_DCM:BUF.MGT_D3 0.3.14
HCLK_DCM:BUF.MGT_U0 0.10.15
HCLK_DCM:BUF.MGT_U1 0.5.15
HCLK_DCM:BUF.MGT_U2 0.11.15
HCLK_DCM:BUF.MGT_U3 0.16.15
HCLK_DCM:COMMON 0.27.15
HCLK_DCM:COMMON_MGT 0.27.14
non-inverted [0]
HCLK_DCM:COMMON_HCLK_GIOB 0.27.13 0.21.12 0.19.12
non-inverted [2] [1] [0]