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Clock column buffers

Tile HCLK

Cells: 1

Bel HCLK

virtex4 HCLK bel HCLK
PinDirectionWires
HCLK_O0outputHCLK0
HCLK_O1outputHCLK1
HCLK_O2outputHCLK2
HCLK_O3outputHCLK3
HCLK_O4outputHCLK4
HCLK_O5outputHCLK5
HCLK_O6outputHCLK6
HCLK_O7outputHCLK7
RCLK_O0outputRCLK0
RCLK_O1outputRCLK1

Bel GLOBALSIG

virtex4 HCLK bel GLOBALSIG
PinDirectionWires

Bel wires

virtex4 HCLK bel wires
WirePins
HCLK0HCLK.HCLK_O0
HCLK1HCLK.HCLK_O1
HCLK2HCLK.HCLK_O2
HCLK3HCLK.HCLK_O3
HCLK4HCLK.HCLK_O4
HCLK5HCLK.HCLK_O5
HCLK6HCLK.HCLK_O6
HCLK7HCLK.HCLK_O7
RCLK0HCLK.RCLK_O0
RCLK1HCLK.RCLK_O1

Bitstream

virtex4 HCLK rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B15 - - - - - - - - - HCLK:BUF.HCLK0 - - - HCLK:BUF.HCLK4 - - - - HCLK:BUF.RCLK1
B14 - - - - - - - - - HCLK:BUF.HCLK1 - - - HCLK:BUF.HCLK5 - - - - HCLK:BUF.RCLK0
B13 - - - - - - - - - HCLK:BUF.HCLK2 - - - HCLK:BUF.HCLK6 - - - - -
B12 - - - - - - - - - HCLK:BUF.HCLK3 - - - HCLK:BUF.HCLK7 - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - -
HCLK:BUF.HCLK0 0.F9.B15
HCLK:BUF.HCLK1 0.F9.B14
HCLK:BUF.HCLK2 0.F9.B13
HCLK:BUF.HCLK3 0.F9.B12
HCLK:BUF.HCLK4 0.F13.B15
HCLK:BUF.HCLK5 0.F13.B14
HCLK:BUF.HCLK6 0.F13.B13
HCLK:BUF.HCLK7 0.F13.B12
HCLK:BUF.RCLK0 0.F18.B14
HCLK:BUF.RCLK1 0.F18.B15
non-inverted [0]

Tile HCLK_TERM

Cells: 0

Bitstream

virtex4 HCLK_TERM rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6
B14 - - - - - - HCLK_TERM:HCLK_ENABLE[2]
B13 - - - - - - HCLK_TERM:HCLK_ENABLE[1]
B12 - - - - - - HCLK_TERM:HCLK_ENABLE[0]
B11 - - - - - - -
B10 - - - - - - -
B9 - - - - - - -
B8 - - - - - - -
B7 - - - - - - -
B6 - - - - - - -
B5 - - - - - - -
B4 - - - - - - -
B3 - - - - - - -
B2 - - - - - - -
B1 - - - - - - -
B0 - - - - - - -
HCLK_TERM:HCLK_ENABLE 0.F6.B14 0.F6.B13 0.F6.B12
non-inverted [2] [1] [0]