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Clock column buffers

Tile HCLK

Cells: 1 IRIs: 0

Bel HCLK

virtex4 HCLK bel HCLK
PinDirectionWires
HCLK_O0outputHCLK0
HCLK_O1outputHCLK1
HCLK_O2outputHCLK2
HCLK_O3outputHCLK3
HCLK_O4outputHCLK4
HCLK_O5outputHCLK5
HCLK_O6outputHCLK6
HCLK_O7outputHCLK7
RCLK_O0outputRCLK0
RCLK_O1outputRCLK1

Bel GLOBALSIG

virtex4 HCLK bel GLOBALSIG
PinDirectionWires

Bel wires

virtex4 HCLK bel wires
WirePins
HCLK0HCLK.HCLK_O0
HCLK1HCLK.HCLK_O1
HCLK2HCLK.HCLK_O2
HCLK3HCLK.HCLK_O3
HCLK4HCLK.HCLK_O4
HCLK5HCLK.HCLK_O5
HCLK6HCLK.HCLK_O6
HCLK7HCLK.HCLK_O7
RCLK0HCLK.RCLK_O0
RCLK1HCLK.RCLK_O1

Bitstream

virtex4 HCLK bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
15 - - - - - - - - - HCLK:BUF.HCLK0 - - - HCLK:BUF.HCLK4 - - - - HCLK:BUF.RCLK1
14 - - - - - - - - - HCLK:BUF.HCLK1 - - - HCLK:BUF.HCLK5 - - - - HCLK:BUF.RCLK0
13 - - - - - - - - - HCLK:BUF.HCLK2 - - - HCLK:BUF.HCLK6 - - - - -
12 - - - - - - - - - HCLK:BUF.HCLK3 - - - HCLK:BUF.HCLK7 - - - - -
11 - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - -
HCLK:BUF.HCLK0 0.9.15
HCLK:BUF.HCLK1 0.9.14
HCLK:BUF.HCLK2 0.9.13
HCLK:BUF.HCLK3 0.9.12
HCLK:BUF.HCLK4 0.13.15
HCLK:BUF.HCLK5 0.13.14
HCLK:BUF.HCLK6 0.13.13
HCLK:BUF.HCLK7 0.13.12
HCLK:BUF.RCLK0 0.18.14
HCLK:BUF.RCLK1 0.18.15
non-inverted [0]

Tile HCLK_TERM

Cells: 0 IRIs: 0

Bitstream

virtex4 HCLK_TERM bittile 0
BitFrame
0 1 2 3 4 5 6
14 - - - - - - HCLK_TERM:HCLK_ENABLE[2]
13 - - - - - - HCLK_TERM:HCLK_ENABLE[1]
12 - - - - - - HCLK_TERM:HCLK_ENABLE[0]
11 - - - - - - -
10 - - - - - - -
9 - - - - - - -
8 - - - - - - -
7 - - - - - - -
6 - - - - - - -
5 - - - - - - -
4 - - - - - - -
3 - - - - - - -
2 - - - - - - -
1 - - - - - - -
0 - - - - - - -
HCLK_TERM:HCLK_ENABLE 0.6.14 0.6.13 0.6.12
non-inverted [2] [1] [0]