Clock spine multiplexers

Tile CLK_TERM

Cells: 1

Switchbox HROW_INT

virtex4 CLK_TERM wire support GCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15], GCLK[16], GCLK[17], GCLK[18], GCLK[19], GCLK[20], GCLK[21], GCLK[22], GCLK[23], GCLK[24], GCLK[25], GCLK[26], GCLK[27], GCLK[28], GCLK[29], GCLK[30], GCLK[31]
Bit
MAIN[0][79]

virtex4 CLK_TERM wire support GIOB[0], GIOB[1], GIOB[2], GIOB[3], GIOB[4], GIOB[5], GIOB[6], GIOB[7], GIOB[8], GIOB[9], GIOB[10], GIOB[11], GIOB[12], GIOB[13], GIOB[14], GIOB[15]
Bit
MAIN[0][12]

Bitstream

virtex4 CLK_TERM rect MAIN
Bit	Frame
Bit	F0	F1	F2
B79	HROW_INT: wire support (GCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15], GCLK[16], GCLK[17], GCLK[18], GCLK[19], GCLK[20], GCLK[21], GCLK[22], GCLK[23], GCLK[24], GCLK[25], GCLK[26], GCLK[27], GCLK[28], GCLK[29], GCLK[30], GCLK[31]) bit 0	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	HROW_INT: wire support (GIOB[0], GIOB[1], GIOB[2], GIOB[3], GIOB[4], GIOB[5], GIOB[6], GIOB[7], GIOB[8], GIOB[9], GIOB[10], GIOB[11], GIOB[12], GIOB[13], GIOB[14], GIOB[15]) bit 0	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

Tile CLK_IOB_S

Cells: 16

Switchbox CLK_INT

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[0]
Bits					Destination
MAIN[1][0][18]	MAIN[1][0][16]	MAIN[1][0][15]	MAIN[1][0][14]	MAIN[1][0][11]	CELL[0].GIOB[0]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[0].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[1]
Bits					Destination
MAIN[1][0][38]	MAIN[1][0][36]	MAIN[1][0][35]	MAIN[1][0][34]	MAIN[1][0][31]	CELL[0].GIOB[1]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[1].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[2]
Bits					Destination
MAIN[1][2][18]	MAIN[1][2][16]	MAIN[1][2][15]	MAIN[1][2][14]	MAIN[1][2][11]	CELL[0].GIOB[2]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[2].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[3]
Bits					Destination
MAIN[1][2][38]	MAIN[1][2][36]	MAIN[1][2][35]	MAIN[1][2][34]	MAIN[1][2][31]	CELL[0].GIOB[3]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[3].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[4]
Bits					Destination
MAIN[1][0][58]	MAIN[1][0][56]	MAIN[1][0][55]	MAIN[1][0][54]	MAIN[1][0][51]	CELL[0].GIOB[4]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[4].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[5]
Bits					Destination
MAIN[1][0][78]	MAIN[1][0][76]	MAIN[1][0][75]	MAIN[1][0][74]	MAIN[1][0][71]	CELL[0].GIOB[5]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[5].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[6]
Bits					Destination
MAIN[1][2][58]	MAIN[1][2][56]	MAIN[1][2][55]	MAIN[1][2][54]	MAIN[1][2][51]	CELL[0].GIOB[6]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[6].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[7]
Bits					Destination
MAIN[1][2][78]	MAIN[1][2][76]	MAIN[1][2][75]	MAIN[1][2][74]	MAIN[1][2][71]	CELL[0].GIOB[7]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[7].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[8]
Bits					Destination
MAIN[2][0][18]	MAIN[2][0][16]	MAIN[2][0][15]	MAIN[2][0][14]	MAIN[2][0][11]	CELL[0].GIOB[8]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[8].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[9]
Bits					Destination
MAIN[2][0][38]	MAIN[2][0][36]	MAIN[2][0][35]	MAIN[2][0][34]	MAIN[2][0][31]	CELL[0].GIOB[9]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[9].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[10]
Bits					Destination
MAIN[2][2][18]	MAIN[2][2][16]	MAIN[2][2][15]	MAIN[2][2][14]	MAIN[2][2][11]	CELL[0].GIOB[10]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[10].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[11]
Bits					Destination
MAIN[2][2][38]	MAIN[2][2][36]	MAIN[2][2][35]	MAIN[2][2][34]	MAIN[2][2][31]	CELL[0].GIOB[11]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[11].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[12]
Bits					Destination
MAIN[2][0][58]	MAIN[2][0][56]	MAIN[2][0][55]	MAIN[2][0][54]	MAIN[2][0][51]	CELL[0].GIOB[12]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[12].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[13]
Bits					Destination
MAIN[2][0][78]	MAIN[2][0][76]	MAIN[2][0][75]	MAIN[2][0][74]	MAIN[2][0][71]	CELL[0].GIOB[13]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[13].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[14]
Bits					Destination
MAIN[2][2][58]	MAIN[2][2][56]	MAIN[2][2][55]	MAIN[2][2][54]	MAIN[2][2][51]	CELL[0].GIOB[14]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[14].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes GIOB[15]
Bits					Destination
MAIN[2][2][78]	MAIN[2][2][76]	MAIN[2][2][75]	MAIN[2][2][74]	MAIN[2][2][71]	CELL[0].GIOB[15]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits															Destination
MAIN[11][0][19]	MAIN[11][0][18]	MAIN[11][0][17]	MAIN[11][0][16]	MAIN[11][0][4]	MAIN[11][2][15]	MAIN[11][2][13]	MAIN[11][0][13]	MAIN[11][0][14]	MAIN[11][0][0]	MAIN[11][0][10]	MAIN[11][0][7]	MAIN[11][0][6]	MAIN[11][0][5]	MAIN[11][0][2]	CELL[0].IMUX_BUFG_O[0]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits															Destination
MAIN[11][2][19]	MAIN[11][2][18]	MAIN[11][2][17]	MAIN[11][2][16]	MAIN[11][2][4]	MAIN[11][2][14]	MAIN[11][2][12]	MAIN[11][0][12]	MAIN[11][0][15]	MAIN[11][2][0]	MAIN[11][2][10]	MAIN[11][2][7]	MAIN[11][2][6]	MAIN[11][2][5]	MAIN[11][2][2]	CELL[0].IMUX_BUFG_O[1]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits															Destination
MAIN[11][0][39]	MAIN[11][0][38]	MAIN[11][0][37]	MAIN[11][0][36]	MAIN[11][0][24]	MAIN[11][2][35]	MAIN[11][2][33]	MAIN[11][0][33]	MAIN[11][0][34]	MAIN[11][0][20]	MAIN[11][0][30]	MAIN[11][0][27]	MAIN[11][0][26]	MAIN[11][0][25]	MAIN[11][0][22]	CELL[0].IMUX_BUFG_O[2]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits															Destination
MAIN[11][2][39]	MAIN[11][2][38]	MAIN[11][2][37]	MAIN[11][2][36]	MAIN[11][2][24]	MAIN[11][2][34]	MAIN[11][2][32]	MAIN[11][0][32]	MAIN[11][0][35]	MAIN[11][2][20]	MAIN[11][2][30]	MAIN[11][2][27]	MAIN[11][2][26]	MAIN[11][2][25]	MAIN[11][2][22]	CELL[0].IMUX_BUFG_O[3]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits															Destination
MAIN[11][0][59]	MAIN[11][0][58]	MAIN[11][0][57]	MAIN[11][0][56]	MAIN[11][0][44]	MAIN[11][2][55]	MAIN[11][2][53]	MAIN[11][0][53]	MAIN[11][0][54]	MAIN[11][0][40]	MAIN[11][0][50]	MAIN[11][0][47]	MAIN[11][0][46]	MAIN[11][0][45]	MAIN[11][0][42]	CELL[0].IMUX_BUFG_O[4]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits															Destination
MAIN[11][2][59]	MAIN[11][2][58]	MAIN[11][2][57]	MAIN[11][2][56]	MAIN[11][2][44]	MAIN[11][2][54]	MAIN[11][2][52]	MAIN[11][0][52]	MAIN[11][0][55]	MAIN[11][2][40]	MAIN[11][2][50]	MAIN[11][2][47]	MAIN[11][2][46]	MAIN[11][2][45]	MAIN[11][2][42]	CELL[0].IMUX_BUFG_O[5]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits															Destination
MAIN[11][0][79]	MAIN[11][0][78]	MAIN[11][0][77]	MAIN[11][0][76]	MAIN[11][0][64]	MAIN[11][2][75]	MAIN[11][2][73]	MAIN[11][0][73]	MAIN[11][0][74]	MAIN[11][0][60]	MAIN[11][0][70]	MAIN[11][0][67]	MAIN[11][0][66]	MAIN[11][0][65]	MAIN[11][0][62]	CELL[0].IMUX_BUFG_O[6]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits															Destination
MAIN[11][2][79]	MAIN[11][2][78]	MAIN[11][2][77]	MAIN[11][2][76]	MAIN[11][2][64]	MAIN[11][2][74]	MAIN[11][2][72]	MAIN[11][0][72]	MAIN[11][0][75]	MAIN[11][2][60]	MAIN[11][2][70]	MAIN[11][2][67]	MAIN[11][2][66]	MAIN[11][2][65]	MAIN[11][2][62]	CELL[0].IMUX_BUFG_O[7]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits															Destination
MAIN[12][0][19]	MAIN[12][0][18]	MAIN[12][0][17]	MAIN[12][0][16]	MAIN[12][0][4]	MAIN[12][2][15]	MAIN[12][2][13]	MAIN[12][0][13]	MAIN[12][0][14]	MAIN[12][0][0]	MAIN[12][0][10]	MAIN[12][0][7]	MAIN[12][0][6]	MAIN[12][0][5]	MAIN[12][0][2]	CELL[0].IMUX_BUFG_O[8]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits															Destination
MAIN[12][2][19]	MAIN[12][2][18]	MAIN[12][2][17]	MAIN[12][2][16]	MAIN[12][2][4]	MAIN[12][2][14]	MAIN[12][2][12]	MAIN[12][0][12]	MAIN[12][0][15]	MAIN[12][2][0]	MAIN[12][2][10]	MAIN[12][2][7]	MAIN[12][2][6]	MAIN[12][2][5]	MAIN[12][2][2]	CELL[0].IMUX_BUFG_O[9]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits															Destination
MAIN[12][0][39]	MAIN[12][0][38]	MAIN[12][0][37]	MAIN[12][0][36]	MAIN[12][0][24]	MAIN[12][2][35]	MAIN[12][2][33]	MAIN[12][0][33]	MAIN[12][0][34]	MAIN[12][0][20]	MAIN[12][0][30]	MAIN[12][0][27]	MAIN[12][0][26]	MAIN[12][0][25]	MAIN[12][0][22]	CELL[0].IMUX_BUFG_O[10]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits															Destination
MAIN[12][2][39]	MAIN[12][2][38]	MAIN[12][2][37]	MAIN[12][2][36]	MAIN[12][2][24]	MAIN[12][2][34]	MAIN[12][2][32]	MAIN[12][0][32]	MAIN[12][0][35]	MAIN[12][2][20]	MAIN[12][2][30]	MAIN[12][2][27]	MAIN[12][2][26]	MAIN[12][2][25]	MAIN[12][2][22]	CELL[0].IMUX_BUFG_O[11]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits															Destination
MAIN[12][0][59]	MAIN[12][0][58]	MAIN[12][0][57]	MAIN[12][0][56]	MAIN[12][0][44]	MAIN[12][2][55]	MAIN[12][2][53]	MAIN[12][0][53]	MAIN[12][0][54]	MAIN[12][0][40]	MAIN[12][0][50]	MAIN[12][0][47]	MAIN[12][0][46]	MAIN[12][0][45]	MAIN[12][0][42]	CELL[0].IMUX_BUFG_O[12]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits															Destination
MAIN[12][2][59]	MAIN[12][2][58]	MAIN[12][2][57]	MAIN[12][2][56]	MAIN[12][2][44]	MAIN[12][2][54]	MAIN[12][2][52]	MAIN[12][0][52]	MAIN[12][0][55]	MAIN[12][2][40]	MAIN[12][2][50]	MAIN[12][2][47]	MAIN[12][2][46]	MAIN[12][2][45]	MAIN[12][2][42]	CELL[0].IMUX_BUFG_O[13]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits															Destination
MAIN[12][0][79]	MAIN[12][0][78]	MAIN[12][0][77]	MAIN[12][0][76]	MAIN[12][0][64]	MAIN[12][2][75]	MAIN[12][2][73]	MAIN[12][0][73]	MAIN[12][0][74]	MAIN[12][0][60]	MAIN[12][0][70]	MAIN[12][0][67]	MAIN[12][0][66]	MAIN[12][0][65]	MAIN[12][0][62]	CELL[0].IMUX_BUFG_O[14]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits															Destination
MAIN[12][2][79]	MAIN[12][2][78]	MAIN[12][2][77]	MAIN[12][2][76]	MAIN[12][2][64]	MAIN[12][2][74]	MAIN[12][2][72]	MAIN[12][0][72]	MAIN[12][0][75]	MAIN[12][2][60]	MAIN[12][2][70]	MAIN[12][2][67]	MAIN[12][2][66]	MAIN[12][2][65]	MAIN[12][2][62]	CELL[0].IMUX_BUFG_O[15]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits															Destination
MAIN[13][0][19]	MAIN[13][0][18]	MAIN[13][0][17]	MAIN[13][0][16]	MAIN[13][0][4]	MAIN[13][2][15]	MAIN[13][2][13]	MAIN[13][0][13]	MAIN[13][0][14]	MAIN[13][0][0]	MAIN[13][0][10]	MAIN[13][0][7]	MAIN[13][0][6]	MAIN[13][0][5]	MAIN[13][0][2]	CELL[0].IMUX_BUFG_O[16]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits															Destination
MAIN[13][2][19]	MAIN[13][2][18]	MAIN[13][2][17]	MAIN[13][2][16]	MAIN[13][2][4]	MAIN[13][2][14]	MAIN[13][2][12]	MAIN[13][0][12]	MAIN[13][0][15]	MAIN[13][2][0]	MAIN[13][2][10]	MAIN[13][2][7]	MAIN[13][2][6]	MAIN[13][2][5]	MAIN[13][2][2]	CELL[0].IMUX_BUFG_O[17]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits															Destination
MAIN[13][0][39]	MAIN[13][0][38]	MAIN[13][0][37]	MAIN[13][0][36]	MAIN[13][0][24]	MAIN[13][2][35]	MAIN[13][2][33]	MAIN[13][0][33]	MAIN[13][0][34]	MAIN[13][0][20]	MAIN[13][0][30]	MAIN[13][0][27]	MAIN[13][0][26]	MAIN[13][0][25]	MAIN[13][0][22]	CELL[0].IMUX_BUFG_O[18]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits															Destination
MAIN[13][2][39]	MAIN[13][2][38]	MAIN[13][2][37]	MAIN[13][2][36]	MAIN[13][2][24]	MAIN[13][2][34]	MAIN[13][2][32]	MAIN[13][0][32]	MAIN[13][0][35]	MAIN[13][2][20]	MAIN[13][2][30]	MAIN[13][2][27]	MAIN[13][2][26]	MAIN[13][2][25]	MAIN[13][2][22]	CELL[0].IMUX_BUFG_O[19]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits															Destination
MAIN[13][0][59]	MAIN[13][0][58]	MAIN[13][0][57]	MAIN[13][0][56]	MAIN[13][0][44]	MAIN[13][2][55]	MAIN[13][2][53]	MAIN[13][0][53]	MAIN[13][0][54]	MAIN[13][0][40]	MAIN[13][0][50]	MAIN[13][0][47]	MAIN[13][0][46]	MAIN[13][0][45]	MAIN[13][0][42]	CELL[0].IMUX_BUFG_O[20]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits															Destination
MAIN[13][2][59]	MAIN[13][2][58]	MAIN[13][2][57]	MAIN[13][2][56]	MAIN[13][2][44]	MAIN[13][2][54]	MAIN[13][2][52]	MAIN[13][0][52]	MAIN[13][0][55]	MAIN[13][2][40]	MAIN[13][2][50]	MAIN[13][2][47]	MAIN[13][2][46]	MAIN[13][2][45]	MAIN[13][2][42]	CELL[0].IMUX_BUFG_O[21]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits															Destination
MAIN[13][0][79]	MAIN[13][0][78]	MAIN[13][0][77]	MAIN[13][0][76]	MAIN[13][0][64]	MAIN[13][2][75]	MAIN[13][2][73]	MAIN[13][0][73]	MAIN[13][0][74]	MAIN[13][0][60]	MAIN[13][0][70]	MAIN[13][0][67]	MAIN[13][0][66]	MAIN[13][0][65]	MAIN[13][0][62]	CELL[0].IMUX_BUFG_O[22]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits															Destination
MAIN[13][2][79]	MAIN[13][2][78]	MAIN[13][2][77]	MAIN[13][2][76]	MAIN[13][2][64]	MAIN[13][2][74]	MAIN[13][2][72]	MAIN[13][0][72]	MAIN[13][0][75]	MAIN[13][2][60]	MAIN[13][2][70]	MAIN[13][2][67]	MAIN[13][2][66]	MAIN[13][2][65]	MAIN[13][2][62]	CELL[0].IMUX_BUFG_O[23]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits															Destination
MAIN[14][0][19]	MAIN[14][0][18]	MAIN[14][0][17]	MAIN[14][0][16]	MAIN[14][0][4]	MAIN[14][2][15]	MAIN[14][2][13]	MAIN[14][0][13]	MAIN[14][0][14]	MAIN[14][0][0]	MAIN[14][0][10]	MAIN[14][0][7]	MAIN[14][0][6]	MAIN[14][0][5]	MAIN[14][0][2]	CELL[0].IMUX_BUFG_O[24]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits															Destination
MAIN[14][2][19]	MAIN[14][2][18]	MAIN[14][2][17]	MAIN[14][2][16]	MAIN[14][2][4]	MAIN[14][2][14]	MAIN[14][2][12]	MAIN[14][0][12]	MAIN[14][0][15]	MAIN[14][2][0]	MAIN[14][2][10]	MAIN[14][2][7]	MAIN[14][2][6]	MAIN[14][2][5]	MAIN[14][2][2]	CELL[0].IMUX_BUFG_O[25]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits															Destination
MAIN[14][0][39]	MAIN[14][0][38]	MAIN[14][0][37]	MAIN[14][0][36]	MAIN[14][0][24]	MAIN[14][2][35]	MAIN[14][2][33]	MAIN[14][0][33]	MAIN[14][0][34]	MAIN[14][0][20]	MAIN[14][0][30]	MAIN[14][0][27]	MAIN[14][0][26]	MAIN[14][0][25]	MAIN[14][0][22]	CELL[0].IMUX_BUFG_O[26]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits															Destination
MAIN[14][2][39]	MAIN[14][2][38]	MAIN[14][2][37]	MAIN[14][2][36]	MAIN[14][2][24]	MAIN[14][2][34]	MAIN[14][2][32]	MAIN[14][0][32]	MAIN[14][0][35]	MAIN[14][2][20]	MAIN[14][2][30]	MAIN[14][2][27]	MAIN[14][2][26]	MAIN[14][2][25]	MAIN[14][2][22]	CELL[0].IMUX_BUFG_O[27]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits															Destination
MAIN[14][0][59]	MAIN[14][0][58]	MAIN[14][0][57]	MAIN[14][0][56]	MAIN[14][0][44]	MAIN[14][2][55]	MAIN[14][2][53]	MAIN[14][0][53]	MAIN[14][0][54]	MAIN[14][0][40]	MAIN[14][0][50]	MAIN[14][0][47]	MAIN[14][0][46]	MAIN[14][0][45]	MAIN[14][0][42]	CELL[0].IMUX_BUFG_O[28]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits															Destination
MAIN[14][2][59]	MAIN[14][2][58]	MAIN[14][2][57]	MAIN[14][2][56]	MAIN[14][2][44]	MAIN[14][2][54]	MAIN[14][2][52]	MAIN[14][0][52]	MAIN[14][0][55]	MAIN[14][2][40]	MAIN[14][2][50]	MAIN[14][2][47]	MAIN[14][2][46]	MAIN[14][2][45]	MAIN[14][2][42]	CELL[0].IMUX_BUFG_O[29]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits															Destination
MAIN[14][0][79]	MAIN[14][0][78]	MAIN[14][0][77]	MAIN[14][0][76]	MAIN[14][0][64]	MAIN[14][2][75]	MAIN[14][2][73]	MAIN[14][0][73]	MAIN[14][0][74]	MAIN[14][0][60]	MAIN[14][0][70]	MAIN[14][0][67]	MAIN[14][0][66]	MAIN[14][0][65]	MAIN[14][0][62]	CELL[0].IMUX_BUFG_O[30]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits															Destination
MAIN[14][2][79]	MAIN[14][2][78]	MAIN[14][2][77]	MAIN[14][2][76]	MAIN[14][2][64]	MAIN[14][2][74]	MAIN[14][2][72]	MAIN[14][0][72]	MAIN[14][0][75]	MAIN[14][2][60]	MAIN[14][2][70]	MAIN[14][2][67]	MAIN[14][2][66]	MAIN[14][2][65]	MAIN[14][2][62]	CELL[0].IMUX_BUFG_O[31]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

Bitstream

virtex4 CLK_IOB_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	CLK_INT: mux CELL[0].GIOB[5] bit 4	-	CLK_INT: mux CELL[0].GIOB[7] bit 4
B77	-	-	-
B76	CLK_INT: mux CELL[0].GIOB[5] bit 3	-	CLK_INT: mux CELL[0].GIOB[7] bit 3
B75	CLK_INT: mux CELL[0].GIOB[5] bit 2	-	CLK_INT: mux CELL[0].GIOB[7] bit 2
B74	CLK_INT: mux CELL[0].GIOB[5] bit 1	-	CLK_INT: mux CELL[0].GIOB[7] bit 1
B73	-	-	-
B72	-	-	-
B71	CLK_INT: mux CELL[0].GIOB[5] bit 0	-	CLK_INT: mux CELL[0].GIOB[7] bit 0
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	CLK_INT: mux CELL[0].GIOB[4] bit 4	-	CLK_INT: mux CELL[0].GIOB[6] bit 4
B57	-	-	-
B56	CLK_INT: mux CELL[0].GIOB[4] bit 3	-	CLK_INT: mux CELL[0].GIOB[6] bit 3
B55	CLK_INT: mux CELL[0].GIOB[4] bit 2	-	CLK_INT: mux CELL[0].GIOB[6] bit 2
B54	CLK_INT: mux CELL[0].GIOB[4] bit 1	-	CLK_INT: mux CELL[0].GIOB[6] bit 1
B53	-	-	-
B52	-	-	-
B51	CLK_INT: mux CELL[0].GIOB[4] bit 0	-	CLK_INT: mux CELL[0].GIOB[6] bit 0
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	CLK_INT: mux CELL[0].GIOB[1] bit 4	-	CLK_INT: mux CELL[0].GIOB[3] bit 4
B37	-	-	-
B36	CLK_INT: mux CELL[0].GIOB[1] bit 3	-	CLK_INT: mux CELL[0].GIOB[3] bit 3
B35	CLK_INT: mux CELL[0].GIOB[1] bit 2	-	CLK_INT: mux CELL[0].GIOB[3] bit 2
B34	CLK_INT: mux CELL[0].GIOB[1] bit 1	-	CLK_INT: mux CELL[0].GIOB[3] bit 1
B33	-	-	-
B32	-	-	-
B31	CLK_INT: mux CELL[0].GIOB[1] bit 0	-	CLK_INT: mux CELL[0].GIOB[3] bit 0
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	CLK_INT: mux CELL[0].GIOB[0] bit 4	-	CLK_INT: mux CELL[0].GIOB[2] bit 4
B17	-	-	-
B16	CLK_INT: mux CELL[0].GIOB[0] bit 3	-	CLK_INT: mux CELL[0].GIOB[2] bit 3
B15	CLK_INT: mux CELL[0].GIOB[0] bit 2	-	CLK_INT: mux CELL[0].GIOB[2] bit 2
B14	CLK_INT: mux CELL[0].GIOB[0] bit 1	-	CLK_INT: mux CELL[0].GIOB[2] bit 1
B13	-	-	-
B12	-	-	-
B11	CLK_INT: mux CELL[0].GIOB[0] bit 0	-	CLK_INT: mux CELL[0].GIOB[2] bit 0
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	CLK_INT: mux CELL[0].GIOB[13] bit 4	-	CLK_INT: mux CELL[0].GIOB[15] bit 4
B77	-	-	-
B76	CLK_INT: mux CELL[0].GIOB[13] bit 3	-	CLK_INT: mux CELL[0].GIOB[15] bit 3
B75	CLK_INT: mux CELL[0].GIOB[13] bit 2	-	CLK_INT: mux CELL[0].GIOB[15] bit 2
B74	CLK_INT: mux CELL[0].GIOB[13] bit 1	-	CLK_INT: mux CELL[0].GIOB[15] bit 1
B73	-	-	-
B72	-	-	-
B71	CLK_INT: mux CELL[0].GIOB[13] bit 0	-	CLK_INT: mux CELL[0].GIOB[15] bit 0
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	CLK_INT: mux CELL[0].GIOB[12] bit 4	-	CLK_INT: mux CELL[0].GIOB[14] bit 4
B57	-	-	-
B56	CLK_INT: mux CELL[0].GIOB[12] bit 3	-	CLK_INT: mux CELL[0].GIOB[14] bit 3
B55	CLK_INT: mux CELL[0].GIOB[12] bit 2	-	CLK_INT: mux CELL[0].GIOB[14] bit 2
B54	CLK_INT: mux CELL[0].GIOB[12] bit 1	-	CLK_INT: mux CELL[0].GIOB[14] bit 1
B53	-	-	-
B52	-	-	-
B51	CLK_INT: mux CELL[0].GIOB[12] bit 0	-	CLK_INT: mux CELL[0].GIOB[14] bit 0
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	CLK_INT: mux CELL[0].GIOB[9] bit 4	-	CLK_INT: mux CELL[0].GIOB[11] bit 4
B37	-	-	-
B36	CLK_INT: mux CELL[0].GIOB[9] bit 3	-	CLK_INT: mux CELL[0].GIOB[11] bit 3
B35	CLK_INT: mux CELL[0].GIOB[9] bit 2	-	CLK_INT: mux CELL[0].GIOB[11] bit 2
B34	CLK_INT: mux CELL[0].GIOB[9] bit 1	-	CLK_INT: mux CELL[0].GIOB[11] bit 1
B33	-	-	-
B32	-	-	-
B31	CLK_INT: mux CELL[0].GIOB[9] bit 0	-	CLK_INT: mux CELL[0].GIOB[11] bit 0
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	CLK_INT: mux CELL[0].GIOB[8] bit 4	-	CLK_INT: mux CELL[0].GIOB[10] bit 4
B17	-	-	-
B16	CLK_INT: mux CELL[0].GIOB[8] bit 3	-	CLK_INT: mux CELL[0].GIOB[10] bit 3
B15	CLK_INT: mux CELL[0].GIOB[8] bit 2	-	CLK_INT: mux CELL[0].GIOB[10] bit 2
B14	CLK_INT: mux CELL[0].GIOB[8] bit 1	-	CLK_INT: mux CELL[0].GIOB[10] bit 1
B13	-	-	-
B12	-	-	-
B11	CLK_INT: mux CELL[0].GIOB[8] bit 0	-	CLK_INT: mux CELL[0].GIOB[10] bit 0
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_S rect MAIN[11]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 14
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B71	-	-	-
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B69	-	-	-
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B63	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 14
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B51	-	-	-
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B49	-	-	-
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B43	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 14
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B31	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B29	-	-	-
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B23	-	-	-
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 14
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B11	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B9	-	-	-
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B3	-	-	-
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5

virtex4 CLK_IOB_S rect MAIN[12]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 14
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B71	-	-	-
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B69	-	-	-
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B63	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 14
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B51	-	-	-
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B49	-	-	-
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B43	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 14
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B31	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B29	-	-	-
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B23	-	-	-
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 14
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B11	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B9	-	-	-
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B3	-	-	-
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5

virtex4 CLK_IOB_S rect MAIN[13]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 14
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B71	-	-	-
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B69	-	-	-
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B63	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 14
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B51	-	-	-
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B49	-	-	-
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B43	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 14
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B31	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B29	-	-	-
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B23	-	-	-
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 14
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B11	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B9	-	-	-
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B3	-	-	-
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5

virtex4 CLK_IOB_S rect MAIN[14]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 14
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B71	-	-	-
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B69	-	-	-
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B63	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 14
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B51	-	-	-
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B49	-	-	-
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B43	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 14
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B31	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B29	-	-	-
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B23	-	-	-
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 14
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B11	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B9	-	-	-
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B3	-	-	-
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5

virtex4 CLK_IOB_S rect MAIN[15]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

Tile CLK_IOB_N

Cells: 16

Switchbox CLK_INT

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[0]
Bits					Destination
MAIN[14][0][68]	MAIN[14][0][65]	MAIN[14][0][64]	MAIN[14][0][63]	MAIN[14][0][61]	CELL[0].GIOB[0]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[0].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[1]
Bits					Destination
MAIN[14][0][48]	MAIN[14][0][45]	MAIN[14][0][44]	MAIN[14][0][43]	MAIN[14][0][41]	CELL[0].GIOB[1]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[1].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[2]
Bits					Destination
MAIN[14][2][68]	MAIN[14][2][65]	MAIN[14][2][64]	MAIN[14][2][63]	MAIN[14][2][61]	CELL[0].GIOB[2]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[2].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[3]
Bits					Destination
MAIN[14][2][48]	MAIN[14][2][45]	MAIN[14][2][44]	MAIN[14][2][43]	MAIN[14][2][41]	CELL[0].GIOB[3]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[3].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[4]
Bits					Destination
MAIN[14][0][28]	MAIN[14][0][25]	MAIN[14][0][24]	MAIN[14][0][23]	MAIN[14][0][21]	CELL[0].GIOB[4]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[4].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[5]
Bits					Destination
MAIN[14][0][8]	MAIN[14][0][5]	MAIN[14][0][4]	MAIN[14][0][3]	MAIN[14][0][1]	CELL[0].GIOB[5]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[5].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[6]
Bits					Destination
MAIN[14][2][28]	MAIN[14][2][25]	MAIN[14][2][24]	MAIN[14][2][23]	MAIN[14][2][21]	CELL[0].GIOB[6]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[6].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[7]
Bits					Destination
MAIN[14][2][8]	MAIN[14][2][5]	MAIN[14][2][4]	MAIN[14][2][3]	MAIN[14][2][1]	CELL[0].GIOB[7]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[7].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[8]
Bits					Destination
MAIN[13][0][68]	MAIN[13][0][65]	MAIN[13][0][64]	MAIN[13][0][63]	MAIN[13][0][61]	CELL[0].GIOB[8]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[8].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[9]
Bits					Destination
MAIN[13][0][48]	MAIN[13][0][45]	MAIN[13][0][44]	MAIN[13][0][43]	MAIN[13][0][41]	CELL[0].GIOB[9]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[9].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[10]
Bits					Destination
MAIN[13][2][68]	MAIN[13][2][65]	MAIN[13][2][64]	MAIN[13][2][63]	MAIN[13][2][61]	CELL[0].GIOB[10]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[10].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[11]
Bits					Destination
MAIN[13][2][48]	MAIN[13][2][45]	MAIN[13][2][44]	MAIN[13][2][43]	MAIN[13][2][41]	CELL[0].GIOB[11]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[11].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[12]
Bits					Destination
MAIN[13][0][28]	MAIN[13][0][25]	MAIN[13][0][24]	MAIN[13][0][23]	MAIN[13][0][21]	CELL[0].GIOB[12]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[12].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[13]
Bits					Destination
MAIN[13][0][8]	MAIN[13][0][5]	MAIN[13][0][4]	MAIN[13][0][3]	MAIN[13][0][1]	CELL[0].GIOB[13]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[13].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[14]
Bits					Destination
MAIN[13][2][28]	MAIN[13][2][25]	MAIN[13][2][24]	MAIN[13][2][23]	MAIN[13][2][21]	CELL[0].GIOB[14]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[14].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes GIOB[15]
Bits					Destination
MAIN[13][2][8]	MAIN[13][2][5]	MAIN[13][2][4]	MAIN[13][2][3]	MAIN[13][2][1]	CELL[0].GIOB[15]
					Source
0	0	0	0	0	off
1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits															Destination
MAIN[4][0][60]	MAIN[4][0][61]	MAIN[4][0][62]	MAIN[4][0][63]	MAIN[4][0][79]	MAIN[4][2][64]	MAIN[4][2][66]	MAIN[4][0][66]	MAIN[4][0][65]	MAIN[4][0][75]	MAIN[4][0][77]	MAIN[4][0][74]	MAIN[4][0][73]	MAIN[4][0][72]	MAIN[4][0][69]	CELL[0].IMUX_BUFG_O[0]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits															Destination
MAIN[4][2][60]	MAIN[4][2][61]	MAIN[4][2][62]	MAIN[4][2][63]	MAIN[4][2][79]	MAIN[4][2][65]	MAIN[4][2][67]	MAIN[4][0][67]	MAIN[4][0][64]	MAIN[4][2][75]	MAIN[4][2][77]	MAIN[4][2][74]	MAIN[4][2][73]	MAIN[4][2][72]	MAIN[4][2][69]	CELL[0].IMUX_BUFG_O[1]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits															Destination
MAIN[4][0][40]	MAIN[4][0][41]	MAIN[4][0][42]	MAIN[4][0][43]	MAIN[4][0][59]	MAIN[4][2][44]	MAIN[4][2][46]	MAIN[4][0][46]	MAIN[4][0][45]	MAIN[4][0][55]	MAIN[4][0][57]	MAIN[4][0][54]	MAIN[4][0][53]	MAIN[4][0][52]	MAIN[4][0][49]	CELL[0].IMUX_BUFG_O[2]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits															Destination
MAIN[4][2][40]	MAIN[4][2][41]	MAIN[4][2][42]	MAIN[4][2][43]	MAIN[4][2][59]	MAIN[4][2][45]	MAIN[4][2][47]	MAIN[4][0][47]	MAIN[4][0][44]	MAIN[4][2][55]	MAIN[4][2][57]	MAIN[4][2][54]	MAIN[4][2][53]	MAIN[4][2][52]	MAIN[4][2][49]	CELL[0].IMUX_BUFG_O[3]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits															Destination
MAIN[4][0][20]	MAIN[4][0][21]	MAIN[4][0][22]	MAIN[4][0][23]	MAIN[4][0][39]	MAIN[4][2][24]	MAIN[4][2][26]	MAIN[4][0][26]	MAIN[4][0][25]	MAIN[4][0][35]	MAIN[4][0][37]	MAIN[4][0][34]	MAIN[4][0][33]	MAIN[4][0][32]	MAIN[4][0][29]	CELL[0].IMUX_BUFG_O[4]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits															Destination
MAIN[4][2][20]	MAIN[4][2][21]	MAIN[4][2][22]	MAIN[4][2][23]	MAIN[4][2][39]	MAIN[4][2][25]	MAIN[4][2][27]	MAIN[4][0][27]	MAIN[4][0][24]	MAIN[4][2][35]	MAIN[4][2][37]	MAIN[4][2][34]	MAIN[4][2][33]	MAIN[4][2][32]	MAIN[4][2][29]	CELL[0].IMUX_BUFG_O[5]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits															Destination
MAIN[4][0][0]	MAIN[4][0][1]	MAIN[4][0][2]	MAIN[4][0][3]	MAIN[4][0][19]	MAIN[4][2][4]	MAIN[4][2][6]	MAIN[4][0][6]	MAIN[4][0][5]	MAIN[4][0][15]	MAIN[4][0][17]	MAIN[4][0][14]	MAIN[4][0][13]	MAIN[4][0][12]	MAIN[4][0][9]	CELL[0].IMUX_BUFG_O[6]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits															Destination
MAIN[4][2][0]	MAIN[4][2][1]	MAIN[4][2][2]	MAIN[4][2][3]	MAIN[4][2][19]	MAIN[4][2][5]	MAIN[4][2][7]	MAIN[4][0][7]	MAIN[4][0][4]	MAIN[4][2][15]	MAIN[4][2][17]	MAIN[4][2][14]	MAIN[4][2][13]	MAIN[4][2][12]	MAIN[4][2][9]	CELL[0].IMUX_BUFG_O[7]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits															Destination
MAIN[3][0][60]	MAIN[3][0][61]	MAIN[3][0][62]	MAIN[3][0][63]	MAIN[3][0][79]	MAIN[3][2][64]	MAIN[3][2][66]	MAIN[3][0][66]	MAIN[3][0][65]	MAIN[3][0][75]	MAIN[3][0][77]	MAIN[3][0][74]	MAIN[3][0][73]	MAIN[3][0][72]	MAIN[3][0][69]	CELL[0].IMUX_BUFG_O[8]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits															Destination
MAIN[3][2][60]	MAIN[3][2][61]	MAIN[3][2][62]	MAIN[3][2][63]	MAIN[3][2][79]	MAIN[3][2][65]	MAIN[3][2][67]	MAIN[3][0][67]	MAIN[3][0][64]	MAIN[3][2][75]	MAIN[3][2][77]	MAIN[3][2][74]	MAIN[3][2][73]	MAIN[3][2][72]	MAIN[3][2][69]	CELL[0].IMUX_BUFG_O[9]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits															Destination
MAIN[3][0][40]	MAIN[3][0][41]	MAIN[3][0][42]	MAIN[3][0][43]	MAIN[3][0][59]	MAIN[3][2][44]	MAIN[3][2][46]	MAIN[3][0][46]	MAIN[3][0][45]	MAIN[3][0][55]	MAIN[3][0][57]	MAIN[3][0][54]	MAIN[3][0][53]	MAIN[3][0][52]	MAIN[3][0][49]	CELL[0].IMUX_BUFG_O[10]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits															Destination
MAIN[3][2][40]	MAIN[3][2][41]	MAIN[3][2][42]	MAIN[3][2][43]	MAIN[3][2][59]	MAIN[3][2][45]	MAIN[3][2][47]	MAIN[3][0][47]	MAIN[3][0][44]	MAIN[3][2][55]	MAIN[3][2][57]	MAIN[3][2][54]	MAIN[3][2][53]	MAIN[3][2][52]	MAIN[3][2][49]	CELL[0].IMUX_BUFG_O[11]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits															Destination
MAIN[3][0][20]	MAIN[3][0][21]	MAIN[3][0][22]	MAIN[3][0][23]	MAIN[3][0][39]	MAIN[3][2][24]	MAIN[3][2][26]	MAIN[3][0][26]	MAIN[3][0][25]	MAIN[3][0][35]	MAIN[3][0][37]	MAIN[3][0][34]	MAIN[3][0][33]	MAIN[3][0][32]	MAIN[3][0][29]	CELL[0].IMUX_BUFG_O[12]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits															Destination
MAIN[3][2][20]	MAIN[3][2][21]	MAIN[3][2][22]	MAIN[3][2][23]	MAIN[3][2][39]	MAIN[3][2][25]	MAIN[3][2][27]	MAIN[3][0][27]	MAIN[3][0][24]	MAIN[3][2][35]	MAIN[3][2][37]	MAIN[3][2][34]	MAIN[3][2][33]	MAIN[3][2][32]	MAIN[3][2][29]	CELL[0].IMUX_BUFG_O[13]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits															Destination
MAIN[3][0][0]	MAIN[3][0][1]	MAIN[3][0][2]	MAIN[3][0][3]	MAIN[3][0][19]	MAIN[3][2][4]	MAIN[3][2][6]	MAIN[3][0][6]	MAIN[3][0][5]	MAIN[3][0][15]	MAIN[3][0][17]	MAIN[3][0][14]	MAIN[3][0][13]	MAIN[3][0][12]	MAIN[3][0][9]	CELL[0].IMUX_BUFG_O[14]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits															Destination
MAIN[3][2][0]	MAIN[3][2][1]	MAIN[3][2][2]	MAIN[3][2][3]	MAIN[3][2][19]	MAIN[3][2][5]	MAIN[3][2][7]	MAIN[3][0][7]	MAIN[3][0][4]	MAIN[3][2][15]	MAIN[3][2][17]	MAIN[3][2][14]	MAIN[3][2][13]	MAIN[3][2][12]	MAIN[3][2][9]	CELL[0].IMUX_BUFG_O[15]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits															Destination
MAIN[2][0][60]	MAIN[2][0][61]	MAIN[2][0][62]	MAIN[2][0][63]	MAIN[2][0][79]	MAIN[2][2][64]	MAIN[2][2][66]	MAIN[2][0][66]	MAIN[2][0][65]	MAIN[2][0][75]	MAIN[2][0][77]	MAIN[2][0][74]	MAIN[2][0][73]	MAIN[2][0][72]	MAIN[2][0][69]	CELL[0].IMUX_BUFG_O[16]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits															Destination
MAIN[2][2][60]	MAIN[2][2][61]	MAIN[2][2][62]	MAIN[2][2][63]	MAIN[2][2][79]	MAIN[2][2][65]	MAIN[2][2][67]	MAIN[2][0][67]	MAIN[2][0][64]	MAIN[2][2][75]	MAIN[2][2][77]	MAIN[2][2][74]	MAIN[2][2][73]	MAIN[2][2][72]	MAIN[2][2][69]	CELL[0].IMUX_BUFG_O[17]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits															Destination
MAIN[2][0][40]	MAIN[2][0][41]	MAIN[2][0][42]	MAIN[2][0][43]	MAIN[2][0][59]	MAIN[2][2][44]	MAIN[2][2][46]	MAIN[2][0][46]	MAIN[2][0][45]	MAIN[2][0][55]	MAIN[2][0][57]	MAIN[2][0][54]	MAIN[2][0][53]	MAIN[2][0][52]	MAIN[2][0][49]	CELL[0].IMUX_BUFG_O[18]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits															Destination
MAIN[2][2][40]	MAIN[2][2][41]	MAIN[2][2][42]	MAIN[2][2][43]	MAIN[2][2][59]	MAIN[2][2][45]	MAIN[2][2][47]	MAIN[2][0][47]	MAIN[2][0][44]	MAIN[2][2][55]	MAIN[2][2][57]	MAIN[2][2][54]	MAIN[2][2][53]	MAIN[2][2][52]	MAIN[2][2][49]	CELL[0].IMUX_BUFG_O[19]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits															Destination
MAIN[2][0][20]	MAIN[2][0][21]	MAIN[2][0][22]	MAIN[2][0][23]	MAIN[2][0][39]	MAIN[2][2][24]	MAIN[2][2][26]	MAIN[2][0][26]	MAIN[2][0][25]	MAIN[2][0][35]	MAIN[2][0][37]	MAIN[2][0][34]	MAIN[2][0][33]	MAIN[2][0][32]	MAIN[2][0][29]	CELL[0].IMUX_BUFG_O[20]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits															Destination
MAIN[2][2][20]	MAIN[2][2][21]	MAIN[2][2][22]	MAIN[2][2][23]	MAIN[2][2][39]	MAIN[2][2][25]	MAIN[2][2][27]	MAIN[2][0][27]	MAIN[2][0][24]	MAIN[2][2][35]	MAIN[2][2][37]	MAIN[2][2][34]	MAIN[2][2][33]	MAIN[2][2][32]	MAIN[2][2][29]	CELL[0].IMUX_BUFG_O[21]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits															Destination
MAIN[2][0][0]	MAIN[2][0][1]	MAIN[2][0][2]	MAIN[2][0][3]	MAIN[2][0][19]	MAIN[2][2][4]	MAIN[2][2][6]	MAIN[2][0][6]	MAIN[2][0][5]	MAIN[2][0][15]	MAIN[2][0][17]	MAIN[2][0][14]	MAIN[2][0][13]	MAIN[2][0][12]	MAIN[2][0][9]	CELL[0].IMUX_BUFG_O[22]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits															Destination
MAIN[2][2][0]	MAIN[2][2][1]	MAIN[2][2][2]	MAIN[2][2][3]	MAIN[2][2][19]	MAIN[2][2][5]	MAIN[2][2][7]	MAIN[2][0][7]	MAIN[2][0][4]	MAIN[2][2][15]	MAIN[2][2][17]	MAIN[2][2][14]	MAIN[2][2][13]	MAIN[2][2][12]	MAIN[2][2][9]	CELL[0].IMUX_BUFG_O[23]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits															Destination
MAIN[1][0][60]	MAIN[1][0][61]	MAIN[1][0][62]	MAIN[1][0][63]	MAIN[1][0][79]	MAIN[1][2][64]	MAIN[1][2][66]	MAIN[1][0][66]	MAIN[1][0][65]	MAIN[1][0][75]	MAIN[1][0][77]	MAIN[1][0][74]	MAIN[1][0][73]	MAIN[1][0][72]	MAIN[1][0][69]	CELL[0].IMUX_BUFG_O[24]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits															Destination
MAIN[1][2][60]	MAIN[1][2][61]	MAIN[1][2][62]	MAIN[1][2][63]	MAIN[1][2][79]	MAIN[1][2][65]	MAIN[1][2][67]	MAIN[1][0][67]	MAIN[1][0][64]	MAIN[1][2][75]	MAIN[1][2][77]	MAIN[1][2][74]	MAIN[1][2][73]	MAIN[1][2][72]	MAIN[1][2][69]	CELL[0].IMUX_BUFG_O[25]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits															Destination
MAIN[1][0][40]	MAIN[1][0][41]	MAIN[1][0][42]	MAIN[1][0][43]	MAIN[1][0][59]	MAIN[1][2][44]	MAIN[1][2][46]	MAIN[1][0][46]	MAIN[1][0][45]	MAIN[1][0][55]	MAIN[1][0][57]	MAIN[1][0][54]	MAIN[1][0][53]	MAIN[1][0][52]	MAIN[1][0][49]	CELL[0].IMUX_BUFG_O[26]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits															Destination
MAIN[1][2][40]	MAIN[1][2][41]	MAIN[1][2][42]	MAIN[1][2][43]	MAIN[1][2][59]	MAIN[1][2][45]	MAIN[1][2][47]	MAIN[1][0][47]	MAIN[1][0][44]	MAIN[1][2][55]	MAIN[1][2][57]	MAIN[1][2][54]	MAIN[1][2][53]	MAIN[1][2][52]	MAIN[1][2][49]	CELL[0].IMUX_BUFG_O[27]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits															Destination
MAIN[1][0][20]	MAIN[1][0][21]	MAIN[1][0][22]	MAIN[1][0][23]	MAIN[1][0][39]	MAIN[1][2][24]	MAIN[1][2][26]	MAIN[1][0][26]	MAIN[1][0][25]	MAIN[1][0][35]	MAIN[1][0][37]	MAIN[1][0][34]	MAIN[1][0][33]	MAIN[1][0][32]	MAIN[1][0][29]	CELL[0].IMUX_BUFG_O[28]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits															Destination
MAIN[1][2][20]	MAIN[1][2][21]	MAIN[1][2][22]	MAIN[1][2][23]	MAIN[1][2][39]	MAIN[1][2][25]	MAIN[1][2][27]	MAIN[1][0][27]	MAIN[1][0][24]	MAIN[1][2][35]	MAIN[1][2][37]	MAIN[1][2][34]	MAIN[1][2][33]	MAIN[1][2][32]	MAIN[1][2][29]	CELL[0].IMUX_BUFG_O[29]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits															Destination
MAIN[1][0][0]	MAIN[1][0][1]	MAIN[1][0][2]	MAIN[1][0][3]	MAIN[1][0][19]	MAIN[1][2][4]	MAIN[1][2][6]	MAIN[1][0][6]	MAIN[1][0][5]	MAIN[1][0][15]	MAIN[1][0][17]	MAIN[1][0][14]	MAIN[1][0][13]	MAIN[1][0][12]	MAIN[1][0][9]	CELL[0].IMUX_BUFG_O[30]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

virtex4 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits															Destination
MAIN[1][2][0]	MAIN[1][2][1]	MAIN[1][2][2]	MAIN[1][2][3]	MAIN[1][2][19]	MAIN[1][2][5]	MAIN[1][2][7]	MAIN[1][0][7]	MAIN[1][0][4]	MAIN[1][2][15]	MAIN[1][2][17]	MAIN[1][2][14]	MAIN[1][2][13]	MAIN[1][2][12]	MAIN[1][2][9]	CELL[0].IMUX_BUFG_O[31]
															Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_CLKPAD
0	0	0	1	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	1	0	0	0	1	1	1	1	1	CELL[8].OUT_CLKPAD
0	0	0	1	0	1	0	0	0	0	1	1	1	1	1	CELL[12].OUT_CLKPAD
0	0	1	0	0	0	0	0	1	0	1	1	1	1	1	CELL[1].OUT_CLKPAD
0	0	1	0	0	0	0	1	0	0	1	1	1	1	1	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	1	1	1	1	1	CELL[9].OUT_CLKPAD
0	0	1	0	0	1	0	0	0	0	1	1	1	1	1	CELL[13].OUT_CLKPAD
0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[2].OUT_CLKPAD
0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[6].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[10].OUT_CLKPAD
0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[14].OUT_CLKPAD
1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[3].OUT_CLKPAD
1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[7].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[11].OUT_CLKPAD
1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[15].OUT_CLKPAD

Bitstream

virtex4 CLK_IOB_N rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B78	-	-	-
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B76	-	-	-
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B71	-	-	-
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 14
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B58	-	-	-
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B56	-	-	-
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B51	-	-	-
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 14
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B38	-	-	-
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B36	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B31	-	-	-
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 14
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B18	-	-	-
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B16	-	-	-
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B11	-	-	-
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 14

virtex4 CLK_IOB_N rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B78	-	-	-
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B76	-	-	-
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B71	-	-	-
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 14
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B58	-	-	-
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B56	-	-	-
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B51	-	-	-
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 14
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B38	-	-	-
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B36	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B31	-	-	-
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 14
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B18	-	-	-
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B16	-	-	-
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B11	-	-	-
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 14

virtex4 CLK_IOB_N rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B78	-	-	-
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B76	-	-	-
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B71	-	-	-
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 14
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B58	-	-	-
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B56	-	-	-
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B51	-	-	-
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 14
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B38	-	-	-
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B36	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B31	-	-	-
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 14
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B18	-	-	-
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B16	-	-	-
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B11	-	-	-
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 14

virtex4 CLK_IOB_N rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B78	-	-	-
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B76	-	-	-
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B71	-	-	-
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0
B68	-	-	-
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 14
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B58	-	-	-
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B56	-	-	-
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B51	-	-	-
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B48	-	-	-
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 14
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B38	-	-	-
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B36	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B31	-	-	-
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B28	-	-	-
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 14
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B18	-	-	-
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B16	-	-	-
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B11	-	-	-
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B8	-	-	-
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 14

virtex4 CLK_IOB_N rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[11]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[12]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[13]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	CLK_INT: mux CELL[0].GIOB[8] bit 4	-	CLK_INT: mux CELL[0].GIOB[10] bit 4
B67	-	-	-
B66	-	-	-
B65	CLK_INT: mux CELL[0].GIOB[8] bit 3	-	CLK_INT: mux CELL[0].GIOB[10] bit 3
B64	CLK_INT: mux CELL[0].GIOB[8] bit 2	-	CLK_INT: mux CELL[0].GIOB[10] bit 2
B63	CLK_INT: mux CELL[0].GIOB[8] bit 1	-	CLK_INT: mux CELL[0].GIOB[10] bit 1
B62	-	-	-
B61	CLK_INT: mux CELL[0].GIOB[8] bit 0	-	CLK_INT: mux CELL[0].GIOB[10] bit 0
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	CLK_INT: mux CELL[0].GIOB[9] bit 4	-	CLK_INT: mux CELL[0].GIOB[11] bit 4
B47	-	-	-
B46	-	-	-
B45	CLK_INT: mux CELL[0].GIOB[9] bit 3	-	CLK_INT: mux CELL[0].GIOB[11] bit 3
B44	CLK_INT: mux CELL[0].GIOB[9] bit 2	-	CLK_INT: mux CELL[0].GIOB[11] bit 2
B43	CLK_INT: mux CELL[0].GIOB[9] bit 1	-	CLK_INT: mux CELL[0].GIOB[11] bit 1
B42	-	-	-
B41	CLK_INT: mux CELL[0].GIOB[9] bit 0	-	CLK_INT: mux CELL[0].GIOB[11] bit 0
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	CLK_INT: mux CELL[0].GIOB[12] bit 4	-	CLK_INT: mux CELL[0].GIOB[14] bit 4
B27	-	-	-
B26	-	-	-
B25	CLK_INT: mux CELL[0].GIOB[12] bit 3	-	CLK_INT: mux CELL[0].GIOB[14] bit 3
B24	CLK_INT: mux CELL[0].GIOB[12] bit 2	-	CLK_INT: mux CELL[0].GIOB[14] bit 2
B23	CLK_INT: mux CELL[0].GIOB[12] bit 1	-	CLK_INT: mux CELL[0].GIOB[14] bit 1
B22	-	-	-
B21	CLK_INT: mux CELL[0].GIOB[12] bit 0	-	CLK_INT: mux CELL[0].GIOB[14] bit 0
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	CLK_INT: mux CELL[0].GIOB[13] bit 4	-	CLK_INT: mux CELL[0].GIOB[15] bit 4
B7	-	-	-
B6	-	-	-
B5	CLK_INT: mux CELL[0].GIOB[13] bit 3	-	CLK_INT: mux CELL[0].GIOB[15] bit 3
B4	CLK_INT: mux CELL[0].GIOB[13] bit 2	-	CLK_INT: mux CELL[0].GIOB[15] bit 2
B3	CLK_INT: mux CELL[0].GIOB[13] bit 1	-	CLK_INT: mux CELL[0].GIOB[15] bit 1
B2	-	-	-
B1	CLK_INT: mux CELL[0].GIOB[13] bit 0	-	CLK_INT: mux CELL[0].GIOB[15] bit 0
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[14]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	CLK_INT: mux CELL[0].GIOB[0] bit 4	-	CLK_INT: mux CELL[0].GIOB[2] bit 4
B67	-	-	-
B66	-	-	-
B65	CLK_INT: mux CELL[0].GIOB[0] bit 3	-	CLK_INT: mux CELL[0].GIOB[2] bit 3
B64	CLK_INT: mux CELL[0].GIOB[0] bit 2	-	CLK_INT: mux CELL[0].GIOB[2] bit 2
B63	CLK_INT: mux CELL[0].GIOB[0] bit 1	-	CLK_INT: mux CELL[0].GIOB[2] bit 1
B62	-	-	-
B61	CLK_INT: mux CELL[0].GIOB[0] bit 0	-	CLK_INT: mux CELL[0].GIOB[2] bit 0
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	CLK_INT: mux CELL[0].GIOB[1] bit 4	-	CLK_INT: mux CELL[0].GIOB[3] bit 4
B47	-	-	-
B46	-	-	-
B45	CLK_INT: mux CELL[0].GIOB[1] bit 3	-	CLK_INT: mux CELL[0].GIOB[3] bit 3
B44	CLK_INT: mux CELL[0].GIOB[1] bit 2	-	CLK_INT: mux CELL[0].GIOB[3] bit 2
B43	CLK_INT: mux CELL[0].GIOB[1] bit 1	-	CLK_INT: mux CELL[0].GIOB[3] bit 1
B42	-	-	-
B41	CLK_INT: mux CELL[0].GIOB[1] bit 0	-	CLK_INT: mux CELL[0].GIOB[3] bit 0
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	CLK_INT: mux CELL[0].GIOB[4] bit 4	-	CLK_INT: mux CELL[0].GIOB[6] bit 4
B27	-	-	-
B26	-	-	-
B25	CLK_INT: mux CELL[0].GIOB[4] bit 3	-	CLK_INT: mux CELL[0].GIOB[6] bit 3
B24	CLK_INT: mux CELL[0].GIOB[4] bit 2	-	CLK_INT: mux CELL[0].GIOB[6] bit 2
B23	CLK_INT: mux CELL[0].GIOB[4] bit 1	-	CLK_INT: mux CELL[0].GIOB[6] bit 1
B22	-	-	-
B21	CLK_INT: mux CELL[0].GIOB[4] bit 0	-	CLK_INT: mux CELL[0].GIOB[6] bit 0
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	CLK_INT: mux CELL[0].GIOB[5] bit 4	-	CLK_INT: mux CELL[0].GIOB[7] bit 4
B7	-	-	-
B6	-	-	-
B5	CLK_INT: mux CELL[0].GIOB[5] bit 3	-	CLK_INT: mux CELL[0].GIOB[7] bit 3
B4	CLK_INT: mux CELL[0].GIOB[5] bit 2	-	CLK_INT: mux CELL[0].GIOB[7] bit 2
B3	CLK_INT: mux CELL[0].GIOB[5] bit 1	-	CLK_INT: mux CELL[0].GIOB[7] bit 1
B2	-	-	-
B1	CLK_INT: mux CELL[0].GIOB[5] bit 0	-	CLK_INT: mux CELL[0].GIOB[7] bit 0
B0	-	-	-

virtex4 CLK_IOB_N rect MAIN[15]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

Tile CLK_DCM_S

Cells: 8

Switchbox CLK_INT

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits																	Destination
MAIN[2][0][10]	MAIN[2][0][11]	MAIN[2][0][12]	MAIN[2][0][13]	MAIN[2][0][6]	MAIN[2][0][19]	MAIN[2][0][18]	MAIN[2][0][17]	MAIN[2][0][16]	MAIN[2][0][15]	MAIN[2][0][14]	MAIN[2][0][7]	MAIN[2][0][8]	MAIN[2][0][5]	MAIN[2][0][4]	MAIN[2][0][3]	MAIN[2][0][0]	CELL[0].IMUX_BUFG_O[0]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits																	Destination
MAIN[2][2][10]	MAIN[2][2][11]	MAIN[2][2][12]	MAIN[2][2][13]	MAIN[2][2][6]	MAIN[2][2][19]	MAIN[2][2][18]	MAIN[2][2][17]	MAIN[2][2][16]	MAIN[2][2][15]	MAIN[2][2][14]	MAIN[2][2][7]	MAIN[2][2][8]	MAIN[2][2][5]	MAIN[2][2][4]	MAIN[2][2][3]	MAIN[2][2][0]	CELL[0].IMUX_BUFG_O[1]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits																	Destination
MAIN[2][0][30]	MAIN[2][0][31]	MAIN[2][0][32]	MAIN[2][0][33]	MAIN[2][0][26]	MAIN[2][0][39]	MAIN[2][0][38]	MAIN[2][0][37]	MAIN[2][0][36]	MAIN[2][0][35]	MAIN[2][0][34]	MAIN[2][0][27]	MAIN[2][0][28]	MAIN[2][0][25]	MAIN[2][0][24]	MAIN[2][0][23]	MAIN[2][0][20]	CELL[0].IMUX_BUFG_O[2]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits																	Destination
MAIN[2][2][30]	MAIN[2][2][31]	MAIN[2][2][32]	MAIN[2][2][33]	MAIN[2][2][26]	MAIN[2][2][39]	MAIN[2][2][38]	MAIN[2][2][37]	MAIN[2][2][36]	MAIN[2][2][35]	MAIN[2][2][34]	MAIN[2][2][27]	MAIN[2][2][28]	MAIN[2][2][25]	MAIN[2][2][24]	MAIN[2][2][23]	MAIN[2][2][20]	CELL[0].IMUX_BUFG_O[3]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits																	Destination
MAIN[2][0][50]	MAIN[2][0][51]	MAIN[2][0][52]	MAIN[2][0][53]	MAIN[2][0][46]	MAIN[2][0][59]	MAIN[2][0][58]	MAIN[2][0][57]	MAIN[2][0][56]	MAIN[2][0][55]	MAIN[2][0][54]	MAIN[2][0][47]	MAIN[2][0][48]	MAIN[2][0][45]	MAIN[2][0][44]	MAIN[2][0][43]	MAIN[2][0][40]	CELL[0].IMUX_BUFG_O[4]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits																	Destination
MAIN[2][2][50]	MAIN[2][2][51]	MAIN[2][2][52]	MAIN[2][2][53]	MAIN[2][2][46]	MAIN[2][2][59]	MAIN[2][2][58]	MAIN[2][2][57]	MAIN[2][2][56]	MAIN[2][2][55]	MAIN[2][2][54]	MAIN[2][2][47]	MAIN[2][2][48]	MAIN[2][2][45]	MAIN[2][2][44]	MAIN[2][2][43]	MAIN[2][2][40]	CELL[0].IMUX_BUFG_O[5]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits																	Destination
MAIN[2][0][70]	MAIN[2][0][71]	MAIN[2][0][72]	MAIN[2][0][73]	MAIN[2][0][66]	MAIN[2][0][79]	MAIN[2][0][78]	MAIN[2][0][77]	MAIN[2][0][76]	MAIN[2][0][75]	MAIN[2][0][74]	MAIN[2][0][67]	MAIN[2][0][68]	MAIN[2][0][65]	MAIN[2][0][64]	MAIN[2][0][63]	MAIN[2][0][60]	CELL[0].IMUX_BUFG_O[6]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits																	Destination
MAIN[2][2][70]	MAIN[2][2][71]	MAIN[2][2][72]	MAIN[2][2][73]	MAIN[2][2][66]	MAIN[2][2][79]	MAIN[2][2][78]	MAIN[2][2][77]	MAIN[2][2][76]	MAIN[2][2][75]	MAIN[2][2][74]	MAIN[2][2][67]	MAIN[2][2][68]	MAIN[2][2][65]	MAIN[2][2][64]	MAIN[2][2][63]	MAIN[2][2][60]	CELL[0].IMUX_BUFG_O[7]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits																	Destination
MAIN[3][0][10]	MAIN[3][0][11]	MAIN[3][0][12]	MAIN[3][0][13]	MAIN[3][0][6]	MAIN[3][0][19]	MAIN[3][0][18]	MAIN[3][0][17]	MAIN[3][0][16]	MAIN[3][0][15]	MAIN[3][0][14]	MAIN[3][0][7]	MAIN[3][0][8]	MAIN[3][0][5]	MAIN[3][0][4]	MAIN[3][0][3]	MAIN[3][0][0]	CELL[0].IMUX_BUFG_O[8]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits																	Destination
MAIN[3][2][10]	MAIN[3][2][11]	MAIN[3][2][12]	MAIN[3][2][13]	MAIN[3][2][6]	MAIN[3][2][19]	MAIN[3][2][18]	MAIN[3][2][17]	MAIN[3][2][16]	MAIN[3][2][15]	MAIN[3][2][14]	MAIN[3][2][7]	MAIN[3][2][8]	MAIN[3][2][5]	MAIN[3][2][4]	MAIN[3][2][3]	MAIN[3][2][0]	CELL[0].IMUX_BUFG_O[9]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits																	Destination
MAIN[3][0][30]	MAIN[3][0][31]	MAIN[3][0][32]	MAIN[3][0][33]	MAIN[3][0][26]	MAIN[3][0][39]	MAIN[3][0][38]	MAIN[3][0][37]	MAIN[3][0][36]	MAIN[3][0][35]	MAIN[3][0][34]	MAIN[3][0][27]	MAIN[3][0][28]	MAIN[3][0][25]	MAIN[3][0][24]	MAIN[3][0][23]	MAIN[3][0][20]	CELL[0].IMUX_BUFG_O[10]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits																	Destination
MAIN[3][2][30]	MAIN[3][2][31]	MAIN[3][2][32]	MAIN[3][2][33]	MAIN[3][2][26]	MAIN[3][2][39]	MAIN[3][2][38]	MAIN[3][2][37]	MAIN[3][2][36]	MAIN[3][2][35]	MAIN[3][2][34]	MAIN[3][2][27]	MAIN[3][2][28]	MAIN[3][2][25]	MAIN[3][2][24]	MAIN[3][2][23]	MAIN[3][2][20]	CELL[0].IMUX_BUFG_O[11]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits																	Destination
MAIN[3][0][50]	MAIN[3][0][51]	MAIN[3][0][52]	MAIN[3][0][53]	MAIN[3][0][46]	MAIN[3][0][59]	MAIN[3][0][58]	MAIN[3][0][57]	MAIN[3][0][56]	MAIN[3][0][55]	MAIN[3][0][54]	MAIN[3][0][47]	MAIN[3][0][48]	MAIN[3][0][45]	MAIN[3][0][44]	MAIN[3][0][43]	MAIN[3][0][40]	CELL[0].IMUX_BUFG_O[12]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits																	Destination
MAIN[3][2][50]	MAIN[3][2][51]	MAIN[3][2][52]	MAIN[3][2][53]	MAIN[3][2][46]	MAIN[3][2][59]	MAIN[3][2][58]	MAIN[3][2][57]	MAIN[3][2][56]	MAIN[3][2][55]	MAIN[3][2][54]	MAIN[3][2][47]	MAIN[3][2][48]	MAIN[3][2][45]	MAIN[3][2][44]	MAIN[3][2][43]	MAIN[3][2][40]	CELL[0].IMUX_BUFG_O[13]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits																	Destination
MAIN[3][0][70]	MAIN[3][0][71]	MAIN[3][0][72]	MAIN[3][0][73]	MAIN[3][0][66]	MAIN[3][0][79]	MAIN[3][0][78]	MAIN[3][0][77]	MAIN[3][0][76]	MAIN[3][0][75]	MAIN[3][0][74]	MAIN[3][0][67]	MAIN[3][0][68]	MAIN[3][0][65]	MAIN[3][0][64]	MAIN[3][0][63]	MAIN[3][0][60]	CELL[0].IMUX_BUFG_O[14]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits																	Destination
MAIN[3][2][70]	MAIN[3][2][71]	MAIN[3][2][72]	MAIN[3][2][73]	MAIN[3][2][66]	MAIN[3][2][79]	MAIN[3][2][78]	MAIN[3][2][77]	MAIN[3][2][76]	MAIN[3][2][75]	MAIN[3][2][74]	MAIN[3][2][67]	MAIN[3][2][68]	MAIN[3][2][65]	MAIN[3][2][64]	MAIN[3][2][63]	MAIN[3][2][60]	CELL[0].IMUX_BUFG_O[15]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits																	Destination
MAIN[4][0][10]	MAIN[4][0][11]	MAIN[4][0][12]	MAIN[4][0][13]	MAIN[4][0][6]	MAIN[4][0][19]	MAIN[4][0][18]	MAIN[4][0][17]	MAIN[4][0][16]	MAIN[4][0][15]	MAIN[4][0][14]	MAIN[4][0][7]	MAIN[4][0][8]	MAIN[4][0][5]	MAIN[4][0][4]	MAIN[4][0][3]	MAIN[4][0][0]	CELL[0].IMUX_BUFG_O[16]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits																	Destination
MAIN[4][2][10]	MAIN[4][2][11]	MAIN[4][2][12]	MAIN[4][2][13]	MAIN[4][2][6]	MAIN[4][2][19]	MAIN[4][2][18]	MAIN[4][2][17]	MAIN[4][2][16]	MAIN[4][2][15]	MAIN[4][2][14]	MAIN[4][2][7]	MAIN[4][2][8]	MAIN[4][2][5]	MAIN[4][2][4]	MAIN[4][2][3]	MAIN[4][2][0]	CELL[0].IMUX_BUFG_O[17]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits																	Destination
MAIN[4][0][30]	MAIN[4][0][31]	MAIN[4][0][32]	MAIN[4][0][33]	MAIN[4][0][26]	MAIN[4][0][39]	MAIN[4][0][38]	MAIN[4][0][37]	MAIN[4][0][36]	MAIN[4][0][35]	MAIN[4][0][34]	MAIN[4][0][27]	MAIN[4][0][28]	MAIN[4][0][25]	MAIN[4][0][24]	MAIN[4][0][23]	MAIN[4][0][20]	CELL[0].IMUX_BUFG_O[18]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits																	Destination
MAIN[4][2][30]	MAIN[4][2][31]	MAIN[4][2][32]	MAIN[4][2][33]	MAIN[4][2][26]	MAIN[4][2][39]	MAIN[4][2][38]	MAIN[4][2][37]	MAIN[4][2][36]	MAIN[4][2][35]	MAIN[4][2][34]	MAIN[4][2][27]	MAIN[4][2][28]	MAIN[4][2][25]	MAIN[4][2][24]	MAIN[4][2][23]	MAIN[4][2][20]	CELL[0].IMUX_BUFG_O[19]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits																	Destination
MAIN[4][0][50]	MAIN[4][0][51]	MAIN[4][0][52]	MAIN[4][0][53]	MAIN[4][0][46]	MAIN[4][0][59]	MAIN[4][0][58]	MAIN[4][0][57]	MAIN[4][0][56]	MAIN[4][0][55]	MAIN[4][0][54]	MAIN[4][0][47]	MAIN[4][0][48]	MAIN[4][0][45]	MAIN[4][0][44]	MAIN[4][0][43]	MAIN[4][0][40]	CELL[0].IMUX_BUFG_O[20]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits																	Destination
MAIN[4][2][50]	MAIN[4][2][51]	MAIN[4][2][52]	MAIN[4][2][53]	MAIN[4][2][46]	MAIN[4][2][59]	MAIN[4][2][58]	MAIN[4][2][57]	MAIN[4][2][56]	MAIN[4][2][55]	MAIN[4][2][54]	MAIN[4][2][47]	MAIN[4][2][48]	MAIN[4][2][45]	MAIN[4][2][44]	MAIN[4][2][43]	MAIN[4][2][40]	CELL[0].IMUX_BUFG_O[21]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits																	Destination
MAIN[4][0][70]	MAIN[4][0][71]	MAIN[4][0][72]	MAIN[4][0][73]	MAIN[4][0][66]	MAIN[4][0][79]	MAIN[4][0][78]	MAIN[4][0][77]	MAIN[4][0][76]	MAIN[4][0][75]	MAIN[4][0][74]	MAIN[4][0][67]	MAIN[4][0][68]	MAIN[4][0][65]	MAIN[4][0][64]	MAIN[4][0][63]	MAIN[4][0][60]	CELL[0].IMUX_BUFG_O[22]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits																	Destination
MAIN[4][2][70]	MAIN[4][2][71]	MAIN[4][2][72]	MAIN[4][2][73]	MAIN[4][2][66]	MAIN[4][2][79]	MAIN[4][2][78]	MAIN[4][2][77]	MAIN[4][2][76]	MAIN[4][2][75]	MAIN[4][2][74]	MAIN[4][2][67]	MAIN[4][2][68]	MAIN[4][2][65]	MAIN[4][2][64]	MAIN[4][2][63]	MAIN[4][2][60]	CELL[0].IMUX_BUFG_O[23]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits																	Destination
MAIN[5][0][10]	MAIN[5][0][11]	MAIN[5][0][12]	MAIN[5][0][13]	MAIN[5][0][6]	MAIN[5][0][19]	MAIN[5][0][18]	MAIN[5][0][17]	MAIN[5][0][16]	MAIN[5][0][15]	MAIN[5][0][14]	MAIN[5][0][7]	MAIN[5][0][8]	MAIN[5][0][5]	MAIN[5][0][4]	MAIN[5][0][3]	MAIN[5][0][0]	CELL[0].IMUX_BUFG_O[24]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits																	Destination
MAIN[5][2][10]	MAIN[5][2][11]	MAIN[5][2][12]	MAIN[5][2][13]	MAIN[5][2][6]	MAIN[5][2][19]	MAIN[5][2][18]	MAIN[5][2][17]	MAIN[5][2][16]	MAIN[5][2][15]	MAIN[5][2][14]	MAIN[5][2][7]	MAIN[5][2][8]	MAIN[5][2][5]	MAIN[5][2][4]	MAIN[5][2][3]	MAIN[5][2][0]	CELL[0].IMUX_BUFG_O[25]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits																	Destination
MAIN[5][0][30]	MAIN[5][0][31]	MAIN[5][0][32]	MAIN[5][0][33]	MAIN[5][0][26]	MAIN[5][0][39]	MAIN[5][0][38]	MAIN[5][0][37]	MAIN[5][0][36]	MAIN[5][0][35]	MAIN[5][0][34]	MAIN[5][0][27]	MAIN[5][0][28]	MAIN[5][0][25]	MAIN[5][0][24]	MAIN[5][0][23]	MAIN[5][0][20]	CELL[0].IMUX_BUFG_O[26]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits																	Destination
MAIN[5][2][30]	MAIN[5][2][31]	MAIN[5][2][32]	MAIN[5][2][33]	MAIN[5][2][26]	MAIN[5][2][39]	MAIN[5][2][38]	MAIN[5][2][37]	MAIN[5][2][36]	MAIN[5][2][35]	MAIN[5][2][34]	MAIN[5][2][27]	MAIN[5][2][28]	MAIN[5][2][25]	MAIN[5][2][24]	MAIN[5][2][23]	MAIN[5][2][20]	CELL[0].IMUX_BUFG_O[27]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits																	Destination
MAIN[5][0][50]	MAIN[5][0][51]	MAIN[5][0][52]	MAIN[5][0][53]	MAIN[5][0][46]	MAIN[5][0][59]	MAIN[5][0][58]	MAIN[5][0][57]	MAIN[5][0][56]	MAIN[5][0][55]	MAIN[5][0][54]	MAIN[5][0][47]	MAIN[5][0][48]	MAIN[5][0][45]	MAIN[5][0][44]	MAIN[5][0][43]	MAIN[5][0][40]	CELL[0].IMUX_BUFG_O[28]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits																	Destination
MAIN[5][2][50]	MAIN[5][2][51]	MAIN[5][2][52]	MAIN[5][2][53]	MAIN[5][2][46]	MAIN[5][2][59]	MAIN[5][2][58]	MAIN[5][2][57]	MAIN[5][2][56]	MAIN[5][2][55]	MAIN[5][2][54]	MAIN[5][2][47]	MAIN[5][2][48]	MAIN[5][2][45]	MAIN[5][2][44]	MAIN[5][2][43]	MAIN[5][2][40]	CELL[0].IMUX_BUFG_O[29]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits																	Destination
MAIN[5][0][70]	MAIN[5][0][71]	MAIN[5][0][72]	MAIN[5][0][73]	MAIN[5][0][66]	MAIN[5][0][79]	MAIN[5][0][78]	MAIN[5][0][77]	MAIN[5][0][76]	MAIN[5][0][75]	MAIN[5][0][74]	MAIN[5][0][67]	MAIN[5][0][68]	MAIN[5][0][65]	MAIN[5][0][64]	MAIN[5][0][63]	MAIN[5][0][60]	CELL[0].IMUX_BUFG_O[30]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_S switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits																	Destination
MAIN[5][2][70]	MAIN[5][2][71]	MAIN[5][2][72]	MAIN[5][2][73]	MAIN[5][2][66]	MAIN[5][2][79]	MAIN[5][2][78]	MAIN[5][2][77]	MAIN[5][2][76]	MAIN[5][2][75]	MAIN[5][2][74]	MAIN[5][2][67]	MAIN[5][2][68]	MAIN[5][2][65]	MAIN[5][2][64]	MAIN[5][2][63]	MAIN[5][2][60]	CELL[0].IMUX_BUFG_O[31]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

Bitstream

virtex4 CLK_DCM_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_S rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 14
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 15
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 16
B69	-	-	-
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B62	-	-	-
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 14
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 15
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 16
B49	-	-	-
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B42	-	-	-
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 14
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 15
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 16
B29	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B22	-	-	-
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 14
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 15
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 16
B9	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B2	-	-	-
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0

virtex4 CLK_DCM_S rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 14
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 15
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 16
B69	-	-	-
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B62	-	-	-
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 14
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 15
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 16
B49	-	-	-
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B42	-	-	-
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 14
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 15
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 16
B29	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B22	-	-	-
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 14
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 15
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 16
B9	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B2	-	-	-
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0

virtex4 CLK_DCM_S rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 14
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 15
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 16
B69	-	-	-
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B62	-	-	-
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 14
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 15
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 16
B49	-	-	-
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B42	-	-	-
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 14
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 15
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 16
B29	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B22	-	-	-
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 14
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 15
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 16
B9	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B2	-	-	-
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0

virtex4 CLK_DCM_S rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11
B78	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B77	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 14
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 15
B70	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 16
B69	-	-	-
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B62	-	-	-
B61	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 14
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 15
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 16
B49	-	-	-
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B42	-	-	-
B41	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 14
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 15
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 16
B29	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B22	-	-	-
B21	-	-	-
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 14
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 15
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 16
B9	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B2	-	-	-
B1	-	-	-
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0

virtex4 CLK_DCM_S rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_S rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

Tile CLK_DCM_N

Cells: 8

Switchbox CLK_INT

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits																	Destination
MAIN[5][0][69]	MAIN[5][0][68]	MAIN[5][0][67]	MAIN[5][0][66]	MAIN[5][0][72]	MAIN[5][0][60]	MAIN[5][0][61]	MAIN[5][0][62]	MAIN[5][0][63]	MAIN[5][0][64]	MAIN[5][0][65]	MAIN[5][0][73]	MAIN[5][0][79]	MAIN[5][0][76]	MAIN[5][0][75]	MAIN[5][0][74]	MAIN[5][0][71]	CELL[0].IMUX_BUFG_O[0]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits																	Destination
MAIN[5][2][69]	MAIN[5][2][68]	MAIN[5][2][67]	MAIN[5][2][66]	MAIN[5][2][72]	MAIN[5][2][60]	MAIN[5][2][61]	MAIN[5][2][62]	MAIN[5][2][63]	MAIN[5][2][64]	MAIN[5][2][65]	MAIN[5][2][73]	MAIN[5][2][79]	MAIN[5][2][76]	MAIN[5][2][75]	MAIN[5][2][74]	MAIN[5][2][71]	CELL[0].IMUX_BUFG_O[1]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits																	Destination
MAIN[5][0][49]	MAIN[5][0][48]	MAIN[5][0][47]	MAIN[5][0][46]	MAIN[5][0][52]	MAIN[5][0][40]	MAIN[5][0][41]	MAIN[5][0][42]	MAIN[5][0][43]	MAIN[5][0][44]	MAIN[5][0][45]	MAIN[5][0][53]	MAIN[5][0][59]	MAIN[5][0][56]	MAIN[5][0][55]	MAIN[5][0][54]	MAIN[5][0][51]	CELL[0].IMUX_BUFG_O[2]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits																	Destination
MAIN[5][2][49]	MAIN[5][2][48]	MAIN[5][2][47]	MAIN[5][2][46]	MAIN[5][2][52]	MAIN[5][2][40]	MAIN[5][2][41]	MAIN[5][2][42]	MAIN[5][2][43]	MAIN[5][2][44]	MAIN[5][2][45]	MAIN[5][2][53]	MAIN[5][2][59]	MAIN[5][2][56]	MAIN[5][2][55]	MAIN[5][2][54]	MAIN[5][2][51]	CELL[0].IMUX_BUFG_O[3]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits																	Destination
MAIN[5][0][29]	MAIN[5][0][28]	MAIN[5][0][27]	MAIN[5][0][26]	MAIN[5][0][32]	MAIN[5][0][20]	MAIN[5][0][21]	MAIN[5][0][22]	MAIN[5][0][23]	MAIN[5][0][24]	MAIN[5][0][25]	MAIN[5][0][33]	MAIN[5][0][39]	MAIN[5][0][36]	MAIN[5][0][35]	MAIN[5][0][34]	MAIN[5][0][31]	CELL[0].IMUX_BUFG_O[4]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits																	Destination
MAIN[5][2][29]	MAIN[5][2][28]	MAIN[5][2][27]	MAIN[5][2][26]	MAIN[5][2][32]	MAIN[5][2][20]	MAIN[5][2][21]	MAIN[5][2][22]	MAIN[5][2][23]	MAIN[5][2][24]	MAIN[5][2][25]	MAIN[5][2][33]	MAIN[5][2][39]	MAIN[5][2][36]	MAIN[5][2][35]	MAIN[5][2][34]	MAIN[5][2][31]	CELL[0].IMUX_BUFG_O[5]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits																	Destination
MAIN[5][0][9]	MAIN[5][0][8]	MAIN[5][0][7]	MAIN[5][0][6]	MAIN[5][0][12]	MAIN[5][0][0]	MAIN[5][0][1]	MAIN[5][0][2]	MAIN[5][0][3]	MAIN[5][0][4]	MAIN[5][0][5]	MAIN[5][0][13]	MAIN[5][0][19]	MAIN[5][0][16]	MAIN[5][0][15]	MAIN[5][0][14]	MAIN[5][0][11]	CELL[0].IMUX_BUFG_O[6]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits																	Destination
MAIN[5][2][9]	MAIN[5][2][8]	MAIN[5][2][7]	MAIN[5][2][6]	MAIN[5][2][12]	MAIN[5][2][0]	MAIN[5][2][1]	MAIN[5][2][2]	MAIN[5][2][3]	MAIN[5][2][4]	MAIN[5][2][5]	MAIN[5][2][13]	MAIN[5][2][19]	MAIN[5][2][16]	MAIN[5][2][15]	MAIN[5][2][14]	MAIN[5][2][11]	CELL[0].IMUX_BUFG_O[7]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits																	Destination
MAIN[4][0][69]	MAIN[4][0][68]	MAIN[4][0][67]	MAIN[4][0][66]	MAIN[4][0][72]	MAIN[4][0][60]	MAIN[4][0][61]	MAIN[4][0][62]	MAIN[4][0][63]	MAIN[4][0][64]	MAIN[4][0][65]	MAIN[4][0][73]	MAIN[4][0][79]	MAIN[4][0][76]	MAIN[4][0][75]	MAIN[4][0][74]	MAIN[4][0][71]	CELL[0].IMUX_BUFG_O[8]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits																	Destination
MAIN[4][2][69]	MAIN[4][2][68]	MAIN[4][2][67]	MAIN[4][2][66]	MAIN[4][2][72]	MAIN[4][2][60]	MAIN[4][2][61]	MAIN[4][2][62]	MAIN[4][2][63]	MAIN[4][2][64]	MAIN[4][2][65]	MAIN[4][2][73]	MAIN[4][2][79]	MAIN[4][2][76]	MAIN[4][2][75]	MAIN[4][2][74]	MAIN[4][2][71]	CELL[0].IMUX_BUFG_O[9]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits																	Destination
MAIN[4][0][49]	MAIN[4][0][48]	MAIN[4][0][47]	MAIN[4][0][46]	MAIN[4][0][52]	MAIN[4][0][40]	MAIN[4][0][41]	MAIN[4][0][42]	MAIN[4][0][43]	MAIN[4][0][44]	MAIN[4][0][45]	MAIN[4][0][53]	MAIN[4][0][59]	MAIN[4][0][56]	MAIN[4][0][55]	MAIN[4][0][54]	MAIN[4][0][51]	CELL[0].IMUX_BUFG_O[10]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits																	Destination
MAIN[4][2][49]	MAIN[4][2][48]	MAIN[4][2][47]	MAIN[4][2][46]	MAIN[4][2][52]	MAIN[4][2][40]	MAIN[4][2][41]	MAIN[4][2][42]	MAIN[4][2][43]	MAIN[4][2][44]	MAIN[4][2][45]	MAIN[4][2][53]	MAIN[4][2][59]	MAIN[4][2][56]	MAIN[4][2][55]	MAIN[4][2][54]	MAIN[4][2][51]	CELL[0].IMUX_BUFG_O[11]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits																	Destination
MAIN[4][0][29]	MAIN[4][0][28]	MAIN[4][0][27]	MAIN[4][0][26]	MAIN[4][0][32]	MAIN[4][0][20]	MAIN[4][0][21]	MAIN[4][0][22]	MAIN[4][0][23]	MAIN[4][0][24]	MAIN[4][0][25]	MAIN[4][0][33]	MAIN[4][0][39]	MAIN[4][0][36]	MAIN[4][0][35]	MAIN[4][0][34]	MAIN[4][0][31]	CELL[0].IMUX_BUFG_O[12]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits																	Destination
MAIN[4][2][29]	MAIN[4][2][28]	MAIN[4][2][27]	MAIN[4][2][26]	MAIN[4][2][32]	MAIN[4][2][20]	MAIN[4][2][21]	MAIN[4][2][22]	MAIN[4][2][23]	MAIN[4][2][24]	MAIN[4][2][25]	MAIN[4][2][33]	MAIN[4][2][39]	MAIN[4][2][36]	MAIN[4][2][35]	MAIN[4][2][34]	MAIN[4][2][31]	CELL[0].IMUX_BUFG_O[13]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits																	Destination
MAIN[4][0][9]	MAIN[4][0][8]	MAIN[4][0][7]	MAIN[4][0][6]	MAIN[4][0][12]	MAIN[4][0][0]	MAIN[4][0][1]	MAIN[4][0][2]	MAIN[4][0][3]	MAIN[4][0][4]	MAIN[4][0][5]	MAIN[4][0][13]	MAIN[4][0][19]	MAIN[4][0][16]	MAIN[4][0][15]	MAIN[4][0][14]	MAIN[4][0][11]	CELL[0].IMUX_BUFG_O[14]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits																	Destination
MAIN[4][2][9]	MAIN[4][2][8]	MAIN[4][2][7]	MAIN[4][2][6]	MAIN[4][2][12]	MAIN[4][2][0]	MAIN[4][2][1]	MAIN[4][2][2]	MAIN[4][2][3]	MAIN[4][2][4]	MAIN[4][2][5]	MAIN[4][2][13]	MAIN[4][2][19]	MAIN[4][2][16]	MAIN[4][2][15]	MAIN[4][2][14]	MAIN[4][2][11]	CELL[0].IMUX_BUFG_O[15]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits																	Destination
MAIN[3][0][69]	MAIN[3][0][68]	MAIN[3][0][67]	MAIN[3][0][66]	MAIN[3][0][72]	MAIN[3][0][60]	MAIN[3][0][61]	MAIN[3][0][62]	MAIN[3][0][63]	MAIN[3][0][64]	MAIN[3][0][65]	MAIN[3][0][73]	MAIN[3][0][79]	MAIN[3][0][76]	MAIN[3][0][75]	MAIN[3][0][74]	MAIN[3][0][71]	CELL[0].IMUX_BUFG_O[16]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits																	Destination
MAIN[3][2][69]	MAIN[3][2][68]	MAIN[3][2][67]	MAIN[3][2][66]	MAIN[3][2][72]	MAIN[3][2][60]	MAIN[3][2][61]	MAIN[3][2][62]	MAIN[3][2][63]	MAIN[3][2][64]	MAIN[3][2][65]	MAIN[3][2][73]	MAIN[3][2][79]	MAIN[3][2][76]	MAIN[3][2][75]	MAIN[3][2][74]	MAIN[3][2][71]	CELL[0].IMUX_BUFG_O[17]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits																	Destination
MAIN[3][0][49]	MAIN[3][0][48]	MAIN[3][0][47]	MAIN[3][0][46]	MAIN[3][0][52]	MAIN[3][0][40]	MAIN[3][0][41]	MAIN[3][0][42]	MAIN[3][0][43]	MAIN[3][0][44]	MAIN[3][0][45]	MAIN[3][0][53]	MAIN[3][0][59]	MAIN[3][0][56]	MAIN[3][0][55]	MAIN[3][0][54]	MAIN[3][0][51]	CELL[0].IMUX_BUFG_O[18]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits																	Destination
MAIN[3][2][49]	MAIN[3][2][48]	MAIN[3][2][47]	MAIN[3][2][46]	MAIN[3][2][52]	MAIN[3][2][40]	MAIN[3][2][41]	MAIN[3][2][42]	MAIN[3][2][43]	MAIN[3][2][44]	MAIN[3][2][45]	MAIN[3][2][53]	MAIN[3][2][59]	MAIN[3][2][56]	MAIN[3][2][55]	MAIN[3][2][54]	MAIN[3][2][51]	CELL[0].IMUX_BUFG_O[19]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits																	Destination
MAIN[3][0][29]	MAIN[3][0][28]	MAIN[3][0][27]	MAIN[3][0][26]	MAIN[3][0][32]	MAIN[3][0][20]	MAIN[3][0][21]	MAIN[3][0][22]	MAIN[3][0][23]	MAIN[3][0][24]	MAIN[3][0][25]	MAIN[3][0][33]	MAIN[3][0][39]	MAIN[3][0][36]	MAIN[3][0][35]	MAIN[3][0][34]	MAIN[3][0][31]	CELL[0].IMUX_BUFG_O[20]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits																	Destination
MAIN[3][2][29]	MAIN[3][2][28]	MAIN[3][2][27]	MAIN[3][2][26]	MAIN[3][2][32]	MAIN[3][2][20]	MAIN[3][2][21]	MAIN[3][2][22]	MAIN[3][2][23]	MAIN[3][2][24]	MAIN[3][2][25]	MAIN[3][2][33]	MAIN[3][2][39]	MAIN[3][2][36]	MAIN[3][2][35]	MAIN[3][2][34]	MAIN[3][2][31]	CELL[0].IMUX_BUFG_O[21]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits																	Destination
MAIN[3][0][9]	MAIN[3][0][8]	MAIN[3][0][7]	MAIN[3][0][6]	MAIN[3][0][12]	MAIN[3][0][0]	MAIN[3][0][1]	MAIN[3][0][2]	MAIN[3][0][3]	MAIN[3][0][4]	MAIN[3][0][5]	MAIN[3][0][13]	MAIN[3][0][19]	MAIN[3][0][16]	MAIN[3][0][15]	MAIN[3][0][14]	MAIN[3][0][11]	CELL[0].IMUX_BUFG_O[22]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits																	Destination
MAIN[3][2][9]	MAIN[3][2][8]	MAIN[3][2][7]	MAIN[3][2][6]	MAIN[3][2][12]	MAIN[3][2][0]	MAIN[3][2][1]	MAIN[3][2][2]	MAIN[3][2][3]	MAIN[3][2][4]	MAIN[3][2][5]	MAIN[3][2][13]	MAIN[3][2][19]	MAIN[3][2][16]	MAIN[3][2][15]	MAIN[3][2][14]	MAIN[3][2][11]	CELL[0].IMUX_BUFG_O[23]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits																	Destination
MAIN[2][0][69]	MAIN[2][0][68]	MAIN[2][0][67]	MAIN[2][0][66]	MAIN[2][0][72]	MAIN[2][0][60]	MAIN[2][0][61]	MAIN[2][0][62]	MAIN[2][0][63]	MAIN[2][0][64]	MAIN[2][0][65]	MAIN[2][0][73]	MAIN[2][0][79]	MAIN[2][0][76]	MAIN[2][0][75]	MAIN[2][0][74]	MAIN[2][0][71]	CELL[0].IMUX_BUFG_O[24]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits																	Destination
MAIN[2][2][69]	MAIN[2][2][68]	MAIN[2][2][67]	MAIN[2][2][66]	MAIN[2][2][72]	MAIN[2][2][60]	MAIN[2][2][61]	MAIN[2][2][62]	MAIN[2][2][63]	MAIN[2][2][64]	MAIN[2][2][65]	MAIN[2][2][73]	MAIN[2][2][79]	MAIN[2][2][76]	MAIN[2][2][75]	MAIN[2][2][74]	MAIN[2][2][71]	CELL[0].IMUX_BUFG_O[25]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits																	Destination
MAIN[2][0][49]	MAIN[2][0][48]	MAIN[2][0][47]	MAIN[2][0][46]	MAIN[2][0][52]	MAIN[2][0][40]	MAIN[2][0][41]	MAIN[2][0][42]	MAIN[2][0][43]	MAIN[2][0][44]	MAIN[2][0][45]	MAIN[2][0][53]	MAIN[2][0][59]	MAIN[2][0][56]	MAIN[2][0][55]	MAIN[2][0][54]	MAIN[2][0][51]	CELL[0].IMUX_BUFG_O[26]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits																	Destination
MAIN[2][2][49]	MAIN[2][2][48]	MAIN[2][2][47]	MAIN[2][2][46]	MAIN[2][2][52]	MAIN[2][2][40]	MAIN[2][2][41]	MAIN[2][2][42]	MAIN[2][2][43]	MAIN[2][2][44]	MAIN[2][2][45]	MAIN[2][2][53]	MAIN[2][2][59]	MAIN[2][2][56]	MAIN[2][2][55]	MAIN[2][2][54]	MAIN[2][2][51]	CELL[0].IMUX_BUFG_O[27]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits																	Destination
MAIN[2][0][29]	MAIN[2][0][28]	MAIN[2][0][27]	MAIN[2][0][26]	MAIN[2][0][32]	MAIN[2][0][20]	MAIN[2][0][21]	MAIN[2][0][22]	MAIN[2][0][23]	MAIN[2][0][24]	MAIN[2][0][25]	MAIN[2][0][33]	MAIN[2][0][39]	MAIN[2][0][36]	MAIN[2][0][35]	MAIN[2][0][34]	MAIN[2][0][31]	CELL[0].IMUX_BUFG_O[28]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits																	Destination
MAIN[2][2][29]	MAIN[2][2][28]	MAIN[2][2][27]	MAIN[2][2][26]	MAIN[2][2][32]	MAIN[2][2][20]	MAIN[2][2][21]	MAIN[2][2][22]	MAIN[2][2][23]	MAIN[2][2][24]	MAIN[2][2][25]	MAIN[2][2][33]	MAIN[2][2][39]	MAIN[2][2][36]	MAIN[2][2][35]	MAIN[2][2][34]	MAIN[2][2][31]	CELL[0].IMUX_BUFG_O[29]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits																	Destination
MAIN[2][0][9]	MAIN[2][0][8]	MAIN[2][0][7]	MAIN[2][0][6]	MAIN[2][0][12]	MAIN[2][0][0]	MAIN[2][0][1]	MAIN[2][0][2]	MAIN[2][0][3]	MAIN[2][0][4]	MAIN[2][0][5]	MAIN[2][0][13]	MAIN[2][0][19]	MAIN[2][0][16]	MAIN[2][0][15]	MAIN[2][0][14]	MAIN[2][0][11]	CELL[0].IMUX_BUFG_O[30]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

virtex4 CLK_DCM_N switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits																	Destination
MAIN[2][2][9]	MAIN[2][2][8]	MAIN[2][2][7]	MAIN[2][2][6]	MAIN[2][2][12]	MAIN[2][2][0]	MAIN[2][2][1]	MAIN[2][2][2]	MAIN[2][2][3]	MAIN[2][2][4]	MAIN[2][2][5]	MAIN[2][2][13]	MAIN[2][2][19]	MAIN[2][2][16]	MAIN[2][2][15]	MAIN[2][2][14]	MAIN[2][2][11]	CELL[0].IMUX_BUFG_O[31]
																	Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[0]
0	0	0	1	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[1]
0	0	0	1	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[2]
0	0	0	1	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[3]
0	0	0	1	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[4]
0	0	0	1	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[5]
0	0	1	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[0].OUT_DCM[6]
0	0	1	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[0].OUT_DCM[7]
0	0	1	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[8]
0	0	1	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[9]
0	0	1	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[10]
0	0	1	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[0].OUT_DCM[11]
0	1	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[0]
0	1	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[1]
0	1	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[2]
0	1	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[3]
0	1	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[4]
0	1	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[5]
1	0	0	0	0	0	0	0	0	0	1	0	1	1	1	1	1	CELL[4].OUT_DCM[6]
1	0	0	0	0	0	0	0	0	1	0	0	1	1	1	1	1	CELL[4].OUT_DCM[7]
1	0	0	0	0	0	0	0	1	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[8]
1	0	0	0	0	0	0	1	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[9]
1	0	0	0	0	0	1	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[10]
1	0	0	0	0	1	0	0	0	0	0	0	1	1	1	1	1	CELL[4].OUT_DCM[11]

Bitstream

virtex4 CLK_DCM_N rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_N rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B78	-	-	-
B77	-	-	-
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 16
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 15
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 14
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B58	-	-	-
B57	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 16
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 15
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 14
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B38	-	-	-
B37	-	-	-
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 16
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 15
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 14
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B18	-	-	-
B17	-	-	-
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 16
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 15
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 14
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11

virtex4 CLK_DCM_N rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B78	-	-	-
B77	-	-	-
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 16
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 15
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 14
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B58	-	-	-
B57	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 16
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 15
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 14
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B38	-	-	-
B37	-	-	-
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 16
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 15
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 14
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B18	-	-	-
B17	-	-	-
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 16
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 15
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 14
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11

virtex4 CLK_DCM_N rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B78	-	-	-
B77	-	-	-
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 16
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 15
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 14
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B58	-	-	-
B57	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 16
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 15
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 14
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B38	-	-	-
B37	-	-	-
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 16
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 15
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 14
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B18	-	-	-
B17	-	-	-
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 16
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 15
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 14
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11

virtex4 CLK_DCM_N rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2
B79	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B78	-	-	-
B77	-	-	-
B76	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B75	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B74	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B73	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B72	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B71	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0
B70	-	-	-
B69	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 16
B68	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 15
B67	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 14
B66	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13
B65	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6
B64	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7
B63	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B58	-	-	-
B57	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B50	-	-	-
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 16
B48	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 15
B47	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 14
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B38	-	-	-
B37	-	-	-
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B32	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B31	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B30	-	-	-
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 16
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 15
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 14
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B18	-	-	-
B17	-	-	-
B16	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B15	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B10	-	-	-
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 16	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 16
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 15	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 15
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 14
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B0	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11

virtex4 CLK_DCM_N rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

virtex4 CLK_DCM_N rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2
B79	-	-	-
B78	-	-	-
B77	-	-	-
B76	-	-	-
B75	-	-	-
B74	-	-	-
B73	-	-	-
B72	-	-	-
B71	-	-	-
B70	-	-	-
B69	-	-	-
B68	-	-	-
B67	-	-	-
B66	-	-	-
B65	-	-	-
B64	-	-	-
B63	-	-	-
B62	-	-	-
B61	-	-	-
B60	-	-	-
B59	-	-	-
B58	-	-	-
B57	-	-	-
B56	-	-	-
B55	-	-	-
B54	-	-	-
B53	-	-	-
B52	-	-	-
B51	-	-	-
B50	-	-	-
B49	-	-	-
B48	-	-	-
B47	-	-	-
B46	-	-	-
B45	-	-	-
B44	-	-	-
B43	-	-	-
B42	-	-	-
B41	-	-	-
B40	-	-	-
B39	-	-	-
B38	-	-	-
B37	-	-	-
B36	-	-	-
B35	-	-	-
B34	-	-	-
B33	-	-	-
B32	-	-	-
B31	-	-	-
B30	-	-	-
B29	-	-	-
B28	-	-	-
B27	-	-	-
B26	-	-	-
B25	-	-	-
B24	-	-	-
B23	-	-	-
B22	-	-	-
B21	-	-	-
B20	-	-	-
B19	-	-	-
B18	-	-	-
B17	-	-	-
B16	-	-	-
B15	-	-	-
B14	-	-	-
B13	-	-	-
B12	-	-	-
B11	-	-	-
B10	-	-	-
B9	-	-	-
B8	-	-	-
B7	-	-	-
B6	-	-	-
B5	-	-	-
B4	-	-	-
B3	-	-	-
B2	-	-	-
B1	-	-	-
B0	-	-	-

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