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Input/Output

I/O banks and special functions

Virtex 4 devices have exactly three I/O columns:

  • the left I/O column, containing only IO tiles; if the device has no transceivers, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column
  • the center column, part of which contains IO tiles; the IO tiles in this column come in two segments:
    • the lower segment, between lower DCMs/CCMs and the configuration center
    • the upper segment, between the configuration center and the upper DCMs/CCMs
  • the right I/O column, containing only IO tiles; if the device has no transceivers, it is the rightmost column of the device; otherwise, it is somewhat to the left of the right GT column

Virtex 4 has the following banks:

  • bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:

    • CCLK
    • CS_B
    • DONE
    • DOUT_BUSY
    • D_IN
    • HSWAP_EN
    • INIT
    • M0
    • M1
    • M2
    • PROGRAM_B
    • PWRDWN_B
    • RDWR_B
    • TCK
    • TDI
    • TDO
    • TMS

    bank 0 is not associated with any IO tiles

  • banks 1-4 are central column banks, with no support for true differential output; they are:

    • bank 1: right above configuration center; has 8, 24, or 40 I/O tiles
    • bank 2: right below configuration center; has 8, 24, or 40 I/O tiles
    • bank 3: above bank 1, below top DCMs/CCMs; always has 8 I/O tiles
    • bank 4: below bank 2, above bottom DCMs/CCMs; always has 8 I/O tiles

  • banks 5-16: left and right column banks; the number of present banks in these column varies between devices, but each bank has a constant size of 32 I/O tiles (ie. is two regions high); the HCLK tile in bottom region of the bank contains DCI control circuitry, while the HCLK tile in top region of the bank contains contains LVDS output circuitry

    • odd-numbered banks belong to the left column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
      • 4 regions: 7, 5
      • 6 regions: 7, 9, 5
      • 8 regions: 7, 11, 9, 5
      • 10 regions: 7, 11, 13, 9, 5
      • 12 regions: 7, 11, 15, 13, 9, 5
    • even-numbered banks belong to the right column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
      • 4 regions: 8, 6
      • 6 regions: 8, 10, 6
      • 8 regions: 8, 12, 10, 6
      • 10 regions: 8, 12, 14, 10, 6
      • 12 regions: 8, 12, 16, 14, 10, 6

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input is supported on all pins of the device. True differential output is supported only in the left and right columns, in all tiles except for rows 7 and 8 of every region (ie. except the “clock-capable” pads).

IOB1 pads next to the HCLK row (that is, in row 7 and 8 of every clock region) are considered “clock-capable”. They can drive BUFIO and BUFR buffers via dedicated connections. While Xilinx documentation also considers IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

The 16 bottommost IOB1 pads and 16 topmost IOB1 pads in the central column are considered “global clock-capable”. They can drive BUFGCTRL buffers and DCM primitives via dedicated connections. Likewise, Xilinx considers IOB0 pads to be clock-capable, but they can only drive clocks as part of differential pair with IOB1.

The IOB0 in rows 4 and 12 of every region is capable of being used as a VREF pad.

Each bank, with some exceptions on the smaller devices, has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

  • bank 1, if the bank has 8 I/O tiles: DCI is not supported in this bank
  • bank 1, if the bank has 24 I/O tiles: row 14 of the bank (row 6 of the topmost region of the bank)
  • bank 1, if the bank has 40 I/O tiles: row 30 of the bank (row 6 of the topmost region of the bank)
  • bank 2, if the bank has 8 I/O tiles: DCI is not supported in this bank
  • bank 2, if the bank has 24 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
  • bank 2, if the bank has 40 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
  • bank 3: row 6 of the bank (row 6 of the region)
  • bank 4: row 1 of the bank (row 9 of the region)
  • banks 5-16: row 9 of the bank (row 9 of the bottom region of the bank)

In parallel configuration modes, some I/O pads in banks 1 and 2 are borrowed for configuration use, as the parallel data pins:

  • D[i], i % 2 == 0, 0 <= i < 16: IOB0 of row i / 2 of topmost region of bank 2
  • D[i], i % 2 == 1, 0 <= i < 16: IOB1 of row (i - 1) / 2 of topmost region of bank 2
  • D[i], i % 2 == 0, 16 <= i < 32: IOB0 of row i / 2 of bottom region of bank 1 (or, row (i - 16) / 2 of the bank)
  • D[i], i % 2 == 1, 16 <= i < 32: IOB1 of row (i - 1) / 2 of bottom region of bank 1 (or, row (i - 17) / 2 of the bank)

Every SYSMON present on the device can use up to seven IOB pairs from the left I/O column as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. The IOBs are in the following tiles, where r is the bottom row of the SYSMON:

  • VP1/VN1: left I/O column, row r
  • VP2/VN2: left I/O column, row r + 1
  • VP3/VN3: left I/O column, row r + 2
  • VP4/VN4: left I/O column, row r + 3
  • VP5/VN5: left I/O column, row r + 5
  • VP6/VN6: left I/O column, row r + 6
  • VP7/VN7: left I/O column, row r + 7

Row r + 4 is not used as SYSMON input — the “analog function” of that pin is considered to be VREF instead (they are controlled by the same bit).

Tile IO

Cells: 1

Switchbox SPEC_INT

virtex4 IO switchbox SPEC_INT muxes IMUX_SPEC[0]
BitsDestination
MAIN[22][29]MAIN[22][34]MAIN[22][33]MAIN[22][32]MAIN[22][37]MAIN[22][36]MAIN[23][38]MAIN[23][37]MAIN[23][36]IMUX_SPEC[0]
Source
000000000off
000000001IMUX_BYP[6]
000100010HCLK_IO[0]
000100100HCLK_IO[4]
000101000RCLK_IO[0]
000110000IOCLK_S_IO[0]
001000010HCLK_IO[1]
001000100HCLK_IO[5]
001001000RCLK_IO[1]
001010000IOCLK_S_IO[1]
010000010HCLK_IO[2]
010000100HCLK_IO[6]
010001000IOCLK[0]
010010000IOCLK_N_IO[0]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000IOCLK[1]
100010000IOCLK_N_IO[1]
virtex4 IO switchbox SPEC_INT muxes IMUX_SPEC[1]
BitsDestination
MAIN[22][35]MAIN[23][35]MAIN[23][34]MAIN[23][33]MAIN[22][30]MAIN[22][31]MAIN[23][31]MAIN[23][30]MAIN[23][32]IMUX_SPEC[1]
Source
000000000off
000000001IMUX_BYP[3]
000100010HCLK_IO[0]
000100100HCLK_IO[4]
000101000RCLK_IO[0]
000110000IOCLK_S_IO[0]
001000010HCLK_IO[1]
001000100HCLK_IO[5]
001001000RCLK_IO[1]
001010000IOCLK_S_IO[1]
010000010HCLK_IO[2]
010000100HCLK_IO[6]
010001000IOCLK[0]
010010000IOCLK_N_IO[0]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000IOCLK[1]
100010000IOCLK_N_IO[1]
virtex4 IO switchbox SPEC_INT muxes IMUX_SPEC[2]
BitsDestination
MAIN[22][50]MAIN[22][45]MAIN[22][46]MAIN[22][47]MAIN[22][42]MAIN[22][43]MAIN[23][41]MAIN[23][42]MAIN[23][43]IMUX_SPEC[2]
Source
000000000off
000000001IMUX_BYP[5]
000100010HCLK_IO[0]
000100100HCLK_IO[4]
000101000RCLK_IO[0]
000110000IOCLK_S_IO[0]
001000010HCLK_IO[1]
001000100HCLK_IO[5]
001001000RCLK_IO[1]
001010000IOCLK_S_IO[1]
010000010HCLK_IO[2]
010000100HCLK_IO[6]
010001000IOCLK[0]
010010000IOCLK_N_IO[0]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000IOCLK[1]
100010000IOCLK_N_IO[1]
virtex4 IO switchbox SPEC_INT muxes IMUX_SPEC[3]
BitsDestination
MAIN[22][44]MAIN[23][44]MAIN[23][45]MAIN[23][46]MAIN[22][49]MAIN[22][48]MAIN[23][48]MAIN[23][49]MAIN[23][47]IMUX_SPEC[3]
Source
000000000off
000000001IMUX_BYP[1]
000100010HCLK_IO[0]
000100100HCLK_IO[4]
000101000RCLK_IO[0]
000110000IOCLK_S_IO[0]
001000010HCLK_IO[1]
001000100HCLK_IO[5]
001001000RCLK_IO[1]
001010000IOCLK_S_IO[1]
010000010HCLK_IO[2]
010000100HCLK_IO[6]
010001000IOCLK[0]
010010000IOCLK_N_IO[0]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000IOCLK[1]
100010000IOCLK_N_IO[1]

Bels ILOGIC

virtex4 IO bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinIMUX_SPEC[1]IMUX_SPEC[3]
CLKDIVinIMUX_CLK_OPTINV[0]IMUX_CLK_OPTINV[2]
SRinIMUX_SR_OPTINV[0] invert by MAIN[20][17]IMUX_SR_OPTINV[1] invert by MAIN[20][62]
REVinIMUX_SR_OPTINV[2] invert by MAIN[19][34]IMUX_SR_OPTINV[3] invert by MAIN[19][45]
CE1inIMUX_IMUX[6] invert by !MAIN[19][39]IMUX_IMUX[2] invert by !MAIN[19][40]
CE2inIMUX_IMUX[14] invert by !MAIN[19][38]IMUX_IMUX[10] invert by !MAIN[19][41]
BITSLIPinIMUX_IMUX[21]IMUX_IMUX[17]
DLYCEinIMUX_IMUX[0]IMUX_IMUX[7]
DLYINCinIMUX_IMUX[29]IMUX_IMUX[3]
DLYRSTinIMUX_IMUX[4]IMUX_IMUX[11]
OoutOUT_BEST_TMIN[2]OUT_BEST_TMIN[0]
Q1outOUT_BEST_TMIN[4]OUT_BEST_TMIN[6]
Q2outOUT_BEST_TMIN[3]OUT_BEST_TMIN[1]
Q3outOUT_BEST_TMIN[5]OUT_BEST_TMIN[7]
Q4outOUT_SEC_TMIN[0]OUT_SEC_TMIN[2]
Q5outOUT_SEC_TMIN[4]OUT_SEC_TMIN[7]
Q6outOUT_SEC_TMIN[5]OUT_SEC_TMIN[6]
CLKPADout-OUT_CLKPAD
virtex4 IO bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]
CLK_INV bit 0!MAIN[19][26]!MAIN[19][53]
CLK_INV bit 1!MAIN[20][25]!MAIN[20][48]
CLK_INV bit 2!MAIN[20][31]!MAIN[20][54]
OCLK1_INVMAIN[20][26]MAIN[20][53]
OCLK2_INVMAIN[19][25]MAIN[19][54]
FFI1_INIT bit 0!MAIN[20][34]!MAIN[20][45]
FFI2_INIT bit 0!MAIN[19][28]!MAIN[19][51]
FFI3_INIT bit 0!MAIN[19][29]!MAIN[19][50]
FFI4_INIT bit 0!MAIN[20][35]!MAIN[20][44]
FFI1_SRVAL bit 0!MAIN[20][27]!MAIN[20][52]
FFI2_SRVAL bit 0!MAIN[20][38]!MAIN[20][41]
FFI3_SRVAL bit 0!MAIN[20][39]!MAIN[20][40]
FFI4_SRVAL bit 0!MAIN[20][28]!MAIN[20][51]
FFI_ENABLEMAIN[21][30]MAIN[21][49]
FFI_LATCH!MAIN[19][36]!MAIN[19][43]
FFI_SR_SYNC!MAIN[19][37]!MAIN[19][42]
INIT_BITSLIPCNT bit 0!MAIN[19][6]MAIN[19][73]
INIT_BITSLIPCNT bit 1!MAIN[20][18]MAIN[20][61]
INIT_BITSLIPCNT bit 2!MAIN[20][24]MAIN[20][55]
INIT_BITSLIPCNT bit 3!MAIN[19][24]MAIN[19][55]
INIT_CE bit 0!MAIN[20][36]!MAIN[20][43]
INIT_CE bit 1!MAIN[20][33]!MAIN[20][46]
INIT_RANK1_PARTIAL bit 0!MAIN[20][30]!MAIN[20][49]
INIT_RANK1_PARTIAL bit 1!MAIN[20][29]!MAIN[20][50]
INIT_RANK1_PARTIAL bit 2!MAIN[20][37]!MAIN[20][42]
INIT_RANK1_PARTIAL bit 3!MAIN[19][27]!MAIN[19][52]
INIT_RANK1_PARTIAL bit 4!MAIN[19][33]!MAIN[19][46]
INIT_RANK2 bit 0!MAIN[19][11]!MAIN[19][68]
INIT_RANK2 bit 1!MAIN[19][10]!MAIN[19][69]
INIT_RANK2 bit 2!MAIN[19][12]!MAIN[19][67]
INIT_RANK2 bit 3!MAIN[20][10]!MAIN[20][69]
INIT_RANK2 bit 4!MAIN[19][9]!MAIN[19][70]
INIT_RANK2 bit 5!MAIN[19][8]!MAIN[19][71]
INIT_RANK3 bit 0!MAIN[19][21]!MAIN[19][58]
INIT_RANK3 bit 1!MAIN[19][22]!MAIN[19][57]
INIT_RANK3 bit 2!MAIN[19][23]!MAIN[19][56]
INIT_RANK3 bit 3!MAIN[20][21]!MAIN[20][58]
INIT_RANK3 bit 4!MAIN[19][20]!MAIN[19][59]
INIT_RANK3 bit 5!MAIN[19][19]!MAIN[19][60]
I_DELAY_ENABLEMAIN[21][36]MAIN[21][43]
I_DELAY_DEFAULTMAIN[21][35]MAIN[21][44]
I_TSBYPASS_ENABLEMAIN[21][33]MAIN[21][46]
FFI_DELAY_ENABLEMAIN[21][38]MAIN[21][41]
FFI_TSBYPASS_ENABLEMAIN[21][39]MAIN[21][40]
MUX_TSBYPASS[enum: ILOGIC_MUX_TSBYPASS][enum: ILOGIC_MUX_TSBYPASS]
SERDESMAIN[19][30]MAIN[19][49]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_RATE[enum: IO_DATA_RATE][enum: IO_DATA_RATE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
INTERFACE_TYPE[enum: ILOGIC_INTERFACE_TYPE][enum: ILOGIC_INTERFACE_TYPE]
NUM_CE[enum: ILOGIC_NUM_CE][enum: ILOGIC_NUM_CE]
BITSLIP_ENABLE bit 0MAIN[19][0]MAIN[19][61]
BITSLIP_ENABLE bit 1MAIN[19][7]MAIN[19][72]
BITSLIP_ENABLE bit 2MAIN[19][18]MAIN[19][79]
BITSLIP_ENABLE bit 3MAIN[20][7]MAIN[20][59]
BITSLIP_ENABLE bit 4MAIN[20][8]MAIN[20][60]
BITSLIP_ENABLE bit 5MAIN[20][19]MAIN[20][71]
BITSLIP_ENABLE bit 6MAIN[20][20]MAIN[20][72]
BITSLIP_SYNCMAIN[20][2]MAIN[20][77]
DDR_CLK_EDGE[enum: ILOGIC_DDR_CLK_EDGE][enum: ILOGIC_DDR_CLK_EDGE]
IDELAYMUX[enum: ILOGIC_IDELAYMUX][enum: ILOGIC_IDELAYMUX]
IOBDELAY_TYPE[enum: ILOGIC_IOBDELAY_TYPE][enum: ILOGIC_IOBDELAY_TYPE]
IOBDELAY_VALUE_CUR bit 0!MAIN[21][27]!MAIN[21][52]
IOBDELAY_VALUE_CUR bit 1!MAIN[21][23]!MAIN[21][56]
IOBDELAY_VALUE_CUR bit 2!MAIN[21][18]!MAIN[21][61]
IOBDELAY_VALUE_CUR bit 3!MAIN[21][12]!MAIN[21][67]
IOBDELAY_VALUE_CUR bit 4!MAIN[21][8]!MAIN[21][71]
IOBDELAY_VALUE_CUR bit 5!MAIN[21][4]!MAIN[21][75]
IOBDELAY_VALUE_INIT bit 0MAIN[21][24]MAIN[21][55]
IOBDELAY_VALUE_INIT bit 1MAIN[21][20]MAIN[21][59]
IOBDELAY_VALUE_INIT bit 2MAIN[21][15]MAIN[21][64]
IOBDELAY_VALUE_INIT bit 3MAIN[21][10]MAIN[21][69]
IOBDELAY_VALUE_INIT bit 4MAIN[21][5]MAIN[21][74]
IOBDELAY_VALUE_INIT bit 5MAIN[21][1]MAIN[21][78]
READBACK_I bit 0MAIN[21][47]MAIN[21][32]
virtex4 IO enum ILOGIC_MUX_TSBYPASS
ILOGIC[0].MUX_TSBYPASSMAIN[21][37]
ILOGIC[1].MUX_TSBYPASSMAIN[21][42]
GND1
T0
virtex4 IO enum IO_SERDES_MODE
ILOGIC[0].SERDES_MODEMAIN[20][32]
ILOGIC[1].SERDES_MODEMAIN[20][47]
MASTER0
SLAVE1
virtex4 IO enum IO_DATA_RATE
ILOGIC[0].DATA_RATEMAIN[19][1]
ILOGIC[1].DATA_RATEMAIN[19][78]
SDR1
DDR0
virtex4 IO enum IO_DATA_WIDTH
ILOGIC[0].DATA_WIDTHMAIN[19][16]MAIN[19][15]MAIN[20][16]MAIN[20][15]
ILOGIC[1].DATA_WIDTHMAIN[19][63]MAIN[19][64]MAIN[20][63]MAIN[20][64]
NONE0000
_20010
_30011
_40100
_50101
_60110
_70111
_81000
_101010
virtex4 IO enum ILOGIC_INTERFACE_TYPE
ILOGIC[0].INTERFACE_TYPEMAIN[19][32]
ILOGIC[1].INTERFACE_TYPEMAIN[19][47]
MEMORY0
NETWORKING1
virtex4 IO enum ILOGIC_NUM_CE
ILOGIC[0].NUM_CEMAIN[19][35]
ILOGIC[1].NUM_CEMAIN[19][44]
_10
_21
virtex4 IO enum ILOGIC_DDR_CLK_EDGE
ILOGIC[0].DDR_CLK_EDGEMAIN[20][22]MAIN[20][23]
ILOGIC[1].DDR_CLK_EDGEMAIN[20][57]MAIN[20][56]
SAME_EDGE_PIPELINED00
SAME_EDGE10
OPPOSITE_EDGE01
virtex4 IO enum ILOGIC_IDELAYMUX
ILOGIC[0].IDELAYMUXMAIN[21][34]MAIN[21][31]
ILOGIC[1].IDELAYMUXMAIN[21][45]MAIN[21][48]
NONE00
D01
OFB10
virtex4 IO enum ILOGIC_IOBDELAY_TYPE
ILOGIC[0].IOBDELAY_TYPEMAIN[21][28]MAIN[21][22]
ILOGIC[1].IOBDELAY_TYPEMAIN[21][51]MAIN[21][57]
DEFAULT00
FIXED01
VARIABLE11

Bels OLOGIC

virtex4 IO bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinIMUX_SPEC[0]IMUX_SPEC[2]
CLKDIVinIMUX_CLK_OPTINV[1]IMUX_CLK_OPTINV[3]
SRinIMUX_SR_OPTINV[0]IMUX_SR_OPTINV[1]
REVinIMUX_SR_OPTINV[2]IMUX_SR_OPTINV[3]
OCEinIMUX_CE_OPTINV[0]IMUX_CE_OPTINV[1]
TCEinIMUX_CE_OPTINV[2]IMUX_CE_OPTINV[3]
D1inIMUX_IMUX[28] invert by !MAIN[24][23]IMUX_IMUX[25] invert by !MAIN[24][56]
D2inIMUX_IMUX[24] invert by !MAIN[24][17]IMUX_IMUX[31] invert by !MAIN[24][62]
D3inIMUX_IMUX[20] invert by !MAIN[24][21]IMUX_IMUX[27] invert by !MAIN[24][58]
D4inIMUX_IMUX[16] invert by !MAIN[24][19]IMUX_IMUX[23] invert by !MAIN[24][60]
D5inIMUX_IMUX[12] invert by !MAIN[24][18]IMUX_IMUX[19] invert by !MAIN[24][61]
D6inIMUX_IMUX[8] invert by !MAIN[24][16]IMUX_IMUX[15] invert by !MAIN[24][63]
T1inIMUX_IMUX[13] invert by !MAIN[24][4]IMUX_IMUX[9] invert by !MAIN[24][75]
T2inIMUX_IMUX[5] invert by !MAIN[24][6]IMUX_IMUX[1] invert by !MAIN[24][73]
T3inIMUX_IMUX[30] invert by !MAIN[24][8]IMUX_IMUX[26] invert by !MAIN[24][71]
T4inIMUX_IMUX[22] invert by !MAIN[24][13]IMUX_IMUX[18] invert by !MAIN[24][66]
TQoutOUT_SEC_TMIN[1]OUT_SEC_TMIN[3]
virtex4 IO bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
CLK1_INV!MAIN[21][6]!MAIN[21][73]
CLK2_INV!MAIN[21][7]!MAIN[21][72]
FFO_INIT bit 0!MAIN[25][26]!MAIN[25][53]
FFO_RANK1_INIT bit 0!MAIN[24][1]!MAIN[24][78]
FFO_RANK1_INIT bit 1!MAIN[24][3]!MAIN[24][76]
FFO_RANK1_INIT bit 2!MAIN[24][9]!MAIN[24][70]
FFO_RANK1_INIT bit 3!MAIN[24][32]!MAIN[24][47]
FFO_RANK1_INIT bit 4!MAIN[24][36]!MAIN[24][43]
FFO_RANK1_INIT bit 5!MAIN[24][37]!MAIN[24][42]
FFO_RANK2_INIT bit 0!MAIN[25][0]!MAIN[25][79]
FFO_RANK2_INIT bit 1!MAIN[25][4]!MAIN[25][75]
FFO_RANK2_INIT bit 2!MAIN[25][8]!MAIN[25][71]
FFO_RANK2_INIT bit 3!MAIN[25][14]!MAIN[25][65]
FFO_SRVAL bit 0!MAIN[25][33]!MAIN[25][46]
FFO_SRVAL bit 1!MAIN[25][34]!MAIN[25][45]
FFO_SRVAL bit 2!MAIN[25][25]!MAIN[25][54]
FFO_LATCHMAIN[25][32]MAIN[25][47]
FFO_SR_SYNCMAIN[25][38]MAIN[25][41]
FFO_RANK1_SR_SYNCMAIN[24][12]MAIN[24][67]
FFO_RANK2_SR_SYNCMAIN[25][18]MAIN[25][61]
FFO_LOADGEN_SR_SYNCMAIN[24][35]MAIN[24][44]
FFO_SR_ENABLEMAIN[25][35]MAIN[25][44]
FFO_REV_ENABLEMAIN[25][39]MAIN[25][40]
V4_MUX_O[enum: OLOGIC_V4_MUX_O][enum: OLOGIC_V4_MUX_O]
FFT_INIT bit 0!MAIN[24][26]!MAIN[24][53]
FFT_RANK1_INIT bit 0!MAIN[24][0]!MAIN[24][79]
FFT_RANK1_INIT bit 1!MAIN[24][2]!MAIN[24][77]
FFT_RANK1_INIT bit 2!MAIN[24][7]!MAIN[24][72]
FFT_RANK1_INIT bit 3!MAIN[24][15]!MAIN[24][64]
FFT_SRVAL bit 0!MAIN[24][28]!MAIN[24][51]
FFT_SRVAL bit 1!MAIN[24][27]!MAIN[24][52]
FFT_SRVAL bit 2!MAIN[24][25]!MAIN[24][54]
FFT_LATCHMAIN[24][20]MAIN[24][59]
FFT_SR_SYNCMAIN[24][33]MAIN[24][46]
FFT_RANK1_SR_SYNCMAIN[24][5]MAIN[24][74]
FFT_SR_ENABLEMAIN[24][31]MAIN[24][48]
FFT_REV_ENABLEMAIN[24][34]MAIN[24][45]
V4_MUX_T[enum: OLOGIC_V4_MUX_T][enum: OLOGIC_V4_MUX_T]
INIT_LOADCNT bit 0!MAIN[25][24]!MAIN[25][55]
INIT_LOADCNT bit 1!MAIN[25][10]!MAIN[25][69]
INIT_LOADCNT bit 2!MAIN[25][5]!MAIN[25][74]
INIT_LOADCNT bit 3!MAIN[25][1]!MAIN[25][78]
SERDESMAIN[24][38]MAIN[24][41]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH][enum: OLOGIC_TRISTATE_WIDTH]
virtex4 IO enum OLOGIC_V4_MUX_O
OLOGIC[0].V4_MUX_OMAIN[25][28]MAIN[25][27]MAIN[25][31]
OLOGIC[1].V4_MUX_OMAIN[25][51]MAIN[25][52]MAIN[25][48]
NONE000
D1001
FFO1010
FFODDR110
virtex4 IO enum OLOGIC_V4_MUX_T
OLOGIC[0].V4_MUX_TMAIN[24][11]MAIN[24][10]MAIN[24][24]
OLOGIC[1].V4_MUX_TMAIN[24][68]MAIN[24][69]MAIN[24][55]
NONE000
T1001
FFT1010
FFTDDR110
virtex4 IO enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[24][39]
OLOGIC[1].SERDES_MODEMAIN[24][40]
MASTER0
SLAVE1
virtex4 IO enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[25][6]MAIN[25][17]MAIN[25][12]MAIN[25][13]MAIN[25][15]MAIN[25][9]MAIN[25][11]MAIN[25][2]
OLOGIC[1].DATA_WIDTHMAIN[25][73]MAIN[25][62]MAIN[25][67]MAIN[25][66]MAIN[25][64]MAIN[25][70]MAIN[25][68]MAIN[25][77]
NONE00000000
_200000001
_300000010
_400000100
_500001000
_600010000
_700100000
_801000000
_1010000000
virtex4 IO enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[24][29]MAIN[24][30]
OLOGIC[1].TRISTATE_WIDTHMAIN[24][50]MAIN[24][49]
_100
_201
_411

Bels IOB

virtex4 IO bel IOB pins
PinDirectionIOB[0]IOB[1]
virtex4 IO bel IOB attribute bits
AttributeIOB[0]IOB[1]
PULL[enum: IOB_PULL][enum: IOB_PULL]
VREF_SYSMONMAIN[26][39]MAIN[26][40]
VRMAIN[26][38]MAIN[26][41]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
OUTPUT_ENABLE bit 0MAIN[25][21]MAIN[25][58]
OUTPUT_ENABLE bit 1MAIN[26][17]MAIN[26][62]
DCI_MODE[enum: IOB_DCI_MODE][enum: IOB_DCI_MODE]
DCI_MISC bit 0MAIN[26][23]MAIN[26][56]
DCI_MISC bit 1MAIN[26][34]MAIN[26][45]
DCI_TMAIN[26][8]MAIN[26][71]
DCIUPDATEMODE_ASREQUIRED!MAIN[26][14]!MAIN[26][65]
V4_PDRIVE bit 0MAIN[26][25]MAIN[26][54]
V4_PDRIVE bit 1!MAIN[26][27]!MAIN[26][52]
V4_PDRIVE bit 2MAIN[26][29]MAIN[26][50]
V4_PDRIVE bit 3!MAIN[26][31]!MAIN[26][48]
V4_PDRIVE bit 4MAIN[26][33]MAIN[26][46]
V4_NDRIVE bit 0MAIN[26][24]MAIN[26][55]
V4_NDRIVE bit 1!MAIN[26][26]!MAIN[26][53]
V4_NDRIVE bit 2!MAIN[26][28]!MAIN[26][51]
V4_NDRIVE bit 3MAIN[26][30]MAIN[26][49]
V4_NDRIVE bit 4MAIN[26][32]MAIN[26][47]
V4_PSLEW bit 0MAIN[26][0]MAIN[26][79]
V4_PSLEW bit 1MAIN[26][6]MAIN[26][73]
V4_PSLEW bit 2MAIN[26][12]MAIN[26][67]
V4_PSLEW bit 3MAIN[26][18]MAIN[26][61]
V4_NSLEW bit 0MAIN[26][1]MAIN[26][78]
V4_NSLEW bit 1!MAIN[26][7]!MAIN[26][72]
V4_NSLEW bit 2MAIN[26][13]MAIN[26][66]
V4_NSLEW bit 3MAIN[25][19]MAIN[25][60]
V4_OUTPUT_MISC bit 0MAIN[26][19]MAIN[26][60]
V4_OUTPUT_MISC bit 1MAIN[25][20]MAIN[25][59]
V4_LVDS bit 0MAIN[26][9]MAIN[26][70]
V4_LVDS bit 1MAIN[26][22]MAIN[26][57]
V4_LVDS bit 2MAIN[26][20]MAIN[26][59]
V4_LVDS bit 3MAIN[25][22]MAIN[25][57]
virtex4 IO enum IOB_PULL
IOB[0].PULLMAIN[26][16]MAIN[26][15]MAIN[26][21]
IOB[1].PULLMAIN[26][63]MAIN[26][64]MAIN[26][58]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex4 IO enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[26][2]MAIN[26][3]MAIN[26][4]
IOB[1].IBUF_MODEMAIN[26][77]MAIN[26][76]MAIN[26][75]
NONE000
VREF001
DIFF010
CMOS111
virtex4 IO enum IOB_DCI_MODE
IOB[0].DCI_MODEMAIN[26][37]MAIN[26][36]MAIN[26][35]
IOB[1].DCI_MODEMAIN[26][42]MAIN[26][43]MAIN[26][44]
NONE000
OUTPUT001
OUTPUT_HALF010
TERM_VCC011
TERM_SPLIT100

Bel wires

virtex4 IO bel wires
WirePins
IMUX_SR_OPTINV[0]ILOGIC[0].SR, OLOGIC[0].SR
IMUX_SR_OPTINV[1]ILOGIC[1].SR, OLOGIC[1].SR
IMUX_SR_OPTINV[2]ILOGIC[0].REV, OLOGIC[0].REV
IMUX_SR_OPTINV[3]ILOGIC[1].REV, OLOGIC[1].REV
IMUX_CLK_OPTINV[0]ILOGIC[0].CLKDIV
IMUX_CLK_OPTINV[1]OLOGIC[0].CLKDIV
IMUX_CLK_OPTINV[2]ILOGIC[1].CLKDIV
IMUX_CLK_OPTINV[3]OLOGIC[1].CLKDIV
IMUX_CE_OPTINV[0]OLOGIC[0].OCE
IMUX_CE_OPTINV[1]OLOGIC[1].OCE
IMUX_CE_OPTINV[2]OLOGIC[0].TCE
IMUX_CE_OPTINV[3]OLOGIC[1].TCE
IMUX_IMUX[0]ILOGIC[0].DLYCE
IMUX_IMUX[1]OLOGIC[1].T2
IMUX_IMUX[2]ILOGIC[1].CE1
IMUX_IMUX[3]ILOGIC[1].DLYINC
IMUX_IMUX[4]ILOGIC[0].DLYRST
IMUX_IMUX[5]OLOGIC[0].T2
IMUX_IMUX[6]ILOGIC[0].CE1
IMUX_IMUX[7]ILOGIC[1].DLYCE
IMUX_IMUX[8]OLOGIC[0].D6
IMUX_IMUX[9]OLOGIC[1].T1
IMUX_IMUX[10]ILOGIC[1].CE2
IMUX_IMUX[11]ILOGIC[1].DLYRST
IMUX_IMUX[12]OLOGIC[0].D5
IMUX_IMUX[13]OLOGIC[0].T1
IMUX_IMUX[14]ILOGIC[0].CE2
IMUX_IMUX[15]OLOGIC[1].D6
IMUX_IMUX[16]OLOGIC[0].D4
IMUX_IMUX[17]ILOGIC[1].BITSLIP
IMUX_IMUX[18]OLOGIC[1].T4
IMUX_IMUX[19]OLOGIC[1].D5
IMUX_IMUX[20]OLOGIC[0].D3
IMUX_IMUX[21]ILOGIC[0].BITSLIP
IMUX_IMUX[22]OLOGIC[0].T4
IMUX_IMUX[23]OLOGIC[1].D4
IMUX_IMUX[24]OLOGIC[0].D2
IMUX_IMUX[25]OLOGIC[1].D1
IMUX_IMUX[26]OLOGIC[1].T3
IMUX_IMUX[27]OLOGIC[1].D3
IMUX_IMUX[28]OLOGIC[0].D1
IMUX_IMUX[29]ILOGIC[0].DLYINC
IMUX_IMUX[30]OLOGIC[0].T3
IMUX_IMUX[31]OLOGIC[1].D2
OUT_BEST_TMIN[0]ILOGIC[1].O
OUT_BEST_TMIN[1]ILOGIC[1].Q2
OUT_BEST_TMIN[2]ILOGIC[0].O
OUT_BEST_TMIN[3]ILOGIC[0].Q2
OUT_BEST_TMIN[4]ILOGIC[0].Q1
OUT_BEST_TMIN[5]ILOGIC[0].Q3
OUT_BEST_TMIN[6]ILOGIC[1].Q1
OUT_BEST_TMIN[7]ILOGIC[1].Q3
OUT_SEC_TMIN[0]ILOGIC[0].Q4
OUT_SEC_TMIN[1]OLOGIC[0].TQ
OUT_SEC_TMIN[2]ILOGIC[1].Q4
OUT_SEC_TMIN[3]OLOGIC[1].TQ
OUT_SEC_TMIN[4]ILOGIC[0].Q5
OUT_SEC_TMIN[5]ILOGIC[0].Q6
OUT_SEC_TMIN[6]ILOGIC[1].Q6
OUT_SEC_TMIN[7]ILOGIC[1].Q5
IMUX_SPEC[0]OLOGIC[0].CLK
IMUX_SPEC[1]ILOGIC[0].CLK
IMUX_SPEC[2]OLOGIC[1].CLK
IMUX_SPEC[3]ILOGIC[1].CLK
OUT_CLKPADILOGIC[1].CLKPAD

Bitstream

virtex4 IO rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B79 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_ENABLE bit 2 - - - - OLOGIC[1]: ! FFT_RANK1_INIT bit 0 OLOGIC[1]: ! FFO_RANK2_INIT bit 0 IOB[1]: V4_PSLEW bit 0 - - -
B78 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DATA_RATE bit 0 - ILOGIC[1]: IOBDELAY_VALUE_INIT bit 5 - - OLOGIC[1]: ! FFO_RANK1_INIT bit 0 OLOGIC[1]: ! INIT_LOADCNT bit 3 IOB[1]: V4_NSLEW bit 0 - - -
B77 - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_SYNC - - - OLOGIC[1]: ! FFT_RANK1_INIT bit 1 OLOGIC[1]: DATA_WIDTH bit 0 IOB[1]: IBUF_MODE bit 2 - - -
B76 - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_RANK1_INIT bit 1 - IOB[1]: IBUF_MODE bit 1 - - -
B75 - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 5 - - OLOGIC[1]: !invert T1 OLOGIC[1]: ! FFO_RANK2_INIT bit 1 IOB[1]: IBUF_MODE bit 0 - - -
B74 - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: IOBDELAY_VALUE_INIT bit 4 - - OLOGIC[1]: FFT_RANK1_SR_SYNC OLOGIC[1]: ! INIT_LOADCNT bit 2 - - - -
B73 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: INIT_BITSLIPCNT bit 0 - OLOGIC[1]: ! CLK1_INV - - OLOGIC[1]: !invert T2 OLOGIC[1]: DATA_WIDTH bit 7 IOB[1]: V4_PSLEW bit 1 - - -
B72 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_ENABLE bit 1 ILOGIC[1]: BITSLIP_ENABLE bit 6 OLOGIC[1]: ! CLK2_INV - - OLOGIC[1]: ! FFT_RANK1_INIT bit 2 - IOB[1]: ! V4_NSLEW bit 1 - - -
B71 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 5 ILOGIC[1]: BITSLIP_ENABLE bit 5 ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 4 - - OLOGIC[1]: !invert T3 OLOGIC[1]: ! FFO_RANK2_INIT bit 2 IOB[1]: DCI_T - - -
B70 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 4 - - - - OLOGIC[1]: ! FFO_RANK1_INIT bit 2 OLOGIC[1]: DATA_WIDTH bit 2 IOB[1]: V4_LVDS bit 0 - - -
B69 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 1 ILOGIC[1]: ! INIT_RANK2 bit 3 ILOGIC[1]: IOBDELAY_VALUE_INIT bit 3 - - OLOGIC[1]: V4_MUX_T bit 1 OLOGIC[1]: ! INIT_LOADCNT bit 1 - - - -
B68 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 0 - - - - OLOGIC[1]: V4_MUX_T bit 2 OLOGIC[1]: DATA_WIDTH bit 1 - - - -
B67 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 2 - ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 3 - - OLOGIC[1]: FFO_RANK1_SR_SYNC OLOGIC[1]: DATA_WIDTH bit 5 IOB[1]: V4_PSLEW bit 2 - - -
B66 - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: !invert T4 OLOGIC[1]: DATA_WIDTH bit 4 IOB[1]: V4_NSLEW bit 2 - - -
B65 - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: ! FFO_RANK2_INIT bit 3 IOB[1]: ! DCIUPDATEMODE_ASREQUIRED - - -
B64 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DATA_WIDTH bit 2 ILOGIC[1]: DATA_WIDTH bit 0 ILOGIC[1]: IOBDELAY_VALUE_INIT bit 2 - - OLOGIC[1]: ! FFT_RANK1_INIT bit 3 OLOGIC[1]: DATA_WIDTH bit 3 IOB[1]: PULL bit 1 - - -
B63 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DATA_WIDTH bit 3 ILOGIC[1]: DATA_WIDTH bit 1 - - - OLOGIC[1]: !invert D6 - IOB[1]: PULL bit 2 - - -
B62 - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: invert SR - - - OLOGIC[1]: !invert D2 OLOGIC[1]: DATA_WIDTH bit 6 IOB[1]: OUTPUT_ENABLE bit 1 - - -
B61 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_ENABLE bit 0 ILOGIC[1]: INIT_BITSLIPCNT bit 1 ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 2 - - OLOGIC[1]: !invert D5 OLOGIC[1]: FFO_RANK2_SR_SYNC IOB[1]: V4_PSLEW bit 3 - - -
B60 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 5 ILOGIC[1]: BITSLIP_ENABLE bit 4 - - - OLOGIC[1]: !invert D4 IOB[1]: V4_NSLEW bit 3 IOB[1]: V4_OUTPUT_MISC bit 0 - - -
B59 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 4 ILOGIC[1]: BITSLIP_ENABLE bit 3 ILOGIC[1]: IOBDELAY_VALUE_INIT bit 1 - - OLOGIC[1]: FFT_LATCH IOB[1]: V4_OUTPUT_MISC bit 1 IOB[1]: V4_LVDS bit 2 - - -
B58 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 0 ILOGIC[1]: ! INIT_RANK3 bit 3 - - - OLOGIC[1]: !invert D3 IOB[1]: OUTPUT_ENABLE bit 0 IOB[1]: PULL bit 0 - - -
B57 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 1 ILOGIC[1]: DDR_CLK_EDGE bit 1 ILOGIC[1]: IOBDELAY_TYPE bit 0 - - - IOB[1]: V4_LVDS bit 3 IOB[1]: V4_LVDS bit 1 - - -
B56 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 2 ILOGIC[1]: DDR_CLK_EDGE bit 0 ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 1 - - OLOGIC[1]: !invert D1 - IOB[1]: DCI_MISC bit 0 - - -
B55 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: INIT_BITSLIPCNT bit 3 ILOGIC[1]: INIT_BITSLIPCNT bit 2 ILOGIC[1]: IOBDELAY_VALUE_INIT bit 0 - - OLOGIC[1]: V4_MUX_T bit 0 OLOGIC[1]: ! INIT_LOADCNT bit 0 IOB[1]: V4_NDRIVE bit 0 - - -
B54 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: OCLK2_INV ILOGIC[1]: ! CLK_INV bit 2 - - - OLOGIC[1]: ! FFT_SRVAL bit 2 OLOGIC[1]: ! FFO_SRVAL bit 2 IOB[1]: V4_PDRIVE bit 0 - - -
B53 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! CLK_INV bit 0 ILOGIC[1]: OCLK1_INV - - - OLOGIC[1]: ! FFT_INIT bit 0 OLOGIC[1]: ! FFO_INIT bit 0 IOB[1]: ! V4_NDRIVE bit 1 - - -
B52 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 3 ILOGIC[1]: ! FFI1_SRVAL bit 0 ILOGIC[1]: ! IOBDELAY_VALUE_CUR bit 0 - - OLOGIC[1]: ! FFT_SRVAL bit 1 OLOGIC[1]: V4_MUX_O bit 1 IOB[1]: ! V4_PDRIVE bit 1 - - -
B51 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI2_INIT bit 0 ILOGIC[1]: ! FFI4_SRVAL bit 0 ILOGIC[1]: IOBDELAY_TYPE bit 1 - - OLOGIC[1]: ! FFT_SRVAL bit 0 OLOGIC[1]: V4_MUX_O bit 2 IOB[1]: ! V4_NDRIVE bit 2 - - -
B50 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI3_INIT bit 0 ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 1 - SPEC_INT: mux IMUX_SPEC[2] bit 8 - OLOGIC[1]: TRISTATE_WIDTH bit 1 - IOB[1]: V4_PDRIVE bit 2 - - -
B49 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: SERDES ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 0 ILOGIC[1]: FFI_ENABLE SPEC_INT: mux IMUX_SPEC[3] bit 4 SPEC_INT: mux IMUX_SPEC[3] bit 1 OLOGIC[1]: TRISTATE_WIDTH bit 0 - IOB[1]: V4_NDRIVE bit 3 - - -
B48 - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! CLK_INV bit 1 ILOGIC[1]: IDELAYMUX bit 0 SPEC_INT: mux IMUX_SPEC[3] bit 3 SPEC_INT: mux IMUX_SPEC[3] bit 2 OLOGIC[1]: FFT_SR_ENABLE OLOGIC[1]: V4_MUX_O bit 0 IOB[1]: ! V4_PDRIVE bit 3 - - -
B47 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: INTERFACE_TYPE bit 0 ILOGIC[1]: SERDES_MODE bit 0 ILOGIC[0]: READBACK_I bit 0 SPEC_INT: mux IMUX_SPEC[2] bit 5 SPEC_INT: mux IMUX_SPEC[3] bit 0 OLOGIC[1]: ! FFO_RANK1_INIT bit 3 OLOGIC[1]: FFO_LATCH IOB[1]: V4_NDRIVE bit 4 - - -
B46 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 4 ILOGIC[1]: ! INIT_CE bit 1 ILOGIC[1]: I_TSBYPASS_ENABLE SPEC_INT: mux IMUX_SPEC[2] bit 6 SPEC_INT: mux IMUX_SPEC[3] bit 5 OLOGIC[1]: FFT_SR_SYNC OLOGIC[1]: ! FFO_SRVAL bit 0 IOB[1]: V4_PDRIVE bit 4 - - -
B45 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: invert REV ILOGIC[1]: ! FFI1_INIT bit 0 ILOGIC[1]: IDELAYMUX bit 1 SPEC_INT: mux IMUX_SPEC[2] bit 7 SPEC_INT: mux IMUX_SPEC[3] bit 6 OLOGIC[1]: FFT_REV_ENABLE OLOGIC[1]: ! FFO_SRVAL bit 1 IOB[1]: DCI_MISC bit 1 - - -
B44 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: NUM_CE bit 0 ILOGIC[1]: ! FFI4_INIT bit 0 ILOGIC[1]: I_DELAY_DEFAULT SPEC_INT: mux IMUX_SPEC[3] bit 8 SPEC_INT: mux IMUX_SPEC[3] bit 7 OLOGIC[1]: FFO_LOADGEN_SR_SYNC OLOGIC[1]: FFO_SR_ENABLE IOB[1]: DCI_MODE bit 0 - - -
B43 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_LATCH ILOGIC[1]: ! INIT_CE bit 0 ILOGIC[1]: I_DELAY_ENABLE SPEC_INT: mux IMUX_SPEC[2] bit 3 SPEC_INT: mux IMUX_SPEC[2] bit 0 OLOGIC[1]: ! FFO_RANK1_INIT bit 4 - IOB[1]: DCI_MODE bit 1 - - -
B42 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI_SR_SYNC ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 2 ILOGIC[1]: MUX_TSBYPASS bit 0 SPEC_INT: mux IMUX_SPEC[2] bit 4 SPEC_INT: mux IMUX_SPEC[2] bit 1 OLOGIC[1]: ! FFO_RANK1_INIT bit 5 - IOB[1]: DCI_MODE bit 2 - - -
B41 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: !invert CE2 ILOGIC[1]: ! FFI2_SRVAL bit 0 ILOGIC[1]: FFI_DELAY_ENABLE - SPEC_INT: mux IMUX_SPEC[2] bit 2 OLOGIC[1]: SERDES OLOGIC[1]: FFO_SR_SYNC IOB[1]: VR - - -
B40 - - - - - - - - - - - - - - - - - - - ILOGIC[1]: !invert CE1 ILOGIC[1]: ! FFI3_SRVAL bit 0 ILOGIC[1]: FFI_TSBYPASS_ENABLE - - OLOGIC[1]: SERDES_MODE bit 0 OLOGIC[1]: FFO_REV_ENABLE IOB[1]: VREF_SYSMON - - -
B39 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: !invert CE1 ILOGIC[0]: ! FFI3_SRVAL bit 0 ILOGIC[0]: FFI_TSBYPASS_ENABLE - - OLOGIC[0]: SERDES_MODE bit 0 OLOGIC[0]: FFO_REV_ENABLE IOB[0]: VREF_SYSMON - - -
B38 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: !invert CE2 ILOGIC[0]: ! FFI2_SRVAL bit 0 ILOGIC[0]: FFI_DELAY_ENABLE - SPEC_INT: mux IMUX_SPEC[0] bit 2 OLOGIC[0]: SERDES OLOGIC[0]: FFO_SR_SYNC IOB[0]: VR - - -
B37 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_SR_SYNC ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 2 ILOGIC[0]: MUX_TSBYPASS bit 0 SPEC_INT: mux IMUX_SPEC[0] bit 4 SPEC_INT: mux IMUX_SPEC[0] bit 1 OLOGIC[0]: ! FFO_RANK1_INIT bit 5 - IOB[0]: DCI_MODE bit 2 - - -
B36 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI_LATCH ILOGIC[0]: ! INIT_CE bit 0 ILOGIC[0]: I_DELAY_ENABLE SPEC_INT: mux IMUX_SPEC[0] bit 3 SPEC_INT: mux IMUX_SPEC[0] bit 0 OLOGIC[0]: ! FFO_RANK1_INIT bit 4 - IOB[0]: DCI_MODE bit 1 - - -
B35 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: NUM_CE bit 0 ILOGIC[0]: ! FFI4_INIT bit 0 ILOGIC[0]: I_DELAY_DEFAULT SPEC_INT: mux IMUX_SPEC[1] bit 8 SPEC_INT: mux IMUX_SPEC[1] bit 7 OLOGIC[0]: FFO_LOADGEN_SR_SYNC OLOGIC[0]: FFO_SR_ENABLE IOB[0]: DCI_MODE bit 0 - - -
B34 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: invert REV ILOGIC[0]: ! FFI1_INIT bit 0 ILOGIC[0]: IDELAYMUX bit 1 SPEC_INT: mux IMUX_SPEC[0] bit 7 SPEC_INT: mux IMUX_SPEC[1] bit 6 OLOGIC[0]: FFT_REV_ENABLE OLOGIC[0]: ! FFO_SRVAL bit 1 IOB[0]: DCI_MISC bit 1 - - -
B33 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 4 ILOGIC[0]: ! INIT_CE bit 1 ILOGIC[0]: I_TSBYPASS_ENABLE SPEC_INT: mux IMUX_SPEC[0] bit 6 SPEC_INT: mux IMUX_SPEC[1] bit 5 OLOGIC[0]: FFT_SR_SYNC OLOGIC[0]: ! FFO_SRVAL bit 0 IOB[0]: V4_PDRIVE bit 4 - - -
B32 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: INTERFACE_TYPE bit 0 ILOGIC[0]: SERDES_MODE bit 0 ILOGIC[1]: READBACK_I bit 0 SPEC_INT: mux IMUX_SPEC[0] bit 5 SPEC_INT: mux IMUX_SPEC[1] bit 0 OLOGIC[0]: ! FFO_RANK1_INIT bit 3 OLOGIC[0]: FFO_LATCH IOB[0]: V4_NDRIVE bit 4 - - -
B31 - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! CLK_INV bit 2 ILOGIC[0]: IDELAYMUX bit 0 SPEC_INT: mux IMUX_SPEC[1] bit 3 SPEC_INT: mux IMUX_SPEC[1] bit 2 OLOGIC[0]: FFT_SR_ENABLE OLOGIC[0]: V4_MUX_O bit 0 IOB[0]: ! V4_PDRIVE bit 3 - - -
B30 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: SERDES ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 0 ILOGIC[0]: FFI_ENABLE SPEC_INT: mux IMUX_SPEC[1] bit 4 SPEC_INT: mux IMUX_SPEC[1] bit 1 OLOGIC[0]: TRISTATE_WIDTH bit 0 - IOB[0]: V4_NDRIVE bit 3 - - -
B29 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI3_INIT bit 0 ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 1 - SPEC_INT: mux IMUX_SPEC[0] bit 8 - OLOGIC[0]: TRISTATE_WIDTH bit 1 - IOB[0]: V4_PDRIVE bit 2 - - -
B28 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI2_INIT bit 0 ILOGIC[0]: ! FFI4_SRVAL bit 0 ILOGIC[0]: IOBDELAY_TYPE bit 1 - - OLOGIC[0]: ! FFT_SRVAL bit 0 OLOGIC[0]: V4_MUX_O bit 2 IOB[0]: ! V4_NDRIVE bit 2 - - -
B27 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 3 ILOGIC[0]: ! FFI1_SRVAL bit 0 ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 0 - - OLOGIC[0]: ! FFT_SRVAL bit 1 OLOGIC[0]: V4_MUX_O bit 1 IOB[0]: ! V4_PDRIVE bit 1 - - -
B26 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! CLK_INV bit 0 ILOGIC[0]: OCLK1_INV - - - OLOGIC[0]: ! FFT_INIT bit 0 OLOGIC[0]: ! FFO_INIT bit 0 IOB[0]: ! V4_NDRIVE bit 1 - - -
B25 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: OCLK2_INV ILOGIC[0]: ! CLK_INV bit 1 - - - OLOGIC[0]: ! FFT_SRVAL bit 2 OLOGIC[0]: ! FFO_SRVAL bit 2 IOB[0]: V4_PDRIVE bit 0 - - -
B24 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_BITSLIPCNT bit 3 ILOGIC[0]: ! INIT_BITSLIPCNT bit 2 ILOGIC[0]: IOBDELAY_VALUE_INIT bit 0 - - OLOGIC[0]: V4_MUX_T bit 0 OLOGIC[0]: ! INIT_LOADCNT bit 0 IOB[0]: V4_NDRIVE bit 0 - - -
B23 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 2 ILOGIC[0]: DDR_CLK_EDGE bit 0 ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 1 - - OLOGIC[0]: !invert D1 - IOB[0]: DCI_MISC bit 0 - - -
B22 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 1 ILOGIC[0]: DDR_CLK_EDGE bit 1 ILOGIC[0]: IOBDELAY_TYPE bit 0 - - - IOB[0]: V4_LVDS bit 3 IOB[0]: V4_LVDS bit 1 - - -
B21 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 0 ILOGIC[0]: ! INIT_RANK3 bit 3 - - - OLOGIC[0]: !invert D3 IOB[0]: OUTPUT_ENABLE bit 0 IOB[0]: PULL bit 0 - - -
B20 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 4 ILOGIC[0]: BITSLIP_ENABLE bit 6 ILOGIC[0]: IOBDELAY_VALUE_INIT bit 1 - - OLOGIC[0]: FFT_LATCH IOB[0]: V4_OUTPUT_MISC bit 1 IOB[0]: V4_LVDS bit 2 - - -
B19 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 5 ILOGIC[0]: BITSLIP_ENABLE bit 5 - - - OLOGIC[0]: !invert D4 IOB[0]: V4_NSLEW bit 3 IOB[0]: V4_OUTPUT_MISC bit 0 - - -
B18 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_ENABLE bit 2 ILOGIC[0]: ! INIT_BITSLIPCNT bit 1 ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 2 - - OLOGIC[0]: !invert D5 OLOGIC[0]: FFO_RANK2_SR_SYNC IOB[0]: V4_PSLEW bit 3 - - -
B17 - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: invert SR - - - OLOGIC[0]: !invert D2 OLOGIC[0]: DATA_WIDTH bit 6 IOB[0]: OUTPUT_ENABLE bit 1 - - -
B16 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DATA_WIDTH bit 3 ILOGIC[0]: DATA_WIDTH bit 1 - - - OLOGIC[0]: !invert D6 - IOB[0]: PULL bit 2 - - -
B15 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DATA_WIDTH bit 2 ILOGIC[0]: DATA_WIDTH bit 0 ILOGIC[0]: IOBDELAY_VALUE_INIT bit 2 - - OLOGIC[0]: ! FFT_RANK1_INIT bit 3 OLOGIC[0]: DATA_WIDTH bit 3 IOB[0]: PULL bit 1 - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_RANK2_INIT bit 3 IOB[0]: ! DCIUPDATEMODE_ASREQUIRED - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: !invert T4 OLOGIC[0]: DATA_WIDTH bit 4 IOB[0]: V4_NSLEW bit 2 - - -
B12 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 2 - ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 3 - - OLOGIC[0]: FFO_RANK1_SR_SYNC OLOGIC[0]: DATA_WIDTH bit 5 IOB[0]: V4_PSLEW bit 2 - - -
B11 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 0 - - - - OLOGIC[0]: V4_MUX_T bit 2 OLOGIC[0]: DATA_WIDTH bit 1 - - - -
B10 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 1 ILOGIC[0]: ! INIT_RANK2 bit 3 ILOGIC[0]: IOBDELAY_VALUE_INIT bit 3 - - OLOGIC[0]: V4_MUX_T bit 1 OLOGIC[0]: ! INIT_LOADCNT bit 1 - - - -
B9 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 4 - - - - OLOGIC[0]: ! FFO_RANK1_INIT bit 2 OLOGIC[0]: DATA_WIDTH bit 2 IOB[0]: V4_LVDS bit 0 - - -
B8 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 5 ILOGIC[0]: BITSLIP_ENABLE bit 4 ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 4 - - OLOGIC[0]: !invert T3 OLOGIC[0]: ! FFO_RANK2_INIT bit 2 IOB[0]: DCI_T - - -
B7 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_ENABLE bit 1 ILOGIC[0]: BITSLIP_ENABLE bit 3 OLOGIC[0]: ! CLK2_INV - - OLOGIC[0]: ! FFT_RANK1_INIT bit 2 - IOB[0]: ! V4_NSLEW bit 1 - - -
B6 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_BITSLIPCNT bit 0 - OLOGIC[0]: ! CLK1_INV - - OLOGIC[0]: !invert T2 OLOGIC[0]: DATA_WIDTH bit 7 IOB[0]: V4_PSLEW bit 1 - - -
B5 - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: IOBDELAY_VALUE_INIT bit 4 - - OLOGIC[0]: FFT_RANK1_SR_SYNC OLOGIC[0]: ! INIT_LOADCNT bit 2 - - - -
B4 - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! IOBDELAY_VALUE_CUR bit 5 - - OLOGIC[0]: !invert T1 OLOGIC[0]: ! FFO_RANK2_INIT bit 1 IOB[0]: IBUF_MODE bit 0 - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: ! FFO_RANK1_INIT bit 1 - IOB[0]: IBUF_MODE bit 1 - - -
B2 - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_SYNC - - - OLOGIC[0]: ! FFT_RANK1_INIT bit 1 OLOGIC[0]: DATA_WIDTH bit 0 IOB[0]: IBUF_MODE bit 2 - - -
B1 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DATA_RATE bit 0 - ILOGIC[0]: IOBDELAY_VALUE_INIT bit 5 - - OLOGIC[0]: ! FFO_RANK1_INIT bit 0 OLOGIC[0]: ! INIT_LOADCNT bit 3 IOB[0]: V4_NSLEW bit 0 - - -
B0 - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_ENABLE bit 0 - - - - OLOGIC[0]: ! FFT_RANK1_INIT bit 0 OLOGIC[0]: ! FFO_RANK2_INIT bit 0 IOB[0]: V4_PSLEW bit 0 - - -

Tables

Table IOB_DATA

virtex4 table IOB_DATA
Row PDRIVE NDRIVE OUTPUT_MISC PSLEW_FAST NSLEW_FAST PSLEW_SLOW NSLEW_SLOW PMASK_TERM_VCC PMASK_TERM_SPLIT NMASK_TERM_SPLIT LVDIV2
OFF 0b00000 0b00000 0b00 0b0000 0b0010 - - 0b00000 0b00000 0b00000 0b00
VREF 0b01101 0b00000 - 0b0000 0b0000 - - - - - -
VR 0b00000 0b00000 - 0b0111 0b0111 - - - - - -
LVCMOS12_2 - - - - - - - - - - -
LVCMOS12_4 - - - - - - - - - - -
LVCMOS12_6 - - - - - - - - - - -
LVCMOS12_8 - - - - - - - - - - -
LVCMOS15_2 0b00011 0b00001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS15_4 0b00110 0b00010 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS15_6 0b01000 0b00011 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS15_8 0b01100 0b00100 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS15_12 0b10011 0b00110 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS15_16 0b11000 0b01001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS18_2 0b00011 0b00001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS18_4 0b00101 0b00010 0b00 0b0111 0b1111 0b0001 0b0001 - - - -
LVCMOS18_6 0b00111 0b00011 0b00 0b0111 0b1111 0b0001 0b0001 - - - -
LVCMOS18_8 0b01001 0b00100 0b00 0b0111 0b1111 0b0000 0b0010 - - - -
LVCMOS18_12 0b01110 0b00110 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS18_16 0b10100 0b01001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS25_2 0b00010 0b00001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS25_4 0b00100 0b00010 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS25_6 0b00101 0b00011 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS25_8 0b00111 0b00101 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS25_12 0b01010 0b00110 0b00 0b0111 0b1111 0b0000 0b0010 - - - -
LVCMOS25_16 0b01101 0b01001 0b00 0b0111 0b1111 0b0000 0b0010 - - - -
LVCMOS25_24 0b10111 0b01110 0b00 0b0111 0b1111 0b0001 0b0011 - - - -
LVCMOS33_2 0b00001 0b00001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS33_4 0b00011 0b00010 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS33_6 0b00100 0b00011 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS33_8 0b00101 0b00100 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS33_12 0b01000 0b00111 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVCMOS33_16 0b01010 0b01001 0b00 0b1111 0b0111 0b0000 0b0010 - - - -
LVCMOS33_24 0b10011 0b01110 0b00 0b0111 0b1111 0b0001 0b0010 - - - -
LVTTL_2 0b00001 0b00001 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVTTL_4 0b00011 0b00010 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVTTL_6 0b00100 0b00011 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVTTL_8 0b00101 0b00100 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVTTL_12 0b01000 0b00111 0b00 0b0111 0b1111 0b0000 0b0001 - - - -
LVTTL_16 0b01010 0b01001 0b00 0b1111 0b0111 0b0000 0b0010 - - - -
LVTTL_24 0b10011 0b01110 0b00 0b0111 0b1111 0b0001 0b0010 - - - -
PCI33_3 0b01001 0b01101 0b10 0b0001 0b0011 - - - - - -
PCI66_3 0b01001 0b01101 0b10 0b0001 0b0011 - - - - - -
PCIX 0b01100 0b01100 0b00 0b0111 0b1011 - - - - - -
LVDCI_15 - - 0b00 0b1110 0b1001 - - - - - -
LVDCI_18 - - 0b00 0b0001 0b1100 - - - - - -
LVDCI_25 - - 0b00 0b0000 0b1001 - - - - - -
LVDCI_33 - - 0b00 0b0000 0b1111 - - - - - -
LVDCI_DV2_15 - - 0b00 0b0011 0b0111 - - - - - 0b00
LVDCI_DV2_18 - - 0b00 0b0001 0b0111 - - - - - 0b10
LVDCI_DV2_25 - - 0b00 0b0001 0b1111 - - - - - 0b01
HSLVDCI_15 - - 0b00 0b1110 0b1001 - - - - - -
HSLVDCI_18 - - 0b00 0b0001 0b1100 - - - - - -
HSLVDCI_25 - - 0b00 0b0000 0b1001 - - - - - -
HSLVDCI_33 - - 0b00 0b0000 0b1111 - - - - - -
HSUL_12_DCI - - - - - - - - - - -
GTL 0b00000 0b10010 0b01 0b0000 0b1010 - - - - - -
GTLP 0b00000 0b10000 0b10 0b0000 0b1100 - - - - - -
SSTL12 - - - - - - - - - - -
SSTL135 - - - - - - - - - - -
SSTL15 - - - - - - - - - - -
SSTL18_I 0b01000 0b00100 0b01 0b0100 0b0110 - - - - - -
SSTL18_II 0b11001 0b01011 0b01 0b0100 0b0100 - - - - - -
SSTL2_I 0b00110 0b00100 0b01 0b0011 0b0111 - - - - - -
SSTL2_II 0b10011 0b01010 0b10 0b0011 0b1000 - - - - - -
HSUL_12 - - - - - - - - - - -
HSTL_I_12 0b10101 0b00100 0b00 0b0111 0b0100 - - - - - -
HSTL_I 0b01101 0b00101 0b01 0b1111 0b1001 - - - - - -
HSTL_II 0b11010 0b01001 0b00 0b1011 0b0100 - - - - - -
HSTL_III 0b01101 0b01111 0b01 0b0011 0b0110 - - - - - -
HSTL_IV 0b01101 0b11110 0b01 0b0011 0b1010 - - - - - -
HSTL_I_18 0b01100 0b00110 0b01 0b0111 0b1001 - - - - - -
HSTL_II_18 0b11011 0b01101 0b01 0b0011 0b0110 - - - - - -
HSTL_III_18 0b01100 0b10001 0b00 0b1000 0b0110 - - - - - -
HSTL_IV_18 0b01100 0b11111 0b10 0b0011 0b1000 - - - - - -
GTL_DCI 0b00000 0b10010 0b01 0b0000 0b1110 - - 0b00000 - - -
GTLP_DCI 0b00000 0b10000 0b00 0b0000 0b1111 - - 0b00000 - - -
SSTL12_DCI - - - - - - - - - - -
SSTL12_T_DCI - - - - - - - - - - -
SSTL135_DCI - - - - - - - - - - -
SSTL135_T_DCI - - - - - - - - - - -
SSTL15_DCI - - - - - - - - - - -
SSTL15_T_DCI - - - - - - - - - - -
SSTL18_I_DCI 0b00111 0b00011 0b00 0b0011 0b0100 - - - 0b00000 0b00000 -
SSTL18_II_DCI 0b01101 0b00110 0b00 0b0011 0b0100 - - - 0b00100 0b01100 -
SSTL18_II_T_DCI 0b00111 0b00011 0b00 0b0011 0b0100 - - - 0b01100 0b01000 -
SSTL2_I_DCI 0b00101 0b00011 0b00 0b0010 0b0110 - - - 0b00000 0b00000 -
SSTL2_II_DCI 0b01000 0b00110 0b00 0b0010 0b0101 - - - 0b00000 0b01100 -
SSTL2_II_T_DCI 0b00101 0b00011 0b00 0b0010 0b0110 - - - 0b00100 0b01000 -
HSTL_I_DCI 0b01101 0b00101 0b01 0b1111 0b1001 - - - 0b00000 0b00000 -
HSTL_II_DCI 0b11010 0b01001 0b00 0b0111 0b0110 - - - 0b01001 0b00010 -
HSTL_II_T_DCI 0b01101 0b00101 0b01 0b1111 0b1001 - - - 0b00100 0b00100 -
HSTL_III_DCI 0b01101 0b01111 0b01 0b0011 0b0110 - - 0b00000 - - -
HSTL_IV_DCI 0b01101 0b11110 0b01 0b0011 0b1000 - - 0b00100 - - -
HSTL_I_DCI_18 0b01100 0b00110 0b01 0b0111 0b1001 - - - 0b00000 0b00000 -
HSTL_II_DCI_18 0b11011 0b01101 0b01 0b0011 0b0110 - - - 0b01001 0b00110 -
HSTL_II_T_DCI_18 0b01100 0b00110 0b01 0b0111 0b1001 - - - 0b00100 0b01100 -
HSTL_III_DCI_18 0b01100 0b10001 0b00 0b1000 0b0110 - - 0b00000 - - -
HSTL_IV_DCI_18 0b01100 0b11111 0b10 0b0011 0b1000 - - 0b00100 - - -
BLVDS_25 0b11111 0b11100 0b00 0b0100 0b1010 - - - - - -
LVPECL_25 0b11000 0b11110 0b00 0b0110 0b1010 - - - - - -
LVDS_25_DCI - - - - - - - - 0b00000 0b00000 -
LVDSEXT_25_DCI - - - - - - - - 0b00000 0b00000 -

Table LVDS_DATA

virtex4 table LVDS_DATA
Row OUTPUT_T OUTPUT_C TERM_T TERM_C LVDSBIAS
OFF 0b0000 0b0000 - - 0b0000000000
LVDS_25 0b0110 0b1010 0b0011 0b1010 0b0001000111
LVDSEXT_25 0b1110 0b0010 0b0011 0b1010 0b0001000111
MINI_LVDS_25 0b0110 0b0110 0b0011 0b0010 0b0001000111
RSDS_25 0b0110 0b1010 0b0011 0b1010 0b0001000111
HT_25 0b0110 0b0110 0b0011 0b0010 0b0001000111
LVDS_25_DCI 0b0100 0b0000 - - 0b0001000111
LVDSEXT_25_DCI 0b1100 0b0000 - - 0b0001000111