Multi-gigabit transceivers

TODO: document

Tile MGT

Cells: 32

Bel GT11_0

virtex4 MGT bel GT11_0
Pin	Direction	Wires
CDRSTATUS0	output	TCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN
CDRSTATUS1	output	TCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN
CDRSTATUS10	output	TCELL3:OUT.HALF.BOT7.TMIN, TCELL3:OUT.HALT.TOP7.TMIN
CDRSTATUS11	output	TCELL4:OUT.HALF.BOT4.TMIN, TCELL4:OUT.HALT.TOP4.TMIN
CDRSTATUS12	output	TCELL4:OUT.HALF.BOT5.TMIN, TCELL4:OUT.HALT.TOP5.TMIN
CDRSTATUS13	output	TCELL5:OUT.SEC0.TMIN
CDRSTATUS14	output	TCELL5:OUT.SEC1.TMIN
CDRSTATUS15	output	TCELL6:OUT.HALF.BOT4.TMIN, TCELL6:OUT.HALT.TOP4.TMIN
CDRSTATUS16	output	TCELL6:OUT.HALF.BOT5.TMIN, TCELL6:OUT.HALT.TOP5.TMIN
CDRSTATUS17	output	TCELL8:OUT.HALF.BOT4.TMIN, TCELL8:OUT.HALT.TOP4.TMIN
CDRSTATUS2	output	TCELL1:OUT.HALF.BOT6.TMIN, TCELL1:OUT.HALT.TOP6.TMIN
CDRSTATUS3	output	TCELL1:OUT.HALF.BOT7.TMIN, TCELL1:OUT.HALT.TOP7.TMIN
CDRSTATUS4	output	TCELL2:OUT.HALF.BOT4.TMIN, TCELL2:OUT.HALT.TOP4.TMIN
CDRSTATUS5	output	TCELL2:OUT.HALF.BOT5.TMIN, TCELL2:OUT.HALT.TOP5.TMIN
CDRSTATUS6	output	TCELL2:OUT.HALF.BOT6.TMIN, TCELL2:OUT.HALT.TOP6.TMIN
CDRSTATUS7	output	TCELL3:OUT.HALF.BOT4.TMIN, TCELL3:OUT.HALT.TOP4.TMIN
CDRSTATUS8	output	TCELL3:OUT.HALF.BOT5.TMIN, TCELL3:OUT.HALT.TOP5.TMIN
CDRSTATUS9	output	TCELL3:OUT.HALF.BOT6.TMIN, TCELL3:OUT.HALT.TOP6.TMIN
CHBONDI0	input	TCELL13:IMUX.IMUX12
CHBONDI1	input	TCELL13:IMUX.IMUX13
CHBONDI2	input	TCELL13:IMUX.IMUX14
CHBONDI3	input	TCELL13:IMUX.IMUX15
CHBONDI4	input	TCELL13:IMUX.IMUX16
CHBONDO0	output	TCELL11:OUT.BEST4.TMIN
CHBONDO1	output	TCELL11:OUT.BEST5.TMIN
CHBONDO2	output	TCELL11:OUT.BEST6.TMIN
CHBONDO3	output	TCELL11:OUT.BEST7.TMIN
CHBONDO4	output	TCELL11:OUT.SEC0.TMIN
DADDR0	input	TCELL6:IMUX.IMUX12
DADDR1	input	TCELL6:IMUX.IMUX13
DADDR2	input	TCELL6:IMUX.IMUX14
DADDR3	input	TCELL6:IMUX.IMUX15
DADDR4	input	TCELL7:IMUX.IMUX20
DADDR5	input	TCELL7:IMUX.IMUX21
DADDR6	input	TCELL7:IMUX.IMUX22
DADDR7	input	TCELL7:IMUX.IMUX23
DCLK	input	TCELL8:IMUX.CLK3
DEN	input	TCELL8:IMUX.CE0
DI0	input	TCELL7:IMUX.IMUX12
DI1	input	TCELL7:IMUX.IMUX13
DI10	input	TCELL8:IMUX.IMUX14
DI11	input	TCELL8:IMUX.IMUX15
DI12	input	TCELL8:IMUX.IMUX20
DI13	input	TCELL8:IMUX.IMUX21
DI14	input	TCELL8:IMUX.IMUX22
DI15	input	TCELL8:IMUX.IMUX23
DI2	input	TCELL7:IMUX.IMUX14
DI3	input	TCELL7:IMUX.IMUX15
DI4	input	TCELL7:IMUX.IMUX16
DI5	input	TCELL7:IMUX.IMUX17
DI6	input	TCELL7:IMUX.IMUX18
DI7	input	TCELL7:IMUX.IMUX19
DI8	input	TCELL8:IMUX.IMUX12
DI9	input	TCELL8:IMUX.IMUX13
DO0	output	TCELL5:OUT.HALF.BOT4.TMIN, TCELL5:OUT.HALT.TOP4.TMIN
DO1	output	TCELL5:OUT.HALF.BOT5.TMIN, TCELL5:OUT.HALT.TOP5.TMIN
DO10	output	TCELL7:OUT.HALF.BOT6.TMIN, TCELL7:OUT.HALT.TOP6.TMIN
DO11	output	TCELL7:OUT.HALF.BOT7.TMIN, TCELL7:OUT.HALT.TOP7.TMIN
DO12	output	TCELL9:OUT.HALF.BOT4.TMIN, TCELL9:OUT.HALT.TOP4.TMIN
DO13	output	TCELL9:OUT.HALF.BOT5.TMIN, TCELL9:OUT.HALT.TOP5.TMIN
DO14	output	TCELL9:OUT.HALF.BOT6.TMIN, TCELL9:OUT.HALT.TOP6.TMIN
DO15	output	TCELL9:OUT.HALF.BOT7.TMIN, TCELL9:OUT.HALT.TOP7.TMIN
DO2	output	TCELL5:OUT.HALF.BOT6.TMIN, TCELL5:OUT.HALT.TOP6.TMIN
DO3	output	TCELL5:OUT.HALF.BOT7.TMIN, TCELL5:OUT.HALT.TOP7.TMIN
DO4	output	TCELL5:OUT.BEST4.TMIN
DO5	output	TCELL5:OUT.BEST5.TMIN
DO6	output	TCELL5:OUT.BEST6.TMIN
DO7	output	TCELL5:OUT.BEST7.TMIN
DO8	output	TCELL7:OUT.HALF.BOT4.TMIN, TCELL7:OUT.HALT.TOP4.TMIN
DO9	output	TCELL7:OUT.HALF.BOT5.TMIN, TCELL7:OUT.HALT.TOP5.TMIN
DRDY	output	TCELL7:OUT.SEC0.TMIN
DWE	input	TCELL8:IMUX.CE1
ENCHANSYNC	input	TCELL15:IMUX.IMUX12
ENMCOMMAALIGN	input	TCELL3:IMUX.IMUX13
ENPCOMMAALIGN	input	TCELL3:IMUX.IMUX12
LOOPBACK0	input	TCELL15:IMUX.IMUX15
LOOPBACK1	input	TCELL15:IMUX.IMUX16
MGTADCSEL0	input	TCELL9:IMUX.IMUX14
MGTADCSEL1	input	TCELL9:IMUX.IMUX15
MGTADCSEL2	input	TCELL9:IMUX.IMUX16
MGTADCSEL3	input	TCELL9:IMUX.IMUX17
MGTADCSEL4	input	TCELL9:IMUX.IMUX18
POWERDOWN	input	TCELL15:IMUX.IMUX13
RXADCN	output	TCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN
RXADCP	output	TCELL1:OUT.BEST7.TMIN
RXBLOCKSYNC64B66BUSE	input	TCELL3:IMUX.IMUX15
RXBUFERR	output	TCELL4:OUT.HALF.BOT6.TMIN, TCELL4:OUT.HALT.TOP6.TMIN
RXCALFAIL	output	TCELL3:OUT.BEST6.TMIN
RXCHARISCOMMA0	output	TCELL0:OUT.BEST7.TMIN
RXCHARISCOMMA1	output	TCELL2:OUT.BEST7.TMIN
RXCHARISCOMMA2	output	TCELL4:OUT.BEST7.TMIN
RXCHARISCOMMA3	output	TCELL6:OUT.BEST7.TMIN
RXCHARISCOMMA4	output	TCELL8:OUT.BEST7.TMIN
RXCHARISCOMMA5	output	TCELL10:OUT.BEST7.TMIN
RXCHARISCOMMA6	output	TCELL12:OUT.BEST7.TMIN
RXCHARISCOMMA7	output	TCELL14:OUT.BEST7.TMIN
RXCHARISK0	output	TCELL0:OUT.BEST6.TMIN
RXCHARISK1	output	TCELL2:OUT.BEST6.TMIN
RXCHARISK2	output	TCELL4:OUT.BEST6.TMIN
RXCHARISK3	output	TCELL6:OUT.BEST6.TMIN
RXCHARISK4	output	TCELL8:OUT.BEST6.TMIN
RXCHARISK5	output	TCELL10:OUT.BEST6.TMIN
RXCHARISK6	output	TCELL12:OUT.BEST6.TMIN
RXCHARISK7	output	TCELL14:OUT.BEST6.TMIN
RXCLKSTABLE	input	TCELL3:IMUX.IMUX19
RXCOARSEST	output	TCELL15:OUT.SEC0.TMIN
RXCOMMADET	output	TCELL9:OUT.BEST5.TMIN
RXCOMMADETUSE	input	TCELL3:IMUX.IMUX16
RXCRCCLK	input	TCELL8:IMUX.CLK1
RXCRCDATAVALID	input	TCELL7:IMUX.CE0
RXCRCDATAWIDTH0	input	TCELL11:IMUX.IMUX17
RXCRCDATAWIDTH1	input	TCELL11:IMUX.IMUX18
RXCRCDATAWIDTH2	input	TCELL11:IMUX.IMUX19
RXCRCIN0	input	TCELL1:IMUX.IMUX11
RXCRCIN1	input	TCELL1:IMUX.IMUX10
RXCRCIN10	input	TCELL3:IMUX.IMUX9
RXCRCIN11	input	TCELL3:IMUX.IMUX8
RXCRCIN12	input	TCELL2:IMUX.IMUX11
RXCRCIN13	input	TCELL2:IMUX.IMUX10
RXCRCIN14	input	TCELL2:IMUX.IMUX9
RXCRCIN15	input	TCELL2:IMUX.IMUX8
RXCRCIN16	input	TCELL5:IMUX.IMUX11
RXCRCIN17	input	TCELL5:IMUX.IMUX10
RXCRCIN18	input	TCELL5:IMUX.IMUX9
RXCRCIN19	input	TCELL5:IMUX.IMUX8
RXCRCIN2	input	TCELL1:IMUX.IMUX9
RXCRCIN20	input	TCELL4:IMUX.IMUX11
RXCRCIN21	input	TCELL4:IMUX.IMUX10
RXCRCIN22	input	TCELL4:IMUX.IMUX9
RXCRCIN23	input	TCELL4:IMUX.IMUX8
RXCRCIN24	input	TCELL7:IMUX.IMUX11
RXCRCIN25	input	TCELL7:IMUX.IMUX10
RXCRCIN26	input	TCELL7:IMUX.IMUX9
RXCRCIN27	input	TCELL7:IMUX.IMUX8
RXCRCIN28	input	TCELL6:IMUX.IMUX11
RXCRCIN29	input	TCELL6:IMUX.IMUX10
RXCRCIN3	input	TCELL1:IMUX.IMUX8
RXCRCIN30	input	TCELL6:IMUX.IMUX9
RXCRCIN31	input	TCELL6:IMUX.IMUX8
RXCRCIN32	input	TCELL9:IMUX.IMUX11
RXCRCIN33	input	TCELL9:IMUX.IMUX10
RXCRCIN34	input	TCELL9:IMUX.IMUX9
RXCRCIN35	input	TCELL9:IMUX.IMUX8
RXCRCIN36	input	TCELL8:IMUX.IMUX11
RXCRCIN37	input	TCELL8:IMUX.IMUX10
RXCRCIN38	input	TCELL8:IMUX.IMUX9
RXCRCIN39	input	TCELL8:IMUX.IMUX8
RXCRCIN4	input	TCELL0:IMUX.IMUX11
RXCRCIN40	input	TCELL11:IMUX.IMUX11
RXCRCIN41	input	TCELL11:IMUX.IMUX10
RXCRCIN42	input	TCELL11:IMUX.IMUX9
RXCRCIN43	input	TCELL11:IMUX.IMUX8
RXCRCIN44	input	TCELL10:IMUX.IMUX11
RXCRCIN45	input	TCELL10:IMUX.IMUX10
RXCRCIN46	input	TCELL10:IMUX.IMUX9
RXCRCIN47	input	TCELL10:IMUX.IMUX8
RXCRCIN48	input	TCELL13:IMUX.IMUX11
RXCRCIN49	input	TCELL13:IMUX.IMUX10
RXCRCIN5	input	TCELL0:IMUX.IMUX10
RXCRCIN50	input	TCELL13:IMUX.IMUX9
RXCRCIN51	input	TCELL13:IMUX.IMUX8
RXCRCIN52	input	TCELL12:IMUX.IMUX11
RXCRCIN53	input	TCELL12:IMUX.IMUX10
RXCRCIN54	input	TCELL12:IMUX.IMUX9
RXCRCIN55	input	TCELL12:IMUX.IMUX8
RXCRCIN56	input	TCELL15:IMUX.IMUX11
RXCRCIN57	input	TCELL15:IMUX.IMUX10
RXCRCIN58	input	TCELL15:IMUX.IMUX9
RXCRCIN59	input	TCELL15:IMUX.IMUX8
RXCRCIN6	input	TCELL0:IMUX.IMUX9
RXCRCIN60	input	TCELL14:IMUX.IMUX11
RXCRCIN61	input	TCELL14:IMUX.IMUX10
RXCRCIN62	input	TCELL14:IMUX.IMUX9
RXCRCIN63	input	TCELL14:IMUX.IMUX8
RXCRCIN7	input	TCELL0:IMUX.IMUX8
RXCRCIN8	input	TCELL3:IMUX.IMUX11
RXCRCIN9	input	TCELL3:IMUX.IMUX10
RXCRCINIT	input	TCELL5:IMUX.IMUX16
RXCRCINTCLK	input	TCELL7:IMUX.CLK0
RXCRCOUT0	output	TCELL9:OUT.HALF.BOT3.TMIN, TCELL9:OUT.HALT.TOP3.TMIN
RXCRCOUT1	output	TCELL9:OUT.HALF.BOT2.TMIN, TCELL9:OUT.HALT.TOP2.TMIN
RXCRCOUT10	output	TCELL11:OUT.HALF.BOT1.TMIN, TCELL11:OUT.HALT.TOP1.TMIN
RXCRCOUT11	output	TCELL11:OUT.HALF.BOT0.TMIN, TCELL11:OUT.HALT.TOP0.TMIN
RXCRCOUT12	output	TCELL10:OUT.HALF.BOT3.TMIN, TCELL10:OUT.HALT.TOP3.TMIN
RXCRCOUT13	output	TCELL10:OUT.HALF.BOT2.TMIN, TCELL10:OUT.HALT.TOP2.TMIN
RXCRCOUT14	output	TCELL10:OUT.HALF.BOT1.TMIN, TCELL10:OUT.HALT.TOP1.TMIN
RXCRCOUT15	output	TCELL10:OUT.HALF.BOT0.TMIN, TCELL10:OUT.HALT.TOP0.TMIN
RXCRCOUT16	output	TCELL13:OUT.HALF.BOT3.TMIN, TCELL13:OUT.HALT.TOP3.TMIN
RXCRCOUT17	output	TCELL13:OUT.HALF.BOT2.TMIN, TCELL13:OUT.HALT.TOP2.TMIN
RXCRCOUT18	output	TCELL13:OUT.HALF.BOT1.TMIN, TCELL13:OUT.HALT.TOP1.TMIN
RXCRCOUT19	output	TCELL13:OUT.HALF.BOT0.TMIN, TCELL13:OUT.HALT.TOP0.TMIN
RXCRCOUT2	output	TCELL9:OUT.HALF.BOT1.TMIN, TCELL9:OUT.HALT.TOP1.TMIN
RXCRCOUT20	output	TCELL12:OUT.HALF.BOT3.TMIN, TCELL12:OUT.HALT.TOP3.TMIN
RXCRCOUT21	output	TCELL12:OUT.HALF.BOT2.TMIN, TCELL12:OUT.HALT.TOP2.TMIN
RXCRCOUT22	output	TCELL12:OUT.HALF.BOT1.TMIN, TCELL12:OUT.HALT.TOP1.TMIN
RXCRCOUT23	output	TCELL12:OUT.HALF.BOT0.TMIN, TCELL12:OUT.HALT.TOP0.TMIN
RXCRCOUT24	output	TCELL15:OUT.HALF.BOT3.TMIN, TCELL15:OUT.HALT.TOP3.TMIN
RXCRCOUT25	output	TCELL15:OUT.HALF.BOT2.TMIN, TCELL15:OUT.HALT.TOP2.TMIN
RXCRCOUT26	output	TCELL15:OUT.HALF.BOT1.TMIN, TCELL15:OUT.HALT.TOP1.TMIN
RXCRCOUT27	output	TCELL15:OUT.HALF.BOT0.TMIN, TCELL15:OUT.HALT.TOP0.TMIN
RXCRCOUT28	output	TCELL14:OUT.HALF.BOT3.TMIN, TCELL14:OUT.HALT.TOP3.TMIN
RXCRCOUT29	output	TCELL14:OUT.HALF.BOT2.TMIN, TCELL14:OUT.HALT.TOP2.TMIN
RXCRCOUT3	output	TCELL9:OUT.HALF.BOT0.TMIN, TCELL9:OUT.HALT.TOP0.TMIN
RXCRCOUT30	output	TCELL14:OUT.HALF.BOT1.TMIN, TCELL14:OUT.HALT.TOP1.TMIN
RXCRCOUT31	output	TCELL14:OUT.HALF.BOT0.TMIN, TCELL14:OUT.HALT.TOP0.TMIN
RXCRCOUT4	output	TCELL8:OUT.HALF.BOT3.TMIN, TCELL8:OUT.HALT.TOP3.TMIN
RXCRCOUT5	output	TCELL8:OUT.HALF.BOT2.TMIN, TCELL8:OUT.HALT.TOP2.TMIN
RXCRCOUT6	output	TCELL8:OUT.HALF.BOT1.TMIN, TCELL8:OUT.HALT.TOP1.TMIN
RXCRCOUT7	output	TCELL8:OUT.HALF.BOT0.TMIN, TCELL8:OUT.HALT.TOP0.TMIN
RXCRCOUT8	output	TCELL11:OUT.HALF.BOT3.TMIN, TCELL11:OUT.HALT.TOP3.TMIN
RXCRCOUT9	output	TCELL11:OUT.HALF.BOT2.TMIN, TCELL11:OUT.HALT.TOP2.TMIN
RXCRCPD	input	TCELL9:IMUX.IMUX12
RXCRCRESET	input	TCELL7:IMUX.SR0
RXCYCLELIMIT	output	TCELL11:OUT.HALF.BOT4.TMIN, TCELL11:OUT.HALT.TOP4.TMIN
RXDATA0	output	TCELL0:OUT.BEST0.TMIN
RXDATA1	output	TCELL0:OUT.BEST1.TMIN
RXDATA10	output	TCELL2:OUT.BEST2.TMIN
RXDATA11	output	TCELL2:OUT.BEST3.TMIN
RXDATA12	output	TCELL3:OUT.BEST0.TMIN
RXDATA13	output	TCELL3:OUT.BEST1.TMIN
RXDATA14	output	TCELL3:OUT.BEST2.TMIN
RXDATA15	output	TCELL3:OUT.BEST3.TMIN
RXDATA16	output	TCELL4:OUT.BEST0.TMIN
RXDATA17	output	TCELL4:OUT.BEST1.TMIN
RXDATA18	output	TCELL4:OUT.BEST2.TMIN
RXDATA19	output	TCELL4:OUT.BEST3.TMIN
RXDATA2	output	TCELL0:OUT.BEST2.TMIN
RXDATA20	output	TCELL5:OUT.BEST0.TMIN
RXDATA21	output	TCELL5:OUT.BEST1.TMIN
RXDATA22	output	TCELL5:OUT.BEST2.TMIN
RXDATA23	output	TCELL5:OUT.BEST3.TMIN
RXDATA24	output	TCELL6:OUT.BEST0.TMIN
RXDATA25	output	TCELL6:OUT.BEST1.TMIN
RXDATA26	output	TCELL6:OUT.BEST2.TMIN
RXDATA27	output	TCELL6:OUT.BEST3.TMIN
RXDATA28	output	TCELL7:OUT.BEST0.TMIN
RXDATA29	output	TCELL7:OUT.BEST1.TMIN
RXDATA3	output	TCELL0:OUT.BEST3.TMIN
RXDATA30	output	TCELL7:OUT.BEST2.TMIN
RXDATA31	output	TCELL7:OUT.BEST3.TMIN
RXDATA32	output	TCELL8:OUT.BEST0.TMIN
RXDATA33	output	TCELL8:OUT.BEST1.TMIN
RXDATA34	output	TCELL8:OUT.BEST2.TMIN
RXDATA35	output	TCELL8:OUT.BEST3.TMIN
RXDATA36	output	TCELL9:OUT.BEST0.TMIN
RXDATA37	output	TCELL9:OUT.BEST1.TMIN
RXDATA38	output	TCELL9:OUT.BEST2.TMIN
RXDATA39	output	TCELL9:OUT.BEST3.TMIN
RXDATA4	output	TCELL1:OUT.BEST0.TMIN
RXDATA40	output	TCELL10:OUT.BEST0.TMIN
RXDATA41	output	TCELL10:OUT.BEST1.TMIN
RXDATA42	output	TCELL10:OUT.BEST2.TMIN
RXDATA43	output	TCELL10:OUT.BEST3.TMIN
RXDATA44	output	TCELL11:OUT.BEST0.TMIN
RXDATA45	output	TCELL11:OUT.BEST1.TMIN
RXDATA46	output	TCELL11:OUT.BEST2.TMIN
RXDATA47	output	TCELL11:OUT.BEST3.TMIN
RXDATA48	output	TCELL12:OUT.BEST0.TMIN
RXDATA49	output	TCELL12:OUT.BEST1.TMIN
RXDATA5	output	TCELL1:OUT.BEST1.TMIN
RXDATA50	output	TCELL12:OUT.BEST2.TMIN
RXDATA51	output	TCELL12:OUT.BEST3.TMIN
RXDATA52	output	TCELL13:OUT.BEST0.TMIN
RXDATA53	output	TCELL13:OUT.BEST1.TMIN
RXDATA54	output	TCELL13:OUT.BEST2.TMIN
RXDATA55	output	TCELL13:OUT.BEST3.TMIN
RXDATA56	output	TCELL14:OUT.BEST0.TMIN
RXDATA57	output	TCELL14:OUT.BEST1.TMIN
RXDATA58	output	TCELL14:OUT.BEST2.TMIN
RXDATA59	output	TCELL14:OUT.BEST3.TMIN
RXDATA6	output	TCELL1:OUT.BEST2.TMIN
RXDATA60	output	TCELL15:OUT.BEST0.TMIN
RXDATA61	output	TCELL15:OUT.BEST1.TMIN
RXDATA62	output	TCELL15:OUT.BEST2.TMIN
RXDATA63	output	TCELL15:OUT.BEST3.TMIN
RXDATA7	output	TCELL1:OUT.BEST3.TMIN
RXDATA8	output	TCELL2:OUT.BEST0.TMIN
RXDATA9	output	TCELL2:OUT.BEST1.TMIN
RXDATAWIDTH0	input	TCELL1:IMUX.IMUX22
RXDATAWIDTH1	input	TCELL1:IMUX.IMUX23
RXDEC64B66BUSE	input	TCELL12:IMUX.IMUX13
RXDEC8B10BUSE	input	TCELL12:IMUX.IMUX12
RXDESCRAM64B66BUSE	input	TCELL3:IMUX.IMUX14
RXDISPERR0	output	TCELL0:OUT.BEST4.TMIN
RXDISPERR1	output	TCELL2:OUT.BEST4.TMIN
RXDISPERR2	output	TCELL4:OUT.BEST4.TMIN
RXDISPERR3	output	TCELL6:OUT.BEST4.TMIN
RXDISPERR4	output	TCELL8:OUT.BEST4.TMIN
RXDISPERR5	output	TCELL10:OUT.BEST4.TMIN
RXDISPERR6	output	TCELL12:OUT.BEST4.TMIN
RXDISPERR7	output	TCELL14:OUT.BEST4.TMIN
RXENABLECAL	output	TCELL15:OUT.SEC1.TMIN
RXFCALSTATE0	output	TCELL14:OUT.HALF.BOT4.TMIN, TCELL14:OUT.HALT.TOP4.TMIN
RXFCALSTATE1	output	TCELL14:OUT.HALF.BOT5.TMIN, TCELL14:OUT.HALT.TOP5.TMIN
RXFCALSTATE2	output	TCELL14:OUT.HALF.BOT6.TMIN, TCELL14:OUT.HALT.TOP6.TMIN
RXFDETSTATE0	output	TCELL13:OUT.SEC0.TMIN
RXFDETSTATE1	output	TCELL13:OUT.SEC1.TMIN
RXFDETSTATE2	output	TCELL13:OUT.SEC2.TMIN
RXIGNOREBTF	input	TCELL12:IMUX.IMUX15
RXINTDATAWIDTH0	input	TCELL1:IMUX.IMUX18
RXINTDATAWIDTH1	input	TCELL1:IMUX.IMUX19
RXLOCK	output	TCELL15:OUT.HALF.BOT4.TMIN, TCELL15:OUT.HALT.TOP4.TMIN
RXLOCKUPDATE	output	TCELL15:OUT.HALF.BOT6.TMIN, TCELL15:OUT.HALT.TOP6.TMIN
RXLOSSOFSYNC0	output	TCELL1:OUT.BEST4.TMIN
RXLOSSOFSYNC1	output	TCELL1:OUT.BEST5.TMIN
RXNOTINTABLE0	output	TCELL0:OUT.BEST5.TMIN
RXNOTINTABLE1	output	TCELL2:OUT.BEST5.TMIN
RXNOTINTABLE2	output	TCELL4:OUT.BEST5.TMIN
RXNOTINTABLE3	output	TCELL6:OUT.BEST5.TMIN
RXNOTINTABLE4	output	TCELL8:OUT.BEST5.TMIN
RXNOTINTABLE5	output	TCELL10:OUT.BEST5.TMIN
RXNOTINTABLE6	output	TCELL12:OUT.BEST5.TMIN
RXNOTINTABLE7	output	TCELL14:OUT.BEST5.TMIN
RXPMARESET	input	TCELL9:IMUX.SR0
RXPOLARITY	input	TCELL15:IMUX.IMUX14
RXREALIGN	output	TCELL9:OUT.BEST4.TMIN
RXRECCLK1	output	TCELL7:OUT.BEST4.TMIN
RXRECCLK2	output	TCELL7:OUT.BEST5.TMIN
RXRESET	input	TCELL0:IMUX.SR0
RXRUNDISP0	output	TCELL0:OUT.SEC0.TMIN
RXRUNDISP1	output	TCELL2:OUT.SEC0.TMIN
RXRUNDISP2	output	TCELL4:OUT.SEC0.TMIN
RXRUNDISP3	output	TCELL6:OUT.SEC0.TMIN
RXRUNDISP4	output	TCELL8:OUT.SEC0.TMIN
RXRUNDISP5	output	TCELL10:OUT.SEC0.TMIN
RXRUNDISP6	output	TCELL12:OUT.SEC0.TMIN
RXRUNDISP7	output	TCELL14:OUT.SEC0.TMIN
RXSIGDET	output	TCELL1:OUT.BEST6.TMIN
RXSLIDE	input	TCELL3:IMUX.IMUX17
RXSTATUS0	output	TCELL15:OUT.BEST4.TMIN
RXSTATUS1	output	TCELL15:OUT.BEST5.TMIN
RXSTATUS2	output	TCELL15:OUT.BEST6.TMIN
RXSTATUS3	output	TCELL13:OUT.HALF.BOT5.TMIN, TCELL13:OUT.HALT.TOP5.TMIN
RXSTATUS4	output	TCELL13:OUT.HALF.BOT6.TMIN, TCELL13:OUT.HALT.TOP6.TMIN
RXSTATUS5	output	TCELL13:OUT.BEST4.TMIN
RXSYNC	input	TCELL2:IMUX.IMUX14
RXUSRCLK	input	TCELL6:IMUX.CLK0
RXUSRCLK2	input	TCELL6:IMUX.CLK1
RXUSRLOCK	input	TCELL10:IMUX.IMUX12
RXUSRVCOCAL	input	TCELL10:IMUX.IMUX13
RXUSRVCODAC0	input	TCELL0:IMUX.IMUX12
RXUSRVCODAC1	input	TCELL0:IMUX.IMUX13
RXUSRVCODAC2	input	TCELL0:IMUX.IMUX14
RXUSRVCODAC3	input	TCELL0:IMUX.IMUX15
RXUSRVCODAC4	input	TCELL1:IMUX.IMUX12
RXUSRVCODAC5	input	TCELL1:IMUX.IMUX13
RXUSRVCODAC6	input	TCELL1:IMUX.IMUX14
RXUSRVCODAC7	input	TCELL1:IMUX.IMUX15
RXUSRVCODAC8	input	TCELL2:IMUX.IMUX12
RXUSRVCODAC9	input	TCELL2:IMUX.IMUX13
RXVCOHIGH	output	TCELL3:OUT.BEST4.TMIN
SCANEN0	input	TCELL14:IMUX.CE0
SCANEN1	input	TCELL14:IMUX.CE1
SCANEN2	input	TCELL12:IMUX.CE0
SCANIN0	input	TCELL15:IMUX.IMUX19
SCANIN1	input	TCELL15:IMUX.IMUX20
SCANIN2	input	TCELL15:IMUX.IMUX21
SCANMODE0	input	TCELL13:IMUX.CE0
SCANMODE1	input	TCELL13:IMUX.CE1
SCANMODE2	input	TCELL12:IMUX.CE1
SCANOUT0	output	TCELL13:OUT.BEST6.TMIN
SCANOUT1	output	TCELL13:OUT.BEST7.TMIN
SCANOUT2	output	TCELL11:OUT.SEC1.TMIN
TESTMEMORY	input	TCELL12:IMUX.IMUX14
TXADCN	output	TCELL6:OUT.HALF.BOT6.TMIN, TCELL6:OUT.HALT.TOP6.TMIN
TXADCP	output	TCELL7:OUT.SEC1.TMIN
TXBUFERR	output	TCELL13:OUT.BEST5.TMIN
TXBYPASS8B10B0	input	TCELL0:IMUX.IMUX16
TXBYPASS8B10B1	input	TCELL2:IMUX.IMUX16
TXBYPASS8B10B2	input	TCELL4:IMUX.IMUX16
TXBYPASS8B10B3	input	TCELL6:IMUX.IMUX16
TXBYPASS8B10B4	input	TCELL8:IMUX.IMUX16
TXBYPASS8B10B5	input	TCELL10:IMUX.IMUX16
TXBYPASS8B10B6	input	TCELL12:IMUX.IMUX16
TXBYPASS8B10B7	input	TCELL14:IMUX.IMUX16
TXCALFAIL	output	TCELL3:OUT.BEST7.TMIN
TXCHARDISPMODE0	input	TCELL0:IMUX.IMUX18
TXCHARDISPMODE1	input	TCELL2:IMUX.IMUX18
TXCHARDISPMODE2	input	TCELL4:IMUX.IMUX18
TXCHARDISPMODE3	input	TCELL6:IMUX.IMUX18
TXCHARDISPMODE4	input	TCELL8:IMUX.IMUX18
TXCHARDISPMODE5	input	TCELL10:IMUX.IMUX18
TXCHARDISPMODE6	input	TCELL12:IMUX.IMUX18
TXCHARDISPMODE7	input	TCELL14:IMUX.IMUX18
TXCHARDISPVAL0	input	TCELL0:IMUX.IMUX19
TXCHARDISPVAL1	input	TCELL2:IMUX.IMUX19
TXCHARDISPVAL2	input	TCELL4:IMUX.IMUX19
TXCHARDISPVAL3	input	TCELL6:IMUX.IMUX19
TXCHARDISPVAL4	input	TCELL8:IMUX.IMUX19
TXCHARDISPVAL5	input	TCELL10:IMUX.IMUX19
TXCHARDISPVAL6	input	TCELL12:IMUX.IMUX19
TXCHARDISPVAL7	input	TCELL14:IMUX.IMUX19
TXCHARISK0	input	TCELL0:IMUX.IMUX17
TXCHARISK1	input	TCELL2:IMUX.IMUX17
TXCHARISK2	input	TCELL4:IMUX.IMUX17
TXCHARISK3	input	TCELL6:IMUX.IMUX17
TXCHARISK4	input	TCELL8:IMUX.IMUX17
TXCHARISK5	input	TCELL10:IMUX.IMUX17
TXCHARISK6	input	TCELL12:IMUX.IMUX17
TXCHARISK7	input	TCELL14:IMUX.IMUX17
TXCLKSTABLE	input	TCELL3:IMUX.IMUX18
TXCOARSEST	output	TCELL12:OUT.HALF.BOT4.TMIN, TCELL12:OUT.HALT.TOP4.TMIN
TXCRCCLK	input	TCELL8:IMUX.CLK0
TXCRCDATAVALID	input	TCELL7:IMUX.CE1
TXCRCDATAWIDTH0	input	TCELL11:IMUX.IMUX20
TXCRCDATAWIDTH1	input	TCELL11:IMUX.IMUX21
TXCRCDATAWIDTH2	input	TCELL11:IMUX.IMUX22
TXCRCIN0	input	TCELL1:IMUX.IMUX7
TXCRCIN1	input	TCELL1:IMUX.IMUX6
TXCRCIN10	input	TCELL3:IMUX.IMUX5
TXCRCIN11	input	TCELL3:IMUX.IMUX4
TXCRCIN12	input	TCELL2:IMUX.IMUX7
TXCRCIN13	input	TCELL2:IMUX.IMUX6
TXCRCIN14	input	TCELL2:IMUX.IMUX5
TXCRCIN15	input	TCELL2:IMUX.IMUX4
TXCRCIN16	input	TCELL5:IMUX.IMUX7
TXCRCIN17	input	TCELL5:IMUX.IMUX6
TXCRCIN18	input	TCELL5:IMUX.IMUX5
TXCRCIN19	input	TCELL5:IMUX.IMUX4
TXCRCIN2	input	TCELL1:IMUX.IMUX5
TXCRCIN20	input	TCELL4:IMUX.IMUX7
TXCRCIN21	input	TCELL4:IMUX.IMUX6
TXCRCIN22	input	TCELL4:IMUX.IMUX5
TXCRCIN23	input	TCELL4:IMUX.IMUX4
TXCRCIN24	input	TCELL7:IMUX.IMUX7
TXCRCIN25	input	TCELL7:IMUX.IMUX6
TXCRCIN26	input	TCELL7:IMUX.IMUX5
TXCRCIN27	input	TCELL7:IMUX.IMUX4
TXCRCIN28	input	TCELL6:IMUX.IMUX7
TXCRCIN29	input	TCELL6:IMUX.IMUX6
TXCRCIN3	input	TCELL1:IMUX.IMUX4
TXCRCIN30	input	TCELL6:IMUX.IMUX5
TXCRCIN31	input	TCELL6:IMUX.IMUX4
TXCRCIN32	input	TCELL9:IMUX.IMUX7
TXCRCIN33	input	TCELL9:IMUX.IMUX6
TXCRCIN34	input	TCELL9:IMUX.IMUX5
TXCRCIN35	input	TCELL9:IMUX.IMUX4
TXCRCIN36	input	TCELL8:IMUX.IMUX7
TXCRCIN37	input	TCELL8:IMUX.IMUX6
TXCRCIN38	input	TCELL8:IMUX.IMUX5
TXCRCIN39	input	TCELL8:IMUX.IMUX4
TXCRCIN4	input	TCELL0:IMUX.IMUX7
TXCRCIN40	input	TCELL11:IMUX.IMUX7
TXCRCIN41	input	TCELL11:IMUX.IMUX6
TXCRCIN42	input	TCELL11:IMUX.IMUX5
TXCRCIN43	input	TCELL11:IMUX.IMUX4
TXCRCIN44	input	TCELL10:IMUX.IMUX7
TXCRCIN45	input	TCELL10:IMUX.IMUX6
TXCRCIN46	input	TCELL10:IMUX.IMUX5
TXCRCIN47	input	TCELL10:IMUX.IMUX4
TXCRCIN48	input	TCELL13:IMUX.IMUX7
TXCRCIN49	input	TCELL13:IMUX.IMUX6
TXCRCIN5	input	TCELL0:IMUX.IMUX6
TXCRCIN50	input	TCELL13:IMUX.IMUX5
TXCRCIN51	input	TCELL13:IMUX.IMUX4
TXCRCIN52	input	TCELL12:IMUX.IMUX7
TXCRCIN53	input	TCELL12:IMUX.IMUX6
TXCRCIN54	input	TCELL12:IMUX.IMUX5
TXCRCIN55	input	TCELL12:IMUX.IMUX4
TXCRCIN56	input	TCELL15:IMUX.IMUX7
TXCRCIN57	input	TCELL15:IMUX.IMUX6
TXCRCIN58	input	TCELL15:IMUX.IMUX5
TXCRCIN59	input	TCELL15:IMUX.IMUX4
TXCRCIN6	input	TCELL0:IMUX.IMUX5
TXCRCIN60	input	TCELL14:IMUX.IMUX7
TXCRCIN61	input	TCELL14:IMUX.IMUX6
TXCRCIN62	input	TCELL14:IMUX.IMUX5
TXCRCIN63	input	TCELL14:IMUX.IMUX4
TXCRCIN7	input	TCELL0:IMUX.IMUX4
TXCRCIN8	input	TCELL3:IMUX.IMUX7
TXCRCIN9	input	TCELL3:IMUX.IMUX6
TXCRCINIT	input	TCELL5:IMUX.IMUX17
TXCRCINTCLK	input	TCELL7:IMUX.CLK1
TXCRCOUT0	output	TCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN
TXCRCOUT1	output	TCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN
TXCRCOUT10	output	TCELL3:OUT.HALF.BOT1.TMIN, TCELL3:OUT.HALT.TOP1.TMIN
TXCRCOUT11	output	TCELL3:OUT.HALF.BOT0.TMIN, TCELL3:OUT.HALT.TOP0.TMIN
TXCRCOUT12	output	TCELL2:OUT.HALF.BOT3.TMIN, TCELL2:OUT.HALT.TOP3.TMIN
TXCRCOUT13	output	TCELL2:OUT.HALF.BOT2.TMIN, TCELL2:OUT.HALT.TOP2.TMIN
TXCRCOUT14	output	TCELL2:OUT.HALF.BOT1.TMIN, TCELL2:OUT.HALT.TOP1.TMIN
TXCRCOUT15	output	TCELL2:OUT.HALF.BOT0.TMIN, TCELL2:OUT.HALT.TOP0.TMIN
TXCRCOUT16	output	TCELL5:OUT.HALF.BOT3.TMIN, TCELL5:OUT.HALT.TOP3.TMIN
TXCRCOUT17	output	TCELL5:OUT.HALF.BOT2.TMIN, TCELL5:OUT.HALT.TOP2.TMIN
TXCRCOUT18	output	TCELL5:OUT.HALF.BOT1.TMIN, TCELL5:OUT.HALT.TOP1.TMIN
TXCRCOUT19	output	TCELL5:OUT.HALF.BOT0.TMIN, TCELL5:OUT.HALT.TOP0.TMIN
TXCRCOUT2	output	TCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN
TXCRCOUT20	output	TCELL4:OUT.HALF.BOT3.TMIN, TCELL4:OUT.HALT.TOP3.TMIN
TXCRCOUT21	output	TCELL4:OUT.HALF.BOT2.TMIN, TCELL4:OUT.HALT.TOP2.TMIN
TXCRCOUT22	output	TCELL4:OUT.HALF.BOT1.TMIN, TCELL4:OUT.HALT.TOP1.TMIN
TXCRCOUT23	output	TCELL4:OUT.HALF.BOT0.TMIN, TCELL4:OUT.HALT.TOP0.TMIN
TXCRCOUT24	output	TCELL7:OUT.HALF.BOT3.TMIN, TCELL7:OUT.HALT.TOP3.TMIN
TXCRCOUT25	output	TCELL7:OUT.HALF.BOT2.TMIN, TCELL7:OUT.HALT.TOP2.TMIN
TXCRCOUT26	output	TCELL7:OUT.HALF.BOT1.TMIN, TCELL7:OUT.HALT.TOP1.TMIN
TXCRCOUT27	output	TCELL7:OUT.HALF.BOT0.TMIN, TCELL7:OUT.HALT.TOP0.TMIN
TXCRCOUT28	output	TCELL6:OUT.HALF.BOT3.TMIN, TCELL6:OUT.HALT.TOP3.TMIN
TXCRCOUT29	output	TCELL6:OUT.HALF.BOT2.TMIN, TCELL6:OUT.HALT.TOP2.TMIN
TXCRCOUT3	output	TCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN
TXCRCOUT30	output	TCELL6:OUT.HALF.BOT1.TMIN, TCELL6:OUT.HALT.TOP1.TMIN
TXCRCOUT31	output	TCELL6:OUT.HALF.BOT0.TMIN, TCELL6:OUT.HALT.TOP0.TMIN
TXCRCOUT4	output	TCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN
TXCRCOUT5	output	TCELL0:OUT.HALF.BOT2.TMIN, TCELL0:OUT.HALT.TOP2.TMIN
TXCRCOUT6	output	TCELL0:OUT.HALF.BOT1.TMIN, TCELL0:OUT.HALT.TOP1.TMIN
TXCRCOUT7	output	TCELL0:OUT.HALF.BOT0.TMIN, TCELL0:OUT.HALT.TOP0.TMIN
TXCRCOUT8	output	TCELL3:OUT.HALF.BOT3.TMIN, TCELL3:OUT.HALT.TOP3.TMIN
TXCRCOUT9	output	TCELL3:OUT.HALF.BOT2.TMIN, TCELL3:OUT.HALT.TOP2.TMIN
TXCRCPD	input	TCELL9:IMUX.IMUX13
TXCRCRESET	input	TCELL8:IMUX.SR0
TXCYCLELIMIT	output	TCELL13:OUT.HALF.BOT4.TMIN, TCELL13:OUT.HALT.TOP4.TMIN
TXDATA0	input	TCELL0:IMUX.IMUX0
TXDATA1	input	TCELL0:IMUX.IMUX1
TXDATA10	input	TCELL2:IMUX.IMUX2
TXDATA11	input	TCELL2:IMUX.IMUX3
TXDATA12	input	TCELL3:IMUX.IMUX0
TXDATA13	input	TCELL3:IMUX.IMUX1
TXDATA14	input	TCELL3:IMUX.IMUX2
TXDATA15	input	TCELL3:IMUX.IMUX3
TXDATA16	input	TCELL4:IMUX.IMUX0
TXDATA17	input	TCELL4:IMUX.IMUX1
TXDATA18	input	TCELL4:IMUX.IMUX2
TXDATA19	input	TCELL4:IMUX.IMUX3
TXDATA2	input	TCELL0:IMUX.IMUX2
TXDATA20	input	TCELL5:IMUX.IMUX0
TXDATA21	input	TCELL5:IMUX.IMUX1
TXDATA22	input	TCELL5:IMUX.IMUX2
TXDATA23	input	TCELL5:IMUX.IMUX3
TXDATA24	input	TCELL6:IMUX.IMUX0
TXDATA25	input	TCELL6:IMUX.IMUX1
TXDATA26	input	TCELL6:IMUX.IMUX2
TXDATA27	input	TCELL6:IMUX.IMUX3
TXDATA28	input	TCELL7:IMUX.IMUX0
TXDATA29	input	TCELL7:IMUX.IMUX1
TXDATA3	input	TCELL0:IMUX.IMUX3
TXDATA30	input	TCELL7:IMUX.IMUX2
TXDATA31	input	TCELL7:IMUX.IMUX3
TXDATA32	input	TCELL8:IMUX.IMUX0
TXDATA33	input	TCELL8:IMUX.IMUX1
TXDATA34	input	TCELL8:IMUX.IMUX2
TXDATA35	input	TCELL8:IMUX.IMUX3
TXDATA36	input	TCELL9:IMUX.IMUX0
TXDATA37	input	TCELL9:IMUX.IMUX1
TXDATA38	input	TCELL9:IMUX.IMUX2
TXDATA39	input	TCELL9:IMUX.IMUX3
TXDATA4	input	TCELL1:IMUX.IMUX0
TXDATA40	input	TCELL10:IMUX.IMUX0
TXDATA41	input	TCELL10:IMUX.IMUX1
TXDATA42	input	TCELL10:IMUX.IMUX2
TXDATA43	input	TCELL10:IMUX.IMUX3
TXDATA44	input	TCELL11:IMUX.IMUX0
TXDATA45	input	TCELL11:IMUX.IMUX1
TXDATA46	input	TCELL11:IMUX.IMUX2
TXDATA47	input	TCELL11:IMUX.IMUX3
TXDATA48	input	TCELL12:IMUX.IMUX0
TXDATA49	input	TCELL12:IMUX.IMUX1
TXDATA5	input	TCELL1:IMUX.IMUX1
TXDATA50	input	TCELL12:IMUX.IMUX2
TXDATA51	input	TCELL12:IMUX.IMUX3
TXDATA52	input	TCELL13:IMUX.IMUX0
TXDATA53	input	TCELL13:IMUX.IMUX1
TXDATA54	input	TCELL13:IMUX.IMUX2
TXDATA55	input	TCELL13:IMUX.IMUX3
TXDATA56	input	TCELL14:IMUX.IMUX0
TXDATA57	input	TCELL14:IMUX.IMUX1
TXDATA58	input	TCELL14:IMUX.IMUX2
TXDATA59	input	TCELL14:IMUX.IMUX3
TXDATA6	input	TCELL1:IMUX.IMUX2
TXDATA60	input	TCELL15:IMUX.IMUX0
TXDATA61	input	TCELL15:IMUX.IMUX1
TXDATA62	input	TCELL15:IMUX.IMUX2
TXDATA63	input	TCELL15:IMUX.IMUX3
TXDATA7	input	TCELL1:IMUX.IMUX3
TXDATA8	input	TCELL2:IMUX.IMUX0
TXDATA9	input	TCELL2:IMUX.IMUX1
TXDATAWIDTH0	input	TCELL1:IMUX.IMUX20
TXDATAWIDTH1	input	TCELL1:IMUX.IMUX21
TXENABLECAL	output	TCELL12:OUT.HALF.BOT5.TMIN, TCELL12:OUT.HALT.TOP5.TMIN
TXENC64B66BUSE	input	TCELL14:IMUX.IMUX13
TXENC8B10BUSE	input	TCELL14:IMUX.IMUX12
TXENOOB	input	TCELL5:IMUX.IMUX18
TXFCALSTATE0	output	TCELL10:OUT.HALF.BOT4.TMIN, TCELL10:OUT.HALT.TOP4.TMIN
TXFCALSTATE1	output	TCELL10:OUT.HALF.BOT5.TMIN, TCELL10:OUT.HALT.TOP5.TMIN
TXFCALSTATE2	output	TCELL10:OUT.HALF.BOT6.TMIN, TCELL10:OUT.HALT.TOP6.TMIN
TXFDETSTATE0	output	TCELL9:OUT.SEC0.TMIN
TXFDETSTATE1	output	TCELL9:OUT.SEC1.TMIN
TXFDETSTATE2	output	TCELL9:OUT.SEC2.TMIN
TXGEARBOX64B66BUSE	input	TCELL14:IMUX.IMUX15
TXINHIBIT	input	TCELL15:IMUX.IMUX18
TXINTDATAWIDTH0	input	TCELL1:IMUX.IMUX16
TXINTDATAWIDTH1	input	TCELL1:IMUX.IMUX17
TXKERR0	output	TCELL0:OUT.SEC2.TMIN
TXKERR1	output	TCELL2:OUT.SEC2.TMIN
TXKERR2	output	TCELL4:OUT.SEC2.TMIN
TXKERR3	output	TCELL6:OUT.SEC2.TMIN
TXKERR4	output	TCELL8:OUT.SEC2.TMIN
TXKERR5	output	TCELL10:OUT.SEC2.TMIN
TXKERR6	output	TCELL12:OUT.SEC2.TMIN
TXKERR7	output	TCELL14:OUT.SEC2.TMIN
TXLOCK	output	TCELL15:OUT.HALF.BOT5.TMIN, TCELL15:OUT.HALT.TOP5.TMIN
TXLOCKUPDATE	output	TCELL15:OUT.HALF.BOT7.TMIN, TCELL15:OUT.HALT.TOP7.TMIN
TXOUTCLK1	output	TCELL7:OUT.BEST6.TMIN
TXOUTCLK2	output	TCELL7:OUT.BEST7.TMIN
TXPMARESET	input	TCELL10:IMUX.SR0
TXPOLARITY	input	TCELL15:IMUX.IMUX17
TXRESET	input	TCELL1:IMUX.SR0
TXRUNDISP0	output	TCELL0:OUT.SEC1.TMIN
TXRUNDISP1	output	TCELL2:OUT.SEC1.TMIN
TXRUNDISP2	output	TCELL4:OUT.SEC1.TMIN
TXRUNDISP3	output	TCELL6:OUT.SEC1.TMIN
TXRUNDISP4	output	TCELL8:OUT.SEC1.TMIN
TXRUNDISP5	output	TCELL10:OUT.SEC1.TMIN
TXRUNDISP6	output	TCELL12:OUT.SEC1.TMIN
TXRUNDISP7	output	TCELL14:OUT.SEC1.TMIN
TXSCRAM64B66BUSE	input	TCELL14:IMUX.IMUX14
TXSYNC	input	TCELL11:IMUX.IMUX12
TXUSRCLK	input	TCELL6:IMUX.CLK2
TXUSRCLK2	input	TCELL6:IMUX.CLK3
TXUSRLOCK	input	TCELL10:IMUX.IMUX14
TXUSRVCOCAL	input	TCELL10:IMUX.IMUX15
TXUSRVCODAC0	input	TCELL4:IMUX.IMUX12
TXUSRVCODAC1	input	TCELL4:IMUX.IMUX13
TXUSRVCODAC2	input	TCELL4:IMUX.IMUX14
TXUSRVCODAC3	input	TCELL4:IMUX.IMUX15
TXUSRVCODAC4	input	TCELL5:IMUX.IMUX12
TXUSRVCODAC5	input	TCELL5:IMUX.IMUX13
TXUSRVCODAC6	input	TCELL5:IMUX.IMUX14
TXUSRVCODAC7	input	TCELL5:IMUX.IMUX15
TXUSRVCODAC8	input	TCELL6:IMUX.IMUX20
TXUSRVCODAC9	input	TCELL6:IMUX.IMUX21
TXVCOHIGH	output	TCELL3:OUT.BEST5.TMIN

Bel GT11_1

virtex4 MGT bel GT11_1
Pin	Direction	Wires
CDRSTATUS0	output	TCELL17:OUT.HALF.BOT4.TMIN, TCELL17:OUT.HALT.TOP4.TMIN
CDRSTATUS1	output	TCELL17:OUT.HALF.BOT5.TMIN, TCELL17:OUT.HALT.TOP5.TMIN
CDRSTATUS10	output	TCELL19:OUT.HALF.BOT7.TMIN, TCELL19:OUT.HALT.TOP7.TMIN
CDRSTATUS11	output	TCELL20:OUT.HALF.BOT4.TMIN, TCELL20:OUT.HALT.TOP4.TMIN
CDRSTATUS12	output	TCELL20:OUT.HALF.BOT5.TMIN, TCELL20:OUT.HALT.TOP5.TMIN
CDRSTATUS13	output	TCELL21:OUT.SEC0.TMIN
CDRSTATUS14	output	TCELL21:OUT.SEC1.TMIN
CDRSTATUS15	output	TCELL22:OUT.HALF.BOT4.TMIN, TCELL22:OUT.HALT.TOP4.TMIN
CDRSTATUS16	output	TCELL22:OUT.HALF.BOT5.TMIN, TCELL22:OUT.HALT.TOP5.TMIN
CDRSTATUS17	output	TCELL24:OUT.HALF.BOT4.TMIN, TCELL24:OUT.HALT.TOP4.TMIN
CDRSTATUS2	output	TCELL17:OUT.HALF.BOT6.TMIN, TCELL17:OUT.HALT.TOP6.TMIN
CDRSTATUS3	output	TCELL17:OUT.HALF.BOT7.TMIN, TCELL17:OUT.HALT.TOP7.TMIN
CDRSTATUS4	output	TCELL18:OUT.HALF.BOT4.TMIN, TCELL18:OUT.HALT.TOP4.TMIN
CDRSTATUS5	output	TCELL18:OUT.HALF.BOT5.TMIN, TCELL18:OUT.HALT.TOP5.TMIN
CDRSTATUS6	output	TCELL18:OUT.HALF.BOT6.TMIN, TCELL18:OUT.HALT.TOP6.TMIN
CDRSTATUS7	output	TCELL19:OUT.HALF.BOT4.TMIN, TCELL19:OUT.HALT.TOP4.TMIN
CDRSTATUS8	output	TCELL19:OUT.HALF.BOT5.TMIN, TCELL19:OUT.HALT.TOP5.TMIN
CDRSTATUS9	output	TCELL19:OUT.HALF.BOT6.TMIN, TCELL19:OUT.HALT.TOP6.TMIN
CHBONDI0	input	TCELL29:IMUX.IMUX12
CHBONDI1	input	TCELL29:IMUX.IMUX13
CHBONDI2	input	TCELL29:IMUX.IMUX14
CHBONDI3	input	TCELL29:IMUX.IMUX15
CHBONDI4	input	TCELL29:IMUX.IMUX16
CHBONDO0	output	TCELL27:OUT.BEST4.TMIN
CHBONDO1	output	TCELL27:OUT.BEST5.TMIN
CHBONDO2	output	TCELL27:OUT.BEST6.TMIN
CHBONDO3	output	TCELL27:OUT.BEST7.TMIN
CHBONDO4	output	TCELL27:OUT.SEC0.TMIN
DADDR0	input	TCELL22:IMUX.IMUX12
DADDR1	input	TCELL22:IMUX.IMUX13
DADDR2	input	TCELL22:IMUX.IMUX14
DADDR3	input	TCELL22:IMUX.IMUX15
DADDR4	input	TCELL23:IMUX.IMUX20
DADDR5	input	TCELL23:IMUX.IMUX21
DADDR6	input	TCELL23:IMUX.IMUX22
DADDR7	input	TCELL23:IMUX.IMUX23
DCLK	input	TCELL24:IMUX.CLK3
DEN	input	TCELL24:IMUX.CE0
DI0	input	TCELL23:IMUX.IMUX12
DI1	input	TCELL23:IMUX.IMUX13
DI10	input	TCELL24:IMUX.IMUX14
DI11	input	TCELL24:IMUX.IMUX15
DI12	input	TCELL24:IMUX.IMUX20
DI13	input	TCELL24:IMUX.IMUX21
DI14	input	TCELL24:IMUX.IMUX22
DI15	input	TCELL24:IMUX.IMUX23
DI2	input	TCELL23:IMUX.IMUX14
DI3	input	TCELL23:IMUX.IMUX15
DI4	input	TCELL23:IMUX.IMUX16
DI5	input	TCELL23:IMUX.IMUX17
DI6	input	TCELL23:IMUX.IMUX18
DI7	input	TCELL23:IMUX.IMUX19
DI8	input	TCELL24:IMUX.IMUX12
DI9	input	TCELL24:IMUX.IMUX13
DO0	output	TCELL21:OUT.HALF.BOT4.TMIN, TCELL21:OUT.HALT.TOP4.TMIN
DO1	output	TCELL21:OUT.HALF.BOT5.TMIN, TCELL21:OUT.HALT.TOP5.TMIN
DO10	output	TCELL23:OUT.HALF.BOT6.TMIN, TCELL23:OUT.HALT.TOP6.TMIN
DO11	output	TCELL23:OUT.HALF.BOT7.TMIN, TCELL23:OUT.HALT.TOP7.TMIN
DO12	output	TCELL25:OUT.HALF.BOT4.TMIN, TCELL25:OUT.HALT.TOP4.TMIN
DO13	output	TCELL25:OUT.HALF.BOT5.TMIN, TCELL25:OUT.HALT.TOP5.TMIN
DO14	output	TCELL25:OUT.HALF.BOT6.TMIN, TCELL25:OUT.HALT.TOP6.TMIN
DO15	output	TCELL25:OUT.HALF.BOT7.TMIN, TCELL25:OUT.HALT.TOP7.TMIN
DO2	output	TCELL21:OUT.HALF.BOT6.TMIN, TCELL21:OUT.HALT.TOP6.TMIN
DO3	output	TCELL21:OUT.HALF.BOT7.TMIN, TCELL21:OUT.HALT.TOP7.TMIN
DO4	output	TCELL21:OUT.BEST4.TMIN
DO5	output	TCELL21:OUT.BEST5.TMIN
DO6	output	TCELL21:OUT.BEST6.TMIN
DO7	output	TCELL21:OUT.BEST7.TMIN
DO8	output	TCELL23:OUT.HALF.BOT4.TMIN, TCELL23:OUT.HALT.TOP4.TMIN
DO9	output	TCELL23:OUT.HALF.BOT5.TMIN, TCELL23:OUT.HALT.TOP5.TMIN
DRDY	output	TCELL23:OUT.SEC0.TMIN
DWE	input	TCELL24:IMUX.CE1
ENCHANSYNC	input	TCELL31:IMUX.IMUX12
ENMCOMMAALIGN	input	TCELL19:IMUX.IMUX13
ENPCOMMAALIGN	input	TCELL19:IMUX.IMUX12
LOOPBACK0	input	TCELL31:IMUX.IMUX15
LOOPBACK1	input	TCELL31:IMUX.IMUX16
MGTADCSEL0	input	TCELL25:IMUX.IMUX14
MGTADCSEL1	input	TCELL25:IMUX.IMUX15
MGTADCSEL2	input	TCELL25:IMUX.IMUX16
MGTADCSEL3	input	TCELL25:IMUX.IMUX17
MGTADCSEL4	input	TCELL25:IMUX.IMUX18
POWERDOWN	input	TCELL31:IMUX.IMUX13
RXADCN	output	TCELL16:OUT.HALF.BOT4.TMIN, TCELL16:OUT.HALT.TOP4.TMIN
RXADCP	output	TCELL17:OUT.BEST7.TMIN
RXBLOCKSYNC64B66BUSE	input	TCELL19:IMUX.IMUX15
RXBUFERR	output	TCELL20:OUT.HALF.BOT6.TMIN, TCELL20:OUT.HALT.TOP6.TMIN
RXCALFAIL	output	TCELL19:OUT.BEST6.TMIN
RXCHARISCOMMA0	output	TCELL16:OUT.BEST7.TMIN
RXCHARISCOMMA1	output	TCELL18:OUT.BEST7.TMIN
RXCHARISCOMMA2	output	TCELL20:OUT.BEST7.TMIN
RXCHARISCOMMA3	output	TCELL22:OUT.BEST7.TMIN
RXCHARISCOMMA4	output	TCELL24:OUT.BEST7.TMIN
RXCHARISCOMMA5	output	TCELL26:OUT.BEST7.TMIN
RXCHARISCOMMA6	output	TCELL28:OUT.BEST7.TMIN
RXCHARISCOMMA7	output	TCELL30:OUT.BEST7.TMIN
RXCHARISK0	output	TCELL16:OUT.BEST6.TMIN
RXCHARISK1	output	TCELL18:OUT.BEST6.TMIN
RXCHARISK2	output	TCELL20:OUT.BEST6.TMIN
RXCHARISK3	output	TCELL22:OUT.BEST6.TMIN
RXCHARISK4	output	TCELL24:OUT.BEST6.TMIN
RXCHARISK5	output	TCELL26:OUT.BEST6.TMIN
RXCHARISK6	output	TCELL28:OUT.BEST6.TMIN
RXCHARISK7	output	TCELL30:OUT.BEST6.TMIN
RXCLKSTABLE	input	TCELL19:IMUX.IMUX19
RXCOARSEST	output	TCELL31:OUT.SEC0.TMIN
RXCOMMADET	output	TCELL25:OUT.BEST5.TMIN
RXCOMMADETUSE	input	TCELL19:IMUX.IMUX16
RXCRCCLK	input	TCELL24:IMUX.CLK1
RXCRCDATAVALID	input	TCELL23:IMUX.CE0
RXCRCDATAWIDTH0	input	TCELL27:IMUX.IMUX17
RXCRCDATAWIDTH1	input	TCELL27:IMUX.IMUX18
RXCRCDATAWIDTH2	input	TCELL27:IMUX.IMUX19
RXCRCIN0	input	TCELL17:IMUX.IMUX11
RXCRCIN1	input	TCELL17:IMUX.IMUX10
RXCRCIN10	input	TCELL19:IMUX.IMUX9
RXCRCIN11	input	TCELL19:IMUX.IMUX8
RXCRCIN12	input	TCELL18:IMUX.IMUX11
RXCRCIN13	input	TCELL18:IMUX.IMUX10
RXCRCIN14	input	TCELL18:IMUX.IMUX9
RXCRCIN15	input	TCELL18:IMUX.IMUX8
RXCRCIN16	input	TCELL21:IMUX.IMUX11
RXCRCIN17	input	TCELL21:IMUX.IMUX10
RXCRCIN18	input	TCELL21:IMUX.IMUX9
RXCRCIN19	input	TCELL21:IMUX.IMUX8
RXCRCIN2	input	TCELL17:IMUX.IMUX9
RXCRCIN20	input	TCELL20:IMUX.IMUX11
RXCRCIN21	input	TCELL20:IMUX.IMUX10
RXCRCIN22	input	TCELL20:IMUX.IMUX9
RXCRCIN23	input	TCELL20:IMUX.IMUX8
RXCRCIN24	input	TCELL23:IMUX.IMUX11
RXCRCIN25	input	TCELL23:IMUX.IMUX10
RXCRCIN26	input	TCELL23:IMUX.IMUX9
RXCRCIN27	input	TCELL23:IMUX.IMUX8
RXCRCIN28	input	TCELL22:IMUX.IMUX11
RXCRCIN29	input	TCELL22:IMUX.IMUX10
RXCRCIN3	input	TCELL17:IMUX.IMUX8
RXCRCIN30	input	TCELL22:IMUX.IMUX9
RXCRCIN31	input	TCELL22:IMUX.IMUX8
RXCRCIN32	input	TCELL25:IMUX.IMUX11
RXCRCIN33	input	TCELL25:IMUX.IMUX10
RXCRCIN34	input	TCELL25:IMUX.IMUX9
RXCRCIN35	input	TCELL25:IMUX.IMUX8
RXCRCIN36	input	TCELL24:IMUX.IMUX11
RXCRCIN37	input	TCELL24:IMUX.IMUX10
RXCRCIN38	input	TCELL24:IMUX.IMUX9
RXCRCIN39	input	TCELL24:IMUX.IMUX8
RXCRCIN4	input	TCELL16:IMUX.IMUX11
RXCRCIN40	input	TCELL27:IMUX.IMUX11
RXCRCIN41	input	TCELL27:IMUX.IMUX10
RXCRCIN42	input	TCELL27:IMUX.IMUX9
RXCRCIN43	input	TCELL27:IMUX.IMUX8
RXCRCIN44	input	TCELL26:IMUX.IMUX11
RXCRCIN45	input	TCELL26:IMUX.IMUX10
RXCRCIN46	input	TCELL26:IMUX.IMUX9
RXCRCIN47	input	TCELL26:IMUX.IMUX8
RXCRCIN48	input	TCELL29:IMUX.IMUX11
RXCRCIN49	input	TCELL29:IMUX.IMUX10
RXCRCIN5	input	TCELL16:IMUX.IMUX10
RXCRCIN50	input	TCELL29:IMUX.IMUX9
RXCRCIN51	input	TCELL29:IMUX.IMUX8
RXCRCIN52	input	TCELL28:IMUX.IMUX11
RXCRCIN53	input	TCELL28:IMUX.IMUX10
RXCRCIN54	input	TCELL28:IMUX.IMUX9
RXCRCIN55	input	TCELL28:IMUX.IMUX8
RXCRCIN56	input	TCELL31:IMUX.IMUX11
RXCRCIN57	input	TCELL31:IMUX.IMUX10
RXCRCIN58	input	TCELL31:IMUX.IMUX9
RXCRCIN59	input	TCELL31:IMUX.IMUX8
RXCRCIN6	input	TCELL16:IMUX.IMUX9
RXCRCIN60	input	TCELL30:IMUX.IMUX11
RXCRCIN61	input	TCELL30:IMUX.IMUX10
RXCRCIN62	input	TCELL30:IMUX.IMUX9
RXCRCIN63	input	TCELL30:IMUX.IMUX8
RXCRCIN7	input	TCELL16:IMUX.IMUX8
RXCRCIN8	input	TCELL19:IMUX.IMUX11
RXCRCIN9	input	TCELL19:IMUX.IMUX10
RXCRCINIT	input	TCELL21:IMUX.IMUX16
RXCRCINTCLK	input	TCELL23:IMUX.CLK0
RXCRCOUT0	output	TCELL25:OUT.HALF.BOT3.TMIN, TCELL25:OUT.HALT.TOP3.TMIN
RXCRCOUT1	output	TCELL25:OUT.HALF.BOT2.TMIN, TCELL25:OUT.HALT.TOP2.TMIN
RXCRCOUT10	output	TCELL27:OUT.HALF.BOT1.TMIN, TCELL27:OUT.HALT.TOP1.TMIN
RXCRCOUT11	output	TCELL27:OUT.HALF.BOT0.TMIN, TCELL27:OUT.HALT.TOP0.TMIN
RXCRCOUT12	output	TCELL26:OUT.HALF.BOT3.TMIN, TCELL26:OUT.HALT.TOP3.TMIN
RXCRCOUT13	output	TCELL26:OUT.HALF.BOT2.TMIN, TCELL26:OUT.HALT.TOP2.TMIN
RXCRCOUT14	output	TCELL26:OUT.HALF.BOT1.TMIN, TCELL26:OUT.HALT.TOP1.TMIN
RXCRCOUT15	output	TCELL26:OUT.HALF.BOT0.TMIN, TCELL26:OUT.HALT.TOP0.TMIN
RXCRCOUT16	output	TCELL29:OUT.HALF.BOT3.TMIN, TCELL29:OUT.HALT.TOP3.TMIN
RXCRCOUT17	output	TCELL29:OUT.HALF.BOT2.TMIN, TCELL29:OUT.HALT.TOP2.TMIN
RXCRCOUT18	output	TCELL29:OUT.HALF.BOT1.TMIN, TCELL29:OUT.HALT.TOP1.TMIN
RXCRCOUT19	output	TCELL29:OUT.HALF.BOT0.TMIN, TCELL29:OUT.HALT.TOP0.TMIN
RXCRCOUT2	output	TCELL25:OUT.HALF.BOT1.TMIN, TCELL25:OUT.HALT.TOP1.TMIN
RXCRCOUT20	output	TCELL28:OUT.HALF.BOT3.TMIN, TCELL28:OUT.HALT.TOP3.TMIN
RXCRCOUT21	output	TCELL28:OUT.HALF.BOT2.TMIN, TCELL28:OUT.HALT.TOP2.TMIN
RXCRCOUT22	output	TCELL28:OUT.HALF.BOT1.TMIN, TCELL28:OUT.HALT.TOP1.TMIN
RXCRCOUT23	output	TCELL28:OUT.HALF.BOT0.TMIN, TCELL28:OUT.HALT.TOP0.TMIN
RXCRCOUT24	output	TCELL31:OUT.HALF.BOT3.TMIN, TCELL31:OUT.HALT.TOP3.TMIN
RXCRCOUT25	output	TCELL31:OUT.HALF.BOT2.TMIN, TCELL31:OUT.HALT.TOP2.TMIN
RXCRCOUT26	output	TCELL31:OUT.HALF.BOT1.TMIN, TCELL31:OUT.HALT.TOP1.TMIN
RXCRCOUT27	output	TCELL31:OUT.HALF.BOT0.TMIN, TCELL31:OUT.HALT.TOP0.TMIN
RXCRCOUT28	output	TCELL30:OUT.HALF.BOT3.TMIN, TCELL30:OUT.HALT.TOP3.TMIN
RXCRCOUT29	output	TCELL30:OUT.HALF.BOT2.TMIN, TCELL30:OUT.HALT.TOP2.TMIN
RXCRCOUT3	output	TCELL25:OUT.HALF.BOT0.TMIN, TCELL25:OUT.HALT.TOP0.TMIN
RXCRCOUT30	output	TCELL30:OUT.HALF.BOT1.TMIN, TCELL30:OUT.HALT.TOP1.TMIN
RXCRCOUT31	output	TCELL30:OUT.HALF.BOT0.TMIN, TCELL30:OUT.HALT.TOP0.TMIN
RXCRCOUT4	output	TCELL24:OUT.HALF.BOT3.TMIN, TCELL24:OUT.HALT.TOP3.TMIN
RXCRCOUT5	output	TCELL24:OUT.HALF.BOT2.TMIN, TCELL24:OUT.HALT.TOP2.TMIN
RXCRCOUT6	output	TCELL24:OUT.HALF.BOT1.TMIN, TCELL24:OUT.HALT.TOP1.TMIN
RXCRCOUT7	output	TCELL24:OUT.HALF.BOT0.TMIN, TCELL24:OUT.HALT.TOP0.TMIN
RXCRCOUT8	output	TCELL27:OUT.HALF.BOT3.TMIN, TCELL27:OUT.HALT.TOP3.TMIN
RXCRCOUT9	output	TCELL27:OUT.HALF.BOT2.TMIN, TCELL27:OUT.HALT.TOP2.TMIN
RXCRCPD	input	TCELL25:IMUX.IMUX12
RXCRCRESET	input	TCELL23:IMUX.SR0
RXCYCLELIMIT	output	TCELL27:OUT.HALF.BOT4.TMIN, TCELL27:OUT.HALT.TOP4.TMIN
RXDATA0	output	TCELL16:OUT.BEST0.TMIN
RXDATA1	output	TCELL16:OUT.BEST1.TMIN
RXDATA10	output	TCELL18:OUT.BEST2.TMIN
RXDATA11	output	TCELL18:OUT.BEST3.TMIN
RXDATA12	output	TCELL19:OUT.BEST0.TMIN
RXDATA13	output	TCELL19:OUT.BEST1.TMIN
RXDATA14	output	TCELL19:OUT.BEST2.TMIN
RXDATA15	output	TCELL19:OUT.BEST3.TMIN
RXDATA16	output	TCELL20:OUT.BEST0.TMIN
RXDATA17	output	TCELL20:OUT.BEST1.TMIN
RXDATA18	output	TCELL20:OUT.BEST2.TMIN
RXDATA19	output	TCELL20:OUT.BEST3.TMIN
RXDATA2	output	TCELL16:OUT.BEST2.TMIN
RXDATA20	output	TCELL21:OUT.BEST0.TMIN
RXDATA21	output	TCELL21:OUT.BEST1.TMIN
RXDATA22	output	TCELL21:OUT.BEST2.TMIN
RXDATA23	output	TCELL21:OUT.BEST3.TMIN
RXDATA24	output	TCELL22:OUT.BEST0.TMIN
RXDATA25	output	TCELL22:OUT.BEST1.TMIN
RXDATA26	output	TCELL22:OUT.BEST2.TMIN
RXDATA27	output	TCELL22:OUT.BEST3.TMIN
RXDATA28	output	TCELL23:OUT.BEST0.TMIN
RXDATA29	output	TCELL23:OUT.BEST1.TMIN
RXDATA3	output	TCELL16:OUT.BEST3.TMIN
RXDATA30	output	TCELL23:OUT.BEST2.TMIN
RXDATA31	output	TCELL23:OUT.BEST3.TMIN
RXDATA32	output	TCELL24:OUT.BEST0.TMIN
RXDATA33	output	TCELL24:OUT.BEST1.TMIN
RXDATA34	output	TCELL24:OUT.BEST2.TMIN
RXDATA35	output	TCELL24:OUT.BEST3.TMIN
RXDATA36	output	TCELL25:OUT.BEST0.TMIN
RXDATA37	output	TCELL25:OUT.BEST1.TMIN
RXDATA38	output	TCELL25:OUT.BEST2.TMIN
RXDATA39	output	TCELL25:OUT.BEST3.TMIN
RXDATA4	output	TCELL17:OUT.BEST0.TMIN
RXDATA40	output	TCELL26:OUT.BEST0.TMIN
RXDATA41	output	TCELL26:OUT.BEST1.TMIN
RXDATA42	output	TCELL26:OUT.BEST2.TMIN
RXDATA43	output	TCELL26:OUT.BEST3.TMIN
RXDATA44	output	TCELL27:OUT.BEST0.TMIN
RXDATA45	output	TCELL27:OUT.BEST1.TMIN
RXDATA46	output	TCELL27:OUT.BEST2.TMIN
RXDATA47	output	TCELL27:OUT.BEST3.TMIN
RXDATA48	output	TCELL28:OUT.BEST0.TMIN
RXDATA49	output	TCELL28:OUT.BEST1.TMIN
RXDATA5	output	TCELL17:OUT.BEST1.TMIN
RXDATA50	output	TCELL28:OUT.BEST2.TMIN
RXDATA51	output	TCELL28:OUT.BEST3.TMIN
RXDATA52	output	TCELL29:OUT.BEST0.TMIN
RXDATA53	output	TCELL29:OUT.BEST1.TMIN
RXDATA54	output	TCELL29:OUT.BEST2.TMIN
RXDATA55	output	TCELL29:OUT.BEST3.TMIN
RXDATA56	output	TCELL30:OUT.BEST0.TMIN
RXDATA57	output	TCELL30:OUT.BEST1.TMIN
RXDATA58	output	TCELL30:OUT.BEST2.TMIN
RXDATA59	output	TCELL30:OUT.BEST3.TMIN
RXDATA6	output	TCELL17:OUT.BEST2.TMIN
RXDATA60	output	TCELL31:OUT.BEST0.TMIN
RXDATA61	output	TCELL31:OUT.BEST1.TMIN
RXDATA62	output	TCELL31:OUT.BEST2.TMIN
RXDATA63	output	TCELL31:OUT.BEST3.TMIN
RXDATA7	output	TCELL17:OUT.BEST3.TMIN
RXDATA8	output	TCELL18:OUT.BEST0.TMIN
RXDATA9	output	TCELL18:OUT.BEST1.TMIN
RXDATAWIDTH0	input	TCELL17:IMUX.IMUX22
RXDATAWIDTH1	input	TCELL17:IMUX.IMUX23
RXDEC64B66BUSE	input	TCELL28:IMUX.IMUX13
RXDEC8B10BUSE	input	TCELL28:IMUX.IMUX12
RXDESCRAM64B66BUSE	input	TCELL19:IMUX.IMUX14
RXDISPERR0	output	TCELL16:OUT.BEST4.TMIN
RXDISPERR1	output	TCELL18:OUT.BEST4.TMIN
RXDISPERR2	output	TCELL20:OUT.BEST4.TMIN
RXDISPERR3	output	TCELL22:OUT.BEST4.TMIN
RXDISPERR4	output	TCELL24:OUT.BEST4.TMIN
RXDISPERR5	output	TCELL26:OUT.BEST4.TMIN
RXDISPERR6	output	TCELL28:OUT.BEST4.TMIN
RXDISPERR7	output	TCELL30:OUT.BEST4.TMIN
RXENABLECAL	output	TCELL31:OUT.SEC1.TMIN
RXFCALSTATE0	output	TCELL30:OUT.HALF.BOT4.TMIN, TCELL30:OUT.HALT.TOP4.TMIN
RXFCALSTATE1	output	TCELL30:OUT.HALF.BOT5.TMIN, TCELL30:OUT.HALT.TOP5.TMIN
RXFCALSTATE2	output	TCELL30:OUT.HALF.BOT6.TMIN, TCELL30:OUT.HALT.TOP6.TMIN
RXFDETSTATE0	output	TCELL29:OUT.SEC0.TMIN
RXFDETSTATE1	output	TCELL29:OUT.SEC1.TMIN
RXFDETSTATE2	output	TCELL29:OUT.SEC2.TMIN
RXIGNOREBTF	input	TCELL28:IMUX.IMUX15
RXINTDATAWIDTH0	input	TCELL17:IMUX.IMUX18
RXINTDATAWIDTH1	input	TCELL17:IMUX.IMUX19
RXLOCK	output	TCELL31:OUT.HALF.BOT4.TMIN, TCELL31:OUT.HALT.TOP4.TMIN
RXLOCKUPDATE	output	TCELL31:OUT.HALF.BOT6.TMIN, TCELL31:OUT.HALT.TOP6.TMIN
RXLOSSOFSYNC0	output	TCELL17:OUT.BEST4.TMIN
RXLOSSOFSYNC1	output	TCELL17:OUT.BEST5.TMIN
RXNOTINTABLE0	output	TCELL16:OUT.BEST5.TMIN
RXNOTINTABLE1	output	TCELL18:OUT.BEST5.TMIN
RXNOTINTABLE2	output	TCELL20:OUT.BEST5.TMIN
RXNOTINTABLE3	output	TCELL22:OUT.BEST5.TMIN
RXNOTINTABLE4	output	TCELL24:OUT.BEST5.TMIN
RXNOTINTABLE5	output	TCELL26:OUT.BEST5.TMIN
RXNOTINTABLE6	output	TCELL28:OUT.BEST5.TMIN
RXNOTINTABLE7	output	TCELL30:OUT.BEST5.TMIN
RXPMARESET	input	TCELL25:IMUX.SR0
RXPOLARITY	input	TCELL31:IMUX.IMUX14
RXREALIGN	output	TCELL25:OUT.BEST4.TMIN
RXRECCLK1	output	TCELL23:OUT.BEST4.TMIN
RXRECCLK2	output	TCELL23:OUT.BEST5.TMIN
RXRESET	input	TCELL16:IMUX.SR0
RXRUNDISP0	output	TCELL16:OUT.SEC0.TMIN
RXRUNDISP1	output	TCELL18:OUT.SEC0.TMIN
RXRUNDISP2	output	TCELL20:OUT.SEC0.TMIN
RXRUNDISP3	output	TCELL22:OUT.SEC0.TMIN
RXRUNDISP4	output	TCELL24:OUT.SEC0.TMIN
RXRUNDISP5	output	TCELL26:OUT.SEC0.TMIN
RXRUNDISP6	output	TCELL28:OUT.SEC0.TMIN
RXRUNDISP7	output	TCELL30:OUT.SEC0.TMIN
RXSIGDET	output	TCELL17:OUT.BEST6.TMIN
RXSLIDE	input	TCELL19:IMUX.IMUX17
RXSTATUS0	output	TCELL31:OUT.BEST4.TMIN
RXSTATUS1	output	TCELL31:OUT.BEST5.TMIN
RXSTATUS2	output	TCELL31:OUT.BEST6.TMIN
RXSTATUS3	output	TCELL29:OUT.HALF.BOT5.TMIN, TCELL29:OUT.HALT.TOP5.TMIN
RXSTATUS4	output	TCELL29:OUT.HALF.BOT6.TMIN, TCELL29:OUT.HALT.TOP6.TMIN
RXSTATUS5	output	TCELL29:OUT.BEST4.TMIN
RXSYNC	input	TCELL18:IMUX.IMUX14
RXUSRCLK	input	TCELL22:IMUX.CLK0
RXUSRCLK2	input	TCELL22:IMUX.CLK1
RXUSRLOCK	input	TCELL26:IMUX.IMUX12
RXUSRVCOCAL	input	TCELL26:IMUX.IMUX13
RXUSRVCODAC0	input	TCELL16:IMUX.IMUX12
RXUSRVCODAC1	input	TCELL16:IMUX.IMUX13
RXUSRVCODAC2	input	TCELL16:IMUX.IMUX14
RXUSRVCODAC3	input	TCELL16:IMUX.IMUX15
RXUSRVCODAC4	input	TCELL17:IMUX.IMUX12
RXUSRVCODAC5	input	TCELL17:IMUX.IMUX13
RXUSRVCODAC6	input	TCELL17:IMUX.IMUX14
RXUSRVCODAC7	input	TCELL17:IMUX.IMUX15
RXUSRVCODAC8	input	TCELL18:IMUX.IMUX12
RXUSRVCODAC9	input	TCELL18:IMUX.IMUX13
RXVCOHIGH	output	TCELL19:OUT.BEST4.TMIN
SCANEN0	input	TCELL30:IMUX.CE0
SCANEN1	input	TCELL30:IMUX.CE1
SCANEN2	input	TCELL28:IMUX.CE0
SCANIN0	input	TCELL31:IMUX.IMUX19
SCANIN1	input	TCELL31:IMUX.IMUX20
SCANIN2	input	TCELL31:IMUX.IMUX21
SCANMODE0	input	TCELL29:IMUX.CE0
SCANMODE1	input	TCELL29:IMUX.CE1
SCANMODE2	input	TCELL28:IMUX.CE1
SCANOUT0	output	TCELL29:OUT.BEST6.TMIN
SCANOUT1	output	TCELL29:OUT.BEST7.TMIN
SCANOUT2	output	TCELL27:OUT.SEC1.TMIN
TESTMEMORY	input	TCELL28:IMUX.IMUX14
TXADCN	output	TCELL22:OUT.HALF.BOT6.TMIN, TCELL22:OUT.HALT.TOP6.TMIN
TXADCP	output	TCELL23:OUT.SEC1.TMIN
TXBUFERR	output	TCELL29:OUT.BEST5.TMIN
TXBYPASS8B10B0	input	TCELL16:IMUX.IMUX16
TXBYPASS8B10B1	input	TCELL18:IMUX.IMUX16
TXBYPASS8B10B2	input	TCELL20:IMUX.IMUX16
TXBYPASS8B10B3	input	TCELL22:IMUX.IMUX16
TXBYPASS8B10B4	input	TCELL24:IMUX.IMUX16
TXBYPASS8B10B5	input	TCELL26:IMUX.IMUX16
TXBYPASS8B10B6	input	TCELL28:IMUX.IMUX16
TXBYPASS8B10B7	input	TCELL30:IMUX.IMUX16
TXCALFAIL	output	TCELL19:OUT.BEST7.TMIN
TXCHARDISPMODE0	input	TCELL16:IMUX.IMUX18
TXCHARDISPMODE1	input	TCELL18:IMUX.IMUX18
TXCHARDISPMODE2	input	TCELL20:IMUX.IMUX18
TXCHARDISPMODE3	input	TCELL22:IMUX.IMUX18
TXCHARDISPMODE4	input	TCELL24:IMUX.IMUX18
TXCHARDISPMODE5	input	TCELL26:IMUX.IMUX18
TXCHARDISPMODE6	input	TCELL28:IMUX.IMUX18
TXCHARDISPMODE7	input	TCELL30:IMUX.IMUX18
TXCHARDISPVAL0	input	TCELL16:IMUX.IMUX19
TXCHARDISPVAL1	input	TCELL18:IMUX.IMUX19
TXCHARDISPVAL2	input	TCELL20:IMUX.IMUX19
TXCHARDISPVAL3	input	TCELL22:IMUX.IMUX19
TXCHARDISPVAL4	input	TCELL24:IMUX.IMUX19
TXCHARDISPVAL5	input	TCELL26:IMUX.IMUX19
TXCHARDISPVAL6	input	TCELL28:IMUX.IMUX19
TXCHARDISPVAL7	input	TCELL30:IMUX.IMUX19
TXCHARISK0	input	TCELL16:IMUX.IMUX17
TXCHARISK1	input	TCELL18:IMUX.IMUX17
TXCHARISK2	input	TCELL20:IMUX.IMUX17
TXCHARISK3	input	TCELL22:IMUX.IMUX17
TXCHARISK4	input	TCELL24:IMUX.IMUX17
TXCHARISK5	input	TCELL26:IMUX.IMUX17
TXCHARISK6	input	TCELL28:IMUX.IMUX17
TXCHARISK7	input	TCELL30:IMUX.IMUX17
TXCLKSTABLE	input	TCELL19:IMUX.IMUX18
TXCOARSEST	output	TCELL28:OUT.HALF.BOT4.TMIN, TCELL28:OUT.HALT.TOP4.TMIN
TXCRCCLK	input	TCELL24:IMUX.CLK0
TXCRCDATAVALID	input	TCELL23:IMUX.CE1
TXCRCDATAWIDTH0	input	TCELL27:IMUX.IMUX20
TXCRCDATAWIDTH1	input	TCELL27:IMUX.IMUX21
TXCRCDATAWIDTH2	input	TCELL27:IMUX.IMUX22
TXCRCIN0	input	TCELL17:IMUX.IMUX7
TXCRCIN1	input	TCELL17:IMUX.IMUX6
TXCRCIN10	input	TCELL19:IMUX.IMUX5
TXCRCIN11	input	TCELL19:IMUX.IMUX4
TXCRCIN12	input	TCELL18:IMUX.IMUX7
TXCRCIN13	input	TCELL18:IMUX.IMUX6
TXCRCIN14	input	TCELL18:IMUX.IMUX5
TXCRCIN15	input	TCELL18:IMUX.IMUX4
TXCRCIN16	input	TCELL21:IMUX.IMUX7
TXCRCIN17	input	TCELL21:IMUX.IMUX6
TXCRCIN18	input	TCELL21:IMUX.IMUX5
TXCRCIN19	input	TCELL21:IMUX.IMUX4
TXCRCIN2	input	TCELL17:IMUX.IMUX5
TXCRCIN20	input	TCELL20:IMUX.IMUX7
TXCRCIN21	input	TCELL20:IMUX.IMUX6
TXCRCIN22	input	TCELL20:IMUX.IMUX5
TXCRCIN23	input	TCELL20:IMUX.IMUX4
TXCRCIN24	input	TCELL23:IMUX.IMUX7
TXCRCIN25	input	TCELL23:IMUX.IMUX6
TXCRCIN26	input	TCELL23:IMUX.IMUX5
TXCRCIN27	input	TCELL23:IMUX.IMUX4
TXCRCIN28	input	TCELL22:IMUX.IMUX7
TXCRCIN29	input	TCELL22:IMUX.IMUX6
TXCRCIN3	input	TCELL17:IMUX.IMUX4
TXCRCIN30	input	TCELL22:IMUX.IMUX5
TXCRCIN31	input	TCELL22:IMUX.IMUX4
TXCRCIN32	input	TCELL25:IMUX.IMUX7
TXCRCIN33	input	TCELL25:IMUX.IMUX6
TXCRCIN34	input	TCELL25:IMUX.IMUX5
TXCRCIN35	input	TCELL25:IMUX.IMUX4
TXCRCIN36	input	TCELL24:IMUX.IMUX7
TXCRCIN37	input	TCELL24:IMUX.IMUX6
TXCRCIN38	input	TCELL24:IMUX.IMUX5
TXCRCIN39	input	TCELL24:IMUX.IMUX4
TXCRCIN4	input	TCELL16:IMUX.IMUX7
TXCRCIN40	input	TCELL27:IMUX.IMUX7
TXCRCIN41	input	TCELL27:IMUX.IMUX6
TXCRCIN42	input	TCELL27:IMUX.IMUX5
TXCRCIN43	input	TCELL27:IMUX.IMUX4
TXCRCIN44	input	TCELL26:IMUX.IMUX7
TXCRCIN45	input	TCELL26:IMUX.IMUX6
TXCRCIN46	input	TCELL26:IMUX.IMUX5
TXCRCIN47	input	TCELL26:IMUX.IMUX4
TXCRCIN48	input	TCELL29:IMUX.IMUX7
TXCRCIN49	input	TCELL29:IMUX.IMUX6
TXCRCIN5	input	TCELL16:IMUX.IMUX6
TXCRCIN50	input	TCELL29:IMUX.IMUX5
TXCRCIN51	input	TCELL29:IMUX.IMUX4
TXCRCIN52	input	TCELL28:IMUX.IMUX7
TXCRCIN53	input	TCELL28:IMUX.IMUX6
TXCRCIN54	input	TCELL28:IMUX.IMUX5
TXCRCIN55	input	TCELL28:IMUX.IMUX4
TXCRCIN56	input	TCELL31:IMUX.IMUX7
TXCRCIN57	input	TCELL31:IMUX.IMUX6
TXCRCIN58	input	TCELL31:IMUX.IMUX5
TXCRCIN59	input	TCELL31:IMUX.IMUX4
TXCRCIN6	input	TCELL16:IMUX.IMUX5
TXCRCIN60	input	TCELL30:IMUX.IMUX7
TXCRCIN61	input	TCELL30:IMUX.IMUX6
TXCRCIN62	input	TCELL30:IMUX.IMUX5
TXCRCIN63	input	TCELL30:IMUX.IMUX4
TXCRCIN7	input	TCELL16:IMUX.IMUX4
TXCRCIN8	input	TCELL19:IMUX.IMUX7
TXCRCIN9	input	TCELL19:IMUX.IMUX6
TXCRCINIT	input	TCELL21:IMUX.IMUX17
TXCRCINTCLK	input	TCELL23:IMUX.CLK1
TXCRCOUT0	output	TCELL17:OUT.HALF.BOT3.TMIN, TCELL17:OUT.HALT.TOP3.TMIN
TXCRCOUT1	output	TCELL17:OUT.HALF.BOT2.TMIN, TCELL17:OUT.HALT.TOP2.TMIN
TXCRCOUT10	output	TCELL19:OUT.HALF.BOT1.TMIN, TCELL19:OUT.HALT.TOP1.TMIN
TXCRCOUT11	output	TCELL19:OUT.HALF.BOT0.TMIN, TCELL19:OUT.HALT.TOP0.TMIN
TXCRCOUT12	output	TCELL18:OUT.HALF.BOT3.TMIN, TCELL18:OUT.HALT.TOP3.TMIN
TXCRCOUT13	output	TCELL18:OUT.HALF.BOT2.TMIN, TCELL18:OUT.HALT.TOP2.TMIN
TXCRCOUT14	output	TCELL18:OUT.HALF.BOT1.TMIN, TCELL18:OUT.HALT.TOP1.TMIN
TXCRCOUT15	output	TCELL18:OUT.HALF.BOT0.TMIN, TCELL18:OUT.HALT.TOP0.TMIN
TXCRCOUT16	output	TCELL21:OUT.HALF.BOT3.TMIN, TCELL21:OUT.HALT.TOP3.TMIN
TXCRCOUT17	output	TCELL21:OUT.HALF.BOT2.TMIN, TCELL21:OUT.HALT.TOP2.TMIN
TXCRCOUT18	output	TCELL21:OUT.HALF.BOT1.TMIN, TCELL21:OUT.HALT.TOP1.TMIN
TXCRCOUT19	output	TCELL21:OUT.HALF.BOT0.TMIN, TCELL21:OUT.HALT.TOP0.TMIN
TXCRCOUT2	output	TCELL17:OUT.HALF.BOT1.TMIN, TCELL17:OUT.HALT.TOP1.TMIN
TXCRCOUT20	output	TCELL20:OUT.HALF.BOT3.TMIN, TCELL20:OUT.HALT.TOP3.TMIN
TXCRCOUT21	output	TCELL20:OUT.HALF.BOT2.TMIN, TCELL20:OUT.HALT.TOP2.TMIN
TXCRCOUT22	output	TCELL20:OUT.HALF.BOT1.TMIN, TCELL20:OUT.HALT.TOP1.TMIN
TXCRCOUT23	output	TCELL20:OUT.HALF.BOT0.TMIN, TCELL20:OUT.HALT.TOP0.TMIN
TXCRCOUT24	output	TCELL23:OUT.HALF.BOT3.TMIN, TCELL23:OUT.HALT.TOP3.TMIN
TXCRCOUT25	output	TCELL23:OUT.HALF.BOT2.TMIN, TCELL23:OUT.HALT.TOP2.TMIN
TXCRCOUT26	output	TCELL23:OUT.HALF.BOT1.TMIN, TCELL23:OUT.HALT.TOP1.TMIN
TXCRCOUT27	output	TCELL23:OUT.HALF.BOT0.TMIN, TCELL23:OUT.HALT.TOP0.TMIN
TXCRCOUT28	output	TCELL22:OUT.HALF.BOT3.TMIN, TCELL22:OUT.HALT.TOP3.TMIN
TXCRCOUT29	output	TCELL22:OUT.HALF.BOT2.TMIN, TCELL22:OUT.HALT.TOP2.TMIN
TXCRCOUT3	output	TCELL17:OUT.HALF.BOT0.TMIN, TCELL17:OUT.HALT.TOP0.TMIN
TXCRCOUT30	output	TCELL22:OUT.HALF.BOT1.TMIN, TCELL22:OUT.HALT.TOP1.TMIN
TXCRCOUT31	output	TCELL22:OUT.HALF.BOT0.TMIN, TCELL22:OUT.HALT.TOP0.TMIN
TXCRCOUT4	output	TCELL16:OUT.HALF.BOT3.TMIN, TCELL16:OUT.HALT.TOP3.TMIN
TXCRCOUT5	output	TCELL16:OUT.HALF.BOT2.TMIN, TCELL16:OUT.HALT.TOP2.TMIN
TXCRCOUT6	output	TCELL16:OUT.HALF.BOT1.TMIN, TCELL16:OUT.HALT.TOP1.TMIN
TXCRCOUT7	output	TCELL16:OUT.HALF.BOT0.TMIN, TCELL16:OUT.HALT.TOP0.TMIN
TXCRCOUT8	output	TCELL19:OUT.HALF.BOT3.TMIN, TCELL19:OUT.HALT.TOP3.TMIN
TXCRCOUT9	output	TCELL19:OUT.HALF.BOT2.TMIN, TCELL19:OUT.HALT.TOP2.TMIN
TXCRCPD	input	TCELL25:IMUX.IMUX13
TXCRCRESET	input	TCELL24:IMUX.SR0
TXCYCLELIMIT	output	TCELL29:OUT.HALF.BOT4.TMIN, TCELL29:OUT.HALT.TOP4.TMIN
TXDATA0	input	TCELL16:IMUX.IMUX0
TXDATA1	input	TCELL16:IMUX.IMUX1
TXDATA10	input	TCELL18:IMUX.IMUX2
TXDATA11	input	TCELL18:IMUX.IMUX3
TXDATA12	input	TCELL19:IMUX.IMUX0
TXDATA13	input	TCELL19:IMUX.IMUX1
TXDATA14	input	TCELL19:IMUX.IMUX2
TXDATA15	input	TCELL19:IMUX.IMUX3
TXDATA16	input	TCELL20:IMUX.IMUX0
TXDATA17	input	TCELL20:IMUX.IMUX1
TXDATA18	input	TCELL20:IMUX.IMUX2
TXDATA19	input	TCELL20:IMUX.IMUX3
TXDATA2	input	TCELL16:IMUX.IMUX2
TXDATA20	input	TCELL21:IMUX.IMUX0
TXDATA21	input	TCELL21:IMUX.IMUX1
TXDATA22	input	TCELL21:IMUX.IMUX2
TXDATA23	input	TCELL21:IMUX.IMUX3
TXDATA24	input	TCELL22:IMUX.IMUX0
TXDATA25	input	TCELL22:IMUX.IMUX1
TXDATA26	input	TCELL22:IMUX.IMUX2
TXDATA27	input	TCELL22:IMUX.IMUX3
TXDATA28	input	TCELL23:IMUX.IMUX0
TXDATA29	input	TCELL23:IMUX.IMUX1
TXDATA3	input	TCELL16:IMUX.IMUX3
TXDATA30	input	TCELL23:IMUX.IMUX2
TXDATA31	input	TCELL23:IMUX.IMUX3
TXDATA32	input	TCELL24:IMUX.IMUX0
TXDATA33	input	TCELL24:IMUX.IMUX1
TXDATA34	input	TCELL24:IMUX.IMUX2
TXDATA35	input	TCELL24:IMUX.IMUX3
TXDATA36	input	TCELL25:IMUX.IMUX0
TXDATA37	input	TCELL25:IMUX.IMUX1
TXDATA38	input	TCELL25:IMUX.IMUX2
TXDATA39	input	TCELL25:IMUX.IMUX3
TXDATA4	input	TCELL17:IMUX.IMUX0
TXDATA40	input	TCELL26:IMUX.IMUX0
TXDATA41	input	TCELL26:IMUX.IMUX1
TXDATA42	input	TCELL26:IMUX.IMUX2
TXDATA43	input	TCELL26:IMUX.IMUX3
TXDATA44	input	TCELL27:IMUX.IMUX0
TXDATA45	input	TCELL27:IMUX.IMUX1
TXDATA46	input	TCELL27:IMUX.IMUX2
TXDATA47	input	TCELL27:IMUX.IMUX3
TXDATA48	input	TCELL28:IMUX.IMUX0
TXDATA49	input	TCELL28:IMUX.IMUX1
TXDATA5	input	TCELL17:IMUX.IMUX1
TXDATA50	input	TCELL28:IMUX.IMUX2
TXDATA51	input	TCELL28:IMUX.IMUX3
TXDATA52	input	TCELL29:IMUX.IMUX0
TXDATA53	input	TCELL29:IMUX.IMUX1
TXDATA54	input	TCELL29:IMUX.IMUX2
TXDATA55	input	TCELL29:IMUX.IMUX3
TXDATA56	input	TCELL30:IMUX.IMUX0
TXDATA57	input	TCELL30:IMUX.IMUX1
TXDATA58	input	TCELL30:IMUX.IMUX2
TXDATA59	input	TCELL30:IMUX.IMUX3
TXDATA6	input	TCELL17:IMUX.IMUX2
TXDATA60	input	TCELL31:IMUX.IMUX0
TXDATA61	input	TCELL31:IMUX.IMUX1
TXDATA62	input	TCELL31:IMUX.IMUX2
TXDATA63	input	TCELL31:IMUX.IMUX3
TXDATA7	input	TCELL17:IMUX.IMUX3
TXDATA8	input	TCELL18:IMUX.IMUX0
TXDATA9	input	TCELL18:IMUX.IMUX1
TXDATAWIDTH0	input	TCELL17:IMUX.IMUX20
TXDATAWIDTH1	input	TCELL17:IMUX.IMUX21
TXENABLECAL	output	TCELL28:OUT.HALF.BOT5.TMIN, TCELL28:OUT.HALT.TOP5.TMIN
TXENC64B66BUSE	input	TCELL30:IMUX.IMUX13
TXENC8B10BUSE	input	TCELL30:IMUX.IMUX12
TXENOOB	input	TCELL21:IMUX.IMUX18
TXFCALSTATE0	output	TCELL26:OUT.HALF.BOT4.TMIN, TCELL26:OUT.HALT.TOP4.TMIN
TXFCALSTATE1	output	TCELL26:OUT.HALF.BOT5.TMIN, TCELL26:OUT.HALT.TOP5.TMIN
TXFCALSTATE2	output	TCELL26:OUT.HALF.BOT6.TMIN, TCELL26:OUT.HALT.TOP6.TMIN
TXFDETSTATE0	output	TCELL25:OUT.SEC0.TMIN
TXFDETSTATE1	output	TCELL25:OUT.SEC1.TMIN
TXFDETSTATE2	output	TCELL25:OUT.SEC2.TMIN
TXGEARBOX64B66BUSE	input	TCELL30:IMUX.IMUX15
TXINHIBIT	input	TCELL31:IMUX.IMUX18
TXINTDATAWIDTH0	input	TCELL17:IMUX.IMUX16
TXINTDATAWIDTH1	input	TCELL17:IMUX.IMUX17
TXKERR0	output	TCELL16:OUT.SEC2.TMIN
TXKERR1	output	TCELL18:OUT.SEC2.TMIN
TXKERR2	output	TCELL20:OUT.SEC2.TMIN
TXKERR3	output	TCELL22:OUT.SEC2.TMIN
TXKERR4	output	TCELL24:OUT.SEC2.TMIN
TXKERR5	output	TCELL26:OUT.SEC2.TMIN
TXKERR6	output	TCELL28:OUT.SEC2.TMIN
TXKERR7	output	TCELL30:OUT.SEC2.TMIN
TXLOCK	output	TCELL31:OUT.HALF.BOT5.TMIN, TCELL31:OUT.HALT.TOP5.TMIN
TXLOCKUPDATE	output	TCELL31:OUT.HALF.BOT7.TMIN, TCELL31:OUT.HALT.TOP7.TMIN
TXOUTCLK1	output	TCELL23:OUT.BEST6.TMIN
TXOUTCLK2	output	TCELL23:OUT.BEST7.TMIN
TXPMARESET	input	TCELL26:IMUX.SR0
TXPOLARITY	input	TCELL31:IMUX.IMUX17
TXRESET	input	TCELL17:IMUX.SR0
TXRUNDISP0	output	TCELL16:OUT.SEC1.TMIN
TXRUNDISP1	output	TCELL18:OUT.SEC1.TMIN
TXRUNDISP2	output	TCELL20:OUT.SEC1.TMIN
TXRUNDISP3	output	TCELL22:OUT.SEC1.TMIN
TXRUNDISP4	output	TCELL24:OUT.SEC1.TMIN
TXRUNDISP5	output	TCELL26:OUT.SEC1.TMIN
TXRUNDISP6	output	TCELL28:OUT.SEC1.TMIN
TXRUNDISP7	output	TCELL30:OUT.SEC1.TMIN
TXSCRAM64B66BUSE	input	TCELL30:IMUX.IMUX14
TXSYNC	input	TCELL27:IMUX.IMUX12
TXUSRCLK	input	TCELL22:IMUX.CLK2
TXUSRCLK2	input	TCELL22:IMUX.CLK3
TXUSRLOCK	input	TCELL26:IMUX.IMUX14
TXUSRVCOCAL	input	TCELL26:IMUX.IMUX15
TXUSRVCODAC0	input	TCELL20:IMUX.IMUX12
TXUSRVCODAC1	input	TCELL20:IMUX.IMUX13
TXUSRVCODAC2	input	TCELL20:IMUX.IMUX14
TXUSRVCODAC3	input	TCELL20:IMUX.IMUX15
TXUSRVCODAC4	input	TCELL21:IMUX.IMUX12
TXUSRVCODAC5	input	TCELL21:IMUX.IMUX13
TXUSRVCODAC6	input	TCELL21:IMUX.IMUX14
TXUSRVCODAC7	input	TCELL21:IMUX.IMUX15
TXUSRVCODAC8	input	TCELL22:IMUX.IMUX20
TXUSRVCODAC9	input	TCELL22:IMUX.IMUX21
TXVCOHIGH	output	TCELL19:OUT.BEST5.TMIN

Bel GT11CLK

virtex4 MGT bel GT11CLK
Pin	Direction	Wires

Bel IPAD_CLKP0

virtex4 MGT bel IPAD_CLKP0
Pin	Direction	Wires

Bel IPAD_CLKN0

virtex4 MGT bel IPAD_CLKN0
Pin	Direction	Wires

Bel IPAD_RXP0

virtex4 MGT bel IPAD_RXP0
Pin	Direction	Wires

Bel IPAD_RXN0

virtex4 MGT bel IPAD_RXN0
Pin	Direction	Wires

Bel IPAD_RXP1

virtex4 MGT bel IPAD_RXP1
Pin	Direction	Wires

Bel IPAD_RXN1

virtex4 MGT bel IPAD_RXN1
Pin	Direction	Wires

Bel OPAD_TXP0

virtex4 MGT bel OPAD_TXP0
Pin	Direction	Wires

Bel OPAD_TXN0

virtex4 MGT bel OPAD_TXN0
Pin	Direction	Wires

Bel OPAD_TXP1

virtex4 MGT bel OPAD_TXP1
Pin	Direction	Wires

Bel OPAD_TXN1

virtex4 MGT bel OPAD_TXN1
Pin	Direction	Wires

Bel wires

virtex4 MGT bel wires
Wire	Pins
TCELL0:IMUX.SR0	GT11_0.RXRESET
TCELL0:IMUX.IMUX0	GT11_0.TXDATA0
TCELL0:IMUX.IMUX1	GT11_0.TXDATA1
TCELL0:IMUX.IMUX2	GT11_0.TXDATA2
TCELL0:IMUX.IMUX3	GT11_0.TXDATA3
TCELL0:IMUX.IMUX4	GT11_0.TXCRCIN7
TCELL0:IMUX.IMUX5	GT11_0.TXCRCIN6
TCELL0:IMUX.IMUX6	GT11_0.TXCRCIN5
TCELL0:IMUX.IMUX7	GT11_0.TXCRCIN4
TCELL0:IMUX.IMUX8	GT11_0.RXCRCIN7
TCELL0:IMUX.IMUX9	GT11_0.RXCRCIN6
TCELL0:IMUX.IMUX10	GT11_0.RXCRCIN5
TCELL0:IMUX.IMUX11	GT11_0.RXCRCIN4
TCELL0:IMUX.IMUX12	GT11_0.RXUSRVCODAC0
TCELL0:IMUX.IMUX13	GT11_0.RXUSRVCODAC1
TCELL0:IMUX.IMUX14	GT11_0.RXUSRVCODAC2
TCELL0:IMUX.IMUX15	GT11_0.RXUSRVCODAC3
TCELL0:IMUX.IMUX16	GT11_0.TXBYPASS8B10B0
TCELL0:IMUX.IMUX17	GT11_0.TXCHARISK0
TCELL0:IMUX.IMUX18	GT11_0.TXCHARDISPMODE0
TCELL0:IMUX.IMUX19	GT11_0.TXCHARDISPVAL0
TCELL0:OUT.BEST0.TMIN	GT11_0.RXDATA0
TCELL0:OUT.BEST1.TMIN	GT11_0.RXDATA1
TCELL0:OUT.BEST2.TMIN	GT11_0.RXDATA2
TCELL0:OUT.BEST3.TMIN	GT11_0.RXDATA3
TCELL0:OUT.BEST4.TMIN	GT11_0.RXDISPERR0
TCELL0:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE0
TCELL0:OUT.BEST6.TMIN	GT11_0.RXCHARISK0
TCELL0:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA0
TCELL0:OUT.SEC0.TMIN	GT11_0.RXRUNDISP0
TCELL0:OUT.SEC1.TMIN	GT11_0.TXRUNDISP0
TCELL0:OUT.SEC2.TMIN	GT11_0.TXKERR0
TCELL0:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT7
TCELL0:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT6
TCELL0:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT5
TCELL0:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT4
TCELL0:OUT.HALF.BOT4.TMIN	GT11_0.RXADCN
TCELL0:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT7
TCELL0:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT6
TCELL0:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT5
TCELL0:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT4
TCELL0:OUT.HALT.TOP4.TMIN	GT11_0.RXADCN
TCELL1:IMUX.SR0	GT11_0.TXRESET
TCELL1:IMUX.IMUX0	GT11_0.TXDATA4
TCELL1:IMUX.IMUX1	GT11_0.TXDATA5
TCELL1:IMUX.IMUX2	GT11_0.TXDATA6
TCELL1:IMUX.IMUX3	GT11_0.TXDATA7
TCELL1:IMUX.IMUX4	GT11_0.TXCRCIN3
TCELL1:IMUX.IMUX5	GT11_0.TXCRCIN2
TCELL1:IMUX.IMUX6	GT11_0.TXCRCIN1
TCELL1:IMUX.IMUX7	GT11_0.TXCRCIN0
TCELL1:IMUX.IMUX8	GT11_0.RXCRCIN3
TCELL1:IMUX.IMUX9	GT11_0.RXCRCIN2
TCELL1:IMUX.IMUX10	GT11_0.RXCRCIN1
TCELL1:IMUX.IMUX11	GT11_0.RXCRCIN0
TCELL1:IMUX.IMUX12	GT11_0.RXUSRVCODAC4
TCELL1:IMUX.IMUX13	GT11_0.RXUSRVCODAC5
TCELL1:IMUX.IMUX14	GT11_0.RXUSRVCODAC6
TCELL1:IMUX.IMUX15	GT11_0.RXUSRVCODAC7
TCELL1:IMUX.IMUX16	GT11_0.TXINTDATAWIDTH0
TCELL1:IMUX.IMUX17	GT11_0.TXINTDATAWIDTH1
TCELL1:IMUX.IMUX18	GT11_0.RXINTDATAWIDTH0
TCELL1:IMUX.IMUX19	GT11_0.RXINTDATAWIDTH1
TCELL1:IMUX.IMUX20	GT11_0.TXDATAWIDTH0
TCELL1:IMUX.IMUX21	GT11_0.TXDATAWIDTH1
TCELL1:IMUX.IMUX22	GT11_0.RXDATAWIDTH0
TCELL1:IMUX.IMUX23	GT11_0.RXDATAWIDTH1
TCELL1:OUT.BEST0.TMIN	GT11_0.RXDATA4
TCELL1:OUT.BEST1.TMIN	GT11_0.RXDATA5
TCELL1:OUT.BEST2.TMIN	GT11_0.RXDATA6
TCELL1:OUT.BEST3.TMIN	GT11_0.RXDATA7
TCELL1:OUT.BEST4.TMIN	GT11_0.RXLOSSOFSYNC0
TCELL1:OUT.BEST5.TMIN	GT11_0.RXLOSSOFSYNC1
TCELL1:OUT.BEST6.TMIN	GT11_0.RXSIGDET
TCELL1:OUT.BEST7.TMIN	GT11_0.RXADCP
TCELL1:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT3
TCELL1:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT2
TCELL1:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT1
TCELL1:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT0
TCELL1:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS0
TCELL1:OUT.HALF.BOT5.TMIN	GT11_0.CDRSTATUS1
TCELL1:OUT.HALF.BOT6.TMIN	GT11_0.CDRSTATUS2
TCELL1:OUT.HALF.BOT7.TMIN	GT11_0.CDRSTATUS3
TCELL1:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT3
TCELL1:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT2
TCELL1:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT1
TCELL1:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT0
TCELL1:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS0
TCELL1:OUT.HALT.TOP5.TMIN	GT11_0.CDRSTATUS1
TCELL1:OUT.HALT.TOP6.TMIN	GT11_0.CDRSTATUS2
TCELL1:OUT.HALT.TOP7.TMIN	GT11_0.CDRSTATUS3
TCELL2:IMUX.IMUX0	GT11_0.TXDATA8
TCELL2:IMUX.IMUX1	GT11_0.TXDATA9
TCELL2:IMUX.IMUX2	GT11_0.TXDATA10
TCELL2:IMUX.IMUX3	GT11_0.TXDATA11
TCELL2:IMUX.IMUX4	GT11_0.TXCRCIN15
TCELL2:IMUX.IMUX5	GT11_0.TXCRCIN14
TCELL2:IMUX.IMUX6	GT11_0.TXCRCIN13
TCELL2:IMUX.IMUX7	GT11_0.TXCRCIN12
TCELL2:IMUX.IMUX8	GT11_0.RXCRCIN15
TCELL2:IMUX.IMUX9	GT11_0.RXCRCIN14
TCELL2:IMUX.IMUX10	GT11_0.RXCRCIN13
TCELL2:IMUX.IMUX11	GT11_0.RXCRCIN12
TCELL2:IMUX.IMUX12	GT11_0.RXUSRVCODAC8
TCELL2:IMUX.IMUX13	GT11_0.RXUSRVCODAC9
TCELL2:IMUX.IMUX14	GT11_0.RXSYNC
TCELL2:IMUX.IMUX16	GT11_0.TXBYPASS8B10B1
TCELL2:IMUX.IMUX17	GT11_0.TXCHARISK1
TCELL2:IMUX.IMUX18	GT11_0.TXCHARDISPMODE1
TCELL2:IMUX.IMUX19	GT11_0.TXCHARDISPVAL1
TCELL2:OUT.BEST0.TMIN	GT11_0.RXDATA8
TCELL2:OUT.BEST1.TMIN	GT11_0.RXDATA9
TCELL2:OUT.BEST2.TMIN	GT11_0.RXDATA10
TCELL2:OUT.BEST3.TMIN	GT11_0.RXDATA11
TCELL2:OUT.BEST4.TMIN	GT11_0.RXDISPERR1
TCELL2:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE1
TCELL2:OUT.BEST6.TMIN	GT11_0.RXCHARISK1
TCELL2:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA1
TCELL2:OUT.SEC0.TMIN	GT11_0.RXRUNDISP1
TCELL2:OUT.SEC1.TMIN	GT11_0.TXRUNDISP1
TCELL2:OUT.SEC2.TMIN	GT11_0.TXKERR1
TCELL2:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT15
TCELL2:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT14
TCELL2:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT13
TCELL2:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT12
TCELL2:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS4
TCELL2:OUT.HALF.BOT5.TMIN	GT11_0.CDRSTATUS5
TCELL2:OUT.HALF.BOT6.TMIN	GT11_0.CDRSTATUS6
TCELL2:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT15
TCELL2:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT14
TCELL2:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT13
TCELL2:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT12
TCELL2:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS4
TCELL2:OUT.HALT.TOP5.TMIN	GT11_0.CDRSTATUS5
TCELL2:OUT.HALT.TOP6.TMIN	GT11_0.CDRSTATUS6
TCELL3:IMUX.IMUX0	GT11_0.TXDATA12
TCELL3:IMUX.IMUX1	GT11_0.TXDATA13
TCELL3:IMUX.IMUX2	GT11_0.TXDATA14
TCELL3:IMUX.IMUX3	GT11_0.TXDATA15
TCELL3:IMUX.IMUX4	GT11_0.TXCRCIN11
TCELL3:IMUX.IMUX5	GT11_0.TXCRCIN10
TCELL3:IMUX.IMUX6	GT11_0.TXCRCIN9
TCELL3:IMUX.IMUX7	GT11_0.TXCRCIN8
TCELL3:IMUX.IMUX8	GT11_0.RXCRCIN11
TCELL3:IMUX.IMUX9	GT11_0.RXCRCIN10
TCELL3:IMUX.IMUX10	GT11_0.RXCRCIN9
TCELL3:IMUX.IMUX11	GT11_0.RXCRCIN8
TCELL3:IMUX.IMUX12	GT11_0.ENPCOMMAALIGN
TCELL3:IMUX.IMUX13	GT11_0.ENMCOMMAALIGN
TCELL3:IMUX.IMUX14	GT11_0.RXDESCRAM64B66BUSE
TCELL3:IMUX.IMUX15	GT11_0.RXBLOCKSYNC64B66BUSE
TCELL3:IMUX.IMUX16	GT11_0.RXCOMMADETUSE
TCELL3:IMUX.IMUX17	GT11_0.RXSLIDE
TCELL3:IMUX.IMUX18	GT11_0.TXCLKSTABLE
TCELL3:IMUX.IMUX19	GT11_0.RXCLKSTABLE
TCELL3:OUT.BEST0.TMIN	GT11_0.RXDATA12
TCELL3:OUT.BEST1.TMIN	GT11_0.RXDATA13
TCELL3:OUT.BEST2.TMIN	GT11_0.RXDATA14
TCELL3:OUT.BEST3.TMIN	GT11_0.RXDATA15
TCELL3:OUT.BEST4.TMIN	GT11_0.RXVCOHIGH
TCELL3:OUT.BEST5.TMIN	GT11_0.TXVCOHIGH
TCELL3:OUT.BEST6.TMIN	GT11_0.RXCALFAIL
TCELL3:OUT.BEST7.TMIN	GT11_0.TXCALFAIL
TCELL3:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT11
TCELL3:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT10
TCELL3:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT9
TCELL3:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT8
TCELL3:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS7
TCELL3:OUT.HALF.BOT5.TMIN	GT11_0.CDRSTATUS8
TCELL3:OUT.HALF.BOT6.TMIN	GT11_0.CDRSTATUS9
TCELL3:OUT.HALF.BOT7.TMIN	GT11_0.CDRSTATUS10
TCELL3:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT11
TCELL3:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT10
TCELL3:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT9
TCELL3:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT8
TCELL3:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS7
TCELL3:OUT.HALT.TOP5.TMIN	GT11_0.CDRSTATUS8
TCELL3:OUT.HALT.TOP6.TMIN	GT11_0.CDRSTATUS9
TCELL3:OUT.HALT.TOP7.TMIN	GT11_0.CDRSTATUS10
TCELL4:IMUX.IMUX0	GT11_0.TXDATA16
TCELL4:IMUX.IMUX1	GT11_0.TXDATA17
TCELL4:IMUX.IMUX2	GT11_0.TXDATA18
TCELL4:IMUX.IMUX3	GT11_0.TXDATA19
TCELL4:IMUX.IMUX4	GT11_0.TXCRCIN23
TCELL4:IMUX.IMUX5	GT11_0.TXCRCIN22
TCELL4:IMUX.IMUX6	GT11_0.TXCRCIN21
TCELL4:IMUX.IMUX7	GT11_0.TXCRCIN20
TCELL4:IMUX.IMUX8	GT11_0.RXCRCIN23
TCELL4:IMUX.IMUX9	GT11_0.RXCRCIN22
TCELL4:IMUX.IMUX10	GT11_0.RXCRCIN21
TCELL4:IMUX.IMUX11	GT11_0.RXCRCIN20
TCELL4:IMUX.IMUX12	GT11_0.TXUSRVCODAC0
TCELL4:IMUX.IMUX13	GT11_0.TXUSRVCODAC1
TCELL4:IMUX.IMUX14	GT11_0.TXUSRVCODAC2
TCELL4:IMUX.IMUX15	GT11_0.TXUSRVCODAC3
TCELL4:IMUX.IMUX16	GT11_0.TXBYPASS8B10B2
TCELL4:IMUX.IMUX17	GT11_0.TXCHARISK2
TCELL4:IMUX.IMUX18	GT11_0.TXCHARDISPMODE2
TCELL4:IMUX.IMUX19	GT11_0.TXCHARDISPVAL2
TCELL4:OUT.BEST0.TMIN	GT11_0.RXDATA16
TCELL4:OUT.BEST1.TMIN	GT11_0.RXDATA17
TCELL4:OUT.BEST2.TMIN	GT11_0.RXDATA18
TCELL4:OUT.BEST3.TMIN	GT11_0.RXDATA19
TCELL4:OUT.BEST4.TMIN	GT11_0.RXDISPERR2
TCELL4:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE2
TCELL4:OUT.BEST6.TMIN	GT11_0.RXCHARISK2
TCELL4:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA2
TCELL4:OUT.SEC0.TMIN	GT11_0.RXRUNDISP2
TCELL4:OUT.SEC1.TMIN	GT11_0.TXRUNDISP2
TCELL4:OUT.SEC2.TMIN	GT11_0.TXKERR2
TCELL4:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT23
TCELL4:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT22
TCELL4:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT21
TCELL4:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT20
TCELL4:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS11
TCELL4:OUT.HALF.BOT5.TMIN	GT11_0.CDRSTATUS12
TCELL4:OUT.HALF.BOT6.TMIN	GT11_0.RXBUFERR
TCELL4:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT23
TCELL4:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT22
TCELL4:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT21
TCELL4:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT20
TCELL4:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS11
TCELL4:OUT.HALT.TOP5.TMIN	GT11_0.CDRSTATUS12
TCELL4:OUT.HALT.TOP6.TMIN	GT11_0.RXBUFERR
TCELL5:IMUX.IMUX0	GT11_0.TXDATA20
TCELL5:IMUX.IMUX1	GT11_0.TXDATA21
TCELL5:IMUX.IMUX2	GT11_0.TXDATA22
TCELL5:IMUX.IMUX3	GT11_0.TXDATA23
TCELL5:IMUX.IMUX4	GT11_0.TXCRCIN19
TCELL5:IMUX.IMUX5	GT11_0.TXCRCIN18
TCELL5:IMUX.IMUX6	GT11_0.TXCRCIN17
TCELL5:IMUX.IMUX7	GT11_0.TXCRCIN16
TCELL5:IMUX.IMUX8	GT11_0.RXCRCIN19
TCELL5:IMUX.IMUX9	GT11_0.RXCRCIN18
TCELL5:IMUX.IMUX10	GT11_0.RXCRCIN17
TCELL5:IMUX.IMUX11	GT11_0.RXCRCIN16
TCELL5:IMUX.IMUX12	GT11_0.TXUSRVCODAC4
TCELL5:IMUX.IMUX13	GT11_0.TXUSRVCODAC5
TCELL5:IMUX.IMUX14	GT11_0.TXUSRVCODAC6
TCELL5:IMUX.IMUX15	GT11_0.TXUSRVCODAC7
TCELL5:IMUX.IMUX16	GT11_0.RXCRCINIT
TCELL5:IMUX.IMUX17	GT11_0.TXCRCINIT
TCELL5:IMUX.IMUX18	GT11_0.TXENOOB
TCELL5:OUT.BEST0.TMIN	GT11_0.RXDATA20
TCELL5:OUT.BEST1.TMIN	GT11_0.RXDATA21
TCELL5:OUT.BEST2.TMIN	GT11_0.RXDATA22
TCELL5:OUT.BEST3.TMIN	GT11_0.RXDATA23
TCELL5:OUT.BEST4.TMIN	GT11_0.DO4
TCELL5:OUT.BEST5.TMIN	GT11_0.DO5
TCELL5:OUT.BEST6.TMIN	GT11_0.DO6
TCELL5:OUT.BEST7.TMIN	GT11_0.DO7
TCELL5:OUT.SEC0.TMIN	GT11_0.CDRSTATUS13
TCELL5:OUT.SEC1.TMIN	GT11_0.CDRSTATUS14
TCELL5:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT19
TCELL5:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT18
TCELL5:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT17
TCELL5:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT16
TCELL5:OUT.HALF.BOT4.TMIN	GT11_0.DO0
TCELL5:OUT.HALF.BOT5.TMIN	GT11_0.DO1
TCELL5:OUT.HALF.BOT6.TMIN	GT11_0.DO2
TCELL5:OUT.HALF.BOT7.TMIN	GT11_0.DO3
TCELL5:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT19
TCELL5:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT18
TCELL5:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT17
TCELL5:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT16
TCELL5:OUT.HALT.TOP4.TMIN	GT11_0.DO0
TCELL5:OUT.HALT.TOP5.TMIN	GT11_0.DO1
TCELL5:OUT.HALT.TOP6.TMIN	GT11_0.DO2
TCELL5:OUT.HALT.TOP7.TMIN	GT11_0.DO3
TCELL6:IMUX.CLK0	GT11_0.RXUSRCLK
TCELL6:IMUX.CLK1	GT11_0.RXUSRCLK2
TCELL6:IMUX.CLK2	GT11_0.TXUSRCLK
TCELL6:IMUX.CLK3	GT11_0.TXUSRCLK2
TCELL6:IMUX.IMUX0	GT11_0.TXDATA24
TCELL6:IMUX.IMUX1	GT11_0.TXDATA25
TCELL6:IMUX.IMUX2	GT11_0.TXDATA26
TCELL6:IMUX.IMUX3	GT11_0.TXDATA27
TCELL6:IMUX.IMUX4	GT11_0.TXCRCIN31
TCELL6:IMUX.IMUX5	GT11_0.TXCRCIN30
TCELL6:IMUX.IMUX6	GT11_0.TXCRCIN29
TCELL6:IMUX.IMUX7	GT11_0.TXCRCIN28
TCELL6:IMUX.IMUX8	GT11_0.RXCRCIN31
TCELL6:IMUX.IMUX9	GT11_0.RXCRCIN30
TCELL6:IMUX.IMUX10	GT11_0.RXCRCIN29
TCELL6:IMUX.IMUX11	GT11_0.RXCRCIN28
TCELL6:IMUX.IMUX12	GT11_0.DADDR0
TCELL6:IMUX.IMUX13	GT11_0.DADDR1
TCELL6:IMUX.IMUX14	GT11_0.DADDR2
TCELL6:IMUX.IMUX15	GT11_0.DADDR3
TCELL6:IMUX.IMUX16	GT11_0.TXBYPASS8B10B3
TCELL6:IMUX.IMUX17	GT11_0.TXCHARISK3
TCELL6:IMUX.IMUX18	GT11_0.TXCHARDISPMODE3
TCELL6:IMUX.IMUX19	GT11_0.TXCHARDISPVAL3
TCELL6:IMUX.IMUX20	GT11_0.TXUSRVCODAC8
TCELL6:IMUX.IMUX21	GT11_0.TXUSRVCODAC9
TCELL6:OUT.BEST0.TMIN	GT11_0.RXDATA24
TCELL6:OUT.BEST1.TMIN	GT11_0.RXDATA25
TCELL6:OUT.BEST2.TMIN	GT11_0.RXDATA26
TCELL6:OUT.BEST3.TMIN	GT11_0.RXDATA27
TCELL6:OUT.BEST4.TMIN	GT11_0.RXDISPERR3
TCELL6:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE3
TCELL6:OUT.BEST6.TMIN	GT11_0.RXCHARISK3
TCELL6:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA3
TCELL6:OUT.SEC0.TMIN	GT11_0.RXRUNDISP3
TCELL6:OUT.SEC1.TMIN	GT11_0.TXRUNDISP3
TCELL6:OUT.SEC2.TMIN	GT11_0.TXKERR3
TCELL6:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT31
TCELL6:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT30
TCELL6:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT29
TCELL6:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT28
TCELL6:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS15
TCELL6:OUT.HALF.BOT5.TMIN	GT11_0.CDRSTATUS16
TCELL6:OUT.HALF.BOT6.TMIN	GT11_0.TXADCN
TCELL6:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT31
TCELL6:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT30
TCELL6:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT29
TCELL6:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT28
TCELL6:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS15
TCELL6:OUT.HALT.TOP5.TMIN	GT11_0.CDRSTATUS16
TCELL6:OUT.HALT.TOP6.TMIN	GT11_0.TXADCN
TCELL7:IMUX.SR0	GT11_0.RXCRCRESET
TCELL7:IMUX.CLK0	GT11_0.RXCRCINTCLK
TCELL7:IMUX.CLK1	GT11_0.TXCRCINTCLK
TCELL7:IMUX.CE0	GT11_0.RXCRCDATAVALID
TCELL7:IMUX.CE1	GT11_0.TXCRCDATAVALID
TCELL7:IMUX.IMUX0	GT11_0.TXDATA28
TCELL7:IMUX.IMUX1	GT11_0.TXDATA29
TCELL7:IMUX.IMUX2	GT11_0.TXDATA30
TCELL7:IMUX.IMUX3	GT11_0.TXDATA31
TCELL7:IMUX.IMUX4	GT11_0.TXCRCIN27
TCELL7:IMUX.IMUX5	GT11_0.TXCRCIN26
TCELL7:IMUX.IMUX6	GT11_0.TXCRCIN25
TCELL7:IMUX.IMUX7	GT11_0.TXCRCIN24
TCELL7:IMUX.IMUX8	GT11_0.RXCRCIN27
TCELL7:IMUX.IMUX9	GT11_0.RXCRCIN26
TCELL7:IMUX.IMUX10	GT11_0.RXCRCIN25
TCELL7:IMUX.IMUX11	GT11_0.RXCRCIN24
TCELL7:IMUX.IMUX12	GT11_0.DI0
TCELL7:IMUX.IMUX13	GT11_0.DI1
TCELL7:IMUX.IMUX14	GT11_0.DI2
TCELL7:IMUX.IMUX15	GT11_0.DI3
TCELL7:IMUX.IMUX16	GT11_0.DI4
TCELL7:IMUX.IMUX17	GT11_0.DI5
TCELL7:IMUX.IMUX18	GT11_0.DI6
TCELL7:IMUX.IMUX19	GT11_0.DI7
TCELL7:IMUX.IMUX20	GT11_0.DADDR4
TCELL7:IMUX.IMUX21	GT11_0.DADDR5
TCELL7:IMUX.IMUX22	GT11_0.DADDR6
TCELL7:IMUX.IMUX23	GT11_0.DADDR7
TCELL7:OUT.BEST0.TMIN	GT11_0.RXDATA28
TCELL7:OUT.BEST1.TMIN	GT11_0.RXDATA29
TCELL7:OUT.BEST2.TMIN	GT11_0.RXDATA30
TCELL7:OUT.BEST3.TMIN	GT11_0.RXDATA31
TCELL7:OUT.BEST4.TMIN	GT11_0.RXRECCLK1
TCELL7:OUT.BEST5.TMIN	GT11_0.RXRECCLK2
TCELL7:OUT.BEST6.TMIN	GT11_0.TXOUTCLK1
TCELL7:OUT.BEST7.TMIN	GT11_0.TXOUTCLK2
TCELL7:OUT.SEC0.TMIN	GT11_0.DRDY
TCELL7:OUT.SEC1.TMIN	GT11_0.TXADCP
TCELL7:OUT.HALF.BOT0.TMIN	GT11_0.TXCRCOUT27
TCELL7:OUT.HALF.BOT1.TMIN	GT11_0.TXCRCOUT26
TCELL7:OUT.HALF.BOT2.TMIN	GT11_0.TXCRCOUT25
TCELL7:OUT.HALF.BOT3.TMIN	GT11_0.TXCRCOUT24
TCELL7:OUT.HALF.BOT4.TMIN	GT11_0.DO8
TCELL7:OUT.HALF.BOT5.TMIN	GT11_0.DO9
TCELL7:OUT.HALF.BOT6.TMIN	GT11_0.DO10
TCELL7:OUT.HALF.BOT7.TMIN	GT11_0.DO11
TCELL7:OUT.HALT.TOP0.TMIN	GT11_0.TXCRCOUT27
TCELL7:OUT.HALT.TOP1.TMIN	GT11_0.TXCRCOUT26
TCELL7:OUT.HALT.TOP2.TMIN	GT11_0.TXCRCOUT25
TCELL7:OUT.HALT.TOP3.TMIN	GT11_0.TXCRCOUT24
TCELL7:OUT.HALT.TOP4.TMIN	GT11_0.DO8
TCELL7:OUT.HALT.TOP5.TMIN	GT11_0.DO9
TCELL7:OUT.HALT.TOP6.TMIN	GT11_0.DO10
TCELL7:OUT.HALT.TOP7.TMIN	GT11_0.DO11
TCELL8:IMUX.SR0	GT11_0.TXCRCRESET
TCELL8:IMUX.CLK0	GT11_0.TXCRCCLK
TCELL8:IMUX.CLK1	GT11_0.RXCRCCLK
TCELL8:IMUX.CLK3	GT11_0.DCLK
TCELL8:IMUX.CE0	GT11_0.DEN
TCELL8:IMUX.CE1	GT11_0.DWE
TCELL8:IMUX.IMUX0	GT11_0.TXDATA32
TCELL8:IMUX.IMUX1	GT11_0.TXDATA33
TCELL8:IMUX.IMUX2	GT11_0.TXDATA34
TCELL8:IMUX.IMUX3	GT11_0.TXDATA35
TCELL8:IMUX.IMUX4	GT11_0.TXCRCIN39
TCELL8:IMUX.IMUX5	GT11_0.TXCRCIN38
TCELL8:IMUX.IMUX6	GT11_0.TXCRCIN37
TCELL8:IMUX.IMUX7	GT11_0.TXCRCIN36
TCELL8:IMUX.IMUX8	GT11_0.RXCRCIN39
TCELL8:IMUX.IMUX9	GT11_0.RXCRCIN38
TCELL8:IMUX.IMUX10	GT11_0.RXCRCIN37
TCELL8:IMUX.IMUX11	GT11_0.RXCRCIN36
TCELL8:IMUX.IMUX12	GT11_0.DI8
TCELL8:IMUX.IMUX13	GT11_0.DI9
TCELL8:IMUX.IMUX14	GT11_0.DI10
TCELL8:IMUX.IMUX15	GT11_0.DI11
TCELL8:IMUX.IMUX16	GT11_0.TXBYPASS8B10B4
TCELL8:IMUX.IMUX17	GT11_0.TXCHARISK4
TCELL8:IMUX.IMUX18	GT11_0.TXCHARDISPMODE4
TCELL8:IMUX.IMUX19	GT11_0.TXCHARDISPVAL4
TCELL8:IMUX.IMUX20	GT11_0.DI12
TCELL8:IMUX.IMUX21	GT11_0.DI13
TCELL8:IMUX.IMUX22	GT11_0.DI14
TCELL8:IMUX.IMUX23	GT11_0.DI15
TCELL8:OUT.BEST0.TMIN	GT11_0.RXDATA32
TCELL8:OUT.BEST1.TMIN	GT11_0.RXDATA33
TCELL8:OUT.BEST2.TMIN	GT11_0.RXDATA34
TCELL8:OUT.BEST3.TMIN	GT11_0.RXDATA35
TCELL8:OUT.BEST4.TMIN	GT11_0.RXDISPERR4
TCELL8:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE4
TCELL8:OUT.BEST6.TMIN	GT11_0.RXCHARISK4
TCELL8:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA4
TCELL8:OUT.SEC0.TMIN	GT11_0.RXRUNDISP4
TCELL8:OUT.SEC1.TMIN	GT11_0.TXRUNDISP4
TCELL8:OUT.SEC2.TMIN	GT11_0.TXKERR4
TCELL8:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT7
TCELL8:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT6
TCELL8:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT5
TCELL8:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT4
TCELL8:OUT.HALF.BOT4.TMIN	GT11_0.CDRSTATUS17
TCELL8:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT7
TCELL8:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT6
TCELL8:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT5
TCELL8:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT4
TCELL8:OUT.HALT.TOP4.TMIN	GT11_0.CDRSTATUS17
TCELL9:IMUX.SR0	GT11_0.RXPMARESET
TCELL9:IMUX.IMUX0	GT11_0.TXDATA36
TCELL9:IMUX.IMUX1	GT11_0.TXDATA37
TCELL9:IMUX.IMUX2	GT11_0.TXDATA38
TCELL9:IMUX.IMUX3	GT11_0.TXDATA39
TCELL9:IMUX.IMUX4	GT11_0.TXCRCIN35
TCELL9:IMUX.IMUX5	GT11_0.TXCRCIN34
TCELL9:IMUX.IMUX6	GT11_0.TXCRCIN33
TCELL9:IMUX.IMUX7	GT11_0.TXCRCIN32
TCELL9:IMUX.IMUX8	GT11_0.RXCRCIN35
TCELL9:IMUX.IMUX9	GT11_0.RXCRCIN34
TCELL9:IMUX.IMUX10	GT11_0.RXCRCIN33
TCELL9:IMUX.IMUX11	GT11_0.RXCRCIN32
TCELL9:IMUX.IMUX12	GT11_0.RXCRCPD
TCELL9:IMUX.IMUX13	GT11_0.TXCRCPD
TCELL9:IMUX.IMUX14	GT11_0.MGTADCSEL0
TCELL9:IMUX.IMUX15	GT11_0.MGTADCSEL1
TCELL9:IMUX.IMUX16	GT11_0.MGTADCSEL2
TCELL9:IMUX.IMUX17	GT11_0.MGTADCSEL3
TCELL9:IMUX.IMUX18	GT11_0.MGTADCSEL4
TCELL9:OUT.BEST0.TMIN	GT11_0.RXDATA36
TCELL9:OUT.BEST1.TMIN	GT11_0.RXDATA37
TCELL9:OUT.BEST2.TMIN	GT11_0.RXDATA38
TCELL9:OUT.BEST3.TMIN	GT11_0.RXDATA39
TCELL9:OUT.BEST4.TMIN	GT11_0.RXREALIGN
TCELL9:OUT.BEST5.TMIN	GT11_0.RXCOMMADET
TCELL9:OUT.SEC0.TMIN	GT11_0.TXFDETSTATE0
TCELL9:OUT.SEC1.TMIN	GT11_0.TXFDETSTATE1
TCELL9:OUT.SEC2.TMIN	GT11_0.TXFDETSTATE2
TCELL9:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT3
TCELL9:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT2
TCELL9:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT1
TCELL9:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT0
TCELL9:OUT.HALF.BOT4.TMIN	GT11_0.DO12
TCELL9:OUT.HALF.BOT5.TMIN	GT11_0.DO13
TCELL9:OUT.HALF.BOT6.TMIN	GT11_0.DO14
TCELL9:OUT.HALF.BOT7.TMIN	GT11_0.DO15
TCELL9:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT3
TCELL9:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT2
TCELL9:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT1
TCELL9:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT0
TCELL9:OUT.HALT.TOP4.TMIN	GT11_0.DO12
TCELL9:OUT.HALT.TOP5.TMIN	GT11_0.DO13
TCELL9:OUT.HALT.TOP6.TMIN	GT11_0.DO14
TCELL9:OUT.HALT.TOP7.TMIN	GT11_0.DO15
TCELL10:IMUX.SR0	GT11_0.TXPMARESET
TCELL10:IMUX.IMUX0	GT11_0.TXDATA40
TCELL10:IMUX.IMUX1	GT11_0.TXDATA41
TCELL10:IMUX.IMUX2	GT11_0.TXDATA42
TCELL10:IMUX.IMUX3	GT11_0.TXDATA43
TCELL10:IMUX.IMUX4	GT11_0.TXCRCIN47
TCELL10:IMUX.IMUX5	GT11_0.TXCRCIN46
TCELL10:IMUX.IMUX6	GT11_0.TXCRCIN45
TCELL10:IMUX.IMUX7	GT11_0.TXCRCIN44
TCELL10:IMUX.IMUX8	GT11_0.RXCRCIN47
TCELL10:IMUX.IMUX9	GT11_0.RXCRCIN46
TCELL10:IMUX.IMUX10	GT11_0.RXCRCIN45
TCELL10:IMUX.IMUX11	GT11_0.RXCRCIN44
TCELL10:IMUX.IMUX12	GT11_0.RXUSRLOCK
TCELL10:IMUX.IMUX13	GT11_0.RXUSRVCOCAL
TCELL10:IMUX.IMUX14	GT11_0.TXUSRLOCK
TCELL10:IMUX.IMUX15	GT11_0.TXUSRVCOCAL
TCELL10:IMUX.IMUX16	GT11_0.TXBYPASS8B10B5
TCELL10:IMUX.IMUX17	GT11_0.TXCHARISK5
TCELL10:IMUX.IMUX18	GT11_0.TXCHARDISPMODE5
TCELL10:IMUX.IMUX19	GT11_0.TXCHARDISPVAL5
TCELL10:OUT.BEST0.TMIN	GT11_0.RXDATA40
TCELL10:OUT.BEST1.TMIN	GT11_0.RXDATA41
TCELL10:OUT.BEST2.TMIN	GT11_0.RXDATA42
TCELL10:OUT.BEST3.TMIN	GT11_0.RXDATA43
TCELL10:OUT.BEST4.TMIN	GT11_0.RXDISPERR5
TCELL10:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE5
TCELL10:OUT.BEST6.TMIN	GT11_0.RXCHARISK5
TCELL10:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA5
TCELL10:OUT.SEC0.TMIN	GT11_0.RXRUNDISP5
TCELL10:OUT.SEC1.TMIN	GT11_0.TXRUNDISP5
TCELL10:OUT.SEC2.TMIN	GT11_0.TXKERR5
TCELL10:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT15
TCELL10:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT14
TCELL10:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT13
TCELL10:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT12
TCELL10:OUT.HALF.BOT4.TMIN	GT11_0.TXFCALSTATE0
TCELL10:OUT.HALF.BOT5.TMIN	GT11_0.TXFCALSTATE1
TCELL10:OUT.HALF.BOT6.TMIN	GT11_0.TXFCALSTATE2
TCELL10:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT15
TCELL10:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT14
TCELL10:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT13
TCELL10:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT12
TCELL10:OUT.HALT.TOP4.TMIN	GT11_0.TXFCALSTATE0
TCELL10:OUT.HALT.TOP5.TMIN	GT11_0.TXFCALSTATE1
TCELL10:OUT.HALT.TOP6.TMIN	GT11_0.TXFCALSTATE2
TCELL11:IMUX.IMUX0	GT11_0.TXDATA44
TCELL11:IMUX.IMUX1	GT11_0.TXDATA45
TCELL11:IMUX.IMUX2	GT11_0.TXDATA46
TCELL11:IMUX.IMUX3	GT11_0.TXDATA47
TCELL11:IMUX.IMUX4	GT11_0.TXCRCIN43
TCELL11:IMUX.IMUX5	GT11_0.TXCRCIN42
TCELL11:IMUX.IMUX6	GT11_0.TXCRCIN41
TCELL11:IMUX.IMUX7	GT11_0.TXCRCIN40
TCELL11:IMUX.IMUX8	GT11_0.RXCRCIN43
TCELL11:IMUX.IMUX9	GT11_0.RXCRCIN42
TCELL11:IMUX.IMUX10	GT11_0.RXCRCIN41
TCELL11:IMUX.IMUX11	GT11_0.RXCRCIN40
TCELL11:IMUX.IMUX12	GT11_0.TXSYNC
TCELL11:IMUX.IMUX17	GT11_0.RXCRCDATAWIDTH0
TCELL11:IMUX.IMUX18	GT11_0.RXCRCDATAWIDTH1
TCELL11:IMUX.IMUX19	GT11_0.RXCRCDATAWIDTH2
TCELL11:IMUX.IMUX20	GT11_0.TXCRCDATAWIDTH0
TCELL11:IMUX.IMUX21	GT11_0.TXCRCDATAWIDTH1
TCELL11:IMUX.IMUX22	GT11_0.TXCRCDATAWIDTH2
TCELL11:OUT.BEST0.TMIN	GT11_0.RXDATA44
TCELL11:OUT.BEST1.TMIN	GT11_0.RXDATA45
TCELL11:OUT.BEST2.TMIN	GT11_0.RXDATA46
TCELL11:OUT.BEST3.TMIN	GT11_0.RXDATA47
TCELL11:OUT.BEST4.TMIN	GT11_0.CHBONDO0
TCELL11:OUT.BEST5.TMIN	GT11_0.CHBONDO1
TCELL11:OUT.BEST6.TMIN	GT11_0.CHBONDO2
TCELL11:OUT.BEST7.TMIN	GT11_0.CHBONDO3
TCELL11:OUT.SEC0.TMIN	GT11_0.CHBONDO4
TCELL11:OUT.SEC1.TMIN	GT11_0.SCANOUT2
TCELL11:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT11
TCELL11:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT10
TCELL11:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT9
TCELL11:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT8
TCELL11:OUT.HALF.BOT4.TMIN	GT11_0.RXCYCLELIMIT
TCELL11:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT11
TCELL11:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT10
TCELL11:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT9
TCELL11:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT8
TCELL11:OUT.HALT.TOP4.TMIN	GT11_0.RXCYCLELIMIT
TCELL12:IMUX.CE0	GT11_0.SCANEN2
TCELL12:IMUX.CE1	GT11_0.SCANMODE2
TCELL12:IMUX.IMUX0	GT11_0.TXDATA48
TCELL12:IMUX.IMUX1	GT11_0.TXDATA49
TCELL12:IMUX.IMUX2	GT11_0.TXDATA50
TCELL12:IMUX.IMUX3	GT11_0.TXDATA51
TCELL12:IMUX.IMUX4	GT11_0.TXCRCIN55
TCELL12:IMUX.IMUX5	GT11_0.TXCRCIN54
TCELL12:IMUX.IMUX6	GT11_0.TXCRCIN53
TCELL12:IMUX.IMUX7	GT11_0.TXCRCIN52
TCELL12:IMUX.IMUX8	GT11_0.RXCRCIN55
TCELL12:IMUX.IMUX9	GT11_0.RXCRCIN54
TCELL12:IMUX.IMUX10	GT11_0.RXCRCIN53
TCELL12:IMUX.IMUX11	GT11_0.RXCRCIN52
TCELL12:IMUX.IMUX12	GT11_0.RXDEC8B10BUSE
TCELL12:IMUX.IMUX13	GT11_0.RXDEC64B66BUSE
TCELL12:IMUX.IMUX14	GT11_0.TESTMEMORY
TCELL12:IMUX.IMUX15	GT11_0.RXIGNOREBTF
TCELL12:IMUX.IMUX16	GT11_0.TXBYPASS8B10B6
TCELL12:IMUX.IMUX17	GT11_0.TXCHARISK6
TCELL12:IMUX.IMUX18	GT11_0.TXCHARDISPMODE6
TCELL12:IMUX.IMUX19	GT11_0.TXCHARDISPVAL6
TCELL12:OUT.BEST0.TMIN	GT11_0.RXDATA48
TCELL12:OUT.BEST1.TMIN	GT11_0.RXDATA49
TCELL12:OUT.BEST2.TMIN	GT11_0.RXDATA50
TCELL12:OUT.BEST3.TMIN	GT11_0.RXDATA51
TCELL12:OUT.BEST4.TMIN	GT11_0.RXDISPERR6
TCELL12:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE6
TCELL12:OUT.BEST6.TMIN	GT11_0.RXCHARISK6
TCELL12:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA6
TCELL12:OUT.SEC0.TMIN	GT11_0.RXRUNDISP6
TCELL12:OUT.SEC1.TMIN	GT11_0.TXRUNDISP6
TCELL12:OUT.SEC2.TMIN	GT11_0.TXKERR6
TCELL12:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT23
TCELL12:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT22
TCELL12:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT21
TCELL12:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT20
TCELL12:OUT.HALF.BOT4.TMIN	GT11_0.TXCOARSEST
TCELL12:OUT.HALF.BOT5.TMIN	GT11_0.TXENABLECAL
TCELL12:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT23
TCELL12:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT22
TCELL12:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT21
TCELL12:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT20
TCELL12:OUT.HALT.TOP4.TMIN	GT11_0.TXCOARSEST
TCELL12:OUT.HALT.TOP5.TMIN	GT11_0.TXENABLECAL
TCELL13:IMUX.CE0	GT11_0.SCANMODE0
TCELL13:IMUX.CE1	GT11_0.SCANMODE1
TCELL13:IMUX.IMUX0	GT11_0.TXDATA52
TCELL13:IMUX.IMUX1	GT11_0.TXDATA53
TCELL13:IMUX.IMUX2	GT11_0.TXDATA54
TCELL13:IMUX.IMUX3	GT11_0.TXDATA55
TCELL13:IMUX.IMUX4	GT11_0.TXCRCIN51
TCELL13:IMUX.IMUX5	GT11_0.TXCRCIN50
TCELL13:IMUX.IMUX6	GT11_0.TXCRCIN49
TCELL13:IMUX.IMUX7	GT11_0.TXCRCIN48
TCELL13:IMUX.IMUX8	GT11_0.RXCRCIN51
TCELL13:IMUX.IMUX9	GT11_0.RXCRCIN50
TCELL13:IMUX.IMUX10	GT11_0.RXCRCIN49
TCELL13:IMUX.IMUX11	GT11_0.RXCRCIN48
TCELL13:IMUX.IMUX12	GT11_0.CHBONDI0
TCELL13:IMUX.IMUX13	GT11_0.CHBONDI1
TCELL13:IMUX.IMUX14	GT11_0.CHBONDI2
TCELL13:IMUX.IMUX15	GT11_0.CHBONDI3
TCELL13:IMUX.IMUX16	GT11_0.CHBONDI4
TCELL13:OUT.BEST0.TMIN	GT11_0.RXDATA52
TCELL13:OUT.BEST1.TMIN	GT11_0.RXDATA53
TCELL13:OUT.BEST2.TMIN	GT11_0.RXDATA54
TCELL13:OUT.BEST3.TMIN	GT11_0.RXDATA55
TCELL13:OUT.BEST4.TMIN	GT11_0.RXSTATUS5
TCELL13:OUT.BEST5.TMIN	GT11_0.TXBUFERR
TCELL13:OUT.BEST6.TMIN	GT11_0.SCANOUT0
TCELL13:OUT.BEST7.TMIN	GT11_0.SCANOUT1
TCELL13:OUT.SEC0.TMIN	GT11_0.RXFDETSTATE0
TCELL13:OUT.SEC1.TMIN	GT11_0.RXFDETSTATE1
TCELL13:OUT.SEC2.TMIN	GT11_0.RXFDETSTATE2
TCELL13:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT19
TCELL13:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT18
TCELL13:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT17
TCELL13:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT16
TCELL13:OUT.HALF.BOT4.TMIN	GT11_0.TXCYCLELIMIT
TCELL13:OUT.HALF.BOT5.TMIN	GT11_0.RXSTATUS3
TCELL13:OUT.HALF.BOT6.TMIN	GT11_0.RXSTATUS4
TCELL13:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT19
TCELL13:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT18
TCELL13:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT17
TCELL13:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT16
TCELL13:OUT.HALT.TOP4.TMIN	GT11_0.TXCYCLELIMIT
TCELL13:OUT.HALT.TOP5.TMIN	GT11_0.RXSTATUS3
TCELL13:OUT.HALT.TOP6.TMIN	GT11_0.RXSTATUS4
TCELL14:IMUX.CE0	GT11_0.SCANEN0
TCELL14:IMUX.CE1	GT11_0.SCANEN1
TCELL14:IMUX.IMUX0	GT11_0.TXDATA56
TCELL14:IMUX.IMUX1	GT11_0.TXDATA57
TCELL14:IMUX.IMUX2	GT11_0.TXDATA58
TCELL14:IMUX.IMUX3	GT11_0.TXDATA59
TCELL14:IMUX.IMUX4	GT11_0.TXCRCIN63
TCELL14:IMUX.IMUX5	GT11_0.TXCRCIN62
TCELL14:IMUX.IMUX6	GT11_0.TXCRCIN61
TCELL14:IMUX.IMUX7	GT11_0.TXCRCIN60
TCELL14:IMUX.IMUX8	GT11_0.RXCRCIN63
TCELL14:IMUX.IMUX9	GT11_0.RXCRCIN62
TCELL14:IMUX.IMUX10	GT11_0.RXCRCIN61
TCELL14:IMUX.IMUX11	GT11_0.RXCRCIN60
TCELL14:IMUX.IMUX12	GT11_0.TXENC8B10BUSE
TCELL14:IMUX.IMUX13	GT11_0.TXENC64B66BUSE
TCELL14:IMUX.IMUX14	GT11_0.TXSCRAM64B66BUSE
TCELL14:IMUX.IMUX15	GT11_0.TXGEARBOX64B66BUSE
TCELL14:IMUX.IMUX16	GT11_0.TXBYPASS8B10B7
TCELL14:IMUX.IMUX17	GT11_0.TXCHARISK7
TCELL14:IMUX.IMUX18	GT11_0.TXCHARDISPMODE7
TCELL14:IMUX.IMUX19	GT11_0.TXCHARDISPVAL7
TCELL14:OUT.BEST0.TMIN	GT11_0.RXDATA56
TCELL14:OUT.BEST1.TMIN	GT11_0.RXDATA57
TCELL14:OUT.BEST2.TMIN	GT11_0.RXDATA58
TCELL14:OUT.BEST3.TMIN	GT11_0.RXDATA59
TCELL14:OUT.BEST4.TMIN	GT11_0.RXDISPERR7
TCELL14:OUT.BEST5.TMIN	GT11_0.RXNOTINTABLE7
TCELL14:OUT.BEST6.TMIN	GT11_0.RXCHARISK7
TCELL14:OUT.BEST7.TMIN	GT11_0.RXCHARISCOMMA7
TCELL14:OUT.SEC0.TMIN	GT11_0.RXRUNDISP7
TCELL14:OUT.SEC1.TMIN	GT11_0.TXRUNDISP7
TCELL14:OUT.SEC2.TMIN	GT11_0.TXKERR7
TCELL14:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT31
TCELL14:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT30
TCELL14:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT29
TCELL14:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT28
TCELL14:OUT.HALF.BOT4.TMIN	GT11_0.RXFCALSTATE0
TCELL14:OUT.HALF.BOT5.TMIN	GT11_0.RXFCALSTATE1
TCELL14:OUT.HALF.BOT6.TMIN	GT11_0.RXFCALSTATE2
TCELL14:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT31
TCELL14:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT30
TCELL14:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT29
TCELL14:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT28
TCELL14:OUT.HALT.TOP4.TMIN	GT11_0.RXFCALSTATE0
TCELL14:OUT.HALT.TOP5.TMIN	GT11_0.RXFCALSTATE1
TCELL14:OUT.HALT.TOP6.TMIN	GT11_0.RXFCALSTATE2
TCELL15:IMUX.IMUX0	GT11_0.TXDATA60
TCELL15:IMUX.IMUX1	GT11_0.TXDATA61
TCELL15:IMUX.IMUX2	GT11_0.TXDATA62
TCELL15:IMUX.IMUX3	GT11_0.TXDATA63
TCELL15:IMUX.IMUX4	GT11_0.TXCRCIN59
TCELL15:IMUX.IMUX5	GT11_0.TXCRCIN58
TCELL15:IMUX.IMUX6	GT11_0.TXCRCIN57
TCELL15:IMUX.IMUX7	GT11_0.TXCRCIN56
TCELL15:IMUX.IMUX8	GT11_0.RXCRCIN59
TCELL15:IMUX.IMUX9	GT11_0.RXCRCIN58
TCELL15:IMUX.IMUX10	GT11_0.RXCRCIN57
TCELL15:IMUX.IMUX11	GT11_0.RXCRCIN56
TCELL15:IMUX.IMUX12	GT11_0.ENCHANSYNC
TCELL15:IMUX.IMUX13	GT11_0.POWERDOWN
TCELL15:IMUX.IMUX14	GT11_0.RXPOLARITY
TCELL15:IMUX.IMUX15	GT11_0.LOOPBACK0
TCELL15:IMUX.IMUX16	GT11_0.LOOPBACK1
TCELL15:IMUX.IMUX17	GT11_0.TXPOLARITY
TCELL15:IMUX.IMUX18	GT11_0.TXINHIBIT
TCELL15:IMUX.IMUX19	GT11_0.SCANIN0
TCELL15:IMUX.IMUX20	GT11_0.SCANIN1
TCELL15:IMUX.IMUX21	GT11_0.SCANIN2
TCELL15:OUT.BEST0.TMIN	GT11_0.RXDATA60
TCELL15:OUT.BEST1.TMIN	GT11_0.RXDATA61
TCELL15:OUT.BEST2.TMIN	GT11_0.RXDATA62
TCELL15:OUT.BEST3.TMIN	GT11_0.RXDATA63
TCELL15:OUT.BEST4.TMIN	GT11_0.RXSTATUS0
TCELL15:OUT.BEST5.TMIN	GT11_0.RXSTATUS1
TCELL15:OUT.BEST6.TMIN	GT11_0.RXSTATUS2
TCELL15:OUT.SEC0.TMIN	GT11_0.RXCOARSEST
TCELL15:OUT.SEC1.TMIN	GT11_0.RXENABLECAL
TCELL15:OUT.HALF.BOT0.TMIN	GT11_0.RXCRCOUT27
TCELL15:OUT.HALF.BOT1.TMIN	GT11_0.RXCRCOUT26
TCELL15:OUT.HALF.BOT2.TMIN	GT11_0.RXCRCOUT25
TCELL15:OUT.HALF.BOT3.TMIN	GT11_0.RXCRCOUT24
TCELL15:OUT.HALF.BOT4.TMIN	GT11_0.RXLOCK
TCELL15:OUT.HALF.BOT5.TMIN	GT11_0.TXLOCK
TCELL15:OUT.HALF.BOT6.TMIN	GT11_0.RXLOCKUPDATE
TCELL15:OUT.HALF.BOT7.TMIN	GT11_0.TXLOCKUPDATE
TCELL15:OUT.HALT.TOP0.TMIN	GT11_0.RXCRCOUT27
TCELL15:OUT.HALT.TOP1.TMIN	GT11_0.RXCRCOUT26
TCELL15:OUT.HALT.TOP2.TMIN	GT11_0.RXCRCOUT25
TCELL15:OUT.HALT.TOP3.TMIN	GT11_0.RXCRCOUT24
TCELL15:OUT.HALT.TOP4.TMIN	GT11_0.RXLOCK
TCELL15:OUT.HALT.TOP5.TMIN	GT11_0.TXLOCK
TCELL15:OUT.HALT.TOP6.TMIN	GT11_0.RXLOCKUPDATE
TCELL15:OUT.HALT.TOP7.TMIN	GT11_0.TXLOCKUPDATE
TCELL16:IMUX.SR0	GT11_1.RXRESET
TCELL16:IMUX.IMUX0	GT11_1.TXDATA0
TCELL16:IMUX.IMUX1	GT11_1.TXDATA1
TCELL16:IMUX.IMUX2	GT11_1.TXDATA2
TCELL16:IMUX.IMUX3	GT11_1.TXDATA3
TCELL16:IMUX.IMUX4	GT11_1.TXCRCIN7
TCELL16:IMUX.IMUX5	GT11_1.TXCRCIN6
TCELL16:IMUX.IMUX6	GT11_1.TXCRCIN5
TCELL16:IMUX.IMUX7	GT11_1.TXCRCIN4
TCELL16:IMUX.IMUX8	GT11_1.RXCRCIN7
TCELL16:IMUX.IMUX9	GT11_1.RXCRCIN6
TCELL16:IMUX.IMUX10	GT11_1.RXCRCIN5
TCELL16:IMUX.IMUX11	GT11_1.RXCRCIN4
TCELL16:IMUX.IMUX12	GT11_1.RXUSRVCODAC0
TCELL16:IMUX.IMUX13	GT11_1.RXUSRVCODAC1
TCELL16:IMUX.IMUX14	GT11_1.RXUSRVCODAC2
TCELL16:IMUX.IMUX15	GT11_1.RXUSRVCODAC3
TCELL16:IMUX.IMUX16	GT11_1.TXBYPASS8B10B0
TCELL16:IMUX.IMUX17	GT11_1.TXCHARISK0
TCELL16:IMUX.IMUX18	GT11_1.TXCHARDISPMODE0
TCELL16:IMUX.IMUX19	GT11_1.TXCHARDISPVAL0
TCELL16:OUT.BEST0.TMIN	GT11_1.RXDATA0
TCELL16:OUT.BEST1.TMIN	GT11_1.RXDATA1
TCELL16:OUT.BEST2.TMIN	GT11_1.RXDATA2
TCELL16:OUT.BEST3.TMIN	GT11_1.RXDATA3
TCELL16:OUT.BEST4.TMIN	GT11_1.RXDISPERR0
TCELL16:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE0
TCELL16:OUT.BEST6.TMIN	GT11_1.RXCHARISK0
TCELL16:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA0
TCELL16:OUT.SEC0.TMIN	GT11_1.RXRUNDISP0
TCELL16:OUT.SEC1.TMIN	GT11_1.TXRUNDISP0
TCELL16:OUT.SEC2.TMIN	GT11_1.TXKERR0
TCELL16:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT7
TCELL16:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT6
TCELL16:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT5
TCELL16:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT4
TCELL16:OUT.HALF.BOT4.TMIN	GT11_1.RXADCN
TCELL16:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT7
TCELL16:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT6
TCELL16:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT5
TCELL16:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT4
TCELL16:OUT.HALT.TOP4.TMIN	GT11_1.RXADCN
TCELL17:IMUX.SR0	GT11_1.TXRESET
TCELL17:IMUX.IMUX0	GT11_1.TXDATA4
TCELL17:IMUX.IMUX1	GT11_1.TXDATA5
TCELL17:IMUX.IMUX2	GT11_1.TXDATA6
TCELL17:IMUX.IMUX3	GT11_1.TXDATA7
TCELL17:IMUX.IMUX4	GT11_1.TXCRCIN3
TCELL17:IMUX.IMUX5	GT11_1.TXCRCIN2
TCELL17:IMUX.IMUX6	GT11_1.TXCRCIN1
TCELL17:IMUX.IMUX7	GT11_1.TXCRCIN0
TCELL17:IMUX.IMUX8	GT11_1.RXCRCIN3
TCELL17:IMUX.IMUX9	GT11_1.RXCRCIN2
TCELL17:IMUX.IMUX10	GT11_1.RXCRCIN1
TCELL17:IMUX.IMUX11	GT11_1.RXCRCIN0
TCELL17:IMUX.IMUX12	GT11_1.RXUSRVCODAC4
TCELL17:IMUX.IMUX13	GT11_1.RXUSRVCODAC5
TCELL17:IMUX.IMUX14	GT11_1.RXUSRVCODAC6
TCELL17:IMUX.IMUX15	GT11_1.RXUSRVCODAC7
TCELL17:IMUX.IMUX16	GT11_1.TXINTDATAWIDTH0
TCELL17:IMUX.IMUX17	GT11_1.TXINTDATAWIDTH1
TCELL17:IMUX.IMUX18	GT11_1.RXINTDATAWIDTH0
TCELL17:IMUX.IMUX19	GT11_1.RXINTDATAWIDTH1
TCELL17:IMUX.IMUX20	GT11_1.TXDATAWIDTH0
TCELL17:IMUX.IMUX21	GT11_1.TXDATAWIDTH1
TCELL17:IMUX.IMUX22	GT11_1.RXDATAWIDTH0
TCELL17:IMUX.IMUX23	GT11_1.RXDATAWIDTH1
TCELL17:OUT.BEST0.TMIN	GT11_1.RXDATA4
TCELL17:OUT.BEST1.TMIN	GT11_1.RXDATA5
TCELL17:OUT.BEST2.TMIN	GT11_1.RXDATA6
TCELL17:OUT.BEST3.TMIN	GT11_1.RXDATA7
TCELL17:OUT.BEST4.TMIN	GT11_1.RXLOSSOFSYNC0
TCELL17:OUT.BEST5.TMIN	GT11_1.RXLOSSOFSYNC1
TCELL17:OUT.BEST6.TMIN	GT11_1.RXSIGDET
TCELL17:OUT.BEST7.TMIN	GT11_1.RXADCP
TCELL17:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT3
TCELL17:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT2
TCELL17:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT1
TCELL17:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT0
TCELL17:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS0
TCELL17:OUT.HALF.BOT5.TMIN	GT11_1.CDRSTATUS1
TCELL17:OUT.HALF.BOT6.TMIN	GT11_1.CDRSTATUS2
TCELL17:OUT.HALF.BOT7.TMIN	GT11_1.CDRSTATUS3
TCELL17:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT3
TCELL17:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT2
TCELL17:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT1
TCELL17:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT0
TCELL17:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS0
TCELL17:OUT.HALT.TOP5.TMIN	GT11_1.CDRSTATUS1
TCELL17:OUT.HALT.TOP6.TMIN	GT11_1.CDRSTATUS2
TCELL17:OUT.HALT.TOP7.TMIN	GT11_1.CDRSTATUS3
TCELL18:IMUX.IMUX0	GT11_1.TXDATA8
TCELL18:IMUX.IMUX1	GT11_1.TXDATA9
TCELL18:IMUX.IMUX2	GT11_1.TXDATA10
TCELL18:IMUX.IMUX3	GT11_1.TXDATA11
TCELL18:IMUX.IMUX4	GT11_1.TXCRCIN15
TCELL18:IMUX.IMUX5	GT11_1.TXCRCIN14
TCELL18:IMUX.IMUX6	GT11_1.TXCRCIN13
TCELL18:IMUX.IMUX7	GT11_1.TXCRCIN12
TCELL18:IMUX.IMUX8	GT11_1.RXCRCIN15
TCELL18:IMUX.IMUX9	GT11_1.RXCRCIN14
TCELL18:IMUX.IMUX10	GT11_1.RXCRCIN13
TCELL18:IMUX.IMUX11	GT11_1.RXCRCIN12
TCELL18:IMUX.IMUX12	GT11_1.RXUSRVCODAC8
TCELL18:IMUX.IMUX13	GT11_1.RXUSRVCODAC9
TCELL18:IMUX.IMUX14	GT11_1.RXSYNC
TCELL18:IMUX.IMUX16	GT11_1.TXBYPASS8B10B1
TCELL18:IMUX.IMUX17	GT11_1.TXCHARISK1
TCELL18:IMUX.IMUX18	GT11_1.TXCHARDISPMODE1
TCELL18:IMUX.IMUX19	GT11_1.TXCHARDISPVAL1
TCELL18:OUT.BEST0.TMIN	GT11_1.RXDATA8
TCELL18:OUT.BEST1.TMIN	GT11_1.RXDATA9
TCELL18:OUT.BEST2.TMIN	GT11_1.RXDATA10
TCELL18:OUT.BEST3.TMIN	GT11_1.RXDATA11
TCELL18:OUT.BEST4.TMIN	GT11_1.RXDISPERR1
TCELL18:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE1
TCELL18:OUT.BEST6.TMIN	GT11_1.RXCHARISK1
TCELL18:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA1
TCELL18:OUT.SEC0.TMIN	GT11_1.RXRUNDISP1
TCELL18:OUT.SEC1.TMIN	GT11_1.TXRUNDISP1
TCELL18:OUT.SEC2.TMIN	GT11_1.TXKERR1
TCELL18:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT15
TCELL18:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT14
TCELL18:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT13
TCELL18:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT12
TCELL18:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS4
TCELL18:OUT.HALF.BOT5.TMIN	GT11_1.CDRSTATUS5
TCELL18:OUT.HALF.BOT6.TMIN	GT11_1.CDRSTATUS6
TCELL18:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT15
TCELL18:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT14
TCELL18:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT13
TCELL18:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT12
TCELL18:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS4
TCELL18:OUT.HALT.TOP5.TMIN	GT11_1.CDRSTATUS5
TCELL18:OUT.HALT.TOP6.TMIN	GT11_1.CDRSTATUS6
TCELL19:IMUX.IMUX0	GT11_1.TXDATA12
TCELL19:IMUX.IMUX1	GT11_1.TXDATA13
TCELL19:IMUX.IMUX2	GT11_1.TXDATA14
TCELL19:IMUX.IMUX3	GT11_1.TXDATA15
TCELL19:IMUX.IMUX4	GT11_1.TXCRCIN11
TCELL19:IMUX.IMUX5	GT11_1.TXCRCIN10
TCELL19:IMUX.IMUX6	GT11_1.TXCRCIN9
TCELL19:IMUX.IMUX7	GT11_1.TXCRCIN8
TCELL19:IMUX.IMUX8	GT11_1.RXCRCIN11
TCELL19:IMUX.IMUX9	GT11_1.RXCRCIN10
TCELL19:IMUX.IMUX10	GT11_1.RXCRCIN9
TCELL19:IMUX.IMUX11	GT11_1.RXCRCIN8
TCELL19:IMUX.IMUX12	GT11_1.ENPCOMMAALIGN
TCELL19:IMUX.IMUX13	GT11_1.ENMCOMMAALIGN
TCELL19:IMUX.IMUX14	GT11_1.RXDESCRAM64B66BUSE
TCELL19:IMUX.IMUX15	GT11_1.RXBLOCKSYNC64B66BUSE
TCELL19:IMUX.IMUX16	GT11_1.RXCOMMADETUSE
TCELL19:IMUX.IMUX17	GT11_1.RXSLIDE
TCELL19:IMUX.IMUX18	GT11_1.TXCLKSTABLE
TCELL19:IMUX.IMUX19	GT11_1.RXCLKSTABLE
TCELL19:OUT.BEST0.TMIN	GT11_1.RXDATA12
TCELL19:OUT.BEST1.TMIN	GT11_1.RXDATA13
TCELL19:OUT.BEST2.TMIN	GT11_1.RXDATA14
TCELL19:OUT.BEST3.TMIN	GT11_1.RXDATA15
TCELL19:OUT.BEST4.TMIN	GT11_1.RXVCOHIGH
TCELL19:OUT.BEST5.TMIN	GT11_1.TXVCOHIGH
TCELL19:OUT.BEST6.TMIN	GT11_1.RXCALFAIL
TCELL19:OUT.BEST7.TMIN	GT11_1.TXCALFAIL
TCELL19:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT11
TCELL19:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT10
TCELL19:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT9
TCELL19:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT8
TCELL19:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS7
TCELL19:OUT.HALF.BOT5.TMIN	GT11_1.CDRSTATUS8
TCELL19:OUT.HALF.BOT6.TMIN	GT11_1.CDRSTATUS9
TCELL19:OUT.HALF.BOT7.TMIN	GT11_1.CDRSTATUS10
TCELL19:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT11
TCELL19:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT10
TCELL19:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT9
TCELL19:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT8
TCELL19:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS7
TCELL19:OUT.HALT.TOP5.TMIN	GT11_1.CDRSTATUS8
TCELL19:OUT.HALT.TOP6.TMIN	GT11_1.CDRSTATUS9
TCELL19:OUT.HALT.TOP7.TMIN	GT11_1.CDRSTATUS10
TCELL20:IMUX.IMUX0	GT11_1.TXDATA16
TCELL20:IMUX.IMUX1	GT11_1.TXDATA17
TCELL20:IMUX.IMUX2	GT11_1.TXDATA18
TCELL20:IMUX.IMUX3	GT11_1.TXDATA19
TCELL20:IMUX.IMUX4	GT11_1.TXCRCIN23
TCELL20:IMUX.IMUX5	GT11_1.TXCRCIN22
TCELL20:IMUX.IMUX6	GT11_1.TXCRCIN21
TCELL20:IMUX.IMUX7	GT11_1.TXCRCIN20
TCELL20:IMUX.IMUX8	GT11_1.RXCRCIN23
TCELL20:IMUX.IMUX9	GT11_1.RXCRCIN22
TCELL20:IMUX.IMUX10	GT11_1.RXCRCIN21
TCELL20:IMUX.IMUX11	GT11_1.RXCRCIN20
TCELL20:IMUX.IMUX12	GT11_1.TXUSRVCODAC0
TCELL20:IMUX.IMUX13	GT11_1.TXUSRVCODAC1
TCELL20:IMUX.IMUX14	GT11_1.TXUSRVCODAC2
TCELL20:IMUX.IMUX15	GT11_1.TXUSRVCODAC3
TCELL20:IMUX.IMUX16	GT11_1.TXBYPASS8B10B2
TCELL20:IMUX.IMUX17	GT11_1.TXCHARISK2
TCELL20:IMUX.IMUX18	GT11_1.TXCHARDISPMODE2
TCELL20:IMUX.IMUX19	GT11_1.TXCHARDISPVAL2
TCELL20:OUT.BEST0.TMIN	GT11_1.RXDATA16
TCELL20:OUT.BEST1.TMIN	GT11_1.RXDATA17
TCELL20:OUT.BEST2.TMIN	GT11_1.RXDATA18
TCELL20:OUT.BEST3.TMIN	GT11_1.RXDATA19
TCELL20:OUT.BEST4.TMIN	GT11_1.RXDISPERR2
TCELL20:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE2
TCELL20:OUT.BEST6.TMIN	GT11_1.RXCHARISK2
TCELL20:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA2
TCELL20:OUT.SEC0.TMIN	GT11_1.RXRUNDISP2
TCELL20:OUT.SEC1.TMIN	GT11_1.TXRUNDISP2
TCELL20:OUT.SEC2.TMIN	GT11_1.TXKERR2
TCELL20:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT23
TCELL20:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT22
TCELL20:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT21
TCELL20:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT20
TCELL20:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS11
TCELL20:OUT.HALF.BOT5.TMIN	GT11_1.CDRSTATUS12
TCELL20:OUT.HALF.BOT6.TMIN	GT11_1.RXBUFERR
TCELL20:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT23
TCELL20:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT22
TCELL20:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT21
TCELL20:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT20
TCELL20:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS11
TCELL20:OUT.HALT.TOP5.TMIN	GT11_1.CDRSTATUS12
TCELL20:OUT.HALT.TOP6.TMIN	GT11_1.RXBUFERR
TCELL21:IMUX.IMUX0	GT11_1.TXDATA20
TCELL21:IMUX.IMUX1	GT11_1.TXDATA21
TCELL21:IMUX.IMUX2	GT11_1.TXDATA22
TCELL21:IMUX.IMUX3	GT11_1.TXDATA23
TCELL21:IMUX.IMUX4	GT11_1.TXCRCIN19
TCELL21:IMUX.IMUX5	GT11_1.TXCRCIN18
TCELL21:IMUX.IMUX6	GT11_1.TXCRCIN17
TCELL21:IMUX.IMUX7	GT11_1.TXCRCIN16
TCELL21:IMUX.IMUX8	GT11_1.RXCRCIN19
TCELL21:IMUX.IMUX9	GT11_1.RXCRCIN18
TCELL21:IMUX.IMUX10	GT11_1.RXCRCIN17
TCELL21:IMUX.IMUX11	GT11_1.RXCRCIN16
TCELL21:IMUX.IMUX12	GT11_1.TXUSRVCODAC4
TCELL21:IMUX.IMUX13	GT11_1.TXUSRVCODAC5
TCELL21:IMUX.IMUX14	GT11_1.TXUSRVCODAC6
TCELL21:IMUX.IMUX15	GT11_1.TXUSRVCODAC7
TCELL21:IMUX.IMUX16	GT11_1.RXCRCINIT
TCELL21:IMUX.IMUX17	GT11_1.TXCRCINIT
TCELL21:IMUX.IMUX18	GT11_1.TXENOOB
TCELL21:OUT.BEST0.TMIN	GT11_1.RXDATA20
TCELL21:OUT.BEST1.TMIN	GT11_1.RXDATA21
TCELL21:OUT.BEST2.TMIN	GT11_1.RXDATA22
TCELL21:OUT.BEST3.TMIN	GT11_1.RXDATA23
TCELL21:OUT.BEST4.TMIN	GT11_1.DO4
TCELL21:OUT.BEST5.TMIN	GT11_1.DO5
TCELL21:OUT.BEST6.TMIN	GT11_1.DO6
TCELL21:OUT.BEST7.TMIN	GT11_1.DO7
TCELL21:OUT.SEC0.TMIN	GT11_1.CDRSTATUS13
TCELL21:OUT.SEC1.TMIN	GT11_1.CDRSTATUS14
TCELL21:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT19
TCELL21:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT18
TCELL21:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT17
TCELL21:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT16
TCELL21:OUT.HALF.BOT4.TMIN	GT11_1.DO0
TCELL21:OUT.HALF.BOT5.TMIN	GT11_1.DO1
TCELL21:OUT.HALF.BOT6.TMIN	GT11_1.DO2
TCELL21:OUT.HALF.BOT7.TMIN	GT11_1.DO3
TCELL21:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT19
TCELL21:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT18
TCELL21:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT17
TCELL21:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT16
TCELL21:OUT.HALT.TOP4.TMIN	GT11_1.DO0
TCELL21:OUT.HALT.TOP5.TMIN	GT11_1.DO1
TCELL21:OUT.HALT.TOP6.TMIN	GT11_1.DO2
TCELL21:OUT.HALT.TOP7.TMIN	GT11_1.DO3
TCELL22:IMUX.CLK0	GT11_1.RXUSRCLK
TCELL22:IMUX.CLK1	GT11_1.RXUSRCLK2
TCELL22:IMUX.CLK2	GT11_1.TXUSRCLK
TCELL22:IMUX.CLK3	GT11_1.TXUSRCLK2
TCELL22:IMUX.IMUX0	GT11_1.TXDATA24
TCELL22:IMUX.IMUX1	GT11_1.TXDATA25
TCELL22:IMUX.IMUX2	GT11_1.TXDATA26
TCELL22:IMUX.IMUX3	GT11_1.TXDATA27
TCELL22:IMUX.IMUX4	GT11_1.TXCRCIN31
TCELL22:IMUX.IMUX5	GT11_1.TXCRCIN30
TCELL22:IMUX.IMUX6	GT11_1.TXCRCIN29
TCELL22:IMUX.IMUX7	GT11_1.TXCRCIN28
TCELL22:IMUX.IMUX8	GT11_1.RXCRCIN31
TCELL22:IMUX.IMUX9	GT11_1.RXCRCIN30
TCELL22:IMUX.IMUX10	GT11_1.RXCRCIN29
TCELL22:IMUX.IMUX11	GT11_1.RXCRCIN28
TCELL22:IMUX.IMUX12	GT11_1.DADDR0
TCELL22:IMUX.IMUX13	GT11_1.DADDR1
TCELL22:IMUX.IMUX14	GT11_1.DADDR2
TCELL22:IMUX.IMUX15	GT11_1.DADDR3
TCELL22:IMUX.IMUX16	GT11_1.TXBYPASS8B10B3
TCELL22:IMUX.IMUX17	GT11_1.TXCHARISK3
TCELL22:IMUX.IMUX18	GT11_1.TXCHARDISPMODE3
TCELL22:IMUX.IMUX19	GT11_1.TXCHARDISPVAL3
TCELL22:IMUX.IMUX20	GT11_1.TXUSRVCODAC8
TCELL22:IMUX.IMUX21	GT11_1.TXUSRVCODAC9
TCELL22:OUT.BEST0.TMIN	GT11_1.RXDATA24
TCELL22:OUT.BEST1.TMIN	GT11_1.RXDATA25
TCELL22:OUT.BEST2.TMIN	GT11_1.RXDATA26
TCELL22:OUT.BEST3.TMIN	GT11_1.RXDATA27
TCELL22:OUT.BEST4.TMIN	GT11_1.RXDISPERR3
TCELL22:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE3
TCELL22:OUT.BEST6.TMIN	GT11_1.RXCHARISK3
TCELL22:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA3
TCELL22:OUT.SEC0.TMIN	GT11_1.RXRUNDISP3
TCELL22:OUT.SEC1.TMIN	GT11_1.TXRUNDISP3
TCELL22:OUT.SEC2.TMIN	GT11_1.TXKERR3
TCELL22:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT31
TCELL22:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT30
TCELL22:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT29
TCELL22:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT28
TCELL22:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS15
TCELL22:OUT.HALF.BOT5.TMIN	GT11_1.CDRSTATUS16
TCELL22:OUT.HALF.BOT6.TMIN	GT11_1.TXADCN
TCELL22:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT31
TCELL22:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT30
TCELL22:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT29
TCELL22:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT28
TCELL22:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS15
TCELL22:OUT.HALT.TOP5.TMIN	GT11_1.CDRSTATUS16
TCELL22:OUT.HALT.TOP6.TMIN	GT11_1.TXADCN
TCELL23:IMUX.SR0	GT11_1.RXCRCRESET
TCELL23:IMUX.CLK0	GT11_1.RXCRCINTCLK
TCELL23:IMUX.CLK1	GT11_1.TXCRCINTCLK
TCELL23:IMUX.CE0	GT11_1.RXCRCDATAVALID
TCELL23:IMUX.CE1	GT11_1.TXCRCDATAVALID
TCELL23:IMUX.IMUX0	GT11_1.TXDATA28
TCELL23:IMUX.IMUX1	GT11_1.TXDATA29
TCELL23:IMUX.IMUX2	GT11_1.TXDATA30
TCELL23:IMUX.IMUX3	GT11_1.TXDATA31
TCELL23:IMUX.IMUX4	GT11_1.TXCRCIN27
TCELL23:IMUX.IMUX5	GT11_1.TXCRCIN26
TCELL23:IMUX.IMUX6	GT11_1.TXCRCIN25
TCELL23:IMUX.IMUX7	GT11_1.TXCRCIN24
TCELL23:IMUX.IMUX8	GT11_1.RXCRCIN27
TCELL23:IMUX.IMUX9	GT11_1.RXCRCIN26
TCELL23:IMUX.IMUX10	GT11_1.RXCRCIN25
TCELL23:IMUX.IMUX11	GT11_1.RXCRCIN24
TCELL23:IMUX.IMUX12	GT11_1.DI0
TCELL23:IMUX.IMUX13	GT11_1.DI1
TCELL23:IMUX.IMUX14	GT11_1.DI2
TCELL23:IMUX.IMUX15	GT11_1.DI3
TCELL23:IMUX.IMUX16	GT11_1.DI4
TCELL23:IMUX.IMUX17	GT11_1.DI5
TCELL23:IMUX.IMUX18	GT11_1.DI6
TCELL23:IMUX.IMUX19	GT11_1.DI7
TCELL23:IMUX.IMUX20	GT11_1.DADDR4
TCELL23:IMUX.IMUX21	GT11_1.DADDR5
TCELL23:IMUX.IMUX22	GT11_1.DADDR6
TCELL23:IMUX.IMUX23	GT11_1.DADDR7
TCELL23:OUT.BEST0.TMIN	GT11_1.RXDATA28
TCELL23:OUT.BEST1.TMIN	GT11_1.RXDATA29
TCELL23:OUT.BEST2.TMIN	GT11_1.RXDATA30
TCELL23:OUT.BEST3.TMIN	GT11_1.RXDATA31
TCELL23:OUT.BEST4.TMIN	GT11_1.RXRECCLK1
TCELL23:OUT.BEST5.TMIN	GT11_1.RXRECCLK2
TCELL23:OUT.BEST6.TMIN	GT11_1.TXOUTCLK1
TCELL23:OUT.BEST7.TMIN	GT11_1.TXOUTCLK2
TCELL23:OUT.SEC0.TMIN	GT11_1.DRDY
TCELL23:OUT.SEC1.TMIN	GT11_1.TXADCP
TCELL23:OUT.HALF.BOT0.TMIN	GT11_1.TXCRCOUT27
TCELL23:OUT.HALF.BOT1.TMIN	GT11_1.TXCRCOUT26
TCELL23:OUT.HALF.BOT2.TMIN	GT11_1.TXCRCOUT25
TCELL23:OUT.HALF.BOT3.TMIN	GT11_1.TXCRCOUT24
TCELL23:OUT.HALF.BOT4.TMIN	GT11_1.DO8
TCELL23:OUT.HALF.BOT5.TMIN	GT11_1.DO9
TCELL23:OUT.HALF.BOT6.TMIN	GT11_1.DO10
TCELL23:OUT.HALF.BOT7.TMIN	GT11_1.DO11
TCELL23:OUT.HALT.TOP0.TMIN	GT11_1.TXCRCOUT27
TCELL23:OUT.HALT.TOP1.TMIN	GT11_1.TXCRCOUT26
TCELL23:OUT.HALT.TOP2.TMIN	GT11_1.TXCRCOUT25
TCELL23:OUT.HALT.TOP3.TMIN	GT11_1.TXCRCOUT24
TCELL23:OUT.HALT.TOP4.TMIN	GT11_1.DO8
TCELL23:OUT.HALT.TOP5.TMIN	GT11_1.DO9
TCELL23:OUT.HALT.TOP6.TMIN	GT11_1.DO10
TCELL23:OUT.HALT.TOP7.TMIN	GT11_1.DO11
TCELL24:IMUX.SR0	GT11_1.TXCRCRESET
TCELL24:IMUX.CLK0	GT11_1.TXCRCCLK
TCELL24:IMUX.CLK1	GT11_1.RXCRCCLK
TCELL24:IMUX.CLK3	GT11_1.DCLK
TCELL24:IMUX.CE0	GT11_1.DEN
TCELL24:IMUX.CE1	GT11_1.DWE
TCELL24:IMUX.IMUX0	GT11_1.TXDATA32
TCELL24:IMUX.IMUX1	GT11_1.TXDATA33
TCELL24:IMUX.IMUX2	GT11_1.TXDATA34
TCELL24:IMUX.IMUX3	GT11_1.TXDATA35
TCELL24:IMUX.IMUX4	GT11_1.TXCRCIN39
TCELL24:IMUX.IMUX5	GT11_1.TXCRCIN38
TCELL24:IMUX.IMUX6	GT11_1.TXCRCIN37
TCELL24:IMUX.IMUX7	GT11_1.TXCRCIN36
TCELL24:IMUX.IMUX8	GT11_1.RXCRCIN39
TCELL24:IMUX.IMUX9	GT11_1.RXCRCIN38
TCELL24:IMUX.IMUX10	GT11_1.RXCRCIN37
TCELL24:IMUX.IMUX11	GT11_1.RXCRCIN36
TCELL24:IMUX.IMUX12	GT11_1.DI8
TCELL24:IMUX.IMUX13	GT11_1.DI9
TCELL24:IMUX.IMUX14	GT11_1.DI10
TCELL24:IMUX.IMUX15	GT11_1.DI11
TCELL24:IMUX.IMUX16	GT11_1.TXBYPASS8B10B4
TCELL24:IMUX.IMUX17	GT11_1.TXCHARISK4
TCELL24:IMUX.IMUX18	GT11_1.TXCHARDISPMODE4
TCELL24:IMUX.IMUX19	GT11_1.TXCHARDISPVAL4
TCELL24:IMUX.IMUX20	GT11_1.DI12
TCELL24:IMUX.IMUX21	GT11_1.DI13
TCELL24:IMUX.IMUX22	GT11_1.DI14
TCELL24:IMUX.IMUX23	GT11_1.DI15
TCELL24:OUT.BEST0.TMIN	GT11_1.RXDATA32
TCELL24:OUT.BEST1.TMIN	GT11_1.RXDATA33
TCELL24:OUT.BEST2.TMIN	GT11_1.RXDATA34
TCELL24:OUT.BEST3.TMIN	GT11_1.RXDATA35
TCELL24:OUT.BEST4.TMIN	GT11_1.RXDISPERR4
TCELL24:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE4
TCELL24:OUT.BEST6.TMIN	GT11_1.RXCHARISK4
TCELL24:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA4
TCELL24:OUT.SEC0.TMIN	GT11_1.RXRUNDISP4
TCELL24:OUT.SEC1.TMIN	GT11_1.TXRUNDISP4
TCELL24:OUT.SEC2.TMIN	GT11_1.TXKERR4
TCELL24:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT7
TCELL24:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT6
TCELL24:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT5
TCELL24:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT4
TCELL24:OUT.HALF.BOT4.TMIN	GT11_1.CDRSTATUS17
TCELL24:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT7
TCELL24:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT6
TCELL24:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT5
TCELL24:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT4
TCELL24:OUT.HALT.TOP4.TMIN	GT11_1.CDRSTATUS17
TCELL25:IMUX.SR0	GT11_1.RXPMARESET
TCELL25:IMUX.IMUX0	GT11_1.TXDATA36
TCELL25:IMUX.IMUX1	GT11_1.TXDATA37
TCELL25:IMUX.IMUX2	GT11_1.TXDATA38
TCELL25:IMUX.IMUX3	GT11_1.TXDATA39
TCELL25:IMUX.IMUX4	GT11_1.TXCRCIN35
TCELL25:IMUX.IMUX5	GT11_1.TXCRCIN34
TCELL25:IMUX.IMUX6	GT11_1.TXCRCIN33
TCELL25:IMUX.IMUX7	GT11_1.TXCRCIN32
TCELL25:IMUX.IMUX8	GT11_1.RXCRCIN35
TCELL25:IMUX.IMUX9	GT11_1.RXCRCIN34
TCELL25:IMUX.IMUX10	GT11_1.RXCRCIN33
TCELL25:IMUX.IMUX11	GT11_1.RXCRCIN32
TCELL25:IMUX.IMUX12	GT11_1.RXCRCPD
TCELL25:IMUX.IMUX13	GT11_1.TXCRCPD
TCELL25:IMUX.IMUX14	GT11_1.MGTADCSEL0
TCELL25:IMUX.IMUX15	GT11_1.MGTADCSEL1
TCELL25:IMUX.IMUX16	GT11_1.MGTADCSEL2
TCELL25:IMUX.IMUX17	GT11_1.MGTADCSEL3
TCELL25:IMUX.IMUX18	GT11_1.MGTADCSEL4
TCELL25:OUT.BEST0.TMIN	GT11_1.RXDATA36
TCELL25:OUT.BEST1.TMIN	GT11_1.RXDATA37
TCELL25:OUT.BEST2.TMIN	GT11_1.RXDATA38
TCELL25:OUT.BEST3.TMIN	GT11_1.RXDATA39
TCELL25:OUT.BEST4.TMIN	GT11_1.RXREALIGN
TCELL25:OUT.BEST5.TMIN	GT11_1.RXCOMMADET
TCELL25:OUT.SEC0.TMIN	GT11_1.TXFDETSTATE0
TCELL25:OUT.SEC1.TMIN	GT11_1.TXFDETSTATE1
TCELL25:OUT.SEC2.TMIN	GT11_1.TXFDETSTATE2
TCELL25:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT3
TCELL25:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT2
TCELL25:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT1
TCELL25:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT0
TCELL25:OUT.HALF.BOT4.TMIN	GT11_1.DO12
TCELL25:OUT.HALF.BOT5.TMIN	GT11_1.DO13
TCELL25:OUT.HALF.BOT6.TMIN	GT11_1.DO14
TCELL25:OUT.HALF.BOT7.TMIN	GT11_1.DO15
TCELL25:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT3
TCELL25:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT2
TCELL25:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT1
TCELL25:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT0
TCELL25:OUT.HALT.TOP4.TMIN	GT11_1.DO12
TCELL25:OUT.HALT.TOP5.TMIN	GT11_1.DO13
TCELL25:OUT.HALT.TOP6.TMIN	GT11_1.DO14
TCELL25:OUT.HALT.TOP7.TMIN	GT11_1.DO15
TCELL26:IMUX.SR0	GT11_1.TXPMARESET
TCELL26:IMUX.IMUX0	GT11_1.TXDATA40
TCELL26:IMUX.IMUX1	GT11_1.TXDATA41
TCELL26:IMUX.IMUX2	GT11_1.TXDATA42
TCELL26:IMUX.IMUX3	GT11_1.TXDATA43
TCELL26:IMUX.IMUX4	GT11_1.TXCRCIN47
TCELL26:IMUX.IMUX5	GT11_1.TXCRCIN46
TCELL26:IMUX.IMUX6	GT11_1.TXCRCIN45
TCELL26:IMUX.IMUX7	GT11_1.TXCRCIN44
TCELL26:IMUX.IMUX8	GT11_1.RXCRCIN47
TCELL26:IMUX.IMUX9	GT11_1.RXCRCIN46
TCELL26:IMUX.IMUX10	GT11_1.RXCRCIN45
TCELL26:IMUX.IMUX11	GT11_1.RXCRCIN44
TCELL26:IMUX.IMUX12	GT11_1.RXUSRLOCK
TCELL26:IMUX.IMUX13	GT11_1.RXUSRVCOCAL
TCELL26:IMUX.IMUX14	GT11_1.TXUSRLOCK
TCELL26:IMUX.IMUX15	GT11_1.TXUSRVCOCAL
TCELL26:IMUX.IMUX16	GT11_1.TXBYPASS8B10B5
TCELL26:IMUX.IMUX17	GT11_1.TXCHARISK5
TCELL26:IMUX.IMUX18	GT11_1.TXCHARDISPMODE5
TCELL26:IMUX.IMUX19	GT11_1.TXCHARDISPVAL5
TCELL26:OUT.BEST0.TMIN	GT11_1.RXDATA40
TCELL26:OUT.BEST1.TMIN	GT11_1.RXDATA41
TCELL26:OUT.BEST2.TMIN	GT11_1.RXDATA42
TCELL26:OUT.BEST3.TMIN	GT11_1.RXDATA43
TCELL26:OUT.BEST4.TMIN	GT11_1.RXDISPERR5
TCELL26:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE5
TCELL26:OUT.BEST6.TMIN	GT11_1.RXCHARISK5
TCELL26:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA5
TCELL26:OUT.SEC0.TMIN	GT11_1.RXRUNDISP5
TCELL26:OUT.SEC1.TMIN	GT11_1.TXRUNDISP5
TCELL26:OUT.SEC2.TMIN	GT11_1.TXKERR5
TCELL26:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT15
TCELL26:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT14
TCELL26:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT13
TCELL26:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT12
TCELL26:OUT.HALF.BOT4.TMIN	GT11_1.TXFCALSTATE0
TCELL26:OUT.HALF.BOT5.TMIN	GT11_1.TXFCALSTATE1
TCELL26:OUT.HALF.BOT6.TMIN	GT11_1.TXFCALSTATE2
TCELL26:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT15
TCELL26:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT14
TCELL26:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT13
TCELL26:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT12
TCELL26:OUT.HALT.TOP4.TMIN	GT11_1.TXFCALSTATE0
TCELL26:OUT.HALT.TOP5.TMIN	GT11_1.TXFCALSTATE1
TCELL26:OUT.HALT.TOP6.TMIN	GT11_1.TXFCALSTATE2
TCELL27:IMUX.IMUX0	GT11_1.TXDATA44
TCELL27:IMUX.IMUX1	GT11_1.TXDATA45
TCELL27:IMUX.IMUX2	GT11_1.TXDATA46
TCELL27:IMUX.IMUX3	GT11_1.TXDATA47
TCELL27:IMUX.IMUX4	GT11_1.TXCRCIN43
TCELL27:IMUX.IMUX5	GT11_1.TXCRCIN42
TCELL27:IMUX.IMUX6	GT11_1.TXCRCIN41
TCELL27:IMUX.IMUX7	GT11_1.TXCRCIN40
TCELL27:IMUX.IMUX8	GT11_1.RXCRCIN43
TCELL27:IMUX.IMUX9	GT11_1.RXCRCIN42
TCELL27:IMUX.IMUX10	GT11_1.RXCRCIN41
TCELL27:IMUX.IMUX11	GT11_1.RXCRCIN40
TCELL27:IMUX.IMUX12	GT11_1.TXSYNC
TCELL27:IMUX.IMUX17	GT11_1.RXCRCDATAWIDTH0
TCELL27:IMUX.IMUX18	GT11_1.RXCRCDATAWIDTH1
TCELL27:IMUX.IMUX19	GT11_1.RXCRCDATAWIDTH2
TCELL27:IMUX.IMUX20	GT11_1.TXCRCDATAWIDTH0
TCELL27:IMUX.IMUX21	GT11_1.TXCRCDATAWIDTH1
TCELL27:IMUX.IMUX22	GT11_1.TXCRCDATAWIDTH2
TCELL27:OUT.BEST0.TMIN	GT11_1.RXDATA44
TCELL27:OUT.BEST1.TMIN	GT11_1.RXDATA45
TCELL27:OUT.BEST2.TMIN	GT11_1.RXDATA46
TCELL27:OUT.BEST3.TMIN	GT11_1.RXDATA47
TCELL27:OUT.BEST4.TMIN	GT11_1.CHBONDO0
TCELL27:OUT.BEST5.TMIN	GT11_1.CHBONDO1
TCELL27:OUT.BEST6.TMIN	GT11_1.CHBONDO2
TCELL27:OUT.BEST7.TMIN	GT11_1.CHBONDO3
TCELL27:OUT.SEC0.TMIN	GT11_1.CHBONDO4
TCELL27:OUT.SEC1.TMIN	GT11_1.SCANOUT2
TCELL27:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT11
TCELL27:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT10
TCELL27:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT9
TCELL27:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT8
TCELL27:OUT.HALF.BOT4.TMIN	GT11_1.RXCYCLELIMIT
TCELL27:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT11
TCELL27:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT10
TCELL27:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT9
TCELL27:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT8
TCELL27:OUT.HALT.TOP4.TMIN	GT11_1.RXCYCLELIMIT
TCELL28:IMUX.CE0	GT11_1.SCANEN2
TCELL28:IMUX.CE1	GT11_1.SCANMODE2
TCELL28:IMUX.IMUX0	GT11_1.TXDATA48
TCELL28:IMUX.IMUX1	GT11_1.TXDATA49
TCELL28:IMUX.IMUX2	GT11_1.TXDATA50
TCELL28:IMUX.IMUX3	GT11_1.TXDATA51
TCELL28:IMUX.IMUX4	GT11_1.TXCRCIN55
TCELL28:IMUX.IMUX5	GT11_1.TXCRCIN54
TCELL28:IMUX.IMUX6	GT11_1.TXCRCIN53
TCELL28:IMUX.IMUX7	GT11_1.TXCRCIN52
TCELL28:IMUX.IMUX8	GT11_1.RXCRCIN55
TCELL28:IMUX.IMUX9	GT11_1.RXCRCIN54
TCELL28:IMUX.IMUX10	GT11_1.RXCRCIN53
TCELL28:IMUX.IMUX11	GT11_1.RXCRCIN52
TCELL28:IMUX.IMUX12	GT11_1.RXDEC8B10BUSE
TCELL28:IMUX.IMUX13	GT11_1.RXDEC64B66BUSE
TCELL28:IMUX.IMUX14	GT11_1.TESTMEMORY
TCELL28:IMUX.IMUX15	GT11_1.RXIGNOREBTF
TCELL28:IMUX.IMUX16	GT11_1.TXBYPASS8B10B6
TCELL28:IMUX.IMUX17	GT11_1.TXCHARISK6
TCELL28:IMUX.IMUX18	GT11_1.TXCHARDISPMODE6
TCELL28:IMUX.IMUX19	GT11_1.TXCHARDISPVAL6
TCELL28:OUT.BEST0.TMIN	GT11_1.RXDATA48
TCELL28:OUT.BEST1.TMIN	GT11_1.RXDATA49
TCELL28:OUT.BEST2.TMIN	GT11_1.RXDATA50
TCELL28:OUT.BEST3.TMIN	GT11_1.RXDATA51
TCELL28:OUT.BEST4.TMIN	GT11_1.RXDISPERR6
TCELL28:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE6
TCELL28:OUT.BEST6.TMIN	GT11_1.RXCHARISK6
TCELL28:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA6
TCELL28:OUT.SEC0.TMIN	GT11_1.RXRUNDISP6
TCELL28:OUT.SEC1.TMIN	GT11_1.TXRUNDISP6
TCELL28:OUT.SEC2.TMIN	GT11_1.TXKERR6
TCELL28:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT23
TCELL28:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT22
TCELL28:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT21
TCELL28:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT20
TCELL28:OUT.HALF.BOT4.TMIN	GT11_1.TXCOARSEST
TCELL28:OUT.HALF.BOT5.TMIN	GT11_1.TXENABLECAL
TCELL28:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT23
TCELL28:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT22
TCELL28:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT21
TCELL28:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT20
TCELL28:OUT.HALT.TOP4.TMIN	GT11_1.TXCOARSEST
TCELL28:OUT.HALT.TOP5.TMIN	GT11_1.TXENABLECAL
TCELL29:IMUX.CE0	GT11_1.SCANMODE0
TCELL29:IMUX.CE1	GT11_1.SCANMODE1
TCELL29:IMUX.IMUX0	GT11_1.TXDATA52
TCELL29:IMUX.IMUX1	GT11_1.TXDATA53
TCELL29:IMUX.IMUX2	GT11_1.TXDATA54
TCELL29:IMUX.IMUX3	GT11_1.TXDATA55
TCELL29:IMUX.IMUX4	GT11_1.TXCRCIN51
TCELL29:IMUX.IMUX5	GT11_1.TXCRCIN50
TCELL29:IMUX.IMUX6	GT11_1.TXCRCIN49
TCELL29:IMUX.IMUX7	GT11_1.TXCRCIN48
TCELL29:IMUX.IMUX8	GT11_1.RXCRCIN51
TCELL29:IMUX.IMUX9	GT11_1.RXCRCIN50
TCELL29:IMUX.IMUX10	GT11_1.RXCRCIN49
TCELL29:IMUX.IMUX11	GT11_1.RXCRCIN48
TCELL29:IMUX.IMUX12	GT11_1.CHBONDI0
TCELL29:IMUX.IMUX13	GT11_1.CHBONDI1
TCELL29:IMUX.IMUX14	GT11_1.CHBONDI2
TCELL29:IMUX.IMUX15	GT11_1.CHBONDI3
TCELL29:IMUX.IMUX16	GT11_1.CHBONDI4
TCELL29:OUT.BEST0.TMIN	GT11_1.RXDATA52
TCELL29:OUT.BEST1.TMIN	GT11_1.RXDATA53
TCELL29:OUT.BEST2.TMIN	GT11_1.RXDATA54
TCELL29:OUT.BEST3.TMIN	GT11_1.RXDATA55
TCELL29:OUT.BEST4.TMIN	GT11_1.RXSTATUS5
TCELL29:OUT.BEST5.TMIN	GT11_1.TXBUFERR
TCELL29:OUT.BEST6.TMIN	GT11_1.SCANOUT0
TCELL29:OUT.BEST7.TMIN	GT11_1.SCANOUT1
TCELL29:OUT.SEC0.TMIN	GT11_1.RXFDETSTATE0
TCELL29:OUT.SEC1.TMIN	GT11_1.RXFDETSTATE1
TCELL29:OUT.SEC2.TMIN	GT11_1.RXFDETSTATE2
TCELL29:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT19
TCELL29:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT18
TCELL29:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT17
TCELL29:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT16
TCELL29:OUT.HALF.BOT4.TMIN	GT11_1.TXCYCLELIMIT
TCELL29:OUT.HALF.BOT5.TMIN	GT11_1.RXSTATUS3
TCELL29:OUT.HALF.BOT6.TMIN	GT11_1.RXSTATUS4
TCELL29:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT19
TCELL29:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT18
TCELL29:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT17
TCELL29:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT16
TCELL29:OUT.HALT.TOP4.TMIN	GT11_1.TXCYCLELIMIT
TCELL29:OUT.HALT.TOP5.TMIN	GT11_1.RXSTATUS3
TCELL29:OUT.HALT.TOP6.TMIN	GT11_1.RXSTATUS4
TCELL30:IMUX.CE0	GT11_1.SCANEN0
TCELL30:IMUX.CE1	GT11_1.SCANEN1
TCELL30:IMUX.IMUX0	GT11_1.TXDATA56
TCELL30:IMUX.IMUX1	GT11_1.TXDATA57
TCELL30:IMUX.IMUX2	GT11_1.TXDATA58
TCELL30:IMUX.IMUX3	GT11_1.TXDATA59
TCELL30:IMUX.IMUX4	GT11_1.TXCRCIN63
TCELL30:IMUX.IMUX5	GT11_1.TXCRCIN62
TCELL30:IMUX.IMUX6	GT11_1.TXCRCIN61
TCELL30:IMUX.IMUX7	GT11_1.TXCRCIN60
TCELL30:IMUX.IMUX8	GT11_1.RXCRCIN63
TCELL30:IMUX.IMUX9	GT11_1.RXCRCIN62
TCELL30:IMUX.IMUX10	GT11_1.RXCRCIN61
TCELL30:IMUX.IMUX11	GT11_1.RXCRCIN60
TCELL30:IMUX.IMUX12	GT11_1.TXENC8B10BUSE
TCELL30:IMUX.IMUX13	GT11_1.TXENC64B66BUSE
TCELL30:IMUX.IMUX14	GT11_1.TXSCRAM64B66BUSE
TCELL30:IMUX.IMUX15	GT11_1.TXGEARBOX64B66BUSE
TCELL30:IMUX.IMUX16	GT11_1.TXBYPASS8B10B7
TCELL30:IMUX.IMUX17	GT11_1.TXCHARISK7
TCELL30:IMUX.IMUX18	GT11_1.TXCHARDISPMODE7
TCELL30:IMUX.IMUX19	GT11_1.TXCHARDISPVAL7
TCELL30:OUT.BEST0.TMIN	GT11_1.RXDATA56
TCELL30:OUT.BEST1.TMIN	GT11_1.RXDATA57
TCELL30:OUT.BEST2.TMIN	GT11_1.RXDATA58
TCELL30:OUT.BEST3.TMIN	GT11_1.RXDATA59
TCELL30:OUT.BEST4.TMIN	GT11_1.RXDISPERR7
TCELL30:OUT.BEST5.TMIN	GT11_1.RXNOTINTABLE7
TCELL30:OUT.BEST6.TMIN	GT11_1.RXCHARISK7
TCELL30:OUT.BEST7.TMIN	GT11_1.RXCHARISCOMMA7
TCELL30:OUT.SEC0.TMIN	GT11_1.RXRUNDISP7
TCELL30:OUT.SEC1.TMIN	GT11_1.TXRUNDISP7
TCELL30:OUT.SEC2.TMIN	GT11_1.TXKERR7
TCELL30:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT31
TCELL30:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT30
TCELL30:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT29
TCELL30:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT28
TCELL30:OUT.HALF.BOT4.TMIN	GT11_1.RXFCALSTATE0
TCELL30:OUT.HALF.BOT5.TMIN	GT11_1.RXFCALSTATE1
TCELL30:OUT.HALF.BOT6.TMIN	GT11_1.RXFCALSTATE2
TCELL30:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT31
TCELL30:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT30
TCELL30:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT29
TCELL30:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT28
TCELL30:OUT.HALT.TOP4.TMIN	GT11_1.RXFCALSTATE0
TCELL30:OUT.HALT.TOP5.TMIN	GT11_1.RXFCALSTATE1
TCELL30:OUT.HALT.TOP6.TMIN	GT11_1.RXFCALSTATE2
TCELL31:IMUX.IMUX0	GT11_1.TXDATA60
TCELL31:IMUX.IMUX1	GT11_1.TXDATA61
TCELL31:IMUX.IMUX2	GT11_1.TXDATA62
TCELL31:IMUX.IMUX3	GT11_1.TXDATA63
TCELL31:IMUX.IMUX4	GT11_1.TXCRCIN59
TCELL31:IMUX.IMUX5	GT11_1.TXCRCIN58
TCELL31:IMUX.IMUX6	GT11_1.TXCRCIN57
TCELL31:IMUX.IMUX7	GT11_1.TXCRCIN56
TCELL31:IMUX.IMUX8	GT11_1.RXCRCIN59
TCELL31:IMUX.IMUX9	GT11_1.RXCRCIN58
TCELL31:IMUX.IMUX10	GT11_1.RXCRCIN57
TCELL31:IMUX.IMUX11	GT11_1.RXCRCIN56
TCELL31:IMUX.IMUX12	GT11_1.ENCHANSYNC
TCELL31:IMUX.IMUX13	GT11_1.POWERDOWN
TCELL31:IMUX.IMUX14	GT11_1.RXPOLARITY
TCELL31:IMUX.IMUX15	GT11_1.LOOPBACK0
TCELL31:IMUX.IMUX16	GT11_1.LOOPBACK1
TCELL31:IMUX.IMUX17	GT11_1.TXPOLARITY
TCELL31:IMUX.IMUX18	GT11_1.TXINHIBIT
TCELL31:IMUX.IMUX19	GT11_1.SCANIN0
TCELL31:IMUX.IMUX20	GT11_1.SCANIN1
TCELL31:IMUX.IMUX21	GT11_1.SCANIN2
TCELL31:OUT.BEST0.TMIN	GT11_1.RXDATA60
TCELL31:OUT.BEST1.TMIN	GT11_1.RXDATA61
TCELL31:OUT.BEST2.TMIN	GT11_1.RXDATA62
TCELL31:OUT.BEST3.TMIN	GT11_1.RXDATA63
TCELL31:OUT.BEST4.TMIN	GT11_1.RXSTATUS0
TCELL31:OUT.BEST5.TMIN	GT11_1.RXSTATUS1
TCELL31:OUT.BEST6.TMIN	GT11_1.RXSTATUS2
TCELL31:OUT.SEC0.TMIN	GT11_1.RXCOARSEST
TCELL31:OUT.SEC1.TMIN	GT11_1.RXENABLECAL
TCELL31:OUT.HALF.BOT0.TMIN	GT11_1.RXCRCOUT27
TCELL31:OUT.HALF.BOT1.TMIN	GT11_1.RXCRCOUT26
TCELL31:OUT.HALF.BOT2.TMIN	GT11_1.RXCRCOUT25
TCELL31:OUT.HALF.BOT3.TMIN	GT11_1.RXCRCOUT24
TCELL31:OUT.HALF.BOT4.TMIN	GT11_1.RXLOCK
TCELL31:OUT.HALF.BOT5.TMIN	GT11_1.TXLOCK
TCELL31:OUT.HALF.BOT6.TMIN	GT11_1.RXLOCKUPDATE
TCELL31:OUT.HALF.BOT7.TMIN	GT11_1.TXLOCKUPDATE
TCELL31:OUT.HALT.TOP0.TMIN	GT11_1.RXCRCOUT27
TCELL31:OUT.HALT.TOP1.TMIN	GT11_1.RXCRCOUT26
TCELL31:OUT.HALT.TOP2.TMIN	GT11_1.RXCRCOUT25
TCELL31:OUT.HALT.TOP3.TMIN	GT11_1.RXCRCOUT24
TCELL31:OUT.HALT.TOP4.TMIN	GT11_1.RXLOCK
TCELL31:OUT.HALT.TOP5.TMIN	GT11_1.TXLOCK
TCELL31:OUT.HALT.TOP6.TMIN	GT11_1.RXLOCKUPDATE
TCELL31:OUT.HALT.TOP7.TMIN	GT11_1.TXLOCKUPDATE

Bitstream

virtex4 MGT bittile 0
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[15] GT11_0:TXCRCINITVAL[31]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[14] GT11_0:TXCRCINITVAL[30]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[13] GT11_0:TXCRCINITVAL[29]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[12] GT11_0:TXCRCINITVAL[28]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[11] GT11_0:TXCRCINITVAL[27]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[10] GT11_0:TXCRCINITVAL[26]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[9] GT11_0:TXCRCINITVAL[25]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[8] GT11_0:TXCRCINITVAL[24]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[7] GT11_0:TXCRCINITVAL[23]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[6] GT11_0:TXCRCINITVAL[22]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[5] GT11_0:TXCRCINITVAL[21]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[4] GT11_0:TXCRCINITVAL[20]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[3] GT11_0:TXCRCINITVAL[19]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[2] GT11_0:TXCRCINITVAL[18]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[1] GT11_0:TXCRCINITVAL[17]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP58[0] GT11_0:TXCRCINITVAL[16]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[15] GT11_0:TXCRCINITVAL[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[14] GT11_0:TXCRCINITVAL[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[13] GT11_0:TXCRCINITVAL[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[12] GT11_0:TXCRCINITVAL[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[11] GT11_0:TXCRCINITVAL[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[10] GT11_0:TXCRCINITVAL[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[9] GT11_0:TXCRCINITVAL[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[8] GT11_0:TXCRCINITVAL[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[7] GT11_0:TXCRCINITVAL[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[6] GT11_0:TXCRCINITVAL[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[5] GT11_0:TXCRCINITVAL[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[4] GT11_0:TXCRCINITVAL[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[3] GT11_0:TXCRCINITVAL[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[2] GT11_0:TXCRCINITVAL[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[1] GT11_0:TXCRCINITVAL[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP50[0] GT11_0:TXCRCINITVAL[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[15] GT11_0:RXCRCINITVAL[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[14] GT11_0:RXCRCINITVAL[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[13] GT11_0:RXCRCINITVAL[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[12] GT11_0:RXCRCINITVAL[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[11] GT11_0:RXCRCINITVAL[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[10] GT11_0:RXCRCINITVAL[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[9] GT11_0:RXCRCINITVAL[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[8] GT11_0:RXCRCINITVAL[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[7] GT11_0:RXCRCINITVAL[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[6] GT11_0:RXCRCINITVAL[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[5] GT11_0:RXCRCINITVAL[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[4] GT11_0:RXCRCINITVAL[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[3] GT11_0:RXCRCINITVAL[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[2] GT11_0:RXCRCINITVAL[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[1] GT11_0:RXCRCINITVAL[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP48[0] GT11_0:RXCRCINITVAL[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[15] GT11_0:RXCRCINITVAL[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[14] GT11_0:RXCRCINITVAL[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[13] GT11_0:RXCRCINITVAL[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[12] GT11_0:RXCRCINITVAL[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[11] GT11_0:RXCRCINITVAL[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[10] GT11_0:RXCRCINITVAL[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[9] GT11_0:RXCRCINITVAL[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[8] GT11_0:RXCRCINITVAL[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[7] GT11_0:RXCRCINITVAL[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[6] GT11_0:RXCRCINITVAL[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[5] GT11_0:RXCRCINITVAL[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[4] GT11_0:RXCRCINITVAL[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[3] GT11_0:RXCRCINITVAL[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[2] GT11_0:RXCRCINITVAL[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[1] GT11_0:RXCRCINITVAL[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP40[0] GT11_0:RXCRCINITVAL[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 1
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:AUTO_CAL GT11_0:DRP78[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[14] GT11_0:VCODAC_INIT[9]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[13] GT11_0:VCODAC_INIT[8]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[12] GT11_0:VCODAC_INIT[7]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[11] GT11_0:VCODAC_INIT[6]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[10] GT11_0:VCODAC_INIT[5]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[9] GT11_0:VCODAC_INIT[4]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[8] GT11_0:VCODAC_INIT[3]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[7] GT11_0:VCODAC_INIT[2]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[6] GT11_0:VCODAC_INIT[1]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[5] GT11_0:VCODAC_INIT[0]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[4] GT11_0:SLOWDOWN_CAL[1]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[3] GT11_0:SLOWDOWN_CAL[0]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:BYPASS_FDET GT11_0:DRP78[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[1] GT11_0:LOOPCAL_WAIT[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP78[0] GT11_0:LOOPCAL_WAIT[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:BYPASS_CAL GT11_0:DRP70[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[14] GT11_0:FDET_HYS_CAL[2]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[13] GT11_0:FDET_HYS_CAL[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[12] GT11_0:FDET_HYS_CAL[0]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[11] GT11_0:FDET_LCK_CAL[2]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[10] GT11_0:FDET_LCK_CAL[1]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[9] GT11_0:FDET_LCK_CAL[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[8] GT11_0:FDET_HYS_SEL[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[7] GT11_0:FDET_HYS_SEL[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[6] GT11_0:FDET_HYS_SEL[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[5] GT11_0:FDET_LCK_SEL[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[4] GT11_0:FDET_LCK_SEL[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[3] GT11_0:FDET_LCK_SEL[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP70[2] GT11_0:VCO_CTRL_ENABLE
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CYCLE_LIMIT_SEL[1] GT11_0:DRP70[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CYCLE_LIMIT_SEL[0] GT11_0:DRP70[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[15] GT11_0:RXAUTO_CAL
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[14] GT11_0:RXVCODAC_INIT[9]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[13] GT11_0:RXVCODAC_INIT[8]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[12] GT11_0:RXVCODAC_INIT[7]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[11] GT11_0:RXVCODAC_INIT[6]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[10] GT11_0:RXVCODAC_INIT[5]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[9] GT11_0:RXVCODAC_INIT[4]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[8] GT11_0:RXVCODAC_INIT[3]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[7] GT11_0:RXVCODAC_INIT[2]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[6] GT11_0:RXVCODAC_INIT[1]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[5] GT11_0:RXVCODAC_INIT[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[4] GT11_0:RXSLOWDOWN_CAL[1]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[3] GT11_0:RXSLOWDOWN_CAL[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[2] GT11_0:RXBYPASS_FDET
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[1] GT11_0:RXLOOPCAL_WAIT[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP68[0] GT11_0:RXLOOPCAL_WAIT[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[15] GT11_0:RXBYPASS_CAL
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[14] GT11_0:RXFDET_HYS_CAL[2]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[13] GT11_0:RXFDET_HYS_CAL[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[12] GT11_0:RXFDET_HYS_CAL[0]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[11] GT11_0:RXFDET_LCK_CAL[2]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[10] GT11_0:RXFDET_LCK_CAL[1]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[9] GT11_0:RXFDET_LCK_CAL[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[8] GT11_0:RXFDET_HYS_SEL[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[7] GT11_0:RXFDET_HYS_SEL[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[6] GT11_0:RXFDET_HYS_SEL[0]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[5] GT11_0:RXFDET_LCK_SEL[2]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[4] GT11_0:RXFDET_LCK_SEL[1]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[3] GT11_0:RXFDET_LCK_SEL[0]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[2] GT11_0:RXVCO_CTRL_ENABLE
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[1] GT11_0:RXCYCLE_LIMIT_SEL[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP60[0] GT11_0:RXCYCLE_LIMIT_SEL[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 2
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[14] GT11_0:RXOUTDIV2SEL[5]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[13] GT11_0:RXOUTDIV2SEL[3]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[12] GT11_0:RXOUTDIV2SEL[1]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[11] GT11_0:RXPLLNDIVSEL[2]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[10] GT11_0:RXPLLNDIVSEL[1]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[9] GT11_0:RXPLLNDIVSEL[0]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[7] GT11_0:RXCLMODE[1]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[6] GT11_0:RXCLMODE[0]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[5] GT11_0:RXLOOPFILT[3]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[4] GT11_0:RXLOOPFILT[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[3] GT11_0:RXLOOPFILT[1]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[2] GT11_0:RXLOOPFILT[0]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[1] GT11_0:RXDIGRX
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP59[0] GT11_0:RXPFDTX
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[15] GT11_0:RXTUNE[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[14] GT11_0:RXTUNE[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[13] GT11_0:RXTUNE[10]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[12] GT11_0:RXTUNE[9]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[11] GT11_0:RXTUNE[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[10] GT11_0:RXTUNE[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[9] GT11_0:RXTUNE[6]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[8] GT11_0:RXTUNE[5]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[7] GT11_0:RXTUNE[4]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[6] GT11_0:RXTUNE[3]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[5] GT11_0:RXTUNE[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[4] GT11_0:RXTUNE[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[3] GT11_0:RXTUNE[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[2] GT11_0:RXSLOSEL
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[1] GT11_0:RXDACSEL
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP51[0] GT11_0:RXCPSEL
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[15] GT11_0:RXDACTST
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[13] GT11_0:RXOUTDIV2SEL[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[12] GT11_0:RXOUTDIV2SEL[2]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[11] GT11_0:RXOUTDIV2SEL[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[10] GT11_0:RXCTRL1[9]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[9] GT11_0:RXCTRL1[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[8] GT11_0:RXCTRL1[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[7] GT11_0:RXCTRL1[6]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[6] GT11_0:RXCTRL1[5]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[5] GT11_0:RXCTRL1[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[4] GT11_0:RXCTRL1[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[3] GT11_0:RXCTRL1[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[2] GT11_0:RXCTRL1[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[1] GT11_0:RXCTRL1[0]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP49[0] GT11_0:RXQPPD
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[15] GT11_0:RXCMFPD
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[14] GT11_0:RXVCOPD
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[13] GT11_0:RXADCADJPD
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[12] GT11_0:RXDIVPD
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[11] GT11_0:RXBIASPD
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[10] GT11_0:RXVCOBUFPD
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[9] GT11_0:RXDIVBUFPD
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[8] GT11_0:RXAPD
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[7] GT11_0:RXAPTST
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[6] GT11_0:RXCMFTST
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[5] GT11_0:RXFILTTST
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[4] GT11_0:RXDIVTST
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[3] GT11_0:RXPFDTST
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[2] GT11_0:RXVCOBUFTST
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[1] GT11_0:RXDIVBUFTST
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP41[0] GT11_0:RXVCOTST
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 3
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[15] GT11_0:PCOMMA_VALUE[31]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[14] GT11_0:PCOMMA_VALUE[30]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[13] GT11_0:PCOMMA_VALUE[29]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[12] GT11_0:PCOMMA_VALUE[28]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[11] GT11_0:PCOMMA_VALUE[27]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[10] GT11_0:PCOMMA_VALUE[26]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[9] GT11_0:PCOMMA_VALUE[25]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[8] GT11_0:PCOMMA_VALUE[24]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[7] GT11_0:PCOMMA_VALUE[23]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[6] GT11_0:PCOMMA_VALUE[22]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[5] GT11_0:PCOMMA_VALUE[21]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[4] GT11_0:PCOMMA_VALUE[20]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[3] GT11_0:PCOMMA_VALUE[19]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[2] GT11_0:PCOMMA_VALUE[18]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[1] GT11_0:PCOMMA_VALUE[17]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP79[0] GT11_0:PCOMMA_VALUE[16]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[15] GT11_0:PCOMMA_VALUE[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[14] GT11_0:PCOMMA_VALUE[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[13] GT11_0:PCOMMA_VALUE[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[12] GT11_0:PCOMMA_VALUE[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[11] GT11_0:PCOMMA_VALUE[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[10] GT11_0:PCOMMA_VALUE[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[9] GT11_0:PCOMMA_VALUE[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[8] GT11_0:PCOMMA_VALUE[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[7] GT11_0:PCOMMA_VALUE[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[6] GT11_0:PCOMMA_VALUE[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[5] GT11_0:PCOMMA_VALUE[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[4] GT11_0:PCOMMA_VALUE[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[3] GT11_0:PCOMMA_VALUE[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[2] GT11_0:PCOMMA_VALUE[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[1] GT11_0:PCOMMA_VALUE[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP71[0] GT11_0:PCOMMA_VALUE[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[15] GT11_0:MCOMMA_VALUE[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[14] GT11_0:MCOMMA_VALUE[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[13] GT11_0:MCOMMA_VALUE[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[12] GT11_0:MCOMMA_VALUE[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[11] GT11_0:MCOMMA_VALUE[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[10] GT11_0:MCOMMA_VALUE[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[9] GT11_0:MCOMMA_VALUE[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[8] GT11_0:MCOMMA_VALUE[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[7] GT11_0:MCOMMA_VALUE[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[6] GT11_0:MCOMMA_VALUE[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[5] GT11_0:MCOMMA_VALUE[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[4] GT11_0:MCOMMA_VALUE[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[3] GT11_0:MCOMMA_VALUE[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[2] GT11_0:MCOMMA_VALUE[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[1] GT11_0:MCOMMA_VALUE[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP69[0] GT11_0:MCOMMA_VALUE[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[15] GT11_0:MCOMMA_VALUE[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[14] GT11_0:MCOMMA_VALUE[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[13] GT11_0:MCOMMA_VALUE[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[12] GT11_0:MCOMMA_VALUE[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[11] GT11_0:MCOMMA_VALUE[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[10] GT11_0:MCOMMA_VALUE[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[9] GT11_0:MCOMMA_VALUE[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[8] GT11_0:MCOMMA_VALUE[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[7] GT11_0:MCOMMA_VALUE[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[6] GT11_0:MCOMMA_VALUE[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[5] GT11_0:MCOMMA_VALUE[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[4] GT11_0:MCOMMA_VALUE[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[3] GT11_0:MCOMMA_VALUE[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[2] GT11_0:MCOMMA_VALUE[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[1] GT11_0:MCOMMA_VALUE[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP61[0] GT11_0:MCOMMA_VALUE[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 4
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[15] GT11_0:RESERVED_CM2[21]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[14] GT11_0:RESERVED_CM2[20]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[13] GT11_0:RESERVED_CM2[19]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[12] GT11_0:RESERVED_CM2[18]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[11] GT11_0:RESERVED_CM2[17]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[10] GT11_0:RESERVED_CM2[16]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[9] GT11_0:RESERVED_CM2[15]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[8] GT11_0:RESERVED_CM2[14]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[7] GT11_0:RESERVED_CM2[13]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[6] GT11_0:RESERVED_CM2[12]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[5] GT11_0:RESERVED_CM2[11]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[4] GT11_0:RESERVED_CM2[10]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[3] GT11_0:RESERVED_CM2[9]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[2] GT11_0:RESERVED_CM2[8]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[1] GT11_0:RESERVED_CM2[7]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5A[0] GT11_0:RESERVED_CM2[6]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[15] GT11_0:RESERVED_CM2[5]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[14] GT11_0:RESERVED_CM2[4]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[13] GT11_0:RESERVED_CM2[3]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[12] GT11_0:RESERVED_CM2[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[11] GT11_0:RESERVED_CM2[1]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP52[10] GT11_0:RESERVED_CM2[0]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[9] GT11_0:DRP52[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[8] GT11_0:DRP52[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[7] GT11_0:DRP52[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[6] GT11_0:DRP52[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[5] GT11_0:DRP52[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[4] GT11_0:DRP52[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[3] GT11_0:DRP52[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[2] GT11_0:DRP52[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[1] GT11_0:DRP52[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA_10B_MASK[0] GT11_0:DRP52[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[15] GT11_0:RESERVED_CM[23]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[14] GT11_0:RESERVED_CM[22]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[13] GT11_0:RESERVED_CM[21]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[12] GT11_0:RESERVED_CM[20]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[11] GT11_0:RESERVED_CM[19]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[10] GT11_0:RESERVED_CM[18]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[9] GT11_0:RESERVED_CM[17]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[8] GT11_0:RESERVED_CM[16]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[7] GT11_0:RESERVED_CM[15]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[6] GT11_0:RESERVED_CM[14]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[5] GT11_0:RESERVED_CM[13]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[4] GT11_0:RESERVED_CM[12]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[3] GT11_0:RESERVED_CM[11]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[2] GT11_0:RESERVED_CM[10]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[1] GT11_0:RESERVED_CM[9]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4A[0] GT11_0:RESERVED_CM[8]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[15] GT11_0:RESERVED_CM[7]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[14] GT11_0:RESERVED_CM[6]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[13] GT11_0:RESERVED_CM[5]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[12] GT11_0:RESERVED_CM[4]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[11] GT11_0:RESERVED_CM[3]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[10] GT11_0:RESERVED_CM[2]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[9] GT11_0:RESERVED_CM[1]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[8] GT11_0:RESERVED_CM[0]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:COMMA32 GT11_0:DRP42[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[6] GT11_0:PCOMMA_DETECT
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP42[5] GT11_0:MCOMMA_DETECT
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DEC_VALID_COMMA_ONLY GT11_0:DRP42[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DEC_PCOMMA_DETECT GT11_0:DRP42[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DEC_MCOMMA_DETECT GT11_0:DRP42[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:ALIGN_COMMA_WORD[1] GT11_0:DRP42[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:ALIGN_COMMA_WORD[0] GT11_0:DRP42[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 5
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[15] GT11_0:RXMODE[5]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[14] GT11_0:RXMODE[4]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[13] GT11_0:RXMODE[3]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[12] GT11_0:RXMODE[2]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[11] GT11_0:RXMODE[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[10] GT11_0:RXMODE[0]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[9] GT11_0:PMA_BIT_SLIP
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[8] GT11_0:RXASYNCDIVIDE[1]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[7] GT11_0:RXASYNCDIVIDE[0]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[6] GT11_0:RXCLKMODE[5]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[5] GT11_0:RXCLKMODE[4]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[4] GT11_0:RXCLKMODE[3]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[3] GT11_0:RXCLKMODE[2]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[2] GT11_0:RXCLKMODE[1]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[1] GT11_0:RXCLKMODE[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7A[0] GT11_0:RXLB
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[15] GT11_0:RXFETUNE[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[14] GT11_0:RXFETUNE[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[13] GT11_0:RXRCPADJ[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[12] GT11_0:RXRCPADJ[1]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[11] GT11_0:RXRCPADJ[0]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[10] GT11_0:RXRIBADJ[1]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[9] GT11_0:RXRIBADJ[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[8] GT11_0:RXAFEEQ[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[7] GT11_0:RXAFEEQ[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[6] GT11_0:RXAFEEQ[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[5] GT11_0:RXAFEEQ[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[4] GT11_0:RXAFEEQ[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[3] GT11_0:RXAFEEQ[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[2] GT11_0:RXAFEEQ[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[1] GT11_0:RXAFEEQ[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP72[0] GT11_0:RXAFEEQ[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[15] GT11_0:RXCMADJ[1]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[14] GT11_0:RXCMADJ[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[13] GT11_0:RXCDRLOS[5]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[12] GT11_0:RXCDRLOS[4]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[11] GT11_0:RXCDRLOS[3]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[10] GT11_0:RXCDRLOS[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[9] GT11_0:RXCDRLOS[1]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[8] GT11_0:RXCDRLOS[0]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[7] GT11_0:RXTADJ
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[6] GT11_0:RXDCCOUPLE
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[4] GT11_0:RXLKADJ[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[3] GT11_0:RXLKADJ[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[2] GT11_0:RXLKADJ[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[1] GT11_0:RXLKADJ[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6A[0] GT11_0:RXLKADJ[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[15] GT11_0:RXDIGRESET
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[14] GT11_0:RXFECONTROL2[2]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[13] GT11_0:RXFECONTROL2[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[12] GT11_0:RXFECONTROL2[0]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[11] GT11_0:RXCPTST
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[10] GT11_0:RXPDDTST
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[9] GT11_0:RXACTST
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[8] GT11_0:RXAFETST
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[7] GT11_0:RXFECONTROL1[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[6] GT11_0:RXFECONTROL1[0]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[5] GT11_0:RXLKAPD
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[4] GT11_0:RXRSDPD
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[3] GT11_0:RXRCPPD
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[2] GT11_0:RXRPDPD
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[1] GT11_0:RXAFEPD
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP62[0] GT11_0:RXPD
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 6
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[15] GT11_0:RXRECCLK1_USE_SYNC
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[14] GT11_0:TXOUTCLK1_USE_SYNC
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[13] GT11_0:TXCLK0_FORCE_PMACLK
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[12] GT11_0:RXCLK0_FORCE_PMACLK
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[11] GT11_0:TX_CLOCK_DIVIDER[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[10] GT11_0:TX_CLOCK_DIVIDER[0]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[9] GT11_0:RX_CLOCK_DIVIDER[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[8] GT11_0:RX_CLOCK_DIVIDER[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[7] GT11_0:TXCRCENABLE
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[6] GT11_0:TXCRCSAMECLOCK
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[5] GT11_0:TXCRCINVERTGEN
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[4] GT11_0:TXCRCCLOCKDOUBLE
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[3] GT11_0:RXCRCENABLE
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[2] GT11_0:RXCRCSAMECLOCK
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[1] GT11_0:RXCRCINVERTGEN
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5B[0] GT11_0:RXCRCCLOCKDOUBLE
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[15] GT11_0:RXFDCAL_CLOCK_DIVIDE[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[14] GT11_0:RXFDCAL_CLOCK_DIVIDE[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[13] GT11_0:TXFDCAL_CLOCK_DIVIDE[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[12] GT11_0:TXFDCAL_CLOCK_DIVIDE[0]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[11] GT11_0:RXBY_32
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[10] GT11_0:REPEATER
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[9] GT11_0:ENABLE_DCDR
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[8] GT11_0:SAMPLE_8X
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DCDR_FILTER[2] GT11_0:DRP53[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DCDR_FILTER[1] GT11_0:DRP53[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DCDR_FILTER[0] GT11_0:DRP53[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[4] GT11_0:RXUSRDIVISOR[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[3] GT11_0:RXUSRDIVISOR[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[2] GT11_0:RXUSRDIVISOR[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[1] GT11_0:RXUSRDIVISOR[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP53[0] GT11_0:RXUSRDIVISOR[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[15] GT11_0:SH_INVALID_CNT_MAX[7]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[14] GT11_0:SH_INVALID_CNT_MAX[6]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[13] GT11_0:SH_INVALID_CNT_MAX[5]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[12] GT11_0:SH_INVALID_CNT_MAX[4]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[11] GT11_0:SH_INVALID_CNT_MAX[3]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[10] GT11_0:SH_INVALID_CNT_MAX[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[9] GT11_0:SH_INVALID_CNT_MAX[1]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[8] GT11_0:SH_INVALID_CNT_MAX[0]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[7] GT11_0:SH_CNT_MAX[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[6] GT11_0:SH_CNT_MAX[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[5] GT11_0:SH_CNT_MAX[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[4] GT11_0:SH_CNT_MAX[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[3] GT11_0:SH_CNT_MAX[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[2] GT11_0:SH_CNT_MAX[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[1] GT11_0:SH_CNT_MAX[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4B[0] GT11_0:SH_CNT_MAX[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP43_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP43[15] GT11_0:RESERVED_M2
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_8B10B_DE GT11_0:DRP43[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_CORRECT_USE GT11_0:DRP43[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_LEN[2] GT11_0:DRP43[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_LEN[1] GT11_0:DRP43[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_LEN[0] GT11_0:DRP43[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_DROP GT11_0:DRP43[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_USE GT11_0:DRP43[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP43[7] GT11_0:TXCLK0_INVERT_PMALEAF
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP43[6] GT11_0:RXCLK0_INVERT_PMALEAF
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[5] GT11_0:DRP43[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[4] GT11_0:DRP43[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[3] GT11_0:DRP43[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[2] GT11_0:DRP43[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[1] GT11_0:DRP43[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MAX_LAT[0] GT11_0:DRP43[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 7
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[15] GT11_0:RX_LOS_THRESHOLD[7]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[14] GT11_0:RX_LOS_THRESHOLD[6]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[13] GT11_0:RX_LOS_THRESHOLD[5]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[12] GT11_0:RX_LOS_THRESHOLD[4]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[11] GT11_0:RX_LOS_THRESHOLD[3]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[10] GT11_0:RX_LOS_THRESHOLD[2]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[9] GT11_0:RX_LOS_THRESHOLD[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[8] GT11_0:RX_LOS_THRESHOLD[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[7] GT11_0:RX_LOS_INVALID_INCR[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[6] GT11_0:RX_LOS_INVALID_INCR[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[5] GT11_0:RX_LOS_INVALID_INCR[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[4] GT11_0:RX_LOS_INVALID_INCR[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[3] GT11_0:RX_LOS_INVALID_INCR[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[2] GT11_0:RX_LOS_INVALID_INCR[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[1] GT11_0:RX_LOS_INVALID_INCR[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7B[0] GT11_0:RX_LOS_INVALID_INCR[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP73_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_MASK[3] GT11_0:DRP73[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_MASK[2] GT11_0:DRP73[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_MASK[1] GT11_0:DRP73[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_MASK[0] GT11_0:DRP73[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[10] GT11_0:DRP73[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[9] GT11_0:DRP73[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[8] GT11_0:DRP73[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[7] GT11_0:DRP73[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[6] GT11_0:DRP73[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[5] GT11_0:DRP73[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[4] GT11_0:DRP73[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[3] GT11_0:DRP73[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[2] GT11_0:DRP73[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[1] GT11_0:DRP73[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_4[0] GT11_0:DRP73[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[10] GT11_0:DRP73[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6B_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[9] GT11_0:DRP6B[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[8] GT11_0:DRP6B[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[7] GT11_0:DRP6B[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[6] GT11_0:DRP6B[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[5] GT11_0:DRP6B[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[4] GT11_0:DRP6B[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[3] GT11_0:DRP6B[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[2] GT11_0:DRP6B[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[1] GT11_0:DRP6B[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_3[0] GT11_0:DRP6B[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[10] GT11_0:DRP6B[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[9] GT11_0:DRP6B[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[8] GT11_0:DRP6B[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[7] GT11_0:DRP6B[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[6] GT11_0:DRP6B[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[5] GT11_0:DRP6B[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP63_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[4] GT11_0:DRP63[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[3] GT11_0:DRP63[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[2] GT11_0:DRP63[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[1] GT11_0:DRP63[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_2[0] GT11_0:DRP63[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[10] GT11_0:DRP63[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[9] GT11_0:DRP63[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[8] GT11_0:DRP63[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[7] GT11_0:DRP63[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[6] GT11_0:DRP63[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[5] GT11_0:DRP63[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[4] GT11_0:DRP63[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[3] GT11_0:DRP63[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[2] GT11_0:DRP63[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[1] GT11_0:DRP63[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_2_1[0] GT11_0:DRP63[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 8
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[15] GT11_0:RXEQ[63]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[14] GT11_0:RXEQ[62]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[13] GT11_0:RXEQ[61]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[12] GT11_0:RXEQ[60]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[11] GT11_0:RXEQ[59]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[10] GT11_0:RXEQ[58]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[9] GT11_0:RXEQ[57]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[8] GT11_0:RXEQ[56]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[7] GT11_0:RXEQ[55]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[6] GT11_0:RXEQ[54]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[5] GT11_0:RXEQ[53]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[4] GT11_0:RXEQ[52]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[3] GT11_0:RXEQ[51]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[2] GT11_0:RXEQ[50]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[1] GT11_0:RXEQ[49]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5C[0] GT11_0:RXEQ[48]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[15] GT11_0:RXEQ[47]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[14] GT11_0:RXEQ[46]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[13] GT11_0:RXEQ[45]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[12] GT11_0:RXEQ[44]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[11] GT11_0:RXEQ[43]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[10] GT11_0:RXEQ[42]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[9] GT11_0:RXEQ[41]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[8] GT11_0:RXEQ[40]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[7] GT11_0:RXEQ[39]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[6] GT11_0:RXEQ[38]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[5] GT11_0:RXEQ[37]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[4] GT11_0:RXEQ[36]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[3] GT11_0:RXEQ[35]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[2] GT11_0:RXEQ[34]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[1] GT11_0:RXEQ[33]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP54[0] GT11_0:RXEQ[32]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[15] GT11_0:RXEQ[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[14] GT11_0:RXEQ[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[13] GT11_0:RXEQ[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[12] GT11_0:RXEQ[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[11] GT11_0:RXEQ[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[10] GT11_0:RXEQ[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[9] GT11_0:RXEQ[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[8] GT11_0:RXEQ[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[7] GT11_0:RXEQ[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[6] GT11_0:RXEQ[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[5] GT11_0:RXEQ[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[4] GT11_0:RXEQ[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[3] GT11_0:RXEQ[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[2] GT11_0:RXEQ[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[1] GT11_0:RXEQ[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4C[0] GT11_0:RXEQ[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[15] GT11_0:RXEQ[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[14] GT11_0:RXEQ[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[13] GT11_0:RXEQ[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[12] GT11_0:RXEQ[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[11] GT11_0:RXEQ[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[10] GT11_0:RXEQ[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[9] GT11_0:RXEQ[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[8] GT11_0:RXEQ[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[7] GT11_0:RXEQ[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[6] GT11_0:RXEQ[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[5] GT11_0:RXEQ[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[4] GT11_0:RXEQ[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[3] GT11_0:RXEQ[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[2] GT11_0:RXEQ[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[1] GT11_0:RXEQ[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP44[0] GT11_0:RXEQ[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 9
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[15] GT11_0:RXDATA_SEL[1]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[14] GT11_0:RXDATA_SEL[0]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[13] GT11_0:TXDATA_SEL[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[12] GT11_0:TXDATA_SEL[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[11] GT11_0:RESERVED_CCB
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[5] GT11_0:DRP7C[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[4] GT11_0:DRP7C[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[3] GT11_0:DRP7C[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[2] GT11_0:DRP7C[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[1] GT11_0:DRP7C[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_MIN_LAT[0] GT11_0:DRP7C[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[4] GT11_0:RESERVED_CCA
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7C[3] GT11_0:PCS_BIT_SLIP
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DIGRX_SYNC_MODE GT11_0:DRP7C[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DIGRX_FWDCLK[1] GT11_0:DRP7C[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DIGRX_FWDCLK[0] GT11_0:DRP7C[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP74_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_MASK[3] GT11_0:DRP74[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_MASK[2] GT11_0:DRP74[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_MASK[1] GT11_0:DRP74[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_MASK[0] GT11_0:DRP74[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[10] GT11_0:DRP74[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[9] GT11_0:DRP74[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[8] GT11_0:DRP74[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[7] GT11_0:DRP74[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[6] GT11_0:DRP74[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[5] GT11_0:DRP74[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[4] GT11_0:DRP74[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[3] GT11_0:DRP74[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[2] GT11_0:DRP74[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[1] GT11_0:DRP74[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_4[0] GT11_0:DRP74[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[10] GT11_0:DRP74[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6C_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[9] GT11_0:DRP6C[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[8] GT11_0:DRP6C[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[7] GT11_0:DRP6C[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[6] GT11_0:DRP6C[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[5] GT11_0:DRP6C[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[4] GT11_0:DRP6C[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[3] GT11_0:DRP6C[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[2] GT11_0:DRP6C[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[1] GT11_0:DRP6C[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_3[0] GT11_0:DRP6C[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[10] GT11_0:DRP6C[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[9] GT11_0:DRP6C[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[8] GT11_0:DRP6C[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[7] GT11_0:DRP6C[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[6] GT11_0:DRP6C[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[5] GT11_0:DRP6C[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP64_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[4] GT11_0:DRP64[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[3] GT11_0:DRP64[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[2] GT11_0:DRP64[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[1] GT11_0:DRP64[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_2[0] GT11_0:DRP64[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[10] GT11_0:DRP64[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[9] GT11_0:DRP64[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[8] GT11_0:DRP64[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[7] GT11_0:DRP64[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[6] GT11_0:DRP64[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[5] GT11_0:DRP64[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[4] GT11_0:DRP64[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[3] GT11_0:DRP64[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[2] GT11_0:DRP64[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[1] GT11_0:DRP64[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CLK_COR_SEQ_1_1[0] GT11_0:DRP64[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 10
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[15] GT11_1:MUX.SYNCLK_OUT[1]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[14] GT11_0:MUX.SYNCLK_OUT[1]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[13] GT11_1:RXPMACLKSEL[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[12] GT11_1:RXPMACLKSEL[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[11] GT11_0:RXPMACLKSEL[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[10] GT11_0:RXPMACLKSEL[0]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[9] GT11_COMMON:TXABPMACLKSEL[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[8] GT11_COMMON:TXABPMACLKSEL[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[7] GT11_COMMON:SYNCLK2[2]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[6] GT11_COMMON:SYNCLK2[1]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[5] GT11_COMMON:SYNCLK2[0]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[4] GT11_COMMON:SYNCLK1[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[3] GT11_COMMON:SYNCLK1[1]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[2] GT11_COMMON:SYNCLK1[0]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[1] GT11_COMMON:REFCLKSEL[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5D[0] GT11_COMMON:REFCLKSEL[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[15] GT11_COMMON:PMATUNE
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[14] GT11_COMMON:TXREGCTRL[4]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[13] GT11_COMMON:TXREGCTRL[3]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[12] GT11_COMMON:TXREGCTRL[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[11] GT11_COMMON:TXREGCTRL[1]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[10] GT11_COMMON:TXREGCTRL[0]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[9] GT11_COMMON:RXAREGCTRL[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[8] GT11_COMMON:RXAREGCTRL[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[7] GT11_COMMON:RXAREGCTRL[2]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[6] GT11_COMMON:RXAREGCTRL[1]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[5] GT11_COMMON:RXAREGCTRL[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[4] GT11_COMMON:PMAVBGCTRL[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[3] GT11_COMMON:PMAVBGCTRL[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[2] GT11_COMMON:PMAVBGCTRL[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[1] GT11_COMMON:PMAVBGCTRL[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP55[0] GT11_COMMON:PMAVBGCTRL[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[15] GT11_COMMON:BANDGAPSEL
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[14] GT11_COMMON:PMAIREFTRIM[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[13] GT11_COMMON:PMAIREFTRIM[2]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[12] GT11_COMMON:PMAIREFTRIM[1]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[11] GT11_COMMON:PMAIREFTRIM[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[10] GT11_COMMON:IREFBIASMODE[1]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[9] GT11_COMMON:IREFBIASMODE[0]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[8] GT11_COMMON:BIASRESSEL
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[7] GT11_COMMON:PMAVREFTRIM[3]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[6] GT11_COMMON:PMAVREFTRIM[2]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[5] GT11_COMMON:PMAVREFTRIM[1]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[4] GT11_COMMON:PMAVREFTRIM[0]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[3] GT11_COMMON:VREFSELECT
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[2] GT11_COMMON:VREFBIASMODE[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[1] GT11_COMMON:VREFBIASMODE[0]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4D[0] GT11_COMMON:PMABIASPD
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[15] GT11_COMMON:ATBENABLE
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[14] GT11_1:MUX.SYNCLK_OUT[0]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[13] GT11_0:MUX.SYNCLK_OUT[0]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[12] GT11_COMMON:ATBBUMPEN
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[11] GT11_COMMON:NATBENABLE
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[10] GT11_COMMON:REFCLKSEL[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[6] ~GT11_COMMON:SYNCLK_DRIVE_ENABLE
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[5] GT11_COMMON:REFCLKSEL[2]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[4] GT11_1:TXPHASESEL
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[3] GT11_0:TXPHASESEL
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[2] GT11_COMMON:PMACTRL
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[1] GT11_COMMON:SYNCLK_ENABLE
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP45[0] GT11_COMMON:PMACOREPWRENABLE
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 11
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[15] GT11_COMMON:PMACFG2SPARE[45]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[14] GT11_COMMON:PMACFG2SPARE[44]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[13] GT11_COMMON:PMACFG2SPARE[43]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[12] GT11_COMMON:PMACFG2SPARE[42]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[11] GT11_COMMON:PMACFG2SPARE[41]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[10] GT11_COMMON:PMACFG2SPARE[40]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[9] GT11_COMMON:PMACFG2SPARE[39]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[8] GT11_COMMON:PMACFG2SPARE[38]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[7] GT11_COMMON:PMACFG2SPARE[37]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[6] GT11_COMMON:PMACFG2SPARE[36]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[5] GT11_COMMON:PMACFG2SPARE[35]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[4] GT11_COMMON:PMACFG2SPARE[34]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[3] GT11_COMMON:PMACFG2SPARE[33]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[2] GT11_COMMON:PMACFG2SPARE[32]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[1] GT11_COMMON:PMACFG2SPARE[31]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7D[0] GT11_COMMON:PMACFG2SPARE[30]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[15] GT11_COMMON:PMACFG2SPARE[29]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[14] GT11_COMMON:PMACFG2SPARE[28]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[13] GT11_COMMON:PMACFG2SPARE[27]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[12] GT11_COMMON:PMACFG2SPARE[26]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[11] GT11_COMMON:PMACFG2SPARE[25]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[10] GT11_COMMON:PMACFG2SPARE[24]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[9] GT11_COMMON:PMACFG2SPARE[23]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[8] GT11_COMMON:PMACFG2SPARE[22]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[7] GT11_COMMON:PMACFG2SPARE[21]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[6] GT11_COMMON:PMACFG2SPARE[20]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[5] GT11_COMMON:PMACFG2SPARE[19]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[4] GT11_COMMON:PMACFG2SPARE[18]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[3] GT11_COMMON:PMACFG2SPARE[17]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[2] GT11_COMMON:PMACFG2SPARE[16]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[1] GT11_COMMON:PMACFG2SPARE[15]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP75[0] GT11_COMMON:PMACFG2SPARE[14]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[15] GT11_COMMON:PMACFG2SPARE[13]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[14] GT11_COMMON:PMACFG2SPARE[12]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[13] GT11_COMMON:PMACFG2SPARE[11]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[12] GT11_COMMON:PMACFG2SPARE[10]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[11] GT11_COMMON:PMACFG2SPARE[9]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[10] GT11_COMMON:PMACFG2SPARE[8]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[9] GT11_COMMON:PMACFG2SPARE[7]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[8] GT11_COMMON:PMACFG2SPARE[6]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[7] GT11_COMMON:PMACFG2SPARE[5]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[6] GT11_COMMON:PMACFG2SPARE[4]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[5] GT11_COMMON:PMACFG2SPARE[3]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[4] GT11_COMMON:PMACFG2SPARE[2]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[3] GT11_COMMON:PMACFG2SPARE[1]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[2] GT11_COMMON:PMACFG2SPARE[0]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[1] GT11_COMMON:ATBSEL[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6D[0] GT11_COMMON:ATBSEL[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[15] GT11_COMMON:ATBSEL[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[14] GT11_COMMON:ATBSEL[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[13] GT11_COMMON:ATBSEL[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[12] GT11_COMMON:ATBSEL[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[11] GT11_COMMON:ATBSEL[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[10] GT11_COMMON:ATBSEL[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[9] GT11_COMMON:ATBSEL[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[8] GT11_COMMON:ATBSEL[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[7] GT11_COMMON:ATBSEL[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[6] GT11_COMMON:ATBSEL[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[5] GT11_COMMON:ATBSEL[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[4] GT11_COMMON:ATBSEL[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[3] GT11_COMMON:ATBSEL[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[2] GT11_COMMON:ATBSEL[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[1] GT11_COMMON:ATBSEL[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP65[0] GT11_COMMON:ATBSEL[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 12
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[15] GT11_0:TXLNDR_TST1[3]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[14] GT11_0:TXLNDR_TST1[2]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[13] GT11_0:TXLNDR_TST1[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[12] GT11_0:TXLNDR_TST1[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[11] GT11_0:TXLVLSHFTPD
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[10] GT11_0:TXPRE_PRDRV_DAC[2]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[9] GT11_0:TXPRE_PRDRV_DAC[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[8] GT11_0:TXPRE_PRDRV_DAC[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[7] GT11_0:TXPRE_TAP_PD
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[6] GT11_0:TXPRE_TAP_DAC[4]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[5] GT11_0:TXPRE_TAP_DAC[3]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[4] GT11_0:TXDIGPD
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[3] GT11_0:TXCLKMODE[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[2] GT11_0:TXCLKMODE[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[1] GT11_0:TXCLKMODE[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5E[0] GT11_0:TXCLKMODE[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[15] GT11_0:TXPRE_TAP_DAC[2]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[14] GT11_0:TXPRE_TAP_DAC[1]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[13] GT11_0:TXPRE_TAP_DAC[0]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[12] GT11_0:TXCFGENABLE
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[11] GT11_0:TXHIGHSIGNALEN
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[10] GT11_0:TXAREFBIASSEL
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[9] GT11_0:TXTERMTRIM[3]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[8] GT11_0:TXTERMTRIM[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[7] GT11_0:TXTERMTRIM[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[6] GT11_0:TXTERMTRIM[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[5] GT11_0:TXASYNCDIVIDE[1]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[4] GT11_0:TXSLEWRATE
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[3] GT11_0:TXPOST_PRDRV_DAC[2]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[2] GT11_0:TXPOST_PRDRV_DAC[1]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[1] GT11_0:TXPOST_PRDRV_DAC[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP56[0] GT11_0:TXDAT_PRDRV_DAC[2]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[15] GT11_0:TXDAT_PRDRV_DAC[1]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[14] GT11_0:TXDAT_PRDRV_DAC[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[13] GT11_0:TXASYNCDIVIDE[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[12] GT11_0:TXPOST_TAP_PD
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[11] GT11_0:TXPOST_TAP_DAC[4]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[10] GT11_0:TXPOST_TAP_DAC[3]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[9] GT11_0:TXPOST_TAP_DAC[2]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[8] GT11_0:TXPOST_TAP_DAC[1]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[7] GT11_0:TXPOST_TAP_DAC[0]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[6] GT11_0:TXLNDR_TST2[1]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[5] GT11_0:TXLNDR_TST2[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[4] GT11_0:TXDAT_TAP_DAC[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[3] GT11_0:TXDAT_TAP_DAC[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[2] GT11_0:TXDAT_TAP_DAC[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[1] GT11_0:TXDAT_TAP_DAC[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4E[0] GT11_0:TXDAT_TAP_DAC[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[15] GT11_0:TXLNDR_TST3[14]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[14] GT11_0:TXLNDR_TST3[13]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[13] GT11_0:TXLNDR_TST3[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[12] GT11_0:TXLNDR_TST3[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[11] GT11_0:TXLNDR_TST3[10]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[10] GT11_0:TXLNDR_TST3[9]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[9] GT11_0:TXLNDR_TST3[8]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[8] GT11_0:TXLNDR_TST3[7]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[7] GT11_0:TXLNDR_TST3[6]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[6] GT11_0:TXLNDR_TST3[5]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[5] GT11_0:TXLNDR_TST3[4]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[4] GT11_0:TXLNDR_TST3[3]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[3] GT11_0:TXLNDR_TST3[2]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[2] GT11_0:TXLNDR_TST3[1]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[1] GT11_0:TXLNDR_TST3[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP46[0] GT11_0:TXPD
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 13
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[7] GT11_0:DRP7E[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[6] GT11_0:DRP7E[14]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[5] GT11_0:DRP7E[13]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[4] GT11_0:DRP7E[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[3] GT11_0:DRP7E[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[2] GT11_0:DRP7E[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[1] GT11_0:DRP7E[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_TUNE[0] GT11_0:DRP7E[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CCCB_ARBITRATOR_DISABLE GT11_0:DRP7E[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[4] GT11_0:OPPOSITE_SELECT
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[3] GT11_0:POWER_ENABLE
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[2] GT11_0:TEST_MODE_3
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[1] GT11_0:TEST_MODE_2
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7E[0] GT11_0:TEST_MODE_1
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP76_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_MASK[3] GT11_0:DRP76[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_MASK[2] GT11_0:DRP76[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_MASK[1] GT11_0:DRP76[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_MASK[0] GT11_0:DRP76[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[10] GT11_0:DRP76[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[9] GT11_0:DRP76[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[8] GT11_0:DRP76[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[7] GT11_0:DRP76[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[6] GT11_0:DRP76[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[5] GT11_0:DRP76[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[4] GT11_0:DRP76[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[3] GT11_0:DRP76[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[2] GT11_0:DRP76[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[1] GT11_0:DRP76[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_4[0] GT11_0:DRP76[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[10] GT11_0:DRP76[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6E_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[9] GT11_0:DRP6E[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[8] GT11_0:DRP6E[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[7] GT11_0:DRP6E[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[6] GT11_0:DRP6E[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[5] GT11_0:DRP6E[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[4] GT11_0:DRP6E[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[3] GT11_0:DRP6E[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[2] GT11_0:DRP6E[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[1] GT11_0:DRP6E[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_3[0] GT11_0:DRP6E[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[10] GT11_0:DRP6E[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[9] GT11_0:DRP6E[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[8] GT11_0:DRP6E[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[7] GT11_0:DRP6E[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[6] GT11_0:DRP6E[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[5] GT11_0:DRP6E[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP66_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[4] GT11_0:DRP66[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[3] GT11_0:DRP66[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[2] GT11_0:DRP66[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[1] GT11_0:DRP66[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_2[0] GT11_0:DRP66[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[10] GT11_0:DRP66[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[9] GT11_0:DRP66[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[8] GT11_0:DRP66[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[7] GT11_0:DRP66[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[6] GT11_0:DRP66[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[5] GT11_0:DRP66[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[4] GT11_0:DRP66[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[3] GT11_0:DRP66[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[2] GT11_0:DRP66[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[1] GT11_0:DRP66[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_1[0] GT11_0:DRP66[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 14
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[14]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[13]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[5] GT11_1:MUX.PMACLK[7]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[4] GT11_1:MUX.PMACLK[6]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[3] GT11_1:MUX.PMACLK[5]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[2] GT11_1:MUX.PMACLK[4]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[1] GT11_1:MUX.PMACLK[3]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP5F[0] GT11_1:MUX.PMACLK[2]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[15] GT11_1:MUX.PMACLK[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[14] GT11_1:MUX.PMACLK[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[13] GT11_1:MUX.REFCLK[7]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[12] GT11_1:MUX.REFCLK[6]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[11] GT11_1:MUX.REFCLK[5]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[10] GT11_1:MUX.REFCLK[4]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[9] GT11_1:MUX.REFCLK[3]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[8] GT11_1:MUX.REFCLK[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[7] GT11_1:MUX.REFCLK[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[6] GT11_1:MUX.REFCLK[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[5] GT11_1:MUX.MGT0[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[4] GT11_1:MUX.MGT0[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[3] GT11_1:MUX.MGT0[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[2] GT11_1:MUX.MGT1[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[1] GT11_1:MUX.MGT1[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP57[0] GT11_1:MUX.MGT1[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[5] GT11_0:MUX.PMACLK[7]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[4] GT11_0:MUX.PMACLK[6]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[3] GT11_0:MUX.PMACLK[5]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[2] GT11_0:MUX.PMACLK[4]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[1] GT11_0:MUX.PMACLK[3]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP4F[0] GT11_0:MUX.PMACLK[2]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[15] GT11_0:MUX.PMACLK[1]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[14] GT11_0:MUX.PMACLK[0]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[13] GT11_0:MUX.REFCLK[7]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[12] GT11_0:MUX.REFCLK[6]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[11] GT11_0:MUX.REFCLK[5]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[10] GT11_0:MUX.REFCLK[4]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[9] GT11_0:MUX.REFCLK[3]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[8] GT11_0:MUX.REFCLK[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[7] GT11_0:MUX.REFCLK[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[6] GT11_0:MUX.REFCLK[0]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[5] GT11_0:MUX.MGT0[2]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[4] GT11_0:MUX.MGT0[1]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[3] GT11_0:MUX.MGT0[0]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[2] GT11_0:MUX.MGT1[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[1] GT11_0:MUX.MGT1[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP47[0] GT11_0:MUX.MGT1[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 15
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7F_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7F[15] GT11_0:RESERVED_CB1
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7F[14] GT11_0:TX_BUFFER_USE
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7F[13] GT11_0:RX_BUFFER_USE
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_LEN[2] GT11_0:DRP7F[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_LEN[1] GT11_0:DRP7F[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_LEN[0] GT11_0:DRP7F[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_2_USE GT11_0:DRP7F[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_ONE_SHOT GT11_0:DRP7F[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_MODE[1] GT11_0:DRP7F[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_MODE[0] GT11_0:DRP7F[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP7F[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_LIMIT[4] GT11_0:DRP7F[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_LIMIT[3] GT11_0:DRP7F[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_LIMIT[2] GT11_0:DRP7F[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_LIMIT[1] GT11_0:DRP7F[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_LIMIT[0] GT11_0:DRP7F[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP77_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_MASK[3] GT11_0:DRP77[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_MASK[2] GT11_0:DRP77[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_MASK[1] GT11_0:DRP77[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_MASK[0] GT11_0:DRP77[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[10] GT11_0:DRP77[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[9] GT11_0:DRP77[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[8] GT11_0:DRP77[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[7] GT11_0:DRP77[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[6] GT11_0:DRP77[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[5] GT11_0:DRP77[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[4] GT11_0:DRP77[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[3] GT11_0:DRP77[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[2] GT11_0:DRP77[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[1] GT11_0:DRP77[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_4[0] GT11_0:DRP77[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[10] GT11_0:DRP77[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP6F_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[9] GT11_0:DRP6F[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[8] GT11_0:DRP6F[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[7] GT11_0:DRP6F[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[6] GT11_0:DRP6F[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[5] GT11_0:DRP6F[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[4] GT11_0:DRP6F[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[3] GT11_0:DRP6F[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[2] GT11_0:DRP6F[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[1] GT11_0:DRP6F[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_3[0] GT11_0:DRP6F[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[10] GT11_0:DRP6F[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[9] GT11_0:DRP6F[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[8] GT11_0:DRP6F[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[7] GT11_0:DRP6F[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[6] GT11_0:DRP6F[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[5] GT11_0:DRP6F[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:DRP67_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[4] GT11_0:DRP67[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[3] GT11_0:DRP67[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[2] GT11_0:DRP67[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[1] GT11_0:DRP67[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_2[0] GT11_0:DRP67[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[10] GT11_0:DRP67[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[9] GT11_0:DRP67[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[8] GT11_0:DRP67[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[7] GT11_0:DRP67[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[6] GT11_0:DRP67[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[5] GT11_0:DRP67[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[4] GT11_0:DRP67[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[3] GT11_0:DRP67[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[2] GT11_0:DRP67[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[1] GT11_0:DRP67[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:CHAN_BOND_SEQ_1_1[0] GT11_0:DRP67[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 16
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[15] GT11_1:TXCRCINITVAL[31]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[14] GT11_1:TXCRCINITVAL[30]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[13] GT11_1:TXCRCINITVAL[29]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[12] GT11_1:TXCRCINITVAL[28]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[11] GT11_1:TXCRCINITVAL[27]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[10] GT11_1:TXCRCINITVAL[26]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[9] GT11_1:TXCRCINITVAL[25]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[8] GT11_1:TXCRCINITVAL[24]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[7] GT11_1:TXCRCINITVAL[23]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[6] GT11_1:TXCRCINITVAL[22]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[5] GT11_1:TXCRCINITVAL[21]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[4] GT11_1:TXCRCINITVAL[20]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[3] GT11_1:TXCRCINITVAL[19]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[2] GT11_1:TXCRCINITVAL[18]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[1] GT11_1:TXCRCINITVAL[17]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP58[0] GT11_1:TXCRCINITVAL[16]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[15] GT11_1:TXCRCINITVAL[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[14] GT11_1:TXCRCINITVAL[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[13] GT11_1:TXCRCINITVAL[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[12] GT11_1:TXCRCINITVAL[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[11] GT11_1:TXCRCINITVAL[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[10] GT11_1:TXCRCINITVAL[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[9] GT11_1:TXCRCINITVAL[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[8] GT11_1:TXCRCINITVAL[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[7] GT11_1:TXCRCINITVAL[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[6] GT11_1:TXCRCINITVAL[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[5] GT11_1:TXCRCINITVAL[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[4] GT11_1:TXCRCINITVAL[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[3] GT11_1:TXCRCINITVAL[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[2] GT11_1:TXCRCINITVAL[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[1] GT11_1:TXCRCINITVAL[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP50[0] GT11_1:TXCRCINITVAL[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[15] GT11_1:RXCRCINITVAL[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[14] GT11_1:RXCRCINITVAL[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[13] GT11_1:RXCRCINITVAL[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[12] GT11_1:RXCRCINITVAL[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[11] GT11_1:RXCRCINITVAL[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[10] GT11_1:RXCRCINITVAL[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[9] GT11_1:RXCRCINITVAL[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[8] GT11_1:RXCRCINITVAL[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[7] GT11_1:RXCRCINITVAL[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[6] GT11_1:RXCRCINITVAL[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[5] GT11_1:RXCRCINITVAL[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[4] GT11_1:RXCRCINITVAL[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[3] GT11_1:RXCRCINITVAL[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[2] GT11_1:RXCRCINITVAL[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[1] GT11_1:RXCRCINITVAL[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP48[0] GT11_1:RXCRCINITVAL[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[15] GT11_1:RXCRCINITVAL[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[14] GT11_1:RXCRCINITVAL[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[13] GT11_1:RXCRCINITVAL[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[12] GT11_1:RXCRCINITVAL[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[11] GT11_1:RXCRCINITVAL[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[10] GT11_1:RXCRCINITVAL[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[9] GT11_1:RXCRCINITVAL[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[8] GT11_1:RXCRCINITVAL[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[7] GT11_1:RXCRCINITVAL[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[6] GT11_1:RXCRCINITVAL[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[5] GT11_1:RXCRCINITVAL[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[4] GT11_1:RXCRCINITVAL[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[3] GT11_1:RXCRCINITVAL[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[2] GT11_1:RXCRCINITVAL[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[1] GT11_1:RXCRCINITVAL[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP40[0] GT11_1:RXCRCINITVAL[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 17
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:AUTO_CAL GT11_1:DRP78[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[14] GT11_1:VCODAC_INIT[9]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[13] GT11_1:VCODAC_INIT[8]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[12] GT11_1:VCODAC_INIT[7]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[11] GT11_1:VCODAC_INIT[6]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[10] GT11_1:VCODAC_INIT[5]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[9] GT11_1:VCODAC_INIT[4]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[8] GT11_1:VCODAC_INIT[3]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[7] GT11_1:VCODAC_INIT[2]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[6] GT11_1:VCODAC_INIT[1]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[5] GT11_1:VCODAC_INIT[0]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[4] GT11_1:SLOWDOWN_CAL[1]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[3] GT11_1:SLOWDOWN_CAL[0]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:BYPASS_FDET GT11_1:DRP78[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[1] GT11_1:LOOPCAL_WAIT[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP78[0] GT11_1:LOOPCAL_WAIT[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:BYPASS_CAL GT11_1:DRP70[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[14] GT11_1:FDET_HYS_CAL[2]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[13] GT11_1:FDET_HYS_CAL[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[12] GT11_1:FDET_HYS_CAL[0]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[11] GT11_1:FDET_LCK_CAL[2]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[10] GT11_1:FDET_LCK_CAL[1]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[9] GT11_1:FDET_LCK_CAL[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[8] GT11_1:FDET_HYS_SEL[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[7] GT11_1:FDET_HYS_SEL[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[6] GT11_1:FDET_HYS_SEL[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[5] GT11_1:FDET_LCK_SEL[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[4] GT11_1:FDET_LCK_SEL[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[3] GT11_1:FDET_LCK_SEL[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP70[2] GT11_1:VCO_CTRL_ENABLE
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CYCLE_LIMIT_SEL[1] GT11_1:DRP70[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CYCLE_LIMIT_SEL[0] GT11_1:DRP70[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[15] GT11_1:RXAUTO_CAL
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[14] GT11_1:RXVCODAC_INIT[9]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[13] GT11_1:RXVCODAC_INIT[8]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[12] GT11_1:RXVCODAC_INIT[7]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[11] GT11_1:RXVCODAC_INIT[6]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[10] GT11_1:RXVCODAC_INIT[5]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[9] GT11_1:RXVCODAC_INIT[4]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[8] GT11_1:RXVCODAC_INIT[3]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[7] GT11_1:RXVCODAC_INIT[2]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[6] GT11_1:RXVCODAC_INIT[1]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[5] GT11_1:RXVCODAC_INIT[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[4] GT11_1:RXSLOWDOWN_CAL[1]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[3] GT11_1:RXSLOWDOWN_CAL[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[2] GT11_1:RXBYPASS_FDET
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[1] GT11_1:RXLOOPCAL_WAIT[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP68[0] GT11_1:RXLOOPCAL_WAIT[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[15] GT11_1:RXBYPASS_CAL
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[14] GT11_1:RXFDET_HYS_CAL[2]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[13] GT11_1:RXFDET_HYS_CAL[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[12] GT11_1:RXFDET_HYS_CAL[0]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[11] GT11_1:RXFDET_LCK_CAL[2]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[10] GT11_1:RXFDET_LCK_CAL[1]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[9] GT11_1:RXFDET_LCK_CAL[0]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[8] GT11_1:RXFDET_HYS_SEL[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[7] GT11_1:RXFDET_HYS_SEL[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[6] GT11_1:RXFDET_HYS_SEL[0]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[5] GT11_1:RXFDET_LCK_SEL[2]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[4] GT11_1:RXFDET_LCK_SEL[1]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[3] GT11_1:RXFDET_LCK_SEL[0]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[2] GT11_1:RXVCO_CTRL_ENABLE
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[1] GT11_1:RXCYCLE_LIMIT_SEL[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP60[0] GT11_1:RXCYCLE_LIMIT_SEL[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 18
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[14]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[13]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP59[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[15] GT11_1:MUX.FWDCLK1[2]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[14] GT11_1:MUX.FWDCLK1[1]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[13] GT11_1:MUX.FWDCLK1[0]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[12] GT11_1:MUX.FWDCLK2[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[11] GT11_1:MUX.FWDCLK2[1]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[10] GT11_1:MUX.FWDCLK2[0]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[9] GT11_1:MUX.FWDCLK3[2]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[8] GT11_1:MUX.FWDCLK3[1]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[7] GT11_1:MUX.FWDCLK3[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[6] GT11_1:MUX.FWDCLK4[2]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[5] GT11_1:MUX.FWDCLK4[1]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP51[4] GT11_1:MUX.FWDCLK4[0]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK1[2] GT11_1:DRP51[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK1[1] GT11_1:DRP51[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK1[0] GT11_1:DRP51[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK2[2] GT11_1:DRP51[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP49_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK2[1] GT11_1:DRP49[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK2[0] GT11_1:DRP49[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK3[2] GT11_1:DRP49[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK3[1] GT11_1:DRP49[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK3[0] GT11_1:DRP49[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK4[2] GT11_1:DRP49[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK4[1] GT11_1:DRP49[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK4[0] GT11_1:DRP49[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP49[7] GT11_1:MUX.FWDCLK1_OUT[1]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP49[6] GT11_1:MUX.FWDCLK1_OUT[0]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP49[5] GT11_1:MUX.FWDCLK0_OUT[1]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP49[4] GT11_1:MUX.FWDCLK0_OUT[0]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK1_OUT[1] GT11_1:DRP49[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK1_OUT[0] GT11_1:DRP49[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK0_OUT[1] GT11_1:DRP49[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:MUX.FWDCLK0_OUT[0] GT11_1:DRP49[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[15] GT11_COMMON:FWDCLK_OUT_ENABLE
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[7] GT11_COMMON:MUX.PMACLK[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[6] GT11_COMMON:MUX.REFCLK[1]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[3] GT11_COMMON:MUX.PMACLK[0]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[2] GT11_COMMON:MUX.REFCLK[0]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP41[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 19
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[15] GT11_1:PCOMMA_VALUE[31]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[14] GT11_1:PCOMMA_VALUE[30]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[13] GT11_1:PCOMMA_VALUE[29]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[12] GT11_1:PCOMMA_VALUE[28]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[11] GT11_1:PCOMMA_VALUE[27]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[10] GT11_1:PCOMMA_VALUE[26]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[9] GT11_1:PCOMMA_VALUE[25]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[8] GT11_1:PCOMMA_VALUE[24]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[7] GT11_1:PCOMMA_VALUE[23]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[6] GT11_1:PCOMMA_VALUE[22]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[5] GT11_1:PCOMMA_VALUE[21]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[4] GT11_1:PCOMMA_VALUE[20]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[3] GT11_1:PCOMMA_VALUE[19]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[2] GT11_1:PCOMMA_VALUE[18]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[1] GT11_1:PCOMMA_VALUE[17]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP79[0] GT11_1:PCOMMA_VALUE[16]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[15] GT11_1:PCOMMA_VALUE[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[14] GT11_1:PCOMMA_VALUE[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[13] GT11_1:PCOMMA_VALUE[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[12] GT11_1:PCOMMA_VALUE[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[11] GT11_1:PCOMMA_VALUE[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[10] GT11_1:PCOMMA_VALUE[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[9] GT11_1:PCOMMA_VALUE[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[8] GT11_1:PCOMMA_VALUE[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[7] GT11_1:PCOMMA_VALUE[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[6] GT11_1:PCOMMA_VALUE[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[5] GT11_1:PCOMMA_VALUE[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[4] GT11_1:PCOMMA_VALUE[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[3] GT11_1:PCOMMA_VALUE[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[2] GT11_1:PCOMMA_VALUE[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[1] GT11_1:PCOMMA_VALUE[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP71[0] GT11_1:PCOMMA_VALUE[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[15] GT11_1:MCOMMA_VALUE[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[14] GT11_1:MCOMMA_VALUE[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[13] GT11_1:MCOMMA_VALUE[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[12] GT11_1:MCOMMA_VALUE[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[11] GT11_1:MCOMMA_VALUE[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[10] GT11_1:MCOMMA_VALUE[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[9] GT11_1:MCOMMA_VALUE[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[8] GT11_1:MCOMMA_VALUE[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[7] GT11_1:MCOMMA_VALUE[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[6] GT11_1:MCOMMA_VALUE[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[5] GT11_1:MCOMMA_VALUE[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[4] GT11_1:MCOMMA_VALUE[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[3] GT11_1:MCOMMA_VALUE[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[2] GT11_1:MCOMMA_VALUE[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[1] GT11_1:MCOMMA_VALUE[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP69[0] GT11_1:MCOMMA_VALUE[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[15] GT11_1:MCOMMA_VALUE[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[14] GT11_1:MCOMMA_VALUE[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[13] GT11_1:MCOMMA_VALUE[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[12] GT11_1:MCOMMA_VALUE[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[11] GT11_1:MCOMMA_VALUE[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[10] GT11_1:MCOMMA_VALUE[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[9] GT11_1:MCOMMA_VALUE[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[8] GT11_1:MCOMMA_VALUE[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[7] GT11_1:MCOMMA_VALUE[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[6] GT11_1:MCOMMA_VALUE[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[5] GT11_1:MCOMMA_VALUE[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[4] GT11_1:MCOMMA_VALUE[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[3] GT11_1:MCOMMA_VALUE[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[2] GT11_1:MCOMMA_VALUE[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[1] GT11_1:MCOMMA_VALUE[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP61[0] GT11_1:MCOMMA_VALUE[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 20
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[15] GT11_1:RESERVED_CM2[21]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[14] GT11_1:RESERVED_CM2[20]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[13] GT11_1:RESERVED_CM2[19]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[12] GT11_1:RESERVED_CM2[18]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[11] GT11_1:RESERVED_CM2[17]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[10] GT11_1:RESERVED_CM2[16]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[9] GT11_1:RESERVED_CM2[15]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[8] GT11_1:RESERVED_CM2[14]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[7] GT11_1:RESERVED_CM2[13]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[6] GT11_1:RESERVED_CM2[12]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[5] GT11_1:RESERVED_CM2[11]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[4] GT11_1:RESERVED_CM2[10]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[3] GT11_1:RESERVED_CM2[9]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[2] GT11_1:RESERVED_CM2[8]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[1] GT11_1:RESERVED_CM2[7]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5A[0] GT11_1:RESERVED_CM2[6]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[15] GT11_1:RESERVED_CM2[5]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[14] GT11_1:RESERVED_CM2[4]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[13] GT11_1:RESERVED_CM2[3]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[12] GT11_1:RESERVED_CM2[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[11] GT11_1:RESERVED_CM2[1]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP52[10] GT11_1:RESERVED_CM2[0]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[9] GT11_1:DRP52[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[8] GT11_1:DRP52[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[7] GT11_1:DRP52[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[6] GT11_1:DRP52[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[5] GT11_1:DRP52[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[4] GT11_1:DRP52[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[3] GT11_1:DRP52[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[2] GT11_1:DRP52[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[1] GT11_1:DRP52[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA_10B_MASK[0] GT11_1:DRP52[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[15] GT11_1:RESERVED_CM[23]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[14] GT11_1:RESERVED_CM[22]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[13] GT11_1:RESERVED_CM[21]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[12] GT11_1:RESERVED_CM[20]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[11] GT11_1:RESERVED_CM[19]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[10] GT11_1:RESERVED_CM[18]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[9] GT11_1:RESERVED_CM[17]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[8] GT11_1:RESERVED_CM[16]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[7] GT11_1:RESERVED_CM[15]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[6] GT11_1:RESERVED_CM[14]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[5] GT11_1:RESERVED_CM[13]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[4] GT11_1:RESERVED_CM[12]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[3] GT11_1:RESERVED_CM[11]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[2] GT11_1:RESERVED_CM[10]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[1] GT11_1:RESERVED_CM[9]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4A[0] GT11_1:RESERVED_CM[8]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[15] GT11_1:RESERVED_CM[7]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[14] GT11_1:RESERVED_CM[6]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[13] GT11_1:RESERVED_CM[5]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[12] GT11_1:RESERVED_CM[4]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[11] GT11_1:RESERVED_CM[3]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[10] GT11_1:RESERVED_CM[2]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[9] GT11_1:RESERVED_CM[1]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[8] GT11_1:RESERVED_CM[0]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:COMMA32 GT11_1:DRP42[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[6] GT11_1:PCOMMA_DETECT
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP42[5] GT11_1:MCOMMA_DETECT
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DEC_VALID_COMMA_ONLY GT11_1:DRP42[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DEC_PCOMMA_DETECT GT11_1:DRP42[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DEC_MCOMMA_DETECT GT11_1:DRP42[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:ALIGN_COMMA_WORD[1] GT11_1:DRP42[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:ALIGN_COMMA_WORD[0] GT11_1:DRP42[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 21
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[14] GT11_1:TXOUTDIV2SEL[2]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[13] GT11_1:TXOUTDIV2SEL[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[12] GT11_1:TXOUTDIV2SEL[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[11] GT11_COMMON:TXPLLNDIVSEL[2]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[10] GT11_COMMON:TXPLLNDIVSEL[1]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[9] GT11_COMMON:TXPLLNDIVSEL[0]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[7] GT11_COMMON:TXCLMODE[1]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[6] GT11_COMMON:TXCLMODE[0]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[5] GT11_COMMON:TXLOOPFILT[3]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[4] GT11_COMMON:TXLOOPFILT[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[3] GT11_COMMON:TXLOOPFILT[1]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[2] GT11_COMMON:TXLOOPFILT[0]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[1] GT11_COMMON:TXDIGRX
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7A[0] GT11_COMMON:TXPFDTX
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[15] GT11_COMMON:TXTUNE[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[14] GT11_COMMON:TXTUNE[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[13] GT11_COMMON:TXTUNE[10]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[12] GT11_COMMON:TXTUNE[9]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[11] GT11_COMMON:TXTUNE[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[10] GT11_COMMON:TXTUNE[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[9] GT11_COMMON:TXTUNE[6]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[8] GT11_COMMON:TXTUNE[5]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[7] GT11_COMMON:TXTUNE[4]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[6] GT11_COMMON:TXTUNE[3]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[5] GT11_COMMON:TXTUNE[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[4] GT11_COMMON:TXTUNE[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[3] GT11_COMMON:TXTUNE[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[2] GT11_COMMON:TXSLOSEL
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[1] GT11_COMMON:TXDACSEL
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP72[0] GT11_COMMON:TXCPSEL
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[15] GT11_COMMON:TXDACTST
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:TXOUTDIV2SEL[2] GT11_1:DRP6A[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:TXOUTDIV2SEL[1] GT11_1:DRP6A[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_0:TXOUTDIV2SEL[0] GT11_1:DRP6A[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[10] GT11_COMMON:TXCTRL1[9]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[9] GT11_COMMON:TXCTRL1[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[8] GT11_COMMON:TXCTRL1[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[7] GT11_COMMON:TXCTRL1[6]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[6] GT11_COMMON:TXCTRL1[5]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[5] GT11_COMMON:TXCTRL1[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[4] GT11_COMMON:TXCTRL1[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[3] GT11_COMMON:TXCTRL1[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[2] GT11_COMMON:TXCTRL1[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[1] GT11_COMMON:TXCTRL1[0]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6A[0] GT11_COMMON:TXQPPD
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[15] GT11_COMMON:TXCMFPD
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[14] GT11_COMMON:TXVCOPD
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[13] GT11_COMMON:TXADCADJPD
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[12] GT11_COMMON:TXDIVPD
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[11] GT11_COMMON:TXBIASPD
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[10] GT11_COMMON:TXVCOBUFPD
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[9] GT11_COMMON:TXDIVBUFPD
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[8] GT11_COMMON:TXAPD
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[7] GT11_COMMON:TXAPTST
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[6] GT11_COMMON:TXCMFTST
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[5] GT11_COMMON:TXFILTTST
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[4] GT11_COMMON:TXDIVTST
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[3] GT11_COMMON:TXPFDTST
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[2] GT11_COMMON:TXVCOBUFTST
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[1] GT11_COMMON:TXDIVBUFTST
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP62[0] GT11_COMMON:TXVCOTST
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 22
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[15] GT11_1:RXRECCLK1_USE_SYNC
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[14] GT11_1:TXOUTCLK1_USE_SYNC
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[13] GT11_1:TXCLK0_FORCE_PMACLK
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[12] GT11_1:RXCLK0_FORCE_PMACLK
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[11] GT11_1:TX_CLOCK_DIVIDER[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[10] GT11_1:TX_CLOCK_DIVIDER[0]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[9] GT11_1:RX_CLOCK_DIVIDER[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[8] GT11_1:RX_CLOCK_DIVIDER[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[7] GT11_1:TXCRCENABLE
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[6] GT11_1:TXCRCSAMECLOCK
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[5] GT11_1:TXCRCINVERTGEN
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[4] GT11_1:TXCRCCLOCKDOUBLE
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[3] GT11_1:RXCRCENABLE
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[2] GT11_1:RXCRCSAMECLOCK
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[1] GT11_1:RXCRCINVERTGEN
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5B[0] GT11_1:RXCRCCLOCKDOUBLE
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[15] GT11_1:RXFDCAL_CLOCK_DIVIDE[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[14] GT11_1:RXFDCAL_CLOCK_DIVIDE[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[13] GT11_1:TXFDCAL_CLOCK_DIVIDE[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[12] GT11_1:TXFDCAL_CLOCK_DIVIDE[0]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[11] GT11_1:RXBY_32
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[10] GT11_1:REPEATER
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[9] GT11_1:ENABLE_DCDR
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[8] GT11_1:SAMPLE_8X
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DCDR_FILTER[2] GT11_1:DRP53[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DCDR_FILTER[1] GT11_1:DRP53[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DCDR_FILTER[0] GT11_1:DRP53[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[4] GT11_1:RXUSRDIVISOR[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[3] GT11_1:RXUSRDIVISOR[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[2] GT11_1:RXUSRDIVISOR[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[1] GT11_1:RXUSRDIVISOR[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP53[0] GT11_1:RXUSRDIVISOR[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[15] GT11_1:SH_INVALID_CNT_MAX[7]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[14] GT11_1:SH_INVALID_CNT_MAX[6]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[13] GT11_1:SH_INVALID_CNT_MAX[5]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[12] GT11_1:SH_INVALID_CNT_MAX[4]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[11] GT11_1:SH_INVALID_CNT_MAX[3]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[10] GT11_1:SH_INVALID_CNT_MAX[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[9] GT11_1:SH_INVALID_CNT_MAX[1]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[8] GT11_1:SH_INVALID_CNT_MAX[0]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[7] GT11_1:SH_CNT_MAX[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[6] GT11_1:SH_CNT_MAX[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[5] GT11_1:SH_CNT_MAX[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[4] GT11_1:SH_CNT_MAX[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[3] GT11_1:SH_CNT_MAX[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[2] GT11_1:SH_CNT_MAX[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[1] GT11_1:SH_CNT_MAX[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4B[0] GT11_1:SH_CNT_MAX[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP43_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP43[15] GT11_1:RESERVED_M2
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_8B10B_DE GT11_1:DRP43[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_CORRECT_USE GT11_1:DRP43[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_LEN[2] GT11_1:DRP43[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_LEN[1] GT11_1:DRP43[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_LEN[0] GT11_1:DRP43[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_DROP GT11_1:DRP43[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_USE GT11_1:DRP43[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP43[7] GT11_1:TXCLK0_INVERT_PMALEAF
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP43[6] GT11_1:RXCLK0_INVERT_PMALEAF
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[5] GT11_1:DRP43[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[4] GT11_1:DRP43[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[3] GT11_1:DRP43[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[2] GT11_1:DRP43[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[1] GT11_1:DRP43[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MAX_LAT[0] GT11_1:DRP43[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 23
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[15] GT11_1:RX_LOS_THRESHOLD[7]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[14] GT11_1:RX_LOS_THRESHOLD[6]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[13] GT11_1:RX_LOS_THRESHOLD[5]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[12] GT11_1:RX_LOS_THRESHOLD[4]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[11] GT11_1:RX_LOS_THRESHOLD[3]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[10] GT11_1:RX_LOS_THRESHOLD[2]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[9] GT11_1:RX_LOS_THRESHOLD[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[8] GT11_1:RX_LOS_THRESHOLD[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[7] GT11_1:RX_LOS_INVALID_INCR[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[6] GT11_1:RX_LOS_INVALID_INCR[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[5] GT11_1:RX_LOS_INVALID_INCR[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[4] GT11_1:RX_LOS_INVALID_INCR[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[3] GT11_1:RX_LOS_INVALID_INCR[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[2] GT11_1:RX_LOS_INVALID_INCR[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[1] GT11_1:RX_LOS_INVALID_INCR[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7B[0] GT11_1:RX_LOS_INVALID_INCR[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP73_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_MASK[3] GT11_1:DRP73[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_MASK[2] GT11_1:DRP73[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_MASK[1] GT11_1:DRP73[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_MASK[0] GT11_1:DRP73[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[10] GT11_1:DRP73[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[9] GT11_1:DRP73[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[8] GT11_1:DRP73[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[7] GT11_1:DRP73[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[6] GT11_1:DRP73[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[5] GT11_1:DRP73[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[4] GT11_1:DRP73[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[3] GT11_1:DRP73[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[2] GT11_1:DRP73[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[1] GT11_1:DRP73[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_4[0] GT11_1:DRP73[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[10] GT11_1:DRP73[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6B_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[9] GT11_1:DRP6B[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[8] GT11_1:DRP6B[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[7] GT11_1:DRP6B[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[6] GT11_1:DRP6B[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[5] GT11_1:DRP6B[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[4] GT11_1:DRP6B[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[3] GT11_1:DRP6B[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[2] GT11_1:DRP6B[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[1] GT11_1:DRP6B[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_3[0] GT11_1:DRP6B[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[10] GT11_1:DRP6B[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[9] GT11_1:DRP6B[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[8] GT11_1:DRP6B[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[7] GT11_1:DRP6B[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[6] GT11_1:DRP6B[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[5] GT11_1:DRP6B[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP63_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[4] GT11_1:DRP63[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[3] GT11_1:DRP63[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[2] GT11_1:DRP63[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[1] GT11_1:DRP63[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_2[0] GT11_1:DRP63[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[10] GT11_1:DRP63[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[9] GT11_1:DRP63[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[8] GT11_1:DRP63[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[7] GT11_1:DRP63[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[6] GT11_1:DRP63[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[5] GT11_1:DRP63[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[4] GT11_1:DRP63[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[3] GT11_1:DRP63[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[2] GT11_1:DRP63[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[1] GT11_1:DRP63[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_2_1[0] GT11_1:DRP63[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 24
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[15] GT11_1:TXLNDR_TST1[3]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[14] GT11_1:TXLNDR_TST1[2]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[13] GT11_1:TXLNDR_TST1[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[12] GT11_1:TXLNDR_TST1[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[11] GT11_1:TXLVLSHFTPD
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[10] GT11_1:TXPRE_PRDRV_DAC[2]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[9] GT11_1:TXPRE_PRDRV_DAC[1]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[8] GT11_1:TXPRE_PRDRV_DAC[0]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[7] GT11_1:TXPRE_TAP_PD
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[6] GT11_1:TXPRE_TAP_DAC[4]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[5] GT11_1:TXPRE_TAP_DAC[3]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[4] GT11_1:TXDIGPD
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[3] GT11_1:TXCLKMODE[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[2] GT11_1:TXCLKMODE[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[1] GT11_1:TXCLKMODE[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5C[0] GT11_1:TXCLKMODE[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[15] GT11_1:TXPRE_TAP_DAC[2]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[14] GT11_1:TXPRE_TAP_DAC[1]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[13] GT11_1:TXPRE_TAP_DAC[0]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[12] GT11_1:TXCFGENABLE
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[11] GT11_1:TXHIGHSIGNALEN
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[10] GT11_1:TXAREFBIASSEL
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[9] GT11_1:TXTERMTRIM[3]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[8] GT11_1:TXTERMTRIM[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[7] GT11_1:TXTERMTRIM[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[6] GT11_1:TXTERMTRIM[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[5] GT11_1:TXASYNCDIVIDE[1]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[4] GT11_1:TXSLEWRATE
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[3] GT11_1:TXPOST_PRDRV_DAC[2]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[2] GT11_1:TXPOST_PRDRV_DAC[1]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[1] GT11_1:TXPOST_PRDRV_DAC[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP54[0] GT11_1:TXDAT_PRDRV_DAC[2]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[15] GT11_1:TXDAT_PRDRV_DAC[1]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[14] GT11_1:TXDAT_PRDRV_DAC[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[13] GT11_1:TXASYNCDIVIDE[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[12] GT11_1:TXPOST_TAP_PD
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[11] GT11_1:TXPOST_TAP_DAC[4]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[10] GT11_1:TXPOST_TAP_DAC[3]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[9] GT11_1:TXPOST_TAP_DAC[2]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[8] GT11_1:TXPOST_TAP_DAC[1]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[7] GT11_1:TXPOST_TAP_DAC[0]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[6] GT11_1:TXLNDR_TST2[1]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[5] GT11_1:TXLNDR_TST2[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[4] GT11_1:TXDAT_TAP_DAC[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[3] GT11_1:TXDAT_TAP_DAC[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[2] GT11_1:TXDAT_TAP_DAC[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[1] GT11_1:TXDAT_TAP_DAC[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4C[0] GT11_1:TXDAT_TAP_DAC[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[15] GT11_1:TXLNDR_TST3[14]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[14] GT11_1:TXLNDR_TST3[13]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[13] GT11_1:TXLNDR_TST3[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[12] GT11_1:TXLNDR_TST3[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[11] GT11_1:TXLNDR_TST3[10]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[10] GT11_1:TXLNDR_TST3[9]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[9] GT11_1:TXLNDR_TST3[8]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[8] GT11_1:TXLNDR_TST3[7]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[7] GT11_1:TXLNDR_TST3[6]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[6] GT11_1:TXLNDR_TST3[5]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[5] GT11_1:TXLNDR_TST3[4]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[4] GT11_1:TXLNDR_TST3[3]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[3] GT11_1:TXLNDR_TST3[2]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[2] GT11_1:TXLNDR_TST3[1]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[1] GT11_1:TXLNDR_TST3[0]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP44[0] GT11_1:TXPD
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 25
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[15] GT11_1:RXDATA_SEL[1]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[14] GT11_1:RXDATA_SEL[0]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[13] GT11_1:TXDATA_SEL[1]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[12] GT11_1:TXDATA_SEL[0]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[11] GT11_1:RESERVED_CCB
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[5] GT11_1:DRP7C[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[4] GT11_1:DRP7C[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[3] GT11_1:DRP7C[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[2] GT11_1:DRP7C[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[1] GT11_1:DRP7C[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_MIN_LAT[0] GT11_1:DRP7C[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[4] GT11_1:RESERVED_CCA
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7C[3] GT11_1:PCS_BIT_SLIP
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DIGRX_SYNC_MODE GT11_1:DRP7C[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DIGRX_FWDCLK[1] GT11_1:DRP7C[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DIGRX_FWDCLK[0] GT11_1:DRP7C[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP74_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_MASK[3] GT11_1:DRP74[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_MASK[2] GT11_1:DRP74[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_MASK[1] GT11_1:DRP74[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_MASK[0] GT11_1:DRP74[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[10] GT11_1:DRP74[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[9] GT11_1:DRP74[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[8] GT11_1:DRP74[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[7] GT11_1:DRP74[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[6] GT11_1:DRP74[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[5] GT11_1:DRP74[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[4] GT11_1:DRP74[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[3] GT11_1:DRP74[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[2] GT11_1:DRP74[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[1] GT11_1:DRP74[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_4[0] GT11_1:DRP74[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[10] GT11_1:DRP74[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6C_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[9] GT11_1:DRP6C[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[8] GT11_1:DRP6C[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[7] GT11_1:DRP6C[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[6] GT11_1:DRP6C[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[5] GT11_1:DRP6C[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[4] GT11_1:DRP6C[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[3] GT11_1:DRP6C[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[2] GT11_1:DRP6C[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[1] GT11_1:DRP6C[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_3[0] GT11_1:DRP6C[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[10] GT11_1:DRP6C[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[9] GT11_1:DRP6C[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[8] GT11_1:DRP6C[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[7] GT11_1:DRP6C[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[6] GT11_1:DRP6C[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[5] GT11_1:DRP6C[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP64_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[4] GT11_1:DRP64[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[3] GT11_1:DRP64[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[2] GT11_1:DRP64[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[1] GT11_1:DRP64[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_2[0] GT11_1:DRP64[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[10] GT11_1:DRP64[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[9] GT11_1:DRP64[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[8] GT11_1:DRP64[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[7] GT11_1:DRP64[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[6] GT11_1:DRP64[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[5] GT11_1:DRP64[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[4] GT11_1:DRP64[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[3] GT11_1:DRP64[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[2] GT11_1:DRP64[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[1] GT11_1:DRP64[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CLK_COR_SEQ_1_1[0] GT11_1:DRP64[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 26
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[14]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[13]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5D[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP55[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4D[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP45[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 27
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[14] GT11_1:RXOUTDIV2SEL[5]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[13] GT11_1:RXOUTDIV2SEL[3]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[12] GT11_1:RXOUTDIV2SEL[1]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[11] GT11_1:RXPLLNDIVSEL[2]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[10] GT11_1:RXPLLNDIVSEL[1]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[9] GT11_1:RXPLLNDIVSEL[0]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[7] GT11_1:RXCLMODE[1]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[6] GT11_1:RXCLMODE[0]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[5] GT11_1:RXLOOPFILT[3]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[4] GT11_1:RXLOOPFILT[2]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[3] GT11_1:RXLOOPFILT[1]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[2] GT11_1:RXLOOPFILT[0]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[1] GT11_1:RXDIGRX
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7D[0] GT11_1:RXPFDTX
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[15] GT11_1:RXTUNE[12]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[14] GT11_1:RXTUNE[11]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[13] GT11_1:RXTUNE[10]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[12] GT11_1:RXTUNE[9]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[11] GT11_1:RXTUNE[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[10] GT11_1:RXTUNE[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[9] GT11_1:RXTUNE[6]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[8] GT11_1:RXTUNE[5]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[7] GT11_1:RXTUNE[4]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[6] GT11_1:RXTUNE[3]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[5] GT11_1:RXTUNE[2]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[4] GT11_1:RXTUNE[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[3] GT11_1:RXTUNE[0]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[2] GT11_1:RXSLOSEL
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[1] GT11_1:RXDACSEL
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP75[0] GT11_1:RXCPSEL
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[15] GT11_1:RXDACTST
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[13] GT11_1:RXOUTDIV2SEL[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[12] GT11_1:RXOUTDIV2SEL[2]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[11] GT11_1:RXOUTDIV2SEL[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[10] GT11_1:RXCTRL1[9]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[9] GT11_1:RXCTRL1[8]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[8] GT11_1:RXCTRL1[7]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[7] GT11_1:RXCTRL1[6]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[6] GT11_1:RXCTRL1[5]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[5] GT11_1:RXCTRL1[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[4] GT11_1:RXCTRL1[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[3] GT11_1:RXCTRL1[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[2] GT11_1:RXCTRL1[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[1] GT11_1:RXCTRL1[0]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6D[0] GT11_1:RXQPPD
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[15] GT11_1:RXCMFPD
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[14] GT11_1:RXVCOPD
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[13] GT11_1:RXADCADJPD
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[12] GT11_1:RXDIVPD
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[11] GT11_1:RXBIASPD
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[10] GT11_1:RXVCOBUFPD
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[9] GT11_1:RXDIVBUFPD
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[8] GT11_1:RXAPD
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[7] GT11_1:RXAPTST
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[6] GT11_1:RXCMFTST
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[5] GT11_1:RXFILTTST
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[4] GT11_1:RXDIVTST
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[3] GT11_1:RXPFDTST
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[2] GT11_1:RXVCOBUFTST
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[1] GT11_1:RXDIVBUFTST
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP65[0] GT11_1:RXVCOTST
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 28
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[15] GT11_1:RXMODE[5]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[14] GT11_1:RXMODE[4]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[13] GT11_1:RXMODE[3]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[12] GT11_1:RXMODE[2]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[11] GT11_1:RXMODE[1]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[10] GT11_1:RXMODE[0]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[9] GT11_1:PMA_BIT_SLIP
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[8] GT11_1:RXASYNCDIVIDE[1]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[7] GT11_1:RXASYNCDIVIDE[0]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[6] GT11_1:RXCLKMODE[5]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[5] GT11_1:RXCLKMODE[4]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[4] GT11_1:RXCLKMODE[3]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[3] GT11_1:RXCLKMODE[2]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[2] GT11_1:RXCLKMODE[1]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[1] GT11_1:RXCLKMODE[0]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5E[0] GT11_1:RXLB
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[15] GT11_1:RXFETUNE[1]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[14] GT11_1:RXFETUNE[0]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[13] GT11_1:RXRCPADJ[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[12] GT11_1:RXRCPADJ[1]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[11] GT11_1:RXRCPADJ[0]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[10] GT11_1:RXRIBADJ[1]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[9] GT11_1:RXRIBADJ[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[8] GT11_1:RXAFEEQ[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[7] GT11_1:RXAFEEQ[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[6] GT11_1:RXAFEEQ[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[5] GT11_1:RXAFEEQ[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[4] GT11_1:RXAFEEQ[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[3] GT11_1:RXAFEEQ[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[2] GT11_1:RXAFEEQ[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[1] GT11_1:RXAFEEQ[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP56[0] GT11_1:RXAFEEQ[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[15] GT11_1:RXCMADJ[1]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[14] GT11_1:RXCMADJ[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[13] GT11_1:RXCDRLOS[5]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[12] GT11_1:RXCDRLOS[4]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[11] GT11_1:RXCDRLOS[3]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[10] GT11_1:RXCDRLOS[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[9] GT11_1:RXCDRLOS[1]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[8] GT11_1:RXCDRLOS[0]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[7] GT11_1:RXTADJ
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[6] GT11_1:RXDCCOUPLE
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[4] GT11_1:RXLKADJ[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[3] GT11_1:RXLKADJ[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[2] GT11_1:RXLKADJ[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[1] GT11_1:RXLKADJ[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4E[0] GT11_1:RXLKADJ[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[15] GT11_1:RXDIGRESET
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[14] GT11_1:RXFECONTROL2[2]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[13] GT11_1:RXFECONTROL2[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[12] GT11_1:RXFECONTROL2[0]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[11] GT11_1:RXCPTST
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[10] GT11_1:RXPDDTST
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[9] GT11_1:RXACTST
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[8] GT11_1:RXAFETST
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[7] GT11_1:RXFECONTROL1[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[6] GT11_1:RXFECONTROL1[0]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[5] GT11_1:RXLKAPD
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[4] GT11_1:RXRSDPD
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[3] GT11_1:RXRCPPD
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[2] GT11_1:RXRPDPD
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[1] GT11_1:RXAFEPD
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP46[0] GT11_1:RXPD
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 29
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[7] GT11_1:DRP7E[15]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[6] GT11_1:DRP7E[14]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[5] GT11_1:DRP7E[13]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[4] GT11_1:DRP7E[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[3] GT11_1:DRP7E[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[2] GT11_1:DRP7E[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[1] GT11_1:DRP7E[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_TUNE[0] GT11_1:DRP7E[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CCCB_ARBITRATOR_DISABLE GT11_1:DRP7E[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[4] GT11_1:OPPOSITE_SELECT
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[3] GT11_1:POWER_ENABLE
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[2] GT11_1:TEST_MODE_3
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[1] GT11_1:TEST_MODE_2
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7E[0] GT11_1:TEST_MODE_1
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP76_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_MASK[3] GT11_1:DRP76[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_MASK[2] GT11_1:DRP76[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_MASK[1] GT11_1:DRP76[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_MASK[0] GT11_1:DRP76[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[10] GT11_1:DRP76[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[9] GT11_1:DRP76[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[8] GT11_1:DRP76[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[7] GT11_1:DRP76[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[6] GT11_1:DRP76[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[5] GT11_1:DRP76[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[4] GT11_1:DRP76[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[3] GT11_1:DRP76[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[2] GT11_1:DRP76[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[1] GT11_1:DRP76[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_4[0] GT11_1:DRP76[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[10] GT11_1:DRP76[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6E_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[9] GT11_1:DRP6E[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[8] GT11_1:DRP6E[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[7] GT11_1:DRP6E[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[6] GT11_1:DRP6E[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[5] GT11_1:DRP6E[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[4] GT11_1:DRP6E[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[3] GT11_1:DRP6E[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[2] GT11_1:DRP6E[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[1] GT11_1:DRP6E[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_3[0] GT11_1:DRP6E[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[10] GT11_1:DRP6E[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[9] GT11_1:DRP6E[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[8] GT11_1:DRP6E[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[7] GT11_1:DRP6E[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[6] GT11_1:DRP6E[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[5] GT11_1:DRP6E[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP66_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[4] GT11_1:DRP66[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[3] GT11_1:DRP66[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[2] GT11_1:DRP66[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[1] GT11_1:DRP66[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_2[0] GT11_1:DRP66[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[10] GT11_1:DRP66[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[9] GT11_1:DRP66[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[8] GT11_1:DRP66[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[7] GT11_1:DRP66[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[6] GT11_1:DRP66[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[5] GT11_1:DRP66[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[4] GT11_1:DRP66[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[3] GT11_1:DRP66[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[2] GT11_1:DRP66[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[1] GT11_1:DRP66[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_1[0] GT11_1:DRP66[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 30
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[15] GT11_1:RXEQ[63]
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[14] GT11_1:RXEQ[62]
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[13] GT11_1:RXEQ[61]
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[12] GT11_1:RXEQ[60]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[11] GT11_1:RXEQ[59]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[10] GT11_1:RXEQ[58]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[9] GT11_1:RXEQ[57]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[8] GT11_1:RXEQ[56]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[7] GT11_1:RXEQ[55]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[6] GT11_1:RXEQ[54]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[5] GT11_1:RXEQ[53]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[4] GT11_1:RXEQ[52]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[3] GT11_1:RXEQ[51]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[2] GT11_1:RXEQ[50]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[1] GT11_1:RXEQ[49]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP5F[0] GT11_1:RXEQ[48]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[15] GT11_1:RXEQ[47]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[14] GT11_1:RXEQ[46]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[13] GT11_1:RXEQ[45]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[12] GT11_1:RXEQ[44]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[11] GT11_1:RXEQ[43]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[10] GT11_1:RXEQ[42]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[9] GT11_1:RXEQ[41]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[8] GT11_1:RXEQ[40]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[7] GT11_1:RXEQ[39]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[6] GT11_1:RXEQ[38]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[5] GT11_1:RXEQ[37]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[4] GT11_1:RXEQ[36]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[3] GT11_1:RXEQ[35]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[2] GT11_1:RXEQ[34]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[1] GT11_1:RXEQ[33]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP57[0] GT11_1:RXEQ[32]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[15] GT11_1:RXEQ[31]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[14] GT11_1:RXEQ[30]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[13] GT11_1:RXEQ[29]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[12] GT11_1:RXEQ[28]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[11] GT11_1:RXEQ[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[10] GT11_1:RXEQ[26]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[9] GT11_1:RXEQ[25]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[8] GT11_1:RXEQ[24]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[7] GT11_1:RXEQ[23]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[6] GT11_1:RXEQ[22]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[5] GT11_1:RXEQ[21]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[4] GT11_1:RXEQ[20]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[3] GT11_1:RXEQ[19]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[2] GT11_1:RXEQ[18]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[1] GT11_1:RXEQ[17]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP4F[0] GT11_1:RXEQ[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[15] GT11_1:RXEQ[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[14] GT11_1:RXEQ[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[13] GT11_1:RXEQ[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[12] GT11_1:RXEQ[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[11] GT11_1:RXEQ[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[10] GT11_1:RXEQ[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[9] GT11_1:RXEQ[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[8] GT11_1:RXEQ[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[7] GT11_1:RXEQ[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[6] GT11_1:RXEQ[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[5] GT11_1:RXEQ[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[4] GT11_1:RXEQ[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[3] GT11_1:RXEQ[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[2] GT11_1:RXEQ[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[1] GT11_1:RXEQ[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP47[0] GT11_1:RXEQ[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex4 MGT bittile 31
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19
78	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7F_MASK
77	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
76	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7F[15] GT11_1:RESERVED_CB1
75	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7F[14] GT11_1:TX_BUFFER_USE
74	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7F[13] GT11_1:RX_BUFFER_USE
73	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_LEN[2] GT11_1:DRP7F[12]
72	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_LEN[1] GT11_1:DRP7F[11]
71	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_LEN[0] GT11_1:DRP7F[10]
70	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_2_USE GT11_1:DRP7F[9]
69	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_ONE_SHOT GT11_1:DRP7F[8]
68	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_MODE[1] GT11_1:DRP7F[7]
67	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_MODE[0] GT11_1:DRP7F[6]
66	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP7F[5]
65	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_LIMIT[4] GT11_1:DRP7F[4]
64	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_LIMIT[3] GT11_1:DRP7F[3]
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_LIMIT[2] GT11_1:DRP7F[2]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_LIMIT[1] GT11_1:DRP7F[1]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_LIMIT[0] GT11_1:DRP7F[0]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP77_MASK
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_MASK[3] GT11_1:DRP77[15]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_MASK[2] GT11_1:DRP77[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_MASK[1] GT11_1:DRP77[13]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_MASK[0] GT11_1:DRP77[12]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[10] GT11_1:DRP77[11]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[9] GT11_1:DRP77[10]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[8] GT11_1:DRP77[9]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[7] GT11_1:DRP77[8]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[6] GT11_1:DRP77[7]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[5] GT11_1:DRP77[6]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[4] GT11_1:DRP77[5]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[3] GT11_1:DRP77[4]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[2] GT11_1:DRP77[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[1] GT11_1:DRP77[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_4[0] GT11_1:DRP77[1]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[10] GT11_1:DRP77[0]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP6F_MASK
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[9] GT11_1:DRP6F[15]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[8] GT11_1:DRP6F[14]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[7] GT11_1:DRP6F[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[6] GT11_1:DRP6F[12]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[5] GT11_1:DRP6F[11]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[4] GT11_1:DRP6F[10]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[3] GT11_1:DRP6F[9]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[2] GT11_1:DRP6F[8]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[1] GT11_1:DRP6F[7]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_3[0] GT11_1:DRP6F[6]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[10] GT11_1:DRP6F[5]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[9] GT11_1:DRP6F[4]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[8] GT11_1:DRP6F[3]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[7] GT11_1:DRP6F[2]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[6] GT11_1:DRP6F[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[5] GT11_1:DRP6F[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:DRP67_MASK
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[4] GT11_1:DRP67[15]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[3] GT11_1:DRP67[14]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[2] GT11_1:DRP67[13]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[1] GT11_1:DRP67[12]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_2[0] GT11_1:DRP67[11]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[10] GT11_1:DRP67[10]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[9] GT11_1:DRP67[9]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[8] GT11_1:DRP67[8]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[7] GT11_1:DRP67[7]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[6] GT11_1:DRP67[6]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[5] GT11_1:DRP67[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[4] GT11_1:DRP67[4]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[3] GT11_1:DRP67[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[2] GT11_1:DRP67[2]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[1] GT11_1:DRP67[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GT11_1:CHAN_BOND_SEQ_1_1[0] GT11_1:DRP67[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

GT11_0:ALIGN_COMMA_WORD	4.19.2	4.19.1
GT11_1:ALIGN_COMMA_WORD	20.19.2	20.19.1
1	0	0
2	0	1
4	1	0

GT11_0:AUTO_CAL	1.19.76
GT11_0:BYPASS_CAL	1.19.56
GT11_0:BYPASS_FDET	1.19.63
GT11_0:CCCB_ARBITRATOR_DISABLE	13.19.66
GT11_0:CHAN_BOND_ONE_SHOT	15.19.69
GT11_0:CHAN_BOND_SEQ_2_USE	15.19.70
GT11_0:CLK_CORRECT_USE	6.19.14
GT11_0:CLK_COR_8B10B_DE	6.19.15
GT11_0:CLK_COR_SEQ_2_USE	6.19.9
GT11_0:CLK_COR_SEQ_DROP	6.19.10
GT11_0:COMMA32	4.19.8
GT11_0:DEC_MCOMMA_DETECT	4.19.3
GT11_0:DEC_PCOMMA_DETECT	4.19.4
GT11_0:DEC_VALID_COMMA_ONLY	4.19.5
GT11_0:DIGRX_SYNC_MODE	9.19.63
GT11_0:DRP40_MASK	0.19.18
GT11_0:DRP41_MASK	2.19.18
GT11_0:DRP42_MASK	4.19.18
GT11_0:DRP43_MASK	6.19.18
GT11_0:DRP44_MASK	8.19.18
GT11_0:DRP45_MASK	10.19.18
GT11_0:DRP46_MASK	12.19.18
GT11_0:DRP47_MASK	14.19.18
GT11_0:DRP48_MASK	0.19.38
GT11_0:DRP49_MASK	2.19.38
GT11_0:DRP4A_MASK	4.19.38
GT11_0:DRP4B_MASK	6.19.38
GT11_0:DRP4C_MASK	8.19.38
GT11_0:DRP4D_MASK	10.19.38
GT11_0:DRP4E_MASK	12.19.38
GT11_0:DRP4F_MASK	14.19.38
GT11_0:DRP50_MASK	0.19.58
GT11_0:DRP51_MASK	2.19.58
GT11_0:DRP52_MASK	4.19.58
GT11_0:DRP53_MASK	6.19.58
GT11_0:DRP54_MASK	8.19.58
GT11_0:DRP55_MASK	10.19.58
GT11_0:DRP56_MASK	12.19.58
GT11_0:DRP57_MASK	14.19.58
GT11_0:DRP58_MASK	0.19.78
GT11_0:DRP59_MASK	2.19.78
GT11_0:DRP5A_MASK	4.19.78
GT11_0:DRP5B_MASK	6.19.78
GT11_0:DRP5C_MASK	8.19.78
GT11_0:DRP5D_MASK	10.19.78
GT11_0:DRP5E_MASK	12.19.78
GT11_0:DRP5F_MASK	14.19.78
GT11_0:DRP60_MASK	1.19.18
GT11_0:DRP61_MASK	3.19.18
GT11_0:DRP62_MASK	5.19.18
GT11_0:DRP63_MASK	7.19.18
GT11_0:DRP64_MASK	9.19.18
GT11_0:DRP65_MASK	11.19.18
GT11_0:DRP66_MASK	13.19.18
GT11_0:DRP67_MASK	15.19.18
GT11_0:DRP68_MASK	1.19.38
GT11_0:DRP69_MASK	3.19.38
GT11_0:DRP6A_MASK	5.19.38
GT11_0:DRP6B_MASK	7.19.38
GT11_0:DRP6C_MASK	9.19.38
GT11_0:DRP6D_MASK	11.19.38
GT11_0:DRP6E_MASK	13.19.38
GT11_0:DRP6F_MASK	15.19.38
GT11_0:DRP70_MASK	1.19.58
GT11_0:DRP71_MASK	3.19.58
GT11_0:DRP72_MASK	5.19.58
GT11_0:DRP73_MASK	7.19.58
GT11_0:DRP74_MASK	9.19.58
GT11_0:DRP75_MASK	11.19.58
GT11_0:DRP76_MASK	13.19.58
GT11_0:DRP77_MASK	15.19.58
GT11_0:DRP78_MASK	1.19.78
GT11_0:DRP79_MASK	3.19.78
GT11_0:DRP7A_MASK	5.19.78
GT11_0:DRP7B_MASK	7.19.78
GT11_0:DRP7C_MASK	9.19.78
GT11_0:DRP7D_MASK	11.19.78
GT11_0:DRP7E_MASK	13.19.78
GT11_0:DRP7F_MASK	15.19.78
GT11_0:ENABLE_DCDR	6.19.50
GT11_0:MCOMMA_DETECT	4.19.6
GT11_0:OPPOSITE_SELECT	13.19.65
GT11_0:PCOMMA_DETECT	4.19.7
GT11_0:PCS_BIT_SLIP	9.19.64
GT11_0:PMA_BIT_SLIP	5.19.70
GT11_0:POWER_ENABLE	13.19.64
GT11_0:REPEATER	6.19.51
GT11_0:RESERVED_CB1	15.19.76
GT11_0:RESERVED_CCA	9.19.65
GT11_0:RESERVED_CCB	9.19.72
GT11_0:RESERVED_M2	6.19.16
GT11_0:RXACTST	5.19.10
GT11_0:RXADCADJPD	2.19.14
GT11_0:RXAFEPD	5.19.2
GT11_0:RXAFETST	5.19.9
GT11_0:RXAPD	2.19.9
GT11_0:RXAPTST	2.19.8
GT11_0:RXAUTO_CAL	1.19.36
GT11_0:RXBIASPD	2.19.12
GT11_0:RXBYPASS_CAL	1.19.16
GT11_0:RXBYPASS_FDET	1.19.23
GT11_0:RXBY_32	6.19.52
GT11_0:RXCLK0_FORCE_PMACLK	6.19.73
GT11_0:RXCLK0_INVERT_PMALEAF	6.19.7
GT11_0:RXCMFPD	2.19.16
GT11_0:RXCMFTST	2.19.7
GT11_0:RXCPSEL	2.19.41
GT11_0:RXCPTST	5.19.12
GT11_0:RXCRCCLOCKDOUBLE	6.19.61
GT11_0:RXCRCENABLE	6.19.64
GT11_0:RXCRCINVERTGEN	6.19.62
GT11_0:RXCRCSAMECLOCK	6.19.63
GT11_0:RXDACSEL	2.19.42
GT11_0:RXDACTST	2.19.36
GT11_0:RXDCCOUPLE	5.19.27
GT11_0:RXDIGRESET	5.19.16
GT11_0:RXDIGRX	2.19.62
GT11_0:RXDIVBUFPD	2.19.10
GT11_0:RXDIVBUFTST	2.19.2
GT11_0:RXDIVPD	2.19.13
GT11_0:RXDIVTST	2.19.5
GT11_0:RXFILTTST	2.19.6
GT11_0:RXLB	5.19.61
GT11_0:RXLKAPD	5.19.6
GT11_0:RXPD	5.19.1
GT11_0:RXPDDTST	5.19.11
GT11_0:RXPFDTST	2.19.4
GT11_0:RXPFDTX	2.19.61
GT11_0:RXQPPD	2.19.21
GT11_0:RXRCPPD	5.19.4
GT11_0:RXRECCLK1_USE_SYNC	6.19.76
GT11_0:RXRPDPD	5.19.3
GT11_0:RXRSDPD	5.19.5
GT11_0:RXSLOSEL	2.19.43
GT11_0:RXTADJ	5.19.28
GT11_0:RXVCOBUFPD	2.19.11
GT11_0:RXVCOBUFTST	2.19.3
GT11_0:RXVCOPD	2.19.15
GT11_0:RXVCOTST	2.19.1
GT11_0:RXVCO_CTRL_ENABLE	1.19.3
GT11_0:RX_BUFFER_USE	15.19.74
GT11_0:SAMPLE_8X	6.19.49
GT11_0:TEST_MODE_1	13.19.61
GT11_0:TEST_MODE_2	13.19.62
GT11_0:TEST_MODE_3	13.19.63
GT11_0:TXAREFBIASSEL	12.19.51
GT11_0:TXCFGENABLE	12.19.53
GT11_0:TXCLK0_FORCE_PMACLK	6.19.74
GT11_0:TXCLK0_INVERT_PMALEAF	6.19.8
GT11_0:TXCRCCLOCKDOUBLE	6.19.65
GT11_0:TXCRCENABLE	6.19.68
GT11_0:TXCRCINVERTGEN	6.19.66
GT11_0:TXCRCSAMECLOCK	6.19.67
GT11_0:TXDIGPD	12.19.65
GT11_0:TXHIGHSIGNALEN	12.19.52
GT11_0:TXLVLSHFTPD	12.19.72
GT11_0:TXOUTCLK1_USE_SYNC	6.19.75
GT11_0:TXPD	12.19.1
GT11_0:TXPHASESEL	10.19.4
GT11_0:TXPOST_TAP_PD	12.19.33
GT11_0:TXPRE_TAP_PD	12.19.68
GT11_0:TXSLEWRATE	12.19.45
GT11_0:TX_BUFFER_USE	15.19.75
GT11_0:VCO_CTRL_ENABLE	1.19.43
GT11_1:AUTO_CAL	17.19.76
GT11_1:BYPASS_CAL	17.19.56
GT11_1:BYPASS_FDET	17.19.63
GT11_1:CCCB_ARBITRATOR_DISABLE	29.19.66
GT11_1:CHAN_BOND_ONE_SHOT	31.19.69
GT11_1:CHAN_BOND_SEQ_2_USE	31.19.70
GT11_1:CLK_CORRECT_USE	22.19.14
GT11_1:CLK_COR_8B10B_DE	22.19.15
GT11_1:CLK_COR_SEQ_2_USE	22.19.9
GT11_1:CLK_COR_SEQ_DROP	22.19.10
GT11_1:COMMA32	20.19.8
GT11_1:DEC_MCOMMA_DETECT	20.19.3
GT11_1:DEC_PCOMMA_DETECT	20.19.4
GT11_1:DEC_VALID_COMMA_ONLY	20.19.5
GT11_1:DIGRX_SYNC_MODE	25.19.63
GT11_1:DRP40_MASK	16.19.18
GT11_1:DRP41_MASK	18.19.18
GT11_1:DRP42_MASK	20.19.18
GT11_1:DRP43_MASK	22.19.18
GT11_1:DRP44_MASK	24.19.18
GT11_1:DRP45_MASK	26.19.18
GT11_1:DRP46_MASK	28.19.18
GT11_1:DRP47_MASK	30.19.18
GT11_1:DRP48_MASK	16.19.38
GT11_1:DRP49_MASK	18.19.38
GT11_1:DRP4A_MASK	20.19.38
GT11_1:DRP4B_MASK	22.19.38
GT11_1:DRP4C_MASK	24.19.38
GT11_1:DRP4D_MASK	26.19.38
GT11_1:DRP4E_MASK	28.19.38
GT11_1:DRP4F_MASK	30.19.38
GT11_1:DRP50_MASK	16.19.58
GT11_1:DRP51_MASK	18.19.58
GT11_1:DRP52_MASK	20.19.58
GT11_1:DRP53_MASK	22.19.58
GT11_1:DRP54_MASK	24.19.58
GT11_1:DRP55_MASK	26.19.58
GT11_1:DRP56_MASK	28.19.58
GT11_1:DRP57_MASK	30.19.58
GT11_1:DRP58_MASK	16.19.78
GT11_1:DRP59_MASK	18.19.78
GT11_1:DRP5A_MASK	20.19.78
GT11_1:DRP5B_MASK	22.19.78
GT11_1:DRP5C_MASK	24.19.78
GT11_1:DRP5D_MASK	26.19.78
GT11_1:DRP5E_MASK	28.19.78
GT11_1:DRP5F_MASK	30.19.78
GT11_1:DRP60_MASK	17.19.18
GT11_1:DRP61_MASK	19.19.18
GT11_1:DRP62_MASK	21.19.18
GT11_1:DRP63_MASK	23.19.18
GT11_1:DRP64_MASK	25.19.18
GT11_1:DRP65_MASK	27.19.18
GT11_1:DRP66_MASK	29.19.18
GT11_1:DRP67_MASK	31.19.18
GT11_1:DRP68_MASK	17.19.38
GT11_1:DRP69_MASK	19.19.38
GT11_1:DRP6A_MASK	21.19.38
GT11_1:DRP6B_MASK	23.19.38
GT11_1:DRP6C_MASK	25.19.38
GT11_1:DRP6D_MASK	27.19.38
GT11_1:DRP6E_MASK	29.19.38
GT11_1:DRP6F_MASK	31.19.38
GT11_1:DRP70_MASK	17.19.58
GT11_1:DRP71_MASK	19.19.58
GT11_1:DRP72_MASK	21.19.58
GT11_1:DRP73_MASK	23.19.58
GT11_1:DRP74_MASK	25.19.58
GT11_1:DRP75_MASK	27.19.58
GT11_1:DRP76_MASK	29.19.58
GT11_1:DRP77_MASK	31.19.58
GT11_1:DRP78_MASK	17.19.78
GT11_1:DRP79_MASK	19.19.78
GT11_1:DRP7A_MASK	21.19.78
GT11_1:DRP7B_MASK	23.19.78
GT11_1:DRP7C_MASK	25.19.78
GT11_1:DRP7D_MASK	27.19.78
GT11_1:DRP7E_MASK	29.19.78
GT11_1:DRP7F_MASK	31.19.78
GT11_1:ENABLE_DCDR	22.19.50
GT11_1:MCOMMA_DETECT	20.19.6
GT11_1:OPPOSITE_SELECT	29.19.65
GT11_1:PCOMMA_DETECT	20.19.7
GT11_1:PCS_BIT_SLIP	25.19.64
GT11_1:PMA_BIT_SLIP	28.19.70
GT11_1:POWER_ENABLE	29.19.64
GT11_1:REPEATER	22.19.51
GT11_1:RESERVED_CB1	31.19.76
GT11_1:RESERVED_CCA	25.19.65
GT11_1:RESERVED_CCB	25.19.72
GT11_1:RESERVED_M2	22.19.16
GT11_1:RXACTST	28.19.10
GT11_1:RXADCADJPD	27.19.14
GT11_1:RXAFEPD	28.19.2
GT11_1:RXAFETST	28.19.9
GT11_1:RXAPD	27.19.9
GT11_1:RXAPTST	27.19.8
GT11_1:RXAUTO_CAL	17.19.36
GT11_1:RXBIASPD	27.19.12
GT11_1:RXBYPASS_CAL	17.19.16
GT11_1:RXBYPASS_FDET	17.19.23
GT11_1:RXBY_32	22.19.52
GT11_1:RXCLK0_FORCE_PMACLK	22.19.73
GT11_1:RXCLK0_INVERT_PMALEAF	22.19.7
GT11_1:RXCMFPD	27.19.16
GT11_1:RXCMFTST	27.19.7
GT11_1:RXCPSEL	27.19.41
GT11_1:RXCPTST	28.19.12
GT11_1:RXCRCCLOCKDOUBLE	22.19.61
GT11_1:RXCRCENABLE	22.19.64
GT11_1:RXCRCINVERTGEN	22.19.62
GT11_1:RXCRCSAMECLOCK	22.19.63
GT11_1:RXDACSEL	27.19.42
GT11_1:RXDACTST	27.19.36
GT11_1:RXDCCOUPLE	28.19.27
GT11_1:RXDIGRESET	28.19.16
GT11_1:RXDIGRX	27.19.62
GT11_1:RXDIVBUFPD	27.19.10
GT11_1:RXDIVBUFTST	27.19.2
GT11_1:RXDIVPD	27.19.13
GT11_1:RXDIVTST	27.19.5
GT11_1:RXFILTTST	27.19.6
GT11_1:RXLB	28.19.61
GT11_1:RXLKAPD	28.19.6
GT11_1:RXPD	28.19.1
GT11_1:RXPDDTST	28.19.11
GT11_1:RXPFDTST	27.19.4
GT11_1:RXPFDTX	27.19.61
GT11_1:RXQPPD	27.19.21
GT11_1:RXRCPPD	28.19.4
GT11_1:RXRECCLK1_USE_SYNC	22.19.76
GT11_1:RXRPDPD	28.19.3
GT11_1:RXRSDPD	28.19.5
GT11_1:RXSLOSEL	27.19.43
GT11_1:RXTADJ	28.19.28
GT11_1:RXVCOBUFPD	27.19.11
GT11_1:RXVCOBUFTST	27.19.3
GT11_1:RXVCOPD	27.19.15
GT11_1:RXVCOTST	27.19.1
GT11_1:RXVCO_CTRL_ENABLE	17.19.3
GT11_1:RX_BUFFER_USE	31.19.74
GT11_1:SAMPLE_8X	22.19.49
GT11_1:TEST_MODE_1	29.19.61
GT11_1:TEST_MODE_2	29.19.62
GT11_1:TEST_MODE_3	29.19.63
GT11_1:TXAREFBIASSEL	24.19.51
GT11_1:TXCFGENABLE	24.19.53
GT11_1:TXCLK0_FORCE_PMACLK	22.19.74
GT11_1:TXCLK0_INVERT_PMALEAF	22.19.8
GT11_1:TXCRCCLOCKDOUBLE	22.19.65
GT11_1:TXCRCENABLE	22.19.68
GT11_1:TXCRCINVERTGEN	22.19.66
GT11_1:TXCRCSAMECLOCK	22.19.67
GT11_1:TXDIGPD	24.19.65
GT11_1:TXHIGHSIGNALEN	24.19.52
GT11_1:TXLVLSHFTPD	24.19.72
GT11_1:TXOUTCLK1_USE_SYNC	22.19.75
GT11_1:TXPD	24.19.1
GT11_1:TXPHASESEL	10.19.5
GT11_1:TXPOST_TAP_PD	24.19.33
GT11_1:TXPRE_TAP_PD	24.19.68
GT11_1:TXSLEWRATE	24.19.45
GT11_1:TX_BUFFER_USE	31.19.75
GT11_1:VCO_CTRL_ENABLE	17.19.43
GT11_COMMON:ATBBUMPEN	10.19.13
GT11_COMMON:ATBENABLE	10.19.16
GT11_COMMON:BANDGAPSEL	10.19.36
GT11_COMMON:BIASRESSEL	10.19.29
GT11_COMMON:FWDCLK_OUT_ENABLE	18.19.16
GT11_COMMON:NATBENABLE	10.19.12
GT11_COMMON:PMABIASPD	10.19.21
GT11_COMMON:PMACOREPWRENABLE	10.19.1
GT11_COMMON:PMACTRL	10.19.3
GT11_COMMON:PMATUNE	10.19.56
GT11_COMMON:SYNCLK_ENABLE	10.19.2
GT11_COMMON:TXADCADJPD	21.19.14
GT11_COMMON:TXAPD	21.19.9
GT11_COMMON:TXAPTST	21.19.8
GT11_COMMON:TXBIASPD	21.19.12
GT11_COMMON:TXCMFPD	21.19.16
GT11_COMMON:TXCMFTST	21.19.7
GT11_COMMON:TXCPSEL	21.19.41
GT11_COMMON:TXDACSEL	21.19.42
GT11_COMMON:TXDACTST	21.19.36
GT11_COMMON:TXDIGRX	21.19.62
GT11_COMMON:TXDIVBUFPD	21.19.10
GT11_COMMON:TXDIVBUFTST	21.19.2
GT11_COMMON:TXDIVPD	21.19.13
GT11_COMMON:TXDIVTST	21.19.5
GT11_COMMON:TXFILTTST	21.19.6
GT11_COMMON:TXPFDTST	21.19.4
GT11_COMMON:TXPFDTX	21.19.61
GT11_COMMON:TXQPPD	21.19.21
GT11_COMMON:TXSLOSEL	21.19.43
GT11_COMMON:TXVCOBUFPD	21.19.11
GT11_COMMON:TXVCOBUFTST	21.19.3
GT11_COMMON:TXVCOPD	21.19.15
GT11_COMMON:TXVCOTST	21.19.1
GT11_COMMON:VREFSELECT	10.19.24
non-inverted	[0]

GT11_0:CHAN_BOND_LIMIT	15.19.65	15.19.64	15.19.63	15.19.62	15.19.61
GT11_0:RXLKADJ	5.19.25	5.19.24	5.19.23	5.19.22	5.19.21
GT11_0:TXDAT_TAP_DAC	12.19.25	12.19.24	12.19.23	12.19.22	12.19.21
GT11_0:TXPOST_TAP_DAC	12.19.32	12.19.31	12.19.30	12.19.29	12.19.28
GT11_0:TXPRE_TAP_DAC	12.19.67	12.19.66	12.19.56	12.19.55	12.19.54
GT11_1:CHAN_BOND_LIMIT	31.19.65	31.19.64	31.19.63	31.19.62	31.19.61
GT11_1:RXLKADJ	28.19.25	28.19.24	28.19.23	28.19.22	28.19.21
GT11_1:TXDAT_TAP_DAC	24.19.25	24.19.24	24.19.23	24.19.22	24.19.21
GT11_1:TXPOST_TAP_DAC	24.19.32	24.19.31	24.19.30	24.19.29	24.19.28
GT11_1:TXPRE_TAP_DAC	24.19.67	24.19.66	24.19.56	24.19.55	24.19.54
GT11_COMMON:PMAVBGCTRL	10.19.45	10.19.44	10.19.43	10.19.42	10.19.41
GT11_COMMON:RXAREGCTRL	10.19.50	10.19.49	10.19.48	10.19.47	10.19.46
GT11_COMMON:TXREGCTRL	10.19.55	10.19.54	10.19.53	10.19.52	10.19.51
non-inverted	[4]	[3]	[2]	[1]	[0]

GT11_0:CHAN_BOND_MODE	15.19.68	15.19.67
GT11_1:CHAN_BOND_MODE	31.19.68	31.19.67
NONE	0	0
MASTER	0	1
SLAVE_1_HOP	1	0
SLAVE_2_HOPS	1	1

GT11_0:CHAN_BOND_SEQ_1_1	15.19.11	15.19.10	15.19.9	15.19.8	15.19.7	15.19.6	15.19.5	15.19.4	15.19.3	15.19.2	15.19.1
GT11_0:CHAN_BOND_SEQ_1_2	15.19.26	15.19.25	15.19.24	15.19.23	15.19.22	15.19.21	15.19.16	15.19.15	15.19.14	15.19.13	15.19.12
GT11_0:CHAN_BOND_SEQ_1_3	15.19.41	15.19.36	15.19.35	15.19.34	15.19.33	15.19.32	15.19.31	15.19.30	15.19.29	15.19.28	15.19.27
GT11_0:CHAN_BOND_SEQ_1_4	15.19.52	15.19.51	15.19.50	15.19.49	15.19.48	15.19.47	15.19.46	15.19.45	15.19.44	15.19.43	15.19.42
GT11_0:CHAN_BOND_SEQ_2_1	13.19.11	13.19.10	13.19.9	13.19.8	13.19.7	13.19.6	13.19.5	13.19.4	13.19.3	13.19.2	13.19.1
GT11_0:CHAN_BOND_SEQ_2_2	13.19.26	13.19.25	13.19.24	13.19.23	13.19.22	13.19.21	13.19.16	13.19.15	13.19.14	13.19.13	13.19.12
GT11_0:CHAN_BOND_SEQ_2_3	13.19.41	13.19.36	13.19.35	13.19.34	13.19.33	13.19.32	13.19.31	13.19.30	13.19.29	13.19.28	13.19.27
GT11_0:CHAN_BOND_SEQ_2_4	13.19.52	13.19.51	13.19.50	13.19.49	13.19.48	13.19.47	13.19.46	13.19.45	13.19.44	13.19.43	13.19.42
GT11_0:CLK_COR_SEQ_1_1	9.19.11	9.19.10	9.19.9	9.19.8	9.19.7	9.19.6	9.19.5	9.19.4	9.19.3	9.19.2	9.19.1
GT11_0:CLK_COR_SEQ_1_2	9.19.26	9.19.25	9.19.24	9.19.23	9.19.22	9.19.21	9.19.16	9.19.15	9.19.14	9.19.13	9.19.12
GT11_0:CLK_COR_SEQ_1_3	9.19.41	9.19.36	9.19.35	9.19.34	9.19.33	9.19.32	9.19.31	9.19.30	9.19.29	9.19.28	9.19.27
GT11_0:CLK_COR_SEQ_1_4	9.19.52	9.19.51	9.19.50	9.19.49	9.19.48	9.19.47	9.19.46	9.19.45	9.19.44	9.19.43	9.19.42
GT11_0:CLK_COR_SEQ_2_1	7.19.11	7.19.10	7.19.9	7.19.8	7.19.7	7.19.6	7.19.5	7.19.4	7.19.3	7.19.2	7.19.1
GT11_0:CLK_COR_SEQ_2_2	7.19.26	7.19.25	7.19.24	7.19.23	7.19.22	7.19.21	7.19.16	7.19.15	7.19.14	7.19.13	7.19.12
GT11_0:CLK_COR_SEQ_2_3	7.19.41	7.19.36	7.19.35	7.19.34	7.19.33	7.19.32	7.19.31	7.19.30	7.19.29	7.19.28	7.19.27
GT11_0:CLK_COR_SEQ_2_4	7.19.52	7.19.51	7.19.50	7.19.49	7.19.48	7.19.47	7.19.46	7.19.45	7.19.44	7.19.43	7.19.42
GT11_1:CHAN_BOND_SEQ_1_1	31.19.11	31.19.10	31.19.9	31.19.8	31.19.7	31.19.6	31.19.5	31.19.4	31.19.3	31.19.2	31.19.1
GT11_1:CHAN_BOND_SEQ_1_2	31.19.26	31.19.25	31.19.24	31.19.23	31.19.22	31.19.21	31.19.16	31.19.15	31.19.14	31.19.13	31.19.12
GT11_1:CHAN_BOND_SEQ_1_3	31.19.41	31.19.36	31.19.35	31.19.34	31.19.33	31.19.32	31.19.31	31.19.30	31.19.29	31.19.28	31.19.27
GT11_1:CHAN_BOND_SEQ_1_4	31.19.52	31.19.51	31.19.50	31.19.49	31.19.48	31.19.47	31.19.46	31.19.45	31.19.44	31.19.43	31.19.42
GT11_1:CHAN_BOND_SEQ_2_1	29.19.11	29.19.10	29.19.9	29.19.8	29.19.7	29.19.6	29.19.5	29.19.4	29.19.3	29.19.2	29.19.1
GT11_1:CHAN_BOND_SEQ_2_2	29.19.26	29.19.25	29.19.24	29.19.23	29.19.22	29.19.21	29.19.16	29.19.15	29.19.14	29.19.13	29.19.12
GT11_1:CHAN_BOND_SEQ_2_3	29.19.41	29.19.36	29.19.35	29.19.34	29.19.33	29.19.32	29.19.31	29.19.30	29.19.29	29.19.28	29.19.27
GT11_1:CHAN_BOND_SEQ_2_4	29.19.52	29.19.51	29.19.50	29.19.49	29.19.48	29.19.47	29.19.46	29.19.45	29.19.44	29.19.43	29.19.42
GT11_1:CLK_COR_SEQ_1_1	25.19.11	25.19.10	25.19.9	25.19.8	25.19.7	25.19.6	25.19.5	25.19.4	25.19.3	25.19.2	25.19.1
GT11_1:CLK_COR_SEQ_1_2	25.19.26	25.19.25	25.19.24	25.19.23	25.19.22	25.19.21	25.19.16	25.19.15	25.19.14	25.19.13	25.19.12
GT11_1:CLK_COR_SEQ_1_3	25.19.41	25.19.36	25.19.35	25.19.34	25.19.33	25.19.32	25.19.31	25.19.30	25.19.29	25.19.28	25.19.27
GT11_1:CLK_COR_SEQ_1_4	25.19.52	25.19.51	25.19.50	25.19.49	25.19.48	25.19.47	25.19.46	25.19.45	25.19.44	25.19.43	25.19.42
GT11_1:CLK_COR_SEQ_2_1	23.19.11	23.19.10	23.19.9	23.19.8	23.19.7	23.19.6	23.19.5	23.19.4	23.19.3	23.19.2	23.19.1
GT11_1:CLK_COR_SEQ_2_2	23.19.26	23.19.25	23.19.24	23.19.23	23.19.22	23.19.21	23.19.16	23.19.15	23.19.14	23.19.13	23.19.12
GT11_1:CLK_COR_SEQ_2_3	23.19.41	23.19.36	23.19.35	23.19.34	23.19.33	23.19.32	23.19.31	23.19.30	23.19.29	23.19.28	23.19.27
GT11_1:CLK_COR_SEQ_2_4	23.19.52	23.19.51	23.19.50	23.19.49	23.19.48	23.19.47	23.19.46	23.19.45	23.19.44	23.19.43	23.19.42
non-inverted	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:CHAN_BOND_SEQ_1_MASK	15.19.56	15.19.55	15.19.54	15.19.53
GT11_0:CHAN_BOND_SEQ_2_MASK	13.19.56	13.19.55	13.19.54	13.19.53
GT11_0:CLK_COR_SEQ_1_MASK	9.19.56	9.19.55	9.19.54	9.19.53
GT11_0:CLK_COR_SEQ_2_MASK	7.19.56	7.19.55	7.19.54	7.19.53
GT11_0:RXLOOPFILT	2.19.66	2.19.65	2.19.64	2.19.63
GT11_0:TXCLKMODE	12.19.64	12.19.63	12.19.62	12.19.61
GT11_0:TXLNDR_TST1	12.19.76	12.19.75	12.19.74	12.19.73
GT11_0:TXTERMTRIM	12.19.50	12.19.49	12.19.48	12.19.47
GT11_1:CHAN_BOND_SEQ_1_MASK	31.19.56	31.19.55	31.19.54	31.19.53
GT11_1:CHAN_BOND_SEQ_2_MASK	29.19.56	29.19.55	29.19.54	29.19.53
GT11_1:CLK_COR_SEQ_1_MASK	25.19.56	25.19.55	25.19.54	25.19.53
GT11_1:CLK_COR_SEQ_2_MASK	23.19.56	23.19.55	23.19.54	23.19.53
GT11_1:RXLOOPFILT	27.19.66	27.19.65	27.19.64	27.19.63
GT11_1:TXCLKMODE	24.19.64	24.19.63	24.19.62	24.19.61
GT11_1:TXLNDR_TST1	24.19.76	24.19.75	24.19.74	24.19.73
GT11_1:TXTERMTRIM	24.19.50	24.19.49	24.19.48	24.19.47
GT11_COMMON:PMAIREFTRIM	10.19.35	10.19.34	10.19.33	10.19.32
GT11_COMMON:PMAVREFTRIM	10.19.28	10.19.27	10.19.26	10.19.25
GT11_COMMON:TXLOOPFILT	21.19.66	21.19.65	21.19.64	21.19.63
non-inverted	[3]	[2]	[1]	[0]

GT11_0:CHAN_BOND_SEQ_LEN	15.19.73	15.19.72	15.19.71
GT11_0:CLK_COR_SEQ_LEN	6.19.13	6.19.12	6.19.11
GT11_1:CHAN_BOND_SEQ_LEN	31.19.73	31.19.72	31.19.71
GT11_1:CLK_COR_SEQ_LEN	22.19.13	22.19.12	22.19.11
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
8	1	1	1

GT11_0:CHAN_BOND_TUNE	13.19.76	13.19.75	13.19.74	13.19.73	13.19.72	13.19.71	13.19.70	13.19.69
GT11_0:SH_CNT_MAX	6.19.28	6.19.27	6.19.26	6.19.25	6.19.24	6.19.23	6.19.22	6.19.21
GT11_0:SH_INVALID_CNT_MAX	6.19.36	6.19.35	6.19.34	6.19.33	6.19.32	6.19.31	6.19.30	6.19.29
GT11_1:CHAN_BOND_TUNE	29.19.76	29.19.75	29.19.74	29.19.73	29.19.72	29.19.71	29.19.70	29.19.69
GT11_1:SH_CNT_MAX	22.19.28	22.19.27	22.19.26	22.19.25	22.19.24	22.19.23	22.19.22	22.19.21
GT11_1:SH_INVALID_CNT_MAX	22.19.36	22.19.35	22.19.34	22.19.33	22.19.32	22.19.31	22.19.30	22.19.29
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:CLK_COR_MAX_LAT	6.19.6	6.19.5	6.19.4	6.19.3	6.19.2	6.19.1
GT11_0:CLK_COR_MIN_LAT	9.19.71	9.19.70	9.19.69	9.19.68	9.19.67	9.19.66
GT11_0:RXCDRLOS	5.19.34	5.19.33	5.19.32	5.19.31	5.19.30	5.19.29
GT11_0:RXCLKMODE	5.19.67	5.19.66	5.19.65	5.19.64	5.19.63	5.19.62
GT11_0:RXMODE	5.19.76	5.19.75	5.19.74	5.19.73	5.19.72	5.19.71
GT11_1:CLK_COR_MAX_LAT	22.19.6	22.19.5	22.19.4	22.19.3	22.19.2	22.19.1
GT11_1:CLK_COR_MIN_LAT	25.19.71	25.19.70	25.19.69	25.19.68	25.19.67	25.19.66
GT11_1:RXCDRLOS	28.19.34	28.19.33	28.19.32	28.19.31	28.19.30	28.19.29
GT11_1:RXCLKMODE	28.19.67	28.19.66	28.19.65	28.19.64	28.19.63	28.19.62
GT11_1:RXMODE	28.19.76	28.19.75	28.19.74	28.19.73	28.19.72	28.19.71
non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:COMMA_10B_MASK	4.19.50	4.19.49	4.19.48	4.19.47	4.19.46	4.19.45	4.19.44	4.19.43	4.19.42	4.19.41
GT11_0:RXCTRL1	2.19.31	2.19.30	2.19.29	2.19.28	2.19.27	2.19.26	2.19.25	2.19.24	2.19.23	2.19.22
GT11_0:RXVCODAC_INIT	1.19.35	1.19.34	1.19.33	1.19.32	1.19.31	1.19.30	1.19.29	1.19.28	1.19.27	1.19.26
GT11_0:VCODAC_INIT	1.19.75	1.19.74	1.19.73	1.19.72	1.19.71	1.19.70	1.19.69	1.19.68	1.19.67	1.19.66
GT11_1:COMMA_10B_MASK	20.19.50	20.19.49	20.19.48	20.19.47	20.19.46	20.19.45	20.19.44	20.19.43	20.19.42	20.19.41
GT11_1:RXCTRL1	27.19.31	27.19.30	27.19.29	27.19.28	27.19.27	27.19.26	27.19.25	27.19.24	27.19.23	27.19.22
GT11_1:RXVCODAC_INIT	17.19.35	17.19.34	17.19.33	17.19.32	17.19.31	17.19.30	17.19.29	17.19.28	17.19.27	17.19.26
GT11_1:VCODAC_INIT	17.19.75	17.19.74	17.19.73	17.19.72	17.19.71	17.19.70	17.19.69	17.19.68	17.19.67	17.19.66
GT11_COMMON:TXCTRL1	21.19.31	21.19.30	21.19.29	21.19.28	21.19.27	21.19.26	21.19.25	21.19.24	21.19.23	21.19.22
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:CYCLE_LIMIT_SEL	1.19.42	1.19.41
GT11_0:DIGRX_FWDCLK	9.19.62	9.19.61
GT11_0:LOOPCAL_WAIT	1.19.62	1.19.61
GT11_0:RXASYNCDIVIDE	5.19.69	5.19.68
GT11_0:RXCLMODE	2.19.68	2.19.67
GT11_0:RXCMADJ	5.19.36	5.19.35
GT11_0:RXCYCLE_LIMIT_SEL	1.19.2	1.19.1
GT11_0:RXDATA_SEL	9.19.76	9.19.75
GT11_0:RXFECONTROL1	5.19.8	5.19.7
GT11_0:RXFETUNE	5.19.56	5.19.55
GT11_0:RXLOOPCAL_WAIT	1.19.22	1.19.21
GT11_0:RXRIBADJ	5.19.51	5.19.50
GT11_0:RXSLOWDOWN_CAL	1.19.25	1.19.24
GT11_0:RX_CLOCK_DIVIDER	6.19.70	6.19.69
GT11_0:SLOWDOWN_CAL	1.19.65	1.19.64
GT11_0:TXASYNCDIVIDE	12.19.46	12.19.34
GT11_0:TXDATA_SEL	9.19.74	9.19.73
GT11_0:TXLNDR_TST2	12.19.27	12.19.26
GT11_0:TX_CLOCK_DIVIDER	6.19.72	6.19.71
GT11_1:CYCLE_LIMIT_SEL	17.19.42	17.19.41
GT11_1:DIGRX_FWDCLK	25.19.62	25.19.61
GT11_1:LOOPCAL_WAIT	17.19.62	17.19.61
GT11_1:RXASYNCDIVIDE	28.19.69	28.19.68
GT11_1:RXCLMODE	27.19.68	27.19.67
GT11_1:RXCMADJ	28.19.36	28.19.35
GT11_1:RXCYCLE_LIMIT_SEL	17.19.2	17.19.1
GT11_1:RXDATA_SEL	25.19.76	25.19.75
GT11_1:RXFECONTROL1	28.19.8	28.19.7
GT11_1:RXFETUNE	28.19.56	28.19.55
GT11_1:RXLOOPCAL_WAIT	17.19.22	17.19.21
GT11_1:RXRIBADJ	28.19.51	28.19.50
GT11_1:RXSLOWDOWN_CAL	17.19.25	17.19.24
GT11_1:RX_CLOCK_DIVIDER	22.19.70	22.19.69
GT11_1:SLOWDOWN_CAL	17.19.65	17.19.64
GT11_1:TXASYNCDIVIDE	24.19.46	24.19.34
GT11_1:TXDATA_SEL	25.19.74	25.19.73
GT11_1:TXLNDR_TST2	24.19.27	24.19.26
GT11_1:TX_CLOCK_DIVIDER	22.19.72	22.19.71
GT11_COMMON:IREFBIASMODE	10.19.31	10.19.30
GT11_COMMON:TXCLMODE	21.19.68	21.19.67
GT11_COMMON:VREFBIASMODE	10.19.23	10.19.22
non-inverted	[1]	[0]

GT11_0:DCDR_FILTER	6.19.48	6.19.47	6.19.46
GT11_0:FDET_HYS_CAL	1.19.55	1.19.54	1.19.53
GT11_0:FDET_HYS_SEL	1.19.49	1.19.48	1.19.47
GT11_0:FDET_LCK_CAL	1.19.52	1.19.51	1.19.50
GT11_0:FDET_LCK_SEL	1.19.46	1.19.45	1.19.44
GT11_0:RXFDET_HYS_CAL	1.19.15	1.19.14	1.19.13
GT11_0:RXFDET_HYS_SEL	1.19.9	1.19.8	1.19.7
GT11_0:RXFDET_LCK_CAL	1.19.12	1.19.11	1.19.10
GT11_0:RXFDET_LCK_SEL	1.19.6	1.19.5	1.19.4
GT11_0:RXFECONTROL2	5.19.15	5.19.14	5.19.13
GT11_0:RXRCPADJ	5.19.54	5.19.53	5.19.52
GT11_0:TXDAT_PRDRV_DAC	12.19.41	12.19.36	12.19.35
GT11_0:TXPOST_PRDRV_DAC	12.19.44	12.19.43	12.19.42
GT11_0:TXPRE_PRDRV_DAC	12.19.71	12.19.70	12.19.69
GT11_1:DCDR_FILTER	22.19.48	22.19.47	22.19.46
GT11_1:FDET_HYS_CAL	17.19.55	17.19.54	17.19.53
GT11_1:FDET_HYS_SEL	17.19.49	17.19.48	17.19.47
GT11_1:FDET_LCK_CAL	17.19.52	17.19.51	17.19.50
GT11_1:FDET_LCK_SEL	17.19.46	17.19.45	17.19.44
GT11_1:RXFDET_HYS_CAL	17.19.15	17.19.14	17.19.13
GT11_1:RXFDET_HYS_SEL	17.19.9	17.19.8	17.19.7
GT11_1:RXFDET_LCK_CAL	17.19.12	17.19.11	17.19.10
GT11_1:RXFDET_LCK_SEL	17.19.6	17.19.5	17.19.4
GT11_1:RXFECONTROL2	28.19.15	28.19.14	28.19.13
GT11_1:RXRCPADJ	28.19.54	28.19.53	28.19.52
GT11_1:TXDAT_PRDRV_DAC	24.19.41	24.19.36	24.19.35
GT11_1:TXPOST_PRDRV_DAC	24.19.44	24.19.43	24.19.42
GT11_1:TXPRE_PRDRV_DAC	24.19.71	24.19.70	24.19.69
non-inverted	[2]	[1]	[0]

GT11_0:DRP40	0.19.16	0.19.15	0.19.14	0.19.13	0.19.12	0.19.11	0.19.10	0.19.9	0.19.8	0.19.7	0.19.6	0.19.5	0.19.4	0.19.3	0.19.2	0.19.1
GT11_0:DRP41	2.19.16	2.19.15	2.19.14	2.19.13	2.19.12	2.19.11	2.19.10	2.19.9	2.19.8	2.19.7	2.19.6	2.19.5	2.19.4	2.19.3	2.19.2	2.19.1
GT11_0:DRP42	4.19.16	4.19.15	4.19.14	4.19.13	4.19.12	4.19.11	4.19.10	4.19.9	4.19.8	4.19.7	4.19.6	4.19.5	4.19.4	4.19.3	4.19.2	4.19.1
GT11_0:DRP43	6.19.16	6.19.15	6.19.14	6.19.13	6.19.12	6.19.11	6.19.10	6.19.9	6.19.8	6.19.7	6.19.6	6.19.5	6.19.4	6.19.3	6.19.2	6.19.1
GT11_0:DRP44	8.19.16	8.19.15	8.19.14	8.19.13	8.19.12	8.19.11	8.19.10	8.19.9	8.19.8	8.19.7	8.19.6	8.19.5	8.19.4	8.19.3	8.19.2	8.19.1
GT11_0:DRP45	10.19.16	10.19.15	10.19.14	10.19.13	10.19.12	10.19.11	10.19.10	10.19.9	10.19.8	10.19.7	10.19.6	10.19.5	10.19.4	10.19.3	10.19.2	10.19.1
GT11_0:DRP46	12.19.16	12.19.15	12.19.14	12.19.13	12.19.12	12.19.11	12.19.10	12.19.9	12.19.8	12.19.7	12.19.6	12.19.5	12.19.4	12.19.3	12.19.2	12.19.1
GT11_0:DRP47	14.19.16	14.19.15	14.19.14	14.19.13	14.19.12	14.19.11	14.19.10	14.19.9	14.19.8	14.19.7	14.19.6	14.19.5	14.19.4	14.19.3	14.19.2	14.19.1
GT11_0:DRP48	0.19.36	0.19.35	0.19.34	0.19.33	0.19.32	0.19.31	0.19.30	0.19.29	0.19.28	0.19.27	0.19.26	0.19.25	0.19.24	0.19.23	0.19.22	0.19.21
GT11_0:DRP49	2.19.36	2.19.35	2.19.34	2.19.33	2.19.32	2.19.31	2.19.30	2.19.29	2.19.28	2.19.27	2.19.26	2.19.25	2.19.24	2.19.23	2.19.22	2.19.21
GT11_0:DRP4A	4.19.36	4.19.35	4.19.34	4.19.33	4.19.32	4.19.31	4.19.30	4.19.29	4.19.28	4.19.27	4.19.26	4.19.25	4.19.24	4.19.23	4.19.22	4.19.21
GT11_0:DRP4B	6.19.36	6.19.35	6.19.34	6.19.33	6.19.32	6.19.31	6.19.30	6.19.29	6.19.28	6.19.27	6.19.26	6.19.25	6.19.24	6.19.23	6.19.22	6.19.21
GT11_0:DRP4C	8.19.36	8.19.35	8.19.34	8.19.33	8.19.32	8.19.31	8.19.30	8.19.29	8.19.28	8.19.27	8.19.26	8.19.25	8.19.24	8.19.23	8.19.22	8.19.21
GT11_0:DRP4D	10.19.36	10.19.35	10.19.34	10.19.33	10.19.32	10.19.31	10.19.30	10.19.29	10.19.28	10.19.27	10.19.26	10.19.25	10.19.24	10.19.23	10.19.22	10.19.21
GT11_0:DRP4E	12.19.36	12.19.35	12.19.34	12.19.33	12.19.32	12.19.31	12.19.30	12.19.29	12.19.28	12.19.27	12.19.26	12.19.25	12.19.24	12.19.23	12.19.22	12.19.21
GT11_0:DRP4F	14.19.36	14.19.35	14.19.34	14.19.33	14.19.32	14.19.31	14.19.30	14.19.29	14.19.28	14.19.27	14.19.26	14.19.25	14.19.24	14.19.23	14.19.22	14.19.21
GT11_0:DRP50	0.19.56	0.19.55	0.19.54	0.19.53	0.19.52	0.19.51	0.19.50	0.19.49	0.19.48	0.19.47	0.19.46	0.19.45	0.19.44	0.19.43	0.19.42	0.19.41
GT11_0:DRP51	2.19.56	2.19.55	2.19.54	2.19.53	2.19.52	2.19.51	2.19.50	2.19.49	2.19.48	2.19.47	2.19.46	2.19.45	2.19.44	2.19.43	2.19.42	2.19.41
GT11_0:DRP52	4.19.56	4.19.55	4.19.54	4.19.53	4.19.52	4.19.51	4.19.50	4.19.49	4.19.48	4.19.47	4.19.46	4.19.45	4.19.44	4.19.43	4.19.42	4.19.41
GT11_0:DRP53	6.19.56	6.19.55	6.19.54	6.19.53	6.19.52	6.19.51	6.19.50	6.19.49	6.19.48	6.19.47	6.19.46	6.19.45	6.19.44	6.19.43	6.19.42	6.19.41
GT11_0:DRP54	8.19.56	8.19.55	8.19.54	8.19.53	8.19.52	8.19.51	8.19.50	8.19.49	8.19.48	8.19.47	8.19.46	8.19.45	8.19.44	8.19.43	8.19.42	8.19.41
GT11_0:DRP55	10.19.56	10.19.55	10.19.54	10.19.53	10.19.52	10.19.51	10.19.50	10.19.49	10.19.48	10.19.47	10.19.46	10.19.45	10.19.44	10.19.43	10.19.42	10.19.41
GT11_0:DRP56	12.19.56	12.19.55	12.19.54	12.19.53	12.19.52	12.19.51	12.19.50	12.19.49	12.19.48	12.19.47	12.19.46	12.19.45	12.19.44	12.19.43	12.19.42	12.19.41
GT11_0:DRP57	14.19.56	14.19.55	14.19.54	14.19.53	14.19.52	14.19.51	14.19.50	14.19.49	14.19.48	14.19.47	14.19.46	14.19.45	14.19.44	14.19.43	14.19.42	14.19.41
GT11_0:DRP58	0.19.76	0.19.75	0.19.74	0.19.73	0.19.72	0.19.71	0.19.70	0.19.69	0.19.68	0.19.67	0.19.66	0.19.65	0.19.64	0.19.63	0.19.62	0.19.61
GT11_0:DRP59	2.19.76	2.19.75	2.19.74	2.19.73	2.19.72	2.19.71	2.19.70	2.19.69	2.19.68	2.19.67	2.19.66	2.19.65	2.19.64	2.19.63	2.19.62	2.19.61
GT11_0:DRP5A	4.19.76	4.19.75	4.19.74	4.19.73	4.19.72	4.19.71	4.19.70	4.19.69	4.19.68	4.19.67	4.19.66	4.19.65	4.19.64	4.19.63	4.19.62	4.19.61
GT11_0:DRP5B	6.19.76	6.19.75	6.19.74	6.19.73	6.19.72	6.19.71	6.19.70	6.19.69	6.19.68	6.19.67	6.19.66	6.19.65	6.19.64	6.19.63	6.19.62	6.19.61
GT11_0:DRP5C	8.19.76	8.19.75	8.19.74	8.19.73	8.19.72	8.19.71	8.19.70	8.19.69	8.19.68	8.19.67	8.19.66	8.19.65	8.19.64	8.19.63	8.19.62	8.19.61
GT11_0:DRP5D	10.19.76	10.19.75	10.19.74	10.19.73	10.19.72	10.19.71	10.19.70	10.19.69	10.19.68	10.19.67	10.19.66	10.19.65	10.19.64	10.19.63	10.19.62	10.19.61
GT11_0:DRP5E	12.19.76	12.19.75	12.19.74	12.19.73	12.19.72	12.19.71	12.19.70	12.19.69	12.19.68	12.19.67	12.19.66	12.19.65	12.19.64	12.19.63	12.19.62	12.19.61
GT11_0:DRP5F	14.19.76	14.19.75	14.19.74	14.19.73	14.19.72	14.19.71	14.19.70	14.19.69	14.19.68	14.19.67	14.19.66	14.19.65	14.19.64	14.19.63	14.19.62	14.19.61
GT11_0:DRP60	1.19.16	1.19.15	1.19.14	1.19.13	1.19.12	1.19.11	1.19.10	1.19.9	1.19.8	1.19.7	1.19.6	1.19.5	1.19.4	1.19.3	1.19.2	1.19.1
GT11_0:DRP61	3.19.16	3.19.15	3.19.14	3.19.13	3.19.12	3.19.11	3.19.10	3.19.9	3.19.8	3.19.7	3.19.6	3.19.5	3.19.4	3.19.3	3.19.2	3.19.1
GT11_0:DRP62	5.19.16	5.19.15	5.19.14	5.19.13	5.19.12	5.19.11	5.19.10	5.19.9	5.19.8	5.19.7	5.19.6	5.19.5	5.19.4	5.19.3	5.19.2	5.19.1
GT11_0:DRP63	7.19.16	7.19.15	7.19.14	7.19.13	7.19.12	7.19.11	7.19.10	7.19.9	7.19.8	7.19.7	7.19.6	7.19.5	7.19.4	7.19.3	7.19.2	7.19.1
GT11_0:DRP64	9.19.16	9.19.15	9.19.14	9.19.13	9.19.12	9.19.11	9.19.10	9.19.9	9.19.8	9.19.7	9.19.6	9.19.5	9.19.4	9.19.3	9.19.2	9.19.1
GT11_0:DRP65	11.19.16	11.19.15	11.19.14	11.19.13	11.19.12	11.19.11	11.19.10	11.19.9	11.19.8	11.19.7	11.19.6	11.19.5	11.19.4	11.19.3	11.19.2	11.19.1
GT11_0:DRP66	13.19.16	13.19.15	13.19.14	13.19.13	13.19.12	13.19.11	13.19.10	13.19.9	13.19.8	13.19.7	13.19.6	13.19.5	13.19.4	13.19.3	13.19.2	13.19.1
GT11_0:DRP67	15.19.16	15.19.15	15.19.14	15.19.13	15.19.12	15.19.11	15.19.10	15.19.9	15.19.8	15.19.7	15.19.6	15.19.5	15.19.4	15.19.3	15.19.2	15.19.1
GT11_0:DRP68	1.19.36	1.19.35	1.19.34	1.19.33	1.19.32	1.19.31	1.19.30	1.19.29	1.19.28	1.19.27	1.19.26	1.19.25	1.19.24	1.19.23	1.19.22	1.19.21
GT11_0:DRP69	3.19.36	3.19.35	3.19.34	3.19.33	3.19.32	3.19.31	3.19.30	3.19.29	3.19.28	3.19.27	3.19.26	3.19.25	3.19.24	3.19.23	3.19.22	3.19.21
GT11_0:DRP6A	5.19.36	5.19.35	5.19.34	5.19.33	5.19.32	5.19.31	5.19.30	5.19.29	5.19.28	5.19.27	5.19.26	5.19.25	5.19.24	5.19.23	5.19.22	5.19.21
GT11_0:DRP6B	7.19.36	7.19.35	7.19.34	7.19.33	7.19.32	7.19.31	7.19.30	7.19.29	7.19.28	7.19.27	7.19.26	7.19.25	7.19.24	7.19.23	7.19.22	7.19.21
GT11_0:DRP6C	9.19.36	9.19.35	9.19.34	9.19.33	9.19.32	9.19.31	9.19.30	9.19.29	9.19.28	9.19.27	9.19.26	9.19.25	9.19.24	9.19.23	9.19.22	9.19.21
GT11_0:DRP6D	11.19.36	11.19.35	11.19.34	11.19.33	11.19.32	11.19.31	11.19.30	11.19.29	11.19.28	11.19.27	11.19.26	11.19.25	11.19.24	11.19.23	11.19.22	11.19.21
GT11_0:DRP6E	13.19.36	13.19.35	13.19.34	13.19.33	13.19.32	13.19.31	13.19.30	13.19.29	13.19.28	13.19.27	13.19.26	13.19.25	13.19.24	13.19.23	13.19.22	13.19.21
GT11_0:DRP6F	15.19.36	15.19.35	15.19.34	15.19.33	15.19.32	15.19.31	15.19.30	15.19.29	15.19.28	15.19.27	15.19.26	15.19.25	15.19.24	15.19.23	15.19.22	15.19.21
GT11_0:DRP70	1.19.56	1.19.55	1.19.54	1.19.53	1.19.52	1.19.51	1.19.50	1.19.49	1.19.48	1.19.47	1.19.46	1.19.45	1.19.44	1.19.43	1.19.42	1.19.41
GT11_0:DRP71	3.19.56	3.19.55	3.19.54	3.19.53	3.19.52	3.19.51	3.19.50	3.19.49	3.19.48	3.19.47	3.19.46	3.19.45	3.19.44	3.19.43	3.19.42	3.19.41
GT11_0:DRP72	5.19.56	5.19.55	5.19.54	5.19.53	5.19.52	5.19.51	5.19.50	5.19.49	5.19.48	5.19.47	5.19.46	5.19.45	5.19.44	5.19.43	5.19.42	5.19.41
GT11_0:DRP73	7.19.56	7.19.55	7.19.54	7.19.53	7.19.52	7.19.51	7.19.50	7.19.49	7.19.48	7.19.47	7.19.46	7.19.45	7.19.44	7.19.43	7.19.42	7.19.41
GT11_0:DRP74	9.19.56	9.19.55	9.19.54	9.19.53	9.19.52	9.19.51	9.19.50	9.19.49	9.19.48	9.19.47	9.19.46	9.19.45	9.19.44	9.19.43	9.19.42	9.19.41
GT11_0:DRP75	11.19.56	11.19.55	11.19.54	11.19.53	11.19.52	11.19.51	11.19.50	11.19.49	11.19.48	11.19.47	11.19.46	11.19.45	11.19.44	11.19.43	11.19.42	11.19.41
GT11_0:DRP76	13.19.56	13.19.55	13.19.54	13.19.53	13.19.52	13.19.51	13.19.50	13.19.49	13.19.48	13.19.47	13.19.46	13.19.45	13.19.44	13.19.43	13.19.42	13.19.41
GT11_0:DRP77	15.19.56	15.19.55	15.19.54	15.19.53	15.19.52	15.19.51	15.19.50	15.19.49	15.19.48	15.19.47	15.19.46	15.19.45	15.19.44	15.19.43	15.19.42	15.19.41
GT11_0:DRP78	1.19.76	1.19.75	1.19.74	1.19.73	1.19.72	1.19.71	1.19.70	1.19.69	1.19.68	1.19.67	1.19.66	1.19.65	1.19.64	1.19.63	1.19.62	1.19.61
GT11_0:DRP79	3.19.76	3.19.75	3.19.74	3.19.73	3.19.72	3.19.71	3.19.70	3.19.69	3.19.68	3.19.67	3.19.66	3.19.65	3.19.64	3.19.63	3.19.62	3.19.61
GT11_0:DRP7A	5.19.76	5.19.75	5.19.74	5.19.73	5.19.72	5.19.71	5.19.70	5.19.69	5.19.68	5.19.67	5.19.66	5.19.65	5.19.64	5.19.63	5.19.62	5.19.61
GT11_0:DRP7B	7.19.76	7.19.75	7.19.74	7.19.73	7.19.72	7.19.71	7.19.70	7.19.69	7.19.68	7.19.67	7.19.66	7.19.65	7.19.64	7.19.63	7.19.62	7.19.61
GT11_0:DRP7C	9.19.76	9.19.75	9.19.74	9.19.73	9.19.72	9.19.71	9.19.70	9.19.69	9.19.68	9.19.67	9.19.66	9.19.65	9.19.64	9.19.63	9.19.62	9.19.61
GT11_0:DRP7D	11.19.76	11.19.75	11.19.74	11.19.73	11.19.72	11.19.71	11.19.70	11.19.69	11.19.68	11.19.67	11.19.66	11.19.65	11.19.64	11.19.63	11.19.62	11.19.61
GT11_0:DRP7E	13.19.76	13.19.75	13.19.74	13.19.73	13.19.72	13.19.71	13.19.70	13.19.69	13.19.68	13.19.67	13.19.66	13.19.65	13.19.64	13.19.63	13.19.62	13.19.61
GT11_0:DRP7F	15.19.76	15.19.75	15.19.74	15.19.73	15.19.72	15.19.71	15.19.70	15.19.69	15.19.68	15.19.67	15.19.66	15.19.65	15.19.64	15.19.63	15.19.62	15.19.61
GT11_1:DRP40	16.19.16	16.19.15	16.19.14	16.19.13	16.19.12	16.19.11	16.19.10	16.19.9	16.19.8	16.19.7	16.19.6	16.19.5	16.19.4	16.19.3	16.19.2	16.19.1
GT11_1:DRP41	18.19.16	18.19.15	18.19.14	18.19.13	18.19.12	18.19.11	18.19.10	18.19.9	18.19.8	18.19.7	18.19.6	18.19.5	18.19.4	18.19.3	18.19.2	18.19.1
GT11_1:DRP42	20.19.16	20.19.15	20.19.14	20.19.13	20.19.12	20.19.11	20.19.10	20.19.9	20.19.8	20.19.7	20.19.6	20.19.5	20.19.4	20.19.3	20.19.2	20.19.1
GT11_1:DRP43	22.19.16	22.19.15	22.19.14	22.19.13	22.19.12	22.19.11	22.19.10	22.19.9	22.19.8	22.19.7	22.19.6	22.19.5	22.19.4	22.19.3	22.19.2	22.19.1
GT11_1:DRP44	24.19.16	24.19.15	24.19.14	24.19.13	24.19.12	24.19.11	24.19.10	24.19.9	24.19.8	24.19.7	24.19.6	24.19.5	24.19.4	24.19.3	24.19.2	24.19.1
GT11_1:DRP45	26.19.16	26.19.15	26.19.14	26.19.13	26.19.12	26.19.11	26.19.10	26.19.9	26.19.8	26.19.7	26.19.6	26.19.5	26.19.4	26.19.3	26.19.2	26.19.1
GT11_1:DRP46	28.19.16	28.19.15	28.19.14	28.19.13	28.19.12	28.19.11	28.19.10	28.19.9	28.19.8	28.19.7	28.19.6	28.19.5	28.19.4	28.19.3	28.19.2	28.19.1
GT11_1:DRP47	30.19.16	30.19.15	30.19.14	30.19.13	30.19.12	30.19.11	30.19.10	30.19.9	30.19.8	30.19.7	30.19.6	30.19.5	30.19.4	30.19.3	30.19.2	30.19.1
GT11_1:DRP48	16.19.36	16.19.35	16.19.34	16.19.33	16.19.32	16.19.31	16.19.30	16.19.29	16.19.28	16.19.27	16.19.26	16.19.25	16.19.24	16.19.23	16.19.22	16.19.21
GT11_1:DRP49	18.19.36	18.19.35	18.19.34	18.19.33	18.19.32	18.19.31	18.19.30	18.19.29	18.19.28	18.19.27	18.19.26	18.19.25	18.19.24	18.19.23	18.19.22	18.19.21
GT11_1:DRP4A	20.19.36	20.19.35	20.19.34	20.19.33	20.19.32	20.19.31	20.19.30	20.19.29	20.19.28	20.19.27	20.19.26	20.19.25	20.19.24	20.19.23	20.19.22	20.19.21
GT11_1:DRP4B	22.19.36	22.19.35	22.19.34	22.19.33	22.19.32	22.19.31	22.19.30	22.19.29	22.19.28	22.19.27	22.19.26	22.19.25	22.19.24	22.19.23	22.19.22	22.19.21
GT11_1:DRP4C	24.19.36	24.19.35	24.19.34	24.19.33	24.19.32	24.19.31	24.19.30	24.19.29	24.19.28	24.19.27	24.19.26	24.19.25	24.19.24	24.19.23	24.19.22	24.19.21
GT11_1:DRP4D	26.19.36	26.19.35	26.19.34	26.19.33	26.19.32	26.19.31	26.19.30	26.19.29	26.19.28	26.19.27	26.19.26	26.19.25	26.19.24	26.19.23	26.19.22	26.19.21
GT11_1:DRP4E	28.19.36	28.19.35	28.19.34	28.19.33	28.19.32	28.19.31	28.19.30	28.19.29	28.19.28	28.19.27	28.19.26	28.19.25	28.19.24	28.19.23	28.19.22	28.19.21
GT11_1:DRP4F	30.19.36	30.19.35	30.19.34	30.19.33	30.19.32	30.19.31	30.19.30	30.19.29	30.19.28	30.19.27	30.19.26	30.19.25	30.19.24	30.19.23	30.19.22	30.19.21
GT11_1:DRP50	16.19.56	16.19.55	16.19.54	16.19.53	16.19.52	16.19.51	16.19.50	16.19.49	16.19.48	16.19.47	16.19.46	16.19.45	16.19.44	16.19.43	16.19.42	16.19.41
GT11_1:DRP51	18.19.56	18.19.55	18.19.54	18.19.53	18.19.52	18.19.51	18.19.50	18.19.49	18.19.48	18.19.47	18.19.46	18.19.45	18.19.44	18.19.43	18.19.42	18.19.41
GT11_1:DRP52	20.19.56	20.19.55	20.19.54	20.19.53	20.19.52	20.19.51	20.19.50	20.19.49	20.19.48	20.19.47	20.19.46	20.19.45	20.19.44	20.19.43	20.19.42	20.19.41
GT11_1:DRP53	22.19.56	22.19.55	22.19.54	22.19.53	22.19.52	22.19.51	22.19.50	22.19.49	22.19.48	22.19.47	22.19.46	22.19.45	22.19.44	22.19.43	22.19.42	22.19.41
GT11_1:DRP54	24.19.56	24.19.55	24.19.54	24.19.53	24.19.52	24.19.51	24.19.50	24.19.49	24.19.48	24.19.47	24.19.46	24.19.45	24.19.44	24.19.43	24.19.42	24.19.41
GT11_1:DRP55	26.19.56	26.19.55	26.19.54	26.19.53	26.19.52	26.19.51	26.19.50	26.19.49	26.19.48	26.19.47	26.19.46	26.19.45	26.19.44	26.19.43	26.19.42	26.19.41
GT11_1:DRP56	28.19.56	28.19.55	28.19.54	28.19.53	28.19.52	28.19.51	28.19.50	28.19.49	28.19.48	28.19.47	28.19.46	28.19.45	28.19.44	28.19.43	28.19.42	28.19.41
GT11_1:DRP57	30.19.56	30.19.55	30.19.54	30.19.53	30.19.52	30.19.51	30.19.50	30.19.49	30.19.48	30.19.47	30.19.46	30.19.45	30.19.44	30.19.43	30.19.42	30.19.41
GT11_1:DRP58	16.19.76	16.19.75	16.19.74	16.19.73	16.19.72	16.19.71	16.19.70	16.19.69	16.19.68	16.19.67	16.19.66	16.19.65	16.19.64	16.19.63	16.19.62	16.19.61
GT11_1:DRP59	18.19.76	18.19.75	18.19.74	18.19.73	18.19.72	18.19.71	18.19.70	18.19.69	18.19.68	18.19.67	18.19.66	18.19.65	18.19.64	18.19.63	18.19.62	18.19.61
GT11_1:DRP5A	20.19.76	20.19.75	20.19.74	20.19.73	20.19.72	20.19.71	20.19.70	20.19.69	20.19.68	20.19.67	20.19.66	20.19.65	20.19.64	20.19.63	20.19.62	20.19.61
GT11_1:DRP5B	22.19.76	22.19.75	22.19.74	22.19.73	22.19.72	22.19.71	22.19.70	22.19.69	22.19.68	22.19.67	22.19.66	22.19.65	22.19.64	22.19.63	22.19.62	22.19.61
GT11_1:DRP5C	24.19.76	24.19.75	24.19.74	24.19.73	24.19.72	24.19.71	24.19.70	24.19.69	24.19.68	24.19.67	24.19.66	24.19.65	24.19.64	24.19.63	24.19.62	24.19.61
GT11_1:DRP5D	26.19.76	26.19.75	26.19.74	26.19.73	26.19.72	26.19.71	26.19.70	26.19.69	26.19.68	26.19.67	26.19.66	26.19.65	26.19.64	26.19.63	26.19.62	26.19.61
GT11_1:DRP5E	28.19.76	28.19.75	28.19.74	28.19.73	28.19.72	28.19.71	28.19.70	28.19.69	28.19.68	28.19.67	28.19.66	28.19.65	28.19.64	28.19.63	28.19.62	28.19.61
GT11_1:DRP5F	30.19.76	30.19.75	30.19.74	30.19.73	30.19.72	30.19.71	30.19.70	30.19.69	30.19.68	30.19.67	30.19.66	30.19.65	30.19.64	30.19.63	30.19.62	30.19.61
GT11_1:DRP60	17.19.16	17.19.15	17.19.14	17.19.13	17.19.12	17.19.11	17.19.10	17.19.9	17.19.8	17.19.7	17.19.6	17.19.5	17.19.4	17.19.3	17.19.2	17.19.1
GT11_1:DRP61	19.19.16	19.19.15	19.19.14	19.19.13	19.19.12	19.19.11	19.19.10	19.19.9	19.19.8	19.19.7	19.19.6	19.19.5	19.19.4	19.19.3	19.19.2	19.19.1
GT11_1:DRP62	21.19.16	21.19.15	21.19.14	21.19.13	21.19.12	21.19.11	21.19.10	21.19.9	21.19.8	21.19.7	21.19.6	21.19.5	21.19.4	21.19.3	21.19.2	21.19.1
GT11_1:DRP63	23.19.16	23.19.15	23.19.14	23.19.13	23.19.12	23.19.11	23.19.10	23.19.9	23.19.8	23.19.7	23.19.6	23.19.5	23.19.4	23.19.3	23.19.2	23.19.1
GT11_1:DRP64	25.19.16	25.19.15	25.19.14	25.19.13	25.19.12	25.19.11	25.19.10	25.19.9	25.19.8	25.19.7	25.19.6	25.19.5	25.19.4	25.19.3	25.19.2	25.19.1
GT11_1:DRP65	27.19.16	27.19.15	27.19.14	27.19.13	27.19.12	27.19.11	27.19.10	27.19.9	27.19.8	27.19.7	27.19.6	27.19.5	27.19.4	27.19.3	27.19.2	27.19.1
GT11_1:DRP66	29.19.16	29.19.15	29.19.14	29.19.13	29.19.12	29.19.11	29.19.10	29.19.9	29.19.8	29.19.7	29.19.6	29.19.5	29.19.4	29.19.3	29.19.2	29.19.1
GT11_1:DRP67	31.19.16	31.19.15	31.19.14	31.19.13	31.19.12	31.19.11	31.19.10	31.19.9	31.19.8	31.19.7	31.19.6	31.19.5	31.19.4	31.19.3	31.19.2	31.19.1
GT11_1:DRP68	17.19.36	17.19.35	17.19.34	17.19.33	17.19.32	17.19.31	17.19.30	17.19.29	17.19.28	17.19.27	17.19.26	17.19.25	17.19.24	17.19.23	17.19.22	17.19.21
GT11_1:DRP69	19.19.36	19.19.35	19.19.34	19.19.33	19.19.32	19.19.31	19.19.30	19.19.29	19.19.28	19.19.27	19.19.26	19.19.25	19.19.24	19.19.23	19.19.22	19.19.21
GT11_1:DRP6A	21.19.36	21.19.35	21.19.34	21.19.33	21.19.32	21.19.31	21.19.30	21.19.29	21.19.28	21.19.27	21.19.26	21.19.25	21.19.24	21.19.23	21.19.22	21.19.21
GT11_1:DRP6B	23.19.36	23.19.35	23.19.34	23.19.33	23.19.32	23.19.31	23.19.30	23.19.29	23.19.28	23.19.27	23.19.26	23.19.25	23.19.24	23.19.23	23.19.22	23.19.21
GT11_1:DRP6C	25.19.36	25.19.35	25.19.34	25.19.33	25.19.32	25.19.31	25.19.30	25.19.29	25.19.28	25.19.27	25.19.26	25.19.25	25.19.24	25.19.23	25.19.22	25.19.21
GT11_1:DRP6D	27.19.36	27.19.35	27.19.34	27.19.33	27.19.32	27.19.31	27.19.30	27.19.29	27.19.28	27.19.27	27.19.26	27.19.25	27.19.24	27.19.23	27.19.22	27.19.21
GT11_1:DRP6E	29.19.36	29.19.35	29.19.34	29.19.33	29.19.32	29.19.31	29.19.30	29.19.29	29.19.28	29.19.27	29.19.26	29.19.25	29.19.24	29.19.23	29.19.22	29.19.21
GT11_1:DRP6F	31.19.36	31.19.35	31.19.34	31.19.33	31.19.32	31.19.31	31.19.30	31.19.29	31.19.28	31.19.27	31.19.26	31.19.25	31.19.24	31.19.23	31.19.22	31.19.21
GT11_1:DRP70	17.19.56	17.19.55	17.19.54	17.19.53	17.19.52	17.19.51	17.19.50	17.19.49	17.19.48	17.19.47	17.19.46	17.19.45	17.19.44	17.19.43	17.19.42	17.19.41
GT11_1:DRP71	19.19.56	19.19.55	19.19.54	19.19.53	19.19.52	19.19.51	19.19.50	19.19.49	19.19.48	19.19.47	19.19.46	19.19.45	19.19.44	19.19.43	19.19.42	19.19.41
GT11_1:DRP72	21.19.56	21.19.55	21.19.54	21.19.53	21.19.52	21.19.51	21.19.50	21.19.49	21.19.48	21.19.47	21.19.46	21.19.45	21.19.44	21.19.43	21.19.42	21.19.41
GT11_1:DRP73	23.19.56	23.19.55	23.19.54	23.19.53	23.19.52	23.19.51	23.19.50	23.19.49	23.19.48	23.19.47	23.19.46	23.19.45	23.19.44	23.19.43	23.19.42	23.19.41
GT11_1:DRP74	25.19.56	25.19.55	25.19.54	25.19.53	25.19.52	25.19.51	25.19.50	25.19.49	25.19.48	25.19.47	25.19.46	25.19.45	25.19.44	25.19.43	25.19.42	25.19.41
GT11_1:DRP75	27.19.56	27.19.55	27.19.54	27.19.53	27.19.52	27.19.51	27.19.50	27.19.49	27.19.48	27.19.47	27.19.46	27.19.45	27.19.44	27.19.43	27.19.42	27.19.41
GT11_1:DRP76	29.19.56	29.19.55	29.19.54	29.19.53	29.19.52	29.19.51	29.19.50	29.19.49	29.19.48	29.19.47	29.19.46	29.19.45	29.19.44	29.19.43	29.19.42	29.19.41
GT11_1:DRP77	31.19.56	31.19.55	31.19.54	31.19.53	31.19.52	31.19.51	31.19.50	31.19.49	31.19.48	31.19.47	31.19.46	31.19.45	31.19.44	31.19.43	31.19.42	31.19.41
GT11_1:DRP78	17.19.76	17.19.75	17.19.74	17.19.73	17.19.72	17.19.71	17.19.70	17.19.69	17.19.68	17.19.67	17.19.66	17.19.65	17.19.64	17.19.63	17.19.62	17.19.61
GT11_1:DRP79	19.19.76	19.19.75	19.19.74	19.19.73	19.19.72	19.19.71	19.19.70	19.19.69	19.19.68	19.19.67	19.19.66	19.19.65	19.19.64	19.19.63	19.19.62	19.19.61
GT11_1:DRP7A	21.19.76	21.19.75	21.19.74	21.19.73	21.19.72	21.19.71	21.19.70	21.19.69	21.19.68	21.19.67	21.19.66	21.19.65	21.19.64	21.19.63	21.19.62	21.19.61
GT11_1:DRP7B	23.19.76	23.19.75	23.19.74	23.19.73	23.19.72	23.19.71	23.19.70	23.19.69	23.19.68	23.19.67	23.19.66	23.19.65	23.19.64	23.19.63	23.19.62	23.19.61
GT11_1:DRP7C	25.19.76	25.19.75	25.19.74	25.19.73	25.19.72	25.19.71	25.19.70	25.19.69	25.19.68	25.19.67	25.19.66	25.19.65	25.19.64	25.19.63	25.19.62	25.19.61
GT11_1:DRP7D	27.19.76	27.19.75	27.19.74	27.19.73	27.19.72	27.19.71	27.19.70	27.19.69	27.19.68	27.19.67	27.19.66	27.19.65	27.19.64	27.19.63	27.19.62	27.19.61
GT11_1:DRP7E	29.19.76	29.19.75	29.19.74	29.19.73	29.19.72	29.19.71	29.19.70	29.19.69	29.19.68	29.19.67	29.19.66	29.19.65	29.19.64	29.19.63	29.19.62	29.19.61
GT11_1:DRP7F	31.19.76	31.19.75	31.19.74	31.19.73	31.19.72	31.19.71	31.19.70	31.19.69	31.19.68	31.19.67	31.19.66	31.19.65	31.19.64	31.19.63	31.19.62	31.19.61
non-inverted	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:MCOMMA_VALUE	3.19.36	3.19.35	3.19.34	3.19.33	3.19.32	3.19.31	3.19.30	3.19.29	3.19.28	3.19.27	3.19.26	3.19.25	3.19.24	3.19.23	3.19.22	3.19.21	3.19.16	3.19.15	3.19.14	3.19.13	3.19.12	3.19.11	3.19.10	3.19.9	3.19.8	3.19.7	3.19.6	3.19.5	3.19.4	3.19.3	3.19.2	3.19.1
GT11_0:PCOMMA_VALUE	3.19.76	3.19.75	3.19.74	3.19.73	3.19.72	3.19.71	3.19.70	3.19.69	3.19.68	3.19.67	3.19.66	3.19.65	3.19.64	3.19.63	3.19.62	3.19.61	3.19.56	3.19.55	3.19.54	3.19.53	3.19.52	3.19.51	3.19.50	3.19.49	3.19.48	3.19.47	3.19.46	3.19.45	3.19.44	3.19.43	3.19.42	3.19.41
GT11_0:RXCRCINITVAL	0.19.36	0.19.35	0.19.34	0.19.33	0.19.32	0.19.31	0.19.30	0.19.29	0.19.28	0.19.27	0.19.26	0.19.25	0.19.24	0.19.23	0.19.22	0.19.21	0.19.16	0.19.15	0.19.14	0.19.13	0.19.12	0.19.11	0.19.10	0.19.9	0.19.8	0.19.7	0.19.6	0.19.5	0.19.4	0.19.3	0.19.2	0.19.1
GT11_0:TXCRCINITVAL	0.19.76	0.19.75	0.19.74	0.19.73	0.19.72	0.19.71	0.19.70	0.19.69	0.19.68	0.19.67	0.19.66	0.19.65	0.19.64	0.19.63	0.19.62	0.19.61	0.19.56	0.19.55	0.19.54	0.19.53	0.19.52	0.19.51	0.19.50	0.19.49	0.19.48	0.19.47	0.19.46	0.19.45	0.19.44	0.19.43	0.19.42	0.19.41
GT11_1:MCOMMA_VALUE	19.19.36	19.19.35	19.19.34	19.19.33	19.19.32	19.19.31	19.19.30	19.19.29	19.19.28	19.19.27	19.19.26	19.19.25	19.19.24	19.19.23	19.19.22	19.19.21	19.19.16	19.19.15	19.19.14	19.19.13	19.19.12	19.19.11	19.19.10	19.19.9	19.19.8	19.19.7	19.19.6	19.19.5	19.19.4	19.19.3	19.19.2	19.19.1
GT11_1:PCOMMA_VALUE	19.19.76	19.19.75	19.19.74	19.19.73	19.19.72	19.19.71	19.19.70	19.19.69	19.19.68	19.19.67	19.19.66	19.19.65	19.19.64	19.19.63	19.19.62	19.19.61	19.19.56	19.19.55	19.19.54	19.19.53	19.19.52	19.19.51	19.19.50	19.19.49	19.19.48	19.19.47	19.19.46	19.19.45	19.19.44	19.19.43	19.19.42	19.19.41
GT11_1:RXCRCINITVAL	16.19.36	16.19.35	16.19.34	16.19.33	16.19.32	16.19.31	16.19.30	16.19.29	16.19.28	16.19.27	16.19.26	16.19.25	16.19.24	16.19.23	16.19.22	16.19.21	16.19.16	16.19.15	16.19.14	16.19.13	16.19.12	16.19.11	16.19.10	16.19.9	16.19.8	16.19.7	16.19.6	16.19.5	16.19.4	16.19.3	16.19.2	16.19.1
GT11_1:TXCRCINITVAL	16.19.76	16.19.75	16.19.74	16.19.73	16.19.72	16.19.71	16.19.70	16.19.69	16.19.68	16.19.67	16.19.66	16.19.65	16.19.64	16.19.63	16.19.62	16.19.61	16.19.56	16.19.55	16.19.54	16.19.53	16.19.52	16.19.51	16.19.50	16.19.49	16.19.48	16.19.47	16.19.46	16.19.45	16.19.44	16.19.43	16.19.42	16.19.41
non-inverted	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:MUX.FWDCLK0_OUT	18.19.22	18.19.21
GT11_0:MUX.FWDCLK1_OUT	18.19.24	18.19.23
GT11_1:MUX.FWDCLK0_OUT	18.19.26	18.19.25
GT11_1:MUX.FWDCLK1_OUT	18.19.28	18.19.27
FWDCLK4	0	0
FWDCLK3	0	1
FWDCLK2	1	0
FWDCLK1	1	1

GT11_0:MUX.FWDCLK1	18.19.44	18.19.43	18.19.42
NONE	0	0	0
A_FWDCLK1	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_0:MUX.FWDCLK2	18.19.41	18.19.36	18.19.35
NONE	0	0	0
A_FWDCLK2	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_0:MUX.FWDCLK3	18.19.34	18.19.33	18.19.32
NONE	0	0	0
A_FWDCLK3	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_0:MUX.FWDCLK4	18.19.31	18.19.30	18.19.29
NONE	0	0	0
A_FWDCLK4	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_0:MUX.MGT0	14.19.6	14.19.5	14.19.4
GT11_0:MUX.MGT1	14.19.3	14.19.2	14.19.1
GT11_1:MUX.MGT0	14.19.46	14.19.45	14.19.44
GT11_1:MUX.MGT1	14.19.43	14.19.42	14.19.41
NONE	0	0	0
FWDCLK0_OUT	0	0	1
FWDCLK1_OUT	0	1	0
SYNCLK_OUT	1	0	0

GT11_0:MUX.PMACLK	14.19.26	14.19.25	14.19.24	14.19.23	14.19.22	14.19.21	14.19.16	14.19.15
GT11_0:MUX.REFCLK	14.19.14	14.19.13	14.19.12	14.19.11	14.19.10	14.19.9	14.19.8	14.19.7
GT11_1:MUX.PMACLK	14.19.66	14.19.65	14.19.64	14.19.63	14.19.62	14.19.61	14.19.56	14.19.55
GT11_1:MUX.REFCLK	14.19.54	14.19.53	14.19.52	14.19.51	14.19.50	14.19.49	14.19.48	14.19.47
NONE	0	0	0	0	0	0	0	0
HCLK0	0	0	0	0	0	0	0	1
HCLK1	0	0	0	0	0	0	1	0
HCLK2	0	0	0	0	0	1	0	0
HCLK3	0	0	0	0	1	0	0	0
HCLK4	0	0	0	1	0	0	0	0
HCLK5	0	0	1	0	0	0	0	0
HCLK6	0	1	0	0	0	0	0	0
HCLK7	1	0	0	0	0	0	0	0

GT11_0:MUX.SYNCLK_OUT	10.19.75	10.19.14
GT11_1:MUX.SYNCLK_OUT	10.19.76	10.19.15
SYNCLK1	0	0
NONE	0	1
SYNCLK2	1	0

GT11_0:RESERVED_CM	4.19.36	4.19.35	4.19.34	4.19.33	4.19.32	4.19.31	4.19.30	4.19.29	4.19.28	4.19.27	4.19.26	4.19.25	4.19.24	4.19.23	4.19.22	4.19.21	4.19.16	4.19.15	4.19.14	4.19.13	4.19.12	4.19.11	4.19.10	4.19.9
GT11_1:RESERVED_CM	20.19.36	20.19.35	20.19.34	20.19.33	20.19.32	20.19.31	20.19.30	20.19.29	20.19.28	20.19.27	20.19.26	20.19.25	20.19.24	20.19.23	20.19.22	20.19.21	20.19.16	20.19.15	20.19.14	20.19.13	20.19.12	20.19.11	20.19.10	20.19.9
non-inverted	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:RESERVED_CM2	4.19.76	4.19.75	4.19.74	4.19.73	4.19.72	4.19.71	4.19.70	4.19.69	4.19.68	4.19.67	4.19.66	4.19.65	4.19.64	4.19.63	4.19.62	4.19.61	4.19.56	4.19.55	4.19.54	4.19.53	4.19.52	4.19.51
GT11_1:RESERVED_CM2	20.19.76	20.19.75	20.19.74	20.19.73	20.19.72	20.19.71	20.19.70	20.19.69	20.19.68	20.19.67	20.19.66	20.19.65	20.19.64	20.19.63	20.19.62	20.19.61	20.19.56	20.19.55	20.19.54	20.19.53	20.19.52	20.19.51
non-inverted	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:RXAFEEQ	5.19.49	5.19.48	5.19.47	5.19.46	5.19.45	5.19.44	5.19.43	5.19.42	5.19.41
GT11_1:RXAFEEQ	28.19.49	28.19.48	28.19.47	28.19.46	28.19.45	28.19.44	28.19.43	28.19.42	28.19.41
non-inverted	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:RXEQ	8.19.76	8.19.75	8.19.74	8.19.73	8.19.72	8.19.71	8.19.70	8.19.69	8.19.68	8.19.67	8.19.66	8.19.65	8.19.64	8.19.63	8.19.62	8.19.61	8.19.56	8.19.55	8.19.54	8.19.53	8.19.52	8.19.51	8.19.50	8.19.49	8.19.48	8.19.47	8.19.46	8.19.45	8.19.44	8.19.43	8.19.42	8.19.41	8.19.36	8.19.35	8.19.34	8.19.33	8.19.32	8.19.31	8.19.30	8.19.29	8.19.28	8.19.27	8.19.26	8.19.25	8.19.24	8.19.23	8.19.22	8.19.21	8.19.16	8.19.15	8.19.14	8.19.13	8.19.12	8.19.11	8.19.10	8.19.9	8.19.8	8.19.7	8.19.6	8.19.5	8.19.4	8.19.3	8.19.2	8.19.1
GT11_1:RXEQ	30.19.76	30.19.75	30.19.74	30.19.73	30.19.72	30.19.71	30.19.70	30.19.69	30.19.68	30.19.67	30.19.66	30.19.65	30.19.64	30.19.63	30.19.62	30.19.61	30.19.56	30.19.55	30.19.54	30.19.53	30.19.52	30.19.51	30.19.50	30.19.49	30.19.48	30.19.47	30.19.46	30.19.45	30.19.44	30.19.43	30.19.42	30.19.41	30.19.36	30.19.35	30.19.34	30.19.33	30.19.32	30.19.31	30.19.30	30.19.29	30.19.28	30.19.27	30.19.26	30.19.25	30.19.24	30.19.23	30.19.22	30.19.21	30.19.16	30.19.15	30.19.14	30.19.13	30.19.12	30.19.11	30.19.10	30.19.9	30.19.8	30.19.7	30.19.6	30.19.5	30.19.4	30.19.3	30.19.2	30.19.1
non-inverted	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:RXFDCAL_CLOCK_DIVIDE	6.19.56	6.19.55
GT11_0:TXFDCAL_CLOCK_DIVIDE	6.19.54	6.19.53
GT11_1:RXFDCAL_CLOCK_DIVIDE	22.19.56	22.19.55
GT11_1:TXFDCAL_CLOCK_DIVIDE	22.19.54	22.19.53
NONE	0	0
TWO	0	1
FOUR	1	0

GT11_0:RXOUTDIV2SEL	2.19.75	2.19.34	2.19.74	2.19.33	2.19.73	2.19.32
GT11_1:RXOUTDIV2SEL	27.19.75	27.19.34	27.19.74	27.19.33	27.19.73	27.19.32
1	0	0	0	0	1	1
2	0	0	1	1	0	0
4	0	0	1	1	1	1
8	1	1	0	0	0	0
16	1	1	0	0	1	1
32	1	1	1	1	0	0

GT11_0:RXPLLNDIVSEL	2.19.72	2.19.71	2.19.70
GT11_1:RXPLLNDIVSEL	27.19.72	27.19.71	27.19.70
GT11_COMMON:TXPLLNDIVSEL	21.19.72	21.19.71	21.19.70
8	0	0	0
10	0	0	1
16	0	1	0
20	0	1	1
32	1	0	0
40	1	0	1

GT11_0:RXPMACLKSEL	10.19.72	10.19.71
GT11_1:RXPMACLKSEL	10.19.74	10.19.73
GT11_COMMON:TXABPMACLKSEL	10.19.70	10.19.69
REFCLK1	0	0
REFCLK2	0	1
GREFCLK	1	0

GT11_0:RXTUNE	2.19.56	2.19.55	2.19.54	2.19.53	2.19.52	2.19.51	2.19.50	2.19.49	2.19.48	2.19.47	2.19.46	2.19.45	2.19.44
GT11_1:RXTUNE	27.19.56	27.19.55	27.19.54	27.19.53	27.19.52	27.19.51	27.19.50	27.19.49	27.19.48	27.19.47	27.19.46	27.19.45	27.19.44
GT11_COMMON:TXTUNE	21.19.56	21.19.55	21.19.54	21.19.53	21.19.52	21.19.51	21.19.50	21.19.49	21.19.48	21.19.47	21.19.46	21.19.45	21.19.44
non-inverted	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:RXUSRDIVISOR	6.19.45	6.19.44	6.19.43	6.19.42	6.19.41
GT11_1:RXUSRDIVISOR	22.19.45	22.19.44	22.19.43	22.19.42	22.19.41
1	0	0	0	0	1
2	0	0	0	1	0
4	0	0	1	0	0
8	0	1	0	0	0
16	1	0	0	0	0

GT11_0:RX_LOS_INVALID_INCR	7.19.68	7.19.67	7.19.66	7.19.65	7.19.64	7.19.63	7.19.62	7.19.61
GT11_1:RX_LOS_INVALID_INCR	23.19.68	23.19.67	23.19.66	23.19.65	23.19.64	23.19.63	23.19.62	23.19.61
1	0	0	0	0	0	0	0	1
2	0	0	0	0	0	0	1	0
4	0	0	0	0	0	1	0	0
8	0	0	0	0	1	0	0	0
16	0	0	0	1	0	0	0	0
32	0	0	1	0	0	0	0	0
64	0	1	0	0	0	0	0	0
128	1	0	0	0	0	0	0	0

GT11_0:RX_LOS_THRESHOLD	7.19.76	7.19.75	7.19.74	7.19.73	7.19.72	7.19.71	7.19.70	7.19.69
GT11_1:RX_LOS_THRESHOLD	23.19.76	23.19.75	23.19.74	23.19.73	23.19.72	23.19.71	23.19.70	23.19.69
4	0	0	0	0	0	0	0	1
8	0	0	0	0	0	0	1	0
16	0	0	0	0	0	1	0	0
32	0	0	0	0	1	0	0	0
64	0	0	0	1	0	0	0	0
128	0	0	1	0	0	0	0	0
256	0	1	0	0	0	0	0	0
512	1	0	0	0	0	0	0	0

GT11_0:TXLNDR_TST3	12.19.16	12.19.15	12.19.14	12.19.13	12.19.12	12.19.11	12.19.10	12.19.9	12.19.8	12.19.7	12.19.6	12.19.5	12.19.4	12.19.3	12.19.2
GT11_1:TXLNDR_TST3	24.19.16	24.19.15	24.19.14	24.19.13	24.19.12	24.19.11	24.19.10	24.19.9	24.19.8	24.19.7	24.19.6	24.19.5	24.19.4	24.19.3	24.19.2
non-inverted	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_0:TXOUTDIV2SEL	21.19.34	21.19.33	21.19.32
GT11_1:TXOUTDIV2SEL	21.19.75	21.19.74	21.19.73
1	0	0	1
2	0	1	0
4	0	1	1
8	1	0	0
16	1	0	1
32	1	1	0

GT11_1:MUX.FWDCLK1	18.19.56	18.19.55	18.19.54
NONE	0	0	0
B_FWDCLK1	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_1:MUX.FWDCLK2	18.19.53	18.19.52	18.19.51
NONE	0	0	0
B_FWDCLK2	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_1:MUX.FWDCLK3	18.19.50	18.19.49	18.19.48
NONE	0	0	0
B_FWDCLK3	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_1:MUX.FWDCLK4	18.19.47	18.19.46	18.19.45
NONE	0	0	0
B_FWDCLK4	0	0	1
RXPCSHCLKOUTA	1	0	0
TXPCSHCLKOUTA	1	0	1
RXPCSHCLKOUTB	1	1	0
TXPCSHCLKOUTB	1	1	1

GT11_COMMON:ATBSEL	11.19.22	11.19.21	11.19.16	11.19.15	11.19.14	11.19.13	11.19.12	11.19.11	11.19.10	11.19.9	11.19.8	11.19.7	11.19.6	11.19.5	11.19.4	11.19.3	11.19.2	11.19.1
non-inverted	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_COMMON:MUX.PMACLK	18.19.8	18.19.4
PMACLKA	0	1
PMACLKB	1	0
NONE	1	1

GT11_COMMON:MUX.REFCLK	18.19.7	18.19.3
REFCLKA	0	1
REFCLKB	1	0
NONE	1	1

GT11_COMMON:PMACFG2SPARE	11.19.76	11.19.75	11.19.74	11.19.73	11.19.72	11.19.71	11.19.70	11.19.69	11.19.68	11.19.67	11.19.66	11.19.65	11.19.64	11.19.63	11.19.62	11.19.61	11.19.56	11.19.55	11.19.54	11.19.53	11.19.52	11.19.51	11.19.50	11.19.49	11.19.48	11.19.47	11.19.46	11.19.45	11.19.44	11.19.43	11.19.42	11.19.41	11.19.36	11.19.35	11.19.34	11.19.33	11.19.32	11.19.31	11.19.30	11.19.29	11.19.28	11.19.27	11.19.26	11.19.25	11.19.24	11.19.23
non-inverted	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GT11_COMMON:REFCLKSEL	10.19.11	10.19.6	10.19.62	10.19.61
SYNCLK1IN	0	0	0	0
SYNCLK2IN	0	0	0	1
RXBCLK	0	0	1	0
REFCLK	0	0	1	1
MGTCLK	1	1	1	1

GT11_COMMON:SYNCLK1	10.19.65	10.19.64	10.19.63
GT11_COMMON:SYNCLK2	10.19.68	10.19.67	10.19.66
NONE	0	0	0
BUF_UP	0	0	1
BUF_DOWN	0	1	0
DRIVE_UP	1	0	1
DRIVE_DOWN	1	1	0
DRIVE_BOTH	1	1	1

GT11_COMMON:SYNCLK_DRIVE_ENABLE	10.19.7
inverted	~[0]

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