PowerPC 405 and Ethernet MAC
Tile PPC
Cells: 62
Bel PPC
| Pin | Direction | Wires |
|---|---|---|
| APUFCMDECODED | output | TCELL38:OUT.SEC2.TMIN |
| APUFCMDECUDI0 | output | TCELL37:OUT.SEC1.TMIN |
| APUFCMDECUDI1 | output | TCELL37:OUT.SEC2.TMIN |
| APUFCMDECUDI2 | output | TCELL37:OUT.SEC3.TMIN |
| APUFCMDECUDIVALID | output | TCELL38:OUT.SEC3.TMIN |
| APUFCMENDIAN | output | TCELL38:OUT.BEST6.TMIN |
| APUFCMFLUSH | output | TCELL38:OUT.BEST4.TMIN |
| APUFCMINSTRUCTION0 | output | TCELL61:OUT.SEC3.TMIN |
| APUFCMINSTRUCTION1 | output | TCELL61:OUT.SEC2.TMIN |
| APUFCMINSTRUCTION10 | output | TCELL60:OUT.SEC1.TMIN |
| APUFCMINSTRUCTION11 | output | TCELL60:OUT.SEC0.TMIN |
| APUFCMINSTRUCTION12 | output | TCELL60:OUT.BEST7.TMIN |
| APUFCMINSTRUCTION13 | output | TCELL60:OUT.BEST6.TMIN |
| APUFCMINSTRUCTION14 | output | TCELL60:OUT.BEST5.TMIN |
| APUFCMINSTRUCTION15 | output | TCELL60:OUT.BEST4.TMIN |
| APUFCMINSTRUCTION16 | output | TCELL59:OUT.SEC3.TMIN |
| APUFCMINSTRUCTION17 | output | TCELL59:OUT.SEC2.TMIN |
| APUFCMINSTRUCTION18 | output | TCELL59:OUT.SEC1.TMIN |
| APUFCMINSTRUCTION19 | output | TCELL59:OUT.SEC0.TMIN |
| APUFCMINSTRUCTION2 | output | TCELL61:OUT.SEC1.TMIN |
| APUFCMINSTRUCTION20 | output | TCELL59:OUT.BEST7.TMIN |
| APUFCMINSTRUCTION21 | output | TCELL59:OUT.BEST6.TMIN |
| APUFCMINSTRUCTION22 | output | TCELL59:OUT.BEST5.TMIN |
| APUFCMINSTRUCTION23 | output | TCELL59:OUT.BEST4.TMIN |
| APUFCMINSTRUCTION24 | output | TCELL58:OUT.SEC3.TMIN |
| APUFCMINSTRUCTION25 | output | TCELL58:OUT.SEC2.TMIN |
| APUFCMINSTRUCTION26 | output | TCELL58:OUT.SEC1.TMIN |
| APUFCMINSTRUCTION27 | output | TCELL58:OUT.SEC0.TMIN |
| APUFCMINSTRUCTION28 | output | TCELL58:OUT.BEST7.TMIN |
| APUFCMINSTRUCTION29 | output | TCELL58:OUT.BEST6.TMIN |
| APUFCMINSTRUCTION3 | output | TCELL61:OUT.SEC0.TMIN |
| APUFCMINSTRUCTION30 | output | TCELL58:OUT.BEST5.TMIN |
| APUFCMINSTRUCTION31 | output | TCELL58:OUT.BEST4.TMIN |
| APUFCMINSTRUCTION4 | output | TCELL61:OUT.BEST7.TMIN |
| APUFCMINSTRUCTION5 | output | TCELL61:OUT.BEST6.TMIN |
| APUFCMINSTRUCTION6 | output | TCELL61:OUT.BEST5.TMIN |
| APUFCMINSTRUCTION7 | output | TCELL61:OUT.BEST4.TMIN |
| APUFCMINSTRUCTION8 | output | TCELL60:OUT.SEC3.TMIN |
| APUFCMINSTRUCTION9 | output | TCELL60:OUT.SEC2.TMIN |
| APUFCMINSTRVALID | output | TCELL38:OUT.SEC1.TMIN |
| APUFCMLOADBYTEEN0 | output | TCELL39:OUT.SEC0.TMIN |
| APUFCMLOADBYTEEN1 | output | TCELL39:OUT.SEC1.TMIN |
| APUFCMLOADBYTEEN2 | output | TCELL39:OUT.SEC2.TMIN |
| APUFCMLOADBYTEEN3 | output | TCELL39:OUT.SEC3.TMIN |
| APUFCMLOADDATA0 | output | TCELL47:OUT.SEC0.TMIN |
| APUFCMLOADDATA1 | output | TCELL47:OUT.SEC1.TMIN |
| APUFCMLOADDATA10 | output | TCELL45:OUT.SEC2.TMIN |
| APUFCMLOADDATA11 | output | TCELL45:OUT.SEC3.TMIN |
| APUFCMLOADDATA12 | output | TCELL44:OUT.SEC0.TMIN |
| APUFCMLOADDATA13 | output | TCELL44:OUT.SEC1.TMIN |
| APUFCMLOADDATA14 | output | TCELL44:OUT.SEC2.TMIN |
| APUFCMLOADDATA15 | output | TCELL44:OUT.SEC3.TMIN |
| APUFCMLOADDATA16 | output | TCELL43:OUT.SEC0.TMIN |
| APUFCMLOADDATA17 | output | TCELL43:OUT.SEC1.TMIN |
| APUFCMLOADDATA18 | output | TCELL43:OUT.SEC2.TMIN |
| APUFCMLOADDATA19 | output | TCELL43:OUT.SEC3.TMIN |
| APUFCMLOADDATA2 | output | TCELL47:OUT.SEC2.TMIN |
| APUFCMLOADDATA20 | output | TCELL42:OUT.SEC0.TMIN |
| APUFCMLOADDATA21 | output | TCELL42:OUT.SEC1.TMIN |
| APUFCMLOADDATA22 | output | TCELL42:OUT.SEC2.TMIN |
| APUFCMLOADDATA23 | output | TCELL42:OUT.SEC3.TMIN |
| APUFCMLOADDATA24 | output | TCELL41:OUT.SEC0.TMIN |
| APUFCMLOADDATA25 | output | TCELL41:OUT.SEC1.TMIN |
| APUFCMLOADDATA26 | output | TCELL41:OUT.SEC2.TMIN |
| APUFCMLOADDATA27 | output | TCELL41:OUT.SEC3.TMIN |
| APUFCMLOADDATA28 | output | TCELL40:OUT.SEC0.TMIN |
| APUFCMLOADDATA29 | output | TCELL40:OUT.SEC1.TMIN |
| APUFCMLOADDATA3 | output | TCELL47:OUT.SEC3.TMIN |
| APUFCMLOADDATA30 | output | TCELL40:OUT.SEC2.TMIN |
| APUFCMLOADDATA31 | output | TCELL40:OUT.SEC3.TMIN |
| APUFCMLOADDATA4 | output | TCELL46:OUT.SEC0.TMIN |
| APUFCMLOADDATA5 | output | TCELL46:OUT.SEC1.TMIN |
| APUFCMLOADDATA6 | output | TCELL46:OUT.SEC2.TMIN |
| APUFCMLOADDATA7 | output | TCELL46:OUT.SEC3.TMIN |
| APUFCMLOADDATA8 | output | TCELL45:OUT.SEC0.TMIN |
| APUFCMLOADDATA9 | output | TCELL45:OUT.SEC1.TMIN |
| APUFCMLOADDVALID | output | TCELL37:OUT.SEC0.TMIN |
| APUFCMOPERANDVALID | output | TCELL37:OUT.BEST7.TMIN |
| APUFCMRADATA0 | output | TCELL47:OUT.BEST0.TMIN |
| APUFCMRADATA1 | output | TCELL47:OUT.BEST1.TMIN |
| APUFCMRADATA10 | output | TCELL45:OUT.BEST2.TMIN |
| APUFCMRADATA11 | output | TCELL45:OUT.BEST3.TMIN |
| APUFCMRADATA12 | output | TCELL44:OUT.BEST0.TMIN |
| APUFCMRADATA13 | output | TCELL44:OUT.BEST1.TMIN |
| APUFCMRADATA14 | output | TCELL44:OUT.BEST2.TMIN |
| APUFCMRADATA15 | output | TCELL44:OUT.BEST3.TMIN |
| APUFCMRADATA16 | output | TCELL43:OUT.BEST0.TMIN |
| APUFCMRADATA17 | output | TCELL43:OUT.BEST1.TMIN |
| APUFCMRADATA18 | output | TCELL43:OUT.BEST2.TMIN |
| APUFCMRADATA19 | output | TCELL43:OUT.BEST3.TMIN |
| APUFCMRADATA2 | output | TCELL47:OUT.BEST2.TMIN |
| APUFCMRADATA20 | output | TCELL42:OUT.BEST0.TMIN |
| APUFCMRADATA21 | output | TCELL42:OUT.BEST1.TMIN |
| APUFCMRADATA22 | output | TCELL42:OUT.BEST2.TMIN |
| APUFCMRADATA23 | output | TCELL42:OUT.BEST3.TMIN |
| APUFCMRADATA24 | output | TCELL41:OUT.BEST0.TMIN |
| APUFCMRADATA25 | output | TCELL41:OUT.BEST1.TMIN |
| APUFCMRADATA26 | output | TCELL41:OUT.BEST2.TMIN |
| APUFCMRADATA27 | output | TCELL41:OUT.BEST3.TMIN |
| APUFCMRADATA28 | output | TCELL40:OUT.BEST0.TMIN |
| APUFCMRADATA29 | output | TCELL40:OUT.BEST1.TMIN |
| APUFCMRADATA3 | output | TCELL47:OUT.BEST3.TMIN |
| APUFCMRADATA30 | output | TCELL40:OUT.BEST2.TMIN |
| APUFCMRADATA31 | output | TCELL40:OUT.BEST3.TMIN |
| APUFCMRADATA4 | output | TCELL46:OUT.BEST0.TMIN |
| APUFCMRADATA5 | output | TCELL46:OUT.BEST1.TMIN |
| APUFCMRADATA6 | output | TCELL46:OUT.BEST2.TMIN |
| APUFCMRADATA7 | output | TCELL46:OUT.BEST3.TMIN |
| APUFCMRADATA8 | output | TCELL45:OUT.BEST0.TMIN |
| APUFCMRADATA9 | output | TCELL45:OUT.BEST1.TMIN |
| APUFCMRBDATA0 | output | TCELL47:OUT.BEST4.TMIN |
| APUFCMRBDATA1 | output | TCELL47:OUT.BEST5.TMIN |
| APUFCMRBDATA10 | output | TCELL45:OUT.BEST6.TMIN |
| APUFCMRBDATA11 | output | TCELL45:OUT.BEST7.TMIN |
| APUFCMRBDATA12 | output | TCELL44:OUT.BEST4.TMIN |
| APUFCMRBDATA13 | output | TCELL44:OUT.BEST5.TMIN |
| APUFCMRBDATA14 | output | TCELL44:OUT.BEST6.TMIN |
| APUFCMRBDATA15 | output | TCELL44:OUT.BEST7.TMIN |
| APUFCMRBDATA16 | output | TCELL43:OUT.BEST4.TMIN |
| APUFCMRBDATA17 | output | TCELL43:OUT.BEST5.TMIN |
| APUFCMRBDATA18 | output | TCELL43:OUT.BEST6.TMIN |
| APUFCMRBDATA19 | output | TCELL43:OUT.BEST7.TMIN |
| APUFCMRBDATA2 | output | TCELL47:OUT.BEST6.TMIN |
| APUFCMRBDATA20 | output | TCELL42:OUT.BEST4.TMIN |
| APUFCMRBDATA21 | output | TCELL42:OUT.BEST5.TMIN |
| APUFCMRBDATA22 | output | TCELL42:OUT.BEST6.TMIN |
| APUFCMRBDATA23 | output | TCELL42:OUT.BEST7.TMIN |
| APUFCMRBDATA24 | output | TCELL41:OUT.BEST4.TMIN |
| APUFCMRBDATA25 | output | TCELL41:OUT.BEST5.TMIN |
| APUFCMRBDATA26 | output | TCELL41:OUT.BEST6.TMIN |
| APUFCMRBDATA27 | output | TCELL41:OUT.BEST7.TMIN |
| APUFCMRBDATA28 | output | TCELL40:OUT.BEST4.TMIN |
| APUFCMRBDATA29 | output | TCELL40:OUT.BEST5.TMIN |
| APUFCMRBDATA3 | output | TCELL47:OUT.BEST7.TMIN |
| APUFCMRBDATA30 | output | TCELL40:OUT.BEST6.TMIN |
| APUFCMRBDATA31 | output | TCELL40:OUT.BEST7.TMIN |
| APUFCMRBDATA4 | output | TCELL46:OUT.BEST4.TMIN |
| APUFCMRBDATA5 | output | TCELL46:OUT.BEST5.TMIN |
| APUFCMRBDATA6 | output | TCELL46:OUT.BEST6.TMIN |
| APUFCMRBDATA7 | output | TCELL46:OUT.BEST7.TMIN |
| APUFCMRBDATA8 | output | TCELL45:OUT.BEST4.TMIN |
| APUFCMRBDATA9 | output | TCELL45:OUT.BEST5.TMIN |
| APUFCMWRITEBACKOK | output | TCELL38:OUT.BEST5.TMIN |
| APUFCMXERCA | output | TCELL38:OUT.BEST7.TMIN |
| BISTCE0CONTINUE | input | TCELL14:IMUX.CE0 |
| BISTCE0DIAGSHIFTSEL | input | TCELL15:IMUX.CE2 |
| BISTCE0LOADIN | input | TCELL11:IMUX.SR0 |
| BISTCE0LOADOPCODE | input | TCELL15:IMUX.CE3 |
| BISTCE0TESTM1 | input | TCELL15:IMUX.CE1 |
| BRAMDSOCMCLK | input | TCELL55:IMUX.CLK0 |
| BRAMDSOCMRDDBUS0 | input | TCELL55:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS1 | input | TCELL55:IMUX.IMUX1 |
| BRAMDSOCMRDDBUS10 | input | TCELL57:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS11 | input | TCELL57:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS12 | input | TCELL58:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS13 | input | TCELL58:IMUX.IMUX1 |
| BRAMDSOCMRDDBUS14 | input | TCELL58:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS15 | input | TCELL58:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS16 | input | TCELL58:IMUX.IMUX4 |
| BRAMDSOCMRDDBUS17 | input | TCELL58:IMUX.IMUX5 |
| BRAMDSOCMRDDBUS18 | input | TCELL58:IMUX.IMUX6 |
| BRAMDSOCMRDDBUS19 | input | TCELL58:IMUX.IMUX7 |
| BRAMDSOCMRDDBUS2 | input | TCELL55:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS20 | input | TCELL59:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS21 | input | TCELL59:IMUX.IMUX1 |
| BRAMDSOCMRDDBUS22 | input | TCELL59:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS23 | input | TCELL59:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS24 | input | TCELL60:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS25 | input | TCELL60:IMUX.IMUX1 |
| BRAMDSOCMRDDBUS26 | input | TCELL60:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS27 | input | TCELL60:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS28 | input | TCELL61:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS29 | input | TCELL61:IMUX.IMUX1 |
| BRAMDSOCMRDDBUS3 | input | TCELL55:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS30 | input | TCELL61:IMUX.IMUX2 |
| BRAMDSOCMRDDBUS31 | input | TCELL61:IMUX.IMUX3 |
| BRAMDSOCMRDDBUS4 | input | TCELL55:IMUX.IMUX4 |
| BRAMDSOCMRDDBUS5 | input | TCELL55:IMUX.IMUX5 |
| BRAMDSOCMRDDBUS6 | input | TCELL55:IMUX.IMUX6 |
| BRAMDSOCMRDDBUS7 | input | TCELL55:IMUX.IMUX7 |
| BRAMDSOCMRDDBUS8 | input | TCELL57:IMUX.IMUX0 |
| BRAMDSOCMRDDBUS9 | input | TCELL57:IMUX.IMUX1 |
| BRAMISOCMCLK | input | TCELL54:IMUX.CLK0 |
| BRAMISOCMDCRRDDBUS0 | input | TCELL54:IMUX.IMUX12 |
| BRAMISOCMDCRRDDBUS1 | input | TCELL54:IMUX.IMUX13 |
| BRAMISOCMDCRRDDBUS10 | input | TCELL52:IMUX.IMUX10 |
| BRAMISOCMDCRRDDBUS11 | input | TCELL52:IMUX.IMUX11 |
| BRAMISOCMDCRRDDBUS12 | input | TCELL51:IMUX.IMUX8 |
| BRAMISOCMDCRRDDBUS13 | input | TCELL51:IMUX.IMUX9 |
| BRAMISOCMDCRRDDBUS14 | input | TCELL51:IMUX.IMUX10 |
| BRAMISOCMDCRRDDBUS15 | input | TCELL51:IMUX.IMUX11 |
| BRAMISOCMDCRRDDBUS16 | input | TCELL51:IMUX.IMUX12 |
| BRAMISOCMDCRRDDBUS17 | input | TCELL51:IMUX.IMUX13 |
| BRAMISOCMDCRRDDBUS18 | input | TCELL51:IMUX.IMUX14 |
| BRAMISOCMDCRRDDBUS19 | input | TCELL51:IMUX.IMUX15 |
| BRAMISOCMDCRRDDBUS2 | input | TCELL54:IMUX.IMUX14 |
| BRAMISOCMDCRRDDBUS20 | input | TCELL50:IMUX.IMUX8 |
| BRAMISOCMDCRRDDBUS21 | input | TCELL50:IMUX.IMUX9 |
| BRAMISOCMDCRRDDBUS22 | input | TCELL50:IMUX.IMUX10 |
| BRAMISOCMDCRRDDBUS23 | input | TCELL50:IMUX.IMUX11 |
| BRAMISOCMDCRRDDBUS24 | input | TCELL50:IMUX.IMUX12 |
| BRAMISOCMDCRRDDBUS25 | input | TCELL50:IMUX.IMUX13 |
| BRAMISOCMDCRRDDBUS26 | input | TCELL50:IMUX.IMUX14 |
| BRAMISOCMDCRRDDBUS27 | input | TCELL50:IMUX.IMUX15 |
| BRAMISOCMDCRRDDBUS28 | input | TCELL49:IMUX.IMUX12 |
| BRAMISOCMDCRRDDBUS29 | input | TCELL49:IMUX.IMUX13 |
| BRAMISOCMDCRRDDBUS3 | input | TCELL54:IMUX.IMUX15 |
| BRAMISOCMDCRRDDBUS30 | input | TCELL49:IMUX.IMUX14 |
| BRAMISOCMDCRRDDBUS31 | input | TCELL49:IMUX.IMUX15 |
| BRAMISOCMDCRRDDBUS4 | input | TCELL53:IMUX.IMUX10 |
| BRAMISOCMDCRRDDBUS5 | input | TCELL53:IMUX.IMUX11 |
| BRAMISOCMDCRRDDBUS6 | input | TCELL53:IMUX.IMUX12 |
| BRAMISOCMDCRRDDBUS7 | input | TCELL53:IMUX.IMUX13 |
| BRAMISOCMDCRRDDBUS8 | input | TCELL52:IMUX.IMUX8 |
| BRAMISOCMDCRRDDBUS9 | input | TCELL52:IMUX.IMUX9 |
| BRAMISOCMRDDBUS0 | input | TCELL54:IMUX.IMUX0 |
| BRAMISOCMRDDBUS1 | input | TCELL54:IMUX.IMUX1 |
| BRAMISOCMRDDBUS10 | input | TCELL52:IMUX.IMUX2 |
| BRAMISOCMRDDBUS11 | input | TCELL52:IMUX.IMUX3 |
| BRAMISOCMRDDBUS12 | input | TCELL51:IMUX.IMUX0 |
| BRAMISOCMRDDBUS13 | input | TCELL51:IMUX.IMUX1 |
| BRAMISOCMRDDBUS14 | input | TCELL51:IMUX.IMUX2 |
| BRAMISOCMRDDBUS15 | input | TCELL51:IMUX.IMUX3 |
| BRAMISOCMRDDBUS16 | input | TCELL54:IMUX.IMUX4 |
| BRAMISOCMRDDBUS17 | input | TCELL54:IMUX.IMUX5 |
| BRAMISOCMRDDBUS18 | input | TCELL54:IMUX.IMUX6 |
| BRAMISOCMRDDBUS19 | input | TCELL54:IMUX.IMUX7 |
| BRAMISOCMRDDBUS2 | input | TCELL54:IMUX.IMUX2 |
| BRAMISOCMRDDBUS20 | input | TCELL53:IMUX.IMUX4 |
| BRAMISOCMRDDBUS21 | input | TCELL53:IMUX.IMUX5 |
| BRAMISOCMRDDBUS22 | input | TCELL53:IMUX.IMUX6 |
| BRAMISOCMRDDBUS23 | input | TCELL53:IMUX.IMUX7 |
| BRAMISOCMRDDBUS24 | input | TCELL52:IMUX.IMUX4 |
| BRAMISOCMRDDBUS25 | input | TCELL52:IMUX.IMUX5 |
| BRAMISOCMRDDBUS26 | input | TCELL52:IMUX.IMUX6 |
| BRAMISOCMRDDBUS27 | input | TCELL52:IMUX.IMUX7 |
| BRAMISOCMRDDBUS28 | input | TCELL51:IMUX.IMUX4 |
| BRAMISOCMRDDBUS29 | input | TCELL51:IMUX.IMUX5 |
| BRAMISOCMRDDBUS3 | input | TCELL54:IMUX.IMUX3 |
| BRAMISOCMRDDBUS30 | input | TCELL51:IMUX.IMUX6 |
| BRAMISOCMRDDBUS31 | input | TCELL51:IMUX.IMUX7 |
| BRAMISOCMRDDBUS32 | input | TCELL50:IMUX.IMUX0 |
| BRAMISOCMRDDBUS33 | input | TCELL50:IMUX.IMUX1 |
| BRAMISOCMRDDBUS34 | input | TCELL50:IMUX.IMUX2 |
| BRAMISOCMRDDBUS35 | input | TCELL50:IMUX.IMUX3 |
| BRAMISOCMRDDBUS36 | input | TCELL49:IMUX.IMUX0 |
| BRAMISOCMRDDBUS37 | input | TCELL49:IMUX.IMUX1 |
| BRAMISOCMRDDBUS38 | input | TCELL49:IMUX.IMUX2 |
| BRAMISOCMRDDBUS39 | input | TCELL49:IMUX.IMUX3 |
| BRAMISOCMRDDBUS4 | input | TCELL53:IMUX.IMUX0 |
| BRAMISOCMRDDBUS40 | input | TCELL48:IMUX.IMUX0 |
| BRAMISOCMRDDBUS41 | input | TCELL48:IMUX.IMUX1 |
| BRAMISOCMRDDBUS42 | input | TCELL48:IMUX.IMUX2 |
| BRAMISOCMRDDBUS43 | input | TCELL48:IMUX.IMUX3 |
| BRAMISOCMRDDBUS44 | input | TCELL48:IMUX.IMUX8 |
| BRAMISOCMRDDBUS45 | input | TCELL48:IMUX.IMUX9 |
| BRAMISOCMRDDBUS46 | input | TCELL48:IMUX.IMUX10 |
| BRAMISOCMRDDBUS47 | input | TCELL48:IMUX.IMUX11 |
| BRAMISOCMRDDBUS48 | input | TCELL50:IMUX.IMUX4 |
| BRAMISOCMRDDBUS49 | input | TCELL50:IMUX.IMUX5 |
| BRAMISOCMRDDBUS5 | input | TCELL53:IMUX.IMUX1 |
| BRAMISOCMRDDBUS50 | input | TCELL50:IMUX.IMUX6 |
| BRAMISOCMRDDBUS51 | input | TCELL50:IMUX.IMUX7 |
| BRAMISOCMRDDBUS52 | input | TCELL49:IMUX.IMUX4 |
| BRAMISOCMRDDBUS53 | input | TCELL49:IMUX.IMUX5 |
| BRAMISOCMRDDBUS54 | input | TCELL49:IMUX.IMUX6 |
| BRAMISOCMRDDBUS55 | input | TCELL49:IMUX.IMUX7 |
| BRAMISOCMRDDBUS56 | input | TCELL48:IMUX.IMUX4 |
| BRAMISOCMRDDBUS57 | input | TCELL48:IMUX.IMUX5 |
| BRAMISOCMRDDBUS58 | input | TCELL48:IMUX.IMUX6 |
| BRAMISOCMRDDBUS59 | input | TCELL48:IMUX.IMUX7 |
| BRAMISOCMRDDBUS6 | input | TCELL53:IMUX.IMUX2 |
| BRAMISOCMRDDBUS60 | input | TCELL49:IMUX.IMUX8 |
| BRAMISOCMRDDBUS61 | input | TCELL49:IMUX.IMUX9 |
| BRAMISOCMRDDBUS62 | input | TCELL49:IMUX.IMUX10 |
| BRAMISOCMRDDBUS63 | input | TCELL49:IMUX.IMUX11 |
| BRAMISOCMRDDBUS7 | input | TCELL53:IMUX.IMUX3 |
| BRAMISOCMRDDBUS8 | input | TCELL52:IMUX.IMUX0 |
| BRAMISOCMRDDBUS9 | input | TCELL52:IMUX.IMUX1 |
| C405CPMCLOCKFB | output | TCELL36:OUT.SEC3.TMIN |
| C405CPMCORESLEEPREQ | output | TCELL8:OUT.BEST7.TMIN |
| C405CPMMSRCE | output | TCELL8:OUT.SEC0.TMIN |
| C405CPMMSREE | output | TCELL8:OUT.SEC1.TMIN |
| C405CPMTIMERIRQ | output | TCELL8:OUT.SEC2.TMIN |
| C405CPMTIMERRESETREQ | output | TCELL8:OUT.SEC3.TMIN |
| C405DBGLOADDATAONAPUDBUS | output | TCELL12:OUT.SEC3.TMIN |
| C405DBGMSRWE | output | TCELL12:OUT.BEST6.TMIN |
| C405DBGSTOPACK | output | TCELL13:OUT.SEC3.TMIN |
| C405DBGWBCOMPLETE | output | TCELL13:OUT.BEST6.TMIN |
| C405DBGWBFULL | output | TCELL8:OUT.BEST6.TMIN |
| C405DBGWBIAR0 | output | TCELL15:OUT.SEC0.TMIN |
| C405DBGWBIAR1 | output | TCELL15:OUT.SEC1.TMIN |
| C405DBGWBIAR10 | output | TCELL13:OUT.SEC1.TMIN |
| C405DBGWBIAR11 | output | TCELL13:OUT.SEC2.TMIN |
| C405DBGWBIAR12 | output | TCELL12:OUT.BEST7.TMIN |
| C405DBGWBIAR13 | output | TCELL12:OUT.SEC0.TMIN |
| C405DBGWBIAR14 | output | TCELL12:OUT.SEC1.TMIN |
| C405DBGWBIAR15 | output | TCELL12:OUT.SEC2.TMIN |
| C405DBGWBIAR16 | output | TCELL11:OUT.BEST4.TMIN |
| C405DBGWBIAR17 | output | TCELL11:OUT.BEST5.TMIN |
| C405DBGWBIAR18 | output | TCELL11:OUT.BEST6.TMIN |
| C405DBGWBIAR19 | output | TCELL11:OUT.BEST7.TMIN |
| C405DBGWBIAR2 | output | TCELL15:OUT.SEC2.TMIN |
| C405DBGWBIAR20 | output | TCELL10:OUT.BEST4.TMIN |
| C405DBGWBIAR21 | output | TCELL10:OUT.BEST5.TMIN |
| C405DBGWBIAR22 | output | TCELL10:OUT.BEST6.TMIN |
| C405DBGWBIAR23 | output | TCELL10:OUT.BEST7.TMIN |
| C405DBGWBIAR24 | output | TCELL9:OUT.BEST4.TMIN |
| C405DBGWBIAR25 | output | TCELL9:OUT.BEST5.TMIN |
| C405DBGWBIAR26 | output | TCELL9:OUT.BEST6.TMIN |
| C405DBGWBIAR27 | output | TCELL9:OUT.BEST7.TMIN |
| C405DBGWBIAR28 | output | TCELL8:OUT.BEST4.TMIN |
| C405DBGWBIAR29 | output | TCELL8:OUT.BEST5.TMIN |
| C405DBGWBIAR3 | output | TCELL15:OUT.SEC3.TMIN |
| C405DBGWBIAR4 | output | TCELL14:OUT.SEC0.TMIN |
| C405DBGWBIAR5 | output | TCELL14:OUT.SEC1.TMIN |
| C405DBGWBIAR6 | output | TCELL14:OUT.SEC2.TMIN |
| C405DBGWBIAR7 | output | TCELL14:OUT.SEC3.TMIN |
| C405DBGWBIAR8 | output | TCELL13:OUT.BEST7.TMIN |
| C405DBGWBIAR9 | output | TCELL13:OUT.SEC0.TMIN |
| C405DSOCMCACHEABLE | output | TCELL7:OUT.HALF.BOT0.TMIN, TCELL7:OUT.HALT.TOP0.TMIN |
| C405DSOCMGUARDED | output | TCELL7:OUT.HALF.BOT1.TMIN, TCELL7:OUT.HALT.TOP1.TMIN |
| C405DSOCMSTRINGMULTIPLE | output | TCELL7:OUT.HALF.BOT2.TMIN, TCELL7:OUT.HALT.TOP2.TMIN |
| C405DSOCMU0ATTR | output | TCELL7:OUT.HALF.BOT3.TMIN, TCELL7:OUT.HALT.TOP3.TMIN |
| C405ISOCMCACHEABLE | output | TCELL49:OUT.HALF.BOT4.TMIN, TCELL49:OUT.HALT.TOP4.TMIN |
| C405ISOCMCONTEXTSYNC | output | TCELL49:OUT.HALF.BOT5.TMIN, TCELL49:OUT.HALT.TOP5.TMIN |
| C405ISOCMU0ATTR | output | TCELL49:OUT.HALF.BOT6.TMIN, TCELL49:OUT.HALT.TOP6.TMIN |
| C405JTGCAPTUREDR | output | TCELL48:OUT.BEST0.TMIN |
| C405JTGEXTEST | output | TCELL48:OUT.BEST1.TMIN |
| C405JTGPGMOUT | output | TCELL48:OUT.BEST2.TMIN |
| C405JTGSHIFTDR | output | TCELL4:OUT.SEC0.TMIN |
| C405JTGTDO | output | TCELL4:OUT.SEC1.TMIN |
| C405JTGTDOEN | output | TCELL4:OUT.SEC2.TMIN |
| C405JTGUPDATEDR | output | TCELL4:OUT.SEC3.TMIN |
| C405PLBDCUABORT | output | TCELL39:OUT.BEST7.TMIN |
| C405PLBDCUABUS0 | output | TCELL35:OUT.BEST4.TMIN |
| C405PLBDCUABUS1 | output | TCELL35:OUT.BEST5.TMIN |
| C405PLBDCUABUS10 | output | TCELL33:OUT.BEST6.TMIN |
| C405PLBDCUABUS11 | output | TCELL33:OUT.BEST7.TMIN |
| C405PLBDCUABUS12 | output | TCELL32:OUT.BEST4.TMIN |
| C405PLBDCUABUS13 | output | TCELL32:OUT.BEST5.TMIN |
| C405PLBDCUABUS14 | output | TCELL32:OUT.BEST6.TMIN |
| C405PLBDCUABUS15 | output | TCELL32:OUT.BEST7.TMIN |
| C405PLBDCUABUS16 | output | TCELL31:OUT.BEST4.TMIN |
| C405PLBDCUABUS17 | output | TCELL31:OUT.BEST5.TMIN |
| C405PLBDCUABUS18 | output | TCELL31:OUT.BEST6.TMIN |
| C405PLBDCUABUS19 | output | TCELL31:OUT.BEST7.TMIN |
| C405PLBDCUABUS2 | output | TCELL35:OUT.BEST6.TMIN |
| C405PLBDCUABUS20 | output | TCELL30:OUT.BEST4.TMIN |
| C405PLBDCUABUS21 | output | TCELL30:OUT.BEST5.TMIN |
| C405PLBDCUABUS22 | output | TCELL30:OUT.BEST6.TMIN |
| C405PLBDCUABUS23 | output | TCELL30:OUT.BEST7.TMIN |
| C405PLBDCUABUS24 | output | TCELL29:OUT.BEST4.TMIN |
| C405PLBDCUABUS25 | output | TCELL29:OUT.BEST5.TMIN |
| C405PLBDCUABUS26 | output | TCELL29:OUT.BEST6.TMIN |
| C405PLBDCUABUS27 | output | TCELL29:OUT.BEST7.TMIN |
| C405PLBDCUABUS28 | output | TCELL28:OUT.BEST4.TMIN |
| C405PLBDCUABUS29 | output | TCELL28:OUT.BEST5.TMIN |
| C405PLBDCUABUS3 | output | TCELL35:OUT.BEST7.TMIN |
| C405PLBDCUABUS30 | output | TCELL28:OUT.BEST6.TMIN |
| C405PLBDCUABUS31 | output | TCELL28:OUT.BEST7.TMIN |
| C405PLBDCUABUS4 | output | TCELL34:OUT.BEST4.TMIN |
| C405PLBDCUABUS5 | output | TCELL34:OUT.BEST5.TMIN |
| C405PLBDCUABUS6 | output | TCELL34:OUT.BEST6.TMIN |
| C405PLBDCUABUS7 | output | TCELL34:OUT.BEST7.TMIN |
| C405PLBDCUABUS8 | output | TCELL33:OUT.BEST4.TMIN |
| C405PLBDCUABUS9 | output | TCELL33:OUT.BEST5.TMIN |
| C405PLBDCUBE0 | output | TCELL36:OUT.BEST4.TMIN |
| C405PLBDCUBE1 | output | TCELL36:OUT.BEST5.TMIN |
| C405PLBDCUBE2 | output | TCELL36:OUT.BEST6.TMIN |
| C405PLBDCUBE3 | output | TCELL36:OUT.BEST7.TMIN |
| C405PLBDCUBE4 | output | TCELL26:OUT.BEST4.TMIN |
| C405PLBDCUBE5 | output | TCELL26:OUT.BEST5.TMIN |
| C405PLBDCUBE6 | output | TCELL26:OUT.BEST6.TMIN |
| C405PLBDCUBE7 | output | TCELL26:OUT.BEST7.TMIN |
| C405PLBDCUCACHEABLE | output | TCELL27:OUT.SEC2.TMIN |
| C405PLBDCUGUARDED | output | TCELL37:OUT.BEST4.TMIN |
| C405PLBDCUPRIORITY0 | output | TCELL39:OUT.BEST5.TMIN |
| C405PLBDCUPRIORITY1 | output | TCELL39:OUT.BEST6.TMIN |
| C405PLBDCUREQUEST | output | TCELL39:OUT.BEST4.TMIN |
| C405PLBDCURNW | output | TCELL37:OUT.BEST6.TMIN |
| C405PLBDCUSIZE2 | output | TCELL27:OUT.SEC0.TMIN |
| C405PLBDCUU0ATTR | output | TCELL27:OUT.SEC1.TMIN |
| C405PLBDCUWRDBUS0 | output | TCELL39:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS1 | output | TCELL39:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS10 | output | TCELL37:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS11 | output | TCELL37:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS12 | output | TCELL36:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS13 | output | TCELL36:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS14 | output | TCELL36:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS15 | output | TCELL36:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS16 | output | TCELL35:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS17 | output | TCELL35:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS18 | output | TCELL35:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS19 | output | TCELL35:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS2 | output | TCELL39:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS20 | output | TCELL34:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS21 | output | TCELL34:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS22 | output | TCELL34:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS23 | output | TCELL34:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS24 | output | TCELL33:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS25 | output | TCELL33:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS26 | output | TCELL33:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS27 | output | TCELL33:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS28 | output | TCELL32:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS29 | output | TCELL32:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS3 | output | TCELL39:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS30 | output | TCELL32:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS31 | output | TCELL32:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS32 | output | TCELL31:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS33 | output | TCELL31:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS34 | output | TCELL31:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS35 | output | TCELL31:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS36 | output | TCELL30:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS37 | output | TCELL30:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS38 | output | TCELL30:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS39 | output | TCELL30:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS4 | output | TCELL38:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS40 | output | TCELL29:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS41 | output | TCELL29:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS42 | output | TCELL29:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS43 | output | TCELL29:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS44 | output | TCELL28:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS45 | output | TCELL28:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS46 | output | TCELL28:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS47 | output | TCELL28:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS48 | output | TCELL27:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS49 | output | TCELL27:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS5 | output | TCELL38:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS50 | output | TCELL27:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS51 | output | TCELL27:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS52 | output | TCELL26:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS53 | output | TCELL26:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS54 | output | TCELL26:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS55 | output | TCELL26:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS56 | output | TCELL25:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS57 | output | TCELL25:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS58 | output | TCELL25:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS59 | output | TCELL25:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS6 | output | TCELL38:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS60 | output | TCELL24:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS61 | output | TCELL24:OUT.BEST1.TMIN |
| C405PLBDCUWRDBUS62 | output | TCELL24:OUT.BEST2.TMIN |
| C405PLBDCUWRDBUS63 | output | TCELL24:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS7 | output | TCELL38:OUT.BEST3.TMIN |
| C405PLBDCUWRDBUS8 | output | TCELL37:OUT.BEST0.TMIN |
| C405PLBDCUWRDBUS9 | output | TCELL37:OUT.BEST1.TMIN |
| C405PLBDCUWRITETHRU | output | TCELL37:OUT.BEST5.TMIN |
| C405PLBICUABORT | output | TCELL27:OUT.BEST7.TMIN |
| C405PLBICUABUS0 | output | TCELL35:OUT.SEC0.TMIN |
| C405PLBICUABUS1 | output | TCELL35:OUT.SEC1.TMIN |
| C405PLBICUABUS10 | output | TCELL33:OUT.SEC2.TMIN |
| C405PLBICUABUS11 | output | TCELL33:OUT.SEC3.TMIN |
| C405PLBICUABUS12 | output | TCELL32:OUT.SEC0.TMIN |
| C405PLBICUABUS13 | output | TCELL32:OUT.SEC1.TMIN |
| C405PLBICUABUS14 | output | TCELL32:OUT.SEC2.TMIN |
| C405PLBICUABUS15 | output | TCELL32:OUT.SEC3.TMIN |
| C405PLBICUABUS16 | output | TCELL31:OUT.SEC0.TMIN |
| C405PLBICUABUS17 | output | TCELL31:OUT.SEC1.TMIN |
| C405PLBICUABUS18 | output | TCELL31:OUT.SEC2.TMIN |
| C405PLBICUABUS19 | output | TCELL31:OUT.SEC3.TMIN |
| C405PLBICUABUS2 | output | TCELL35:OUT.SEC2.TMIN |
| C405PLBICUABUS20 | output | TCELL30:OUT.SEC0.TMIN |
| C405PLBICUABUS21 | output | TCELL30:OUT.SEC1.TMIN |
| C405PLBICUABUS22 | output | TCELL30:OUT.SEC2.TMIN |
| C405PLBICUABUS23 | output | TCELL30:OUT.SEC3.TMIN |
| C405PLBICUABUS24 | output | TCELL29:OUT.SEC0.TMIN |
| C405PLBICUABUS25 | output | TCELL29:OUT.SEC1.TMIN |
| C405PLBICUABUS26 | output | TCELL29:OUT.SEC2.TMIN |
| C405PLBICUABUS27 | output | TCELL29:OUT.SEC3.TMIN |
| C405PLBICUABUS28 | output | TCELL28:OUT.SEC0.TMIN |
| C405PLBICUABUS29 | output | TCELL28:OUT.SEC1.TMIN |
| C405PLBICUABUS3 | output | TCELL35:OUT.SEC3.TMIN |
| C405PLBICUABUS4 | output | TCELL34:OUT.SEC0.TMIN |
| C405PLBICUABUS5 | output | TCELL34:OUT.SEC1.TMIN |
| C405PLBICUABUS6 | output | TCELL34:OUT.SEC2.TMIN |
| C405PLBICUABUS7 | output | TCELL34:OUT.SEC3.TMIN |
| C405PLBICUABUS8 | output | TCELL33:OUT.SEC0.TMIN |
| C405PLBICUABUS9 | output | TCELL33:OUT.SEC1.TMIN |
| C405PLBICUCACHEABLE | output | TCELL27:OUT.SEC3.TMIN |
| C405PLBICUPRIORITY0 | output | TCELL27:OUT.BEST5.TMIN |
| C405PLBICUPRIORITY1 | output | TCELL27:OUT.BEST6.TMIN |
| C405PLBICUREQUEST | output | TCELL27:OUT.BEST4.TMIN |
| C405PLBICUSIZE2 | output | TCELL26:OUT.SEC0.TMIN |
| C405PLBICUSIZE3 | output | TCELL26:OUT.SEC1.TMIN |
| C405PLBICUU0ATTR | output | TCELL26:OUT.SEC2.TMIN |
| C405RSTCHIPRESETREQ | output | TCELL9:OUT.SEC1.TMIN |
| C405RSTCORERESETREQ | output | TCELL9:OUT.SEC2.TMIN |
| C405RSTSYSRESETREQ | output | TCELL9:OUT.SEC3.TMIN |
| C405TESTRESERVE1 | input | TCELL11:IMUX.SR1 |
| C405TESTRESERVE2 | input | TCELL11:IMUX.SR2 |
| C405TRCCYCLE | output | TCELL26:OUT.SEC3.TMIN |
| C405TRCEVENEXECUTIONSTATUS0 | output | TCELL48:OUT.BEST3.TMIN |
| C405TRCEVENEXECUTIONSTATUS1 | output | TCELL48:OUT.BEST4.TMIN |
| C405TRCODDEXECUTIONSTATUS0 | output | TCELL48:OUT.BEST5.TMIN |
| C405TRCODDEXECUTIONSTATUS1 | output | TCELL48:OUT.BEST6.TMIN |
| C405TRCTRACESTATUS0 | output | TCELL25:OUT.SEC0.TMIN |
| C405TRCTRACESTATUS1 | output | TCELL25:OUT.SEC1.TMIN |
| C405TRCTRACESTATUS2 | output | TCELL25:OUT.SEC2.TMIN |
| C405TRCTRACESTATUS3 | output | TCELL25:OUT.SEC3.TMIN |
| C405TRCTRIGGEREVENTOUT | output | TCELL25:OUT.BEST7.TMIN |
| C405TRCTRIGGEREVENTTYPE0 | output | TCELL24:OUT.BEST4.TMIN |
| C405TRCTRIGGEREVENTTYPE1 | output | TCELL24:OUT.BEST5.TMIN |
| C405TRCTRIGGEREVENTTYPE10 | output | TCELL25:OUT.BEST6.TMIN |
| C405TRCTRIGGEREVENTTYPE2 | output | TCELL24:OUT.BEST6.TMIN |
| C405TRCTRIGGEREVENTTYPE3 | output | TCELL24:OUT.BEST7.TMIN |
| C405TRCTRIGGEREVENTTYPE4 | output | TCELL24:OUT.SEC0.TMIN |
| C405TRCTRIGGEREVENTTYPE5 | output | TCELL24:OUT.SEC1.TMIN |
| C405TRCTRIGGEREVENTTYPE6 | output | TCELL24:OUT.SEC2.TMIN |
| C405TRCTRIGGEREVENTTYPE7 | output | TCELL24:OUT.SEC3.TMIN |
| C405TRCTRIGGEREVENTTYPE8 | output | TCELL25:OUT.BEST4.TMIN |
| C405TRCTRIGGEREVENTTYPE9 | output | TCELL25:OUT.BEST5.TMIN |
| C405XXXMACHINECHECK | output | TCELL9:OUT.SEC0.TMIN |
| CPMC405CLOCK | input | TCELL53:IMUX.CLK0 |
| CPMC405CLOCKFBENABLE | input | TCELL54:IMUX.SR2 |
| CPMC405CORECLKINACTIVE | input | TCELL15:IMUX.IMUX5 |
| CPMC405CPUCLKEN | input | TCELL14:IMUX.IMUX9 |
| CPMC405JTAGCLKEN | input | TCELL14:IMUX.IMUX10 |
| CPMC405PLBSAMPLECYCLE | input | TCELL12:IMUX.IMUX7 |
| CPMC405PLBSAMPLECYCLEALT | input | TCELL8:IMUX.IMUX11 |
| CPMC405PLBSYNCCLOCK | input | TCELL8:IMUX.IMUX12 |
| CPMC405SYNCBYPASS | input | TCELL11:IMUX.IMUX4 |
| CPMC405TIMERCLKEN | input | TCELL14:IMUX.IMUX7 |
| CPMC405TIMERTICK | input | TCELL14:IMUX.IMUX8 |
| CPMDCRCLK | input | TCELL7:IMUX.CLK0 |
| CPMFCMCLK | input | TCELL60:IMUX.CLK0 |
| DBGC405DEBUGHALT | input | TCELL14:IMUX.IMUX4 |
| DBGC405EXTBUSHOLDACK | input | TCELL14:IMUX.IMUX5 |
| DBGC405UNCONDDEBUGEVENT | input | TCELL14:IMUX.IMUX6 |
| DCREMACENABLER | output | TCELL2:OUT.BEST7.TMIN |
| DIAGOUT | output | TCELL5:OUT.HALF.BOT0.TMIN, TCELL5:OUT.HALT.TOP0.TMIN |
| DSARCVALUE0 | input | TCELL55:IMUX.CE0 |
| DSARCVALUE1 | input | TCELL55:IMUX.CE1 |
| DSARCVALUE2 | input | TCELL55:IMUX.CE2 |
| DSARCVALUE3 | input | TCELL55:IMUX.CE3 |
| DSARCVALUE4 | input | TCELL55:IMUX.SR0 |
| DSARCVALUE5 | input | TCELL55:IMUX.SR1 |
| DSARCVALUE6 | input | TCELL55:IMUX.SR2 |
| DSARCVALUE7 | input | TCELL55:IMUX.SR3 |
| DSCNTLVALUE0 | input | TCELL56:IMUX.CE0 |
| DSCNTLVALUE1 | input | TCELL56:IMUX.CE1 |
| DSCNTLVALUE2 | input | TCELL56:IMUX.CE2 |
| DSCNTLVALUE3 | input | TCELL56:IMUX.CE3 |
| DSCNTLVALUE4 | input | TCELL56:IMUX.SR0 |
| DSCNTLVALUE5 | input | TCELL56:IMUX.SR1 |
| DSCNTLVALUE6 | input | TCELL56:IMUX.SR2 |
| DSCNTLVALUE7 | input | TCELL56:IMUX.SR3 |
| DSOCMBRAMABUS10 | output | TCELL21:OUT.SEC2.TMIN |
| DSOCMBRAMABUS11 | output | TCELL21:OUT.SEC3.TMIN |
| DSOCMBRAMABUS12 | output | TCELL23:OUT.SEC0.TMIN |
| DSOCMBRAMABUS13 | output | TCELL23:OUT.SEC1.TMIN |
| DSOCMBRAMABUS14 | output | TCELL23:OUT.SEC2.TMIN |
| DSOCMBRAMABUS15 | output | TCELL23:OUT.SEC3.TMIN |
| DSOCMBRAMABUS16 | output | TCELL56:OUT.BEST4.TMIN |
| DSOCMBRAMABUS17 | output | TCELL56:OUT.BEST5.TMIN |
| DSOCMBRAMABUS18 | output | TCELL56:OUT.BEST6.TMIN |
| DSOCMBRAMABUS19 | output | TCELL56:OUT.BEST7.TMIN |
| DSOCMBRAMABUS20 | output | TCELL56:OUT.SEC0.TMIN |
| DSOCMBRAMABUS21 | output | TCELL56:OUT.SEC1.TMIN |
| DSOCMBRAMABUS22 | output | TCELL56:OUT.SEC2.TMIN |
| DSOCMBRAMABUS23 | output | TCELL56:OUT.SEC3.TMIN |
| DSOCMBRAMABUS24 | output | TCELL55:OUT.SEC0.TMIN |
| DSOCMBRAMABUS25 | output | TCELL55:OUT.SEC1.TMIN |
| DSOCMBRAMABUS26 | output | TCELL55:OUT.SEC2.TMIN |
| DSOCMBRAMABUS27 | output | TCELL55:OUT.SEC3.TMIN |
| DSOCMBRAMABUS28 | output | TCELL57:OUT.SEC0.TMIN |
| DSOCMBRAMABUS29 | output | TCELL57:OUT.SEC1.TMIN |
| DSOCMBRAMABUS8 | output | TCELL21:OUT.SEC0.TMIN |
| DSOCMBRAMABUS9 | output | TCELL21:OUT.SEC1.TMIN |
| DSOCMBRAMBYTEWRITE0 | output | TCELL57:OUT.BEST4.TMIN |
| DSOCMBRAMBYTEWRITE1 | output | TCELL57:OUT.BEST5.TMIN |
| DSOCMBRAMBYTEWRITE2 | output | TCELL57:OUT.BEST6.TMIN |
| DSOCMBRAMBYTEWRITE3 | output | TCELL57:OUT.BEST7.TMIN |
| DSOCMBRAMEN | output | TCELL57:OUT.SEC2.TMIN |
| DSOCMBRAMWRDBUS0 | output | TCELL55:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS1 | output | TCELL55:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS10 | output | TCELL56:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS11 | output | TCELL56:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS12 | output | TCELL57:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS13 | output | TCELL57:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS14 | output | TCELL57:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS15 | output | TCELL57:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS16 | output | TCELL58:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS17 | output | TCELL58:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS18 | output | TCELL58:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS19 | output | TCELL58:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS2 | output | TCELL55:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS20 | output | TCELL59:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS21 | output | TCELL59:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS22 | output | TCELL59:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS23 | output | TCELL59:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS24 | output | TCELL60:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS25 | output | TCELL60:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS26 | output | TCELL60:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS27 | output | TCELL60:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS28 | output | TCELL61:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS29 | output | TCELL61:OUT.BEST1.TMIN |
| DSOCMBRAMWRDBUS3 | output | TCELL55:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS30 | output | TCELL61:OUT.BEST2.TMIN |
| DSOCMBRAMWRDBUS31 | output | TCELL61:OUT.BEST3.TMIN |
| DSOCMBRAMWRDBUS4 | output | TCELL55:OUT.BEST4.TMIN |
| DSOCMBRAMWRDBUS5 | output | TCELL55:OUT.BEST5.TMIN |
| DSOCMBRAMWRDBUS6 | output | TCELL55:OUT.BEST6.TMIN |
| DSOCMBRAMWRDBUS7 | output | TCELL55:OUT.BEST7.TMIN |
| DSOCMBRAMWRDBUS8 | output | TCELL56:OUT.BEST0.TMIN |
| DSOCMBRAMWRDBUS9 | output | TCELL56:OUT.BEST1.TMIN |
| DSOCMBUSY | output | TCELL38:OUT.SEC0.TMIN |
| DSOCMRDADDRVALID | output | TCELL57:OUT.SEC3.TMIN |
| DSOCMRWCOMPLETE | input | TCELL57:IMUX.IMUX7 |
| DSOCMWRADDRVALID | output | TCELL22:OUT.SEC4.TMIN |
| EICC405CRITINPUTIRQ | input | TCELL53:IMUX.IMUX8 |
| EICC405EXTINPUTIRQ | input | TCELL53:IMUX.IMUX9 |
| EXTDCRABUS0 | output | TCELL15:OUT.BEST4.TMIN |
| EXTDCRABUS1 | output | TCELL15:OUT.BEST5.TMIN |
| EXTDCRABUS2 | output | TCELL15:OUT.BEST6.TMIN |
| EXTDCRABUS3 | output | TCELL15:OUT.BEST7.TMIN |
| EXTDCRABUS4 | output | TCELL14:OUT.BEST4.TMIN |
| EXTDCRABUS5 | output | TCELL14:OUT.BEST5.TMIN |
| EXTDCRABUS6 | output | TCELL14:OUT.BEST6.TMIN |
| EXTDCRABUS7 | output | TCELL14:OUT.BEST7.TMIN |
| EXTDCRABUS8 | output | TCELL13:OUT.BEST5.TMIN |
| EXTDCRABUS9 | output | TCELL13:OUT.BEST4.TMIN |
| EXTDCRACK | input | TCELL15:IMUX.IMUX4 |
| EXTDCRDBUSIN0 | input | TCELL15:IMUX.IMUX0 |
| EXTDCRDBUSIN1 | input | TCELL15:IMUX.IMUX1 |
| EXTDCRDBUSIN10 | input | TCELL13:IMUX.IMUX2 |
| EXTDCRDBUSIN11 | input | TCELL13:IMUX.IMUX3 |
| EXTDCRDBUSIN12 | input | TCELL12:IMUX.IMUX0 |
| EXTDCRDBUSIN13 | input | TCELL12:IMUX.IMUX1 |
| EXTDCRDBUSIN14 | input | TCELL12:IMUX.IMUX2 |
| EXTDCRDBUSIN15 | input | TCELL12:IMUX.IMUX3 |
| EXTDCRDBUSIN16 | input | TCELL11:IMUX.IMUX0 |
| EXTDCRDBUSIN17 | input | TCELL11:IMUX.IMUX1 |
| EXTDCRDBUSIN18 | input | TCELL11:IMUX.IMUX2 |
| EXTDCRDBUSIN19 | input | TCELL11:IMUX.IMUX3 |
| EXTDCRDBUSIN2 | input | TCELL15:IMUX.IMUX2 |
| EXTDCRDBUSIN20 | input | TCELL10:IMUX.IMUX0 |
| EXTDCRDBUSIN21 | input | TCELL10:IMUX.IMUX1 |
| EXTDCRDBUSIN22 | input | TCELL10:IMUX.IMUX2 |
| EXTDCRDBUSIN23 | input | TCELL10:IMUX.IMUX3 |
| EXTDCRDBUSIN24 | input | TCELL9:IMUX.IMUX0 |
| EXTDCRDBUSIN25 | input | TCELL9:IMUX.IMUX1 |
| EXTDCRDBUSIN26 | input | TCELL9:IMUX.IMUX2 |
| EXTDCRDBUSIN27 | input | TCELL9:IMUX.IMUX3 |
| EXTDCRDBUSIN28 | input | TCELL8:IMUX.IMUX0 |
| EXTDCRDBUSIN29 | input | TCELL8:IMUX.IMUX1 |
| EXTDCRDBUSIN3 | input | TCELL15:IMUX.IMUX3 |
| EXTDCRDBUSIN30 | input | TCELL8:IMUX.IMUX2 |
| EXTDCRDBUSIN31 | input | TCELL8:IMUX.IMUX3 |
| EXTDCRDBUSIN4 | input | TCELL14:IMUX.IMUX0 |
| EXTDCRDBUSIN5 | input | TCELL14:IMUX.IMUX1 |
| EXTDCRDBUSIN6 | input | TCELL14:IMUX.IMUX2 |
| EXTDCRDBUSIN7 | input | TCELL14:IMUX.IMUX3 |
| EXTDCRDBUSIN8 | input | TCELL13:IMUX.IMUX0 |
| EXTDCRDBUSIN9 | input | TCELL13:IMUX.IMUX1 |
| EXTDCRDBUSOUT0 | output | TCELL15:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT1 | output | TCELL15:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT10 | output | TCELL13:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT11 | output | TCELL13:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT12 | output | TCELL12:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT13 | output | TCELL12:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT14 | output | TCELL12:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT15 | output | TCELL12:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT16 | output | TCELL11:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT17 | output | TCELL11:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT18 | output | TCELL11:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT19 | output | TCELL11:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT2 | output | TCELL15:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT20 | output | TCELL10:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT21 | output | TCELL10:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT22 | output | TCELL10:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT23 | output | TCELL10:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT24 | output | TCELL9:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT25 | output | TCELL9:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT26 | output | TCELL9:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT27 | output | TCELL9:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT28 | output | TCELL8:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT29 | output | TCELL8:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT3 | output | TCELL15:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT30 | output | TCELL8:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT31 | output | TCELL8:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT4 | output | TCELL14:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT5 | output | TCELL14:OUT.BEST1.TMIN |
| EXTDCRDBUSOUT6 | output | TCELL14:OUT.BEST2.TMIN |
| EXTDCRDBUSOUT7 | output | TCELL14:OUT.BEST3.TMIN |
| EXTDCRDBUSOUT8 | output | TCELL13:OUT.BEST0.TMIN |
| EXTDCRDBUSOUT9 | output | TCELL13:OUT.BEST1.TMIN |
| EXTDCRREAD | output | TCELL12:OUT.BEST4.TMIN |
| EXTDCRWRITE | output | TCELL12:OUT.BEST5.TMIN |
| FCMAPUCR0 | input | TCELL40:IMUX.IMUX4 |
| FCMAPUCR1 | input | TCELL40:IMUX.IMUX5 |
| FCMAPUCR2 | input | TCELL40:IMUX.IMUX6 |
| FCMAPUCR3 | input | TCELL40:IMUX.IMUX7 |
| FCMAPUDCDCREN | input | TCELL47:IMUX.IMUX7 |
| FCMAPUDCDFORCEALIGN | input | TCELL44:IMUX.IMUX4 |
| FCMAPUDCDFORCEBESTEERING | input | TCELL60:IMUX.IMUX4 |
| FCMAPUDCDFPUOP | input | TCELL40:IMUX.IMUX10 |
| FCMAPUDCDGPRWRITE | input | TCELL61:IMUX.IMUX5 |
| FCMAPUDCDLDSTBYTE | input | TCELL56:IMUX.IMUX0 |
| FCMAPUDCDLDSTDW | input | TCELL56:IMUX.IMUX3 |
| FCMAPUDCDLDSTHW | input | TCELL56:IMUX.IMUX1 |
| FCMAPUDCDLDSTQW | input | TCELL56:IMUX.IMUX4 |
| FCMAPUDCDLDSTWD | input | TCELL56:IMUX.IMUX2 |
| FCMAPUDCDLOAD | input | TCELL57:IMUX.IMUX8 |
| FCMAPUDCDPRIVOP | input | TCELL47:IMUX.IMUX6 |
| FCMAPUDCDRAEN | input | TCELL61:IMUX.IMUX6 |
| FCMAPUDCDRBEN | input | TCELL61:IMUX.IMUX7 |
| FCMAPUDCDSTORE | input | TCELL57:IMUX.IMUX9 |
| FCMAPUDCDTRAPBE | input | TCELL56:IMUX.IMUX5 |
| FCMAPUDCDTRAPLE | input | TCELL56:IMUX.IMUX6 |
| FCMAPUDCDUPDATE | input | TCELL61:IMUX.IMUX4 |
| FCMAPUDCDXERCAEN | input | TCELL47:IMUX.IMUX4 |
| FCMAPUDCDXEROVEN | input | TCELL47:IMUX.IMUX5 |
| FCMAPUDECODEBUSY | input | TCELL38:IMUX.IMUX4 |
| FCMAPUDONE | input | TCELL40:IMUX.IMUX11 |
| FCMAPUEXCEPTION | input | TCELL39:IMUX.IMUX4 |
| FCMAPUEXEBLOCKINGMCO | input | TCELL58:IMUX.IMUX8 |
| FCMAPUEXECRFIELD0 | input | TCELL57:IMUX.IMUX4 |
| FCMAPUEXECRFIELD1 | input | TCELL57:IMUX.IMUX5 |
| FCMAPUEXECRFIELD2 | input | TCELL57:IMUX.IMUX6 |
| FCMAPUEXENONBLOCKINGMCO | input | TCELL59:IMUX.IMUX4 |
| FCMAPUINSTRACK | input | TCELL40:IMUX.IMUX9 |
| FCMAPULOADWAIT | input | TCELL56:IMUX.IMUX7 |
| FCMAPURESULT0 | input | TCELL47:IMUX.IMUX0 |
| FCMAPURESULT1 | input | TCELL47:IMUX.IMUX1 |
| FCMAPURESULT10 | input | TCELL45:IMUX.IMUX2 |
| FCMAPURESULT11 | input | TCELL45:IMUX.IMUX3 |
| FCMAPURESULT12 | input | TCELL44:IMUX.IMUX0 |
| FCMAPURESULT13 | input | TCELL44:IMUX.IMUX1 |
| FCMAPURESULT14 | input | TCELL44:IMUX.IMUX2 |
| FCMAPURESULT15 | input | TCELL44:IMUX.IMUX3 |
| FCMAPURESULT16 | input | TCELL43:IMUX.IMUX0 |
| FCMAPURESULT17 | input | TCELL43:IMUX.IMUX1 |
| FCMAPURESULT18 | input | TCELL43:IMUX.IMUX2 |
| FCMAPURESULT19 | input | TCELL43:IMUX.IMUX3 |
| FCMAPURESULT2 | input | TCELL47:IMUX.IMUX2 |
| FCMAPURESULT20 | input | TCELL42:IMUX.IMUX0 |
| FCMAPURESULT21 | input | TCELL42:IMUX.IMUX1 |
| FCMAPURESULT22 | input | TCELL42:IMUX.IMUX2 |
| FCMAPURESULT23 | input | TCELL42:IMUX.IMUX3 |
| FCMAPURESULT24 | input | TCELL41:IMUX.IMUX0 |
| FCMAPURESULT25 | input | TCELL41:IMUX.IMUX1 |
| FCMAPURESULT26 | input | TCELL41:IMUX.IMUX2 |
| FCMAPURESULT27 | input | TCELL41:IMUX.IMUX3 |
| FCMAPURESULT28 | input | TCELL40:IMUX.IMUX0 |
| FCMAPURESULT29 | input | TCELL40:IMUX.IMUX1 |
| FCMAPURESULT3 | input | TCELL47:IMUX.IMUX3 |
| FCMAPURESULT30 | input | TCELL40:IMUX.IMUX2 |
| FCMAPURESULT31 | input | TCELL40:IMUX.IMUX3 |
| FCMAPURESULT4 | input | TCELL46:IMUX.IMUX0 |
| FCMAPURESULT5 | input | TCELL46:IMUX.IMUX1 |
| FCMAPURESULT6 | input | TCELL46:IMUX.IMUX2 |
| FCMAPURESULT7 | input | TCELL46:IMUX.IMUX3 |
| FCMAPURESULT8 | input | TCELL45:IMUX.IMUX0 |
| FCMAPURESULT9 | input | TCELL45:IMUX.IMUX1 |
| FCMAPURESULTVALID | input | TCELL40:IMUX.IMUX8 |
| FCMAPUSLEEPNOTREADY | input | TCELL39:IMUX.IMUX7 |
| FCMAPUXERCA | input | TCELL39:IMUX.IMUX5 |
| FCMAPUXEROV | input | TCELL39:IMUX.IMUX6 |
| ISARCVALUE0 | input | TCELL53:IMUX.CE0 |
| ISARCVALUE1 | input | TCELL53:IMUX.CE1 |
| ISARCVALUE2 | input | TCELL53:IMUX.CE2 |
| ISARCVALUE3 | input | TCELL53:IMUX.CE3 |
| ISARCVALUE4 | input | TCELL53:IMUX.SR0 |
| ISARCVALUE5 | input | TCELL53:IMUX.SR1 |
| ISARCVALUE6 | input | TCELL53:IMUX.SR2 |
| ISARCVALUE7 | input | TCELL53:IMUX.SR3 |
| ISCNTLVALUE0 | input | TCELL52:IMUX.CE0 |
| ISCNTLVALUE1 | input | TCELL52:IMUX.CE1 |
| ISCNTLVALUE2 | input | TCELL52:IMUX.CE2 |
| ISCNTLVALUE3 | input | TCELL52:IMUX.CE3 |
| ISCNTLVALUE4 | input | TCELL52:IMUX.SR0 |
| ISCNTLVALUE5 | input | TCELL52:IMUX.SR1 |
| ISCNTLVALUE6 | input | TCELL52:IMUX.SR2 |
| ISCNTLVALUE7 | input | TCELL52:IMUX.SR3 |
| ISOCMBRAMEN | output | TCELL53:OUT.BEST2.TMIN |
| ISOCMBRAMEVENWRITEEN | output | TCELL53:OUT.BEST0.TMIN |
| ISOCMBRAMODDWRITEEN | output | TCELL53:OUT.BEST1.TMIN |
| ISOCMBRAMRDABUS10 | output | TCELL53:OUT.BEST5.TMIN |
| ISOCMBRAMRDABUS11 | output | TCELL53:OUT.BEST6.TMIN |
| ISOCMBRAMRDABUS12 | output | TCELL53:OUT.BEST7.TMIN |
| ISOCMBRAMRDABUS13 | output | TCELL53:OUT.SEC0.TMIN |
| ISOCMBRAMRDABUS14 | output | TCELL53:OUT.SEC1.TMIN |
| ISOCMBRAMRDABUS15 | output | TCELL53:OUT.SEC2.TMIN |
| ISOCMBRAMRDABUS16 | output | TCELL53:OUT.SEC3.TMIN |
| ISOCMBRAMRDABUS17 | output | TCELL54:OUT.BEST0.TMIN |
| ISOCMBRAMRDABUS18 | output | TCELL54:OUT.BEST1.TMIN |
| ISOCMBRAMRDABUS19 | output | TCELL54:OUT.BEST2.TMIN |
| ISOCMBRAMRDABUS20 | output | TCELL54:OUT.BEST3.TMIN |
| ISOCMBRAMRDABUS21 | output | TCELL54:OUT.BEST4.TMIN |
| ISOCMBRAMRDABUS22 | output | TCELL54:OUT.BEST5.TMIN |
| ISOCMBRAMRDABUS23 | output | TCELL54:OUT.BEST6.TMIN |
| ISOCMBRAMRDABUS24 | output | TCELL54:OUT.BEST7.TMIN |
| ISOCMBRAMRDABUS25 | output | TCELL54:OUT.SEC0.TMIN |
| ISOCMBRAMRDABUS26 | output | TCELL54:OUT.SEC1.TMIN |
| ISOCMBRAMRDABUS27 | output | TCELL54:OUT.SEC2.TMIN |
| ISOCMBRAMRDABUS28 | output | TCELL54:OUT.SEC3.TMIN |
| ISOCMBRAMRDABUS8 | output | TCELL53:OUT.BEST3.TMIN |
| ISOCMBRAMRDABUS9 | output | TCELL53:OUT.BEST4.TMIN |
| ISOCMBRAMWRABUS10 | output | TCELL51:OUT.BEST5.TMIN |
| ISOCMBRAMWRABUS11 | output | TCELL51:OUT.BEST6.TMIN |
| ISOCMBRAMWRABUS12 | output | TCELL51:OUT.BEST7.TMIN |
| ISOCMBRAMWRABUS13 | output | TCELL51:OUT.SEC0.TMIN |
| ISOCMBRAMWRABUS14 | output | TCELL51:OUT.SEC1.TMIN |
| ISOCMBRAMWRABUS15 | output | TCELL51:OUT.SEC2.TMIN |
| ISOCMBRAMWRABUS16 | output | TCELL51:OUT.SEC3.TMIN |
| ISOCMBRAMWRABUS17 | output | TCELL52:OUT.BEST0.TMIN |
| ISOCMBRAMWRABUS18 | output | TCELL52:OUT.BEST1.TMIN |
| ISOCMBRAMWRABUS19 | output | TCELL52:OUT.BEST2.TMIN |
| ISOCMBRAMWRABUS20 | output | TCELL52:OUT.BEST3.TMIN |
| ISOCMBRAMWRABUS21 | output | TCELL52:OUT.BEST4.TMIN |
| ISOCMBRAMWRABUS22 | output | TCELL52:OUT.BEST5.TMIN |
| ISOCMBRAMWRABUS23 | output | TCELL52:OUT.BEST6.TMIN |
| ISOCMBRAMWRABUS24 | output | TCELL52:OUT.BEST7.TMIN |
| ISOCMBRAMWRABUS25 | output | TCELL52:OUT.SEC0.TMIN |
| ISOCMBRAMWRABUS26 | output | TCELL52:OUT.SEC1.TMIN |
| ISOCMBRAMWRABUS27 | output | TCELL52:OUT.SEC2.TMIN |
| ISOCMBRAMWRABUS28 | output | TCELL52:OUT.SEC3.TMIN |
| ISOCMBRAMWRABUS8 | output | TCELL51:OUT.BEST3.TMIN |
| ISOCMBRAMWRABUS9 | output | TCELL51:OUT.BEST4.TMIN |
| ISOCMBRAMWRDBUS0 | output | TCELL48:OUT.BEST7.TMIN |
| ISOCMBRAMWRDBUS1 | output | TCELL48:OUT.SEC0.TMIN |
| ISOCMBRAMWRDBUS10 | output | TCELL49:OUT.BEST5.TMIN |
| ISOCMBRAMWRDBUS11 | output | TCELL49:OUT.BEST6.TMIN |
| ISOCMBRAMWRDBUS12 | output | TCELL49:OUT.BEST7.TMIN |
| ISOCMBRAMWRDBUS13 | output | TCELL49:OUT.SEC0.TMIN |
| ISOCMBRAMWRDBUS14 | output | TCELL49:OUT.SEC1.TMIN |
| ISOCMBRAMWRDBUS15 | output | TCELL49:OUT.SEC2.TMIN |
| ISOCMBRAMWRDBUS16 | output | TCELL49:OUT.SEC3.TMIN |
| ISOCMBRAMWRDBUS17 | output | TCELL50:OUT.BEST0.TMIN |
| ISOCMBRAMWRDBUS18 | output | TCELL50:OUT.BEST1.TMIN |
| ISOCMBRAMWRDBUS19 | output | TCELL50:OUT.BEST2.TMIN |
| ISOCMBRAMWRDBUS2 | output | TCELL48:OUT.SEC1.TMIN |
| ISOCMBRAMWRDBUS20 | output | TCELL50:OUT.BEST3.TMIN |
| ISOCMBRAMWRDBUS21 | output | TCELL50:OUT.BEST4.TMIN |
| ISOCMBRAMWRDBUS22 | output | TCELL50:OUT.BEST5.TMIN |
| ISOCMBRAMWRDBUS23 | output | TCELL50:OUT.BEST6.TMIN |
| ISOCMBRAMWRDBUS24 | output | TCELL50:OUT.BEST7.TMIN |
| ISOCMBRAMWRDBUS25 | output | TCELL50:OUT.SEC0.TMIN |
| ISOCMBRAMWRDBUS26 | output | TCELL50:OUT.SEC1.TMIN |
| ISOCMBRAMWRDBUS27 | output | TCELL50:OUT.SEC2.TMIN |
| ISOCMBRAMWRDBUS28 | output | TCELL50:OUT.SEC3.TMIN |
| ISOCMBRAMWRDBUS29 | output | TCELL51:OUT.BEST0.TMIN |
| ISOCMBRAMWRDBUS3 | output | TCELL48:OUT.SEC2.TMIN |
| ISOCMBRAMWRDBUS30 | output | TCELL51:OUT.BEST1.TMIN |
| ISOCMBRAMWRDBUS31 | output | TCELL51:OUT.BEST2.TMIN |
| ISOCMBRAMWRDBUS4 | output | TCELL48:OUT.SEC3.TMIN |
| ISOCMBRAMWRDBUS5 | output | TCELL49:OUT.BEST0.TMIN |
| ISOCMBRAMWRDBUS6 | output | TCELL49:OUT.BEST1.TMIN |
| ISOCMBRAMWRDBUS7 | output | TCELL49:OUT.BEST2.TMIN |
| ISOCMBRAMWRDBUS8 | output | TCELL49:OUT.BEST3.TMIN |
| ISOCMBRAMWRDBUS9 | output | TCELL49:OUT.BEST4.TMIN |
| ISOCMDCRBRAMEVENEN | output | TCELL0:OUT.SEC1.TMIN |
| ISOCMDCRBRAMODDEN | output | TCELL0:OUT.SEC2.TMIN |
| ISOCMDCRBRAMRDSELECT | output | TCELL0:OUT.SEC3.TMIN |
| JTGC405BNDSCANTDO | input | TCELL54:IMUX.IMUX8 |
| JTGC405TCK | input | TCELL52:IMUX.CLK0 |
| JTGC405TDI | input | TCELL54:IMUX.IMUX9 |
| JTGC405TMS | input | TCELL54:IMUX.IMUX10 |
| JTGC405TRSTNEG | input | TCELL54:IMUX.IMUX11 |
| LSSDCE0A | input | TCELL15:IMUX.CE0 |
| LSSDCE0CNTLPOINT | input | TCELL14:IMUX.CE3 |
| LSSDCE0SCAN | input | TCELL14:IMUX.CE2 |
| LSSDCE0TESTM3 | input | TCELL14:IMUX.CE1 |
| LSSDCE1B | input | TCELL15:IMUX.IMUX16 |
| LSSDCE1C1 | input | TCELL9:IMUX.IMUX13 |
| LSSDCE1C3BIST | input | TCELL12:IMUX.IMUX6 |
| LSSDCE1CA1 | input | TCELL9:IMUX.IMUX14 |
| LSSDCE1CRAM | input | TCELL12:IMUX.IMUX5 |
| LSSDSCANIN0 | input | TCELL9:IMUX.CE0 |
| LSSDSCANIN1 | input | TCELL9:IMUX.CE1 |
| LSSDSCANIN10 | input | TCELL11:IMUX.CE2 |
| LSSDSCANIN11 | input | TCELL11:IMUX.CE3 |
| LSSDSCANIN12 | input | TCELL12:IMUX.CE0 |
| LSSDSCANIN13 | input | TCELL12:IMUX.CE1 |
| LSSDSCANIN14 | input | TCELL12:IMUX.CE2 |
| LSSDSCANIN15 | input | TCELL12:IMUX.CE3 |
| LSSDSCANIN2 | input | TCELL9:IMUX.CE2 |
| LSSDSCANIN3 | input | TCELL9:IMUX.CE3 |
| LSSDSCANIN4 | input | TCELL10:IMUX.CE0 |
| LSSDSCANIN5 | input | TCELL10:IMUX.CE1 |
| LSSDSCANIN6 | input | TCELL10:IMUX.CE2 |
| LSSDSCANIN7 | input | TCELL10:IMUX.CE3 |
| LSSDSCANIN8 | input | TCELL11:IMUX.CE0 |
| LSSDSCANIN9 | input | TCELL11:IMUX.CE1 |
| LSSDSCANOUT0 | output | TCELL0:OUT.HALF.BOT0.TMIN, TCELL0:OUT.HALT.TOP0.TMIN |
| LSSDSCANOUT1 | output | TCELL0:OUT.HALF.BOT1.TMIN, TCELL0:OUT.HALT.TOP1.TMIN |
| LSSDSCANOUT10 | output | TCELL1:OUT.HALF.BOT4.TMIN, TCELL1:OUT.HALT.TOP4.TMIN |
| LSSDSCANOUT11 | output | TCELL1:OUT.HALF.BOT5.TMIN, TCELL1:OUT.HALT.TOP5.TMIN |
| LSSDSCANOUT12 | output | TCELL2:OUT.HALF.BOT0.TMIN, TCELL2:OUT.HALT.TOP0.TMIN |
| LSSDSCANOUT13 | output | TCELL2:OUT.HALF.BOT1.TMIN, TCELL2:OUT.HALT.TOP1.TMIN |
| LSSDSCANOUT14 | output | TCELL2:OUT.HALF.BOT2.TMIN, TCELL2:OUT.HALT.TOP2.TMIN |
| LSSDSCANOUT15 | output | TCELL2:OUT.HALF.BOT3.TMIN, TCELL2:OUT.HALT.TOP3.TMIN |
| LSSDSCANOUT2 | output | TCELL0:OUT.HALF.BOT2.TMIN, TCELL0:OUT.HALT.TOP2.TMIN |
| LSSDSCANOUT3 | output | TCELL0:OUT.HALF.BOT3.TMIN, TCELL0:OUT.HALT.TOP3.TMIN |
| LSSDSCANOUT4 | output | TCELL0:OUT.HALF.BOT4.TMIN, TCELL0:OUT.HALT.TOP4.TMIN |
| LSSDSCANOUT5 | output | TCELL0:OUT.HALF.BOT5.TMIN, TCELL0:OUT.HALT.TOP5.TMIN |
| LSSDSCANOUT6 | output | TCELL1:OUT.HALF.BOT0.TMIN, TCELL1:OUT.HALT.TOP0.TMIN |
| LSSDSCANOUT7 | output | TCELL1:OUT.HALF.BOT1.TMIN, TCELL1:OUT.HALT.TOP1.TMIN |
| LSSDSCANOUT8 | output | TCELL1:OUT.HALF.BOT2.TMIN, TCELL1:OUT.HALT.TOP2.TMIN |
| LSSDSCANOUT9 | output | TCELL1:OUT.HALF.BOT3.TMIN, TCELL1:OUT.HALT.TOP3.TMIN |
| MCBCPUCLKEN | input | TCELL14:IMUX.SR1 |
| MCBJTAGEN | input | TCELL14:IMUX.SR0 |
| MCBTIMEREN | input | TCELL14:IMUX.SR2 |
| MCPPCRST | input | TCELL14:IMUX.SR3 |
| PLBC405DCUADDRACK | input | TCELL32:IMUX.IMUX8 |
| PLBC405DCUBUSY | input | TCELL32:IMUX.IMUX10 |
| PLBC405DCUERR | input | TCELL32:IMUX.IMUX11 |
| PLBC405DCURDDACK | input | TCELL33:IMUX.IMUX11 |
| PLBC405DCURDDBUS0 | input | TCELL41:IMUX.IMUX4 |
| PLBC405DCURDDBUS1 | input | TCELL41:IMUX.IMUX5 |
| PLBC405DCURDDBUS10 | input | TCELL37:IMUX.IMUX2 |
| PLBC405DCURDDBUS11 | input | TCELL37:IMUX.IMUX3 |
| PLBC405DCURDDBUS12 | input | TCELL36:IMUX.IMUX0 |
| PLBC405DCURDDBUS13 | input | TCELL36:IMUX.IMUX1 |
| PLBC405DCURDDBUS14 | input | TCELL36:IMUX.IMUX2 |
| PLBC405DCURDDBUS15 | input | TCELL36:IMUX.IMUX3 |
| PLBC405DCURDDBUS16 | input | TCELL35:IMUX.IMUX0 |
| PLBC405DCURDDBUS17 | input | TCELL35:IMUX.IMUX1 |
| PLBC405DCURDDBUS18 | input | TCELL35:IMUX.IMUX2 |
| PLBC405DCURDDBUS19 | input | TCELL35:IMUX.IMUX3 |
| PLBC405DCURDDBUS2 | input | TCELL41:IMUX.IMUX6 |
| PLBC405DCURDDBUS20 | input | TCELL34:IMUX.IMUX0 |
| PLBC405DCURDDBUS21 | input | TCELL34:IMUX.IMUX1 |
| PLBC405DCURDDBUS22 | input | TCELL34:IMUX.IMUX2 |
| PLBC405DCURDDBUS23 | input | TCELL34:IMUX.IMUX3 |
| PLBC405DCURDDBUS24 | input | TCELL33:IMUX.IMUX0 |
| PLBC405DCURDDBUS25 | input | TCELL33:IMUX.IMUX1 |
| PLBC405DCURDDBUS26 | input | TCELL33:IMUX.IMUX2 |
| PLBC405DCURDDBUS27 | input | TCELL33:IMUX.IMUX3 |
| PLBC405DCURDDBUS28 | input | TCELL32:IMUX.IMUX0 |
| PLBC405DCURDDBUS29 | input | TCELL32:IMUX.IMUX1 |
| PLBC405DCURDDBUS3 | input | TCELL41:IMUX.IMUX7 |
| PLBC405DCURDDBUS30 | input | TCELL32:IMUX.IMUX2 |
| PLBC405DCURDDBUS31 | input | TCELL32:IMUX.IMUX3 |
| PLBC405DCURDDBUS32 | input | TCELL31:IMUX.IMUX0 |
| PLBC405DCURDDBUS33 | input | TCELL31:IMUX.IMUX1 |
| PLBC405DCURDDBUS34 | input | TCELL31:IMUX.IMUX2 |
| PLBC405DCURDDBUS35 | input | TCELL31:IMUX.IMUX3 |
| PLBC405DCURDDBUS36 | input | TCELL30:IMUX.IMUX0 |
| PLBC405DCURDDBUS37 | input | TCELL30:IMUX.IMUX1 |
| PLBC405DCURDDBUS38 | input | TCELL30:IMUX.IMUX2 |
| PLBC405DCURDDBUS39 | input | TCELL30:IMUX.IMUX3 |
| PLBC405DCURDDBUS4 | input | TCELL39:IMUX.IMUX0 |
| PLBC405DCURDDBUS40 | input | TCELL29:IMUX.IMUX0 |
| PLBC405DCURDDBUS41 | input | TCELL29:IMUX.IMUX1 |
| PLBC405DCURDDBUS42 | input | TCELL29:IMUX.IMUX2 |
| PLBC405DCURDDBUS43 | input | TCELL29:IMUX.IMUX3 |
| PLBC405DCURDDBUS44 | input | TCELL28:IMUX.IMUX0 |
| PLBC405DCURDDBUS45 | input | TCELL28:IMUX.IMUX1 |
| PLBC405DCURDDBUS46 | input | TCELL28:IMUX.IMUX2 |
| PLBC405DCURDDBUS47 | input | TCELL28:IMUX.IMUX3 |
| PLBC405DCURDDBUS48 | input | TCELL27:IMUX.IMUX0 |
| PLBC405DCURDDBUS49 | input | TCELL27:IMUX.IMUX1 |
| PLBC405DCURDDBUS5 | input | TCELL39:IMUX.IMUX1 |
| PLBC405DCURDDBUS50 | input | TCELL27:IMUX.IMUX2 |
| PLBC405DCURDDBUS51 | input | TCELL27:IMUX.IMUX3 |
| PLBC405DCURDDBUS52 | input | TCELL26:IMUX.IMUX0 |
| PLBC405DCURDDBUS53 | input | TCELL26:IMUX.IMUX1 |
| PLBC405DCURDDBUS54 | input | TCELL26:IMUX.IMUX2 |
| PLBC405DCURDDBUS55 | input | TCELL26:IMUX.IMUX3 |
| PLBC405DCURDDBUS56 | input | TCELL25:IMUX.IMUX0 |
| PLBC405DCURDDBUS57 | input | TCELL25:IMUX.IMUX1 |
| PLBC405DCURDDBUS58 | input | TCELL25:IMUX.IMUX2 |
| PLBC405DCURDDBUS59 | input | TCELL25:IMUX.IMUX3 |
| PLBC405DCURDDBUS6 | input | TCELL39:IMUX.IMUX2 |
| PLBC405DCURDDBUS60 | input | TCELL24:IMUX.IMUX0 |
| PLBC405DCURDDBUS61 | input | TCELL24:IMUX.IMUX1 |
| PLBC405DCURDDBUS62 | input | TCELL24:IMUX.IMUX2 |
| PLBC405DCURDDBUS63 | input | TCELL24:IMUX.IMUX3 |
| PLBC405DCURDDBUS7 | input | TCELL39:IMUX.IMUX3 |
| PLBC405DCURDDBUS8 | input | TCELL37:IMUX.IMUX0 |
| PLBC405DCURDDBUS9 | input | TCELL37:IMUX.IMUX1 |
| PLBC405DCURDWDADDR1 | input | TCELL33:IMUX.IMUX8 |
| PLBC405DCURDWDADDR2 | input | TCELL33:IMUX.IMUX9 |
| PLBC405DCURDWDADDR3 | input | TCELL33:IMUX.IMUX10 |
| PLBC405DCUSSIZE1 | input | TCELL32:IMUX.IMUX9 |
| PLBC405DCUWRDACK | input | TCELL34:IMUX.IMUX8 |
| PLBC405ICUADDRACK | input | TCELL31:IMUX.IMUX8 |
| PLBC405ICUBUSY | input | TCELL31:IMUX.IMUX10 |
| PLBC405ICUERR | input | TCELL31:IMUX.IMUX11 |
| PLBC405ICURDDACK | input | TCELL30:IMUX.IMUX11 |
| PLBC405ICURDDBUS0 | input | TCELL40:IMUX.IMUX12 |
| PLBC405ICURDDBUS1 | input | TCELL40:IMUX.IMUX13 |
| PLBC405ICURDDBUS10 | input | TCELL37:IMUX.IMUX6 |
| PLBC405ICURDDBUS11 | input | TCELL37:IMUX.IMUX7 |
| PLBC405ICURDDBUS12 | input | TCELL36:IMUX.IMUX4 |
| PLBC405ICURDDBUS13 | input | TCELL36:IMUX.IMUX5 |
| PLBC405ICURDDBUS14 | input | TCELL36:IMUX.IMUX6 |
| PLBC405ICURDDBUS15 | input | TCELL36:IMUX.IMUX7 |
| PLBC405ICURDDBUS16 | input | TCELL35:IMUX.IMUX4 |
| PLBC405ICURDDBUS17 | input | TCELL35:IMUX.IMUX5 |
| PLBC405ICURDDBUS18 | input | TCELL35:IMUX.IMUX6 |
| PLBC405ICURDDBUS19 | input | TCELL35:IMUX.IMUX7 |
| PLBC405ICURDDBUS2 | input | TCELL40:IMUX.IMUX14 |
| PLBC405ICURDDBUS20 | input | TCELL34:IMUX.IMUX4 |
| PLBC405ICURDDBUS21 | input | TCELL34:IMUX.IMUX5 |
| PLBC405ICURDDBUS22 | input | TCELL34:IMUX.IMUX6 |
| PLBC405ICURDDBUS23 | input | TCELL34:IMUX.IMUX7 |
| PLBC405ICURDDBUS24 | input | TCELL33:IMUX.IMUX4 |
| PLBC405ICURDDBUS25 | input | TCELL33:IMUX.IMUX5 |
| PLBC405ICURDDBUS26 | input | TCELL33:IMUX.IMUX6 |
| PLBC405ICURDDBUS27 | input | TCELL33:IMUX.IMUX7 |
| PLBC405ICURDDBUS28 | input | TCELL32:IMUX.IMUX4 |
| PLBC405ICURDDBUS29 | input | TCELL32:IMUX.IMUX5 |
| PLBC405ICURDDBUS3 | input | TCELL40:IMUX.IMUX15 |
| PLBC405ICURDDBUS30 | input | TCELL32:IMUX.IMUX6 |
| PLBC405ICURDDBUS31 | input | TCELL32:IMUX.IMUX7 |
| PLBC405ICURDDBUS32 | input | TCELL31:IMUX.IMUX4 |
| PLBC405ICURDDBUS33 | input | TCELL31:IMUX.IMUX5 |
| PLBC405ICURDDBUS34 | input | TCELL31:IMUX.IMUX6 |
| PLBC405ICURDDBUS35 | input | TCELL31:IMUX.IMUX7 |
| PLBC405ICURDDBUS36 | input | TCELL30:IMUX.IMUX4 |
| PLBC405ICURDDBUS37 | input | TCELL30:IMUX.IMUX5 |
| PLBC405ICURDDBUS38 | input | TCELL30:IMUX.IMUX6 |
| PLBC405ICURDDBUS39 | input | TCELL30:IMUX.IMUX7 |
| PLBC405ICURDDBUS4 | input | TCELL38:IMUX.IMUX0 |
| PLBC405ICURDDBUS40 | input | TCELL29:IMUX.IMUX4 |
| PLBC405ICURDDBUS41 | input | TCELL29:IMUX.IMUX5 |
| PLBC405ICURDDBUS42 | input | TCELL29:IMUX.IMUX6 |
| PLBC405ICURDDBUS43 | input | TCELL29:IMUX.IMUX7 |
| PLBC405ICURDDBUS44 | input | TCELL28:IMUX.IMUX4 |
| PLBC405ICURDDBUS45 | input | TCELL28:IMUX.IMUX5 |
| PLBC405ICURDDBUS46 | input | TCELL28:IMUX.IMUX6 |
| PLBC405ICURDDBUS47 | input | TCELL28:IMUX.IMUX7 |
| PLBC405ICURDDBUS48 | input | TCELL27:IMUX.IMUX4 |
| PLBC405ICURDDBUS49 | input | TCELL27:IMUX.IMUX5 |
| PLBC405ICURDDBUS5 | input | TCELL38:IMUX.IMUX1 |
| PLBC405ICURDDBUS50 | input | TCELL27:IMUX.IMUX6 |
| PLBC405ICURDDBUS51 | input | TCELL27:IMUX.IMUX7 |
| PLBC405ICURDDBUS52 | input | TCELL26:IMUX.IMUX4 |
| PLBC405ICURDDBUS53 | input | TCELL26:IMUX.IMUX5 |
| PLBC405ICURDDBUS54 | input | TCELL26:IMUX.IMUX6 |
| PLBC405ICURDDBUS55 | input | TCELL26:IMUX.IMUX7 |
| PLBC405ICURDDBUS56 | input | TCELL25:IMUX.IMUX4 |
| PLBC405ICURDDBUS57 | input | TCELL25:IMUX.IMUX5 |
| PLBC405ICURDDBUS58 | input | TCELL25:IMUX.IMUX6 |
| PLBC405ICURDDBUS59 | input | TCELL25:IMUX.IMUX7 |
| PLBC405ICURDDBUS6 | input | TCELL38:IMUX.IMUX2 |
| PLBC405ICURDDBUS60 | input | TCELL24:IMUX.IMUX4 |
| PLBC405ICURDDBUS61 | input | TCELL24:IMUX.IMUX5 |
| PLBC405ICURDDBUS62 | input | TCELL24:IMUX.IMUX6 |
| PLBC405ICURDDBUS63 | input | TCELL24:IMUX.IMUX7 |
| PLBC405ICURDDBUS7 | input | TCELL38:IMUX.IMUX3 |
| PLBC405ICURDDBUS8 | input | TCELL37:IMUX.IMUX4 |
| PLBC405ICURDDBUS9 | input | TCELL37:IMUX.IMUX5 |
| PLBC405ICURDWDADDR1 | input | TCELL30:IMUX.IMUX8 |
| PLBC405ICURDWDADDR2 | input | TCELL30:IMUX.IMUX9 |
| PLBC405ICURDWDADDR3 | input | TCELL30:IMUX.IMUX10 |
| PLBC405ICUSSIZE1 | input | TCELL31:IMUX.IMUX9 |
| PLBCLK | input | TCELL51:IMUX.CLK0 |
| RSTC405RESETCHIP | input | TCELL9:IMUX.IMUX5 |
| RSTC405RESETCORE | input | TCELL9:IMUX.IMUX4 |
| RSTC405RESETSYS | input | TCELL9:IMUX.IMUX6 |
| TESTSELI | input | TCELL7:IMUX.CE1 |
| TIEAPUCONTROL0 | input | TCELL58:IMUX.SR3 |
| TIEAPUCONTROL1 | input | TCELL58:IMUX.SR2 |
| TIEAPUCONTROL10 | input | TCELL57:IMUX.SR1 |
| TIEAPUCONTROL11 | input | TCELL57:IMUX.SR0 |
| TIEAPUCONTROL12 | input | TCELL57:IMUX.CE3 |
| TIEAPUCONTROL13 | input | TCELL57:IMUX.CE2 |
| TIEAPUCONTROL14 | input | TCELL57:IMUX.CE1 |
| TIEAPUCONTROL15 | input | TCELL57:IMUX.CE0 |
| TIEAPUCONTROL2 | input | TCELL58:IMUX.SR1 |
| TIEAPUCONTROL3 | input | TCELL58:IMUX.SR0 |
| TIEAPUCONTROL4 | input | TCELL58:IMUX.CE3 |
| TIEAPUCONTROL5 | input | TCELL58:IMUX.CE2 |
| TIEAPUCONTROL6 | input | TCELL58:IMUX.CE1 |
| TIEAPUCONTROL7 | input | TCELL58:IMUX.CE0 |
| TIEAPUCONTROL8 | input | TCELL57:IMUX.SR3 |
| TIEAPUCONTROL9 | input | TCELL57:IMUX.SR2 |
| TIEAPUUDI10 | input | TCELL47:IMUX.SR3 |
| TIEAPUUDI11 | input | TCELL47:IMUX.SR2 |
| TIEAPUUDI110 | input | TCELL46:IMUX.SR1 |
| TIEAPUUDI111 | input | TCELL46:IMUX.SR0 |
| TIEAPUUDI112 | input | TCELL46:IMUX.CE3 |
| TIEAPUUDI113 | input | TCELL46:IMUX.CE2 |
| TIEAPUUDI114 | input | TCELL46:IMUX.CE1 |
| TIEAPUUDI115 | input | TCELL46:IMUX.CE0 |
| TIEAPUUDI116 | input | TCELL45:IMUX.SR3 |
| TIEAPUUDI117 | input | TCELL45:IMUX.SR2 |
| TIEAPUUDI118 | input | TCELL45:IMUX.SR1 |
| TIEAPUUDI119 | input | TCELL45:IMUX.SR0 |
| TIEAPUUDI12 | input | TCELL47:IMUX.SR1 |
| TIEAPUUDI120 | input | TCELL45:IMUX.CE3 |
| TIEAPUUDI121 | input | TCELL45:IMUX.CE2 |
| TIEAPUUDI122 | input | TCELL45:IMUX.CE1 |
| TIEAPUUDI123 | input | TCELL45:IMUX.CE0 |
| TIEAPUUDI13 | input | TCELL47:IMUX.SR0 |
| TIEAPUUDI14 | input | TCELL47:IMUX.CE3 |
| TIEAPUUDI15 | input | TCELL47:IMUX.CE2 |
| TIEAPUUDI16 | input | TCELL47:IMUX.CE1 |
| TIEAPUUDI17 | input | TCELL47:IMUX.CE0 |
| TIEAPUUDI18 | input | TCELL46:IMUX.SR3 |
| TIEAPUUDI19 | input | TCELL46:IMUX.SR2 |
| TIEAPUUDI20 | input | TCELL44:IMUX.SR3 |
| TIEAPUUDI21 | input | TCELL44:IMUX.SR2 |
| TIEAPUUDI210 | input | TCELL43:IMUX.SR1 |
| TIEAPUUDI211 | input | TCELL43:IMUX.SR0 |
| TIEAPUUDI212 | input | TCELL43:IMUX.CE3 |
| TIEAPUUDI213 | input | TCELL43:IMUX.CE2 |
| TIEAPUUDI214 | input | TCELL43:IMUX.CE1 |
| TIEAPUUDI215 | input | TCELL43:IMUX.CE0 |
| TIEAPUUDI216 | input | TCELL42:IMUX.SR3 |
| TIEAPUUDI217 | input | TCELL42:IMUX.SR2 |
| TIEAPUUDI218 | input | TCELL42:IMUX.SR1 |
| TIEAPUUDI219 | input | TCELL42:IMUX.SR0 |
| TIEAPUUDI22 | input | TCELL44:IMUX.SR1 |
| TIEAPUUDI220 | input | TCELL42:IMUX.CE3 |
| TIEAPUUDI221 | input | TCELL42:IMUX.CE2 |
| TIEAPUUDI222 | input | TCELL42:IMUX.CE1 |
| TIEAPUUDI223 | input | TCELL42:IMUX.CE0 |
| TIEAPUUDI23 | input | TCELL44:IMUX.SR0 |
| TIEAPUUDI24 | input | TCELL44:IMUX.CE3 |
| TIEAPUUDI25 | input | TCELL44:IMUX.CE2 |
| TIEAPUUDI26 | input | TCELL44:IMUX.CE1 |
| TIEAPUUDI27 | input | TCELL44:IMUX.CE0 |
| TIEAPUUDI28 | input | TCELL43:IMUX.SR3 |
| TIEAPUUDI29 | input | TCELL43:IMUX.SR2 |
| TIEAPUUDI30 | input | TCELL41:IMUX.SR3 |
| TIEAPUUDI31 | input | TCELL41:IMUX.SR2 |
| TIEAPUUDI310 | input | TCELL40:IMUX.SR1 |
| TIEAPUUDI311 | input | TCELL40:IMUX.SR0 |
| TIEAPUUDI312 | input | TCELL40:IMUX.CE3 |
| TIEAPUUDI313 | input | TCELL40:IMUX.CE2 |
| TIEAPUUDI314 | input | TCELL40:IMUX.CE1 |
| TIEAPUUDI315 | input | TCELL40:IMUX.CE0 |
| TIEAPUUDI316 | input | TCELL39:IMUX.SR3 |
| TIEAPUUDI317 | input | TCELL39:IMUX.SR2 |
| TIEAPUUDI318 | input | TCELL39:IMUX.SR1 |
| TIEAPUUDI319 | input | TCELL39:IMUX.SR0 |
| TIEAPUUDI32 | input | TCELL41:IMUX.SR1 |
| TIEAPUUDI320 | input | TCELL39:IMUX.CE3 |
| TIEAPUUDI321 | input | TCELL39:IMUX.CE2 |
| TIEAPUUDI322 | input | TCELL39:IMUX.CE1 |
| TIEAPUUDI323 | input | TCELL39:IMUX.CE0 |
| TIEAPUUDI33 | input | TCELL41:IMUX.SR0 |
| TIEAPUUDI34 | input | TCELL41:IMUX.CE3 |
| TIEAPUUDI35 | input | TCELL41:IMUX.CE2 |
| TIEAPUUDI36 | input | TCELL41:IMUX.CE1 |
| TIEAPUUDI37 | input | TCELL41:IMUX.CE0 |
| TIEAPUUDI38 | input | TCELL40:IMUX.SR3 |
| TIEAPUUDI39 | input | TCELL40:IMUX.SR2 |
| TIEAPUUDI40 | input | TCELL38:IMUX.SR3 |
| TIEAPUUDI41 | input | TCELL38:IMUX.SR2 |
| TIEAPUUDI410 | input | TCELL37:IMUX.SR1 |
| TIEAPUUDI411 | input | TCELL37:IMUX.SR0 |
| TIEAPUUDI412 | input | TCELL37:IMUX.CE3 |
| TIEAPUUDI413 | input | TCELL37:IMUX.CE2 |
| TIEAPUUDI414 | input | TCELL37:IMUX.CE1 |
| TIEAPUUDI415 | input | TCELL37:IMUX.CE0 |
| TIEAPUUDI416 | input | TCELL36:IMUX.SR3 |
| TIEAPUUDI417 | input | TCELL36:IMUX.SR2 |
| TIEAPUUDI418 | input | TCELL36:IMUX.SR1 |
| TIEAPUUDI419 | input | TCELL36:IMUX.SR0 |
| TIEAPUUDI42 | input | TCELL38:IMUX.SR1 |
| TIEAPUUDI420 | input | TCELL36:IMUX.CE3 |
| TIEAPUUDI421 | input | TCELL36:IMUX.CE2 |
| TIEAPUUDI422 | input | TCELL36:IMUX.CE1 |
| TIEAPUUDI423 | input | TCELL36:IMUX.CE0 |
| TIEAPUUDI43 | input | TCELL38:IMUX.SR0 |
| TIEAPUUDI44 | input | TCELL38:IMUX.CE3 |
| TIEAPUUDI45 | input | TCELL38:IMUX.CE2 |
| TIEAPUUDI46 | input | TCELL38:IMUX.CE1 |
| TIEAPUUDI47 | input | TCELL38:IMUX.CE0 |
| TIEAPUUDI48 | input | TCELL37:IMUX.SR3 |
| TIEAPUUDI49 | input | TCELL37:IMUX.SR2 |
| TIEAPUUDI50 | input | TCELL35:IMUX.SR3 |
| TIEAPUUDI51 | input | TCELL35:IMUX.SR2 |
| TIEAPUUDI510 | input | TCELL34:IMUX.SR1 |
| TIEAPUUDI511 | input | TCELL34:IMUX.SR0 |
| TIEAPUUDI512 | input | TCELL34:IMUX.CE3 |
| TIEAPUUDI513 | input | TCELL34:IMUX.CE2 |
| TIEAPUUDI514 | input | TCELL34:IMUX.CE1 |
| TIEAPUUDI515 | input | TCELL34:IMUX.CE0 |
| TIEAPUUDI516 | input | TCELL33:IMUX.SR3 |
| TIEAPUUDI517 | input | TCELL33:IMUX.SR2 |
| TIEAPUUDI518 | input | TCELL33:IMUX.SR1 |
| TIEAPUUDI519 | input | TCELL33:IMUX.SR0 |
| TIEAPUUDI52 | input | TCELL35:IMUX.SR1 |
| TIEAPUUDI520 | input | TCELL33:IMUX.CE3 |
| TIEAPUUDI521 | input | TCELL33:IMUX.CE2 |
| TIEAPUUDI522 | input | TCELL33:IMUX.CE1 |
| TIEAPUUDI523 | input | TCELL33:IMUX.CE0 |
| TIEAPUUDI53 | input | TCELL35:IMUX.SR0 |
| TIEAPUUDI54 | input | TCELL35:IMUX.CE3 |
| TIEAPUUDI55 | input | TCELL35:IMUX.CE2 |
| TIEAPUUDI56 | input | TCELL35:IMUX.CE1 |
| TIEAPUUDI57 | input | TCELL35:IMUX.CE0 |
| TIEAPUUDI58 | input | TCELL34:IMUX.SR3 |
| TIEAPUUDI59 | input | TCELL34:IMUX.SR2 |
| TIEAPUUDI60 | input | TCELL32:IMUX.SR3 |
| TIEAPUUDI61 | input | TCELL32:IMUX.SR2 |
| TIEAPUUDI610 | input | TCELL31:IMUX.SR1 |
| TIEAPUUDI611 | input | TCELL31:IMUX.SR0 |
| TIEAPUUDI612 | input | TCELL31:IMUX.CE3 |
| TIEAPUUDI613 | input | TCELL31:IMUX.CE2 |
| TIEAPUUDI614 | input | TCELL31:IMUX.CE1 |
| TIEAPUUDI615 | input | TCELL31:IMUX.CE0 |
| TIEAPUUDI616 | input | TCELL30:IMUX.SR3 |
| TIEAPUUDI617 | input | TCELL30:IMUX.SR2 |
| TIEAPUUDI618 | input | TCELL30:IMUX.SR1 |
| TIEAPUUDI619 | input | TCELL30:IMUX.SR0 |
| TIEAPUUDI62 | input | TCELL32:IMUX.SR1 |
| TIEAPUUDI620 | input | TCELL30:IMUX.CE3 |
| TIEAPUUDI621 | input | TCELL30:IMUX.CE2 |
| TIEAPUUDI622 | input | TCELL30:IMUX.CE1 |
| TIEAPUUDI623 | input | TCELL30:IMUX.CE0 |
| TIEAPUUDI63 | input | TCELL32:IMUX.SR0 |
| TIEAPUUDI64 | input | TCELL32:IMUX.CE3 |
| TIEAPUUDI65 | input | TCELL32:IMUX.CE2 |
| TIEAPUUDI66 | input | TCELL32:IMUX.CE1 |
| TIEAPUUDI67 | input | TCELL32:IMUX.CE0 |
| TIEAPUUDI68 | input | TCELL31:IMUX.SR3 |
| TIEAPUUDI69 | input | TCELL31:IMUX.SR2 |
| TIEAPUUDI70 | input | TCELL29:IMUX.SR3 |
| TIEAPUUDI71 | input | TCELL29:IMUX.SR2 |
| TIEAPUUDI710 | input | TCELL28:IMUX.SR1 |
| TIEAPUUDI711 | input | TCELL28:IMUX.SR0 |
| TIEAPUUDI712 | input | TCELL28:IMUX.CE3 |
| TIEAPUUDI713 | input | TCELL28:IMUX.CE2 |
| TIEAPUUDI714 | input | TCELL28:IMUX.CE1 |
| TIEAPUUDI715 | input | TCELL28:IMUX.CE0 |
| TIEAPUUDI716 | input | TCELL27:IMUX.SR3 |
| TIEAPUUDI717 | input | TCELL27:IMUX.SR2 |
| TIEAPUUDI718 | input | TCELL27:IMUX.SR1 |
| TIEAPUUDI719 | input | TCELL27:IMUX.SR0 |
| TIEAPUUDI72 | input | TCELL29:IMUX.SR1 |
| TIEAPUUDI720 | input | TCELL27:IMUX.CE3 |
| TIEAPUUDI721 | input | TCELL27:IMUX.CE2 |
| TIEAPUUDI722 | input | TCELL27:IMUX.CE1 |
| TIEAPUUDI723 | input | TCELL27:IMUX.CE0 |
| TIEAPUUDI73 | input | TCELL29:IMUX.SR0 |
| TIEAPUUDI74 | input | TCELL29:IMUX.CE3 |
| TIEAPUUDI75 | input | TCELL29:IMUX.CE2 |
| TIEAPUUDI76 | input | TCELL29:IMUX.CE1 |
| TIEAPUUDI77 | input | TCELL29:IMUX.CE0 |
| TIEAPUUDI78 | input | TCELL28:IMUX.SR3 |
| TIEAPUUDI79 | input | TCELL28:IMUX.SR2 |
| TIEAPUUDI80 | input | TCELL26:IMUX.SR3 |
| TIEAPUUDI81 | input | TCELL26:IMUX.SR2 |
| TIEAPUUDI810 | input | TCELL25:IMUX.SR1 |
| TIEAPUUDI811 | input | TCELL25:IMUX.SR0 |
| TIEAPUUDI812 | input | TCELL25:IMUX.CE3 |
| TIEAPUUDI813 | input | TCELL25:IMUX.CE2 |
| TIEAPUUDI814 | input | TCELL25:IMUX.CE1 |
| TIEAPUUDI815 | input | TCELL25:IMUX.CE0 |
| TIEAPUUDI816 | input | TCELL24:IMUX.SR3 |
| TIEAPUUDI817 | input | TCELL24:IMUX.SR2 |
| TIEAPUUDI818 | input | TCELL24:IMUX.SR1 |
| TIEAPUUDI819 | input | TCELL24:IMUX.SR0 |
| TIEAPUUDI82 | input | TCELL26:IMUX.SR1 |
| TIEAPUUDI820 | input | TCELL24:IMUX.CE3 |
| TIEAPUUDI821 | input | TCELL24:IMUX.CE2 |
| TIEAPUUDI822 | input | TCELL24:IMUX.CE1 |
| TIEAPUUDI823 | input | TCELL24:IMUX.CE0 |
| TIEAPUUDI83 | input | TCELL26:IMUX.SR0 |
| TIEAPUUDI84 | input | TCELL26:IMUX.CE3 |
| TIEAPUUDI85 | input | TCELL26:IMUX.CE2 |
| TIEAPUUDI86 | input | TCELL26:IMUX.CE1 |
| TIEAPUUDI87 | input | TCELL26:IMUX.CE0 |
| TIEAPUUDI88 | input | TCELL25:IMUX.SR3 |
| TIEAPUUDI89 | input | TCELL25:IMUX.SR2 |
| TIEC405CLOCKENABLE | input | TCELL9:IMUX.IMUX7 |
| TIEC405CLOCKSELECTS0 | input | TCELL54:IMUX.SR0 |
| TIEC405CLOCKSELECTS1 | input | TCELL54:IMUX.SR1 |
| TIEC405DCUMARGIN | input | TCELL54:IMUX.CE1 |
| TIEC405DETERMINISTICMULT | input | TCELL50:IMUX.CE0 |
| TIEC405DISOPERANDFWD | input | TCELL50:IMUX.CE1 |
| TIEC405DUTYENABLE | input | TCELL9:IMUX.IMUX8 |
| TIEC405ICUMARGIN | input | TCELL54:IMUX.CE0 |
| TIEC405MMUEN | input | TCELL50:IMUX.CE2 |
| TIEC405TAGMARGIN | input | TCELL54:IMUX.CE2 |
| TIEC405TLBMARGIN | input | TCELL54:IMUX.CE3 |
| TIEDCRADDR0 | input | TCELL6:IMUX.CE0 |
| TIEDCRADDR1 | input | TCELL6:IMUX.CE1 |
| TIEDCRADDR2 | input | TCELL6:IMUX.CE2 |
| TIEDCRADDR3 | input | TCELL6:IMUX.CE3 |
| TIEDCRADDR4 | input | TCELL6:IMUX.SR0 |
| TIEDCRADDR5 | input | TCELL7:IMUX.CE0 |
| TIEPVRBIT0 | input | TCELL20:IMUX.IMUX15 |
| TIEPVRBIT1 | input | TCELL20:IMUX.IMUX16 |
| TIEPVRBIT10 | input | TCELL13:IMUX.CE2 |
| TIEPVRBIT11 | input | TCELL13:IMUX.CE3 |
| TIEPVRBIT12 | input | TCELL16:IMUX.IMUX16 |
| TIEPVRBIT13 | input | TCELL16:IMUX.IMUX17 |
| TIEPVRBIT14 | input | TCELL16:IMUX.IMUX18 |
| TIEPVRBIT15 | input | TCELL16:IMUX.IMUX19 |
| TIEPVRBIT16 | input | TCELL17:IMUX.IMUX16 |
| TIEPVRBIT17 | input | TCELL17:IMUX.IMUX17 |
| TIEPVRBIT18 | input | TCELL17:IMUX.IMUX18 |
| TIEPVRBIT19 | input | TCELL17:IMUX.IMUX19 |
| TIEPVRBIT2 | input | TCELL20:IMUX.IMUX17 |
| TIEPVRBIT20 | input | TCELL18:IMUX.IMUX15 |
| TIEPVRBIT21 | input | TCELL18:IMUX.IMUX16 |
| TIEPVRBIT22 | input | TCELL18:IMUX.IMUX17 |
| TIEPVRBIT23 | input | TCELL18:IMUX.IMUX18 |
| TIEPVRBIT24 | input | TCELL19:IMUX.IMUX15 |
| TIEPVRBIT25 | input | TCELL19:IMUX.IMUX16 |
| TIEPVRBIT26 | input | TCELL19:IMUX.IMUX17 |
| TIEPVRBIT27 | input | TCELL19:IMUX.IMUX18 |
| TIEPVRBIT28 | input | TCELL8:IMUX.CE0 |
| TIEPVRBIT29 | input | TCELL8:IMUX.CE1 |
| TIEPVRBIT3 | input | TCELL20:IMUX.IMUX18 |
| TIEPVRBIT30 | input | TCELL8:IMUX.CE2 |
| TIEPVRBIT31 | input | TCELL8:IMUX.CE3 |
| TIEPVRBIT4 | input | TCELL21:IMUX.IMUX15 |
| TIEPVRBIT5 | input | TCELL21:IMUX.IMUX16 |
| TIEPVRBIT6 | input | TCELL21:IMUX.IMUX17 |
| TIEPVRBIT7 | input | TCELL21:IMUX.IMUX18 |
| TIEPVRBIT8 | input | TCELL13:IMUX.CE0 |
| TIEPVRBIT9 | input | TCELL13:IMUX.CE1 |
| TRCC405TRACEDISABLE | input | TCELL24:IMUX.IMUX8 |
| TRCC405TRIGGEREVENTIN | input | TCELL24:IMUX.IMUX9 |
| TSTAPUC405APUDIVENI | input | TCELL44:IMUX.IMUX6 |
| TSTAPUC405APUDIVENO | output | TCELL36:OUT.HALF.BOT2.TMIN, TCELL36:OUT.HALT.TOP2.TMIN |
| TSTAPUC405APUPRESENTI | input | TCELL44:IMUX.IMUX7 |
| TSTAPUC405APUPRESENTO | output | TCELL36:OUT.HALF.BOT3.TMIN, TCELL36:OUT.HALT.TOP3.TMIN |
| TSTAPUC405DCDAPUOPI | input | TCELL44:IMUX.IMUX9 |
| TSTAPUC405DCDAPUOPO | output | TCELL36:OUT.HALF.BOT4.TMIN, TCELL36:OUT.HALT.TOP4.TMIN |
| TSTAPUC405DCDCRENI | input | TCELL59:IMUX.IMUX14 |
| TSTAPUC405DCDCRENO | output | TCELL29:OUT.HALF.BOT4.TMIN, TCELL29:OUT.HALT.TOP4.TMIN |
| TSTAPUC405DCDFORCEALIGNI | input | TCELL42:IMUX.IMUX4 |
| TSTAPUC405DCDFORCEALIGNO | output | TCELL36:OUT.HALF.BOT5.TMIN, TCELL36:OUT.HALT.TOP5.TMIN |
| TSTAPUC405DCDFORCEBESTEERINGI | input | TCELL42:IMUX.IMUX5 |
| TSTAPUC405DCDFORCEBESTEERINGO | output | TCELL36:OUT.HALF.BOT6.TMIN, TCELL36:OUT.HALT.TOP6.TMIN |
| TSTAPUC405DCDFPUOPI | input | TCELL60:IMUX.IMUX12 |
| TSTAPUC405DCDFPUOPO | output | TCELL31:OUT.HALF.BOT7.TMIN, TCELL31:OUT.HALT.TOP7.TMIN |
| TSTAPUC405DCDGPRWRITEI | input | TCELL60:IMUX.IMUX13 |
| TSTAPUC405DCDGPRWRITEO | output | TCELL31:OUT.HALF.BOT0.TMIN, TCELL31:OUT.HALT.TOP0.TMIN |
| TSTAPUC405DCDLDSTBYTEI | input | TCELL42:IMUX.IMUX6 |
| TSTAPUC405DCDLDSTBYTEO | output | TCELL36:OUT.HALF.BOT7.TMIN, TCELL36:OUT.HALT.TOP7.TMIN |
| TSTAPUC405DCDLDSTDWI | input | TCELL43:IMUX.IMUX6 |
| TSTAPUC405DCDLDSTDWO | output | TCELL29:OUT.HALF.BOT1.TMIN, TCELL29:OUT.HALT.TOP1.TMIN |
| TSTAPUC405DCDLDSTHWI | input | TCELL43:IMUX.IMUX4 |
| TSTAPUC405DCDLDSTHWO | output | TCELL29:OUT.HALF.BOT7.TMIN, TCELL29:OUT.HALT.TOP7.TMIN |
| TSTAPUC405DCDLDSTQWI | input | TCELL43:IMUX.IMUX7 |
| TSTAPUC405DCDLDSTQWO | output | TCELL29:OUT.HALF.BOT2.TMIN, TCELL29:OUT.HALT.TOP2.TMIN |
| TSTAPUC405DCDLDSTWDI | input | TCELL43:IMUX.IMUX5 |
| TSTAPUC405DCDLDSTWDO | output | TCELL29:OUT.HALF.BOT0.TMIN, TCELL29:OUT.HALT.TOP0.TMIN |
| TSTAPUC405DCDLOADI | input | TCELL59:IMUX.IMUX9 |
| TSTAPUC405DCDLOADO | output | TCELL31:OUT.HALF.BOT3.TMIN, TCELL31:OUT.HALT.TOP3.TMIN |
| TSTAPUC405DCDPRIVOPI | input | TCELL59:IMUX.IMUX13 |
| TSTAPUC405DCDPRIVOPO | output | TCELL30:OUT.HALF.BOT3.TMIN, TCELL30:OUT.HALT.TOP3.TMIN |
| TSTAPUC405DCDRAENI | input | TCELL60:IMUX.IMUX14 |
| TSTAPUC405DCDRAENO | output | TCELL31:OUT.HALF.BOT1.TMIN, TCELL31:OUT.HALT.TOP1.TMIN |
| TSTAPUC405DCDRBENI | input | TCELL60:IMUX.IMUX15 |
| TSTAPUC405DCDRBENO | output | TCELL31:OUT.HALF.BOT2.TMIN, TCELL31:OUT.HALT.TOP2.TMIN |
| TSTAPUC405DCDSTOREI | input | TCELL59:IMUX.IMUX10 |
| TSTAPUC405DCDSTOREO | output | TCELL30:OUT.HALF.BOT0.TMIN, TCELL30:OUT.HALT.TOP0.TMIN |
| TSTAPUC405DCDTRAPBEI | input | TCELL58:IMUX.IMUX14 |
| TSTAPUC405DCDTRAPBEO | output | TCELL29:OUT.HALF.BOT3.TMIN, TCELL29:OUT.HALT.TOP3.TMIN |
| TSTAPUC405DCDTRAPLEI | input | TCELL58:IMUX.IMUX15 |
| TSTAPUC405DCDTRAPLEO | output | TCELL28:OUT.HALF.BOT4.TMIN, TCELL28:OUT.HALT.TOP4.TMIN |
| TSTAPUC405DCDUPDATEI | input | TCELL59:IMUX.IMUX15 |
| TSTAPUC405DCDUPDATEO | output | TCELL29:OUT.HALF.BOT5.TMIN, TCELL29:OUT.HALT.TOP5.TMIN |
| TSTAPUC405DCDVALIDOPI | input | TCELL44:IMUX.IMUX8 |
| TSTAPUC405DCDVALIDOPO | output | TCELL36:OUT.HALF.BOT1.TMIN, TCELL36:OUT.HALT.TOP1.TMIN |
| TSTAPUC405DCDXERCAENI | input | TCELL59:IMUX.IMUX11 |
| TSTAPUC405DCDXERCAENO | output | TCELL30:OUT.HALF.BOT1.TMIN, TCELL30:OUT.HALT.TOP1.TMIN |
| TSTAPUC405DCDXEROVENI | input | TCELL59:IMUX.IMUX12 |
| TSTAPUC405DCDXEROVENO | output | TCELL30:OUT.HALF.BOT2.TMIN, TCELL30:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXCEPTIONI | input | TCELL45:IMUX.IMUX4 |
| TSTAPUC405EXCEPTIONO | output | TCELL28:OUT.SEC3.TMIN |
| TSTAPUC405EXEBLOCKINGMCOI | input | TCELL45:IMUX.IMUX5 |
| TSTAPUC405EXEBLOCKINGMCOO | output | TCELL28:OUT.HALF.BOT0.TMIN, TCELL28:OUT.HALT.TOP0.TMIN |
| TSTAPUC405EXEBUSYI | input | TCELL45:IMUX.IMUX7 |
| TSTAPUC405EXEBUSYO | output | TCELL28:OUT.HALF.BOT2.TMIN, TCELL28:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXECRFIELDI0 | input | TCELL60:IMUX.IMUX9 |
| TSTAPUC405EXECRFIELDI1 | input | TCELL60:IMUX.IMUX10 |
| TSTAPUC405EXECRFIELDI2 | input | TCELL60:IMUX.IMUX11 |
| TSTAPUC405EXECRFIELDO0 | output | TCELL31:OUT.HALF.BOT4.TMIN, TCELL31:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXECRFIELDO1 | output | TCELL31:OUT.HALF.BOT5.TMIN, TCELL31:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXECRFIELDO2 | output | TCELL31:OUT.HALF.BOT6.TMIN, TCELL31:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXECRI0 | input | TCELL61:IMUX.IMUX12 |
| TSTAPUC405EXECRI1 | input | TCELL61:IMUX.IMUX13 |
| TSTAPUC405EXECRI2 | input | TCELL61:IMUX.IMUX14 |
| TSTAPUC405EXECRI3 | input | TCELL61:IMUX.IMUX15 |
| TSTAPUC405EXECRO0 | output | TCELL30:OUT.HALF.BOT4.TMIN, TCELL30:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXECRO1 | output | TCELL30:OUT.HALF.BOT5.TMIN, TCELL30:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXECRO2 | output | TCELL30:OUT.HALF.BOT6.TMIN, TCELL30:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXECRO3 | output | TCELL30:OUT.HALF.BOT7.TMIN, TCELL30:OUT.HALT.TOP7.TMIN |
| TSTAPUC405EXELDDEPENDI | input | TCELL46:IMUX.IMUX5 |
| TSTAPUC405EXELDDEPENDO | output | TCELL28:OUT.HALF.BOT5.TMIN, TCELL28:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXENONBLOCKINGMCOI | input | TCELL45:IMUX.IMUX6 |
| TSTAPUC405EXENONBLOCKINGMCOO | output | TCELL28:OUT.HALF.BOT1.TMIN, TCELL28:OUT.HALT.TOP1.TMIN |
| TSTAPUC405EXERESULTI0 | input | TCELL61:IMUX.IMUX8 |
| TSTAPUC405EXERESULTI1 | input | TCELL61:IMUX.IMUX9 |
| TSTAPUC405EXERESULTI10 | input | TCELL59:IMUX.IMUX7 |
| TSTAPUC405EXERESULTI11 | input | TCELL59:IMUX.IMUX8 |
| TSTAPUC405EXERESULTI12 | input | TCELL58:IMUX.IMUX9 |
| TSTAPUC405EXERESULTI13 | input | TCELL58:IMUX.IMUX10 |
| TSTAPUC405EXERESULTI14 | input | TCELL58:IMUX.IMUX11 |
| TSTAPUC405EXERESULTI15 | input | TCELL58:IMUX.IMUX12 |
| TSTAPUC405EXERESULTI16 | input | TCELL57:IMUX.IMUX12 |
| TSTAPUC405EXERESULTI17 | input | TCELL57:IMUX.IMUX13 |
| TSTAPUC405EXERESULTI18 | input | TCELL57:IMUX.IMUX14 |
| TSTAPUC405EXERESULTI19 | input | TCELL57:IMUX.IMUX15 |
| TSTAPUC405EXERESULTI2 | input | TCELL61:IMUX.IMUX10 |
| TSTAPUC405EXERESULTI20 | input | TCELL56:IMUX.IMUX8 |
| TSTAPUC405EXERESULTI21 | input | TCELL56:IMUX.IMUX9 |
| TSTAPUC405EXERESULTI22 | input | TCELL56:IMUX.IMUX10 |
| TSTAPUC405EXERESULTI23 | input | TCELL56:IMUX.IMUX11 |
| TSTAPUC405EXERESULTI24 | input | TCELL56:IMUX.IMUX12 |
| TSTAPUC405EXERESULTI25 | input | TCELL56:IMUX.IMUX13 |
| TSTAPUC405EXERESULTI26 | input | TCELL56:IMUX.IMUX14 |
| TSTAPUC405EXERESULTI27 | input | TCELL56:IMUX.IMUX15 |
| TSTAPUC405EXERESULTI28 | input | TCELL55:IMUX.IMUX8 |
| TSTAPUC405EXERESULTI29 | input | TCELL55:IMUX.IMUX9 |
| TSTAPUC405EXERESULTI3 | input | TCELL61:IMUX.IMUX11 |
| TSTAPUC405EXERESULTI30 | input | TCELL55:IMUX.IMUX10 |
| TSTAPUC405EXERESULTI31 | input | TCELL55:IMUX.IMUX11 |
| TSTAPUC405EXERESULTI4 | input | TCELL60:IMUX.IMUX5 |
| TSTAPUC405EXERESULTI5 | input | TCELL60:IMUX.IMUX6 |
| TSTAPUC405EXERESULTI6 | input | TCELL60:IMUX.IMUX7 |
| TSTAPUC405EXERESULTI7 | input | TCELL60:IMUX.IMUX8 |
| TSTAPUC405EXERESULTI8 | input | TCELL59:IMUX.IMUX5 |
| TSTAPUC405EXERESULTI9 | input | TCELL59:IMUX.IMUX6 |
| TSTAPUC405EXERESULTO0 | output | TCELL35:OUT.HALF.BOT0.TMIN, TCELL35:OUT.HALT.TOP0.TMIN |
| TSTAPUC405EXERESULTO1 | output | TCELL35:OUT.HALF.BOT1.TMIN, TCELL35:OUT.HALT.TOP1.TMIN |
| TSTAPUC405EXERESULTO10 | output | TCELL34:OUT.HALF.BOT2.TMIN, TCELL34:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXERESULTO11 | output | TCELL34:OUT.HALF.BOT3.TMIN, TCELL34:OUT.HALT.TOP3.TMIN |
| TSTAPUC405EXERESULTO12 | output | TCELL34:OUT.HALF.BOT4.TMIN, TCELL34:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXERESULTO13 | output | TCELL34:OUT.HALF.BOT5.TMIN, TCELL34:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXERESULTO14 | output | TCELL34:OUT.HALF.BOT6.TMIN, TCELL34:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXERESULTO15 | output | TCELL34:OUT.HALF.BOT7.TMIN, TCELL34:OUT.HALT.TOP7.TMIN |
| TSTAPUC405EXERESULTO16 | output | TCELL33:OUT.HALF.BOT0.TMIN, TCELL33:OUT.HALT.TOP0.TMIN |
| TSTAPUC405EXERESULTO17 | output | TCELL33:OUT.HALF.BOT1.TMIN, TCELL33:OUT.HALT.TOP1.TMIN |
| TSTAPUC405EXERESULTO18 | output | TCELL33:OUT.HALF.BOT2.TMIN, TCELL33:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXERESULTO19 | output | TCELL33:OUT.HALF.BOT3.TMIN, TCELL33:OUT.HALT.TOP3.TMIN |
| TSTAPUC405EXERESULTO2 | output | TCELL35:OUT.HALF.BOT2.TMIN, TCELL35:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXERESULTO20 | output | TCELL33:OUT.HALF.BOT4.TMIN, TCELL33:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXERESULTO21 | output | TCELL33:OUT.HALF.BOT5.TMIN, TCELL33:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXERESULTO22 | output | TCELL33:OUT.HALF.BOT6.TMIN, TCELL33:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXERESULTO23 | output | TCELL33:OUT.HALF.BOT7.TMIN, TCELL33:OUT.HALT.TOP7.TMIN |
| TSTAPUC405EXERESULTO24 | output | TCELL32:OUT.HALF.BOT0.TMIN, TCELL32:OUT.HALT.TOP0.TMIN |
| TSTAPUC405EXERESULTO25 | output | TCELL32:OUT.HALF.BOT1.TMIN, TCELL32:OUT.HALT.TOP1.TMIN |
| TSTAPUC405EXERESULTO26 | output | TCELL32:OUT.HALF.BOT2.TMIN, TCELL32:OUT.HALT.TOP2.TMIN |
| TSTAPUC405EXERESULTO27 | output | TCELL32:OUT.HALF.BOT3.TMIN, TCELL32:OUT.HALT.TOP3.TMIN |
| TSTAPUC405EXERESULTO28 | output | TCELL32:OUT.HALF.BOT4.TMIN, TCELL32:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXERESULTO29 | output | TCELL32:OUT.HALF.BOT5.TMIN, TCELL32:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXERESULTO3 | output | TCELL35:OUT.HALF.BOT3.TMIN, TCELL35:OUT.HALT.TOP3.TMIN |
| TSTAPUC405EXERESULTO30 | output | TCELL32:OUT.HALF.BOT6.TMIN, TCELL32:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXERESULTO31 | output | TCELL32:OUT.HALF.BOT7.TMIN, TCELL32:OUT.HALT.TOP7.TMIN |
| TSTAPUC405EXERESULTO4 | output | TCELL35:OUT.HALF.BOT4.TMIN, TCELL35:OUT.HALT.TOP4.TMIN |
| TSTAPUC405EXERESULTO5 | output | TCELL35:OUT.HALF.BOT5.TMIN, TCELL35:OUT.HALT.TOP5.TMIN |
| TSTAPUC405EXERESULTO6 | output | TCELL35:OUT.HALF.BOT6.TMIN, TCELL35:OUT.HALT.TOP6.TMIN |
| TSTAPUC405EXERESULTO7 | output | TCELL35:OUT.HALF.BOT7.TMIN, TCELL35:OUT.HALT.TOP7.TMIN |
| TSTAPUC405EXERESULTO8 | output | TCELL34:OUT.HALF.BOT0.TMIN, TCELL34:OUT.HALT.TOP0.TMIN |
| TSTAPUC405EXERESULTO9 | output | TCELL34:OUT.HALF.BOT1.TMIN, TCELL34:OUT.HALT.TOP1.TMIN |
| TSTAPUC405EXEXERCAI | input | TCELL44:IMUX.IMUX10 |
| TSTAPUC405EXEXERCAO | output | TCELL28:OUT.HALF.BOT3.TMIN, TCELL28:OUT.HALT.TOP3.TMIN |
| TSTAPUC405EXEXEROVI | input | TCELL44:IMUX.IMUX11 |
| TSTAPUC405EXEXEROVO | output | TCELL28:OUT.SEC2.TMIN |
| TSTAPUC405FPUEXCEPTIONI | input | TCELL42:IMUX.IMUX7 |
| TSTAPUC405FPUEXCEPTIONO | output | TCELL36:OUT.HALF.BOT0.TMIN, TCELL36:OUT.HALT.TOP0.TMIN |
| TSTAPUC405LWBLDDEPENDI | input | TCELL46:IMUX.IMUX7 |
| TSTAPUC405LWBLDDEPENDO | output | TCELL28:OUT.HALF.BOT7.TMIN, TCELL28:OUT.HALT.TOP7.TMIN |
| TSTAPUC405SLEEPREQI | input | TCELL46:IMUX.IMUX4 |
| TSTAPUC405SLEEPREQO | output | TCELL29:OUT.HALF.BOT6.TMIN, TCELL29:OUT.HALT.TOP6.TMIN |
| TSTAPUC405WBLDDEPENDI | input | TCELL46:IMUX.IMUX6 |
| TSTAPUC405WBLDDEPENDO | output | TCELL28:OUT.HALF.BOT6.TMIN, TCELL28:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDFULLI | input | TCELL45:IMUX.IMUX8 |
| TSTC405APUDCDFULLO | output | TCELL5:OUT.HALF.BOT3.TMIN, TCELL5:OUT.HALT.TOP3.TMIN |
| TSTC405APUDCDHOLDI | input | TCELL45:IMUX.IMUX9 |
| TSTC405APUDCDHOLDO | output | TCELL37:OUT.HALF.BOT6.TMIN, TCELL37:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONI0 | input | TCELL38:IMUX.IMUX13 |
| TSTC405APUDCDINSTRUCTIONI1 | input | TCELL38:IMUX.IMUX14 |
| TSTC405APUDCDINSTRUCTIONI10 | input | TCELL37:IMUX.IMUX14 |
| TSTC405APUDCDINSTRUCTIONI11 | input | TCELL37:IMUX.IMUX15 |
| TSTC405APUDCDINSTRUCTIONI12 | input | TCELL36:IMUX.IMUX8 |
| TSTC405APUDCDINSTRUCTIONI13 | input | TCELL36:IMUX.IMUX9 |
| TSTC405APUDCDINSTRUCTIONI14 | input | TCELL36:IMUX.IMUX10 |
| TSTC405APUDCDINSTRUCTIONI15 | input | TCELL36:IMUX.IMUX11 |
| TSTC405APUDCDINSTRUCTIONI16 | input | TCELL35:IMUX.IMUX8 |
| TSTC405APUDCDINSTRUCTIONI17 | input | TCELL35:IMUX.IMUX9 |
| TSTC405APUDCDINSTRUCTIONI18 | input | TCELL35:IMUX.IMUX10 |
| TSTC405APUDCDINSTRUCTIONI19 | input | TCELL35:IMUX.IMUX11 |
| TSTC405APUDCDINSTRUCTIONI2 | input | TCELL38:IMUX.IMUX15 |
| TSTC405APUDCDINSTRUCTIONI20 | input | TCELL34:IMUX.IMUX9 |
| TSTC405APUDCDINSTRUCTIONI21 | input | TCELL34:IMUX.IMUX10 |
| TSTC405APUDCDINSTRUCTIONI22 | input | TCELL34:IMUX.IMUX11 |
| TSTC405APUDCDINSTRUCTIONI23 | input | TCELL34:IMUX.IMUX12 |
| TSTC405APUDCDINSTRUCTIONI24 | input | TCELL33:IMUX.IMUX12 |
| TSTC405APUDCDINSTRUCTIONI25 | input | TCELL33:IMUX.IMUX13 |
| TSTC405APUDCDINSTRUCTIONI26 | input | TCELL33:IMUX.IMUX14 |
| TSTC405APUDCDINSTRUCTIONI27 | input | TCELL33:IMUX.IMUX15 |
| TSTC405APUDCDINSTRUCTIONI28 | input | TCELL32:IMUX.IMUX12 |
| TSTC405APUDCDINSTRUCTIONI29 | input | TCELL32:IMUX.IMUX13 |
| TSTC405APUDCDINSTRUCTIONI3 | input | TCELL38:IMUX.IMUX16 |
| TSTC405APUDCDINSTRUCTIONI30 | input | TCELL32:IMUX.IMUX14 |
| TSTC405APUDCDINSTRUCTIONI31 | input | TCELL32:IMUX.IMUX15 |
| TSTC405APUDCDINSTRUCTIONI4 | input | TCELL37:IMUX.IMUX8 |
| TSTC405APUDCDINSTRUCTIONI5 | input | TCELL37:IMUX.IMUX9 |
| TSTC405APUDCDINSTRUCTIONI6 | input | TCELL37:IMUX.IMUX10 |
| TSTC405APUDCDINSTRUCTIONI7 | input | TCELL37:IMUX.IMUX11 |
| TSTC405APUDCDINSTRUCTIONI8 | input | TCELL37:IMUX.IMUX12 |
| TSTC405APUDCDINSTRUCTIONI9 | input | TCELL37:IMUX.IMUX13 |
| TSTC405APUDCDINSTRUCTIONO0 | output | TCELL61:OUT.HALF.BOT4.TMIN, TCELL61:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO1 | output | TCELL61:OUT.HALF.BOT5.TMIN, TCELL61:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO10 | output | TCELL59:OUT.HALF.BOT6.TMIN, TCELL59:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO11 | output | TCELL59:OUT.HALF.BOT7.TMIN, TCELL59:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO12 | output | TCELL58:OUT.HALF.BOT4.TMIN, TCELL58:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO13 | output | TCELL58:OUT.HALF.BOT5.TMIN, TCELL58:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO14 | output | TCELL58:OUT.HALF.BOT6.TMIN, TCELL58:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO15 | output | TCELL58:OUT.HALF.BOT7.TMIN, TCELL58:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO16 | output | TCELL57:OUT.HALF.BOT4.TMIN, TCELL57:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO17 | output | TCELL57:OUT.HALF.BOT5.TMIN, TCELL57:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO18 | output | TCELL57:OUT.HALF.BOT6.TMIN, TCELL57:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO19 | output | TCELL57:OUT.HALF.BOT7.TMIN, TCELL57:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO2 | output | TCELL61:OUT.HALF.BOT6.TMIN, TCELL61:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO20 | output | TCELL56:OUT.HALF.BOT4.TMIN, TCELL56:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO21 | output | TCELL56:OUT.HALF.BOT5.TMIN, TCELL56:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO22 | output | TCELL56:OUT.HALF.BOT6.TMIN, TCELL56:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO23 | output | TCELL56:OUT.HALF.BOT7.TMIN, TCELL56:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO24 | output | TCELL55:OUT.HALF.BOT4.TMIN, TCELL55:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO25 | output | TCELL55:OUT.HALF.BOT5.TMIN, TCELL55:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO26 | output | TCELL55:OUT.HALF.BOT6.TMIN, TCELL55:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO27 | output | TCELL55:OUT.HALF.BOT7.TMIN, TCELL55:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO28 | output | TCELL38:OUT.HALF.BOT4.TMIN, TCELL38:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO29 | output | TCELL38:OUT.HALF.BOT5.TMIN, TCELL38:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO3 | output | TCELL61:OUT.HALF.BOT7.TMIN, TCELL61:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO30 | output | TCELL38:OUT.HALF.BOT6.TMIN, TCELL38:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO31 | output | TCELL38:OUT.HALF.BOT7.TMIN, TCELL38:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO4 | output | TCELL60:OUT.HALF.BOT4.TMIN, TCELL60:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO5 | output | TCELL60:OUT.HALF.BOT5.TMIN, TCELL60:OUT.HALT.TOP5.TMIN |
| TSTC405APUDCDINSTRUCTIONO6 | output | TCELL60:OUT.HALF.BOT6.TMIN, TCELL60:OUT.HALT.TOP6.TMIN |
| TSTC405APUDCDINSTRUCTIONO7 | output | TCELL60:OUT.HALF.BOT7.TMIN, TCELL60:OUT.HALT.TOP7.TMIN |
| TSTC405APUDCDINSTRUCTIONO8 | output | TCELL59:OUT.HALF.BOT4.TMIN, TCELL59:OUT.HALT.TOP4.TMIN |
| TSTC405APUDCDINSTRUCTIONO9 | output | TCELL59:OUT.HALF.BOT5.TMIN, TCELL59:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXEFLUSHI | input | TCELL45:IMUX.IMUX10 |
| TSTC405APUEXEFLUSHO | output | TCELL36:OUT.SEC2.TMIN |
| TSTC405APUEXEHOLDI | input | TCELL45:IMUX.IMUX11 |
| TSTC405APUEXEHOLDO | output | TCELL37:OUT.HALF.BOT5.TMIN, TCELL37:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXELOADDBUSI0 | input | TCELL31:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI1 | input | TCELL31:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSI10 | input | TCELL29:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI11 | input | TCELL29:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI12 | input | TCELL28:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI13 | input | TCELL28:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSI14 | input | TCELL28:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI15 | input | TCELL28:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI16 | input | TCELL27:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI17 | input | TCELL27:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSI18 | input | TCELL27:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI19 | input | TCELL27:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI2 | input | TCELL31:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI20 | input | TCELL26:IMUX.IMUX8 |
| TSTC405APUEXELOADDBUSI21 | input | TCELL26:IMUX.IMUX9 |
| TSTC405APUEXELOADDBUSI22 | input | TCELL26:IMUX.IMUX10 |
| TSTC405APUEXELOADDBUSI23 | input | TCELL26:IMUX.IMUX11 |
| TSTC405APUEXELOADDBUSI24 | input | TCELL26:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI25 | input | TCELL26:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSI26 | input | TCELL26:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI27 | input | TCELL26:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI28 | input | TCELL25:IMUX.IMUX16 |
| TSTC405APUEXELOADDBUSI29 | input | TCELL25:IMUX.IMUX17 |
| TSTC405APUEXELOADDBUSI3 | input | TCELL31:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI30 | input | TCELL25:IMUX.IMUX18 |
| TSTC405APUEXELOADDBUSI31 | input | TCELL25:IMUX.IMUX19 |
| TSTC405APUEXELOADDBUSI4 | input | TCELL30:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI5 | input | TCELL30:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSI6 | input | TCELL30:IMUX.IMUX14 |
| TSTC405APUEXELOADDBUSI7 | input | TCELL30:IMUX.IMUX15 |
| TSTC405APUEXELOADDBUSI8 | input | TCELL29:IMUX.IMUX12 |
| TSTC405APUEXELOADDBUSI9 | input | TCELL29:IMUX.IMUX13 |
| TSTC405APUEXELOADDBUSO0 | output | TCELL43:OUT.HALF.BOT0.TMIN, TCELL43:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXELOADDBUSO1 | output | TCELL43:OUT.HALF.BOT1.TMIN, TCELL43:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXELOADDBUSO10 | output | TCELL42:OUT.HALF.BOT2.TMIN, TCELL42:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXELOADDBUSO11 | output | TCELL42:OUT.HALF.BOT3.TMIN, TCELL42:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXELOADDBUSO12 | output | TCELL42:OUT.HALF.BOT4.TMIN, TCELL42:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXELOADDBUSO13 | output | TCELL42:OUT.HALF.BOT5.TMIN, TCELL42:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXELOADDBUSO14 | output | TCELL42:OUT.HALF.BOT6.TMIN, TCELL42:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXELOADDBUSO15 | output | TCELL42:OUT.HALF.BOT7.TMIN, TCELL42:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXELOADDBUSO16 | output | TCELL41:OUT.HALF.BOT0.TMIN, TCELL41:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXELOADDBUSO17 | output | TCELL41:OUT.HALF.BOT1.TMIN, TCELL41:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXELOADDBUSO18 | output | TCELL41:OUT.HALF.BOT2.TMIN, TCELL41:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXELOADDBUSO19 | output | TCELL41:OUT.HALF.BOT3.TMIN, TCELL41:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXELOADDBUSO2 | output | TCELL43:OUT.HALF.BOT2.TMIN, TCELL43:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXELOADDBUSO20 | output | TCELL41:OUT.HALF.BOT4.TMIN, TCELL41:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXELOADDBUSO21 | output | TCELL41:OUT.HALF.BOT5.TMIN, TCELL41:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXELOADDBUSO22 | output | TCELL41:OUT.HALF.BOT6.TMIN, TCELL41:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXELOADDBUSO23 | output | TCELL41:OUT.HALF.BOT7.TMIN, TCELL41:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXELOADDBUSO24 | output | TCELL40:OUT.HALF.BOT0.TMIN, TCELL40:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXELOADDBUSO25 | output | TCELL40:OUT.HALF.BOT1.TMIN, TCELL40:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXELOADDBUSO26 | output | TCELL40:OUT.HALF.BOT2.TMIN, TCELL40:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXELOADDBUSO27 | output | TCELL40:OUT.HALF.BOT3.TMIN, TCELL40:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXELOADDBUSO28 | output | TCELL40:OUT.HALF.BOT4.TMIN, TCELL40:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXELOADDBUSO29 | output | TCELL40:OUT.HALF.BOT5.TMIN, TCELL40:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXELOADDBUSO3 | output | TCELL43:OUT.HALF.BOT3.TMIN, TCELL43:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXELOADDBUSO30 | output | TCELL40:OUT.HALF.BOT6.TMIN, TCELL40:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXELOADDBUSO31 | output | TCELL40:OUT.HALF.BOT7.TMIN, TCELL40:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXELOADDBUSO4 | output | TCELL43:OUT.HALF.BOT4.TMIN, TCELL43:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXELOADDBUSO5 | output | TCELL43:OUT.HALF.BOT5.TMIN, TCELL43:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXELOADDBUSO6 | output | TCELL43:OUT.HALF.BOT6.TMIN, TCELL43:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXELOADDBUSO7 | output | TCELL43:OUT.HALF.BOT7.TMIN, TCELL43:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXELOADDBUSO8 | output | TCELL42:OUT.HALF.BOT0.TMIN, TCELL42:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXELOADDBUSO9 | output | TCELL42:OUT.HALF.BOT1.TMIN, TCELL42:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXELOADDVALIDI | input | TCELL46:IMUX.IMUX8 |
| TSTC405APUEXELOADDVALIDO | output | TCELL36:OUT.SEC1.TMIN |
| TSTC405APUEXERADATAI0 | input | TCELL38:IMUX.IMUX5 |
| TSTC405APUEXERADATAI1 | input | TCELL38:IMUX.IMUX6 |
| TSTC405APUEXERADATAI10 | input | TCELL37:IMUX.IMUX18 |
| TSTC405APUEXERADATAI11 | input | TCELL37:IMUX.IMUX19 |
| TSTC405APUEXERADATAI12 | input | TCELL36:IMUX.IMUX16 |
| TSTC405APUEXERADATAI13 | input | TCELL36:IMUX.IMUX17 |
| TSTC405APUEXERADATAI14 | input | TCELL36:IMUX.IMUX18 |
| TSTC405APUEXERADATAI15 | input | TCELL36:IMUX.IMUX19 |
| TSTC405APUEXERADATAI16 | input | TCELL35:IMUX.IMUX16 |
| TSTC405APUEXERADATAI17 | input | TCELL35:IMUX.IMUX17 |
| TSTC405APUEXERADATAI18 | input | TCELL35:IMUX.IMUX18 |
| TSTC405APUEXERADATAI19 | input | TCELL35:IMUX.IMUX19 |
| TSTC405APUEXERADATAI2 | input | TCELL38:IMUX.IMUX7 |
| TSTC405APUEXERADATAI20 | input | TCELL34:IMUX.IMUX13 |
| TSTC405APUEXERADATAI21 | input | TCELL34:IMUX.IMUX14 |
| TSTC405APUEXERADATAI22 | input | TCELL34:IMUX.IMUX15 |
| TSTC405APUEXERADATAI23 | input | TCELL34:IMUX.IMUX16 |
| TSTC405APUEXERADATAI24 | input | TCELL33:IMUX.IMUX16 |
| TSTC405APUEXERADATAI25 | input | TCELL33:IMUX.IMUX17 |
| TSTC405APUEXERADATAI26 | input | TCELL33:IMUX.IMUX18 |
| TSTC405APUEXERADATAI27 | input | TCELL33:IMUX.IMUX19 |
| TSTC405APUEXERADATAI28 | input | TCELL32:IMUX.IMUX16 |
| TSTC405APUEXERADATAI29 | input | TCELL32:IMUX.IMUX17 |
| TSTC405APUEXERADATAI3 | input | TCELL38:IMUX.IMUX8 |
| TSTC405APUEXERADATAI30 | input | TCELL32:IMUX.IMUX18 |
| TSTC405APUEXERADATAI31 | input | TCELL32:IMUX.IMUX19 |
| TSTC405APUEXERADATAI4 | input | TCELL38:IMUX.IMUX9 |
| TSTC405APUEXERADATAI5 | input | TCELL38:IMUX.IMUX10 |
| TSTC405APUEXERADATAI6 | input | TCELL38:IMUX.IMUX11 |
| TSTC405APUEXERADATAI7 | input | TCELL38:IMUX.IMUX12 |
| TSTC405APUEXERADATAI8 | input | TCELL37:IMUX.IMUX16 |
| TSTC405APUEXERADATAI9 | input | TCELL37:IMUX.IMUX17 |
| TSTC405APUEXERADATAO0 | output | TCELL61:OUT.HALF.BOT0.TMIN, TCELL61:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO1 | output | TCELL61:OUT.HALF.BOT1.TMIN, TCELL61:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO10 | output | TCELL59:OUT.HALF.BOT2.TMIN, TCELL59:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO11 | output | TCELL59:OUT.HALF.BOT3.TMIN, TCELL59:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO12 | output | TCELL58:OUT.HALF.BOT0.TMIN, TCELL58:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO13 | output | TCELL58:OUT.HALF.BOT1.TMIN, TCELL58:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO14 | output | TCELL58:OUT.HALF.BOT2.TMIN, TCELL58:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO15 | output | TCELL58:OUT.HALF.BOT3.TMIN, TCELL58:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO16 | output | TCELL57:OUT.HALF.BOT0.TMIN, TCELL57:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO17 | output | TCELL57:OUT.HALF.BOT1.TMIN, TCELL57:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO18 | output | TCELL57:OUT.HALF.BOT2.TMIN, TCELL57:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO19 | output | TCELL57:OUT.HALF.BOT3.TMIN, TCELL57:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO2 | output | TCELL61:OUT.HALF.BOT2.TMIN, TCELL61:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO20 | output | TCELL56:OUT.HALF.BOT0.TMIN, TCELL56:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO21 | output | TCELL56:OUT.HALF.BOT1.TMIN, TCELL56:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO22 | output | TCELL56:OUT.HALF.BOT2.TMIN, TCELL56:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO23 | output | TCELL56:OUT.HALF.BOT3.TMIN, TCELL56:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO24 | output | TCELL55:OUT.HALF.BOT0.TMIN, TCELL55:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO25 | output | TCELL55:OUT.HALF.BOT1.TMIN, TCELL55:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO26 | output | TCELL55:OUT.HALF.BOT2.TMIN, TCELL55:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO27 | output | TCELL55:OUT.HALF.BOT3.TMIN, TCELL55:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO28 | output | TCELL38:OUT.HALF.BOT0.TMIN, TCELL38:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO29 | output | TCELL38:OUT.HALF.BOT1.TMIN, TCELL38:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO3 | output | TCELL61:OUT.HALF.BOT3.TMIN, TCELL61:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO30 | output | TCELL38:OUT.HALF.BOT2.TMIN, TCELL38:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO31 | output | TCELL38:OUT.HALF.BOT3.TMIN, TCELL38:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO4 | output | TCELL60:OUT.HALF.BOT0.TMIN, TCELL60:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO5 | output | TCELL60:OUT.HALF.BOT1.TMIN, TCELL60:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERADATAO6 | output | TCELL60:OUT.HALF.BOT2.TMIN, TCELL60:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERADATAO7 | output | TCELL60:OUT.HALF.BOT3.TMIN, TCELL60:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERADATAO8 | output | TCELL59:OUT.HALF.BOT0.TMIN, TCELL59:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERADATAO9 | output | TCELL59:OUT.HALF.BOT1.TMIN, TCELL59:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERBDATAI0 | input | TCELL31:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI1 | input | TCELL31:IMUX.IMUX17 |
| TSTC405APUEXERBDATAI10 | input | TCELL29:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI11 | input | TCELL29:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI12 | input | TCELL28:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI13 | input | TCELL28:IMUX.IMUX17 |
| TSTC405APUEXERBDATAI14 | input | TCELL28:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI15 | input | TCELL28:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI16 | input | TCELL27:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI17 | input | TCELL27:IMUX.IMUX17 |
| TSTC405APUEXERBDATAI18 | input | TCELL27:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI19 | input | TCELL27:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI2 | input | TCELL31:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI20 | input | TCELL26:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI21 | input | TCELL26:IMUX.IMUX17 |
| TSTC405APUEXERBDATAI22 | input | TCELL26:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI23 | input | TCELL26:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI24 | input | TCELL25:IMUX.IMUX8 |
| TSTC405APUEXERBDATAI25 | input | TCELL25:IMUX.IMUX9 |
| TSTC405APUEXERBDATAI26 | input | TCELL25:IMUX.IMUX10 |
| TSTC405APUEXERBDATAI27 | input | TCELL25:IMUX.IMUX11 |
| TSTC405APUEXERBDATAI28 | input | TCELL25:IMUX.IMUX12 |
| TSTC405APUEXERBDATAI29 | input | TCELL25:IMUX.IMUX13 |
| TSTC405APUEXERBDATAI3 | input | TCELL31:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI30 | input | TCELL25:IMUX.IMUX14 |
| TSTC405APUEXERBDATAI31 | input | TCELL25:IMUX.IMUX15 |
| TSTC405APUEXERBDATAI4 | input | TCELL30:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI5 | input | TCELL30:IMUX.IMUX17 |
| TSTC405APUEXERBDATAI6 | input | TCELL30:IMUX.IMUX18 |
| TSTC405APUEXERBDATAI7 | input | TCELL30:IMUX.IMUX19 |
| TSTC405APUEXERBDATAI8 | input | TCELL29:IMUX.IMUX16 |
| TSTC405APUEXERBDATAI9 | input | TCELL29:IMUX.IMUX17 |
| TSTC405APUEXERBDATAO0 | output | TCELL47:OUT.HALF.BOT0.TMIN, TCELL47:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERBDATAO1 | output | TCELL47:OUT.HALF.BOT1.TMIN, TCELL47:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERBDATAO10 | output | TCELL46:OUT.HALF.BOT2.TMIN, TCELL46:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERBDATAO11 | output | TCELL46:OUT.HALF.BOT3.TMIN, TCELL46:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERBDATAO12 | output | TCELL46:OUT.HALF.BOT4.TMIN, TCELL46:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXERBDATAO13 | output | TCELL46:OUT.HALF.BOT5.TMIN, TCELL46:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXERBDATAO14 | output | TCELL46:OUT.HALF.BOT6.TMIN, TCELL46:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXERBDATAO15 | output | TCELL46:OUT.HALF.BOT7.TMIN, TCELL46:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXERBDATAO16 | output | TCELL45:OUT.HALF.BOT0.TMIN, TCELL45:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERBDATAO17 | output | TCELL45:OUT.HALF.BOT1.TMIN, TCELL45:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERBDATAO18 | output | TCELL45:OUT.HALF.BOT2.TMIN, TCELL45:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERBDATAO19 | output | TCELL45:OUT.HALF.BOT3.TMIN, TCELL45:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERBDATAO2 | output | TCELL47:OUT.HALF.BOT2.TMIN, TCELL47:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERBDATAO20 | output | TCELL45:OUT.HALF.BOT4.TMIN, TCELL45:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXERBDATAO21 | output | TCELL45:OUT.HALF.BOT5.TMIN, TCELL45:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXERBDATAO22 | output | TCELL45:OUT.HALF.BOT6.TMIN, TCELL45:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXERBDATAO23 | output | TCELL45:OUT.HALF.BOT7.TMIN, TCELL45:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXERBDATAO24 | output | TCELL44:OUT.HALF.BOT0.TMIN, TCELL44:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERBDATAO25 | output | TCELL44:OUT.HALF.BOT1.TMIN, TCELL44:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXERBDATAO26 | output | TCELL44:OUT.HALF.BOT2.TMIN, TCELL44:OUT.HALT.TOP2.TMIN |
| TSTC405APUEXERBDATAO27 | output | TCELL44:OUT.HALF.BOT3.TMIN, TCELL44:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERBDATAO28 | output | TCELL44:OUT.HALF.BOT4.TMIN, TCELL44:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXERBDATAO29 | output | TCELL44:OUT.HALF.BOT5.TMIN, TCELL44:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXERBDATAO3 | output | TCELL47:OUT.HALF.BOT3.TMIN, TCELL47:OUT.HALT.TOP3.TMIN |
| TSTC405APUEXERBDATAO30 | output | TCELL44:OUT.HALF.BOT6.TMIN, TCELL44:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXERBDATAO31 | output | TCELL44:OUT.HALF.BOT7.TMIN, TCELL44:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXERBDATAO4 | output | TCELL47:OUT.HALF.BOT4.TMIN, TCELL47:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXERBDATAO5 | output | TCELL47:OUT.HALF.BOT5.TMIN, TCELL47:OUT.HALT.TOP5.TMIN |
| TSTC405APUEXERBDATAO6 | output | TCELL47:OUT.HALF.BOT6.TMIN, TCELL47:OUT.HALT.TOP6.TMIN |
| TSTC405APUEXERBDATAO7 | output | TCELL47:OUT.HALF.BOT7.TMIN, TCELL47:OUT.HALT.TOP7.TMIN |
| TSTC405APUEXERBDATAO8 | output | TCELL46:OUT.HALF.BOT0.TMIN, TCELL46:OUT.HALT.TOP0.TMIN |
| TSTC405APUEXERBDATAO9 | output | TCELL46:OUT.HALF.BOT1.TMIN, TCELL46:OUT.HALT.TOP1.TMIN |
| TSTC405APUEXEWDCNTI0 | input | TCELL47:IMUX.IMUX8 |
| TSTC405APUEXEWDCNTI1 | input | TCELL47:IMUX.IMUX9 |
| TSTC405APUEXEWDCNTO0 | output | TCELL7:OUT.HALF.BOT4.TMIN, TCELL7:OUT.HALT.TOP4.TMIN |
| TSTC405APUEXEWDCNTO1 | output | TCELL7:OUT.HALF.BOT5.TMIN, TCELL7:OUT.HALT.TOP5.TMIN |
| TSTC405APUMSRFE0I | input | TCELL47:IMUX.IMUX10 |
| TSTC405APUMSRFE0O | output | TCELL7:OUT.HALF.BOT6.TMIN, TCELL7:OUT.HALT.TOP6.TMIN |
| TSTC405APUMSRFE1I | input | TCELL47:IMUX.IMUX11 |
| TSTC405APUMSRFE1O | output | TCELL7:OUT.HALF.BOT7.TMIN, TCELL7:OUT.HALT.TOP7.TMIN |
| TSTC405APUWBBYTEENI0 | input | TCELL24:IMUX.IMUX10 |
| TSTC405APUWBBYTEENI1 | input | TCELL24:IMUX.IMUX11 |
| TSTC405APUWBBYTEENI2 | input | TCELL24:IMUX.IMUX12 |
| TSTC405APUWBBYTEENI3 | input | TCELL24:IMUX.IMUX13 |
| TSTC405APUWBBYTEENO0 | output | TCELL3:OUT.HALF.BOT0.TMIN, TCELL3:OUT.HALT.TOP0.TMIN |
| TSTC405APUWBBYTEENO1 | output | TCELL3:OUT.HALF.BOT1.TMIN, TCELL3:OUT.HALT.TOP1.TMIN |
| TSTC405APUWBBYTEENO2 | output | TCELL3:OUT.HALF.BOT2.TMIN, TCELL3:OUT.HALT.TOP2.TMIN |
| TSTC405APUWBBYTEENO3 | output | TCELL3:OUT.HALF.BOT3.TMIN, TCELL3:OUT.HALT.TOP3.TMIN |
| TSTC405APUWBENDIANI | input | TCELL46:IMUX.IMUX9 |
| TSTC405APUWBENDIANO | output | TCELL36:OUT.SEC0.TMIN |
| TSTC405APUWBFLUSHI | input | TCELL46:IMUX.IMUX10 |
| TSTC405APUWBFLUSHO | output | TCELL5:OUT.HALF.BOT1.TMIN, TCELL5:OUT.HALT.TOP1.TMIN |
| TSTC405APUWBHOLDI | input | TCELL46:IMUX.IMUX11 |
| TSTC405APUWBHOLDO | output | TCELL5:OUT.HALF.BOT2.TMIN, TCELL5:OUT.HALT.TOP2.TMIN |
| TSTC405APUXERCAI | input | TCELL44:IMUX.IMUX5 |
| TSTC405APUXERCAO | output | TCELL37:OUT.HALF.BOT7.TMIN, TCELL37:OUT.HALT.TOP7.TMIN |
| TSTC405DCRABUSI0 | input | TCELL27:IMUX.IMUX8 |
| TSTC405DCRABUSI1 | input | TCELL27:IMUX.IMUX9 |
| TSTC405DCRABUSI2 | input | TCELL27:IMUX.IMUX10 |
| TSTC405DCRABUSI3 | input | TCELL27:IMUX.IMUX11 |
| TSTC405DCRABUSI4 | input | TCELL28:IMUX.IMUX8 |
| TSTC405DCRABUSI5 | input | TCELL28:IMUX.IMUX9 |
| TSTC405DCRABUSI6 | input | TCELL28:IMUX.IMUX10 |
| TSTC405DCRABUSI7 | input | TCELL28:IMUX.IMUX11 |
| TSTC405DCRABUSI8 | input | TCELL29:IMUX.IMUX8 |
| TSTC405DCRABUSI9 | input | TCELL29:IMUX.IMUX9 |
| TSTC405DCRDBUSOUTI0 | input | TCELL46:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI1 | input | TCELL46:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI10 | input | TCELL44:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI11 | input | TCELL44:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI12 | input | TCELL42:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI13 | input | TCELL42:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI14 | input | TCELL42:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI15 | input | TCELL42:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI16 | input | TCELL41:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI17 | input | TCELL41:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI18 | input | TCELL41:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI19 | input | TCELL41:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI2 | input | TCELL46:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI20 | input | TCELL40:IMUX.IMUX16 |
| TSTC405DCRDBUSOUTI21 | input | TCELL40:IMUX.IMUX17 |
| TSTC405DCRDBUSOUTI22 | input | TCELL40:IMUX.IMUX18 |
| TSTC405DCRDBUSOUTI23 | input | TCELL40:IMUX.IMUX19 |
| TSTC405DCRDBUSOUTI24 | input | TCELL36:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI25 | input | TCELL36:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI26 | input | TCELL36:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI27 | input | TCELL36:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI28 | input | TCELL35:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI29 | input | TCELL35:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI3 | input | TCELL46:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI30 | input | TCELL35:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI31 | input | TCELL35:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI4 | input | TCELL45:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI5 | input | TCELL45:IMUX.IMUX13 |
| TSTC405DCRDBUSOUTI6 | input | TCELL45:IMUX.IMUX14 |
| TSTC405DCRDBUSOUTI7 | input | TCELL45:IMUX.IMUX15 |
| TSTC405DCRDBUSOUTI8 | input | TCELL44:IMUX.IMUX12 |
| TSTC405DCRDBUSOUTI9 | input | TCELL44:IMUX.IMUX13 |
| TSTC405DCRREADI | input | TCELL29:IMUX.IMUX10 |
| TSTC405DCRWRITEI | input | TCELL29:IMUX.IMUX11 |
| TSTC405DSOCMABORTOPI | input | TCELL39:IMUX.IMUX15 |
| TSTC405DSOCMABORTOPO | output | TCELL6:OUT.HALF.BOT5.TMIN, TCELL6:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMABORTREQI | input | TCELL39:IMUX.IMUX14 |
| TSTC405DSOCMABORTREQO | output | TCELL6:OUT.HALF.BOT6.TMIN, TCELL6:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMABUSI0 | input | TCELL14:IMUX.IMUX11 |
| TSTC405DSOCMABUSI1 | input | TCELL14:IMUX.IMUX12 |
| TSTC405DSOCMABUSI10 | input | TCELL12:IMUX.IMUX10 |
| TSTC405DSOCMABUSI11 | input | TCELL12:IMUX.IMUX11 |
| TSTC405DSOCMABUSI12 | input | TCELL11:IMUX.IMUX5 |
| TSTC405DSOCMABUSI13 | input | TCELL11:IMUX.IMUX6 |
| TSTC405DSOCMABUSI14 | input | TCELL11:IMUX.IMUX7 |
| TSTC405DSOCMABUSI15 | input | TCELL11:IMUX.IMUX8 |
| TSTC405DSOCMABUSI16 | input | TCELL43:IMUX.IMUX8 |
| TSTC405DSOCMABUSI17 | input | TCELL43:IMUX.IMUX9 |
| TSTC405DSOCMABUSI18 | input | TCELL43:IMUX.IMUX10 |
| TSTC405DSOCMABUSI19 | input | TCELL43:IMUX.IMUX11 |
| TSTC405DSOCMABUSI2 | input | TCELL14:IMUX.IMUX13 |
| TSTC405DSOCMABUSI20 | input | TCELL42:IMUX.IMUX8 |
| TSTC405DSOCMABUSI21 | input | TCELL42:IMUX.IMUX9 |
| TSTC405DSOCMABUSI22 | input | TCELL42:IMUX.IMUX10 |
| TSTC405DSOCMABUSI23 | input | TCELL42:IMUX.IMUX11 |
| TSTC405DSOCMABUSI24 | input | TCELL41:IMUX.IMUX8 |
| TSTC405DSOCMABUSI25 | input | TCELL41:IMUX.IMUX9 |
| TSTC405DSOCMABUSI26 | input | TCELL41:IMUX.IMUX10 |
| TSTC405DSOCMABUSI27 | input | TCELL41:IMUX.IMUX11 |
| TSTC405DSOCMABUSI28 | input | TCELL39:IMUX.IMUX8 |
| TSTC405DSOCMABUSI29 | input | TCELL39:IMUX.IMUX9 |
| TSTC405DSOCMABUSI3 | input | TCELL14:IMUX.IMUX14 |
| TSTC405DSOCMABUSI4 | input | TCELL13:IMUX.IMUX8 |
| TSTC405DSOCMABUSI5 | input | TCELL13:IMUX.IMUX9 |
| TSTC405DSOCMABUSI6 | input | TCELL13:IMUX.IMUX10 |
| TSTC405DSOCMABUSI7 | input | TCELL13:IMUX.IMUX11 |
| TSTC405DSOCMABUSI8 | input | TCELL12:IMUX.IMUX8 |
| TSTC405DSOCMABUSI9 | input | TCELL12:IMUX.IMUX9 |
| TSTC405DSOCMABUSO0 | output | TCELL23:OUT.HALF.BOT0.TMIN, TCELL23:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO1 | output | TCELL23:OUT.HALF.BOT1.TMIN, TCELL23:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO10 | output | TCELL21:OUT.HALF.BOT2.TMIN, TCELL21:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO11 | output | TCELL21:OUT.HALF.BOT3.TMIN, TCELL21:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO12 | output | TCELL20:OUT.HALF.BOT0.TMIN, TCELL20:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO13 | output | TCELL20:OUT.HALF.BOT1.TMIN, TCELL20:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO14 | output | TCELL20:OUT.HALF.BOT2.TMIN, TCELL20:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO15 | output | TCELL20:OUT.HALF.BOT3.TMIN, TCELL20:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO16 | output | TCELL19:OUT.HALF.BOT0.TMIN, TCELL19:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO17 | output | TCELL19:OUT.HALF.BOT1.TMIN, TCELL19:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO18 | output | TCELL19:OUT.HALF.BOT2.TMIN, TCELL19:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO19 | output | TCELL19:OUT.HALF.BOT3.TMIN, TCELL19:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO2 | output | TCELL23:OUT.HALF.BOT2.TMIN, TCELL23:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO20 | output | TCELL18:OUT.HALF.BOT0.TMIN, TCELL18:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO21 | output | TCELL18:OUT.HALF.BOT1.TMIN, TCELL18:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO22 | output | TCELL18:OUT.HALF.BOT2.TMIN, TCELL18:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO23 | output | TCELL18:OUT.HALF.BOT3.TMIN, TCELL18:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO24 | output | TCELL17:OUT.HALF.BOT0.TMIN, TCELL17:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO25 | output | TCELL17:OUT.HALF.BOT1.TMIN, TCELL17:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO26 | output | TCELL17:OUT.HALF.BOT2.TMIN, TCELL17:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO27 | output | TCELL17:OUT.HALF.BOT3.TMIN, TCELL17:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO28 | output | TCELL16:OUT.HALF.BOT0.TMIN, TCELL16:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO29 | output | TCELL16:OUT.HALF.BOT1.TMIN, TCELL16:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO3 | output | TCELL23:OUT.HALF.BOT3.TMIN, TCELL23:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO4 | output | TCELL22:OUT.HALF.BOT0.TMIN, TCELL22:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO5 | output | TCELL22:OUT.HALF.BOT1.TMIN, TCELL22:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMABUSO6 | output | TCELL22:OUT.HALF.BOT2.TMIN, TCELL22:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMABUSO7 | output | TCELL22:OUT.HALF.BOT3.TMIN, TCELL22:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMABUSO8 | output | TCELL21:OUT.HALF.BOT0.TMIN, TCELL21:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMABUSO9 | output | TCELL21:OUT.HALF.BOT1.TMIN, TCELL21:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMBYTEENI0 | input | TCELL39:IMUX.IMUX10 |
| TSTC405DSOCMBYTEENI1 | input | TCELL39:IMUX.IMUX11 |
| TSTC405DSOCMBYTEENI2 | input | TCELL39:IMUX.IMUX12 |
| TSTC405DSOCMBYTEENI3 | input | TCELL39:IMUX.IMUX13 |
| TSTC405DSOCMBYTEENO0 | output | TCELL6:OUT.HALF.BOT0.TMIN, TCELL6:OUT.HALT.TOP0.TMIN |
| TSTC405DSOCMBYTEENO1 | output | TCELL6:OUT.HALF.BOT1.TMIN, TCELL6:OUT.HALT.TOP1.TMIN |
| TSTC405DSOCMBYTEENO2 | output | TCELL6:OUT.HALF.BOT2.TMIN, TCELL6:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMBYTEENO3 | output | TCELL6:OUT.HALF.BOT3.TMIN, TCELL6:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMLOADREQI | input | TCELL43:IMUX.IMUX12 |
| TSTC405DSOCMLOADREQO | output | TCELL6:OUT.HALF.BOT7.TMIN, TCELL6:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMSTOREREQI | input | TCELL43:IMUX.IMUX13 |
| TSTC405DSOCMSTOREREQO | output | TCELL16:OUT.HALF.BOT6.TMIN, TCELL16:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWAITI | input | TCELL43:IMUX.IMUX14 |
| TSTC405DSOCMWAITO | output | TCELL16:OUT.HALF.BOT7.TMIN, TCELL16:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSI0 | input | TCELL47:IMUX.IMUX12 |
| TSTC405DSOCMWRDBUSI1 | input | TCELL47:IMUX.IMUX13 |
| TSTC405DSOCMWRDBUSI10 | input | TCELL45:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI11 | input | TCELL45:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI12 | input | TCELL44:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI13 | input | TCELL44:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI14 | input | TCELL44:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI15 | input | TCELL44:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI16 | input | TCELL43:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI17 | input | TCELL43:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI18 | input | TCELL43:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI19 | input | TCELL43:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI2 | input | TCELL47:IMUX.IMUX14 |
| TSTC405DSOCMWRDBUSI20 | input | TCELL42:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI21 | input | TCELL42:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI22 | input | TCELL42:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI23 | input | TCELL42:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI24 | input | TCELL41:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI25 | input | TCELL41:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI26 | input | TCELL41:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI27 | input | TCELL41:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI28 | input | TCELL39:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI29 | input | TCELL39:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI3 | input | TCELL47:IMUX.IMUX15 |
| TSTC405DSOCMWRDBUSI30 | input | TCELL39:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI31 | input | TCELL39:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI4 | input | TCELL46:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI5 | input | TCELL46:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSI6 | input | TCELL46:IMUX.IMUX18 |
| TSTC405DSOCMWRDBUSI7 | input | TCELL46:IMUX.IMUX19 |
| TSTC405DSOCMWRDBUSI8 | input | TCELL45:IMUX.IMUX16 |
| TSTC405DSOCMWRDBUSI9 | input | TCELL45:IMUX.IMUX17 |
| TSTC405DSOCMWRDBUSO0 | output | TCELL23:OUT.HALF.BOT4.TMIN, TCELL23:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO1 | output | TCELL23:OUT.HALF.BOT5.TMIN, TCELL23:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO10 | output | TCELL21:OUT.HALF.BOT6.TMIN, TCELL21:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO11 | output | TCELL21:OUT.HALF.BOT7.TMIN, TCELL21:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO12 | output | TCELL20:OUT.HALF.BOT4.TMIN, TCELL20:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO13 | output | TCELL20:OUT.HALF.BOT5.TMIN, TCELL20:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO14 | output | TCELL20:OUT.HALF.BOT6.TMIN, TCELL20:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO15 | output | TCELL20:OUT.HALF.BOT7.TMIN, TCELL20:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO16 | output | TCELL19:OUT.HALF.BOT4.TMIN, TCELL19:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO17 | output | TCELL19:OUT.HALF.BOT5.TMIN, TCELL19:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO18 | output | TCELL19:OUT.HALF.BOT6.TMIN, TCELL19:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO19 | output | TCELL19:OUT.HALF.BOT7.TMIN, TCELL19:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO2 | output | TCELL23:OUT.HALF.BOT6.TMIN, TCELL23:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO20 | output | TCELL18:OUT.HALF.BOT4.TMIN, TCELL18:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO21 | output | TCELL18:OUT.HALF.BOT5.TMIN, TCELL18:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO22 | output | TCELL18:OUT.HALF.BOT6.TMIN, TCELL18:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO23 | output | TCELL18:OUT.HALF.BOT7.TMIN, TCELL18:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO24 | output | TCELL17:OUT.HALF.BOT4.TMIN, TCELL17:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO25 | output | TCELL17:OUT.HALF.BOT5.TMIN, TCELL17:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO26 | output | TCELL17:OUT.HALF.BOT6.TMIN, TCELL17:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO27 | output | TCELL17:OUT.HALF.BOT7.TMIN, TCELL17:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO28 | output | TCELL16:OUT.HALF.BOT2.TMIN, TCELL16:OUT.HALT.TOP2.TMIN |
| TSTC405DSOCMWRDBUSO29 | output | TCELL16:OUT.HALF.BOT3.TMIN, TCELL16:OUT.HALT.TOP3.TMIN |
| TSTC405DSOCMWRDBUSO3 | output | TCELL23:OUT.HALF.BOT7.TMIN, TCELL23:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO30 | output | TCELL16:OUT.HALF.BOT4.TMIN, TCELL16:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO31 | output | TCELL16:OUT.HALF.BOT5.TMIN, TCELL16:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO4 | output | TCELL22:OUT.HALF.BOT4.TMIN, TCELL22:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO5 | output | TCELL22:OUT.HALF.BOT5.TMIN, TCELL22:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMWRDBUSO6 | output | TCELL22:OUT.HALF.BOT6.TMIN, TCELL22:OUT.HALT.TOP6.TMIN |
| TSTC405DSOCMWRDBUSO7 | output | TCELL22:OUT.HALF.BOT7.TMIN, TCELL22:OUT.HALT.TOP7.TMIN |
| TSTC405DSOCMWRDBUSO8 | output | TCELL21:OUT.HALF.BOT4.TMIN, TCELL21:OUT.HALT.TOP4.TMIN |
| TSTC405DSOCMWRDBUSO9 | output | TCELL21:OUT.HALF.BOT5.TMIN, TCELL21:OUT.HALT.TOP5.TMIN |
| TSTC405DSOCMXLTVALIDI | input | TCELL43:IMUX.IMUX15 |
| TSTC405DSOCMXLTVALIDO | output | TCELL6:OUT.HALF.BOT4.TMIN, TCELL6:OUT.HALT.TOP4.TMIN |
| TSTC405ISOCMABORTI | input | TCELL24:IMUX.IMUX17 |
| TSTC405ISOCMABORTO | output | TCELL49:OUT.HALF.BOT3.TMIN, TCELL49:OUT.HALT.TOP3.TMIN |
| TSTC405ISOCMABUSI0 | input | TCELL14:IMUX.IMUX15 |
| TSTC405ISOCMABUSI1 | input | TCELL14:IMUX.IMUX16 |
| TSTC405ISOCMABUSI10 | input | TCELL12:IMUX.IMUX14 |
| TSTC405ISOCMABUSI11 | input | TCELL12:IMUX.IMUX15 |
| TSTC405ISOCMABUSI12 | input | TCELL11:IMUX.IMUX11 |
| TSTC405ISOCMABUSI13 | input | TCELL11:IMUX.IMUX12 |
| TSTC405ISOCMABUSI14 | input | TCELL11:IMUX.IMUX13 |
| TSTC405ISOCMABUSI15 | input | TCELL11:IMUX.IMUX14 |
| TSTC405ISOCMABUSI16 | input | TCELL10:IMUX.IMUX16 |
| TSTC405ISOCMABUSI17 | input | TCELL10:IMUX.IMUX17 |
| TSTC405ISOCMABUSI18 | input | TCELL10:IMUX.IMUX18 |
| TSTC405ISOCMABUSI19 | input | TCELL10:IMUX.IMUX19 |
| TSTC405ISOCMABUSI2 | input | TCELL14:IMUX.IMUX17 |
| TSTC405ISOCMABUSI20 | input | TCELL9:IMUX.IMUX15 |
| TSTC405ISOCMABUSI21 | input | TCELL9:IMUX.IMUX16 |
| TSTC405ISOCMABUSI22 | input | TCELL9:IMUX.IMUX17 |
| TSTC405ISOCMABUSI23 | input | TCELL9:IMUX.IMUX18 |
| TSTC405ISOCMABUSI24 | input | TCELL9:IMUX.IMUX19 |
| TSTC405ISOCMABUSI25 | input | TCELL8:IMUX.IMUX13 |
| TSTC405ISOCMABUSI26 | input | TCELL8:IMUX.IMUX14 |
| TSTC405ISOCMABUSI27 | input | TCELL8:IMUX.IMUX15 |
| TSTC405ISOCMABUSI28 | input | TCELL8:IMUX.IMUX16 |
| TSTC405ISOCMABUSI29 | input | TCELL8:IMUX.IMUX17 |
| TSTC405ISOCMABUSI3 | input | TCELL14:IMUX.IMUX18 |
| TSTC405ISOCMABUSI4 | input | TCELL13:IMUX.IMUX12 |
| TSTC405ISOCMABUSI5 | input | TCELL13:IMUX.IMUX13 |
| TSTC405ISOCMABUSI6 | input | TCELL13:IMUX.IMUX14 |
| TSTC405ISOCMABUSI7 | input | TCELL13:IMUX.IMUX15 |
| TSTC405ISOCMABUSI8 | input | TCELL12:IMUX.IMUX12 |
| TSTC405ISOCMABUSI9 | input | TCELL12:IMUX.IMUX13 |
| TSTC405ISOCMABUSO0 | output | TCELL53:OUT.HALF.BOT0.TMIN, TCELL53:OUT.HALT.TOP0.TMIN |
| TSTC405ISOCMABUSO1 | output | TCELL53:OUT.HALF.BOT1.TMIN, TCELL53:OUT.HALT.TOP1.TMIN |
| TSTC405ISOCMABUSO10 | output | TCELL52:OUT.HALF.BOT2.TMIN, TCELL52:OUT.HALT.TOP2.TMIN |
| TSTC405ISOCMABUSO11 | output | TCELL52:OUT.HALF.BOT3.TMIN, TCELL52:OUT.HALT.TOP3.TMIN |
| TSTC405ISOCMABUSO12 | output | TCELL52:OUT.HALF.BOT4.TMIN, TCELL52:OUT.HALT.TOP4.TMIN |
| TSTC405ISOCMABUSO13 | output | TCELL52:OUT.HALF.BOT5.TMIN, TCELL52:OUT.HALT.TOP5.TMIN |
| TSTC405ISOCMABUSO14 | output | TCELL52:OUT.HALF.BOT6.TMIN, TCELL52:OUT.HALT.TOP6.TMIN |
| TSTC405ISOCMABUSO15 | output | TCELL52:OUT.HALF.BOT7.TMIN, TCELL52:OUT.HALT.TOP7.TMIN |
| TSTC405ISOCMABUSO16 | output | TCELL51:OUT.HALF.BOT0.TMIN, TCELL51:OUT.HALT.TOP0.TMIN |
| TSTC405ISOCMABUSO17 | output | TCELL51:OUT.HALF.BOT1.TMIN, TCELL51:OUT.HALT.TOP1.TMIN |
| TSTC405ISOCMABUSO18 | output | TCELL51:OUT.HALF.BOT2.TMIN, TCELL51:OUT.HALT.TOP2.TMIN |
| TSTC405ISOCMABUSO19 | output | TCELL51:OUT.HALF.BOT3.TMIN, TCELL51:OUT.HALT.TOP3.TMIN |
| TSTC405ISOCMABUSO2 | output | TCELL53:OUT.HALF.BOT2.TMIN, TCELL53:OUT.HALT.TOP2.TMIN |
| TSTC405ISOCMABUSO20 | output | TCELL51:OUT.HALF.BOT4.TMIN, TCELL51:OUT.HALT.TOP4.TMIN |
| TSTC405ISOCMABUSO21 | output | TCELL51:OUT.HALF.BOT5.TMIN, TCELL51:OUT.HALT.TOP5.TMIN |
| TSTC405ISOCMABUSO22 | output | TCELL51:OUT.HALF.BOT6.TMIN, TCELL51:OUT.HALT.TOP6.TMIN |
| TSTC405ISOCMABUSO23 | output | TCELL51:OUT.HALF.BOT7.TMIN, TCELL51:OUT.HALT.TOP7.TMIN |
| TSTC405ISOCMABUSO24 | output | TCELL50:OUT.HALF.BOT0.TMIN, TCELL50:OUT.HALT.TOP0.TMIN |
| TSTC405ISOCMABUSO25 | output | TCELL50:OUT.HALF.BOT1.TMIN, TCELL50:OUT.HALT.TOP1.TMIN |
| TSTC405ISOCMABUSO26 | output | TCELL50:OUT.HALF.BOT2.TMIN, TCELL50:OUT.HALT.TOP2.TMIN |
| TSTC405ISOCMABUSO27 | output | TCELL50:OUT.HALF.BOT3.TMIN, TCELL50:OUT.HALT.TOP3.TMIN |
| TSTC405ISOCMABUSO28 | output | TCELL50:OUT.HALF.BOT4.TMIN, TCELL50:OUT.HALT.TOP4.TMIN |
| TSTC405ISOCMABUSO29 | output | TCELL50:OUT.HALF.BOT5.TMIN, TCELL50:OUT.HALT.TOP5.TMIN |
| TSTC405ISOCMABUSO3 | output | TCELL53:OUT.HALF.BOT3.TMIN, TCELL53:OUT.HALT.TOP3.TMIN |
| TSTC405ISOCMABUSO4 | output | TCELL53:OUT.HALF.BOT4.TMIN, TCELL53:OUT.HALT.TOP4.TMIN |
| TSTC405ISOCMABUSO5 | output | TCELL53:OUT.HALF.BOT5.TMIN, TCELL53:OUT.HALT.TOP5.TMIN |
| TSTC405ISOCMABUSO6 | output | TCELL53:OUT.HALF.BOT6.TMIN, TCELL53:OUT.HALT.TOP6.TMIN |
| TSTC405ISOCMABUSO7 | output | TCELL53:OUT.HALF.BOT7.TMIN, TCELL53:OUT.HALT.TOP7.TMIN |
| TSTC405ISOCMABUSO8 | output | TCELL52:OUT.HALF.BOT0.TMIN, TCELL52:OUT.HALT.TOP0.TMIN |
| TSTC405ISOCMABUSO9 | output | TCELL52:OUT.HALF.BOT1.TMIN, TCELL52:OUT.HALT.TOP1.TMIN |
| TSTC405ISOCMICUREADYI | input | TCELL24:IMUX.IMUX15 |
| TSTC405ISOCMICUREADYO | output | TCELL49:OUT.HALF.BOT1.TMIN, TCELL49:OUT.HALT.TOP1.TMIN |
| TSTC405ISOCMREQPENDINGI | input | TCELL24:IMUX.IMUX14 |
| TSTC405ISOCMREQPENDINGO | output | TCELL49:OUT.HALF.BOT0.TMIN, TCELL49:OUT.HALT.TOP0.TMIN |
| TSTC405ISOCMXLTVALIDI | input | TCELL24:IMUX.IMUX16 |
| TSTC405ISOCMXLTVALIDO | output | TCELL49:OUT.HALF.BOT2.TMIN, TCELL49:OUT.HALT.TOP2.TMIN |
| TSTCLKINACTI | input | TCELL10:IMUX.IMUX12 |
| TSTCLKINACTO | output | TCELL48:OUT.HALF.BOT1.TMIN, TCELL48:OUT.HALT.TOP1.TMIN |
| TSTCPUCLKENI | input | TCELL10:IMUX.IMUX11 |
| TSTCPUCLKENO | output | TCELL48:OUT.HALF.BOT0.TMIN, TCELL48:OUT.HALT.TOP0.TMIN |
| TSTDCRC405ACKO | output | TCELL39:OUT.HALF.BOT3.TMIN, TCELL39:OUT.HALT.TOP3.TMIN |
| TSTDCRC405DBUSINO0 | output | TCELL20:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO1 | output | TCELL20:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO10 | output | TCELL18:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO11 | output | TCELL18:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO12 | output | TCELL11:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO13 | output | TCELL11:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO14 | output | TCELL11:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO15 | output | TCELL11:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO16 | output | TCELL10:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO17 | output | TCELL10:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO18 | output | TCELL10:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO19 | output | TCELL10:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO2 | output | TCELL20:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO20 | output | TCELL5:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO21 | output | TCELL5:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO22 | output | TCELL5:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO23 | output | TCELL5:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO24 | output | TCELL3:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO25 | output | TCELL3:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO26 | output | TCELL3:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO27 | output | TCELL3:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO28 | output | TCELL2:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO29 | output | TCELL2:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO3 | output | TCELL20:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO30 | output | TCELL2:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO31 | output | TCELL2:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO4 | output | TCELL19:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO5 | output | TCELL19:OUT.SEC1.TMIN |
| TSTDCRC405DBUSINO6 | output | TCELL19:OUT.SEC2.TMIN |
| TSTDCRC405DBUSINO7 | output | TCELL19:OUT.SEC3.TMIN |
| TSTDCRC405DBUSINO8 | output | TCELL18:OUT.SEC0.TMIN |
| TSTDCRC405DBUSINO9 | output | TCELL18:OUT.SEC1.TMIN |
| TSTDSOCMC405COMPLETEI | input | TCELL57:IMUX.IMUX10 |
| TSTDSOCMC405COMPLETEO | output | TCELL39:OUT.HALF.BOT0.TMIN, TCELL39:OUT.HALT.TOP0.TMIN |
| TSTDSOCMC405DISOPERANDFWDI | input | TCELL57:IMUX.IMUX11 |
| TSTDSOCMC405DISOPERANDFWDO | output | TCELL39:OUT.HALF.BOT1.TMIN, TCELL39:OUT.HALT.TOP1.TMIN |
| TSTDSOCMC405HOLDI | input | TCELL58:IMUX.IMUX13 |
| TSTDSOCMC405HOLDO | output | TCELL39:OUT.HALF.BOT2.TMIN, TCELL39:OUT.HALT.TOP2.TMIN |
| TSTDSOCMC405RDDBUSI0 | input | TCELL61:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI1 | input | TCELL61:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI10 | input | TCELL59:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI11 | input | TCELL59:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI12 | input | TCELL58:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI13 | input | TCELL58:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI14 | input | TCELL58:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI15 | input | TCELL58:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI16 | input | TCELL57:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI17 | input | TCELL57:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI18 | input | TCELL57:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI19 | input | TCELL57:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI2 | input | TCELL61:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI20 | input | TCELL56:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI21 | input | TCELL56:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI22 | input | TCELL56:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI23 | input | TCELL56:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI24 | input | TCELL55:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI25 | input | TCELL55:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI26 | input | TCELL55:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI27 | input | TCELL55:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI28 | input | TCELL55:IMUX.IMUX12 |
| TSTDSOCMC405RDDBUSI29 | input | TCELL55:IMUX.IMUX13 |
| TSTDSOCMC405RDDBUSI3 | input | TCELL61:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI30 | input | TCELL55:IMUX.IMUX14 |
| TSTDSOCMC405RDDBUSI31 | input | TCELL55:IMUX.IMUX15 |
| TSTDSOCMC405RDDBUSI4 | input | TCELL60:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI5 | input | TCELL60:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSI6 | input | TCELL60:IMUX.IMUX18 |
| TSTDSOCMC405RDDBUSI7 | input | TCELL60:IMUX.IMUX19 |
| TSTDSOCMC405RDDBUSI8 | input | TCELL59:IMUX.IMUX16 |
| TSTDSOCMC405RDDBUSI9 | input | TCELL59:IMUX.IMUX17 |
| TSTDSOCMC405RDDBUSO0 | output | TCELL15:OUT.HALF.BOT4.TMIN, TCELL15:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO1 | output | TCELL15:OUT.HALF.BOT5.TMIN, TCELL15:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO10 | output | TCELL13:OUT.HALF.BOT6.TMIN, TCELL13:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO11 | output | TCELL13:OUT.HALF.BOT7.TMIN, TCELL13:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO12 | output | TCELL12:OUT.HALF.BOT4.TMIN, TCELL12:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO13 | output | TCELL12:OUT.HALF.BOT5.TMIN, TCELL12:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO14 | output | TCELL12:OUT.HALF.BOT6.TMIN, TCELL12:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO15 | output | TCELL12:OUT.HALF.BOT7.TMIN, TCELL12:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO16 | output | TCELL11:OUT.HALF.BOT4.TMIN, TCELL11:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO17 | output | TCELL11:OUT.HALF.BOT5.TMIN, TCELL11:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO18 | output | TCELL11:OUT.HALF.BOT6.TMIN, TCELL11:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO19 | output | TCELL11:OUT.HALF.BOT7.TMIN, TCELL11:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO2 | output | TCELL15:OUT.HALF.BOT6.TMIN, TCELL15:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO20 | output | TCELL10:OUT.HALF.BOT4.TMIN, TCELL10:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO21 | output | TCELL10:OUT.HALF.BOT5.TMIN, TCELL10:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO22 | output | TCELL10:OUT.HALF.BOT6.TMIN, TCELL10:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO23 | output | TCELL10:OUT.HALF.BOT7.TMIN, TCELL10:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO24 | output | TCELL9:OUT.HALF.BOT4.TMIN, TCELL9:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO25 | output | TCELL9:OUT.HALF.BOT5.TMIN, TCELL9:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO26 | output | TCELL9:OUT.HALF.BOT6.TMIN, TCELL9:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO27 | output | TCELL9:OUT.HALF.BOT7.TMIN, TCELL9:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO28 | output | TCELL8:OUT.HALF.BOT4.TMIN, TCELL8:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO29 | output | TCELL8:OUT.HALF.BOT5.TMIN, TCELL8:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO3 | output | TCELL15:OUT.HALF.BOT7.TMIN, TCELL15:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO30 | output | TCELL8:OUT.HALF.BOT6.TMIN, TCELL8:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO31 | output | TCELL8:OUT.HALF.BOT7.TMIN, TCELL8:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO4 | output | TCELL14:OUT.HALF.BOT4.TMIN, TCELL14:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO5 | output | TCELL14:OUT.HALF.BOT5.TMIN, TCELL14:OUT.HALT.TOP5.TMIN |
| TSTDSOCMC405RDDBUSO6 | output | TCELL14:OUT.HALF.BOT6.TMIN, TCELL14:OUT.HALT.TOP6.TMIN |
| TSTDSOCMC405RDDBUSO7 | output | TCELL14:OUT.HALF.BOT7.TMIN, TCELL14:OUT.HALT.TOP7.TMIN |
| TSTDSOCMC405RDDBUSO8 | output | TCELL13:OUT.HALF.BOT4.TMIN, TCELL13:OUT.HALT.TOP4.TMIN |
| TSTDSOCMC405RDDBUSO9 | output | TCELL13:OUT.HALF.BOT5.TMIN, TCELL13:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405HOLDI | input | TCELL53:IMUX.IMUX14 |
| TSTISOCMC405HOLDO | output | TCELL48:OUT.HALF.BOT6.TMIN, TCELL48:OUT.HALT.TOP6.TMIN |
| TSTISOCMC405RDDVALIDI0 | input | TCELL52:IMUX.IMUX16 |
| TSTISOCMC405RDDVALIDI1 | input | TCELL52:IMUX.IMUX17 |
| TSTISOCMC405RDDVALIDO0 | output | TCELL48:OUT.HALF.BOT4.TMIN, TCELL48:OUT.HALT.TOP4.TMIN |
| TSTISOCMC405RDDVALIDO1 | output | TCELL48:OUT.HALF.BOT5.TMIN, TCELL48:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405READDATAOUTI0 | input | TCELL7:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI1 | input | TCELL7:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI10 | input | TCELL5:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI11 | input | TCELL5:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI12 | input | TCELL4:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI13 | input | TCELL4:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI14 | input | TCELL4:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI15 | input | TCELL4:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI16 | input | TCELL3:IMUX.IMUX15 |
| TSTISOCMC405READDATAOUTI17 | input | TCELL3:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI18 | input | TCELL3:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI19 | input | TCELL3:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI2 | input | TCELL7:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI20 | input | TCELL2:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI21 | input | TCELL2:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI22 | input | TCELL2:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI23 | input | TCELL2:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI24 | input | TCELL1:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI25 | input | TCELL1:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI26 | input | TCELL1:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI27 | input | TCELL1:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI28 | input | TCELL0:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI29 | input | TCELL0:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI3 | input | TCELL7:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI30 | input | TCELL0:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI31 | input | TCELL0:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI32 | input | TCELL54:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI33 | input | TCELL54:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI34 | input | TCELL54:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI35 | input | TCELL54:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI36 | input | TCELL53:IMUX.IMUX15 |
| TSTISOCMC405READDATAOUTI37 | input | TCELL53:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI38 | input | TCELL53:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI39 | input | TCELL53:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI4 | input | TCELL6:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI40 | input | TCELL52:IMUX.IMUX12 |
| TSTISOCMC405READDATAOUTI41 | input | TCELL52:IMUX.IMUX13 |
| TSTISOCMC405READDATAOUTI42 | input | TCELL52:IMUX.IMUX14 |
| TSTISOCMC405READDATAOUTI43 | input | TCELL52:IMUX.IMUX15 |
| TSTISOCMC405READDATAOUTI44 | input | TCELL51:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI45 | input | TCELL51:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI46 | input | TCELL51:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI47 | input | TCELL51:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI48 | input | TCELL50:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI49 | input | TCELL50:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI5 | input | TCELL6:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI50 | input | TCELL50:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI51 | input | TCELL50:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI52 | input | TCELL49:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI53 | input | TCELL49:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI54 | input | TCELL49:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI55 | input | TCELL49:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI56 | input | TCELL48:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI57 | input | TCELL48:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTI58 | input | TCELL48:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI59 | input | TCELL48:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI6 | input | TCELL6:IMUX.IMUX18 |
| TSTISOCMC405READDATAOUTI60 | input | TCELL48:IMUX.IMUX12 |
| TSTISOCMC405READDATAOUTI61 | input | TCELL48:IMUX.IMUX13 |
| TSTISOCMC405READDATAOUTI62 | input | TCELL48:IMUX.IMUX14 |
| TSTISOCMC405READDATAOUTI63 | input | TCELL48:IMUX.IMUX15 |
| TSTISOCMC405READDATAOUTI7 | input | TCELL6:IMUX.IMUX19 |
| TSTISOCMC405READDATAOUTI8 | input | TCELL5:IMUX.IMUX16 |
| TSTISOCMC405READDATAOUTI9 | input | TCELL5:IMUX.IMUX17 |
| TSTISOCMC405READDATAOUTO0 | output | TCELL27:OUT.HALF.BOT0.TMIN, TCELL27:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO1 | output | TCELL27:OUT.HALF.BOT1.TMIN, TCELL27:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO10 | output | TCELL26:OUT.HALF.BOT2.TMIN, TCELL26:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO11 | output | TCELL26:OUT.HALF.BOT3.TMIN, TCELL26:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO12 | output | TCELL26:OUT.HALF.BOT4.TMIN, TCELL26:OUT.HALT.TOP4.TMIN |
| TSTISOCMC405READDATAOUTO13 | output | TCELL26:OUT.HALF.BOT5.TMIN, TCELL26:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405READDATAOUTO14 | output | TCELL26:OUT.HALF.BOT6.TMIN, TCELL26:OUT.HALT.TOP6.TMIN |
| TSTISOCMC405READDATAOUTO15 | output | TCELL26:OUT.HALF.BOT7.TMIN, TCELL26:OUT.HALT.TOP7.TMIN |
| TSTISOCMC405READDATAOUTO16 | output | TCELL25:OUT.HALF.BOT0.TMIN, TCELL25:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO17 | output | TCELL25:OUT.HALF.BOT1.TMIN, TCELL25:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO18 | output | TCELL25:OUT.HALF.BOT2.TMIN, TCELL25:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO19 | output | TCELL25:OUT.HALF.BOT3.TMIN, TCELL25:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO2 | output | TCELL27:OUT.HALF.BOT2.TMIN, TCELL27:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO20 | output | TCELL25:OUT.HALF.BOT4.TMIN, TCELL25:OUT.HALT.TOP4.TMIN |
| TSTISOCMC405READDATAOUTO21 | output | TCELL25:OUT.HALF.BOT5.TMIN, TCELL25:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405READDATAOUTO22 | output | TCELL25:OUT.HALF.BOT6.TMIN, TCELL25:OUT.HALT.TOP6.TMIN |
| TSTISOCMC405READDATAOUTO23 | output | TCELL25:OUT.HALF.BOT7.TMIN, TCELL25:OUT.HALT.TOP7.TMIN |
| TSTISOCMC405READDATAOUTO24 | output | TCELL24:OUT.HALF.BOT0.TMIN, TCELL24:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO25 | output | TCELL24:OUT.HALF.BOT1.TMIN, TCELL24:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO26 | output | TCELL24:OUT.HALF.BOT2.TMIN, TCELL24:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO27 | output | TCELL24:OUT.HALF.BOT3.TMIN, TCELL24:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO28 | output | TCELL24:OUT.HALF.BOT4.TMIN, TCELL24:OUT.HALT.TOP4.TMIN |
| TSTISOCMC405READDATAOUTO29 | output | TCELL24:OUT.HALF.BOT5.TMIN, TCELL24:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405READDATAOUTO3 | output | TCELL27:OUT.HALF.BOT3.TMIN, TCELL27:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO30 | output | TCELL24:OUT.HALF.BOT6.TMIN, TCELL24:OUT.HALT.TOP6.TMIN |
| TSTISOCMC405READDATAOUTO31 | output | TCELL24:OUT.HALF.BOT7.TMIN, TCELL24:OUT.HALT.TOP7.TMIN |
| TSTISOCMC405READDATAOUTO32 | output | TCELL15:OUT.HALF.BOT0.TMIN, TCELL15:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO33 | output | TCELL15:OUT.HALF.BOT1.TMIN, TCELL15:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO34 | output | TCELL15:OUT.HALF.BOT2.TMIN, TCELL15:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO35 | output | TCELL15:OUT.HALF.BOT3.TMIN, TCELL15:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO36 | output | TCELL14:OUT.HALF.BOT0.TMIN, TCELL14:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO37 | output | TCELL14:OUT.HALF.BOT1.TMIN, TCELL14:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO38 | output | TCELL14:OUT.HALF.BOT2.TMIN, TCELL14:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO39 | output | TCELL14:OUT.HALF.BOT3.TMIN, TCELL14:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO4 | output | TCELL27:OUT.HALF.BOT4.TMIN, TCELL27:OUT.HALT.TOP4.TMIN |
| TSTISOCMC405READDATAOUTO40 | output | TCELL13:OUT.HALF.BOT0.TMIN, TCELL13:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO41 | output | TCELL13:OUT.HALF.BOT1.TMIN, TCELL13:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO42 | output | TCELL13:OUT.HALF.BOT2.TMIN, TCELL13:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO43 | output | TCELL13:OUT.HALF.BOT3.TMIN, TCELL13:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO44 | output | TCELL12:OUT.HALF.BOT0.TMIN, TCELL12:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO45 | output | TCELL12:OUT.HALF.BOT1.TMIN, TCELL12:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO46 | output | TCELL12:OUT.HALF.BOT2.TMIN, TCELL12:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO47 | output | TCELL12:OUT.HALF.BOT3.TMIN, TCELL12:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO48 | output | TCELL11:OUT.HALF.BOT0.TMIN, TCELL11:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO49 | output | TCELL11:OUT.HALF.BOT1.TMIN, TCELL11:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO5 | output | TCELL27:OUT.HALF.BOT5.TMIN, TCELL27:OUT.HALT.TOP5.TMIN |
| TSTISOCMC405READDATAOUTO50 | output | TCELL11:OUT.HALF.BOT2.TMIN, TCELL11:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO51 | output | TCELL11:OUT.HALF.BOT3.TMIN, TCELL11:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO52 | output | TCELL10:OUT.HALF.BOT0.TMIN, TCELL10:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO53 | output | TCELL10:OUT.HALF.BOT1.TMIN, TCELL10:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO54 | output | TCELL10:OUT.HALF.BOT2.TMIN, TCELL10:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO55 | output | TCELL10:OUT.HALF.BOT3.TMIN, TCELL10:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO56 | output | TCELL9:OUT.HALF.BOT0.TMIN, TCELL9:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO57 | output | TCELL9:OUT.HALF.BOT1.TMIN, TCELL9:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO58 | output | TCELL9:OUT.HALF.BOT2.TMIN, TCELL9:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO59 | output | TCELL9:OUT.HALF.BOT3.TMIN, TCELL9:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO6 | output | TCELL27:OUT.HALF.BOT6.TMIN, TCELL27:OUT.HALT.TOP6.TMIN |
| TSTISOCMC405READDATAOUTO60 | output | TCELL8:OUT.HALF.BOT0.TMIN, TCELL8:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO61 | output | TCELL8:OUT.HALF.BOT1.TMIN, TCELL8:OUT.HALT.TOP1.TMIN |
| TSTISOCMC405READDATAOUTO62 | output | TCELL8:OUT.HALF.BOT2.TMIN, TCELL8:OUT.HALT.TOP2.TMIN |
| TSTISOCMC405READDATAOUTO63 | output | TCELL8:OUT.HALF.BOT3.TMIN, TCELL8:OUT.HALT.TOP3.TMIN |
| TSTISOCMC405READDATAOUTO7 | output | TCELL27:OUT.HALF.BOT7.TMIN, TCELL27:OUT.HALT.TOP7.TMIN |
| TSTISOCMC405READDATAOUTO8 | output | TCELL26:OUT.HALF.BOT0.TMIN, TCELL26:OUT.HALT.TOP0.TMIN |
| TSTISOCMC405READDATAOUTO9 | output | TCELL26:OUT.HALF.BOT1.TMIN, TCELL26:OUT.HALT.TOP1.TMIN |
| TSTJTAGENI | input | TCELL10:IMUX.IMUX14 |
| TSTJTAGENO | output | TCELL48:OUT.HALF.BOT3.TMIN, TCELL48:OUT.HALT.TOP3.TMIN |
| TSTPLBSAMPLECYCLEO | output | TCELL21:OUT.SEC4.TMIN |
| TSTRESETCHIPI | input | TCELL11:IMUX.IMUX9 |
| TSTRESETCHIPO | output | TCELL39:OUT.HALF.BOT5.TMIN, TCELL39:OUT.HALT.TOP5.TMIN |
| TSTRESETCOREI | input | TCELL10:IMUX.IMUX15 |
| TSTRESETCOREO | output | TCELL39:OUT.HALF.BOT4.TMIN, TCELL39:OUT.HALT.TOP4.TMIN |
| TSTRESETSYSI | input | TCELL11:IMUX.IMUX10 |
| TSTRESETSYSO | output | TCELL39:OUT.HALF.BOT6.TMIN, TCELL39:OUT.HALT.TOP6.TMIN |
| TSTSEPPCEMACI | input | TCELL54:IMUX.SR3 |
| TSTSIGASKETI0 | input | TCELL20:IMUX.IMUX13 |
| TSTSIGASKETI1 | input | TCELL20:IMUX.IMUX14 |
| TSTSOGASKETO0 | output | TCELL37:OUT.HALF.BOT3.TMIN, TCELL37:OUT.HALT.TOP3.TMIN |
| TSTSOGASKETO1 | output | TCELL37:OUT.HALF.BOT4.TMIN, TCELL37:OUT.HALT.TOP4.TMIN |
| TSTTIMERENI | input | TCELL10:IMUX.IMUX13 |
| TSTTIMERENO | output | TCELL48:OUT.HALF.BOT2.TMIN, TCELL48:OUT.HALT.TOP2.TMIN |
| TSTTRSTNEGI | input | TCELL22:IMUX.IMUX16 |
| TSTTRSTNEGO | output | TCELL39:OUT.HALF.BOT7.TMIN, TCELL39:OUT.HALT.TOP7.TMIN |
| TSTUSECPMCLKSELI | input | TCELL7:IMUX.CE3 |
Bel EMAC
| Pin | Direction | Wires |
|---|---|---|
| CLIENTEMAC0DCMLOCKED | input | TCELL10:IMUX.IMUX4 |
| CLIENTEMAC0PAUSEREQ | input | TCELL1:IMUX.IMUX11 |
| CLIENTEMAC0PAUSEVAL0 | input | TCELL4:IMUX.IMUX8 |
| CLIENTEMAC0PAUSEVAL1 | input | TCELL4:IMUX.IMUX9 |
| CLIENTEMAC0PAUSEVAL10 | input | TCELL8:IMUX.IMUX6 |
| CLIENTEMAC0PAUSEVAL11 | input | TCELL8:IMUX.IMUX7 |
| CLIENTEMAC0PAUSEVAL12 | input | TCELL7:IMUX.IMUX12 |
| CLIENTEMAC0PAUSEVAL13 | input | TCELL7:IMUX.IMUX13 |
| CLIENTEMAC0PAUSEVAL14 | input | TCELL7:IMUX.IMUX14 |
| CLIENTEMAC0PAUSEVAL15 | input | TCELL7:IMUX.IMUX15 |
| CLIENTEMAC0PAUSEVAL2 | input | TCELL4:IMUX.IMUX10 |
| CLIENTEMAC0PAUSEVAL3 | input | TCELL4:IMUX.IMUX11 |
| CLIENTEMAC0PAUSEVAL4 | input | TCELL5:IMUX.IMUX8 |
| CLIENTEMAC0PAUSEVAL5 | input | TCELL5:IMUX.IMUX9 |
| CLIENTEMAC0PAUSEVAL6 | input | TCELL5:IMUX.IMUX10 |
| CLIENTEMAC0PAUSEVAL7 | input | TCELL5:IMUX.IMUX11 |
| CLIENTEMAC0PAUSEVAL8 | input | TCELL8:IMUX.IMUX4 |
| CLIENTEMAC0PAUSEVAL9 | input | TCELL8:IMUX.IMUX5 |
| CLIENTEMAC0RXCLIENTCLKIN | input | TCELL10:IMUX.CLK0 |
| CLIENTEMAC0TXCLIENTCLKIN | input | TCELL12:IMUX.CLK0 |
| CLIENTEMAC0TXD0 | input | TCELL2:IMUX.IMUX8 |
| CLIENTEMAC0TXD1 | input | TCELL2:IMUX.IMUX9 |
| CLIENTEMAC0TXD10 | input | TCELL4:IMUX.IMUX2 |
| CLIENTEMAC0TXD11 | input | TCELL4:IMUX.IMUX3 |
| CLIENTEMAC0TXD12 | input | TCELL5:IMUX.IMUX0 |
| CLIENTEMAC0TXD13 | input | TCELL5:IMUX.IMUX1 |
| CLIENTEMAC0TXD14 | input | TCELL5:IMUX.IMUX2 |
| CLIENTEMAC0TXD15 | input | TCELL5:IMUX.IMUX3 |
| CLIENTEMAC0TXD2 | input | TCELL2:IMUX.IMUX10 |
| CLIENTEMAC0TXD3 | input | TCELL2:IMUX.IMUX11 |
| CLIENTEMAC0TXD4 | input | TCELL3:IMUX.IMUX5 |
| CLIENTEMAC0TXD5 | input | TCELL3:IMUX.IMUX6 |
| CLIENTEMAC0TXD6 | input | TCELL3:IMUX.IMUX7 |
| CLIENTEMAC0TXD7 | input | TCELL3:IMUX.IMUX8 |
| CLIENTEMAC0TXD8 | input | TCELL4:IMUX.IMUX0 |
| CLIENTEMAC0TXD9 | input | TCELL4:IMUX.IMUX1 |
| CLIENTEMAC0TXDVLD | input | TCELL1:IMUX.IMUX12 |
| CLIENTEMAC0TXDVLDMSW | input | TCELL1:IMUX.IMUX13 |
| CLIENTEMAC0TXFIRSTBYTE | input | TCELL3:IMUX.IMUX0 |
| CLIENTEMAC0TXGMIIMIICLKIN | input | TCELL11:IMUX.CLK0 |
| CLIENTEMAC0TXIFGDELAY0 | input | TCELL4:IMUX.IMUX4 |
| CLIENTEMAC0TXIFGDELAY1 | input | TCELL4:IMUX.IMUX5 |
| CLIENTEMAC0TXIFGDELAY2 | input | TCELL4:IMUX.IMUX6 |
| CLIENTEMAC0TXIFGDELAY3 | input | TCELL4:IMUX.IMUX7 |
| CLIENTEMAC0TXIFGDELAY4 | input | TCELL5:IMUX.IMUX4 |
| CLIENTEMAC0TXIFGDELAY5 | input | TCELL5:IMUX.IMUX5 |
| CLIENTEMAC0TXIFGDELAY6 | input | TCELL5:IMUX.IMUX6 |
| CLIENTEMAC0TXIFGDELAY7 | input | TCELL5:IMUX.IMUX7 |
| CLIENTEMAC0TXUNDERRUN | input | TCELL1:IMUX.IMUX10 |
| CLIENTEMAC1DCMLOCKED | input | TCELL18:IMUX.IMUX12 |
| CLIENTEMAC1PAUSEREQ | input | TCELL22:IMUX.IMUX11 |
| CLIENTEMAC1PAUSEVAL0 | input | TCELL19:IMUX.IMUX8 |
| CLIENTEMAC1PAUSEVAL1 | input | TCELL19:IMUX.IMUX9 |
| CLIENTEMAC1PAUSEVAL10 | input | TCELL17:IMUX.IMUX13 |
| CLIENTEMAC1PAUSEVAL11 | input | TCELL17:IMUX.IMUX14 |
| CLIENTEMAC1PAUSEVAL12 | input | TCELL16:IMUX.IMUX12 |
| CLIENTEMAC1PAUSEVAL13 | input | TCELL16:IMUX.IMUX13 |
| CLIENTEMAC1PAUSEVAL14 | input | TCELL16:IMUX.IMUX14 |
| CLIENTEMAC1PAUSEVAL15 | input | TCELL16:IMUX.IMUX15 |
| CLIENTEMAC1PAUSEVAL2 | input | TCELL19:IMUX.IMUX10 |
| CLIENTEMAC1PAUSEVAL3 | input | TCELL19:IMUX.IMUX11 |
| CLIENTEMAC1PAUSEVAL4 | input | TCELL18:IMUX.IMUX8 |
| CLIENTEMAC1PAUSEVAL5 | input | TCELL18:IMUX.IMUX9 |
| CLIENTEMAC1PAUSEVAL6 | input | TCELL18:IMUX.IMUX10 |
| CLIENTEMAC1PAUSEVAL7 | input | TCELL18:IMUX.IMUX11 |
| CLIENTEMAC1PAUSEVAL8 | input | TCELL17:IMUX.IMUX11 |
| CLIENTEMAC1PAUSEVAL9 | input | TCELL17:IMUX.IMUX12 |
| CLIENTEMAC1RXCLIENTCLKIN | input | TCELL20:IMUX.CLK0 |
| CLIENTEMAC1TXCLIENTCLKIN | input | TCELL22:IMUX.CLK0 |
| CLIENTEMAC1TXD0 | input | TCELL21:IMUX.IMUX8 |
| CLIENTEMAC1TXD1 | input | TCELL21:IMUX.IMUX9 |
| CLIENTEMAC1TXD10 | input | TCELL19:IMUX.IMUX2 |
| CLIENTEMAC1TXD11 | input | TCELL19:IMUX.IMUX3 |
| CLIENTEMAC1TXD12 | input | TCELL18:IMUX.IMUX0 |
| CLIENTEMAC1TXD13 | input | TCELL18:IMUX.IMUX1 |
| CLIENTEMAC1TXD14 | input | TCELL18:IMUX.IMUX2 |
| CLIENTEMAC1TXD15 | input | TCELL18:IMUX.IMUX3 |
| CLIENTEMAC1TXD2 | input | TCELL21:IMUX.IMUX10 |
| CLIENTEMAC1TXD3 | input | TCELL21:IMUX.IMUX11 |
| CLIENTEMAC1TXD4 | input | TCELL20:IMUX.IMUX5 |
| CLIENTEMAC1TXD5 | input | TCELL20:IMUX.IMUX6 |
| CLIENTEMAC1TXD6 | input | TCELL20:IMUX.IMUX7 |
| CLIENTEMAC1TXD7 | input | TCELL20:IMUX.IMUX8 |
| CLIENTEMAC1TXD8 | input | TCELL19:IMUX.IMUX0 |
| CLIENTEMAC1TXD9 | input | TCELL19:IMUX.IMUX1 |
| CLIENTEMAC1TXDVLD | input | TCELL22:IMUX.IMUX12 |
| CLIENTEMAC1TXDVLDMSW | input | TCELL22:IMUX.IMUX13 |
| CLIENTEMAC1TXFIRSTBYTE | input | TCELL20:IMUX.IMUX0 |
| CLIENTEMAC1TXGMIIMIICLKIN | input | TCELL21:IMUX.CLK0 |
| CLIENTEMAC1TXIFGDELAY0 | input | TCELL19:IMUX.IMUX4 |
| CLIENTEMAC1TXIFGDELAY1 | input | TCELL19:IMUX.IMUX5 |
| CLIENTEMAC1TXIFGDELAY2 | input | TCELL19:IMUX.IMUX6 |
| CLIENTEMAC1TXIFGDELAY3 | input | TCELL19:IMUX.IMUX7 |
| CLIENTEMAC1TXIFGDELAY4 | input | TCELL18:IMUX.IMUX4 |
| CLIENTEMAC1TXIFGDELAY5 | input | TCELL18:IMUX.IMUX5 |
| CLIENTEMAC1TXIFGDELAY6 | input | TCELL18:IMUX.IMUX6 |
| CLIENTEMAC1TXIFGDELAY7 | input | TCELL18:IMUX.IMUX7 |
| CLIENTEMAC1TXUNDERRUN | input | TCELL22:IMUX.IMUX10 |
| DCREMACENABLE | input | TCELL17:IMUX.IMUX15 |
| DCRHOSTDONEIR | output | TCELL23:OUT.BEST7.TMIN |
| EMAC0CLIENTANINTERRUPT | output | TCELL8:OUT.SEC4.TMIN |
| EMAC0CLIENTRXBADFRAME | output | TCELL3:OUT.BEST7.TMIN |
| EMAC0CLIENTRXCLIENTCLKOUT | output | TCELL3:OUT.BEST4.TMIN |
| EMAC0CLIENTRXD0 | output | TCELL4:OUT.BEST0.TMIN |
| EMAC0CLIENTRXD1 | output | TCELL4:OUT.BEST1.TMIN |
| EMAC0CLIENTRXD10 | output | TCELL6:OUT.BEST5.TMIN |
| EMAC0CLIENTRXD11 | output | TCELL6:OUT.BEST6.TMIN |
| EMAC0CLIENTRXD12 | output | TCELL7:OUT.BEST4.TMIN |
| EMAC0CLIENTRXD13 | output | TCELL7:OUT.BEST5.TMIN |
| EMAC0CLIENTRXD14 | output | TCELL7:OUT.BEST6.TMIN |
| EMAC0CLIENTRXD15 | output | TCELL7:OUT.BEST7.TMIN |
| EMAC0CLIENTRXD2 | output | TCELL4:OUT.BEST2.TMIN |
| EMAC0CLIENTRXD3 | output | TCELL4:OUT.BEST3.TMIN |
| EMAC0CLIENTRXD4 | output | TCELL5:OUT.BEST4.TMIN |
| EMAC0CLIENTRXD5 | output | TCELL5:OUT.BEST5.TMIN |
| EMAC0CLIENTRXD6 | output | TCELL5:OUT.BEST6.TMIN |
| EMAC0CLIENTRXD7 | output | TCELL5:OUT.BEST7.TMIN |
| EMAC0CLIENTRXD8 | output | TCELL6:OUT.BEST3.TMIN |
| EMAC0CLIENTRXD9 | output | TCELL6:OUT.BEST4.TMIN |
| EMAC0CLIENTRXDVLD | output | TCELL1:OUT.BEST6.TMIN |
| EMAC0CLIENTRXDVLDMSW | output | TCELL1:OUT.BEST5.TMIN |
| EMAC0CLIENTRXDVREG6 | output | TCELL5:OUT.SEC4.TMIN |
| EMAC0CLIENTRXFRAMEDROP | output | TCELL3:OUT.BEST5.TMIN |
| EMAC0CLIENTRXGOODFRAME | output | TCELL3:OUT.BEST6.TMIN |
| EMAC0CLIENTRXSTATS0 | output | TCELL1:OUT.SEC0.TMIN |
| EMAC0CLIENTRXSTATS1 | output | TCELL1:OUT.SEC1.TMIN |
| EMAC0CLIENTRXSTATS2 | output | TCELL1:OUT.SEC2.TMIN |
| EMAC0CLIENTRXSTATS3 | output | TCELL2:OUT.BEST1.TMIN |
| EMAC0CLIENTRXSTATS4 | output | TCELL4:OUT.BEST6.TMIN |
| EMAC0CLIENTRXSTATS5 | output | TCELL4:OUT.BEST7.TMIN |
| EMAC0CLIENTRXSTATS6 | output | TCELL4:OUT.BEST5.TMIN |
| EMAC0CLIENTRXSTATSBYTEVLD | output | TCELL2:OUT.BEST5.TMIN |
| EMAC0CLIENTRXSTATSVLD | output | TCELL1:OUT.BEST7.TMIN |
| EMAC0CLIENTTXACK | output | TCELL2:OUT.BEST2.TMIN |
| EMAC0CLIENTTXCLIENTCLKOUT | output | TCELL2:OUT.BEST0.TMIN |
| EMAC0CLIENTTXCOLLISION | output | TCELL2:OUT.BEST3.TMIN |
| EMAC0CLIENTTXGMIIMIICLKOUT | output | TCELL3:OUT.BEST2.TMIN |
| EMAC0CLIENTTXRETRANSMIT | output | TCELL2:OUT.BEST4.TMIN |
| EMAC0CLIENTTXSTATS | output | TCELL4:OUT.BEST4.TMIN |
| EMAC0CLIENTTXSTATSBYTEVLD | output | TCELL0:OUT.SEC0.TMIN |
| EMAC0CLIENTTXSTATSVLD | output | TCELL0:OUT.BEST7.TMIN |
| EMAC0PHYENCOMMAALIGN | output | TCELL9:OUT.SEC4.TMIN |
| EMAC0PHYLOOPBACKMSB | output | TCELL3:OUT.BEST3.TMIN |
| EMAC0PHYMCLKOUT | output | TCELL5:OUT.BEST1.TMIN |
| EMAC0PHYMDOUT | output | TCELL5:OUT.BEST3.TMIN |
| EMAC0PHYMDTRI | output | TCELL5:OUT.BEST2.TMIN |
| EMAC0PHYMGTRXRESET | output | TCELL0:OUT.SEC4.TMIN |
| EMAC0PHYMGTTXRESET | output | TCELL1:OUT.SEC3.TMIN |
| EMAC0PHYPOWERDOWN | output | TCELL10:OUT.SEC4.TMIN |
| EMAC0PHYSYNCACQSTATUS | output | TCELL5:OUT.BEST0.TMIN |
| EMAC0PHYTXCHARDISPMODE | output | TCELL3:OUT.BEST0.TMIN |
| EMAC0PHYTXCHARDISPVAL | output | TCELL3:OUT.BEST1.TMIN |
| EMAC0PHYTXCHARISK | output | TCELL1:OUT.BEST4.TMIN |
| EMAC0PHYTXCLK | output | TCELL0:OUT.BEST4.TMIN |
| EMAC0PHYTXD0 | output | TCELL0:OUT.BEST0.TMIN |
| EMAC0PHYTXD1 | output | TCELL0:OUT.BEST1.TMIN |
| EMAC0PHYTXD2 | output | TCELL0:OUT.BEST2.TMIN |
| EMAC0PHYTXD3 | output | TCELL0:OUT.BEST3.TMIN |
| EMAC0PHYTXD4 | output | TCELL1:OUT.BEST0.TMIN |
| EMAC0PHYTXD5 | output | TCELL1:OUT.BEST1.TMIN |
| EMAC0PHYTXD6 | output | TCELL1:OUT.BEST2.TMIN |
| EMAC0PHYTXD7 | output | TCELL1:OUT.BEST3.TMIN |
| EMAC0PHYTXEN | output | TCELL0:OUT.BEST5.TMIN |
| EMAC0PHYTXER | output | TCELL0:OUT.BEST6.TMIN |
| EMAC0TIBUS0 | input | TCELL6:IMUX.CLK0 |
| EMAC0TIBUS1 | input | TCELL8:IMUX.CLK0 |
| EMAC0TIBUS2 | input | TCELL1:IMUX.IMUX9 |
| EMAC0TIBUS3 | input | TCELL1:IMUX.IMUX8 |
| EMAC0TIBUS4 | input | TCELL4:IMUX.IMUX15 |
| EMAC1CLIENTANINTERRUPT | output | TCELL14:OUT.SEC4.TMIN |
| EMAC1CLIENTRXBADFRAME | output | TCELL20:OUT.BEST7.TMIN |
| EMAC1CLIENTRXCLIENTCLKOUT | output | TCELL20:OUT.BEST4.TMIN |
| EMAC1CLIENTRXD0 | output | TCELL19:OUT.BEST0.TMIN |
| EMAC1CLIENTRXD1 | output | TCELL19:OUT.BEST1.TMIN |
| EMAC1CLIENTRXD10 | output | TCELL17:OUT.BEST6.TMIN |
| EMAC1CLIENTRXD11 | output | TCELL17:OUT.BEST7.TMIN |
| EMAC1CLIENTRXD12 | output | TCELL16:OUT.BEST4.TMIN |
| EMAC1CLIENTRXD13 | output | TCELL16:OUT.BEST5.TMIN |
| EMAC1CLIENTRXD14 | output | TCELL16:OUT.BEST6.TMIN |
| EMAC1CLIENTRXD15 | output | TCELL16:OUT.BEST7.TMIN |
| EMAC1CLIENTRXD2 | output | TCELL19:OUT.BEST2.TMIN |
| EMAC1CLIENTRXD3 | output | TCELL19:OUT.BEST3.TMIN |
| EMAC1CLIENTRXD4 | output | TCELL18:OUT.BEST4.TMIN |
| EMAC1CLIENTRXD5 | output | TCELL18:OUT.BEST5.TMIN |
| EMAC1CLIENTRXD6 | output | TCELL18:OUT.BEST6.TMIN |
| EMAC1CLIENTRXD7 | output | TCELL18:OUT.BEST7.TMIN |
| EMAC1CLIENTRXD8 | output | TCELL17:OUT.BEST4.TMIN |
| EMAC1CLIENTRXD9 | output | TCELL17:OUT.BEST5.TMIN |
| EMAC1CLIENTRXDVLD | output | TCELL22:OUT.BEST6.TMIN |
| EMAC1CLIENTRXDVLDMSW | output | TCELL22:OUT.BEST5.TMIN |
| EMAC1CLIENTRXDVREG6 | output | TCELL18:OUT.SEC4.TMIN |
| EMAC1CLIENTRXFRAMEDROP | output | TCELL20:OUT.BEST5.TMIN |
| EMAC1CLIENTRXGOODFRAME | output | TCELL20:OUT.BEST6.TMIN |
| EMAC1CLIENTRXSTATS0 | output | TCELL22:OUT.SEC0.TMIN |
| EMAC1CLIENTRXSTATS1 | output | TCELL22:OUT.SEC1.TMIN |
| EMAC1CLIENTRXSTATS2 | output | TCELL22:OUT.SEC2.TMIN |
| EMAC1CLIENTRXSTATS3 | output | TCELL22:OUT.SEC3.TMIN |
| EMAC1CLIENTRXSTATS4 | output | TCELL19:OUT.BEST6.TMIN |
| EMAC1CLIENTRXSTATS5 | output | TCELL19:OUT.BEST7.TMIN |
| EMAC1CLIENTRXSTATS6 | output | TCELL19:OUT.BEST5.TMIN |
| EMAC1CLIENTRXSTATSBYTEVLD | output | TCELL21:OUT.BEST6.TMIN |
| EMAC1CLIENTRXSTATSVLD | output | TCELL22:OUT.BEST7.TMIN |
| EMAC1CLIENTTXACK | output | TCELL21:OUT.BEST2.TMIN |
| EMAC1CLIENTTXCLIENTCLKOUT | output | TCELL21:OUT.BEST1.TMIN |
| EMAC1CLIENTTXCOLLISION | output | TCELL21:OUT.BEST3.TMIN |
| EMAC1CLIENTTXGMIIMIICLKOUT | output | TCELL20:OUT.BEST2.TMIN |
| EMAC1CLIENTTXRETRANSMIT | output | TCELL21:OUT.BEST4.TMIN |
| EMAC1CLIENTTXSTATS | output | TCELL19:OUT.BEST4.TMIN |
| EMAC1CLIENTTXSTATSBYTEVLD | output | TCELL21:OUT.BEST5.TMIN |
| EMAC1CLIENTTXSTATSVLD | output | TCELL21:OUT.BEST7.TMIN |
| EMAC1PHYENCOMMAALIGN | output | TCELL15:OUT.SEC4.TMIN |
| EMAC1PHYLOOPBACKMSB | output | TCELL20:OUT.BEST3.TMIN |
| EMAC1PHYMCLKOUT | output | TCELL18:OUT.BEST1.TMIN |
| EMAC1PHYMDOUT | output | TCELL18:OUT.BEST3.TMIN |
| EMAC1PHYMDTRI | output | TCELL18:OUT.BEST2.TMIN |
| EMAC1PHYMGTRXRESET | output | TCELL21:OUT.BEST0.TMIN |
| EMAC1PHYMGTTXRESET | output | TCELL23:OUT.SEC4.TMIN |
| EMAC1PHYPOWERDOWN | output | TCELL19:OUT.SEC4.TMIN |
| EMAC1PHYSYNCACQSTATUS | output | TCELL18:OUT.BEST0.TMIN |
| EMAC1PHYTXCHARDISPMODE | output | TCELL20:OUT.BEST0.TMIN |
| EMAC1PHYTXCHARDISPVAL | output | TCELL20:OUT.BEST1.TMIN |
| EMAC1PHYTXCHARISK | output | TCELL22:OUT.BEST4.TMIN |
| EMAC1PHYTXCLK | output | TCELL23:OUT.BEST4.TMIN |
| EMAC1PHYTXD0 | output | TCELL23:OUT.BEST0.TMIN |
| EMAC1PHYTXD1 | output | TCELL23:OUT.BEST1.TMIN |
| EMAC1PHYTXD2 | output | TCELL23:OUT.BEST2.TMIN |
| EMAC1PHYTXD3 | output | TCELL23:OUT.BEST3.TMIN |
| EMAC1PHYTXD4 | output | TCELL22:OUT.BEST0.TMIN |
| EMAC1PHYTXD5 | output | TCELL22:OUT.BEST1.TMIN |
| EMAC1PHYTXD6 | output | TCELL22:OUT.BEST2.TMIN |
| EMAC1PHYTXD7 | output | TCELL22:OUT.BEST3.TMIN |
| EMAC1PHYTXEN | output | TCELL23:OUT.BEST5.TMIN |
| EMAC1PHYTXER | output | TCELL23:OUT.BEST6.TMIN |
| EMAC1TIBUS0 | input | TCELL17:IMUX.CLK0 |
| EMAC1TIBUS1 | input | TCELL18:IMUX.CLK0 |
| EMAC1TIBUS2 | input | TCELL22:IMUX.IMUX9 |
| EMAC1TIBUS3 | input | TCELL22:IMUX.IMUX8 |
| EMAC1TIBUS4 | input | TCELL15:IMUX.IMUX15 |
| HOSTADDR0 | input | TCELL6:IMUX.IMUX0 |
| HOSTADDR1 | input | TCELL6:IMUX.IMUX1 |
| HOSTADDR2 | input | TCELL6:IMUX.IMUX2 |
| HOSTADDR3 | input | TCELL6:IMUX.IMUX3 |
| HOSTADDR4 | input | TCELL6:IMUX.IMUX4 |
| HOSTADDR5 | input | TCELL6:IMUX.IMUX5 |
| HOSTADDR6 | input | TCELL6:IMUX.IMUX6 |
| HOSTADDR7 | input | TCELL6:IMUX.IMUX7 |
| HOSTADDR8 | input | TCELL6:IMUX.IMUX8 |
| HOSTADDR9 | input | TCELL6:IMUX.IMUX9 |
| HOSTCLK | input | TCELL16:IMUX.CLK0 |
| HOSTEMAC1SEL | input | TCELL17:IMUX.IMUX10 |
| HOSTMIIMRDY | output | TCELL2:OUT.BEST6.TMIN |
| HOSTMIIMSEL | input | TCELL17:IMUX.IMUX8 |
| HOSTOPCODE0 | input | TCELL17:IMUX.IMUX7 |
| HOSTOPCODE1 | input | TCELL17:IMUX.IMUX6 |
| HOSTRDDATA0 | output | TCELL6:OUT.BEST0.TMIN |
| HOSTRDDATA1 | output | TCELL6:OUT.BEST1.TMIN |
| HOSTRDDATA10 | output | TCELL7:OUT.BEST2.TMIN |
| HOSTRDDATA11 | output | TCELL7:OUT.BEST3.TMIN |
| HOSTRDDATA12 | output | TCELL7:OUT.SEC0.TMIN |
| HOSTRDDATA13 | output | TCELL7:OUT.SEC1.TMIN |
| HOSTRDDATA14 | output | TCELL7:OUT.SEC2.TMIN |
| HOSTRDDATA15 | output | TCELL7:OUT.SEC3.TMIN |
| HOSTRDDATA16 | output | TCELL16:OUT.BEST0.TMIN |
| HOSTRDDATA17 | output | TCELL16:OUT.BEST1.TMIN |
| HOSTRDDATA18 | output | TCELL16:OUT.BEST2.TMIN |
| HOSTRDDATA19 | output | TCELL16:OUT.BEST3.TMIN |
| HOSTRDDATA2 | output | TCELL6:OUT.BEST2.TMIN |
| HOSTRDDATA20 | output | TCELL16:OUT.SEC0.TMIN |
| HOSTRDDATA21 | output | TCELL16:OUT.SEC1.TMIN |
| HOSTRDDATA22 | output | TCELL16:OUT.SEC2.TMIN |
| HOSTRDDATA23 | output | TCELL16:OUT.SEC3.TMIN |
| HOSTRDDATA24 | output | TCELL17:OUT.BEST0.TMIN |
| HOSTRDDATA25 | output | TCELL17:OUT.BEST1.TMIN |
| HOSTRDDATA26 | output | TCELL17:OUT.BEST2.TMIN |
| HOSTRDDATA27 | output | TCELL17:OUT.BEST3.TMIN |
| HOSTRDDATA28 | output | TCELL17:OUT.SEC0.TMIN |
| HOSTRDDATA29 | output | TCELL17:OUT.SEC1.TMIN |
| HOSTRDDATA3 | output | TCELL6:OUT.BEST7.TMIN |
| HOSTRDDATA30 | output | TCELL17:OUT.SEC2.TMIN |
| HOSTRDDATA31 | output | TCELL17:OUT.SEC3.TMIN |
| HOSTRDDATA4 | output | TCELL6:OUT.SEC0.TMIN |
| HOSTRDDATA5 | output | TCELL6:OUT.SEC1.TMIN |
| HOSTRDDATA6 | output | TCELL6:OUT.SEC2.TMIN |
| HOSTRDDATA7 | output | TCELL6:OUT.SEC3.TMIN |
| HOSTRDDATA8 | output | TCELL7:OUT.BEST0.TMIN |
| HOSTRDDATA9 | output | TCELL7:OUT.BEST1.TMIN |
| HOSTREQ | input | TCELL17:IMUX.IMUX9 |
| HOSTWRDATA0 | input | TCELL6:IMUX.IMUX10 |
| HOSTWRDATA1 | input | TCELL6:IMUX.IMUX11 |
| HOSTWRDATA10 | input | TCELL7:IMUX.IMUX8 |
| HOSTWRDATA11 | input | TCELL7:IMUX.IMUX9 |
| HOSTWRDATA12 | input | TCELL7:IMUX.IMUX10 |
| HOSTWRDATA13 | input | TCELL7:IMUX.IMUX11 |
| HOSTWRDATA14 | input | TCELL16:IMUX.IMUX0 |
| HOSTWRDATA15 | input | TCELL16:IMUX.IMUX1 |
| HOSTWRDATA16 | input | TCELL16:IMUX.IMUX2 |
| HOSTWRDATA17 | input | TCELL16:IMUX.IMUX3 |
| HOSTWRDATA18 | input | TCELL16:IMUX.IMUX4 |
| HOSTWRDATA19 | input | TCELL16:IMUX.IMUX5 |
| HOSTWRDATA2 | input | TCELL7:IMUX.IMUX0 |
| HOSTWRDATA20 | input | TCELL16:IMUX.IMUX6 |
| HOSTWRDATA21 | input | TCELL16:IMUX.IMUX7 |
| HOSTWRDATA22 | input | TCELL16:IMUX.IMUX8 |
| HOSTWRDATA23 | input | TCELL16:IMUX.IMUX9 |
| HOSTWRDATA24 | input | TCELL16:IMUX.IMUX10 |
| HOSTWRDATA25 | input | TCELL16:IMUX.IMUX11 |
| HOSTWRDATA26 | input | TCELL17:IMUX.IMUX0 |
| HOSTWRDATA27 | input | TCELL17:IMUX.IMUX1 |
| HOSTWRDATA28 | input | TCELL17:IMUX.IMUX2 |
| HOSTWRDATA29 | input | TCELL17:IMUX.IMUX3 |
| HOSTWRDATA3 | input | TCELL7:IMUX.IMUX1 |
| HOSTWRDATA30 | input | TCELL17:IMUX.IMUX4 |
| HOSTWRDATA31 | input | TCELL17:IMUX.IMUX5 |
| HOSTWRDATA4 | input | TCELL7:IMUX.IMUX2 |
| HOSTWRDATA5 | input | TCELL7:IMUX.IMUX3 |
| HOSTWRDATA6 | input | TCELL7:IMUX.IMUX4 |
| HOSTWRDATA7 | input | TCELL7:IMUX.IMUX5 |
| HOSTWRDATA8 | input | TCELL7:IMUX.IMUX6 |
| HOSTWRDATA9 | input | TCELL7:IMUX.IMUX7 |
| PHYEMAC0COL | input | TCELL0:IMUX.IMUX5 |
| PHYEMAC0CRS | input | TCELL0:IMUX.IMUX4 |
| PHYEMAC0GTXCLK | input | TCELL15:IMUX.CLK0 |
| PHYEMAC0MCLKIN | input | TCELL9:IMUX.CLK0 |
| PHYEMAC0MDIN | input | TCELL3:IMUX.IMUX4 |
| PHYEMAC0MIITXCLK | input | TCELL13:IMUX.CLK0 |
| PHYEMAC0PHYAD0 | input | TCELL1:IMUX.IMUX14 |
| PHYEMAC0PHYAD1 | input | TCELL1:IMUX.IMUX15 |
| PHYEMAC0PHYAD2 | input | TCELL0:IMUX.IMUX6 |
| PHYEMAC0PHYAD3 | input | TCELL0:IMUX.IMUX7 |
| PHYEMAC0PHYAD4 | input | TCELL0:IMUX.IMUX8 |
| PHYEMAC0RXBUFERR | input | TCELL8:IMUX.IMUX10 |
| PHYEMAC0RXBUFSTATUS0 | input | TCELL2:IMUX.IMUX6 |
| PHYEMAC0RXBUFSTATUS1 | input | TCELL2:IMUX.IMUX7 |
| PHYEMAC0RXCHARISCOMMA | input | TCELL2:IMUX.IMUX3 |
| PHYEMAC0RXCHARISK | input | TCELL2:IMUX.IMUX2 |
| PHYEMAC0RXCHECKINGCRC | input | TCELL1:IMUX.IMUX7 |
| PHYEMAC0RXCLK | input | TCELL14:IMUX.CLK0 |
| PHYEMAC0RXCLKCORCNT0 | input | TCELL3:IMUX.IMUX1 |
| PHYEMAC0RXCLKCORCNT1 | input | TCELL8:IMUX.IMUX8 |
| PHYEMAC0RXCLKCORCNT2 | input | TCELL8:IMUX.IMUX9 |
| PHYEMAC0RXCOMMADET | input | TCELL1:IMUX.IMUX6 |
| PHYEMAC0RXD0 | input | TCELL0:IMUX.IMUX0 |
| PHYEMAC0RXD1 | input | TCELL0:IMUX.IMUX1 |
| PHYEMAC0RXD2 | input | TCELL0:IMUX.IMUX2 |
| PHYEMAC0RXD3 | input | TCELL0:IMUX.IMUX3 |
| PHYEMAC0RXD4 | input | TCELL1:IMUX.IMUX0 |
| PHYEMAC0RXD5 | input | TCELL1:IMUX.IMUX1 |
| PHYEMAC0RXD6 | input | TCELL1:IMUX.IMUX2 |
| PHYEMAC0RXD7 | input | TCELL1:IMUX.IMUX3 |
| PHYEMAC0RXDISPERR | input | TCELL2:IMUX.IMUX1 |
| PHYEMAC0RXDV | input | TCELL1:IMUX.IMUX4 |
| PHYEMAC0RXER | input | TCELL1:IMUX.IMUX5 |
| PHYEMAC0RXLOSSOFSYNC0 | input | TCELL2:IMUX.IMUX4 |
| PHYEMAC0RXLOSSOFSYNC1 | input | TCELL2:IMUX.IMUX5 |
| PHYEMAC0RXNOTINTABLE | input | TCELL2:IMUX.IMUX0 |
| PHYEMAC0RXRUNDISP | input | TCELL3:IMUX.IMUX2 |
| PHYEMAC0SIGNALDET | input | TCELL2:IMUX.IMUX15 |
| PHYEMAC0TXBUFERR | input | TCELL3:IMUX.IMUX3 |
| PHYEMAC1COL | input | TCELL23:IMUX.IMUX5 |
| PHYEMAC1CRS | input | TCELL23:IMUX.IMUX4 |
| PHYEMAC1GTXCLK | input | TCELL57:IMUX.CLK0 |
| PHYEMAC1MCLKIN | input | TCELL19:IMUX.CLK0 |
| PHYEMAC1MDIN | input | TCELL20:IMUX.IMUX4 |
| PHYEMAC1MIITXCLK | input | TCELL59:IMUX.CLK0 |
| PHYEMAC1PHYAD0 | input | TCELL22:IMUX.IMUX15 |
| PHYEMAC1PHYAD1 | input | TCELL22:IMUX.IMUX14 |
| PHYEMAC1PHYAD2 | input | TCELL23:IMUX.IMUX14 |
| PHYEMAC1PHYAD3 | input | TCELL23:IMUX.IMUX13 |
| PHYEMAC1PHYAD4 | input | TCELL23:IMUX.IMUX12 |
| PHYEMAC1RXBUFERR | input | TCELL20:IMUX.IMUX12 |
| PHYEMAC1RXBUFSTATUS0 | input | TCELL21:IMUX.IMUX4 |
| PHYEMAC1RXBUFSTATUS1 | input | TCELL21:IMUX.IMUX5 |
| PHYEMAC1RXCHARISCOMMA | input | TCELL21:IMUX.IMUX3 |
| PHYEMAC1RXCHARISK | input | TCELL21:IMUX.IMUX2 |
| PHYEMAC1RXCHECKINGCRC | input | TCELL22:IMUX.IMUX7 |
| PHYEMAC1RXCLK | input | TCELL58:IMUX.CLK0 |
| PHYEMAC1RXCLKCORCNT0 | input | TCELL20:IMUX.IMUX1 |
| PHYEMAC1RXCLKCORCNT1 | input | TCELL21:IMUX.IMUX12 |
| PHYEMAC1RXCLKCORCNT2 | input | TCELL21:IMUX.IMUX13 |
| PHYEMAC1RXCOMMADET | input | TCELL22:IMUX.IMUX6 |
| PHYEMAC1RXD0 | input | TCELL23:IMUX.IMUX0 |
| PHYEMAC1RXD1 | input | TCELL23:IMUX.IMUX1 |
| PHYEMAC1RXD2 | input | TCELL23:IMUX.IMUX2 |
| PHYEMAC1RXD3 | input | TCELL23:IMUX.IMUX3 |
| PHYEMAC1RXD4 | input | TCELL22:IMUX.IMUX0 |
| PHYEMAC1RXD5 | input | TCELL22:IMUX.IMUX1 |
| PHYEMAC1RXD6 | input | TCELL22:IMUX.IMUX2 |
| PHYEMAC1RXD7 | input | TCELL22:IMUX.IMUX3 |
| PHYEMAC1RXDISPERR | input | TCELL21:IMUX.IMUX1 |
| PHYEMAC1RXDV | input | TCELL22:IMUX.IMUX4 |
| PHYEMAC1RXER | input | TCELL22:IMUX.IMUX5 |
| PHYEMAC1RXLOSSOFSYNC0 | input | TCELL21:IMUX.IMUX6 |
| PHYEMAC1RXLOSSOFSYNC1 | input | TCELL21:IMUX.IMUX7 |
| PHYEMAC1RXNOTINTABLE | input | TCELL21:IMUX.IMUX0 |
| PHYEMAC1RXRUNDISP | input | TCELL20:IMUX.IMUX2 |
| PHYEMAC1SIGNALDET | input | TCELL19:IMUX.IMUX12 |
| PHYEMAC1TXBUFERR | input | TCELL20:IMUX.IMUX3 |
| RESET | input | TCELL2:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC0 | input | TCELL0:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC1 | input | TCELL0:IMUX.IMUX13 |
| TIEEMAC0CONFIGVEC10 | input | TCELL0:IMUX.SR2 |
| TIEEMAC0CONFIGVEC11 | input | TCELL0:IMUX.SR3 |
| TIEEMAC0CONFIGVEC12 | input | TCELL5:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC13 | input | TCELL5:IMUX.IMUX13 |
| TIEEMAC0CONFIGVEC14 | input | TCELL5:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC15 | input | TCELL5:IMUX.IMUX15 |
| TIEEMAC0CONFIGVEC16 | input | TCELL6:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC17 | input | TCELL6:IMUX.IMUX13 |
| TIEEMAC0CONFIGVEC18 | input | TCELL6:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC19 | input | TCELL6:IMUX.IMUX15 |
| TIEEMAC0CONFIGVEC2 | input | TCELL0:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC20 | input | TCELL48:IMUX.CE0 |
| TIEEMAC0CONFIGVEC21 | input | TCELL48:IMUX.CE1 |
| TIEEMAC0CONFIGVEC22 | input | TCELL48:IMUX.CE2 |
| TIEEMAC0CONFIGVEC23 | input | TCELL48:IMUX.CE3 |
| TIEEMAC0CONFIGVEC24 | input | TCELL48:IMUX.SR0 |
| TIEEMAC0CONFIGVEC25 | input | TCELL48:IMUX.SR1 |
| TIEEMAC0CONFIGVEC26 | input | TCELL48:IMUX.SR2 |
| TIEEMAC0CONFIGVEC27 | input | TCELL48:IMUX.SR3 |
| TIEEMAC0CONFIGVEC28 | input | TCELL49:IMUX.CE0 |
| TIEEMAC0CONFIGVEC29 | input | TCELL49:IMUX.CE1 |
| TIEEMAC0CONFIGVEC3 | input | TCELL0:IMUX.IMUX15 |
| TIEEMAC0CONFIGVEC30 | input | TCELL49:IMUX.CE2 |
| TIEEMAC0CONFIGVEC31 | input | TCELL49:IMUX.CE3 |
| TIEEMAC0CONFIGVEC32 | input | TCELL49:IMUX.SR0 |
| TIEEMAC0CONFIGVEC33 | input | TCELL49:IMUX.SR1 |
| TIEEMAC0CONFIGVEC34 | input | TCELL49:IMUX.SR2 |
| TIEEMAC0CONFIGVEC35 | input | TCELL49:IMUX.SR3 |
| TIEEMAC0CONFIGVEC36 | input | TCELL50:IMUX.CE3 |
| TIEEMAC0CONFIGVEC37 | input | TCELL50:IMUX.SR0 |
| TIEEMAC0CONFIGVEC38 | input | TCELL50:IMUX.SR1 |
| TIEEMAC0CONFIGVEC39 | input | TCELL50:IMUX.SR2 |
| TIEEMAC0CONFIGVEC4 | input | TCELL0:IMUX.CE0 |
| TIEEMAC0CONFIGVEC40 | input | TCELL50:IMUX.SR3 |
| TIEEMAC0CONFIGVEC41 | input | TCELL51:IMUX.CE0 |
| TIEEMAC0CONFIGVEC42 | input | TCELL51:IMUX.CE1 |
| TIEEMAC0CONFIGVEC43 | input | TCELL51:IMUX.CE2 |
| TIEEMAC0CONFIGVEC44 | input | TCELL51:IMUX.CE3 |
| TIEEMAC0CONFIGVEC45 | input | TCELL51:IMUX.SR0 |
| TIEEMAC0CONFIGVEC46 | input | TCELL51:IMUX.SR1 |
| TIEEMAC0CONFIGVEC47 | input | TCELL51:IMUX.SR2 |
| TIEEMAC0CONFIGVEC48 | input | TCELL51:IMUX.SR3 |
| TIEEMAC0CONFIGVEC49 | input | TCELL8:IMUX.SR0 |
| TIEEMAC0CONFIGVEC5 | input | TCELL0:IMUX.CE1 |
| TIEEMAC0CONFIGVEC50 | input | TCELL8:IMUX.SR1 |
| TIEEMAC0CONFIGVEC51 | input | TCELL8:IMUX.SR2 |
| TIEEMAC0CONFIGVEC52 | input | TCELL8:IMUX.SR3 |
| TIEEMAC0CONFIGVEC53 | input | TCELL9:IMUX.SR0 |
| TIEEMAC0CONFIGVEC54 | input | TCELL9:IMUX.SR1 |
| TIEEMAC0CONFIGVEC55 | input | TCELL9:IMUX.SR2 |
| TIEEMAC0CONFIGVEC56 | input | TCELL9:IMUX.SR3 |
| TIEEMAC0CONFIGVEC57 | input | TCELL10:IMUX.SR0 |
| TIEEMAC0CONFIGVEC58 | input | TCELL10:IMUX.SR1 |
| TIEEMAC0CONFIGVEC59 | input | TCELL10:IMUX.SR2 |
| TIEEMAC0CONFIGVEC6 | input | TCELL0:IMUX.CE2 |
| TIEEMAC0CONFIGVEC60 | input | TCELL10:IMUX.SR3 |
| TIEEMAC0CONFIGVEC61 | input | TCELL10:IMUX.IMUX8 |
| TIEEMAC0CONFIGVEC62 | input | TCELL10:IMUX.IMUX9 |
| TIEEMAC0CONFIGVEC63 | input | TCELL7:IMUX.CE2 |
| TIEEMAC0CONFIGVEC64 | input | TCELL3:IMUX.IMUX9 |
| TIEEMAC0CONFIGVEC65 | input | TCELL3:IMUX.IMUX10 |
| TIEEMAC0CONFIGVEC66 | input | TCELL3:IMUX.IMUX11 |
| TIEEMAC0CONFIGVEC67 | input | TCELL3:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC68 | input | TCELL3:IMUX.IMUX13 |
| TIEEMAC0CONFIGVEC69 | input | TCELL3:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC7 | input | TCELL0:IMUX.CE3 |
| TIEEMAC0CONFIGVEC70 | input | TCELL4:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC71 | input | TCELL4:IMUX.IMUX13 |
| TIEEMAC0CONFIGVEC72 | input | TCELL4:IMUX.IMUX14 |
| TIEEMAC0CONFIGVEC73 | input | TCELL9:IMUX.IMUX9 |
| TIEEMAC0CONFIGVEC74 | input | TCELL9:IMUX.IMUX10 |
| TIEEMAC0CONFIGVEC75 | input | TCELL9:IMUX.IMUX11 |
| TIEEMAC0CONFIGVEC76 | input | TCELL9:IMUX.IMUX12 |
| TIEEMAC0CONFIGVEC77 | input | TCELL10:IMUX.IMUX5 |
| TIEEMAC0CONFIGVEC78 | input | TCELL10:IMUX.IMUX6 |
| TIEEMAC0CONFIGVEC79 | input | TCELL10:IMUX.IMUX7 |
| TIEEMAC0CONFIGVEC8 | input | TCELL0:IMUX.SR0 |
| TIEEMAC0CONFIGVEC9 | input | TCELL0:IMUX.SR1 |
| TIEEMAC0UNICASTADDR0 | input | TCELL6:IMUX.SR1 |
| TIEEMAC0UNICASTADDR1 | input | TCELL6:IMUX.SR2 |
| TIEEMAC0UNICASTADDR10 | input | TCELL5:IMUX.SR3 |
| TIEEMAC0UNICASTADDR11 | input | TCELL4:IMUX.CE0 |
| TIEEMAC0UNICASTADDR12 | input | TCELL4:IMUX.CE1 |
| TIEEMAC0UNICASTADDR13 | input | TCELL4:IMUX.CE2 |
| TIEEMAC0UNICASTADDR14 | input | TCELL4:IMUX.CE3 |
| TIEEMAC0UNICASTADDR15 | input | TCELL4:IMUX.SR0 |
| TIEEMAC0UNICASTADDR16 | input | TCELL4:IMUX.SR1 |
| TIEEMAC0UNICASTADDR17 | input | TCELL4:IMUX.SR2 |
| TIEEMAC0UNICASTADDR18 | input | TCELL4:IMUX.SR3 |
| TIEEMAC0UNICASTADDR19 | input | TCELL2:IMUX.IMUX13 |
| TIEEMAC0UNICASTADDR2 | input | TCELL6:IMUX.SR3 |
| TIEEMAC0UNICASTADDR20 | input | TCELL3:IMUX.CE0 |
| TIEEMAC0UNICASTADDR21 | input | TCELL3:IMUX.CE1 |
| TIEEMAC0UNICASTADDR22 | input | TCELL3:IMUX.CE2 |
| TIEEMAC0UNICASTADDR23 | input | TCELL3:IMUX.CE3 |
| TIEEMAC0UNICASTADDR24 | input | TCELL3:IMUX.SR0 |
| TIEEMAC0UNICASTADDR25 | input | TCELL3:IMUX.SR1 |
| TIEEMAC0UNICASTADDR26 | input | TCELL3:IMUX.SR2 |
| TIEEMAC0UNICASTADDR27 | input | TCELL3:IMUX.SR3 |
| TIEEMAC0UNICASTADDR28 | input | TCELL2:IMUX.IMUX12 |
| TIEEMAC0UNICASTADDR29 | input | TCELL2:IMUX.CE0 |
| TIEEMAC0UNICASTADDR3 | input | TCELL5:IMUX.CE0 |
| TIEEMAC0UNICASTADDR30 | input | TCELL2:IMUX.CE1 |
| TIEEMAC0UNICASTADDR31 | input | TCELL2:IMUX.CE2 |
| TIEEMAC0UNICASTADDR32 | input | TCELL2:IMUX.CE3 |
| TIEEMAC0UNICASTADDR33 | input | TCELL2:IMUX.SR0 |
| TIEEMAC0UNICASTADDR34 | input | TCELL2:IMUX.SR1 |
| TIEEMAC0UNICASTADDR35 | input | TCELL2:IMUX.SR2 |
| TIEEMAC0UNICASTADDR36 | input | TCELL2:IMUX.SR3 |
| TIEEMAC0UNICASTADDR37 | input | TCELL1:IMUX.CE0 |
| TIEEMAC0UNICASTADDR38 | input | TCELL1:IMUX.CE1 |
| TIEEMAC0UNICASTADDR39 | input | TCELL1:IMUX.CE2 |
| TIEEMAC0UNICASTADDR4 | input | TCELL5:IMUX.CE1 |
| TIEEMAC0UNICASTADDR40 | input | TCELL1:IMUX.CE3 |
| TIEEMAC0UNICASTADDR41 | input | TCELL1:IMUX.SR0 |
| TIEEMAC0UNICASTADDR42 | input | TCELL1:IMUX.SR1 |
| TIEEMAC0UNICASTADDR43 | input | TCELL1:IMUX.SR2 |
| TIEEMAC0UNICASTADDR44 | input | TCELL1:IMUX.SR3 |
| TIEEMAC0UNICASTADDR45 | input | TCELL0:IMUX.IMUX9 |
| TIEEMAC0UNICASTADDR46 | input | TCELL0:IMUX.IMUX10 |
| TIEEMAC0UNICASTADDR47 | input | TCELL0:IMUX.IMUX11 |
| TIEEMAC0UNICASTADDR5 | input | TCELL5:IMUX.CE2 |
| TIEEMAC0UNICASTADDR6 | input | TCELL5:IMUX.CE3 |
| TIEEMAC0UNICASTADDR7 | input | TCELL5:IMUX.SR0 |
| TIEEMAC0UNICASTADDR8 | input | TCELL5:IMUX.SR1 |
| TIEEMAC0UNICASTADDR9 | input | TCELL5:IMUX.SR2 |
| TIEEMAC1CONFIGVEC0 | input | TCELL21:IMUX.CE3 |
| TIEEMAC1CONFIGVEC1 | input | TCELL21:IMUX.CE2 |
| TIEEMAC1CONFIGVEC10 | input | TCELL22:IMUX.CE1 |
| TIEEMAC1CONFIGVEC11 | input | TCELL22:IMUX.CE0 |
| TIEEMAC1CONFIGVEC12 | input | TCELL23:IMUX.SR3 |
| TIEEMAC1CONFIGVEC13 | input | TCELL23:IMUX.SR2 |
| TIEEMAC1CONFIGVEC14 | input | TCELL23:IMUX.SR1 |
| TIEEMAC1CONFIGVEC15 | input | TCELL23:IMUX.SR0 |
| TIEEMAC1CONFIGVEC16 | input | TCELL23:IMUX.CE3 |
| TIEEMAC1CONFIGVEC17 | input | TCELL23:IMUX.CE2 |
| TIEEMAC1CONFIGVEC18 | input | TCELL23:IMUX.CE1 |
| TIEEMAC1CONFIGVEC19 | input | TCELL23:IMUX.CE0 |
| TIEEMAC1CONFIGVEC2 | input | TCELL21:IMUX.CE1 |
| TIEEMAC1CONFIGVEC20 | input | TCELL23:IMUX.IMUX11 |
| TIEEMAC1CONFIGVEC21 | input | TCELL23:IMUX.IMUX10 |
| TIEEMAC1CONFIGVEC22 | input | TCELL23:IMUX.IMUX9 |
| TIEEMAC1CONFIGVEC23 | input | TCELL23:IMUX.IMUX8 |
| TIEEMAC1CONFIGVEC24 | input | TCELL23:IMUX.IMUX7 |
| TIEEMAC1CONFIGVEC25 | input | TCELL23:IMUX.IMUX6 |
| TIEEMAC1CONFIGVEC26 | input | TCELL59:IMUX.SR3 |
| TIEEMAC1CONFIGVEC27 | input | TCELL59:IMUX.SR2 |
| TIEEMAC1CONFIGVEC28 | input | TCELL59:IMUX.SR1 |
| TIEEMAC1CONFIGVEC29 | input | TCELL59:IMUX.SR0 |
| TIEEMAC1CONFIGVEC3 | input | TCELL21:IMUX.CE0 |
| TIEEMAC1CONFIGVEC30 | input | TCELL59:IMUX.CE3 |
| TIEEMAC1CONFIGVEC31 | input | TCELL59:IMUX.CE2 |
| TIEEMAC1CONFIGVEC32 | input | TCELL59:IMUX.CE1 |
| TIEEMAC1CONFIGVEC33 | input | TCELL59:IMUX.CE0 |
| TIEEMAC1CONFIGVEC34 | input | TCELL60:IMUX.SR3 |
| TIEEMAC1CONFIGVEC35 | input | TCELL60:IMUX.SR2 |
| TIEEMAC1CONFIGVEC36 | input | TCELL60:IMUX.SR1 |
| TIEEMAC1CONFIGVEC37 | input | TCELL60:IMUX.SR0 |
| TIEEMAC1CONFIGVEC38 | input | TCELL60:IMUX.CE3 |
| TIEEMAC1CONFIGVEC39 | input | TCELL60:IMUX.CE2 |
| TIEEMAC1CONFIGVEC4 | input | TCELL22:IMUX.SR3 |
| TIEEMAC1CONFIGVEC40 | input | TCELL60:IMUX.CE1 |
| TIEEMAC1CONFIGVEC41 | input | TCELL60:IMUX.CE0 |
| TIEEMAC1CONFIGVEC42 | input | TCELL61:IMUX.SR3 |
| TIEEMAC1CONFIGVEC43 | input | TCELL61:IMUX.SR2 |
| TIEEMAC1CONFIGVEC44 | input | TCELL61:IMUX.SR1 |
| TIEEMAC1CONFIGVEC45 | input | TCELL61:IMUX.SR0 |
| TIEEMAC1CONFIGVEC46 | input | TCELL61:IMUX.CE3 |
| TIEEMAC1CONFIGVEC47 | input | TCELL61:IMUX.CE2 |
| TIEEMAC1CONFIGVEC48 | input | TCELL61:IMUX.CE1 |
| TIEEMAC1CONFIGVEC49 | input | TCELL61:IMUX.CE0 |
| TIEEMAC1CONFIGVEC5 | input | TCELL22:IMUX.SR2 |
| TIEEMAC1CONFIGVEC50 | input | TCELL15:IMUX.SR3 |
| TIEEMAC1CONFIGVEC51 | input | TCELL15:IMUX.SR2 |
| TIEEMAC1CONFIGVEC52 | input | TCELL15:IMUX.SR1 |
| TIEEMAC1CONFIGVEC53 | input | TCELL13:IMUX.SR3 |
| TIEEMAC1CONFIGVEC54 | input | TCELL13:IMUX.SR2 |
| TIEEMAC1CONFIGVEC55 | input | TCELL13:IMUX.SR1 |
| TIEEMAC1CONFIGVEC56 | input | TCELL13:IMUX.SR0 |
| TIEEMAC1CONFIGVEC57 | input | TCELL12:IMUX.SR3 |
| TIEEMAC1CONFIGVEC58 | input | TCELL12:IMUX.SR2 |
| TIEEMAC1CONFIGVEC59 | input | TCELL12:IMUX.SR1 |
| TIEEMAC1CONFIGVEC6 | input | TCELL22:IMUX.SR1 |
| TIEEMAC1CONFIGVEC60 | input | TCELL12:IMUX.SR0 |
| TIEEMAC1CONFIGVEC61 | input | TCELL11:IMUX.SR3 |
| TIEEMAC1CONFIGVEC62 | input | TCELL12:IMUX.IMUX4 |
| TIEEMAC1CONFIGVEC63 | input | TCELL15:IMUX.SR0 |
| TIEEMAC1CONFIGVEC64 | input | TCELL15:IMUX.IMUX6 |
| TIEEMAC1CONFIGVEC65 | input | TCELL15:IMUX.IMUX7 |
| TIEEMAC1CONFIGVEC66 | input | TCELL15:IMUX.IMUX8 |
| TIEEMAC1CONFIGVEC67 | input | TCELL15:IMUX.IMUX9 |
| TIEEMAC1CONFIGVEC68 | input | TCELL15:IMUX.IMUX10 |
| TIEEMAC1CONFIGVEC69 | input | TCELL15:IMUX.IMUX11 |
| TIEEMAC1CONFIGVEC7 | input | TCELL22:IMUX.SR0 |
| TIEEMAC1CONFIGVEC70 | input | TCELL15:IMUX.IMUX12 |
| TIEEMAC1CONFIGVEC71 | input | TCELL15:IMUX.IMUX13 |
| TIEEMAC1CONFIGVEC72 | input | TCELL15:IMUX.IMUX14 |
| TIEEMAC1CONFIGVEC73 | input | TCELL13:IMUX.IMUX4 |
| TIEEMAC1CONFIGVEC74 | input | TCELL13:IMUX.IMUX5 |
| TIEEMAC1CONFIGVEC75 | input | TCELL13:IMUX.IMUX6 |
| TIEEMAC1CONFIGVEC76 | input | TCELL13:IMUX.IMUX7 |
| TIEEMAC1CONFIGVEC77 | input | TCELL20:IMUX.IMUX9 |
| TIEEMAC1CONFIGVEC78 | input | TCELL20:IMUX.IMUX10 |
| TIEEMAC1CONFIGVEC79 | input | TCELL20:IMUX.IMUX11 |
| TIEEMAC1CONFIGVEC8 | input | TCELL22:IMUX.CE3 |
| TIEEMAC1CONFIGVEC9 | input | TCELL22:IMUX.CE2 |
| TIEEMAC1UNICASTADDR0 | input | TCELL7:IMUX.SR3 |
| TIEEMAC1UNICASTADDR1 | input | TCELL7:IMUX.SR2 |
| TIEEMAC1UNICASTADDR10 | input | TCELL16:IMUX.CE1 |
| TIEEMAC1UNICASTADDR11 | input | TCELL16:IMUX.CE0 |
| TIEEMAC1UNICASTADDR12 | input | TCELL17:IMUX.SR3 |
| TIEEMAC1UNICASTADDR13 | input | TCELL17:IMUX.SR2 |
| TIEEMAC1UNICASTADDR14 | input | TCELL17:IMUX.SR1 |
| TIEEMAC1UNICASTADDR15 | input | TCELL17:IMUX.SR0 |
| TIEEMAC1UNICASTADDR16 | input | TCELL17:IMUX.CE3 |
| TIEEMAC1UNICASTADDR17 | input | TCELL17:IMUX.CE2 |
| TIEEMAC1UNICASTADDR18 | input | TCELL17:IMUX.CE1 |
| TIEEMAC1UNICASTADDR19 | input | TCELL17:IMUX.CE0 |
| TIEEMAC1UNICASTADDR2 | input | TCELL7:IMUX.SR1 |
| TIEEMAC1UNICASTADDR20 | input | TCELL18:IMUX.SR3 |
| TIEEMAC1UNICASTADDR21 | input | TCELL18:IMUX.SR2 |
| TIEEMAC1UNICASTADDR22 | input | TCELL18:IMUX.SR1 |
| TIEEMAC1UNICASTADDR23 | input | TCELL18:IMUX.SR0 |
| TIEEMAC1UNICASTADDR24 | input | TCELL18:IMUX.CE3 |
| TIEEMAC1UNICASTADDR25 | input | TCELL18:IMUX.CE2 |
| TIEEMAC1UNICASTADDR26 | input | TCELL18:IMUX.CE1 |
| TIEEMAC1UNICASTADDR27 | input | TCELL18:IMUX.CE0 |
| TIEEMAC1UNICASTADDR28 | input | TCELL19:IMUX.SR3 |
| TIEEMAC1UNICASTADDR29 | input | TCELL19:IMUX.SR2 |
| TIEEMAC1UNICASTADDR3 | input | TCELL7:IMUX.SR0 |
| TIEEMAC1UNICASTADDR30 | input | TCELL19:IMUX.SR1 |
| TIEEMAC1UNICASTADDR31 | input | TCELL19:IMUX.SR0 |
| TIEEMAC1UNICASTADDR32 | input | TCELL19:IMUX.CE3 |
| TIEEMAC1UNICASTADDR33 | input | TCELL19:IMUX.CE2 |
| TIEEMAC1UNICASTADDR34 | input | TCELL19:IMUX.CE1 |
| TIEEMAC1UNICASTADDR35 | input | TCELL19:IMUX.CE0 |
| TIEEMAC1UNICASTADDR36 | input | TCELL20:IMUX.SR3 |
| TIEEMAC1UNICASTADDR37 | input | TCELL20:IMUX.SR2 |
| TIEEMAC1UNICASTADDR38 | input | TCELL20:IMUX.SR1 |
| TIEEMAC1UNICASTADDR39 | input | TCELL20:IMUX.SR0 |
| TIEEMAC1UNICASTADDR4 | input | TCELL16:IMUX.SR3 |
| TIEEMAC1UNICASTADDR40 | input | TCELL20:IMUX.CE3 |
| TIEEMAC1UNICASTADDR41 | input | TCELL20:IMUX.CE2 |
| TIEEMAC1UNICASTADDR42 | input | TCELL20:IMUX.CE1 |
| TIEEMAC1UNICASTADDR43 | input | TCELL20:IMUX.CE0 |
| TIEEMAC1UNICASTADDR44 | input | TCELL21:IMUX.SR3 |
| TIEEMAC1UNICASTADDR45 | input | TCELL21:IMUX.SR2 |
| TIEEMAC1UNICASTADDR46 | input | TCELL21:IMUX.SR1 |
| TIEEMAC1UNICASTADDR47 | input | TCELL21:IMUX.SR0 |
| TIEEMAC1UNICASTADDR5 | input | TCELL16:IMUX.SR2 |
| TIEEMAC1UNICASTADDR6 | input | TCELL16:IMUX.SR1 |
| TIEEMAC1UNICASTADDR7 | input | TCELL16:IMUX.SR0 |
| TIEEMAC1UNICASTADDR8 | input | TCELL16:IMUX.CE3 |
| TIEEMAC1UNICASTADDR9 | input | TCELL16:IMUX.CE2 |
| TSTSIEMACI0 | input | TCELL18:IMUX.IMUX13 |
| TSTSIEMACI1 | input | TCELL18:IMUX.IMUX14 |
| TSTSIEMACI2 | input | TCELL19:IMUX.IMUX13 |
| TSTSIEMACI3 | input | TCELL19:IMUX.IMUX14 |
| TSTSIEMACI4 | input | TCELL21:IMUX.IMUX14 |
| TSTSIEMACI5 | input | TCELL23:IMUX.IMUX15 |
| TSTSIEMACI6 | input | TCELL10:IMUX.IMUX10 |
| TSTSOEMACO0 | output | TCELL4:OUT.HALF.BOT0.TMIN, TCELL4:OUT.HALT.TOP0.TMIN |
| TSTSOEMACO1 | output | TCELL4:OUT.HALF.BOT1.TMIN, TCELL4:OUT.HALT.TOP1.TMIN |
| TSTSOEMACO2 | output | TCELL4:OUT.HALF.BOT2.TMIN, TCELL4:OUT.HALT.TOP2.TMIN |
| TSTSOEMACO3 | output | TCELL4:OUT.HALF.BOT3.TMIN, TCELL4:OUT.HALT.TOP3.TMIN |
| TSTSOEMACO4 | output | TCELL37:OUT.HALF.BOT0.TMIN, TCELL37:OUT.HALT.TOP0.TMIN |
| TSTSOEMACO5 | output | TCELL37:OUT.HALF.BOT1.TMIN, TCELL37:OUT.HALT.TOP1.TMIN |
| TSTSOEMACO6 | output | TCELL37:OUT.HALF.BOT2.TMIN, TCELL37:OUT.HALT.TOP2.TMIN |
Bel wires
| Wire | Pins |
|---|---|
| TCELL0:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC8 |
| TCELL0:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC9 |
| TCELL0:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC10 |
| TCELL0:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC11 |
| TCELL0:IMUX.CE0 | EMAC.TIEEMAC0CONFIGVEC4 |
| TCELL0:IMUX.CE1 | EMAC.TIEEMAC0CONFIGVEC5 |
| TCELL0:IMUX.CE2 | EMAC.TIEEMAC0CONFIGVEC6 |
| TCELL0:IMUX.CE3 | EMAC.TIEEMAC0CONFIGVEC7 |
| TCELL0:IMUX.IMUX0 | EMAC.PHYEMAC0RXD0 |
| TCELL0:IMUX.IMUX1 | EMAC.PHYEMAC0RXD1 |
| TCELL0:IMUX.IMUX2 | EMAC.PHYEMAC0RXD2 |
| TCELL0:IMUX.IMUX3 | EMAC.PHYEMAC0RXD3 |
| TCELL0:IMUX.IMUX4 | EMAC.PHYEMAC0CRS |
| TCELL0:IMUX.IMUX5 | EMAC.PHYEMAC0COL |
| TCELL0:IMUX.IMUX6 | EMAC.PHYEMAC0PHYAD2 |
| TCELL0:IMUX.IMUX7 | EMAC.PHYEMAC0PHYAD3 |
| TCELL0:IMUX.IMUX8 | EMAC.PHYEMAC0PHYAD4 |
| TCELL0:IMUX.IMUX9 | EMAC.TIEEMAC0UNICASTADDR45 |
| TCELL0:IMUX.IMUX10 | EMAC.TIEEMAC0UNICASTADDR46 |
| TCELL0:IMUX.IMUX11 | EMAC.TIEEMAC0UNICASTADDR47 |
| TCELL0:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC0 |
| TCELL0:IMUX.IMUX13 | EMAC.TIEEMAC0CONFIGVEC1 |
| TCELL0:IMUX.IMUX14 | EMAC.TIEEMAC0CONFIGVEC2 |
| TCELL0:IMUX.IMUX15 | EMAC.TIEEMAC0CONFIGVEC3 |
| TCELL0:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI28 |
| TCELL0:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI29 |
| TCELL0:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI30 |
| TCELL0:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI31 |
| TCELL0:OUT.BEST0.TMIN | EMAC.EMAC0PHYTXD0 |
| TCELL0:OUT.BEST1.TMIN | EMAC.EMAC0PHYTXD1 |
| TCELL0:OUT.BEST2.TMIN | EMAC.EMAC0PHYTXD2 |
| TCELL0:OUT.BEST3.TMIN | EMAC.EMAC0PHYTXD3 |
| TCELL0:OUT.BEST4.TMIN | EMAC.EMAC0PHYTXCLK |
| TCELL0:OUT.BEST5.TMIN | EMAC.EMAC0PHYTXEN |
| TCELL0:OUT.BEST6.TMIN | EMAC.EMAC0PHYTXER |
| TCELL0:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTTXSTATSVLD |
| TCELL0:OUT.SEC0.TMIN | EMAC.EMAC0CLIENTTXSTATSBYTEVLD |
| TCELL0:OUT.SEC1.TMIN | PPC.ISOCMDCRBRAMEVENEN |
| TCELL0:OUT.SEC2.TMIN | PPC.ISOCMDCRBRAMODDEN |
| TCELL0:OUT.SEC3.TMIN | PPC.ISOCMDCRBRAMRDSELECT |
| TCELL0:OUT.SEC4.TMIN | EMAC.EMAC0PHYMGTRXRESET |
| TCELL0:OUT.HALF.BOT0.TMIN | PPC.LSSDSCANOUT0 |
| TCELL0:OUT.HALF.BOT1.TMIN | PPC.LSSDSCANOUT1 |
| TCELL0:OUT.HALF.BOT2.TMIN | PPC.LSSDSCANOUT2 |
| TCELL0:OUT.HALF.BOT3.TMIN | PPC.LSSDSCANOUT3 |
| TCELL0:OUT.HALF.BOT4.TMIN | PPC.LSSDSCANOUT4 |
| TCELL0:OUT.HALF.BOT5.TMIN | PPC.LSSDSCANOUT5 |
| TCELL0:OUT.HALT.TOP0.TMIN | PPC.LSSDSCANOUT0 |
| TCELL0:OUT.HALT.TOP1.TMIN | PPC.LSSDSCANOUT1 |
| TCELL0:OUT.HALT.TOP2.TMIN | PPC.LSSDSCANOUT2 |
| TCELL0:OUT.HALT.TOP3.TMIN | PPC.LSSDSCANOUT3 |
| TCELL0:OUT.HALT.TOP4.TMIN | PPC.LSSDSCANOUT4 |
| TCELL0:OUT.HALT.TOP5.TMIN | PPC.LSSDSCANOUT5 |
| TCELL1:IMUX.SR0 | EMAC.TIEEMAC0UNICASTADDR41 |
| TCELL1:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR42 |
| TCELL1:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR43 |
| TCELL1:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR44 |
| TCELL1:IMUX.CE0 | EMAC.TIEEMAC0UNICASTADDR37 |
| TCELL1:IMUX.CE1 | EMAC.TIEEMAC0UNICASTADDR38 |
| TCELL1:IMUX.CE2 | EMAC.TIEEMAC0UNICASTADDR39 |
| TCELL1:IMUX.CE3 | EMAC.TIEEMAC0UNICASTADDR40 |
| TCELL1:IMUX.IMUX0 | EMAC.PHYEMAC0RXD4 |
| TCELL1:IMUX.IMUX1 | EMAC.PHYEMAC0RXD5 |
| TCELL1:IMUX.IMUX2 | EMAC.PHYEMAC0RXD6 |
| TCELL1:IMUX.IMUX3 | EMAC.PHYEMAC0RXD7 |
| TCELL1:IMUX.IMUX4 | EMAC.PHYEMAC0RXDV |
| TCELL1:IMUX.IMUX5 | EMAC.PHYEMAC0RXER |
| TCELL1:IMUX.IMUX6 | EMAC.PHYEMAC0RXCOMMADET |
| TCELL1:IMUX.IMUX7 | EMAC.PHYEMAC0RXCHECKINGCRC |
| TCELL1:IMUX.IMUX8 | EMAC.EMAC0TIBUS3 |
| TCELL1:IMUX.IMUX9 | EMAC.EMAC0TIBUS2 |
| TCELL1:IMUX.IMUX10 | EMAC.CLIENTEMAC0TXUNDERRUN |
| TCELL1:IMUX.IMUX11 | EMAC.CLIENTEMAC0PAUSEREQ |
| TCELL1:IMUX.IMUX12 | EMAC.CLIENTEMAC0TXDVLD |
| TCELL1:IMUX.IMUX13 | EMAC.CLIENTEMAC0TXDVLDMSW |
| TCELL1:IMUX.IMUX14 | EMAC.PHYEMAC0PHYAD0 |
| TCELL1:IMUX.IMUX15 | EMAC.PHYEMAC0PHYAD1 |
| TCELL1:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI24 |
| TCELL1:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI25 |
| TCELL1:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI26 |
| TCELL1:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI27 |
| TCELL1:OUT.BEST0.TMIN | EMAC.EMAC0PHYTXD4 |
| TCELL1:OUT.BEST1.TMIN | EMAC.EMAC0PHYTXD5 |
| TCELL1:OUT.BEST2.TMIN | EMAC.EMAC0PHYTXD6 |
| TCELL1:OUT.BEST3.TMIN | EMAC.EMAC0PHYTXD7 |
| TCELL1:OUT.BEST4.TMIN | EMAC.EMAC0PHYTXCHARISK |
| TCELL1:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXDVLDMSW |
| TCELL1:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXDVLD |
| TCELL1:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTRXSTATSVLD |
| TCELL1:OUT.SEC0.TMIN | EMAC.EMAC0CLIENTRXSTATS0 |
| TCELL1:OUT.SEC1.TMIN | EMAC.EMAC0CLIENTRXSTATS1 |
| TCELL1:OUT.SEC2.TMIN | EMAC.EMAC0CLIENTRXSTATS2 |
| TCELL1:OUT.SEC3.TMIN | EMAC.EMAC0PHYMGTTXRESET |
| TCELL1:OUT.HALF.BOT0.TMIN | PPC.LSSDSCANOUT6 |
| TCELL1:OUT.HALF.BOT1.TMIN | PPC.LSSDSCANOUT7 |
| TCELL1:OUT.HALF.BOT2.TMIN | PPC.LSSDSCANOUT8 |
| TCELL1:OUT.HALF.BOT3.TMIN | PPC.LSSDSCANOUT9 |
| TCELL1:OUT.HALF.BOT4.TMIN | PPC.LSSDSCANOUT10 |
| TCELL1:OUT.HALF.BOT5.TMIN | PPC.LSSDSCANOUT11 |
| TCELL1:OUT.HALT.TOP0.TMIN | PPC.LSSDSCANOUT6 |
| TCELL1:OUT.HALT.TOP1.TMIN | PPC.LSSDSCANOUT7 |
| TCELL1:OUT.HALT.TOP2.TMIN | PPC.LSSDSCANOUT8 |
| TCELL1:OUT.HALT.TOP3.TMIN | PPC.LSSDSCANOUT9 |
| TCELL1:OUT.HALT.TOP4.TMIN | PPC.LSSDSCANOUT10 |
| TCELL1:OUT.HALT.TOP5.TMIN | PPC.LSSDSCANOUT11 |
| TCELL2:IMUX.SR0 | EMAC.TIEEMAC0UNICASTADDR33 |
| TCELL2:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR34 |
| TCELL2:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR35 |
| TCELL2:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR36 |
| TCELL2:IMUX.CE0 | EMAC.TIEEMAC0UNICASTADDR29 |
| TCELL2:IMUX.CE1 | EMAC.TIEEMAC0UNICASTADDR30 |
| TCELL2:IMUX.CE2 | EMAC.TIEEMAC0UNICASTADDR31 |
| TCELL2:IMUX.CE3 | EMAC.TIEEMAC0UNICASTADDR32 |
| TCELL2:IMUX.IMUX0 | EMAC.PHYEMAC0RXNOTINTABLE |
| TCELL2:IMUX.IMUX1 | EMAC.PHYEMAC0RXDISPERR |
| TCELL2:IMUX.IMUX2 | EMAC.PHYEMAC0RXCHARISK |
| TCELL2:IMUX.IMUX3 | EMAC.PHYEMAC0RXCHARISCOMMA |
| TCELL2:IMUX.IMUX4 | EMAC.PHYEMAC0RXLOSSOFSYNC0 |
| TCELL2:IMUX.IMUX5 | EMAC.PHYEMAC0RXLOSSOFSYNC1 |
| TCELL2:IMUX.IMUX6 | EMAC.PHYEMAC0RXBUFSTATUS0 |
| TCELL2:IMUX.IMUX7 | EMAC.PHYEMAC0RXBUFSTATUS1 |
| TCELL2:IMUX.IMUX8 | EMAC.CLIENTEMAC0TXD0 |
| TCELL2:IMUX.IMUX9 | EMAC.CLIENTEMAC0TXD1 |
| TCELL2:IMUX.IMUX10 | EMAC.CLIENTEMAC0TXD2 |
| TCELL2:IMUX.IMUX11 | EMAC.CLIENTEMAC0TXD3 |
| TCELL2:IMUX.IMUX12 | EMAC.TIEEMAC0UNICASTADDR28 |
| TCELL2:IMUX.IMUX13 | EMAC.TIEEMAC0UNICASTADDR19 |
| TCELL2:IMUX.IMUX14 | EMAC.RESET |
| TCELL2:IMUX.IMUX15 | EMAC.PHYEMAC0SIGNALDET |
| TCELL2:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI20 |
| TCELL2:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI21 |
| TCELL2:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI22 |
| TCELL2:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI23 |
| TCELL2:OUT.BEST0.TMIN | EMAC.EMAC0CLIENTTXCLIENTCLKOUT |
| TCELL2:OUT.BEST1.TMIN | EMAC.EMAC0CLIENTRXSTATS3 |
| TCELL2:OUT.BEST2.TMIN | EMAC.EMAC0CLIENTTXACK |
| TCELL2:OUT.BEST3.TMIN | EMAC.EMAC0CLIENTTXCOLLISION |
| TCELL2:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTTXRETRANSMIT |
| TCELL2:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXSTATSBYTEVLD |
| TCELL2:OUT.BEST6.TMIN | EMAC.HOSTMIIMRDY |
| TCELL2:OUT.BEST7.TMIN | PPC.DCREMACENABLER |
| TCELL2:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO28 |
| TCELL2:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO29 |
| TCELL2:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO30 |
| TCELL2:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO31 |
| TCELL2:OUT.HALF.BOT0.TMIN | PPC.LSSDSCANOUT12 |
| TCELL2:OUT.HALF.BOT1.TMIN | PPC.LSSDSCANOUT13 |
| TCELL2:OUT.HALF.BOT2.TMIN | PPC.LSSDSCANOUT14 |
| TCELL2:OUT.HALF.BOT3.TMIN | PPC.LSSDSCANOUT15 |
| TCELL2:OUT.HALT.TOP0.TMIN | PPC.LSSDSCANOUT12 |
| TCELL2:OUT.HALT.TOP1.TMIN | PPC.LSSDSCANOUT13 |
| TCELL2:OUT.HALT.TOP2.TMIN | PPC.LSSDSCANOUT14 |
| TCELL2:OUT.HALT.TOP3.TMIN | PPC.LSSDSCANOUT15 |
| TCELL3:IMUX.SR0 | EMAC.TIEEMAC0UNICASTADDR24 |
| TCELL3:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR25 |
| TCELL3:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR26 |
| TCELL3:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR27 |
| TCELL3:IMUX.CE0 | EMAC.TIEEMAC0UNICASTADDR20 |
| TCELL3:IMUX.CE1 | EMAC.TIEEMAC0UNICASTADDR21 |
| TCELL3:IMUX.CE2 | EMAC.TIEEMAC0UNICASTADDR22 |
| TCELL3:IMUX.CE3 | EMAC.TIEEMAC0UNICASTADDR23 |
| TCELL3:IMUX.IMUX0 | EMAC.CLIENTEMAC0TXFIRSTBYTE |
| TCELL3:IMUX.IMUX1 | EMAC.PHYEMAC0RXCLKCORCNT0 |
| TCELL3:IMUX.IMUX2 | EMAC.PHYEMAC0RXRUNDISP |
| TCELL3:IMUX.IMUX3 | EMAC.PHYEMAC0TXBUFERR |
| TCELL3:IMUX.IMUX4 | EMAC.PHYEMAC0MDIN |
| TCELL3:IMUX.IMUX5 | EMAC.CLIENTEMAC0TXD4 |
| TCELL3:IMUX.IMUX6 | EMAC.CLIENTEMAC0TXD5 |
| TCELL3:IMUX.IMUX7 | EMAC.CLIENTEMAC0TXD6 |
| TCELL3:IMUX.IMUX8 | EMAC.CLIENTEMAC0TXD7 |
| TCELL3:IMUX.IMUX9 | EMAC.TIEEMAC0CONFIGVEC64 |
| TCELL3:IMUX.IMUX10 | EMAC.TIEEMAC0CONFIGVEC65 |
| TCELL3:IMUX.IMUX11 | EMAC.TIEEMAC0CONFIGVEC66 |
| TCELL3:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC67 |
| TCELL3:IMUX.IMUX13 | EMAC.TIEEMAC0CONFIGVEC68 |
| TCELL3:IMUX.IMUX14 | EMAC.TIEEMAC0CONFIGVEC69 |
| TCELL3:IMUX.IMUX15 | PPC.TSTISOCMC405READDATAOUTI16 |
| TCELL3:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI17 |
| TCELL3:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI18 |
| TCELL3:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI19 |
| TCELL3:OUT.BEST0.TMIN | EMAC.EMAC0PHYTXCHARDISPMODE |
| TCELL3:OUT.BEST1.TMIN | EMAC.EMAC0PHYTXCHARDISPVAL |
| TCELL3:OUT.BEST2.TMIN | EMAC.EMAC0CLIENTTXGMIIMIICLKOUT |
| TCELL3:OUT.BEST3.TMIN | EMAC.EMAC0PHYLOOPBACKMSB |
| TCELL3:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTRXCLIENTCLKOUT |
| TCELL3:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXFRAMEDROP |
| TCELL3:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXGOODFRAME |
| TCELL3:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTRXBADFRAME |
| TCELL3:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO24 |
| TCELL3:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO25 |
| TCELL3:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO26 |
| TCELL3:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO27 |
| TCELL3:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUWBBYTEENO0 |
| TCELL3:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUWBBYTEENO1 |
| TCELL3:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUWBBYTEENO2 |
| TCELL3:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUWBBYTEENO3 |
| TCELL3:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUWBBYTEENO0 |
| TCELL3:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUWBBYTEENO1 |
| TCELL3:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUWBBYTEENO2 |
| TCELL3:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUWBBYTEENO3 |
| TCELL4:IMUX.SR0 | EMAC.TIEEMAC0UNICASTADDR15 |
| TCELL4:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR16 |
| TCELL4:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR17 |
| TCELL4:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR18 |
| TCELL4:IMUX.CE0 | EMAC.TIEEMAC0UNICASTADDR11 |
| TCELL4:IMUX.CE1 | EMAC.TIEEMAC0UNICASTADDR12 |
| TCELL4:IMUX.CE2 | EMAC.TIEEMAC0UNICASTADDR13 |
| TCELL4:IMUX.CE3 | EMAC.TIEEMAC0UNICASTADDR14 |
| TCELL4:IMUX.IMUX0 | EMAC.CLIENTEMAC0TXD8 |
| TCELL4:IMUX.IMUX1 | EMAC.CLIENTEMAC0TXD9 |
| TCELL4:IMUX.IMUX2 | EMAC.CLIENTEMAC0TXD10 |
| TCELL4:IMUX.IMUX3 | EMAC.CLIENTEMAC0TXD11 |
| TCELL4:IMUX.IMUX4 | EMAC.CLIENTEMAC0TXIFGDELAY0 |
| TCELL4:IMUX.IMUX5 | EMAC.CLIENTEMAC0TXIFGDELAY1 |
| TCELL4:IMUX.IMUX6 | EMAC.CLIENTEMAC0TXIFGDELAY2 |
| TCELL4:IMUX.IMUX7 | EMAC.CLIENTEMAC0TXIFGDELAY3 |
| TCELL4:IMUX.IMUX8 | EMAC.CLIENTEMAC0PAUSEVAL0 |
| TCELL4:IMUX.IMUX9 | EMAC.CLIENTEMAC0PAUSEVAL1 |
| TCELL4:IMUX.IMUX10 | EMAC.CLIENTEMAC0PAUSEVAL2 |
| TCELL4:IMUX.IMUX11 | EMAC.CLIENTEMAC0PAUSEVAL3 |
| TCELL4:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC70 |
| TCELL4:IMUX.IMUX13 | EMAC.TIEEMAC0CONFIGVEC71 |
| TCELL4:IMUX.IMUX14 | EMAC.TIEEMAC0CONFIGVEC72 |
| TCELL4:IMUX.IMUX15 | EMAC.EMAC0TIBUS4 |
| TCELL4:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI12 |
| TCELL4:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI13 |
| TCELL4:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI14 |
| TCELL4:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI15 |
| TCELL4:OUT.BEST0.TMIN | EMAC.EMAC0CLIENTRXD0 |
| TCELL4:OUT.BEST1.TMIN | EMAC.EMAC0CLIENTRXD1 |
| TCELL4:OUT.BEST2.TMIN | EMAC.EMAC0CLIENTRXD2 |
| TCELL4:OUT.BEST3.TMIN | EMAC.EMAC0CLIENTRXD3 |
| TCELL4:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTTXSTATS |
| TCELL4:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXSTATS6 |
| TCELL4:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXSTATS4 |
| TCELL4:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTRXSTATS5 |
| TCELL4:OUT.SEC0.TMIN | PPC.C405JTGSHIFTDR |
| TCELL4:OUT.SEC1.TMIN | PPC.C405JTGTDO |
| TCELL4:OUT.SEC2.TMIN | PPC.C405JTGTDOEN |
| TCELL4:OUT.SEC3.TMIN | PPC.C405JTGUPDATEDR |
| TCELL4:OUT.HALF.BOT0.TMIN | EMAC.TSTSOEMACO0 |
| TCELL4:OUT.HALF.BOT1.TMIN | EMAC.TSTSOEMACO1 |
| TCELL4:OUT.HALF.BOT2.TMIN | EMAC.TSTSOEMACO2 |
| TCELL4:OUT.HALF.BOT3.TMIN | EMAC.TSTSOEMACO3 |
| TCELL4:OUT.HALT.TOP0.TMIN | EMAC.TSTSOEMACO0 |
| TCELL4:OUT.HALT.TOP1.TMIN | EMAC.TSTSOEMACO1 |
| TCELL4:OUT.HALT.TOP2.TMIN | EMAC.TSTSOEMACO2 |
| TCELL4:OUT.HALT.TOP3.TMIN | EMAC.TSTSOEMACO3 |
| TCELL5:IMUX.SR0 | EMAC.TIEEMAC0UNICASTADDR7 |
| TCELL5:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR8 |
| TCELL5:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR9 |
| TCELL5:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR10 |
| TCELL5:IMUX.CE0 | EMAC.TIEEMAC0UNICASTADDR3 |
| TCELL5:IMUX.CE1 | EMAC.TIEEMAC0UNICASTADDR4 |
| TCELL5:IMUX.CE2 | EMAC.TIEEMAC0UNICASTADDR5 |
| TCELL5:IMUX.CE3 | EMAC.TIEEMAC0UNICASTADDR6 |
| TCELL5:IMUX.IMUX0 | EMAC.CLIENTEMAC0TXD12 |
| TCELL5:IMUX.IMUX1 | EMAC.CLIENTEMAC0TXD13 |
| TCELL5:IMUX.IMUX2 | EMAC.CLIENTEMAC0TXD14 |
| TCELL5:IMUX.IMUX3 | EMAC.CLIENTEMAC0TXD15 |
| TCELL5:IMUX.IMUX4 | EMAC.CLIENTEMAC0TXIFGDELAY4 |
| TCELL5:IMUX.IMUX5 | EMAC.CLIENTEMAC0TXIFGDELAY5 |
| TCELL5:IMUX.IMUX6 | EMAC.CLIENTEMAC0TXIFGDELAY6 |
| TCELL5:IMUX.IMUX7 | EMAC.CLIENTEMAC0TXIFGDELAY7 |
| TCELL5:IMUX.IMUX8 | EMAC.CLIENTEMAC0PAUSEVAL4 |
| TCELL5:IMUX.IMUX9 | EMAC.CLIENTEMAC0PAUSEVAL5 |
| TCELL5:IMUX.IMUX10 | EMAC.CLIENTEMAC0PAUSEVAL6 |
| TCELL5:IMUX.IMUX11 | EMAC.CLIENTEMAC0PAUSEVAL7 |
| TCELL5:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC12 |
| TCELL5:IMUX.IMUX13 | EMAC.TIEEMAC0CONFIGVEC13 |
| TCELL5:IMUX.IMUX14 | EMAC.TIEEMAC0CONFIGVEC14 |
| TCELL5:IMUX.IMUX15 | EMAC.TIEEMAC0CONFIGVEC15 |
| TCELL5:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI8 |
| TCELL5:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI9 |
| TCELL5:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI10 |
| TCELL5:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI11 |
| TCELL5:OUT.BEST0.TMIN | EMAC.EMAC0PHYSYNCACQSTATUS |
| TCELL5:OUT.BEST1.TMIN | EMAC.EMAC0PHYMCLKOUT |
| TCELL5:OUT.BEST2.TMIN | EMAC.EMAC0PHYMDTRI |
| TCELL5:OUT.BEST3.TMIN | EMAC.EMAC0PHYMDOUT |
| TCELL5:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTRXD4 |
| TCELL5:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXD5 |
| TCELL5:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXD6 |
| TCELL5:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTRXD7 |
| TCELL5:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO20 |
| TCELL5:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO21 |
| TCELL5:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO22 |
| TCELL5:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO23 |
| TCELL5:OUT.SEC4.TMIN | EMAC.EMAC0CLIENTRXDVREG6 |
| TCELL5:OUT.HALF.BOT0.TMIN | PPC.DIAGOUT |
| TCELL5:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUWBFLUSHO |
| TCELL5:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUWBHOLDO |
| TCELL5:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUDCDFULLO |
| TCELL5:OUT.HALT.TOP0.TMIN | PPC.DIAGOUT |
| TCELL5:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUWBFLUSHO |
| TCELL5:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUWBHOLDO |
| TCELL5:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUDCDFULLO |
| TCELL6:IMUX.SR0 | PPC.TIEDCRADDR4 |
| TCELL6:IMUX.SR1 | EMAC.TIEEMAC0UNICASTADDR0 |
| TCELL6:IMUX.SR2 | EMAC.TIEEMAC0UNICASTADDR1 |
| TCELL6:IMUX.SR3 | EMAC.TIEEMAC0UNICASTADDR2 |
| TCELL6:IMUX.CLK0 | EMAC.EMAC0TIBUS0 |
| TCELL6:IMUX.CE0 | PPC.TIEDCRADDR0 |
| TCELL6:IMUX.CE1 | PPC.TIEDCRADDR1 |
| TCELL6:IMUX.CE2 | PPC.TIEDCRADDR2 |
| TCELL6:IMUX.CE3 | PPC.TIEDCRADDR3 |
| TCELL6:IMUX.IMUX0 | EMAC.HOSTADDR0 |
| TCELL6:IMUX.IMUX1 | EMAC.HOSTADDR1 |
| TCELL6:IMUX.IMUX2 | EMAC.HOSTADDR2 |
| TCELL6:IMUX.IMUX3 | EMAC.HOSTADDR3 |
| TCELL6:IMUX.IMUX4 | EMAC.HOSTADDR4 |
| TCELL6:IMUX.IMUX5 | EMAC.HOSTADDR5 |
| TCELL6:IMUX.IMUX6 | EMAC.HOSTADDR6 |
| TCELL6:IMUX.IMUX7 | EMAC.HOSTADDR7 |
| TCELL6:IMUX.IMUX8 | EMAC.HOSTADDR8 |
| TCELL6:IMUX.IMUX9 | EMAC.HOSTADDR9 |
| TCELL6:IMUX.IMUX10 | EMAC.HOSTWRDATA0 |
| TCELL6:IMUX.IMUX11 | EMAC.HOSTWRDATA1 |
| TCELL6:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC16 |
| TCELL6:IMUX.IMUX13 | EMAC.TIEEMAC0CONFIGVEC17 |
| TCELL6:IMUX.IMUX14 | EMAC.TIEEMAC0CONFIGVEC18 |
| TCELL6:IMUX.IMUX15 | EMAC.TIEEMAC0CONFIGVEC19 |
| TCELL6:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI4 |
| TCELL6:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI5 |
| TCELL6:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI6 |
| TCELL6:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI7 |
| TCELL6:OUT.BEST0.TMIN | EMAC.HOSTRDDATA0 |
| TCELL6:OUT.BEST1.TMIN | EMAC.HOSTRDDATA1 |
| TCELL6:OUT.BEST2.TMIN | EMAC.HOSTRDDATA2 |
| TCELL6:OUT.BEST3.TMIN | EMAC.EMAC0CLIENTRXD8 |
| TCELL6:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTRXD9 |
| TCELL6:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXD10 |
| TCELL6:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXD11 |
| TCELL6:OUT.BEST7.TMIN | EMAC.HOSTRDDATA3 |
| TCELL6:OUT.SEC0.TMIN | EMAC.HOSTRDDATA4 |
| TCELL6:OUT.SEC1.TMIN | EMAC.HOSTRDDATA5 |
| TCELL6:OUT.SEC2.TMIN | EMAC.HOSTRDDATA6 |
| TCELL6:OUT.SEC3.TMIN | EMAC.HOSTRDDATA7 |
| TCELL6:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMBYTEENO0 |
| TCELL6:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMBYTEENO1 |
| TCELL6:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMBYTEENO2 |
| TCELL6:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMBYTEENO3 |
| TCELL6:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMXLTVALIDO |
| TCELL6:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMABORTOPO |
| TCELL6:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMABORTREQO |
| TCELL6:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMLOADREQO |
| TCELL6:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMBYTEENO0 |
| TCELL6:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMBYTEENO1 |
| TCELL6:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMBYTEENO2 |
| TCELL6:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMBYTEENO3 |
| TCELL6:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMXLTVALIDO |
| TCELL6:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMABORTOPO |
| TCELL6:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMABORTREQO |
| TCELL6:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMLOADREQO |
| TCELL7:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR3 |
| TCELL7:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR2 |
| TCELL7:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR1 |
| TCELL7:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR0 |
| TCELL7:IMUX.CLK0 | PPC.CPMDCRCLK |
| TCELL7:IMUX.CE0 | PPC.TIEDCRADDR5 |
| TCELL7:IMUX.CE1 | PPC.TESTSELI |
| TCELL7:IMUX.CE2 | EMAC.TIEEMAC0CONFIGVEC63 |
| TCELL7:IMUX.CE3 | PPC.TSTUSECPMCLKSELI |
| TCELL7:IMUX.IMUX0 | EMAC.HOSTWRDATA2 |
| TCELL7:IMUX.IMUX1 | EMAC.HOSTWRDATA3 |
| TCELL7:IMUX.IMUX2 | EMAC.HOSTWRDATA4 |
| TCELL7:IMUX.IMUX3 | EMAC.HOSTWRDATA5 |
| TCELL7:IMUX.IMUX4 | EMAC.HOSTWRDATA6 |
| TCELL7:IMUX.IMUX5 | EMAC.HOSTWRDATA7 |
| TCELL7:IMUX.IMUX6 | EMAC.HOSTWRDATA8 |
| TCELL7:IMUX.IMUX7 | EMAC.HOSTWRDATA9 |
| TCELL7:IMUX.IMUX8 | EMAC.HOSTWRDATA10 |
| TCELL7:IMUX.IMUX9 | EMAC.HOSTWRDATA11 |
| TCELL7:IMUX.IMUX10 | EMAC.HOSTWRDATA12 |
| TCELL7:IMUX.IMUX11 | EMAC.HOSTWRDATA13 |
| TCELL7:IMUX.IMUX12 | EMAC.CLIENTEMAC0PAUSEVAL12 |
| TCELL7:IMUX.IMUX13 | EMAC.CLIENTEMAC0PAUSEVAL13 |
| TCELL7:IMUX.IMUX14 | EMAC.CLIENTEMAC0PAUSEVAL14 |
| TCELL7:IMUX.IMUX15 | EMAC.CLIENTEMAC0PAUSEVAL15 |
| TCELL7:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI0 |
| TCELL7:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI1 |
| TCELL7:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI2 |
| TCELL7:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI3 |
| TCELL7:OUT.BEST0.TMIN | EMAC.HOSTRDDATA8 |
| TCELL7:OUT.BEST1.TMIN | EMAC.HOSTRDDATA9 |
| TCELL7:OUT.BEST2.TMIN | EMAC.HOSTRDDATA10 |
| TCELL7:OUT.BEST3.TMIN | EMAC.HOSTRDDATA11 |
| TCELL7:OUT.BEST4.TMIN | EMAC.EMAC0CLIENTRXD12 |
| TCELL7:OUT.BEST5.TMIN | EMAC.EMAC0CLIENTRXD13 |
| TCELL7:OUT.BEST6.TMIN | EMAC.EMAC0CLIENTRXD14 |
| TCELL7:OUT.BEST7.TMIN | EMAC.EMAC0CLIENTRXD15 |
| TCELL7:OUT.SEC0.TMIN | EMAC.HOSTRDDATA12 |
| TCELL7:OUT.SEC1.TMIN | EMAC.HOSTRDDATA13 |
| TCELL7:OUT.SEC2.TMIN | EMAC.HOSTRDDATA14 |
| TCELL7:OUT.SEC3.TMIN | EMAC.HOSTRDDATA15 |
| TCELL7:OUT.HALF.BOT0.TMIN | PPC.C405DSOCMCACHEABLE |
| TCELL7:OUT.HALF.BOT1.TMIN | PPC.C405DSOCMGUARDED |
| TCELL7:OUT.HALF.BOT2.TMIN | PPC.C405DSOCMSTRINGMULTIPLE |
| TCELL7:OUT.HALF.BOT3.TMIN | PPC.C405DSOCMU0ATTR |
| TCELL7:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXEWDCNTO0 |
| TCELL7:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXEWDCNTO1 |
| TCELL7:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUMSRFE0O |
| TCELL7:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUMSRFE1O |
| TCELL7:OUT.HALT.TOP0.TMIN | PPC.C405DSOCMCACHEABLE |
| TCELL7:OUT.HALT.TOP1.TMIN | PPC.C405DSOCMGUARDED |
| TCELL7:OUT.HALT.TOP2.TMIN | PPC.C405DSOCMSTRINGMULTIPLE |
| TCELL7:OUT.HALT.TOP3.TMIN | PPC.C405DSOCMU0ATTR |
| TCELL7:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXEWDCNTO0 |
| TCELL7:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXEWDCNTO1 |
| TCELL7:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUMSRFE0O |
| TCELL7:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUMSRFE1O |
| TCELL8:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC49 |
| TCELL8:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC50 |
| TCELL8:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC51 |
| TCELL8:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC52 |
| TCELL8:IMUX.CLK0 | EMAC.EMAC0TIBUS1 |
| TCELL8:IMUX.CE0 | PPC.TIEPVRBIT28 |
| TCELL8:IMUX.CE1 | PPC.TIEPVRBIT29 |
| TCELL8:IMUX.CE2 | PPC.TIEPVRBIT30 |
| TCELL8:IMUX.CE3 | PPC.TIEPVRBIT31 |
| TCELL8:IMUX.IMUX0 | PPC.EXTDCRDBUSIN28 |
| TCELL8:IMUX.IMUX1 | PPC.EXTDCRDBUSIN29 |
| TCELL8:IMUX.IMUX2 | PPC.EXTDCRDBUSIN30 |
| TCELL8:IMUX.IMUX3 | PPC.EXTDCRDBUSIN31 |
| TCELL8:IMUX.IMUX4 | EMAC.CLIENTEMAC0PAUSEVAL8 |
| TCELL8:IMUX.IMUX5 | EMAC.CLIENTEMAC0PAUSEVAL9 |
| TCELL8:IMUX.IMUX6 | EMAC.CLIENTEMAC0PAUSEVAL10 |
| TCELL8:IMUX.IMUX7 | EMAC.CLIENTEMAC0PAUSEVAL11 |
| TCELL8:IMUX.IMUX8 | EMAC.PHYEMAC0RXCLKCORCNT1 |
| TCELL8:IMUX.IMUX9 | EMAC.PHYEMAC0RXCLKCORCNT2 |
| TCELL8:IMUX.IMUX10 | EMAC.PHYEMAC0RXBUFERR |
| TCELL8:IMUX.IMUX11 | PPC.CPMC405PLBSAMPLECYCLEALT |
| TCELL8:IMUX.IMUX12 | PPC.CPMC405PLBSYNCCLOCK |
| TCELL8:IMUX.IMUX13 | PPC.TSTC405ISOCMABUSI25 |
| TCELL8:IMUX.IMUX14 | PPC.TSTC405ISOCMABUSI26 |
| TCELL8:IMUX.IMUX15 | PPC.TSTC405ISOCMABUSI27 |
| TCELL8:IMUX.IMUX16 | PPC.TSTC405ISOCMABUSI28 |
| TCELL8:IMUX.IMUX17 | PPC.TSTC405ISOCMABUSI29 |
| TCELL8:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT28 |
| TCELL8:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT29 |
| TCELL8:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT30 |
| TCELL8:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT31 |
| TCELL8:OUT.BEST4.TMIN | PPC.C405DBGWBIAR28 |
| TCELL8:OUT.BEST5.TMIN | PPC.C405DBGWBIAR29 |
| TCELL8:OUT.BEST6.TMIN | PPC.C405DBGWBFULL |
| TCELL8:OUT.BEST7.TMIN | PPC.C405CPMCORESLEEPREQ |
| TCELL8:OUT.SEC0.TMIN | PPC.C405CPMMSRCE |
| TCELL8:OUT.SEC1.TMIN | PPC.C405CPMMSREE |
| TCELL8:OUT.SEC2.TMIN | PPC.C405CPMTIMERIRQ |
| TCELL8:OUT.SEC3.TMIN | PPC.C405CPMTIMERRESETREQ |
| TCELL8:OUT.SEC4.TMIN | EMAC.EMAC0CLIENTANINTERRUPT |
| TCELL8:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO60 |
| TCELL8:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO61 |
| TCELL8:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO62 |
| TCELL8:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO63 |
| TCELL8:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO28 |
| TCELL8:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO29 |
| TCELL8:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO30 |
| TCELL8:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO31 |
| TCELL8:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO60 |
| TCELL8:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO61 |
| TCELL8:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO62 |
| TCELL8:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO63 |
| TCELL8:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO28 |
| TCELL8:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO29 |
| TCELL8:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO30 |
| TCELL8:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO31 |
| TCELL9:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC53 |
| TCELL9:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC54 |
| TCELL9:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC55 |
| TCELL9:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC56 |
| TCELL9:IMUX.CLK0 | EMAC.PHYEMAC0MCLKIN |
| TCELL9:IMUX.CE0 | PPC.LSSDSCANIN0 |
| TCELL9:IMUX.CE1 | PPC.LSSDSCANIN1 |
| TCELL9:IMUX.CE2 | PPC.LSSDSCANIN2 |
| TCELL9:IMUX.CE3 | PPC.LSSDSCANIN3 |
| TCELL9:IMUX.IMUX0 | PPC.EXTDCRDBUSIN24 |
| TCELL9:IMUX.IMUX1 | PPC.EXTDCRDBUSIN25 |
| TCELL9:IMUX.IMUX2 | PPC.EXTDCRDBUSIN26 |
| TCELL9:IMUX.IMUX3 | PPC.EXTDCRDBUSIN27 |
| TCELL9:IMUX.IMUX4 | PPC.RSTC405RESETCORE |
| TCELL9:IMUX.IMUX5 | PPC.RSTC405RESETCHIP |
| TCELL9:IMUX.IMUX6 | PPC.RSTC405RESETSYS |
| TCELL9:IMUX.IMUX7 | PPC.TIEC405CLOCKENABLE |
| TCELL9:IMUX.IMUX8 | PPC.TIEC405DUTYENABLE |
| TCELL9:IMUX.IMUX9 | EMAC.TIEEMAC0CONFIGVEC73 |
| TCELL9:IMUX.IMUX10 | EMAC.TIEEMAC0CONFIGVEC74 |
| TCELL9:IMUX.IMUX11 | EMAC.TIEEMAC0CONFIGVEC75 |
| TCELL9:IMUX.IMUX12 | EMAC.TIEEMAC0CONFIGVEC76 |
| TCELL9:IMUX.IMUX13 | PPC.LSSDCE1C1 |
| TCELL9:IMUX.IMUX14 | PPC.LSSDCE1CA1 |
| TCELL9:IMUX.IMUX15 | PPC.TSTC405ISOCMABUSI20 |
| TCELL9:IMUX.IMUX16 | PPC.TSTC405ISOCMABUSI21 |
| TCELL9:IMUX.IMUX17 | PPC.TSTC405ISOCMABUSI22 |
| TCELL9:IMUX.IMUX18 | PPC.TSTC405ISOCMABUSI23 |
| TCELL9:IMUX.IMUX19 | PPC.TSTC405ISOCMABUSI24 |
| TCELL9:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT24 |
| TCELL9:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT25 |
| TCELL9:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT26 |
| TCELL9:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT27 |
| TCELL9:OUT.BEST4.TMIN | PPC.C405DBGWBIAR24 |
| TCELL9:OUT.BEST5.TMIN | PPC.C405DBGWBIAR25 |
| TCELL9:OUT.BEST6.TMIN | PPC.C405DBGWBIAR26 |
| TCELL9:OUT.BEST7.TMIN | PPC.C405DBGWBIAR27 |
| TCELL9:OUT.SEC0.TMIN | PPC.C405XXXMACHINECHECK |
| TCELL9:OUT.SEC1.TMIN | PPC.C405RSTCHIPRESETREQ |
| TCELL9:OUT.SEC2.TMIN | PPC.C405RSTCORERESETREQ |
| TCELL9:OUT.SEC3.TMIN | PPC.C405RSTSYSRESETREQ |
| TCELL9:OUT.SEC4.TMIN | EMAC.EMAC0PHYENCOMMAALIGN |
| TCELL9:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO56 |
| TCELL9:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO57 |
| TCELL9:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO58 |
| TCELL9:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO59 |
| TCELL9:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO24 |
| TCELL9:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO25 |
| TCELL9:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO26 |
| TCELL9:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO27 |
| TCELL9:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO56 |
| TCELL9:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO57 |
| TCELL9:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO58 |
| TCELL9:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO59 |
| TCELL9:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO24 |
| TCELL9:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO25 |
| TCELL9:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO26 |
| TCELL9:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO27 |
| TCELL10:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC57 |
| TCELL10:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC58 |
| TCELL10:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC59 |
| TCELL10:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC60 |
| TCELL10:IMUX.CLK0 | EMAC.CLIENTEMAC0RXCLIENTCLKIN |
| TCELL10:IMUX.CE0 | PPC.LSSDSCANIN4 |
| TCELL10:IMUX.CE1 | PPC.LSSDSCANIN5 |
| TCELL10:IMUX.CE2 | PPC.LSSDSCANIN6 |
| TCELL10:IMUX.CE3 | PPC.LSSDSCANIN7 |
| TCELL10:IMUX.IMUX0 | PPC.EXTDCRDBUSIN20 |
| TCELL10:IMUX.IMUX1 | PPC.EXTDCRDBUSIN21 |
| TCELL10:IMUX.IMUX2 | PPC.EXTDCRDBUSIN22 |
| TCELL10:IMUX.IMUX3 | PPC.EXTDCRDBUSIN23 |
| TCELL10:IMUX.IMUX4 | EMAC.CLIENTEMAC0DCMLOCKED |
| TCELL10:IMUX.IMUX5 | EMAC.TIEEMAC0CONFIGVEC77 |
| TCELL10:IMUX.IMUX6 | EMAC.TIEEMAC0CONFIGVEC78 |
| TCELL10:IMUX.IMUX7 | EMAC.TIEEMAC0CONFIGVEC79 |
| TCELL10:IMUX.IMUX8 | EMAC.TIEEMAC0CONFIGVEC61 |
| TCELL10:IMUX.IMUX9 | EMAC.TIEEMAC0CONFIGVEC62 |
| TCELL10:IMUX.IMUX10 | EMAC.TSTSIEMACI6 |
| TCELL10:IMUX.IMUX11 | PPC.TSTCPUCLKENI |
| TCELL10:IMUX.IMUX12 | PPC.TSTCLKINACTI |
| TCELL10:IMUX.IMUX13 | PPC.TSTTIMERENI |
| TCELL10:IMUX.IMUX14 | PPC.TSTJTAGENI |
| TCELL10:IMUX.IMUX15 | PPC.TSTRESETCOREI |
| TCELL10:IMUX.IMUX16 | PPC.TSTC405ISOCMABUSI16 |
| TCELL10:IMUX.IMUX17 | PPC.TSTC405ISOCMABUSI17 |
| TCELL10:IMUX.IMUX18 | PPC.TSTC405ISOCMABUSI18 |
| TCELL10:IMUX.IMUX19 | PPC.TSTC405ISOCMABUSI19 |
| TCELL10:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT20 |
| TCELL10:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT21 |
| TCELL10:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT22 |
| TCELL10:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT23 |
| TCELL10:OUT.BEST4.TMIN | PPC.C405DBGWBIAR20 |
| TCELL10:OUT.BEST5.TMIN | PPC.C405DBGWBIAR21 |
| TCELL10:OUT.BEST6.TMIN | PPC.C405DBGWBIAR22 |
| TCELL10:OUT.BEST7.TMIN | PPC.C405DBGWBIAR23 |
| TCELL10:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO16 |
| TCELL10:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO17 |
| TCELL10:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO18 |
| TCELL10:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO19 |
| TCELL10:OUT.SEC4.TMIN | EMAC.EMAC0PHYPOWERDOWN |
| TCELL10:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO52 |
| TCELL10:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO53 |
| TCELL10:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO54 |
| TCELL10:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO55 |
| TCELL10:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO20 |
| TCELL10:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO21 |
| TCELL10:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO22 |
| TCELL10:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO23 |
| TCELL10:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO52 |
| TCELL10:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO53 |
| TCELL10:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO54 |
| TCELL10:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO55 |
| TCELL10:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO20 |
| TCELL10:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO21 |
| TCELL10:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO22 |
| TCELL10:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO23 |
| TCELL11:IMUX.SR0 | PPC.BISTCE0LOADIN |
| TCELL11:IMUX.SR1 | PPC.C405TESTRESERVE1 |
| TCELL11:IMUX.SR2 | PPC.C405TESTRESERVE2 |
| TCELL11:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC61 |
| TCELL11:IMUX.CLK0 | EMAC.CLIENTEMAC0TXGMIIMIICLKIN |
| TCELL11:IMUX.CE0 | PPC.LSSDSCANIN8 |
| TCELL11:IMUX.CE1 | PPC.LSSDSCANIN9 |
| TCELL11:IMUX.CE2 | PPC.LSSDSCANIN10 |
| TCELL11:IMUX.CE3 | PPC.LSSDSCANIN11 |
| TCELL11:IMUX.IMUX0 | PPC.EXTDCRDBUSIN16 |
| TCELL11:IMUX.IMUX1 | PPC.EXTDCRDBUSIN17 |
| TCELL11:IMUX.IMUX2 | PPC.EXTDCRDBUSIN18 |
| TCELL11:IMUX.IMUX3 | PPC.EXTDCRDBUSIN19 |
| TCELL11:IMUX.IMUX4 | PPC.CPMC405SYNCBYPASS |
| TCELL11:IMUX.IMUX5 | PPC.TSTC405DSOCMABUSI12 |
| TCELL11:IMUX.IMUX6 | PPC.TSTC405DSOCMABUSI13 |
| TCELL11:IMUX.IMUX7 | PPC.TSTC405DSOCMABUSI14 |
| TCELL11:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI15 |
| TCELL11:IMUX.IMUX9 | PPC.TSTRESETCHIPI |
| TCELL11:IMUX.IMUX10 | PPC.TSTRESETSYSI |
| TCELL11:IMUX.IMUX11 | PPC.TSTC405ISOCMABUSI12 |
| TCELL11:IMUX.IMUX12 | PPC.TSTC405ISOCMABUSI13 |
| TCELL11:IMUX.IMUX13 | PPC.TSTC405ISOCMABUSI14 |
| TCELL11:IMUX.IMUX14 | PPC.TSTC405ISOCMABUSI15 |
| TCELL11:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT16 |
| TCELL11:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT17 |
| TCELL11:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT18 |
| TCELL11:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT19 |
| TCELL11:OUT.BEST4.TMIN | PPC.C405DBGWBIAR16 |
| TCELL11:OUT.BEST5.TMIN | PPC.C405DBGWBIAR17 |
| TCELL11:OUT.BEST6.TMIN | PPC.C405DBGWBIAR18 |
| TCELL11:OUT.BEST7.TMIN | PPC.C405DBGWBIAR19 |
| TCELL11:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO12 |
| TCELL11:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO13 |
| TCELL11:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO14 |
| TCELL11:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO15 |
| TCELL11:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO48 |
| TCELL11:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO49 |
| TCELL11:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO50 |
| TCELL11:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO51 |
| TCELL11:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO16 |
| TCELL11:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO17 |
| TCELL11:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO18 |
| TCELL11:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO19 |
| TCELL11:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO48 |
| TCELL11:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO49 |
| TCELL11:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO50 |
| TCELL11:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO51 |
| TCELL11:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO16 |
| TCELL11:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO17 |
| TCELL11:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO18 |
| TCELL11:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO19 |
| TCELL12:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC60 |
| TCELL12:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC59 |
| TCELL12:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC58 |
| TCELL12:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC57 |
| TCELL12:IMUX.CLK0 | EMAC.CLIENTEMAC0TXCLIENTCLKIN |
| TCELL12:IMUX.CE0 | PPC.LSSDSCANIN12 |
| TCELL12:IMUX.CE1 | PPC.LSSDSCANIN13 |
| TCELL12:IMUX.CE2 | PPC.LSSDSCANIN14 |
| TCELL12:IMUX.CE3 | PPC.LSSDSCANIN15 |
| TCELL12:IMUX.IMUX0 | PPC.EXTDCRDBUSIN12 |
| TCELL12:IMUX.IMUX1 | PPC.EXTDCRDBUSIN13 |
| TCELL12:IMUX.IMUX2 | PPC.EXTDCRDBUSIN14 |
| TCELL12:IMUX.IMUX3 | PPC.EXTDCRDBUSIN15 |
| TCELL12:IMUX.IMUX4 | EMAC.TIEEMAC1CONFIGVEC62 |
| TCELL12:IMUX.IMUX5 | PPC.LSSDCE1CRAM |
| TCELL12:IMUX.IMUX6 | PPC.LSSDCE1C3BIST |
| TCELL12:IMUX.IMUX7 | PPC.CPMC405PLBSAMPLECYCLE |
| TCELL12:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI8 |
| TCELL12:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI9 |
| TCELL12:IMUX.IMUX10 | PPC.TSTC405DSOCMABUSI10 |
| TCELL12:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI11 |
| TCELL12:IMUX.IMUX12 | PPC.TSTC405ISOCMABUSI8 |
| TCELL12:IMUX.IMUX13 | PPC.TSTC405ISOCMABUSI9 |
| TCELL12:IMUX.IMUX14 | PPC.TSTC405ISOCMABUSI10 |
| TCELL12:IMUX.IMUX15 | PPC.TSTC405ISOCMABUSI11 |
| TCELL12:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT12 |
| TCELL12:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT13 |
| TCELL12:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT14 |
| TCELL12:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT15 |
| TCELL12:OUT.BEST4.TMIN | PPC.EXTDCRREAD |
| TCELL12:OUT.BEST5.TMIN | PPC.EXTDCRWRITE |
| TCELL12:OUT.BEST6.TMIN | PPC.C405DBGMSRWE |
| TCELL12:OUT.BEST7.TMIN | PPC.C405DBGWBIAR12 |
| TCELL12:OUT.SEC0.TMIN | PPC.C405DBGWBIAR13 |
| TCELL12:OUT.SEC1.TMIN | PPC.C405DBGWBIAR14 |
| TCELL12:OUT.SEC2.TMIN | PPC.C405DBGWBIAR15 |
| TCELL12:OUT.SEC3.TMIN | PPC.C405DBGLOADDATAONAPUDBUS |
| TCELL12:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO44 |
| TCELL12:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO45 |
| TCELL12:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO46 |
| TCELL12:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO47 |
| TCELL12:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO12 |
| TCELL12:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO13 |
| TCELL12:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO14 |
| TCELL12:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO15 |
| TCELL12:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO44 |
| TCELL12:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO45 |
| TCELL12:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO46 |
| TCELL12:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO47 |
| TCELL12:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO12 |
| TCELL12:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO13 |
| TCELL12:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO14 |
| TCELL12:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO15 |
| TCELL13:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC56 |
| TCELL13:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC55 |
| TCELL13:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC54 |
| TCELL13:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC53 |
| TCELL13:IMUX.CLK0 | EMAC.PHYEMAC0MIITXCLK |
| TCELL13:IMUX.CE0 | PPC.TIEPVRBIT8 |
| TCELL13:IMUX.CE1 | PPC.TIEPVRBIT9 |
| TCELL13:IMUX.CE2 | PPC.TIEPVRBIT10 |
| TCELL13:IMUX.CE3 | PPC.TIEPVRBIT11 |
| TCELL13:IMUX.IMUX0 | PPC.EXTDCRDBUSIN8 |
| TCELL13:IMUX.IMUX1 | PPC.EXTDCRDBUSIN9 |
| TCELL13:IMUX.IMUX2 | PPC.EXTDCRDBUSIN10 |
| TCELL13:IMUX.IMUX3 | PPC.EXTDCRDBUSIN11 |
| TCELL13:IMUX.IMUX4 | EMAC.TIEEMAC1CONFIGVEC73 |
| TCELL13:IMUX.IMUX5 | EMAC.TIEEMAC1CONFIGVEC74 |
| TCELL13:IMUX.IMUX6 | EMAC.TIEEMAC1CONFIGVEC75 |
| TCELL13:IMUX.IMUX7 | EMAC.TIEEMAC1CONFIGVEC76 |
| TCELL13:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI4 |
| TCELL13:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI5 |
| TCELL13:IMUX.IMUX10 | PPC.TSTC405DSOCMABUSI6 |
| TCELL13:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI7 |
| TCELL13:IMUX.IMUX12 | PPC.TSTC405ISOCMABUSI4 |
| TCELL13:IMUX.IMUX13 | PPC.TSTC405ISOCMABUSI5 |
| TCELL13:IMUX.IMUX14 | PPC.TSTC405ISOCMABUSI6 |
| TCELL13:IMUX.IMUX15 | PPC.TSTC405ISOCMABUSI7 |
| TCELL13:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT8 |
| TCELL13:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT9 |
| TCELL13:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT10 |
| TCELL13:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT11 |
| TCELL13:OUT.BEST4.TMIN | PPC.EXTDCRABUS9 |
| TCELL13:OUT.BEST5.TMIN | PPC.EXTDCRABUS8 |
| TCELL13:OUT.BEST6.TMIN | PPC.C405DBGWBCOMPLETE |
| TCELL13:OUT.BEST7.TMIN | PPC.C405DBGWBIAR8 |
| TCELL13:OUT.SEC0.TMIN | PPC.C405DBGWBIAR9 |
| TCELL13:OUT.SEC1.TMIN | PPC.C405DBGWBIAR10 |
| TCELL13:OUT.SEC2.TMIN | PPC.C405DBGWBIAR11 |
| TCELL13:OUT.SEC3.TMIN | PPC.C405DBGSTOPACK |
| TCELL13:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO40 |
| TCELL13:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO41 |
| TCELL13:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO42 |
| TCELL13:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO43 |
| TCELL13:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO8 |
| TCELL13:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO9 |
| TCELL13:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO10 |
| TCELL13:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO11 |
| TCELL13:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO40 |
| TCELL13:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO41 |
| TCELL13:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO42 |
| TCELL13:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO43 |
| TCELL13:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO8 |
| TCELL13:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO9 |
| TCELL13:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO10 |
| TCELL13:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO11 |
| TCELL14:IMUX.SR0 | PPC.MCBJTAGEN |
| TCELL14:IMUX.SR1 | PPC.MCBCPUCLKEN |
| TCELL14:IMUX.SR2 | PPC.MCBTIMEREN |
| TCELL14:IMUX.SR3 | PPC.MCPPCRST |
| TCELL14:IMUX.CLK0 | EMAC.PHYEMAC0RXCLK |
| TCELL14:IMUX.CE0 | PPC.BISTCE0CONTINUE |
| TCELL14:IMUX.CE1 | PPC.LSSDCE0TESTM3 |
| TCELL14:IMUX.CE2 | PPC.LSSDCE0SCAN |
| TCELL14:IMUX.CE3 | PPC.LSSDCE0CNTLPOINT |
| TCELL14:IMUX.IMUX0 | PPC.EXTDCRDBUSIN4 |
| TCELL14:IMUX.IMUX1 | PPC.EXTDCRDBUSIN5 |
| TCELL14:IMUX.IMUX2 | PPC.EXTDCRDBUSIN6 |
| TCELL14:IMUX.IMUX3 | PPC.EXTDCRDBUSIN7 |
| TCELL14:IMUX.IMUX4 | PPC.DBGC405DEBUGHALT |
| TCELL14:IMUX.IMUX5 | PPC.DBGC405EXTBUSHOLDACK |
| TCELL14:IMUX.IMUX6 | PPC.DBGC405UNCONDDEBUGEVENT |
| TCELL14:IMUX.IMUX7 | PPC.CPMC405TIMERCLKEN |
| TCELL14:IMUX.IMUX8 | PPC.CPMC405TIMERTICK |
| TCELL14:IMUX.IMUX9 | PPC.CPMC405CPUCLKEN |
| TCELL14:IMUX.IMUX10 | PPC.CPMC405JTAGCLKEN |
| TCELL14:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI0 |
| TCELL14:IMUX.IMUX12 | PPC.TSTC405DSOCMABUSI1 |
| TCELL14:IMUX.IMUX13 | PPC.TSTC405DSOCMABUSI2 |
| TCELL14:IMUX.IMUX14 | PPC.TSTC405DSOCMABUSI3 |
| TCELL14:IMUX.IMUX15 | PPC.TSTC405ISOCMABUSI0 |
| TCELL14:IMUX.IMUX16 | PPC.TSTC405ISOCMABUSI1 |
| TCELL14:IMUX.IMUX17 | PPC.TSTC405ISOCMABUSI2 |
| TCELL14:IMUX.IMUX18 | PPC.TSTC405ISOCMABUSI3 |
| TCELL14:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT4 |
| TCELL14:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT5 |
| TCELL14:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT6 |
| TCELL14:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT7 |
| TCELL14:OUT.BEST4.TMIN | PPC.EXTDCRABUS4 |
| TCELL14:OUT.BEST5.TMIN | PPC.EXTDCRABUS5 |
| TCELL14:OUT.BEST6.TMIN | PPC.EXTDCRABUS6 |
| TCELL14:OUT.BEST7.TMIN | PPC.EXTDCRABUS7 |
| TCELL14:OUT.SEC0.TMIN | PPC.C405DBGWBIAR4 |
| TCELL14:OUT.SEC1.TMIN | PPC.C405DBGWBIAR5 |
| TCELL14:OUT.SEC2.TMIN | PPC.C405DBGWBIAR6 |
| TCELL14:OUT.SEC3.TMIN | PPC.C405DBGWBIAR7 |
| TCELL14:OUT.SEC4.TMIN | EMAC.EMAC1CLIENTANINTERRUPT |
| TCELL14:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO36 |
| TCELL14:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO37 |
| TCELL14:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO38 |
| TCELL14:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO39 |
| TCELL14:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO4 |
| TCELL14:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO5 |
| TCELL14:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO6 |
| TCELL14:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO7 |
| TCELL14:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO36 |
| TCELL14:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO37 |
| TCELL14:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO38 |
| TCELL14:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO39 |
| TCELL14:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO4 |
| TCELL14:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO5 |
| TCELL14:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO6 |
| TCELL14:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO7 |
| TCELL15:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC63 |
| TCELL15:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC52 |
| TCELL15:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC51 |
| TCELL15:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC50 |
| TCELL15:IMUX.CLK0 | EMAC.PHYEMAC0GTXCLK |
| TCELL15:IMUX.CE0 | PPC.LSSDCE0A |
| TCELL15:IMUX.CE1 | PPC.BISTCE0TESTM1 |
| TCELL15:IMUX.CE2 | PPC.BISTCE0DIAGSHIFTSEL |
| TCELL15:IMUX.CE3 | PPC.BISTCE0LOADOPCODE |
| TCELL15:IMUX.IMUX0 | PPC.EXTDCRDBUSIN0 |
| TCELL15:IMUX.IMUX1 | PPC.EXTDCRDBUSIN1 |
| TCELL15:IMUX.IMUX2 | PPC.EXTDCRDBUSIN2 |
| TCELL15:IMUX.IMUX3 | PPC.EXTDCRDBUSIN3 |
| TCELL15:IMUX.IMUX4 | PPC.EXTDCRACK |
| TCELL15:IMUX.IMUX5 | PPC.CPMC405CORECLKINACTIVE |
| TCELL15:IMUX.IMUX6 | EMAC.TIEEMAC1CONFIGVEC64 |
| TCELL15:IMUX.IMUX7 | EMAC.TIEEMAC1CONFIGVEC65 |
| TCELL15:IMUX.IMUX8 | EMAC.TIEEMAC1CONFIGVEC66 |
| TCELL15:IMUX.IMUX9 | EMAC.TIEEMAC1CONFIGVEC67 |
| TCELL15:IMUX.IMUX10 | EMAC.TIEEMAC1CONFIGVEC68 |
| TCELL15:IMUX.IMUX11 | EMAC.TIEEMAC1CONFIGVEC69 |
| TCELL15:IMUX.IMUX12 | EMAC.TIEEMAC1CONFIGVEC70 |
| TCELL15:IMUX.IMUX13 | EMAC.TIEEMAC1CONFIGVEC71 |
| TCELL15:IMUX.IMUX14 | EMAC.TIEEMAC1CONFIGVEC72 |
| TCELL15:IMUX.IMUX15 | EMAC.EMAC1TIBUS4 |
| TCELL15:IMUX.IMUX16 | PPC.LSSDCE1B |
| TCELL15:OUT.BEST0.TMIN | PPC.EXTDCRDBUSOUT0 |
| TCELL15:OUT.BEST1.TMIN | PPC.EXTDCRDBUSOUT1 |
| TCELL15:OUT.BEST2.TMIN | PPC.EXTDCRDBUSOUT2 |
| TCELL15:OUT.BEST3.TMIN | PPC.EXTDCRDBUSOUT3 |
| TCELL15:OUT.BEST4.TMIN | PPC.EXTDCRABUS0 |
| TCELL15:OUT.BEST5.TMIN | PPC.EXTDCRABUS1 |
| TCELL15:OUT.BEST6.TMIN | PPC.EXTDCRABUS2 |
| TCELL15:OUT.BEST7.TMIN | PPC.EXTDCRABUS3 |
| TCELL15:OUT.SEC0.TMIN | PPC.C405DBGWBIAR0 |
| TCELL15:OUT.SEC1.TMIN | PPC.C405DBGWBIAR1 |
| TCELL15:OUT.SEC2.TMIN | PPC.C405DBGWBIAR2 |
| TCELL15:OUT.SEC3.TMIN | PPC.C405DBGWBIAR3 |
| TCELL15:OUT.SEC4.TMIN | EMAC.EMAC1PHYENCOMMAALIGN |
| TCELL15:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO32 |
| TCELL15:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO33 |
| TCELL15:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO34 |
| TCELL15:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO35 |
| TCELL15:OUT.HALF.BOT4.TMIN | PPC.TSTDSOCMC405RDDBUSO0 |
| TCELL15:OUT.HALF.BOT5.TMIN | PPC.TSTDSOCMC405RDDBUSO1 |
| TCELL15:OUT.HALF.BOT6.TMIN | PPC.TSTDSOCMC405RDDBUSO2 |
| TCELL15:OUT.HALF.BOT7.TMIN | PPC.TSTDSOCMC405RDDBUSO3 |
| TCELL15:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO32 |
| TCELL15:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO33 |
| TCELL15:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO34 |
| TCELL15:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO35 |
| TCELL15:OUT.HALT.TOP4.TMIN | PPC.TSTDSOCMC405RDDBUSO0 |
| TCELL15:OUT.HALT.TOP5.TMIN | PPC.TSTDSOCMC405RDDBUSO1 |
| TCELL15:OUT.HALT.TOP6.TMIN | PPC.TSTDSOCMC405RDDBUSO2 |
| TCELL15:OUT.HALT.TOP7.TMIN | PPC.TSTDSOCMC405RDDBUSO3 |
| TCELL16:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR7 |
| TCELL16:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR6 |
| TCELL16:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR5 |
| TCELL16:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR4 |
| TCELL16:IMUX.CLK0 | EMAC.HOSTCLK |
| TCELL16:IMUX.CE0 | EMAC.TIEEMAC1UNICASTADDR11 |
| TCELL16:IMUX.CE1 | EMAC.TIEEMAC1UNICASTADDR10 |
| TCELL16:IMUX.CE2 | EMAC.TIEEMAC1UNICASTADDR9 |
| TCELL16:IMUX.CE3 | EMAC.TIEEMAC1UNICASTADDR8 |
| TCELL16:IMUX.IMUX0 | EMAC.HOSTWRDATA14 |
| TCELL16:IMUX.IMUX1 | EMAC.HOSTWRDATA15 |
| TCELL16:IMUX.IMUX2 | EMAC.HOSTWRDATA16 |
| TCELL16:IMUX.IMUX3 | EMAC.HOSTWRDATA17 |
| TCELL16:IMUX.IMUX4 | EMAC.HOSTWRDATA18 |
| TCELL16:IMUX.IMUX5 | EMAC.HOSTWRDATA19 |
| TCELL16:IMUX.IMUX6 | EMAC.HOSTWRDATA20 |
| TCELL16:IMUX.IMUX7 | EMAC.HOSTWRDATA21 |
| TCELL16:IMUX.IMUX8 | EMAC.HOSTWRDATA22 |
| TCELL16:IMUX.IMUX9 | EMAC.HOSTWRDATA23 |
| TCELL16:IMUX.IMUX10 | EMAC.HOSTWRDATA24 |
| TCELL16:IMUX.IMUX11 | EMAC.HOSTWRDATA25 |
| TCELL16:IMUX.IMUX12 | EMAC.CLIENTEMAC1PAUSEVAL12 |
| TCELL16:IMUX.IMUX13 | EMAC.CLIENTEMAC1PAUSEVAL13 |
| TCELL16:IMUX.IMUX14 | EMAC.CLIENTEMAC1PAUSEVAL14 |
| TCELL16:IMUX.IMUX15 | EMAC.CLIENTEMAC1PAUSEVAL15 |
| TCELL16:IMUX.IMUX16 | PPC.TIEPVRBIT12 |
| TCELL16:IMUX.IMUX17 | PPC.TIEPVRBIT13 |
| TCELL16:IMUX.IMUX18 | PPC.TIEPVRBIT14 |
| TCELL16:IMUX.IMUX19 | PPC.TIEPVRBIT15 |
| TCELL16:OUT.BEST0.TMIN | EMAC.HOSTRDDATA16 |
| TCELL16:OUT.BEST1.TMIN | EMAC.HOSTRDDATA17 |
| TCELL16:OUT.BEST2.TMIN | EMAC.HOSTRDDATA18 |
| TCELL16:OUT.BEST3.TMIN | EMAC.HOSTRDDATA19 |
| TCELL16:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTRXD12 |
| TCELL16:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXD13 |
| TCELL16:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXD14 |
| TCELL16:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXD15 |
| TCELL16:OUT.SEC0.TMIN | EMAC.HOSTRDDATA20 |
| TCELL16:OUT.SEC1.TMIN | EMAC.HOSTRDDATA21 |
| TCELL16:OUT.SEC2.TMIN | EMAC.HOSTRDDATA22 |
| TCELL16:OUT.SEC3.TMIN | EMAC.HOSTRDDATA23 |
| TCELL16:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO28 |
| TCELL16:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO29 |
| TCELL16:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMWRDBUSO28 |
| TCELL16:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMWRDBUSO29 |
| TCELL16:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO30 |
| TCELL16:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO31 |
| TCELL16:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMSTOREREQO |
| TCELL16:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWAITO |
| TCELL16:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO28 |
| TCELL16:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO29 |
| TCELL16:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMWRDBUSO28 |
| TCELL16:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMWRDBUSO29 |
| TCELL16:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO30 |
| TCELL16:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO31 |
| TCELL16:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMSTOREREQO |
| TCELL16:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWAITO |
| TCELL17:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR15 |
| TCELL17:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR14 |
| TCELL17:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR13 |
| TCELL17:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR12 |
| TCELL17:IMUX.CLK0 | EMAC.EMAC1TIBUS0 |
| TCELL17:IMUX.CE0 | EMAC.TIEEMAC1UNICASTADDR19 |
| TCELL17:IMUX.CE1 | EMAC.TIEEMAC1UNICASTADDR18 |
| TCELL17:IMUX.CE2 | EMAC.TIEEMAC1UNICASTADDR17 |
| TCELL17:IMUX.CE3 | EMAC.TIEEMAC1UNICASTADDR16 |
| TCELL17:IMUX.IMUX0 | EMAC.HOSTWRDATA26 |
| TCELL17:IMUX.IMUX1 | EMAC.HOSTWRDATA27 |
| TCELL17:IMUX.IMUX2 | EMAC.HOSTWRDATA28 |
| TCELL17:IMUX.IMUX3 | EMAC.HOSTWRDATA29 |
| TCELL17:IMUX.IMUX4 | EMAC.HOSTWRDATA30 |
| TCELL17:IMUX.IMUX5 | EMAC.HOSTWRDATA31 |
| TCELL17:IMUX.IMUX6 | EMAC.HOSTOPCODE1 |
| TCELL17:IMUX.IMUX7 | EMAC.HOSTOPCODE0 |
| TCELL17:IMUX.IMUX8 | EMAC.HOSTMIIMSEL |
| TCELL17:IMUX.IMUX9 | EMAC.HOSTREQ |
| TCELL17:IMUX.IMUX10 | EMAC.HOSTEMAC1SEL |
| TCELL17:IMUX.IMUX11 | EMAC.CLIENTEMAC1PAUSEVAL8 |
| TCELL17:IMUX.IMUX12 | EMAC.CLIENTEMAC1PAUSEVAL9 |
| TCELL17:IMUX.IMUX13 | EMAC.CLIENTEMAC1PAUSEVAL10 |
| TCELL17:IMUX.IMUX14 | EMAC.CLIENTEMAC1PAUSEVAL11 |
| TCELL17:IMUX.IMUX15 | EMAC.DCREMACENABLE |
| TCELL17:IMUX.IMUX16 | PPC.TIEPVRBIT16 |
| TCELL17:IMUX.IMUX17 | PPC.TIEPVRBIT17 |
| TCELL17:IMUX.IMUX18 | PPC.TIEPVRBIT18 |
| TCELL17:IMUX.IMUX19 | PPC.TIEPVRBIT19 |
| TCELL17:OUT.BEST0.TMIN | EMAC.HOSTRDDATA24 |
| TCELL17:OUT.BEST1.TMIN | EMAC.HOSTRDDATA25 |
| TCELL17:OUT.BEST2.TMIN | EMAC.HOSTRDDATA26 |
| TCELL17:OUT.BEST3.TMIN | EMAC.HOSTRDDATA27 |
| TCELL17:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTRXD8 |
| TCELL17:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXD9 |
| TCELL17:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXD10 |
| TCELL17:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXD11 |
| TCELL17:OUT.SEC0.TMIN | EMAC.HOSTRDDATA28 |
| TCELL17:OUT.SEC1.TMIN | EMAC.HOSTRDDATA29 |
| TCELL17:OUT.SEC2.TMIN | EMAC.HOSTRDDATA30 |
| TCELL17:OUT.SEC3.TMIN | EMAC.HOSTRDDATA31 |
| TCELL17:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO24 |
| TCELL17:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO25 |
| TCELL17:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO26 |
| TCELL17:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO27 |
| TCELL17:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO24 |
| TCELL17:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO25 |
| TCELL17:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO26 |
| TCELL17:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO27 |
| TCELL17:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO24 |
| TCELL17:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO25 |
| TCELL17:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO26 |
| TCELL17:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO27 |
| TCELL17:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO24 |
| TCELL17:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO25 |
| TCELL17:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO26 |
| TCELL17:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO27 |
| TCELL18:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR23 |
| TCELL18:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR22 |
| TCELL18:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR21 |
| TCELL18:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR20 |
| TCELL18:IMUX.CLK0 | EMAC.EMAC1TIBUS1 |
| TCELL18:IMUX.CE0 | EMAC.TIEEMAC1UNICASTADDR27 |
| TCELL18:IMUX.CE1 | EMAC.TIEEMAC1UNICASTADDR26 |
| TCELL18:IMUX.CE2 | EMAC.TIEEMAC1UNICASTADDR25 |
| TCELL18:IMUX.CE3 | EMAC.TIEEMAC1UNICASTADDR24 |
| TCELL18:IMUX.IMUX0 | EMAC.CLIENTEMAC1TXD12 |
| TCELL18:IMUX.IMUX1 | EMAC.CLIENTEMAC1TXD13 |
| TCELL18:IMUX.IMUX2 | EMAC.CLIENTEMAC1TXD14 |
| TCELL18:IMUX.IMUX3 | EMAC.CLIENTEMAC1TXD15 |
| TCELL18:IMUX.IMUX4 | EMAC.CLIENTEMAC1TXIFGDELAY4 |
| TCELL18:IMUX.IMUX5 | EMAC.CLIENTEMAC1TXIFGDELAY5 |
| TCELL18:IMUX.IMUX6 | EMAC.CLIENTEMAC1TXIFGDELAY6 |
| TCELL18:IMUX.IMUX7 | EMAC.CLIENTEMAC1TXIFGDELAY7 |
| TCELL18:IMUX.IMUX8 | EMAC.CLIENTEMAC1PAUSEVAL4 |
| TCELL18:IMUX.IMUX9 | EMAC.CLIENTEMAC1PAUSEVAL5 |
| TCELL18:IMUX.IMUX10 | EMAC.CLIENTEMAC1PAUSEVAL6 |
| TCELL18:IMUX.IMUX11 | EMAC.CLIENTEMAC1PAUSEVAL7 |
| TCELL18:IMUX.IMUX12 | EMAC.CLIENTEMAC1DCMLOCKED |
| TCELL18:IMUX.IMUX13 | EMAC.TSTSIEMACI0 |
| TCELL18:IMUX.IMUX14 | EMAC.TSTSIEMACI1 |
| TCELL18:IMUX.IMUX15 | PPC.TIEPVRBIT20 |
| TCELL18:IMUX.IMUX16 | PPC.TIEPVRBIT21 |
| TCELL18:IMUX.IMUX17 | PPC.TIEPVRBIT22 |
| TCELL18:IMUX.IMUX18 | PPC.TIEPVRBIT23 |
| TCELL18:OUT.BEST0.TMIN | EMAC.EMAC1PHYSYNCACQSTATUS |
| TCELL18:OUT.BEST1.TMIN | EMAC.EMAC1PHYMCLKOUT |
| TCELL18:OUT.BEST2.TMIN | EMAC.EMAC1PHYMDTRI |
| TCELL18:OUT.BEST3.TMIN | EMAC.EMAC1PHYMDOUT |
| TCELL18:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTRXD4 |
| TCELL18:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXD5 |
| TCELL18:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXD6 |
| TCELL18:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXD7 |
| TCELL18:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO8 |
| TCELL18:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO9 |
| TCELL18:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO10 |
| TCELL18:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO11 |
| TCELL18:OUT.SEC4.TMIN | EMAC.EMAC1CLIENTRXDVREG6 |
| TCELL18:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO20 |
| TCELL18:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO21 |
| TCELL18:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO22 |
| TCELL18:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO23 |
| TCELL18:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO20 |
| TCELL18:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO21 |
| TCELL18:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO22 |
| TCELL18:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO23 |
| TCELL18:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO20 |
| TCELL18:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO21 |
| TCELL18:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO22 |
| TCELL18:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO23 |
| TCELL18:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO20 |
| TCELL18:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO21 |
| TCELL18:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO22 |
| TCELL18:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO23 |
| TCELL19:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR31 |
| TCELL19:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR30 |
| TCELL19:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR29 |
| TCELL19:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR28 |
| TCELL19:IMUX.CLK0 | EMAC.PHYEMAC1MCLKIN |
| TCELL19:IMUX.CE0 | EMAC.TIEEMAC1UNICASTADDR35 |
| TCELL19:IMUX.CE1 | EMAC.TIEEMAC1UNICASTADDR34 |
| TCELL19:IMUX.CE2 | EMAC.TIEEMAC1UNICASTADDR33 |
| TCELL19:IMUX.CE3 | EMAC.TIEEMAC1UNICASTADDR32 |
| TCELL19:IMUX.IMUX0 | EMAC.CLIENTEMAC1TXD8 |
| TCELL19:IMUX.IMUX1 | EMAC.CLIENTEMAC1TXD9 |
| TCELL19:IMUX.IMUX2 | EMAC.CLIENTEMAC1TXD10 |
| TCELL19:IMUX.IMUX3 | EMAC.CLIENTEMAC1TXD11 |
| TCELL19:IMUX.IMUX4 | EMAC.CLIENTEMAC1TXIFGDELAY0 |
| TCELL19:IMUX.IMUX5 | EMAC.CLIENTEMAC1TXIFGDELAY1 |
| TCELL19:IMUX.IMUX6 | EMAC.CLIENTEMAC1TXIFGDELAY2 |
| TCELL19:IMUX.IMUX7 | EMAC.CLIENTEMAC1TXIFGDELAY3 |
| TCELL19:IMUX.IMUX8 | EMAC.CLIENTEMAC1PAUSEVAL0 |
| TCELL19:IMUX.IMUX9 | EMAC.CLIENTEMAC1PAUSEVAL1 |
| TCELL19:IMUX.IMUX10 | EMAC.CLIENTEMAC1PAUSEVAL2 |
| TCELL19:IMUX.IMUX11 | EMAC.CLIENTEMAC1PAUSEVAL3 |
| TCELL19:IMUX.IMUX12 | EMAC.PHYEMAC1SIGNALDET |
| TCELL19:IMUX.IMUX13 | EMAC.TSTSIEMACI2 |
| TCELL19:IMUX.IMUX14 | EMAC.TSTSIEMACI3 |
| TCELL19:IMUX.IMUX15 | PPC.TIEPVRBIT24 |
| TCELL19:IMUX.IMUX16 | PPC.TIEPVRBIT25 |
| TCELL19:IMUX.IMUX17 | PPC.TIEPVRBIT26 |
| TCELL19:IMUX.IMUX18 | PPC.TIEPVRBIT27 |
| TCELL19:OUT.BEST0.TMIN | EMAC.EMAC1CLIENTRXD0 |
| TCELL19:OUT.BEST1.TMIN | EMAC.EMAC1CLIENTRXD1 |
| TCELL19:OUT.BEST2.TMIN | EMAC.EMAC1CLIENTRXD2 |
| TCELL19:OUT.BEST3.TMIN | EMAC.EMAC1CLIENTRXD3 |
| TCELL19:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTTXSTATS |
| TCELL19:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXSTATS6 |
| TCELL19:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXSTATS4 |
| TCELL19:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXSTATS5 |
| TCELL19:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO4 |
| TCELL19:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO5 |
| TCELL19:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO6 |
| TCELL19:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO7 |
| TCELL19:OUT.SEC4.TMIN | EMAC.EMAC1PHYPOWERDOWN |
| TCELL19:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO16 |
| TCELL19:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO17 |
| TCELL19:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO18 |
| TCELL19:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO19 |
| TCELL19:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO16 |
| TCELL19:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO17 |
| TCELL19:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO18 |
| TCELL19:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO19 |
| TCELL19:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO16 |
| TCELL19:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO17 |
| TCELL19:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO18 |
| TCELL19:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO19 |
| TCELL19:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO16 |
| TCELL19:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO17 |
| TCELL19:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO18 |
| TCELL19:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO19 |
| TCELL20:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR39 |
| TCELL20:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR38 |
| TCELL20:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR37 |
| TCELL20:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR36 |
| TCELL20:IMUX.CLK0 | EMAC.CLIENTEMAC1RXCLIENTCLKIN |
| TCELL20:IMUX.CE0 | EMAC.TIEEMAC1UNICASTADDR43 |
| TCELL20:IMUX.CE1 | EMAC.TIEEMAC1UNICASTADDR42 |
| TCELL20:IMUX.CE2 | EMAC.TIEEMAC1UNICASTADDR41 |
| TCELL20:IMUX.CE3 | EMAC.TIEEMAC1UNICASTADDR40 |
| TCELL20:IMUX.IMUX0 | EMAC.CLIENTEMAC1TXFIRSTBYTE |
| TCELL20:IMUX.IMUX1 | EMAC.PHYEMAC1RXCLKCORCNT0 |
| TCELL20:IMUX.IMUX2 | EMAC.PHYEMAC1RXRUNDISP |
| TCELL20:IMUX.IMUX3 | EMAC.PHYEMAC1TXBUFERR |
| TCELL20:IMUX.IMUX4 | EMAC.PHYEMAC1MDIN |
| TCELL20:IMUX.IMUX5 | EMAC.CLIENTEMAC1TXD4 |
| TCELL20:IMUX.IMUX6 | EMAC.CLIENTEMAC1TXD5 |
| TCELL20:IMUX.IMUX7 | EMAC.CLIENTEMAC1TXD6 |
| TCELL20:IMUX.IMUX8 | EMAC.CLIENTEMAC1TXD7 |
| TCELL20:IMUX.IMUX9 | EMAC.TIEEMAC1CONFIGVEC77 |
| TCELL20:IMUX.IMUX10 | EMAC.TIEEMAC1CONFIGVEC78 |
| TCELL20:IMUX.IMUX11 | EMAC.TIEEMAC1CONFIGVEC79 |
| TCELL20:IMUX.IMUX12 | EMAC.PHYEMAC1RXBUFERR |
| TCELL20:IMUX.IMUX13 | PPC.TSTSIGASKETI0 |
| TCELL20:IMUX.IMUX14 | PPC.TSTSIGASKETI1 |
| TCELL20:IMUX.IMUX15 | PPC.TIEPVRBIT0 |
| TCELL20:IMUX.IMUX16 | PPC.TIEPVRBIT1 |
| TCELL20:IMUX.IMUX17 | PPC.TIEPVRBIT2 |
| TCELL20:IMUX.IMUX18 | PPC.TIEPVRBIT3 |
| TCELL20:OUT.BEST0.TMIN | EMAC.EMAC1PHYTXCHARDISPMODE |
| TCELL20:OUT.BEST1.TMIN | EMAC.EMAC1PHYTXCHARDISPVAL |
| TCELL20:OUT.BEST2.TMIN | EMAC.EMAC1CLIENTTXGMIIMIICLKOUT |
| TCELL20:OUT.BEST3.TMIN | EMAC.EMAC1PHYLOOPBACKMSB |
| TCELL20:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTRXCLIENTCLKOUT |
| TCELL20:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXFRAMEDROP |
| TCELL20:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXGOODFRAME |
| TCELL20:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXBADFRAME |
| TCELL20:OUT.SEC0.TMIN | PPC.TSTDCRC405DBUSINO0 |
| TCELL20:OUT.SEC1.TMIN | PPC.TSTDCRC405DBUSINO1 |
| TCELL20:OUT.SEC2.TMIN | PPC.TSTDCRC405DBUSINO2 |
| TCELL20:OUT.SEC3.TMIN | PPC.TSTDCRC405DBUSINO3 |
| TCELL20:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO12 |
| TCELL20:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO13 |
| TCELL20:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO14 |
| TCELL20:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO15 |
| TCELL20:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO12 |
| TCELL20:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO13 |
| TCELL20:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO14 |
| TCELL20:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO15 |
| TCELL20:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO12 |
| TCELL20:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO13 |
| TCELL20:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO14 |
| TCELL20:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO15 |
| TCELL20:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO12 |
| TCELL20:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO13 |
| TCELL20:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO14 |
| TCELL20:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO15 |
| TCELL21:IMUX.SR0 | EMAC.TIEEMAC1UNICASTADDR47 |
| TCELL21:IMUX.SR1 | EMAC.TIEEMAC1UNICASTADDR46 |
| TCELL21:IMUX.SR2 | EMAC.TIEEMAC1UNICASTADDR45 |
| TCELL21:IMUX.SR3 | EMAC.TIEEMAC1UNICASTADDR44 |
| TCELL21:IMUX.CLK0 | EMAC.CLIENTEMAC1TXGMIIMIICLKIN |
| TCELL21:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC3 |
| TCELL21:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC2 |
| TCELL21:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC1 |
| TCELL21:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC0 |
| TCELL21:IMUX.IMUX0 | EMAC.PHYEMAC1RXNOTINTABLE |
| TCELL21:IMUX.IMUX1 | EMAC.PHYEMAC1RXDISPERR |
| TCELL21:IMUX.IMUX2 | EMAC.PHYEMAC1RXCHARISK |
| TCELL21:IMUX.IMUX3 | EMAC.PHYEMAC1RXCHARISCOMMA |
| TCELL21:IMUX.IMUX4 | EMAC.PHYEMAC1RXBUFSTATUS0 |
| TCELL21:IMUX.IMUX5 | EMAC.PHYEMAC1RXBUFSTATUS1 |
| TCELL21:IMUX.IMUX6 | EMAC.PHYEMAC1RXLOSSOFSYNC0 |
| TCELL21:IMUX.IMUX7 | EMAC.PHYEMAC1RXLOSSOFSYNC1 |
| TCELL21:IMUX.IMUX8 | EMAC.CLIENTEMAC1TXD0 |
| TCELL21:IMUX.IMUX9 | EMAC.CLIENTEMAC1TXD1 |
| TCELL21:IMUX.IMUX10 | EMAC.CLIENTEMAC1TXD2 |
| TCELL21:IMUX.IMUX11 | EMAC.CLIENTEMAC1TXD3 |
| TCELL21:IMUX.IMUX12 | EMAC.PHYEMAC1RXCLKCORCNT1 |
| TCELL21:IMUX.IMUX13 | EMAC.PHYEMAC1RXCLKCORCNT2 |
| TCELL21:IMUX.IMUX14 | EMAC.TSTSIEMACI4 |
| TCELL21:IMUX.IMUX15 | PPC.TIEPVRBIT4 |
| TCELL21:IMUX.IMUX16 | PPC.TIEPVRBIT5 |
| TCELL21:IMUX.IMUX17 | PPC.TIEPVRBIT6 |
| TCELL21:IMUX.IMUX18 | PPC.TIEPVRBIT7 |
| TCELL21:OUT.BEST0.TMIN | EMAC.EMAC1PHYMGTRXRESET |
| TCELL21:OUT.BEST1.TMIN | EMAC.EMAC1CLIENTTXCLIENTCLKOUT |
| TCELL21:OUT.BEST2.TMIN | EMAC.EMAC1CLIENTTXACK |
| TCELL21:OUT.BEST3.TMIN | EMAC.EMAC1CLIENTTXCOLLISION |
| TCELL21:OUT.BEST4.TMIN | EMAC.EMAC1CLIENTTXRETRANSMIT |
| TCELL21:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTTXSTATSBYTEVLD |
| TCELL21:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXSTATSBYTEVLD |
| TCELL21:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTTXSTATSVLD |
| TCELL21:OUT.SEC0.TMIN | PPC.DSOCMBRAMABUS8 |
| TCELL21:OUT.SEC1.TMIN | PPC.DSOCMBRAMABUS9 |
| TCELL21:OUT.SEC2.TMIN | PPC.DSOCMBRAMABUS10 |
| TCELL21:OUT.SEC3.TMIN | PPC.DSOCMBRAMABUS11 |
| TCELL21:OUT.SEC4.TMIN | PPC.TSTPLBSAMPLECYCLEO |
| TCELL21:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO8 |
| TCELL21:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO9 |
| TCELL21:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO10 |
| TCELL21:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO11 |
| TCELL21:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO8 |
| TCELL21:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO9 |
| TCELL21:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO10 |
| TCELL21:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO11 |
| TCELL21:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO8 |
| TCELL21:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO9 |
| TCELL21:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO10 |
| TCELL21:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO11 |
| TCELL21:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO8 |
| TCELL21:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO9 |
| TCELL21:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO10 |
| TCELL21:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO11 |
| TCELL22:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC7 |
| TCELL22:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC6 |
| TCELL22:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC5 |
| TCELL22:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC4 |
| TCELL22:IMUX.CLK0 | EMAC.CLIENTEMAC1TXCLIENTCLKIN |
| TCELL22:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC11 |
| TCELL22:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC10 |
| TCELL22:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC9 |
| TCELL22:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC8 |
| TCELL22:IMUX.IMUX0 | EMAC.PHYEMAC1RXD4 |
| TCELL22:IMUX.IMUX1 | EMAC.PHYEMAC1RXD5 |
| TCELL22:IMUX.IMUX2 | EMAC.PHYEMAC1RXD6 |
| TCELL22:IMUX.IMUX3 | EMAC.PHYEMAC1RXD7 |
| TCELL22:IMUX.IMUX4 | EMAC.PHYEMAC1RXDV |
| TCELL22:IMUX.IMUX5 | EMAC.PHYEMAC1RXER |
| TCELL22:IMUX.IMUX6 | EMAC.PHYEMAC1RXCOMMADET |
| TCELL22:IMUX.IMUX7 | EMAC.PHYEMAC1RXCHECKINGCRC |
| TCELL22:IMUX.IMUX8 | EMAC.EMAC1TIBUS3 |
| TCELL22:IMUX.IMUX9 | EMAC.EMAC1TIBUS2 |
| TCELL22:IMUX.IMUX10 | EMAC.CLIENTEMAC1TXUNDERRUN |
| TCELL22:IMUX.IMUX11 | EMAC.CLIENTEMAC1PAUSEREQ |
| TCELL22:IMUX.IMUX12 | EMAC.CLIENTEMAC1TXDVLD |
| TCELL22:IMUX.IMUX13 | EMAC.CLIENTEMAC1TXDVLDMSW |
| TCELL22:IMUX.IMUX14 | EMAC.PHYEMAC1PHYAD1 |
| TCELL22:IMUX.IMUX15 | EMAC.PHYEMAC1PHYAD0 |
| TCELL22:IMUX.IMUX16 | PPC.TSTTRSTNEGI |
| TCELL22:OUT.BEST0.TMIN | EMAC.EMAC1PHYTXD4 |
| TCELL22:OUT.BEST1.TMIN | EMAC.EMAC1PHYTXD5 |
| TCELL22:OUT.BEST2.TMIN | EMAC.EMAC1PHYTXD6 |
| TCELL22:OUT.BEST3.TMIN | EMAC.EMAC1PHYTXD7 |
| TCELL22:OUT.BEST4.TMIN | EMAC.EMAC1PHYTXCHARISK |
| TCELL22:OUT.BEST5.TMIN | EMAC.EMAC1CLIENTRXDVLDMSW |
| TCELL22:OUT.BEST6.TMIN | EMAC.EMAC1CLIENTRXDVLD |
| TCELL22:OUT.BEST7.TMIN | EMAC.EMAC1CLIENTRXSTATSVLD |
| TCELL22:OUT.SEC0.TMIN | EMAC.EMAC1CLIENTRXSTATS0 |
| TCELL22:OUT.SEC1.TMIN | EMAC.EMAC1CLIENTRXSTATS1 |
| TCELL22:OUT.SEC2.TMIN | EMAC.EMAC1CLIENTRXSTATS2 |
| TCELL22:OUT.SEC3.TMIN | EMAC.EMAC1CLIENTRXSTATS3 |
| TCELL22:OUT.SEC4.TMIN | PPC.DSOCMWRADDRVALID |
| TCELL22:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO4 |
| TCELL22:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO5 |
| TCELL22:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO6 |
| TCELL22:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO7 |
| TCELL22:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO4 |
| TCELL22:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO5 |
| TCELL22:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO6 |
| TCELL22:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO7 |
| TCELL22:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO4 |
| TCELL22:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO5 |
| TCELL22:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO6 |
| TCELL22:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO7 |
| TCELL22:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO4 |
| TCELL22:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO5 |
| TCELL22:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO6 |
| TCELL22:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO7 |
| TCELL23:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC15 |
| TCELL23:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC14 |
| TCELL23:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC13 |
| TCELL23:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC12 |
| TCELL23:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC19 |
| TCELL23:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC18 |
| TCELL23:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC17 |
| TCELL23:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC16 |
| TCELL23:IMUX.IMUX0 | EMAC.PHYEMAC1RXD0 |
| TCELL23:IMUX.IMUX1 | EMAC.PHYEMAC1RXD1 |
| TCELL23:IMUX.IMUX2 | EMAC.PHYEMAC1RXD2 |
| TCELL23:IMUX.IMUX3 | EMAC.PHYEMAC1RXD3 |
| TCELL23:IMUX.IMUX4 | EMAC.PHYEMAC1CRS |
| TCELL23:IMUX.IMUX5 | EMAC.PHYEMAC1COL |
| TCELL23:IMUX.IMUX6 | EMAC.TIEEMAC1CONFIGVEC25 |
| TCELL23:IMUX.IMUX7 | EMAC.TIEEMAC1CONFIGVEC24 |
| TCELL23:IMUX.IMUX8 | EMAC.TIEEMAC1CONFIGVEC23 |
| TCELL23:IMUX.IMUX9 | EMAC.TIEEMAC1CONFIGVEC22 |
| TCELL23:IMUX.IMUX10 | EMAC.TIEEMAC1CONFIGVEC21 |
| TCELL23:IMUX.IMUX11 | EMAC.TIEEMAC1CONFIGVEC20 |
| TCELL23:IMUX.IMUX12 | EMAC.PHYEMAC1PHYAD4 |
| TCELL23:IMUX.IMUX13 | EMAC.PHYEMAC1PHYAD3 |
| TCELL23:IMUX.IMUX14 | EMAC.PHYEMAC1PHYAD2 |
| TCELL23:IMUX.IMUX15 | EMAC.TSTSIEMACI5 |
| TCELL23:OUT.BEST0.TMIN | EMAC.EMAC1PHYTXD0 |
| TCELL23:OUT.BEST1.TMIN | EMAC.EMAC1PHYTXD1 |
| TCELL23:OUT.BEST2.TMIN | EMAC.EMAC1PHYTXD2 |
| TCELL23:OUT.BEST3.TMIN | EMAC.EMAC1PHYTXD3 |
| TCELL23:OUT.BEST4.TMIN | EMAC.EMAC1PHYTXCLK |
| TCELL23:OUT.BEST5.TMIN | EMAC.EMAC1PHYTXEN |
| TCELL23:OUT.BEST6.TMIN | EMAC.EMAC1PHYTXER |
| TCELL23:OUT.BEST7.TMIN | EMAC.DCRHOSTDONEIR |
| TCELL23:OUT.SEC0.TMIN | PPC.DSOCMBRAMABUS12 |
| TCELL23:OUT.SEC1.TMIN | PPC.DSOCMBRAMABUS13 |
| TCELL23:OUT.SEC2.TMIN | PPC.DSOCMBRAMABUS14 |
| TCELL23:OUT.SEC3.TMIN | PPC.DSOCMBRAMABUS15 |
| TCELL23:OUT.SEC4.TMIN | EMAC.EMAC1PHYMGTTXRESET |
| TCELL23:OUT.HALF.BOT0.TMIN | PPC.TSTC405DSOCMABUSO0 |
| TCELL23:OUT.HALF.BOT1.TMIN | PPC.TSTC405DSOCMABUSO1 |
| TCELL23:OUT.HALF.BOT2.TMIN | PPC.TSTC405DSOCMABUSO2 |
| TCELL23:OUT.HALF.BOT3.TMIN | PPC.TSTC405DSOCMABUSO3 |
| TCELL23:OUT.HALF.BOT4.TMIN | PPC.TSTC405DSOCMWRDBUSO0 |
| TCELL23:OUT.HALF.BOT5.TMIN | PPC.TSTC405DSOCMWRDBUSO1 |
| TCELL23:OUT.HALF.BOT6.TMIN | PPC.TSTC405DSOCMWRDBUSO2 |
| TCELL23:OUT.HALF.BOT7.TMIN | PPC.TSTC405DSOCMWRDBUSO3 |
| TCELL23:OUT.HALT.TOP0.TMIN | PPC.TSTC405DSOCMABUSO0 |
| TCELL23:OUT.HALT.TOP1.TMIN | PPC.TSTC405DSOCMABUSO1 |
| TCELL23:OUT.HALT.TOP2.TMIN | PPC.TSTC405DSOCMABUSO2 |
| TCELL23:OUT.HALT.TOP3.TMIN | PPC.TSTC405DSOCMABUSO3 |
| TCELL23:OUT.HALT.TOP4.TMIN | PPC.TSTC405DSOCMWRDBUSO0 |
| TCELL23:OUT.HALT.TOP5.TMIN | PPC.TSTC405DSOCMWRDBUSO1 |
| TCELL23:OUT.HALT.TOP6.TMIN | PPC.TSTC405DSOCMWRDBUSO2 |
| TCELL23:OUT.HALT.TOP7.TMIN | PPC.TSTC405DSOCMWRDBUSO3 |
| TCELL24:IMUX.SR0 | PPC.TIEAPUUDI819 |
| TCELL24:IMUX.SR1 | PPC.TIEAPUUDI818 |
| TCELL24:IMUX.SR2 | PPC.TIEAPUUDI817 |
| TCELL24:IMUX.SR3 | PPC.TIEAPUUDI816 |
| TCELL24:IMUX.CE0 | PPC.TIEAPUUDI823 |
| TCELL24:IMUX.CE1 | PPC.TIEAPUUDI822 |
| TCELL24:IMUX.CE2 | PPC.TIEAPUUDI821 |
| TCELL24:IMUX.CE3 | PPC.TIEAPUUDI820 |
| TCELL24:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS60 |
| TCELL24:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS61 |
| TCELL24:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS62 |
| TCELL24:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS63 |
| TCELL24:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS60 |
| TCELL24:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS61 |
| TCELL24:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS62 |
| TCELL24:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS63 |
| TCELL24:IMUX.IMUX8 | PPC.TRCC405TRACEDISABLE |
| TCELL24:IMUX.IMUX9 | PPC.TRCC405TRIGGEREVENTIN |
| TCELL24:IMUX.IMUX10 | PPC.TSTC405APUWBBYTEENI0 |
| TCELL24:IMUX.IMUX11 | PPC.TSTC405APUWBBYTEENI1 |
| TCELL24:IMUX.IMUX12 | PPC.TSTC405APUWBBYTEENI2 |
| TCELL24:IMUX.IMUX13 | PPC.TSTC405APUWBBYTEENI3 |
| TCELL24:IMUX.IMUX14 | PPC.TSTC405ISOCMREQPENDINGI |
| TCELL24:IMUX.IMUX15 | PPC.TSTC405ISOCMICUREADYI |
| TCELL24:IMUX.IMUX16 | PPC.TSTC405ISOCMXLTVALIDI |
| TCELL24:IMUX.IMUX17 | PPC.TSTC405ISOCMABORTI |
| TCELL24:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS60 |
| TCELL24:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS61 |
| TCELL24:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS62 |
| TCELL24:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS63 |
| TCELL24:OUT.BEST4.TMIN | PPC.C405TRCTRIGGEREVENTTYPE0 |
| TCELL24:OUT.BEST5.TMIN | PPC.C405TRCTRIGGEREVENTTYPE1 |
| TCELL24:OUT.BEST6.TMIN | PPC.C405TRCTRIGGEREVENTTYPE2 |
| TCELL24:OUT.BEST7.TMIN | PPC.C405TRCTRIGGEREVENTTYPE3 |
| TCELL24:OUT.SEC0.TMIN | PPC.C405TRCTRIGGEREVENTTYPE4 |
| TCELL24:OUT.SEC1.TMIN | PPC.C405TRCTRIGGEREVENTTYPE5 |
| TCELL24:OUT.SEC2.TMIN | PPC.C405TRCTRIGGEREVENTTYPE6 |
| TCELL24:OUT.SEC3.TMIN | PPC.C405TRCTRIGGEREVENTTYPE7 |
| TCELL24:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO24 |
| TCELL24:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO25 |
| TCELL24:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO26 |
| TCELL24:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO27 |
| TCELL24:OUT.HALF.BOT4.TMIN | PPC.TSTISOCMC405READDATAOUTO28 |
| TCELL24:OUT.HALF.BOT5.TMIN | PPC.TSTISOCMC405READDATAOUTO29 |
| TCELL24:OUT.HALF.BOT6.TMIN | PPC.TSTISOCMC405READDATAOUTO30 |
| TCELL24:OUT.HALF.BOT7.TMIN | PPC.TSTISOCMC405READDATAOUTO31 |
| TCELL24:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO24 |
| TCELL24:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO25 |
| TCELL24:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO26 |
| TCELL24:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO27 |
| TCELL24:OUT.HALT.TOP4.TMIN | PPC.TSTISOCMC405READDATAOUTO28 |
| TCELL24:OUT.HALT.TOP5.TMIN | PPC.TSTISOCMC405READDATAOUTO29 |
| TCELL24:OUT.HALT.TOP6.TMIN | PPC.TSTISOCMC405READDATAOUTO30 |
| TCELL24:OUT.HALT.TOP7.TMIN | PPC.TSTISOCMC405READDATAOUTO31 |
| TCELL25:IMUX.SR0 | PPC.TIEAPUUDI811 |
| TCELL25:IMUX.SR1 | PPC.TIEAPUUDI810 |
| TCELL25:IMUX.SR2 | PPC.TIEAPUUDI89 |
| TCELL25:IMUX.SR3 | PPC.TIEAPUUDI88 |
| TCELL25:IMUX.CE0 | PPC.TIEAPUUDI815 |
| TCELL25:IMUX.CE1 | PPC.TIEAPUUDI814 |
| TCELL25:IMUX.CE2 | PPC.TIEAPUUDI813 |
| TCELL25:IMUX.CE3 | PPC.TIEAPUUDI812 |
| TCELL25:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS56 |
| TCELL25:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS57 |
| TCELL25:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS58 |
| TCELL25:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS59 |
| TCELL25:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS56 |
| TCELL25:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS57 |
| TCELL25:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS58 |
| TCELL25:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS59 |
| TCELL25:IMUX.IMUX8 | PPC.TSTC405APUEXERBDATAI24 |
| TCELL25:IMUX.IMUX9 | PPC.TSTC405APUEXERBDATAI25 |
| TCELL25:IMUX.IMUX10 | PPC.TSTC405APUEXERBDATAI26 |
| TCELL25:IMUX.IMUX11 | PPC.TSTC405APUEXERBDATAI27 |
| TCELL25:IMUX.IMUX12 | PPC.TSTC405APUEXERBDATAI28 |
| TCELL25:IMUX.IMUX13 | PPC.TSTC405APUEXERBDATAI29 |
| TCELL25:IMUX.IMUX14 | PPC.TSTC405APUEXERBDATAI30 |
| TCELL25:IMUX.IMUX15 | PPC.TSTC405APUEXERBDATAI31 |
| TCELL25:IMUX.IMUX16 | PPC.TSTC405APUEXELOADDBUSI28 |
| TCELL25:IMUX.IMUX17 | PPC.TSTC405APUEXELOADDBUSI29 |
| TCELL25:IMUX.IMUX18 | PPC.TSTC405APUEXELOADDBUSI30 |
| TCELL25:IMUX.IMUX19 | PPC.TSTC405APUEXELOADDBUSI31 |
| TCELL25:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS56 |
| TCELL25:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS57 |
| TCELL25:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS58 |
| TCELL25:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS59 |
| TCELL25:OUT.BEST4.TMIN | PPC.C405TRCTRIGGEREVENTTYPE8 |
| TCELL25:OUT.BEST5.TMIN | PPC.C405TRCTRIGGEREVENTTYPE9 |
| TCELL25:OUT.BEST6.TMIN | PPC.C405TRCTRIGGEREVENTTYPE10 |
| TCELL25:OUT.BEST7.TMIN | PPC.C405TRCTRIGGEREVENTOUT |
| TCELL25:OUT.SEC0.TMIN | PPC.C405TRCTRACESTATUS0 |
| TCELL25:OUT.SEC1.TMIN | PPC.C405TRCTRACESTATUS1 |
| TCELL25:OUT.SEC2.TMIN | PPC.C405TRCTRACESTATUS2 |
| TCELL25:OUT.SEC3.TMIN | PPC.C405TRCTRACESTATUS3 |
| TCELL25:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO16 |
| TCELL25:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO17 |
| TCELL25:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO18 |
| TCELL25:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO19 |
| TCELL25:OUT.HALF.BOT4.TMIN | PPC.TSTISOCMC405READDATAOUTO20 |
| TCELL25:OUT.HALF.BOT5.TMIN | PPC.TSTISOCMC405READDATAOUTO21 |
| TCELL25:OUT.HALF.BOT6.TMIN | PPC.TSTISOCMC405READDATAOUTO22 |
| TCELL25:OUT.HALF.BOT7.TMIN | PPC.TSTISOCMC405READDATAOUTO23 |
| TCELL25:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO16 |
| TCELL25:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO17 |
| TCELL25:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO18 |
| TCELL25:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO19 |
| TCELL25:OUT.HALT.TOP4.TMIN | PPC.TSTISOCMC405READDATAOUTO20 |
| TCELL25:OUT.HALT.TOP5.TMIN | PPC.TSTISOCMC405READDATAOUTO21 |
| TCELL25:OUT.HALT.TOP6.TMIN | PPC.TSTISOCMC405READDATAOUTO22 |
| TCELL25:OUT.HALT.TOP7.TMIN | PPC.TSTISOCMC405READDATAOUTO23 |
| TCELL26:IMUX.SR0 | PPC.TIEAPUUDI83 |
| TCELL26:IMUX.SR1 | PPC.TIEAPUUDI82 |
| TCELL26:IMUX.SR2 | PPC.TIEAPUUDI81 |
| TCELL26:IMUX.SR3 | PPC.TIEAPUUDI80 |
| TCELL26:IMUX.CE0 | PPC.TIEAPUUDI87 |
| TCELL26:IMUX.CE1 | PPC.TIEAPUUDI86 |
| TCELL26:IMUX.CE2 | PPC.TIEAPUUDI85 |
| TCELL26:IMUX.CE3 | PPC.TIEAPUUDI84 |
| TCELL26:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS52 |
| TCELL26:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS53 |
| TCELL26:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS54 |
| TCELL26:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS55 |
| TCELL26:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS52 |
| TCELL26:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS53 |
| TCELL26:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS54 |
| TCELL26:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS55 |
| TCELL26:IMUX.IMUX8 | PPC.TSTC405APUEXELOADDBUSI20 |
| TCELL26:IMUX.IMUX9 | PPC.TSTC405APUEXELOADDBUSI21 |
| TCELL26:IMUX.IMUX10 | PPC.TSTC405APUEXELOADDBUSI22 |
| TCELL26:IMUX.IMUX11 | PPC.TSTC405APUEXELOADDBUSI23 |
| TCELL26:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI24 |
| TCELL26:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI25 |
| TCELL26:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI26 |
| TCELL26:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI27 |
| TCELL26:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI20 |
| TCELL26:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI21 |
| TCELL26:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI22 |
| TCELL26:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI23 |
| TCELL26:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS52 |
| TCELL26:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS53 |
| TCELL26:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS54 |
| TCELL26:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS55 |
| TCELL26:OUT.BEST4.TMIN | PPC.C405PLBDCUBE4 |
| TCELL26:OUT.BEST5.TMIN | PPC.C405PLBDCUBE5 |
| TCELL26:OUT.BEST6.TMIN | PPC.C405PLBDCUBE6 |
| TCELL26:OUT.BEST7.TMIN | PPC.C405PLBDCUBE7 |
| TCELL26:OUT.SEC0.TMIN | PPC.C405PLBICUSIZE2 |
| TCELL26:OUT.SEC1.TMIN | PPC.C405PLBICUSIZE3 |
| TCELL26:OUT.SEC2.TMIN | PPC.C405PLBICUU0ATTR |
| TCELL26:OUT.SEC3.TMIN | PPC.C405TRCCYCLE |
| TCELL26:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO8 |
| TCELL26:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO9 |
| TCELL26:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO10 |
| TCELL26:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO11 |
| TCELL26:OUT.HALF.BOT4.TMIN | PPC.TSTISOCMC405READDATAOUTO12 |
| TCELL26:OUT.HALF.BOT5.TMIN | PPC.TSTISOCMC405READDATAOUTO13 |
| TCELL26:OUT.HALF.BOT6.TMIN | PPC.TSTISOCMC405READDATAOUTO14 |
| TCELL26:OUT.HALF.BOT7.TMIN | PPC.TSTISOCMC405READDATAOUTO15 |
| TCELL26:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO8 |
| TCELL26:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO9 |
| TCELL26:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO10 |
| TCELL26:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO11 |
| TCELL26:OUT.HALT.TOP4.TMIN | PPC.TSTISOCMC405READDATAOUTO12 |
| TCELL26:OUT.HALT.TOP5.TMIN | PPC.TSTISOCMC405READDATAOUTO13 |
| TCELL26:OUT.HALT.TOP6.TMIN | PPC.TSTISOCMC405READDATAOUTO14 |
| TCELL26:OUT.HALT.TOP7.TMIN | PPC.TSTISOCMC405READDATAOUTO15 |
| TCELL27:IMUX.SR0 | PPC.TIEAPUUDI719 |
| TCELL27:IMUX.SR1 | PPC.TIEAPUUDI718 |
| TCELL27:IMUX.SR2 | PPC.TIEAPUUDI717 |
| TCELL27:IMUX.SR3 | PPC.TIEAPUUDI716 |
| TCELL27:IMUX.CE0 | PPC.TIEAPUUDI723 |
| TCELL27:IMUX.CE1 | PPC.TIEAPUUDI722 |
| TCELL27:IMUX.CE2 | PPC.TIEAPUUDI721 |
| TCELL27:IMUX.CE3 | PPC.TIEAPUUDI720 |
| TCELL27:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS48 |
| TCELL27:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS49 |
| TCELL27:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS50 |
| TCELL27:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS51 |
| TCELL27:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS48 |
| TCELL27:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS49 |
| TCELL27:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS50 |
| TCELL27:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS51 |
| TCELL27:IMUX.IMUX8 | PPC.TSTC405DCRABUSI0 |
| TCELL27:IMUX.IMUX9 | PPC.TSTC405DCRABUSI1 |
| TCELL27:IMUX.IMUX10 | PPC.TSTC405DCRABUSI2 |
| TCELL27:IMUX.IMUX11 | PPC.TSTC405DCRABUSI3 |
| TCELL27:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI16 |
| TCELL27:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI17 |
| TCELL27:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI18 |
| TCELL27:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI19 |
| TCELL27:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI16 |
| TCELL27:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI17 |
| TCELL27:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI18 |
| TCELL27:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI19 |
| TCELL27:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS48 |
| TCELL27:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS49 |
| TCELL27:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS50 |
| TCELL27:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS51 |
| TCELL27:OUT.BEST4.TMIN | PPC.C405PLBICUREQUEST |
| TCELL27:OUT.BEST5.TMIN | PPC.C405PLBICUPRIORITY0 |
| TCELL27:OUT.BEST6.TMIN | PPC.C405PLBICUPRIORITY1 |
| TCELL27:OUT.BEST7.TMIN | PPC.C405PLBICUABORT |
| TCELL27:OUT.SEC0.TMIN | PPC.C405PLBDCUSIZE2 |
| TCELL27:OUT.SEC1.TMIN | PPC.C405PLBDCUU0ATTR |
| TCELL27:OUT.SEC2.TMIN | PPC.C405PLBDCUCACHEABLE |
| TCELL27:OUT.SEC3.TMIN | PPC.C405PLBICUCACHEABLE |
| TCELL27:OUT.HALF.BOT0.TMIN | PPC.TSTISOCMC405READDATAOUTO0 |
| TCELL27:OUT.HALF.BOT1.TMIN | PPC.TSTISOCMC405READDATAOUTO1 |
| TCELL27:OUT.HALF.BOT2.TMIN | PPC.TSTISOCMC405READDATAOUTO2 |
| TCELL27:OUT.HALF.BOT3.TMIN | PPC.TSTISOCMC405READDATAOUTO3 |
| TCELL27:OUT.HALF.BOT4.TMIN | PPC.TSTISOCMC405READDATAOUTO4 |
| TCELL27:OUT.HALF.BOT5.TMIN | PPC.TSTISOCMC405READDATAOUTO5 |
| TCELL27:OUT.HALF.BOT6.TMIN | PPC.TSTISOCMC405READDATAOUTO6 |
| TCELL27:OUT.HALF.BOT7.TMIN | PPC.TSTISOCMC405READDATAOUTO7 |
| TCELL27:OUT.HALT.TOP0.TMIN | PPC.TSTISOCMC405READDATAOUTO0 |
| TCELL27:OUT.HALT.TOP1.TMIN | PPC.TSTISOCMC405READDATAOUTO1 |
| TCELL27:OUT.HALT.TOP2.TMIN | PPC.TSTISOCMC405READDATAOUTO2 |
| TCELL27:OUT.HALT.TOP3.TMIN | PPC.TSTISOCMC405READDATAOUTO3 |
| TCELL27:OUT.HALT.TOP4.TMIN | PPC.TSTISOCMC405READDATAOUTO4 |
| TCELL27:OUT.HALT.TOP5.TMIN | PPC.TSTISOCMC405READDATAOUTO5 |
| TCELL27:OUT.HALT.TOP6.TMIN | PPC.TSTISOCMC405READDATAOUTO6 |
| TCELL27:OUT.HALT.TOP7.TMIN | PPC.TSTISOCMC405READDATAOUTO7 |
| TCELL28:IMUX.SR0 | PPC.TIEAPUUDI711 |
| TCELL28:IMUX.SR1 | PPC.TIEAPUUDI710 |
| TCELL28:IMUX.SR2 | PPC.TIEAPUUDI79 |
| TCELL28:IMUX.SR3 | PPC.TIEAPUUDI78 |
| TCELL28:IMUX.CE0 | PPC.TIEAPUUDI715 |
| TCELL28:IMUX.CE1 | PPC.TIEAPUUDI714 |
| TCELL28:IMUX.CE2 | PPC.TIEAPUUDI713 |
| TCELL28:IMUX.CE3 | PPC.TIEAPUUDI712 |
| TCELL28:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS44 |
| TCELL28:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS45 |
| TCELL28:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS46 |
| TCELL28:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS47 |
| TCELL28:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS44 |
| TCELL28:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS45 |
| TCELL28:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS46 |
| TCELL28:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS47 |
| TCELL28:IMUX.IMUX8 | PPC.TSTC405DCRABUSI4 |
| TCELL28:IMUX.IMUX9 | PPC.TSTC405DCRABUSI5 |
| TCELL28:IMUX.IMUX10 | PPC.TSTC405DCRABUSI6 |
| TCELL28:IMUX.IMUX11 | PPC.TSTC405DCRABUSI7 |
| TCELL28:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI12 |
| TCELL28:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI13 |
| TCELL28:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI14 |
| TCELL28:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI15 |
| TCELL28:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI12 |
| TCELL28:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI13 |
| TCELL28:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI14 |
| TCELL28:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI15 |
| TCELL28:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS44 |
| TCELL28:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS45 |
| TCELL28:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS46 |
| TCELL28:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS47 |
| TCELL28:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS28 |
| TCELL28:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS29 |
| TCELL28:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS30 |
| TCELL28:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS31 |
| TCELL28:OUT.SEC0.TMIN | PPC.C405PLBICUABUS28 |
| TCELL28:OUT.SEC1.TMIN | PPC.C405PLBICUABUS29 |
| TCELL28:OUT.SEC2.TMIN | PPC.TSTAPUC405EXEXEROVO |
| TCELL28:OUT.SEC3.TMIN | PPC.TSTAPUC405EXCEPTIONO |
| TCELL28:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405EXEBLOCKINGMCOO |
| TCELL28:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405EXENONBLOCKINGMCOO |
| TCELL28:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405EXEBUSYO |
| TCELL28:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405EXEXERCAO |
| TCELL28:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405DCDTRAPLEO |
| TCELL28:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXELDDEPENDO |
| TCELL28:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405WBLDDEPENDO |
| TCELL28:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405LWBLDDEPENDO |
| TCELL28:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405EXEBLOCKINGMCOO |
| TCELL28:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405EXENONBLOCKINGMCOO |
| TCELL28:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405EXEBUSYO |
| TCELL28:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405EXEXERCAO |
| TCELL28:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405DCDTRAPLEO |
| TCELL28:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXELDDEPENDO |
| TCELL28:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405WBLDDEPENDO |
| TCELL28:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405LWBLDDEPENDO |
| TCELL29:IMUX.SR0 | PPC.TIEAPUUDI73 |
| TCELL29:IMUX.SR1 | PPC.TIEAPUUDI72 |
| TCELL29:IMUX.SR2 | PPC.TIEAPUUDI71 |
| TCELL29:IMUX.SR3 | PPC.TIEAPUUDI70 |
| TCELL29:IMUX.CE0 | PPC.TIEAPUUDI77 |
| TCELL29:IMUX.CE1 | PPC.TIEAPUUDI76 |
| TCELL29:IMUX.CE2 | PPC.TIEAPUUDI75 |
| TCELL29:IMUX.CE3 | PPC.TIEAPUUDI74 |
| TCELL29:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS40 |
| TCELL29:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS41 |
| TCELL29:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS42 |
| TCELL29:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS43 |
| TCELL29:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS40 |
| TCELL29:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS41 |
| TCELL29:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS42 |
| TCELL29:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS43 |
| TCELL29:IMUX.IMUX8 | PPC.TSTC405DCRABUSI8 |
| TCELL29:IMUX.IMUX9 | PPC.TSTC405DCRABUSI9 |
| TCELL29:IMUX.IMUX10 | PPC.TSTC405DCRREADI |
| TCELL29:IMUX.IMUX11 | PPC.TSTC405DCRWRITEI |
| TCELL29:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI8 |
| TCELL29:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI9 |
| TCELL29:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI10 |
| TCELL29:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI11 |
| TCELL29:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI8 |
| TCELL29:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI9 |
| TCELL29:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI10 |
| TCELL29:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI11 |
| TCELL29:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS40 |
| TCELL29:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS41 |
| TCELL29:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS42 |
| TCELL29:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS43 |
| TCELL29:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS24 |
| TCELL29:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS25 |
| TCELL29:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS26 |
| TCELL29:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS27 |
| TCELL29:OUT.SEC0.TMIN | PPC.C405PLBICUABUS24 |
| TCELL29:OUT.SEC1.TMIN | PPC.C405PLBICUABUS25 |
| TCELL29:OUT.SEC2.TMIN | PPC.C405PLBICUABUS26 |
| TCELL29:OUT.SEC3.TMIN | PPC.C405PLBICUABUS27 |
| TCELL29:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405DCDLDSTWDO |
| TCELL29:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405DCDLDSTDWO |
| TCELL29:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405DCDLDSTQWO |
| TCELL29:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405DCDTRAPBEO |
| TCELL29:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405DCDCRENO |
| TCELL29:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405DCDUPDATEO |
| TCELL29:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405SLEEPREQO |
| TCELL29:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405DCDLDSTHWO |
| TCELL29:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405DCDLDSTWDO |
| TCELL29:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405DCDLDSTDWO |
| TCELL29:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405DCDLDSTQWO |
| TCELL29:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405DCDTRAPBEO |
| TCELL29:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405DCDCRENO |
| TCELL29:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405DCDUPDATEO |
| TCELL29:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405SLEEPREQO |
| TCELL29:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405DCDLDSTHWO |
| TCELL30:IMUX.SR0 | PPC.TIEAPUUDI619 |
| TCELL30:IMUX.SR1 | PPC.TIEAPUUDI618 |
| TCELL30:IMUX.SR2 | PPC.TIEAPUUDI617 |
| TCELL30:IMUX.SR3 | PPC.TIEAPUUDI616 |
| TCELL30:IMUX.CE0 | PPC.TIEAPUUDI623 |
| TCELL30:IMUX.CE1 | PPC.TIEAPUUDI622 |
| TCELL30:IMUX.CE2 | PPC.TIEAPUUDI621 |
| TCELL30:IMUX.CE3 | PPC.TIEAPUUDI620 |
| TCELL30:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS36 |
| TCELL30:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS37 |
| TCELL30:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS38 |
| TCELL30:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS39 |
| TCELL30:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS36 |
| TCELL30:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS37 |
| TCELL30:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS38 |
| TCELL30:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS39 |
| TCELL30:IMUX.IMUX8 | PPC.PLBC405ICURDWDADDR1 |
| TCELL30:IMUX.IMUX9 | PPC.PLBC405ICURDWDADDR2 |
| TCELL30:IMUX.IMUX10 | PPC.PLBC405ICURDWDADDR3 |
| TCELL30:IMUX.IMUX11 | PPC.PLBC405ICURDDACK |
| TCELL30:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI4 |
| TCELL30:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI5 |
| TCELL30:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI6 |
| TCELL30:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI7 |
| TCELL30:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI4 |
| TCELL30:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI5 |
| TCELL30:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI6 |
| TCELL30:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI7 |
| TCELL30:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS36 |
| TCELL30:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS37 |
| TCELL30:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS38 |
| TCELL30:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS39 |
| TCELL30:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS20 |
| TCELL30:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS21 |
| TCELL30:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS22 |
| TCELL30:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS23 |
| TCELL30:OUT.SEC0.TMIN | PPC.C405PLBICUABUS20 |
| TCELL30:OUT.SEC1.TMIN | PPC.C405PLBICUABUS21 |
| TCELL30:OUT.SEC2.TMIN | PPC.C405PLBICUABUS22 |
| TCELL30:OUT.SEC3.TMIN | PPC.C405PLBICUABUS23 |
| TCELL30:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405DCDSTOREO |
| TCELL30:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405DCDXERCAENO |
| TCELL30:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405DCDXEROVENO |
| TCELL30:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405DCDPRIVOPO |
| TCELL30:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXECRO0 |
| TCELL30:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXECRO1 |
| TCELL30:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXECRO2 |
| TCELL30:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405EXECRO3 |
| TCELL30:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405DCDSTOREO |
| TCELL30:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405DCDXERCAENO |
| TCELL30:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405DCDXEROVENO |
| TCELL30:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405DCDPRIVOPO |
| TCELL30:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXECRO0 |
| TCELL30:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXECRO1 |
| TCELL30:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXECRO2 |
| TCELL30:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405EXECRO3 |
| TCELL31:IMUX.SR0 | PPC.TIEAPUUDI611 |
| TCELL31:IMUX.SR1 | PPC.TIEAPUUDI610 |
| TCELL31:IMUX.SR2 | PPC.TIEAPUUDI69 |
| TCELL31:IMUX.SR3 | PPC.TIEAPUUDI68 |
| TCELL31:IMUX.CE0 | PPC.TIEAPUUDI615 |
| TCELL31:IMUX.CE1 | PPC.TIEAPUUDI614 |
| TCELL31:IMUX.CE2 | PPC.TIEAPUUDI613 |
| TCELL31:IMUX.CE3 | PPC.TIEAPUUDI612 |
| TCELL31:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS32 |
| TCELL31:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS33 |
| TCELL31:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS34 |
| TCELL31:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS35 |
| TCELL31:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS32 |
| TCELL31:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS33 |
| TCELL31:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS34 |
| TCELL31:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS35 |
| TCELL31:IMUX.IMUX8 | PPC.PLBC405ICUADDRACK |
| TCELL31:IMUX.IMUX9 | PPC.PLBC405ICUSSIZE1 |
| TCELL31:IMUX.IMUX10 | PPC.PLBC405ICUBUSY |
| TCELL31:IMUX.IMUX11 | PPC.PLBC405ICUERR |
| TCELL31:IMUX.IMUX12 | PPC.TSTC405APUEXELOADDBUSI0 |
| TCELL31:IMUX.IMUX13 | PPC.TSTC405APUEXELOADDBUSI1 |
| TCELL31:IMUX.IMUX14 | PPC.TSTC405APUEXELOADDBUSI2 |
| TCELL31:IMUX.IMUX15 | PPC.TSTC405APUEXELOADDBUSI3 |
| TCELL31:IMUX.IMUX16 | PPC.TSTC405APUEXERBDATAI0 |
| TCELL31:IMUX.IMUX17 | PPC.TSTC405APUEXERBDATAI1 |
| TCELL31:IMUX.IMUX18 | PPC.TSTC405APUEXERBDATAI2 |
| TCELL31:IMUX.IMUX19 | PPC.TSTC405APUEXERBDATAI3 |
| TCELL31:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS32 |
| TCELL31:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS33 |
| TCELL31:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS34 |
| TCELL31:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS35 |
| TCELL31:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS16 |
| TCELL31:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS17 |
| TCELL31:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS18 |
| TCELL31:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS19 |
| TCELL31:OUT.SEC0.TMIN | PPC.C405PLBICUABUS16 |
| TCELL31:OUT.SEC1.TMIN | PPC.C405PLBICUABUS17 |
| TCELL31:OUT.SEC2.TMIN | PPC.C405PLBICUABUS18 |
| TCELL31:OUT.SEC3.TMIN | PPC.C405PLBICUABUS19 |
| TCELL31:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405DCDGPRWRITEO |
| TCELL31:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405DCDRAENO |
| TCELL31:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405DCDRBENO |
| TCELL31:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405DCDLOADO |
| TCELL31:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXECRFIELDO0 |
| TCELL31:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXECRFIELDO1 |
| TCELL31:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXECRFIELDO2 |
| TCELL31:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405DCDFPUOPO |
| TCELL31:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405DCDGPRWRITEO |
| TCELL31:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405DCDRAENO |
| TCELL31:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405DCDRBENO |
| TCELL31:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405DCDLOADO |
| TCELL31:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXECRFIELDO0 |
| TCELL31:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXECRFIELDO1 |
| TCELL31:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXECRFIELDO2 |
| TCELL31:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405DCDFPUOPO |
| TCELL32:IMUX.SR0 | PPC.TIEAPUUDI63 |
| TCELL32:IMUX.SR1 | PPC.TIEAPUUDI62 |
| TCELL32:IMUX.SR2 | PPC.TIEAPUUDI61 |
| TCELL32:IMUX.SR3 | PPC.TIEAPUUDI60 |
| TCELL32:IMUX.CE0 | PPC.TIEAPUUDI67 |
| TCELL32:IMUX.CE1 | PPC.TIEAPUUDI66 |
| TCELL32:IMUX.CE2 | PPC.TIEAPUUDI65 |
| TCELL32:IMUX.CE3 | PPC.TIEAPUUDI64 |
| TCELL32:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS28 |
| TCELL32:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS29 |
| TCELL32:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS30 |
| TCELL32:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS31 |
| TCELL32:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS28 |
| TCELL32:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS29 |
| TCELL32:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS30 |
| TCELL32:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS31 |
| TCELL32:IMUX.IMUX8 | PPC.PLBC405DCUADDRACK |
| TCELL32:IMUX.IMUX9 | PPC.PLBC405DCUSSIZE1 |
| TCELL32:IMUX.IMUX10 | PPC.PLBC405DCUBUSY |
| TCELL32:IMUX.IMUX11 | PPC.PLBC405DCUERR |
| TCELL32:IMUX.IMUX12 | PPC.TSTC405APUDCDINSTRUCTIONI28 |
| TCELL32:IMUX.IMUX13 | PPC.TSTC405APUDCDINSTRUCTIONI29 |
| TCELL32:IMUX.IMUX14 | PPC.TSTC405APUDCDINSTRUCTIONI30 |
| TCELL32:IMUX.IMUX15 | PPC.TSTC405APUDCDINSTRUCTIONI31 |
| TCELL32:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI28 |
| TCELL32:IMUX.IMUX17 | PPC.TSTC405APUEXERADATAI29 |
| TCELL32:IMUX.IMUX18 | PPC.TSTC405APUEXERADATAI30 |
| TCELL32:IMUX.IMUX19 | PPC.TSTC405APUEXERADATAI31 |
| TCELL32:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS28 |
| TCELL32:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS29 |
| TCELL32:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS30 |
| TCELL32:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS31 |
| TCELL32:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS12 |
| TCELL32:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS13 |
| TCELL32:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS14 |
| TCELL32:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS15 |
| TCELL32:OUT.SEC0.TMIN | PPC.C405PLBICUABUS12 |
| TCELL32:OUT.SEC1.TMIN | PPC.C405PLBICUABUS13 |
| TCELL32:OUT.SEC2.TMIN | PPC.C405PLBICUABUS14 |
| TCELL32:OUT.SEC3.TMIN | PPC.C405PLBICUABUS15 |
| TCELL32:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405EXERESULTO24 |
| TCELL32:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405EXERESULTO25 |
| TCELL32:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405EXERESULTO26 |
| TCELL32:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405EXERESULTO27 |
| TCELL32:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXERESULTO28 |
| TCELL32:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXERESULTO29 |
| TCELL32:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXERESULTO30 |
| TCELL32:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405EXERESULTO31 |
| TCELL32:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405EXERESULTO24 |
| TCELL32:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405EXERESULTO25 |
| TCELL32:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405EXERESULTO26 |
| TCELL32:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405EXERESULTO27 |
| TCELL32:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXERESULTO28 |
| TCELL32:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXERESULTO29 |
| TCELL32:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXERESULTO30 |
| TCELL32:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405EXERESULTO31 |
| TCELL33:IMUX.SR0 | PPC.TIEAPUUDI519 |
| TCELL33:IMUX.SR1 | PPC.TIEAPUUDI518 |
| TCELL33:IMUX.SR2 | PPC.TIEAPUUDI517 |
| TCELL33:IMUX.SR3 | PPC.TIEAPUUDI516 |
| TCELL33:IMUX.CE0 | PPC.TIEAPUUDI523 |
| TCELL33:IMUX.CE1 | PPC.TIEAPUUDI522 |
| TCELL33:IMUX.CE2 | PPC.TIEAPUUDI521 |
| TCELL33:IMUX.CE3 | PPC.TIEAPUUDI520 |
| TCELL33:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS24 |
| TCELL33:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS25 |
| TCELL33:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS26 |
| TCELL33:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS27 |
| TCELL33:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS24 |
| TCELL33:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS25 |
| TCELL33:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS26 |
| TCELL33:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS27 |
| TCELL33:IMUX.IMUX8 | PPC.PLBC405DCURDWDADDR1 |
| TCELL33:IMUX.IMUX9 | PPC.PLBC405DCURDWDADDR2 |
| TCELL33:IMUX.IMUX10 | PPC.PLBC405DCURDWDADDR3 |
| TCELL33:IMUX.IMUX11 | PPC.PLBC405DCURDDACK |
| TCELL33:IMUX.IMUX12 | PPC.TSTC405APUDCDINSTRUCTIONI24 |
| TCELL33:IMUX.IMUX13 | PPC.TSTC405APUDCDINSTRUCTIONI25 |
| TCELL33:IMUX.IMUX14 | PPC.TSTC405APUDCDINSTRUCTIONI26 |
| TCELL33:IMUX.IMUX15 | PPC.TSTC405APUDCDINSTRUCTIONI27 |
| TCELL33:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI24 |
| TCELL33:IMUX.IMUX17 | PPC.TSTC405APUEXERADATAI25 |
| TCELL33:IMUX.IMUX18 | PPC.TSTC405APUEXERADATAI26 |
| TCELL33:IMUX.IMUX19 | PPC.TSTC405APUEXERADATAI27 |
| TCELL33:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS24 |
| TCELL33:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS25 |
| TCELL33:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS26 |
| TCELL33:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS27 |
| TCELL33:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS8 |
| TCELL33:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS9 |
| TCELL33:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS10 |
| TCELL33:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS11 |
| TCELL33:OUT.SEC0.TMIN | PPC.C405PLBICUABUS8 |
| TCELL33:OUT.SEC1.TMIN | PPC.C405PLBICUABUS9 |
| TCELL33:OUT.SEC2.TMIN | PPC.C405PLBICUABUS10 |
| TCELL33:OUT.SEC3.TMIN | PPC.C405PLBICUABUS11 |
| TCELL33:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405EXERESULTO16 |
| TCELL33:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405EXERESULTO17 |
| TCELL33:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405EXERESULTO18 |
| TCELL33:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405EXERESULTO19 |
| TCELL33:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXERESULTO20 |
| TCELL33:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXERESULTO21 |
| TCELL33:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXERESULTO22 |
| TCELL33:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405EXERESULTO23 |
| TCELL33:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405EXERESULTO16 |
| TCELL33:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405EXERESULTO17 |
| TCELL33:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405EXERESULTO18 |
| TCELL33:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405EXERESULTO19 |
| TCELL33:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXERESULTO20 |
| TCELL33:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXERESULTO21 |
| TCELL33:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXERESULTO22 |
| TCELL33:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405EXERESULTO23 |
| TCELL34:IMUX.SR0 | PPC.TIEAPUUDI511 |
| TCELL34:IMUX.SR1 | PPC.TIEAPUUDI510 |
| TCELL34:IMUX.SR2 | PPC.TIEAPUUDI59 |
| TCELL34:IMUX.SR3 | PPC.TIEAPUUDI58 |
| TCELL34:IMUX.CE0 | PPC.TIEAPUUDI515 |
| TCELL34:IMUX.CE1 | PPC.TIEAPUUDI514 |
| TCELL34:IMUX.CE2 | PPC.TIEAPUUDI513 |
| TCELL34:IMUX.CE3 | PPC.TIEAPUUDI512 |
| TCELL34:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS20 |
| TCELL34:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS21 |
| TCELL34:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS22 |
| TCELL34:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS23 |
| TCELL34:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS20 |
| TCELL34:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS21 |
| TCELL34:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS22 |
| TCELL34:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS23 |
| TCELL34:IMUX.IMUX8 | PPC.PLBC405DCUWRDACK |
| TCELL34:IMUX.IMUX9 | PPC.TSTC405APUDCDINSTRUCTIONI20 |
| TCELL34:IMUX.IMUX10 | PPC.TSTC405APUDCDINSTRUCTIONI21 |
| TCELL34:IMUX.IMUX11 | PPC.TSTC405APUDCDINSTRUCTIONI22 |
| TCELL34:IMUX.IMUX12 | PPC.TSTC405APUDCDINSTRUCTIONI23 |
| TCELL34:IMUX.IMUX13 | PPC.TSTC405APUEXERADATAI20 |
| TCELL34:IMUX.IMUX14 | PPC.TSTC405APUEXERADATAI21 |
| TCELL34:IMUX.IMUX15 | PPC.TSTC405APUEXERADATAI22 |
| TCELL34:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI23 |
| TCELL34:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS20 |
| TCELL34:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS21 |
| TCELL34:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS22 |
| TCELL34:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS23 |
| TCELL34:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS4 |
| TCELL34:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS5 |
| TCELL34:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS6 |
| TCELL34:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS7 |
| TCELL34:OUT.SEC0.TMIN | PPC.C405PLBICUABUS4 |
| TCELL34:OUT.SEC1.TMIN | PPC.C405PLBICUABUS5 |
| TCELL34:OUT.SEC2.TMIN | PPC.C405PLBICUABUS6 |
| TCELL34:OUT.SEC3.TMIN | PPC.C405PLBICUABUS7 |
| TCELL34:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405EXERESULTO8 |
| TCELL34:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405EXERESULTO9 |
| TCELL34:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405EXERESULTO10 |
| TCELL34:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405EXERESULTO11 |
| TCELL34:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXERESULTO12 |
| TCELL34:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXERESULTO13 |
| TCELL34:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXERESULTO14 |
| TCELL34:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405EXERESULTO15 |
| TCELL34:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405EXERESULTO8 |
| TCELL34:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405EXERESULTO9 |
| TCELL34:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405EXERESULTO10 |
| TCELL34:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405EXERESULTO11 |
| TCELL34:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXERESULTO12 |
| TCELL34:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXERESULTO13 |
| TCELL34:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXERESULTO14 |
| TCELL34:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405EXERESULTO15 |
| TCELL35:IMUX.SR0 | PPC.TIEAPUUDI53 |
| TCELL35:IMUX.SR1 | PPC.TIEAPUUDI52 |
| TCELL35:IMUX.SR2 | PPC.TIEAPUUDI51 |
| TCELL35:IMUX.SR3 | PPC.TIEAPUUDI50 |
| TCELL35:IMUX.CE0 | PPC.TIEAPUUDI57 |
| TCELL35:IMUX.CE1 | PPC.TIEAPUUDI56 |
| TCELL35:IMUX.CE2 | PPC.TIEAPUUDI55 |
| TCELL35:IMUX.CE3 | PPC.TIEAPUUDI54 |
| TCELL35:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS16 |
| TCELL35:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS17 |
| TCELL35:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS18 |
| TCELL35:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS19 |
| TCELL35:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS16 |
| TCELL35:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS17 |
| TCELL35:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS18 |
| TCELL35:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS19 |
| TCELL35:IMUX.IMUX8 | PPC.TSTC405APUDCDINSTRUCTIONI16 |
| TCELL35:IMUX.IMUX9 | PPC.TSTC405APUDCDINSTRUCTIONI17 |
| TCELL35:IMUX.IMUX10 | PPC.TSTC405APUDCDINSTRUCTIONI18 |
| TCELL35:IMUX.IMUX11 | PPC.TSTC405APUDCDINSTRUCTIONI19 |
| TCELL35:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI28 |
| TCELL35:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI29 |
| TCELL35:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI30 |
| TCELL35:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI31 |
| TCELL35:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI16 |
| TCELL35:IMUX.IMUX17 | PPC.TSTC405APUEXERADATAI17 |
| TCELL35:IMUX.IMUX18 | PPC.TSTC405APUEXERADATAI18 |
| TCELL35:IMUX.IMUX19 | PPC.TSTC405APUEXERADATAI19 |
| TCELL35:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS16 |
| TCELL35:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS17 |
| TCELL35:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS18 |
| TCELL35:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS19 |
| TCELL35:OUT.BEST4.TMIN | PPC.C405PLBDCUABUS0 |
| TCELL35:OUT.BEST5.TMIN | PPC.C405PLBDCUABUS1 |
| TCELL35:OUT.BEST6.TMIN | PPC.C405PLBDCUABUS2 |
| TCELL35:OUT.BEST7.TMIN | PPC.C405PLBDCUABUS3 |
| TCELL35:OUT.SEC0.TMIN | PPC.C405PLBICUABUS0 |
| TCELL35:OUT.SEC1.TMIN | PPC.C405PLBICUABUS1 |
| TCELL35:OUT.SEC2.TMIN | PPC.C405PLBICUABUS2 |
| TCELL35:OUT.SEC3.TMIN | PPC.C405PLBICUABUS3 |
| TCELL35:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405EXERESULTO0 |
| TCELL35:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405EXERESULTO1 |
| TCELL35:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405EXERESULTO2 |
| TCELL35:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405EXERESULTO3 |
| TCELL35:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405EXERESULTO4 |
| TCELL35:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405EXERESULTO5 |
| TCELL35:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405EXERESULTO6 |
| TCELL35:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405EXERESULTO7 |
| TCELL35:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405EXERESULTO0 |
| TCELL35:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405EXERESULTO1 |
| TCELL35:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405EXERESULTO2 |
| TCELL35:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405EXERESULTO3 |
| TCELL35:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405EXERESULTO4 |
| TCELL35:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405EXERESULTO5 |
| TCELL35:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405EXERESULTO6 |
| TCELL35:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405EXERESULTO7 |
| TCELL36:IMUX.SR0 | PPC.TIEAPUUDI419 |
| TCELL36:IMUX.SR1 | PPC.TIEAPUUDI418 |
| TCELL36:IMUX.SR2 | PPC.TIEAPUUDI417 |
| TCELL36:IMUX.SR3 | PPC.TIEAPUUDI416 |
| TCELL36:IMUX.CE0 | PPC.TIEAPUUDI423 |
| TCELL36:IMUX.CE1 | PPC.TIEAPUUDI422 |
| TCELL36:IMUX.CE2 | PPC.TIEAPUUDI421 |
| TCELL36:IMUX.CE3 | PPC.TIEAPUUDI420 |
| TCELL36:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS12 |
| TCELL36:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS13 |
| TCELL36:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS14 |
| TCELL36:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS15 |
| TCELL36:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS12 |
| TCELL36:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS13 |
| TCELL36:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS14 |
| TCELL36:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS15 |
| TCELL36:IMUX.IMUX8 | PPC.TSTC405APUDCDINSTRUCTIONI12 |
| TCELL36:IMUX.IMUX9 | PPC.TSTC405APUDCDINSTRUCTIONI13 |
| TCELL36:IMUX.IMUX10 | PPC.TSTC405APUDCDINSTRUCTIONI14 |
| TCELL36:IMUX.IMUX11 | PPC.TSTC405APUDCDINSTRUCTIONI15 |
| TCELL36:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI24 |
| TCELL36:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI25 |
| TCELL36:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI26 |
| TCELL36:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI27 |
| TCELL36:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI12 |
| TCELL36:IMUX.IMUX17 | PPC.TSTC405APUEXERADATAI13 |
| TCELL36:IMUX.IMUX18 | PPC.TSTC405APUEXERADATAI14 |
| TCELL36:IMUX.IMUX19 | PPC.TSTC405APUEXERADATAI15 |
| TCELL36:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS12 |
| TCELL36:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS13 |
| TCELL36:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS14 |
| TCELL36:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS15 |
| TCELL36:OUT.BEST4.TMIN | PPC.C405PLBDCUBE0 |
| TCELL36:OUT.BEST5.TMIN | PPC.C405PLBDCUBE1 |
| TCELL36:OUT.BEST6.TMIN | PPC.C405PLBDCUBE2 |
| TCELL36:OUT.BEST7.TMIN | PPC.C405PLBDCUBE3 |
| TCELL36:OUT.SEC0.TMIN | PPC.TSTC405APUWBENDIANO |
| TCELL36:OUT.SEC1.TMIN | PPC.TSTC405APUEXELOADDVALIDO |
| TCELL36:OUT.SEC2.TMIN | PPC.TSTC405APUEXEFLUSHO |
| TCELL36:OUT.SEC3.TMIN | PPC.C405CPMCLOCKFB |
| TCELL36:OUT.HALF.BOT0.TMIN | PPC.TSTAPUC405FPUEXCEPTIONO |
| TCELL36:OUT.HALF.BOT1.TMIN | PPC.TSTAPUC405DCDVALIDOPO |
| TCELL36:OUT.HALF.BOT2.TMIN | PPC.TSTAPUC405APUDIVENO |
| TCELL36:OUT.HALF.BOT3.TMIN | PPC.TSTAPUC405APUPRESENTO |
| TCELL36:OUT.HALF.BOT4.TMIN | PPC.TSTAPUC405DCDAPUOPO |
| TCELL36:OUT.HALF.BOT5.TMIN | PPC.TSTAPUC405DCDFORCEALIGNO |
| TCELL36:OUT.HALF.BOT6.TMIN | PPC.TSTAPUC405DCDFORCEBESTEERINGO |
| TCELL36:OUT.HALF.BOT7.TMIN | PPC.TSTAPUC405DCDLDSTBYTEO |
| TCELL36:OUT.HALT.TOP0.TMIN | PPC.TSTAPUC405FPUEXCEPTIONO |
| TCELL36:OUT.HALT.TOP1.TMIN | PPC.TSTAPUC405DCDVALIDOPO |
| TCELL36:OUT.HALT.TOP2.TMIN | PPC.TSTAPUC405APUDIVENO |
| TCELL36:OUT.HALT.TOP3.TMIN | PPC.TSTAPUC405APUPRESENTO |
| TCELL36:OUT.HALT.TOP4.TMIN | PPC.TSTAPUC405DCDAPUOPO |
| TCELL36:OUT.HALT.TOP5.TMIN | PPC.TSTAPUC405DCDFORCEALIGNO |
| TCELL36:OUT.HALT.TOP6.TMIN | PPC.TSTAPUC405DCDFORCEBESTEERINGO |
| TCELL36:OUT.HALT.TOP7.TMIN | PPC.TSTAPUC405DCDLDSTBYTEO |
| TCELL37:IMUX.SR0 | PPC.TIEAPUUDI411 |
| TCELL37:IMUX.SR1 | PPC.TIEAPUUDI410 |
| TCELL37:IMUX.SR2 | PPC.TIEAPUUDI49 |
| TCELL37:IMUX.SR3 | PPC.TIEAPUUDI48 |
| TCELL37:IMUX.CE0 | PPC.TIEAPUUDI415 |
| TCELL37:IMUX.CE1 | PPC.TIEAPUUDI414 |
| TCELL37:IMUX.CE2 | PPC.TIEAPUUDI413 |
| TCELL37:IMUX.CE3 | PPC.TIEAPUUDI412 |
| TCELL37:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS8 |
| TCELL37:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS9 |
| TCELL37:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS10 |
| TCELL37:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS11 |
| TCELL37:IMUX.IMUX4 | PPC.PLBC405ICURDDBUS8 |
| TCELL37:IMUX.IMUX5 | PPC.PLBC405ICURDDBUS9 |
| TCELL37:IMUX.IMUX6 | PPC.PLBC405ICURDDBUS10 |
| TCELL37:IMUX.IMUX7 | PPC.PLBC405ICURDDBUS11 |
| TCELL37:IMUX.IMUX8 | PPC.TSTC405APUDCDINSTRUCTIONI4 |
| TCELL37:IMUX.IMUX9 | PPC.TSTC405APUDCDINSTRUCTIONI5 |
| TCELL37:IMUX.IMUX10 | PPC.TSTC405APUDCDINSTRUCTIONI6 |
| TCELL37:IMUX.IMUX11 | PPC.TSTC405APUDCDINSTRUCTIONI7 |
| TCELL37:IMUX.IMUX12 | PPC.TSTC405APUDCDINSTRUCTIONI8 |
| TCELL37:IMUX.IMUX13 | PPC.TSTC405APUDCDINSTRUCTIONI9 |
| TCELL37:IMUX.IMUX14 | PPC.TSTC405APUDCDINSTRUCTIONI10 |
| TCELL37:IMUX.IMUX15 | PPC.TSTC405APUDCDINSTRUCTIONI11 |
| TCELL37:IMUX.IMUX16 | PPC.TSTC405APUEXERADATAI8 |
| TCELL37:IMUX.IMUX17 | PPC.TSTC405APUEXERADATAI9 |
| TCELL37:IMUX.IMUX18 | PPC.TSTC405APUEXERADATAI10 |
| TCELL37:IMUX.IMUX19 | PPC.TSTC405APUEXERADATAI11 |
| TCELL37:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS8 |
| TCELL37:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS9 |
| TCELL37:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS10 |
| TCELL37:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS11 |
| TCELL37:OUT.BEST4.TMIN | PPC.C405PLBDCUGUARDED |
| TCELL37:OUT.BEST5.TMIN | PPC.C405PLBDCUWRITETHRU |
| TCELL37:OUT.BEST6.TMIN | PPC.C405PLBDCURNW |
| TCELL37:OUT.BEST7.TMIN | PPC.APUFCMOPERANDVALID |
| TCELL37:OUT.SEC0.TMIN | PPC.APUFCMLOADDVALID |
| TCELL37:OUT.SEC1.TMIN | PPC.APUFCMDECUDI0 |
| TCELL37:OUT.SEC2.TMIN | PPC.APUFCMDECUDI1 |
| TCELL37:OUT.SEC3.TMIN | PPC.APUFCMDECUDI2 |
| TCELL37:OUT.HALF.BOT0.TMIN | EMAC.TSTSOEMACO4 |
| TCELL37:OUT.HALF.BOT1.TMIN | EMAC.TSTSOEMACO5 |
| TCELL37:OUT.HALF.BOT2.TMIN | EMAC.TSTSOEMACO6 |
| TCELL37:OUT.HALF.BOT3.TMIN | PPC.TSTSOGASKETO0 |
| TCELL37:OUT.HALF.BOT4.TMIN | PPC.TSTSOGASKETO1 |
| TCELL37:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXEHOLDO |
| TCELL37:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDHOLDO |
| TCELL37:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUXERCAO |
| TCELL37:OUT.HALT.TOP0.TMIN | EMAC.TSTSOEMACO4 |
| TCELL37:OUT.HALT.TOP1.TMIN | EMAC.TSTSOEMACO5 |
| TCELL37:OUT.HALT.TOP2.TMIN | EMAC.TSTSOEMACO6 |
| TCELL37:OUT.HALT.TOP3.TMIN | PPC.TSTSOGASKETO0 |
| TCELL37:OUT.HALT.TOP4.TMIN | PPC.TSTSOGASKETO1 |
| TCELL37:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXEHOLDO |
| TCELL37:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDHOLDO |
| TCELL37:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUXERCAO |
| TCELL38:IMUX.SR0 | PPC.TIEAPUUDI43 |
| TCELL38:IMUX.SR1 | PPC.TIEAPUUDI42 |
| TCELL38:IMUX.SR2 | PPC.TIEAPUUDI41 |
| TCELL38:IMUX.SR3 | PPC.TIEAPUUDI40 |
| TCELL38:IMUX.CE0 | PPC.TIEAPUUDI47 |
| TCELL38:IMUX.CE1 | PPC.TIEAPUUDI46 |
| TCELL38:IMUX.CE2 | PPC.TIEAPUUDI45 |
| TCELL38:IMUX.CE3 | PPC.TIEAPUUDI44 |
| TCELL38:IMUX.IMUX0 | PPC.PLBC405ICURDDBUS4 |
| TCELL38:IMUX.IMUX1 | PPC.PLBC405ICURDDBUS5 |
| TCELL38:IMUX.IMUX2 | PPC.PLBC405ICURDDBUS6 |
| TCELL38:IMUX.IMUX3 | PPC.PLBC405ICURDDBUS7 |
| TCELL38:IMUX.IMUX4 | PPC.FCMAPUDECODEBUSY |
| TCELL38:IMUX.IMUX5 | PPC.TSTC405APUEXERADATAI0 |
| TCELL38:IMUX.IMUX6 | PPC.TSTC405APUEXERADATAI1 |
| TCELL38:IMUX.IMUX7 | PPC.TSTC405APUEXERADATAI2 |
| TCELL38:IMUX.IMUX8 | PPC.TSTC405APUEXERADATAI3 |
| TCELL38:IMUX.IMUX9 | PPC.TSTC405APUEXERADATAI4 |
| TCELL38:IMUX.IMUX10 | PPC.TSTC405APUEXERADATAI5 |
| TCELL38:IMUX.IMUX11 | PPC.TSTC405APUEXERADATAI6 |
| TCELL38:IMUX.IMUX12 | PPC.TSTC405APUEXERADATAI7 |
| TCELL38:IMUX.IMUX13 | PPC.TSTC405APUDCDINSTRUCTIONI0 |
| TCELL38:IMUX.IMUX14 | PPC.TSTC405APUDCDINSTRUCTIONI1 |
| TCELL38:IMUX.IMUX15 | PPC.TSTC405APUDCDINSTRUCTIONI2 |
| TCELL38:IMUX.IMUX16 | PPC.TSTC405APUDCDINSTRUCTIONI3 |
| TCELL38:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS4 |
| TCELL38:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS5 |
| TCELL38:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS6 |
| TCELL38:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS7 |
| TCELL38:OUT.BEST4.TMIN | PPC.APUFCMFLUSH |
| TCELL38:OUT.BEST5.TMIN | PPC.APUFCMWRITEBACKOK |
| TCELL38:OUT.BEST6.TMIN | PPC.APUFCMENDIAN |
| TCELL38:OUT.BEST7.TMIN | PPC.APUFCMXERCA |
| TCELL38:OUT.SEC0.TMIN | PPC.DSOCMBUSY |
| TCELL38:OUT.SEC1.TMIN | PPC.APUFCMINSTRVALID |
| TCELL38:OUT.SEC2.TMIN | PPC.APUFCMDECODED |
| TCELL38:OUT.SEC3.TMIN | PPC.APUFCMDECUDIVALID |
| TCELL38:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO28 |
| TCELL38:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO29 |
| TCELL38:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO30 |
| TCELL38:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO31 |
| TCELL38:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO28 |
| TCELL38:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO29 |
| TCELL38:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO30 |
| TCELL38:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO31 |
| TCELL38:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO28 |
| TCELL38:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO29 |
| TCELL38:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO30 |
| TCELL38:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO31 |
| TCELL38:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO28 |
| TCELL38:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO29 |
| TCELL38:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO30 |
| TCELL38:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO31 |
| TCELL39:IMUX.SR0 | PPC.TIEAPUUDI319 |
| TCELL39:IMUX.SR1 | PPC.TIEAPUUDI318 |
| TCELL39:IMUX.SR2 | PPC.TIEAPUUDI317 |
| TCELL39:IMUX.SR3 | PPC.TIEAPUUDI316 |
| TCELL39:IMUX.CE0 | PPC.TIEAPUUDI323 |
| TCELL39:IMUX.CE1 | PPC.TIEAPUUDI322 |
| TCELL39:IMUX.CE2 | PPC.TIEAPUUDI321 |
| TCELL39:IMUX.CE3 | PPC.TIEAPUUDI320 |
| TCELL39:IMUX.IMUX0 | PPC.PLBC405DCURDDBUS4 |
| TCELL39:IMUX.IMUX1 | PPC.PLBC405DCURDDBUS5 |
| TCELL39:IMUX.IMUX2 | PPC.PLBC405DCURDDBUS6 |
| TCELL39:IMUX.IMUX3 | PPC.PLBC405DCURDDBUS7 |
| TCELL39:IMUX.IMUX4 | PPC.FCMAPUEXCEPTION |
| TCELL39:IMUX.IMUX5 | PPC.FCMAPUXERCA |
| TCELL39:IMUX.IMUX6 | PPC.FCMAPUXEROV |
| TCELL39:IMUX.IMUX7 | PPC.FCMAPUSLEEPNOTREADY |
| TCELL39:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI28 |
| TCELL39:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI29 |
| TCELL39:IMUX.IMUX10 | PPC.TSTC405DSOCMBYTEENI0 |
| TCELL39:IMUX.IMUX11 | PPC.TSTC405DSOCMBYTEENI1 |
| TCELL39:IMUX.IMUX12 | PPC.TSTC405DSOCMBYTEENI2 |
| TCELL39:IMUX.IMUX13 | PPC.TSTC405DSOCMBYTEENI3 |
| TCELL39:IMUX.IMUX14 | PPC.TSTC405DSOCMABORTREQI |
| TCELL39:IMUX.IMUX15 | PPC.TSTC405DSOCMABORTOPI |
| TCELL39:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI28 |
| TCELL39:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI29 |
| TCELL39:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI30 |
| TCELL39:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI31 |
| TCELL39:OUT.BEST0.TMIN | PPC.C405PLBDCUWRDBUS0 |
| TCELL39:OUT.BEST1.TMIN | PPC.C405PLBDCUWRDBUS1 |
| TCELL39:OUT.BEST2.TMIN | PPC.C405PLBDCUWRDBUS2 |
| TCELL39:OUT.BEST3.TMIN | PPC.C405PLBDCUWRDBUS3 |
| TCELL39:OUT.BEST4.TMIN | PPC.C405PLBDCUREQUEST |
| TCELL39:OUT.BEST5.TMIN | PPC.C405PLBDCUPRIORITY0 |
| TCELL39:OUT.BEST6.TMIN | PPC.C405PLBDCUPRIORITY1 |
| TCELL39:OUT.BEST7.TMIN | PPC.C405PLBDCUABORT |
| TCELL39:OUT.SEC0.TMIN | PPC.APUFCMLOADBYTEEN0 |
| TCELL39:OUT.SEC1.TMIN | PPC.APUFCMLOADBYTEEN1 |
| TCELL39:OUT.SEC2.TMIN | PPC.APUFCMLOADBYTEEN2 |
| TCELL39:OUT.SEC3.TMIN | PPC.APUFCMLOADBYTEEN3 |
| TCELL39:OUT.HALF.BOT0.TMIN | PPC.TSTDSOCMC405COMPLETEO |
| TCELL39:OUT.HALF.BOT1.TMIN | PPC.TSTDSOCMC405DISOPERANDFWDO |
| TCELL39:OUT.HALF.BOT2.TMIN | PPC.TSTDSOCMC405HOLDO |
| TCELL39:OUT.HALF.BOT3.TMIN | PPC.TSTDCRC405ACKO |
| TCELL39:OUT.HALF.BOT4.TMIN | PPC.TSTRESETCOREO |
| TCELL39:OUT.HALF.BOT5.TMIN | PPC.TSTRESETCHIPO |
| TCELL39:OUT.HALF.BOT6.TMIN | PPC.TSTRESETSYSO |
| TCELL39:OUT.HALF.BOT7.TMIN | PPC.TSTTRSTNEGO |
| TCELL39:OUT.HALT.TOP0.TMIN | PPC.TSTDSOCMC405COMPLETEO |
| TCELL39:OUT.HALT.TOP1.TMIN | PPC.TSTDSOCMC405DISOPERANDFWDO |
| TCELL39:OUT.HALT.TOP2.TMIN | PPC.TSTDSOCMC405HOLDO |
| TCELL39:OUT.HALT.TOP3.TMIN | PPC.TSTDCRC405ACKO |
| TCELL39:OUT.HALT.TOP4.TMIN | PPC.TSTRESETCOREO |
| TCELL39:OUT.HALT.TOP5.TMIN | PPC.TSTRESETCHIPO |
| TCELL39:OUT.HALT.TOP6.TMIN | PPC.TSTRESETSYSO |
| TCELL39:OUT.HALT.TOP7.TMIN | PPC.TSTTRSTNEGO |
| TCELL40:IMUX.SR0 | PPC.TIEAPUUDI311 |
| TCELL40:IMUX.SR1 | PPC.TIEAPUUDI310 |
| TCELL40:IMUX.SR2 | PPC.TIEAPUUDI39 |
| TCELL40:IMUX.SR3 | PPC.TIEAPUUDI38 |
| TCELL40:IMUX.CE0 | PPC.TIEAPUUDI315 |
| TCELL40:IMUX.CE1 | PPC.TIEAPUUDI314 |
| TCELL40:IMUX.CE2 | PPC.TIEAPUUDI313 |
| TCELL40:IMUX.CE3 | PPC.TIEAPUUDI312 |
| TCELL40:IMUX.IMUX0 | PPC.FCMAPURESULT28 |
| TCELL40:IMUX.IMUX1 | PPC.FCMAPURESULT29 |
| TCELL40:IMUX.IMUX2 | PPC.FCMAPURESULT30 |
| TCELL40:IMUX.IMUX3 | PPC.FCMAPURESULT31 |
| TCELL40:IMUX.IMUX4 | PPC.FCMAPUCR0 |
| TCELL40:IMUX.IMUX5 | PPC.FCMAPUCR1 |
| TCELL40:IMUX.IMUX6 | PPC.FCMAPUCR2 |
| TCELL40:IMUX.IMUX7 | PPC.FCMAPUCR3 |
| TCELL40:IMUX.IMUX8 | PPC.FCMAPURESULTVALID |
| TCELL40:IMUX.IMUX9 | PPC.FCMAPUINSTRACK |
| TCELL40:IMUX.IMUX10 | PPC.FCMAPUDCDFPUOP |
| TCELL40:IMUX.IMUX11 | PPC.FCMAPUDONE |
| TCELL40:IMUX.IMUX12 | PPC.PLBC405ICURDDBUS0 |
| TCELL40:IMUX.IMUX13 | PPC.PLBC405ICURDDBUS1 |
| TCELL40:IMUX.IMUX14 | PPC.PLBC405ICURDDBUS2 |
| TCELL40:IMUX.IMUX15 | PPC.PLBC405ICURDDBUS3 |
| TCELL40:IMUX.IMUX16 | PPC.TSTC405DCRDBUSOUTI20 |
| TCELL40:IMUX.IMUX17 | PPC.TSTC405DCRDBUSOUTI21 |
| TCELL40:IMUX.IMUX18 | PPC.TSTC405DCRDBUSOUTI22 |
| TCELL40:IMUX.IMUX19 | PPC.TSTC405DCRDBUSOUTI23 |
| TCELL40:OUT.BEST0.TMIN | PPC.APUFCMRADATA28 |
| TCELL40:OUT.BEST1.TMIN | PPC.APUFCMRADATA29 |
| TCELL40:OUT.BEST2.TMIN | PPC.APUFCMRADATA30 |
| TCELL40:OUT.BEST3.TMIN | PPC.APUFCMRADATA31 |
| TCELL40:OUT.BEST4.TMIN | PPC.APUFCMRBDATA28 |
| TCELL40:OUT.BEST5.TMIN | PPC.APUFCMRBDATA29 |
| TCELL40:OUT.BEST6.TMIN | PPC.APUFCMRBDATA30 |
| TCELL40:OUT.BEST7.TMIN | PPC.APUFCMRBDATA31 |
| TCELL40:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA28 |
| TCELL40:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA29 |
| TCELL40:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA30 |
| TCELL40:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA31 |
| TCELL40:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXELOADDBUSO24 |
| TCELL40:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXELOADDBUSO25 |
| TCELL40:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXELOADDBUSO26 |
| TCELL40:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXELOADDBUSO27 |
| TCELL40:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXELOADDBUSO28 |
| TCELL40:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXELOADDBUSO29 |
| TCELL40:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXELOADDBUSO30 |
| TCELL40:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXELOADDBUSO31 |
| TCELL40:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXELOADDBUSO24 |
| TCELL40:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXELOADDBUSO25 |
| TCELL40:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXELOADDBUSO26 |
| TCELL40:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXELOADDBUSO27 |
| TCELL40:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXELOADDBUSO28 |
| TCELL40:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXELOADDBUSO29 |
| TCELL40:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXELOADDBUSO30 |
| TCELL40:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXELOADDBUSO31 |
| TCELL41:IMUX.SR0 | PPC.TIEAPUUDI33 |
| TCELL41:IMUX.SR1 | PPC.TIEAPUUDI32 |
| TCELL41:IMUX.SR2 | PPC.TIEAPUUDI31 |
| TCELL41:IMUX.SR3 | PPC.TIEAPUUDI30 |
| TCELL41:IMUX.CE0 | PPC.TIEAPUUDI37 |
| TCELL41:IMUX.CE1 | PPC.TIEAPUUDI36 |
| TCELL41:IMUX.CE2 | PPC.TIEAPUUDI35 |
| TCELL41:IMUX.CE3 | PPC.TIEAPUUDI34 |
| TCELL41:IMUX.IMUX0 | PPC.FCMAPURESULT24 |
| TCELL41:IMUX.IMUX1 | PPC.FCMAPURESULT25 |
| TCELL41:IMUX.IMUX2 | PPC.FCMAPURESULT26 |
| TCELL41:IMUX.IMUX3 | PPC.FCMAPURESULT27 |
| TCELL41:IMUX.IMUX4 | PPC.PLBC405DCURDDBUS0 |
| TCELL41:IMUX.IMUX5 | PPC.PLBC405DCURDDBUS1 |
| TCELL41:IMUX.IMUX6 | PPC.PLBC405DCURDDBUS2 |
| TCELL41:IMUX.IMUX7 | PPC.PLBC405DCURDDBUS3 |
| TCELL41:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI24 |
| TCELL41:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI25 |
| TCELL41:IMUX.IMUX10 | PPC.TSTC405DSOCMABUSI26 |
| TCELL41:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI27 |
| TCELL41:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI16 |
| TCELL41:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI17 |
| TCELL41:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI18 |
| TCELL41:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI19 |
| TCELL41:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI24 |
| TCELL41:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI25 |
| TCELL41:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI26 |
| TCELL41:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI27 |
| TCELL41:OUT.BEST0.TMIN | PPC.APUFCMRADATA24 |
| TCELL41:OUT.BEST1.TMIN | PPC.APUFCMRADATA25 |
| TCELL41:OUT.BEST2.TMIN | PPC.APUFCMRADATA26 |
| TCELL41:OUT.BEST3.TMIN | PPC.APUFCMRADATA27 |
| TCELL41:OUT.BEST4.TMIN | PPC.APUFCMRBDATA24 |
| TCELL41:OUT.BEST5.TMIN | PPC.APUFCMRBDATA25 |
| TCELL41:OUT.BEST6.TMIN | PPC.APUFCMRBDATA26 |
| TCELL41:OUT.BEST7.TMIN | PPC.APUFCMRBDATA27 |
| TCELL41:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA24 |
| TCELL41:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA25 |
| TCELL41:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA26 |
| TCELL41:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA27 |
| TCELL41:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXELOADDBUSO16 |
| TCELL41:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXELOADDBUSO17 |
| TCELL41:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXELOADDBUSO18 |
| TCELL41:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXELOADDBUSO19 |
| TCELL41:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXELOADDBUSO20 |
| TCELL41:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXELOADDBUSO21 |
| TCELL41:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXELOADDBUSO22 |
| TCELL41:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXELOADDBUSO23 |
| TCELL41:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXELOADDBUSO16 |
| TCELL41:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXELOADDBUSO17 |
| TCELL41:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXELOADDBUSO18 |
| TCELL41:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXELOADDBUSO19 |
| TCELL41:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXELOADDBUSO20 |
| TCELL41:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXELOADDBUSO21 |
| TCELL41:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXELOADDBUSO22 |
| TCELL41:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXELOADDBUSO23 |
| TCELL42:IMUX.SR0 | PPC.TIEAPUUDI219 |
| TCELL42:IMUX.SR1 | PPC.TIEAPUUDI218 |
| TCELL42:IMUX.SR2 | PPC.TIEAPUUDI217 |
| TCELL42:IMUX.SR3 | PPC.TIEAPUUDI216 |
| TCELL42:IMUX.CE0 | PPC.TIEAPUUDI223 |
| TCELL42:IMUX.CE1 | PPC.TIEAPUUDI222 |
| TCELL42:IMUX.CE2 | PPC.TIEAPUUDI221 |
| TCELL42:IMUX.CE3 | PPC.TIEAPUUDI220 |
| TCELL42:IMUX.IMUX0 | PPC.FCMAPURESULT20 |
| TCELL42:IMUX.IMUX1 | PPC.FCMAPURESULT21 |
| TCELL42:IMUX.IMUX2 | PPC.FCMAPURESULT22 |
| TCELL42:IMUX.IMUX3 | PPC.FCMAPURESULT23 |
| TCELL42:IMUX.IMUX4 | PPC.TSTAPUC405DCDFORCEALIGNI |
| TCELL42:IMUX.IMUX5 | PPC.TSTAPUC405DCDFORCEBESTEERINGI |
| TCELL42:IMUX.IMUX6 | PPC.TSTAPUC405DCDLDSTBYTEI |
| TCELL42:IMUX.IMUX7 | PPC.TSTAPUC405FPUEXCEPTIONI |
| TCELL42:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI20 |
| TCELL42:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI21 |
| TCELL42:IMUX.IMUX10 | PPC.TSTC405DSOCMABUSI22 |
| TCELL42:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI23 |
| TCELL42:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI12 |
| TCELL42:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI13 |
| TCELL42:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI14 |
| TCELL42:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI15 |
| TCELL42:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI20 |
| TCELL42:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI21 |
| TCELL42:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI22 |
| TCELL42:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI23 |
| TCELL42:OUT.BEST0.TMIN | PPC.APUFCMRADATA20 |
| TCELL42:OUT.BEST1.TMIN | PPC.APUFCMRADATA21 |
| TCELL42:OUT.BEST2.TMIN | PPC.APUFCMRADATA22 |
| TCELL42:OUT.BEST3.TMIN | PPC.APUFCMRADATA23 |
| TCELL42:OUT.BEST4.TMIN | PPC.APUFCMRBDATA20 |
| TCELL42:OUT.BEST5.TMIN | PPC.APUFCMRBDATA21 |
| TCELL42:OUT.BEST6.TMIN | PPC.APUFCMRBDATA22 |
| TCELL42:OUT.BEST7.TMIN | PPC.APUFCMRBDATA23 |
| TCELL42:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA20 |
| TCELL42:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA21 |
| TCELL42:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA22 |
| TCELL42:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA23 |
| TCELL42:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXELOADDBUSO8 |
| TCELL42:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXELOADDBUSO9 |
| TCELL42:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXELOADDBUSO10 |
| TCELL42:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXELOADDBUSO11 |
| TCELL42:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXELOADDBUSO12 |
| TCELL42:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXELOADDBUSO13 |
| TCELL42:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXELOADDBUSO14 |
| TCELL42:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXELOADDBUSO15 |
| TCELL42:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXELOADDBUSO8 |
| TCELL42:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXELOADDBUSO9 |
| TCELL42:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXELOADDBUSO10 |
| TCELL42:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXELOADDBUSO11 |
| TCELL42:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXELOADDBUSO12 |
| TCELL42:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXELOADDBUSO13 |
| TCELL42:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXELOADDBUSO14 |
| TCELL42:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXELOADDBUSO15 |
| TCELL43:IMUX.SR0 | PPC.TIEAPUUDI211 |
| TCELL43:IMUX.SR1 | PPC.TIEAPUUDI210 |
| TCELL43:IMUX.SR2 | PPC.TIEAPUUDI29 |
| TCELL43:IMUX.SR3 | PPC.TIEAPUUDI28 |
| TCELL43:IMUX.CE0 | PPC.TIEAPUUDI215 |
| TCELL43:IMUX.CE1 | PPC.TIEAPUUDI214 |
| TCELL43:IMUX.CE2 | PPC.TIEAPUUDI213 |
| TCELL43:IMUX.CE3 | PPC.TIEAPUUDI212 |
| TCELL43:IMUX.IMUX0 | PPC.FCMAPURESULT16 |
| TCELL43:IMUX.IMUX1 | PPC.FCMAPURESULT17 |
| TCELL43:IMUX.IMUX2 | PPC.FCMAPURESULT18 |
| TCELL43:IMUX.IMUX3 | PPC.FCMAPURESULT19 |
| TCELL43:IMUX.IMUX4 | PPC.TSTAPUC405DCDLDSTHWI |
| TCELL43:IMUX.IMUX5 | PPC.TSTAPUC405DCDLDSTWDI |
| TCELL43:IMUX.IMUX6 | PPC.TSTAPUC405DCDLDSTDWI |
| TCELL43:IMUX.IMUX7 | PPC.TSTAPUC405DCDLDSTQWI |
| TCELL43:IMUX.IMUX8 | PPC.TSTC405DSOCMABUSI16 |
| TCELL43:IMUX.IMUX9 | PPC.TSTC405DSOCMABUSI17 |
| TCELL43:IMUX.IMUX10 | PPC.TSTC405DSOCMABUSI18 |
| TCELL43:IMUX.IMUX11 | PPC.TSTC405DSOCMABUSI19 |
| TCELL43:IMUX.IMUX12 | PPC.TSTC405DSOCMLOADREQI |
| TCELL43:IMUX.IMUX13 | PPC.TSTC405DSOCMSTOREREQI |
| TCELL43:IMUX.IMUX14 | PPC.TSTC405DSOCMWAITI |
| TCELL43:IMUX.IMUX15 | PPC.TSTC405DSOCMXLTVALIDI |
| TCELL43:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI16 |
| TCELL43:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI17 |
| TCELL43:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI18 |
| TCELL43:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI19 |
| TCELL43:OUT.BEST0.TMIN | PPC.APUFCMRADATA16 |
| TCELL43:OUT.BEST1.TMIN | PPC.APUFCMRADATA17 |
| TCELL43:OUT.BEST2.TMIN | PPC.APUFCMRADATA18 |
| TCELL43:OUT.BEST3.TMIN | PPC.APUFCMRADATA19 |
| TCELL43:OUT.BEST4.TMIN | PPC.APUFCMRBDATA16 |
| TCELL43:OUT.BEST5.TMIN | PPC.APUFCMRBDATA17 |
| TCELL43:OUT.BEST6.TMIN | PPC.APUFCMRBDATA18 |
| TCELL43:OUT.BEST7.TMIN | PPC.APUFCMRBDATA19 |
| TCELL43:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA16 |
| TCELL43:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA17 |
| TCELL43:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA18 |
| TCELL43:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA19 |
| TCELL43:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXELOADDBUSO0 |
| TCELL43:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXELOADDBUSO1 |
| TCELL43:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXELOADDBUSO2 |
| TCELL43:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXELOADDBUSO3 |
| TCELL43:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXELOADDBUSO4 |
| TCELL43:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXELOADDBUSO5 |
| TCELL43:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXELOADDBUSO6 |
| TCELL43:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXELOADDBUSO7 |
| TCELL43:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXELOADDBUSO0 |
| TCELL43:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXELOADDBUSO1 |
| TCELL43:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXELOADDBUSO2 |
| TCELL43:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXELOADDBUSO3 |
| TCELL43:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXELOADDBUSO4 |
| TCELL43:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXELOADDBUSO5 |
| TCELL43:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXELOADDBUSO6 |
| TCELL43:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXELOADDBUSO7 |
| TCELL44:IMUX.SR0 | PPC.TIEAPUUDI23 |
| TCELL44:IMUX.SR1 | PPC.TIEAPUUDI22 |
| TCELL44:IMUX.SR2 | PPC.TIEAPUUDI21 |
| TCELL44:IMUX.SR3 | PPC.TIEAPUUDI20 |
| TCELL44:IMUX.CE0 | PPC.TIEAPUUDI27 |
| TCELL44:IMUX.CE1 | PPC.TIEAPUUDI26 |
| TCELL44:IMUX.CE2 | PPC.TIEAPUUDI25 |
| TCELL44:IMUX.CE3 | PPC.TIEAPUUDI24 |
| TCELL44:IMUX.IMUX0 | PPC.FCMAPURESULT12 |
| TCELL44:IMUX.IMUX1 | PPC.FCMAPURESULT13 |
| TCELL44:IMUX.IMUX2 | PPC.FCMAPURESULT14 |
| TCELL44:IMUX.IMUX3 | PPC.FCMAPURESULT15 |
| TCELL44:IMUX.IMUX4 | PPC.FCMAPUDCDFORCEALIGN |
| TCELL44:IMUX.IMUX5 | PPC.TSTC405APUXERCAI |
| TCELL44:IMUX.IMUX6 | PPC.TSTAPUC405APUDIVENI |
| TCELL44:IMUX.IMUX7 | PPC.TSTAPUC405APUPRESENTI |
| TCELL44:IMUX.IMUX8 | PPC.TSTAPUC405DCDVALIDOPI |
| TCELL44:IMUX.IMUX9 | PPC.TSTAPUC405DCDAPUOPI |
| TCELL44:IMUX.IMUX10 | PPC.TSTAPUC405EXEXERCAI |
| TCELL44:IMUX.IMUX11 | PPC.TSTAPUC405EXEXEROVI |
| TCELL44:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI8 |
| TCELL44:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI9 |
| TCELL44:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI10 |
| TCELL44:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI11 |
| TCELL44:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI12 |
| TCELL44:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI13 |
| TCELL44:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI14 |
| TCELL44:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI15 |
| TCELL44:OUT.BEST0.TMIN | PPC.APUFCMRADATA12 |
| TCELL44:OUT.BEST1.TMIN | PPC.APUFCMRADATA13 |
| TCELL44:OUT.BEST2.TMIN | PPC.APUFCMRADATA14 |
| TCELL44:OUT.BEST3.TMIN | PPC.APUFCMRADATA15 |
| TCELL44:OUT.BEST4.TMIN | PPC.APUFCMRBDATA12 |
| TCELL44:OUT.BEST5.TMIN | PPC.APUFCMRBDATA13 |
| TCELL44:OUT.BEST6.TMIN | PPC.APUFCMRBDATA14 |
| TCELL44:OUT.BEST7.TMIN | PPC.APUFCMRBDATA15 |
| TCELL44:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA12 |
| TCELL44:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA13 |
| TCELL44:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA14 |
| TCELL44:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA15 |
| TCELL44:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERBDATAO24 |
| TCELL44:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERBDATAO25 |
| TCELL44:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERBDATAO26 |
| TCELL44:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERBDATAO27 |
| TCELL44:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXERBDATAO28 |
| TCELL44:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXERBDATAO29 |
| TCELL44:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXERBDATAO30 |
| TCELL44:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXERBDATAO31 |
| TCELL44:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERBDATAO24 |
| TCELL44:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERBDATAO25 |
| TCELL44:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERBDATAO26 |
| TCELL44:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERBDATAO27 |
| TCELL44:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXERBDATAO28 |
| TCELL44:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXERBDATAO29 |
| TCELL44:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXERBDATAO30 |
| TCELL44:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXERBDATAO31 |
| TCELL45:IMUX.SR0 | PPC.TIEAPUUDI119 |
| TCELL45:IMUX.SR1 | PPC.TIEAPUUDI118 |
| TCELL45:IMUX.SR2 | PPC.TIEAPUUDI117 |
| TCELL45:IMUX.SR3 | PPC.TIEAPUUDI116 |
| TCELL45:IMUX.CE0 | PPC.TIEAPUUDI123 |
| TCELL45:IMUX.CE1 | PPC.TIEAPUUDI122 |
| TCELL45:IMUX.CE2 | PPC.TIEAPUUDI121 |
| TCELL45:IMUX.CE3 | PPC.TIEAPUUDI120 |
| TCELL45:IMUX.IMUX0 | PPC.FCMAPURESULT8 |
| TCELL45:IMUX.IMUX1 | PPC.FCMAPURESULT9 |
| TCELL45:IMUX.IMUX2 | PPC.FCMAPURESULT10 |
| TCELL45:IMUX.IMUX3 | PPC.FCMAPURESULT11 |
| TCELL45:IMUX.IMUX4 | PPC.TSTAPUC405EXCEPTIONI |
| TCELL45:IMUX.IMUX5 | PPC.TSTAPUC405EXEBLOCKINGMCOI |
| TCELL45:IMUX.IMUX6 | PPC.TSTAPUC405EXENONBLOCKINGMCOI |
| TCELL45:IMUX.IMUX7 | PPC.TSTAPUC405EXEBUSYI |
| TCELL45:IMUX.IMUX8 | PPC.TSTC405APUDCDFULLI |
| TCELL45:IMUX.IMUX9 | PPC.TSTC405APUDCDHOLDI |
| TCELL45:IMUX.IMUX10 | PPC.TSTC405APUEXEFLUSHI |
| TCELL45:IMUX.IMUX11 | PPC.TSTC405APUEXEHOLDI |
| TCELL45:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI4 |
| TCELL45:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI5 |
| TCELL45:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI6 |
| TCELL45:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI7 |
| TCELL45:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI8 |
| TCELL45:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI9 |
| TCELL45:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI10 |
| TCELL45:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI11 |
| TCELL45:OUT.BEST0.TMIN | PPC.APUFCMRADATA8 |
| TCELL45:OUT.BEST1.TMIN | PPC.APUFCMRADATA9 |
| TCELL45:OUT.BEST2.TMIN | PPC.APUFCMRADATA10 |
| TCELL45:OUT.BEST3.TMIN | PPC.APUFCMRADATA11 |
| TCELL45:OUT.BEST4.TMIN | PPC.APUFCMRBDATA8 |
| TCELL45:OUT.BEST5.TMIN | PPC.APUFCMRBDATA9 |
| TCELL45:OUT.BEST6.TMIN | PPC.APUFCMRBDATA10 |
| TCELL45:OUT.BEST7.TMIN | PPC.APUFCMRBDATA11 |
| TCELL45:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA8 |
| TCELL45:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA9 |
| TCELL45:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA10 |
| TCELL45:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA11 |
| TCELL45:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERBDATAO16 |
| TCELL45:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERBDATAO17 |
| TCELL45:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERBDATAO18 |
| TCELL45:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERBDATAO19 |
| TCELL45:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXERBDATAO20 |
| TCELL45:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXERBDATAO21 |
| TCELL45:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXERBDATAO22 |
| TCELL45:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXERBDATAO23 |
| TCELL45:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERBDATAO16 |
| TCELL45:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERBDATAO17 |
| TCELL45:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERBDATAO18 |
| TCELL45:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERBDATAO19 |
| TCELL45:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXERBDATAO20 |
| TCELL45:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXERBDATAO21 |
| TCELL45:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXERBDATAO22 |
| TCELL45:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXERBDATAO23 |
| TCELL46:IMUX.SR0 | PPC.TIEAPUUDI111 |
| TCELL46:IMUX.SR1 | PPC.TIEAPUUDI110 |
| TCELL46:IMUX.SR2 | PPC.TIEAPUUDI19 |
| TCELL46:IMUX.SR3 | PPC.TIEAPUUDI18 |
| TCELL46:IMUX.CE0 | PPC.TIEAPUUDI115 |
| TCELL46:IMUX.CE1 | PPC.TIEAPUUDI114 |
| TCELL46:IMUX.CE2 | PPC.TIEAPUUDI113 |
| TCELL46:IMUX.CE3 | PPC.TIEAPUUDI112 |
| TCELL46:IMUX.IMUX0 | PPC.FCMAPURESULT4 |
| TCELL46:IMUX.IMUX1 | PPC.FCMAPURESULT5 |
| TCELL46:IMUX.IMUX2 | PPC.FCMAPURESULT6 |
| TCELL46:IMUX.IMUX3 | PPC.FCMAPURESULT7 |
| TCELL46:IMUX.IMUX4 | PPC.TSTAPUC405SLEEPREQI |
| TCELL46:IMUX.IMUX5 | PPC.TSTAPUC405EXELDDEPENDI |
| TCELL46:IMUX.IMUX6 | PPC.TSTAPUC405WBLDDEPENDI |
| TCELL46:IMUX.IMUX7 | PPC.TSTAPUC405LWBLDDEPENDI |
| TCELL46:IMUX.IMUX8 | PPC.TSTC405APUEXELOADDVALIDI |
| TCELL46:IMUX.IMUX9 | PPC.TSTC405APUWBENDIANI |
| TCELL46:IMUX.IMUX10 | PPC.TSTC405APUWBFLUSHI |
| TCELL46:IMUX.IMUX11 | PPC.TSTC405APUWBHOLDI |
| TCELL46:IMUX.IMUX12 | PPC.TSTC405DCRDBUSOUTI0 |
| TCELL46:IMUX.IMUX13 | PPC.TSTC405DCRDBUSOUTI1 |
| TCELL46:IMUX.IMUX14 | PPC.TSTC405DCRDBUSOUTI2 |
| TCELL46:IMUX.IMUX15 | PPC.TSTC405DCRDBUSOUTI3 |
| TCELL46:IMUX.IMUX16 | PPC.TSTC405DSOCMWRDBUSI4 |
| TCELL46:IMUX.IMUX17 | PPC.TSTC405DSOCMWRDBUSI5 |
| TCELL46:IMUX.IMUX18 | PPC.TSTC405DSOCMWRDBUSI6 |
| TCELL46:IMUX.IMUX19 | PPC.TSTC405DSOCMWRDBUSI7 |
| TCELL46:OUT.BEST0.TMIN | PPC.APUFCMRADATA4 |
| TCELL46:OUT.BEST1.TMIN | PPC.APUFCMRADATA5 |
| TCELL46:OUT.BEST2.TMIN | PPC.APUFCMRADATA6 |
| TCELL46:OUT.BEST3.TMIN | PPC.APUFCMRADATA7 |
| TCELL46:OUT.BEST4.TMIN | PPC.APUFCMRBDATA4 |
| TCELL46:OUT.BEST5.TMIN | PPC.APUFCMRBDATA5 |
| TCELL46:OUT.BEST6.TMIN | PPC.APUFCMRBDATA6 |
| TCELL46:OUT.BEST7.TMIN | PPC.APUFCMRBDATA7 |
| TCELL46:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA4 |
| TCELL46:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA5 |
| TCELL46:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA6 |
| TCELL46:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA7 |
| TCELL46:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERBDATAO8 |
| TCELL46:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERBDATAO9 |
| TCELL46:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERBDATAO10 |
| TCELL46:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERBDATAO11 |
| TCELL46:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXERBDATAO12 |
| TCELL46:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXERBDATAO13 |
| TCELL46:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXERBDATAO14 |
| TCELL46:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXERBDATAO15 |
| TCELL46:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERBDATAO8 |
| TCELL46:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERBDATAO9 |
| TCELL46:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERBDATAO10 |
| TCELL46:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERBDATAO11 |
| TCELL46:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXERBDATAO12 |
| TCELL46:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXERBDATAO13 |
| TCELL46:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXERBDATAO14 |
| TCELL46:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXERBDATAO15 |
| TCELL47:IMUX.SR0 | PPC.TIEAPUUDI13 |
| TCELL47:IMUX.SR1 | PPC.TIEAPUUDI12 |
| TCELL47:IMUX.SR2 | PPC.TIEAPUUDI11 |
| TCELL47:IMUX.SR3 | PPC.TIEAPUUDI10 |
| TCELL47:IMUX.CE0 | PPC.TIEAPUUDI17 |
| TCELL47:IMUX.CE1 | PPC.TIEAPUUDI16 |
| TCELL47:IMUX.CE2 | PPC.TIEAPUUDI15 |
| TCELL47:IMUX.CE3 | PPC.TIEAPUUDI14 |
| TCELL47:IMUX.IMUX0 | PPC.FCMAPURESULT0 |
| TCELL47:IMUX.IMUX1 | PPC.FCMAPURESULT1 |
| TCELL47:IMUX.IMUX2 | PPC.FCMAPURESULT2 |
| TCELL47:IMUX.IMUX3 | PPC.FCMAPURESULT3 |
| TCELL47:IMUX.IMUX4 | PPC.FCMAPUDCDXERCAEN |
| TCELL47:IMUX.IMUX5 | PPC.FCMAPUDCDXEROVEN |
| TCELL47:IMUX.IMUX6 | PPC.FCMAPUDCDPRIVOP |
| TCELL47:IMUX.IMUX7 | PPC.FCMAPUDCDCREN |
| TCELL47:IMUX.IMUX8 | PPC.TSTC405APUEXEWDCNTI0 |
| TCELL47:IMUX.IMUX9 | PPC.TSTC405APUEXEWDCNTI1 |
| TCELL47:IMUX.IMUX10 | PPC.TSTC405APUMSRFE0I |
| TCELL47:IMUX.IMUX11 | PPC.TSTC405APUMSRFE1I |
| TCELL47:IMUX.IMUX12 | PPC.TSTC405DSOCMWRDBUSI0 |
| TCELL47:IMUX.IMUX13 | PPC.TSTC405DSOCMWRDBUSI1 |
| TCELL47:IMUX.IMUX14 | PPC.TSTC405DSOCMWRDBUSI2 |
| TCELL47:IMUX.IMUX15 | PPC.TSTC405DSOCMWRDBUSI3 |
| TCELL47:OUT.BEST0.TMIN | PPC.APUFCMRADATA0 |
| TCELL47:OUT.BEST1.TMIN | PPC.APUFCMRADATA1 |
| TCELL47:OUT.BEST2.TMIN | PPC.APUFCMRADATA2 |
| TCELL47:OUT.BEST3.TMIN | PPC.APUFCMRADATA3 |
| TCELL47:OUT.BEST4.TMIN | PPC.APUFCMRBDATA0 |
| TCELL47:OUT.BEST5.TMIN | PPC.APUFCMRBDATA1 |
| TCELL47:OUT.BEST6.TMIN | PPC.APUFCMRBDATA2 |
| TCELL47:OUT.BEST7.TMIN | PPC.APUFCMRBDATA3 |
| TCELL47:OUT.SEC0.TMIN | PPC.APUFCMLOADDATA0 |
| TCELL47:OUT.SEC1.TMIN | PPC.APUFCMLOADDATA1 |
| TCELL47:OUT.SEC2.TMIN | PPC.APUFCMLOADDATA2 |
| TCELL47:OUT.SEC3.TMIN | PPC.APUFCMLOADDATA3 |
| TCELL47:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERBDATAO0 |
| TCELL47:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERBDATAO1 |
| TCELL47:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERBDATAO2 |
| TCELL47:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERBDATAO3 |
| TCELL47:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUEXERBDATAO4 |
| TCELL47:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUEXERBDATAO5 |
| TCELL47:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUEXERBDATAO6 |
| TCELL47:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUEXERBDATAO7 |
| TCELL47:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERBDATAO0 |
| TCELL47:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERBDATAO1 |
| TCELL47:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERBDATAO2 |
| TCELL47:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERBDATAO3 |
| TCELL47:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUEXERBDATAO4 |
| TCELL47:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUEXERBDATAO5 |
| TCELL47:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUEXERBDATAO6 |
| TCELL47:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUEXERBDATAO7 |
| TCELL48:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC24 |
| TCELL48:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC25 |
| TCELL48:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC26 |
| TCELL48:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC27 |
| TCELL48:IMUX.CE0 | EMAC.TIEEMAC0CONFIGVEC20 |
| TCELL48:IMUX.CE1 | EMAC.TIEEMAC0CONFIGVEC21 |
| TCELL48:IMUX.CE2 | EMAC.TIEEMAC0CONFIGVEC22 |
| TCELL48:IMUX.CE3 | EMAC.TIEEMAC0CONFIGVEC23 |
| TCELL48:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS40 |
| TCELL48:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS41 |
| TCELL48:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS42 |
| TCELL48:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS43 |
| TCELL48:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS56 |
| TCELL48:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS57 |
| TCELL48:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS58 |
| TCELL48:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS59 |
| TCELL48:IMUX.IMUX8 | PPC.BRAMISOCMRDDBUS44 |
| TCELL48:IMUX.IMUX9 | PPC.BRAMISOCMRDDBUS45 |
| TCELL48:IMUX.IMUX10 | PPC.BRAMISOCMRDDBUS46 |
| TCELL48:IMUX.IMUX11 | PPC.BRAMISOCMRDDBUS47 |
| TCELL48:IMUX.IMUX12 | PPC.TSTISOCMC405READDATAOUTI60 |
| TCELL48:IMUX.IMUX13 | PPC.TSTISOCMC405READDATAOUTI61 |
| TCELL48:IMUX.IMUX14 | PPC.TSTISOCMC405READDATAOUTI62 |
| TCELL48:IMUX.IMUX15 | PPC.TSTISOCMC405READDATAOUTI63 |
| TCELL48:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI56 |
| TCELL48:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI57 |
| TCELL48:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI58 |
| TCELL48:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI59 |
| TCELL48:OUT.BEST0.TMIN | PPC.C405JTGCAPTUREDR |
| TCELL48:OUT.BEST1.TMIN | PPC.C405JTGEXTEST |
| TCELL48:OUT.BEST2.TMIN | PPC.C405JTGPGMOUT |
| TCELL48:OUT.BEST3.TMIN | PPC.C405TRCEVENEXECUTIONSTATUS0 |
| TCELL48:OUT.BEST4.TMIN | PPC.C405TRCEVENEXECUTIONSTATUS1 |
| TCELL48:OUT.BEST5.TMIN | PPC.C405TRCODDEXECUTIONSTATUS0 |
| TCELL48:OUT.BEST6.TMIN | PPC.C405TRCODDEXECUTIONSTATUS1 |
| TCELL48:OUT.BEST7.TMIN | PPC.ISOCMBRAMWRDBUS0 |
| TCELL48:OUT.SEC0.TMIN | PPC.ISOCMBRAMWRDBUS1 |
| TCELL48:OUT.SEC1.TMIN | PPC.ISOCMBRAMWRDBUS2 |
| TCELL48:OUT.SEC2.TMIN | PPC.ISOCMBRAMWRDBUS3 |
| TCELL48:OUT.SEC3.TMIN | PPC.ISOCMBRAMWRDBUS4 |
| TCELL48:OUT.HALF.BOT0.TMIN | PPC.TSTCPUCLKENO |
| TCELL48:OUT.HALF.BOT1.TMIN | PPC.TSTCLKINACTO |
| TCELL48:OUT.HALF.BOT2.TMIN | PPC.TSTTIMERENO |
| TCELL48:OUT.HALF.BOT3.TMIN | PPC.TSTJTAGENO |
| TCELL48:OUT.HALF.BOT4.TMIN | PPC.TSTISOCMC405RDDVALIDO0 |
| TCELL48:OUT.HALF.BOT5.TMIN | PPC.TSTISOCMC405RDDVALIDO1 |
| TCELL48:OUT.HALF.BOT6.TMIN | PPC.TSTISOCMC405HOLDO |
| TCELL48:OUT.HALT.TOP0.TMIN | PPC.TSTCPUCLKENO |
| TCELL48:OUT.HALT.TOP1.TMIN | PPC.TSTCLKINACTO |
| TCELL48:OUT.HALT.TOP2.TMIN | PPC.TSTTIMERENO |
| TCELL48:OUT.HALT.TOP3.TMIN | PPC.TSTJTAGENO |
| TCELL48:OUT.HALT.TOP4.TMIN | PPC.TSTISOCMC405RDDVALIDO0 |
| TCELL48:OUT.HALT.TOP5.TMIN | PPC.TSTISOCMC405RDDVALIDO1 |
| TCELL48:OUT.HALT.TOP6.TMIN | PPC.TSTISOCMC405HOLDO |
| TCELL49:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC32 |
| TCELL49:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC33 |
| TCELL49:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC34 |
| TCELL49:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC35 |
| TCELL49:IMUX.CE0 | EMAC.TIEEMAC0CONFIGVEC28 |
| TCELL49:IMUX.CE1 | EMAC.TIEEMAC0CONFIGVEC29 |
| TCELL49:IMUX.CE2 | EMAC.TIEEMAC0CONFIGVEC30 |
| TCELL49:IMUX.CE3 | EMAC.TIEEMAC0CONFIGVEC31 |
| TCELL49:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS36 |
| TCELL49:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS37 |
| TCELL49:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS38 |
| TCELL49:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS39 |
| TCELL49:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS52 |
| TCELL49:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS53 |
| TCELL49:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS54 |
| TCELL49:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS55 |
| TCELL49:IMUX.IMUX8 | PPC.BRAMISOCMRDDBUS60 |
| TCELL49:IMUX.IMUX9 | PPC.BRAMISOCMRDDBUS61 |
| TCELL49:IMUX.IMUX10 | PPC.BRAMISOCMRDDBUS62 |
| TCELL49:IMUX.IMUX11 | PPC.BRAMISOCMRDDBUS63 |
| TCELL49:IMUX.IMUX12 | PPC.BRAMISOCMDCRRDDBUS28 |
| TCELL49:IMUX.IMUX13 | PPC.BRAMISOCMDCRRDDBUS29 |
| TCELL49:IMUX.IMUX14 | PPC.BRAMISOCMDCRRDDBUS30 |
| TCELL49:IMUX.IMUX15 | PPC.BRAMISOCMDCRRDDBUS31 |
| TCELL49:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI52 |
| TCELL49:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI53 |
| TCELL49:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI54 |
| TCELL49:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI55 |
| TCELL49:OUT.BEST0.TMIN | PPC.ISOCMBRAMWRDBUS5 |
| TCELL49:OUT.BEST1.TMIN | PPC.ISOCMBRAMWRDBUS6 |
| TCELL49:OUT.BEST2.TMIN | PPC.ISOCMBRAMWRDBUS7 |
| TCELL49:OUT.BEST3.TMIN | PPC.ISOCMBRAMWRDBUS8 |
| TCELL49:OUT.BEST4.TMIN | PPC.ISOCMBRAMWRDBUS9 |
| TCELL49:OUT.BEST5.TMIN | PPC.ISOCMBRAMWRDBUS10 |
| TCELL49:OUT.BEST6.TMIN | PPC.ISOCMBRAMWRDBUS11 |
| TCELL49:OUT.BEST7.TMIN | PPC.ISOCMBRAMWRDBUS12 |
| TCELL49:OUT.SEC0.TMIN | PPC.ISOCMBRAMWRDBUS13 |
| TCELL49:OUT.SEC1.TMIN | PPC.ISOCMBRAMWRDBUS14 |
| TCELL49:OUT.SEC2.TMIN | PPC.ISOCMBRAMWRDBUS15 |
| TCELL49:OUT.SEC3.TMIN | PPC.ISOCMBRAMWRDBUS16 |
| TCELL49:OUT.HALF.BOT0.TMIN | PPC.TSTC405ISOCMREQPENDINGO |
| TCELL49:OUT.HALF.BOT1.TMIN | PPC.TSTC405ISOCMICUREADYO |
| TCELL49:OUT.HALF.BOT2.TMIN | PPC.TSTC405ISOCMXLTVALIDO |
| TCELL49:OUT.HALF.BOT3.TMIN | PPC.TSTC405ISOCMABORTO |
| TCELL49:OUT.HALF.BOT4.TMIN | PPC.C405ISOCMCACHEABLE |
| TCELL49:OUT.HALF.BOT5.TMIN | PPC.C405ISOCMCONTEXTSYNC |
| TCELL49:OUT.HALF.BOT6.TMIN | PPC.C405ISOCMU0ATTR |
| TCELL49:OUT.HALT.TOP0.TMIN | PPC.TSTC405ISOCMREQPENDINGO |
| TCELL49:OUT.HALT.TOP1.TMIN | PPC.TSTC405ISOCMICUREADYO |
| TCELL49:OUT.HALT.TOP2.TMIN | PPC.TSTC405ISOCMXLTVALIDO |
| TCELL49:OUT.HALT.TOP3.TMIN | PPC.TSTC405ISOCMABORTO |
| TCELL49:OUT.HALT.TOP4.TMIN | PPC.C405ISOCMCACHEABLE |
| TCELL49:OUT.HALT.TOP5.TMIN | PPC.C405ISOCMCONTEXTSYNC |
| TCELL49:OUT.HALT.TOP6.TMIN | PPC.C405ISOCMU0ATTR |
| TCELL50:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC37 |
| TCELL50:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC38 |
| TCELL50:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC39 |
| TCELL50:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC40 |
| TCELL50:IMUX.CE0 | PPC.TIEC405DETERMINISTICMULT |
| TCELL50:IMUX.CE1 | PPC.TIEC405DISOPERANDFWD |
| TCELL50:IMUX.CE2 | PPC.TIEC405MMUEN |
| TCELL50:IMUX.CE3 | EMAC.TIEEMAC0CONFIGVEC36 |
| TCELL50:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS32 |
| TCELL50:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS33 |
| TCELL50:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS34 |
| TCELL50:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS35 |
| TCELL50:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS48 |
| TCELL50:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS49 |
| TCELL50:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS50 |
| TCELL50:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS51 |
| TCELL50:IMUX.IMUX8 | PPC.BRAMISOCMDCRRDDBUS20 |
| TCELL50:IMUX.IMUX9 | PPC.BRAMISOCMDCRRDDBUS21 |
| TCELL50:IMUX.IMUX10 | PPC.BRAMISOCMDCRRDDBUS22 |
| TCELL50:IMUX.IMUX11 | PPC.BRAMISOCMDCRRDDBUS23 |
| TCELL50:IMUX.IMUX12 | PPC.BRAMISOCMDCRRDDBUS24 |
| TCELL50:IMUX.IMUX13 | PPC.BRAMISOCMDCRRDDBUS25 |
| TCELL50:IMUX.IMUX14 | PPC.BRAMISOCMDCRRDDBUS26 |
| TCELL50:IMUX.IMUX15 | PPC.BRAMISOCMDCRRDDBUS27 |
| TCELL50:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI48 |
| TCELL50:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI49 |
| TCELL50:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI50 |
| TCELL50:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI51 |
| TCELL50:OUT.BEST0.TMIN | PPC.ISOCMBRAMWRDBUS17 |
| TCELL50:OUT.BEST1.TMIN | PPC.ISOCMBRAMWRDBUS18 |
| TCELL50:OUT.BEST2.TMIN | PPC.ISOCMBRAMWRDBUS19 |
| TCELL50:OUT.BEST3.TMIN | PPC.ISOCMBRAMWRDBUS20 |
| TCELL50:OUT.BEST4.TMIN | PPC.ISOCMBRAMWRDBUS21 |
| TCELL50:OUT.BEST5.TMIN | PPC.ISOCMBRAMWRDBUS22 |
| TCELL50:OUT.BEST6.TMIN | PPC.ISOCMBRAMWRDBUS23 |
| TCELL50:OUT.BEST7.TMIN | PPC.ISOCMBRAMWRDBUS24 |
| TCELL50:OUT.SEC0.TMIN | PPC.ISOCMBRAMWRDBUS25 |
| TCELL50:OUT.SEC1.TMIN | PPC.ISOCMBRAMWRDBUS26 |
| TCELL50:OUT.SEC2.TMIN | PPC.ISOCMBRAMWRDBUS27 |
| TCELL50:OUT.SEC3.TMIN | PPC.ISOCMBRAMWRDBUS28 |
| TCELL50:OUT.HALF.BOT0.TMIN | PPC.TSTC405ISOCMABUSO24 |
| TCELL50:OUT.HALF.BOT1.TMIN | PPC.TSTC405ISOCMABUSO25 |
| TCELL50:OUT.HALF.BOT2.TMIN | PPC.TSTC405ISOCMABUSO26 |
| TCELL50:OUT.HALF.BOT3.TMIN | PPC.TSTC405ISOCMABUSO27 |
| TCELL50:OUT.HALF.BOT4.TMIN | PPC.TSTC405ISOCMABUSO28 |
| TCELL50:OUT.HALF.BOT5.TMIN | PPC.TSTC405ISOCMABUSO29 |
| TCELL50:OUT.HALT.TOP0.TMIN | PPC.TSTC405ISOCMABUSO24 |
| TCELL50:OUT.HALT.TOP1.TMIN | PPC.TSTC405ISOCMABUSO25 |
| TCELL50:OUT.HALT.TOP2.TMIN | PPC.TSTC405ISOCMABUSO26 |
| TCELL50:OUT.HALT.TOP3.TMIN | PPC.TSTC405ISOCMABUSO27 |
| TCELL50:OUT.HALT.TOP4.TMIN | PPC.TSTC405ISOCMABUSO28 |
| TCELL50:OUT.HALT.TOP5.TMIN | PPC.TSTC405ISOCMABUSO29 |
| TCELL51:IMUX.SR0 | EMAC.TIEEMAC0CONFIGVEC45 |
| TCELL51:IMUX.SR1 | EMAC.TIEEMAC0CONFIGVEC46 |
| TCELL51:IMUX.SR2 | EMAC.TIEEMAC0CONFIGVEC47 |
| TCELL51:IMUX.SR3 | EMAC.TIEEMAC0CONFIGVEC48 |
| TCELL51:IMUX.CLK0 | PPC.PLBCLK |
| TCELL51:IMUX.CE0 | EMAC.TIEEMAC0CONFIGVEC41 |
| TCELL51:IMUX.CE1 | EMAC.TIEEMAC0CONFIGVEC42 |
| TCELL51:IMUX.CE2 | EMAC.TIEEMAC0CONFIGVEC43 |
| TCELL51:IMUX.CE3 | EMAC.TIEEMAC0CONFIGVEC44 |
| TCELL51:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS12 |
| TCELL51:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS13 |
| TCELL51:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS14 |
| TCELL51:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS15 |
| TCELL51:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS28 |
| TCELL51:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS29 |
| TCELL51:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS30 |
| TCELL51:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS31 |
| TCELL51:IMUX.IMUX8 | PPC.BRAMISOCMDCRRDDBUS12 |
| TCELL51:IMUX.IMUX9 | PPC.BRAMISOCMDCRRDDBUS13 |
| TCELL51:IMUX.IMUX10 | PPC.BRAMISOCMDCRRDDBUS14 |
| TCELL51:IMUX.IMUX11 | PPC.BRAMISOCMDCRRDDBUS15 |
| TCELL51:IMUX.IMUX12 | PPC.BRAMISOCMDCRRDDBUS16 |
| TCELL51:IMUX.IMUX13 | PPC.BRAMISOCMDCRRDDBUS17 |
| TCELL51:IMUX.IMUX14 | PPC.BRAMISOCMDCRRDDBUS18 |
| TCELL51:IMUX.IMUX15 | PPC.BRAMISOCMDCRRDDBUS19 |
| TCELL51:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI44 |
| TCELL51:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI45 |
| TCELL51:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI46 |
| TCELL51:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI47 |
| TCELL51:OUT.BEST0.TMIN | PPC.ISOCMBRAMWRDBUS29 |
| TCELL51:OUT.BEST1.TMIN | PPC.ISOCMBRAMWRDBUS30 |
| TCELL51:OUT.BEST2.TMIN | PPC.ISOCMBRAMWRDBUS31 |
| TCELL51:OUT.BEST3.TMIN | PPC.ISOCMBRAMWRABUS8 |
| TCELL51:OUT.BEST4.TMIN | PPC.ISOCMBRAMWRABUS9 |
| TCELL51:OUT.BEST5.TMIN | PPC.ISOCMBRAMWRABUS10 |
| TCELL51:OUT.BEST6.TMIN | PPC.ISOCMBRAMWRABUS11 |
| TCELL51:OUT.BEST7.TMIN | PPC.ISOCMBRAMWRABUS12 |
| TCELL51:OUT.SEC0.TMIN | PPC.ISOCMBRAMWRABUS13 |
| TCELL51:OUT.SEC1.TMIN | PPC.ISOCMBRAMWRABUS14 |
| TCELL51:OUT.SEC2.TMIN | PPC.ISOCMBRAMWRABUS15 |
| TCELL51:OUT.SEC3.TMIN | PPC.ISOCMBRAMWRABUS16 |
| TCELL51:OUT.HALF.BOT0.TMIN | PPC.TSTC405ISOCMABUSO16 |
| TCELL51:OUT.HALF.BOT1.TMIN | PPC.TSTC405ISOCMABUSO17 |
| TCELL51:OUT.HALF.BOT2.TMIN | PPC.TSTC405ISOCMABUSO18 |
| TCELL51:OUT.HALF.BOT3.TMIN | PPC.TSTC405ISOCMABUSO19 |
| TCELL51:OUT.HALF.BOT4.TMIN | PPC.TSTC405ISOCMABUSO20 |
| TCELL51:OUT.HALF.BOT5.TMIN | PPC.TSTC405ISOCMABUSO21 |
| TCELL51:OUT.HALF.BOT6.TMIN | PPC.TSTC405ISOCMABUSO22 |
| TCELL51:OUT.HALF.BOT7.TMIN | PPC.TSTC405ISOCMABUSO23 |
| TCELL51:OUT.HALT.TOP0.TMIN | PPC.TSTC405ISOCMABUSO16 |
| TCELL51:OUT.HALT.TOP1.TMIN | PPC.TSTC405ISOCMABUSO17 |
| TCELL51:OUT.HALT.TOP2.TMIN | PPC.TSTC405ISOCMABUSO18 |
| TCELL51:OUT.HALT.TOP3.TMIN | PPC.TSTC405ISOCMABUSO19 |
| TCELL51:OUT.HALT.TOP4.TMIN | PPC.TSTC405ISOCMABUSO20 |
| TCELL51:OUT.HALT.TOP5.TMIN | PPC.TSTC405ISOCMABUSO21 |
| TCELL51:OUT.HALT.TOP6.TMIN | PPC.TSTC405ISOCMABUSO22 |
| TCELL51:OUT.HALT.TOP7.TMIN | PPC.TSTC405ISOCMABUSO23 |
| TCELL52:IMUX.SR0 | PPC.ISCNTLVALUE4 |
| TCELL52:IMUX.SR1 | PPC.ISCNTLVALUE5 |
| TCELL52:IMUX.SR2 | PPC.ISCNTLVALUE6 |
| TCELL52:IMUX.SR3 | PPC.ISCNTLVALUE7 |
| TCELL52:IMUX.CLK0 | PPC.JTGC405TCK |
| TCELL52:IMUX.CE0 | PPC.ISCNTLVALUE0 |
| TCELL52:IMUX.CE1 | PPC.ISCNTLVALUE1 |
| TCELL52:IMUX.CE2 | PPC.ISCNTLVALUE2 |
| TCELL52:IMUX.CE3 | PPC.ISCNTLVALUE3 |
| TCELL52:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS8 |
| TCELL52:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS9 |
| TCELL52:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS10 |
| TCELL52:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS11 |
| TCELL52:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS24 |
| TCELL52:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS25 |
| TCELL52:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS26 |
| TCELL52:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS27 |
| TCELL52:IMUX.IMUX8 | PPC.BRAMISOCMDCRRDDBUS8 |
| TCELL52:IMUX.IMUX9 | PPC.BRAMISOCMDCRRDDBUS9 |
| TCELL52:IMUX.IMUX10 | PPC.BRAMISOCMDCRRDDBUS10 |
| TCELL52:IMUX.IMUX11 | PPC.BRAMISOCMDCRRDDBUS11 |
| TCELL52:IMUX.IMUX12 | PPC.TSTISOCMC405READDATAOUTI40 |
| TCELL52:IMUX.IMUX13 | PPC.TSTISOCMC405READDATAOUTI41 |
| TCELL52:IMUX.IMUX14 | PPC.TSTISOCMC405READDATAOUTI42 |
| TCELL52:IMUX.IMUX15 | PPC.TSTISOCMC405READDATAOUTI43 |
| TCELL52:IMUX.IMUX16 | PPC.TSTISOCMC405RDDVALIDI0 |
| TCELL52:IMUX.IMUX17 | PPC.TSTISOCMC405RDDVALIDI1 |
| TCELL52:OUT.BEST0.TMIN | PPC.ISOCMBRAMWRABUS17 |
| TCELL52:OUT.BEST1.TMIN | PPC.ISOCMBRAMWRABUS18 |
| TCELL52:OUT.BEST2.TMIN | PPC.ISOCMBRAMWRABUS19 |
| TCELL52:OUT.BEST3.TMIN | PPC.ISOCMBRAMWRABUS20 |
| TCELL52:OUT.BEST4.TMIN | PPC.ISOCMBRAMWRABUS21 |
| TCELL52:OUT.BEST5.TMIN | PPC.ISOCMBRAMWRABUS22 |
| TCELL52:OUT.BEST6.TMIN | PPC.ISOCMBRAMWRABUS23 |
| TCELL52:OUT.BEST7.TMIN | PPC.ISOCMBRAMWRABUS24 |
| TCELL52:OUT.SEC0.TMIN | PPC.ISOCMBRAMWRABUS25 |
| TCELL52:OUT.SEC1.TMIN | PPC.ISOCMBRAMWRABUS26 |
| TCELL52:OUT.SEC2.TMIN | PPC.ISOCMBRAMWRABUS27 |
| TCELL52:OUT.SEC3.TMIN | PPC.ISOCMBRAMWRABUS28 |
| TCELL52:OUT.HALF.BOT0.TMIN | PPC.TSTC405ISOCMABUSO8 |
| TCELL52:OUT.HALF.BOT1.TMIN | PPC.TSTC405ISOCMABUSO9 |
| TCELL52:OUT.HALF.BOT2.TMIN | PPC.TSTC405ISOCMABUSO10 |
| TCELL52:OUT.HALF.BOT3.TMIN | PPC.TSTC405ISOCMABUSO11 |
| TCELL52:OUT.HALF.BOT4.TMIN | PPC.TSTC405ISOCMABUSO12 |
| TCELL52:OUT.HALF.BOT5.TMIN | PPC.TSTC405ISOCMABUSO13 |
| TCELL52:OUT.HALF.BOT6.TMIN | PPC.TSTC405ISOCMABUSO14 |
| TCELL52:OUT.HALF.BOT7.TMIN | PPC.TSTC405ISOCMABUSO15 |
| TCELL52:OUT.HALT.TOP0.TMIN | PPC.TSTC405ISOCMABUSO8 |
| TCELL52:OUT.HALT.TOP1.TMIN | PPC.TSTC405ISOCMABUSO9 |
| TCELL52:OUT.HALT.TOP2.TMIN | PPC.TSTC405ISOCMABUSO10 |
| TCELL52:OUT.HALT.TOP3.TMIN | PPC.TSTC405ISOCMABUSO11 |
| TCELL52:OUT.HALT.TOP4.TMIN | PPC.TSTC405ISOCMABUSO12 |
| TCELL52:OUT.HALT.TOP5.TMIN | PPC.TSTC405ISOCMABUSO13 |
| TCELL52:OUT.HALT.TOP6.TMIN | PPC.TSTC405ISOCMABUSO14 |
| TCELL52:OUT.HALT.TOP7.TMIN | PPC.TSTC405ISOCMABUSO15 |
| TCELL53:IMUX.SR0 | PPC.ISARCVALUE4 |
| TCELL53:IMUX.SR1 | PPC.ISARCVALUE5 |
| TCELL53:IMUX.SR2 | PPC.ISARCVALUE6 |
| TCELL53:IMUX.SR3 | PPC.ISARCVALUE7 |
| TCELL53:IMUX.CLK0 | PPC.CPMC405CLOCK |
| TCELL53:IMUX.CE0 | PPC.ISARCVALUE0 |
| TCELL53:IMUX.CE1 | PPC.ISARCVALUE1 |
| TCELL53:IMUX.CE2 | PPC.ISARCVALUE2 |
| TCELL53:IMUX.CE3 | PPC.ISARCVALUE3 |
| TCELL53:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS4 |
| TCELL53:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS5 |
| TCELL53:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS6 |
| TCELL53:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS7 |
| TCELL53:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS20 |
| TCELL53:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS21 |
| TCELL53:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS22 |
| TCELL53:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS23 |
| TCELL53:IMUX.IMUX8 | PPC.EICC405CRITINPUTIRQ |
| TCELL53:IMUX.IMUX9 | PPC.EICC405EXTINPUTIRQ |
| TCELL53:IMUX.IMUX10 | PPC.BRAMISOCMDCRRDDBUS4 |
| TCELL53:IMUX.IMUX11 | PPC.BRAMISOCMDCRRDDBUS5 |
| TCELL53:IMUX.IMUX12 | PPC.BRAMISOCMDCRRDDBUS6 |
| TCELL53:IMUX.IMUX13 | PPC.BRAMISOCMDCRRDDBUS7 |
| TCELL53:IMUX.IMUX14 | PPC.TSTISOCMC405HOLDI |
| TCELL53:IMUX.IMUX15 | PPC.TSTISOCMC405READDATAOUTI36 |
| TCELL53:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI37 |
| TCELL53:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI38 |
| TCELL53:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI39 |
| TCELL53:OUT.BEST0.TMIN | PPC.ISOCMBRAMEVENWRITEEN |
| TCELL53:OUT.BEST1.TMIN | PPC.ISOCMBRAMODDWRITEEN |
| TCELL53:OUT.BEST2.TMIN | PPC.ISOCMBRAMEN |
| TCELL53:OUT.BEST3.TMIN | PPC.ISOCMBRAMRDABUS8 |
| TCELL53:OUT.BEST4.TMIN | PPC.ISOCMBRAMRDABUS9 |
| TCELL53:OUT.BEST5.TMIN | PPC.ISOCMBRAMRDABUS10 |
| TCELL53:OUT.BEST6.TMIN | PPC.ISOCMBRAMRDABUS11 |
| TCELL53:OUT.BEST7.TMIN | PPC.ISOCMBRAMRDABUS12 |
| TCELL53:OUT.SEC0.TMIN | PPC.ISOCMBRAMRDABUS13 |
| TCELL53:OUT.SEC1.TMIN | PPC.ISOCMBRAMRDABUS14 |
| TCELL53:OUT.SEC2.TMIN | PPC.ISOCMBRAMRDABUS15 |
| TCELL53:OUT.SEC3.TMIN | PPC.ISOCMBRAMRDABUS16 |
| TCELL53:OUT.HALF.BOT0.TMIN | PPC.TSTC405ISOCMABUSO0 |
| TCELL53:OUT.HALF.BOT1.TMIN | PPC.TSTC405ISOCMABUSO1 |
| TCELL53:OUT.HALF.BOT2.TMIN | PPC.TSTC405ISOCMABUSO2 |
| TCELL53:OUT.HALF.BOT3.TMIN | PPC.TSTC405ISOCMABUSO3 |
| TCELL53:OUT.HALF.BOT4.TMIN | PPC.TSTC405ISOCMABUSO4 |
| TCELL53:OUT.HALF.BOT5.TMIN | PPC.TSTC405ISOCMABUSO5 |
| TCELL53:OUT.HALF.BOT6.TMIN | PPC.TSTC405ISOCMABUSO6 |
| TCELL53:OUT.HALF.BOT7.TMIN | PPC.TSTC405ISOCMABUSO7 |
| TCELL53:OUT.HALT.TOP0.TMIN | PPC.TSTC405ISOCMABUSO0 |
| TCELL53:OUT.HALT.TOP1.TMIN | PPC.TSTC405ISOCMABUSO1 |
| TCELL53:OUT.HALT.TOP2.TMIN | PPC.TSTC405ISOCMABUSO2 |
| TCELL53:OUT.HALT.TOP3.TMIN | PPC.TSTC405ISOCMABUSO3 |
| TCELL53:OUT.HALT.TOP4.TMIN | PPC.TSTC405ISOCMABUSO4 |
| TCELL53:OUT.HALT.TOP5.TMIN | PPC.TSTC405ISOCMABUSO5 |
| TCELL53:OUT.HALT.TOP6.TMIN | PPC.TSTC405ISOCMABUSO6 |
| TCELL53:OUT.HALT.TOP7.TMIN | PPC.TSTC405ISOCMABUSO7 |
| TCELL54:IMUX.SR0 | PPC.TIEC405CLOCKSELECTS0 |
| TCELL54:IMUX.SR1 | PPC.TIEC405CLOCKSELECTS1 |
| TCELL54:IMUX.SR2 | PPC.CPMC405CLOCKFBENABLE |
| TCELL54:IMUX.SR3 | PPC.TSTSEPPCEMACI |
| TCELL54:IMUX.CLK0 | PPC.BRAMISOCMCLK |
| TCELL54:IMUX.CE0 | PPC.TIEC405ICUMARGIN |
| TCELL54:IMUX.CE1 | PPC.TIEC405DCUMARGIN |
| TCELL54:IMUX.CE2 | PPC.TIEC405TAGMARGIN |
| TCELL54:IMUX.CE3 | PPC.TIEC405TLBMARGIN |
| TCELL54:IMUX.IMUX0 | PPC.BRAMISOCMRDDBUS0 |
| TCELL54:IMUX.IMUX1 | PPC.BRAMISOCMRDDBUS1 |
| TCELL54:IMUX.IMUX2 | PPC.BRAMISOCMRDDBUS2 |
| TCELL54:IMUX.IMUX3 | PPC.BRAMISOCMRDDBUS3 |
| TCELL54:IMUX.IMUX4 | PPC.BRAMISOCMRDDBUS16 |
| TCELL54:IMUX.IMUX5 | PPC.BRAMISOCMRDDBUS17 |
| TCELL54:IMUX.IMUX6 | PPC.BRAMISOCMRDDBUS18 |
| TCELL54:IMUX.IMUX7 | PPC.BRAMISOCMRDDBUS19 |
| TCELL54:IMUX.IMUX8 | PPC.JTGC405BNDSCANTDO |
| TCELL54:IMUX.IMUX9 | PPC.JTGC405TDI |
| TCELL54:IMUX.IMUX10 | PPC.JTGC405TMS |
| TCELL54:IMUX.IMUX11 | PPC.JTGC405TRSTNEG |
| TCELL54:IMUX.IMUX12 | PPC.BRAMISOCMDCRRDDBUS0 |
| TCELL54:IMUX.IMUX13 | PPC.BRAMISOCMDCRRDDBUS1 |
| TCELL54:IMUX.IMUX14 | PPC.BRAMISOCMDCRRDDBUS2 |
| TCELL54:IMUX.IMUX15 | PPC.BRAMISOCMDCRRDDBUS3 |
| TCELL54:IMUX.IMUX16 | PPC.TSTISOCMC405READDATAOUTI32 |
| TCELL54:IMUX.IMUX17 | PPC.TSTISOCMC405READDATAOUTI33 |
| TCELL54:IMUX.IMUX18 | PPC.TSTISOCMC405READDATAOUTI34 |
| TCELL54:IMUX.IMUX19 | PPC.TSTISOCMC405READDATAOUTI35 |
| TCELL54:OUT.BEST0.TMIN | PPC.ISOCMBRAMRDABUS17 |
| TCELL54:OUT.BEST1.TMIN | PPC.ISOCMBRAMRDABUS18 |
| TCELL54:OUT.BEST2.TMIN | PPC.ISOCMBRAMRDABUS19 |
| TCELL54:OUT.BEST3.TMIN | PPC.ISOCMBRAMRDABUS20 |
| TCELL54:OUT.BEST4.TMIN | PPC.ISOCMBRAMRDABUS21 |
| TCELL54:OUT.BEST5.TMIN | PPC.ISOCMBRAMRDABUS22 |
| TCELL54:OUT.BEST6.TMIN | PPC.ISOCMBRAMRDABUS23 |
| TCELL54:OUT.BEST7.TMIN | PPC.ISOCMBRAMRDABUS24 |
| TCELL54:OUT.SEC0.TMIN | PPC.ISOCMBRAMRDABUS25 |
| TCELL54:OUT.SEC1.TMIN | PPC.ISOCMBRAMRDABUS26 |
| TCELL54:OUT.SEC2.TMIN | PPC.ISOCMBRAMRDABUS27 |
| TCELL54:OUT.SEC3.TMIN | PPC.ISOCMBRAMRDABUS28 |
| TCELL55:IMUX.SR0 | PPC.DSARCVALUE4 |
| TCELL55:IMUX.SR1 | PPC.DSARCVALUE5 |
| TCELL55:IMUX.SR2 | PPC.DSARCVALUE6 |
| TCELL55:IMUX.SR3 | PPC.DSARCVALUE7 |
| TCELL55:IMUX.CLK0 | PPC.BRAMDSOCMCLK |
| TCELL55:IMUX.CE0 | PPC.DSARCVALUE0 |
| TCELL55:IMUX.CE1 | PPC.DSARCVALUE1 |
| TCELL55:IMUX.CE2 | PPC.DSARCVALUE2 |
| TCELL55:IMUX.CE3 | PPC.DSARCVALUE3 |
| TCELL55:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS0 |
| TCELL55:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS1 |
| TCELL55:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS2 |
| TCELL55:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS3 |
| TCELL55:IMUX.IMUX4 | PPC.BRAMDSOCMRDDBUS4 |
| TCELL55:IMUX.IMUX5 | PPC.BRAMDSOCMRDDBUS5 |
| TCELL55:IMUX.IMUX6 | PPC.BRAMDSOCMRDDBUS6 |
| TCELL55:IMUX.IMUX7 | PPC.BRAMDSOCMRDDBUS7 |
| TCELL55:IMUX.IMUX8 | PPC.TSTAPUC405EXERESULTI28 |
| TCELL55:IMUX.IMUX9 | PPC.TSTAPUC405EXERESULTI29 |
| TCELL55:IMUX.IMUX10 | PPC.TSTAPUC405EXERESULTI30 |
| TCELL55:IMUX.IMUX11 | PPC.TSTAPUC405EXERESULTI31 |
| TCELL55:IMUX.IMUX12 | PPC.TSTDSOCMC405RDDBUSI28 |
| TCELL55:IMUX.IMUX13 | PPC.TSTDSOCMC405RDDBUSI29 |
| TCELL55:IMUX.IMUX14 | PPC.TSTDSOCMC405RDDBUSI30 |
| TCELL55:IMUX.IMUX15 | PPC.TSTDSOCMC405RDDBUSI31 |
| TCELL55:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI24 |
| TCELL55:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI25 |
| TCELL55:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI26 |
| TCELL55:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI27 |
| TCELL55:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS0 |
| TCELL55:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS1 |
| TCELL55:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS2 |
| TCELL55:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS3 |
| TCELL55:OUT.BEST4.TMIN | PPC.DSOCMBRAMWRDBUS4 |
| TCELL55:OUT.BEST5.TMIN | PPC.DSOCMBRAMWRDBUS5 |
| TCELL55:OUT.BEST6.TMIN | PPC.DSOCMBRAMWRDBUS6 |
| TCELL55:OUT.BEST7.TMIN | PPC.DSOCMBRAMWRDBUS7 |
| TCELL55:OUT.SEC0.TMIN | PPC.DSOCMBRAMABUS24 |
| TCELL55:OUT.SEC1.TMIN | PPC.DSOCMBRAMABUS25 |
| TCELL55:OUT.SEC2.TMIN | PPC.DSOCMBRAMABUS26 |
| TCELL55:OUT.SEC3.TMIN | PPC.DSOCMBRAMABUS27 |
| TCELL55:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO24 |
| TCELL55:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO25 |
| TCELL55:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO26 |
| TCELL55:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO27 |
| TCELL55:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO24 |
| TCELL55:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO25 |
| TCELL55:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO26 |
| TCELL55:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO27 |
| TCELL55:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO24 |
| TCELL55:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO25 |
| TCELL55:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO26 |
| TCELL55:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO27 |
| TCELL55:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO24 |
| TCELL55:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO25 |
| TCELL55:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO26 |
| TCELL55:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO27 |
| TCELL56:IMUX.SR0 | PPC.DSCNTLVALUE4 |
| TCELL56:IMUX.SR1 | PPC.DSCNTLVALUE5 |
| TCELL56:IMUX.SR2 | PPC.DSCNTLVALUE6 |
| TCELL56:IMUX.SR3 | PPC.DSCNTLVALUE7 |
| TCELL56:IMUX.CE0 | PPC.DSCNTLVALUE0 |
| TCELL56:IMUX.CE1 | PPC.DSCNTLVALUE1 |
| TCELL56:IMUX.CE2 | PPC.DSCNTLVALUE2 |
| TCELL56:IMUX.CE3 | PPC.DSCNTLVALUE3 |
| TCELL56:IMUX.IMUX0 | PPC.FCMAPUDCDLDSTBYTE |
| TCELL56:IMUX.IMUX1 | PPC.FCMAPUDCDLDSTHW |
| TCELL56:IMUX.IMUX2 | PPC.FCMAPUDCDLDSTWD |
| TCELL56:IMUX.IMUX3 | PPC.FCMAPUDCDLDSTDW |
| TCELL56:IMUX.IMUX4 | PPC.FCMAPUDCDLDSTQW |
| TCELL56:IMUX.IMUX5 | PPC.FCMAPUDCDTRAPBE |
| TCELL56:IMUX.IMUX6 | PPC.FCMAPUDCDTRAPLE |
| TCELL56:IMUX.IMUX7 | PPC.FCMAPULOADWAIT |
| TCELL56:IMUX.IMUX8 | PPC.TSTAPUC405EXERESULTI20 |
| TCELL56:IMUX.IMUX9 | PPC.TSTAPUC405EXERESULTI21 |
| TCELL56:IMUX.IMUX10 | PPC.TSTAPUC405EXERESULTI22 |
| TCELL56:IMUX.IMUX11 | PPC.TSTAPUC405EXERESULTI23 |
| TCELL56:IMUX.IMUX12 | PPC.TSTAPUC405EXERESULTI24 |
| TCELL56:IMUX.IMUX13 | PPC.TSTAPUC405EXERESULTI25 |
| TCELL56:IMUX.IMUX14 | PPC.TSTAPUC405EXERESULTI26 |
| TCELL56:IMUX.IMUX15 | PPC.TSTAPUC405EXERESULTI27 |
| TCELL56:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI20 |
| TCELL56:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI21 |
| TCELL56:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI22 |
| TCELL56:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI23 |
| TCELL56:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS8 |
| TCELL56:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS9 |
| TCELL56:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS10 |
| TCELL56:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS11 |
| TCELL56:OUT.BEST4.TMIN | PPC.DSOCMBRAMABUS16 |
| TCELL56:OUT.BEST5.TMIN | PPC.DSOCMBRAMABUS17 |
| TCELL56:OUT.BEST6.TMIN | PPC.DSOCMBRAMABUS18 |
| TCELL56:OUT.BEST7.TMIN | PPC.DSOCMBRAMABUS19 |
| TCELL56:OUT.SEC0.TMIN | PPC.DSOCMBRAMABUS20 |
| TCELL56:OUT.SEC1.TMIN | PPC.DSOCMBRAMABUS21 |
| TCELL56:OUT.SEC2.TMIN | PPC.DSOCMBRAMABUS22 |
| TCELL56:OUT.SEC3.TMIN | PPC.DSOCMBRAMABUS23 |
| TCELL56:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO20 |
| TCELL56:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO21 |
| TCELL56:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO22 |
| TCELL56:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO23 |
| TCELL56:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO20 |
| TCELL56:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO21 |
| TCELL56:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO22 |
| TCELL56:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO23 |
| TCELL56:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO20 |
| TCELL56:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO21 |
| TCELL56:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO22 |
| TCELL56:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO23 |
| TCELL56:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO20 |
| TCELL56:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO21 |
| TCELL56:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO22 |
| TCELL56:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO23 |
| TCELL57:IMUX.SR0 | PPC.TIEAPUCONTROL11 |
| TCELL57:IMUX.SR1 | PPC.TIEAPUCONTROL10 |
| TCELL57:IMUX.SR2 | PPC.TIEAPUCONTROL9 |
| TCELL57:IMUX.SR3 | PPC.TIEAPUCONTROL8 |
| TCELL57:IMUX.CLK0 | EMAC.PHYEMAC1GTXCLK |
| TCELL57:IMUX.CE0 | PPC.TIEAPUCONTROL15 |
| TCELL57:IMUX.CE1 | PPC.TIEAPUCONTROL14 |
| TCELL57:IMUX.CE2 | PPC.TIEAPUCONTROL13 |
| TCELL57:IMUX.CE3 | PPC.TIEAPUCONTROL12 |
| TCELL57:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS8 |
| TCELL57:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS9 |
| TCELL57:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS10 |
| TCELL57:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS11 |
| TCELL57:IMUX.IMUX4 | PPC.FCMAPUEXECRFIELD0 |
| TCELL57:IMUX.IMUX5 | PPC.FCMAPUEXECRFIELD1 |
| TCELL57:IMUX.IMUX6 | PPC.FCMAPUEXECRFIELD2 |
| TCELL57:IMUX.IMUX7 | PPC.DSOCMRWCOMPLETE |
| TCELL57:IMUX.IMUX8 | PPC.FCMAPUDCDLOAD |
| TCELL57:IMUX.IMUX9 | PPC.FCMAPUDCDSTORE |
| TCELL57:IMUX.IMUX10 | PPC.TSTDSOCMC405COMPLETEI |
| TCELL57:IMUX.IMUX11 | PPC.TSTDSOCMC405DISOPERANDFWDI |
| TCELL57:IMUX.IMUX12 | PPC.TSTAPUC405EXERESULTI16 |
| TCELL57:IMUX.IMUX13 | PPC.TSTAPUC405EXERESULTI17 |
| TCELL57:IMUX.IMUX14 | PPC.TSTAPUC405EXERESULTI18 |
| TCELL57:IMUX.IMUX15 | PPC.TSTAPUC405EXERESULTI19 |
| TCELL57:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI16 |
| TCELL57:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI17 |
| TCELL57:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI18 |
| TCELL57:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI19 |
| TCELL57:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS12 |
| TCELL57:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS13 |
| TCELL57:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS14 |
| TCELL57:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS15 |
| TCELL57:OUT.BEST4.TMIN | PPC.DSOCMBRAMBYTEWRITE0 |
| TCELL57:OUT.BEST5.TMIN | PPC.DSOCMBRAMBYTEWRITE1 |
| TCELL57:OUT.BEST6.TMIN | PPC.DSOCMBRAMBYTEWRITE2 |
| TCELL57:OUT.BEST7.TMIN | PPC.DSOCMBRAMBYTEWRITE3 |
| TCELL57:OUT.SEC0.TMIN | PPC.DSOCMBRAMABUS28 |
| TCELL57:OUT.SEC1.TMIN | PPC.DSOCMBRAMABUS29 |
| TCELL57:OUT.SEC2.TMIN | PPC.DSOCMBRAMEN |
| TCELL57:OUT.SEC3.TMIN | PPC.DSOCMRDADDRVALID |
| TCELL57:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO16 |
| TCELL57:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO17 |
| TCELL57:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO18 |
| TCELL57:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO19 |
| TCELL57:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO16 |
| TCELL57:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO17 |
| TCELL57:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO18 |
| TCELL57:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO19 |
| TCELL57:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO16 |
| TCELL57:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO17 |
| TCELL57:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO18 |
| TCELL57:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO19 |
| TCELL57:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO16 |
| TCELL57:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO17 |
| TCELL57:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO18 |
| TCELL57:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO19 |
| TCELL58:IMUX.SR0 | PPC.TIEAPUCONTROL3 |
| TCELL58:IMUX.SR1 | PPC.TIEAPUCONTROL2 |
| TCELL58:IMUX.SR2 | PPC.TIEAPUCONTROL1 |
| TCELL58:IMUX.SR3 | PPC.TIEAPUCONTROL0 |
| TCELL58:IMUX.CLK0 | EMAC.PHYEMAC1RXCLK |
| TCELL58:IMUX.CE0 | PPC.TIEAPUCONTROL7 |
| TCELL58:IMUX.CE1 | PPC.TIEAPUCONTROL6 |
| TCELL58:IMUX.CE2 | PPC.TIEAPUCONTROL5 |
| TCELL58:IMUX.CE3 | PPC.TIEAPUCONTROL4 |
| TCELL58:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS12 |
| TCELL58:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS13 |
| TCELL58:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS14 |
| TCELL58:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS15 |
| TCELL58:IMUX.IMUX4 | PPC.BRAMDSOCMRDDBUS16 |
| TCELL58:IMUX.IMUX5 | PPC.BRAMDSOCMRDDBUS17 |
| TCELL58:IMUX.IMUX6 | PPC.BRAMDSOCMRDDBUS18 |
| TCELL58:IMUX.IMUX7 | PPC.BRAMDSOCMRDDBUS19 |
| TCELL58:IMUX.IMUX8 | PPC.FCMAPUEXEBLOCKINGMCO |
| TCELL58:IMUX.IMUX9 | PPC.TSTAPUC405EXERESULTI12 |
| TCELL58:IMUX.IMUX10 | PPC.TSTAPUC405EXERESULTI13 |
| TCELL58:IMUX.IMUX11 | PPC.TSTAPUC405EXERESULTI14 |
| TCELL58:IMUX.IMUX12 | PPC.TSTAPUC405EXERESULTI15 |
| TCELL58:IMUX.IMUX13 | PPC.TSTDSOCMC405HOLDI |
| TCELL58:IMUX.IMUX14 | PPC.TSTAPUC405DCDTRAPBEI |
| TCELL58:IMUX.IMUX15 | PPC.TSTAPUC405DCDTRAPLEI |
| TCELL58:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI12 |
| TCELL58:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI13 |
| TCELL58:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI14 |
| TCELL58:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI15 |
| TCELL58:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS16 |
| TCELL58:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS17 |
| TCELL58:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS18 |
| TCELL58:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS19 |
| TCELL58:OUT.BEST4.TMIN | PPC.APUFCMINSTRUCTION31 |
| TCELL58:OUT.BEST5.TMIN | PPC.APUFCMINSTRUCTION30 |
| TCELL58:OUT.BEST6.TMIN | PPC.APUFCMINSTRUCTION29 |
| TCELL58:OUT.BEST7.TMIN | PPC.APUFCMINSTRUCTION28 |
| TCELL58:OUT.SEC0.TMIN | PPC.APUFCMINSTRUCTION27 |
| TCELL58:OUT.SEC1.TMIN | PPC.APUFCMINSTRUCTION26 |
| TCELL58:OUT.SEC2.TMIN | PPC.APUFCMINSTRUCTION25 |
| TCELL58:OUT.SEC3.TMIN | PPC.APUFCMINSTRUCTION24 |
| TCELL58:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO12 |
| TCELL58:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO13 |
| TCELL58:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO14 |
| TCELL58:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO15 |
| TCELL58:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO12 |
| TCELL58:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO13 |
| TCELL58:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO14 |
| TCELL58:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO15 |
| TCELL58:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO12 |
| TCELL58:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO13 |
| TCELL58:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO14 |
| TCELL58:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO15 |
| TCELL58:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO12 |
| TCELL58:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO13 |
| TCELL58:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO14 |
| TCELL58:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO15 |
| TCELL59:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC29 |
| TCELL59:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC28 |
| TCELL59:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC27 |
| TCELL59:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC26 |
| TCELL59:IMUX.CLK0 | EMAC.PHYEMAC1MIITXCLK |
| TCELL59:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC33 |
| TCELL59:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC32 |
| TCELL59:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC31 |
| TCELL59:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC30 |
| TCELL59:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS20 |
| TCELL59:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS21 |
| TCELL59:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS22 |
| TCELL59:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS23 |
| TCELL59:IMUX.IMUX4 | PPC.FCMAPUEXENONBLOCKINGMCO |
| TCELL59:IMUX.IMUX5 | PPC.TSTAPUC405EXERESULTI8 |
| TCELL59:IMUX.IMUX6 | PPC.TSTAPUC405EXERESULTI9 |
| TCELL59:IMUX.IMUX7 | PPC.TSTAPUC405EXERESULTI10 |
| TCELL59:IMUX.IMUX8 | PPC.TSTAPUC405EXERESULTI11 |
| TCELL59:IMUX.IMUX9 | PPC.TSTAPUC405DCDLOADI |
| TCELL59:IMUX.IMUX10 | PPC.TSTAPUC405DCDSTOREI |
| TCELL59:IMUX.IMUX11 | PPC.TSTAPUC405DCDXERCAENI |
| TCELL59:IMUX.IMUX12 | PPC.TSTAPUC405DCDXEROVENI |
| TCELL59:IMUX.IMUX13 | PPC.TSTAPUC405DCDPRIVOPI |
| TCELL59:IMUX.IMUX14 | PPC.TSTAPUC405DCDCRENI |
| TCELL59:IMUX.IMUX15 | PPC.TSTAPUC405DCDUPDATEI |
| TCELL59:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI8 |
| TCELL59:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI9 |
| TCELL59:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI10 |
| TCELL59:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI11 |
| TCELL59:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS20 |
| TCELL59:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS21 |
| TCELL59:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS22 |
| TCELL59:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS23 |
| TCELL59:OUT.BEST4.TMIN | PPC.APUFCMINSTRUCTION23 |
| TCELL59:OUT.BEST5.TMIN | PPC.APUFCMINSTRUCTION22 |
| TCELL59:OUT.BEST6.TMIN | PPC.APUFCMINSTRUCTION21 |
| TCELL59:OUT.BEST7.TMIN | PPC.APUFCMINSTRUCTION20 |
| TCELL59:OUT.SEC0.TMIN | PPC.APUFCMINSTRUCTION19 |
| TCELL59:OUT.SEC1.TMIN | PPC.APUFCMINSTRUCTION18 |
| TCELL59:OUT.SEC2.TMIN | PPC.APUFCMINSTRUCTION17 |
| TCELL59:OUT.SEC3.TMIN | PPC.APUFCMINSTRUCTION16 |
| TCELL59:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO8 |
| TCELL59:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO9 |
| TCELL59:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO10 |
| TCELL59:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO11 |
| TCELL59:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO8 |
| TCELL59:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO9 |
| TCELL59:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO10 |
| TCELL59:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO11 |
| TCELL59:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO8 |
| TCELL59:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO9 |
| TCELL59:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO10 |
| TCELL59:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO11 |
| TCELL59:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO8 |
| TCELL59:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO9 |
| TCELL59:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO10 |
| TCELL59:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO11 |
| TCELL60:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC37 |
| TCELL60:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC36 |
| TCELL60:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC35 |
| TCELL60:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC34 |
| TCELL60:IMUX.CLK0 | PPC.CPMFCMCLK |
| TCELL60:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC41 |
| TCELL60:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC40 |
| TCELL60:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC39 |
| TCELL60:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC38 |
| TCELL60:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS24 |
| TCELL60:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS25 |
| TCELL60:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS26 |
| TCELL60:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS27 |
| TCELL60:IMUX.IMUX4 | PPC.FCMAPUDCDFORCEBESTEERING |
| TCELL60:IMUX.IMUX5 | PPC.TSTAPUC405EXERESULTI4 |
| TCELL60:IMUX.IMUX6 | PPC.TSTAPUC405EXERESULTI5 |
| TCELL60:IMUX.IMUX7 | PPC.TSTAPUC405EXERESULTI6 |
| TCELL60:IMUX.IMUX8 | PPC.TSTAPUC405EXERESULTI7 |
| TCELL60:IMUX.IMUX9 | PPC.TSTAPUC405EXECRFIELDI0 |
| TCELL60:IMUX.IMUX10 | PPC.TSTAPUC405EXECRFIELDI1 |
| TCELL60:IMUX.IMUX11 | PPC.TSTAPUC405EXECRFIELDI2 |
| TCELL60:IMUX.IMUX12 | PPC.TSTAPUC405DCDFPUOPI |
| TCELL60:IMUX.IMUX13 | PPC.TSTAPUC405DCDGPRWRITEI |
| TCELL60:IMUX.IMUX14 | PPC.TSTAPUC405DCDRAENI |
| TCELL60:IMUX.IMUX15 | PPC.TSTAPUC405DCDRBENI |
| TCELL60:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI4 |
| TCELL60:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI5 |
| TCELL60:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI6 |
| TCELL60:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI7 |
| TCELL60:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS24 |
| TCELL60:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS25 |
| TCELL60:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS26 |
| TCELL60:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS27 |
| TCELL60:OUT.BEST4.TMIN | PPC.APUFCMINSTRUCTION15 |
| TCELL60:OUT.BEST5.TMIN | PPC.APUFCMINSTRUCTION14 |
| TCELL60:OUT.BEST6.TMIN | PPC.APUFCMINSTRUCTION13 |
| TCELL60:OUT.BEST7.TMIN | PPC.APUFCMINSTRUCTION12 |
| TCELL60:OUT.SEC0.TMIN | PPC.APUFCMINSTRUCTION11 |
| TCELL60:OUT.SEC1.TMIN | PPC.APUFCMINSTRUCTION10 |
| TCELL60:OUT.SEC2.TMIN | PPC.APUFCMINSTRUCTION9 |
| TCELL60:OUT.SEC3.TMIN | PPC.APUFCMINSTRUCTION8 |
| TCELL60:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO4 |
| TCELL60:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO5 |
| TCELL60:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO6 |
| TCELL60:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO7 |
| TCELL60:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO4 |
| TCELL60:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO5 |
| TCELL60:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO6 |
| TCELL60:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO7 |
| TCELL60:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO4 |
| TCELL60:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO5 |
| TCELL60:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO6 |
| TCELL60:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO7 |
| TCELL60:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO4 |
| TCELL60:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO5 |
| TCELL60:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO6 |
| TCELL60:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO7 |
| TCELL61:IMUX.SR0 | EMAC.TIEEMAC1CONFIGVEC45 |
| TCELL61:IMUX.SR1 | EMAC.TIEEMAC1CONFIGVEC44 |
| TCELL61:IMUX.SR2 | EMAC.TIEEMAC1CONFIGVEC43 |
| TCELL61:IMUX.SR3 | EMAC.TIEEMAC1CONFIGVEC42 |
| TCELL61:IMUX.CE0 | EMAC.TIEEMAC1CONFIGVEC49 |
| TCELL61:IMUX.CE1 | EMAC.TIEEMAC1CONFIGVEC48 |
| TCELL61:IMUX.CE2 | EMAC.TIEEMAC1CONFIGVEC47 |
| TCELL61:IMUX.CE3 | EMAC.TIEEMAC1CONFIGVEC46 |
| TCELL61:IMUX.IMUX0 | PPC.BRAMDSOCMRDDBUS28 |
| TCELL61:IMUX.IMUX1 | PPC.BRAMDSOCMRDDBUS29 |
| TCELL61:IMUX.IMUX2 | PPC.BRAMDSOCMRDDBUS30 |
| TCELL61:IMUX.IMUX3 | PPC.BRAMDSOCMRDDBUS31 |
| TCELL61:IMUX.IMUX4 | PPC.FCMAPUDCDUPDATE |
| TCELL61:IMUX.IMUX5 | PPC.FCMAPUDCDGPRWRITE |
| TCELL61:IMUX.IMUX6 | PPC.FCMAPUDCDRAEN |
| TCELL61:IMUX.IMUX7 | PPC.FCMAPUDCDRBEN |
| TCELL61:IMUX.IMUX8 | PPC.TSTAPUC405EXERESULTI0 |
| TCELL61:IMUX.IMUX9 | PPC.TSTAPUC405EXERESULTI1 |
| TCELL61:IMUX.IMUX10 | PPC.TSTAPUC405EXERESULTI2 |
| TCELL61:IMUX.IMUX11 | PPC.TSTAPUC405EXERESULTI3 |
| TCELL61:IMUX.IMUX12 | PPC.TSTAPUC405EXECRI0 |
| TCELL61:IMUX.IMUX13 | PPC.TSTAPUC405EXECRI1 |
| TCELL61:IMUX.IMUX14 | PPC.TSTAPUC405EXECRI2 |
| TCELL61:IMUX.IMUX15 | PPC.TSTAPUC405EXECRI3 |
| TCELL61:IMUX.IMUX16 | PPC.TSTDSOCMC405RDDBUSI0 |
| TCELL61:IMUX.IMUX17 | PPC.TSTDSOCMC405RDDBUSI1 |
| TCELL61:IMUX.IMUX18 | PPC.TSTDSOCMC405RDDBUSI2 |
| TCELL61:IMUX.IMUX19 | PPC.TSTDSOCMC405RDDBUSI3 |
| TCELL61:OUT.BEST0.TMIN | PPC.DSOCMBRAMWRDBUS28 |
| TCELL61:OUT.BEST1.TMIN | PPC.DSOCMBRAMWRDBUS29 |
| TCELL61:OUT.BEST2.TMIN | PPC.DSOCMBRAMWRDBUS30 |
| TCELL61:OUT.BEST3.TMIN | PPC.DSOCMBRAMWRDBUS31 |
| TCELL61:OUT.BEST4.TMIN | PPC.APUFCMINSTRUCTION7 |
| TCELL61:OUT.BEST5.TMIN | PPC.APUFCMINSTRUCTION6 |
| TCELL61:OUT.BEST6.TMIN | PPC.APUFCMINSTRUCTION5 |
| TCELL61:OUT.BEST7.TMIN | PPC.APUFCMINSTRUCTION4 |
| TCELL61:OUT.SEC0.TMIN | PPC.APUFCMINSTRUCTION3 |
| TCELL61:OUT.SEC1.TMIN | PPC.APUFCMINSTRUCTION2 |
| TCELL61:OUT.SEC2.TMIN | PPC.APUFCMINSTRUCTION1 |
| TCELL61:OUT.SEC3.TMIN | PPC.APUFCMINSTRUCTION0 |
| TCELL61:OUT.HALF.BOT0.TMIN | PPC.TSTC405APUEXERADATAO0 |
| TCELL61:OUT.HALF.BOT1.TMIN | PPC.TSTC405APUEXERADATAO1 |
| TCELL61:OUT.HALF.BOT2.TMIN | PPC.TSTC405APUEXERADATAO2 |
| TCELL61:OUT.HALF.BOT3.TMIN | PPC.TSTC405APUEXERADATAO3 |
| TCELL61:OUT.HALF.BOT4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO0 |
| TCELL61:OUT.HALF.BOT5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO1 |
| TCELL61:OUT.HALF.BOT6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO2 |
| TCELL61:OUT.HALF.BOT7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO3 |
| TCELL61:OUT.HALT.TOP0.TMIN | PPC.TSTC405APUEXERADATAO0 |
| TCELL61:OUT.HALT.TOP1.TMIN | PPC.TSTC405APUEXERADATAO1 |
| TCELL61:OUT.HALT.TOP2.TMIN | PPC.TSTC405APUEXERADATAO2 |
| TCELL61:OUT.HALT.TOP3.TMIN | PPC.TSTC405APUEXERADATAO3 |
| TCELL61:OUT.HALT.TOP4.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO0 |
| TCELL61:OUT.HALT.TOP5.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO1 |
| TCELL61:OUT.HALT.TOP6.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO2 |
| TCELL61:OUT.HALT.TOP7.TMIN | PPC.TSTC405APUDCDINSTRUCTIONO3 |