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General Interconnect

TODO: document

Tile slots

virtex4 tile slots
SlotTilesBel slots
INTINTINT
INTFINTFINTF_INT, INTF_TESTMUX
BELCLB, BRAM, DSP, IO, DCM, CCM, PPC, MGT, CLK_BUFGSPEC_INT, SLICE[0], SLICE[1], SLICE[2], SLICE[3], BRAM, BRAM_F, BRAM_H[0], BRAM_H[1], BRAM_ADDR, DSP[0], DSP[1], DSP_C, ILOGIC[0], ILOGIC[1], OLOGIC[0], OLOGIC[1], IODELAY[0], IODELAY[1], IDELAY[0], IDELAY[1], ODELAY[0], ODELAY[1], IOB[0], IOB[1], DCM[0], DCM[1], PLL[0], PLL[1], PPR_FRAME, PHASER_IN[0], PHASER_IN[1], PHASER_IN[2], PHASER_IN[3], PHASER_OUT[0], PHASER_OUT[1], PHASER_OUT[2], PHASER_OUT[3], PHASER_REF, PHY_CONTROL, BUFMRCE[0], BUFMRCE[1], CCM, PMCD[0], PMCD[1], DPM, BUFHCE_W[0], BUFHCE_W[1], BUFHCE_W[2], BUFHCE_W[3], BUFHCE_W[4], BUFHCE_W[5], BUFHCE_W[6], BUFHCE_W[7], BUFHCE_W[8], BUFHCE_W[9], BUFHCE_W[10], BUFHCE_W[11], BUFHCE_E[0], BUFHCE_E[1], BUFHCE_E[2], BUFHCE_E[3], BUFHCE_E[4], BUFHCE_E[5], BUFHCE_E[6], BUFHCE_E[7], BUFHCE_E[8], BUFHCE_E[9], BUFHCE_E[10], BUFHCE_E[11], PMV_CLK, PMVIOB_CLK, PMV2, PMV2_SVT, MTBF2, PPC, EMAC, PCIE, PCIE3, GT11[0], GT11[1], GT11CLK, GTP_DUAL, GTX_DUAL, HCLK_GTX, GTCLK[0], GTCLK[1], GTX[0], GTX[1], GTX[2], GTX[3], GTH_QUAD, HCLK_DRP_GTP_MID, GTP_COMMON, GTX_COMMON, GTP_CHANNEL, GTX_CHANNEL, CRC32[0], CRC32[1], CRC32[2], CRC32[3], BUFGCTRL[0], BUFGCTRL[1], BUFGCTRL[2], BUFGCTRL[3], BUFGCTRL[4], BUFGCTRL[5], BUFGCTRL[6], BUFGCTRL[7], BUFGCTRL[8], BUFGCTRL[9], BUFGCTRL[10], BUFGCTRL[11], BUFGCTRL[12], BUFGCTRL[13], BUFGCTRL[14], BUFGCTRL[15], BUFGCTRL[16], BUFGCTRL[17], BUFGCTRL[18], BUFGCTRL[19], BUFGCTRL[20], BUFGCTRL[21], BUFGCTRL[22], BUFGCTRL[23], BUFGCTRL[24], BUFGCTRL[25], BUFGCTRL[26], BUFGCTRL[27], BUFGCTRL[28], BUFGCTRL[29], BUFGCTRL[30], BUFGCTRL[31], PS
CMT_FIFOCMT_FIFO_INT, IN_FIFO, OUT_FIFO
CFGCFG, SYSMONSYSMON_INT, BSCAN[0], BSCAN[1], BSCAN[2], BSCAN[3], ICAP[0], ICAP[1], STARTUP, CAPTURE, JTAGPPC, PMV_CFG[0], PMV_CFG[1], DCIRESET, FRAME_ECC, USR_ACCESS, KEY_CLEAR, EFUSE_USR, DNA_PORT, CFG_IO_ACCESS, PMVIOB_CFG, MISC_CFG, SYSMON
CLKCLK_DCM_S, CLK_DCM_N, CLK_IOB_S, CLK_IOB_N, HCLK_MGT_BUFCLK_INT
HROWCLK_HROW, CLK_TERM, HCLK_TERMHROW_INT
HCLKHCLKHCLK, GLOBALSIG, HCLK_DRP[0], HCLK_DRP[1]
HCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N, HCLK_DCM, HCLK_MGTPMVBRAM, HCLK_IO_INT, HCLK_CMT_DRP, BUFR[0], BUFR[1], BUFR[2], BUFR[3], BUFIO[0], BUFIO[1], BUFIO[2], BUFIO[3], IDELAYCTRL, DCI, BANK, LVDS
GLOBALGLOBALGLOBAL

Bel slots

virtex4 bel slots
SlotClassTile slotTiles
INTroutingINTINT
INTF_INTroutingINTFINTF
INTF_TESTMUXroutingINTFINTF
SPEC_INTroutingBELIO, DCM, CCM, MGT, CLK_BUFG
SLICE[0]SLICE_V4BELCLB
SLICE[1]SLICE_V4BELCLB
SLICE[2]SLICE_V4BELCLB
SLICE[3]SLICE_V4BELCLB
BRAMBRAM_V4BELBRAM
BRAM_FlegacyBEL
BRAM_H[0]legacyBEL
BRAM_H[1]legacyBEL
BRAM_ADDRlegacyBEL
DSP[0]DSP_V4BELDSP
DSP[1]DSP_V4BELDSP
DSP_CDSP_CBELDSP
ILOGIC[0]ILOGICBELIO
ILOGIC[1]ILOGICBELIO
OLOGIC[0]OLOGICBELIO
OLOGIC[1]OLOGICBELIO
IODELAY[0]IODELAY_V5BEL
IODELAY[1]IODELAY_V5BEL
IDELAY[0]IDELAYBEL
IDELAY[1]IDELAYBEL
ODELAY[0]ODELAYBEL
ODELAY[1]ODELAYBEL
IOB[0]IOBBELIO
IOB[1]IOBBELIO
DCM[0]DCM_V4BELDCM
DCM[1]DCM_V4BEL
PLL[0]PLL_V5BEL
PLL[1]PLL_V5BEL
PPR_FRAMEPPR_FRAMEBEL
PHASER_IN[0]PHASER_INBEL
PHASER_IN[1]PHASER_INBEL
PHASER_IN[2]PHASER_INBEL
PHASER_IN[3]PHASER_INBEL
PHASER_OUT[0]PHASER_OUTBEL
PHASER_OUT[1]PHASER_OUTBEL
PHASER_OUT[2]PHASER_OUTBEL
PHASER_OUT[3]PHASER_OUTBEL
PHASER_REFPHASER_REFBEL
PHY_CONTROLPHY_CONTROLBEL
BUFMRCE[0]BUFHCEBEL
BUFMRCE[1]BUFHCEBEL
CCMCCMBELCCM
PMCD[0]PMCDBELCCM
PMCD[1]PMCDBELCCM
DPMDPMBELCCM
BUFHCE_W[0]BUFHCEBEL
BUFHCE_W[1]BUFHCEBEL
BUFHCE_W[2]BUFHCEBEL
BUFHCE_W[3]BUFHCEBEL
BUFHCE_W[4]BUFHCEBEL
BUFHCE_W[5]BUFHCEBEL
BUFHCE_W[6]BUFHCEBEL
BUFHCE_W[7]BUFHCEBEL
BUFHCE_W[8]BUFHCEBEL
BUFHCE_W[9]BUFHCEBEL
BUFHCE_W[10]BUFHCEBEL
BUFHCE_W[11]BUFHCEBEL
BUFHCE_E[0]BUFHCEBEL
BUFHCE_E[1]BUFHCEBEL
BUFHCE_E[2]BUFHCEBEL
BUFHCE_E[3]BUFHCEBEL
BUFHCE_E[4]BUFHCEBEL
BUFHCE_E[5]BUFHCEBEL
BUFHCE_E[6]BUFHCEBEL
BUFHCE_E[7]BUFHCEBEL
BUFHCE_E[8]BUFHCEBEL
BUFHCE_E[9]BUFHCEBEL
BUFHCE_E[10]BUFHCEBEL
BUFHCE_E[11]BUFHCEBEL
PMV_CLKPMVBEL
PMVIOB_CLKPMVIOBBEL
PMV2PMV2BEL
PMV2_SVTPMV2BEL
MTBF2MTBF2BEL
PPCPPC405BELPPC
EMACEMAC_V4BELPPC
PCIEPCIE_V5BEL
PCIE3PCIE3BEL
GT11[0]GT11BELMGT
GT11[1]GT11BELMGT
GT11CLKGT11CLKBELMGT
GTP_DUALGTP_DUALBEL
GTX_DUALGTX_DUALBEL
HCLK_GTXHCLK_GTXBEL
GTCLK[0]GTCLKBEL
GTCLK[1]GTCLKBEL
GTX[0]GTXBEL
GTX[1]GTXBEL
GTX[2]GTXBEL
GTX[3]GTXBEL
GTH_QUADGTH_QUADBEL
HCLK_DRP_GTP_MIDHCLK_DRPBEL
GTP_COMMONGTP_COMMONBEL
GTX_COMMONGTX_COMMONBEL
GTP_CHANNELGTP_CHANNELBEL
GTX_CHANNELGTX_CHANNELBEL
CRC32[0]CRC32BEL
CRC32[1]CRC32BEL
CRC32[2]CRC32BEL
CRC32[3]CRC32BEL
BUFGCTRL[0]BUFGCTRLBELCLK_BUFG
BUFGCTRL[1]BUFGCTRLBELCLK_BUFG
BUFGCTRL[2]BUFGCTRLBELCLK_BUFG
BUFGCTRL[3]BUFGCTRLBELCLK_BUFG
BUFGCTRL[4]BUFGCTRLBELCLK_BUFG
BUFGCTRL[5]BUFGCTRLBELCLK_BUFG
BUFGCTRL[6]BUFGCTRLBELCLK_BUFG
BUFGCTRL[7]BUFGCTRLBELCLK_BUFG
BUFGCTRL[8]BUFGCTRLBELCLK_BUFG
BUFGCTRL[9]BUFGCTRLBELCLK_BUFG
BUFGCTRL[10]BUFGCTRLBELCLK_BUFG
BUFGCTRL[11]BUFGCTRLBELCLK_BUFG
BUFGCTRL[12]BUFGCTRLBELCLK_BUFG
BUFGCTRL[13]BUFGCTRLBELCLK_BUFG
BUFGCTRL[14]BUFGCTRLBELCLK_BUFG
BUFGCTRL[15]BUFGCTRLBELCLK_BUFG
BUFGCTRL[16]BUFGCTRLBELCLK_BUFG
BUFGCTRL[17]BUFGCTRLBELCLK_BUFG
BUFGCTRL[18]BUFGCTRLBELCLK_BUFG
BUFGCTRL[19]BUFGCTRLBELCLK_BUFG
BUFGCTRL[20]BUFGCTRLBELCLK_BUFG
BUFGCTRL[21]BUFGCTRLBELCLK_BUFG
BUFGCTRL[22]BUFGCTRLBELCLK_BUFG
BUFGCTRL[23]BUFGCTRLBELCLK_BUFG
BUFGCTRL[24]BUFGCTRLBELCLK_BUFG
BUFGCTRL[25]BUFGCTRLBELCLK_BUFG
BUFGCTRL[26]BUFGCTRLBELCLK_BUFG
BUFGCTRL[27]BUFGCTRLBELCLK_BUFG
BUFGCTRL[28]BUFGCTRLBELCLK_BUFG
BUFGCTRL[29]BUFGCTRLBELCLK_BUFG
BUFGCTRL[30]BUFGCTRLBELCLK_BUFG
BUFGCTRL[31]BUFGCTRLBELCLK_BUFG
PSPSBEL
CMT_FIFO_INTroutingCMT_FIFO
IN_FIFOIN_FIFOCMT_FIFO
OUT_FIFOOUT_FIFOCMT_FIFO
SYSMON_INTroutingCFGSYSMON
BSCAN[0]BSCANCFGCFG
BSCAN[1]BSCANCFGCFG
BSCAN[2]BSCANCFGCFG
BSCAN[3]BSCANCFGCFG
ICAP[0]ICAP_V4CFGCFG
ICAP[1]ICAP_V4CFGCFG
STARTUPSTARTUPCFGCFG
CAPTURECAPTURECFGCFG
JTAGPPCJTAGPPCCFGCFG
PMV_CFG[0]PMVCFGCFG
PMV_CFG[1]PMVCFG
DCIRESETDCIRESETCFGCFG
FRAME_ECCFRAME_ECC_V4CFGCFG
USR_ACCESSUSR_ACCESSCFGCFG
KEY_CLEARKEY_CLEARCFG
EFUSE_USREFUSE_USRCFG
DNA_PORTDNA_PORTCFG
CFG_IO_ACCESSCFG_IO_ACCESS_V6CFG
PMVIOB_CFGPMVIOBCFG
MISC_CFGMISC_CFGCFGCFG
SYSMONSYSMON_V4CFGSYSMON
CLK_INTroutingCLKCLK_DCM_S, CLK_DCM_N, CLK_IOB_S, CLK_IOB_N, HCLK_MGT_BUF
HROW_INTroutingHROWCLK_HROW, CLK_TERM, HCLK_TERM
HCLKroutingHCLKHCLK
GLOBALSIGGLOBALSIGHCLKHCLK
HCLK_DRP[0]HCLK_DRPHCLK
HCLK_DRP[1]HCLK_DRPHCLK
PMVBRAMPMVBRAM_V5HCLK_BEL
HCLK_IO_INTroutingHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N, HCLK_DCM, HCLK_MGT
HCLK_CMT_DRPHCLK_CMT_DRPHCLK_BEL
BUFR[0]BUFRHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS
BUFR[1]BUFRHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS
BUFR[2]BUFRHCLK_BEL
BUFR[3]BUFRHCLK_BEL
BUFIO[0]BUFIOHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N
BUFIO[1]BUFIOHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N
BUFIO[2]BUFIOHCLK_BEL
BUFIO[3]BUFIOHCLK_BEL
IDELAYCTRLIDELAYCTRLHCLK_BELHCLK_IO_DCI, HCLK_IO_LVDS, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N
DCIDCIHCLK_BELHCLK_IO_DCI, HCLK_IO_CENTER, HCLK_IO_CFG_N, HCLK_IO_DCM_S, HCLK_IO_DCM_N
BANKBANKHCLK_BEL
LVDSLVDS_V4HCLK_BELHCLK_IO_LVDS
GLOBALGLOBALGLOBALGLOBAL

Connector slots

virtex4 connector slots
SlotOppositeConnectors
WEPASS_W, TERM_W, CLB_BUFFER_W, PPC_W
EWPASS_E, TERM_E, CLB_BUFFER_E, PPC_E
SNPASS_S, TERM_S, BRKH_S, PPC_A_S, PPC_B_S
NSPASS_N, TERM_N, BRKH_N, PPC_A_N, PPC_B_N
IO_SIO_NIO_S
IO_NIO_SIO_N
CLK_PREVCLK_NEXTCLK_PREV
CLK_NEXTCLK_PREVCLK_NEXT
BEL_SBEL_NMGT_S
BEL_NBEL_SMGT_N
CMT_PREVCMT_NEXTCMT_PREV, CMT_PREV_CCM
CMT_NEXTCMT_PREVCMT_NEXT
HCLK_ROW_PREVHCLK_ROW_NEXT
HCLK_ROW_NEXTHCLK_ROW_PREV

Region slots

virtex4 region slots
SlotWires
GLOBALGCLK[0], GCLK[1], GCLK[2], GCLK[3], GCLK[4], GCLK[5], GCLK[6], GCLK[7], GCLK[8], GCLK[9], GCLK[10], GCLK[11], GCLK[12], GCLK[13], GCLK[14], GCLK[15], GCLK[16], GCLK[17], GCLK[18], GCLK[19], GCLK[20], GCLK[21], GCLK[22], GCLK[23], GCLK[24], GCLK[25], GCLK[26], GCLK[27], GCLK[28], GCLK[29], GCLK[30], GCLK[31]
GIOBGIOB[0], GIOB[1], GIOB[2], GIOB[3], GIOB[4], GIOB[5], GIOB[6], GIOB[7], GIOB[8], GIOB[9], GIOB[10], GIOB[11], GIOB[12], GIOB[13], GIOB[14], GIOB[15]
HROWHCLK_ROW[0], HCLK_ROW[1], HCLK_ROW[2], HCLK_ROW[3], HCLK_ROW[4], HCLK_ROW[5], HCLK_ROW[6], HCLK_ROW[7], RCLK_ROW[0], RCLK_ROW[1], MGT_ROW[0], MGT_ROW[1]
LEAFHCLK[0], HCLK[1], HCLK[2], HCLK[3], HCLK[4], HCLK[5], HCLK[6], HCLK[7], RCLK[0], RCLK[1], HCLK_IO[0], HCLK_IO[1], HCLK_IO[2], HCLK_IO[3], HCLK_IO[4], HCLK_IO[5], HCLK_IO[6], HCLK_IO[7], RCLK_IO[0], RCLK_IO[1], IOCLK[0], IOCLK[1], IOCLK_S_IO[0], IOCLK_S_IO[1], IOCLK_N_IO[0], IOCLK_N_IO[1]
LEAF_DCMHCLK_DCM[0], HCLK_DCM[1], HCLK_DCM[2], HCLK_DCM[3], HCLK_DCM[4], HCLK_DCM[5], HCLK_DCM[6], HCLK_DCM[7], GIOB_DCM[0], GIOB_DCM[1], GIOB_DCM[2], GIOB_DCM[3], GIOB_DCM[4], GIOB_DCM[5], GIOB_DCM[6], GIOB_DCM[7], GIOB_DCM[8], GIOB_DCM[9], GIOB_DCM[10], GIOB_DCM[11], GIOB_DCM[12], GIOB_DCM[13], GIOB_DCM[14], GIOB_DCM[15], MGT_DCM[0], MGT_DCM[1], MGT_DCM[2], MGT_DCM[3]

Wires

virtex4 wires
WireKind
PULLUPpullup
TIE_0tie 0
TIE_1tie 1
HCLK[0]regional LEAF
HCLK[1]regional LEAF
HCLK[2]regional LEAF
HCLK[3]regional LEAF
HCLK[4]regional LEAF
HCLK[5]regional LEAF
HCLK[6]regional LEAF
HCLK[7]regional LEAF
RCLK[0]regional LEAF
RCLK[1]regional LEAF
OMUX[0]mux
OMUX[1]mux
OMUX[2]mux
OMUX[3]mux
OMUX[4]mux
OMUX[5]mux
OMUX[6]mux
OMUX[7]mux
OMUX[8]mux
OMUX[9]mux
OMUX[10]mux
OMUX[11]mux
OMUX[12]mux
OMUX[13]mux
OMUX[14]mux
OMUX[15]mux
OMUX_S0branch N
OMUX_S0_ALTbranch N
OMUX_W1branch E
OMUX_WS1branch N
OMUX_E2branch W
OMUX_S2branch N
OMUX_S3branch N
OMUX_SE3branch W
OMUX_S4branch N
OMUX_S5branch N
OMUX_SW5branch E
OMUX_W6branch E
OMUX_E7branch W
OMUX_ES7branch N
OMUX_E8branch W
OMUX_EN8branch S
OMUX_W9branch E
OMUX_N10branch S
OMUX_NW10branch E
OMUX_N11branch S
OMUX_N12branch S
OMUX_NE12branch W
OMUX_E13branch W
OMUX_N13branch S
OMUX_W14branch E
OMUX_WN14branch S
OMUX_N15branch S
DBL_W0[0]mux
DBL_W0[1]mux
DBL_W0[2]mux
DBL_W0[3]mux
DBL_W0[4]mux
DBL_W0[5]mux
DBL_W0[6]mux
DBL_W0[7]mux
DBL_W0[8]mux
DBL_W0[9]mux
DBL_W1[0]branch E
DBL_W1[1]branch E
DBL_W1[2]branch E
DBL_W1[3]branch E
DBL_W1[4]branch E
DBL_W1[5]branch E
DBL_W1[6]branch E
DBL_W1[7]branch E
DBL_W1[8]branch E
DBL_W1[9]branch E
DBL_W2[0]branch E
DBL_W2[1]branch E
DBL_W2[2]branch E
DBL_W2[3]branch E
DBL_W2[4]branch E
DBL_W2[5]branch E
DBL_W2[6]branch E
DBL_W2[7]branch E
DBL_W2[8]branch E
DBL_W2[9]branch E
DBL_W2_N[0]branch S
DBL_W2_N[1]branch S
DBL_W2_N[2]branch S
DBL_W2_N[3]branch S
DBL_W2_N[4]branch S
DBL_W2_N[5]branch S
DBL_W2_N[6]branch S
DBL_W2_N[7]branch S
DBL_W2_N[8]branch S
DBL_W2_N[9]branch S
DBL_E0[0]mux
DBL_E0[1]mux
DBL_E0[2]mux
DBL_E0[3]mux
DBL_E0[4]mux
DBL_E0[5]mux
DBL_E0[6]mux
DBL_E0[7]mux
DBL_E0[8]mux
DBL_E0[9]mux
DBL_E1[0]branch W
DBL_E1[1]branch W
DBL_E1[2]branch W
DBL_E1[3]branch W
DBL_E1[4]branch W
DBL_E1[5]branch W
DBL_E1[6]branch W
DBL_E1[7]branch W
DBL_E1[8]branch W
DBL_E1[9]branch W
DBL_E2[0]branch W
DBL_E2[1]branch W
DBL_E2[2]branch W
DBL_E2[3]branch W
DBL_E2[4]branch W
DBL_E2[5]branch W
DBL_E2[6]branch W
DBL_E2[7]branch W
DBL_E2[8]branch W
DBL_E2[9]branch W
DBL_E2_S[0]branch N
DBL_E2_S[1]branch N
DBL_E2_S[2]branch N
DBL_E2_S[3]branch N
DBL_E2_S[4]branch N
DBL_E2_S[5]branch N
DBL_E2_S[6]branch N
DBL_E2_S[7]branch N
DBL_E2_S[8]branch N
DBL_E2_S[9]branch N
DBL_S0[0]mux
DBL_S0[1]mux
DBL_S0[2]mux
DBL_S0[3]mux
DBL_S0[4]mux
DBL_S0[5]mux
DBL_S0[6]mux
DBL_S0[7]mux
DBL_S0[8]mux
DBL_S0[9]mux
DBL_S1[0]branch N
DBL_S1[1]branch N
DBL_S1[2]branch N
DBL_S1[3]branch N
DBL_S1[4]branch N
DBL_S1[5]branch N
DBL_S1[6]branch N
DBL_S1[7]branch N
DBL_S1[8]branch N
DBL_S1[9]branch N
DBL_S2[0]branch N
DBL_S2[1]branch N
DBL_S2[2]branch N
DBL_S2[3]branch N
DBL_S2[4]branch N
DBL_S2[5]branch N
DBL_S2[6]branch N
DBL_S2[7]branch N
DBL_S2[8]branch N
DBL_S2[9]branch N
DBL_S3[0]branch N
DBL_S3[1]branch N
DBL_S3[2]branch N
DBL_S3[3]branch N
DBL_S3[4]branch N
DBL_S3[5]branch N
DBL_S3[6]branch N
DBL_S3[7]branch N
DBL_S3[8]branch N
DBL_S3[9]branch N
DBL_N0[0]mux
DBL_N0[1]mux
DBL_N0[2]mux
DBL_N0[3]mux
DBL_N0[4]mux
DBL_N0[5]mux
DBL_N0[6]mux
DBL_N0[7]mux
DBL_N0[8]mux
DBL_N0[9]mux
DBL_N1[0]branch S
DBL_N1[1]branch S
DBL_N1[2]branch S
DBL_N1[3]branch S
DBL_N1[4]branch S
DBL_N1[5]branch S
DBL_N1[6]branch S
DBL_N1[7]branch S
DBL_N1[8]branch S
DBL_N1[9]branch S
DBL_N2[0]branch S
DBL_N2[1]branch S
DBL_N2[2]branch S
DBL_N2[3]branch S
DBL_N2[4]branch S
DBL_N2[5]branch S
DBL_N2[6]branch S
DBL_N2[7]branch S
DBL_N2[8]branch S
DBL_N2[9]branch S
DBL_N3[0]branch S
DBL_N3[1]branch S
DBL_N3[2]branch S
DBL_N3[3]branch S
DBL_N3[4]branch S
DBL_N3[5]branch S
DBL_N3[6]branch S
DBL_N3[7]branch S
DBL_N3[8]branch S
DBL_N3[9]branch S
HEX_W0[0]mux
HEX_W0[1]mux
HEX_W0[2]mux
HEX_W0[3]mux
HEX_W0[4]mux
HEX_W0[5]mux
HEX_W0[6]mux
HEX_W0[7]mux
HEX_W0[8]mux
HEX_W0[9]mux
HEX_W1[0]branch E
HEX_W1[1]branch E
HEX_W1[2]branch E
HEX_W1[3]branch E
HEX_W1[4]branch E
HEX_W1[5]branch E
HEX_W1[6]branch E
HEX_W1[7]branch E
HEX_W1[8]branch E
HEX_W1[9]branch E
HEX_W2[0]branch E
HEX_W2[1]branch E
HEX_W2[2]branch E
HEX_W2[3]branch E
HEX_W2[4]branch E
HEX_W2[5]branch E
HEX_W2[6]branch E
HEX_W2[7]branch E
HEX_W2[8]branch E
HEX_W2[9]branch E
HEX_W3[0]branch E
HEX_W3[1]branch E
HEX_W3[2]branch E
HEX_W3[3]branch E
HEX_W3[4]branch E
HEX_W3[5]branch E
HEX_W3[6]branch E
HEX_W3[7]branch E
HEX_W3[8]branch E
HEX_W3[9]branch E
HEX_W4[0]branch E
HEX_W4[1]branch E
HEX_W4[2]branch E
HEX_W4[3]branch E
HEX_W4[4]branch E
HEX_W4[5]branch E
HEX_W4[6]branch E
HEX_W4[7]branch E
HEX_W4[8]branch E
HEX_W4[9]branch E
HEX_W5[0]branch E
HEX_W5[1]branch E
HEX_W5[2]branch E
HEX_W5[3]branch E
HEX_W5[4]branch E
HEX_W5[5]branch E
HEX_W5[6]branch E
HEX_W5[7]branch E
HEX_W5[8]branch E
HEX_W5[9]branch E
HEX_W6[0]branch E
HEX_W6[1]branch E
HEX_W6[2]branch E
HEX_W6[3]branch E
HEX_W6[4]branch E
HEX_W6[5]branch E
HEX_W6[6]branch E
HEX_W6[7]branch E
HEX_W6[8]branch E
HEX_W6[9]branch E
HEX_W6_N[0]branch S
HEX_W6_N[1]branch S
HEX_W6_N[2]branch S
HEX_W6_N[3]branch S
HEX_W6_N[4]branch S
HEX_W6_N[5]branch S
HEX_W6_N[6]branch S
HEX_W6_N[7]branch S
HEX_W6_N[8]branch S
HEX_W6_N[9]branch S
HEX_E0[0]mux
HEX_E0[1]mux
HEX_E0[2]mux
HEX_E0[3]mux
HEX_E0[4]mux
HEX_E0[5]mux
HEX_E0[6]mux
HEX_E0[7]mux
HEX_E0[8]mux
HEX_E0[9]mux
HEX_E1[0]branch W
HEX_E1[1]branch W
HEX_E1[2]branch W
HEX_E1[3]branch W
HEX_E1[4]branch W
HEX_E1[5]branch W
HEX_E1[6]branch W
HEX_E1[7]branch W
HEX_E1[8]branch W
HEX_E1[9]branch W
HEX_E2[0]branch W
HEX_E2[1]branch W
HEX_E2[2]branch W
HEX_E2[3]branch W
HEX_E2[4]branch W
HEX_E2[5]branch W
HEX_E2[6]branch W
HEX_E2[7]branch W
HEX_E2[8]branch W
HEX_E2[9]branch W
HEX_E3[0]branch W
HEX_E3[1]branch W
HEX_E3[2]branch W
HEX_E3[3]branch W
HEX_E3[4]branch W
HEX_E3[5]branch W
HEX_E3[6]branch W
HEX_E3[7]branch W
HEX_E3[8]branch W
HEX_E3[9]branch W
HEX_E4[0]branch W
HEX_E4[1]branch W
HEX_E4[2]branch W
HEX_E4[3]branch W
HEX_E4[4]branch W
HEX_E4[5]branch W
HEX_E4[6]branch W
HEX_E4[7]branch W
HEX_E4[8]branch W
HEX_E4[9]branch W
HEX_E5[0]branch W
HEX_E5[1]branch W
HEX_E5[2]branch W
HEX_E5[3]branch W
HEX_E5[4]branch W
HEX_E5[5]branch W
HEX_E5[6]branch W
HEX_E5[7]branch W
HEX_E5[8]branch W
HEX_E5[9]branch W
HEX_E6[0]branch W
HEX_E6[1]branch W
HEX_E6[2]branch W
HEX_E6[3]branch W
HEX_E6[4]branch W
HEX_E6[5]branch W
HEX_E6[6]branch W
HEX_E6[7]branch W
HEX_E6[8]branch W
HEX_E6[9]branch W
HEX_E6_S[0]branch N
HEX_E6_S[1]branch N
HEX_E6_S[2]branch N
HEX_E6_S[3]branch N
HEX_E6_S[4]branch N
HEX_E6_S[5]branch N
HEX_E6_S[6]branch N
HEX_E6_S[7]branch N
HEX_E6_S[8]branch N
HEX_E6_S[9]branch N
HEX_S0[0]mux
HEX_S0[1]mux
HEX_S0[2]mux
HEX_S0[3]mux
HEX_S0[4]mux
HEX_S0[5]mux
HEX_S0[6]mux
HEX_S0[7]mux
HEX_S0[8]mux
HEX_S0[9]mux
HEX_S1[0]branch N
HEX_S1[1]branch N
HEX_S1[2]branch N
HEX_S1[3]branch N
HEX_S1[4]branch N
HEX_S1[5]branch N
HEX_S1[6]branch N
HEX_S1[7]branch N
HEX_S1[8]branch N
HEX_S1[9]branch N
HEX_S2[0]branch N
HEX_S2[1]branch N
HEX_S2[2]branch N
HEX_S2[3]branch N
HEX_S2[4]branch N
HEX_S2[5]branch N
HEX_S2[6]branch N
HEX_S2[7]branch N
HEX_S2[8]branch N
HEX_S2[9]branch N
HEX_S3[0]branch N
HEX_S3[1]branch N
HEX_S3[2]branch N
HEX_S3[3]branch N
HEX_S3[4]branch N
HEX_S3[5]branch N
HEX_S3[6]branch N
HEX_S3[7]branch N
HEX_S3[8]branch N
HEX_S3[9]branch N
HEX_S4[0]branch N
HEX_S4[1]branch N
HEX_S4[2]branch N
HEX_S4[3]branch N
HEX_S4[4]branch N
HEX_S4[5]branch N
HEX_S4[6]branch N
HEX_S4[7]branch N
HEX_S4[8]branch N
HEX_S4[9]branch N
HEX_S5[0]branch N
HEX_S5[1]branch N
HEX_S5[2]branch N
HEX_S5[3]branch N
HEX_S5[4]branch N
HEX_S5[5]branch N
HEX_S5[6]branch N
HEX_S5[7]branch N
HEX_S5[8]branch N
HEX_S5[9]branch N
HEX_S6[0]branch N
HEX_S6[1]branch N
HEX_S6[2]branch N
HEX_S6[3]branch N
HEX_S6[4]branch N
HEX_S6[5]branch N
HEX_S6[6]branch N
HEX_S6[7]branch N
HEX_S6[8]branch N
HEX_S6[9]branch N
HEX_S7[0]branch N
HEX_S7[1]branch N
HEX_S7[2]branch N
HEX_S7[3]branch N
HEX_S7[4]branch N
HEX_S7[5]branch N
HEX_S7[6]branch N
HEX_S7[7]branch N
HEX_S7[8]branch N
HEX_S7[9]branch N
HEX_N0[0]mux
HEX_N0[1]mux
HEX_N0[2]mux
HEX_N0[3]mux
HEX_N0[4]mux
HEX_N0[5]mux
HEX_N0[6]mux
HEX_N0[7]mux
HEX_N0[8]mux
HEX_N0[9]mux
HEX_N1[0]branch S
HEX_N1[1]branch S
HEX_N1[2]branch S
HEX_N1[3]branch S
HEX_N1[4]branch S
HEX_N1[5]branch S
HEX_N1[6]branch S
HEX_N1[7]branch S
HEX_N1[8]branch S
HEX_N1[9]branch S
HEX_N2[0]branch S
HEX_N2[1]branch S
HEX_N2[2]branch S
HEX_N2[3]branch S
HEX_N2[4]branch S
HEX_N2[5]branch S
HEX_N2[6]branch S
HEX_N2[7]branch S
HEX_N2[8]branch S
HEX_N2[9]branch S
HEX_N3[0]branch S
HEX_N3[1]branch S
HEX_N3[2]branch S
HEX_N3[3]branch S
HEX_N3[4]branch S
HEX_N3[5]branch S
HEX_N3[6]branch S
HEX_N3[7]branch S
HEX_N3[8]branch S
HEX_N3[9]branch S
HEX_N4[0]branch S
HEX_N4[1]branch S
HEX_N4[2]branch S
HEX_N4[3]branch S
HEX_N4[4]branch S
HEX_N4[5]branch S
HEX_N4[6]branch S
HEX_N4[7]branch S
HEX_N4[8]branch S
HEX_N4[9]branch S
HEX_N5[0]branch S
HEX_N5[1]branch S
HEX_N5[2]branch S
HEX_N5[3]branch S
HEX_N5[4]branch S
HEX_N5[5]branch S
HEX_N5[6]branch S
HEX_N5[7]branch S
HEX_N5[8]branch S
HEX_N5[9]branch S
HEX_N6[0]branch S
HEX_N6[1]branch S
HEX_N6[2]branch S
HEX_N6[3]branch S
HEX_N6[4]branch S
HEX_N6[5]branch S
HEX_N6[6]branch S
HEX_N6[7]branch S
HEX_N6[8]branch S
HEX_N6[9]branch S
HEX_N7[0]branch S
HEX_N7[1]branch S
HEX_N7[2]branch S
HEX_N7[3]branch S
HEX_N7[4]branch S
HEX_N7[5]branch S
HEX_N7[6]branch S
HEX_N7[7]branch S
HEX_N7[8]branch S
HEX_N7[9]branch S
LH[0]multi_branch W
LH[1]multi_branch W
LH[2]multi_branch W
LH[3]multi_branch W
LH[4]multi_branch W
LH[5]multi_branch W
LH[6]multi_branch W
LH[7]multi_branch W
LH[8]multi_branch W
LH[9]multi_branch W
LH[10]multi_branch W
LH[11]multi_branch W
LH[12]multi_root
LH[13]multi_branch E
LH[14]multi_branch E
LH[15]multi_branch E
LH[16]multi_branch E
LH[17]multi_branch E
LH[18]multi_branch E
LH[19]multi_branch E
LH[20]multi_branch E
LH[21]multi_branch E
LH[22]multi_branch E
LH[23]multi_branch E
LH[24]multi_branch E
LV[0]multi_branch S
LV[1]multi_branch S
LV[2]multi_branch S
LV[3]multi_branch S
LV[4]multi_branch S
LV[5]multi_branch S
LV[6]multi_branch S
LV[7]multi_branch S
LV[8]multi_branch S
LV[9]multi_branch S
LV[10]multi_branch S
LV[11]multi_branch S
LV[12]multi_root
LV[13]multi_branch N
LV[14]multi_branch N
LV[15]multi_branch N
LV[16]multi_branch N
LV[17]multi_branch N
LV[18]multi_branch N
LV[19]multi_branch N
LV[20]multi_branch N
LV[21]multi_branch N
LV[22]multi_branch N
LV[23]multi_branch N
LV[24]multi_branch N
IMUX_SR[0]mux
IMUX_SR[1]mux
IMUX_SR[2]mux
IMUX_SR[3]mux
IMUX_SR_OPTINV[0]mux
IMUX_SR_OPTINV[1]mux
IMUX_SR_OPTINV[2]mux
IMUX_SR_OPTINV[3]mux
IMUX_BOUNCE[0]mux
IMUX_BOUNCE[1]mux
IMUX_BOUNCE[2]mux
IMUX_BOUNCE[3]mux
IMUX_CLK[0]mux
IMUX_CLK[1]mux
IMUX_CLK[2]mux
IMUX_CLK[3]mux
IMUX_CLK_OPTINV[0]mux
IMUX_CLK_OPTINV[1]mux
IMUX_CLK_OPTINV[2]mux
IMUX_CLK_OPTINV[3]mux
IMUX_CE[0]mux
IMUX_CE[1]mux
IMUX_CE[2]mux
IMUX_CE[3]mux
IMUX_CE_OPTINV[0]mux
IMUX_CE_OPTINV[1]mux
IMUX_CE_OPTINV[2]mux
IMUX_CE_OPTINV[3]mux
IMUX_BYP[0]mux
IMUX_BYP[1]mux
IMUX_BYP[2]mux
IMUX_BYP[3]mux
IMUX_BYP[4]mux
IMUX_BYP[5]mux
IMUX_BYP[6]mux
IMUX_BYP[7]mux
IMUX_BYP_BOUNCE[0]mux
IMUX_BYP_BOUNCE[1]mux
IMUX_BYP_BOUNCE[2]mux
IMUX_BYP_BOUNCE[3]mux
IMUX_BYP_BOUNCE[4]mux
IMUX_BYP_BOUNCE[5]mux
IMUX_BYP_BOUNCE[6]mux
IMUX_BYP_BOUNCE[7]mux
IMUX_IMUX[0]mux
IMUX_IMUX[1]mux
IMUX_IMUX[2]mux
IMUX_IMUX[3]mux
IMUX_IMUX[4]mux
IMUX_IMUX[5]mux
IMUX_IMUX[6]mux
IMUX_IMUX[7]mux
IMUX_IMUX[8]mux
IMUX_IMUX[9]mux
IMUX_IMUX[10]mux
IMUX_IMUX[11]mux
IMUX_IMUX[12]mux
IMUX_IMUX[13]mux
IMUX_IMUX[14]mux
IMUX_IMUX[15]mux
IMUX_IMUX[16]mux
IMUX_IMUX[17]mux
IMUX_IMUX[18]mux
IMUX_IMUX[19]mux
IMUX_IMUX[20]mux
IMUX_IMUX[21]mux
IMUX_IMUX[22]mux
IMUX_IMUX[23]mux
IMUX_IMUX[24]mux
IMUX_IMUX[25]mux
IMUX_IMUX[26]mux
IMUX_IMUX[27]mux
IMUX_IMUX[28]mux
IMUX_IMUX[29]mux
IMUX_IMUX[30]mux
IMUX_IMUX[31]mux
OUT_BEST[0]bel
OUT_BEST[1]bel
OUT_BEST[2]bel
OUT_BEST[3]bel
OUT_BEST[4]bel
OUT_BEST[5]bel
OUT_BEST[6]bel
OUT_BEST[7]bel
OUT_BEST_TMIN[0]bel
OUT_BEST_TMIN[1]bel
OUT_BEST_TMIN[2]bel
OUT_BEST_TMIN[3]bel
OUT_BEST_TMIN[4]bel
OUT_BEST_TMIN[5]bel
OUT_BEST_TMIN[6]bel
OUT_BEST_TMIN[7]bel
OUT_SEC[0]bel
OUT_SEC[1]bel
OUT_SEC[2]bel
OUT_SEC[3]bel
OUT_SEC[4]bel
OUT_SEC[5]bel
OUT_SEC[6]bel
OUT_SEC[7]bel
OUT_SEC_TMIN[0]bel
OUT_SEC_TMIN[1]bel
OUT_SEC_TMIN[2]bel
OUT_SEC_TMIN[3]bel
OUT_SEC_TMIN[4]bel
OUT_SEC_TMIN[5]bel
OUT_SEC_TMIN[6]bel
OUT_SEC_TMIN[7]bel
OUT_HALF0[0]bel
OUT_HALF0[1]bel
OUT_HALF0[2]bel
OUT_HALF0[3]bel
OUT_HALF0[4]bel
OUT_HALF0[5]bel
OUT_HALF0[6]bel
OUT_HALF0[7]bel
OUT_HALF0_BEL[0]bel
OUT_HALF0_BEL[1]bel
OUT_HALF0_BEL[2]bel
OUT_HALF0_BEL[3]bel
OUT_HALF0_BEL[4]bel
OUT_HALF0_BEL[5]bel
OUT_HALF0_BEL[6]bel
OUT_HALF0_BEL[7]bel
OUT_HALF0_TEST[0]test
OUT_HALF0_TEST[1]test
OUT_HALF0_TEST[2]test
OUT_HALF0_TEST[3]test
OUT_HALF0_TEST[4]test
OUT_HALF0_TEST[5]test
OUT_HALF0_TEST[6]test
OUT_HALF0_TEST[7]test
OUT_HALF1[0]bel
OUT_HALF1[1]bel
OUT_HALF1[2]bel
OUT_HALF1[3]bel
OUT_HALF1[4]bel
OUT_HALF1[5]bel
OUT_HALF1[6]bel
OUT_HALF1[7]bel
OUT_HALF1_BEL[0]bel
OUT_HALF1_BEL[1]bel
OUT_HALF1_BEL[2]bel
OUT_HALF1_BEL[3]bel
OUT_HALF1_BEL[4]bel
OUT_HALF1_BEL[5]bel
OUT_HALF1_BEL[6]bel
OUT_HALF1_BEL[7]bel
OUT_HALF1_TEST[0]test
OUT_HALF1_TEST[1]test
OUT_HALF1_TEST[2]test
OUT_HALF1_TEST[3]test
OUT_HALF1_TEST[4]test
OUT_HALF1_TEST[5]test
OUT_HALF1_TEST[6]test
OUT_HALF1_TEST[7]test
IMUX_SPEC[0]test
IMUX_SPEC[1]test
IMUX_SPEC[2]test
IMUX_SPEC[3]test
HCLK_ROW[0]regional HROW
HCLK_ROW[1]regional HROW
HCLK_ROW[2]regional HROW
HCLK_ROW[3]regional HROW
HCLK_ROW[4]regional HROW
HCLK_ROW[5]regional HROW
HCLK_ROW[6]regional HROW
HCLK_ROW[7]regional HROW
RCLK_ROW[0]regional HROW
RCLK_ROW[1]regional HROW
MGT_ROW[0]regional HROW
MGT_ROW[1]regional HROW
OUT_BUFG[0]bel
OUT_BUFG[1]bel
OUT_BUFG[2]bel
OUT_BUFG[3]bel
OUT_BUFG[4]bel
OUT_BUFG[5]bel
OUT_BUFG[6]bel
OUT_BUFG[7]bel
OUT_BUFG[8]bel
OUT_BUFG[9]bel
OUT_BUFG[10]bel
OUT_BUFG[11]bel
OUT_BUFG[12]bel
OUT_BUFG[13]bel
OUT_BUFG[14]bel
OUT_BUFG[15]bel
OUT_BUFG[16]bel
OUT_BUFG[17]bel
OUT_BUFG[18]bel
OUT_BUFG[19]bel
OUT_BUFG[20]bel
OUT_BUFG[21]bel
OUT_BUFG[22]bel
OUT_BUFG[23]bel
OUT_BUFG[24]bel
OUT_BUFG[25]bel
OUT_BUFG[26]bel
OUT_BUFG[27]bel
OUT_BUFG[28]bel
OUT_BUFG[29]bel
OUT_BUFG[30]bel
OUT_BUFG[31]bel
GCLK[0]regional GLOBAL
GCLK[1]regional GLOBAL
GCLK[2]regional GLOBAL
GCLK[3]regional GLOBAL
GCLK[4]regional GLOBAL
GCLK[5]regional GLOBAL
GCLK[6]regional GLOBAL
GCLK[7]regional GLOBAL
GCLK[8]regional GLOBAL
GCLK[9]regional GLOBAL
GCLK[10]regional GLOBAL
GCLK[11]regional GLOBAL
GCLK[12]regional GLOBAL
GCLK[13]regional GLOBAL
GCLK[14]regional GLOBAL
GCLK[15]regional GLOBAL
GCLK[16]regional GLOBAL
GCLK[17]regional GLOBAL
GCLK[18]regional GLOBAL
GCLK[19]regional GLOBAL
GCLK[20]regional GLOBAL
GCLK[21]regional GLOBAL
GCLK[22]regional GLOBAL
GCLK[23]regional GLOBAL
GCLK[24]regional GLOBAL
GCLK[25]regional GLOBAL
GCLK[26]regional GLOBAL
GCLK[27]regional GLOBAL
GCLK[28]regional GLOBAL
GCLK[29]regional GLOBAL
GCLK[30]regional GLOBAL
GCLK[31]regional GLOBAL
GCLK_BUF[0]mux
GCLK_BUF[1]mux
GCLK_BUF[2]mux
GCLK_BUF[3]mux
GCLK_BUF[4]mux
GCLK_BUF[5]mux
GCLK_BUF[6]mux
GCLK_BUF[7]mux
GCLK_BUF[8]mux
GCLK_BUF[9]mux
GCLK_BUF[10]mux
GCLK_BUF[11]mux
GCLK_BUF[12]mux
GCLK_BUF[13]mux
GCLK_BUF[14]mux
GCLK_BUF[15]mux
GCLK_BUF[16]mux
GCLK_BUF[17]mux
GCLK_BUF[18]mux
GCLK_BUF[19]mux
GCLK_BUF[20]mux
GCLK_BUF[21]mux
GCLK_BUF[22]mux
GCLK_BUF[23]mux
GCLK_BUF[24]mux
GCLK_BUF[25]mux
GCLK_BUF[26]mux
GCLK_BUF[27]mux
GCLK_BUF[28]mux
GCLK_BUF[29]mux
GCLK_BUF[30]mux
GCLK_BUF[31]mux
GIOB[0]regional GIOB
GIOB[1]regional GIOB
GIOB[2]regional GIOB
GIOB[3]regional GIOB
GIOB[4]regional GIOB
GIOB[5]regional GIOB
GIOB[6]regional GIOB
GIOB[7]regional GIOB
GIOB[8]regional GIOB
GIOB[9]regional GIOB
GIOB[10]regional GIOB
GIOB[11]regional GIOB
GIOB[12]regional GIOB
GIOB[13]regional GIOB
GIOB[14]regional GIOB
GIOB[15]regional GIOB
IMUX_BUFG_O[0]mux
IMUX_BUFG_O[1]mux
IMUX_BUFG_O[2]mux
IMUX_BUFG_O[3]mux
IMUX_BUFG_O[4]mux
IMUX_BUFG_O[5]mux
IMUX_BUFG_O[6]mux
IMUX_BUFG_O[7]mux
IMUX_BUFG_O[8]mux
IMUX_BUFG_O[9]mux
IMUX_BUFG_O[10]mux
IMUX_BUFG_O[11]mux
IMUX_BUFG_O[12]mux
IMUX_BUFG_O[13]mux
IMUX_BUFG_O[14]mux
IMUX_BUFG_O[15]mux
IMUX_BUFG_O[16]mux
IMUX_BUFG_O[17]mux
IMUX_BUFG_O[18]mux
IMUX_BUFG_O[19]mux
IMUX_BUFG_O[20]mux
IMUX_BUFG_O[21]mux
IMUX_BUFG_O[22]mux
IMUX_BUFG_O[23]mux
IMUX_BUFG_O[24]mux
IMUX_BUFG_O[25]mux
IMUX_BUFG_O[26]mux
IMUX_BUFG_O[27]mux
IMUX_BUFG_O[28]mux
IMUX_BUFG_O[29]mux
IMUX_BUFG_O[30]mux
IMUX_BUFG_O[31]mux
IMUX_BUFG_I[0]branch CLK_PREV
IMUX_BUFG_I[1]branch CLK_PREV
IMUX_BUFG_I[2]branch CLK_PREV
IMUX_BUFG_I[3]branch CLK_PREV
IMUX_BUFG_I[4]branch CLK_PREV
IMUX_BUFG_I[5]branch CLK_PREV
IMUX_BUFG_I[6]branch CLK_PREV
IMUX_BUFG_I[7]branch CLK_PREV
IMUX_BUFG_I[8]branch CLK_PREV
IMUX_BUFG_I[9]branch CLK_PREV
IMUX_BUFG_I[10]branch CLK_PREV
IMUX_BUFG_I[11]branch CLK_PREV
IMUX_BUFG_I[12]branch CLK_PREV
IMUX_BUFG_I[13]branch CLK_PREV
IMUX_BUFG_I[14]branch CLK_PREV
IMUX_BUFG_I[15]branch CLK_PREV
IMUX_BUFG_I[16]branch CLK_PREV
IMUX_BUFG_I[17]branch CLK_PREV
IMUX_BUFG_I[18]branch CLK_PREV
IMUX_BUFG_I[19]branch CLK_PREV
IMUX_BUFG_I[20]branch CLK_PREV
IMUX_BUFG_I[21]branch CLK_PREV
IMUX_BUFG_I[22]branch CLK_PREV
IMUX_BUFG_I[23]branch CLK_PREV
IMUX_BUFG_I[24]branch CLK_PREV
IMUX_BUFG_I[25]branch CLK_PREV
IMUX_BUFG_I[26]branch CLK_PREV
IMUX_BUFG_I[27]branch CLK_PREV
IMUX_BUFG_I[28]branch CLK_PREV
IMUX_BUFG_I[29]branch CLK_PREV
IMUX_BUFG_I[30]branch CLK_PREV
IMUX_BUFG_I[31]branch CLK_PREV
OUT_CLKPADbel
HCLK_IO[0]regional LEAF
HCLK_IO[1]regional LEAF
HCLK_IO[2]regional LEAF
HCLK_IO[3]regional LEAF
HCLK_IO[4]regional LEAF
HCLK_IO[5]regional LEAF
HCLK_IO[6]regional LEAF
HCLK_IO[7]regional LEAF
RCLK_IO[0]regional LEAF
RCLK_IO[1]regional LEAF
IMUX_IDELAYCTRL_REFCLKmux
IMUX_BUFR[0]mux
IMUX_BUFR[1]mux
IOCLK[0]regional LEAF
IOCLK[1]regional LEAF
IOCLK_S[0]branch IO_N
IOCLK_S[1]branch IO_N
IOCLK_N[0]branch IO_S
IOCLK_N[1]branch IO_S
IOCLK_S_IO[0]regional LEAF
IOCLK_S_IO[1]regional LEAF
IOCLK_N_IO[0]regional LEAF
IOCLK_N_IO[1]regional LEAF
VRCLK[0]mux
VRCLK[1]mux
VRCLK_S[0]branch IO_N
VRCLK_S[1]branch IO_N
VRCLK_N[0]branch IO_S
VRCLK_N[1]branch IO_S
HCLK_DCM[0]regional LEAF_DCM
HCLK_DCM[1]regional LEAF_DCM
HCLK_DCM[2]regional LEAF_DCM
HCLK_DCM[3]regional LEAF_DCM
HCLK_DCM[4]regional LEAF_DCM
HCLK_DCM[5]regional LEAF_DCM
HCLK_DCM[6]regional LEAF_DCM
HCLK_DCM[7]regional LEAF_DCM
GIOB_DCM[0]regional LEAF_DCM
GIOB_DCM[1]regional LEAF_DCM
GIOB_DCM[2]regional LEAF_DCM
GIOB_DCM[3]regional LEAF_DCM
GIOB_DCM[4]regional LEAF_DCM
GIOB_DCM[5]regional LEAF_DCM
GIOB_DCM[6]regional LEAF_DCM
GIOB_DCM[7]regional LEAF_DCM
GIOB_DCM[8]regional LEAF_DCM
GIOB_DCM[9]regional LEAF_DCM
GIOB_DCM[10]regional LEAF_DCM
GIOB_DCM[11]regional LEAF_DCM
GIOB_DCM[12]regional LEAF_DCM
GIOB_DCM[13]regional LEAF_DCM
GIOB_DCM[14]regional LEAF_DCM
GIOB_DCM[15]regional LEAF_DCM
MGT_DCM[0]regional LEAF_DCM
MGT_DCM[1]regional LEAF_DCM
MGT_DCM[2]regional LEAF_DCM
MGT_DCM[3]regional LEAF_DCM
OUT_DCM[0]mux
OUT_DCM[1]mux
OUT_DCM[2]mux
OUT_DCM[3]mux
OUT_DCM[4]mux
OUT_DCM[5]mux
OUT_DCM[6]mux
OUT_DCM[7]mux
OUT_DCM[8]mux
OUT_DCM[9]mux
OUT_DCM[10]mux
OUT_DCM[11]mux
IMUX_CCM_REL[0]mux
IMUX_CCM_REL[1]mux
OUT_CCM_CLKA1[0]bel
OUT_CCM_CLKA1[1]bel
OUT_CCM_CLKA1D2[0]bel
OUT_CCM_CLKA1D2[1]bel
OUT_CCM_CLKA1D4[0]bel
OUT_CCM_CLKA1D4[1]bel
OUT_CCM_CLKA1D8[0]bel
OUT_CCM_CLKA1D8[1]bel
OUT_CCM_CLKB1[0]bel
OUT_CCM_CLKB1[1]bel
OUT_CCM_CLKC1[0]bel
OUT_CCM_CLKC1[1]bel
OUT_CCM_CLKD1[0]bel
OUT_CCM_CLKD1[1]bel
OUT_CCM_REFCLKOUTbel
OUT_CCM_OSCOUT1bel
OUT_CCM_OSCOUT2bel
OUT_DCM_LOCKEDbel
DCM_DCM_O[0]mux
DCM_DCM_O[1]mux
DCM_DCM_O[2]mux
DCM_DCM_O[3]mux
DCM_DCM_O[4]mux
DCM_DCM_O[5]mux
DCM_DCM_O[6]mux
DCM_DCM_O[7]mux
DCM_DCM_O[8]mux
DCM_DCM_O[9]mux
DCM_DCM_O[10]mux
DCM_DCM_O[11]mux
DCM_DCM_O[12]mux
DCM_DCM_O[13]mux
DCM_DCM_O[14]mux
DCM_DCM_O[15]mux
DCM_DCM_O[16]mux
DCM_DCM_O[17]mux
DCM_DCM_O[18]mux
DCM_DCM_O[19]mux
DCM_DCM_O[20]mux
DCM_DCM_O[21]mux
DCM_DCM_O[22]mux
DCM_DCM_O[23]mux
DCM_DCM_I[0]branch CMT_PREV
DCM_DCM_I[1]branch CMT_PREV
DCM_DCM_I[2]branch CMT_PREV
DCM_DCM_I[3]branch CMT_PREV
DCM_DCM_I[4]branch CMT_PREV
DCM_DCM_I[5]branch CMT_PREV
DCM_DCM_I[6]branch CMT_PREV
DCM_DCM_I[7]branch CMT_PREV
DCM_DCM_I[8]branch CMT_PREV
DCM_DCM_I[9]branch CMT_PREV
DCM_DCM_I[10]branch CMT_PREV
DCM_DCM_I[11]branch CMT_PREV
DCM_DCM_I[12]branch CMT_PREV
DCM_DCM_I[13]branch CMT_PREV
DCM_DCM_I[14]branch CMT_PREV
DCM_DCM_I[15]branch CMT_PREV
DCM_DCM_I[16]branch CMT_PREV
DCM_DCM_I[17]branch CMT_PREV
DCM_DCM_I[18]branch CMT_PREV
DCM_DCM_I[19]branch CMT_PREV
DCM_DCM_I[20]branch CMT_PREV
DCM_DCM_I[21]branch CMT_PREV
DCM_DCM_I[22]branch CMT_PREV
DCM_DCM_I[23]branch CMT_PREV
HCLK_MGT[0]mux
HCLK_MGT[1]mux
HCLK_MGT[2]mux
HCLK_MGT[3]mux
HCLK_MGT[4]mux
HCLK_MGT[5]mux
HCLK_MGT[6]mux
HCLK_MGT[7]mux
MGT_CLK_OUT[0]mux
MGT_CLK_OUT[1]mux
MGT_CLK_OUT_SYNCLKmux
MGT_CLK_OUT_FWDCLK[0]mux
MGT_CLK_OUT_FWDCLK[1]mux
MGT_FWDCLK_S[0]multi_branch BEL_S
MGT_FWDCLK_S[1]multi_branch BEL_S
MGT_FWDCLK_S[2]multi_branch BEL_S
MGT_FWDCLK_S[3]multi_branch BEL_S
MGT_FWDCLK_N[0]multi_root
MGT_FWDCLK_N[1]multi_root
MGT_FWDCLK_N[2]multi_root
MGT_FWDCLK_N[3]multi_root
IMUX_MGT_GREFCLKmux
IMUX_MGT_REFCLKmux
IMUX_MGT_GREFCLK_PRE[0]mux
IMUX_MGT_GREFCLK_PRE[1]mux
IMUX_MGT_REFCLK_PRE[0]mux
IMUX_MGT_REFCLK_PRE[1]mux
OUT_MGT_SYNCLK[0]bel
OUT_MGT_SYNCLK[1]bel
OUT_MGT_RXPCSHCLKOUT[0]bel
OUT_MGT_RXPCSHCLKOUT[1]bel
OUT_MGT_TXPCSHCLKOUT[0]bel
OUT_MGT_TXPCSHCLKOUT[1]bel

Connectors — W

virtex4 wires
Wire PASS_W TERM_W CLB_BUFFER_W PPC_W
OMUX_E2 → OMUX[2] ← OMUX[6] → OMUX[2] ← OMUX[6]
OMUX_SE3 → OMUX_S3 ← OMUX_S5 → OMUX_S3 ← OMUX_S5
OMUX_E7 → OMUX[7] ← OMUX[1] → OMUX[7] ← OMUX[1]
OMUX_E8 → OMUX[8] ← OMUX[14] → OMUX[8] ← OMUX[14]
OMUX_NE12 → OMUX_N12 ← OMUX_N10 → OMUX_N12 ← OMUX_N10
OMUX_E13 → OMUX[13] ← OMUX[9] → OMUX[13] ← OMUX[9]
DBL_E1[0] → DBL_E0[0] ← DBL_W0[0] → DBL_E0[0] ← DBL_W0[0]
DBL_E1[1] → DBL_E0[1] ← DBL_W0[1] → DBL_E0[1] ← DBL_W0[1]
DBL_E1[2] → DBL_E0[2] ← DBL_W0[2] → DBL_E0[2] ← DBL_W0[2]
DBL_E1[3] → DBL_E0[3] ← DBL_W0[3] → DBL_E0[3] ← DBL_W0[3]
DBL_E1[4] → DBL_E0[4] ← DBL_W0[4] → DBL_E0[4] ← DBL_W0[4]
DBL_E1[5] → DBL_E0[5] ← DBL_W0[5] → DBL_E0[5] ← DBL_W0[5]
DBL_E1[6] → DBL_E0[6] ← DBL_W0[6] → DBL_E0[6] ← DBL_W0[6]
DBL_E1[7] → DBL_E0[7] ← DBL_W0[7] → DBL_E0[7] ← DBL_W0[7]
DBL_E1[8] → DBL_E0[8] ← DBL_W0[8] → DBL_E0[8] ← DBL_W0[8]
DBL_E1[9] → DBL_E0[9] ← DBL_W0[9] → DBL_E0[9] ← DBL_W0[9]
DBL_E2[0] → DBL_E1[0] ← DBL_W1[0] → DBL_E1[0] ← DBL_W1[0]
DBL_E2[1] → DBL_E1[1] ← DBL_W1[1] → DBL_E1[1] ← DBL_W1[1]
DBL_E2[2] → DBL_E1[2] ← DBL_W1[2] → DBL_E1[2] ← DBL_W1[2]
DBL_E2[3] → DBL_E1[3] ← DBL_W1[3] → DBL_E1[3] ← DBL_W1[3]
DBL_E2[4] → DBL_E1[4] ← DBL_W1[4] → DBL_E1[4] ← DBL_W1[4]
DBL_E2[5] → DBL_E1[5] ← DBL_W1[5] → DBL_E1[5] ← DBL_W1[5]
DBL_E2[6] → DBL_E1[6] ← DBL_W1[6] → DBL_E1[6] ← DBL_W1[6]
DBL_E2[7] → DBL_E1[7] ← DBL_W1[7] → DBL_E1[7] ← DBL_W1[7]
DBL_E2[8] → DBL_E1[8] ← DBL_W1[8] → DBL_E1[8] ← DBL_W1[8]
DBL_E2[9] → DBL_E1[9] ← DBL_W1[9] → DBL_E1[9] ← DBL_W1[9]
HEX_E1[0] → HEX_E0[0] ← HEX_W0[0] → HEX_E0[0] → HEX_E0[0]
HEX_E1[1] → HEX_E0[1] ← HEX_W0[1] → HEX_E0[1] → HEX_E0[1]
HEX_E1[2] → HEX_E0[2] ← HEX_W0[2] → HEX_E0[2] → HEX_E0[2]
HEX_E1[3] → HEX_E0[3] ← HEX_W0[3] → HEX_E0[3] → HEX_E0[3]
HEX_E1[4] → HEX_E0[4] ← HEX_W0[4] → HEX_E0[4] → HEX_E0[4]
HEX_E1[5] → HEX_E0[5] ← HEX_W0[5] → HEX_E0[5] → HEX_E0[5]
HEX_E1[6] → HEX_E0[6] ← HEX_W0[6] → HEX_E0[6] → HEX_E0[6]
HEX_E1[7] → HEX_E0[7] ← HEX_W0[7] → HEX_E0[7] → HEX_E0[7]
HEX_E1[8] → HEX_E0[8] ← HEX_W0[8] → HEX_E0[8] → HEX_E0[8]
HEX_E1[9] → HEX_E0[9] ← HEX_W0[9] → HEX_E0[9] → HEX_E0[9]
HEX_E2[0] → HEX_E1[0] ← HEX_W1[0] → HEX_E1[0] → HEX_E1[0]
HEX_E2[1] → HEX_E1[1] ← HEX_W1[1] → HEX_E1[1] → HEX_E1[1]
HEX_E2[2] → HEX_E1[2] ← HEX_W1[2] → HEX_E1[2] → HEX_E1[2]
HEX_E2[3] → HEX_E1[3] ← HEX_W1[3] → HEX_E1[3] → HEX_E1[3]
HEX_E2[4] → HEX_E1[4] ← HEX_W1[4] → HEX_E1[4] → HEX_E1[4]
HEX_E2[5] → HEX_E1[5] ← HEX_W1[5] → HEX_E1[5] → HEX_E1[5]
HEX_E2[6] → HEX_E1[6] ← HEX_W1[6] → HEX_E1[6] → HEX_E1[6]
HEX_E2[7] → HEX_E1[7] ← HEX_W1[7] → HEX_E1[7] → HEX_E1[7]
HEX_E2[8] → HEX_E1[8] ← HEX_W1[8] → HEX_E1[8] → HEX_E1[8]
HEX_E2[9] → HEX_E1[9] ← HEX_W1[9] → HEX_E1[9] → HEX_E1[9]
HEX_E3[0] → HEX_E2[0] ← HEX_W2[0] → HEX_E2[0] → HEX_E2[0]
HEX_E3[1] → HEX_E2[1] ← HEX_W2[1] → HEX_E2[1] → HEX_E2[1]
HEX_E3[2] → HEX_E2[2] ← HEX_W2[2] → HEX_E2[2] → HEX_E2[2]
HEX_E3[3] → HEX_E2[3] ← HEX_W2[3] → HEX_E2[3] → HEX_E2[3]
HEX_E3[4] → HEX_E2[4] ← HEX_W2[4] → HEX_E2[4] → HEX_E2[4]
HEX_E3[5] → HEX_E2[5] ← HEX_W2[5] → HEX_E2[5] → HEX_E2[5]
HEX_E3[6] → HEX_E2[6] ← HEX_W2[6] → HEX_E2[6] → HEX_E2[6]
HEX_E3[7] → HEX_E2[7] ← HEX_W2[7] → HEX_E2[7] → HEX_E2[7]
HEX_E3[8] → HEX_E2[8] ← HEX_W2[8] → HEX_E2[8] → HEX_E2[8]
HEX_E3[9] → HEX_E2[9] ← HEX_W2[9] → HEX_E2[9] → HEX_E2[9]
HEX_E4[0] → HEX_E3[0] ← HEX_W3[0] → HEX_E3[0] → HEX_E3[0]
HEX_E4[1] → HEX_E3[1] ← HEX_W3[1] → HEX_E3[1] → HEX_E3[1]
HEX_E4[2] → HEX_E3[2] ← HEX_W3[2] → HEX_E3[2] → HEX_E3[2]
HEX_E4[3] → HEX_E3[3] ← HEX_W3[3] → HEX_E3[3] → HEX_E3[3]
HEX_E4[4] → HEX_E3[4] ← HEX_W3[4] → HEX_E3[4] → HEX_E3[4]
HEX_E4[5] → HEX_E3[5] ← HEX_W3[5] → HEX_E3[5] → HEX_E3[5]
HEX_E4[6] → HEX_E3[6] ← HEX_W3[6] → HEX_E3[6] → HEX_E3[6]
HEX_E4[7] → HEX_E3[7] ← HEX_W3[7] → HEX_E3[7] → HEX_E3[7]
HEX_E4[8] → HEX_E3[8] ← HEX_W3[8] → HEX_E3[8] → HEX_E3[8]
HEX_E4[9] → HEX_E3[9] ← HEX_W3[9] → HEX_E3[9] → HEX_E3[9]
HEX_E5[0] → HEX_E4[0] ← HEX_W4[0] → HEX_E4[0] → HEX_E4[0]
HEX_E5[1] → HEX_E4[1] ← HEX_W4[1] → HEX_E4[1] → HEX_E4[1]
HEX_E5[2] → HEX_E4[2] ← HEX_W4[2] → HEX_E4[2] → HEX_E4[2]
HEX_E5[3] → HEX_E4[3] ← HEX_W4[3] → HEX_E4[3] → HEX_E4[3]
HEX_E5[4] → HEX_E4[4] ← HEX_W4[4] → HEX_E4[4] → HEX_E4[4]
HEX_E5[5] → HEX_E4[5] ← HEX_W4[5] → HEX_E4[5] → HEX_E4[5]
HEX_E5[6] → HEX_E4[6] ← HEX_W4[6] → HEX_E4[6] → HEX_E4[6]
HEX_E5[7] → HEX_E4[7] ← HEX_W4[7] → HEX_E4[7] → HEX_E4[7]
HEX_E5[8] → HEX_E4[8] ← HEX_W4[8] → HEX_E4[8] → HEX_E4[8]
HEX_E5[9] → HEX_E4[9] ← HEX_W4[9] → HEX_E4[9] → HEX_E4[9]
HEX_E6[0] → HEX_E5[0] ← HEX_W5[0] → HEX_E5[0] → HEX_E5[0]
HEX_E6[1] → HEX_E5[1] ← HEX_W5[1] → HEX_E5[1] → HEX_E5[1]
HEX_E6[2] → HEX_E5[2] ← HEX_W5[2] → HEX_E5[2] → HEX_E5[2]
HEX_E6[3] → HEX_E5[3] ← HEX_W5[3] → HEX_E5[3] → HEX_E5[3]
HEX_E6[4] → HEX_E5[4] ← HEX_W5[4] → HEX_E5[4] → HEX_E5[4]
HEX_E6[5] → HEX_E5[5] ← HEX_W5[5] → HEX_E5[5] → HEX_E5[5]
HEX_E6[6] → HEX_E5[6] ← HEX_W5[6] → HEX_E5[6] → HEX_E5[6]
HEX_E6[7] → HEX_E5[7] ← HEX_W5[7] → HEX_E5[7] → HEX_E5[7]
HEX_E6[8] → HEX_E5[8] ← HEX_W5[8] → HEX_E5[8] → HEX_E5[8]
HEX_E6[9] → HEX_E5[9] ← HEX_W5[9] → HEX_E5[9] → HEX_E5[9]
LH[0] → LH[1] - → LH[1] → LH[1]
LH[1] → LH[2] - → LH[2] → LH[2]
LH[2] → LH[3] - → LH[3] → LH[3]
LH[3] → LH[4] - → LH[4] → LH[4]
LH[4] → LH[5] - → LH[5] → LH[5]
LH[5] → LH[6] - → LH[6] → LH[6]
LH[6] → LH[7] - → LH[7] → LH[7]
LH[7] → LH[8] - → LH[8] → LH[8]
LH[8] → LH[9] - → LH[9] → LH[9]
LH[9] → LH[10] - → LH[10] → LH[10]
LH[10] → LH[11] - → LH[11] → LH[11]
LH[11] → LH[12] - → LH[12] → LH[12]

Connectors — E

virtex4 wires
Wire PASS_E TERM_E CLB_BUFFER_E PPC_E
OMUX_W1 → OMUX[1] ← OMUX[7] → OMUX[1] ← OMUX[7]
OMUX_SW5 → OMUX_S5 ← OMUX_S3 → OMUX_S5 ← OMUX_S3
OMUX_W6 → OMUX[6] ← OMUX[2] → OMUX[6] ← OMUX[2]
OMUX_W9 → OMUX[9] ← OMUX[13] → OMUX[9] ← OMUX[13]
OMUX_NW10 → OMUX_N10 ← OMUX_N12 → OMUX_N10 ← OMUX_N12
OMUX_W14 → OMUX[14] ← OMUX[8] → OMUX[14] ← OMUX[8]
DBL_W1[0] → DBL_W0[0] ← DBL_E0[0] → DBL_W0[0] ← DBL_E0[0]
DBL_W1[1] → DBL_W0[1] ← DBL_E0[1] → DBL_W0[1] ← DBL_E0[1]
DBL_W1[2] → DBL_W0[2] ← DBL_E0[2] → DBL_W0[2] ← DBL_E0[2]
DBL_W1[3] → DBL_W0[3] ← DBL_E0[3] → DBL_W0[3] ← DBL_E0[3]
DBL_W1[4] → DBL_W0[4] ← DBL_E0[4] → DBL_W0[4] ← DBL_E0[4]
DBL_W1[5] → DBL_W0[5] ← DBL_E0[5] → DBL_W0[5] ← DBL_E0[5]
DBL_W1[6] → DBL_W0[6] ← DBL_E0[6] → DBL_W0[6] ← DBL_E0[6]
DBL_W1[7] → DBL_W0[7] ← DBL_E0[7] → DBL_W0[7] ← DBL_E0[7]
DBL_W1[8] → DBL_W0[8] ← DBL_E0[8] → DBL_W0[8] ← DBL_E0[8]
DBL_W1[9] → DBL_W0[9] ← DBL_E0[9] → DBL_W0[9] ← DBL_E0[9]
DBL_W2[0] → DBL_W1[0] ← DBL_E1[0] → DBL_W1[0] ← DBL_E1[0]
DBL_W2[1] → DBL_W1[1] ← DBL_E1[1] → DBL_W1[1] ← DBL_E1[1]
DBL_W2[2] → DBL_W1[2] ← DBL_E1[2] → DBL_W1[2] ← DBL_E1[2]
DBL_W2[3] → DBL_W1[3] ← DBL_E1[3] → DBL_W1[3] ← DBL_E1[3]
DBL_W2[4] → DBL_W1[4] ← DBL_E1[4] → DBL_W1[4] ← DBL_E1[4]
DBL_W2[5] → DBL_W1[5] ← DBL_E1[5] → DBL_W1[5] ← DBL_E1[5]
DBL_W2[6] → DBL_W1[6] ← DBL_E1[6] → DBL_W1[6] ← DBL_E1[6]
DBL_W2[7] → DBL_W1[7] ← DBL_E1[7] → DBL_W1[7] ← DBL_E1[7]
DBL_W2[8] → DBL_W1[8] ← DBL_E1[8] → DBL_W1[8] ← DBL_E1[8]
DBL_W2[9] → DBL_W1[9] ← DBL_E1[9] → DBL_W1[9] ← DBL_E1[9]
HEX_W1[0] → HEX_W0[0] ← HEX_E0[0] → HEX_W0[0] → HEX_W0[0]
HEX_W1[1] → HEX_W0[1] ← HEX_E0[1] → HEX_W0[1] → HEX_W0[1]
HEX_W1[2] → HEX_W0[2] ← HEX_E0[2] → HEX_W0[2] → HEX_W0[2]
HEX_W1[3] → HEX_W0[3] ← HEX_E0[3] → HEX_W0[3] → HEX_W0[3]
HEX_W1[4] → HEX_W0[4] ← HEX_E0[4] → HEX_W0[4] → HEX_W0[4]
HEX_W1[5] → HEX_W0[5] ← HEX_E0[5] → HEX_W0[5] → HEX_W0[5]
HEX_W1[6] → HEX_W0[6] ← HEX_E0[6] → HEX_W0[6] → HEX_W0[6]
HEX_W1[7] → HEX_W0[7] ← HEX_E0[7] → HEX_W0[7] → HEX_W0[7]
HEX_W1[8] → HEX_W0[8] ← HEX_E0[8] → HEX_W0[8] → HEX_W0[8]
HEX_W1[9] → HEX_W0[9] ← HEX_E0[9] → HEX_W0[9] → HEX_W0[9]
HEX_W2[0] → HEX_W1[0] ← HEX_E1[0] → HEX_W1[0] → HEX_W1[0]
HEX_W2[1] → HEX_W1[1] ← HEX_E1[1] → HEX_W1[1] → HEX_W1[1]
HEX_W2[2] → HEX_W1[2] ← HEX_E1[2] → HEX_W1[2] → HEX_W1[2]
HEX_W2[3] → HEX_W1[3] ← HEX_E1[3] → HEX_W1[3] → HEX_W1[3]
HEX_W2[4] → HEX_W1[4] ← HEX_E1[4] → HEX_W1[4] → HEX_W1[4]
HEX_W2[5] → HEX_W1[5] ← HEX_E1[5] → HEX_W1[5] → HEX_W1[5]
HEX_W2[6] → HEX_W1[6] ← HEX_E1[6] → HEX_W1[6] → HEX_W1[6]
HEX_W2[7] → HEX_W1[7] ← HEX_E1[7] → HEX_W1[7] → HEX_W1[7]
HEX_W2[8] → HEX_W1[8] ← HEX_E1[8] → HEX_W1[8] → HEX_W1[8]
HEX_W2[9] → HEX_W1[9] ← HEX_E1[9] → HEX_W1[9] → HEX_W1[9]
HEX_W3[0] → HEX_W2[0] ← HEX_E2[0] → HEX_W2[0] → HEX_W2[0]
HEX_W3[1] → HEX_W2[1] ← HEX_E2[1] → HEX_W2[1] → HEX_W2[1]
HEX_W3[2] → HEX_W2[2] ← HEX_E2[2] → HEX_W2[2] → HEX_W2[2]
HEX_W3[3] → HEX_W2[3] ← HEX_E2[3] → HEX_W2[3] → HEX_W2[3]
HEX_W3[4] → HEX_W2[4] ← HEX_E2[4] → HEX_W2[4] → HEX_W2[4]
HEX_W3[5] → HEX_W2[5] ← HEX_E2[5] → HEX_W2[5] → HEX_W2[5]
HEX_W3[6] → HEX_W2[6] ← HEX_E2[6] → HEX_W2[6] → HEX_W2[6]
HEX_W3[7] → HEX_W2[7] ← HEX_E2[7] → HEX_W2[7] → HEX_W2[7]
HEX_W3[8] → HEX_W2[8] ← HEX_E2[8] → HEX_W2[8] → HEX_W2[8]
HEX_W3[9] → HEX_W2[9] ← HEX_E2[9] → HEX_W2[9] → HEX_W2[9]
HEX_W4[0] → HEX_W3[0] ← HEX_E3[0] → HEX_W3[0] → HEX_W3[0]
HEX_W4[1] → HEX_W3[1] ← HEX_E3[1] → HEX_W3[1] → HEX_W3[1]
HEX_W4[2] → HEX_W3[2] ← HEX_E3[2] → HEX_W3[2] → HEX_W3[2]
HEX_W4[3] → HEX_W3[3] ← HEX_E3[3] → HEX_W3[3] → HEX_W3[3]
HEX_W4[4] → HEX_W3[4] ← HEX_E3[4] → HEX_W3[4] → HEX_W3[4]
HEX_W4[5] → HEX_W3[5] ← HEX_E3[5] → HEX_W3[5] → HEX_W3[5]
HEX_W4[6] → HEX_W3[6] ← HEX_E3[6] → HEX_W3[6] → HEX_W3[6]
HEX_W4[7] → HEX_W3[7] ← HEX_E3[7] → HEX_W3[7] → HEX_W3[7]
HEX_W4[8] → HEX_W3[8] ← HEX_E3[8] → HEX_W3[8] → HEX_W3[8]
HEX_W4[9] → HEX_W3[9] ← HEX_E3[9] → HEX_W3[9] → HEX_W3[9]
HEX_W5[0] → HEX_W4[0] ← HEX_E4[0] → HEX_W4[0] → HEX_W4[0]
HEX_W5[1] → HEX_W4[1] ← HEX_E4[1] → HEX_W4[1] → HEX_W4[1]
HEX_W5[2] → HEX_W4[2] ← HEX_E4[2] → HEX_W4[2] → HEX_W4[2]
HEX_W5[3] → HEX_W4[3] ← HEX_E4[3] → HEX_W4[3] → HEX_W4[3]
HEX_W5[4] → HEX_W4[4] ← HEX_E4[4] → HEX_W4[4] → HEX_W4[4]
HEX_W5[5] → HEX_W4[5] ← HEX_E4[5] → HEX_W4[5] → HEX_W4[5]
HEX_W5[6] → HEX_W4[6] ← HEX_E4[6] → HEX_W4[6] → HEX_W4[6]
HEX_W5[7] → HEX_W4[7] ← HEX_E4[7] → HEX_W4[7] → HEX_W4[7]
HEX_W5[8] → HEX_W4[8] ← HEX_E4[8] → HEX_W4[8] → HEX_W4[8]
HEX_W5[9] → HEX_W4[9] ← HEX_E4[9] → HEX_W4[9] → HEX_W4[9]
HEX_W6[0] → HEX_W5[0] ← HEX_E5[0] → HEX_W5[0] → HEX_W5[0]
HEX_W6[1] → HEX_W5[1] ← HEX_E5[1] → HEX_W5[1] → HEX_W5[1]
HEX_W6[2] → HEX_W5[2] ← HEX_E5[2] → HEX_W5[2] → HEX_W5[2]
HEX_W6[3] → HEX_W5[3] ← HEX_E5[3] → HEX_W5[3] → HEX_W5[3]
HEX_W6[4] → HEX_W5[4] ← HEX_E5[4] → HEX_W5[4] → HEX_W5[4]
HEX_W6[5] → HEX_W5[5] ← HEX_E5[5] → HEX_W5[5] → HEX_W5[5]
HEX_W6[6] → HEX_W5[6] ← HEX_E5[6] → HEX_W5[6] → HEX_W5[6]
HEX_W6[7] → HEX_W5[7] ← HEX_E5[7] → HEX_W5[7] → HEX_W5[7]
HEX_W6[8] → HEX_W5[8] ← HEX_E5[8] → HEX_W5[8] → HEX_W5[8]
HEX_W6[9] → HEX_W5[9] ← HEX_E5[9] → HEX_W5[9] → HEX_W5[9]
LH[13] → LH[12] - → LH[12] → LH[12]
LH[14] → LH[13] - → LH[13] → LH[13]
LH[15] → LH[14] - → LH[14] → LH[14]
LH[16] → LH[15] - → LH[15] → LH[15]
LH[17] → LH[16] - → LH[16] → LH[16]
LH[18] → LH[17] - → LH[17] → LH[17]
LH[19] → LH[18] - → LH[18] → LH[18]
LH[20] → LH[19] - → LH[19] → LH[19]
LH[21] → LH[20] - → LH[20] → LH[20]
LH[22] → LH[21] - → LH[21] → LH[21]
LH[23] → LH[22] - → LH[22] → LH[22]
LH[24] → LH[23] - → LH[23] → LH[23]

Connectors — S

virtex4 wires
Wire PASS_S TERM_S BRKH_S PPC_A_S PPC_B_S
OMUX_EN8 → OMUX_E8 ← OMUX_E7 → OMUX_E8 ← OMUX_E7 -
OMUX_N10 → OMUX[10] ← OMUX[5] → OMUX[10] ← OMUX[5] -
OMUX_N11 → OMUX[11] ← OMUX[4] → OMUX[11] ← OMUX[4] -
OMUX_N12 → OMUX[12] ← OMUX[3] → OMUX[12] ← OMUX[3] -
OMUX_N13 → OMUX[13] - → OMUX[13] - -
OMUX_WN14 → OMUX_W14 ← OMUX_W1 → OMUX_W14 ← OMUX_W1 -
OMUX_N15 → OMUX[15] ← OMUX[0] → OMUX[15] ← OMUX[0] -
DBL_W2_N[0] → DBL_W2[0] - - - -
DBL_W2_N[1] → DBL_W2[1] - - - -
DBL_W2_N[2] → DBL_W2[2] - - - -
DBL_W2_N[3] → DBL_W2[3] - - - -
DBL_W2_N[4] → DBL_W2[4] - - - -
DBL_W2_N[5] → DBL_W2[5] - - - -
DBL_W2_N[6] → DBL_W2[6] - - - -
DBL_W2_N[7] → DBL_W2[7] - - - -
DBL_W2_N[8] → DBL_W2[8] - → DBL_W2[8] - -
DBL_W2_N[9] → DBL_W2[9] - → DBL_W2[9] - -
DBL_N1[0] → DBL_N0[0] ← DBL_S0[0] → DBL_N0[0] ← DBL_S0[0] ← DBL_S0[0]
DBL_N1[1] → DBL_N0[1] ← DBL_S0[1] → DBL_N0[1] ← DBL_S0[1] ← DBL_S0[1]
DBL_N1[2] → DBL_N0[2] ← DBL_S0[2] → DBL_N0[2] ← DBL_S0[2] ← DBL_S0[2]
DBL_N1[3] → DBL_N0[3] ← DBL_S0[3] → DBL_N0[3] ← DBL_S0[3] ← DBL_S0[3]
DBL_N1[4] → DBL_N0[4] ← DBL_S0[4] → DBL_N0[4] ← DBL_S0[4] ← DBL_S0[4]
DBL_N1[5] → DBL_N0[5] ← DBL_S0[5] → DBL_N0[5] ← DBL_S0[5] ← DBL_S0[5]
DBL_N1[6] → DBL_N0[6] ← DBL_S0[6] → DBL_N0[6] ← DBL_S0[6] ← DBL_S0[6]
DBL_N1[7] → DBL_N0[7] ← DBL_S0[7] → DBL_N0[7] ← DBL_S0[7] ← DBL_S0[7]
DBL_N1[8] → DBL_N0[8] ← DBL_S0[8] → DBL_N0[8] ← DBL_S0[8] ← DBL_S0[8]
DBL_N1[9] → DBL_N0[9] ← DBL_S0[9] → DBL_N0[9] ← DBL_S0[9] ← DBL_S0[9]
DBL_N2[0] → DBL_N1[0] ← DBL_S1[0] → DBL_N1[0] ← DBL_S1[0] ← DBL_S1[0]
DBL_N2[1] → DBL_N1[1] ← DBL_S1[1] → DBL_N1[1] ← DBL_S1[1] ← DBL_S1[1]
DBL_N2[2] → DBL_N1[2] ← DBL_S1[2] → DBL_N1[2] ← DBL_S1[2] ← DBL_S1[2]
DBL_N2[3] → DBL_N1[3] ← DBL_S1[3] → DBL_N1[3] ← DBL_S1[3] ← DBL_S1[3]
DBL_N2[4] → DBL_N1[4] ← DBL_S1[4] → DBL_N1[4] ← DBL_S1[4] ← DBL_S1[4]
DBL_N2[5] → DBL_N1[5] ← DBL_S1[5] → DBL_N1[5] ← DBL_S1[5] ← DBL_S1[5]
DBL_N2[6] → DBL_N1[6] ← DBL_S1[6] → DBL_N1[6] ← DBL_S1[6] ← DBL_S1[6]
DBL_N2[7] → DBL_N1[7] ← DBL_S1[7] → DBL_N1[7] ← DBL_S1[7] ← DBL_S1[7]
DBL_N2[8] → DBL_N1[8] ← DBL_S1[8] → DBL_N1[8] ← DBL_S1[8] ← DBL_S1[8]
DBL_N2[9] → DBL_N1[9] ← DBL_S1[9] → DBL_N1[9] ← DBL_S1[9] ← DBL_S1[9]
DBL_N3[0] → DBL_N2[0] - - - -
DBL_N3[1] → DBL_N2[1] - - - -
DBL_N3[2] → DBL_N2[2] - - - -
DBL_N3[3] → DBL_N2[3] - - - -
DBL_N3[4] → DBL_N2[4] - - - -
DBL_N3[5] → DBL_N2[5] - - - -
DBL_N3[6] → DBL_N2[6] - - - -
DBL_N3[7] → DBL_N2[7] - - - -
DBL_N3[8] → DBL_N2[8] - → DBL_N2[8] - -
DBL_N3[9] → DBL_N2[9] - → DBL_N2[9] - -
HEX_W6_N[0] → HEX_W6[0] - - - -
HEX_W6_N[1] → HEX_W6[1] - - - -
HEX_W6_N[2] → HEX_W6[2] - - - -
HEX_W6_N[3] → HEX_W6[3] - - - -
HEX_W6_N[4] → HEX_W6[4] - - - -
HEX_W6_N[5] → HEX_W6[5] - - - -
HEX_W6_N[6] → HEX_W6[6] - - - -
HEX_W6_N[7] → HEX_W6[7] - - - -
HEX_W6_N[8] → HEX_W6[8] - → HEX_W6[8] - -
HEX_W6_N[9] → HEX_W6[9] - → HEX_W6[9] - -
HEX_N1[0] → HEX_N0[0] ← HEX_S0[0] → HEX_N0[0] → HEX_N0[0] → HEX_N0[0]
HEX_N1[1] → HEX_N0[1] ← HEX_S0[1] → HEX_N0[1] ← HEX_S0[1] ← HEX_S0[1]
HEX_N1[2] → HEX_N0[2] ← HEX_S0[2] → HEX_N0[2] → HEX_N0[2] → HEX_N0[2]
HEX_N1[3] → HEX_N0[3] ← HEX_S0[3] → HEX_N0[3] ← HEX_S0[3] ← HEX_S0[3]
HEX_N1[4] → HEX_N0[4] ← HEX_S0[4] → HEX_N0[4] → HEX_N0[4] → HEX_N0[4]
HEX_N1[5] → HEX_N0[5] ← HEX_S0[5] → HEX_N0[5] → HEX_N0[5] → HEX_N0[5]
HEX_N1[6] → HEX_N0[6] ← HEX_S0[6] → HEX_N0[6] ← HEX_S0[6] ← HEX_S0[6]
HEX_N1[7] → HEX_N0[7] ← HEX_S0[7] → HEX_N0[7] → HEX_N0[7] → HEX_N0[7]
HEX_N1[8] → HEX_N0[8] ← HEX_S0[8] → HEX_N0[8] ← HEX_S0[8] ← HEX_S0[8]
HEX_N1[9] → HEX_N0[9] ← HEX_S0[9] → HEX_N0[9] → HEX_N0[9] → HEX_N0[9]
HEX_N2[0] → HEX_N1[0] ← HEX_S1[0] → HEX_N1[0] → HEX_N1[0] → HEX_N1[0]
HEX_N2[1] → HEX_N1[1] ← HEX_S1[1] → HEX_N1[1] ← HEX_S1[1] ← HEX_S1[1]
HEX_N2[2] → HEX_N1[2] ← HEX_S1[2] → HEX_N1[2] → HEX_N1[2] → HEX_N1[2]
HEX_N2[3] → HEX_N1[3] ← HEX_S1[3] → HEX_N1[3] ← HEX_S1[3] ← HEX_S1[3]
HEX_N2[4] → HEX_N1[4] ← HEX_S1[4] → HEX_N1[4] → HEX_N1[4] → HEX_N1[4]
HEX_N2[5] → HEX_N1[5] ← HEX_S1[5] → HEX_N1[5] → HEX_N1[5] → HEX_N1[5]
HEX_N2[6] → HEX_N1[6] ← HEX_S1[6] → HEX_N1[6] ← HEX_S1[6] ← HEX_S1[6]
HEX_N2[7] → HEX_N1[7] ← HEX_S1[7] → HEX_N1[7] → HEX_N1[7] → HEX_N1[7]
HEX_N2[8] → HEX_N1[8] ← HEX_S1[8] → HEX_N1[8] ← HEX_S1[8] ← HEX_S1[8]
HEX_N2[9] → HEX_N1[9] ← HEX_S1[9] → HEX_N1[9] → HEX_N1[9] → HEX_N1[9]
HEX_N3[0] → HEX_N2[0] ← HEX_S2[0] → HEX_N2[0] → HEX_N2[0] → HEX_N2[0]
HEX_N3[1] → HEX_N2[1] ← HEX_S2[1] → HEX_N2[1] ← HEX_S2[1] ← HEX_S2[1]
HEX_N3[2] → HEX_N2[2] ← HEX_S2[2] → HEX_N2[2] → HEX_N2[2] → HEX_N2[2]
HEX_N3[3] → HEX_N2[3] ← HEX_S2[3] → HEX_N2[3] ← HEX_S2[3] ← HEX_S2[3]
HEX_N3[4] → HEX_N2[4] ← HEX_S2[4] → HEX_N2[4] → HEX_N2[4] → HEX_N2[4]
HEX_N3[5] → HEX_N2[5] ← HEX_S2[5] → HEX_N2[5] → HEX_N2[5] → HEX_N2[5]
HEX_N3[6] → HEX_N2[6] ← HEX_S2[6] → HEX_N2[6] ← HEX_S2[6] ← HEX_S2[6]
HEX_N3[7] → HEX_N2[7] ← HEX_S2[7] → HEX_N2[7] → HEX_N2[7] → HEX_N2[7]
HEX_N3[8] → HEX_N2[8] ← HEX_S2[8] → HEX_N2[8] ← HEX_S2[8] ← HEX_S2[8]
HEX_N3[9] → HEX_N2[9] ← HEX_S2[9] → HEX_N2[9] → HEX_N2[9] → HEX_N2[9]
HEX_N4[0] → HEX_N3[0] ← HEX_S3[0] → HEX_N3[0] → HEX_N3[0] → HEX_N3[0]
HEX_N4[1] → HEX_N3[1] ← HEX_S3[1] → HEX_N3[1] ← HEX_S3[1] ← HEX_S3[1]
HEX_N4[2] → HEX_N3[2] ← HEX_S3[2] → HEX_N3[2] → HEX_N3[2] → HEX_N3[2]
HEX_N4[3] → HEX_N3[3] ← HEX_S3[3] → HEX_N3[3] ← HEX_S3[3] ← HEX_S3[3]
HEX_N4[4] → HEX_N3[4] ← HEX_S3[4] → HEX_N3[4] → HEX_N3[4] → HEX_N3[4]
HEX_N4[5] → HEX_N3[5] ← HEX_S3[5] → HEX_N3[5] → HEX_N3[5] → HEX_N3[5]
HEX_N4[6] → HEX_N3[6] ← HEX_S3[6] → HEX_N3[6] ← HEX_S3[6] ← HEX_S3[6]
HEX_N4[7] → HEX_N3[7] ← HEX_S3[7] → HEX_N3[7] → HEX_N3[7] → HEX_N3[7]
HEX_N4[8] → HEX_N3[8] ← HEX_S3[8] → HEX_N3[8] ← HEX_S3[8] ← HEX_S3[8]
HEX_N4[9] → HEX_N3[9] ← HEX_S3[9] → HEX_N3[9] → HEX_N3[9] → HEX_N3[9]
HEX_N5[0] → HEX_N4[0] ← HEX_S4[0] → HEX_N4[0] → HEX_N4[0] → HEX_N4[0]
HEX_N5[1] → HEX_N4[1] ← HEX_S4[1] → HEX_N4[1] ← HEX_S4[1] ← HEX_S4[1]
HEX_N5[2] → HEX_N4[2] ← HEX_S4[2] → HEX_N4[2] → HEX_N4[2] → HEX_N4[2]
HEX_N5[3] → HEX_N4[3] ← HEX_S4[3] → HEX_N4[3] ← HEX_S4[3] ← HEX_S4[3]
HEX_N5[4] → HEX_N4[4] ← HEX_S4[4] → HEX_N4[4] → HEX_N4[4] → HEX_N4[4]
HEX_N5[5] → HEX_N4[5] ← HEX_S4[5] → HEX_N4[5] → HEX_N4[5] → HEX_N4[5]
HEX_N5[6] → HEX_N4[6] ← HEX_S4[6] → HEX_N4[6] ← HEX_S4[6] ← HEX_S4[6]
HEX_N5[7] → HEX_N4[7] ← HEX_S4[7] → HEX_N4[7] → HEX_N4[7] → HEX_N4[7]
HEX_N5[8] → HEX_N4[8] ← HEX_S4[8] → HEX_N4[8] ← HEX_S4[8] ← HEX_S4[8]
HEX_N5[9] → HEX_N4[9] ← HEX_S4[9] → HEX_N4[9] → HEX_N4[9] → HEX_N4[9]
HEX_N6[0] → HEX_N5[0] ← HEX_S5[0] → HEX_N5[0] → HEX_N5[0] → HEX_N5[0]
HEX_N6[1] → HEX_N5[1] ← HEX_S5[1] → HEX_N5[1] ← HEX_S5[1] ← HEX_S5[1]
HEX_N6[2] → HEX_N5[2] ← HEX_S5[2] → HEX_N5[2] → HEX_N5[2] → HEX_N5[2]
HEX_N6[3] → HEX_N5[3] ← HEX_S5[3] → HEX_N5[3] ← HEX_S5[3] ← HEX_S5[3]
HEX_N6[4] → HEX_N5[4] ← HEX_S5[4] → HEX_N5[4] → HEX_N5[4] → HEX_N5[4]
HEX_N6[5] → HEX_N5[5] ← HEX_S5[5] → HEX_N5[5] → HEX_N5[5] → HEX_N5[5]
HEX_N6[6] → HEX_N5[6] ← HEX_S5[6] → HEX_N5[6] ← HEX_S5[6] ← HEX_S5[6]
HEX_N6[7] → HEX_N5[7] ← HEX_S5[7] → HEX_N5[7] → HEX_N5[7] → HEX_N5[7]
HEX_N6[8] → HEX_N5[8] ← HEX_S5[8] → HEX_N5[8] ← HEX_S5[8] ← HEX_S5[8]
HEX_N6[9] → HEX_N5[9] ← HEX_S5[9] → HEX_N5[9] → HEX_N5[9] → HEX_N5[9]
HEX_N7[0] → HEX_N6[0] - - - -
HEX_N7[1] → HEX_N6[1] - - - -
HEX_N7[2] → HEX_N6[2] - - - -
HEX_N7[3] → HEX_N6[3] - - - -
HEX_N7[4] → HEX_N6[4] - - - -
HEX_N7[5] → HEX_N6[5] - - - -
HEX_N7[6] → HEX_N6[6] - - - -
HEX_N7[7] → HEX_N6[7] - - - -
HEX_N7[8] → HEX_N6[8] - → HEX_N6[8] - -
HEX_N7[9] → HEX_N6[9] - → HEX_N6[9] - -
LV[0] → LV[1] - → LV[1] → LV[1] → LV[1]
LV[1] → LV[2] - → LV[2] → LV[2] → LV[2]
LV[2] → LV[3] - → LV[3] → LV[3] → LV[3]
LV[3] → LV[4] - → LV[4] → LV[4] → LV[4]
LV[4] → LV[5] - → LV[5] → LV[5] → LV[5]
LV[5] → LV[6] - → LV[6] → LV[6] → LV[6]
LV[6] → LV[7] - → LV[7] → LV[7] → LV[7]
LV[7] → LV[8] - → LV[8] → LV[8] → LV[8]
LV[8] → LV[9] - → LV[9] → LV[9] → LV[9]
LV[9] → LV[10] - → LV[10] → LV[10] → LV[10]
LV[10] → LV[11] - → LV[11] → LV[11] → LV[11]
LV[11] → LV[12] - → LV[12] → LV[12] → LV[12]

Connectors — N

virtex4 wires
Wire PASS_N TERM_N BRKH_N PPC_A_N PPC_B_N
OMUX_S0 → OMUX[0] ← OMUX[15] → OMUX[0] ← OMUX[15] -
OMUX_S0_ALT → OMUX[0] - - - -
OMUX_WS1 → OMUX_W1 ← OMUX_W14 → OMUX_W1 ← OMUX_W14 -
OMUX_S2 → OMUX[2] - → OMUX[2] - -
OMUX_S3 → OMUX[3] ← OMUX[12] → OMUX[3] ← OMUX[12] -
OMUX_S4 → OMUX[4] ← OMUX[11] → OMUX[4] ← OMUX[11] -
OMUX_S5 → OMUX[5] ← OMUX[10] → OMUX[5] ← OMUX[10] -
OMUX_ES7 → OMUX_E7 ← OMUX_E8 → OMUX_E7 ← OMUX_E8 -
DBL_E2_S[0] → DBL_E2[0] - → DBL_E2[0] - -
DBL_E2_S[1] → DBL_E2[1] - → DBL_E2[1] - -
DBL_E2_S[2] → DBL_E2[2] - - - -
DBL_E2_S[3] → DBL_E2[3] - - - -
DBL_E2_S[4] → DBL_E2[4] - - - -
DBL_E2_S[5] → DBL_E2[5] - - - -
DBL_E2_S[6] → DBL_E2[6] - - - -
DBL_E2_S[7] → DBL_E2[7] - - - -
DBL_E2_S[8] → DBL_E2[8] - - - -
DBL_E2_S[9] → DBL_E2[9] - - - -
DBL_S1[0] → DBL_S0[0] ← DBL_N0[0] → DBL_S0[0] ← DBL_N0[0] ← DBL_N0[0]
DBL_S1[1] → DBL_S0[1] ← DBL_N0[1] → DBL_S0[1] ← DBL_N0[1] ← DBL_N0[1]
DBL_S1[2] → DBL_S0[2] ← DBL_N0[2] → DBL_S0[2] ← DBL_N0[2] ← DBL_N0[2]
DBL_S1[3] → DBL_S0[3] ← DBL_N0[3] → DBL_S0[3] ← DBL_N0[3] ← DBL_N0[3]
DBL_S1[4] → DBL_S0[4] ← DBL_N0[4] → DBL_S0[4] ← DBL_N0[4] ← DBL_N0[4]
DBL_S1[5] → DBL_S0[5] ← DBL_N0[5] → DBL_S0[5] ← DBL_N0[5] ← DBL_N0[5]
DBL_S1[6] → DBL_S0[6] ← DBL_N0[6] → DBL_S0[6] ← DBL_N0[6] ← DBL_N0[6]
DBL_S1[7] → DBL_S0[7] ← DBL_N0[7] → DBL_S0[7] ← DBL_N0[7] ← DBL_N0[7]
DBL_S1[8] → DBL_S0[8] ← DBL_N0[8] → DBL_S0[8] ← DBL_N0[8] ← DBL_N0[8]
DBL_S1[9] → DBL_S0[9] ← DBL_N0[9] → DBL_S0[9] ← DBL_N0[9] ← DBL_N0[9]
DBL_S2[0] → DBL_S1[0] ← DBL_N1[0] → DBL_S1[0] ← DBL_N1[0] ← DBL_N1[0]
DBL_S2[1] → DBL_S1[1] ← DBL_N1[1] → DBL_S1[1] ← DBL_N1[1] ← DBL_N1[1]
DBL_S2[2] → DBL_S1[2] ← DBL_N1[2] → DBL_S1[2] ← DBL_N1[2] ← DBL_N1[2]
DBL_S2[3] → DBL_S1[3] ← DBL_N1[3] → DBL_S1[3] ← DBL_N1[3] ← DBL_N1[3]
DBL_S2[4] → DBL_S1[4] ← DBL_N1[4] → DBL_S1[4] ← DBL_N1[4] ← DBL_N1[4]
DBL_S2[5] → DBL_S1[5] ← DBL_N1[5] → DBL_S1[5] ← DBL_N1[5] ← DBL_N1[5]
DBL_S2[6] → DBL_S1[6] ← DBL_N1[6] → DBL_S1[6] ← DBL_N1[6] ← DBL_N1[6]
DBL_S2[7] → DBL_S1[7] ← DBL_N1[7] → DBL_S1[7] ← DBL_N1[7] ← DBL_N1[7]
DBL_S2[8] → DBL_S1[8] ← DBL_N1[8] → DBL_S1[8] ← DBL_N1[8] ← DBL_N1[8]
DBL_S2[9] → DBL_S1[9] ← DBL_N1[9] → DBL_S1[9] ← DBL_N1[9] ← DBL_N1[9]
DBL_S3[0] → DBL_S2[0] - → DBL_S2[0] - -
DBL_S3[1] → DBL_S2[1] - → DBL_S2[1] - -
DBL_S3[2] → DBL_S2[2] - - - -
DBL_S3[3] → DBL_S2[3] - - - -
DBL_S3[4] → DBL_S2[4] - - - -
DBL_S3[5] → DBL_S2[5] - - - -
DBL_S3[6] → DBL_S2[6] - - - -
DBL_S3[7] → DBL_S2[7] - - - -
DBL_S3[8] → DBL_S2[8] - - - -
DBL_S3[9] → DBL_S2[9] - - - -
HEX_E6_S[0] → HEX_E6[0] - → HEX_E6[0] - -
HEX_E6_S[1] → HEX_E6[1] - → HEX_E6[1] - -
HEX_E6_S[2] → HEX_E6[2] - - - -
HEX_E6_S[3] → HEX_E6[3] - - - -
HEX_E6_S[4] → HEX_E6[4] - - - -
HEX_E6_S[5] → HEX_E6[5] - - - -
HEX_E6_S[6] → HEX_E6[6] - - - -
HEX_E6_S[7] → HEX_E6[7] - - - -
HEX_E6_S[8] → HEX_E6[8] - - - -
HEX_E6_S[9] → HEX_E6[9] - - - -
HEX_S1[0] → HEX_S0[0] ← HEX_N0[0] → HEX_S0[0] → HEX_S0[0] → HEX_S0[0]
HEX_S1[1] → HEX_S0[1] ← HEX_N0[1] → HEX_S0[1] ← HEX_N0[1] ← HEX_N0[1]
HEX_S1[2] → HEX_S0[2] ← HEX_N0[2] → HEX_S0[2] → HEX_S0[2] → HEX_S0[2]
HEX_S1[3] → HEX_S0[3] ← HEX_N0[3] → HEX_S0[3] ← HEX_N0[3] ← HEX_N0[3]
HEX_S1[4] → HEX_S0[4] ← HEX_N0[4] → HEX_S0[4] → HEX_S0[4] → HEX_S0[4]
HEX_S1[5] → HEX_S0[5] ← HEX_N0[5] → HEX_S0[5] → HEX_S0[5] → HEX_S0[5]
HEX_S1[6] → HEX_S0[6] ← HEX_N0[6] → HEX_S0[6] ← HEX_N0[6] ← HEX_N0[6]
HEX_S1[7] → HEX_S0[7] ← HEX_N0[7] → HEX_S0[7] → HEX_S0[7] → HEX_S0[7]
HEX_S1[8] → HEX_S0[8] ← HEX_N0[8] → HEX_S0[8] ← HEX_N0[8] ← HEX_N0[8]
HEX_S1[9] → HEX_S0[9] ← HEX_N0[9] → HEX_S0[9] → HEX_S0[9] → HEX_S0[9]
HEX_S2[0] → HEX_S1[0] ← HEX_N1[0] → HEX_S1[0] → HEX_S1[0] → HEX_S1[0]
HEX_S2[1] → HEX_S1[1] ← HEX_N1[1] → HEX_S1[1] ← HEX_N1[1] ← HEX_N1[1]
HEX_S2[2] → HEX_S1[2] ← HEX_N1[2] → HEX_S1[2] → HEX_S1[2] → HEX_S1[2]
HEX_S2[3] → HEX_S1[3] ← HEX_N1[3] → HEX_S1[3] ← HEX_N1[3] ← HEX_N1[3]
HEX_S2[4] → HEX_S1[4] ← HEX_N1[4] → HEX_S1[4] → HEX_S1[4] → HEX_S1[4]
HEX_S2[5] → HEX_S1[5] ← HEX_N1[5] → HEX_S1[5] → HEX_S1[5] → HEX_S1[5]
HEX_S2[6] → HEX_S1[6] ← HEX_N1[6] → HEX_S1[6] ← HEX_N1[6] ← HEX_N1[6]
HEX_S2[7] → HEX_S1[7] ← HEX_N1[7] → HEX_S1[7] → HEX_S1[7] → HEX_S1[7]
HEX_S2[8] → HEX_S1[8] ← HEX_N1[8] → HEX_S1[8] ← HEX_N1[8] ← HEX_N1[8]
HEX_S2[9] → HEX_S1[9] ← HEX_N1[9] → HEX_S1[9] → HEX_S1[9] → HEX_S1[9]
HEX_S3[0] → HEX_S2[0] ← HEX_N2[0] → HEX_S2[0] → HEX_S2[0] → HEX_S2[0]
HEX_S3[1] → HEX_S2[1] ← HEX_N2[1] → HEX_S2[1] ← HEX_N2[1] ← HEX_N2[1]
HEX_S3[2] → HEX_S2[2] ← HEX_N2[2] → HEX_S2[2] → HEX_S2[2] → HEX_S2[2]
HEX_S3[3] → HEX_S2[3] ← HEX_N2[3] → HEX_S2[3] ← HEX_N2[3] ← HEX_N2[3]
HEX_S3[4] → HEX_S2[4] ← HEX_N2[4] → HEX_S2[4] → HEX_S2[4] → HEX_S2[4]
HEX_S3[5] → HEX_S2[5] ← HEX_N2[5] → HEX_S2[5] → HEX_S2[5] → HEX_S2[5]
HEX_S3[6] → HEX_S2[6] ← HEX_N2[6] → HEX_S2[6] ← HEX_N2[6] ← HEX_N2[6]
HEX_S3[7] → HEX_S2[7] ← HEX_N2[7] → HEX_S2[7] → HEX_S2[7] → HEX_S2[7]
HEX_S3[8] → HEX_S2[8] ← HEX_N2[8] → HEX_S2[8] ← HEX_N2[8] ← HEX_N2[8]
HEX_S3[9] → HEX_S2[9] ← HEX_N2[9] → HEX_S2[9] → HEX_S2[9] → HEX_S2[9]
HEX_S4[0] → HEX_S3[0] ← HEX_N3[0] → HEX_S3[0] → HEX_S3[0] → HEX_S3[0]
HEX_S4[1] → HEX_S3[1] ← HEX_N3[1] → HEX_S3[1] ← HEX_N3[1] ← HEX_N3[1]
HEX_S4[2] → HEX_S3[2] ← HEX_N3[2] → HEX_S3[2] → HEX_S3[2] → HEX_S3[2]
HEX_S4[3] → HEX_S3[3] ← HEX_N3[3] → HEX_S3[3] ← HEX_N3[3] ← HEX_N3[3]
HEX_S4[4] → HEX_S3[4] ← HEX_N3[4] → HEX_S3[4] → HEX_S3[4] → HEX_S3[4]
HEX_S4[5] → HEX_S3[5] ← HEX_N3[5] → HEX_S3[5] → HEX_S3[5] → HEX_S3[5]
HEX_S4[6] → HEX_S3[6] ← HEX_N3[6] → HEX_S3[6] ← HEX_N3[6] ← HEX_N3[6]
HEX_S4[7] → HEX_S3[7] ← HEX_N3[7] → HEX_S3[7] → HEX_S3[7] → HEX_S3[7]
HEX_S4[8] → HEX_S3[8] ← HEX_N3[8] → HEX_S3[8] ← HEX_N3[8] ← HEX_N3[8]
HEX_S4[9] → HEX_S3[9] ← HEX_N3[9] → HEX_S3[9] → HEX_S3[9] → HEX_S3[9]
HEX_S5[0] → HEX_S4[0] ← HEX_N4[0] → HEX_S4[0] → HEX_S4[0] → HEX_S4[0]
HEX_S5[1] → HEX_S4[1] ← HEX_N4[1] → HEX_S4[1] ← HEX_N4[1] ← HEX_N4[1]
HEX_S5[2] → HEX_S4[2] ← HEX_N4[2] → HEX_S4[2] → HEX_S4[2] → HEX_S4[2]
HEX_S5[3] → HEX_S4[3] ← HEX_N4[3] → HEX_S4[3] ← HEX_N4[3] ← HEX_N4[3]
HEX_S5[4] → HEX_S4[4] ← HEX_N4[4] → HEX_S4[4] → HEX_S4[4] → HEX_S4[4]
HEX_S5[5] → HEX_S4[5] ← HEX_N4[5] → HEX_S4[5] → HEX_S4[5] → HEX_S4[5]
HEX_S5[6] → HEX_S4[6] ← HEX_N4[6] → HEX_S4[6] ← HEX_N4[6] ← HEX_N4[6]
HEX_S5[7] → HEX_S4[7] ← HEX_N4[7] → HEX_S4[7] → HEX_S4[7] → HEX_S4[7]
HEX_S5[8] → HEX_S4[8] ← HEX_N4[8] → HEX_S4[8] ← HEX_N4[8] ← HEX_N4[8]
HEX_S5[9] → HEX_S4[9] ← HEX_N4[9] → HEX_S4[9] → HEX_S4[9] → HEX_S4[9]
HEX_S6[0] → HEX_S5[0] ← HEX_N5[0] → HEX_S5[0] → HEX_S5[0] → HEX_S5[0]
HEX_S6[1] → HEX_S5[1] ← HEX_N5[1] → HEX_S5[1] ← HEX_N5[1] ← HEX_N5[1]
HEX_S6[2] → HEX_S5[2] ← HEX_N5[2] → HEX_S5[2] → HEX_S5[2] → HEX_S5[2]
HEX_S6[3] → HEX_S5[3] ← HEX_N5[3] → HEX_S5[3] ← HEX_N5[3] ← HEX_N5[3]
HEX_S6[4] → HEX_S5[4] ← HEX_N5[4] → HEX_S5[4] → HEX_S5[4] → HEX_S5[4]
HEX_S6[5] → HEX_S5[5] ← HEX_N5[5] → HEX_S5[5] → HEX_S5[5] → HEX_S5[5]
HEX_S6[6] → HEX_S5[6] ← HEX_N5[6] → HEX_S5[6] ← HEX_N5[6] ← HEX_N5[6]
HEX_S6[7] → HEX_S5[7] ← HEX_N5[7] → HEX_S5[7] → HEX_S5[7] → HEX_S5[7]
HEX_S6[8] → HEX_S5[8] ← HEX_N5[8] → HEX_S5[8] ← HEX_N5[8] ← HEX_N5[8]
HEX_S6[9] → HEX_S5[9] ← HEX_N5[9] → HEX_S5[9] → HEX_S5[9] → HEX_S5[9]
HEX_S7[0] → HEX_S6[0] - → HEX_S6[0] - -
HEX_S7[1] → HEX_S6[1] - → HEX_S6[1] - -
HEX_S7[2] → HEX_S6[2] - - - -
HEX_S7[3] → HEX_S6[3] - - - -
HEX_S7[4] → HEX_S6[4] - - - -
HEX_S7[5] → HEX_S6[5] - - - -
HEX_S7[6] → HEX_S6[6] - - - -
HEX_S7[7] → HEX_S6[7] - - - -
HEX_S7[8] → HEX_S6[8] - - - -
HEX_S7[9] → HEX_S6[9] - - - -
LV[13] → LV[12] - → LV[12] → LV[12] → LV[12]
LV[14] → LV[13] - → LV[13] → LV[13] → LV[13]
LV[15] → LV[14] - → LV[14] → LV[14] → LV[14]
LV[16] → LV[15] - → LV[15] → LV[15] → LV[15]
LV[17] → LV[16] - → LV[16] → LV[16] → LV[16]
LV[18] → LV[17] - → LV[17] → LV[17] → LV[17]
LV[19] → LV[18] - → LV[18] → LV[18] → LV[18]
LV[20] → LV[19] - → LV[19] → LV[19] → LV[19]
LV[21] → LV[20] - → LV[20] → LV[20] → LV[20]
LV[22] → LV[21] - → LV[21] → LV[21] → LV[21]
LV[23] → LV[22] - → LV[22] → LV[22] → LV[22]
LV[24] → LV[23] - → LV[23] → LV[23] → LV[23]

Connectors — IO_S

virtex4 wires
Wire IO_S
IOCLK_N[0] → IOCLK[0]
IOCLK_N[1] → IOCLK[1]
VRCLK_N[0] → VRCLK[0]
VRCLK_N[1] → VRCLK[1]

Connectors — IO_N

virtex4 wires
Wire IO_N
IOCLK_S[0] → IOCLK[0]
IOCLK_S[1] → IOCLK[1]
VRCLK_S[0] → VRCLK[0]
VRCLK_S[1] → VRCLK[1]

Connectors — CLK_PREV

virtex4 wires
Wire CLK_PREV
IMUX_BUFG_I[0] → IMUX_BUFG_O[0]
IMUX_BUFG_I[1] → IMUX_BUFG_O[1]
IMUX_BUFG_I[2] → IMUX_BUFG_O[2]
IMUX_BUFG_I[3] → IMUX_BUFG_O[3]
IMUX_BUFG_I[4] → IMUX_BUFG_O[4]
IMUX_BUFG_I[5] → IMUX_BUFG_O[5]
IMUX_BUFG_I[6] → IMUX_BUFG_O[6]
IMUX_BUFG_I[7] → IMUX_BUFG_O[7]
IMUX_BUFG_I[8] → IMUX_BUFG_O[8]
IMUX_BUFG_I[9] → IMUX_BUFG_O[9]
IMUX_BUFG_I[10] → IMUX_BUFG_O[10]
IMUX_BUFG_I[11] → IMUX_BUFG_O[11]
IMUX_BUFG_I[12] → IMUX_BUFG_O[12]
IMUX_BUFG_I[13] → IMUX_BUFG_O[13]
IMUX_BUFG_I[14] → IMUX_BUFG_O[14]
IMUX_BUFG_I[15] → IMUX_BUFG_O[15]
IMUX_BUFG_I[16] → IMUX_BUFG_O[16]
IMUX_BUFG_I[17] → IMUX_BUFG_O[17]
IMUX_BUFG_I[18] → IMUX_BUFG_O[18]
IMUX_BUFG_I[19] → IMUX_BUFG_O[19]
IMUX_BUFG_I[20] → IMUX_BUFG_O[20]
IMUX_BUFG_I[21] → IMUX_BUFG_O[21]
IMUX_BUFG_I[22] → IMUX_BUFG_O[22]
IMUX_BUFG_I[23] → IMUX_BUFG_O[23]
IMUX_BUFG_I[24] → IMUX_BUFG_O[24]
IMUX_BUFG_I[25] → IMUX_BUFG_O[25]
IMUX_BUFG_I[26] → IMUX_BUFG_O[26]
IMUX_BUFG_I[27] → IMUX_BUFG_O[27]
IMUX_BUFG_I[28] → IMUX_BUFG_O[28]
IMUX_BUFG_I[29] → IMUX_BUFG_O[29]
IMUX_BUFG_I[30] → IMUX_BUFG_O[30]
IMUX_BUFG_I[31] → IMUX_BUFG_O[31]

Connectors — CLK_NEXT

virtex4 wires
Wire CLK_NEXT

Connectors — BEL_S

virtex4 wires
Wire MGT_S
MGT_FWDCLK_S[0] → MGT_FWDCLK_N[0]
MGT_FWDCLK_S[1] → MGT_FWDCLK_N[1]
MGT_FWDCLK_S[2] → MGT_FWDCLK_N[2]
MGT_FWDCLK_S[3] → MGT_FWDCLK_N[3]

Connectors — BEL_N

virtex4 wires
Wire MGT_N

Connectors — CMT_PREV

virtex4 wires
Wire CMT_PREV CMT_PREV_CCM
DCM_DCM_I[0] → DCM_DCM_O[0] → DCM_DCM_I[0]
DCM_DCM_I[1] → DCM_DCM_O[1] → DCM_DCM_I[1]
DCM_DCM_I[2] → DCM_DCM_O[2] → DCM_DCM_I[2]
DCM_DCM_I[3] → DCM_DCM_O[3] → DCM_DCM_I[3]
DCM_DCM_I[4] → DCM_DCM_O[4] → DCM_DCM_I[4]
DCM_DCM_I[5] → DCM_DCM_O[5] → DCM_DCM_I[5]
DCM_DCM_I[6] → DCM_DCM_O[6] → DCM_DCM_I[6]
DCM_DCM_I[7] → DCM_DCM_O[7] → DCM_DCM_I[7]
DCM_DCM_I[8] → DCM_DCM_O[8] → DCM_DCM_I[8]
DCM_DCM_I[9] → DCM_DCM_O[9] → DCM_DCM_I[9]
DCM_DCM_I[10] → DCM_DCM_O[10] → DCM_DCM_I[10]
DCM_DCM_I[11] → DCM_DCM_O[11] → DCM_DCM_I[11]
DCM_DCM_I[12] → DCM_DCM_O[12] → DCM_DCM_I[12]
DCM_DCM_I[13] → DCM_DCM_O[13] → DCM_DCM_I[13]
DCM_DCM_I[14] → DCM_DCM_O[14] → DCM_DCM_I[14]
DCM_DCM_I[15] → DCM_DCM_O[15] → DCM_DCM_I[15]
DCM_DCM_I[16] → DCM_DCM_O[16] → DCM_DCM_I[16]
DCM_DCM_I[17] → DCM_DCM_O[17] → DCM_DCM_I[17]
DCM_DCM_I[18] → DCM_DCM_O[18] → DCM_DCM_I[18]
DCM_DCM_I[19] → DCM_DCM_O[19] → DCM_DCM_I[19]
DCM_DCM_I[20] → DCM_DCM_O[20] → DCM_DCM_I[20]
DCM_DCM_I[21] → DCM_DCM_O[21] → DCM_DCM_I[21]
DCM_DCM_I[22] → DCM_DCM_O[22] → DCM_DCM_I[22]
DCM_DCM_I[23] → DCM_DCM_O[23] → DCM_DCM_I[23]

Connectors — CMT_NEXT

virtex4 wires
Wire CMT_NEXT

Connectors — HCLK_ROW_PREV

virtex4 wires
Wire

Connectors — HCLK_ROW_NEXT

virtex4 wires
Wire

Tile INT

Cells: 1

Switchbox INT

virtex4 INT switchbox INT permanent buffers
DestinationSource
IMUX_BYP_BOUNCE[0]IMUX_BYP[0]
IMUX_BYP_BOUNCE[1]IMUX_BYP[1]
IMUX_BYP_BOUNCE[2]IMUX_BYP[2]
IMUX_BYP_BOUNCE[3]IMUX_BYP[3]
IMUX_BYP_BOUNCE[4]IMUX_BYP[4]
IMUX_BYP_BOUNCE[5]IMUX_BYP[5]
IMUX_BYP_BOUNCE[6]IMUX_BYP[6]
IMUX_BYP_BOUNCE[7]IMUX_BYP[7]
virtex4 INT switchbox INT programmable inverters
DestinationSourceBit
IMUX_SR_OPTINV[0]IMUX_SR[0]!MAIN[18][24]
IMUX_SR_OPTINV[1]IMUX_SR[1]!MAIN[18][26]
IMUX_SR_OPTINV[2]IMUX_SR[2]!MAIN[18][23]
IMUX_SR_OPTINV[3]IMUX_SR[3]!MAIN[18][25]
IMUX_CLK_OPTINV[0]IMUX_CLK[0]!MAIN[18][29]
IMUX_CLK_OPTINV[1]IMUX_CLK[1]!MAIN[18][27]
IMUX_CLK_OPTINV[2]IMUX_CLK[2]!MAIN[18][55]
IMUX_CLK_OPTINV[3]IMUX_CLK[3]!MAIN[18][50]
IMUX_CE_OPTINV[0]IMUX_CE[0]!MAIN[18][53]
IMUX_CE_OPTINV[1]IMUX_CE[1]!MAIN[18][56]
IMUX_CE_OPTINV[2]IMUX_CE[2]!MAIN[18][52]
IMUX_CE_OPTINV[3]IMUX_CE[3]!MAIN[18][54]
virtex4 INT switchbox INT muxes OMUX[0]
BitsDestination
MAIN[17][0]MAIN[16][0]MAIN[17][1]MAIN[17][2]MAIN[17][3]MAIN[16][3]MAIN[16][1]MAIN[16][8]MAIN[16][6]MAIN[17][6]OMUX[0]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[1]
BitsDestination
MAIN[17][9]MAIN[16][9]MAIN[17][8]MAIN[17][7]MAIN[16][2]MAIN[16][4]MAIN[17][4]MAIN[16][5]MAIN[17][5]MAIN[16][7]OMUX[1]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[2]
BitsDestination
MAIN[17][10]MAIN[16][10]MAIN[17][11]MAIN[17][12]MAIN[17][13]MAIN[16][13]MAIN[16][11]MAIN[16][18]MAIN[16][16]MAIN[17][16]OMUX[2]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[3]
BitsDestination
MAIN[17][19]MAIN[16][19]MAIN[17][18]MAIN[17][17]MAIN[16][12]MAIN[16][14]MAIN[17][14]MAIN[16][15]MAIN[17][15]MAIN[16][17]OMUX[3]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[4]
BitsDestination
MAIN[17][20]MAIN[16][20]MAIN[17][21]MAIN[17][22]MAIN[17][23]MAIN[16][23]MAIN[16][21]MAIN[16][28]MAIN[16][26]MAIN[17][26]OMUX[4]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[5]
BitsDestination
MAIN[17][29]MAIN[16][29]MAIN[17][28]MAIN[17][27]MAIN[16][22]MAIN[16][24]MAIN[17][24]MAIN[16][25]MAIN[17][25]MAIN[16][27]OMUX[5]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[6]
BitsDestination
MAIN[17][30]MAIN[16][30]MAIN[17][31]MAIN[17][32]MAIN[17][33]MAIN[16][33]MAIN[16][31]MAIN[16][38]MAIN[16][36]MAIN[17][36]OMUX[6]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[7]
BitsDestination
MAIN[17][39]MAIN[16][39]MAIN[17][38]MAIN[17][37]MAIN[16][32]MAIN[16][34]MAIN[17][34]MAIN[16][35]MAIN[17][35]MAIN[16][37]OMUX[7]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF0[0]
0100100000OUT_HALF0[1]
1000000001OUT_HALF0[2]
1000000010OUT_HALF0[3]
1000000100OUT_HALF0[4]
1000001000OUT_HALF0[5]
1000010000OUT_HALF0[6]
1000100000OUT_HALF0[7]
virtex4 INT switchbox INT muxes OMUX[8]
BitsDestination
MAIN[17][40]MAIN[16][40]MAIN[17][41]MAIN[17][42]MAIN[17][43]MAIN[16][43]MAIN[16][41]MAIN[16][48]MAIN[16][46]MAIN[17][46]OMUX[8]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[9]
BitsDestination
MAIN[17][49]MAIN[16][49]MAIN[17][48]MAIN[17][47]MAIN[16][42]MAIN[16][44]MAIN[17][44]MAIN[16][45]MAIN[17][45]MAIN[16][47]OMUX[9]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[10]
BitsDestination
MAIN[17][50]MAIN[16][50]MAIN[17][51]MAIN[17][52]MAIN[17][53]MAIN[16][53]MAIN[16][51]MAIN[16][58]MAIN[16][56]MAIN[17][56]OMUX[10]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[11]
BitsDestination
MAIN[17][59]MAIN[16][59]MAIN[17][58]MAIN[17][57]MAIN[16][52]MAIN[16][54]MAIN[17][54]MAIN[16][55]MAIN[17][55]MAIN[16][57]OMUX[11]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[12]
BitsDestination
MAIN[17][60]MAIN[16][60]MAIN[17][61]MAIN[17][62]MAIN[17][63]MAIN[16][63]MAIN[16][61]MAIN[16][68]MAIN[16][66]MAIN[17][66]OMUX[12]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[13]
BitsDestination
MAIN[17][69]MAIN[16][69]MAIN[17][68]MAIN[17][67]MAIN[16][62]MAIN[16][64]MAIN[17][64]MAIN[16][65]MAIN[17][65]MAIN[16][67]OMUX[13]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[14]
BitsDestination
MAIN[17][70]MAIN[16][70]MAIN[17][71]MAIN[17][72]MAIN[17][73]MAIN[16][73]MAIN[16][71]MAIN[16][78]MAIN[16][76]MAIN[17][76]OMUX[14]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes OMUX[15]
BitsDestination
MAIN[17][79]MAIN[16][79]MAIN[17][78]MAIN[17][77]MAIN[16][72]MAIN[16][74]MAIN[17][74]MAIN[16][75]MAIN[17][75]MAIN[16][77]OMUX[15]
Source
0000000000off
0001000001OUT_BEST[0]
0001000010OUT_BEST[1]
0001000100OUT_BEST[2]
0001001000OUT_BEST[3]
0001010000OUT_BEST[4]
0001100000OUT_BEST[5]
0010000001OUT_BEST[6]
0010000010OUT_BEST[7]
0010000100OUT_SEC[0]
0010001000OUT_SEC[1]
0010010000OUT_SEC[2]
0010100000OUT_SEC[3]
0100000001OUT_SEC[4]
0100000010OUT_SEC[5]
0100000100OUT_SEC[6]
0100001000OUT_SEC[7]
0100010000OUT_HALF1[0]
0100100000OUT_HALF1[1]
1000000001OUT_HALF1[2]
1000000010OUT_HALF1[3]
1000000100OUT_HALF1[4]
1000001000OUT_HALF1[5]
1000010000OUT_HALF1[6]
1000100000OUT_HALF1[7]
virtex4 INT switchbox INT muxes DBL_W0[0]
BitsDestination
MAIN[6][4]MAIN[6][7]MAIN[7][7]MAIN[7][4]MAIN[4][4]MAIN[5][5]MAIN[4][7]MAIN[5][6]DBL_W0[0]
Source
00000000off
00010001OMUX_S0
00010010HEX_E6[0]
00010100OUT_BEST[3]
00011000HEX_N6[0]
00100001OMUX_NW10
00100010HEX_S6[1]
00100100OUT_BEST[4]
00101000HEX_W6[0]
01000001DBL_W2[0]
01000010HEX_N3[0]
01000100HEX_S3[0]
01001000DBL_N3[9]
10000001DBL_W2_N[8]
10000010DBL_S1[0]
10000100DBL_S2[2]
10001000DBL_N1[0]
virtex4 INT switchbox INT muxes DBL_W0[1]
BitsDestination
MAIN[6][12]MAIN[6][15]MAIN[7][15]MAIN[7][12]MAIN[4][12]MAIN[5][13]MAIN[4][15]MAIN[5][14]DBL_W0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_E6[1]
00010100OUT_BEST[2]
00011000HEX_N6[1]
00100001OMUX_W1
00100010HEX_S6[2]
00100100OUT_BEST[5]
00101000HEX_W6[1]
01000001DBL_W2[1]
01000010HEX_N3[1]
01000100HEX_S3[1]
01001000DBL_N2[0]
10000001DBL_W2_N[9]
10000010DBL_S1[1]
10000100DBL_S2[3]
10001000DBL_N1[1]
virtex4 INT switchbox INT muxes DBL_W0[2]
BitsDestination
MAIN[4][20]MAIN[4][23]MAIN[5][22]MAIN[5][21]MAIN[6][23]MAIN[6][20]MAIN[7][23]MAIN[7][20]DBL_W0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_BEST[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX[6]
00100010OMUX_WN14
00100100DBL_W2[0]
00101000DBL_W2[2]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex4 INT switchbox INT muxes DBL_W0[3]
BitsDestination
MAIN[6][31]MAIN[6][28]MAIN[7][31]MAIN[7][28]MAIN[4][28]MAIN[5][29]MAIN[4][31]MAIN[5][30]DBL_W0[3]
Source
00000000off
00010001OMUX_W6
00010010HEX_E6[3]
00010100OUT_BEST[4]
00011000HEX_N6[3]
00100001OMUX_NW10
00100010HEX_S6[4]
00100100OUT_BEST[2]
00101000HEX_W6[3]
01000001DBL_W2[1]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_W2[3]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex4 INT switchbox INT muxes DBL_W0[4]
BitsDestination
MAIN[6][39]MAIN[6][36]MAIN[7][39]MAIN[7][36]MAIN[4][36]MAIN[5][37]MAIN[4][39]MAIN[5][38]DBL_W0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_E6[4]
00010100OUT_BEST[5]
00011000HEX_N6[4]
00100001OMUX_N12
00100010HEX_S6[5]
00100100OUT_BEST[6]
00101000HEX_W6[4]
01000001DBL_W2[2]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_W2[4]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex4 INT switchbox INT muxes DBL_W0[5]
BitsDestination
MAIN[6][47]MAIN[6][44]MAIN[7][47]MAIN[7][44]MAIN[4][44]MAIN[5][45]MAIN[4][47]MAIN[5][46]DBL_W0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_E6[5]
00010100OUT_BEST[1]
00011000HEX_N6[5]
00100001OMUX_WN14
00100010HEX_S6[6]
00100100OUT_BEST[7]
00101000HEX_W6[5]
01000001DBL_W2[3]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_W2[5]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex4 INT switchbox INT muxes DBL_W0[6]
BitsDestination
MAIN[4][52]MAIN[4][55]MAIN[5][54]MAIN[5][53]MAIN[6][55]MAIN[6][52]MAIN[7][52]MAIN[7][55]DBL_W0[6]
Source
00000000off
00010001OMUX[11]
00010010OUT_BEST[0]
00010100DBL_S2[8]
00011000HEX_S3[6]
00100001OMUX_W9
00100010OMUX_SW5
00100100DBL_W2[4]
00101000DBL_W2[6]
01000001HEX_S6[7]
01000010HEX_E6[6]
01000100DBL_S1[6]
01001000HEX_N3[6]
10000001HEX_W6[6]
10000010HEX_N6[6]
10000100DBL_N1[6]
10001000DBL_N2[5]
virtex4 INT switchbox INT muxes DBL_W0[7]
BitsDestination
MAIN[6][63]MAIN[6][60]MAIN[7][60]MAIN[7][63]MAIN[4][60]MAIN[5][61]MAIN[4][63]MAIN[5][62]DBL_W0[7]
Source
00000000off
00010001OMUX[9]
00010010HEX_S6[8]
00010100OUT_BEST[1]
00011000HEX_W6[7]
00100001OMUX_WS1
00100010HEX_E6[7]
00100100OUT_BEST[6]
00101000HEX_N6[7]
01000001DBL_W2[5]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_W2[7]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex4 INT switchbox INT muxes DBL_W0[8]
BitsDestination
MAIN[6][71]MAIN[6][68]MAIN[7][68]MAIN[7][71]MAIN[4][68]MAIN[5][69]MAIN[4][71]MAIN[5][70]DBL_W0[8]
Source
00000000off
00010001OMUX[13]
00010010HEX_S6[9]
00010100OUT_BEST[0]
00011000HEX_W6[8]
00100001OMUX_W14
00100010HEX_E6[8]
00100100OUT_BEST[7]
00101000HEX_N6[8]
01000001DBL_W2[6]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_W2[8]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex4 INT switchbox INT muxes DBL_W0[9]
BitsDestination
MAIN[4][76]MAIN[4][79]MAIN[5][77]MAIN[5][78]MAIN[6][79]MAIN[6][76]MAIN[7][76]MAIN[7][79]DBL_W0[9]
Source
00000000off
00010001OMUX[13]
00010010OMUX_SW5
00010100DBL_W2[7]
00011000DBL_W2[9]
00100001OMUX_S0_ALT
00100010OMUX[15]
00100100DBL_S3[1]
00101000HEX_S3[9]
01000001HEX_S7[0]
01000010HEX_E6[9]
01000100DBL_S1[9]
01001000HEX_N3[9]
10000001HEX_W6[9]
10000010HEX_N6[9]
10000100DBL_N1[9]
10001000DBL_N2[8]
virtex4 INT switchbox INT muxes DBL_E0[0]
BitsDestination
MAIN[6][6]MAIN[6][5]MAIN[7][5]MAIN[7][6]MAIN[5][7]MAIN[4][6]MAIN[4][5]MAIN[5][4]DBL_E0[0]
Source
00000000off
00010001OMUX_E2
00010010HEX_S6[1]
00010100OUT_BEST[4]
00011000HEX_W6[0]
00100001OMUX_EN8
00100010HEX_E6[0]
00100100OUT_BEST[3]
00101000HEX_N6[0]
01000001DBL_E2[0]
01000010DBL_S1[0]
01000100DBL_S2[2]
01001000DBL_N1[0]
10000001DBL_E2[2]
10000010HEX_N3[0]
10000100HEX_S3[0]
10001000DBL_N3[9]
virtex4 INT switchbox INT muxes DBL_E0[1]
BitsDestination
MAIN[6][14]MAIN[6][13]MAIN[7][13]MAIN[7][14]MAIN[5][15]MAIN[4][14]MAIN[4][13]MAIN[5][12]DBL_E0[1]
Source
00000000off
00010001OMUX_S4
00010010HEX_S6[2]
00010100OUT_BEST[5]
00011000HEX_W6[1]
00100001OMUX_N10
00100010HEX_E6[1]
00100100OUT_BEST[2]
00101000HEX_N6[1]
01000001DBL_E2[1]
01000010DBL_S1[1]
01000100DBL_S2[3]
01001000DBL_N1[1]
10000001DBL_E2[3]
10000010HEX_N3[1]
10000100HEX_S3[1]
10001000DBL_N2[0]
virtex4 INT switchbox INT muxes DBL_E0[2]
BitsDestination
MAIN[5][23]MAIN[4][21]MAIN[5][20]MAIN[4][22]MAIN[6][22]MAIN[6][21]MAIN[7][22]MAIN[7][21]DBL_E0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_BEST[3]
00010100DBL_S2[4]
00011000HEX_S3[2]
00100001OMUX_NE12
00100010OMUX[6]
00100100DBL_E2[2]
00101000DBL_E2[4]
01000001HEX_E6[2]
01000010HEX_S6[3]
01000100DBL_S1[2]
01001000HEX_N3[2]
10000001HEX_N6[2]
10000010HEX_W6[2]
10000100DBL_N1[2]
10001000DBL_N2[1]
virtex4 INT switchbox INT muxes DBL_E0[3]
BitsDestination
MAIN[6][30]MAIN[6][29]MAIN[7][29]MAIN[7][30]MAIN[5][31]MAIN[4][30]MAIN[4][29]MAIN[5][28]DBL_E0[3]
Source
00000000off
00010001OMUX_SE3
00010010HEX_S6[4]
00010100OUT_BEST[2]
00011000HEX_W6[3]
00100001OMUX_EN8
00100010HEX_E6[3]
00100100OUT_BEST[4]
00101000HEX_N6[3]
01000001DBL_E2[3]
01000010DBL_S1[3]
01000100DBL_S2[5]
01001000DBL_N1[3]
10000001DBL_E2[5]
10000010HEX_N3[3]
10000100HEX_S3[3]
10001000DBL_N2[2]
virtex4 INT switchbox INT muxes DBL_E0[4]
BitsDestination
MAIN[6][38]MAIN[6][37]MAIN[7][38]MAIN[7][37]MAIN[5][39]MAIN[4][38]MAIN[4][37]MAIN[5][36]DBL_E0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_E6[4]
00010100OUT_BEST[5]
00011000HEX_N6[4]
00100001OMUX_E8
00100010HEX_S6[5]
00100100OUT_BEST[6]
00101000HEX_W6[4]
01000001DBL_E2[4]
01000010DBL_S1[4]
01000100DBL_S2[6]
01001000DBL_N1[4]
10000001DBL_E2[6]
10000010HEX_N3[4]
10000100HEX_S3[4]
10001000DBL_N2[3]
virtex4 INT switchbox INT muxes DBL_E0[5]
BitsDestination
MAIN[6][46]MAIN[6][45]MAIN[7][45]MAIN[7][46]MAIN[5][47]MAIN[4][46]MAIN[4][45]MAIN[5][44]DBL_E0[5]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[6]
00010100OUT_BEST[7]
00011000HEX_W6[5]
00100001OMUX_NE12
00100010HEX_E6[5]
00100100OUT_BEST[1]
00101000HEX_N6[5]
01000001DBL_E2[5]
01000010DBL_S1[5]
01000100DBL_S2[7]
01001000DBL_N1[5]
10000001DBL_E2[7]
10000010HEX_N3[5]
10000100HEX_S3[5]
10001000DBL_N2[4]
virtex4 INT switchbox INT muxes DBL_E0[6]
BitsDestination
MAIN[6][54]MAIN[6][53]MAIN[7][54]MAIN[7][53]MAIN[5][55]MAIN[4][53]MAIN[4][54]MAIN[5][52]DBL_E0[6]
Source
00000000off
00010001OMUX[9]
00010010OUT_BEST[0]
00010100HEX_E6[6]
00011000HEX_N6[6]
00100001OMUX_SE3
00100010OMUX[11]
00100100HEX_S6[7]
00101000HEX_W6[6]
01000001DBL_E2[6]
01000010DBL_S2[8]
01000100DBL_S1[6]
01001000DBL_N1[6]
10000001DBL_E2[8]
10000010HEX_S3[6]
10000100HEX_N3[6]
10001000DBL_N2[5]
virtex4 INT switchbox INT muxes DBL_E0[7]
BitsDestination
MAIN[6][62]MAIN[6][61]MAIN[7][61]MAIN[7][62]MAIN[5][63]MAIN[4][62]MAIN[4][61]MAIN[5][60]DBL_E0[7]
Source
00000000off
00010001OMUX_S5
00010010HEX_S6[8]
00010100OUT_BEST[1]
00011000HEX_W6[7]
00100001OMUX_N11
00100010HEX_E6[7]
00100100OUT_BEST[6]
00101000HEX_N6[7]
01000001DBL_E2[7]
01000010DBL_S1[7]
01000100DBL_S2[9]
01001000DBL_N1[7]
10000001DBL_E2[9]
10000010HEX_N3[7]
10000100HEX_S3[7]
10001000DBL_N2[6]
virtex4 INT switchbox INT muxes DBL_E0[8]
BitsDestination
MAIN[6][70]MAIN[6][69]MAIN[7][69]MAIN[7][70]MAIN[5][71]MAIN[4][70]MAIN[4][69]MAIN[5][68]DBL_E0[8]
Source
00000000off
00010001OMUX_ES7
00010010HEX_S6[9]
00010100OUT_BEST[0]
00011000HEX_W6[8]
00100001OMUX_E13
00100010HEX_E6[8]
00100100OUT_BEST[7]
00101000HEX_N6[8]
01000001DBL_E2[8]
01000010DBL_S1[8]
01000100DBL_S3[0]
01001000DBL_N1[8]
10000001DBL_E2_S[0]
10000010HEX_N3[8]
10000100HEX_S3[8]
10001000DBL_N2[7]
virtex4 INT switchbox INT muxes DBL_E0[9]
BitsDestination
MAIN[6][78]MAIN[6][77]MAIN[7][78]MAIN[7][77]MAIN[5][79]MAIN[4][77]MAIN[5][76]MAIN[4][78]DBL_E0[9]
Source
00000000off
00010001OMUX[15]
00010010OMUX_N15
00010100HEX_E6[9]
00011000HEX_N6[9]
00100001OMUX_S0_ALT
00100010OMUX_S2
00100100HEX_S7[0]
00101000HEX_W6[9]
01000001DBL_S3[1]
01000010DBL_E2[9]
01000100DBL_S1[9]
01001000DBL_N1[9]
10000001HEX_S3[9]
10000010DBL_E2_S[1]
10000100HEX_N3[9]
10001000DBL_N2[8]
virtex4 INT switchbox INT muxes DBL_S0[0]
BitsDestination
MAIN[4][1]MAIN[5][3]MAIN[5][0]MAIN[4][2]MAIN[6][2]MAIN[6][1]MAIN[7][2]MAIN[7][1]DBL_S0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_BEST[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX[2]
00100010OMUX_S0
00100100DBL_S2[0]
00101000DBL_S2[2]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex4 INT switchbox INT muxes DBL_S0[1]
BitsDestination
MAIN[6][10]MAIN[6][9]MAIN[7][9]MAIN[7][10]MAIN[4][10]MAIN[4][9]MAIN[5][11]MAIN[5][8]DBL_S0[1]
Source
00000000off
00010001OMUX[2]
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_BEST[2]
00100001OMUX_E2
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_BEST[4]
01000001DBL_S2[1]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_S2[3]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex4 INT switchbox INT muxes DBL_S0[2]
BitsDestination
MAIN[4][17]MAIN[5][19]MAIN[5][16]MAIN[4][18]MAIN[6][18]MAIN[6][17]MAIN[7][17]MAIN[7][18]DBL_S0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_BEST[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX[6]
00100010OMUX_S4
00100100DBL_S2[2]
00101000DBL_S2[4]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex4 INT switchbox INT muxes DBL_S0[3]
BitsDestination
MAIN[6][26]MAIN[6][25]MAIN[7][26]MAIN[7][25]MAIN[4][26]MAIN[4][25]MAIN[5][27]MAIN[5][24]DBL_S0[3]
Source
00000000off
00010001OMUX[6]
00010010HEX_W6[2]
00010100HEX_S6[3]
00011000OUT_BEST[3]
00100001OMUX_W6
00100010HEX_N6[3]
00100100HEX_E6[3]
00101000OUT_BEST[4]
01000001DBL_S2[3]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_S2[5]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex4 INT switchbox INT muxes DBL_S0[4]
BitsDestination
MAIN[6][34]MAIN[6][33]MAIN[7][33]MAIN[7][34]MAIN[4][34]MAIN[4][33]MAIN[5][35]MAIN[5][32]DBL_S0[4]
Source
00000000off
00010001OMUX_WS1
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_BEST[5]
00100001OMUX_SE3
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_BEST[2]
01000001DBL_S2[4]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_S2[6]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex4 INT switchbox INT muxes DBL_S0[5]
BitsDestination
MAIN[6][42]MAIN[6][41]MAIN[7][41]MAIN[7][42]MAIN[4][42]MAIN[4][41]MAIN[5][43]MAIN[5][40]DBL_S0[5]
Source
00000000off
00010001OMUX_S3
00010010HEX_N6[5]
00010100HEX_E6[5]
00011000OUT_BEST[1]
00100001OMUX_E8
00100010HEX_W6[4]
00100100HEX_S6[5]
00101000OUT_BEST[6]
01000001DBL_S2[5]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_S2[7]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex4 INT switchbox INT muxes DBL_S0[6]
BitsDestination
MAIN[6][50]MAIN[6][49]MAIN[7][49]MAIN[7][50]MAIN[4][50]MAIN[4][49]MAIN[5][51]MAIN[5][48]DBL_S0[6]
Source
00000000off
00010001OMUX_SW5
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_BEST[0]
00100001OMUX_ES7
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_BEST[7]
01000001DBL_S2[6]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_S2[8]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex4 INT switchbox INT muxes DBL_S0[7]
BitsDestination
MAIN[4][57]MAIN[5][59]MAIN[5][56]MAIN[4][58]MAIN[6][58]MAIN[6][57]MAIN[7][58]MAIN[7][57]DBL_S0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_BEST[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_SE3
00100010OMUX_WS1
00100100DBL_S2[7]
00101000DBL_S2[9]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex4 INT switchbox INT muxes DBL_S0[8]
BitsDestination
MAIN[6][66]MAIN[6][65]MAIN[7][66]MAIN[7][65]MAIN[4][66]MAIN[4][65]MAIN[5][67]MAIN[5][64]DBL_S0[8]
Source
00000000off
00010001OMUX_S5
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_BEST[1]
00100001OMUX_W14
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_BEST[7]
01000001DBL_S2[8]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_S3[0]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex4 INT switchbox INT muxes DBL_S0[9]
BitsDestination
MAIN[4][73]MAIN[5][75]MAIN[5][72]MAIN[4][74]MAIN[6][74]MAIN[6][73]MAIN[7][73]MAIN[7][74]DBL_S0[9]
Source
00000000off
00010001OMUX[15]
00010010OUT_BEST[0]
00010100DBL_E2_S[0]
00011000HEX_E3[9]
00100001OMUX_SW5
00100010OMUX_ES7
00100100DBL_S2[9]
00101000DBL_S3[1]
01000001HEX_N6[9]
01000010HEX_W6[8]
01000100DBL_W1[9]
01001000DBL_W2[7]
10000001HEX_E6[9]
10000010HEX_S6[9]
10000100DBL_E1[9]
10001000HEX_W3[9]
virtex4 INT switchbox INT muxes DBL_N0[0]
BitsDestination
MAIN[4][3]MAIN[4][0]MAIN[5][2]MAIN[5][1]MAIN[6][3]MAIN[6][0]MAIN[7][3]MAIN[7][0]DBL_N0[0]
Source
00000000off
00010001OMUX[0]
00010010OUT_BEST[3]
00010100DBL_E2[1]
00011000HEX_E3[0]
00100001OMUX_N13
00100010OMUX_EN8
00100100DBL_N3[8]
00101000DBL_N2[0]
01000001HEX_W6_N[9]
01000010HEX_N6[0]
01000100DBL_W1[0]
01001000DBL_W2_N[8]
10000001HEX_S6[0]
10000010HEX_E6[0]
10000100DBL_E1[0]
10001000HEX_W3[0]
virtex4 INT switchbox INT muxes DBL_N0[1]
BitsDestination
MAIN[6][11]MAIN[6][8]MAIN[7][8]MAIN[7][11]MAIN[5][9]MAIN[4][11]MAIN[4][8]MAIN[5][10]DBL_N0[1]
Source
00000000off
00010001OMUX_N10
00010010HEX_N6[1]
00010100HEX_E6[1]
00011000OUT_BEST[2]
00100001OMUX_NW10
00100010HEX_W6[0]
00100100HEX_S6[1]
00101000OUT_BEST[4]
01000001DBL_N3[9]
01000010DBL_W1[1]
01000100DBL_E1[1]
01001000DBL_E2[2]
10000001DBL_N2[1]
10000010DBL_W2_N[9]
10000100HEX_W3[1]
10001000HEX_E3[1]
virtex4 INT switchbox INT muxes DBL_N0[2]
BitsDestination
MAIN[4][19]MAIN[4][16]MAIN[5][18]MAIN[5][17]MAIN[6][19]MAIN[6][16]MAIN[7][16]MAIN[7][19]DBL_N0[2]
Source
00000000off
00010001OMUX[4]
00010010OUT_BEST[5]
00010100DBL_E2[3]
00011000HEX_E3[2]
00100001OMUX_NE12
00100010OMUX_W1
00100100DBL_N2[0]
00101000DBL_N2[2]
01000001HEX_N6[2]
01000010HEX_W6[1]
01000100DBL_W1[2]
01001000DBL_W2[0]
10000001HEX_E6[2]
10000010HEX_S6[2]
10000100DBL_E1[2]
10001000HEX_W3[2]
virtex4 INT switchbox INT muxes DBL_N0[3]
BitsDestination
MAIN[6][27]MAIN[6][24]MAIN[7][24]MAIN[7][27]MAIN[5][25]MAIN[4][27]MAIN[4][24]MAIN[5][26]DBL_N0[3]
Source
00000000off
00010001OMUX_EN8
00010010HEX_N6[3]
00010100HEX_E6[3]
00011000OUT_BEST[4]
00100001OMUX_WN14
00100010HEX_W6[2]
00100100HEX_S6[3]
00101000OUT_BEST[3]
01000001DBL_N2[1]
01000010DBL_W1[3]
01000100DBL_E1[3]
01001000DBL_E2[4]
10000001DBL_N2[3]
10000010DBL_W2[1]
10000100HEX_W3[3]
10001000HEX_E3[3]
virtex4 INT switchbox INT muxes DBL_N0[4]
BitsDestination
MAIN[6][35]MAIN[6][32]MAIN[7][32]MAIN[7][35]MAIN[5][33]MAIN[4][35]MAIN[4][32]MAIN[5][34]DBL_N0[4]
Source
00000000off
00010001OMUX_E7
00010010HEX_N6[4]
00010100HEX_E6[4]
00011000OUT_BEST[5]
00100001OMUX_NW10
00100010HEX_W6[3]
00100100HEX_S6[4]
00101000OUT_BEST[2]
01000001DBL_N2[2]
01000010DBL_W1[4]
01000100DBL_E1[4]
01001000DBL_E2[5]
10000001DBL_N2[4]
10000010DBL_W2[2]
10000100HEX_W3[4]
10001000HEX_E3[4]
virtex4 INT switchbox INT muxes DBL_N0[5]
BitsDestination
MAIN[6][43]MAIN[6][40]MAIN[7][43]MAIN[7][40]MAIN[5][41]MAIN[4][43]MAIN[4][40]MAIN[5][42]DBL_N0[5]
Source
00000000off
00010001OMUX_N12
00010010HEX_W6[4]
00010100HEX_S6[5]
00011000OUT_BEST[6]
00100001OMUX_NE12
00100010HEX_N6[5]
00100100HEX_E6[5]
00101000OUT_BEST[1]
01000001DBL_N2[3]
01000010DBL_W1[5]
01000100DBL_E1[5]
01001000DBL_E2[6]
10000001DBL_N2[5]
10000010DBL_W2[3]
10000100HEX_W3[5]
10001000HEX_E3[5]
virtex4 INT switchbox INT muxes DBL_N0[6]
BitsDestination
MAIN[6][51]MAIN[6][48]MAIN[7][48]MAIN[7][51]MAIN[5][49]MAIN[4][51]MAIN[4][48]MAIN[5][50]DBL_N0[6]
Source
00000000off
00010001OMUX[9]
00010010HEX_N6[6]
00010100HEX_E6[6]
00011000OUT_BEST[0]
00100001OMUX_WN14
00100010HEX_W6[5]
00100100HEX_S6[6]
00101000OUT_BEST[7]
01000001DBL_N2[4]
01000010DBL_W1[6]
01000100DBL_E1[6]
01001000DBL_E2[7]
10000001DBL_N2[6]
10000010DBL_W2[4]
10000100HEX_W3[6]
10001000HEX_E3[6]
virtex4 INT switchbox INT muxes DBL_N0[7]
BitsDestination
MAIN[4][59]MAIN[4][56]MAIN[5][58]MAIN[5][57]MAIN[6][59]MAIN[6][56]MAIN[7][59]MAIN[7][56]DBL_N0[7]
Source
00000000off
00010001OMUX[11]
00010010OUT_BEST[6]
00010100DBL_E2[8]
00011000HEX_E3[7]
00100001OMUX_W9
00100010OMUX_N11
00100100DBL_N2[5]
00101000DBL_N2[7]
01000001HEX_W6[6]
01000010HEX_N6[7]
01000100DBL_W1[7]
01001000DBL_W2[5]
10000001HEX_S6[7]
10000010HEX_E6[7]
10000100DBL_E1[7]
10001000HEX_W3[7]
virtex4 INT switchbox INT muxes DBL_N0[8]
BitsDestination
MAIN[6][67]MAIN[6][64]MAIN[7][67]MAIN[7][64]MAIN[5][65]MAIN[4][67]MAIN[4][64]MAIN[5][66]DBL_N0[8]
Source
00000000off
00010001OMUX[9]
00010010HEX_W6[7]
00010100HEX_S6[8]
00011000OUT_BEST[1]
00100001OMUX_E13
00100010HEX_N6[8]
00100100HEX_E6[8]
00101000OUT_BEST[7]
01000001DBL_N2[6]
01000010DBL_W1[8]
01000100DBL_E1[8]
01001000DBL_E2[9]
10000001DBL_N2[8]
10000010DBL_W2[6]
10000100HEX_W3[8]
10001000HEX_E3[8]
virtex4 INT switchbox INT muxes DBL_N0[9]
BitsDestination
MAIN[6][75]MAIN[6][72]MAIN[7][75]MAIN[7][72]MAIN[4][75]MAIN[4][72]MAIN[5][73]MAIN[5][74]DBL_N0[9]
Source
00000000off
00010001OMUX[13]
00010010OUT_BEST[0]
00010100HEX_W6[8]
00011000HEX_S6[9]
00100001OMUX_N15
00100010OMUX[15]
00100100HEX_N6[9]
00101000HEX_E6[9]
01000001DBL_N2[7]
01000010DBL_E2_S[0]
01000100DBL_W1[9]
01001000DBL_E1[9]
10000001DBL_N2[9]
10000010HEX_E3[9]
10000100DBL_W2[7]
10001000HEX_W3[9]
virtex4 INT switchbox INT muxes HEX_W0[0]
BitsDestination
MAIN[1][5]MAIN[1][6]MAIN[1][4]MAIN[2][4]MAIN[2][7]MAIN[3][7]MAIN[3][4]HEX_W0[0]
Source
0000000off
0010001OMUX_S0
0010010OMUX_NW10
0010100HEX_W6[0]
0011000HEX_W6_N[8]
0100001OUT_BEST[3]
0100010HEX_S3[0]
0100100LV[18]
0101000HEX_N7[9]
1000001HEX_S6[2]
1000010OUT_BEST[4]
1000100HEX_N3[0]
1001000LH[6]
virtex4 INT switchbox INT muxes HEX_W0[1]
BitsDestination
MAIN[0][12]MAIN[0][15]MAIN[1][15]MAIN[2][13]MAIN[2][14]MAIN[3][14]MAIN[3][13]HEX_W0[1]
Source
0000000off
0010001OMUX[2]
0010010OMUX_W1
0010100HEX_W6[1]
0011000HEX_W6_N[9]
0100001OUT_BEST[2]
0100010HEX_S3[1]
0100100LV[18]
0101000HEX_N6[0]
1000001HEX_S6[3]
1000010OUT_BEST[5]
1000100HEX_N3[1]
1001000LH[6]
virtex4 INT switchbox INT muxes HEX_W0[2]
BitsDestination
MAIN[1][21]MAIN[1][20]MAIN[1][22]MAIN[2][23]MAIN[2][20]MAIN[3][23]MAIN[3][20]HEX_W0[2]
Source
0000000off
0010001OMUX[4]
0010010HEX_S3[2]
0010100HEX_N6[1]
0011000LV[12]
0100001OMUX[6]
0100010OMUX_WN14
0100100HEX_W6[0]
0101000HEX_W6[2]
1000001HEX_S6[4]
1000010OUT_BEST[3]
1000100LH[0]
1001000HEX_N3[2]
virtex4 INT switchbox INT muxes HEX_W0[3]
BitsDestination
MAIN[0][28]MAIN[0][31]MAIN[1][31]MAIN[2][30]MAIN[2][29]MAIN[3][30]MAIN[3][29]HEX_W0[3]
Source
0000000off
0010001OMUX_W6
0010010OMUX_NW10
0010100HEX_W6[1]
0011000HEX_W6[3]
0100001OUT_BEST[4]
0100010HEX_S3[3]
0100100HEX_N6[2]
0101000LV[12]
1000001HEX_S6[5]
1000010OUT_BEST[2]
1000100LH[0]
1001000HEX_N3[3]
virtex4 INT switchbox INT muxes HEX_W0[4]
BitsDestination
MAIN[1][37]MAIN[1][38]MAIN[1][36]MAIN[2][39]MAIN[2][36]MAIN[3][39]MAIN[3][36]HEX_W0[4]
Source
0000000off
0010001OMUX_WS1
0010010OMUX_N12
0010100HEX_W6[2]
0011000HEX_W6[4]
0100001OUT_BEST[5]
0100010HEX_S3[4]
0100100HEX_N6[3]
0101000LH[12]
1000001HEX_S6[6]
1000010OUT_BEST[6]
1000100LV[0]
1001000HEX_N3[4]
virtex4 INT switchbox INT muxes HEX_W0[5]
BitsDestination
MAIN[0][44]MAIN[0][47]MAIN[1][47]MAIN[2][46]MAIN[2][45]MAIN[3][46]MAIN[3][45]HEX_W0[5]
Source
0000000off
0010001OMUX_S3
0010010OMUX_WN14
0010100HEX_W6[3]
0011000HEX_W6[5]
0100001OUT_BEST[1]
0100010HEX_S3[5]
0100100HEX_N6[4]
0101000LH[12]
1000001HEX_S6[7]
1000010OUT_BEST[7]
1000100LV[0]
1001000HEX_N3[5]
virtex4 INT switchbox INT muxes HEX_W0[6]
BitsDestination
MAIN[1][54]MAIN[1][52]MAIN[1][53]MAIN[2][55]MAIN[2][52]MAIN[3][52]MAIN[3][55]HEX_W0[6]
Source
0000000off
0010001OMUX[11]
0010010HEX_S6[8]
0010100LH[18]
0011000HEX_N3[6]
0100001OMUX_W9
0100010OMUX_SW5
0100100HEX_W6[4]
0101000HEX_W6[6]
1000001HEX_S3[6]
1000010OUT_BEST[0]
1000100HEX_N6[5]
1001000LV[6]
virtex4 INT switchbox INT muxes HEX_W0[7]
BitsDestination
MAIN[0][60]MAIN[0][63]MAIN[1][63]MAIN[2][62]MAIN[2][61]MAIN[3][61]MAIN[3][62]HEX_W0[7]
Source
0000000off
0010001OMUX[9]
0010010OMUX_WS1
0010100HEX_W6[5]
0011000HEX_W6[7]
0100001HEX_S3[7]
0100010OUT_BEST[6]
0100100HEX_N6[6]
0101000LV[6]
1000001OUT_BEST[1]
1000010HEX_S6[9]
1000100LH[18]
1001000HEX_N3[7]
virtex4 INT switchbox INT muxes HEX_W0[8]
BitsDestination
MAIN[1][69]MAIN[1][70]MAIN[1][68]MAIN[2][71]MAIN[2][68]MAIN[3][68]MAIN[3][71]HEX_W0[8]
Source
0000000off
0010001OMUX[13]
0010010OMUX_W14
0010100HEX_W6[6]
0011000HEX_W6[8]
0100001HEX_S3[8]
0100010OUT_BEST[7]
0100100HEX_N6[7]
0101000LV[24]
1000001OUT_BEST[0]
1000010HEX_S7[0]
1000100LH[24]
1001000HEX_N3[8]
virtex4 INT switchbox INT muxes HEX_W0[9]
BitsDestination
MAIN[0][76]MAIN[0][79]MAIN[1][79]MAIN[2][78]MAIN[2][77]MAIN[3][77]MAIN[3][78]HEX_W0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX_SW5
0010100HEX_W6[7]
0011000HEX_W6[9]
0100001HEX_S3[9]
0100010OMUX[15]
0100100HEX_N6[8]
0101000LV[24]
1000001OMUX_S0_ALT
1000010HEX_S7[1]
1000100LH[24]
1001000HEX_N3[9]
virtex4 INT switchbox INT muxes HEX_E0[0]
BitsDestination
MAIN[0][4]MAIN[0][7]MAIN[1][7]MAIN[2][6]MAIN[2][5]MAIN[3][5]MAIN[3][6]HEX_E0[0]
Source
0000000off
0010001OMUX_E2
0010010OMUX_EN8
0010100HEX_E6[0]
0011000HEX_E6[2]
0100001HEX_S3[0]
0100010OUT_BEST[3]
0100100HEX_N7[9]
0101000LV[18]
1000001OUT_BEST[4]
1000010HEX_S6[2]
1000100LH[6]
1001000HEX_N3[0]
virtex4 INT switchbox INT muxes HEX_E0[1]
BitsDestination
MAIN[1][13]MAIN[1][14]MAIN[1][12]MAIN[2][15]MAIN[2][12]MAIN[3][12]MAIN[3][15]HEX_E0[1]
Source
0000000off
0010001OMUX_S4
0010010OMUX_N10
0010100HEX_E6[1]
0011000HEX_E6[3]
0100001HEX_S3[1]
0100010OUT_BEST[2]
0100100HEX_N6[0]
0101000LV[18]
1000001OUT_BEST[5]
1000010HEX_S6[3]
1000100LH[6]
1001000HEX_N3[1]
virtex4 INT switchbox INT muxes HEX_E0[2]
BitsDestination
MAIN[0][20]MAIN[1][23]MAIN[0][23]MAIN[2][22]MAIN[2][21]MAIN[3][22]MAIN[3][21]HEX_E0[2]
Source
0000000off
0010001OMUX[4]
0010010HEX_S3[2]
0010100HEX_N6[1]
0011000LV[12]
0100001OMUX_NE12
0100010OMUX[6]
0100100HEX_E6[2]
0101000HEX_E6[4]
1000001HEX_S6[4]
1000010OUT_BEST[3]
1000100LH[0]
1001000HEX_N3[2]
virtex4 INT switchbox INT muxes HEX_E0[3]
BitsDestination
MAIN[1][29]MAIN[1][30]MAIN[1][28]MAIN[2][31]MAIN[2][28]MAIN[3][28]MAIN[3][31]HEX_E0[3]
Source
0000000off
0010001OMUX_SE3
0010010OMUX_EN8
0010100HEX_E6[3]
0011000HEX_E6[5]
0100001HEX_S3[3]
0100010OUT_BEST[4]
0100100HEX_N6[2]
0101000LV[12]
1000001OUT_BEST[2]
1000010HEX_S6[5]
1000100LH[0]
1001000HEX_N3[3]
virtex4 INT switchbox INT muxes HEX_E0[4]
BitsDestination
MAIN[0][36]MAIN[0][39]MAIN[1][39]MAIN[2][38]MAIN[2][37]MAIN[3][38]MAIN[3][37]HEX_E0[4]
Source
0000000off
0010001OMUX_E7
0010010OMUX_E8
0010100HEX_E6[4]
0011000HEX_E6[6]
0100001OUT_BEST[5]
0100010HEX_S3[4]
0100100HEX_N6[3]
0101000LH[12]
1000001HEX_S6[6]
1000010OUT_BEST[6]
1000100LV[0]
1001000HEX_N3[4]
virtex4 INT switchbox INT muxes HEX_E0[5]
BitsDestination
MAIN[1][45]MAIN[1][46]MAIN[1][44]MAIN[2][47]MAIN[2][44]MAIN[3][44]MAIN[3][47]HEX_E0[5]
Source
0000000off
0010001OMUX_ES7
0010010OMUX_NE12
0010100HEX_E6[5]
0011000HEX_E6[7]
0100001HEX_S3[5]
0100010OUT_BEST[1]
0100100HEX_N6[4]
0101000LH[12]
1000001OUT_BEST[7]
1000010HEX_S6[7]
1000100LV[0]
1001000HEX_N3[5]
virtex4 INT switchbox INT muxes HEX_E0[6]
BitsDestination
MAIN[0][55]MAIN[0][52]MAIN[1][55]MAIN[2][54]MAIN[2][53]MAIN[3][54]MAIN[3][53]HEX_E0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX_SE3
0010100HEX_E6[6]
0011000HEX_E6[8]
0100001HEX_S6[8]
0100010OMUX[11]
0100100LH[18]
0101000HEX_N3[6]
1000001OUT_BEST[0]
1000010HEX_S3[6]
1000100HEX_N6[5]
1001000LV[6]
virtex4 INT switchbox INT muxes HEX_E0[7]
BitsDestination
MAIN[1][61]MAIN[1][62]MAIN[1][60]MAIN[2][63]MAIN[2][60]MAIN[3][60]MAIN[3][63]HEX_E0[7]
Source
0000000off
0010001OMUX_S5
0010010OMUX_N11
0010100HEX_E6[7]
0011000HEX_E6[9]
0100001HEX_S3[7]
0100010OUT_BEST[6]
0100100HEX_N6[6]
0101000LV[6]
1000001OUT_BEST[1]
1000010HEX_S6[9]
1000100LH[18]
1001000HEX_N3[7]
virtex4 INT switchbox INT muxes HEX_E0[8]
BitsDestination
MAIN[0][68]MAIN[0][71]MAIN[1][71]MAIN[2][70]MAIN[2][69]MAIN[3][69]MAIN[3][70]HEX_E0[8]
Source
0000000off
0010001OMUX_ES7
0010010OMUX_E13
0010100HEX_E6[8]
0011000HEX_E6_S[0]
0100001HEX_S3[8]
0100010OUT_BEST[7]
0100100HEX_N6[7]
0101000LV[24]
1000001OUT_BEST[0]
1000010HEX_S7[0]
1000100LH[24]
1001000HEX_N3[8]
virtex4 INT switchbox INT muxes HEX_E0[9]
BitsDestination
MAIN[1][76]MAIN[1][77]MAIN[1][78]MAIN[2][79]MAIN[2][76]MAIN[3][79]MAIN[3][76]HEX_E0[9]
Source
0000000off
0010001OMUX[15]
0010010HEX_S3[9]
0010100HEX_N6[8]
0011000LV[24]
0100001HEX_S7[1]
0100010OMUX_S0_ALT
0100100LH[24]
0101000HEX_N3[9]
1000001OMUX_N15
1000010OMUX_S2
1000100HEX_E6[9]
1001000HEX_E6_S[1]
virtex4 INT switchbox INT muxes HEX_S0[0]
BitsDestination
MAIN[0][0]MAIN[1][3]MAIN[0][3]MAIN[2][1]MAIN[2][2]MAIN[3][2]MAIN[3][1]HEX_S0[0]
Source
0000000off
0010001OMUX[0]
0010010HEX_E3[0]
0010100LV[18]
0011000HEX_W6_N[8]
0100001OMUX[2]
0100010OMUX_S0
0100100HEX_S6[2]
0101000HEX_S6[0]
1000001HEX_E6[1]
1000010OUT_BEST[3]
1000100HEX_W3[0]
1001000LH[6]
virtex4 INT switchbox INT muxes HEX_S0[1]
BitsDestination
MAIN[1][10]MAIN[1][9]MAIN[1][8]MAIN[2][8]MAIN[2][11]MAIN[3][8]MAIN[3][11]HEX_S0[1]
Source
0000000off
0010001OMUX[2]
0010010OMUX_E2
0010100HEX_S6[3]
0011000HEX_S6[1]
0100001OUT_BEST[2]
0100010HEX_E6[2]
0100100HEX_W3[1]
0101000LH[6]
1000001HEX_E3[1]
1000010OUT_BEST[4]
1000100LV[18]
1001000HEX_W6_N[9]
virtex4 INT switchbox INT muxes HEX_S0[2]
BitsDestination
MAIN[0][19]MAIN[1][19]MAIN[0][16]MAIN[2][17]MAIN[2][18]MAIN[3][17]MAIN[3][18]HEX_S0[2]
Source
0000000off
0010001OMUX[4]
0010010HEX_E6[3]
0010100HEX_W3[2]
0011000LH[0]
0100001OMUX[6]
0100010OMUX_S4
0100100HEX_S6[4]
0101000HEX_S6[2]
1000001HEX_E3[2]
1000010OUT_BEST[5]
1000100LV[12]
1001000HEX_W6[0]
virtex4 INT switchbox INT muxes HEX_S0[3]
BitsDestination
MAIN[1][26]MAIN[1][25]MAIN[1][24]MAIN[2][24]MAIN[2][27]MAIN[3][27]MAIN[3][24]HEX_S0[3]
Source
0000000off
0010001OMUX[6]
0010010OMUX_W6
0010100HEX_S6[5]
0011000HEX_S6[3]
0100001HEX_E6[4]
0100010OUT_BEST[4]
0100100HEX_W3[3]
0101000LH[0]
1000001OUT_BEST[3]
1000010HEX_E3[3]
1000100LV[12]
1001000HEX_W6[1]
virtex4 INT switchbox INT muxes HEX_S0[4]
BitsDestination
MAIN[0][35]MAIN[0][32]MAIN[1][35]MAIN[2][33]MAIN[2][34]MAIN[3][33]MAIN[3][34]HEX_S0[4]
Source
0000000off
0010001OMUX_WS1
0010010OMUX_SE3
0010100HEX_S6[6]
0011000HEX_S6[4]
0100001OUT_BEST[5]
0100010HEX_E6[5]
0100100HEX_W3[4]
0101000LV[0]
1000001HEX_E3[4]
1000010OUT_BEST[2]
1000100LH[12]
1001000HEX_W6[2]
virtex4 INT switchbox INT muxes HEX_S0[5]
BitsDestination
MAIN[1][42]MAIN[1][41]MAIN[1][40]MAIN[2][40]MAIN[2][43]MAIN[3][40]MAIN[3][43]HEX_S0[5]
Source
0000000off
0010001OMUX_S3
0010010OMUX_E8
0010100HEX_S6[7]
0011000HEX_S6[5]
0100001OUT_BEST[1]
0100010HEX_E6[6]
0100100HEX_W3[5]
0101000LV[0]
1000001HEX_E3[5]
1000010OUT_BEST[6]
1000100LH[12]
1001000HEX_W6[3]
virtex4 INT switchbox INT muxes HEX_S0[6]
BitsDestination
MAIN[0][51]MAIN[0][48]MAIN[1][51]MAIN[2][49]MAIN[2][50]MAIN[3][49]MAIN[3][50]HEX_S0[6]
Source
0000000off
0010001OMUX_SW5
0010010OMUX_ES7
0010100HEX_S6[8]
0011000HEX_S6[6]
0100001OUT_BEST[0]
0100010HEX_E6[7]
0100100HEX_W3[6]
0101000LH[18]
1000001HEX_E3[6]
1000010OUT_BEST[7]
1000100LV[6]
1001000HEX_W6[4]
virtex4 INT switchbox INT muxes HEX_S0[7]
BitsDestination
MAIN[1][57]MAIN[1][56]MAIN[1][58]MAIN[2][56]MAIN[2][59]MAIN[3][59]MAIN[3][56]HEX_S0[7]
Source
0000000off
0010001OMUX[11]
0010010HEX_E3[7]
0010100LV[6]
0011000HEX_W6[5]
0100001OMUX_SE3
0100010OMUX_WS1
0100100HEX_S6[9]
0101000HEX_S6[7]
1000001HEX_E6[8]
1000010OUT_BEST[6]
1000100HEX_W3[7]
1001000LH[18]
virtex4 INT switchbox INT muxes HEX_S0[8]
BitsDestination
MAIN[0][67]MAIN[0][64]MAIN[1][67]MAIN[2][65]MAIN[2][66]MAIN[3][66]MAIN[3][65]HEX_S0[8]
Source
0000000off
0010001OMUX_S5
0010010OMUX_W14
0010100HEX_S7[0]
0011000HEX_S6[8]
0100001HEX_E6[9]
0100010OUT_BEST[7]
0100100HEX_W3[8]
0101000LH[24]
1000001OUT_BEST[1]
1000010HEX_E3[8]
1000100LV[24]
1001000HEX_W6[6]
virtex4 INT switchbox INT muxes HEX_S0[9]
BitsDestination
MAIN[1][74]MAIN[1][72]MAIN[1][73]MAIN[2][72]MAIN[2][75]MAIN[3][72]MAIN[3][75]HEX_S0[9]
Source
0000000off
0010001OMUX[15]
0010010HEX_E6_S[0]
0010100HEX_W3[9]
0011000LH[24]
0100001OMUX_SW5
0100010OMUX_ES7
0100100HEX_S7[1]
0101000HEX_S6[9]
1000001HEX_E3[9]
1000010OUT_BEST[0]
1000100LV[24]
1001000HEX_W6[7]
virtex4 INT switchbox INT muxes HEX_N0[0]
BitsDestination
MAIN[1][1]MAIN[1][0]MAIN[1][2]MAIN[2][0]MAIN[2][3]MAIN[3][3]MAIN[3][0]HEX_N0[0]
Source
0000000off
0010001OMUX[0]
0010010HEX_E3[0]
0010100LV[18]
0011000HEX_W6_N[8]
0100001OMUX_N13
0100010OMUX_EN8
0100100HEX_N6[0]
0101000HEX_N7[8]
1000001HEX_E6[1]
1000010OUT_BEST[3]
1000100HEX_W3[0]
1001000LH[6]
virtex4 INT switchbox INT muxes HEX_N0[1]
BitsDestination
MAIN[0][11]MAIN[0][8]MAIN[1][11]MAIN[2][9]MAIN[2][10]MAIN[3][9]MAIN[3][10]HEX_N0[1]
Source
0000000off
0010001OMUX_N10
0010010OMUX_NW10
0010100HEX_N6[1]
0011000HEX_N7[9]
0100001OUT_BEST[2]
0100010HEX_E6[2]
0100100HEX_W3[1]
0101000LH[6]
1000001HEX_E3[1]
1000010OUT_BEST[4]
1000100LV[18]
1001000HEX_W6_N[9]
virtex4 INT switchbox INT muxes HEX_N0[2]
BitsDestination
MAIN[1][18]MAIN[1][16]MAIN[1][17]MAIN[2][16]MAIN[2][19]MAIN[3][16]MAIN[3][19]HEX_N0[2]
Source
0000000off
0010001OMUX[4]
0010010HEX_E6[3]
0010100HEX_W3[2]
0011000LH[0]
0100001OMUX_NE12
0100010OMUX_W1
0100100HEX_N6[2]
0101000HEX_N6[0]
1000001HEX_E3[2]
1000010OUT_BEST[5]
1000100LV[12]
1001000HEX_W6[0]
virtex4 INT switchbox INT muxes HEX_N0[3]
BitsDestination
MAIN[0][27]MAIN[0][24]MAIN[1][27]MAIN[2][25]MAIN[2][26]MAIN[3][25]MAIN[3][26]HEX_N0[3]
Source
0000000off
0010001OMUX_EN8
0010010OMUX_WN14
0010100HEX_N6[3]
0011000HEX_N6[1]
0100001OUT_BEST[4]
0100010HEX_E6[4]
0100100HEX_W3[3]
0101000LH[0]
1000001HEX_E3[3]
1000010OUT_BEST[3]
1000100LV[12]
1001000HEX_W6[1]
virtex4 INT switchbox INT muxes HEX_N0[4]
BitsDestination
MAIN[1][34]MAIN[1][33]MAIN[1][32]MAIN[2][32]MAIN[2][35]MAIN[3][32]MAIN[3][35]HEX_N0[4]
Source
0000000off
0010001OMUX_E7
0010010OMUX_NW10
0010100HEX_N6[4]
0011000HEX_N6[2]
0100001OUT_BEST[5]
0100010HEX_E6[5]
0100100HEX_W3[4]
0101000LV[0]
1000001HEX_E3[4]
1000010OUT_BEST[2]
1000100LH[12]
1001000HEX_W6[2]
virtex4 INT switchbox INT muxes HEX_N0[5]
BitsDestination
MAIN[0][43]MAIN[0][40]MAIN[1][43]MAIN[2][41]MAIN[2][42]MAIN[3][42]MAIN[3][41]HEX_N0[5]
Source
0000000off
0010001OMUX_N12
0010010OMUX_NE12
0010100HEX_N6[5]
0011000HEX_N6[3]
0100001HEX_E6[6]
0100010OUT_BEST[1]
0100100HEX_W3[5]
0101000LV[0]
1000001OUT_BEST[6]
1000010HEX_E3[5]
1000100LH[12]
1001000HEX_W6[3]
virtex4 INT switchbox INT muxes HEX_N0[6]
BitsDestination
MAIN[1][50]MAIN[1][49]MAIN[1][48]MAIN[2][48]MAIN[2][51]MAIN[3][48]MAIN[3][51]HEX_N0[6]
Source
0000000off
0010001OMUX[9]
0010010OMUX_WN14
0010100HEX_N6[6]
0011000HEX_N6[4]
0100001OUT_BEST[0]
0100010HEX_E6[7]
0100100HEX_W3[6]
0101000LH[18]
1000001HEX_E3[6]
1000010OUT_BEST[7]
1000100LV[6]
1001000HEX_W6[4]
virtex4 INT switchbox INT muxes HEX_N0[7]
BitsDestination
MAIN[0][56]MAIN[1][59]MAIN[0][59]MAIN[2][57]MAIN[2][58]MAIN[3][58]MAIN[3][57]HEX_N0[7]
Source
0000000off
0010001OMUX[11]
0010010HEX_E3[7]
0010100LV[6]
0011000HEX_W6[5]
0100001OMUX_W9
0100010OMUX_N11
0100100HEX_N6[7]
0101000HEX_N6[5]
1000001HEX_E6[8]
1000010OUT_BEST[6]
1000100HEX_W3[7]
1001000LH[18]
virtex4 INT switchbox INT muxes HEX_N0[8]
BitsDestination
MAIN[1][66]MAIN[1][65]MAIN[1][64]MAIN[2][64]MAIN[2][67]MAIN[3][67]MAIN[3][64]HEX_N0[8]
Source
0000000off
0010001OMUX[9]
0010010OMUX_E13
0010100HEX_N6[8]
0011000HEX_N6[6]
0100001HEX_E6[9]
0100010OUT_BEST[7]
0100100HEX_W3[8]
0101000LH[24]
1000001OUT_BEST[1]
1000010HEX_E3[8]
1000100LV[24]
1001000HEX_W6[6]
virtex4 INT switchbox INT muxes HEX_N0[9]
BitsDestination
MAIN[0][75]MAIN[0][72]MAIN[1][75]MAIN[2][73]MAIN[2][74]MAIN[3][74]MAIN[3][73]HEX_N0[9]
Source
0000000off
0010001OMUX[13]
0010010OMUX_N15
0010100HEX_N6[9]
0011000HEX_N6[7]
0100001HEX_E6_S[0]
0100010OMUX[15]
0100100HEX_W3[9]
0101000LH[24]
1000001OUT_BEST[0]
1000010HEX_E3[9]
1000100LV[24]
1001000HEX_W6[7]
virtex4 INT switchbox INT muxes LH[0]
BitsDestination
MAIN[0][22]MAIN[0][38]MAIN[0][33]MAIN[0][10]MAIN[0][30]MAIN[0][21]MAIN[0][13]MAIN[0][25]MAIN[0][5]MAIN[0][2]MAIN[18][28]LH[0]
Source
00000000000off
00000000011DBL_W1[1]
00000000101DBL_E1[1]
00000001001DBL_N2[2]
00000010001DBL_S1[1]
00000100001DBL_S2[2]
00001000001OMUX_N10
00010000001DBL_N1[1]
00100000001DBL_E2[2]
01000000001LV[12]
10000000011OMUX[2]
10000000101OMUX[4]
10000001001OMUX_S0
10000010001OMUX_W1
10000100001OMUX_E2
10001000001LV[24]
10010000001DBL_W2[2]
10100000001LH[24]
11000000001LV[0]
virtex4 INT switchbox INT muxes LH[24]
BitsDestination
MAIN[0][57]MAIN[0][41]MAIN[0][58]MAIN[0][49]MAIN[0][66]MAIN[0][74]MAIN[0][69]MAIN[0][54]MAIN[0][77]MAIN[0][46]MAIN[18][51]LH[24]
Source
00000000000off
00000000011OMUX[11]
00000000101DBL_E1[7]
00000001001OMUX_S5
00000010001OMUX_E13
00000100001DBL_S2[8]
00001000001OMUX_N15
00010000001DBL_W1[7]
00100000001DBL_W2[8]
01000000001LV[12]
10000000011LH[0]
10000000101OMUX[13]
10000001001DBL_E2[8]
10000010001DBL_S1[7]
10000100001OMUX_W14
10001000001DBL_N1[7]
10010000001LV[0]
10100000001DBL_N2[8]
11000000001LV[24]
virtex4 INT switchbox INT muxes LV[0]
BitsDestination
MAIN[0][17]MAIN[0][37]MAIN[0][34]MAIN[0][9]MAIN[0][29]MAIN[0][18]MAIN[0][14]MAIN[0][26]MAIN[0][6]MAIN[0][1]MAIN[18][20]LV[0]
Source
00000000000off
00000000011DBL_W1[1]
00000000101DBL_E1[1]
00000001001DBL_N2[2]
00000010001DBL_S1[1]
00000100001DBL_S2[2]
00001000001OMUX_N10
00010000001DBL_N1[1]
00100000001DBL_E2[2]
01000000001LH[0]
10000000011OMUX[2]
10000000101OMUX[4]
10000001001OMUX_S0
10000010001OMUX_W1
10000100001OMUX_E2
10001000001LV[24]
10010000001DBL_W2[2]
10100000001LH[24]
11000000001LH[12]
virtex4 INT switchbox INT muxes LV[24]
BitsDestination
MAIN[0][62]MAIN[0][42]MAIN[0][61]MAIN[0][50]MAIN[0][65]MAIN[0][73]MAIN[0][70]MAIN[0][53]MAIN[0][78]MAIN[0][45]MAIN[18][59]LV[24]
Source
00000000000off
00000000011OMUX[11]
00000000101DBL_E1[7]
00000001001OMUX_S5
00000010001OMUX_E13
00000100001DBL_S2[8]
00001000001OMUX_N15
00010000001DBL_W1[7]
00100000001DBL_W2[8]
01000000001LH[24]
10000000011LH[0]
10000000101OMUX[13]
10000001001DBL_E2[8]
10000010001DBL_S1[7]
10000100001OMUX_W14
10001000001DBL_N1[7]
10010000001LV[0]
10100000001DBL_N2[8]
11000000001LH[12]
virtex4 INT switchbox INT muxes IMUX_SR[0]
BitsDestination
MAIN[14][7]MAIN[14][6]MAIN[15][6]MAIN[15][7]MAIN[14][4]MAIN[15][4]MAIN[15][2]MAIN[14][2]IMUX_SR[0]
Source
00000000off
00010001TIE_1
00010010DBL_E1[0]
00010100DBL_E2[0]
00011000IMUX_BOUNCE[3]
00100001DBL_E0[1]
00100010DBL_W1[0]
00100100DBL_W2[0]
00101000DBL_N1[0]
01000001DBL_E0[0]
01000010IMUX_BOUNCE[2]
01000100IMUX_BOUNCE[1]
01001000IMUX_BOUNCE[0]
10000001DBL_N0[1]
10000010DBL_N2[0]
10000100DBL_S2[0]
10001000DBL_S1[0]
virtex4 INT switchbox INT muxes IMUX_SR[1]
BitsDestination
MAIN[15][15]MAIN[14][15]MAIN[14][14]MAIN[15][14]MAIN[14][12]MAIN[15][12]MAIN[15][10]MAIN[14][10]IMUX_SR[1]
Source
00000000off
00010001TIE_1
00010010DBL_W1[1]
00010100DBL_W2[1]
00011000DBL_N1[1]
00100001DBL_W0[1]
00100010IMUX_BOUNCE[2]
00100100IMUX_BOUNCE[1]
00101000IMUX_BOUNCE[0]
01000001DBL_E0[2]
01000010DBL_N2[1]
01000100DBL_S2[1]
01001000DBL_S1[1]
10000001DBL_S0[1]
10000010DBL_E1[1]
10000100DBL_E2[1]
10001000IMUX_BOUNCE[3]
virtex4 INT switchbox INT muxes IMUX_SR[2]
BitsDestination
MAIN[14][1]MAIN[14][0]MAIN[15][0]MAIN[15][1]MAIN[15][5]MAIN[15][3]MAIN[14][3]MAIN[14][5]IMUX_SR[2]
Source
00000000off
00010001TIE_1
00010010DBL_E1[0]
00010100DBL_E2[0]
00011000IMUX_BOUNCE[3]
00100001DBL_W0[1]
00100010DBL_N2[0]
00100100DBL_S2[0]
00101000DBL_S1[0]
01000001DBL_S0[1]
01000010DBL_W1[0]
01000100DBL_W2[0]
01001000DBL_N1[0]
10000001DBL_E0[0]
10000010IMUX_BOUNCE[2]
10000100IMUX_BOUNCE[1]
10001000IMUX_BOUNCE[0]
virtex4 INT switchbox INT muxes IMUX_SR[3]
BitsDestination
MAIN[15][13]MAIN[15][11]MAIN[14][11]MAIN[14][13]MAIN[14][9]MAIN[15][8]MAIN[15][9]MAIN[14][8]IMUX_SR[3]
Source
00000000off
00010001TIE_1
00010010DBL_E0[1]
00010100DBL_E0[2]
00011000DBL_N0[1]
00100001DBL_W1[1]
00100010DBL_E1[1]
00100100DBL_N2[1]
00101000IMUX_BOUNCE[2]
01000001DBL_W2[1]
01000010DBL_E2[1]
01000100DBL_S2[1]
01001000IMUX_BOUNCE[1]
10000001DBL_N1[1]
10000010IMUX_BOUNCE[3]
10000100DBL_S1[1]
10001000IMUX_BOUNCE[0]
virtex4 INT switchbox INT muxes IMUX_BOUNCE[0]
BitsDestination
MAIN[14][24]MAIN[15][24]MAIN[14][25]MAIN[15][25]MAIN[14][27]MAIN[15][27]MAIN[15][29]MAIN[14][29]IMUX_BOUNCE[0]
Source
00000000off
00010001TIE_0
00010010HCLK[3]
00010100HCLK[4]
00011000HCLK[5]
00100001TIE_1
00100010HCLK[0]
00100100HCLK[1]
00101000HCLK[2]
01000001DBL_W0[4]
01000010HCLK[6]
01000100HCLK[7]
01001000RCLK[0]
10000001DBL_S0[4]
10000010RCLK[1]
10000100OMUX[5]
10001000DBL_E1[3]
virtex4 INT switchbox INT muxes IMUX_BOUNCE[1]
BitsDestination
MAIN[15][30]MAIN[14][31]MAIN[14][30]MAIN[15][31]MAIN[15][26]MAIN[15][28]MAIN[14][28]MAIN[14][26]IMUX_BOUNCE[1]
Source
00000000off
00010001TIE_0
00010010HCLK[3]
00010100HCLK[4]
00011000HCLK[5]
00100001TIE_1
00100010HCLK[0]
00100100HCLK[1]
00101000HCLK[2]
01000001DBL_N0[4]
01000010HCLK[6]
01000100HCLK[7]
01001000RCLK[0]
10000001DBL_E0[4]
10000010RCLK[1]
10000100OMUX[5]
10001000DBL_E1[3]
virtex4 INT switchbox INT muxes IMUX_BOUNCE[2]
BitsDestination
MAIN[15][33]MAIN[14][33]MAIN[14][32]MAIN[15][32]MAIN[14][35]MAIN[15][35]MAIN[15][37]MAIN[14][37]IMUX_BOUNCE[2]
Source
00000000off
00010001TIE_0
00010010HCLK[6]
00010100HCLK[7]
00011000RCLK[0]
00100001TIE_1
00100010RCLK[1]
00100100OMUX[6]
00101000DBL_E1[4]
01000001DBL_N0[4]
01000010HCLK[0]
01000100HCLK[1]
01001000HCLK[2]
10000001DBL_E0[4]
10000010HCLK[3]
10000100HCLK[4]
10001000HCLK[5]
virtex4 INT switchbox INT muxes IMUX_BOUNCE[3]
BitsDestination
MAIN[15][39]MAIN[14][38]MAIN[15][38]MAIN[14][39]MAIN[15][34]MAIN[15][36]MAIN[14][36]MAIN[14][34]IMUX_BOUNCE[3]
Source
00000000off
00010001TIE_0
00010010HCLK[6]
00010100HCLK[7]
00011000RCLK[0]
00100001TIE_1
00100010RCLK[1]
00100100OMUX[6]
00101000DBL_E1[4]
01000001DBL_W0[4]
01000010HCLK[0]
01000100HCLK[1]
01001000HCLK[2]
10000001DBL_S0[4]
10000010HCLK[3]
10000100HCLK[4]
10001000HCLK[5]
virtex4 INT switchbox INT muxes IMUX_CLK[0]
BitsDestination
MAIN[14][42]MAIN[15][42]MAIN[15][44]MAIN[14][44]MAIN[15][46]MAIN[14][47]MAIN[15][47]MAIN[14][46]IMUX_CLK[0]
Source
00000000off
00010001HCLK[0]
00010010HCLK[3]
00010100HCLK[6]
00011000RCLK[1]
00100001HCLK[1]
00100010HCLK[4]
00100100HCLK[7]
00101000DBL_W1[6]
01000001HCLK[2]
01000010HCLK[5]
01000100RCLK[0]
01001000DBL_E1[6]
10000001DBL_E0[5]
10000010DBL_S0[6]
10000100DBL_W0[6]
10001000DBL_N0[6]
virtex4 INT switchbox INT muxes IMUX_CLK[1]
BitsDestination
MAIN[14][45]MAIN[14][43]MAIN[15][43]MAIN[15][45]MAIN[14][40]MAIN[15][40]MAIN[15][41]MAIN[14][41]IMUX_CLK[1]
Source
00000000off
00010001HCLK[0]
00010010HCLK[3]
00010100HCLK[6]
00011000RCLK[1]
00100001HCLK[1]
00100010HCLK[4]
00100100HCLK[7]
00101000DBL_W1[6]
01000001HCLK[2]
01000010HCLK[5]
01000100RCLK[0]
01001000DBL_E1[6]
10000001DBL_E0[5]
10000010DBL_S0[6]
10000100DBL_W0[6]
10001000DBL_N0[6]
virtex4 INT switchbox INT muxes IMUX_CLK[2]
BitsDestination
MAIN[14][50]MAIN[15][50]MAIN[15][52]MAIN[14][52]MAIN[15][54]MAIN[14][55]MAIN[15][55]MAIN[14][54]IMUX_CLK[2]
Source
00000000off
00010001HCLK[0]
00010010HCLK[3]
00010100HCLK[6]
00011000RCLK[1]
00100001HCLK[1]
00100010HCLK[4]
00100100HCLK[7]
00101000DBL_W1[6]
01000001HCLK[2]
01000010HCLK[5]
01000100RCLK[0]
01001000DBL_E1[6]
10000001DBL_W0[6]
10000010DBL_N0[6]
10000100DBL_E0[5]
10001000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_CLK[3]
BitsDestination
MAIN[14][53]MAIN[14][51]MAIN[15][51]MAIN[15][53]MAIN[14][48]MAIN[15][48]MAIN[15][49]MAIN[14][49]IMUX_CLK[3]
Source
00000000off
00010001HCLK[0]
00010010HCLK[3]
00010100HCLK[6]
00011000RCLK[1]
00100001HCLK[1]
00100010HCLK[4]
00100100HCLK[7]
00101000DBL_W1[6]
01000001HCLK[2]
01000010HCLK[5]
01000100RCLK[0]
01001000DBL_E1[6]
10000001DBL_W0[6]
10000010DBL_N0[6]
10000100DBL_E0[5]
10001000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_CE[0]
BitsDestination
MAIN[14][70]MAIN[15][70]MAIN[14][71]MAIN[15][71]MAIN[14][68]MAIN[15][68]MAIN[15][66]MAIN[14][66]IMUX_CE[0]
Source
00000000off
00010001TIE_1
00010010DBL_E1[8]
00010100DBL_E2[8]
00011000IMUX_BOUNCE[3]
00100001DBL_W0[8]
00100010DBL_N2[8]
00100100DBL_S2[8]
00101000DBL_S1[8]
01000001DBL_S0[8]
01000010DBL_W1[8]
01000100DBL_W2[8]
01001000DBL_N1[8]
10000001DBL_E0[7]
10000010IMUX_BOUNCE[2]
10000100IMUX_BOUNCE[1]
10001000IMUX_BOUNCE[0]
virtex4 INT switchbox INT muxes IMUX_CE[1]
BitsDestination
MAIN[14][76]MAIN[15][76]MAIN[15][74]MAIN[14][74]MAIN[15][79]MAIN[14][79]MAIN[14][78]MAIN[15][78]IMUX_CE[1]
Source
00000000off
00010001TIE_1
00010010DBL_E0[8]
00010100DBL_E0[9]
00011000DBL_N0[8]
00100001DBL_W1[9]
00100010IMUX_BOUNCE[2]
00100100DBL_N2[9]
00101000DBL_E1[9]
01000001DBL_W2[9]
01000010IMUX_BOUNCE[1]
01000100DBL_S2[9]
01001000DBL_E2[9]
10000001DBL_N1[9]
10000010IMUX_BOUNCE[0]
10000100DBL_S1[9]
10001000IMUX_BOUNCE[3]
virtex4 INT switchbox INT muxes IMUX_CE[2]
BitsDestination
MAIN[15][64]MAIN[14][65]MAIN[14][64]MAIN[15][65]MAIN[15][69]MAIN[15][67]MAIN[14][67]MAIN[14][69]IMUX_CE[2]
Source
00000000off
00010001TIE_1
00010010DBL_E1[8]
00010100DBL_E2[8]
00011000IMUX_BOUNCE[3]
00100001DBL_N0[8]
00100010DBL_W1[8]
00100100DBL_W2[8]
00101000DBL_N1[8]
01000001DBL_E0[7]
01000010IMUX_BOUNCE[2]
01000100IMUX_BOUNCE[1]
01001000IMUX_BOUNCE[0]
10000001DBL_E0[8]
10000010DBL_N2[8]
10000100DBL_S2[8]
10001000DBL_S1[8]
virtex4 INT switchbox INT muxes IMUX_CE[3]
BitsDestination
MAIN[15][73]MAIN[15][72]MAIN[14][73]MAIN[14][72]MAIN[15][77]MAIN[15][75]MAIN[14][75]MAIN[14][77]IMUX_CE[3]
Source
00000000off
00010001TIE_1
00010010DBL_W1[9]
00010100DBL_W2[9]
00011000DBL_N1[9]
00100001DBL_W0[8]
00100010IMUX_BOUNCE[2]
00100100IMUX_BOUNCE[1]
00101000IMUX_BOUNCE[0]
01000001DBL_E0[9]
01000010DBL_N2[9]
01000100DBL_S2[9]
01001000DBL_S1[9]
10000001DBL_S0[8]
10000010DBL_E1[9]
10000100DBL_E2[9]
10001000IMUX_BOUNCE[3]
virtex4 INT switchbox INT muxes IMUX_BYP[0]
BitsDestination
MAIN[12][16]MAIN[13][19]MAIN[12][19]MAIN[13][16]MAIN[10][16]MAIN[8][18]MAIN[9][17]MAIN[11][19]MAIN[14][16]MAIN[11][17]MAIN[8][16]MAIN[10][18]MAIN[9][19]IMUX_BYP[0]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[1]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_EN8
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000IMUX_BYP_BOUNCE[4]
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000OMUX_N10
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_BYP[1]
BitsDestination
MAIN[12][59]MAIN[12][56]MAIN[13][59]MAIN[13][56]MAIN[10][56]MAIN[8][58]MAIN[9][57]MAIN[11][57]MAIN[11][59]MAIN[9][59]MAIN[14][58]MAIN[10][58]MAIN[8][56]IMUX_BYP[1]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[0]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BYP_BOUNCE[5]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[5]
0100000000010OMUX_N11
0100000000100OMUX_S3
0100000001000DBL_S2[6]
0100000010000DBL_W1[5]
0100000100000DBL_W1[6]
0100001000000DBL_W2[6]
0100010000000DBL_E2[6]
0100100000000DBL_S1[7]
1000000000001DBL_N2[6]
1000000000010OMUX_W9
1000000000100IMUX_BOUNCE[2]
1000000001000OMUX_E8
1000000010000DBL_S1[5]
1000000100000OUT_BEST[1]
1000001000000DBL_E1[6]
1000010000000DBL_S2[5]
1000100000000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_BYP[2]
BitsDestination
MAIN[12][17]MAIN[13][18]MAIN[13][17]MAIN[12][18]MAIN[11][18]MAIN[8][17]MAIN[8][19]MAIN[11][16]MAIN[14][19]MAIN[10][19]MAIN[9][18]MAIN[10][17]MAIN[9][16]IMUX_BYP[2]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[4]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_N10
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000OMUX_EN8
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000IMUX_BYP_BOUNCE[1]
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_BYP[3]
BitsDestination
MAIN[12][57]MAIN[13][57]MAIN[13][58]MAIN[12][58]MAIN[11][58]MAIN[8][57]MAIN[8][59]MAIN[10][59]MAIN[11][56]MAIN[9][56]MAIN[14][60]MAIN[10][57]MAIN[9][58]IMUX_BYP[3]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[5]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BOUNCE[2]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[6]
0100000000010OMUX_W9
0100000000100OMUX_S3
0100000001000OMUX_E8
0100000010000DBL_S1[5]
0100000100000OUT_BEST[1]
0100001000000DBL_E1[6]
0100010000000DBL_S2[5]
0100100000000DBL_S0[6]
1000000000001DBL_N2[5]
1000000000010OMUX_N11
1000000000100IMUX_BYP_BOUNCE[0]
1000000001000DBL_S2[6]
1000000010000DBL_W1[5]
1000000100000DBL_W1[6]
1000001000000DBL_W2[6]
1000010000000DBL_E2[6]
1000100000000DBL_S1[7]
virtex4 INT switchbox INT muxes IMUX_BYP[4]
BitsDestination
MAIN[13][23]MAIN[12][20]MAIN[12][23]MAIN[13][20]MAIN[9][21]MAIN[8][20]MAIN[8][22]MAIN[11][21]MAIN[9][23]MAIN[15][20]MAIN[10][20]MAIN[10][22]MAIN[11][23]IMUX_BYP[4]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_E7
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[7]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000IMUX_BYP_BOUNCE[2]
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000OMUX_WN14
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_BYP[5]
BitsDestination
MAIN[13][63]MAIN[12][60]MAIN[13][60]MAIN[12][63]MAIN[9][61]MAIN[8][60]MAIN[11][61]MAIN[8][62]MAIN[9][63]MAIN[11][63]MAIN[10][62]MAIN[14][59]MAIN[10][60]IMUX_BYP[5]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010IMUX_BYP_BOUNCE[3]
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001DBL_S1[8]
0010000000010OMUX_S5
0010000000100DBL_N1[8]
0010000001000OMUX_W14
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_E2[8]
0010010000000DBL_N2[7]
0010100000000DBL_W2[9]
0100000000001OUT_BEST[0]
0100000000010OMUX_SW5
0100000000100OMUX_ES7
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_W1[8]
0100010000000DBL_N2[9]
0100100000000DBL_W2[8]
1000000000001DBL_N0[9]
1000000000010IMUX_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_BYP[6]
BitsDestination
MAIN[13][22]MAIN[12][21]MAIN[13][21]MAIN[12][22]MAIN[8][23]MAIN[9][22]MAIN[8][21]MAIN[10][23]MAIN[9][20]MAIN[14][20]MAIN[11][22]MAIN[10][21]MAIN[11][20]IMUX_BYP[6]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_WN14
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[2]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000OMUX_E7
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000IMUX_BYP_BOUNCE[7]
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_BYP[7]
BitsDestination
MAIN[13][62]MAIN[12][62]MAIN[12][61]MAIN[13][61]MAIN[8][63]MAIN[9][62]MAIN[10][63]MAIN[8][61]MAIN[9][60]MAIN[11][60]MAIN[10][61]MAIN[14][63]MAIN[11][62]IMUX_BYP[7]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_SW5
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001OUT_BEST[0]
0010000000010OMUX_S5
0010000000100OMUX_ES7
0010000001000DBL_S2[9]
0010000010000DBL_S2[8]
0010000100000DBL_S1[9]
0010001000000DBL_W1[8]
0010010000000DBL_N2[9]
0010100000000DBL_W2[8]
0100000000001DBL_S1[8]
0100000000010IMUX_BOUNCE[3]
0100000000100DBL_N1[8]
0100000001000OMUX_W14
0100000010000DBL_E0[9]
0100000100000DBL_W1[7]
0100001000000DBL_E2[8]
0100010000000DBL_N2[7]
0100100000000DBL_W2[9]
1000000000001DBL_N0[9]
1000000000010IMUX_BYP_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[0]
BitsDestination
MAIN[12][12]MAIN[13][15]MAIN[12][15]MAIN[13][12]MAIN[10][12]MAIN[8][14]MAIN[9][13]MAIN[11][15]MAIN[14][18]MAIN[11][13]MAIN[8][12]MAIN[10][14]MAIN[9][15]IMUX_IMUX[0]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[1]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_EN8
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000IMUX_BYP_BOUNCE[4]
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000OMUX_N10
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[1]
BitsDestination
MAIN[13][39]MAIN[12][36]MAIN[12][39]MAIN[13][36]MAIN[9][37]MAIN[8][36]MAIN[8][38]MAIN[11][37]MAIN[9][39]MAIN[15][21]MAIN[10][36]MAIN[10][38]MAIN[11][39]IMUX_IMUX[1]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_E7
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[7]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000IMUX_BYP_BOUNCE[2]
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000OMUX_WN14
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[2]
BitsDestination
MAIN[12][55]MAIN[12][52]MAIN[13][55]MAIN[13][52]MAIN[10][52]MAIN[8][54]MAIN[9][53]MAIN[11][53]MAIN[11][55]MAIN[9][55]MAIN[15][57]MAIN[10][54]MAIN[8][52]IMUX_IMUX[2]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[0]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BYP_BOUNCE[5]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[5]
0100000000010OMUX_N11
0100000000100OMUX_S3
0100000001000DBL_S2[6]
0100000010000DBL_W1[5]
0100000100000DBL_W1[6]
0100001000000DBL_W2[6]
0100010000000DBL_E2[6]
0100100000000DBL_S1[7]
1000000000001DBL_N2[6]
1000000000010OMUX_W9
1000000000100IMUX_BOUNCE[2]
1000000001000OMUX_E8
1000000010000DBL_S1[5]
1000000100000OUT_BEST[1]
1000001000000DBL_E1[6]
1000010000000DBL_S2[5]
1000100000000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_IMUX[3]
BitsDestination
MAIN[13][79]MAIN[12][76]MAIN[13][76]MAIN[12][79]MAIN[9][77]MAIN[8][76]MAIN[11][77]MAIN[8][78]MAIN[9][79]MAIN[11][79]MAIN[10][78]MAIN[18][76]MAIN[10][76]IMUX_IMUX[3]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010IMUX_BYP_BOUNCE[3]
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001DBL_S1[8]
0010000000010OMUX_S5
0010000000100DBL_N1[8]
0010000001000OMUX_W14
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_E2[8]
0010010000000DBL_N2[7]
0010100000000DBL_W2[9]
0100000000001OUT_BEST[0]
0100000000010OMUX_SW5
0100000000100OMUX_ES7
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_W1[8]
0100010000000DBL_N2[9]
0100100000000DBL_W2[8]
1000000000001DBL_N0[9]
1000000000010IMUX_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[4]
BitsDestination
MAIN[12][13]MAIN[13][14]MAIN[13][13]MAIN[12][14]MAIN[11][14]MAIN[8][13]MAIN[8][15]MAIN[11][12]MAIN[14][17]MAIN[10][15]MAIN[9][14]MAIN[10][13]MAIN[9][12]IMUX_IMUX[4]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[4]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_N10
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000OMUX_EN8
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000IMUX_BYP_BOUNCE[1]
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[5]
BitsDestination
MAIN[13][38]MAIN[12][37]MAIN[13][37]MAIN[12][38]MAIN[8][39]MAIN[9][38]MAIN[8][37]MAIN[10][39]MAIN[9][36]MAIN[15][19]MAIN[11][38]MAIN[10][37]MAIN[11][36]IMUX_IMUX[5]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_WN14
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[2]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000OMUX_E7
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000IMUX_BYP_BOUNCE[7]
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[6]
BitsDestination
MAIN[12][53]MAIN[13][53]MAIN[13][54]MAIN[12][54]MAIN[11][54]MAIN[8][53]MAIN[8][55]MAIN[10][55]MAIN[11][52]MAIN[9][52]MAIN[14][57]MAIN[10][53]MAIN[9][54]IMUX_IMUX[6]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[5]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BOUNCE[2]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[6]
0100000000010OMUX_W9
0100000000100OMUX_S3
0100000001000OMUX_E8
0100000010000DBL_S1[5]
0100000100000OUT_BEST[1]
0100001000000DBL_E1[6]
0100010000000DBL_S2[5]
0100100000000DBL_S0[6]
1000000000001DBL_N2[5]
1000000000010OMUX_N11
1000000000100IMUX_BYP_BOUNCE[0]
1000000001000DBL_S2[6]
1000000010000DBL_W1[5]
1000000100000DBL_W1[6]
1000001000000DBL_W2[6]
1000010000000DBL_E2[6]
1000100000000DBL_S1[7]
virtex4 INT switchbox INT muxes IMUX_IMUX[7]
BitsDestination
MAIN[13][78]MAIN[12][78]MAIN[12][77]MAIN[13][77]MAIN[8][79]MAIN[9][78]MAIN[10][79]MAIN[8][77]MAIN[9][76]MAIN[11][76]MAIN[10][77]MAIN[18][78]MAIN[11][78]IMUX_IMUX[7]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_SW5
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001OUT_BEST[0]
0010000000010OMUX_S5
0010000000100OMUX_ES7
0010000001000DBL_S2[9]
0010000010000DBL_S2[8]
0010000100000DBL_S1[9]
0010001000000DBL_W1[8]
0010010000000DBL_N2[9]
0010100000000DBL_W2[8]
0100000000001DBL_S1[8]
0100000000010IMUX_BOUNCE[3]
0100000000100DBL_N1[8]
0100000001000OMUX_W14
0100000010000DBL_E0[9]
0100000100000DBL_W1[7]
0100001000000DBL_E2[8]
0100010000000DBL_N2[7]
0100100000000DBL_W2[9]
1000000000001DBL_N0[9]
1000000000010IMUX_BYP_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[8]
BitsDestination
MAIN[12][8]MAIN[13][11]MAIN[12][11]MAIN[13][8]MAIN[10][8]MAIN[8][10]MAIN[9][9]MAIN[11][11]MAIN[15][16]MAIN[11][9]MAIN[8][8]MAIN[10][10]MAIN[9][11]IMUX_IMUX[8]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[1]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_EN8
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000IMUX_BYP_BOUNCE[4]
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000OMUX_N10
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[9]
BitsDestination
MAIN[13][35]MAIN[12][32]MAIN[12][35]MAIN[13][32]MAIN[9][33]MAIN[8][32]MAIN[8][34]MAIN[11][33]MAIN[9][35]MAIN[15][22]MAIN[10][32]MAIN[10][34]MAIN[11][35]IMUX_IMUX[9]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_E7
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[7]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000IMUX_BYP_BOUNCE[2]
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000OMUX_WN14
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[10]
BitsDestination
MAIN[12][51]MAIN[12][48]MAIN[13][51]MAIN[13][48]MAIN[10][48]MAIN[8][50]MAIN[9][49]MAIN[11][49]MAIN[11][51]MAIN[9][51]MAIN[15][56]MAIN[10][50]MAIN[8][48]IMUX_IMUX[10]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[0]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BYP_BOUNCE[5]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[5]
0100000000010OMUX_N11
0100000000100OMUX_S3
0100000001000DBL_S2[6]
0100000010000DBL_W1[5]
0100000100000DBL_W1[6]
0100001000000DBL_W2[6]
0100010000000DBL_E2[6]
0100100000000DBL_S1[7]
1000000000001DBL_N2[6]
1000000000010OMUX_W9
1000000000100IMUX_BOUNCE[2]
1000000001000OMUX_E8
1000000010000DBL_S1[5]
1000000100000OUT_BEST[1]
1000001000000DBL_E1[6]
1000010000000DBL_S2[5]
1000100000000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_IMUX[11]
BitsDestination
MAIN[13][75]MAIN[12][72]MAIN[13][72]MAIN[12][75]MAIN[9][73]MAIN[8][72]MAIN[11][73]MAIN[8][74]MAIN[9][75]MAIN[11][75]MAIN[10][74]MAIN[18][73]MAIN[10][72]IMUX_IMUX[11]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010IMUX_BYP_BOUNCE[3]
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001DBL_S1[8]
0010000000010OMUX_S5
0010000000100DBL_N1[8]
0010000001000OMUX_W14
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_E2[8]
0010010000000DBL_N2[7]
0010100000000DBL_W2[9]
0100000000001OUT_BEST[0]
0100000000010OMUX_SW5
0100000000100OMUX_ES7
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_W1[8]
0100010000000DBL_N2[9]
0100100000000DBL_W2[8]
1000000000001DBL_N0[9]
1000000000010IMUX_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[12]
BitsDestination
MAIN[12][9]MAIN[13][10]MAIN[13][9]MAIN[12][10]MAIN[11][10]MAIN[8][9]MAIN[8][11]MAIN[11][8]MAIN[15][17]MAIN[10][11]MAIN[9][10]MAIN[10][9]MAIN[9][8]IMUX_IMUX[12]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[4]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_N10
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000OMUX_EN8
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000IMUX_BYP_BOUNCE[1]
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[13]
BitsDestination
MAIN[13][34]MAIN[12][33]MAIN[13][33]MAIN[12][34]MAIN[8][35]MAIN[9][34]MAIN[8][33]MAIN[10][35]MAIN[9][32]MAIN[15][23]MAIN[11][34]MAIN[10][33]MAIN[11][32]IMUX_IMUX[13]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_WN14
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[2]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000OMUX_E7
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000IMUX_BYP_BOUNCE[7]
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[14]
BitsDestination
MAIN[12][49]MAIN[13][49]MAIN[13][50]MAIN[12][50]MAIN[11][50]MAIN[8][49]MAIN[8][51]MAIN[10][51]MAIN[11][48]MAIN[9][48]MAIN[15][59]MAIN[10][49]MAIN[9][50]IMUX_IMUX[14]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[5]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BOUNCE[2]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[6]
0100000000010OMUX_W9
0100000000100OMUX_S3
0100000001000OMUX_E8
0100000010000DBL_S1[5]
0100000100000OUT_BEST[1]
0100001000000DBL_E1[6]
0100010000000DBL_S2[5]
0100100000000DBL_S0[6]
1000000000001DBL_N2[5]
1000000000010OMUX_N11
1000000000100IMUX_BYP_BOUNCE[0]
1000000001000DBL_S2[6]
1000000010000DBL_W1[5]
1000000100000DBL_W1[6]
1000001000000DBL_W2[6]
1000010000000DBL_E2[6]
1000100000000DBL_S1[7]
virtex4 INT switchbox INT muxes IMUX_IMUX[15]
BitsDestination
MAIN[13][74]MAIN[12][74]MAIN[12][73]MAIN[13][73]MAIN[8][75]MAIN[9][74]MAIN[10][75]MAIN[8][73]MAIN[9][72]MAIN[11][72]MAIN[10][73]MAIN[18][75]MAIN[11][74]IMUX_IMUX[15]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_SW5
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001OUT_BEST[0]
0010000000010OMUX_S5
0010000000100OMUX_ES7
0010000001000DBL_S2[9]
0010000010000DBL_S2[8]
0010000100000DBL_S1[9]
0010001000000DBL_W1[8]
0010010000000DBL_N2[9]
0010100000000DBL_W2[8]
0100000000001DBL_S1[8]
0100000000010IMUX_BOUNCE[3]
0100000000100DBL_N1[8]
0100000001000OMUX_W14
0100000010000DBL_E0[9]
0100000100000DBL_W1[7]
0100001000000DBL_E2[8]
0100010000000DBL_N2[7]
0100100000000DBL_W2[9]
1000000000001DBL_N0[9]
1000000000010IMUX_BYP_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[16]
BitsDestination
MAIN[12][4]MAIN[13][7]MAIN[12][7]MAIN[13][4]MAIN[10][4]MAIN[8][6]MAIN[9][5]MAIN[11][7]MAIN[18][4]MAIN[11][5]MAIN[8][4]MAIN[10][6]MAIN[9][7]IMUX_IMUX[16]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[1]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_EN8
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000IMUX_BYP_BOUNCE[4]
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000OMUX_N10
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[17]
BitsDestination
MAIN[13][31]MAIN[12][28]MAIN[12][31]MAIN[13][28]MAIN[9][29]MAIN[8][28]MAIN[8][30]MAIN[11][29]MAIN[9][31]MAIN[14][22]MAIN[10][28]MAIN[10][30]MAIN[11][31]IMUX_IMUX[17]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_E7
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[7]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000IMUX_BYP_BOUNCE[2]
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000OMUX_WN14
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[18]
BitsDestination
MAIN[12][47]MAIN[12][44]MAIN[13][47]MAIN[13][44]MAIN[10][44]MAIN[8][46]MAIN[9][45]MAIN[11][45]MAIN[11][47]MAIN[9][47]MAIN[15][58]MAIN[10][46]MAIN[8][44]IMUX_IMUX[18]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[0]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BYP_BOUNCE[5]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[5]
0100000000010OMUX_N11
0100000000100OMUX_S3
0100000001000DBL_S2[6]
0100000010000DBL_W1[5]
0100000100000DBL_W1[6]
0100001000000DBL_W2[6]
0100010000000DBL_E2[6]
0100100000000DBL_S1[7]
1000000000001DBL_N2[6]
1000000000010OMUX_W9
1000000000100IMUX_BOUNCE[2]
1000000001000OMUX_E8
1000000010000DBL_S1[5]
1000000100000OUT_BEST[1]
1000001000000DBL_E1[6]
1000010000000DBL_S2[5]
1000100000000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_IMUX[19]
BitsDestination
MAIN[13][71]MAIN[12][68]MAIN[13][68]MAIN[12][71]MAIN[9][69]MAIN[8][68]MAIN[11][69]MAIN[8][70]MAIN[9][71]MAIN[11][71]MAIN[10][70]MAIN[15][62]MAIN[10][68]IMUX_IMUX[19]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010IMUX_BYP_BOUNCE[3]
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001DBL_S1[8]
0010000000010OMUX_S5
0010000000100DBL_N1[8]
0010000001000OMUX_W14
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_E2[8]
0010010000000DBL_N2[7]
0010100000000DBL_W2[9]
0100000000001OUT_BEST[0]
0100000000010OMUX_SW5
0100000000100OMUX_ES7
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_W1[8]
0100010000000DBL_N2[9]
0100100000000DBL_W2[8]
1000000000001DBL_N0[9]
1000000000010IMUX_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[20]
BitsDestination
MAIN[12][5]MAIN[13][6]MAIN[13][5]MAIN[12][6]MAIN[11][6]MAIN[8][5]MAIN[8][7]MAIN[11][4]MAIN[18][6]MAIN[10][7]MAIN[9][6]MAIN[10][5]MAIN[9][4]IMUX_IMUX[20]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[4]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_N10
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000OMUX_EN8
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000IMUX_BYP_BOUNCE[1]
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[21]
BitsDestination
MAIN[13][30]MAIN[12][29]MAIN[13][29]MAIN[12][30]MAIN[8][31]MAIN[9][30]MAIN[8][29]MAIN[10][31]MAIN[9][28]MAIN[15][18]MAIN[11][30]MAIN[10][29]MAIN[11][28]IMUX_IMUX[21]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_WN14
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[2]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000OMUX_E7
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000IMUX_BYP_BOUNCE[7]
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[22]
BitsDestination
MAIN[12][45]MAIN[13][45]MAIN[13][46]MAIN[12][46]MAIN[11][46]MAIN[8][45]MAIN[8][47]MAIN[10][47]MAIN[11][44]MAIN[9][44]MAIN[14][56]MAIN[10][45]MAIN[9][46]IMUX_IMUX[22]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[5]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BOUNCE[2]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[6]
0100000000010OMUX_W9
0100000000100OMUX_S3
0100000001000OMUX_E8
0100000010000DBL_S1[5]
0100000100000OUT_BEST[1]
0100001000000DBL_E1[6]
0100010000000DBL_S2[5]
0100100000000DBL_S0[6]
1000000000001DBL_N2[5]
1000000000010OMUX_N11
1000000000100IMUX_BYP_BOUNCE[0]
1000000001000DBL_S2[6]
1000000010000DBL_W1[5]
1000000100000DBL_W1[6]
1000001000000DBL_W2[6]
1000010000000DBL_E2[6]
1000100000000DBL_S1[7]
virtex4 INT switchbox INT muxes IMUX_IMUX[23]
BitsDestination
MAIN[13][70]MAIN[12][70]MAIN[12][69]MAIN[13][69]MAIN[8][71]MAIN[9][70]MAIN[10][71]MAIN[8][69]MAIN[9][68]MAIN[11][68]MAIN[10][69]MAIN[15][63]MAIN[11][70]IMUX_IMUX[23]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_SW5
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001OUT_BEST[0]
0010000000010OMUX_S5
0010000000100OMUX_ES7
0010000001000DBL_S2[9]
0010000010000DBL_S2[8]
0010000100000DBL_S1[9]
0010001000000DBL_W1[8]
0010010000000DBL_N2[9]
0010100000000DBL_W2[8]
0100000000001DBL_S1[8]
0100000000010IMUX_BOUNCE[3]
0100000000100DBL_N1[8]
0100000001000OMUX_W14
0100000010000DBL_E0[9]
0100000100000DBL_W1[7]
0100001000000DBL_E2[8]
0100010000000DBL_N2[7]
0100100000000DBL_W2[9]
1000000000001DBL_N0[9]
1000000000010IMUX_BYP_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[24]
BitsDestination
MAIN[12][0]MAIN[13][3]MAIN[12][3]MAIN[13][0]MAIN[10][0]MAIN[8][2]MAIN[9][1]MAIN[11][3]MAIN[18][1]MAIN[11][1]MAIN[8][0]MAIN[10][2]MAIN[9][3]IMUX_IMUX[24]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[1]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_EN8
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000IMUX_BYP_BOUNCE[4]
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000OMUX_N10
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[25]
BitsDestination
MAIN[13][27]MAIN[12][24]MAIN[12][27]MAIN[13][24]MAIN[9][25]MAIN[8][24]MAIN[8][26]MAIN[11][25]MAIN[9][27]MAIN[14][21]MAIN[10][24]MAIN[10][26]MAIN[11][27]IMUX_IMUX[25]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_E7
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[7]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000IMUX_BYP_BOUNCE[2]
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000OMUX_WN14
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[26]
BitsDestination
MAIN[12][43]MAIN[12][40]MAIN[13][43]MAIN[13][40]MAIN[10][40]MAIN[8][42]MAIN[9][41]MAIN[11][41]MAIN[11][43]MAIN[9][43]MAIN[15][61]MAIN[10][42]MAIN[8][40]IMUX_IMUX[26]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[0]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BYP_BOUNCE[5]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[5]
0100000000010OMUX_N11
0100000000100OMUX_S3
0100000001000DBL_S2[6]
0100000010000DBL_W1[5]
0100000100000DBL_W1[6]
0100001000000DBL_W2[6]
0100010000000DBL_E2[6]
0100100000000DBL_S1[7]
1000000000001DBL_N2[6]
1000000000010OMUX_W9
1000000000100IMUX_BOUNCE[2]
1000000001000OMUX_E8
1000000010000DBL_S1[5]
1000000100000OUT_BEST[1]
1000001000000DBL_E1[6]
1000010000000DBL_S2[5]
1000100000000DBL_S0[6]
virtex4 INT switchbox INT muxes IMUX_IMUX[27]
BitsDestination
MAIN[13][67]MAIN[12][64]MAIN[13][64]MAIN[12][67]MAIN[9][65]MAIN[8][64]MAIN[11][65]MAIN[8][66]MAIN[9][67]MAIN[11][67]MAIN[10][66]MAIN[14][61]MAIN[10][64]IMUX_IMUX[27]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010IMUX_BYP_BOUNCE[3]
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001DBL_S1[8]
0010000000010OMUX_S5
0010000000100DBL_N1[8]
0010000001000OMUX_W14
0010000010000DBL_E0[9]
0010000100000DBL_W1[7]
0010001000000DBL_E2[8]
0010010000000DBL_N2[7]
0010100000000DBL_W2[9]
0100000000001OUT_BEST[0]
0100000000010OMUX_SW5
0100000000100OMUX_ES7
0100000001000DBL_S2[9]
0100000010000DBL_S2[8]
0100000100000DBL_S1[9]
0100001000000DBL_W1[8]
0100010000000DBL_N2[9]
0100100000000DBL_W2[8]
1000000000001DBL_N0[9]
1000000000010IMUX_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]
virtex4 INT switchbox INT muxes IMUX_IMUX[28]
BitsDestination
MAIN[12][1]MAIN[13][2]MAIN[13][1]MAIN[12][2]MAIN[11][2]MAIN[8][1]MAIN[8][3]MAIN[11][0]MAIN[18][3]MAIN[10][3]MAIN[9][2]MAIN[10][1]MAIN[9][0]IMUX_IMUX[28]
Source
0000000000000PULLUP
0001000000001OMUX[2]
0001000000010DBL_N1[1]
0001000000100OMUX_W1
0001000001000DBL_S2[2]
0001000010000IMUX_BYP_BOUNCE[4]
0001000100000OUT_BEST[4]
0001001000000DBL_W2[0]
0001010000000DBL_E2[2]
0001100000000DBL_S1[1]
0010000000001DBL_E2[1]
0010000000010OMUX_S0
0010000000100DBL_N2[1]
0010000001000OUT_BEST[3]
0010000010000OMUX_N10
0010000100000DBL_S1[0]
0010001000000DBL_E1[1]
0010010000000DBL_S2[0]
0010100000000DBL_S0[2]
0100000000001DBL_N1[0]
0100000000010OMUX_NW10
0100000000100DBL_E1[2]
0100000001000OMUX_E2
0100000010000OMUX_EN8
0100000100000DBL_W0[0]
0100001000000DBL_E1[0]
0100010000000DBL_E2[0]
0100100000000DBL_N0[1]
1000000000001DBL_S2[1]
1000000000010IMUX_BOUNCE[0]
1000000000100DBL_N2[0]
1000000001000DBL_W1[1]
1000000010000IMUX_BYP_BOUNCE[1]
1000000100000DBL_W1[0]
1000001000000DBL_W2[1]
1000010000000DBL_S0[0]
1000100000000DBL_S1[2]
virtex4 INT switchbox INT muxes IMUX_IMUX[29]
BitsDestination
MAIN[13][26]MAIN[12][25]MAIN[13][25]MAIN[12][26]MAIN[8][27]MAIN[9][26]MAIN[8][25]MAIN[10][27]MAIN[9][24]MAIN[14][23]MAIN[11][26]MAIN[10][25]MAIN[11][24]IMUX_IMUX[29]
Source
0000000000000PULLUP
0001000000001OMUX[6]
0001000000010DBL_N1[3]
0001000000100DBL_S1[3]
0001000001000OMUX_WN14
0001000010000DBL_E0[3]
0001000100000DBL_E2[3]
0001001000000DBL_W1[2]
0001010000000DBL_N2[2]
0001100000000DBL_W2[4]
0010000000001DBL_N1[2]
0010000000010OMUX_S4
0010000000100OMUX_W6
0010000001000IMUX_BYP_BOUNCE[2]
0010000010000OMUX_NE12
0010000100000DBL_W0[2]
0010001000000DBL_W1[4]
0010010000000DBL_N2[3]
0010100000000DBL_E1[3]
0100000000001DBL_S2[4]
0100000000010OUT_BEST[2]
0100000000100OMUX_N12
0100000001000OMUX_E7
0100000010000DBL_S2[3]
0100000100000DBL_W1[3]
0100001000000DBL_S1[4]
0100010000000DBL_N2[4]
0100100000000DBL_W2[3]
1000000000001DBL_W0[4]
1000000000010IMUX_BOUNCE[1]
1000000000100DBL_N0[3]
1000000001000IMUX_BYP_BOUNCE[7]
1000000010000DBL_N1[4]
1000000100000OUT_BEST[5]
1000001000000DBL_E2[4]
1000010000000DBL_W2[2]
1000100000000DBL_E1[4]
virtex4 INT switchbox INT muxes IMUX_IMUX[30]
BitsDestination
MAIN[12][41]MAIN[13][41]MAIN[13][42]MAIN[12][42]MAIN[11][42]MAIN[8][41]MAIN[8][43]MAIN[10][43]MAIN[11][40]MAIN[9][40]MAIN[15][60]MAIN[10][41]MAIN[9][42]IMUX_IMUX[30]
Source
0000000000000PULLUP
0001000000001OMUX[9]
0001000000010OMUX_SE3
0001000000100IMUX_BYP_BOUNCE[5]
0001000001000DBL_E1[7]
0001000010000OUT_BEST[6]
0001000100000DBL_S2[7]
0001001000000DBL_W2[5]
0001010000000DBL_E2[7]
0001100000000DBL_S1[6]
0010000000001DBL_E0[7]
0010000000010OMUX_WS1
0010000000100IMUX_BOUNCE[2]
0010000001000DBL_N1[5]
0010000010000DBL_W0[6]
0010000100000DBL_N1[6]
0010001000000DBL_E1[5]
0010010000000DBL_E2[5]
0010100000000DBL_N0[5]
0100000000001DBL_N2[6]
0100000000010OMUX_W9
0100000000100OMUX_S3
0100000001000OMUX_E8
0100000010000DBL_S1[5]
0100000100000OUT_BEST[1]
0100001000000DBL_E1[6]
0100010000000DBL_S2[5]
0100100000000DBL_S0[6]
1000000000001DBL_N2[5]
1000000000010OMUX_N11
1000000000100IMUX_BYP_BOUNCE[0]
1000000001000DBL_S2[6]
1000000010000DBL_W1[5]
1000000100000DBL_W1[6]
1000001000000DBL_W2[6]
1000010000000DBL_E2[6]
1000100000000DBL_S1[7]
virtex4 INT switchbox INT muxes IMUX_IMUX[31]
BitsDestination
MAIN[13][66]MAIN[12][66]MAIN[12][65]MAIN[13][65]MAIN[8][67]MAIN[9][66]MAIN[10][67]MAIN[8][65]MAIN[9][64]MAIN[11][64]MAIN[10][65]MAIN[14][62]MAIN[11][66]IMUX_IMUX[31]
Source
0000000000000PULLUP
0001000000001OMUX[13]
0001000000010OMUX_SW5
0001000000100OMUX_E13
0001000001000DBL_N1[7]
0001000010000OMUX_N15
0001000100000DBL_W1[9]
0001001000000DBL_N0[7]
0001010000000DBL_N2[8]
0001100000000DBL_E1[8]
0010000000001OUT_BEST[0]
0010000000010OMUX_S5
0010000000100OMUX_ES7
0010000001000DBL_S2[9]
0010000010000DBL_S2[8]
0010000100000DBL_S1[9]
0010001000000DBL_W1[8]
0010010000000DBL_N2[9]
0010100000000DBL_W2[8]
0100000000001DBL_S1[8]
0100000000010IMUX_BOUNCE[3]
0100000000100DBL_N1[8]
0100000001000OMUX_W14
0100000010000DBL_E0[9]
0100000100000DBL_W1[7]
0100001000000DBL_E2[8]
0100010000000DBL_N2[7]
0100100000000DBL_W2[9]
1000000000001DBL_N0[9]
1000000000010IMUX_BYP_BOUNCE[3]
1000000000100IMUX_BYP_BOUNCE[6]
1000000001000DBL_W0[8]
1000000010000DBL_N1[9]
1000000100000DBL_E2[9]
1000001000000OUT_BEST[7]
1000010000000DBL_W2[7]
1000100000000DBL_E1[9]

Bitstream

virtex4 INT rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B79 INT: mux HEX_W0[9] bit 5 INT: mux HEX_W0[9] bit 4 INT: mux HEX_E0[9] bit 3 INT: mux HEX_E0[9] bit 1 INT: mux DBL_W0[9] bit 6 INT: mux DBL_E0[9] bit 3 INT: mux DBL_W0[9] bit 3 INT: mux DBL_W0[9] bit 0 INT: mux IMUX_IMUX[7] bit 8 INT: mux IMUX_IMUX[3] bit 4 INT: mux IMUX_IMUX[7] bit 6 INT: mux IMUX_IMUX[3] bit 3 INT: mux IMUX_IMUX[3] bit 9 INT: mux IMUX_IMUX[3] bit 12 INT: mux IMUX_CE[1] bit 2 INT: mux IMUX_CE[1] bit 3 INT: mux OMUX[15] bit 8 INT: mux OMUX[15] bit 9 -
B78 INT: mux LV[24] bit 2 INT: mux HEX_E0[9] bit 4 INT: mux HEX_W0[9] bit 3 INT: mux HEX_W0[9] bit 0 INT: mux DBL_E0[9] bit 0 INT: mux DBL_W0[9] bit 4 INT: mux DBL_E0[9] bit 7 INT: mux DBL_E0[9] bit 5 INT: mux IMUX_IMUX[3] bit 5 INT: mux IMUX_IMUX[7] bit 7 INT: mux IMUX_IMUX[3] bit 2 INT: mux IMUX_IMUX[7] bit 0 INT: mux IMUX_IMUX[7] bit 11 INT: mux IMUX_IMUX[7] bit 12 INT: mux IMUX_CE[1] bit 1 INT: mux IMUX_CE[1] bit 0 INT: mux OMUX[14] bit 2 INT: mux OMUX[15] bit 7 INT: mux IMUX_IMUX[7] bit 1
B77 INT: mux LH[24] bit 2 INT: mux HEX_E0[9] bit 5 INT: mux HEX_W0[9] bit 2 INT: mux HEX_W0[9] bit 1 INT: mux DBL_E0[9] bit 2 INT: mux DBL_W0[9] bit 5 INT: mux DBL_E0[9] bit 6 INT: mux DBL_E0[9] bit 4 INT: mux IMUX_IMUX[7] bit 5 INT: mux IMUX_IMUX[3] bit 8 INT: mux IMUX_IMUX[7] bit 2 INT: mux IMUX_IMUX[3] bit 6 INT: mux IMUX_IMUX[7] bit 10 INT: mux IMUX_IMUX[7] bit 9 INT: mux IMUX_CE[3] bit 0 INT: mux IMUX_CE[3] bit 3 INT: mux OMUX[15] bit 0 INT: mux OMUX[15] bit 6 -
B76 INT: mux HEX_W0[9] bit 6 INT: mux HEX_E0[9] bit 6 INT: mux HEX_E0[9] bit 2 INT: mux HEX_E0[9] bit 0 INT: mux DBL_W0[9] bit 7 INT: mux DBL_E0[9] bit 1 INT: mux DBL_W0[9] bit 2 INT: mux DBL_W0[9] bit 1 INT: mux IMUX_IMUX[3] bit 7 INT: mux IMUX_IMUX[7] bit 4 INT: mux IMUX_IMUX[3] bit 0 INT: mux IMUX_IMUX[7] bit 3 INT: mux IMUX_IMUX[3] bit 11 INT: mux IMUX_IMUX[3] bit 10 INT: mux IMUX_CE[1] bit 7 INT: mux IMUX_CE[1] bit 6 INT: mux OMUX[14] bit 1 INT: mux OMUX[14] bit 0 INT: mux IMUX_IMUX[3] bit 1
B75 INT: mux HEX_N0[9] bit 6 INT: mux HEX_N0[9] bit 4 INT: mux HEX_S0[9] bit 2 INT: mux HEX_S0[9] bit 0 INT: mux DBL_N0[9] bit 3 INT: mux DBL_S0[9] bit 6 INT: mux DBL_N0[9] bit 7 INT: mux DBL_N0[9] bit 5 INT: mux IMUX_IMUX[15] bit 8 INT: mux IMUX_IMUX[11] bit 4 INT: mux IMUX_IMUX[15] bit 6 INT: mux IMUX_IMUX[11] bit 3 INT: mux IMUX_IMUX[11] bit 9 INT: mux IMUX_IMUX[11] bit 12 INT: mux IMUX_CE[3] bit 1 INT: mux IMUX_CE[3] bit 2 INT: mux OMUX[15] bit 2 INT: mux OMUX[15] bit 1 INT: mux IMUX_IMUX[15] bit 1
B74 INT: mux LH[24] bit 5 INT: mux HEX_S0[9] bit 6 INT: mux HEX_N0[9] bit 2 INT: mux HEX_N0[9] bit 1 INT: mux DBL_S0[9] bit 4 INT: mux DBL_N0[9] bit 0 INT: mux DBL_S0[9] bit 3 INT: mux DBL_S0[9] bit 0 INT: mux IMUX_IMUX[11] bit 5 INT: mux IMUX_IMUX[15] bit 7 INT: mux IMUX_IMUX[11] bit 2 INT: mux IMUX_IMUX[15] bit 0 INT: mux IMUX_IMUX[15] bit 11 INT: mux IMUX_IMUX[15] bit 12 INT: mux IMUX_CE[1] bit 4 INT: mux IMUX_CE[1] bit 5 INT: mux OMUX[15] bit 4 INT: mux OMUX[15] bit 3 -
B73 INT: mux LV[24] bit 5 INT: mux HEX_S0[9] bit 4 INT: mux HEX_N0[9] bit 3 INT: mux HEX_N0[9] bit 0 INT: mux DBL_S0[9] bit 7 INT: mux DBL_N0[9] bit 1 INT: mux DBL_S0[9] bit 2 INT: mux DBL_S0[9] bit 1 INT: mux IMUX_IMUX[15] bit 5 INT: mux IMUX_IMUX[11] bit 8 INT: mux IMUX_IMUX[15] bit 2 INT: mux IMUX_IMUX[11] bit 6 INT: mux IMUX_IMUX[15] bit 10 INT: mux IMUX_IMUX[15] bit 9 INT: mux IMUX_CE[3] bit 5 INT: mux IMUX_CE[3] bit 7 INT: mux OMUX[14] bit 4 INT: mux OMUX[14] bit 5 INT: mux IMUX_IMUX[11] bit 1
B72 INT: mux HEX_N0[9] bit 5 INT: mux HEX_S0[9] bit 5 INT: mux HEX_S0[9] bit 3 INT: mux HEX_S0[9] bit 1 INT: mux DBL_N0[9] bit 2 INT: mux DBL_S0[9] bit 5 INT: mux DBL_N0[9] bit 6 INT: mux DBL_N0[9] bit 4 INT: mux IMUX_IMUX[11] bit 7 INT: mux IMUX_IMUX[15] bit 4 INT: mux IMUX_IMUX[11] bit 0 INT: mux IMUX_IMUX[15] bit 3 INT: mux IMUX_IMUX[11] bit 11 INT: mux IMUX_IMUX[11] bit 10 INT: mux IMUX_CE[3] bit 4 INT: mux IMUX_CE[3] bit 6 INT: mux OMUX[15] bit 5 INT: mux OMUX[14] bit 6 -
B71 INT: mux HEX_E0[8] bit 5 INT: mux HEX_E0[8] bit 4 INT: mux HEX_W0[8] bit 3 INT: mux HEX_W0[8] bit 0 INT: mux DBL_W0[8] bit 1 INT: mux DBL_E0[8] bit 3 INT: mux DBL_W0[8] bit 7 INT: mux DBL_W0[8] bit 4 INT: mux IMUX_IMUX[23] bit 8 INT: mux IMUX_IMUX[19] bit 4 INT: mux IMUX_IMUX[23] bit 6 INT: mux IMUX_IMUX[19] bit 3 INT: mux IMUX_IMUX[19] bit 9 INT: mux IMUX_IMUX[19] bit 12 INT: mux IMUX_CE[0] bit 5 INT: mux IMUX_CE[0] bit 4 INT: mux OMUX[14] bit 3 INT: mux OMUX[14] bit 7 -
B70 INT: mux LV[24] bit 4 INT: mux HEX_W0[8] bit 5 INT: mux HEX_E0[8] bit 3 INT: mux HEX_E0[8] bit 0 INT: mux DBL_E0[8] bit 2 INT: mux DBL_W0[8] bit 0 INT: mux DBL_E0[8] bit 7 INT: mux DBL_E0[8] bit 4 INT: mux IMUX_IMUX[19] bit 5 INT: mux IMUX_IMUX[23] bit 7 INT: mux IMUX_IMUX[19] bit 2 INT: mux IMUX_IMUX[23] bit 0 INT: mux IMUX_IMUX[23] bit 11 INT: mux IMUX_IMUX[23] bit 12 INT: mux IMUX_CE[0] bit 7 INT: mux IMUX_CE[0] bit 6 INT: mux OMUX[14] bit 8 INT: mux OMUX[14] bit 9 -
B69 INT: mux LH[24] bit 4 INT: mux HEX_W0[8] bit 6 INT: mux HEX_E0[8] bit 2 INT: mux HEX_E0[8] bit 1 INT: mux DBL_E0[8] bit 1 INT: mux DBL_W0[8] bit 2 INT: mux DBL_E0[8] bit 6 INT: mux DBL_E0[8] bit 5 INT: mux IMUX_IMUX[23] bit 5 INT: mux IMUX_IMUX[19] bit 8 INT: mux IMUX_IMUX[23] bit 2 INT: mux IMUX_IMUX[19] bit 6 INT: mux IMUX_IMUX[23] bit 10 INT: mux IMUX_IMUX[23] bit 9 INT: mux IMUX_CE[2] bit 0 INT: mux IMUX_CE[2] bit 3 INT: mux OMUX[13] bit 8 INT: mux OMUX[13] bit 9 -
B68 INT: mux HEX_E0[8] bit 6 INT: mux HEX_W0[8] bit 4 INT: mux HEX_W0[8] bit 2 INT: mux HEX_W0[8] bit 1 INT: mux DBL_W0[8] bit 3 INT: mux DBL_E0[8] bit 0 INT: mux DBL_W0[8] bit 6 INT: mux DBL_W0[8] bit 5 INT: mux IMUX_IMUX[19] bit 7 INT: mux IMUX_IMUX[23] bit 4 INT: mux IMUX_IMUX[19] bit 0 INT: mux IMUX_IMUX[23] bit 3 INT: mux IMUX_IMUX[19] bit 11 INT: mux IMUX_IMUX[19] bit 10 INT: mux IMUX_CE[0] bit 3 INT: mux IMUX_CE[0] bit 2 INT: mux OMUX[12] bit 2 INT: mux OMUX[13] bit 7 -
B67 INT: mux HEX_S0[8] bit 6 INT: mux HEX_S0[8] bit 4 INT: mux HEX_N0[8] bit 2 INT: mux HEX_N0[8] bit 1 INT: mux DBL_N0[8] bit 2 INT: mux DBL_S0[8] bit 1 INT: mux DBL_N0[8] bit 7 INT: mux DBL_N0[8] bit 5 INT: mux IMUX_IMUX[31] bit 8 INT: mux IMUX_IMUX[27] bit 4 INT: mux IMUX_IMUX[31] bit 6 INT: mux IMUX_IMUX[27] bit 3 INT: mux IMUX_IMUX[27] bit 9 INT: mux IMUX_IMUX[27] bit 12 INT: mux IMUX_CE[2] bit 1 INT: mux IMUX_CE[2] bit 2 INT: mux OMUX[13] bit 0 INT: mux OMUX[13] bit 6 -
B66 INT: mux LH[24] bit 6 INT: mux HEX_N0[8] bit 6 INT: mux HEX_S0[8] bit 2 INT: mux HEX_S0[8] bit 1 INT: mux DBL_S0[8] bit 3 INT: mux DBL_N0[8] bit 0 INT: mux DBL_S0[8] bit 7 INT: mux DBL_S0[8] bit 5 INT: mux IMUX_IMUX[27] bit 5 INT: mux IMUX_IMUX[31] bit 7 INT: mux IMUX_IMUX[27] bit 2 INT: mux IMUX_IMUX[31] bit 0 INT: mux IMUX_IMUX[31] bit 11 INT: mux IMUX_IMUX[31] bit 12 INT: mux IMUX_CE[0] bit 0 INT: mux IMUX_CE[0] bit 1 INT: mux OMUX[12] bit 1 INT: mux OMUX[12] bit 0 -
B65 INT: mux LV[24] bit 6 INT: mux HEX_N0[8] bit 5 INT: mux HEX_S0[8] bit 3 INT: mux HEX_S0[8] bit 0 INT: mux DBL_S0[8] bit 2 INT: mux DBL_N0[8] bit 3 INT: mux DBL_S0[8] bit 6 INT: mux DBL_S0[8] bit 4 INT: mux IMUX_IMUX[31] bit 5 INT: mux IMUX_IMUX[27] bit 8 INT: mux IMUX_IMUX[31] bit 2 INT: mux IMUX_IMUX[27] bit 6 INT: mux IMUX_IMUX[31] bit 10 INT: mux IMUX_IMUX[31] bit 9 INT: mux IMUX_CE[2] bit 6 INT: mux IMUX_CE[2] bit 4 INT: mux OMUX[13] bit 2 INT: mux OMUX[13] bit 1 -
B64 INT: mux HEX_S0[8] bit 5 INT: mux HEX_N0[8] bit 4 INT: mux HEX_N0[8] bit 3 INT: mux HEX_N0[8] bit 0 INT: mux DBL_N0[8] bit 1 INT: mux DBL_S0[8] bit 0 INT: mux DBL_N0[8] bit 6 INT: mux DBL_N0[8] bit 4 INT: mux IMUX_IMUX[27] bit 7 INT: mux IMUX_IMUX[31] bit 4 INT: mux IMUX_IMUX[27] bit 0 INT: mux IMUX_IMUX[31] bit 3 INT: mux IMUX_IMUX[27] bit 11 INT: mux IMUX_IMUX[27] bit 10 INT: mux IMUX_CE[2] bit 5 INT: mux IMUX_CE[2] bit 7 INT: mux OMUX[13] bit 4 INT: mux OMUX[13] bit 3 -
B63 INT: mux HEX_W0[7] bit 5 INT: mux HEX_W0[7] bit 4 INT: mux HEX_E0[7] bit 3 INT: mux HEX_E0[7] bit 0 INT: mux DBL_W0[7] bit 1 INT: mux DBL_E0[7] bit 3 INT: mux DBL_W0[7] bit 7 INT: mux DBL_W0[7] bit 4 INT: mux IMUX_BYP[7] bit 8 INT: mux IMUX_BYP[5] bit 4 INT: mux IMUX_BYP[7] bit 6 INT: mux IMUX_BYP[5] bit 3 INT: mux IMUX_BYP[5] bit 9 INT: mux IMUX_BYP[5] bit 12 INT: mux IMUX_BYP[7] bit 1 INT: mux IMUX_IMUX[23] bit 1 INT: mux OMUX[12] bit 4 INT: mux OMUX[12] bit 5 -
B62 INT: mux LV[24] bit 10 INT: mux HEX_E0[7] bit 5 INT: mux HEX_W0[7] bit 3 INT: mux HEX_W0[7] bit 0 INT: mux DBL_E0[7] bit 2 INT: mux DBL_W0[7] bit 0 INT: mux DBL_E0[7] bit 7 INT: mux DBL_E0[7] bit 4 INT: mux IMUX_BYP[5] bit 5 INT: mux IMUX_BYP[7] bit 7 INT: mux IMUX_BYP[5] bit 2 INT: mux IMUX_BYP[7] bit 0 INT: mux IMUX_BYP[7] bit 11 INT: mux IMUX_BYP[7] bit 12 INT: mux IMUX_IMUX[31] bit 1 INT: mux IMUX_IMUX[19] bit 1 INT: mux OMUX[13] bit 5 INT: mux OMUX[12] bit 6 -
B61 INT: mux LV[24] bit 8 INT: mux HEX_E0[7] bit 6 INT: mux HEX_W0[7] bit 2 INT: mux HEX_W0[7] bit 1 INT: mux DBL_E0[7] bit 1 INT: mux DBL_W0[7] bit 2 INT: mux DBL_E0[7] bit 6 INT: mux DBL_E0[7] bit 5 INT: mux IMUX_BYP[7] bit 5 INT: mux IMUX_BYP[5] bit 8 INT: mux IMUX_BYP[7] bit 2 INT: mux IMUX_BYP[5] bit 6 INT: mux IMUX_BYP[7] bit 10 INT: mux IMUX_BYP[7] bit 9 INT: mux IMUX_IMUX[27] bit 1 INT: mux IMUX_IMUX[26] bit 2 INT: mux OMUX[12] bit 3 INT: mux OMUX[12] bit 7 -
B60 INT: mux HEX_W0[7] bit 6 INT: mux HEX_E0[7] bit 4 INT: mux HEX_E0[7] bit 2 INT: mux HEX_E0[7] bit 1 INT: mux DBL_W0[7] bit 3 INT: mux DBL_E0[7] bit 0 INT: mux DBL_W0[7] bit 6 INT: mux DBL_W0[7] bit 5 INT: mux IMUX_BYP[5] bit 7 INT: mux IMUX_BYP[7] bit 4 INT: mux IMUX_BYP[5] bit 0 INT: mux IMUX_BYP[7] bit 3 INT: mux IMUX_BYP[5] bit 11 INT: mux IMUX_BYP[5] bit 10 INT: mux IMUX_BYP[3] bit 2 INT: mux IMUX_IMUX[30] bit 2 INT: mux OMUX[12] bit 8 INT: mux OMUX[12] bit 9 -
B59 INT: mux HEX_N0[7] bit 4 INT: mux HEX_N0[7] bit 5 INT: mux HEX_S0[7] bit 2 INT: mux HEX_S0[7] bit 1 INT: mux DBL_N0[7] bit 7 INT: mux DBL_S0[7] bit 6 INT: mux DBL_N0[7] bit 3 INT: mux DBL_N0[7] bit 1 INT: mux IMUX_BYP[3] bit 6 INT: mux IMUX_BYP[1] bit 3 INT: mux IMUX_BYP[3] bit 5 INT: mux IMUX_BYP[1] bit 4 INT: mux IMUX_BYP[1] bit 12 INT: mux IMUX_BYP[1] bit 10 INT: mux IMUX_BYP[5] bit 1 INT: mux IMUX_IMUX[14] bit 2 INT: mux OMUX[11] bit 8 INT: mux OMUX[11] bit 9 INT: mux LV[24] bit 0
B58 INT: mux LH[24] bit 8 INT: mux HEX_S0[7] bit 4 INT: mux HEX_N0[7] bit 2 INT: mux HEX_N0[7] bit 1 INT: mux DBL_S0[7] bit 4 INT: mux DBL_N0[7] bit 5 INT: mux DBL_S0[7] bit 3 INT: mux DBL_S0[7] bit 1 INT: mux IMUX_BYP[1] bit 7 INT: mux IMUX_BYP[3] bit 0 INT: mux IMUX_BYP[1] bit 1 INT: mux IMUX_BYP[3] bit 8 INT: mux IMUX_BYP[3] bit 9 INT: mux IMUX_BYP[3] bit 10 INT: mux IMUX_BYP[1] bit 2 INT: mux IMUX_IMUX[18] bit 2 INT: mux OMUX[10] bit 2 INT: mux OMUX[11] bit 7 -
B57 INT: mux LH[24] bit 10 INT: mux HEX_S0[7] bit 6 INT: mux HEX_N0[7] bit 3 INT: mux HEX_N0[7] bit 0 INT: mux DBL_S0[7] bit 7 INT: mux DBL_N0[7] bit 4 INT: mux DBL_S0[7] bit 2 INT: mux DBL_S0[7] bit 0 INT: mux IMUX_BYP[3] bit 7 INT: mux IMUX_BYP[1] bit 6 INT: mux IMUX_BYP[3] bit 1 INT: mux IMUX_BYP[1] bit 5 INT: mux IMUX_BYP[3] bit 12 INT: mux IMUX_BYP[3] bit 11 INT: mux IMUX_IMUX[6] bit 2 INT: mux IMUX_IMUX[2] bit 2 INT: mux OMUX[11] bit 0 INT: mux OMUX[11] bit 6 -
B56 INT: mux HEX_N0[7] bit 6 INT: mux HEX_S0[7] bit 5 INT: mux HEX_S0[7] bit 3 INT: mux HEX_S0[7] bit 0 INT: mux DBL_N0[7] bit 6 INT: mux DBL_S0[7] bit 5 INT: mux DBL_N0[7] bit 2 INT: mux DBL_N0[7] bit 0 INT: mux IMUX_BYP[1] bit 0 INT: mux IMUX_BYP[3] bit 3 INT: mux IMUX_BYP[1] bit 8 INT: mux IMUX_BYP[3] bit 4 INT: mux IMUX_BYP[1] bit 11 INT: mux IMUX_BYP[1] bit 9 INT: mux IMUX_IMUX[22] bit 2 INT: mux IMUX_IMUX[10] bit 2 INT: mux OMUX[10] bit 1 INT: mux OMUX[10] bit 0 INT: !invert IMUX_CE_OPTINV[1] ← IMUX_CE[1]
B55 INT: mux HEX_E0[6] bit 6 INT: mux HEX_E0[6] bit 4 INT: mux HEX_W0[6] bit 3 INT: mux HEX_W0[6] bit 0 INT: mux DBL_W0[6] bit 6 INT: mux DBL_E0[6] bit 3 INT: mux DBL_W0[6] bit 3 INT: mux DBL_W0[6] bit 0 INT: mux IMUX_IMUX[6] bit 6 INT: mux IMUX_IMUX[2] bit 3 INT: mux IMUX_IMUX[6] bit 5 INT: mux IMUX_IMUX[2] bit 4 INT: mux IMUX_IMUX[2] bit 12 INT: mux IMUX_IMUX[2] bit 10 INT: mux IMUX_CLK[2] bit 2 INT: mux IMUX_CLK[2] bit 1 INT: mux OMUX[11] bit 2 INT: mux OMUX[11] bit 1 INT: !invert IMUX_CLK_OPTINV[2] ← IMUX_CLK[2]
B54 INT: mux LH[24] bit 3 INT: mux HEX_W0[6] bit 6 INT: mux HEX_E0[6] bit 3 INT: mux HEX_E0[6] bit 1 INT: mux DBL_E0[6] bit 1 INT: mux DBL_W0[6] bit 5 INT: mux DBL_E0[6] bit 7 INT: mux DBL_E0[6] bit 5 INT: mux IMUX_IMUX[2] bit 7 INT: mux IMUX_IMUX[6] bit 0 INT: mux IMUX_IMUX[2] bit 1 INT: mux IMUX_IMUX[6] bit 8 INT: mux IMUX_IMUX[6] bit 9 INT: mux IMUX_IMUX[6] bit 10 INT: mux IMUX_CLK[2] bit 0 INT: mux IMUX_CLK[2] bit 3 INT: mux OMUX[11] bit 4 INT: mux OMUX[11] bit 3 INT: !invert IMUX_CE_OPTINV[3] ← IMUX_CE[3]
B53 INT: mux LV[24] bit 3 INT: mux HEX_W0[6] bit 4 INT: mux HEX_E0[6] bit 2 INT: mux HEX_E0[6] bit 0 INT: mux DBL_E0[6] bit 2 INT: mux DBL_W0[6] bit 4 INT: mux DBL_E0[6] bit 6 INT: mux DBL_E0[6] bit 4 INT: mux IMUX_IMUX[6] bit 7 INT: mux IMUX_IMUX[2] bit 6 INT: mux IMUX_IMUX[6] bit 1 INT: mux IMUX_IMUX[2] bit 5 INT: mux IMUX_IMUX[6] bit 12 INT: mux IMUX_IMUX[6] bit 11 INT: mux IMUX_CLK[3] bit 7 INT: mux IMUX_CLK[3] bit 4 INT: mux OMUX[10] bit 4 INT: mux OMUX[10] bit 5 INT: !invert IMUX_CE_OPTINV[0] ← IMUX_CE[0]
B52 INT: mux HEX_E0[6] bit 5 INT: mux HEX_W0[6] bit 5 INT: mux HEX_W0[6] bit 2 INT: mux HEX_W0[6] bit 1 INT: mux DBL_W0[6] bit 7 INT: mux DBL_E0[6] bit 0 INT: mux DBL_W0[6] bit 2 INT: mux DBL_W0[6] bit 1 INT: mux IMUX_IMUX[2] bit 0 INT: mux IMUX_IMUX[6] bit 3 INT: mux IMUX_IMUX[2] bit 8 INT: mux IMUX_IMUX[6] bit 4 INT: mux IMUX_IMUX[2] bit 11 INT: mux IMUX_IMUX[2] bit 9 INT: mux IMUX_CLK[2] bit 4 INT: mux IMUX_CLK[2] bit 5 INT: mux OMUX[11] bit 5 INT: mux OMUX[10] bit 6 INT: !invert IMUX_CE_OPTINV[2] ← IMUX_CE[2]
B51 INT: mux HEX_S0[6] bit 6 INT: mux HEX_S0[6] bit 4 INT: mux HEX_N0[6] bit 2 INT: mux HEX_N0[6] bit 0 INT: mux DBL_N0[6] bit 2 INT: mux DBL_S0[6] bit 1 INT: mux DBL_N0[6] bit 7 INT: mux DBL_N0[6] bit 4 INT: mux IMUX_IMUX[14] bit 6 INT: mux IMUX_IMUX[10] bit 3 INT: mux IMUX_IMUX[14] bit 5 INT: mux IMUX_IMUX[10] bit 4 INT: mux IMUX_IMUX[10] bit 12 INT: mux IMUX_IMUX[10] bit 10 INT: mux IMUX_CLK[3] bit 6 INT: mux IMUX_CLK[3] bit 5 INT: mux OMUX[10] bit 3 INT: mux OMUX[10] bit 7 INT: mux LH[24] bit 0
B50 INT: mux LV[24] bit 7 INT: mux HEX_N0[6] bit 6 INT: mux HEX_S0[6] bit 2 INT: mux HEX_S0[6] bit 0 INT: mux DBL_S0[6] bit 3 INT: mux DBL_N0[6] bit 0 INT: mux DBL_S0[6] bit 7 INT: mux DBL_S0[6] bit 4 INT: mux IMUX_IMUX[10] bit 7 INT: mux IMUX_IMUX[14] bit 0 INT: mux IMUX_IMUX[10] bit 1 INT: mux IMUX_IMUX[14] bit 8 INT: mux IMUX_IMUX[14] bit 9 INT: mux IMUX_IMUX[14] bit 10 INT: mux IMUX_CLK[2] bit 7 INT: mux IMUX_CLK[2] bit 6 INT: mux OMUX[10] bit 8 INT: mux OMUX[10] bit 9 INT: !invert IMUX_CLK_OPTINV[3] ← IMUX_CLK[3]
B49 INT: mux LH[24] bit 7 INT: mux HEX_N0[6] bit 5 INT: mux HEX_S0[6] bit 3 INT: mux HEX_S0[6] bit 1 INT: mux DBL_S0[6] bit 2 INT: mux DBL_N0[6] bit 3 INT: mux DBL_S0[6] bit 6 INT: mux DBL_S0[6] bit 5 INT: mux IMUX_IMUX[14] bit 7 INT: mux IMUX_IMUX[10] bit 6 INT: mux IMUX_IMUX[14] bit 1 INT: mux IMUX_IMUX[10] bit 5 INT: mux IMUX_IMUX[14] bit 12 INT: mux IMUX_IMUX[14] bit 11 INT: mux IMUX_CLK[3] bit 0 INT: mux IMUX_CLK[3] bit 1 INT: mux OMUX[9] bit 8 INT: mux OMUX[9] bit 9 -
B48 INT: mux HEX_S0[6] bit 5 INT: mux HEX_N0[6] bit 4 INT: mux HEX_N0[6] bit 3 INT: mux HEX_N0[6] bit 1 INT: mux DBL_N0[6] bit 1 INT: mux DBL_S0[6] bit 0 INT: mux DBL_N0[6] bit 6 INT: mux DBL_N0[6] bit 5 INT: mux IMUX_IMUX[10] bit 0 INT: mux IMUX_IMUX[14] bit 3 INT: mux IMUX_IMUX[10] bit 8 INT: mux IMUX_IMUX[14] bit 4 INT: mux IMUX_IMUX[10] bit 11 INT: mux IMUX_IMUX[10] bit 9 INT: mux IMUX_CLK[3] bit 3 INT: mux IMUX_CLK[3] bit 2 INT: mux OMUX[8] bit 2 INT: mux OMUX[9] bit 7 -
B47 INT: mux HEX_W0[5] bit 5 INT: mux HEX_W0[5] bit 4 INT: mux HEX_E0[5] bit 3 INT: mux HEX_E0[5] bit 0 INT: mux DBL_W0[5] bit 1 INT: mux DBL_E0[5] bit 3 INT: mux DBL_W0[5] bit 7 INT: mux DBL_W0[5] bit 5 INT: mux IMUX_IMUX[22] bit 6 INT: mux IMUX_IMUX[18] bit 3 INT: mux IMUX_IMUX[22] bit 5 INT: mux IMUX_IMUX[18] bit 4 INT: mux IMUX_IMUX[18] bit 12 INT: mux IMUX_IMUX[18] bit 10 INT: mux IMUX_CLK[0] bit 2 INT: mux IMUX_CLK[0] bit 1 INT: mux OMUX[9] bit 0 INT: mux OMUX[9] bit 6 -
B46 INT: mux LH[24] bit 1 INT: mux HEX_E0[5] bit 5 INT: mux HEX_W0[5] bit 3 INT: mux HEX_W0[5] bit 1 INT: mux DBL_E0[5] bit 2 INT: mux DBL_W0[5] bit 0 INT: mux DBL_E0[5] bit 7 INT: mux DBL_E0[5] bit 4 INT: mux IMUX_IMUX[18] bit 7 INT: mux IMUX_IMUX[22] bit 0 INT: mux IMUX_IMUX[18] bit 1 INT: mux IMUX_IMUX[22] bit 8 INT: mux IMUX_IMUX[22] bit 9 INT: mux IMUX_IMUX[22] bit 10 INT: mux IMUX_CLK[0] bit 0 INT: mux IMUX_CLK[0] bit 3 INT: mux OMUX[8] bit 1 INT: mux OMUX[8] bit 0 -
B45 INT: mux LV[24] bit 1 INT: mux HEX_E0[5] bit 6 INT: mux HEX_W0[5] bit 2 INT: mux HEX_W0[5] bit 0 INT: mux DBL_E0[5] bit 1 INT: mux DBL_W0[5] bit 2 INT: mux DBL_E0[5] bit 6 INT: mux DBL_E0[5] bit 5 INT: mux IMUX_IMUX[22] bit 7 INT: mux IMUX_IMUX[18] bit 6 INT: mux IMUX_IMUX[22] bit 1 INT: mux IMUX_IMUX[18] bit 5 INT: mux IMUX_IMUX[22] bit 12 INT: mux IMUX_IMUX[22] bit 11 INT: mux IMUX_CLK[1] bit 7 INT: mux IMUX_CLK[1] bit 4 INT: mux OMUX[9] bit 2 INT: mux OMUX[9] bit 1 -
B44 INT: mux HEX_W0[5] bit 6 INT: mux HEX_E0[5] bit 4 INT: mux HEX_E0[5] bit 2 INT: mux HEX_E0[5] bit 1 INT: mux DBL_W0[5] bit 3 INT: mux DBL_E0[5] bit 0 INT: mux DBL_W0[5] bit 6 INT: mux DBL_W0[5] bit 4 INT: mux IMUX_IMUX[18] bit 0 INT: mux IMUX_IMUX[22] bit 3 INT: mux IMUX_IMUX[18] bit 8 INT: mux IMUX_IMUX[22] bit 4 INT: mux IMUX_IMUX[18] bit 11 INT: mux IMUX_IMUX[18] bit 9 INT: mux IMUX_CLK[0] bit 4 INT: mux IMUX_CLK[0] bit 5 INT: mux OMUX[9] bit 4 INT: mux OMUX[9] bit 3 -
B43 INT: mux HEX_N0[5] bit 6 INT: mux HEX_N0[5] bit 4 INT: mux HEX_S0[5] bit 2 INT: mux HEX_S0[5] bit 0 INT: mux DBL_N0[5] bit 2 INT: mux DBL_S0[5] bit 1 INT: mux DBL_N0[5] bit 7 INT: mux DBL_N0[5] bit 5 INT: mux IMUX_IMUX[30] bit 6 INT: mux IMUX_IMUX[26] bit 3 INT: mux IMUX_IMUX[30] bit 5 INT: mux IMUX_IMUX[26] bit 4 INT: mux IMUX_IMUX[26] bit 12 INT: mux IMUX_IMUX[26] bit 10 INT: mux IMUX_CLK[1] bit 6 INT: mux IMUX_CLK[1] bit 5 INT: mux OMUX[8] bit 4 INT: mux OMUX[8] bit 5 -
B42 INT: mux LV[24] bit 9 INT: mux HEX_S0[5] bit 6 INT: mux HEX_N0[5] bit 2 INT: mux HEX_N0[5] bit 1 INT: mux DBL_S0[5] bit 3 INT: mux DBL_N0[5] bit 0 INT: mux DBL_S0[5] bit 7 INT: mux DBL_S0[5] bit 4 INT: mux IMUX_IMUX[26] bit 7 INT: mux IMUX_IMUX[30] bit 0 INT: mux IMUX_IMUX[26] bit 1 INT: mux IMUX_IMUX[30] bit 8 INT: mux IMUX_IMUX[30] bit 9 INT: mux IMUX_IMUX[30] bit 10 INT: mux IMUX_CLK[0] bit 7 INT: mux IMUX_CLK[0] bit 6 INT: mux OMUX[9] bit 5 INT: mux OMUX[8] bit 6 -
B41 INT: mux LH[24] bit 9 INT: mux HEX_S0[5] bit 5 INT: mux HEX_N0[5] bit 3 INT: mux HEX_N0[5] bit 0 INT: mux DBL_S0[5] bit 2 INT: mux DBL_N0[5] bit 3 INT: mux DBL_S0[5] bit 6 INT: mux DBL_S0[5] bit 5 INT: mux IMUX_IMUX[30] bit 7 INT: mux IMUX_IMUX[26] bit 6 INT: mux IMUX_IMUX[30] bit 1 INT: mux IMUX_IMUX[26] bit 5 INT: mux IMUX_IMUX[30] bit 12 INT: mux IMUX_IMUX[30] bit 11 INT: mux IMUX_CLK[1] bit 0 INT: mux IMUX_CLK[1] bit 1 INT: mux OMUX[8] bit 3 INT: mux OMUX[8] bit 7 -
B40 INT: mux HEX_N0[5] bit 5 INT: mux HEX_S0[5] bit 4 INT: mux HEX_S0[5] bit 3 INT: mux HEX_S0[5] bit 1 INT: mux DBL_N0[5] bit 1 INT: mux DBL_S0[5] bit 0 INT: mux DBL_N0[5] bit 6 INT: mux DBL_N0[5] bit 4 INT: mux IMUX_IMUX[26] bit 0 INT: mux IMUX_IMUX[30] bit 3 INT: mux IMUX_IMUX[26] bit 8 INT: mux IMUX_IMUX[30] bit 4 INT: mux IMUX_IMUX[26] bit 11 INT: mux IMUX_IMUX[26] bit 9 INT: mux IMUX_CLK[1] bit 3 INT: mux IMUX_CLK[1] bit 2 INT: mux OMUX[8] bit 8 INT: mux OMUX[8] bit 9 -
B39 INT: mux HEX_E0[4] bit 5 INT: mux HEX_E0[4] bit 4 INT: mux HEX_W0[4] bit 3 INT: mux HEX_W0[4] bit 1 INT: mux DBL_W0[4] bit 1 INT: mux DBL_E0[4] bit 3 INT: mux DBL_W0[4] bit 7 INT: mux DBL_W0[4] bit 5 INT: mux IMUX_IMUX[5] bit 8 INT: mux IMUX_IMUX[1] bit 4 INT: mux IMUX_IMUX[5] bit 5 INT: mux IMUX_IMUX[1] bit 0 INT: mux IMUX_IMUX[1] bit 10 INT: mux IMUX_IMUX[1] bit 12 INT: mux IMUX_BOUNCE[3] bit 4 INT: mux IMUX_BOUNCE[3] bit 7 INT: mux OMUX[7] bit 8 INT: mux OMUX[7] bit 9 -
B38 INT: mux LH[0] bit 9 INT: mux HEX_W0[4] bit 5 INT: mux HEX_E0[4] bit 3 INT: mux HEX_E0[4] bit 1 INT: mux DBL_E0[4] bit 2 INT: mux DBL_W0[4] bit 0 INT: mux DBL_E0[4] bit 7 INT: mux DBL_E0[4] bit 5 INT: mux IMUX_IMUX[1] bit 6 INT: mux IMUX_IMUX[5] bit 7 INT: mux IMUX_IMUX[1] bit 1 INT: mux IMUX_IMUX[5] bit 2 INT: mux IMUX_IMUX[5] bit 9 INT: mux IMUX_IMUX[5] bit 12 INT: mux IMUX_BOUNCE[3] bit 6 INT: mux IMUX_BOUNCE[3] bit 5 INT: mux OMUX[6] bit 2 INT: mux OMUX[7] bit 7 -
B37 INT: mux LV[0] bit 9 INT: mux HEX_W0[4] bit 6 INT: mux HEX_E0[4] bit 2 INT: mux HEX_E0[4] bit 0 INT: mux DBL_E0[4] bit 1 INT: mux DBL_W0[4] bit 2 INT: mux DBL_E0[4] bit 6 INT: mux DBL_E0[4] bit 4 INT: mux IMUX_IMUX[5] bit 6 INT: mux IMUX_IMUX[1] bit 8 INT: mux IMUX_IMUX[5] bit 1 INT: mux IMUX_IMUX[1] bit 5 INT: mux IMUX_IMUX[5] bit 11 INT: mux IMUX_IMUX[5] bit 10 INT: mux IMUX_BOUNCE[2] bit 0 INT: mux IMUX_BOUNCE[2] bit 1 INT: mux OMUX[7] bit 0 INT: mux OMUX[7] bit 6 -
B36 INT: mux HEX_E0[4] bit 6 INT: mux HEX_W0[4] bit 4 INT: mux HEX_W0[4] bit 2 INT: mux HEX_W0[4] bit 0 INT: mux DBL_W0[4] bit 3 INT: mux DBL_E0[4] bit 0 INT: mux DBL_W0[4] bit 6 INT: mux DBL_W0[4] bit 4 INT: mux IMUX_IMUX[1] bit 7 INT: mux IMUX_IMUX[5] bit 4 INT: mux IMUX_IMUX[1] bit 2 INT: mux IMUX_IMUX[5] bit 0 INT: mux IMUX_IMUX[1] bit 11 INT: mux IMUX_IMUX[1] bit 9 INT: mux IMUX_BOUNCE[3] bit 1 INT: mux IMUX_BOUNCE[3] bit 2 INT: mux OMUX[6] bit 1 INT: mux OMUX[6] bit 0 -
B35 INT: mux HEX_S0[4] bit 6 INT: mux HEX_S0[4] bit 4 INT: mux HEX_N0[4] bit 2 INT: mux HEX_N0[4] bit 0 INT: mux DBL_N0[4] bit 2 INT: mux DBL_S0[4] bit 1 INT: mux DBL_N0[4] bit 7 INT: mux DBL_N0[4] bit 4 INT: mux IMUX_IMUX[13] bit 8 INT: mux IMUX_IMUX[9] bit 4 INT: mux IMUX_IMUX[13] bit 5 INT: mux IMUX_IMUX[9] bit 0 INT: mux IMUX_IMUX[9] bit 10 INT: mux IMUX_IMUX[9] bit 12 INT: mux IMUX_BOUNCE[2] bit 3 INT: mux IMUX_BOUNCE[2] bit 2 INT: mux OMUX[7] bit 2 INT: mux OMUX[7] bit 1 -
B34 INT: mux LV[0] bit 8 INT: mux HEX_N0[4] bit 6 INT: mux HEX_S0[4] bit 2 INT: mux HEX_S0[4] bit 0 INT: mux DBL_S0[4] bit 3 INT: mux DBL_N0[4] bit 0 INT: mux DBL_S0[4] bit 7 INT: mux DBL_S0[4] bit 4 INT: mux IMUX_IMUX[9] bit 6 INT: mux IMUX_IMUX[13] bit 7 INT: mux IMUX_IMUX[9] bit 1 INT: mux IMUX_IMUX[13] bit 2 INT: mux IMUX_IMUX[13] bit 9 INT: mux IMUX_IMUX[13] bit 12 INT: mux IMUX_BOUNCE[3] bit 0 INT: mux IMUX_BOUNCE[3] bit 3 INT: mux OMUX[7] bit 4 INT: mux OMUX[7] bit 3 -
B33 INT: mux LH[0] bit 8 INT: mux HEX_N0[4] bit 5 INT: mux HEX_S0[4] bit 3 INT: mux HEX_S0[4] bit 1 INT: mux DBL_S0[4] bit 2 INT: mux DBL_N0[4] bit 3 INT: mux DBL_S0[4] bit 6 INT: mux DBL_S0[4] bit 5 INT: mux IMUX_IMUX[13] bit 6 INT: mux IMUX_IMUX[9] bit 8 INT: mux IMUX_IMUX[13] bit 1 INT: mux IMUX_IMUX[9] bit 5 INT: mux IMUX_IMUX[13] bit 11 INT: mux IMUX_IMUX[13] bit 10 INT: mux IMUX_BOUNCE[2] bit 6 INT: mux IMUX_BOUNCE[2] bit 7 INT: mux OMUX[6] bit 4 INT: mux OMUX[6] bit 5 -
B32 INT: mux HEX_S0[4] bit 5 INT: mux HEX_N0[4] bit 4 INT: mux HEX_N0[4] bit 3 INT: mux HEX_N0[4] bit 1 INT: mux DBL_N0[4] bit 1 INT: mux DBL_S0[4] bit 0 INT: mux DBL_N0[4] bit 6 INT: mux DBL_N0[4] bit 5 INT: mux IMUX_IMUX[9] bit 7 INT: mux IMUX_IMUX[13] bit 4 INT: mux IMUX_IMUX[9] bit 2 INT: mux IMUX_IMUX[13] bit 0 INT: mux IMUX_IMUX[9] bit 11 INT: mux IMUX_IMUX[9] bit 9 INT: mux IMUX_BOUNCE[2] bit 5 INT: mux IMUX_BOUNCE[2] bit 4 INT: mux OMUX[7] bit 5 INT: mux OMUX[6] bit 6 -
B31 INT: mux HEX_W0[3] bit 5 INT: mux HEX_W0[3] bit 4 INT: mux HEX_E0[3] bit 3 INT: mux HEX_E0[3] bit 0 INT: mux DBL_W0[3] bit 1 INT: mux DBL_E0[3] bit 3 INT: mux DBL_W0[3] bit 7 INT: mux DBL_W0[3] bit 5 INT: mux IMUX_IMUX[21] bit 8 INT: mux IMUX_IMUX[17] bit 4 INT: mux IMUX_IMUX[21] bit 5 INT: mux IMUX_IMUX[17] bit 0 INT: mux IMUX_IMUX[17] bit 10 INT: mux IMUX_IMUX[17] bit 12 INT: mux IMUX_BOUNCE[1] bit 6 INT: mux IMUX_BOUNCE[1] bit 4 INT: mux OMUX[6] bit 3 INT: mux OMUX[6] bit 7 -
B30 INT: mux LH[0] bit 6 INT: mux HEX_E0[3] bit 5 INT: mux HEX_W0[3] bit 3 INT: mux HEX_W0[3] bit 1 INT: mux DBL_E0[3] bit 2 INT: mux DBL_W0[3] bit 0 INT: mux DBL_E0[3] bit 7 INT: mux DBL_E0[3] bit 4 INT: mux IMUX_IMUX[17] bit 6 INT: mux IMUX_IMUX[21] bit 7 INT: mux IMUX_IMUX[17] bit 1 INT: mux IMUX_IMUX[21] bit 2 INT: mux IMUX_IMUX[21] bit 9 INT: mux IMUX_IMUX[21] bit 12 INT: mux IMUX_BOUNCE[1] bit 5 INT: mux IMUX_BOUNCE[1] bit 7 INT: mux OMUX[6] bit 8 INT: mux OMUX[6] bit 9 -
B29 INT: mux LV[0] bit 6 INT: mux HEX_E0[3] bit 6 INT: mux HEX_W0[3] bit 2 INT: mux HEX_W0[3] bit 0 INT: mux DBL_E0[3] bit 1 INT: mux DBL_W0[3] bit 2 INT: mux DBL_E0[3] bit 6 INT: mux DBL_E0[3] bit 5 INT: mux IMUX_IMUX[21] bit 6 INT: mux IMUX_IMUX[17] bit 8 INT: mux IMUX_IMUX[21] bit 1 INT: mux IMUX_IMUX[17] bit 5 INT: mux IMUX_IMUX[21] bit 11 INT: mux IMUX_IMUX[21] bit 10 INT: mux IMUX_BOUNCE[0] bit 0 INT: mux IMUX_BOUNCE[0] bit 1 INT: mux OMUX[5] bit 8 INT: mux OMUX[5] bit 9 INT: !invert IMUX_CLK_OPTINV[0] ← IMUX_CLK[0]
B28 INT: mux HEX_W0[3] bit 6 INT: mux HEX_E0[3] bit 4 INT: mux HEX_E0[3] bit 2 INT: mux HEX_E0[3] bit 1 INT: mux DBL_W0[3] bit 3 INT: mux DBL_E0[3] bit 0 INT: mux DBL_W0[3] bit 6 INT: mux DBL_W0[3] bit 4 INT: mux IMUX_IMUX[17] bit 7 INT: mux IMUX_IMUX[21] bit 4 INT: mux IMUX_IMUX[17] bit 2 INT: mux IMUX_IMUX[21] bit 0 INT: mux IMUX_IMUX[17] bit 11 INT: mux IMUX_IMUX[17] bit 9 INT: mux IMUX_BOUNCE[1] bit 1 INT: mux IMUX_BOUNCE[1] bit 2 INT: mux OMUX[4] bit 2 INT: mux OMUX[5] bit 7 INT: mux LH[0] bit 0
B27 INT: mux HEX_N0[3] bit 6 INT: mux HEX_N0[3] bit 4 INT: mux HEX_S0[3] bit 2 INT: mux HEX_S0[3] bit 1 INT: mux DBL_N0[3] bit 2 INT: mux DBL_S0[3] bit 1 INT: mux DBL_N0[3] bit 7 INT: mux DBL_N0[3] bit 4 INT: mux IMUX_IMUX[29] bit 8 INT: mux IMUX_IMUX[25] bit 4 INT: mux IMUX_IMUX[29] bit 5 INT: mux IMUX_IMUX[25] bit 0 INT: mux IMUX_IMUX[25] bit 10 INT: mux IMUX_IMUX[25] bit 12 INT: mux IMUX_BOUNCE[0] bit 3 INT: mux IMUX_BOUNCE[0] bit 2 INT: mux OMUX[5] bit 0 INT: mux OMUX[5] bit 6 INT: !invert IMUX_CLK_OPTINV[1] ← IMUX_CLK[1]
B26 INT: mux LV[0] bit 3 INT: mux HEX_S0[3] bit 6 INT: mux HEX_N0[3] bit 2 INT: mux HEX_N0[3] bit 0 INT: mux DBL_S0[3] bit 3 INT: mux DBL_N0[3] bit 0 INT: mux DBL_S0[3] bit 7 INT: mux DBL_S0[3] bit 5 INT: mux IMUX_IMUX[25] bit 6 INT: mux IMUX_IMUX[29] bit 7 INT: mux IMUX_IMUX[25] bit 1 INT: mux IMUX_IMUX[29] bit 2 INT: mux IMUX_IMUX[29] bit 9 INT: mux IMUX_IMUX[29] bit 12 INT: mux IMUX_BOUNCE[1] bit 0 INT: mux IMUX_BOUNCE[1] bit 3 INT: mux OMUX[4] bit 1 INT: mux OMUX[4] bit 0 INT: !invert IMUX_SR_OPTINV[1] ← IMUX_SR[1]
B25 INT: mux LH[0] bit 3 INT: mux HEX_S0[3] bit 5 INT: mux HEX_N0[3] bit 3 INT: mux HEX_N0[3] bit 1 INT: mux DBL_S0[3] bit 2 INT: mux DBL_N0[3] bit 3 INT: mux DBL_S0[3] bit 6 INT: mux DBL_S0[3] bit 4 INT: mux IMUX_IMUX[29] bit 6 INT: mux IMUX_IMUX[25] bit 8 INT: mux IMUX_IMUX[29] bit 1 INT: mux IMUX_IMUX[25] bit 5 INT: mux IMUX_IMUX[29] bit 11 INT: mux IMUX_IMUX[29] bit 10 INT: mux IMUX_BOUNCE[0] bit 5 INT: mux IMUX_BOUNCE[0] bit 4 INT: mux OMUX[5] bit 2 INT: mux OMUX[5] bit 1 INT: !invert IMUX_SR_OPTINV[3] ← IMUX_SR[3]
B24 INT: mux HEX_N0[3] bit 5 INT: mux HEX_S0[3] bit 4 INT: mux HEX_S0[3] bit 3 INT: mux HEX_S0[3] bit 0 INT: mux DBL_N0[3] bit 1 INT: mux DBL_S0[3] bit 0 INT: mux DBL_N0[3] bit 6 INT: mux DBL_N0[3] bit 5 INT: mux IMUX_IMUX[25] bit 7 INT: mux IMUX_IMUX[29] bit 4 INT: mux IMUX_IMUX[25] bit 2 INT: mux IMUX_IMUX[29] bit 0 INT: mux IMUX_IMUX[25] bit 11 INT: mux IMUX_IMUX[25] bit 9 INT: mux IMUX_BOUNCE[0] bit 7 INT: mux IMUX_BOUNCE[0] bit 6 INT: mux OMUX[5] bit 4 INT: mux OMUX[5] bit 3 INT: !invert IMUX_SR_OPTINV[0] ← IMUX_SR[0]
B23 INT: mux HEX_E0[2] bit 4 INT: mux HEX_E0[2] bit 5 INT: mux HEX_W0[2] bit 3 INT: mux HEX_W0[2] bit 1 INT: mux DBL_W0[2] bit 6 INT: mux DBL_E0[2] bit 7 INT: mux DBL_W0[2] bit 3 INT: mux DBL_W0[2] bit 1 INT: mux IMUX_BYP[6] bit 8 INT: mux IMUX_BYP[4] bit 4 INT: mux IMUX_BYP[6] bit 5 INT: mux IMUX_BYP[4] bit 0 INT: mux IMUX_BYP[4] bit 10 INT: mux IMUX_BYP[4] bit 12 INT: mux IMUX_IMUX[29] bit 3 INT: mux IMUX_IMUX[13] bit 3 INT: mux OMUX[4] bit 4 INT: mux OMUX[4] bit 5 INT: !invert IMUX_SR_OPTINV[2] ← IMUX_SR[2]
B22 INT: mux LH[0] bit 10 INT: mux HEX_W0[2] bit 4 INT: mux HEX_E0[2] bit 3 INT: mux HEX_E0[2] bit 1 INT: mux DBL_E0[2] bit 4 INT: mux DBL_W0[2] bit 5 INT: mux DBL_E0[2] bit 3 INT: mux DBL_E0[2] bit 1 INT: mux IMUX_BYP[4] bit 6 INT: mux IMUX_BYP[6] bit 7 INT: mux IMUX_BYP[4] bit 1 INT: mux IMUX_BYP[6] bit 2 INT: mux IMUX_BYP[6] bit 9 INT: mux IMUX_BYP[6] bit 12 INT: mux IMUX_IMUX[17] bit 3 INT: mux IMUX_IMUX[9] bit 3 INT: mux OMUX[5] bit 5 INT: mux OMUX[4] bit 6 -
B21 INT: mux LH[0] bit 5 INT: mux HEX_W0[2] bit 6 INT: mux HEX_E0[2] bit 2 INT: mux HEX_E0[2] bit 0 INT: mux DBL_E0[2] bit 6 INT: mux DBL_W0[2] bit 4 INT: mux DBL_E0[2] bit 2 INT: mux DBL_E0[2] bit 0 INT: mux IMUX_BYP[6] bit 6 INT: mux IMUX_BYP[4] bit 8 INT: mux IMUX_BYP[6] bit 1 INT: mux IMUX_BYP[4] bit 5 INT: mux IMUX_BYP[6] bit 11 INT: mux IMUX_BYP[6] bit 10 INT: mux IMUX_IMUX[25] bit 3 INT: mux IMUX_IMUX[1] bit 3 INT: mux OMUX[4] bit 3 INT: mux OMUX[4] bit 7 -
B20 INT: mux HEX_E0[2] bit 6 INT: mux HEX_W0[2] bit 5 INT: mux HEX_W0[2] bit 2 INT: mux HEX_W0[2] bit 0 INT: mux DBL_W0[2] bit 7 INT: mux DBL_E0[2] bit 5 INT: mux DBL_W0[2] bit 2 INT: mux DBL_W0[2] bit 0 INT: mux IMUX_BYP[4] bit 7 INT: mux IMUX_BYP[6] bit 4 INT: mux IMUX_BYP[4] bit 2 INT: mux IMUX_BYP[6] bit 0 INT: mux IMUX_BYP[4] bit 11 INT: mux IMUX_BYP[4] bit 9 INT: mux IMUX_BYP[6] bit 3 INT: mux IMUX_BYP[4] bit 3 INT: mux OMUX[4] bit 8 INT: mux OMUX[4] bit 9 INT: mux LV[0] bit 0
B19 INT: mux HEX_S0[2] bit 6 INT: mux HEX_S0[2] bit 5 INT: mux HEX_N0[2] bit 2 INT: mux HEX_N0[2] bit 0 INT: mux DBL_N0[2] bit 7 INT: mux DBL_S0[2] bit 6 INT: mux DBL_N0[2] bit 3 INT: mux DBL_N0[2] bit 0 INT: mux IMUX_BYP[2] bit 6 INT: mux IMUX_BYP[0] bit 0 INT: mux IMUX_BYP[2] bit 3 INT: mux IMUX_BYP[0] bit 5 INT: mux IMUX_BYP[0] bit 10 INT: mux IMUX_BYP[0] bit 11 INT: mux IMUX_BYP[2] bit 4 INT: mux IMUX_IMUX[5] bit 3 INT: mux OMUX[3] bit 8 INT: mux OMUX[3] bit 9 -
B18 INT: mux LV[0] bit 5 INT: mux HEX_N0[2] bit 6 INT: mux HEX_S0[2] bit 2 INT: mux HEX_S0[2] bit 0 INT: mux DBL_S0[2] bit 4 INT: mux DBL_N0[2] bit 5 INT: mux DBL_S0[2] bit 3 INT: mux DBL_S0[2] bit 0 INT: mux IMUX_BYP[0] bit 7 INT: mux IMUX_BYP[2] bit 2 INT: mux IMUX_BYP[0] bit 1 INT: mux IMUX_BYP[2] bit 8 INT: mux IMUX_BYP[2] bit 9 INT: mux IMUX_BYP[2] bit 11 INT: mux IMUX_IMUX[0] bit 4 INT: mux IMUX_IMUX[21] bit 3 INT: mux OMUX[2] bit 2 INT: mux OMUX[3] bit 7 -
B17 INT: mux LV[0] bit 10 INT: mux HEX_N0[2] bit 4 INT: mux HEX_S0[2] bit 3 INT: mux HEX_S0[2] bit 1 INT: mux DBL_S0[2] bit 7 INT: mux DBL_N0[2] bit 4 INT: mux DBL_S0[2] bit 2 INT: mux DBL_S0[2] bit 1 INT: mux IMUX_BYP[2] bit 7 INT: mux IMUX_BYP[0] bit 6 INT: mux IMUX_BYP[2] bit 1 INT: mux IMUX_BYP[0] bit 3 INT: mux IMUX_BYP[2] bit 12 INT: mux IMUX_BYP[2] bit 10 INT: mux IMUX_IMUX[4] bit 4 INT: mux IMUX_IMUX[12] bit 4 INT: mux OMUX[3] bit 0 INT: mux OMUX[3] bit 6 -
B16 INT: mux HEX_S0[2] bit 4 INT: mux HEX_N0[2] bit 5 INT: mux HEX_N0[2] bit 3 INT: mux HEX_N0[2] bit 1 INT: mux DBL_N0[2] bit 6 INT: mux DBL_S0[2] bit 5 INT: mux DBL_N0[2] bit 2 INT: mux DBL_N0[2] bit 1 INT: mux IMUX_BYP[0] bit 2 INT: mux IMUX_BYP[2] bit 0 INT: mux IMUX_BYP[0] bit 8 INT: mux IMUX_BYP[2] bit 5 INT: mux IMUX_BYP[0] bit 12 INT: mux IMUX_BYP[0] bit 9 INT: mux IMUX_BYP[0] bit 4 INT: mux IMUX_IMUX[8] bit 4 INT: mux OMUX[2] bit 1 INT: mux OMUX[2] bit 0 -
B15 INT: mux HEX_W0[1] bit 5 INT: mux HEX_W0[1] bit 4 INT: mux HEX_E0[1] bit 3 INT: mux HEX_E0[1] bit 0 INT: mux DBL_W0[1] bit 1 INT: mux DBL_E0[1] bit 3 INT: mux DBL_W0[1] bit 6 INT: mux DBL_W0[1] bit 5 INT: mux IMUX_IMUX[4] bit 6 INT: mux IMUX_IMUX[0] bit 0 INT: mux IMUX_IMUX[4] bit 3 INT: mux IMUX_IMUX[0] bit 5 INT: mux IMUX_IMUX[0] bit 10 INT: mux IMUX_IMUX[0] bit 11 INT: mux IMUX_SR[1] bit 6 INT: mux IMUX_SR[1] bit 7 INT: mux OMUX[3] bit 2 INT: mux OMUX[3] bit 1 -
B14 INT: mux LV[0] bit 4 INT: mux HEX_E0[1] bit 5 INT: mux HEX_W0[1] bit 2 INT: mux HEX_W0[1] bit 1 INT: mux DBL_E0[1] bit 2 INT: mux DBL_W0[1] bit 0 INT: mux DBL_E0[1] bit 7 INT: mux DBL_E0[1] bit 4 INT: mux IMUX_IMUX[0] bit 7 INT: mux IMUX_IMUX[4] bit 2 INT: mux IMUX_IMUX[0] bit 1 INT: mux IMUX_IMUX[4] bit 8 INT: mux IMUX_IMUX[4] bit 9 INT: mux IMUX_IMUX[4] bit 11 INT: mux IMUX_SR[1] bit 5 INT: mux IMUX_SR[1] bit 4 INT: mux OMUX[3] bit 4 INT: mux OMUX[3] bit 3 -
B13 INT: mux LH[0] bit 4 INT: mux HEX_E0[1] bit 6 INT: mux HEX_W0[1] bit 3 INT: mux HEX_W0[1] bit 0 INT: mux DBL_E0[1] bit 1 INT: mux DBL_W0[1] bit 2 INT: mux DBL_E0[1] bit 6 INT: mux DBL_E0[1] bit 5 INT: mux IMUX_IMUX[4] bit 7 INT: mux IMUX_IMUX[0] bit 6 INT: mux IMUX_IMUX[4] bit 1 INT: mux IMUX_IMUX[0] bit 3 INT: mux IMUX_IMUX[4] bit 12 INT: mux IMUX_IMUX[4] bit 10 INT: mux IMUX_SR[3] bit 4 INT: mux IMUX_SR[3] bit 7 INT: mux OMUX[2] bit 4 INT: mux OMUX[2] bit 5 -
B12 INT: mux HEX_W0[1] bit 6 INT: mux HEX_E0[1] bit 4 INT: mux HEX_E0[1] bit 2 INT: mux HEX_E0[1] bit 1 INT: mux DBL_W0[1] bit 3 INT: mux DBL_E0[1] bit 0 INT: mux DBL_W0[1] bit 7 INT: mux DBL_W0[1] bit 4 INT: mux IMUX_IMUX[0] bit 2 INT: mux IMUX_IMUX[4] bit 0 INT: mux IMUX_IMUX[0] bit 8 INT: mux IMUX_IMUX[4] bit 5 INT: mux IMUX_IMUX[0] bit 12 INT: mux IMUX_IMUX[0] bit 9 INT: mux IMUX_SR[1] bit 3 INT: mux IMUX_SR[1] bit 2 INT: mux OMUX[3] bit 5 INT: mux OMUX[2] bit 6 -
B11 INT: mux HEX_N0[1] bit 6 INT: mux HEX_N0[1] bit 4 INT: mux HEX_S0[1] bit 2 INT: mux HEX_S0[1] bit 0 INT: mux DBL_N0[1] bit 2 INT: mux DBL_S0[1] bit 1 INT: mux DBL_N0[1] bit 7 INT: mux DBL_N0[1] bit 4 INT: mux IMUX_IMUX[12] bit 6 INT: mux IMUX_IMUX[8] bit 0 INT: mux IMUX_IMUX[12] bit 3 INT: mux IMUX_IMUX[8] bit 5 INT: mux IMUX_IMUX[8] bit 10 INT: mux IMUX_IMUX[8] bit 11 INT: mux IMUX_SR[3] bit 5 INT: mux IMUX_SR[3] bit 6 INT: mux OMUX[2] bit 3 INT: mux OMUX[2] bit 7 -
B10 INT: mux LH[0] bit 7 INT: mux HEX_S0[1] bit 6 INT: mux HEX_N0[1] bit 2 INT: mux HEX_N0[1] bit 0 INT: mux DBL_S0[1] bit 3 INT: mux DBL_N0[1] bit 0 INT: mux DBL_S0[1] bit 7 INT: mux DBL_S0[1] bit 4 INT: mux IMUX_IMUX[8] bit 7 INT: mux IMUX_IMUX[12] bit 2 INT: mux IMUX_IMUX[8] bit 1 INT: mux IMUX_IMUX[12] bit 8 INT: mux IMUX_IMUX[12] bit 9 INT: mux IMUX_IMUX[12] bit 11 INT: mux IMUX_SR[1] bit 0 INT: mux IMUX_SR[1] bit 1 INT: mux OMUX[2] bit 8 INT: mux OMUX[2] bit 9 -
B9 INT: mux LV[0] bit 7 INT: mux HEX_S0[1] bit 5 INT: mux HEX_N0[1] bit 3 INT: mux HEX_N0[1] bit 1 INT: mux DBL_S0[1] bit 2 INT: mux DBL_N0[1] bit 3 INT: mux DBL_S0[1] bit 6 INT: mux DBL_S0[1] bit 5 INT: mux IMUX_IMUX[12] bit 7 INT: mux IMUX_IMUX[8] bit 6 INT: mux IMUX_IMUX[12] bit 1 INT: mux IMUX_IMUX[8] bit 3 INT: mux IMUX_IMUX[12] bit 12 INT: mux IMUX_IMUX[12] bit 10 INT: mux IMUX_SR[3] bit 3 INT: mux IMUX_SR[3] bit 1 INT: mux OMUX[1] bit 8 INT: mux OMUX[1] bit 9 -
B8 INT: mux HEX_N0[1] bit 5 INT: mux HEX_S0[1] bit 4 INT: mux HEX_S0[1] bit 3 INT: mux HEX_S0[1] bit 1 INT: mux DBL_N0[1] bit 1 INT: mux DBL_S0[1] bit 0 INT: mux DBL_N0[1] bit 6 INT: mux DBL_N0[1] bit 5 INT: mux IMUX_IMUX[8] bit 2 INT: mux IMUX_IMUX[12] bit 0 INT: mux IMUX_IMUX[8] bit 8 INT: mux IMUX_IMUX[12] bit 5 INT: mux IMUX_IMUX[8] bit 12 INT: mux IMUX_IMUX[8] bit 9 INT: mux IMUX_SR[3] bit 0 INT: mux IMUX_SR[3] bit 2 INT: mux OMUX[0] bit 2 INT: mux OMUX[1] bit 7 -
B7 INT: mux HEX_E0[0] bit 5 INT: mux HEX_E0[0] bit 4 INT: mux HEX_W0[0] bit 2 INT: mux HEX_W0[0] bit 1 INT: mux DBL_W0[0] bit 1 INT: mux DBL_E0[0] bit 3 INT: mux DBL_W0[0] bit 6 INT: mux DBL_W0[0] bit 5 INT: mux IMUX_IMUX[20] bit 6 INT: mux IMUX_IMUX[16] bit 0 INT: mux IMUX_IMUX[20] bit 3 INT: mux IMUX_IMUX[16] bit 5 INT: mux IMUX_IMUX[16] bit 10 INT: mux IMUX_IMUX[16] bit 11 INT: mux IMUX_SR[0] bit 7 INT: mux IMUX_SR[0] bit 4 INT: mux OMUX[1] bit 0 INT: mux OMUX[1] bit 6 -
B6 INT: mux LV[0] bit 2 INT: mux HEX_W0[0] bit 5 INT: mux HEX_E0[0] bit 3 INT: mux HEX_E0[0] bit 0 INT: mux DBL_E0[0] bit 2 INT: mux DBL_W0[0] bit 0 INT: mux DBL_E0[0] bit 7 INT: mux DBL_E0[0] bit 4 INT: mux IMUX_IMUX[16] bit 7 INT: mux IMUX_IMUX[20] bit 2 INT: mux IMUX_IMUX[16] bit 1 INT: mux IMUX_IMUX[20] bit 8 INT: mux IMUX_IMUX[20] bit 9 INT: mux IMUX_IMUX[20] bit 11 INT: mux IMUX_SR[0] bit 6 INT: mux IMUX_SR[0] bit 5 INT: mux OMUX[0] bit 1 INT: mux OMUX[0] bit 0 INT: mux IMUX_IMUX[20] bit 4
B5 INT: mux LH[0] bit 2 INT: mux HEX_W0[0] bit 6 INT: mux HEX_E0[0] bit 2 INT: mux HEX_E0[0] bit 1 INT: mux DBL_E0[0] bit 1 INT: mux DBL_W0[0] bit 2 INT: mux DBL_E0[0] bit 6 INT: mux DBL_E0[0] bit 5 INT: mux IMUX_IMUX[20] bit 7 INT: mux IMUX_IMUX[16] bit 6 INT: mux IMUX_IMUX[20] bit 1 INT: mux IMUX_IMUX[16] bit 3 INT: mux IMUX_IMUX[20] bit 12 INT: mux IMUX_IMUX[20] bit 10 INT: mux IMUX_SR[2] bit 0 INT: mux IMUX_SR[2] bit 3 INT: mux OMUX[1] bit 2 INT: mux OMUX[1] bit 1 -
B4 INT: mux HEX_E0[0] bit 6 INT: mux HEX_W0[0] bit 4 INT: mux HEX_W0[0] bit 3 INT: mux HEX_W0[0] bit 0 INT: mux DBL_W0[0] bit 3 INT: mux DBL_E0[0] bit 0 INT: mux DBL_W0[0] bit 7 INT: mux DBL_W0[0] bit 4 INT: mux IMUX_IMUX[16] bit 2 INT: mux IMUX_IMUX[20] bit 0 INT: mux IMUX_IMUX[16] bit 8 INT: mux IMUX_IMUX[20] bit 5 INT: mux IMUX_IMUX[16] bit 12 INT: mux IMUX_IMUX[16] bit 9 INT: mux IMUX_SR[0] bit 3 INT: mux IMUX_SR[0] bit 2 INT: mux OMUX[1] bit 4 INT: mux OMUX[1] bit 3 INT: mux IMUX_IMUX[16] bit 4
B3 INT: mux HEX_S0[0] bit 4 INT: mux HEX_S0[0] bit 5 INT: mux HEX_N0[0] bit 2 INT: mux HEX_N0[0] bit 1 INT: mux DBL_N0[0] bit 7 INT: mux DBL_S0[0] bit 6 INT: mux DBL_N0[0] bit 3 INT: mux DBL_N0[0] bit 1 INT: mux IMUX_IMUX[28] bit 6 INT: mux IMUX_IMUX[24] bit 0 INT: mux IMUX_IMUX[28] bit 3 INT: mux IMUX_IMUX[24] bit 5 INT: mux IMUX_IMUX[24] bit 10 INT: mux IMUX_IMUX[24] bit 11 INT: mux IMUX_SR[2] bit 1 INT: mux IMUX_SR[2] bit 2 INT: mux OMUX[0] bit 4 INT: mux OMUX[0] bit 5 INT: mux IMUX_IMUX[28] bit 4
B2 INT: mux LH[0] bit 1 INT: mux HEX_N0[0] bit 4 INT: mux HEX_S0[0] bit 2 INT: mux HEX_S0[0] bit 1 INT: mux DBL_S0[0] bit 4 INT: mux DBL_N0[0] bit 5 INT: mux DBL_S0[0] bit 3 INT: mux DBL_S0[0] bit 1 INT: mux IMUX_IMUX[24] bit 7 INT: mux IMUX_IMUX[28] bit 2 INT: mux IMUX_IMUX[24] bit 1 INT: mux IMUX_IMUX[28] bit 8 INT: mux IMUX_IMUX[28] bit 9 INT: mux IMUX_IMUX[28] bit 11 INT: mux IMUX_SR[0] bit 0 INT: mux IMUX_SR[0] bit 1 INT: mux OMUX[1] bit 5 INT: mux OMUX[0] bit 6 -
B1 INT: mux LV[0] bit 1 INT: mux HEX_N0[0] bit 6 INT: mux HEX_S0[0] bit 3 INT: mux HEX_S0[0] bit 0 INT: mux DBL_S0[0] bit 7 INT: mux DBL_N0[0] bit 4 INT: mux DBL_S0[0] bit 2 INT: mux DBL_S0[0] bit 0 INT: mux IMUX_IMUX[28] bit 7 INT: mux IMUX_IMUX[24] bit 6 INT: mux IMUX_IMUX[28] bit 1 INT: mux IMUX_IMUX[24] bit 3 INT: mux IMUX_IMUX[28] bit 12 INT: mux IMUX_IMUX[28] bit 10 INT: mux IMUX_SR[2] bit 7 INT: mux IMUX_SR[2] bit 4 INT: mux OMUX[0] bit 3 INT: mux OMUX[0] bit 7 INT: mux IMUX_IMUX[24] bit 4
B0 INT: mux HEX_S0[0] bit 6 INT: mux HEX_N0[0] bit 5 INT: mux HEX_N0[0] bit 3 INT: mux HEX_N0[0] bit 0 INT: mux DBL_N0[0] bit 6 INT: mux DBL_S0[0] bit 5 INT: mux DBL_N0[0] bit 2 INT: mux DBL_N0[0] bit 0 INT: mux IMUX_IMUX[24] bit 2 INT: mux IMUX_IMUX[28] bit 0 INT: mux IMUX_IMUX[24] bit 8 INT: mux IMUX_IMUX[28] bit 5 INT: mux IMUX_IMUX[24] bit 12 INT: mux IMUX_IMUX[24] bit 9 INT: mux IMUX_SR[2] bit 6 INT: mux IMUX_SR[2] bit 5 INT: mux OMUX[0] bit 8 INT: mux OMUX[0] bit 9 -

Tile INTF

Cells: 1

Switchbox INTF_INT

virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[0]
BitsDestination
MAIN[18][2]OUT_HALF0_TEST[0]
Source
0IMUX_IMUX[20]
1IMUX_SR_OPTINV[2]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[1]
BitsDestination
MAIN[18][0]OUT_HALF0_TEST[1]
Source
0IMUX_IMUX[24]
1IMUX_SR_OPTINV[0]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[2]
BitsDestination
MAIN[18][33]OUT_HALF0_TEST[2]
Source
0IMUX_IMUX[5]
1IMUX_SPEC[3]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[3]
BitsDestination
MAIN[18][32]OUT_HALF0_TEST[3]
Source
0IMUX_IMUX[9]
1IMUX_SPEC[1]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[4]
BitsDestination
MAIN[18][15]OUT_HALF0_TEST[4]
Source
0IMUX_IMUX[21]
1IMUX_SPEC[2]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[5]
BitsDestination
MAIN[18][7]OUT_HALF0_TEST[5]
Source
0IMUX_IMUX[8]
1IMUX_SR_OPTINV[1]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[6]
BitsDestination
MAIN[18][13]OUT_HALF0_TEST[6]
Source
0IMUX_IMUX[25]
1IMUX_SPEC[0]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF0_TEST[7]
BitsDestination
MAIN[18][10]OUT_HALF0_TEST[7]
Source
0IMUX_IMUX[4]
1IMUX_SR_OPTINV[3]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[0]
BitsDestination
MAIN[18][47]OUT_HALF1_TEST[0]
Source
0IMUX_IMUX[22]
1IMUX_CLK_OPTINV[2]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[1]
BitsDestination
MAIN[18][43]OUT_HALF1_TEST[1]
Source
0IMUX_IMUX[26]
1IMUX_CLK_OPTINV[0]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[2]
BitsDestination
MAIN[18][69]OUT_HALF1_TEST[2]
Source
0IMUX_IMUX[27]
1IMUX_CE_OPTINV[0]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[3]
BitsDestination
MAIN[18][77]OUT_HALF1_TEST[3]
Source
0IMUX_IMUX[7]
1IMUX_CE_OPTINV[3]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[4]
BitsDestination
MAIN[18][64]OUT_HALF1_TEST[4]
Source
0IMUX_IMUX[10]
1IMUX_CLK_OPTINV[1]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[5]
BitsDestination
MAIN[18][66]OUT_HALF1_TEST[5]
Source
0IMUX_IMUX[6]
1IMUX_CLK_OPTINV[3]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[6]
BitsDestination
MAIN[18][71]OUT_HALF1_TEST[6]
Source
0IMUX_IMUX[23]
1IMUX_CE_OPTINV[2]
virtex4 INTF switchbox INTF_INT muxes OUT_HALF1_TEST[7]
BitsDestination
MAIN[18][74]OUT_HALF1_TEST[7]
Source
0IMUX_IMUX[11]
1IMUX_CE_OPTINV[1]

Test mux INTF_TESTMUX

virtex4 INTF INTF_TESTMUX mux
DestinationPrimary source Test source 0
OUT_BEST[0]OUT_BEST_TMIN[0] IMUX_IMUX[3]
OUT_BEST[1]OUT_BEST_TMIN[1] IMUX_IMUX[2]
OUT_BEST[2]OUT_BEST_TMIN[2] IMUX_IMUX[1]
OUT_BEST[3]OUT_BEST_TMIN[3] IMUX_IMUX[0]
OUT_BEST[4]OUT_BEST_TMIN[4] IMUX_IMUX[16]
OUT_BEST[5]OUT_BEST_TMIN[5] IMUX_IMUX[17]
OUT_BEST[6]OUT_BEST_TMIN[6] IMUX_IMUX[18]
OUT_BEST[7]OUT_BEST_TMIN[7] IMUX_IMUX[19]
OUT_SEC[0]OUT_SEC_TMIN[0] IMUX_IMUX[12]
OUT_SEC[1]OUT_SEC_TMIN[1] IMUX_IMUX[28]
OUT_SEC[2]OUT_SEC_TMIN[2] IMUX_IMUX[14]
OUT_SEC[3]OUT_SEC_TMIN[3] IMUX_IMUX[30]
OUT_SEC[4]OUT_SEC_TMIN[4] IMUX_IMUX[29]
OUT_SEC[5]OUT_SEC_TMIN[5] IMUX_IMUX[13]
OUT_SEC[6]OUT_SEC_TMIN[6] IMUX_IMUX[15]
OUT_SEC[7]OUT_SEC_TMIN[7] IMUX_IMUX[31]
OUT_HALF0[0]OUT_HALF0_BEL[0] OUT_HALF0_TEST[0]
OUT_HALF0[1]OUT_HALF0_BEL[1] OUT_HALF0_TEST[1]
OUT_HALF0[2]OUT_HALF0_BEL[2] OUT_HALF0_TEST[2]
OUT_HALF0[3]OUT_HALF0_BEL[3] OUT_HALF0_TEST[3]
OUT_HALF0[4]OUT_HALF0_BEL[4] OUT_HALF0_TEST[4]
OUT_HALF0[5]OUT_HALF0_BEL[5] OUT_HALF0_TEST[5]
OUT_HALF0[6]OUT_HALF0_BEL[6] OUT_HALF0_TEST[6]
OUT_HALF0[7]OUT_HALF0_BEL[7] OUT_HALF0_TEST[7]
OUT_HALF1[0]OUT_HALF1_BEL[0] OUT_HALF1_TEST[0]
OUT_HALF1[1]OUT_HALF1_BEL[1] OUT_HALF1_TEST[1]
OUT_HALF1[2]OUT_HALF1_BEL[2] OUT_HALF1_TEST[2]
OUT_HALF1[3]OUT_HALF1_BEL[3] OUT_HALF1_TEST[3]
OUT_HALF1[4]OUT_HALF1_BEL[4] OUT_HALF1_TEST[4]
OUT_HALF1[5]OUT_HALF1_BEL[5] OUT_HALF1_TEST[5]
OUT_HALF1[6]OUT_HALF1_BEL[6] OUT_HALF1_TEST[6]
OUT_HALF1[7]OUT_HALF1_BEL[7] OUT_HALF1_TEST[7]
virtex4 INTF INTF_TESTMUX bits
GroupMAIN[18][40]
Primary0
Test 01

Bitstream

virtex4 INTF rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
B79 - - - - - - - - - - - - - - - - - - -
B78 - - - - - - - - - - - - - - - - - - -
B77 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[3] bit 0
B76 - - - - - - - - - - - - - - - - - - -
B75 - - - - - - - - - - - - - - - - - - -
B74 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[7] bit 0
B73 - - - - - - - - - - - - - - - - - - -
B72 - - - - - - - - - - - - - - - - - - -
B71 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[6] bit 0
B70 - - - - - - - - - - - - - - - - - - -
B69 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[2] bit 0
B68 - - - - - - - - - - - - - - - - - - -
B67 - - - - - - - - - - - - - - - - - - -
B66 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[5] bit 0
B65 - - - - - - - - - - - - - - - - - - -
B64 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[4] bit 0
B63 - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[0] bit 0
B46 - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF1_TEST[1] bit 0
B42 - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - INTF_TESTMUX: test mux bit 0
B39 - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[2] bit 0
B32 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[3] bit 0
B31 - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - -
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B18 - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[4] bit 0
B14 - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[6] bit 0
B12 - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[7] bit 0
B9 - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[5] bit 0
B6 - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[0] bit 0
B1 - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - INTF_INT: mux OUT_HALF0_TEST[1] bit 0