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Global buffers

Tile CLK_BUFG

Cells: 22

Switchbox SPEC_INT

virtex5 CLK_BUFG switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[0].MGT_BUF[0]CELL[0].MGT_ROW_I[0]MAIN[1][1][0]
CELL[0].MGT_BUF[1]CELL[0].MGT_ROW_I[1]MAIN[1][0][0]
CELL[0].MGT_BUF[2]CELL[0].MGT_ROW_I[2]MAIN[1][0][1]
CELL[0].MGT_BUF[3]CELL[0].MGT_ROW_I[3]MAIN[1][1][1]
CELL[0].MGT_BUF[4]CELL[0].MGT_ROW_I[4]MAIN[1][1][2]
CELL[0].MGT_BUF[5]CELL_E0.MGT_ROW_I[0]MAIN[1][3][0]
CELL[0].MGT_BUF[6]CELL_E0.MGT_ROW_I[1]MAIN[1][2][0]
CELL[0].MGT_BUF[7]CELL_E0.MGT_ROW_I[2]MAIN[1][2][1]
CELL[0].MGT_BUF[8]CELL_E0.MGT_ROW_I[3]MAIN[1][3][1]
CELL[0].MGT_BUF[9]CELL_E0.MGT_ROW_I[4]MAIN[1][3][2]
CELL[2].OUT_BEL[0]CELL[0].IMUX_BUFG_O[3]MAIN[1][2][28]
CELL[2].OUT_BEL[1]CELL[0].IMUX_BUFG_O[2]MAIN[1][0][28]
CELL[2].OUT_BEL[2]CELL[0].IMUX_BUFG_O[1]MAIN[1][2][12]
CELL[2].OUT_BEL[3]CELL[0].IMUX_BUFG_O[0]MAIN[1][0][12]
CELL[2].OUT_BEL[4]CELL[0].IMUX_BUFG_O[7]MAIN[1][2][60]
CELL[2].OUT_BEL[5]CELL[0].IMUX_BUFG_O[6]MAIN[1][0][60]
CELL[2].OUT_BEL[6]CELL[0].IMUX_BUFG_O[5]MAIN[1][2][44]
CELL[2].OUT_BEL[7]CELL[0].IMUX_BUFG_O[4]MAIN[1][0][44]
CELL[2].OUT_BEL[8]CELL[0].IMUX_BUFG_O[11]MAIN[2][2][28]
CELL[2].OUT_BEL[9]CELL[0].IMUX_BUFG_O[10]MAIN[2][0][28]
CELL[2].OUT_BEL[10]CELL[0].IMUX_BUFG_O[9]MAIN[2][2][12]
CELL[2].OUT_BEL[11]CELL[0].IMUX_BUFG_O[8]MAIN[2][0][12]
CELL[3].OUT_BEL[0]CELL[0].IMUX_BUFG_O[15]MAIN[2][2][60]
CELL[3].OUT_BEL[1]CELL[0].IMUX_BUFG_O[14]MAIN[2][0][60]
CELL[3].OUT_BEL[2]CELL[0].IMUX_BUFG_O[13]MAIN[2][2][44]
CELL[3].OUT_BEL[3]CELL[0].IMUX_BUFG_O[12]MAIN[2][0][44]
CELL[3].OUT_BEL[4]CELL[0].IMUX_BUFG_O[19]MAIN[3][2][28]
CELL[3].OUT_BEL[5]CELL[0].IMUX_BUFG_O[18]MAIN[3][0][28]
CELL[3].OUT_BEL[6]CELL[0].IMUX_BUFG_O[17]MAIN[3][2][12]
CELL[3].OUT_BEL[7]CELL[0].IMUX_BUFG_O[16]MAIN[3][0][12]
CELL[3].OUT_BEL[8]CELL[0].IMUX_BUFG_O[23]MAIN[3][2][60]
CELL[3].OUT_BEL[9]CELL[0].IMUX_BUFG_O[22]MAIN[3][0][60]
CELL[3].OUT_BEL[10]CELL[0].IMUX_BUFG_O[21]MAIN[3][2][44]
CELL[3].OUT_BEL[11]CELL[0].IMUX_BUFG_O[20]MAIN[3][0][44]
CELL[4].OUT_BEL[0]CELL[0].IMUX_BUFG_O[27]MAIN[4][2][28]
CELL[4].OUT_BEL[1]CELL[0].IMUX_BUFG_O[26]MAIN[4][0][28]
CELL[4].OUT_BEL[2]CELL[0].IMUX_BUFG_O[25]MAIN[4][2][12]
CELL[4].OUT_BEL[3]CELL[0].IMUX_BUFG_O[24]MAIN[4][0][12]
CELL[4].OUT_BEL[4]CELL[0].IMUX_BUFG_O[31]MAIN[4][2][60]
CELL[4].OUT_BEL[5]CELL[0].IMUX_BUFG_O[30]MAIN[4][0][60]
CELL[4].OUT_BEL[6]CELL[0].IMUX_BUFG_O[29]MAIN[4][2][44]
CELL[4].OUT_BEL[7]CELL[0].IMUX_BUFG_O[28]MAIN[4][0][44]
CELL[10].MGT_BUF[0]CELL[10].MGT_ROW_I[0]MAIN[18][1][63]
CELL[10].MGT_BUF[1]CELL[10].MGT_ROW_I[1]MAIN[18][0][63]
CELL[10].MGT_BUF[2]CELL[10].MGT_ROW_I[2]MAIN[18][0][62]
CELL[10].MGT_BUF[3]CELL[10].MGT_ROW_I[3]MAIN[18][1][62]
CELL[10].MGT_BUF[4]CELL[10].MGT_ROW_I[4]MAIN[18][1][61]
CELL[10].MGT_BUF[5]CELL_E10.MGT_ROW_I[0]MAIN[18][3][63]
CELL[10].MGT_BUF[6]CELL_E10.MGT_ROW_I[1]MAIN[18][2][63]
CELL[10].MGT_BUF[7]CELL_E10.MGT_ROW_I[2]MAIN[18][2][62]
CELL[10].MGT_BUF[8]CELL_E10.MGT_ROW_I[3]MAIN[18][3][62]
CELL[10].MGT_BUF[9]CELL_E10.MGT_ROW_I[4]MAIN[18][3][61]
CELL[15].OUT_BEL[0]CELL[10].IMUX_BUFG_O[29]MAIN[15][2][19]
CELL[15].OUT_BEL[1]CELL[10].IMUX_BUFG_O[28]MAIN[15][0][19]
CELL[15].OUT_BEL[2]CELL[10].IMUX_BUFG_O[31]MAIN[15][2][3]
CELL[15].OUT_BEL[3]CELL[10].IMUX_BUFG_O[30]MAIN[15][0][3]
CELL[15].OUT_BEL[4]CELL[10].IMUX_BUFG_O[25]MAIN[15][2][51]
CELL[15].OUT_BEL[5]CELL[10].IMUX_BUFG_O[24]MAIN[15][0][51]
CELL[15].OUT_BEL[6]CELL[10].IMUX_BUFG_O[27]MAIN[15][2][35]
CELL[15].OUT_BEL[7]CELL[10].IMUX_BUFG_O[26]MAIN[15][0][35]
CELL[15].OUT_BEL[8]CELL[10].IMUX_BUFG_O[21]MAIN[16][2][19]
CELL[15].OUT_BEL[9]CELL[10].IMUX_BUFG_O[20]MAIN[16][0][19]
CELL[15].OUT_BEL[10]CELL[10].IMUX_BUFG_O[23]MAIN[16][2][3]
CELL[15].OUT_BEL[11]CELL[10].IMUX_BUFG_O[22]MAIN[16][0][3]
CELL[16].OUT_BEL[0]CELL[10].IMUX_BUFG_O[17]MAIN[16][2][51]
CELL[16].OUT_BEL[1]CELL[10].IMUX_BUFG_O[16]MAIN[16][0][51]
CELL[16].OUT_BEL[2]CELL[10].IMUX_BUFG_O[19]MAIN[16][2][35]
CELL[16].OUT_BEL[3]CELL[10].IMUX_BUFG_O[18]MAIN[16][0][35]
CELL[16].OUT_BEL[4]CELL[10].IMUX_BUFG_O[13]MAIN[17][2][19]
CELL[16].OUT_BEL[5]CELL[10].IMUX_BUFG_O[12]MAIN[17][0][19]
CELL[16].OUT_BEL[6]CELL[10].IMUX_BUFG_O[15]MAIN[17][2][3]
CELL[16].OUT_BEL[7]CELL[10].IMUX_BUFG_O[14]MAIN[17][0][3]
CELL[16].OUT_BEL[8]CELL[10].IMUX_BUFG_O[9]MAIN[17][2][51]
CELL[16].OUT_BEL[9]CELL[10].IMUX_BUFG_O[8]MAIN[17][0][51]
CELL[16].OUT_BEL[10]CELL[10].IMUX_BUFG_O[11]MAIN[17][2][35]
CELL[16].OUT_BEL[11]CELL[10].IMUX_BUFG_O[10]MAIN[17][0][35]
CELL[17].OUT_BEL[0]CELL[10].IMUX_BUFG_O[5]MAIN[18][2][19]
CELL[17].OUT_BEL[1]CELL[10].IMUX_BUFG_O[4]MAIN[18][0][19]
CELL[17].OUT_BEL[2]CELL[10].IMUX_BUFG_O[7]MAIN[18][2][3]
CELL[17].OUT_BEL[3]CELL[10].IMUX_BUFG_O[6]MAIN[18][0][3]
CELL[17].OUT_BEL[4]CELL[10].IMUX_BUFG_O[1]MAIN[18][2][51]
CELL[17].OUT_BEL[5]CELL[10].IMUX_BUFG_O[0]MAIN[18][0][51]
CELL[17].OUT_BEL[6]CELL[10].IMUX_BUFG_O[3]MAIN[18][2][35]
CELL[17].OUT_BEL[7]CELL[10].IMUX_BUFG_O[2]MAIN[18][0][35]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[0]
BitsDestination
MAIN[1][0][2]MAIN[1][0][3]MAIN[1][1][3]MAIN[1][1][4]MAIN[1][0][5]MAIN[1][1][6]MAIN[1][0][7]MAIN[1][1][8]MAIN[1][1][9]MAIN[1][0][9]MAIN[1][0][13]MAIN[1][1][10]MAIN[1][0][8]CELL[0].IMUX_BUFG_O[0]-
MAIN[18][0][61]MAIN[18][0][60]MAIN[18][1][60]MAIN[18][1][59]MAIN[18][0][58]MAIN[18][1][57]MAIN[18][0][56]MAIN[18][1][55]MAIN[18][1][54]MAIN[18][0][54]MAIN[18][0][50]MAIN[18][1][53]MAIN[18][0][55]-CELL[10].IMUX_BUFG_O[0]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[0]CELL[10].IMUX_BUFG_I[0]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[15]CELL[17].IMUX_IMUX[47]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[3]CELL[17].IMUX_IMUX[23]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[1]
BitsDestination
MAIN[1][2][2]MAIN[1][2][3]MAIN[1][3][3]MAIN[1][3][4]MAIN[1][2][5]MAIN[1][3][6]MAIN[1][2][7]MAIN[1][3][8]MAIN[1][3][9]MAIN[1][2][9]MAIN[1][2][13]MAIN[1][3][10]MAIN[1][2][8]CELL[0].IMUX_BUFG_O[1]-
MAIN[18][2][61]MAIN[18][2][60]MAIN[18][3][60]MAIN[18][3][59]MAIN[18][2][58]MAIN[18][3][57]MAIN[18][2][56]MAIN[18][3][55]MAIN[18][3][54]MAIN[18][2][54]MAIN[18][2][50]MAIN[18][3][53]MAIN[18][2][55]-CELL[10].IMUX_BUFG_O[1]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[1]CELL[10].IMUX_BUFG_I[1]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[15]CELL[17].IMUX_IMUX[47]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[3]CELL[17].IMUX_IMUX[23]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[2]
BitsDestination
MAIN[1][0][18]MAIN[1][0][19]MAIN[1][1][19]MAIN[1][1][20]MAIN[1][0][21]MAIN[1][1][22]MAIN[1][0][23]MAIN[1][1][24]MAIN[1][1][25]MAIN[1][0][25]MAIN[1][0][29]MAIN[1][1][26]MAIN[1][0][24]CELL[0].IMUX_BUFG_O[2]-
MAIN[18][0][45]MAIN[18][0][44]MAIN[18][1][44]MAIN[18][1][43]MAIN[18][0][42]MAIN[18][1][41]MAIN[18][0][40]MAIN[18][1][39]MAIN[18][1][38]MAIN[18][0][38]MAIN[18][0][34]MAIN[18][1][37]MAIN[18][0][39]-CELL[10].IMUX_BUFG_O[2]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[2]CELL[10].IMUX_BUFG_I[2]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[21]CELL[17].IMUX_IMUX[35]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[9]CELL[17].IMUX_IMUX[11]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[3]
BitsDestination
MAIN[1][2][18]MAIN[1][2][19]MAIN[1][3][19]MAIN[1][3][20]MAIN[1][2][21]MAIN[1][3][22]MAIN[1][2][23]MAIN[1][3][24]MAIN[1][3][25]MAIN[1][2][25]MAIN[1][2][29]MAIN[1][3][26]MAIN[1][2][24]CELL[0].IMUX_BUFG_O[3]-
MAIN[18][2][45]MAIN[18][2][44]MAIN[18][3][44]MAIN[18][3][43]MAIN[18][2][42]MAIN[18][3][41]MAIN[18][2][40]MAIN[18][3][39]MAIN[18][3][38]MAIN[18][2][38]MAIN[18][2][34]MAIN[18][3][37]MAIN[18][2][39]-CELL[10].IMUX_BUFG_O[3]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[3]CELL[10].IMUX_BUFG_I[3]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[21]CELL[17].IMUX_IMUX[35]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[9]CELL[17].IMUX_IMUX[11]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[4]
BitsDestination
MAIN[1][0][34]MAIN[1][0][35]MAIN[1][1][35]MAIN[1][1][36]MAIN[1][0][37]MAIN[1][1][38]MAIN[1][0][39]MAIN[1][1][40]MAIN[1][1][41]MAIN[1][0][41]MAIN[1][0][45]MAIN[1][1][42]MAIN[1][0][40]CELL[0].IMUX_BUFG_O[4]-
MAIN[18][0][29]MAIN[18][0][28]MAIN[18][1][28]MAIN[18][1][27]MAIN[18][0][26]MAIN[18][1][25]MAIN[18][0][24]MAIN[18][1][23]MAIN[18][1][22]MAIN[18][0][22]MAIN[18][0][18]MAIN[18][1][21]MAIN[18][0][23]-CELL[10].IMUX_BUFG_O[4]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[4]CELL[10].IMUX_BUFG_I[4]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[39]CELL[16].IMUX_IMUX[47]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[27]CELL[16].IMUX_IMUX[23]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[5]
BitsDestination
MAIN[1][2][34]MAIN[1][2][35]MAIN[1][3][35]MAIN[1][3][36]MAIN[1][2][37]MAIN[1][3][38]MAIN[1][2][39]MAIN[1][3][40]MAIN[1][3][41]MAIN[1][2][41]MAIN[1][2][45]MAIN[1][3][42]MAIN[1][2][40]CELL[0].IMUX_BUFG_O[5]-
MAIN[18][2][29]MAIN[18][2][28]MAIN[18][3][28]MAIN[18][3][27]MAIN[18][2][26]MAIN[18][3][25]MAIN[18][2][24]MAIN[18][3][23]MAIN[18][3][22]MAIN[18][2][22]MAIN[18][2][18]MAIN[18][3][21]MAIN[18][2][23]-CELL[10].IMUX_BUFG_O[5]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[5]CELL[10].IMUX_BUFG_I[5]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[39]CELL[16].IMUX_IMUX[47]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[27]CELL[16].IMUX_IMUX[23]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[6]
BitsDestination
MAIN[1][0][50]MAIN[1][0][51]MAIN[1][1][51]MAIN[1][1][52]MAIN[1][0][53]MAIN[1][1][54]MAIN[1][0][55]MAIN[1][1][56]MAIN[1][1][57]MAIN[1][0][57]MAIN[1][0][61]MAIN[1][1][58]MAIN[1][0][56]CELL[0].IMUX_BUFG_O[6]-
MAIN[18][0][13]MAIN[18][0][12]MAIN[18][1][12]MAIN[18][1][11]MAIN[18][0][10]MAIN[18][1][9]MAIN[18][0][8]MAIN[18][1][7]MAIN[18][1][6]MAIN[18][0][6]MAIN[18][0][2]MAIN[18][1][5]MAIN[18][0][7]-CELL[10].IMUX_BUFG_O[6]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[6]CELL[10].IMUX_BUFG_I[6]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[45]CELL[16].IMUX_IMUX[35]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[33]CELL[16].IMUX_IMUX[11]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[7]
BitsDestination
MAIN[1][2][50]MAIN[1][2][51]MAIN[1][3][51]MAIN[1][3][52]MAIN[1][2][53]MAIN[1][3][54]MAIN[1][2][55]MAIN[1][3][56]MAIN[1][3][57]MAIN[1][2][57]MAIN[1][2][61]MAIN[1][3][58]MAIN[1][2][56]CELL[0].IMUX_BUFG_O[7]-
MAIN[18][2][13]MAIN[18][2][12]MAIN[18][3][12]MAIN[18][3][11]MAIN[18][2][10]MAIN[18][3][9]MAIN[18][2][8]MAIN[18][3][7]MAIN[18][3][6]MAIN[18][2][6]MAIN[18][2][2]MAIN[18][3][5]MAIN[18][2][7]-CELL[10].IMUX_BUFG_O[7]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[7]CELL[10].IMUX_BUFG_I[7]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[2].IMUX_IMUX[45]CELL[16].IMUX_IMUX[35]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[2].IMUX_IMUX[33]CELL[16].IMUX_IMUX[11]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[8]
BitsDestination
MAIN[2][0][2]MAIN[2][0][3]MAIN[2][1][3]MAIN[2][1][4]MAIN[2][0][5]MAIN[2][1][6]MAIN[2][0][7]MAIN[2][1][8]MAIN[2][1][9]MAIN[2][0][9]MAIN[2][0][13]MAIN[2][1][10]MAIN[2][0][8]CELL[0].IMUX_BUFG_O[8]-
MAIN[17][0][61]MAIN[17][0][60]MAIN[17][1][60]MAIN[17][1][59]MAIN[17][0][58]MAIN[17][1][57]MAIN[17][0][56]MAIN[17][1][55]MAIN[17][1][54]MAIN[17][0][54]MAIN[17][0][50]MAIN[17][1][53]MAIN[17][0][55]-CELL[10].IMUX_BUFG_O[8]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[8]CELL[10].IMUX_BUFG_I[8]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[15]CELL[17].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[3]CELL[17].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[9]
BitsDestination
MAIN[2][2][2]MAIN[2][2][3]MAIN[2][3][3]MAIN[2][3][4]MAIN[2][2][5]MAIN[2][3][6]MAIN[2][2][7]MAIN[2][3][8]MAIN[2][3][9]MAIN[2][2][9]MAIN[2][2][13]MAIN[2][3][10]MAIN[2][2][8]CELL[0].IMUX_BUFG_O[9]-
MAIN[17][2][61]MAIN[17][2][60]MAIN[17][3][60]MAIN[17][3][59]MAIN[17][2][58]MAIN[17][3][57]MAIN[17][2][56]MAIN[17][3][55]MAIN[17][3][54]MAIN[17][2][54]MAIN[17][2][50]MAIN[17][3][53]MAIN[17][2][55]-CELL[10].IMUX_BUFG_O[9]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[9]CELL[10].IMUX_BUFG_I[9]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[15]CELL[17].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[3]CELL[17].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[10]
BitsDestination
MAIN[2][0][18]MAIN[2][0][19]MAIN[2][1][19]MAIN[2][1][20]MAIN[2][0][21]MAIN[2][1][22]MAIN[2][0][23]MAIN[2][1][24]MAIN[2][1][25]MAIN[2][0][25]MAIN[2][0][29]MAIN[2][1][26]MAIN[2][0][24]CELL[0].IMUX_BUFG_O[10]-
MAIN[17][0][45]MAIN[17][0][44]MAIN[17][1][44]MAIN[17][1][43]MAIN[17][0][42]MAIN[17][1][41]MAIN[17][0][40]MAIN[17][1][39]MAIN[17][1][38]MAIN[17][0][38]MAIN[17][0][34]MAIN[17][1][37]MAIN[17][0][39]-CELL[10].IMUX_BUFG_O[10]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[10]CELL[10].IMUX_BUFG_I[10]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[21]CELL[17].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[9]CELL[17].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[11]
BitsDestination
MAIN[2][2][18]MAIN[2][2][19]MAIN[2][3][19]MAIN[2][3][20]MAIN[2][2][21]MAIN[2][3][22]MAIN[2][2][23]MAIN[2][3][24]MAIN[2][3][25]MAIN[2][2][25]MAIN[2][2][29]MAIN[2][3][26]MAIN[2][2][24]CELL[0].IMUX_BUFG_O[11]-
MAIN[17][2][45]MAIN[17][2][44]MAIN[17][3][44]MAIN[17][3][43]MAIN[17][2][42]MAIN[17][3][41]MAIN[17][2][40]MAIN[17][3][39]MAIN[17][3][38]MAIN[17][2][38]MAIN[17][2][34]MAIN[17][3][37]MAIN[17][2][39]-CELL[10].IMUX_BUFG_O[11]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[11]CELL[10].IMUX_BUFG_I[11]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[21]CELL[17].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[9]CELL[17].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[12]
BitsDestination
MAIN[2][0][34]MAIN[2][0][35]MAIN[2][1][35]MAIN[2][1][36]MAIN[2][0][37]MAIN[2][1][38]MAIN[2][0][39]MAIN[2][1][40]MAIN[2][1][41]MAIN[2][0][41]MAIN[2][0][45]MAIN[2][1][42]MAIN[2][0][40]CELL[0].IMUX_BUFG_O[12]-
MAIN[17][0][29]MAIN[17][0][28]MAIN[17][1][28]MAIN[17][1][27]MAIN[17][0][26]MAIN[17][1][25]MAIN[17][0][24]MAIN[17][1][23]MAIN[17][1][22]MAIN[17][0][22]MAIN[17][0][18]MAIN[17][1][21]MAIN[17][0][23]-CELL[10].IMUX_BUFG_O[12]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[12]CELL[10].IMUX_BUFG_I[12]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[39]CELL[17].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[27]CELL[17].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[13]
BitsDestination
MAIN[2][2][34]MAIN[2][2][35]MAIN[2][3][35]MAIN[2][3][36]MAIN[2][2][37]MAIN[2][3][38]MAIN[2][2][39]MAIN[2][3][40]MAIN[2][3][41]MAIN[2][2][41]MAIN[2][2][45]MAIN[2][3][42]MAIN[2][2][40]CELL[0].IMUX_BUFG_O[13]-
MAIN[17][2][29]MAIN[17][2][28]MAIN[17][3][28]MAIN[17][3][27]MAIN[17][2][26]MAIN[17][3][25]MAIN[17][2][24]MAIN[17][3][23]MAIN[17][3][22]MAIN[17][2][22]MAIN[17][2][18]MAIN[17][3][21]MAIN[17][2][23]-CELL[10].IMUX_BUFG_O[13]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[13]CELL[10].IMUX_BUFG_I[13]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[39]CELL[17].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[27]CELL[17].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[14]
BitsDestination
MAIN[2][0][50]MAIN[2][0][51]MAIN[2][1][51]MAIN[2][1][52]MAIN[2][0][53]MAIN[2][1][54]MAIN[2][0][55]MAIN[2][1][56]MAIN[2][1][57]MAIN[2][0][57]MAIN[2][0][61]MAIN[2][1][58]MAIN[2][0][56]CELL[0].IMUX_BUFG_O[14]-
MAIN[17][0][13]MAIN[17][0][12]MAIN[17][1][12]MAIN[17][1][11]MAIN[17][0][10]MAIN[17][1][9]MAIN[17][0][8]MAIN[17][1][7]MAIN[17][1][6]MAIN[17][0][6]MAIN[17][0][2]MAIN[17][1][5]MAIN[17][0][7]-CELL[10].IMUX_BUFG_O[14]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[14]CELL[10].IMUX_BUFG_I[14]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[45]CELL[17].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[33]CELL[17].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[15]
BitsDestination
MAIN[2][2][50]MAIN[2][2][51]MAIN[2][3][51]MAIN[2][3][52]MAIN[2][2][53]MAIN[2][3][54]MAIN[2][2][55]MAIN[2][3][56]MAIN[2][3][57]MAIN[2][2][57]MAIN[2][2][61]MAIN[2][3][58]MAIN[2][2][56]CELL[0].IMUX_BUFG_O[15]-
MAIN[17][2][13]MAIN[17][2][12]MAIN[17][3][12]MAIN[17][3][11]MAIN[17][2][10]MAIN[17][3][9]MAIN[17][2][8]MAIN[17][3][7]MAIN[17][3][6]MAIN[17][2][6]MAIN[17][2][2]MAIN[17][3][5]MAIN[17][2][7]-CELL[10].IMUX_BUFG_O[15]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[15]CELL[10].IMUX_BUFG_I[15]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[45]CELL[17].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[33]CELL[17].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[16]
BitsDestination
MAIN[3][0][2]MAIN[3][0][3]MAIN[3][1][3]MAIN[3][1][4]MAIN[3][0][5]MAIN[3][1][6]MAIN[3][0][7]MAIN[3][1][8]MAIN[3][1][9]MAIN[3][0][9]MAIN[3][0][13]MAIN[3][1][10]MAIN[3][0][8]CELL[0].IMUX_BUFG_O[16]-
MAIN[16][0][61]MAIN[16][0][60]MAIN[16][1][60]MAIN[16][1][59]MAIN[16][0][58]MAIN[16][1][57]MAIN[16][0][56]MAIN[16][1][55]MAIN[16][1][54]MAIN[16][0][54]MAIN[16][0][50]MAIN[16][1][53]MAIN[16][0][55]-CELL[10].IMUX_BUFG_O[16]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[16]CELL[10].IMUX_BUFG_I[16]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[15]CELL[16].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[3]CELL[16].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[17]
BitsDestination
MAIN[3][2][2]MAIN[3][2][3]MAIN[3][3][3]MAIN[3][3][4]MAIN[3][2][5]MAIN[3][3][6]MAIN[3][2][7]MAIN[3][3][8]MAIN[3][3][9]MAIN[3][2][9]MAIN[3][2][13]MAIN[3][3][10]MAIN[3][2][8]CELL[0].IMUX_BUFG_O[17]-
MAIN[16][2][61]MAIN[16][2][60]MAIN[16][3][60]MAIN[16][3][59]MAIN[16][2][58]MAIN[16][3][57]MAIN[16][2][56]MAIN[16][3][55]MAIN[16][3][54]MAIN[16][2][54]MAIN[16][2][50]MAIN[16][3][53]MAIN[16][2][55]-CELL[10].IMUX_BUFG_O[17]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[17]CELL[10].IMUX_BUFG_I[17]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[15]CELL[16].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[3]CELL[16].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[18]
BitsDestination
MAIN[3][0][18]MAIN[3][0][19]MAIN[3][1][19]MAIN[3][1][20]MAIN[3][0][21]MAIN[3][1][22]MAIN[3][0][23]MAIN[3][1][24]MAIN[3][1][25]MAIN[3][0][25]MAIN[3][0][29]MAIN[3][1][26]MAIN[3][0][24]CELL[0].IMUX_BUFG_O[18]-
MAIN[16][0][45]MAIN[16][0][44]MAIN[16][1][44]MAIN[16][1][43]MAIN[16][0][42]MAIN[16][1][41]MAIN[16][0][40]MAIN[16][1][39]MAIN[16][1][38]MAIN[16][0][38]MAIN[16][0][34]MAIN[16][1][37]MAIN[16][0][39]-CELL[10].IMUX_BUFG_O[18]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[18]CELL[10].IMUX_BUFG_I[18]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[21]CELL[16].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[9]CELL[16].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[19]
BitsDestination
MAIN[3][2][18]MAIN[3][2][19]MAIN[3][3][19]MAIN[3][3][20]MAIN[3][2][21]MAIN[3][3][22]MAIN[3][2][23]MAIN[3][3][24]MAIN[3][3][25]MAIN[3][2][25]MAIN[3][2][29]MAIN[3][3][26]MAIN[3][2][24]CELL[0].IMUX_BUFG_O[19]-
MAIN[16][2][45]MAIN[16][2][44]MAIN[16][3][44]MAIN[16][3][43]MAIN[16][2][42]MAIN[16][3][41]MAIN[16][2][40]MAIN[16][3][39]MAIN[16][3][38]MAIN[16][2][38]MAIN[16][2][34]MAIN[16][3][37]MAIN[16][2][39]-CELL[10].IMUX_BUFG_O[19]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[19]CELL[10].IMUX_BUFG_I[19]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[21]CELL[16].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[9]CELL[16].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[20]
BitsDestination
MAIN[3][0][34]MAIN[3][0][35]MAIN[3][1][35]MAIN[3][1][36]MAIN[3][0][37]MAIN[3][1][38]MAIN[3][0][39]MAIN[3][1][40]MAIN[3][1][41]MAIN[3][0][41]MAIN[3][0][45]MAIN[3][1][42]MAIN[3][0][40]CELL[0].IMUX_BUFG_O[20]-
MAIN[16][0][29]MAIN[16][0][28]MAIN[16][1][28]MAIN[16][1][27]MAIN[16][0][26]MAIN[16][1][25]MAIN[16][0][24]MAIN[16][1][23]MAIN[16][1][22]MAIN[16][0][22]MAIN[16][0][18]MAIN[16][1][21]MAIN[16][0][23]-CELL[10].IMUX_BUFG_O[20]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[20]CELL[10].IMUX_BUFG_I[20]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[39]CELL[16].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[27]CELL[16].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[21]
BitsDestination
MAIN[3][2][34]MAIN[3][2][35]MAIN[3][3][35]MAIN[3][3][36]MAIN[3][2][37]MAIN[3][3][38]MAIN[3][2][39]MAIN[3][3][40]MAIN[3][3][41]MAIN[3][2][41]MAIN[3][2][45]MAIN[3][3][42]MAIN[3][2][40]CELL[0].IMUX_BUFG_O[21]-
MAIN[16][2][29]MAIN[16][2][28]MAIN[16][3][28]MAIN[16][3][27]MAIN[16][2][26]MAIN[16][3][25]MAIN[16][2][24]MAIN[16][3][23]MAIN[16][3][22]MAIN[16][2][22]MAIN[16][2][18]MAIN[16][3][21]MAIN[16][2][23]-CELL[10].IMUX_BUFG_O[21]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[21]CELL[10].IMUX_BUFG_I[21]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[39]CELL[16].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[27]CELL[16].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[22]
BitsDestination
MAIN[3][0][50]MAIN[3][0][51]MAIN[3][1][51]MAIN[3][1][52]MAIN[3][0][53]MAIN[3][1][54]MAIN[3][0][55]MAIN[3][1][56]MAIN[3][1][57]MAIN[3][0][57]MAIN[3][0][61]MAIN[3][1][58]MAIN[3][0][56]CELL[0].IMUX_BUFG_O[22]-
MAIN[16][0][13]MAIN[16][0][12]MAIN[16][1][12]MAIN[16][1][11]MAIN[16][0][10]MAIN[16][1][9]MAIN[16][0][8]MAIN[16][1][7]MAIN[16][1][6]MAIN[16][0][6]MAIN[16][0][2]MAIN[16][1][5]MAIN[16][0][7]-CELL[10].IMUX_BUFG_O[22]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[22]CELL[10].IMUX_BUFG_I[22]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[45]CELL[16].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[33]CELL[16].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[23]
BitsDestination
MAIN[3][2][50]MAIN[3][2][51]MAIN[3][3][51]MAIN[3][3][52]MAIN[3][2][53]MAIN[3][3][54]MAIN[3][2][55]MAIN[3][3][56]MAIN[3][3][57]MAIN[3][2][57]MAIN[3][2][61]MAIN[3][3][58]MAIN[3][2][56]CELL[0].IMUX_BUFG_O[23]-
MAIN[16][2][13]MAIN[16][2][12]MAIN[16][3][12]MAIN[16][3][11]MAIN[16][2][10]MAIN[16][3][9]MAIN[16][2][8]MAIN[16][3][7]MAIN[16][3][6]MAIN[16][2][6]MAIN[16][2][2]MAIN[16][3][5]MAIN[16][2][7]-CELL[10].IMUX_BUFG_O[23]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[23]CELL[10].IMUX_BUFG_I[23]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[45]CELL[16].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[33]CELL[16].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[24]
BitsDestination
MAIN[4][0][2]MAIN[4][0][3]MAIN[4][1][3]MAIN[4][1][4]MAIN[4][0][5]MAIN[4][1][6]MAIN[4][0][7]MAIN[4][1][8]MAIN[4][1][9]MAIN[4][0][9]MAIN[4][0][13]MAIN[4][1][10]MAIN[4][0][8]CELL[0].IMUX_BUFG_O[24]-
MAIN[15][0][61]MAIN[15][0][60]MAIN[15][1][60]MAIN[15][1][59]MAIN[15][0][58]MAIN[15][1][57]MAIN[15][0][56]MAIN[15][1][55]MAIN[15][1][54]MAIN[15][0][54]MAIN[15][0][50]MAIN[15][1][53]MAIN[15][0][55]-CELL[10].IMUX_BUFG_O[24]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[24]CELL[10].IMUX_BUFG_I[24]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[35]CELL[15].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[11]CELL[15].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[25]
BitsDestination
MAIN[4][2][2]MAIN[4][2][3]MAIN[4][3][3]MAIN[4][3][4]MAIN[4][2][5]MAIN[4][3][6]MAIN[4][2][7]MAIN[4][3][8]MAIN[4][3][9]MAIN[4][2][9]MAIN[4][2][13]MAIN[4][3][10]MAIN[4][2][8]CELL[0].IMUX_BUFG_O[25]-
MAIN[15][2][61]MAIN[15][2][60]MAIN[15][3][60]MAIN[15][3][59]MAIN[15][2][58]MAIN[15][3][57]MAIN[15][2][56]MAIN[15][3][55]MAIN[15][3][54]MAIN[15][2][54]MAIN[15][2][50]MAIN[15][3][53]MAIN[15][2][55]-CELL[10].IMUX_BUFG_O[25]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[25]CELL[10].IMUX_BUFG_I[25]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[35]CELL[15].IMUX_IMUX[45]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[11]CELL[15].IMUX_IMUX[33]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[26]
BitsDestination
MAIN[4][0][18]MAIN[4][0][19]MAIN[4][1][19]MAIN[4][1][20]MAIN[4][0][21]MAIN[4][1][22]MAIN[4][0][23]MAIN[4][1][24]MAIN[4][1][25]MAIN[4][0][25]MAIN[4][0][29]MAIN[4][1][26]MAIN[4][0][24]CELL[0].IMUX_BUFG_O[26]-
MAIN[15][0][45]MAIN[15][0][44]MAIN[15][1][44]MAIN[15][1][43]MAIN[15][0][42]MAIN[15][1][41]MAIN[15][0][40]MAIN[15][1][39]MAIN[15][1][38]MAIN[15][0][38]MAIN[15][0][34]MAIN[15][1][37]MAIN[15][0][39]-CELL[10].IMUX_BUFG_O[26]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[26]CELL[10].IMUX_BUFG_I[26]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[47]CELL[15].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[23]CELL[15].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[27]
BitsDestination
MAIN[4][2][18]MAIN[4][2][19]MAIN[4][3][19]MAIN[4][3][20]MAIN[4][2][21]MAIN[4][3][22]MAIN[4][2][23]MAIN[4][3][24]MAIN[4][3][25]MAIN[4][2][25]MAIN[4][2][29]MAIN[4][3][26]MAIN[4][2][24]CELL[0].IMUX_BUFG_O[27]-
MAIN[15][2][45]MAIN[15][2][44]MAIN[15][3][44]MAIN[15][3][43]MAIN[15][2][42]MAIN[15][3][41]MAIN[15][2][40]MAIN[15][3][39]MAIN[15][3][38]MAIN[15][2][38]MAIN[15][2][34]MAIN[15][3][37]MAIN[15][2][39]-CELL[10].IMUX_BUFG_O[27]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[27]CELL[10].IMUX_BUFG_I[27]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[3].IMUX_IMUX[47]CELL[15].IMUX_IMUX[39]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[3].IMUX_IMUX[23]CELL[15].IMUX_IMUX[27]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[28]
BitsDestination
MAIN[4][0][34]MAIN[4][0][35]MAIN[4][1][35]MAIN[4][1][36]MAIN[4][0][37]MAIN[4][1][38]MAIN[4][0][39]MAIN[4][1][40]MAIN[4][1][41]MAIN[4][0][41]MAIN[4][0][45]MAIN[4][1][42]MAIN[4][0][40]CELL[0].IMUX_BUFG_O[28]-
MAIN[15][0][29]MAIN[15][0][28]MAIN[15][1][28]MAIN[15][1][27]MAIN[15][0][26]MAIN[15][1][25]MAIN[15][0][24]MAIN[15][1][23]MAIN[15][1][22]MAIN[15][0][22]MAIN[15][0][18]MAIN[15][1][21]MAIN[15][0][23]-CELL[10].IMUX_BUFG_O[28]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[28]CELL[10].IMUX_BUFG_I[28]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[35]CELL[15].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[11]CELL[15].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[29]
BitsDestination
MAIN[4][2][34]MAIN[4][2][35]MAIN[4][3][35]MAIN[4][3][36]MAIN[4][2][37]MAIN[4][3][38]MAIN[4][2][39]MAIN[4][3][40]MAIN[4][3][41]MAIN[4][2][41]MAIN[4][2][45]MAIN[4][3][42]MAIN[4][2][40]CELL[0].IMUX_BUFG_O[29]-
MAIN[15][2][29]MAIN[15][2][28]MAIN[15][3][28]MAIN[15][3][27]MAIN[15][2][26]MAIN[15][3][25]MAIN[15][2][24]MAIN[15][3][23]MAIN[15][3][22]MAIN[15][2][22]MAIN[15][2][18]MAIN[15][3][21]MAIN[15][2][23]-CELL[10].IMUX_BUFG_O[29]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[29]CELL[10].IMUX_BUFG_I[29]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[35]CELL[15].IMUX_IMUX[21]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[11]CELL[15].IMUX_IMUX[9]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[30]
BitsDestination
MAIN[4][0][50]MAIN[4][0][51]MAIN[4][1][51]MAIN[4][1][52]MAIN[4][0][53]MAIN[4][1][54]MAIN[4][0][55]MAIN[4][1][56]MAIN[4][1][57]MAIN[4][0][57]MAIN[4][0][61]MAIN[4][1][58]MAIN[4][0][56]CELL[0].IMUX_BUFG_O[30]-
MAIN[15][0][13]MAIN[15][0][12]MAIN[15][1][12]MAIN[15][1][11]MAIN[15][0][10]MAIN[15][1][9]MAIN[15][0][8]MAIN[15][1][7]MAIN[15][1][6]MAIN[15][0][6]MAIN[15][0][2]MAIN[15][1][5]MAIN[15][0][7]-CELL[10].IMUX_BUFG_O[30]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[30]CELL[10].IMUX_BUFG_I[30]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[47]CELL[15].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[23]CELL[15].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]
virtex5 CLK_BUFG switchbox SPEC_INT muxes IMUX_BUFG_O[31]
BitsDestination
MAIN[4][2][50]MAIN[4][2][51]MAIN[4][3][51]MAIN[4][3][52]MAIN[4][2][53]MAIN[4][3][54]MAIN[4][2][55]MAIN[4][3][56]MAIN[4][3][57]MAIN[4][2][57]MAIN[4][2][61]MAIN[4][3][58]MAIN[4][2][56]CELL[0].IMUX_BUFG_O[31]-
MAIN[15][2][13]MAIN[15][2][12]MAIN[15][3][12]MAIN[15][3][11]MAIN[15][2][10]MAIN[15][3][9]MAIN[15][2][8]MAIN[15][3][7]MAIN[15][3][6]MAIN[15][2][6]MAIN[15][2][2]MAIN[15][3][5]MAIN[15][2][7]-CELL[10].IMUX_BUFG_O[31]
Source
0000000000000offoff
0000000000100CELL[0].IMUX_BUFG_I[31]CELL[10].IMUX_BUFG_I[31]
0000000100001CELL[0].OUT_BUFG[0]CELL[0].OUT_BUFG[16]
0000000100010CELL[0].OUT_BUFG[8]CELL[0].OUT_BUFG[24]
0000000101000CELL[0].MGT_BUF[0]CELL[10].MGT_BUF[0]
0000001000001CELL[0].OUT_BUFG[1]CELL[0].OUT_BUFG[17]
0000001000010CELL[0].OUT_BUFG[9]CELL[0].OUT_BUFG[25]
0000001001000CELL[0].MGT_BUF[1]CELL[10].MGT_BUF[1]
0000001010000CELL[4].IMUX_IMUX[47]CELL[15].IMUX_IMUX[15]
0000010000001CELL[0].OUT_BUFG[2]CELL[0].OUT_BUFG[18]
0000010000010CELL[0].OUT_BUFG[10]CELL[0].OUT_BUFG[26]
0000010001000CELL[0].MGT_BUF[2]CELL[10].MGT_BUF[2]
0000010010000CELL[4].IMUX_IMUX[23]CELL[15].IMUX_IMUX[3]
0000100000001CELL[0].OUT_BUFG[3]CELL[0].OUT_BUFG[19]
0000100000010CELL[0].OUT_BUFG[11]CELL[0].OUT_BUFG[27]
0000100001000CELL[0].MGT_BUF[3]CELL[10].MGT_BUF[3]
0000100010000CELL[0].MGT_BUF[5]CELL[10].MGT_BUF[5]
0001000000001CELL[0].OUT_BUFG[4]CELL[0].OUT_BUFG[20]
0001000000010CELL[0].OUT_BUFG[12]CELL[0].OUT_BUFG[28]
0001000001000CELL[0].MGT_BUF[4]CELL[10].MGT_BUF[4]
0001000010000CELL[0].MGT_BUF[6]CELL[10].MGT_BUF[6]
0010000000001CELL[0].OUT_BUFG[5]CELL[0].OUT_BUFG[21]
0010000000010CELL[0].OUT_BUFG[13]CELL[0].OUT_BUFG[29]
0010000010000CELL[0].MGT_BUF[7]CELL[10].MGT_BUF[7]
0100000000001CELL[0].OUT_BUFG[6]CELL[0].OUT_BUFG[22]
0100000000010CELL[0].OUT_BUFG[14]CELL[0].OUT_BUFG[30]
0100000010000CELL[0].MGT_BUF[8]CELL[10].MGT_BUF[8]
1000000000001CELL[0].OUT_BUFG[7]CELL[0].OUT_BUFG[23]
1000000000010CELL[0].OUT_BUFG[15]CELL[0].OUT_BUFG[31]
1000000010000CELL[0].MGT_BUF[9]CELL[10].MGT_BUF[9]

Bels BUFGCTRL

virtex5 CLK_BUFG bel BUFGCTRL pins
PinDirectionBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]BUFGCTRL[16]BUFGCTRL[17]BUFGCTRL[18]BUFGCTRL[19]BUFGCTRL[20]BUFGCTRL[21]BUFGCTRL[22]BUFGCTRL[23]BUFGCTRL[24]BUFGCTRL[25]BUFGCTRL[26]BUFGCTRL[27]BUFGCTRL[28]BUFGCTRL[29]BUFGCTRL[30]BUFGCTRL[31]
I0inCELL[0].IMUX_BUFG_O[0]CELL[0].IMUX_BUFG_O[2]CELL[0].IMUX_BUFG_O[4]CELL[0].IMUX_BUFG_O[6]CELL[0].IMUX_BUFG_O[8]CELL[0].IMUX_BUFG_O[10]CELL[0].IMUX_BUFG_O[12]CELL[0].IMUX_BUFG_O[14]CELL[0].IMUX_BUFG_O[16]CELL[0].IMUX_BUFG_O[18]CELL[0].IMUX_BUFG_O[20]CELL[0].IMUX_BUFG_O[22]CELL[0].IMUX_BUFG_O[24]CELL[0].IMUX_BUFG_O[26]CELL[0].IMUX_BUFG_O[28]CELL[0].IMUX_BUFG_O[30]CELL[10].IMUX_BUFG_O[0]CELL[10].IMUX_BUFG_O[2]CELL[10].IMUX_BUFG_O[4]CELL[10].IMUX_BUFG_O[6]CELL[10].IMUX_BUFG_O[8]CELL[10].IMUX_BUFG_O[10]CELL[10].IMUX_BUFG_O[12]CELL[10].IMUX_BUFG_O[14]CELL[10].IMUX_BUFG_O[16]CELL[10].IMUX_BUFG_O[18]CELL[10].IMUX_BUFG_O[20]CELL[10].IMUX_BUFG_O[22]CELL[10].IMUX_BUFG_O[24]CELL[10].IMUX_BUFG_O[26]CELL[10].IMUX_BUFG_O[28]CELL[10].IMUX_BUFG_O[30]
I1inCELL[0].IMUX_BUFG_O[1]CELL[0].IMUX_BUFG_O[3]CELL[0].IMUX_BUFG_O[5]CELL[0].IMUX_BUFG_O[7]CELL[0].IMUX_BUFG_O[9]CELL[0].IMUX_BUFG_O[11]CELL[0].IMUX_BUFG_O[13]CELL[0].IMUX_BUFG_O[15]CELL[0].IMUX_BUFG_O[17]CELL[0].IMUX_BUFG_O[19]CELL[0].IMUX_BUFG_O[21]CELL[0].IMUX_BUFG_O[23]CELL[0].IMUX_BUFG_O[25]CELL[0].IMUX_BUFG_O[27]CELL[0].IMUX_BUFG_O[29]CELL[0].IMUX_BUFG_O[31]CELL[10].IMUX_BUFG_O[1]CELL[10].IMUX_BUFG_O[3]CELL[10].IMUX_BUFG_O[5]CELL[10].IMUX_BUFG_O[7]CELL[10].IMUX_BUFG_O[9]CELL[10].IMUX_BUFG_O[11]CELL[10].IMUX_BUFG_O[13]CELL[10].IMUX_BUFG_O[15]CELL[10].IMUX_BUFG_O[17]CELL[10].IMUX_BUFG_O[19]CELL[10].IMUX_BUFG_O[21]CELL[10].IMUX_BUFG_O[23]CELL[10].IMUX_BUFG_O[25]CELL[10].IMUX_BUFG_O[27]CELL[10].IMUX_BUFG_O[29]CELL[10].IMUX_BUFG_O[31]
S0inCELL[2].IMUX_IMUX[0] invert by !MAIN[6][1][7]CELL[2].IMUX_IMUX[6] invert by !MAIN[6][3][7]CELL[2].IMUX_IMUX[24] invert by !MAIN[6][1][15]CELL[2].IMUX_IMUX[30] invert by !MAIN[6][3][15]CELL[3].IMUX_IMUX[0] invert by !MAIN[6][1][23]CELL[3].IMUX_IMUX[6] invert by !MAIN[6][3][23]CELL[3].IMUX_IMUX[24] invert by !MAIN[6][1][31]CELL[3].IMUX_IMUX[30] invert by !MAIN[6][3][31]CELL[4].IMUX_IMUX[0] invert by !MAIN[6][1][39]CELL[4].IMUX_IMUX[6] invert by !MAIN[6][3][39]CELL[4].IMUX_IMUX[24] invert by !MAIN[6][1][47]CELL[4].IMUX_IMUX[30] invert by !MAIN[6][3][47]CELL[3].IMUX_IMUX[4] invert by !MAIN[6][1][55]CELL[3].IMUX_IMUX[16] invert by !MAIN[6][3][55]CELL[4].IMUX_IMUX[4] invert by !MAIN[6][1][63]CELL[4].IMUX_IMUX[16] invert by !MAIN[6][3][63]CELL[17].IMUX_IMUX[16] invert by !MAIN[13][1][56]CELL[17].IMUX_IMUX[4] invert by !MAIN[13][3][56]CELL[16].IMUX_IMUX[16] invert by !MAIN[13][1][48]CELL[16].IMUX_IMUX[4] invert by !MAIN[13][3][48]CELL[17].IMUX_IMUX[30] invert by !MAIN[13][1][40]CELL[17].IMUX_IMUX[24] invert by !MAIN[13][3][40]CELL[17].IMUX_IMUX[6] invert by !MAIN[13][1][32]CELL[17].IMUX_IMUX[0] invert by !MAIN[13][3][32]CELL[16].IMUX_IMUX[30] invert by !MAIN[13][1][24]CELL[16].IMUX_IMUX[24] invert by !MAIN[13][3][24]CELL[16].IMUX_IMUX[6] invert by !MAIN[13][1][16]CELL[16].IMUX_IMUX[0] invert by !MAIN[13][3][16]CELL[15].IMUX_IMUX[30] invert by !MAIN[13][1][8]CELL[15].IMUX_IMUX[24] invert by !MAIN[13][3][8]CELL[15].IMUX_IMUX[6] invert by !MAIN[13][1][0]CELL[15].IMUX_IMUX[0] invert by !MAIN[13][3][0]
S1inCELL[2].IMUX_IMUX[12] invert by !MAIN[6][1][0]CELL[2].IMUX_IMUX[18] invert by !MAIN[6][3][0]CELL[2].IMUX_IMUX[36] invert by !MAIN[6][1][8]CELL[2].IMUX_IMUX[42] invert by !MAIN[6][3][8]CELL[3].IMUX_IMUX[12] invert by !MAIN[6][1][16]CELL[3].IMUX_IMUX[18] invert by !MAIN[6][3][16]CELL[3].IMUX_IMUX[36] invert by !MAIN[6][1][24]CELL[3].IMUX_IMUX[42] invert by !MAIN[6][3][24]CELL[4].IMUX_IMUX[12] invert by !MAIN[6][1][32]CELL[4].IMUX_IMUX[18] invert by !MAIN[6][3][32]CELL[4].IMUX_IMUX[36] invert by !MAIN[6][1][40]CELL[4].IMUX_IMUX[42] invert by !MAIN[6][3][40]CELL[3].IMUX_IMUX[28] invert by !MAIN[6][1][48]CELL[3].IMUX_IMUX[40] invert by !MAIN[6][3][48]CELL[4].IMUX_IMUX[28] invert by !MAIN[6][1][56]CELL[4].IMUX_IMUX[40] invert by !MAIN[6][3][56]CELL[17].IMUX_IMUX[40] invert by !MAIN[13][1][63]CELL[17].IMUX_IMUX[28] invert by !MAIN[13][3][63]CELL[16].IMUX_IMUX[40] invert by !MAIN[13][1][55]CELL[16].IMUX_IMUX[28] invert by !MAIN[13][3][55]CELL[17].IMUX_IMUX[42] invert by !MAIN[13][1][47]CELL[17].IMUX_IMUX[36] invert by !MAIN[13][3][47]CELL[17].IMUX_IMUX[18] invert by !MAIN[13][1][39]CELL[17].IMUX_IMUX[12] invert by !MAIN[13][3][39]CELL[16].IMUX_IMUX[42] invert by !MAIN[13][1][31]CELL[16].IMUX_IMUX[36] invert by !MAIN[13][3][31]CELL[16].IMUX_IMUX[18] invert by !MAIN[13][1][23]CELL[16].IMUX_IMUX[12] invert by !MAIN[13][3][23]CELL[15].IMUX_IMUX[42] invert by !MAIN[13][1][15]CELL[15].IMUX_IMUX[36] invert by !MAIN[13][3][15]CELL[15].IMUX_IMUX[18] invert by !MAIN[13][1][7]CELL[15].IMUX_IMUX[12] invert by !MAIN[13][3][7]
CE0inCELL[2].IMUX_IMUX[1] invert by !MAIN[6][1][5]CELL[2].IMUX_IMUX[7] invert by !MAIN[6][3][5]CELL[2].IMUX_IMUX[25] invert by !MAIN[6][1][13]CELL[2].IMUX_IMUX[31] invert by !MAIN[6][3][13]CELL[3].IMUX_IMUX[1] invert by !MAIN[6][1][21]CELL[3].IMUX_IMUX[7] invert by !MAIN[6][3][21]CELL[3].IMUX_IMUX[25] invert by !MAIN[6][1][29]CELL[3].IMUX_IMUX[31] invert by !MAIN[6][3][29]CELL[4].IMUX_IMUX[1] invert by !MAIN[6][1][37]CELL[4].IMUX_IMUX[7] invert by !MAIN[6][3][37]CELL[4].IMUX_IMUX[25] invert by !MAIN[6][1][45]CELL[4].IMUX_IMUX[31] invert by !MAIN[6][3][45]CELL[3].IMUX_IMUX[5] invert by !MAIN[6][1][53]CELL[3].IMUX_IMUX[17] invert by !MAIN[6][3][53]CELL[4].IMUX_IMUX[5] invert by !MAIN[6][1][61]CELL[4].IMUX_IMUX[17] invert by !MAIN[6][3][61]CELL[17].IMUX_IMUX[17] invert by !MAIN[13][1][58]CELL[17].IMUX_IMUX[5] invert by !MAIN[13][3][58]CELL[16].IMUX_IMUX[17] invert by !MAIN[13][1][50]CELL[16].IMUX_IMUX[5] invert by !MAIN[13][3][50]CELL[17].IMUX_IMUX[31] invert by !MAIN[13][1][42]CELL[17].IMUX_IMUX[25] invert by !MAIN[13][3][42]CELL[17].IMUX_IMUX[7] invert by !MAIN[13][1][34]CELL[17].IMUX_IMUX[1] invert by !MAIN[13][3][34]CELL[16].IMUX_IMUX[31] invert by !MAIN[13][1][26]CELL[16].IMUX_IMUX[25] invert by !MAIN[13][3][26]CELL[16].IMUX_IMUX[7] invert by !MAIN[13][1][18]CELL[16].IMUX_IMUX[1] invert by !MAIN[13][3][18]CELL[15].IMUX_IMUX[31] invert by !MAIN[13][1][10]CELL[15].IMUX_IMUX[25] invert by !MAIN[13][3][10]CELL[15].IMUX_IMUX[7] invert by !MAIN[13][1][2]CELL[15].IMUX_IMUX[1] invert by !MAIN[13][3][2]
CE1inCELL[2].IMUX_IMUX[13] invert by !MAIN[6][1][2]CELL[2].IMUX_IMUX[19] invert by !MAIN[6][3][2]CELL[2].IMUX_IMUX[37] invert by !MAIN[6][1][10]CELL[2].IMUX_IMUX[43] invert by !MAIN[6][3][10]CELL[3].IMUX_IMUX[13] invert by !MAIN[6][1][18]CELL[3].IMUX_IMUX[19] invert by !MAIN[6][3][18]CELL[3].IMUX_IMUX[37] invert by !MAIN[6][1][26]CELL[3].IMUX_IMUX[43] invert by !MAIN[6][3][26]CELL[4].IMUX_IMUX[13] invert by !MAIN[6][1][34]CELL[4].IMUX_IMUX[19] invert by !MAIN[6][3][34]CELL[4].IMUX_IMUX[37] invert by !MAIN[6][1][42]CELL[4].IMUX_IMUX[43] invert by !MAIN[6][3][42]CELL[3].IMUX_IMUX[29] invert by !MAIN[6][1][50]CELL[3].IMUX_IMUX[41] invert by !MAIN[6][3][50]CELL[4].IMUX_IMUX[29] invert by !MAIN[6][1][58]CELL[4].IMUX_IMUX[41] invert by !MAIN[6][3][58]CELL[17].IMUX_IMUX[41] invert by !MAIN[13][1][61]CELL[17].IMUX_IMUX[29] invert by !MAIN[13][3][61]CELL[16].IMUX_IMUX[41] invert by !MAIN[13][1][53]CELL[16].IMUX_IMUX[29] invert by !MAIN[13][3][53]CELL[17].IMUX_IMUX[43] invert by !MAIN[13][1][45]CELL[17].IMUX_IMUX[37] invert by !MAIN[13][3][45]CELL[17].IMUX_IMUX[19] invert by !MAIN[13][1][37]CELL[17].IMUX_IMUX[13] invert by !MAIN[13][3][37]CELL[16].IMUX_IMUX[43] invert by !MAIN[13][1][29]CELL[16].IMUX_IMUX[37] invert by !MAIN[13][3][29]CELL[16].IMUX_IMUX[19] invert by !MAIN[13][1][21]CELL[16].IMUX_IMUX[13] invert by !MAIN[13][3][21]CELL[15].IMUX_IMUX[43] invert by !MAIN[13][1][13]CELL[15].IMUX_IMUX[37] invert by !MAIN[13][3][13]CELL[15].IMUX_IMUX[19] invert by !MAIN[13][1][5]CELL[15].IMUX_IMUX[13] invert by !MAIN[13][3][5]
IGNORE0inCELL[2].IMUX_IMUX[2] invert by !MAIN[6][0][5]CELL[2].IMUX_IMUX[8] invert by !MAIN[6][2][5]CELL[2].IMUX_IMUX[26] invert by !MAIN[6][0][13]CELL[2].IMUX_IMUX[32] invert by !MAIN[6][2][13]CELL[3].IMUX_IMUX[2] invert by !MAIN[6][0][21]CELL[3].IMUX_IMUX[8] invert by !MAIN[6][2][21]CELL[3].IMUX_IMUX[26] invert by !MAIN[6][0][29]CELL[3].IMUX_IMUX[32] invert by !MAIN[6][2][29]CELL[4].IMUX_IMUX[2] invert by !MAIN[6][0][37]CELL[4].IMUX_IMUX[8] invert by !MAIN[6][2][37]CELL[4].IMUX_IMUX[26] invert by !MAIN[6][0][45]CELL[4].IMUX_IMUX[32] invert by !MAIN[6][2][45]CELL[3].IMUX_IMUX[10] invert by !MAIN[6][0][53]CELL[3].IMUX_IMUX[22] invert by !MAIN[6][2][53]CELL[4].IMUX_IMUX[10] invert by !MAIN[6][0][61]CELL[4].IMUX_IMUX[22] invert by !MAIN[6][2][61]CELL[17].IMUX_IMUX[22] invert by !MAIN[13][0][58]CELL[17].IMUX_IMUX[10] invert by !MAIN[13][2][58]CELL[16].IMUX_IMUX[22] invert by !MAIN[13][0][50]CELL[16].IMUX_IMUX[10] invert by !MAIN[13][2][50]CELL[17].IMUX_IMUX[32] invert by !MAIN[13][0][42]CELL[17].IMUX_IMUX[26] invert by !MAIN[13][2][42]CELL[17].IMUX_IMUX[8] invert by !MAIN[13][0][34]CELL[17].IMUX_IMUX[2] invert by !MAIN[13][2][34]CELL[16].IMUX_IMUX[32] invert by !MAIN[13][0][26]CELL[16].IMUX_IMUX[26] invert by !MAIN[13][2][26]CELL[16].IMUX_IMUX[8] invert by !MAIN[13][0][18]CELL[16].IMUX_IMUX[2] invert by !MAIN[13][2][18]CELL[15].IMUX_IMUX[32] invert by !MAIN[13][0][10]CELL[15].IMUX_IMUX[26] invert by !MAIN[13][2][10]CELL[15].IMUX_IMUX[8] invert by !MAIN[13][0][2]CELL[15].IMUX_IMUX[2] invert by !MAIN[13][2][2]
IGNORE1inCELL[2].IMUX_IMUX[14] invert by !MAIN[6][0][2]CELL[2].IMUX_IMUX[20] invert by !MAIN[6][2][2]CELL[2].IMUX_IMUX[38] invert by !MAIN[6][0][10]CELL[2].IMUX_IMUX[44] invert by !MAIN[6][2][10]CELL[3].IMUX_IMUX[14] invert by !MAIN[6][0][18]CELL[3].IMUX_IMUX[20] invert by !MAIN[6][2][18]CELL[3].IMUX_IMUX[38] invert by !MAIN[6][0][26]CELL[3].IMUX_IMUX[44] invert by !MAIN[6][2][26]CELL[4].IMUX_IMUX[14] invert by !MAIN[6][0][34]CELL[4].IMUX_IMUX[20] invert by !MAIN[6][2][34]CELL[4].IMUX_IMUX[38] invert by !MAIN[6][0][42]CELL[4].IMUX_IMUX[44] invert by !MAIN[6][2][42]CELL[3].IMUX_IMUX[34] invert by !MAIN[6][0][50]CELL[3].IMUX_IMUX[46] invert by !MAIN[6][2][50]CELL[4].IMUX_IMUX[34] invert by !MAIN[6][0][58]CELL[4].IMUX_IMUX[46] invert by !MAIN[6][2][58]CELL[17].IMUX_IMUX[46] invert by !MAIN[13][0][61]CELL[17].IMUX_IMUX[34] invert by !MAIN[13][2][61]CELL[16].IMUX_IMUX[46] invert by !MAIN[13][0][53]CELL[16].IMUX_IMUX[34] invert by !MAIN[13][2][53]CELL[17].IMUX_IMUX[44] invert by !MAIN[13][0][45]CELL[17].IMUX_IMUX[38] invert by !MAIN[13][2][45]CELL[17].IMUX_IMUX[20] invert by !MAIN[13][0][37]CELL[17].IMUX_IMUX[14] invert by !MAIN[13][2][37]CELL[16].IMUX_IMUX[44] invert by !MAIN[13][0][29]CELL[16].IMUX_IMUX[38] invert by !MAIN[13][2][29]CELL[16].IMUX_IMUX[20] invert by !MAIN[13][0][21]CELL[16].IMUX_IMUX[14] invert by !MAIN[13][2][21]CELL[15].IMUX_IMUX[44] invert by !MAIN[13][0][13]CELL[15].IMUX_IMUX[38] invert by !MAIN[13][2][13]CELL[15].IMUX_IMUX[20] invert by !MAIN[13][0][5]CELL[15].IMUX_IMUX[14] invert by !MAIN[13][2][5]
OoutCELL[0].OUT_BUFG[0], CELL[0].GCLK[0]CELL[0].OUT_BUFG[1], CELL[0].GCLK[1]CELL[0].OUT_BUFG[2], CELL[0].GCLK[2]CELL[0].OUT_BUFG[3], CELL[0].GCLK[3]CELL[0].OUT_BUFG[4], CELL[0].GCLK[4]CELL[0].OUT_BUFG[5], CELL[0].GCLK[5]CELL[0].OUT_BUFG[6], CELL[0].GCLK[6]CELL[0].OUT_BUFG[7], CELL[0].GCLK[7]CELL[0].OUT_BUFG[8], CELL[0].GCLK[8]CELL[0].OUT_BUFG[9], CELL[0].GCLK[9]CELL[0].OUT_BUFG[10], CELL[0].GCLK[10]CELL[0].OUT_BUFG[11], CELL[0].GCLK[11]CELL[0].OUT_BUFG[12], CELL[0].GCLK[12]CELL[0].OUT_BUFG[13], CELL[0].GCLK[13]CELL[0].OUT_BUFG[14], CELL[0].GCLK[14]CELL[0].OUT_BUFG[15], CELL[0].GCLK[15]CELL[0].OUT_BUFG[16], CELL[0].GCLK[16]CELL[0].OUT_BUFG[17], CELL[0].GCLK[17]CELL[0].OUT_BUFG[18], CELL[0].GCLK[18]CELL[0].OUT_BUFG[19], CELL[0].GCLK[19]CELL[0].OUT_BUFG[20], CELL[0].GCLK[20]CELL[0].OUT_BUFG[21], CELL[0].GCLK[21]CELL[0].OUT_BUFG[22], CELL[0].GCLK[22]CELL[0].OUT_BUFG[23], CELL[0].GCLK[23]CELL[0].OUT_BUFG[24], CELL[0].GCLK[24]CELL[0].OUT_BUFG[25], CELL[0].GCLK[25]CELL[0].OUT_BUFG[26], CELL[0].GCLK[26]CELL[0].OUT_BUFG[27], CELL[0].GCLK[27]CELL[0].OUT_BUFG[28], CELL[0].GCLK[28]CELL[0].OUT_BUFG[29], CELL[0].GCLK[29]CELL[0].OUT_BUFG[30], CELL[0].GCLK[30]CELL[0].OUT_BUFG[31], CELL[0].GCLK[31]
virtex5 CLK_BUFG bel BUFGCTRL attribute bits
AttributeBUFGCTRL[0]BUFGCTRL[1]BUFGCTRL[2]BUFGCTRL[3]BUFGCTRL[4]BUFGCTRL[5]BUFGCTRL[6]BUFGCTRL[7]BUFGCTRL[8]BUFGCTRL[9]BUFGCTRL[10]BUFGCTRL[11]BUFGCTRL[12]BUFGCTRL[13]BUFGCTRL[14]BUFGCTRL[15]BUFGCTRL[16]BUFGCTRL[17]BUFGCTRL[18]BUFGCTRL[19]BUFGCTRL[20]BUFGCTRL[21]BUFGCTRL[22]BUFGCTRL[23]BUFGCTRL[24]BUFGCTRL[25]BUFGCTRL[26]BUFGCTRL[27]BUFGCTRL[28]BUFGCTRL[29]BUFGCTRL[30]BUFGCTRL[31]
CREATE_EDGE!MAIN[6][1][1]!MAIN[6][3][1]!MAIN[6][1][9]!MAIN[6][3][9]!MAIN[6][1][17]!MAIN[6][3][17]!MAIN[6][1][25]!MAIN[6][3][25]!MAIN[6][1][33]!MAIN[6][3][33]!MAIN[6][1][41]!MAIN[6][3][41]!MAIN[6][1][49]!MAIN[6][3][49]!MAIN[6][1][57]!MAIN[6][3][57]!MAIN[13][1][62]!MAIN[13][3][62]!MAIN[13][1][54]!MAIN[13][3][54]!MAIN[13][1][46]!MAIN[13][3][46]!MAIN[13][1][38]!MAIN[13][3][38]!MAIN[13][1][30]!MAIN[13][3][30]!MAIN[13][1][22]!MAIN[13][3][22]!MAIN[13][1][14]!MAIN[13][3][14]!MAIN[13][1][6]!MAIN[13][3][6]
INIT_OUT bit 0MAIN[6][0][7]MAIN[6][2][7]MAIN[6][0][15]MAIN[6][2][15]MAIN[6][0][23]MAIN[6][2][23]MAIN[6][0][31]MAIN[6][2][31]MAIN[6][0][39]MAIN[6][2][39]MAIN[6][0][47]MAIN[6][2][47]MAIN[6][0][55]MAIN[6][2][55]MAIN[6][0][63]MAIN[6][2][63]MAIN[13][0][56]MAIN[13][2][56]MAIN[13][0][48]MAIN[13][2][48]MAIN[13][0][40]MAIN[13][2][40]MAIN[13][0][32]MAIN[13][2][32]MAIN[13][0][24]MAIN[13][2][24]MAIN[13][0][16]MAIN[13][2][16]MAIN[13][0][8]MAIN[13][2][8]MAIN[13][0][0]MAIN[13][2][0]
PRESELECT_I0MAIN[6][1][4]MAIN[6][3][4]MAIN[6][1][12]MAIN[6][3][12]MAIN[6][1][20]MAIN[6][3][20]MAIN[6][1][28]MAIN[6][3][28]MAIN[6][1][36]MAIN[6][3][36]MAIN[6][1][44]MAIN[6][3][44]MAIN[6][1][52]MAIN[6][3][52]MAIN[6][1][60]MAIN[6][3][60]MAIN[13][1][59]MAIN[13][3][59]MAIN[13][1][51]MAIN[13][3][51]MAIN[13][1][43]MAIN[13][3][43]MAIN[13][1][35]MAIN[13][3][35]MAIN[13][1][27]MAIN[13][3][27]MAIN[13][1][19]MAIN[13][3][19]MAIN[13][1][11]MAIN[13][3][11]MAIN[13][1][3]MAIN[13][3][3]
PRESELECT_I1MAIN[6][1][3]MAIN[6][3][3]MAIN[6][1][11]MAIN[6][3][11]MAIN[6][1][19]MAIN[6][3][19]MAIN[6][1][27]MAIN[6][3][27]MAIN[6][1][35]MAIN[6][3][35]MAIN[6][1][43]MAIN[6][3][43]MAIN[6][1][51]MAIN[6][3][51]MAIN[6][1][59]MAIN[6][3][59]MAIN[13][1][60]MAIN[13][3][60]MAIN[13][1][52]MAIN[13][3][52]MAIN[13][1][44]MAIN[13][3][44]MAIN[13][1][36]MAIN[13][3][36]MAIN[13][1][28]MAIN[13][3][28]MAIN[13][1][20]MAIN[13][3][20]MAIN[13][1][12]MAIN[13][3][12]MAIN[13][1][4]MAIN[13][3][4]

Bel wires

virtex5 CLK_BUFG bel wires
WirePins
CELL[0].OUT_BUFG[0]BUFGCTRL[0].O
CELL[0].OUT_BUFG[1]BUFGCTRL[1].O
CELL[0].OUT_BUFG[2]BUFGCTRL[2].O
CELL[0].OUT_BUFG[3]BUFGCTRL[3].O
CELL[0].OUT_BUFG[4]BUFGCTRL[4].O
CELL[0].OUT_BUFG[5]BUFGCTRL[5].O
CELL[0].OUT_BUFG[6]BUFGCTRL[6].O
CELL[0].OUT_BUFG[7]BUFGCTRL[7].O
CELL[0].OUT_BUFG[8]BUFGCTRL[8].O
CELL[0].OUT_BUFG[9]BUFGCTRL[9].O
CELL[0].OUT_BUFG[10]BUFGCTRL[10].O
CELL[0].OUT_BUFG[11]BUFGCTRL[11].O
CELL[0].OUT_BUFG[12]BUFGCTRL[12].O
CELL[0].OUT_BUFG[13]BUFGCTRL[13].O
CELL[0].OUT_BUFG[14]BUFGCTRL[14].O
CELL[0].OUT_BUFG[15]BUFGCTRL[15].O
CELL[0].OUT_BUFG[16]BUFGCTRL[16].O
CELL[0].OUT_BUFG[17]BUFGCTRL[17].O
CELL[0].OUT_BUFG[18]BUFGCTRL[18].O
CELL[0].OUT_BUFG[19]BUFGCTRL[19].O
CELL[0].OUT_BUFG[20]BUFGCTRL[20].O
CELL[0].OUT_BUFG[21]BUFGCTRL[21].O
CELL[0].OUT_BUFG[22]BUFGCTRL[22].O
CELL[0].OUT_BUFG[23]BUFGCTRL[23].O
CELL[0].OUT_BUFG[24]BUFGCTRL[24].O
CELL[0].OUT_BUFG[25]BUFGCTRL[25].O
CELL[0].OUT_BUFG[26]BUFGCTRL[26].O
CELL[0].OUT_BUFG[27]BUFGCTRL[27].O
CELL[0].OUT_BUFG[28]BUFGCTRL[28].O
CELL[0].OUT_BUFG[29]BUFGCTRL[29].O
CELL[0].OUT_BUFG[30]BUFGCTRL[30].O
CELL[0].OUT_BUFG[31]BUFGCTRL[31].O
CELL[0].GCLK[0]BUFGCTRL[0].O
CELL[0].GCLK[1]BUFGCTRL[1].O
CELL[0].GCLK[2]BUFGCTRL[2].O
CELL[0].GCLK[3]BUFGCTRL[3].O
CELL[0].GCLK[4]BUFGCTRL[4].O
CELL[0].GCLK[5]BUFGCTRL[5].O
CELL[0].GCLK[6]BUFGCTRL[6].O
CELL[0].GCLK[7]BUFGCTRL[7].O
CELL[0].GCLK[8]BUFGCTRL[8].O
CELL[0].GCLK[9]BUFGCTRL[9].O
CELL[0].GCLK[10]BUFGCTRL[10].O
CELL[0].GCLK[11]BUFGCTRL[11].O
CELL[0].GCLK[12]BUFGCTRL[12].O
CELL[0].GCLK[13]BUFGCTRL[13].O
CELL[0].GCLK[14]BUFGCTRL[14].O
CELL[0].GCLK[15]BUFGCTRL[15].O
CELL[0].GCLK[16]BUFGCTRL[16].O
CELL[0].GCLK[17]BUFGCTRL[17].O
CELL[0].GCLK[18]BUFGCTRL[18].O
CELL[0].GCLK[19]BUFGCTRL[19].O
CELL[0].GCLK[20]BUFGCTRL[20].O
CELL[0].GCLK[21]BUFGCTRL[21].O
CELL[0].GCLK[22]BUFGCTRL[22].O
CELL[0].GCLK[23]BUFGCTRL[23].O
CELL[0].GCLK[24]BUFGCTRL[24].O
CELL[0].GCLK[25]BUFGCTRL[25].O
CELL[0].GCLK[26]BUFGCTRL[26].O
CELL[0].GCLK[27]BUFGCTRL[27].O
CELL[0].GCLK[28]BUFGCTRL[28].O
CELL[0].GCLK[29]BUFGCTRL[29].O
CELL[0].GCLK[30]BUFGCTRL[30].O
CELL[0].GCLK[31]BUFGCTRL[31].O
CELL[0].IMUX_BUFG_O[0]BUFGCTRL[0].I0
CELL[0].IMUX_BUFG_O[1]BUFGCTRL[0].I1
CELL[0].IMUX_BUFG_O[2]BUFGCTRL[1].I0
CELL[0].IMUX_BUFG_O[3]BUFGCTRL[1].I1
CELL[0].IMUX_BUFG_O[4]BUFGCTRL[2].I0
CELL[0].IMUX_BUFG_O[5]BUFGCTRL[2].I1
CELL[0].IMUX_BUFG_O[6]BUFGCTRL[3].I0
CELL[0].IMUX_BUFG_O[7]BUFGCTRL[3].I1
CELL[0].IMUX_BUFG_O[8]BUFGCTRL[4].I0
CELL[0].IMUX_BUFG_O[9]BUFGCTRL[4].I1
CELL[0].IMUX_BUFG_O[10]BUFGCTRL[5].I0
CELL[0].IMUX_BUFG_O[11]BUFGCTRL[5].I1
CELL[0].IMUX_BUFG_O[12]BUFGCTRL[6].I0
CELL[0].IMUX_BUFG_O[13]BUFGCTRL[6].I1
CELL[0].IMUX_BUFG_O[14]BUFGCTRL[7].I0
CELL[0].IMUX_BUFG_O[15]BUFGCTRL[7].I1
CELL[0].IMUX_BUFG_O[16]BUFGCTRL[8].I0
CELL[0].IMUX_BUFG_O[17]BUFGCTRL[8].I1
CELL[0].IMUX_BUFG_O[18]BUFGCTRL[9].I0
CELL[0].IMUX_BUFG_O[19]BUFGCTRL[9].I1
CELL[0].IMUX_BUFG_O[20]BUFGCTRL[10].I0
CELL[0].IMUX_BUFG_O[21]BUFGCTRL[10].I1
CELL[0].IMUX_BUFG_O[22]BUFGCTRL[11].I0
CELL[0].IMUX_BUFG_O[23]BUFGCTRL[11].I1
CELL[0].IMUX_BUFG_O[24]BUFGCTRL[12].I0
CELL[0].IMUX_BUFG_O[25]BUFGCTRL[12].I1
CELL[0].IMUX_BUFG_O[26]BUFGCTRL[13].I0
CELL[0].IMUX_BUFG_O[27]BUFGCTRL[13].I1
CELL[0].IMUX_BUFG_O[28]BUFGCTRL[14].I0
CELL[0].IMUX_BUFG_O[29]BUFGCTRL[14].I1
CELL[0].IMUX_BUFG_O[30]BUFGCTRL[15].I0
CELL[0].IMUX_BUFG_O[31]BUFGCTRL[15].I1
CELL[2].IMUX_IMUX[0]BUFGCTRL[0].S0
CELL[2].IMUX_IMUX[1]BUFGCTRL[0].CE0
CELL[2].IMUX_IMUX[2]BUFGCTRL[0].IGNORE0
CELL[2].IMUX_IMUX[6]BUFGCTRL[1].S0
CELL[2].IMUX_IMUX[7]BUFGCTRL[1].CE0
CELL[2].IMUX_IMUX[8]BUFGCTRL[1].IGNORE0
CELL[2].IMUX_IMUX[12]BUFGCTRL[0].S1
CELL[2].IMUX_IMUX[13]BUFGCTRL[0].CE1
CELL[2].IMUX_IMUX[14]BUFGCTRL[0].IGNORE1
CELL[2].IMUX_IMUX[18]BUFGCTRL[1].S1
CELL[2].IMUX_IMUX[19]BUFGCTRL[1].CE1
CELL[2].IMUX_IMUX[20]BUFGCTRL[1].IGNORE1
CELL[2].IMUX_IMUX[24]BUFGCTRL[2].S0
CELL[2].IMUX_IMUX[25]BUFGCTRL[2].CE0
CELL[2].IMUX_IMUX[26]BUFGCTRL[2].IGNORE0
CELL[2].IMUX_IMUX[30]BUFGCTRL[3].S0
CELL[2].IMUX_IMUX[31]BUFGCTRL[3].CE0
CELL[2].IMUX_IMUX[32]BUFGCTRL[3].IGNORE0
CELL[2].IMUX_IMUX[36]BUFGCTRL[2].S1
CELL[2].IMUX_IMUX[37]BUFGCTRL[2].CE1
CELL[2].IMUX_IMUX[38]BUFGCTRL[2].IGNORE1
CELL[2].IMUX_IMUX[42]BUFGCTRL[3].S1
CELL[2].IMUX_IMUX[43]BUFGCTRL[3].CE1
CELL[2].IMUX_IMUX[44]BUFGCTRL[3].IGNORE1
CELL[3].IMUX_IMUX[0]BUFGCTRL[4].S0
CELL[3].IMUX_IMUX[1]BUFGCTRL[4].CE0
CELL[3].IMUX_IMUX[2]BUFGCTRL[4].IGNORE0
CELL[3].IMUX_IMUX[4]BUFGCTRL[12].S0
CELL[3].IMUX_IMUX[5]BUFGCTRL[12].CE0
CELL[3].IMUX_IMUX[6]BUFGCTRL[5].S0
CELL[3].IMUX_IMUX[7]BUFGCTRL[5].CE0
CELL[3].IMUX_IMUX[8]BUFGCTRL[5].IGNORE0
CELL[3].IMUX_IMUX[10]BUFGCTRL[12].IGNORE0
CELL[3].IMUX_IMUX[12]BUFGCTRL[4].S1
CELL[3].IMUX_IMUX[13]BUFGCTRL[4].CE1
CELL[3].IMUX_IMUX[14]BUFGCTRL[4].IGNORE1
CELL[3].IMUX_IMUX[16]BUFGCTRL[13].S0
CELL[3].IMUX_IMUX[17]BUFGCTRL[13].CE0
CELL[3].IMUX_IMUX[18]BUFGCTRL[5].S1
CELL[3].IMUX_IMUX[19]BUFGCTRL[5].CE1
CELL[3].IMUX_IMUX[20]BUFGCTRL[5].IGNORE1
CELL[3].IMUX_IMUX[22]BUFGCTRL[13].IGNORE0
CELL[3].IMUX_IMUX[24]BUFGCTRL[6].S0
CELL[3].IMUX_IMUX[25]BUFGCTRL[6].CE0
CELL[3].IMUX_IMUX[26]BUFGCTRL[6].IGNORE0
CELL[3].IMUX_IMUX[28]BUFGCTRL[12].S1
CELL[3].IMUX_IMUX[29]BUFGCTRL[12].CE1
CELL[3].IMUX_IMUX[30]BUFGCTRL[7].S0
CELL[3].IMUX_IMUX[31]BUFGCTRL[7].CE0
CELL[3].IMUX_IMUX[32]BUFGCTRL[7].IGNORE0
CELL[3].IMUX_IMUX[34]BUFGCTRL[12].IGNORE1
CELL[3].IMUX_IMUX[36]BUFGCTRL[6].S1
CELL[3].IMUX_IMUX[37]BUFGCTRL[6].CE1
CELL[3].IMUX_IMUX[38]BUFGCTRL[6].IGNORE1
CELL[3].IMUX_IMUX[40]BUFGCTRL[13].S1
CELL[3].IMUX_IMUX[41]BUFGCTRL[13].CE1
CELL[3].IMUX_IMUX[42]BUFGCTRL[7].S1
CELL[3].IMUX_IMUX[43]BUFGCTRL[7].CE1
CELL[3].IMUX_IMUX[44]BUFGCTRL[7].IGNORE1
CELL[3].IMUX_IMUX[46]BUFGCTRL[13].IGNORE1
CELL[4].IMUX_IMUX[0]BUFGCTRL[8].S0
CELL[4].IMUX_IMUX[1]BUFGCTRL[8].CE0
CELL[4].IMUX_IMUX[2]BUFGCTRL[8].IGNORE0
CELL[4].IMUX_IMUX[4]BUFGCTRL[14].S0
CELL[4].IMUX_IMUX[5]BUFGCTRL[14].CE0
CELL[4].IMUX_IMUX[6]BUFGCTRL[9].S0
CELL[4].IMUX_IMUX[7]BUFGCTRL[9].CE0
CELL[4].IMUX_IMUX[8]BUFGCTRL[9].IGNORE0
CELL[4].IMUX_IMUX[10]BUFGCTRL[14].IGNORE0
CELL[4].IMUX_IMUX[12]BUFGCTRL[8].S1
CELL[4].IMUX_IMUX[13]BUFGCTRL[8].CE1
CELL[4].IMUX_IMUX[14]BUFGCTRL[8].IGNORE1
CELL[4].IMUX_IMUX[16]BUFGCTRL[15].S0
CELL[4].IMUX_IMUX[17]BUFGCTRL[15].CE0
CELL[4].IMUX_IMUX[18]BUFGCTRL[9].S1
CELL[4].IMUX_IMUX[19]BUFGCTRL[9].CE1
CELL[4].IMUX_IMUX[20]BUFGCTRL[9].IGNORE1
CELL[4].IMUX_IMUX[22]BUFGCTRL[15].IGNORE0
CELL[4].IMUX_IMUX[24]BUFGCTRL[10].S0
CELL[4].IMUX_IMUX[25]BUFGCTRL[10].CE0
CELL[4].IMUX_IMUX[26]BUFGCTRL[10].IGNORE0
CELL[4].IMUX_IMUX[28]BUFGCTRL[14].S1
CELL[4].IMUX_IMUX[29]BUFGCTRL[14].CE1
CELL[4].IMUX_IMUX[30]BUFGCTRL[11].S0
CELL[4].IMUX_IMUX[31]BUFGCTRL[11].CE0
CELL[4].IMUX_IMUX[32]BUFGCTRL[11].IGNORE0
CELL[4].IMUX_IMUX[34]BUFGCTRL[14].IGNORE1
CELL[4].IMUX_IMUX[36]BUFGCTRL[10].S1
CELL[4].IMUX_IMUX[37]BUFGCTRL[10].CE1
CELL[4].IMUX_IMUX[38]BUFGCTRL[10].IGNORE1
CELL[4].IMUX_IMUX[40]BUFGCTRL[15].S1
CELL[4].IMUX_IMUX[41]BUFGCTRL[15].CE1
CELL[4].IMUX_IMUX[42]BUFGCTRL[11].S1
CELL[4].IMUX_IMUX[43]BUFGCTRL[11].CE1
CELL[4].IMUX_IMUX[44]BUFGCTRL[11].IGNORE1
CELL[4].IMUX_IMUX[46]BUFGCTRL[15].IGNORE1
CELL[10].IMUX_BUFG_O[0]BUFGCTRL[16].I0
CELL[10].IMUX_BUFG_O[1]BUFGCTRL[16].I1
CELL[10].IMUX_BUFG_O[2]BUFGCTRL[17].I0
CELL[10].IMUX_BUFG_O[3]BUFGCTRL[17].I1
CELL[10].IMUX_BUFG_O[4]BUFGCTRL[18].I0
CELL[10].IMUX_BUFG_O[5]BUFGCTRL[18].I1
CELL[10].IMUX_BUFG_O[6]BUFGCTRL[19].I0
CELL[10].IMUX_BUFG_O[7]BUFGCTRL[19].I1
CELL[10].IMUX_BUFG_O[8]BUFGCTRL[20].I0
CELL[10].IMUX_BUFG_O[9]BUFGCTRL[20].I1
CELL[10].IMUX_BUFG_O[10]BUFGCTRL[21].I0
CELL[10].IMUX_BUFG_O[11]BUFGCTRL[21].I1
CELL[10].IMUX_BUFG_O[12]BUFGCTRL[22].I0
CELL[10].IMUX_BUFG_O[13]BUFGCTRL[22].I1
CELL[10].IMUX_BUFG_O[14]BUFGCTRL[23].I0
CELL[10].IMUX_BUFG_O[15]BUFGCTRL[23].I1
CELL[10].IMUX_BUFG_O[16]BUFGCTRL[24].I0
CELL[10].IMUX_BUFG_O[17]BUFGCTRL[24].I1
CELL[10].IMUX_BUFG_O[18]BUFGCTRL[25].I0
CELL[10].IMUX_BUFG_O[19]BUFGCTRL[25].I1
CELL[10].IMUX_BUFG_O[20]BUFGCTRL[26].I0
CELL[10].IMUX_BUFG_O[21]BUFGCTRL[26].I1
CELL[10].IMUX_BUFG_O[22]BUFGCTRL[27].I0
CELL[10].IMUX_BUFG_O[23]BUFGCTRL[27].I1
CELL[10].IMUX_BUFG_O[24]BUFGCTRL[28].I0
CELL[10].IMUX_BUFG_O[25]BUFGCTRL[28].I1
CELL[10].IMUX_BUFG_O[26]BUFGCTRL[29].I0
CELL[10].IMUX_BUFG_O[27]BUFGCTRL[29].I1
CELL[10].IMUX_BUFG_O[28]BUFGCTRL[30].I0
CELL[10].IMUX_BUFG_O[29]BUFGCTRL[30].I1
CELL[10].IMUX_BUFG_O[30]BUFGCTRL[31].I0
CELL[10].IMUX_BUFG_O[31]BUFGCTRL[31].I1
CELL[15].IMUX_IMUX[0]BUFGCTRL[31].S0
CELL[15].IMUX_IMUX[1]BUFGCTRL[31].CE0
CELL[15].IMUX_IMUX[2]BUFGCTRL[31].IGNORE0
CELL[15].IMUX_IMUX[6]BUFGCTRL[30].S0
CELL[15].IMUX_IMUX[7]BUFGCTRL[30].CE0
CELL[15].IMUX_IMUX[8]BUFGCTRL[30].IGNORE0
CELL[15].IMUX_IMUX[12]BUFGCTRL[31].S1
CELL[15].IMUX_IMUX[13]BUFGCTRL[31].CE1
CELL[15].IMUX_IMUX[14]BUFGCTRL[31].IGNORE1
CELL[15].IMUX_IMUX[18]BUFGCTRL[30].S1
CELL[15].IMUX_IMUX[19]BUFGCTRL[30].CE1
CELL[15].IMUX_IMUX[20]BUFGCTRL[30].IGNORE1
CELL[15].IMUX_IMUX[24]BUFGCTRL[29].S0
CELL[15].IMUX_IMUX[25]BUFGCTRL[29].CE0
CELL[15].IMUX_IMUX[26]BUFGCTRL[29].IGNORE0
CELL[15].IMUX_IMUX[30]BUFGCTRL[28].S0
CELL[15].IMUX_IMUX[31]BUFGCTRL[28].CE0
CELL[15].IMUX_IMUX[32]BUFGCTRL[28].IGNORE0
CELL[15].IMUX_IMUX[36]BUFGCTRL[29].S1
CELL[15].IMUX_IMUX[37]BUFGCTRL[29].CE1
CELL[15].IMUX_IMUX[38]BUFGCTRL[29].IGNORE1
CELL[15].IMUX_IMUX[42]BUFGCTRL[28].S1
CELL[15].IMUX_IMUX[43]BUFGCTRL[28].CE1
CELL[15].IMUX_IMUX[44]BUFGCTRL[28].IGNORE1
CELL[16].IMUX_IMUX[0]BUFGCTRL[27].S0
CELL[16].IMUX_IMUX[1]BUFGCTRL[27].CE0
CELL[16].IMUX_IMUX[2]BUFGCTRL[27].IGNORE0
CELL[16].IMUX_IMUX[4]BUFGCTRL[19].S0
CELL[16].IMUX_IMUX[5]BUFGCTRL[19].CE0
CELL[16].IMUX_IMUX[6]BUFGCTRL[26].S0
CELL[16].IMUX_IMUX[7]BUFGCTRL[26].CE0
CELL[16].IMUX_IMUX[8]BUFGCTRL[26].IGNORE0
CELL[16].IMUX_IMUX[10]BUFGCTRL[19].IGNORE0
CELL[16].IMUX_IMUX[12]BUFGCTRL[27].S1
CELL[16].IMUX_IMUX[13]BUFGCTRL[27].CE1
CELL[16].IMUX_IMUX[14]BUFGCTRL[27].IGNORE1
CELL[16].IMUX_IMUX[16]BUFGCTRL[18].S0
CELL[16].IMUX_IMUX[17]BUFGCTRL[18].CE0
CELL[16].IMUX_IMUX[18]BUFGCTRL[26].S1
CELL[16].IMUX_IMUX[19]BUFGCTRL[26].CE1
CELL[16].IMUX_IMUX[20]BUFGCTRL[26].IGNORE1
CELL[16].IMUX_IMUX[22]BUFGCTRL[18].IGNORE0
CELL[16].IMUX_IMUX[24]BUFGCTRL[25].S0
CELL[16].IMUX_IMUX[25]BUFGCTRL[25].CE0
CELL[16].IMUX_IMUX[26]BUFGCTRL[25].IGNORE0
CELL[16].IMUX_IMUX[28]BUFGCTRL[19].S1
CELL[16].IMUX_IMUX[29]BUFGCTRL[19].CE1
CELL[16].IMUX_IMUX[30]BUFGCTRL[24].S0
CELL[16].IMUX_IMUX[31]BUFGCTRL[24].CE0
CELL[16].IMUX_IMUX[32]BUFGCTRL[24].IGNORE0
CELL[16].IMUX_IMUX[34]BUFGCTRL[19].IGNORE1
CELL[16].IMUX_IMUX[36]BUFGCTRL[25].S1
CELL[16].IMUX_IMUX[37]BUFGCTRL[25].CE1
CELL[16].IMUX_IMUX[38]BUFGCTRL[25].IGNORE1
CELL[16].IMUX_IMUX[40]BUFGCTRL[18].S1
CELL[16].IMUX_IMUX[41]BUFGCTRL[18].CE1
CELL[16].IMUX_IMUX[42]BUFGCTRL[24].S1
CELL[16].IMUX_IMUX[43]BUFGCTRL[24].CE1
CELL[16].IMUX_IMUX[44]BUFGCTRL[24].IGNORE1
CELL[16].IMUX_IMUX[46]BUFGCTRL[18].IGNORE1
CELL[17].IMUX_IMUX[0]BUFGCTRL[23].S0
CELL[17].IMUX_IMUX[1]BUFGCTRL[23].CE0
CELL[17].IMUX_IMUX[2]BUFGCTRL[23].IGNORE0
CELL[17].IMUX_IMUX[4]BUFGCTRL[17].S0
CELL[17].IMUX_IMUX[5]BUFGCTRL[17].CE0
CELL[17].IMUX_IMUX[6]BUFGCTRL[22].S0
CELL[17].IMUX_IMUX[7]BUFGCTRL[22].CE0
CELL[17].IMUX_IMUX[8]BUFGCTRL[22].IGNORE0
CELL[17].IMUX_IMUX[10]BUFGCTRL[17].IGNORE0
CELL[17].IMUX_IMUX[12]BUFGCTRL[23].S1
CELL[17].IMUX_IMUX[13]BUFGCTRL[23].CE1
CELL[17].IMUX_IMUX[14]BUFGCTRL[23].IGNORE1
CELL[17].IMUX_IMUX[16]BUFGCTRL[16].S0
CELL[17].IMUX_IMUX[17]BUFGCTRL[16].CE0
CELL[17].IMUX_IMUX[18]BUFGCTRL[22].S1
CELL[17].IMUX_IMUX[19]BUFGCTRL[22].CE1
CELL[17].IMUX_IMUX[20]BUFGCTRL[22].IGNORE1
CELL[17].IMUX_IMUX[22]BUFGCTRL[16].IGNORE0
CELL[17].IMUX_IMUX[24]BUFGCTRL[21].S0
CELL[17].IMUX_IMUX[25]BUFGCTRL[21].CE0
CELL[17].IMUX_IMUX[26]BUFGCTRL[21].IGNORE0
CELL[17].IMUX_IMUX[28]BUFGCTRL[17].S1
CELL[17].IMUX_IMUX[29]BUFGCTRL[17].CE1
CELL[17].IMUX_IMUX[30]BUFGCTRL[20].S0
CELL[17].IMUX_IMUX[31]BUFGCTRL[20].CE0
CELL[17].IMUX_IMUX[32]BUFGCTRL[20].IGNORE0
CELL[17].IMUX_IMUX[34]BUFGCTRL[17].IGNORE1
CELL[17].IMUX_IMUX[36]BUFGCTRL[21].S1
CELL[17].IMUX_IMUX[37]BUFGCTRL[21].CE1
CELL[17].IMUX_IMUX[38]BUFGCTRL[21].IGNORE1
CELL[17].IMUX_IMUX[40]BUFGCTRL[16].S1
CELL[17].IMUX_IMUX[41]BUFGCTRL[16].CE1
CELL[17].IMUX_IMUX[42]BUFGCTRL[20].S1
CELL[17].IMUX_IMUX[43]BUFGCTRL[20].CE1
CELL[17].IMUX_IMUX[44]BUFGCTRL[20].IGNORE1
CELL[17].IMUX_IMUX[46]BUFGCTRL[16].IGNORE1

Bitstream

virtex5 CLK_BUFG rect MAIN[0]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[1]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2 -
B60 SPEC_INT: buffer CELL[2].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[6] - SPEC_INT: buffer CELL[2].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[7] -
B59 - - - -
B58 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B57 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B56 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B55 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6 -
B54 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7
B53 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8 -
B52 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9
B51 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B50 SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2 -
B44 SPEC_INT: buffer CELL[2].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[4] - SPEC_INT: buffer CELL[2].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[5] -
B43 - - - -
B42 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B41 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B40 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B39 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6 -
B38 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7
B37 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8 -
B36 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9
B35 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B34 SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2 -
B28 SPEC_INT: buffer CELL[2].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[2] - SPEC_INT: buffer CELL[2].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[3] -
B27 - - - -
B26 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B25 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B24 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B23 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6 -
B22 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7
B21 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8 -
B20 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9
B19 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B18 SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2 -
B12 SPEC_INT: buffer CELL[2].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[0] - SPEC_INT: buffer CELL[2].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[1] -
B11 - - - -
B10 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B9 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B8 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B7 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6 -
B6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7
B5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8 -
B4 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9
B3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B2 SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12 SPEC_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4] SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12 SPEC_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E0.MGT_ROW_I[4]
B1 SPEC_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2] SPEC_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3] SPEC_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E0.MGT_ROW_I[2] SPEC_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E0.MGT_ROW_I[3]
B0 SPEC_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1] SPEC_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0] SPEC_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E0.MGT_ROW_I[1] SPEC_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E0.MGT_ROW_I[0]
virtex5 CLK_BUFG rect MAIN[2]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2 -
B60 SPEC_INT: buffer CELL[3].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[14] - SPEC_INT: buffer CELL[3].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[15] -
B59 - - - -
B58 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B57 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B56 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B55 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6 -
B54 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7
B53 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8 -
B52 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9
B51 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B50 SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2 -
B44 SPEC_INT: buffer CELL[3].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[12] - SPEC_INT: buffer CELL[3].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[13] -
B43 - - - -
B42 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B41 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B40 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B39 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6 -
B38 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7
B37 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8 -
B36 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9
B35 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B34 SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2 -
B28 SPEC_INT: buffer CELL[2].OUT_BEL[9] ← CELL[0].IMUX_BUFG_O[10] - SPEC_INT: buffer CELL[2].OUT_BEL[8] ← CELL[0].IMUX_BUFG_O[11] -
B27 - - - -
B26 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B25 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B24 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B23 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6 -
B22 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7
B21 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8 -
B20 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9
B19 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B18 SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2 -
B12 SPEC_INT: buffer CELL[2].OUT_BEL[11] ← CELL[0].IMUX_BUFG_O[8] - SPEC_INT: buffer CELL[2].OUT_BEL[10] ← CELL[0].IMUX_BUFG_O[9] -
B11 - - - -
B10 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B9 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B8 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B7 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6 -
B6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7
B5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8 -
B4 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9
B3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B2 SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[3]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2 -
B60 SPEC_INT: buffer CELL[3].OUT_BEL[9] ← CELL[0].IMUX_BUFG_O[22] - SPEC_INT: buffer CELL[3].OUT_BEL[8] ← CELL[0].IMUX_BUFG_O[23] -
B59 - - - -
B58 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B57 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B56 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B55 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6 -
B54 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7
B53 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8 -
B52 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9
B51 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B50 SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2 -
B44 SPEC_INT: buffer CELL[3].OUT_BEL[11] ← CELL[0].IMUX_BUFG_O[20] - SPEC_INT: buffer CELL[3].OUT_BEL[10] ← CELL[0].IMUX_BUFG_O[21] -
B43 - - - -
B42 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B41 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B40 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B39 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6 -
B38 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7
B37 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8 -
B36 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9
B35 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B34 SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2 -
B28 SPEC_INT: buffer CELL[3].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[18] - SPEC_INT: buffer CELL[3].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[19] -
B27 - - - -
B26 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B25 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B24 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B23 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6 -
B22 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7
B21 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8 -
B20 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9
B19 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B18 SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2 -
B12 SPEC_INT: buffer CELL[3].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[16] - SPEC_INT: buffer CELL[3].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[17] -
B11 - - - -
B10 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B9 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B8 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B7 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6 -
B6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7
B5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8 -
B4 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9
B3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B2 SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[4]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2 -
B60 SPEC_INT: buffer CELL[4].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[30] - SPEC_INT: buffer CELL[4].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[31] -
B59 - - - -
B58 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B57 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B56 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B55 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6 -
B54 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7
B53 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8 -
B52 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9
B51 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B50 SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2 -
B44 SPEC_INT: buffer CELL[4].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[28] - SPEC_INT: buffer CELL[4].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[29] -
B43 - - - -
B42 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B41 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B40 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B39 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6 -
B38 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7
B37 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8 -
B36 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9
B35 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B34 SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2 -
B28 SPEC_INT: buffer CELL[4].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[26] - SPEC_INT: buffer CELL[4].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[27] -
B27 - - - -
B26 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B25 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B24 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B23 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6 -
B22 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7
B21 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8 -
B20 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9
B19 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B18 SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2 -
B12 SPEC_INT: buffer CELL[4].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[24] - SPEC_INT: buffer CELL[4].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[25] -
B11 - - - -
B10 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B9 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B8 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B7 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6 -
B6 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7
B5 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8 -
B4 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9
B3 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11 SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B2 SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12 - SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[5]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[6]
BitFrame
F0 F1 F2 F3
B63 BUFGCTRL[14]: INIT_OUT bit 0 BUFGCTRL[14]: !invert S0 BUFGCTRL[15]: INIT_OUT bit 0 BUFGCTRL[15]: !invert S0
B62 - - - -
B61 BUFGCTRL[14]: !invert IGNORE0 BUFGCTRL[14]: !invert CE0 BUFGCTRL[15]: !invert IGNORE0 BUFGCTRL[15]: !invert CE0
B60 - BUFGCTRL[14]: PRESELECT_I0 - BUFGCTRL[15]: PRESELECT_I0
B59 - BUFGCTRL[14]: PRESELECT_I1 - BUFGCTRL[15]: PRESELECT_I1
B58 BUFGCTRL[14]: !invert IGNORE1 BUFGCTRL[14]: !invert CE1 BUFGCTRL[15]: !invert IGNORE1 BUFGCTRL[15]: !invert CE1
B57 - BUFGCTRL[14]: ! CREATE_EDGE - BUFGCTRL[15]: ! CREATE_EDGE
B56 - BUFGCTRL[14]: !invert S1 - BUFGCTRL[15]: !invert S1
B55 BUFGCTRL[12]: INIT_OUT bit 0 BUFGCTRL[12]: !invert S0 BUFGCTRL[13]: INIT_OUT bit 0 BUFGCTRL[13]: !invert S0
B54 - - - -
B53 BUFGCTRL[12]: !invert IGNORE0 BUFGCTRL[12]: !invert CE0 BUFGCTRL[13]: !invert IGNORE0 BUFGCTRL[13]: !invert CE0
B52 - BUFGCTRL[12]: PRESELECT_I0 - BUFGCTRL[13]: PRESELECT_I0
B51 - BUFGCTRL[12]: PRESELECT_I1 - BUFGCTRL[13]: PRESELECT_I1
B50 BUFGCTRL[12]: !invert IGNORE1 BUFGCTRL[12]: !invert CE1 BUFGCTRL[13]: !invert IGNORE1 BUFGCTRL[13]: !invert CE1
B49 - BUFGCTRL[12]: ! CREATE_EDGE - BUFGCTRL[13]: ! CREATE_EDGE
B48 - BUFGCTRL[12]: !invert S1 - BUFGCTRL[13]: !invert S1
B47 BUFGCTRL[10]: INIT_OUT bit 0 BUFGCTRL[10]: !invert S0 BUFGCTRL[11]: INIT_OUT bit 0 BUFGCTRL[11]: !invert S0
B46 - - - -
B45 BUFGCTRL[10]: !invert IGNORE0 BUFGCTRL[10]: !invert CE0 BUFGCTRL[11]: !invert IGNORE0 BUFGCTRL[11]: !invert CE0
B44 - BUFGCTRL[10]: PRESELECT_I0 - BUFGCTRL[11]: PRESELECT_I0
B43 - BUFGCTRL[10]: PRESELECT_I1 - BUFGCTRL[11]: PRESELECT_I1
B42 BUFGCTRL[10]: !invert IGNORE1 BUFGCTRL[10]: !invert CE1 BUFGCTRL[11]: !invert IGNORE1 BUFGCTRL[11]: !invert CE1
B41 - BUFGCTRL[10]: ! CREATE_EDGE - BUFGCTRL[11]: ! CREATE_EDGE
B40 - BUFGCTRL[10]: !invert S1 - BUFGCTRL[11]: !invert S1
B39 BUFGCTRL[8]: INIT_OUT bit 0 BUFGCTRL[8]: !invert S0 BUFGCTRL[9]: INIT_OUT bit 0 BUFGCTRL[9]: !invert S0
B38 - - - -
B37 BUFGCTRL[8]: !invert IGNORE0 BUFGCTRL[8]: !invert CE0 BUFGCTRL[9]: !invert IGNORE0 BUFGCTRL[9]: !invert CE0
B36 - BUFGCTRL[8]: PRESELECT_I0 - BUFGCTRL[9]: PRESELECT_I0
B35 - BUFGCTRL[8]: PRESELECT_I1 - BUFGCTRL[9]: PRESELECT_I1
B34 BUFGCTRL[8]: !invert IGNORE1 BUFGCTRL[8]: !invert CE1 BUFGCTRL[9]: !invert IGNORE1 BUFGCTRL[9]: !invert CE1
B33 - BUFGCTRL[8]: ! CREATE_EDGE - BUFGCTRL[9]: ! CREATE_EDGE
B32 - BUFGCTRL[8]: !invert S1 - BUFGCTRL[9]: !invert S1
B31 BUFGCTRL[6]: INIT_OUT bit 0 BUFGCTRL[6]: !invert S0 BUFGCTRL[7]: INIT_OUT bit 0 BUFGCTRL[7]: !invert S0
B30 - - - -
B29 BUFGCTRL[6]: !invert IGNORE0 BUFGCTRL[6]: !invert CE0 BUFGCTRL[7]: !invert IGNORE0 BUFGCTRL[7]: !invert CE0
B28 - BUFGCTRL[6]: PRESELECT_I0 - BUFGCTRL[7]: PRESELECT_I0
B27 - BUFGCTRL[6]: PRESELECT_I1 - BUFGCTRL[7]: PRESELECT_I1
B26 BUFGCTRL[6]: !invert IGNORE1 BUFGCTRL[6]: !invert CE1 BUFGCTRL[7]: !invert IGNORE1 BUFGCTRL[7]: !invert CE1
B25 - BUFGCTRL[6]: ! CREATE_EDGE - BUFGCTRL[7]: ! CREATE_EDGE
B24 - BUFGCTRL[6]: !invert S1 - BUFGCTRL[7]: !invert S1
B23 BUFGCTRL[4]: INIT_OUT bit 0 BUFGCTRL[4]: !invert S0 BUFGCTRL[5]: INIT_OUT bit 0 BUFGCTRL[5]: !invert S0
B22 - - - -
B21 BUFGCTRL[4]: !invert IGNORE0 BUFGCTRL[4]: !invert CE0 BUFGCTRL[5]: !invert IGNORE0 BUFGCTRL[5]: !invert CE0
B20 - BUFGCTRL[4]: PRESELECT_I0 - BUFGCTRL[5]: PRESELECT_I0
B19 - BUFGCTRL[4]: PRESELECT_I1 - BUFGCTRL[5]: PRESELECT_I1
B18 BUFGCTRL[4]: !invert IGNORE1 BUFGCTRL[4]: !invert CE1 BUFGCTRL[5]: !invert IGNORE1 BUFGCTRL[5]: !invert CE1
B17 - BUFGCTRL[4]: ! CREATE_EDGE - BUFGCTRL[5]: ! CREATE_EDGE
B16 - BUFGCTRL[4]: !invert S1 - BUFGCTRL[5]: !invert S1
B15 BUFGCTRL[2]: INIT_OUT bit 0 BUFGCTRL[2]: !invert S0 BUFGCTRL[3]: INIT_OUT bit 0 BUFGCTRL[3]: !invert S0
B14 - - - -
B13 BUFGCTRL[2]: !invert IGNORE0 BUFGCTRL[2]: !invert CE0 BUFGCTRL[3]: !invert IGNORE0 BUFGCTRL[3]: !invert CE0
B12 - BUFGCTRL[2]: PRESELECT_I0 - BUFGCTRL[3]: PRESELECT_I0
B11 - BUFGCTRL[2]: PRESELECT_I1 - BUFGCTRL[3]: PRESELECT_I1
B10 BUFGCTRL[2]: !invert IGNORE1 BUFGCTRL[2]: !invert CE1 BUFGCTRL[3]: !invert IGNORE1 BUFGCTRL[3]: !invert CE1
B9 - BUFGCTRL[2]: ! CREATE_EDGE - BUFGCTRL[3]: ! CREATE_EDGE
B8 - BUFGCTRL[2]: !invert S1 - BUFGCTRL[3]: !invert S1
B7 BUFGCTRL[0]: INIT_OUT bit 0 BUFGCTRL[0]: !invert S0 BUFGCTRL[1]: INIT_OUT bit 0 BUFGCTRL[1]: !invert S0
B6 - - - -
B5 BUFGCTRL[0]: !invert IGNORE0 BUFGCTRL[0]: !invert CE0 BUFGCTRL[1]: !invert IGNORE0 BUFGCTRL[1]: !invert CE0
B4 - BUFGCTRL[0]: PRESELECT_I0 - BUFGCTRL[1]: PRESELECT_I0
B3 - BUFGCTRL[0]: PRESELECT_I1 - BUFGCTRL[1]: PRESELECT_I1
B2 BUFGCTRL[0]: !invert IGNORE1 BUFGCTRL[0]: !invert CE1 BUFGCTRL[1]: !invert IGNORE1 BUFGCTRL[1]: !invert CE1
B1 - BUFGCTRL[0]: ! CREATE_EDGE - BUFGCTRL[1]: ! CREATE_EDGE
B0 - BUFGCTRL[0]: !invert S1 - BUFGCTRL[1]: !invert S1
virtex5 CLK_BUFG rect MAIN[7]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[8]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[9]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[10]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[11]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[12]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[13]
BitFrame
F0 F1 F2 F3
B63 - BUFGCTRL[16]: !invert S1 - BUFGCTRL[17]: !invert S1
B62 - BUFGCTRL[16]: ! CREATE_EDGE - BUFGCTRL[17]: ! CREATE_EDGE
B61 BUFGCTRL[16]: !invert IGNORE1 BUFGCTRL[16]: !invert CE1 BUFGCTRL[17]: !invert IGNORE1 BUFGCTRL[17]: !invert CE1
B60 - BUFGCTRL[16]: PRESELECT_I1 - BUFGCTRL[17]: PRESELECT_I1
B59 - BUFGCTRL[16]: PRESELECT_I0 - BUFGCTRL[17]: PRESELECT_I0
B58 BUFGCTRL[16]: !invert IGNORE0 BUFGCTRL[16]: !invert CE0 BUFGCTRL[17]: !invert IGNORE0 BUFGCTRL[17]: !invert CE0
B57 - - - -
B56 BUFGCTRL[16]: INIT_OUT bit 0 BUFGCTRL[16]: !invert S0 BUFGCTRL[17]: INIT_OUT bit 0 BUFGCTRL[17]: !invert S0
B55 - BUFGCTRL[18]: !invert S1 - BUFGCTRL[19]: !invert S1
B54 - BUFGCTRL[18]: ! CREATE_EDGE - BUFGCTRL[19]: ! CREATE_EDGE
B53 BUFGCTRL[18]: !invert IGNORE1 BUFGCTRL[18]: !invert CE1 BUFGCTRL[19]: !invert IGNORE1 BUFGCTRL[19]: !invert CE1
B52 - BUFGCTRL[18]: PRESELECT_I1 - BUFGCTRL[19]: PRESELECT_I1
B51 - BUFGCTRL[18]: PRESELECT_I0 - BUFGCTRL[19]: PRESELECT_I0
B50 BUFGCTRL[18]: !invert IGNORE0 BUFGCTRL[18]: !invert CE0 BUFGCTRL[19]: !invert IGNORE0 BUFGCTRL[19]: !invert CE0
B49 - - - -
B48 BUFGCTRL[18]: INIT_OUT bit 0 BUFGCTRL[18]: !invert S0 BUFGCTRL[19]: INIT_OUT bit 0 BUFGCTRL[19]: !invert S0
B47 - BUFGCTRL[20]: !invert S1 - BUFGCTRL[21]: !invert S1
B46 - BUFGCTRL[20]: ! CREATE_EDGE - BUFGCTRL[21]: ! CREATE_EDGE
B45 BUFGCTRL[20]: !invert IGNORE1 BUFGCTRL[20]: !invert CE1 BUFGCTRL[21]: !invert IGNORE1 BUFGCTRL[21]: !invert CE1
B44 - BUFGCTRL[20]: PRESELECT_I1 - BUFGCTRL[21]: PRESELECT_I1
B43 - BUFGCTRL[20]: PRESELECT_I0 - BUFGCTRL[21]: PRESELECT_I0
B42 BUFGCTRL[20]: !invert IGNORE0 BUFGCTRL[20]: !invert CE0 BUFGCTRL[21]: !invert IGNORE0 BUFGCTRL[21]: !invert CE0
B41 - - - -
B40 BUFGCTRL[20]: INIT_OUT bit 0 BUFGCTRL[20]: !invert S0 BUFGCTRL[21]: INIT_OUT bit 0 BUFGCTRL[21]: !invert S0
B39 - BUFGCTRL[22]: !invert S1 - BUFGCTRL[23]: !invert S1
B38 - BUFGCTRL[22]: ! CREATE_EDGE - BUFGCTRL[23]: ! CREATE_EDGE
B37 BUFGCTRL[22]: !invert IGNORE1 BUFGCTRL[22]: !invert CE1 BUFGCTRL[23]: !invert IGNORE1 BUFGCTRL[23]: !invert CE1
B36 - BUFGCTRL[22]: PRESELECT_I1 - BUFGCTRL[23]: PRESELECT_I1
B35 - BUFGCTRL[22]: PRESELECT_I0 - BUFGCTRL[23]: PRESELECT_I0
B34 BUFGCTRL[22]: !invert IGNORE0 BUFGCTRL[22]: !invert CE0 BUFGCTRL[23]: !invert IGNORE0 BUFGCTRL[23]: !invert CE0
B33 - - - -
B32 BUFGCTRL[22]: INIT_OUT bit 0 BUFGCTRL[22]: !invert S0 BUFGCTRL[23]: INIT_OUT bit 0 BUFGCTRL[23]: !invert S0
B31 - BUFGCTRL[24]: !invert S1 - BUFGCTRL[25]: !invert S1
B30 - BUFGCTRL[24]: ! CREATE_EDGE - BUFGCTRL[25]: ! CREATE_EDGE
B29 BUFGCTRL[24]: !invert IGNORE1 BUFGCTRL[24]: !invert CE1 BUFGCTRL[25]: !invert IGNORE1 BUFGCTRL[25]: !invert CE1
B28 - BUFGCTRL[24]: PRESELECT_I1 - BUFGCTRL[25]: PRESELECT_I1
B27 - BUFGCTRL[24]: PRESELECT_I0 - BUFGCTRL[25]: PRESELECT_I0
B26 BUFGCTRL[24]: !invert IGNORE0 BUFGCTRL[24]: !invert CE0 BUFGCTRL[25]: !invert IGNORE0 BUFGCTRL[25]: !invert CE0
B25 - - - -
B24 BUFGCTRL[24]: INIT_OUT bit 0 BUFGCTRL[24]: !invert S0 BUFGCTRL[25]: INIT_OUT bit 0 BUFGCTRL[25]: !invert S0
B23 - BUFGCTRL[26]: !invert S1 - BUFGCTRL[27]: !invert S1
B22 - BUFGCTRL[26]: ! CREATE_EDGE - BUFGCTRL[27]: ! CREATE_EDGE
B21 BUFGCTRL[26]: !invert IGNORE1 BUFGCTRL[26]: !invert CE1 BUFGCTRL[27]: !invert IGNORE1 BUFGCTRL[27]: !invert CE1
B20 - BUFGCTRL[26]: PRESELECT_I1 - BUFGCTRL[27]: PRESELECT_I1
B19 - BUFGCTRL[26]: PRESELECT_I0 - BUFGCTRL[27]: PRESELECT_I0
B18 BUFGCTRL[26]: !invert IGNORE0 BUFGCTRL[26]: !invert CE0 BUFGCTRL[27]: !invert IGNORE0 BUFGCTRL[27]: !invert CE0
B17 - - - -
B16 BUFGCTRL[26]: INIT_OUT bit 0 BUFGCTRL[26]: !invert S0 BUFGCTRL[27]: INIT_OUT bit 0 BUFGCTRL[27]: !invert S0
B15 - BUFGCTRL[28]: !invert S1 - BUFGCTRL[29]: !invert S1
B14 - BUFGCTRL[28]: ! CREATE_EDGE - BUFGCTRL[29]: ! CREATE_EDGE
B13 BUFGCTRL[28]: !invert IGNORE1 BUFGCTRL[28]: !invert CE1 BUFGCTRL[29]: !invert IGNORE1 BUFGCTRL[29]: !invert CE1
B12 - BUFGCTRL[28]: PRESELECT_I1 - BUFGCTRL[29]: PRESELECT_I1
B11 - BUFGCTRL[28]: PRESELECT_I0 - BUFGCTRL[29]: PRESELECT_I0
B10 BUFGCTRL[28]: !invert IGNORE0 BUFGCTRL[28]: !invert CE0 BUFGCTRL[29]: !invert IGNORE0 BUFGCTRL[29]: !invert CE0
B9 - - - -
B8 BUFGCTRL[28]: INIT_OUT bit 0 BUFGCTRL[28]: !invert S0 BUFGCTRL[29]: INIT_OUT bit 0 BUFGCTRL[29]: !invert S0
B7 - BUFGCTRL[30]: !invert S1 - BUFGCTRL[31]: !invert S1
B6 - BUFGCTRL[30]: ! CREATE_EDGE - BUFGCTRL[31]: ! CREATE_EDGE
B5 BUFGCTRL[30]: !invert IGNORE1 BUFGCTRL[30]: !invert CE1 BUFGCTRL[31]: !invert IGNORE1 BUFGCTRL[31]: !invert CE1
B4 - BUFGCTRL[30]: PRESELECT_I1 - BUFGCTRL[31]: PRESELECT_I1
B3 - BUFGCTRL[30]: PRESELECT_I0 - BUFGCTRL[31]: PRESELECT_I0
B2 BUFGCTRL[30]: !invert IGNORE0 BUFGCTRL[30]: !invert CE0 BUFGCTRL[31]: !invert IGNORE0 BUFGCTRL[31]: !invert CE0
B1 - - - -
B0 BUFGCTRL[30]: INIT_OUT bit 0 BUFGCTRL[30]: !invert S0 BUFGCTRL[31]: INIT_OUT bit 0 BUFGCTRL[31]: !invert S0
virtex5 CLK_BUFG rect MAIN[14]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[15]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 12 -
B60 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 10
B59 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 9
B58 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 8 -
B57 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 7
B56 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 6 -
B55 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 5
B54 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 4
B53 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 1
B52 - - - -
B51 SPEC_INT: buffer CELL[15].OUT_BEL[5] ← CELL[10].IMUX_BUFG_O[24] - SPEC_INT: buffer CELL[15].OUT_BEL[4] ← CELL[10].IMUX_BUFG_O[25] -
B50 SPEC_INT: mux CELL[10].IMUX_BUFG_O[24] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[25] bit 2 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 12 -
B44 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 10
B43 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 9
B42 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 8 -
B41 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 7
B40 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 6 -
B39 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 5
B38 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 4
B37 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 1
B36 - - - -
B35 SPEC_INT: buffer CELL[15].OUT_BEL[7] ← CELL[10].IMUX_BUFG_O[26] - SPEC_INT: buffer CELL[15].OUT_BEL[6] ← CELL[10].IMUX_BUFG_O[27] -
B34 SPEC_INT: mux CELL[10].IMUX_BUFG_O[26] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[27] bit 2 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 12 -
B28 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 10
B27 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 9
B26 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 8 -
B25 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 7
B24 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 6 -
B23 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 5
B22 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 4
B21 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 1
B20 - - - -
B19 SPEC_INT: buffer CELL[15].OUT_BEL[1] ← CELL[10].IMUX_BUFG_O[28] - SPEC_INT: buffer CELL[15].OUT_BEL[0] ← CELL[10].IMUX_BUFG_O[29] -
B18 SPEC_INT: mux CELL[10].IMUX_BUFG_O[28] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[29] bit 2 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 12 -
B12 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 10
B11 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 9
B10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 8 -
B9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 7
B8 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 6 -
B7 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 5
B6 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 4
B5 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 1
B4 - - - -
B3 SPEC_INT: buffer CELL[15].OUT_BEL[3] ← CELL[10].IMUX_BUFG_O[30] - SPEC_INT: buffer CELL[15].OUT_BEL[2] ← CELL[10].IMUX_BUFG_O[31] -
B2 SPEC_INT: mux CELL[10].IMUX_BUFG_O[30] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[31] bit 2 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[16]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 12 -
B60 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 10
B59 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 9
B58 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 8 -
B57 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 7
B56 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 6 -
B55 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 5
B54 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 4
B53 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 1
B52 - - - -
B51 SPEC_INT: buffer CELL[16].OUT_BEL[1] ← CELL[10].IMUX_BUFG_O[16] - SPEC_INT: buffer CELL[16].OUT_BEL[0] ← CELL[10].IMUX_BUFG_O[17] -
B50 SPEC_INT: mux CELL[10].IMUX_BUFG_O[16] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[17] bit 2 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 12 -
B44 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 10
B43 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 9
B42 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 8 -
B41 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 7
B40 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 6 -
B39 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 5
B38 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 4
B37 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 1
B36 - - - -
B35 SPEC_INT: buffer CELL[16].OUT_BEL[3] ← CELL[10].IMUX_BUFG_O[18] - SPEC_INT: buffer CELL[16].OUT_BEL[2] ← CELL[10].IMUX_BUFG_O[19] -
B34 SPEC_INT: mux CELL[10].IMUX_BUFG_O[18] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[19] bit 2 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 12 -
B28 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 10
B27 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 9
B26 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 8 -
B25 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 7
B24 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 6 -
B23 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 5
B22 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 4
B21 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 1
B20 - - - -
B19 SPEC_INT: buffer CELL[15].OUT_BEL[9] ← CELL[10].IMUX_BUFG_O[20] - SPEC_INT: buffer CELL[15].OUT_BEL[8] ← CELL[10].IMUX_BUFG_O[21] -
B18 SPEC_INT: mux CELL[10].IMUX_BUFG_O[20] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[21] bit 2 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 12 -
B12 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 10
B11 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 9
B10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 8 -
B9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 7
B8 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 6 -
B7 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 5
B6 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 4
B5 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 1
B4 - - - -
B3 SPEC_INT: buffer CELL[15].OUT_BEL[11] ← CELL[10].IMUX_BUFG_O[22] - SPEC_INT: buffer CELL[15].OUT_BEL[10] ← CELL[10].IMUX_BUFG_O[23] -
B2 SPEC_INT: mux CELL[10].IMUX_BUFG_O[22] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[23] bit 2 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[17]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 12 -
B60 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 10
B59 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 9
B58 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 8 -
B57 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 7
B56 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 6 -
B55 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 5
B54 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 4
B53 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 1
B52 - - - -
B51 SPEC_INT: buffer CELL[16].OUT_BEL[9] ← CELL[10].IMUX_BUFG_O[8] - SPEC_INT: buffer CELL[16].OUT_BEL[8] ← CELL[10].IMUX_BUFG_O[9] -
B50 SPEC_INT: mux CELL[10].IMUX_BUFG_O[8] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[9] bit 2 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 12 -
B44 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 10
B43 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 9
B42 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 8 -
B41 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 7
B40 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 6 -
B39 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 5
B38 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 4
B37 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 1
B36 - - - -
B35 SPEC_INT: buffer CELL[16].OUT_BEL[11] ← CELL[10].IMUX_BUFG_O[10] - SPEC_INT: buffer CELL[16].OUT_BEL[10] ← CELL[10].IMUX_BUFG_O[11] -
B34 SPEC_INT: mux CELL[10].IMUX_BUFG_O[10] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[11] bit 2 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 12 -
B28 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 10
B27 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 9
B26 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 8 -
B25 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 7
B24 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 6 -
B23 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 5
B22 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 4
B21 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 1
B20 - - - -
B19 SPEC_INT: buffer CELL[16].OUT_BEL[5] ← CELL[10].IMUX_BUFG_O[12] - SPEC_INT: buffer CELL[16].OUT_BEL[4] ← CELL[10].IMUX_BUFG_O[13] -
B18 SPEC_INT: mux CELL[10].IMUX_BUFG_O[12] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[13] bit 2 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 12 -
B12 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 10
B11 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 9
B10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 8 -
B9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 7
B8 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 6 -
B7 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 5
B6 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 4
B5 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 1
B4 - - - -
B3 SPEC_INT: buffer CELL[16].OUT_BEL[7] ← CELL[10].IMUX_BUFG_O[14] - SPEC_INT: buffer CELL[16].OUT_BEL[6] ← CELL[10].IMUX_BUFG_O[15] -
B2 SPEC_INT: mux CELL[10].IMUX_BUFG_O[14] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[15] bit 2 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[18]
BitFrame
F0 F1 F2 F3
B63 SPEC_INT: buffer CELL[10].MGT_BUF[1] ← CELL[10].MGT_ROW_I[1] SPEC_INT: buffer CELL[10].MGT_BUF[0] ← CELL[10].MGT_ROW_I[0] SPEC_INT: buffer CELL[10].MGT_BUF[6] ← CELL_E10.MGT_ROW_I[1] SPEC_INT: buffer CELL[10].MGT_BUF[5] ← CELL_E10.MGT_ROW_I[0]
B62 SPEC_INT: buffer CELL[10].MGT_BUF[2] ← CELL[10].MGT_ROW_I[2] SPEC_INT: buffer CELL[10].MGT_BUF[3] ← CELL[10].MGT_ROW_I[3] SPEC_INT: buffer CELL[10].MGT_BUF[7] ← CELL_E10.MGT_ROW_I[2] SPEC_INT: buffer CELL[10].MGT_BUF[8] ← CELL_E10.MGT_ROW_I[3]
B61 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 12 SPEC_INT: buffer CELL[10].MGT_BUF[4] ← CELL[10].MGT_ROW_I[4] SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 12 SPEC_INT: buffer CELL[10].MGT_BUF[9] ← CELL_E10.MGT_ROW_I[4]
B60 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 10
B59 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 9
B58 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 8 -
B57 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 7
B56 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 6 -
B55 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 5
B54 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 4
B53 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 1
B52 - - - -
B51 SPEC_INT: buffer CELL[17].OUT_BEL[5] ← CELL[10].IMUX_BUFG_O[0] - SPEC_INT: buffer CELL[17].OUT_BEL[4] ← CELL[10].IMUX_BUFG_O[1] -
B50 SPEC_INT: mux CELL[10].IMUX_BUFG_O[0] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[1] bit 2 -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 12 -
B44 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 10
B43 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 9
B42 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 8 -
B41 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 7
B40 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 6 -
B39 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 5
B38 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 4
B37 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 1
B36 - - - -
B35 SPEC_INT: buffer CELL[17].OUT_BEL[7] ← CELL[10].IMUX_BUFG_O[2] - SPEC_INT: buffer CELL[17].OUT_BEL[6] ← CELL[10].IMUX_BUFG_O[3] -
B34 SPEC_INT: mux CELL[10].IMUX_BUFG_O[2] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[3] bit 2 -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 12 -
B28 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 10
B27 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 9
B26 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 8 -
B25 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 7
B24 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 6 -
B23 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 5
B22 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 4
B21 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 1
B20 - - - -
B19 SPEC_INT: buffer CELL[17].OUT_BEL[1] ← CELL[10].IMUX_BUFG_O[4] - SPEC_INT: buffer CELL[17].OUT_BEL[0] ← CELL[10].IMUX_BUFG_O[5] -
B18 SPEC_INT: mux CELL[10].IMUX_BUFG_O[4] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[5] bit 2 -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 12 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 12 -
B12 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 11 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 10
B11 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 9
B10 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 8 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 8 -
B9 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 7 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 7
B8 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 6 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 6 -
B7 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 5 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 0 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 5
B6 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 4 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 3 SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 4
B5 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 1 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 1
B4 - - - -
B3 SPEC_INT: buffer CELL[17].OUT_BEL[3] ← CELL[10].IMUX_BUFG_O[6] - SPEC_INT: buffer CELL[17].OUT_BEL[2] ← CELL[10].IMUX_BUFG_O[7] -
B2 SPEC_INT: mux CELL[10].IMUX_BUFG_O[6] bit 2 - SPEC_INT: mux CELL[10].IMUX_BUFG_O[7] bit 2 -
B1 - - - -
B0 - - - -
virtex5 CLK_BUFG rect MAIN[19]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 - - - -
B60 - - - -
B59 - - - -
B58 - - - -
B57 - - - -
B56 - - - -
B55 - - - -
B54 - - - -
B53 - - - -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 - - - -
B46 - - - -
B45 - - - -
B44 - - - -
B43 - - - -
B42 - - - -
B41 - - - -
B40 - - - -
B39 - - - -
B38 - - - -
B37 - - - -
B36 - - - -
B35 - - - -
B34 - - - -
B33 - - - -
B32 - - - -
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 - - - -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -