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Clock row buffers

Tile CLK_HROW

Cells: 2

Switchbox HROW_INT

virtex5 CLK_HROW switchbox HROW_INT programmable buffers
DestinationSourceBit
W.GCLK_BUF[0]W.GCLK[0]MAIN[1][2][13]
W.GCLK_BUF[1]W.GCLK[1]MAIN[1][3][13]
W.GCLK_BUF[2]W.GCLK[2]HCLK[2][15]
W.GCLK_BUF[3]W.GCLK[3]HCLK[3][15]
W.GCLK_BUF[4]W.GCLK[4]HCLK[2][12]
W.GCLK_BUF[5]W.GCLK[5]HCLK[3][12]
W.GCLK_BUF[6]W.GCLK[6]MAIN[0][2][51]
W.GCLK_BUF[7]W.GCLK[7]MAIN[0][3][51]
W.GCLK_BUF[8]W.GCLK[8]MAIN[1][1][12]
W.GCLK_BUF[9]W.GCLK[9]MAIN[1][0][12]
W.GCLK_BUF[10]W.GCLK[10]HCLK[0][14]
W.GCLK_BUF[11]W.GCLK[11]HCLK[1][14]
W.GCLK_BUF[12]W.GCLK[12]HCLK[0][13]
W.GCLK_BUF[13]W.GCLK[13]HCLK[1][13]
W.GCLK_BUF[14]W.GCLK[14]MAIN[0][1][50]
W.GCLK_BUF[15]W.GCLK[15]MAIN[0][0][50]
W.GCLK_BUF[16]W.GCLK[16]MAIN[1][2][12]
W.GCLK_BUF[17]W.GCLK[17]MAIN[1][3][12]
W.GCLK_BUF[18]W.GCLK[18]HCLK[3][14]
W.GCLK_BUF[19]W.GCLK[19]HCLK[2][14]
W.GCLK_BUF[20]W.GCLK[20]HCLK[3][13]
W.GCLK_BUF[21]W.GCLK[21]HCLK[2][13]
W.GCLK_BUF[22]W.GCLK[22]MAIN[0][2][50]
W.GCLK_BUF[23]W.GCLK[23]MAIN[0][3][50]
W.GCLK_BUF[24]W.GCLK[24]MAIN[1][1][13]
W.GCLK_BUF[25]W.GCLK[25]MAIN[1][0][13]
W.GCLK_BUF[26]W.GCLK[26]HCLK[1][15]
W.GCLK_BUF[27]W.GCLK[27]HCLK[0][15]
W.GCLK_BUF[28]W.GCLK[28]HCLK[1][12]
W.GCLK_BUF[29]W.GCLK[29]HCLK[0][12]
W.GCLK_BUF[30]W.GCLK[30]MAIN[0][1][51]
W.GCLK_BUF[31]W.GCLK[31]MAIN[0][0][51]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[0]
BitsDestination
MAIN[1][0][7]MAIN[1][1][7]MAIN[1][0][8]MAIN[1][0][9]MAIN[1][0][1]MAIN[1][1][2]MAIN[1][1][3]MAIN[1][0][4]MAIN[1][0][5]MAIN[1][1][5]MAIN[1][1][6]MAIN[1][0][6]W.HCLK_ROW[0]
MAIN[1][2][7]MAIN[1][3][7]MAIN[1][2][8]MAIN[1][2][9]MAIN[1][2][1]MAIN[1][3][2]MAIN[1][3][3]MAIN[1][2][4]MAIN[1][2][5]MAIN[1][3][5]MAIN[1][3][6]MAIN[1][2][6]E.HCLK_ROW[0]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[1]
BitsDestination
MAIN[0][0][59]MAIN[0][1][59]MAIN[0][0][60]MAIN[0][0][61]MAIN[0][0][53]MAIN[0][1][54]MAIN[0][1][55]MAIN[0][0][56]MAIN[0][0][57]MAIN[0][1][57]MAIN[0][1][58]MAIN[0][0][58]W.HCLK_ROW[1]
MAIN[0][2][59]MAIN[0][3][59]MAIN[0][2][60]MAIN[0][2][61]MAIN[0][2][53]MAIN[0][3][54]MAIN[0][3][55]MAIN[0][2][56]MAIN[0][2][57]MAIN[0][3][57]MAIN[0][3][58]MAIN[0][2][58]E.HCLK_ROW[1]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[2]
BitsDestination
MAIN[1][0][21]MAIN[1][1][21]MAIN[1][0][22]MAIN[1][0][23]MAIN[1][0][15]MAIN[1][1][16]MAIN[1][1][17]MAIN[1][0][18]MAIN[1][0][19]MAIN[1][1][19]MAIN[1][1][20]MAIN[1][0][20]W.HCLK_ROW[2]
MAIN[1][2][21]MAIN[1][3][21]MAIN[1][2][22]MAIN[1][2][23]MAIN[1][2][15]MAIN[1][3][16]MAIN[1][3][17]MAIN[1][2][18]MAIN[1][2][19]MAIN[1][3][19]MAIN[1][3][20]MAIN[1][2][20]E.HCLK_ROW[2]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[3]
BitsDestination
MAIN[0][0][45]MAIN[0][1][45]MAIN[0][0][46]MAIN[0][0][47]MAIN[0][0][39]MAIN[0][1][40]MAIN[0][1][41]MAIN[0][0][42]MAIN[0][0][43]MAIN[0][1][43]MAIN[0][1][44]MAIN[0][0][44]W.HCLK_ROW[3]
MAIN[0][2][45]MAIN[0][3][45]MAIN[0][2][46]MAIN[0][2][47]MAIN[0][2][39]MAIN[0][3][40]MAIN[0][3][41]MAIN[0][2][42]MAIN[0][2][43]MAIN[0][3][43]MAIN[0][3][44]MAIN[0][2][44]E.HCLK_ROW[3]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[4]
BitsDestination
MAIN[1][0][33]MAIN[1][1][33]MAIN[1][0][34]MAIN[1][0][35]MAIN[1][0][27]MAIN[1][1][28]MAIN[1][1][29]MAIN[1][0][30]MAIN[1][0][31]MAIN[1][1][31]MAIN[1][1][32]MAIN[1][0][32]W.HCLK_ROW[4]
MAIN[1][2][33]MAIN[1][3][33]MAIN[1][2][34]MAIN[1][2][35]MAIN[1][2][27]MAIN[1][3][28]MAIN[1][3][29]MAIN[1][2][30]MAIN[1][2][31]MAIN[1][3][31]MAIN[1][3][32]MAIN[1][2][32]E.HCLK_ROW[4]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[5]
BitsDestination
MAIN[0][0][33]MAIN[0][1][33]MAIN[0][0][34]MAIN[0][0][35]MAIN[0][0][27]MAIN[0][1][28]MAIN[0][1][29]MAIN[0][0][30]MAIN[0][0][31]MAIN[0][1][31]MAIN[0][1][32]MAIN[0][0][32]W.HCLK_ROW[5]
MAIN[0][2][33]MAIN[0][3][33]MAIN[0][2][34]MAIN[0][2][35]MAIN[0][2][27]MAIN[0][3][28]MAIN[0][3][29]MAIN[0][2][30]MAIN[0][2][31]MAIN[0][3][31]MAIN[0][3][32]MAIN[0][2][32]E.HCLK_ROW[5]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[6]
BitsDestination
MAIN[1][0][45]MAIN[1][1][45]MAIN[1][0][46]MAIN[1][0][47]MAIN[1][0][39]MAIN[1][1][40]MAIN[1][1][41]MAIN[1][0][42]MAIN[1][0][43]MAIN[1][1][43]MAIN[1][1][44]MAIN[1][0][44]W.HCLK_ROW[6]
MAIN[1][2][45]MAIN[1][3][45]MAIN[1][2][46]MAIN[1][2][47]MAIN[1][2][39]MAIN[1][3][40]MAIN[1][3][41]MAIN[1][2][42]MAIN[1][2][43]MAIN[1][3][43]MAIN[1][3][44]MAIN[1][2][44]E.HCLK_ROW[6]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[7]
BitsDestination
MAIN[0][0][21]MAIN[0][1][21]MAIN[0][0][22]MAIN[0][0][23]MAIN[0][0][15]MAIN[0][1][16]MAIN[0][1][17]MAIN[0][0][18]MAIN[0][0][19]MAIN[0][1][19]MAIN[0][1][20]MAIN[0][0][20]W.HCLK_ROW[7]
MAIN[0][2][21]MAIN[0][3][21]MAIN[0][2][22]MAIN[0][2][23]MAIN[0][2][15]MAIN[0][3][16]MAIN[0][3][17]MAIN[0][2][18]MAIN[0][2][19]MAIN[0][3][19]MAIN[0][3][20]MAIN[0][2][20]E.HCLK_ROW[7]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[8]
BitsDestination
MAIN[1][0][59]MAIN[1][1][59]MAIN[1][0][60]MAIN[1][0][61]MAIN[1][0][53]MAIN[1][1][54]MAIN[1][1][55]MAIN[1][0][56]MAIN[1][0][57]MAIN[1][1][57]MAIN[1][1][58]MAIN[1][0][58]W.HCLK_ROW[8]
MAIN[1][2][59]MAIN[1][3][59]MAIN[1][2][60]MAIN[1][2][61]MAIN[1][2][53]MAIN[1][3][54]MAIN[1][3][55]MAIN[1][2][56]MAIN[1][2][57]MAIN[1][3][57]MAIN[1][3][58]MAIN[1][2][58]E.HCLK_ROW[8]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]
virtex5 CLK_HROW switchbox HROW_INT muxes HCLK_ROW[9]
BitsDestination
MAIN[0][0][7]MAIN[0][1][7]MAIN[0][0][8]MAIN[0][0][9]MAIN[0][0][1]MAIN[0][1][2]MAIN[0][1][3]MAIN[0][0][4]MAIN[0][0][5]MAIN[0][1][5]MAIN[0][1][6]MAIN[0][0][6]W.HCLK_ROW[9]
MAIN[0][2][7]MAIN[0][3][7]MAIN[0][2][8]MAIN[0][2][9]MAIN[0][2][1]MAIN[0][3][2]MAIN[0][3][3]MAIN[0][2][4]MAIN[0][2][5]MAIN[0][3][5]MAIN[0][3][6]MAIN[0][2][6]E.HCLK_ROW[9]
Source
000000000000off
000100000001W.GCLK_BUF[0]
000100000010W.GCLK_BUF[1]
000100000100W.GCLK_BUF[2]
000100001000W.GCLK_BUF[3]
000100010000W.GCLK_BUF[4]
000100100000W.GCLK_BUF[5]
000101000000W.GCLK_BUF[6]
000110000000W.GCLK_BUF[7]
001000000001W.GCLK_BUF[8]
001000000010W.GCLK_BUF[9]
001000000100W.GCLK_BUF[10]
001000001000W.GCLK_BUF[11]
001000010000W.GCLK_BUF[12]
001000100000W.GCLK_BUF[13]
001001000000W.GCLK_BUF[14]
001010000000W.GCLK_BUF[15]
010000000001W.GCLK_BUF[16]
010000000010W.GCLK_BUF[17]
010000000100W.GCLK_BUF[18]
010000001000W.GCLK_BUF[19]
010000010000W.GCLK_BUF[20]
010000100000W.GCLK_BUF[21]
010001000000W.GCLK_BUF[22]
010010000000W.GCLK_BUF[23]
100000000001W.GCLK_BUF[24]
100000000010W.GCLK_BUF[25]
100000000100W.GCLK_BUF[26]
100000001000W.GCLK_BUF[27]
100000010000W.GCLK_BUF[28]
100000100000W.GCLK_BUF[29]
100001000000W.GCLK_BUF[30]
100010000000W.GCLK_BUF[31]

Bitstream

virtex5 CLK_HROW rect MAIN[0]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 HROW_INT: mux W.HCLK_ROW[1] bit 8 - HROW_INT: mux E.HCLK_ROW[1] bit 8 -
B60 HROW_INT: mux W.HCLK_ROW[1] bit 9 - HROW_INT: mux E.HCLK_ROW[1] bit 9 -
B59 HROW_INT: mux W.HCLK_ROW[1] bit 11 HROW_INT: mux W.HCLK_ROW[1] bit 10 HROW_INT: mux E.HCLK_ROW[1] bit 11 HROW_INT: mux E.HCLK_ROW[1] bit 10
B58 HROW_INT: mux W.HCLK_ROW[1] bit 0 HROW_INT: mux W.HCLK_ROW[1] bit 1 HROW_INT: mux E.HCLK_ROW[1] bit 0 HROW_INT: mux E.HCLK_ROW[1] bit 1
B57 HROW_INT: mux W.HCLK_ROW[1] bit 3 HROW_INT: mux W.HCLK_ROW[1] bit 2 HROW_INT: mux E.HCLK_ROW[1] bit 3 HROW_INT: mux E.HCLK_ROW[1] bit 2
B56 HROW_INT: mux W.HCLK_ROW[1] bit 4 - HROW_INT: mux E.HCLK_ROW[1] bit 4 -
B55 - HROW_INT: mux W.HCLK_ROW[1] bit 5 - HROW_INT: mux E.HCLK_ROW[1] bit 5
B54 - HROW_INT: mux W.HCLK_ROW[1] bit 6 - HROW_INT: mux E.HCLK_ROW[1] bit 6
B53 HROW_INT: mux W.HCLK_ROW[1] bit 7 - HROW_INT: mux E.HCLK_ROW[1] bit 7 -
B52 - - - -
B51 HROW_INT: buffer W.GCLK_BUF[31] ← W.GCLK[31] HROW_INT: buffer W.GCLK_BUF[30] ← W.GCLK[30] HROW_INT: buffer W.GCLK_BUF[6] ← W.GCLK[6] HROW_INT: buffer W.GCLK_BUF[7] ← W.GCLK[7]
B50 HROW_INT: buffer W.GCLK_BUF[15] ← W.GCLK[15] HROW_INT: buffer W.GCLK_BUF[14] ← W.GCLK[14] HROW_INT: buffer W.GCLK_BUF[22] ← W.GCLK[22] HROW_INT: buffer W.GCLK_BUF[23] ← W.GCLK[23]
B49 - - - -
B48 - - - -
B47 HROW_INT: mux W.HCLK_ROW[3] bit 8 - HROW_INT: mux E.HCLK_ROW[3] bit 8 -
B46 HROW_INT: mux W.HCLK_ROW[3] bit 9 - HROW_INT: mux E.HCLK_ROW[3] bit 9 -
B45 HROW_INT: mux W.HCLK_ROW[3] bit 11 HROW_INT: mux W.HCLK_ROW[3] bit 10 HROW_INT: mux E.HCLK_ROW[3] bit 11 HROW_INT: mux E.HCLK_ROW[3] bit 10
B44 HROW_INT: mux W.HCLK_ROW[3] bit 0 HROW_INT: mux W.HCLK_ROW[3] bit 1 HROW_INT: mux E.HCLK_ROW[3] bit 0 HROW_INT: mux E.HCLK_ROW[3] bit 1
B43 HROW_INT: mux W.HCLK_ROW[3] bit 3 HROW_INT: mux W.HCLK_ROW[3] bit 2 HROW_INT: mux E.HCLK_ROW[3] bit 3 HROW_INT: mux E.HCLK_ROW[3] bit 2
B42 HROW_INT: mux W.HCLK_ROW[3] bit 4 - HROW_INT: mux E.HCLK_ROW[3] bit 4 -
B41 - HROW_INT: mux W.HCLK_ROW[3] bit 5 - HROW_INT: mux E.HCLK_ROW[3] bit 5
B40 - HROW_INT: mux W.HCLK_ROW[3] bit 6 - HROW_INT: mux E.HCLK_ROW[3] bit 6
B39 HROW_INT: mux W.HCLK_ROW[3] bit 7 - HROW_INT: mux E.HCLK_ROW[3] bit 7 -
B38 - - - -
B37 - - - -
B36 - - - -
B35 HROW_INT: mux W.HCLK_ROW[5] bit 8 - HROW_INT: mux E.HCLK_ROW[5] bit 8 -
B34 HROW_INT: mux W.HCLK_ROW[5] bit 9 - HROW_INT: mux E.HCLK_ROW[5] bit 9 -
B33 HROW_INT: mux W.HCLK_ROW[5] bit 11 HROW_INT: mux W.HCLK_ROW[5] bit 10 HROW_INT: mux E.HCLK_ROW[5] bit 11 HROW_INT: mux E.HCLK_ROW[5] bit 10
B32 HROW_INT: mux W.HCLK_ROW[5] bit 0 HROW_INT: mux W.HCLK_ROW[5] bit 1 HROW_INT: mux E.HCLK_ROW[5] bit 0 HROW_INT: mux E.HCLK_ROW[5] bit 1
B31 HROW_INT: mux W.HCLK_ROW[5] bit 3 HROW_INT: mux W.HCLK_ROW[5] bit 2 HROW_INT: mux E.HCLK_ROW[5] bit 3 HROW_INT: mux E.HCLK_ROW[5] bit 2
B30 HROW_INT: mux W.HCLK_ROW[5] bit 4 - HROW_INT: mux E.HCLK_ROW[5] bit 4 -
B29 - HROW_INT: mux W.HCLK_ROW[5] bit 5 - HROW_INT: mux E.HCLK_ROW[5] bit 5
B28 - HROW_INT: mux W.HCLK_ROW[5] bit 6 - HROW_INT: mux E.HCLK_ROW[5] bit 6
B27 HROW_INT: mux W.HCLK_ROW[5] bit 7 - HROW_INT: mux E.HCLK_ROW[5] bit 7 -
B26 - - - -
B25 - - - -
B24 - - - -
B23 HROW_INT: mux W.HCLK_ROW[7] bit 8 - HROW_INT: mux E.HCLK_ROW[7] bit 8 -
B22 HROW_INT: mux W.HCLK_ROW[7] bit 9 - HROW_INT: mux E.HCLK_ROW[7] bit 9 -
B21 HROW_INT: mux W.HCLK_ROW[7] bit 11 HROW_INT: mux W.HCLK_ROW[7] bit 10 HROW_INT: mux E.HCLK_ROW[7] bit 11 HROW_INT: mux E.HCLK_ROW[7] bit 10
B20 HROW_INT: mux W.HCLK_ROW[7] bit 0 HROW_INT: mux W.HCLK_ROW[7] bit 1 HROW_INT: mux E.HCLK_ROW[7] bit 0 HROW_INT: mux E.HCLK_ROW[7] bit 1
B19 HROW_INT: mux W.HCLK_ROW[7] bit 3 HROW_INT: mux W.HCLK_ROW[7] bit 2 HROW_INT: mux E.HCLK_ROW[7] bit 3 HROW_INT: mux E.HCLK_ROW[7] bit 2
B18 HROW_INT: mux W.HCLK_ROW[7] bit 4 - HROW_INT: mux E.HCLK_ROW[7] bit 4 -
B17 - HROW_INT: mux W.HCLK_ROW[7] bit 5 - HROW_INT: mux E.HCLK_ROW[7] bit 5
B16 - HROW_INT: mux W.HCLK_ROW[7] bit 6 - HROW_INT: mux E.HCLK_ROW[7] bit 6
B15 HROW_INT: mux W.HCLK_ROW[7] bit 7 - HROW_INT: mux E.HCLK_ROW[7] bit 7 -
B14 - - - -
B13 - - - -
B12 - - - -
B11 - - - -
B10 - - - -
B9 HROW_INT: mux W.HCLK_ROW[9] bit 8 - HROW_INT: mux E.HCLK_ROW[9] bit 8 -
B8 HROW_INT: mux W.HCLK_ROW[9] bit 9 - HROW_INT: mux E.HCLK_ROW[9] bit 9 -
B7 HROW_INT: mux W.HCLK_ROW[9] bit 11 HROW_INT: mux W.HCLK_ROW[9] bit 10 HROW_INT: mux E.HCLK_ROW[9] bit 11 HROW_INT: mux E.HCLK_ROW[9] bit 10
B6 HROW_INT: mux W.HCLK_ROW[9] bit 0 HROW_INT: mux W.HCLK_ROW[9] bit 1 HROW_INT: mux E.HCLK_ROW[9] bit 0 HROW_INT: mux E.HCLK_ROW[9] bit 1
B5 HROW_INT: mux W.HCLK_ROW[9] bit 3 HROW_INT: mux W.HCLK_ROW[9] bit 2 HROW_INT: mux E.HCLK_ROW[9] bit 3 HROW_INT: mux E.HCLK_ROW[9] bit 2
B4 HROW_INT: mux W.HCLK_ROW[9] bit 4 - HROW_INT: mux E.HCLK_ROW[9] bit 4 -
B3 - HROW_INT: mux W.HCLK_ROW[9] bit 5 - HROW_INT: mux E.HCLK_ROW[9] bit 5
B2 - HROW_INT: mux W.HCLK_ROW[9] bit 6 - HROW_INT: mux E.HCLK_ROW[9] bit 6
B1 HROW_INT: mux W.HCLK_ROW[9] bit 7 - HROW_INT: mux E.HCLK_ROW[9] bit 7 -
B0 - - - -
virtex5 CLK_HROW rect MAIN[1]
BitFrame
F0 F1 F2 F3
B63 - - - -
B62 - - - -
B61 HROW_INT: mux W.HCLK_ROW[8] bit 8 - HROW_INT: mux E.HCLK_ROW[8] bit 8 -
B60 HROW_INT: mux W.HCLK_ROW[8] bit 9 - HROW_INT: mux E.HCLK_ROW[8] bit 9 -
B59 HROW_INT: mux W.HCLK_ROW[8] bit 11 HROW_INT: mux W.HCLK_ROW[8] bit 10 HROW_INT: mux E.HCLK_ROW[8] bit 11 HROW_INT: mux E.HCLK_ROW[8] bit 10
B58 HROW_INT: mux W.HCLK_ROW[8] bit 0 HROW_INT: mux W.HCLK_ROW[8] bit 1 HROW_INT: mux E.HCLK_ROW[8] bit 0 HROW_INT: mux E.HCLK_ROW[8] bit 1
B57 HROW_INT: mux W.HCLK_ROW[8] bit 3 HROW_INT: mux W.HCLK_ROW[8] bit 2 HROW_INT: mux E.HCLK_ROW[8] bit 3 HROW_INT: mux E.HCLK_ROW[8] bit 2
B56 HROW_INT: mux W.HCLK_ROW[8] bit 4 - HROW_INT: mux E.HCLK_ROW[8] bit 4 -
B55 - HROW_INT: mux W.HCLK_ROW[8] bit 5 - HROW_INT: mux E.HCLK_ROW[8] bit 5
B54 - HROW_INT: mux W.HCLK_ROW[8] bit 6 - HROW_INT: mux E.HCLK_ROW[8] bit 6
B53 HROW_INT: mux W.HCLK_ROW[8] bit 7 - HROW_INT: mux E.HCLK_ROW[8] bit 7 -
B52 - - - -
B51 - - - -
B50 - - - -
B49 - - - -
B48 - - - -
B47 HROW_INT: mux W.HCLK_ROW[6] bit 8 - HROW_INT: mux E.HCLK_ROW[6] bit 8 -
B46 HROW_INT: mux W.HCLK_ROW[6] bit 9 - HROW_INT: mux E.HCLK_ROW[6] bit 9 -
B45 HROW_INT: mux W.HCLK_ROW[6] bit 11 HROW_INT: mux W.HCLK_ROW[6] bit 10 HROW_INT: mux E.HCLK_ROW[6] bit 11 HROW_INT: mux E.HCLK_ROW[6] bit 10
B44 HROW_INT: mux W.HCLK_ROW[6] bit 0 HROW_INT: mux W.HCLK_ROW[6] bit 1 HROW_INT: mux E.HCLK_ROW[6] bit 0 HROW_INT: mux E.HCLK_ROW[6] bit 1
B43 HROW_INT: mux W.HCLK_ROW[6] bit 3 HROW_INT: mux W.HCLK_ROW[6] bit 2 HROW_INT: mux E.HCLK_ROW[6] bit 3 HROW_INT: mux E.HCLK_ROW[6] bit 2
B42 HROW_INT: mux W.HCLK_ROW[6] bit 4 - HROW_INT: mux E.HCLK_ROW[6] bit 4 -
B41 - HROW_INT: mux W.HCLK_ROW[6] bit 5 - HROW_INT: mux E.HCLK_ROW[6] bit 5
B40 - HROW_INT: mux W.HCLK_ROW[6] bit 6 - HROW_INT: mux E.HCLK_ROW[6] bit 6
B39 HROW_INT: mux W.HCLK_ROW[6] bit 7 - HROW_INT: mux E.HCLK_ROW[6] bit 7 -
B38 - - - -
B37 - - - -
B36 - - - -
B35 HROW_INT: mux W.HCLK_ROW[4] bit 8 - HROW_INT: mux E.HCLK_ROW[4] bit 8 -
B34 HROW_INT: mux W.HCLK_ROW[4] bit 9 - HROW_INT: mux E.HCLK_ROW[4] bit 9 -
B33 HROW_INT: mux W.HCLK_ROW[4] bit 11 HROW_INT: mux W.HCLK_ROW[4] bit 10 HROW_INT: mux E.HCLK_ROW[4] bit 11 HROW_INT: mux E.HCLK_ROW[4] bit 10
B32 HROW_INT: mux W.HCLK_ROW[4] bit 0 HROW_INT: mux W.HCLK_ROW[4] bit 1 HROW_INT: mux E.HCLK_ROW[4] bit 0 HROW_INT: mux E.HCLK_ROW[4] bit 1
B31 HROW_INT: mux W.HCLK_ROW[4] bit 3 HROW_INT: mux W.HCLK_ROW[4] bit 2 HROW_INT: mux E.HCLK_ROW[4] bit 3 HROW_INT: mux E.HCLK_ROW[4] bit 2
B30 HROW_INT: mux W.HCLK_ROW[4] bit 4 - HROW_INT: mux E.HCLK_ROW[4] bit 4 -
B29 - HROW_INT: mux W.HCLK_ROW[4] bit 5 - HROW_INT: mux E.HCLK_ROW[4] bit 5
B28 - HROW_INT: mux W.HCLK_ROW[4] bit 6 - HROW_INT: mux E.HCLK_ROW[4] bit 6
B27 HROW_INT: mux W.HCLK_ROW[4] bit 7 - HROW_INT: mux E.HCLK_ROW[4] bit 7 -
B26 - - - -
B25 - - - -
B24 - - - -
B23 HROW_INT: mux W.HCLK_ROW[2] bit 8 - HROW_INT: mux E.HCLK_ROW[2] bit 8 -
B22 HROW_INT: mux W.HCLK_ROW[2] bit 9 - HROW_INT: mux E.HCLK_ROW[2] bit 9 -
B21 HROW_INT: mux W.HCLK_ROW[2] bit 11 HROW_INT: mux W.HCLK_ROW[2] bit 10 HROW_INT: mux E.HCLK_ROW[2] bit 11 HROW_INT: mux E.HCLK_ROW[2] bit 10
B20 HROW_INT: mux W.HCLK_ROW[2] bit 0 HROW_INT: mux W.HCLK_ROW[2] bit 1 HROW_INT: mux E.HCLK_ROW[2] bit 0 HROW_INT: mux E.HCLK_ROW[2] bit 1
B19 HROW_INT: mux W.HCLK_ROW[2] bit 3 HROW_INT: mux W.HCLK_ROW[2] bit 2 HROW_INT: mux E.HCLK_ROW[2] bit 3 HROW_INT: mux E.HCLK_ROW[2] bit 2
B18 HROW_INT: mux W.HCLK_ROW[2] bit 4 - HROW_INT: mux E.HCLK_ROW[2] bit 4 -
B17 - HROW_INT: mux W.HCLK_ROW[2] bit 5 - HROW_INT: mux E.HCLK_ROW[2] bit 5
B16 - HROW_INT: mux W.HCLK_ROW[2] bit 6 - HROW_INT: mux E.HCLK_ROW[2] bit 6
B15 HROW_INT: mux W.HCLK_ROW[2] bit 7 - HROW_INT: mux E.HCLK_ROW[2] bit 7 -
B14 - - - -
B13 HROW_INT: buffer W.GCLK_BUF[25] ← W.GCLK[25] HROW_INT: buffer W.GCLK_BUF[24] ← W.GCLK[24] HROW_INT: buffer W.GCLK_BUF[0] ← W.GCLK[0] HROW_INT: buffer W.GCLK_BUF[1] ← W.GCLK[1]
B12 HROW_INT: buffer W.GCLK_BUF[9] ← W.GCLK[9] HROW_INT: buffer W.GCLK_BUF[8] ← W.GCLK[8] HROW_INT: buffer W.GCLK_BUF[16] ← W.GCLK[16] HROW_INT: buffer W.GCLK_BUF[17] ← W.GCLK[17]
B11 - - - -
B10 - - - -
B9 HROW_INT: mux W.HCLK_ROW[0] bit 8 - HROW_INT: mux E.HCLK_ROW[0] bit 8 -
B8 HROW_INT: mux W.HCLK_ROW[0] bit 9 - HROW_INT: mux E.HCLK_ROW[0] bit 9 -
B7 HROW_INT: mux W.HCLK_ROW[0] bit 11 HROW_INT: mux W.HCLK_ROW[0] bit 10 HROW_INT: mux E.HCLK_ROW[0] bit 11 HROW_INT: mux E.HCLK_ROW[0] bit 10
B6 HROW_INT: mux W.HCLK_ROW[0] bit 0 HROW_INT: mux W.HCLK_ROW[0] bit 1 HROW_INT: mux E.HCLK_ROW[0] bit 0 HROW_INT: mux E.HCLK_ROW[0] bit 1
B5 HROW_INT: mux W.HCLK_ROW[0] bit 3 HROW_INT: mux W.HCLK_ROW[0] bit 2 HROW_INT: mux E.HCLK_ROW[0] bit 3 HROW_INT: mux E.HCLK_ROW[0] bit 2
B4 HROW_INT: mux W.HCLK_ROW[0] bit 4 - HROW_INT: mux E.HCLK_ROW[0] bit 4 -
B3 - HROW_INT: mux W.HCLK_ROW[0] bit 5 - HROW_INT: mux E.HCLK_ROW[0] bit 5
B2 - HROW_INT: mux W.HCLK_ROW[0] bit 6 - HROW_INT: mux E.HCLK_ROW[0] bit 6
B1 HROW_INT: mux W.HCLK_ROW[0] bit 7 - HROW_INT: mux E.HCLK_ROW[0] bit 7 -
B0 - - - -
virtex5 CLK_HROW rect HCLK
BitFrame
F0 F1 F2 F3
B31 - - - -
B30 - - - -
B29 - - - -
B28 - - - -
B27 - - - -
B26 - - - -
B25 - - - -
B24 - - - -
B23 - - - -
B22 - - - -
B21 - - - -
B20 - - - -
B19 - - - -
B18 - - - -
B17 - - - -
B16 - - - -
B15 HROW_INT: buffer W.GCLK_BUF[27] ← W.GCLK[27] HROW_INT: buffer W.GCLK_BUF[26] ← W.GCLK[26] HROW_INT: buffer W.GCLK_BUF[2] ← W.GCLK[2] HROW_INT: buffer W.GCLK_BUF[3] ← W.GCLK[3]
B14 HROW_INT: buffer W.GCLK_BUF[10] ← W.GCLK[10] HROW_INT: buffer W.GCLK_BUF[11] ← W.GCLK[11] HROW_INT: buffer W.GCLK_BUF[19] ← W.GCLK[19] HROW_INT: buffer W.GCLK_BUF[18] ← W.GCLK[18]
B13 HROW_INT: buffer W.GCLK_BUF[12] ← W.GCLK[12] HROW_INT: buffer W.GCLK_BUF[13] ← W.GCLK[13] HROW_INT: buffer W.GCLK_BUF[21] ← W.GCLK[21] HROW_INT: buffer W.GCLK_BUF[20] ← W.GCLK[20]
B12 HROW_INT: buffer W.GCLK_BUF[29] ← W.GCLK[29] HROW_INT: buffer W.GCLK_BUF[28] ← W.GCLK[28] HROW_INT: buffer W.GCLK_BUF[4] ← W.GCLK[4] HROW_INT: buffer W.GCLK_BUF[5] ← W.GCLK[5]
B11 - - - -
B10 - - - -
B9 - - - -
B8 - - - -
B7 - - - -
B6 - - - -
B5 - - - -
B4 - - - -
B3 - - - -
B2 - - - -
B1 - - - -
B0 - - - -