Clock spine multiplexers

Tile CLK_IOB_S

Cells: 11

Switchbox CLK_INT

virtex5 CLK_IOB_S switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[1][1][0]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[1][1][1]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[1][1][2]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[1][1][3]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[1][1][4]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[1][3][0]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[1][3][1]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[1][3][2]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[1][3][3]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[1][3][4]

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[0]
Bits				Destination
MAIN[1][2][19]	MAIN[1][2][9]	MAIN[1][0][39]	MAIN[1][0][9]	CELL[0].GIOB[0]
				Source
0	0	0	0	off
1	1	1	1	CELL[0].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[1]
Bits				Destination
MAIN[1][2][20]	MAIN[1][2][10]	MAIN[1][0][40]	MAIN[1][0][10]	CELL[0].GIOB[1]
				Source
0	0	0	0	off
1	1	1	1	CELL[1].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[2]
Bits				Destination
MAIN[1][2][21]	MAIN[1][2][11]	MAIN[1][0][41]	MAIN[1][0][11]	CELL[0].GIOB[2]
				Source
0	0	0	0	off
1	1	1	1	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[3]
Bits				Destination
MAIN[1][2][22]	MAIN[1][2][12]	MAIN[1][0][42]	MAIN[1][0][12]	CELL[0].GIOB[3]
				Source
0	0	0	0	off
1	1	1	1	CELL[3].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[4]
Bits				Destination
MAIN[1][2][23]	MAIN[1][2][13]	MAIN[1][0][43]	MAIN[1][0][13]	CELL[0].GIOB[4]
				Source
0	0	0	0	off
1	1	1	1	CELL[4].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[5]
Bits				Destination
MAIN[1][3][19]	MAIN[1][3][9]	MAIN[1][1][39]	MAIN[1][1][9]	CELL[0].GIOB[5]
				Source
0	0	0	0	off
1	1	1	1	CELL[5].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[6]
Bits				Destination
MAIN[1][3][20]	MAIN[1][3][10]	MAIN[1][1][40]	MAIN[1][1][10]	CELL[0].GIOB[6]
				Source
0	0	0	0	off
1	1	1	1	CELL[6].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[7]
Bits				Destination
MAIN[1][3][21]	MAIN[1][3][11]	MAIN[1][1][41]	MAIN[1][1][11]	CELL[0].GIOB[7]
				Source
0	0	0	0	off
1	1	1	1	CELL[7].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[8]
Bits				Destination
MAIN[1][3][22]	MAIN[1][3][12]	MAIN[1][1][42]	MAIN[1][1][12]	CELL[0].GIOB[8]
				Source
0	0	0	0	off
1	1	1	1	CELL[8].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes GIOB[9]
Bits				Destination
MAIN[1][3][23]	MAIN[1][3][13]	MAIN[1][1][43]	MAIN[1][1][13]	CELL[0].GIOB[9]
				Source
0	0	0	0	off
1	1	1	1	CELL[9].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits											Destination
MAIN[5][2][4]	MAIN[5][3][5]	MAIN[5][2][6]	MAIN[5][3][1]	MAIN[5][2][2]	MAIN[5][3][3]	MAIN[5][2][8]	MAIN[5][3][8]	MAIN[5][2][7]	MAIN[5][3][7]	MAIN[5][0][12]	CELL[0].IMUX_BUFG_O[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits											Destination
MAIN[5][0][4]	MAIN[5][1][5]	MAIN[5][0][6]	MAIN[5][1][1]	MAIN[5][0][2]	MAIN[5][1][3]	MAIN[5][0][8]	MAIN[5][1][8]	MAIN[5][0][7]	MAIN[5][1][7]	MAIN[5][2][12]	CELL[0].IMUX_BUFG_O[1]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits											Destination
MAIN[5][2][20]	MAIN[5][3][21]	MAIN[5][2][22]	MAIN[5][3][17]	MAIN[5][2][18]	MAIN[5][3][19]	MAIN[5][2][24]	MAIN[5][3][24]	MAIN[5][2][23]	MAIN[5][3][23]	MAIN[5][0][28]	CELL[0].IMUX_BUFG_O[2]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits											Destination
MAIN[5][0][20]	MAIN[5][1][21]	MAIN[5][0][22]	MAIN[5][1][17]	MAIN[5][0][18]	MAIN[5][1][19]	MAIN[5][0][24]	MAIN[5][1][24]	MAIN[5][0][23]	MAIN[5][1][23]	MAIN[5][2][28]	CELL[0].IMUX_BUFG_O[3]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits											Destination
MAIN[5][2][36]	MAIN[5][3][37]	MAIN[5][2][38]	MAIN[5][3][33]	MAIN[5][2][34]	MAIN[5][3][35]	MAIN[5][2][40]	MAIN[5][3][40]	MAIN[5][2][39]	MAIN[5][3][39]	MAIN[5][0][44]	CELL[0].IMUX_BUFG_O[4]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits											Destination
MAIN[5][0][36]	MAIN[5][1][37]	MAIN[5][0][38]	MAIN[5][1][33]	MAIN[5][0][34]	MAIN[5][1][35]	MAIN[5][0][40]	MAIN[5][1][40]	MAIN[5][0][39]	MAIN[5][1][39]	MAIN[5][2][44]	CELL[0].IMUX_BUFG_O[5]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits											Destination
MAIN[5][2][52]	MAIN[5][3][53]	MAIN[5][2][54]	MAIN[5][3][49]	MAIN[5][2][50]	MAIN[5][3][51]	MAIN[5][2][56]	MAIN[5][3][56]	MAIN[5][2][55]	MAIN[5][3][55]	MAIN[5][0][60]	CELL[0].IMUX_BUFG_O[6]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits											Destination
MAIN[5][0][52]	MAIN[5][1][53]	MAIN[5][0][54]	MAIN[5][1][49]	MAIN[5][0][50]	MAIN[5][1][51]	MAIN[5][0][56]	MAIN[5][1][56]	MAIN[5][0][55]	MAIN[5][1][55]	MAIN[5][2][60]	CELL[0].IMUX_BUFG_O[7]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits											Destination
MAIN[6][2][4]	MAIN[6][3][5]	MAIN[6][2][6]	MAIN[6][3][1]	MAIN[6][2][2]	MAIN[6][3][3]	MAIN[6][2][8]	MAIN[6][3][8]	MAIN[6][2][7]	MAIN[6][3][7]	MAIN[6][0][12]	CELL[0].IMUX_BUFG_O[8]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits											Destination
MAIN[6][0][4]	MAIN[6][1][5]	MAIN[6][0][6]	MAIN[6][1][1]	MAIN[6][0][2]	MAIN[6][1][3]	MAIN[6][0][8]	MAIN[6][1][8]	MAIN[6][0][7]	MAIN[6][1][7]	MAIN[6][2][12]	CELL[0].IMUX_BUFG_O[9]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits											Destination
MAIN[6][2][20]	MAIN[6][3][21]	MAIN[6][2][22]	MAIN[6][3][17]	MAIN[6][2][18]	MAIN[6][3][19]	MAIN[6][2][24]	MAIN[6][3][24]	MAIN[6][2][23]	MAIN[6][3][23]	MAIN[6][0][28]	CELL[0].IMUX_BUFG_O[10]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits											Destination
MAIN[6][0][20]	MAIN[6][1][21]	MAIN[6][0][22]	MAIN[6][1][17]	MAIN[6][0][18]	MAIN[6][1][19]	MAIN[6][0][24]	MAIN[6][1][24]	MAIN[6][0][23]	MAIN[6][1][23]	MAIN[6][2][28]	CELL[0].IMUX_BUFG_O[11]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits											Destination
MAIN[6][2][36]	MAIN[6][3][37]	MAIN[6][2][38]	MAIN[6][3][33]	MAIN[6][2][34]	MAIN[6][3][35]	MAIN[6][2][40]	MAIN[6][3][40]	MAIN[6][2][39]	MAIN[6][3][39]	MAIN[6][0][44]	CELL[0].IMUX_BUFG_O[12]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits											Destination
MAIN[6][0][36]	MAIN[6][1][37]	MAIN[6][0][38]	MAIN[6][1][33]	MAIN[6][0][34]	MAIN[6][1][35]	MAIN[6][0][40]	MAIN[6][1][40]	MAIN[6][0][39]	MAIN[6][1][39]	MAIN[6][2][44]	CELL[0].IMUX_BUFG_O[13]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits											Destination
MAIN[6][2][52]	MAIN[6][3][53]	MAIN[6][2][54]	MAIN[6][3][49]	MAIN[6][2][50]	MAIN[6][3][51]	MAIN[6][2][56]	MAIN[6][3][56]	MAIN[6][2][55]	MAIN[6][3][55]	MAIN[6][0][60]	CELL[0].IMUX_BUFG_O[14]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits											Destination
MAIN[6][0][52]	MAIN[6][1][53]	MAIN[6][0][54]	MAIN[6][1][49]	MAIN[6][0][50]	MAIN[6][1][51]	MAIN[6][0][56]	MAIN[6][1][56]	MAIN[6][0][55]	MAIN[6][1][55]	MAIN[6][2][60]	CELL[0].IMUX_BUFG_O[15]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits											Destination
MAIN[7][2][4]	MAIN[7][3][5]	MAIN[7][2][6]	MAIN[7][3][1]	MAIN[7][2][2]	MAIN[7][3][3]	MAIN[7][2][8]	MAIN[7][3][8]	MAIN[7][2][7]	MAIN[7][3][7]	MAIN[7][0][12]	CELL[0].IMUX_BUFG_O[16]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits											Destination
MAIN[7][0][4]	MAIN[7][1][5]	MAIN[7][0][6]	MAIN[7][1][1]	MAIN[7][0][2]	MAIN[7][1][3]	MAIN[7][0][8]	MAIN[7][1][8]	MAIN[7][0][7]	MAIN[7][1][7]	MAIN[7][2][12]	CELL[0].IMUX_BUFG_O[17]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits											Destination
MAIN[7][2][20]	MAIN[7][3][21]	MAIN[7][2][22]	MAIN[7][3][17]	MAIN[7][2][18]	MAIN[7][3][19]	MAIN[7][2][24]	MAIN[7][3][24]	MAIN[7][2][23]	MAIN[7][3][23]	MAIN[7][0][28]	CELL[0].IMUX_BUFG_O[18]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits											Destination
MAIN[7][0][20]	MAIN[7][1][21]	MAIN[7][0][22]	MAIN[7][1][17]	MAIN[7][0][18]	MAIN[7][1][19]	MAIN[7][0][24]	MAIN[7][1][24]	MAIN[7][0][23]	MAIN[7][1][23]	MAIN[7][2][28]	CELL[0].IMUX_BUFG_O[19]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits											Destination
MAIN[7][2][36]	MAIN[7][3][37]	MAIN[7][2][38]	MAIN[7][3][33]	MAIN[7][2][34]	MAIN[7][3][35]	MAIN[7][2][40]	MAIN[7][3][40]	MAIN[7][2][39]	MAIN[7][3][39]	MAIN[7][0][44]	CELL[0].IMUX_BUFG_O[20]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits											Destination
MAIN[7][0][36]	MAIN[7][1][37]	MAIN[7][0][38]	MAIN[7][1][33]	MAIN[7][0][34]	MAIN[7][1][35]	MAIN[7][0][40]	MAIN[7][1][40]	MAIN[7][0][39]	MAIN[7][1][39]	MAIN[7][2][44]	CELL[0].IMUX_BUFG_O[21]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits											Destination
MAIN[7][2][52]	MAIN[7][3][53]	MAIN[7][2][54]	MAIN[7][3][49]	MAIN[7][2][50]	MAIN[7][3][51]	MAIN[7][2][56]	MAIN[7][3][56]	MAIN[7][2][55]	MAIN[7][3][55]	MAIN[7][0][60]	CELL[0].IMUX_BUFG_O[22]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits											Destination
MAIN[7][0][52]	MAIN[7][1][53]	MAIN[7][0][54]	MAIN[7][1][49]	MAIN[7][0][50]	MAIN[7][1][51]	MAIN[7][0][56]	MAIN[7][1][56]	MAIN[7][0][55]	MAIN[7][1][55]	MAIN[7][2][60]	CELL[0].IMUX_BUFG_O[23]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits											Destination
MAIN[8][2][4]	MAIN[8][3][5]	MAIN[8][2][6]	MAIN[8][3][1]	MAIN[8][2][2]	MAIN[8][3][3]	MAIN[8][2][8]	MAIN[8][3][8]	MAIN[8][2][7]	MAIN[8][3][7]	MAIN[8][0][12]	CELL[0].IMUX_BUFG_O[24]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits											Destination
MAIN[8][0][4]	MAIN[8][1][5]	MAIN[8][0][6]	MAIN[8][1][1]	MAIN[8][0][2]	MAIN[8][1][3]	MAIN[8][0][8]	MAIN[8][1][8]	MAIN[8][0][7]	MAIN[8][1][7]	MAIN[8][2][12]	CELL[0].IMUX_BUFG_O[25]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits											Destination
MAIN[8][2][20]	MAIN[8][3][21]	MAIN[8][2][22]	MAIN[8][3][17]	MAIN[8][2][18]	MAIN[8][3][19]	MAIN[8][2][24]	MAIN[8][3][24]	MAIN[8][2][23]	MAIN[8][3][23]	MAIN[8][0][28]	CELL[0].IMUX_BUFG_O[26]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits											Destination
MAIN[8][0][20]	MAIN[8][1][21]	MAIN[8][0][22]	MAIN[8][1][17]	MAIN[8][0][18]	MAIN[8][1][19]	MAIN[8][0][24]	MAIN[8][1][24]	MAIN[8][0][23]	MAIN[8][1][23]	MAIN[8][2][28]	CELL[0].IMUX_BUFG_O[27]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits											Destination
MAIN[8][2][36]	MAIN[8][3][37]	MAIN[8][2][38]	MAIN[8][3][33]	MAIN[8][2][34]	MAIN[8][3][35]	MAIN[8][2][40]	MAIN[8][3][40]	MAIN[8][2][39]	MAIN[8][3][39]	MAIN[8][0][44]	CELL[0].IMUX_BUFG_O[28]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits											Destination
MAIN[8][0][36]	MAIN[8][1][37]	MAIN[8][0][38]	MAIN[8][1][33]	MAIN[8][0][34]	MAIN[8][1][35]	MAIN[8][0][40]	MAIN[8][1][40]	MAIN[8][0][39]	MAIN[8][1][39]	MAIN[8][2][44]	CELL[0].IMUX_BUFG_O[29]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits											Destination
MAIN[8][2][52]	MAIN[8][3][53]	MAIN[8][2][54]	MAIN[8][3][49]	MAIN[8][2][50]	MAIN[8][3][51]	MAIN[8][2][56]	MAIN[8][3][56]	MAIN[8][2][55]	MAIN[8][3][55]	MAIN[8][0][60]	CELL[0].IMUX_BUFG_O[30]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_S switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits											Destination
MAIN[8][0][52]	MAIN[8][1][53]	MAIN[8][0][54]	MAIN[8][1][49]	MAIN[8][0][50]	MAIN[8][1][51]	MAIN[8][0][56]	MAIN[8][1][56]	MAIN[8][0][55]	MAIN[8][1][55]	MAIN[8][2][60]	CELL[0].IMUX_BUFG_O[31]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

Bitstream

virtex5 CLK_IOB_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	CLK_INT: mux CELL[0].GIOB[4] bit 1	CLK_INT: mux CELL[0].GIOB[9] bit 1	-	-
B42	CLK_INT: mux CELL[0].GIOB[3] bit 1	CLK_INT: mux CELL[0].GIOB[8] bit 1	-	-
B41	CLK_INT: mux CELL[0].GIOB[2] bit 1	CLK_INT: mux CELL[0].GIOB[7] bit 1	-	-
B40	CLK_INT: mux CELL[0].GIOB[1] bit 1	CLK_INT: mux CELL[0].GIOB[6] bit 1	-	-
B39	CLK_INT: mux CELL[0].GIOB[0] bit 1	CLK_INT: mux CELL[0].GIOB[5] bit 1	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	CLK_INT: mux CELL[0].GIOB[4] bit 3	CLK_INT: mux CELL[0].GIOB[9] bit 3
B22	-	-	CLK_INT: mux CELL[0].GIOB[3] bit 3	CLK_INT: mux CELL[0].GIOB[8] bit 3
B21	-	-	CLK_INT: mux CELL[0].GIOB[2] bit 3	CLK_INT: mux CELL[0].GIOB[7] bit 3
B20	-	-	CLK_INT: mux CELL[0].GIOB[1] bit 3	CLK_INT: mux CELL[0].GIOB[6] bit 3
B19	-	-	CLK_INT: mux CELL[0].GIOB[0] bit 3	CLK_INT: mux CELL[0].GIOB[5] bit 3
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	CLK_INT: mux CELL[0].GIOB[4] bit 0	CLK_INT: mux CELL[0].GIOB[9] bit 0	CLK_INT: mux CELL[0].GIOB[4] bit 2	CLK_INT: mux CELL[0].GIOB[9] bit 2
B12	CLK_INT: mux CELL[0].GIOB[3] bit 0	CLK_INT: mux CELL[0].GIOB[8] bit 0	CLK_INT: mux CELL[0].GIOB[3] bit 2	CLK_INT: mux CELL[0].GIOB[8] bit 2
B11	CLK_INT: mux CELL[0].GIOB[2] bit 0	CLK_INT: mux CELL[0].GIOB[7] bit 0	CLK_INT: mux CELL[0].GIOB[2] bit 2	CLK_INT: mux CELL[0].GIOB[7] bit 2
B10	CLK_INT: mux CELL[0].GIOB[1] bit 0	CLK_INT: mux CELL[0].GIOB[6] bit 0	CLK_INT: mux CELL[0].GIOB[1] bit 2	CLK_INT: mux CELL[0].GIOB[6] bit 2
B9	CLK_INT: mux CELL[0].GIOB[0] bit 0	CLK_INT: mux CELL[0].GIOB[5] bit 0	CLK_INT: mux CELL[0].GIOB[0] bit 2	CLK_INT: mux CELL[0].GIOB[5] bit 2
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]
B3	-	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]
B2	-	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]
B1	-	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]
B0	-	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]

virtex5 CLK_IOB_S rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-
B49	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-
B33	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-
B17	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-
B1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-
B49	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-
B33	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-
B17	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-
B1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-
B49	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-
B33	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-
B17	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-
B1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5
B50	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-
B49	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5
B34	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-
B33	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5
B18	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-
B17	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5
B2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-
B1	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7
B0	-	-	-	-

virtex5 CLK_IOB_S rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_IOB_N

Cells: 11

Switchbox CLK_INT

virtex5 CLK_IOB_N switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[8][1][63]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[8][1][62]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[8][1][61]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[8][1][60]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[8][1][59]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[8][3][63]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[8][3][62]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[8][3][61]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[8][3][60]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[8][3][59]

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[0]
Bits				Destination
MAIN[8][2][54]	MAIN[8][2][44]	MAIN[8][0][54]	MAIN[8][0][24]	CELL[0].GIOB[0]
				Source
0	0	0	0	off
1	1	1	1	CELL[0].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[1]
Bits				Destination
MAIN[8][2][53]	MAIN[8][2][43]	MAIN[8][0][53]	MAIN[8][0][23]	CELL[0].GIOB[1]
				Source
0	0	0	0	off
1	1	1	1	CELL[1].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[2]
Bits				Destination
MAIN[8][2][52]	MAIN[8][2][42]	MAIN[8][0][52]	MAIN[8][0][22]	CELL[0].GIOB[2]
				Source
0	0	0	0	off
1	1	1	1	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[3]
Bits				Destination
MAIN[8][2][51]	MAIN[8][2][41]	MAIN[8][0][51]	MAIN[8][0][21]	CELL[0].GIOB[3]
				Source
0	0	0	0	off
1	1	1	1	CELL[3].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[4]
Bits				Destination
MAIN[8][2][50]	MAIN[8][2][40]	MAIN[8][0][50]	MAIN[8][0][20]	CELL[0].GIOB[4]
				Source
0	0	0	0	off
1	1	1	1	CELL[4].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[5]
Bits				Destination
MAIN[8][3][54]	MAIN[8][3][44]	MAIN[8][1][54]	MAIN[8][1][24]	CELL[0].GIOB[5]
				Source
0	0	0	0	off
1	1	1	1	CELL[5].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[6]
Bits				Destination
MAIN[8][3][53]	MAIN[8][3][43]	MAIN[8][1][53]	MAIN[8][1][23]	CELL[0].GIOB[6]
				Source
0	0	0	0	off
1	1	1	1	CELL[6].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[7]
Bits				Destination
MAIN[8][3][52]	MAIN[8][3][42]	MAIN[8][1][52]	MAIN[8][1][22]	CELL[0].GIOB[7]
				Source
0	0	0	0	off
1	1	1	1	CELL[7].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[8]
Bits				Destination
MAIN[8][3][51]	MAIN[8][3][41]	MAIN[8][1][51]	MAIN[8][1][21]	CELL[0].GIOB[8]
				Source
0	0	0	0	off
1	1	1	1	CELL[8].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes GIOB[9]
Bits				Destination
MAIN[8][3][50]	MAIN[8][3][40]	MAIN[8][1][50]	MAIN[8][1][20]	CELL[0].GIOB[9]
				Source
0	0	0	0	off
1	1	1	1	CELL[9].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits											Destination
MAIN[4][2][59]	MAIN[4][3][58]	MAIN[4][2][57]	MAIN[4][3][62]	MAIN[4][2][61]	MAIN[4][3][60]	MAIN[4][2][55]	MAIN[4][3][55]	MAIN[4][2][56]	MAIN[4][3][56]	MAIN[4][0][51]	CELL[0].IMUX_BUFG_O[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits											Destination
MAIN[4][0][59]	MAIN[4][1][58]	MAIN[4][0][57]	MAIN[4][1][62]	MAIN[4][0][61]	MAIN[4][1][60]	MAIN[4][0][55]	MAIN[4][1][55]	MAIN[4][0][56]	MAIN[4][1][56]	MAIN[4][2][51]	CELL[0].IMUX_BUFG_O[1]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits											Destination
MAIN[4][2][43]	MAIN[4][3][42]	MAIN[4][2][41]	MAIN[4][3][46]	MAIN[4][2][45]	MAIN[4][3][44]	MAIN[4][2][39]	MAIN[4][3][39]	MAIN[4][2][40]	MAIN[4][3][40]	MAIN[4][0][35]	CELL[0].IMUX_BUFG_O[2]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits											Destination
MAIN[4][0][43]	MAIN[4][1][42]	MAIN[4][0][41]	MAIN[4][1][46]	MAIN[4][0][45]	MAIN[4][1][44]	MAIN[4][0][39]	MAIN[4][1][39]	MAIN[4][0][40]	MAIN[4][1][40]	MAIN[4][2][35]	CELL[0].IMUX_BUFG_O[3]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits											Destination
MAIN[4][2][27]	MAIN[4][3][26]	MAIN[4][2][25]	MAIN[4][3][30]	MAIN[4][2][29]	MAIN[4][3][28]	MAIN[4][2][23]	MAIN[4][3][23]	MAIN[4][2][24]	MAIN[4][3][24]	MAIN[4][0][19]	CELL[0].IMUX_BUFG_O[4]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits											Destination
MAIN[4][0][27]	MAIN[4][1][26]	MAIN[4][0][25]	MAIN[4][1][30]	MAIN[4][0][29]	MAIN[4][1][28]	MAIN[4][0][23]	MAIN[4][1][23]	MAIN[4][0][24]	MAIN[4][1][24]	MAIN[4][2][19]	CELL[0].IMUX_BUFG_O[5]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits											Destination
MAIN[4][2][11]	MAIN[4][3][10]	MAIN[4][2][9]	MAIN[4][3][14]	MAIN[4][2][13]	MAIN[4][3][12]	MAIN[4][2][7]	MAIN[4][3][7]	MAIN[4][2][8]	MAIN[4][3][8]	MAIN[4][0][3]	CELL[0].IMUX_BUFG_O[6]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits											Destination
MAIN[4][0][11]	MAIN[4][1][10]	MAIN[4][0][9]	MAIN[4][1][14]	MAIN[4][0][13]	MAIN[4][1][12]	MAIN[4][0][7]	MAIN[4][1][7]	MAIN[4][0][8]	MAIN[4][1][8]	MAIN[4][2][3]	CELL[0].IMUX_BUFG_O[7]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits											Destination
MAIN[3][2][59]	MAIN[3][3][58]	MAIN[3][2][57]	MAIN[3][3][62]	MAIN[3][2][61]	MAIN[3][3][60]	MAIN[3][2][55]	MAIN[3][3][55]	MAIN[3][2][56]	MAIN[3][3][56]	MAIN[3][0][51]	CELL[0].IMUX_BUFG_O[8]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits											Destination
MAIN[3][0][59]	MAIN[3][1][58]	MAIN[3][0][57]	MAIN[3][1][62]	MAIN[3][0][61]	MAIN[3][1][60]	MAIN[3][0][55]	MAIN[3][1][55]	MAIN[3][0][56]	MAIN[3][1][56]	MAIN[3][2][51]	CELL[0].IMUX_BUFG_O[9]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits											Destination
MAIN[3][2][43]	MAIN[3][3][42]	MAIN[3][2][41]	MAIN[3][3][46]	MAIN[3][2][45]	MAIN[3][3][44]	MAIN[3][2][39]	MAIN[3][3][39]	MAIN[3][2][40]	MAIN[3][3][40]	MAIN[3][0][35]	CELL[0].IMUX_BUFG_O[10]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits											Destination
MAIN[3][0][43]	MAIN[3][1][42]	MAIN[3][0][41]	MAIN[3][1][46]	MAIN[3][0][45]	MAIN[3][1][44]	MAIN[3][0][39]	MAIN[3][1][39]	MAIN[3][0][40]	MAIN[3][1][40]	MAIN[3][2][35]	CELL[0].IMUX_BUFG_O[11]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits											Destination
MAIN[3][2][27]	MAIN[3][3][26]	MAIN[3][2][25]	MAIN[3][3][30]	MAIN[3][2][29]	MAIN[3][3][28]	MAIN[3][2][23]	MAIN[3][3][23]	MAIN[3][2][24]	MAIN[3][3][24]	MAIN[3][0][19]	CELL[0].IMUX_BUFG_O[12]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits											Destination
MAIN[3][0][27]	MAIN[3][1][26]	MAIN[3][0][25]	MAIN[3][1][30]	MAIN[3][0][29]	MAIN[3][1][28]	MAIN[3][0][23]	MAIN[3][1][23]	MAIN[3][0][24]	MAIN[3][1][24]	MAIN[3][2][19]	CELL[0].IMUX_BUFG_O[13]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits											Destination
MAIN[3][2][11]	MAIN[3][3][10]	MAIN[3][2][9]	MAIN[3][3][14]	MAIN[3][2][13]	MAIN[3][3][12]	MAIN[3][2][7]	MAIN[3][3][7]	MAIN[3][2][8]	MAIN[3][3][8]	MAIN[3][0][3]	CELL[0].IMUX_BUFG_O[14]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits											Destination
MAIN[3][0][11]	MAIN[3][1][10]	MAIN[3][0][9]	MAIN[3][1][14]	MAIN[3][0][13]	MAIN[3][1][12]	MAIN[3][0][7]	MAIN[3][1][7]	MAIN[3][0][8]	MAIN[3][1][8]	MAIN[3][2][3]	CELL[0].IMUX_BUFG_O[15]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits											Destination
MAIN[2][2][59]	MAIN[2][3][58]	MAIN[2][2][57]	MAIN[2][3][62]	MAIN[2][2][61]	MAIN[2][3][60]	MAIN[2][2][55]	MAIN[2][3][55]	MAIN[2][2][56]	MAIN[2][3][56]	MAIN[2][0][51]	CELL[0].IMUX_BUFG_O[16]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits											Destination
MAIN[2][0][59]	MAIN[2][1][58]	MAIN[2][0][57]	MAIN[2][1][62]	MAIN[2][0][61]	MAIN[2][1][60]	MAIN[2][0][55]	MAIN[2][1][55]	MAIN[2][0][56]	MAIN[2][1][56]	MAIN[2][2][51]	CELL[0].IMUX_BUFG_O[17]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits											Destination
MAIN[2][2][43]	MAIN[2][3][42]	MAIN[2][2][41]	MAIN[2][3][46]	MAIN[2][2][45]	MAIN[2][3][44]	MAIN[2][2][39]	MAIN[2][3][39]	MAIN[2][2][40]	MAIN[2][3][40]	MAIN[2][0][35]	CELL[0].IMUX_BUFG_O[18]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits											Destination
MAIN[2][0][43]	MAIN[2][1][42]	MAIN[2][0][41]	MAIN[2][1][46]	MAIN[2][0][45]	MAIN[2][1][44]	MAIN[2][0][39]	MAIN[2][1][39]	MAIN[2][0][40]	MAIN[2][1][40]	MAIN[2][2][35]	CELL[0].IMUX_BUFG_O[19]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits											Destination
MAIN[2][2][27]	MAIN[2][3][26]	MAIN[2][2][25]	MAIN[2][3][30]	MAIN[2][2][29]	MAIN[2][3][28]	MAIN[2][2][23]	MAIN[2][3][23]	MAIN[2][2][24]	MAIN[2][3][24]	MAIN[2][0][19]	CELL[0].IMUX_BUFG_O[20]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits											Destination
MAIN[2][0][27]	MAIN[2][1][26]	MAIN[2][0][25]	MAIN[2][1][30]	MAIN[2][0][29]	MAIN[2][1][28]	MAIN[2][0][23]	MAIN[2][1][23]	MAIN[2][0][24]	MAIN[2][1][24]	MAIN[2][2][19]	CELL[0].IMUX_BUFG_O[21]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits											Destination
MAIN[2][2][11]	MAIN[2][3][10]	MAIN[2][2][9]	MAIN[2][3][14]	MAIN[2][2][13]	MAIN[2][3][12]	MAIN[2][2][7]	MAIN[2][3][7]	MAIN[2][2][8]	MAIN[2][3][8]	MAIN[2][0][3]	CELL[0].IMUX_BUFG_O[22]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits											Destination
MAIN[2][0][11]	MAIN[2][1][10]	MAIN[2][0][9]	MAIN[2][1][14]	MAIN[2][0][13]	MAIN[2][1][12]	MAIN[2][0][7]	MAIN[2][1][7]	MAIN[2][0][8]	MAIN[2][1][8]	MAIN[2][2][3]	CELL[0].IMUX_BUFG_O[23]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits											Destination
MAIN[1][2][59]	MAIN[1][3][58]	MAIN[1][2][57]	MAIN[1][3][62]	MAIN[1][2][61]	MAIN[1][3][60]	MAIN[1][2][55]	MAIN[1][3][55]	MAIN[1][2][56]	MAIN[1][3][56]	MAIN[1][0][51]	CELL[0].IMUX_BUFG_O[24]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits											Destination
MAIN[1][0][59]	MAIN[1][1][58]	MAIN[1][0][57]	MAIN[1][1][62]	MAIN[1][0][61]	MAIN[1][1][60]	MAIN[1][0][55]	MAIN[1][1][55]	MAIN[1][0][56]	MAIN[1][1][56]	MAIN[1][2][51]	CELL[0].IMUX_BUFG_O[25]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits											Destination
MAIN[1][2][43]	MAIN[1][3][42]	MAIN[1][2][41]	MAIN[1][3][46]	MAIN[1][2][45]	MAIN[1][3][44]	MAIN[1][2][39]	MAIN[1][3][39]	MAIN[1][2][40]	MAIN[1][3][40]	MAIN[1][0][35]	CELL[0].IMUX_BUFG_O[26]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits											Destination
MAIN[1][0][43]	MAIN[1][1][42]	MAIN[1][0][41]	MAIN[1][1][46]	MAIN[1][0][45]	MAIN[1][1][44]	MAIN[1][0][39]	MAIN[1][1][39]	MAIN[1][0][40]	MAIN[1][1][40]	MAIN[1][2][35]	CELL[0].IMUX_BUFG_O[27]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits											Destination
MAIN[1][2][27]	MAIN[1][3][26]	MAIN[1][2][25]	MAIN[1][3][30]	MAIN[1][2][29]	MAIN[1][3][28]	MAIN[1][2][23]	MAIN[1][3][23]	MAIN[1][2][24]	MAIN[1][3][24]	MAIN[1][0][19]	CELL[0].IMUX_BUFG_O[28]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits											Destination
MAIN[1][0][27]	MAIN[1][1][26]	MAIN[1][0][25]	MAIN[1][1][30]	MAIN[1][0][29]	MAIN[1][1][28]	MAIN[1][0][23]	MAIN[1][1][23]	MAIN[1][0][24]	MAIN[1][1][24]	MAIN[1][2][19]	CELL[0].IMUX_BUFG_O[29]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits											Destination
MAIN[1][2][11]	MAIN[1][3][10]	MAIN[1][2][9]	MAIN[1][3][14]	MAIN[1][2][13]	MAIN[1][3][12]	MAIN[1][2][7]	MAIN[1][3][7]	MAIN[1][2][8]	MAIN[1][3][8]	MAIN[1][0][3]	CELL[0].IMUX_BUFG_O[30]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

virtex5 CLK_IOB_N switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits											Destination
MAIN[1][0][11]	MAIN[1][1][10]	MAIN[1][0][9]	MAIN[1][1][14]	MAIN[1][0][13]	MAIN[1][1][12]	MAIN[1][0][7]	MAIN[1][1][7]	MAIN[1][0][8]	MAIN[1][1][8]	MAIN[1][2][3]	CELL[0].IMUX_BUFG_O[31]
											Source
0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	1	0	1	0	0	0	CELL[9].OUT_CLKPAD
0	0	0	0	0	1	1	0	0	0	0	CELL[3].OUT_CLKPAD
0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	1	0	0	1	0	0	0	CELL[0].MGT_BUF[5]
0	0	0	0	1	0	1	0	0	0	0	CELL[4].OUT_CLKPAD
0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].MGT_BUF[6]
0	0	0	1	0	0	1	0	0	0	0	CELL[5].OUT_CLKPAD
0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[7]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[3]
0	0	1	0	0	0	0	1	0	0	0	CELL[6].OUT_CLKPAD
0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CLKPAD
0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[8]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[7].OUT_CLKPAD
0	1	0	0	0	0	1	0	0	0	0	CELL[1].OUT_CLKPAD
1	0	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[9]
1	0	0	0	0	0	0	1	0	0	0	CELL[8].OUT_CLKPAD
1	0	0	0	0	0	1	0	0	0	0	CELL[2].OUT_CLKPAD

Bitstream

virtex5 CLK_IOB_N rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7
B61	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7
B45	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7
B29	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7
B13	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]
B62	-	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]
B61	-	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]
B60	-	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]
B59	-	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	CLK_INT: mux CELL[0].GIOB[0] bit 1	CLK_INT: mux CELL[0].GIOB[5] bit 1	CLK_INT: mux CELL[0].GIOB[0] bit 3	CLK_INT: mux CELL[0].GIOB[5] bit 3
B53	CLK_INT: mux CELL[0].GIOB[1] bit 1	CLK_INT: mux CELL[0].GIOB[6] bit 1	CLK_INT: mux CELL[0].GIOB[1] bit 3	CLK_INT: mux CELL[0].GIOB[6] bit 3
B52	CLK_INT: mux CELL[0].GIOB[2] bit 1	CLK_INT: mux CELL[0].GIOB[7] bit 1	CLK_INT: mux CELL[0].GIOB[2] bit 3	CLK_INT: mux CELL[0].GIOB[7] bit 3
B51	CLK_INT: mux CELL[0].GIOB[3] bit 1	CLK_INT: mux CELL[0].GIOB[8] bit 1	CLK_INT: mux CELL[0].GIOB[3] bit 3	CLK_INT: mux CELL[0].GIOB[8] bit 3
B50	CLK_INT: mux CELL[0].GIOB[4] bit 1	CLK_INT: mux CELL[0].GIOB[9] bit 1	CLK_INT: mux CELL[0].GIOB[4] bit 3	CLK_INT: mux CELL[0].GIOB[9] bit 3
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	CLK_INT: mux CELL[0].GIOB[0] bit 2	CLK_INT: mux CELL[0].GIOB[5] bit 2
B43	-	-	CLK_INT: mux CELL[0].GIOB[1] bit 2	CLK_INT: mux CELL[0].GIOB[6] bit 2
B42	-	-	CLK_INT: mux CELL[0].GIOB[2] bit 2	CLK_INT: mux CELL[0].GIOB[7] bit 2
B41	-	-	CLK_INT: mux CELL[0].GIOB[3] bit 2	CLK_INT: mux CELL[0].GIOB[8] bit 2
B40	-	-	CLK_INT: mux CELL[0].GIOB[4] bit 2	CLK_INT: mux CELL[0].GIOB[9] bit 2
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	CLK_INT: mux CELL[0].GIOB[0] bit 0	CLK_INT: mux CELL[0].GIOB[5] bit 0	-	-
B23	CLK_INT: mux CELL[0].GIOB[1] bit 0	CLK_INT: mux CELL[0].GIOB[6] bit 0	-	-
B22	CLK_INT: mux CELL[0].GIOB[2] bit 0	CLK_INT: mux CELL[0].GIOB[7] bit 0	-	-
B21	CLK_INT: mux CELL[0].GIOB[3] bit 0	CLK_INT: mux CELL[0].GIOB[8] bit 0	-	-
B20	CLK_INT: mux CELL[0].GIOB[4] bit 0	CLK_INT: mux CELL[0].GIOB[9] bit 0	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_IOB_N rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_CMT_S

Cells: 11

Switchbox CLK_INT

virtex5 CLK_CMT_S switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[1][1][0]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[1][1][1]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[1][1][2]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[1][1][3]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[1][1][4]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[1][3][0]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[1][3][1]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[1][3][2]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[1][3][3]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[1][3][4]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits														Destination
MAIN[5][0][5]	MAIN[5][1][6]	MAIN[5][0][7]	MAIN[5][1][7]	MAIN[5][0][1]	MAIN[5][1][2]	MAIN[5][0][3]	MAIN[5][1][4]	MAIN[5][1][9]	MAIN[5][1][8]	MAIN[5][0][8]	MAIN[5][0][10]	MAIN[5][1][10]	MAIN[5][1][13]	CELL[0].IMUX_BUFG_O[0]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits														Destination
MAIN[5][2][5]	MAIN[5][3][6]	MAIN[5][2][7]	MAIN[5][3][7]	MAIN[5][2][1]	MAIN[5][3][2]	MAIN[5][2][3]	MAIN[5][3][4]	MAIN[5][3][9]	MAIN[5][3][8]	MAIN[5][2][8]	MAIN[5][2][10]	MAIN[5][3][10]	MAIN[5][3][13]	CELL[0].IMUX_BUFG_O[1]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits														Destination
MAIN[5][0][21]	MAIN[5][1][22]	MAIN[5][0][23]	MAIN[5][1][23]	MAIN[5][0][17]	MAIN[5][1][18]	MAIN[5][0][19]	MAIN[5][1][20]	MAIN[5][1][25]	MAIN[5][1][24]	MAIN[5][0][24]	MAIN[5][0][26]	MAIN[5][1][26]	MAIN[5][1][29]	CELL[0].IMUX_BUFG_O[2]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits														Destination
MAIN[5][2][21]	MAIN[5][3][22]	MAIN[5][2][23]	MAIN[5][3][23]	MAIN[5][2][17]	MAIN[5][3][18]	MAIN[5][2][19]	MAIN[5][3][20]	MAIN[5][3][25]	MAIN[5][3][24]	MAIN[5][2][24]	MAIN[5][2][26]	MAIN[5][3][26]	MAIN[5][3][29]	CELL[0].IMUX_BUFG_O[3]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits														Destination
MAIN[5][0][37]	MAIN[5][1][38]	MAIN[5][0][39]	MAIN[5][1][39]	MAIN[5][0][33]	MAIN[5][1][34]	MAIN[5][0][35]	MAIN[5][1][36]	MAIN[5][1][41]	MAIN[5][1][40]	MAIN[5][0][40]	MAIN[5][0][42]	MAIN[5][1][42]	MAIN[5][1][45]	CELL[0].IMUX_BUFG_O[4]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits														Destination
MAIN[5][2][37]	MAIN[5][3][38]	MAIN[5][2][39]	MAIN[5][3][39]	MAIN[5][2][33]	MAIN[5][3][34]	MAIN[5][2][35]	MAIN[5][3][36]	MAIN[5][3][41]	MAIN[5][3][40]	MAIN[5][2][40]	MAIN[5][2][42]	MAIN[5][3][42]	MAIN[5][3][45]	CELL[0].IMUX_BUFG_O[5]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
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0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
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0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
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0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
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0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits														Destination
MAIN[5][0][53]	MAIN[5][1][54]	MAIN[5][0][55]	MAIN[5][1][55]	MAIN[5][0][49]	MAIN[5][1][50]	MAIN[5][0][51]	MAIN[5][1][52]	MAIN[5][1][57]	MAIN[5][1][56]	MAIN[5][0][56]	MAIN[5][0][58]	MAIN[5][1][58]	MAIN[5][1][61]	CELL[0].IMUX_BUFG_O[6]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits														Destination
MAIN[5][2][53]	MAIN[5][3][54]	MAIN[5][2][55]	MAIN[5][3][55]	MAIN[5][2][49]	MAIN[5][3][50]	MAIN[5][2][51]	MAIN[5][3][52]	MAIN[5][3][57]	MAIN[5][3][56]	MAIN[5][2][56]	MAIN[5][2][58]	MAIN[5][3][58]	MAIN[5][3][61]	CELL[0].IMUX_BUFG_O[7]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits														Destination
MAIN[6][0][5]	MAIN[6][1][6]	MAIN[6][0][7]	MAIN[6][1][7]	MAIN[6][0][1]	MAIN[6][1][2]	MAIN[6][0][3]	MAIN[6][1][4]	MAIN[6][1][9]	MAIN[6][1][8]	MAIN[6][0][8]	MAIN[6][0][10]	MAIN[6][1][10]	MAIN[6][1][13]	CELL[0].IMUX_BUFG_O[8]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits														Destination
MAIN[6][2][5]	MAIN[6][3][6]	MAIN[6][2][7]	MAIN[6][3][7]	MAIN[6][2][1]	MAIN[6][3][2]	MAIN[6][2][3]	MAIN[6][3][4]	MAIN[6][3][9]	MAIN[6][3][8]	MAIN[6][2][8]	MAIN[6][2][10]	MAIN[6][3][10]	MAIN[6][3][13]	CELL[0].IMUX_BUFG_O[9]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits														Destination
MAIN[6][0][21]	MAIN[6][1][22]	MAIN[6][0][23]	MAIN[6][1][23]	MAIN[6][0][17]	MAIN[6][1][18]	MAIN[6][0][19]	MAIN[6][1][20]	MAIN[6][1][25]	MAIN[6][1][24]	MAIN[6][0][24]	MAIN[6][0][26]	MAIN[6][1][26]	MAIN[6][1][29]	CELL[0].IMUX_BUFG_O[10]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits														Destination
MAIN[6][2][21]	MAIN[6][3][22]	MAIN[6][2][23]	MAIN[6][3][23]	MAIN[6][2][17]	MAIN[6][3][18]	MAIN[6][2][19]	MAIN[6][3][20]	MAIN[6][3][25]	MAIN[6][3][24]	MAIN[6][2][24]	MAIN[6][2][26]	MAIN[6][3][26]	MAIN[6][3][29]	CELL[0].IMUX_BUFG_O[11]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits														Destination
MAIN[6][0][37]	MAIN[6][1][38]	MAIN[6][0][39]	MAIN[6][1][39]	MAIN[6][0][33]	MAIN[6][1][34]	MAIN[6][0][35]	MAIN[6][1][36]	MAIN[6][1][41]	MAIN[6][1][40]	MAIN[6][0][40]	MAIN[6][0][42]	MAIN[6][1][42]	MAIN[6][1][45]	CELL[0].IMUX_BUFG_O[12]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits														Destination
MAIN[6][2][37]	MAIN[6][3][38]	MAIN[6][2][39]	MAIN[6][3][39]	MAIN[6][2][33]	MAIN[6][3][34]	MAIN[6][2][35]	MAIN[6][3][36]	MAIN[6][3][41]	MAIN[6][3][40]	MAIN[6][2][40]	MAIN[6][2][42]	MAIN[6][3][42]	MAIN[6][3][45]	CELL[0].IMUX_BUFG_O[13]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits														Destination
MAIN[6][0][53]	MAIN[6][1][54]	MAIN[6][0][55]	MAIN[6][1][55]	MAIN[6][0][49]	MAIN[6][1][50]	MAIN[6][0][51]	MAIN[6][1][52]	MAIN[6][1][57]	MAIN[6][1][56]	MAIN[6][0][56]	MAIN[6][0][58]	MAIN[6][1][58]	MAIN[6][1][61]	CELL[0].IMUX_BUFG_O[14]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits														Destination
MAIN[6][2][53]	MAIN[6][3][54]	MAIN[6][2][55]	MAIN[6][3][55]	MAIN[6][2][49]	MAIN[6][3][50]	MAIN[6][2][51]	MAIN[6][3][52]	MAIN[6][3][57]	MAIN[6][3][56]	MAIN[6][2][56]	MAIN[6][2][58]	MAIN[6][3][58]	MAIN[6][3][61]	CELL[0].IMUX_BUFG_O[15]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits														Destination
MAIN[7][0][5]	MAIN[7][1][6]	MAIN[7][0][7]	MAIN[7][1][7]	MAIN[7][0][1]	MAIN[7][1][2]	MAIN[7][0][3]	MAIN[7][1][4]	MAIN[7][1][9]	MAIN[7][1][8]	MAIN[7][0][8]	MAIN[7][0][10]	MAIN[7][1][10]	MAIN[7][1][13]	CELL[0].IMUX_BUFG_O[16]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits														Destination
MAIN[7][2][5]	MAIN[7][3][6]	MAIN[7][2][7]	MAIN[7][3][7]	MAIN[7][2][1]	MAIN[7][3][2]	MAIN[7][2][3]	MAIN[7][3][4]	MAIN[7][3][9]	MAIN[7][3][8]	MAIN[7][2][8]	MAIN[7][2][10]	MAIN[7][3][10]	MAIN[7][3][13]	CELL[0].IMUX_BUFG_O[17]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits														Destination
MAIN[7][0][21]	MAIN[7][1][22]	MAIN[7][0][23]	MAIN[7][1][23]	MAIN[7][0][17]	MAIN[7][1][18]	MAIN[7][0][19]	MAIN[7][1][20]	MAIN[7][1][25]	MAIN[7][1][24]	MAIN[7][0][24]	MAIN[7][0][26]	MAIN[7][1][26]	MAIN[7][1][29]	CELL[0].IMUX_BUFG_O[18]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
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0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
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1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
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1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits														Destination
MAIN[7][2][21]	MAIN[7][3][22]	MAIN[7][2][23]	MAIN[7][3][23]	MAIN[7][2][17]	MAIN[7][3][18]	MAIN[7][2][19]	MAIN[7][3][20]	MAIN[7][3][25]	MAIN[7][3][24]	MAIN[7][2][24]	MAIN[7][2][26]	MAIN[7][3][26]	MAIN[7][3][29]	CELL[0].IMUX_BUFG_O[19]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
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0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
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0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
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0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
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1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
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1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits														Destination
MAIN[7][0][37]	MAIN[7][1][38]	MAIN[7][0][39]	MAIN[7][1][39]	MAIN[7][0][33]	MAIN[7][1][34]	MAIN[7][0][35]	MAIN[7][1][36]	MAIN[7][1][41]	MAIN[7][1][40]	MAIN[7][0][40]	MAIN[7][0][42]	MAIN[7][1][42]	MAIN[7][1][45]	CELL[0].IMUX_BUFG_O[20]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
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0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
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1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits														Destination
MAIN[7][2][37]	MAIN[7][3][38]	MAIN[7][2][39]	MAIN[7][3][39]	MAIN[7][2][33]	MAIN[7][3][34]	MAIN[7][2][35]	MAIN[7][3][36]	MAIN[7][3][41]	MAIN[7][3][40]	MAIN[7][2][40]	MAIN[7][2][42]	MAIN[7][3][42]	MAIN[7][3][45]	CELL[0].IMUX_BUFG_O[21]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
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0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
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0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
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0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
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0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits														Destination
MAIN[7][0][53]	MAIN[7][1][54]	MAIN[7][0][55]	MAIN[7][1][55]	MAIN[7][0][49]	MAIN[7][1][50]	MAIN[7][0][51]	MAIN[7][1][52]	MAIN[7][1][57]	MAIN[7][1][56]	MAIN[7][0][56]	MAIN[7][0][58]	MAIN[7][1][58]	MAIN[7][1][61]	CELL[0].IMUX_BUFG_O[22]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits														Destination
MAIN[7][2][53]	MAIN[7][3][54]	MAIN[7][2][55]	MAIN[7][3][55]	MAIN[7][2][49]	MAIN[7][3][50]	MAIN[7][2][51]	MAIN[7][3][52]	MAIN[7][3][57]	MAIN[7][3][56]	MAIN[7][2][56]	MAIN[7][2][58]	MAIN[7][3][58]	MAIN[7][3][61]	CELL[0].IMUX_BUFG_O[23]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits														Destination
MAIN[8][0][5]	MAIN[8][1][6]	MAIN[8][0][7]	MAIN[8][1][7]	MAIN[8][0][1]	MAIN[8][1][2]	MAIN[8][0][3]	MAIN[8][1][4]	MAIN[8][1][9]	MAIN[8][1][8]	MAIN[8][0][8]	MAIN[8][0][10]	MAIN[8][1][10]	MAIN[8][1][13]	CELL[0].IMUX_BUFG_O[24]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits														Destination
MAIN[8][2][5]	MAIN[8][3][6]	MAIN[8][2][7]	MAIN[8][3][7]	MAIN[8][2][1]	MAIN[8][3][2]	MAIN[8][2][3]	MAIN[8][3][4]	MAIN[8][3][9]	MAIN[8][3][8]	MAIN[8][2][8]	MAIN[8][2][10]	MAIN[8][3][10]	MAIN[8][3][13]	CELL[0].IMUX_BUFG_O[25]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits														Destination
MAIN[8][0][21]	MAIN[8][1][22]	MAIN[8][0][23]	MAIN[8][1][23]	MAIN[8][0][17]	MAIN[8][1][18]	MAIN[8][0][19]	MAIN[8][1][20]	MAIN[8][1][25]	MAIN[8][1][24]	MAIN[8][0][24]	MAIN[8][0][26]	MAIN[8][1][26]	MAIN[8][1][29]	CELL[0].IMUX_BUFG_O[26]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits														Destination
MAIN[8][2][21]	MAIN[8][3][22]	MAIN[8][2][23]	MAIN[8][3][23]	MAIN[8][2][17]	MAIN[8][3][18]	MAIN[8][2][19]	MAIN[8][3][20]	MAIN[8][3][25]	MAIN[8][3][24]	MAIN[8][2][24]	MAIN[8][2][26]	MAIN[8][3][26]	MAIN[8][3][29]	CELL[0].IMUX_BUFG_O[27]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits														Destination
MAIN[8][0][37]	MAIN[8][1][38]	MAIN[8][0][39]	MAIN[8][1][39]	MAIN[8][0][33]	MAIN[8][1][34]	MAIN[8][0][35]	MAIN[8][1][36]	MAIN[8][1][41]	MAIN[8][1][40]	MAIN[8][0][40]	MAIN[8][0][42]	MAIN[8][1][42]	MAIN[8][1][45]	CELL[0].IMUX_BUFG_O[28]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits														Destination
MAIN[8][2][37]	MAIN[8][3][38]	MAIN[8][2][39]	MAIN[8][3][39]	MAIN[8][2][33]	MAIN[8][3][34]	MAIN[8][2][35]	MAIN[8][3][36]	MAIN[8][3][41]	MAIN[8][3][40]	MAIN[8][2][40]	MAIN[8][2][42]	MAIN[8][3][42]	MAIN[8][3][45]	CELL[0].IMUX_BUFG_O[29]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits														Destination
MAIN[8][0][53]	MAIN[8][1][54]	MAIN[8][0][55]	MAIN[8][1][55]	MAIN[8][0][49]	MAIN[8][1][50]	MAIN[8][0][51]	MAIN[8][1][52]	MAIN[8][1][57]	MAIN[8][1][56]	MAIN[8][0][56]	MAIN[8][0][58]	MAIN[8][1][58]	MAIN[8][1][61]	CELL[0].IMUX_BUFG_O[30]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_S switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits														Destination
MAIN[8][2][53]	MAIN[8][3][54]	MAIN[8][2][55]	MAIN[8][3][55]	MAIN[8][2][49]	MAIN[8][3][50]	MAIN[8][2][51]	MAIN[8][3][52]	MAIN[8][3][57]	MAIN[8][3][56]	MAIN[8][2][56]	MAIN[8][2][58]	MAIN[8][3][58]	MAIN[8][3][61]	CELL[0].IMUX_BUFG_O[31]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

Bitstream

virtex5 CLK_CMT_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]
B3	-	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]
B2	-	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]
B1	-	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]
B0	-	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]

virtex5 CLK_CMT_S rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B60	-	-	-	-
B59	-	-	-	-
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13	-
B52	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B44	-	-	-	-
B43	-	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13	-
B36	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B28	-	-	-	-
B27	-	-	-	-
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13	-
B20	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0
B12	-	-	-	-
B11	-	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13	-
B4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B60	-	-	-	-
B59	-	-	-	-
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13	-
B52	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B44	-	-	-	-
B43	-	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13	-
B36	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B28	-	-	-	-
B27	-	-	-	-
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13	-
B20	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0
B12	-	-	-	-
B11	-	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13	-
B4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B60	-	-	-	-
B59	-	-	-	-
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13	-
B52	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B44	-	-	-	-
B43	-	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13	-
B36	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B28	-	-	-	-
B27	-	-	-	-
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13	-
B20	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0
B12	-	-	-	-
B11	-	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13	-
B4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B60	-	-	-	-
B59	-	-	-	-
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13	-
B52	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B49	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B44	-	-	-	-
B43	-	-	-	-
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13	-
B36	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B33	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B28	-	-	-	-
B27	-	-	-	-
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13	-
B20	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B17	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0
B12	-	-	-	-
B11	-	-	-	-
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13	-
B4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B1	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9	-
B0	-	-	-	-

virtex5 CLK_CMT_S rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_CMT_N

Cells: 11

Switchbox CLK_INT

virtex5 CLK_CMT_N switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[8][1][63]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[8][1][62]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[8][1][61]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[8][1][60]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[8][1][59]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[8][3][63]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[8][3][62]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[8][3][61]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[8][3][60]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[8][3][59]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits														Destination
MAIN[4][0][58]	MAIN[4][1][57]	MAIN[4][0][56]	MAIN[4][1][56]	MAIN[4][0][62]	MAIN[4][1][61]	MAIN[4][0][60]	MAIN[4][1][59]	MAIN[4][1][54]	MAIN[4][1][55]	MAIN[4][0][55]	MAIN[4][0][53]	MAIN[4][1][53]	MAIN[4][1][50]	CELL[0].IMUX_BUFG_O[0]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits														Destination
MAIN[4][2][58]	MAIN[4][3][57]	MAIN[4][2][56]	MAIN[4][3][56]	MAIN[4][2][62]	MAIN[4][3][61]	MAIN[4][2][60]	MAIN[4][3][59]	MAIN[4][3][54]	MAIN[4][3][55]	MAIN[4][2][55]	MAIN[4][2][53]	MAIN[4][3][53]	MAIN[4][3][50]	CELL[0].IMUX_BUFG_O[1]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits														Destination
MAIN[4][0][42]	MAIN[4][1][41]	MAIN[4][0][40]	MAIN[4][1][40]	MAIN[4][0][46]	MAIN[4][1][45]	MAIN[4][0][44]	MAIN[4][1][43]	MAIN[4][1][38]	MAIN[4][1][39]	MAIN[4][0][39]	MAIN[4][0][37]	MAIN[4][1][37]	MAIN[4][1][34]	CELL[0].IMUX_BUFG_O[2]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits														Destination
MAIN[4][2][42]	MAIN[4][3][41]	MAIN[4][2][40]	MAIN[4][3][40]	MAIN[4][2][46]	MAIN[4][3][45]	MAIN[4][2][44]	MAIN[4][3][43]	MAIN[4][3][38]	MAIN[4][3][39]	MAIN[4][2][39]	MAIN[4][2][37]	MAIN[4][3][37]	MAIN[4][3][34]	CELL[0].IMUX_BUFG_O[3]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits														Destination
MAIN[4][0][26]	MAIN[4][1][25]	MAIN[4][0][24]	MAIN[4][1][24]	MAIN[4][0][30]	MAIN[4][1][29]	MAIN[4][0][28]	MAIN[4][1][27]	MAIN[4][1][22]	MAIN[4][1][23]	MAIN[4][0][23]	MAIN[4][0][21]	MAIN[4][1][21]	MAIN[4][1][18]	CELL[0].IMUX_BUFG_O[4]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits														Destination
MAIN[4][2][26]	MAIN[4][3][25]	MAIN[4][2][24]	MAIN[4][3][24]	MAIN[4][2][30]	MAIN[4][3][29]	MAIN[4][2][28]	MAIN[4][3][27]	MAIN[4][3][22]	MAIN[4][3][23]	MAIN[4][2][23]	MAIN[4][2][21]	MAIN[4][3][21]	MAIN[4][3][18]	CELL[0].IMUX_BUFG_O[5]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits														Destination
MAIN[4][0][10]	MAIN[4][1][9]	MAIN[4][0][8]	MAIN[4][1][8]	MAIN[4][0][14]	MAIN[4][1][13]	MAIN[4][0][12]	MAIN[4][1][11]	MAIN[4][1][6]	MAIN[4][1][7]	MAIN[4][0][7]	MAIN[4][0][5]	MAIN[4][1][5]	MAIN[4][1][2]	CELL[0].IMUX_BUFG_O[6]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits														Destination
MAIN[4][2][10]	MAIN[4][3][9]	MAIN[4][2][8]	MAIN[4][3][8]	MAIN[4][2][14]	MAIN[4][3][13]	MAIN[4][2][12]	MAIN[4][3][11]	MAIN[4][3][6]	MAIN[4][3][7]	MAIN[4][2][7]	MAIN[4][2][5]	MAIN[4][3][5]	MAIN[4][3][2]	CELL[0].IMUX_BUFG_O[7]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits														Destination
MAIN[3][0][58]	MAIN[3][1][57]	MAIN[3][0][56]	MAIN[3][1][56]	MAIN[3][0][62]	MAIN[3][1][61]	MAIN[3][0][60]	MAIN[3][1][59]	MAIN[3][1][54]	MAIN[3][1][55]	MAIN[3][0][55]	MAIN[3][0][53]	MAIN[3][1][53]	MAIN[3][1][50]	CELL[0].IMUX_BUFG_O[8]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits														Destination
MAIN[3][2][58]	MAIN[3][3][57]	MAIN[3][2][56]	MAIN[3][3][56]	MAIN[3][2][62]	MAIN[3][3][61]	MAIN[3][2][60]	MAIN[3][3][59]	MAIN[3][3][54]	MAIN[3][3][55]	MAIN[3][2][55]	MAIN[3][2][53]	MAIN[3][3][53]	MAIN[3][3][50]	CELL[0].IMUX_BUFG_O[9]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits														Destination
MAIN[3][0][42]	MAIN[3][1][41]	MAIN[3][0][40]	MAIN[3][1][40]	MAIN[3][0][46]	MAIN[3][1][45]	MAIN[3][0][44]	MAIN[3][1][43]	MAIN[3][1][38]	MAIN[3][1][39]	MAIN[3][0][39]	MAIN[3][0][37]	MAIN[3][1][37]	MAIN[3][1][34]	CELL[0].IMUX_BUFG_O[10]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits														Destination
MAIN[3][2][42]	MAIN[3][3][41]	MAIN[3][2][40]	MAIN[3][3][40]	MAIN[3][2][46]	MAIN[3][3][45]	MAIN[3][2][44]	MAIN[3][3][43]	MAIN[3][3][38]	MAIN[3][3][39]	MAIN[3][2][39]	MAIN[3][2][37]	MAIN[3][3][37]	MAIN[3][3][34]	CELL[0].IMUX_BUFG_O[11]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits														Destination
MAIN[3][0][26]	MAIN[3][1][25]	MAIN[3][0][24]	MAIN[3][1][24]	MAIN[3][0][30]	MAIN[3][1][29]	MAIN[3][0][28]	MAIN[3][1][27]	MAIN[3][1][22]	MAIN[3][1][23]	MAIN[3][0][23]	MAIN[3][0][21]	MAIN[3][1][21]	MAIN[3][1][18]	CELL[0].IMUX_BUFG_O[12]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits														Destination
MAIN[3][2][26]	MAIN[3][3][25]	MAIN[3][2][24]	MAIN[3][3][24]	MAIN[3][2][30]	MAIN[3][3][29]	MAIN[3][2][28]	MAIN[3][3][27]	MAIN[3][3][22]	MAIN[3][3][23]	MAIN[3][2][23]	MAIN[3][2][21]	MAIN[3][3][21]	MAIN[3][3][18]	CELL[0].IMUX_BUFG_O[13]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits														Destination
MAIN[3][0][10]	MAIN[3][1][9]	MAIN[3][0][8]	MAIN[3][1][8]	MAIN[3][0][14]	MAIN[3][1][13]	MAIN[3][0][12]	MAIN[3][1][11]	MAIN[3][1][6]	MAIN[3][1][7]	MAIN[3][0][7]	MAIN[3][0][5]	MAIN[3][1][5]	MAIN[3][1][2]	CELL[0].IMUX_BUFG_O[14]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits														Destination
MAIN[3][2][10]	MAIN[3][3][9]	MAIN[3][2][8]	MAIN[3][3][8]	MAIN[3][2][14]	MAIN[3][3][13]	MAIN[3][2][12]	MAIN[3][3][11]	MAIN[3][3][6]	MAIN[3][3][7]	MAIN[3][2][7]	MAIN[3][2][5]	MAIN[3][3][5]	MAIN[3][3][2]	CELL[0].IMUX_BUFG_O[15]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
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0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
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0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits														Destination
MAIN[2][0][58]	MAIN[2][1][57]	MAIN[2][0][56]	MAIN[2][1][56]	MAIN[2][0][62]	MAIN[2][1][61]	MAIN[2][0][60]	MAIN[2][1][59]	MAIN[2][1][54]	MAIN[2][1][55]	MAIN[2][0][55]	MAIN[2][0][53]	MAIN[2][1][53]	MAIN[2][1][50]	CELL[0].IMUX_BUFG_O[16]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits														Destination
MAIN[2][2][58]	MAIN[2][3][57]	MAIN[2][2][56]	MAIN[2][3][56]	MAIN[2][2][62]	MAIN[2][3][61]	MAIN[2][2][60]	MAIN[2][3][59]	MAIN[2][3][54]	MAIN[2][3][55]	MAIN[2][2][55]	MAIN[2][2][53]	MAIN[2][3][53]	MAIN[2][3][50]	CELL[0].IMUX_BUFG_O[17]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits														Destination
MAIN[2][0][42]	MAIN[2][1][41]	MAIN[2][0][40]	MAIN[2][1][40]	MAIN[2][0][46]	MAIN[2][1][45]	MAIN[2][0][44]	MAIN[2][1][43]	MAIN[2][1][38]	MAIN[2][1][39]	MAIN[2][0][39]	MAIN[2][0][37]	MAIN[2][1][37]	MAIN[2][1][34]	CELL[0].IMUX_BUFG_O[18]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits														Destination
MAIN[2][2][42]	MAIN[2][3][41]	MAIN[2][2][40]	MAIN[2][3][40]	MAIN[2][2][46]	MAIN[2][3][45]	MAIN[2][2][44]	MAIN[2][3][43]	MAIN[2][3][38]	MAIN[2][3][39]	MAIN[2][2][39]	MAIN[2][2][37]	MAIN[2][3][37]	MAIN[2][3][34]	CELL[0].IMUX_BUFG_O[19]
														Source
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0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits														Destination
MAIN[2][0][26]	MAIN[2][1][25]	MAIN[2][0][24]	MAIN[2][1][24]	MAIN[2][0][30]	MAIN[2][1][29]	MAIN[2][0][28]	MAIN[2][1][27]	MAIN[2][1][22]	MAIN[2][1][23]	MAIN[2][0][23]	MAIN[2][0][21]	MAIN[2][1][21]	MAIN[2][1][18]	CELL[0].IMUX_BUFG_O[20]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits														Destination
MAIN[2][2][26]	MAIN[2][3][25]	MAIN[2][2][24]	MAIN[2][3][24]	MAIN[2][2][30]	MAIN[2][3][29]	MAIN[2][2][28]	MAIN[2][3][27]	MAIN[2][3][22]	MAIN[2][3][23]	MAIN[2][2][23]	MAIN[2][2][21]	MAIN[2][3][21]	MAIN[2][3][18]	CELL[0].IMUX_BUFG_O[21]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits														Destination
MAIN[2][0][10]	MAIN[2][1][9]	MAIN[2][0][8]	MAIN[2][1][8]	MAIN[2][0][14]	MAIN[2][1][13]	MAIN[2][0][12]	MAIN[2][1][11]	MAIN[2][1][6]	MAIN[2][1][7]	MAIN[2][0][7]	MAIN[2][0][5]	MAIN[2][1][5]	MAIN[2][1][2]	CELL[0].IMUX_BUFG_O[22]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits														Destination
MAIN[2][2][10]	MAIN[2][3][9]	MAIN[2][2][8]	MAIN[2][3][8]	MAIN[2][2][14]	MAIN[2][3][13]	MAIN[2][2][12]	MAIN[2][3][11]	MAIN[2][3][6]	MAIN[2][3][7]	MAIN[2][2][7]	MAIN[2][2][5]	MAIN[2][3][5]	MAIN[2][3][2]	CELL[0].IMUX_BUFG_O[23]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits														Destination
MAIN[1][0][58]	MAIN[1][1][57]	MAIN[1][0][56]	MAIN[1][1][56]	MAIN[1][0][62]	MAIN[1][1][61]	MAIN[1][0][60]	MAIN[1][1][59]	MAIN[1][1][54]	MAIN[1][1][55]	MAIN[1][0][55]	MAIN[1][0][53]	MAIN[1][1][53]	MAIN[1][1][50]	CELL[0].IMUX_BUFG_O[24]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits														Destination
MAIN[1][2][58]	MAIN[1][3][57]	MAIN[1][2][56]	MAIN[1][3][56]	MAIN[1][2][62]	MAIN[1][3][61]	MAIN[1][2][60]	MAIN[1][3][59]	MAIN[1][3][54]	MAIN[1][3][55]	MAIN[1][2][55]	MAIN[1][2][53]	MAIN[1][3][53]	MAIN[1][3][50]	CELL[0].IMUX_BUFG_O[25]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits														Destination
MAIN[1][0][42]	MAIN[1][1][41]	MAIN[1][0][40]	MAIN[1][1][40]	MAIN[1][0][46]	MAIN[1][1][45]	MAIN[1][0][44]	MAIN[1][1][43]	MAIN[1][1][38]	MAIN[1][1][39]	MAIN[1][0][39]	MAIN[1][0][37]	MAIN[1][1][37]	MAIN[1][1][34]	CELL[0].IMUX_BUFG_O[26]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits														Destination
MAIN[1][2][42]	MAIN[1][3][41]	MAIN[1][2][40]	MAIN[1][3][40]	MAIN[1][2][46]	MAIN[1][3][45]	MAIN[1][2][44]	MAIN[1][3][43]	MAIN[1][3][38]	MAIN[1][3][39]	MAIN[1][2][39]	MAIN[1][2][37]	MAIN[1][3][37]	MAIN[1][3][34]	CELL[0].IMUX_BUFG_O[27]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits														Destination
MAIN[1][0][26]	MAIN[1][1][25]	MAIN[1][0][24]	MAIN[1][1][24]	MAIN[1][0][30]	MAIN[1][1][29]	MAIN[1][0][28]	MAIN[1][1][27]	MAIN[1][1][22]	MAIN[1][1][23]	MAIN[1][0][23]	MAIN[1][0][21]	MAIN[1][1][21]	MAIN[1][1][18]	CELL[0].IMUX_BUFG_O[28]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits														Destination
MAIN[1][2][26]	MAIN[1][3][25]	MAIN[1][2][24]	MAIN[1][3][24]	MAIN[1][2][30]	MAIN[1][3][29]	MAIN[1][2][28]	MAIN[1][3][27]	MAIN[1][3][22]	MAIN[1][3][23]	MAIN[1][2][23]	MAIN[1][2][21]	MAIN[1][3][21]	MAIN[1][3][18]	CELL[0].IMUX_BUFG_O[29]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
0	1	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[18]
1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits														Destination
MAIN[1][0][10]	MAIN[1][1][9]	MAIN[1][0][8]	MAIN[1][1][8]	MAIN[1][0][14]	MAIN[1][1][13]	MAIN[1][0][12]	MAIN[1][1][11]	MAIN[1][1][6]	MAIN[1][1][7]	MAIN[1][0][7]	MAIN[1][0][5]	MAIN[1][1][5]	MAIN[1][1][2]	CELL[0].IMUX_BUFG_O[30]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
0	0	0	1	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[16]
0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

virtex5 CLK_CMT_N switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits														Destination
MAIN[1][2][10]	MAIN[1][3][9]	MAIN[1][2][8]	MAIN[1][3][8]	MAIN[1][2][14]	MAIN[1][3][13]	MAIN[1][2][12]	MAIN[1][3][11]	MAIN[1][3][6]	MAIN[1][3][7]	MAIN[1][2][7]	MAIN[1][2][5]	MAIN[1][3][5]	MAIN[1][3][2]	CELL[0].IMUX_BUFG_O[31]
														Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	0	0	0	0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	0	0	0	0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[8]
0	0	0	0	0	0	0	1	0	0	1	0	0	0	CELL[0].OUT_CMT[4]
0	0	0	0	0	0	0	1	0	1	0	0	0	0	CELL[0].OUT_CMT[12]
0	0	0	0	0	0	0	1	1	0	0	0	0	0	CELL[0].OUT_CMT[20]
0	0	0	0	0	0	1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	0	0	0	0	1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[9]
0	0	0	0	0	0	1	0	0	0	1	0	0	0	CELL[0].OUT_CMT[5]
0	0	0	0	0	0	1	0	0	1	0	0	0	0	CELL[0].OUT_CMT[13]
0	0	0	0	0	0	1	0	1	0	0	0	0	0	CELL[0].OUT_CMT[21]
0	0	0	0	0	1	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	0	0	0	0	1	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[6]
0	0	0	0	0	1	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[14]
0	0	0	0	0	1	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[22]
0	0	0	0	1	0	0	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
0	0	0	0	1	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[7]
0	0	0	0	1	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[15]
0	0	0	0	1	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[23]
0	0	0	1	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[24]
0	0	0	1	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[0]
0	0	0	1	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[8]
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0	0	1	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[25]
0	0	1	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[1]
0	0	1	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[9]
0	0	1	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[17]
0	1	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[26]
0	1	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
0	1	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[2]
0	1	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[10]
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1	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[0].OUT_CMT[27]
1	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]
1	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[0].OUT_CMT[3]
1	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[0].OUT_CMT[11]
1	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[0].OUT_CMT[19]

Bitstream

virtex5 CLK_CMT_N rect MAIN[0]
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B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 9	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 8
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	-
B59	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 13	-
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 10
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1
B52	-	-	-	-
B51	-	-	-	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 9	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 8
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	-
B43	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 13	-
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 12
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 10
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1
B36	-	-	-	-
B35	-	-	-	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 9	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 8
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	-
B27	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 13	-
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 12
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 10
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1
B20	-	-	-	-
B19	-	-	-	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 9	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	-
B11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 13	-
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 12
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 10
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1
B4	-	-	-	-
B3	-	-	-	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 9	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 8
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	-
B59	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 13	-
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 10
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1
B52	-	-	-	-
B51	-	-	-	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 9	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 8
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	-
B43	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 13	-
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 12
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 10
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1
B36	-	-	-	-
B35	-	-	-	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 9	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 8
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	-
B27	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 13	-
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 12
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 10
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1
B20	-	-	-	-
B19	-	-	-	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 9	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	-
B11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 13	-
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 12
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 10
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1
B4	-	-	-	-
B3	-	-	-	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 9	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 8
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	-
B59	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 13	-
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 10
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1
B52	-	-	-	-
B51	-	-	-	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 9	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 8
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	-
B43	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 13	-
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 12
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 10
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1
B36	-	-	-	-
B35	-	-	-	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 9	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 8
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	-
B27	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 13	-
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 12
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 10
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1
B20	-	-	-	-
B19	-	-	-	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 9	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	-
B11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 13	-
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 12
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 10
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1
B4	-	-	-	-
B3	-	-	-	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 9	-
B61	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 8
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	-
B59	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6
B58	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 13	-
B57	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 12
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 10
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4
B54	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B53	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1
B52	-	-	-	-
B51	-	-	-	-
B50	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 9	-
B45	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 8
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-
B43	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6
B42	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 13	-
B41	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 12
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 10
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4
B38	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B37	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1
B36	-	-	-	-
B35	-	-	-	-
B34	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 9	-
B29	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 8
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	-
B27	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6
B26	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 13	-
B25	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 12
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 10
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4
B22	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B21	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1
B20	-	-	-	-
B19	-	-	-	-
B18	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 9	-
B13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 8
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-
B11	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6
B10	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 13	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 13	-
B9	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 12
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 10	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 11	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 10
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4
B6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B5	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1
B4	-	-	-	-
B3	-	-	-	-
B2	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]
B62	-	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]
B61	-	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]
B60	-	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]
B59	-	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_CMT_N rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_MGT_S

Cells: 11

Switchbox CLK_INT

virtex5 CLK_MGT_S switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[1][0][4]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[1][0][3]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[1][0][2]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[1][0][1]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[1][0][0]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[1][2][4]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[1][2][3]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[1][2][2]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[1][2][1]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[1][2][0]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits								Destination
MAIN[5][1][3]	MAIN[5][0][4]	MAIN[5][1][5]	MAIN[5][0][6]	MAIN[5][1][8]	MAIN[5][1][7]	MAIN[5][0][7]	MAIN[5][0][12]	CELL[0].IMUX_BUFG_O[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits								Destination
MAIN[5][3][3]	MAIN[5][2][4]	MAIN[5][3][5]	MAIN[5][2][6]	MAIN[5][3][8]	MAIN[5][3][7]	MAIN[5][2][7]	MAIN[5][2][12]	CELL[0].IMUX_BUFG_O[1]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits								Destination
MAIN[5][1][19]	MAIN[5][0][20]	MAIN[5][1][21]	MAIN[5][0][22]	MAIN[5][1][24]	MAIN[5][1][23]	MAIN[5][0][23]	MAIN[5][0][28]	CELL[0].IMUX_BUFG_O[2]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits								Destination
MAIN[5][3][19]	MAIN[5][2][20]	MAIN[5][3][21]	MAIN[5][2][22]	MAIN[5][3][24]	MAIN[5][3][23]	MAIN[5][2][23]	MAIN[5][2][28]	CELL[0].IMUX_BUFG_O[3]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits								Destination
MAIN[5][1][35]	MAIN[5][0][36]	MAIN[5][1][37]	MAIN[5][0][38]	MAIN[5][1][40]	MAIN[5][1][39]	MAIN[5][0][39]	MAIN[5][0][44]	CELL[0].IMUX_BUFG_O[4]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits								Destination
MAIN[5][3][35]	MAIN[5][2][36]	MAIN[5][3][37]	MAIN[5][2][38]	MAIN[5][3][40]	MAIN[5][3][39]	MAIN[5][2][39]	MAIN[5][2][44]	CELL[0].IMUX_BUFG_O[5]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits								Destination
MAIN[5][1][51]	MAIN[5][0][52]	MAIN[5][1][53]	MAIN[5][0][54]	MAIN[5][1][56]	MAIN[5][1][55]	MAIN[5][0][55]	MAIN[5][0][60]	CELL[0].IMUX_BUFG_O[6]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits								Destination
MAIN[5][3][51]	MAIN[5][2][52]	MAIN[5][3][53]	MAIN[5][2][54]	MAIN[5][3][56]	MAIN[5][3][55]	MAIN[5][2][55]	MAIN[5][2][60]	CELL[0].IMUX_BUFG_O[7]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits								Destination
MAIN[6][1][3]	MAIN[6][0][4]	MAIN[6][1][5]	MAIN[6][0][6]	MAIN[6][1][8]	MAIN[6][1][7]	MAIN[6][0][7]	MAIN[6][0][12]	CELL[0].IMUX_BUFG_O[8]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits								Destination
MAIN[6][3][3]	MAIN[6][2][4]	MAIN[6][3][5]	MAIN[6][2][6]	MAIN[6][3][8]	MAIN[6][3][7]	MAIN[6][2][7]	MAIN[6][2][12]	CELL[0].IMUX_BUFG_O[9]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits								Destination
MAIN[6][1][19]	MAIN[6][0][20]	MAIN[6][1][21]	MAIN[6][0][22]	MAIN[6][1][24]	MAIN[6][1][23]	MAIN[6][0][23]	MAIN[6][0][28]	CELL[0].IMUX_BUFG_O[10]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits								Destination
MAIN[6][3][19]	MAIN[6][2][20]	MAIN[6][3][21]	MAIN[6][2][22]	MAIN[6][3][24]	MAIN[6][3][23]	MAIN[6][2][23]	MAIN[6][2][28]	CELL[0].IMUX_BUFG_O[11]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits								Destination
MAIN[6][1][35]	MAIN[6][0][36]	MAIN[6][1][37]	MAIN[6][0][38]	MAIN[6][1][40]	MAIN[6][1][39]	MAIN[6][0][39]	MAIN[6][0][44]	CELL[0].IMUX_BUFG_O[12]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits								Destination
MAIN[6][3][35]	MAIN[6][2][36]	MAIN[6][3][37]	MAIN[6][2][38]	MAIN[6][3][40]	MAIN[6][3][39]	MAIN[6][2][39]	MAIN[6][2][44]	CELL[0].IMUX_BUFG_O[13]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits								Destination
MAIN[6][1][51]	MAIN[6][0][52]	MAIN[6][1][53]	MAIN[6][0][54]	MAIN[6][1][56]	MAIN[6][1][55]	MAIN[6][0][55]	MAIN[6][0][60]	CELL[0].IMUX_BUFG_O[14]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits								Destination
MAIN[6][3][51]	MAIN[6][2][52]	MAIN[6][3][53]	MAIN[6][2][54]	MAIN[6][3][56]	MAIN[6][3][55]	MAIN[6][2][55]	MAIN[6][2][60]	CELL[0].IMUX_BUFG_O[15]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits								Destination
MAIN[7][1][3]	MAIN[7][0][4]	MAIN[7][1][5]	MAIN[7][0][6]	MAIN[7][1][8]	MAIN[7][1][7]	MAIN[7][0][7]	MAIN[7][0][12]	CELL[0].IMUX_BUFG_O[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits								Destination
MAIN[7][3][3]	MAIN[7][2][4]	MAIN[7][3][5]	MAIN[7][2][6]	MAIN[7][3][8]	MAIN[7][3][7]	MAIN[7][2][7]	MAIN[7][2][12]	CELL[0].IMUX_BUFG_O[17]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits								Destination
MAIN[7][1][19]	MAIN[7][0][20]	MAIN[7][1][21]	MAIN[7][0][22]	MAIN[7][1][24]	MAIN[7][1][23]	MAIN[7][0][23]	MAIN[7][0][28]	CELL[0].IMUX_BUFG_O[18]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits								Destination
MAIN[7][3][19]	MAIN[7][2][20]	MAIN[7][3][21]	MAIN[7][2][22]	MAIN[7][3][24]	MAIN[7][3][23]	MAIN[7][2][23]	MAIN[7][2][28]	CELL[0].IMUX_BUFG_O[19]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits								Destination
MAIN[7][1][35]	MAIN[7][0][36]	MAIN[7][1][37]	MAIN[7][0][38]	MAIN[7][1][40]	MAIN[7][1][39]	MAIN[7][0][39]	MAIN[7][0][44]	CELL[0].IMUX_BUFG_O[20]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits								Destination
MAIN[7][3][35]	MAIN[7][2][36]	MAIN[7][3][37]	MAIN[7][2][38]	MAIN[7][3][40]	MAIN[7][3][39]	MAIN[7][2][39]	MAIN[7][2][44]	CELL[0].IMUX_BUFG_O[21]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits								Destination
MAIN[7][1][51]	MAIN[7][0][52]	MAIN[7][1][53]	MAIN[7][0][54]	MAIN[7][1][56]	MAIN[7][1][55]	MAIN[7][0][55]	MAIN[7][0][60]	CELL[0].IMUX_BUFG_O[22]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits								Destination
MAIN[7][3][51]	MAIN[7][2][52]	MAIN[7][3][53]	MAIN[7][2][54]	MAIN[7][3][56]	MAIN[7][3][55]	MAIN[7][2][55]	MAIN[7][2][60]	CELL[0].IMUX_BUFG_O[23]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits								Destination
MAIN[8][1][3]	MAIN[8][0][4]	MAIN[8][1][5]	MAIN[8][0][6]	MAIN[8][1][8]	MAIN[8][1][7]	MAIN[8][0][7]	MAIN[8][0][12]	CELL[0].IMUX_BUFG_O[24]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits								Destination
MAIN[8][3][3]	MAIN[8][2][4]	MAIN[8][3][5]	MAIN[8][2][6]	MAIN[8][3][8]	MAIN[8][3][7]	MAIN[8][2][7]	MAIN[8][2][12]	CELL[0].IMUX_BUFG_O[25]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits								Destination
MAIN[8][1][19]	MAIN[8][0][20]	MAIN[8][1][21]	MAIN[8][0][22]	MAIN[8][1][24]	MAIN[8][1][23]	MAIN[8][0][23]	MAIN[8][0][28]	CELL[0].IMUX_BUFG_O[26]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits								Destination
MAIN[8][3][19]	MAIN[8][2][20]	MAIN[8][3][21]	MAIN[8][2][22]	MAIN[8][3][24]	MAIN[8][3][23]	MAIN[8][2][23]	MAIN[8][2][28]	CELL[0].IMUX_BUFG_O[27]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits								Destination
MAIN[8][1][35]	MAIN[8][0][36]	MAIN[8][1][37]	MAIN[8][0][38]	MAIN[8][1][40]	MAIN[8][1][39]	MAIN[8][0][39]	MAIN[8][0][44]	CELL[0].IMUX_BUFG_O[28]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits								Destination
MAIN[8][3][35]	MAIN[8][2][36]	MAIN[8][3][37]	MAIN[8][2][38]	MAIN[8][3][40]	MAIN[8][3][39]	MAIN[8][2][39]	MAIN[8][2][44]	CELL[0].IMUX_BUFG_O[29]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits								Destination
MAIN[8][1][51]	MAIN[8][0][52]	MAIN[8][1][53]	MAIN[8][0][54]	MAIN[8][1][56]	MAIN[8][1][55]	MAIN[8][0][55]	MAIN[8][0][60]	CELL[0].IMUX_BUFG_O[30]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_S switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits								Destination
MAIN[8][3][51]	MAIN[8][2][52]	MAIN[8][3][53]	MAIN[8][2][54]	MAIN[8][3][56]	MAIN[8][3][55]	MAIN[8][2][55]	MAIN[8][2][60]	CELL[0].IMUX_BUFG_O[31]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

Bitstream

virtex5 CLK_MGT_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]	-
B3	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]	-
B2	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]	-
B1	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]	-
B0	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]	-

virtex5 CLK_MGT_S rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B55	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B54	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4	-
B53	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B52	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-
B51	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B39	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B38	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4	-
B37	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B36	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-
B35	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B23	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B22	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4	-
B21	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B20	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-
B19	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B7	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B6	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4	-
B5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B4	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-
B3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_S rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

Tile CLK_MGT_N

Cells: 11

Switchbox CLK_INT

virtex5 CLK_MGT_N switchbox CLK_INT programmable buffers
Destination	Source	Bit
CELL[0].MGT_BUF[0]	CELL[0].MGT_ROW_I[0]	MAIN[8][0][59]
CELL[0].MGT_BUF[1]	CELL[0].MGT_ROW_I[1]	MAIN[8][0][60]
CELL[0].MGT_BUF[2]	CELL[0].MGT_ROW_I[2]	MAIN[8][0][61]
CELL[0].MGT_BUF[3]	CELL[0].MGT_ROW_I[3]	MAIN[8][0][62]
CELL[0].MGT_BUF[4]	CELL[0].MGT_ROW_I[4]	MAIN[8][0][63]
CELL[0].MGT_BUF[5]	CELL_E.MGT_ROW_I[0]	MAIN[8][2][59]
CELL[0].MGT_BUF[6]	CELL_E.MGT_ROW_I[1]	MAIN[8][2][60]
CELL[0].MGT_BUF[7]	CELL_E.MGT_ROW_I[2]	MAIN[8][2][61]
CELL[0].MGT_BUF[8]	CELL_E.MGT_ROW_I[3]	MAIN[8][2][62]
CELL[0].MGT_BUF[9]	CELL_E.MGT_ROW_I[4]	MAIN[8][2][63]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[0]
Bits								Destination
MAIN[4][1][60]	MAIN[4][0][59]	MAIN[4][1][58]	MAIN[4][0][57]	MAIN[4][1][55]	MAIN[4][1][56]	MAIN[4][0][56]	MAIN[4][0][51]	CELL[0].IMUX_BUFG_O[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[0]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[1]
Bits								Destination
MAIN[4][3][60]	MAIN[4][2][59]	MAIN[4][3][58]	MAIN[4][2][57]	MAIN[4][3][55]	MAIN[4][3][56]	MAIN[4][2][56]	MAIN[4][2][51]	CELL[0].IMUX_BUFG_O[1]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[1]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[2]
Bits								Destination
MAIN[4][1][44]	MAIN[4][0][43]	MAIN[4][1][42]	MAIN[4][0][41]	MAIN[4][1][39]	MAIN[4][1][40]	MAIN[4][0][40]	MAIN[4][0][35]	CELL[0].IMUX_BUFG_O[2]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[2]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[3]
Bits								Destination
MAIN[4][3][44]	MAIN[4][2][43]	MAIN[4][3][42]	MAIN[4][2][41]	MAIN[4][3][39]	MAIN[4][3][40]	MAIN[4][2][40]	MAIN[4][2][35]	CELL[0].IMUX_BUFG_O[3]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[3]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[4]
Bits								Destination
MAIN[4][1][28]	MAIN[4][0][27]	MAIN[4][1][26]	MAIN[4][0][25]	MAIN[4][1][23]	MAIN[4][1][24]	MAIN[4][0][24]	MAIN[4][0][19]	CELL[0].IMUX_BUFG_O[4]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[4]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[5]
Bits								Destination
MAIN[4][3][28]	MAIN[4][2][27]	MAIN[4][3][26]	MAIN[4][2][25]	MAIN[4][3][23]	MAIN[4][3][24]	MAIN[4][2][24]	MAIN[4][2][19]	CELL[0].IMUX_BUFG_O[5]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[5]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[6]
Bits								Destination
MAIN[4][1][12]	MAIN[4][0][11]	MAIN[4][1][10]	MAIN[4][0][9]	MAIN[4][1][7]	MAIN[4][1][8]	MAIN[4][0][8]	MAIN[4][0][3]	CELL[0].IMUX_BUFG_O[6]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[6]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[7]
Bits								Destination
MAIN[4][3][12]	MAIN[4][2][11]	MAIN[4][3][10]	MAIN[4][2][9]	MAIN[4][3][7]	MAIN[4][3][8]	MAIN[4][2][8]	MAIN[4][2][3]	CELL[0].IMUX_BUFG_O[7]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[7]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[8]
Bits								Destination
MAIN[3][1][60]	MAIN[3][0][59]	MAIN[3][1][58]	MAIN[3][0][57]	MAIN[3][1][55]	MAIN[3][1][56]	MAIN[3][0][56]	MAIN[3][0][51]	CELL[0].IMUX_BUFG_O[8]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[8]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[9]
Bits								Destination
MAIN[3][3][60]	MAIN[3][2][59]	MAIN[3][3][58]	MAIN[3][2][57]	MAIN[3][3][55]	MAIN[3][3][56]	MAIN[3][2][56]	MAIN[3][2][51]	CELL[0].IMUX_BUFG_O[9]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[9]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[10]
Bits								Destination
MAIN[3][1][44]	MAIN[3][0][43]	MAIN[3][1][42]	MAIN[3][0][41]	MAIN[3][1][39]	MAIN[3][1][40]	MAIN[3][0][40]	MAIN[3][0][35]	CELL[0].IMUX_BUFG_O[10]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[11]
Bits								Destination
MAIN[3][3][44]	MAIN[3][2][43]	MAIN[3][3][42]	MAIN[3][2][41]	MAIN[3][3][39]	MAIN[3][3][40]	MAIN[3][2][40]	MAIN[3][2][35]	CELL[0].IMUX_BUFG_O[11]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[12]
Bits								Destination
MAIN[3][1][28]	MAIN[3][0][27]	MAIN[3][1][26]	MAIN[3][0][25]	MAIN[3][1][23]	MAIN[3][1][24]	MAIN[3][0][24]	MAIN[3][0][19]	CELL[0].IMUX_BUFG_O[12]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[13]
Bits								Destination
MAIN[3][3][28]	MAIN[3][2][27]	MAIN[3][3][26]	MAIN[3][2][25]	MAIN[3][3][23]	MAIN[3][3][24]	MAIN[3][2][24]	MAIN[3][2][19]	CELL[0].IMUX_BUFG_O[13]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[14]
Bits								Destination
MAIN[3][1][12]	MAIN[3][0][11]	MAIN[3][1][10]	MAIN[3][0][9]	MAIN[3][1][7]	MAIN[3][1][8]	MAIN[3][0][8]	MAIN[3][0][3]	CELL[0].IMUX_BUFG_O[14]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[15]
Bits								Destination
MAIN[3][3][12]	MAIN[3][2][11]	MAIN[3][3][10]	MAIN[3][2][9]	MAIN[3][3][7]	MAIN[3][3][8]	MAIN[3][2][8]	MAIN[3][2][3]	CELL[0].IMUX_BUFG_O[15]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[16]
Bits								Destination
MAIN[2][1][60]	MAIN[2][0][59]	MAIN[2][1][58]	MAIN[2][0][57]	MAIN[2][1][55]	MAIN[2][1][56]	MAIN[2][0][56]	MAIN[2][0][51]	CELL[0].IMUX_BUFG_O[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[17]
Bits								Destination
MAIN[2][3][60]	MAIN[2][2][59]	MAIN[2][3][58]	MAIN[2][2][57]	MAIN[2][3][55]	MAIN[2][3][56]	MAIN[2][2][56]	MAIN[2][2][51]	CELL[0].IMUX_BUFG_O[17]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[18]
Bits								Destination
MAIN[2][1][44]	MAIN[2][0][43]	MAIN[2][1][42]	MAIN[2][0][41]	MAIN[2][1][39]	MAIN[2][1][40]	MAIN[2][0][40]	MAIN[2][0][35]	CELL[0].IMUX_BUFG_O[18]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[19]
Bits								Destination
MAIN[2][3][44]	MAIN[2][2][43]	MAIN[2][3][42]	MAIN[2][2][41]	MAIN[2][3][39]	MAIN[2][3][40]	MAIN[2][2][40]	MAIN[2][2][35]	CELL[0].IMUX_BUFG_O[19]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[20]
Bits								Destination
MAIN[2][1][28]	MAIN[2][0][27]	MAIN[2][1][26]	MAIN[2][0][25]	MAIN[2][1][23]	MAIN[2][1][24]	MAIN[2][0][24]	MAIN[2][0][19]	CELL[0].IMUX_BUFG_O[20]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[21]
Bits								Destination
MAIN[2][3][28]	MAIN[2][2][27]	MAIN[2][3][26]	MAIN[2][2][25]	MAIN[2][3][23]	MAIN[2][3][24]	MAIN[2][2][24]	MAIN[2][2][19]	CELL[0].IMUX_BUFG_O[21]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[22]
Bits								Destination
MAIN[2][1][12]	MAIN[2][0][11]	MAIN[2][1][10]	MAIN[2][0][9]	MAIN[2][1][7]	MAIN[2][1][8]	MAIN[2][0][8]	MAIN[2][0][3]	CELL[0].IMUX_BUFG_O[22]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[23]
Bits								Destination
MAIN[2][3][12]	MAIN[2][2][11]	MAIN[2][3][10]	MAIN[2][2][9]	MAIN[2][3][7]	MAIN[2][3][8]	MAIN[2][2][8]	MAIN[2][2][3]	CELL[0].IMUX_BUFG_O[23]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[24]
Bits								Destination
MAIN[1][1][60]	MAIN[1][0][59]	MAIN[1][1][58]	MAIN[1][0][57]	MAIN[1][1][55]	MAIN[1][1][56]	MAIN[1][0][56]	MAIN[1][0][51]	CELL[0].IMUX_BUFG_O[24]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[25]
Bits								Destination
MAIN[1][3][60]	MAIN[1][2][59]	MAIN[1][3][58]	MAIN[1][2][57]	MAIN[1][3][55]	MAIN[1][3][56]	MAIN[1][2][56]	MAIN[1][2][51]	CELL[0].IMUX_BUFG_O[25]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[26]
Bits								Destination
MAIN[1][1][44]	MAIN[1][0][43]	MAIN[1][1][42]	MAIN[1][0][41]	MAIN[1][1][39]	MAIN[1][1][40]	MAIN[1][0][40]	MAIN[1][0][35]	CELL[0].IMUX_BUFG_O[26]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[27]
Bits								Destination
MAIN[1][3][44]	MAIN[1][2][43]	MAIN[1][3][42]	MAIN[1][2][41]	MAIN[1][3][39]	MAIN[1][3][40]	MAIN[1][2][40]	MAIN[1][2][35]	CELL[0].IMUX_BUFG_O[27]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[28]
Bits								Destination
MAIN[1][1][28]	MAIN[1][0][27]	MAIN[1][1][26]	MAIN[1][0][25]	MAIN[1][1][23]	MAIN[1][1][24]	MAIN[1][0][24]	MAIN[1][0][19]	CELL[0].IMUX_BUFG_O[28]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[29]
Bits								Destination
MAIN[1][3][28]	MAIN[1][2][27]	MAIN[1][3][26]	MAIN[1][2][25]	MAIN[1][3][23]	MAIN[1][3][24]	MAIN[1][2][24]	MAIN[1][2][19]	CELL[0].IMUX_BUFG_O[29]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[30]
Bits								Destination
MAIN[1][1][12]	MAIN[1][0][11]	MAIN[1][1][10]	MAIN[1][0][9]	MAIN[1][1][7]	MAIN[1][1][8]	MAIN[1][0][8]	MAIN[1][0][3]	CELL[0].IMUX_BUFG_O[30]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

virtex5 CLK_MGT_N switchbox CLK_INT muxes IMUX_BUFG_O[31]
Bits								Destination
MAIN[1][3][12]	MAIN[1][2][11]	MAIN[1][3][10]	MAIN[1][2][9]	MAIN[1][3][7]	MAIN[1][3][8]	MAIN[1][2][8]	MAIN[1][2][3]	CELL[0].IMUX_BUFG_O[31]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	1	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	1	0	CELL[0].MGT_BUF[0]
0	0	0	1	0	1	0	0	CELL[0].MGT_BUF[4]
0	0	0	1	1	0	0	0	CELL[0].MGT_BUF[8]
0	0	1	0	0	0	1	0	CELL[0].MGT_BUF[1]
0	0	1	0	0	1	0	0	CELL[0].MGT_BUF[5]
0	0	1	0	1	0	0	0	CELL[0].MGT_BUF[9]
0	1	0	0	0	0	1	0	CELL[0].MGT_BUF[2]
0	1	0	0	0	1	0	0	CELL[0].MGT_BUF[6]
1	0	0	0	0	0	1	0	CELL[0].MGT_BUF[3]
1	0	0	0	0	1	0	0	CELL[0].MGT_BUF[7]

Bitstream

virtex5 CLK_MGT_N rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2
B55	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2
B39	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2
B23	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2
B7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2
B55	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2
B39	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2
B23	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2
B7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2
B55	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2
B39	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2
B23	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2
B7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7
B59	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	-
B58	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5
B57	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4	-
B56	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2
B55	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	CLK_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7
B43	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	-
B42	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5
B41	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4	-
B40	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2
B39	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	CLK_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7
B27	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	-
B26	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5
B25	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4	-
B24	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2
B23	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	CLK_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7
B11	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	-
B10	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5
B9	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4	-
B8	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2
B7	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	CLK_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	-	CLK_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3
B63	CLK_INT: buffer CELL[0].MGT_BUF[4] ← CELL[0].MGT_ROW_I[4]	-	CLK_INT: buffer CELL[0].MGT_BUF[9] ← CELL_E.MGT_ROW_I[4]	-
B62	CLK_INT: buffer CELL[0].MGT_BUF[3] ← CELL[0].MGT_ROW_I[3]	-	CLK_INT: buffer CELL[0].MGT_BUF[8] ← CELL_E.MGT_ROW_I[3]	-
B61	CLK_INT: buffer CELL[0].MGT_BUF[2] ← CELL[0].MGT_ROW_I[2]	-	CLK_INT: buffer CELL[0].MGT_BUF[7] ← CELL_E.MGT_ROW_I[2]	-
B60	CLK_INT: buffer CELL[0].MGT_BUF[1] ← CELL[0].MGT_ROW_I[1]	-	CLK_INT: buffer CELL[0].MGT_BUF[6] ← CELL_E.MGT_ROW_I[1]	-
B59	CLK_INT: buffer CELL[0].MGT_BUF[0] ← CELL[0].MGT_ROW_I[0]	-	CLK_INT: buffer CELL[0].MGT_BUF[5] ← CELL_E.MGT_ROW_I[0]	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

virtex5 CLK_MGT_N rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3
B63	-	-	-	-
B62	-	-	-	-
B61	-	-	-	-
B60	-	-	-	-
B59	-	-	-	-
B58	-	-	-	-
B57	-	-	-	-
B56	-	-	-	-
B55	-	-	-	-
B54	-	-	-	-
B53	-	-	-	-
B52	-	-	-	-
B51	-	-	-	-
B50	-	-	-	-
B49	-	-	-	-
B48	-	-	-	-
B47	-	-	-	-
B46	-	-	-	-
B45	-	-	-	-
B44	-	-	-	-
B43	-	-	-	-
B42	-	-	-	-
B41	-	-	-	-
B40	-	-	-	-
B39	-	-	-	-
B38	-	-	-	-
B37	-	-	-	-
B36	-	-	-	-
B35	-	-	-	-
B34	-	-	-	-
B33	-	-	-	-
B32	-	-	-	-
B31	-	-	-	-
B30	-	-	-	-
B29	-	-	-	-
B28	-	-	-	-
B27	-	-	-	-
B26	-	-	-	-
B25	-	-	-	-
B24	-	-	-	-
B23	-	-	-	-
B22	-	-	-	-
B21	-	-	-	-
B20	-	-	-	-
B19	-	-	-	-
B18	-	-	-	-
B17	-	-	-	-
B16	-	-	-	-
B15	-	-	-	-
B14	-	-	-	-
B13	-	-	-	-
B12	-	-	-	-
B11	-	-	-	-
B10	-	-	-	-
B9	-	-	-	-
B8	-	-	-	-
B7	-	-	-	-
B6	-	-	-	-
B5	-	-	-	-
B4	-	-	-	-
B3	-	-	-	-
B2	-	-	-	-
B1	-	-	-	-
B0	-	-	-	-

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