Virtex 5 devices have up to three I/O columns:
the left I/O column, containing only IO tiles; if the device has no transceivers on the left side, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column; it is always present
the center column, part of which contains IO tiles; the IO tiles in this column come in up to four segments:
the lower segment (variable size, not present on all devices), between the bottom edge of the device and the lower CMTs
the lower middle segment (always 20 tiles high), between lower CMTs and the configuration center
the upper middle segment (always 20 tiles high), between the configuration center and the upper CMTs
the upper segment (variable size, not present on all devices), between the device and the upper CMTs and the top edge of the device
the right I/O column, containing only IO tiles; it is present on all devices except for xc5vlx20t
; if present, it is somewhat to the left of the device's right edge
Virtex 5 has the following banks:
bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:
CCLK
CS_B
DONE
D_OUT_BUSY
D_IN
HSWAPEN
INIT
M0
M1
M2
PROGRAM_B
RDWR_B
TCK
TDI
TDO
TMS
bank 0 is not associated with any IO tiles
banks 1-4: middle segments of the center column; each of them consists of 10 IO tiles; they contain global clock inputs and shared configuration pins
bank 1: immediately above configuration center
bank 2: immediately below configuration center
bank 3: above bank 1, below upper CMTs (not present on xc5vlx20t
)
bank 4: below bank 2, above lower CMTs
banks 5-10: lower and upper segments of the center column; each of them consists of 20 IO tiles
banks 5, 7, 9 are the upper segment, with bank 5 being immediately above upper CMTs; bank number increases upwards
banks 6, 8, 10 are the lower segment, with bank 6 being immediately below lower CMTs; bank number increases downwards
banks 11 and up: left and right column; each of them consists of 20 IO tiles
banks 11, 15, 19, 23, ...: left column, above the configuration center; bank number increases upwards, starting from bank 11 immediately above the configuration center row
banks 12, 16, 20, 24, ...: right column, above the configuration center; bank number increases upwards, starting from bank 12 immediately above the configuration center row
banks 13, 17, 21, 25, ...: left column, below the configuration center; bank number increases downwards, starting from bank 13 immediately below the configuration center row
banks 14, 18, 22, 26, ...: right column, below the configuration center; bank number increases downwards, starting from bank 14 immediately below the configuration center row
All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1
is the "true" pin of the pair, while IOB0
is the "complemented" pin. Differential input and true differential output is supported on all pins of the device.
IOB1
pads in the 4 rows surronding the HCLK row (that is, in rows 8-11 of every clock region) are considered "clock-capable". They can drive BUFIO
and BUFR
buffers via dedicated connections. While Xilinx documentation also considers IOB0
pads clock-capable, this only means that they can be used together with IOB1
as a differential pair.
The IOB1
pads in banks 3 and 4 are considered "global clock-capable". They can drive BUFGCTRL
buffers and CMT primitives via dedicated connections. Likewise, Xilinx considers IOB0
pads to be clock-capable, but they can only drive clocks as part of differential pair with IOB1
.
The IOB0
in rows 5 and 15 of every region is capable of being used as a VREF pad.
Each bank except for banks 1 and 2 has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0
and VRN located on IOB1
. The relevant tile is located as follows:
bank 1 and 2: VRP/VRN are not present in this bank (DCI can still be used by cascade from banks 3 and 4)
bank 3: row 7 of the bank (or row 7 of the region)
bank 4: row 2 of the bank (or row 12 of the region)
banks 5 and up: row 7 of the bank (or row 7 of the region)
In parallel configuration modes, some I/O pads in banks 1-4 are borrowed for configuration use, as the parallel data pins:
bank 4 row 6 IOB0
: D[8]
bank 4 row 6 IOB1
: D[9]
bank 4 row 7 IOB0
: D[10]
bank 4 row 7 IOB1
: D[11]
bank 4 row 8 IOB0
: D[12]
bank 4 row 8 IOB1
: D[13]
bank 4 row 9 IOB0
: D[14]
bank 4 row 9 IOB1
: D[15]
bank 2 row 0 IOB0
: D[0]/FS[0]
bank 2 row 0 IOB1
: D[1]/FS[1]
bank 2 row 1 IOB0
: D[2]/FS[2]
bank 2 row 1 IOB1
: D[3]
bank 2 row 2 IOB0
: D[4]
bank 2 row 2 IOB1
: D[5]
bank 2 row 3 IOB0
: D[6]
bank 2 row 3 IOB1
: D[7]
bank 2 row 4 IOB0
: CSO_B
bank 2 row 4 IOB1
: FWE_B
bank 2 row 5 IOB0
: FOE_B/MOSI
bank 2 row 5 IOB1
: FCS_B
bank 2 row 6 IOB0
: A[20]
bank 2 row 6 IOB1
: A[21]
bank 2 row 7 IOB0
: A[22]
bank 2 row 7 IOB1
: A[23]
bank 2 row 8 IOB0
: A[24]
bank 2 row 8 IOB1
: A[25]
bank 2 row 9 IOB0
: RS[0]
bank 2 row 9 IOB1
: RS[1]
bank 1 row 0 IOB0
: D[16]/A[0]
bank 1 row 0 IOB1
: D[17]/A[1]
bank 1 row 1 IOB0
: D[18]/A[2]
bank 1 row 1 IOB1
: D[19]/A[3]
bank 1 row 2 IOB0
: D[20]/A[4]
bank 1 row 2 IOB1
: D[21]/A[5]
bank 1 row 3 IOB0
: D[22]/A[6]
bank 1 row 3 IOB1
: D[23]/A[7]
bank 1 row 4 IOB0
: D[24]/A[8]
bank 1 row 4 IOB1
: D[25]/A[9]
bank 1 row 5 IOB0
: D[26]/A[10]
bank 1 row 5 IOB1
: D[27]/A[11]
bank 1 row 6 IOB0
: D[28]/A[12]
bank 1 row 6 IOB1
: D[29]/A[13]
bank 1 row 7 IOB0
: D[30]/A[14]
bank 1 row 7 IOB1
: D[31]/A[15]
bank 1 row 8 IOB0
: A[16]
bank 1 row 8 IOB1
: A[17]
bank 1 row 9 IOB0
: A[18]
bank 1 row 9 IOB1
: A[19]
The SYSMON
present on the device can use up to 16 IOB pairs from the left I/O column as auxiliary analog differential inputs. The VPx
input corresponds to IOB1
and VNx
corresponds to IOB0
within the same tile. The IOBs are in the following tiles, where r
is the configuration center row:
VP0/VN0
: left I/O column, row r - 10
VP1/VN1
: left I/O column, row r - 9
VP2/VN2
: left I/O column, row r - 8
VP3/VN3
: left I/O column, row r - 7
VP4/VN4
: left I/O column, row r - 6
VP5/VN5
: left I/O column, row r - 4
VP6/VN6
: left I/O column, row r - 3
VP7/VN7
: left I/O column, row r - 2
VP8/VN8
: left I/O column, row r - 1
VP9/VN9
: left I/O column, row r
VP10/VN10
: left I/O column, row r + 1
VP11/VN11
: left I/O column, row r + 2
VP12/VN12
: left I/O column, row r + 3
VP13/VN13
: left I/O column, row r + 4
VP14/VN14
: left I/O column, row r + 8
VP15/VN15
: left I/O column, row r + 9
ILOGIC0:BITSLIP_ENABLE
0.31.16
0.29.30
0.29.26
0.29.15
0.29.12
0.28.22
0.28.18
ILOGIC1:BITSLIP_ENABLE
0.31.47
0.29.51
0.29.48
0.29.37
0.29.33
0.28.45
0.28.41
non-inverted
[6]
[5]
[4]
[3]
[2]
[1]
[0]
ILOGIC0:BITSLIP_SYNC
0.29.19
ILOGIC0:IFF_DELAY_ENABLE
0.31.17
ILOGIC0:IFF_REV_USED
0.30.25
ILOGIC0:IFF_SR_SYNC
0.31.24
ILOGIC0:IFF_SR_USED
0.31.26
ILOGIC0:IFF_TSBYPASS_ENABLE
0.30.17
ILOGIC0:INV.CLKDIV
0.28.6
ILOGIC0:INV.OCLK1
0.30.12
ILOGIC0:INV.OCLK2
0.30.14
ILOGIC0:I_DELAY_ENABLE
0.30.31
ILOGIC0:I_TSBYPASS_ENABLE
0.31.31
ILOGIC0:READBACK_I
0.29.13
ILOGIC0:SERDES
0.28.23
ILOGIC1:BITSLIP_SYNC
0.29.44
ILOGIC1:IFF_DELAY_ENABLE
0.31.46
ILOGIC1:IFF_REV_USED
0.30.38
ILOGIC1:IFF_SR_SYNC
0.31.39
ILOGIC1:IFF_SR_USED
0.31.37
ILOGIC1:IFF_TSBYPASS_ENABLE
0.30.46
ILOGIC1:INV.CLKDIV
0.28.57
ILOGIC1:INV.OCLK1
0.30.51
ILOGIC1:INV.OCLK2
0.30.49
ILOGIC1:I_DELAY_ENABLE
0.30.32
ILOGIC1:I_TSBYPASS_ENABLE
0.31.32
ILOGIC1:READBACK_I
0.29.50
ILOGIC1:SERDES
0.28.40
IOB0:DCI_T
0.36.12
IOB0:OUTPUT_DELAY
0.36.7
IOB0:VR
0.36.3
IOB0:VREF_SYSMON
0.36.30
IOB1:DCI_T
0.36.51
IOB1:OUTPUT_DELAY
0.36.56
IOB1:VR
0.36.60
IOB1:VREF_SYSMON
0.36.33
IODELAY0:DELAYCHAIN_OSC
0.31.2
IODELAY0:HIGH_PERFORMANCE_MODE
0.32.14
IODELAY1:DELAYCHAIN_OSC
0.31.61
IODELAY1:HIGH_PERFORMANCE_MODE
0.32.49
OLOGIC0:INV.CLKDIV
0.34.13
OLOGIC0:INV.D1
0.32.24
OLOGIC0:INV.D2
0.32.23
OLOGIC0:INV.D3
0.35.23
OLOGIC0:INV.D4
0.34.20
OLOGIC0:INV.D5
0.34.23
OLOGIC0:INV.D6
0.35.25
OLOGIC0:MISR_ENABLE
0.28.16
OLOGIC0:MISR_ENABLE_FDBK
0.29.18
OLOGIC0:MISR_RESET
0.28.15
OLOGIC0:OFF_REV_USED
0.34.26
OLOGIC0:OFF_SR_USED
0.34.27
OLOGIC0:SERDES
0.35.20
OLOGIC0:TFF_REV_USED
0.34.15
OLOGIC0:TFF_SR_USED
0.35.15
OLOGIC1:INV.CLKDIV
0.34.50
OLOGIC1:INV.D1
0.32.39
OLOGIC1:INV.D2
0.32.40
OLOGIC1:INV.D3
0.35.40
OLOGIC1:INV.D4
0.34.43
OLOGIC1:INV.D5
0.34.40
OLOGIC1:INV.D6
0.35.38
OLOGIC1:MISR_ENABLE
0.28.47
OLOGIC1:MISR_ENABLE_FDBK
0.29.45
OLOGIC1:MISR_RESET
0.28.48
OLOGIC1:OFF_REV_USED
0.34.37
OLOGIC1:OFF_SR_USED
0.34.36
OLOGIC1:SERDES
0.35.43
OLOGIC1:TFF_REV_USED
0.34.48
OLOGIC1:TFF_SR_USED
0.35.48
non-inverted
[0]
ILOGIC0:DATA_RATE
0.31.6
ILOGIC1:DATA_RATE
0.31.57
DDR
0
SDR
1
ILOGIC0:DATA_WIDTH
0.31.5
0.31.8
0.31.7
0.30.5
ILOGIC1:DATA_WIDTH
0.31.58
0.31.55
0.31.56
0.30.58
NONE
0
0
0
0
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
10
1
0
1
0
ILOGIC0:DDR_CLK_EDGE
0.28.30
0.29.31
ILOGIC1:DDR_CLK_EDGE
0.28.33
0.29.32
SAME_EDGE_PIPELINED
0
0
OPPOSITE_EDGE
0
1
SAME_EDGE
1
0
ILOGIC0:IFF1_INIT
0.28.26
ILOGIC0:IFF1_SRVAL
0.28.24
ILOGIC0:IFF2_INIT
0.29.20
ILOGIC0:IFF2_SRVAL
0.29.22
ILOGIC0:IFF3_INIT
0.28.27
ILOGIC0:IFF3_SRVAL
0.29.28
ILOGIC0:IFF4_INIT
0.28.31
ILOGIC0:IFF4_SRVAL
0.28.29
ILOGIC0:IFF_LATCH
0.31.20
ILOGIC1:IFF1_INIT
0.28.37
ILOGIC1:IFF1_SRVAL
0.28.39
ILOGIC1:IFF2_INIT
0.29.43
ILOGIC1:IFF2_SRVAL
0.29.41
ILOGIC1:IFF3_INIT
0.28.36
ILOGIC1:IFF3_SRVAL
0.29.35
ILOGIC1:IFF4_INIT
0.28.32
ILOGIC1:IFF4_SRVAL
0.28.34
ILOGIC1:IFF_LATCH
0.31.43
IOB0:DCIUPDATEMODE_ASREQUIRED
0.37.5
IOB0:INV.I
0.31.23
IOB1:DCIUPDATEMODE_ASREQUIRED
0.37.58
IOB1:INV.I
0.31.40
IODELAY0:INV.DATAIN
0.30.8
IODELAY0:LEGIDELAY
0.33.9
IODELAY1:INV.DATAIN
0.30.55
IODELAY1:LEGIDELAY
0.33.54
OLOGIC0:INV.CLK1
0.33.31
OLOGIC0:INV.CLK2
0.33.30
OLOGIC0:INV.T1
0.32.2
OLOGIC0:INV.T2
0.33.3
OLOGIC0:INV.T3
0.34.0
OLOGIC0:INV.T4
0.35.0
OLOGIC0:TFF1_SRVAL
0.35.12
OLOGIC1:INV.CLK1
0.33.32
OLOGIC1:INV.CLK2
0.33.33
OLOGIC1:INV.T1
0.32.61
OLOGIC1:INV.T2
0.33.60
OLOGIC1:INV.T3
0.34.63
OLOGIC1:INV.T4
0.35.63
OLOGIC1:TFF1_SRVAL
0.35.51
inverted
~[0]
ILOGIC0:INIT_BITSLIPCNT
0.29.29
0.28.2
0.28.4
0.29.8
ILOGIC1:INIT_BITSLIPCNT
0.29.34
0.28.61
0.28.59
0.29.55
IODELAY0:ENABLE
0.33.16
0.32.20
0.32.18
0.32.8
IODELAY1:ENABLE
0.33.47
0.32.55
0.32.45
0.32.43
OLOGIC0:INIT_LOADCNT
0.33.29
0.33.23
0.35.27
0.35.24
OLOGIC0:OFF_INIT
0.35.22
0.33.20
0.33.18
0.32.15
OLOGIC1:INIT_LOADCNT
0.33.34
0.33.40
0.35.36
0.35.39
OLOGIC1:OFF_INIT
0.35.41
0.33.45
0.33.43
0.32.48
inverted
~[3]
~[2]
~[1]
~[0]
ILOGIC0:INIT_CE
0.28.12
0.28.13
ILOGIC1:INIT_CE
0.28.51
0.28.50
OLOGIC0:TFF23_SRVAL
0.35.10
0.34.10
OLOGIC1:TFF23_SRVAL
0.35.53
0.34.53
inverted
~[1]
~[0]
ILOGIC0:INIT_RANK1_PARTIAL
0.29.14
0.29.11
0.28.8
0.29.5
0.28.1
ILOGIC1:INIT_RANK1_PARTIAL
0.29.49
0.29.52
0.28.55
0.29.58
0.28.62
OLOGIC0:TFF_INIT
0.35.16
0.35.4
0.35.1
0.34.8
0.34.7
OLOGIC1:TFF_INIT
0.35.62
0.35.59
0.35.47
0.34.56
0.34.55
inverted
~[4]
~[3]
~[2]
~[1]
~[0]
ILOGIC0:INIT_RANK2
0.28.19
0.29.17
0.28.10
0.28.11
0.28.5
0.29.3
ILOGIC0:INIT_RANK3
0.28.28
0.29.21
0.28.14
0.29.7
0.29.1
0.28.0
ILOGIC1:INIT_RANK2
0.28.44
0.29.46
0.28.53
0.28.52
0.28.58
0.29.60
ILOGIC1:INIT_RANK3
0.28.35
0.29.42
0.28.49
0.29.56
0.29.62
0.28.63
IODELAY0:IDELAY_VALUE_CUR
0.32.12
0.32.16
0.32.19
0.32.22
0.32.31
0.33.28
IODELAY1:IDELAY_VALUE_CUR
0.32.51
0.32.47
0.32.44
0.32.41
0.32.32
0.33.35
inverted
~[5]
~[4]
~[3]
~[2]
~[1]
~[0]
ILOGIC0:INTERFACE_TYPE
0.31.25
ILOGIC1:INTERFACE_TYPE
0.31.38
MEMORY
0
NETWORKING
1
ILOGIC0:MUX.CLK
0.28.21
ILOGIC0:MUX.CLKB
0.28.20
ICLK0
0
ICLK1
1
ILOGIC0:NUM_CE
0.30.22
ILOGIC1:NUM_CE
0.30.41
1
0
2
1
ILOGIC0:SERDES_MODE
0.31.15
ILOGIC1:SERDES_MODE
0.31.48
OLOGIC0:SERDES_MODE
0.34.5
OLOGIC1:SERDES_MODE
0.34.58
MASTER
0
SLAVE
1
ILOGIC0:TSBYPASS_MUX
0.30.16
ILOGIC1:TSBYPASS_MUX
0.30.47
T
0
GND
1
ILOGIC1:MUX.CLK
0.28.42
ILOGIC1:MUX.CLKB
0.28.43
ICLK1
0
ICLK0
1
IOB0:DCI_MISC
0.37.26
0.37.16
IOB0:OUTPUT_ENABLE
0.36.22
0.36.19
IOB1:DCI_MISC
0.37.37
0.37.47
IOB1:OUTPUT_ENABLE
0.36.44
0.36.41
OLOGIC0:TFF_SR_SYNC
0.34.19
0.32.1
OLOGIC1:TFF_SR_SYNC
0.34.44
0.32.62
non-inverted
[1]
[0]
IOB0:DCI_MODE
0.37.8
0.36.8
0.37.7
IOB1:DCI_MODE
0.37.55
0.36.55
0.37.56
NONE
0
0
0
OUTPUT
0
0
1
OUTPUT_HALF
0
1
0
TERM_VCC
0
1
1
TERM_SPLIT
1
0
0
IOB0:IBUF_MODE
0.36.29
0.36.25
0.37.18
IOB1:IBUF_MODE
0.36.34
0.36.38
0.37.45
OFF
0
0
0
VREF
0
0
1
DIFF
0
1
0
CMOS
1
1
1
IOB0:LVDS
0.36.5
0.37.22
0.37.21
0.36.21
0.36.18
0.36.17
0.37.15
0.36.13
0.37.11
IOB1:LVDS
0.36.58
0.37.41
0.37.42
0.36.42
0.36.45
0.36.46
0.37.48
0.36.50
0.37.52
non-inverted
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
IOB0:NDRIVE
0.36.11
0.36.6
0.37.14
0.37.2
0.36.10
IOB1:NDRIVE
0.36.52
0.36.57
0.37.49
0.37.61
0.36.53
mixed inversion
[4]
[3]
~[2]
~[1]
~[0]
IOB0:NSLEW
0.37.20
0.36.26
0.37.28
0.37.31
0.36.27
0.36.31
IOB0:OUTPUT_MISC
0.37.3
0.36.4
0.36.20
0.37.25
0.37.24
0.36.24
IOB0:PSLEW
0.37.27
0.37.29
0.37.30
0.37.23
0.36.23
0.37.17
IOB1:NSLEW
0.37.43
0.36.37
0.37.35
0.37.32
0.36.36
0.36.32
IOB1:OUTPUT_MISC
0.37.60
0.36.59
0.36.43
0.37.38
0.37.39
0.36.39
IOB1:PSLEW
0.37.36
0.37.34
0.37.33
0.37.40
0.36.40
0.37.46
IODELAY0:IDELAY_VALUE_INIT
0.32.3
0.32.17
0.33.6
0.32.10
0.32.5
0.32.21
IODELAY0:ODELAY_VALUE
0.33.13
0.33.17
0.33.21
0.33.22
0.33.15
0.32.7
IODELAY1:IDELAY_VALUE_INIT
0.32.60
0.32.46
0.33.57
0.32.53
0.32.58
0.32.42
IODELAY1:ODELAY_VALUE
0.33.50
0.33.46
0.33.42
0.33.41
0.33.48
0.32.56
non-inverted
[5]
[4]
[3]
[2]
[1]
[0]
IOB0:PDRIVE
0.37.10
0.37.9
0.37.13
0.37.0
0.36.14
IOB1:PDRIVE
0.37.53
0.37.54
0.37.50
0.37.63
0.36.49
mixed inversion
[4]
~[3]
[2]
[1]
~[0]
IOB0:PULL
0.37.19
0.36.15
0.36.16
IOB1:PULL
0.37.44
0.36.48
0.36.47
PULLDOWN
0
0
0
NONE
0
0
1
PULLUP
0
1
1
KEEPER
1
0
1
IODELAY0:DELAY_SRC
0.31.0
0.31.3
0.30.1
0.30.0
IODELAY1:DELAY_SRC
0.31.63
0.31.60
0.30.62
0.30.63
NONE
0
0
0
0
I
0
0
0
1
IO
0
0
1
1
O
0
1
1
0
DATAIN
1
0
0
0
IODELAY0:IDELAY_TYPE
0.33.5
0.33.7
IODELAY1:IDELAY_TYPE
0.33.58
0.33.56
FIXED
0
0
VARIABLE
0
1
DEFAULT
1
0
IOI:INV.ICLK0
0.31.28
0.30.30
0.30.29
IOI:INV.ICLK1
0.31.35
0.30.34
0.30.33
OLOGIC0:OFF_INIT_SERDES
0.33.11
0.33.8
0.32.13
OLOGIC0:OFF_SRVAL
0.35.31
0.34.31
0.34.30
OLOGIC1:OFF_INIT_SERDES
0.33.55
0.33.52
0.32.50
OLOGIC1:OFF_SRVAL
0.35.32
0.34.33
0.34.32
inverted
~[2]
~[1]
~[0]
IOI:MUX.ICLK0
0.31.14
0.31.11
0.31.18
0.30.6
0.31.1
0.30.2
0.30.3
0.31.4
0.30.4
NONE
0
0
0
0
0
0
0
0
0
HCLK0
0
0
0
1
0
0
0
0
1
HCLK4
0
0
0
1
0
0
0
1
0
HCLK8
0
0
0
1
0
0
1
0
0
RCLK2
0
0
0
1
0
1
0
0
0
IOCLK2
0
0
0
1
1
0
0
0
0
HCLK1
0
0
1
0
0
0
0
0
1
HCLK5
0
0
1
0
0
0
0
1
0
HCLK9
0
0
1
0
0
0
1
0
0
RCLK3
0
0
1
0
0
1
0
0
0
IOCLK3
0
0
1
0
1
0
0
0
0
HCLK2
0
1
0
0
0
0
0
0
1
HCLK6
0
1
0
0
0
0
0
1
0
RCLK0
0
1
0
0
0
0
1
0
0
IOCLK0
0
1
0
0
0
1
0
0
0
CKINT0
0
1
0
0
1
0
0
0
0
HCLK3
1
0
0
0
0
0
0
0
1
HCLK7
1
0
0
0
0
0
0
1
0
RCLK1
1
0
0
0
0
0
1
0
0
IOCLK1
1
0
0
0
0
1
0
0
0
CKINT1
1
0
0
0
1
0
0
0
0
IOI:MUX.ICLK1
0.31.49
0.31.52
0.31.45
0.30.57
0.31.62
0.30.61
0.30.60
0.31.59
0.30.59
NONE
0
0
0
0
0
0
0
0
0
HCLK0
0
0
0
1
0
0
0
0
1
HCLK4
0
0
0
1
0
0
0
1
0
HCLK8
0
0
0
1
0
0
1
0
0
RCLK2
0
0
0
1
0
1
0
0
0
IOCLK2
0
0
0
1
1
0
0
0
0
HCLK1
0
0
1
0
0
0
0
0
1
HCLK5
0
0
1
0
0
0
0
1
0
HCLK9
0
0
1
0
0
0
1
0
0
RCLK3
0
0
1
0
0
1
0
0
0
IOCLK3
0
0
1
0
1
0
0
0
0
HCLK2
0
1
0
0
0
0
0
0
1
HCLK6
0
1
0
0
0
0
0
1
0
RCLK0
0
1
0
0
0
0
1
0
0
IOCLK0
0
1
0
0
0
1
0
0
0
CKINT1
0
1
0
0
1
0
0
0
0
HCLK3
1
0
0
0
0
0
0
0
1
HCLK7
1
0
0
0
0
0
0
1
0
RCLK1
1
0
0
0
0
0
1
0
0
IOCLK1
1
0
0
0
0
1
0
0
0
CKINT0
1
0
0
0
1
0
0
0
0
OLOGIC0:DATA_WIDTH
0.32.30
0.32.29
0.34.28
0.35.28
0.32.28
0.32.27
0.33.27
0.33.26
OLOGIC1:DATA_WIDTH
0.32.33
0.32.34
0.34.35
0.35.35
0.32.35
0.32.36
0.33.36
0.33.37
2
0
0
0
0
0
0
0
1
3
0
0
0
0
0
0
1
0
4
0
0
0
0
0
1
0
0
5
0
0
0
0
1
0
0
0
6
0
0
0
1
0
0
0
0
7
0
0
1
0
0
0
0
0
8
0
1
0
0
0
0
0
0
10
1
0
0
0
0
0
0
0
OLOGIC0:MISR_CLK_SELECT
0.29.16
0.28.17
OLOGIC1:MISR_CLK_SELECT
0.29.47
0.28.46
NONE
0
0
CLK1
0
1
CLK2
1
0
OLOGIC0:MUX.CLK
0.30.15
0.31.9
0.30.9
0.30.10
0.30.11
0.31.12
0.30.13
0.31.10
0.30.7
OLOGIC1:MUX.CLK
0.30.48
0.31.54
0.30.54
0.30.53
0.30.52
0.31.51
0.30.50
0.31.53
0.30.56
NONE
0
0
0
0
0
0
0
0
0
HCLK0
0
0
0
1
0
0
0
0
1
HCLK4
0
0
0
1
0
0
0
1
0
HCLK8
0
0
0
1
0
0
1
0
0
RCLK2
0
0
0
1
0
1
0
0
0
IOCLK2
0
0
0
1
1
0
0
0
0
HCLK1
0
0
1
0
0
0
0
0
1
HCLK5
0
0
1
0
0
0
0
1
0
HCLK9
0
0
1
0
0
0
1
0
0
RCLK3
0
0
1
0
0
1
0
0
0
IOCLK3
0
0
1
0
1
0
0
0
0
HCLK2
0
1
0
0
0
0
0
0
1
HCLK6
0
1
0
0
0
0
0
1
0
RCLK0
0
1
0
0
0
0
1
0
0
IOCLK0
0
1
0
0
0
1
0
0
0
CKINT
0
1
0
0
1
0
0
0
0
HCLK3
1
0
0
0
0
0
0
0
1
HCLK7
1
0
0
0
0
0
0
1
0
RCLK1
1
0
0
0
0
0
1
0
0
IOCLK1
1
0
0
0
0
1
0
0
0
OLOGIC0:MUX.CLKDIV
0.30.18
0.31.13
0.30.23
0.31.21
0.30.21
0.30.20
0.31.19
0.30.19
OLOGIC1:MUX.CLKDIV
0.30.45
0.31.50
0.30.40
0.31.42
0.30.42
0.30.43
0.31.44
0.30.44
NONE
0
0
0
0
0
0
0
0
HCLK0
0
0
0
1
0
0
0
1
HCLK4
0
0
0
1
0
0
1
0
HCLK8
0
0
0
1
0
1
0
0
RCLK2
0
0
0
1
1
0
0
0
HCLK1
0
0
1
0
0
0
0
1
HCLK5
0
0
1
0
0
0
1
0
HCLK9
0
0
1
0
0
1
0
0
RCLK3
0
0
1
0
1
0
0
0
HCLK2
0
1
0
0
0
0
0
1
HCLK6
0
1
0
0
0
0
1
0
RCLK0
0
1
0
0
0
1
0
0
CKINT
0
1
0
0
1
0
0
0
HCLK3
1
0
0
0
0
0
0
1
HCLK7
1
0
0
0
0
0
1
0
RCLK1
1
0
0
0
0
1
0
0
OLOGIC0:OFF_SERDES
0.35.13
0.35.6
0.34.11
0.34.2
OLOGIC0:OFF_SR_SYNC
0.35.26
0.34.12
0.33.0
0.32.26
OLOGIC1:OFF_SERDES
0.35.57
0.35.50
0.34.61
0.34.52
OLOGIC1:OFF_SR_SYNC
0.35.37
0.34.51
0.33.63
0.32.37
non-inverted
[3]
[2]
[1]
[0]
OLOGIC0:OMUX
0.35.29
0.34.29
0.34.6
0.35.5
0.35.30
OLOGIC1:OMUX
0.35.34
0.34.34
0.34.57
0.35.58
0.35.33
NONE
0
0
0
0
0
D1
0
0
0
0
1
SERDES_SDR
0
0
0
1
0
SERDES_DDR
0
0
1
0
0
FF
0
1
0
1
0
DDR
0
1
1
0
0
LATCH
1
0
0
1
0
OLOGIC0:TMUX
0.35.18
0.34.16
0.34.17
0.35.17
0.35.11
OLOGIC1:TMUX
0.35.45
0.34.47
0.34.46
0.35.46
0.35.52
NONE
0
0
0
0
0
T1
0
0
0
0
1
DDR
0
0
1
0
0
SERDES_DDR
0
0
1
1
0
FF
0
1
0
1
0
LATCH
1
1
0
0
0
OLOGIC0:TRISTATE_WIDTH
0.35.19
OLOGIC1:TRISTATE_WIDTH
0.35.44
1
0
4
1
Device
IODELAY:DEFAULT_IDELAY_VALUE
[5]
[4]
[3]
[2]
[1]
[0]
xc5vlx30
1
0
0
1
1
1
xc5vlx50
1
0
0
1
1
1
xc5vlx85
1
0
1
1
0
0
xq5vlx85
1
0
1
1
0
0
xc5vlx110
1
0
1
1
0
0
xq5vlx110
1
0
1
1
0
0
xc5vlx155
1
1
0
0
1
0
xc5vlx220
1
1
1
0
0
0
xc5vlx330
1
1
1
0
0
0
xc5vlx20t
1
0
0
1
1
1
xc5vlx30t
1
0
0
1
1
1
xq5vlx30t
1
0
0
1
1
1
xc5vlx50t
1
0
0
1
1
1
xc5vlx85t
1
0
1
1
0
0
xc5vlx110t
1
0
1
1
0
0
xq5vlx110t
1
0
1
1
0
0
xc5vlx155t
1
1
0
0
1
0
xq5vlx155t
1
1
0
0
1
0
xc5vlx220t
1
1
1
0
0
0
xq5vlx220t
1
1
1
0
0
0
xc5vlx330t
1
1
1
0
0
0
xq5vlx330t
1
1
1
0
0
0
xc5vsx35t
1
0
0
1
1
1
xc5vsx50t
1
0
1
0
1
1
xq5vsx50t
1
0
1
0
1
1
xc5vsx95t
1
1
0
0
1
0
xq5vsx95t
1
1
0
0
1
0
xc5vsx240t
1
1
1
0
0
0
xq5vsx240t
1
1
1
0
0
0
xc5vfx30t
1
0
0
1
1
1
xc5vfx70t
1
0
1
1
0
0
xq5vfx70t
1
0
1
1
0
0
xc5vfx100t
1
1
0
0
1
0
xq5vfx100t
1
1
0
0
1
0
xc5vfx130t
1
1
0
1
1
1
xq5vfx130t
1
1
0
1
1
1
xc5vfx200t
1
1
1
0
0
0
xq5vfx200t
1
1
1
0
0
0
xc5vtx150t
1
1
0
1
1
1
xc5vtx240t
1
1
1
0
0
0
Name
IOSTD:PDRIVE
IOSTD:NDRIVE
[4]
[3]
[2]
[1]
[0]
[4]
[3]
[2]
[1]
[0]
BLVDS_25
1
1
1
1
1
1
0
1
1
1
GTL
0
0
0
0
0
1
0
0
1
1
GTLP
0
0
0
0
0
1
0
0
0
0
GTLP_DCI
0
0
0
0
0
1
0
0
0
0
GTL_DCI
0
0
0
0
0
1
0
0
1
1
HSTL_I
0
1
1
0
1
0
0
1
0
1
HSTL_II
1
1
0
1
0
0
1
0
1
0
HSTL_III
0
1
1
0
1
0
1
1
1
1
HSTL_III_18
0
1
1
1
0
1
0
0
1
0
HSTL_III_DCI
0
1
1
0
1
0
1
1
1
1
HSTL_III_DCI_18
0
1
1
1
0
1
0
0
1
0
HSTL_II_18
1
1
0
1
1
0
1
1
0
1
HSTL_II_DCI
1
1
0
1
0
0
1
0
1
0
HSTL_II_DCI_18
1
1
0
1
1
0
1
1
0
1
HSTL_II_T_DCI
0
1
1
0
1
0
0
1
0
1
HSTL_II_T_DCI_18
0
1
1
1
0
0
0
1
1
1
HSTL_IV
0
1
1
0
1
1
1
1
1
0
HSTL_IV_18
0
1
1
1
0
1
1
1
1
1
HSTL_IV_DCI
0
1
1
0
1
1
1
1
1
0
HSTL_IV_DCI_18
0
1
1
1
0
1
1
1
1
1
HSTL_I_12
1
1
0
1
0
0
0
1
1
0
HSTL_I_18
0
1
1
1
0
0
0
1
1
1
HSTL_I_DCI
0
1
1
0
1
0
0
1
0
1
HSTL_I_DCI_18
0
1
1
1
0
0
0
1
1
1
LVCMOS12.2
0
0
1
1
1
0
0
0
1
0
LVCMOS12.4
0
1
1
1
0
0
0
1
0
0
LVCMOS12.6
1
0
0
1
1
0
0
1
0
1
LVCMOS12.8
1
1
0
1
0
0
1
0
0
1
LVCMOS15.12
1
0
1
1
0
0
1
0
0
0
LVCMOS15.16
1
1
1
0
0
0
1
0
1
0
LVCMOS15.2
0
0
1
1
0
0
0
0
1
0
LVCMOS15.4
0
1
0
0
0
0
0
0
1
1
LVCMOS15.6
0
1
0
0
1
0
0
1
0
0
LVCMOS15.8
0
1
1
0
1
0
0
1
0
1
LVCMOS18.12
0
1
1
0
1
0
0
1
1
0
LVCMOS18.16
1
0
0
1
1
0
1
0
0
1
LVCMOS18.2
0
0
0
1
1
0
0
0
0
1
LVCMOS18.4
0
0
1
0
1
0
0
0
1
0
LVCMOS18.6
0
0
1
1
1
0
0
0
1
1
LVCMOS18.8
0
1
0
0
0
0
0
1
0
0
LVCMOS25.12
0
1
0
0
1
0
0
1
1
1
LVCMOS25.16
0
1
1
1
0
0
1
0
1
0
LVCMOS25.2
0
0
0
1
1
0
0
0
1
0
LVCMOS25.24
1
0
1
0
1
0
1
1
1
1
LVCMOS25.4
0
0
1
0
1
0
0
0
1
1
LVCMOS25.6
0
0
1
1
0
0
0
1
0
0
LVCMOS25.8
0
0
1
1
1
0
0
1
0
1
LVCMOS33.12
0
1
0
0
0
0
1
0
0
0
LVCMOS33.16
0
1
0
1
0
0
1
0
1
0
LVCMOS33.2
0
0
0
1
0
0
0
0
1
0
LVCMOS33.24
1
0
0
0
1
1
0
0
0
0
LVCMOS33.4
0
0
0
1
1
0
0
0
1
1
LVCMOS33.6
0
0
1
0
0
0
0
1
0
0
LVCMOS33.8
0
0
1
1
0
0
0
1
0
1
LVPECL_25
1
1
0
0
0
1
1
1
1
0
LVTTL.12
0
1
0
0
0
0
1
0
0
0
LVTTL.16
0
1
0
1
0
0
1
0
1
0
LVTTL.2
0
0
0
1
0
0
0
0
1
0
LVTTL.24
1
0
0
0
1
1
0
0
0
0
LVTTL.4
0
0
0
1
1
0
0
0
1
1
LVTTL.6
0
0
1
0
0
0
0
1
0
0
LVTTL.8
0
0
1
1
0
0
0
1
0
1
OFF
0
0
0
0
0
0
0
0
0
0
PCI33_3
0
1
0
1
0
0
1
1
0
1
PCI66_3
0
1
0
1
0
0
1
1
0
1
PCIX
0
1
1
0
0
0
1
1
0
0
SSTL18_I
0
1
0
0
0
0
0
1
0
0
SSTL18_II
1
1
0
0
0
0
1
1
0
0
SSTL18_II_DCI
0
1
1
1
0
0
0
1
1
0
SSTL18_II_T_DCI
0
0
1
1
1
0
0
0
1
1
SSTL18_I_DCI
0
0
1
1
1
0
0
0
1
1
SSTL2_I
0
0
1
1
0
0
0
1
0
0
SSTL2_II
1
0
0
1
1
0
1
1
0
1
SSTL2_II_DCI
0
1
0
0
0
0
0
1
1
0
SSTL2_II_T_DCI
0
0
1
0
1
0
0
0
1
1
SSTL2_I_DCI
0
0
1
0
1
0
0
0
1
1
VR
0
0
0
0
0
0
0
0
0
0
Name
IOSTD:PSLEW
IOSTD:NSLEW
[5]
[4]
[3]
[2]
[1]
[0]
[5]
[4]
[3]
[2]
[1]
[0]
BLVDS_25
1
1
1
1
1
1
1
0
1
1
1
1
GTL
0
0
0
0
0
0
0
1
0
1
0
1
GTLP
0
0
0
0
0
0
0
1
0
1
0
1
GTLP_DCI
0
0
0
0
0
0
1
1
1
1
1
1
GTL_DCI
0
0
0
0
0
0
1
1
1
1
1
1
HSLVDCI_15
1
1
1
1
1
1
0
0
0
0
1
0
HSLVDCI_18
1
1
1
1
1
1
0
0
0
0
0
0
HSLVDCI_25
1
1
1
1
1
1
0
0
1
1
1
1
HSLVDCI_33
1
1
1
1
1
1
1
1
1
1
1
1
HSTL_I
1
1
1
1
1
1
0
0
1
1
0
1
HSTL_II
1
1
1
1
1
1
0
0
1
0
1
0
HSTL_III
1
1
1
1
1
1
0
1
0
0
0
0
HSTL_III_18
1
1
1
1
1
1
0
1
0
0
0
0
HSTL_III_DCI
0
0
0
1
1
0
1
1
0
0
0
1
HSTL_III_DCI_18
0
0
0
1
0
0
0
1
1
0
0
1
HSTL_II_18
1
1
1
1
1
1
0
1
0
0
1
0
HSTL_II_DCI
1
0
1
1
1
0
0
0
1
0
0
1
HSTL_II_DCI_18
1
0
1
1
1
0
1
0
1
1
0
1
HSTL_II_T_DCI
0
1
1
1
1
1
0
0
1
0
1
0
HSTL_II_T_DCI_18
0
1
1
1
1
1
1
0
1
1
1
0
HSTL_IV
1
1
1
1
1
1
0
1
0
0
1
0
HSTL_IV_18
1
1
1
1
1
1
0
1
1
0
0
0
HSTL_IV_DCI
0
0
0
0
0
0
1
1
1
1
0
1
HSTL_IV_DCI_18
0
0
1
1
1
1
1
1
1
1
1
1
HSTL_I_12
1
1
1
1
1
1
0
0
1
0
1
0
HSTL_I_18
1
1
1
1
1
1
0
0
1
1
1
1
HSTL_I_DCI
0
1
1
1
1
1
0
0
1
0
1
0
HSTL_I_DCI_18
0
1
1
1
1
1
1
0
1
1
1
0
LVCMOS12.2.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS12.2.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS12.4.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS12.4.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS12.6.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS12.6.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS12.8.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS12.8.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.12.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS15.12.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.16.FAST
1
1
1
1
1
1
0
0
1
0
1
0
LVCMOS15.16.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.2.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS15.2.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.4.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS15.4.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.6.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS15.6.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS15.8.FAST
1
1
1
1
1
1
0
0
0
1
1
1
LVCMOS15.8.SLOW
0
0
0
1
0
1
0
0
0
0
0
0
LVCMOS18.12.FAST
1
1
1
1
1
1
0
1
0
0
1
1
LVCMOS18.12.SLOW
0
0
0
0
0
1
0
0
0
0
0
1
LVCMOS18.16.FAST
1
1
1
1
1
1
0
0
1
1
1
1
LVCMOS18.16.SLOW
0
0
0
0
0
1
0
0
0
0
0
0
LVCMOS18.2.FAST
0
1
1
1
1
1
1
1
1
1
1
1
LVCMOS18.2.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVCMOS18.4.FAST
1
1
1
1
1
1
1
1
1
0
0
0
LVCMOS18.4.SLOW
0
0
0
0
0
1
0
0
0
1
0
1
LVCMOS18.6.FAST
1
1
1
1
1
1
0
0
1
1
1
1
LVCMOS18.6.SLOW
0
0
0
0
0
1
0
0
0
0
0
1
LVCMOS18.8.FAST
1
1
1
1
1
1
0
0
1
1
1
1
LVCMOS18.8.SLOW
0
0
0
0
0
1
0
0
0
0
0
1
LVCMOS25.12.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVCMOS25.12.SLOW
0
0
0
0
0
0
0
0
0
0
0
0
LVCMOS25.16.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVCMOS25.16.SLOW
0
0
0
0
0
1
0
0
0
0
1
0
LVCMOS25.2.FAST
0
1
1
1
1
1
0
0
1
1
1
1
LVCMOS25.2.SLOW
0
0
0
0
0
0
0
0
1
0
1
0
LVCMOS25.24.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVCMOS25.24.SLOW
0
0
0
0
0
1
0
0
0
0
0
0
LVCMOS25.4.FAST
1
1
1
1
1
1
1
0
1
0
0
0
LVCMOS25.4.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVCMOS25.6.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVCMOS25.6.SLOW
0
0
0
0
0
1
0
0
0
0
1
0
LVCMOS25.8.FAST
1
1
1
1
1
1
0
1
0
0
0
1
LVCMOS25.8.SLOW
0
0
0
0
0
1
0
0
0
0
1
0
LVCMOS33.12.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.12.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVCMOS33.16.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.16.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVCMOS33.2.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.2.SLOW
0
0
0
0
0
1
0
0
0
1
0
0
LVCMOS33.24.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.24.SLOW
0
0
0
0
0
1
0
0
0
0
0
1
LVCMOS33.4.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.4.SLOW
0
0
0
0
0
1
0
0
0
1
0
1
LVCMOS33.6.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVCMOS33.6.SLOW
0
0
0
0
0
1
0
0
0
0
1
0
LVCMOS33.8.FAST
0
1
1
1
1
1
1
1
1
1
1
1
LVCMOS33.8.SLOW
0
0
0
0
0
1
0
0
0
1
0
0
LVDCI_15
1
1
1
1
1
1
0
0
0
0
1
0
LVDCI_18
1
1
1
1
1
1
0
0
0
0
0
0
LVDCI_25
1
1
1
1
1
1
0
0
1
1
1
1
LVDCI_33
1
1
1
1
1
1
1
1
1
1
1
1
LVDCI_DV2_15
1
1
1
1
1
1
0
0
0
0
1
1
LVDCI_DV2_18
1
1
1
1
1
1
0
0
0
1
1
1
LVDCI_DV2_25
1
1
1
1
1
1
0
1
1
1
0
1
LVPECL_25
1
1
1
1
1
1
0
0
1
1
1
1
LVTTL.12.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL.12.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVTTL.16.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL.16.SLOW
0
0
0
0
0
1
0
0
0
0
1
1
LVTTL.2.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL.2.SLOW
0
0
0
0
0
1
0
0
0
1
0
0
LVTTL.24.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL.24.SLOW
0
0
0
0
0
1
0
0
0
0
0
1
LVTTL.4.FAST
1
1
1
1
1
1
1
1
1
1
1
1
LVTTL.4.SLOW
0
0
0
0
0
1
0
0
0
1
0
1
LVTTL.6.FAST
1
1
1
1
1
1
1
0
0
0
0
0
LVTTL.6.SLOW
0
0
0
0
0
1
0
0
0
0
1
0
LVTTL.8.FAST
0
1
1
1
1
1
1
1
1
1
1
1
LVTTL.8.SLOW
0
0
0
0
0
1
0
0
0
1
0
0
OFF
0
0
0
0
0
0
0
0
0
0
0
0
PCI33_3
0
0
0
0
0
0
0
0
0
0
0
0
PCI66_3
0
0
0
0
0
0
0
0
0
0
0
0
PCIX
0
0
1
1
1
1
1
0
0
0
0
0
SSTL18_I
1
1
1
1
1
1
0
1
0
0
1
1
SSTL18_II
1
1
1
1
1
1
0
0
1
1
1
1
SSTL18_II_DCI
1
1
1
1
1
1
1
1
1
1
1
1
SSTL18_II_T_DCI
0
0
1
1
1
1
1
1
0
0
0
0
SSTL18_I_DCI
0
0
1
1
1
1
1
1
0
0
0
0
SSTL2_I
1
1
1
1
1
1
0
1
0
0
1
1
SSTL2_II
1
1
1
1
1
1
0
0
1
1
1
1
SSTL2_II_DCI
1
1
1
0
1
1
0
0
1
1
0
1
SSTL2_II_T_DCI
1
1
1
1
1
1
0
1
0
1
0
1
SSTL2_I_DCI
1
1
1
1
1
1
0
1
0
1
0
1
VR
1
1
1
1
1
1
1
1
1
1
1
1
Name
IOSTD:OUTPUT_MISC
[5]
[4]
[3]
[2]
[1]
[0]
BLVDS_25
0
1
1
0
0
0
GTL
0
0
0
0
0
0
GTLP
0
0
0
0
0
0
GTLP_DCI
1
0
0
0
0
0
GTL_DCI
1
0
0
0
0
1
HSLVDCI_15
1
0
0
0
0
0
HSLVDCI_18
1
0
0
0
0
0
HSLVDCI_25
0
0
0
0
0
0
HSLVDCI_33
0
0
0
0
0
0
HSTL_I
1
1
0
0
0
0
HSTL_II
1
1
0
0
0
0
HSTL_III
1
1
0
0
0
0
HSTL_III_18
1
0
0
0
0
0
HSTL_III_DCI
1
0
0
0
0
0
HSTL_III_DCI_18
1
0
0
0
0
0
HSTL_II_18
1
0
0
0
0
0
HSTL_II_DCI
1
0
0
0
0
0
HSTL_II_DCI_18
1
0
0
0
0
0
HSTL_II_T_DCI
1
0
0
0
0
0
HSTL_II_T_DCI_18
1
0
0
0
0
0
HSTL_IV
1
0
0
0
0
0
HSTL_IV_18
1
0
0
0
0
0
HSTL_IV_DCI
1
0
0
0
0
0
HSTL_IV_DCI_18
1
0
0
0
1
0
HSTL_I_12
1
1
1
0
0
0
HSTL_I_18
1
0
0
0
0
0
HSTL_I_DCI
1
0
0
0
0
0
HSTL_I_DCI_18
1
0
0
0
0
0
LVCMOS12
1
1
1
0
0
0
LVCMOS15
1
1
1
0
0
0
LVCMOS18
1
0
0
0
0
0
LVCMOS25
0
0
0
0
0
0
LVCMOS33
0
0
0
0
0
0
LVDCI_15
1
0
0
0
0
0
LVDCI_18
1
0
0
0
0
0
LVDCI_25
0
0
0
0
0
0
LVDCI_33
0
0
0
0
0
0
LVDCI_DV2_15
1
0
0
0
0
0
LVDCI_DV2_18
1
0
0
0
0
0
LVDCI_DV2_25
0
0
0
0
0
0
LVPECL_25
0
1
1
0
0
0
LVTTL
0
0
0
0
0
0
OFF
0
0
0
0
0
0
PCI33_3
0
0
0
0
0
0
PCI66_3
0
0
0
0
0
0
PCIX
0
0
0
0
0
0
SSTL18_I
1
0
0
0
0
0
SSTL18_II
1
0
0
0
0
0
SSTL18_II_DCI
1
0
0
0
0
0
SSTL18_II_T_DCI
1
0
0
0
0
0
SSTL18_I_DCI
1
0
0
0
0
0
SSTL2_I
0
0
0
0
0
0
SSTL2_II
0
0
0
0
0
0
SSTL2_II_DCI
0
0
0
0
0
0
SSTL2_II_T_DCI
0
0
0
0
0
0
SSTL2_I_DCI
0
0
0
0
0
0
Name
IOSTD:LVDS_T
IOSTD:LVDS_C
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTPUT_HT_25
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
OUTPUT_LVDSEXT_25
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
OUTPUT_LVDS_25
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
OUTPUT_RSDS_25
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
TERM_HT_25
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
TERM_LVDSEXT_25
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
TERM_LVDS_25
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
TERM_RSDS_25
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
Name
IOSTD:LVDSBIAS
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HT_25
0
0
0
0
0
0
0
0
1
0
0
0
LVDSEXT_25
0
0
0
0
0
0
0
0
1
0
0
0
LVDS_25
0
0
0
0
0
0
0
0
1
0
0
0
OFF
0
0
0
0
0
0
0
0
0
0
0
0
RSDS_25
0
0
0
0
0
0
0
0
1
0
0
0
Name
IOSTD:DCI:LVDIV2
[2]
[1]
[0]
LVDCI_DV2_15
0
0
0
LVDCI_DV2_18
0
1
0
LVDCI_DV2_25
1
0
1
OFF
0
0
0
Name
IOSTD:DCI:PMASK_TERM_VCC
[4]
[3]
[2]
[1]
[0]
GTLP_DCI
0
0
0
0
0
GTL_DCI
0
0
0
0
0
HSTL_III_DCI
0
0
0
0
0
HSTL_III_DCI_18
0
0
0
0
0
HSTL_IV_DCI
0
0
1
0
0
HSTL_IV_DCI_18
0
1
1
0
0
OFF
0
0
0
0
0
Name
IOSTD:DCI:PMASK_TERM_SPLIT
IOSTD:DCI:NMASK_TERM_SPLIT
[4]
[3]
[2]
[1]
[0]
[4]
[3]
[2]
[1]
[0]
HSTL_II_DCI
0
1
0
0
1
0
1
0
1
0
HSTL_II_DCI_18
0
1
0
0
1
0
0
1
1
0
HSTL_II_T_DCI
0
0
1
0
0
0
0
1
0
0
HSTL_II_T_DCI_18
0
1
1
0
0
0
1
1
0
0
HSTL_I_DCI
0
0
0
0
0
0
0
0
0
0
HSTL_I_DCI_18
0
0
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
0
0
0
SSTL18_II_DCI
0
1
1
0
0
0
1
1
0
0
SSTL18_II_T_DCI
0
1
1
0
0
0
1
0
0
0
SSTL18_I_DCI
0
0
0
0
0
0
0
0
0
0
SSTL2_II_DCI
0
0
0
0
0
0
1
1
0
0
SSTL2_II_T_DCI
0
0
1
0
0
0
1
0
0
0
SSTL2_I_DCI
0
0
0
0
0
0
0
0
0
0