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Input/Output

I/O banks and special functions

Virtex 5 devices have up to three I/O columns:

  • the left I/O column, containing only IO tiles; if the device has no transceivers on the left side, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column; it is always present
  • the center column, part of which contains IO tiles; the IO tiles in this column come in up to four segments:
    • the lower segment (variable size, not present on all devices), between the bottom edge of the device and the lower CMTs
    • the lower middle segment (always 20 tiles high), between lower CMTs and the configuration center
    • the upper middle segment (always 20 tiles high), between the configuration center and the upper CMTs
    • the upper segment (variable size, not present on all devices), between the device and the upper CMTs and the top edge of the device
  • the right I/O column, containing only IO tiles; it is present on all devices except for xc5vlx20t; if present, it is somewhat to the left of the device’s right edge

Virtex 5 has the following banks:

  • bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:

    • CCLK
    • CS_B
    • DONE
    • D_OUT_BUSY
    • D_IN
    • HSWAPEN
    • INIT
    • M0
    • M1
    • M2
    • PROGRAM_B
    • RDWR_B
    • TCK
    • TDI
    • TDO
    • TMS

    bank 0 is not associated with any IO tiles

  • banks 1-4: middle segments of the center column; each of them consists of 10 IO tiles; they contain global clock inputs and shared configuration pins

    • bank 1: immediately above configuration center
    • bank 2: immediately below configuration center
    • bank 3: above bank 1, below upper CMTs (not present on xc5vlx20t)
    • bank 4: below bank 2, above lower CMTs

  • banks 5-10: lower and upper segments of the center column; each of them consists of 20 IO tiles

    • banks 5, 7, 9 are the upper segment, with bank 5 being immediately above upper CMTs; bank number increases upwards
    • banks 6, 8, 10 are the lower segment, with bank 6 being immediately below lower CMTs; bank number increases downwards

  • banks 11 and up: left and right column; each of them consists of 20 IO tiles

    • banks 11, 15, 19, 23, …: left column, above the configuration center; bank number increases upwards, starting from bank 11 immediately above the configuration center row
    • banks 12, 16, 20, 24, …: right column, above the configuration center; bank number increases upwards, starting from bank 12 immediately above the configuration center row
    • banks 13, 17, 21, 25, …: left column, below the configuration center; bank number increases downwards, starting from bank 13 immediately below the configuration center row
    • banks 14, 18, 22, 26, …: right column, below the configuration center; bank number increases downwards, starting from bank 14 immediately below the configuration center row

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input and true differential output is supported on all pins of the device.

IOB1 pads in the 4 rows surronding the HCLK row (that is, in rows 8-11 of every clock region) are considered “clock-capable”. They can drive BUFIO and BUFR buffers via dedicated connections. While Xilinx documentation also considers IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

The IOB1 pads in banks 3 and 4 are considered “global clock-capable”. They can drive BUFGCTRL buffers and CMT primitives via dedicated connections. Likewise, Xilinx considers IOB0 pads to be clock-capable, but they can only drive clocks as part of differential pair with IOB1.

The IOB0 in rows 5 and 15 of every region is capable of being used as a VREF pad.

Each bank except for banks 1 and 2 has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

  • bank 1 and 2: VRP/VRN are not present in this bank (DCI can still be used by cascade from banks 3 and 4)
  • bank 3: row 7 of the bank (or row 7 of the region)
  • bank 4: row 2 of the bank (or row 12 of the region)
  • banks 5 and up: row 7 of the bank (or row 7 of the region)

In parallel configuration modes, some I/O pads in banks 1-4 are borrowed for configuration use, as the parallel data pins:

  • bank 4 row 6 IOB0: D[8]
  • bank 4 row 6 IOB1: D[9]
  • bank 4 row 7 IOB0: D[10]
  • bank 4 row 7 IOB1: D[11]
  • bank 4 row 8 IOB0: D[12]
  • bank 4 row 8 IOB1: D[13]
  • bank 4 row 9 IOB0: D[14]
  • bank 4 row 9 IOB1: D[15]
  • bank 2 row 0 IOB0: D[0]/FS[0]
  • bank 2 row 0 IOB1: D[1]/FS[1]
  • bank 2 row 1 IOB0: D[2]/FS[2]
  • bank 2 row 1 IOB1: D[3]
  • bank 2 row 2 IOB0: D[4]
  • bank 2 row 2 IOB1: D[5]
  • bank 2 row 3 IOB0: D[6]
  • bank 2 row 3 IOB1: D[7]
  • bank 2 row 4 IOB0: CSO_B
  • bank 2 row 4 IOB1: FWE_B
  • bank 2 row 5 IOB0: FOE_B/MOSI
  • bank 2 row 5 IOB1: FCS_B
  • bank 2 row 6 IOB0: A[20]
  • bank 2 row 6 IOB1: A[21]
  • bank 2 row 7 IOB0: A[22]
  • bank 2 row 7 IOB1: A[23]
  • bank 2 row 8 IOB0: A[24]
  • bank 2 row 8 IOB1: A[25]
  • bank 2 row 9 IOB0: RS[0]
  • bank 2 row 9 IOB1: RS[1]
  • bank 1 row 0 IOB0: D[16]/A[0]
  • bank 1 row 0 IOB1: D[17]/A[1]
  • bank 1 row 1 IOB0: D[18]/A[2]
  • bank 1 row 1 IOB1: D[19]/A[3]
  • bank 1 row 2 IOB0: D[20]/A[4]
  • bank 1 row 2 IOB1: D[21]/A[5]
  • bank 1 row 3 IOB0: D[22]/A[6]
  • bank 1 row 3 IOB1: D[23]/A[7]
  • bank 1 row 4 IOB0: D[24]/A[8]
  • bank 1 row 4 IOB1: D[25]/A[9]
  • bank 1 row 5 IOB0: D[26]/A[10]
  • bank 1 row 5 IOB1: D[27]/A[11]
  • bank 1 row 6 IOB0: D[28]/A[12]
  • bank 1 row 6 IOB1: D[29]/A[13]
  • bank 1 row 7 IOB0: D[30]/A[14]
  • bank 1 row 7 IOB1: D[31]/A[15]
  • bank 1 row 8 IOB0: A[16]
  • bank 1 row 8 IOB1: A[17]
  • bank 1 row 9 IOB0: A[18]
  • bank 1 row 9 IOB1: A[19]

The SYSMON present on the device can use up to 16 IOB pairs from the left I/O column as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. The IOBs are in the following tiles, where r is the configuration center row:

  • VP0/VN0: left I/O column, row r - 10
  • VP1/VN1: left I/O column, row r - 9
  • VP2/VN2: left I/O column, row r - 8
  • VP3/VN3: left I/O column, row r - 7
  • VP4/VN4: left I/O column, row r - 6
  • VP5/VN5: left I/O column, row r - 4
  • VP6/VN6: left I/O column, row r - 3
  • VP7/VN7: left I/O column, row r - 2
  • VP8/VN8: left I/O column, row r - 1
  • VP9/VN9: left I/O column, row r
  • VP10/VN10: left I/O column, row r + 1
  • VP11/VN11: left I/O column, row r + 2
  • VP12/VN12: left I/O column, row r + 3
  • VP13/VN13: left I/O column, row r + 4
  • VP14/VN14: left I/O column, row r + 8
  • VP15/VN15: left I/O column, row r + 9

Tile IO

Cells: 1

Switchbox SPEC_INT

virtex5 IO switchbox SPEC_INT muxes IMUX_SPEC[0]
BitsDestination
MAIN[30][15]MAIN[30][9]MAIN[30][10]MAIN[31][9]MAIN[31][12]MAIN[30][13]MAIN[31][10]MAIN[30][7]MAIN[30][11]IMUX_SPEC[0]
Source
000000000off
000100001IMUX_IMUX[4]
000100010HCLK_IO[2]
000100100HCLK_IO[6]
000101000RCLK_IO[0]
000110000IOCLK[0]
001000001IOCLK[2]
001000010HCLK_IO[0]
001000100HCLK_IO[4]
001001000HCLK_IO[8]
001010000RCLK_IO[2]
010000001IOCLK[3]
010000010HCLK_IO[1]
010000100HCLK_IO[5]
010001000HCLK_IO[9]
010010000RCLK_IO[3]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000RCLK_IO[1]
100010000IOCLK[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_SPEC[1]
BitsDestination
MAIN[30][20]MAIN[31][19]MAIN[30][19]MAIN[30][21]MAIN[30][18]MAIN[30][23]MAIN[31][21]MAIN[31][13]IMUX_SPEC[1]
Source
00000000off
00010001IMUX_IMUX[1]
00010010RCLK_IO[2]
00010100RCLK_IO[3]
00100001HCLK_IO[2]
00100010HCLK_IO[0]
00100100HCLK_IO[1]
00101000HCLK_IO[3]
01000001HCLK_IO[6]
01000010HCLK_IO[4]
01000100HCLK_IO[5]
01001000HCLK_IO[7]
10000001RCLK_IO[0]
10000010HCLK_IO[8]
10000100HCLK_IO[9]
10001000RCLK_IO[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_SPEC[2]
BitsDestination
MAIN[30][48]MAIN[30][54]MAIN[30][53]MAIN[31][54]MAIN[31][51]MAIN[30][50]MAIN[31][53]MAIN[30][56]MAIN[30][52]IMUX_SPEC[2]
Source
000000000off
000100001IMUX_IMUX[10]
000100010HCLK_IO[2]
000100100HCLK_IO[6]
000101000RCLK_IO[0]
000110000IOCLK[0]
001000001IOCLK[2]
001000010HCLK_IO[0]
001000100HCLK_IO[4]
001001000HCLK_IO[8]
001010000RCLK_IO[2]
010000001IOCLK[3]
010000010HCLK_IO[1]
010000100HCLK_IO[5]
010001000HCLK_IO[9]
010010000RCLK_IO[3]
100000010HCLK_IO[3]
100000100HCLK_IO[7]
100001000RCLK_IO[1]
100010000IOCLK[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_SPEC[3]
BitsDestination
MAIN[30][43]MAIN[31][44]MAIN[30][44]MAIN[30][42]MAIN[30][45]MAIN[30][40]MAIN[31][42]MAIN[31][50]IMUX_SPEC[3]
Source
00000000off
00010001IMUX_IMUX[7]
00010010RCLK_IO[2]
00010100RCLK_IO[3]
00100001HCLK_IO[2]
00100010HCLK_IO[0]
00100100HCLK_IO[1]
00101000HCLK_IO[3]
01000001HCLK_IO[6]
01000010HCLK_IO[4]
01000100HCLK_IO[5]
01001000HCLK_IO[7]
10000001RCLK_IO[0]
10000010HCLK_IO[8]
10000100HCLK_IO[9]
10001000RCLK_IO[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_IO_ICLK[0]
BitsDestination
MAIN[31][18]MAIN[30][6]MAIN[31][14]MAIN[31][11]MAIN[30][2]MAIN[30][3]MAIN[31][4]MAIN[30][4]MAIN[31][1]IMUX_IO_ICLK[0]
Source
000000000off
000100001IMUX_IMUX[5]
000100010HCLK_IO[2]
000100100HCLK_IO[6]
000101000RCLK_IO[0]
000110000IOCLK[0]
001000001IMUX_IMUX[11]
001000010HCLK_IO[3]
001000100HCLK_IO[7]
001001000RCLK_IO[1]
001010000IOCLK[1]
010000001IOCLK[2]
010000010HCLK_IO[0]
010000100HCLK_IO[4]
010001000HCLK_IO[8]
010010000RCLK_IO[2]
100000001IOCLK[3]
100000010HCLK_IO[1]
100000100HCLK_IO[5]
100001000HCLK_IO[9]
100010000RCLK_IO[3]
virtex5 IO switchbox SPEC_INT muxes IMUX_IO_ICLK[1]
BitsDestination
MAIN[31][45]MAIN[30][57]MAIN[31][52]MAIN[31][49]MAIN[30][61]MAIN[30][60]MAIN[31][59]MAIN[30][59]MAIN[31][62]IMUX_IO_ICLK[1]
Source
000000000off
000100001IMUX_IMUX[5]
000100010HCLK_IO[3]
000100100HCLK_IO[7]
000101000RCLK_IO[1]
000110000IOCLK[1]
001000001IMUX_IMUX[11]
001000010HCLK_IO[2]
001000100HCLK_IO[6]
001001000RCLK_IO[0]
001010000IOCLK[0]
010000001IOCLK[2]
010000010HCLK_IO[0]
010000100HCLK_IO[4]
010001000HCLK_IO[8]
010010000RCLK_IO[2]
100000001IOCLK[3]
100000010HCLK_IO[1]
100000100HCLK_IO[5]
100001000HCLK_IO[9]
100010000RCLK_IO[3]
virtex5 IO switchbox SPEC_INT muxes IMUX_IO_ICLK_OPTINV[0]
BitsDestination
MAIN[31][28]MAIN[30][30]MAIN[30][29]IMUX_IO_ICLK_OPTINV[0]
Source
000~IMUX_IO_ICLK[0]
111IMUX_IO_ICLK[0]
virtex5 IO switchbox SPEC_INT muxes IMUX_IO_ICLK_OPTINV[1]
BitsDestination
MAIN[31][35]MAIN[30][34]MAIN[30][33]IMUX_IO_ICLK_OPTINV[1]
Source
000~IMUX_IO_ICLK[1]
111IMUX_IO_ICLK[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_ILOGIC_CLK[0]
BitsDestination
MAIN[28][21]IMUX_ILOGIC_CLK[0]
Source
0IMUX_IO_ICLK_OPTINV[0]
1IMUX_IO_ICLK_OPTINV[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_ILOGIC_CLK[1]
BitsDestination
MAIN[28][42]IMUX_ILOGIC_CLK[1]
Source
0IMUX_IO_ICLK_OPTINV[1]
1IMUX_IO_ICLK_OPTINV[0]
virtex5 IO switchbox SPEC_INT muxes IMUX_ILOGIC_CLKB[0]
BitsDestination
MAIN[28][20]IMUX_ILOGIC_CLKB[0]
Source
0IMUX_IO_ICLK_OPTINV[0]
1IMUX_IO_ICLK_OPTINV[1]
virtex5 IO switchbox SPEC_INT muxes IMUX_ILOGIC_CLKB[1]
BitsDestination
MAIN[28][43]IMUX_ILOGIC_CLKB[1]
Source
0IMUX_IO_ICLK_OPTINV[1]
1IMUX_IO_ICLK_OPTINV[0]

Bels ILOGIC

virtex5 IO bel ILOGIC pins
PinDirectionILOGIC[0]ILOGIC[1]
CLKinIMUX_ILOGIC_CLK[0]IMUX_ILOGIC_CLK[1]
CLKBinIMUX_ILOGIC_CLKB[0]IMUX_ILOGIC_CLKB[1]
CLKDIVinIMUX_CLK[0] invert by MAIN[28][6]IMUX_CLK[1] invert by MAIN[28][57]
SRinIMUX_CTRL_SITE[0]IMUX_CTRL_SITE[1]
REVinIMUX_IMUX[2]IMUX_IMUX[8]
CE1inIMUX_IMUX[13]IMUX_IMUX[19]
CE2inIMUX_IMUX[16]IMUX_IMUX[22]
BITSLIPinIMUX_IMUX[3]IMUX_IMUX[9]
OoutOUT_BEL[21]OUT_BEL[11]
Q1outOUT_BEL[3], OUT_BEL[9]OUT_BEL[0], OUT_BEL[10]
Q2outOUT_BEL[1], OUT_BEL[19]OUT_BEL[2], OUT_BEL[16]
Q3outOUT_BEL[4]OUT_BEL[7]
Q4outOUT_BEL[6]OUT_BEL[5]
Q5outOUT_BEL[13]OUT_BEL[14]
Q6outOUT_BEL[8]OUT_BEL[20]
CLKPADout-OUT_CLKPAD
virtex5 IO bel ILOGIC attribute bits
AttributeILOGIC[0]ILOGIC[1]
OCLK1_INVMAIN[30][12]MAIN[30][51]
OCLK2_INVMAIN[30][14]MAIN[30][49]
FFI1_INIT bit 0!MAIN[28][26]!MAIN[28][37]
FFI2_INIT bit 0!MAIN[29][20]!MAIN[29][43]
FFI3_INIT bit 0!MAIN[28][27]!MAIN[28][36]
FFI4_INIT bit 0!MAIN[28][31]!MAIN[28][32]
FFI1_SRVAL bit 0!MAIN[28][24]!MAIN[28][39]
FFI2_SRVAL bit 0!MAIN[29][22]!MAIN[29][41]
FFI3_SRVAL bit 0!MAIN[29][28]!MAIN[29][35]
FFI4_SRVAL bit 0!MAIN[28][29]!MAIN[28][34]
FFI_LATCH!MAIN[31][20]!MAIN[31][43]
FFI_SR_SYNCMAIN[31][24]MAIN[31][39]
FFI_SR_ENABLEMAIN[31][26]MAIN[31][37]
FFI_REV_ENABLEMAIN[30][25]MAIN[30][38]
INIT_BITSLIPCNT bit 0!MAIN[29][8]!MAIN[29][55]
INIT_BITSLIPCNT bit 1!MAIN[28][4]!MAIN[28][59]
INIT_BITSLIPCNT bit 2!MAIN[28][2]!MAIN[28][61]
INIT_BITSLIPCNT bit 3!MAIN[29][29]!MAIN[29][34]
INIT_CE bit 0!MAIN[28][13]!MAIN[28][50]
INIT_CE bit 1!MAIN[28][12]!MAIN[28][51]
INIT_RANK1_PARTIAL bit 0!MAIN[28][1]!MAIN[28][62]
INIT_RANK1_PARTIAL bit 1!MAIN[29][5]!MAIN[29][58]
INIT_RANK1_PARTIAL bit 2!MAIN[28][8]!MAIN[28][55]
INIT_RANK1_PARTIAL bit 3!MAIN[29][11]!MAIN[29][52]
INIT_RANK1_PARTIAL bit 4!MAIN[29][14]!MAIN[29][49]
INIT_RANK2 bit 0!MAIN[29][3]!MAIN[29][60]
INIT_RANK2 bit 1!MAIN[28][5]!MAIN[28][58]
INIT_RANK2 bit 2!MAIN[28][11]!MAIN[28][52]
INIT_RANK2 bit 3!MAIN[28][10]!MAIN[28][53]
INIT_RANK2 bit 4!MAIN[29][17]!MAIN[29][46]
INIT_RANK2 bit 5!MAIN[28][19]!MAIN[28][44]
INIT_RANK3 bit 0!MAIN[28][0]!MAIN[28][63]
INIT_RANK3 bit 1!MAIN[29][1]!MAIN[29][62]
INIT_RANK3 bit 2!MAIN[29][7]!MAIN[29][56]
INIT_RANK3 bit 3!MAIN[28][14]!MAIN[28][49]
INIT_RANK3 bit 4!MAIN[29][21]!MAIN[29][42]
INIT_RANK3 bit 5!MAIN[28][28]!MAIN[28][35]
I_DELAY_ENABLEMAIN[30][31]MAIN[30][32]
I_TSBYPASS_ENABLEMAIN[31][31]MAIN[31][32]
FFI_DELAY_ENABLEMAIN[31][17]MAIN[31][46]
FFI_TSBYPASS_ENABLEMAIN[30][17]MAIN[30][46]
MUX_TSBYPASS[enum: ILOGIC_MUX_TSBYPASS][enum: ILOGIC_MUX_TSBYPASS]
SERDESMAIN[28][23]MAIN[28][40]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_RATE[enum: IO_DATA_RATE][enum: IO_DATA_RATE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
INTERFACE_TYPE[enum: ILOGIC_INTERFACE_TYPE][enum: ILOGIC_INTERFACE_TYPE]
NUM_CE[enum: ILOGIC_NUM_CE][enum: ILOGIC_NUM_CE]
BITSLIP_ENABLE bit 0MAIN[28][18]MAIN[28][41]
BITSLIP_ENABLE bit 1MAIN[28][22]MAIN[28][45]
BITSLIP_ENABLE bit 2MAIN[29][12]MAIN[29][33]
BITSLIP_ENABLE bit 3MAIN[29][15]MAIN[29][37]
BITSLIP_ENABLE bit 4MAIN[29][26]MAIN[29][48]
BITSLIP_ENABLE bit 5MAIN[29][30]MAIN[29][51]
BITSLIP_ENABLE bit 6MAIN[31][16]MAIN[31][47]
BITSLIP_SYNCMAIN[29][19]MAIN[29][44]
DDR_CLK_EDGE[enum: ILOGIC_DDR_CLK_EDGE][enum: ILOGIC_DDR_CLK_EDGE]
READBACK_I bit 0MAIN[29][13]MAIN[29][50]
virtex5 IO enum ILOGIC_MUX_TSBYPASS
ILOGIC[0].MUX_TSBYPASSMAIN[30][16]
ILOGIC[1].MUX_TSBYPASSMAIN[30][47]
GND1
T0
virtex5 IO enum IO_SERDES_MODE
ILOGIC[0].SERDES_MODEMAIN[31][15]
ILOGIC[1].SERDES_MODEMAIN[31][48]
MASTER0
SLAVE1
virtex5 IO enum IO_DATA_RATE
ILOGIC[0].DATA_RATEMAIN[31][6]
ILOGIC[1].DATA_RATEMAIN[31][57]
SDR1
DDR0
virtex5 IO enum IO_DATA_WIDTH
ILOGIC[0].DATA_WIDTHMAIN[31][5]MAIN[31][8]MAIN[31][7]MAIN[30][5]
ILOGIC[1].DATA_WIDTHMAIN[31][58]MAIN[31][55]MAIN[31][56]MAIN[30][58]
NONE0000
_20010
_30011
_40100
_50101
_60110
_70111
_81000
_101010
virtex5 IO enum ILOGIC_INTERFACE_TYPE
ILOGIC[0].INTERFACE_TYPEMAIN[31][25]
ILOGIC[1].INTERFACE_TYPEMAIN[31][38]
MEMORY0
NETWORKING1
virtex5 IO enum ILOGIC_NUM_CE
ILOGIC[0].NUM_CEMAIN[30][22]
ILOGIC[1].NUM_CEMAIN[30][41]
_10
_21
virtex5 IO enum ILOGIC_DDR_CLK_EDGE
ILOGIC[0].DDR_CLK_EDGEMAIN[29][31]MAIN[28][30]
ILOGIC[1].DDR_CLK_EDGEMAIN[29][32]MAIN[28][33]
SAME_EDGE_PIPELINED00
SAME_EDGE01
OPPOSITE_EDGE10

Bels OLOGIC

virtex5 IO bel OLOGIC pins
PinDirectionOLOGIC[0]OLOGIC[1]
CLKinIMUX_SPEC[0]IMUX_SPEC[2]
CLKDIVinIMUX_SPEC[1] invert by MAIN[34][13]IMUX_SPEC[3] invert by MAIN[34][50]
SRinIMUX_CTRL_SITE[2]IMUX_CTRL_SITE[3]
REVinIMUX_IMUX[2]IMUX_IMUX[8]
OCEinIMUX_IMUX[27]IMUX_IMUX[33]
TCEinIMUX_IMUX[26]IMUX_IMUX[32]
D1inIMUX_IMUX[41] invert by MAIN[32][24]IMUX_IMUX[47] invert by MAIN[32][39]
D2inIMUX_IMUX[40] invert by MAIN[32][23]IMUX_IMUX[46] invert by MAIN[32][40]
D3inIMUX_IMUX[39] invert by MAIN[35][23]IMUX_IMUX[45] invert by MAIN[35][40]
D4inIMUX_IMUX[38] invert by MAIN[34][20]IMUX_IMUX[44] invert by MAIN[34][43]
D5inIMUX_IMUX[37] invert by MAIN[34][23]IMUX_IMUX[43] invert by MAIN[34][40]
D6inIMUX_IMUX[36] invert by MAIN[35][25]IMUX_IMUX[42] invert by MAIN[35][38]
T1inIMUX_IMUX[24] invert by !MAIN[32][2]IMUX_IMUX[30] invert by !MAIN[32][61]
T2inIMUX_IMUX[25] invert by !MAIN[33][3]IMUX_IMUX[31] invert by !MAIN[33][60]
T3inIMUX_IMUX[28] invert by !MAIN[34][0]IMUX_IMUX[34] invert by !MAIN[34][63]
T4inIMUX_IMUX[29] invert by !MAIN[35][0]IMUX_IMUX[35] invert by !MAIN[35][63]
TQoutOUT_BEL[23]OUT_BEL[12]
virtex5 IO bel OLOGIC attribute bits
AttributeOLOGIC[0]OLOGIC[1]
CLK1_INV!MAIN[33][31]!MAIN[33][32]
CLK2_INV!MAIN[33][30]!MAIN[33][33]
FFO_INIT bit 0!MAIN[35][22]!MAIN[35][41]
FFO_RANK1_INIT bit 0!MAIN[33][20]!MAIN[33][43]
FFO_RANK1_INIT bit 1!MAIN[33][18]!MAIN[33][45]
FFO_RANK1_INIT bit 2!MAIN[32][15]!MAIN[32][48]
FFO_RANK1_INIT bit 3!MAIN[32][13]!MAIN[32][50]
FFO_RANK1_INIT bit 4!MAIN[33][11]!MAIN[33][52]
FFO_RANK1_INIT bit 5!MAIN[33][8]!MAIN[33][55]
FFO_RANK2_INIT bit 0!MAIN[35][13]!MAIN[35][50]
FFO_RANK2_INIT bit 1!MAIN[34][11]!MAIN[34][52]
FFO_RANK2_INIT bit 2!MAIN[35][6]!MAIN[35][57]
FFO_RANK2_INIT bit 3!MAIN[34][2]!MAIN[34][61]
FFO_SRVAL bit 0!MAIN[34][31]!MAIN[34][32]
FFO_SRVAL bit 1!MAIN[34][30]!MAIN[34][33]
FFO_SRVAL bit 2!MAIN[35][31]!MAIN[35][32]
FFO_SR_SYNCMAIN[35][26]MAIN[35][37]
FFO_RANK1_SR_SYNCMAIN[33][0]MAIN[33][63]
FFO_RANK2_SR_SYNCMAIN[34][12]MAIN[34][51]
FFO_LOADGEN_SR_SYNCMAIN[32][26]MAIN[32][37]
FFO_SR_ENABLEMAIN[34][27]MAIN[34][36]
FFO_REV_ENABLEMAIN[34][26]MAIN[34][37]
V5_MUX_O[enum: OLOGIC_V5_MUX_O][enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0!MAIN[34][8]!MAIN[34][55]
FFT_RANK1_INIT bit 0!MAIN[35][16]!MAIN[35][47]
FFT_RANK1_INIT bit 1!MAIN[34][7]!MAIN[34][56]
FFT_RANK1_INIT bit 2!MAIN[35][4]!MAIN[35][59]
FFT_RANK1_INIT bit 3!MAIN[35][1]!MAIN[35][62]
FFT_SRVAL bit 0!MAIN[35][12]!MAIN[35][51]
FFT_SRVAL bit 1!MAIN[35][10]!MAIN[35][53]
FFT_SRVAL bit 2!MAIN[34][10]!MAIN[34][53]
FFT_SR_SYNCMAIN[34][19]MAIN[34][44]
FFT_RANK1_SR_SYNCMAIN[32][1]MAIN[32][62]
FFT_SR_ENABLEMAIN[35][15]MAIN[35][48]
FFT_REV_ENABLEMAIN[34][15]MAIN[34][48]
V5_MUX_T[enum: OLOGIC_V5_MUX_T][enum: OLOGIC_V5_MUX_T]
INIT_LOADCNT bit 0!MAIN[35][24]!MAIN[35][39]
INIT_LOADCNT bit 1!MAIN[35][27]!MAIN[35][36]
INIT_LOADCNT bit 2!MAIN[33][23]!MAIN[33][40]
INIT_LOADCNT bit 3!MAIN[33][29]!MAIN[33][34]
SERDESMAIN[35][20]MAIN[35][43]
SERDES_MODE[enum: IO_SERDES_MODE][enum: IO_SERDES_MODE]
DATA_WIDTH[enum: IO_DATA_WIDTH][enum: IO_DATA_WIDTH]
TRISTATE_WIDTH[enum: OLOGIC_TRISTATE_WIDTH][enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLEMAIN[28][16]MAIN[28][47]
MISR_ENABLE_FDBKMAIN[29][18]MAIN[29][45]
MISR_RESETMAIN[28][15]MAIN[28][48]
MISR_CLK_SELECT[enum: OLOGIC_MISR_CLK_SELECT][enum: OLOGIC_MISR_CLK_SELECT]
virtex5 IO enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_OMAIN[35][29]MAIN[34][29]MAIN[34][6]MAIN[35][5]MAIN[35][30]
OLOGIC[1].V5_MUX_OMAIN[35][34]MAIN[34][34]MAIN[34][57]MAIN[35][58]MAIN[35][33]
NONE00000
D100001
SERDES_SDR00010
SERDES_DDR00100
LATCH10010
FF01010
DDR01100
virtex5 IO enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_TMAIN[35][18]MAIN[34][16]MAIN[34][17]MAIN[35][17]MAIN[35][11]
OLOGIC[1].V5_MUX_TMAIN[35][45]MAIN[34][47]MAIN[34][46]MAIN[35][46]MAIN[35][52]
NONE00000
T100001
SERDES_DDR00110
LATCH11000
FF01010
DDR00100
virtex5 IO enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODEMAIN[34][5]
OLOGIC[1].SERDES_MODEMAIN[34][58]
MASTER0
SLAVE1
virtex5 IO enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTHMAIN[32][30]MAIN[32][29]MAIN[34][28]MAIN[35][28]MAIN[32][28]MAIN[32][27]MAIN[33][27]MAIN[33][26]
OLOGIC[1].DATA_WIDTHMAIN[32][33]MAIN[32][34]MAIN[34][35]MAIN[35][35]MAIN[32][35]MAIN[32][36]MAIN[33][36]MAIN[33][37]
NONE00000000
_200000001
_300000010
_400000100
_500001000
_600010000
_700100000
_801000000
_1010000000
virtex5 IO enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTHMAIN[35][19]
OLOGIC[1].TRISTATE_WIDTHMAIN[35][44]
_10
_41
virtex5 IO enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECTMAIN[29][16]MAIN[28][17]
OLOGIC[1].MISR_CLK_SELECTMAIN[29][47]MAIN[28][46]
NONE00
CLK101
CLK210

Bels IODELAY_V5

virtex5 IO bel IODELAY_V5 pins
PinDirectionIODELAY[0]IODELAY[1]
CEinIMUX_IMUX[14]IMUX_IMUX[20]
DATAINinIMUX_IMUX[17] invert by !MAIN[30][8]IMUX_IMUX[23] invert by !MAIN[30][55]
INCinIMUX_IMUX[15]IMUX_IMUX[21]
RSTinIMUX_IMUX[12]IMUX_IMUX[18]
virtex5 IO bel IODELAY_V5 attribute bits
AttributeIODELAY[0]IODELAY[1]
ENABLE bit 0!MAIN[32][8]!MAIN[32][43]
ENABLE bit 1!MAIN[32][18]!MAIN[32][45]
ENABLE bit 2!MAIN[32][20]!MAIN[32][55]
ENABLE bit 3!MAIN[33][16]!MAIN[33][47]
DELAY_SRC[enum: IODELAY_V5_DELAY_SRC][enum: IODELAY_V5_DELAY_SRC]
DELAYCHAIN_OSCMAIN[31][2]MAIN[31][61]
HIGH_PERFORMANCE_MODEMAIN[32][14]MAIN[32][49]
LEGIDELAY!MAIN[33][9]!MAIN[33][54]
IDELAY_TYPE[enum: IODELAY_V5_IDELAY_TYPE][enum: IODELAY_V5_IDELAY_TYPE]
IDELAY_VALUE_CUR bit 0!MAIN[33][28]!MAIN[33][35]
IDELAY_VALUE_CUR bit 1!MAIN[32][31]!MAIN[32][32]
IDELAY_VALUE_CUR bit 2!MAIN[32][22]!MAIN[32][41]
IDELAY_VALUE_CUR bit 3!MAIN[32][19]!MAIN[32][44]
IDELAY_VALUE_CUR bit 4!MAIN[32][16]!MAIN[32][47]
IDELAY_VALUE_CUR bit 5!MAIN[32][12]!MAIN[32][51]
IDELAY_VALUE_INIT bit 0MAIN[32][21]MAIN[32][42]
IDELAY_VALUE_INIT bit 1MAIN[32][5]MAIN[32][58]
IDELAY_VALUE_INIT bit 2MAIN[32][10]MAIN[32][53]
IDELAY_VALUE_INIT bit 3MAIN[33][6]MAIN[33][57]
IDELAY_VALUE_INIT bit 4MAIN[32][17]MAIN[32][46]
IDELAY_VALUE_INIT bit 5MAIN[32][3]MAIN[32][60]
ODELAY_VALUE bit 0MAIN[32][7]MAIN[32][56]
ODELAY_VALUE bit 1MAIN[33][15]MAIN[33][48]
ODELAY_VALUE bit 2MAIN[33][22]MAIN[33][41]
ODELAY_VALUE bit 3MAIN[33][21]MAIN[33][42]
ODELAY_VALUE bit 4MAIN[33][17]MAIN[33][46]
ODELAY_VALUE bit 5MAIN[33][13]MAIN[33][50]
virtex5 IO enum IODELAY_V5_DELAY_SRC
IODELAY[0].DELAY_SRCMAIN[31][0]MAIN[31][3]MAIN[30][1]MAIN[30][0]
IODELAY[1].DELAY_SRCMAIN[31][63]MAIN[31][60]MAIN[30][62]MAIN[30][63]
NONE0000
I0001
IO0011
O0110
DATAIN1000
virtex5 IO enum IODELAY_V5_IDELAY_TYPE
IODELAY[0].IDELAY_TYPEMAIN[33][5]MAIN[33][7]
IODELAY[1].IDELAY_TYPEMAIN[33][58]MAIN[33][56]
FIXED00
VARIABLE01
DEFAULT10

Bels IOB

virtex5 IO bel IOB pins
PinDirectionIOB[0]IOB[1]
virtex5 IO bel IOB attribute bits
AttributeIOB[0]IOB[1]
PULL[enum: IOB_PULL][enum: IOB_PULL]
VREF_SYSMONMAIN[36][30]MAIN[36][33]
VRMAIN[36][3]MAIN[36][60]
IBUF_MODE[enum: IOB_IBUF_MODE][enum: IOB_IBUF_MODE]
I_INV!MAIN[31][23]!MAIN[31][40]
OUTPUT_ENABLE bit 0MAIN[36][19]MAIN[36][41]
OUTPUT_ENABLE bit 1MAIN[36][22]MAIN[36][44]
OUTPUT_DELAYMAIN[36][7]MAIN[36][56]
DCI_MODE[enum: IOB_DCI_MODE][enum: IOB_DCI_MODE]
DCI_MISC bit 0MAIN[37][16]MAIN[37][47]
DCI_MISC bit 1MAIN[37][26]MAIN[37][37]
DCI_TMAIN[36][12]MAIN[36][51]
DCIUPDATEMODE_ASREQUIRED!MAIN[37][5]!MAIN[37][58]
V4_PDRIVE bit 0!MAIN[36][14]!MAIN[36][49]
V4_PDRIVE bit 1MAIN[37][0]MAIN[37][63]
V4_PDRIVE bit 2MAIN[37][13]MAIN[37][50]
V4_PDRIVE bit 3!MAIN[37][9]!MAIN[37][54]
V4_PDRIVE bit 4MAIN[37][10]MAIN[37][53]
V4_NDRIVE bit 0!MAIN[36][10]!MAIN[36][53]
V4_NDRIVE bit 1!MAIN[37][2]!MAIN[37][61]
V4_NDRIVE bit 2!MAIN[37][14]!MAIN[37][49]
V4_NDRIVE bit 3MAIN[36][6]MAIN[36][57]
V4_NDRIVE bit 4MAIN[36][11]MAIN[36][52]
V5_PSLEW bit 0MAIN[37][17]MAIN[37][46]
V5_PSLEW bit 1MAIN[36][23]MAIN[36][40]
V5_PSLEW bit 2MAIN[37][23]MAIN[37][40]
V5_PSLEW bit 3MAIN[37][30]MAIN[37][33]
V5_PSLEW bit 4MAIN[37][29]MAIN[37][34]
V5_PSLEW bit 5MAIN[37][27]MAIN[37][36]
V5_NSLEW bit 0MAIN[36][31]MAIN[36][32]
V5_NSLEW bit 1MAIN[36][27]MAIN[36][36]
V5_NSLEW bit 2MAIN[37][31]MAIN[37][32]
V5_NSLEW bit 3MAIN[37][28]MAIN[37][35]
V5_NSLEW bit 4MAIN[36][26]MAIN[36][37]
V5_NSLEW bit 5MAIN[37][20]MAIN[37][43]
V5_OUTPUT_MISC bit 0MAIN[36][24]MAIN[36][39]
V5_OUTPUT_MISC bit 1MAIN[37][24]MAIN[37][39]
V5_OUTPUT_MISC bit 2MAIN[37][25]MAIN[37][38]
V5_OUTPUT_MISC bit 3MAIN[36][20]MAIN[36][43]
V5_OUTPUT_MISC bit 4MAIN[36][4]MAIN[36][59]
V5_OUTPUT_MISC bit 5MAIN[37][3]MAIN[37][60]
V5_LVDS bit 0MAIN[37][11]MAIN[37][52]
V5_LVDS bit 1MAIN[36][13]MAIN[36][50]
V5_LVDS bit 2MAIN[37][15]MAIN[37][48]
V5_LVDS bit 3MAIN[36][17]MAIN[36][46]
V5_LVDS bit 4MAIN[36][18]MAIN[36][45]
V5_LVDS bit 5MAIN[36][21]MAIN[36][42]
V5_LVDS bit 6MAIN[37][21]MAIN[37][42]
V5_LVDS bit 7MAIN[37][22]MAIN[37][41]
V5_LVDS bit 8MAIN[36][5]MAIN[36][58]
virtex5 IO enum IOB_PULL
IOB[0].PULLMAIN[37][19]MAIN[36][15]MAIN[36][16]
IOB[1].PULLMAIN[37][44]MAIN[36][48]MAIN[36][47]
NONE001
PULLUP011
PULLDOWN000
KEEPER101
virtex5 IO enum IOB_IBUF_MODE
IOB[0].IBUF_MODEMAIN[36][29]MAIN[36][25]MAIN[37][18]
IOB[1].IBUF_MODEMAIN[36][34]MAIN[36][38]MAIN[37][45]
NONE000
VREF001
DIFF010
CMOS111
virtex5 IO enum IOB_DCI_MODE
IOB[0].DCI_MODEMAIN[37][8]MAIN[36][8]MAIN[37][7]
IOB[1].DCI_MODEMAIN[37][55]MAIN[36][55]MAIN[37][56]
NONE000
OUTPUT001
OUTPUT_HALF010
TERM_VCC011
TERM_SPLIT100

Bel wires

virtex5 IO bel wires
WirePins
IMUX_CLK[0]ILOGIC[0].CLKDIV
IMUX_CLK[1]ILOGIC[1].CLKDIV
IMUX_CTRL_SITE[0]ILOGIC[0].SR
IMUX_CTRL_SITE[1]ILOGIC[1].SR
IMUX_CTRL_SITE[2]OLOGIC[0].SR
IMUX_CTRL_SITE[3]OLOGIC[1].SR
IMUX_IMUX[2]ILOGIC[0].REV, OLOGIC[0].REV
IMUX_IMUX[3]ILOGIC[0].BITSLIP
IMUX_IMUX[8]ILOGIC[1].REV, OLOGIC[1].REV
IMUX_IMUX[9]ILOGIC[1].BITSLIP
IMUX_IMUX[12]IODELAY[0].RST
IMUX_IMUX[13]ILOGIC[0].CE1
IMUX_IMUX[14]IODELAY[0].CE
IMUX_IMUX[15]IODELAY[0].INC
IMUX_IMUX[16]ILOGIC[0].CE2
IMUX_IMUX[17]IODELAY[0].DATAIN
IMUX_IMUX[18]IODELAY[1].RST
IMUX_IMUX[19]ILOGIC[1].CE1
IMUX_IMUX[20]IODELAY[1].CE
IMUX_IMUX[21]IODELAY[1].INC
IMUX_IMUX[22]ILOGIC[1].CE2
IMUX_IMUX[23]IODELAY[1].DATAIN
IMUX_IMUX[24]OLOGIC[0].T1
IMUX_IMUX[25]OLOGIC[0].T2
IMUX_IMUX[26]OLOGIC[0].TCE
IMUX_IMUX[27]OLOGIC[0].OCE
IMUX_IMUX[28]OLOGIC[0].T3
IMUX_IMUX[29]OLOGIC[0].T4
IMUX_IMUX[30]OLOGIC[1].T1
IMUX_IMUX[31]OLOGIC[1].T2
IMUX_IMUX[32]OLOGIC[1].TCE
IMUX_IMUX[33]OLOGIC[1].OCE
IMUX_IMUX[34]OLOGIC[1].T3
IMUX_IMUX[35]OLOGIC[1].T4
IMUX_IMUX[36]OLOGIC[0].D6
IMUX_IMUX[37]OLOGIC[0].D5
IMUX_IMUX[38]OLOGIC[0].D4
IMUX_IMUX[39]OLOGIC[0].D3
IMUX_IMUX[40]OLOGIC[0].D2
IMUX_IMUX[41]OLOGIC[0].D1
IMUX_IMUX[42]OLOGIC[1].D6
IMUX_IMUX[43]OLOGIC[1].D5
IMUX_IMUX[44]OLOGIC[1].D4
IMUX_IMUX[45]OLOGIC[1].D3
IMUX_IMUX[46]OLOGIC[1].D2
IMUX_IMUX[47]OLOGIC[1].D1
OUT_BEL[0]ILOGIC[1].Q1
OUT_BEL[1]ILOGIC[0].Q2
OUT_BEL[2]ILOGIC[1].Q2
OUT_BEL[3]ILOGIC[0].Q1
OUT_BEL[4]ILOGIC[0].Q3
OUT_BEL[5]ILOGIC[1].Q4
OUT_BEL[6]ILOGIC[0].Q4
OUT_BEL[7]ILOGIC[1].Q3
OUT_BEL[8]ILOGIC[0].Q6
OUT_BEL[9]ILOGIC[0].Q1
OUT_BEL[10]ILOGIC[1].Q1
OUT_BEL[11]ILOGIC[1].O
OUT_BEL[12]OLOGIC[1].TQ
OUT_BEL[13]ILOGIC[0].Q5
OUT_BEL[14]ILOGIC[1].Q5
OUT_BEL[16]ILOGIC[1].Q2
OUT_BEL[19]ILOGIC[0].Q2
OUT_BEL[20]ILOGIC[1].Q6
OUT_BEL[21]ILOGIC[0].O
OUT_BEL[23]OLOGIC[0].TQ
IMUX_SPEC[0]OLOGIC[0].CLK
IMUX_SPEC[1]OLOGIC[0].CLKDIV
IMUX_SPEC[2]OLOGIC[1].CLK
IMUX_SPEC[3]OLOGIC[1].CLKDIV
OUT_CLKPADILOGIC[1].CLKPAD
IMUX_ILOGIC_CLK[0]ILOGIC[0].CLK
IMUX_ILOGIC_CLK[1]ILOGIC[1].CLK
IMUX_ILOGIC_CLKB[0]ILOGIC[0].CLKB
IMUX_ILOGIC_CLKB[1]ILOGIC[1].CLKB

Bitstream

virtex5 IO rect MAIN
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 F48 F49 F50 F51 F52 F53
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 0 - IODELAY[1]: DELAY_SRC bit 0 IODELAY[1]: DELAY_SRC bit 3 - OLOGIC[1]: FFO_RANK1_SR_SYNC OLOGIC[1]: !invert T3 OLOGIC[1]: !invert T4 - IOB[1]: V4_PDRIVE bit 1 - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 0 ILOGIC[1]: ! INIT_RANK3 bit 1 IODELAY[1]: DELAY_SRC bit 1 SPEC_INT: mux IMUX_IO_ICLK[1] bit 0 OLOGIC[1]: FFT_RANK1_SR_SYNC - - OLOGIC[1]: ! FFT_RANK1_INIT bit 3 - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_BITSLIPCNT bit 2 - SPEC_INT: mux IMUX_IO_ICLK[1] bit 4 IODELAY[1]: DELAYCHAIN_OSC OLOGIC[1]: !invert T1 - OLOGIC[1]: ! FFO_RANK2_INIT bit 3 - - IOB[1]: ! V4_NDRIVE bit 1 - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 0 SPEC_INT: mux IMUX_IO_ICLK[1] bit 3 IODELAY[1]: DELAY_SRC bit 2 IODELAY[1]: IDELAY_VALUE_INIT bit 5 OLOGIC[1]: !invert T2 - - IOB[1]: VR IOB[1]: V5_OUTPUT_MISC bit 5 - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_BITSLIPCNT bit 1 - SPEC_INT: mux IMUX_IO_ICLK[1] bit 1 SPEC_INT: mux IMUX_IO_ICLK[1] bit 2 - - - OLOGIC[1]: ! FFT_RANK1_INIT bit 2 IOB[1]: V5_OUTPUT_MISC bit 4 - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 1 ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 1 ILOGIC[1]: DATA_WIDTH bit 0 ILOGIC[1]: DATA_WIDTH bit 3 IODELAY[1]: IDELAY_VALUE_INIT bit 1 IODELAY[1]: IDELAY_TYPE bit 1 OLOGIC[1]: SERDES_MODE bit 0 OLOGIC[1]: V5_MUX_O bit 1 IOB[1]: V5_LVDS bit 8 IOB[1]: ! DCIUPDATEMODE_ASREQUIRED - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: invert CLKDIV - SPEC_INT: mux IMUX_IO_ICLK[1] bit 7 ILOGIC[1]: DATA_RATE bit 0 - IODELAY[1]: IDELAY_VALUE_INIT bit 3 OLOGIC[1]: V5_MUX_O bit 2 OLOGIC[1]: ! FFO_RANK2_INIT bit 2 IOB[1]: V4_NDRIVE bit 3 - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 2 SPEC_INT: mux IMUX_SPEC[2] bit 1 ILOGIC[1]: DATA_WIDTH bit 1 IODELAY[1]: ODELAY_VALUE bit 0 IODELAY[1]: IDELAY_TYPE bit 0 OLOGIC[1]: ! FFT_RANK1_INIT bit 1 - IOB[1]: OUTPUT_DELAY IOB[1]: DCI_MODE bit 0 - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 2 ILOGIC[1]: ! INIT_BITSLIPCNT bit 0 IODELAY[1]: !invert DATAIN ILOGIC[1]: DATA_WIDTH bit 2 IODELAY[1]: ! ENABLE bit 2 OLOGIC[1]: ! FFO_RANK1_INIT bit 5 OLOGIC[1]: ! FFT_INIT bit 0 - IOB[1]: DCI_MODE bit 1 IOB[1]: DCI_MODE bit 2 - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_SPEC[2] bit 7 SPEC_INT: mux IMUX_SPEC[2] bit 5 - IODELAY[1]: ! LEGIDELAY - - - IOB[1]: ! V4_PDRIVE bit 3 - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 3 - SPEC_INT: mux IMUX_SPEC[2] bit 6 SPEC_INT: mux IMUX_SPEC[2] bit 2 IODELAY[1]: IDELAY_VALUE_INIT bit 2 - OLOGIC[1]: ! FFT_SRVAL bit 2 OLOGIC[1]: ! FFT_SRVAL bit 1 IOB[1]: ! V4_NDRIVE bit 0 IOB[1]: V4_PDRIVE bit 4 - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 2 ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 3 SPEC_INT: mux IMUX_SPEC[2] bit 0 SPEC_INT: mux IMUX_IO_ICLK[1] bit 6 - OLOGIC[1]: ! FFO_RANK1_INIT bit 4 OLOGIC[1]: ! FFO_RANK2_INIT bit 1 OLOGIC[1]: V5_MUX_T bit 0 IOB[1]: V4_NDRIVE bit 4 IOB[1]: V5_LVDS bit 0 - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_CE bit 1 ILOGIC[1]: BITSLIP_ENABLE bit 5 ILOGIC[1]: OCLK1_INV SPEC_INT: mux IMUX_SPEC[2] bit 4 IODELAY[1]: ! IDELAY_VALUE_CUR bit 5 - OLOGIC[1]: FFO_RANK2_SR_SYNC OLOGIC[1]: ! FFT_SRVAL bit 0 IOB[1]: DCI_T - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_CE bit 0 ILOGIC[1]: READBACK_I bit 0 SPEC_INT: mux IMUX_SPEC[2] bit 3 SPEC_INT: mux IMUX_SPEC[3] bit 0 OLOGIC[1]: ! FFO_RANK1_INIT bit 3 IODELAY[1]: ODELAY_VALUE bit 5 OLOGIC[1]: invert CLKDIV OLOGIC[1]: ! FFO_RANK2_INIT bit 0 IOB[1]: V5_LVDS bit 1 IOB[1]: V4_PDRIVE bit 2 - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 3 ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 4 ILOGIC[1]: OCLK2_INV SPEC_INT: mux IMUX_IO_ICLK[1] bit 5 IODELAY[1]: HIGH_PERFORMANCE_MODE - - - IOB[1]: ! V4_PDRIVE bit 0 IOB[1]: ! V4_NDRIVE bit 2 - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_RESET ILOGIC[1]: BITSLIP_ENABLE bit 4 SPEC_INT: mux IMUX_SPEC[2] bit 8 ILOGIC[1]: SERDES_MODE bit 0 OLOGIC[1]: ! FFO_RANK1_INIT bit 2 IODELAY[1]: ODELAY_VALUE bit 1 OLOGIC[1]: FFT_REV_ENABLE OLOGIC[1]: FFT_SR_ENABLE IOB[1]: PULL bit 1 IOB[1]: V5_LVDS bit 2 - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_ENABLE OLOGIC[1]: MISR_CLK_SELECT bit 1 ILOGIC[1]: MUX_TSBYPASS bit 0 ILOGIC[1]: BITSLIP_ENABLE bit 6 IODELAY[1]: ! IDELAY_VALUE_CUR bit 4 IODELAY[1]: ! ENABLE bit 3 OLOGIC[1]: V5_MUX_T bit 3 OLOGIC[1]: ! FFT_RANK1_INIT bit 0 IOB[1]: PULL bit 0 IOB[1]: DCI_MISC bit 0 - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[1]: MISR_CLK_SELECT bit 0 ILOGIC[1]: ! INIT_RANK2 bit 4 ILOGIC[1]: FFI_TSBYPASS_ENABLE ILOGIC[1]: FFI_DELAY_ENABLE IODELAY[1]: IDELAY_VALUE_INIT bit 4 IODELAY[1]: ODELAY_VALUE bit 4 OLOGIC[1]: V5_MUX_T bit 2 OLOGIC[1]: V5_MUX_T bit 1 IOB[1]: V5_LVDS bit 3 IOB[1]: V5_PSLEW bit 0 - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_ENABLE bit 1 OLOGIC[1]: MISR_ENABLE_FDBK SPEC_INT: mux IMUX_SPEC[3] bit 3 SPEC_INT: mux IMUX_IO_ICLK[1] bit 8 IODELAY[1]: ! ENABLE bit 1 OLOGIC[1]: ! FFO_RANK1_INIT bit 1 - OLOGIC[1]: V5_MUX_T bit 4 IOB[1]: V5_LVDS bit 4 IOB[1]: IBUF_MODE bit 0 - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK2 bit 5 ILOGIC[1]: BITSLIP_SYNC SPEC_INT: mux IMUX_SPEC[3] bit 5 SPEC_INT: mux IMUX_SPEC[3] bit 6 IODELAY[1]: ! IDELAY_VALUE_CUR bit 3 - OLOGIC[1]: FFT_SR_SYNC OLOGIC[1]: TRISTATE_WIDTH bit 0 IOB[1]: OUTPUT_ENABLE bit 1 IOB[1]: PULL bit 2 - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_ILOGIC_CLKB[1] bit 0 ILOGIC[1]: ! FFI2_INIT bit 0 SPEC_INT: mux IMUX_SPEC[3] bit 7 ILOGIC[1]: ! FFI_LATCH IODELAY[1]: ! ENABLE bit 0 OLOGIC[1]: ! FFO_RANK1_INIT bit 0 OLOGIC[1]: invert D4 OLOGIC[1]: SERDES IOB[1]: V5_OUTPUT_MISC bit 3 IOB[1]: V5_NSLEW bit 5 - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_ILOGIC_CLK[1] bit 0 ILOGIC[1]: ! INIT_RANK3 bit 4 SPEC_INT: mux IMUX_SPEC[3] bit 4 SPEC_INT: mux IMUX_SPEC[3] bit 1 IODELAY[1]: IDELAY_VALUE_INIT bit 0 IODELAY[1]: ODELAY_VALUE bit 3 - - IOB[1]: V5_LVDS bit 5 IOB[1]: V5_LVDS bit 6 - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: BITSLIP_ENABLE bit 0 ILOGIC[1]: ! FFI2_SRVAL bit 0 ILOGIC[1]: NUM_CE bit 0 - IODELAY[1]: ! IDELAY_VALUE_CUR bit 2 IODELAY[1]: ODELAY_VALUE bit 2 - OLOGIC[1]: ! FFO_INIT bit 0 IOB[1]: OUTPUT_ENABLE bit 0 IOB[1]: V5_LVDS bit 7 - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: SERDES - SPEC_INT: mux IMUX_SPEC[3] bit 2 IOB[1]: ! I_INV OLOGIC[1]: invert D2 OLOGIC[1]: ! INIT_LOADCNT bit 2 OLOGIC[1]: invert D5 OLOGIC[1]: invert D3 IOB[1]: V5_PSLEW bit 1 IOB[1]: V5_PSLEW bit 2 - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI1_SRVAL bit 0 - - ILOGIC[1]: FFI_SR_SYNC OLOGIC[1]: invert D1 - - OLOGIC[1]: ! INIT_LOADCNT bit 0 IOB[1]: V5_OUTPUT_MISC bit 0 IOB[1]: V5_OUTPUT_MISC bit 1 - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: FFI_REV_ENABLE ILOGIC[1]: INTERFACE_TYPE bit 0 - - - OLOGIC[1]: invert D6 IOB[1]: IBUF_MODE bit 1 IOB[1]: V5_OUTPUT_MISC bit 2 - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI1_INIT bit 0 ILOGIC[1]: BITSLIP_ENABLE bit 3 - ILOGIC[1]: FFI_SR_ENABLE OLOGIC[1]: FFO_LOADGEN_SR_SYNC OLOGIC[1]: DATA_WIDTH bit 0 OLOGIC[1]: FFO_REV_ENABLE OLOGIC[1]: FFO_SR_SYNC IOB[1]: V5_NSLEW bit 4 IOB[1]: DCI_MISC bit 1 - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI3_INIT bit 0 - - - OLOGIC[1]: DATA_WIDTH bit 2 OLOGIC[1]: DATA_WIDTH bit 1 OLOGIC[1]: FFO_SR_ENABLE OLOGIC[1]: ! INIT_LOADCNT bit 1 IOB[1]: V5_NSLEW bit 1 IOB[1]: V5_PSLEW bit 5 - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! INIT_RANK3 bit 5 ILOGIC[1]: ! FFI3_SRVAL bit 0 - SPEC_INT: mux IMUX_IO_ICLK_OPTINV[1] bit 2 OLOGIC[1]: DATA_WIDTH bit 3 IODELAY[1]: ! IDELAY_VALUE_CUR bit 0 OLOGIC[1]: DATA_WIDTH bit 5 OLOGIC[1]: DATA_WIDTH bit 4 - IOB[1]: V5_NSLEW bit 3 - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI4_SRVAL bit 0 ILOGIC[1]: ! INIT_BITSLIPCNT bit 3 SPEC_INT: mux IMUX_IO_ICLK_OPTINV[1] bit 1 - OLOGIC[1]: DATA_WIDTH bit 6 OLOGIC[1]: ! INIT_LOADCNT bit 3 OLOGIC[1]: V5_MUX_O bit 3 OLOGIC[1]: V5_MUX_O bit 4 IOB[1]: IBUF_MODE bit 2 IOB[1]: V5_PSLEW bit 4 - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: DDR_CLK_EDGE bit 0 ILOGIC[1]: BITSLIP_ENABLE bit 2 SPEC_INT: mux IMUX_IO_ICLK_OPTINV[1] bit 0 - OLOGIC[1]: DATA_WIDTH bit 7 OLOGIC[1]: ! CLK2_INV OLOGIC[1]: ! FFO_SRVAL bit 1 OLOGIC[1]: V5_MUX_O bit 0 IOB[1]: VREF_SYSMON IOB[1]: V5_PSLEW bit 3 - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[1]: ! FFI4_INIT bit 0 ILOGIC[1]: DDR_CLK_EDGE bit 1 ILOGIC[1]: I_DELAY_ENABLE ILOGIC[1]: I_TSBYPASS_ENABLE IODELAY[1]: ! IDELAY_VALUE_CUR bit 1 OLOGIC[1]: ! CLK1_INV OLOGIC[1]: ! FFO_SRVAL bit 0 OLOGIC[1]: ! FFO_SRVAL bit 2 IOB[1]: V5_NSLEW bit 0 IOB[1]: V5_NSLEW bit 2 - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI4_INIT bit 0 ILOGIC[0]: DDR_CLK_EDGE bit 1 ILOGIC[0]: I_DELAY_ENABLE ILOGIC[0]: I_TSBYPASS_ENABLE IODELAY[0]: ! IDELAY_VALUE_CUR bit 1 OLOGIC[0]: ! CLK1_INV OLOGIC[0]: ! FFO_SRVAL bit 0 OLOGIC[0]: ! FFO_SRVAL bit 2 IOB[0]: V5_NSLEW bit 0 IOB[0]: V5_NSLEW bit 2 - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: DDR_CLK_EDGE bit 0 ILOGIC[0]: BITSLIP_ENABLE bit 5 SPEC_INT: mux IMUX_IO_ICLK_OPTINV[0] bit 1 - OLOGIC[0]: DATA_WIDTH bit 7 OLOGIC[0]: ! CLK2_INV OLOGIC[0]: ! FFO_SRVAL bit 1 OLOGIC[0]: V5_MUX_O bit 0 IOB[0]: VREF_SYSMON IOB[0]: V5_PSLEW bit 3 - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI4_SRVAL bit 0 ILOGIC[0]: ! INIT_BITSLIPCNT bit 3 SPEC_INT: mux IMUX_IO_ICLK_OPTINV[0] bit 0 - OLOGIC[0]: DATA_WIDTH bit 6 OLOGIC[0]: ! INIT_LOADCNT bit 3 OLOGIC[0]: V5_MUX_O bit 3 OLOGIC[0]: V5_MUX_O bit 4 IOB[0]: IBUF_MODE bit 2 IOB[0]: V5_PSLEW bit 4 - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 5 ILOGIC[0]: ! FFI3_SRVAL bit 0 - SPEC_INT: mux IMUX_IO_ICLK_OPTINV[0] bit 2 OLOGIC[0]: DATA_WIDTH bit 3 IODELAY[0]: ! IDELAY_VALUE_CUR bit 0 OLOGIC[0]: DATA_WIDTH bit 5 OLOGIC[0]: DATA_WIDTH bit 4 - IOB[0]: V5_NSLEW bit 3 - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI3_INIT bit 0 - - - OLOGIC[0]: DATA_WIDTH bit 2 OLOGIC[0]: DATA_WIDTH bit 1 OLOGIC[0]: FFO_SR_ENABLE OLOGIC[0]: ! INIT_LOADCNT bit 1 IOB[0]: V5_NSLEW bit 1 IOB[0]: V5_PSLEW bit 5 - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI1_INIT bit 0 ILOGIC[0]: BITSLIP_ENABLE bit 4 - ILOGIC[0]: FFI_SR_ENABLE OLOGIC[0]: FFO_LOADGEN_SR_SYNC OLOGIC[0]: DATA_WIDTH bit 0 OLOGIC[0]: FFO_REV_ENABLE OLOGIC[0]: FFO_SR_SYNC IOB[0]: V5_NSLEW bit 4 IOB[0]: DCI_MISC bit 1 - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: FFI_REV_ENABLE ILOGIC[0]: INTERFACE_TYPE bit 0 - - - OLOGIC[0]: invert D6 IOB[0]: IBUF_MODE bit 1 IOB[0]: V5_OUTPUT_MISC bit 2 - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! FFI1_SRVAL bit 0 - - ILOGIC[0]: FFI_SR_SYNC OLOGIC[0]: invert D1 - - OLOGIC[0]: ! INIT_LOADCNT bit 0 IOB[0]: V5_OUTPUT_MISC bit 0 IOB[0]: V5_OUTPUT_MISC bit 1 - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: SERDES - SPEC_INT: mux IMUX_SPEC[1] bit 2 IOB[0]: ! I_INV OLOGIC[0]: invert D2 OLOGIC[0]: ! INIT_LOADCNT bit 2 OLOGIC[0]: invert D5 OLOGIC[0]: invert D3 IOB[0]: V5_PSLEW bit 1 IOB[0]: V5_PSLEW bit 2 - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_ENABLE bit 1 ILOGIC[0]: ! FFI2_SRVAL bit 0 ILOGIC[0]: NUM_CE bit 0 - IODELAY[0]: ! IDELAY_VALUE_CUR bit 2 IODELAY[0]: ODELAY_VALUE bit 2 - OLOGIC[0]: ! FFO_INIT bit 0 IOB[0]: OUTPUT_ENABLE bit 1 IOB[0]: V5_LVDS bit 7 - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_ILOGIC_CLK[0] bit 0 ILOGIC[0]: ! INIT_RANK3 bit 4 SPEC_INT: mux IMUX_SPEC[1] bit 4 SPEC_INT: mux IMUX_SPEC[1] bit 1 IODELAY[0]: IDELAY_VALUE_INIT bit 0 IODELAY[0]: ODELAY_VALUE bit 3 - - IOB[0]: V5_LVDS bit 5 IOB[0]: V5_LVDS bit 6 - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_ILOGIC_CLKB[0] bit 0 ILOGIC[0]: ! FFI2_INIT bit 0 SPEC_INT: mux IMUX_SPEC[1] bit 7 ILOGIC[0]: ! FFI_LATCH IODELAY[0]: ! ENABLE bit 2 OLOGIC[0]: ! FFO_RANK1_INIT bit 0 OLOGIC[0]: invert D4 OLOGIC[0]: SERDES IOB[0]: V5_OUTPUT_MISC bit 3 IOB[0]: V5_NSLEW bit 5 - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 5 ILOGIC[0]: BITSLIP_SYNC SPEC_INT: mux IMUX_SPEC[1] bit 5 SPEC_INT: mux IMUX_SPEC[1] bit 6 IODELAY[0]: ! IDELAY_VALUE_CUR bit 3 - OLOGIC[0]: FFT_SR_SYNC OLOGIC[0]: TRISTATE_WIDTH bit 0 IOB[0]: OUTPUT_ENABLE bit 0 IOB[0]: PULL bit 2 - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: BITSLIP_ENABLE bit 0 OLOGIC[0]: MISR_ENABLE_FDBK SPEC_INT: mux IMUX_SPEC[1] bit 3 SPEC_INT: mux IMUX_IO_ICLK[0] bit 8 IODELAY[0]: ! ENABLE bit 1 OLOGIC[0]: ! FFO_RANK1_INIT bit 1 - OLOGIC[0]: V5_MUX_T bit 4 IOB[0]: V5_LVDS bit 4 IOB[0]: IBUF_MODE bit 0 - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_CLK_SELECT bit 0 ILOGIC[0]: ! INIT_RANK2 bit 4 ILOGIC[0]: FFI_TSBYPASS_ENABLE ILOGIC[0]: FFI_DELAY_ENABLE IODELAY[0]: IDELAY_VALUE_INIT bit 4 IODELAY[0]: ODELAY_VALUE bit 4 OLOGIC[0]: V5_MUX_T bit 2 OLOGIC[0]: V5_MUX_T bit 1 IOB[0]: V5_LVDS bit 3 IOB[0]: V5_PSLEW bit 0 - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_ENABLE OLOGIC[0]: MISR_CLK_SELECT bit 1 ILOGIC[0]: MUX_TSBYPASS bit 0 ILOGIC[0]: BITSLIP_ENABLE bit 6 IODELAY[0]: ! IDELAY_VALUE_CUR bit 4 IODELAY[0]: ! ENABLE bit 3 OLOGIC[0]: V5_MUX_T bit 3 OLOGIC[0]: ! FFT_RANK1_INIT bit 0 IOB[0]: PULL bit 0 IOB[0]: DCI_MISC bit 0 - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC[0]: MISR_RESET ILOGIC[0]: BITSLIP_ENABLE bit 3 SPEC_INT: mux IMUX_SPEC[0] bit 8 ILOGIC[0]: SERDES_MODE bit 0 OLOGIC[0]: ! FFO_RANK1_INIT bit 2 IODELAY[0]: ODELAY_VALUE bit 1 OLOGIC[0]: FFT_REV_ENABLE OLOGIC[0]: FFT_SR_ENABLE IOB[0]: PULL bit 1 IOB[0]: V5_LVDS bit 2 - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 3 ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 4 ILOGIC[0]: OCLK2_INV SPEC_INT: mux IMUX_IO_ICLK[0] bit 6 IODELAY[0]: HIGH_PERFORMANCE_MODE - - - IOB[0]: ! V4_PDRIVE bit 0 IOB[0]: ! V4_NDRIVE bit 2 - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_CE bit 0 ILOGIC[0]: READBACK_I bit 0 SPEC_INT: mux IMUX_SPEC[0] bit 3 SPEC_INT: mux IMUX_SPEC[1] bit 0 OLOGIC[0]: ! FFO_RANK1_INIT bit 3 IODELAY[0]: ODELAY_VALUE bit 5 OLOGIC[0]: invert CLKDIV OLOGIC[0]: ! FFO_RANK2_INIT bit 0 IOB[0]: V5_LVDS bit 1 IOB[0]: V4_PDRIVE bit 2 - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_CE bit 1 ILOGIC[0]: BITSLIP_ENABLE bit 2 ILOGIC[0]: OCLK1_INV SPEC_INT: mux IMUX_SPEC[0] bit 4 IODELAY[0]: ! IDELAY_VALUE_CUR bit 5 - OLOGIC[0]: FFO_RANK2_SR_SYNC OLOGIC[0]: ! FFT_SRVAL bit 0 IOB[0]: DCI_T - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 2 ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 3 SPEC_INT: mux IMUX_SPEC[0] bit 0 SPEC_INT: mux IMUX_IO_ICLK[0] bit 5 - OLOGIC[0]: ! FFO_RANK1_INIT bit 4 OLOGIC[0]: ! FFO_RANK2_INIT bit 1 OLOGIC[0]: V5_MUX_T bit 0 IOB[0]: V4_NDRIVE bit 4 IOB[0]: V5_LVDS bit 0 - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 3 - SPEC_INT: mux IMUX_SPEC[0] bit 6 SPEC_INT: mux IMUX_SPEC[0] bit 2 IODELAY[0]: IDELAY_VALUE_INIT bit 2 - OLOGIC[0]: ! FFT_SRVAL bit 2 OLOGIC[0]: ! FFT_SRVAL bit 1 IOB[0]: ! V4_NDRIVE bit 0 IOB[0]: V4_PDRIVE bit 4 - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux IMUX_SPEC[0] bit 7 SPEC_INT: mux IMUX_SPEC[0] bit 5 - IODELAY[0]: ! LEGIDELAY - - - IOB[0]: ! V4_PDRIVE bit 3 - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 2 ILOGIC[0]: ! INIT_BITSLIPCNT bit 0 IODELAY[0]: !invert DATAIN ILOGIC[0]: DATA_WIDTH bit 2 IODELAY[0]: ! ENABLE bit 0 OLOGIC[0]: ! FFO_RANK1_INIT bit 5 OLOGIC[0]: ! FFT_INIT bit 0 - IOB[0]: DCI_MODE bit 1 IOB[0]: DCI_MODE bit 2 - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 2 SPEC_INT: mux IMUX_SPEC[0] bit 1 ILOGIC[0]: DATA_WIDTH bit 1 IODELAY[0]: ODELAY_VALUE bit 0 IODELAY[0]: IDELAY_TYPE bit 0 OLOGIC[0]: ! FFT_RANK1_INIT bit 1 - IOB[0]: OUTPUT_DELAY IOB[0]: DCI_MODE bit 0 - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: invert CLKDIV - SPEC_INT: mux IMUX_IO_ICLK[0] bit 7 ILOGIC[0]: DATA_RATE bit 0 - IODELAY[0]: IDELAY_VALUE_INIT bit 3 OLOGIC[0]: V5_MUX_O bit 2 OLOGIC[0]: ! FFO_RANK2_INIT bit 2 IOB[0]: V4_NDRIVE bit 3 - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 1 ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 1 ILOGIC[0]: DATA_WIDTH bit 0 ILOGIC[0]: DATA_WIDTH bit 3 IODELAY[0]: IDELAY_VALUE_INIT bit 1 IODELAY[0]: IDELAY_TYPE bit 1 OLOGIC[0]: SERDES_MODE bit 0 OLOGIC[0]: V5_MUX_O bit 1 IOB[0]: V5_LVDS bit 8 IOB[0]: ! DCIUPDATEMODE_ASREQUIRED - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_BITSLIPCNT bit 1 - SPEC_INT: mux IMUX_IO_ICLK[0] bit 1 SPEC_INT: mux IMUX_IO_ICLK[0] bit 2 - - - OLOGIC[0]: ! FFT_RANK1_INIT bit 2 IOB[0]: V5_OUTPUT_MISC bit 4 - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK2 bit 0 SPEC_INT: mux IMUX_IO_ICLK[0] bit 3 IODELAY[0]: DELAY_SRC bit 2 IODELAY[0]: IDELAY_VALUE_INIT bit 5 OLOGIC[0]: !invert T2 - - IOB[0]: VR IOB[0]: V5_OUTPUT_MISC bit 5 - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_BITSLIPCNT bit 2 - SPEC_INT: mux IMUX_IO_ICLK[0] bit 4 IODELAY[0]: DELAYCHAIN_OSC OLOGIC[0]: !invert T1 - OLOGIC[0]: ! FFO_RANK2_INIT bit 3 - - IOB[0]: ! V4_NDRIVE bit 1 - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 0 ILOGIC[0]: ! INIT_RANK3 bit 1 IODELAY[0]: DELAY_SRC bit 1 SPEC_INT: mux IMUX_IO_ICLK[0] bit 0 OLOGIC[0]: FFT_RANK1_SR_SYNC - - OLOGIC[0]: ! FFT_RANK1_INIT bit 3 - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC[0]: ! INIT_RANK3 bit 0 - IODELAY[0]: DELAY_SRC bit 0 IODELAY[0]: DELAY_SRC bit 3 - OLOGIC[0]: FFO_RANK1_SR_SYNC OLOGIC[0]: !invert T3 OLOGIC[0]: !invert T4 - IOB[0]: V4_PDRIVE bit 1 - - - - - - - - - - - - - - - -

Tables

Device data iodelay-default

virtex5 device data iodelay-default
Device IODELAY_V5_IDELAY_DEFAULT
xc5vlx30 0b100111
xc5vlx50 0b100111
xc5vlx85 0b101100
xq5vlx85 0b101100
xc5vlx110 0b101100
xq5vlx110 0b101100
xc5vlx155 0b110010
xc5vlx220 0b111000
xc5vlx330 0b111000
xc5vlx20t 0b100111
xc5vlx30t 0b100111
xq5vlx30t 0b100111
xc5vlx50t 0b100111
xc5vlx85t 0b101100
xc5vlx110t 0b101100
xq5vlx110t 0b101100
xc5vlx155t 0b110010
xq5vlx155t 0b110010
xc5vlx220t 0b111000
xq5vlx220t 0b111000
xc5vlx330t 0b111000
xq5vlx330t 0b111000
xc5vsx35t 0b100111
xc5vsx50t 0b101011
xq5vsx50t 0b101011
xc5vsx95t 0b110010
xq5vsx95t 0b110010
xc5vsx240t 0b111000
xq5vsx240t 0b111000
xc5vfx30t 0b100111
xc5vfx70t 0b101100
xq5vfx70t 0b101100
xc5vfx100t 0b110010
xq5vfx100t 0b110010
xc5vfx130t 0b110111
xq5vfx130t 0b110111
xc5vfx200t 0b111000
xq5vfx200t 0b111000
xc5vtx150t 0b110111
xc5vtx240t 0b111000

Table IOB_DATA

virtex5 table IOB_DATA
Row PDRIVE NDRIVE OUTPUT_MISC PSLEW_FAST NSLEW_FAST PSLEW_SLOW NSLEW_SLOW PMASK_TERM_VCC PMASK_TERM_SPLIT NMASK_TERM_SPLIT LVDIV2
OFF 0b00000 0b00000 0b000000 0b000000 0b000000 - - 0b00000 0b00000 0b00000 0b000
VREF 0b00000 0b00000 - 0b000000 0b000000 - - - - - -
VR 0b00000 0b00000 - 0b111111 0b111111 - - - - - -
LVCMOS12_2 0b00111 0b00010 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS12_4 0b01110 0b00100 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS12_6 0b10011 0b00101 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS12_8 0b11010 0b01001 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_2 0b00110 0b00010 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_4 0b01000 0b00011 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_6 0b01001 0b00100 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_8 0b01101 0b00101 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_12 0b10110 0b01000 0b111000 0b111111 0b000111 0b000101 0b000000 - - - -
LVCMOS15_16 0b11100 0b01010 0b111000 0b111111 0b001010 0b000101 0b000000 - - - -
LVCMOS18_2 0b00011 0b00001 0b100000 0b011111 0b111111 0b000001 0b000011 - - - -
LVCMOS18_4 0b00101 0b00010 0b100000 0b111111 0b111000 0b000001 0b000101 - - - -
LVCMOS18_6 0b00111 0b00011 0b100000 0b111111 0b001111 0b000001 0b000001 - - - -
LVCMOS18_8 0b01000 0b00100 0b100000 0b111111 0b001111 0b000001 0b000001 - - - -
LVCMOS18_12 0b01101 0b00110 0b100000 0b111111 0b010011 0b000001 0b000001 - - - -
LVCMOS18_16 0b10011 0b01001 0b100000 0b111111 0b001111 0b000001 0b000000 - - - -
LVCMOS25_2 0b00011 0b00010 0b000000 0b011111 0b001111 0b000000 0b001010 - - - -
LVCMOS25_4 0b00101 0b00011 0b000000 0b111111 0b101000 0b000001 0b000011 - - - -
LVCMOS25_6 0b00110 0b00100 0b000000 0b111111 0b100000 0b000001 0b000010 - - - -
LVCMOS25_8 0b00111 0b00101 0b000000 0b111111 0b010001 0b000001 0b000010 - - - -
LVCMOS25_12 0b01001 0b00111 0b000000 0b111111 0b100000 0b000000 0b000000 - - - -
LVCMOS25_16 0b01110 0b01010 0b000000 0b111111 0b100000 0b000001 0b000010 - - - -
LVCMOS25_24 0b10101 0b01111 0b000000 0b111111 0b100000 0b000001 0b000000 - - - -
LVCMOS33_2 0b00010 0b00010 0b000000 0b111111 0b111111 0b000001 0b000100 - - - -
LVCMOS33_4 0b00011 0b00011 0b000000 0b111111 0b111111 0b000001 0b000101 - - - -
LVCMOS33_6 0b00100 0b00100 0b000000 0b111111 0b100000 0b000001 0b000010 - - - -
LVCMOS33_8 0b00110 0b00101 0b000000 0b011111 0b111111 0b000001 0b000100 - - - -
LVCMOS33_12 0b01000 0b01000 0b000000 0b111111 0b111111 0b000001 0b000011 - - - -
LVCMOS33_16 0b01010 0b01010 0b000000 0b111111 0b111111 0b000001 0b000011 - - - -
LVCMOS33_24 0b10001 0b10000 0b000000 0b111111 0b111111 0b000001 0b000001 - - - -
LVTTL_2 0b00010 0b00010 0b000000 0b111111 0b111111 0b000001 0b000100 - - - -
LVTTL_4 0b00011 0b00011 0b000000 0b111111 0b111111 0b000001 0b000101 - - - -
LVTTL_6 0b00100 0b00100 0b000000 0b111111 0b100000 0b000001 0b000010 - - - -
LVTTL_8 0b00110 0b00101 0b000000 0b011111 0b111111 0b000001 0b000100 - - - -
LVTTL_12 0b01000 0b01000 0b000000 0b111111 0b111111 0b000001 0b000011 - - - -
LVTTL_16 0b01010 0b01010 0b000000 0b111111 0b111111 0b000001 0b000011 - - - -
LVTTL_24 0b10001 0b10000 0b000000 0b111111 0b111111 0b000001 0b000001 - - - -
PCI33_3 0b01010 0b01101 0b000000 0b000000 0b000000 - - - - - -
PCI66_3 0b01010 0b01101 0b000000 0b000000 0b000000 - - - - - -
PCIX 0b01100 0b01100 0b000000 0b001111 0b100000 - - - - - -
LVDCI_15 - - 0b100000 0b111111 0b000010 - - - - - -
LVDCI_18 - - 0b100000 0b111111 0b000000 - - - - - -
LVDCI_25 - - 0b000000 0b111111 0b001111 - - - - - -
LVDCI_33 - - 0b000000 0b111111 0b111111 - - - - - -
LVDCI_DV2_15 - - 0b100000 0b111111 0b000011 - - - - - 0b000
LVDCI_DV2_18 - - 0b100000 0b111111 0b000111 - - - - - 0b010
LVDCI_DV2_25 - - 0b000000 0b111111 0b011101 - - - - - 0b101
HSLVDCI_15 - - 0b100000 0b111111 0b000010 - - - - - -
HSLVDCI_18 - - 0b100000 0b111111 0b000000 - - - - - -
HSLVDCI_25 - - 0b000000 0b111111 0b001111 - - - - - -
HSLVDCI_33 - - 0b000000 0b111111 0b111111 - - - - - -
HSUL_12_DCI - - - - - - - - - - -
GTL 0b00000 0b10011 0b000000 0b000000 0b010101 - - - - - -
GTLP 0b00000 0b10000 0b000000 0b000000 0b010101 - - - - - -
SSTL12 - - - - - - - - - - -
SSTL135 - - - - - - - - - - -
SSTL15 - - - - - - - - - - -
SSTL18_I 0b01000 0b00100 0b100000 0b111111 0b010011 - - - - - -
SSTL18_II 0b11000 0b01100 0b100000 0b111111 0b001111 - - - - - -
SSTL2_I 0b00110 0b00100 0b000000 0b111111 0b010011 - - - - - -
SSTL2_II 0b10011 0b01101 0b000000 0b111111 0b001111 - - - - - -
HSUL_12 - - - - - - - - - - -
HSTL_I_12 0b11010 0b00110 0b111000 0b111111 0b001010 - - - - - -
HSTL_I 0b01101 0b00101 0b110000 0b111111 0b001101 - - - - - -
HSTL_II 0b11010 0b01010 0b110000 0b111111 0b001010 - - - - - -
HSTL_III 0b01101 0b01111 0b110000 0b111111 0b010000 - - - - - -
HSTL_IV 0b01101 0b11110 0b100000 0b111111 0b010010 - - - - - -
HSTL_I_18 0b01110 0b00111 0b100000 0b111111 0b001111 - - - - - -
HSTL_II_18 0b11011 0b01101 0b100000 0b111111 0b010010 - - - - - -
HSTL_III_18 0b01110 0b10010 0b100000 0b111111 0b010000 - - - - - -
HSTL_IV_18 0b01110 0b11111 0b100000 0b111111 0b011000 - - - - - -
GTL_DCI 0b00000 0b10011 0b100001 0b000000 0b111111 - - 0b00000 - - -
GTLP_DCI 0b00000 0b10000 0b100000 0b000000 0b111111 - - 0b00000 - - -
SSTL12_DCI - - - - - - - - - - -
SSTL12_T_DCI - - - - - - - - - - -
SSTL135_DCI - - - - - - - - - - -
SSTL135_T_DCI - - - - - - - - - - -
SSTL15_DCI - - - - - - - - - - -
SSTL15_T_DCI - - - - - - - - - - -
SSTL18_I_DCI 0b00111 0b00011 0b100000 0b001111 0b110000 - - - 0b00000 0b00000 -
SSTL18_II_DCI 0b01110 0b00110 0b100000 0b111111 0b111111 - - - 0b01100 0b01100 -
SSTL18_II_T_DCI 0b00111 0b00011 0b100000 0b001111 0b110000 - - - 0b01100 0b01000 -
SSTL2_I_DCI 0b00101 0b00011 0b000000 0b111111 0b010101 - - - 0b00000 0b00000 -
SSTL2_II_DCI 0b01000 0b00110 0b000000 0b111011 0b001101 - - - 0b00000 0b01100 -
SSTL2_II_T_DCI 0b00101 0b00011 0b000000 0b111111 0b010101 - - - 0b00100 0b01000 -
HSTL_I_DCI 0b01101 0b00101 0b100000 0b011111 0b001010 - - - 0b00000 0b00000 -
HSTL_II_DCI 0b11010 0b01010 0b100000 0b101110 0b001001 - - - 0b01001 0b01010 -
HSTL_II_T_DCI 0b01101 0b00101 0b100000 0b011111 0b001010 - - - 0b00100 0b00100 -
HSTL_III_DCI 0b01101 0b01111 0b100000 0b000110 0b110001 - - 0b00000 - - -
HSTL_IV_DCI 0b01101 0b11110 0b100000 0b000000 0b111101 - - 0b00100 - - -
HSTL_I_DCI_18 0b01110 0b00111 0b100000 0b011111 0b101110 - - - 0b00000 0b00000 -
HSTL_II_DCI_18 0b11011 0b01101 0b100000 0b101110 0b101101 - - - 0b01001 0b00110 -
HSTL_II_T_DCI_18 0b01110 0b00111 0b100000 0b011111 0b101110 - - - 0b01100 0b01100 -
HSTL_III_DCI_18 0b01110 0b10010 0b100000 0b000100 0b011001 - - 0b00000 - - -
HSTL_IV_DCI_18 0b01110 0b11111 0b100010 0b001111 0b111111 - - 0b01100 - - -
BLVDS_25 0b11111 0b10111 0b011000 0b111111 0b101111 - - - - - -
LVPECL_25 0b11000 0b11110 0b011000 0b111111 0b001111 - - - - - -
LVDS_25_DCI - - - - - - - - - - -
LVDSEXT_25_DCI - - - - - - - - - - -

Table LVDS_DATA

virtex5 table LVDS_DATA
Row OUTPUT_T OUTPUT_C TERM_T TERM_C LVDSBIAS
OFF 0b000000000 0b000000000 - - 0b000000000000
LVDS_25 0b100000000 0b001100011 0b000000000 0b101100011 0b000000001000
LVDSEXT_25 0b110000000 0b001000101 0b000000000 0b101100011 0b000000001000
RSDS_25 0b100000000 0b001100011 0b000000000 0b101100011 0b000000001000
HT_25 0b101000000 0b001100011 0b000000000 0b101100011 0b000000001000