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Configuration registers

TODO: document

Tile GLOBAL

Cells: 0

Bels GLOBAL

virtex5 GLOBAL bel GLOBAL pins
PinDirectionGLOBAL
virtex5 GLOBAL bel GLOBAL attribute bits
AttributeGLOBAL
GWE_CYCLE[enum: STARTUP_CYCLE]
GTS_CYCLE[enum: STARTUP_CYCLE]
LOCK_CYCLE[enum: STARTUP_CYCLE]
MATCH_CYCLE[enum: STARTUP_CYCLE]
DONE_CYCLE[enum: STARTUP_CYCLE]
STARTUP_CLOCK[enum: STARTUP_CLOCK]
CONFIG_RATE_V5[enum: CONFIG_RATE_V5]
CAPTURE_ONESHOTCOR0[0][23]
DRIVE_DONECOR0[0][24]
DONE_PIPECOR0[0][25]
CRC_ENABLE!COR0[0][28]
BPI_PAGE_SIZE[enum: BPI_PAGE_SIZE]
BPI_1ST_READ_CYCLE[enum: BPI_1ST_READ_CYCLE]
POST_CRC_ENCOR1[0][8]
POST_CRC_NO_PINCOR1[0][9]
POST_CRC_RECONFIGCOR1[0][23]
RETAIN_CONFIG_STATUS!COR1[0][25]
POST_CRC_SEL bit 0COR1[0][7]
PERSIST_DEASSERT_AT_DESYNCHCOR1[0][17]
GTS_USR_BCTL0[0][0]
PERSISTCTL0[0][3]
SECURITY[enum: SECURITY]
ENCRYPTCTL0[0][6]
GLUTMASK!CTL0[0][8]
ICAP_SELECT[enum: ICAP_SELECT]
CONFIG_FALLBACK!CTL0[0][10]
ENCRYPT_KEY_SELECT[enum: ENCRYPT_KEY_SELECT]
OVERTEMP_POWERDOWNCTL0[0][12]
SELECTMAP_ABORT!CTL0[0][9]
VGG_SEL bit 0CTL0[0][13]
VGG_SEL bit 1CTL0[0][14]
VGG_SEL bit 2CTL0[0][15]
VGG_SEL bit 3CTL0[0][16]
VGG_SEL bit 4CTL0[0][17]
VBG_DLL_SEL bit 0CTL0[0][18]
VBG_DLL_SEL bit 1CTL0[0][19]
VBG_DLL_SEL bit 2CTL0[0][20]
VBG_DLL_SEL bit 3CTL0[0][21]
VBG_DLL_SEL bit 4CTL0[0][22]
V5_VBG_SEL bit 0CTL0[0][23]
V5_VBG_SEL bit 1CTL0[0][24]
V5_VBG_SEL bit 2CTL0[0][25]
V5_VBG_SEL bit 3CTL0[0][26]
V5_VBG_SEL bit 4CTL0[0][27]
TIMER bit 0TIMER[0][0]
TIMER bit 1TIMER[0][1]
TIMER bit 2TIMER[0][2]
TIMER bit 3TIMER[0][3]
TIMER bit 4TIMER[0][4]
TIMER bit 5TIMER[0][5]
TIMER bit 6TIMER[0][6]
TIMER bit 7TIMER[0][7]
TIMER bit 8TIMER[0][8]
TIMER bit 9TIMER[0][9]
TIMER bit 10TIMER[0][10]
TIMER bit 11TIMER[0][11]
TIMER bit 12TIMER[0][12]
TIMER bit 13TIMER[0][13]
TIMER bit 14TIMER[0][14]
TIMER bit 15TIMER[0][15]
TIMER bit 16TIMER[0][16]
TIMER bit 17TIMER[0][17]
TIMER bit 18TIMER[0][18]
TIMER bit 19TIMER[0][19]
TIMER bit 20TIMER[0][20]
TIMER bit 21TIMER[0][21]
TIMER bit 22TIMER[0][22]
TIMER bit 23TIMER[0][23]
TIMER_CFGTIMER[0][24]
TIMER_USRTIMER[0][25]
V5_NEXT_CONFIG_ADDR bit 0WBSTAR[0][0]
V5_NEXT_CONFIG_ADDR bit 1WBSTAR[0][1]
V5_NEXT_CONFIG_ADDR bit 2WBSTAR[0][2]
V5_NEXT_CONFIG_ADDR bit 3WBSTAR[0][3]
V5_NEXT_CONFIG_ADDR bit 4WBSTAR[0][4]
V5_NEXT_CONFIG_ADDR bit 5WBSTAR[0][5]
V5_NEXT_CONFIG_ADDR bit 6WBSTAR[0][6]
V5_NEXT_CONFIG_ADDR bit 7WBSTAR[0][7]
V5_NEXT_CONFIG_ADDR bit 8WBSTAR[0][8]
V5_NEXT_CONFIG_ADDR bit 9WBSTAR[0][9]
V5_NEXT_CONFIG_ADDR bit 10WBSTAR[0][10]
V5_NEXT_CONFIG_ADDR bit 11WBSTAR[0][11]
V5_NEXT_CONFIG_ADDR bit 12WBSTAR[0][12]
V5_NEXT_CONFIG_ADDR bit 13WBSTAR[0][13]
V5_NEXT_CONFIG_ADDR bit 14WBSTAR[0][14]
V5_NEXT_CONFIG_ADDR bit 15WBSTAR[0][15]
V5_NEXT_CONFIG_ADDR bit 16WBSTAR[0][16]
V5_NEXT_CONFIG_ADDR bit 17WBSTAR[0][17]
V5_NEXT_CONFIG_ADDR bit 18WBSTAR[0][18]
V5_NEXT_CONFIG_ADDR bit 19WBSTAR[0][19]
V5_NEXT_CONFIG_ADDR bit 20WBSTAR[0][20]
V5_NEXT_CONFIG_ADDR bit 21WBSTAR[0][21]
V5_NEXT_CONFIG_ADDR bit 22WBSTAR[0][22]
V5_NEXT_CONFIG_ADDR bit 23WBSTAR[0][23]
V5_NEXT_CONFIG_ADDR bit 24WBSTAR[0][24]
V5_NEXT_CONFIG_ADDR bit 25WBSTAR[0][25]
REVISION_SELECT_TRISTATE!WBSTAR[0][26]
REVISION_SELECT bit 0WBSTAR[0][27]
REVISION_SELECT bit 1WBSTAR[0][28]
DD_OVERRIDETESTMODE[0][14]
virtex5 GLOBAL enum STARTUP_CYCLE
GLOBAL.GWE_CYCLECOR0[0][2]COR0[0][1]COR0[0][0]
GLOBAL.GTS_CYCLECOR0[0][5]COR0[0][4]COR0[0][3]
_1000
_2001
_3010
_4011
_5100
_6101
DONE110
KEEP111
virtex5 GLOBAL enum STARTUP_CYCLE
GLOBAL.LOCK_CYCLECOR0[0][8]COR0[0][7]COR0[0][6]
GLOBAL.MATCH_CYCLECOR0[0][11]COR0[0][10]COR0[0][9]
_0000
_1001
_2010
_3011
_4100
_5101
_6110
NOWAIT111
virtex5 GLOBAL enum STARTUP_CYCLE
GLOBAL.DONE_CYCLECOR0[0][14]COR0[0][13]COR0[0][12]
_1000
_2001
_3010
_4011
_5100
_6101
KEEP111
virtex5 GLOBAL enum STARTUP_CLOCK
GLOBAL.STARTUP_CLOCKCOR0[0][16]COR0[0][15]
CCLK00
USERCLK01
JTAGCLK10
virtex5 GLOBAL enum CONFIG_RATE_V5
GLOBAL.CONFIG_RATE_V5COR0[0][22]COR0[0][21]COR0[0][20]COR0[0][19]COR0[0][18]COR0[0][17]
_2000000
_6000001
_9000010
_13000100
_17000101
_20000110
_24001001
_27001010
_31001100
_35001110
_38010110
_42010111
_46100011
_49011001
_53011011
_56100100
_60011101
virtex5 GLOBAL enum BPI_PAGE_SIZE
GLOBAL.BPI_PAGE_SIZECOR1[0][1]COR1[0][0]
_100
_401
_810
virtex5 GLOBAL enum BPI_1ST_READ_CYCLE
GLOBAL.BPI_1ST_READ_CYCLECOR1[0][3]COR1[0][2]
_100
_201
_310
_411
virtex5 GLOBAL enum SECURITY
GLOBAL.SECURITYCTL0[0][5]CTL0[0][4]
NONE00
LEVEL101
LEVEL210
virtex5 GLOBAL enum ICAP_SELECT
GLOBAL.ICAP_SELECTCTL0[0][30]
BOTTOM1
TOP0
virtex5 GLOBAL enum ENCRYPT_KEY_SELECT
GLOBAL.ENCRYPT_KEY_SELECTCTL0[0][31]
BBRAM0
EFUSE1

Bitstream

virtex5 GLOBAL rect COR1
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - GLOBAL: ! RETAIN_CONFIG_STATUS - GLOBAL: POST_CRC_RECONFIG - - - - - GLOBAL: PERSIST_DEASSERT_AT_DESYNCH - - - - - - - GLOBAL: POST_CRC_NO_PIN GLOBAL: POST_CRC_EN GLOBAL: POST_CRC_SEL bit 0 - - - GLOBAL: BPI_1ST_READ_CYCLE bit 1 GLOBAL: BPI_1ST_READ_CYCLE bit 0 GLOBAL: BPI_PAGE_SIZE bit 1 GLOBAL: BPI_PAGE_SIZE bit 0
virtex5 GLOBAL rect CTL1
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex5 GLOBAL rect TESTMODE
FrameBit
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
F0 - - - - - - - - - - - - - - - - - GLOBAL: DD_OVERRIDE - - - - - - - - - - - - - -