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Configuration registers

TODO: document

COR

virtex5 REG.COR rect R0
BitFrame
F0
B0 STARTUP:GWE_CYCLE[0]
B1 STARTUP:GWE_CYCLE[1]
B2 STARTUP:GWE_CYCLE[2]
B3 STARTUP:GTS_CYCLE[0]
B4 STARTUP:GTS_CYCLE[1]
B5 STARTUP:GTS_CYCLE[2]
B6 STARTUP:LCK_CYCLE[0]
B7 STARTUP:LCK_CYCLE[1]
B8 STARTUP:LCK_CYCLE[2]
B9 STARTUP:MATCH_CYCLE[0]
B10 STARTUP:MATCH_CYCLE[1]
B11 STARTUP:MATCH_CYCLE[2]
B12 STARTUP:DONE_CYCLE[0]
B13 STARTUP:DONE_CYCLE[1]
B14 STARTUP:DONE_CYCLE[2]
B15 STARTUP:STARTUPCLK[0]
B16 STARTUP:STARTUPCLK[1]
B17 STARTUP:CONFIG_RATE[0]
B18 STARTUP:CONFIG_RATE[1]
B19 STARTUP:CONFIG_RATE[2]
B20 STARTUP:CONFIG_RATE[3]
B21 STARTUP:CONFIG_RATE[4]
B22 STARTUP:CONFIG_RATE[5]
B23 CAPTURE:ONESHOT
B24 STARTUP:DRIVE_DONE
B25 STARTUP:DONE_PIPE
B26 -
B27 -
B28 ~STARTUP:CRC
CAPTURE:ONESHOT 0.F0.B23
STARTUP:DONE_PIPE 0.F0.B25
STARTUP:DRIVE_DONE 0.F0.B24
non-inverted [0]
STARTUP:CONFIG_RATE 0.F0.B22 0.F0.B21 0.F0.B20 0.F0.B19 0.F0.B18 0.F0.B17
2 0 0 0 0 0 0
6 0 0 0 0 0 1
9 0 0 0 0 1 0
13 0 0 0 1 0 0
17 0 0 0 1 0 1
20 0 0 0 1 1 0
24 0 0 1 0 0 1
27 0 0 1 0 1 0
31 0 0 1 1 0 0
35 0 0 1 1 1 0
38 0 1 0 1 1 0
42 0 1 0 1 1 1
49 0 1 1 0 0 1
53 0 1 1 0 1 1
60 0 1 1 1 0 1
46 1 0 0 0 1 1
56 1 0 0 1 0 0
STARTUP:CRC 0.F0.B28
inverted ~[0]
STARTUP:DONE_CYCLE 0.F0.B14 0.F0.B13 0.F0.B12
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
KEEP 1 1 1
STARTUP:GTS_CYCLE 0.F0.B5 0.F0.B4 0.F0.B3
STARTUP:GWE_CYCLE 0.F0.B2 0.F0.B1 0.F0.B0
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
DONE 1 1 0
KEEP 1 1 1
STARTUP:LCK_CYCLE 0.F0.B8 0.F0.B7 0.F0.B6
STARTUP:MATCH_CYCLE 0.F0.B11 0.F0.B10 0.F0.B9
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
NOWAIT 1 1 1
STARTUP:STARTUPCLK 0.F0.B16 0.F0.B15
CCLK 0 0
USERCLK 0 1
JTAGCLK 1 0

COR1

virtex5 REG.COR1 rect R0
BitFrame
F0
B0 MISC:BPI_PAGE_SIZE[0]
B1 MISC:BPI_PAGE_SIZE[1]
B2 MISC:BPI_1ST_READ_CYCLE[0]
B3 MISC:BPI_1ST_READ_CYCLE[1]
B4 -
B5 -
B6 -
B7 MISC:POST_CRC_SEL
B8 MISC:POST_CRC_EN
B9 MISC:POST_CRC_NO_PIN
B10 -
B11 -
B12 -
B13 -
B14 -
B15 -
B16 -
B17 -
B18 -
B19 -
B20 -
B21 -
B22 -
B23 MISC:POST_CRC_RECONFIG
B24 -
B25 ~MISC:RETAIN_CONFIG_STATUS
MISC:BPI_1ST_READ_CYCLE 0.F0.B3 0.F0.B2
1 0 0
2 0 1
3 1 0
4 1 1
MISC:BPI_PAGE_SIZE 0.F0.B1 0.F0.B0
1 0 0
4 0 1
8 1 0
MISC:POST_CRC_EN 0.F0.B8
MISC:POST_CRC_NO_PIN 0.F0.B9
MISC:POST_CRC_RECONFIG 0.F0.B23
MISC:POST_CRC_SEL 0.F0.B7
non-inverted [0]
MISC:RETAIN_CONFIG_STATUS 0.F0.B25
inverted ~[0]

CTL

virtex5 REG.CTL rect R0
BitFrame
F0
B0 MISC:GTS_USR_B
B1 -
B2 -
B3 MISC:PERSIST
B4 MISC:SECURITY[0]
B5 MISC:SECURITY[1]
B6 MISC:ENCRYPT
B7 -
B8 ~MISC:GLUTMASK
B9 ~MISC:SELECTMAP_ABORT
B10 ~MISC:CONFIG_FALLBACK
B11 -
B12 MISC:OVERTEMP_POWERDOWN
B13 MISC:VGG_SEL[0]
B14 MISC:VGG_SEL[1]
B15 MISC:VGG_SEL[2]
B16 MISC:VGG_SEL[3]
B17 MISC:VGG_SEL[4]
B18 MISC:VBG_DLL_SEL[0]
B19 MISC:VBG_DLL_SEL[1]
B20 MISC:VBG_DLL_SEL[2]
B21 MISC:VBG_DLL_SEL[3]
B22 MISC:VBG_DLL_SEL[4]
B23 MISC:VBG_SEL[0]
B24 MISC:VBG_SEL[1]
B25 MISC:VBG_SEL[2]
B26 MISC:VBG_SEL[3]
B27 MISC:VBG_SEL[4]
B28 -
B29 -
B30 MISC:ICAP_SELECT[0]
B31 MISC:ENCRYPT_KEY_SELECT[0]
MISC:CONFIG_FALLBACK 0.F0.B10
MISC:GLUTMASK 0.F0.B8
MISC:SELECTMAP_ABORT 0.F0.B9
inverted ~[0]
MISC:ENCRYPT 0.F0.B6
MISC:GTS_USR_B 0.F0.B0
MISC:OVERTEMP_POWERDOWN 0.F0.B12
MISC:PERSIST 0.F0.B3
non-inverted [0]
MISC:ENCRYPT_KEY_SELECT 0.F0.B31
BBRAM 0
EFUSE 1
MISC:ICAP_SELECT 0.F0.B30
TOP 0
BOTTOM 1
MISC:SECURITY 0.F0.B5 0.F0.B4
NONE 0 0
LEVEL1 0 1
LEVEL2 1 0
MISC:VBG_DLL_SEL 0.F0.B22 0.F0.B21 0.F0.B20 0.F0.B19 0.F0.B18
MISC:VBG_SEL 0.F0.B27 0.F0.B26 0.F0.B25 0.F0.B24 0.F0.B23
MISC:VGG_SEL 0.F0.B17 0.F0.B16 0.F0.B15 0.F0.B14 0.F0.B13
non-inverted [4] [3] [2] [1] [0]

TIMER

virtex5 REG.TIMER rect R0
BitFrame
F0
B0 MISC:TIMER[0]
B1 MISC:TIMER[1]
B2 MISC:TIMER[2]
B3 MISC:TIMER[3]
B4 MISC:TIMER[4]
B5 MISC:TIMER[5]
B6 MISC:TIMER[6]
B7 MISC:TIMER[7]
B8 MISC:TIMER[8]
B9 MISC:TIMER[9]
B10 MISC:TIMER[10]
B11 MISC:TIMER[11]
B12 MISC:TIMER[12]
B13 MISC:TIMER[13]
B14 MISC:TIMER[14]
B15 MISC:TIMER[15]
B16 MISC:TIMER[16]
B17 MISC:TIMER[17]
B18 MISC:TIMER[18]
B19 MISC:TIMER[19]
B20 MISC:TIMER[20]
B21 MISC:TIMER[21]
B22 MISC:TIMER[22]
B23 MISC:TIMER[23]
B24 MISC:TIMER_CFG
B25 MISC:TIMER_USR
MISC:TIMER 0.F0.B23 0.F0.B22 0.F0.B21 0.F0.B20 0.F0.B19 0.F0.B18 0.F0.B17 0.F0.B16 0.F0.B15 0.F0.B14 0.F0.B13 0.F0.B12 0.F0.B11 0.F0.B10 0.F0.B9 0.F0.B8 0.F0.B7 0.F0.B6 0.F0.B5 0.F0.B4 0.F0.B3 0.F0.B2 0.F0.B1 0.F0.B0
non-inverted [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
MISC:TIMER_CFG 0.F0.B24
MISC:TIMER_USR 0.F0.B25
non-inverted [0]

TESTMODE

virtex5 REG.TESTMODE rect R0
BitFrame
F0
B0 -
B1 -
B2 -
B3 -
B4 -
B5 -
B6 -
B7 -
B8 -
B9 -
B10 -
B11 -
B12 -
B13 -
B14 MISC:DD_OVERRIDE
MISC:DD_OVERRIDE 0.F0.B14
non-inverted [0]