GTX transceivers

TODO: document

Tile GTX

Cells: 20

Bels GTX_DUAL

virtex5 GTX bel GTX_DUAL pins
Pin	Direction	GTX_DUAL
DCLK	in	CELL[7].IMUX_CLK[1] invert by HCLK[19][13]
DEN	in	CELL[10].IMUX_IMUX_DELAY[39]
DWE	in	CELL[9].IMUX_IMUX_DELAY[19]
DADDR[0]	in	CELL[10].IMUX_IMUX_DELAY[32]
DADDR[1]	in	CELL[10].IMUX_IMUX_DELAY[31]
DADDR[2]	in	CELL[10].IMUX_IMUX_DELAY[24]
DADDR[3]	in	CELL[9].IMUX_IMUX_DELAY[29]
DADDR[4]	in	CELL[9].IMUX_IMUX_DELAY[28]
DADDR[5]	in	CELL[9].IMUX_IMUX_DELAY[27]
DADDR[6]	in	CELL[9].IMUX_IMUX_DELAY[26]
DI[0]	in	CELL[11].IMUX_IMUX_DELAY[3]
DI[1]	in	CELL[11].IMUX_IMUX_DELAY[2]
DI[2]	in	CELL[11].IMUX_IMUX_DELAY[1]
DI[3]	in	CELL[11].IMUX_IMUX_DELAY[0]
DI[4]	in	CELL[10].IMUX_IMUX_DELAY[3]
DI[5]	in	CELL[10].IMUX_IMUX_DELAY[2]
DI[6]	in	CELL[10].IMUX_IMUX_DELAY[1]
DI[7]	in	CELL[10].IMUX_IMUX_DELAY[0]
DI[8]	in	CELL[9].IMUX_IMUX_DELAY[45]
DI[9]	in	CELL[9].IMUX_IMUX_DELAY[44]
DI[10]	in	CELL[9].IMUX_IMUX_DELAY[43]
DI[11]	in	CELL[9].IMUX_IMUX_DELAY[42]
DI[12]	in	CELL[8].IMUX_IMUX_DELAY[47]
DI[13]	in	CELL[8].IMUX_IMUX_DELAY[46]
DI[14]	in	CELL[8].IMUX_IMUX_DELAY[45]
DI[15]	in	CELL[8].IMUX_IMUX_DELAY[44]
GREFCLK	in	CELL[12].IMUX_CLK[0]
GTXRESET	in	CELL[11].IMUX_IMUX_DELAY[36]
GTXTEST[0]	in	CELL[19].IMUX_IMUX_DELAY[27]
GTXTEST[1]	in	CELL[0].IMUX_IMUX_DELAY[13]
GTXTEST[2]	in	CELL[9].IMUX_IMUX_DELAY[16]
GTXTEST[3]	in	CELL[9].IMUX_IMUX_DELAY[17]
GTXTEST[4]	in	CELL[14].IMUX_IMUX_DELAY[22]
GTXTEST[5]	in	CELL[19].IMUX_IMUX_DELAY[28]
GTXTEST[6]	in	CELL[19].IMUX_IMUX_DELAY[6]
GTXTEST[7]	in	CELL[19].IMUX_IMUX_DELAY[29]
GTXTEST[8]	in	CELL[10].IMUX_IMUX_DELAY[40]
GTXTEST[9]	in	CELL[5].IMUX_IMUX_DELAY[13]
GTXTEST[10]	in	CELL[0].IMUX_IMUX_DELAY[12]
GTXTEST[11]	in	CELL[0].IMUX_IMUX_DELAY[11]
GTXTEST[12]	in	CELL[0].IMUX_IMUX_DELAY[14]
GTXTEST[13]	in	CELL[10].IMUX_IMUX_DELAY[33]
INTDATAWIDTH	in	CELL[10].IMUX_IMUX_DELAY[6]
PLLLKDETEN	in	CELL[9].IMUX_IMUX_DELAY[8]
PLLPOWERDOWN	in	CELL[10].IMUX_IMUX_DELAY[36]
REFCLKPWRDNB	in	CELL[9].IMUX_IMUX_DELAY[18]
PMAAMUX[0]	in	CELL[9].IMUX_IMUX_DELAY[3]
PMAAMUX[1]	in	CELL[9].IMUX_IMUX_DELAY[4]
PMAAMUX[2]	in	CELL[9].IMUX_IMUX_DELAY[5]
PMATSTCLKSEL[0]	in	CELL[10].IMUX_IMUX_DELAY[14]
PMATSTCLKSEL[1]	in	CELL[10].IMUX_IMUX_DELAY[13]
PMATSTCLKSEL[2]	in	CELL[10].IMUX_IMUX_DELAY[12]
DFECLKDLYADJ0[0]	in	CELL[14].IMUX_IMUX_DELAY[23]
DFECLKDLYADJ0[1]	in	CELL[15].IMUX_IMUX_DELAY[36]
DFECLKDLYADJ0[2]	in	CELL[15].IMUX_IMUX_DELAY[19]
DFECLKDLYADJ0[3]	in	CELL[15].IMUX_IMUX_DELAY[38]
DFECLKDLYADJ0[4]	in	CELL[15].IMUX_IMUX_DELAY[39]
DFECLKDLYADJ0[5]	in	CELL[15].IMUX_IMUX_DELAY[40]
DFETAP10[0]	in	CELL[14].IMUX_IMUX_DELAY[31]
DFETAP10[1]	in	CELL[14].IMUX_IMUX_DELAY[26]
DFETAP10[2]	in	CELL[14].IMUX_IMUX_DELAY[33]
DFETAP10[3]	in	CELL[14].IMUX_IMUX_DELAY[34]
DFETAP10[4]	in	CELL[14].IMUX_IMUX_DELAY[35]
DFETAP20[0]	in	CELL[14].IMUX_IMUX_DELAY[12]
DFETAP20[1]	in	CELL[14].IMUX_IMUX_DELAY[36]
DFETAP20[2]	in	CELL[14].IMUX_IMUX_DELAY[37]
DFETAP20[3]	in	CELL[14].IMUX_IMUX_DELAY[38]
DFETAP20[4]	in	CELL[14].IMUX_IMUX_DELAY[39]
DFETAP30[0]	in	CELL[13].IMUX_IMUX_DELAY[25]
DFETAP30[1]	in	CELL[13].IMUX_IMUX_DELAY[26]
DFETAP30[2]	in	CELL[13].IMUX_IMUX_DELAY[27]
DFETAP30[3]	in	CELL[13].IMUX_IMUX_DELAY[28]
DFETAP40[0]	in	CELL[12].IMUX_IMUX_DELAY[37]
DFETAP40[1]	in	CELL[12].IMUX_IMUX_DELAY[40]
DFETAP40[2]	in	CELL[12].IMUX_IMUX_DELAY[41]
DFETAP40[3]	in	CELL[13].IMUX_IMUX_DELAY[36]
LOOPBACK0[0]	in	CELL[12].IMUX_IMUX_DELAY[15]
LOOPBACK0[1]	in	CELL[12].IMUX_IMUX_DELAY[16]
LOOPBACK0[2]	in	CELL[12].IMUX_IMUX_DELAY[17]
PRBSCNTRESET0	in	CELL[11].IMUX_IMUX_DELAY[45]
RXBUFRESET0	in	CELL[12].IMUX_IMUX_DELAY[43]
RXCDRRESET0	in	CELL[12].IMUX_IMUX_DELAY[47]
RXCHBONDI0[0]	in	CELL[13].IMUX_IMUX_DELAY[44]
RXCHBONDI0[1]	in	CELL[13].IMUX_IMUX_DELAY[45]
RXCHBONDI0[2]	in	CELL[13].IMUX_IMUX_DELAY[46]
RXCHBONDI0[3]	in	CELL[13].IMUX_IMUX_DELAY[43]
RXCOMMADETUSE0	in	CELL[15].IMUX_IMUX_DELAY[30]
RXDATAWIDTH0[0]	in	CELL[15].IMUX_IMUX_DELAY[37]
RXDATAWIDTH0[1]	in	CELL[15].IMUX_IMUX_DELAY[18]
RXDEC8B10BUSE0	in	CELL[13].IMUX_IMUX_DELAY[41]
RXENCHANSYNC0	in	CELL[13].IMUX_IMUX_DELAY[23]
RXENEQB0	in	CELL[15].IMUX_IMUX_DELAY[42]
RXENMCOMMAALIGN0	in	CELL[15].IMUX_IMUX_DELAY[45]
RXENPCOMMAALIGN0	in	CELL[15].IMUX_IMUX_DELAY[46]
RXENPMAPHASEALIGN0	in	CELL[12].IMUX_IMUX_DELAY[13]
RXENPRBSTST0[0]	in	CELL[15].IMUX_IMUX_DELAY[28]
RXENPRBSTST0[1]	in	CELL[15].IMUX_IMUX_DELAY[29]
RXENSAMPLEALIGN0	in	CELL[15].IMUX_IMUX_DELAY[14]
RXEQMIX0[0]	in	CELL[14].IMUX_IMUX_DELAY[46]
RXEQMIX0[1]	in	CELL[14].IMUX_IMUX_DELAY[47]
RXEQPOLE0[0]	in	CELL[14].IMUX_IMUX_DELAY[42]
RXEQPOLE0[1]	in	CELL[14].IMUX_IMUX_DELAY[43]
RXEQPOLE0[2]	in	CELL[14].IMUX_IMUX_DELAY[44]
RXEQPOLE0[3]	in	CELL[14].IMUX_IMUX_DELAY[45]
RXGEARBOXSLIP0	in	CELL[15].IMUX_IMUX_DELAY[17]
RXPMASETPHASE0	in	CELL[12].IMUX_IMUX_DELAY[7]
RXPOLARITY0	in	CELL[15].IMUX_IMUX_DELAY[41]
RXPOWERDOWN0[0]	in	CELL[12].IMUX_IMUX_DELAY[38]
RXPOWERDOWN0[1]	in	CELL[12].IMUX_IMUX_DELAY[39]
RXRESET0	in	CELL[12].IMUX_IMUX_DELAY[42]
RXSLIDE0	in	CELL[15].IMUX_IMUX_DELAY[44]
RXUSRCLK0	in	CELL[10].IMUX_CLK[0] invert by HCLK[22][12]
RXUSRCLK20	in	CELL[10].IMUX_CLK[1] invert by HCLK[22][13]
TSTPWRDN0[0]	in	CELL[13].IMUX_IMUX_DELAY[31]
TSTPWRDN0[1]	in	CELL[13].IMUX_IMUX_DELAY[32]
TSTPWRDN0[2]	in	CELL[13].IMUX_IMUX_DELAY[33]
TSTPWRDN0[3]	in	CELL[13].IMUX_IMUX_DELAY[34]
TSTPWRDN0[4]	in	CELL[13].IMUX_IMUX_DELAY[35]
TSTPWRDNOVRD0	in	CELL[18].IMUX_IMUX_DELAY[30]
TXBUFDIFFCTRL0[0]	in	CELL[19].IMUX_IMUX_DELAY[30]
TXBUFDIFFCTRL0[1]	in	CELL[19].IMUX_IMUX_DELAY[31]
TXBUFDIFFCTRL0[2]	in	CELL[19].IMUX_IMUX_DELAY[32]
TXBYPASS8B10B0[0]	in	CELL[18].IMUX_IMUX_DELAY[29]
TXBYPASS8B10B0[1]	in	CELL[17].IMUX_IMUX_DELAY[29]
TXBYPASS8B10B0[2]	in	CELL[15].IMUX_IMUX_DELAY[27]
TXBYPASS8B10B0[3]	in	CELL[15].IMUX_IMUX_DELAY[21]
TXCHARDISPMODE0[0]	in	CELL[18].IMUX_IMUX_DELAY[27]
TXCHARDISPMODE0[1]	in	CELL[17].IMUX_IMUX_DELAY[27]
TXCHARDISPMODE0[2]	in	CELL[19].IMUX_IMUX_DELAY[15]
TXCHARDISPMODE0[3]	in	CELL[17].IMUX_IMUX_DELAY[7]
TXCHARDISPVAL0[0]	in	CELL[18].IMUX_IMUX_DELAY[26]
TXCHARDISPVAL0[1]	in	CELL[17].IMUX_IMUX_DELAY[26]
TXCHARDISPVAL0[2]	in	CELL[19].IMUX_IMUX_DELAY[2]
TXCHARDISPVAL0[3]	in	CELL[17].IMUX_IMUX_DELAY[25]
TXCHARISK0[0]	in	CELL[18].IMUX_IMUX_DELAY[46]
TXCHARISK0[1]	in	CELL[17].IMUX_IMUX_DELAY[28]
TXCHARISK0[2]	in	CELL[18].IMUX_IMUX_DELAY[28]
TXCHARISK0[3]	in	CELL[17].IMUX_IMUX_DELAY[8]
TXCOMSTART0	in	CELL[18].IMUX_IMUX_DELAY[4]
TXCOMTYPE0	in	CELL[18].IMUX_IMUX_DELAY[5]
TXDATA0[0]	in	CELL[19].IMUX_IMUX_DELAY[45]
TXDATA0[1]	in	CELL[19].IMUX_IMUX_DELAY[44]
TXDATA0[2]	in	CELL[19].IMUX_IMUX_DELAY[43]
TXDATA0[3]	in	CELL[19].IMUX_IMUX_DELAY[42]
TXDATA0[4]	in	CELL[18].IMUX_IMUX_DELAY[45]
TXDATA0[5]	in	CELL[18].IMUX_IMUX_DELAY[44]
TXDATA0[6]	in	CELL[18].IMUX_IMUX_DELAY[43]
TXDATA0[7]	in	CELL[18].IMUX_IMUX_DELAY[42]
TXDATA0[8]	in	CELL[17].IMUX_IMUX_DELAY[45]
TXDATA0[9]	in	CELL[17].IMUX_IMUX_DELAY[44]
TXDATA0[10]	in	CELL[17].IMUX_IMUX_DELAY[43]
TXDATA0[11]	in	CELL[17].IMUX_IMUX_DELAY[42]
TXDATA0[12]	in	CELL[16].IMUX_IMUX_DELAY[45]
TXDATA0[13]	in	CELL[16].IMUX_IMUX_DELAY[44]
TXDATA0[14]	in	CELL[16].IMUX_IMUX_DELAY[43]
TXDATA0[15]	in	CELL[16].IMUX_IMUX_DELAY[42]
TXDATA0[16]	in	CELL[19].IMUX_IMUX_DELAY[23]
TXDATA0[17]	in	CELL[19].IMUX_IMUX_DELAY[22]
TXDATA0[18]	in	CELL[19].IMUX_IMUX_DELAY[20]
TXDATA0[19]	in	CELL[19].IMUX_IMUX_DELAY[12]
TXDATA0[20]	in	CELL[18].IMUX_IMUX_DELAY[35]
TXDATA0[21]	in	CELL[18].IMUX_IMUX_DELAY[33]
TXDATA0[22]	in	CELL[18].IMUX_IMUX_DELAY[32]
TXDATA0[23]	in	CELL[18].IMUX_IMUX_DELAY[31]
TXDATA0[24]	in	CELL[17].IMUX_IMUX_DELAY[23]
TXDATA0[25]	in	CELL[17].IMUX_IMUX_DELAY[22]
TXDATA0[26]	in	CELL[17].IMUX_IMUX_DELAY[21]
TXDATA0[27]	in	CELL[17].IMUX_IMUX_DELAY[20]
TXDATA0[28]	in	CELL[16].IMUX_IMUX_DELAY[23]
TXDATA0[29]	in	CELL[16].IMUX_IMUX_DELAY[22]
TXDATA0[30]	in	CELL[16].IMUX_IMUX_DELAY[21]
TXDATA0[31]	in	CELL[16].IMUX_IMUX_DELAY[20]
TXDATAWIDTH0[0]	in	CELL[16].IMUX_IMUX_DELAY[31]
TXDATAWIDTH0[1]	in	CELL[16].IMUX_IMUX_DELAY[24]
TXDETECTRX0	in	CELL[19].IMUX_IMUX_DELAY[18]
TXDIFFCTRL0[0]	in	CELL[19].IMUX_IMUX_DELAY[33]
TXDIFFCTRL0[1]	in	CELL[19].IMUX_IMUX_DELAY[34]
TXDIFFCTRL0[2]	in	CELL[19].IMUX_IMUX_DELAY[35]
TXELECIDLE0	in	CELL[19].IMUX_IMUX_DELAY[19]
TXENC8B10BUSE0	in	CELL[16].IMUX_IMUX_DELAY[30]
TXENPMAPHASEALIGN0	in	CELL[10].IMUX_IMUX_DELAY[16]
TXENPRBSTST0[0]	in	CELL[18].IMUX_IMUX_DELAY[24]
TXENPRBSTST0[1]	in	CELL[18].IMUX_IMUX_DELAY[25]
TXHEADER0[0]	in	CELL[16].IMUX_IMUX_DELAY[32]
TXHEADER0[1]	in	CELL[16].IMUX_IMUX_DELAY[33]
TXHEADER0[2]	in	CELL[16].IMUX_IMUX_DELAY[4]
TXINHIBIT0	in	CELL[16].IMUX_IMUX_DELAY[28]
TXPMASETPHASE0	in	CELL[10].IMUX_IMUX_DELAY[17]
TXPOLARITY0	in	CELL[17].IMUX_IMUX_DELAY[15]
TXPOWERDOWN0[0]	in	CELL[17].IMUX_IMUX_DELAY[10]
TXPOWERDOWN0[1]	in	CELL[17].IMUX_IMUX_DELAY[11]
TXPREEMPHASIS0[0]	in	CELL[18].IMUX_IMUX_DELAY[15]
TXPREEMPHASIS0[1]	in	CELL[18].IMUX_IMUX_DELAY[16]
TXPREEMPHASIS0[2]	in	CELL[18].IMUX_IMUX_DELAY[17]
TXPREEMPHASIS0[3]	in	CELL[17].IMUX_IMUX_DELAY[37]
TXRESET0	in	CELL[16].IMUX_IMUX_DELAY[47]
TXSEQUENCE0[0]	in	CELL[18].IMUX_IMUX_DELAY[2]
TXSEQUENCE0[1]	in	CELL[18].IMUX_IMUX_DELAY[3]
TXSEQUENCE0[2]	in	CELL[19].IMUX_IMUX_DELAY[0]
TXSEQUENCE0[3]	in	CELL[19].IMUX_IMUX_DELAY[1]
TXSEQUENCE0[4]	in	CELL[19].IMUX_IMUX_DELAY[3]
TXSEQUENCE0[5]	in	CELL[19].IMUX_IMUX_DELAY[4]
TXSEQUENCE0[6]	in	CELL[19].IMUX_IMUX_DELAY[5]
TXSTARTSEQ0	in	CELL[16].IMUX_IMUX_DELAY[9]
TXUSRCLK0	in	CELL[11].IMUX_CLK[0] invert by HCLK[23][12]
TXUSRCLK20	in	CELL[11].IMUX_CLK[1] invert by HCLK[23][13]
DFECLKDLYADJ1[0]	in	CELL[5].IMUX_IMUX_DELAY[24]
DFECLKDLYADJ1[1]	in	CELL[4].IMUX_IMUX_DELAY[29]
DFECLKDLYADJ1[2]	in	CELL[4].IMUX_IMUX_DELAY[34]
DFECLKDLYADJ1[3]	in	CELL[4].IMUX_IMUX_DELAY[27]
DFECLKDLYADJ1[4]	in	CELL[4].IMUX_IMUX_DELAY[32]
DFECLKDLYADJ1[5]	in	CELL[4].IMUX_IMUX_DELAY[31]
DFETAP11[0]	in	CELL[5].IMUX_IMUX_DELAY[28]
DFETAP11[1]	in	CELL[5].IMUX_IMUX_DELAY[33]
DFETAP11[2]	in	CELL[5].IMUX_IMUX_DELAY[26]
DFETAP11[3]	in	CELL[5].IMUX_IMUX_DELAY[25]
DFETAP11[4]	in	CELL[5].IMUX_IMUX_DELAY[12]
DFETAP21[0]	in	CELL[5].IMUX_IMUX_DELAY[29]
DFETAP21[1]	in	CELL[5].IMUX_IMUX_DELAY[11]
DFETAP21[2]	in	CELL[5].IMUX_IMUX_DELAY[22]
DFETAP21[3]	in	CELL[5].IMUX_IMUX_DELAY[27]
DFETAP21[4]	in	CELL[5].IMUX_IMUX_DELAY[20]
DFETAP31[0]	in	CELL[6].IMUX_IMUX_DELAY[34]
DFETAP31[1]	in	CELL[6].IMUX_IMUX_DELAY[39]
DFETAP31[2]	in	CELL[6].IMUX_IMUX_DELAY[32]
DFETAP31[3]	in	CELL[6].IMUX_IMUX_DELAY[31]
DFETAP41[0]	in	CELL[7].IMUX_IMUX_DELAY[28]
DFETAP41[1]	in	CELL[7].IMUX_IMUX_DELAY[25]
DFETAP41[2]	in	CELL[7].IMUX_IMUX_DELAY[24]
DFETAP41[3]	in	CELL[6].IMUX_IMUX_DELAY[11]
LOOPBACK1[0]	in	CELL[7].IMUX_IMUX_DELAY[20]
LOOPBACK1[1]	in	CELL[7].IMUX_IMUX_DELAY[19]
LOOPBACK1[2]	in	CELL[7].IMUX_IMUX_DELAY[18]
PRBSCNTRESET1	in	CELL[8].IMUX_IMUX_DELAY[2]
RXBUFRESET1	in	CELL[7].IMUX_IMUX_DELAY[4]
RXCDRRESET1	in	CELL[7].IMUX_IMUX_DELAY[0]
RXCHBONDI1[0]	in	CELL[6].IMUX_IMUX_DELAY[3]
RXCHBONDI1[1]	in	CELL[6].IMUX_IMUX_DELAY[2]
RXCHBONDI1[2]	in	CELL[6].IMUX_IMUX_DELAY[1]
RXCHBONDI1[3]	in	CELL[6].IMUX_IMUX_DELAY[23]
RXCOMMADETUSE1	in	CELL[4].IMUX_IMUX_DELAY[17]
RXDATAWIDTH1[0]	in	CELL[4].IMUX_IMUX_DELAY[10]
RXDATAWIDTH1[1]	in	CELL[4].IMUX_IMUX_DELAY[15]
RXDEC8B10BUSE1	in	CELL[6].IMUX_IMUX_DELAY[6]
RXENCHANSYNC1	in	CELL[6].IMUX_IMUX_DELAY[24]
RXENEQB1	in	CELL[4].IMUX_IMUX_DELAY[5]
RXENMCOMMAALIGN1	in	CELL[4].IMUX_IMUX_DELAY[2]
RXENPCOMMAALIGN1	in	CELL[4].IMUX_IMUX_DELAY[1]
RXENPMAPHASEALIGN1	in	CELL[7].IMUX_IMUX_DELAY[34]
RXENPRBSTST1[0]	in	CELL[4].IMUX_IMUX_DELAY[25]
RXENPRBSTST1[1]	in	CELL[4].IMUX_IMUX_DELAY[24]
RXENSAMPLEALIGN1	in	CELL[4].IMUX_IMUX_DELAY[33]
RXEQMIX1[0]	in	CELL[5].IMUX_IMUX_DELAY[1]
RXEQMIX1[1]	in	CELL[5].IMUX_IMUX_DELAY[0]
RXEQPOLE1[0]	in	CELL[5].IMUX_IMUX_DELAY[5]
RXEQPOLE1[1]	in	CELL[5].IMUX_IMUX_DELAY[4]
RXEQPOLE1[2]	in	CELL[5].IMUX_IMUX_DELAY[3]
RXEQPOLE1[3]	in	CELL[5].IMUX_IMUX_DELAY[2]
RXGEARBOXSLIP1	in	CELL[4].IMUX_IMUX_DELAY[22]
RXPMASETPHASE1	in	CELL[7].IMUX_IMUX_DELAY[40]
RXPOLARITY1	in	CELL[4].IMUX_IMUX_DELAY[0]
RXPOWERDOWN1[0]	in	CELL[7].IMUX_IMUX_DELAY[9]
RXPOWERDOWN1[1]	in	CELL[7].IMUX_IMUX_DELAY[8]
RXRESET1	in	CELL[7].IMUX_IMUX_DELAY[5]
RXSLIDE1	in	CELL[4].IMUX_IMUX_DELAY[3]
RXUSRCLK1	in	CELL[9].IMUX_CLK[1] invert by HCLK[21][13]
RXUSRCLK21	in	CELL[9].IMUX_CLK[0] invert by HCLK[21][12]
TSTPWRDN1[0]	in	CELL[6].IMUX_IMUX_DELAY[16]
TSTPWRDN1[1]	in	CELL[6].IMUX_IMUX_DELAY[15]
TSTPWRDN1[2]	in	CELL[6].IMUX_IMUX_DELAY[14]
TSTPWRDN1[3]	in	CELL[6].IMUX_IMUX_DELAY[13]
TSTPWRDN1[4]	in	CELL[6].IMUX_IMUX_DELAY[12]
TSTPWRDNOVRD1	in	CELL[1].IMUX_IMUX_DELAY[47]
TXBUFDIFFCTRL1[0]	in	CELL[0].IMUX_IMUX_DELAY[17]
TXBUFDIFFCTRL1[1]	in	CELL[0].IMUX_IMUX_DELAY[16]
TXBUFDIFFCTRL1[2]	in	CELL[0].IMUX_IMUX_DELAY[15]
TXBYPASS8B10B1[0]	in	CELL[1].IMUX_IMUX_DELAY[12]
TXBYPASS8B10B1[1]	in	CELL[2].IMUX_IMUX_DELAY[24]
TXBYPASS8B10B1[2]	in	CELL[4].IMUX_IMUX_DELAY[20]
TXBYPASS8B10B1[3]	in	CELL[4].IMUX_IMUX_DELAY[14]
TXCHARDISPMODE1[0]	in	CELL[1].IMUX_IMUX_DELAY[8]
TXCHARDISPMODE1[1]	in	CELL[2].IMUX_IMUX_DELAY[20]
TXCHARDISPMODE1[2]	in	CELL[0].IMUX_IMUX_DELAY[38]
TXCHARDISPMODE1[3]	in	CELL[2].IMUX_IMUX_DELAY[40]
TXCHARDISPVAL1[0]	in	CELL[1].IMUX_IMUX_DELAY[21]
TXCHARDISPVAL1[1]	in	CELL[2].IMUX_IMUX_DELAY[21]
TXCHARDISPVAL1[2]	in	CELL[0].IMUX_IMUX_DELAY[9]
TXCHARDISPVAL1[3]	in	CELL[2].IMUX_IMUX_DELAY[28]
TXCHARISK1[0]	in	CELL[1].IMUX_IMUX_DELAY[1]
TXCHARISK1[1]	in	CELL[2].IMUX_IMUX_DELAY[25]
TXCHARISK1[2]	in	CELL[1].IMUX_IMUX_DELAY[13]
TXCHARISK1[3]	in	CELL[2].IMUX_IMUX_DELAY[39]
TXCOMSTART1	in	CELL[1].IMUX_IMUX_DELAY[37]
TXCOMTYPE1	in	CELL[1].IMUX_IMUX_DELAY[0]
TXDATA1[0]	in	CELL[0].IMUX_IMUX_DELAY[32]
TXDATA1[1]	in	CELL[0].IMUX_IMUX_DELAY[33]
TXDATA1[2]	in	CELL[0].IMUX_IMUX_DELAY[34]
TXDATA1[3]	in	CELL[0].IMUX_IMUX_DELAY[35]
TXDATA1[4]	in	CELL[1].IMUX_IMUX_DELAY[32]
TXDATA1[5]	in	CELL[1].IMUX_IMUX_DELAY[33]
TXDATA1[6]	in	CELL[1].IMUX_IMUX_DELAY[34]
TXDATA1[7]	in	CELL[1].IMUX_IMUX_DELAY[35]
TXDATA1[8]	in	CELL[2].IMUX_IMUX_DELAY[32]
TXDATA1[9]	in	CELL[2].IMUX_IMUX_DELAY[33]
TXDATA1[10]	in	CELL[2].IMUX_IMUX_DELAY[34]
TXDATA1[11]	in	CELL[2].IMUX_IMUX_DELAY[35]
TXDATA1[12]	in	CELL[3].IMUX_IMUX_DELAY[32]
TXDATA1[13]	in	CELL[3].IMUX_IMUX_DELAY[33]
TXDATA1[14]	in	CELL[3].IMUX_IMUX_DELAY[34]
TXDATA1[15]	in	CELL[3].IMUX_IMUX_DELAY[35]
TXDATA1[16]	in	CELL[0].IMUX_IMUX_DELAY[0]
TXDATA1[17]	in	CELL[0].IMUX_IMUX_DELAY[31]
TXDATA1[18]	in	CELL[0].IMUX_IMUX_DELAY[27]
TXDATA1[19]	in	CELL[0].IMUX_IMUX_DELAY[29]
TXDATA1[20]	in	CELL[1].IMUX_IMUX_DELAY[6]
TXDATA1[21]	in	CELL[1].IMUX_IMUX_DELAY[20]
TXDATA1[22]	in	CELL[1].IMUX_IMUX_DELAY[39]
TXDATA1[23]	in	CELL[1].IMUX_IMUX_DELAY[28]
TXDATA1[24]	in	CELL[2].IMUX_IMUX_DELAY[30]
TXDATA1[25]	in	CELL[2].IMUX_IMUX_DELAY[31]
TXDATA1[26]	in	CELL[2].IMUX_IMUX_DELAY[38]
TXDATA1[27]	in	CELL[2].IMUX_IMUX_DELAY[27]
TXDATA1[28]	in	CELL[3].IMUX_IMUX_DELAY[30]
TXDATA1[29]	in	CELL[3].IMUX_IMUX_DELAY[31]
TXDATA1[30]	in	CELL[3].IMUX_IMUX_DELAY[38]
TXDATA1[31]	in	CELL[3].IMUX_IMUX_DELAY[39]
TXDATAWIDTH1[0]	in	CELL[3].IMUX_IMUX_DELAY[4]
TXDATAWIDTH1[1]	in	CELL[3].IMUX_IMUX_DELAY[5]
TXDETECTRX1	in	CELL[0].IMUX_IMUX_DELAY[47]
TXDIFFCTRL1[0]	in	CELL[0].IMUX_IMUX_DELAY[8]
TXDIFFCTRL1[1]	in	CELL[0].IMUX_IMUX_DELAY[7]
TXDIFFCTRL1[2]	in	CELL[0].IMUX_IMUX_DELAY[6]
TXELECIDLE1	in	CELL[0].IMUX_IMUX_DELAY[4]
TXENC8B10BUSE1	in	CELL[3].IMUX_IMUX_DELAY[47]
TXENPMAPHASEALIGN1	in	CELL[9].IMUX_IMUX_DELAY[20]
TXENPRBSTST1[0]	in	CELL[1].IMUX_IMUX_DELAY[11]
TXENPRBSTST1[1]	in	CELL[1].IMUX_IMUX_DELAY[10]
TXHEADER1[0]	in	CELL[3].IMUX_IMUX_DELAY[9]
TXHEADER1[1]	in	CELL[3].IMUX_IMUX_DELAY[20]
TXHEADER1[2]	in	CELL[3].IMUX_IMUX_DELAY[7]
TXINHIBIT1	in	CELL[3].IMUX_IMUX_DELAY[1]
TXPMASETPHASE1	in	CELL[9].IMUX_IMUX_DELAY[33]
TXPOLARITY1	in	CELL[2].IMUX_IMUX_DELAY[2]
TXPOWERDOWN1[0]	in	CELL[2].IMUX_IMUX_DELAY[43]
TXPOWERDOWN1[1]	in	CELL[2].IMUX_IMUX_DELAY[42]
TXPREEMPHASIS1[0]	in	CELL[1].IMUX_IMUX_DELAY[26]
TXPREEMPHASIS1[1]	in	CELL[1].IMUX_IMUX_DELAY[25]
TXPREEMPHASIS1[2]	in	CELL[1].IMUX_IMUX_DELAY[24]
TXPREEMPHASIS1[3]	in	CELL[2].IMUX_IMUX_DELAY[10]
TXRESET1	in	CELL[3].IMUX_IMUX_DELAY[0]
TXSEQUENCE1[0]	in	CELL[1].IMUX_IMUX_DELAY[46]
TXSEQUENCE1[1]	in	CELL[1].IMUX_IMUX_DELAY[3]
TXSEQUENCE1[2]	in	CELL[0].IMUX_IMUX_DELAY[41]
TXSEQUENCE1[3]	in	CELL[0].IMUX_IMUX_DELAY[46]
TXSEQUENCE1[4]	in	CELL[0].IMUX_IMUX_DELAY[45]
TXSEQUENCE1[5]	in	CELL[0].IMUX_IMUX_DELAY[44]
TXSEQUENCE1[6]	in	CELL[0].IMUX_IMUX_DELAY[37]
TXSTARTSEQ1	in	CELL[3].IMUX_IMUX_DELAY[8]
TXUSRCLK1	in	CELL[8].IMUX_CLK[1] invert by HCLK[20][13]
TXUSRCLK21	in	CELL[8].IMUX_CLK[0] invert by HCLK[20][12]
SCANEN	in	CELL[19].IMUX_IMUX_DELAY[17]
SCANINPCS0	in	CELL[19].IMUX_IMUX_DELAY[47]
SCANINPCS1	in	CELL[0].IMUX_IMUX_DELAY[30]
SCANINPCSCOMMON	in	CELL[11].IMUX_IMUX_DELAY[29]
SCANMODE	in	CELL[0].IMUX_IMUX_DELAY[36]
DRDY	out	CELL[9].OUT_BEL[15]
DO[0]	out	CELL[11].OUT_BEL[21]
DO[1]	out	CELL[11].OUT_BEL[17]
DO[2]	out	CELL[11].OUT_BEL[15]
DO[3]	out	CELL[11].OUT_BEL[14]
DO[4]	out	CELL[10].OUT_BEL[10]
DO[5]	out	CELL[10].OUT_BEL[9]
DO[6]	out	CELL[10].OUT_BEL[0]
DO[7]	out	CELL[10].OUT_BEL[12]
DO[8]	out	CELL[9].OUT_BEL[21]
DO[9]	out	CELL[9].OUT_BEL[6]
DO[10]	out	CELL[9].OUT_BEL[20]
DO[11]	out	CELL[9].OUT_BEL[10]
DO[12]	out	CELL[8].OUT_BEL[13]
DO[13]	out	CELL[8].OUT_BEL[18]
DO[14]	out	CELL[8].OUT_BEL[12]
DO[15]	out	CELL[8].OUT_BEL[8]
PLLLKDET	out	CELL[9].OUT_BEL[23]
REFCLKOUT	out	CELL[10].OUT_BEL[8], CELL[10].MGT_ROW_O[2]
PMATSTCLK	out	CELL[10].OUT_BEL[22]
DFECLKDLYADJMONITOR0[0]	out	CELL[15].OUT_BEL[4]
DFECLKDLYADJMONITOR0[1]	out	CELL[15].OUT_BEL[0]
DFECLKDLYADJMONITOR0[2]	out	CELL[15].OUT_BEL[19]
DFECLKDLYADJMONITOR0[3]	out	CELL[15].OUT_BEL[16]
DFECLKDLYADJMONITOR0[4]	out	CELL[15].OUT_BEL[6]
DFECLKDLYADJMONITOR0[5]	out	CELL[15].OUT_BEL[15]
DFEEYEDACMONITOR0[0]	out	CELL[14].OUT_BEL[0]
DFEEYEDACMONITOR0[1]	out	CELL[14].OUT_BEL[19]
DFEEYEDACMONITOR0[2]	out	CELL[14].OUT_BEL[16]
DFEEYEDACMONITOR0[3]	out	CELL[14].OUT_BEL[2]
DFEEYEDACMONITOR0[4]	out	CELL[15].OUT_BEL[8]
DFESENSCAL0[0]	out	CELL[10].OUT_BEL[18]
DFESENSCAL0[1]	out	CELL[10].OUT_BEL[19]
DFESENSCAL0[2]	out	CELL[10].OUT_BEL[17]
DFETAP1MONITOR0[0]	out	CELL[13].OUT_BEL[8]
DFETAP1MONITOR0[1]	out	CELL[13].OUT_BEL[0]
DFETAP1MONITOR0[2]	out	CELL[13].OUT_BEL[16]
DFETAP1MONITOR0[3]	out	CELL[13].OUT_BEL[6]
DFETAP1MONITOR0[4]	out	CELL[13].OUT_BEL[15]
DFETAP2MONITOR0[0]	out	CELL[12].OUT_BEL[12]
DFETAP2MONITOR0[1]	out	CELL[12].OUT_BEL[19]
DFETAP2MONITOR0[2]	out	CELL[12].OUT_BEL[16]
DFETAP2MONITOR0[3]	out	CELL[12].OUT_BEL[2]
DFETAP2MONITOR0[4]	out	CELL[12].OUT_BEL[6]
DFETAP3MONITOR0[0]	out	CELL[11].OUT_BEL[8]
DFETAP3MONITOR0[1]	out	CELL[11].OUT_BEL[18]
DFETAP3MONITOR0[2]	out	CELL[11].OUT_BEL[1]
DFETAP3MONITOR0[3]	out	CELL[11].OUT_BEL[11]
DFETAP4MONITOR0[0]	out	CELL[10].OUT_BEL[1]
DFETAP4MONITOR0[1]	out	CELL[10].OUT_BEL[14]
DFETAP4MONITOR0[2]	out	CELL[10].OUT_BEL[20]
DFETAP4MONITOR0[3]	out	CELL[10].OUT_BEL[3]
PHYSTATUS0	out	CELL[15].OUT_BEL[12]
RESETDONE0	out	CELL[15].OUT_BEL[7]
RXBUFSTATUS0[0]	out	CELL[15].OUT_BEL[1]
RXBUFSTATUS0[1]	out	CELL[15].OUT_BEL[13]
RXBUFSTATUS0[2]	out	CELL[15].OUT_BEL[14]
RXBYTEISALIGNED0	out	CELL[14].OUT_BEL[7]
RXBYTEREALIGN0	out	CELL[14].OUT_BEL[15]
RXCHANBONDSEQ0	out	CELL[12].OUT_BEL[1]
RXCHANISALIGNED0	out	CELL[12].OUT_BEL[15]
RXCHANREALIGN0	out	CELL[12].OUT_BEL[3]
RXCHARISCOMMA0[0]	out	CELL[14].OUT_BEL[12]
RXCHARISCOMMA0[1]	out	CELL[13].OUT_BEL[12]
RXCHARISCOMMA0[2]	out	CELL[16].OUT_BEL[1]
RXCHARISCOMMA0[3]	out	CELL[17].OUT_BEL[21]
RXCHARISK0[0]	out	CELL[14].OUT_BEL[13]
RXCHARISK0[1]	out	CELL[13].OUT_BEL[13]
RXCHARISK0[2]	out	CELL[17].OUT_BEL[12]
RXCHARISK0[3]	out	CELL[18].OUT_BEL[18]
RXCHBONDO0[0]	out	CELL[12].OUT_BEL[14]
RXCHBONDO0[1]	out	CELL[12].OUT_BEL[7]
RXCHBONDO0[2]	out	CELL[12].OUT_BEL[21]
RXCHBONDO0[3]	out	CELL[12].OUT_BEL[11]
RXCLKCORCNT0[0]	out	CELL[16].OUT_BEL[5]
RXCLKCORCNT0[1]	out	CELL[16].OUT_BEL[23]
RXCLKCORCNT0[2]	out	CELL[16].OUT_BEL[20]
RXCOMMADET0	out	CELL[14].OUT_BEL[21]
RXDATA0[0]	out	CELL[15].OUT_BEL[20]
RXDATA0[1]	out	CELL[15].OUT_BEL[23]
RXDATA0[2]	out	CELL[15].OUT_BEL[5]
RXDATA0[3]	out	CELL[15].OUT_BEL[22]
RXDATA0[4]	out	CELL[14].OUT_BEL[20]
RXDATA0[5]	out	CELL[14].OUT_BEL[23]
RXDATA0[6]	out	CELL[14].OUT_BEL[5]
RXDATA0[7]	out	CELL[14].OUT_BEL[22]
RXDATA0[8]	out	CELL[13].OUT_BEL[20]
RXDATA0[9]	out	CELL[13].OUT_BEL[23]
RXDATA0[10]	out	CELL[13].OUT_BEL[5]
RXDATA0[11]	out	CELL[13].OUT_BEL[22]
RXDATA0[12]	out	CELL[12].OUT_BEL[20]
RXDATA0[13]	out	CELL[12].OUT_BEL[23]
RXDATA0[14]	out	CELL[12].OUT_BEL[5]
RXDATA0[15]	out	CELL[12].OUT_BEL[22]
RXDATA0[16]	out	CELL[15].OUT_BEL[17]
RXDATA0[17]	out	CELL[15].OUT_BEL[21]
RXDATA0[18]	out	CELL[16].OUT_BEL[12]
RXDATA0[19]	out	CELL[16].OUT_BEL[16]
RXDATA0[20]	out	CELL[16].OUT_BEL[2]
RXDATA0[21]	out	CELL[16].OUT_BEL[6]
RXDATA0[22]	out	CELL[16].OUT_BEL[11]
RXDATA0[23]	out	CELL[16].OUT_BEL[17]
RXDATA0[24]	out	CELL[17].OUT_BEL[9]
RXDATA0[25]	out	CELL[17].OUT_BEL[23]
RXDATA0[26]	out	CELL[17].OUT_BEL[10]
RXDATA0[27]	out	CELL[17].OUT_BEL[16]
RXDATA0[28]	out	CELL[18].OUT_BEL[19]
RXDATA0[29]	out	CELL[18].OUT_BEL[16]
RXDATA0[30]	out	CELL[18].OUT_BEL[20]
RXDATA0[31]	out	CELL[18].OUT_BEL[11]
RXDATAVALID0	out	CELL[19].OUT_BEL[23]
RXDISPERR0[0]	out	CELL[14].OUT_BEL[14]
RXDISPERR0[1]	out	CELL[13].OUT_BEL[14]
RXDISPERR0[2]	out	CELL[17].OUT_BEL[4]
RXDISPERR0[3]	out	CELL[18].OUT_BEL[4]
RXELECIDLE0	out	CELL[17].OUT_BEL[5]
RXHEADER0[0]	out	CELL[19].OUT_BEL[22]
RXHEADER0[1]	out	CELL[19].OUT_BEL[0]
RXHEADER0[2]	out	CELL[19].OUT_BEL[9]
RXHEADERVALID0	out	CELL[19].OUT_BEL[8]
RXLOSSOFSYNC0[0]	out	CELL[13].OUT_BEL[11]
RXLOSSOFSYNC0[1]	out	CELL[13].OUT_BEL[21]
RXNOTINTABLE0[0]	out	CELL[14].OUT_BEL[3]
RXNOTINTABLE0[1]	out	CELL[13].OUT_BEL[3]
RXNOTINTABLE0[2]	out	CELL[16].OUT_BEL[0]
RXNOTINTABLE0[3]	out	CELL[17].OUT_BEL[7]
RXOVERSAMPLEERR0	out	CELL[15].OUT_BEL[3]
RXPRBSERR0	out	CELL[16].OUT_BEL[22]
RXRECCLK0	out	CELL[10].MGT_ROW_O[0], CELL[12].OUT_BEL[13]
RXRUNDISP0[0]	out	CELL[14].OUT_BEL[1]
RXRUNDISP0[1]	out	CELL[13].OUT_BEL[1]
RXRUNDISP0[2]	out	CELL[16].OUT_BEL[19]
RXRUNDISP0[3]	out	CELL[18].OUT_BEL[8]
RXSTARTOFSEQ0	out	CELL[19].OUT_BEL[18]
RXSTATUS0[0]	out	CELL[16].OUT_BEL[14]
RXSTATUS0[1]	out	CELL[16].OUT_BEL[7]
RXSTATUS0[2]	out	CELL[16].OUT_BEL[21]
RXVALID0	out	CELL[13].OUT_BEL[7]
TXBUFSTATUS0[0]	out	CELL[18].OUT_BEL[0]
TXBUFSTATUS0[1]	out	CELL[18].OUT_BEL[23]
TXGEARBOXREADY0	out	CELL[19].OUT_BEL[16]
TXKERR0[0]	out	CELL[18].OUT_BEL[5]
TXKERR0[1]	out	CELL[17].OUT_BEL[18]
TXKERR0[2]	out	CELL[18].OUT_BEL[13]
TXKERR0[3]	out	CELL[17].OUT_BEL[22]
TXOUTCLK0	out	CELL[10].OUT_BEL[13], CELL[10].MGT_ROW_O[3]
TXRUNDISP0[0]	out	CELL[18].OUT_BEL[22]
TXRUNDISP0[1]	out	CELL[17].OUT_BEL[2]
TXRUNDISP0[2]	out	CELL[18].OUT_BEL[15]
TXRUNDISP0[3]	out	CELL[16].OUT_BEL[18]
DFECLKDLYADJMONITOR1[0]	out	CELL[4].OUT_BEL[15]
DFECLKDLYADJMONITOR1[1]	out	CELL[4].OUT_BEL[7]
DFECLKDLYADJMONITOR1[2]	out	CELL[4].OUT_BEL[3]
DFECLKDLYADJMONITOR1[3]	out	CELL[4].OUT_BEL[14]
DFECLKDLYADJMONITOR1[4]	out	CELL[4].OUT_BEL[13]
DFECLKDLYADJMONITOR1[5]	out	CELL[4].OUT_BEL[1]
DFEEYEDACMONITOR1[0]	out	CELL[6].OUT_BEL[18]
DFEEYEDACMONITOR1[1]	out	CELL[5].OUT_BEL[15]
DFEEYEDACMONITOR1[2]	out	CELL[5].OUT_BEL[14]
DFEEYEDACMONITOR1[3]	out	CELL[5].OUT_BEL[13]
DFEEYEDACMONITOR1[4]	out	CELL[5].OUT_BEL[12]
DFESENSCAL1[0]	out	CELL[9].OUT_BEL[7]
DFESENSCAL1[1]	out	CELL[9].OUT_BEL[9]
DFESENSCAL1[2]	out	CELL[9].OUT_BEL[22]
DFETAP1MONITOR1[0]	out	CELL[7].OUT_BEL[22]
DFETAP1MONITOR1[1]	out	CELL[6].OUT_BEL[21]
DFETAP1MONITOR1[2]	out	CELL[6].OUT_BEL[7]
DFETAP1MONITOR1[3]	out	CELL[6].OUT_BEL[23]
DFETAP1MONITOR1[4]	out	CELL[6].OUT_BEL[5]
DFETAP2MONITOR1[0]	out	CELL[8].OUT_BEL[22]
DFETAP2MONITOR1[1]	out	CELL[7].OUT_BEL[16]
DFETAP2MONITOR1[2]	out	CELL[7].OUT_BEL[14]
DFETAP2MONITOR1[3]	out	CELL[7].OUT_BEL[13]
DFETAP2MONITOR1[4]	out	CELL[7].OUT_BEL[1]
DFETAP3MONITOR1[0]	out	CELL[8].OUT_BEL[21]
DFETAP3MONITOR1[1]	out	CELL[8].OUT_BEL[7]
DFETAP3MONITOR1[2]	out	CELL[8].OUT_BEL[20]
DFETAP3MONITOR1[3]	out	CELL[8].OUT_BEL[4]
DFETAP4MONITOR1[0]	out	CELL[9].OUT_BEL[17]
DFETAP4MONITOR1[1]	out	CELL[9].OUT_BEL[16]
DFETAP4MONITOR1[2]	out	CELL[9].OUT_BEL[19]
DFETAP4MONITOR1[3]	out	CELL[9].OUT_BEL[5]
PHYSTATUS1	out	CELL[4].OUT_BEL[17]
RESETDONE1	out	CELL[4].OUT_BEL[0]
RXBUFSTATUS1[0]	out	CELL[4].OUT_BEL[6]
RXBUFSTATUS1[1]	out	CELL[4].OUT_BEL[16]
RXBUFSTATUS1[2]	out	CELL[4].OUT_BEL[19]
RXBYTEISALIGNED1	out	CELL[5].OUT_BEL[0]
RXBYTEREALIGN1	out	CELL[5].OUT_BEL[18]
RXCHANBONDSEQ1	out	CELL[7].OUT_BEL[6]
RXCHANISALIGNED1	out	CELL[7].OUT_BEL[18]
RXCHANREALIGN1	out	CELL[7].OUT_BEL[4]
RXCHARISCOMMA1[0]	out	CELL[5].OUT_BEL[17]
RXCHARISCOMMA1[1]	out	CELL[6].OUT_BEL[17]
RXCHARISCOMMA1[2]	out	CELL[3].OUT_BEL[7]
RXCHARISCOMMA1[3]	out	CELL[2].OUT_BEL[3]
RXCHARISK1[0]	out	CELL[5].OUT_BEL[16]
RXCHARISK1[1]	out	CELL[6].OUT_BEL[16]
RXCHARISK1[2]	out	CELL[3].OUT_BEL[12]
RXCHARISK1[3]	out	CELL[1].OUT_BEL[21]
RXCHBONDO1[0]	out	CELL[7].OUT_BEL[19]
RXCHBONDO1[1]	out	CELL[7].OUT_BEL[0]
RXCHBONDO1[2]	out	CELL[7].OUT_BEL[8]
RXCHBONDO1[3]	out	CELL[7].OUT_BEL[5]
RXCLKCORCNT1[0]	out	CELL[3].OUT_BEL[2]
RXCLKCORCNT1[1]	out	CELL[3].OUT_BEL[10]
RXCLKCORCNT1[2]	out	CELL[3].OUT_BEL[9]
RXCOMMADET1	out	CELL[5].OUT_BEL[8]
RXDATA1[0]	out	CELL[4].OUT_BEL[9]
RXDATA1[1]	out	CELL[4].OUT_BEL[10]
RXDATA1[2]	out	CELL[4].OUT_BEL[2]
RXDATA1[3]	out	CELL[4].OUT_BEL[11]
RXDATA1[4]	out	CELL[5].OUT_BEL[9]
RXDATA1[5]	out	CELL[5].OUT_BEL[10]
RXDATA1[6]	out	CELL[5].OUT_BEL[2]
RXDATA1[7]	out	CELL[5].OUT_BEL[11]
RXDATA1[8]	out	CELL[6].OUT_BEL[9]
RXDATA1[9]	out	CELL[6].OUT_BEL[10]
RXDATA1[10]	out	CELL[6].OUT_BEL[2]
RXDATA1[11]	out	CELL[6].OUT_BEL[11]
RXDATA1[12]	out	CELL[7].OUT_BEL[9]
RXDATA1[13]	out	CELL[7].OUT_BEL[10]
RXDATA1[14]	out	CELL[7].OUT_BEL[2]
RXDATA1[15]	out	CELL[7].OUT_BEL[11]
RXDATA1[16]	out	CELL[4].OUT_BEL[22]
RXDATA1[17]	out	CELL[4].OUT_BEL[18]
RXDATA1[18]	out	CELL[4].OUT_BEL[12]
RXDATA1[19]	out	CELL[3].OUT_BEL[16]
RXDATA1[20]	out	CELL[3].OUT_BEL[14]
RXDATA1[21]	out	CELL[3].OUT_BEL[23]
RXDATA1[22]	out	CELL[3].OUT_BEL[5]
RXDATA1[23]	out	CELL[3].OUT_BEL[22]
RXDATA1[24]	out	CELL[2].OUT_BEL[11]
RXDATA1[25]	out	CELL[2].OUT_BEL[7]
RXDATA1[26]	out	CELL[2].OUT_BEL[16]
RXDATA1[27]	out	CELL[2].OUT_BEL[19]
RXDATA1[28]	out	CELL[1].OUT_BEL[6]
RXDATA1[29]	out	CELL[1].OUT_BEL[20]
RXDATA1[30]	out	CELL[1].OUT_BEL[9]
RXDATA1[31]	out	CELL[1].OUT_BEL[4]
RXDATAVALID1	out	CELL[0].OUT_BEL[12]
RXDISPERR1[0]	out	CELL[5].OUT_BEL[19]
RXDISPERR1[1]	out	CELL[6].OUT_BEL[19]
RXDISPERR1[2]	out	CELL[2].OUT_BEL[17]
RXDISPERR1[3]	out	CELL[1].OUT_BEL[15]
RXELECIDLE1	out	CELL[2].OUT_BEL[2]
RXHEADER1[0]	out	CELL[0].OUT_BEL[17]
RXHEADER1[1]	out	CELL[0].OUT_BEL[6]
RXHEADER1[2]	out	CELL[0].OUT_BEL[16]
RXHEADERVALID1	out	CELL[0].OUT_BEL[11]
RXLOSSOFSYNC1[0]	out	CELL[6].OUT_BEL[22]
RXLOSSOFSYNC1[1]	out	CELL[6].OUT_BEL[8]
RXNOTINTABLE1[0]	out	CELL[5].OUT_BEL[4]
RXNOTINTABLE1[1]	out	CELL[6].OUT_BEL[4]
RXNOTINTABLE1[2]	out	CELL[3].OUT_BEL[17]
RXNOTINTABLE1[3]	out	CELL[2].OUT_BEL[4]
RXOVERSAMPLEERR1	out	CELL[4].OUT_BEL[4]
RXPRBSERR1	out	CELL[3].OUT_BEL[11]
RXRECCLK1	out	CELL[7].OUT_BEL[20], CELL[10].MGT_ROW_O[1]
RXRUNDISP1[0]	out	CELL[5].OUT_BEL[6]
RXRUNDISP1[1]	out	CELL[6].OUT_BEL[6]
RXRUNDISP1[2]	out	CELL[3].OUT_BEL[20]
RXRUNDISP1[3]	out	CELL[2].OUT_BEL[18]
RXSTARTOFSEQ1	out	CELL[0].OUT_BEL[2]
RXSTATUS1[0]	out	CELL[3].OUT_BEL[19]
RXSTATUS1[1]	out	CELL[3].OUT_BEL[0]
RXSTATUS1[2]	out	CELL[3].OUT_BEL[8]
RXVALID1	out	CELL[6].OUT_BEL[0]
TXBUFSTATUS1[0]	out	CELL[1].OUT_BEL[2]
TXBUFSTATUS1[1]	out	CELL[1].OUT_BEL[10]
TXGEARBOXREADY1	out	CELL[0].OUT_BEL[0]
TXKERR1[0]	out	CELL[1].OUT_BEL[7]
TXKERR1[1]	out	CELL[2].OUT_BEL[15]
TXKERR1[2]	out	CELL[1].OUT_BEL[14]
TXKERR1[3]	out	CELL[2].OUT_BEL[10]
TXOUTCLK1	out	CELL[9].OUT_BEL[2], CELL[10].MGT_ROW_O[4]
TXRUNDISP1[0]	out	CELL[1].OUT_BEL[11]
TXRUNDISP1[1]	out	CELL[2].OUT_BEL[5]
TXRUNDISP1[2]	out	CELL[1].OUT_BEL[18]
TXRUNDISP1[3]	out	CELL[3].OUT_BEL[21]
SCANOUTPCS0	out	CELL[12].OUT_BEL[10]
SCANOUTPCS1	out	CELL[7].OUT_BEL[7]
SCANOUTPCSCOMMON	out	CELL[8].OUT_BEL[1]

virtex5 GTX bel GTX_DUAL attribute bits
Attribute	GTX_DUAL
DRP[0] bit 0	MAIN[5][31][0]
DRP[0] bit 1	MAIN[5][30][0]
DRP[0] bit 2	MAIN[5][30][1]
DRP[0] bit 3	MAIN[5][31][1]
DRP[0] bit 4	MAIN[5][31][2]
DRP[0] bit 5	MAIN[5][30][2]
DRP[0] bit 6	MAIN[5][30][3]
DRP[0] bit 7	MAIN[5][31][3]
DRP[0] bit 8	MAIN[5][31][4]
DRP[0] bit 9	MAIN[5][30][4]
DRP[0] bit 10	MAIN[5][30][5]
DRP[0] bit 11	MAIN[5][31][5]
DRP[0] bit 12	MAIN[5][31][6]
DRP[0] bit 13	MAIN[5][30][6]
DRP[0] bit 14	MAIN[5][30][7]
DRP[0] bit 15	MAIN[5][31][7]
DRP[1] bit 0	MAIN[5][31][8]
DRP[1] bit 1	MAIN[5][30][8]
DRP[1] bit 2	MAIN[5][30][9]
DRP[1] bit 3	MAIN[5][31][9]
DRP[1] bit 4	MAIN[5][31][10]
DRP[1] bit 5	MAIN[5][30][10]
DRP[1] bit 6	MAIN[5][30][11]
DRP[1] bit 7	MAIN[5][31][11]
DRP[1] bit 8	MAIN[5][31][12]
DRP[1] bit 9	MAIN[5][30][12]
DRP[1] bit 10	MAIN[5][30][13]
DRP[1] bit 11	MAIN[5][31][13]
DRP[1] bit 12	MAIN[5][31][14]
DRP[1] bit 13	MAIN[5][30][14]
DRP[1] bit 14	MAIN[5][30][15]
DRP[1] bit 15	MAIN[5][31][15]
DRP[2] bit 0	MAIN[5][31][16]
DRP[2] bit 1	MAIN[5][30][16]
DRP[2] bit 2	MAIN[5][30][17]
DRP[2] bit 3	MAIN[5][31][17]
DRP[2] bit 4	MAIN[5][31][18]
DRP[2] bit 5	MAIN[5][30][18]
DRP[2] bit 6	MAIN[5][30][19]
DRP[2] bit 7	MAIN[5][31][19]
DRP[2] bit 8	MAIN[5][31][20]
DRP[2] bit 9	MAIN[5][30][20]
DRP[2] bit 10	MAIN[5][30][21]
DRP[2] bit 11	MAIN[5][31][21]
DRP[2] bit 12	MAIN[5][31][22]
DRP[2] bit 13	MAIN[5][30][22]
DRP[2] bit 14	MAIN[5][30][23]
DRP[2] bit 15	MAIN[5][31][23]
DRP[3] bit 0	MAIN[5][31][24]
DRP[3] bit 1	MAIN[5][30][24]
DRP[3] bit 2	MAIN[5][30][25]
DRP[3] bit 3	MAIN[5][31][25]
DRP[3] bit 4	MAIN[5][31][26]
DRP[3] bit 5	MAIN[5][30][26]
DRP[3] bit 6	MAIN[5][30][27]
DRP[3] bit 7	MAIN[5][31][27]
DRP[3] bit 8	MAIN[5][31][28]
DRP[3] bit 9	MAIN[5][30][28]
DRP[3] bit 10	MAIN[5][30][29]
DRP[3] bit 11	MAIN[5][31][29]
DRP[3] bit 12	MAIN[5][31][30]
DRP[3] bit 13	MAIN[5][30][30]
DRP[3] bit 14	MAIN[5][30][31]
DRP[3] bit 15	MAIN[5][31][31]
DRP[4] bit 0	MAIN[5][31][32]
DRP[4] bit 1	MAIN[5][30][32]
DRP[4] bit 2	MAIN[5][30][33]
DRP[4] bit 3	MAIN[5][31][33]
DRP[4] bit 4	MAIN[5][31][34]
DRP[4] bit 5	MAIN[5][30][34]
DRP[4] bit 6	MAIN[5][30][35]
DRP[4] bit 7	MAIN[5][31][35]
DRP[4] bit 8	MAIN[5][31][36]
DRP[4] bit 9	MAIN[5][30][36]
DRP[4] bit 10	MAIN[5][30][37]
DRP[4] bit 11	MAIN[5][31][37]
DRP[4] bit 12	MAIN[5][31][38]
DRP[4] bit 13	MAIN[5][30][38]
DRP[4] bit 14	MAIN[5][30][39]
DRP[4] bit 15	MAIN[5][31][39]
DRP[5] bit 0	MAIN[5][31][40]
DRP[5] bit 1	MAIN[5][30][40]
DRP[5] bit 2	MAIN[5][30][41]
DRP[5] bit 3	MAIN[5][31][41]
DRP[5] bit 4	MAIN[5][31][42]
DRP[5] bit 5	MAIN[5][30][42]
DRP[5] bit 6	MAIN[5][30][43]
DRP[5] bit 7	MAIN[5][31][43]
DRP[5] bit 8	MAIN[5][31][44]
DRP[5] bit 9	MAIN[5][30][44]
DRP[5] bit 10	MAIN[5][30][45]
DRP[5] bit 11	MAIN[5][31][45]
DRP[5] bit 12	MAIN[5][31][46]
DRP[5] bit 13	MAIN[5][30][46]
DRP[5] bit 14	MAIN[5][30][47]
DRP[5] bit 15	MAIN[5][31][47]
DRP[6] bit 0	MAIN[5][31][48]
DRP[6] bit 1	MAIN[5][30][48]
DRP[6] bit 2	MAIN[5][30][49]
DRP[6] bit 3	MAIN[5][31][49]
DRP[6] bit 4	MAIN[5][31][50]
DRP[6] bit 5	MAIN[5][30][50]
DRP[6] bit 6	MAIN[5][30][51]
DRP[6] bit 7	MAIN[5][31][51]
DRP[6] bit 8	MAIN[5][31][52]
DRP[6] bit 9	MAIN[5][30][52]
DRP[6] bit 10	MAIN[5][30][53]
DRP[6] bit 11	MAIN[5][31][53]
DRP[6] bit 12	MAIN[5][31][54]
DRP[6] bit 13	MAIN[5][30][54]
DRP[6] bit 14	MAIN[5][30][55]
DRP[6] bit 15	MAIN[5][31][55]
DRP[7] bit 0	MAIN[5][31][56]
DRP[7] bit 1	MAIN[5][30][56]
DRP[7] bit 2	MAIN[5][30][57]
DRP[7] bit 3	MAIN[5][31][57]
DRP[7] bit 4	MAIN[5][31][58]
DRP[7] bit 5	MAIN[5][30][58]
DRP[7] bit 6	MAIN[5][30][59]
DRP[7] bit 7	MAIN[5][31][59]
DRP[7] bit 8	MAIN[5][31][60]
DRP[7] bit 9	MAIN[5][30][60]
DRP[7] bit 10	MAIN[5][30][61]
DRP[7] bit 11	MAIN[5][31][61]
DRP[7] bit 12	MAIN[5][31][62]
DRP[7] bit 13	MAIN[5][30][62]
DRP[7] bit 14	MAIN[5][30][63]
DRP[7] bit 15	MAIN[5][31][63]
DRP[8] bit 0	MAIN[6][31][0]
DRP[8] bit 1	MAIN[6][30][0]
DRP[8] bit 2	MAIN[6][30][1]
DRP[8] bit 3	MAIN[6][31][1]
DRP[8] bit 4	MAIN[6][31][2]
DRP[8] bit 5	MAIN[6][30][2]
DRP[8] bit 6	MAIN[6][30][3]
DRP[8] bit 7	MAIN[6][31][3]
DRP[8] bit 8	MAIN[6][31][4]
DRP[8] bit 9	MAIN[6][30][4]
DRP[8] bit 10	MAIN[6][30][5]
DRP[8] bit 11	MAIN[6][31][5]
DRP[8] bit 12	MAIN[6][31][6]
DRP[8] bit 13	MAIN[6][30][6]
DRP[8] bit 14	MAIN[6][30][7]
DRP[8] bit 15	MAIN[6][31][7]
DRP[9] bit 0	MAIN[6][31][8]
DRP[9] bit 1	MAIN[6][30][8]
DRP[9] bit 2	MAIN[6][30][9]
DRP[9] bit 3	MAIN[6][31][9]
DRP[9] bit 4	MAIN[6][31][10]
DRP[9] bit 5	MAIN[6][30][10]
DRP[9] bit 6	MAIN[6][30][11]
DRP[9] bit 7	MAIN[6][31][11]
DRP[9] bit 8	MAIN[6][31][12]
DRP[9] bit 9	MAIN[6][30][12]
DRP[9] bit 10	MAIN[6][30][13]
DRP[9] bit 11	MAIN[6][31][13]
DRP[9] bit 12	MAIN[6][31][14]
DRP[9] bit 13	MAIN[6][30][14]
DRP[9] bit 14	MAIN[6][30][15]
DRP[9] bit 15	MAIN[6][31][15]
DRP[10] bit 0	MAIN[6][31][16]
DRP[10] bit 1	MAIN[6][30][16]
DRP[10] bit 2	MAIN[6][30][17]
DRP[10] bit 3	MAIN[6][31][17]
DRP[10] bit 4	MAIN[6][31][18]
DRP[10] bit 5	MAIN[6][30][18]
DRP[10] bit 6	MAIN[6][30][19]
DRP[10] bit 7	MAIN[6][31][19]
DRP[10] bit 8	MAIN[6][31][20]
DRP[10] bit 9	MAIN[6][30][20]
DRP[10] bit 10	MAIN[6][30][21]
DRP[10] bit 11	MAIN[6][31][21]
DRP[10] bit 12	MAIN[6][31][22]
DRP[10] bit 13	MAIN[6][30][22]
DRP[10] bit 14	MAIN[6][30][23]
DRP[10] bit 15	MAIN[6][31][23]
DRP[11] bit 0	MAIN[6][31][24]
DRP[11] bit 1	MAIN[6][30][24]
DRP[11] bit 2	MAIN[6][30][25]
DRP[11] bit 3	MAIN[6][31][25]
DRP[11] bit 4	MAIN[6][31][26]
DRP[11] bit 5	MAIN[6][30][26]
DRP[11] bit 6	MAIN[6][30][27]
DRP[11] bit 7	MAIN[6][31][27]
DRP[11] bit 8	MAIN[6][31][28]
DRP[11] bit 9	MAIN[6][30][28]
DRP[11] bit 10	MAIN[6][30][29]
DRP[11] bit 11	MAIN[6][31][29]
DRP[11] bit 12	MAIN[6][31][30]
DRP[11] bit 13	MAIN[6][30][30]
DRP[11] bit 14	MAIN[6][30][31]
DRP[11] bit 15	MAIN[6][31][31]
DRP[12] bit 0	MAIN[6][31][32]
DRP[12] bit 1	MAIN[6][30][32]
DRP[12] bit 2	MAIN[6][30][33]
DRP[12] bit 3	MAIN[6][31][33]
DRP[12] bit 4	MAIN[6][31][34]
DRP[12] bit 5	MAIN[6][30][34]
DRP[12] bit 6	MAIN[6][30][35]
DRP[12] bit 7	MAIN[6][31][35]
DRP[12] bit 8	MAIN[6][31][36]
DRP[12] bit 9	MAIN[6][30][36]
DRP[12] bit 10	MAIN[6][30][37]
DRP[12] bit 11	MAIN[6][31][37]
DRP[12] bit 12	MAIN[6][31][38]
DRP[12] bit 13	MAIN[6][30][38]
DRP[12] bit 14	MAIN[6][30][39]
DRP[12] bit 15	MAIN[6][31][39]
DRP[13] bit 0	MAIN[6][31][40]
DRP[13] bit 1	MAIN[6][30][40]
DRP[13] bit 2	MAIN[6][30][41]
DRP[13] bit 3	MAIN[6][31][41]
DRP[13] bit 4	MAIN[6][31][42]
DRP[13] bit 5	MAIN[6][30][42]
DRP[13] bit 6	MAIN[6][30][43]
DRP[13] bit 7	MAIN[6][31][43]
DRP[13] bit 8	MAIN[6][31][44]
DRP[13] bit 9	MAIN[6][30][44]
DRP[13] bit 10	MAIN[6][30][45]
DRP[13] bit 11	MAIN[6][31][45]
DRP[13] bit 12	MAIN[6][31][46]
DRP[13] bit 13	MAIN[6][30][46]
DRP[13] bit 14	MAIN[6][30][47]
DRP[13] bit 15	MAIN[6][31][47]
DRP[14] bit 0	MAIN[6][31][48]
DRP[14] bit 1	MAIN[6][30][48]
DRP[14] bit 2	MAIN[6][30][49]
DRP[14] bit 3	MAIN[6][31][49]
DRP[14] bit 4	MAIN[6][31][50]
DRP[14] bit 5	MAIN[6][30][50]
DRP[14] bit 6	MAIN[6][30][51]
DRP[14] bit 7	MAIN[6][31][51]
DRP[14] bit 8	MAIN[6][31][52]
DRP[14] bit 9	MAIN[6][30][52]
DRP[14] bit 10	MAIN[6][30][53]
DRP[14] bit 11	MAIN[6][31][53]
DRP[14] bit 12	MAIN[6][31][54]
DRP[14] bit 13	MAIN[6][30][54]
DRP[14] bit 14	MAIN[6][30][55]
DRP[14] bit 15	MAIN[6][31][55]
DRP[15] bit 0	MAIN[6][31][56]
DRP[15] bit 1	MAIN[6][30][56]
DRP[15] bit 2	MAIN[6][30][57]
DRP[15] bit 3	MAIN[6][31][57]
DRP[15] bit 4	MAIN[6][31][58]
DRP[15] bit 5	MAIN[6][30][58]
DRP[15] bit 6	MAIN[6][30][59]
DRP[15] bit 7	MAIN[6][31][59]
DRP[15] bit 8	MAIN[6][31][60]
DRP[15] bit 9	MAIN[6][30][60]
DRP[15] bit 10	MAIN[6][30][61]
DRP[15] bit 11	MAIN[6][31][61]
DRP[15] bit 12	MAIN[6][31][62]
DRP[15] bit 13	MAIN[6][30][62]
DRP[15] bit 14	MAIN[6][30][63]
DRP[15] bit 15	MAIN[6][31][63]
DRP[16] bit 0	MAIN[7][31][0]
DRP[16] bit 1	MAIN[7][30][0]
DRP[16] bit 2	MAIN[7][30][1]
DRP[16] bit 3	MAIN[7][31][1]
DRP[16] bit 4	MAIN[7][31][2]
DRP[16] bit 5	MAIN[7][30][2]
DRP[16] bit 6	MAIN[7][30][3]
DRP[16] bit 7	MAIN[7][31][3]
DRP[16] bit 8	MAIN[7][31][4]
DRP[16] bit 9	MAIN[7][30][4]
DRP[16] bit 10	MAIN[7][30][5]
DRP[16] bit 11	MAIN[7][31][5]
DRP[16] bit 12	MAIN[7][31][6]
DRP[16] bit 13	MAIN[7][30][6]
DRP[16] bit 14	MAIN[7][30][7]
DRP[16] bit 15	MAIN[7][31][7]
DRP[17] bit 0	MAIN[7][31][8]
DRP[17] bit 1	MAIN[7][30][8]
DRP[17] bit 2	MAIN[7][30][9]
DRP[17] bit 3	MAIN[7][31][9]
DRP[17] bit 4	MAIN[7][31][10]
DRP[17] bit 5	MAIN[7][30][10]
DRP[17] bit 6	MAIN[7][30][11]
DRP[17] bit 7	MAIN[7][31][11]
DRP[17] bit 8	MAIN[7][31][12]
DRP[17] bit 9	MAIN[7][30][12]
DRP[17] bit 10	MAIN[7][30][13]
DRP[17] bit 11	MAIN[7][31][13]
DRP[17] bit 12	MAIN[7][31][14]
DRP[17] bit 13	MAIN[7][30][14]
DRP[17] bit 14	MAIN[7][30][15]
DRP[17] bit 15	MAIN[7][31][15]
DRP[18] bit 0	MAIN[7][31][16]
DRP[18] bit 1	MAIN[7][30][16]
DRP[18] bit 2	MAIN[7][30][17]
DRP[18] bit 3	MAIN[7][31][17]
DRP[18] bit 4	MAIN[7][31][18]
DRP[18] bit 5	MAIN[7][30][18]
DRP[18] bit 6	MAIN[7][30][19]
DRP[18] bit 7	MAIN[7][31][19]
DRP[18] bit 8	MAIN[7][31][20]
DRP[18] bit 9	MAIN[7][30][20]
DRP[18] bit 10	MAIN[7][30][21]
DRP[18] bit 11	MAIN[7][31][21]
DRP[18] bit 12	MAIN[7][31][22]
DRP[18] bit 13	MAIN[7][30][22]
DRP[18] bit 14	MAIN[7][30][23]
DRP[18] bit 15	MAIN[7][31][23]
DRP[19] bit 0	MAIN[7][31][24]
DRP[19] bit 1	MAIN[7][30][24]
DRP[19] bit 2	MAIN[7][30][25]
DRP[19] bit 3	MAIN[7][31][25]
DRP[19] bit 4	MAIN[7][31][26]
DRP[19] bit 5	MAIN[7][30][26]
DRP[19] bit 6	MAIN[7][30][27]
DRP[19] bit 7	MAIN[7][31][27]
DRP[19] bit 8	MAIN[7][31][28]
DRP[19] bit 9	MAIN[7][30][28]
DRP[19] bit 10	MAIN[7][30][29]
DRP[19] bit 11	MAIN[7][31][29]
DRP[19] bit 12	MAIN[7][31][30]
DRP[19] bit 13	MAIN[7][30][30]
DRP[19] bit 14	MAIN[7][30][31]
DRP[19] bit 15	MAIN[7][31][31]
DRP[20] bit 0	MAIN[7][31][32]
DRP[20] bit 1	MAIN[7][30][32]
DRP[20] bit 2	MAIN[7][30][33]
DRP[20] bit 3	MAIN[7][31][33]
DRP[20] bit 4	MAIN[7][31][34]
DRP[20] bit 5	MAIN[7][30][34]
DRP[20] bit 6	MAIN[7][30][35]
DRP[20] bit 7	MAIN[7][31][35]
DRP[20] bit 8	MAIN[7][31][36]
DRP[20] bit 9	MAIN[7][30][36]
DRP[20] bit 10	MAIN[7][30][37]
DRP[20] bit 11	MAIN[7][31][37]
DRP[20] bit 12	MAIN[7][31][38]
DRP[20] bit 13	MAIN[7][30][38]
DRP[20] bit 14	MAIN[7][30][39]
DRP[20] bit 15	MAIN[7][31][39]
DRP[21] bit 0	MAIN[7][31][40]
DRP[21] bit 1	MAIN[7][30][40]
DRP[21] bit 2	MAIN[7][30][41]
DRP[21] bit 3	MAIN[7][31][41]
DRP[21] bit 4	MAIN[7][31][42]
DRP[21] bit 5	MAIN[7][30][42]
DRP[21] bit 6	MAIN[7][30][43]
DRP[21] bit 7	MAIN[7][31][43]
DRP[21] bit 8	MAIN[7][31][44]
DRP[21] bit 9	MAIN[7][30][44]
DRP[21] bit 10	MAIN[7][30][45]
DRP[21] bit 11	MAIN[7][31][45]
DRP[21] bit 12	MAIN[7][31][46]
DRP[21] bit 13	MAIN[7][30][46]
DRP[21] bit 14	MAIN[7][30][47]
DRP[21] bit 15	MAIN[7][31][47]
DRP[22] bit 0	MAIN[7][31][48]
DRP[22] bit 1	MAIN[7][30][48]
DRP[22] bit 2	MAIN[7][30][49]
DRP[22] bit 3	MAIN[7][31][49]
DRP[22] bit 4	MAIN[7][31][50]
DRP[22] bit 5	MAIN[7][30][50]
DRP[22] bit 6	MAIN[7][30][51]
DRP[22] bit 7	MAIN[7][31][51]
DRP[22] bit 8	MAIN[7][31][52]
DRP[22] bit 9	MAIN[7][30][52]
DRP[22] bit 10	MAIN[7][30][53]
DRP[22] bit 11	MAIN[7][31][53]
DRP[22] bit 12	MAIN[7][31][54]
DRP[22] bit 13	MAIN[7][30][54]
DRP[22] bit 14	MAIN[7][30][55]
DRP[22] bit 15	MAIN[7][31][55]
DRP[23] bit 0	MAIN[7][31][56]
DRP[23] bit 1	MAIN[7][30][56]
DRP[23] bit 2	MAIN[7][30][57]
DRP[23] bit 3	MAIN[7][31][57]
DRP[23] bit 4	MAIN[7][31][58]
DRP[23] bit 5	MAIN[7][30][58]
DRP[23] bit 6	MAIN[7][30][59]
DRP[23] bit 7	MAIN[7][31][59]
DRP[23] bit 8	MAIN[7][31][60]
DRP[23] bit 9	MAIN[7][30][60]
DRP[23] bit 10	MAIN[7][30][61]
DRP[23] bit 11	MAIN[7][31][61]
DRP[23] bit 12	MAIN[7][31][62]
DRP[23] bit 13	MAIN[7][30][62]
DRP[23] bit 14	MAIN[7][30][63]
DRP[23] bit 15	MAIN[7][31][63]
DRP[24] bit 0	MAIN[8][31][0]
DRP[24] bit 1	MAIN[8][30][0]
DRP[24] bit 2	MAIN[8][30][1]
DRP[24] bit 3	MAIN[8][31][1]
DRP[24] bit 4	MAIN[8][31][2]
DRP[24] bit 5	MAIN[8][30][2]
DRP[24] bit 6	MAIN[8][30][3]
DRP[24] bit 7	MAIN[8][31][3]
DRP[24] bit 8	MAIN[8][31][4]
DRP[24] bit 9	MAIN[8][30][4]
DRP[24] bit 10	MAIN[8][30][5]
DRP[24] bit 11	MAIN[8][31][5]
DRP[24] bit 12	MAIN[8][31][6]
DRP[24] bit 13	MAIN[8][30][6]
DRP[24] bit 14	MAIN[8][30][7]
DRP[24] bit 15	MAIN[8][31][7]
DRP[25] bit 0	MAIN[8][31][8]
DRP[25] bit 1	MAIN[8][30][8]
DRP[25] bit 2	MAIN[8][30][9]
DRP[25] bit 3	MAIN[8][31][9]
DRP[25] bit 4	MAIN[8][31][10]
DRP[25] bit 5	MAIN[8][30][10]
DRP[25] bit 6	MAIN[8][30][11]
DRP[25] bit 7	MAIN[8][31][11]
DRP[25] bit 8	MAIN[8][31][12]
DRP[25] bit 9	MAIN[8][30][12]
DRP[25] bit 10	MAIN[8][30][13]
DRP[25] bit 11	MAIN[8][31][13]
DRP[25] bit 12	MAIN[8][31][14]
DRP[25] bit 13	MAIN[8][30][14]
DRP[25] bit 14	MAIN[8][30][15]
DRP[25] bit 15	MAIN[8][31][15]
DRP[26] bit 0	MAIN[8][31][16]
DRP[26] bit 1	MAIN[8][30][16]
DRP[26] bit 2	MAIN[8][30][17]
DRP[26] bit 3	MAIN[8][31][17]
DRP[26] bit 4	MAIN[8][31][18]
DRP[26] bit 5	MAIN[8][30][18]
DRP[26] bit 6	MAIN[8][30][19]
DRP[26] bit 7	MAIN[8][31][19]
DRP[26] bit 8	MAIN[8][31][20]
DRP[26] bit 9	MAIN[8][30][20]
DRP[26] bit 10	MAIN[8][30][21]
DRP[26] bit 11	MAIN[8][31][21]
DRP[26] bit 12	MAIN[8][31][22]
DRP[26] bit 13	MAIN[8][30][22]
DRP[26] bit 14	MAIN[8][30][23]
DRP[26] bit 15	MAIN[8][31][23]
DRP[27] bit 0	MAIN[8][31][24]
DRP[27] bit 1	MAIN[8][30][24]
DRP[27] bit 2	MAIN[8][30][25]
DRP[27] bit 3	MAIN[8][31][25]
DRP[27] bit 4	MAIN[8][31][26]
DRP[27] bit 5	MAIN[8][30][26]
DRP[27] bit 6	MAIN[8][30][27]
DRP[27] bit 7	MAIN[8][31][27]
DRP[27] bit 8	MAIN[8][31][28]
DRP[27] bit 9	MAIN[8][30][28]
DRP[27] bit 10	MAIN[8][30][29]
DRP[27] bit 11	MAIN[8][31][29]
DRP[27] bit 12	MAIN[8][31][30]
DRP[27] bit 13	MAIN[8][30][30]
DRP[27] bit 14	MAIN[8][30][31]
DRP[27] bit 15	MAIN[8][31][31]
DRP[28] bit 0	MAIN[8][31][32]
DRP[28] bit 1	MAIN[8][30][32]
DRP[28] bit 2	MAIN[8][30][33]
DRP[28] bit 3	MAIN[8][31][33]
DRP[28] bit 4	MAIN[8][31][34]
DRP[28] bit 5	MAIN[8][30][34]
DRP[28] bit 6	MAIN[8][30][35]
DRP[28] bit 7	MAIN[8][31][35]
DRP[28] bit 8	MAIN[8][31][36]
DRP[28] bit 9	MAIN[8][30][36]
DRP[28] bit 10	MAIN[8][30][37]
DRP[28] bit 11	MAIN[8][31][37]
DRP[28] bit 12	MAIN[8][31][38]
DRP[28] bit 13	MAIN[8][30][38]
DRP[28] bit 14	MAIN[8][30][39]
DRP[28] bit 15	MAIN[8][31][39]
DRP[29] bit 0	MAIN[8][31][40]
DRP[29] bit 1	MAIN[8][30][40]
DRP[29] bit 2	MAIN[8][30][41]
DRP[29] bit 3	MAIN[8][31][41]
DRP[29] bit 4	MAIN[8][31][42]
DRP[29] bit 5	MAIN[8][30][42]
DRP[29] bit 6	MAIN[8][30][43]
DRP[29] bit 7	MAIN[8][31][43]
DRP[29] bit 8	MAIN[8][31][44]
DRP[29] bit 9	MAIN[8][30][44]
DRP[29] bit 10	MAIN[8][30][45]
DRP[29] bit 11	MAIN[8][31][45]
DRP[29] bit 12	MAIN[8][31][46]
DRP[29] bit 13	MAIN[8][30][46]
DRP[29] bit 14	MAIN[8][30][47]
DRP[29] bit 15	MAIN[8][31][47]
DRP[30] bit 0	MAIN[8][31][48]
DRP[30] bit 1	MAIN[8][30][48]
DRP[30] bit 2	MAIN[8][30][49]
DRP[30] bit 3	MAIN[8][31][49]
DRP[30] bit 4	MAIN[8][31][50]
DRP[30] bit 5	MAIN[8][30][50]
DRP[30] bit 6	MAIN[8][30][51]
DRP[30] bit 7	MAIN[8][31][51]
DRP[30] bit 8	MAIN[8][31][52]
DRP[30] bit 9	MAIN[8][30][52]
DRP[30] bit 10	MAIN[8][30][53]
DRP[30] bit 11	MAIN[8][31][53]
DRP[30] bit 12	MAIN[8][31][54]
DRP[30] bit 13	MAIN[8][30][54]
DRP[30] bit 14	MAIN[8][30][55]
DRP[30] bit 15	MAIN[8][31][55]
DRP[31] bit 0	MAIN[8][31][56]
DRP[31] bit 1	MAIN[8][30][56]
DRP[31] bit 2	MAIN[8][30][57]
DRP[31] bit 3	MAIN[8][31][57]
DRP[31] bit 4	MAIN[8][31][58]
DRP[31] bit 5	MAIN[8][30][58]
DRP[31] bit 6	MAIN[8][30][59]
DRP[31] bit 7	MAIN[8][31][59]
DRP[31] bit 8	MAIN[8][31][60]
DRP[31] bit 9	MAIN[8][30][60]
DRP[31] bit 10	MAIN[8][30][61]
DRP[31] bit 11	MAIN[8][31][61]
DRP[31] bit 12	MAIN[8][31][62]
DRP[31] bit 13	MAIN[8][30][62]
DRP[31] bit 14	MAIN[8][30][63]
DRP[31] bit 15	MAIN[8][31][63]
DRP[32] bit 0	MAIN[9][31][0]
DRP[32] bit 1	MAIN[9][30][0]
DRP[32] bit 2	MAIN[9][30][1]
DRP[32] bit 3	MAIN[9][31][1]
DRP[32] bit 4	MAIN[9][31][2]
DRP[32] bit 5	MAIN[9][30][2]
DRP[32] bit 6	MAIN[9][30][3]
DRP[32] bit 7	MAIN[9][31][3]
DRP[32] bit 8	MAIN[9][31][4]
DRP[32] bit 9	MAIN[9][30][4]
DRP[32] bit 10	MAIN[9][30][5]
DRP[32] bit 11	MAIN[9][31][5]
DRP[32] bit 12	MAIN[9][31][6]
DRP[32] bit 13	MAIN[9][30][6]
DRP[32] bit 14	MAIN[9][30][7]
DRP[32] bit 15	MAIN[9][31][7]
DRP[33] bit 0	MAIN[9][31][8]
DRP[33] bit 1	MAIN[9][30][8]
DRP[33] bit 2	MAIN[9][30][9]
DRP[33] bit 3	MAIN[9][31][9]
DRP[33] bit 4	MAIN[9][31][10]
DRP[33] bit 5	MAIN[9][30][10]
DRP[33] bit 6	MAIN[9][30][11]
DRP[33] bit 7	MAIN[9][31][11]
DRP[33] bit 8	MAIN[9][31][12]
DRP[33] bit 9	MAIN[9][30][12]
DRP[33] bit 10	MAIN[9][30][13]
DRP[33] bit 11	MAIN[9][31][13]
DRP[33] bit 12	MAIN[9][31][14]
DRP[33] bit 13	MAIN[9][30][14]
DRP[33] bit 14	MAIN[9][30][15]
DRP[33] bit 15	MAIN[9][31][15]
DRP[34] bit 0	MAIN[9][31][16]
DRP[34] bit 1	MAIN[9][30][16]
DRP[34] bit 2	MAIN[9][30][17]
DRP[34] bit 3	MAIN[9][31][17]
DRP[34] bit 4	MAIN[9][31][18]
DRP[34] bit 5	MAIN[9][30][18]
DRP[34] bit 6	MAIN[9][30][19]
DRP[34] bit 7	MAIN[9][31][19]
DRP[34] bit 8	MAIN[9][31][20]
DRP[34] bit 9	MAIN[9][30][20]
DRP[34] bit 10	MAIN[9][30][21]
DRP[34] bit 11	MAIN[9][31][21]
DRP[34] bit 12	MAIN[9][31][22]
DRP[34] bit 13	MAIN[9][30][22]
DRP[34] bit 14	MAIN[9][30][23]
DRP[34] bit 15	MAIN[9][31][23]
DRP[35] bit 0	MAIN[9][31][24]
DRP[35] bit 1	MAIN[9][30][24]
DRP[35] bit 2	MAIN[9][30][25]
DRP[35] bit 3	MAIN[9][31][25]
DRP[35] bit 4	MAIN[9][31][26]
DRP[35] bit 5	MAIN[9][30][26]
DRP[35] bit 6	MAIN[9][30][27]
DRP[35] bit 7	MAIN[9][31][27]
DRP[35] bit 8	MAIN[9][31][28]
DRP[35] bit 9	MAIN[9][30][28]
DRP[35] bit 10	MAIN[9][30][29]
DRP[35] bit 11	MAIN[9][31][29]
DRP[35] bit 12	MAIN[9][31][30]
DRP[35] bit 13	MAIN[9][30][30]
DRP[35] bit 14	MAIN[9][30][31]
DRP[35] bit 15	MAIN[9][31][31]
DRP[36] bit 0	MAIN[9][31][32]
DRP[36] bit 1	MAIN[9][30][32]
DRP[36] bit 2	MAIN[9][30][33]
DRP[36] bit 3	MAIN[9][31][33]
DRP[36] bit 4	MAIN[9][31][34]
DRP[36] bit 5	MAIN[9][30][34]
DRP[36] bit 6	MAIN[9][30][35]
DRP[36] bit 7	MAIN[9][31][35]
DRP[36] bit 8	MAIN[9][31][36]
DRP[36] bit 9	MAIN[9][30][36]
DRP[36] bit 10	MAIN[9][30][37]
DRP[36] bit 11	MAIN[9][31][37]
DRP[36] bit 12	MAIN[9][31][38]
DRP[36] bit 13	MAIN[9][30][38]
DRP[36] bit 14	MAIN[9][30][39]
DRP[36] bit 15	MAIN[9][31][39]
DRP[37] bit 0	MAIN[9][31][40]
DRP[37] bit 1	MAIN[9][30][40]
DRP[37] bit 2	MAIN[9][30][41]
DRP[37] bit 3	MAIN[9][31][41]
DRP[37] bit 4	MAIN[9][31][42]
DRP[37] bit 5	MAIN[9][30][42]
DRP[37] bit 6	MAIN[9][30][43]
DRP[37] bit 7	MAIN[9][31][43]
DRP[37] bit 8	MAIN[9][31][44]
DRP[37] bit 9	MAIN[9][30][44]
DRP[37] bit 10	MAIN[9][30][45]
DRP[37] bit 11	MAIN[9][31][45]
DRP[37] bit 12	MAIN[9][31][46]
DRP[37] bit 13	MAIN[9][30][46]
DRP[37] bit 14	MAIN[9][30][47]
DRP[37] bit 15	MAIN[9][31][47]
DRP[38] bit 0	MAIN[9][31][48]
DRP[38] bit 1	MAIN[9][30][48]
DRP[38] bit 2	MAIN[9][30][49]
DRP[38] bit 3	MAIN[9][31][49]
DRP[38] bit 4	MAIN[9][31][50]
DRP[38] bit 5	MAIN[9][30][50]
DRP[38] bit 6	MAIN[9][30][51]
DRP[38] bit 7	MAIN[9][31][51]
DRP[38] bit 8	MAIN[9][31][52]
DRP[38] bit 9	MAIN[9][30][52]
DRP[38] bit 10	MAIN[9][30][53]
DRP[38] bit 11	MAIN[9][31][53]
DRP[38] bit 12	MAIN[9][31][54]
DRP[38] bit 13	MAIN[9][30][54]
DRP[38] bit 14	MAIN[9][30][55]
DRP[38] bit 15	MAIN[9][31][55]
DRP[39] bit 0	MAIN[9][31][56]
DRP[39] bit 1	MAIN[9][30][56]
DRP[39] bit 2	MAIN[9][30][57]
DRP[39] bit 3	MAIN[9][31][57]
DRP[39] bit 4	MAIN[9][31][58]
DRP[39] bit 5	MAIN[9][30][58]
DRP[39] bit 6	MAIN[9][30][59]
DRP[39] bit 7	MAIN[9][31][59]
DRP[39] bit 8	MAIN[9][31][60]
DRP[39] bit 9	MAIN[9][30][60]
DRP[39] bit 10	MAIN[9][30][61]
DRP[39] bit 11	MAIN[9][31][61]
DRP[39] bit 12	MAIN[9][31][62]
DRP[39] bit 13	MAIN[9][30][62]
DRP[39] bit 14	MAIN[9][30][63]
DRP[39] bit 15	MAIN[9][31][63]
DRP[40] bit 0	MAIN[10][31][0]
DRP[40] bit 1	MAIN[10][30][0]
DRP[40] bit 2	MAIN[10][30][1]
DRP[40] bit 3	MAIN[10][31][1]
DRP[40] bit 4	MAIN[10][31][2]
DRP[40] bit 5	MAIN[10][30][2]
DRP[40] bit 6	MAIN[10][30][3]
DRP[40] bit 7	MAIN[10][31][3]
DRP[40] bit 8	MAIN[10][31][4]
DRP[40] bit 9	MAIN[10][30][4]
DRP[40] bit 10	MAIN[10][30][5]
DRP[40] bit 11	MAIN[10][31][5]
DRP[40] bit 12	MAIN[10][31][6]
DRP[40] bit 13	MAIN[10][30][6]
DRP[40] bit 14	MAIN[10][30][7]
DRP[40] bit 15	MAIN[10][31][7]
DRP[41] bit 0	MAIN[10][31][8]
DRP[41] bit 1	MAIN[10][30][8]
DRP[41] bit 2	MAIN[10][30][9]
DRP[41] bit 3	MAIN[10][31][9]
DRP[41] bit 4	MAIN[10][31][10]
DRP[41] bit 5	MAIN[10][30][10]
DRP[41] bit 6	MAIN[10][30][11]
DRP[41] bit 7	MAIN[10][31][11]
DRP[41] bit 8	MAIN[10][31][12]
DRP[41] bit 9	MAIN[10][30][12]
DRP[41] bit 10	MAIN[10][30][13]
DRP[41] bit 11	MAIN[10][31][13]
DRP[41] bit 12	MAIN[10][31][14]
DRP[41] bit 13	MAIN[10][30][14]
DRP[41] bit 14	MAIN[10][30][15]
DRP[41] bit 15	MAIN[10][31][15]
DRP[42] bit 0	MAIN[10][31][16]
DRP[42] bit 1	MAIN[10][30][16]
DRP[42] bit 2	MAIN[10][30][17]
DRP[42] bit 3	MAIN[10][31][17]
DRP[42] bit 4	MAIN[10][31][18]
DRP[42] bit 5	MAIN[10][30][18]
DRP[42] bit 6	MAIN[10][30][19]
DRP[42] bit 7	MAIN[10][31][19]
DRP[42] bit 8	MAIN[10][31][20]
DRP[42] bit 9	MAIN[10][30][20]
DRP[42] bit 10	MAIN[10][30][21]
DRP[42] bit 11	MAIN[10][31][21]
DRP[42] bit 12	MAIN[10][31][22]
DRP[42] bit 13	MAIN[10][30][22]
DRP[42] bit 14	MAIN[10][30][23]
DRP[42] bit 15	MAIN[10][31][23]
DRP[43] bit 0	MAIN[10][31][24]
DRP[43] bit 1	MAIN[10][30][24]
DRP[43] bit 2	MAIN[10][30][25]
DRP[43] bit 3	MAIN[10][31][25]
DRP[43] bit 4	MAIN[10][31][26]
DRP[43] bit 5	MAIN[10][30][26]
DRP[43] bit 6	MAIN[10][30][27]
DRP[43] bit 7	MAIN[10][31][27]
DRP[43] bit 8	MAIN[10][31][28]
DRP[43] bit 9	MAIN[10][30][28]
DRP[43] bit 10	MAIN[10][30][29]
DRP[43] bit 11	MAIN[10][31][29]
DRP[43] bit 12	MAIN[10][31][30]
DRP[43] bit 13	MAIN[10][30][30]
DRP[43] bit 14	MAIN[10][30][31]
DRP[43] bit 15	MAIN[10][31][31]
DRP[44] bit 0	MAIN[10][31][32]
DRP[44] bit 1	MAIN[10][30][32]
DRP[44] bit 2	MAIN[10][30][33]
DRP[44] bit 3	MAIN[10][31][33]
DRP[44] bit 4	MAIN[10][31][34]
DRP[44] bit 5	MAIN[10][30][34]
DRP[44] bit 6	MAIN[10][30][35]
DRP[44] bit 7	MAIN[10][31][35]
DRP[44] bit 8	MAIN[10][31][36]
DRP[44] bit 9	MAIN[10][30][36]
DRP[44] bit 10	MAIN[10][30][37]
DRP[44] bit 11	MAIN[10][31][37]
DRP[44] bit 12	MAIN[10][31][38]
DRP[44] bit 13	MAIN[10][30][38]
DRP[44] bit 14	MAIN[10][30][39]
DRP[44] bit 15	MAIN[10][31][39]
DRP[45] bit 0	MAIN[10][31][40]
DRP[45] bit 1	MAIN[10][30][40]
DRP[45] bit 2	MAIN[10][30][41]
DRP[45] bit 3	MAIN[10][31][41]
DRP[45] bit 4	MAIN[10][31][42]
DRP[45] bit 5	MAIN[10][30][42]
DRP[45] bit 6	MAIN[10][30][43]
DRP[45] bit 7	MAIN[10][31][43]
DRP[45] bit 8	MAIN[10][31][44]
DRP[45] bit 9	MAIN[10][30][44]
DRP[45] bit 10	MAIN[10][30][45]
DRP[45] bit 11	MAIN[10][31][45]
DRP[45] bit 12	MAIN[10][31][46]
DRP[45] bit 13	MAIN[10][30][46]
DRP[45] bit 14	MAIN[10][30][47]
DRP[45] bit 15	MAIN[10][31][47]
DRP[46] bit 0	MAIN[10][31][48]
DRP[46] bit 1	MAIN[10][30][48]
DRP[46] bit 2	MAIN[10][30][49]
DRP[46] bit 3	MAIN[10][31][49]
DRP[46] bit 4	MAIN[10][31][50]
DRP[46] bit 5	MAIN[10][30][50]
DRP[46] bit 6	MAIN[10][30][51]
DRP[46] bit 7	MAIN[10][31][51]
DRP[46] bit 8	MAIN[10][31][52]
DRP[46] bit 9	MAIN[10][30][52]
DRP[46] bit 10	MAIN[10][30][53]
DRP[46] bit 11	MAIN[10][31][53]
DRP[46] bit 12	MAIN[10][31][54]
DRP[46] bit 13	MAIN[10][30][54]
DRP[46] bit 14	MAIN[10][30][55]
DRP[46] bit 15	MAIN[10][31][55]
DRP[47] bit 0	MAIN[10][31][56]
DRP[47] bit 1	MAIN[10][30][56]
DRP[47] bit 2	MAIN[10][30][57]
DRP[47] bit 3	MAIN[10][31][57]
DRP[47] bit 4	MAIN[10][31][58]
DRP[47] bit 5	MAIN[10][30][58]
DRP[47] bit 6	MAIN[10][30][59]
DRP[47] bit 7	MAIN[10][31][59]
DRP[47] bit 8	MAIN[10][31][60]
DRP[47] bit 9	MAIN[10][30][60]
DRP[47] bit 10	MAIN[10][30][61]
DRP[47] bit 11	MAIN[10][31][61]
DRP[47] bit 12	MAIN[10][31][62]
DRP[47] bit 13	MAIN[10][30][62]
DRP[47] bit 14	MAIN[10][30][63]
DRP[47] bit 15	MAIN[10][31][63]
DRP[48] bit 0	MAIN[11][31][0]
DRP[48] bit 1	MAIN[11][30][0]
DRP[48] bit 2	MAIN[11][30][1]
DRP[48] bit 3	MAIN[11][31][1]
DRP[48] bit 4	MAIN[11][31][2]
DRP[48] bit 5	MAIN[11][30][2]
DRP[48] bit 6	MAIN[11][30][3]
DRP[48] bit 7	MAIN[11][31][3]
DRP[48] bit 8	MAIN[11][31][4]
DRP[48] bit 9	MAIN[11][30][4]
DRP[48] bit 10	MAIN[11][30][5]
DRP[48] bit 11	MAIN[11][31][5]
DRP[48] bit 12	MAIN[11][31][6]
DRP[48] bit 13	MAIN[11][30][6]
DRP[48] bit 14	MAIN[11][30][7]
DRP[48] bit 15	MAIN[11][31][7]
DRP[49] bit 0	MAIN[11][31][8]
DRP[49] bit 1	MAIN[11][30][8]
DRP[49] bit 2	MAIN[11][30][9]
DRP[49] bit 3	MAIN[11][31][9]
DRP[49] bit 4	MAIN[11][31][10]
DRP[49] bit 5	MAIN[11][30][10]
DRP[49] bit 6	MAIN[11][30][11]
DRP[49] bit 7	MAIN[11][31][11]
DRP[49] bit 8	MAIN[11][31][12]
DRP[49] bit 9	MAIN[11][30][12]
DRP[49] bit 10	MAIN[11][30][13]
DRP[49] bit 11	MAIN[11][31][13]
DRP[49] bit 12	MAIN[11][31][14]
DRP[49] bit 13	MAIN[11][30][14]
DRP[49] bit 14	MAIN[11][30][15]
DRP[49] bit 15	MAIN[11][31][15]
DRP[50] bit 0	MAIN[11][31][16]
DRP[50] bit 1	MAIN[11][30][16]
DRP[50] bit 2	MAIN[11][30][17]
DRP[50] bit 3	MAIN[11][31][17]
DRP[50] bit 4	MAIN[11][31][18]
DRP[50] bit 5	MAIN[11][30][18]
DRP[50] bit 6	MAIN[11][30][19]
DRP[50] bit 7	MAIN[11][31][19]
DRP[50] bit 8	MAIN[11][31][20]
DRP[50] bit 9	MAIN[11][30][20]
DRP[50] bit 10	MAIN[11][30][21]
DRP[50] bit 11	MAIN[11][31][21]
DRP[50] bit 12	MAIN[11][31][22]
DRP[50] bit 13	MAIN[11][30][22]
DRP[50] bit 14	MAIN[11][30][23]
DRP[50] bit 15	MAIN[11][31][23]
DRP[51] bit 0	MAIN[11][31][24]
DRP[51] bit 1	MAIN[11][30][24]
DRP[51] bit 2	MAIN[11][30][25]
DRP[51] bit 3	MAIN[11][31][25]
DRP[51] bit 4	MAIN[11][31][26]
DRP[51] bit 5	MAIN[11][30][26]
DRP[51] bit 6	MAIN[11][30][27]
DRP[51] bit 7	MAIN[11][31][27]
DRP[51] bit 8	MAIN[11][31][28]
DRP[51] bit 9	MAIN[11][30][28]
DRP[51] bit 10	MAIN[11][30][29]
DRP[51] bit 11	MAIN[11][31][29]
DRP[51] bit 12	MAIN[11][31][30]
DRP[51] bit 13	MAIN[11][30][30]
DRP[51] bit 14	MAIN[11][30][31]
DRP[51] bit 15	MAIN[11][31][31]
DRP[52] bit 0	MAIN[11][31][32]
DRP[52] bit 1	MAIN[11][30][32]
DRP[52] bit 2	MAIN[11][30][33]
DRP[52] bit 3	MAIN[11][31][33]
DRP[52] bit 4	MAIN[11][31][34]
DRP[52] bit 5	MAIN[11][30][34]
DRP[52] bit 6	MAIN[11][30][35]
DRP[52] bit 7	MAIN[11][31][35]
DRP[52] bit 8	MAIN[11][31][36]
DRP[52] bit 9	MAIN[11][30][36]
DRP[52] bit 10	MAIN[11][30][37]
DRP[52] bit 11	MAIN[11][31][37]
DRP[52] bit 12	MAIN[11][31][38]
DRP[52] bit 13	MAIN[11][30][38]
DRP[52] bit 14	MAIN[11][30][39]
DRP[52] bit 15	MAIN[11][31][39]
DRP[53] bit 0	MAIN[11][31][40]
DRP[53] bit 1	MAIN[11][30][40]
DRP[53] bit 2	MAIN[11][30][41]
DRP[53] bit 3	MAIN[11][31][41]
DRP[53] bit 4	MAIN[11][31][42]
DRP[53] bit 5	MAIN[11][30][42]
DRP[53] bit 6	MAIN[11][30][43]
DRP[53] bit 7	MAIN[11][31][43]
DRP[53] bit 8	MAIN[11][31][44]
DRP[53] bit 9	MAIN[11][30][44]
DRP[53] bit 10	MAIN[11][30][45]
DRP[53] bit 11	MAIN[11][31][45]
DRP[53] bit 12	MAIN[11][31][46]
DRP[53] bit 13	MAIN[11][30][46]
DRP[53] bit 14	MAIN[11][30][47]
DRP[53] bit 15	MAIN[11][31][47]
DRP[54] bit 0	MAIN[11][31][48]
DRP[54] bit 1	MAIN[11][30][48]
DRP[54] bit 2	MAIN[11][30][49]
DRP[54] bit 3	MAIN[11][31][49]
DRP[54] bit 4	MAIN[11][31][50]
DRP[54] bit 5	MAIN[11][30][50]
DRP[54] bit 6	MAIN[11][30][51]
DRP[54] bit 7	MAIN[11][31][51]
DRP[54] bit 8	MAIN[11][31][52]
DRP[54] bit 9	MAIN[11][30][52]
DRP[54] bit 10	MAIN[11][30][53]
DRP[54] bit 11	MAIN[11][31][53]
DRP[54] bit 12	MAIN[11][31][54]
DRP[54] bit 13	MAIN[11][30][54]
DRP[54] bit 14	MAIN[11][30][55]
DRP[54] bit 15	MAIN[11][31][55]
DRP[55] bit 0	MAIN[11][31][56]
DRP[55] bit 1	MAIN[11][30][56]
DRP[55] bit 2	MAIN[11][30][57]
DRP[55] bit 3	MAIN[11][31][57]
DRP[55] bit 4	MAIN[11][31][58]
DRP[55] bit 5	MAIN[11][30][58]
DRP[55] bit 6	MAIN[11][30][59]
DRP[55] bit 7	MAIN[11][31][59]
DRP[55] bit 8	MAIN[11][31][60]
DRP[55] bit 9	MAIN[11][30][60]
DRP[55] bit 10	MAIN[11][30][61]
DRP[55] bit 11	MAIN[11][31][61]
DRP[55] bit 12	MAIN[11][31][62]
DRP[55] bit 13	MAIN[11][30][62]
DRP[55] bit 14	MAIN[11][30][63]
DRP[55] bit 15	MAIN[11][31][63]
DRP[56] bit 0	MAIN[12][31][0]
DRP[56] bit 1	MAIN[12][30][0]
DRP[56] bit 2	MAIN[12][30][1]
DRP[56] bit 3	MAIN[12][31][1]
DRP[56] bit 4	MAIN[12][31][2]
DRP[56] bit 5	MAIN[12][30][2]
DRP[56] bit 6	MAIN[12][30][3]
DRP[56] bit 7	MAIN[12][31][3]
DRP[56] bit 8	MAIN[12][31][4]
DRP[56] bit 9	MAIN[12][30][4]
DRP[56] bit 10	MAIN[12][30][5]
DRP[56] bit 11	MAIN[12][31][5]
DRP[56] bit 12	MAIN[12][31][6]
DRP[56] bit 13	MAIN[12][30][6]
DRP[56] bit 14	MAIN[12][30][7]
DRP[56] bit 15	MAIN[12][31][7]
DRP[57] bit 0	MAIN[12][31][8]
DRP[57] bit 1	MAIN[12][30][8]
DRP[57] bit 2	MAIN[12][30][9]
DRP[57] bit 3	MAIN[12][31][9]
DRP[57] bit 4	MAIN[12][31][10]
DRP[57] bit 5	MAIN[12][30][10]
DRP[57] bit 6	MAIN[12][30][11]
DRP[57] bit 7	MAIN[12][31][11]
DRP[57] bit 8	MAIN[12][31][12]
DRP[57] bit 9	MAIN[12][30][12]
DRP[57] bit 10	MAIN[12][30][13]
DRP[57] bit 11	MAIN[12][31][13]
DRP[57] bit 12	MAIN[12][31][14]
DRP[57] bit 13	MAIN[12][30][14]
DRP[57] bit 14	MAIN[12][30][15]
DRP[57] bit 15	MAIN[12][31][15]
DRP[58] bit 0	MAIN[12][31][16]
DRP[58] bit 1	MAIN[12][30][16]
DRP[58] bit 2	MAIN[12][30][17]
DRP[58] bit 3	MAIN[12][31][17]
DRP[58] bit 4	MAIN[12][31][18]
DRP[58] bit 5	MAIN[12][30][18]
DRP[58] bit 6	MAIN[12][30][19]
DRP[58] bit 7	MAIN[12][31][19]
DRP[58] bit 8	MAIN[12][31][20]
DRP[58] bit 9	MAIN[12][30][20]
DRP[58] bit 10	MAIN[12][30][21]
DRP[58] bit 11	MAIN[12][31][21]
DRP[58] bit 12	MAIN[12][31][22]
DRP[58] bit 13	MAIN[12][30][22]
DRP[58] bit 14	MAIN[12][30][23]
DRP[58] bit 15	MAIN[12][31][23]
DRP[59] bit 0	MAIN[12][31][24]
DRP[59] bit 1	MAIN[12][30][24]
DRP[59] bit 2	MAIN[12][30][25]
DRP[59] bit 3	MAIN[12][31][25]
DRP[59] bit 4	MAIN[12][31][26]
DRP[59] bit 5	MAIN[12][30][26]
DRP[59] bit 6	MAIN[12][30][27]
DRP[59] bit 7	MAIN[12][31][27]
DRP[59] bit 8	MAIN[12][31][28]
DRP[59] bit 9	MAIN[12][30][28]
DRP[59] bit 10	MAIN[12][30][29]
DRP[59] bit 11	MAIN[12][31][29]
DRP[59] bit 12	MAIN[12][31][30]
DRP[59] bit 13	MAIN[12][30][30]
DRP[59] bit 14	MAIN[12][30][31]
DRP[59] bit 15	MAIN[12][31][31]
DRP[60] bit 0	MAIN[12][31][32]
DRP[60] bit 1	MAIN[12][30][32]
DRP[60] bit 2	MAIN[12][30][33]
DRP[60] bit 3	MAIN[12][31][33]
DRP[60] bit 4	MAIN[12][31][34]
DRP[60] bit 5	MAIN[12][30][34]
DRP[60] bit 6	MAIN[12][30][35]
DRP[60] bit 7	MAIN[12][31][35]
DRP[60] bit 8	MAIN[12][31][36]
DRP[60] bit 9	MAIN[12][30][36]
DRP[60] bit 10	MAIN[12][30][37]
DRP[60] bit 11	MAIN[12][31][37]
DRP[60] bit 12	MAIN[12][31][38]
DRP[60] bit 13	MAIN[12][30][38]
DRP[60] bit 14	MAIN[12][30][39]
DRP[60] bit 15	MAIN[12][31][39]
DRP[61] bit 0	MAIN[12][31][40]
DRP[61] bit 1	MAIN[12][30][40]
DRP[61] bit 2	MAIN[12][30][41]
DRP[61] bit 3	MAIN[12][31][41]
DRP[61] bit 4	MAIN[12][31][42]
DRP[61] bit 5	MAIN[12][30][42]
DRP[61] bit 6	MAIN[12][30][43]
DRP[61] bit 7	MAIN[12][31][43]
DRP[61] bit 8	MAIN[12][31][44]
DRP[61] bit 9	MAIN[12][30][44]
DRP[61] bit 10	MAIN[12][30][45]
DRP[61] bit 11	MAIN[12][31][45]
DRP[61] bit 12	MAIN[12][31][46]
DRP[61] bit 13	MAIN[12][30][46]
DRP[61] bit 14	MAIN[12][30][47]
DRP[61] bit 15	MAIN[12][31][47]
DRP[62] bit 0	MAIN[12][31][48]
DRP[62] bit 1	MAIN[12][30][48]
DRP[62] bit 2	MAIN[12][30][49]
DRP[62] bit 3	MAIN[12][31][49]
DRP[62] bit 4	MAIN[12][31][50]
DRP[62] bit 5	MAIN[12][30][50]
DRP[62] bit 6	MAIN[12][30][51]
DRP[62] bit 7	MAIN[12][31][51]
DRP[62] bit 8	MAIN[12][31][52]
DRP[62] bit 9	MAIN[12][30][52]
DRP[62] bit 10	MAIN[12][30][53]
DRP[62] bit 11	MAIN[12][31][53]
DRP[62] bit 12	MAIN[12][31][54]
DRP[62] bit 13	MAIN[12][30][54]
DRP[62] bit 14	MAIN[12][30][55]
DRP[62] bit 15	MAIN[12][31][55]
DRP[63] bit 0	MAIN[12][31][56]
DRP[63] bit 1	MAIN[12][30][56]
DRP[63] bit 2	MAIN[12][30][57]
DRP[63] bit 3	MAIN[12][31][57]
DRP[63] bit 4	MAIN[12][31][58]
DRP[63] bit 5	MAIN[12][30][58]
DRP[63] bit 6	MAIN[12][30][59]
DRP[63] bit 7	MAIN[12][31][59]
DRP[63] bit 8	MAIN[12][31][60]
DRP[63] bit 9	MAIN[12][30][60]
DRP[63] bit 10	MAIN[12][30][61]
DRP[63] bit 11	MAIN[12][31][61]
DRP[63] bit 12	MAIN[12][31][62]
DRP[63] bit 13	MAIN[12][30][62]
DRP[63] bit 14	MAIN[12][30][63]
DRP[63] bit 15	MAIN[12][31][63]
DRP[64] bit 0	MAIN[13][31][0]
DRP[64] bit 1	MAIN[13][30][0]
DRP[64] bit 2	MAIN[13][30][1]
DRP[64] bit 3	MAIN[13][31][1]
DRP[64] bit 4	MAIN[13][31][2]
DRP[64] bit 5	MAIN[13][30][2]
DRP[64] bit 6	MAIN[13][30][3]
DRP[64] bit 7	MAIN[13][31][3]
DRP[64] bit 8	MAIN[13][31][4]
DRP[64] bit 9	MAIN[13][30][4]
DRP[64] bit 10	MAIN[13][30][5]
DRP[64] bit 11	MAIN[13][31][5]
DRP[64] bit 12	MAIN[13][31][6]
DRP[64] bit 13	MAIN[13][30][6]
DRP[64] bit 14	MAIN[13][30][7]
DRP[64] bit 15	MAIN[13][31][7]
DRP[65] bit 0	MAIN[13][31][8]
DRP[65] bit 1	MAIN[13][30][8]
DRP[65] bit 2	MAIN[13][30][9]
DRP[65] bit 3	MAIN[13][31][9]
DRP[65] bit 4	MAIN[13][31][10]
DRP[65] bit 5	MAIN[13][30][10]
DRP[65] bit 6	MAIN[13][30][11]
DRP[65] bit 7	MAIN[13][31][11]
DRP[65] bit 8	MAIN[13][31][12]
DRP[65] bit 9	MAIN[13][30][12]
DRP[65] bit 10	MAIN[13][30][13]
DRP[65] bit 11	MAIN[13][31][13]
DRP[65] bit 12	MAIN[13][31][14]
DRP[65] bit 13	MAIN[13][30][14]
DRP[65] bit 14	MAIN[13][30][15]
DRP[65] bit 15	MAIN[13][31][15]
DRP[66] bit 0	MAIN[13][31][16]
DRP[66] bit 1	MAIN[13][30][16]
DRP[66] bit 2	MAIN[13][30][17]
DRP[66] bit 3	MAIN[13][31][17]
DRP[66] bit 4	MAIN[13][31][18]
DRP[66] bit 5	MAIN[13][30][18]
DRP[66] bit 6	MAIN[13][30][19]
DRP[66] bit 7	MAIN[13][31][19]
DRP[66] bit 8	MAIN[13][31][20]
DRP[66] bit 9	MAIN[13][30][20]
DRP[66] bit 10	MAIN[13][30][21]
DRP[66] bit 11	MAIN[13][31][21]
DRP[66] bit 12	MAIN[13][31][22]
DRP[66] bit 13	MAIN[13][30][22]
DRP[66] bit 14	MAIN[13][30][23]
DRP[66] bit 15	MAIN[13][31][23]
DRP[67] bit 0	MAIN[13][31][24]
DRP[67] bit 1	MAIN[13][30][24]
DRP[67] bit 2	MAIN[13][30][25]
DRP[67] bit 3	MAIN[13][31][25]
DRP[67] bit 4	MAIN[13][31][26]
DRP[67] bit 5	MAIN[13][30][26]
DRP[67] bit 6	MAIN[13][30][27]
DRP[67] bit 7	MAIN[13][31][27]
DRP[67] bit 8	MAIN[13][31][28]
DRP[67] bit 9	MAIN[13][30][28]
DRP[67] bit 10	MAIN[13][30][29]
DRP[67] bit 11	MAIN[13][31][29]
DRP[67] bit 12	MAIN[13][31][30]
DRP[67] bit 13	MAIN[13][30][30]
DRP[67] bit 14	MAIN[13][30][31]
DRP[67] bit 15	MAIN[13][31][31]
DRP[68] bit 0	MAIN[13][31][32]
DRP[68] bit 1	MAIN[13][30][32]
DRP[68] bit 2	MAIN[13][30][33]
DRP[68] bit 3	MAIN[13][31][33]
DRP[68] bit 4	MAIN[13][31][34]
DRP[68] bit 5	MAIN[13][30][34]
DRP[68] bit 6	MAIN[13][30][35]
DRP[68] bit 7	MAIN[13][31][35]
DRP[68] bit 8	MAIN[13][31][36]
DRP[68] bit 9	MAIN[13][30][36]
DRP[68] bit 10	MAIN[13][30][37]
DRP[68] bit 11	MAIN[13][31][37]
DRP[68] bit 12	MAIN[13][31][38]
DRP[68] bit 13	MAIN[13][30][38]
DRP[68] bit 14	MAIN[13][30][39]
DRP[68] bit 15	MAIN[13][31][39]
DRP[69] bit 0	MAIN[13][31][40]
DRP[69] bit 1	MAIN[13][30][40]
DRP[69] bit 2	MAIN[13][30][41]
DRP[69] bit 3	MAIN[13][31][41]
DRP[69] bit 4	MAIN[13][31][42]
DRP[69] bit 5	MAIN[13][30][42]
DRP[69] bit 6	MAIN[13][30][43]
DRP[69] bit 7	MAIN[13][31][43]
DRP[69] bit 8	MAIN[13][31][44]
DRP[69] bit 9	MAIN[13][30][44]
DRP[69] bit 10	MAIN[13][30][45]
DRP[69] bit 11	MAIN[13][31][45]
DRP[69] bit 12	MAIN[13][31][46]
DRP[69] bit 13	MAIN[13][30][46]
DRP[69] bit 14	MAIN[13][30][47]
DRP[69] bit 15	MAIN[13][31][47]
DRP[70] bit 0	MAIN[13][31][48]
DRP[70] bit 1	MAIN[13][30][48]
DRP[70] bit 2	MAIN[13][30][49]
DRP[70] bit 3	MAIN[13][31][49]
DRP[70] bit 4	MAIN[13][31][50]
DRP[70] bit 5	MAIN[13][30][50]
DRP[70] bit 6	MAIN[13][30][51]
DRP[70] bit 7	MAIN[13][31][51]
DRP[70] bit 8	MAIN[13][31][52]
DRP[70] bit 9	MAIN[13][30][52]
DRP[70] bit 10	MAIN[13][30][53]
DRP[70] bit 11	MAIN[13][31][53]
DRP[70] bit 12	MAIN[13][31][54]
DRP[70] bit 13	MAIN[13][30][54]
DRP[70] bit 14	MAIN[13][30][55]
DRP[70] bit 15	MAIN[13][31][55]
DRP[71] bit 0	MAIN[13][31][56]
DRP[71] bit 1	MAIN[13][30][56]
DRP[71] bit 2	MAIN[13][30][57]
DRP[71] bit 3	MAIN[13][31][57]
DRP[71] bit 4	MAIN[13][31][58]
DRP[71] bit 5	MAIN[13][30][58]
DRP[71] bit 6	MAIN[13][30][59]
DRP[71] bit 7	MAIN[13][31][59]
DRP[71] bit 8	MAIN[13][31][60]
DRP[71] bit 9	MAIN[13][30][60]
DRP[71] bit 10	MAIN[13][30][61]
DRP[71] bit 11	MAIN[13][31][61]
DRP[71] bit 12	MAIN[13][31][62]
DRP[71] bit 13	MAIN[13][30][62]
DRP[71] bit 14	MAIN[13][30][63]
DRP[71] bit 15	MAIN[13][31][63]
DRP[72] bit 0	MAIN[14][31][0]
DRP[72] bit 1	MAIN[14][30][0]
DRP[72] bit 2	MAIN[14][30][1]
DRP[72] bit 3	MAIN[14][31][1]
DRP[72] bit 4	MAIN[14][31][2]
DRP[72] bit 5	MAIN[14][30][2]
DRP[72] bit 6	MAIN[14][30][3]
DRP[72] bit 7	MAIN[14][31][3]
DRP[72] bit 8	MAIN[14][31][4]
DRP[72] bit 9	MAIN[14][30][4]
DRP[72] bit 10	MAIN[14][30][5]
DRP[72] bit 11	MAIN[14][31][5]
DRP[72] bit 12	MAIN[14][31][6]
DRP[72] bit 13	MAIN[14][30][6]
DRP[72] bit 14	MAIN[14][30][7]
DRP[72] bit 15	MAIN[14][31][7]
DRP[73] bit 0	MAIN[14][31][8]
DRP[73] bit 1	MAIN[14][30][8]
DRP[73] bit 2	MAIN[14][30][9]
DRP[73] bit 3	MAIN[14][31][9]
DRP[73] bit 4	MAIN[14][31][10]
DRP[73] bit 5	MAIN[14][30][10]
DRP[73] bit 6	MAIN[14][30][11]
DRP[73] bit 7	MAIN[14][31][11]
DRP[73] bit 8	MAIN[14][31][12]
DRP[73] bit 9	MAIN[14][30][12]
DRP[73] bit 10	MAIN[14][30][13]
DRP[73] bit 11	MAIN[14][31][13]
DRP[73] bit 12	MAIN[14][31][14]
DRP[73] bit 13	MAIN[14][30][14]
DRP[73] bit 14	MAIN[14][30][15]
DRP[73] bit 15	MAIN[14][31][15]
DRP[74] bit 0	MAIN[14][31][16]
DRP[74] bit 1	MAIN[14][30][16]
DRP[74] bit 2	MAIN[14][30][17]
DRP[74] bit 3	MAIN[14][31][17]
DRP[74] bit 4	MAIN[14][31][18]
DRP[74] bit 5	MAIN[14][30][18]
DRP[74] bit 6	MAIN[14][30][19]
DRP[74] bit 7	MAIN[14][31][19]
DRP[74] bit 8	MAIN[14][31][20]
DRP[74] bit 9	MAIN[14][30][20]
DRP[74] bit 10	MAIN[14][30][21]
DRP[74] bit 11	MAIN[14][31][21]
DRP[74] bit 12	MAIN[14][31][22]
DRP[74] bit 13	MAIN[14][30][22]
DRP[74] bit 14	MAIN[14][30][23]
DRP[74] bit 15	MAIN[14][31][23]
DRP[75] bit 0	MAIN[14][31][24]
DRP[75] bit 1	MAIN[14][30][24]
DRP[75] bit 2	MAIN[14][30][25]
DRP[75] bit 3	MAIN[14][31][25]
DRP[75] bit 4	MAIN[14][31][26]
DRP[75] bit 5	MAIN[14][30][26]
DRP[75] bit 6	MAIN[14][30][27]
DRP[75] bit 7	MAIN[14][31][27]
DRP[75] bit 8	MAIN[14][31][28]
DRP[75] bit 9	MAIN[14][30][28]
DRP[75] bit 10	MAIN[14][30][29]
DRP[75] bit 11	MAIN[14][31][29]
DRP[75] bit 12	MAIN[14][31][30]
DRP[75] bit 13	MAIN[14][30][30]
DRP[75] bit 14	MAIN[14][30][31]
DRP[75] bit 15	MAIN[14][31][31]
DRP[76] bit 0	MAIN[14][31][32]
DRP[76] bit 1	MAIN[14][30][32]
DRP[76] bit 2	MAIN[14][30][33]
DRP[76] bit 3	MAIN[14][31][33]
DRP[76] bit 4	MAIN[14][31][34]
DRP[76] bit 5	MAIN[14][30][34]
DRP[76] bit 6	MAIN[14][30][35]
DRP[76] bit 7	MAIN[14][31][35]
DRP[76] bit 8	MAIN[14][31][36]
DRP[76] bit 9	MAIN[14][30][36]
DRP[76] bit 10	MAIN[14][30][37]
DRP[76] bit 11	MAIN[14][31][37]
DRP[76] bit 12	MAIN[14][31][38]
DRP[76] bit 13	MAIN[14][30][38]
DRP[76] bit 14	MAIN[14][30][39]
DRP[76] bit 15	MAIN[14][31][39]
DRP[77] bit 0	MAIN[14][31][40]
DRP[77] bit 1	MAIN[14][30][40]
DRP[77] bit 2	MAIN[14][30][41]
DRP[77] bit 3	MAIN[14][31][41]
DRP[77] bit 4	MAIN[14][31][42]
DRP[77] bit 5	MAIN[14][30][42]
DRP[77] bit 6	MAIN[14][30][43]
DRP[77] bit 7	MAIN[14][31][43]
DRP[77] bit 8	MAIN[14][31][44]
DRP[77] bit 9	MAIN[14][30][44]
DRP[77] bit 10	MAIN[14][30][45]
DRP[77] bit 11	MAIN[14][31][45]
DRP[77] bit 12	MAIN[14][31][46]
DRP[77] bit 13	MAIN[14][30][46]
DRP[77] bit 14	MAIN[14][30][47]
DRP[77] bit 15	MAIN[14][31][47]
DRP[78] bit 0	MAIN[14][31][48]
DRP[78] bit 1	MAIN[14][30][48]
DRP[78] bit 2	MAIN[14][30][49]
DRP[78] bit 3	MAIN[14][31][49]
DRP[78] bit 4	MAIN[14][31][50]
DRP[78] bit 5	MAIN[14][30][50]
DRP[78] bit 6	MAIN[14][30][51]
DRP[78] bit 7	MAIN[14][31][51]
DRP[78] bit 8	MAIN[14][31][52]
DRP[78] bit 9	MAIN[14][30][52]
DRP[78] bit 10	MAIN[14][30][53]
DRP[78] bit 11	MAIN[14][31][53]
DRP[78] bit 12	MAIN[14][31][54]
DRP[78] bit 13	MAIN[14][30][54]
DRP[78] bit 14	MAIN[14][30][55]
DRP[78] bit 15	MAIN[14][31][55]
DRP[79] bit 0	MAIN[14][31][56]
DRP[79] bit 1	MAIN[14][30][56]
DRP[79] bit 2	MAIN[14][30][57]
DRP[79] bit 3	MAIN[14][31][57]
DRP[79] bit 4	MAIN[14][31][58]
DRP[79] bit 5	MAIN[14][30][58]
DRP[79] bit 6	MAIN[14][30][59]
DRP[79] bit 7	MAIN[14][31][59]
DRP[79] bit 8	MAIN[14][31][60]
DRP[79] bit 9	MAIN[14][30][60]
DRP[79] bit 10	MAIN[14][30][61]
DRP[79] bit 11	MAIN[14][31][61]
DRP[79] bit 12	MAIN[14][31][62]
DRP[79] bit 13	MAIN[14][30][62]
DRP[79] bit 14	MAIN[14][30][63]
DRP[79] bit 15	MAIN[14][31][63]
DRP_MASK	HCLK[28][12]
MUX_CLKIN	[enum: GTP_MUX_CLKIN]
MUX_CLKOUT_NORTH	[enum: GTP_MUX_CLKOUT_NORTH]
MUX_CLKOUT_SOUTH	[enum: GTP_MUX_CLKOUT_SOUTH]
CLKINDC_B	MAIN[5][31][33]
CLKRCV_TRST	MAIN[6][31][14]
OVERSAMPLE_MODE	MAIN[9][31][55]
PLL_FB_DCCEN	MAIN[11][30][1]
PLL_STARTUP_EN	MAIN[14][30][21]
RX_EN_IDLE_HOLD_CDR	MAIN[12][30][20]
RX_EN_IDLE_RESET_FR	MAIN[12][30][21]
RX_EN_IDLE_RESET_PH	MAIN[12][30][17]
TERMINATION_OVRD	MAIN[10][30][11]
CLK25_DIVIDER	[enum: GTP_CLK25_DIVIDER]
OOB_CLK_DIVIDER	[enum: GTP_OOB_CLK_DIVIDER]
PLL_DIVSEL_FB	[enum: GTP_PLL_DIVSEL_FB]
PLL_DIVSEL_REF	[enum: GTP_PLL_DIVSEL_REF]
CDR_PH_ADJ_TIME bit 0	MAIN[12][31][39]
CDR_PH_ADJ_TIME bit 1	MAIN[12][31][40]
CDR_PH_ADJ_TIME bit 2	MAIN[12][30][40]
CDR_PH_ADJ_TIME bit 3	MAIN[12][30][41]
CDR_PH_ADJ_TIME bit 4	MAIN[12][31][41]
DFE_CAL_TIME bit 0	MAIN[12][30][31]
DFE_CAL_TIME bit 1	MAIN[12][31][31]
DFE_CAL_TIME bit 2	MAIN[12][31][32]
DFE_CAL_TIME bit 3	MAIN[12][30][32]
DFE_CAL_TIME bit 4	MAIN[12][30][33]
TERMINATION_CTRL bit 0	MAIN[10][30][10]
TERMINATION_CTRL bit 1	MAIN[10][31][10]
TERMINATION_CTRL bit 2	MAIN[10][31][9]
TERMINATION_CTRL bit 3	MAIN[10][30][9]
TERMINATION_CTRL bit 4	MAIN[10][30][8]
PLL_LKDET_CFG bit 0	MAIN[5][30][40]
PLL_LKDET_CFG bit 1	MAIN[5][31][40]
PLL_LKDET_CFG bit 2	MAIN[5][31][39]
PLL_COM_CFG bit 0	MAIN[10][31][1]
PLL_COM_CFG bit 1	MAIN[10][30][1]
PLL_COM_CFG bit 2	MAIN[10][30][0]
PLL_COM_CFG bit 3	MAIN[10][31][0]
PLL_COM_CFG bit 4	MAIN[9][31][63]
PLL_COM_CFG bit 5	MAIN[9][30][63]
PLL_COM_CFG bit 6	MAIN[9][30][62]
PLL_COM_CFG bit 7	MAIN[9][31][62]
PLL_COM_CFG bit 8	MAIN[9][31][61]
PLL_COM_CFG bit 9	MAIN[9][30][61]
PLL_COM_CFG bit 10	MAIN[9][30][60]
PLL_COM_CFG bit 11	MAIN[9][31][60]
PLL_COM_CFG bit 12	MAIN[9][31][59]
PLL_COM_CFG bit 13	MAIN[9][30][59]
PLL_COM_CFG bit 14	MAIN[9][30][58]
PLL_COM_CFG bit 15	MAIN[9][31][58]
PLL_COM_CFG bit 16	MAIN[9][31][57]
PLL_COM_CFG bit 17	MAIN[9][30][57]
PLL_COM_CFG bit 18	MAIN[9][30][56]
PLL_COM_CFG bit 19	MAIN[9][31][56]
PLL_COM_CFG bit 20	MAIN[7][31][31]
PLL_COM_CFG bit 21	MAIN[7][31][32]
PLL_COM_CFG bit 22	MAIN[7][30][32]
PLL_COM_CFG bit 23	MAIN[7][30][33]
PLL_CP_CFG bit 0	MAIN[10][31][5]
PLL_CP_CFG bit 1	MAIN[10][30][5]
PLL_CP_CFG bit 2	MAIN[10][30][4]
PLL_CP_CFG bit 3	MAIN[10][31][4]
PLL_CP_CFG bit 4	MAIN[10][31][3]
PLL_CP_CFG bit 5	MAIN[10][30][3]
PLL_CP_CFG bit 6	MAIN[10][30][2]
PLL_CP_CFG bit 7	MAIN[10][31][2]
PLL_TDCC_CFG bit 0	MAIN[14][31][23]
PLL_TDCC_CFG bit 1	MAIN[14][30][23]
PLL_TDCC_CFG bit 2	MAIN[14][31][24]
PMA_COM_CFG bit 0	MAIN[10][30][27]
PMA_COM_CFG bit 1	MAIN[10][30][29]
PMA_COM_CFG bit 2	MAIN[10][30][28]
PMA_COM_CFG bit 3	MAIN[10][31][28]
PMA_COM_CFG bit 4	MAIN[10][31][27]
PMA_COM_CFG bit 5	MAIN[10][30][26]
PMA_COM_CFG bit 6	MAIN[10][31][26]
PMA_COM_CFG bit 7	MAIN[10][31][25]
PMA_COM_CFG bit 8	MAIN[7][30][46]
PMA_COM_CFG bit 9	MAIN[10][31][29]
PMA_COM_CFG bit 10	MAIN[9][31][38]
PMA_COM_CFG bit 11	MAIN[9][31][37]
PMA_COM_CFG bit 12	MAIN[9][30][37]
PMA_COM_CFG bit 13	MAIN[9][30][36]
PMA_COM_CFG bit 14	MAIN[9][31][36]
PMA_COM_CFG bit 15	MAIN[9][31][35]
PMA_COM_CFG bit 16	MAIN[9][30][35]
PMA_COM_CFG bit 17	MAIN[9][30][34]
PMA_COM_CFG bit 18	MAIN[9][31][34]
PMA_COM_CFG bit 19	MAIN[12][30][19]
PMA_COM_CFG bit 20	MAIN[14][31][19]
PMA_COM_CFG bit 21	MAIN[5][31][44]
PMA_COM_CFG bit 22	MAIN[5][30][46]
PMA_COM_CFG bit 23	MAIN[5][31][46]
PMA_COM_CFG bit 24	MAIN[5][31][45]
PMA_COM_CFG bit 25	MAIN[5][30][45]
PMA_COM_CFG bit 26	MAIN[5][30][44]
PMA_COM_CFG bit 27	MAIN[14][30][17]
PMA_COM_CFG bit 28	MAIN[14][31][17]
PMA_COM_CFG bit 29	MAIN[14][31][18]
PMA_COM_CFG bit 30	MAIN[14][30][18]
PMA_COM_CFG bit 31	MAIN[14][30][19]
PMA_COM_CFG bit 32	MAIN[10][31][11]
PMA_COM_CFG bit 33	MAIN[10][30][15]
PMA_COM_CFG bit 34	MAIN[9][30][48]
PMA_COM_CFG bit 35	MAIN[10][31][15]
PMA_COM_CFG bit 36	MAIN[9][30][49]
PMA_COM_CFG bit 37	MAIN[10][30][14]
PMA_COM_CFG bit 38	MAIN[9][31][50]
PMA_COM_CFG bit 39	MAIN[10][31][14]
PMA_COM_CFG bit 40	MAIN[9][31][49]
PMA_COM_CFG bit 41	MAIN[10][31][13]
PMA_COM_CFG bit 42	MAIN[9][30][50]
PMA_COM_CFG bit 43	MAIN[10][30][13]
PMA_COM_CFG bit 44	MAIN[9][30][51]
PMA_COM_CFG bit 45	MAIN[10][30][12]
PMA_COM_CFG bit 46	MAIN[9][31][51]
PMA_COM_CFG bit 47	MAIN[10][31][12]
PMA_COM_CFG bit 48	MAIN[9][31][52]
PMA_COM_CFG bit 49	MAIN[10][31][23]
PMA_COM_CFG bit 50	MAIN[9][30][41]
PMA_COM_CFG bit 51	MAIN[10][30][23]
PMA_COM_CFG bit 52	MAIN[9][30][40]
PMA_COM_CFG bit 53	MAIN[10][31][16]
PMA_COM_CFG bit 54	MAIN[9][31][47]
PMA_COM_CFG bit 55	MAIN[10][30][16]
PMA_COM_CFG bit 56	MAIN[9][31][48]
PMA_COM_CFG bit 57	MAIN[10][31][18]
PMA_COM_CFG bit 58	MAIN[10][31][17]
PMA_COM_CFG bit 59	MAIN[10][30][18]
PMA_COM_CFG bit 60	MAIN[10][30][17]
PMA_COM_CFG bit 61	MAIN[9][31][46]
PMA_COM_CFG bit 62	MAIN[9][30][46]
PMA_COM_CFG bit 63	MAIN[9][31][45]
PMA_COM_CFG bit 64	MAIN[9][30][47]
PMA_COM_CFG bit 65	MAIN[10][31][19]
PMA_COM_CFG bit 66	MAIN[9][30][44]
PMA_COM_CFG bit 67	MAIN[10][30][19]
PMA_COM_CFG bit 68	MAIN[9][30][45]
USRCLK_ENABLE_0	HCLK[17][15]
AC_CAP_DIS_0	MAIN[14][30][15]
CHAN_BOND_KEEP_ALIGN_0	MAIN[14][31][42]
CHAN_BOND_SEQ_2_USE_0	MAIN[12][30][14]
CLK_COR_INSERT_IDLE_FLAG_0	MAIN[12][30][11]
CLK_COR_KEEP_IDLE_0	MAIN[12][30][10]
CLK_COR_PRECEDENCE_0	MAIN[12][31][4]
CLK_CORRECT_USE_0	MAIN[12][31][3]
CLK_COR_SEQ_2_USE_0	MAIN[11][30][20]
COMMA_DOUBLE_0	MAIN[11][30][13]
DEC_MCOMMA_DETECT_0	MAIN[11][30][12]
DEC_PCOMMA_DETECT_0	MAIN[11][31][12]
DEC_VALID_COMMA_ONLY_0	MAIN[11][31][11]
MCOMMA_DETECT_0	MAIN[11][31][6]
PCI_EXPRESS_MODE_0	MAIN[13][31][55]
PCOMMA_DETECT_0	MAIN[13][31][50]
PLL_SATA_0	MAIN[13][30][48]
RCV_TERM_GND_0	MAIN[14][31][16]
RCV_TERM_VTTRX_0	MAIN[14][30][16]
RX_BUFFER_USE_0	MAIN[13][31][17]
RX_CDR_FORCE_ROTATE_0	MAIN[14][30][7]
RX_DECODE_SEQ_MATCH_0	MAIN[13][30][17]
RX_EN_IDLE_HOLD_DFE_0	MAIN[14][30][32]
RX_EN_IDLE_RESET_BUF_0	MAIN[14][31][33]
RXGEARBOX_USE_0	MAIN[14][31][44]
RX_LOSS_OF_SYNC_FSM_0	MAIN[13][30][15]
TX_BUFFER_USE_0	MAIN[12][31][30]
TXGEARBOX_USE_0	MAIN[14][30][44]
ALIGN_COMMA_WORD_0	[enum: GTP_ALIGN_COMMA_WORD]
CHAN_BOND_MODE_0	[enum: GTP_CHAN_BOND_MODE]
CHAN_BOND_SEQ_LEN_0	[enum: GTP_SEQ_LEN]
CLK_COR_ADJ_LEN_0	[enum: GTP_SEQ_LEN]
CLK_COR_DET_LEN_0	[enum: GTP_SEQ_LEN]
PLL_RXDIVSEL_OUT_0	[enum: GTP_PLL_DIVSEL_OUT]
PLL_TXDIVSEL_OUT_0	[enum: GTP_PLL_DIVSEL_OUT]
RX_LOS_INVALID_INCR_0	[enum: GT_RX_LOS_INVALID_INCR]
RX_LOS_THRESHOLD_0	[enum: GT_RX_LOS_THRESHOLD]
RX_SLIDE_MODE_0	[enum: GTP_RX_SLIDE_MODE]
RX_STATUS_FMT_0	[enum: GTP_RX_STATUS_FMT]
RX_XCLK_SEL_0	[enum: GTP_RX_XCLK_SEL]
TX_XCLK_SEL_0	[enum: GTP_TX_XCLK_SEL]
TERMINATION_IMP_0	[enum: GTP_TERMINATION_IMP]
CHAN_BOND_1_MAX_SKEW_0 bit 0	MAIN[10][31][32]
CHAN_BOND_1_MAX_SKEW_0 bit 1	MAIN[10][31][31]
CHAN_BOND_1_MAX_SKEW_0 bit 2	MAIN[10][30][31]
CHAN_BOND_1_MAX_SKEW_0 bit 3	MAIN[10][30][30]
CHAN_BOND_2_MAX_SKEW_0 bit 0	MAIN[10][31][34]
CHAN_BOND_2_MAX_SKEW_0 bit 1	MAIN[10][31][33]
CHAN_BOND_2_MAX_SKEW_0 bit 2	MAIN[10][30][33]
CHAN_BOND_2_MAX_SKEW_0 bit 3	MAIN[10][30][32]
CLK_COR_MAX_LAT_0 bit 0	MAIN[12][31][7]
CLK_COR_MAX_LAT_0 bit 1	MAIN[12][31][8]
CLK_COR_MAX_LAT_0 bit 2	MAIN[12][30][8]
CLK_COR_MAX_LAT_0 bit 3	MAIN[12][30][9]
CLK_COR_MAX_LAT_0 bit 4	MAIN[12][31][9]
CLK_COR_MAX_LAT_0 bit 5	MAIN[12][31][10]
CLK_COR_MIN_LAT_0 bit 0	MAIN[12][30][4]
CLK_COR_MIN_LAT_0 bit 1	MAIN[12][30][5]
CLK_COR_MIN_LAT_0 bit 2	MAIN[12][31][5]
CLK_COR_MIN_LAT_0 bit 3	MAIN[12][31][6]
CLK_COR_MIN_LAT_0 bit 4	MAIN[12][30][6]
CLK_COR_MIN_LAT_0 bit 5	MAIN[12][30][7]
SATA_MAX_BURST_0 bit 0	MAIN[13][31][6]
SATA_MAX_BURST_0 bit 1	MAIN[13][30][6]
SATA_MAX_BURST_0 bit 2	MAIN[13][30][7]
SATA_MAX_BURST_0 bit 3	MAIN[13][31][7]
SATA_MAX_BURST_0 bit 4	MAIN[13][31][8]
SATA_MAX_BURST_0 bit 5	MAIN[13][30][8]
SATA_MAX_INIT_0 bit 0	MAIN[13][30][3]
SATA_MAX_INIT_0 bit 1	MAIN[13][31][3]
SATA_MAX_INIT_0 bit 2	MAIN[13][31][4]
SATA_MAX_INIT_0 bit 3	MAIN[13][30][4]
SATA_MAX_INIT_0 bit 4	MAIN[13][30][5]
SATA_MAX_INIT_0 bit 5	MAIN[13][31][5]
SATA_MAX_WAKE_0 bit 0	MAIN[13][31][0]
SATA_MAX_WAKE_0 bit 1	MAIN[13][30][0]
SATA_MAX_WAKE_0 bit 2	MAIN[13][30][1]
SATA_MAX_WAKE_0 bit 3	MAIN[13][31][1]
SATA_MAX_WAKE_0 bit 4	MAIN[13][31][2]
SATA_MAX_WAKE_0 bit 5	MAIN[13][30][2]
SATA_MIN_BURST_0 bit 0	MAIN[12][30][61]
SATA_MIN_BURST_0 bit 1	MAIN[12][31][61]
SATA_MIN_BURST_0 bit 2	MAIN[12][31][62]
SATA_MIN_BURST_0 bit 3	MAIN[12][30][62]
SATA_MIN_BURST_0 bit 4	MAIN[12][30][63]
SATA_MIN_BURST_0 bit 5	MAIN[12][31][63]
SATA_MIN_INIT_0 bit 0	MAIN[12][31][58]
SATA_MIN_INIT_0 bit 1	MAIN[12][30][58]
SATA_MIN_INIT_0 bit 2	MAIN[12][30][59]
SATA_MIN_INIT_0 bit 3	MAIN[12][31][59]
SATA_MIN_INIT_0 bit 4	MAIN[12][31][60]
SATA_MIN_INIT_0 bit 5	MAIN[12][30][60]
SATA_MIN_WAKE_0 bit 0	MAIN[12][30][55]
SATA_MIN_WAKE_0 bit 1	MAIN[12][31][55]
SATA_MIN_WAKE_0 bit 2	MAIN[12][31][56]
SATA_MIN_WAKE_0 bit 3	MAIN[12][30][56]
SATA_MIN_WAKE_0 bit 4	MAIN[12][30][57]
SATA_MIN_WAKE_0 bit 5	MAIN[12][31][57]
CHAN_BOND_LEVEL_0 bit 0	MAIN[10][31][35]
CHAN_BOND_LEVEL_0 bit 1	MAIN[10][30][35]
CHAN_BOND_LEVEL_0 bit 2	MAIN[10][30][34]
CB2_INH_CC_PERIOD_0 bit 0	MAIN[14][31][40]
CB2_INH_CC_PERIOD_0 bit 1	MAIN[14][30][40]
CB2_INH_CC_PERIOD_0 bit 2	MAIN[14][30][41]
CB2_INH_CC_PERIOD_0 bit 3	MAIN[14][31][41]
CLK_COR_REPEAT_WAIT_0 bit 0	MAIN[12][30][1]
CLK_COR_REPEAT_WAIT_0 bit 1	MAIN[12][31][1]
CLK_COR_REPEAT_WAIT_0 bit 2	MAIN[12][31][2]
CLK_COR_REPEAT_WAIT_0 bit 3	MAIN[12][30][2]
CLK_COR_REPEAT_WAIT_0 bit 4	MAIN[12][30][3]
TXOUTCLK_SEL_0 bit 0	MAIN[12][31][19]
CHAN_BOND_SEQ_1_1_0 bit 0	MAIN[10][31][41]
CHAN_BOND_SEQ_1_1_0 bit 1	MAIN[10][30][41]
CHAN_BOND_SEQ_1_1_0 bit 2	MAIN[10][30][40]
CHAN_BOND_SEQ_1_1_0 bit 3	MAIN[10][31][40]
CHAN_BOND_SEQ_1_1_0 bit 4	MAIN[10][31][39]
CHAN_BOND_SEQ_1_1_0 bit 5	MAIN[10][30][39]
CHAN_BOND_SEQ_1_1_0 bit 6	MAIN[10][30][38]
CHAN_BOND_SEQ_1_1_0 bit 7	MAIN[10][31][38]
CHAN_BOND_SEQ_1_1_0 bit 8	MAIN[10][31][37]
CHAN_BOND_SEQ_1_1_0 bit 9	MAIN[10][30][37]
CHAN_BOND_SEQ_1_2_0 bit 0	MAIN[10][30][46]
CHAN_BOND_SEQ_1_2_0 bit 1	MAIN[10][31][46]
CHAN_BOND_SEQ_1_2_0 bit 2	MAIN[10][31][45]
CHAN_BOND_SEQ_1_2_0 bit 3	MAIN[10][30][45]
CHAN_BOND_SEQ_1_2_0 bit 4	MAIN[10][30][44]
CHAN_BOND_SEQ_1_2_0 bit 5	MAIN[10][31][44]
CHAN_BOND_SEQ_1_2_0 bit 6	MAIN[10][31][43]
CHAN_BOND_SEQ_1_2_0 bit 7	MAIN[10][30][43]
CHAN_BOND_SEQ_1_2_0 bit 8	MAIN[10][30][42]
CHAN_BOND_SEQ_1_2_0 bit 9	MAIN[10][31][42]
CHAN_BOND_SEQ_1_3_0 bit 0	MAIN[10][31][51]
CHAN_BOND_SEQ_1_3_0 bit 1	MAIN[10][30][51]
CHAN_BOND_SEQ_1_3_0 bit 2	MAIN[10][30][50]
CHAN_BOND_SEQ_1_3_0 bit 3	MAIN[10][31][50]
CHAN_BOND_SEQ_1_3_0 bit 4	MAIN[10][31][49]
CHAN_BOND_SEQ_1_3_0 bit 5	MAIN[10][30][49]
CHAN_BOND_SEQ_1_3_0 bit 6	MAIN[10][30][48]
CHAN_BOND_SEQ_1_3_0 bit 7	MAIN[10][31][48]
CHAN_BOND_SEQ_1_3_0 bit 8	MAIN[10][31][47]
CHAN_BOND_SEQ_1_3_0 bit 9	MAIN[10][30][47]
CHAN_BOND_SEQ_1_4_0 bit 0	MAIN[10][30][56]
CHAN_BOND_SEQ_1_4_0 bit 1	MAIN[10][31][56]
CHAN_BOND_SEQ_1_4_0 bit 2	MAIN[10][31][55]
CHAN_BOND_SEQ_1_4_0 bit 3	MAIN[10][30][55]
CHAN_BOND_SEQ_1_4_0 bit 4	MAIN[10][30][54]
CHAN_BOND_SEQ_1_4_0 bit 5	MAIN[10][31][54]
CHAN_BOND_SEQ_1_4_0 bit 6	MAIN[10][31][53]
CHAN_BOND_SEQ_1_4_0 bit 7	MAIN[10][30][53]
CHAN_BOND_SEQ_1_4_0 bit 8	MAIN[10][30][52]
CHAN_BOND_SEQ_1_4_0 bit 9	MAIN[10][31][52]
CHAN_BOND_SEQ_1_ENABLE_0 bit 0	MAIN[10][30][58]
CHAN_BOND_SEQ_1_ENABLE_0 bit 1	MAIN[10][31][58]
CHAN_BOND_SEQ_1_ENABLE_0 bit 2	MAIN[10][31][57]
CHAN_BOND_SEQ_1_ENABLE_0 bit 3	MAIN[10][30][57]
CHAN_BOND_SEQ_2_1_0 bit 0	MAIN[10][31][63]
CHAN_BOND_SEQ_2_1_0 bit 1	MAIN[10][30][63]
CHAN_BOND_SEQ_2_1_0 bit 2	MAIN[10][30][62]
CHAN_BOND_SEQ_2_1_0 bit 3	MAIN[10][31][62]
CHAN_BOND_SEQ_2_1_0 bit 4	MAIN[10][31][61]
CHAN_BOND_SEQ_2_1_0 bit 5	MAIN[10][30][61]
CHAN_BOND_SEQ_2_1_0 bit 6	MAIN[10][30][60]
CHAN_BOND_SEQ_2_1_0 bit 7	MAIN[10][31][60]
CHAN_BOND_SEQ_2_1_0 bit 8	MAIN[10][31][59]
CHAN_BOND_SEQ_2_1_0 bit 9	MAIN[10][30][59]
CHAN_BOND_SEQ_2_2_0 bit 0	MAIN[11][30][5]
CHAN_BOND_SEQ_2_2_0 bit 1	MAIN[11][30][4]
CHAN_BOND_SEQ_2_2_0 bit 2	MAIN[11][31][4]
CHAN_BOND_SEQ_2_2_0 bit 3	MAIN[11][31][3]
CHAN_BOND_SEQ_2_2_0 bit 4	MAIN[11][30][3]
CHAN_BOND_SEQ_2_2_0 bit 5	MAIN[11][30][2]
CHAN_BOND_SEQ_2_2_0 bit 6	MAIN[11][31][2]
CHAN_BOND_SEQ_2_2_0 bit 7	MAIN[11][31][1]
CHAN_BOND_SEQ_2_2_0 bit 8	MAIN[11][30][0]
CHAN_BOND_SEQ_2_2_0 bit 9	MAIN[11][31][0]
CHAN_BOND_SEQ_2_3_0 bit 0	MAIN[13][30][60]
CHAN_BOND_SEQ_2_3_0 bit 1	MAIN[13][31][60]
CHAN_BOND_SEQ_2_3_0 bit 2	MAIN[13][31][59]
CHAN_BOND_SEQ_2_3_0 bit 3	MAIN[13][30][59]
CHAN_BOND_SEQ_2_3_0 bit 4	MAIN[13][30][58]
CHAN_BOND_SEQ_2_3_0 bit 5	MAIN[13][31][58]
CHAN_BOND_SEQ_2_3_0 bit 6	MAIN[13][31][57]
CHAN_BOND_SEQ_2_3_0 bit 7	MAIN[13][30][57]
CHAN_BOND_SEQ_2_3_0 bit 8	MAIN[13][30][56]
CHAN_BOND_SEQ_2_3_0 bit 9	MAIN[11][31][5]
CHAN_BOND_SEQ_2_4_0 bit 0	MAIN[14][31][1]
CHAN_BOND_SEQ_2_4_0 bit 1	MAIN[14][30][1]
CHAN_BOND_SEQ_2_4_0 bit 2	MAIN[14][30][0]
CHAN_BOND_SEQ_2_4_0 bit 3	MAIN[14][31][0]
CHAN_BOND_SEQ_2_4_0 bit 4	MAIN[13][31][63]
CHAN_BOND_SEQ_2_4_0 bit 5	MAIN[13][30][63]
CHAN_BOND_SEQ_2_4_0 bit 6	MAIN[13][30][62]
CHAN_BOND_SEQ_2_4_0 bit 7	MAIN[13][31][62]
CHAN_BOND_SEQ_2_4_0 bit 8	MAIN[13][31][61]
CHAN_BOND_SEQ_2_4_0 bit 9	MAIN[13][30][61]
CHAN_BOND_SEQ_2_ENABLE_0 bit 0	MAIN[12][30][15]
CHAN_BOND_SEQ_2_ENABLE_0 bit 1	MAIN[12][31][15]
CHAN_BOND_SEQ_2_ENABLE_0 bit 2	MAIN[12][31][16]
CHAN_BOND_SEQ_2_ENABLE_0 bit 3	MAIN[12][30][16]
CLK_COR_SEQ_1_1_0 bit 0	MAIN[11][31][60]
CLK_COR_SEQ_1_1_0 bit 1	MAIN[11][30][60]
CLK_COR_SEQ_1_1_0 bit 2	MAIN[11][30][61]
CLK_COR_SEQ_1_1_0 bit 3	MAIN[11][31][61]
CLK_COR_SEQ_1_1_0 bit 4	MAIN[11][31][62]
CLK_COR_SEQ_1_1_0 bit 5	MAIN[11][30][62]
CLK_COR_SEQ_1_1_0 bit 6	MAIN[11][30][63]
CLK_COR_SEQ_1_1_0 bit 7	MAIN[11][31][63]
CLK_COR_SEQ_1_1_0 bit 8	MAIN[12][31][0]
CLK_COR_SEQ_1_1_0 bit 9	MAIN[12][30][0]
CLK_COR_SEQ_1_2_0 bit 0	MAIN[11][30][55]
CLK_COR_SEQ_1_2_0 bit 1	MAIN[11][31][55]
CLK_COR_SEQ_1_2_0 bit 2	MAIN[11][31][56]
CLK_COR_SEQ_1_2_0 bit 3	MAIN[11][30][56]
CLK_COR_SEQ_1_2_0 bit 4	MAIN[11][30][57]
CLK_COR_SEQ_1_2_0 bit 5	MAIN[11][31][57]
CLK_COR_SEQ_1_2_0 bit 6	MAIN[11][31][58]
CLK_COR_SEQ_1_2_0 bit 7	MAIN[11][30][58]
CLK_COR_SEQ_1_2_0 bit 8	MAIN[11][30][59]
CLK_COR_SEQ_1_2_0 bit 9	MAIN[11][31][59]
CLK_COR_SEQ_1_3_0 bit 0	MAIN[11][31][50]
CLK_COR_SEQ_1_3_0 bit 1	MAIN[11][30][50]
CLK_COR_SEQ_1_3_0 bit 2	MAIN[11][30][51]
CLK_COR_SEQ_1_3_0 bit 3	MAIN[11][31][51]
CLK_COR_SEQ_1_3_0 bit 4	MAIN[11][31][52]
CLK_COR_SEQ_1_3_0 bit 5	MAIN[11][30][52]
CLK_COR_SEQ_1_3_0 bit 6	MAIN[11][30][53]
CLK_COR_SEQ_1_3_0 bit 7	MAIN[11][31][53]
CLK_COR_SEQ_1_3_0 bit 8	MAIN[11][31][54]
CLK_COR_SEQ_1_3_0 bit 9	MAIN[11][30][54]
CLK_COR_SEQ_1_4_0 bit 0	MAIN[11][30][45]
CLK_COR_SEQ_1_4_0 bit 1	MAIN[11][31][45]
CLK_COR_SEQ_1_4_0 bit 2	MAIN[11][31][46]
CLK_COR_SEQ_1_4_0 bit 3	MAIN[11][30][46]
CLK_COR_SEQ_1_4_0 bit 4	MAIN[11][30][47]
CLK_COR_SEQ_1_4_0 bit 5	MAIN[11][31][47]
CLK_COR_SEQ_1_4_0 bit 6	MAIN[11][31][48]
CLK_COR_SEQ_1_4_0 bit 7	MAIN[11][30][48]
CLK_COR_SEQ_1_4_0 bit 8	MAIN[11][30][49]
CLK_COR_SEQ_1_4_0 bit 9	MAIN[11][31][49]
CLK_COR_SEQ_1_ENABLE_0 bit 0	MAIN[11][30][43]
CLK_COR_SEQ_1_ENABLE_0 bit 1	MAIN[11][31][43]
CLK_COR_SEQ_1_ENABLE_0 bit 2	MAIN[11][31][44]
CLK_COR_SEQ_1_ENABLE_0 bit 3	MAIN[11][30][44]
CLK_COR_SEQ_2_1_0 bit 0	MAIN[11][31][38]
CLK_COR_SEQ_2_1_0 bit 1	MAIN[11][30][38]
CLK_COR_SEQ_2_1_0 bit 2	MAIN[11][30][39]
CLK_COR_SEQ_2_1_0 bit 3	MAIN[11][31][39]
CLK_COR_SEQ_2_1_0 bit 4	MAIN[11][31][40]
CLK_COR_SEQ_2_1_0 bit 5	MAIN[11][30][40]
CLK_COR_SEQ_2_1_0 bit 6	MAIN[11][30][41]
CLK_COR_SEQ_2_1_0 bit 7	MAIN[11][31][41]
CLK_COR_SEQ_2_1_0 bit 8	MAIN[11][31][42]
CLK_COR_SEQ_2_1_0 bit 9	MAIN[11][30][42]
CLK_COR_SEQ_2_2_0 bit 0	MAIN[11][30][33]
CLK_COR_SEQ_2_2_0 bit 1	MAIN[11][31][33]
CLK_COR_SEQ_2_2_0 bit 2	MAIN[11][31][34]
CLK_COR_SEQ_2_2_0 bit 3	MAIN[11][30][34]
CLK_COR_SEQ_2_2_0 bit 4	MAIN[11][30][35]
CLK_COR_SEQ_2_2_0 bit 5	MAIN[11][31][35]
CLK_COR_SEQ_2_2_0 bit 6	MAIN[11][31][36]
CLK_COR_SEQ_2_2_0 bit 7	MAIN[11][30][36]
CLK_COR_SEQ_2_2_0 bit 8	MAIN[11][30][37]
CLK_COR_SEQ_2_2_0 bit 9	MAIN[11][31][37]
CLK_COR_SEQ_2_3_0 bit 0	MAIN[11][31][28]
CLK_COR_SEQ_2_3_0 bit 1	MAIN[11][30][28]
CLK_COR_SEQ_2_3_0 bit 2	MAIN[11][30][29]
CLK_COR_SEQ_2_3_0 bit 3	MAIN[11][31][29]
CLK_COR_SEQ_2_3_0 bit 4	MAIN[11][31][30]
CLK_COR_SEQ_2_3_0 bit 5	MAIN[11][30][30]
CLK_COR_SEQ_2_3_0 bit 6	MAIN[11][30][31]
CLK_COR_SEQ_2_3_0 bit 7	MAIN[11][31][31]
CLK_COR_SEQ_2_3_0 bit 8	MAIN[11][31][32]
CLK_COR_SEQ_2_3_0 bit 9	MAIN[11][30][32]
CLK_COR_SEQ_2_4_0 bit 0	MAIN[11][30][23]
CLK_COR_SEQ_2_4_0 bit 1	MAIN[11][31][23]
CLK_COR_SEQ_2_4_0 bit 2	MAIN[11][31][24]
CLK_COR_SEQ_2_4_0 bit 3	MAIN[11][30][24]
CLK_COR_SEQ_2_4_0 bit 4	MAIN[11][30][25]
CLK_COR_SEQ_2_4_0 bit 5	MAIN[11][31][25]
CLK_COR_SEQ_2_4_0 bit 6	MAIN[11][31][26]
CLK_COR_SEQ_2_4_0 bit 7	MAIN[11][30][26]
CLK_COR_SEQ_2_4_0 bit 8	MAIN[11][30][27]
CLK_COR_SEQ_2_4_0 bit 9	MAIN[11][31][27]
CLK_COR_SEQ_2_ENABLE_0 bit 0	MAIN[11][30][21]
CLK_COR_SEQ_2_ENABLE_0 bit 1	MAIN[11][31][21]
CLK_COR_SEQ_2_ENABLE_0 bit 2	MAIN[11][31][22]
CLK_COR_SEQ_2_ENABLE_0 bit 3	MAIN[11][30][22]
CM_TRIM_0 bit 0	MAIN[14][31][50]
CM_TRIM_0 bit 1	MAIN[14][30][50]
COMMA_10B_ENABLE_0 bit 0	MAIN[11][31][13]
COMMA_10B_ENABLE_0 bit 1	MAIN[11][31][14]
COMMA_10B_ENABLE_0 bit 2	MAIN[11][30][14]
COMMA_10B_ENABLE_0 bit 3	MAIN[11][30][15]
COMMA_10B_ENABLE_0 bit 4	MAIN[11][31][15]
COMMA_10B_ENABLE_0 bit 5	MAIN[11][31][16]
COMMA_10B_ENABLE_0 bit 6	MAIN[11][30][16]
COMMA_10B_ENABLE_0 bit 7	MAIN[11][30][17]
COMMA_10B_ENABLE_0 bit 8	MAIN[11][31][17]
COMMA_10B_ENABLE_0 bit 9	MAIN[11][31][18]
COM_BURST_VAL_0 bit 0	MAIN[11][30][18]
COM_BURST_VAL_0 bit 1	MAIN[11][30][19]
COM_BURST_VAL_0 bit 2	MAIN[11][31][19]
COM_BURST_VAL_0 bit 3	MAIN[11][31][20]
DFE_CFG_0 bit 0	MAIN[14][30][45]
DFE_CFG_0 bit 1	MAIN[14][31][45]
DFE_CFG_0 bit 2	MAIN[14][31][46]
DFE_CFG_0 bit 3	MAIN[14][30][46]
DFE_CFG_0 bit 4	MAIN[14][30][47]
DFE_CFG_0 bit 5	MAIN[14][31][47]
DFE_CFG_0 bit 6	MAIN[14][31][48]
DFE_CFG_0 bit 7	MAIN[14][30][48]
DFE_CFG_0 bit 8	MAIN[14][30][49]
DFE_CFG_0 bit 9	MAIN[14][31][49]
GEARBOX_ENDEC_0 bit 0	MAIN[14][30][42]
GEARBOX_ENDEC_0 bit 1	MAIN[14][30][43]
GEARBOX_ENDEC_0 bit 2	MAIN[14][31][43]
MCOMMA_10B_VALUE_0 bit 0	MAIN[11][30][6]
MCOMMA_10B_VALUE_0 bit 1	MAIN[11][30][7]
MCOMMA_10B_VALUE_0 bit 2	MAIN[11][31][7]
MCOMMA_10B_VALUE_0 bit 3	MAIN[11][31][8]
MCOMMA_10B_VALUE_0 bit 4	MAIN[11][30][8]
MCOMMA_10B_VALUE_0 bit 5	MAIN[11][30][9]
MCOMMA_10B_VALUE_0 bit 6	MAIN[11][31][9]
MCOMMA_10B_VALUE_0 bit 7	MAIN[11][31][10]
MCOMMA_10B_VALUE_0 bit 8	MAIN[11][30][10]
MCOMMA_10B_VALUE_0 bit 9	MAIN[11][30][11]
OOBDETECT_THRESHOLD_0 bit 0	MAIN[12][31][17]
OOBDETECT_THRESHOLD_0 bit 1	MAIN[12][31][18]
OOBDETECT_THRESHOLD_0 bit 2	MAIN[12][30][18]
PCOMMA_10B_VALUE_0 bit 0	MAIN[13][30][50]
PCOMMA_10B_VALUE_0 bit 1	MAIN[13][30][51]
PCOMMA_10B_VALUE_0 bit 2	MAIN[13][31][51]
PCOMMA_10B_VALUE_0 bit 3	MAIN[13][31][52]
PCOMMA_10B_VALUE_0 bit 4	MAIN[13][30][52]
PCOMMA_10B_VALUE_0 bit 5	MAIN[13][30][53]
PCOMMA_10B_VALUE_0 bit 6	MAIN[13][31][53]
PCOMMA_10B_VALUE_0 bit 7	MAIN[13][31][54]
PCOMMA_10B_VALUE_0 bit 8	MAIN[13][30][54]
PCOMMA_10B_VALUE_0 bit 9	MAIN[13][30][55]
RX_IDLE_HI_CNT_0 bit 0	MAIN[14][30][35]
RX_IDLE_HI_CNT_0 bit 1	MAIN[14][31][35]
RX_IDLE_HI_CNT_0 bit 2	MAIN[14][31][36]
RX_IDLE_HI_CNT_0 bit 3	MAIN[14][30][36]
RX_IDLE_LO_CNT_0 bit 0	MAIN[14][31][38]
RX_IDLE_LO_CNT_0 bit 1	MAIN[14][30][38]
RX_IDLE_LO_CNT_0 bit 2	MAIN[14][30][39]
RX_IDLE_LO_CNT_0 bit 3	MAIN[14][31][39]
SATA_BURST_VAL_0 bit 0	MAIN[13][30][10]
SATA_BURST_VAL_0 bit 1	MAIN[13][30][11]
SATA_BURST_VAL_0 bit 2	MAIN[13][31][11]
SATA_IDLE_VAL_0 bit 0	MAIN[13][30][9]
SATA_IDLE_VAL_0 bit 1	MAIN[13][31][9]
SATA_IDLE_VAL_0 bit 2	MAIN[13][31][10]
TXRX_INVERT_0 bit 0	MAIN[12][31][21]
TXRX_INVERT_0 bit 1	MAIN[12][31][22]
TXRX_INVERT_0 bit 2	MAIN[12][30][22]
TX_IDLE_DELAY_0 bit 0	MAIN[14][30][27]
TX_IDLE_DELAY_0 bit 1	MAIN[14][31][27]
TX_IDLE_DELAY_0 bit 2	MAIN[14][31][28]
PMA_CDR_SCAN_0 bit 0	MAIN[13][31][34]
PMA_CDR_SCAN_0 bit 1	MAIN[13][30][34]
PMA_CDR_SCAN_0 bit 2	MAIN[13][30][35]
PMA_CDR_SCAN_0 bit 3	MAIN[13][31][35]
PMA_CDR_SCAN_0 bit 4	MAIN[13][31][36]
PMA_CDR_SCAN_0 bit 5	MAIN[13][30][36]
PMA_CDR_SCAN_0 bit 6	MAIN[13][30][37]
PMA_CDR_SCAN_0 bit 7	MAIN[13][31][37]
PMA_CDR_SCAN_0 bit 8	MAIN[13][31][38]
PMA_CDR_SCAN_0 bit 9	MAIN[13][30][38]
PMA_CDR_SCAN_0 bit 10	MAIN[13][30][39]
PMA_CDR_SCAN_0 bit 11	MAIN[13][31][39]
PMA_CDR_SCAN_0 bit 12	MAIN[13][31][40]
PMA_CDR_SCAN_0 bit 13	MAIN[13][30][40]
PMA_CDR_SCAN_0 bit 14	MAIN[13][30][41]
PMA_CDR_SCAN_0 bit 15	MAIN[13][31][41]
PMA_CDR_SCAN_0 bit 16	MAIN[13][31][42]
PMA_CDR_SCAN_0 bit 17	MAIN[13][30][42]
PMA_CDR_SCAN_0 bit 18	MAIN[13][30][43]
PMA_CDR_SCAN_0 bit 19	MAIN[13][31][43]
PMA_CDR_SCAN_0 bit 20	MAIN[13][31][44]
PMA_CDR_SCAN_0 bit 21	MAIN[13][30][44]
PMA_CDR_SCAN_0 bit 22	MAIN[13][30][45]
PMA_CDR_SCAN_0 bit 23	MAIN[13][31][45]
PMA_CDR_SCAN_0 bit 24	MAIN[13][31][46]
PMA_CDR_SCAN_0 bit 25	MAIN[13][30][46]
PMA_CDR_SCAN_0 bit 26	MAIN[13][30][47]
PMA_RXSYNC_CFG_0 bit 0	MAIN[14][30][28]
PMA_RXSYNC_CFG_0 bit 1	MAIN[14][30][29]
PMA_RXSYNC_CFG_0 bit 2	MAIN[14][31][29]
PMA_RXSYNC_CFG_0 bit 3	MAIN[14][31][30]
PMA_RXSYNC_CFG_0 bit 4	MAIN[14][30][30]
PMA_RXSYNC_CFG_0 bit 5	MAIN[14][30][31]
PMA_RXSYNC_CFG_0 bit 6	MAIN[14][31][31]
PMA_RX_CFG_0 bit 0	MAIN[5][30][50]
PMA_RX_CFG_0 bit 1	MAIN[5][31][50]
PMA_RX_CFG_0 bit 2	MAIN[14][30][5]
PMA_RX_CFG_0 bit 3	MAIN[14][31][5]
PMA_RX_CFG_0 bit 4	MAIN[14][31][6]
PMA_RX_CFG_0 bit 5	MAIN[14][30][6]
PMA_RX_CFG_0 bit 6	MAIN[14][31][2]
PMA_RX_CFG_0 bit 7	MAIN[14][30][2]
PMA_RX_CFG_0 bit 8	MAIN[14][30][3]
PMA_RX_CFG_0 bit 9	MAIN[14][31][3]
PMA_RX_CFG_0 bit 10	MAIN[14][31][4]
PMA_RX_CFG_0 bit 11	MAIN[5][30][51]
PMA_RX_CFG_0 bit 12	MAIN[5][30][49]
PMA_RX_CFG_0 bit 13	MAIN[14][31][7]
PMA_RX_CFG_0 bit 14	MAIN[14][31][8]
PMA_RX_CFG_0 bit 15	MAIN[14][30][8]
PMA_RX_CFG_0 bit 16	MAIN[14][30][9]
PMA_RX_CFG_0 bit 17	MAIN[14][31][9]
PMA_RX_CFG_0 bit 18	MAIN[14][31][10]
PMA_RX_CFG_0 bit 19	MAIN[14][30][10]
PMA_RX_CFG_0 bit 20	MAIN[14][30][11]
PMA_RX_CFG_0 bit 21	MAIN[14][31][11]
PMA_RX_CFG_0 bit 22	MAIN[14][31][12]
PMA_RX_CFG_0 bit 23	MAIN[5][30][59]
PMA_RX_CFG_0 bit 24	MAIN[5][31][49]
PMA_TX_CFG_0 bit 0	MAIN[14][30][51]
PMA_TX_CFG_0 bit 1	MAIN[14][31][51]
PMA_TX_CFG_0 bit 2	MAIN[14][31][52]
PMA_TX_CFG_0 bit 3	MAIN[14][30][52]
PMA_TX_CFG_0 bit 4	MAIN[14][30][53]
PMA_TX_CFG_0 bit 5	MAIN[14][31][53]
PMA_TX_CFG_0 bit 6	MAIN[14][31][54]
PMA_TX_CFG_0 bit 7	MAIN[14][30][54]
PMA_TX_CFG_0 bit 8	MAIN[14][30][55]
PMA_TX_CFG_0 bit 9	MAIN[14][31][55]
PMA_TX_CFG_0 bit 10	MAIN[14][31][56]
PMA_TX_CFG_0 bit 11	MAIN[14][30][56]
PMA_TX_CFG_0 bit 12	MAIN[14][30][57]
PMA_TX_CFG_0 bit 13	MAIN[14][31][57]
PMA_TX_CFG_0 bit 14	MAIN[14][31][58]
PMA_TX_CFG_0 bit 15	MAIN[14][30][58]
PMA_TX_CFG_0 bit 16	MAIN[14][30][59]
PMA_TX_CFG_0 bit 17	MAIN[14][31][59]
PMA_TX_CFG_0 bit 18	MAIN[14][31][60]
PMA_TX_CFG_0 bit 19	MAIN[14][30][60]
PRBS_ERR_THRESHOLD_0 bit 0	MAIN[13][31][18]
PRBS_ERR_THRESHOLD_0 bit 1	MAIN[13][30][18]
PRBS_ERR_THRESHOLD_0 bit 2	MAIN[13][30][19]
PRBS_ERR_THRESHOLD_0 bit 3	MAIN[13][31][19]
PRBS_ERR_THRESHOLD_0 bit 4	MAIN[13][31][20]
PRBS_ERR_THRESHOLD_0 bit 5	MAIN[13][30][20]
PRBS_ERR_THRESHOLD_0 bit 6	MAIN[13][30][21]
PRBS_ERR_THRESHOLD_0 bit 7	MAIN[13][31][21]
PRBS_ERR_THRESHOLD_0 bit 8	MAIN[13][31][22]
PRBS_ERR_THRESHOLD_0 bit 9	MAIN[13][30][22]
PRBS_ERR_THRESHOLD_0 bit 10	MAIN[13][30][23]
PRBS_ERR_THRESHOLD_0 bit 11	MAIN[13][31][23]
PRBS_ERR_THRESHOLD_0 bit 12	MAIN[13][31][24]
PRBS_ERR_THRESHOLD_0 bit 13	MAIN[13][30][24]
PRBS_ERR_THRESHOLD_0 bit 14	MAIN[13][30][25]
PRBS_ERR_THRESHOLD_0 bit 15	MAIN[13][31][25]
PRBS_ERR_THRESHOLD_0 bit 16	MAIN[13][31][26]
PRBS_ERR_THRESHOLD_0 bit 17	MAIN[13][30][26]
PRBS_ERR_THRESHOLD_0 bit 18	MAIN[13][30][27]
PRBS_ERR_THRESHOLD_0 bit 19	MAIN[13][31][27]
PRBS_ERR_THRESHOLD_0 bit 20	MAIN[13][31][28]
PRBS_ERR_THRESHOLD_0 bit 21	MAIN[13][30][28]
PRBS_ERR_THRESHOLD_0 bit 22	MAIN[13][30][29]
PRBS_ERR_THRESHOLD_0 bit 23	MAIN[13][31][29]
PRBS_ERR_THRESHOLD_0 bit 24	MAIN[13][31][30]
PRBS_ERR_THRESHOLD_0 bit 25	MAIN[13][30][30]
PRBS_ERR_THRESHOLD_0 bit 26	MAIN[13][30][31]
PRBS_ERR_THRESHOLD_0 bit 27	MAIN[13][31][31]
PRBS_ERR_THRESHOLD_0 bit 28	MAIN[13][31][32]
PRBS_ERR_THRESHOLD_0 bit 29	MAIN[13][30][32]
PRBS_ERR_THRESHOLD_0 bit 30	MAIN[13][30][33]
PRBS_ERR_THRESHOLD_0 bit 31	MAIN[13][31][33]
TRANS_TIME_FROM_P2_0 bit 0	MAIN[12][30][48]
TRANS_TIME_FROM_P2_0 bit 1	MAIN[12][30][49]
TRANS_TIME_FROM_P2_0 bit 2	MAIN[12][31][49]
TRANS_TIME_FROM_P2_0 bit 3	MAIN[12][31][50]
TRANS_TIME_FROM_P2_0 bit 4	MAIN[12][30][50]
TRANS_TIME_FROM_P2_0 bit 5	MAIN[12][30][51]
TRANS_TIME_FROM_P2_0 bit 6	MAIN[12][31][51]
TRANS_TIME_FROM_P2_0 bit 7	MAIN[12][31][52]
TRANS_TIME_FROM_P2_0 bit 8	MAIN[12][30][52]
TRANS_TIME_FROM_P2_0 bit 9	MAIN[12][30][53]
TRANS_TIME_FROM_P2_0 bit 10	MAIN[12][31][53]
TRANS_TIME_FROM_P2_0 bit 11	MAIN[12][31][54]
TRANS_TIME_NON_P2_0 bit 0	MAIN[12][30][42]
TRANS_TIME_NON_P2_0 bit 1	MAIN[12][30][43]
TRANS_TIME_NON_P2_0 bit 2	MAIN[12][31][43]
TRANS_TIME_NON_P2_0 bit 3	MAIN[12][31][44]
TRANS_TIME_NON_P2_0 bit 4	MAIN[12][30][44]
TRANS_TIME_NON_P2_0 bit 5	MAIN[12][30][45]
TRANS_TIME_NON_P2_0 bit 6	MAIN[12][31][45]
TRANS_TIME_NON_P2_0 bit 7	MAIN[12][31][46]
TRANS_TIME_TO_P2_0 bit 0	MAIN[12][31][33]
TRANS_TIME_TO_P2_0 bit 1	MAIN[12][31][34]
TRANS_TIME_TO_P2_0 bit 2	MAIN[12][30][34]
TRANS_TIME_TO_P2_0 bit 3	MAIN[12][30][35]
TRANS_TIME_TO_P2_0 bit 4	MAIN[12][31][35]
TRANS_TIME_TO_P2_0 bit 5	MAIN[12][31][36]
TRANS_TIME_TO_P2_0 bit 6	MAIN[12][30][36]
TRANS_TIME_TO_P2_0 bit 7	MAIN[12][30][37]
TRANS_TIME_TO_P2_0 bit 8	MAIN[12][31][37]
TRANS_TIME_TO_P2_0 bit 9	MAIN[12][31][38]
TX_DETECT_RX_CFG_0 bit 0	MAIN[12][30][23]
TX_DETECT_RX_CFG_0 bit 1	MAIN[12][31][23]
TX_DETECT_RX_CFG_0 bit 2	MAIN[12][31][24]
TX_DETECT_RX_CFG_0 bit 3	MAIN[12][30][24]
TX_DETECT_RX_CFG_0 bit 4	MAIN[12][30][25]
TX_DETECT_RX_CFG_0 bit 5	MAIN[12][31][25]
TX_DETECT_RX_CFG_0 bit 6	MAIN[12][31][26]
TX_DETECT_RX_CFG_0 bit 7	MAIN[12][30][26]
TX_DETECT_RX_CFG_0 bit 8	MAIN[12][30][27]
TX_DETECT_RX_CFG_0 bit 9	MAIN[12][31][27]
TX_DETECT_RX_CFG_0 bit 10	MAIN[12][31][28]
TX_DETECT_RX_CFG_0 bit 11	MAIN[12][30][28]
TX_DETECT_RX_CFG_0 bit 12	MAIN[12][30][29]
TX_DETECT_RX_CFG_0 bit 13	MAIN[12][31][29]
USRCLK_ENABLE_1	HCLK[18][12]
AC_CAP_DIS_1	MAIN[5][30][48]
CHAN_BOND_KEEP_ALIGN_1	MAIN[5][31][22]
CHAN_BOND_SEQ_2_USE_1	MAIN[7][30][49]
CLK_COR_INSERT_IDLE_FLAG_1	MAIN[7][30][52]
CLK_COR_KEEP_IDLE_1	MAIN[7][30][53]
CLK_COR_PRECEDENCE_1	MAIN[7][31][59]
CLK_CORRECT_USE_1	MAIN[7][31][60]
CLK_COR_SEQ_2_USE_1	MAIN[8][30][43]
COMMA_DOUBLE_1	MAIN[8][30][50]
DEC_MCOMMA_DETECT_1	MAIN[8][30][51]
DEC_PCOMMA_DETECT_1	MAIN[8][31][51]
DEC_VALID_COMMA_ONLY_1	MAIN[8][31][52]
MCOMMA_DETECT_1	MAIN[8][31][57]
PCI_EXPRESS_MODE_1	MAIN[6][31][8]
PCOMMA_DETECT_1	MAIN[6][31][13]
PLL_SATA_1	MAIN[6][30][15]
RCV_TERM_GND_1	MAIN[5][31][47]
RCV_TERM_VTTRX_1	MAIN[5][30][47]
RX_BUFFER_USE_1	MAIN[6][31][46]
RX_CDR_FORCE_ROTATE_1	MAIN[5][30][56]
RX_DECODE_SEQ_MATCH_1	MAIN[6][30][46]
RX_EN_IDLE_HOLD_DFE_1	MAIN[5][30][31]
RX_EN_IDLE_RESET_BUF_1	MAIN[5][31][30]
RXGEARBOX_USE_1	MAIN[5][31][20]
RX_LOSS_OF_SYNC_FSM_1	MAIN[6][30][48]
TX_BUFFER_USE_1	MAIN[7][31][33]
TXGEARBOX_USE_1	MAIN[5][31][19]
ALIGN_COMMA_WORD_1	[enum: GTP_ALIGN_COMMA_WORD]
CHAN_BOND_MODE_1	[enum: GTP_CHAN_BOND_MODE]
CHAN_BOND_SEQ_LEN_1	[enum: GTP_SEQ_LEN]
CLK_COR_ADJ_LEN_1	[enum: GTP_SEQ_LEN]
CLK_COR_DET_LEN_1	[enum: GTP_SEQ_LEN]
PLL_RXDIVSEL_OUT_1	[enum: GTP_PLL_DIVSEL_OUT]
PLL_TXDIVSEL_OUT_1	[enum: GTP_PLL_DIVSEL_OUT]
RX_LOS_INVALID_INCR_1	[enum: GT_RX_LOS_INVALID_INCR]
RX_LOS_THRESHOLD_1	[enum: GT_RX_LOS_THRESHOLD]
RX_SLIDE_MODE_1	[enum: GTP_RX_SLIDE_MODE]
RX_STATUS_FMT_1	[enum: GTP_RX_STATUS_FMT]
RX_XCLK_SEL_1	[enum: GTP_RX_XCLK_SEL]
TX_XCLK_SEL_1	[enum: GTP_TX_XCLK_SEL]
TERMINATION_IMP_1	[enum: GTP_TERMINATION_IMP]
CHAN_BOND_1_MAX_SKEW_1 bit 0	MAIN[9][31][31]
CHAN_BOND_1_MAX_SKEW_1 bit 1	MAIN[9][31][32]
CHAN_BOND_1_MAX_SKEW_1 bit 2	MAIN[9][30][32]
CHAN_BOND_1_MAX_SKEW_1 bit 3	MAIN[9][30][33]
CHAN_BOND_2_MAX_SKEW_1 bit 0	MAIN[9][31][29]
CHAN_BOND_2_MAX_SKEW_1 bit 1	MAIN[9][31][30]
CHAN_BOND_2_MAX_SKEW_1 bit 2	MAIN[9][30][30]
CHAN_BOND_2_MAX_SKEW_1 bit 3	MAIN[9][30][31]
CLK_COR_MAX_LAT_1 bit 0	MAIN[7][31][56]
CLK_COR_MAX_LAT_1 bit 1	MAIN[7][31][55]
CLK_COR_MAX_LAT_1 bit 2	MAIN[7][30][55]
CLK_COR_MAX_LAT_1 bit 3	MAIN[7][30][54]
CLK_COR_MAX_LAT_1 bit 4	MAIN[7][31][54]
CLK_COR_MAX_LAT_1 bit 5	MAIN[7][31][53]
CLK_COR_MIN_LAT_1 bit 0	MAIN[7][30][59]
CLK_COR_MIN_LAT_1 bit 1	MAIN[7][30][58]
CLK_COR_MIN_LAT_1 bit 2	MAIN[7][31][58]
CLK_COR_MIN_LAT_1 bit 3	MAIN[7][31][57]
CLK_COR_MIN_LAT_1 bit 4	MAIN[7][30][57]
CLK_COR_MIN_LAT_1 bit 5	MAIN[7][30][56]
SATA_MAX_BURST_1 bit 0	MAIN[6][31][57]
SATA_MAX_BURST_1 bit 1	MAIN[6][30][57]
SATA_MAX_BURST_1 bit 2	MAIN[6][30][56]
SATA_MAX_BURST_1 bit 3	MAIN[6][31][56]
SATA_MAX_BURST_1 bit 4	MAIN[6][31][55]
SATA_MAX_BURST_1 bit 5	MAIN[6][30][55]
SATA_MAX_INIT_1 bit 0	MAIN[6][30][60]
SATA_MAX_INIT_1 bit 1	MAIN[6][31][60]
SATA_MAX_INIT_1 bit 2	MAIN[6][31][59]
SATA_MAX_INIT_1 bit 3	MAIN[6][30][59]
SATA_MAX_INIT_1 bit 4	MAIN[6][30][58]
SATA_MAX_INIT_1 bit 5	MAIN[6][31][58]
SATA_MAX_WAKE_1 bit 0	MAIN[6][31][63]
SATA_MAX_WAKE_1 bit 1	MAIN[6][30][63]
SATA_MAX_WAKE_1 bit 2	MAIN[6][30][62]
SATA_MAX_WAKE_1 bit 3	MAIN[6][31][62]
SATA_MAX_WAKE_1 bit 4	MAIN[6][31][61]
SATA_MAX_WAKE_1 bit 5	MAIN[6][30][61]
SATA_MIN_BURST_1 bit 0	MAIN[7][30][2]
SATA_MIN_BURST_1 bit 1	MAIN[7][31][2]
SATA_MIN_BURST_1 bit 2	MAIN[7][31][1]
SATA_MIN_BURST_1 bit 3	MAIN[7][30][1]
SATA_MIN_BURST_1 bit 4	MAIN[7][30][0]
SATA_MIN_BURST_1 bit 5	MAIN[7][31][0]
SATA_MIN_INIT_1 bit 0	MAIN[7][31][5]
SATA_MIN_INIT_1 bit 1	MAIN[7][30][5]
SATA_MIN_INIT_1 bit 2	MAIN[7][30][4]
SATA_MIN_INIT_1 bit 3	MAIN[7][31][4]
SATA_MIN_INIT_1 bit 4	MAIN[7][31][3]
SATA_MIN_INIT_1 bit 5	MAIN[7][30][3]
SATA_MIN_WAKE_1 bit 0	MAIN[7][30][8]
SATA_MIN_WAKE_1 bit 1	MAIN[7][31][8]
SATA_MIN_WAKE_1 bit 2	MAIN[7][31][7]
SATA_MIN_WAKE_1 bit 3	MAIN[7][30][7]
SATA_MIN_WAKE_1 bit 4	MAIN[7][30][6]
SATA_MIN_WAKE_1 bit 5	MAIN[7][31][6]
CHAN_BOND_LEVEL_1 bit 0	MAIN[9][31][28]
CHAN_BOND_LEVEL_1 bit 1	MAIN[9][30][28]
CHAN_BOND_LEVEL_1 bit 2	MAIN[9][30][29]
CB2_INH_CC_PERIOD_1 bit 0	MAIN[5][31][24]
CB2_INH_CC_PERIOD_1 bit 1	MAIN[5][31][23]
CB2_INH_CC_PERIOD_1 bit 2	MAIN[5][30][23]
CB2_INH_CC_PERIOD_1 bit 3	MAIN[5][30][22]
CLK_COR_REPEAT_WAIT_1 bit 0	MAIN[7][30][62]
CLK_COR_REPEAT_WAIT_1 bit 1	MAIN[7][31][62]
CLK_COR_REPEAT_WAIT_1 bit 2	MAIN[7][31][61]
CLK_COR_REPEAT_WAIT_1 bit 3	MAIN[7][30][61]
CLK_COR_REPEAT_WAIT_1 bit 4	MAIN[7][30][60]
TXOUTCLK_SEL_1 bit 0	MAIN[7][31][44]
CHAN_BOND_SEQ_1_1_1 bit 0	MAIN[9][31][22]
CHAN_BOND_SEQ_1_1_1 bit 1	MAIN[9][30][22]
CHAN_BOND_SEQ_1_1_1 bit 2	MAIN[9][30][23]
CHAN_BOND_SEQ_1_1_1 bit 3	MAIN[9][31][23]
CHAN_BOND_SEQ_1_1_1 bit 4	MAIN[9][31][24]
CHAN_BOND_SEQ_1_1_1 bit 5	MAIN[9][30][24]
CHAN_BOND_SEQ_1_1_1 bit 6	MAIN[9][30][25]
CHAN_BOND_SEQ_1_1_1 bit 7	MAIN[9][31][25]
CHAN_BOND_SEQ_1_1_1 bit 8	MAIN[9][31][26]
CHAN_BOND_SEQ_1_1_1 bit 9	MAIN[9][30][26]
CHAN_BOND_SEQ_1_2_1 bit 0	MAIN[9][30][17]
CHAN_BOND_SEQ_1_2_1 bit 1	MAIN[9][31][17]
CHAN_BOND_SEQ_1_2_1 bit 2	MAIN[9][31][18]
CHAN_BOND_SEQ_1_2_1 bit 3	MAIN[9][30][18]
CHAN_BOND_SEQ_1_2_1 bit 4	MAIN[9][30][19]
CHAN_BOND_SEQ_1_2_1 bit 5	MAIN[9][31][19]
CHAN_BOND_SEQ_1_2_1 bit 6	MAIN[9][31][20]
CHAN_BOND_SEQ_1_2_1 bit 7	MAIN[9][30][20]
CHAN_BOND_SEQ_1_2_1 bit 8	MAIN[9][30][21]
CHAN_BOND_SEQ_1_2_1 bit 9	MAIN[9][31][21]
CHAN_BOND_SEQ_1_3_1 bit 0	MAIN[9][31][12]
CHAN_BOND_SEQ_1_3_1 bit 1	MAIN[9][30][12]
CHAN_BOND_SEQ_1_3_1 bit 2	MAIN[9][30][13]
CHAN_BOND_SEQ_1_3_1 bit 3	MAIN[9][31][13]
CHAN_BOND_SEQ_1_3_1 bit 4	MAIN[9][31][14]
CHAN_BOND_SEQ_1_3_1 bit 5	MAIN[9][30][14]
CHAN_BOND_SEQ_1_3_1 bit 6	MAIN[9][30][15]
CHAN_BOND_SEQ_1_3_1 bit 7	MAIN[9][31][15]
CHAN_BOND_SEQ_1_3_1 bit 8	MAIN[9][31][16]
CHAN_BOND_SEQ_1_3_1 bit 9	MAIN[9][30][16]
CHAN_BOND_SEQ_1_4_1 bit 0	MAIN[9][30][7]
CHAN_BOND_SEQ_1_4_1 bit 1	MAIN[9][31][7]
CHAN_BOND_SEQ_1_4_1 bit 2	MAIN[9][31][8]
CHAN_BOND_SEQ_1_4_1 bit 3	MAIN[9][30][8]
CHAN_BOND_SEQ_1_4_1 bit 4	MAIN[9][30][9]
CHAN_BOND_SEQ_1_4_1 bit 5	MAIN[9][31][9]
CHAN_BOND_SEQ_1_4_1 bit 6	MAIN[9][31][10]
CHAN_BOND_SEQ_1_4_1 bit 7	MAIN[9][30][10]
CHAN_BOND_SEQ_1_4_1 bit 8	MAIN[9][30][11]
CHAN_BOND_SEQ_1_4_1 bit 9	MAIN[9][31][11]
CHAN_BOND_SEQ_1_ENABLE_1 bit 0	MAIN[9][30][5]
CHAN_BOND_SEQ_1_ENABLE_1 bit 1	MAIN[9][31][5]
CHAN_BOND_SEQ_1_ENABLE_1 bit 2	MAIN[9][31][6]
CHAN_BOND_SEQ_1_ENABLE_1 bit 3	MAIN[9][30][6]
CHAN_BOND_SEQ_2_1_1 bit 0	MAIN[9][31][0]
CHAN_BOND_SEQ_2_1_1 bit 1	MAIN[9][30][0]
CHAN_BOND_SEQ_2_1_1 bit 2	MAIN[9][30][1]
CHAN_BOND_SEQ_2_1_1 bit 3	MAIN[9][31][1]
CHAN_BOND_SEQ_2_1_1 bit 4	MAIN[9][31][2]
CHAN_BOND_SEQ_2_1_1 bit 5	MAIN[9][30][2]
CHAN_BOND_SEQ_2_1_1 bit 6	MAIN[9][30][3]
CHAN_BOND_SEQ_2_1_1 bit 7	MAIN[9][31][3]
CHAN_BOND_SEQ_2_1_1 bit 8	MAIN[9][31][4]
CHAN_BOND_SEQ_2_1_1 bit 9	MAIN[9][30][4]
CHAN_BOND_SEQ_2_2_1 bit 0	MAIN[8][30][58]
CHAN_BOND_SEQ_2_2_1 bit 1	MAIN[8][30][59]
CHAN_BOND_SEQ_2_2_1 bit 2	MAIN[8][31][59]
CHAN_BOND_SEQ_2_2_1 bit 3	MAIN[8][31][60]
CHAN_BOND_SEQ_2_2_1 bit 4	MAIN[8][30][60]
CHAN_BOND_SEQ_2_2_1 bit 5	MAIN[8][30][61]
CHAN_BOND_SEQ_2_2_1 bit 6	MAIN[8][31][61]
CHAN_BOND_SEQ_2_2_1 bit 7	MAIN[8][31][62]
CHAN_BOND_SEQ_2_2_1 bit 8	MAIN[8][30][63]
CHAN_BOND_SEQ_2_2_1 bit 9	MAIN[8][31][63]
CHAN_BOND_SEQ_2_3_1 bit 0	MAIN[6][30][3]
CHAN_BOND_SEQ_2_3_1 bit 1	MAIN[6][31][3]
CHAN_BOND_SEQ_2_3_1 bit 2	MAIN[6][31][4]
CHAN_BOND_SEQ_2_3_1 bit 3	MAIN[6][30][4]
CHAN_BOND_SEQ_2_3_1 bit 4	MAIN[6][30][5]
CHAN_BOND_SEQ_2_3_1 bit 5	MAIN[6][31][5]
CHAN_BOND_SEQ_2_3_1 bit 6	MAIN[6][31][6]
CHAN_BOND_SEQ_2_3_1 bit 7	MAIN[6][30][6]
CHAN_BOND_SEQ_2_3_1 bit 8	MAIN[6][30][7]
CHAN_BOND_SEQ_2_3_1 bit 9	MAIN[8][31][58]
CHAN_BOND_SEQ_2_4_1 bit 0	MAIN[5][31][62]
CHAN_BOND_SEQ_2_4_1 bit 1	MAIN[5][30][62]
CHAN_BOND_SEQ_2_4_1 bit 2	MAIN[5][30][63]
CHAN_BOND_SEQ_2_4_1 bit 3	MAIN[5][31][63]
CHAN_BOND_SEQ_2_4_1 bit 4	MAIN[6][31][0]
CHAN_BOND_SEQ_2_4_1 bit 5	MAIN[6][30][0]
CHAN_BOND_SEQ_2_4_1 bit 6	MAIN[6][30][1]
CHAN_BOND_SEQ_2_4_1 bit 7	MAIN[6][31][1]
CHAN_BOND_SEQ_2_4_1 bit 8	MAIN[6][31][2]
CHAN_BOND_SEQ_2_4_1 bit 9	MAIN[6][30][2]
CHAN_BOND_SEQ_2_ENABLE_1 bit 0	MAIN[7][30][48]
CHAN_BOND_SEQ_2_ENABLE_1 bit 1	MAIN[7][31][48]
CHAN_BOND_SEQ_2_ENABLE_1 bit 2	MAIN[7][31][47]
CHAN_BOND_SEQ_2_ENABLE_1 bit 3	MAIN[7][30][47]
CLK_COR_SEQ_1_1_1 bit 0	MAIN[8][31][3]
CLK_COR_SEQ_1_1_1 bit 1	MAIN[8][30][3]
CLK_COR_SEQ_1_1_1 bit 2	MAIN[8][30][2]
CLK_COR_SEQ_1_1_1 bit 3	MAIN[8][31][2]
CLK_COR_SEQ_1_1_1 bit 4	MAIN[8][31][1]
CLK_COR_SEQ_1_1_1 bit 5	MAIN[8][30][1]
CLK_COR_SEQ_1_1_1 bit 6	MAIN[8][30][0]
CLK_COR_SEQ_1_1_1 bit 7	MAIN[8][31][0]
CLK_COR_SEQ_1_1_1 bit 8	MAIN[7][31][63]
CLK_COR_SEQ_1_1_1 bit 9	MAIN[7][30][63]
CLK_COR_SEQ_1_2_1 bit 0	MAIN[8][30][8]
CLK_COR_SEQ_1_2_1 bit 1	MAIN[8][31][8]
CLK_COR_SEQ_1_2_1 bit 2	MAIN[8][31][7]
CLK_COR_SEQ_1_2_1 bit 3	MAIN[8][30][7]
CLK_COR_SEQ_1_2_1 bit 4	MAIN[8][30][6]
CLK_COR_SEQ_1_2_1 bit 5	MAIN[8][31][6]
CLK_COR_SEQ_1_2_1 bit 6	MAIN[8][31][5]
CLK_COR_SEQ_1_2_1 bit 7	MAIN[8][30][5]
CLK_COR_SEQ_1_2_1 bit 8	MAIN[8][30][4]
CLK_COR_SEQ_1_2_1 bit 9	MAIN[8][31][4]
CLK_COR_SEQ_1_3_1 bit 0	MAIN[8][31][13]
CLK_COR_SEQ_1_3_1 bit 1	MAIN[8][30][13]
CLK_COR_SEQ_1_3_1 bit 2	MAIN[8][30][12]
CLK_COR_SEQ_1_3_1 bit 3	MAIN[8][31][12]
CLK_COR_SEQ_1_3_1 bit 4	MAIN[8][31][11]
CLK_COR_SEQ_1_3_1 bit 5	MAIN[8][30][11]
CLK_COR_SEQ_1_3_1 bit 6	MAIN[8][30][10]
CLK_COR_SEQ_1_3_1 bit 7	MAIN[8][31][10]
CLK_COR_SEQ_1_3_1 bit 8	MAIN[8][31][9]
CLK_COR_SEQ_1_3_1 bit 9	MAIN[8][30][9]
CLK_COR_SEQ_1_4_1 bit 0	MAIN[8][30][18]
CLK_COR_SEQ_1_4_1 bit 1	MAIN[8][31][18]
CLK_COR_SEQ_1_4_1 bit 2	MAIN[8][31][17]
CLK_COR_SEQ_1_4_1 bit 3	MAIN[8][30][17]
CLK_COR_SEQ_1_4_1 bit 4	MAIN[8][30][16]
CLK_COR_SEQ_1_4_1 bit 5	MAIN[8][31][16]
CLK_COR_SEQ_1_4_1 bit 6	MAIN[8][31][15]
CLK_COR_SEQ_1_4_1 bit 7	MAIN[8][30][15]
CLK_COR_SEQ_1_4_1 bit 8	MAIN[8][30][14]
CLK_COR_SEQ_1_4_1 bit 9	MAIN[8][31][14]
CLK_COR_SEQ_1_ENABLE_1 bit 0	MAIN[8][30][20]
CLK_COR_SEQ_1_ENABLE_1 bit 1	MAIN[8][31][20]
CLK_COR_SEQ_1_ENABLE_1 bit 2	MAIN[8][31][19]
CLK_COR_SEQ_1_ENABLE_1 bit 3	MAIN[8][30][19]
CLK_COR_SEQ_2_1_1 bit 0	MAIN[8][31][25]
CLK_COR_SEQ_2_1_1 bit 1	MAIN[8][30][25]
CLK_COR_SEQ_2_1_1 bit 2	MAIN[8][30][24]
CLK_COR_SEQ_2_1_1 bit 3	MAIN[8][31][24]
CLK_COR_SEQ_2_1_1 bit 4	MAIN[8][31][23]
CLK_COR_SEQ_2_1_1 bit 5	MAIN[8][30][23]
CLK_COR_SEQ_2_1_1 bit 6	MAIN[8][30][22]
CLK_COR_SEQ_2_1_1 bit 7	MAIN[8][31][22]
CLK_COR_SEQ_2_1_1 bit 8	MAIN[8][31][21]
CLK_COR_SEQ_2_1_1 bit 9	MAIN[8][30][21]
CLK_COR_SEQ_2_2_1 bit 0	MAIN[8][30][30]
CLK_COR_SEQ_2_2_1 bit 1	MAIN[8][31][30]
CLK_COR_SEQ_2_2_1 bit 2	MAIN[8][31][29]
CLK_COR_SEQ_2_2_1 bit 3	MAIN[8][30][29]
CLK_COR_SEQ_2_2_1 bit 4	MAIN[8][30][28]
CLK_COR_SEQ_2_2_1 bit 5	MAIN[8][31][28]
CLK_COR_SEQ_2_2_1 bit 6	MAIN[8][31][27]
CLK_COR_SEQ_2_2_1 bit 7	MAIN[8][30][27]
CLK_COR_SEQ_2_2_1 bit 8	MAIN[8][30][26]
CLK_COR_SEQ_2_2_1 bit 9	MAIN[8][31][26]
CLK_COR_SEQ_2_3_1 bit 0	MAIN[8][31][35]
CLK_COR_SEQ_2_3_1 bit 1	MAIN[8][30][35]
CLK_COR_SEQ_2_3_1 bit 2	MAIN[8][30][34]
CLK_COR_SEQ_2_3_1 bit 3	MAIN[8][31][34]
CLK_COR_SEQ_2_3_1 bit 4	MAIN[8][31][33]
CLK_COR_SEQ_2_3_1 bit 5	MAIN[8][30][33]
CLK_COR_SEQ_2_3_1 bit 6	MAIN[8][30][32]
CLK_COR_SEQ_2_3_1 bit 7	MAIN[8][31][32]
CLK_COR_SEQ_2_3_1 bit 8	MAIN[8][31][31]
CLK_COR_SEQ_2_3_1 bit 9	MAIN[8][30][31]
CLK_COR_SEQ_2_4_1 bit 0	MAIN[8][30][40]
CLK_COR_SEQ_2_4_1 bit 1	MAIN[8][31][40]
CLK_COR_SEQ_2_4_1 bit 2	MAIN[8][31][39]
CLK_COR_SEQ_2_4_1 bit 3	MAIN[8][30][39]
CLK_COR_SEQ_2_4_1 bit 4	MAIN[8][30][38]
CLK_COR_SEQ_2_4_1 bit 5	MAIN[8][31][38]
CLK_COR_SEQ_2_4_1 bit 6	MAIN[8][31][37]
CLK_COR_SEQ_2_4_1 bit 7	MAIN[8][30][37]
CLK_COR_SEQ_2_4_1 bit 8	MAIN[8][30][36]
CLK_COR_SEQ_2_4_1 bit 9	MAIN[8][31][36]
CLK_COR_SEQ_2_ENABLE_1 bit 0	MAIN[8][30][42]
CLK_COR_SEQ_2_ENABLE_1 bit 1	MAIN[8][31][42]
CLK_COR_SEQ_2_ENABLE_1 bit 2	MAIN[8][31][41]
CLK_COR_SEQ_2_ENABLE_1 bit 3	MAIN[8][30][41]
CM_TRIM_1 bit 0	MAIN[5][31][14]
CM_TRIM_1 bit 1	MAIN[5][31][13]
COMMA_10B_ENABLE_1 bit 0	MAIN[8][31][50]
COMMA_10B_ENABLE_1 bit 1	MAIN[8][31][49]
COMMA_10B_ENABLE_1 bit 2	MAIN[8][30][49]
COMMA_10B_ENABLE_1 bit 3	MAIN[8][30][48]
COMMA_10B_ENABLE_1 bit 4	MAIN[8][31][48]
COMMA_10B_ENABLE_1 bit 5	MAIN[8][31][47]
COMMA_10B_ENABLE_1 bit 6	MAIN[8][30][47]
COMMA_10B_ENABLE_1 bit 7	MAIN[8][30][46]
COMMA_10B_ENABLE_1 bit 8	MAIN[8][31][46]
COMMA_10B_ENABLE_1 bit 9	MAIN[8][31][45]
COM_BURST_VAL_1 bit 0	MAIN[8][30][45]
COM_BURST_VAL_1 bit 1	MAIN[8][30][44]
COM_BURST_VAL_1 bit 2	MAIN[8][31][44]
COM_BURST_VAL_1 bit 3	MAIN[8][31][43]
DFE_CFG_1 bit 0	MAIN[5][30][19]
DFE_CFG_1 bit 1	MAIN[5][30][18]
DFE_CFG_1 bit 2	MAIN[5][31][18]
DFE_CFG_1 bit 3	MAIN[5][31][17]
DFE_CFG_1 bit 4	MAIN[5][30][17]
DFE_CFG_1 bit 5	MAIN[5][30][16]
DFE_CFG_1 bit 6	MAIN[5][31][16]
DFE_CFG_1 bit 7	MAIN[5][31][15]
DFE_CFG_1 bit 8	MAIN[5][30][15]
DFE_CFG_1 bit 9	MAIN[5][30][14]
GEARBOX_ENDEC_1 bit 0	MAIN[5][31][21]
GEARBOX_ENDEC_1 bit 1	MAIN[5][30][21]
GEARBOX_ENDEC_1 bit 2	MAIN[5][30][20]
MCOMMA_10B_VALUE_1 bit 0	MAIN[8][30][57]
MCOMMA_10B_VALUE_1 bit 1	MAIN[8][30][56]
MCOMMA_10B_VALUE_1 bit 2	MAIN[8][31][56]
MCOMMA_10B_VALUE_1 bit 3	MAIN[8][31][55]
MCOMMA_10B_VALUE_1 bit 4	MAIN[8][30][55]
MCOMMA_10B_VALUE_1 bit 5	MAIN[8][30][54]
MCOMMA_10B_VALUE_1 bit 6	MAIN[8][31][54]
MCOMMA_10B_VALUE_1 bit 7	MAIN[8][31][53]
MCOMMA_10B_VALUE_1 bit 8	MAIN[8][30][53]
MCOMMA_10B_VALUE_1 bit 9	MAIN[8][30][52]
OOBDETECT_THRESHOLD_1 bit 0	MAIN[7][31][46]
OOBDETECT_THRESHOLD_1 bit 1	MAIN[7][31][45]
OOBDETECT_THRESHOLD_1 bit 2	MAIN[7][30][45]
PCOMMA_10B_VALUE_1 bit 0	MAIN[6][30][13]
PCOMMA_10B_VALUE_1 bit 1	MAIN[6][30][12]
PCOMMA_10B_VALUE_1 bit 2	MAIN[6][31][12]
PCOMMA_10B_VALUE_1 bit 3	MAIN[6][31][11]
PCOMMA_10B_VALUE_1 bit 4	MAIN[6][30][11]
PCOMMA_10B_VALUE_1 bit 5	MAIN[6][30][10]
PCOMMA_10B_VALUE_1 bit 6	MAIN[6][31][10]
PCOMMA_10B_VALUE_1 bit 7	MAIN[6][31][9]
PCOMMA_10B_VALUE_1 bit 8	MAIN[6][30][9]
PCOMMA_10B_VALUE_1 bit 9	MAIN[6][30][8]
RX_IDLE_HI_CNT_1 bit 0	MAIN[5][30][28]
RX_IDLE_HI_CNT_1 bit 1	MAIN[5][31][28]
RX_IDLE_HI_CNT_1 bit 2	MAIN[5][31][27]
RX_IDLE_HI_CNT_1 bit 3	MAIN[5][30][27]
RX_IDLE_LO_CNT_1 bit 0	MAIN[5][31][26]
RX_IDLE_LO_CNT_1 bit 1	MAIN[5][31][25]
RX_IDLE_LO_CNT_1 bit 2	MAIN[5][30][25]
RX_IDLE_LO_CNT_1 bit 3	MAIN[5][30][24]
SATA_BURST_VAL_1 bit 0	MAIN[6][30][53]
SATA_BURST_VAL_1 bit 1	MAIN[6][30][52]
SATA_BURST_VAL_1 bit 2	MAIN[6][31][52]
SATA_IDLE_VAL_1 bit 0	MAIN[6][30][54]
SATA_IDLE_VAL_1 bit 1	MAIN[6][31][54]
SATA_IDLE_VAL_1 bit 2	MAIN[6][31][53]
TXRX_INVERT_1 bit 0	MAIN[7][31][42]
TXRX_INVERT_1 bit 1	MAIN[7][31][41]
TXRX_INVERT_1 bit 2	MAIN[7][30][41]
TX_IDLE_DELAY_1 bit 0	MAIN[5][30][32]
TX_IDLE_DELAY_1 bit 1	MAIN[5][31][32]
TX_IDLE_DELAY_1 bit 2	MAIN[5][31][31]
PMA_CDR_SCAN_1 bit 0	MAIN[6][31][29]
PMA_CDR_SCAN_1 bit 1	MAIN[6][30][29]
PMA_CDR_SCAN_1 bit 2	MAIN[6][30][28]
PMA_CDR_SCAN_1 bit 3	MAIN[6][31][28]
PMA_CDR_SCAN_1 bit 4	MAIN[6][31][27]
PMA_CDR_SCAN_1 bit 5	MAIN[6][30][27]
PMA_CDR_SCAN_1 bit 6	MAIN[6][30][26]
PMA_CDR_SCAN_1 bit 7	MAIN[6][31][26]
PMA_CDR_SCAN_1 bit 8	MAIN[6][31][25]
PMA_CDR_SCAN_1 bit 9	MAIN[6][30][25]
PMA_CDR_SCAN_1 bit 10	MAIN[6][30][24]
PMA_CDR_SCAN_1 bit 11	MAIN[6][31][24]
PMA_CDR_SCAN_1 bit 12	MAIN[6][31][23]
PMA_CDR_SCAN_1 bit 13	MAIN[6][30][23]
PMA_CDR_SCAN_1 bit 14	MAIN[6][30][22]
PMA_CDR_SCAN_1 bit 15	MAIN[6][31][22]
PMA_CDR_SCAN_1 bit 16	MAIN[6][31][21]
PMA_CDR_SCAN_1 bit 17	MAIN[6][30][21]
PMA_CDR_SCAN_1 bit 18	MAIN[6][30][20]
PMA_CDR_SCAN_1 bit 19	MAIN[6][31][20]
PMA_CDR_SCAN_1 bit 20	MAIN[6][31][19]
PMA_CDR_SCAN_1 bit 21	MAIN[6][30][19]
PMA_CDR_SCAN_1 bit 22	MAIN[6][30][18]
PMA_CDR_SCAN_1 bit 23	MAIN[6][31][18]
PMA_CDR_SCAN_1 bit 24	MAIN[6][31][17]
PMA_CDR_SCAN_1 bit 25	MAIN[6][30][17]
PMA_CDR_SCAN_1 bit 26	MAIN[6][30][16]
PMA_RXSYNC_CFG_1 bit 0	MAIN[5][30][3]
PMA_RXSYNC_CFG_1 bit 1	MAIN[5][30][2]
PMA_RXSYNC_CFG_1 bit 2	MAIN[5][31][2]
PMA_RXSYNC_CFG_1 bit 3	MAIN[5][31][1]
PMA_RXSYNC_CFG_1 bit 4	MAIN[5][30][1]
PMA_RXSYNC_CFG_1 bit 5	MAIN[5][30][0]
PMA_RXSYNC_CFG_1 bit 6	MAIN[5][31][0]
PMA_RX_CFG_1 bit 0	MAIN[14][30][13]
PMA_RX_CFG_1 bit 1	MAIN[14][31][13]
PMA_RX_CFG_1 bit 2	MAIN[5][30][58]
PMA_RX_CFG_1 bit 3	MAIN[5][31][58]
PMA_RX_CFG_1 bit 4	MAIN[5][31][57]
PMA_RX_CFG_1 bit 5	MAIN[5][30][57]
PMA_RX_CFG_1 bit 6	MAIN[5][31][61]
PMA_RX_CFG_1 bit 7	MAIN[5][30][61]
PMA_RX_CFG_1 bit 8	MAIN[5][30][60]
PMA_RX_CFG_1 bit 9	MAIN[5][31][60]
PMA_RX_CFG_1 bit 10	MAIN[5][31][59]
PMA_RX_CFG_1 bit 11	MAIN[14][30][12]
PMA_RX_CFG_1 bit 12	MAIN[14][30][14]
PMA_RX_CFG_1 bit 13	MAIN[5][31][56]
PMA_RX_CFG_1 bit 14	MAIN[5][31][55]
PMA_RX_CFG_1 bit 15	MAIN[5][30][55]
PMA_RX_CFG_1 bit 16	MAIN[5][30][54]
PMA_RX_CFG_1 bit 17	MAIN[5][31][54]
PMA_RX_CFG_1 bit 18	MAIN[5][31][53]
PMA_RX_CFG_1 bit 19	MAIN[5][30][53]
PMA_RX_CFG_1 bit 20	MAIN[5][30][52]
PMA_RX_CFG_1 bit 21	MAIN[5][31][52]
PMA_RX_CFG_1 bit 22	MAIN[5][31][51]
PMA_RX_CFG_1 bit 23	MAIN[14][30][4]
PMA_RX_CFG_1 bit 24	MAIN[14][31][14]
PMA_TX_CFG_1 bit 0	MAIN[5][30][13]
PMA_TX_CFG_1 bit 1	MAIN[5][30][12]
PMA_TX_CFG_1 bit 2	MAIN[5][31][12]
PMA_TX_CFG_1 bit 3	MAIN[5][31][11]
PMA_TX_CFG_1 bit 4	MAIN[5][30][11]
PMA_TX_CFG_1 bit 5	MAIN[5][30][10]
PMA_TX_CFG_1 bit 6	MAIN[5][31][10]
PMA_TX_CFG_1 bit 7	MAIN[5][31][9]
PMA_TX_CFG_1 bit 8	MAIN[5][30][9]
PMA_TX_CFG_1 bit 9	MAIN[5][30][8]
PMA_TX_CFG_1 bit 10	MAIN[5][31][8]
PMA_TX_CFG_1 bit 11	MAIN[5][31][7]
PMA_TX_CFG_1 bit 12	MAIN[5][30][7]
PMA_TX_CFG_1 bit 13	MAIN[5][30][6]
PMA_TX_CFG_1 bit 14	MAIN[5][31][6]
PMA_TX_CFG_1 bit 15	MAIN[5][31][5]
PMA_TX_CFG_1 bit 16	MAIN[5][30][5]
PMA_TX_CFG_1 bit 17	MAIN[5][30][4]
PMA_TX_CFG_1 bit 18	MAIN[5][31][4]
PMA_TX_CFG_1 bit 19	MAIN[5][31][3]
PRBS_ERR_THRESHOLD_1 bit 0	MAIN[6][31][45]
PRBS_ERR_THRESHOLD_1 bit 1	MAIN[6][30][45]
PRBS_ERR_THRESHOLD_1 bit 2	MAIN[6][30][44]
PRBS_ERR_THRESHOLD_1 bit 3	MAIN[6][31][44]
PRBS_ERR_THRESHOLD_1 bit 4	MAIN[6][31][43]
PRBS_ERR_THRESHOLD_1 bit 5	MAIN[6][30][43]
PRBS_ERR_THRESHOLD_1 bit 6	MAIN[6][30][42]
PRBS_ERR_THRESHOLD_1 bit 7	MAIN[6][31][42]
PRBS_ERR_THRESHOLD_1 bit 8	MAIN[6][31][41]
PRBS_ERR_THRESHOLD_1 bit 9	MAIN[6][30][41]
PRBS_ERR_THRESHOLD_1 bit 10	MAIN[6][30][40]
PRBS_ERR_THRESHOLD_1 bit 11	MAIN[6][31][40]
PRBS_ERR_THRESHOLD_1 bit 12	MAIN[6][31][39]
PRBS_ERR_THRESHOLD_1 bit 13	MAIN[6][30][39]
PRBS_ERR_THRESHOLD_1 bit 14	MAIN[6][30][38]
PRBS_ERR_THRESHOLD_1 bit 15	MAIN[6][31][38]
PRBS_ERR_THRESHOLD_1 bit 16	MAIN[6][31][37]
PRBS_ERR_THRESHOLD_1 bit 17	MAIN[6][30][37]
PRBS_ERR_THRESHOLD_1 bit 18	MAIN[6][30][36]
PRBS_ERR_THRESHOLD_1 bit 19	MAIN[6][31][36]
PRBS_ERR_THRESHOLD_1 bit 20	MAIN[6][31][35]
PRBS_ERR_THRESHOLD_1 bit 21	MAIN[6][30][35]
PRBS_ERR_THRESHOLD_1 bit 22	MAIN[6][30][34]
PRBS_ERR_THRESHOLD_1 bit 23	MAIN[6][31][34]
PRBS_ERR_THRESHOLD_1 bit 24	MAIN[6][31][33]
PRBS_ERR_THRESHOLD_1 bit 25	MAIN[6][30][33]
PRBS_ERR_THRESHOLD_1 bit 26	MAIN[6][30][32]
PRBS_ERR_THRESHOLD_1 bit 27	MAIN[6][31][32]
PRBS_ERR_THRESHOLD_1 bit 28	MAIN[6][31][31]
PRBS_ERR_THRESHOLD_1 bit 29	MAIN[6][30][31]
PRBS_ERR_THRESHOLD_1 bit 30	MAIN[6][30][30]
PRBS_ERR_THRESHOLD_1 bit 31	MAIN[6][31][30]
TRANS_TIME_FROM_P2_1 bit 0	MAIN[7][30][15]
TRANS_TIME_FROM_P2_1 bit 1	MAIN[7][30][14]
TRANS_TIME_FROM_P2_1 bit 2	MAIN[7][31][14]
TRANS_TIME_FROM_P2_1 bit 3	MAIN[7][31][13]
TRANS_TIME_FROM_P2_1 bit 4	MAIN[7][30][13]
TRANS_TIME_FROM_P2_1 bit 5	MAIN[7][30][12]
TRANS_TIME_FROM_P2_1 bit 6	MAIN[7][31][12]
TRANS_TIME_FROM_P2_1 bit 7	MAIN[7][31][11]
TRANS_TIME_FROM_P2_1 bit 8	MAIN[7][30][11]
TRANS_TIME_FROM_P2_1 bit 9	MAIN[7][30][10]
TRANS_TIME_FROM_P2_1 bit 10	MAIN[7][31][10]
TRANS_TIME_FROM_P2_1 bit 11	MAIN[7][31][9]
TRANS_TIME_NON_P2_1 bit 0	MAIN[7][30][21]
TRANS_TIME_NON_P2_1 bit 1	MAIN[7][30][20]
TRANS_TIME_NON_P2_1 bit 2	MAIN[7][31][20]
TRANS_TIME_NON_P2_1 bit 3	MAIN[7][31][19]
TRANS_TIME_NON_P2_1 bit 4	MAIN[7][30][19]
TRANS_TIME_NON_P2_1 bit 5	MAIN[7][30][18]
TRANS_TIME_NON_P2_1 bit 6	MAIN[7][31][18]
TRANS_TIME_NON_P2_1 bit 7	MAIN[7][31][17]
TRANS_TIME_TO_P2_1 bit 0	MAIN[7][31][30]
TRANS_TIME_TO_P2_1 bit 1	MAIN[7][31][29]
TRANS_TIME_TO_P2_1 bit 2	MAIN[7][30][29]
TRANS_TIME_TO_P2_1 bit 3	MAIN[7][30][28]
TRANS_TIME_TO_P2_1 bit 4	MAIN[7][31][28]
TRANS_TIME_TO_P2_1 bit 5	MAIN[7][31][27]
TRANS_TIME_TO_P2_1 bit 6	MAIN[7][30][27]
TRANS_TIME_TO_P2_1 bit 7	MAIN[7][30][26]
TRANS_TIME_TO_P2_1 bit 8	MAIN[7][31][26]
TRANS_TIME_TO_P2_1 bit 9	MAIN[7][31][25]
TX_DETECT_RX_CFG_1 bit 0	MAIN[7][30][40]
TX_DETECT_RX_CFG_1 bit 1	MAIN[7][31][40]
TX_DETECT_RX_CFG_1 bit 2	MAIN[7][31][39]
TX_DETECT_RX_CFG_1 bit 3	MAIN[7][30][39]
TX_DETECT_RX_CFG_1 bit 4	MAIN[7][30][38]
TX_DETECT_RX_CFG_1 bit 5	MAIN[7][31][38]
TX_DETECT_RX_CFG_1 bit 6	MAIN[7][31][37]
TX_DETECT_RX_CFG_1 bit 7	MAIN[7][30][37]
TX_DETECT_RX_CFG_1 bit 8	MAIN[7][30][36]
TX_DETECT_RX_CFG_1 bit 9	MAIN[7][31][36]
TX_DETECT_RX_CFG_1 bit 10	MAIN[7][31][35]
TX_DETECT_RX_CFG_1 bit 11	MAIN[7][30][35]
TX_DETECT_RX_CFG_1 bit 12	MAIN[7][30][34]
TX_DETECT_RX_CFG_1 bit 13	MAIN[7][31][34]

virtex5 GTX enum GTP_MUX_CLKIN
GTX_DUAL.MUX_CLKIN	MAIN[5][31][34]	MAIN[5][30][34]	MAIN[5][30][35]
CLKPN	0	1	1
GREFCLK	0	0	0
CLKOUT_NORTH_S	1	0	1
CLKOUT_SOUTH_N	0	0	1

virtex5 GTX enum GTP_MUX_CLKOUT_NORTH
GTX_DUAL.MUX_CLKOUT_NORTH	MAIN[5][31][36]
CLKPN	1
CLKOUT_NORTH_S	0

virtex5 GTX enum GTP_MUX_CLKOUT_SOUTH
GTX_DUAL.MUX_CLKOUT_SOUTH	MAIN[5][31][35]
CLKPN	1
CLKOUT_SOUTH_N	0

virtex5 GTX enum GTP_CLK25_DIVIDER
GTX_DUAL.CLK25_DIVIDER	MAIN[9][30][52]	MAIN[9][30][53]	MAIN[9][31][53]
_1	0	0	0
_2	0	0	1
_3	0	1	0
_4	0	1	1
_5	1	0	0
_6	1	0	1
_10	1	1	0
_12	1	1	1

virtex5 GTX enum GTP_OOB_CLK_DIVIDER
GTX_DUAL.OOB_CLK_DIVIDER	MAIN[9][31][54]	MAIN[9][30][54]	MAIN[9][30][55]
_1	0	0	0
_2	0	0	1
_4	0	1	0
_6	0	1	1
_8	1	0	0
_10	1	0	1
_12	1	1	0
_14	1	1	1

virtex5 GTX enum GTP_PLL_DIVSEL_FB
GTX_DUAL.PLL_DIVSEL_FB	MAIN[10][30][7]	MAIN[10][31][7]	MAIN[10][31][8]	MAIN[10][31][6]
_1	0	0	0	1
_2	0	0	0	0
_3	0	0	1	0
_4	0	1	0	0
_5	0	1	1	0
_8	1	1	0	0
_10	1	1	1	0

virtex5 GTX enum GTP_PLL_DIVSEL_REF
GTX_DUAL.PLL_DIVSEL_REF	MAIN[5][31][38]	MAIN[5][31][37]	MAIN[5][30][37]	MAIN[5][30][36]	MAIN[5][30][38]
_1	0	0	0	0	1
_2	0	0	0	0	0
_3	0	0	0	1	0
_4	0	0	1	0	0
_5	0	0	1	1	0
_6	0	1	0	1	0
_8	0	1	1	0	0
_10	0	1	1	1	0
_12	1	1	0	1	0
_16	1	1	1	0	0
_20	1	1	1	1	0

virtex5 GTX enum GTP_ALIGN_COMMA_WORD
GTX_DUAL.ALIGN_COMMA_WORD_0	MAIN[10][31][30]
GTX_DUAL.ALIGN_COMMA_WORD_1	MAIN[9][31][33]
_1	0
_2	1

virtex5 GTX enum GTP_CHAN_BOND_MODE
GTX_DUAL.CHAN_BOND_MODE_0	MAIN[10][31][36]	MAIN[10][30][36]
GTX_DUAL.CHAN_BOND_MODE_1	MAIN[9][31][27]	MAIN[9][30][27]
NONE	0	0
MASTER	0	1
SLAVE	1	0

virtex5 GTX enum GTP_SEQ_LEN
GTX_DUAL.CHAN_BOND_SEQ_LEN_0	MAIN[12][31][14]	MAIN[12][31][13]
GTX_DUAL.CLK_COR_ADJ_LEN_0	MAIN[12][30][13]	MAIN[12][30][12]
GTX_DUAL.CLK_COR_DET_LEN_0	MAIN[12][31][12]	MAIN[12][31][11]
GTX_DUAL.CHAN_BOND_SEQ_LEN_1	MAIN[7][31][49]	MAIN[7][31][50]
GTX_DUAL.CLK_COR_ADJ_LEN_1	MAIN[7][30][50]	MAIN[7][30][51]
GTX_DUAL.CLK_COR_DET_LEN_1	MAIN[7][31][51]	MAIN[7][31][52]
_1	0	0
_2	0	1
_3	1	0
_4	1	1

virtex5 GTX enum GTP_PLL_DIVSEL_OUT
GTX_DUAL.PLL_RXDIVSEL_OUT_0	MAIN[13][31][49]	MAIN[13][30][49]
GTX_DUAL.PLL_TXDIVSEL_OUT_0	MAIN[13][31][48]	MAIN[13][31][47]
GTX_DUAL.PLL_RXDIVSEL_OUT_1	MAIN[6][31][15]	MAIN[6][31][16]
GTX_DUAL.PLL_TXDIVSEL_OUT_1	MAIN[5][31][41]	MAIN[5][31][42]
_1	0	0
_2	0	1
_4	1	0

virtex5 GTX enum GT_RX_LOS_INVALID_INCR
GTX_DUAL.RX_LOS_INVALID_INCR_0	MAIN[13][30][16]	MAIN[13][31][16]	MAIN[13][31][15]
GTX_DUAL.RX_LOS_INVALID_INCR_1	MAIN[6][30][47]	MAIN[6][31][47]	MAIN[6][31][48]
_1	0	0	0
_2	0	0	1
_4	0	1	0
_8	0	1	1
_16	1	0	0
_32	1	0	1
_64	1	1	0
_128	1	1	1

virtex5 GTX enum GT_RX_LOS_THRESHOLD
GTX_DUAL.RX_LOS_THRESHOLD_0	MAIN[13][30][14]	MAIN[13][31][14]	MAIN[13][31][13]
GTX_DUAL.RX_LOS_THRESHOLD_1	MAIN[6][30][49]	MAIN[6][31][49]	MAIN[6][31][50]
_4	0	0	0
_8	0	0	1
_16	0	1	0
_32	0	1	1
_64	1	0	0
_128	1	0	1
_256	1	1	0
_512	1	1	1

virtex5 GTX enum GTP_RX_SLIDE_MODE
GTX_DUAL.RX_SLIDE_MODE_0	MAIN[13][30][13]
GTX_DUAL.RX_SLIDE_MODE_1	MAIN[6][30][50]
PCS	0
PMA	1

virtex5 GTX enum GTP_RX_STATUS_FMT
GTX_DUAL.RX_STATUS_FMT_0	MAIN[13][30][12]
GTX_DUAL.RX_STATUS_FMT_1	MAIN[6][30][51]
PCIE	0
SATA	1

virtex5 GTX enum GTP_RX_XCLK_SEL
GTX_DUAL.RX_XCLK_SEL_0	MAIN[13][31][12]
GTX_DUAL.RX_XCLK_SEL_1	MAIN[6][31][51]
RXUSR	1
RXREC	0

virtex5 GTX enum GTP_TX_XCLK_SEL
GTX_DUAL.TX_XCLK_SEL_0	MAIN[12][31][20]
GTX_DUAL.TX_XCLK_SEL_1	MAIN[7][31][43]
TXUSR	1
TXOUT	0

virtex5 GTX enum GTP_TERMINATION_IMP
GTX_DUAL.TERMINATION_IMP_0	MAIN[12][30][54]
GTX_DUAL.TERMINATION_IMP_1	MAIN[7][30][9]
_50	0
_75	1

Bels CRC32

virtex5 GTX bel CRC32 pins
Pin	Direction	CRC32[0]	CRC32[1]	CRC32[2]	CRC32[3]
CRCCLK	in	CELL[1].IMUX_CLK[1] invert by !HCLK[18][15]	CELL[6].IMUX_CLK[1] invert by !HCLK[19][12]	CELL[18].IMUX_CLK[0] invert by !HCLK[18][13]	CELL[13].IMUX_CLK[0] invert by !HCLK[18][14]
CRCRESET	in	CELL[2].IMUX_IMUX_DELAY[5]	CELL[8].IMUX_IMUX_DELAY[0]	CELL[17].IMUX_IMUX_DELAY[0]	CELL[11].IMUX_IMUX_DELAY[5]
CRCDATAVALID	in	CELL[3].IMUX_IMUX_DELAY[22]	CELL[8].IMUX_IMUX_DELAY[35]	CELL[16].IMUX_IMUX_DELAY[7]	CELL[11].IMUX_IMUX_DELAY[30]
CRCDATAWIDTH[0]	in	CELL[3].IMUX_IMUX_DELAY[40]	CELL[8].IMUX_IMUX_DELAY[11]	CELL[16].IMUX_IMUX_DELAY[6]	CELL[11].IMUX_IMUX_DELAY[24]
CRCDATAWIDTH[1]	in	CELL[3].IMUX_IMUX_DELAY[23]	CELL[8].IMUX_IMUX_DELAY[34]	CELL[16].IMUX_IMUX_DELAY[1]	CELL[11].IMUX_IMUX_DELAY[13]
CRCDATAWIDTH[2]	in	CELL[3].IMUX_IMUX_DELAY[21]	CELL[3].IMUX_IMUX_DELAY[21]	CELL[16].IMUX_IMUX_DELAY[8]	CELL[16].IMUX_IMUX_DELAY[8]
CRCIN[0]	in	CELL[3].IMUX_IMUX_DELAY[17]	CELL[7].IMUX_IMUX_DELAY[47]	CELL[16].IMUX_IMUX_DELAY[36]	CELL[12].IMUX_IMUX_DELAY[0]
CRCIN[1]	in	CELL[3].IMUX_IMUX_DELAY[16]	CELL[7].IMUX_IMUX_DELAY[46]	CELL[16].IMUX_IMUX_DELAY[37]	CELL[12].IMUX_IMUX_DELAY[1]
CRCIN[2]	in	CELL[3].IMUX_IMUX_DELAY[15]	CELL[7].IMUX_IMUX_DELAY[45]	CELL[16].IMUX_IMUX_DELAY[38]	CELL[12].IMUX_IMUX_DELAY[2]
CRCIN[3]	in	CELL[3].IMUX_IMUX_DELAY[14]	CELL[7].IMUX_IMUX_DELAY[44]	CELL[16].IMUX_IMUX_DELAY[39]	CELL[12].IMUX_IMUX_DELAY[9]
CRCIN[4]	in	CELL[3].IMUX_IMUX_DELAY[13]	CELL[7].IMUX_IMUX_DELAY[43]	CELL[16].IMUX_IMUX_DELAY[40]	CELL[12].IMUX_IMUX_DELAY[45]
CRCIN[5]	in	CELL[3].IMUX_IMUX_DELAY[12]	CELL[7].IMUX_IMUX_DELAY[42]	CELL[16].IMUX_IMUX_DELAY[35]	CELL[12].IMUX_IMUX_DELAY[35]
CRCIN[6]	in	CELL[3].IMUX_IMUX_DELAY[37]	CELL[7].IMUX_IMUX_DELAY[37]	CELL[16].IMUX_IMUX_DELAY[10]	CELL[12].IMUX_IMUX_DELAY[10]
CRCIN[7]	in	CELL[3].IMUX_IMUX_DELAY[36]	CELL[7].IMUX_IMUX_DELAY[36]	CELL[16].IMUX_IMUX_DELAY[11]	CELL[12].IMUX_IMUX_DELAY[11]
CRCIN[8]	in	CELL[2].IMUX_IMUX_DELAY[17]	CELL[6].IMUX_IMUX_DELAY[47]	CELL[17].IMUX_IMUX_DELAY[30]	CELL[13].IMUX_IMUX_DELAY[6]
CRCIN[9]	in	CELL[2].IMUX_IMUX_DELAY[16]	CELL[6].IMUX_IMUX_DELAY[46]	CELL[17].IMUX_IMUX_DELAY[31]	CELL[13].IMUX_IMUX_DELAY[7]
CRCIN[10]	in	CELL[2].IMUX_IMUX_DELAY[15]	CELL[6].IMUX_IMUX_DELAY[45]	CELL[17].IMUX_IMUX_DELAY[32]	CELL[13].IMUX_IMUX_DELAY[8]
CRCIN[11]	in	CELL[2].IMUX_IMUX_DELAY[14]	CELL[6].IMUX_IMUX_DELAY[44]	CELL[17].IMUX_IMUX_DELAY[33]	CELL[13].IMUX_IMUX_DELAY[9]
CRCIN[12]	in	CELL[2].IMUX_IMUX_DELAY[13]	CELL[6].IMUX_IMUX_DELAY[43]	CELL[17].IMUX_IMUX_DELAY[34]	CELL[13].IMUX_IMUX_DELAY[4]
CRCIN[13]	in	CELL[2].IMUX_IMUX_DELAY[12]	CELL[6].IMUX_IMUX_DELAY[42]	CELL[17].IMUX_IMUX_DELAY[35]	CELL[13].IMUX_IMUX_DELAY[5]
CRCIN[14]	in	CELL[2].IMUX_IMUX_DELAY[37]	CELL[6].IMUX_IMUX_DELAY[37]	CELL[17].IMUX_IMUX_DELAY[46]	CELL[13].IMUX_IMUX_DELAY[10]
CRCIN[15]	in	CELL[2].IMUX_IMUX_DELAY[36]	CELL[6].IMUX_IMUX_DELAY[36]	CELL[17].IMUX_IMUX_DELAY[47]	CELL[13].IMUX_IMUX_DELAY[11]
CRCIN[16]	in	CELL[1].IMUX_IMUX_DELAY[23]	CELL[5].IMUX_IMUX_DELAY[47]	CELL[18].IMUX_IMUX_DELAY[6]	CELL[14].IMUX_IMUX_DELAY[6]
CRCIN[17]	in	CELL[1].IMUX_IMUX_DELAY[22]	CELL[5].IMUX_IMUX_DELAY[46]	CELL[18].IMUX_IMUX_DELAY[7]	CELL[14].IMUX_IMUX_DELAY[7]
CRCIN[18]	in	CELL[1].IMUX_IMUX_DELAY[45]	CELL[5].IMUX_IMUX_DELAY[45]	CELL[18].IMUX_IMUX_DELAY[8]	CELL[14].IMUX_IMUX_DELAY[8]
CRCIN[19]	in	CELL[1].IMUX_IMUX_DELAY[44]	CELL[5].IMUX_IMUX_DELAY[44]	CELL[18].IMUX_IMUX_DELAY[21]	CELL[14].IMUX_IMUX_DELAY[9]
CRCIN[20]	in	CELL[1].IMUX_IMUX_DELAY[43]	CELL[5].IMUX_IMUX_DELAY[43]	CELL[18].IMUX_IMUX_DELAY[10]	CELL[14].IMUX_IMUX_DELAY[4]
CRCIN[21]	in	CELL[1].IMUX_IMUX_DELAY[42]	CELL[5].IMUX_IMUX_DELAY[42]	CELL[18].IMUX_IMUX_DELAY[11]	CELL[14].IMUX_IMUX_DELAY[5]
CRCIN[22]	in	CELL[1].IMUX_IMUX_DELAY[19]	CELL[5].IMUX_IMUX_DELAY[37]	CELL[18].IMUX_IMUX_DELAY[40]	CELL[14].IMUX_IMUX_DELAY[10]
CRCIN[23]	in	CELL[1].IMUX_IMUX_DELAY[18]	CELL[5].IMUX_IMUX_DELAY[36]	CELL[18].IMUX_IMUX_DELAY[41]	CELL[14].IMUX_IMUX_DELAY[11]
CRCIN[24]	in	CELL[0].IMUX_IMUX_DELAY[23]	CELL[4].IMUX_IMUX_DELAY[47]	CELL[19].IMUX_IMUX_DELAY[24]	CELL[15].IMUX_IMUX_DELAY[6]
CRCIN[25]	in	CELL[0].IMUX_IMUX_DELAY[22]	CELL[4].IMUX_IMUX_DELAY[46]	CELL[19].IMUX_IMUX_DELAY[25]	CELL[15].IMUX_IMUX_DELAY[7]
CRCIN[26]	in	CELL[0].IMUX_IMUX_DELAY[21]	CELL[4].IMUX_IMUX_DELAY[45]	CELL[19].IMUX_IMUX_DELAY[26]	CELL[15].IMUX_IMUX_DELAY[8]
CRCIN[27]	in	CELL[0].IMUX_IMUX_DELAY[20]	CELL[4].IMUX_IMUX_DELAY[44]	CELL[19].IMUX_IMUX_DELAY[21]	CELL[15].IMUX_IMUX_DELAY[9]
CRCIN[28]	in	CELL[0].IMUX_IMUX_DELAY[25]	CELL[4].IMUX_IMUX_DELAY[43]	CELL[19].IMUX_IMUX_DELAY[10]	CELL[15].IMUX_IMUX_DELAY[4]
CRCIN[29]	in	CELL[0].IMUX_IMUX_DELAY[24]	CELL[4].IMUX_IMUX_DELAY[42]	CELL[19].IMUX_IMUX_DELAY[11]	CELL[15].IMUX_IMUX_DELAY[5]
CRCIN[30]	in	CELL[0].IMUX_IMUX_DELAY[43]	CELL[4].IMUX_IMUX_DELAY[37]	CELL[19].IMUX_IMUX_DELAY[40]	CELL[15].IMUX_IMUX_DELAY[10]
CRCIN[31]	in	CELL[0].IMUX_IMUX_DELAY[42]	CELL[4].IMUX_IMUX_DELAY[36]	CELL[19].IMUX_IMUX_DELAY[41]	CELL[15].IMUX_IMUX_DELAY[11]
CRCOUT[0]	out	CELL[3].OUT_BEL[6]	CELL[9].OUT_BEL[11]	CELL[16].OUT_BEL[13]	CELL[10].OUT_BEL[4]
CRCOUT[1]	out	CELL[3].OUT_BEL[4]	CELL[9].OUT_BEL[3]	CELL[16].OUT_BEL[3]	CELL[10].OUT_BEL[23]
CRCOUT[2]	out	CELL[3].OUT_BEL[18]	CELL[9].OUT_BEL[14]	CELL[16].OUT_BEL[15]	CELL[10].OUT_BEL[16]
CRCOUT[3]	out	CELL[2].OUT_BEL[21]	CELL[9].OUT_BEL[13]	CELL[17].OUT_BEL[8]	CELL[10].OUT_BEL[2]
CRCOUT[4]	out	CELL[2].OUT_BEL[6]	CELL[9].OUT_BEL[4]	CELL[17].OUT_BEL[1]	CELL[10].OUT_BEL[6]
CRCOUT[5]	out	CELL[2].OUT_BEL[20]	CELL[9].OUT_BEL[0]	CELL[17].OUT_BEL[13]	CELL[10].OUT_BEL[7]
CRCOUT[6]	out	CELL[2].OUT_BEL[14]	CELL[9].OUT_BEL[18]	CELL[17].OUT_BEL[19]	CELL[10].OUT_BEL[11]
CRCOUT[7]	out	CELL[2].OUT_BEL[23]	CELL[9].OUT_BEL[12]	CELL[17].OUT_BEL[14]	CELL[10].OUT_BEL[15]
CRCOUT[8]	out	CELL[2].OUT_BEL[13]	CELL[9].OUT_BEL[8]	CELL[17].OUT_BEL[20]	CELL[10].OUT_BEL[21]
CRCOUT[9]	out	CELL[2].OUT_BEL[1]	CELL[8].OUT_BEL[17]	CELL[17].OUT_BEL[6]	CELL[11].OUT_BEL[12]
CRCOUT[10]	out	CELL[2].OUT_BEL[22]	CELL[8].OUT_BEL[15]	CELL[17].OUT_BEL[15]	CELL[11].OUT_BEL[4]
CRCOUT[11]	out	CELL[2].OUT_BEL[12]	CELL[8].OUT_BEL[11]	CELL[17].OUT_BEL[17]	CELL[11].OUT_BEL[22]
CRCOUT[12]	out	CELL[1].OUT_BEL[17]	CELL[8].OUT_BEL[6]	CELL[18].OUT_BEL[12]	CELL[11].OUT_BEL[5]
CRCOUT[13]	out	CELL[1].OUT_BEL[16]	CELL[8].OUT_BEL[2]	CELL[18].OUT_BEL[9]	CELL[11].OUT_BEL[13]
CRCOUT[14]	out	CELL[1].OUT_BEL[23]	CELL[8].OUT_BEL[16]	CELL[18].OUT_BEL[10]	CELL[11].OUT_BEL[19]
CRCOUT[15]	out	CELL[1].OUT_BEL[13]	CELL[8].OUT_BEL[10]	CELL[18].OUT_BEL[6]	CELL[11].OUT_BEL[23]
CRCOUT[16]	out	CELL[1].OUT_BEL[5]	CELL[8].OUT_BEL[23]	CELL[18].OUT_BEL[3]	CELL[11].OUT_BEL[10]
CRCOUT[17]	out	CELL[1].OUT_BEL[1]	CELL[8].OUT_BEL[9]	CELL[18].OUT_BEL[7]	CELL[11].OUT_BEL[16]
CRCOUT[18]	out	CELL[1].OUT_BEL[22]	CELL[8].OUT_BEL[5]	CELL[18].OUT_BEL[17]	CELL[11].OUT_BEL[3]
CRCOUT[19]	out	CELL[1].OUT_BEL[12]	CELL[8].OUT_BEL[0]	CELL[18].OUT_BEL[21]	CELL[11].OUT_BEL[7]
CRCOUT[20]	out	CELL[0].OUT_BEL[21]	CELL[7].OUT_BEL[21]	CELL[19].OUT_BEL[12]	CELL[12].OUT_BEL[8]
CRCOUT[21]	out	CELL[0].OUT_BEL[15]	CELL[7].OUT_BEL[17]	CELL[19].OUT_BEL[4]	CELL[12].OUT_BEL[18]
CRCOUT[22]	out	CELL[0].OUT_BEL[7]	CELL[7].OUT_BEL[3]	CELL[19].OUT_BEL[1]	CELL[12].OUT_BEL[4]
CRCOUT[23]	out	CELL[0].OUT_BEL[3]	CELL[7].OUT_BEL[12]	CELL[19].OUT_BEL[5]	CELL[12].OUT_BEL[17]
CRCOUT[24]	out	CELL[0].OUT_BEL[20]	CELL[6].OUT_BEL[15]	CELL[19].OUT_BEL[19]	CELL[13].OUT_BEL[18]
CRCOUT[25]	out	CELL[0].OUT_BEL[14]	CELL[6].OUT_BEL[14]	CELL[19].OUT_BEL[20]	CELL[13].OUT_BEL[19]
CRCOUT[26]	out	CELL[0].OUT_BEL[23]	CELL[6].OUT_BEL[12]	CELL[19].OUT_BEL[10]	CELL[13].OUT_BEL[17]
CRCOUT[27]	out	CELL[0].OUT_BEL[13]	CELL[5].OUT_BEL[21]	CELL[19].OUT_BEL[6]	CELL[14].OUT_BEL[18]
CRCOUT[28]	out	CELL[0].OUT_BEL[5]	CELL[5].OUT_BEL[7]	CELL[19].OUT_BEL[3]	CELL[14].OUT_BEL[4]
CRCOUT[29]	out	CELL[0].OUT_BEL[1]	CELL[5].OUT_BEL[5]	CELL[19].OUT_BEL[7]	CELL[14].OUT_BEL[6]
CRCOUT[30]	out	CELL[0].OUT_BEL[22]	CELL[5].OUT_BEL[22]	CELL[19].OUT_BEL[11]	CELL[14].OUT_BEL[17]
CRCOUT[31]	out	CELL[0].OUT_BEL[4]	CELL[4].OUT_BEL[21]	CELL[19].OUT_BEL[21]	CELL[15].OUT_BEL[18]

virtex5 GTX bel CRC32 attribute bits
Attribute	CRC32[0]	CRC32[1]	CRC32[2]	CRC32[3]
CRC_INIT bit 0	MAIN[3][29][24]	MAIN[9][29][27]	MAIN[16][29][39]	MAIN[10][29][36]
CRC_INIT bit 1	MAIN[3][29][22]	MAIN[9][29][26]	MAIN[16][29][41]	MAIN[10][29][37]
CRC_INIT bit 2	MAIN[3][29][20]	MAIN[9][28][25]	MAIN[16][29][43]	MAIN[10][28][38]
CRC_INIT bit 3	MAIN[3][29][18]	MAIN[9][29][24]	MAIN[16][29][45]	MAIN[10][29][39]
CRC_INIT bit 4	MAIN[3][29][16]	MAIN[9][28][23]	MAIN[16][29][47]	MAIN[10][28][40]
CRC_INIT bit 5	MAIN[3][29][14]	MAIN[9][29][22]	MAIN[16][29][49]	MAIN[10][29][41]
CRC_INIT bit 6	MAIN[3][29][12]	MAIN[9][28][21]	MAIN[16][29][51]	MAIN[10][28][42]
CRC_INIT bit 7	MAIN[3][29][10]	MAIN[9][29][20]	MAIN[16][29][53]	MAIN[10][29][43]
CRC_INIT bit 8	MAIN[3][29][8]	MAIN[9][28][19]	MAIN[16][29][55]	MAIN[10][28][44]
CRC_INIT bit 9	MAIN[3][29][5]	MAIN[9][29][18]	MAIN[16][29][58]	MAIN[10][29][45]
CRC_INIT bit 10	MAIN[3][29][3]	MAIN[9][28][17]	MAIN[16][29][60]	MAIN[10][28][46]
CRC_INIT bit 11	MAIN[3][29][1]	MAIN[9][29][15]	MAIN[16][29][62]	MAIN[10][29][48]
CRC_INIT bit 12	MAIN[2][29][63]	MAIN[9][28][14]	MAIN[17][29][0]	MAIN[10][28][49]
CRC_INIT bit 13	MAIN[2][29][61]	MAIN[9][29][13]	MAIN[17][29][2]	MAIN[10][29][50]
CRC_INIT bit 14	MAIN[2][29][59]	MAIN[9][28][12]	MAIN[17][29][4]	MAIN[10][28][51]
CRC_INIT bit 15	MAIN[2][29][57]	MAIN[9][29][12]	MAIN[17][29][6]	MAIN[10][29][51]
CRC_INIT bit 16	MAIN[2][28][55]	MAIN[9][28][11]	MAIN[17][28][8]	MAIN[10][28][52]
CRC_INIT bit 17	MAIN[2][28][53]	MAIN[9][29][10]	MAIN[17][28][10]	MAIN[10][29][53]
CRC_INIT bit 18	MAIN[2][28][51]	MAIN[9][28][9]	MAIN[17][28][12]	MAIN[10][28][54]
CRC_INIT bit 19	MAIN[2][28][49]	MAIN[9][28][8]	MAIN[17][28][14]	MAIN[10][28][55]
CRC_INIT bit 20	MAIN[2][28][47]	MAIN[9][29][7]	MAIN[17][28][16]	MAIN[10][29][56]
CRC_INIT bit 21	MAIN[2][28][45]	MAIN[9][28][6]	MAIN[17][28][18]	MAIN[10][28][57]
CRC_INIT bit 22	MAIN[2][28][43]	MAIN[9][29][6]	MAIN[17][28][20]	MAIN[10][29][57]
CRC_INIT bit 23	MAIN[2][28][41]	MAIN[9][28][4]	MAIN[17][28][22]	MAIN[10][28][59]
CRC_INIT bit 24	MAIN[2][28][39]	MAIN[9][29][3]	MAIN[17][28][24]	MAIN[10][29][60]
CRC_INIT bit 25	MAIN[2][28][36]	MAIN[9][28][3]	MAIN[17][28][27]	MAIN[10][28][60]
CRC_INIT bit 26	MAIN[2][28][35]	MAIN[9][29][1]	MAIN[17][28][28]	MAIN[10][29][62]
CRC_INIT bit 27	MAIN[2][28][32]	MAIN[9][28][0]	MAIN[17][28][31]	MAIN[10][28][63]
CRC_INIT bit 28	MAIN[2][28][30]	MAIN[8][29][63]	MAIN[17][28][33]	MAIN[11][29][0]
CRC_INIT bit 29	MAIN[2][28][28]	MAIN[8][28][62]	MAIN[17][28][35]	MAIN[11][28][1]
CRC_INIT bit 30	MAIN[2][28][26]	MAIN[8][29][61]	MAIN[17][28][37]	MAIN[11][29][2]
CRC_INIT bit 31	MAIN[2][28][24]	MAIN[8][28][60]	MAIN[17][28][39]	MAIN[11][28][3]
ENABLE64	MAIN[2][29][22]	-	MAIN[17][29][41]	-

Bel wires

virtex5 GTX bel wires
Wire	Pins
CELL[0].IMUX_IMUX_DELAY[0]	GTX_DUAL.TXDATA1[16]
CELL[0].IMUX_IMUX_DELAY[4]	GTX_DUAL.TXELECIDLE1
CELL[0].IMUX_IMUX_DELAY[6]	GTX_DUAL.TXDIFFCTRL1[2]
CELL[0].IMUX_IMUX_DELAY[7]	GTX_DUAL.TXDIFFCTRL1[1]
CELL[0].IMUX_IMUX_DELAY[8]	GTX_DUAL.TXDIFFCTRL1[0]
CELL[0].IMUX_IMUX_DELAY[9]	GTX_DUAL.TXCHARDISPVAL1[2]
CELL[0].IMUX_IMUX_DELAY[11]	GTX_DUAL.GTXTEST[11]
CELL[0].IMUX_IMUX_DELAY[12]	GTX_DUAL.GTXTEST[10]
CELL[0].IMUX_IMUX_DELAY[13]	GTX_DUAL.GTXTEST[1]
CELL[0].IMUX_IMUX_DELAY[14]	GTX_DUAL.GTXTEST[12]
CELL[0].IMUX_IMUX_DELAY[15]	GTX_DUAL.TXBUFDIFFCTRL1[2]
CELL[0].IMUX_IMUX_DELAY[16]	GTX_DUAL.TXBUFDIFFCTRL1[1]
CELL[0].IMUX_IMUX_DELAY[17]	GTX_DUAL.TXBUFDIFFCTRL1[0]
CELL[0].IMUX_IMUX_DELAY[20]	CRC32[0].CRCIN[27]
CELL[0].IMUX_IMUX_DELAY[21]	CRC32[0].CRCIN[26]
CELL[0].IMUX_IMUX_DELAY[22]	CRC32[0].CRCIN[25]
CELL[0].IMUX_IMUX_DELAY[23]	CRC32[0].CRCIN[24]
CELL[0].IMUX_IMUX_DELAY[24]	CRC32[0].CRCIN[29]
CELL[0].IMUX_IMUX_DELAY[25]	CRC32[0].CRCIN[28]
CELL[0].IMUX_IMUX_DELAY[27]	GTX_DUAL.TXDATA1[18]
CELL[0].IMUX_IMUX_DELAY[29]	GTX_DUAL.TXDATA1[19]
CELL[0].IMUX_IMUX_DELAY[30]	GTX_DUAL.SCANINPCS1
CELL[0].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXDATA1[17]
CELL[0].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXDATA1[0]
CELL[0].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDATA1[1]
CELL[0].IMUX_IMUX_DELAY[34]	GTX_DUAL.TXDATA1[2]
CELL[0].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDATA1[3]
CELL[0].IMUX_IMUX_DELAY[36]	GTX_DUAL.SCANMODE
CELL[0].IMUX_IMUX_DELAY[37]	GTX_DUAL.TXSEQUENCE1[6]
CELL[0].IMUX_IMUX_DELAY[38]	GTX_DUAL.TXCHARDISPMODE1[2]
CELL[0].IMUX_IMUX_DELAY[41]	GTX_DUAL.TXSEQUENCE1[2]
CELL[0].IMUX_IMUX_DELAY[42]	CRC32[0].CRCIN[31]
CELL[0].IMUX_IMUX_DELAY[43]	CRC32[0].CRCIN[30]
CELL[0].IMUX_IMUX_DELAY[44]	GTX_DUAL.TXSEQUENCE1[5]
CELL[0].IMUX_IMUX_DELAY[45]	GTX_DUAL.TXSEQUENCE1[4]
CELL[0].IMUX_IMUX_DELAY[46]	GTX_DUAL.TXSEQUENCE1[3]
CELL[0].IMUX_IMUX_DELAY[47]	GTX_DUAL.TXDETECTRX1
CELL[0].OUT_BEL[0]	GTX_DUAL.TXGEARBOXREADY1
CELL[0].OUT_BEL[1]	CRC32[0].CRCOUT[29]
CELL[0].OUT_BEL[2]	GTX_DUAL.RXSTARTOFSEQ1
CELL[0].OUT_BEL[3]	CRC32[0].CRCOUT[23]
CELL[0].OUT_BEL[4]	CRC32[0].CRCOUT[31]
CELL[0].OUT_BEL[5]	CRC32[0].CRCOUT[28]
CELL[0].OUT_BEL[6]	GTX_DUAL.RXHEADER1[1]
CELL[0].OUT_BEL[7]	CRC32[0].CRCOUT[22]
CELL[0].OUT_BEL[11]	GTX_DUAL.RXHEADERVALID1
CELL[0].OUT_BEL[12]	GTX_DUAL.RXDATAVALID1
CELL[0].OUT_BEL[13]	CRC32[0].CRCOUT[27]
CELL[0].OUT_BEL[14]	CRC32[0].CRCOUT[25]
CELL[0].OUT_BEL[15]	CRC32[0].CRCOUT[21]
CELL[0].OUT_BEL[16]	GTX_DUAL.RXHEADER1[2]
CELL[0].OUT_BEL[17]	GTX_DUAL.RXHEADER1[0]
CELL[0].OUT_BEL[20]	CRC32[0].CRCOUT[24]
CELL[0].OUT_BEL[21]	CRC32[0].CRCOUT[20]
CELL[0].OUT_BEL[22]	CRC32[0].CRCOUT[30]
CELL[0].OUT_BEL[23]	CRC32[0].CRCOUT[26]
CELL[1].IMUX_CLK[1]	CRC32[0].CRCCLK
CELL[1].IMUX_IMUX_DELAY[0]	GTX_DUAL.TXCOMTYPE1
CELL[1].IMUX_IMUX_DELAY[1]	GTX_DUAL.TXCHARISK1[0]
CELL[1].IMUX_IMUX_DELAY[3]	GTX_DUAL.TXSEQUENCE1[1]
CELL[1].IMUX_IMUX_DELAY[6]	GTX_DUAL.TXDATA1[20]
CELL[1].IMUX_IMUX_DELAY[8]	GTX_DUAL.TXCHARDISPMODE1[0]
CELL[1].IMUX_IMUX_DELAY[10]	GTX_DUAL.TXENPRBSTST1[1]
CELL[1].IMUX_IMUX_DELAY[11]	GTX_DUAL.TXENPRBSTST1[0]
CELL[1].IMUX_IMUX_DELAY[12]	GTX_DUAL.TXBYPASS8B10B1[0]
CELL[1].IMUX_IMUX_DELAY[13]	GTX_DUAL.TXCHARISK1[2]
CELL[1].IMUX_IMUX_DELAY[18]	CRC32[0].CRCIN[23]
CELL[1].IMUX_IMUX_DELAY[19]	CRC32[0].CRCIN[22]
CELL[1].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXDATA1[21]
CELL[1].IMUX_IMUX_DELAY[21]	GTX_DUAL.TXCHARDISPVAL1[0]
CELL[1].IMUX_IMUX_DELAY[22]	CRC32[0].CRCIN[17]
CELL[1].IMUX_IMUX_DELAY[23]	CRC32[0].CRCIN[16]
CELL[1].IMUX_IMUX_DELAY[24]	GTX_DUAL.TXPREEMPHASIS1[2]
CELL[1].IMUX_IMUX_DELAY[25]	GTX_DUAL.TXPREEMPHASIS1[1]
CELL[1].IMUX_IMUX_DELAY[26]	GTX_DUAL.TXPREEMPHASIS1[0]
CELL[1].IMUX_IMUX_DELAY[28]	GTX_DUAL.TXDATA1[23]
CELL[1].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXDATA1[4]
CELL[1].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDATA1[5]
CELL[1].IMUX_IMUX_DELAY[34]	GTX_DUAL.TXDATA1[6]
CELL[1].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDATA1[7]
CELL[1].IMUX_IMUX_DELAY[37]	GTX_DUAL.TXCOMSTART1
CELL[1].IMUX_IMUX_DELAY[39]	GTX_DUAL.TXDATA1[22]
CELL[1].IMUX_IMUX_DELAY[42]	CRC32[0].CRCIN[21]
CELL[1].IMUX_IMUX_DELAY[43]	CRC32[0].CRCIN[20]
CELL[1].IMUX_IMUX_DELAY[44]	CRC32[0].CRCIN[19]
CELL[1].IMUX_IMUX_DELAY[45]	CRC32[0].CRCIN[18]
CELL[1].IMUX_IMUX_DELAY[46]	GTX_DUAL.TXSEQUENCE1[0]
CELL[1].IMUX_IMUX_DELAY[47]	GTX_DUAL.TSTPWRDNOVRD1
CELL[1].OUT_BEL[1]	CRC32[0].CRCOUT[17]
CELL[1].OUT_BEL[2]	GTX_DUAL.TXBUFSTATUS1[0]
CELL[1].OUT_BEL[4]	GTX_DUAL.RXDATA1[31]
CELL[1].OUT_BEL[5]	CRC32[0].CRCOUT[16]
CELL[1].OUT_BEL[6]	GTX_DUAL.RXDATA1[28]
CELL[1].OUT_BEL[7]	GTX_DUAL.TXKERR1[0]
CELL[1].OUT_BEL[9]	GTX_DUAL.RXDATA1[30]
CELL[1].OUT_BEL[10]	GTX_DUAL.TXBUFSTATUS1[1]
CELL[1].OUT_BEL[11]	GTX_DUAL.TXRUNDISP1[0]
CELL[1].OUT_BEL[12]	CRC32[0].CRCOUT[19]
CELL[1].OUT_BEL[13]	CRC32[0].CRCOUT[15]
CELL[1].OUT_BEL[14]	GTX_DUAL.TXKERR1[2]
CELL[1].OUT_BEL[15]	GTX_DUAL.RXDISPERR1[3]
CELL[1].OUT_BEL[16]	CRC32[0].CRCOUT[13]
CELL[1].OUT_BEL[17]	CRC32[0].CRCOUT[12]
CELL[1].OUT_BEL[18]	GTX_DUAL.TXRUNDISP1[2]
CELL[1].OUT_BEL[20]	GTX_DUAL.RXDATA1[29]
CELL[1].OUT_BEL[21]	GTX_DUAL.RXCHARISK1[3]
CELL[1].OUT_BEL[22]	CRC32[0].CRCOUT[18]
CELL[1].OUT_BEL[23]	CRC32[0].CRCOUT[14]
CELL[2].IMUX_IMUX_DELAY[2]	GTX_DUAL.TXPOLARITY1
CELL[2].IMUX_IMUX_DELAY[5]	CRC32[0].CRCRESET
CELL[2].IMUX_IMUX_DELAY[10]	GTX_DUAL.TXPREEMPHASIS1[3]
CELL[2].IMUX_IMUX_DELAY[12]	CRC32[0].CRCIN[13]
CELL[2].IMUX_IMUX_DELAY[13]	CRC32[0].CRCIN[12]
CELL[2].IMUX_IMUX_DELAY[14]	CRC32[0].CRCIN[11]
CELL[2].IMUX_IMUX_DELAY[15]	CRC32[0].CRCIN[10]
CELL[2].IMUX_IMUX_DELAY[16]	CRC32[0].CRCIN[9]
CELL[2].IMUX_IMUX_DELAY[17]	CRC32[0].CRCIN[8]
CELL[2].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXCHARDISPMODE1[1]
CELL[2].IMUX_IMUX_DELAY[21]	GTX_DUAL.TXCHARDISPVAL1[1]
CELL[2].IMUX_IMUX_DELAY[24]	GTX_DUAL.TXBYPASS8B10B1[1]
CELL[2].IMUX_IMUX_DELAY[25]	GTX_DUAL.TXCHARISK1[1]
CELL[2].IMUX_IMUX_DELAY[27]	GTX_DUAL.TXDATA1[27]
CELL[2].IMUX_IMUX_DELAY[28]	GTX_DUAL.TXCHARDISPVAL1[3]
CELL[2].IMUX_IMUX_DELAY[30]	GTX_DUAL.TXDATA1[24]
CELL[2].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXDATA1[25]
CELL[2].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXDATA1[8]
CELL[2].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDATA1[9]
CELL[2].IMUX_IMUX_DELAY[34]	GTX_DUAL.TXDATA1[10]
CELL[2].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDATA1[11]
CELL[2].IMUX_IMUX_DELAY[36]	CRC32[0].CRCIN[15]
CELL[2].IMUX_IMUX_DELAY[37]	CRC32[0].CRCIN[14]
CELL[2].IMUX_IMUX_DELAY[38]	GTX_DUAL.TXDATA1[26]
CELL[2].IMUX_IMUX_DELAY[39]	GTX_DUAL.TXCHARISK1[3]
CELL[2].IMUX_IMUX_DELAY[40]	GTX_DUAL.TXCHARDISPMODE1[3]
CELL[2].IMUX_IMUX_DELAY[42]	GTX_DUAL.TXPOWERDOWN1[1]
CELL[2].IMUX_IMUX_DELAY[43]	GTX_DUAL.TXPOWERDOWN1[0]
CELL[2].OUT_BEL[1]	CRC32[0].CRCOUT[9]
CELL[2].OUT_BEL[2]	GTX_DUAL.RXELECIDLE1
CELL[2].OUT_BEL[3]	GTX_DUAL.RXCHARISCOMMA1[3]
CELL[2].OUT_BEL[4]	GTX_DUAL.RXNOTINTABLE1[3]
CELL[2].OUT_BEL[5]	GTX_DUAL.TXRUNDISP1[1]
CELL[2].OUT_BEL[6]	CRC32[0].CRCOUT[4]
CELL[2].OUT_BEL[7]	GTX_DUAL.RXDATA1[25]
CELL[2].OUT_BEL[10]	GTX_DUAL.TXKERR1[3]
CELL[2].OUT_BEL[11]	GTX_DUAL.RXDATA1[24]
CELL[2].OUT_BEL[12]	CRC32[0].CRCOUT[11]
CELL[2].OUT_BEL[13]	CRC32[0].CRCOUT[8]
CELL[2].OUT_BEL[14]	CRC32[0].CRCOUT[6]
CELL[2].OUT_BEL[15]	GTX_DUAL.TXKERR1[1]
CELL[2].OUT_BEL[16]	GTX_DUAL.RXDATA1[26]
CELL[2].OUT_BEL[17]	GTX_DUAL.RXDISPERR1[2]
CELL[2].OUT_BEL[18]	GTX_DUAL.RXRUNDISP1[3]
CELL[2].OUT_BEL[19]	GTX_DUAL.RXDATA1[27]
CELL[2].OUT_BEL[20]	CRC32[0].CRCOUT[5]
CELL[2].OUT_BEL[21]	CRC32[0].CRCOUT[3]
CELL[2].OUT_BEL[22]	CRC32[0].CRCOUT[10]
CELL[2].OUT_BEL[23]	CRC32[0].CRCOUT[7]
CELL[3].IMUX_IMUX_DELAY[0]	GTX_DUAL.TXRESET1
CELL[3].IMUX_IMUX_DELAY[1]	GTX_DUAL.TXINHIBIT1
CELL[3].IMUX_IMUX_DELAY[4]	GTX_DUAL.TXDATAWIDTH1[0]
CELL[3].IMUX_IMUX_DELAY[5]	GTX_DUAL.TXDATAWIDTH1[1]
CELL[3].IMUX_IMUX_DELAY[7]	GTX_DUAL.TXHEADER1[2]
CELL[3].IMUX_IMUX_DELAY[8]	GTX_DUAL.TXSTARTSEQ1
CELL[3].IMUX_IMUX_DELAY[9]	GTX_DUAL.TXHEADER1[0]
CELL[3].IMUX_IMUX_DELAY[12]	CRC32[0].CRCIN[5]
CELL[3].IMUX_IMUX_DELAY[13]	CRC32[0].CRCIN[4]
CELL[3].IMUX_IMUX_DELAY[14]	CRC32[0].CRCIN[3]
CELL[3].IMUX_IMUX_DELAY[15]	CRC32[0].CRCIN[2]
CELL[3].IMUX_IMUX_DELAY[16]	CRC32[0].CRCIN[1]
CELL[3].IMUX_IMUX_DELAY[17]	CRC32[0].CRCIN[0]
CELL[3].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXHEADER1[1]
CELL[3].IMUX_IMUX_DELAY[21]	CRC32[0].CRCDATAWIDTH[2], CRC32[1].CRCDATAWIDTH[2]
CELL[3].IMUX_IMUX_DELAY[22]	CRC32[0].CRCDATAVALID
CELL[3].IMUX_IMUX_DELAY[23]	CRC32[0].CRCDATAWIDTH[1]
CELL[3].IMUX_IMUX_DELAY[30]	GTX_DUAL.TXDATA1[28]
CELL[3].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXDATA1[29]
CELL[3].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXDATA1[12]
CELL[3].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDATA1[13]
CELL[3].IMUX_IMUX_DELAY[34]	GTX_DUAL.TXDATA1[14]
CELL[3].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDATA1[15]
CELL[3].IMUX_IMUX_DELAY[36]	CRC32[0].CRCIN[7]
CELL[3].IMUX_IMUX_DELAY[37]	CRC32[0].CRCIN[6]
CELL[3].IMUX_IMUX_DELAY[38]	GTX_DUAL.TXDATA1[30]
CELL[3].IMUX_IMUX_DELAY[39]	GTX_DUAL.TXDATA1[31]
CELL[3].IMUX_IMUX_DELAY[40]	CRC32[0].CRCDATAWIDTH[0]
CELL[3].IMUX_IMUX_DELAY[47]	GTX_DUAL.TXENC8B10BUSE1
CELL[3].OUT_BEL[0]	GTX_DUAL.RXSTATUS1[1]
CELL[3].OUT_BEL[2]	GTX_DUAL.RXCLKCORCNT1[0]
CELL[3].OUT_BEL[4]	CRC32[0].CRCOUT[1]
CELL[3].OUT_BEL[5]	GTX_DUAL.RXDATA1[22]
CELL[3].OUT_BEL[6]	CRC32[0].CRCOUT[0]
CELL[3].OUT_BEL[7]	GTX_DUAL.RXCHARISCOMMA1[2]
CELL[3].OUT_BEL[8]	GTX_DUAL.RXSTATUS1[2]
CELL[3].OUT_BEL[9]	GTX_DUAL.RXCLKCORCNT1[2]
CELL[3].OUT_BEL[10]	GTX_DUAL.RXCLKCORCNT1[1]
CELL[3].OUT_BEL[11]	GTX_DUAL.RXPRBSERR1
CELL[3].OUT_BEL[12]	GTX_DUAL.RXCHARISK1[2]
CELL[3].OUT_BEL[14]	GTX_DUAL.RXDATA1[20]
CELL[3].OUT_BEL[16]	GTX_DUAL.RXDATA1[19]
CELL[3].OUT_BEL[17]	GTX_DUAL.RXNOTINTABLE1[2]
CELL[3].OUT_BEL[18]	CRC32[0].CRCOUT[2]
CELL[3].OUT_BEL[19]	GTX_DUAL.RXSTATUS1[0]
CELL[3].OUT_BEL[20]	GTX_DUAL.RXRUNDISP1[2]
CELL[3].OUT_BEL[21]	GTX_DUAL.TXRUNDISP1[3]
CELL[3].OUT_BEL[22]	GTX_DUAL.RXDATA1[23]
CELL[3].OUT_BEL[23]	GTX_DUAL.RXDATA1[21]
CELL[4].IMUX_IMUX_DELAY[0]	GTX_DUAL.RXPOLARITY1
CELL[4].IMUX_IMUX_DELAY[1]	GTX_DUAL.RXENPCOMMAALIGN1
CELL[4].IMUX_IMUX_DELAY[2]	GTX_DUAL.RXENMCOMMAALIGN1
CELL[4].IMUX_IMUX_DELAY[3]	GTX_DUAL.RXSLIDE1
CELL[4].IMUX_IMUX_DELAY[5]	GTX_DUAL.RXENEQB1
CELL[4].IMUX_IMUX_DELAY[10]	GTX_DUAL.RXDATAWIDTH1[0]
CELL[4].IMUX_IMUX_DELAY[14]	GTX_DUAL.TXBYPASS8B10B1[3]
CELL[4].IMUX_IMUX_DELAY[15]	GTX_DUAL.RXDATAWIDTH1[1]
CELL[4].IMUX_IMUX_DELAY[17]	GTX_DUAL.RXCOMMADETUSE1
CELL[4].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXBYPASS8B10B1[2]
CELL[4].IMUX_IMUX_DELAY[22]	GTX_DUAL.RXGEARBOXSLIP1
CELL[4].IMUX_IMUX_DELAY[24]	GTX_DUAL.RXENPRBSTST1[1]
CELL[4].IMUX_IMUX_DELAY[25]	GTX_DUAL.RXENPRBSTST1[0]
CELL[4].IMUX_IMUX_DELAY[27]	GTX_DUAL.DFECLKDLYADJ1[3]
CELL[4].IMUX_IMUX_DELAY[29]	GTX_DUAL.DFECLKDLYADJ1[1]
CELL[4].IMUX_IMUX_DELAY[31]	GTX_DUAL.DFECLKDLYADJ1[5]
CELL[4].IMUX_IMUX_DELAY[32]	GTX_DUAL.DFECLKDLYADJ1[4]
CELL[4].IMUX_IMUX_DELAY[33]	GTX_DUAL.RXENSAMPLEALIGN1
CELL[4].IMUX_IMUX_DELAY[34]	GTX_DUAL.DFECLKDLYADJ1[2]
CELL[4].IMUX_IMUX_DELAY[36]	CRC32[1].CRCIN[31]
CELL[4].IMUX_IMUX_DELAY[37]	CRC32[1].CRCIN[30]
CELL[4].IMUX_IMUX_DELAY[42]	CRC32[1].CRCIN[29]
CELL[4].IMUX_IMUX_DELAY[43]	CRC32[1].CRCIN[28]
CELL[4].IMUX_IMUX_DELAY[44]	CRC32[1].CRCIN[27]
CELL[4].IMUX_IMUX_DELAY[45]	CRC32[1].CRCIN[26]
CELL[4].IMUX_IMUX_DELAY[46]	CRC32[1].CRCIN[25]
CELL[4].IMUX_IMUX_DELAY[47]	CRC32[1].CRCIN[24]
CELL[4].OUT_BEL[0]	GTX_DUAL.RESETDONE1
CELL[4].OUT_BEL[1]	GTX_DUAL.DFECLKDLYADJMONITOR1[5]
CELL[4].OUT_BEL[2]	GTX_DUAL.RXDATA1[2]
CELL[4].OUT_BEL[3]	GTX_DUAL.DFECLKDLYADJMONITOR1[2]
CELL[4].OUT_BEL[4]	GTX_DUAL.RXOVERSAMPLEERR1
CELL[4].OUT_BEL[6]	GTX_DUAL.RXBUFSTATUS1[0]
CELL[4].OUT_BEL[7]	GTX_DUAL.DFECLKDLYADJMONITOR1[1]
CELL[4].OUT_BEL[9]	GTX_DUAL.RXDATA1[0]
CELL[4].OUT_BEL[10]	GTX_DUAL.RXDATA1[1]
CELL[4].OUT_BEL[11]	GTX_DUAL.RXDATA1[3]
CELL[4].OUT_BEL[12]	GTX_DUAL.RXDATA1[18]
CELL[4].OUT_BEL[13]	GTX_DUAL.DFECLKDLYADJMONITOR1[4]
CELL[4].OUT_BEL[14]	GTX_DUAL.DFECLKDLYADJMONITOR1[3]
CELL[4].OUT_BEL[15]	GTX_DUAL.DFECLKDLYADJMONITOR1[0]
CELL[4].OUT_BEL[16]	GTX_DUAL.RXBUFSTATUS1[1]
CELL[4].OUT_BEL[17]	GTX_DUAL.PHYSTATUS1
CELL[4].OUT_BEL[18]	GTX_DUAL.RXDATA1[17]
CELL[4].OUT_BEL[19]	GTX_DUAL.RXBUFSTATUS1[2]
CELL[4].OUT_BEL[21]	CRC32[1].CRCOUT[31]
CELL[4].OUT_BEL[22]	GTX_DUAL.RXDATA1[16]
CELL[5].IMUX_IMUX_DELAY[0]	GTX_DUAL.RXEQMIX1[1]
CELL[5].IMUX_IMUX_DELAY[1]	GTX_DUAL.RXEQMIX1[0]
CELL[5].IMUX_IMUX_DELAY[2]	GTX_DUAL.RXEQPOLE1[3]
CELL[5].IMUX_IMUX_DELAY[3]	GTX_DUAL.RXEQPOLE1[2]
CELL[5].IMUX_IMUX_DELAY[4]	GTX_DUAL.RXEQPOLE1[1]
CELL[5].IMUX_IMUX_DELAY[5]	GTX_DUAL.RXEQPOLE1[0]
CELL[5].IMUX_IMUX_DELAY[11]	GTX_DUAL.DFETAP21[1]
CELL[5].IMUX_IMUX_DELAY[12]	GTX_DUAL.DFETAP11[4]
CELL[5].IMUX_IMUX_DELAY[13]	GTX_DUAL.GTXTEST[9]
CELL[5].IMUX_IMUX_DELAY[20]	GTX_DUAL.DFETAP21[4]
CELL[5].IMUX_IMUX_DELAY[22]	GTX_DUAL.DFETAP21[2]
CELL[5].IMUX_IMUX_DELAY[24]	GTX_DUAL.DFECLKDLYADJ1[0]
CELL[5].IMUX_IMUX_DELAY[25]	GTX_DUAL.DFETAP11[3]
CELL[5].IMUX_IMUX_DELAY[26]	GTX_DUAL.DFETAP11[2]
CELL[5].IMUX_IMUX_DELAY[27]	GTX_DUAL.DFETAP21[3]
CELL[5].IMUX_IMUX_DELAY[28]	GTX_DUAL.DFETAP11[0]
CELL[5].IMUX_IMUX_DELAY[29]	GTX_DUAL.DFETAP21[0]
CELL[5].IMUX_IMUX_DELAY[33]	GTX_DUAL.DFETAP11[1]
CELL[5].IMUX_IMUX_DELAY[36]	CRC32[1].CRCIN[23]
CELL[5].IMUX_IMUX_DELAY[37]	CRC32[1].CRCIN[22]
CELL[5].IMUX_IMUX_DELAY[42]	CRC32[1].CRCIN[21]
CELL[5].IMUX_IMUX_DELAY[43]	CRC32[1].CRCIN[20]
CELL[5].IMUX_IMUX_DELAY[44]	CRC32[1].CRCIN[19]
CELL[5].IMUX_IMUX_DELAY[45]	CRC32[1].CRCIN[18]
CELL[5].IMUX_IMUX_DELAY[46]	CRC32[1].CRCIN[17]
CELL[5].IMUX_IMUX_DELAY[47]	CRC32[1].CRCIN[16]
CELL[5].OUT_BEL[0]	GTX_DUAL.RXBYTEISALIGNED1
CELL[5].OUT_BEL[2]	GTX_DUAL.RXDATA1[6]
CELL[5].OUT_BEL[4]	GTX_DUAL.RXNOTINTABLE1[0]
CELL[5].OUT_BEL[5]	CRC32[1].CRCOUT[29]
CELL[5].OUT_BEL[6]	GTX_DUAL.RXRUNDISP1[0]
CELL[5].OUT_BEL[7]	CRC32[1].CRCOUT[28]
CELL[5].OUT_BEL[8]	GTX_DUAL.RXCOMMADET1
CELL[5].OUT_BEL[9]	GTX_DUAL.RXDATA1[4]
CELL[5].OUT_BEL[10]	GTX_DUAL.RXDATA1[5]
CELL[5].OUT_BEL[11]	GTX_DUAL.RXDATA1[7]
CELL[5].OUT_BEL[12]	GTX_DUAL.DFEEYEDACMONITOR1[4]
CELL[5].OUT_BEL[13]	GTX_DUAL.DFEEYEDACMONITOR1[3]
CELL[5].OUT_BEL[14]	GTX_DUAL.DFEEYEDACMONITOR1[2]
CELL[5].OUT_BEL[15]	GTX_DUAL.DFEEYEDACMONITOR1[1]
CELL[5].OUT_BEL[16]	GTX_DUAL.RXCHARISK1[0]
CELL[5].OUT_BEL[17]	GTX_DUAL.RXCHARISCOMMA1[0]
CELL[5].OUT_BEL[18]	GTX_DUAL.RXBYTEREALIGN1
CELL[5].OUT_BEL[19]	GTX_DUAL.RXDISPERR1[0]
CELL[5].OUT_BEL[21]	CRC32[1].CRCOUT[27]
CELL[5].OUT_BEL[22]	CRC32[1].CRCOUT[30]
CELL[6].IMUX_CLK[1]	CRC32[1].CRCCLK
CELL[6].IMUX_IMUX_DELAY[1]	GTX_DUAL.RXCHBONDI1[2]
CELL[6].IMUX_IMUX_DELAY[2]	GTX_DUAL.RXCHBONDI1[1]
CELL[6].IMUX_IMUX_DELAY[3]	GTX_DUAL.RXCHBONDI1[0]
CELL[6].IMUX_IMUX_DELAY[6]	GTX_DUAL.RXDEC8B10BUSE1
CELL[6].IMUX_IMUX_DELAY[11]	GTX_DUAL.DFETAP41[3]
CELL[6].IMUX_IMUX_DELAY[12]	GTX_DUAL.TSTPWRDN1[4]
CELL[6].IMUX_IMUX_DELAY[13]	GTX_DUAL.TSTPWRDN1[3]
CELL[6].IMUX_IMUX_DELAY[14]	GTX_DUAL.TSTPWRDN1[2]
CELL[6].IMUX_IMUX_DELAY[15]	GTX_DUAL.TSTPWRDN1[1]
CELL[6].IMUX_IMUX_DELAY[16]	GTX_DUAL.TSTPWRDN1[0]
CELL[6].IMUX_IMUX_DELAY[23]	GTX_DUAL.RXCHBONDI1[3]
CELL[6].IMUX_IMUX_DELAY[24]	GTX_DUAL.RXENCHANSYNC1
CELL[6].IMUX_IMUX_DELAY[31]	GTX_DUAL.DFETAP31[3]
CELL[6].IMUX_IMUX_DELAY[32]	GTX_DUAL.DFETAP31[2]
CELL[6].IMUX_IMUX_DELAY[34]	GTX_DUAL.DFETAP31[0]
CELL[6].IMUX_IMUX_DELAY[36]	CRC32[1].CRCIN[15]
CELL[6].IMUX_IMUX_DELAY[37]	CRC32[1].CRCIN[14]
CELL[6].IMUX_IMUX_DELAY[39]	GTX_DUAL.DFETAP31[1]
CELL[6].IMUX_IMUX_DELAY[42]	CRC32[1].CRCIN[13]
CELL[6].IMUX_IMUX_DELAY[43]	CRC32[1].CRCIN[12]
CELL[6].IMUX_IMUX_DELAY[44]	CRC32[1].CRCIN[11]
CELL[6].IMUX_IMUX_DELAY[45]	CRC32[1].CRCIN[10]
CELL[6].IMUX_IMUX_DELAY[46]	CRC32[1].CRCIN[9]
CELL[6].IMUX_IMUX_DELAY[47]	CRC32[1].CRCIN[8]
CELL[6].OUT_BEL[0]	GTX_DUAL.RXVALID1
CELL[6].OUT_BEL[2]	GTX_DUAL.RXDATA1[10]
CELL[6].OUT_BEL[4]	GTX_DUAL.RXNOTINTABLE1[1]
CELL[6].OUT_BEL[5]	GTX_DUAL.DFETAP1MONITOR1[4]
CELL[6].OUT_BEL[6]	GTX_DUAL.RXRUNDISP1[1]
CELL[6].OUT_BEL[7]	GTX_DUAL.DFETAP1MONITOR1[2]
CELL[6].OUT_BEL[8]	GTX_DUAL.RXLOSSOFSYNC1[1]
CELL[6].OUT_BEL[9]	GTX_DUAL.RXDATA1[8]
CELL[6].OUT_BEL[10]	GTX_DUAL.RXDATA1[9]
CELL[6].OUT_BEL[11]	GTX_DUAL.RXDATA1[11]
CELL[6].OUT_BEL[12]	CRC32[1].CRCOUT[26]
CELL[6].OUT_BEL[14]	CRC32[1].CRCOUT[25]
CELL[6].OUT_BEL[15]	CRC32[1].CRCOUT[24]
CELL[6].OUT_BEL[16]	GTX_DUAL.RXCHARISK1[1]
CELL[6].OUT_BEL[17]	GTX_DUAL.RXCHARISCOMMA1[1]
CELL[6].OUT_BEL[18]	GTX_DUAL.DFEEYEDACMONITOR1[0]
CELL[6].OUT_BEL[19]	GTX_DUAL.RXDISPERR1[1]
CELL[6].OUT_BEL[21]	GTX_DUAL.DFETAP1MONITOR1[1]
CELL[6].OUT_BEL[22]	GTX_DUAL.RXLOSSOFSYNC1[0]
CELL[6].OUT_BEL[23]	GTX_DUAL.DFETAP1MONITOR1[3]
CELL[7].IMUX_CLK[1]	GTX_DUAL.DCLK
CELL[7].IMUX_IMUX_DELAY[0]	GTX_DUAL.RXCDRRESET1
CELL[7].IMUX_IMUX_DELAY[4]	GTX_DUAL.RXBUFRESET1
CELL[7].IMUX_IMUX_DELAY[5]	GTX_DUAL.RXRESET1
CELL[7].IMUX_IMUX_DELAY[8]	GTX_DUAL.RXPOWERDOWN1[1]
CELL[7].IMUX_IMUX_DELAY[9]	GTX_DUAL.RXPOWERDOWN1[0]
CELL[7].IMUX_IMUX_DELAY[18]	GTX_DUAL.LOOPBACK1[2]
CELL[7].IMUX_IMUX_DELAY[19]	GTX_DUAL.LOOPBACK1[1]
CELL[7].IMUX_IMUX_DELAY[20]	GTX_DUAL.LOOPBACK1[0]
CELL[7].IMUX_IMUX_DELAY[24]	GTX_DUAL.DFETAP41[2]
CELL[7].IMUX_IMUX_DELAY[25]	GTX_DUAL.DFETAP41[1]
CELL[7].IMUX_IMUX_DELAY[28]	GTX_DUAL.DFETAP41[0]
CELL[7].IMUX_IMUX_DELAY[34]	GTX_DUAL.RXENPMAPHASEALIGN1
CELL[7].IMUX_IMUX_DELAY[36]	CRC32[1].CRCIN[7]
CELL[7].IMUX_IMUX_DELAY[37]	CRC32[1].CRCIN[6]
CELL[7].IMUX_IMUX_DELAY[40]	GTX_DUAL.RXPMASETPHASE1
CELL[7].IMUX_IMUX_DELAY[42]	CRC32[1].CRCIN[5]
CELL[7].IMUX_IMUX_DELAY[43]	CRC32[1].CRCIN[4]
CELL[7].IMUX_IMUX_DELAY[44]	CRC32[1].CRCIN[3]
CELL[7].IMUX_IMUX_DELAY[45]	CRC32[1].CRCIN[2]
CELL[7].IMUX_IMUX_DELAY[46]	CRC32[1].CRCIN[1]
CELL[7].IMUX_IMUX_DELAY[47]	CRC32[1].CRCIN[0]
CELL[7].OUT_BEL[0]	GTX_DUAL.RXCHBONDO1[1]
CELL[7].OUT_BEL[1]	GTX_DUAL.DFETAP2MONITOR1[4]
CELL[7].OUT_BEL[2]	GTX_DUAL.RXDATA1[14]
CELL[7].OUT_BEL[3]	CRC32[1].CRCOUT[22]
CELL[7].OUT_BEL[4]	GTX_DUAL.RXCHANREALIGN1
CELL[7].OUT_BEL[5]	GTX_DUAL.RXCHBONDO1[3]
CELL[7].OUT_BEL[6]	GTX_DUAL.RXCHANBONDSEQ1
CELL[7].OUT_BEL[7]	GTX_DUAL.SCANOUTPCS1
CELL[7].OUT_BEL[8]	GTX_DUAL.RXCHBONDO1[2]
CELL[7].OUT_BEL[9]	GTX_DUAL.RXDATA1[12]
CELL[7].OUT_BEL[10]	GTX_DUAL.RXDATA1[13]
CELL[7].OUT_BEL[11]	GTX_DUAL.RXDATA1[15]
CELL[7].OUT_BEL[12]	CRC32[1].CRCOUT[23]
CELL[7].OUT_BEL[13]	GTX_DUAL.DFETAP2MONITOR1[3]
CELL[7].OUT_BEL[14]	GTX_DUAL.DFETAP2MONITOR1[2]
CELL[7].OUT_BEL[16]	GTX_DUAL.DFETAP2MONITOR1[1]
CELL[7].OUT_BEL[17]	CRC32[1].CRCOUT[21]
CELL[7].OUT_BEL[18]	GTX_DUAL.RXCHANISALIGNED1
CELL[7].OUT_BEL[19]	GTX_DUAL.RXCHBONDO1[0]
CELL[7].OUT_BEL[20]	GTX_DUAL.RXRECCLK1
CELL[7].OUT_BEL[21]	CRC32[1].CRCOUT[20]
CELL[7].OUT_BEL[22]	GTX_DUAL.DFETAP1MONITOR1[0]
CELL[8].IMUX_CLK[0]	GTX_DUAL.TXUSRCLK21
CELL[8].IMUX_CLK[1]	GTX_DUAL.TXUSRCLK1
CELL[8].IMUX_IMUX_DELAY[0]	CRC32[1].CRCRESET
CELL[8].IMUX_IMUX_DELAY[2]	GTX_DUAL.PRBSCNTRESET1
CELL[8].IMUX_IMUX_DELAY[11]	CRC32[1].CRCDATAWIDTH[0]
CELL[8].IMUX_IMUX_DELAY[34]	CRC32[1].CRCDATAWIDTH[1]
CELL[8].IMUX_IMUX_DELAY[35]	CRC32[1].CRCDATAVALID
CELL[8].IMUX_IMUX_DELAY[44]	GTX_DUAL.DI[15]
CELL[8].IMUX_IMUX_DELAY[45]	GTX_DUAL.DI[14]
CELL[8].IMUX_IMUX_DELAY[46]	GTX_DUAL.DI[13]
CELL[8].IMUX_IMUX_DELAY[47]	GTX_DUAL.DI[12]
CELL[8].OUT_BEL[0]	CRC32[1].CRCOUT[19]
CELL[8].OUT_BEL[1]	GTX_DUAL.SCANOUTPCSCOMMON
CELL[8].OUT_BEL[2]	CRC32[1].CRCOUT[13]
CELL[8].OUT_BEL[4]	GTX_DUAL.DFETAP3MONITOR1[3]
CELL[8].OUT_BEL[5]	CRC32[1].CRCOUT[18]
CELL[8].OUT_BEL[6]	CRC32[1].CRCOUT[12]
CELL[8].OUT_BEL[7]	GTX_DUAL.DFETAP3MONITOR1[1]
CELL[8].OUT_BEL[8]	GTX_DUAL.DO[15]
CELL[8].OUT_BEL[9]	CRC32[1].CRCOUT[17]
CELL[8].OUT_BEL[10]	CRC32[1].CRCOUT[15]
CELL[8].OUT_BEL[11]	CRC32[1].CRCOUT[11]
CELL[8].OUT_BEL[12]	GTX_DUAL.DO[14]
CELL[8].OUT_BEL[13]	GTX_DUAL.DO[12]
CELL[8].OUT_BEL[15]	CRC32[1].CRCOUT[10]
CELL[8].OUT_BEL[16]	CRC32[1].CRCOUT[14]
CELL[8].OUT_BEL[17]	CRC32[1].CRCOUT[9]
CELL[8].OUT_BEL[18]	GTX_DUAL.DO[13]
CELL[8].OUT_BEL[20]	GTX_DUAL.DFETAP3MONITOR1[2]
CELL[8].OUT_BEL[21]	GTX_DUAL.DFETAP3MONITOR1[0]
CELL[8].OUT_BEL[22]	GTX_DUAL.DFETAP2MONITOR1[0]
CELL[8].OUT_BEL[23]	CRC32[1].CRCOUT[16]
CELL[9].IMUX_CLK[0]	GTX_DUAL.RXUSRCLK21
CELL[9].IMUX_CLK[1]	GTX_DUAL.RXUSRCLK1
CELL[9].IMUX_IMUX_DELAY[3]	GTX_DUAL.PMAAMUX[0]
CELL[9].IMUX_IMUX_DELAY[4]	GTX_DUAL.PMAAMUX[1]
CELL[9].IMUX_IMUX_DELAY[5]	GTX_DUAL.PMAAMUX[2]
CELL[9].IMUX_IMUX_DELAY[8]	GTX_DUAL.PLLLKDETEN
CELL[9].IMUX_IMUX_DELAY[16]	GTX_DUAL.GTXTEST[2]
CELL[9].IMUX_IMUX_DELAY[17]	GTX_DUAL.GTXTEST[3]
CELL[9].IMUX_IMUX_DELAY[18]	GTX_DUAL.REFCLKPWRDNB
CELL[9].IMUX_IMUX_DELAY[19]	GTX_DUAL.DWE
CELL[9].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXENPMAPHASEALIGN1
CELL[9].IMUX_IMUX_DELAY[26]	GTX_DUAL.DADDR[6]
CELL[9].IMUX_IMUX_DELAY[27]	GTX_DUAL.DADDR[5]
CELL[9].IMUX_IMUX_DELAY[28]	GTX_DUAL.DADDR[4]
CELL[9].IMUX_IMUX_DELAY[29]	GTX_DUAL.DADDR[3]
CELL[9].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXPMASETPHASE1
CELL[9].IMUX_IMUX_DELAY[42]	GTX_DUAL.DI[11]
CELL[9].IMUX_IMUX_DELAY[43]	GTX_DUAL.DI[10]
CELL[9].IMUX_IMUX_DELAY[44]	GTX_DUAL.DI[9]
CELL[9].IMUX_IMUX_DELAY[45]	GTX_DUAL.DI[8]
CELL[9].OUT_BEL[0]	CRC32[1].CRCOUT[5]
CELL[9].OUT_BEL[2]	GTX_DUAL.TXOUTCLK1
CELL[9].OUT_BEL[3]	CRC32[1].CRCOUT[1]
CELL[9].OUT_BEL[4]	CRC32[1].CRCOUT[4]
CELL[9].OUT_BEL[5]	GTX_DUAL.DFETAP4MONITOR1[3]
CELL[9].OUT_BEL[6]	GTX_DUAL.DO[9]
CELL[9].OUT_BEL[7]	GTX_DUAL.DFESENSCAL1[0]
CELL[9].OUT_BEL[8]	CRC32[1].CRCOUT[8]
CELL[9].OUT_BEL[9]	GTX_DUAL.DFESENSCAL1[1]
CELL[9].OUT_BEL[10]	GTX_DUAL.DO[11]
CELL[9].OUT_BEL[11]	CRC32[1].CRCOUT[0]
CELL[9].OUT_BEL[12]	CRC32[1].CRCOUT[7]
CELL[9].OUT_BEL[13]	CRC32[1].CRCOUT[3]
CELL[9].OUT_BEL[14]	CRC32[1].CRCOUT[2]
CELL[9].OUT_BEL[15]	GTX_DUAL.DRDY
CELL[9].OUT_BEL[16]	GTX_DUAL.DFETAP4MONITOR1[1]
CELL[9].OUT_BEL[17]	GTX_DUAL.DFETAP4MONITOR1[0]
CELL[9].OUT_BEL[18]	CRC32[1].CRCOUT[6]
CELL[9].OUT_BEL[19]	GTX_DUAL.DFETAP4MONITOR1[2]
CELL[9].OUT_BEL[20]	GTX_DUAL.DO[10]
CELL[9].OUT_BEL[21]	GTX_DUAL.DO[8]
CELL[9].OUT_BEL[22]	GTX_DUAL.DFESENSCAL1[2]
CELL[9].OUT_BEL[23]	GTX_DUAL.PLLLKDET
CELL[10].IMUX_CLK[0]	GTX_DUAL.RXUSRCLK0
CELL[10].IMUX_CLK[1]	GTX_DUAL.RXUSRCLK20
CELL[10].IMUX_IMUX_DELAY[0]	GTX_DUAL.DI[7]
CELL[10].IMUX_IMUX_DELAY[1]	GTX_DUAL.DI[6]
CELL[10].IMUX_IMUX_DELAY[2]	GTX_DUAL.DI[5]
CELL[10].IMUX_IMUX_DELAY[3]	GTX_DUAL.DI[4]
CELL[10].IMUX_IMUX_DELAY[6]	GTX_DUAL.INTDATAWIDTH
CELL[10].IMUX_IMUX_DELAY[12]	GTX_DUAL.PMATSTCLKSEL[2]
CELL[10].IMUX_IMUX_DELAY[13]	GTX_DUAL.PMATSTCLKSEL[1]
CELL[10].IMUX_IMUX_DELAY[14]	GTX_DUAL.PMATSTCLKSEL[0]
CELL[10].IMUX_IMUX_DELAY[16]	GTX_DUAL.TXENPMAPHASEALIGN0
CELL[10].IMUX_IMUX_DELAY[17]	GTX_DUAL.TXPMASETPHASE0
CELL[10].IMUX_IMUX_DELAY[24]	GTX_DUAL.DADDR[2]
CELL[10].IMUX_IMUX_DELAY[31]	GTX_DUAL.DADDR[1]
CELL[10].IMUX_IMUX_DELAY[32]	GTX_DUAL.DADDR[0]
CELL[10].IMUX_IMUX_DELAY[33]	GTX_DUAL.GTXTEST[13]
CELL[10].IMUX_IMUX_DELAY[36]	GTX_DUAL.PLLPOWERDOWN
CELL[10].IMUX_IMUX_DELAY[39]	GTX_DUAL.DEN
CELL[10].IMUX_IMUX_DELAY[40]	GTX_DUAL.GTXTEST[8]
CELL[10].OUT_BEL[0]	GTX_DUAL.DO[6]
CELL[10].OUT_BEL[1]	GTX_DUAL.DFETAP4MONITOR0[0]
CELL[10].OUT_BEL[2]	CRC32[3].CRCOUT[3]
CELL[10].OUT_BEL[3]	GTX_DUAL.DFETAP4MONITOR0[3]
CELL[10].OUT_BEL[4]	CRC32[3].CRCOUT[0]
CELL[10].OUT_BEL[6]	CRC32[3].CRCOUT[4]
CELL[10].OUT_BEL[7]	CRC32[3].CRCOUT[5]
CELL[10].OUT_BEL[8]	GTX_DUAL.REFCLKOUT
CELL[10].OUT_BEL[9]	GTX_DUAL.DO[5]
CELL[10].OUT_BEL[10]	GTX_DUAL.DO[4]
CELL[10].OUT_BEL[11]	CRC32[3].CRCOUT[6]
CELL[10].OUT_BEL[12]	GTX_DUAL.DO[7]
CELL[10].OUT_BEL[13]	GTX_DUAL.TXOUTCLK0
CELL[10].OUT_BEL[14]	GTX_DUAL.DFETAP4MONITOR0[1]
CELL[10].OUT_BEL[15]	CRC32[3].CRCOUT[7]
CELL[10].OUT_BEL[16]	CRC32[3].CRCOUT[2]
CELL[10].OUT_BEL[17]	GTX_DUAL.DFESENSCAL0[2]
CELL[10].OUT_BEL[18]	GTX_DUAL.DFESENSCAL0[0]
CELL[10].OUT_BEL[19]	GTX_DUAL.DFESENSCAL0[1]
CELL[10].OUT_BEL[20]	GTX_DUAL.DFETAP4MONITOR0[2]
CELL[10].OUT_BEL[21]	CRC32[3].CRCOUT[8]
CELL[10].OUT_BEL[22]	GTX_DUAL.PMATSTCLK
CELL[10].OUT_BEL[23]	CRC32[3].CRCOUT[1]
CELL[10].MGT_ROW_O[0]	GTX_DUAL.RXRECCLK0
CELL[10].MGT_ROW_O[1]	GTX_DUAL.RXRECCLK1
CELL[10].MGT_ROW_O[2]	GTX_DUAL.REFCLKOUT
CELL[10].MGT_ROW_O[3]	GTX_DUAL.TXOUTCLK0
CELL[10].MGT_ROW_O[4]	GTX_DUAL.TXOUTCLK1
CELL[11].IMUX_CLK[0]	GTX_DUAL.TXUSRCLK0
CELL[11].IMUX_CLK[1]	GTX_DUAL.TXUSRCLK20
CELL[11].IMUX_IMUX_DELAY[0]	GTX_DUAL.DI[3]
CELL[11].IMUX_IMUX_DELAY[1]	GTX_DUAL.DI[2]
CELL[11].IMUX_IMUX_DELAY[2]	GTX_DUAL.DI[1]
CELL[11].IMUX_IMUX_DELAY[3]	GTX_DUAL.DI[0]
CELL[11].IMUX_IMUX_DELAY[5]	CRC32[3].CRCRESET
CELL[11].IMUX_IMUX_DELAY[13]	CRC32[3].CRCDATAWIDTH[1]
CELL[11].IMUX_IMUX_DELAY[24]	CRC32[3].CRCDATAWIDTH[0]
CELL[11].IMUX_IMUX_DELAY[29]	GTX_DUAL.SCANINPCSCOMMON
CELL[11].IMUX_IMUX_DELAY[30]	CRC32[3].CRCDATAVALID
CELL[11].IMUX_IMUX_DELAY[36]	GTX_DUAL.GTXRESET
CELL[11].IMUX_IMUX_DELAY[45]	GTX_DUAL.PRBSCNTRESET0
CELL[11].OUT_BEL[1]	GTX_DUAL.DFETAP3MONITOR0[2]
CELL[11].OUT_BEL[3]	CRC32[3].CRCOUT[18]
CELL[11].OUT_BEL[4]	CRC32[3].CRCOUT[10]
CELL[11].OUT_BEL[5]	CRC32[3].CRCOUT[12]
CELL[11].OUT_BEL[7]	CRC32[3].CRCOUT[19]
CELL[11].OUT_BEL[8]	GTX_DUAL.DFETAP3MONITOR0[0]
CELL[11].OUT_BEL[10]	CRC32[3].CRCOUT[16]
CELL[11].OUT_BEL[11]	GTX_DUAL.DFETAP3MONITOR0[3]
CELL[11].OUT_BEL[12]	CRC32[3].CRCOUT[9]
CELL[11].OUT_BEL[13]	CRC32[3].CRCOUT[13]
CELL[11].OUT_BEL[14]	GTX_DUAL.DO[3]
CELL[11].OUT_BEL[15]	GTX_DUAL.DO[2]
CELL[11].OUT_BEL[16]	CRC32[3].CRCOUT[17]
CELL[11].OUT_BEL[17]	GTX_DUAL.DO[1]
CELL[11].OUT_BEL[18]	GTX_DUAL.DFETAP3MONITOR0[1]
CELL[11].OUT_BEL[19]	CRC32[3].CRCOUT[14]
CELL[11].OUT_BEL[21]	GTX_DUAL.DO[0]
CELL[11].OUT_BEL[22]	CRC32[3].CRCOUT[11]
CELL[11].OUT_BEL[23]	CRC32[3].CRCOUT[15]
CELL[12].IMUX_CLK[0]	GTX_DUAL.GREFCLK
CELL[12].IMUX_IMUX_DELAY[0]	CRC32[3].CRCIN[0]
CELL[12].IMUX_IMUX_DELAY[1]	CRC32[3].CRCIN[1]
CELL[12].IMUX_IMUX_DELAY[2]	CRC32[3].CRCIN[2]
CELL[12].IMUX_IMUX_DELAY[7]	GTX_DUAL.RXPMASETPHASE0
CELL[12].IMUX_IMUX_DELAY[9]	CRC32[3].CRCIN[3]
CELL[12].IMUX_IMUX_DELAY[10]	CRC32[3].CRCIN[6]
CELL[12].IMUX_IMUX_DELAY[11]	CRC32[3].CRCIN[7]
CELL[12].IMUX_IMUX_DELAY[13]	GTX_DUAL.RXENPMAPHASEALIGN0
CELL[12].IMUX_IMUX_DELAY[15]	GTX_DUAL.LOOPBACK0[0]
CELL[12].IMUX_IMUX_DELAY[16]	GTX_DUAL.LOOPBACK0[1]
CELL[12].IMUX_IMUX_DELAY[17]	GTX_DUAL.LOOPBACK0[2]
CELL[12].IMUX_IMUX_DELAY[35]	CRC32[3].CRCIN[5]
CELL[12].IMUX_IMUX_DELAY[37]	GTX_DUAL.DFETAP40[0]
CELL[12].IMUX_IMUX_DELAY[38]	GTX_DUAL.RXPOWERDOWN0[0]
CELL[12].IMUX_IMUX_DELAY[39]	GTX_DUAL.RXPOWERDOWN0[1]
CELL[12].IMUX_IMUX_DELAY[40]	GTX_DUAL.DFETAP40[1]
CELL[12].IMUX_IMUX_DELAY[41]	GTX_DUAL.DFETAP40[2]
CELL[12].IMUX_IMUX_DELAY[42]	GTX_DUAL.RXRESET0
CELL[12].IMUX_IMUX_DELAY[43]	GTX_DUAL.RXBUFRESET0
CELL[12].IMUX_IMUX_DELAY[45]	CRC32[3].CRCIN[4]
CELL[12].IMUX_IMUX_DELAY[47]	GTX_DUAL.RXCDRRESET0
CELL[12].OUT_BEL[1]	GTX_DUAL.RXCHANBONDSEQ0
CELL[12].OUT_BEL[2]	GTX_DUAL.DFETAP2MONITOR0[3]
CELL[12].OUT_BEL[3]	GTX_DUAL.RXCHANREALIGN0
CELL[12].OUT_BEL[4]	CRC32[3].CRCOUT[22]
CELL[12].OUT_BEL[5]	GTX_DUAL.RXDATA0[14]
CELL[12].OUT_BEL[6]	GTX_DUAL.DFETAP2MONITOR0[4]
CELL[12].OUT_BEL[7]	GTX_DUAL.RXCHBONDO0[1]
CELL[12].OUT_BEL[8]	CRC32[3].CRCOUT[20]
CELL[12].OUT_BEL[10]	GTX_DUAL.SCANOUTPCS0
CELL[12].OUT_BEL[11]	GTX_DUAL.RXCHBONDO0[3]
CELL[12].OUT_BEL[12]	GTX_DUAL.DFETAP2MONITOR0[0]
CELL[12].OUT_BEL[13]	GTX_DUAL.RXRECCLK0
CELL[12].OUT_BEL[14]	GTX_DUAL.RXCHBONDO0[0]
CELL[12].OUT_BEL[15]	GTX_DUAL.RXCHANISALIGNED0
CELL[12].OUT_BEL[16]	GTX_DUAL.DFETAP2MONITOR0[2]
CELL[12].OUT_BEL[17]	CRC32[3].CRCOUT[23]
CELL[12].OUT_BEL[18]	CRC32[3].CRCOUT[21]
CELL[12].OUT_BEL[19]	GTX_DUAL.DFETAP2MONITOR0[1]
CELL[12].OUT_BEL[20]	GTX_DUAL.RXDATA0[12]
CELL[12].OUT_BEL[21]	GTX_DUAL.RXCHBONDO0[2]
CELL[12].OUT_BEL[22]	GTX_DUAL.RXDATA0[15]
CELL[12].OUT_BEL[23]	GTX_DUAL.RXDATA0[13]
CELL[13].IMUX_CLK[0]	CRC32[3].CRCCLK
CELL[13].IMUX_IMUX_DELAY[4]	CRC32[3].CRCIN[12]
CELL[13].IMUX_IMUX_DELAY[5]	CRC32[3].CRCIN[13]
CELL[13].IMUX_IMUX_DELAY[6]	CRC32[3].CRCIN[8]
CELL[13].IMUX_IMUX_DELAY[7]	CRC32[3].CRCIN[9]
CELL[13].IMUX_IMUX_DELAY[8]	CRC32[3].CRCIN[10]
CELL[13].IMUX_IMUX_DELAY[9]	CRC32[3].CRCIN[11]
CELL[13].IMUX_IMUX_DELAY[10]	CRC32[3].CRCIN[14]
CELL[13].IMUX_IMUX_DELAY[11]	CRC32[3].CRCIN[15]
CELL[13].IMUX_IMUX_DELAY[23]	GTX_DUAL.RXENCHANSYNC0
CELL[13].IMUX_IMUX_DELAY[25]	GTX_DUAL.DFETAP30[0]
CELL[13].IMUX_IMUX_DELAY[26]	GTX_DUAL.DFETAP30[1]
CELL[13].IMUX_IMUX_DELAY[27]	GTX_DUAL.DFETAP30[2]
CELL[13].IMUX_IMUX_DELAY[28]	GTX_DUAL.DFETAP30[3]
CELL[13].IMUX_IMUX_DELAY[31]	GTX_DUAL.TSTPWRDN0[0]
CELL[13].IMUX_IMUX_DELAY[32]	GTX_DUAL.TSTPWRDN0[1]
CELL[13].IMUX_IMUX_DELAY[33]	GTX_DUAL.TSTPWRDN0[2]
CELL[13].IMUX_IMUX_DELAY[34]	GTX_DUAL.TSTPWRDN0[3]
CELL[13].IMUX_IMUX_DELAY[35]	GTX_DUAL.TSTPWRDN0[4]
CELL[13].IMUX_IMUX_DELAY[36]	GTX_DUAL.DFETAP40[3]
CELL[13].IMUX_IMUX_DELAY[41]	GTX_DUAL.RXDEC8B10BUSE0
CELL[13].IMUX_IMUX_DELAY[43]	GTX_DUAL.RXCHBONDI0[3]
CELL[13].IMUX_IMUX_DELAY[44]	GTX_DUAL.RXCHBONDI0[0]
CELL[13].IMUX_IMUX_DELAY[45]	GTX_DUAL.RXCHBONDI0[1]
CELL[13].IMUX_IMUX_DELAY[46]	GTX_DUAL.RXCHBONDI0[2]
CELL[13].OUT_BEL[0]	GTX_DUAL.DFETAP1MONITOR0[1]
CELL[13].OUT_BEL[1]	GTX_DUAL.RXRUNDISP0[1]
CELL[13].OUT_BEL[3]	GTX_DUAL.RXNOTINTABLE0[1]
CELL[13].OUT_BEL[5]	GTX_DUAL.RXDATA0[10]
CELL[13].OUT_BEL[6]	GTX_DUAL.DFETAP1MONITOR0[3]
CELL[13].OUT_BEL[7]	GTX_DUAL.RXVALID0
CELL[13].OUT_BEL[8]	GTX_DUAL.DFETAP1MONITOR0[0]
CELL[13].OUT_BEL[11]	GTX_DUAL.RXLOSSOFSYNC0[0]
CELL[13].OUT_BEL[12]	GTX_DUAL.RXCHARISCOMMA0[1]
CELL[13].OUT_BEL[13]	GTX_DUAL.RXCHARISK0[1]
CELL[13].OUT_BEL[14]	GTX_DUAL.RXDISPERR0[1]
CELL[13].OUT_BEL[15]	GTX_DUAL.DFETAP1MONITOR0[4]
CELL[13].OUT_BEL[16]	GTX_DUAL.DFETAP1MONITOR0[2]
CELL[13].OUT_BEL[17]	CRC32[3].CRCOUT[26]
CELL[13].OUT_BEL[18]	CRC32[3].CRCOUT[24]
CELL[13].OUT_BEL[19]	CRC32[3].CRCOUT[25]
CELL[13].OUT_BEL[20]	GTX_DUAL.RXDATA0[8]
CELL[13].OUT_BEL[21]	GTX_DUAL.RXLOSSOFSYNC0[1]
CELL[13].OUT_BEL[22]	GTX_DUAL.RXDATA0[11]
CELL[13].OUT_BEL[23]	GTX_DUAL.RXDATA0[9]
CELL[14].IMUX_IMUX_DELAY[4]	CRC32[3].CRCIN[20]
CELL[14].IMUX_IMUX_DELAY[5]	CRC32[3].CRCIN[21]
CELL[14].IMUX_IMUX_DELAY[6]	CRC32[3].CRCIN[16]
CELL[14].IMUX_IMUX_DELAY[7]	CRC32[3].CRCIN[17]
CELL[14].IMUX_IMUX_DELAY[8]	CRC32[3].CRCIN[18]
CELL[14].IMUX_IMUX_DELAY[9]	CRC32[3].CRCIN[19]
CELL[14].IMUX_IMUX_DELAY[10]	CRC32[3].CRCIN[22]
CELL[14].IMUX_IMUX_DELAY[11]	CRC32[3].CRCIN[23]
CELL[14].IMUX_IMUX_DELAY[12]	GTX_DUAL.DFETAP20[0]
CELL[14].IMUX_IMUX_DELAY[22]	GTX_DUAL.GTXTEST[4]
CELL[14].IMUX_IMUX_DELAY[23]	GTX_DUAL.DFECLKDLYADJ0[0]
CELL[14].IMUX_IMUX_DELAY[26]	GTX_DUAL.DFETAP10[1]
CELL[14].IMUX_IMUX_DELAY[31]	GTX_DUAL.DFETAP10[0]
CELL[14].IMUX_IMUX_DELAY[33]	GTX_DUAL.DFETAP10[2]
CELL[14].IMUX_IMUX_DELAY[34]	GTX_DUAL.DFETAP10[3]
CELL[14].IMUX_IMUX_DELAY[35]	GTX_DUAL.DFETAP10[4]
CELL[14].IMUX_IMUX_DELAY[36]	GTX_DUAL.DFETAP20[1]
CELL[14].IMUX_IMUX_DELAY[37]	GTX_DUAL.DFETAP20[2]
CELL[14].IMUX_IMUX_DELAY[38]	GTX_DUAL.DFETAP20[3]
CELL[14].IMUX_IMUX_DELAY[39]	GTX_DUAL.DFETAP20[4]
CELL[14].IMUX_IMUX_DELAY[42]	GTX_DUAL.RXEQPOLE0[0]
CELL[14].IMUX_IMUX_DELAY[43]	GTX_DUAL.RXEQPOLE0[1]
CELL[14].IMUX_IMUX_DELAY[44]	GTX_DUAL.RXEQPOLE0[2]
CELL[14].IMUX_IMUX_DELAY[45]	GTX_DUAL.RXEQPOLE0[3]
CELL[14].IMUX_IMUX_DELAY[46]	GTX_DUAL.RXEQMIX0[0]
CELL[14].IMUX_IMUX_DELAY[47]	GTX_DUAL.RXEQMIX0[1]
CELL[14].OUT_BEL[0]	GTX_DUAL.DFEEYEDACMONITOR0[0]
CELL[14].OUT_BEL[1]	GTX_DUAL.RXRUNDISP0[0]
CELL[14].OUT_BEL[2]	GTX_DUAL.DFEEYEDACMONITOR0[3]
CELL[14].OUT_BEL[3]	GTX_DUAL.RXNOTINTABLE0[0]
CELL[14].OUT_BEL[4]	CRC32[3].CRCOUT[28]
CELL[14].OUT_BEL[5]	GTX_DUAL.RXDATA0[6]
CELL[14].OUT_BEL[6]	CRC32[3].CRCOUT[29]
CELL[14].OUT_BEL[7]	GTX_DUAL.RXBYTEISALIGNED0
CELL[14].OUT_BEL[12]	GTX_DUAL.RXCHARISCOMMA0[0]
CELL[14].OUT_BEL[13]	GTX_DUAL.RXCHARISK0[0]
CELL[14].OUT_BEL[14]	GTX_DUAL.RXDISPERR0[0]
CELL[14].OUT_BEL[15]	GTX_DUAL.RXBYTEREALIGN0
CELL[14].OUT_BEL[16]	GTX_DUAL.DFEEYEDACMONITOR0[2]
CELL[14].OUT_BEL[17]	CRC32[3].CRCOUT[30]
CELL[14].OUT_BEL[18]	CRC32[3].CRCOUT[27]
CELL[14].OUT_BEL[19]	GTX_DUAL.DFEEYEDACMONITOR0[1]
CELL[14].OUT_BEL[20]	GTX_DUAL.RXDATA0[4]
CELL[14].OUT_BEL[21]	GTX_DUAL.RXCOMMADET0
CELL[14].OUT_BEL[22]	GTX_DUAL.RXDATA0[7]
CELL[14].OUT_BEL[23]	GTX_DUAL.RXDATA0[5]
CELL[15].IMUX_IMUX_DELAY[4]	CRC32[3].CRCIN[28]
CELL[15].IMUX_IMUX_DELAY[5]	CRC32[3].CRCIN[29]
CELL[15].IMUX_IMUX_DELAY[6]	CRC32[3].CRCIN[24]
CELL[15].IMUX_IMUX_DELAY[7]	CRC32[3].CRCIN[25]
CELL[15].IMUX_IMUX_DELAY[8]	CRC32[3].CRCIN[26]
CELL[15].IMUX_IMUX_DELAY[9]	CRC32[3].CRCIN[27]
CELL[15].IMUX_IMUX_DELAY[10]	CRC32[3].CRCIN[30]
CELL[15].IMUX_IMUX_DELAY[11]	CRC32[3].CRCIN[31]
CELL[15].IMUX_IMUX_DELAY[14]	GTX_DUAL.RXENSAMPLEALIGN0
CELL[15].IMUX_IMUX_DELAY[17]	GTX_DUAL.RXGEARBOXSLIP0
CELL[15].IMUX_IMUX_DELAY[18]	GTX_DUAL.RXDATAWIDTH0[1]
CELL[15].IMUX_IMUX_DELAY[19]	GTX_DUAL.DFECLKDLYADJ0[2]
CELL[15].IMUX_IMUX_DELAY[21]	GTX_DUAL.TXBYPASS8B10B0[3]
CELL[15].IMUX_IMUX_DELAY[27]	GTX_DUAL.TXBYPASS8B10B0[2]
CELL[15].IMUX_IMUX_DELAY[28]	GTX_DUAL.RXENPRBSTST0[0]
CELL[15].IMUX_IMUX_DELAY[29]	GTX_DUAL.RXENPRBSTST0[1]
CELL[15].IMUX_IMUX_DELAY[30]	GTX_DUAL.RXCOMMADETUSE0
CELL[15].IMUX_IMUX_DELAY[36]	GTX_DUAL.DFECLKDLYADJ0[1]
CELL[15].IMUX_IMUX_DELAY[37]	GTX_DUAL.RXDATAWIDTH0[0]
CELL[15].IMUX_IMUX_DELAY[38]	GTX_DUAL.DFECLKDLYADJ0[3]
CELL[15].IMUX_IMUX_DELAY[39]	GTX_DUAL.DFECLKDLYADJ0[4]
CELL[15].IMUX_IMUX_DELAY[40]	GTX_DUAL.DFECLKDLYADJ0[5]
CELL[15].IMUX_IMUX_DELAY[41]	GTX_DUAL.RXPOLARITY0
CELL[15].IMUX_IMUX_DELAY[42]	GTX_DUAL.RXENEQB0
CELL[15].IMUX_IMUX_DELAY[44]	GTX_DUAL.RXSLIDE0
CELL[15].IMUX_IMUX_DELAY[45]	GTX_DUAL.RXENMCOMMAALIGN0
CELL[15].IMUX_IMUX_DELAY[46]	GTX_DUAL.RXENPCOMMAALIGN0
CELL[15].OUT_BEL[0]	GTX_DUAL.DFECLKDLYADJMONITOR0[1]
CELL[15].OUT_BEL[1]	GTX_DUAL.RXBUFSTATUS0[0]
CELL[15].OUT_BEL[3]	GTX_DUAL.RXOVERSAMPLEERR0
CELL[15].OUT_BEL[4]	GTX_DUAL.DFECLKDLYADJMONITOR0[0]
CELL[15].OUT_BEL[5]	GTX_DUAL.RXDATA0[2]
CELL[15].OUT_BEL[6]	GTX_DUAL.DFECLKDLYADJMONITOR0[4]
CELL[15].OUT_BEL[7]	GTX_DUAL.RESETDONE0
CELL[15].OUT_BEL[8]	GTX_DUAL.DFEEYEDACMONITOR0[4]
CELL[15].OUT_BEL[12]	GTX_DUAL.PHYSTATUS0
CELL[15].OUT_BEL[13]	GTX_DUAL.RXBUFSTATUS0[1]
CELL[15].OUT_BEL[14]	GTX_DUAL.RXBUFSTATUS0[2]
CELL[15].OUT_BEL[15]	GTX_DUAL.DFECLKDLYADJMONITOR0[5]
CELL[15].OUT_BEL[16]	GTX_DUAL.DFECLKDLYADJMONITOR0[3]
CELL[15].OUT_BEL[17]	GTX_DUAL.RXDATA0[16]
CELL[15].OUT_BEL[18]	CRC32[3].CRCOUT[31]
CELL[15].OUT_BEL[19]	GTX_DUAL.DFECLKDLYADJMONITOR0[2]
CELL[15].OUT_BEL[20]	GTX_DUAL.RXDATA0[0]
CELL[15].OUT_BEL[21]	GTX_DUAL.RXDATA0[17]
CELL[15].OUT_BEL[22]	GTX_DUAL.RXDATA0[3]
CELL[15].OUT_BEL[23]	GTX_DUAL.RXDATA0[1]
CELL[16].IMUX_IMUX_DELAY[1]	CRC32[2].CRCDATAWIDTH[1]
CELL[16].IMUX_IMUX_DELAY[4]	GTX_DUAL.TXHEADER0[2]
CELL[16].IMUX_IMUX_DELAY[6]	CRC32[2].CRCDATAWIDTH[0]
CELL[16].IMUX_IMUX_DELAY[7]	CRC32[2].CRCDATAVALID
CELL[16].IMUX_IMUX_DELAY[8]	CRC32[2].CRCDATAWIDTH[2], CRC32[3].CRCDATAWIDTH[2]
CELL[16].IMUX_IMUX_DELAY[9]	GTX_DUAL.TXSTARTSEQ0
CELL[16].IMUX_IMUX_DELAY[10]	CRC32[2].CRCIN[6]
CELL[16].IMUX_IMUX_DELAY[11]	CRC32[2].CRCIN[7]
CELL[16].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXDATA0[31]
CELL[16].IMUX_IMUX_DELAY[21]	GTX_DUAL.TXDATA0[30]
CELL[16].IMUX_IMUX_DELAY[22]	GTX_DUAL.TXDATA0[29]
CELL[16].IMUX_IMUX_DELAY[23]	GTX_DUAL.TXDATA0[28]
CELL[16].IMUX_IMUX_DELAY[24]	GTX_DUAL.TXDATAWIDTH0[1]
CELL[16].IMUX_IMUX_DELAY[28]	GTX_DUAL.TXINHIBIT0
CELL[16].IMUX_IMUX_DELAY[30]	GTX_DUAL.TXENC8B10BUSE0
CELL[16].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXDATAWIDTH0[0]
CELL[16].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXHEADER0[0]
CELL[16].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXHEADER0[1]
CELL[16].IMUX_IMUX_DELAY[35]	CRC32[2].CRCIN[5]
CELL[16].IMUX_IMUX_DELAY[36]	CRC32[2].CRCIN[0]
CELL[16].IMUX_IMUX_DELAY[37]	CRC32[2].CRCIN[1]
CELL[16].IMUX_IMUX_DELAY[38]	CRC32[2].CRCIN[2]
CELL[16].IMUX_IMUX_DELAY[39]	CRC32[2].CRCIN[3]
CELL[16].IMUX_IMUX_DELAY[40]	CRC32[2].CRCIN[4]
CELL[16].IMUX_IMUX_DELAY[42]	GTX_DUAL.TXDATA0[15]
CELL[16].IMUX_IMUX_DELAY[43]	GTX_DUAL.TXDATA0[14]
CELL[16].IMUX_IMUX_DELAY[44]	GTX_DUAL.TXDATA0[13]
CELL[16].IMUX_IMUX_DELAY[45]	GTX_DUAL.TXDATA0[12]
CELL[16].IMUX_IMUX_DELAY[47]	GTX_DUAL.TXRESET0
CELL[16].OUT_BEL[0]	GTX_DUAL.RXNOTINTABLE0[2]
CELL[16].OUT_BEL[1]	GTX_DUAL.RXCHARISCOMMA0[2]
CELL[16].OUT_BEL[2]	GTX_DUAL.RXDATA0[20]
CELL[16].OUT_BEL[3]	CRC32[2].CRCOUT[1]
CELL[16].OUT_BEL[5]	GTX_DUAL.RXCLKCORCNT0[0]
CELL[16].OUT_BEL[6]	GTX_DUAL.RXDATA0[21]
CELL[16].OUT_BEL[7]	GTX_DUAL.RXSTATUS0[1]
CELL[16].OUT_BEL[11]	GTX_DUAL.RXDATA0[22]
CELL[16].OUT_BEL[12]	GTX_DUAL.RXDATA0[18]
CELL[16].OUT_BEL[13]	CRC32[2].CRCOUT[0]
CELL[16].OUT_BEL[14]	GTX_DUAL.RXSTATUS0[0]
CELL[16].OUT_BEL[15]	CRC32[2].CRCOUT[2]
CELL[16].OUT_BEL[16]	GTX_DUAL.RXDATA0[19]
CELL[16].OUT_BEL[17]	GTX_DUAL.RXDATA0[23]
CELL[16].OUT_BEL[18]	GTX_DUAL.TXRUNDISP0[3]
CELL[16].OUT_BEL[19]	GTX_DUAL.RXRUNDISP0[2]
CELL[16].OUT_BEL[20]	GTX_DUAL.RXCLKCORCNT0[2]
CELL[16].OUT_BEL[21]	GTX_DUAL.RXSTATUS0[2]
CELL[16].OUT_BEL[22]	GTX_DUAL.RXPRBSERR0
CELL[16].OUT_BEL[23]	GTX_DUAL.RXCLKCORCNT0[1]
CELL[17].IMUX_IMUX_DELAY[0]	CRC32[2].CRCRESET
CELL[17].IMUX_IMUX_DELAY[7]	GTX_DUAL.TXCHARDISPMODE0[3]
CELL[17].IMUX_IMUX_DELAY[8]	GTX_DUAL.TXCHARISK0[3]
CELL[17].IMUX_IMUX_DELAY[10]	GTX_DUAL.TXPOWERDOWN0[0]
CELL[17].IMUX_IMUX_DELAY[11]	GTX_DUAL.TXPOWERDOWN0[1]
CELL[17].IMUX_IMUX_DELAY[15]	GTX_DUAL.TXPOLARITY0
CELL[17].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXDATA0[27]
CELL[17].IMUX_IMUX_DELAY[21]	GTX_DUAL.TXDATA0[26]
CELL[17].IMUX_IMUX_DELAY[22]	GTX_DUAL.TXDATA0[25]
CELL[17].IMUX_IMUX_DELAY[23]	GTX_DUAL.TXDATA0[24]
CELL[17].IMUX_IMUX_DELAY[25]	GTX_DUAL.TXCHARDISPVAL0[3]
CELL[17].IMUX_IMUX_DELAY[26]	GTX_DUAL.TXCHARDISPVAL0[1]
CELL[17].IMUX_IMUX_DELAY[27]	GTX_DUAL.TXCHARDISPMODE0[1]
CELL[17].IMUX_IMUX_DELAY[28]	GTX_DUAL.TXCHARISK0[1]
CELL[17].IMUX_IMUX_DELAY[29]	GTX_DUAL.TXBYPASS8B10B0[1]
CELL[17].IMUX_IMUX_DELAY[30]	CRC32[2].CRCIN[8]
CELL[17].IMUX_IMUX_DELAY[31]	CRC32[2].CRCIN[9]
CELL[17].IMUX_IMUX_DELAY[32]	CRC32[2].CRCIN[10]
CELL[17].IMUX_IMUX_DELAY[33]	CRC32[2].CRCIN[11]
CELL[17].IMUX_IMUX_DELAY[34]	CRC32[2].CRCIN[12]
CELL[17].IMUX_IMUX_DELAY[35]	CRC32[2].CRCIN[13]
CELL[17].IMUX_IMUX_DELAY[37]	GTX_DUAL.TXPREEMPHASIS0[3]
CELL[17].IMUX_IMUX_DELAY[42]	GTX_DUAL.TXDATA0[11]
CELL[17].IMUX_IMUX_DELAY[43]	GTX_DUAL.TXDATA0[10]
CELL[17].IMUX_IMUX_DELAY[44]	GTX_DUAL.TXDATA0[9]
CELL[17].IMUX_IMUX_DELAY[45]	GTX_DUAL.TXDATA0[8]
CELL[17].IMUX_IMUX_DELAY[46]	CRC32[2].CRCIN[14]
CELL[17].IMUX_IMUX_DELAY[47]	CRC32[2].CRCIN[15]
CELL[17].OUT_BEL[1]	CRC32[2].CRCOUT[4]
CELL[17].OUT_BEL[2]	GTX_DUAL.TXRUNDISP0[1]
CELL[17].OUT_BEL[4]	GTX_DUAL.RXDISPERR0[2]
CELL[17].OUT_BEL[5]	GTX_DUAL.RXELECIDLE0
CELL[17].OUT_BEL[6]	CRC32[2].CRCOUT[9]
CELL[17].OUT_BEL[7]	GTX_DUAL.RXNOTINTABLE0[3]
CELL[17].OUT_BEL[8]	CRC32[2].CRCOUT[3]
CELL[17].OUT_BEL[9]	GTX_DUAL.RXDATA0[24]
CELL[17].OUT_BEL[10]	GTX_DUAL.RXDATA0[26]
CELL[17].OUT_BEL[12]	GTX_DUAL.RXCHARISK0[2]
CELL[17].OUT_BEL[13]	CRC32[2].CRCOUT[5]
CELL[17].OUT_BEL[14]	CRC32[2].CRCOUT[7]
CELL[17].OUT_BEL[15]	CRC32[2].CRCOUT[10]
CELL[17].OUT_BEL[16]	GTX_DUAL.RXDATA0[27]
CELL[17].OUT_BEL[17]	CRC32[2].CRCOUT[11]
CELL[17].OUT_BEL[18]	GTX_DUAL.TXKERR0[1]
CELL[17].OUT_BEL[19]	CRC32[2].CRCOUT[6]
CELL[17].OUT_BEL[20]	CRC32[2].CRCOUT[8]
CELL[17].OUT_BEL[21]	GTX_DUAL.RXCHARISCOMMA0[3]
CELL[17].OUT_BEL[22]	GTX_DUAL.TXKERR0[3]
CELL[17].OUT_BEL[23]	GTX_DUAL.RXDATA0[25]
CELL[18].IMUX_CLK[0]	CRC32[2].CRCCLK
CELL[18].IMUX_IMUX_DELAY[2]	GTX_DUAL.TXSEQUENCE0[0]
CELL[18].IMUX_IMUX_DELAY[3]	GTX_DUAL.TXSEQUENCE0[1]
CELL[18].IMUX_IMUX_DELAY[4]	GTX_DUAL.TXCOMSTART0
CELL[18].IMUX_IMUX_DELAY[5]	GTX_DUAL.TXCOMTYPE0
CELL[18].IMUX_IMUX_DELAY[6]	CRC32[2].CRCIN[16]
CELL[18].IMUX_IMUX_DELAY[7]	CRC32[2].CRCIN[17]
CELL[18].IMUX_IMUX_DELAY[8]	CRC32[2].CRCIN[18]
CELL[18].IMUX_IMUX_DELAY[10]	CRC32[2].CRCIN[20]
CELL[18].IMUX_IMUX_DELAY[11]	CRC32[2].CRCIN[21]
CELL[18].IMUX_IMUX_DELAY[15]	GTX_DUAL.TXPREEMPHASIS0[0]
CELL[18].IMUX_IMUX_DELAY[16]	GTX_DUAL.TXPREEMPHASIS0[1]
CELL[18].IMUX_IMUX_DELAY[17]	GTX_DUAL.TXPREEMPHASIS0[2]
CELL[18].IMUX_IMUX_DELAY[21]	CRC32[2].CRCIN[19]
CELL[18].IMUX_IMUX_DELAY[24]	GTX_DUAL.TXENPRBSTST0[0]
CELL[18].IMUX_IMUX_DELAY[25]	GTX_DUAL.TXENPRBSTST0[1]
CELL[18].IMUX_IMUX_DELAY[26]	GTX_DUAL.TXCHARDISPVAL0[0]
CELL[18].IMUX_IMUX_DELAY[27]	GTX_DUAL.TXCHARDISPMODE0[0]
CELL[18].IMUX_IMUX_DELAY[28]	GTX_DUAL.TXCHARISK0[2]
CELL[18].IMUX_IMUX_DELAY[29]	GTX_DUAL.TXBYPASS8B10B0[0]
CELL[18].IMUX_IMUX_DELAY[30]	GTX_DUAL.TSTPWRDNOVRD0
CELL[18].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXDATA0[23]
CELL[18].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXDATA0[22]
CELL[18].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDATA0[21]
CELL[18].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDATA0[20]
CELL[18].IMUX_IMUX_DELAY[40]	CRC32[2].CRCIN[22]
CELL[18].IMUX_IMUX_DELAY[41]	CRC32[2].CRCIN[23]
CELL[18].IMUX_IMUX_DELAY[42]	GTX_DUAL.TXDATA0[7]
CELL[18].IMUX_IMUX_DELAY[43]	GTX_DUAL.TXDATA0[6]
CELL[18].IMUX_IMUX_DELAY[44]	GTX_DUAL.TXDATA0[5]
CELL[18].IMUX_IMUX_DELAY[45]	GTX_DUAL.TXDATA0[4]
CELL[18].IMUX_IMUX_DELAY[46]	GTX_DUAL.TXCHARISK0[0]
CELL[18].OUT_BEL[0]	GTX_DUAL.TXBUFSTATUS0[0]
CELL[18].OUT_BEL[3]	CRC32[2].CRCOUT[16]
CELL[18].OUT_BEL[4]	GTX_DUAL.RXDISPERR0[3]
CELL[18].OUT_BEL[5]	GTX_DUAL.TXKERR0[0]
CELL[18].OUT_BEL[6]	CRC32[2].CRCOUT[15]
CELL[18].OUT_BEL[7]	CRC32[2].CRCOUT[17]
CELL[18].OUT_BEL[8]	GTX_DUAL.RXRUNDISP0[3]
CELL[18].OUT_BEL[9]	CRC32[2].CRCOUT[13]
CELL[18].OUT_BEL[10]	CRC32[2].CRCOUT[14]
CELL[18].OUT_BEL[11]	GTX_DUAL.RXDATA0[31]
CELL[18].OUT_BEL[12]	CRC32[2].CRCOUT[12]
CELL[18].OUT_BEL[13]	GTX_DUAL.TXKERR0[2]
CELL[18].OUT_BEL[15]	GTX_DUAL.TXRUNDISP0[2]
CELL[18].OUT_BEL[16]	GTX_DUAL.RXDATA0[29]
CELL[18].OUT_BEL[17]	CRC32[2].CRCOUT[18]
CELL[18].OUT_BEL[18]	GTX_DUAL.RXCHARISK0[3]
CELL[18].OUT_BEL[19]	GTX_DUAL.RXDATA0[28]
CELL[18].OUT_BEL[20]	GTX_DUAL.RXDATA0[30]
CELL[18].OUT_BEL[21]	CRC32[2].CRCOUT[19]
CELL[18].OUT_BEL[22]	GTX_DUAL.TXRUNDISP0[0]
CELL[18].OUT_BEL[23]	GTX_DUAL.TXBUFSTATUS0[1]
CELL[19].IMUX_IMUX_DELAY[0]	GTX_DUAL.TXSEQUENCE0[2]
CELL[19].IMUX_IMUX_DELAY[1]	GTX_DUAL.TXSEQUENCE0[3]
CELL[19].IMUX_IMUX_DELAY[2]	GTX_DUAL.TXCHARDISPVAL0[2]
CELL[19].IMUX_IMUX_DELAY[3]	GTX_DUAL.TXSEQUENCE0[4]
CELL[19].IMUX_IMUX_DELAY[4]	GTX_DUAL.TXSEQUENCE0[5]
CELL[19].IMUX_IMUX_DELAY[5]	GTX_DUAL.TXSEQUENCE0[6]
CELL[19].IMUX_IMUX_DELAY[6]	GTX_DUAL.GTXTEST[6]
CELL[19].IMUX_IMUX_DELAY[10]	CRC32[2].CRCIN[28]
CELL[19].IMUX_IMUX_DELAY[11]	CRC32[2].CRCIN[29]
CELL[19].IMUX_IMUX_DELAY[12]	GTX_DUAL.TXDATA0[19]
CELL[19].IMUX_IMUX_DELAY[15]	GTX_DUAL.TXCHARDISPMODE0[2]
CELL[19].IMUX_IMUX_DELAY[17]	GTX_DUAL.SCANEN
CELL[19].IMUX_IMUX_DELAY[18]	GTX_DUAL.TXDETECTRX0
CELL[19].IMUX_IMUX_DELAY[19]	GTX_DUAL.TXELECIDLE0
CELL[19].IMUX_IMUX_DELAY[20]	GTX_DUAL.TXDATA0[18]
CELL[19].IMUX_IMUX_DELAY[21]	CRC32[2].CRCIN[27]
CELL[19].IMUX_IMUX_DELAY[22]	GTX_DUAL.TXDATA0[17]
CELL[19].IMUX_IMUX_DELAY[23]	GTX_DUAL.TXDATA0[16]
CELL[19].IMUX_IMUX_DELAY[24]	CRC32[2].CRCIN[24]
CELL[19].IMUX_IMUX_DELAY[25]	CRC32[2].CRCIN[25]
CELL[19].IMUX_IMUX_DELAY[26]	CRC32[2].CRCIN[26]
CELL[19].IMUX_IMUX_DELAY[27]	GTX_DUAL.GTXTEST[0]
CELL[19].IMUX_IMUX_DELAY[28]	GTX_DUAL.GTXTEST[5]
CELL[19].IMUX_IMUX_DELAY[29]	GTX_DUAL.GTXTEST[7]
CELL[19].IMUX_IMUX_DELAY[30]	GTX_DUAL.TXBUFDIFFCTRL0[0]
CELL[19].IMUX_IMUX_DELAY[31]	GTX_DUAL.TXBUFDIFFCTRL0[1]
CELL[19].IMUX_IMUX_DELAY[32]	GTX_DUAL.TXBUFDIFFCTRL0[2]
CELL[19].IMUX_IMUX_DELAY[33]	GTX_DUAL.TXDIFFCTRL0[0]
CELL[19].IMUX_IMUX_DELAY[34]	GTX_DUAL.TXDIFFCTRL0[1]
CELL[19].IMUX_IMUX_DELAY[35]	GTX_DUAL.TXDIFFCTRL0[2]
CELL[19].IMUX_IMUX_DELAY[40]	CRC32[2].CRCIN[30]
CELL[19].IMUX_IMUX_DELAY[41]	CRC32[2].CRCIN[31]
CELL[19].IMUX_IMUX_DELAY[42]	GTX_DUAL.TXDATA0[3]
CELL[19].IMUX_IMUX_DELAY[43]	GTX_DUAL.TXDATA0[2]
CELL[19].IMUX_IMUX_DELAY[44]	GTX_DUAL.TXDATA0[1]
CELL[19].IMUX_IMUX_DELAY[45]	GTX_DUAL.TXDATA0[0]
CELL[19].IMUX_IMUX_DELAY[47]	GTX_DUAL.SCANINPCS0
CELL[19].OUT_BEL[0]	GTX_DUAL.RXHEADER0[1]
CELL[19].OUT_BEL[1]	CRC32[2].CRCOUT[22]
CELL[19].OUT_BEL[3]	CRC32[2].CRCOUT[28]
CELL[19].OUT_BEL[4]	CRC32[2].CRCOUT[21]
CELL[19].OUT_BEL[5]	CRC32[2].CRCOUT[23]
CELL[19].OUT_BEL[6]	CRC32[2].CRCOUT[27]
CELL[19].OUT_BEL[7]	CRC32[2].CRCOUT[29]
CELL[19].OUT_BEL[8]	GTX_DUAL.RXHEADERVALID0
CELL[19].OUT_BEL[9]	GTX_DUAL.RXHEADER0[2]
CELL[19].OUT_BEL[10]	CRC32[2].CRCOUT[26]
CELL[19].OUT_BEL[11]	CRC32[2].CRCOUT[30]
CELL[19].OUT_BEL[12]	CRC32[2].CRCOUT[20]
CELL[19].OUT_BEL[16]	GTX_DUAL.TXGEARBOXREADY0
CELL[19].OUT_BEL[18]	GTX_DUAL.RXSTARTOFSEQ0
CELL[19].OUT_BEL[19]	CRC32[2].CRCOUT[24]
CELL[19].OUT_BEL[20]	CRC32[2].CRCOUT[25]
CELL[19].OUT_BEL[21]	CRC32[2].CRCOUT[31]
CELL[19].OUT_BEL[22]	GTX_DUAL.RXHEADER0[0]
CELL[19].OUT_BEL[23]	GTX_DUAL.RXDATAVALID0

Bitstream

virtex5 GTX rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[2]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 12	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 13	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 14	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 15	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 16	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 17	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 18	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 19	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 20	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 21	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 22	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 23	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 24	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 25	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 26	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 27	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 28	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 29	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 30	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 31	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: ENABLE64	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[3]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 0	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 1	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 2	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 3	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 4	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 5	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 6	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 7	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 8	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 9	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 10	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[0]: CRC_INIT bit 11	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[4]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[5]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 2	GTX_DUAL: DRP[7] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 3
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 13 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 1	GTX_DUAL: DRP[7] bit 12 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 0
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 10 GTX_DUAL: PMA_RX_CFG_1 bit 7	GTX_DUAL: DRP[7] bit 11 GTX_DUAL: PMA_RX_CFG_1 bit 6
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 9 GTX_DUAL: PMA_RX_CFG_1 bit 8	GTX_DUAL: DRP[7] bit 8 GTX_DUAL: PMA_RX_CFG_1 bit 9
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 6 GTX_DUAL: PMA_RX_CFG_0 bit 23	GTX_DUAL: DRP[7] bit 7 GTX_DUAL: PMA_RX_CFG_1 bit 10
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 5 GTX_DUAL: PMA_RX_CFG_1 bit 2	GTX_DUAL: DRP[7] bit 4 GTX_DUAL: PMA_RX_CFG_1 bit 3
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 2 GTX_DUAL: PMA_RX_CFG_1 bit 5	GTX_DUAL: DRP[7] bit 3 GTX_DUAL: PMA_RX_CFG_1 bit 4
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[7] bit 1 GTX_DUAL: RX_CDR_FORCE_ROTATE_1	GTX_DUAL: DRP[7] bit 0 GTX_DUAL: PMA_RX_CFG_1 bit 13
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 14 GTX_DUAL: PMA_RX_CFG_1 bit 15	GTX_DUAL: DRP[6] bit 15 GTX_DUAL: PMA_RX_CFG_1 bit 14
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 13 GTX_DUAL: PMA_RX_CFG_1 bit 16	GTX_DUAL: DRP[6] bit 12 GTX_DUAL: PMA_RX_CFG_1 bit 17
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 10 GTX_DUAL: PMA_RX_CFG_1 bit 19	GTX_DUAL: DRP[6] bit 11 GTX_DUAL: PMA_RX_CFG_1 bit 18
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 9 GTX_DUAL: PMA_RX_CFG_1 bit 20	GTX_DUAL: DRP[6] bit 8 GTX_DUAL: PMA_RX_CFG_1 bit 21
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 6 GTX_DUAL: PMA_RX_CFG_0 bit 11	GTX_DUAL: DRP[6] bit 7 GTX_DUAL: PMA_RX_CFG_1 bit 22
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 5 GTX_DUAL: PMA_RX_CFG_0 bit 0	GTX_DUAL: DRP[6] bit 4 GTX_DUAL: PMA_RX_CFG_0 bit 1
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 2 GTX_DUAL: PMA_RX_CFG_0 bit 12	GTX_DUAL: DRP[6] bit 3 GTX_DUAL: PMA_RX_CFG_0 bit 24
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[6] bit 1 GTX_DUAL: AC_CAP_DIS_1	GTX_DUAL: DRP[6] bit 0
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 14 GTX_DUAL: RCV_TERM_VTTRX_1	GTX_DUAL: DRP[5] bit 15 GTX_DUAL: RCV_TERM_GND_1
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 13 GTX_DUAL: PMA_COM_CFG bit 22	GTX_DUAL: DRP[5] bit 12 GTX_DUAL: PMA_COM_CFG bit 23
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 10 GTX_DUAL: PMA_COM_CFG bit 25	GTX_DUAL: DRP[5] bit 11 GTX_DUAL: PMA_COM_CFG bit 24
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 9 GTX_DUAL: PMA_COM_CFG bit 26	GTX_DUAL: DRP[5] bit 8 GTX_DUAL: PMA_COM_CFG bit 21
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 6	GTX_DUAL: DRP[5] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 5	GTX_DUAL: DRP[5] bit 4 GTX_DUAL: PLL_TXDIVSEL_OUT_1 bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 2	GTX_DUAL: DRP[5] bit 3 GTX_DUAL: PLL_TXDIVSEL_OUT_1 bit 1
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[5] bit 1 GTX_DUAL: PLL_LKDET_CFG bit 0	GTX_DUAL: DRP[5] bit 0 GTX_DUAL: PLL_LKDET_CFG bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 14	GTX_DUAL: DRP[4] bit 15 GTX_DUAL: PLL_LKDET_CFG bit 2
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 13 GTX_DUAL: PLL_DIVSEL_REF bit 0	GTX_DUAL: DRP[4] bit 12 GTX_DUAL: PLL_DIVSEL_REF bit 4
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 10 GTX_DUAL: PLL_DIVSEL_REF bit 2	GTX_DUAL: DRP[4] bit 11 GTX_DUAL: PLL_DIVSEL_REF bit 3
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 9 GTX_DUAL: PLL_DIVSEL_REF bit 1	GTX_DUAL: DRP[4] bit 8 GTX_DUAL: MUX_CLKOUT_NORTH bit 0
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 6 GTX_DUAL: MUX_CLKIN bit 0	GTX_DUAL: DRP[4] bit 7 GTX_DUAL: MUX_CLKOUT_SOUTH bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 5 GTX_DUAL: MUX_CLKIN bit 1	GTX_DUAL: DRP[4] bit 4 GTX_DUAL: MUX_CLKIN bit 2
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 2	GTX_DUAL: DRP[4] bit 3 GTX_DUAL: CLKINDC_B
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[4] bit 1 GTX_DUAL: TX_IDLE_DELAY_1 bit 0	GTX_DUAL: DRP[4] bit 0 GTX_DUAL: TX_IDLE_DELAY_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 14 GTX_DUAL: RX_EN_IDLE_HOLD_DFE_1	GTX_DUAL: DRP[3] bit 15 GTX_DUAL: TX_IDLE_DELAY_1 bit 2
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 13	GTX_DUAL: DRP[3] bit 12 GTX_DUAL: RX_EN_IDLE_RESET_BUF_1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 10	GTX_DUAL: DRP[3] bit 11
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 9 GTX_DUAL: RX_IDLE_HI_CNT_1 bit 0	GTX_DUAL: DRP[3] bit 8 GTX_DUAL: RX_IDLE_HI_CNT_1 bit 1
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 6 GTX_DUAL: RX_IDLE_HI_CNT_1 bit 3	GTX_DUAL: DRP[3] bit 7 GTX_DUAL: RX_IDLE_HI_CNT_1 bit 2
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 5	GTX_DUAL: DRP[3] bit 4 GTX_DUAL: RX_IDLE_LO_CNT_1 bit 0
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 2 GTX_DUAL: RX_IDLE_LO_CNT_1 bit 2	GTX_DUAL: DRP[3] bit 3 GTX_DUAL: RX_IDLE_LO_CNT_1 bit 1
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[3] bit 1 GTX_DUAL: RX_IDLE_LO_CNT_1 bit 3	GTX_DUAL: DRP[3] bit 0 GTX_DUAL: CB2_INH_CC_PERIOD_1 bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 14 GTX_DUAL: CB2_INH_CC_PERIOD_1 bit 2	GTX_DUAL: DRP[2] bit 15 GTX_DUAL: CB2_INH_CC_PERIOD_1 bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 13 GTX_DUAL: CB2_INH_CC_PERIOD_1 bit 3	GTX_DUAL: DRP[2] bit 12 GTX_DUAL: CHAN_BOND_KEEP_ALIGN_1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 10 GTX_DUAL: GEARBOX_ENDEC_1 bit 1	GTX_DUAL: DRP[2] bit 11 GTX_DUAL: GEARBOX_ENDEC_1 bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 9 GTX_DUAL: GEARBOX_ENDEC_1 bit 2	GTX_DUAL: DRP[2] bit 8 GTX_DUAL: RXGEARBOX_USE_1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 6 GTX_DUAL: DFE_CFG_1 bit 0	GTX_DUAL: DRP[2] bit 7 GTX_DUAL: TXGEARBOX_USE_1
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 5 GTX_DUAL: DFE_CFG_1 bit 1	GTX_DUAL: DRP[2] bit 4 GTX_DUAL: DFE_CFG_1 bit 2
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 2 GTX_DUAL: DFE_CFG_1 bit 4	GTX_DUAL: DRP[2] bit 3 GTX_DUAL: DFE_CFG_1 bit 3
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[2] bit 1 GTX_DUAL: DFE_CFG_1 bit 5	GTX_DUAL: DRP[2] bit 0 GTX_DUAL: DFE_CFG_1 bit 6
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 14 GTX_DUAL: DFE_CFG_1 bit 8	GTX_DUAL: DRP[1] bit 15 GTX_DUAL: DFE_CFG_1 bit 7
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 13 GTX_DUAL: DFE_CFG_1 bit 9	GTX_DUAL: DRP[1] bit 12 GTX_DUAL: CM_TRIM_1 bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 10 GTX_DUAL: PMA_TX_CFG_1 bit 0	GTX_DUAL: DRP[1] bit 11 GTX_DUAL: CM_TRIM_1 bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 9 GTX_DUAL: PMA_TX_CFG_1 bit 1	GTX_DUAL: DRP[1] bit 8 GTX_DUAL: PMA_TX_CFG_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 6 GTX_DUAL: PMA_TX_CFG_1 bit 4	GTX_DUAL: DRP[1] bit 7 GTX_DUAL: PMA_TX_CFG_1 bit 3
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 5 GTX_DUAL: PMA_TX_CFG_1 bit 5	GTX_DUAL: DRP[1] bit 4 GTX_DUAL: PMA_TX_CFG_1 bit 6
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 2 GTX_DUAL: PMA_TX_CFG_1 bit 8	GTX_DUAL: DRP[1] bit 3 GTX_DUAL: PMA_TX_CFG_1 bit 7
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[1] bit 1 GTX_DUAL: PMA_TX_CFG_1 bit 9	GTX_DUAL: DRP[1] bit 0 GTX_DUAL: PMA_TX_CFG_1 bit 10
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 14 GTX_DUAL: PMA_TX_CFG_1 bit 12	GTX_DUAL: DRP[0] bit 15 GTX_DUAL: PMA_TX_CFG_1 bit 11
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 13 GTX_DUAL: PMA_TX_CFG_1 bit 13	GTX_DUAL: DRP[0] bit 12 GTX_DUAL: PMA_TX_CFG_1 bit 14
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 10 GTX_DUAL: PMA_TX_CFG_1 bit 16	GTX_DUAL: DRP[0] bit 11 GTX_DUAL: PMA_TX_CFG_1 bit 15
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 9 GTX_DUAL: PMA_TX_CFG_1 bit 17	GTX_DUAL: DRP[0] bit 8 GTX_DUAL: PMA_TX_CFG_1 bit 18
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 6 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 0	GTX_DUAL: DRP[0] bit 7 GTX_DUAL: PMA_TX_CFG_1 bit 19
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 5 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 1	GTX_DUAL: DRP[0] bit 4 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 2
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 2 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 4	GTX_DUAL: DRP[0] bit 3 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[0] bit 1 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 5	GTX_DUAL: DRP[0] bit 0 GTX_DUAL: PMA_RXSYNC_CFG_1 bit 6

virtex5 GTX rect MAIN[6]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 14 GTX_DUAL: SATA_MAX_WAKE_1 bit 1	GTX_DUAL: DRP[15] bit 15 GTX_DUAL: SATA_MAX_WAKE_1 bit 0
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 13 GTX_DUAL: SATA_MAX_WAKE_1 bit 2	GTX_DUAL: DRP[15] bit 12 GTX_DUAL: SATA_MAX_WAKE_1 bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 10 GTX_DUAL: SATA_MAX_WAKE_1 bit 5	GTX_DUAL: DRP[15] bit 11 GTX_DUAL: SATA_MAX_WAKE_1 bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 9 GTX_DUAL: SATA_MAX_INIT_1 bit 0	GTX_DUAL: DRP[15] bit 8 GTX_DUAL: SATA_MAX_INIT_1 bit 1
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 6 GTX_DUAL: SATA_MAX_INIT_1 bit 3	GTX_DUAL: DRP[15] bit 7 GTX_DUAL: SATA_MAX_INIT_1 bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 5 GTX_DUAL: SATA_MAX_INIT_1 bit 4	GTX_DUAL: DRP[15] bit 4 GTX_DUAL: SATA_MAX_INIT_1 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 2 GTX_DUAL: SATA_MAX_BURST_1 bit 1	GTX_DUAL: DRP[15] bit 3 GTX_DUAL: SATA_MAX_BURST_1 bit 0
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[15] bit 1 GTX_DUAL: SATA_MAX_BURST_1 bit 2	GTX_DUAL: DRP[15] bit 0 GTX_DUAL: SATA_MAX_BURST_1 bit 3
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 14 GTX_DUAL: SATA_MAX_BURST_1 bit 5	GTX_DUAL: DRP[14] bit 15 GTX_DUAL: SATA_MAX_BURST_1 bit 4
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 13 GTX_DUAL: SATA_IDLE_VAL_1 bit 0	GTX_DUAL: DRP[14] bit 12 GTX_DUAL: SATA_IDLE_VAL_1 bit 1
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 10 GTX_DUAL: SATA_BURST_VAL_1 bit 0	GTX_DUAL: DRP[14] bit 11 GTX_DUAL: SATA_IDLE_VAL_1 bit 2
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 9 GTX_DUAL: SATA_BURST_VAL_1 bit 1	GTX_DUAL: DRP[14] bit 8 GTX_DUAL: SATA_BURST_VAL_1 bit 2
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 6 GTX_DUAL: RX_STATUS_FMT_1 bit 0	GTX_DUAL: DRP[14] bit 7 GTX_DUAL: RX_XCLK_SEL_1 bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 5 GTX_DUAL: RX_SLIDE_MODE_1 bit 0	GTX_DUAL: DRP[14] bit 4 GTX_DUAL: RX_LOS_THRESHOLD_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 2 GTX_DUAL: RX_LOS_THRESHOLD_1 bit 2	GTX_DUAL: DRP[14] bit 3 GTX_DUAL: RX_LOS_THRESHOLD_1 bit 1
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[14] bit 1 GTX_DUAL: RX_LOSS_OF_SYNC_FSM_1	GTX_DUAL: DRP[14] bit 0 GTX_DUAL: RX_LOS_INVALID_INCR_1 bit 0
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 14 GTX_DUAL: RX_LOS_INVALID_INCR_1 bit 2	GTX_DUAL: DRP[13] bit 15 GTX_DUAL: RX_LOS_INVALID_INCR_1 bit 1
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 13 GTX_DUAL: RX_DECODE_SEQ_MATCH_1	GTX_DUAL: DRP[13] bit 12 GTX_DUAL: RX_BUFFER_USE_1
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 10 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 1	GTX_DUAL: DRP[13] bit 11 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 0
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 9 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 2	GTX_DUAL: DRP[13] bit 8 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 6 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 5	GTX_DUAL: DRP[13] bit 7 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 4
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 5 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 6	GTX_DUAL: DRP[13] bit 4 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 7
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 2 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 9	GTX_DUAL: DRP[13] bit 3 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 8
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[13] bit 1 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 10	GTX_DUAL: DRP[13] bit 0 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 11
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 14 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 13	GTX_DUAL: DRP[12] bit 15 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 12
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 13 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 14	GTX_DUAL: DRP[12] bit 12 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 15
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 10 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 17	GTX_DUAL: DRP[12] bit 11 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 16
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 9 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 18	GTX_DUAL: DRP[12] bit 8 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 19
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 6 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 21	GTX_DUAL: DRP[12] bit 7 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 20
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 5 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 22	GTX_DUAL: DRP[12] bit 4 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 23
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 2 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 25	GTX_DUAL: DRP[12] bit 3 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 24
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[12] bit 1 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 26	GTX_DUAL: DRP[12] bit 0 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 27
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 14 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 29	GTX_DUAL: DRP[11] bit 15 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 28
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 13 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 30	GTX_DUAL: DRP[11] bit 12 GTX_DUAL: PRBS_ERR_THRESHOLD_1 bit 31
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 10 GTX_DUAL: PMA_CDR_SCAN_1 bit 1	GTX_DUAL: DRP[11] bit 11 GTX_DUAL: PMA_CDR_SCAN_1 bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 9 GTX_DUAL: PMA_CDR_SCAN_1 bit 2	GTX_DUAL: DRP[11] bit 8 GTX_DUAL: PMA_CDR_SCAN_1 bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 6 GTX_DUAL: PMA_CDR_SCAN_1 bit 5	GTX_DUAL: DRP[11] bit 7 GTX_DUAL: PMA_CDR_SCAN_1 bit 4
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 5 GTX_DUAL: PMA_CDR_SCAN_1 bit 6	GTX_DUAL: DRP[11] bit 4 GTX_DUAL: PMA_CDR_SCAN_1 bit 7
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 2 GTX_DUAL: PMA_CDR_SCAN_1 bit 9	GTX_DUAL: DRP[11] bit 3 GTX_DUAL: PMA_CDR_SCAN_1 bit 8
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[11] bit 1 GTX_DUAL: PMA_CDR_SCAN_1 bit 10	GTX_DUAL: DRP[11] bit 0 GTX_DUAL: PMA_CDR_SCAN_1 bit 11
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 14 GTX_DUAL: PMA_CDR_SCAN_1 bit 13	GTX_DUAL: DRP[10] bit 15 GTX_DUAL: PMA_CDR_SCAN_1 bit 12
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 13 GTX_DUAL: PMA_CDR_SCAN_1 bit 14	GTX_DUAL: DRP[10] bit 12 GTX_DUAL: PMA_CDR_SCAN_1 bit 15
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 10 GTX_DUAL: PMA_CDR_SCAN_1 bit 17	GTX_DUAL: DRP[10] bit 11 GTX_DUAL: PMA_CDR_SCAN_1 bit 16
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 9 GTX_DUAL: PMA_CDR_SCAN_1 bit 18	GTX_DUAL: DRP[10] bit 8 GTX_DUAL: PMA_CDR_SCAN_1 bit 19
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 6 GTX_DUAL: PMA_CDR_SCAN_1 bit 21	GTX_DUAL: DRP[10] bit 7 GTX_DUAL: PMA_CDR_SCAN_1 bit 20
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 5 GTX_DUAL: PMA_CDR_SCAN_1 bit 22	GTX_DUAL: DRP[10] bit 4 GTX_DUAL: PMA_CDR_SCAN_1 bit 23
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 2 GTX_DUAL: PMA_CDR_SCAN_1 bit 25	GTX_DUAL: DRP[10] bit 3 GTX_DUAL: PMA_CDR_SCAN_1 bit 24
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[10] bit 1 GTX_DUAL: PMA_CDR_SCAN_1 bit 26	GTX_DUAL: DRP[10] bit 0 GTX_DUAL: PLL_RXDIVSEL_OUT_1 bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 14 GTX_DUAL: PLL_SATA_1	GTX_DUAL: DRP[9] bit 15 GTX_DUAL: PLL_RXDIVSEL_OUT_1 bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 13	GTX_DUAL: DRP[9] bit 12 GTX_DUAL: CLKRCV_TRST
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 10 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 0	GTX_DUAL: DRP[9] bit 11 GTX_DUAL: PCOMMA_DETECT_1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 9 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 1	GTX_DUAL: DRP[9] bit 8 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 2
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 6 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 4	GTX_DUAL: DRP[9] bit 7 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 3
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 5 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 5	GTX_DUAL: DRP[9] bit 4 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 6
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 2 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 8	GTX_DUAL: DRP[9] bit 3 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 7
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[9] bit 1 GTX_DUAL: PCOMMA_10B_VALUE_1 bit 9	GTX_DUAL: DRP[9] bit 0 GTX_DUAL: PCI_EXPRESS_MODE_1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 8	GTX_DUAL: DRP[8] bit 15
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 13 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 7	GTX_DUAL: DRP[8] bit 12 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 6
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 10 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 4	GTX_DUAL: DRP[8] bit 11 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 3	GTX_DUAL: DRP[8] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 0	GTX_DUAL: DRP[8] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 5 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 9	GTX_DUAL: DRP[8] bit 4 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 8
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 2 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 6	GTX_DUAL: DRP[8] bit 3 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 7
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[8] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 5	GTX_DUAL: DRP[8] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_4_1 bit 4

virtex5 GTX rect MAIN[7]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 14 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 9	GTX_DUAL: DRP[23] bit 15 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 8
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 13 GTX_DUAL: CLK_COR_REPEAT_WAIT_1 bit 0	GTX_DUAL: DRP[23] bit 12 GTX_DUAL: CLK_COR_REPEAT_WAIT_1 bit 1
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 10 GTX_DUAL: CLK_COR_REPEAT_WAIT_1 bit 3	GTX_DUAL: DRP[23] bit 11 GTX_DUAL: CLK_COR_REPEAT_WAIT_1 bit 2
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 9 GTX_DUAL: CLK_COR_REPEAT_WAIT_1 bit 4	GTX_DUAL: DRP[23] bit 8 GTX_DUAL: CLK_CORRECT_USE_1
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 6 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 0	GTX_DUAL: DRP[23] bit 7 GTX_DUAL: CLK_COR_PRECEDENCE_1
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 5 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 1	GTX_DUAL: DRP[23] bit 4 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 2
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 2 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 4	GTX_DUAL: DRP[23] bit 3 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 3
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[23] bit 1 GTX_DUAL: CLK_COR_MIN_LAT_1 bit 5	GTX_DUAL: DRP[23] bit 0 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 14 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 2	GTX_DUAL: DRP[22] bit 15 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 13 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 3	GTX_DUAL: DRP[22] bit 12 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 4
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 10 GTX_DUAL: CLK_COR_KEEP_IDLE_1	GTX_DUAL: DRP[22] bit 11 GTX_DUAL: CLK_COR_MAX_LAT_1 bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 9 GTX_DUAL: CLK_COR_INSERT_IDLE_FLAG_1	GTX_DUAL: DRP[22] bit 8 GTX_DUAL: CLK_COR_DET_LEN_1 bit 0
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 6 GTX_DUAL: CLK_COR_ADJ_LEN_1 bit 0	GTX_DUAL: DRP[22] bit 7 GTX_DUAL: CLK_COR_DET_LEN_1 bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 5 GTX_DUAL: CLK_COR_ADJ_LEN_1 bit 1	GTX_DUAL: DRP[22] bit 4 GTX_DUAL: CHAN_BOND_SEQ_LEN_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 2 GTX_DUAL: CHAN_BOND_SEQ_2_USE_1	GTX_DUAL: DRP[22] bit 3 GTX_DUAL: CHAN_BOND_SEQ_LEN_1 bit 1
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[22] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_1 bit 0	GTX_DUAL: DRP[22] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_1 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_1 bit 3	GTX_DUAL: DRP[21] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_1 bit 2
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 13 GTX_DUAL: PMA_COM_CFG bit 8	GTX_DUAL: DRP[21] bit 12 GTX_DUAL: OOBDETECT_THRESHOLD_1 bit 0
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 10 GTX_DUAL: OOBDETECT_THRESHOLD_1 bit 2	GTX_DUAL: DRP[21] bit 11 GTX_DUAL: OOBDETECT_THRESHOLD_1 bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 9	GTX_DUAL: DRP[21] bit 8 GTX_DUAL: TXOUTCLK_SEL_1 bit 0
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 6	GTX_DUAL: DRP[21] bit 7 GTX_DUAL: TX_XCLK_SEL_1 bit 0
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 5	GTX_DUAL: DRP[21] bit 4 GTX_DUAL: TXRX_INVERT_1 bit 0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 2 GTX_DUAL: TXRX_INVERT_1 bit 2	GTX_DUAL: DRP[21] bit 3 GTX_DUAL: TXRX_INVERT_1 bit 1
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[21] bit 1 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 0	GTX_DUAL: DRP[21] bit 0 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 14 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 3	GTX_DUAL: DRP[20] bit 15 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 2
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 13 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 4	GTX_DUAL: DRP[20] bit 12 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 10 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 7	GTX_DUAL: DRP[20] bit 11 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 6
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 9 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 8	GTX_DUAL: DRP[20] bit 8 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 6 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 11	GTX_DUAL: DRP[20] bit 7 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 10
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 5 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 12	GTX_DUAL: DRP[20] bit 4 GTX_DUAL: TX_DETECT_RX_CFG_1 bit 13
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 2 GTX_DUAL: PLL_COM_CFG bit 23	GTX_DUAL: DRP[20] bit 3 GTX_DUAL: TX_BUFFER_USE_1
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[20] bit 1 GTX_DUAL: PLL_COM_CFG bit 22	GTX_DUAL: DRP[20] bit 0 GTX_DUAL: PLL_COM_CFG bit 21
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 14	GTX_DUAL: DRP[19] bit 15 GTX_DUAL: PLL_COM_CFG bit 20
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 13	GTX_DUAL: DRP[19] bit 12 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 10 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 2	GTX_DUAL: DRP[19] bit 11 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 1
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 9 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 3	GTX_DUAL: DRP[19] bit 8 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 4
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 6 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 6	GTX_DUAL: DRP[19] bit 7 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 5
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 5 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 7	GTX_DUAL: DRP[19] bit 4 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 8
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 2	GTX_DUAL: DRP[19] bit 3 GTX_DUAL: TRANS_TIME_TO_P2_1 bit 9
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[19] bit 1	GTX_DUAL: DRP[19] bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 14	GTX_DUAL: DRP[18] bit 15
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 13	GTX_DUAL: DRP[18] bit 12
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 10 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 0	GTX_DUAL: DRP[18] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 9 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 1	GTX_DUAL: DRP[18] bit 8 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 2
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 6 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 4	GTX_DUAL: DRP[18] bit 7 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 3
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 5 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 5	GTX_DUAL: DRP[18] bit 4 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 6
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 2	GTX_DUAL: DRP[18] bit 3 GTX_DUAL: TRANS_TIME_NON_P2_1 bit 7
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[18] bit 1	GTX_DUAL: DRP[18] bit 0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 14 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 0	GTX_DUAL: DRP[17] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 13 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 1	GTX_DUAL: DRP[17] bit 12 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 2
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 10 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 4	GTX_DUAL: DRP[17] bit 11 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 3
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 9 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 5	GTX_DUAL: DRP[17] bit 8 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 6
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 6 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 8	GTX_DUAL: DRP[17] bit 7 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 7
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 5 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 9	GTX_DUAL: DRP[17] bit 4 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 10
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 2 GTX_DUAL: TERMINATION_IMP_1 bit 0	GTX_DUAL: DRP[17] bit 3 GTX_DUAL: TRANS_TIME_FROM_P2_1 bit 11
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[17] bit 1 GTX_DUAL: SATA_MIN_WAKE_1 bit 0	GTX_DUAL: DRP[17] bit 0 GTX_DUAL: SATA_MIN_WAKE_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 14 GTX_DUAL: SATA_MIN_WAKE_1 bit 3	GTX_DUAL: DRP[16] bit 15 GTX_DUAL: SATA_MIN_WAKE_1 bit 2
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 13 GTX_DUAL: SATA_MIN_WAKE_1 bit 4	GTX_DUAL: DRP[16] bit 12 GTX_DUAL: SATA_MIN_WAKE_1 bit 5
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 10 GTX_DUAL: SATA_MIN_INIT_1 bit 1	GTX_DUAL: DRP[16] bit 11 GTX_DUAL: SATA_MIN_INIT_1 bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 9 GTX_DUAL: SATA_MIN_INIT_1 bit 2	GTX_DUAL: DRP[16] bit 8 GTX_DUAL: SATA_MIN_INIT_1 bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 6 GTX_DUAL: SATA_MIN_INIT_1 bit 5	GTX_DUAL: DRP[16] bit 7 GTX_DUAL: SATA_MIN_INIT_1 bit 4
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 5 GTX_DUAL: SATA_MIN_BURST_1 bit 0	GTX_DUAL: DRP[16] bit 4 GTX_DUAL: SATA_MIN_BURST_1 bit 1
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 2 GTX_DUAL: SATA_MIN_BURST_1 bit 3	GTX_DUAL: DRP[16] bit 3 GTX_DUAL: SATA_MIN_BURST_1 bit 2
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[16] bit 1 GTX_DUAL: SATA_MIN_BURST_1 bit 4	GTX_DUAL: DRP[16] bit 0 GTX_DUAL: SATA_MIN_BURST_1 bit 5

virtex5 GTX rect MAIN[8]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 28	GTX_DUAL: DRP[31] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 8	GTX_DUAL: DRP[31] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 9
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 29	-	GTX_DUAL: DRP[31] bit 13	GTX_DUAL: DRP[31] bit 12 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 7
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 30	GTX_DUAL: DRP[31] bit 10 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 5	GTX_DUAL: DRP[31] bit 11 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 6
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 31	-	GTX_DUAL: DRP[31] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 4	GTX_DUAL: DRP[31] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 3
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[31] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 1	GTX_DUAL: DRP[31] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[31] bit 5 GTX_DUAL: CHAN_BOND_SEQ_2_2_1 bit 0	GTX_DUAL: DRP[31] bit 4 GTX_DUAL: CHAN_BOND_SEQ_2_3_1 bit 9
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[31] bit 2 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 0	GTX_DUAL: DRP[31] bit 3 GTX_DUAL: MCOMMA_DETECT_1
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[31] bit 1 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 1	GTX_DUAL: DRP[31] bit 0 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 2
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 14 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 4	GTX_DUAL: DRP[30] bit 15 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 3
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 13 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 5	GTX_DUAL: DRP[30] bit 12 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 6
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 10 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 8	GTX_DUAL: DRP[30] bit 11 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 7
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 9 GTX_DUAL: MCOMMA_10B_VALUE_1 bit 9	GTX_DUAL: DRP[30] bit 8 GTX_DUAL: DEC_VALID_COMMA_ONLY_1
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 6 GTX_DUAL: DEC_MCOMMA_DETECT_1	GTX_DUAL: DRP[30] bit 7 GTX_DUAL: DEC_PCOMMA_DETECT_1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 5 GTX_DUAL: COMMA_DOUBLE_1	GTX_DUAL: DRP[30] bit 4 GTX_DUAL: COMMA_10B_ENABLE_1 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 2 GTX_DUAL: COMMA_10B_ENABLE_1 bit 2	GTX_DUAL: DRP[30] bit 3 GTX_DUAL: COMMA_10B_ENABLE_1 bit 1
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[30] bit 1 GTX_DUAL: COMMA_10B_ENABLE_1 bit 3	GTX_DUAL: DRP[30] bit 0 GTX_DUAL: COMMA_10B_ENABLE_1 bit 4
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 14 GTX_DUAL: COMMA_10B_ENABLE_1 bit 6	GTX_DUAL: DRP[29] bit 15 GTX_DUAL: COMMA_10B_ENABLE_1 bit 5
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 13 GTX_DUAL: COMMA_10B_ENABLE_1 bit 7	GTX_DUAL: DRP[29] bit 12 GTX_DUAL: COMMA_10B_ENABLE_1 bit 8
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 10 GTX_DUAL: COM_BURST_VAL_1 bit 0	GTX_DUAL: DRP[29] bit 11 GTX_DUAL: COMMA_10B_ENABLE_1 bit 9
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 9 GTX_DUAL: COM_BURST_VAL_1 bit 1	GTX_DUAL: DRP[29] bit 8 GTX_DUAL: COM_BURST_VAL_1 bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 6 GTX_DUAL: CLK_COR_SEQ_2_USE_1	GTX_DUAL: DRP[29] bit 7 GTX_DUAL: COM_BURST_VAL_1 bit 3
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 5 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_1 bit 0	GTX_DUAL: DRP[29] bit 4 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_1 bit 1
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 2 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_1 bit 3	GTX_DUAL: DRP[29] bit 3 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_1 bit 2
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[29] bit 1 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 0	GTX_DUAL: DRP[29] bit 0 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 14 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 3	GTX_DUAL: DRP[28] bit 15 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 2
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 13 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 4	GTX_DUAL: DRP[28] bit 12 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 5
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 10 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 7	GTX_DUAL: DRP[28] bit 11 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 6
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 9 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 8	GTX_DUAL: DRP[28] bit 8 GTX_DUAL: CLK_COR_SEQ_2_4_1 bit 9
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 6 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 1	GTX_DUAL: DRP[28] bit 7 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 5 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 2	GTX_DUAL: DRP[28] bit 4 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 3
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 2 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 5	GTX_DUAL: DRP[28] bit 3 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 4
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[28] bit 1 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 6	GTX_DUAL: DRP[28] bit 0 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 7
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 14 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 9	GTX_DUAL: DRP[27] bit 15 GTX_DUAL: CLK_COR_SEQ_2_3_1 bit 8
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 13 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 0	GTX_DUAL: DRP[27] bit 12 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 10 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 3	GTX_DUAL: DRP[27] bit 11 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 2
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 9 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 4	GTX_DUAL: DRP[27] bit 8 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 5
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 6 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 7	GTX_DUAL: DRP[27] bit 7 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 6
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 5 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 8	GTX_DUAL: DRP[27] bit 4 GTX_DUAL: CLK_COR_SEQ_2_2_1 bit 9
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 2 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 1	GTX_DUAL: DRP[27] bit 3 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 0
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[27] bit 1 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 2	GTX_DUAL: DRP[27] bit 0 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 3
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 14 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 5	GTX_DUAL: DRP[26] bit 15 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 4
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 13 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 6	GTX_DUAL: DRP[26] bit 12 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 7
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 10 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 9	GTX_DUAL: DRP[26] bit 11 GTX_DUAL: CLK_COR_SEQ_2_1_1 bit 8
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 9 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_1 bit 0	GTX_DUAL: DRP[26] bit 8 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_1 bit 1
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 6 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_1 bit 3	GTX_DUAL: DRP[26] bit 7 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_1 bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 5 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 0	GTX_DUAL: DRP[26] bit 4 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 1
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 2 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 3	GTX_DUAL: DRP[26] bit 3 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[26] bit 1 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 4	GTX_DUAL: DRP[26] bit 0 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 5
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 14 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 7	GTX_DUAL: DRP[25] bit 15 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 6
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 13 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 8	GTX_DUAL: DRP[25] bit 12 GTX_DUAL: CLK_COR_SEQ_1_4_1 bit 9
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 10 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 1	GTX_DUAL: DRP[25] bit 11 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 9 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 2	GTX_DUAL: DRP[25] bit 8 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 3
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 6 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 5	GTX_DUAL: DRP[25] bit 7 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 4
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 5 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 6	GTX_DUAL: DRP[25] bit 4 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 7
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 2 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 9	GTX_DUAL: DRP[25] bit 3 GTX_DUAL: CLK_COR_SEQ_1_3_1 bit 8
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[25] bit 1 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 0	GTX_DUAL: DRP[25] bit 0 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 14 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 3	GTX_DUAL: DRP[24] bit 15 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 2
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 13 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 4	GTX_DUAL: DRP[24] bit 12 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 5
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 10 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 7	GTX_DUAL: DRP[24] bit 11 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 6
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 9 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 8	GTX_DUAL: DRP[24] bit 8 GTX_DUAL: CLK_COR_SEQ_1_2_1 bit 9
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 6 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 1	GTX_DUAL: DRP[24] bit 7 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 5 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 2	GTX_DUAL: DRP[24] bit 4 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 3
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 2 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 5	GTX_DUAL: DRP[24] bit 3 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 4
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[24] bit 1 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 6	GTX_DUAL: DRP[24] bit 0 GTX_DUAL: CLK_COR_SEQ_1_1_1 bit 7

virtex5 GTX rect MAIN[9]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 14 GTX_DUAL: PLL_COM_CFG bit 5	GTX_DUAL: DRP[39] bit 15 GTX_DUAL: PLL_COM_CFG bit 4
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 13 GTX_DUAL: PLL_COM_CFG bit 6	GTX_DUAL: DRP[39] bit 12 GTX_DUAL: PLL_COM_CFG bit 7
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 10 GTX_DUAL: PLL_COM_CFG bit 9	GTX_DUAL: DRP[39] bit 11 GTX_DUAL: PLL_COM_CFG bit 8
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 9 GTX_DUAL: PLL_COM_CFG bit 10	GTX_DUAL: DRP[39] bit 8 GTX_DUAL: PLL_COM_CFG bit 11
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 6 GTX_DUAL: PLL_COM_CFG bit 13	GTX_DUAL: DRP[39] bit 7 GTX_DUAL: PLL_COM_CFG bit 12
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 5 GTX_DUAL: PLL_COM_CFG bit 14	GTX_DUAL: DRP[39] bit 4 GTX_DUAL: PLL_COM_CFG bit 15
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 2 GTX_DUAL: PLL_COM_CFG bit 17	GTX_DUAL: DRP[39] bit 3 GTX_DUAL: PLL_COM_CFG bit 16
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[39] bit 1 GTX_DUAL: PLL_COM_CFG bit 18	GTX_DUAL: DRP[39] bit 0 GTX_DUAL: PLL_COM_CFG bit 19
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 14 GTX_DUAL: OOB_CLK_DIVIDER bit 0	GTX_DUAL: DRP[38] bit 15 GTX_DUAL: OVERSAMPLE_MODE
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 13 GTX_DUAL: OOB_CLK_DIVIDER bit 1	GTX_DUAL: DRP[38] bit 12 GTX_DUAL: OOB_CLK_DIVIDER bit 2
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 10 GTX_DUAL: CLK25_DIVIDER bit 1	GTX_DUAL: DRP[38] bit 11 GTX_DUAL: CLK25_DIVIDER bit 0
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 9 GTX_DUAL: CLK25_DIVIDER bit 2	GTX_DUAL: DRP[38] bit 8 GTX_DUAL: PMA_COM_CFG bit 48
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 6 GTX_DUAL: PMA_COM_CFG bit 44	GTX_DUAL: DRP[38] bit 7 GTX_DUAL: PMA_COM_CFG bit 46
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 5 GTX_DUAL: PMA_COM_CFG bit 42	GTX_DUAL: DRP[38] bit 4 GTX_DUAL: PMA_COM_CFG bit 38
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 2 GTX_DUAL: PMA_COM_CFG bit 36	GTX_DUAL: DRP[38] bit 3 GTX_DUAL: PMA_COM_CFG bit 40
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[38] bit 1 GTX_DUAL: PMA_COM_CFG bit 34	GTX_DUAL: DRP[38] bit 0 GTX_DUAL: PMA_COM_CFG bit 56
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 14 GTX_DUAL: PMA_COM_CFG bit 64	GTX_DUAL: DRP[37] bit 15 GTX_DUAL: PMA_COM_CFG bit 54
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 13 GTX_DUAL: PMA_COM_CFG bit 62	GTX_DUAL: DRP[37] bit 12 GTX_DUAL: PMA_COM_CFG bit 61
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 10 GTX_DUAL: PMA_COM_CFG bit 68	GTX_DUAL: DRP[37] bit 11 GTX_DUAL: PMA_COM_CFG bit 63
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 9 GTX_DUAL: PMA_COM_CFG bit 66	GTX_DUAL: DRP[37] bit 8
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 6	GTX_DUAL: DRP[37] bit 7
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 5	GTX_DUAL: DRP[37] bit 4
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 2 GTX_DUAL: PMA_COM_CFG bit 50	GTX_DUAL: DRP[37] bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[37] bit 1 GTX_DUAL: PMA_COM_CFG bit 52	GTX_DUAL: DRP[37] bit 0
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 14	GTX_DUAL: DRP[36] bit 15
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 13	GTX_DUAL: DRP[36] bit 12 GTX_DUAL: PMA_COM_CFG bit 10
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 10 GTX_DUAL: PMA_COM_CFG bit 12	GTX_DUAL: DRP[36] bit 11 GTX_DUAL: PMA_COM_CFG bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 9 GTX_DUAL: PMA_COM_CFG bit 13	GTX_DUAL: DRP[36] bit 8 GTX_DUAL: PMA_COM_CFG bit 14
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 6 GTX_DUAL: PMA_COM_CFG bit 16	GTX_DUAL: DRP[36] bit 7 GTX_DUAL: PMA_COM_CFG bit 15
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 5 GTX_DUAL: PMA_COM_CFG bit 17	GTX_DUAL: DRP[36] bit 4 GTX_DUAL: PMA_COM_CFG bit 18
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 2 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_1 bit 3	GTX_DUAL: DRP[36] bit 3 GTX_DUAL: ALIGN_COMMA_WORD_1 bit 0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[36] bit 1 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_1 bit 2	GTX_DUAL: DRP[36] bit 0 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_1 bit 1
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[35] bit 14 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_1 bit 3	GTX_DUAL: DRP[35] bit 15 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_1 bit 0
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[35] bit 13 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_1 bit 2	GTX_DUAL: DRP[35] bit 12 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_1 bit 1
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[35] bit 10 GTX_DUAL: CHAN_BOND_LEVEL_1 bit 2	GTX_DUAL: DRP[35] bit 11 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_1 bit 0
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[35] bit 9 GTX_DUAL: CHAN_BOND_LEVEL_1 bit 1	GTX_DUAL: DRP[35] bit 8 GTX_DUAL: CHAN_BOND_LEVEL_1 bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 0	GTX_DUAL: DRP[35] bit 6 GTX_DUAL: CHAN_BOND_MODE_1 bit 0	GTX_DUAL: DRP[35] bit 7 GTX_DUAL: CHAN_BOND_MODE_1 bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 1	GTX_DUAL: DRP[35] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 9	GTX_DUAL: DRP[35] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 8
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 2	-	GTX_DUAL: DRP[35] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 6	GTX_DUAL: DRP[35] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 7
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 3	GTX_DUAL: DRP[35] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 5	GTX_DUAL: DRP[35] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 4
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 4	-	GTX_DUAL: DRP[34] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 2	GTX_DUAL: DRP[34] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 3
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 5	GTX_DUAL: DRP[34] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 1	GTX_DUAL: DRP[34] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_1_1 bit 0
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 6	-	GTX_DUAL: DRP[34] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 8	GTX_DUAL: DRP[34] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 9
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 7	GTX_DUAL: DRP[34] bit 9 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 7	GTX_DUAL: DRP[34] bit 8 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 6
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 8	-	GTX_DUAL: DRP[34] bit 6 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 4	GTX_DUAL: DRP[34] bit 7 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 5
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 9	GTX_DUAL: DRP[34] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 3	GTX_DUAL: DRP[34] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 2
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 10	-	GTX_DUAL: DRP[34] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 0	GTX_DUAL: DRP[34] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_2_1 bit 1
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[34] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 9	GTX_DUAL: DRP[34] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 8
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 11	GTX_DUAL: DRP[33] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 6	GTX_DUAL: DRP[33] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 7
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 12	-	GTX_DUAL: DRP[33] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 5	GTX_DUAL: DRP[33] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 4
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 13	GTX_DUAL: DRP[33] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 2	GTX_DUAL: DRP[33] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 3
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 14	CRC32[1]: CRC_INIT bit 15	GTX_DUAL: DRP[33] bit 9 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 1	GTX_DUAL: DRP[33] bit 8 GTX_DUAL: CHAN_BOND_SEQ_1_3_1 bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 16	-	GTX_DUAL: DRP[33] bit 6 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 8	GTX_DUAL: DRP[33] bit 7 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 9
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 17	GTX_DUAL: DRP[33] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 7	GTX_DUAL: DRP[33] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 6
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 18	-	GTX_DUAL: DRP[33] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 4	GTX_DUAL: DRP[33] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 5
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 19	-	GTX_DUAL: DRP[33] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 3	GTX_DUAL: DRP[33] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 2
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 20	GTX_DUAL: DRP[32] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 0	GTX_DUAL: DRP[32] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_4_1 bit 1
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 21	CRC32[1]: CRC_INIT bit 22	GTX_DUAL: DRP[32] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_1 bit 3	GTX_DUAL: DRP[32] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_1 bit 2
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[32] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_1 bit 0	GTX_DUAL: DRP[32] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_1 bit 1
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 23	-	GTX_DUAL: DRP[32] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 9	GTX_DUAL: DRP[32] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 8
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 25	CRC32[1]: CRC_INIT bit 24	GTX_DUAL: DRP[32] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 6	GTX_DUAL: DRP[32] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 7
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[32] bit 5 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 5	GTX_DUAL: DRP[32] bit 4 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 26	GTX_DUAL: DRP[32] bit 2 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 2	GTX_DUAL: DRP[32] bit 3 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[1]: CRC_INIT bit 27	-	GTX_DUAL: DRP[32] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 1	GTX_DUAL: DRP[32] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_1_1 bit 0

virtex5 GTX rect MAIN[10]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 27	-	GTX_DUAL: DRP[47] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 1	GTX_DUAL: DRP[47] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 0
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 26	GTX_DUAL: DRP[47] bit 13 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 2	GTX_DUAL: DRP[47] bit 12 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 3
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[47] bit 10 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 5	GTX_DUAL: DRP[47] bit 11 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 4
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 25	CRC32[3]: CRC_INIT bit 24	GTX_DUAL: DRP[47] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 6	GTX_DUAL: DRP[47] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 7
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 23	-	GTX_DUAL: DRP[47] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 9	GTX_DUAL: DRP[47] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_1_0 bit 8
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[47] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_0 bit 0	GTX_DUAL: DRP[47] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_0 bit 1
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 21	CRC32[3]: CRC_INIT bit 22	GTX_DUAL: DRP[47] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_0 bit 3	GTX_DUAL: DRP[47] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_ENABLE_0 bit 2
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 20	GTX_DUAL: DRP[47] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 0	GTX_DUAL: DRP[47] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 1
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 19	-	GTX_DUAL: DRP[46] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 3	GTX_DUAL: DRP[46] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 2
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 18	-	GTX_DUAL: DRP[46] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 4	GTX_DUAL: DRP[46] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 5
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 17	GTX_DUAL: DRP[46] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 7	GTX_DUAL: DRP[46] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 6
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 16	-	GTX_DUAL: DRP[46] bit 9 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 8	GTX_DUAL: DRP[46] bit 8 GTX_DUAL: CHAN_BOND_SEQ_1_4_0 bit 9
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 14	CRC32[3]: CRC_INIT bit 15	GTX_DUAL: DRP[46] bit 6 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 1	GTX_DUAL: DRP[46] bit 7 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 0
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 13	GTX_DUAL: DRP[46] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 2	GTX_DUAL: DRP[46] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 3
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 12	-	GTX_DUAL: DRP[46] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 5	GTX_DUAL: DRP[46] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 4
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 11	GTX_DUAL: DRP[46] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 6	GTX_DUAL: DRP[46] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 7
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[45] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 9	GTX_DUAL: DRP[45] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_3_0 bit 8
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 10	-	GTX_DUAL: DRP[45] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 0	GTX_DUAL: DRP[45] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 1
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 9	GTX_DUAL: DRP[45] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 3	GTX_DUAL: DRP[45] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 2
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 8	-	GTX_DUAL: DRP[45] bit 9 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 4	GTX_DUAL: DRP[45] bit 8 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 5
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 7	GTX_DUAL: DRP[45] bit 6 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 7	GTX_DUAL: DRP[45] bit 7 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 6
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 6	-	GTX_DUAL: DRP[45] bit 5 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 8	GTX_DUAL: DRP[45] bit 4 GTX_DUAL: CHAN_BOND_SEQ_1_2_0 bit 9
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 5	GTX_DUAL: DRP[45] bit 2 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 1	GTX_DUAL: DRP[45] bit 3 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 0
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 4	-	GTX_DUAL: DRP[45] bit 1 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 2	GTX_DUAL: DRP[45] bit 0 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 3
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 3	GTX_DUAL: DRP[44] bit 14 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 5	GTX_DUAL: DRP[44] bit 15 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 4
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 2	-	GTX_DUAL: DRP[44] bit 13 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 6	GTX_DUAL: DRP[44] bit 12 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 7
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 1	GTX_DUAL: DRP[44] bit 10 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 9	GTX_DUAL: DRP[44] bit 11 GTX_DUAL: CHAN_BOND_SEQ_1_1_0 bit 8
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 0	GTX_DUAL: DRP[44] bit 9 GTX_DUAL: CHAN_BOND_MODE_0 bit 0	GTX_DUAL: DRP[44] bit 8 GTX_DUAL: CHAN_BOND_MODE_0 bit 1
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[44] bit 6 GTX_DUAL: CHAN_BOND_LEVEL_0 bit 1	GTX_DUAL: DRP[44] bit 7 GTX_DUAL: CHAN_BOND_LEVEL_0 bit 0
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[44] bit 5 GTX_DUAL: CHAN_BOND_LEVEL_0 bit 2	GTX_DUAL: DRP[44] bit 4 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_0 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[44] bit 2 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_0 bit 2	GTX_DUAL: DRP[44] bit 3 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_0 bit 1
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[44] bit 1 GTX_DUAL: CHAN_BOND_2_MAX_SKEW_0 bit 3	GTX_DUAL: DRP[44] bit 0 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_0 bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 14 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_0 bit 2	GTX_DUAL: DRP[43] bit 15 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_0 bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 13 GTX_DUAL: CHAN_BOND_1_MAX_SKEW_0 bit 3	GTX_DUAL: DRP[43] bit 12 GTX_DUAL: ALIGN_COMMA_WORD_0 bit 0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 10 GTX_DUAL: PMA_COM_CFG bit 1	GTX_DUAL: DRP[43] bit 11 GTX_DUAL: PMA_COM_CFG bit 9
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 9 GTX_DUAL: PMA_COM_CFG bit 2	GTX_DUAL: DRP[43] bit 8 GTX_DUAL: PMA_COM_CFG bit 3
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 6 GTX_DUAL: PMA_COM_CFG bit 0	GTX_DUAL: DRP[43] bit 7 GTX_DUAL: PMA_COM_CFG bit 4
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 5 GTX_DUAL: PMA_COM_CFG bit 5	GTX_DUAL: DRP[43] bit 4 GTX_DUAL: PMA_COM_CFG bit 6
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 2	GTX_DUAL: DRP[43] bit 3 GTX_DUAL: PMA_COM_CFG bit 7
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[43] bit 1	GTX_DUAL: DRP[43] bit 0
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 14 GTX_DUAL: PMA_COM_CFG bit 51	GTX_DUAL: DRP[42] bit 15 GTX_DUAL: PMA_COM_CFG bit 49
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 13	GTX_DUAL: DRP[42] bit 12
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 10	GTX_DUAL: DRP[42] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 9	GTX_DUAL: DRP[42] bit 8
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 6 GTX_DUAL: PMA_COM_CFG bit 67	GTX_DUAL: DRP[42] bit 7 GTX_DUAL: PMA_COM_CFG bit 65
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 5 GTX_DUAL: PMA_COM_CFG bit 59	GTX_DUAL: DRP[42] bit 4 GTX_DUAL: PMA_COM_CFG bit 57
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 2 GTX_DUAL: PMA_COM_CFG bit 60	GTX_DUAL: DRP[42] bit 3 GTX_DUAL: PMA_COM_CFG bit 58
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[42] bit 1 GTX_DUAL: PMA_COM_CFG bit 55	GTX_DUAL: DRP[42] bit 0 GTX_DUAL: PMA_COM_CFG bit 53
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 14 GTX_DUAL: PMA_COM_CFG bit 33	GTX_DUAL: DRP[41] bit 15 GTX_DUAL: PMA_COM_CFG bit 35
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 13 GTX_DUAL: PMA_COM_CFG bit 37	GTX_DUAL: DRP[41] bit 12 GTX_DUAL: PMA_COM_CFG bit 39
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 10 GTX_DUAL: PMA_COM_CFG bit 43	GTX_DUAL: DRP[41] bit 11 GTX_DUAL: PMA_COM_CFG bit 41
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 9 GTX_DUAL: PMA_COM_CFG bit 45	GTX_DUAL: DRP[41] bit 8 GTX_DUAL: PMA_COM_CFG bit 47
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 6 GTX_DUAL: TERMINATION_OVRD	GTX_DUAL: DRP[41] bit 7 GTX_DUAL: PMA_COM_CFG bit 32
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 5 GTX_DUAL: TERMINATION_CTRL bit 0	GTX_DUAL: DRP[41] bit 4 GTX_DUAL: TERMINATION_CTRL bit 1
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 2 GTX_DUAL: TERMINATION_CTRL bit 3	GTX_DUAL: DRP[41] bit 3 GTX_DUAL: TERMINATION_CTRL bit 2
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[41] bit 1 GTX_DUAL: TERMINATION_CTRL bit 4	GTX_DUAL: DRP[41] bit 0 GTX_DUAL: PLL_DIVSEL_FB bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 14 GTX_DUAL: PLL_DIVSEL_FB bit 3	GTX_DUAL: DRP[40] bit 15 GTX_DUAL: PLL_DIVSEL_FB bit 2
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 13	GTX_DUAL: DRP[40] bit 12 GTX_DUAL: PLL_DIVSEL_FB bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 10 GTX_DUAL: PLL_CP_CFG bit 1	GTX_DUAL: DRP[40] bit 11 GTX_DUAL: PLL_CP_CFG bit 0
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 9 GTX_DUAL: PLL_CP_CFG bit 2	GTX_DUAL: DRP[40] bit 8 GTX_DUAL: PLL_CP_CFG bit 3
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 6 GTX_DUAL: PLL_CP_CFG bit 5	GTX_DUAL: DRP[40] bit 7 GTX_DUAL: PLL_CP_CFG bit 4
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 5 GTX_DUAL: PLL_CP_CFG bit 6	GTX_DUAL: DRP[40] bit 4 GTX_DUAL: PLL_CP_CFG bit 7
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 2 GTX_DUAL: PLL_COM_CFG bit 1	GTX_DUAL: DRP[40] bit 3 GTX_DUAL: PLL_COM_CFG bit 0
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[40] bit 1 GTX_DUAL: PLL_COM_CFG bit 2	GTX_DUAL: DRP[40] bit 0 GTX_DUAL: PLL_COM_CFG bit 3

virtex5 GTX rect MAIN[11]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 14 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 6	GTX_DUAL: DRP[55] bit 15 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 7
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 13 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 5	GTX_DUAL: DRP[55] bit 12 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 4
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 10 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 2	GTX_DUAL: DRP[55] bit 11 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 3
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 9 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 1	GTX_DUAL: DRP[55] bit 8 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 0
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 6 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 8	GTX_DUAL: DRP[55] bit 7 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 9
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 5 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 7	GTX_DUAL: DRP[55] bit 4 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 6
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 2 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 4	GTX_DUAL: DRP[55] bit 3 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 5
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[55] bit 1 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 3	GTX_DUAL: DRP[55] bit 0 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 2
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 14 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 0	GTX_DUAL: DRP[54] bit 15 GTX_DUAL: CLK_COR_SEQ_1_2_0 bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 13 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 9	GTX_DUAL: DRP[54] bit 12 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 8
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 10 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 6	GTX_DUAL: DRP[54] bit 11 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 7
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 9 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 5	GTX_DUAL: DRP[54] bit 8 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 4
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 6 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 2	GTX_DUAL: DRP[54] bit 7 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 3
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 5 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 1	GTX_DUAL: DRP[54] bit 4 GTX_DUAL: CLK_COR_SEQ_1_3_0 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 2 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 8	GTX_DUAL: DRP[54] bit 3 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 9
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[54] bit 1 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 7	GTX_DUAL: DRP[54] bit 0 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 6
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 14 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 4	GTX_DUAL: DRP[53] bit 15 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 5
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 13 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 3	GTX_DUAL: DRP[53] bit 12 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 10 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 0	GTX_DUAL: DRP[53] bit 11 GTX_DUAL: CLK_COR_SEQ_1_4_0 bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 9 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_0 bit 3	GTX_DUAL: DRP[53] bit 8 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_0 bit 2
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 6 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_0 bit 0	GTX_DUAL: DRP[53] bit 7 GTX_DUAL: CLK_COR_SEQ_1_ENABLE_0 bit 1
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 5 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 9	GTX_DUAL: DRP[53] bit 4 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 8
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 2 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 6	GTX_DUAL: DRP[53] bit 3 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 7
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[53] bit 1 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 5	GTX_DUAL: DRP[53] bit 0 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 4
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 14 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 2	GTX_DUAL: DRP[52] bit 15 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 13 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 1	GTX_DUAL: DRP[52] bit 12 GTX_DUAL: CLK_COR_SEQ_2_1_0 bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 10 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 8	GTX_DUAL: DRP[52] bit 11 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 9
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 9 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 7	GTX_DUAL: DRP[52] bit 8 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 6
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 6 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 4	GTX_DUAL: DRP[52] bit 7 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 5
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 5 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 3	GTX_DUAL: DRP[52] bit 4 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 2
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 2 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 0	GTX_DUAL: DRP[52] bit 3 GTX_DUAL: CLK_COR_SEQ_2_2_0 bit 1
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[52] bit 1 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 9	GTX_DUAL: DRP[52] bit 0 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 8
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 14 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 6	GTX_DUAL: DRP[51] bit 15 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 7
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 13 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 5	GTX_DUAL: DRP[51] bit 12 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 4
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 10 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 2	GTX_DUAL: DRP[51] bit 11 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 3
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 9 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 1	GTX_DUAL: DRP[51] bit 8 GTX_DUAL: CLK_COR_SEQ_2_3_0 bit 0
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 6 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 8	GTX_DUAL: DRP[51] bit 7 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 9
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 5 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 7	GTX_DUAL: DRP[51] bit 4 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 6
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 2 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 4	GTX_DUAL: DRP[51] bit 3 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 5
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[51] bit 1 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 3	GTX_DUAL: DRP[51] bit 0 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 2
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 14 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 0	GTX_DUAL: DRP[50] bit 15 GTX_DUAL: CLK_COR_SEQ_2_4_0 bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 13 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_0 bit 3	GTX_DUAL: DRP[50] bit 12 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_0 bit 2
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 10 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_0 bit 0	GTX_DUAL: DRP[50] bit 11 GTX_DUAL: CLK_COR_SEQ_2_ENABLE_0 bit 1
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 9 GTX_DUAL: CLK_COR_SEQ_2_USE_0	GTX_DUAL: DRP[50] bit 8 GTX_DUAL: COM_BURST_VAL_0 bit 3
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 6 GTX_DUAL: COM_BURST_VAL_0 bit 1	GTX_DUAL: DRP[50] bit 7 GTX_DUAL: COM_BURST_VAL_0 bit 2
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 5 GTX_DUAL: COM_BURST_VAL_0 bit 0	GTX_DUAL: DRP[50] bit 4 GTX_DUAL: COMMA_10B_ENABLE_0 bit 9
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 2 GTX_DUAL: COMMA_10B_ENABLE_0 bit 7	GTX_DUAL: DRP[50] bit 3 GTX_DUAL: COMMA_10B_ENABLE_0 bit 8
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[50] bit 1 GTX_DUAL: COMMA_10B_ENABLE_0 bit 6	GTX_DUAL: DRP[50] bit 0 GTX_DUAL: COMMA_10B_ENABLE_0 bit 5
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 14 GTX_DUAL: COMMA_10B_ENABLE_0 bit 3	GTX_DUAL: DRP[49] bit 15 GTX_DUAL: COMMA_10B_ENABLE_0 bit 4
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 13 GTX_DUAL: COMMA_10B_ENABLE_0 bit 2	GTX_DUAL: DRP[49] bit 12 GTX_DUAL: COMMA_10B_ENABLE_0 bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 10 GTX_DUAL: COMMA_DOUBLE_0	GTX_DUAL: DRP[49] bit 11 GTX_DUAL: COMMA_10B_ENABLE_0 bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 9 GTX_DUAL: DEC_MCOMMA_DETECT_0	GTX_DUAL: DRP[49] bit 8 GTX_DUAL: DEC_PCOMMA_DETECT_0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 6 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 9	GTX_DUAL: DRP[49] bit 7 GTX_DUAL: DEC_VALID_COMMA_ONLY_0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 5 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 8	GTX_DUAL: DRP[49] bit 4 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 7
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 2 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 5	GTX_DUAL: DRP[49] bit 3 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 6
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[49] bit 1 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 4	GTX_DUAL: DRP[49] bit 0 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 3
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[48] bit 14 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 1	GTX_DUAL: DRP[48] bit 15 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 2
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[48] bit 13 GTX_DUAL: MCOMMA_10B_VALUE_0 bit 0	GTX_DUAL: DRP[48] bit 12 GTX_DUAL: MCOMMA_DETECT_0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[48] bit 10 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 0	GTX_DUAL: DRP[48] bit 11 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 9
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[48] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 1	GTX_DUAL: DRP[48] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 31	-	GTX_DUAL: DRP[48] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 4	GTX_DUAL: DRP[48] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 3
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 30	GTX_DUAL: DRP[48] bit 5 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 5	GTX_DUAL: DRP[48] bit 4 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 6
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 29	-	GTX_DUAL: DRP[48] bit 2 GTX_DUAL: PLL_FB_DCCEN	GTX_DUAL: DRP[48] bit 3 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 7
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: CRC_INIT bit 28	GTX_DUAL: DRP[48] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 8	GTX_DUAL: DRP[48] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_2_0 bit 9

virtex5 GTX rect MAIN[12]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 14 GTX_DUAL: SATA_MIN_BURST_0 bit 4	GTX_DUAL: DRP[63] bit 15 GTX_DUAL: SATA_MIN_BURST_0 bit 5
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 13 GTX_DUAL: SATA_MIN_BURST_0 bit 3	GTX_DUAL: DRP[63] bit 12 GTX_DUAL: SATA_MIN_BURST_0 bit 2
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 10 GTX_DUAL: SATA_MIN_BURST_0 bit 0	GTX_DUAL: DRP[63] bit 11 GTX_DUAL: SATA_MIN_BURST_0 bit 1
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 9 GTX_DUAL: SATA_MIN_INIT_0 bit 5	GTX_DUAL: DRP[63] bit 8 GTX_DUAL: SATA_MIN_INIT_0 bit 4
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 6 GTX_DUAL: SATA_MIN_INIT_0 bit 2	GTX_DUAL: DRP[63] bit 7 GTX_DUAL: SATA_MIN_INIT_0 bit 3
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 5 GTX_DUAL: SATA_MIN_INIT_0 bit 1	GTX_DUAL: DRP[63] bit 4 GTX_DUAL: SATA_MIN_INIT_0 bit 0
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 2 GTX_DUAL: SATA_MIN_WAKE_0 bit 4	GTX_DUAL: DRP[63] bit 3 GTX_DUAL: SATA_MIN_WAKE_0 bit 5
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[63] bit 1 GTX_DUAL: SATA_MIN_WAKE_0 bit 3	GTX_DUAL: DRP[63] bit 0 GTX_DUAL: SATA_MIN_WAKE_0 bit 2
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 14 GTX_DUAL: SATA_MIN_WAKE_0 bit 0	GTX_DUAL: DRP[62] bit 15 GTX_DUAL: SATA_MIN_WAKE_0 bit 1
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 13 GTX_DUAL: TERMINATION_IMP_0 bit 0	GTX_DUAL: DRP[62] bit 12 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 11
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 10 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 9	GTX_DUAL: DRP[62] bit 11 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 10
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 9 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 8	GTX_DUAL: DRP[62] bit 8 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 7
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 6 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 5	GTX_DUAL: DRP[62] bit 7 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 6
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 5 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 4	GTX_DUAL: DRP[62] bit 4 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 3
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 2 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 1	GTX_DUAL: DRP[62] bit 3 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 2
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[62] bit 1 GTX_DUAL: TRANS_TIME_FROM_P2_0 bit 0	GTX_DUAL: DRP[62] bit 0
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 14	GTX_DUAL: DRP[61] bit 15
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 13	GTX_DUAL: DRP[61] bit 12 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 7
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 10 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 5	GTX_DUAL: DRP[61] bit 11 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 6
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 9 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 4	GTX_DUAL: DRP[61] bit 8 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 3
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 6 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 1	GTX_DUAL: DRP[61] bit 7 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 2
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 5 GTX_DUAL: TRANS_TIME_NON_P2_0 bit 0	GTX_DUAL: DRP[61] bit 4
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 2 GTX_DUAL: CDR_PH_ADJ_TIME bit 3	GTX_DUAL: DRP[61] bit 3 GTX_DUAL: CDR_PH_ADJ_TIME bit 4
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[61] bit 1 GTX_DUAL: CDR_PH_ADJ_TIME bit 2	GTX_DUAL: DRP[61] bit 0 GTX_DUAL: CDR_PH_ADJ_TIME bit 1
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 14	GTX_DUAL: DRP[60] bit 15 GTX_DUAL: CDR_PH_ADJ_TIME bit 0
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 13	GTX_DUAL: DRP[60] bit 12 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 9
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 10 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 7	GTX_DUAL: DRP[60] bit 11 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 8
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 9 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 6	GTX_DUAL: DRP[60] bit 8 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 5
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 6 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 3	GTX_DUAL: DRP[60] bit 7 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 4
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 5 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 2	GTX_DUAL: DRP[60] bit 4 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 1
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 2 GTX_DUAL: DFE_CAL_TIME bit 4	GTX_DUAL: DRP[60] bit 3 GTX_DUAL: TRANS_TIME_TO_P2_0 bit 0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[60] bit 1 GTX_DUAL: DFE_CAL_TIME bit 3	GTX_DUAL: DRP[60] bit 0 GTX_DUAL: DFE_CAL_TIME bit 2
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 14 GTX_DUAL: DFE_CAL_TIME bit 0	GTX_DUAL: DRP[59] bit 15 GTX_DUAL: DFE_CAL_TIME bit 1
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 13	GTX_DUAL: DRP[59] bit 12 GTX_DUAL: TX_BUFFER_USE_0
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 10 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 12	GTX_DUAL: DRP[59] bit 11 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 13
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 9 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 11	GTX_DUAL: DRP[59] bit 8 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 10
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 6 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 8	GTX_DUAL: DRP[59] bit 7 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 9
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 5 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 7	GTX_DUAL: DRP[59] bit 4 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 6
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 2 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 4	GTX_DUAL: DRP[59] bit 3 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 5
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[59] bit 1 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 3	GTX_DUAL: DRP[59] bit 0 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 2
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 14 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 0	GTX_DUAL: DRP[58] bit 15 GTX_DUAL: TX_DETECT_RX_CFG_0 bit 1
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 13 GTX_DUAL: TXRX_INVERT_0 bit 2	GTX_DUAL: DRP[58] bit 12 GTX_DUAL: TXRX_INVERT_0 bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 10 GTX_DUAL: RX_EN_IDLE_RESET_FR	GTX_DUAL: DRP[58] bit 11 GTX_DUAL: TXRX_INVERT_0 bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 9 GTX_DUAL: RX_EN_IDLE_HOLD_CDR	GTX_DUAL: DRP[58] bit 8 GTX_DUAL: TX_XCLK_SEL_0 bit 0
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 6 GTX_DUAL: PMA_COM_CFG bit 19	GTX_DUAL: DRP[58] bit 7 GTX_DUAL: TXOUTCLK_SEL_0 bit 0
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 5 GTX_DUAL: OOBDETECT_THRESHOLD_0 bit 2	GTX_DUAL: DRP[58] bit 4 GTX_DUAL: OOBDETECT_THRESHOLD_0 bit 1
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 2 GTX_DUAL: RX_EN_IDLE_RESET_PH	GTX_DUAL: DRP[58] bit 3 GTX_DUAL: OOBDETECT_THRESHOLD_0 bit 0
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[58] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_0 bit 3	GTX_DUAL: DRP[58] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_0 bit 2
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_0 bit 0	GTX_DUAL: DRP[57] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_ENABLE_0 bit 1
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 13 GTX_DUAL: CHAN_BOND_SEQ_2_USE_0	GTX_DUAL: DRP[57] bit 12 GTX_DUAL: CHAN_BOND_SEQ_LEN_0 bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 10 GTX_DUAL: CLK_COR_ADJ_LEN_0 bit 1	GTX_DUAL: DRP[57] bit 11 GTX_DUAL: CHAN_BOND_SEQ_LEN_0 bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 9 GTX_DUAL: CLK_COR_ADJ_LEN_0 bit 0	GTX_DUAL: DRP[57] bit 8 GTX_DUAL: CLK_COR_DET_LEN_0 bit 1
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 6 GTX_DUAL: CLK_COR_INSERT_IDLE_FLAG_0	GTX_DUAL: DRP[57] bit 7 GTX_DUAL: CLK_COR_DET_LEN_0 bit 0
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 5 GTX_DUAL: CLK_COR_KEEP_IDLE_0	GTX_DUAL: DRP[57] bit 4 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 5
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 2 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 3	GTX_DUAL: DRP[57] bit 3 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 4
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[57] bit 1 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 2	GTX_DUAL: DRP[57] bit 0 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 1
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 14 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 5	GTX_DUAL: DRP[56] bit 15 GTX_DUAL: CLK_COR_MAX_LAT_0 bit 0
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 13 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 4	GTX_DUAL: DRP[56] bit 12 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 3
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 10 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 1	GTX_DUAL: DRP[56] bit 11 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 2
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 9 GTX_DUAL: CLK_COR_MIN_LAT_0 bit 0	GTX_DUAL: DRP[56] bit 8 GTX_DUAL: CLK_COR_PRECEDENCE_0
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 6 GTX_DUAL: CLK_COR_REPEAT_WAIT_0 bit 4	GTX_DUAL: DRP[56] bit 7 GTX_DUAL: CLK_CORRECT_USE_0
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 5 GTX_DUAL: CLK_COR_REPEAT_WAIT_0 bit 3	GTX_DUAL: DRP[56] bit 4 GTX_DUAL: CLK_COR_REPEAT_WAIT_0 bit 2
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 2 GTX_DUAL: CLK_COR_REPEAT_WAIT_0 bit 0	GTX_DUAL: DRP[56] bit 3 GTX_DUAL: CLK_COR_REPEAT_WAIT_0 bit 1
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[56] bit 1 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 9	GTX_DUAL: DRP[56] bit 0 GTX_DUAL: CLK_COR_SEQ_1_1_0 bit 8

virtex5 GTX rect MAIN[13]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 14 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 5	GTX_DUAL: DRP[71] bit 15 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 4
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 13 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 6	GTX_DUAL: DRP[71] bit 12 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 7
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 10 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 9	GTX_DUAL: DRP[71] bit 11 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 8
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 9 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 0	GTX_DUAL: DRP[71] bit 8 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 1
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 6 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 3	GTX_DUAL: DRP[71] bit 7 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 2
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 5 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 4	GTX_DUAL: DRP[71] bit 4 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 5
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 2 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 7	GTX_DUAL: DRP[71] bit 3 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 6
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[71] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_3_0 bit 8	GTX_DUAL: DRP[71] bit 0
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 14 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 9	GTX_DUAL: DRP[70] bit 15 GTX_DUAL: PCI_EXPRESS_MODE_0
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 13 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 8	GTX_DUAL: DRP[70] bit 12 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 7
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 10 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 5	GTX_DUAL: DRP[70] bit 11 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 6
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 9 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 4	GTX_DUAL: DRP[70] bit 8 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 3
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 6 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 1	GTX_DUAL: DRP[70] bit 7 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 2
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 5 GTX_DUAL: PCOMMA_10B_VALUE_0 bit 0	GTX_DUAL: DRP[70] bit 4 GTX_DUAL: PCOMMA_DETECT_0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 2 GTX_DUAL: PLL_RXDIVSEL_OUT_0 bit 0	GTX_DUAL: DRP[70] bit 3 GTX_DUAL: PLL_RXDIVSEL_OUT_0 bit 1
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[70] bit 1 GTX_DUAL: PLL_SATA_0	GTX_DUAL: DRP[70] bit 0 GTX_DUAL: PLL_TXDIVSEL_OUT_0 bit 1
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 14 GTX_DUAL: PMA_CDR_SCAN_0 bit 26	GTX_DUAL: DRP[69] bit 15 GTX_DUAL: PLL_TXDIVSEL_OUT_0 bit 0
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 13 GTX_DUAL: PMA_CDR_SCAN_0 bit 25	GTX_DUAL: DRP[69] bit 12 GTX_DUAL: PMA_CDR_SCAN_0 bit 24
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 10 GTX_DUAL: PMA_CDR_SCAN_0 bit 22	GTX_DUAL: DRP[69] bit 11 GTX_DUAL: PMA_CDR_SCAN_0 bit 23
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 9 GTX_DUAL: PMA_CDR_SCAN_0 bit 21	GTX_DUAL: DRP[69] bit 8 GTX_DUAL: PMA_CDR_SCAN_0 bit 20
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 6 GTX_DUAL: PMA_CDR_SCAN_0 bit 18	GTX_DUAL: DRP[69] bit 7 GTX_DUAL: PMA_CDR_SCAN_0 bit 19
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 5 GTX_DUAL: PMA_CDR_SCAN_0 bit 17	GTX_DUAL: DRP[69] bit 4 GTX_DUAL: PMA_CDR_SCAN_0 bit 16
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 2 GTX_DUAL: PMA_CDR_SCAN_0 bit 14	GTX_DUAL: DRP[69] bit 3 GTX_DUAL: PMA_CDR_SCAN_0 bit 15
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[69] bit 1 GTX_DUAL: PMA_CDR_SCAN_0 bit 13	GTX_DUAL: DRP[69] bit 0 GTX_DUAL: PMA_CDR_SCAN_0 bit 12
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 14 GTX_DUAL: PMA_CDR_SCAN_0 bit 10	GTX_DUAL: DRP[68] bit 15 GTX_DUAL: PMA_CDR_SCAN_0 bit 11
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 13 GTX_DUAL: PMA_CDR_SCAN_0 bit 9	GTX_DUAL: DRP[68] bit 12 GTX_DUAL: PMA_CDR_SCAN_0 bit 8
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 10 GTX_DUAL: PMA_CDR_SCAN_0 bit 6	GTX_DUAL: DRP[68] bit 11 GTX_DUAL: PMA_CDR_SCAN_0 bit 7
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 9 GTX_DUAL: PMA_CDR_SCAN_0 bit 5	GTX_DUAL: DRP[68] bit 8 GTX_DUAL: PMA_CDR_SCAN_0 bit 4
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 6 GTX_DUAL: PMA_CDR_SCAN_0 bit 2	GTX_DUAL: DRP[68] bit 7 GTX_DUAL: PMA_CDR_SCAN_0 bit 3
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 5 GTX_DUAL: PMA_CDR_SCAN_0 bit 1	GTX_DUAL: DRP[68] bit 4 GTX_DUAL: PMA_CDR_SCAN_0 bit 0
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 2 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 30	GTX_DUAL: DRP[68] bit 3 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 31
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[68] bit 1 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 29	GTX_DUAL: DRP[68] bit 0 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 28
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 14 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 26	GTX_DUAL: DRP[67] bit 15 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 27
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 13 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 25	GTX_DUAL: DRP[67] bit 12 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 24
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 10 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 22	GTX_DUAL: DRP[67] bit 11 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 23
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 9 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 21	GTX_DUAL: DRP[67] bit 8 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 20
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 6 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 18	GTX_DUAL: DRP[67] bit 7 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 19
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 5 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 17	GTX_DUAL: DRP[67] bit 4 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 16
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 2 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 14	GTX_DUAL: DRP[67] bit 3 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 15
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[67] bit 1 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 13	GTX_DUAL: DRP[67] bit 0 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 12
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 14 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 10	GTX_DUAL: DRP[66] bit 15 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 11
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 13 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 9	GTX_DUAL: DRP[66] bit 12 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 8
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 10 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 6	GTX_DUAL: DRP[66] bit 11 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 7
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 9 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 5	GTX_DUAL: DRP[66] bit 8 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 4
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 6 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 2	GTX_DUAL: DRP[66] bit 7 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 3
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 5 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 1	GTX_DUAL: DRP[66] bit 4 GTX_DUAL: PRBS_ERR_THRESHOLD_0 bit 0
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 2 GTX_DUAL: RX_DECODE_SEQ_MATCH_0	GTX_DUAL: DRP[66] bit 3 GTX_DUAL: RX_BUFFER_USE_0
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[66] bit 1 GTX_DUAL: RX_LOS_INVALID_INCR_0 bit 2	GTX_DUAL: DRP[66] bit 0 GTX_DUAL: RX_LOS_INVALID_INCR_0 bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 14 GTX_DUAL: RX_LOSS_OF_SYNC_FSM_0	GTX_DUAL: DRP[65] bit 15 GTX_DUAL: RX_LOS_INVALID_INCR_0 bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 13 GTX_DUAL: RX_LOS_THRESHOLD_0 bit 2	GTX_DUAL: DRP[65] bit 12 GTX_DUAL: RX_LOS_THRESHOLD_0 bit 1
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 10 GTX_DUAL: RX_SLIDE_MODE_0 bit 0	GTX_DUAL: DRP[65] bit 11 GTX_DUAL: RX_LOS_THRESHOLD_0 bit 0
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 9 GTX_DUAL: RX_STATUS_FMT_0 bit 0	GTX_DUAL: DRP[65] bit 8 GTX_DUAL: RX_XCLK_SEL_0 bit 0
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 6 GTX_DUAL: SATA_BURST_VAL_0 bit 1	GTX_DUAL: DRP[65] bit 7 GTX_DUAL: SATA_BURST_VAL_0 bit 2
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 5 GTX_DUAL: SATA_BURST_VAL_0 bit 0	GTX_DUAL: DRP[65] bit 4 GTX_DUAL: SATA_IDLE_VAL_0 bit 2
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 2 GTX_DUAL: SATA_IDLE_VAL_0 bit 0	GTX_DUAL: DRP[65] bit 3 GTX_DUAL: SATA_IDLE_VAL_0 bit 1
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[65] bit 1 GTX_DUAL: SATA_MAX_BURST_0 bit 5	GTX_DUAL: DRP[65] bit 0 GTX_DUAL: SATA_MAX_BURST_0 bit 4
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 14 GTX_DUAL: SATA_MAX_BURST_0 bit 2	GTX_DUAL: DRP[64] bit 15 GTX_DUAL: SATA_MAX_BURST_0 bit 3
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 13 GTX_DUAL: SATA_MAX_BURST_0 bit 1	GTX_DUAL: DRP[64] bit 12 GTX_DUAL: SATA_MAX_BURST_0 bit 0
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 10 GTX_DUAL: SATA_MAX_INIT_0 bit 4	GTX_DUAL: DRP[64] bit 11 GTX_DUAL: SATA_MAX_INIT_0 bit 5
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 9 GTX_DUAL: SATA_MAX_INIT_0 bit 3	GTX_DUAL: DRP[64] bit 8 GTX_DUAL: SATA_MAX_INIT_0 bit 2
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 6 GTX_DUAL: SATA_MAX_INIT_0 bit 0	GTX_DUAL: DRP[64] bit 7 GTX_DUAL: SATA_MAX_INIT_0 bit 1
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 5 GTX_DUAL: SATA_MAX_WAKE_0 bit 5	GTX_DUAL: DRP[64] bit 4 GTX_DUAL: SATA_MAX_WAKE_0 bit 4
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 2 GTX_DUAL: SATA_MAX_WAKE_0 bit 2	GTX_DUAL: DRP[64] bit 3 GTX_DUAL: SATA_MAX_WAKE_0 bit 3
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[64] bit 1 GTX_DUAL: SATA_MAX_WAKE_0 bit 1	GTX_DUAL: DRP[64] bit 0 GTX_DUAL: SATA_MAX_WAKE_0 bit 0

virtex5 GTX rect MAIN[14]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 14	GTX_DUAL: DRP[79] bit 15
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 13	GTX_DUAL: DRP[79] bit 12
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 10	GTX_DUAL: DRP[79] bit 11
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 9 GTX_DUAL: PMA_TX_CFG_0 bit 19	GTX_DUAL: DRP[79] bit 8 GTX_DUAL: PMA_TX_CFG_0 bit 18
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 6 GTX_DUAL: PMA_TX_CFG_0 bit 16	GTX_DUAL: DRP[79] bit 7 GTX_DUAL: PMA_TX_CFG_0 bit 17
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 5 GTX_DUAL: PMA_TX_CFG_0 bit 15	GTX_DUAL: DRP[79] bit 4 GTX_DUAL: PMA_TX_CFG_0 bit 14
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 2 GTX_DUAL: PMA_TX_CFG_0 bit 12	GTX_DUAL: DRP[79] bit 3 GTX_DUAL: PMA_TX_CFG_0 bit 13
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[79] bit 1 GTX_DUAL: PMA_TX_CFG_0 bit 11	GTX_DUAL: DRP[79] bit 0 GTX_DUAL: PMA_TX_CFG_0 bit 10
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 14 GTX_DUAL: PMA_TX_CFG_0 bit 8	GTX_DUAL: DRP[78] bit 15 GTX_DUAL: PMA_TX_CFG_0 bit 9
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 13 GTX_DUAL: PMA_TX_CFG_0 bit 7	GTX_DUAL: DRP[78] bit 12 GTX_DUAL: PMA_TX_CFG_0 bit 6
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 10 GTX_DUAL: PMA_TX_CFG_0 bit 4	GTX_DUAL: DRP[78] bit 11 GTX_DUAL: PMA_TX_CFG_0 bit 5
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 9 GTX_DUAL: PMA_TX_CFG_0 bit 3	GTX_DUAL: DRP[78] bit 8 GTX_DUAL: PMA_TX_CFG_0 bit 2
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 6 GTX_DUAL: PMA_TX_CFG_0 bit 0	GTX_DUAL: DRP[78] bit 7 GTX_DUAL: PMA_TX_CFG_0 bit 1
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 5 GTX_DUAL: CM_TRIM_0 bit 1	GTX_DUAL: DRP[78] bit 4 GTX_DUAL: CM_TRIM_0 bit 0
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 2 GTX_DUAL: DFE_CFG_0 bit 8	GTX_DUAL: DRP[78] bit 3 GTX_DUAL: DFE_CFG_0 bit 9
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[78] bit 1 GTX_DUAL: DFE_CFG_0 bit 7	GTX_DUAL: DRP[78] bit 0 GTX_DUAL: DFE_CFG_0 bit 6
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 14 GTX_DUAL: DFE_CFG_0 bit 4	GTX_DUAL: DRP[77] bit 15 GTX_DUAL: DFE_CFG_0 bit 5
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 13 GTX_DUAL: DFE_CFG_0 bit 3	GTX_DUAL: DRP[77] bit 12 GTX_DUAL: DFE_CFG_0 bit 2
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 10 GTX_DUAL: DFE_CFG_0 bit 0	GTX_DUAL: DRP[77] bit 11 GTX_DUAL: DFE_CFG_0 bit 1
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 9 GTX_DUAL: TXGEARBOX_USE_0	GTX_DUAL: DRP[77] bit 8 GTX_DUAL: RXGEARBOX_USE_0
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 6 GTX_DUAL: GEARBOX_ENDEC_0 bit 1	GTX_DUAL: DRP[77] bit 7 GTX_DUAL: GEARBOX_ENDEC_0 bit 2
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 5 GTX_DUAL: GEARBOX_ENDEC_0 bit 0	GTX_DUAL: DRP[77] bit 4 GTX_DUAL: CHAN_BOND_KEEP_ALIGN_0
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 2 GTX_DUAL: CB2_INH_CC_PERIOD_0 bit 2	GTX_DUAL: DRP[77] bit 3 GTX_DUAL: CB2_INH_CC_PERIOD_0 bit 3
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[77] bit 1 GTX_DUAL: CB2_INH_CC_PERIOD_0 bit 1	GTX_DUAL: DRP[77] bit 0 GTX_DUAL: CB2_INH_CC_PERIOD_0 bit 0
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 14 GTX_DUAL: RX_IDLE_LO_CNT_0 bit 2	GTX_DUAL: DRP[76] bit 15 GTX_DUAL: RX_IDLE_LO_CNT_0 bit 3
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 13 GTX_DUAL: RX_IDLE_LO_CNT_0 bit 1	GTX_DUAL: DRP[76] bit 12 GTX_DUAL: RX_IDLE_LO_CNT_0 bit 0
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 10	GTX_DUAL: DRP[76] bit 11
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 9 GTX_DUAL: RX_IDLE_HI_CNT_0 bit 3	GTX_DUAL: DRP[76] bit 8 GTX_DUAL: RX_IDLE_HI_CNT_0 bit 2
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 6 GTX_DUAL: RX_IDLE_HI_CNT_0 bit 0	GTX_DUAL: DRP[76] bit 7 GTX_DUAL: RX_IDLE_HI_CNT_0 bit 1
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 5	GTX_DUAL: DRP[76] bit 4
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 2	GTX_DUAL: DRP[76] bit 3 GTX_DUAL: RX_EN_IDLE_RESET_BUF_0
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[76] bit 1 GTX_DUAL: RX_EN_IDLE_HOLD_DFE_0	GTX_DUAL: DRP[76] bit 0
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 14 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 5	GTX_DUAL: DRP[75] bit 15 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 6
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 13 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 4	GTX_DUAL: DRP[75] bit 12 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 3
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 10 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 1	GTX_DUAL: DRP[75] bit 11 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 2
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 9 GTX_DUAL: PMA_RXSYNC_CFG_0 bit 0	GTX_DUAL: DRP[75] bit 8 GTX_DUAL: TX_IDLE_DELAY_0 bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 6 GTX_DUAL: TX_IDLE_DELAY_0 bit 0	GTX_DUAL: DRP[75] bit 7 GTX_DUAL: TX_IDLE_DELAY_0 bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 5	GTX_DUAL: DRP[75] bit 4
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 2	GTX_DUAL: DRP[75] bit 3
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[75] bit 1	GTX_DUAL: DRP[75] bit 0 GTX_DUAL: PLL_TDCC_CFG bit 2
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 14 GTX_DUAL: PLL_TDCC_CFG bit 1	GTX_DUAL: DRP[74] bit 15 GTX_DUAL: PLL_TDCC_CFG bit 0
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 13	GTX_DUAL: DRP[74] bit 12
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 10 GTX_DUAL: PLL_STARTUP_EN	GTX_DUAL: DRP[74] bit 11
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 9	GTX_DUAL: DRP[74] bit 8
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 6 GTX_DUAL: PMA_COM_CFG bit 31	GTX_DUAL: DRP[74] bit 7 GTX_DUAL: PMA_COM_CFG bit 20
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 5 GTX_DUAL: PMA_COM_CFG bit 30	GTX_DUAL: DRP[74] bit 4 GTX_DUAL: PMA_COM_CFG bit 29
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 2 GTX_DUAL: PMA_COM_CFG bit 27	GTX_DUAL: DRP[74] bit 3 GTX_DUAL: PMA_COM_CFG bit 28
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[74] bit 1 GTX_DUAL: RCV_TERM_VTTRX_0	GTX_DUAL: DRP[74] bit 0 GTX_DUAL: RCV_TERM_GND_0
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 14 GTX_DUAL: AC_CAP_DIS_0	GTX_DUAL: DRP[73] bit 15
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 13 GTX_DUAL: PMA_RX_CFG_1 bit 12	GTX_DUAL: DRP[73] bit 12 GTX_DUAL: PMA_RX_CFG_1 bit 24
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 10 GTX_DUAL: PMA_RX_CFG_1 bit 0	GTX_DUAL: DRP[73] bit 11 GTX_DUAL: PMA_RX_CFG_1 bit 1
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 9 GTX_DUAL: PMA_RX_CFG_1 bit 11	GTX_DUAL: DRP[73] bit 8 GTX_DUAL: PMA_RX_CFG_0 bit 22
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 6 GTX_DUAL: PMA_RX_CFG_0 bit 20	GTX_DUAL: DRP[73] bit 7 GTX_DUAL: PMA_RX_CFG_0 bit 21
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 5 GTX_DUAL: PMA_RX_CFG_0 bit 19	GTX_DUAL: DRP[73] bit 4 GTX_DUAL: PMA_RX_CFG_0 bit 18
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 2 GTX_DUAL: PMA_RX_CFG_0 bit 16	GTX_DUAL: DRP[73] bit 3 GTX_DUAL: PMA_RX_CFG_0 bit 17
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[73] bit 1 GTX_DUAL: PMA_RX_CFG_0 bit 15	GTX_DUAL: DRP[73] bit 0 GTX_DUAL: PMA_RX_CFG_0 bit 14
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 14 GTX_DUAL: RX_CDR_FORCE_ROTATE_0	GTX_DUAL: DRP[72] bit 15 GTX_DUAL: PMA_RX_CFG_0 bit 13
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 13 GTX_DUAL: PMA_RX_CFG_0 bit 5	GTX_DUAL: DRP[72] bit 12 GTX_DUAL: PMA_RX_CFG_0 bit 4
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 10 GTX_DUAL: PMA_RX_CFG_0 bit 2	GTX_DUAL: DRP[72] bit 11 GTX_DUAL: PMA_RX_CFG_0 bit 3
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 9 GTX_DUAL: PMA_RX_CFG_1 bit 23	GTX_DUAL: DRP[72] bit 8 GTX_DUAL: PMA_RX_CFG_0 bit 10
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 6 GTX_DUAL: PMA_RX_CFG_0 bit 8	GTX_DUAL: DRP[72] bit 7 GTX_DUAL: PMA_RX_CFG_0 bit 9
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 5 GTX_DUAL: PMA_RX_CFG_0 bit 7	GTX_DUAL: DRP[72] bit 4 GTX_DUAL: PMA_RX_CFG_0 bit 6
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 2 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 1	GTX_DUAL: DRP[72] bit 3 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 0
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: DRP[72] bit 1 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 2	GTX_DUAL: DRP[72] bit 0 GTX_DUAL: CHAN_BOND_SEQ_2_4_0 bit 3

virtex5 GTX rect MAIN[15]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[16]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 11	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 10	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 9	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 8	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 7	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 6	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 5	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 4	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 3	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 2	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 1	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 0	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[17]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: ENABLE64	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 31	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 30	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 29	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 28	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 27	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 26	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 25	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 24	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 23	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 22	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 21	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 20	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 19	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 18	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 17	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 16	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 15	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 14	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 13	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: CRC_INIT bit 12	-	-

virtex5 GTX rect MAIN[18]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect MAIN[19]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX rect HCLK
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: USRCLK_ENABLE_0	CRC32[0]: !invert CRCCLK	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[3]: !invert CRCCLK	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32[2]: !invert CRCCLK	GTX_DUAL: invert DCLK	GTX_DUAL: invert TXUSRCLK1	GTX_DUAL: invert RXUSRCLK1	GTX_DUAL: invert RXUSRCLK20	GTX_DUAL: invert TXUSRCLK20	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL: USRCLK_ENABLE_1	CRC32[1]: !invert CRCCLK	GTX_DUAL: invert TXUSRCLK21	GTX_DUAL: invert RXUSRCLK21	GTX_DUAL: invert RXUSRCLK0	GTX_DUAL: invert TXUSRCLK0	-	-	-	-	GTX_DUAL: DRP_MASK	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

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