GTX transceivers

TODO: document

Tile GTX

Cells: 20 IRIs: 0

Bel GTX_DUAL

virtex5 GTX bel GTX_DUAL
Pin	Direction	Wires
DADDR0	input	TCELL10:IMUX.IMUX32
DADDR1	input	TCELL10:IMUX.IMUX31
DADDR2	input	TCELL10:IMUX.IMUX24
DADDR3	input	TCELL9:IMUX.IMUX29
DADDR4	input	TCELL9:IMUX.IMUX28
DADDR5	input	TCELL9:IMUX.IMUX27
DADDR6	input	TCELL9:IMUX.IMUX26
DCLK	input	TCELL7:IMUX.CLK1
DEN	input	TCELL10:IMUX.IMUX39
DFECLKDLYADJ00	input	TCELL14:IMUX.IMUX23
DFECLKDLYADJ01	input	TCELL15:IMUX.IMUX36
DFECLKDLYADJ02	input	TCELL15:IMUX.IMUX19
DFECLKDLYADJ03	input	TCELL15:IMUX.IMUX38
DFECLKDLYADJ04	input	TCELL15:IMUX.IMUX39
DFECLKDLYADJ05	input	TCELL15:IMUX.IMUX40
DFECLKDLYADJ10	input	TCELL5:IMUX.IMUX24
DFECLKDLYADJ11	input	TCELL4:IMUX.IMUX29
DFECLKDLYADJ12	input	TCELL4:IMUX.IMUX34
DFECLKDLYADJ13	input	TCELL4:IMUX.IMUX27
DFECLKDLYADJ14	input	TCELL4:IMUX.IMUX32
DFECLKDLYADJ15	input	TCELL4:IMUX.IMUX31
DFECLKDLYADJMONITOR00	output	TCELL15:OUT4
DFECLKDLYADJMONITOR01	output	TCELL15:OUT0
DFECLKDLYADJMONITOR02	output	TCELL15:OUT19
DFECLKDLYADJMONITOR03	output	TCELL15:OUT16
DFECLKDLYADJMONITOR04	output	TCELL15:OUT6
DFECLKDLYADJMONITOR05	output	TCELL15:OUT15
DFECLKDLYADJMONITOR10	output	TCELL4:OUT15
DFECLKDLYADJMONITOR11	output	TCELL4:OUT7
DFECLKDLYADJMONITOR12	output	TCELL4:OUT3
DFECLKDLYADJMONITOR13	output	TCELL4:OUT14
DFECLKDLYADJMONITOR14	output	TCELL4:OUT13
DFECLKDLYADJMONITOR15	output	TCELL4:OUT1
DFEEYEDACMONITOR00	output	TCELL14:OUT0
DFEEYEDACMONITOR01	output	TCELL14:OUT19
DFEEYEDACMONITOR02	output	TCELL14:OUT16
DFEEYEDACMONITOR03	output	TCELL14:OUT2
DFEEYEDACMONITOR04	output	TCELL15:OUT8
DFEEYEDACMONITOR10	output	TCELL6:OUT18
DFEEYEDACMONITOR11	output	TCELL5:OUT15
DFEEYEDACMONITOR12	output	TCELL5:OUT14
DFEEYEDACMONITOR13	output	TCELL5:OUT13
DFEEYEDACMONITOR14	output	TCELL5:OUT12
DFESENSCAL00	output	TCELL10:OUT18
DFESENSCAL01	output	TCELL10:OUT19
DFESENSCAL02	output	TCELL10:OUT17
DFESENSCAL10	output	TCELL9:OUT7
DFESENSCAL11	output	TCELL9:OUT9
DFESENSCAL12	output	TCELL9:OUT22
DFETAP100	input	TCELL14:IMUX.IMUX31
DFETAP101	input	TCELL14:IMUX.IMUX26
DFETAP102	input	TCELL14:IMUX.IMUX33
DFETAP103	input	TCELL14:IMUX.IMUX34
DFETAP104	input	TCELL14:IMUX.IMUX35
DFETAP110	input	TCELL5:IMUX.IMUX28
DFETAP111	input	TCELL5:IMUX.IMUX33
DFETAP112	input	TCELL5:IMUX.IMUX26
DFETAP113	input	TCELL5:IMUX.IMUX25
DFETAP114	input	TCELL5:IMUX.IMUX12
DFETAP1MONITOR00	output	TCELL13:OUT8
DFETAP1MONITOR01	output	TCELL13:OUT0
DFETAP1MONITOR02	output	TCELL13:OUT16
DFETAP1MONITOR03	output	TCELL13:OUT6
DFETAP1MONITOR04	output	TCELL13:OUT15
DFETAP1MONITOR10	output	TCELL7:OUT22
DFETAP1MONITOR11	output	TCELL6:OUT21
DFETAP1MONITOR12	output	TCELL6:OUT7
DFETAP1MONITOR13	output	TCELL6:OUT23
DFETAP1MONITOR14	output	TCELL6:OUT5
DFETAP200	input	TCELL14:IMUX.IMUX12
DFETAP201	input	TCELL14:IMUX.IMUX36
DFETAP202	input	TCELL14:IMUX.IMUX37
DFETAP203	input	TCELL14:IMUX.IMUX38
DFETAP204	input	TCELL14:IMUX.IMUX39
DFETAP210	input	TCELL5:IMUX.IMUX29
DFETAP211	input	TCELL5:IMUX.IMUX11
DFETAP212	input	TCELL5:IMUX.IMUX22
DFETAP213	input	TCELL5:IMUX.IMUX27
DFETAP214	input	TCELL5:IMUX.IMUX20
DFETAP2MONITOR00	output	TCELL12:OUT12
DFETAP2MONITOR01	output	TCELL12:OUT19
DFETAP2MONITOR02	output	TCELL12:OUT16
DFETAP2MONITOR03	output	TCELL12:OUT2
DFETAP2MONITOR04	output	TCELL12:OUT6
DFETAP2MONITOR10	output	TCELL8:OUT22
DFETAP2MONITOR11	output	TCELL7:OUT16
DFETAP2MONITOR12	output	TCELL7:OUT14
DFETAP2MONITOR13	output	TCELL7:OUT13
DFETAP2MONITOR14	output	TCELL7:OUT1
DFETAP300	input	TCELL13:IMUX.IMUX25
DFETAP301	input	TCELL13:IMUX.IMUX26
DFETAP302	input	TCELL13:IMUX.IMUX27
DFETAP303	input	TCELL13:IMUX.IMUX28
DFETAP310	input	TCELL6:IMUX.IMUX34
DFETAP311	input	TCELL6:IMUX.IMUX39
DFETAP312	input	TCELL6:IMUX.IMUX32
DFETAP313	input	TCELL6:IMUX.IMUX31
DFETAP3MONITOR00	output	TCELL11:OUT8
DFETAP3MONITOR01	output	TCELL11:OUT18
DFETAP3MONITOR02	output	TCELL11:OUT1
DFETAP3MONITOR03	output	TCELL11:OUT11
DFETAP3MONITOR10	output	TCELL8:OUT21
DFETAP3MONITOR11	output	TCELL8:OUT7
DFETAP3MONITOR12	output	TCELL8:OUT20
DFETAP3MONITOR13	output	TCELL8:OUT4
DFETAP400	input	TCELL12:IMUX.IMUX37
DFETAP401	input	TCELL12:IMUX.IMUX40
DFETAP402	input	TCELL12:IMUX.IMUX41
DFETAP403	input	TCELL13:IMUX.IMUX36
DFETAP410	input	TCELL7:IMUX.IMUX28
DFETAP411	input	TCELL7:IMUX.IMUX25
DFETAP412	input	TCELL7:IMUX.IMUX24
DFETAP413	input	TCELL6:IMUX.IMUX11
DFETAP4MONITOR00	output	TCELL10:OUT1
DFETAP4MONITOR01	output	TCELL10:OUT14
DFETAP4MONITOR02	output	TCELL10:OUT20
DFETAP4MONITOR03	output	TCELL10:OUT3
DFETAP4MONITOR10	output	TCELL9:OUT17
DFETAP4MONITOR11	output	TCELL9:OUT16
DFETAP4MONITOR12	output	TCELL9:OUT19
DFETAP4MONITOR13	output	TCELL9:OUT5
DI0	input	TCELL11:IMUX.IMUX3
DI1	input	TCELL11:IMUX.IMUX2
DI10	input	TCELL9:IMUX.IMUX43
DI11	input	TCELL9:IMUX.IMUX42
DI12	input	TCELL8:IMUX.IMUX47
DI13	input	TCELL8:IMUX.IMUX46
DI14	input	TCELL8:IMUX.IMUX45
DI15	input	TCELL8:IMUX.IMUX44
DI2	input	TCELL11:IMUX.IMUX1
DI3	input	TCELL11:IMUX.IMUX0
DI4	input	TCELL10:IMUX.IMUX3
DI5	input	TCELL10:IMUX.IMUX2
DI6	input	TCELL10:IMUX.IMUX1
DI7	input	TCELL10:IMUX.IMUX0
DI8	input	TCELL9:IMUX.IMUX45
DI9	input	TCELL9:IMUX.IMUX44
DO0	output	TCELL11:OUT21
DO1	output	TCELL11:OUT17
DO10	output	TCELL9:OUT20
DO11	output	TCELL9:OUT10
DO12	output	TCELL8:OUT13
DO13	output	TCELL8:OUT18
DO14	output	TCELL8:OUT12
DO15	output	TCELL8:OUT8
DO2	output	TCELL11:OUT15
DO3	output	TCELL11:OUT14
DO4	output	TCELL10:OUT10
DO5	output	TCELL10:OUT9
DO6	output	TCELL10:OUT0
DO7	output	TCELL10:OUT12
DO8	output	TCELL9:OUT21
DO9	output	TCELL9:OUT6
DRDY	output	TCELL9:OUT15
DWE	input	TCELL9:IMUX.IMUX19
GREFCLK	input	TCELL12:IMUX.CLK0
GTXRESET	input	TCELL11:IMUX.IMUX36
GTXTEST0	input	TCELL19:IMUX.IMUX27
GTXTEST1	input	TCELL0:IMUX.IMUX13
GTXTEST10	input	TCELL0:IMUX.IMUX12
GTXTEST11	input	TCELL0:IMUX.IMUX11
GTXTEST12	input	TCELL0:IMUX.IMUX14
GTXTEST13	input	TCELL10:IMUX.IMUX33
GTXTEST2	input	TCELL9:IMUX.IMUX16
GTXTEST3	input	TCELL9:IMUX.IMUX17
GTXTEST4	input	TCELL14:IMUX.IMUX22
GTXTEST5	input	TCELL19:IMUX.IMUX28
GTXTEST6	input	TCELL19:IMUX.IMUX6
GTXTEST7	input	TCELL19:IMUX.IMUX29
GTXTEST8	input	TCELL10:IMUX.IMUX40
GTXTEST9	input	TCELL5:IMUX.IMUX13
INTDATAWIDTH	input	TCELL10:IMUX.IMUX6
LOOPBACK00	input	TCELL12:IMUX.IMUX15
LOOPBACK01	input	TCELL12:IMUX.IMUX16
LOOPBACK02	input	TCELL12:IMUX.IMUX17
LOOPBACK10	input	TCELL7:IMUX.IMUX20
LOOPBACK11	input	TCELL7:IMUX.IMUX19
LOOPBACK12	input	TCELL7:IMUX.IMUX18
PHYSTATUS0	output	TCELL15:OUT12
PHYSTATUS1	output	TCELL4:OUT17
PLLLKDET	output	TCELL9:OUT23
PLLLKDETEN	input	TCELL9:IMUX.IMUX8
PLLPOWERDOWN	input	TCELL10:IMUX.IMUX36
PMAAMUX0	input	TCELL9:IMUX.IMUX3
PMAAMUX1	input	TCELL9:IMUX.IMUX4
PMAAMUX2	input	TCELL9:IMUX.IMUX5
PMATSTCLK	output	TCELL10:OUT22
PMATSTCLKSEL0	input	TCELL10:IMUX.IMUX14
PMATSTCLKSEL1	input	TCELL10:IMUX.IMUX13
PMATSTCLKSEL2	input	TCELL10:IMUX.IMUX12
PRBSCNTRESET0	input	TCELL11:IMUX.IMUX45
PRBSCNTRESET1	input	TCELL8:IMUX.IMUX2
REFCLKOUT	output	TCELL10:OUT8
REFCLKPWRDNB	input	TCELL9:IMUX.IMUX18
RESETDONE0	output	TCELL15:OUT7
RESETDONE1	output	TCELL4:OUT0
RXBUFRESET0	input	TCELL12:IMUX.IMUX43
RXBUFRESET1	input	TCELL7:IMUX.IMUX4
RXBUFSTATUS00	output	TCELL15:OUT1
RXBUFSTATUS01	output	TCELL15:OUT13
RXBUFSTATUS02	output	TCELL15:OUT14
RXBUFSTATUS10	output	TCELL4:OUT6
RXBUFSTATUS11	output	TCELL4:OUT16
RXBUFSTATUS12	output	TCELL4:OUT19
RXBYTEISALIGNED0	output	TCELL14:OUT7
RXBYTEISALIGNED1	output	TCELL5:OUT0
RXBYTEREALIGN0	output	TCELL14:OUT15
RXBYTEREALIGN1	output	TCELL5:OUT18
RXCDRRESET0	input	TCELL12:IMUX.IMUX47
RXCDRRESET1	input	TCELL7:IMUX.IMUX0
RXCHANBONDSEQ0	output	TCELL12:OUT1
RXCHANBONDSEQ1	output	TCELL7:OUT6
RXCHANISALIGNED0	output	TCELL12:OUT15
RXCHANISALIGNED1	output	TCELL7:OUT18
RXCHANREALIGN0	output	TCELL12:OUT3
RXCHANREALIGN1	output	TCELL7:OUT4
RXCHARISCOMMA00	output	TCELL14:OUT12
RXCHARISCOMMA01	output	TCELL13:OUT12
RXCHARISCOMMA02	output	TCELL16:OUT1
RXCHARISCOMMA03	output	TCELL17:OUT21
RXCHARISCOMMA10	output	TCELL5:OUT17
RXCHARISCOMMA11	output	TCELL6:OUT17
RXCHARISCOMMA12	output	TCELL3:OUT7
RXCHARISCOMMA13	output	TCELL2:OUT3
RXCHARISK00	output	TCELL14:OUT13
RXCHARISK01	output	TCELL13:OUT13
RXCHARISK02	output	TCELL17:OUT12
RXCHARISK03	output	TCELL18:OUT18
RXCHARISK10	output	TCELL5:OUT16
RXCHARISK11	output	TCELL6:OUT16
RXCHARISK12	output	TCELL3:OUT12
RXCHARISK13	output	TCELL1:OUT21
RXCHBONDI00	input	TCELL13:IMUX.IMUX44
RXCHBONDI01	input	TCELL13:IMUX.IMUX45
RXCHBONDI02	input	TCELL13:IMUX.IMUX46
RXCHBONDI03	input	TCELL13:IMUX.IMUX43
RXCHBONDI10	input	TCELL6:IMUX.IMUX3
RXCHBONDI11	input	TCELL6:IMUX.IMUX2
RXCHBONDI12	input	TCELL6:IMUX.IMUX1
RXCHBONDI13	input	TCELL6:IMUX.IMUX23
RXCHBONDO00	output	TCELL12:OUT14
RXCHBONDO01	output	TCELL12:OUT7
RXCHBONDO02	output	TCELL12:OUT21
RXCHBONDO03	output	TCELL12:OUT11
RXCHBONDO10	output	TCELL7:OUT19
RXCHBONDO11	output	TCELL7:OUT0
RXCHBONDO12	output	TCELL7:OUT8
RXCHBONDO13	output	TCELL7:OUT5
RXCLKCORCNT00	output	TCELL16:OUT5
RXCLKCORCNT01	output	TCELL16:OUT23
RXCLKCORCNT02	output	TCELL16:OUT20
RXCLKCORCNT10	output	TCELL3:OUT2
RXCLKCORCNT11	output	TCELL3:OUT10
RXCLKCORCNT12	output	TCELL3:OUT9
RXCOMMADET0	output	TCELL14:OUT21
RXCOMMADET1	output	TCELL5:OUT8
RXCOMMADETUSE0	input	TCELL15:IMUX.IMUX30
RXCOMMADETUSE1	input	TCELL4:IMUX.IMUX17
RXDATA00	output	TCELL15:OUT20
RXDATA01	output	TCELL15:OUT23
RXDATA010	output	TCELL13:OUT5
RXDATA011	output	TCELL13:OUT22
RXDATA012	output	TCELL12:OUT20
RXDATA013	output	TCELL12:OUT23
RXDATA014	output	TCELL12:OUT5
RXDATA015	output	TCELL12:OUT22
RXDATA016	output	TCELL15:OUT17
RXDATA017	output	TCELL15:OUT21
RXDATA018	output	TCELL16:OUT12
RXDATA019	output	TCELL16:OUT16
RXDATA02	output	TCELL15:OUT5
RXDATA020	output	TCELL16:OUT2
RXDATA021	output	TCELL16:OUT6
RXDATA022	output	TCELL16:OUT11
RXDATA023	output	TCELL16:OUT17
RXDATA024	output	TCELL17:OUT9
RXDATA025	output	TCELL17:OUT23
RXDATA026	output	TCELL17:OUT10
RXDATA027	output	TCELL17:OUT16
RXDATA028	output	TCELL18:OUT19
RXDATA029	output	TCELL18:OUT16
RXDATA03	output	TCELL15:OUT22
RXDATA030	output	TCELL18:OUT20
RXDATA031	output	TCELL18:OUT11
RXDATA04	output	TCELL14:OUT20
RXDATA05	output	TCELL14:OUT23
RXDATA06	output	TCELL14:OUT5
RXDATA07	output	TCELL14:OUT22
RXDATA08	output	TCELL13:OUT20
RXDATA09	output	TCELL13:OUT23
RXDATA10	output	TCELL4:OUT9
RXDATA11	output	TCELL4:OUT10
RXDATA110	output	TCELL6:OUT2
RXDATA111	output	TCELL6:OUT11
RXDATA112	output	TCELL7:OUT9
RXDATA113	output	TCELL7:OUT10
RXDATA114	output	TCELL7:OUT2
RXDATA115	output	TCELL7:OUT11
RXDATA116	output	TCELL4:OUT22
RXDATA117	output	TCELL4:OUT18
RXDATA118	output	TCELL4:OUT12
RXDATA119	output	TCELL3:OUT16
RXDATA12	output	TCELL4:OUT2
RXDATA120	output	TCELL3:OUT14
RXDATA121	output	TCELL3:OUT23
RXDATA122	output	TCELL3:OUT5
RXDATA123	output	TCELL3:OUT22
RXDATA124	output	TCELL2:OUT11
RXDATA125	output	TCELL2:OUT7
RXDATA126	output	TCELL2:OUT16
RXDATA127	output	TCELL2:OUT19
RXDATA128	output	TCELL1:OUT6
RXDATA129	output	TCELL1:OUT20
RXDATA13	output	TCELL4:OUT11
RXDATA130	output	TCELL1:OUT9
RXDATA131	output	TCELL1:OUT4
RXDATA14	output	TCELL5:OUT9
RXDATA15	output	TCELL5:OUT10
RXDATA16	output	TCELL5:OUT2
RXDATA17	output	TCELL5:OUT11
RXDATA18	output	TCELL6:OUT9
RXDATA19	output	TCELL6:OUT10
RXDATAVALID0	output	TCELL19:OUT23
RXDATAVALID1	output	TCELL0:OUT12
RXDATAWIDTH00	input	TCELL15:IMUX.IMUX37
RXDATAWIDTH01	input	TCELL15:IMUX.IMUX18
RXDATAWIDTH10	input	TCELL4:IMUX.IMUX10
RXDATAWIDTH11	input	TCELL4:IMUX.IMUX15
RXDEC8B10BUSE0	input	TCELL13:IMUX.IMUX41
RXDEC8B10BUSE1	input	TCELL6:IMUX.IMUX6
RXDISPERR00	output	TCELL14:OUT14
RXDISPERR01	output	TCELL13:OUT14
RXDISPERR02	output	TCELL17:OUT4
RXDISPERR03	output	TCELL18:OUT4
RXDISPERR10	output	TCELL5:OUT19
RXDISPERR11	output	TCELL6:OUT19
RXDISPERR12	output	TCELL2:OUT17
RXDISPERR13	output	TCELL1:OUT15
RXELECIDLE0	output	TCELL17:OUT5
RXELECIDLE1	output	TCELL2:OUT2
RXENCHANSYNC0	input	TCELL13:IMUX.IMUX23
RXENCHANSYNC1	input	TCELL6:IMUX.IMUX24
RXENEQB0	input	TCELL15:IMUX.IMUX42
RXENEQB1	input	TCELL4:IMUX.IMUX5
RXENMCOMMAALIGN0	input	TCELL15:IMUX.IMUX45
RXENMCOMMAALIGN1	input	TCELL4:IMUX.IMUX2
RXENPCOMMAALIGN0	input	TCELL15:IMUX.IMUX46
RXENPCOMMAALIGN1	input	TCELL4:IMUX.IMUX1
RXENPMAPHASEALIGN0	input	TCELL12:IMUX.IMUX13
RXENPMAPHASEALIGN1	input	TCELL7:IMUX.IMUX34
RXENPRBSTST00	input	TCELL15:IMUX.IMUX28
RXENPRBSTST01	input	TCELL15:IMUX.IMUX29
RXENPRBSTST10	input	TCELL4:IMUX.IMUX25
RXENPRBSTST11	input	TCELL4:IMUX.IMUX24
RXENSAMPLEALIGN0	input	TCELL15:IMUX.IMUX14
RXENSAMPLEALIGN1	input	TCELL4:IMUX.IMUX33
RXEQMIX00	input	TCELL14:IMUX.IMUX46
RXEQMIX01	input	TCELL14:IMUX.IMUX47
RXEQMIX10	input	TCELL5:IMUX.IMUX1
RXEQMIX11	input	TCELL5:IMUX.IMUX0
RXEQPOLE00	input	TCELL14:IMUX.IMUX42
RXEQPOLE01	input	TCELL14:IMUX.IMUX43
RXEQPOLE02	input	TCELL14:IMUX.IMUX44
RXEQPOLE03	input	TCELL14:IMUX.IMUX45
RXEQPOLE10	input	TCELL5:IMUX.IMUX5
RXEQPOLE11	input	TCELL5:IMUX.IMUX4
RXEQPOLE12	input	TCELL5:IMUX.IMUX3
RXEQPOLE13	input	TCELL5:IMUX.IMUX2
RXGEARBOXSLIP0	input	TCELL15:IMUX.IMUX17
RXGEARBOXSLIP1	input	TCELL4:IMUX.IMUX22
RXHEADER00	output	TCELL19:OUT22
RXHEADER01	output	TCELL19:OUT0
RXHEADER02	output	TCELL19:OUT9
RXHEADER10	output	TCELL0:OUT17
RXHEADER11	output	TCELL0:OUT6
RXHEADER12	output	TCELL0:OUT16
RXHEADERVALID0	output	TCELL19:OUT8
RXHEADERVALID1	output	TCELL0:OUT11
RXLOSSOFSYNC00	output	TCELL13:OUT11
RXLOSSOFSYNC01	output	TCELL13:OUT21
RXLOSSOFSYNC10	output	TCELL6:OUT22
RXLOSSOFSYNC11	output	TCELL6:OUT8
RXNOTINTABLE00	output	TCELL14:OUT3
RXNOTINTABLE01	output	TCELL13:OUT3
RXNOTINTABLE02	output	TCELL16:OUT0
RXNOTINTABLE03	output	TCELL17:OUT7
RXNOTINTABLE10	output	TCELL5:OUT4
RXNOTINTABLE11	output	TCELL6:OUT4
RXNOTINTABLE12	output	TCELL3:OUT17
RXNOTINTABLE13	output	TCELL2:OUT4
RXOVERSAMPLEERR0	output	TCELL15:OUT3
RXOVERSAMPLEERR1	output	TCELL4:OUT4
RXPMASETPHASE0	input	TCELL12:IMUX.IMUX7
RXPMASETPHASE1	input	TCELL7:IMUX.IMUX40
RXPOLARITY0	input	TCELL15:IMUX.IMUX41
RXPOLARITY1	input	TCELL4:IMUX.IMUX0
RXPOWERDOWN00	input	TCELL12:IMUX.IMUX38
RXPOWERDOWN01	input	TCELL12:IMUX.IMUX39
RXPOWERDOWN10	input	TCELL7:IMUX.IMUX9
RXPOWERDOWN11	input	TCELL7:IMUX.IMUX8
RXPRBSERR0	output	TCELL16:OUT22
RXPRBSERR1	output	TCELL3:OUT11
RXRECCLK0	output	TCELL12:OUT13
RXRECCLK1	output	TCELL7:OUT20
RXRESET0	input	TCELL12:IMUX.IMUX42
RXRESET1	input	TCELL7:IMUX.IMUX5
RXRUNDISP00	output	TCELL14:OUT1
RXRUNDISP01	output	TCELL13:OUT1
RXRUNDISP02	output	TCELL16:OUT19
RXRUNDISP03	output	TCELL18:OUT8
RXRUNDISP10	output	TCELL5:OUT6
RXRUNDISP11	output	TCELL6:OUT6
RXRUNDISP12	output	TCELL3:OUT20
RXRUNDISP13	output	TCELL2:OUT18
RXSLIDE0	input	TCELL15:IMUX.IMUX44
RXSLIDE1	input	TCELL4:IMUX.IMUX3
RXSTARTOFSEQ0	output	TCELL19:OUT18
RXSTARTOFSEQ1	output	TCELL0:OUT2
RXSTATUS00	output	TCELL16:OUT14
RXSTATUS01	output	TCELL16:OUT7
RXSTATUS02	output	TCELL16:OUT21
RXSTATUS10	output	TCELL3:OUT19
RXSTATUS11	output	TCELL3:OUT0
RXSTATUS12	output	TCELL3:OUT8
RXUSRCLK0	input	TCELL10:IMUX.CLK0
RXUSRCLK1	input	TCELL9:IMUX.CLK1
RXUSRCLK20	input	TCELL10:IMUX.CLK1
RXUSRCLK21	input	TCELL9:IMUX.CLK0
RXVALID0	output	TCELL13:OUT7
RXVALID1	output	TCELL6:OUT0
SCANEN	input	TCELL19:IMUX.IMUX17
SCANINPCS0	input	TCELL19:IMUX.IMUX47
SCANINPCS1	input	TCELL0:IMUX.IMUX30
SCANINPCSCOMMON	input	TCELL11:IMUX.IMUX29
SCANMODE	input	TCELL0:IMUX.IMUX36
SCANOUTPCS0	output	TCELL12:OUT10
SCANOUTPCS1	output	TCELL7:OUT7
SCANOUTPCSCOMMON	output	TCELL8:OUT1
TSTPWRDN00	input	TCELL13:IMUX.IMUX31
TSTPWRDN01	input	TCELL13:IMUX.IMUX32
TSTPWRDN02	input	TCELL13:IMUX.IMUX33
TSTPWRDN03	input	TCELL13:IMUX.IMUX34
TSTPWRDN04	input	TCELL13:IMUX.IMUX35
TSTPWRDN10	input	TCELL6:IMUX.IMUX16
TSTPWRDN11	input	TCELL6:IMUX.IMUX15
TSTPWRDN12	input	TCELL6:IMUX.IMUX14
TSTPWRDN13	input	TCELL6:IMUX.IMUX13
TSTPWRDN14	input	TCELL6:IMUX.IMUX12
TSTPWRDNOVRD0	input	TCELL18:IMUX.IMUX30
TSTPWRDNOVRD1	input	TCELL1:IMUX.IMUX47
TXBUFDIFFCTRL00	input	TCELL19:IMUX.IMUX30
TXBUFDIFFCTRL01	input	TCELL19:IMUX.IMUX31
TXBUFDIFFCTRL02	input	TCELL19:IMUX.IMUX32
TXBUFDIFFCTRL10	input	TCELL0:IMUX.IMUX17
TXBUFDIFFCTRL11	input	TCELL0:IMUX.IMUX16
TXBUFDIFFCTRL12	input	TCELL0:IMUX.IMUX15
TXBUFSTATUS00	output	TCELL18:OUT0
TXBUFSTATUS01	output	TCELL18:OUT23
TXBUFSTATUS10	output	TCELL1:OUT2
TXBUFSTATUS11	output	TCELL1:OUT10
TXBYPASS8B10B00	input	TCELL18:IMUX.IMUX29
TXBYPASS8B10B01	input	TCELL17:IMUX.IMUX29
TXBYPASS8B10B02	input	TCELL15:IMUX.IMUX27
TXBYPASS8B10B03	input	TCELL15:IMUX.IMUX21
TXBYPASS8B10B10	input	TCELL1:IMUX.IMUX12
TXBYPASS8B10B11	input	TCELL2:IMUX.IMUX24
TXBYPASS8B10B12	input	TCELL4:IMUX.IMUX20
TXBYPASS8B10B13	input	TCELL4:IMUX.IMUX14
TXCHARDISPMODE00	input	TCELL18:IMUX.IMUX27
TXCHARDISPMODE01	input	TCELL17:IMUX.IMUX27
TXCHARDISPMODE02	input	TCELL19:IMUX.IMUX15
TXCHARDISPMODE03	input	TCELL17:IMUX.IMUX7
TXCHARDISPMODE10	input	TCELL1:IMUX.IMUX8
TXCHARDISPMODE11	input	TCELL2:IMUX.IMUX20
TXCHARDISPMODE12	input	TCELL0:IMUX.IMUX38
TXCHARDISPMODE13	input	TCELL2:IMUX.IMUX40
TXCHARDISPVAL00	input	TCELL18:IMUX.IMUX26
TXCHARDISPVAL01	input	TCELL17:IMUX.IMUX26
TXCHARDISPVAL02	input	TCELL19:IMUX.IMUX2
TXCHARDISPVAL03	input	TCELL17:IMUX.IMUX25
TXCHARDISPVAL10	input	TCELL1:IMUX.IMUX21
TXCHARDISPVAL11	input	TCELL2:IMUX.IMUX21
TXCHARDISPVAL12	input	TCELL0:IMUX.IMUX9
TXCHARDISPVAL13	input	TCELL2:IMUX.IMUX28
TXCHARISK00	input	TCELL18:IMUX.IMUX46
TXCHARISK01	input	TCELL17:IMUX.IMUX28
TXCHARISK02	input	TCELL18:IMUX.IMUX28
TXCHARISK03	input	TCELL17:IMUX.IMUX8
TXCHARISK10	input	TCELL1:IMUX.IMUX1
TXCHARISK11	input	TCELL2:IMUX.IMUX25
TXCHARISK12	input	TCELL1:IMUX.IMUX13
TXCHARISK13	input	TCELL2:IMUX.IMUX39
TXCOMSTART0	input	TCELL18:IMUX.IMUX4
TXCOMSTART1	input	TCELL1:IMUX.IMUX37
TXCOMTYPE0	input	TCELL18:IMUX.IMUX5
TXCOMTYPE1	input	TCELL1:IMUX.IMUX0
TXDATA00	input	TCELL19:IMUX.IMUX45
TXDATA01	input	TCELL19:IMUX.IMUX44
TXDATA010	input	TCELL17:IMUX.IMUX43
TXDATA011	input	TCELL17:IMUX.IMUX42
TXDATA012	input	TCELL16:IMUX.IMUX45
TXDATA013	input	TCELL16:IMUX.IMUX44
TXDATA014	input	TCELL16:IMUX.IMUX43
TXDATA015	input	TCELL16:IMUX.IMUX42
TXDATA016	input	TCELL19:IMUX.IMUX23
TXDATA017	input	TCELL19:IMUX.IMUX22
TXDATA018	input	TCELL19:IMUX.IMUX20
TXDATA019	input	TCELL19:IMUX.IMUX12
TXDATA02	input	TCELL19:IMUX.IMUX43
TXDATA020	input	TCELL18:IMUX.IMUX35
TXDATA021	input	TCELL18:IMUX.IMUX33
TXDATA022	input	TCELL18:IMUX.IMUX32
TXDATA023	input	TCELL18:IMUX.IMUX31
TXDATA024	input	TCELL17:IMUX.IMUX23
TXDATA025	input	TCELL17:IMUX.IMUX22
TXDATA026	input	TCELL17:IMUX.IMUX21
TXDATA027	input	TCELL17:IMUX.IMUX20
TXDATA028	input	TCELL16:IMUX.IMUX23
TXDATA029	input	TCELL16:IMUX.IMUX22
TXDATA03	input	TCELL19:IMUX.IMUX42
TXDATA030	input	TCELL16:IMUX.IMUX21
TXDATA031	input	TCELL16:IMUX.IMUX20
TXDATA04	input	TCELL18:IMUX.IMUX45
TXDATA05	input	TCELL18:IMUX.IMUX44
TXDATA06	input	TCELL18:IMUX.IMUX43
TXDATA07	input	TCELL18:IMUX.IMUX42
TXDATA08	input	TCELL17:IMUX.IMUX45
TXDATA09	input	TCELL17:IMUX.IMUX44
TXDATA10	input	TCELL0:IMUX.IMUX32
TXDATA11	input	TCELL0:IMUX.IMUX33
TXDATA110	input	TCELL2:IMUX.IMUX34
TXDATA111	input	TCELL2:IMUX.IMUX35
TXDATA112	input	TCELL3:IMUX.IMUX32
TXDATA113	input	TCELL3:IMUX.IMUX33
TXDATA114	input	TCELL3:IMUX.IMUX34
TXDATA115	input	TCELL3:IMUX.IMUX35
TXDATA116	input	TCELL0:IMUX.IMUX0
TXDATA117	input	TCELL0:IMUX.IMUX31
TXDATA118	input	TCELL0:IMUX.IMUX27
TXDATA119	input	TCELL0:IMUX.IMUX29
TXDATA12	input	TCELL0:IMUX.IMUX34
TXDATA120	input	TCELL1:IMUX.IMUX6
TXDATA121	input	TCELL1:IMUX.IMUX20
TXDATA122	input	TCELL1:IMUX.IMUX39
TXDATA123	input	TCELL1:IMUX.IMUX28
TXDATA124	input	TCELL2:IMUX.IMUX30
TXDATA125	input	TCELL2:IMUX.IMUX31
TXDATA126	input	TCELL2:IMUX.IMUX38
TXDATA127	input	TCELL2:IMUX.IMUX27
TXDATA128	input	TCELL3:IMUX.IMUX30
TXDATA129	input	TCELL3:IMUX.IMUX31
TXDATA13	input	TCELL0:IMUX.IMUX35
TXDATA130	input	TCELL3:IMUX.IMUX38
TXDATA131	input	TCELL3:IMUX.IMUX39
TXDATA14	input	TCELL1:IMUX.IMUX32
TXDATA15	input	TCELL1:IMUX.IMUX33
TXDATA16	input	TCELL1:IMUX.IMUX34
TXDATA17	input	TCELL1:IMUX.IMUX35
TXDATA18	input	TCELL2:IMUX.IMUX32
TXDATA19	input	TCELL2:IMUX.IMUX33
TXDATAWIDTH00	input	TCELL16:IMUX.IMUX31
TXDATAWIDTH01	input	TCELL16:IMUX.IMUX24
TXDATAWIDTH10	input	TCELL3:IMUX.IMUX4
TXDATAWIDTH11	input	TCELL3:IMUX.IMUX5
TXDETECTRX0	input	TCELL19:IMUX.IMUX18
TXDETECTRX1	input	TCELL0:IMUX.IMUX47
TXDIFFCTRL00	input	TCELL19:IMUX.IMUX33
TXDIFFCTRL01	input	TCELL19:IMUX.IMUX34
TXDIFFCTRL02	input	TCELL19:IMUX.IMUX35
TXDIFFCTRL10	input	TCELL0:IMUX.IMUX8
TXDIFFCTRL11	input	TCELL0:IMUX.IMUX7
TXDIFFCTRL12	input	TCELL0:IMUX.IMUX6
TXELECIDLE0	input	TCELL19:IMUX.IMUX19
TXELECIDLE1	input	TCELL0:IMUX.IMUX4
TXENC8B10BUSE0	input	TCELL16:IMUX.IMUX30
TXENC8B10BUSE1	input	TCELL3:IMUX.IMUX47
TXENPMAPHASEALIGN0	input	TCELL10:IMUX.IMUX16
TXENPMAPHASEALIGN1	input	TCELL9:IMUX.IMUX20
TXENPRBSTST00	input	TCELL18:IMUX.IMUX24
TXENPRBSTST01	input	TCELL18:IMUX.IMUX25
TXENPRBSTST10	input	TCELL1:IMUX.IMUX11
TXENPRBSTST11	input	TCELL1:IMUX.IMUX10
TXGEARBOXREADY0	output	TCELL19:OUT16
TXGEARBOXREADY1	output	TCELL0:OUT0
TXHEADER00	input	TCELL16:IMUX.IMUX32
TXHEADER01	input	TCELL16:IMUX.IMUX33
TXHEADER02	input	TCELL16:IMUX.IMUX4
TXHEADER10	input	TCELL3:IMUX.IMUX9
TXHEADER11	input	TCELL3:IMUX.IMUX20
TXHEADER12	input	TCELL3:IMUX.IMUX7
TXINHIBIT0	input	TCELL16:IMUX.IMUX28
TXINHIBIT1	input	TCELL3:IMUX.IMUX1
TXKERR00	output	TCELL18:OUT5
TXKERR01	output	TCELL17:OUT18
TXKERR02	output	TCELL18:OUT13
TXKERR03	output	TCELL17:OUT22
TXKERR10	output	TCELL1:OUT7
TXKERR11	output	TCELL2:OUT15
TXKERR12	output	TCELL1:OUT14
TXKERR13	output	TCELL2:OUT10
TXOUTCLK0	output	TCELL10:OUT13
TXOUTCLK1	output	TCELL9:OUT2
TXPMASETPHASE0	input	TCELL10:IMUX.IMUX17
TXPMASETPHASE1	input	TCELL9:IMUX.IMUX33
TXPOLARITY0	input	TCELL17:IMUX.IMUX15
TXPOLARITY1	input	TCELL2:IMUX.IMUX2
TXPOWERDOWN00	input	TCELL17:IMUX.IMUX10
TXPOWERDOWN01	input	TCELL17:IMUX.IMUX11
TXPOWERDOWN10	input	TCELL2:IMUX.IMUX43
TXPOWERDOWN11	input	TCELL2:IMUX.IMUX42
TXPREEMPHASIS00	input	TCELL18:IMUX.IMUX15
TXPREEMPHASIS01	input	TCELL18:IMUX.IMUX16
TXPREEMPHASIS02	input	TCELL18:IMUX.IMUX17
TXPREEMPHASIS03	input	TCELL17:IMUX.IMUX37
TXPREEMPHASIS10	input	TCELL1:IMUX.IMUX26
TXPREEMPHASIS11	input	TCELL1:IMUX.IMUX25
TXPREEMPHASIS12	input	TCELL1:IMUX.IMUX24
TXPREEMPHASIS13	input	TCELL2:IMUX.IMUX10
TXRESET0	input	TCELL16:IMUX.IMUX47
TXRESET1	input	TCELL3:IMUX.IMUX0
TXRUNDISP00	output	TCELL18:OUT22
TXRUNDISP01	output	TCELL17:OUT2
TXRUNDISP02	output	TCELL18:OUT15
TXRUNDISP03	output	TCELL16:OUT18
TXRUNDISP10	output	TCELL1:OUT11
TXRUNDISP11	output	TCELL2:OUT5
TXRUNDISP12	output	TCELL1:OUT18
TXRUNDISP13	output	TCELL3:OUT21
TXSEQUENCE00	input	TCELL18:IMUX.IMUX2
TXSEQUENCE01	input	TCELL18:IMUX.IMUX3
TXSEQUENCE02	input	TCELL19:IMUX.IMUX0
TXSEQUENCE03	input	TCELL19:IMUX.IMUX1
TXSEQUENCE04	input	TCELL19:IMUX.IMUX3
TXSEQUENCE05	input	TCELL19:IMUX.IMUX4
TXSEQUENCE06	input	TCELL19:IMUX.IMUX5
TXSEQUENCE10	input	TCELL1:IMUX.IMUX46
TXSEQUENCE11	input	TCELL1:IMUX.IMUX3
TXSEQUENCE12	input	TCELL0:IMUX.IMUX41
TXSEQUENCE13	input	TCELL0:IMUX.IMUX46
TXSEQUENCE14	input	TCELL0:IMUX.IMUX45
TXSEQUENCE15	input	TCELL0:IMUX.IMUX44
TXSEQUENCE16	input	TCELL0:IMUX.IMUX37
TXSTARTSEQ0	input	TCELL16:IMUX.IMUX9
TXSTARTSEQ1	input	TCELL3:IMUX.IMUX8
TXUSRCLK0	input	TCELL11:IMUX.CLK0
TXUSRCLK1	input	TCELL8:IMUX.CLK1
TXUSRCLK20	input	TCELL11:IMUX.CLK1
TXUSRCLK21	input	TCELL8:IMUX.CLK0

Bel BUFDS0

virtex5 GTX bel BUFDS0
Pin	Direction	Wires

Bel CRC32_0

virtex5 GTX bel CRC32_0
Pin	Direction	Wires
CRCCLK	input	TCELL1:IMUX.CLK1
CRCDATAVALID	input	TCELL3:IMUX.IMUX22
CRCDATAWIDTH0	input	TCELL3:IMUX.IMUX40
CRCDATAWIDTH1	input	TCELL3:IMUX.IMUX23
CRCDATAWIDTH2	input	TCELL3:IMUX.IMUX21
CRCIN0	input	TCELL3:IMUX.IMUX17
CRCIN1	input	TCELL3:IMUX.IMUX16
CRCIN10	input	TCELL2:IMUX.IMUX15
CRCIN11	input	TCELL2:IMUX.IMUX14
CRCIN12	input	TCELL2:IMUX.IMUX13
CRCIN13	input	TCELL2:IMUX.IMUX12
CRCIN14	input	TCELL2:IMUX.IMUX37
CRCIN15	input	TCELL2:IMUX.IMUX36
CRCIN16	input	TCELL1:IMUX.IMUX23
CRCIN17	input	TCELL1:IMUX.IMUX22
CRCIN18	input	TCELL1:IMUX.IMUX45
CRCIN19	input	TCELL1:IMUX.IMUX44
CRCIN2	input	TCELL3:IMUX.IMUX15
CRCIN20	input	TCELL1:IMUX.IMUX43
CRCIN21	input	TCELL1:IMUX.IMUX42
CRCIN22	input	TCELL1:IMUX.IMUX19
CRCIN23	input	TCELL1:IMUX.IMUX18
CRCIN24	input	TCELL0:IMUX.IMUX23
CRCIN25	input	TCELL0:IMUX.IMUX22
CRCIN26	input	TCELL0:IMUX.IMUX21
CRCIN27	input	TCELL0:IMUX.IMUX20
CRCIN28	input	TCELL0:IMUX.IMUX25
CRCIN29	input	TCELL0:IMUX.IMUX24
CRCIN3	input	TCELL3:IMUX.IMUX14
CRCIN30	input	TCELL0:IMUX.IMUX43
CRCIN31	input	TCELL0:IMUX.IMUX42
CRCIN4	input	TCELL3:IMUX.IMUX13
CRCIN5	input	TCELL3:IMUX.IMUX12
CRCIN6	input	TCELL3:IMUX.IMUX37
CRCIN7	input	TCELL3:IMUX.IMUX36
CRCIN8	input	TCELL2:IMUX.IMUX17
CRCIN9	input	TCELL2:IMUX.IMUX16
CRCOUT0	output	TCELL3:OUT6
CRCOUT1	output	TCELL3:OUT4
CRCOUT10	output	TCELL2:OUT22
CRCOUT11	output	TCELL2:OUT12
CRCOUT12	output	TCELL1:OUT17
CRCOUT13	output	TCELL1:OUT16
CRCOUT14	output	TCELL1:OUT23
CRCOUT15	output	TCELL1:OUT13
CRCOUT16	output	TCELL1:OUT5
CRCOUT17	output	TCELL1:OUT1
CRCOUT18	output	TCELL1:OUT22
CRCOUT19	output	TCELL1:OUT12
CRCOUT2	output	TCELL3:OUT18
CRCOUT20	output	TCELL0:OUT21
CRCOUT21	output	TCELL0:OUT15
CRCOUT22	output	TCELL0:OUT7
CRCOUT23	output	TCELL0:OUT3
CRCOUT24	output	TCELL0:OUT20
CRCOUT25	output	TCELL0:OUT14
CRCOUT26	output	TCELL0:OUT23
CRCOUT27	output	TCELL0:OUT13
CRCOUT28	output	TCELL0:OUT5
CRCOUT29	output	TCELL0:OUT1
CRCOUT3	output	TCELL2:OUT21
CRCOUT30	output	TCELL0:OUT22
CRCOUT31	output	TCELL0:OUT4
CRCOUT4	output	TCELL2:OUT6
CRCOUT5	output	TCELL2:OUT20
CRCOUT6	output	TCELL2:OUT14
CRCOUT7	output	TCELL2:OUT23
CRCOUT8	output	TCELL2:OUT13
CRCOUT9	output	TCELL2:OUT1
CRCRESET	input	TCELL2:IMUX.IMUX5

Bel CRC32_1

virtex5 GTX bel CRC32_1
Pin	Direction	Wires
CRCCLK	input	TCELL6:IMUX.CLK1
CRCDATAVALID	input	TCELL8:IMUX.IMUX35
CRCDATAWIDTH0	input	TCELL8:IMUX.IMUX11
CRCDATAWIDTH1	input	TCELL8:IMUX.IMUX34
CRCDATAWIDTH2	input	TCELL3:IMUX.IMUX21
CRCIN0	input	TCELL7:IMUX.IMUX47
CRCIN1	input	TCELL7:IMUX.IMUX46
CRCIN10	input	TCELL6:IMUX.IMUX45
CRCIN11	input	TCELL6:IMUX.IMUX44
CRCIN12	input	TCELL6:IMUX.IMUX43
CRCIN13	input	TCELL6:IMUX.IMUX42
CRCIN14	input	TCELL6:IMUX.IMUX37
CRCIN15	input	TCELL6:IMUX.IMUX36
CRCIN16	input	TCELL5:IMUX.IMUX47
CRCIN17	input	TCELL5:IMUX.IMUX46
CRCIN18	input	TCELL5:IMUX.IMUX45
CRCIN19	input	TCELL5:IMUX.IMUX44
CRCIN2	input	TCELL7:IMUX.IMUX45
CRCIN20	input	TCELL5:IMUX.IMUX43
CRCIN21	input	TCELL5:IMUX.IMUX42
CRCIN22	input	TCELL5:IMUX.IMUX37
CRCIN23	input	TCELL5:IMUX.IMUX36
CRCIN24	input	TCELL4:IMUX.IMUX47
CRCIN25	input	TCELL4:IMUX.IMUX46
CRCIN26	input	TCELL4:IMUX.IMUX45
CRCIN27	input	TCELL4:IMUX.IMUX44
CRCIN28	input	TCELL4:IMUX.IMUX43
CRCIN29	input	TCELL4:IMUX.IMUX42
CRCIN3	input	TCELL7:IMUX.IMUX44
CRCIN30	input	TCELL4:IMUX.IMUX37
CRCIN31	input	TCELL4:IMUX.IMUX36
CRCIN4	input	TCELL7:IMUX.IMUX43
CRCIN5	input	TCELL7:IMUX.IMUX42
CRCIN6	input	TCELL7:IMUX.IMUX37
CRCIN7	input	TCELL7:IMUX.IMUX36
CRCIN8	input	TCELL6:IMUX.IMUX47
CRCIN9	input	TCELL6:IMUX.IMUX46
CRCOUT0	output	TCELL9:OUT11
CRCOUT1	output	TCELL9:OUT3
CRCOUT10	output	TCELL8:OUT15
CRCOUT11	output	TCELL8:OUT11
CRCOUT12	output	TCELL8:OUT6
CRCOUT13	output	TCELL8:OUT2
CRCOUT14	output	TCELL8:OUT16
CRCOUT15	output	TCELL8:OUT10
CRCOUT16	output	TCELL8:OUT23
CRCOUT17	output	TCELL8:OUT9
CRCOUT18	output	TCELL8:OUT5
CRCOUT19	output	TCELL8:OUT0
CRCOUT2	output	TCELL9:OUT14
CRCOUT20	output	TCELL7:OUT21
CRCOUT21	output	TCELL7:OUT17
CRCOUT22	output	TCELL7:OUT3
CRCOUT23	output	TCELL7:OUT12
CRCOUT24	output	TCELL6:OUT15
CRCOUT25	output	TCELL6:OUT14
CRCOUT26	output	TCELL6:OUT12
CRCOUT27	output	TCELL5:OUT21
CRCOUT28	output	TCELL5:OUT7
CRCOUT29	output	TCELL5:OUT5
CRCOUT3	output	TCELL9:OUT13
CRCOUT30	output	TCELL5:OUT22
CRCOUT31	output	TCELL4:OUT21
CRCOUT4	output	TCELL9:OUT4
CRCOUT5	output	TCELL9:OUT0
CRCOUT6	output	TCELL9:OUT18
CRCOUT7	output	TCELL9:OUT12
CRCOUT8	output	TCELL9:OUT8
CRCOUT9	output	TCELL8:OUT17
CRCRESET	input	TCELL8:IMUX.IMUX0

Bel CRC32_2

virtex5 GTX bel CRC32_2
Pin	Direction	Wires
CRCCLK	input	TCELL13:IMUX.CLK0
CRCDATAVALID	input	TCELL11:IMUX.IMUX30
CRCDATAWIDTH0	input	TCELL11:IMUX.IMUX24
CRCDATAWIDTH1	input	TCELL11:IMUX.IMUX13
CRCDATAWIDTH2	input	TCELL16:IMUX.IMUX8
CRCIN0	input	TCELL12:IMUX.IMUX0
CRCIN1	input	TCELL12:IMUX.IMUX1
CRCIN10	input	TCELL13:IMUX.IMUX8
CRCIN11	input	TCELL13:IMUX.IMUX9
CRCIN12	input	TCELL13:IMUX.IMUX4
CRCIN13	input	TCELL13:IMUX.IMUX5
CRCIN14	input	TCELL13:IMUX.IMUX10
CRCIN15	input	TCELL13:IMUX.IMUX11
CRCIN16	input	TCELL14:IMUX.IMUX6
CRCIN17	input	TCELL14:IMUX.IMUX7
CRCIN18	input	TCELL14:IMUX.IMUX8
CRCIN19	input	TCELL14:IMUX.IMUX9
CRCIN2	input	TCELL12:IMUX.IMUX2
CRCIN20	input	TCELL14:IMUX.IMUX4
CRCIN21	input	TCELL14:IMUX.IMUX5
CRCIN22	input	TCELL14:IMUX.IMUX10
CRCIN23	input	TCELL14:IMUX.IMUX11
CRCIN24	input	TCELL15:IMUX.IMUX6
CRCIN25	input	TCELL15:IMUX.IMUX7
CRCIN26	input	TCELL15:IMUX.IMUX8
CRCIN27	input	TCELL15:IMUX.IMUX9
CRCIN28	input	TCELL15:IMUX.IMUX4
CRCIN29	input	TCELL15:IMUX.IMUX5
CRCIN3	input	TCELL12:IMUX.IMUX9
CRCIN30	input	TCELL15:IMUX.IMUX10
CRCIN31	input	TCELL15:IMUX.IMUX11
CRCIN4	input	TCELL12:IMUX.IMUX45
CRCIN5	input	TCELL12:IMUX.IMUX35
CRCIN6	input	TCELL12:IMUX.IMUX10
CRCIN7	input	TCELL12:IMUX.IMUX11
CRCIN8	input	TCELL13:IMUX.IMUX6
CRCIN9	input	TCELL13:IMUX.IMUX7
CRCOUT0	output	TCELL10:OUT4
CRCOUT1	output	TCELL10:OUT23
CRCOUT10	output	TCELL11:OUT4
CRCOUT11	output	TCELL11:OUT22
CRCOUT12	output	TCELL11:OUT5
CRCOUT13	output	TCELL11:OUT13
CRCOUT14	output	TCELL11:OUT19
CRCOUT15	output	TCELL11:OUT23
CRCOUT16	output	TCELL11:OUT10
CRCOUT17	output	TCELL11:OUT16
CRCOUT18	output	TCELL11:OUT3
CRCOUT19	output	TCELL11:OUT7
CRCOUT2	output	TCELL10:OUT16
CRCOUT20	output	TCELL12:OUT8
CRCOUT21	output	TCELL12:OUT18
CRCOUT22	output	TCELL12:OUT4
CRCOUT23	output	TCELL12:OUT17
CRCOUT24	output	TCELL13:OUT18
CRCOUT25	output	TCELL13:OUT19
CRCOUT26	output	TCELL13:OUT17
CRCOUT27	output	TCELL14:OUT18
CRCOUT28	output	TCELL14:OUT4
CRCOUT29	output	TCELL14:OUT6
CRCOUT3	output	TCELL10:OUT2
CRCOUT30	output	TCELL14:OUT17
CRCOUT31	output	TCELL15:OUT18
CRCOUT4	output	TCELL10:OUT6
CRCOUT5	output	TCELL10:OUT7
CRCOUT6	output	TCELL10:OUT11
CRCOUT7	output	TCELL10:OUT15
CRCOUT8	output	TCELL10:OUT21
CRCOUT9	output	TCELL11:OUT12
CRCRESET	input	TCELL11:IMUX.IMUX5

Bel CRC32_3

virtex5 GTX bel CRC32_3
Pin	Direction	Wires
CRCCLK	input	TCELL18:IMUX.CLK0
CRCDATAVALID	input	TCELL16:IMUX.IMUX7
CRCDATAWIDTH0	input	TCELL16:IMUX.IMUX6
CRCDATAWIDTH1	input	TCELL16:IMUX.IMUX1
CRCDATAWIDTH2	input	TCELL16:IMUX.IMUX8
CRCIN0	input	TCELL16:IMUX.IMUX36
CRCIN1	input	TCELL16:IMUX.IMUX37
CRCIN10	input	TCELL17:IMUX.IMUX32
CRCIN11	input	TCELL17:IMUX.IMUX33
CRCIN12	input	TCELL17:IMUX.IMUX34
CRCIN13	input	TCELL17:IMUX.IMUX35
CRCIN14	input	TCELL17:IMUX.IMUX46
CRCIN15	input	TCELL17:IMUX.IMUX47
CRCIN16	input	TCELL18:IMUX.IMUX6
CRCIN17	input	TCELL18:IMUX.IMUX7
CRCIN18	input	TCELL18:IMUX.IMUX8
CRCIN19	input	TCELL18:IMUX.IMUX21
CRCIN2	input	TCELL16:IMUX.IMUX38
CRCIN20	input	TCELL18:IMUX.IMUX10
CRCIN21	input	TCELL18:IMUX.IMUX11
CRCIN22	input	TCELL18:IMUX.IMUX40
CRCIN23	input	TCELL18:IMUX.IMUX41
CRCIN24	input	TCELL19:IMUX.IMUX24
CRCIN25	input	TCELL19:IMUX.IMUX25
CRCIN26	input	TCELL19:IMUX.IMUX26
CRCIN27	input	TCELL19:IMUX.IMUX21
CRCIN28	input	TCELL19:IMUX.IMUX10
CRCIN29	input	TCELL19:IMUX.IMUX11
CRCIN3	input	TCELL16:IMUX.IMUX39
CRCIN30	input	TCELL19:IMUX.IMUX40
CRCIN31	input	TCELL19:IMUX.IMUX41
CRCIN4	input	TCELL16:IMUX.IMUX40
CRCIN5	input	TCELL16:IMUX.IMUX35
CRCIN6	input	TCELL16:IMUX.IMUX10
CRCIN7	input	TCELL16:IMUX.IMUX11
CRCIN8	input	TCELL17:IMUX.IMUX30
CRCIN9	input	TCELL17:IMUX.IMUX31
CRCOUT0	output	TCELL16:OUT13
CRCOUT1	output	TCELL16:OUT3
CRCOUT10	output	TCELL17:OUT15
CRCOUT11	output	TCELL17:OUT17
CRCOUT12	output	TCELL18:OUT12
CRCOUT13	output	TCELL18:OUT9
CRCOUT14	output	TCELL18:OUT10
CRCOUT15	output	TCELL18:OUT6
CRCOUT16	output	TCELL18:OUT3
CRCOUT17	output	TCELL18:OUT7
CRCOUT18	output	TCELL18:OUT17
CRCOUT19	output	TCELL18:OUT21
CRCOUT2	output	TCELL16:OUT15
CRCOUT20	output	TCELL19:OUT12
CRCOUT21	output	TCELL19:OUT4
CRCOUT22	output	TCELL19:OUT1
CRCOUT23	output	TCELL19:OUT5
CRCOUT24	output	TCELL19:OUT19
CRCOUT25	output	TCELL19:OUT20
CRCOUT26	output	TCELL19:OUT10
CRCOUT27	output	TCELL19:OUT6
CRCOUT28	output	TCELL19:OUT3
CRCOUT29	output	TCELL19:OUT7
CRCOUT3	output	TCELL17:OUT8
CRCOUT30	output	TCELL19:OUT11
CRCOUT31	output	TCELL19:OUT21
CRCOUT4	output	TCELL17:OUT1
CRCOUT5	output	TCELL17:OUT13
CRCOUT6	output	TCELL17:OUT19
CRCOUT7	output	TCELL17:OUT14
CRCOUT8	output	TCELL17:OUT20
CRCOUT9	output	TCELL17:OUT6
CRCRESET	input	TCELL17:IMUX.IMUX0

Bel CRC64_0

virtex5 GTX bel CRC64_0
Pin	Direction	Wires
CRCCLK	input	TCELL1:IMUX.CLK1
CRCDATAVALID	input	TCELL3:IMUX.IMUX22
CRCDATAWIDTH0	input	TCELL3:IMUX.IMUX40
CRCDATAWIDTH1	input	TCELL3:IMUX.IMUX23
CRCDATAWIDTH2	input	TCELL3:IMUX.IMUX21
CRCIN0	input	TCELL7:IMUX.IMUX47
CRCIN1	input	TCELL7:IMUX.IMUX46
CRCIN10	input	TCELL6:IMUX.IMUX45
CRCIN11	input	TCELL6:IMUX.IMUX44
CRCIN12	input	TCELL6:IMUX.IMUX43
CRCIN13	input	TCELL6:IMUX.IMUX42
CRCIN14	input	TCELL6:IMUX.IMUX37
CRCIN15	input	TCELL6:IMUX.IMUX36
CRCIN16	input	TCELL5:IMUX.IMUX47
CRCIN17	input	TCELL5:IMUX.IMUX46
CRCIN18	input	TCELL5:IMUX.IMUX45
CRCIN19	input	TCELL5:IMUX.IMUX44
CRCIN2	input	TCELL7:IMUX.IMUX45
CRCIN20	input	TCELL5:IMUX.IMUX43
CRCIN21	input	TCELL5:IMUX.IMUX42
CRCIN22	input	TCELL5:IMUX.IMUX37
CRCIN23	input	TCELL5:IMUX.IMUX36
CRCIN24	input	TCELL4:IMUX.IMUX47
CRCIN25	input	TCELL4:IMUX.IMUX46
CRCIN26	input	TCELL4:IMUX.IMUX45
CRCIN27	input	TCELL4:IMUX.IMUX44
CRCIN28	input	TCELL4:IMUX.IMUX43
CRCIN29	input	TCELL4:IMUX.IMUX42
CRCIN3	input	TCELL7:IMUX.IMUX44
CRCIN30	input	TCELL4:IMUX.IMUX37
CRCIN31	input	TCELL4:IMUX.IMUX36
CRCIN32	input	TCELL3:IMUX.IMUX17
CRCIN33	input	TCELL3:IMUX.IMUX16
CRCIN34	input	TCELL3:IMUX.IMUX15
CRCIN35	input	TCELL3:IMUX.IMUX14
CRCIN36	input	TCELL3:IMUX.IMUX13
CRCIN37	input	TCELL3:IMUX.IMUX12
CRCIN38	input	TCELL3:IMUX.IMUX37
CRCIN39	input	TCELL3:IMUX.IMUX36
CRCIN4	input	TCELL7:IMUX.IMUX43
CRCIN40	input	TCELL2:IMUX.IMUX17
CRCIN41	input	TCELL2:IMUX.IMUX16
CRCIN42	input	TCELL2:IMUX.IMUX15
CRCIN43	input	TCELL2:IMUX.IMUX14
CRCIN44	input	TCELL2:IMUX.IMUX13
CRCIN45	input	TCELL2:IMUX.IMUX12
CRCIN46	input	TCELL2:IMUX.IMUX37
CRCIN47	input	TCELL2:IMUX.IMUX36
CRCIN48	input	TCELL1:IMUX.IMUX23
CRCIN49	input	TCELL1:IMUX.IMUX22
CRCIN5	input	TCELL7:IMUX.IMUX42
CRCIN50	input	TCELL1:IMUX.IMUX45
CRCIN51	input	TCELL1:IMUX.IMUX44
CRCIN52	input	TCELL1:IMUX.IMUX43
CRCIN53	input	TCELL1:IMUX.IMUX42
CRCIN54	input	TCELL1:IMUX.IMUX19
CRCIN55	input	TCELL1:IMUX.IMUX18
CRCIN56	input	TCELL0:IMUX.IMUX23
CRCIN57	input	TCELL0:IMUX.IMUX22
CRCIN58	input	TCELL0:IMUX.IMUX21
CRCIN59	input	TCELL0:IMUX.IMUX20
CRCIN6	input	TCELL7:IMUX.IMUX37
CRCIN60	input	TCELL0:IMUX.IMUX25
CRCIN61	input	TCELL0:IMUX.IMUX24
CRCIN62	input	TCELL0:IMUX.IMUX43
CRCIN63	input	TCELL0:IMUX.IMUX42
CRCIN7	input	TCELL7:IMUX.IMUX36
CRCIN8	input	TCELL6:IMUX.IMUX47
CRCIN9	input	TCELL6:IMUX.IMUX46
CRCOUT0	output	TCELL3:OUT6
CRCOUT1	output	TCELL3:OUT4
CRCOUT10	output	TCELL2:OUT22
CRCOUT11	output	TCELL2:OUT12
CRCOUT12	output	TCELL1:OUT17
CRCOUT13	output	TCELL1:OUT16
CRCOUT14	output	TCELL1:OUT23
CRCOUT15	output	TCELL1:OUT13
CRCOUT16	output	TCELL1:OUT5
CRCOUT17	output	TCELL1:OUT1
CRCOUT18	output	TCELL1:OUT22
CRCOUT19	output	TCELL1:OUT12
CRCOUT2	output	TCELL3:OUT18
CRCOUT20	output	TCELL0:OUT21
CRCOUT21	output	TCELL0:OUT15
CRCOUT22	output	TCELL0:OUT7
CRCOUT23	output	TCELL0:OUT3
CRCOUT24	output	TCELL0:OUT20
CRCOUT25	output	TCELL0:OUT14
CRCOUT26	output	TCELL0:OUT23
CRCOUT27	output	TCELL0:OUT13
CRCOUT28	output	TCELL0:OUT5
CRCOUT29	output	TCELL0:OUT1
CRCOUT3	output	TCELL2:OUT21
CRCOUT30	output	TCELL0:OUT22
CRCOUT31	output	TCELL0:OUT4
CRCOUT4	output	TCELL2:OUT6
CRCOUT5	output	TCELL2:OUT20
CRCOUT6	output	TCELL2:OUT14
CRCOUT7	output	TCELL2:OUT23
CRCOUT8	output	TCELL2:OUT13
CRCOUT9	output	TCELL2:OUT1
CRCRESET	input	TCELL2:IMUX.IMUX5

Bel CRC64_1

virtex5 GTX bel CRC64_1
Pin	Direction	Wires
CRCCLK	input	TCELL18:IMUX.CLK0
CRCDATAVALID	input	TCELL16:IMUX.IMUX7
CRCDATAWIDTH0	input	TCELL16:IMUX.IMUX6
CRCDATAWIDTH1	input	TCELL16:IMUX.IMUX1
CRCDATAWIDTH2	input	TCELL16:IMUX.IMUX8
CRCIN0	input	TCELL12:IMUX.IMUX0
CRCIN1	input	TCELL12:IMUX.IMUX1
CRCIN10	input	TCELL13:IMUX.IMUX8
CRCIN11	input	TCELL13:IMUX.IMUX9
CRCIN12	input	TCELL13:IMUX.IMUX4
CRCIN13	input	TCELL13:IMUX.IMUX5
CRCIN14	input	TCELL13:IMUX.IMUX10
CRCIN15	input	TCELL13:IMUX.IMUX11
CRCIN16	input	TCELL14:IMUX.IMUX6
CRCIN17	input	TCELL14:IMUX.IMUX7
CRCIN18	input	TCELL14:IMUX.IMUX8
CRCIN19	input	TCELL14:IMUX.IMUX9
CRCIN2	input	TCELL12:IMUX.IMUX2
CRCIN20	input	TCELL14:IMUX.IMUX4
CRCIN21	input	TCELL14:IMUX.IMUX5
CRCIN22	input	TCELL14:IMUX.IMUX10
CRCIN23	input	TCELL14:IMUX.IMUX11
CRCIN24	input	TCELL15:IMUX.IMUX6
CRCIN25	input	TCELL15:IMUX.IMUX7
CRCIN26	input	TCELL15:IMUX.IMUX8
CRCIN27	input	TCELL15:IMUX.IMUX9
CRCIN28	input	TCELL15:IMUX.IMUX4
CRCIN29	input	TCELL15:IMUX.IMUX5
CRCIN3	input	TCELL12:IMUX.IMUX9
CRCIN30	input	TCELL15:IMUX.IMUX10
CRCIN31	input	TCELL15:IMUX.IMUX11
CRCIN32	input	TCELL16:IMUX.IMUX36
CRCIN33	input	TCELL16:IMUX.IMUX37
CRCIN34	input	TCELL16:IMUX.IMUX38
CRCIN35	input	TCELL16:IMUX.IMUX39
CRCIN36	input	TCELL16:IMUX.IMUX40
CRCIN37	input	TCELL16:IMUX.IMUX35
CRCIN38	input	TCELL16:IMUX.IMUX10
CRCIN39	input	TCELL16:IMUX.IMUX11
CRCIN4	input	TCELL12:IMUX.IMUX45
CRCIN40	input	TCELL17:IMUX.IMUX30
CRCIN41	input	TCELL17:IMUX.IMUX31
CRCIN42	input	TCELL17:IMUX.IMUX32
CRCIN43	input	TCELL17:IMUX.IMUX33
CRCIN44	input	TCELL17:IMUX.IMUX34
CRCIN45	input	TCELL17:IMUX.IMUX35
CRCIN46	input	TCELL17:IMUX.IMUX46
CRCIN47	input	TCELL17:IMUX.IMUX47
CRCIN48	input	TCELL18:IMUX.IMUX6
CRCIN49	input	TCELL18:IMUX.IMUX7
CRCIN5	input	TCELL12:IMUX.IMUX35
CRCIN50	input	TCELL18:IMUX.IMUX8
CRCIN51	input	TCELL18:IMUX.IMUX21
CRCIN52	input	TCELL18:IMUX.IMUX10
CRCIN53	input	TCELL18:IMUX.IMUX11
CRCIN54	input	TCELL18:IMUX.IMUX40
CRCIN55	input	TCELL18:IMUX.IMUX41
CRCIN56	input	TCELL19:IMUX.IMUX24
CRCIN57	input	TCELL19:IMUX.IMUX25
CRCIN58	input	TCELL19:IMUX.IMUX26
CRCIN59	input	TCELL19:IMUX.IMUX21
CRCIN6	input	TCELL12:IMUX.IMUX10
CRCIN60	input	TCELL19:IMUX.IMUX10
CRCIN61	input	TCELL19:IMUX.IMUX11
CRCIN62	input	TCELL19:IMUX.IMUX40
CRCIN63	input	TCELL19:IMUX.IMUX41
CRCIN7	input	TCELL12:IMUX.IMUX11
CRCIN8	input	TCELL13:IMUX.IMUX6
CRCIN9	input	TCELL13:IMUX.IMUX7
CRCOUT0	output	TCELL16:OUT13
CRCOUT1	output	TCELL16:OUT3
CRCOUT10	output	TCELL17:OUT15
CRCOUT11	output	TCELL17:OUT17
CRCOUT12	output	TCELL18:OUT12
CRCOUT13	output	TCELL18:OUT9
CRCOUT14	output	TCELL18:OUT10
CRCOUT15	output	TCELL18:OUT6
CRCOUT16	output	TCELL18:OUT3
CRCOUT17	output	TCELL18:OUT7
CRCOUT18	output	TCELL18:OUT17
CRCOUT19	output	TCELL18:OUT21
CRCOUT2	output	TCELL16:OUT15
CRCOUT20	output	TCELL19:OUT12
CRCOUT21	output	TCELL19:OUT4
CRCOUT22	output	TCELL19:OUT1
CRCOUT23	output	TCELL19:OUT5
CRCOUT24	output	TCELL19:OUT19
CRCOUT25	output	TCELL19:OUT20
CRCOUT26	output	TCELL19:OUT10
CRCOUT27	output	TCELL19:OUT6
CRCOUT28	output	TCELL19:OUT3
CRCOUT29	output	TCELL19:OUT7
CRCOUT3	output	TCELL17:OUT8
CRCOUT30	output	TCELL19:OUT11
CRCOUT31	output	TCELL19:OUT21
CRCOUT4	output	TCELL17:OUT1
CRCOUT5	output	TCELL17:OUT13
CRCOUT6	output	TCELL17:OUT19
CRCOUT7	output	TCELL17:OUT14
CRCOUT8	output	TCELL17:OUT20
CRCOUT9	output	TCELL17:OUT6
CRCRESET	input	TCELL17:IMUX.IMUX0

Bel IPAD_CLKP0

virtex5 GTX bel IPAD_CLKP0
Pin	Direction	Wires

Bel IPAD_CLKN0

virtex5 GTX bel IPAD_CLKN0
Pin	Direction	Wires

Bel IPAD_RXP0

virtex5 GTX bel IPAD_RXP0
Pin	Direction	Wires

Bel IPAD_RXN0

virtex5 GTX bel IPAD_RXN0
Pin	Direction	Wires

Bel IPAD_RXP1

virtex5 GTX bel IPAD_RXP1
Pin	Direction	Wires

Bel IPAD_RXN1

virtex5 GTX bel IPAD_RXN1
Pin	Direction	Wires

Bel OPAD_TXP0

virtex5 GTX bel OPAD_TXP0
Pin	Direction	Wires

Bel OPAD_TXN0

virtex5 GTX bel OPAD_TXN0
Pin	Direction	Wires

Bel OPAD_TXP1

virtex5 GTX bel OPAD_TXP1
Pin	Direction	Wires

Bel OPAD_TXN1

virtex5 GTX bel OPAD_TXN1
Pin	Direction	Wires

Bel wires

virtex5 GTX bel wires
Wire	Pins
TCELL0:IMUX.IMUX0	GTX_DUAL.TXDATA116
TCELL0:IMUX.IMUX4	GTX_DUAL.TXELECIDLE1
TCELL0:IMUX.IMUX6	GTX_DUAL.TXDIFFCTRL12
TCELL0:IMUX.IMUX7	GTX_DUAL.TXDIFFCTRL11
TCELL0:IMUX.IMUX8	GTX_DUAL.TXDIFFCTRL10
TCELL0:IMUX.IMUX9	GTX_DUAL.TXCHARDISPVAL12
TCELL0:IMUX.IMUX11	GTX_DUAL.GTXTEST11
TCELL0:IMUX.IMUX12	GTX_DUAL.GTXTEST10
TCELL0:IMUX.IMUX13	GTX_DUAL.GTXTEST1
TCELL0:IMUX.IMUX14	GTX_DUAL.GTXTEST12
TCELL0:IMUX.IMUX15	GTX_DUAL.TXBUFDIFFCTRL12
TCELL0:IMUX.IMUX16	GTX_DUAL.TXBUFDIFFCTRL11
TCELL0:IMUX.IMUX17	GTX_DUAL.TXBUFDIFFCTRL10
TCELL0:IMUX.IMUX20	CRC32_0.CRCIN27, CRC64_0.CRCIN59
TCELL0:IMUX.IMUX21	CRC32_0.CRCIN26, CRC64_0.CRCIN58
TCELL0:IMUX.IMUX22	CRC32_0.CRCIN25, CRC64_0.CRCIN57
TCELL0:IMUX.IMUX23	CRC32_0.CRCIN24, CRC64_0.CRCIN56
TCELL0:IMUX.IMUX24	CRC32_0.CRCIN29, CRC64_0.CRCIN61
TCELL0:IMUX.IMUX25	CRC32_0.CRCIN28, CRC64_0.CRCIN60
TCELL0:IMUX.IMUX27	GTX_DUAL.TXDATA118
TCELL0:IMUX.IMUX29	GTX_DUAL.TXDATA119
TCELL0:IMUX.IMUX30	GTX_DUAL.SCANINPCS1
TCELL0:IMUX.IMUX31	GTX_DUAL.TXDATA117
TCELL0:IMUX.IMUX32	GTX_DUAL.TXDATA10
TCELL0:IMUX.IMUX33	GTX_DUAL.TXDATA11
TCELL0:IMUX.IMUX34	GTX_DUAL.TXDATA12
TCELL0:IMUX.IMUX35	GTX_DUAL.TXDATA13
TCELL0:IMUX.IMUX36	GTX_DUAL.SCANMODE
TCELL0:IMUX.IMUX37	GTX_DUAL.TXSEQUENCE16
TCELL0:IMUX.IMUX38	GTX_DUAL.TXCHARDISPMODE12
TCELL0:IMUX.IMUX41	GTX_DUAL.TXSEQUENCE12
TCELL0:IMUX.IMUX42	CRC32_0.CRCIN31, CRC64_0.CRCIN63
TCELL0:IMUX.IMUX43	CRC32_0.CRCIN30, CRC64_0.CRCIN62
TCELL0:IMUX.IMUX44	GTX_DUAL.TXSEQUENCE15
TCELL0:IMUX.IMUX45	GTX_DUAL.TXSEQUENCE14
TCELL0:IMUX.IMUX46	GTX_DUAL.TXSEQUENCE13
TCELL0:IMUX.IMUX47	GTX_DUAL.TXDETECTRX1
TCELL0:OUT0	GTX_DUAL.TXGEARBOXREADY1
TCELL0:OUT1	CRC32_0.CRCOUT29, CRC64_0.CRCOUT29
TCELL0:OUT2	GTX_DUAL.RXSTARTOFSEQ1
TCELL0:OUT3	CRC32_0.CRCOUT23, CRC64_0.CRCOUT23
TCELL0:OUT4	CRC32_0.CRCOUT31, CRC64_0.CRCOUT31
TCELL0:OUT5	CRC32_0.CRCOUT28, CRC64_0.CRCOUT28
TCELL0:OUT6	GTX_DUAL.RXHEADER11
TCELL0:OUT7	CRC32_0.CRCOUT22, CRC64_0.CRCOUT22
TCELL0:OUT11	GTX_DUAL.RXHEADERVALID1
TCELL0:OUT12	GTX_DUAL.RXDATAVALID1
TCELL0:OUT13	CRC32_0.CRCOUT27, CRC64_0.CRCOUT27
TCELL0:OUT14	CRC32_0.CRCOUT25, CRC64_0.CRCOUT25
TCELL0:OUT15	CRC32_0.CRCOUT21, CRC64_0.CRCOUT21
TCELL0:OUT16	GTX_DUAL.RXHEADER12
TCELL0:OUT17	GTX_DUAL.RXHEADER10
TCELL0:OUT20	CRC32_0.CRCOUT24, CRC64_0.CRCOUT24
TCELL0:OUT21	CRC32_0.CRCOUT20, CRC64_0.CRCOUT20
TCELL0:OUT22	CRC32_0.CRCOUT30, CRC64_0.CRCOUT30
TCELL0:OUT23	CRC32_0.CRCOUT26, CRC64_0.CRCOUT26
TCELL1:IMUX.CLK1	CRC32_0.CRCCLK, CRC64_0.CRCCLK
TCELL1:IMUX.IMUX0	GTX_DUAL.TXCOMTYPE1
TCELL1:IMUX.IMUX1	GTX_DUAL.TXCHARISK10
TCELL1:IMUX.IMUX3	GTX_DUAL.TXSEQUENCE11
TCELL1:IMUX.IMUX6	GTX_DUAL.TXDATA120
TCELL1:IMUX.IMUX8	GTX_DUAL.TXCHARDISPMODE10
TCELL1:IMUX.IMUX10	GTX_DUAL.TXENPRBSTST11
TCELL1:IMUX.IMUX11	GTX_DUAL.TXENPRBSTST10
TCELL1:IMUX.IMUX12	GTX_DUAL.TXBYPASS8B10B10
TCELL1:IMUX.IMUX13	GTX_DUAL.TXCHARISK12
TCELL1:IMUX.IMUX18	CRC32_0.CRCIN23, CRC64_0.CRCIN55
TCELL1:IMUX.IMUX19	CRC32_0.CRCIN22, CRC64_0.CRCIN54
TCELL1:IMUX.IMUX20	GTX_DUAL.TXDATA121
TCELL1:IMUX.IMUX21	GTX_DUAL.TXCHARDISPVAL10
TCELL1:IMUX.IMUX22	CRC32_0.CRCIN17, CRC64_0.CRCIN49
TCELL1:IMUX.IMUX23	CRC32_0.CRCIN16, CRC64_0.CRCIN48
TCELL1:IMUX.IMUX24	GTX_DUAL.TXPREEMPHASIS12
TCELL1:IMUX.IMUX25	GTX_DUAL.TXPREEMPHASIS11
TCELL1:IMUX.IMUX26	GTX_DUAL.TXPREEMPHASIS10
TCELL1:IMUX.IMUX28	GTX_DUAL.TXDATA123
TCELL1:IMUX.IMUX32	GTX_DUAL.TXDATA14
TCELL1:IMUX.IMUX33	GTX_DUAL.TXDATA15
TCELL1:IMUX.IMUX34	GTX_DUAL.TXDATA16
TCELL1:IMUX.IMUX35	GTX_DUAL.TXDATA17
TCELL1:IMUX.IMUX37	GTX_DUAL.TXCOMSTART1
TCELL1:IMUX.IMUX39	GTX_DUAL.TXDATA122
TCELL1:IMUX.IMUX42	CRC32_0.CRCIN21, CRC64_0.CRCIN53
TCELL1:IMUX.IMUX43	CRC32_0.CRCIN20, CRC64_0.CRCIN52
TCELL1:IMUX.IMUX44	CRC32_0.CRCIN19, CRC64_0.CRCIN51
TCELL1:IMUX.IMUX45	CRC32_0.CRCIN18, CRC64_0.CRCIN50
TCELL1:IMUX.IMUX46	GTX_DUAL.TXSEQUENCE10
TCELL1:IMUX.IMUX47	GTX_DUAL.TSTPWRDNOVRD1
TCELL1:OUT1	CRC32_0.CRCOUT17, CRC64_0.CRCOUT17
TCELL1:OUT2	GTX_DUAL.TXBUFSTATUS10
TCELL1:OUT4	GTX_DUAL.RXDATA131
TCELL1:OUT5	CRC32_0.CRCOUT16, CRC64_0.CRCOUT16
TCELL1:OUT6	GTX_DUAL.RXDATA128
TCELL1:OUT7	GTX_DUAL.TXKERR10
TCELL1:OUT9	GTX_DUAL.RXDATA130
TCELL1:OUT10	GTX_DUAL.TXBUFSTATUS11
TCELL1:OUT11	GTX_DUAL.TXRUNDISP10
TCELL1:OUT12	CRC32_0.CRCOUT19, CRC64_0.CRCOUT19
TCELL1:OUT13	CRC32_0.CRCOUT15, CRC64_0.CRCOUT15
TCELL1:OUT14	GTX_DUAL.TXKERR12
TCELL1:OUT15	GTX_DUAL.RXDISPERR13
TCELL1:OUT16	CRC32_0.CRCOUT13, CRC64_0.CRCOUT13
TCELL1:OUT17	CRC32_0.CRCOUT12, CRC64_0.CRCOUT12
TCELL1:OUT18	GTX_DUAL.TXRUNDISP12
TCELL1:OUT20	GTX_DUAL.RXDATA129
TCELL1:OUT21	GTX_DUAL.RXCHARISK13
TCELL1:OUT22	CRC32_0.CRCOUT18, CRC64_0.CRCOUT18
TCELL1:OUT23	CRC32_0.CRCOUT14, CRC64_0.CRCOUT14
TCELL2:IMUX.IMUX2	GTX_DUAL.TXPOLARITY1
TCELL2:IMUX.IMUX5	CRC32_0.CRCRESET, CRC64_0.CRCRESET
TCELL2:IMUX.IMUX10	GTX_DUAL.TXPREEMPHASIS13
TCELL2:IMUX.IMUX12	CRC32_0.CRCIN13, CRC64_0.CRCIN45
TCELL2:IMUX.IMUX13	CRC32_0.CRCIN12, CRC64_0.CRCIN44
TCELL2:IMUX.IMUX14	CRC32_0.CRCIN11, CRC64_0.CRCIN43
TCELL2:IMUX.IMUX15	CRC32_0.CRCIN10, CRC64_0.CRCIN42
TCELL2:IMUX.IMUX16	CRC32_0.CRCIN9, CRC64_0.CRCIN41
TCELL2:IMUX.IMUX17	CRC32_0.CRCIN8, CRC64_0.CRCIN40
TCELL2:IMUX.IMUX20	GTX_DUAL.TXCHARDISPMODE11
TCELL2:IMUX.IMUX21	GTX_DUAL.TXCHARDISPVAL11
TCELL2:IMUX.IMUX24	GTX_DUAL.TXBYPASS8B10B11
TCELL2:IMUX.IMUX25	GTX_DUAL.TXCHARISK11
TCELL2:IMUX.IMUX27	GTX_DUAL.TXDATA127
TCELL2:IMUX.IMUX28	GTX_DUAL.TXCHARDISPVAL13
TCELL2:IMUX.IMUX30	GTX_DUAL.TXDATA124
TCELL2:IMUX.IMUX31	GTX_DUAL.TXDATA125
TCELL2:IMUX.IMUX32	GTX_DUAL.TXDATA18
TCELL2:IMUX.IMUX33	GTX_DUAL.TXDATA19
TCELL2:IMUX.IMUX34	GTX_DUAL.TXDATA110
TCELL2:IMUX.IMUX35	GTX_DUAL.TXDATA111
TCELL2:IMUX.IMUX36	CRC32_0.CRCIN15, CRC64_0.CRCIN47
TCELL2:IMUX.IMUX37	CRC32_0.CRCIN14, CRC64_0.CRCIN46
TCELL2:IMUX.IMUX38	GTX_DUAL.TXDATA126
TCELL2:IMUX.IMUX39	GTX_DUAL.TXCHARISK13
TCELL2:IMUX.IMUX40	GTX_DUAL.TXCHARDISPMODE13
TCELL2:IMUX.IMUX42	GTX_DUAL.TXPOWERDOWN11
TCELL2:IMUX.IMUX43	GTX_DUAL.TXPOWERDOWN10
TCELL2:OUT1	CRC32_0.CRCOUT9, CRC64_0.CRCOUT9
TCELL2:OUT2	GTX_DUAL.RXELECIDLE1
TCELL2:OUT3	GTX_DUAL.RXCHARISCOMMA13
TCELL2:OUT4	GTX_DUAL.RXNOTINTABLE13
TCELL2:OUT5	GTX_DUAL.TXRUNDISP11
TCELL2:OUT6	CRC32_0.CRCOUT4, CRC64_0.CRCOUT4
TCELL2:OUT7	GTX_DUAL.RXDATA125
TCELL2:OUT10	GTX_DUAL.TXKERR13
TCELL2:OUT11	GTX_DUAL.RXDATA124
TCELL2:OUT12	CRC32_0.CRCOUT11, CRC64_0.CRCOUT11
TCELL2:OUT13	CRC32_0.CRCOUT8, CRC64_0.CRCOUT8
TCELL2:OUT14	CRC32_0.CRCOUT6, CRC64_0.CRCOUT6
TCELL2:OUT15	GTX_DUAL.TXKERR11
TCELL2:OUT16	GTX_DUAL.RXDATA126
TCELL2:OUT17	GTX_DUAL.RXDISPERR12
TCELL2:OUT18	GTX_DUAL.RXRUNDISP13
TCELL2:OUT19	GTX_DUAL.RXDATA127
TCELL2:OUT20	CRC32_0.CRCOUT5, CRC64_0.CRCOUT5
TCELL2:OUT21	CRC32_0.CRCOUT3, CRC64_0.CRCOUT3
TCELL2:OUT22	CRC32_0.CRCOUT10, CRC64_0.CRCOUT10
TCELL2:OUT23	CRC32_0.CRCOUT7, CRC64_0.CRCOUT7
TCELL3:IMUX.IMUX0	GTX_DUAL.TXRESET1
TCELL3:IMUX.IMUX1	GTX_DUAL.TXINHIBIT1
TCELL3:IMUX.IMUX4	GTX_DUAL.TXDATAWIDTH10
TCELL3:IMUX.IMUX5	GTX_DUAL.TXDATAWIDTH11
TCELL3:IMUX.IMUX7	GTX_DUAL.TXHEADER12
TCELL3:IMUX.IMUX8	GTX_DUAL.TXSTARTSEQ1
TCELL3:IMUX.IMUX9	GTX_DUAL.TXHEADER10
TCELL3:IMUX.IMUX12	CRC32_0.CRCIN5, CRC64_0.CRCIN37
TCELL3:IMUX.IMUX13	CRC32_0.CRCIN4, CRC64_0.CRCIN36
TCELL3:IMUX.IMUX14	CRC32_0.CRCIN3, CRC64_0.CRCIN35
TCELL3:IMUX.IMUX15	CRC32_0.CRCIN2, CRC64_0.CRCIN34
TCELL3:IMUX.IMUX16	CRC32_0.CRCIN1, CRC64_0.CRCIN33
TCELL3:IMUX.IMUX17	CRC32_0.CRCIN0, CRC64_0.CRCIN32
TCELL3:IMUX.IMUX20	GTX_DUAL.TXHEADER11
TCELL3:IMUX.IMUX21	CRC32_0.CRCDATAWIDTH2, CRC32_1.CRCDATAWIDTH2, CRC64_0.CRCDATAWIDTH2
TCELL3:IMUX.IMUX22	CRC32_0.CRCDATAVALID, CRC64_0.CRCDATAVALID
TCELL3:IMUX.IMUX23	CRC32_0.CRCDATAWIDTH1, CRC64_0.CRCDATAWIDTH1
TCELL3:IMUX.IMUX30	GTX_DUAL.TXDATA128
TCELL3:IMUX.IMUX31	GTX_DUAL.TXDATA129
TCELL3:IMUX.IMUX32	GTX_DUAL.TXDATA112
TCELL3:IMUX.IMUX33	GTX_DUAL.TXDATA113
TCELL3:IMUX.IMUX34	GTX_DUAL.TXDATA114
TCELL3:IMUX.IMUX35	GTX_DUAL.TXDATA115
TCELL3:IMUX.IMUX36	CRC32_0.CRCIN7, CRC64_0.CRCIN39
TCELL3:IMUX.IMUX37	CRC32_0.CRCIN6, CRC64_0.CRCIN38
TCELL3:IMUX.IMUX38	GTX_DUAL.TXDATA130
TCELL3:IMUX.IMUX39	GTX_DUAL.TXDATA131
TCELL3:IMUX.IMUX40	CRC32_0.CRCDATAWIDTH0, CRC64_0.CRCDATAWIDTH0
TCELL3:IMUX.IMUX47	GTX_DUAL.TXENC8B10BUSE1
TCELL3:OUT0	GTX_DUAL.RXSTATUS11
TCELL3:OUT2	GTX_DUAL.RXCLKCORCNT10
TCELL3:OUT4	CRC32_0.CRCOUT1, CRC64_0.CRCOUT1
TCELL3:OUT5	GTX_DUAL.RXDATA122
TCELL3:OUT6	CRC32_0.CRCOUT0, CRC64_0.CRCOUT0
TCELL3:OUT7	GTX_DUAL.RXCHARISCOMMA12
TCELL3:OUT8	GTX_DUAL.RXSTATUS12
TCELL3:OUT9	GTX_DUAL.RXCLKCORCNT12
TCELL3:OUT10	GTX_DUAL.RXCLKCORCNT11
TCELL3:OUT11	GTX_DUAL.RXPRBSERR1
TCELL3:OUT12	GTX_DUAL.RXCHARISK12
TCELL3:OUT14	GTX_DUAL.RXDATA120
TCELL3:OUT16	GTX_DUAL.RXDATA119
TCELL3:OUT17	GTX_DUAL.RXNOTINTABLE12
TCELL3:OUT18	CRC32_0.CRCOUT2, CRC64_0.CRCOUT2
TCELL3:OUT19	GTX_DUAL.RXSTATUS10
TCELL3:OUT20	GTX_DUAL.RXRUNDISP12
TCELL3:OUT21	GTX_DUAL.TXRUNDISP13
TCELL3:OUT22	GTX_DUAL.RXDATA123
TCELL3:OUT23	GTX_DUAL.RXDATA121
TCELL4:IMUX.IMUX0	GTX_DUAL.RXPOLARITY1
TCELL4:IMUX.IMUX1	GTX_DUAL.RXENPCOMMAALIGN1
TCELL4:IMUX.IMUX2	GTX_DUAL.RXENMCOMMAALIGN1
TCELL4:IMUX.IMUX3	GTX_DUAL.RXSLIDE1
TCELL4:IMUX.IMUX5	GTX_DUAL.RXENEQB1
TCELL4:IMUX.IMUX10	GTX_DUAL.RXDATAWIDTH10
TCELL4:IMUX.IMUX14	GTX_DUAL.TXBYPASS8B10B13
TCELL4:IMUX.IMUX15	GTX_DUAL.RXDATAWIDTH11
TCELL4:IMUX.IMUX17	GTX_DUAL.RXCOMMADETUSE1
TCELL4:IMUX.IMUX20	GTX_DUAL.TXBYPASS8B10B12
TCELL4:IMUX.IMUX22	GTX_DUAL.RXGEARBOXSLIP1
TCELL4:IMUX.IMUX24	GTX_DUAL.RXENPRBSTST11
TCELL4:IMUX.IMUX25	GTX_DUAL.RXENPRBSTST10
TCELL4:IMUX.IMUX27	GTX_DUAL.DFECLKDLYADJ13
TCELL4:IMUX.IMUX29	GTX_DUAL.DFECLKDLYADJ11
TCELL4:IMUX.IMUX31	GTX_DUAL.DFECLKDLYADJ15
TCELL4:IMUX.IMUX32	GTX_DUAL.DFECLKDLYADJ14
TCELL4:IMUX.IMUX33	GTX_DUAL.RXENSAMPLEALIGN1
TCELL4:IMUX.IMUX34	GTX_DUAL.DFECLKDLYADJ12
TCELL4:IMUX.IMUX36	CRC32_1.CRCIN31, CRC64_0.CRCIN31
TCELL4:IMUX.IMUX37	CRC32_1.CRCIN30, CRC64_0.CRCIN30
TCELL4:IMUX.IMUX42	CRC32_1.CRCIN29, CRC64_0.CRCIN29
TCELL4:IMUX.IMUX43	CRC32_1.CRCIN28, CRC64_0.CRCIN28
TCELL4:IMUX.IMUX44	CRC32_1.CRCIN27, CRC64_0.CRCIN27
TCELL4:IMUX.IMUX45	CRC32_1.CRCIN26, CRC64_0.CRCIN26
TCELL4:IMUX.IMUX46	CRC32_1.CRCIN25, CRC64_0.CRCIN25
TCELL4:IMUX.IMUX47	CRC32_1.CRCIN24, CRC64_0.CRCIN24
TCELL4:OUT0	GTX_DUAL.RESETDONE1
TCELL4:OUT1	GTX_DUAL.DFECLKDLYADJMONITOR15
TCELL4:OUT2	GTX_DUAL.RXDATA12
TCELL4:OUT3	GTX_DUAL.DFECLKDLYADJMONITOR12
TCELL4:OUT4	GTX_DUAL.RXOVERSAMPLEERR1
TCELL4:OUT6	GTX_DUAL.RXBUFSTATUS10
TCELL4:OUT7	GTX_DUAL.DFECLKDLYADJMONITOR11
TCELL4:OUT9	GTX_DUAL.RXDATA10
TCELL4:OUT10	GTX_DUAL.RXDATA11
TCELL4:OUT11	GTX_DUAL.RXDATA13
TCELL4:OUT12	GTX_DUAL.RXDATA118
TCELL4:OUT13	GTX_DUAL.DFECLKDLYADJMONITOR14
TCELL4:OUT14	GTX_DUAL.DFECLKDLYADJMONITOR13
TCELL4:OUT15	GTX_DUAL.DFECLKDLYADJMONITOR10
TCELL4:OUT16	GTX_DUAL.RXBUFSTATUS11
TCELL4:OUT17	GTX_DUAL.PHYSTATUS1
TCELL4:OUT18	GTX_DUAL.RXDATA117
TCELL4:OUT19	GTX_DUAL.RXBUFSTATUS12
TCELL4:OUT21	CRC32_1.CRCOUT31
TCELL4:OUT22	GTX_DUAL.RXDATA116
TCELL5:IMUX.IMUX0	GTX_DUAL.RXEQMIX11
TCELL5:IMUX.IMUX1	GTX_DUAL.RXEQMIX10
TCELL5:IMUX.IMUX2	GTX_DUAL.RXEQPOLE13
TCELL5:IMUX.IMUX3	GTX_DUAL.RXEQPOLE12
TCELL5:IMUX.IMUX4	GTX_DUAL.RXEQPOLE11
TCELL5:IMUX.IMUX5	GTX_DUAL.RXEQPOLE10
TCELL5:IMUX.IMUX11	GTX_DUAL.DFETAP211
TCELL5:IMUX.IMUX12	GTX_DUAL.DFETAP114
TCELL5:IMUX.IMUX13	GTX_DUAL.GTXTEST9
TCELL5:IMUX.IMUX20	GTX_DUAL.DFETAP214
TCELL5:IMUX.IMUX22	GTX_DUAL.DFETAP212
TCELL5:IMUX.IMUX24	GTX_DUAL.DFECLKDLYADJ10
TCELL5:IMUX.IMUX25	GTX_DUAL.DFETAP113
TCELL5:IMUX.IMUX26	GTX_DUAL.DFETAP112
TCELL5:IMUX.IMUX27	GTX_DUAL.DFETAP213
TCELL5:IMUX.IMUX28	GTX_DUAL.DFETAP110
TCELL5:IMUX.IMUX29	GTX_DUAL.DFETAP210
TCELL5:IMUX.IMUX33	GTX_DUAL.DFETAP111
TCELL5:IMUX.IMUX36	CRC32_1.CRCIN23, CRC64_0.CRCIN23
TCELL5:IMUX.IMUX37	CRC32_1.CRCIN22, CRC64_0.CRCIN22
TCELL5:IMUX.IMUX42	CRC32_1.CRCIN21, CRC64_0.CRCIN21
TCELL5:IMUX.IMUX43	CRC32_1.CRCIN20, CRC64_0.CRCIN20
TCELL5:IMUX.IMUX44	CRC32_1.CRCIN19, CRC64_0.CRCIN19
TCELL5:IMUX.IMUX45	CRC32_1.CRCIN18, CRC64_0.CRCIN18
TCELL5:IMUX.IMUX46	CRC32_1.CRCIN17, CRC64_0.CRCIN17
TCELL5:IMUX.IMUX47	CRC32_1.CRCIN16, CRC64_0.CRCIN16
TCELL5:OUT0	GTX_DUAL.RXBYTEISALIGNED1
TCELL5:OUT2	GTX_DUAL.RXDATA16
TCELL5:OUT4	GTX_DUAL.RXNOTINTABLE10
TCELL5:OUT5	CRC32_1.CRCOUT29
TCELL5:OUT6	GTX_DUAL.RXRUNDISP10
TCELL5:OUT7	CRC32_1.CRCOUT28
TCELL5:OUT8	GTX_DUAL.RXCOMMADET1
TCELL5:OUT9	GTX_DUAL.RXDATA14
TCELL5:OUT10	GTX_DUAL.RXDATA15
TCELL5:OUT11	GTX_DUAL.RXDATA17
TCELL5:OUT12	GTX_DUAL.DFEEYEDACMONITOR14
TCELL5:OUT13	GTX_DUAL.DFEEYEDACMONITOR13
TCELL5:OUT14	GTX_DUAL.DFEEYEDACMONITOR12
TCELL5:OUT15	GTX_DUAL.DFEEYEDACMONITOR11
TCELL5:OUT16	GTX_DUAL.RXCHARISK10
TCELL5:OUT17	GTX_DUAL.RXCHARISCOMMA10
TCELL5:OUT18	GTX_DUAL.RXBYTEREALIGN1
TCELL5:OUT19	GTX_DUAL.RXDISPERR10
TCELL5:OUT21	CRC32_1.CRCOUT27
TCELL5:OUT22	CRC32_1.CRCOUT30
TCELL6:IMUX.CLK1	CRC32_1.CRCCLK
TCELL6:IMUX.IMUX1	GTX_DUAL.RXCHBONDI12
TCELL6:IMUX.IMUX2	GTX_DUAL.RXCHBONDI11
TCELL6:IMUX.IMUX3	GTX_DUAL.RXCHBONDI10
TCELL6:IMUX.IMUX6	GTX_DUAL.RXDEC8B10BUSE1
TCELL6:IMUX.IMUX11	GTX_DUAL.DFETAP413
TCELL6:IMUX.IMUX12	GTX_DUAL.TSTPWRDN14
TCELL6:IMUX.IMUX13	GTX_DUAL.TSTPWRDN13
TCELL6:IMUX.IMUX14	GTX_DUAL.TSTPWRDN12
TCELL6:IMUX.IMUX15	GTX_DUAL.TSTPWRDN11
TCELL6:IMUX.IMUX16	GTX_DUAL.TSTPWRDN10
TCELL6:IMUX.IMUX23	GTX_DUAL.RXCHBONDI13
TCELL6:IMUX.IMUX24	GTX_DUAL.RXENCHANSYNC1
TCELL6:IMUX.IMUX31	GTX_DUAL.DFETAP313
TCELL6:IMUX.IMUX32	GTX_DUAL.DFETAP312
TCELL6:IMUX.IMUX34	GTX_DUAL.DFETAP310
TCELL6:IMUX.IMUX36	CRC32_1.CRCIN15, CRC64_0.CRCIN15
TCELL6:IMUX.IMUX37	CRC32_1.CRCIN14, CRC64_0.CRCIN14
TCELL6:IMUX.IMUX39	GTX_DUAL.DFETAP311
TCELL6:IMUX.IMUX42	CRC32_1.CRCIN13, CRC64_0.CRCIN13
TCELL6:IMUX.IMUX43	CRC32_1.CRCIN12, CRC64_0.CRCIN12
TCELL6:IMUX.IMUX44	CRC32_1.CRCIN11, CRC64_0.CRCIN11
TCELL6:IMUX.IMUX45	CRC32_1.CRCIN10, CRC64_0.CRCIN10
TCELL6:IMUX.IMUX46	CRC32_1.CRCIN9, CRC64_0.CRCIN9
TCELL6:IMUX.IMUX47	CRC32_1.CRCIN8, CRC64_0.CRCIN8
TCELL6:OUT0	GTX_DUAL.RXVALID1
TCELL6:OUT2	GTX_DUAL.RXDATA110
TCELL6:OUT4	GTX_DUAL.RXNOTINTABLE11
TCELL6:OUT5	GTX_DUAL.DFETAP1MONITOR14
TCELL6:OUT6	GTX_DUAL.RXRUNDISP11
TCELL6:OUT7	GTX_DUAL.DFETAP1MONITOR12
TCELL6:OUT8	GTX_DUAL.RXLOSSOFSYNC11
TCELL6:OUT9	GTX_DUAL.RXDATA18
TCELL6:OUT10	GTX_DUAL.RXDATA19
TCELL6:OUT11	GTX_DUAL.RXDATA111
TCELL6:OUT12	CRC32_1.CRCOUT26
TCELL6:OUT14	CRC32_1.CRCOUT25
TCELL6:OUT15	CRC32_1.CRCOUT24
TCELL6:OUT16	GTX_DUAL.RXCHARISK11
TCELL6:OUT17	GTX_DUAL.RXCHARISCOMMA11
TCELL6:OUT18	GTX_DUAL.DFEEYEDACMONITOR10
TCELL6:OUT19	GTX_DUAL.RXDISPERR11
TCELL6:OUT21	GTX_DUAL.DFETAP1MONITOR11
TCELL6:OUT22	GTX_DUAL.RXLOSSOFSYNC10
TCELL6:OUT23	GTX_DUAL.DFETAP1MONITOR13
TCELL7:IMUX.CLK1	GTX_DUAL.DCLK
TCELL7:IMUX.IMUX0	GTX_DUAL.RXCDRRESET1
TCELL7:IMUX.IMUX4	GTX_DUAL.RXBUFRESET1
TCELL7:IMUX.IMUX5	GTX_DUAL.RXRESET1
TCELL7:IMUX.IMUX8	GTX_DUAL.RXPOWERDOWN11
TCELL7:IMUX.IMUX9	GTX_DUAL.RXPOWERDOWN10
TCELL7:IMUX.IMUX18	GTX_DUAL.LOOPBACK12
TCELL7:IMUX.IMUX19	GTX_DUAL.LOOPBACK11
TCELL7:IMUX.IMUX20	GTX_DUAL.LOOPBACK10
TCELL7:IMUX.IMUX24	GTX_DUAL.DFETAP412
TCELL7:IMUX.IMUX25	GTX_DUAL.DFETAP411
TCELL7:IMUX.IMUX28	GTX_DUAL.DFETAP410
TCELL7:IMUX.IMUX34	GTX_DUAL.RXENPMAPHASEALIGN1
TCELL7:IMUX.IMUX36	CRC32_1.CRCIN7, CRC64_0.CRCIN7
TCELL7:IMUX.IMUX37	CRC32_1.CRCIN6, CRC64_0.CRCIN6
TCELL7:IMUX.IMUX40	GTX_DUAL.RXPMASETPHASE1
TCELL7:IMUX.IMUX42	CRC32_1.CRCIN5, CRC64_0.CRCIN5
TCELL7:IMUX.IMUX43	CRC32_1.CRCIN4, CRC64_0.CRCIN4
TCELL7:IMUX.IMUX44	CRC32_1.CRCIN3, CRC64_0.CRCIN3
TCELL7:IMUX.IMUX45	CRC32_1.CRCIN2, CRC64_0.CRCIN2
TCELL7:IMUX.IMUX46	CRC32_1.CRCIN1, CRC64_0.CRCIN1
TCELL7:IMUX.IMUX47	CRC32_1.CRCIN0, CRC64_0.CRCIN0
TCELL7:OUT0	GTX_DUAL.RXCHBONDO11
TCELL7:OUT1	GTX_DUAL.DFETAP2MONITOR14
TCELL7:OUT2	GTX_DUAL.RXDATA114
TCELL7:OUT3	CRC32_1.CRCOUT22
TCELL7:OUT4	GTX_DUAL.RXCHANREALIGN1
TCELL7:OUT5	GTX_DUAL.RXCHBONDO13
TCELL7:OUT6	GTX_DUAL.RXCHANBONDSEQ1
TCELL7:OUT7	GTX_DUAL.SCANOUTPCS1
TCELL7:OUT8	GTX_DUAL.RXCHBONDO12
TCELL7:OUT9	GTX_DUAL.RXDATA112
TCELL7:OUT10	GTX_DUAL.RXDATA113
TCELL7:OUT11	GTX_DUAL.RXDATA115
TCELL7:OUT12	CRC32_1.CRCOUT23
TCELL7:OUT13	GTX_DUAL.DFETAP2MONITOR13
TCELL7:OUT14	GTX_DUAL.DFETAP2MONITOR12
TCELL7:OUT16	GTX_DUAL.DFETAP2MONITOR11
TCELL7:OUT17	CRC32_1.CRCOUT21
TCELL7:OUT18	GTX_DUAL.RXCHANISALIGNED1
TCELL7:OUT19	GTX_DUAL.RXCHBONDO10
TCELL7:OUT20	GTX_DUAL.RXRECCLK1
TCELL7:OUT21	CRC32_1.CRCOUT20
TCELL7:OUT22	GTX_DUAL.DFETAP1MONITOR10
TCELL8:IMUX.CLK0	GTX_DUAL.TXUSRCLK21
TCELL8:IMUX.CLK1	GTX_DUAL.TXUSRCLK1
TCELL8:IMUX.IMUX0	CRC32_1.CRCRESET
TCELL8:IMUX.IMUX2	GTX_DUAL.PRBSCNTRESET1
TCELL8:IMUX.IMUX11	CRC32_1.CRCDATAWIDTH0
TCELL8:IMUX.IMUX34	CRC32_1.CRCDATAWIDTH1
TCELL8:IMUX.IMUX35	CRC32_1.CRCDATAVALID
TCELL8:IMUX.IMUX44	GTX_DUAL.DI15
TCELL8:IMUX.IMUX45	GTX_DUAL.DI14
TCELL8:IMUX.IMUX46	GTX_DUAL.DI13
TCELL8:IMUX.IMUX47	GTX_DUAL.DI12
TCELL8:OUT0	CRC32_1.CRCOUT19
TCELL8:OUT1	GTX_DUAL.SCANOUTPCSCOMMON
TCELL8:OUT2	CRC32_1.CRCOUT13
TCELL8:OUT4	GTX_DUAL.DFETAP3MONITOR13
TCELL8:OUT5	CRC32_1.CRCOUT18
TCELL8:OUT6	CRC32_1.CRCOUT12
TCELL8:OUT7	GTX_DUAL.DFETAP3MONITOR11
TCELL8:OUT8	GTX_DUAL.DO15
TCELL8:OUT9	CRC32_1.CRCOUT17
TCELL8:OUT10	CRC32_1.CRCOUT15
TCELL8:OUT11	CRC32_1.CRCOUT11
TCELL8:OUT12	GTX_DUAL.DO14
TCELL8:OUT13	GTX_DUAL.DO12
TCELL8:OUT15	CRC32_1.CRCOUT10
TCELL8:OUT16	CRC32_1.CRCOUT14
TCELL8:OUT17	CRC32_1.CRCOUT9
TCELL8:OUT18	GTX_DUAL.DO13
TCELL8:OUT20	GTX_DUAL.DFETAP3MONITOR12
TCELL8:OUT21	GTX_DUAL.DFETAP3MONITOR10
TCELL8:OUT22	GTX_DUAL.DFETAP2MONITOR10
TCELL8:OUT23	CRC32_1.CRCOUT16
TCELL9:IMUX.CLK0	GTX_DUAL.RXUSRCLK21
TCELL9:IMUX.CLK1	GTX_DUAL.RXUSRCLK1
TCELL9:IMUX.IMUX3	GTX_DUAL.PMAAMUX0
TCELL9:IMUX.IMUX4	GTX_DUAL.PMAAMUX1
TCELL9:IMUX.IMUX5	GTX_DUAL.PMAAMUX2
TCELL9:IMUX.IMUX8	GTX_DUAL.PLLLKDETEN
TCELL9:IMUX.IMUX16	GTX_DUAL.GTXTEST2
TCELL9:IMUX.IMUX17	GTX_DUAL.GTXTEST3
TCELL9:IMUX.IMUX18	GTX_DUAL.REFCLKPWRDNB
TCELL9:IMUX.IMUX19	GTX_DUAL.DWE
TCELL9:IMUX.IMUX20	GTX_DUAL.TXENPMAPHASEALIGN1
TCELL9:IMUX.IMUX26	GTX_DUAL.DADDR6
TCELL9:IMUX.IMUX27	GTX_DUAL.DADDR5
TCELL9:IMUX.IMUX28	GTX_DUAL.DADDR4
TCELL9:IMUX.IMUX29	GTX_DUAL.DADDR3
TCELL9:IMUX.IMUX33	GTX_DUAL.TXPMASETPHASE1
TCELL9:IMUX.IMUX42	GTX_DUAL.DI11
TCELL9:IMUX.IMUX43	GTX_DUAL.DI10
TCELL9:IMUX.IMUX44	GTX_DUAL.DI9
TCELL9:IMUX.IMUX45	GTX_DUAL.DI8
TCELL9:OUT0	CRC32_1.CRCOUT5
TCELL9:OUT2	GTX_DUAL.TXOUTCLK1
TCELL9:OUT3	CRC32_1.CRCOUT1
TCELL9:OUT4	CRC32_1.CRCOUT4
TCELL9:OUT5	GTX_DUAL.DFETAP4MONITOR13
TCELL9:OUT6	GTX_DUAL.DO9
TCELL9:OUT7	GTX_DUAL.DFESENSCAL10
TCELL9:OUT8	CRC32_1.CRCOUT8
TCELL9:OUT9	GTX_DUAL.DFESENSCAL11
TCELL9:OUT10	GTX_DUAL.DO11
TCELL9:OUT11	CRC32_1.CRCOUT0
TCELL9:OUT12	CRC32_1.CRCOUT7
TCELL9:OUT13	CRC32_1.CRCOUT3
TCELL9:OUT14	CRC32_1.CRCOUT2
TCELL9:OUT15	GTX_DUAL.DRDY
TCELL9:OUT16	GTX_DUAL.DFETAP4MONITOR11
TCELL9:OUT17	GTX_DUAL.DFETAP4MONITOR10
TCELL9:OUT18	CRC32_1.CRCOUT6
TCELL9:OUT19	GTX_DUAL.DFETAP4MONITOR12
TCELL9:OUT20	GTX_DUAL.DO10
TCELL9:OUT21	GTX_DUAL.DO8
TCELL9:OUT22	GTX_DUAL.DFESENSCAL12
TCELL9:OUT23	GTX_DUAL.PLLLKDET
TCELL10:IMUX.CLK0	GTX_DUAL.RXUSRCLK0
TCELL10:IMUX.CLK1	GTX_DUAL.RXUSRCLK20
TCELL10:IMUX.IMUX0	GTX_DUAL.DI7
TCELL10:IMUX.IMUX1	GTX_DUAL.DI6
TCELL10:IMUX.IMUX2	GTX_DUAL.DI5
TCELL10:IMUX.IMUX3	GTX_DUAL.DI4
TCELL10:IMUX.IMUX6	GTX_DUAL.INTDATAWIDTH
TCELL10:IMUX.IMUX12	GTX_DUAL.PMATSTCLKSEL2
TCELL10:IMUX.IMUX13	GTX_DUAL.PMATSTCLKSEL1
TCELL10:IMUX.IMUX14	GTX_DUAL.PMATSTCLKSEL0
TCELL10:IMUX.IMUX16	GTX_DUAL.TXENPMAPHASEALIGN0
TCELL10:IMUX.IMUX17	GTX_DUAL.TXPMASETPHASE0
TCELL10:IMUX.IMUX24	GTX_DUAL.DADDR2
TCELL10:IMUX.IMUX31	GTX_DUAL.DADDR1
TCELL10:IMUX.IMUX32	GTX_DUAL.DADDR0
TCELL10:IMUX.IMUX33	GTX_DUAL.GTXTEST13
TCELL10:IMUX.IMUX36	GTX_DUAL.PLLPOWERDOWN
TCELL10:IMUX.IMUX39	GTX_DUAL.DEN
TCELL10:IMUX.IMUX40	GTX_DUAL.GTXTEST8
TCELL10:OUT0	GTX_DUAL.DO6
TCELL10:OUT1	GTX_DUAL.DFETAP4MONITOR00
TCELL10:OUT2	CRC32_2.CRCOUT3
TCELL10:OUT3	GTX_DUAL.DFETAP4MONITOR03
TCELL10:OUT4	CRC32_2.CRCOUT0
TCELL10:OUT6	CRC32_2.CRCOUT4
TCELL10:OUT7	CRC32_2.CRCOUT5
TCELL10:OUT8	GTX_DUAL.REFCLKOUT
TCELL10:OUT9	GTX_DUAL.DO5
TCELL10:OUT10	GTX_DUAL.DO4
TCELL10:OUT11	CRC32_2.CRCOUT6
TCELL10:OUT12	GTX_DUAL.DO7
TCELL10:OUT13	GTX_DUAL.TXOUTCLK0
TCELL10:OUT14	GTX_DUAL.DFETAP4MONITOR01
TCELL10:OUT15	CRC32_2.CRCOUT7
TCELL10:OUT16	CRC32_2.CRCOUT2
TCELL10:OUT17	GTX_DUAL.DFESENSCAL02
TCELL10:OUT18	GTX_DUAL.DFESENSCAL00
TCELL10:OUT19	GTX_DUAL.DFESENSCAL01
TCELL10:OUT20	GTX_DUAL.DFETAP4MONITOR02
TCELL10:OUT21	CRC32_2.CRCOUT8
TCELL10:OUT22	GTX_DUAL.PMATSTCLK
TCELL10:OUT23	CRC32_2.CRCOUT1
TCELL11:IMUX.CLK0	GTX_DUAL.TXUSRCLK0
TCELL11:IMUX.CLK1	GTX_DUAL.TXUSRCLK20
TCELL11:IMUX.IMUX0	GTX_DUAL.DI3
TCELL11:IMUX.IMUX1	GTX_DUAL.DI2
TCELL11:IMUX.IMUX2	GTX_DUAL.DI1
TCELL11:IMUX.IMUX3	GTX_DUAL.DI0
TCELL11:IMUX.IMUX5	CRC32_2.CRCRESET
TCELL11:IMUX.IMUX13	CRC32_2.CRCDATAWIDTH1
TCELL11:IMUX.IMUX24	CRC32_2.CRCDATAWIDTH0
TCELL11:IMUX.IMUX29	GTX_DUAL.SCANINPCSCOMMON
TCELL11:IMUX.IMUX30	CRC32_2.CRCDATAVALID
TCELL11:IMUX.IMUX36	GTX_DUAL.GTXRESET
TCELL11:IMUX.IMUX45	GTX_DUAL.PRBSCNTRESET0
TCELL11:OUT1	GTX_DUAL.DFETAP3MONITOR02
TCELL11:OUT3	CRC32_2.CRCOUT18
TCELL11:OUT4	CRC32_2.CRCOUT10
TCELL11:OUT5	CRC32_2.CRCOUT12
TCELL11:OUT7	CRC32_2.CRCOUT19
TCELL11:OUT8	GTX_DUAL.DFETAP3MONITOR00
TCELL11:OUT10	CRC32_2.CRCOUT16
TCELL11:OUT11	GTX_DUAL.DFETAP3MONITOR03
TCELL11:OUT12	CRC32_2.CRCOUT9
TCELL11:OUT13	CRC32_2.CRCOUT13
TCELL11:OUT14	GTX_DUAL.DO3
TCELL11:OUT15	GTX_DUAL.DO2
TCELL11:OUT16	CRC32_2.CRCOUT17
TCELL11:OUT17	GTX_DUAL.DO1
TCELL11:OUT18	GTX_DUAL.DFETAP3MONITOR01
TCELL11:OUT19	CRC32_2.CRCOUT14
TCELL11:OUT21	GTX_DUAL.DO0
TCELL11:OUT22	CRC32_2.CRCOUT11
TCELL11:OUT23	CRC32_2.CRCOUT15
TCELL12:IMUX.CLK0	GTX_DUAL.GREFCLK
TCELL12:IMUX.IMUX0	CRC32_2.CRCIN0, CRC64_1.CRCIN0
TCELL12:IMUX.IMUX1	CRC32_2.CRCIN1, CRC64_1.CRCIN1
TCELL12:IMUX.IMUX2	CRC32_2.CRCIN2, CRC64_1.CRCIN2
TCELL12:IMUX.IMUX7	GTX_DUAL.RXPMASETPHASE0
TCELL12:IMUX.IMUX9	CRC32_2.CRCIN3, CRC64_1.CRCIN3
TCELL12:IMUX.IMUX10	CRC32_2.CRCIN6, CRC64_1.CRCIN6
TCELL12:IMUX.IMUX11	CRC32_2.CRCIN7, CRC64_1.CRCIN7
TCELL12:IMUX.IMUX13	GTX_DUAL.RXENPMAPHASEALIGN0
TCELL12:IMUX.IMUX15	GTX_DUAL.LOOPBACK00
TCELL12:IMUX.IMUX16	GTX_DUAL.LOOPBACK01
TCELL12:IMUX.IMUX17	GTX_DUAL.LOOPBACK02
TCELL12:IMUX.IMUX35	CRC32_2.CRCIN5, CRC64_1.CRCIN5
TCELL12:IMUX.IMUX37	GTX_DUAL.DFETAP400
TCELL12:IMUX.IMUX38	GTX_DUAL.RXPOWERDOWN00
TCELL12:IMUX.IMUX39	GTX_DUAL.RXPOWERDOWN01
TCELL12:IMUX.IMUX40	GTX_DUAL.DFETAP401
TCELL12:IMUX.IMUX41	GTX_DUAL.DFETAP402
TCELL12:IMUX.IMUX42	GTX_DUAL.RXRESET0
TCELL12:IMUX.IMUX43	GTX_DUAL.RXBUFRESET0
TCELL12:IMUX.IMUX45	CRC32_2.CRCIN4, CRC64_1.CRCIN4
TCELL12:IMUX.IMUX47	GTX_DUAL.RXCDRRESET0
TCELL12:OUT1	GTX_DUAL.RXCHANBONDSEQ0
TCELL12:OUT2	GTX_DUAL.DFETAP2MONITOR03
TCELL12:OUT3	GTX_DUAL.RXCHANREALIGN0
TCELL12:OUT4	CRC32_2.CRCOUT22
TCELL12:OUT5	GTX_DUAL.RXDATA014
TCELL12:OUT6	GTX_DUAL.DFETAP2MONITOR04
TCELL12:OUT7	GTX_DUAL.RXCHBONDO01
TCELL12:OUT8	CRC32_2.CRCOUT20
TCELL12:OUT10	GTX_DUAL.SCANOUTPCS0
TCELL12:OUT11	GTX_DUAL.RXCHBONDO03
TCELL12:OUT12	GTX_DUAL.DFETAP2MONITOR00
TCELL12:OUT13	GTX_DUAL.RXRECCLK0
TCELL12:OUT14	GTX_DUAL.RXCHBONDO00
TCELL12:OUT15	GTX_DUAL.RXCHANISALIGNED0
TCELL12:OUT16	GTX_DUAL.DFETAP2MONITOR02
TCELL12:OUT17	CRC32_2.CRCOUT23
TCELL12:OUT18	CRC32_2.CRCOUT21
TCELL12:OUT19	GTX_DUAL.DFETAP2MONITOR01
TCELL12:OUT20	GTX_DUAL.RXDATA012
TCELL12:OUT21	GTX_DUAL.RXCHBONDO02
TCELL12:OUT22	GTX_DUAL.RXDATA015
TCELL12:OUT23	GTX_DUAL.RXDATA013
TCELL13:IMUX.CLK0	CRC32_2.CRCCLK
TCELL13:IMUX.IMUX4	CRC32_2.CRCIN12, CRC64_1.CRCIN12
TCELL13:IMUX.IMUX5	CRC32_2.CRCIN13, CRC64_1.CRCIN13
TCELL13:IMUX.IMUX6	CRC32_2.CRCIN8, CRC64_1.CRCIN8
TCELL13:IMUX.IMUX7	CRC32_2.CRCIN9, CRC64_1.CRCIN9
TCELL13:IMUX.IMUX8	CRC32_2.CRCIN10, CRC64_1.CRCIN10
TCELL13:IMUX.IMUX9	CRC32_2.CRCIN11, CRC64_1.CRCIN11
TCELL13:IMUX.IMUX10	CRC32_2.CRCIN14, CRC64_1.CRCIN14
TCELL13:IMUX.IMUX11	CRC32_2.CRCIN15, CRC64_1.CRCIN15
TCELL13:IMUX.IMUX23	GTX_DUAL.RXENCHANSYNC0
TCELL13:IMUX.IMUX25	GTX_DUAL.DFETAP300
TCELL13:IMUX.IMUX26	GTX_DUAL.DFETAP301
TCELL13:IMUX.IMUX27	GTX_DUAL.DFETAP302
TCELL13:IMUX.IMUX28	GTX_DUAL.DFETAP303
TCELL13:IMUX.IMUX31	GTX_DUAL.TSTPWRDN00
TCELL13:IMUX.IMUX32	GTX_DUAL.TSTPWRDN01
TCELL13:IMUX.IMUX33	GTX_DUAL.TSTPWRDN02
TCELL13:IMUX.IMUX34	GTX_DUAL.TSTPWRDN03
TCELL13:IMUX.IMUX35	GTX_DUAL.TSTPWRDN04
TCELL13:IMUX.IMUX36	GTX_DUAL.DFETAP403
TCELL13:IMUX.IMUX41	GTX_DUAL.RXDEC8B10BUSE0
TCELL13:IMUX.IMUX43	GTX_DUAL.RXCHBONDI03
TCELL13:IMUX.IMUX44	GTX_DUAL.RXCHBONDI00
TCELL13:IMUX.IMUX45	GTX_DUAL.RXCHBONDI01
TCELL13:IMUX.IMUX46	GTX_DUAL.RXCHBONDI02
TCELL13:OUT0	GTX_DUAL.DFETAP1MONITOR01
TCELL13:OUT1	GTX_DUAL.RXRUNDISP01
TCELL13:OUT3	GTX_DUAL.RXNOTINTABLE01
TCELL13:OUT5	GTX_DUAL.RXDATA010
TCELL13:OUT6	GTX_DUAL.DFETAP1MONITOR03
TCELL13:OUT7	GTX_DUAL.RXVALID0
TCELL13:OUT8	GTX_DUAL.DFETAP1MONITOR00
TCELL13:OUT11	GTX_DUAL.RXLOSSOFSYNC00
TCELL13:OUT12	GTX_DUAL.RXCHARISCOMMA01
TCELL13:OUT13	GTX_DUAL.RXCHARISK01
TCELL13:OUT14	GTX_DUAL.RXDISPERR01
TCELL13:OUT15	GTX_DUAL.DFETAP1MONITOR04
TCELL13:OUT16	GTX_DUAL.DFETAP1MONITOR02
TCELL13:OUT17	CRC32_2.CRCOUT26
TCELL13:OUT18	CRC32_2.CRCOUT24
TCELL13:OUT19	CRC32_2.CRCOUT25
TCELL13:OUT20	GTX_DUAL.RXDATA08
TCELL13:OUT21	GTX_DUAL.RXLOSSOFSYNC01
TCELL13:OUT22	GTX_DUAL.RXDATA011
TCELL13:OUT23	GTX_DUAL.RXDATA09
TCELL14:IMUX.IMUX4	CRC32_2.CRCIN20, CRC64_1.CRCIN20
TCELL14:IMUX.IMUX5	CRC32_2.CRCIN21, CRC64_1.CRCIN21
TCELL14:IMUX.IMUX6	CRC32_2.CRCIN16, CRC64_1.CRCIN16
TCELL14:IMUX.IMUX7	CRC32_2.CRCIN17, CRC64_1.CRCIN17
TCELL14:IMUX.IMUX8	CRC32_2.CRCIN18, CRC64_1.CRCIN18
TCELL14:IMUX.IMUX9	CRC32_2.CRCIN19, CRC64_1.CRCIN19
TCELL14:IMUX.IMUX10	CRC32_2.CRCIN22, CRC64_1.CRCIN22
TCELL14:IMUX.IMUX11	CRC32_2.CRCIN23, CRC64_1.CRCIN23
TCELL14:IMUX.IMUX12	GTX_DUAL.DFETAP200
TCELL14:IMUX.IMUX22	GTX_DUAL.GTXTEST4
TCELL14:IMUX.IMUX23	GTX_DUAL.DFECLKDLYADJ00
TCELL14:IMUX.IMUX26	GTX_DUAL.DFETAP101
TCELL14:IMUX.IMUX31	GTX_DUAL.DFETAP100
TCELL14:IMUX.IMUX33	GTX_DUAL.DFETAP102
TCELL14:IMUX.IMUX34	GTX_DUAL.DFETAP103
TCELL14:IMUX.IMUX35	GTX_DUAL.DFETAP104
TCELL14:IMUX.IMUX36	GTX_DUAL.DFETAP201
TCELL14:IMUX.IMUX37	GTX_DUAL.DFETAP202
TCELL14:IMUX.IMUX38	GTX_DUAL.DFETAP203
TCELL14:IMUX.IMUX39	GTX_DUAL.DFETAP204
TCELL14:IMUX.IMUX42	GTX_DUAL.RXEQPOLE00
TCELL14:IMUX.IMUX43	GTX_DUAL.RXEQPOLE01
TCELL14:IMUX.IMUX44	GTX_DUAL.RXEQPOLE02
TCELL14:IMUX.IMUX45	GTX_DUAL.RXEQPOLE03
TCELL14:IMUX.IMUX46	GTX_DUAL.RXEQMIX00
TCELL14:IMUX.IMUX47	GTX_DUAL.RXEQMIX01
TCELL14:OUT0	GTX_DUAL.DFEEYEDACMONITOR00
TCELL14:OUT1	GTX_DUAL.RXRUNDISP00
TCELL14:OUT2	GTX_DUAL.DFEEYEDACMONITOR03
TCELL14:OUT3	GTX_DUAL.RXNOTINTABLE00
TCELL14:OUT4	CRC32_2.CRCOUT28
TCELL14:OUT5	GTX_DUAL.RXDATA06
TCELL14:OUT6	CRC32_2.CRCOUT29
TCELL14:OUT7	GTX_DUAL.RXBYTEISALIGNED0
TCELL14:OUT12	GTX_DUAL.RXCHARISCOMMA00
TCELL14:OUT13	GTX_DUAL.RXCHARISK00
TCELL14:OUT14	GTX_DUAL.RXDISPERR00
TCELL14:OUT15	GTX_DUAL.RXBYTEREALIGN0
TCELL14:OUT16	GTX_DUAL.DFEEYEDACMONITOR02
TCELL14:OUT17	CRC32_2.CRCOUT30
TCELL14:OUT18	CRC32_2.CRCOUT27
TCELL14:OUT19	GTX_DUAL.DFEEYEDACMONITOR01
TCELL14:OUT20	GTX_DUAL.RXDATA04
TCELL14:OUT21	GTX_DUAL.RXCOMMADET0
TCELL14:OUT22	GTX_DUAL.RXDATA07
TCELL14:OUT23	GTX_DUAL.RXDATA05
TCELL15:IMUX.IMUX4	CRC32_2.CRCIN28, CRC64_1.CRCIN28
TCELL15:IMUX.IMUX5	CRC32_2.CRCIN29, CRC64_1.CRCIN29
TCELL15:IMUX.IMUX6	CRC32_2.CRCIN24, CRC64_1.CRCIN24
TCELL15:IMUX.IMUX7	CRC32_2.CRCIN25, CRC64_1.CRCIN25
TCELL15:IMUX.IMUX8	CRC32_2.CRCIN26, CRC64_1.CRCIN26
TCELL15:IMUX.IMUX9	CRC32_2.CRCIN27, CRC64_1.CRCIN27
TCELL15:IMUX.IMUX10	CRC32_2.CRCIN30, CRC64_1.CRCIN30
TCELL15:IMUX.IMUX11	CRC32_2.CRCIN31, CRC64_1.CRCIN31
TCELL15:IMUX.IMUX14	GTX_DUAL.RXENSAMPLEALIGN0
TCELL15:IMUX.IMUX17	GTX_DUAL.RXGEARBOXSLIP0
TCELL15:IMUX.IMUX18	GTX_DUAL.RXDATAWIDTH01
TCELL15:IMUX.IMUX19	GTX_DUAL.DFECLKDLYADJ02
TCELL15:IMUX.IMUX21	GTX_DUAL.TXBYPASS8B10B03
TCELL15:IMUX.IMUX27	GTX_DUAL.TXBYPASS8B10B02
TCELL15:IMUX.IMUX28	GTX_DUAL.RXENPRBSTST00
TCELL15:IMUX.IMUX29	GTX_DUAL.RXENPRBSTST01
TCELL15:IMUX.IMUX30	GTX_DUAL.RXCOMMADETUSE0
TCELL15:IMUX.IMUX36	GTX_DUAL.DFECLKDLYADJ01
TCELL15:IMUX.IMUX37	GTX_DUAL.RXDATAWIDTH00
TCELL15:IMUX.IMUX38	GTX_DUAL.DFECLKDLYADJ03
TCELL15:IMUX.IMUX39	GTX_DUAL.DFECLKDLYADJ04
TCELL15:IMUX.IMUX40	GTX_DUAL.DFECLKDLYADJ05
TCELL15:IMUX.IMUX41	GTX_DUAL.RXPOLARITY0
TCELL15:IMUX.IMUX42	GTX_DUAL.RXENEQB0
TCELL15:IMUX.IMUX44	GTX_DUAL.RXSLIDE0
TCELL15:IMUX.IMUX45	GTX_DUAL.RXENMCOMMAALIGN0
TCELL15:IMUX.IMUX46	GTX_DUAL.RXENPCOMMAALIGN0
TCELL15:OUT0	GTX_DUAL.DFECLKDLYADJMONITOR01
TCELL15:OUT1	GTX_DUAL.RXBUFSTATUS00
TCELL15:OUT3	GTX_DUAL.RXOVERSAMPLEERR0
TCELL15:OUT4	GTX_DUAL.DFECLKDLYADJMONITOR00
TCELL15:OUT5	GTX_DUAL.RXDATA02
TCELL15:OUT6	GTX_DUAL.DFECLKDLYADJMONITOR04
TCELL15:OUT7	GTX_DUAL.RESETDONE0
TCELL15:OUT8	GTX_DUAL.DFEEYEDACMONITOR04
TCELL15:OUT12	GTX_DUAL.PHYSTATUS0
TCELL15:OUT13	GTX_DUAL.RXBUFSTATUS01
TCELL15:OUT14	GTX_DUAL.RXBUFSTATUS02
TCELL15:OUT15	GTX_DUAL.DFECLKDLYADJMONITOR05
TCELL15:OUT16	GTX_DUAL.DFECLKDLYADJMONITOR03
TCELL15:OUT17	GTX_DUAL.RXDATA016
TCELL15:OUT18	CRC32_2.CRCOUT31
TCELL15:OUT19	GTX_DUAL.DFECLKDLYADJMONITOR02
TCELL15:OUT20	GTX_DUAL.RXDATA00
TCELL15:OUT21	GTX_DUAL.RXDATA017
TCELL15:OUT22	GTX_DUAL.RXDATA03
TCELL15:OUT23	GTX_DUAL.RXDATA01
TCELL16:IMUX.IMUX1	CRC32_3.CRCDATAWIDTH1, CRC64_1.CRCDATAWIDTH1
TCELL16:IMUX.IMUX4	GTX_DUAL.TXHEADER02
TCELL16:IMUX.IMUX6	CRC32_3.CRCDATAWIDTH0, CRC64_1.CRCDATAWIDTH0
TCELL16:IMUX.IMUX7	CRC32_3.CRCDATAVALID, CRC64_1.CRCDATAVALID
TCELL16:IMUX.IMUX8	CRC32_2.CRCDATAWIDTH2, CRC32_3.CRCDATAWIDTH2, CRC64_1.CRCDATAWIDTH2
TCELL16:IMUX.IMUX9	GTX_DUAL.TXSTARTSEQ0
TCELL16:IMUX.IMUX10	CRC32_3.CRCIN6, CRC64_1.CRCIN38
TCELL16:IMUX.IMUX11	CRC32_3.CRCIN7, CRC64_1.CRCIN39
TCELL16:IMUX.IMUX20	GTX_DUAL.TXDATA031
TCELL16:IMUX.IMUX21	GTX_DUAL.TXDATA030
TCELL16:IMUX.IMUX22	GTX_DUAL.TXDATA029
TCELL16:IMUX.IMUX23	GTX_DUAL.TXDATA028
TCELL16:IMUX.IMUX24	GTX_DUAL.TXDATAWIDTH01
TCELL16:IMUX.IMUX28	GTX_DUAL.TXINHIBIT0
TCELL16:IMUX.IMUX30	GTX_DUAL.TXENC8B10BUSE0
TCELL16:IMUX.IMUX31	GTX_DUAL.TXDATAWIDTH00
TCELL16:IMUX.IMUX32	GTX_DUAL.TXHEADER00
TCELL16:IMUX.IMUX33	GTX_DUAL.TXHEADER01
TCELL16:IMUX.IMUX35	CRC32_3.CRCIN5, CRC64_1.CRCIN37
TCELL16:IMUX.IMUX36	CRC32_3.CRCIN0, CRC64_1.CRCIN32
TCELL16:IMUX.IMUX37	CRC32_3.CRCIN1, CRC64_1.CRCIN33
TCELL16:IMUX.IMUX38	CRC32_3.CRCIN2, CRC64_1.CRCIN34
TCELL16:IMUX.IMUX39	CRC32_3.CRCIN3, CRC64_1.CRCIN35
TCELL16:IMUX.IMUX40	CRC32_3.CRCIN4, CRC64_1.CRCIN36
TCELL16:IMUX.IMUX42	GTX_DUAL.TXDATA015
TCELL16:IMUX.IMUX43	GTX_DUAL.TXDATA014
TCELL16:IMUX.IMUX44	GTX_DUAL.TXDATA013
TCELL16:IMUX.IMUX45	GTX_DUAL.TXDATA012
TCELL16:IMUX.IMUX47	GTX_DUAL.TXRESET0
TCELL16:OUT0	GTX_DUAL.RXNOTINTABLE02
TCELL16:OUT1	GTX_DUAL.RXCHARISCOMMA02
TCELL16:OUT2	GTX_DUAL.RXDATA020
TCELL16:OUT3	CRC32_3.CRCOUT1, CRC64_1.CRCOUT1
TCELL16:OUT5	GTX_DUAL.RXCLKCORCNT00
TCELL16:OUT6	GTX_DUAL.RXDATA021
TCELL16:OUT7	GTX_DUAL.RXSTATUS01
TCELL16:OUT11	GTX_DUAL.RXDATA022
TCELL16:OUT12	GTX_DUAL.RXDATA018
TCELL16:OUT13	CRC32_3.CRCOUT0, CRC64_1.CRCOUT0
TCELL16:OUT14	GTX_DUAL.RXSTATUS00
TCELL16:OUT15	CRC32_3.CRCOUT2, CRC64_1.CRCOUT2
TCELL16:OUT16	GTX_DUAL.RXDATA019
TCELL16:OUT17	GTX_DUAL.RXDATA023
TCELL16:OUT18	GTX_DUAL.TXRUNDISP03
TCELL16:OUT19	GTX_DUAL.RXRUNDISP02
TCELL16:OUT20	GTX_DUAL.RXCLKCORCNT02
TCELL16:OUT21	GTX_DUAL.RXSTATUS02
TCELL16:OUT22	GTX_DUAL.RXPRBSERR0
TCELL16:OUT23	GTX_DUAL.RXCLKCORCNT01
TCELL17:IMUX.IMUX0	CRC32_3.CRCRESET, CRC64_1.CRCRESET
TCELL17:IMUX.IMUX7	GTX_DUAL.TXCHARDISPMODE03
TCELL17:IMUX.IMUX8	GTX_DUAL.TXCHARISK03
TCELL17:IMUX.IMUX10	GTX_DUAL.TXPOWERDOWN00
TCELL17:IMUX.IMUX11	GTX_DUAL.TXPOWERDOWN01
TCELL17:IMUX.IMUX15	GTX_DUAL.TXPOLARITY0
TCELL17:IMUX.IMUX20	GTX_DUAL.TXDATA027
TCELL17:IMUX.IMUX21	GTX_DUAL.TXDATA026
TCELL17:IMUX.IMUX22	GTX_DUAL.TXDATA025
TCELL17:IMUX.IMUX23	GTX_DUAL.TXDATA024
TCELL17:IMUX.IMUX25	GTX_DUAL.TXCHARDISPVAL03
TCELL17:IMUX.IMUX26	GTX_DUAL.TXCHARDISPVAL01
TCELL17:IMUX.IMUX27	GTX_DUAL.TXCHARDISPMODE01
TCELL17:IMUX.IMUX28	GTX_DUAL.TXCHARISK01
TCELL17:IMUX.IMUX29	GTX_DUAL.TXBYPASS8B10B01
TCELL17:IMUX.IMUX30	CRC32_3.CRCIN8, CRC64_1.CRCIN40
TCELL17:IMUX.IMUX31	CRC32_3.CRCIN9, CRC64_1.CRCIN41
TCELL17:IMUX.IMUX32	CRC32_3.CRCIN10, CRC64_1.CRCIN42
TCELL17:IMUX.IMUX33	CRC32_3.CRCIN11, CRC64_1.CRCIN43
TCELL17:IMUX.IMUX34	CRC32_3.CRCIN12, CRC64_1.CRCIN44
TCELL17:IMUX.IMUX35	CRC32_3.CRCIN13, CRC64_1.CRCIN45
TCELL17:IMUX.IMUX37	GTX_DUAL.TXPREEMPHASIS03
TCELL17:IMUX.IMUX42	GTX_DUAL.TXDATA011
TCELL17:IMUX.IMUX43	GTX_DUAL.TXDATA010
TCELL17:IMUX.IMUX44	GTX_DUAL.TXDATA09
TCELL17:IMUX.IMUX45	GTX_DUAL.TXDATA08
TCELL17:IMUX.IMUX46	CRC32_3.CRCIN14, CRC64_1.CRCIN46
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virtex5 GTX bittile 0
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virtex5 GTX bittile 1
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virtex5 GTX bittile 2
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20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[2]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[3]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[4]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[5]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[6]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[7]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[8]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[9]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[10]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_0:CRC_INIT[11]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX bittile 4
Bit	Frame
Bit

virtex5 GTX bittile 5
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[2] GTX_DUAL:DRP07[14]	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[3] GTX_DUAL:DRP07[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[1] GTX_DUAL:DRP07[13]	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[0] GTX_DUAL:DRP07[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[10] GTX_DUAL:PMA_RX_CFG_1[7]	GTX_DUAL:DRP07[11] GTX_DUAL:PMA_RX_CFG_1[6]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[9] GTX_DUAL:PMA_RX_CFG_1[8]	GTX_DUAL:DRP07[8] GTX_DUAL:PMA_RX_CFG_1[9]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[6] GTX_DUAL:PMA_RX_CFG_0[23]	GTX_DUAL:DRP07[7] GTX_DUAL:PMA_RX_CFG_1[10]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[5] GTX_DUAL:PMA_RX_CFG_1[2]	GTX_DUAL:DRP07[4] GTX_DUAL:PMA_RX_CFG_1[3]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[2] GTX_DUAL:PMA_RX_CFG_1[5]	GTX_DUAL:DRP07[3] GTX_DUAL:PMA_RX_CFG_1[4]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP07[1] GTX_DUAL:RX_CDR_FORCE_ROTATE_1	GTX_DUAL:DRP07[0] GTX_DUAL:PMA_RX_CFG_1[13]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[14] GTX_DUAL:PMA_RX_CFG_1[15]	GTX_DUAL:DRP06[15] GTX_DUAL:PMA_RX_CFG_1[14]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[13] GTX_DUAL:PMA_RX_CFG_1[16]	GTX_DUAL:DRP06[12] GTX_DUAL:PMA_RX_CFG_1[17]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[10] GTX_DUAL:PMA_RX_CFG_1[19]	GTX_DUAL:DRP06[11] GTX_DUAL:PMA_RX_CFG_1[18]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[9] GTX_DUAL:PMA_RX_CFG_1[20]	GTX_DUAL:DRP06[8] GTX_DUAL:PMA_RX_CFG_1[21]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[6] GTX_DUAL:PMA_RX_CFG_0[11]	GTX_DUAL:DRP06[7] GTX_DUAL:PMA_RX_CFG_1[22]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[5] GTX_DUAL:PMA_RX_CFG_0[0]	GTX_DUAL:DRP06[4] GTX_DUAL:PMA_RX_CFG_0[1]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP06[2] GTX_DUAL:PMA_RX_CFG_0[12]	GTX_DUAL:DRP06[3] GTX_DUAL:PMA_RX_CFG_0[24]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:AC_CAP_DIS_1 GTX_DUAL:DRP06[1]	GTX_DUAL:DRP06[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[14] GTX_DUAL:RCV_TERM_VTTRX_1	GTX_DUAL:DRP05[15] GTX_DUAL:RCV_TERM_GND_1
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[13] GTX_DUAL:PMA_COM_CFG[22]	GTX_DUAL:DRP05[12] GTX_DUAL:PMA_COM_CFG[23]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[10] GTX_DUAL:PMA_COM_CFG[25]	GTX_DUAL:DRP05[11] GTX_DUAL:PMA_COM_CFG[24]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[9] GTX_DUAL:PMA_COM_CFG[26]	GTX_DUAL:DRP05[8] GTX_DUAL:PMA_COM_CFG[21]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[6]	GTX_DUAL:DRP05[7]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[5]	GTX_DUAL:DRP05[4] GTX_DUAL:PLL_TXDIVSEL_OUT_1[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[2]	GTX_DUAL:DRP05[3] GTX_DUAL:PLL_TXDIVSEL_OUT_1[1]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP05[1] GTX_DUAL:PLL_LKDET_CFG[0]	GTX_DUAL:DRP05[0] GTX_DUAL:PLL_LKDET_CFG[1]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[14]	GTX_DUAL:DRP04[15] GTX_DUAL:PLL_LKDET_CFG[2]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[13] GTX_DUAL:PLL_DIVSEL_REF[0]	GTX_DUAL:DRP04[12] GTX_DUAL:PLL_DIVSEL_REF[4]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[10] GTX_DUAL:PLL_DIVSEL_REF[2]	GTX_DUAL:DRP04[11] GTX_DUAL:PLL_DIVSEL_REF[3]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[9] GTX_DUAL:PLL_DIVSEL_REF[1]	GTX_DUAL:DRP04[8] GTX_DUAL:MUX.CLKOUT_NORTH[0]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[6] GTX_DUAL:MUX.CLKIN[0]	GTX_DUAL:DRP04[7] GTX_DUAL:MUX.CLKOUT_SOUTH[0]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[5] GTX_DUAL:MUX.CLKIN[1]	GTX_DUAL:DRP04[4] GTX_DUAL:MUX.CLKIN[2]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[2]	GTX_DUAL:CLKINDC_B GTX_DUAL:DRP04[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP04[1] GTX_DUAL:TX_IDLE_DELAY_1[0]	GTX_DUAL:DRP04[0] GTX_DUAL:TX_IDLE_DELAY_1[1]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[14] GTX_DUAL:RX_EN_IDLE_HOLD_DFE_1	GTX_DUAL:DRP03[15] GTX_DUAL:TX_IDLE_DELAY_1[2]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[13]	GTX_DUAL:DRP03[12] GTX_DUAL:RX_EN_IDLE_RESET_BUF_1
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[10]	GTX_DUAL:DRP03[11]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[9] GTX_DUAL:RX_IDLE_HI_CNT_1[0]	GTX_DUAL:DRP03[8] GTX_DUAL:RX_IDLE_HI_CNT_1[1]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[6] GTX_DUAL:RX_IDLE_HI_CNT_1[3]	GTX_DUAL:DRP03[7] GTX_DUAL:RX_IDLE_HI_CNT_1[2]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[5]	GTX_DUAL:DRP03[4] GTX_DUAL:RX_IDLE_LO_CNT_1[0]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[2] GTX_DUAL:RX_IDLE_LO_CNT_1[2]	GTX_DUAL:DRP03[3] GTX_DUAL:RX_IDLE_LO_CNT_1[1]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP03[1] GTX_DUAL:RX_IDLE_LO_CNT_1[3]	GTX_DUAL:CB2_INH_CC_PERIOD_1[0] GTX_DUAL:DRP03[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CB2_INH_CC_PERIOD_1[2] GTX_DUAL:DRP02[14]	GTX_DUAL:CB2_INH_CC_PERIOD_1[1] GTX_DUAL:DRP02[15]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CB2_INH_CC_PERIOD_1[3] GTX_DUAL:DRP02[13]	GTX_DUAL:CHAN_BOND_KEEP_ALIGN_1 GTX_DUAL:DRP02[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP02[10] GTX_DUAL:GEARBOX_ENDEC_1[1]	GTX_DUAL:DRP02[11] GTX_DUAL:GEARBOX_ENDEC_1[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP02[9] GTX_DUAL:GEARBOX_ENDEC_1[2]	GTX_DUAL:DRP02[8] GTX_DUAL:RXGEARBOX_USE_1
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[0] GTX_DUAL:DRP02[6]	GTX_DUAL:DRP02[7] GTX_DUAL:TXGEARBOX_USE_1
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[1] GTX_DUAL:DRP02[5]	GTX_DUAL:DFE_CFG_1[2] GTX_DUAL:DRP02[4]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[4] GTX_DUAL:DRP02[2]	GTX_DUAL:DFE_CFG_1[3] GTX_DUAL:DRP02[3]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[5] GTX_DUAL:DRP02[1]	GTX_DUAL:DFE_CFG_1[6] GTX_DUAL:DRP02[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[8] GTX_DUAL:DRP01[14]	GTX_DUAL:DFE_CFG_1[7] GTX_DUAL:DRP01[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_1[9] GTX_DUAL:DRP01[13]	GTX_DUAL:CM_TRIM_1[0] GTX_DUAL:DRP01[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[10] GTX_DUAL:PMA_TX_CFG_1[0]	GTX_DUAL:CM_TRIM_1[1] GTX_DUAL:DRP01[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[9] GTX_DUAL:PMA_TX_CFG_1[1]	GTX_DUAL:DRP01[8] GTX_DUAL:PMA_TX_CFG_1[2]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[6] GTX_DUAL:PMA_TX_CFG_1[4]	GTX_DUAL:DRP01[7] GTX_DUAL:PMA_TX_CFG_1[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[5] GTX_DUAL:PMA_TX_CFG_1[5]	GTX_DUAL:DRP01[4] GTX_DUAL:PMA_TX_CFG_1[6]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[2] GTX_DUAL:PMA_TX_CFG_1[8]	GTX_DUAL:DRP01[3] GTX_DUAL:PMA_TX_CFG_1[7]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP01[1] GTX_DUAL:PMA_TX_CFG_1[9]	GTX_DUAL:DRP01[0] GTX_DUAL:PMA_TX_CFG_1[10]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[14] GTX_DUAL:PMA_TX_CFG_1[12]	GTX_DUAL:DRP00[15] GTX_DUAL:PMA_TX_CFG_1[11]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[13] GTX_DUAL:PMA_TX_CFG_1[13]	GTX_DUAL:DRP00[12] GTX_DUAL:PMA_TX_CFG_1[14]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[10] GTX_DUAL:PMA_TX_CFG_1[16]	GTX_DUAL:DRP00[11] GTX_DUAL:PMA_TX_CFG_1[15]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[9] GTX_DUAL:PMA_TX_CFG_1[17]	GTX_DUAL:DRP00[8] GTX_DUAL:PMA_TX_CFG_1[18]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[6] GTX_DUAL:PMA_RXSYNC_CFG_1[0]	GTX_DUAL:DRP00[7] GTX_DUAL:PMA_TX_CFG_1[19]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[5] GTX_DUAL:PMA_RXSYNC_CFG_1[1]	GTX_DUAL:DRP00[4] GTX_DUAL:PMA_RXSYNC_CFG_1[2]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[2] GTX_DUAL:PMA_RXSYNC_CFG_1[4]	GTX_DUAL:DRP00[3] GTX_DUAL:PMA_RXSYNC_CFG_1[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP00[1] GTX_DUAL:PMA_RXSYNC_CFG_1[5]	GTX_DUAL:DRP00[0] GTX_DUAL:PMA_RXSYNC_CFG_1[6]

virtex5 GTX bittile 6
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[14] GTX_DUAL:SATA_MAX_WAKE_1[1]	GTX_DUAL:DRP0F[15] GTX_DUAL:SATA_MAX_WAKE_1[0]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[13] GTX_DUAL:SATA_MAX_WAKE_1[2]	GTX_DUAL:DRP0F[12] GTX_DUAL:SATA_MAX_WAKE_1[3]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[10] GTX_DUAL:SATA_MAX_WAKE_1[5]	GTX_DUAL:DRP0F[11] GTX_DUAL:SATA_MAX_WAKE_1[4]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[9] GTX_DUAL:SATA_MAX_INIT_1[0]	GTX_DUAL:DRP0F[8] GTX_DUAL:SATA_MAX_INIT_1[1]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[6] GTX_DUAL:SATA_MAX_INIT_1[3]	GTX_DUAL:DRP0F[7] GTX_DUAL:SATA_MAX_INIT_1[2]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[5] GTX_DUAL:SATA_MAX_INIT_1[4]	GTX_DUAL:DRP0F[4] GTX_DUAL:SATA_MAX_INIT_1[5]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[2] GTX_DUAL:SATA_MAX_BURST_1[1]	GTX_DUAL:DRP0F[3] GTX_DUAL:SATA_MAX_BURST_1[0]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0F[1] GTX_DUAL:SATA_MAX_BURST_1[2]	GTX_DUAL:DRP0F[0] GTX_DUAL:SATA_MAX_BURST_1[3]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[14] GTX_DUAL:SATA_MAX_BURST_1[5]	GTX_DUAL:DRP0E[15] GTX_DUAL:SATA_MAX_BURST_1[4]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[13] GTX_DUAL:SATA_IDLE_VAL_1[0]	GTX_DUAL:DRP0E[12] GTX_DUAL:SATA_IDLE_VAL_1[1]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[10] GTX_DUAL:SATA_BURST_VAL_1[0]	GTX_DUAL:DRP0E[11] GTX_DUAL:SATA_IDLE_VAL_1[2]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[9] GTX_DUAL:SATA_BURST_VAL_1[1]	GTX_DUAL:DRP0E[8] GTX_DUAL:SATA_BURST_VAL_1[2]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[6] GTX_DUAL:RX_STATUS_FMT_1[0]	GTX_DUAL:DRP0E[7] GTX_DUAL:RX_XCLK_SEL_1[0]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[5] GTX_DUAL:RX_SLIDE_MODE_1[0]	GTX_DUAL:DRP0E[4] GTX_DUAL:RX_LOS_THRESHOLD_1[0]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[2] GTX_DUAL:RX_LOS_THRESHOLD_1[2]	GTX_DUAL:DRP0E[3] GTX_DUAL:RX_LOS_THRESHOLD_1[1]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0E[1] GTX_DUAL:RX_LOSS_OF_SYNC_FSM_1	GTX_DUAL:DRP0E[0] GTX_DUAL:RX_LOS_INVALID_INCR_1[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[14] GTX_DUAL:RX_LOS_INVALID_INCR_1[2]	GTX_DUAL:DRP0D[15] GTX_DUAL:RX_LOS_INVALID_INCR_1[1]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[13] GTX_DUAL:RX_DECODE_SEQ_MATCH_1	GTX_DUAL:DRP0D[12] GTX_DUAL:RX_BUFFER_USE_1
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[10] GTX_DUAL:PRBS_ERR_THRESHOLD_1[1]	GTX_DUAL:DRP0D[11] GTX_DUAL:PRBS_ERR_THRESHOLD_1[0]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[9] GTX_DUAL:PRBS_ERR_THRESHOLD_1[2]	GTX_DUAL:DRP0D[8] GTX_DUAL:PRBS_ERR_THRESHOLD_1[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[6] GTX_DUAL:PRBS_ERR_THRESHOLD_1[5]	GTX_DUAL:DRP0D[7] GTX_DUAL:PRBS_ERR_THRESHOLD_1[4]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[5] GTX_DUAL:PRBS_ERR_THRESHOLD_1[6]	GTX_DUAL:DRP0D[4] GTX_DUAL:PRBS_ERR_THRESHOLD_1[7]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[2] GTX_DUAL:PRBS_ERR_THRESHOLD_1[9]	GTX_DUAL:DRP0D[3] GTX_DUAL:PRBS_ERR_THRESHOLD_1[8]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0D[1] GTX_DUAL:PRBS_ERR_THRESHOLD_1[10]	GTX_DUAL:DRP0D[0] GTX_DUAL:PRBS_ERR_THRESHOLD_1[11]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[14] GTX_DUAL:PRBS_ERR_THRESHOLD_1[13]	GTX_DUAL:DRP0C[15] GTX_DUAL:PRBS_ERR_THRESHOLD_1[12]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[13] GTX_DUAL:PRBS_ERR_THRESHOLD_1[14]	GTX_DUAL:DRP0C[12] GTX_DUAL:PRBS_ERR_THRESHOLD_1[15]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[10] GTX_DUAL:PRBS_ERR_THRESHOLD_1[17]	GTX_DUAL:DRP0C[11] GTX_DUAL:PRBS_ERR_THRESHOLD_1[16]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[9] GTX_DUAL:PRBS_ERR_THRESHOLD_1[18]	GTX_DUAL:DRP0C[8] GTX_DUAL:PRBS_ERR_THRESHOLD_1[19]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[6] GTX_DUAL:PRBS_ERR_THRESHOLD_1[21]	GTX_DUAL:DRP0C[7] GTX_DUAL:PRBS_ERR_THRESHOLD_1[20]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[5] GTX_DUAL:PRBS_ERR_THRESHOLD_1[22]	GTX_DUAL:DRP0C[4] GTX_DUAL:PRBS_ERR_THRESHOLD_1[23]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[2] GTX_DUAL:PRBS_ERR_THRESHOLD_1[25]	GTX_DUAL:DRP0C[3] GTX_DUAL:PRBS_ERR_THRESHOLD_1[24]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0C[1] GTX_DUAL:PRBS_ERR_THRESHOLD_1[26]	GTX_DUAL:DRP0C[0] GTX_DUAL:PRBS_ERR_THRESHOLD_1[27]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[14] GTX_DUAL:PRBS_ERR_THRESHOLD_1[29]	GTX_DUAL:DRP0B[15] GTX_DUAL:PRBS_ERR_THRESHOLD_1[28]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[13] GTX_DUAL:PRBS_ERR_THRESHOLD_1[30]	GTX_DUAL:DRP0B[12] GTX_DUAL:PRBS_ERR_THRESHOLD_1[31]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[10] GTX_DUAL:PMA_CDR_SCAN_1[1]	GTX_DUAL:DRP0B[11] GTX_DUAL:PMA_CDR_SCAN_1[0]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[9] GTX_DUAL:PMA_CDR_SCAN_1[2]	GTX_DUAL:DRP0B[8] GTX_DUAL:PMA_CDR_SCAN_1[3]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[6] GTX_DUAL:PMA_CDR_SCAN_1[5]	GTX_DUAL:DRP0B[7] GTX_DUAL:PMA_CDR_SCAN_1[4]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[5] GTX_DUAL:PMA_CDR_SCAN_1[6]	GTX_DUAL:DRP0B[4] GTX_DUAL:PMA_CDR_SCAN_1[7]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[2] GTX_DUAL:PMA_CDR_SCAN_1[9]	GTX_DUAL:DRP0B[3] GTX_DUAL:PMA_CDR_SCAN_1[8]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0B[1] GTX_DUAL:PMA_CDR_SCAN_1[10]	GTX_DUAL:DRP0B[0] GTX_DUAL:PMA_CDR_SCAN_1[11]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[14] GTX_DUAL:PMA_CDR_SCAN_1[13]	GTX_DUAL:DRP0A[15] GTX_DUAL:PMA_CDR_SCAN_1[12]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[13] GTX_DUAL:PMA_CDR_SCAN_1[14]	GTX_DUAL:DRP0A[12] GTX_DUAL:PMA_CDR_SCAN_1[15]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[10] GTX_DUAL:PMA_CDR_SCAN_1[17]	GTX_DUAL:DRP0A[11] GTX_DUAL:PMA_CDR_SCAN_1[16]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[9] GTX_DUAL:PMA_CDR_SCAN_1[18]	GTX_DUAL:DRP0A[8] GTX_DUAL:PMA_CDR_SCAN_1[19]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[6] GTX_DUAL:PMA_CDR_SCAN_1[21]	GTX_DUAL:DRP0A[7] GTX_DUAL:PMA_CDR_SCAN_1[20]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[5] GTX_DUAL:PMA_CDR_SCAN_1[22]	GTX_DUAL:DRP0A[4] GTX_DUAL:PMA_CDR_SCAN_1[23]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[2] GTX_DUAL:PMA_CDR_SCAN_1[25]	GTX_DUAL:DRP0A[3] GTX_DUAL:PMA_CDR_SCAN_1[24]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP0A[1] GTX_DUAL:PMA_CDR_SCAN_1[26]	GTX_DUAL:DRP0A[0] GTX_DUAL:PLL_RXDIVSEL_OUT_1[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[14] GTX_DUAL:PLL_SATA_1	GTX_DUAL:DRP09[15] GTX_DUAL:PLL_RXDIVSEL_OUT_1[1]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[13]	GTX_DUAL:CLKRCV_TRST GTX_DUAL:DRP09[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[10] GTX_DUAL:PCOMMA_10B_VALUE_1[0]	GTX_DUAL:DRP09[11] GTX_DUAL:PCOMMA_DETECT_1
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[9] GTX_DUAL:PCOMMA_10B_VALUE_1[1]	GTX_DUAL:DRP09[8] GTX_DUAL:PCOMMA_10B_VALUE_1[2]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[6] GTX_DUAL:PCOMMA_10B_VALUE_1[4]	GTX_DUAL:DRP09[7] GTX_DUAL:PCOMMA_10B_VALUE_1[3]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[5] GTX_DUAL:PCOMMA_10B_VALUE_1[5]	GTX_DUAL:DRP09[4] GTX_DUAL:PCOMMA_10B_VALUE_1[6]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[2] GTX_DUAL:PCOMMA_10B_VALUE_1[8]	GTX_DUAL:DRP09[3] GTX_DUAL:PCOMMA_10B_VALUE_1[7]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP09[1] GTX_DUAL:PCOMMA_10B_VALUE_1[9]	GTX_DUAL:DRP09[0] GTX_DUAL:PCI_EXPRESS_MODE_1
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[8] GTX_DUAL:DRP08[14]	GTX_DUAL:DRP08[15]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[7] GTX_DUAL:DRP08[13]	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[6] GTX_DUAL:DRP08[12]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[4] GTX_DUAL:DRP08[10]	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[5] GTX_DUAL:DRP08[11]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[3] GTX_DUAL:DRP08[9]	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[2] GTX_DUAL:DRP08[8]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[0] GTX_DUAL:DRP08[6]	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[1] GTX_DUAL:DRP08[7]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[9] GTX_DUAL:DRP08[5]	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[8] GTX_DUAL:DRP08[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[6] GTX_DUAL:DRP08[2]	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[7] GTX_DUAL:DRP08[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[5] GTX_DUAL:DRP08[1]	GTX_DUAL:CHAN_BOND_SEQ_2_4_1[4] GTX_DUAL:DRP08[0]

virtex5 GTX bittile 7
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_1[9] GTX_DUAL:DRP17[14]	GTX_DUAL:CLK_COR_SEQ_1_1_1[8] GTX_DUAL:DRP17[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_1[0] GTX_DUAL:DRP17[13]	GTX_DUAL:CLK_COR_REPEAT_WAIT_1[1] GTX_DUAL:DRP17[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_1[3] GTX_DUAL:DRP17[10]	GTX_DUAL:CLK_COR_REPEAT_WAIT_1[2] GTX_DUAL:DRP17[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_1[4] GTX_DUAL:DRP17[9]	GTX_DUAL:CLK_CORRECT_USE_1 GTX_DUAL:DRP17[8]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_1[0] GTX_DUAL:DRP17[6]	GTX_DUAL:CLK_COR_PRECEDENCE_1 GTX_DUAL:DRP17[7]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_1[1] GTX_DUAL:DRP17[5]	GTX_DUAL:CLK_COR_MIN_LAT_1[2] GTX_DUAL:DRP17[4]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_1[4] GTX_DUAL:DRP17[2]	GTX_DUAL:CLK_COR_MIN_LAT_1[3] GTX_DUAL:DRP17[3]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_1[5] GTX_DUAL:DRP17[1]	GTX_DUAL:CLK_COR_MAX_LAT_1[0] GTX_DUAL:DRP17[0]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MAX_LAT_1[2] GTX_DUAL:DRP16[14]	GTX_DUAL:CLK_COR_MAX_LAT_1[1] GTX_DUAL:DRP16[15]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MAX_LAT_1[3] GTX_DUAL:DRP16[13]	GTX_DUAL:CLK_COR_MAX_LAT_1[4] GTX_DUAL:DRP16[12]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_KEEP_IDLE_1 GTX_DUAL:DRP16[10]	GTX_DUAL:CLK_COR_MAX_LAT_1[5] GTX_DUAL:DRP16[11]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_1 GTX_DUAL:DRP16[9]	GTX_DUAL:CLK_COR_DET_LEN_1[0] GTX_DUAL:DRP16[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_ADJ_LEN_1[0] GTX_DUAL:DRP16[6]	GTX_DUAL:CLK_COR_DET_LEN_1[1] GTX_DUAL:DRP16[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_ADJ_LEN_1[1] GTX_DUAL:DRP16[5]	GTX_DUAL:CHAN_BOND_SEQ_LEN_1[0] GTX_DUAL:DRP16[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_USE_1 GTX_DUAL:DRP16[2]	GTX_DUAL:CHAN_BOND_SEQ_LEN_1[1] GTX_DUAL:DRP16[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[0] GTX_DUAL:DRP16[1]	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[1] GTX_DUAL:DRP16[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[3] GTX_DUAL:DRP15[14]	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[2] GTX_DUAL:DRP15[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[13] GTX_DUAL:PMA_COM_CFG[8]	GTX_DUAL:DRP15[12] GTX_DUAL:OOBDETECT_THRESHOLD_1[0]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[10] GTX_DUAL:OOBDETECT_THRESHOLD_1[2]	GTX_DUAL:DRP15[11] GTX_DUAL:OOBDETECT_THRESHOLD_1[1]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[9]	GTX_DUAL:DRP15[8] GTX_DUAL:TXOUTCLK_SEL_1
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[6]	GTX_DUAL:DRP15[7] GTX_DUAL:TX_XCLK_SEL_1[0]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[5]	GTX_DUAL:DRP15[4] GTX_DUAL:TXRX_INVERT_1[0]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[2] GTX_DUAL:TXRX_INVERT_1[2]	GTX_DUAL:DRP15[3] GTX_DUAL:TXRX_INVERT_1[1]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP15[1] GTX_DUAL:TX_DETECT_RX_CFG_1[0]	GTX_DUAL:DRP15[0] GTX_DUAL:TX_DETECT_RX_CFG_1[1]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[14] GTX_DUAL:TX_DETECT_RX_CFG_1[3]	GTX_DUAL:DRP14[15] GTX_DUAL:TX_DETECT_RX_CFG_1[2]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[13] GTX_DUAL:TX_DETECT_RX_CFG_1[4]	GTX_DUAL:DRP14[12] GTX_DUAL:TX_DETECT_RX_CFG_1[5]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[10] GTX_DUAL:TX_DETECT_RX_CFG_1[7]	GTX_DUAL:DRP14[11] GTX_DUAL:TX_DETECT_RX_CFG_1[6]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[9] GTX_DUAL:TX_DETECT_RX_CFG_1[8]	GTX_DUAL:DRP14[8] GTX_DUAL:TX_DETECT_RX_CFG_1[9]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[6] GTX_DUAL:TX_DETECT_RX_CFG_1[11]	GTX_DUAL:DRP14[7] GTX_DUAL:TX_DETECT_RX_CFG_1[10]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[5] GTX_DUAL:TX_DETECT_RX_CFG_1[12]	GTX_DUAL:DRP14[4] GTX_DUAL:TX_DETECT_RX_CFG_1[13]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[2] GTX_DUAL:PLL_COM_CFG[23]	GTX_DUAL:DRP14[3] GTX_DUAL:TX_BUFFER_USE_1
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP14[1] GTX_DUAL:PLL_COM_CFG[22]	GTX_DUAL:DRP14[0] GTX_DUAL:PLL_COM_CFG[21]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[14]	GTX_DUAL:DRP13[15] GTX_DUAL:PLL_COM_CFG[20]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[13]	GTX_DUAL:DRP13[12] GTX_DUAL:TRANS_TIME_TO_P2_1[0]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[10] GTX_DUAL:TRANS_TIME_TO_P2_1[2]	GTX_DUAL:DRP13[11] GTX_DUAL:TRANS_TIME_TO_P2_1[1]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[9] GTX_DUAL:TRANS_TIME_TO_P2_1[3]	GTX_DUAL:DRP13[8] GTX_DUAL:TRANS_TIME_TO_P2_1[4]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[6] GTX_DUAL:TRANS_TIME_TO_P2_1[6]	GTX_DUAL:DRP13[7] GTX_DUAL:TRANS_TIME_TO_P2_1[5]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[5] GTX_DUAL:TRANS_TIME_TO_P2_1[7]	GTX_DUAL:DRP13[4] GTX_DUAL:TRANS_TIME_TO_P2_1[8]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[2]	GTX_DUAL:DRP13[3] GTX_DUAL:TRANS_TIME_TO_P2_1[9]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP13[1]	GTX_DUAL:DRP13[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[14]	GTX_DUAL:DRP12[15]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[13]	GTX_DUAL:DRP12[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[10] GTX_DUAL:TRANS_TIME_NON_P2_1[0]	GTX_DUAL:DRP12[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[9] GTX_DUAL:TRANS_TIME_NON_P2_1[1]	GTX_DUAL:DRP12[8] GTX_DUAL:TRANS_TIME_NON_P2_1[2]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[6] GTX_DUAL:TRANS_TIME_NON_P2_1[4]	GTX_DUAL:DRP12[7] GTX_DUAL:TRANS_TIME_NON_P2_1[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[5] GTX_DUAL:TRANS_TIME_NON_P2_1[5]	GTX_DUAL:DRP12[4] GTX_DUAL:TRANS_TIME_NON_P2_1[6]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[2]	GTX_DUAL:DRP12[3] GTX_DUAL:TRANS_TIME_NON_P2_1[7]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP12[1]	GTX_DUAL:DRP12[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[14] GTX_DUAL:TRANS_TIME_FROM_P2_1[0]	GTX_DUAL:DRP11[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[13] GTX_DUAL:TRANS_TIME_FROM_P2_1[1]	GTX_DUAL:DRP11[12] GTX_DUAL:TRANS_TIME_FROM_P2_1[2]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[10] GTX_DUAL:TRANS_TIME_FROM_P2_1[4]	GTX_DUAL:DRP11[11] GTX_DUAL:TRANS_TIME_FROM_P2_1[3]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[9] GTX_DUAL:TRANS_TIME_FROM_P2_1[5]	GTX_DUAL:DRP11[8] GTX_DUAL:TRANS_TIME_FROM_P2_1[6]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[6] GTX_DUAL:TRANS_TIME_FROM_P2_1[8]	GTX_DUAL:DRP11[7] GTX_DUAL:TRANS_TIME_FROM_P2_1[7]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[5] GTX_DUAL:TRANS_TIME_FROM_P2_1[9]	GTX_DUAL:DRP11[4] GTX_DUAL:TRANS_TIME_FROM_P2_1[10]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[2] GTX_DUAL:TERMINATION_IMP_1[0]	GTX_DUAL:DRP11[3] GTX_DUAL:TRANS_TIME_FROM_P2_1[11]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP11[1] GTX_DUAL:SATA_MIN_WAKE_1[0]	GTX_DUAL:DRP11[0] GTX_DUAL:SATA_MIN_WAKE_1[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[14] GTX_DUAL:SATA_MIN_WAKE_1[3]	GTX_DUAL:DRP10[15] GTX_DUAL:SATA_MIN_WAKE_1[2]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[13] GTX_DUAL:SATA_MIN_WAKE_1[4]	GTX_DUAL:DRP10[12] GTX_DUAL:SATA_MIN_WAKE_1[5]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[10] GTX_DUAL:SATA_MIN_INIT_1[1]	GTX_DUAL:DRP10[11] GTX_DUAL:SATA_MIN_INIT_1[0]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[9] GTX_DUAL:SATA_MIN_INIT_1[2]	GTX_DUAL:DRP10[8] GTX_DUAL:SATA_MIN_INIT_1[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[6] GTX_DUAL:SATA_MIN_INIT_1[5]	GTX_DUAL:DRP10[7] GTX_DUAL:SATA_MIN_INIT_1[4]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[5] GTX_DUAL:SATA_MIN_BURST_1[0]	GTX_DUAL:DRP10[4] GTX_DUAL:SATA_MIN_BURST_1[1]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[2] GTX_DUAL:SATA_MIN_BURST_1[3]	GTX_DUAL:DRP10[3] GTX_DUAL:SATA_MIN_BURST_1[2]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP10[1] GTX_DUAL:SATA_MIN_BURST_1[4]	GTX_DUAL:DRP10[0] GTX_DUAL:SATA_MIN_BURST_1[5]

virtex5 GTX bittile 8
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[28]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[8] GTX_DUAL:DRP1F[14]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[9] GTX_DUAL:DRP1F[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[29]	-	GTX_DUAL:DRP1F[13]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[7] GTX_DUAL:DRP1F[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[30]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[5] GTX_DUAL:DRP1F[10]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[6] GTX_DUAL:DRP1F[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[31]	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[4] GTX_DUAL:DRP1F[9]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[3] GTX_DUAL:DRP1F[8]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[1] GTX_DUAL:DRP1F[6]	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[2] GTX_DUAL:DRP1F[7]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_1[0] GTX_DUAL:DRP1F[5]	GTX_DUAL:CHAN_BOND_SEQ_2_3_1[9] GTX_DUAL:DRP1F[4]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1F[2] GTX_DUAL:MCOMMA_10B_VALUE_1[0]	GTX_DUAL:DRP1F[3] GTX_DUAL:MCOMMA_DETECT_1
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1F[1] GTX_DUAL:MCOMMA_10B_VALUE_1[1]	GTX_DUAL:DRP1F[0] GTX_DUAL:MCOMMA_10B_VALUE_1[2]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1E[14] GTX_DUAL:MCOMMA_10B_VALUE_1[4]	GTX_DUAL:DRP1E[15] GTX_DUAL:MCOMMA_10B_VALUE_1[3]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1E[13] GTX_DUAL:MCOMMA_10B_VALUE_1[5]	GTX_DUAL:DRP1E[12] GTX_DUAL:MCOMMA_10B_VALUE_1[6]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1E[10] GTX_DUAL:MCOMMA_10B_VALUE_1[8]	GTX_DUAL:DRP1E[11] GTX_DUAL:MCOMMA_10B_VALUE_1[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP1E[9] GTX_DUAL:MCOMMA_10B_VALUE_1[9]	GTX_DUAL:DEC_VALID_COMMA_ONLY_1 GTX_DUAL:DRP1E[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DEC_MCOMMA_DETECT_1 GTX_DUAL:DRP1E[6]	GTX_DUAL:DEC_PCOMMA_DETECT_1 GTX_DUAL:DRP1E[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_DOUBLE_1 GTX_DUAL:DRP1E[5]	GTX_DUAL:COMMA_10B_ENABLE_1[0] GTX_DUAL:DRP1E[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_1[2] GTX_DUAL:DRP1E[2]	GTX_DUAL:COMMA_10B_ENABLE_1[1] GTX_DUAL:DRP1E[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_1[3] GTX_DUAL:DRP1E[1]	GTX_DUAL:COMMA_10B_ENABLE_1[4] GTX_DUAL:DRP1E[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_1[6] GTX_DUAL:DRP1D[14]	GTX_DUAL:COMMA_10B_ENABLE_1[5] GTX_DUAL:DRP1D[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_1[7] GTX_DUAL:DRP1D[13]	GTX_DUAL:COMMA_10B_ENABLE_1[8] GTX_DUAL:DRP1D[12]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COM_BURST_VAL_1[0] GTX_DUAL:DRP1D[10]	GTX_DUAL:COMMA_10B_ENABLE_1[9] GTX_DUAL:DRP1D[11]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COM_BURST_VAL_1[1] GTX_DUAL:DRP1D[9]	GTX_DUAL:COM_BURST_VAL_1[2] GTX_DUAL:DRP1D[8]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_USE_1 GTX_DUAL:DRP1D[6]	GTX_DUAL:COM_BURST_VAL_1[3] GTX_DUAL:DRP1D[7]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[0] GTX_DUAL:DRP1D[5]	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[1] GTX_DUAL:DRP1D[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[3] GTX_DUAL:DRP1D[2]	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[2] GTX_DUAL:DRP1D[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_1[0] GTX_DUAL:DRP1D[1]	GTX_DUAL:CLK_COR_SEQ_2_4_1[1] GTX_DUAL:DRP1D[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_1[3] GTX_DUAL:DRP1C[14]	GTX_DUAL:CLK_COR_SEQ_2_4_1[2] GTX_DUAL:DRP1C[15]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_1[4] GTX_DUAL:DRP1C[13]	GTX_DUAL:CLK_COR_SEQ_2_4_1[5] GTX_DUAL:DRP1C[12]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_1[7] GTX_DUAL:DRP1C[10]	GTX_DUAL:CLK_COR_SEQ_2_4_1[6] GTX_DUAL:DRP1C[11]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_1[8] GTX_DUAL:DRP1C[9]	GTX_DUAL:CLK_COR_SEQ_2_4_1[9] GTX_DUAL:DRP1C[8]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_1[1] GTX_DUAL:DRP1C[6]	GTX_DUAL:CLK_COR_SEQ_2_3_1[0] GTX_DUAL:DRP1C[7]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_1[2] GTX_DUAL:DRP1C[5]	GTX_DUAL:CLK_COR_SEQ_2_3_1[3] GTX_DUAL:DRP1C[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_1[5] GTX_DUAL:DRP1C[2]	GTX_DUAL:CLK_COR_SEQ_2_3_1[4] GTX_DUAL:DRP1C[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_1[6] GTX_DUAL:DRP1C[1]	GTX_DUAL:CLK_COR_SEQ_2_3_1[7] GTX_DUAL:DRP1C[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_1[9] GTX_DUAL:DRP1B[14]	GTX_DUAL:CLK_COR_SEQ_2_3_1[8] GTX_DUAL:DRP1B[15]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_1[0] GTX_DUAL:DRP1B[13]	GTX_DUAL:CLK_COR_SEQ_2_2_1[1] GTX_DUAL:DRP1B[12]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_1[3] GTX_DUAL:DRP1B[10]	GTX_DUAL:CLK_COR_SEQ_2_2_1[2] GTX_DUAL:DRP1B[11]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_1[4] GTX_DUAL:DRP1B[9]	GTX_DUAL:CLK_COR_SEQ_2_2_1[5] GTX_DUAL:DRP1B[8]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_1[7] GTX_DUAL:DRP1B[6]	GTX_DUAL:CLK_COR_SEQ_2_2_1[6] GTX_DUAL:DRP1B[7]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_1[8] GTX_DUAL:DRP1B[5]	GTX_DUAL:CLK_COR_SEQ_2_2_1[9] GTX_DUAL:DRP1B[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_1[1] GTX_DUAL:DRP1B[2]	GTX_DUAL:CLK_COR_SEQ_2_1_1[0] GTX_DUAL:DRP1B[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_1[2] GTX_DUAL:DRP1B[1]	GTX_DUAL:CLK_COR_SEQ_2_1_1[3] GTX_DUAL:DRP1B[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_1[5] GTX_DUAL:DRP1A[14]	GTX_DUAL:CLK_COR_SEQ_2_1_1[4] GTX_DUAL:DRP1A[15]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_1[6] GTX_DUAL:DRP1A[13]	GTX_DUAL:CLK_COR_SEQ_2_1_1[7] GTX_DUAL:DRP1A[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_1[9] GTX_DUAL:DRP1A[10]	GTX_DUAL:CLK_COR_SEQ_2_1_1[8] GTX_DUAL:DRP1A[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[0] GTX_DUAL:DRP1A[9]	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[1] GTX_DUAL:DRP1A[8]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[3] GTX_DUAL:DRP1A[6]	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[2] GTX_DUAL:DRP1A[7]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_1[0] GTX_DUAL:DRP1A[5]	GTX_DUAL:CLK_COR_SEQ_1_4_1[1] GTX_DUAL:DRP1A[4]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_1[3] GTX_DUAL:DRP1A[2]	GTX_DUAL:CLK_COR_SEQ_1_4_1[2] GTX_DUAL:DRP1A[3]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_1[4] GTX_DUAL:DRP1A[1]	GTX_DUAL:CLK_COR_SEQ_1_4_1[5] GTX_DUAL:DRP1A[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_1[7] GTX_DUAL:DRP19[14]	GTX_DUAL:CLK_COR_SEQ_1_4_1[6] GTX_DUAL:DRP19[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_1[8] GTX_DUAL:DRP19[13]	GTX_DUAL:CLK_COR_SEQ_1_4_1[9] GTX_DUAL:DRP19[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_1[1] GTX_DUAL:DRP19[10]	GTX_DUAL:CLK_COR_SEQ_1_3_1[0] GTX_DUAL:DRP19[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_1[2] GTX_DUAL:DRP19[9]	GTX_DUAL:CLK_COR_SEQ_1_3_1[3] GTX_DUAL:DRP19[8]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_1[5] GTX_DUAL:DRP19[6]	GTX_DUAL:CLK_COR_SEQ_1_3_1[4] GTX_DUAL:DRP19[7]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_1[6] GTX_DUAL:DRP19[5]	GTX_DUAL:CLK_COR_SEQ_1_3_1[7] GTX_DUAL:DRP19[4]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_1[9] GTX_DUAL:DRP19[2]	GTX_DUAL:CLK_COR_SEQ_1_3_1[8] GTX_DUAL:DRP19[3]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_1[0] GTX_DUAL:DRP19[1]	GTX_DUAL:CLK_COR_SEQ_1_2_1[1] GTX_DUAL:DRP19[0]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_1[3] GTX_DUAL:DRP18[14]	GTX_DUAL:CLK_COR_SEQ_1_2_1[2] GTX_DUAL:DRP18[15]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_1[4] GTX_DUAL:DRP18[13]	GTX_DUAL:CLK_COR_SEQ_1_2_1[5] GTX_DUAL:DRP18[12]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_1[7] GTX_DUAL:DRP18[10]	GTX_DUAL:CLK_COR_SEQ_1_2_1[6] GTX_DUAL:DRP18[11]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_1[8] GTX_DUAL:DRP18[9]	GTX_DUAL:CLK_COR_SEQ_1_2_1[9] GTX_DUAL:DRP18[8]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_1[1] GTX_DUAL:DRP18[6]	GTX_DUAL:CLK_COR_SEQ_1_1_1[0] GTX_DUAL:DRP18[7]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_1[2] GTX_DUAL:DRP18[5]	GTX_DUAL:CLK_COR_SEQ_1_1_1[3] GTX_DUAL:DRP18[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_1[5] GTX_DUAL:DRP18[2]	GTX_DUAL:CLK_COR_SEQ_1_1_1[4] GTX_DUAL:DRP18[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_1[6] GTX_DUAL:DRP18[1]	GTX_DUAL:CLK_COR_SEQ_1_1_1[7] GTX_DUAL:DRP18[0]

virtex5 GTX bittile 9
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[14] GTX_DUAL:PLL_COM_CFG[5]	GTX_DUAL:DRP27[15] GTX_DUAL:PLL_COM_CFG[4]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[13] GTX_DUAL:PLL_COM_CFG[6]	GTX_DUAL:DRP27[12] GTX_DUAL:PLL_COM_CFG[7]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[10] GTX_DUAL:PLL_COM_CFG[9]	GTX_DUAL:DRP27[11] GTX_DUAL:PLL_COM_CFG[8]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[9] GTX_DUAL:PLL_COM_CFG[10]	GTX_DUAL:DRP27[8] GTX_DUAL:PLL_COM_CFG[11]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[6] GTX_DUAL:PLL_COM_CFG[13]	GTX_DUAL:DRP27[7] GTX_DUAL:PLL_COM_CFG[12]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[5] GTX_DUAL:PLL_COM_CFG[14]	GTX_DUAL:DRP27[4] GTX_DUAL:PLL_COM_CFG[15]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[2] GTX_DUAL:PLL_COM_CFG[17]	GTX_DUAL:DRP27[3] GTX_DUAL:PLL_COM_CFG[16]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP27[1] GTX_DUAL:PLL_COM_CFG[18]	GTX_DUAL:DRP27[0] GTX_DUAL:PLL_COM_CFG[19]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[14] GTX_DUAL:OOB_CLK_DIVIDER[0]	GTX_DUAL:DRP26[15] GTX_DUAL:OVERSAMPLE_MODE
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[13] GTX_DUAL:OOB_CLK_DIVIDER[1]	GTX_DUAL:DRP26[12] GTX_DUAL:OOB_CLK_DIVIDER[2]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK25_DIVIDER[1] GTX_DUAL:DRP26[10]	GTX_DUAL:CLK25_DIVIDER[0] GTX_DUAL:DRP26[11]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK25_DIVIDER[2] GTX_DUAL:DRP26[9]	GTX_DUAL:DRP26[8] GTX_DUAL:PMA_COM_CFG[48]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[6] GTX_DUAL:PMA_COM_CFG[44]	GTX_DUAL:DRP26[7] GTX_DUAL:PMA_COM_CFG[46]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[5] GTX_DUAL:PMA_COM_CFG[42]	GTX_DUAL:DRP26[4] GTX_DUAL:PMA_COM_CFG[38]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[2] GTX_DUAL:PMA_COM_CFG[36]	GTX_DUAL:DRP26[3] GTX_DUAL:PMA_COM_CFG[40]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP26[1] GTX_DUAL:PMA_COM_CFG[34]	GTX_DUAL:DRP26[0] GTX_DUAL:PMA_COM_CFG[56]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[14] GTX_DUAL:PMA_COM_CFG[64]	GTX_DUAL:DRP25[15] GTX_DUAL:PMA_COM_CFG[54]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[13] GTX_DUAL:PMA_COM_CFG[62]	GTX_DUAL:DRP25[12] GTX_DUAL:PMA_COM_CFG[61]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[10] GTX_DUAL:PMA_COM_CFG[68]	GTX_DUAL:DRP25[11] GTX_DUAL:PMA_COM_CFG[63]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[9] GTX_DUAL:PMA_COM_CFG[66]	GTX_DUAL:DRP25[8]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[6]	GTX_DUAL:DRP25[7]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[5]	GTX_DUAL:DRP25[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[2] GTX_DUAL:PMA_COM_CFG[50]	GTX_DUAL:DRP25[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP25[1] GTX_DUAL:PMA_COM_CFG[52]	GTX_DUAL:DRP25[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[14]	GTX_DUAL:DRP24[15]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[13]	GTX_DUAL:DRP24[12] GTX_DUAL:PMA_COM_CFG[10]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[10] GTX_DUAL:PMA_COM_CFG[12]	GTX_DUAL:DRP24[11] GTX_DUAL:PMA_COM_CFG[11]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[9] GTX_DUAL:PMA_COM_CFG[13]	GTX_DUAL:DRP24[8] GTX_DUAL:PMA_COM_CFG[14]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[6] GTX_DUAL:PMA_COM_CFG[16]	GTX_DUAL:DRP24[7] GTX_DUAL:PMA_COM_CFG[15]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP24[5] GTX_DUAL:PMA_COM_CFG[17]	GTX_DUAL:DRP24[4] GTX_DUAL:PMA_COM_CFG[18]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[3] GTX_DUAL:DRP24[2]	GTX_DUAL:ALIGN_COMMA_WORD_1[0] GTX_DUAL:DRP24[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[2] GTX_DUAL:DRP24[1]	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[1] GTX_DUAL:DRP24[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[3] GTX_DUAL:DRP23[14]	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[0] GTX_DUAL:DRP23[15]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[2] GTX_DUAL:DRP23[13]	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[1] GTX_DUAL:DRP23[12]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_LEVEL_1[2] GTX_DUAL:DRP23[10]	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[0] GTX_DUAL:DRP23[11]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_LEVEL_1[1] GTX_DUAL:DRP23[9]	GTX_DUAL:CHAN_BOND_LEVEL_1[0] GTX_DUAL:DRP23[8]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[0]	GTX_DUAL:CHAN_BOND_MODE_1[1] GTX_DUAL:DRP23[6]	GTX_DUAL:CHAN_BOND_MODE_1[0] GTX_DUAL:DRP23[7]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[1]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[9] GTX_DUAL:DRP23[5]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[8] GTX_DUAL:DRP23[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[2]	-	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[6] GTX_DUAL:DRP23[2]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[7] GTX_DUAL:DRP23[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[3]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[5] GTX_DUAL:DRP23[1]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[4] GTX_DUAL:DRP23[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[4]	-	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[2] GTX_DUAL:DRP22[14]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[3] GTX_DUAL:DRP22[15]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[5]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[1] GTX_DUAL:DRP22[13]	GTX_DUAL:CHAN_BOND_SEQ_1_1_1[0] GTX_DUAL:DRP22[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[6]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[8] GTX_DUAL:DRP22[10]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[9] GTX_DUAL:DRP22[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[7]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[7] GTX_DUAL:DRP22[9]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[6] GTX_DUAL:DRP22[8]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[8]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[4] GTX_DUAL:DRP22[6]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[5] GTX_DUAL:DRP22[7]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[9]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[3] GTX_DUAL:DRP22[5]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[2] GTX_DUAL:DRP22[4]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[10]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[0] GTX_DUAL:DRP22[2]	GTX_DUAL:CHAN_BOND_SEQ_1_2_1[1] GTX_DUAL:DRP22[3]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[9] GTX_DUAL:DRP22[1]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[8] GTX_DUAL:DRP22[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[11]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[6] GTX_DUAL:DRP21[14]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[7] GTX_DUAL:DRP21[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[12]	-	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[5] GTX_DUAL:DRP21[13]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[4] GTX_DUAL:DRP21[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[13]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[2] GTX_DUAL:DRP21[10]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[3] GTX_DUAL:DRP21[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[14]	CRC32_1:CRC_INIT[15]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[1] GTX_DUAL:DRP21[9]	GTX_DUAL:CHAN_BOND_SEQ_1_3_1[0] GTX_DUAL:DRP21[8]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[16]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[8] GTX_DUAL:DRP21[6]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[9] GTX_DUAL:DRP21[7]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[17]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[7] GTX_DUAL:DRP21[5]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[6] GTX_DUAL:DRP21[4]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[18]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[4] GTX_DUAL:DRP21[2]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[5] GTX_DUAL:DRP21[3]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[19]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[3] GTX_DUAL:DRP21[1]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[2] GTX_DUAL:DRP21[0]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[20]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[0] GTX_DUAL:DRP20[14]	GTX_DUAL:CHAN_BOND_SEQ_1_4_1[1] GTX_DUAL:DRP20[15]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[21]	CRC32_1:CRC_INIT[22]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[3] GTX_DUAL:DRP20[13]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[2] GTX_DUAL:DRP20[12]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[0] GTX_DUAL:DRP20[10]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[1] GTX_DUAL:DRP20[11]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[23]	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[9] GTX_DUAL:DRP20[9]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[8] GTX_DUAL:DRP20[8]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[25]	CRC32_1:CRC_INIT[24]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[6] GTX_DUAL:DRP20[6]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[7] GTX_DUAL:DRP20[7]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[5] GTX_DUAL:DRP20[5]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[4] GTX_DUAL:DRP20[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[26]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[2] GTX_DUAL:DRP20[2]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[3] GTX_DUAL:DRP20[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_1:CRC_INIT[27]	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[1] GTX_DUAL:DRP20[1]	GTX_DUAL:CHAN_BOND_SEQ_2_1_1[0] GTX_DUAL:DRP20[0]

virtex5 GTX bittile 10
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[27]	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[1] GTX_DUAL:DRP2F[14]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[0] GTX_DUAL:DRP2F[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[26]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[2] GTX_DUAL:DRP2F[13]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[3] GTX_DUAL:DRP2F[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[5] GTX_DUAL:DRP2F[10]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[4] GTX_DUAL:DRP2F[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[25]	CRC32_2:CRC_INIT[24]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[6] GTX_DUAL:DRP2F[9]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[7] GTX_DUAL:DRP2F[8]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[23]	-	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[9] GTX_DUAL:DRP2F[6]	GTX_DUAL:CHAN_BOND_SEQ_2_1_0[8] GTX_DUAL:DRP2F[7]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[0] GTX_DUAL:DRP2F[5]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[1] GTX_DUAL:DRP2F[4]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[21]	CRC32_2:CRC_INIT[22]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[3] GTX_DUAL:DRP2F[2]	GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[2] GTX_DUAL:DRP2F[3]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[20]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[0] GTX_DUAL:DRP2F[1]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[1] GTX_DUAL:DRP2F[0]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[19]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[3] GTX_DUAL:DRP2E[14]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[2] GTX_DUAL:DRP2E[15]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[18]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[4] GTX_DUAL:DRP2E[13]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[5] GTX_DUAL:DRP2E[12]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[17]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[7] GTX_DUAL:DRP2E[10]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[6] GTX_DUAL:DRP2E[11]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[16]	-	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[8] GTX_DUAL:DRP2E[9]	GTX_DUAL:CHAN_BOND_SEQ_1_4_0[9] GTX_DUAL:DRP2E[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[14]	CRC32_2:CRC_INIT[15]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[1] GTX_DUAL:DRP2E[6]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[0] GTX_DUAL:DRP2E[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[13]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[2] GTX_DUAL:DRP2E[5]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[3] GTX_DUAL:DRP2E[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[12]	-	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[5] GTX_DUAL:DRP2E[2]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[4] GTX_DUAL:DRP2E[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[11]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[6] GTX_DUAL:DRP2E[1]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[7] GTX_DUAL:DRP2E[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[9] GTX_DUAL:DRP2D[14]	GTX_DUAL:CHAN_BOND_SEQ_1_3_0[8] GTX_DUAL:DRP2D[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[10]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[0] GTX_DUAL:DRP2D[13]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[1] GTX_DUAL:DRP2D[12]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[9]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[3] GTX_DUAL:DRP2D[10]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[2] GTX_DUAL:DRP2D[11]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[8]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[4] GTX_DUAL:DRP2D[9]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[5] GTX_DUAL:DRP2D[8]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[7]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[7] GTX_DUAL:DRP2D[6]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[6] GTX_DUAL:DRP2D[7]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[6]	-	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[8] GTX_DUAL:DRP2D[5]	GTX_DUAL:CHAN_BOND_SEQ_1_2_0[9] GTX_DUAL:DRP2D[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[5]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[1] GTX_DUAL:DRP2D[2]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[0] GTX_DUAL:DRP2D[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[4]	-	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[2] GTX_DUAL:DRP2D[1]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[3] GTX_DUAL:DRP2D[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[3]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[5] GTX_DUAL:DRP2C[14]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[4] GTX_DUAL:DRP2C[15]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[2]	-	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[6] GTX_DUAL:DRP2C[13]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[7] GTX_DUAL:DRP2C[12]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[1]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[9] GTX_DUAL:DRP2C[10]	GTX_DUAL:CHAN_BOND_SEQ_1_1_0[8] GTX_DUAL:DRP2C[11]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[0]	GTX_DUAL:CHAN_BOND_MODE_0[1] GTX_DUAL:DRP2C[9]	GTX_DUAL:CHAN_BOND_MODE_0[0] GTX_DUAL:DRP2C[8]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_LEVEL_0[1] GTX_DUAL:DRP2C[6]	GTX_DUAL:CHAN_BOND_LEVEL_0[0] GTX_DUAL:DRP2C[7]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_LEVEL_0[2] GTX_DUAL:DRP2C[5]	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[0] GTX_DUAL:DRP2C[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[2] GTX_DUAL:DRP2C[2]	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[1] GTX_DUAL:DRP2C[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[3] GTX_DUAL:DRP2C[1]	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[0] GTX_DUAL:DRP2C[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[2] GTX_DUAL:DRP2B[14]	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[1] GTX_DUAL:DRP2B[15]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[3] GTX_DUAL:DRP2B[13]	GTX_DUAL:ALIGN_COMMA_WORD_0[0] GTX_DUAL:DRP2B[12]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[10] GTX_DUAL:PMA_COM_CFG[1]	GTX_DUAL:DRP2B[11] GTX_DUAL:PMA_COM_CFG[9]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[9] GTX_DUAL:PMA_COM_CFG[2]	GTX_DUAL:DRP2B[8] GTX_DUAL:PMA_COM_CFG[3]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[6] GTX_DUAL:PMA_COM_CFG[0]	GTX_DUAL:DRP2B[7] GTX_DUAL:PMA_COM_CFG[4]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[5] GTX_DUAL:PMA_COM_CFG[5]	GTX_DUAL:DRP2B[4] GTX_DUAL:PMA_COM_CFG[6]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[2]	GTX_DUAL:DRP2B[3] GTX_DUAL:PMA_COM_CFG[7]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2B[1]	GTX_DUAL:DRP2B[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[14] GTX_DUAL:PMA_COM_CFG[51]	GTX_DUAL:DRP2A[15] GTX_DUAL:PMA_COM_CFG[49]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[13]	GTX_DUAL:DRP2A[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[10]	GTX_DUAL:DRP2A[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[9]	GTX_DUAL:DRP2A[8]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[6] GTX_DUAL:PMA_COM_CFG[67]	GTX_DUAL:DRP2A[7] GTX_DUAL:PMA_COM_CFG[65]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[5] GTX_DUAL:PMA_COM_CFG[59]	GTX_DUAL:DRP2A[4] GTX_DUAL:PMA_COM_CFG[57]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[2] GTX_DUAL:PMA_COM_CFG[60]	GTX_DUAL:DRP2A[3] GTX_DUAL:PMA_COM_CFG[58]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP2A[1] GTX_DUAL:PMA_COM_CFG[55]	GTX_DUAL:DRP2A[0] GTX_DUAL:PMA_COM_CFG[53]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[14] GTX_DUAL:PMA_COM_CFG[33]	GTX_DUAL:DRP29[15] GTX_DUAL:PMA_COM_CFG[35]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[13] GTX_DUAL:PMA_COM_CFG[37]	GTX_DUAL:DRP29[12] GTX_DUAL:PMA_COM_CFG[39]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[10] GTX_DUAL:PMA_COM_CFG[43]	GTX_DUAL:DRP29[11] GTX_DUAL:PMA_COM_CFG[41]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[9] GTX_DUAL:PMA_COM_CFG[45]	GTX_DUAL:DRP29[8] GTX_DUAL:PMA_COM_CFG[47]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[6] GTX_DUAL:TERMINATION_OVRD	GTX_DUAL:DRP29[7] GTX_DUAL:PMA_COM_CFG[32]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[5] GTX_DUAL:TERMINATION_CTRL[0]	GTX_DUAL:DRP29[4] GTX_DUAL:TERMINATION_CTRL[1]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[2] GTX_DUAL:TERMINATION_CTRL[3]	GTX_DUAL:DRP29[3] GTX_DUAL:TERMINATION_CTRL[2]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP29[1] GTX_DUAL:TERMINATION_CTRL[4]	GTX_DUAL:DRP29[0] GTX_DUAL:PLL_DIVSEL_FB[1]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[14] GTX_DUAL:PLL_DIVSEL_FB[3]	GTX_DUAL:DRP28[15] GTX_DUAL:PLL_DIVSEL_FB[2]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[13]	GTX_DUAL:DRP28[12] GTX_DUAL:PLL_DIVSEL_FB[0]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[10] GTX_DUAL:PLL_CP_CFG[1]	GTX_DUAL:DRP28[11] GTX_DUAL:PLL_CP_CFG[0]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[9] GTX_DUAL:PLL_CP_CFG[2]	GTX_DUAL:DRP28[8] GTX_DUAL:PLL_CP_CFG[3]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[6] GTX_DUAL:PLL_CP_CFG[5]	GTX_DUAL:DRP28[7] GTX_DUAL:PLL_CP_CFG[4]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[5] GTX_DUAL:PLL_CP_CFG[6]	GTX_DUAL:DRP28[4] GTX_DUAL:PLL_CP_CFG[7]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[2] GTX_DUAL:PLL_COM_CFG[1]	GTX_DUAL:DRP28[3] GTX_DUAL:PLL_COM_CFG[0]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP28[1] GTX_DUAL:PLL_COM_CFG[2]	GTX_DUAL:DRP28[0] GTX_DUAL:PLL_COM_CFG[3]

virtex5 GTX bittile 11
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_0[6] GTX_DUAL:DRP37[14]	GTX_DUAL:CLK_COR_SEQ_1_1_0[7] GTX_DUAL:DRP37[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_0[5] GTX_DUAL:DRP37[13]	GTX_DUAL:CLK_COR_SEQ_1_1_0[4] GTX_DUAL:DRP37[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_0[2] GTX_DUAL:DRP37[10]	GTX_DUAL:CLK_COR_SEQ_1_1_0[3] GTX_DUAL:DRP37[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_0[1] GTX_DUAL:DRP37[9]	GTX_DUAL:CLK_COR_SEQ_1_1_0[0] GTX_DUAL:DRP37[8]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_0[8] GTX_DUAL:DRP37[6]	GTX_DUAL:CLK_COR_SEQ_1_2_0[9] GTX_DUAL:DRP37[7]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_0[7] GTX_DUAL:DRP37[5]	GTX_DUAL:CLK_COR_SEQ_1_2_0[6] GTX_DUAL:DRP37[4]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_0[4] GTX_DUAL:DRP37[2]	GTX_DUAL:CLK_COR_SEQ_1_2_0[5] GTX_DUAL:DRP37[3]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_0[3] GTX_DUAL:DRP37[1]	GTX_DUAL:CLK_COR_SEQ_1_2_0[2] GTX_DUAL:DRP37[0]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_2_0[0] GTX_DUAL:DRP36[14]	GTX_DUAL:CLK_COR_SEQ_1_2_0[1] GTX_DUAL:DRP36[15]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_0[9] GTX_DUAL:DRP36[13]	GTX_DUAL:CLK_COR_SEQ_1_3_0[8] GTX_DUAL:DRP36[12]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_0[6] GTX_DUAL:DRP36[10]	GTX_DUAL:CLK_COR_SEQ_1_3_0[7] GTX_DUAL:DRP36[11]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_0[5] GTX_DUAL:DRP36[9]	GTX_DUAL:CLK_COR_SEQ_1_3_0[4] GTX_DUAL:DRP36[8]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_0[2] GTX_DUAL:DRP36[6]	GTX_DUAL:CLK_COR_SEQ_1_3_0[3] GTX_DUAL:DRP36[7]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_3_0[1] GTX_DUAL:DRP36[5]	GTX_DUAL:CLK_COR_SEQ_1_3_0[0] GTX_DUAL:DRP36[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_0[8] GTX_DUAL:DRP36[2]	GTX_DUAL:CLK_COR_SEQ_1_4_0[9] GTX_DUAL:DRP36[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_0[7] GTX_DUAL:DRP36[1]	GTX_DUAL:CLK_COR_SEQ_1_4_0[6] GTX_DUAL:DRP36[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_0[4] GTX_DUAL:DRP35[14]	GTX_DUAL:CLK_COR_SEQ_1_4_0[5] GTX_DUAL:DRP35[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_0[3] GTX_DUAL:DRP35[13]	GTX_DUAL:CLK_COR_SEQ_1_4_0[2] GTX_DUAL:DRP35[12]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_4_0[0] GTX_DUAL:DRP35[10]	GTX_DUAL:CLK_COR_SEQ_1_4_0[1] GTX_DUAL:DRP35[11]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[3] GTX_DUAL:DRP35[9]	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[2] GTX_DUAL:DRP35[8]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[0] GTX_DUAL:DRP35[6]	GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[1] GTX_DUAL:DRP35[7]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_0[9] GTX_DUAL:DRP35[5]	GTX_DUAL:CLK_COR_SEQ_2_1_0[8] GTX_DUAL:DRP35[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_0[6] GTX_DUAL:DRP35[2]	GTX_DUAL:CLK_COR_SEQ_2_1_0[7] GTX_DUAL:DRP35[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_0[5] GTX_DUAL:DRP35[1]	GTX_DUAL:CLK_COR_SEQ_2_1_0[4] GTX_DUAL:DRP35[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_0[2] GTX_DUAL:DRP34[14]	GTX_DUAL:CLK_COR_SEQ_2_1_0[3] GTX_DUAL:DRP34[15]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_1_0[1] GTX_DUAL:DRP34[13]	GTX_DUAL:CLK_COR_SEQ_2_1_0[0] GTX_DUAL:DRP34[12]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_0[8] GTX_DUAL:DRP34[10]	GTX_DUAL:CLK_COR_SEQ_2_2_0[9] GTX_DUAL:DRP34[11]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_0[7] GTX_DUAL:DRP34[9]	GTX_DUAL:CLK_COR_SEQ_2_2_0[6] GTX_DUAL:DRP34[8]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_0[4] GTX_DUAL:DRP34[6]	GTX_DUAL:CLK_COR_SEQ_2_2_0[5] GTX_DUAL:DRP34[7]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_0[3] GTX_DUAL:DRP34[5]	GTX_DUAL:CLK_COR_SEQ_2_2_0[2] GTX_DUAL:DRP34[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_2_0[0] GTX_DUAL:DRP34[2]	GTX_DUAL:CLK_COR_SEQ_2_2_0[1] GTX_DUAL:DRP34[3]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_0[9] GTX_DUAL:DRP34[1]	GTX_DUAL:CLK_COR_SEQ_2_3_0[8] GTX_DUAL:DRP34[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_0[6] GTX_DUAL:DRP33[14]	GTX_DUAL:CLK_COR_SEQ_2_3_0[7] GTX_DUAL:DRP33[15]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_0[5] GTX_DUAL:DRP33[13]	GTX_DUAL:CLK_COR_SEQ_2_3_0[4] GTX_DUAL:DRP33[12]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_0[2] GTX_DUAL:DRP33[10]	GTX_DUAL:CLK_COR_SEQ_2_3_0[3] GTX_DUAL:DRP33[11]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_3_0[1] GTX_DUAL:DRP33[9]	GTX_DUAL:CLK_COR_SEQ_2_3_0[0] GTX_DUAL:DRP33[8]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_0[8] GTX_DUAL:DRP33[6]	GTX_DUAL:CLK_COR_SEQ_2_4_0[9] GTX_DUAL:DRP33[7]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_0[7] GTX_DUAL:DRP33[5]	GTX_DUAL:CLK_COR_SEQ_2_4_0[6] GTX_DUAL:DRP33[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_0[4] GTX_DUAL:DRP33[2]	GTX_DUAL:CLK_COR_SEQ_2_4_0[5] GTX_DUAL:DRP33[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_0[3] GTX_DUAL:DRP33[1]	GTX_DUAL:CLK_COR_SEQ_2_4_0[2] GTX_DUAL:DRP33[0]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_4_0[0] GTX_DUAL:DRP32[14]	GTX_DUAL:CLK_COR_SEQ_2_4_0[1] GTX_DUAL:DRP32[15]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[3] GTX_DUAL:DRP32[13]	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[2] GTX_DUAL:DRP32[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[0] GTX_DUAL:DRP32[10]	GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[1] GTX_DUAL:DRP32[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_2_USE_0 GTX_DUAL:DRP32[9]	GTX_DUAL:COM_BURST_VAL_0[3] GTX_DUAL:DRP32[8]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COM_BURST_VAL_0[1] GTX_DUAL:DRP32[6]	GTX_DUAL:COM_BURST_VAL_0[2] GTX_DUAL:DRP32[7]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COM_BURST_VAL_0[0] GTX_DUAL:DRP32[5]	GTX_DUAL:COMMA_10B_ENABLE_0[9] GTX_DUAL:DRP32[4]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_0[7] GTX_DUAL:DRP32[2]	GTX_DUAL:COMMA_10B_ENABLE_0[8] GTX_DUAL:DRP32[3]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_0[6] GTX_DUAL:DRP32[1]	GTX_DUAL:COMMA_10B_ENABLE_0[5] GTX_DUAL:DRP32[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_0[3] GTX_DUAL:DRP31[14]	GTX_DUAL:COMMA_10B_ENABLE_0[4] GTX_DUAL:DRP31[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_10B_ENABLE_0[2] GTX_DUAL:DRP31[13]	GTX_DUAL:COMMA_10B_ENABLE_0[1] GTX_DUAL:DRP31[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:COMMA_DOUBLE_0 GTX_DUAL:DRP31[10]	GTX_DUAL:COMMA_10B_ENABLE_0[0] GTX_DUAL:DRP31[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DEC_MCOMMA_DETECT_0 GTX_DUAL:DRP31[9]	GTX_DUAL:DEC_PCOMMA_DETECT_0 GTX_DUAL:DRP31[8]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP31[6] GTX_DUAL:MCOMMA_10B_VALUE_0[9]	GTX_DUAL:DEC_VALID_COMMA_ONLY_0 GTX_DUAL:DRP31[7]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP31[5] GTX_DUAL:MCOMMA_10B_VALUE_0[8]	GTX_DUAL:DRP31[4] GTX_DUAL:MCOMMA_10B_VALUE_0[7]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP31[2] GTX_DUAL:MCOMMA_10B_VALUE_0[5]	GTX_DUAL:DRP31[3] GTX_DUAL:MCOMMA_10B_VALUE_0[6]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP31[1] GTX_DUAL:MCOMMA_10B_VALUE_0[4]	GTX_DUAL:DRP31[0] GTX_DUAL:MCOMMA_10B_VALUE_0[3]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP30[14] GTX_DUAL:MCOMMA_10B_VALUE_0[1]	GTX_DUAL:DRP30[15] GTX_DUAL:MCOMMA_10B_VALUE_0[2]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP30[13] GTX_DUAL:MCOMMA_10B_VALUE_0[0]	GTX_DUAL:DRP30[12] GTX_DUAL:MCOMMA_DETECT_0
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[0] GTX_DUAL:DRP30[10]	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[9] GTX_DUAL:DRP30[11]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[1] GTX_DUAL:DRP30[9]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[2] GTX_DUAL:DRP30[8]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[31]	-	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[4] GTX_DUAL:DRP30[6]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[3] GTX_DUAL:DRP30[7]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[30]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[5] GTX_DUAL:DRP30[5]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[6] GTX_DUAL:DRP30[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[29]	-	GTX_DUAL:DRP30[2] GTX_DUAL:PLL_FB_DCCEN	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[7] GTX_DUAL:DRP30[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_2:CRC_INIT[28]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[8] GTX_DUAL:DRP30[1]	GTX_DUAL:CHAN_BOND_SEQ_2_2_0[9] GTX_DUAL:DRP30[0]

virtex5 GTX bittile 12
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[14] GTX_DUAL:SATA_MIN_BURST_0[4]	GTX_DUAL:DRP3F[15] GTX_DUAL:SATA_MIN_BURST_0[5]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[13] GTX_DUAL:SATA_MIN_BURST_0[3]	GTX_DUAL:DRP3F[12] GTX_DUAL:SATA_MIN_BURST_0[2]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[10] GTX_DUAL:SATA_MIN_BURST_0[0]	GTX_DUAL:DRP3F[11] GTX_DUAL:SATA_MIN_BURST_0[1]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[9] GTX_DUAL:SATA_MIN_INIT_0[5]	GTX_DUAL:DRP3F[8] GTX_DUAL:SATA_MIN_INIT_0[4]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[6] GTX_DUAL:SATA_MIN_INIT_0[2]	GTX_DUAL:DRP3F[7] GTX_DUAL:SATA_MIN_INIT_0[3]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[5] GTX_DUAL:SATA_MIN_INIT_0[1]	GTX_DUAL:DRP3F[4] GTX_DUAL:SATA_MIN_INIT_0[0]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[2] GTX_DUAL:SATA_MIN_WAKE_0[4]	GTX_DUAL:DRP3F[3] GTX_DUAL:SATA_MIN_WAKE_0[5]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3F[1] GTX_DUAL:SATA_MIN_WAKE_0[3]	GTX_DUAL:DRP3F[0] GTX_DUAL:SATA_MIN_WAKE_0[2]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[14] GTX_DUAL:SATA_MIN_WAKE_0[0]	GTX_DUAL:DRP3E[15] GTX_DUAL:SATA_MIN_WAKE_0[1]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[13] GTX_DUAL:TERMINATION_IMP_0[0]	GTX_DUAL:DRP3E[12] GTX_DUAL:TRANS_TIME_FROM_P2_0[11]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[10] GTX_DUAL:TRANS_TIME_FROM_P2_0[9]	GTX_DUAL:DRP3E[11] GTX_DUAL:TRANS_TIME_FROM_P2_0[10]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[9] GTX_DUAL:TRANS_TIME_FROM_P2_0[8]	GTX_DUAL:DRP3E[8] GTX_DUAL:TRANS_TIME_FROM_P2_0[7]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[6] GTX_DUAL:TRANS_TIME_FROM_P2_0[5]	GTX_DUAL:DRP3E[7] GTX_DUAL:TRANS_TIME_FROM_P2_0[6]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[5] GTX_DUAL:TRANS_TIME_FROM_P2_0[4]	GTX_DUAL:DRP3E[4] GTX_DUAL:TRANS_TIME_FROM_P2_0[3]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[2] GTX_DUAL:TRANS_TIME_FROM_P2_0[1]	GTX_DUAL:DRP3E[3] GTX_DUAL:TRANS_TIME_FROM_P2_0[2]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3E[1] GTX_DUAL:TRANS_TIME_FROM_P2_0[0]	GTX_DUAL:DRP3E[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[14]	GTX_DUAL:DRP3D[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[13]	GTX_DUAL:DRP3D[12] GTX_DUAL:TRANS_TIME_NON_P2_0[7]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[10] GTX_DUAL:TRANS_TIME_NON_P2_0[5]	GTX_DUAL:DRP3D[11] GTX_DUAL:TRANS_TIME_NON_P2_0[6]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[9] GTX_DUAL:TRANS_TIME_NON_P2_0[4]	GTX_DUAL:DRP3D[8] GTX_DUAL:TRANS_TIME_NON_P2_0[3]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[6] GTX_DUAL:TRANS_TIME_NON_P2_0[1]	GTX_DUAL:DRP3D[7] GTX_DUAL:TRANS_TIME_NON_P2_0[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3D[5] GTX_DUAL:TRANS_TIME_NON_P2_0[0]	GTX_DUAL:DRP3D[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CDR_PH_ADJ_TIME[3] GTX_DUAL:DRP3D[2]	GTX_DUAL:CDR_PH_ADJ_TIME[4] GTX_DUAL:DRP3D[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CDR_PH_ADJ_TIME[2] GTX_DUAL:DRP3D[1]	GTX_DUAL:CDR_PH_ADJ_TIME[1] GTX_DUAL:DRP3D[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[14]	GTX_DUAL:CDR_PH_ADJ_TIME[0] GTX_DUAL:DRP3C[15]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[13]	GTX_DUAL:DRP3C[12] GTX_DUAL:TRANS_TIME_TO_P2_0[9]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[10] GTX_DUAL:TRANS_TIME_TO_P2_0[7]	GTX_DUAL:DRP3C[11] GTX_DUAL:TRANS_TIME_TO_P2_0[8]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[9] GTX_DUAL:TRANS_TIME_TO_P2_0[6]	GTX_DUAL:DRP3C[8] GTX_DUAL:TRANS_TIME_TO_P2_0[5]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[6] GTX_DUAL:TRANS_TIME_TO_P2_0[3]	GTX_DUAL:DRP3C[7] GTX_DUAL:TRANS_TIME_TO_P2_0[4]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3C[5] GTX_DUAL:TRANS_TIME_TO_P2_0[2]	GTX_DUAL:DRP3C[4] GTX_DUAL:TRANS_TIME_TO_P2_0[1]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CAL_TIME[4] GTX_DUAL:DRP3C[2]	GTX_DUAL:DRP3C[3] GTX_DUAL:TRANS_TIME_TO_P2_0[0]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CAL_TIME[3] GTX_DUAL:DRP3C[1]	GTX_DUAL:DFE_CAL_TIME[2] GTX_DUAL:DRP3C[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CAL_TIME[0] GTX_DUAL:DRP3B[14]	GTX_DUAL:DFE_CAL_TIME[1] GTX_DUAL:DRP3B[15]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[13]	GTX_DUAL:DRP3B[12] GTX_DUAL:TX_BUFFER_USE_0
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[10] GTX_DUAL:TX_DETECT_RX_CFG_0[12]	GTX_DUAL:DRP3B[11] GTX_DUAL:TX_DETECT_RX_CFG_0[13]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[9] GTX_DUAL:TX_DETECT_RX_CFG_0[11]	GTX_DUAL:DRP3B[8] GTX_DUAL:TX_DETECT_RX_CFG_0[10]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[6] GTX_DUAL:TX_DETECT_RX_CFG_0[8]	GTX_DUAL:DRP3B[7] GTX_DUAL:TX_DETECT_RX_CFG_0[9]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[5] GTX_DUAL:TX_DETECT_RX_CFG_0[7]	GTX_DUAL:DRP3B[4] GTX_DUAL:TX_DETECT_RX_CFG_0[6]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[2] GTX_DUAL:TX_DETECT_RX_CFG_0[4]	GTX_DUAL:DRP3B[3] GTX_DUAL:TX_DETECT_RX_CFG_0[5]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3B[1] GTX_DUAL:TX_DETECT_RX_CFG_0[3]	GTX_DUAL:DRP3B[0] GTX_DUAL:TX_DETECT_RX_CFG_0[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[14] GTX_DUAL:TX_DETECT_RX_CFG_0[0]	GTX_DUAL:DRP3A[15] GTX_DUAL:TX_DETECT_RX_CFG_0[1]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[13] GTX_DUAL:TXRX_INVERT_0[2]	GTX_DUAL:DRP3A[12] GTX_DUAL:TXRX_INVERT_0[1]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[10] GTX_DUAL:RX_EN_IDLE_RESET_FR	GTX_DUAL:DRP3A[11] GTX_DUAL:TXRX_INVERT_0[0]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[9] GTX_DUAL:RX_EN_IDLE_HOLD_CDR	GTX_DUAL:DRP3A[8] GTX_DUAL:TX_XCLK_SEL_0[0]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[6] GTX_DUAL:PMA_COM_CFG[19]	GTX_DUAL:DRP3A[7] GTX_DUAL:TXOUTCLK_SEL_0
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[5] GTX_DUAL:OOBDETECT_THRESHOLD_0[2]	GTX_DUAL:DRP3A[4] GTX_DUAL:OOBDETECT_THRESHOLD_0[1]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP3A[2] GTX_DUAL:RX_EN_IDLE_RESET_PH	GTX_DUAL:DRP3A[3] GTX_DUAL:OOBDETECT_THRESHOLD_0[0]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[3] GTX_DUAL:DRP3A[1]	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[2] GTX_DUAL:DRP3A[0]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[0] GTX_DUAL:DRP39[14]	GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[1] GTX_DUAL:DRP39[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_USE_0 GTX_DUAL:DRP39[13]	GTX_DUAL:CHAN_BOND_SEQ_LEN_0[1] GTX_DUAL:DRP39[12]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_ADJ_LEN_0[1] GTX_DUAL:DRP39[10]	GTX_DUAL:CHAN_BOND_SEQ_LEN_0[0] GTX_DUAL:DRP39[11]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_ADJ_LEN_0[0] GTX_DUAL:DRP39[9]	GTX_DUAL:CLK_COR_DET_LEN_0[1] GTX_DUAL:DRP39[8]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_0 GTX_DUAL:DRP39[6]	GTX_DUAL:CLK_COR_DET_LEN_0[0] GTX_DUAL:DRP39[7]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_KEEP_IDLE_0 GTX_DUAL:DRP39[5]	GTX_DUAL:CLK_COR_MAX_LAT_0[5] GTX_DUAL:DRP39[4]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MAX_LAT_0[3] GTX_DUAL:DRP39[2]	GTX_DUAL:CLK_COR_MAX_LAT_0[4] GTX_DUAL:DRP39[3]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MAX_LAT_0[2] GTX_DUAL:DRP39[1]	GTX_DUAL:CLK_COR_MAX_LAT_0[1] GTX_DUAL:DRP39[0]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_0[5] GTX_DUAL:DRP38[14]	GTX_DUAL:CLK_COR_MAX_LAT_0[0] GTX_DUAL:DRP38[15]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_0[4] GTX_DUAL:DRP38[13]	GTX_DUAL:CLK_COR_MIN_LAT_0[3] GTX_DUAL:DRP38[12]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_0[1] GTX_DUAL:DRP38[10]	GTX_DUAL:CLK_COR_MIN_LAT_0[2] GTX_DUAL:DRP38[11]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_MIN_LAT_0[0] GTX_DUAL:DRP38[9]	GTX_DUAL:CLK_COR_PRECEDENCE_0 GTX_DUAL:DRP38[8]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_0[4] GTX_DUAL:DRP38[6]	GTX_DUAL:CLK_CORRECT_USE_0 GTX_DUAL:DRP38[7]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_0[3] GTX_DUAL:DRP38[5]	GTX_DUAL:CLK_COR_REPEAT_WAIT_0[2] GTX_DUAL:DRP38[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_REPEAT_WAIT_0[0] GTX_DUAL:DRP38[2]	GTX_DUAL:CLK_COR_REPEAT_WAIT_0[1] GTX_DUAL:DRP38[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CLK_COR_SEQ_1_1_0[9] GTX_DUAL:DRP38[1]	GTX_DUAL:CLK_COR_SEQ_1_1_0[8] GTX_DUAL:DRP38[0]

virtex5 GTX bittile 13
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[5] GTX_DUAL:DRP47[14]	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[4] GTX_DUAL:DRP47[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[6] GTX_DUAL:DRP47[13]	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[7] GTX_DUAL:DRP47[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[9] GTX_DUAL:DRP47[10]	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[8] GTX_DUAL:DRP47[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[0] GTX_DUAL:DRP47[9]	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[1] GTX_DUAL:DRP47[8]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[3] GTX_DUAL:DRP47[6]	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[2] GTX_DUAL:DRP47[7]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[4] GTX_DUAL:DRP47[5]	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[5] GTX_DUAL:DRP47[4]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[7] GTX_DUAL:DRP47[2]	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[6] GTX_DUAL:DRP47[3]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_3_0[8] GTX_DUAL:DRP47[1]	GTX_DUAL:DRP47[0]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[14] GTX_DUAL:PCOMMA_10B_VALUE_0[9]	GTX_DUAL:DRP46[15] GTX_DUAL:PCI_EXPRESS_MODE_0
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[13] GTX_DUAL:PCOMMA_10B_VALUE_0[8]	GTX_DUAL:DRP46[12] GTX_DUAL:PCOMMA_10B_VALUE_0[7]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[10] GTX_DUAL:PCOMMA_10B_VALUE_0[5]	GTX_DUAL:DRP46[11] GTX_DUAL:PCOMMA_10B_VALUE_0[6]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[9] GTX_DUAL:PCOMMA_10B_VALUE_0[4]	GTX_DUAL:DRP46[8] GTX_DUAL:PCOMMA_10B_VALUE_0[3]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[6] GTX_DUAL:PCOMMA_10B_VALUE_0[1]	GTX_DUAL:DRP46[7] GTX_DUAL:PCOMMA_10B_VALUE_0[2]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[5] GTX_DUAL:PCOMMA_10B_VALUE_0[0]	GTX_DUAL:DRP46[4] GTX_DUAL:PCOMMA_DETECT_0
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[2] GTX_DUAL:PLL_RXDIVSEL_OUT_0[0]	GTX_DUAL:DRP46[3] GTX_DUAL:PLL_RXDIVSEL_OUT_0[1]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP46[1] GTX_DUAL:PLL_SATA_0	GTX_DUAL:DRP46[0] GTX_DUAL:PLL_TXDIVSEL_OUT_0[1]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[14] GTX_DUAL:PMA_CDR_SCAN_0[26]	GTX_DUAL:DRP45[15] GTX_DUAL:PLL_TXDIVSEL_OUT_0[0]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[13] GTX_DUAL:PMA_CDR_SCAN_0[25]	GTX_DUAL:DRP45[12] GTX_DUAL:PMA_CDR_SCAN_0[24]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[10] GTX_DUAL:PMA_CDR_SCAN_0[22]	GTX_DUAL:DRP45[11] GTX_DUAL:PMA_CDR_SCAN_0[23]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[9] GTX_DUAL:PMA_CDR_SCAN_0[21]	GTX_DUAL:DRP45[8] GTX_DUAL:PMA_CDR_SCAN_0[20]
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[6] GTX_DUAL:PMA_CDR_SCAN_0[18]	GTX_DUAL:DRP45[7] GTX_DUAL:PMA_CDR_SCAN_0[19]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[5] GTX_DUAL:PMA_CDR_SCAN_0[17]	GTX_DUAL:DRP45[4] GTX_DUAL:PMA_CDR_SCAN_0[16]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[2] GTX_DUAL:PMA_CDR_SCAN_0[14]	GTX_DUAL:DRP45[3] GTX_DUAL:PMA_CDR_SCAN_0[15]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP45[1] GTX_DUAL:PMA_CDR_SCAN_0[13]	GTX_DUAL:DRP45[0] GTX_DUAL:PMA_CDR_SCAN_0[12]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[14] GTX_DUAL:PMA_CDR_SCAN_0[10]	GTX_DUAL:DRP44[15] GTX_DUAL:PMA_CDR_SCAN_0[11]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[13] GTX_DUAL:PMA_CDR_SCAN_0[9]	GTX_DUAL:DRP44[12] GTX_DUAL:PMA_CDR_SCAN_0[8]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[10] GTX_DUAL:PMA_CDR_SCAN_0[6]	GTX_DUAL:DRP44[11] GTX_DUAL:PMA_CDR_SCAN_0[7]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[9] GTX_DUAL:PMA_CDR_SCAN_0[5]	GTX_DUAL:DRP44[8] GTX_DUAL:PMA_CDR_SCAN_0[4]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[6] GTX_DUAL:PMA_CDR_SCAN_0[2]	GTX_DUAL:DRP44[7] GTX_DUAL:PMA_CDR_SCAN_0[3]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[5] GTX_DUAL:PMA_CDR_SCAN_0[1]	GTX_DUAL:DRP44[4] GTX_DUAL:PMA_CDR_SCAN_0[0]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[2] GTX_DUAL:PRBS_ERR_THRESHOLD_0[30]	GTX_DUAL:DRP44[3] GTX_DUAL:PRBS_ERR_THRESHOLD_0[31]
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP44[1] GTX_DUAL:PRBS_ERR_THRESHOLD_0[29]	GTX_DUAL:DRP44[0] GTX_DUAL:PRBS_ERR_THRESHOLD_0[28]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[14] GTX_DUAL:PRBS_ERR_THRESHOLD_0[26]	GTX_DUAL:DRP43[15] GTX_DUAL:PRBS_ERR_THRESHOLD_0[27]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[13] GTX_DUAL:PRBS_ERR_THRESHOLD_0[25]	GTX_DUAL:DRP43[12] GTX_DUAL:PRBS_ERR_THRESHOLD_0[24]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[10] GTX_DUAL:PRBS_ERR_THRESHOLD_0[22]	GTX_DUAL:DRP43[11] GTX_DUAL:PRBS_ERR_THRESHOLD_0[23]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[9] GTX_DUAL:PRBS_ERR_THRESHOLD_0[21]	GTX_DUAL:DRP43[8] GTX_DUAL:PRBS_ERR_THRESHOLD_0[20]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[6] GTX_DUAL:PRBS_ERR_THRESHOLD_0[18]	GTX_DUAL:DRP43[7] GTX_DUAL:PRBS_ERR_THRESHOLD_0[19]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[5] GTX_DUAL:PRBS_ERR_THRESHOLD_0[17]	GTX_DUAL:DRP43[4] GTX_DUAL:PRBS_ERR_THRESHOLD_0[16]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[2] GTX_DUAL:PRBS_ERR_THRESHOLD_0[14]	GTX_DUAL:DRP43[3] GTX_DUAL:PRBS_ERR_THRESHOLD_0[15]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP43[1] GTX_DUAL:PRBS_ERR_THRESHOLD_0[13]	GTX_DUAL:DRP43[0] GTX_DUAL:PRBS_ERR_THRESHOLD_0[12]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[14] GTX_DUAL:PRBS_ERR_THRESHOLD_0[10]	GTX_DUAL:DRP42[15] GTX_DUAL:PRBS_ERR_THRESHOLD_0[11]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[13] GTX_DUAL:PRBS_ERR_THRESHOLD_0[9]	GTX_DUAL:DRP42[12] GTX_DUAL:PRBS_ERR_THRESHOLD_0[8]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[10] GTX_DUAL:PRBS_ERR_THRESHOLD_0[6]	GTX_DUAL:DRP42[11] GTX_DUAL:PRBS_ERR_THRESHOLD_0[7]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[9] GTX_DUAL:PRBS_ERR_THRESHOLD_0[5]	GTX_DUAL:DRP42[8] GTX_DUAL:PRBS_ERR_THRESHOLD_0[4]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[6] GTX_DUAL:PRBS_ERR_THRESHOLD_0[2]	GTX_DUAL:DRP42[7] GTX_DUAL:PRBS_ERR_THRESHOLD_0[3]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[5] GTX_DUAL:PRBS_ERR_THRESHOLD_0[1]	GTX_DUAL:DRP42[4] GTX_DUAL:PRBS_ERR_THRESHOLD_0[0]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[2] GTX_DUAL:RX_DECODE_SEQ_MATCH_0	GTX_DUAL:DRP42[3] GTX_DUAL:RX_BUFFER_USE_0
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP42[1] GTX_DUAL:RX_LOS_INVALID_INCR_0[2]	GTX_DUAL:DRP42[0] GTX_DUAL:RX_LOS_INVALID_INCR_0[1]
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[14] GTX_DUAL:RX_LOSS_OF_SYNC_FSM_0	GTX_DUAL:DRP41[15] GTX_DUAL:RX_LOS_INVALID_INCR_0[0]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[13] GTX_DUAL:RX_LOS_THRESHOLD_0[2]	GTX_DUAL:DRP41[12] GTX_DUAL:RX_LOS_THRESHOLD_0[1]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[10] GTX_DUAL:RX_SLIDE_MODE_0[0]	GTX_DUAL:DRP41[11] GTX_DUAL:RX_LOS_THRESHOLD_0[0]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[9] GTX_DUAL:RX_STATUS_FMT_0[0]	GTX_DUAL:DRP41[8] GTX_DUAL:RX_XCLK_SEL_0[0]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[6] GTX_DUAL:SATA_BURST_VAL_0[1]	GTX_DUAL:DRP41[7] GTX_DUAL:SATA_BURST_VAL_0[2]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[5] GTX_DUAL:SATA_BURST_VAL_0[0]	GTX_DUAL:DRP41[4] GTX_DUAL:SATA_IDLE_VAL_0[2]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[2] GTX_DUAL:SATA_IDLE_VAL_0[0]	GTX_DUAL:DRP41[3] GTX_DUAL:SATA_IDLE_VAL_0[1]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP41[1] GTX_DUAL:SATA_MAX_BURST_0[5]	GTX_DUAL:DRP41[0] GTX_DUAL:SATA_MAX_BURST_0[4]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[14] GTX_DUAL:SATA_MAX_BURST_0[2]	GTX_DUAL:DRP40[15] GTX_DUAL:SATA_MAX_BURST_0[3]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[13] GTX_DUAL:SATA_MAX_BURST_0[1]	GTX_DUAL:DRP40[12] GTX_DUAL:SATA_MAX_BURST_0[0]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[10] GTX_DUAL:SATA_MAX_INIT_0[4]	GTX_DUAL:DRP40[11] GTX_DUAL:SATA_MAX_INIT_0[5]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[9] GTX_DUAL:SATA_MAX_INIT_0[3]	GTX_DUAL:DRP40[8] GTX_DUAL:SATA_MAX_INIT_0[2]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[6] GTX_DUAL:SATA_MAX_INIT_0[0]	GTX_DUAL:DRP40[7] GTX_DUAL:SATA_MAX_INIT_0[1]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[5] GTX_DUAL:SATA_MAX_WAKE_0[5]	GTX_DUAL:DRP40[4] GTX_DUAL:SATA_MAX_WAKE_0[4]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[2] GTX_DUAL:SATA_MAX_WAKE_0[2]	GTX_DUAL:DRP40[3] GTX_DUAL:SATA_MAX_WAKE_0[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP40[1] GTX_DUAL:SATA_MAX_WAKE_0[1]	GTX_DUAL:DRP40[0] GTX_DUAL:SATA_MAX_WAKE_0[0]

virtex5 GTX bittile 14
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[14]	GTX_DUAL:DRP4F[15]
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[13]	GTX_DUAL:DRP4F[12]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[10]	GTX_DUAL:DRP4F[11]
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[9] GTX_DUAL:PMA_TX_CFG_0[19]	GTX_DUAL:DRP4F[8] GTX_DUAL:PMA_TX_CFG_0[18]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[6] GTX_DUAL:PMA_TX_CFG_0[16]	GTX_DUAL:DRP4F[7] GTX_DUAL:PMA_TX_CFG_0[17]
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[5] GTX_DUAL:PMA_TX_CFG_0[15]	GTX_DUAL:DRP4F[4] GTX_DUAL:PMA_TX_CFG_0[14]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[2] GTX_DUAL:PMA_TX_CFG_0[12]	GTX_DUAL:DRP4F[3] GTX_DUAL:PMA_TX_CFG_0[13]
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4F[1] GTX_DUAL:PMA_TX_CFG_0[11]	GTX_DUAL:DRP4F[0] GTX_DUAL:PMA_TX_CFG_0[10]
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4E[14] GTX_DUAL:PMA_TX_CFG_0[8]	GTX_DUAL:DRP4E[15] GTX_DUAL:PMA_TX_CFG_0[9]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4E[13] GTX_DUAL:PMA_TX_CFG_0[7]	GTX_DUAL:DRP4E[12] GTX_DUAL:PMA_TX_CFG_0[6]
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4E[10] GTX_DUAL:PMA_TX_CFG_0[4]	GTX_DUAL:DRP4E[11] GTX_DUAL:PMA_TX_CFG_0[5]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4E[9] GTX_DUAL:PMA_TX_CFG_0[3]	GTX_DUAL:DRP4E[8] GTX_DUAL:PMA_TX_CFG_0[2]
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4E[6] GTX_DUAL:PMA_TX_CFG_0[0]	GTX_DUAL:DRP4E[7] GTX_DUAL:PMA_TX_CFG_0[1]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CM_TRIM_0[1] GTX_DUAL:DRP4E[5]	GTX_DUAL:CM_TRIM_0[0] GTX_DUAL:DRP4E[4]
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_0[8] GTX_DUAL:DRP4E[2]	GTX_DUAL:DFE_CFG_0[9] GTX_DUAL:DRP4E[3]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_0[7] GTX_DUAL:DRP4E[1]	GTX_DUAL:DFE_CFG_0[6] GTX_DUAL:DRP4E[0]
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_0[4] GTX_DUAL:DRP4D[14]	GTX_DUAL:DFE_CFG_0[5] GTX_DUAL:DRP4D[15]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_0[3] GTX_DUAL:DRP4D[13]	GTX_DUAL:DFE_CFG_0[2] GTX_DUAL:DRP4D[12]
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DFE_CFG_0[0] GTX_DUAL:DRP4D[10]	GTX_DUAL:DFE_CFG_0[1] GTX_DUAL:DRP4D[11]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4D[9] GTX_DUAL:TXGEARBOX_USE_0	GTX_DUAL:DRP4D[8] GTX_DUAL:RXGEARBOX_USE_0
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4D[6] GTX_DUAL:GEARBOX_ENDEC_0[1]	GTX_DUAL:DRP4D[7] GTX_DUAL:GEARBOX_ENDEC_0[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4D[5] GTX_DUAL:GEARBOX_ENDEC_0[0]	GTX_DUAL:CHAN_BOND_KEEP_ALIGN_0 GTX_DUAL:DRP4D[4]
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CB2_INH_CC_PERIOD_0[2] GTX_DUAL:DRP4D[2]	GTX_DUAL:CB2_INH_CC_PERIOD_0[3] GTX_DUAL:DRP4D[3]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CB2_INH_CC_PERIOD_0[1] GTX_DUAL:DRP4D[1]	GTX_DUAL:CB2_INH_CC_PERIOD_0[0] GTX_DUAL:DRP4D[0]
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[14] GTX_DUAL:RX_IDLE_LO_CNT_0[2]	GTX_DUAL:DRP4C[15] GTX_DUAL:RX_IDLE_LO_CNT_0[3]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[13] GTX_DUAL:RX_IDLE_LO_CNT_0[1]	GTX_DUAL:DRP4C[12] GTX_DUAL:RX_IDLE_LO_CNT_0[0]
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[10]	GTX_DUAL:DRP4C[11]
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[9] GTX_DUAL:RX_IDLE_HI_CNT_0[3]	GTX_DUAL:DRP4C[8] GTX_DUAL:RX_IDLE_HI_CNT_0[2]
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[6] GTX_DUAL:RX_IDLE_HI_CNT_0[0]	GTX_DUAL:DRP4C[7] GTX_DUAL:RX_IDLE_HI_CNT_0[1]
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[5]	GTX_DUAL:DRP4C[4]
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[2]	GTX_DUAL:DRP4C[3] GTX_DUAL:RX_EN_IDLE_RESET_BUF_0
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4C[1] GTX_DUAL:RX_EN_IDLE_HOLD_DFE_0	GTX_DUAL:DRP4C[0]
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[14] GTX_DUAL:PMA_RXSYNC_CFG_0[5]	GTX_DUAL:DRP4B[15] GTX_DUAL:PMA_RXSYNC_CFG_0[6]
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[13] GTX_DUAL:PMA_RXSYNC_CFG_0[4]	GTX_DUAL:DRP4B[12] GTX_DUAL:PMA_RXSYNC_CFG_0[3]
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[10] GTX_DUAL:PMA_RXSYNC_CFG_0[1]	GTX_DUAL:DRP4B[11] GTX_DUAL:PMA_RXSYNC_CFG_0[2]
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[9] GTX_DUAL:PMA_RXSYNC_CFG_0[0]	GTX_DUAL:DRP4B[8] GTX_DUAL:TX_IDLE_DELAY_0[2]
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[6] GTX_DUAL:TX_IDLE_DELAY_0[0]	GTX_DUAL:DRP4B[7] GTX_DUAL:TX_IDLE_DELAY_0[1]
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[5]	GTX_DUAL:DRP4B[4]
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[2]	GTX_DUAL:DRP4B[3]
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4B[1]	GTX_DUAL:DRP4B[0] GTX_DUAL:PLL_TDCC_CFG[2]
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[14] GTX_DUAL:PLL_TDCC_CFG[1]	GTX_DUAL:DRP4A[15] GTX_DUAL:PLL_TDCC_CFG[0]
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[13]	GTX_DUAL:DRP4A[12]
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[10] GTX_DUAL:PLL_STARTUP_EN	GTX_DUAL:DRP4A[11]
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[9]	GTX_DUAL:DRP4A[8]
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[6] GTX_DUAL:PMA_COM_CFG[31]	GTX_DUAL:DRP4A[7] GTX_DUAL:PMA_COM_CFG[20]
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[5] GTX_DUAL:PMA_COM_CFG[30]	GTX_DUAL:DRP4A[4] GTX_DUAL:PMA_COM_CFG[29]
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[2] GTX_DUAL:PMA_COM_CFG[27]	GTX_DUAL:DRP4A[3] GTX_DUAL:PMA_COM_CFG[28]
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP4A[1] GTX_DUAL:RCV_TERM_VTTRX_0	GTX_DUAL:DRP4A[0] GTX_DUAL:RCV_TERM_GND_0
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:AC_CAP_DIS_0 GTX_DUAL:DRP49[14]	GTX_DUAL:DRP49[15]
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[13] GTX_DUAL:PMA_RX_CFG_1[12]	GTX_DUAL:DRP49[12] GTX_DUAL:PMA_RX_CFG_1[24]
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[10] GTX_DUAL:PMA_RX_CFG_1[0]	GTX_DUAL:DRP49[11] GTX_DUAL:PMA_RX_CFG_1[1]
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[9] GTX_DUAL:PMA_RX_CFG_1[11]	GTX_DUAL:DRP49[8] GTX_DUAL:PMA_RX_CFG_0[22]
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[6] GTX_DUAL:PMA_RX_CFG_0[20]	GTX_DUAL:DRP49[7] GTX_DUAL:PMA_RX_CFG_0[21]
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[5] GTX_DUAL:PMA_RX_CFG_0[19]	GTX_DUAL:DRP49[4] GTX_DUAL:PMA_RX_CFG_0[18]
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[2] GTX_DUAL:PMA_RX_CFG_0[16]	GTX_DUAL:DRP49[3] GTX_DUAL:PMA_RX_CFG_0[17]
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP49[1] GTX_DUAL:PMA_RX_CFG_0[15]	GTX_DUAL:DRP49[0] GTX_DUAL:PMA_RX_CFG_0[14]
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[14] GTX_DUAL:RX_CDR_FORCE_ROTATE_0	GTX_DUAL:DRP48[15] GTX_DUAL:PMA_RX_CFG_0[13]
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[13] GTX_DUAL:PMA_RX_CFG_0[5]	GTX_DUAL:DRP48[12] GTX_DUAL:PMA_RX_CFG_0[4]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[10] GTX_DUAL:PMA_RX_CFG_0[2]	GTX_DUAL:DRP48[11] GTX_DUAL:PMA_RX_CFG_0[3]
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[9] GTX_DUAL:PMA_RX_CFG_1[23]	GTX_DUAL:DRP48[8] GTX_DUAL:PMA_RX_CFG_0[10]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[6] GTX_DUAL:PMA_RX_CFG_0[8]	GTX_DUAL:DRP48[7] GTX_DUAL:PMA_RX_CFG_0[9]
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:DRP48[5] GTX_DUAL:PMA_RX_CFG_0[7]	GTX_DUAL:DRP48[4] GTX_DUAL:PMA_RX_CFG_0[6]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[1] GTX_DUAL:DRP48[2]	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[0] GTX_DUAL:DRP48[3]
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[2] GTX_DUAL:DRP48[1]	GTX_DUAL:CHAN_BOND_SEQ_2_4_0[3] GTX_DUAL:DRP48[0]

virtex5 GTX bittile 15
Bit	Frame
Bit

virtex5 GTX bittile 16
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[11]
61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[10]
59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[9]
57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[8]
54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[7]
52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[6]
50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[5]
48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[4]
46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[3]
44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[2]
42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[1]
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[0]
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

virtex5 GTX bittile 17
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29
41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:ENABLE64
40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[31]	-
38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[30]	-
36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[29]	-
34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[28]	-
32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[27]	-
30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[26]	-
27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[25]	-
26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[24]	-
23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[23]	-
21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[22]	-
19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[21]	-
17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[20]	-
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[19]	-
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[18]	-
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[17]	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[16]	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[15]
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[14]
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[13]
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	CRC32_3:CRC_INIT[12]

virtex5 GTX bittile 18
Bit	Frame
Bit

virtex5 GTX bittile 19
Bit	Frame
Bit

virtex5 GTX bittile 20
Bit	Frame
Bit	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28
15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:USRCLK0	~CRC32_0:INV.CRCCLK	-	-	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~CRC32_2:INV.CRCCLK	-	-	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	~CRC32_3:INV.CRCCLK	GTX_DUAL:INV.DCLK	GTX_DUAL:INV.TXUSRCLK1	GTX_DUAL:INV.RXUSRCLK1	GTX_DUAL:INV.RXUSRCLK20	GTX_DUAL:INV.TXUSRCLK20	-	-	-	-	-
12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	GTX_DUAL:USRCLK1	~CRC32_1:INV.CRCCLK	GTX_DUAL:INV.TXUSRCLK21	GTX_DUAL:INV.RXUSRCLK21	GTX_DUAL:INV.RXUSRCLK0	GTX_DUAL:INV.TXUSRCLK0	-	-	-	-	GTX_DUAL:ENABLE
11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

CRC32_0:CRC_INIT	2.28.24	2.28.26	2.28.28	2.28.30	2.28.32	2.28.35	2.28.36	2.28.39	2.28.41	2.28.43	2.28.45	2.28.47	2.28.49	2.28.51	2.28.53	2.28.55	2.29.57	2.29.59	2.29.61	2.29.63	3.29.1	3.29.3	3.29.5	3.29.8	3.29.10	3.29.12	3.29.14	3.29.16	3.29.18	3.29.20	3.29.22	3.29.24
CRC32_1:CRC_INIT	8.28.60	8.29.61	8.28.62	8.29.63	9.28.0	9.29.1	9.28.3	9.29.3	9.28.4	9.29.6	9.28.6	9.29.7	9.28.8	9.28.9	9.29.10	9.28.11	9.29.12	9.28.12	9.29.13	9.28.14	9.29.15	9.28.17	9.29.18	9.28.19	9.29.20	9.28.21	9.29.22	9.28.23	9.29.24	9.28.25	9.29.26	9.29.27
CRC32_2:CRC_INIT	11.28.3	11.29.2	11.28.1	11.29.0	10.28.63	10.29.62	10.28.60	10.29.60	10.28.59	10.29.57	10.28.57	10.29.56	10.28.55	10.28.54	10.29.53	10.28.52	10.29.51	10.28.51	10.29.50	10.28.49	10.29.48	10.28.46	10.29.45	10.28.44	10.29.43	10.28.42	10.29.41	10.28.40	10.29.39	10.28.38	10.29.37	10.29.36
CRC32_3:CRC_INIT	17.28.39	17.28.37	17.28.35	17.28.33	17.28.31	17.28.28	17.28.27	17.28.24	17.28.22	17.28.20	17.28.18	17.28.16	17.28.14	17.28.12	17.28.10	17.28.8	17.29.6	17.29.4	17.29.2	17.29.0	16.29.62	16.29.60	16.29.58	16.29.55	16.29.53	16.29.51	16.29.49	16.29.47	16.29.45	16.29.43	16.29.41	16.29.39
GTX_DUAL:PRBS_ERR_THRESHOLD_0	13.31.33	13.30.33	13.30.32	13.31.32	13.31.31	13.30.31	13.30.30	13.31.30	13.31.29	13.30.29	13.30.28	13.31.28	13.31.27	13.30.27	13.30.26	13.31.26	13.31.25	13.30.25	13.30.24	13.31.24	13.31.23	13.30.23	13.30.22	13.31.22	13.31.21	13.30.21	13.30.20	13.31.20	13.31.19	13.30.19	13.30.18	13.31.18
GTX_DUAL:PRBS_ERR_THRESHOLD_1	6.31.30	6.30.30	6.30.31	6.31.31	6.31.32	6.30.32	6.30.33	6.31.33	6.31.34	6.30.34	6.30.35	6.31.35	6.31.36	6.30.36	6.30.37	6.31.37	6.31.38	6.30.38	6.30.39	6.31.39	6.31.40	6.30.40	6.30.41	6.31.41	6.31.42	6.30.42	6.30.43	6.31.43	6.31.44	6.30.44	6.30.45	6.31.45
non-inverted	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

CRC32_0:ENABLE64	2.29.22
CRC32_3:ENABLE64	17.29.41
GTX_DUAL:AC_CAP_DIS_0	14.30.15
GTX_DUAL:AC_CAP_DIS_1	5.30.48
GTX_DUAL:CHAN_BOND_KEEP_ALIGN_0	14.31.42
GTX_DUAL:CHAN_BOND_KEEP_ALIGN_1	5.31.22
GTX_DUAL:CHAN_BOND_SEQ_2_USE_0	12.30.14
GTX_DUAL:CHAN_BOND_SEQ_2_USE_1	7.30.49
GTX_DUAL:CLKINDC_B	5.31.33
GTX_DUAL:CLKRCV_TRST	6.31.14
GTX_DUAL:CLK_CORRECT_USE_0	12.31.3
GTX_DUAL:CLK_CORRECT_USE_1	7.31.60
GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_0	12.30.11
GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_1	7.30.52
GTX_DUAL:CLK_COR_KEEP_IDLE_0	12.30.10
GTX_DUAL:CLK_COR_KEEP_IDLE_1	7.30.53
GTX_DUAL:CLK_COR_PRECEDENCE_0	12.31.4
GTX_DUAL:CLK_COR_PRECEDENCE_1	7.31.59
GTX_DUAL:CLK_COR_SEQ_2_USE_0	11.30.20
GTX_DUAL:CLK_COR_SEQ_2_USE_1	8.30.43
GTX_DUAL:COMMA_DOUBLE_0	11.30.13
GTX_DUAL:COMMA_DOUBLE_1	8.30.50
GTX_DUAL:DEC_MCOMMA_DETECT_0	11.30.12
GTX_DUAL:DEC_MCOMMA_DETECT_1	8.30.51
GTX_DUAL:DEC_PCOMMA_DETECT_0	11.31.12
GTX_DUAL:DEC_PCOMMA_DETECT_1	8.31.51
GTX_DUAL:DEC_VALID_COMMA_ONLY_0	11.31.11
GTX_DUAL:DEC_VALID_COMMA_ONLY_1	8.31.52
GTX_DUAL:ENABLE	20.28.12
GTX_DUAL:INV.DCLK	20.19.13
GTX_DUAL:INV.RXUSRCLK0	20.22.12
GTX_DUAL:INV.RXUSRCLK1	20.21.13
GTX_DUAL:INV.RXUSRCLK20	20.22.13
GTX_DUAL:INV.RXUSRCLK21	20.21.12
GTX_DUAL:INV.TXUSRCLK0	20.23.12
GTX_DUAL:INV.TXUSRCLK1	20.20.13
GTX_DUAL:INV.TXUSRCLK20	20.23.13
GTX_DUAL:INV.TXUSRCLK21	20.20.12
GTX_DUAL:MCOMMA_DETECT_0	11.31.6
GTX_DUAL:MCOMMA_DETECT_1	8.31.57
GTX_DUAL:OVERSAMPLE_MODE	9.31.55
GTX_DUAL:PCI_EXPRESS_MODE_0	13.31.55
GTX_DUAL:PCI_EXPRESS_MODE_1	6.31.8
GTX_DUAL:PCOMMA_DETECT_0	13.31.50
GTX_DUAL:PCOMMA_DETECT_1	6.31.13
GTX_DUAL:PLL_FB_DCCEN	11.30.1
GTX_DUAL:PLL_SATA_0	13.30.48
GTX_DUAL:PLL_SATA_1	6.30.15
GTX_DUAL:PLL_STARTUP_EN	14.30.21
GTX_DUAL:RCV_TERM_GND_0	14.31.16
GTX_DUAL:RCV_TERM_GND_1	5.31.47
GTX_DUAL:RCV_TERM_VTTRX_0	14.30.16
GTX_DUAL:RCV_TERM_VTTRX_1	5.30.47
GTX_DUAL:RXGEARBOX_USE_0	14.31.44
GTX_DUAL:RXGEARBOX_USE_1	5.31.20
GTX_DUAL:RX_BUFFER_USE_0	13.31.17
GTX_DUAL:RX_BUFFER_USE_1	6.31.46
GTX_DUAL:RX_CDR_FORCE_ROTATE_0	14.30.7
GTX_DUAL:RX_CDR_FORCE_ROTATE_1	5.30.56
GTX_DUAL:RX_DECODE_SEQ_MATCH_0	13.30.17
GTX_DUAL:RX_DECODE_SEQ_MATCH_1	6.30.46
GTX_DUAL:RX_EN_IDLE_HOLD_CDR	12.30.20
GTX_DUAL:RX_EN_IDLE_HOLD_DFE_0	14.30.32
GTX_DUAL:RX_EN_IDLE_HOLD_DFE_1	5.30.31
GTX_DUAL:RX_EN_IDLE_RESET_BUF_0	14.31.33
GTX_DUAL:RX_EN_IDLE_RESET_BUF_1	5.31.30
GTX_DUAL:RX_EN_IDLE_RESET_FR	12.30.21
GTX_DUAL:RX_EN_IDLE_RESET_PH	12.30.17
GTX_DUAL:RX_LOSS_OF_SYNC_FSM_0	13.30.15
GTX_DUAL:RX_LOSS_OF_SYNC_FSM_1	6.30.48
GTX_DUAL:TERMINATION_OVRD	10.30.11
GTX_DUAL:TXGEARBOX_USE_0	14.30.44
GTX_DUAL:TXGEARBOX_USE_1	5.31.19
GTX_DUAL:TXOUTCLK_SEL_0	12.31.19
GTX_DUAL:TXOUTCLK_SEL_1	7.31.44
GTX_DUAL:TX_BUFFER_USE_0	12.31.30
GTX_DUAL:TX_BUFFER_USE_1	7.31.33
GTX_DUAL:USRCLK0	20.17.15
GTX_DUAL:USRCLK1	20.18.12
non-inverted	[0]

CRC32_0:INV.CRCCLK	20.18.15
CRC32_1:INV.CRCCLK	20.19.12
CRC32_2:INV.CRCCLK	20.18.14
CRC32_3:INV.CRCCLK	20.18.13
inverted	~[0]

GTX_DUAL:ALIGN_COMMA_WORD_0	10.31.30
GTX_DUAL:ALIGN_COMMA_WORD_1	9.31.33
1	0
2	1

GTX_DUAL:CB2_INH_CC_PERIOD_0	14.31.41	14.30.41	14.30.40	14.31.40
GTX_DUAL:CB2_INH_CC_PERIOD_1	5.30.22	5.30.23	5.31.23	5.31.24
GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0	10.30.30	10.30.31	10.31.31	10.31.32
GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1	9.30.33	9.30.32	9.31.32	9.31.31
GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0	10.30.32	10.30.33	10.31.33	10.31.34
GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1	9.30.31	9.30.30	9.31.30	9.31.29
GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0	10.30.57	10.31.57	10.31.58	10.30.58
GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1	9.30.6	9.31.6	9.31.5	9.30.5
GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0	12.30.16	12.31.16	12.31.15	12.30.15
GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1	7.30.47	7.31.47	7.31.48	7.30.48
GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0	11.30.44	11.31.44	11.31.43	11.30.43
GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1	8.30.19	8.31.19	8.31.20	8.30.20
GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0	11.30.22	11.31.22	11.31.21	11.30.21
GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1	8.30.41	8.31.41	8.31.42	8.30.42
GTX_DUAL:COM_BURST_VAL_0	11.31.20	11.31.19	11.30.19	11.30.18
GTX_DUAL:COM_BURST_VAL_1	8.31.43	8.31.44	8.30.44	8.30.45
GTX_DUAL:RX_IDLE_HI_CNT_0	14.30.36	14.31.36	14.31.35	14.30.35
GTX_DUAL:RX_IDLE_HI_CNT_1	5.30.27	5.31.27	5.31.28	5.30.28
GTX_DUAL:RX_IDLE_LO_CNT_0	14.31.39	14.30.39	14.30.38	14.31.38
GTX_DUAL:RX_IDLE_LO_CNT_1	5.30.24	5.30.25	5.31.25	5.31.26
non-inverted	[3]	[2]	[1]	[0]

GTX_DUAL:CDR_PH_ADJ_TIME	12.31.41	12.30.41	12.30.40	12.31.40	12.31.39
GTX_DUAL:CLK_COR_REPEAT_WAIT_0	12.30.3	12.30.2	12.31.2	12.31.1	12.30.1
GTX_DUAL:CLK_COR_REPEAT_WAIT_1	7.30.60	7.30.61	7.31.61	7.31.62	7.30.62
GTX_DUAL:DFE_CAL_TIME	12.30.33	12.30.32	12.31.32	12.31.31	12.30.31
GTX_DUAL:TERMINATION_CTRL	10.30.8	10.30.9	10.31.9	10.31.10	10.30.10
non-inverted	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:CHAN_BOND_LEVEL_0	10.30.34	10.30.35	10.31.35
GTX_DUAL:CHAN_BOND_LEVEL_1	9.30.29	9.30.28	9.31.28
GTX_DUAL:GEARBOX_ENDEC_0	14.31.43	14.30.43	14.30.42
GTX_DUAL:GEARBOX_ENDEC_1	5.30.20	5.30.21	5.31.21
GTX_DUAL:OOBDETECT_THRESHOLD_0	12.30.18	12.31.18	12.31.17
GTX_DUAL:OOBDETECT_THRESHOLD_1	7.30.45	7.31.45	7.31.46
GTX_DUAL:PLL_LKDET_CFG	5.31.39	5.31.40	5.30.40
GTX_DUAL:PLL_TDCC_CFG	14.31.24	14.30.23	14.31.23
GTX_DUAL:SATA_BURST_VAL_0	13.31.11	13.30.11	13.30.10
GTX_DUAL:SATA_BURST_VAL_1	6.31.52	6.30.52	6.30.53
GTX_DUAL:SATA_IDLE_VAL_0	13.31.10	13.31.9	13.30.9
GTX_DUAL:SATA_IDLE_VAL_1	6.31.53	6.31.54	6.30.54
GTX_DUAL:TXRX_INVERT_0	12.30.22	12.31.22	12.31.21
GTX_DUAL:TXRX_INVERT_1	7.30.41	7.31.41	7.31.42
GTX_DUAL:TX_IDLE_DELAY_0	14.31.28	14.31.27	14.30.27
GTX_DUAL:TX_IDLE_DELAY_1	5.31.31	5.31.32	5.30.32
non-inverted	[2]	[1]	[0]

GTX_DUAL:CHAN_BOND_MODE_0	10.30.36	10.31.36
GTX_DUAL:CHAN_BOND_MODE_1	9.30.27	9.31.27
#OFF	0	0
SLAVE	0	1
MASTER	1	0

GTX_DUAL:CHAN_BOND_SEQ_1_1_0	10.30.37	10.31.37	10.31.38	10.30.38	10.30.39	10.31.39	10.31.40	10.30.40	10.30.41	10.31.41
GTX_DUAL:CHAN_BOND_SEQ_1_1_1	9.30.26	9.31.26	9.31.25	9.30.25	9.30.24	9.31.24	9.31.23	9.30.23	9.30.22	9.31.22
GTX_DUAL:CHAN_BOND_SEQ_1_2_0	10.31.42	10.30.42	10.30.43	10.31.43	10.31.44	10.30.44	10.30.45	10.31.45	10.31.46	10.30.46
GTX_DUAL:CHAN_BOND_SEQ_1_2_1	9.31.21	9.30.21	9.30.20	9.31.20	9.31.19	9.30.19	9.30.18	9.31.18	9.31.17	9.30.17
GTX_DUAL:CHAN_BOND_SEQ_1_3_0	10.30.47	10.31.47	10.31.48	10.30.48	10.30.49	10.31.49	10.31.50	10.30.50	10.30.51	10.31.51
GTX_DUAL:CHAN_BOND_SEQ_1_3_1	9.30.16	9.31.16	9.31.15	9.30.15	9.30.14	9.31.14	9.31.13	9.30.13	9.30.12	9.31.12
GTX_DUAL:CHAN_BOND_SEQ_1_4_0	10.31.52	10.30.52	10.30.53	10.31.53	10.31.54	10.30.54	10.30.55	10.31.55	10.31.56	10.30.56
GTX_DUAL:CHAN_BOND_SEQ_1_4_1	9.31.11	9.30.11	9.30.10	9.31.10	9.31.9	9.30.9	9.30.8	9.31.8	9.31.7	9.30.7
GTX_DUAL:CHAN_BOND_SEQ_2_1_0	10.30.59	10.31.59	10.31.60	10.30.60	10.30.61	10.31.61	10.31.62	10.30.62	10.30.63	10.31.63
GTX_DUAL:CHAN_BOND_SEQ_2_1_1	9.30.4	9.31.4	9.31.3	9.30.3	9.30.2	9.31.2	9.31.1	9.30.1	9.30.0	9.31.0
GTX_DUAL:CHAN_BOND_SEQ_2_2_0	11.31.0	11.30.0	11.31.1	11.31.2	11.30.2	11.30.3	11.31.3	11.31.4	11.30.4	11.30.5
GTX_DUAL:CHAN_BOND_SEQ_2_2_1	8.31.63	8.30.63	8.31.62	8.31.61	8.30.61	8.30.60	8.31.60	8.31.59	8.30.59	8.30.58
GTX_DUAL:CHAN_BOND_SEQ_2_3_0	11.31.5	13.30.56	13.30.57	13.31.57	13.31.58	13.30.58	13.30.59	13.31.59	13.31.60	13.30.60
GTX_DUAL:CHAN_BOND_SEQ_2_3_1	8.31.58	6.30.7	6.30.6	6.31.6	6.31.5	6.30.5	6.30.4	6.31.4	6.31.3	6.30.3
GTX_DUAL:CHAN_BOND_SEQ_2_4_0	13.30.61	13.31.61	13.31.62	13.30.62	13.30.63	13.31.63	14.31.0	14.30.0	14.30.1	14.31.1
GTX_DUAL:CHAN_BOND_SEQ_2_4_1	6.30.2	6.31.2	6.31.1	6.30.1	6.30.0	6.31.0	5.31.63	5.30.63	5.30.62	5.31.62
GTX_DUAL:CLK_COR_SEQ_1_1_0	12.30.0	12.31.0	11.31.63	11.30.63	11.30.62	11.31.62	11.31.61	11.30.61	11.30.60	11.31.60
GTX_DUAL:CLK_COR_SEQ_1_1_1	7.30.63	7.31.63	8.31.0	8.30.0	8.30.1	8.31.1	8.31.2	8.30.2	8.30.3	8.31.3
GTX_DUAL:CLK_COR_SEQ_1_2_0	11.31.59	11.30.59	11.30.58	11.31.58	11.31.57	11.30.57	11.30.56	11.31.56	11.31.55	11.30.55
GTX_DUAL:CLK_COR_SEQ_1_2_1	8.31.4	8.30.4	8.30.5	8.31.5	8.31.6	8.30.6	8.30.7	8.31.7	8.31.8	8.30.8
GTX_DUAL:CLK_COR_SEQ_1_3_0	11.30.54	11.31.54	11.31.53	11.30.53	11.30.52	11.31.52	11.31.51	11.30.51	11.30.50	11.31.50
GTX_DUAL:CLK_COR_SEQ_1_3_1	8.30.9	8.31.9	8.31.10	8.30.10	8.30.11	8.31.11	8.31.12	8.30.12	8.30.13	8.31.13
GTX_DUAL:CLK_COR_SEQ_1_4_0	11.31.49	11.30.49	11.30.48	11.31.48	11.31.47	11.30.47	11.30.46	11.31.46	11.31.45	11.30.45
GTX_DUAL:CLK_COR_SEQ_1_4_1	8.31.14	8.30.14	8.30.15	8.31.15	8.31.16	8.30.16	8.30.17	8.31.17	8.31.18	8.30.18
GTX_DUAL:CLK_COR_SEQ_2_1_0	11.30.42	11.31.42	11.31.41	11.30.41	11.30.40	11.31.40	11.31.39	11.30.39	11.30.38	11.31.38
GTX_DUAL:CLK_COR_SEQ_2_1_1	8.30.21	8.31.21	8.31.22	8.30.22	8.30.23	8.31.23	8.31.24	8.30.24	8.30.25	8.31.25
GTX_DUAL:CLK_COR_SEQ_2_2_0	11.31.37	11.30.37	11.30.36	11.31.36	11.31.35	11.30.35	11.30.34	11.31.34	11.31.33	11.30.33
GTX_DUAL:CLK_COR_SEQ_2_2_1	8.31.26	8.30.26	8.30.27	8.31.27	8.31.28	8.30.28	8.30.29	8.31.29	8.31.30	8.30.30
GTX_DUAL:CLK_COR_SEQ_2_3_0	11.30.32	11.31.32	11.31.31	11.30.31	11.30.30	11.31.30	11.31.29	11.30.29	11.30.28	11.31.28
GTX_DUAL:CLK_COR_SEQ_2_3_1	8.30.31	8.31.31	8.31.32	8.30.32	8.30.33	8.31.33	8.31.34	8.30.34	8.30.35	8.31.35
GTX_DUAL:CLK_COR_SEQ_2_4_0	11.31.27	11.30.27	11.30.26	11.31.26	11.31.25	11.30.25	11.30.24	11.31.24	11.31.23	11.30.23
GTX_DUAL:CLK_COR_SEQ_2_4_1	8.31.36	8.30.36	8.30.37	8.31.37	8.31.38	8.30.38	8.30.39	8.31.39	8.31.40	8.30.40
GTX_DUAL:COMMA_10B_ENABLE_0	11.31.18	11.31.17	11.30.17	11.30.16	11.31.16	11.31.15	11.30.15	11.30.14	11.31.14	11.31.13
GTX_DUAL:COMMA_10B_ENABLE_1	8.31.45	8.31.46	8.30.46	8.30.47	8.31.47	8.31.48	8.30.48	8.30.49	8.31.49	8.31.50
GTX_DUAL:DFE_CFG_0	14.31.49	14.30.49	14.30.48	14.31.48	14.31.47	14.30.47	14.30.46	14.31.46	14.31.45	14.30.45
GTX_DUAL:DFE_CFG_1	5.30.14	5.30.15	5.31.15	5.31.16	5.30.16	5.30.17	5.31.17	5.31.18	5.30.18	5.30.19
GTX_DUAL:MCOMMA_10B_VALUE_0	11.30.11	11.30.10	11.31.10	11.31.9	11.30.9	11.30.8	11.31.8	11.31.7	11.30.7	11.30.6
GTX_DUAL:MCOMMA_10B_VALUE_1	8.30.52	8.30.53	8.31.53	8.31.54	8.30.54	8.30.55	8.31.55	8.31.56	8.30.56	8.30.57
GTX_DUAL:PCOMMA_10B_VALUE_0	13.30.55	13.30.54	13.31.54	13.31.53	13.30.53	13.30.52	13.31.52	13.31.51	13.30.51	13.30.50
GTX_DUAL:PCOMMA_10B_VALUE_1	6.30.8	6.30.9	6.31.9	6.31.10	6.30.10	6.30.11	6.31.11	6.31.12	6.30.12	6.30.13
GTX_DUAL:TRANS_TIME_TO_P2_0	12.31.38	12.31.37	12.30.37	12.30.36	12.31.36	12.31.35	12.30.35	12.30.34	12.31.34	12.31.33
GTX_DUAL:TRANS_TIME_TO_P2_1	7.31.25	7.31.26	7.30.26	7.30.27	7.31.27	7.31.28	7.30.28	7.30.29	7.31.29	7.31.30
non-inverted	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:CHAN_BOND_SEQ_LEN_0	12.31.14	12.31.13
GTX_DUAL:CHAN_BOND_SEQ_LEN_1	7.31.49	7.31.50
GTX_DUAL:CLK_COR_ADJ_LEN_0	12.30.13	12.30.12
GTX_DUAL:CLK_COR_ADJ_LEN_1	7.30.50	7.30.51
GTX_DUAL:CLK_COR_DET_LEN_0	12.31.12	12.31.11
GTX_DUAL:CLK_COR_DET_LEN_1	7.31.51	7.31.52
1	0	0
2	0	1
3	1	0
4	1	1

GTX_DUAL:CLK25_DIVIDER	9.30.52	9.30.53	9.31.53
1	0	0	0
2	0	0	1
3	0	1	0
4	0	1	1
5	1	0	0
6	1	0	1
10	1	1	0
12	1	1	1

GTX_DUAL:CLK_COR_MAX_LAT_0	12.31.10	12.31.9	12.30.9	12.30.8	12.31.8	12.31.7
GTX_DUAL:CLK_COR_MAX_LAT_1	7.31.53	7.31.54	7.30.54	7.30.55	7.31.55	7.31.56
GTX_DUAL:CLK_COR_MIN_LAT_0	12.30.7	12.30.6	12.31.6	12.31.5	12.30.5	12.30.4
GTX_DUAL:CLK_COR_MIN_LAT_1	7.30.56	7.30.57	7.31.57	7.31.58	7.30.58	7.30.59
GTX_DUAL:SATA_MAX_BURST_0	13.30.8	13.31.8	13.31.7	13.30.7	13.30.6	13.31.6
GTX_DUAL:SATA_MAX_BURST_1	6.30.55	6.31.55	6.31.56	6.30.56	6.30.57	6.31.57
GTX_DUAL:SATA_MAX_INIT_0	13.31.5	13.30.5	13.30.4	13.31.4	13.31.3	13.30.3
GTX_DUAL:SATA_MAX_INIT_1	6.31.58	6.30.58	6.30.59	6.31.59	6.31.60	6.30.60
GTX_DUAL:SATA_MAX_WAKE_0	13.30.2	13.31.2	13.31.1	13.30.1	13.30.0	13.31.0
GTX_DUAL:SATA_MAX_WAKE_1	6.30.61	6.31.61	6.31.62	6.30.62	6.30.63	6.31.63
GTX_DUAL:SATA_MIN_BURST_0	12.31.63	12.30.63	12.30.62	12.31.62	12.31.61	12.30.61
GTX_DUAL:SATA_MIN_BURST_1	7.31.0	7.30.0	7.30.1	7.31.1	7.31.2	7.30.2
GTX_DUAL:SATA_MIN_INIT_0	12.30.60	12.31.60	12.31.59	12.30.59	12.30.58	12.31.58
GTX_DUAL:SATA_MIN_INIT_1	7.30.3	7.31.3	7.31.4	7.30.4	7.30.5	7.31.5
GTX_DUAL:SATA_MIN_WAKE_0	12.31.57	12.30.57	12.30.56	12.31.56	12.31.55	12.30.55
GTX_DUAL:SATA_MIN_WAKE_1	7.31.6	7.30.6	7.30.7	7.31.7	7.31.8	7.30.8
non-inverted	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:CM_TRIM_0	14.30.50	14.31.50
GTX_DUAL:CM_TRIM_1	5.31.13	5.31.14
non-inverted	[1]	[0]

GTX_DUAL:DRP00	5.31.7	5.30.7	5.30.6	5.31.6	5.31.5	5.30.5	5.30.4	5.31.4	5.31.3	5.30.3	5.30.2	5.31.2	5.31.1	5.30.1	5.30.0	5.31.0
GTX_DUAL:DRP01	5.31.15	5.30.15	5.30.14	5.31.14	5.31.13	5.30.13	5.30.12	5.31.12	5.31.11	5.30.11	5.30.10	5.31.10	5.31.9	5.30.9	5.30.8	5.31.8
GTX_DUAL:DRP02	5.31.23	5.30.23	5.30.22	5.31.22	5.31.21	5.30.21	5.30.20	5.31.20	5.31.19	5.30.19	5.30.18	5.31.18	5.31.17	5.30.17	5.30.16	5.31.16
GTX_DUAL:DRP03	5.31.31	5.30.31	5.30.30	5.31.30	5.31.29	5.30.29	5.30.28	5.31.28	5.31.27	5.30.27	5.30.26	5.31.26	5.31.25	5.30.25	5.30.24	5.31.24
GTX_DUAL:DRP04	5.31.39	5.30.39	5.30.38	5.31.38	5.31.37	5.30.37	5.30.36	5.31.36	5.31.35	5.30.35	5.30.34	5.31.34	5.31.33	5.30.33	5.30.32	5.31.32
GTX_DUAL:DRP05	5.31.47	5.30.47	5.30.46	5.31.46	5.31.45	5.30.45	5.30.44	5.31.44	5.31.43	5.30.43	5.30.42	5.31.42	5.31.41	5.30.41	5.30.40	5.31.40
GTX_DUAL:DRP06	5.31.55	5.30.55	5.30.54	5.31.54	5.31.53	5.30.53	5.30.52	5.31.52	5.31.51	5.30.51	5.30.50	5.31.50	5.31.49	5.30.49	5.30.48	5.31.48
GTX_DUAL:DRP07	5.31.63	5.30.63	5.30.62	5.31.62	5.31.61	5.30.61	5.30.60	5.31.60	5.31.59	5.30.59	5.30.58	5.31.58	5.31.57	5.30.57	5.30.56	5.31.56
GTX_DUAL:DRP08	6.31.7	6.30.7	6.30.6	6.31.6	6.31.5	6.30.5	6.30.4	6.31.4	6.31.3	6.30.3	6.30.2	6.31.2	6.31.1	6.30.1	6.30.0	6.31.0
GTX_DUAL:DRP09	6.31.15	6.30.15	6.30.14	6.31.14	6.31.13	6.30.13	6.30.12	6.31.12	6.31.11	6.30.11	6.30.10	6.31.10	6.31.9	6.30.9	6.30.8	6.31.8
GTX_DUAL:DRP0A	6.31.23	6.30.23	6.30.22	6.31.22	6.31.21	6.30.21	6.30.20	6.31.20	6.31.19	6.30.19	6.30.18	6.31.18	6.31.17	6.30.17	6.30.16	6.31.16
GTX_DUAL:DRP0B	6.31.31	6.30.31	6.30.30	6.31.30	6.31.29	6.30.29	6.30.28	6.31.28	6.31.27	6.30.27	6.30.26	6.31.26	6.31.25	6.30.25	6.30.24	6.31.24
GTX_DUAL:DRP0C	6.31.39	6.30.39	6.30.38	6.31.38	6.31.37	6.30.37	6.30.36	6.31.36	6.31.35	6.30.35	6.30.34	6.31.34	6.31.33	6.30.33	6.30.32	6.31.32
GTX_DUAL:DRP0D	6.31.47	6.30.47	6.30.46	6.31.46	6.31.45	6.30.45	6.30.44	6.31.44	6.31.43	6.30.43	6.30.42	6.31.42	6.31.41	6.30.41	6.30.40	6.31.40
GTX_DUAL:DRP0E	6.31.55	6.30.55	6.30.54	6.31.54	6.31.53	6.30.53	6.30.52	6.31.52	6.31.51	6.30.51	6.30.50	6.31.50	6.31.49	6.30.49	6.30.48	6.31.48
GTX_DUAL:DRP0F	6.31.63	6.30.63	6.30.62	6.31.62	6.31.61	6.30.61	6.30.60	6.31.60	6.31.59	6.30.59	6.30.58	6.31.58	6.31.57	6.30.57	6.30.56	6.31.56
GTX_DUAL:DRP10	7.31.7	7.30.7	7.30.6	7.31.6	7.31.5	7.30.5	7.30.4	7.31.4	7.31.3	7.30.3	7.30.2	7.31.2	7.31.1	7.30.1	7.30.0	7.31.0
GTX_DUAL:DRP11	7.31.15	7.30.15	7.30.14	7.31.14	7.31.13	7.30.13	7.30.12	7.31.12	7.31.11	7.30.11	7.30.10	7.31.10	7.31.9	7.30.9	7.30.8	7.31.8
GTX_DUAL:DRP12	7.31.23	7.30.23	7.30.22	7.31.22	7.31.21	7.30.21	7.30.20	7.31.20	7.31.19	7.30.19	7.30.18	7.31.18	7.31.17	7.30.17	7.30.16	7.31.16
GTX_DUAL:DRP13	7.31.31	7.30.31	7.30.30	7.31.30	7.31.29	7.30.29	7.30.28	7.31.28	7.31.27	7.30.27	7.30.26	7.31.26	7.31.25	7.30.25	7.30.24	7.31.24
GTX_DUAL:DRP14	7.31.39	7.30.39	7.30.38	7.31.38	7.31.37	7.30.37	7.30.36	7.31.36	7.31.35	7.30.35	7.30.34	7.31.34	7.31.33	7.30.33	7.30.32	7.31.32
GTX_DUAL:DRP15	7.31.47	7.30.47	7.30.46	7.31.46	7.31.45	7.30.45	7.30.44	7.31.44	7.31.43	7.30.43	7.30.42	7.31.42	7.31.41	7.30.41	7.30.40	7.31.40
GTX_DUAL:DRP16	7.31.55	7.30.55	7.30.54	7.31.54	7.31.53	7.30.53	7.30.52	7.31.52	7.31.51	7.30.51	7.30.50	7.31.50	7.31.49	7.30.49	7.30.48	7.31.48
GTX_DUAL:DRP17	7.31.63	7.30.63	7.30.62	7.31.62	7.31.61	7.30.61	7.30.60	7.31.60	7.31.59	7.30.59	7.30.58	7.31.58	7.31.57	7.30.57	7.30.56	7.31.56
GTX_DUAL:DRP18	8.31.7	8.30.7	8.30.6	8.31.6	8.31.5	8.30.5	8.30.4	8.31.4	8.31.3	8.30.3	8.30.2	8.31.2	8.31.1	8.30.1	8.30.0	8.31.0
GTX_DUAL:DRP19	8.31.15	8.30.15	8.30.14	8.31.14	8.31.13	8.30.13	8.30.12	8.31.12	8.31.11	8.30.11	8.30.10	8.31.10	8.31.9	8.30.9	8.30.8	8.31.8
GTX_DUAL:DRP1A	8.31.23	8.30.23	8.30.22	8.31.22	8.31.21	8.30.21	8.30.20	8.31.20	8.31.19	8.30.19	8.30.18	8.31.18	8.31.17	8.30.17	8.30.16	8.31.16
GTX_DUAL:DRP1B	8.31.31	8.30.31	8.30.30	8.31.30	8.31.29	8.30.29	8.30.28	8.31.28	8.31.27	8.30.27	8.30.26	8.31.26	8.31.25	8.30.25	8.30.24	8.31.24
GTX_DUAL:DRP1C	8.31.39	8.30.39	8.30.38	8.31.38	8.31.37	8.30.37	8.30.36	8.31.36	8.31.35	8.30.35	8.30.34	8.31.34	8.31.33	8.30.33	8.30.32	8.31.32
GTX_DUAL:DRP1D	8.31.47	8.30.47	8.30.46	8.31.46	8.31.45	8.30.45	8.30.44	8.31.44	8.31.43	8.30.43	8.30.42	8.31.42	8.31.41	8.30.41	8.30.40	8.31.40
GTX_DUAL:DRP1E	8.31.55	8.30.55	8.30.54	8.31.54	8.31.53	8.30.53	8.30.52	8.31.52	8.31.51	8.30.51	8.30.50	8.31.50	8.31.49	8.30.49	8.30.48	8.31.48
GTX_DUAL:DRP1F	8.31.63	8.30.63	8.30.62	8.31.62	8.31.61	8.30.61	8.30.60	8.31.60	8.31.59	8.30.59	8.30.58	8.31.58	8.31.57	8.30.57	8.30.56	8.31.56
GTX_DUAL:DRP20	9.31.7	9.30.7	9.30.6	9.31.6	9.31.5	9.30.5	9.30.4	9.31.4	9.31.3	9.30.3	9.30.2	9.31.2	9.31.1	9.30.1	9.30.0	9.31.0
GTX_DUAL:DRP21	9.31.15	9.30.15	9.30.14	9.31.14	9.31.13	9.30.13	9.30.12	9.31.12	9.31.11	9.30.11	9.30.10	9.31.10	9.31.9	9.30.9	9.30.8	9.31.8
GTX_DUAL:DRP22	9.31.23	9.30.23	9.30.22	9.31.22	9.31.21	9.30.21	9.30.20	9.31.20	9.31.19	9.30.19	9.30.18	9.31.18	9.31.17	9.30.17	9.30.16	9.31.16
GTX_DUAL:DRP23	9.31.31	9.30.31	9.30.30	9.31.30	9.31.29	9.30.29	9.30.28	9.31.28	9.31.27	9.30.27	9.30.26	9.31.26	9.31.25	9.30.25	9.30.24	9.31.24
GTX_DUAL:DRP24	9.31.39	9.30.39	9.30.38	9.31.38	9.31.37	9.30.37	9.30.36	9.31.36	9.31.35	9.30.35	9.30.34	9.31.34	9.31.33	9.30.33	9.30.32	9.31.32
GTX_DUAL:DRP25	9.31.47	9.30.47	9.30.46	9.31.46	9.31.45	9.30.45	9.30.44	9.31.44	9.31.43	9.30.43	9.30.42	9.31.42	9.31.41	9.30.41	9.30.40	9.31.40
GTX_DUAL:DRP26	9.31.55	9.30.55	9.30.54	9.31.54	9.31.53	9.30.53	9.30.52	9.31.52	9.31.51	9.30.51	9.30.50	9.31.50	9.31.49	9.30.49	9.30.48	9.31.48
GTX_DUAL:DRP27	9.31.63	9.30.63	9.30.62	9.31.62	9.31.61	9.30.61	9.30.60	9.31.60	9.31.59	9.30.59	9.30.58	9.31.58	9.31.57	9.30.57	9.30.56	9.31.56
GTX_DUAL:DRP28	10.31.7	10.30.7	10.30.6	10.31.6	10.31.5	10.30.5	10.30.4	10.31.4	10.31.3	10.30.3	10.30.2	10.31.2	10.31.1	10.30.1	10.30.0	10.31.0
GTX_DUAL:DRP29	10.31.15	10.30.15	10.30.14	10.31.14	10.31.13	10.30.13	10.30.12	10.31.12	10.31.11	10.30.11	10.30.10	10.31.10	10.31.9	10.30.9	10.30.8	10.31.8
GTX_DUAL:DRP2A	10.31.23	10.30.23	10.30.22	10.31.22	10.31.21	10.30.21	10.30.20	10.31.20	10.31.19	10.30.19	10.30.18	10.31.18	10.31.17	10.30.17	10.30.16	10.31.16
GTX_DUAL:DRP2B	10.31.31	10.30.31	10.30.30	10.31.30	10.31.29	10.30.29	10.30.28	10.31.28	10.31.27	10.30.27	10.30.26	10.31.26	10.31.25	10.30.25	10.30.24	10.31.24
GTX_DUAL:DRP2C	10.31.39	10.30.39	10.30.38	10.31.38	10.31.37	10.30.37	10.30.36	10.31.36	10.31.35	10.30.35	10.30.34	10.31.34	10.31.33	10.30.33	10.30.32	10.31.32
GTX_DUAL:DRP2D	10.31.47	10.30.47	10.30.46	10.31.46	10.31.45	10.30.45	10.30.44	10.31.44	10.31.43	10.30.43	10.30.42	10.31.42	10.31.41	10.30.41	10.30.40	10.31.40
GTX_DUAL:DRP2E	10.31.55	10.30.55	10.30.54	10.31.54	10.31.53	10.30.53	10.30.52	10.31.52	10.31.51	10.30.51	10.30.50	10.31.50	10.31.49	10.30.49	10.30.48	10.31.48
GTX_DUAL:DRP2F	10.31.63	10.30.63	10.30.62	10.31.62	10.31.61	10.30.61	10.30.60	10.31.60	10.31.59	10.30.59	10.30.58	10.31.58	10.31.57	10.30.57	10.30.56	10.31.56
GTX_DUAL:DRP30	11.31.7	11.30.7	11.30.6	11.31.6	11.31.5	11.30.5	11.30.4	11.31.4	11.31.3	11.30.3	11.30.2	11.31.2	11.31.1	11.30.1	11.30.0	11.31.0
GTX_DUAL:DRP31	11.31.15	11.30.15	11.30.14	11.31.14	11.31.13	11.30.13	11.30.12	11.31.12	11.31.11	11.30.11	11.30.10	11.31.10	11.31.9	11.30.9	11.30.8	11.31.8
GTX_DUAL:DRP32	11.31.23	11.30.23	11.30.22	11.31.22	11.31.21	11.30.21	11.30.20	11.31.20	11.31.19	11.30.19	11.30.18	11.31.18	11.31.17	11.30.17	11.30.16	11.31.16
GTX_DUAL:DRP33	11.31.31	11.30.31	11.30.30	11.31.30	11.31.29	11.30.29	11.30.28	11.31.28	11.31.27	11.30.27	11.30.26	11.31.26	11.31.25	11.30.25	11.30.24	11.31.24
GTX_DUAL:DRP34	11.31.39	11.30.39	11.30.38	11.31.38	11.31.37	11.30.37	11.30.36	11.31.36	11.31.35	11.30.35	11.30.34	11.31.34	11.31.33	11.30.33	11.30.32	11.31.32
GTX_DUAL:DRP35	11.31.47	11.30.47	11.30.46	11.31.46	11.31.45	11.30.45	11.30.44	11.31.44	11.31.43	11.30.43	11.30.42	11.31.42	11.31.41	11.30.41	11.30.40	11.31.40
GTX_DUAL:DRP36	11.31.55	11.30.55	11.30.54	11.31.54	11.31.53	11.30.53	11.30.52	11.31.52	11.31.51	11.30.51	11.30.50	11.31.50	11.31.49	11.30.49	11.30.48	11.31.48
GTX_DUAL:DRP37	11.31.63	11.30.63	11.30.62	11.31.62	11.31.61	11.30.61	11.30.60	11.31.60	11.31.59	11.30.59	11.30.58	11.31.58	11.31.57	11.30.57	11.30.56	11.31.56
GTX_DUAL:DRP38	12.31.7	12.30.7	12.30.6	12.31.6	12.31.5	12.30.5	12.30.4	12.31.4	12.31.3	12.30.3	12.30.2	12.31.2	12.31.1	12.30.1	12.30.0	12.31.0
GTX_DUAL:DRP39	12.31.15	12.30.15	12.30.14	12.31.14	12.31.13	12.30.13	12.30.12	12.31.12	12.31.11	12.30.11	12.30.10	12.31.10	12.31.9	12.30.9	12.30.8	12.31.8
GTX_DUAL:DRP3A	12.31.23	12.30.23	12.30.22	12.31.22	12.31.21	12.30.21	12.30.20	12.31.20	12.31.19	12.30.19	12.30.18	12.31.18	12.31.17	12.30.17	12.30.16	12.31.16
GTX_DUAL:DRP3B	12.31.31	12.30.31	12.30.30	12.31.30	12.31.29	12.30.29	12.30.28	12.31.28	12.31.27	12.30.27	12.30.26	12.31.26	12.31.25	12.30.25	12.30.24	12.31.24
GTX_DUAL:DRP3C	12.31.39	12.30.39	12.30.38	12.31.38	12.31.37	12.30.37	12.30.36	12.31.36	12.31.35	12.30.35	12.30.34	12.31.34	12.31.33	12.30.33	12.30.32	12.31.32
GTX_DUAL:DRP3D	12.31.47	12.30.47	12.30.46	12.31.46	12.31.45	12.30.45	12.30.44	12.31.44	12.31.43	12.30.43	12.30.42	12.31.42	12.31.41	12.30.41	12.30.40	12.31.40
GTX_DUAL:DRP3E	12.31.55	12.30.55	12.30.54	12.31.54	12.31.53	12.30.53	12.30.52	12.31.52	12.31.51	12.30.51	12.30.50	12.31.50	12.31.49	12.30.49	12.30.48	12.31.48
GTX_DUAL:DRP3F	12.31.63	12.30.63	12.30.62	12.31.62	12.31.61	12.30.61	12.30.60	12.31.60	12.31.59	12.30.59	12.30.58	12.31.58	12.31.57	12.30.57	12.30.56	12.31.56
GTX_DUAL:DRP40	13.31.7	13.30.7	13.30.6	13.31.6	13.31.5	13.30.5	13.30.4	13.31.4	13.31.3	13.30.3	13.30.2	13.31.2	13.31.1	13.30.1	13.30.0	13.31.0
GTX_DUAL:DRP41	13.31.15	13.30.15	13.30.14	13.31.14	13.31.13	13.30.13	13.30.12	13.31.12	13.31.11	13.30.11	13.30.10	13.31.10	13.31.9	13.30.9	13.30.8	13.31.8
GTX_DUAL:DRP42	13.31.23	13.30.23	13.30.22	13.31.22	13.31.21	13.30.21	13.30.20	13.31.20	13.31.19	13.30.19	13.30.18	13.31.18	13.31.17	13.30.17	13.30.16	13.31.16
GTX_DUAL:DRP43	13.31.31	13.30.31	13.30.30	13.31.30	13.31.29	13.30.29	13.30.28	13.31.28	13.31.27	13.30.27	13.30.26	13.31.26	13.31.25	13.30.25	13.30.24	13.31.24
GTX_DUAL:DRP44	13.31.39	13.30.39	13.30.38	13.31.38	13.31.37	13.30.37	13.30.36	13.31.36	13.31.35	13.30.35	13.30.34	13.31.34	13.31.33	13.30.33	13.30.32	13.31.32
GTX_DUAL:DRP45	13.31.47	13.30.47	13.30.46	13.31.46	13.31.45	13.30.45	13.30.44	13.31.44	13.31.43	13.30.43	13.30.42	13.31.42	13.31.41	13.30.41	13.30.40	13.31.40
GTX_DUAL:DRP46	13.31.55	13.30.55	13.30.54	13.31.54	13.31.53	13.30.53	13.30.52	13.31.52	13.31.51	13.30.51	13.30.50	13.31.50	13.31.49	13.30.49	13.30.48	13.31.48
GTX_DUAL:DRP47	13.31.63	13.30.63	13.30.62	13.31.62	13.31.61	13.30.61	13.30.60	13.31.60	13.31.59	13.30.59	13.30.58	13.31.58	13.31.57	13.30.57	13.30.56	13.31.56
GTX_DUAL:DRP48	14.31.7	14.30.7	14.30.6	14.31.6	14.31.5	14.30.5	14.30.4	14.31.4	14.31.3	14.30.3	14.30.2	14.31.2	14.31.1	14.30.1	14.30.0	14.31.0
GTX_DUAL:DRP49	14.31.15	14.30.15	14.30.14	14.31.14	14.31.13	14.30.13	14.30.12	14.31.12	14.31.11	14.30.11	14.30.10	14.31.10	14.31.9	14.30.9	14.30.8	14.31.8
GTX_DUAL:DRP4A	14.31.23	14.30.23	14.30.22	14.31.22	14.31.21	14.30.21	14.30.20	14.31.20	14.31.19	14.30.19	14.30.18	14.31.18	14.31.17	14.30.17	14.30.16	14.31.16
GTX_DUAL:DRP4B	14.31.31	14.30.31	14.30.30	14.31.30	14.31.29	14.30.29	14.30.28	14.31.28	14.31.27	14.30.27	14.30.26	14.31.26	14.31.25	14.30.25	14.30.24	14.31.24
GTX_DUAL:DRP4C	14.31.39	14.30.39	14.30.38	14.31.38	14.31.37	14.30.37	14.30.36	14.31.36	14.31.35	14.30.35	14.30.34	14.31.34	14.31.33	14.30.33	14.30.32	14.31.32
GTX_DUAL:DRP4D	14.31.47	14.30.47	14.30.46	14.31.46	14.31.45	14.30.45	14.30.44	14.31.44	14.31.43	14.30.43	14.30.42	14.31.42	14.31.41	14.30.41	14.30.40	14.31.40
GTX_DUAL:DRP4E	14.31.55	14.30.55	14.30.54	14.31.54	14.31.53	14.30.53	14.30.52	14.31.52	14.31.51	14.30.51	14.30.50	14.31.50	14.31.49	14.30.49	14.30.48	14.31.48
GTX_DUAL:DRP4F	14.31.63	14.30.63	14.30.62	14.31.62	14.31.61	14.30.61	14.30.60	14.31.60	14.31.59	14.30.59	14.30.58	14.31.58	14.31.57	14.30.57	14.30.56	14.31.56
non-inverted	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:MUX.CLKIN	5.31.34	5.30.34	5.30.35
GREFCLK	0	0	0
CLKOUT_SOUTH_N	0	0	1
CLKPN	0	1	1
CLKOUT_NORTH_S	1	0	1

GTX_DUAL:MUX.CLKOUT_NORTH	5.31.36
CLKOUT_NORTH_S	0
CLKPN	1

GTX_DUAL:MUX.CLKOUT_SOUTH	5.31.35
CLKOUT_SOUTH_N	0
CLKPN	1

GTX_DUAL:OOB_CLK_DIVIDER	9.31.54	9.30.54	9.30.55
1	0	0	0
2	0	0	1
4	0	1	0
6	0	1	1
8	1	0	0
10	1	0	1
12	1	1	0
14	1	1	1

GTX_DUAL:PLL_COM_CFG	7.30.33	7.30.32	7.31.32	7.31.31	9.31.56	9.30.56	9.30.57	9.31.57	9.31.58	9.30.58	9.30.59	9.31.59	9.31.60	9.30.60	9.30.61	9.31.61	9.31.62	9.30.62	9.30.63	9.31.63	10.31.0	10.30.0	10.30.1	10.31.1
non-inverted	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PLL_CP_CFG	10.31.2	10.30.2	10.30.3	10.31.3	10.31.4	10.30.4	10.30.5	10.31.5
GTX_DUAL:TRANS_TIME_NON_P2_0	12.31.46	12.31.45	12.30.45	12.30.44	12.31.44	12.31.43	12.30.43	12.30.42
GTX_DUAL:TRANS_TIME_NON_P2_1	7.31.17	7.31.18	7.30.18	7.30.19	7.31.19	7.31.20	7.30.20	7.30.21
non-inverted	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PLL_DIVSEL_FB	10.30.7	10.31.7	10.31.8	10.31.6
2	0	0	0	0
1	0	0	0	1
3	0	0	1	0
4	0	1	0	0
5	0	1	1	0
8	1	1	0	0
10	1	1	1	0

GTX_DUAL:PLL_DIVSEL_REF	5.31.38	5.31.37	5.30.37	5.30.36	5.30.38
2	0	0	0	0	0
1	0	0	0	0	1
3	0	0	0	1	0
4	0	0	1	0	0
5	0	0	1	1	0
6	0	1	0	1	0
8	0	1	1	0	0
10	0	1	1	1	0
12	1	1	0	1	0
16	1	1	1	0	0
20	1	1	1	1	0

GTX_DUAL:PLL_RXDIVSEL_OUT_0	13.31.49	13.30.49
GTX_DUAL:PLL_RXDIVSEL_OUT_1	6.31.15	6.31.16
GTX_DUAL:PLL_TXDIVSEL_OUT_0	13.31.48	13.31.47
GTX_DUAL:PLL_TXDIVSEL_OUT_1	5.31.41	5.31.42
1	0	0
2	0	1
4	1	0

GTX_DUAL:PMA_CDR_SCAN_0	13.30.47	13.30.46	13.31.46	13.31.45	13.30.45	13.30.44	13.31.44	13.31.43	13.30.43	13.30.42	13.31.42	13.31.41	13.30.41	13.30.40	13.31.40	13.31.39	13.30.39	13.30.38	13.31.38	13.31.37	13.30.37	13.30.36	13.31.36	13.31.35	13.30.35	13.30.34	13.31.34
GTX_DUAL:PMA_CDR_SCAN_1	6.30.16	6.30.17	6.31.17	6.31.18	6.30.18	6.30.19	6.31.19	6.31.20	6.30.20	6.30.21	6.31.21	6.31.22	6.30.22	6.30.23	6.31.23	6.31.24	6.30.24	6.30.25	6.31.25	6.31.26	6.30.26	6.30.27	6.31.27	6.31.28	6.30.28	6.30.29	6.31.29
non-inverted	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PMA_COM_CFG	9.30.45	10.30.19	9.30.44	10.31.19	9.30.47	9.31.45	9.30.46	9.31.46	10.30.17	10.30.18	10.31.17	10.31.18	9.31.48	10.30.16	9.31.47	10.31.16	9.30.40	10.30.23	9.30.41	10.31.23	9.31.52	10.31.12	9.31.51	10.30.12	9.30.51	10.30.13	9.30.50	10.31.13	9.31.49	10.31.14	9.31.50	10.30.14	9.30.49	10.31.15	9.30.48	10.30.15	10.31.11	14.30.19	14.30.18	14.31.18	14.31.17	14.30.17	5.30.44	5.30.45	5.31.45	5.31.46	5.30.46	5.31.44	14.31.19	12.30.19	9.31.34	9.30.34	9.30.35	9.31.35	9.31.36	9.30.36	9.30.37	9.31.37	9.31.38	10.31.29	7.30.46	10.31.25	10.31.26	10.30.26	10.31.27	10.31.28	10.30.28	10.30.29	10.30.27
non-inverted	[68]	[67]	[66]	[65]	[64]	[63]	[62]	[61]	[60]	[59]	[58]	[57]	[56]	[55]	[54]	[53]	[52]	[51]	[50]	[49]	[48]	[47]	[46]	[45]	[44]	[43]	[42]	[41]	[40]	[39]	[38]	[37]	[36]	[35]	[34]	[33]	[32]	[31]	[30]	[29]	[28]	[27]	[26]	[25]	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PMA_RXSYNC_CFG_0	14.31.31	14.30.31	14.30.30	14.31.30	14.31.29	14.30.29	14.30.28
GTX_DUAL:PMA_RXSYNC_CFG_1	5.31.0	5.30.0	5.30.1	5.31.1	5.31.2	5.30.2	5.30.3
non-inverted	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PMA_RX_CFG_0	5.31.49	5.30.59	14.31.12	14.31.11	14.30.11	14.30.10	14.31.10	14.31.9	14.30.9	14.30.8	14.31.8	14.31.7	5.30.49	5.30.51	14.31.4	14.31.3	14.30.3	14.30.2	14.31.2	14.30.6	14.31.6	14.31.5	14.30.5	5.31.50	5.30.50
GTX_DUAL:PMA_RX_CFG_1	14.31.14	14.30.4	5.31.51	5.31.52	5.30.52	5.30.53	5.31.53	5.31.54	5.30.54	5.30.55	5.31.55	5.31.56	14.30.14	14.30.12	5.31.59	5.31.60	5.30.60	5.30.61	5.31.61	5.30.57	5.31.57	5.31.58	5.30.58	14.31.13	14.30.13
non-inverted	[24]	[23]	[22]	[21]	[20]	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:PMA_TX_CFG_0	14.30.60	14.31.60	14.31.59	14.30.59	14.30.58	14.31.58	14.31.57	14.30.57	14.30.56	14.31.56	14.31.55	14.30.55	14.30.54	14.31.54	14.31.53	14.30.53	14.30.52	14.31.52	14.31.51	14.30.51
GTX_DUAL:PMA_TX_CFG_1	5.31.3	5.31.4	5.30.4	5.30.5	5.31.5	5.31.6	5.30.6	5.30.7	5.31.7	5.31.8	5.30.8	5.30.9	5.31.9	5.31.10	5.30.10	5.30.11	5.31.11	5.31.12	5.30.12	5.30.13
non-inverted	[19]	[18]	[17]	[16]	[15]	[14]	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:RX_LOS_INVALID_INCR_0	13.30.16	13.31.16	13.31.15
GTX_DUAL:RX_LOS_INVALID_INCR_1	6.30.47	6.31.47	6.31.48
1	0	0	0
2	0	0	1
4	0	1	0
8	0	1	1
16	1	0	0
32	1	0	1
64	1	1	0
128	1	1	1

GTX_DUAL:RX_LOS_THRESHOLD_0	13.30.14	13.31.14	13.31.13
GTX_DUAL:RX_LOS_THRESHOLD_1	6.30.49	6.31.49	6.31.50
4	0	0	0
8	0	0	1
16	0	1	0
32	0	1	1
64	1	0	0
128	1	0	1
256	1	1	0
512	1	1	1

GTX_DUAL:RX_SLIDE_MODE_0	13.30.13
GTX_DUAL:RX_SLIDE_MODE_1	6.30.50
PCS	0
PMA	1

GTX_DUAL:RX_STATUS_FMT_0	13.30.12
GTX_DUAL:RX_STATUS_FMT_1	6.30.51
PCIE	0
SATA	1

GTX_DUAL:RX_XCLK_SEL_0	13.31.12
GTX_DUAL:RX_XCLK_SEL_1	6.31.51
RXREC	0
RXUSR	1

GTX_DUAL:TERMINATION_IMP_0	12.30.54
GTX_DUAL:TERMINATION_IMP_1	7.30.9
50	0
75	1

GTX_DUAL:TRANS_TIME_FROM_P2_0	12.31.54	12.31.53	12.30.53	12.30.52	12.31.52	12.31.51	12.30.51	12.30.50	12.31.50	12.31.49	12.30.49	12.30.48
GTX_DUAL:TRANS_TIME_FROM_P2_1	7.31.9	7.31.10	7.30.10	7.30.11	7.31.11	7.31.12	7.30.12	7.30.13	7.31.13	7.31.14	7.30.14	7.30.15
non-inverted	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:TX_DETECT_RX_CFG_0	12.31.29	12.30.29	12.30.28	12.31.28	12.31.27	12.30.27	12.30.26	12.31.26	12.31.25	12.30.25	12.30.24	12.31.24	12.31.23	12.30.23
GTX_DUAL:TX_DETECT_RX_CFG_1	7.31.34	7.30.34	7.30.35	7.31.35	7.31.36	7.30.36	7.30.37	7.31.37	7.31.38	7.30.38	7.30.39	7.31.39	7.31.40	7.30.40
non-inverted	[13]	[12]	[11]	[10]	[9]	[8]	[7]	[6]	[5]	[4]	[3]	[2]	[1]	[0]

GTX_DUAL:TX_XCLK_SEL_0	12.31.20
GTX_DUAL:TX_XCLK_SEL_1	7.31.43
TXOUT	0
TXUSR	1

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