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GTX transceivers

TODO: document

Tile GTX

Cells: 20

Bel GTX_DUAL

virtex5 GTX bel GTX_DUAL
PinDirectionWires
DADDR0inputCELL10.IMUX.IMUX32.DELAY
DADDR1inputCELL10.IMUX.IMUX31.DELAY
DADDR2inputCELL10.IMUX.IMUX24.DELAY
DADDR3inputCELL9.IMUX.IMUX29.DELAY
DADDR4inputCELL9.IMUX.IMUX28.DELAY
DADDR5inputCELL9.IMUX.IMUX27.DELAY
DADDR6inputCELL9.IMUX.IMUX26.DELAY
DCLKinputCELL7.IMUX.CLK1
DENinputCELL10.IMUX.IMUX39.DELAY
DFECLKDLYADJ00inputCELL14.IMUX.IMUX23.DELAY
DFECLKDLYADJ01inputCELL15.IMUX.IMUX36.DELAY
DFECLKDLYADJ02inputCELL15.IMUX.IMUX19.DELAY
DFECLKDLYADJ03inputCELL15.IMUX.IMUX38.DELAY
DFECLKDLYADJ04inputCELL15.IMUX.IMUX39.DELAY
DFECLKDLYADJ05inputCELL15.IMUX.IMUX40.DELAY
DFECLKDLYADJ10inputCELL5.IMUX.IMUX24.DELAY
DFECLKDLYADJ11inputCELL4.IMUX.IMUX29.DELAY
DFECLKDLYADJ12inputCELL4.IMUX.IMUX34.DELAY
DFECLKDLYADJ13inputCELL4.IMUX.IMUX27.DELAY
DFECLKDLYADJ14inputCELL4.IMUX.IMUX32.DELAY
DFECLKDLYADJ15inputCELL4.IMUX.IMUX31.DELAY
DFECLKDLYADJMONITOR00outputCELL15.OUT4.TMIN
DFECLKDLYADJMONITOR01outputCELL15.OUT0.TMIN
DFECLKDLYADJMONITOR02outputCELL15.OUT19.TMIN
DFECLKDLYADJMONITOR03outputCELL15.OUT16.TMIN
DFECLKDLYADJMONITOR04outputCELL15.OUT6.TMIN
DFECLKDLYADJMONITOR05outputCELL15.OUT15.TMIN
DFECLKDLYADJMONITOR10outputCELL4.OUT15.TMIN
DFECLKDLYADJMONITOR11outputCELL4.OUT7.TMIN
DFECLKDLYADJMONITOR12outputCELL4.OUT3.TMIN
DFECLKDLYADJMONITOR13outputCELL4.OUT14.TMIN
DFECLKDLYADJMONITOR14outputCELL4.OUT13.TMIN
DFECLKDLYADJMONITOR15outputCELL4.OUT1.TMIN
DFEEYEDACMONITOR00outputCELL14.OUT0.TMIN
DFEEYEDACMONITOR01outputCELL14.OUT19.TMIN
DFEEYEDACMONITOR02outputCELL14.OUT16.TMIN
DFEEYEDACMONITOR03outputCELL14.OUT2.TMIN
DFEEYEDACMONITOR04outputCELL15.OUT8.TMIN
DFEEYEDACMONITOR10outputCELL6.OUT18.TMIN
DFEEYEDACMONITOR11outputCELL5.OUT15.TMIN
DFEEYEDACMONITOR12outputCELL5.OUT14.TMIN
DFEEYEDACMONITOR13outputCELL5.OUT13.TMIN
DFEEYEDACMONITOR14outputCELL5.OUT12.TMIN
DFESENSCAL00outputCELL10.OUT18.TMIN
DFESENSCAL01outputCELL10.OUT19.TMIN
DFESENSCAL02outputCELL10.OUT17.TMIN
DFESENSCAL10outputCELL9.OUT7.TMIN
DFESENSCAL11outputCELL9.OUT9.TMIN
DFESENSCAL12outputCELL9.OUT22.TMIN
DFETAP100inputCELL14.IMUX.IMUX31.DELAY
DFETAP101inputCELL14.IMUX.IMUX26.DELAY
DFETAP102inputCELL14.IMUX.IMUX33.DELAY
DFETAP103inputCELL14.IMUX.IMUX34.DELAY
DFETAP104inputCELL14.IMUX.IMUX35.DELAY
DFETAP110inputCELL5.IMUX.IMUX28.DELAY
DFETAP111inputCELL5.IMUX.IMUX33.DELAY
DFETAP112inputCELL5.IMUX.IMUX26.DELAY
DFETAP113inputCELL5.IMUX.IMUX25.DELAY
DFETAP114inputCELL5.IMUX.IMUX12.DELAY
DFETAP1MONITOR00outputCELL13.OUT8.TMIN
DFETAP1MONITOR01outputCELL13.OUT0.TMIN
DFETAP1MONITOR02outputCELL13.OUT16.TMIN
DFETAP1MONITOR03outputCELL13.OUT6.TMIN
DFETAP1MONITOR04outputCELL13.OUT15.TMIN
DFETAP1MONITOR10outputCELL7.OUT22.TMIN
DFETAP1MONITOR11outputCELL6.OUT21.TMIN
DFETAP1MONITOR12outputCELL6.OUT7.TMIN
DFETAP1MONITOR13outputCELL6.OUT23.TMIN
DFETAP1MONITOR14outputCELL6.OUT5.TMIN
DFETAP200inputCELL14.IMUX.IMUX12.DELAY
DFETAP201inputCELL14.IMUX.IMUX36.DELAY
DFETAP202inputCELL14.IMUX.IMUX37.DELAY
DFETAP203inputCELL14.IMUX.IMUX38.DELAY
DFETAP204inputCELL14.IMUX.IMUX39.DELAY
DFETAP210inputCELL5.IMUX.IMUX29.DELAY
DFETAP211inputCELL5.IMUX.IMUX11.DELAY
DFETAP212inputCELL5.IMUX.IMUX22.DELAY
DFETAP213inputCELL5.IMUX.IMUX27.DELAY
DFETAP214inputCELL5.IMUX.IMUX20.DELAY
DFETAP2MONITOR00outputCELL12.OUT12.TMIN
DFETAP2MONITOR01outputCELL12.OUT19.TMIN
DFETAP2MONITOR02outputCELL12.OUT16.TMIN
DFETAP2MONITOR03outputCELL12.OUT2.TMIN
DFETAP2MONITOR04outputCELL12.OUT6.TMIN
DFETAP2MONITOR10outputCELL8.OUT22.TMIN
DFETAP2MONITOR11outputCELL7.OUT16.TMIN
DFETAP2MONITOR12outputCELL7.OUT14.TMIN
DFETAP2MONITOR13outputCELL7.OUT13.TMIN
DFETAP2MONITOR14outputCELL7.OUT1.TMIN
DFETAP300inputCELL13.IMUX.IMUX25.DELAY
DFETAP301inputCELL13.IMUX.IMUX26.DELAY
DFETAP302inputCELL13.IMUX.IMUX27.DELAY
DFETAP303inputCELL13.IMUX.IMUX28.DELAY
DFETAP310inputCELL6.IMUX.IMUX34.DELAY
DFETAP311inputCELL6.IMUX.IMUX39.DELAY
DFETAP312inputCELL6.IMUX.IMUX32.DELAY
DFETAP313inputCELL6.IMUX.IMUX31.DELAY
DFETAP3MONITOR00outputCELL11.OUT8.TMIN
DFETAP3MONITOR01outputCELL11.OUT18.TMIN
DFETAP3MONITOR02outputCELL11.OUT1.TMIN
DFETAP3MONITOR03outputCELL11.OUT11.TMIN
DFETAP3MONITOR10outputCELL8.OUT21.TMIN
DFETAP3MONITOR11outputCELL8.OUT7.TMIN
DFETAP3MONITOR12outputCELL8.OUT20.TMIN
DFETAP3MONITOR13outputCELL8.OUT4.TMIN
DFETAP400inputCELL12.IMUX.IMUX37.DELAY
DFETAP401inputCELL12.IMUX.IMUX40.DELAY
DFETAP402inputCELL12.IMUX.IMUX41.DELAY
DFETAP403inputCELL13.IMUX.IMUX36.DELAY
DFETAP410inputCELL7.IMUX.IMUX28.DELAY
DFETAP411inputCELL7.IMUX.IMUX25.DELAY
DFETAP412inputCELL7.IMUX.IMUX24.DELAY
DFETAP413inputCELL6.IMUX.IMUX11.DELAY
DFETAP4MONITOR00outputCELL10.OUT1.TMIN
DFETAP4MONITOR01outputCELL10.OUT14.TMIN
DFETAP4MONITOR02outputCELL10.OUT20.TMIN
DFETAP4MONITOR03outputCELL10.OUT3.TMIN
DFETAP4MONITOR10outputCELL9.OUT17.TMIN
DFETAP4MONITOR11outputCELL9.OUT16.TMIN
DFETAP4MONITOR12outputCELL9.OUT19.TMIN
DFETAP4MONITOR13outputCELL9.OUT5.TMIN
DI0inputCELL11.IMUX.IMUX3.DELAY
DI1inputCELL11.IMUX.IMUX2.DELAY
DI10inputCELL9.IMUX.IMUX43.DELAY
DI11inputCELL9.IMUX.IMUX42.DELAY
DI12inputCELL8.IMUX.IMUX47.DELAY
DI13inputCELL8.IMUX.IMUX46.DELAY
DI14inputCELL8.IMUX.IMUX45.DELAY
DI15inputCELL8.IMUX.IMUX44.DELAY
DI2inputCELL11.IMUX.IMUX1.DELAY
DI3inputCELL11.IMUX.IMUX0.DELAY
DI4inputCELL10.IMUX.IMUX3.DELAY
DI5inputCELL10.IMUX.IMUX2.DELAY
DI6inputCELL10.IMUX.IMUX1.DELAY
DI7inputCELL10.IMUX.IMUX0.DELAY
DI8inputCELL9.IMUX.IMUX45.DELAY
DI9inputCELL9.IMUX.IMUX44.DELAY
DO0outputCELL11.OUT21.TMIN
DO1outputCELL11.OUT17.TMIN
DO10outputCELL9.OUT20.TMIN
DO11outputCELL9.OUT10.TMIN
DO12outputCELL8.OUT13.TMIN
DO13outputCELL8.OUT18.TMIN
DO14outputCELL8.OUT12.TMIN
DO15outputCELL8.OUT8.TMIN
DO2outputCELL11.OUT15.TMIN
DO3outputCELL11.OUT14.TMIN
DO4outputCELL10.OUT10.TMIN
DO5outputCELL10.OUT9.TMIN
DO6outputCELL10.OUT0.TMIN
DO7outputCELL10.OUT12.TMIN
DO8outputCELL9.OUT21.TMIN
DO9outputCELL9.OUT6.TMIN
DRDYoutputCELL9.OUT15.TMIN
DWEinputCELL9.IMUX.IMUX19.DELAY
GREFCLKinputCELL12.IMUX.CLK0
GTXRESETinputCELL11.IMUX.IMUX36.DELAY
GTXTEST0inputCELL19.IMUX.IMUX27.DELAY
GTXTEST1inputCELL0.IMUX.IMUX13.DELAY
GTXTEST10inputCELL0.IMUX.IMUX12.DELAY
GTXTEST11inputCELL0.IMUX.IMUX11.DELAY
GTXTEST12inputCELL0.IMUX.IMUX14.DELAY
GTXTEST13inputCELL10.IMUX.IMUX33.DELAY
GTXTEST2inputCELL9.IMUX.IMUX16.DELAY
GTXTEST3inputCELL9.IMUX.IMUX17.DELAY
GTXTEST4inputCELL14.IMUX.IMUX22.DELAY
GTXTEST5inputCELL19.IMUX.IMUX28.DELAY
GTXTEST6inputCELL19.IMUX.IMUX6.DELAY
GTXTEST7inputCELL19.IMUX.IMUX29.DELAY
GTXTEST8inputCELL10.IMUX.IMUX40.DELAY
GTXTEST9inputCELL5.IMUX.IMUX13.DELAY
INTDATAWIDTHinputCELL10.IMUX.IMUX6.DELAY
LOOPBACK00inputCELL12.IMUX.IMUX15.DELAY
LOOPBACK01inputCELL12.IMUX.IMUX16.DELAY
LOOPBACK02inputCELL12.IMUX.IMUX17.DELAY
LOOPBACK10inputCELL7.IMUX.IMUX20.DELAY
LOOPBACK11inputCELL7.IMUX.IMUX19.DELAY
LOOPBACK12inputCELL7.IMUX.IMUX18.DELAY
PHYSTATUS0outputCELL15.OUT12.TMIN
PHYSTATUS1outputCELL4.OUT17.TMIN
PLLLKDEToutputCELL9.OUT23.TMIN
PLLLKDETENinputCELL9.IMUX.IMUX8.DELAY
PLLPOWERDOWNinputCELL10.IMUX.IMUX36.DELAY
PMAAMUX0inputCELL9.IMUX.IMUX3.DELAY
PMAAMUX1inputCELL9.IMUX.IMUX4.DELAY
PMAAMUX2inputCELL9.IMUX.IMUX5.DELAY
PMATSTCLKoutputCELL10.OUT22.TMIN
PMATSTCLKSEL0inputCELL10.IMUX.IMUX14.DELAY
PMATSTCLKSEL1inputCELL10.IMUX.IMUX13.DELAY
PMATSTCLKSEL2inputCELL10.IMUX.IMUX12.DELAY
PRBSCNTRESET0inputCELL11.IMUX.IMUX45.DELAY
PRBSCNTRESET1inputCELL8.IMUX.IMUX2.DELAY
REFCLKOUToutputCELL10.OUT8.TMIN
REFCLKPWRDNBinputCELL9.IMUX.IMUX18.DELAY
RESETDONE0outputCELL15.OUT7.TMIN
RESETDONE1outputCELL4.OUT0.TMIN
RXBUFRESET0inputCELL12.IMUX.IMUX43.DELAY
RXBUFRESET1inputCELL7.IMUX.IMUX4.DELAY
RXBUFSTATUS00outputCELL15.OUT1.TMIN
RXBUFSTATUS01outputCELL15.OUT13.TMIN
RXBUFSTATUS02outputCELL15.OUT14.TMIN
RXBUFSTATUS10outputCELL4.OUT6.TMIN
RXBUFSTATUS11outputCELL4.OUT16.TMIN
RXBUFSTATUS12outputCELL4.OUT19.TMIN
RXBYTEISALIGNED0outputCELL14.OUT7.TMIN
RXBYTEISALIGNED1outputCELL5.OUT0.TMIN
RXBYTEREALIGN0outputCELL14.OUT15.TMIN
RXBYTEREALIGN1outputCELL5.OUT18.TMIN
RXCDRRESET0inputCELL12.IMUX.IMUX47.DELAY
RXCDRRESET1inputCELL7.IMUX.IMUX0.DELAY
RXCHANBONDSEQ0outputCELL12.OUT1.TMIN
RXCHANBONDSEQ1outputCELL7.OUT6.TMIN
RXCHANISALIGNED0outputCELL12.OUT15.TMIN
RXCHANISALIGNED1outputCELL7.OUT18.TMIN
RXCHANREALIGN0outputCELL12.OUT3.TMIN
RXCHANREALIGN1outputCELL7.OUT4.TMIN
RXCHARISCOMMA00outputCELL14.OUT12.TMIN
RXCHARISCOMMA01outputCELL13.OUT12.TMIN
RXCHARISCOMMA02outputCELL16.OUT1.TMIN
RXCHARISCOMMA03outputCELL17.OUT21.TMIN
RXCHARISCOMMA10outputCELL5.OUT17.TMIN
RXCHARISCOMMA11outputCELL6.OUT17.TMIN
RXCHARISCOMMA12outputCELL3.OUT7.TMIN
RXCHARISCOMMA13outputCELL2.OUT3.TMIN
RXCHARISK00outputCELL14.OUT13.TMIN
RXCHARISK01outputCELL13.OUT13.TMIN
RXCHARISK02outputCELL17.OUT12.TMIN
RXCHARISK03outputCELL18.OUT18.TMIN
RXCHARISK10outputCELL5.OUT16.TMIN
RXCHARISK11outputCELL6.OUT16.TMIN
RXCHARISK12outputCELL3.OUT12.TMIN
RXCHARISK13outputCELL1.OUT21.TMIN
RXCHBONDI00inputCELL13.IMUX.IMUX44.DELAY
RXCHBONDI01inputCELL13.IMUX.IMUX45.DELAY
RXCHBONDI02inputCELL13.IMUX.IMUX46.DELAY
RXCHBONDI03inputCELL13.IMUX.IMUX43.DELAY
RXCHBONDI10inputCELL6.IMUX.IMUX3.DELAY
RXCHBONDI11inputCELL6.IMUX.IMUX2.DELAY
RXCHBONDI12inputCELL6.IMUX.IMUX1.DELAY
RXCHBONDI13inputCELL6.IMUX.IMUX23.DELAY
RXCHBONDO00outputCELL12.OUT14.TMIN
RXCHBONDO01outputCELL12.OUT7.TMIN
RXCHBONDO02outputCELL12.OUT21.TMIN
RXCHBONDO03outputCELL12.OUT11.TMIN
RXCHBONDO10outputCELL7.OUT19.TMIN
RXCHBONDO11outputCELL7.OUT0.TMIN
RXCHBONDO12outputCELL7.OUT8.TMIN
RXCHBONDO13outputCELL7.OUT5.TMIN
RXCLKCORCNT00outputCELL16.OUT5.TMIN
RXCLKCORCNT01outputCELL16.OUT23.TMIN
RXCLKCORCNT02outputCELL16.OUT20.TMIN
RXCLKCORCNT10outputCELL3.OUT2.TMIN
RXCLKCORCNT11outputCELL3.OUT10.TMIN
RXCLKCORCNT12outputCELL3.OUT9.TMIN
RXCOMMADET0outputCELL14.OUT21.TMIN
RXCOMMADET1outputCELL5.OUT8.TMIN
RXCOMMADETUSE0inputCELL15.IMUX.IMUX30.DELAY
RXCOMMADETUSE1inputCELL4.IMUX.IMUX17.DELAY
RXDATA00outputCELL15.OUT20.TMIN
RXDATA01outputCELL15.OUT23.TMIN
RXDATA010outputCELL13.OUT5.TMIN
RXDATA011outputCELL13.OUT22.TMIN
RXDATA012outputCELL12.OUT20.TMIN
RXDATA013outputCELL12.OUT23.TMIN
RXDATA014outputCELL12.OUT5.TMIN
RXDATA015outputCELL12.OUT22.TMIN
RXDATA016outputCELL15.OUT17.TMIN
RXDATA017outputCELL15.OUT21.TMIN
RXDATA018outputCELL16.OUT12.TMIN
RXDATA019outputCELL16.OUT16.TMIN
RXDATA02outputCELL15.OUT5.TMIN
RXDATA020outputCELL16.OUT2.TMIN
RXDATA021outputCELL16.OUT6.TMIN
RXDATA022outputCELL16.OUT11.TMIN
RXDATA023outputCELL16.OUT17.TMIN
RXDATA024outputCELL17.OUT9.TMIN
RXDATA025outputCELL17.OUT23.TMIN
RXDATA026outputCELL17.OUT10.TMIN
RXDATA027outputCELL17.OUT16.TMIN
RXDATA028outputCELL18.OUT19.TMIN
RXDATA029outputCELL18.OUT16.TMIN
RXDATA03outputCELL15.OUT22.TMIN
RXDATA030outputCELL18.OUT20.TMIN
RXDATA031outputCELL18.OUT11.TMIN
RXDATA04outputCELL14.OUT20.TMIN
RXDATA05outputCELL14.OUT23.TMIN
RXDATA06outputCELL14.OUT5.TMIN
RXDATA07outputCELL14.OUT22.TMIN
RXDATA08outputCELL13.OUT20.TMIN
RXDATA09outputCELL13.OUT23.TMIN
RXDATA10outputCELL4.OUT9.TMIN
RXDATA11outputCELL4.OUT10.TMIN
RXDATA110outputCELL6.OUT2.TMIN
RXDATA111outputCELL6.OUT11.TMIN
RXDATA112outputCELL7.OUT9.TMIN
RXDATA113outputCELL7.OUT10.TMIN
RXDATA114outputCELL7.OUT2.TMIN
RXDATA115outputCELL7.OUT11.TMIN
RXDATA116outputCELL4.OUT22.TMIN
RXDATA117outputCELL4.OUT18.TMIN
RXDATA118outputCELL4.OUT12.TMIN
RXDATA119outputCELL3.OUT16.TMIN
RXDATA12outputCELL4.OUT2.TMIN
RXDATA120outputCELL3.OUT14.TMIN
RXDATA121outputCELL3.OUT23.TMIN
RXDATA122outputCELL3.OUT5.TMIN
RXDATA123outputCELL3.OUT22.TMIN
RXDATA124outputCELL2.OUT11.TMIN
RXDATA125outputCELL2.OUT7.TMIN
RXDATA126outputCELL2.OUT16.TMIN
RXDATA127outputCELL2.OUT19.TMIN
RXDATA128outputCELL1.OUT6.TMIN
RXDATA129outputCELL1.OUT20.TMIN
RXDATA13outputCELL4.OUT11.TMIN
RXDATA130outputCELL1.OUT9.TMIN
RXDATA131outputCELL1.OUT4.TMIN
RXDATA14outputCELL5.OUT9.TMIN
RXDATA15outputCELL5.OUT10.TMIN
RXDATA16outputCELL5.OUT2.TMIN
RXDATA17outputCELL5.OUT11.TMIN
RXDATA18outputCELL6.OUT9.TMIN
RXDATA19outputCELL6.OUT10.TMIN
RXDATAVALID0outputCELL19.OUT23.TMIN
RXDATAVALID1outputCELL0.OUT12.TMIN
RXDATAWIDTH00inputCELL15.IMUX.IMUX37.DELAY
RXDATAWIDTH01inputCELL15.IMUX.IMUX18.DELAY
RXDATAWIDTH10inputCELL4.IMUX.IMUX10.DELAY
RXDATAWIDTH11inputCELL4.IMUX.IMUX15.DELAY
RXDEC8B10BUSE0inputCELL13.IMUX.IMUX41.DELAY
RXDEC8B10BUSE1inputCELL6.IMUX.IMUX6.DELAY
RXDISPERR00outputCELL14.OUT14.TMIN
RXDISPERR01outputCELL13.OUT14.TMIN
RXDISPERR02outputCELL17.OUT4.TMIN
RXDISPERR03outputCELL18.OUT4.TMIN
RXDISPERR10outputCELL5.OUT19.TMIN
RXDISPERR11outputCELL6.OUT19.TMIN
RXDISPERR12outputCELL2.OUT17.TMIN
RXDISPERR13outputCELL1.OUT15.TMIN
RXELECIDLE0outputCELL17.OUT5.TMIN
RXELECIDLE1outputCELL2.OUT2.TMIN
RXENCHANSYNC0inputCELL13.IMUX.IMUX23.DELAY
RXENCHANSYNC1inputCELL6.IMUX.IMUX24.DELAY
RXENEQB0inputCELL15.IMUX.IMUX42.DELAY
RXENEQB1inputCELL4.IMUX.IMUX5.DELAY
RXENMCOMMAALIGN0inputCELL15.IMUX.IMUX45.DELAY
RXENMCOMMAALIGN1inputCELL4.IMUX.IMUX2.DELAY
RXENPCOMMAALIGN0inputCELL15.IMUX.IMUX46.DELAY
RXENPCOMMAALIGN1inputCELL4.IMUX.IMUX1.DELAY
RXENPMAPHASEALIGN0inputCELL12.IMUX.IMUX13.DELAY
RXENPMAPHASEALIGN1inputCELL7.IMUX.IMUX34.DELAY
RXENPRBSTST00inputCELL15.IMUX.IMUX28.DELAY
RXENPRBSTST01inputCELL15.IMUX.IMUX29.DELAY
RXENPRBSTST10inputCELL4.IMUX.IMUX25.DELAY
RXENPRBSTST11inputCELL4.IMUX.IMUX24.DELAY
RXENSAMPLEALIGN0inputCELL15.IMUX.IMUX14.DELAY
RXENSAMPLEALIGN1inputCELL4.IMUX.IMUX33.DELAY
RXEQMIX00inputCELL14.IMUX.IMUX46.DELAY
RXEQMIX01inputCELL14.IMUX.IMUX47.DELAY
RXEQMIX10inputCELL5.IMUX.IMUX1.DELAY
RXEQMIX11inputCELL5.IMUX.IMUX0.DELAY
RXEQPOLE00inputCELL14.IMUX.IMUX42.DELAY
RXEQPOLE01inputCELL14.IMUX.IMUX43.DELAY
RXEQPOLE02inputCELL14.IMUX.IMUX44.DELAY
RXEQPOLE03inputCELL14.IMUX.IMUX45.DELAY
RXEQPOLE10inputCELL5.IMUX.IMUX5.DELAY
RXEQPOLE11inputCELL5.IMUX.IMUX4.DELAY
RXEQPOLE12inputCELL5.IMUX.IMUX3.DELAY
RXEQPOLE13inputCELL5.IMUX.IMUX2.DELAY
RXGEARBOXSLIP0inputCELL15.IMUX.IMUX17.DELAY
RXGEARBOXSLIP1inputCELL4.IMUX.IMUX22.DELAY
RXHEADER00outputCELL19.OUT22.TMIN
RXHEADER01outputCELL19.OUT0.TMIN
RXHEADER02outputCELL19.OUT9.TMIN
RXHEADER10outputCELL0.OUT17.TMIN
RXHEADER11outputCELL0.OUT6.TMIN
RXHEADER12outputCELL0.OUT16.TMIN
RXHEADERVALID0outputCELL19.OUT8.TMIN
RXHEADERVALID1outputCELL0.OUT11.TMIN
RXLOSSOFSYNC00outputCELL13.OUT11.TMIN
RXLOSSOFSYNC01outputCELL13.OUT21.TMIN
RXLOSSOFSYNC10outputCELL6.OUT22.TMIN
RXLOSSOFSYNC11outputCELL6.OUT8.TMIN
RXNOTINTABLE00outputCELL14.OUT3.TMIN
RXNOTINTABLE01outputCELL13.OUT3.TMIN
RXNOTINTABLE02outputCELL16.OUT0.TMIN
RXNOTINTABLE03outputCELL17.OUT7.TMIN
RXNOTINTABLE10outputCELL5.OUT4.TMIN
RXNOTINTABLE11outputCELL6.OUT4.TMIN
RXNOTINTABLE12outputCELL3.OUT17.TMIN
RXNOTINTABLE13outputCELL2.OUT4.TMIN
RXOVERSAMPLEERR0outputCELL15.OUT3.TMIN
RXOVERSAMPLEERR1outputCELL4.OUT4.TMIN
RXPMASETPHASE0inputCELL12.IMUX.IMUX7.DELAY
RXPMASETPHASE1inputCELL7.IMUX.IMUX40.DELAY
RXPOLARITY0inputCELL15.IMUX.IMUX41.DELAY
RXPOLARITY1inputCELL4.IMUX.IMUX0.DELAY
RXPOWERDOWN00inputCELL12.IMUX.IMUX38.DELAY
RXPOWERDOWN01inputCELL12.IMUX.IMUX39.DELAY
RXPOWERDOWN10inputCELL7.IMUX.IMUX9.DELAY
RXPOWERDOWN11inputCELL7.IMUX.IMUX8.DELAY
RXPRBSERR0outputCELL16.OUT22.TMIN
RXPRBSERR1outputCELL3.OUT11.TMIN
RXRECCLK0outputCELL12.OUT13.TMIN
RXRECCLK1outputCELL7.OUT20.TMIN
RXRESET0inputCELL12.IMUX.IMUX42.DELAY
RXRESET1inputCELL7.IMUX.IMUX5.DELAY
RXRUNDISP00outputCELL14.OUT1.TMIN
RXRUNDISP01outputCELL13.OUT1.TMIN
RXRUNDISP02outputCELL16.OUT19.TMIN
RXRUNDISP03outputCELL18.OUT8.TMIN
RXRUNDISP10outputCELL5.OUT6.TMIN
RXRUNDISP11outputCELL6.OUT6.TMIN
RXRUNDISP12outputCELL3.OUT20.TMIN
RXRUNDISP13outputCELL2.OUT18.TMIN
RXSLIDE0inputCELL15.IMUX.IMUX44.DELAY
RXSLIDE1inputCELL4.IMUX.IMUX3.DELAY
RXSTARTOFSEQ0outputCELL19.OUT18.TMIN
RXSTARTOFSEQ1outputCELL0.OUT2.TMIN
RXSTATUS00outputCELL16.OUT14.TMIN
RXSTATUS01outputCELL16.OUT7.TMIN
RXSTATUS02outputCELL16.OUT21.TMIN
RXSTATUS10outputCELL3.OUT19.TMIN
RXSTATUS11outputCELL3.OUT0.TMIN
RXSTATUS12outputCELL3.OUT8.TMIN
RXUSRCLK0inputCELL10.IMUX.CLK0
RXUSRCLK1inputCELL9.IMUX.CLK1
RXUSRCLK20inputCELL10.IMUX.CLK1
RXUSRCLK21inputCELL9.IMUX.CLK0
RXVALID0outputCELL13.OUT7.TMIN
RXVALID1outputCELL6.OUT0.TMIN
SCANENinputCELL19.IMUX.IMUX17.DELAY
SCANINPCS0inputCELL19.IMUX.IMUX47.DELAY
SCANINPCS1inputCELL0.IMUX.IMUX30.DELAY
SCANINPCSCOMMONinputCELL11.IMUX.IMUX29.DELAY
SCANMODEinputCELL0.IMUX.IMUX36.DELAY
SCANOUTPCS0outputCELL12.OUT10.TMIN
SCANOUTPCS1outputCELL7.OUT7.TMIN
SCANOUTPCSCOMMONoutputCELL8.OUT1.TMIN
TSTPWRDN00inputCELL13.IMUX.IMUX31.DELAY
TSTPWRDN01inputCELL13.IMUX.IMUX32.DELAY
TSTPWRDN02inputCELL13.IMUX.IMUX33.DELAY
TSTPWRDN03inputCELL13.IMUX.IMUX34.DELAY
TSTPWRDN04inputCELL13.IMUX.IMUX35.DELAY
TSTPWRDN10inputCELL6.IMUX.IMUX16.DELAY
TSTPWRDN11inputCELL6.IMUX.IMUX15.DELAY
TSTPWRDN12inputCELL6.IMUX.IMUX14.DELAY
TSTPWRDN13inputCELL6.IMUX.IMUX13.DELAY
TSTPWRDN14inputCELL6.IMUX.IMUX12.DELAY
TSTPWRDNOVRD0inputCELL18.IMUX.IMUX30.DELAY
TSTPWRDNOVRD1inputCELL1.IMUX.IMUX47.DELAY
TXBUFDIFFCTRL00inputCELL19.IMUX.IMUX30.DELAY
TXBUFDIFFCTRL01inputCELL19.IMUX.IMUX31.DELAY
TXBUFDIFFCTRL02inputCELL19.IMUX.IMUX32.DELAY
TXBUFDIFFCTRL10inputCELL0.IMUX.IMUX17.DELAY
TXBUFDIFFCTRL11inputCELL0.IMUX.IMUX16.DELAY
TXBUFDIFFCTRL12inputCELL0.IMUX.IMUX15.DELAY
TXBUFSTATUS00outputCELL18.OUT0.TMIN
TXBUFSTATUS01outputCELL18.OUT23.TMIN
TXBUFSTATUS10outputCELL1.OUT2.TMIN
TXBUFSTATUS11outputCELL1.OUT10.TMIN
TXBYPASS8B10B00inputCELL18.IMUX.IMUX29.DELAY
TXBYPASS8B10B01inputCELL17.IMUX.IMUX29.DELAY
TXBYPASS8B10B02inputCELL15.IMUX.IMUX27.DELAY
TXBYPASS8B10B03inputCELL15.IMUX.IMUX21.DELAY
TXBYPASS8B10B10inputCELL1.IMUX.IMUX12.DELAY
TXBYPASS8B10B11inputCELL2.IMUX.IMUX24.DELAY
TXBYPASS8B10B12inputCELL4.IMUX.IMUX20.DELAY
TXBYPASS8B10B13inputCELL4.IMUX.IMUX14.DELAY
TXCHARDISPMODE00inputCELL18.IMUX.IMUX27.DELAY
TXCHARDISPMODE01inputCELL17.IMUX.IMUX27.DELAY
TXCHARDISPMODE02inputCELL19.IMUX.IMUX15.DELAY
TXCHARDISPMODE03inputCELL17.IMUX.IMUX7.DELAY
TXCHARDISPMODE10inputCELL1.IMUX.IMUX8.DELAY
TXCHARDISPMODE11inputCELL2.IMUX.IMUX20.DELAY
TXCHARDISPMODE12inputCELL0.IMUX.IMUX38.DELAY
TXCHARDISPMODE13inputCELL2.IMUX.IMUX40.DELAY
TXCHARDISPVAL00inputCELL18.IMUX.IMUX26.DELAY
TXCHARDISPVAL01inputCELL17.IMUX.IMUX26.DELAY
TXCHARDISPVAL02inputCELL19.IMUX.IMUX2.DELAY
TXCHARDISPVAL03inputCELL17.IMUX.IMUX25.DELAY
TXCHARDISPVAL10inputCELL1.IMUX.IMUX21.DELAY
TXCHARDISPVAL11inputCELL2.IMUX.IMUX21.DELAY
TXCHARDISPVAL12inputCELL0.IMUX.IMUX9.DELAY
TXCHARDISPVAL13inputCELL2.IMUX.IMUX28.DELAY
TXCHARISK00inputCELL18.IMUX.IMUX46.DELAY
TXCHARISK01inputCELL17.IMUX.IMUX28.DELAY
TXCHARISK02inputCELL18.IMUX.IMUX28.DELAY
TXCHARISK03inputCELL17.IMUX.IMUX8.DELAY
TXCHARISK10inputCELL1.IMUX.IMUX1.DELAY
TXCHARISK11inputCELL2.IMUX.IMUX25.DELAY
TXCHARISK12inputCELL1.IMUX.IMUX13.DELAY
TXCHARISK13inputCELL2.IMUX.IMUX39.DELAY
TXCOMSTART0inputCELL18.IMUX.IMUX4.DELAY
TXCOMSTART1inputCELL1.IMUX.IMUX37.DELAY
TXCOMTYPE0inputCELL18.IMUX.IMUX5.DELAY
TXCOMTYPE1inputCELL1.IMUX.IMUX0.DELAY
TXDATA00inputCELL19.IMUX.IMUX45.DELAY
TXDATA01inputCELL19.IMUX.IMUX44.DELAY
TXDATA010inputCELL17.IMUX.IMUX43.DELAY
TXDATA011inputCELL17.IMUX.IMUX42.DELAY
TXDATA012inputCELL16.IMUX.IMUX45.DELAY
TXDATA013inputCELL16.IMUX.IMUX44.DELAY
TXDATA014inputCELL16.IMUX.IMUX43.DELAY
TXDATA015inputCELL16.IMUX.IMUX42.DELAY
TXDATA016inputCELL19.IMUX.IMUX23.DELAY
TXDATA017inputCELL19.IMUX.IMUX22.DELAY
TXDATA018inputCELL19.IMUX.IMUX20.DELAY
TXDATA019inputCELL19.IMUX.IMUX12.DELAY
TXDATA02inputCELL19.IMUX.IMUX43.DELAY
TXDATA020inputCELL18.IMUX.IMUX35.DELAY
TXDATA021inputCELL18.IMUX.IMUX33.DELAY
TXDATA022inputCELL18.IMUX.IMUX32.DELAY
TXDATA023inputCELL18.IMUX.IMUX31.DELAY
TXDATA024inputCELL17.IMUX.IMUX23.DELAY
TXDATA025inputCELL17.IMUX.IMUX22.DELAY
TXDATA026inputCELL17.IMUX.IMUX21.DELAY
TXDATA027inputCELL17.IMUX.IMUX20.DELAY
TXDATA028inputCELL16.IMUX.IMUX23.DELAY
TXDATA029inputCELL16.IMUX.IMUX22.DELAY
TXDATA03inputCELL19.IMUX.IMUX42.DELAY
TXDATA030inputCELL16.IMUX.IMUX21.DELAY
TXDATA031inputCELL16.IMUX.IMUX20.DELAY
TXDATA04inputCELL18.IMUX.IMUX45.DELAY
TXDATA05inputCELL18.IMUX.IMUX44.DELAY
TXDATA06inputCELL18.IMUX.IMUX43.DELAY
TXDATA07inputCELL18.IMUX.IMUX42.DELAY
TXDATA08inputCELL17.IMUX.IMUX45.DELAY
TXDATA09inputCELL17.IMUX.IMUX44.DELAY
TXDATA10inputCELL0.IMUX.IMUX32.DELAY
TXDATA11inputCELL0.IMUX.IMUX33.DELAY
TXDATA110inputCELL2.IMUX.IMUX34.DELAY
TXDATA111inputCELL2.IMUX.IMUX35.DELAY
TXDATA112inputCELL3.IMUX.IMUX32.DELAY
TXDATA113inputCELL3.IMUX.IMUX33.DELAY
TXDATA114inputCELL3.IMUX.IMUX34.DELAY
TXDATA115inputCELL3.IMUX.IMUX35.DELAY
TXDATA116inputCELL0.IMUX.IMUX0.DELAY
TXDATA117inputCELL0.IMUX.IMUX31.DELAY
TXDATA118inputCELL0.IMUX.IMUX27.DELAY
TXDATA119inputCELL0.IMUX.IMUX29.DELAY
TXDATA12inputCELL0.IMUX.IMUX34.DELAY
TXDATA120inputCELL1.IMUX.IMUX6.DELAY
TXDATA121inputCELL1.IMUX.IMUX20.DELAY
TXDATA122inputCELL1.IMUX.IMUX39.DELAY
TXDATA123inputCELL1.IMUX.IMUX28.DELAY
TXDATA124inputCELL2.IMUX.IMUX30.DELAY
TXDATA125inputCELL2.IMUX.IMUX31.DELAY
TXDATA126inputCELL2.IMUX.IMUX38.DELAY
TXDATA127inputCELL2.IMUX.IMUX27.DELAY
TXDATA128inputCELL3.IMUX.IMUX30.DELAY
TXDATA129inputCELL3.IMUX.IMUX31.DELAY
TXDATA13inputCELL0.IMUX.IMUX35.DELAY
TXDATA130inputCELL3.IMUX.IMUX38.DELAY
TXDATA131inputCELL3.IMUX.IMUX39.DELAY
TXDATA14inputCELL1.IMUX.IMUX32.DELAY
TXDATA15inputCELL1.IMUX.IMUX33.DELAY
TXDATA16inputCELL1.IMUX.IMUX34.DELAY
TXDATA17inputCELL1.IMUX.IMUX35.DELAY
TXDATA18inputCELL2.IMUX.IMUX32.DELAY
TXDATA19inputCELL2.IMUX.IMUX33.DELAY
TXDATAWIDTH00inputCELL16.IMUX.IMUX31.DELAY
TXDATAWIDTH01inputCELL16.IMUX.IMUX24.DELAY
TXDATAWIDTH10inputCELL3.IMUX.IMUX4.DELAY
TXDATAWIDTH11inputCELL3.IMUX.IMUX5.DELAY
TXDETECTRX0inputCELL19.IMUX.IMUX18.DELAY
TXDETECTRX1inputCELL0.IMUX.IMUX47.DELAY
TXDIFFCTRL00inputCELL19.IMUX.IMUX33.DELAY
TXDIFFCTRL01inputCELL19.IMUX.IMUX34.DELAY
TXDIFFCTRL02inputCELL19.IMUX.IMUX35.DELAY
TXDIFFCTRL10inputCELL0.IMUX.IMUX8.DELAY
TXDIFFCTRL11inputCELL0.IMUX.IMUX7.DELAY
TXDIFFCTRL12inputCELL0.IMUX.IMUX6.DELAY
TXELECIDLE0inputCELL19.IMUX.IMUX19.DELAY
TXELECIDLE1inputCELL0.IMUX.IMUX4.DELAY
TXENC8B10BUSE0inputCELL16.IMUX.IMUX30.DELAY
TXENC8B10BUSE1inputCELL3.IMUX.IMUX47.DELAY
TXENPMAPHASEALIGN0inputCELL10.IMUX.IMUX16.DELAY
TXENPMAPHASEALIGN1inputCELL9.IMUX.IMUX20.DELAY
TXENPRBSTST00inputCELL18.IMUX.IMUX24.DELAY
TXENPRBSTST01inputCELL18.IMUX.IMUX25.DELAY
TXENPRBSTST10inputCELL1.IMUX.IMUX11.DELAY
TXENPRBSTST11inputCELL1.IMUX.IMUX10.DELAY
TXGEARBOXREADY0outputCELL19.OUT16.TMIN
TXGEARBOXREADY1outputCELL0.OUT0.TMIN
TXHEADER00inputCELL16.IMUX.IMUX32.DELAY
TXHEADER01inputCELL16.IMUX.IMUX33.DELAY
TXHEADER02inputCELL16.IMUX.IMUX4.DELAY
TXHEADER10inputCELL3.IMUX.IMUX9.DELAY
TXHEADER11inputCELL3.IMUX.IMUX20.DELAY
TXHEADER12inputCELL3.IMUX.IMUX7.DELAY
TXINHIBIT0inputCELL16.IMUX.IMUX28.DELAY
TXINHIBIT1inputCELL3.IMUX.IMUX1.DELAY
TXKERR00outputCELL18.OUT5.TMIN
TXKERR01outputCELL17.OUT18.TMIN
TXKERR02outputCELL18.OUT13.TMIN
TXKERR03outputCELL17.OUT22.TMIN
TXKERR10outputCELL1.OUT7.TMIN
TXKERR11outputCELL2.OUT15.TMIN
TXKERR12outputCELL1.OUT14.TMIN
TXKERR13outputCELL2.OUT10.TMIN
TXOUTCLK0outputCELL10.OUT13.TMIN
TXOUTCLK1outputCELL9.OUT2.TMIN
TXPMASETPHASE0inputCELL10.IMUX.IMUX17.DELAY
TXPMASETPHASE1inputCELL9.IMUX.IMUX33.DELAY
TXPOLARITY0inputCELL17.IMUX.IMUX15.DELAY
TXPOLARITY1inputCELL2.IMUX.IMUX2.DELAY
TXPOWERDOWN00inputCELL17.IMUX.IMUX10.DELAY
TXPOWERDOWN01inputCELL17.IMUX.IMUX11.DELAY
TXPOWERDOWN10inputCELL2.IMUX.IMUX43.DELAY
TXPOWERDOWN11inputCELL2.IMUX.IMUX42.DELAY
TXPREEMPHASIS00inputCELL18.IMUX.IMUX15.DELAY
TXPREEMPHASIS01inputCELL18.IMUX.IMUX16.DELAY
TXPREEMPHASIS02inputCELL18.IMUX.IMUX17.DELAY
TXPREEMPHASIS03inputCELL17.IMUX.IMUX37.DELAY
TXPREEMPHASIS10inputCELL1.IMUX.IMUX26.DELAY
TXPREEMPHASIS11inputCELL1.IMUX.IMUX25.DELAY
TXPREEMPHASIS12inputCELL1.IMUX.IMUX24.DELAY
TXPREEMPHASIS13inputCELL2.IMUX.IMUX10.DELAY
TXRESET0inputCELL16.IMUX.IMUX47.DELAY
TXRESET1inputCELL3.IMUX.IMUX0.DELAY
TXRUNDISP00outputCELL18.OUT22.TMIN
TXRUNDISP01outputCELL17.OUT2.TMIN
TXRUNDISP02outputCELL18.OUT15.TMIN
TXRUNDISP03outputCELL16.OUT18.TMIN
TXRUNDISP10outputCELL1.OUT11.TMIN
TXRUNDISP11outputCELL2.OUT5.TMIN
TXRUNDISP12outputCELL1.OUT18.TMIN
TXRUNDISP13outputCELL3.OUT21.TMIN
TXSEQUENCE00inputCELL18.IMUX.IMUX2.DELAY
TXSEQUENCE01inputCELL18.IMUX.IMUX3.DELAY
TXSEQUENCE02inputCELL19.IMUX.IMUX0.DELAY
TXSEQUENCE03inputCELL19.IMUX.IMUX1.DELAY
TXSEQUENCE04inputCELL19.IMUX.IMUX3.DELAY
TXSEQUENCE05inputCELL19.IMUX.IMUX4.DELAY
TXSEQUENCE06inputCELL19.IMUX.IMUX5.DELAY
TXSEQUENCE10inputCELL1.IMUX.IMUX46.DELAY
TXSEQUENCE11inputCELL1.IMUX.IMUX3.DELAY
TXSEQUENCE12inputCELL0.IMUX.IMUX41.DELAY
TXSEQUENCE13inputCELL0.IMUX.IMUX46.DELAY
TXSEQUENCE14inputCELL0.IMUX.IMUX45.DELAY
TXSEQUENCE15inputCELL0.IMUX.IMUX44.DELAY
TXSEQUENCE16inputCELL0.IMUX.IMUX37.DELAY
TXSTARTSEQ0inputCELL16.IMUX.IMUX9.DELAY
TXSTARTSEQ1inputCELL3.IMUX.IMUX8.DELAY
TXUSRCLK0inputCELL11.IMUX.CLK0
TXUSRCLK1inputCELL8.IMUX.CLK1
TXUSRCLK20inputCELL11.IMUX.CLK1
TXUSRCLK21inputCELL8.IMUX.CLK0

Bel BUFDS0

virtex5 GTX bel BUFDS0
PinDirectionWires

Bel CRC32_0

virtex5 GTX bel CRC32_0
PinDirectionWires
CRCCLKinputCELL1.IMUX.CLK1
CRCDATAVALIDinputCELL3.IMUX.IMUX22.DELAY
CRCDATAWIDTH0inputCELL3.IMUX.IMUX40.DELAY
CRCDATAWIDTH1inputCELL3.IMUX.IMUX23.DELAY
CRCDATAWIDTH2inputCELL3.IMUX.IMUX21.DELAY
CRCIN0inputCELL3.IMUX.IMUX17.DELAY
CRCIN1inputCELL3.IMUX.IMUX16.DELAY
CRCIN10inputCELL2.IMUX.IMUX15.DELAY
CRCIN11inputCELL2.IMUX.IMUX14.DELAY
CRCIN12inputCELL2.IMUX.IMUX13.DELAY
CRCIN13inputCELL2.IMUX.IMUX12.DELAY
CRCIN14inputCELL2.IMUX.IMUX37.DELAY
CRCIN15inputCELL2.IMUX.IMUX36.DELAY
CRCIN16inputCELL1.IMUX.IMUX23.DELAY
CRCIN17inputCELL1.IMUX.IMUX22.DELAY
CRCIN18inputCELL1.IMUX.IMUX45.DELAY
CRCIN19inputCELL1.IMUX.IMUX44.DELAY
CRCIN2inputCELL3.IMUX.IMUX15.DELAY
CRCIN20inputCELL1.IMUX.IMUX43.DELAY
CRCIN21inputCELL1.IMUX.IMUX42.DELAY
CRCIN22inputCELL1.IMUX.IMUX19.DELAY
CRCIN23inputCELL1.IMUX.IMUX18.DELAY
CRCIN24inputCELL0.IMUX.IMUX23.DELAY
CRCIN25inputCELL0.IMUX.IMUX22.DELAY
CRCIN26inputCELL0.IMUX.IMUX21.DELAY
CRCIN27inputCELL0.IMUX.IMUX20.DELAY
CRCIN28inputCELL0.IMUX.IMUX25.DELAY
CRCIN29inputCELL0.IMUX.IMUX24.DELAY
CRCIN3inputCELL3.IMUX.IMUX14.DELAY
CRCIN30inputCELL0.IMUX.IMUX43.DELAY
CRCIN31inputCELL0.IMUX.IMUX42.DELAY
CRCIN4inputCELL3.IMUX.IMUX13.DELAY
CRCIN5inputCELL3.IMUX.IMUX12.DELAY
CRCIN6inputCELL3.IMUX.IMUX37.DELAY
CRCIN7inputCELL3.IMUX.IMUX36.DELAY
CRCIN8inputCELL2.IMUX.IMUX17.DELAY
CRCIN9inputCELL2.IMUX.IMUX16.DELAY
CRCOUT0outputCELL3.OUT6.TMIN
CRCOUT1outputCELL3.OUT4.TMIN
CRCOUT10outputCELL2.OUT22.TMIN
CRCOUT11outputCELL2.OUT12.TMIN
CRCOUT12outputCELL1.OUT17.TMIN
CRCOUT13outputCELL1.OUT16.TMIN
CRCOUT14outputCELL1.OUT23.TMIN
CRCOUT15outputCELL1.OUT13.TMIN
CRCOUT16outputCELL1.OUT5.TMIN
CRCOUT17outputCELL1.OUT1.TMIN
CRCOUT18outputCELL1.OUT22.TMIN
CRCOUT19outputCELL1.OUT12.TMIN
CRCOUT2outputCELL3.OUT18.TMIN
CRCOUT20outputCELL0.OUT21.TMIN
CRCOUT21outputCELL0.OUT15.TMIN
CRCOUT22outputCELL0.OUT7.TMIN
CRCOUT23outputCELL0.OUT3.TMIN
CRCOUT24outputCELL0.OUT20.TMIN
CRCOUT25outputCELL0.OUT14.TMIN
CRCOUT26outputCELL0.OUT23.TMIN
CRCOUT27outputCELL0.OUT13.TMIN
CRCOUT28outputCELL0.OUT5.TMIN
CRCOUT29outputCELL0.OUT1.TMIN
CRCOUT3outputCELL2.OUT21.TMIN
CRCOUT30outputCELL0.OUT22.TMIN
CRCOUT31outputCELL0.OUT4.TMIN
CRCOUT4outputCELL2.OUT6.TMIN
CRCOUT5outputCELL2.OUT20.TMIN
CRCOUT6outputCELL2.OUT14.TMIN
CRCOUT7outputCELL2.OUT23.TMIN
CRCOUT8outputCELL2.OUT13.TMIN
CRCOUT9outputCELL2.OUT1.TMIN
CRCRESETinputCELL2.IMUX.IMUX5.DELAY

Bel CRC32_1

virtex5 GTX bel CRC32_1
PinDirectionWires
CRCCLKinputCELL6.IMUX.CLK1
CRCDATAVALIDinputCELL8.IMUX.IMUX35.DELAY
CRCDATAWIDTH0inputCELL8.IMUX.IMUX11.DELAY
CRCDATAWIDTH1inputCELL8.IMUX.IMUX34.DELAY
CRCDATAWIDTH2inputCELL3.IMUX.IMUX21.DELAY
CRCIN0inputCELL7.IMUX.IMUX47.DELAY
CRCIN1inputCELL7.IMUX.IMUX46.DELAY
CRCIN10inputCELL6.IMUX.IMUX45.DELAY
CRCIN11inputCELL6.IMUX.IMUX44.DELAY
CRCIN12inputCELL6.IMUX.IMUX43.DELAY
CRCIN13inputCELL6.IMUX.IMUX42.DELAY
CRCIN14inputCELL6.IMUX.IMUX37.DELAY
CRCIN15inputCELL6.IMUX.IMUX36.DELAY
CRCIN16inputCELL5.IMUX.IMUX47.DELAY
CRCIN17inputCELL5.IMUX.IMUX46.DELAY
CRCIN18inputCELL5.IMUX.IMUX45.DELAY
CRCIN19inputCELL5.IMUX.IMUX44.DELAY
CRCIN2inputCELL7.IMUX.IMUX45.DELAY
CRCIN20inputCELL5.IMUX.IMUX43.DELAY
CRCIN21inputCELL5.IMUX.IMUX42.DELAY
CRCIN22inputCELL5.IMUX.IMUX37.DELAY
CRCIN23inputCELL5.IMUX.IMUX36.DELAY
CRCIN24inputCELL4.IMUX.IMUX47.DELAY
CRCIN25inputCELL4.IMUX.IMUX46.DELAY
CRCIN26inputCELL4.IMUX.IMUX45.DELAY
CRCIN27inputCELL4.IMUX.IMUX44.DELAY
CRCIN28inputCELL4.IMUX.IMUX43.DELAY
CRCIN29inputCELL4.IMUX.IMUX42.DELAY
CRCIN3inputCELL7.IMUX.IMUX44.DELAY
CRCIN30inputCELL4.IMUX.IMUX37.DELAY
CRCIN31inputCELL4.IMUX.IMUX36.DELAY
CRCIN4inputCELL7.IMUX.IMUX43.DELAY
CRCIN5inputCELL7.IMUX.IMUX42.DELAY
CRCIN6inputCELL7.IMUX.IMUX37.DELAY
CRCIN7inputCELL7.IMUX.IMUX36.DELAY
CRCIN8inputCELL6.IMUX.IMUX47.DELAY
CRCIN9inputCELL6.IMUX.IMUX46.DELAY
CRCOUT0outputCELL9.OUT11.TMIN
CRCOUT1outputCELL9.OUT3.TMIN
CRCOUT10outputCELL8.OUT15.TMIN
CRCOUT11outputCELL8.OUT11.TMIN
CRCOUT12outputCELL8.OUT6.TMIN
CRCOUT13outputCELL8.OUT2.TMIN
CRCOUT14outputCELL8.OUT16.TMIN
CRCOUT15outputCELL8.OUT10.TMIN
CRCOUT16outputCELL8.OUT23.TMIN
CRCOUT17outputCELL8.OUT9.TMIN
CRCOUT18outputCELL8.OUT5.TMIN
CRCOUT19outputCELL8.OUT0.TMIN
CRCOUT2outputCELL9.OUT14.TMIN
CRCOUT20outputCELL7.OUT21.TMIN
CRCOUT21outputCELL7.OUT17.TMIN
CRCOUT22outputCELL7.OUT3.TMIN
CRCOUT23outputCELL7.OUT12.TMIN
CRCOUT24outputCELL6.OUT15.TMIN
CRCOUT25outputCELL6.OUT14.TMIN
CRCOUT26outputCELL6.OUT12.TMIN
CRCOUT27outputCELL5.OUT21.TMIN
CRCOUT28outputCELL5.OUT7.TMIN
CRCOUT29outputCELL5.OUT5.TMIN
CRCOUT3outputCELL9.OUT13.TMIN
CRCOUT30outputCELL5.OUT22.TMIN
CRCOUT31outputCELL4.OUT21.TMIN
CRCOUT4outputCELL9.OUT4.TMIN
CRCOUT5outputCELL9.OUT0.TMIN
CRCOUT6outputCELL9.OUT18.TMIN
CRCOUT7outputCELL9.OUT12.TMIN
CRCOUT8outputCELL9.OUT8.TMIN
CRCOUT9outputCELL8.OUT17.TMIN
CRCRESETinputCELL8.IMUX.IMUX0.DELAY

Bel CRC32_2

virtex5 GTX bel CRC32_2
PinDirectionWires
CRCCLKinputCELL13.IMUX.CLK0
CRCDATAVALIDinputCELL11.IMUX.IMUX30.DELAY
CRCDATAWIDTH0inputCELL11.IMUX.IMUX24.DELAY
CRCDATAWIDTH1inputCELL11.IMUX.IMUX13.DELAY
CRCDATAWIDTH2inputCELL16.IMUX.IMUX8.DELAY
CRCIN0inputCELL12.IMUX.IMUX0.DELAY
CRCIN1inputCELL12.IMUX.IMUX1.DELAY
CRCIN10inputCELL13.IMUX.IMUX8.DELAY
CRCIN11inputCELL13.IMUX.IMUX9.DELAY
CRCIN12inputCELL13.IMUX.IMUX4.DELAY
CRCIN13inputCELL13.IMUX.IMUX5.DELAY
CRCIN14inputCELL13.IMUX.IMUX10.DELAY
CRCIN15inputCELL13.IMUX.IMUX11.DELAY
CRCIN16inputCELL14.IMUX.IMUX6.DELAY
CRCIN17inputCELL14.IMUX.IMUX7.DELAY
CRCIN18inputCELL14.IMUX.IMUX8.DELAY
CRCIN19inputCELL14.IMUX.IMUX9.DELAY
CRCIN2inputCELL12.IMUX.IMUX2.DELAY
CRCIN20inputCELL14.IMUX.IMUX4.DELAY
CRCIN21inputCELL14.IMUX.IMUX5.DELAY
CRCIN22inputCELL14.IMUX.IMUX10.DELAY
CRCIN23inputCELL14.IMUX.IMUX11.DELAY
CRCIN24inputCELL15.IMUX.IMUX6.DELAY
CRCIN25inputCELL15.IMUX.IMUX7.DELAY
CRCIN26inputCELL15.IMUX.IMUX8.DELAY
CRCIN27inputCELL15.IMUX.IMUX9.DELAY
CRCIN28inputCELL15.IMUX.IMUX4.DELAY
CRCIN29inputCELL15.IMUX.IMUX5.DELAY
CRCIN3inputCELL12.IMUX.IMUX9.DELAY
CRCIN30inputCELL15.IMUX.IMUX10.DELAY
CRCIN31inputCELL15.IMUX.IMUX11.DELAY
CRCIN4inputCELL12.IMUX.IMUX45.DELAY
CRCIN5inputCELL12.IMUX.IMUX35.DELAY
CRCIN6inputCELL12.IMUX.IMUX10.DELAY
CRCIN7inputCELL12.IMUX.IMUX11.DELAY
CRCIN8inputCELL13.IMUX.IMUX6.DELAY
CRCIN9inputCELL13.IMUX.IMUX7.DELAY
CRCOUT0outputCELL10.OUT4.TMIN
CRCOUT1outputCELL10.OUT23.TMIN
CRCOUT10outputCELL11.OUT4.TMIN
CRCOUT11outputCELL11.OUT22.TMIN
CRCOUT12outputCELL11.OUT5.TMIN
CRCOUT13outputCELL11.OUT13.TMIN
CRCOUT14outputCELL11.OUT19.TMIN
CRCOUT15outputCELL11.OUT23.TMIN
CRCOUT16outputCELL11.OUT10.TMIN
CRCOUT17outputCELL11.OUT16.TMIN
CRCOUT18outputCELL11.OUT3.TMIN
CRCOUT19outputCELL11.OUT7.TMIN
CRCOUT2outputCELL10.OUT16.TMIN
CRCOUT20outputCELL12.OUT8.TMIN
CRCOUT21outputCELL12.OUT18.TMIN
CRCOUT22outputCELL12.OUT4.TMIN
CRCOUT23outputCELL12.OUT17.TMIN
CRCOUT24outputCELL13.OUT18.TMIN
CRCOUT25outputCELL13.OUT19.TMIN
CRCOUT26outputCELL13.OUT17.TMIN
CRCOUT27outputCELL14.OUT18.TMIN
CRCOUT28outputCELL14.OUT4.TMIN
CRCOUT29outputCELL14.OUT6.TMIN
CRCOUT3outputCELL10.OUT2.TMIN
CRCOUT30outputCELL14.OUT17.TMIN
CRCOUT31outputCELL15.OUT18.TMIN
CRCOUT4outputCELL10.OUT6.TMIN
CRCOUT5outputCELL10.OUT7.TMIN
CRCOUT6outputCELL10.OUT11.TMIN
CRCOUT7outputCELL10.OUT15.TMIN
CRCOUT8outputCELL10.OUT21.TMIN
CRCOUT9outputCELL11.OUT12.TMIN
CRCRESETinputCELL11.IMUX.IMUX5.DELAY

Bel CRC32_3

virtex5 GTX bel CRC32_3
PinDirectionWires
CRCCLKinputCELL18.IMUX.CLK0
CRCDATAVALIDinputCELL16.IMUX.IMUX7.DELAY
CRCDATAWIDTH0inputCELL16.IMUX.IMUX6.DELAY
CRCDATAWIDTH1inputCELL16.IMUX.IMUX1.DELAY
CRCDATAWIDTH2inputCELL16.IMUX.IMUX8.DELAY
CRCIN0inputCELL16.IMUX.IMUX36.DELAY
CRCIN1inputCELL16.IMUX.IMUX37.DELAY
CRCIN10inputCELL17.IMUX.IMUX32.DELAY
CRCIN11inputCELL17.IMUX.IMUX33.DELAY
CRCIN12inputCELL17.IMUX.IMUX34.DELAY
CRCIN13inputCELL17.IMUX.IMUX35.DELAY
CRCIN14inputCELL17.IMUX.IMUX46.DELAY
CRCIN15inputCELL17.IMUX.IMUX47.DELAY
CRCIN16inputCELL18.IMUX.IMUX6.DELAY
CRCIN17inputCELL18.IMUX.IMUX7.DELAY
CRCIN18inputCELL18.IMUX.IMUX8.DELAY
CRCIN19inputCELL18.IMUX.IMUX21.DELAY
CRCIN2inputCELL16.IMUX.IMUX38.DELAY
CRCIN20inputCELL18.IMUX.IMUX10.DELAY
CRCIN21inputCELL18.IMUX.IMUX11.DELAY
CRCIN22inputCELL18.IMUX.IMUX40.DELAY
CRCIN23inputCELL18.IMUX.IMUX41.DELAY
CRCIN24inputCELL19.IMUX.IMUX24.DELAY
CRCIN25inputCELL19.IMUX.IMUX25.DELAY
CRCIN26inputCELL19.IMUX.IMUX26.DELAY
CRCIN27inputCELL19.IMUX.IMUX21.DELAY
CRCIN28inputCELL19.IMUX.IMUX10.DELAY
CRCIN29inputCELL19.IMUX.IMUX11.DELAY
CRCIN3inputCELL16.IMUX.IMUX39.DELAY
CRCIN30inputCELL19.IMUX.IMUX40.DELAY
CRCIN31inputCELL19.IMUX.IMUX41.DELAY
CRCIN4inputCELL16.IMUX.IMUX40.DELAY
CRCIN5inputCELL16.IMUX.IMUX35.DELAY
CRCIN6inputCELL16.IMUX.IMUX10.DELAY
CRCIN7inputCELL16.IMUX.IMUX11.DELAY
CRCIN8inputCELL17.IMUX.IMUX30.DELAY
CRCIN9inputCELL17.IMUX.IMUX31.DELAY
CRCOUT0outputCELL16.OUT13.TMIN
CRCOUT1outputCELL16.OUT3.TMIN
CRCOUT10outputCELL17.OUT15.TMIN
CRCOUT11outputCELL17.OUT17.TMIN
CRCOUT12outputCELL18.OUT12.TMIN
CRCOUT13outputCELL18.OUT9.TMIN
CRCOUT14outputCELL18.OUT10.TMIN
CRCOUT15outputCELL18.OUT6.TMIN
CRCOUT16outputCELL18.OUT3.TMIN
CRCOUT17outputCELL18.OUT7.TMIN
CRCOUT18outputCELL18.OUT17.TMIN
CRCOUT19outputCELL18.OUT21.TMIN
CRCOUT2outputCELL16.OUT15.TMIN
CRCOUT20outputCELL19.OUT12.TMIN
CRCOUT21outputCELL19.OUT4.TMIN
CRCOUT22outputCELL19.OUT1.TMIN
CRCOUT23outputCELL19.OUT5.TMIN
CRCOUT24outputCELL19.OUT19.TMIN
CRCOUT25outputCELL19.OUT20.TMIN
CRCOUT26outputCELL19.OUT10.TMIN
CRCOUT27outputCELL19.OUT6.TMIN
CRCOUT28outputCELL19.OUT3.TMIN
CRCOUT29outputCELL19.OUT7.TMIN
CRCOUT3outputCELL17.OUT8.TMIN
CRCOUT30outputCELL19.OUT11.TMIN
CRCOUT31outputCELL19.OUT21.TMIN
CRCOUT4outputCELL17.OUT1.TMIN
CRCOUT5outputCELL17.OUT13.TMIN
CRCOUT6outputCELL17.OUT19.TMIN
CRCOUT7outputCELL17.OUT14.TMIN
CRCOUT8outputCELL17.OUT20.TMIN
CRCOUT9outputCELL17.OUT6.TMIN
CRCRESETinputCELL17.IMUX.IMUX0.DELAY

Bel CRC64_0

virtex5 GTX bel CRC64_0
PinDirectionWires
CRCCLKinputCELL1.IMUX.CLK1
CRCDATAVALIDinputCELL3.IMUX.IMUX22.DELAY
CRCDATAWIDTH0inputCELL3.IMUX.IMUX40.DELAY
CRCDATAWIDTH1inputCELL3.IMUX.IMUX23.DELAY
CRCDATAWIDTH2inputCELL3.IMUX.IMUX21.DELAY
CRCIN0inputCELL7.IMUX.IMUX47.DELAY
CRCIN1inputCELL7.IMUX.IMUX46.DELAY
CRCIN10inputCELL6.IMUX.IMUX45.DELAY
CRCIN11inputCELL6.IMUX.IMUX44.DELAY
CRCIN12inputCELL6.IMUX.IMUX43.DELAY
CRCIN13inputCELL6.IMUX.IMUX42.DELAY
CRCIN14inputCELL6.IMUX.IMUX37.DELAY
CRCIN15inputCELL6.IMUX.IMUX36.DELAY
CRCIN16inputCELL5.IMUX.IMUX47.DELAY
CRCIN17inputCELL5.IMUX.IMUX46.DELAY
CRCIN18inputCELL5.IMUX.IMUX45.DELAY
CRCIN19inputCELL5.IMUX.IMUX44.DELAY
CRCIN2inputCELL7.IMUX.IMUX45.DELAY
CRCIN20inputCELL5.IMUX.IMUX43.DELAY
CRCIN21inputCELL5.IMUX.IMUX42.DELAY
CRCIN22inputCELL5.IMUX.IMUX37.DELAY
CRCIN23inputCELL5.IMUX.IMUX36.DELAY
CRCIN24inputCELL4.IMUX.IMUX47.DELAY
CRCIN25inputCELL4.IMUX.IMUX46.DELAY
CRCIN26inputCELL4.IMUX.IMUX45.DELAY
CRCIN27inputCELL4.IMUX.IMUX44.DELAY
CRCIN28inputCELL4.IMUX.IMUX43.DELAY
CRCIN29inputCELL4.IMUX.IMUX42.DELAY
CRCIN3inputCELL7.IMUX.IMUX44.DELAY
CRCIN30inputCELL4.IMUX.IMUX37.DELAY
CRCIN31inputCELL4.IMUX.IMUX36.DELAY
CRCIN32inputCELL3.IMUX.IMUX17.DELAY
CRCIN33inputCELL3.IMUX.IMUX16.DELAY
CRCIN34inputCELL3.IMUX.IMUX15.DELAY
CRCIN35inputCELL3.IMUX.IMUX14.DELAY
CRCIN36inputCELL3.IMUX.IMUX13.DELAY
CRCIN37inputCELL3.IMUX.IMUX12.DELAY
CRCIN38inputCELL3.IMUX.IMUX37.DELAY
CRCIN39inputCELL3.IMUX.IMUX36.DELAY
CRCIN4inputCELL7.IMUX.IMUX43.DELAY
CRCIN40inputCELL2.IMUX.IMUX17.DELAY
CRCIN41inputCELL2.IMUX.IMUX16.DELAY
CRCIN42inputCELL2.IMUX.IMUX15.DELAY
CRCIN43inputCELL2.IMUX.IMUX14.DELAY
CRCIN44inputCELL2.IMUX.IMUX13.DELAY
CRCIN45inputCELL2.IMUX.IMUX12.DELAY
CRCIN46inputCELL2.IMUX.IMUX37.DELAY
CRCIN47inputCELL2.IMUX.IMUX36.DELAY
CRCIN48inputCELL1.IMUX.IMUX23.DELAY
CRCIN49inputCELL1.IMUX.IMUX22.DELAY
CRCIN5inputCELL7.IMUX.IMUX42.DELAY
CRCIN50inputCELL1.IMUX.IMUX45.DELAY
CRCIN51inputCELL1.IMUX.IMUX44.DELAY
CRCIN52inputCELL1.IMUX.IMUX43.DELAY
CRCIN53inputCELL1.IMUX.IMUX42.DELAY
CRCIN54inputCELL1.IMUX.IMUX19.DELAY
CRCIN55inputCELL1.IMUX.IMUX18.DELAY
CRCIN56inputCELL0.IMUX.IMUX23.DELAY
CRCIN57inputCELL0.IMUX.IMUX22.DELAY
CRCIN58inputCELL0.IMUX.IMUX21.DELAY
CRCIN59inputCELL0.IMUX.IMUX20.DELAY
CRCIN6inputCELL7.IMUX.IMUX37.DELAY
CRCIN60inputCELL0.IMUX.IMUX25.DELAY
CRCIN61inputCELL0.IMUX.IMUX24.DELAY
CRCIN62inputCELL0.IMUX.IMUX43.DELAY
CRCIN63inputCELL0.IMUX.IMUX42.DELAY
CRCIN7inputCELL7.IMUX.IMUX36.DELAY
CRCIN8inputCELL6.IMUX.IMUX47.DELAY
CRCIN9inputCELL6.IMUX.IMUX46.DELAY
CRCOUT0outputCELL3.OUT6.TMIN
CRCOUT1outputCELL3.OUT4.TMIN
CRCOUT10outputCELL2.OUT22.TMIN
CRCOUT11outputCELL2.OUT12.TMIN
CRCOUT12outputCELL1.OUT17.TMIN
CRCOUT13outputCELL1.OUT16.TMIN
CRCOUT14outputCELL1.OUT23.TMIN
CRCOUT15outputCELL1.OUT13.TMIN
CRCOUT16outputCELL1.OUT5.TMIN
CRCOUT17outputCELL1.OUT1.TMIN
CRCOUT18outputCELL1.OUT22.TMIN
CRCOUT19outputCELL1.OUT12.TMIN
CRCOUT2outputCELL3.OUT18.TMIN
CRCOUT20outputCELL0.OUT21.TMIN
CRCOUT21outputCELL0.OUT15.TMIN
CRCOUT22outputCELL0.OUT7.TMIN
CRCOUT23outputCELL0.OUT3.TMIN
CRCOUT24outputCELL0.OUT20.TMIN
CRCOUT25outputCELL0.OUT14.TMIN
CRCOUT26outputCELL0.OUT23.TMIN
CRCOUT27outputCELL0.OUT13.TMIN
CRCOUT28outputCELL0.OUT5.TMIN
CRCOUT29outputCELL0.OUT1.TMIN
CRCOUT3outputCELL2.OUT21.TMIN
CRCOUT30outputCELL0.OUT22.TMIN
CRCOUT31outputCELL0.OUT4.TMIN
CRCOUT4outputCELL2.OUT6.TMIN
CRCOUT5outputCELL2.OUT20.TMIN
CRCOUT6outputCELL2.OUT14.TMIN
CRCOUT7outputCELL2.OUT23.TMIN
CRCOUT8outputCELL2.OUT13.TMIN
CRCOUT9outputCELL2.OUT1.TMIN
CRCRESETinputCELL2.IMUX.IMUX5.DELAY

Bel CRC64_1

virtex5 GTX bel CRC64_1
PinDirectionWires
CRCCLKinputCELL18.IMUX.CLK0
CRCDATAVALIDinputCELL16.IMUX.IMUX7.DELAY
CRCDATAWIDTH0inputCELL16.IMUX.IMUX6.DELAY
CRCDATAWIDTH1inputCELL16.IMUX.IMUX1.DELAY
CRCDATAWIDTH2inputCELL16.IMUX.IMUX8.DELAY
CRCIN0inputCELL12.IMUX.IMUX0.DELAY
CRCIN1inputCELL12.IMUX.IMUX1.DELAY
CRCIN10inputCELL13.IMUX.IMUX8.DELAY
CRCIN11inputCELL13.IMUX.IMUX9.DELAY
CRCIN12inputCELL13.IMUX.IMUX4.DELAY
CRCIN13inputCELL13.IMUX.IMUX5.DELAY
CRCIN14inputCELL13.IMUX.IMUX10.DELAY
CRCIN15inputCELL13.IMUX.IMUX11.DELAY
CRCIN16inputCELL14.IMUX.IMUX6.DELAY
CRCIN17inputCELL14.IMUX.IMUX7.DELAY
CRCIN18inputCELL14.IMUX.IMUX8.DELAY
CRCIN19inputCELL14.IMUX.IMUX9.DELAY
CRCIN2inputCELL12.IMUX.IMUX2.DELAY
CRCIN20inputCELL14.IMUX.IMUX4.DELAY
CRCIN21inputCELL14.IMUX.IMUX5.DELAY
CRCIN22inputCELL14.IMUX.IMUX10.DELAY
CRCIN23inputCELL14.IMUX.IMUX11.DELAY
CRCIN24inputCELL15.IMUX.IMUX6.DELAY
CRCIN25inputCELL15.IMUX.IMUX7.DELAY
CRCIN26inputCELL15.IMUX.IMUX8.DELAY
CRCIN27inputCELL15.IMUX.IMUX9.DELAY
CRCIN28inputCELL15.IMUX.IMUX4.DELAY
CRCIN29inputCELL15.IMUX.IMUX5.DELAY
CRCIN3inputCELL12.IMUX.IMUX9.DELAY
CRCIN30inputCELL15.IMUX.IMUX10.DELAY
CRCIN31inputCELL15.IMUX.IMUX11.DELAY
CRCIN32inputCELL16.IMUX.IMUX36.DELAY
CRCIN33inputCELL16.IMUX.IMUX37.DELAY
CRCIN34inputCELL16.IMUX.IMUX38.DELAY
CRCIN35inputCELL16.IMUX.IMUX39.DELAY
CRCIN36inputCELL16.IMUX.IMUX40.DELAY
CRCIN37inputCELL16.IMUX.IMUX35.DELAY
CRCIN38inputCELL16.IMUX.IMUX10.DELAY
CRCIN39inputCELL16.IMUX.IMUX11.DELAY
CRCIN4inputCELL12.IMUX.IMUX45.DELAY
CRCIN40inputCELL17.IMUX.IMUX30.DELAY
CRCIN41inputCELL17.IMUX.IMUX31.DELAY
CRCIN42inputCELL17.IMUX.IMUX32.DELAY
CRCIN43inputCELL17.IMUX.IMUX33.DELAY
CRCIN44inputCELL17.IMUX.IMUX34.DELAY
CRCIN45inputCELL17.IMUX.IMUX35.DELAY
CRCIN46inputCELL17.IMUX.IMUX46.DELAY
CRCIN47inputCELL17.IMUX.IMUX47.DELAY
CRCIN48inputCELL18.IMUX.IMUX6.DELAY
CRCIN49inputCELL18.IMUX.IMUX7.DELAY
CRCIN5inputCELL12.IMUX.IMUX35.DELAY
CRCIN50inputCELL18.IMUX.IMUX8.DELAY
CRCIN51inputCELL18.IMUX.IMUX21.DELAY
CRCIN52inputCELL18.IMUX.IMUX10.DELAY
CRCIN53inputCELL18.IMUX.IMUX11.DELAY
CRCIN54inputCELL18.IMUX.IMUX40.DELAY
CRCIN55inputCELL18.IMUX.IMUX41.DELAY
CRCIN56inputCELL19.IMUX.IMUX24.DELAY
CRCIN57inputCELL19.IMUX.IMUX25.DELAY
CRCIN58inputCELL19.IMUX.IMUX26.DELAY
CRCIN59inputCELL19.IMUX.IMUX21.DELAY
CRCIN6inputCELL12.IMUX.IMUX10.DELAY
CRCIN60inputCELL19.IMUX.IMUX10.DELAY
CRCIN61inputCELL19.IMUX.IMUX11.DELAY
CRCIN62inputCELL19.IMUX.IMUX40.DELAY
CRCIN63inputCELL19.IMUX.IMUX41.DELAY
CRCIN7inputCELL12.IMUX.IMUX11.DELAY
CRCIN8inputCELL13.IMUX.IMUX6.DELAY
CRCIN9inputCELL13.IMUX.IMUX7.DELAY
CRCOUT0outputCELL16.OUT13.TMIN
CRCOUT1outputCELL16.OUT3.TMIN
CRCOUT10outputCELL17.OUT15.TMIN
CRCOUT11outputCELL17.OUT17.TMIN
CRCOUT12outputCELL18.OUT12.TMIN
CRCOUT13outputCELL18.OUT9.TMIN
CRCOUT14outputCELL18.OUT10.TMIN
CRCOUT15outputCELL18.OUT6.TMIN
CRCOUT16outputCELL18.OUT3.TMIN
CRCOUT17outputCELL18.OUT7.TMIN
CRCOUT18outputCELL18.OUT17.TMIN
CRCOUT19outputCELL18.OUT21.TMIN
CRCOUT2outputCELL16.OUT15.TMIN
CRCOUT20outputCELL19.OUT12.TMIN
CRCOUT21outputCELL19.OUT4.TMIN
CRCOUT22outputCELL19.OUT1.TMIN
CRCOUT23outputCELL19.OUT5.TMIN
CRCOUT24outputCELL19.OUT19.TMIN
CRCOUT25outputCELL19.OUT20.TMIN
CRCOUT26outputCELL19.OUT10.TMIN
CRCOUT27outputCELL19.OUT6.TMIN
CRCOUT28outputCELL19.OUT3.TMIN
CRCOUT29outputCELL19.OUT7.TMIN
CRCOUT3outputCELL17.OUT8.TMIN
CRCOUT30outputCELL19.OUT11.TMIN
CRCOUT31outputCELL19.OUT21.TMIN
CRCOUT4outputCELL17.OUT1.TMIN
CRCOUT5outputCELL17.OUT13.TMIN
CRCOUT6outputCELL17.OUT19.TMIN
CRCOUT7outputCELL17.OUT14.TMIN
CRCOUT8outputCELL17.OUT20.TMIN
CRCOUT9outputCELL17.OUT6.TMIN
CRCRESETinputCELL17.IMUX.IMUX0.DELAY

Bel IPAD_CLKP0

virtex5 GTX bel IPAD_CLKP0
PinDirectionWires

Bel IPAD_CLKN0

virtex5 GTX bel IPAD_CLKN0
PinDirectionWires

Bel IPAD_RXP0

virtex5 GTX bel IPAD_RXP0
PinDirectionWires

Bel IPAD_RXN0

virtex5 GTX bel IPAD_RXN0
PinDirectionWires

Bel IPAD_RXP1

virtex5 GTX bel IPAD_RXP1
PinDirectionWires

Bel IPAD_RXN1

virtex5 GTX bel IPAD_RXN1
PinDirectionWires

Bel OPAD_TXP0

virtex5 GTX bel OPAD_TXP0
PinDirectionWires

Bel OPAD_TXN0

virtex5 GTX bel OPAD_TXN0
PinDirectionWires

Bel OPAD_TXP1

virtex5 GTX bel OPAD_TXP1
PinDirectionWires

Bel OPAD_TXN1

virtex5 GTX bel OPAD_TXN1
PinDirectionWires

Bel wires

virtex5 GTX bel wires
WirePins
CELL0.IMUX.IMUX0.DELAYGTX_DUAL.TXDATA116
CELL0.IMUX.IMUX4.DELAYGTX_DUAL.TXELECIDLE1
CELL0.IMUX.IMUX6.DELAYGTX_DUAL.TXDIFFCTRL12
CELL0.IMUX.IMUX7.DELAYGTX_DUAL.TXDIFFCTRL11
CELL0.IMUX.IMUX8.DELAYGTX_DUAL.TXDIFFCTRL10
CELL0.IMUX.IMUX9.DELAYGTX_DUAL.TXCHARDISPVAL12
CELL0.IMUX.IMUX11.DELAYGTX_DUAL.GTXTEST11
CELL0.IMUX.IMUX12.DELAYGTX_DUAL.GTXTEST10
CELL0.IMUX.IMUX13.DELAYGTX_DUAL.GTXTEST1
CELL0.IMUX.IMUX14.DELAYGTX_DUAL.GTXTEST12
CELL0.IMUX.IMUX15.DELAYGTX_DUAL.TXBUFDIFFCTRL12
CELL0.IMUX.IMUX16.DELAYGTX_DUAL.TXBUFDIFFCTRL11
CELL0.IMUX.IMUX17.DELAYGTX_DUAL.TXBUFDIFFCTRL10
CELL0.IMUX.IMUX20.DELAYCRC32_0.CRCIN27, CRC64_0.CRCIN59
CELL0.IMUX.IMUX21.DELAYCRC32_0.CRCIN26, CRC64_0.CRCIN58
CELL0.IMUX.IMUX22.DELAYCRC32_0.CRCIN25, CRC64_0.CRCIN57
CELL0.IMUX.IMUX23.DELAYCRC32_0.CRCIN24, CRC64_0.CRCIN56
CELL0.IMUX.IMUX24.DELAYCRC32_0.CRCIN29, CRC64_0.CRCIN61
CELL0.IMUX.IMUX25.DELAYCRC32_0.CRCIN28, CRC64_0.CRCIN60
CELL0.IMUX.IMUX27.DELAYGTX_DUAL.TXDATA118
CELL0.IMUX.IMUX29.DELAYGTX_DUAL.TXDATA119
CELL0.IMUX.IMUX30.DELAYGTX_DUAL.SCANINPCS1
CELL0.IMUX.IMUX31.DELAYGTX_DUAL.TXDATA117
CELL0.IMUX.IMUX32.DELAYGTX_DUAL.TXDATA10
CELL0.IMUX.IMUX33.DELAYGTX_DUAL.TXDATA11
CELL0.IMUX.IMUX34.DELAYGTX_DUAL.TXDATA12
CELL0.IMUX.IMUX35.DELAYGTX_DUAL.TXDATA13
CELL0.IMUX.IMUX36.DELAYGTX_DUAL.SCANMODE
CELL0.IMUX.IMUX37.DELAYGTX_DUAL.TXSEQUENCE16
CELL0.IMUX.IMUX38.DELAYGTX_DUAL.TXCHARDISPMODE12
CELL0.IMUX.IMUX41.DELAYGTX_DUAL.TXSEQUENCE12
CELL0.IMUX.IMUX42.DELAYCRC32_0.CRCIN31, CRC64_0.CRCIN63
CELL0.IMUX.IMUX43.DELAYCRC32_0.CRCIN30, CRC64_0.CRCIN62
CELL0.IMUX.IMUX44.DELAYGTX_DUAL.TXSEQUENCE15
CELL0.IMUX.IMUX45.DELAYGTX_DUAL.TXSEQUENCE14
CELL0.IMUX.IMUX46.DELAYGTX_DUAL.TXSEQUENCE13
CELL0.IMUX.IMUX47.DELAYGTX_DUAL.TXDETECTRX1
CELL0.OUT0.TMINGTX_DUAL.TXGEARBOXREADY1
CELL0.OUT1.TMINCRC32_0.CRCOUT29, CRC64_0.CRCOUT29
CELL0.OUT2.TMINGTX_DUAL.RXSTARTOFSEQ1
CELL0.OUT3.TMINCRC32_0.CRCOUT23, CRC64_0.CRCOUT23
CELL0.OUT4.TMINCRC32_0.CRCOUT31, CRC64_0.CRCOUT31
CELL0.OUT5.TMINCRC32_0.CRCOUT28, CRC64_0.CRCOUT28
CELL0.OUT6.TMINGTX_DUAL.RXHEADER11
CELL0.OUT7.TMINCRC32_0.CRCOUT22, CRC64_0.CRCOUT22
CELL0.OUT11.TMINGTX_DUAL.RXHEADERVALID1
CELL0.OUT12.TMINGTX_DUAL.RXDATAVALID1
CELL0.OUT13.TMINCRC32_0.CRCOUT27, CRC64_0.CRCOUT27
CELL0.OUT14.TMINCRC32_0.CRCOUT25, CRC64_0.CRCOUT25
CELL0.OUT15.TMINCRC32_0.CRCOUT21, CRC64_0.CRCOUT21
CELL0.OUT16.TMINGTX_DUAL.RXHEADER12
CELL0.OUT17.TMINGTX_DUAL.RXHEADER10
CELL0.OUT20.TMINCRC32_0.CRCOUT24, CRC64_0.CRCOUT24
CELL0.OUT21.TMINCRC32_0.CRCOUT20, CRC64_0.CRCOUT20
CELL0.OUT22.TMINCRC32_0.CRCOUT30, CRC64_0.CRCOUT30
CELL0.OUT23.TMINCRC32_0.CRCOUT26, CRC64_0.CRCOUT26
CELL1.IMUX.CLK1CRC32_0.CRCCLK, CRC64_0.CRCCLK
CELL1.IMUX.IMUX0.DELAYGTX_DUAL.TXCOMTYPE1
CELL1.IMUX.IMUX1.DELAYGTX_DUAL.TXCHARISK10
CELL1.IMUX.IMUX3.DELAYGTX_DUAL.TXSEQUENCE11
CELL1.IMUX.IMUX6.DELAYGTX_DUAL.TXDATA120
CELL1.IMUX.IMUX8.DELAYGTX_DUAL.TXCHARDISPMODE10
CELL1.IMUX.IMUX10.DELAYGTX_DUAL.TXENPRBSTST11
CELL1.IMUX.IMUX11.DELAYGTX_DUAL.TXENPRBSTST10
CELL1.IMUX.IMUX12.DELAYGTX_DUAL.TXBYPASS8B10B10
CELL1.IMUX.IMUX13.DELAYGTX_DUAL.TXCHARISK12
CELL1.IMUX.IMUX18.DELAYCRC32_0.CRCIN23, CRC64_0.CRCIN55
CELL1.IMUX.IMUX19.DELAYCRC32_0.CRCIN22, CRC64_0.CRCIN54
CELL1.IMUX.IMUX20.DELAYGTX_DUAL.TXDATA121
CELL1.IMUX.IMUX21.DELAYGTX_DUAL.TXCHARDISPVAL10
CELL1.IMUX.IMUX22.DELAYCRC32_0.CRCIN17, CRC64_0.CRCIN49
CELL1.IMUX.IMUX23.DELAYCRC32_0.CRCIN16, CRC64_0.CRCIN48
CELL1.IMUX.IMUX24.DELAYGTX_DUAL.TXPREEMPHASIS12
CELL1.IMUX.IMUX25.DELAYGTX_DUAL.TXPREEMPHASIS11
CELL1.IMUX.IMUX26.DELAYGTX_DUAL.TXPREEMPHASIS10
CELL1.IMUX.IMUX28.DELAYGTX_DUAL.TXDATA123
CELL1.IMUX.IMUX32.DELAYGTX_DUAL.TXDATA14
CELL1.IMUX.IMUX33.DELAYGTX_DUAL.TXDATA15
CELL1.IMUX.IMUX34.DELAYGTX_DUAL.TXDATA16
CELL1.IMUX.IMUX35.DELAYGTX_DUAL.TXDATA17
CELL1.IMUX.IMUX37.DELAYGTX_DUAL.TXCOMSTART1
CELL1.IMUX.IMUX39.DELAYGTX_DUAL.TXDATA122
CELL1.IMUX.IMUX42.DELAYCRC32_0.CRCIN21, CRC64_0.CRCIN53
CELL1.IMUX.IMUX43.DELAYCRC32_0.CRCIN20, CRC64_0.CRCIN52
CELL1.IMUX.IMUX44.DELAYCRC32_0.CRCIN19, CRC64_0.CRCIN51
CELL1.IMUX.IMUX45.DELAYCRC32_0.CRCIN18, CRC64_0.CRCIN50
CELL1.IMUX.IMUX46.DELAYGTX_DUAL.TXSEQUENCE10
CELL1.IMUX.IMUX47.DELAYGTX_DUAL.TSTPWRDNOVRD1
CELL1.OUT1.TMINCRC32_0.CRCOUT17, CRC64_0.CRCOUT17
CELL1.OUT2.TMINGTX_DUAL.TXBUFSTATUS10
CELL1.OUT4.TMINGTX_DUAL.RXDATA131
CELL1.OUT5.TMINCRC32_0.CRCOUT16, CRC64_0.CRCOUT16
CELL1.OUT6.TMINGTX_DUAL.RXDATA128
CELL1.OUT7.TMINGTX_DUAL.TXKERR10
CELL1.OUT9.TMINGTX_DUAL.RXDATA130
CELL1.OUT10.TMINGTX_DUAL.TXBUFSTATUS11
CELL1.OUT11.TMINGTX_DUAL.TXRUNDISP10
CELL1.OUT12.TMINCRC32_0.CRCOUT19, CRC64_0.CRCOUT19
CELL1.OUT13.TMINCRC32_0.CRCOUT15, CRC64_0.CRCOUT15
CELL1.OUT14.TMINGTX_DUAL.TXKERR12
CELL1.OUT15.TMINGTX_DUAL.RXDISPERR13
CELL1.OUT16.TMINCRC32_0.CRCOUT13, CRC64_0.CRCOUT13
CELL1.OUT17.TMINCRC32_0.CRCOUT12, CRC64_0.CRCOUT12
CELL1.OUT18.TMINGTX_DUAL.TXRUNDISP12
CELL1.OUT20.TMINGTX_DUAL.RXDATA129
CELL1.OUT21.TMINGTX_DUAL.RXCHARISK13
CELL1.OUT22.TMINCRC32_0.CRCOUT18, CRC64_0.CRCOUT18
CELL1.OUT23.TMINCRC32_0.CRCOUT14, CRC64_0.CRCOUT14
CELL2.IMUX.IMUX2.DELAYGTX_DUAL.TXPOLARITY1
CELL2.IMUX.IMUX5.DELAYCRC32_0.CRCRESET, CRC64_0.CRCRESET
CELL2.IMUX.IMUX10.DELAYGTX_DUAL.TXPREEMPHASIS13
CELL2.IMUX.IMUX12.DELAYCRC32_0.CRCIN13, CRC64_0.CRCIN45
CELL2.IMUX.IMUX13.DELAYCRC32_0.CRCIN12, CRC64_0.CRCIN44
CELL2.IMUX.IMUX14.DELAYCRC32_0.CRCIN11, CRC64_0.CRCIN43
CELL2.IMUX.IMUX15.DELAYCRC32_0.CRCIN10, CRC64_0.CRCIN42
CELL2.IMUX.IMUX16.DELAYCRC32_0.CRCIN9, CRC64_0.CRCIN41
CELL2.IMUX.IMUX17.DELAYCRC32_0.CRCIN8, CRC64_0.CRCIN40
CELL2.IMUX.IMUX20.DELAYGTX_DUAL.TXCHARDISPMODE11
CELL2.IMUX.IMUX21.DELAYGTX_DUAL.TXCHARDISPVAL11
CELL2.IMUX.IMUX24.DELAYGTX_DUAL.TXBYPASS8B10B11
CELL2.IMUX.IMUX25.DELAYGTX_DUAL.TXCHARISK11
CELL2.IMUX.IMUX27.DELAYGTX_DUAL.TXDATA127
CELL2.IMUX.IMUX28.DELAYGTX_DUAL.TXCHARDISPVAL13
CELL2.IMUX.IMUX30.DELAYGTX_DUAL.TXDATA124
CELL2.IMUX.IMUX31.DELAYGTX_DUAL.TXDATA125
CELL2.IMUX.IMUX32.DELAYGTX_DUAL.TXDATA18
CELL2.IMUX.IMUX33.DELAYGTX_DUAL.TXDATA19
CELL2.IMUX.IMUX34.DELAYGTX_DUAL.TXDATA110
CELL2.IMUX.IMUX35.DELAYGTX_DUAL.TXDATA111
CELL2.IMUX.IMUX36.DELAYCRC32_0.CRCIN15, CRC64_0.CRCIN47
CELL2.IMUX.IMUX37.DELAYCRC32_0.CRCIN14, CRC64_0.CRCIN46
CELL2.IMUX.IMUX38.DELAYGTX_DUAL.TXDATA126
CELL2.IMUX.IMUX39.DELAYGTX_DUAL.TXCHARISK13
CELL2.IMUX.IMUX40.DELAYGTX_DUAL.TXCHARDISPMODE13
CELL2.IMUX.IMUX42.DELAYGTX_DUAL.TXPOWERDOWN11
CELL2.IMUX.IMUX43.DELAYGTX_DUAL.TXPOWERDOWN10
CELL2.OUT1.TMINCRC32_0.CRCOUT9, CRC64_0.CRCOUT9
CELL2.OUT2.TMINGTX_DUAL.RXELECIDLE1
CELL2.OUT3.TMINGTX_DUAL.RXCHARISCOMMA13
CELL2.OUT4.TMINGTX_DUAL.RXNOTINTABLE13
CELL2.OUT5.TMINGTX_DUAL.TXRUNDISP11
CELL2.OUT6.TMINCRC32_0.CRCOUT4, CRC64_0.CRCOUT4
CELL2.OUT7.TMINGTX_DUAL.RXDATA125
CELL2.OUT10.TMINGTX_DUAL.TXKERR13
CELL2.OUT11.TMINGTX_DUAL.RXDATA124
CELL2.OUT12.TMINCRC32_0.CRCOUT11, CRC64_0.CRCOUT11
CELL2.OUT13.TMINCRC32_0.CRCOUT8, CRC64_0.CRCOUT8
CELL2.OUT14.TMINCRC32_0.CRCOUT6, CRC64_0.CRCOUT6
CELL2.OUT15.TMINGTX_DUAL.TXKERR11
CELL2.OUT16.TMINGTX_DUAL.RXDATA126
CELL2.OUT17.TMINGTX_DUAL.RXDISPERR12
CELL2.OUT18.TMINGTX_DUAL.RXRUNDISP13
CELL2.OUT19.TMINGTX_DUAL.RXDATA127
CELL2.OUT20.TMINCRC32_0.CRCOUT5, CRC64_0.CRCOUT5
CELL2.OUT21.TMINCRC32_0.CRCOUT3, CRC64_0.CRCOUT3
CELL2.OUT22.TMINCRC32_0.CRCOUT10, CRC64_0.CRCOUT10
CELL2.OUT23.TMINCRC32_0.CRCOUT7, CRC64_0.CRCOUT7
CELL3.IMUX.IMUX0.DELAYGTX_DUAL.TXRESET1
CELL3.IMUX.IMUX1.DELAYGTX_DUAL.TXINHIBIT1
CELL3.IMUX.IMUX4.DELAYGTX_DUAL.TXDATAWIDTH10
CELL3.IMUX.IMUX5.DELAYGTX_DUAL.TXDATAWIDTH11
CELL3.IMUX.IMUX7.DELAYGTX_DUAL.TXHEADER12
CELL3.IMUX.IMUX8.DELAYGTX_DUAL.TXSTARTSEQ1
CELL3.IMUX.IMUX9.DELAYGTX_DUAL.TXHEADER10
CELL3.IMUX.IMUX12.DELAYCRC32_0.CRCIN5, CRC64_0.CRCIN37
CELL3.IMUX.IMUX13.DELAYCRC32_0.CRCIN4, CRC64_0.CRCIN36
CELL3.IMUX.IMUX14.DELAYCRC32_0.CRCIN3, CRC64_0.CRCIN35
CELL3.IMUX.IMUX15.DELAYCRC32_0.CRCIN2, CRC64_0.CRCIN34
CELL3.IMUX.IMUX16.DELAYCRC32_0.CRCIN1, CRC64_0.CRCIN33
CELL3.IMUX.IMUX17.DELAYCRC32_0.CRCIN0, CRC64_0.CRCIN32
CELL3.IMUX.IMUX20.DELAYGTX_DUAL.TXHEADER11
CELL3.IMUX.IMUX21.DELAYCRC32_0.CRCDATAWIDTH2, CRC32_1.CRCDATAWIDTH2, CRC64_0.CRCDATAWIDTH2
CELL3.IMUX.IMUX22.DELAYCRC32_0.CRCDATAVALID, CRC64_0.CRCDATAVALID
CELL3.IMUX.IMUX23.DELAYCRC32_0.CRCDATAWIDTH1, CRC64_0.CRCDATAWIDTH1
CELL3.IMUX.IMUX30.DELAYGTX_DUAL.TXDATA128
CELL3.IMUX.IMUX31.DELAYGTX_DUAL.TXDATA129
CELL3.IMUX.IMUX32.DELAYGTX_DUAL.TXDATA112
CELL3.IMUX.IMUX33.DELAYGTX_DUAL.TXDATA113
CELL3.IMUX.IMUX34.DELAYGTX_DUAL.TXDATA114
CELL3.IMUX.IMUX35.DELAYGTX_DUAL.TXDATA115
CELL3.IMUX.IMUX36.DELAYCRC32_0.CRCIN7, CRC64_0.CRCIN39
CELL3.IMUX.IMUX37.DELAYCRC32_0.CRCIN6, CRC64_0.CRCIN38
CELL3.IMUX.IMUX38.DELAYGTX_DUAL.TXDATA130
CELL3.IMUX.IMUX39.DELAYGTX_DUAL.TXDATA131
CELL3.IMUX.IMUX40.DELAYCRC32_0.CRCDATAWIDTH0, CRC64_0.CRCDATAWIDTH0
CELL3.IMUX.IMUX47.DELAYGTX_DUAL.TXENC8B10BUSE1
CELL3.OUT0.TMINGTX_DUAL.RXSTATUS11
CELL3.OUT2.TMINGTX_DUAL.RXCLKCORCNT10
CELL3.OUT4.TMINCRC32_0.CRCOUT1, CRC64_0.CRCOUT1
CELL3.OUT5.TMINGTX_DUAL.RXDATA122
CELL3.OUT6.TMINCRC32_0.CRCOUT0, CRC64_0.CRCOUT0
CELL3.OUT7.TMINGTX_DUAL.RXCHARISCOMMA12
CELL3.OUT8.TMINGTX_DUAL.RXSTATUS12
CELL3.OUT9.TMINGTX_DUAL.RXCLKCORCNT12
CELL3.OUT10.TMINGTX_DUAL.RXCLKCORCNT11
CELL3.OUT11.TMINGTX_DUAL.RXPRBSERR1
CELL3.OUT12.TMINGTX_DUAL.RXCHARISK12
CELL3.OUT14.TMINGTX_DUAL.RXDATA120
CELL3.OUT16.TMINGTX_DUAL.RXDATA119
CELL3.OUT17.TMINGTX_DUAL.RXNOTINTABLE12
CELL3.OUT18.TMINCRC32_0.CRCOUT2, CRC64_0.CRCOUT2
CELL3.OUT19.TMINGTX_DUAL.RXSTATUS10
CELL3.OUT20.TMINGTX_DUAL.RXRUNDISP12
CELL3.OUT21.TMINGTX_DUAL.TXRUNDISP13
CELL3.OUT22.TMINGTX_DUAL.RXDATA123
CELL3.OUT23.TMINGTX_DUAL.RXDATA121
CELL4.IMUX.IMUX0.DELAYGTX_DUAL.RXPOLARITY1
CELL4.IMUX.IMUX1.DELAYGTX_DUAL.RXENPCOMMAALIGN1
CELL4.IMUX.IMUX2.DELAYGTX_DUAL.RXENMCOMMAALIGN1
CELL4.IMUX.IMUX3.DELAYGTX_DUAL.RXSLIDE1
CELL4.IMUX.IMUX5.DELAYGTX_DUAL.RXENEQB1
CELL4.IMUX.IMUX10.DELAYGTX_DUAL.RXDATAWIDTH10
CELL4.IMUX.IMUX14.DELAYGTX_DUAL.TXBYPASS8B10B13
CELL4.IMUX.IMUX15.DELAYGTX_DUAL.RXDATAWIDTH11
CELL4.IMUX.IMUX17.DELAYGTX_DUAL.RXCOMMADETUSE1
CELL4.IMUX.IMUX20.DELAYGTX_DUAL.TXBYPASS8B10B12
CELL4.IMUX.IMUX22.DELAYGTX_DUAL.RXGEARBOXSLIP1
CELL4.IMUX.IMUX24.DELAYGTX_DUAL.RXENPRBSTST11
CELL4.IMUX.IMUX25.DELAYGTX_DUAL.RXENPRBSTST10
CELL4.IMUX.IMUX27.DELAYGTX_DUAL.DFECLKDLYADJ13
CELL4.IMUX.IMUX29.DELAYGTX_DUAL.DFECLKDLYADJ11
CELL4.IMUX.IMUX31.DELAYGTX_DUAL.DFECLKDLYADJ15
CELL4.IMUX.IMUX32.DELAYGTX_DUAL.DFECLKDLYADJ14
CELL4.IMUX.IMUX33.DELAYGTX_DUAL.RXENSAMPLEALIGN1
CELL4.IMUX.IMUX34.DELAYGTX_DUAL.DFECLKDLYADJ12
CELL4.IMUX.IMUX36.DELAYCRC32_1.CRCIN31, CRC64_0.CRCIN31
CELL4.IMUX.IMUX37.DELAYCRC32_1.CRCIN30, CRC64_0.CRCIN30
CELL4.IMUX.IMUX42.DELAYCRC32_1.CRCIN29, CRC64_0.CRCIN29
CELL4.IMUX.IMUX43.DELAYCRC32_1.CRCIN28, CRC64_0.CRCIN28
CELL4.IMUX.IMUX44.DELAYCRC32_1.CRCIN27, CRC64_0.CRCIN27
CELL4.IMUX.IMUX45.DELAYCRC32_1.CRCIN26, CRC64_0.CRCIN26
CELL4.IMUX.IMUX46.DELAYCRC32_1.CRCIN25, CRC64_0.CRCIN25
CELL4.IMUX.IMUX47.DELAYCRC32_1.CRCIN24, CRC64_0.CRCIN24
CELL4.OUT0.TMINGTX_DUAL.RESETDONE1
CELL4.OUT1.TMINGTX_DUAL.DFECLKDLYADJMONITOR15
CELL4.OUT2.TMINGTX_DUAL.RXDATA12
CELL4.OUT3.TMINGTX_DUAL.DFECLKDLYADJMONITOR12
CELL4.OUT4.TMINGTX_DUAL.RXOVERSAMPLEERR1
CELL4.OUT6.TMINGTX_DUAL.RXBUFSTATUS10
CELL4.OUT7.TMINGTX_DUAL.DFECLKDLYADJMONITOR11
CELL4.OUT9.TMINGTX_DUAL.RXDATA10
CELL4.OUT10.TMINGTX_DUAL.RXDATA11
CELL4.OUT11.TMINGTX_DUAL.RXDATA13
CELL4.OUT12.TMINGTX_DUAL.RXDATA118
CELL4.OUT13.TMINGTX_DUAL.DFECLKDLYADJMONITOR14
CELL4.OUT14.TMINGTX_DUAL.DFECLKDLYADJMONITOR13
CELL4.OUT15.TMINGTX_DUAL.DFECLKDLYADJMONITOR10
CELL4.OUT16.TMINGTX_DUAL.RXBUFSTATUS11
CELL4.OUT17.TMINGTX_DUAL.PHYSTATUS1
CELL4.OUT18.TMINGTX_DUAL.RXDATA117
CELL4.OUT19.TMINGTX_DUAL.RXBUFSTATUS12
CELL4.OUT21.TMINCRC32_1.CRCOUT31
CELL4.OUT22.TMINGTX_DUAL.RXDATA116
CELL5.IMUX.IMUX0.DELAYGTX_DUAL.RXEQMIX11
CELL5.IMUX.IMUX1.DELAYGTX_DUAL.RXEQMIX10
CELL5.IMUX.IMUX2.DELAYGTX_DUAL.RXEQPOLE13
CELL5.IMUX.IMUX3.DELAYGTX_DUAL.RXEQPOLE12
CELL5.IMUX.IMUX4.DELAYGTX_DUAL.RXEQPOLE11
CELL5.IMUX.IMUX5.DELAYGTX_DUAL.RXEQPOLE10
CELL5.IMUX.IMUX11.DELAYGTX_DUAL.DFETAP211
CELL5.IMUX.IMUX12.DELAYGTX_DUAL.DFETAP114
CELL5.IMUX.IMUX13.DELAYGTX_DUAL.GTXTEST9
CELL5.IMUX.IMUX20.DELAYGTX_DUAL.DFETAP214
CELL5.IMUX.IMUX22.DELAYGTX_DUAL.DFETAP212
CELL5.IMUX.IMUX24.DELAYGTX_DUAL.DFECLKDLYADJ10
CELL5.IMUX.IMUX25.DELAYGTX_DUAL.DFETAP113
CELL5.IMUX.IMUX26.DELAYGTX_DUAL.DFETAP112
CELL5.IMUX.IMUX27.DELAYGTX_DUAL.DFETAP213
CELL5.IMUX.IMUX28.DELAYGTX_DUAL.DFETAP110
CELL5.IMUX.IMUX29.DELAYGTX_DUAL.DFETAP210
CELL5.IMUX.IMUX33.DELAYGTX_DUAL.DFETAP111
CELL5.IMUX.IMUX36.DELAYCRC32_1.CRCIN23, CRC64_0.CRCIN23
CELL5.IMUX.IMUX37.DELAYCRC32_1.CRCIN22, CRC64_0.CRCIN22
CELL5.IMUX.IMUX42.DELAYCRC32_1.CRCIN21, CRC64_0.CRCIN21
CELL5.IMUX.IMUX43.DELAYCRC32_1.CRCIN20, CRC64_0.CRCIN20
CELL5.IMUX.IMUX44.DELAYCRC32_1.CRCIN19, CRC64_0.CRCIN19
CELL5.IMUX.IMUX45.DELAYCRC32_1.CRCIN18, CRC64_0.CRCIN18
CELL5.IMUX.IMUX46.DELAYCRC32_1.CRCIN17, CRC64_0.CRCIN17
CELL5.IMUX.IMUX47.DELAYCRC32_1.CRCIN16, CRC64_0.CRCIN16
CELL5.OUT0.TMINGTX_DUAL.RXBYTEISALIGNED1
CELL5.OUT2.TMINGTX_DUAL.RXDATA16
CELL5.OUT4.TMINGTX_DUAL.RXNOTINTABLE10
CELL5.OUT5.TMINCRC32_1.CRCOUT29
CELL5.OUT6.TMINGTX_DUAL.RXRUNDISP10
CELL5.OUT7.TMINCRC32_1.CRCOUT28
CELL5.OUT8.TMINGTX_DUAL.RXCOMMADET1
CELL5.OUT9.TMINGTX_DUAL.RXDATA14
CELL5.OUT10.TMINGTX_DUAL.RXDATA15
CELL5.OUT11.TMINGTX_DUAL.RXDATA17
CELL5.OUT12.TMINGTX_DUAL.DFEEYEDACMONITOR14
CELL5.OUT13.TMINGTX_DUAL.DFEEYEDACMONITOR13
CELL5.OUT14.TMINGTX_DUAL.DFEEYEDACMONITOR12
CELL5.OUT15.TMINGTX_DUAL.DFEEYEDACMONITOR11
CELL5.OUT16.TMINGTX_DUAL.RXCHARISK10
CELL5.OUT17.TMINGTX_DUAL.RXCHARISCOMMA10
CELL5.OUT18.TMINGTX_DUAL.RXBYTEREALIGN1
CELL5.OUT19.TMINGTX_DUAL.RXDISPERR10
CELL5.OUT21.TMINCRC32_1.CRCOUT27
CELL5.OUT22.TMINCRC32_1.CRCOUT30
CELL6.IMUX.CLK1CRC32_1.CRCCLK
CELL6.IMUX.IMUX1.DELAYGTX_DUAL.RXCHBONDI12
CELL6.IMUX.IMUX2.DELAYGTX_DUAL.RXCHBONDI11
CELL6.IMUX.IMUX3.DELAYGTX_DUAL.RXCHBONDI10
CELL6.IMUX.IMUX6.DELAYGTX_DUAL.RXDEC8B10BUSE1
CELL6.IMUX.IMUX11.DELAYGTX_DUAL.DFETAP413
CELL6.IMUX.IMUX12.DELAYGTX_DUAL.TSTPWRDN14
CELL6.IMUX.IMUX13.DELAYGTX_DUAL.TSTPWRDN13
CELL6.IMUX.IMUX14.DELAYGTX_DUAL.TSTPWRDN12
CELL6.IMUX.IMUX15.DELAYGTX_DUAL.TSTPWRDN11
CELL6.IMUX.IMUX16.DELAYGTX_DUAL.TSTPWRDN10
CELL6.IMUX.IMUX23.DELAYGTX_DUAL.RXCHBONDI13
CELL6.IMUX.IMUX24.DELAYGTX_DUAL.RXENCHANSYNC1
CELL6.IMUX.IMUX31.DELAYGTX_DUAL.DFETAP313
CELL6.IMUX.IMUX32.DELAYGTX_DUAL.DFETAP312
CELL6.IMUX.IMUX34.DELAYGTX_DUAL.DFETAP310
CELL6.IMUX.IMUX36.DELAYCRC32_1.CRCIN15, CRC64_0.CRCIN15
CELL6.IMUX.IMUX37.DELAYCRC32_1.CRCIN14, CRC64_0.CRCIN14
CELL6.IMUX.IMUX39.DELAYGTX_DUAL.DFETAP311
CELL6.IMUX.IMUX42.DELAYCRC32_1.CRCIN13, CRC64_0.CRCIN13
CELL6.IMUX.IMUX43.DELAYCRC32_1.CRCIN12, CRC64_0.CRCIN12
CELL6.IMUX.IMUX44.DELAYCRC32_1.CRCIN11, CRC64_0.CRCIN11
CELL6.IMUX.IMUX45.DELAYCRC32_1.CRCIN10, CRC64_0.CRCIN10
CELL6.IMUX.IMUX46.DELAYCRC32_1.CRCIN9, CRC64_0.CRCIN9
CELL6.IMUX.IMUX47.DELAYCRC32_1.CRCIN8, CRC64_0.CRCIN8
CELL6.OUT0.TMINGTX_DUAL.RXVALID1
CELL6.OUT2.TMINGTX_DUAL.RXDATA110
CELL6.OUT4.TMINGTX_DUAL.RXNOTINTABLE11
CELL6.OUT5.TMINGTX_DUAL.DFETAP1MONITOR14
CELL6.OUT6.TMINGTX_DUAL.RXRUNDISP11
CELL6.OUT7.TMINGTX_DUAL.DFETAP1MONITOR12
CELL6.OUT8.TMINGTX_DUAL.RXLOSSOFSYNC11
CELL6.OUT9.TMINGTX_DUAL.RXDATA18
CELL6.OUT10.TMINGTX_DUAL.RXDATA19
CELL6.OUT11.TMINGTX_DUAL.RXDATA111
CELL6.OUT12.TMINCRC32_1.CRCOUT26
CELL6.OUT14.TMINCRC32_1.CRCOUT25
CELL6.OUT15.TMINCRC32_1.CRCOUT24
CELL6.OUT16.TMINGTX_DUAL.RXCHARISK11
CELL6.OUT17.TMINGTX_DUAL.RXCHARISCOMMA11
CELL6.OUT18.TMINGTX_DUAL.DFEEYEDACMONITOR10
CELL6.OUT19.TMINGTX_DUAL.RXDISPERR11
CELL6.OUT21.TMINGTX_DUAL.DFETAP1MONITOR11
CELL6.OUT22.TMINGTX_DUAL.RXLOSSOFSYNC10
CELL6.OUT23.TMINGTX_DUAL.DFETAP1MONITOR13
CELL7.IMUX.CLK1GTX_DUAL.DCLK
CELL7.IMUX.IMUX0.DELAYGTX_DUAL.RXCDRRESET1
CELL7.IMUX.IMUX4.DELAYGTX_DUAL.RXBUFRESET1
CELL7.IMUX.IMUX5.DELAYGTX_DUAL.RXRESET1
CELL7.IMUX.IMUX8.DELAYGTX_DUAL.RXPOWERDOWN11
CELL7.IMUX.IMUX9.DELAYGTX_DUAL.RXPOWERDOWN10
CELL7.IMUX.IMUX18.DELAYGTX_DUAL.LOOPBACK12
CELL7.IMUX.IMUX19.DELAYGTX_DUAL.LOOPBACK11
CELL7.IMUX.IMUX20.DELAYGTX_DUAL.LOOPBACK10
CELL7.IMUX.IMUX24.DELAYGTX_DUAL.DFETAP412
CELL7.IMUX.IMUX25.DELAYGTX_DUAL.DFETAP411
CELL7.IMUX.IMUX28.DELAYGTX_DUAL.DFETAP410
CELL7.IMUX.IMUX34.DELAYGTX_DUAL.RXENPMAPHASEALIGN1
CELL7.IMUX.IMUX36.DELAYCRC32_1.CRCIN7, CRC64_0.CRCIN7
CELL7.IMUX.IMUX37.DELAYCRC32_1.CRCIN6, CRC64_0.CRCIN6
CELL7.IMUX.IMUX40.DELAYGTX_DUAL.RXPMASETPHASE1
CELL7.IMUX.IMUX42.DELAYCRC32_1.CRCIN5, CRC64_0.CRCIN5
CELL7.IMUX.IMUX43.DELAYCRC32_1.CRCIN4, CRC64_0.CRCIN4
CELL7.IMUX.IMUX44.DELAYCRC32_1.CRCIN3, CRC64_0.CRCIN3
CELL7.IMUX.IMUX45.DELAYCRC32_1.CRCIN2, CRC64_0.CRCIN2
CELL7.IMUX.IMUX46.DELAYCRC32_1.CRCIN1, CRC64_0.CRCIN1
CELL7.IMUX.IMUX47.DELAYCRC32_1.CRCIN0, CRC64_0.CRCIN0
CELL7.OUT0.TMINGTX_DUAL.RXCHBONDO11
CELL7.OUT1.TMINGTX_DUAL.DFETAP2MONITOR14
CELL7.OUT2.TMINGTX_DUAL.RXDATA114
CELL7.OUT3.TMINCRC32_1.CRCOUT22
CELL7.OUT4.TMINGTX_DUAL.RXCHANREALIGN1
CELL7.OUT5.TMINGTX_DUAL.RXCHBONDO13
CELL7.OUT6.TMINGTX_DUAL.RXCHANBONDSEQ1
CELL7.OUT7.TMINGTX_DUAL.SCANOUTPCS1
CELL7.OUT8.TMINGTX_DUAL.RXCHBONDO12
CELL7.OUT9.TMINGTX_DUAL.RXDATA112
CELL7.OUT10.TMINGTX_DUAL.RXDATA113
CELL7.OUT11.TMINGTX_DUAL.RXDATA115
CELL7.OUT12.TMINCRC32_1.CRCOUT23
CELL7.OUT13.TMINGTX_DUAL.DFETAP2MONITOR13
CELL7.OUT14.TMINGTX_DUAL.DFETAP2MONITOR12
CELL7.OUT16.TMINGTX_DUAL.DFETAP2MONITOR11
CELL7.OUT17.TMINCRC32_1.CRCOUT21
CELL7.OUT18.TMINGTX_DUAL.RXCHANISALIGNED1
CELL7.OUT19.TMINGTX_DUAL.RXCHBONDO10
CELL7.OUT20.TMINGTX_DUAL.RXRECCLK1
CELL7.OUT21.TMINCRC32_1.CRCOUT20
CELL7.OUT22.TMINGTX_DUAL.DFETAP1MONITOR10
CELL8.IMUX.CLK0GTX_DUAL.TXUSRCLK21
CELL8.IMUX.CLK1GTX_DUAL.TXUSRCLK1
CELL8.IMUX.IMUX0.DELAYCRC32_1.CRCRESET
CELL8.IMUX.IMUX2.DELAYGTX_DUAL.PRBSCNTRESET1
CELL8.IMUX.IMUX11.DELAYCRC32_1.CRCDATAWIDTH0
CELL8.IMUX.IMUX34.DELAYCRC32_1.CRCDATAWIDTH1
CELL8.IMUX.IMUX35.DELAYCRC32_1.CRCDATAVALID
CELL8.IMUX.IMUX44.DELAYGTX_DUAL.DI15
CELL8.IMUX.IMUX45.DELAYGTX_DUAL.DI14
CELL8.IMUX.IMUX46.DELAYGTX_DUAL.DI13
CELL8.IMUX.IMUX47.DELAYGTX_DUAL.DI12
CELL8.OUT0.TMINCRC32_1.CRCOUT19
CELL8.OUT1.TMINGTX_DUAL.SCANOUTPCSCOMMON
CELL8.OUT2.TMINCRC32_1.CRCOUT13
CELL8.OUT4.TMINGTX_DUAL.DFETAP3MONITOR13
CELL8.OUT5.TMINCRC32_1.CRCOUT18
CELL8.OUT6.TMINCRC32_1.CRCOUT12
CELL8.OUT7.TMINGTX_DUAL.DFETAP3MONITOR11
CELL8.OUT8.TMINGTX_DUAL.DO15
CELL8.OUT9.TMINCRC32_1.CRCOUT17
CELL8.OUT10.TMINCRC32_1.CRCOUT15
CELL8.OUT11.TMINCRC32_1.CRCOUT11
CELL8.OUT12.TMINGTX_DUAL.DO14
CELL8.OUT13.TMINGTX_DUAL.DO12
CELL8.OUT15.TMINCRC32_1.CRCOUT10
CELL8.OUT16.TMINCRC32_1.CRCOUT14
CELL8.OUT17.TMINCRC32_1.CRCOUT9
CELL8.OUT18.TMINGTX_DUAL.DO13
CELL8.OUT20.TMINGTX_DUAL.DFETAP3MONITOR12
CELL8.OUT21.TMINGTX_DUAL.DFETAP3MONITOR10
CELL8.OUT22.TMINGTX_DUAL.DFETAP2MONITOR10
CELL8.OUT23.TMINCRC32_1.CRCOUT16
CELL9.IMUX.CLK0GTX_DUAL.RXUSRCLK21
CELL9.IMUX.CLK1GTX_DUAL.RXUSRCLK1
CELL9.IMUX.IMUX3.DELAYGTX_DUAL.PMAAMUX0
CELL9.IMUX.IMUX4.DELAYGTX_DUAL.PMAAMUX1
CELL9.IMUX.IMUX5.DELAYGTX_DUAL.PMAAMUX2
CELL9.IMUX.IMUX8.DELAYGTX_DUAL.PLLLKDETEN
CELL9.IMUX.IMUX16.DELAYGTX_DUAL.GTXTEST2
CELL9.IMUX.IMUX17.DELAYGTX_DUAL.GTXTEST3
CELL9.IMUX.IMUX18.DELAYGTX_DUAL.REFCLKPWRDNB
CELL9.IMUX.IMUX19.DELAYGTX_DUAL.DWE
CELL9.IMUX.IMUX20.DELAYGTX_DUAL.TXENPMAPHASEALIGN1
CELL9.IMUX.IMUX26.DELAYGTX_DUAL.DADDR6
CELL9.IMUX.IMUX27.DELAYGTX_DUAL.DADDR5
CELL9.IMUX.IMUX28.DELAYGTX_DUAL.DADDR4
CELL9.IMUX.IMUX29.DELAYGTX_DUAL.DADDR3
CELL9.IMUX.IMUX33.DELAYGTX_DUAL.TXPMASETPHASE1
CELL9.IMUX.IMUX42.DELAYGTX_DUAL.DI11
CELL9.IMUX.IMUX43.DELAYGTX_DUAL.DI10
CELL9.IMUX.IMUX44.DELAYGTX_DUAL.DI9
CELL9.IMUX.IMUX45.DELAYGTX_DUAL.DI8
CELL9.OUT0.TMINCRC32_1.CRCOUT5
CELL9.OUT2.TMINGTX_DUAL.TXOUTCLK1
CELL9.OUT3.TMINCRC32_1.CRCOUT1
CELL9.OUT4.TMINCRC32_1.CRCOUT4
CELL9.OUT5.TMINGTX_DUAL.DFETAP4MONITOR13
CELL9.OUT6.TMINGTX_DUAL.DO9
CELL9.OUT7.TMINGTX_DUAL.DFESENSCAL10
CELL9.OUT8.TMINCRC32_1.CRCOUT8
CELL9.OUT9.TMINGTX_DUAL.DFESENSCAL11
CELL9.OUT10.TMINGTX_DUAL.DO11
CELL9.OUT11.TMINCRC32_1.CRCOUT0
CELL9.OUT12.TMINCRC32_1.CRCOUT7
CELL9.OUT13.TMINCRC32_1.CRCOUT3
CELL9.OUT14.TMINCRC32_1.CRCOUT2
CELL9.OUT15.TMINGTX_DUAL.DRDY
CELL9.OUT16.TMINGTX_DUAL.DFETAP4MONITOR11
CELL9.OUT17.TMINGTX_DUAL.DFETAP4MONITOR10
CELL9.OUT18.TMINCRC32_1.CRCOUT6
CELL9.OUT19.TMINGTX_DUAL.DFETAP4MONITOR12
CELL9.OUT20.TMINGTX_DUAL.DO10
CELL9.OUT21.TMINGTX_DUAL.DO8
CELL9.OUT22.TMINGTX_DUAL.DFESENSCAL12
CELL9.OUT23.TMINGTX_DUAL.PLLLKDET
CELL10.IMUX.CLK0GTX_DUAL.RXUSRCLK0
CELL10.IMUX.CLK1GTX_DUAL.RXUSRCLK20
CELL10.IMUX.IMUX0.DELAYGTX_DUAL.DI7
CELL10.IMUX.IMUX1.DELAYGTX_DUAL.DI6
CELL10.IMUX.IMUX2.DELAYGTX_DUAL.DI5
CELL10.IMUX.IMUX3.DELAYGTX_DUAL.DI4
CELL10.IMUX.IMUX6.DELAYGTX_DUAL.INTDATAWIDTH
CELL10.IMUX.IMUX12.DELAYGTX_DUAL.PMATSTCLKSEL2
CELL10.IMUX.IMUX13.DELAYGTX_DUAL.PMATSTCLKSEL1
CELL10.IMUX.IMUX14.DELAYGTX_DUAL.PMATSTCLKSEL0
CELL10.IMUX.IMUX16.DELAYGTX_DUAL.TXENPMAPHASEALIGN0
CELL10.IMUX.IMUX17.DELAYGTX_DUAL.TXPMASETPHASE0
CELL10.IMUX.IMUX24.DELAYGTX_DUAL.DADDR2
CELL10.IMUX.IMUX31.DELAYGTX_DUAL.DADDR1
CELL10.IMUX.IMUX32.DELAYGTX_DUAL.DADDR0
CELL10.IMUX.IMUX33.DELAYGTX_DUAL.GTXTEST13
CELL10.IMUX.IMUX36.DELAYGTX_DUAL.PLLPOWERDOWN
CELL10.IMUX.IMUX39.DELAYGTX_DUAL.DEN
CELL10.IMUX.IMUX40.DELAYGTX_DUAL.GTXTEST8
CELL10.OUT0.TMINGTX_DUAL.DO6
CELL10.OUT1.TMINGTX_DUAL.DFETAP4MONITOR00
CELL10.OUT2.TMINCRC32_2.CRCOUT3
CELL10.OUT3.TMINGTX_DUAL.DFETAP4MONITOR03
CELL10.OUT4.TMINCRC32_2.CRCOUT0
CELL10.OUT6.TMINCRC32_2.CRCOUT4
CELL10.OUT7.TMINCRC32_2.CRCOUT5
CELL10.OUT8.TMINGTX_DUAL.REFCLKOUT
CELL10.OUT9.TMINGTX_DUAL.DO5
CELL10.OUT10.TMINGTX_DUAL.DO4
CELL10.OUT11.TMINCRC32_2.CRCOUT6
CELL10.OUT12.TMINGTX_DUAL.DO7
CELL10.OUT13.TMINGTX_DUAL.TXOUTCLK0
CELL10.OUT14.TMINGTX_DUAL.DFETAP4MONITOR01
CELL10.OUT15.TMINCRC32_2.CRCOUT7
CELL10.OUT16.TMINCRC32_2.CRCOUT2
CELL10.OUT17.TMINGTX_DUAL.DFESENSCAL02
CELL10.OUT18.TMINGTX_DUAL.DFESENSCAL00
CELL10.OUT19.TMINGTX_DUAL.DFESENSCAL01
CELL10.OUT20.TMINGTX_DUAL.DFETAP4MONITOR02
CELL10.OUT21.TMINCRC32_2.CRCOUT8
CELL10.OUT22.TMINGTX_DUAL.PMATSTCLK
CELL10.OUT23.TMINCRC32_2.CRCOUT1
CELL11.IMUX.CLK0GTX_DUAL.TXUSRCLK0
CELL11.IMUX.CLK1GTX_DUAL.TXUSRCLK20
CELL11.IMUX.IMUX0.DELAYGTX_DUAL.DI3
CELL11.IMUX.IMUX1.DELAYGTX_DUAL.DI2
CELL11.IMUX.IMUX2.DELAYGTX_DUAL.DI1
CELL11.IMUX.IMUX3.DELAYGTX_DUAL.DI0
CELL11.IMUX.IMUX5.DELAYCRC32_2.CRCRESET
CELL11.IMUX.IMUX13.DELAYCRC32_2.CRCDATAWIDTH1
CELL11.IMUX.IMUX24.DELAYCRC32_2.CRCDATAWIDTH0
CELL11.IMUX.IMUX29.DELAYGTX_DUAL.SCANINPCSCOMMON
CELL11.IMUX.IMUX30.DELAYCRC32_2.CRCDATAVALID
CELL11.IMUX.IMUX36.DELAYGTX_DUAL.GTXRESET
CELL11.IMUX.IMUX45.DELAYGTX_DUAL.PRBSCNTRESET0
CELL11.OUT1.TMINGTX_DUAL.DFETAP3MONITOR02
CELL11.OUT3.TMINCRC32_2.CRCOUT18
CELL11.OUT4.TMINCRC32_2.CRCOUT10
CELL11.OUT5.TMINCRC32_2.CRCOUT12
CELL11.OUT7.TMINCRC32_2.CRCOUT19
CELL11.OUT8.TMINGTX_DUAL.DFETAP3MONITOR00
CELL11.OUT10.TMINCRC32_2.CRCOUT16
CELL11.OUT11.TMINGTX_DUAL.DFETAP3MONITOR03
CELL11.OUT12.TMINCRC32_2.CRCOUT9
CELL11.OUT13.TMINCRC32_2.CRCOUT13
CELL11.OUT14.TMINGTX_DUAL.DO3
CELL11.OUT15.TMINGTX_DUAL.DO2
CELL11.OUT16.TMINCRC32_2.CRCOUT17
CELL11.OUT17.TMINGTX_DUAL.DO1
CELL11.OUT18.TMINGTX_DUAL.DFETAP3MONITOR01
CELL11.OUT19.TMINCRC32_2.CRCOUT14
CELL11.OUT21.TMINGTX_DUAL.DO0
CELL11.OUT22.TMINCRC32_2.CRCOUT11
CELL11.OUT23.TMINCRC32_2.CRCOUT15
CELL12.IMUX.CLK0GTX_DUAL.GREFCLK
CELL12.IMUX.IMUX0.DELAYCRC32_2.CRCIN0, CRC64_1.CRCIN0
CELL12.IMUX.IMUX1.DELAYCRC32_2.CRCIN1, CRC64_1.CRCIN1
CELL12.IMUX.IMUX2.DELAYCRC32_2.CRCIN2, CRC64_1.CRCIN2
CELL12.IMUX.IMUX7.DELAYGTX_DUAL.RXPMASETPHASE0
CELL12.IMUX.IMUX9.DELAYCRC32_2.CRCIN3, CRC64_1.CRCIN3
CELL12.IMUX.IMUX10.DELAYCRC32_2.CRCIN6, CRC64_1.CRCIN6
CELL12.IMUX.IMUX11.DELAYCRC32_2.CRCIN7, CRC64_1.CRCIN7
CELL12.IMUX.IMUX13.DELAYGTX_DUAL.RXENPMAPHASEALIGN0
CELL12.IMUX.IMUX15.DELAYGTX_DUAL.LOOPBACK00
CELL12.IMUX.IMUX16.DELAYGTX_DUAL.LOOPBACK01
CELL12.IMUX.IMUX17.DELAYGTX_DUAL.LOOPBACK02
CELL12.IMUX.IMUX35.DELAYCRC32_2.CRCIN5, CRC64_1.CRCIN5
CELL12.IMUX.IMUX37.DELAYGTX_DUAL.DFETAP400
CELL12.IMUX.IMUX38.DELAYGTX_DUAL.RXPOWERDOWN00
CELL12.IMUX.IMUX39.DELAYGTX_DUAL.RXPOWERDOWN01
CELL12.IMUX.IMUX40.DELAYGTX_DUAL.DFETAP401
CELL12.IMUX.IMUX41.DELAYGTX_DUAL.DFETAP402
CELL12.IMUX.IMUX42.DELAYGTX_DUAL.RXRESET0
CELL12.IMUX.IMUX43.DELAYGTX_DUAL.RXBUFRESET0
CELL12.IMUX.IMUX45.DELAYCRC32_2.CRCIN4, CRC64_1.CRCIN4
CELL12.IMUX.IMUX47.DELAYGTX_DUAL.RXCDRRESET0
CELL12.OUT1.TMINGTX_DUAL.RXCHANBONDSEQ0
CELL12.OUT2.TMINGTX_DUAL.DFETAP2MONITOR03
CELL12.OUT3.TMINGTX_DUAL.RXCHANREALIGN0
CELL12.OUT4.TMINCRC32_2.CRCOUT22
CELL12.OUT5.TMINGTX_DUAL.RXDATA014
CELL12.OUT6.TMINGTX_DUAL.DFETAP2MONITOR04
CELL12.OUT7.TMINGTX_DUAL.RXCHBONDO01
CELL12.OUT8.TMINCRC32_2.CRCOUT20
CELL12.OUT10.TMINGTX_DUAL.SCANOUTPCS0
CELL12.OUT11.TMINGTX_DUAL.RXCHBONDO03
CELL12.OUT12.TMINGTX_DUAL.DFETAP2MONITOR00
CELL12.OUT13.TMINGTX_DUAL.RXRECCLK0
CELL12.OUT14.TMINGTX_DUAL.RXCHBONDO00
CELL12.OUT15.TMINGTX_DUAL.RXCHANISALIGNED0
CELL12.OUT16.TMINGTX_DUAL.DFETAP2MONITOR02
CELL12.OUT17.TMINCRC32_2.CRCOUT23
CELL12.OUT18.TMINCRC32_2.CRCOUT21
CELL12.OUT19.TMINGTX_DUAL.DFETAP2MONITOR01
CELL12.OUT20.TMINGTX_DUAL.RXDATA012
CELL12.OUT21.TMINGTX_DUAL.RXCHBONDO02
CELL12.OUT22.TMINGTX_DUAL.RXDATA015
CELL12.OUT23.TMINGTX_DUAL.RXDATA013
CELL13.IMUX.CLK0CRC32_2.CRCCLK
CELL13.IMUX.IMUX4.DELAYCRC32_2.CRCIN12, CRC64_1.CRCIN12
CELL13.IMUX.IMUX5.DELAYCRC32_2.CRCIN13, CRC64_1.CRCIN13
CELL13.IMUX.IMUX6.DELAYCRC32_2.CRCIN8, CRC64_1.CRCIN8
CELL13.IMUX.IMUX7.DELAYCRC32_2.CRCIN9, CRC64_1.CRCIN9
CELL13.IMUX.IMUX8.DELAYCRC32_2.CRCIN10, CRC64_1.CRCIN10
CELL13.IMUX.IMUX9.DELAYCRC32_2.CRCIN11, CRC64_1.CRCIN11
CELL13.IMUX.IMUX10.DELAYCRC32_2.CRCIN14, CRC64_1.CRCIN14
CELL13.IMUX.IMUX11.DELAYCRC32_2.CRCIN15, CRC64_1.CRCIN15
CELL13.IMUX.IMUX23.DELAYGTX_DUAL.RXENCHANSYNC0
CELL13.IMUX.IMUX25.DELAYGTX_DUAL.DFETAP300
CELL13.IMUX.IMUX26.DELAYGTX_DUAL.DFETAP301
CELL13.IMUX.IMUX27.DELAYGTX_DUAL.DFETAP302
CELL13.IMUX.IMUX28.DELAYGTX_DUAL.DFETAP303
CELL13.IMUX.IMUX31.DELAYGTX_DUAL.TSTPWRDN00
CELL13.IMUX.IMUX32.DELAYGTX_DUAL.TSTPWRDN01
CELL13.IMUX.IMUX33.DELAYGTX_DUAL.TSTPWRDN02
CELL13.IMUX.IMUX34.DELAYGTX_DUAL.TSTPWRDN03
CELL13.IMUX.IMUX35.DELAYGTX_DUAL.TSTPWRDN04
CELL13.IMUX.IMUX36.DELAYGTX_DUAL.DFETAP403
CELL13.IMUX.IMUX41.DELAYGTX_DUAL.RXDEC8B10BUSE0
CELL13.IMUX.IMUX43.DELAYGTX_DUAL.RXCHBONDI03
CELL13.IMUX.IMUX44.DELAYGTX_DUAL.RXCHBONDI00
CELL13.IMUX.IMUX45.DELAYGTX_DUAL.RXCHBONDI01
CELL13.IMUX.IMUX46.DELAYGTX_DUAL.RXCHBONDI02
CELL13.OUT0.TMINGTX_DUAL.DFETAP1MONITOR01
CELL13.OUT1.TMINGTX_DUAL.RXRUNDISP01
CELL13.OUT3.TMINGTX_DUAL.RXNOTINTABLE01
CELL13.OUT5.TMINGTX_DUAL.RXDATA010
CELL13.OUT6.TMINGTX_DUAL.DFETAP1MONITOR03
CELL13.OUT7.TMINGTX_DUAL.RXVALID0
CELL13.OUT8.TMINGTX_DUAL.DFETAP1MONITOR00
CELL13.OUT11.TMINGTX_DUAL.RXLOSSOFSYNC00
CELL13.OUT12.TMINGTX_DUAL.RXCHARISCOMMA01
CELL13.OUT13.TMINGTX_DUAL.RXCHARISK01
CELL13.OUT14.TMINGTX_DUAL.RXDISPERR01
CELL13.OUT15.TMINGTX_DUAL.DFETAP1MONITOR04
CELL13.OUT16.TMINGTX_DUAL.DFETAP1MONITOR02
CELL13.OUT17.TMINCRC32_2.CRCOUT26
CELL13.OUT18.TMINCRC32_2.CRCOUT24
CELL13.OUT19.TMINCRC32_2.CRCOUT25
CELL13.OUT20.TMINGTX_DUAL.RXDATA08
CELL13.OUT21.TMINGTX_DUAL.RXLOSSOFSYNC01
CELL13.OUT22.TMINGTX_DUAL.RXDATA011
CELL13.OUT23.TMINGTX_DUAL.RXDATA09
CELL14.IMUX.IMUX4.DELAYCRC32_2.CRCIN20, CRC64_1.CRCIN20
CELL14.IMUX.IMUX5.DELAYCRC32_2.CRCIN21, CRC64_1.CRCIN21
CELL14.IMUX.IMUX6.DELAYCRC32_2.CRCIN16, CRC64_1.CRCIN16
CELL14.IMUX.IMUX7.DELAYCRC32_2.CRCIN17, CRC64_1.CRCIN17
CELL14.IMUX.IMUX8.DELAYCRC32_2.CRCIN18, CRC64_1.CRCIN18
CELL14.IMUX.IMUX9.DELAYCRC32_2.CRCIN19, CRC64_1.CRCIN19
CELL14.IMUX.IMUX10.DELAYCRC32_2.CRCIN22, CRC64_1.CRCIN22
CELL14.IMUX.IMUX11.DELAYCRC32_2.CRCIN23, CRC64_1.CRCIN23
CELL14.IMUX.IMUX12.DELAYGTX_DUAL.DFETAP200
CELL14.IMUX.IMUX22.DELAYGTX_DUAL.GTXTEST4
CELL14.IMUX.IMUX23.DELAYGTX_DUAL.DFECLKDLYADJ00
CELL14.IMUX.IMUX26.DELAYGTX_DUAL.DFETAP101
CELL14.IMUX.IMUX31.DELAYGTX_DUAL.DFETAP100
CELL14.IMUX.IMUX33.DELAYGTX_DUAL.DFETAP102
CELL14.IMUX.IMUX34.DELAYGTX_DUAL.DFETAP103
CELL14.IMUX.IMUX35.DELAYGTX_DUAL.DFETAP104
CELL14.IMUX.IMUX36.DELAYGTX_DUAL.DFETAP201
CELL14.IMUX.IMUX37.DELAYGTX_DUAL.DFETAP202
CELL14.IMUX.IMUX38.DELAYGTX_DUAL.DFETAP203
CELL14.IMUX.IMUX39.DELAYGTX_DUAL.DFETAP204
CELL14.IMUX.IMUX42.DELAYGTX_DUAL.RXEQPOLE00
CELL14.IMUX.IMUX43.DELAYGTX_DUAL.RXEQPOLE01
CELL14.IMUX.IMUX44.DELAYGTX_DUAL.RXEQPOLE02
CELL14.IMUX.IMUX45.DELAYGTX_DUAL.RXEQPOLE03
CELL14.IMUX.IMUX46.DELAYGTX_DUAL.RXEQMIX00
CELL14.IMUX.IMUX47.DELAYGTX_DUAL.RXEQMIX01
CELL14.OUT0.TMINGTX_DUAL.DFEEYEDACMONITOR00
CELL14.OUT1.TMINGTX_DUAL.RXRUNDISP00
CELL14.OUT2.TMINGTX_DUAL.DFEEYEDACMONITOR03
CELL14.OUT3.TMINGTX_DUAL.RXNOTINTABLE00
CELL14.OUT4.TMINCRC32_2.CRCOUT28
CELL14.OUT5.TMINGTX_DUAL.RXDATA06
CELL14.OUT6.TMINCRC32_2.CRCOUT29
CELL14.OUT7.TMINGTX_DUAL.RXBYTEISALIGNED0
CELL14.OUT12.TMINGTX_DUAL.RXCHARISCOMMA00
CELL14.OUT13.TMINGTX_DUAL.RXCHARISK00
CELL14.OUT14.TMINGTX_DUAL.RXDISPERR00
CELL14.OUT15.TMINGTX_DUAL.RXBYTEREALIGN0
CELL14.OUT16.TMINGTX_DUAL.DFEEYEDACMONITOR02
CELL14.OUT17.TMINCRC32_2.CRCOUT30
CELL14.OUT18.TMINCRC32_2.CRCOUT27
CELL14.OUT19.TMINGTX_DUAL.DFEEYEDACMONITOR01
CELL14.OUT20.TMINGTX_DUAL.RXDATA04
CELL14.OUT21.TMINGTX_DUAL.RXCOMMADET0
CELL14.OUT22.TMINGTX_DUAL.RXDATA07
CELL14.OUT23.TMINGTX_DUAL.RXDATA05
CELL15.IMUX.IMUX4.DELAYCRC32_2.CRCIN28, CRC64_1.CRCIN28
CELL15.IMUX.IMUX5.DELAYCRC32_2.CRCIN29, CRC64_1.CRCIN29
CELL15.IMUX.IMUX6.DELAYCRC32_2.CRCIN24, CRC64_1.CRCIN24
CELL15.IMUX.IMUX7.DELAYCRC32_2.CRCIN25, CRC64_1.CRCIN25
CELL15.IMUX.IMUX8.DELAYCRC32_2.CRCIN26, CRC64_1.CRCIN26
CELL15.IMUX.IMUX9.DELAYCRC32_2.CRCIN27, CRC64_1.CRCIN27
CELL15.IMUX.IMUX10.DELAYCRC32_2.CRCIN30, CRC64_1.CRCIN30
CELL15.IMUX.IMUX11.DELAYCRC32_2.CRCIN31, CRC64_1.CRCIN31
CELL15.IMUX.IMUX14.DELAYGTX_DUAL.RXENSAMPLEALIGN0
CELL15.IMUX.IMUX17.DELAYGTX_DUAL.RXGEARBOXSLIP0
CELL15.IMUX.IMUX18.DELAYGTX_DUAL.RXDATAWIDTH01
CELL15.IMUX.IMUX19.DELAYGTX_DUAL.DFECLKDLYADJ02
CELL15.IMUX.IMUX21.DELAYGTX_DUAL.TXBYPASS8B10B03
CELL15.IMUX.IMUX27.DELAYGTX_DUAL.TXBYPASS8B10B02
CELL15.IMUX.IMUX28.DELAYGTX_DUAL.RXENPRBSTST00
CELL15.IMUX.IMUX29.DELAYGTX_DUAL.RXENPRBSTST01
CELL15.IMUX.IMUX30.DELAYGTX_DUAL.RXCOMMADETUSE0
CELL15.IMUX.IMUX36.DELAYGTX_DUAL.DFECLKDLYADJ01
CELL15.IMUX.IMUX37.DELAYGTX_DUAL.RXDATAWIDTH00
CELL15.IMUX.IMUX38.DELAYGTX_DUAL.DFECLKDLYADJ03
CELL15.IMUX.IMUX39.DELAYGTX_DUAL.DFECLKDLYADJ04
CELL15.IMUX.IMUX40.DELAYGTX_DUAL.DFECLKDLYADJ05
CELL15.IMUX.IMUX41.DELAYGTX_DUAL.RXPOLARITY0
CELL15.IMUX.IMUX42.DELAYGTX_DUAL.RXENEQB0
CELL15.IMUX.IMUX44.DELAYGTX_DUAL.RXSLIDE0
CELL15.IMUX.IMUX45.DELAYGTX_DUAL.RXENMCOMMAALIGN0
CELL15.IMUX.IMUX46.DELAYGTX_DUAL.RXENPCOMMAALIGN0
CELL15.OUT0.TMINGTX_DUAL.DFECLKDLYADJMONITOR01
CELL15.OUT1.TMINGTX_DUAL.RXBUFSTATUS00
CELL15.OUT3.TMINGTX_DUAL.RXOVERSAMPLEERR0
CELL15.OUT4.TMINGTX_DUAL.DFECLKDLYADJMONITOR00
CELL15.OUT5.TMINGTX_DUAL.RXDATA02
CELL15.OUT6.TMINGTX_DUAL.DFECLKDLYADJMONITOR04
CELL15.OUT7.TMINGTX_DUAL.RESETDONE0
CELL15.OUT8.TMINGTX_DUAL.DFEEYEDACMONITOR04
CELL15.OUT12.TMINGTX_DUAL.PHYSTATUS0
CELL15.OUT13.TMINGTX_DUAL.RXBUFSTATUS01
CELL15.OUT14.TMINGTX_DUAL.RXBUFSTATUS02
CELL15.OUT15.TMINGTX_DUAL.DFECLKDLYADJMONITOR05
CELL15.OUT16.TMINGTX_DUAL.DFECLKDLYADJMONITOR03
CELL15.OUT17.TMINGTX_DUAL.RXDATA016
CELL15.OUT18.TMINCRC32_2.CRCOUT31
CELL15.OUT19.TMINGTX_DUAL.DFECLKDLYADJMONITOR02
CELL15.OUT20.TMINGTX_DUAL.RXDATA00
CELL15.OUT21.TMINGTX_DUAL.RXDATA017
CELL15.OUT22.TMINGTX_DUAL.RXDATA03
CELL15.OUT23.TMINGTX_DUAL.RXDATA01
CELL16.IMUX.IMUX1.DELAYCRC32_3.CRCDATAWIDTH1, CRC64_1.CRCDATAWIDTH1
CELL16.IMUX.IMUX4.DELAYGTX_DUAL.TXHEADER02
CELL16.IMUX.IMUX6.DELAYCRC32_3.CRCDATAWIDTH0, CRC64_1.CRCDATAWIDTH0
CELL16.IMUX.IMUX7.DELAYCRC32_3.CRCDATAVALID, CRC64_1.CRCDATAVALID
CELL16.IMUX.IMUX8.DELAYCRC32_2.CRCDATAWIDTH2, CRC32_3.CRCDATAWIDTH2, CRC64_1.CRCDATAWIDTH2
CELL16.IMUX.IMUX9.DELAYGTX_DUAL.TXSTARTSEQ0
CELL16.IMUX.IMUX10.DELAYCRC32_3.CRCIN6, CRC64_1.CRCIN38
CELL16.IMUX.IMUX11.DELAYCRC32_3.CRCIN7, CRC64_1.CRCIN39
CELL16.IMUX.IMUX20.DELAYGTX_DUAL.TXDATA031
CELL16.IMUX.IMUX21.DELAYGTX_DUAL.TXDATA030
CELL16.IMUX.IMUX22.DELAYGTX_DUAL.TXDATA029
CELL16.IMUX.IMUX23.DELAYGTX_DUAL.TXDATA028
CELL16.IMUX.IMUX24.DELAYGTX_DUAL.TXDATAWIDTH01
CELL16.IMUX.IMUX28.DELAYGTX_DUAL.TXINHIBIT0
CELL16.IMUX.IMUX30.DELAYGTX_DUAL.TXENC8B10BUSE0
CELL16.IMUX.IMUX31.DELAYGTX_DUAL.TXDATAWIDTH00
CELL16.IMUX.IMUX32.DELAYGTX_DUAL.TXHEADER00
CELL16.IMUX.IMUX33.DELAYGTX_DUAL.TXHEADER01
CELL16.IMUX.IMUX35.DELAYCRC32_3.CRCIN5, CRC64_1.CRCIN37
CELL16.IMUX.IMUX36.DELAYCRC32_3.CRCIN0, CRC64_1.CRCIN32
CELL16.IMUX.IMUX37.DELAYCRC32_3.CRCIN1, CRC64_1.CRCIN33
CELL16.IMUX.IMUX38.DELAYCRC32_3.CRCIN2, CRC64_1.CRCIN34
CELL16.IMUX.IMUX39.DELAYCRC32_3.CRCIN3, CRC64_1.CRCIN35
CELL16.IMUX.IMUX40.DELAYCRC32_3.CRCIN4, CRC64_1.CRCIN36
CELL16.IMUX.IMUX42.DELAYGTX_DUAL.TXDATA015
CELL16.IMUX.IMUX43.DELAYGTX_DUAL.TXDATA014
CELL16.IMUX.IMUX44.DELAYGTX_DUAL.TXDATA013
CELL16.IMUX.IMUX45.DELAYGTX_DUAL.TXDATA012
CELL16.IMUX.IMUX47.DELAYGTX_DUAL.TXRESET0
CELL16.OUT0.TMINGTX_DUAL.RXNOTINTABLE02
CELL16.OUT1.TMINGTX_DUAL.RXCHARISCOMMA02
CELL16.OUT2.TMINGTX_DUAL.RXDATA020
CELL16.OUT3.TMINCRC32_3.CRCOUT1, CRC64_1.CRCOUT1
CELL16.OUT5.TMINGTX_DUAL.RXCLKCORCNT00
CELL16.OUT6.TMINGTX_DUAL.RXDATA021
CELL16.OUT7.TMINGTX_DUAL.RXSTATUS01
CELL16.OUT11.TMINGTX_DUAL.RXDATA022
CELL16.OUT12.TMINGTX_DUAL.RXDATA018
CELL16.OUT13.TMINCRC32_3.CRCOUT0, CRC64_1.CRCOUT0
CELL16.OUT14.TMINGTX_DUAL.RXSTATUS00
CELL16.OUT15.TMINCRC32_3.CRCOUT2, CRC64_1.CRCOUT2
CELL16.OUT16.TMINGTX_DUAL.RXDATA019
CELL16.OUT17.TMINGTX_DUAL.RXDATA023
CELL16.OUT18.TMINGTX_DUAL.TXRUNDISP03
CELL16.OUT19.TMINGTX_DUAL.RXRUNDISP02
CELL16.OUT20.TMINGTX_DUAL.RXCLKCORCNT02
CELL16.OUT21.TMINGTX_DUAL.RXSTATUS02
CELL16.OUT22.TMINGTX_DUAL.RXPRBSERR0
CELL16.OUT23.TMINGTX_DUAL.RXCLKCORCNT01
CELL17.IMUX.IMUX0.DELAYCRC32_3.CRCRESET, CRC64_1.CRCRESET
CELL17.IMUX.IMUX7.DELAYGTX_DUAL.TXCHARDISPMODE03
CELL17.IMUX.IMUX8.DELAYGTX_DUAL.TXCHARISK03
CELL17.IMUX.IMUX10.DELAYGTX_DUAL.TXPOWERDOWN00
CELL17.IMUX.IMUX11.DELAYGTX_DUAL.TXPOWERDOWN01
CELL17.IMUX.IMUX15.DELAYGTX_DUAL.TXPOLARITY0
CELL17.IMUX.IMUX20.DELAYGTX_DUAL.TXDATA027
CELL17.IMUX.IMUX21.DELAYGTX_DUAL.TXDATA026
CELL17.IMUX.IMUX22.DELAYGTX_DUAL.TXDATA025
CELL17.IMUX.IMUX23.DELAYGTX_DUAL.TXDATA024
CELL17.IMUX.IMUX25.DELAYGTX_DUAL.TXCHARDISPVAL03
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Bitstream

virtex5 GTX rect R0
BitFrame
virtex5 GTX rect R1
BitFrame
virtex5 GTX rect R2
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_0:CRC_INIT[12]
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virtex5 GTX rect R3
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_0:CRC_INIT[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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virtex5 GTX rect R4
BitFrame
virtex5 GTX rect R5
BitFrame
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B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_1[2] GTX_DUAL:DRP07[14] GTX_DUAL:CHAN_BOND_SEQ_2_4_1[3] GTX_DUAL:DRP07[15]
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B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[10] GTX_DUAL:PMA_RX_CFG_1[7] GTX_DUAL:DRP07[11] GTX_DUAL:PMA_RX_CFG_1[6]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[9] GTX_DUAL:PMA_RX_CFG_1[8] GTX_DUAL:DRP07[8] GTX_DUAL:PMA_RX_CFG_1[9]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[6] GTX_DUAL:PMA_RX_CFG_0[23] GTX_DUAL:DRP07[7] GTX_DUAL:PMA_RX_CFG_1[10]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[5] GTX_DUAL:PMA_RX_CFG_1[2] GTX_DUAL:DRP07[4] GTX_DUAL:PMA_RX_CFG_1[3]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[2] GTX_DUAL:PMA_RX_CFG_1[5] GTX_DUAL:DRP07[3] GTX_DUAL:PMA_RX_CFG_1[4]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP07[1] GTX_DUAL:RX_CDR_FORCE_ROTATE_1 GTX_DUAL:DRP07[0] GTX_DUAL:PMA_RX_CFG_1[13]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[14] GTX_DUAL:PMA_RX_CFG_1[15] GTX_DUAL:DRP06[15] GTX_DUAL:PMA_RX_CFG_1[14]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[13] GTX_DUAL:PMA_RX_CFG_1[16] GTX_DUAL:DRP06[12] GTX_DUAL:PMA_RX_CFG_1[17]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[10] GTX_DUAL:PMA_RX_CFG_1[19] GTX_DUAL:DRP06[11] GTX_DUAL:PMA_RX_CFG_1[18]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[9] GTX_DUAL:PMA_RX_CFG_1[20] GTX_DUAL:DRP06[8] GTX_DUAL:PMA_RX_CFG_1[21]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[6] GTX_DUAL:PMA_RX_CFG_0[11] GTX_DUAL:DRP06[7] GTX_DUAL:PMA_RX_CFG_1[22]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[5] GTX_DUAL:PMA_RX_CFG_0[0] GTX_DUAL:DRP06[4] GTX_DUAL:PMA_RX_CFG_0[1]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP06[2] GTX_DUAL:PMA_RX_CFG_0[12] GTX_DUAL:DRP06[3] GTX_DUAL:PMA_RX_CFG_0[24]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:AC_CAP_DIS_1 GTX_DUAL:DRP06[1] GTX_DUAL:DRP06[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[14] GTX_DUAL:RCV_TERM_VTTRX_1 GTX_DUAL:DRP05[15] GTX_DUAL:RCV_TERM_GND_1
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[13] GTX_DUAL:PMA_COM_CFG[22] GTX_DUAL:DRP05[12] GTX_DUAL:PMA_COM_CFG[23]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[10] GTX_DUAL:PMA_COM_CFG[25] GTX_DUAL:DRP05[11] GTX_DUAL:PMA_COM_CFG[24]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[9] GTX_DUAL:PMA_COM_CFG[26] GTX_DUAL:DRP05[8] GTX_DUAL:PMA_COM_CFG[21]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[6] GTX_DUAL:DRP05[7]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[5] GTX_DUAL:DRP05[4] GTX_DUAL:PLL_TXDIVSEL_OUT_1[0]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[2] GTX_DUAL:DRP05[3] GTX_DUAL:PLL_TXDIVSEL_OUT_1[1]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP05[1] GTX_DUAL:PLL_LKDET_CFG[0] GTX_DUAL:DRP05[0] GTX_DUAL:PLL_LKDET_CFG[1]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[14] GTX_DUAL:DRP04[15] GTX_DUAL:PLL_LKDET_CFG[2]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[13] GTX_DUAL:PLL_DIVSEL_REF[0] GTX_DUAL:DRP04[12] GTX_DUAL:PLL_DIVSEL_REF[4]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[10] GTX_DUAL:PLL_DIVSEL_REF[2] GTX_DUAL:DRP04[11] GTX_DUAL:PLL_DIVSEL_REF[3]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[9] GTX_DUAL:PLL_DIVSEL_REF[1] GTX_DUAL:DRP04[8] GTX_DUAL:MUX.CLKOUT_NORTH[0]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[6] GTX_DUAL:MUX.CLKIN[0] GTX_DUAL:DRP04[7] GTX_DUAL:MUX.CLKOUT_SOUTH[0]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[5] GTX_DUAL:MUX.CLKIN[1] GTX_DUAL:DRP04[4] GTX_DUAL:MUX.CLKIN[2]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[2] GTX_DUAL:CLKINDC_B GTX_DUAL:DRP04[3]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP04[1] GTX_DUAL:TX_IDLE_DELAY_1[0] GTX_DUAL:DRP04[0] GTX_DUAL:TX_IDLE_DELAY_1[1]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[14] GTX_DUAL:RX_EN_IDLE_HOLD_DFE_1 GTX_DUAL:DRP03[15] GTX_DUAL:TX_IDLE_DELAY_1[2]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[13] GTX_DUAL:DRP03[12] GTX_DUAL:RX_EN_IDLE_RESET_BUF_1
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[10] GTX_DUAL:DRP03[11]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[9] GTX_DUAL:RX_IDLE_HI_CNT_1[0] GTX_DUAL:DRP03[8] GTX_DUAL:RX_IDLE_HI_CNT_1[1]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[6] GTX_DUAL:RX_IDLE_HI_CNT_1[3] GTX_DUAL:DRP03[7] GTX_DUAL:RX_IDLE_HI_CNT_1[2]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[5] GTX_DUAL:DRP03[4] GTX_DUAL:RX_IDLE_LO_CNT_1[0]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[2] GTX_DUAL:RX_IDLE_LO_CNT_1[2] GTX_DUAL:DRP03[3] GTX_DUAL:RX_IDLE_LO_CNT_1[1]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP03[1] GTX_DUAL:RX_IDLE_LO_CNT_1[3] GTX_DUAL:CB2_INH_CC_PERIOD_1[0] GTX_DUAL:DRP03[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CB2_INH_CC_PERIOD_1[2] GTX_DUAL:DRP02[14] GTX_DUAL:CB2_INH_CC_PERIOD_1[1] GTX_DUAL:DRP02[15]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CB2_INH_CC_PERIOD_1[3] GTX_DUAL:DRP02[13] GTX_DUAL:CHAN_BOND_KEEP_ALIGN_1 GTX_DUAL:DRP02[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP02[10] GTX_DUAL:GEARBOX_ENDEC_1[1] GTX_DUAL:DRP02[11] GTX_DUAL:GEARBOX_ENDEC_1[0]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP02[9] GTX_DUAL:GEARBOX_ENDEC_1[2] GTX_DUAL:DRP02[8] GTX_DUAL:RXGEARBOX_USE_1
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[0] GTX_DUAL:DRP02[6] GTX_DUAL:DRP02[7] GTX_DUAL:TXGEARBOX_USE_1
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[1] GTX_DUAL:DRP02[5] GTX_DUAL:DFE_CFG_1[2] GTX_DUAL:DRP02[4]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[4] GTX_DUAL:DRP02[2] GTX_DUAL:DFE_CFG_1[3] GTX_DUAL:DRP02[3]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[5] GTX_DUAL:DRP02[1] GTX_DUAL:DFE_CFG_1[6] GTX_DUAL:DRP02[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[8] GTX_DUAL:DRP01[14] GTX_DUAL:DFE_CFG_1[7] GTX_DUAL:DRP01[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_1[9] GTX_DUAL:DRP01[13] GTX_DUAL:CM_TRIM_1[0] GTX_DUAL:DRP01[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[10] GTX_DUAL:PMA_TX_CFG_1[0] GTX_DUAL:CM_TRIM_1[1] GTX_DUAL:DRP01[11]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[9] GTX_DUAL:PMA_TX_CFG_1[1] GTX_DUAL:DRP01[8] GTX_DUAL:PMA_TX_CFG_1[2]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[6] GTX_DUAL:PMA_TX_CFG_1[4] GTX_DUAL:DRP01[7] GTX_DUAL:PMA_TX_CFG_1[3]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[5] GTX_DUAL:PMA_TX_CFG_1[5] GTX_DUAL:DRP01[4] GTX_DUAL:PMA_TX_CFG_1[6]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[2] GTX_DUAL:PMA_TX_CFG_1[8] GTX_DUAL:DRP01[3] GTX_DUAL:PMA_TX_CFG_1[7]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP01[1] GTX_DUAL:PMA_TX_CFG_1[9] GTX_DUAL:DRP01[0] GTX_DUAL:PMA_TX_CFG_1[10]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[14] GTX_DUAL:PMA_TX_CFG_1[12] GTX_DUAL:DRP00[15] GTX_DUAL:PMA_TX_CFG_1[11]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[13] GTX_DUAL:PMA_TX_CFG_1[13] GTX_DUAL:DRP00[12] GTX_DUAL:PMA_TX_CFG_1[14]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[10] GTX_DUAL:PMA_TX_CFG_1[16] GTX_DUAL:DRP00[11] GTX_DUAL:PMA_TX_CFG_1[15]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[9] GTX_DUAL:PMA_TX_CFG_1[17] GTX_DUAL:DRP00[8] GTX_DUAL:PMA_TX_CFG_1[18]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[6] GTX_DUAL:PMA_RXSYNC_CFG_1[0] GTX_DUAL:DRP00[7] GTX_DUAL:PMA_TX_CFG_1[19]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[5] GTX_DUAL:PMA_RXSYNC_CFG_1[1] GTX_DUAL:DRP00[4] GTX_DUAL:PMA_RXSYNC_CFG_1[2]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[2] GTX_DUAL:PMA_RXSYNC_CFG_1[4] GTX_DUAL:DRP00[3] GTX_DUAL:PMA_RXSYNC_CFG_1[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP00[1] GTX_DUAL:PMA_RXSYNC_CFG_1[5] GTX_DUAL:DRP00[0] GTX_DUAL:PMA_RXSYNC_CFG_1[6]
virtex5 GTX rect R6
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[14] GTX_DUAL:SATA_MAX_WAKE_1[1] GTX_DUAL:DRP0F[15] GTX_DUAL:SATA_MAX_WAKE_1[0]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[13] GTX_DUAL:SATA_MAX_WAKE_1[2] GTX_DUAL:DRP0F[12] GTX_DUAL:SATA_MAX_WAKE_1[3]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[10] GTX_DUAL:SATA_MAX_WAKE_1[5] GTX_DUAL:DRP0F[11] GTX_DUAL:SATA_MAX_WAKE_1[4]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[9] GTX_DUAL:SATA_MAX_INIT_1[0] GTX_DUAL:DRP0F[8] GTX_DUAL:SATA_MAX_INIT_1[1]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[6] GTX_DUAL:SATA_MAX_INIT_1[3] GTX_DUAL:DRP0F[7] GTX_DUAL:SATA_MAX_INIT_1[2]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[5] GTX_DUAL:SATA_MAX_INIT_1[4] GTX_DUAL:DRP0F[4] GTX_DUAL:SATA_MAX_INIT_1[5]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[2] GTX_DUAL:SATA_MAX_BURST_1[1] GTX_DUAL:DRP0F[3] GTX_DUAL:SATA_MAX_BURST_1[0]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0F[1] GTX_DUAL:SATA_MAX_BURST_1[2] GTX_DUAL:DRP0F[0] GTX_DUAL:SATA_MAX_BURST_1[3]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[14] GTX_DUAL:SATA_MAX_BURST_1[5] GTX_DUAL:DRP0E[15] GTX_DUAL:SATA_MAX_BURST_1[4]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[13] GTX_DUAL:SATA_IDLE_VAL_1[0] GTX_DUAL:DRP0E[12] GTX_DUAL:SATA_IDLE_VAL_1[1]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[10] GTX_DUAL:SATA_BURST_VAL_1[0] GTX_DUAL:DRP0E[11] GTX_DUAL:SATA_IDLE_VAL_1[2]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[9] GTX_DUAL:SATA_BURST_VAL_1[1] GTX_DUAL:DRP0E[8] GTX_DUAL:SATA_BURST_VAL_1[2]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[6] GTX_DUAL:RX_STATUS_FMT_1[0] GTX_DUAL:DRP0E[7] GTX_DUAL:RX_XCLK_SEL_1[0]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[5] GTX_DUAL:RX_SLIDE_MODE_1[0] GTX_DUAL:DRP0E[4] GTX_DUAL:RX_LOS_THRESHOLD_1[0]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[2] GTX_DUAL:RX_LOS_THRESHOLD_1[2] GTX_DUAL:DRP0E[3] GTX_DUAL:RX_LOS_THRESHOLD_1[1]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0E[1] GTX_DUAL:RX_LOSS_OF_SYNC_FSM_1 GTX_DUAL:DRP0E[0] GTX_DUAL:RX_LOS_INVALID_INCR_1[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[14] GTX_DUAL:RX_LOS_INVALID_INCR_1[2] GTX_DUAL:DRP0D[15] GTX_DUAL:RX_LOS_INVALID_INCR_1[1]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[13] GTX_DUAL:RX_DECODE_SEQ_MATCH_1 GTX_DUAL:DRP0D[12] GTX_DUAL:RX_BUFFER_USE_1
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[10] GTX_DUAL:PRBS_ERR_THRESHOLD_1[1] GTX_DUAL:DRP0D[11] GTX_DUAL:PRBS_ERR_THRESHOLD_1[0]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[9] GTX_DUAL:PRBS_ERR_THRESHOLD_1[2] GTX_DUAL:DRP0D[8] GTX_DUAL:PRBS_ERR_THRESHOLD_1[3]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[6] GTX_DUAL:PRBS_ERR_THRESHOLD_1[5] GTX_DUAL:DRP0D[7] GTX_DUAL:PRBS_ERR_THRESHOLD_1[4]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[5] GTX_DUAL:PRBS_ERR_THRESHOLD_1[6] GTX_DUAL:DRP0D[4] GTX_DUAL:PRBS_ERR_THRESHOLD_1[7]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[2] GTX_DUAL:PRBS_ERR_THRESHOLD_1[9] GTX_DUAL:DRP0D[3] GTX_DUAL:PRBS_ERR_THRESHOLD_1[8]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0D[1] GTX_DUAL:PRBS_ERR_THRESHOLD_1[10] GTX_DUAL:DRP0D[0] GTX_DUAL:PRBS_ERR_THRESHOLD_1[11]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[14] GTX_DUAL:PRBS_ERR_THRESHOLD_1[13] GTX_DUAL:DRP0C[15] GTX_DUAL:PRBS_ERR_THRESHOLD_1[12]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[13] GTX_DUAL:PRBS_ERR_THRESHOLD_1[14] GTX_DUAL:DRP0C[12] GTX_DUAL:PRBS_ERR_THRESHOLD_1[15]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[10] GTX_DUAL:PRBS_ERR_THRESHOLD_1[17] GTX_DUAL:DRP0C[11] GTX_DUAL:PRBS_ERR_THRESHOLD_1[16]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[9] GTX_DUAL:PRBS_ERR_THRESHOLD_1[18] GTX_DUAL:DRP0C[8] GTX_DUAL:PRBS_ERR_THRESHOLD_1[19]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[6] GTX_DUAL:PRBS_ERR_THRESHOLD_1[21] GTX_DUAL:DRP0C[7] GTX_DUAL:PRBS_ERR_THRESHOLD_1[20]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[5] GTX_DUAL:PRBS_ERR_THRESHOLD_1[22] GTX_DUAL:DRP0C[4] GTX_DUAL:PRBS_ERR_THRESHOLD_1[23]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[2] GTX_DUAL:PRBS_ERR_THRESHOLD_1[25] GTX_DUAL:DRP0C[3] GTX_DUAL:PRBS_ERR_THRESHOLD_1[24]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0C[1] GTX_DUAL:PRBS_ERR_THRESHOLD_1[26] GTX_DUAL:DRP0C[0] GTX_DUAL:PRBS_ERR_THRESHOLD_1[27]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[14] GTX_DUAL:PRBS_ERR_THRESHOLD_1[29] GTX_DUAL:DRP0B[15] GTX_DUAL:PRBS_ERR_THRESHOLD_1[28]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[13] GTX_DUAL:PRBS_ERR_THRESHOLD_1[30] GTX_DUAL:DRP0B[12] GTX_DUAL:PRBS_ERR_THRESHOLD_1[31]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[10] GTX_DUAL:PMA_CDR_SCAN_1[1] GTX_DUAL:DRP0B[11] GTX_DUAL:PMA_CDR_SCAN_1[0]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[9] GTX_DUAL:PMA_CDR_SCAN_1[2] GTX_DUAL:DRP0B[8] GTX_DUAL:PMA_CDR_SCAN_1[3]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[6] GTX_DUAL:PMA_CDR_SCAN_1[5] GTX_DUAL:DRP0B[7] GTX_DUAL:PMA_CDR_SCAN_1[4]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[5] GTX_DUAL:PMA_CDR_SCAN_1[6] GTX_DUAL:DRP0B[4] GTX_DUAL:PMA_CDR_SCAN_1[7]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[2] GTX_DUAL:PMA_CDR_SCAN_1[9] GTX_DUAL:DRP0B[3] GTX_DUAL:PMA_CDR_SCAN_1[8]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0B[1] GTX_DUAL:PMA_CDR_SCAN_1[10] GTX_DUAL:DRP0B[0] GTX_DUAL:PMA_CDR_SCAN_1[11]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[14] GTX_DUAL:PMA_CDR_SCAN_1[13] GTX_DUAL:DRP0A[15] GTX_DUAL:PMA_CDR_SCAN_1[12]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[13] GTX_DUAL:PMA_CDR_SCAN_1[14] GTX_DUAL:DRP0A[12] GTX_DUAL:PMA_CDR_SCAN_1[15]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[10] GTX_DUAL:PMA_CDR_SCAN_1[17] GTX_DUAL:DRP0A[11] GTX_DUAL:PMA_CDR_SCAN_1[16]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[9] GTX_DUAL:PMA_CDR_SCAN_1[18] GTX_DUAL:DRP0A[8] GTX_DUAL:PMA_CDR_SCAN_1[19]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[6] GTX_DUAL:PMA_CDR_SCAN_1[21] GTX_DUAL:DRP0A[7] GTX_DUAL:PMA_CDR_SCAN_1[20]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[5] GTX_DUAL:PMA_CDR_SCAN_1[22] GTX_DUAL:DRP0A[4] GTX_DUAL:PMA_CDR_SCAN_1[23]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[2] GTX_DUAL:PMA_CDR_SCAN_1[25] GTX_DUAL:DRP0A[3] GTX_DUAL:PMA_CDR_SCAN_1[24]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP0A[1] GTX_DUAL:PMA_CDR_SCAN_1[26] GTX_DUAL:DRP0A[0] GTX_DUAL:PLL_RXDIVSEL_OUT_1[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[14] GTX_DUAL:PLL_SATA_1 GTX_DUAL:DRP09[15] GTX_DUAL:PLL_RXDIVSEL_OUT_1[1]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[13] GTX_DUAL:CLKRCV_TRST GTX_DUAL:DRP09[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[10] GTX_DUAL:PCOMMA_10B_VALUE_1[0] GTX_DUAL:DRP09[11] GTX_DUAL:PCOMMA_DETECT_1
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[9] GTX_DUAL:PCOMMA_10B_VALUE_1[1] GTX_DUAL:DRP09[8] GTX_DUAL:PCOMMA_10B_VALUE_1[2]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[6] GTX_DUAL:PCOMMA_10B_VALUE_1[4] GTX_DUAL:DRP09[7] GTX_DUAL:PCOMMA_10B_VALUE_1[3]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[5] GTX_DUAL:PCOMMA_10B_VALUE_1[5] GTX_DUAL:DRP09[4] GTX_DUAL:PCOMMA_10B_VALUE_1[6]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[2] GTX_DUAL:PCOMMA_10B_VALUE_1[8] GTX_DUAL:DRP09[3] GTX_DUAL:PCOMMA_10B_VALUE_1[7]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP09[1] GTX_DUAL:PCOMMA_10B_VALUE_1[9] GTX_DUAL:DRP09[0] GTX_DUAL:PCI_EXPRESS_MODE_1
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_1[8] GTX_DUAL:DRP08[14] GTX_DUAL:DRP08[15]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_1[7] GTX_DUAL:DRP08[13] GTX_DUAL:CHAN_BOND_SEQ_2_3_1[6] GTX_DUAL:DRP08[12]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_1[4] GTX_DUAL:DRP08[10] GTX_DUAL:CHAN_BOND_SEQ_2_3_1[5] GTX_DUAL:DRP08[11]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_1[3] GTX_DUAL:DRP08[9] GTX_DUAL:CHAN_BOND_SEQ_2_3_1[2] GTX_DUAL:DRP08[8]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_1[0] GTX_DUAL:DRP08[6] GTX_DUAL:CHAN_BOND_SEQ_2_3_1[1] GTX_DUAL:DRP08[7]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_1[9] GTX_DUAL:DRP08[5] GTX_DUAL:CHAN_BOND_SEQ_2_4_1[8] GTX_DUAL:DRP08[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_1[6] GTX_DUAL:DRP08[2] GTX_DUAL:CHAN_BOND_SEQ_2_4_1[7] GTX_DUAL:DRP08[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_1[5] GTX_DUAL:DRP08[1] GTX_DUAL:CHAN_BOND_SEQ_2_4_1[4] GTX_DUAL:DRP08[0]
virtex5 GTX rect R7
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_1[9] GTX_DUAL:DRP17[14] GTX_DUAL:CLK_COR_SEQ_1_1_1[8] GTX_DUAL:DRP17[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_1[0] GTX_DUAL:DRP17[13] GTX_DUAL:CLK_COR_REPEAT_WAIT_1[1] GTX_DUAL:DRP17[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_1[3] GTX_DUAL:DRP17[10] GTX_DUAL:CLK_COR_REPEAT_WAIT_1[2] GTX_DUAL:DRP17[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_1[4] GTX_DUAL:DRP17[9] GTX_DUAL:CLK_CORRECT_USE_1 GTX_DUAL:DRP17[8]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_1[0] GTX_DUAL:DRP17[6] GTX_DUAL:CLK_COR_PRECEDENCE_1 GTX_DUAL:DRP17[7]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_1[1] GTX_DUAL:DRP17[5] GTX_DUAL:CLK_COR_MIN_LAT_1[2] GTX_DUAL:DRP17[4]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_1[4] GTX_DUAL:DRP17[2] GTX_DUAL:CLK_COR_MIN_LAT_1[3] GTX_DUAL:DRP17[3]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_1[5] GTX_DUAL:DRP17[1] GTX_DUAL:CLK_COR_MAX_LAT_1[0] GTX_DUAL:DRP17[0]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MAX_LAT_1[2] GTX_DUAL:DRP16[14] GTX_DUAL:CLK_COR_MAX_LAT_1[1] GTX_DUAL:DRP16[15]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MAX_LAT_1[3] GTX_DUAL:DRP16[13] GTX_DUAL:CLK_COR_MAX_LAT_1[4] GTX_DUAL:DRP16[12]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_KEEP_IDLE_1 GTX_DUAL:DRP16[10] GTX_DUAL:CLK_COR_MAX_LAT_1[5] GTX_DUAL:DRP16[11]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_1 GTX_DUAL:DRP16[9] GTX_DUAL:CLK_COR_DET_LEN_1[0] GTX_DUAL:DRP16[8]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_ADJ_LEN_1[0] GTX_DUAL:DRP16[6] GTX_DUAL:CLK_COR_DET_LEN_1[1] GTX_DUAL:DRP16[7]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_ADJ_LEN_1[1] GTX_DUAL:DRP16[5] GTX_DUAL:CHAN_BOND_SEQ_LEN_1[0] GTX_DUAL:DRP16[4]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_USE_1 GTX_DUAL:DRP16[2] GTX_DUAL:CHAN_BOND_SEQ_LEN_1[1] GTX_DUAL:DRP16[3]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[0] GTX_DUAL:DRP16[1] GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[1] GTX_DUAL:DRP16[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[3] GTX_DUAL:DRP15[14] GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1[2] GTX_DUAL:DRP15[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[13] GTX_DUAL:PMA_COM_CFG[8] GTX_DUAL:DRP15[12] GTX_DUAL:OOBDETECT_THRESHOLD_1[0]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[10] GTX_DUAL:OOBDETECT_THRESHOLD_1[2] GTX_DUAL:DRP15[11] GTX_DUAL:OOBDETECT_THRESHOLD_1[1]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[9] GTX_DUAL:DRP15[8] GTX_DUAL:TXOUTCLK_SEL_1
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[6] GTX_DUAL:DRP15[7] GTX_DUAL:TX_XCLK_SEL_1[0]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[5] GTX_DUAL:DRP15[4] GTX_DUAL:TXRX_INVERT_1[0]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[2] GTX_DUAL:TXRX_INVERT_1[2] GTX_DUAL:DRP15[3] GTX_DUAL:TXRX_INVERT_1[1]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP15[1] GTX_DUAL:TX_DETECT_RX_CFG_1[0] GTX_DUAL:DRP15[0] GTX_DUAL:TX_DETECT_RX_CFG_1[1]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[14] GTX_DUAL:TX_DETECT_RX_CFG_1[3] GTX_DUAL:DRP14[15] GTX_DUAL:TX_DETECT_RX_CFG_1[2]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[13] GTX_DUAL:TX_DETECT_RX_CFG_1[4] GTX_DUAL:DRP14[12] GTX_DUAL:TX_DETECT_RX_CFG_1[5]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[10] GTX_DUAL:TX_DETECT_RX_CFG_1[7] GTX_DUAL:DRP14[11] GTX_DUAL:TX_DETECT_RX_CFG_1[6]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[9] GTX_DUAL:TX_DETECT_RX_CFG_1[8] GTX_DUAL:DRP14[8] GTX_DUAL:TX_DETECT_RX_CFG_1[9]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[6] GTX_DUAL:TX_DETECT_RX_CFG_1[11] GTX_DUAL:DRP14[7] GTX_DUAL:TX_DETECT_RX_CFG_1[10]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[5] GTX_DUAL:TX_DETECT_RX_CFG_1[12] GTX_DUAL:DRP14[4] GTX_DUAL:TX_DETECT_RX_CFG_1[13]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[2] GTX_DUAL:PLL_COM_CFG[23] GTX_DUAL:DRP14[3] GTX_DUAL:TX_BUFFER_USE_1
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP14[1] GTX_DUAL:PLL_COM_CFG[22] GTX_DUAL:DRP14[0] GTX_DUAL:PLL_COM_CFG[21]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[14] GTX_DUAL:DRP13[15] GTX_DUAL:PLL_COM_CFG[20]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[13] GTX_DUAL:DRP13[12] GTX_DUAL:TRANS_TIME_TO_P2_1[0]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[10] GTX_DUAL:TRANS_TIME_TO_P2_1[2] GTX_DUAL:DRP13[11] GTX_DUAL:TRANS_TIME_TO_P2_1[1]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[9] GTX_DUAL:TRANS_TIME_TO_P2_1[3] GTX_DUAL:DRP13[8] GTX_DUAL:TRANS_TIME_TO_P2_1[4]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[6] GTX_DUAL:TRANS_TIME_TO_P2_1[6] GTX_DUAL:DRP13[7] GTX_DUAL:TRANS_TIME_TO_P2_1[5]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[5] GTX_DUAL:TRANS_TIME_TO_P2_1[7] GTX_DUAL:DRP13[4] GTX_DUAL:TRANS_TIME_TO_P2_1[8]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[2] GTX_DUAL:DRP13[3] GTX_DUAL:TRANS_TIME_TO_P2_1[9]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP13[1] GTX_DUAL:DRP13[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[14] GTX_DUAL:DRP12[15]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[13] GTX_DUAL:DRP12[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[10] GTX_DUAL:TRANS_TIME_NON_P2_1[0] GTX_DUAL:DRP12[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[9] GTX_DUAL:TRANS_TIME_NON_P2_1[1] GTX_DUAL:DRP12[8] GTX_DUAL:TRANS_TIME_NON_P2_1[2]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[6] GTX_DUAL:TRANS_TIME_NON_P2_1[4] GTX_DUAL:DRP12[7] GTX_DUAL:TRANS_TIME_NON_P2_1[3]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[5] GTX_DUAL:TRANS_TIME_NON_P2_1[5] GTX_DUAL:DRP12[4] GTX_DUAL:TRANS_TIME_NON_P2_1[6]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[2] GTX_DUAL:DRP12[3] GTX_DUAL:TRANS_TIME_NON_P2_1[7]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP12[1] GTX_DUAL:DRP12[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[14] GTX_DUAL:TRANS_TIME_FROM_P2_1[0] GTX_DUAL:DRP11[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[13] GTX_DUAL:TRANS_TIME_FROM_P2_1[1] GTX_DUAL:DRP11[12] GTX_DUAL:TRANS_TIME_FROM_P2_1[2]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[10] GTX_DUAL:TRANS_TIME_FROM_P2_1[4] GTX_DUAL:DRP11[11] GTX_DUAL:TRANS_TIME_FROM_P2_1[3]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[9] GTX_DUAL:TRANS_TIME_FROM_P2_1[5] GTX_DUAL:DRP11[8] GTX_DUAL:TRANS_TIME_FROM_P2_1[6]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[6] GTX_DUAL:TRANS_TIME_FROM_P2_1[8] GTX_DUAL:DRP11[7] GTX_DUAL:TRANS_TIME_FROM_P2_1[7]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[5] GTX_DUAL:TRANS_TIME_FROM_P2_1[9] GTX_DUAL:DRP11[4] GTX_DUAL:TRANS_TIME_FROM_P2_1[10]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[2] GTX_DUAL:TERMINATION_IMP_1[0] GTX_DUAL:DRP11[3] GTX_DUAL:TRANS_TIME_FROM_P2_1[11]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP11[1] GTX_DUAL:SATA_MIN_WAKE_1[0] GTX_DUAL:DRP11[0] GTX_DUAL:SATA_MIN_WAKE_1[1]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[14] GTX_DUAL:SATA_MIN_WAKE_1[3] GTX_DUAL:DRP10[15] GTX_DUAL:SATA_MIN_WAKE_1[2]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[13] GTX_DUAL:SATA_MIN_WAKE_1[4] GTX_DUAL:DRP10[12] GTX_DUAL:SATA_MIN_WAKE_1[5]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[10] GTX_DUAL:SATA_MIN_INIT_1[1] GTX_DUAL:DRP10[11] GTX_DUAL:SATA_MIN_INIT_1[0]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[9] GTX_DUAL:SATA_MIN_INIT_1[2] GTX_DUAL:DRP10[8] GTX_DUAL:SATA_MIN_INIT_1[3]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[6] GTX_DUAL:SATA_MIN_INIT_1[5] GTX_DUAL:DRP10[7] GTX_DUAL:SATA_MIN_INIT_1[4]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[5] GTX_DUAL:SATA_MIN_BURST_1[0] GTX_DUAL:DRP10[4] GTX_DUAL:SATA_MIN_BURST_1[1]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[2] GTX_DUAL:SATA_MIN_BURST_1[3] GTX_DUAL:DRP10[3] GTX_DUAL:SATA_MIN_BURST_1[2]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP10[1] GTX_DUAL:SATA_MIN_BURST_1[4] GTX_DUAL:DRP10[0] GTX_DUAL:SATA_MIN_BURST_1[5]
virtex5 GTX rect R8
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[28] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[8] GTX_DUAL:DRP1F[14] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[9] GTX_DUAL:DRP1F[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[29] - GTX_DUAL:DRP1F[13] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[7] GTX_DUAL:DRP1F[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[30] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[5] GTX_DUAL:DRP1F[10] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[6] GTX_DUAL:DRP1F[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[31] - GTX_DUAL:CHAN_BOND_SEQ_2_2_1[4] GTX_DUAL:DRP1F[9] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[3] GTX_DUAL:DRP1F[8]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_2_1[1] GTX_DUAL:DRP1F[6] GTX_DUAL:CHAN_BOND_SEQ_2_2_1[2] GTX_DUAL:DRP1F[7]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_2_1[0] GTX_DUAL:DRP1F[5] GTX_DUAL:CHAN_BOND_SEQ_2_3_1[9] GTX_DUAL:DRP1F[4]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1F[2] GTX_DUAL:MCOMMA_10B_VALUE_1[0] GTX_DUAL:DRP1F[3] GTX_DUAL:MCOMMA_DETECT_1
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1F[1] GTX_DUAL:MCOMMA_10B_VALUE_1[1] GTX_DUAL:DRP1F[0] GTX_DUAL:MCOMMA_10B_VALUE_1[2]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1E[14] GTX_DUAL:MCOMMA_10B_VALUE_1[4] GTX_DUAL:DRP1E[15] GTX_DUAL:MCOMMA_10B_VALUE_1[3]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1E[13] GTX_DUAL:MCOMMA_10B_VALUE_1[5] GTX_DUAL:DRP1E[12] GTX_DUAL:MCOMMA_10B_VALUE_1[6]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1E[10] GTX_DUAL:MCOMMA_10B_VALUE_1[8] GTX_DUAL:DRP1E[11] GTX_DUAL:MCOMMA_10B_VALUE_1[7]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP1E[9] GTX_DUAL:MCOMMA_10B_VALUE_1[9] GTX_DUAL:DEC_VALID_COMMA_ONLY_1 GTX_DUAL:DRP1E[8]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DEC_MCOMMA_DETECT_1 GTX_DUAL:DRP1E[6] GTX_DUAL:DEC_PCOMMA_DETECT_1 GTX_DUAL:DRP1E[7]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_DOUBLE_1 GTX_DUAL:DRP1E[5] GTX_DUAL:COMMA_10B_ENABLE_1[0] GTX_DUAL:DRP1E[4]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_1[2] GTX_DUAL:DRP1E[2] GTX_DUAL:COMMA_10B_ENABLE_1[1] GTX_DUAL:DRP1E[3]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_1[3] GTX_DUAL:DRP1E[1] GTX_DUAL:COMMA_10B_ENABLE_1[4] GTX_DUAL:DRP1E[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_1[6] GTX_DUAL:DRP1D[14] GTX_DUAL:COMMA_10B_ENABLE_1[5] GTX_DUAL:DRP1D[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_1[7] GTX_DUAL:DRP1D[13] GTX_DUAL:COMMA_10B_ENABLE_1[8] GTX_DUAL:DRP1D[12]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COM_BURST_VAL_1[0] GTX_DUAL:DRP1D[10] GTX_DUAL:COMMA_10B_ENABLE_1[9] GTX_DUAL:DRP1D[11]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COM_BURST_VAL_1[1] GTX_DUAL:DRP1D[9] GTX_DUAL:COM_BURST_VAL_1[2] GTX_DUAL:DRP1D[8]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_USE_1 GTX_DUAL:DRP1D[6] GTX_DUAL:COM_BURST_VAL_1[3] GTX_DUAL:DRP1D[7]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[0] GTX_DUAL:DRP1D[5] GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[1] GTX_DUAL:DRP1D[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[3] GTX_DUAL:DRP1D[2] GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1[2] GTX_DUAL:DRP1D[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_1[0] GTX_DUAL:DRP1D[1] GTX_DUAL:CLK_COR_SEQ_2_4_1[1] GTX_DUAL:DRP1D[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_1[3] GTX_DUAL:DRP1C[14] GTX_DUAL:CLK_COR_SEQ_2_4_1[2] GTX_DUAL:DRP1C[15]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_1[4] GTX_DUAL:DRP1C[13] GTX_DUAL:CLK_COR_SEQ_2_4_1[5] GTX_DUAL:DRP1C[12]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_1[7] GTX_DUAL:DRP1C[10] GTX_DUAL:CLK_COR_SEQ_2_4_1[6] GTX_DUAL:DRP1C[11]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_1[8] GTX_DUAL:DRP1C[9] GTX_DUAL:CLK_COR_SEQ_2_4_1[9] GTX_DUAL:DRP1C[8]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_1[1] GTX_DUAL:DRP1C[6] GTX_DUAL:CLK_COR_SEQ_2_3_1[0] GTX_DUAL:DRP1C[7]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_1[2] GTX_DUAL:DRP1C[5] GTX_DUAL:CLK_COR_SEQ_2_3_1[3] GTX_DUAL:DRP1C[4]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_1[5] GTX_DUAL:DRP1C[2] GTX_DUAL:CLK_COR_SEQ_2_3_1[4] GTX_DUAL:DRP1C[3]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_1[6] GTX_DUAL:DRP1C[1] GTX_DUAL:CLK_COR_SEQ_2_3_1[7] GTX_DUAL:DRP1C[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_1[9] GTX_DUAL:DRP1B[14] GTX_DUAL:CLK_COR_SEQ_2_3_1[8] GTX_DUAL:DRP1B[15]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_1[0] GTX_DUAL:DRP1B[13] GTX_DUAL:CLK_COR_SEQ_2_2_1[1] GTX_DUAL:DRP1B[12]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_1[3] GTX_DUAL:DRP1B[10] GTX_DUAL:CLK_COR_SEQ_2_2_1[2] GTX_DUAL:DRP1B[11]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_1[4] GTX_DUAL:DRP1B[9] GTX_DUAL:CLK_COR_SEQ_2_2_1[5] GTX_DUAL:DRP1B[8]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_1[7] GTX_DUAL:DRP1B[6] GTX_DUAL:CLK_COR_SEQ_2_2_1[6] GTX_DUAL:DRP1B[7]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_1[8] GTX_DUAL:DRP1B[5] GTX_DUAL:CLK_COR_SEQ_2_2_1[9] GTX_DUAL:DRP1B[4]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_1[1] GTX_DUAL:DRP1B[2] GTX_DUAL:CLK_COR_SEQ_2_1_1[0] GTX_DUAL:DRP1B[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_1[2] GTX_DUAL:DRP1B[1] GTX_DUAL:CLK_COR_SEQ_2_1_1[3] GTX_DUAL:DRP1B[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_1[5] GTX_DUAL:DRP1A[14] GTX_DUAL:CLK_COR_SEQ_2_1_1[4] GTX_DUAL:DRP1A[15]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_1[6] GTX_DUAL:DRP1A[13] GTX_DUAL:CLK_COR_SEQ_2_1_1[7] GTX_DUAL:DRP1A[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_1[9] GTX_DUAL:DRP1A[10] GTX_DUAL:CLK_COR_SEQ_2_1_1[8] GTX_DUAL:DRP1A[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[0] GTX_DUAL:DRP1A[9] GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[1] GTX_DUAL:DRP1A[8]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[3] GTX_DUAL:DRP1A[6] GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1[2] GTX_DUAL:DRP1A[7]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_1[0] GTX_DUAL:DRP1A[5] GTX_DUAL:CLK_COR_SEQ_1_4_1[1] GTX_DUAL:DRP1A[4]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_1[3] GTX_DUAL:DRP1A[2] GTX_DUAL:CLK_COR_SEQ_1_4_1[2] GTX_DUAL:DRP1A[3]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_1[4] GTX_DUAL:DRP1A[1] GTX_DUAL:CLK_COR_SEQ_1_4_1[5] GTX_DUAL:DRP1A[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_1[7] GTX_DUAL:DRP19[14] GTX_DUAL:CLK_COR_SEQ_1_4_1[6] GTX_DUAL:DRP19[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_1[8] GTX_DUAL:DRP19[13] GTX_DUAL:CLK_COR_SEQ_1_4_1[9] GTX_DUAL:DRP19[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_1[1] GTX_DUAL:DRP19[10] GTX_DUAL:CLK_COR_SEQ_1_3_1[0] GTX_DUAL:DRP19[11]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_1[2] GTX_DUAL:DRP19[9] GTX_DUAL:CLK_COR_SEQ_1_3_1[3] GTX_DUAL:DRP19[8]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_1[5] GTX_DUAL:DRP19[6] GTX_DUAL:CLK_COR_SEQ_1_3_1[4] GTX_DUAL:DRP19[7]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_1[6] GTX_DUAL:DRP19[5] GTX_DUAL:CLK_COR_SEQ_1_3_1[7] GTX_DUAL:DRP19[4]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_1[9] GTX_DUAL:DRP19[2] GTX_DUAL:CLK_COR_SEQ_1_3_1[8] GTX_DUAL:DRP19[3]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_1[0] GTX_DUAL:DRP19[1] GTX_DUAL:CLK_COR_SEQ_1_2_1[1] GTX_DUAL:DRP19[0]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_1[3] GTX_DUAL:DRP18[14] GTX_DUAL:CLK_COR_SEQ_1_2_1[2] GTX_DUAL:DRP18[15]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_1[4] GTX_DUAL:DRP18[13] GTX_DUAL:CLK_COR_SEQ_1_2_1[5] GTX_DUAL:DRP18[12]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_1[7] GTX_DUAL:DRP18[10] GTX_DUAL:CLK_COR_SEQ_1_2_1[6] GTX_DUAL:DRP18[11]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_1[8] GTX_DUAL:DRP18[9] GTX_DUAL:CLK_COR_SEQ_1_2_1[9] GTX_DUAL:DRP18[8]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_1[1] GTX_DUAL:DRP18[6] GTX_DUAL:CLK_COR_SEQ_1_1_1[0] GTX_DUAL:DRP18[7]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_1[2] GTX_DUAL:DRP18[5] GTX_DUAL:CLK_COR_SEQ_1_1_1[3] GTX_DUAL:DRP18[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_1[5] GTX_DUAL:DRP18[2] GTX_DUAL:CLK_COR_SEQ_1_1_1[4] GTX_DUAL:DRP18[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_1[6] GTX_DUAL:DRP18[1] GTX_DUAL:CLK_COR_SEQ_1_1_1[7] GTX_DUAL:DRP18[0]
virtex5 GTX rect R9
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[14] GTX_DUAL:PLL_COM_CFG[5] GTX_DUAL:DRP27[15] GTX_DUAL:PLL_COM_CFG[4]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[13] GTX_DUAL:PLL_COM_CFG[6] GTX_DUAL:DRP27[12] GTX_DUAL:PLL_COM_CFG[7]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[10] GTX_DUAL:PLL_COM_CFG[9] GTX_DUAL:DRP27[11] GTX_DUAL:PLL_COM_CFG[8]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[9] GTX_DUAL:PLL_COM_CFG[10] GTX_DUAL:DRP27[8] GTX_DUAL:PLL_COM_CFG[11]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[6] GTX_DUAL:PLL_COM_CFG[13] GTX_DUAL:DRP27[7] GTX_DUAL:PLL_COM_CFG[12]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[5] GTX_DUAL:PLL_COM_CFG[14] GTX_DUAL:DRP27[4] GTX_DUAL:PLL_COM_CFG[15]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[2] GTX_DUAL:PLL_COM_CFG[17] GTX_DUAL:DRP27[3] GTX_DUAL:PLL_COM_CFG[16]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP27[1] GTX_DUAL:PLL_COM_CFG[18] GTX_DUAL:DRP27[0] GTX_DUAL:PLL_COM_CFG[19]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[14] GTX_DUAL:OOB_CLK_DIVIDER[0] GTX_DUAL:DRP26[15] GTX_DUAL:OVERSAMPLE_MODE
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[13] GTX_DUAL:OOB_CLK_DIVIDER[1] GTX_DUAL:DRP26[12] GTX_DUAL:OOB_CLK_DIVIDER[2]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK25_DIVIDER[1] GTX_DUAL:DRP26[10] GTX_DUAL:CLK25_DIVIDER[0] GTX_DUAL:DRP26[11]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK25_DIVIDER[2] GTX_DUAL:DRP26[9] GTX_DUAL:DRP26[8] GTX_DUAL:PMA_COM_CFG[48]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[6] GTX_DUAL:PMA_COM_CFG[44] GTX_DUAL:DRP26[7] GTX_DUAL:PMA_COM_CFG[46]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[5] GTX_DUAL:PMA_COM_CFG[42] GTX_DUAL:DRP26[4] GTX_DUAL:PMA_COM_CFG[38]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[2] GTX_DUAL:PMA_COM_CFG[36] GTX_DUAL:DRP26[3] GTX_DUAL:PMA_COM_CFG[40]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP26[1] GTX_DUAL:PMA_COM_CFG[34] GTX_DUAL:DRP26[0] GTX_DUAL:PMA_COM_CFG[56]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[14] GTX_DUAL:PMA_COM_CFG[64] GTX_DUAL:DRP25[15] GTX_DUAL:PMA_COM_CFG[54]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[13] GTX_DUAL:PMA_COM_CFG[62] GTX_DUAL:DRP25[12] GTX_DUAL:PMA_COM_CFG[61]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[10] GTX_DUAL:PMA_COM_CFG[68] GTX_DUAL:DRP25[11] GTX_DUAL:PMA_COM_CFG[63]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[9] GTX_DUAL:PMA_COM_CFG[66] GTX_DUAL:DRP25[8]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[6] GTX_DUAL:DRP25[7]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[5] GTX_DUAL:DRP25[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[2] GTX_DUAL:PMA_COM_CFG[50] GTX_DUAL:DRP25[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP25[1] GTX_DUAL:PMA_COM_CFG[52] GTX_DUAL:DRP25[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[14] GTX_DUAL:DRP24[15]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[13] GTX_DUAL:DRP24[12] GTX_DUAL:PMA_COM_CFG[10]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[10] GTX_DUAL:PMA_COM_CFG[12] GTX_DUAL:DRP24[11] GTX_DUAL:PMA_COM_CFG[11]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[9] GTX_DUAL:PMA_COM_CFG[13] GTX_DUAL:DRP24[8] GTX_DUAL:PMA_COM_CFG[14]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[6] GTX_DUAL:PMA_COM_CFG[16] GTX_DUAL:DRP24[7] GTX_DUAL:PMA_COM_CFG[15]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP24[5] GTX_DUAL:PMA_COM_CFG[17] GTX_DUAL:DRP24[4] GTX_DUAL:PMA_COM_CFG[18]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[3] GTX_DUAL:DRP24[2] GTX_DUAL:ALIGN_COMMA_WORD_1[0] GTX_DUAL:DRP24[3]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[2] GTX_DUAL:DRP24[1] GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[1] GTX_DUAL:DRP24[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[3] GTX_DUAL:DRP23[14] GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1[0] GTX_DUAL:DRP23[15]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[2] GTX_DUAL:DRP23[13] GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[1] GTX_DUAL:DRP23[12]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_LEVEL_1[2] GTX_DUAL:DRP23[10] GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1[0] GTX_DUAL:DRP23[11]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_LEVEL_1[1] GTX_DUAL:DRP23[9] GTX_DUAL:CHAN_BOND_LEVEL_1[0] GTX_DUAL:DRP23[8]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[0] GTX_DUAL:CHAN_BOND_MODE_1[1] GTX_DUAL:DRP23[6] GTX_DUAL:CHAN_BOND_MODE_1[0] GTX_DUAL:DRP23[7]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[1] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[9] GTX_DUAL:DRP23[5] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[8] GTX_DUAL:DRP23[4]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[2] - GTX_DUAL:CHAN_BOND_SEQ_1_1_1[6] GTX_DUAL:DRP23[2] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[7] GTX_DUAL:DRP23[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[3] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[5] GTX_DUAL:DRP23[1] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[4] GTX_DUAL:DRP23[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[4] - GTX_DUAL:CHAN_BOND_SEQ_1_1_1[2] GTX_DUAL:DRP22[14] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[3] GTX_DUAL:DRP22[15]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[5] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[1] GTX_DUAL:DRP22[13] GTX_DUAL:CHAN_BOND_SEQ_1_1_1[0] GTX_DUAL:DRP22[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[6] - GTX_DUAL:CHAN_BOND_SEQ_1_2_1[8] GTX_DUAL:DRP22[10] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[9] GTX_DUAL:DRP22[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[7] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[7] GTX_DUAL:DRP22[9] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[6] GTX_DUAL:DRP22[8]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[8] - GTX_DUAL:CHAN_BOND_SEQ_1_2_1[4] GTX_DUAL:DRP22[6] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[5] GTX_DUAL:DRP22[7]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[9] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[3] GTX_DUAL:DRP22[5] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[2] GTX_DUAL:DRP22[4]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[10] - GTX_DUAL:CHAN_BOND_SEQ_1_2_1[0] GTX_DUAL:DRP22[2] GTX_DUAL:CHAN_BOND_SEQ_1_2_1[1] GTX_DUAL:DRP22[3]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_1_3_1[9] GTX_DUAL:DRP22[1] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[8] GTX_DUAL:DRP22[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[11] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[6] GTX_DUAL:DRP21[14] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[7] GTX_DUAL:DRP21[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[12] - GTX_DUAL:CHAN_BOND_SEQ_1_3_1[5] GTX_DUAL:DRP21[13] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[4] GTX_DUAL:DRP21[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[13] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[2] GTX_DUAL:DRP21[10] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[3] GTX_DUAL:DRP21[11]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[14] CRC32_1:CRC_INIT[15] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[1] GTX_DUAL:DRP21[9] GTX_DUAL:CHAN_BOND_SEQ_1_3_1[0] GTX_DUAL:DRP21[8]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[16] - GTX_DUAL:CHAN_BOND_SEQ_1_4_1[8] GTX_DUAL:DRP21[6] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[9] GTX_DUAL:DRP21[7]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[17] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[7] GTX_DUAL:DRP21[5] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[6] GTX_DUAL:DRP21[4]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[18] - GTX_DUAL:CHAN_BOND_SEQ_1_4_1[4] GTX_DUAL:DRP21[2] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[5] GTX_DUAL:DRP21[3]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[19] - GTX_DUAL:CHAN_BOND_SEQ_1_4_1[3] GTX_DUAL:DRP21[1] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[2] GTX_DUAL:DRP21[0]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[20] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[0] GTX_DUAL:DRP20[14] GTX_DUAL:CHAN_BOND_SEQ_1_4_1[1] GTX_DUAL:DRP20[15]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[21] CRC32_1:CRC_INIT[22] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[3] GTX_DUAL:DRP20[13] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[2] GTX_DUAL:DRP20[12]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[0] GTX_DUAL:DRP20[10] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1[1] GTX_DUAL:DRP20[11]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[23] - GTX_DUAL:CHAN_BOND_SEQ_2_1_1[9] GTX_DUAL:DRP20[9] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[8] GTX_DUAL:DRP20[8]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[25] CRC32_1:CRC_INIT[24] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[6] GTX_DUAL:DRP20[6] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[7] GTX_DUAL:DRP20[7]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_1_1[5] GTX_DUAL:DRP20[5] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[4] GTX_DUAL:DRP20[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[26] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[2] GTX_DUAL:DRP20[2] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[3] GTX_DUAL:DRP20[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_1:CRC_INIT[27] - GTX_DUAL:CHAN_BOND_SEQ_2_1_1[1] GTX_DUAL:DRP20[1] GTX_DUAL:CHAN_BOND_SEQ_2_1_1[0] GTX_DUAL:DRP20[0]
virtex5 GTX rect R10
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[27] - GTX_DUAL:CHAN_BOND_SEQ_2_1_0[1] GTX_DUAL:DRP2F[14] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[0] GTX_DUAL:DRP2F[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[26] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[2] GTX_DUAL:DRP2F[13] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[3] GTX_DUAL:DRP2F[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_1_0[5] GTX_DUAL:DRP2F[10] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[4] GTX_DUAL:DRP2F[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[25] CRC32_2:CRC_INIT[24] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[6] GTX_DUAL:DRP2F[9] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[7] GTX_DUAL:DRP2F[8]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[23] - GTX_DUAL:CHAN_BOND_SEQ_2_1_0[9] GTX_DUAL:DRP2F[6] GTX_DUAL:CHAN_BOND_SEQ_2_1_0[8] GTX_DUAL:DRP2F[7]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[0] GTX_DUAL:DRP2F[5] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[1] GTX_DUAL:DRP2F[4]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[21] CRC32_2:CRC_INIT[22] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[3] GTX_DUAL:DRP2F[2] GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0[2] GTX_DUAL:DRP2F[3]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[20] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[0] GTX_DUAL:DRP2F[1] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[1] GTX_DUAL:DRP2F[0]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[19] - GTX_DUAL:CHAN_BOND_SEQ_1_4_0[3] GTX_DUAL:DRP2E[14] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[2] GTX_DUAL:DRP2E[15]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[18] - GTX_DUAL:CHAN_BOND_SEQ_1_4_0[4] GTX_DUAL:DRP2E[13] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[5] GTX_DUAL:DRP2E[12]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[17] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[7] GTX_DUAL:DRP2E[10] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[6] GTX_DUAL:DRP2E[11]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[16] - GTX_DUAL:CHAN_BOND_SEQ_1_4_0[8] GTX_DUAL:DRP2E[9] GTX_DUAL:CHAN_BOND_SEQ_1_4_0[9] GTX_DUAL:DRP2E[8]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[14] CRC32_2:CRC_INIT[15] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[1] GTX_DUAL:DRP2E[6] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[0] GTX_DUAL:DRP2E[7]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[13] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[2] GTX_DUAL:DRP2E[5] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[3] GTX_DUAL:DRP2E[4]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[12] - GTX_DUAL:CHAN_BOND_SEQ_1_3_0[5] GTX_DUAL:DRP2E[2] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[4] GTX_DUAL:DRP2E[3]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[11] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[6] GTX_DUAL:DRP2E[1] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[7] GTX_DUAL:DRP2E[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_1_3_0[9] GTX_DUAL:DRP2D[14] GTX_DUAL:CHAN_BOND_SEQ_1_3_0[8] GTX_DUAL:DRP2D[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[10] - GTX_DUAL:CHAN_BOND_SEQ_1_2_0[0] GTX_DUAL:DRP2D[13] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[1] GTX_DUAL:DRP2D[12]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[9] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[3] GTX_DUAL:DRP2D[10] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[2] GTX_DUAL:DRP2D[11]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[8] - GTX_DUAL:CHAN_BOND_SEQ_1_2_0[4] GTX_DUAL:DRP2D[9] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[5] GTX_DUAL:DRP2D[8]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[7] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[7] GTX_DUAL:DRP2D[6] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[6] GTX_DUAL:DRP2D[7]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[6] - GTX_DUAL:CHAN_BOND_SEQ_1_2_0[8] GTX_DUAL:DRP2D[5] GTX_DUAL:CHAN_BOND_SEQ_1_2_0[9] GTX_DUAL:DRP2D[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[5] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[1] GTX_DUAL:DRP2D[2] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[0] GTX_DUAL:DRP2D[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[4] - GTX_DUAL:CHAN_BOND_SEQ_1_1_0[2] GTX_DUAL:DRP2D[1] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[3] GTX_DUAL:DRP2D[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[3] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[5] GTX_DUAL:DRP2C[14] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[4] GTX_DUAL:DRP2C[15]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[2] - GTX_DUAL:CHAN_BOND_SEQ_1_1_0[6] GTX_DUAL:DRP2C[13] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[7] GTX_DUAL:DRP2C[12]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[1] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[9] GTX_DUAL:DRP2C[10] GTX_DUAL:CHAN_BOND_SEQ_1_1_0[8] GTX_DUAL:DRP2C[11]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[0] GTX_DUAL:CHAN_BOND_MODE_0[1] GTX_DUAL:DRP2C[9] GTX_DUAL:CHAN_BOND_MODE_0[0] GTX_DUAL:DRP2C[8]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_LEVEL_0[1] GTX_DUAL:DRP2C[6] GTX_DUAL:CHAN_BOND_LEVEL_0[0] GTX_DUAL:DRP2C[7]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_LEVEL_0[2] GTX_DUAL:DRP2C[5] GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[0] GTX_DUAL:DRP2C[4]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[2] GTX_DUAL:DRP2C[2] GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[1] GTX_DUAL:DRP2C[3]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0[3] GTX_DUAL:DRP2C[1] GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[0] GTX_DUAL:DRP2C[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[2] GTX_DUAL:DRP2B[14] GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[1] GTX_DUAL:DRP2B[15]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0[3] GTX_DUAL:DRP2B[13] GTX_DUAL:ALIGN_COMMA_WORD_0[0] GTX_DUAL:DRP2B[12]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[10] GTX_DUAL:PMA_COM_CFG[1] GTX_DUAL:DRP2B[11] GTX_DUAL:PMA_COM_CFG[9]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[9] GTX_DUAL:PMA_COM_CFG[2] GTX_DUAL:DRP2B[8] GTX_DUAL:PMA_COM_CFG[3]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[6] GTX_DUAL:PMA_COM_CFG[0] GTX_DUAL:DRP2B[7] GTX_DUAL:PMA_COM_CFG[4]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[5] GTX_DUAL:PMA_COM_CFG[5] GTX_DUAL:DRP2B[4] GTX_DUAL:PMA_COM_CFG[6]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[2] GTX_DUAL:DRP2B[3] GTX_DUAL:PMA_COM_CFG[7]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2B[1] GTX_DUAL:DRP2B[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[14] GTX_DUAL:PMA_COM_CFG[51] GTX_DUAL:DRP2A[15] GTX_DUAL:PMA_COM_CFG[49]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[13] GTX_DUAL:DRP2A[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[10] GTX_DUAL:DRP2A[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[9] GTX_DUAL:DRP2A[8]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[6] GTX_DUAL:PMA_COM_CFG[67] GTX_DUAL:DRP2A[7] GTX_DUAL:PMA_COM_CFG[65]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[5] GTX_DUAL:PMA_COM_CFG[59] GTX_DUAL:DRP2A[4] GTX_DUAL:PMA_COM_CFG[57]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[2] GTX_DUAL:PMA_COM_CFG[60] GTX_DUAL:DRP2A[3] GTX_DUAL:PMA_COM_CFG[58]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP2A[1] GTX_DUAL:PMA_COM_CFG[55] GTX_DUAL:DRP2A[0] GTX_DUAL:PMA_COM_CFG[53]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[14] GTX_DUAL:PMA_COM_CFG[33] GTX_DUAL:DRP29[15] GTX_DUAL:PMA_COM_CFG[35]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[13] GTX_DUAL:PMA_COM_CFG[37] GTX_DUAL:DRP29[12] GTX_DUAL:PMA_COM_CFG[39]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[10] GTX_DUAL:PMA_COM_CFG[43] GTX_DUAL:DRP29[11] GTX_DUAL:PMA_COM_CFG[41]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[9] GTX_DUAL:PMA_COM_CFG[45] GTX_DUAL:DRP29[8] GTX_DUAL:PMA_COM_CFG[47]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[6] GTX_DUAL:TERMINATION_OVRD GTX_DUAL:DRP29[7] GTX_DUAL:PMA_COM_CFG[32]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[5] GTX_DUAL:TERMINATION_CTRL[0] GTX_DUAL:DRP29[4] GTX_DUAL:TERMINATION_CTRL[1]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[2] GTX_DUAL:TERMINATION_CTRL[3] GTX_DUAL:DRP29[3] GTX_DUAL:TERMINATION_CTRL[2]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP29[1] GTX_DUAL:TERMINATION_CTRL[4] GTX_DUAL:DRP29[0] GTX_DUAL:PLL_DIVSEL_FB[1]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[14] GTX_DUAL:PLL_DIVSEL_FB[3] GTX_DUAL:DRP28[15] GTX_DUAL:PLL_DIVSEL_FB[2]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[13] GTX_DUAL:DRP28[12] GTX_DUAL:PLL_DIVSEL_FB[0]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[10] GTX_DUAL:PLL_CP_CFG[1] GTX_DUAL:DRP28[11] GTX_DUAL:PLL_CP_CFG[0]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[9] GTX_DUAL:PLL_CP_CFG[2] GTX_DUAL:DRP28[8] GTX_DUAL:PLL_CP_CFG[3]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[6] GTX_DUAL:PLL_CP_CFG[5] GTX_DUAL:DRP28[7] GTX_DUAL:PLL_CP_CFG[4]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[5] GTX_DUAL:PLL_CP_CFG[6] GTX_DUAL:DRP28[4] GTX_DUAL:PLL_CP_CFG[7]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[2] GTX_DUAL:PLL_COM_CFG[1] GTX_DUAL:DRP28[3] GTX_DUAL:PLL_COM_CFG[0]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP28[1] GTX_DUAL:PLL_COM_CFG[2] GTX_DUAL:DRP28[0] GTX_DUAL:PLL_COM_CFG[3]
virtex5 GTX rect R11
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_0[6] GTX_DUAL:DRP37[14] GTX_DUAL:CLK_COR_SEQ_1_1_0[7] GTX_DUAL:DRP37[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_0[5] GTX_DUAL:DRP37[13] GTX_DUAL:CLK_COR_SEQ_1_1_0[4] GTX_DUAL:DRP37[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_0[2] GTX_DUAL:DRP37[10] GTX_DUAL:CLK_COR_SEQ_1_1_0[3] GTX_DUAL:DRP37[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_0[1] GTX_DUAL:DRP37[9] GTX_DUAL:CLK_COR_SEQ_1_1_0[0] GTX_DUAL:DRP37[8]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_0[8] GTX_DUAL:DRP37[6] GTX_DUAL:CLK_COR_SEQ_1_2_0[9] GTX_DUAL:DRP37[7]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_0[7] GTX_DUAL:DRP37[5] GTX_DUAL:CLK_COR_SEQ_1_2_0[6] GTX_DUAL:DRP37[4]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_0[4] GTX_DUAL:DRP37[2] GTX_DUAL:CLK_COR_SEQ_1_2_0[5] GTX_DUAL:DRP37[3]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_0[3] GTX_DUAL:DRP37[1] GTX_DUAL:CLK_COR_SEQ_1_2_0[2] GTX_DUAL:DRP37[0]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_2_0[0] GTX_DUAL:DRP36[14] GTX_DUAL:CLK_COR_SEQ_1_2_0[1] GTX_DUAL:DRP36[15]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_0[9] GTX_DUAL:DRP36[13] GTX_DUAL:CLK_COR_SEQ_1_3_0[8] GTX_DUAL:DRP36[12]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_0[6] GTX_DUAL:DRP36[10] GTX_DUAL:CLK_COR_SEQ_1_3_0[7] GTX_DUAL:DRP36[11]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_0[5] GTX_DUAL:DRP36[9] GTX_DUAL:CLK_COR_SEQ_1_3_0[4] GTX_DUAL:DRP36[8]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_0[2] GTX_DUAL:DRP36[6] GTX_DUAL:CLK_COR_SEQ_1_3_0[3] GTX_DUAL:DRP36[7]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_3_0[1] GTX_DUAL:DRP36[5] GTX_DUAL:CLK_COR_SEQ_1_3_0[0] GTX_DUAL:DRP36[4]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_0[8] GTX_DUAL:DRP36[2] GTX_DUAL:CLK_COR_SEQ_1_4_0[9] GTX_DUAL:DRP36[3]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_0[7] GTX_DUAL:DRP36[1] GTX_DUAL:CLK_COR_SEQ_1_4_0[6] GTX_DUAL:DRP36[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_0[4] GTX_DUAL:DRP35[14] GTX_DUAL:CLK_COR_SEQ_1_4_0[5] GTX_DUAL:DRP35[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_0[3] GTX_DUAL:DRP35[13] GTX_DUAL:CLK_COR_SEQ_1_4_0[2] GTX_DUAL:DRP35[12]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_4_0[0] GTX_DUAL:DRP35[10] GTX_DUAL:CLK_COR_SEQ_1_4_0[1] GTX_DUAL:DRP35[11]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[3] GTX_DUAL:DRP35[9] GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[2] GTX_DUAL:DRP35[8]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[0] GTX_DUAL:DRP35[6] GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0[1] GTX_DUAL:DRP35[7]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_0[9] GTX_DUAL:DRP35[5] GTX_DUAL:CLK_COR_SEQ_2_1_0[8] GTX_DUAL:DRP35[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_0[6] GTX_DUAL:DRP35[2] GTX_DUAL:CLK_COR_SEQ_2_1_0[7] GTX_DUAL:DRP35[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_0[5] GTX_DUAL:DRP35[1] GTX_DUAL:CLK_COR_SEQ_2_1_0[4] GTX_DUAL:DRP35[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_0[2] GTX_DUAL:DRP34[14] GTX_DUAL:CLK_COR_SEQ_2_1_0[3] GTX_DUAL:DRP34[15]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_1_0[1] GTX_DUAL:DRP34[13] GTX_DUAL:CLK_COR_SEQ_2_1_0[0] GTX_DUAL:DRP34[12]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_0[8] GTX_DUAL:DRP34[10] GTX_DUAL:CLK_COR_SEQ_2_2_0[9] GTX_DUAL:DRP34[11]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_0[7] GTX_DUAL:DRP34[9] GTX_DUAL:CLK_COR_SEQ_2_2_0[6] GTX_DUAL:DRP34[8]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_0[4] GTX_DUAL:DRP34[6] GTX_DUAL:CLK_COR_SEQ_2_2_0[5] GTX_DUAL:DRP34[7]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_0[3] GTX_DUAL:DRP34[5] GTX_DUAL:CLK_COR_SEQ_2_2_0[2] GTX_DUAL:DRP34[4]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_2_0[0] GTX_DUAL:DRP34[2] GTX_DUAL:CLK_COR_SEQ_2_2_0[1] GTX_DUAL:DRP34[3]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_0[9] GTX_DUAL:DRP34[1] GTX_DUAL:CLK_COR_SEQ_2_3_0[8] GTX_DUAL:DRP34[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_0[6] GTX_DUAL:DRP33[14] GTX_DUAL:CLK_COR_SEQ_2_3_0[7] GTX_DUAL:DRP33[15]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_0[5] GTX_DUAL:DRP33[13] GTX_DUAL:CLK_COR_SEQ_2_3_0[4] GTX_DUAL:DRP33[12]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_0[2] GTX_DUAL:DRP33[10] GTX_DUAL:CLK_COR_SEQ_2_3_0[3] GTX_DUAL:DRP33[11]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_3_0[1] GTX_DUAL:DRP33[9] GTX_DUAL:CLK_COR_SEQ_2_3_0[0] GTX_DUAL:DRP33[8]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_0[8] GTX_DUAL:DRP33[6] GTX_DUAL:CLK_COR_SEQ_2_4_0[9] GTX_DUAL:DRP33[7]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_0[7] GTX_DUAL:DRP33[5] GTX_DUAL:CLK_COR_SEQ_2_4_0[6] GTX_DUAL:DRP33[4]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_0[4] GTX_DUAL:DRP33[2] GTX_DUAL:CLK_COR_SEQ_2_4_0[5] GTX_DUAL:DRP33[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_0[3] GTX_DUAL:DRP33[1] GTX_DUAL:CLK_COR_SEQ_2_4_0[2] GTX_DUAL:DRP33[0]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_4_0[0] GTX_DUAL:DRP32[14] GTX_DUAL:CLK_COR_SEQ_2_4_0[1] GTX_DUAL:DRP32[15]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[3] GTX_DUAL:DRP32[13] GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[2] GTX_DUAL:DRP32[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[0] GTX_DUAL:DRP32[10] GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0[1] GTX_DUAL:DRP32[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_2_USE_0 GTX_DUAL:DRP32[9] GTX_DUAL:COM_BURST_VAL_0[3] GTX_DUAL:DRP32[8]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COM_BURST_VAL_0[1] GTX_DUAL:DRP32[6] GTX_DUAL:COM_BURST_VAL_0[2] GTX_DUAL:DRP32[7]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COM_BURST_VAL_0[0] GTX_DUAL:DRP32[5] GTX_DUAL:COMMA_10B_ENABLE_0[9] GTX_DUAL:DRP32[4]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_0[7] GTX_DUAL:DRP32[2] GTX_DUAL:COMMA_10B_ENABLE_0[8] GTX_DUAL:DRP32[3]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_0[6] GTX_DUAL:DRP32[1] GTX_DUAL:COMMA_10B_ENABLE_0[5] GTX_DUAL:DRP32[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_0[3] GTX_DUAL:DRP31[14] GTX_DUAL:COMMA_10B_ENABLE_0[4] GTX_DUAL:DRP31[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_10B_ENABLE_0[2] GTX_DUAL:DRP31[13] GTX_DUAL:COMMA_10B_ENABLE_0[1] GTX_DUAL:DRP31[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:COMMA_DOUBLE_0 GTX_DUAL:DRP31[10] GTX_DUAL:COMMA_10B_ENABLE_0[0] GTX_DUAL:DRP31[11]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DEC_MCOMMA_DETECT_0 GTX_DUAL:DRP31[9] GTX_DUAL:DEC_PCOMMA_DETECT_0 GTX_DUAL:DRP31[8]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP31[6] GTX_DUAL:MCOMMA_10B_VALUE_0[9] GTX_DUAL:DEC_VALID_COMMA_ONLY_0 GTX_DUAL:DRP31[7]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP31[5] GTX_DUAL:MCOMMA_10B_VALUE_0[8] GTX_DUAL:DRP31[4] GTX_DUAL:MCOMMA_10B_VALUE_0[7]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP31[2] GTX_DUAL:MCOMMA_10B_VALUE_0[5] GTX_DUAL:DRP31[3] GTX_DUAL:MCOMMA_10B_VALUE_0[6]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP31[1] GTX_DUAL:MCOMMA_10B_VALUE_0[4] GTX_DUAL:DRP31[0] GTX_DUAL:MCOMMA_10B_VALUE_0[3]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP30[14] GTX_DUAL:MCOMMA_10B_VALUE_0[1] GTX_DUAL:DRP30[15] GTX_DUAL:MCOMMA_10B_VALUE_0[2]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP30[13] GTX_DUAL:MCOMMA_10B_VALUE_0[0] GTX_DUAL:DRP30[12] GTX_DUAL:MCOMMA_DETECT_0
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_2_0[0] GTX_DUAL:DRP30[10] GTX_DUAL:CHAN_BOND_SEQ_2_3_0[9] GTX_DUAL:DRP30[11]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_2_0[1] GTX_DUAL:DRP30[9] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[2] GTX_DUAL:DRP30[8]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[31] - GTX_DUAL:CHAN_BOND_SEQ_2_2_0[4] GTX_DUAL:DRP30[6] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[3] GTX_DUAL:DRP30[7]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[30] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[5] GTX_DUAL:DRP30[5] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[6] GTX_DUAL:DRP30[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[29] - GTX_DUAL:DRP30[2] GTX_DUAL:PLL_FB_DCCEN GTX_DUAL:CHAN_BOND_SEQ_2_2_0[7] GTX_DUAL:DRP30[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_2:CRC_INIT[28] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[8] GTX_DUAL:DRP30[1] GTX_DUAL:CHAN_BOND_SEQ_2_2_0[9] GTX_DUAL:DRP30[0]
virtex5 GTX rect R12
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[14] GTX_DUAL:SATA_MIN_BURST_0[4] GTX_DUAL:DRP3F[15] GTX_DUAL:SATA_MIN_BURST_0[5]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[13] GTX_DUAL:SATA_MIN_BURST_0[3] GTX_DUAL:DRP3F[12] GTX_DUAL:SATA_MIN_BURST_0[2]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[10] GTX_DUAL:SATA_MIN_BURST_0[0] GTX_DUAL:DRP3F[11] GTX_DUAL:SATA_MIN_BURST_0[1]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[9] GTX_DUAL:SATA_MIN_INIT_0[5] GTX_DUAL:DRP3F[8] GTX_DUAL:SATA_MIN_INIT_0[4]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[6] GTX_DUAL:SATA_MIN_INIT_0[2] GTX_DUAL:DRP3F[7] GTX_DUAL:SATA_MIN_INIT_0[3]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[5] GTX_DUAL:SATA_MIN_INIT_0[1] GTX_DUAL:DRP3F[4] GTX_DUAL:SATA_MIN_INIT_0[0]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[2] GTX_DUAL:SATA_MIN_WAKE_0[4] GTX_DUAL:DRP3F[3] GTX_DUAL:SATA_MIN_WAKE_0[5]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3F[1] GTX_DUAL:SATA_MIN_WAKE_0[3] GTX_DUAL:DRP3F[0] GTX_DUAL:SATA_MIN_WAKE_0[2]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[14] GTX_DUAL:SATA_MIN_WAKE_0[0] GTX_DUAL:DRP3E[15] GTX_DUAL:SATA_MIN_WAKE_0[1]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[13] GTX_DUAL:TERMINATION_IMP_0[0] GTX_DUAL:DRP3E[12] GTX_DUAL:TRANS_TIME_FROM_P2_0[11]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[10] GTX_DUAL:TRANS_TIME_FROM_P2_0[9] GTX_DUAL:DRP3E[11] GTX_DUAL:TRANS_TIME_FROM_P2_0[10]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[9] GTX_DUAL:TRANS_TIME_FROM_P2_0[8] GTX_DUAL:DRP3E[8] GTX_DUAL:TRANS_TIME_FROM_P2_0[7]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[6] GTX_DUAL:TRANS_TIME_FROM_P2_0[5] GTX_DUAL:DRP3E[7] GTX_DUAL:TRANS_TIME_FROM_P2_0[6]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[5] GTX_DUAL:TRANS_TIME_FROM_P2_0[4] GTX_DUAL:DRP3E[4] GTX_DUAL:TRANS_TIME_FROM_P2_0[3]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[2] GTX_DUAL:TRANS_TIME_FROM_P2_0[1] GTX_DUAL:DRP3E[3] GTX_DUAL:TRANS_TIME_FROM_P2_0[2]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3E[1] GTX_DUAL:TRANS_TIME_FROM_P2_0[0] GTX_DUAL:DRP3E[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[14] GTX_DUAL:DRP3D[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[13] GTX_DUAL:DRP3D[12] GTX_DUAL:TRANS_TIME_NON_P2_0[7]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[10] GTX_DUAL:TRANS_TIME_NON_P2_0[5] GTX_DUAL:DRP3D[11] GTX_DUAL:TRANS_TIME_NON_P2_0[6]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[9] GTX_DUAL:TRANS_TIME_NON_P2_0[4] GTX_DUAL:DRP3D[8] GTX_DUAL:TRANS_TIME_NON_P2_0[3]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[6] GTX_DUAL:TRANS_TIME_NON_P2_0[1] GTX_DUAL:DRP3D[7] GTX_DUAL:TRANS_TIME_NON_P2_0[2]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3D[5] GTX_DUAL:TRANS_TIME_NON_P2_0[0] GTX_DUAL:DRP3D[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CDR_PH_ADJ_TIME[3] GTX_DUAL:DRP3D[2] GTX_DUAL:CDR_PH_ADJ_TIME[4] GTX_DUAL:DRP3D[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CDR_PH_ADJ_TIME[2] GTX_DUAL:DRP3D[1] GTX_DUAL:CDR_PH_ADJ_TIME[1] GTX_DUAL:DRP3D[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[14] GTX_DUAL:CDR_PH_ADJ_TIME[0] GTX_DUAL:DRP3C[15]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[13] GTX_DUAL:DRP3C[12] GTX_DUAL:TRANS_TIME_TO_P2_0[9]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[10] GTX_DUAL:TRANS_TIME_TO_P2_0[7] GTX_DUAL:DRP3C[11] GTX_DUAL:TRANS_TIME_TO_P2_0[8]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[9] GTX_DUAL:TRANS_TIME_TO_P2_0[6] GTX_DUAL:DRP3C[8] GTX_DUAL:TRANS_TIME_TO_P2_0[5]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[6] GTX_DUAL:TRANS_TIME_TO_P2_0[3] GTX_DUAL:DRP3C[7] GTX_DUAL:TRANS_TIME_TO_P2_0[4]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3C[5] GTX_DUAL:TRANS_TIME_TO_P2_0[2] GTX_DUAL:DRP3C[4] GTX_DUAL:TRANS_TIME_TO_P2_0[1]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CAL_TIME[4] GTX_DUAL:DRP3C[2] GTX_DUAL:DRP3C[3] GTX_DUAL:TRANS_TIME_TO_P2_0[0]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CAL_TIME[3] GTX_DUAL:DRP3C[1] GTX_DUAL:DFE_CAL_TIME[2] GTX_DUAL:DRP3C[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CAL_TIME[0] GTX_DUAL:DRP3B[14] GTX_DUAL:DFE_CAL_TIME[1] GTX_DUAL:DRP3B[15]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[13] GTX_DUAL:DRP3B[12] GTX_DUAL:TX_BUFFER_USE_0
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[10] GTX_DUAL:TX_DETECT_RX_CFG_0[12] GTX_DUAL:DRP3B[11] GTX_DUAL:TX_DETECT_RX_CFG_0[13]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[9] GTX_DUAL:TX_DETECT_RX_CFG_0[11] GTX_DUAL:DRP3B[8] GTX_DUAL:TX_DETECT_RX_CFG_0[10]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[6] GTX_DUAL:TX_DETECT_RX_CFG_0[8] GTX_DUAL:DRP3B[7] GTX_DUAL:TX_DETECT_RX_CFG_0[9]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[5] GTX_DUAL:TX_DETECT_RX_CFG_0[7] GTX_DUAL:DRP3B[4] GTX_DUAL:TX_DETECT_RX_CFG_0[6]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[2] GTX_DUAL:TX_DETECT_RX_CFG_0[4] GTX_DUAL:DRP3B[3] GTX_DUAL:TX_DETECT_RX_CFG_0[5]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3B[1] GTX_DUAL:TX_DETECT_RX_CFG_0[3] GTX_DUAL:DRP3B[0] GTX_DUAL:TX_DETECT_RX_CFG_0[2]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[14] GTX_DUAL:TX_DETECT_RX_CFG_0[0] GTX_DUAL:DRP3A[15] GTX_DUAL:TX_DETECT_RX_CFG_0[1]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[13] GTX_DUAL:TXRX_INVERT_0[2] GTX_DUAL:DRP3A[12] GTX_DUAL:TXRX_INVERT_0[1]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[10] GTX_DUAL:RX_EN_IDLE_RESET_FR GTX_DUAL:DRP3A[11] GTX_DUAL:TXRX_INVERT_0[0]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[9] GTX_DUAL:RX_EN_IDLE_HOLD_CDR GTX_DUAL:DRP3A[8] GTX_DUAL:TX_XCLK_SEL_0[0]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[6] GTX_DUAL:PMA_COM_CFG[19] GTX_DUAL:DRP3A[7] GTX_DUAL:TXOUTCLK_SEL_0
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[5] GTX_DUAL:OOBDETECT_THRESHOLD_0[2] GTX_DUAL:DRP3A[4] GTX_DUAL:OOBDETECT_THRESHOLD_0[1]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP3A[2] GTX_DUAL:RX_EN_IDLE_RESET_PH GTX_DUAL:DRP3A[3] GTX_DUAL:OOBDETECT_THRESHOLD_0[0]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[3] GTX_DUAL:DRP3A[1] GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[2] GTX_DUAL:DRP3A[0]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[0] GTX_DUAL:DRP39[14] GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0[1] GTX_DUAL:DRP39[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_USE_0 GTX_DUAL:DRP39[13] GTX_DUAL:CHAN_BOND_SEQ_LEN_0[1] GTX_DUAL:DRP39[12]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_ADJ_LEN_0[1] GTX_DUAL:DRP39[10] GTX_DUAL:CHAN_BOND_SEQ_LEN_0[0] GTX_DUAL:DRP39[11]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_ADJ_LEN_0[0] GTX_DUAL:DRP39[9] GTX_DUAL:CLK_COR_DET_LEN_0[1] GTX_DUAL:DRP39[8]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_0 GTX_DUAL:DRP39[6] GTX_DUAL:CLK_COR_DET_LEN_0[0] GTX_DUAL:DRP39[7]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_KEEP_IDLE_0 GTX_DUAL:DRP39[5] GTX_DUAL:CLK_COR_MAX_LAT_0[5] GTX_DUAL:DRP39[4]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MAX_LAT_0[3] GTX_DUAL:DRP39[2] GTX_DUAL:CLK_COR_MAX_LAT_0[4] GTX_DUAL:DRP39[3]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MAX_LAT_0[2] GTX_DUAL:DRP39[1] GTX_DUAL:CLK_COR_MAX_LAT_0[1] GTX_DUAL:DRP39[0]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_0[5] GTX_DUAL:DRP38[14] GTX_DUAL:CLK_COR_MAX_LAT_0[0] GTX_DUAL:DRP38[15]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_0[4] GTX_DUAL:DRP38[13] GTX_DUAL:CLK_COR_MIN_LAT_0[3] GTX_DUAL:DRP38[12]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_0[1] GTX_DUAL:DRP38[10] GTX_DUAL:CLK_COR_MIN_LAT_0[2] GTX_DUAL:DRP38[11]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_MIN_LAT_0[0] GTX_DUAL:DRP38[9] GTX_DUAL:CLK_COR_PRECEDENCE_0 GTX_DUAL:DRP38[8]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_0[4] GTX_DUAL:DRP38[6] GTX_DUAL:CLK_CORRECT_USE_0 GTX_DUAL:DRP38[7]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_0[3] GTX_DUAL:DRP38[5] GTX_DUAL:CLK_COR_REPEAT_WAIT_0[2] GTX_DUAL:DRP38[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_REPEAT_WAIT_0[0] GTX_DUAL:DRP38[2] GTX_DUAL:CLK_COR_REPEAT_WAIT_0[1] GTX_DUAL:DRP38[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CLK_COR_SEQ_1_1_0[9] GTX_DUAL:DRP38[1] GTX_DUAL:CLK_COR_SEQ_1_1_0[8] GTX_DUAL:DRP38[0]
virtex5 GTX rect R13
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_0[5] GTX_DUAL:DRP47[14] GTX_DUAL:CHAN_BOND_SEQ_2_4_0[4] GTX_DUAL:DRP47[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_0[6] GTX_DUAL:DRP47[13] GTX_DUAL:CHAN_BOND_SEQ_2_4_0[7] GTX_DUAL:DRP47[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_0[9] GTX_DUAL:DRP47[10] GTX_DUAL:CHAN_BOND_SEQ_2_4_0[8] GTX_DUAL:DRP47[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_0[0] GTX_DUAL:DRP47[9] GTX_DUAL:CHAN_BOND_SEQ_2_3_0[1] GTX_DUAL:DRP47[8]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_0[3] GTX_DUAL:DRP47[6] GTX_DUAL:CHAN_BOND_SEQ_2_3_0[2] GTX_DUAL:DRP47[7]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_0[4] GTX_DUAL:DRP47[5] GTX_DUAL:CHAN_BOND_SEQ_2_3_0[5] GTX_DUAL:DRP47[4]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_0[7] GTX_DUAL:DRP47[2] GTX_DUAL:CHAN_BOND_SEQ_2_3_0[6] GTX_DUAL:DRP47[3]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_3_0[8] GTX_DUAL:DRP47[1] GTX_DUAL:DRP47[0]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[14] GTX_DUAL:PCOMMA_10B_VALUE_0[9] GTX_DUAL:DRP46[15] GTX_DUAL:PCI_EXPRESS_MODE_0
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[13] GTX_DUAL:PCOMMA_10B_VALUE_0[8] GTX_DUAL:DRP46[12] GTX_DUAL:PCOMMA_10B_VALUE_0[7]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[10] GTX_DUAL:PCOMMA_10B_VALUE_0[5] GTX_DUAL:DRP46[11] GTX_DUAL:PCOMMA_10B_VALUE_0[6]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[9] GTX_DUAL:PCOMMA_10B_VALUE_0[4] GTX_DUAL:DRP46[8] GTX_DUAL:PCOMMA_10B_VALUE_0[3]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[6] GTX_DUAL:PCOMMA_10B_VALUE_0[1] GTX_DUAL:DRP46[7] GTX_DUAL:PCOMMA_10B_VALUE_0[2]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[5] GTX_DUAL:PCOMMA_10B_VALUE_0[0] GTX_DUAL:DRP46[4] GTX_DUAL:PCOMMA_DETECT_0
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[2] GTX_DUAL:PLL_RXDIVSEL_OUT_0[0] GTX_DUAL:DRP46[3] GTX_DUAL:PLL_RXDIVSEL_OUT_0[1]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP46[1] GTX_DUAL:PLL_SATA_0 GTX_DUAL:DRP46[0] GTX_DUAL:PLL_TXDIVSEL_OUT_0[1]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[14] GTX_DUAL:PMA_CDR_SCAN_0[26] GTX_DUAL:DRP45[15] GTX_DUAL:PLL_TXDIVSEL_OUT_0[0]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[13] GTX_DUAL:PMA_CDR_SCAN_0[25] GTX_DUAL:DRP45[12] GTX_DUAL:PMA_CDR_SCAN_0[24]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[10] GTX_DUAL:PMA_CDR_SCAN_0[22] GTX_DUAL:DRP45[11] GTX_DUAL:PMA_CDR_SCAN_0[23]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[9] GTX_DUAL:PMA_CDR_SCAN_0[21] GTX_DUAL:DRP45[8] GTX_DUAL:PMA_CDR_SCAN_0[20]
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[6] GTX_DUAL:PMA_CDR_SCAN_0[18] GTX_DUAL:DRP45[7] GTX_DUAL:PMA_CDR_SCAN_0[19]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[5] GTX_DUAL:PMA_CDR_SCAN_0[17] GTX_DUAL:DRP45[4] GTX_DUAL:PMA_CDR_SCAN_0[16]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[2] GTX_DUAL:PMA_CDR_SCAN_0[14] GTX_DUAL:DRP45[3] GTX_DUAL:PMA_CDR_SCAN_0[15]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP45[1] GTX_DUAL:PMA_CDR_SCAN_0[13] GTX_DUAL:DRP45[0] GTX_DUAL:PMA_CDR_SCAN_0[12]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[14] GTX_DUAL:PMA_CDR_SCAN_0[10] GTX_DUAL:DRP44[15] GTX_DUAL:PMA_CDR_SCAN_0[11]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[13] GTX_DUAL:PMA_CDR_SCAN_0[9] GTX_DUAL:DRP44[12] GTX_DUAL:PMA_CDR_SCAN_0[8]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[10] GTX_DUAL:PMA_CDR_SCAN_0[6] GTX_DUAL:DRP44[11] GTX_DUAL:PMA_CDR_SCAN_0[7]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[9] GTX_DUAL:PMA_CDR_SCAN_0[5] GTX_DUAL:DRP44[8] GTX_DUAL:PMA_CDR_SCAN_0[4]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[6] GTX_DUAL:PMA_CDR_SCAN_0[2] GTX_DUAL:DRP44[7] GTX_DUAL:PMA_CDR_SCAN_0[3]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[5] GTX_DUAL:PMA_CDR_SCAN_0[1] GTX_DUAL:DRP44[4] GTX_DUAL:PMA_CDR_SCAN_0[0]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[2] GTX_DUAL:PRBS_ERR_THRESHOLD_0[30] GTX_DUAL:DRP44[3] GTX_DUAL:PRBS_ERR_THRESHOLD_0[31]
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP44[1] GTX_DUAL:PRBS_ERR_THRESHOLD_0[29] GTX_DUAL:DRP44[0] GTX_DUAL:PRBS_ERR_THRESHOLD_0[28]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[14] GTX_DUAL:PRBS_ERR_THRESHOLD_0[26] GTX_DUAL:DRP43[15] GTX_DUAL:PRBS_ERR_THRESHOLD_0[27]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[13] GTX_DUAL:PRBS_ERR_THRESHOLD_0[25] GTX_DUAL:DRP43[12] GTX_DUAL:PRBS_ERR_THRESHOLD_0[24]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[10] GTX_DUAL:PRBS_ERR_THRESHOLD_0[22] GTX_DUAL:DRP43[11] GTX_DUAL:PRBS_ERR_THRESHOLD_0[23]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[9] GTX_DUAL:PRBS_ERR_THRESHOLD_0[21] GTX_DUAL:DRP43[8] GTX_DUAL:PRBS_ERR_THRESHOLD_0[20]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[6] GTX_DUAL:PRBS_ERR_THRESHOLD_0[18] GTX_DUAL:DRP43[7] GTX_DUAL:PRBS_ERR_THRESHOLD_0[19]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[5] GTX_DUAL:PRBS_ERR_THRESHOLD_0[17] GTX_DUAL:DRP43[4] GTX_DUAL:PRBS_ERR_THRESHOLD_0[16]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[2] GTX_DUAL:PRBS_ERR_THRESHOLD_0[14] GTX_DUAL:DRP43[3] GTX_DUAL:PRBS_ERR_THRESHOLD_0[15]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP43[1] GTX_DUAL:PRBS_ERR_THRESHOLD_0[13] GTX_DUAL:DRP43[0] GTX_DUAL:PRBS_ERR_THRESHOLD_0[12]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[14] GTX_DUAL:PRBS_ERR_THRESHOLD_0[10] GTX_DUAL:DRP42[15] GTX_DUAL:PRBS_ERR_THRESHOLD_0[11]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[13] GTX_DUAL:PRBS_ERR_THRESHOLD_0[9] GTX_DUAL:DRP42[12] GTX_DUAL:PRBS_ERR_THRESHOLD_0[8]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[10] GTX_DUAL:PRBS_ERR_THRESHOLD_0[6] GTX_DUAL:DRP42[11] GTX_DUAL:PRBS_ERR_THRESHOLD_0[7]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[9] GTX_DUAL:PRBS_ERR_THRESHOLD_0[5] GTX_DUAL:DRP42[8] GTX_DUAL:PRBS_ERR_THRESHOLD_0[4]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[6] GTX_DUAL:PRBS_ERR_THRESHOLD_0[2] GTX_DUAL:DRP42[7] GTX_DUAL:PRBS_ERR_THRESHOLD_0[3]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[5] GTX_DUAL:PRBS_ERR_THRESHOLD_0[1] GTX_DUAL:DRP42[4] GTX_DUAL:PRBS_ERR_THRESHOLD_0[0]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[2] GTX_DUAL:RX_DECODE_SEQ_MATCH_0 GTX_DUAL:DRP42[3] GTX_DUAL:RX_BUFFER_USE_0
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP42[1] GTX_DUAL:RX_LOS_INVALID_INCR_0[2] GTX_DUAL:DRP42[0] GTX_DUAL:RX_LOS_INVALID_INCR_0[1]
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[14] GTX_DUAL:RX_LOSS_OF_SYNC_FSM_0 GTX_DUAL:DRP41[15] GTX_DUAL:RX_LOS_INVALID_INCR_0[0]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[13] GTX_DUAL:RX_LOS_THRESHOLD_0[2] GTX_DUAL:DRP41[12] GTX_DUAL:RX_LOS_THRESHOLD_0[1]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[10] GTX_DUAL:RX_SLIDE_MODE_0[0] GTX_DUAL:DRP41[11] GTX_DUAL:RX_LOS_THRESHOLD_0[0]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[9] GTX_DUAL:RX_STATUS_FMT_0[0] GTX_DUAL:DRP41[8] GTX_DUAL:RX_XCLK_SEL_0[0]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[6] GTX_DUAL:SATA_BURST_VAL_0[1] GTX_DUAL:DRP41[7] GTX_DUAL:SATA_BURST_VAL_0[2]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[5] GTX_DUAL:SATA_BURST_VAL_0[0] GTX_DUAL:DRP41[4] GTX_DUAL:SATA_IDLE_VAL_0[2]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[2] GTX_DUAL:SATA_IDLE_VAL_0[0] GTX_DUAL:DRP41[3] GTX_DUAL:SATA_IDLE_VAL_0[1]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP41[1] GTX_DUAL:SATA_MAX_BURST_0[5] GTX_DUAL:DRP41[0] GTX_DUAL:SATA_MAX_BURST_0[4]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[14] GTX_DUAL:SATA_MAX_BURST_0[2] GTX_DUAL:DRP40[15] GTX_DUAL:SATA_MAX_BURST_0[3]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[13] GTX_DUAL:SATA_MAX_BURST_0[1] GTX_DUAL:DRP40[12] GTX_DUAL:SATA_MAX_BURST_0[0]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[10] GTX_DUAL:SATA_MAX_INIT_0[4] GTX_DUAL:DRP40[11] GTX_DUAL:SATA_MAX_INIT_0[5]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[9] GTX_DUAL:SATA_MAX_INIT_0[3] GTX_DUAL:DRP40[8] GTX_DUAL:SATA_MAX_INIT_0[2]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[6] GTX_DUAL:SATA_MAX_INIT_0[0] GTX_DUAL:DRP40[7] GTX_DUAL:SATA_MAX_INIT_0[1]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[5] GTX_DUAL:SATA_MAX_WAKE_0[5] GTX_DUAL:DRP40[4] GTX_DUAL:SATA_MAX_WAKE_0[4]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[2] GTX_DUAL:SATA_MAX_WAKE_0[2] GTX_DUAL:DRP40[3] GTX_DUAL:SATA_MAX_WAKE_0[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP40[1] GTX_DUAL:SATA_MAX_WAKE_0[1] GTX_DUAL:DRP40[0] GTX_DUAL:SATA_MAX_WAKE_0[0]
virtex5 GTX rect R14
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[14] GTX_DUAL:DRP4F[15]
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[13] GTX_DUAL:DRP4F[12]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[10] GTX_DUAL:DRP4F[11]
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[9] GTX_DUAL:PMA_TX_CFG_0[19] GTX_DUAL:DRP4F[8] GTX_DUAL:PMA_TX_CFG_0[18]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[6] GTX_DUAL:PMA_TX_CFG_0[16] GTX_DUAL:DRP4F[7] GTX_DUAL:PMA_TX_CFG_0[17]
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[5] GTX_DUAL:PMA_TX_CFG_0[15] GTX_DUAL:DRP4F[4] GTX_DUAL:PMA_TX_CFG_0[14]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[2] GTX_DUAL:PMA_TX_CFG_0[12] GTX_DUAL:DRP4F[3] GTX_DUAL:PMA_TX_CFG_0[13]
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4F[1] GTX_DUAL:PMA_TX_CFG_0[11] GTX_DUAL:DRP4F[0] GTX_DUAL:PMA_TX_CFG_0[10]
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4E[14] GTX_DUAL:PMA_TX_CFG_0[8] GTX_DUAL:DRP4E[15] GTX_DUAL:PMA_TX_CFG_0[9]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4E[13] GTX_DUAL:PMA_TX_CFG_0[7] GTX_DUAL:DRP4E[12] GTX_DUAL:PMA_TX_CFG_0[6]
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4E[10] GTX_DUAL:PMA_TX_CFG_0[4] GTX_DUAL:DRP4E[11] GTX_DUAL:PMA_TX_CFG_0[5]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4E[9] GTX_DUAL:PMA_TX_CFG_0[3] GTX_DUAL:DRP4E[8] GTX_DUAL:PMA_TX_CFG_0[2]
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4E[6] GTX_DUAL:PMA_TX_CFG_0[0] GTX_DUAL:DRP4E[7] GTX_DUAL:PMA_TX_CFG_0[1]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CM_TRIM_0[1] GTX_DUAL:DRP4E[5] GTX_DUAL:CM_TRIM_0[0] GTX_DUAL:DRP4E[4]
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_0[8] GTX_DUAL:DRP4E[2] GTX_DUAL:DFE_CFG_0[9] GTX_DUAL:DRP4E[3]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_0[7] GTX_DUAL:DRP4E[1] GTX_DUAL:DFE_CFG_0[6] GTX_DUAL:DRP4E[0]
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_0[4] GTX_DUAL:DRP4D[14] GTX_DUAL:DFE_CFG_0[5] GTX_DUAL:DRP4D[15]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_0[3] GTX_DUAL:DRP4D[13] GTX_DUAL:DFE_CFG_0[2] GTX_DUAL:DRP4D[12]
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DFE_CFG_0[0] GTX_DUAL:DRP4D[10] GTX_DUAL:DFE_CFG_0[1] GTX_DUAL:DRP4D[11]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4D[9] GTX_DUAL:TXGEARBOX_USE_0 GTX_DUAL:DRP4D[8] GTX_DUAL:RXGEARBOX_USE_0
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4D[6] GTX_DUAL:GEARBOX_ENDEC_0[1] GTX_DUAL:DRP4D[7] GTX_DUAL:GEARBOX_ENDEC_0[2]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4D[5] GTX_DUAL:GEARBOX_ENDEC_0[0] GTX_DUAL:CHAN_BOND_KEEP_ALIGN_0 GTX_DUAL:DRP4D[4]
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CB2_INH_CC_PERIOD_0[2] GTX_DUAL:DRP4D[2] GTX_DUAL:CB2_INH_CC_PERIOD_0[3] GTX_DUAL:DRP4D[3]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CB2_INH_CC_PERIOD_0[1] GTX_DUAL:DRP4D[1] GTX_DUAL:CB2_INH_CC_PERIOD_0[0] GTX_DUAL:DRP4D[0]
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[14] GTX_DUAL:RX_IDLE_LO_CNT_0[2] GTX_DUAL:DRP4C[15] GTX_DUAL:RX_IDLE_LO_CNT_0[3]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[13] GTX_DUAL:RX_IDLE_LO_CNT_0[1] GTX_DUAL:DRP4C[12] GTX_DUAL:RX_IDLE_LO_CNT_0[0]
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[10] GTX_DUAL:DRP4C[11]
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[9] GTX_DUAL:RX_IDLE_HI_CNT_0[3] GTX_DUAL:DRP4C[8] GTX_DUAL:RX_IDLE_HI_CNT_0[2]
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[6] GTX_DUAL:RX_IDLE_HI_CNT_0[0] GTX_DUAL:DRP4C[7] GTX_DUAL:RX_IDLE_HI_CNT_0[1]
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[5] GTX_DUAL:DRP4C[4]
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[2] GTX_DUAL:DRP4C[3] GTX_DUAL:RX_EN_IDLE_RESET_BUF_0
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4C[1] GTX_DUAL:RX_EN_IDLE_HOLD_DFE_0 GTX_DUAL:DRP4C[0]
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[14] GTX_DUAL:PMA_RXSYNC_CFG_0[5] GTX_DUAL:DRP4B[15] GTX_DUAL:PMA_RXSYNC_CFG_0[6]
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[13] GTX_DUAL:PMA_RXSYNC_CFG_0[4] GTX_DUAL:DRP4B[12] GTX_DUAL:PMA_RXSYNC_CFG_0[3]
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[10] GTX_DUAL:PMA_RXSYNC_CFG_0[1] GTX_DUAL:DRP4B[11] GTX_DUAL:PMA_RXSYNC_CFG_0[2]
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[9] GTX_DUAL:PMA_RXSYNC_CFG_0[0] GTX_DUAL:DRP4B[8] GTX_DUAL:TX_IDLE_DELAY_0[2]
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[6] GTX_DUAL:TX_IDLE_DELAY_0[0] GTX_DUAL:DRP4B[7] GTX_DUAL:TX_IDLE_DELAY_0[1]
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[5] GTX_DUAL:DRP4B[4]
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[2] GTX_DUAL:DRP4B[3]
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4B[1] GTX_DUAL:DRP4B[0] GTX_DUAL:PLL_TDCC_CFG[2]
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[14] GTX_DUAL:PLL_TDCC_CFG[1] GTX_DUAL:DRP4A[15] GTX_DUAL:PLL_TDCC_CFG[0]
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[13] GTX_DUAL:DRP4A[12]
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[10] GTX_DUAL:PLL_STARTUP_EN GTX_DUAL:DRP4A[11]
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[9] GTX_DUAL:DRP4A[8]
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[6] GTX_DUAL:PMA_COM_CFG[31] GTX_DUAL:DRP4A[7] GTX_DUAL:PMA_COM_CFG[20]
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[5] GTX_DUAL:PMA_COM_CFG[30] GTX_DUAL:DRP4A[4] GTX_DUAL:PMA_COM_CFG[29]
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[2] GTX_DUAL:PMA_COM_CFG[27] GTX_DUAL:DRP4A[3] GTX_DUAL:PMA_COM_CFG[28]
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP4A[1] GTX_DUAL:RCV_TERM_VTTRX_0 GTX_DUAL:DRP4A[0] GTX_DUAL:RCV_TERM_GND_0
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:AC_CAP_DIS_0 GTX_DUAL:DRP49[14] GTX_DUAL:DRP49[15]
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[13] GTX_DUAL:PMA_RX_CFG_1[12] GTX_DUAL:DRP49[12] GTX_DUAL:PMA_RX_CFG_1[24]
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[10] GTX_DUAL:PMA_RX_CFG_1[0] GTX_DUAL:DRP49[11] GTX_DUAL:PMA_RX_CFG_1[1]
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[9] GTX_DUAL:PMA_RX_CFG_1[11] GTX_DUAL:DRP49[8] GTX_DUAL:PMA_RX_CFG_0[22]
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[6] GTX_DUAL:PMA_RX_CFG_0[20] GTX_DUAL:DRP49[7] GTX_DUAL:PMA_RX_CFG_0[21]
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[5] GTX_DUAL:PMA_RX_CFG_0[19] GTX_DUAL:DRP49[4] GTX_DUAL:PMA_RX_CFG_0[18]
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[2] GTX_DUAL:PMA_RX_CFG_0[16] GTX_DUAL:DRP49[3] GTX_DUAL:PMA_RX_CFG_0[17]
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP49[1] GTX_DUAL:PMA_RX_CFG_0[15] GTX_DUAL:DRP49[0] GTX_DUAL:PMA_RX_CFG_0[14]
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[14] GTX_DUAL:RX_CDR_FORCE_ROTATE_0 GTX_DUAL:DRP48[15] GTX_DUAL:PMA_RX_CFG_0[13]
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[13] GTX_DUAL:PMA_RX_CFG_0[5] GTX_DUAL:DRP48[12] GTX_DUAL:PMA_RX_CFG_0[4]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[10] GTX_DUAL:PMA_RX_CFG_0[2] GTX_DUAL:DRP48[11] GTX_DUAL:PMA_RX_CFG_0[3]
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[9] GTX_DUAL:PMA_RX_CFG_1[23] GTX_DUAL:DRP48[8] GTX_DUAL:PMA_RX_CFG_0[10]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[6] GTX_DUAL:PMA_RX_CFG_0[8] GTX_DUAL:DRP48[7] GTX_DUAL:PMA_RX_CFG_0[9]
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:DRP48[5] GTX_DUAL:PMA_RX_CFG_0[7] GTX_DUAL:DRP48[4] GTX_DUAL:PMA_RX_CFG_0[6]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_0[1] GTX_DUAL:DRP48[2] GTX_DUAL:CHAN_BOND_SEQ_2_4_0[0] GTX_DUAL:DRP48[3]
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GTX_DUAL:CHAN_BOND_SEQ_2_4_0[2] GTX_DUAL:DRP48[1] GTX_DUAL:CHAN_BOND_SEQ_2_4_0[3] GTX_DUAL:DRP48[0]
virtex5 GTX rect R15
BitFrame
virtex5 GTX rect R16
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[11]
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[10]
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[9]
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[8]
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[7]
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[6]
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[5]
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[4]
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[3]
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[2]
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[1]
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[0]
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex5 GTX rect R17
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:ENABLE64
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[31] -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[30] -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[29] -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[28] -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[27] -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[26] -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[25] -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[24] -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[23] -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[22] -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[21] -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[20] -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[19] -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[18] -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[17] -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[16] -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[15]
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[14]
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[13]
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CRC32_3:CRC_INIT[12]
virtex5 GTX rect R18
BitFrame
virtex5 GTX rect R19
BitFrame
virtex5 GTX rect R20
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28
B15 - - - - - - - - - - - - - - - - - GTX_DUAL:USRCLK0 ~CRC32_0:INV.CRCCLK - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - ~CRC32_2:INV.CRCCLK - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - ~CRC32_3:INV.CRCCLK GTX_DUAL:INV.DCLK GTX_DUAL:INV.TXUSRCLK1 GTX_DUAL:INV.RXUSRCLK1 GTX_DUAL:INV.RXUSRCLK20 GTX_DUAL:INV.TXUSRCLK20 - - - - -
B12 - - - - - - - - - - - - - - - - - - GTX_DUAL:USRCLK1 ~CRC32_1:INV.CRCCLK GTX_DUAL:INV.TXUSRCLK21 GTX_DUAL:INV.RXUSRCLK21 GTX_DUAL:INV.RXUSRCLK0 GTX_DUAL:INV.TXUSRCLK0 - - - - GTX_DUAL:ENABLE
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
CRC32_0:CRC_INIT 2.F28.B24 2.F28.B26 2.F28.B28 2.F28.B30 2.F28.B32 2.F28.B35 2.F28.B36 2.F28.B39 2.F28.B41 2.F28.B43 2.F28.B45 2.F28.B47 2.F28.B49 2.F28.B51 2.F28.B53 2.F28.B55 2.F29.B57 2.F29.B59 2.F29.B61 2.F29.B63 3.F29.B1 3.F29.B3 3.F29.B5 3.F29.B8 3.F29.B10 3.F29.B12 3.F29.B14 3.F29.B16 3.F29.B18 3.F29.B20 3.F29.B22 3.F29.B24
CRC32_1:CRC_INIT 8.F28.B60 8.F29.B61 8.F28.B62 8.F29.B63 9.F28.B0 9.F29.B1 9.F28.B3 9.F29.B3 9.F28.B4 9.F29.B6 9.F28.B6 9.F29.B7 9.F28.B8 9.F28.B9 9.F29.B10 9.F28.B11 9.F29.B12 9.F28.B12 9.F29.B13 9.F28.B14 9.F29.B15 9.F28.B17 9.F29.B18 9.F28.B19 9.F29.B20 9.F28.B21 9.F29.B22 9.F28.B23 9.F29.B24 9.F28.B25 9.F29.B26 9.F29.B27
CRC32_2:CRC_INIT 11.F28.B3 11.F29.B2 11.F28.B1 11.F29.B0 10.F28.B63 10.F29.B62 10.F28.B60 10.F29.B60 10.F28.B59 10.F29.B57 10.F28.B57 10.F29.B56 10.F28.B55 10.F28.B54 10.F29.B53 10.F28.B52 10.F29.B51 10.F28.B51 10.F29.B50 10.F28.B49 10.F29.B48 10.F28.B46 10.F29.B45 10.F28.B44 10.F29.B43 10.F28.B42 10.F29.B41 10.F28.B40 10.F29.B39 10.F28.B38 10.F29.B37 10.F29.B36
CRC32_3:CRC_INIT 17.F28.B39 17.F28.B37 17.F28.B35 17.F28.B33 17.F28.B31 17.F28.B28 17.F28.B27 17.F28.B24 17.F28.B22 17.F28.B20 17.F28.B18 17.F28.B16 17.F28.B14 17.F28.B12 17.F28.B10 17.F28.B8 17.F29.B6 17.F29.B4 17.F29.B2 17.F29.B0 16.F29.B62 16.F29.B60 16.F29.B58 16.F29.B55 16.F29.B53 16.F29.B51 16.F29.B49 16.F29.B47 16.F29.B45 16.F29.B43 16.F29.B41 16.F29.B39
GTX_DUAL:PRBS_ERR_THRESHOLD_0 13.F31.B33 13.F30.B33 13.F30.B32 13.F31.B32 13.F31.B31 13.F30.B31 13.F30.B30 13.F31.B30 13.F31.B29 13.F30.B29 13.F30.B28 13.F31.B28 13.F31.B27 13.F30.B27 13.F30.B26 13.F31.B26 13.F31.B25 13.F30.B25 13.F30.B24 13.F31.B24 13.F31.B23 13.F30.B23 13.F30.B22 13.F31.B22 13.F31.B21 13.F30.B21 13.F30.B20 13.F31.B20 13.F31.B19 13.F30.B19 13.F30.B18 13.F31.B18
GTX_DUAL:PRBS_ERR_THRESHOLD_1 6.F31.B30 6.F30.B30 6.F30.B31 6.F31.B31 6.F31.B32 6.F30.B32 6.F30.B33 6.F31.B33 6.F31.B34 6.F30.B34 6.F30.B35 6.F31.B35 6.F31.B36 6.F30.B36 6.F30.B37 6.F31.B37 6.F31.B38 6.F30.B38 6.F30.B39 6.F31.B39 6.F31.B40 6.F30.B40 6.F30.B41 6.F31.B41 6.F31.B42 6.F30.B42 6.F30.B43 6.F31.B43 6.F31.B44 6.F30.B44 6.F30.B45 6.F31.B45
non-inverted [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
CRC32_0:ENABLE64 2.F29.B22
CRC32_3:ENABLE64 17.F29.B41
GTX_DUAL:AC_CAP_DIS_0 14.F30.B15
GTX_DUAL:AC_CAP_DIS_1 5.F30.B48
GTX_DUAL:CHAN_BOND_KEEP_ALIGN_0 14.F31.B42
GTX_DUAL:CHAN_BOND_KEEP_ALIGN_1 5.F31.B22
GTX_DUAL:CHAN_BOND_SEQ_2_USE_0 12.F30.B14
GTX_DUAL:CHAN_BOND_SEQ_2_USE_1 7.F30.B49
GTX_DUAL:CLKINDC_B 5.F31.B33
GTX_DUAL:CLKRCV_TRST 6.F31.B14
GTX_DUAL:CLK_CORRECT_USE_0 12.F31.B3
GTX_DUAL:CLK_CORRECT_USE_1 7.F31.B60
GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_0 12.F30.B11
GTX_DUAL:CLK_COR_INSERT_IDLE_FLAG_1 7.F30.B52
GTX_DUAL:CLK_COR_KEEP_IDLE_0 12.F30.B10
GTX_DUAL:CLK_COR_KEEP_IDLE_1 7.F30.B53
GTX_DUAL:CLK_COR_PRECEDENCE_0 12.F31.B4
GTX_DUAL:CLK_COR_PRECEDENCE_1 7.F31.B59
GTX_DUAL:CLK_COR_SEQ_2_USE_0 11.F30.B20
GTX_DUAL:CLK_COR_SEQ_2_USE_1 8.F30.B43
GTX_DUAL:COMMA_DOUBLE_0 11.F30.B13
GTX_DUAL:COMMA_DOUBLE_1 8.F30.B50
GTX_DUAL:DEC_MCOMMA_DETECT_0 11.F30.B12
GTX_DUAL:DEC_MCOMMA_DETECT_1 8.F30.B51
GTX_DUAL:DEC_PCOMMA_DETECT_0 11.F31.B12
GTX_DUAL:DEC_PCOMMA_DETECT_1 8.F31.B51
GTX_DUAL:DEC_VALID_COMMA_ONLY_0 11.F31.B11
GTX_DUAL:DEC_VALID_COMMA_ONLY_1 8.F31.B52
GTX_DUAL:ENABLE 20.F28.B12
GTX_DUAL:INV.DCLK 20.F19.B13
GTX_DUAL:INV.RXUSRCLK0 20.F22.B12
GTX_DUAL:INV.RXUSRCLK1 20.F21.B13
GTX_DUAL:INV.RXUSRCLK20 20.F22.B13
GTX_DUAL:INV.RXUSRCLK21 20.F21.B12
GTX_DUAL:INV.TXUSRCLK0 20.F23.B12
GTX_DUAL:INV.TXUSRCLK1 20.F20.B13
GTX_DUAL:INV.TXUSRCLK20 20.F23.B13
GTX_DUAL:INV.TXUSRCLK21 20.F20.B12
GTX_DUAL:MCOMMA_DETECT_0 11.F31.B6
GTX_DUAL:MCOMMA_DETECT_1 8.F31.B57
GTX_DUAL:OVERSAMPLE_MODE 9.F31.B55
GTX_DUAL:PCI_EXPRESS_MODE_0 13.F31.B55
GTX_DUAL:PCI_EXPRESS_MODE_1 6.F31.B8
GTX_DUAL:PCOMMA_DETECT_0 13.F31.B50
GTX_DUAL:PCOMMA_DETECT_1 6.F31.B13
GTX_DUAL:PLL_FB_DCCEN 11.F30.B1
GTX_DUAL:PLL_SATA_0 13.F30.B48
GTX_DUAL:PLL_SATA_1 6.F30.B15
GTX_DUAL:PLL_STARTUP_EN 14.F30.B21
GTX_DUAL:RCV_TERM_GND_0 14.F31.B16
GTX_DUAL:RCV_TERM_GND_1 5.F31.B47
GTX_DUAL:RCV_TERM_VTTRX_0 14.F30.B16
GTX_DUAL:RCV_TERM_VTTRX_1 5.F30.B47
GTX_DUAL:RXGEARBOX_USE_0 14.F31.B44
GTX_DUAL:RXGEARBOX_USE_1 5.F31.B20
GTX_DUAL:RX_BUFFER_USE_0 13.F31.B17
GTX_DUAL:RX_BUFFER_USE_1 6.F31.B46
GTX_DUAL:RX_CDR_FORCE_ROTATE_0 14.F30.B7
GTX_DUAL:RX_CDR_FORCE_ROTATE_1 5.F30.B56
GTX_DUAL:RX_DECODE_SEQ_MATCH_0 13.F30.B17
GTX_DUAL:RX_DECODE_SEQ_MATCH_1 6.F30.B46
GTX_DUAL:RX_EN_IDLE_HOLD_CDR 12.F30.B20
GTX_DUAL:RX_EN_IDLE_HOLD_DFE_0 14.F30.B32
GTX_DUAL:RX_EN_IDLE_HOLD_DFE_1 5.F30.B31
GTX_DUAL:RX_EN_IDLE_RESET_BUF_0 14.F31.B33
GTX_DUAL:RX_EN_IDLE_RESET_BUF_1 5.F31.B30
GTX_DUAL:RX_EN_IDLE_RESET_FR 12.F30.B21
GTX_DUAL:RX_EN_IDLE_RESET_PH 12.F30.B17
GTX_DUAL:RX_LOSS_OF_SYNC_FSM_0 13.F30.B15
GTX_DUAL:RX_LOSS_OF_SYNC_FSM_1 6.F30.B48
GTX_DUAL:TERMINATION_OVRD 10.F30.B11
GTX_DUAL:TXGEARBOX_USE_0 14.F30.B44
GTX_DUAL:TXGEARBOX_USE_1 5.F31.B19
GTX_DUAL:TXOUTCLK_SEL_0 12.F31.B19
GTX_DUAL:TXOUTCLK_SEL_1 7.F31.B44
GTX_DUAL:TX_BUFFER_USE_0 12.F31.B30
GTX_DUAL:TX_BUFFER_USE_1 7.F31.B33
GTX_DUAL:USRCLK0 20.F17.B15
GTX_DUAL:USRCLK1 20.F18.B12
non-inverted [0]
CRC32_0:INV.CRCCLK 20.F18.B15
CRC32_1:INV.CRCCLK 20.F19.B12
CRC32_2:INV.CRCCLK 20.F18.B14
CRC32_3:INV.CRCCLK 20.F18.B13
inverted ~[0]
GTX_DUAL:ALIGN_COMMA_WORD_0 10.F31.B30
GTX_DUAL:ALIGN_COMMA_WORD_1 9.F31.B33
1 0
2 1
GTX_DUAL:CB2_INH_CC_PERIOD_0 14.F31.B41 14.F30.B41 14.F30.B40 14.F31.B40
GTX_DUAL:CB2_INH_CC_PERIOD_1 5.F30.B22 5.F30.B23 5.F31.B23 5.F31.B24
GTX_DUAL:CHAN_BOND_1_MAX_SKEW_0 10.F30.B30 10.F30.B31 10.F31.B31 10.F31.B32
GTX_DUAL:CHAN_BOND_1_MAX_SKEW_1 9.F30.B33 9.F30.B32 9.F31.B32 9.F31.B31
GTX_DUAL:CHAN_BOND_2_MAX_SKEW_0 10.F30.B32 10.F30.B33 10.F31.B33 10.F31.B34
GTX_DUAL:CHAN_BOND_2_MAX_SKEW_1 9.F30.B31 9.F30.B30 9.F31.B30 9.F31.B29
GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_0 10.F30.B57 10.F31.B57 10.F31.B58 10.F30.B58
GTX_DUAL:CHAN_BOND_SEQ_1_ENABLE_1 9.F30.B6 9.F31.B6 9.F31.B5 9.F30.B5
GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_0 12.F30.B16 12.F31.B16 12.F31.B15 12.F30.B15
GTX_DUAL:CHAN_BOND_SEQ_2_ENABLE_1 7.F30.B47 7.F31.B47 7.F31.B48 7.F30.B48
GTX_DUAL:CLK_COR_SEQ_1_ENABLE_0 11.F30.B44 11.F31.B44 11.F31.B43 11.F30.B43
GTX_DUAL:CLK_COR_SEQ_1_ENABLE_1 8.F30.B19 8.F31.B19 8.F31.B20 8.F30.B20
GTX_DUAL:CLK_COR_SEQ_2_ENABLE_0 11.F30.B22 11.F31.B22 11.F31.B21 11.F30.B21
GTX_DUAL:CLK_COR_SEQ_2_ENABLE_1 8.F30.B41 8.F31.B41 8.F31.B42 8.F30.B42
GTX_DUAL:COM_BURST_VAL_0 11.F31.B20 11.F31.B19 11.F30.B19 11.F30.B18
GTX_DUAL:COM_BURST_VAL_1 8.F31.B43 8.F31.B44 8.F30.B44 8.F30.B45
GTX_DUAL:RX_IDLE_HI_CNT_0 14.F30.B36 14.F31.B36 14.F31.B35 14.F30.B35
GTX_DUAL:RX_IDLE_HI_CNT_1 5.F30.B27 5.F31.B27 5.F31.B28 5.F30.B28
GTX_DUAL:RX_IDLE_LO_CNT_0 14.F31.B39 14.F30.B39 14.F30.B38 14.F31.B38
GTX_DUAL:RX_IDLE_LO_CNT_1 5.F30.B24 5.F30.B25 5.F31.B25 5.F31.B26
non-inverted [3] [2] [1] [0]
GTX_DUAL:CDR_PH_ADJ_TIME 12.F31.B41 12.F30.B41 12.F30.B40 12.F31.B40 12.F31.B39
GTX_DUAL:CLK_COR_REPEAT_WAIT_0 12.F30.B3 12.F30.B2 12.F31.B2 12.F31.B1 12.F30.B1
GTX_DUAL:CLK_COR_REPEAT_WAIT_1 7.F30.B60 7.F30.B61 7.F31.B61 7.F31.B62 7.F30.B62
GTX_DUAL:DFE_CAL_TIME 12.F30.B33 12.F30.B32 12.F31.B32 12.F31.B31 12.F30.B31
GTX_DUAL:TERMINATION_CTRL 10.F30.B8 10.F30.B9 10.F31.B9 10.F31.B10 10.F30.B10
non-inverted [4] [3] [2] [1] [0]
GTX_DUAL:CHAN_BOND_LEVEL_0 10.F30.B34 10.F30.B35 10.F31.B35
GTX_DUAL:CHAN_BOND_LEVEL_1 9.F30.B29 9.F30.B28 9.F31.B28
GTX_DUAL:GEARBOX_ENDEC_0 14.F31.B43 14.F30.B43 14.F30.B42
GTX_DUAL:GEARBOX_ENDEC_1 5.F30.B20 5.F30.B21 5.F31.B21
GTX_DUAL:OOBDETECT_THRESHOLD_0 12.F30.B18 12.F31.B18 12.F31.B17
GTX_DUAL:OOBDETECT_THRESHOLD_1 7.F30.B45 7.F31.B45 7.F31.B46
GTX_DUAL:PLL_LKDET_CFG 5.F31.B39 5.F31.B40 5.F30.B40
GTX_DUAL:PLL_TDCC_CFG 14.F31.B24 14.F30.B23 14.F31.B23
GTX_DUAL:SATA_BURST_VAL_0 13.F31.B11 13.F30.B11 13.F30.B10
GTX_DUAL:SATA_BURST_VAL_1 6.F31.B52 6.F30.B52 6.F30.B53
GTX_DUAL:SATA_IDLE_VAL_0 13.F31.B10 13.F31.B9 13.F30.B9
GTX_DUAL:SATA_IDLE_VAL_1 6.F31.B53 6.F31.B54 6.F30.B54
GTX_DUAL:TXRX_INVERT_0 12.F30.B22 12.F31.B22 12.F31.B21
GTX_DUAL:TXRX_INVERT_1 7.F30.B41 7.F31.B41 7.F31.B42
GTX_DUAL:TX_IDLE_DELAY_0 14.F31.B28 14.F31.B27 14.F30.B27
GTX_DUAL:TX_IDLE_DELAY_1 5.F31.B31 5.F31.B32 5.F30.B32
non-inverted [2] [1] [0]
GTX_DUAL:CHAN_BOND_MODE_0 10.F30.B36 10.F31.B36
GTX_DUAL:CHAN_BOND_MODE_1 9.F30.B27 9.F31.B27
#OFF 0 0
SLAVE 0 1
MASTER 1 0
GTX_DUAL:CHAN_BOND_SEQ_1_1_0 10.F30.B37 10.F31.B37 10.F31.B38 10.F30.B38 10.F30.B39 10.F31.B39 10.F31.B40 10.F30.B40 10.F30.B41 10.F31.B41
GTX_DUAL:CHAN_BOND_SEQ_1_1_1 9.F30.B26 9.F31.B26 9.F31.B25 9.F30.B25 9.F30.B24 9.F31.B24 9.F31.B23 9.F30.B23 9.F30.B22 9.F31.B22
GTX_DUAL:CHAN_BOND_SEQ_1_2_0 10.F31.B42 10.F30.B42 10.F30.B43 10.F31.B43 10.F31.B44 10.F30.B44 10.F30.B45 10.F31.B45 10.F31.B46 10.F30.B46
GTX_DUAL:CHAN_BOND_SEQ_1_2_1 9.F31.B21 9.F30.B21 9.F30.B20 9.F31.B20 9.F31.B19 9.F30.B19 9.F30.B18 9.F31.B18 9.F31.B17 9.F30.B17
GTX_DUAL:CHAN_BOND_SEQ_1_3_0 10.F30.B47 10.F31.B47 10.F31.B48 10.F30.B48 10.F30.B49 10.F31.B49 10.F31.B50 10.F30.B50 10.F30.B51 10.F31.B51
GTX_DUAL:CHAN_BOND_SEQ_1_3_1 9.F30.B16 9.F31.B16 9.F31.B15 9.F30.B15 9.F30.B14 9.F31.B14 9.F31.B13 9.F30.B13 9.F30.B12 9.F31.B12
GTX_DUAL:CHAN_BOND_SEQ_1_4_0 10.F31.B52 10.F30.B52 10.F30.B53 10.F31.B53 10.F31.B54 10.F30.B54 10.F30.B55 10.F31.B55 10.F31.B56 10.F30.B56
GTX_DUAL:CHAN_BOND_SEQ_1_4_1 9.F31.B11 9.F30.B11 9.F30.B10 9.F31.B10 9.F31.B9 9.F30.B9 9.F30.B8 9.F31.B8 9.F31.B7 9.F30.B7
GTX_DUAL:CHAN_BOND_SEQ_2_1_0 10.F30.B59 10.F31.B59 10.F31.B60 10.F30.B60 10.F30.B61 10.F31.B61 10.F31.B62 10.F30.B62 10.F30.B63 10.F31.B63
GTX_DUAL:CHAN_BOND_SEQ_2_1_1 9.F30.B4 9.F31.B4 9.F31.B3 9.F30.B3 9.F30.B2 9.F31.B2 9.F31.B1 9.F30.B1 9.F30.B0 9.F31.B0
GTX_DUAL:CHAN_BOND_SEQ_2_2_0 11.F31.B0 11.F30.B0 11.F31.B1 11.F31.B2 11.F30.B2 11.F30.B3 11.F31.B3 11.F31.B4 11.F30.B4 11.F30.B5
GTX_DUAL:CHAN_BOND_SEQ_2_2_1 8.F31.B63 8.F30.B63 8.F31.B62 8.F31.B61 8.F30.B61 8.F30.B60 8.F31.B60 8.F31.B59 8.F30.B59 8.F30.B58
GTX_DUAL:CHAN_BOND_SEQ_2_3_0 11.F31.B5 13.F30.B56 13.F30.B57 13.F31.B57 13.F31.B58 13.F30.B58 13.F30.B59 13.F31.B59 13.F31.B60 13.F30.B60
GTX_DUAL:CHAN_BOND_SEQ_2_3_1 8.F31.B58 6.F30.B7 6.F30.B6 6.F31.B6 6.F31.B5 6.F30.B5 6.F30.B4 6.F31.B4 6.F31.B3 6.F30.B3
GTX_DUAL:CHAN_BOND_SEQ_2_4_0 13.F30.B61 13.F31.B61 13.F31.B62 13.F30.B62 13.F30.B63 13.F31.B63 14.F31.B0 14.F30.B0 14.F30.B1 14.F31.B1
GTX_DUAL:CHAN_BOND_SEQ_2_4_1 6.F30.B2 6.F31.B2 6.F31.B1 6.F30.B1 6.F30.B0 6.F31.B0 5.F31.B63 5.F30.B63 5.F30.B62 5.F31.B62
GTX_DUAL:CLK_COR_SEQ_1_1_0 12.F30.B0 12.F31.B0 11.F31.B63 11.F30.B63 11.F30.B62 11.F31.B62 11.F31.B61 11.F30.B61 11.F30.B60 11.F31.B60
GTX_DUAL:CLK_COR_SEQ_1_1_1 7.F30.B63 7.F31.B63 8.F31.B0 8.F30.B0 8.F30.B1 8.F31.B1 8.F31.B2 8.F30.B2 8.F30.B3 8.F31.B3
GTX_DUAL:CLK_COR_SEQ_1_2_0 11.F31.B59 11.F30.B59 11.F30.B58 11.F31.B58 11.F31.B57 11.F30.B57 11.F30.B56 11.F31.B56 11.F31.B55 11.F30.B55
GTX_DUAL:CLK_COR_SEQ_1_2_1 8.F31.B4 8.F30.B4 8.F30.B5 8.F31.B5 8.F31.B6 8.F30.B6 8.F30.B7 8.F31.B7 8.F31.B8 8.F30.B8
GTX_DUAL:CLK_COR_SEQ_1_3_0 11.F30.B54 11.F31.B54 11.F31.B53 11.F30.B53 11.F30.B52 11.F31.B52 11.F31.B51 11.F30.B51 11.F30.B50 11.F31.B50
GTX_DUAL:CLK_COR_SEQ_1_3_1 8.F30.B9 8.F31.B9 8.F31.B10 8.F30.B10 8.F30.B11 8.F31.B11 8.F31.B12 8.F30.B12 8.F30.B13 8.F31.B13
GTX_DUAL:CLK_COR_SEQ_1_4_0 11.F31.B49 11.F30.B49 11.F30.B48 11.F31.B48 11.F31.B47 11.F30.B47 11.F30.B46 11.F31.B46 11.F31.B45 11.F30.B45
GTX_DUAL:CLK_COR_SEQ_1_4_1 8.F31.B14 8.F30.B14 8.F30.B15 8.F31.B15 8.F31.B16 8.F30.B16 8.F30.B17 8.F31.B17 8.F31.B18 8.F30.B18
GTX_DUAL:CLK_COR_SEQ_2_1_0 11.F30.B42 11.F31.B42 11.F31.B41 11.F30.B41 11.F30.B40 11.F31.B40 11.F31.B39 11.F30.B39 11.F30.B38 11.F31.B38
GTX_DUAL:CLK_COR_SEQ_2_1_1 8.F30.B21 8.F31.B21 8.F31.B22 8.F30.B22 8.F30.B23 8.F31.B23 8.F31.B24 8.F30.B24 8.F30.B25 8.F31.B25
GTX_DUAL:CLK_COR_SEQ_2_2_0 11.F31.B37 11.F30.B37 11.F30.B36 11.F31.B36 11.F31.B35 11.F30.B35 11.F30.B34 11.F31.B34 11.F31.B33 11.F30.B33
GTX_DUAL:CLK_COR_SEQ_2_2_1 8.F31.B26 8.F30.B26 8.F30.B27 8.F31.B27 8.F31.B28 8.F30.B28 8.F30.B29 8.F31.B29 8.F31.B30 8.F30.B30
GTX_DUAL:CLK_COR_SEQ_2_3_0 11.F30.B32 11.F31.B32 11.F31.B31 11.F30.B31 11.F30.B30 11.F31.B30 11.F31.B29 11.F30.B29 11.F30.B28 11.F31.B28
GTX_DUAL:CLK_COR_SEQ_2_3_1 8.F30.B31 8.F31.B31 8.F31.B32 8.F30.B32 8.F30.B33 8.F31.B33 8.F31.B34 8.F30.B34 8.F30.B35 8.F31.B35
GTX_DUAL:CLK_COR_SEQ_2_4_0 11.F31.B27 11.F30.B27 11.F30.B26 11.F31.B26 11.F31.B25 11.F30.B25 11.F30.B24 11.F31.B24 11.F31.B23 11.F30.B23
GTX_DUAL:CLK_COR_SEQ_2_4_1 8.F31.B36 8.F30.B36 8.F30.B37 8.F31.B37 8.F31.B38 8.F30.B38 8.F30.B39 8.F31.B39 8.F31.B40 8.F30.B40
GTX_DUAL:COMMA_10B_ENABLE_0 11.F31.B18 11.F31.B17 11.F30.B17 11.F30.B16 11.F31.B16 11.F31.B15 11.F30.B15 11.F30.B14 11.F31.B14 11.F31.B13
GTX_DUAL:COMMA_10B_ENABLE_1 8.F31.B45 8.F31.B46 8.F30.B46 8.F30.B47 8.F31.B47 8.F31.B48 8.F30.B48 8.F30.B49 8.F31.B49 8.F31.B50
GTX_DUAL:DFE_CFG_0 14.F31.B49 14.F30.B49 14.F30.B48 14.F31.B48 14.F31.B47 14.F30.B47 14.F30.B46 14.F31.B46 14.F31.B45 14.F30.B45
GTX_DUAL:DFE_CFG_1 5.F30.B14 5.F30.B15 5.F31.B15 5.F31.B16 5.F30.B16 5.F30.B17 5.F31.B17 5.F31.B18 5.F30.B18 5.F30.B19
GTX_DUAL:MCOMMA_10B_VALUE_0 11.F30.B11 11.F30.B10 11.F31.B10 11.F31.B9 11.F30.B9 11.F30.B8 11.F31.B8 11.F31.B7 11.F30.B7 11.F30.B6
GTX_DUAL:MCOMMA_10B_VALUE_1 8.F30.B52 8.F30.B53 8.F31.B53 8.F31.B54 8.F30.B54 8.F30.B55 8.F31.B55 8.F31.B56 8.F30.B56 8.F30.B57
GTX_DUAL:PCOMMA_10B_VALUE_0 13.F30.B55 13.F30.B54 13.F31.B54 13.F31.B53 13.F30.B53 13.F30.B52 13.F31.B52 13.F31.B51 13.F30.B51 13.F30.B50
GTX_DUAL:PCOMMA_10B_VALUE_1 6.F30.B8 6.F30.B9 6.F31.B9 6.F31.B10 6.F30.B10 6.F30.B11 6.F31.B11 6.F31.B12 6.F30.B12 6.F30.B13
GTX_DUAL:TRANS_TIME_TO_P2_0 12.F31.B38 12.F31.B37 12.F30.B37 12.F30.B36 12.F31.B36 12.F31.B35 12.F30.B35 12.F30.B34 12.F31.B34 12.F31.B33
GTX_DUAL:TRANS_TIME_TO_P2_1 7.F31.B25 7.F31.B26 7.F30.B26 7.F30.B27 7.F31.B27 7.F31.B28 7.F30.B28 7.F30.B29 7.F31.B29 7.F31.B30
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:CHAN_BOND_SEQ_LEN_0 12.F31.B14 12.F31.B13
GTX_DUAL:CHAN_BOND_SEQ_LEN_1 7.F31.B49 7.F31.B50
GTX_DUAL:CLK_COR_ADJ_LEN_0 12.F30.B13 12.F30.B12
GTX_DUAL:CLK_COR_ADJ_LEN_1 7.F30.B50 7.F30.B51
GTX_DUAL:CLK_COR_DET_LEN_0 12.F31.B12 12.F31.B11
GTX_DUAL:CLK_COR_DET_LEN_1 7.F31.B51 7.F31.B52
1 0 0
2 0 1
3 1 0
4 1 1
GTX_DUAL:CLK25_DIVIDER 9.F30.B52 9.F30.B53 9.F31.B53
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
10 1 1 0
12 1 1 1
GTX_DUAL:CLK_COR_MAX_LAT_0 12.F31.B10 12.F31.B9 12.F30.B9 12.F30.B8 12.F31.B8 12.F31.B7
GTX_DUAL:CLK_COR_MAX_LAT_1 7.F31.B53 7.F31.B54 7.F30.B54 7.F30.B55 7.F31.B55 7.F31.B56
GTX_DUAL:CLK_COR_MIN_LAT_0 12.F30.B7 12.F30.B6 12.F31.B6 12.F31.B5 12.F30.B5 12.F30.B4
GTX_DUAL:CLK_COR_MIN_LAT_1 7.F30.B56 7.F30.B57 7.F31.B57 7.F31.B58 7.F30.B58 7.F30.B59
GTX_DUAL:SATA_MAX_BURST_0 13.F30.B8 13.F31.B8 13.F31.B7 13.F30.B7 13.F30.B6 13.F31.B6
GTX_DUAL:SATA_MAX_BURST_1 6.F30.B55 6.F31.B55 6.F31.B56 6.F30.B56 6.F30.B57 6.F31.B57
GTX_DUAL:SATA_MAX_INIT_0 13.F31.B5 13.F30.B5 13.F30.B4 13.F31.B4 13.F31.B3 13.F30.B3
GTX_DUAL:SATA_MAX_INIT_1 6.F31.B58 6.F30.B58 6.F30.B59 6.F31.B59 6.F31.B60 6.F30.B60
GTX_DUAL:SATA_MAX_WAKE_0 13.F30.B2 13.F31.B2 13.F31.B1 13.F30.B1 13.F30.B0 13.F31.B0
GTX_DUAL:SATA_MAX_WAKE_1 6.F30.B61 6.F31.B61 6.F31.B62 6.F30.B62 6.F30.B63 6.F31.B63
GTX_DUAL:SATA_MIN_BURST_0 12.F31.B63 12.F30.B63 12.F30.B62 12.F31.B62 12.F31.B61 12.F30.B61
GTX_DUAL:SATA_MIN_BURST_1 7.F31.B0 7.F30.B0 7.F30.B1 7.F31.B1 7.F31.B2 7.F30.B2
GTX_DUAL:SATA_MIN_INIT_0 12.F30.B60 12.F31.B60 12.F31.B59 12.F30.B59 12.F30.B58 12.F31.B58
GTX_DUAL:SATA_MIN_INIT_1 7.F30.B3 7.F31.B3 7.F31.B4 7.F30.B4 7.F30.B5 7.F31.B5
GTX_DUAL:SATA_MIN_WAKE_0 12.F31.B57 12.F30.B57 12.F30.B56 12.F31.B56 12.F31.B55 12.F30.B55
GTX_DUAL:SATA_MIN_WAKE_1 7.F31.B6 7.F30.B6 7.F30.B7 7.F31.B7 7.F31.B8 7.F30.B8
non-inverted [5] [4] [3] [2] [1] [0]
GTX_DUAL:CM_TRIM_0 14.F30.B50 14.F31.B50
GTX_DUAL:CM_TRIM_1 5.F31.B13 5.F31.B14
non-inverted [1] [0]
GTX_DUAL:DRP00 5.F31.B7 5.F30.B7 5.F30.B6 5.F31.B6 5.F31.B5 5.F30.B5 5.F30.B4 5.F31.B4 5.F31.B3 5.F30.B3 5.F30.B2 5.F31.B2 5.F31.B1 5.F30.B1 5.F30.B0 5.F31.B0
GTX_DUAL:DRP01 5.F31.B15 5.F30.B15 5.F30.B14 5.F31.B14 5.F31.B13 5.F30.B13 5.F30.B12 5.F31.B12 5.F31.B11 5.F30.B11 5.F30.B10 5.F31.B10 5.F31.B9 5.F30.B9 5.F30.B8 5.F31.B8
GTX_DUAL:DRP02 5.F31.B23 5.F30.B23 5.F30.B22 5.F31.B22 5.F31.B21 5.F30.B21 5.F30.B20 5.F31.B20 5.F31.B19 5.F30.B19 5.F30.B18 5.F31.B18 5.F31.B17 5.F30.B17 5.F30.B16 5.F31.B16
GTX_DUAL:DRP03 5.F31.B31 5.F30.B31 5.F30.B30 5.F31.B30 5.F31.B29 5.F30.B29 5.F30.B28 5.F31.B28 5.F31.B27 5.F30.B27 5.F30.B26 5.F31.B26 5.F31.B25 5.F30.B25 5.F30.B24 5.F31.B24
GTX_DUAL:DRP04 5.F31.B39 5.F30.B39 5.F30.B38 5.F31.B38 5.F31.B37 5.F30.B37 5.F30.B36 5.F31.B36 5.F31.B35 5.F30.B35 5.F30.B34 5.F31.B34 5.F31.B33 5.F30.B33 5.F30.B32 5.F31.B32
GTX_DUAL:DRP05 5.F31.B47 5.F30.B47 5.F30.B46 5.F31.B46 5.F31.B45 5.F30.B45 5.F30.B44 5.F31.B44 5.F31.B43 5.F30.B43 5.F30.B42 5.F31.B42 5.F31.B41 5.F30.B41 5.F30.B40 5.F31.B40
GTX_DUAL:DRP06 5.F31.B55 5.F30.B55 5.F30.B54 5.F31.B54 5.F31.B53 5.F30.B53 5.F30.B52 5.F31.B52 5.F31.B51 5.F30.B51 5.F30.B50 5.F31.B50 5.F31.B49 5.F30.B49 5.F30.B48 5.F31.B48
GTX_DUAL:DRP07 5.F31.B63 5.F30.B63 5.F30.B62 5.F31.B62 5.F31.B61 5.F30.B61 5.F30.B60 5.F31.B60 5.F31.B59 5.F30.B59 5.F30.B58 5.F31.B58 5.F31.B57 5.F30.B57 5.F30.B56 5.F31.B56
GTX_DUAL:DRP08 6.F31.B7 6.F30.B7 6.F30.B6 6.F31.B6 6.F31.B5 6.F30.B5 6.F30.B4 6.F31.B4 6.F31.B3 6.F30.B3 6.F30.B2 6.F31.B2 6.F31.B1 6.F30.B1 6.F30.B0 6.F31.B0
GTX_DUAL:DRP09 6.F31.B15 6.F30.B15 6.F30.B14 6.F31.B14 6.F31.B13 6.F30.B13 6.F30.B12 6.F31.B12 6.F31.B11 6.F30.B11 6.F30.B10 6.F31.B10 6.F31.B9 6.F30.B9 6.F30.B8 6.F31.B8
GTX_DUAL:DRP0A 6.F31.B23 6.F30.B23 6.F30.B22 6.F31.B22 6.F31.B21 6.F30.B21 6.F30.B20 6.F31.B20 6.F31.B19 6.F30.B19 6.F30.B18 6.F31.B18 6.F31.B17 6.F30.B17 6.F30.B16 6.F31.B16
GTX_DUAL:DRP0B 6.F31.B31 6.F30.B31 6.F30.B30 6.F31.B30 6.F31.B29 6.F30.B29 6.F30.B28 6.F31.B28 6.F31.B27 6.F30.B27 6.F30.B26 6.F31.B26 6.F31.B25 6.F30.B25 6.F30.B24 6.F31.B24
GTX_DUAL:DRP0C 6.F31.B39 6.F30.B39 6.F30.B38 6.F31.B38 6.F31.B37 6.F30.B37 6.F30.B36 6.F31.B36 6.F31.B35 6.F30.B35 6.F30.B34 6.F31.B34 6.F31.B33 6.F30.B33 6.F30.B32 6.F31.B32
GTX_DUAL:DRP0D 6.F31.B47 6.F30.B47 6.F30.B46 6.F31.B46 6.F31.B45 6.F30.B45 6.F30.B44 6.F31.B44 6.F31.B43 6.F30.B43 6.F30.B42 6.F31.B42 6.F31.B41 6.F30.B41 6.F30.B40 6.F31.B40
GTX_DUAL:DRP0E 6.F31.B55 6.F30.B55 6.F30.B54 6.F31.B54 6.F31.B53 6.F30.B53 6.F30.B52 6.F31.B52 6.F31.B51 6.F30.B51 6.F30.B50 6.F31.B50 6.F31.B49 6.F30.B49 6.F30.B48 6.F31.B48
GTX_DUAL:DRP0F 6.F31.B63 6.F30.B63 6.F30.B62 6.F31.B62 6.F31.B61 6.F30.B61 6.F30.B60 6.F31.B60 6.F31.B59 6.F30.B59 6.F30.B58 6.F31.B58 6.F31.B57 6.F30.B57 6.F30.B56 6.F31.B56
GTX_DUAL:DRP10 7.F31.B7 7.F30.B7 7.F30.B6 7.F31.B6 7.F31.B5 7.F30.B5 7.F30.B4 7.F31.B4 7.F31.B3 7.F30.B3 7.F30.B2 7.F31.B2 7.F31.B1 7.F30.B1 7.F30.B0 7.F31.B0
GTX_DUAL:DRP11 7.F31.B15 7.F30.B15 7.F30.B14 7.F31.B14 7.F31.B13 7.F30.B13 7.F30.B12 7.F31.B12 7.F31.B11 7.F30.B11 7.F30.B10 7.F31.B10 7.F31.B9 7.F30.B9 7.F30.B8 7.F31.B8
GTX_DUAL:DRP12 7.F31.B23 7.F30.B23 7.F30.B22 7.F31.B22 7.F31.B21 7.F30.B21 7.F30.B20 7.F31.B20 7.F31.B19 7.F30.B19 7.F30.B18 7.F31.B18 7.F31.B17 7.F30.B17 7.F30.B16 7.F31.B16
GTX_DUAL:DRP13 7.F31.B31 7.F30.B31 7.F30.B30 7.F31.B30 7.F31.B29 7.F30.B29 7.F30.B28 7.F31.B28 7.F31.B27 7.F30.B27 7.F30.B26 7.F31.B26 7.F31.B25 7.F30.B25 7.F30.B24 7.F31.B24
GTX_DUAL:DRP14 7.F31.B39 7.F30.B39 7.F30.B38 7.F31.B38 7.F31.B37 7.F30.B37 7.F30.B36 7.F31.B36 7.F31.B35 7.F30.B35 7.F30.B34 7.F31.B34 7.F31.B33 7.F30.B33 7.F30.B32 7.F31.B32
GTX_DUAL:DRP15 7.F31.B47 7.F30.B47 7.F30.B46 7.F31.B46 7.F31.B45 7.F30.B45 7.F30.B44 7.F31.B44 7.F31.B43 7.F30.B43 7.F30.B42 7.F31.B42 7.F31.B41 7.F30.B41 7.F30.B40 7.F31.B40
GTX_DUAL:DRP16 7.F31.B55 7.F30.B55 7.F30.B54 7.F31.B54 7.F31.B53 7.F30.B53 7.F30.B52 7.F31.B52 7.F31.B51 7.F30.B51 7.F30.B50 7.F31.B50 7.F31.B49 7.F30.B49 7.F30.B48 7.F31.B48
GTX_DUAL:DRP17 7.F31.B63 7.F30.B63 7.F30.B62 7.F31.B62 7.F31.B61 7.F30.B61 7.F30.B60 7.F31.B60 7.F31.B59 7.F30.B59 7.F30.B58 7.F31.B58 7.F31.B57 7.F30.B57 7.F30.B56 7.F31.B56
GTX_DUAL:DRP18 8.F31.B7 8.F30.B7 8.F30.B6 8.F31.B6 8.F31.B5 8.F30.B5 8.F30.B4 8.F31.B4 8.F31.B3 8.F30.B3 8.F30.B2 8.F31.B2 8.F31.B1 8.F30.B1 8.F30.B0 8.F31.B0
GTX_DUAL:DRP19 8.F31.B15 8.F30.B15 8.F30.B14 8.F31.B14 8.F31.B13 8.F30.B13 8.F30.B12 8.F31.B12 8.F31.B11 8.F30.B11 8.F30.B10 8.F31.B10 8.F31.B9 8.F30.B9 8.F30.B8 8.F31.B8
GTX_DUAL:DRP1A 8.F31.B23 8.F30.B23 8.F30.B22 8.F31.B22 8.F31.B21 8.F30.B21 8.F30.B20 8.F31.B20 8.F31.B19 8.F30.B19 8.F30.B18 8.F31.B18 8.F31.B17 8.F30.B17 8.F30.B16 8.F31.B16
GTX_DUAL:DRP1B 8.F31.B31 8.F30.B31 8.F30.B30 8.F31.B30 8.F31.B29 8.F30.B29 8.F30.B28 8.F31.B28 8.F31.B27 8.F30.B27 8.F30.B26 8.F31.B26 8.F31.B25 8.F30.B25 8.F30.B24 8.F31.B24
GTX_DUAL:DRP1C 8.F31.B39 8.F30.B39 8.F30.B38 8.F31.B38 8.F31.B37 8.F30.B37 8.F30.B36 8.F31.B36 8.F31.B35 8.F30.B35 8.F30.B34 8.F31.B34 8.F31.B33 8.F30.B33 8.F30.B32 8.F31.B32
GTX_DUAL:DRP1D 8.F31.B47 8.F30.B47 8.F30.B46 8.F31.B46 8.F31.B45 8.F30.B45 8.F30.B44 8.F31.B44 8.F31.B43 8.F30.B43 8.F30.B42 8.F31.B42 8.F31.B41 8.F30.B41 8.F30.B40 8.F31.B40
GTX_DUAL:DRP1E 8.F31.B55 8.F30.B55 8.F30.B54 8.F31.B54 8.F31.B53 8.F30.B53 8.F30.B52 8.F31.B52 8.F31.B51 8.F30.B51 8.F30.B50 8.F31.B50 8.F31.B49 8.F30.B49 8.F30.B48 8.F31.B48
GTX_DUAL:DRP1F 8.F31.B63 8.F30.B63 8.F30.B62 8.F31.B62 8.F31.B61 8.F30.B61 8.F30.B60 8.F31.B60 8.F31.B59 8.F30.B59 8.F30.B58 8.F31.B58 8.F31.B57 8.F30.B57 8.F30.B56 8.F31.B56
GTX_DUAL:DRP20 9.F31.B7 9.F30.B7 9.F30.B6 9.F31.B6 9.F31.B5 9.F30.B5 9.F30.B4 9.F31.B4 9.F31.B3 9.F30.B3 9.F30.B2 9.F31.B2 9.F31.B1 9.F30.B1 9.F30.B0 9.F31.B0
GTX_DUAL:DRP21 9.F31.B15 9.F30.B15 9.F30.B14 9.F31.B14 9.F31.B13 9.F30.B13 9.F30.B12 9.F31.B12 9.F31.B11 9.F30.B11 9.F30.B10 9.F31.B10 9.F31.B9 9.F30.B9 9.F30.B8 9.F31.B8
GTX_DUAL:DRP22 9.F31.B23 9.F30.B23 9.F30.B22 9.F31.B22 9.F31.B21 9.F30.B21 9.F30.B20 9.F31.B20 9.F31.B19 9.F30.B19 9.F30.B18 9.F31.B18 9.F31.B17 9.F30.B17 9.F30.B16 9.F31.B16
GTX_DUAL:DRP23 9.F31.B31 9.F30.B31 9.F30.B30 9.F31.B30 9.F31.B29 9.F30.B29 9.F30.B28 9.F31.B28 9.F31.B27 9.F30.B27 9.F30.B26 9.F31.B26 9.F31.B25 9.F30.B25 9.F30.B24 9.F31.B24
GTX_DUAL:DRP24 9.F31.B39 9.F30.B39 9.F30.B38 9.F31.B38 9.F31.B37 9.F30.B37 9.F30.B36 9.F31.B36 9.F31.B35 9.F30.B35 9.F30.B34 9.F31.B34 9.F31.B33 9.F30.B33 9.F30.B32 9.F31.B32
GTX_DUAL:DRP25 9.F31.B47 9.F30.B47 9.F30.B46 9.F31.B46 9.F31.B45 9.F30.B45 9.F30.B44 9.F31.B44 9.F31.B43 9.F30.B43 9.F30.B42 9.F31.B42 9.F31.B41 9.F30.B41 9.F30.B40 9.F31.B40
GTX_DUAL:DRP26 9.F31.B55 9.F30.B55 9.F30.B54 9.F31.B54 9.F31.B53 9.F30.B53 9.F30.B52 9.F31.B52 9.F31.B51 9.F30.B51 9.F30.B50 9.F31.B50 9.F31.B49 9.F30.B49 9.F30.B48 9.F31.B48
GTX_DUAL:DRP27 9.F31.B63 9.F30.B63 9.F30.B62 9.F31.B62 9.F31.B61 9.F30.B61 9.F30.B60 9.F31.B60 9.F31.B59 9.F30.B59 9.F30.B58 9.F31.B58 9.F31.B57 9.F30.B57 9.F30.B56 9.F31.B56
GTX_DUAL:DRP28 10.F31.B7 10.F30.B7 10.F30.B6 10.F31.B6 10.F31.B5 10.F30.B5 10.F30.B4 10.F31.B4 10.F31.B3 10.F30.B3 10.F30.B2 10.F31.B2 10.F31.B1 10.F30.B1 10.F30.B0 10.F31.B0
GTX_DUAL:DRP29 10.F31.B15 10.F30.B15 10.F30.B14 10.F31.B14 10.F31.B13 10.F30.B13 10.F30.B12 10.F31.B12 10.F31.B11 10.F30.B11 10.F30.B10 10.F31.B10 10.F31.B9 10.F30.B9 10.F30.B8 10.F31.B8
GTX_DUAL:DRP2A 10.F31.B23 10.F30.B23 10.F30.B22 10.F31.B22 10.F31.B21 10.F30.B21 10.F30.B20 10.F31.B20 10.F31.B19 10.F30.B19 10.F30.B18 10.F31.B18 10.F31.B17 10.F30.B17 10.F30.B16 10.F31.B16
GTX_DUAL:DRP2B 10.F31.B31 10.F30.B31 10.F30.B30 10.F31.B30 10.F31.B29 10.F30.B29 10.F30.B28 10.F31.B28 10.F31.B27 10.F30.B27 10.F30.B26 10.F31.B26 10.F31.B25 10.F30.B25 10.F30.B24 10.F31.B24
GTX_DUAL:DRP2C 10.F31.B39 10.F30.B39 10.F30.B38 10.F31.B38 10.F31.B37 10.F30.B37 10.F30.B36 10.F31.B36 10.F31.B35 10.F30.B35 10.F30.B34 10.F31.B34 10.F31.B33 10.F30.B33 10.F30.B32 10.F31.B32
GTX_DUAL:DRP2D 10.F31.B47 10.F30.B47 10.F30.B46 10.F31.B46 10.F31.B45 10.F30.B45 10.F30.B44 10.F31.B44 10.F31.B43 10.F30.B43 10.F30.B42 10.F31.B42 10.F31.B41 10.F30.B41 10.F30.B40 10.F31.B40
GTX_DUAL:DRP2E 10.F31.B55 10.F30.B55 10.F30.B54 10.F31.B54 10.F31.B53 10.F30.B53 10.F30.B52 10.F31.B52 10.F31.B51 10.F30.B51 10.F30.B50 10.F31.B50 10.F31.B49 10.F30.B49 10.F30.B48 10.F31.B48
GTX_DUAL:DRP2F 10.F31.B63 10.F30.B63 10.F30.B62 10.F31.B62 10.F31.B61 10.F30.B61 10.F30.B60 10.F31.B60 10.F31.B59 10.F30.B59 10.F30.B58 10.F31.B58 10.F31.B57 10.F30.B57 10.F30.B56 10.F31.B56
GTX_DUAL:DRP30 11.F31.B7 11.F30.B7 11.F30.B6 11.F31.B6 11.F31.B5 11.F30.B5 11.F30.B4 11.F31.B4 11.F31.B3 11.F30.B3 11.F30.B2 11.F31.B2 11.F31.B1 11.F30.B1 11.F30.B0 11.F31.B0
GTX_DUAL:DRP31 11.F31.B15 11.F30.B15 11.F30.B14 11.F31.B14 11.F31.B13 11.F30.B13 11.F30.B12 11.F31.B12 11.F31.B11 11.F30.B11 11.F30.B10 11.F31.B10 11.F31.B9 11.F30.B9 11.F30.B8 11.F31.B8
GTX_DUAL:DRP32 11.F31.B23 11.F30.B23 11.F30.B22 11.F31.B22 11.F31.B21 11.F30.B21 11.F30.B20 11.F31.B20 11.F31.B19 11.F30.B19 11.F30.B18 11.F31.B18 11.F31.B17 11.F30.B17 11.F30.B16 11.F31.B16
GTX_DUAL:DRP33 11.F31.B31 11.F30.B31 11.F30.B30 11.F31.B30 11.F31.B29 11.F30.B29 11.F30.B28 11.F31.B28 11.F31.B27 11.F30.B27 11.F30.B26 11.F31.B26 11.F31.B25 11.F30.B25 11.F30.B24 11.F31.B24
GTX_DUAL:DRP34 11.F31.B39 11.F30.B39 11.F30.B38 11.F31.B38 11.F31.B37 11.F30.B37 11.F30.B36 11.F31.B36 11.F31.B35 11.F30.B35 11.F30.B34 11.F31.B34 11.F31.B33 11.F30.B33 11.F30.B32 11.F31.B32
GTX_DUAL:DRP35 11.F31.B47 11.F30.B47 11.F30.B46 11.F31.B46 11.F31.B45 11.F30.B45 11.F30.B44 11.F31.B44 11.F31.B43 11.F30.B43 11.F30.B42 11.F31.B42 11.F31.B41 11.F30.B41 11.F30.B40 11.F31.B40
GTX_DUAL:DRP36 11.F31.B55 11.F30.B55 11.F30.B54 11.F31.B54 11.F31.B53 11.F30.B53 11.F30.B52 11.F31.B52 11.F31.B51 11.F30.B51 11.F30.B50 11.F31.B50 11.F31.B49 11.F30.B49 11.F30.B48 11.F31.B48
GTX_DUAL:DRP37 11.F31.B63 11.F30.B63 11.F30.B62 11.F31.B62 11.F31.B61 11.F30.B61 11.F30.B60 11.F31.B60 11.F31.B59 11.F30.B59 11.F30.B58 11.F31.B58 11.F31.B57 11.F30.B57 11.F30.B56 11.F31.B56
GTX_DUAL:DRP38 12.F31.B7 12.F30.B7 12.F30.B6 12.F31.B6 12.F31.B5 12.F30.B5 12.F30.B4 12.F31.B4 12.F31.B3 12.F30.B3 12.F30.B2 12.F31.B2 12.F31.B1 12.F30.B1 12.F30.B0 12.F31.B0
GTX_DUAL:DRP39 12.F31.B15 12.F30.B15 12.F30.B14 12.F31.B14 12.F31.B13 12.F30.B13 12.F30.B12 12.F31.B12 12.F31.B11 12.F30.B11 12.F30.B10 12.F31.B10 12.F31.B9 12.F30.B9 12.F30.B8 12.F31.B8
GTX_DUAL:DRP3A 12.F31.B23 12.F30.B23 12.F30.B22 12.F31.B22 12.F31.B21 12.F30.B21 12.F30.B20 12.F31.B20 12.F31.B19 12.F30.B19 12.F30.B18 12.F31.B18 12.F31.B17 12.F30.B17 12.F30.B16 12.F31.B16
GTX_DUAL:DRP3B 12.F31.B31 12.F30.B31 12.F30.B30 12.F31.B30 12.F31.B29 12.F30.B29 12.F30.B28 12.F31.B28 12.F31.B27 12.F30.B27 12.F30.B26 12.F31.B26 12.F31.B25 12.F30.B25 12.F30.B24 12.F31.B24
GTX_DUAL:DRP3C 12.F31.B39 12.F30.B39 12.F30.B38 12.F31.B38 12.F31.B37 12.F30.B37 12.F30.B36 12.F31.B36 12.F31.B35 12.F30.B35 12.F30.B34 12.F31.B34 12.F31.B33 12.F30.B33 12.F30.B32 12.F31.B32
GTX_DUAL:DRP3D 12.F31.B47 12.F30.B47 12.F30.B46 12.F31.B46 12.F31.B45 12.F30.B45 12.F30.B44 12.F31.B44 12.F31.B43 12.F30.B43 12.F30.B42 12.F31.B42 12.F31.B41 12.F30.B41 12.F30.B40 12.F31.B40
GTX_DUAL:DRP3E 12.F31.B55 12.F30.B55 12.F30.B54 12.F31.B54 12.F31.B53 12.F30.B53 12.F30.B52 12.F31.B52 12.F31.B51 12.F30.B51 12.F30.B50 12.F31.B50 12.F31.B49 12.F30.B49 12.F30.B48 12.F31.B48
GTX_DUAL:DRP3F 12.F31.B63 12.F30.B63 12.F30.B62 12.F31.B62 12.F31.B61 12.F30.B61 12.F30.B60 12.F31.B60 12.F31.B59 12.F30.B59 12.F30.B58 12.F31.B58 12.F31.B57 12.F30.B57 12.F30.B56 12.F31.B56
GTX_DUAL:DRP40 13.F31.B7 13.F30.B7 13.F30.B6 13.F31.B6 13.F31.B5 13.F30.B5 13.F30.B4 13.F31.B4 13.F31.B3 13.F30.B3 13.F30.B2 13.F31.B2 13.F31.B1 13.F30.B1 13.F30.B0 13.F31.B0
GTX_DUAL:DRP41 13.F31.B15 13.F30.B15 13.F30.B14 13.F31.B14 13.F31.B13 13.F30.B13 13.F30.B12 13.F31.B12 13.F31.B11 13.F30.B11 13.F30.B10 13.F31.B10 13.F31.B9 13.F30.B9 13.F30.B8 13.F31.B8
GTX_DUAL:DRP42 13.F31.B23 13.F30.B23 13.F30.B22 13.F31.B22 13.F31.B21 13.F30.B21 13.F30.B20 13.F31.B20 13.F31.B19 13.F30.B19 13.F30.B18 13.F31.B18 13.F31.B17 13.F30.B17 13.F30.B16 13.F31.B16
GTX_DUAL:DRP43 13.F31.B31 13.F30.B31 13.F30.B30 13.F31.B30 13.F31.B29 13.F30.B29 13.F30.B28 13.F31.B28 13.F31.B27 13.F30.B27 13.F30.B26 13.F31.B26 13.F31.B25 13.F30.B25 13.F30.B24 13.F31.B24
GTX_DUAL:DRP44 13.F31.B39 13.F30.B39 13.F30.B38 13.F31.B38 13.F31.B37 13.F30.B37 13.F30.B36 13.F31.B36 13.F31.B35 13.F30.B35 13.F30.B34 13.F31.B34 13.F31.B33 13.F30.B33 13.F30.B32 13.F31.B32
GTX_DUAL:DRP45 13.F31.B47 13.F30.B47 13.F30.B46 13.F31.B46 13.F31.B45 13.F30.B45 13.F30.B44 13.F31.B44 13.F31.B43 13.F30.B43 13.F30.B42 13.F31.B42 13.F31.B41 13.F30.B41 13.F30.B40 13.F31.B40
GTX_DUAL:DRP46 13.F31.B55 13.F30.B55 13.F30.B54 13.F31.B54 13.F31.B53 13.F30.B53 13.F30.B52 13.F31.B52 13.F31.B51 13.F30.B51 13.F30.B50 13.F31.B50 13.F31.B49 13.F30.B49 13.F30.B48 13.F31.B48
GTX_DUAL:DRP47 13.F31.B63 13.F30.B63 13.F30.B62 13.F31.B62 13.F31.B61 13.F30.B61 13.F30.B60 13.F31.B60 13.F31.B59 13.F30.B59 13.F30.B58 13.F31.B58 13.F31.B57 13.F30.B57 13.F30.B56 13.F31.B56
GTX_DUAL:DRP48 14.F31.B7 14.F30.B7 14.F30.B6 14.F31.B6 14.F31.B5 14.F30.B5 14.F30.B4 14.F31.B4 14.F31.B3 14.F30.B3 14.F30.B2 14.F31.B2 14.F31.B1 14.F30.B1 14.F30.B0 14.F31.B0
GTX_DUAL:DRP49 14.F31.B15 14.F30.B15 14.F30.B14 14.F31.B14 14.F31.B13 14.F30.B13 14.F30.B12 14.F31.B12 14.F31.B11 14.F30.B11 14.F30.B10 14.F31.B10 14.F31.B9 14.F30.B9 14.F30.B8 14.F31.B8
GTX_DUAL:DRP4A 14.F31.B23 14.F30.B23 14.F30.B22 14.F31.B22 14.F31.B21 14.F30.B21 14.F30.B20 14.F31.B20 14.F31.B19 14.F30.B19 14.F30.B18 14.F31.B18 14.F31.B17 14.F30.B17 14.F30.B16 14.F31.B16
GTX_DUAL:DRP4B 14.F31.B31 14.F30.B31 14.F30.B30 14.F31.B30 14.F31.B29 14.F30.B29 14.F30.B28 14.F31.B28 14.F31.B27 14.F30.B27 14.F30.B26 14.F31.B26 14.F31.B25 14.F30.B25 14.F30.B24 14.F31.B24
GTX_DUAL:DRP4C 14.F31.B39 14.F30.B39 14.F30.B38 14.F31.B38 14.F31.B37 14.F30.B37 14.F30.B36 14.F31.B36 14.F31.B35 14.F30.B35 14.F30.B34 14.F31.B34 14.F31.B33 14.F30.B33 14.F30.B32 14.F31.B32
GTX_DUAL:DRP4D 14.F31.B47 14.F30.B47 14.F30.B46 14.F31.B46 14.F31.B45 14.F30.B45 14.F30.B44 14.F31.B44 14.F31.B43 14.F30.B43 14.F30.B42 14.F31.B42 14.F31.B41 14.F30.B41 14.F30.B40 14.F31.B40
GTX_DUAL:DRP4E 14.F31.B55 14.F30.B55 14.F30.B54 14.F31.B54 14.F31.B53 14.F30.B53 14.F30.B52 14.F31.B52 14.F31.B51 14.F30.B51 14.F30.B50 14.F31.B50 14.F31.B49 14.F30.B49 14.F30.B48 14.F31.B48
GTX_DUAL:DRP4F 14.F31.B63 14.F30.B63 14.F30.B62 14.F31.B62 14.F31.B61 14.F30.B61 14.F30.B60 14.F31.B60 14.F31.B59 14.F30.B59 14.F30.B58 14.F31.B58 14.F31.B57 14.F30.B57 14.F30.B56 14.F31.B56
non-inverted [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:MUX.CLKIN 5.F31.B34 5.F30.B34 5.F30.B35
GREFCLK 0 0 0
CLKOUT_SOUTH_N 0 0 1
CLKPN 0 1 1
CLKOUT_NORTH_S 1 0 1
GTX_DUAL:MUX.CLKOUT_NORTH 5.F31.B36
CLKOUT_NORTH_S 0
CLKPN 1
GTX_DUAL:MUX.CLKOUT_SOUTH 5.F31.B35
CLKOUT_SOUTH_N 0
CLKPN 1
GTX_DUAL:OOB_CLK_DIVIDER 9.F31.B54 9.F30.B54 9.F30.B55
1 0 0 0
2 0 0 1
4 0 1 0
6 0 1 1
8 1 0 0
10 1 0 1
12 1 1 0
14 1 1 1
GTX_DUAL:PLL_COM_CFG 7.F30.B33 7.F30.B32 7.F31.B32 7.F31.B31 9.F31.B56 9.F30.B56 9.F30.B57 9.F31.B57 9.F31.B58 9.F30.B58 9.F30.B59 9.F31.B59 9.F31.B60 9.F30.B60 9.F30.B61 9.F31.B61 9.F31.B62 9.F30.B62 9.F30.B63 9.F31.B63 10.F31.B0 10.F30.B0 10.F30.B1 10.F31.B1
non-inverted [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PLL_CP_CFG 10.F31.B2 10.F30.B2 10.F30.B3 10.F31.B3 10.F31.B4 10.F30.B4 10.F30.B5 10.F31.B5
GTX_DUAL:TRANS_TIME_NON_P2_0 12.F31.B46 12.F31.B45 12.F30.B45 12.F30.B44 12.F31.B44 12.F31.B43 12.F30.B43 12.F30.B42
GTX_DUAL:TRANS_TIME_NON_P2_1 7.F31.B17 7.F31.B18 7.F30.B18 7.F30.B19 7.F31.B19 7.F31.B20 7.F30.B20 7.F30.B21
non-inverted [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PLL_DIVSEL_FB 10.F30.B7 10.F31.B7 10.F31.B8 10.F31.B6
2 0 0 0 0
1 0 0 0 1
3 0 0 1 0
4 0 1 0 0
5 0 1 1 0
8 1 1 0 0
10 1 1 1 0
GTX_DUAL:PLL_DIVSEL_REF 5.F31.B38 5.F31.B37 5.F30.B37 5.F30.B36 5.F30.B38
2 0 0 0 0 0
1 0 0 0 0 1
3 0 0 0 1 0
4 0 0 1 0 0
5 0 0 1 1 0
6 0 1 0 1 0
8 0 1 1 0 0
10 0 1 1 1 0
12 1 1 0 1 0
16 1 1 1 0 0
20 1 1 1 1 0
GTX_DUAL:PLL_RXDIVSEL_OUT_0 13.F31.B49 13.F30.B49
GTX_DUAL:PLL_RXDIVSEL_OUT_1 6.F31.B15 6.F31.B16
GTX_DUAL:PLL_TXDIVSEL_OUT_0 13.F31.B48 13.F31.B47
GTX_DUAL:PLL_TXDIVSEL_OUT_1 5.F31.B41 5.F31.B42
1 0 0
2 0 1
4 1 0
GTX_DUAL:PMA_CDR_SCAN_0 13.F30.B47 13.F30.B46 13.F31.B46 13.F31.B45 13.F30.B45 13.F30.B44 13.F31.B44 13.F31.B43 13.F30.B43 13.F30.B42 13.F31.B42 13.F31.B41 13.F30.B41 13.F30.B40 13.F31.B40 13.F31.B39 13.F30.B39 13.F30.B38 13.F31.B38 13.F31.B37 13.F30.B37 13.F30.B36 13.F31.B36 13.F31.B35 13.F30.B35 13.F30.B34 13.F31.B34
GTX_DUAL:PMA_CDR_SCAN_1 6.F30.B16 6.F30.B17 6.F31.B17 6.F31.B18 6.F30.B18 6.F30.B19 6.F31.B19 6.F31.B20 6.F30.B20 6.F30.B21 6.F31.B21 6.F31.B22 6.F30.B22 6.F30.B23 6.F31.B23 6.F31.B24 6.F30.B24 6.F30.B25 6.F31.B25 6.F31.B26 6.F30.B26 6.F30.B27 6.F31.B27 6.F31.B28 6.F30.B28 6.F30.B29 6.F31.B29
non-inverted [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PMA_COM_CFG 9.F30.B45 10.F30.B19 9.F30.B44 10.F31.B19 9.F30.B47 9.F31.B45 9.F30.B46 9.F31.B46 10.F30.B17 10.F30.B18 10.F31.B17 10.F31.B18 9.F31.B48 10.F30.B16 9.F31.B47 10.F31.B16 9.F30.B40 10.F30.B23 9.F30.B41 10.F31.B23 9.F31.B52 10.F31.B12 9.F31.B51 10.F30.B12 9.F30.B51 10.F30.B13 9.F30.B50 10.F31.B13 9.F31.B49 10.F31.B14 9.F31.B50 10.F30.B14 9.F30.B49 10.F31.B15 9.F30.B48 10.F30.B15 10.F31.B11 14.F30.B19 14.F30.B18 14.F31.B18 14.F31.B17 14.F30.B17 5.F30.B44 5.F30.B45 5.F31.B45 5.F31.B46 5.F30.B46 5.F31.B44 14.F31.B19 12.F30.B19 9.F31.B34 9.F30.B34 9.F30.B35 9.F31.B35 9.F31.B36 9.F30.B36 9.F30.B37 9.F31.B37 9.F31.B38 10.F31.B29 7.F30.B46 10.F31.B25 10.F31.B26 10.F30.B26 10.F31.B27 10.F31.B28 10.F30.B28 10.F30.B29 10.F30.B27
non-inverted [68] [67] [66] [65] [64] [63] [62] [61] [60] [59] [58] [57] [56] [55] [54] [53] [52] [51] [50] [49] [48] [47] [46] [45] [44] [43] [42] [41] [40] [39] [38] [37] [36] [35] [34] [33] [32] [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PMA_RXSYNC_CFG_0 14.F31.B31 14.F30.B31 14.F30.B30 14.F31.B30 14.F31.B29 14.F30.B29 14.F30.B28
GTX_DUAL:PMA_RXSYNC_CFG_1 5.F31.B0 5.F30.B0 5.F30.B1 5.F31.B1 5.F31.B2 5.F30.B2 5.F30.B3
non-inverted [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PMA_RX_CFG_0 5.F31.B49 5.F30.B59 14.F31.B12 14.F31.B11 14.F30.B11 14.F30.B10 14.F31.B10 14.F31.B9 14.F30.B9 14.F30.B8 14.F31.B8 14.F31.B7 5.F30.B49 5.F30.B51 14.F31.B4 14.F31.B3 14.F30.B3 14.F30.B2 14.F31.B2 14.F30.B6 14.F31.B6 14.F31.B5 14.F30.B5 5.F31.B50 5.F30.B50
GTX_DUAL:PMA_RX_CFG_1 14.F31.B14 14.F30.B4 5.F31.B51 5.F31.B52 5.F30.B52 5.F30.B53 5.F31.B53 5.F31.B54 5.F30.B54 5.F30.B55 5.F31.B55 5.F31.B56 14.F30.B14 14.F30.B12 5.F31.B59 5.F31.B60 5.F30.B60 5.F30.B61 5.F31.B61 5.F30.B57 5.F31.B57 5.F31.B58 5.F30.B58 14.F31.B13 14.F30.B13
non-inverted [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:PMA_TX_CFG_0 14.F30.B60 14.F31.B60 14.F31.B59 14.F30.B59 14.F30.B58 14.F31.B58 14.F31.B57 14.F30.B57 14.F30.B56 14.F31.B56 14.F31.B55 14.F30.B55 14.F30.B54 14.F31.B54 14.F31.B53 14.F30.B53 14.F30.B52 14.F31.B52 14.F31.B51 14.F30.B51
GTX_DUAL:PMA_TX_CFG_1 5.F31.B3 5.F31.B4 5.F30.B4 5.F30.B5 5.F31.B5 5.F31.B6 5.F30.B6 5.F30.B7 5.F31.B7 5.F31.B8 5.F30.B8 5.F30.B9 5.F31.B9 5.F31.B10 5.F30.B10 5.F30.B11 5.F31.B11 5.F31.B12 5.F30.B12 5.F30.B13
non-inverted [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:RX_LOS_INVALID_INCR_0 13.F30.B16 13.F31.B16 13.F31.B15
GTX_DUAL:RX_LOS_INVALID_INCR_1 6.F30.B47 6.F31.B47 6.F31.B48
1 0 0 0
2 0 0 1
4 0 1 0
8 0 1 1
16 1 0 0
32 1 0 1
64 1 1 0
128 1 1 1
GTX_DUAL:RX_LOS_THRESHOLD_0 13.F30.B14 13.F31.B14 13.F31.B13
GTX_DUAL:RX_LOS_THRESHOLD_1 6.F30.B49 6.F31.B49 6.F31.B50
4 0 0 0
8 0 0 1
16 0 1 0
32 0 1 1
64 1 0 0
128 1 0 1
256 1 1 0
512 1 1 1
GTX_DUAL:RX_SLIDE_MODE_0 13.F30.B13
GTX_DUAL:RX_SLIDE_MODE_1 6.F30.B50
PCS 0
PMA 1
GTX_DUAL:RX_STATUS_FMT_0 13.F30.B12
GTX_DUAL:RX_STATUS_FMT_1 6.F30.B51
PCIE 0
SATA 1
GTX_DUAL:RX_XCLK_SEL_0 13.F31.B12
GTX_DUAL:RX_XCLK_SEL_1 6.F31.B51
RXREC 0
RXUSR 1
GTX_DUAL:TERMINATION_IMP_0 12.F30.B54
GTX_DUAL:TERMINATION_IMP_1 7.F30.B9
50 0
75 1
GTX_DUAL:TRANS_TIME_FROM_P2_0 12.F31.B54 12.F31.B53 12.F30.B53 12.F30.B52 12.F31.B52 12.F31.B51 12.F30.B51 12.F30.B50 12.F31.B50 12.F31.B49 12.F30.B49 12.F30.B48
GTX_DUAL:TRANS_TIME_FROM_P2_1 7.F31.B9 7.F31.B10 7.F30.B10 7.F30.B11 7.F31.B11 7.F31.B12 7.F30.B12 7.F30.B13 7.F31.B13 7.F31.B14 7.F30.B14 7.F30.B15
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:TX_DETECT_RX_CFG_0 12.F31.B29 12.F30.B29 12.F30.B28 12.F31.B28 12.F31.B27 12.F30.B27 12.F30.B26 12.F31.B26 12.F31.B25 12.F30.B25 12.F30.B24 12.F31.B24 12.F31.B23 12.F30.B23
GTX_DUAL:TX_DETECT_RX_CFG_1 7.F31.B34 7.F30.B34 7.F30.B35 7.F31.B35 7.F31.B36 7.F30.B36 7.F30.B37 7.F31.B37 7.F31.B38 7.F30.B38 7.F30.B39 7.F31.B39 7.F31.B40 7.F30.B40
non-inverted [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
GTX_DUAL:TX_XCLK_SEL_0 12.F31.B20
GTX_DUAL:TX_XCLK_SEL_1 7.F31.B43
TXOUT 0
TXUSR 1