Global buffers

Tile CLK_BUFG_S

Cells: 7

Switchbox SPEC_INT

virtex6 CLK_BUFG_S switchbox SPEC_INT permanent buffers
Destination	Source
CELL[0].GCLK[0]	CELL[1].OUT_BUFG[0]
CELL[0].GCLK[1]	CELL[1].OUT_BUFG[1]
CELL[0].GCLK[2]	CELL[1].OUT_BUFG[2]
CELL[0].GCLK[3]	CELL[1].OUT_BUFG[3]
CELL[0].GCLK[4]	CELL[1].OUT_BUFG[4]
CELL[0].GCLK[5]	CELL[1].OUT_BUFG[5]
CELL[0].GCLK[6]	CELL[1].OUT_BUFG[6]
CELL[0].GCLK[7]	CELL[1].OUT_BUFG[7]
CELL[0].GCLK[8]	CELL[1].OUT_BUFG[8]
CELL[0].GCLK[9]	CELL[1].OUT_BUFG[9]
CELL[0].GCLK[10]	CELL[1].OUT_BUFG[10]
CELL[0].GCLK[11]	CELL[1].OUT_BUFG[11]
CELL[0].GCLK[12]	CELL[1].OUT_BUFG[12]
CELL[0].GCLK[13]	CELL[1].OUT_BUFG[13]
CELL[0].GCLK[14]	CELL[1].OUT_BUFG[14]
CELL[0].GCLK[15]	CELL[1].OUT_BUFG[15]
CELL[0].GIOB[0]	IO_W[0].OUT_CLKPAD
CELL[0].GIOB[1]	IO_E[0].OUT_CLKPAD
CELL[0].GIOB[2]	IO_W[1].OUT_CLKPAD
CELL[0].GIOB[3]	IO_E[1].OUT_CLKPAD

virtex6 CLK_BUFG_S switchbox SPEC_INT programmable buffers
Destination	Source	Bit
CELL[1].OUT_BEL[0]	CELL[1].IMUX_BUFG_O[3]	MAIN[0][28][6]
CELL[1].OUT_BEL[1]	CELL[1].IMUX_BUFG_O[4]	MAIN[0][27][22]
CELL[1].OUT_BEL[2]	CELL[1].IMUX_BUFG_O[11]	MAIN[0][28][38]
CELL[1].OUT_BEL[3]	CELL[1].IMUX_BUFG_O[12]	MAIN[0][27][54]
CELL[1].OUT_BEL[4]	CELL[1].IMUX_BUFG_O[0]	MAIN[0][27][6]
CELL[1].OUT_BEL[5]	CELL[1].IMUX_BUFG_O[7]	MAIN[0][28][22]
CELL[1].OUT_BEL[6]	CELL[1].IMUX_BUFG_O[8]	MAIN[0][27][38]
CELL[1].OUT_BEL[7]	CELL[1].IMUX_BUFG_O[15]	MAIN[0][28][54]
CELL[1].OUT_BEL[8]	CELL[1].IMUX_BUFG_O[1]	MAIN[0][26][6]
CELL[1].OUT_BEL[9]	CELL[1].IMUX_BUFG_O[6]	MAIN[0][29][22]
CELL[1].OUT_BEL[10]	CELL[1].IMUX_BUFG_O[9]	MAIN[0][26][38]
CELL[1].OUT_BEL[11]	CELL[1].IMUX_BUFG_O[14]	MAIN[0][29][54]
CELL[1].OUT_BEL[12]	CELL[1].IMUX_BUFG_O[2]	MAIN[0][29][6]
CELL[1].OUT_BEL[13]	CELL[1].IMUX_BUFG_O[5]	MAIN[0][26][22]
CELL[1].OUT_BEL[14]	CELL[1].IMUX_BUFG_O[10]	MAIN[0][29][38]
CELL[1].OUT_BEL[15]	CELL[1].IMUX_BUFG_O[13]	MAIN[0][26][54]
CELL[1].OUT_BUFG_GFB[0]	CELL[1].OUT_BUFG[0]	MAIN[0][27][3]
CELL[1].OUT_BUFG_GFB[1]	CELL[1].OUT_BUFG[1]	MAIN[0][29][3]
CELL[1].OUT_BUFG_GFB[2]	CELL[1].OUT_BUFG[2]	MAIN[0][27][19]
CELL[1].OUT_BUFG_GFB[3]	CELL[1].OUT_BUFG[3]	MAIN[0][29][19]
CELL[1].OUT_BUFG_GFB[4]	CELL[1].OUT_BUFG[4]	MAIN[0][27][35]
CELL[1].OUT_BUFG_GFB[5]	CELL[1].OUT_BUFG[5]	MAIN[0][29][35]
CELL[1].OUT_BUFG_GFB[6]	CELL[1].OUT_BUFG[6]	MAIN[0][27][51]
CELL[1].OUT_BUFG_GFB[7]	CELL[1].OUT_BUFG[7]	MAIN[0][29][51]
CELL[1].OUT_BUFG_GFB[8]	CELL[1].OUT_BUFG[8]	MAIN[1][27][3]
CELL[1].OUT_BUFG_GFB[9]	CELL[1].OUT_BUFG[9]	MAIN[1][29][3]
CELL[1].OUT_BUFG_GFB[10]	CELL[1].OUT_BUFG[10]	MAIN[1][27][19]
CELL[1].OUT_BUFG_GFB[11]	CELL[1].OUT_BUFG[11]	MAIN[1][29][19]
CELL[1].OUT_BUFG_GFB[12]	CELL[1].OUT_BUFG[12]	MAIN[1][27][35]
CELL[1].OUT_BUFG_GFB[13]	CELL[1].OUT_BUFG[13]	MAIN[1][29][35]
CELL[1].OUT_BUFG_GFB[14]	CELL[1].OUT_BUFG[14]	MAIN[1][27][51]
CELL[1].OUT_BUFG_GFB[15]	CELL[1].OUT_BUFG[15]	MAIN[1][29][51]
CELL[2].OUT_BEL[0]	CELL[1].IMUX_BUFG_O[19]	MAIN[1][28][6]
CELL[2].OUT_BEL[1]	CELL[1].IMUX_BUFG_O[20]	MAIN[1][27][22]
CELL[2].OUT_BEL[2]	CELL[1].IMUX_BUFG_O[27]	MAIN[1][28][38]
CELL[2].OUT_BEL[3]	CELL[1].IMUX_BUFG_O[28]	MAIN[1][27][54]
CELL[2].OUT_BEL[4]	CELL[1].IMUX_BUFG_O[16]	MAIN[1][27][6]
CELL[2].OUT_BEL[5]	CELL[1].IMUX_BUFG_O[23]	MAIN[1][28][22]
CELL[2].OUT_BEL[6]	CELL[1].IMUX_BUFG_O[24]	MAIN[1][27][38]
CELL[2].OUT_BEL[7]	CELL[1].IMUX_BUFG_O[31]	MAIN[1][28][54]
CELL[2].OUT_BEL[8]	CELL[1].IMUX_BUFG_O[17]	MAIN[1][26][6]
CELL[2].OUT_BEL[9]	CELL[1].IMUX_BUFG_O[22]	MAIN[1][29][22]
CELL[2].OUT_BEL[10]	CELL[1].IMUX_BUFG_O[25]	MAIN[1][26][38]
CELL[2].OUT_BEL[11]	CELL[1].IMUX_BUFG_O[30]	MAIN[1][29][54]
CELL[2].OUT_BEL[12]	CELL[1].IMUX_BUFG_O[18]	MAIN[1][29][6]
CELL[2].OUT_BEL[13]	CELL[1].IMUX_BUFG_O[21]	MAIN[1][26][22]
CELL[2].OUT_BEL[14]	CELL[1].IMUX_BUFG_O[26]	MAIN[1][29][38]
CELL[2].OUT_BEL[15]	CELL[1].IMUX_BUFG_O[29]	MAIN[1][26][54]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[0]
Bits								Destination
MAIN[0][26][8]	MAIN[0][27][10]	MAIN[0][26][9]	MAIN[0][26][5]	MAIN[0][27][12]	MAIN[0][27][14]	MAIN[0][26][15]	MAIN[0][26][13]	CELL[1].IMUX_BUFG_O[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[0]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[38]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[15]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[1]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[1]
Bits								Destination
MAIN[0][27][8]	MAIN[0][26][10]	MAIN[0][27][9]	MAIN[0][27][5]	MAIN[0][27][13]	MAIN[0][26][14]	MAIN[0][27][15]	MAIN[0][26][12]	CELL[1].IMUX_BUFG_O[1]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[1]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[39]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[15]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[1]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[2]
Bits								Destination
MAIN[0][28][8]	MAIN[0][29][10]	MAIN[0][28][9]	MAIN[0][28][5]	MAIN[0][29][12]	MAIN[0][29][14]	MAIN[0][28][15]	MAIN[0][28][13]	CELL[1].IMUX_BUFG_O[2]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[2]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[25]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[0]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[2]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[3]
Bits								Destination
MAIN[0][29][8]	MAIN[0][28][10]	MAIN[0][29][9]	MAIN[0][29][5]	MAIN[0][29][13]	MAIN[0][28][14]	MAIN[0][29][15]	MAIN[0][28][12]	CELL[1].IMUX_BUFG_O[3]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[3]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[24]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[0]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[2]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[4]
Bits								Destination
MAIN[0][26][24]	MAIN[0][27][26]	MAIN[0][26][25]	MAIN[0][26][21]	MAIN[0][27][28]	MAIN[0][27][30]	MAIN[0][26][31]	MAIN[0][26][29]	CELL[1].IMUX_BUFG_O[4]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[4]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[22]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[1]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[3]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[5]
Bits								Destination
MAIN[0][27][24]	MAIN[0][26][26]	MAIN[0][27][25]	MAIN[0][27][21]	MAIN[0][27][29]	MAIN[0][26][30]	MAIN[0][27][31]	MAIN[0][26][28]	CELL[1].IMUX_BUFG_O[5]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[5]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[23]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[1]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[3]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[6]
Bits								Destination
MAIN[0][28][24]	MAIN[0][29][26]	MAIN[0][28][25]	MAIN[0][28][21]	MAIN[0][29][28]	MAIN[0][29][30]	MAIN[0][28][31]	MAIN[0][28][29]	CELL[1].IMUX_BUFG_O[6]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[6]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[9]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[2]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[4]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[7]
Bits								Destination
MAIN[0][29][24]	MAIN[0][28][26]	MAIN[0][29][25]	MAIN[0][29][21]	MAIN[0][29][29]	MAIN[0][28][30]	MAIN[0][29][31]	MAIN[0][28][28]	CELL[1].IMUX_BUFG_O[7]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[7]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[8]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[2]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[4]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[8]
Bits								Destination
MAIN[0][26][40]	MAIN[0][27][42]	MAIN[0][26][41]	MAIN[0][26][37]	MAIN[0][27][44]	MAIN[0][27][46]	MAIN[0][26][47]	MAIN[0][26][45]	CELL[1].IMUX_BUFG_O[8]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[8]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[6]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[3]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[5]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[9]
Bits								Destination
MAIN[0][27][40]	MAIN[0][26][42]	MAIN[0][27][41]	MAIN[0][27][37]	MAIN[0][27][45]	MAIN[0][26][46]	MAIN[0][27][47]	MAIN[0][26][44]	CELL[1].IMUX_BUFG_O[9]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[1].IMUX_BUFG_I[9]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[7]
0	0	1	0	0	0	1	0	CELL[1].OUT_BUFG_GFB[3]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[5]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[10]
Bits								Destination
MAIN[0][29][44]	MAIN[0][28][45]	MAIN[0][29][46]	MAIN[0][28][47]	MAIN[0][28][37]	MAIN[0][28][41]	MAIN[0][28][40]	MAIN[0][29][42]	CELL[1].IMUX_BUFG_O[10]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[4]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[6]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[1]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[11]
Bits								Destination
MAIN[0][28][44]	MAIN[0][29][45]	MAIN[0][28][46]	MAIN[0][29][47]	MAIN[0][29][37]	MAIN[0][29][41]	MAIN[0][29][40]	MAIN[0][28][42]	CELL[1].IMUX_BUFG_O[11]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[4]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[6]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[9]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[12]
Bits								Destination
MAIN[0][27][60]	MAIN[0][26][61]	MAIN[0][27][62]	MAIN[0][26][63]	MAIN[0][26][53]	MAIN[0][26][57]	MAIN[0][26][56]	MAIN[0][27][58]	CELL[1].IMUX_BUFG_O[12]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[5]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[7]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[25]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[13]
Bits								Destination
MAIN[0][26][60]	MAIN[0][27][61]	MAIN[0][26][62]	MAIN[0][27][63]	MAIN[0][27][53]	MAIN[0][27][57]	MAIN[0][27][56]	MAIN[0][26][58]	CELL[1].IMUX_BUFG_O[13]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[5]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[7]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[17]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[14]
Bits								Destination
MAIN[0][29][60]	MAIN[0][28][61]	MAIN[0][29][62]	MAIN[0][28][63]	MAIN[0][28][53]	MAIN[0][28][57]	MAIN[0][28][56]	MAIN[0][29][58]	CELL[1].IMUX_BUFG_O[14]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[6]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[8]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[35]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[15]
Bits								Destination
MAIN[0][28][60]	MAIN[0][29][61]	MAIN[0][28][62]	MAIN[0][29][63]	MAIN[0][29][53]	MAIN[0][29][57]	MAIN[0][29][56]	MAIN[0][28][58]	CELL[1].IMUX_BUFG_O[15]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[6]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[8]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[43]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[16]
Bits								Destination
MAIN[1][27][12]	MAIN[1][26][13]	MAIN[1][27][14]	MAIN[1][26][15]	MAIN[1][26][5]	MAIN[1][26][9]	MAIN[1][26][8]	MAIN[1][27][10]	CELL[1].IMUX_BUFG_O[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[7]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[9]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[12]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[17]
Bits								Destination
MAIN[1][26][12]	MAIN[1][27][13]	MAIN[1][26][14]	MAIN[1][27][15]	MAIN[1][27][5]	MAIN[1][27][9]	MAIN[1][27][8]	MAIN[1][26][10]	CELL[1].IMUX_BUFG_O[17]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[7]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[9]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[4]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[18]
Bits								Destination
MAIN[1][29][12]	MAIN[1][28][13]	MAIN[1][29][14]	MAIN[1][28][15]	MAIN[1][28][5]	MAIN[1][28][9]	MAIN[1][28][8]	MAIN[1][29][10]	CELL[1].IMUX_BUFG_O[18]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[8]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[10]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[38]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[19]
Bits								Destination
MAIN[1][28][12]	MAIN[1][29][13]	MAIN[1][28][14]	MAIN[1][29][15]	MAIN[1][29][5]	MAIN[1][29][9]	MAIN[1][29][8]	MAIN[1][28][10]	CELL[1].IMUX_BUFG_O[19]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[8]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[10]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[20]
Bits								Destination
MAIN[1][27][28]	MAIN[1][26][29]	MAIN[1][27][30]	MAIN[1][26][31]	MAIN[1][26][21]	MAIN[1][26][25]	MAIN[1][26][24]	MAIN[1][27][26]	CELL[1].IMUX_BUFG_O[20]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[9]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[11]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[23]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[21]
Bits								Destination
MAIN[1][26][28]	MAIN[1][27][29]	MAIN[1][26][30]	MAIN[1][27][31]	MAIN[1][27][21]	MAIN[1][27][25]	MAIN[1][27][24]	MAIN[1][26][26]	CELL[1].IMUX_BUFG_O[21]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[9]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[11]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[15]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[22]
Bits								Destination
MAIN[1][29][28]	MAIN[1][28][29]	MAIN[1][29][30]	MAIN[1][28][31]	MAIN[1][28][21]	MAIN[1][28][25]	MAIN[1][28][24]	MAIN[1][29][26]	CELL[1].IMUX_BUFG_O[22]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[10]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[12]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[33]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[23]
Bits								Destination
MAIN[1][28][28]	MAIN[1][29][29]	MAIN[1][28][30]	MAIN[1][29][31]	MAIN[1][29][21]	MAIN[1][29][25]	MAIN[1][29][24]	MAIN[1][28][26]	CELL[1].IMUX_BUFG_O[23]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[10]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[12]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[41]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[24]
Bits								Destination
MAIN[1][27][44]	MAIN[1][26][45]	MAIN[1][27][46]	MAIN[1][26][47]	MAIN[1][26][37]	MAIN[1][26][41]	MAIN[1][26][40]	MAIN[1][27][42]	CELL[1].IMUX_BUFG_O[24]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[11]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[13]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[10]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[25]
Bits								Destination
MAIN[1][26][44]	MAIN[1][27][45]	MAIN[1][26][46]	MAIN[1][27][47]	MAIN[1][27][37]	MAIN[1][27][41]	MAIN[1][27][40]	MAIN[1][26][42]	CELL[1].IMUX_BUFG_O[25]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[11]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[13]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[2]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[26]
Bits								Destination
MAIN[1][29][44]	MAIN[1][28][45]	MAIN[1][29][46]	MAIN[1][28][47]	MAIN[1][28][37]	MAIN[1][28][41]	MAIN[1][28][40]	MAIN[1][29][42]	CELL[1].IMUX_BUFG_O[26]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[12]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[14]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[20]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[27]
Bits								Destination
MAIN[1][28][44]	MAIN[1][29][45]	MAIN[1][28][46]	MAIN[1][29][47]	MAIN[1][29][37]	MAIN[1][29][41]	MAIN[1][29][40]	MAIN[1][28][42]	CELL[1].IMUX_BUFG_O[27]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[12]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[14]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[28]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[28]
Bits								Destination
MAIN[1][27][60]	MAIN[1][26][61]	MAIN[1][27][62]	MAIN[1][26][63]	MAIN[1][26][53]	MAIN[1][26][57]	MAIN[1][26][56]	MAIN[1][27][58]	CELL[1].IMUX_BUFG_O[28]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[13]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[15]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[5]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[29]
Bits								Destination
MAIN[1][26][60]	MAIN[1][27][61]	MAIN[1][26][62]	MAIN[1][27][63]	MAIN[1][27][53]	MAIN[1][27][57]	MAIN[1][27][56]	MAIN[1][26][58]	CELL[1].IMUX_BUFG_O[29]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[13]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[15]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[36]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[30]
Bits								Destination
MAIN[1][29][60]	MAIN[1][28][61]	MAIN[1][29][62]	MAIN[1][28][63]	MAIN[1][28][53]	MAIN[1][28][57]	MAIN[1][28][56]	MAIN[1][29][58]	CELL[1].IMUX_BUFG_O[30]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[14]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[0]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[31]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_S switchbox SPEC_INT muxes IMUX_BUFG_O[31]
Bits								Destination
MAIN[1][28][60]	MAIN[1][29][61]	MAIN[1][28][62]	MAIN[1][29][63]	MAIN[1][29][53]	MAIN[1][29][57]	MAIN[1][29][56]	MAIN[1][28][58]	CELL[1].IMUX_BUFG_O[31]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[1].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[1].OUT_BUFG_GFB[14]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[1].OUT_BUFG_GFB[0]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[39]

Bels BUFGCTRL

virtex6 CLK_BUFG_S bel BUFGCTRL pins
Pin	Direction	BUFGCTRL[0]	BUFGCTRL[1]	BUFGCTRL[2]	BUFGCTRL[3]	BUFGCTRL[4]	BUFGCTRL[5]	BUFGCTRL[6]	BUFGCTRL[7]	BUFGCTRL[8]	BUFGCTRL[9]	BUFGCTRL[10]	BUFGCTRL[11]	BUFGCTRL[12]	BUFGCTRL[13]	BUFGCTRL[14]	BUFGCTRL[15]
I0	in	CELL[1].IMUX_BUFG_O[0]	CELL[1].IMUX_BUFG_O[2]	CELL[1].IMUX_BUFG_O[4]	CELL[1].IMUX_BUFG_O[6]	CELL[1].IMUX_BUFG_O[8]	CELL[1].IMUX_BUFG_O[10]	CELL[1].IMUX_BUFG_O[12]	CELL[1].IMUX_BUFG_O[14]	CELL[1].IMUX_BUFG_O[16]	CELL[1].IMUX_BUFG_O[18]	CELL[1].IMUX_BUFG_O[20]	CELL[1].IMUX_BUFG_O[22]	CELL[1].IMUX_BUFG_O[24]	CELL[1].IMUX_BUFG_O[26]	CELL[1].IMUX_BUFG_O[28]	CELL[1].IMUX_BUFG_O[30]
I1	in	CELL[1].IMUX_BUFG_O[1]	CELL[1].IMUX_BUFG_O[3]	CELL[1].IMUX_BUFG_O[5]	CELL[1].IMUX_BUFG_O[7]	CELL[1].IMUX_BUFG_O[9]	CELL[1].IMUX_BUFG_O[11]	CELL[1].IMUX_BUFG_O[13]	CELL[1].IMUX_BUFG_O[15]	CELL[1].IMUX_BUFG_O[17]	CELL[1].IMUX_BUFG_O[19]	CELL[1].IMUX_BUFG_O[21]	CELL[1].IMUX_BUFG_O[23]	CELL[1].IMUX_BUFG_O[25]	CELL[1].IMUX_BUFG_O[27]	CELL[1].IMUX_BUFG_O[29]	CELL[1].IMUX_BUFG_O[31]
S0	in	CELL[0].IMUX_IMUX[34] invert by !MAIN[0][26][3]	CELL[0].IMUX_IMUX[29] invert by !MAIN[0][28][3]	CELL[0].IMUX_IMUX[18] invert by !MAIN[0][26][19]	CELL[0].IMUX_IMUX[13] invert by !MAIN[0][28][19]	CELL[0].IMUX_IMUX[2] invert by !MAIN[0][26][35]	CELL[1].IMUX_IMUX[16] invert by !MAIN[0][28][35]	CELL[1].IMUX_IMUX[10] invert by !MAIN[0][26][51]	CELL[1].IMUX_IMUX[3] invert by !MAIN[0][28][51]	CELL[1].IMUX_IMUX[5] invert by !MAIN[1][26][3]	CELL[1].IMUX_IMUX[6] invert by !MAIN[1][28][3]	CELL[2].IMUX_IMUX[8] invert by !MAIN[1][26][19]	CELL[2].IMUX_IMUX[1] invert by !MAIN[1][28][19]	CELL[2].IMUX_IMUX[42] invert by !MAIN[1][26][35]	CELL[2].IMUX_IMUX[35] invert by !MAIN[1][28][35]	CELL[2].IMUX_IMUX[37] invert by !MAIN[1][26][51]	CELL[2].IMUX_IMUX[38] invert by !MAIN[1][28][51]
S1	in	CELL[0].IMUX_IMUX[35] invert by !MAIN[0][27][2]	CELL[0].IMUX_IMUX[28] invert by !MAIN[0][29][2]	CELL[0].IMUX_IMUX[19] invert by !MAIN[0][27][18]	CELL[0].IMUX_IMUX[12] invert by !MAIN[0][29][18]	CELL[0].IMUX_IMUX[3] invert by !MAIN[0][27][34]	CELL[1].IMUX_IMUX[24] invert by !MAIN[0][29][34]	CELL[1].IMUX_IMUX[2] invert by !MAIN[0][27][50]	CELL[1].IMUX_IMUX[11] invert by !MAIN[0][29][50]	CELL[1].IMUX_IMUX[36] invert by !MAIN[1][27][2]	CELL[1].IMUX_IMUX[14] invert by !MAIN[1][29][2]	CELL[2].IMUX_IMUX[0] invert by !MAIN[1][27][18]	CELL[2].IMUX_IMUX[9] invert by !MAIN[1][29][18]	CELL[2].IMUX_IMUX[34] invert by !MAIN[1][27][34]	CELL[2].IMUX_IMUX[43] invert by !MAIN[1][29][34]	CELL[2].IMUX_IMUX[29] invert by !MAIN[1][27][50]	CELL[2].IMUX_IMUX[7] invert by !MAIN[1][29][50]
CE0	in	CELL[0].IMUX_IMUX[36] invert by !MAIN[0][26][0]	CELL[0].IMUX_IMUX[27] invert by !MAIN[0][28][0]	CELL[0].IMUX_IMUX[20] invert by !MAIN[0][26][16]	CELL[0].IMUX_IMUX[11] invert by !MAIN[0][28][16]	CELL[0].IMUX_IMUX[4] invert by !MAIN[0][26][32]	CELL[1].IMUX_IMUX[32] invert by !MAIN[0][28][32]	CELL[1].IMUX_IMUX[41] invert by !MAIN[0][26][48]	CELL[1].IMUX_IMUX[19] invert by !MAIN[0][28][48]	CELL[1].IMUX_IMUX[28] invert by !MAIN[1][26][0]	CELL[1].IMUX_IMUX[22] invert by !MAIN[1][28][0]	CELL[1].IMUX_IMUX[39] invert by !MAIN[1][26][16]	CELL[2].IMUX_IMUX[17] invert by !MAIN[1][28][16]	CELL[2].IMUX_IMUX[26] invert by !MAIN[1][26][32]	CELL[2].IMUX_IMUX[4] invert by !MAIN[1][28][32]	CELL[2].IMUX_IMUX[21] invert by !MAIN[1][26][48]	CELL[2].IMUX_IMUX[15] invert by !MAIN[1][28][48]
CE1	in	CELL[0].IMUX_IMUX[37] invert by !MAIN[0][27][1]	CELL[0].IMUX_IMUX[26] invert by !MAIN[0][29][1]	CELL[0].IMUX_IMUX[21] invert by !MAIN[0][27][17]	CELL[0].IMUX_IMUX[10] invert by !MAIN[0][29][17]	CELL[0].IMUX_IMUX[5] invert by !MAIN[0][27][33]	CELL[1].IMUX_IMUX[40] invert by !MAIN[0][29][33]	CELL[1].IMUX_IMUX[33] invert by !MAIN[0][27][49]	CELL[1].IMUX_IMUX[27] invert by !MAIN[0][29][49]	CELL[1].IMUX_IMUX[20] invert by !MAIN[1][27][1]	CELL[1].IMUX_IMUX[30] invert by !MAIN[1][29][1]	CELL[1].IMUX_IMUX[31] invert by !MAIN[1][27][17]	CELL[2].IMUX_IMUX[25] invert by !MAIN[1][29][17]	CELL[2].IMUX_IMUX[18] invert by !MAIN[1][27][33]	CELL[2].IMUX_IMUX[12] invert by !MAIN[1][29][33]	CELL[2].IMUX_IMUX[13] invert by !MAIN[1][27][49]	CELL[2].IMUX_IMUX[23] invert by !MAIN[1][29][49]
IGNORE0	in	CELL[0].IMUX_IMUX[32] invert by !MAIN[0][26][2]	CELL[0].IMUX_IMUX[31] invert by !MAIN[0][28][2]	CELL[0].IMUX_IMUX[16] invert by !MAIN[0][26][18]	CELL[0].IMUX_IMUX[15] invert by !MAIN[0][28][18]	CELL[0].IMUX_IMUX[0] invert by !MAIN[0][26][34]	CELL[1].IMUX_IMUX[0] invert by !MAIN[0][28][34]	CELL[1].IMUX_IMUX[26] invert by !MAIN[0][26][50]	CELL[1].IMUX_IMUX[34] invert by !MAIN[0][28][50]	CELL[1].IMUX_IMUX[21] invert by !MAIN[1][26][2]	CELL[1].IMUX_IMUX[29] invert by !MAIN[1][28][2]	CELL[2].IMUX_IMUX[24] invert by !MAIN[1][26][18]	CELL[2].IMUX_IMUX[32] invert by !MAIN[1][28][18]	CELL[2].IMUX_IMUX[11] invert by !MAIN[1][26][34]	CELL[2].IMUX_IMUX[19] invert by !MAIN[1][28][34]	CELL[2].IMUX_IMUX[14] invert by !MAIN[1][26][50]	CELL[2].IMUX_IMUX[22] invert by !MAIN[1][28][50]
IGNORE1	in	CELL[0].IMUX_IMUX[33] invert by !MAIN[0][26][1]	CELL[0].IMUX_IMUX[30] invert by !MAIN[0][28][1]	CELL[0].IMUX_IMUX[17] invert by !MAIN[0][26][17]	CELL[0].IMUX_IMUX[14] invert by !MAIN[0][28][17]	CELL[0].IMUX_IMUX[1] invert by !MAIN[0][26][33]	CELL[1].IMUX_IMUX[8] invert by !MAIN[0][28][33]	CELL[1].IMUX_IMUX[18] invert by !MAIN[0][26][49]	CELL[1].IMUX_IMUX[42] invert by !MAIN[0][28][49]	CELL[1].IMUX_IMUX[13] invert by !MAIN[1][26][1]	CELL[1].IMUX_IMUX[37] invert by !MAIN[1][28][1]	CELL[2].IMUX_IMUX[16] invert by !MAIN[1][26][17]	CELL[2].IMUX_IMUX[40] invert by !MAIN[1][28][17]	CELL[2].IMUX_IMUX[3] invert by !MAIN[1][26][33]	CELL[2].IMUX_IMUX[27] invert by !MAIN[1][28][33]	CELL[2].IMUX_IMUX[6] invert by !MAIN[1][26][49]	CELL[2].IMUX_IMUX[30] invert by !MAIN[1][28][49]
O	out	CELL[1].OUT_BUFG[0]	CELL[1].OUT_BUFG[1]	CELL[1].OUT_BUFG[2]	CELL[1].OUT_BUFG[3]	CELL[1].OUT_BUFG[4]	CELL[1].OUT_BUFG[5]	CELL[1].OUT_BUFG[6]	CELL[1].OUT_BUFG[7]	CELL[1].OUT_BUFG[8]	CELL[1].OUT_BUFG[9]	CELL[1].OUT_BUFG[10]	CELL[1].OUT_BUFG[11]	CELL[1].OUT_BUFG[12]	CELL[1].OUT_BUFG[13]	CELL[1].OUT_BUFG[14]	CELL[1].OUT_BUFG[15]

virtex6 CLK_BUFG_S bel BUFGCTRL attribute bits
Attribute	BUFGCTRL[0]	BUFGCTRL[1]	BUFGCTRL[2]	BUFGCTRL[3]	BUFGCTRL[4]	BUFGCTRL[5]	BUFGCTRL[6]	BUFGCTRL[7]	BUFGCTRL[8]	BUFGCTRL[9]	BUFGCTRL[10]	BUFGCTRL[11]	BUFGCTRL[12]	BUFGCTRL[13]	BUFGCTRL[14]	BUFGCTRL[15]
CREATE_EDGE	MAIN[0][27][4]	MAIN[0][29][4]	MAIN[0][27][20]	MAIN[0][29][20]	MAIN[0][27][36]	MAIN[0][29][36]	MAIN[0][27][52]	MAIN[0][29][52]	MAIN[1][27][4]	MAIN[1][29][4]	MAIN[1][27][20]	MAIN[1][29][20]	MAIN[1][27][36]	MAIN[1][29][36]	MAIN[1][27][52]	MAIN[1][29][52]
INIT_OUT bit 0	MAIN[0][27][0]	MAIN[0][29][0]	MAIN[0][27][16]	MAIN[0][29][16]	MAIN[0][27][32]	MAIN[0][29][32]	MAIN[0][27][48]	MAIN[0][29][48]	MAIN[1][27][0]	MAIN[1][29][0]	MAIN[1][27][16]	MAIN[1][29][16]	MAIN[1][27][32]	MAIN[1][29][32]	MAIN[1][27][48]	MAIN[1][29][48]
PRESELECT_I0	!MAIN[0][27][11]	!MAIN[0][29][11]	!MAIN[0][27][27]	!MAIN[0][29][27]	!MAIN[0][27][43]	!MAIN[0][29][43]	!MAIN[0][27][59]	!MAIN[0][29][59]	!MAIN[1][27][11]	!MAIN[1][29][11]	!MAIN[1][27][27]	!MAIN[1][29][27]	!MAIN[1][27][43]	!MAIN[1][29][43]	!MAIN[1][27][59]	!MAIN[1][29][59]
PRESELECT_I1	MAIN[0][26][11]	MAIN[0][28][11]	MAIN[0][26][27]	MAIN[0][28][27]	MAIN[0][26][43]	MAIN[0][28][43]	MAIN[0][26][59]	MAIN[0][28][59]	MAIN[1][26][11]	MAIN[1][28][11]	MAIN[1][26][27]	MAIN[1][28][27]	MAIN[1][26][43]	MAIN[1][28][43]	MAIN[1][26][59]	MAIN[1][28][59]

Bel wires

virtex6 CLK_BUFG_S bel wires
Wire	Pins
CELL[0].IMUX_IMUX[0]	BUFGCTRL[4].IGNORE0
CELL[0].IMUX_IMUX[1]	BUFGCTRL[4].IGNORE1
CELL[0].IMUX_IMUX[2]	BUFGCTRL[4].S0
CELL[0].IMUX_IMUX[3]	BUFGCTRL[4].S1
CELL[0].IMUX_IMUX[4]	BUFGCTRL[4].CE0
CELL[0].IMUX_IMUX[5]	BUFGCTRL[4].CE1
CELL[0].IMUX_IMUX[10]	BUFGCTRL[3].CE1
CELL[0].IMUX_IMUX[11]	BUFGCTRL[3].CE0
CELL[0].IMUX_IMUX[12]	BUFGCTRL[3].S1
CELL[0].IMUX_IMUX[13]	BUFGCTRL[3].S0
CELL[0].IMUX_IMUX[14]	BUFGCTRL[3].IGNORE1
CELL[0].IMUX_IMUX[15]	BUFGCTRL[3].IGNORE0
CELL[0].IMUX_IMUX[16]	BUFGCTRL[2].IGNORE0
CELL[0].IMUX_IMUX[17]	BUFGCTRL[2].IGNORE1
CELL[0].IMUX_IMUX[18]	BUFGCTRL[2].S0
CELL[0].IMUX_IMUX[19]	BUFGCTRL[2].S1
CELL[0].IMUX_IMUX[20]	BUFGCTRL[2].CE0
CELL[0].IMUX_IMUX[21]	BUFGCTRL[2].CE1
CELL[0].IMUX_IMUX[26]	BUFGCTRL[1].CE1
CELL[0].IMUX_IMUX[27]	BUFGCTRL[1].CE0
CELL[0].IMUX_IMUX[28]	BUFGCTRL[1].S1
CELL[0].IMUX_IMUX[29]	BUFGCTRL[1].S0
CELL[0].IMUX_IMUX[30]	BUFGCTRL[1].IGNORE1
CELL[0].IMUX_IMUX[31]	BUFGCTRL[1].IGNORE0
CELL[0].IMUX_IMUX[32]	BUFGCTRL[0].IGNORE0
CELL[0].IMUX_IMUX[33]	BUFGCTRL[0].IGNORE1
CELL[0].IMUX_IMUX[34]	BUFGCTRL[0].S0
CELL[0].IMUX_IMUX[35]	BUFGCTRL[0].S1
CELL[0].IMUX_IMUX[36]	BUFGCTRL[0].CE0
CELL[0].IMUX_IMUX[37]	BUFGCTRL[0].CE1
CELL[1].IMUX_IMUX[0]	BUFGCTRL[5].IGNORE0
CELL[1].IMUX_IMUX[2]	BUFGCTRL[6].S1
CELL[1].IMUX_IMUX[3]	BUFGCTRL[7].S0
CELL[1].IMUX_IMUX[5]	BUFGCTRL[8].S0
CELL[1].IMUX_IMUX[6]	BUFGCTRL[9].S0
CELL[1].IMUX_IMUX[8]	BUFGCTRL[5].IGNORE1
CELL[1].IMUX_IMUX[10]	BUFGCTRL[6].S0
CELL[1].IMUX_IMUX[11]	BUFGCTRL[7].S1
CELL[1].IMUX_IMUX[13]	BUFGCTRL[8].IGNORE1
CELL[1].IMUX_IMUX[14]	BUFGCTRL[9].S1
CELL[1].IMUX_IMUX[16]	BUFGCTRL[5].S0
CELL[1].IMUX_IMUX[18]	BUFGCTRL[6].IGNORE1
CELL[1].IMUX_IMUX[19]	BUFGCTRL[7].CE0
CELL[1].IMUX_IMUX[20]	BUFGCTRL[8].CE1
CELL[1].IMUX_IMUX[21]	BUFGCTRL[8].IGNORE0
CELL[1].IMUX_IMUX[22]	BUFGCTRL[9].CE0
CELL[1].IMUX_IMUX[24]	BUFGCTRL[5].S1
CELL[1].IMUX_IMUX[26]	BUFGCTRL[6].IGNORE0
CELL[1].IMUX_IMUX[27]	BUFGCTRL[7].CE1
CELL[1].IMUX_IMUX[28]	BUFGCTRL[8].CE0
CELL[1].IMUX_IMUX[29]	BUFGCTRL[9].IGNORE0
CELL[1].IMUX_IMUX[30]	BUFGCTRL[9].CE1
CELL[1].IMUX_IMUX[31]	BUFGCTRL[10].CE1
CELL[1].IMUX_IMUX[32]	BUFGCTRL[5].CE0
CELL[1].IMUX_IMUX[33]	BUFGCTRL[6].CE1
CELL[1].IMUX_IMUX[34]	BUFGCTRL[7].IGNORE0
CELL[1].IMUX_IMUX[36]	BUFGCTRL[8].S1
CELL[1].IMUX_IMUX[37]	BUFGCTRL[9].IGNORE1
CELL[1].IMUX_IMUX[39]	BUFGCTRL[10].CE0
CELL[1].IMUX_IMUX[40]	BUFGCTRL[5].CE1
CELL[1].IMUX_IMUX[41]	BUFGCTRL[6].CE0
CELL[1].IMUX_IMUX[42]	BUFGCTRL[7].IGNORE1
CELL[1].OUT_BUFG[0]	BUFGCTRL[0].O
CELL[1].OUT_BUFG[1]	BUFGCTRL[1].O
CELL[1].OUT_BUFG[2]	BUFGCTRL[2].O
CELL[1].OUT_BUFG[3]	BUFGCTRL[3].O
CELL[1].OUT_BUFG[4]	BUFGCTRL[4].O
CELL[1].OUT_BUFG[5]	BUFGCTRL[5].O
CELL[1].OUT_BUFG[6]	BUFGCTRL[6].O
CELL[1].OUT_BUFG[7]	BUFGCTRL[7].O
CELL[1].OUT_BUFG[8]	BUFGCTRL[8].O
CELL[1].OUT_BUFG[9]	BUFGCTRL[9].O
CELL[1].OUT_BUFG[10]	BUFGCTRL[10].O
CELL[1].OUT_BUFG[11]	BUFGCTRL[11].O
CELL[1].OUT_BUFG[12]	BUFGCTRL[12].O
CELL[1].OUT_BUFG[13]	BUFGCTRL[13].O
CELL[1].OUT_BUFG[14]	BUFGCTRL[14].O
CELL[1].OUT_BUFG[15]	BUFGCTRL[15].O
CELL[1].IMUX_BUFG_O[0]	BUFGCTRL[0].I0
CELL[1].IMUX_BUFG_O[1]	BUFGCTRL[0].I1
CELL[1].IMUX_BUFG_O[2]	BUFGCTRL[1].I0
CELL[1].IMUX_BUFG_O[3]	BUFGCTRL[1].I1
CELL[1].IMUX_BUFG_O[4]	BUFGCTRL[2].I0
CELL[1].IMUX_BUFG_O[5]	BUFGCTRL[2].I1
CELL[1].IMUX_BUFG_O[6]	BUFGCTRL[3].I0
CELL[1].IMUX_BUFG_O[7]	BUFGCTRL[3].I1
CELL[1].IMUX_BUFG_O[8]	BUFGCTRL[4].I0
CELL[1].IMUX_BUFG_O[9]	BUFGCTRL[4].I1
CELL[1].IMUX_BUFG_O[10]	BUFGCTRL[5].I0
CELL[1].IMUX_BUFG_O[11]	BUFGCTRL[5].I1
CELL[1].IMUX_BUFG_O[12]	BUFGCTRL[6].I0
CELL[1].IMUX_BUFG_O[13]	BUFGCTRL[6].I1
CELL[1].IMUX_BUFG_O[14]	BUFGCTRL[7].I0
CELL[1].IMUX_BUFG_O[15]	BUFGCTRL[7].I1
CELL[1].IMUX_BUFG_O[16]	BUFGCTRL[8].I0
CELL[1].IMUX_BUFG_O[17]	BUFGCTRL[8].I1
CELL[1].IMUX_BUFG_O[18]	BUFGCTRL[9].I0
CELL[1].IMUX_BUFG_O[19]	BUFGCTRL[9].I1
CELL[1].IMUX_BUFG_O[20]	BUFGCTRL[10].I0
CELL[1].IMUX_BUFG_O[21]	BUFGCTRL[10].I1
CELL[1].IMUX_BUFG_O[22]	BUFGCTRL[11].I0
CELL[1].IMUX_BUFG_O[23]	BUFGCTRL[11].I1
CELL[1].IMUX_BUFG_O[24]	BUFGCTRL[12].I0
CELL[1].IMUX_BUFG_O[25]	BUFGCTRL[12].I1
CELL[1].IMUX_BUFG_O[26]	BUFGCTRL[13].I0
CELL[1].IMUX_BUFG_O[27]	BUFGCTRL[13].I1
CELL[1].IMUX_BUFG_O[28]	BUFGCTRL[14].I0
CELL[1].IMUX_BUFG_O[29]	BUFGCTRL[14].I1
CELL[1].IMUX_BUFG_O[30]	BUFGCTRL[15].I0
CELL[1].IMUX_BUFG_O[31]	BUFGCTRL[15].I1
CELL[2].IMUX_IMUX[0]	BUFGCTRL[10].S1
CELL[2].IMUX_IMUX[1]	BUFGCTRL[11].S0
CELL[2].IMUX_IMUX[3]	BUFGCTRL[12].IGNORE1
CELL[2].IMUX_IMUX[4]	BUFGCTRL[13].CE0
CELL[2].IMUX_IMUX[6]	BUFGCTRL[14].IGNORE1
CELL[2].IMUX_IMUX[7]	BUFGCTRL[15].S1
CELL[2].IMUX_IMUX[8]	BUFGCTRL[10].S0
CELL[2].IMUX_IMUX[9]	BUFGCTRL[11].S1
CELL[2].IMUX_IMUX[11]	BUFGCTRL[12].IGNORE0
CELL[2].IMUX_IMUX[12]	BUFGCTRL[13].CE1
CELL[2].IMUX_IMUX[13]	BUFGCTRL[14].CE1
CELL[2].IMUX_IMUX[14]	BUFGCTRL[14].IGNORE0
CELL[2].IMUX_IMUX[15]	BUFGCTRL[15].CE0
CELL[2].IMUX_IMUX[16]	BUFGCTRL[10].IGNORE1
CELL[2].IMUX_IMUX[17]	BUFGCTRL[11].CE0
CELL[2].IMUX_IMUX[18]	BUFGCTRL[12].CE1
CELL[2].IMUX_IMUX[19]	BUFGCTRL[13].IGNORE0
CELL[2].IMUX_IMUX[21]	BUFGCTRL[14].CE0
CELL[2].IMUX_IMUX[22]	BUFGCTRL[15].IGNORE0
CELL[2].IMUX_IMUX[23]	BUFGCTRL[15].CE1
CELL[2].IMUX_IMUX[24]	BUFGCTRL[10].IGNORE0
CELL[2].IMUX_IMUX[25]	BUFGCTRL[11].CE1
CELL[2].IMUX_IMUX[26]	BUFGCTRL[12].CE0
CELL[2].IMUX_IMUX[27]	BUFGCTRL[13].IGNORE1
CELL[2].IMUX_IMUX[29]	BUFGCTRL[14].S1
CELL[2].IMUX_IMUX[30]	BUFGCTRL[15].IGNORE1
CELL[2].IMUX_IMUX[32]	BUFGCTRL[11].IGNORE0
CELL[2].IMUX_IMUX[34]	BUFGCTRL[12].S1
CELL[2].IMUX_IMUX[35]	BUFGCTRL[13].S0
CELL[2].IMUX_IMUX[37]	BUFGCTRL[14].S0
CELL[2].IMUX_IMUX[38]	BUFGCTRL[15].S0
CELL[2].IMUX_IMUX[40]	BUFGCTRL[11].IGNORE1
CELL[2].IMUX_IMUX[42]	BUFGCTRL[12].S0
CELL[2].IMUX_IMUX[43]	BUFGCTRL[13].S1

Bitstream

virtex6 CLK_BUFG_S rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 4	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 5	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 6	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 7	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: PRESELECT_I1	BUFGCTRL[6]: ! PRESELECT_I0	BUFGCTRL[7]: PRESELECT_I1	BUFGCTRL[7]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 0	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 2	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 1	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[15] ← CELL[1].IMUX_BUFG_O[13]	SPEC_INT: buffer CELL[1].OUT_BEL[3] ← CELL[1].IMUX_BUFG_O[12]	SPEC_INT: buffer CELL[1].OUT_BEL[7] ← CELL[1].IMUX_BUFG_O[15]	SPEC_INT: buffer CELL[1].OUT_BEL[11] ← CELL[1].IMUX_BUFG_O[14]	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[12] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[13] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[14] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[15] bit 3	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: CREATE_EDGE	-	BUFGCTRL[7]: CREATE_EDGE	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[6] ← CELL[1].OUT_BUFG[6]	BUFGCTRL[7]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[7] ← CELL[1].OUT_BUFG[7]	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: !invert IGNORE0	BUFGCTRL[6]: !invert S1	BUFGCTRL[7]: !invert IGNORE0	BUFGCTRL[7]: !invert S1	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: !invert IGNORE1	BUFGCTRL[6]: !invert CE1	BUFGCTRL[7]: !invert IGNORE1	BUFGCTRL[7]: !invert CE1	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[6]: !invert CE0	BUFGCTRL[6]: INIT_OUT bit 0	BUFGCTRL[7]: !invert CE0	BUFGCTRL[7]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 4	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 5	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 6	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 7	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: PRESELECT_I1	BUFGCTRL[4]: ! PRESELECT_I0	BUFGCTRL[5]: PRESELECT_I1	BUFGCTRL[5]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 2	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 1	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[10] ← CELL[1].IMUX_BUFG_O[9]	SPEC_INT: buffer CELL[1].OUT_BEL[6] ← CELL[1].IMUX_BUFG_O[8]	SPEC_INT: buffer CELL[1].OUT_BEL[2] ← CELL[1].IMUX_BUFG_O[11]	SPEC_INT: buffer CELL[1].OUT_BEL[14] ← CELL[1].IMUX_BUFG_O[10]	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[8] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[9] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[10] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[11] bit 3	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: CREATE_EDGE	-	BUFGCTRL[5]: CREATE_EDGE	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[4] ← CELL[1].OUT_BUFG[4]	BUFGCTRL[5]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[5] ← CELL[1].OUT_BUFG[5]	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: !invert IGNORE0	BUFGCTRL[4]: !invert S1	BUFGCTRL[5]: !invert IGNORE0	BUFGCTRL[5]: !invert S1	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: !invert IGNORE1	BUFGCTRL[4]: !invert CE1	BUFGCTRL[5]: !invert IGNORE1	BUFGCTRL[5]: !invert CE1	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[4]: !invert CE0	BUFGCTRL[4]: INIT_OUT bit 0	BUFGCTRL[5]: !invert CE0	BUFGCTRL[5]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 1	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 2	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 3	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 3	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: PRESELECT_I1	BUFGCTRL[2]: ! PRESELECT_I0	BUFGCTRL[3]: PRESELECT_I1	BUFGCTRL[3]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 6	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 5	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 7	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[13] ← CELL[1].IMUX_BUFG_O[5]	SPEC_INT: buffer CELL[1].OUT_BEL[1] ← CELL[1].IMUX_BUFG_O[4]	SPEC_INT: buffer CELL[1].OUT_BEL[5] ← CELL[1].IMUX_BUFG_O[7]	SPEC_INT: buffer CELL[1].OUT_BEL[9] ← CELL[1].IMUX_BUFG_O[6]	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[4] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[5] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[6] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[7] bit 4	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: CREATE_EDGE	-	BUFGCTRL[3]: CREATE_EDGE	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[2] ← CELL[1].OUT_BUFG[2]	BUFGCTRL[3]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[3] ← CELL[1].OUT_BUFG[3]	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: !invert IGNORE0	BUFGCTRL[2]: !invert S1	BUFGCTRL[3]: !invert IGNORE0	BUFGCTRL[3]: !invert S1	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: !invert IGNORE1	BUFGCTRL[2]: !invert CE1	BUFGCTRL[3]: !invert IGNORE1	BUFGCTRL[3]: !invert CE1	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[2]: !invert CE0	BUFGCTRL[2]: INIT_OUT bit 0	BUFGCTRL[3]: !invert CE0	BUFGCTRL[3]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 1	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 2	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 3	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 3	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: PRESELECT_I1	BUFGCTRL[0]: ! PRESELECT_I0	BUFGCTRL[1]: PRESELECT_I1	BUFGCTRL[1]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 6	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 5	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 7	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[8] ← CELL[1].IMUX_BUFG_O[1]	SPEC_INT: buffer CELL[1].OUT_BEL[4] ← CELL[1].IMUX_BUFG_O[0]	SPEC_INT: buffer CELL[1].OUT_BEL[0] ← CELL[1].IMUX_BUFG_O[3]	SPEC_INT: buffer CELL[1].OUT_BEL[12] ← CELL[1].IMUX_BUFG_O[2]	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[0] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[1] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[2] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[3] bit 4	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: CREATE_EDGE	-	BUFGCTRL[1]: CREATE_EDGE	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[0] ← CELL[1].OUT_BUFG[0]	BUFGCTRL[1]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[1] ← CELL[1].OUT_BUFG[1]	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: !invert IGNORE0	BUFGCTRL[0]: !invert S1	BUFGCTRL[1]: !invert IGNORE0	BUFGCTRL[1]: !invert S1	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: !invert IGNORE1	BUFGCTRL[0]: !invert CE1	BUFGCTRL[1]: !invert IGNORE1	BUFGCTRL[1]: !invert CE1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[0]: !invert CE0	BUFGCTRL[0]: INIT_OUT bit 0	BUFGCTRL[1]: !invert CE0	BUFGCTRL[1]: INIT_OUT bit 0	-	-	-	-	-	-	-	-

virtex6 CLK_BUFG_S rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 4	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 5	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 6	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 7	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: PRESELECT_I1	BUFGCTRL[14]: ! PRESELECT_I0	BUFGCTRL[15]: PRESELECT_I1	BUFGCTRL[15]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 0	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 2	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 1	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[2].OUT_BEL[15] ← CELL[1].IMUX_BUFG_O[29]	SPEC_INT: buffer CELL[2].OUT_BEL[3] ← CELL[1].IMUX_BUFG_O[28]	SPEC_INT: buffer CELL[2].OUT_BEL[7] ← CELL[1].IMUX_BUFG_O[31]	SPEC_INT: buffer CELL[2].OUT_BEL[11] ← CELL[1].IMUX_BUFG_O[30]	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[28] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[29] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[30] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[31] bit 3	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: CREATE_EDGE	-	BUFGCTRL[15]: CREATE_EDGE	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[14] ← CELL[1].OUT_BUFG[14]	BUFGCTRL[15]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[15] ← CELL[1].OUT_BUFG[15]	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: !invert IGNORE0	BUFGCTRL[14]: !invert S1	BUFGCTRL[15]: !invert IGNORE0	BUFGCTRL[15]: !invert S1	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: !invert IGNORE1	BUFGCTRL[14]: !invert CE1	BUFGCTRL[15]: !invert IGNORE1	BUFGCTRL[15]: !invert CE1	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[14]: !invert CE0	BUFGCTRL[14]: INIT_OUT bit 0	BUFGCTRL[15]: !invert CE0	BUFGCTRL[15]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 4	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 5	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 6	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 7	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: PRESELECT_I1	BUFGCTRL[12]: ! PRESELECT_I0	BUFGCTRL[13]: PRESELECT_I1	BUFGCTRL[13]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 2	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 1	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[2].OUT_BEL[10] ← CELL[1].IMUX_BUFG_O[25]	SPEC_INT: buffer CELL[2].OUT_BEL[6] ← CELL[1].IMUX_BUFG_O[24]	SPEC_INT: buffer CELL[2].OUT_BEL[2] ← CELL[1].IMUX_BUFG_O[27]	SPEC_INT: buffer CELL[2].OUT_BEL[14] ← CELL[1].IMUX_BUFG_O[26]	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[24] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[25] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[26] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[27] bit 3	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: CREATE_EDGE	-	BUFGCTRL[13]: CREATE_EDGE	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[12] ← CELL[1].OUT_BUFG[12]	BUFGCTRL[13]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[13] ← CELL[1].OUT_BUFG[13]	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: !invert IGNORE0	BUFGCTRL[12]: !invert S1	BUFGCTRL[13]: !invert IGNORE0	BUFGCTRL[13]: !invert S1	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: !invert IGNORE1	BUFGCTRL[12]: !invert CE1	BUFGCTRL[13]: !invert IGNORE1	BUFGCTRL[13]: !invert CE1	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[12]: !invert CE0	BUFGCTRL[12]: INIT_OUT bit 0	BUFGCTRL[13]: !invert CE0	BUFGCTRL[13]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 4	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 5	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 6	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 7	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: PRESELECT_I1	BUFGCTRL[10]: ! PRESELECT_I0	BUFGCTRL[11]: PRESELECT_I1	BUFGCTRL[11]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 0	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 2	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 1	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[2].OUT_BEL[13] ← CELL[1].IMUX_BUFG_O[21]	SPEC_INT: buffer CELL[2].OUT_BEL[1] ← CELL[1].IMUX_BUFG_O[20]	SPEC_INT: buffer CELL[2].OUT_BEL[5] ← CELL[1].IMUX_BUFG_O[23]	SPEC_INT: buffer CELL[2].OUT_BEL[9] ← CELL[1].IMUX_BUFG_O[22]	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[20] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[21] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[22] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[23] bit 3	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: CREATE_EDGE	-	BUFGCTRL[11]: CREATE_EDGE	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[10] ← CELL[1].OUT_BUFG[10]	BUFGCTRL[11]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[11] ← CELL[1].OUT_BUFG[11]	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: !invert IGNORE0	BUFGCTRL[10]: !invert S1	BUFGCTRL[11]: !invert IGNORE0	BUFGCTRL[11]: !invert S1	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: !invert IGNORE1	BUFGCTRL[10]: !invert CE1	BUFGCTRL[11]: !invert IGNORE1	BUFGCTRL[11]: !invert CE1	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[10]: !invert CE0	BUFGCTRL[10]: INIT_OUT bit 0	BUFGCTRL[11]: !invert CE0	BUFGCTRL[11]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 4	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 4	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 5	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 5	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 6	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 6	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 7	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 7	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: PRESELECT_I1	BUFGCTRL[8]: ! PRESELECT_I0	BUFGCTRL[9]: PRESELECT_I1	BUFGCTRL[9]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 0	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 0	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 2	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 2	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 1	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 1	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[2].OUT_BEL[8] ← CELL[1].IMUX_BUFG_O[17]	SPEC_INT: buffer CELL[2].OUT_BEL[4] ← CELL[1].IMUX_BUFG_O[16]	SPEC_INT: buffer CELL[2].OUT_BEL[0] ← CELL[1].IMUX_BUFG_O[19]	SPEC_INT: buffer CELL[2].OUT_BEL[12] ← CELL[1].IMUX_BUFG_O[18]	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_BUFG_O[16] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[17] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[18] bit 3	SPEC_INT: mux CELL[1].IMUX_BUFG_O[19] bit 3	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: CREATE_EDGE	-	BUFGCTRL[9]: CREATE_EDGE	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[8] ← CELL[1].OUT_BUFG[8]	BUFGCTRL[9]: !invert S0	SPEC_INT: buffer CELL[1].OUT_BUFG_GFB[9] ← CELL[1].OUT_BUFG[9]	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: !invert IGNORE0	BUFGCTRL[8]: !invert S1	BUFGCTRL[9]: !invert IGNORE0	BUFGCTRL[9]: !invert S1	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: !invert IGNORE1	BUFGCTRL[8]: !invert CE1	BUFGCTRL[9]: !invert IGNORE1	BUFGCTRL[9]: !invert CE1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[8]: !invert CE0	BUFGCTRL[8]: INIT_OUT bit 0	BUFGCTRL[9]: !invert CE0	BUFGCTRL[9]: INIT_OUT bit 0	-	-	-	-	-	-	-	-

Tile CLK_BUFG_N

Cells: 7

Switchbox SPEC_INT

virtex6 CLK_BUFG_N switchbox SPEC_INT permanent buffers
Destination	Source
CELL[0].GCLK[16]	CELL[0].OUT_BUFG[0]
CELL[0].GCLK[17]	CELL[0].OUT_BUFG[1]
CELL[0].GCLK[18]	CELL[0].OUT_BUFG[2]
CELL[0].GCLK[19]	CELL[0].OUT_BUFG[3]
CELL[0].GCLK[20]	CELL[0].OUT_BUFG[4]
CELL[0].GCLK[21]	CELL[0].OUT_BUFG[5]
CELL[0].GCLK[22]	CELL[0].OUT_BUFG[6]
CELL[0].GCLK[23]	CELL[0].OUT_BUFG[7]
CELL[0].GCLK[24]	CELL[0].OUT_BUFG[8]
CELL[0].GCLK[25]	CELL[0].OUT_BUFG[9]
CELL[0].GCLK[26]	CELL[0].OUT_BUFG[10]
CELL[0].GCLK[27]	CELL[0].OUT_BUFG[11]
CELL[0].GCLK[28]	CELL[0].OUT_BUFG[12]
CELL[0].GCLK[29]	CELL[0].OUT_BUFG[13]
CELL[0].GCLK[30]	CELL[0].OUT_BUFG[14]
CELL[0].GCLK[31]	CELL[0].OUT_BUFG[15]
CELL[0].GIOB[4]	IO_W[0].OUT_CLKPAD
CELL[0].GIOB[5]	IO_E[0].OUT_CLKPAD
CELL[0].GIOB[6]	IO_W[1].OUT_CLKPAD
CELL[0].GIOB[7]	IO_E[1].OUT_CLKPAD

virtex6 CLK_BUFG_N switchbox SPEC_INT programmable buffers
Destination	Source	Bit
CELL[0].OUT_BEL[0]	CELL[0].IMUX_BUFG_O[3]	MAIN[0][28][6]
CELL[0].OUT_BEL[1]	CELL[0].IMUX_BUFG_O[4]	MAIN[0][27][22]
CELL[0].OUT_BEL[2]	CELL[0].IMUX_BUFG_O[11]	MAIN[0][28][38]
CELL[0].OUT_BEL[3]	CELL[0].IMUX_BUFG_O[12]	MAIN[0][27][54]
CELL[0].OUT_BEL[4]	CELL[0].IMUX_BUFG_O[0]	MAIN[0][27][6]
CELL[0].OUT_BEL[5]	CELL[0].IMUX_BUFG_O[7]	MAIN[0][28][22]
CELL[0].OUT_BEL[6]	CELL[0].IMUX_BUFG_O[8]	MAIN[0][27][38]
CELL[0].OUT_BEL[7]	CELL[0].IMUX_BUFG_O[15]	MAIN[0][28][54]
CELL[0].OUT_BEL[8]	CELL[0].IMUX_BUFG_O[1]	MAIN[0][26][6]
CELL[0].OUT_BEL[9]	CELL[0].IMUX_BUFG_O[6]	MAIN[0][29][22]
CELL[0].OUT_BEL[10]	CELL[0].IMUX_BUFG_O[9]	MAIN[0][26][38]
CELL[0].OUT_BEL[11]	CELL[0].IMUX_BUFG_O[14]	MAIN[0][29][54]
CELL[0].OUT_BEL[12]	CELL[0].IMUX_BUFG_O[2]	MAIN[0][29][6]
CELL[0].OUT_BEL[13]	CELL[0].IMUX_BUFG_O[5]	MAIN[0][26][22]
CELL[0].OUT_BEL[14]	CELL[0].IMUX_BUFG_O[10]	MAIN[0][29][38]
CELL[0].OUT_BEL[15]	CELL[0].IMUX_BUFG_O[13]	MAIN[0][26][54]
CELL[0].OUT_BUFG_GFB[0]	CELL[0].OUT_BUFG[0]	MAIN[0][27][3]
CELL[0].OUT_BUFG_GFB[1]	CELL[0].OUT_BUFG[1]	MAIN[0][29][3]
CELL[0].OUT_BUFG_GFB[2]	CELL[0].OUT_BUFG[2]	MAIN[0][27][19]
CELL[0].OUT_BUFG_GFB[3]	CELL[0].OUT_BUFG[3]	MAIN[0][29][19]
CELL[0].OUT_BUFG_GFB[4]	CELL[0].OUT_BUFG[4]	MAIN[0][27][35]
CELL[0].OUT_BUFG_GFB[5]	CELL[0].OUT_BUFG[5]	MAIN[0][29][35]
CELL[0].OUT_BUFG_GFB[6]	CELL[0].OUT_BUFG[6]	MAIN[0][27][51]
CELL[0].OUT_BUFG_GFB[7]	CELL[0].OUT_BUFG[7]	MAIN[0][29][51]
CELL[0].OUT_BUFG_GFB[8]	CELL[0].OUT_BUFG[8]	MAIN[1][27][3]
CELL[0].OUT_BUFG_GFB[9]	CELL[0].OUT_BUFG[9]	MAIN[1][29][3]
CELL[0].OUT_BUFG_GFB[10]	CELL[0].OUT_BUFG[10]	MAIN[1][27][19]
CELL[0].OUT_BUFG_GFB[11]	CELL[0].OUT_BUFG[11]	MAIN[1][29][19]
CELL[0].OUT_BUFG_GFB[12]	CELL[0].OUT_BUFG[12]	MAIN[1][27][35]
CELL[0].OUT_BUFG_GFB[13]	CELL[0].OUT_BUFG[13]	MAIN[1][29][35]
CELL[0].OUT_BUFG_GFB[14]	CELL[0].OUT_BUFG[14]	MAIN[1][27][51]
CELL[0].OUT_BUFG_GFB[15]	CELL[0].OUT_BUFG[15]	MAIN[1][29][51]
CELL[1].OUT_BEL[0]	CELL[0].IMUX_BUFG_O[19]	MAIN[1][28][6]
CELL[1].OUT_BEL[1]	CELL[0].IMUX_BUFG_O[20]	MAIN[1][27][22]
CELL[1].OUT_BEL[2]	CELL[0].IMUX_BUFG_O[27]	MAIN[1][28][38]
CELL[1].OUT_BEL[3]	CELL[0].IMUX_BUFG_O[28]	MAIN[1][27][54]
CELL[1].OUT_BEL[4]	CELL[0].IMUX_BUFG_O[16]	MAIN[1][27][6]
CELL[1].OUT_BEL[5]	CELL[0].IMUX_BUFG_O[23]	MAIN[1][28][22]
CELL[1].OUT_BEL[6]	CELL[0].IMUX_BUFG_O[24]	MAIN[1][27][38]
CELL[1].OUT_BEL[7]	CELL[0].IMUX_BUFG_O[31]	MAIN[1][28][54]
CELL[1].OUT_BEL[8]	CELL[0].IMUX_BUFG_O[17]	MAIN[1][26][6]
CELL[1].OUT_BEL[9]	CELL[0].IMUX_BUFG_O[22]	MAIN[1][29][22]
CELL[1].OUT_BEL[10]	CELL[0].IMUX_BUFG_O[25]	MAIN[1][26][38]
CELL[1].OUT_BEL[11]	CELL[0].IMUX_BUFG_O[30]	MAIN[1][29][54]
CELL[1].OUT_BEL[12]	CELL[0].IMUX_BUFG_O[18]	MAIN[1][29][6]
CELL[1].OUT_BEL[13]	CELL[0].IMUX_BUFG_O[21]	MAIN[1][26][22]
CELL[1].OUT_BEL[14]	CELL[0].IMUX_BUFG_O[26]	MAIN[1][29][38]
CELL[1].OUT_BEL[15]	CELL[0].IMUX_BUFG_O[29]	MAIN[1][26][54]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[0]
Bits								Destination
MAIN[0][26][8]	MAIN[0][27][10]	MAIN[0][26][9]	MAIN[0][26][5]	MAIN[0][27][12]	MAIN[0][27][14]	MAIN[0][26][15]	MAIN[0][26][13]	CELL[0].IMUX_BUFG_O[0]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[0]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[8]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[15]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[1]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[1]
Bits								Destination
MAIN[0][27][8]	MAIN[0][26][10]	MAIN[0][27][9]	MAIN[0][27][5]	MAIN[0][27][13]	MAIN[0][26][14]	MAIN[0][27][15]	MAIN[0][26][12]	CELL[0].IMUX_BUFG_O[1]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[1]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[0]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[15]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[1]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[2]
Bits								Destination
MAIN[0][28][8]	MAIN[0][29][10]	MAIN[0][28][9]	MAIN[0][28][5]	MAIN[0][29][12]	MAIN[0][29][14]	MAIN[0][28][15]	MAIN[0][28][13]	CELL[0].IMUX_BUFG_O[2]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[2]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[18]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[0]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[2]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[3]
Bits								Destination
MAIN[0][29][8]	MAIN[0][28][10]	MAIN[0][29][9]	MAIN[0][29][5]	MAIN[0][29][13]	MAIN[0][28][14]	MAIN[0][29][15]	MAIN[0][28][12]	CELL[0].IMUX_BUFG_O[3]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[3]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[26]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[0]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[2]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[4]
Bits								Destination
MAIN[0][26][24]	MAIN[0][27][26]	MAIN[0][26][25]	MAIN[0][26][21]	MAIN[0][27][28]	MAIN[0][27][30]	MAIN[0][26][31]	MAIN[0][26][29]	CELL[0].IMUX_BUFG_O[4]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[4]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[42]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[1]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[3]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[5]
Bits								Destination
MAIN[0][27][24]	MAIN[0][26][26]	MAIN[0][27][25]	MAIN[0][27][21]	MAIN[0][27][29]	MAIN[0][26][30]	MAIN[0][27][31]	MAIN[0][26][28]	CELL[0].IMUX_BUFG_O[5]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[5]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[34]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[1]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[3]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[6]
Bits								Destination
MAIN[0][28][24]	MAIN[0][29][26]	MAIN[0][28][25]	MAIN[0][28][21]	MAIN[0][29][28]	MAIN[0][29][30]	MAIN[0][28][31]	MAIN[0][28][29]	CELL[0].IMUX_BUFG_O[6]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[6]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[13]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[2]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[4]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[7]
Bits								Destination
MAIN[0][29][24]	MAIN[0][28][26]	MAIN[0][29][25]	MAIN[0][29][21]	MAIN[0][29][29]	MAIN[0][28][30]	MAIN[0][29][31]	MAIN[0][28][28]	CELL[0].IMUX_BUFG_O[7]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[7]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[21]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[2]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[4]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[8]
Bits								Destination
MAIN[0][26][40]	MAIN[0][27][42]	MAIN[0][26][41]	MAIN[0][26][37]	MAIN[0][27][44]	MAIN[0][27][46]	MAIN[0][26][47]	MAIN[0][26][45]	CELL[0].IMUX_BUFG_O[8]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[8]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[37]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[3]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[5]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[6]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[9]
Bits								Destination
MAIN[0][27][40]	MAIN[0][26][42]	MAIN[0][27][41]	MAIN[0][27][37]	MAIN[0][27][45]	MAIN[0][26][46]	MAIN[0][27][47]	MAIN[0][26][44]	CELL[0].IMUX_BUFG_O[9]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	1	0	0	0	0	CELL[0].IMUX_BUFG_I[9]
0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[29]
0	0	1	0	0	0	1	0	CELL[0].OUT_BUFG_GFB[3]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[5]
0	1	0	0	0	0	0	1	CELL[0].GIOB[3]
0	1	0	0	0	0	1	0	CELL[0].GIOB[0]
0	1	0	0	0	1	0	0	CELL[0].GIOB[1]
0	1	0	0	1	0	0	0	CELL[0].GIOB[2]
1	0	0	0	0	0	0	1	CELL[0].GIOB[7]
1	0	0	0	0	0	1	0	CELL[0].GIOB[4]
1	0	0	0	0	1	0	0	CELL[0].GIOB[5]
1	0	0	0	1	0	0	0	CELL[0].GIOB[6]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[10]
Bits								Destination
MAIN[0][29][44]	MAIN[0][28][45]	MAIN[0][29][46]	MAIN[0][28][47]	MAIN[0][28][37]	MAIN[0][28][41]	MAIN[0][28][40]	MAIN[0][29][42]	CELL[0].IMUX_BUFG_O[10]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[10]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[4]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[6]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[16]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[11]
Bits								Destination
MAIN[0][28][44]	MAIN[0][29][45]	MAIN[0][28][46]	MAIN[0][29][47]	MAIN[0][29][37]	MAIN[0][29][41]	MAIN[0][29][40]	MAIN[0][28][42]	CELL[0].IMUX_BUFG_O[11]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[11]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[4]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[6]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[24]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[12]
Bits								Destination
MAIN[0][27][60]	MAIN[0][26][61]	MAIN[0][27][62]	MAIN[0][26][63]	MAIN[0][26][53]	MAIN[0][26][57]	MAIN[0][26][56]	MAIN[0][27][58]	CELL[0].IMUX_BUFG_O[12]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[12]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[5]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[7]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[40]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[13]
Bits								Destination
MAIN[0][26][60]	MAIN[0][27][61]	MAIN[0][26][62]	MAIN[0][27][63]	MAIN[0][27][53]	MAIN[0][27][57]	MAIN[0][27][56]	MAIN[0][26][58]	CELL[0].IMUX_BUFG_O[13]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[13]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[5]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[7]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[32]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[14]
Bits								Destination
MAIN[0][29][60]	MAIN[0][28][61]	MAIN[0][29][62]	MAIN[0][28][63]	MAIN[0][28][53]	MAIN[0][28][57]	MAIN[0][28][56]	MAIN[0][29][58]	CELL[0].IMUX_BUFG_O[14]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[14]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[6]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[8]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[3]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[15]
Bits								Destination
MAIN[0][28][60]	MAIN[0][29][61]	MAIN[0][28][62]	MAIN[0][29][63]	MAIN[0][29][53]	MAIN[0][29][57]	MAIN[0][29][56]	MAIN[0][28][58]	CELL[0].IMUX_BUFG_O[15]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[15]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[6]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[8]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[11]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[16]
Bits								Destination
MAIN[1][27][12]	MAIN[1][26][13]	MAIN[1][27][14]	MAIN[1][26][15]	MAIN[1][26][5]	MAIN[1][26][9]	MAIN[1][26][8]	MAIN[1][27][10]	CELL[0].IMUX_BUFG_O[16]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[16]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[7]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[9]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[27]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[17]
Bits								Destination
MAIN[1][26][12]	MAIN[1][27][13]	MAIN[1][26][14]	MAIN[1][27][15]	MAIN[1][27][5]	MAIN[1][27][9]	MAIN[1][27][8]	MAIN[1][26][10]	CELL[0].IMUX_BUFG_O[17]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[17]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[7]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[9]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[19]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[18]
Bits								Destination
MAIN[1][29][12]	MAIN[1][28][13]	MAIN[1][29][14]	MAIN[1][28][15]	MAIN[1][28][5]	MAIN[1][28][9]	MAIN[1][28][8]	MAIN[1][29][10]	CELL[0].IMUX_BUFG_O[18]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[18]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[8]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[10]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[19]
Bits								Destination
MAIN[1][28][12]	MAIN[1][29][13]	MAIN[1][28][14]	MAIN[1][29][15]	MAIN[1][29][5]	MAIN[1][29][9]	MAIN[1][29][8]	MAIN[1][28][10]	CELL[0].IMUX_BUFG_O[19]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[19]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[8]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[10]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[14]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[20]
Bits								Destination
MAIN[1][27][28]	MAIN[1][26][29]	MAIN[1][27][30]	MAIN[1][26][31]	MAIN[1][26][21]	MAIN[1][26][25]	MAIN[1][26][24]	MAIN[1][27][26]	CELL[0].IMUX_BUFG_O[20]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[20]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[9]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[11]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[1].IMUX_IMUX[30]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[21]
Bits								Destination
MAIN[1][26][28]	MAIN[1][27][29]	MAIN[1][26][30]	MAIN[1][27][31]	MAIN[1][27][21]	MAIN[1][27][25]	MAIN[1][27][24]	MAIN[1][26][26]	CELL[0].IMUX_BUFG_O[21]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[21]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[9]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[11]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[1].IMUX_IMUX[22]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[22]
Bits								Destination
MAIN[1][29][28]	MAIN[1][28][29]	MAIN[1][29][30]	MAIN[1][28][31]	MAIN[1][28][21]	MAIN[1][28][25]	MAIN[1][28][24]	MAIN[1][29][26]	CELL[0].IMUX_BUFG_O[22]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[22]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[10]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[12]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[23]
Bits								Destination
MAIN[1][28][28]	MAIN[1][29][29]	MAIN[1][28][30]	MAIN[1][29][31]	MAIN[1][29][21]	MAIN[1][29][25]	MAIN[1][29][24]	MAIN[1][28][26]	CELL[0].IMUX_BUFG_O[23]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[23]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[10]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[12]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[24]
Bits								Destination
MAIN[1][27][44]	MAIN[1][26][45]	MAIN[1][27][46]	MAIN[1][26][47]	MAIN[1][26][37]	MAIN[1][26][41]	MAIN[1][26][40]	MAIN[1][27][42]	CELL[0].IMUX_BUFG_O[24]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[24]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[11]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[13]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[9]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[25]
Bits								Destination
MAIN[1][26][44]	MAIN[1][27][45]	MAIN[1][26][46]	MAIN[1][27][47]	MAIN[1][27][37]	MAIN[1][27][41]	MAIN[1][27][40]	MAIN[1][26][42]	CELL[0].IMUX_BUFG_O[25]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[25]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[11]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[13]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[8]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[26]
Bits								Destination
MAIN[1][29][44]	MAIN[1][28][45]	MAIN[1][29][46]	MAIN[1][28][47]	MAIN[1][28][37]	MAIN[1][28][41]	MAIN[1][28][40]	MAIN[1][29][42]	CELL[0].IMUX_BUFG_O[26]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[26]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[12]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[14]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[22]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[27]
Bits								Destination
MAIN[1][28][44]	MAIN[1][29][45]	MAIN[1][28][46]	MAIN[1][29][47]	MAIN[1][29][37]	MAIN[1][29][41]	MAIN[1][29][40]	MAIN[1][28][42]	CELL[0].IMUX_BUFG_O[27]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[27]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[12]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[14]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[23]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[28]
Bits								Destination
MAIN[1][27][60]	MAIN[1][26][61]	MAIN[1][27][62]	MAIN[1][26][63]	MAIN[1][26][53]	MAIN[1][26][57]	MAIN[1][26][56]	MAIN[1][27][58]	CELL[0].IMUX_BUFG_O[28]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[28]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[13]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[15]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[25]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[29]
Bits								Destination
MAIN[1][26][60]	MAIN[1][27][61]	MAIN[1][26][62]	MAIN[1][27][63]	MAIN[1][27][53]	MAIN[1][27][57]	MAIN[1][27][56]	MAIN[1][26][58]	CELL[0].IMUX_BUFG_O[29]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[29]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[13]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[15]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[24]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[30]
Bits								Destination
MAIN[1][29][60]	MAIN[1][28][61]	MAIN[1][29][62]	MAIN[1][28][63]	MAIN[1][28][53]	MAIN[1][28][57]	MAIN[1][28][56]	MAIN[1][29][58]	CELL[0].IMUX_BUFG_O[30]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[30]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[14]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[0]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
0	1	0	0	0	1	0	0	CELL[2].IMUX_IMUX[38]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]

virtex6 CLK_BUFG_N switchbox SPEC_INT muxes IMUX_BUFG_O[31]
Bits								Destination
MAIN[1][28][60]	MAIN[1][29][61]	MAIN[1][28][62]	MAIN[1][29][63]	MAIN[1][29][53]	MAIN[1][29][57]	MAIN[1][29][56]	MAIN[1][28][58]	CELL[0].IMUX_BUFG_O[31]
								Source
0	0	0	0	0	0	0	0	off
0	0	0	0	1	0	0	0	CELL[0].IMUX_BUFG_I[31]
0	0	0	1	0	0	0	1	CELL[0].GIOB[0]
0	0	0	1	0	0	1	0	CELL[0].GIOB[4]
0	0	0	1	0	1	0	0	CELL[0].OUT_BUFG_GFB[14]
0	0	1	0	0	0	0	1	CELL[0].GIOB[1]
0	0	1	0	0	0	1	0	CELL[0].GIOB[5]
0	0	1	0	0	1	0	0	CELL[0].OUT_BUFG_GFB[0]
0	1	0	0	0	0	0	1	CELL[0].GIOB[2]
0	1	0	0	0	0	1	0	CELL[0].GIOB[6]
1	0	0	0	0	0	0	1	CELL[0].GIOB[3]
1	0	0	0	0	0	1	0	CELL[0].GIOB[7]
1	0	0	0	0	1	0	0	CELL[2].IMUX_IMUX[39]

Bels BUFGCTRL

virtex6 CLK_BUFG_N bel BUFGCTRL pins
Pin	Direction	BUFGCTRL[16]	BUFGCTRL[17]	BUFGCTRL[18]	BUFGCTRL[19]	BUFGCTRL[20]	BUFGCTRL[21]	BUFGCTRL[22]	BUFGCTRL[23]	BUFGCTRL[24]	BUFGCTRL[25]	BUFGCTRL[26]	BUFGCTRL[27]	BUFGCTRL[28]	BUFGCTRL[29]	BUFGCTRL[30]	BUFGCTRL[31]
I0	in	CELL[0].IMUX_BUFG_O[0]	CELL[0].IMUX_BUFG_O[2]	CELL[0].IMUX_BUFG_O[4]	CELL[0].IMUX_BUFG_O[6]	CELL[0].IMUX_BUFG_O[8]	CELL[0].IMUX_BUFG_O[10]	CELL[0].IMUX_BUFG_O[12]	CELL[0].IMUX_BUFG_O[14]	CELL[0].IMUX_BUFG_O[16]	CELL[0].IMUX_BUFG_O[18]	CELL[0].IMUX_BUFG_O[20]	CELL[0].IMUX_BUFG_O[22]	CELL[0].IMUX_BUFG_O[24]	CELL[0].IMUX_BUFG_O[26]	CELL[0].IMUX_BUFG_O[28]	CELL[0].IMUX_BUFG_O[30]
I1	in	CELL[0].IMUX_BUFG_O[1]	CELL[0].IMUX_BUFG_O[3]	CELL[0].IMUX_BUFG_O[5]	CELL[0].IMUX_BUFG_O[7]	CELL[0].IMUX_BUFG_O[9]	CELL[0].IMUX_BUFG_O[11]	CELL[0].IMUX_BUFG_O[13]	CELL[0].IMUX_BUFG_O[15]	CELL[0].IMUX_BUFG_O[17]	CELL[0].IMUX_BUFG_O[19]	CELL[0].IMUX_BUFG_O[21]	CELL[0].IMUX_BUFG_O[23]	CELL[0].IMUX_BUFG_O[25]	CELL[0].IMUX_BUFG_O[27]	CELL[0].IMUX_BUFG_O[29]	CELL[0].IMUX_BUFG_O[31]
S0	in	CELL[0].IMUX_IMUX[40] invert by !MAIN[0][26][3]	CELL[0].IMUX_IMUX[33] invert by !MAIN[0][28][3]	CELL[0].IMUX_IMUX[27] invert by !MAIN[0][26][19]	CELL[0].IMUX_IMUX[20] invert by !MAIN[0][28][19]	CELL[0].IMUX_IMUX[30] invert by !MAIN[0][26][35]	CELL[0].IMUX_IMUX[31] invert by !MAIN[0][28][35]	CELL[1].IMUX_IMUX[25] invert by !MAIN[0][26][51]	CELL[1].IMUX_IMUX[18] invert by !MAIN[0][28][51]	CELL[1].IMUX_IMUX[12] invert by !MAIN[1][26][3]	CELL[1].IMUX_IMUX[13] invert by !MAIN[1][28][3]	CELL[1].IMUX_IMUX[23] invert by !MAIN[1][26][19]	CELL[2].IMUX_IMUX[2] invert by !MAIN[1][28][19]	CELL[2].IMUX_IMUX[13] invert by !MAIN[1][26][35]	CELL[2].IMUX_IMUX[18] invert by !MAIN[1][28][35]	CELL[2].IMUX_IMUX[29] invert by !MAIN[1][26][51]	CELL[2].IMUX_IMUX[34] invert by !MAIN[1][28][51]
S1	in	CELL[0].IMUX_IMUX[32] invert by !MAIN[0][27][2]	CELL[0].IMUX_IMUX[41] invert by !MAIN[0][29][2]	CELL[0].IMUX_IMUX[19] invert by !MAIN[0][27][18]	CELL[0].IMUX_IMUX[28] invert by !MAIN[0][29][18]	CELL[0].IMUX_IMUX[22] invert by !MAIN[0][27][34]	CELL[0].IMUX_IMUX[39] invert by !MAIN[0][29][34]	CELL[1].IMUX_IMUX[17] invert by !MAIN[0][27][50]	CELL[1].IMUX_IMUX[26] invert by !MAIN[0][29][50]	CELL[1].IMUX_IMUX[4] invert by !MAIN[1][27][2]	CELL[1].IMUX_IMUX[21] invert by !MAIN[1][29][2]	CELL[1].IMUX_IMUX[15] invert by !MAIN[1][27][18]	CELL[2].IMUX_IMUX[3] invert by !MAIN[1][29][18]	CELL[2].IMUX_IMUX[12] invert by !MAIN[1][27][34]	CELL[2].IMUX_IMUX[19] invert by !MAIN[1][29][34]	CELL[2].IMUX_IMUX[28] invert by !MAIN[1][27][50]	CELL[2].IMUX_IMUX[35] invert by !MAIN[1][29][50]
CE0	in	CELL[0].IMUX_IMUX[24] invert by !MAIN[0][26][0]	CELL[0].IMUX_IMUX[2] invert by !MAIN[0][28][0]	CELL[0].IMUX_IMUX[11] invert by !MAIN[0][26][16]	CELL[0].IMUX_IMUX[36] invert by !MAIN[0][28][16]	CELL[0].IMUX_IMUX[14] invert by !MAIN[0][26][32]	CELL[1].IMUX_IMUX[0] invert by !MAIN[0][28][32]	CELL[1].IMUX_IMUX[9] invert by !MAIN[0][26][48]	CELL[1].IMUX_IMUX[34] invert by !MAIN[0][28][48]	CELL[1].IMUX_IMUX[43] invert by !MAIN[1][26][0]	CELL[1].IMUX_IMUX[29] invert by !MAIN[1][28][0]	CELL[1].IMUX_IMUX[7] invert by !MAIN[1][26][16]	CELL[2].IMUX_IMUX[4] invert by !MAIN[1][28][16]	CELL[2].IMUX_IMUX[11] invert by !MAIN[1][26][32]	CELL[2].IMUX_IMUX[20] invert by !MAIN[1][28][32]	CELL[2].IMUX_IMUX[27] invert by !MAIN[1][26][48]	CELL[2].IMUX_IMUX[36] invert by !MAIN[1][28][48]
CE1	in	CELL[0].IMUX_IMUX[16] invert by !MAIN[0][27][1]	CELL[0].IMUX_IMUX[10] invert by !MAIN[0][29][1]	CELL[0].IMUX_IMUX[3] invert by !MAIN[0][27][17]	CELL[0].IMUX_IMUX[5] invert by !MAIN[0][29][17]	CELL[0].IMUX_IMUX[6] invert by !MAIN[0][27][33]	CELL[1].IMUX_IMUX[8] invert by !MAIN[0][29][33]	CELL[1].IMUX_IMUX[1] invert by !MAIN[0][27][49]	CELL[1].IMUX_IMUX[42] invert by !MAIN[0][29][49]	CELL[1].IMUX_IMUX[35] invert by !MAIN[1][27][1]	CELL[1].IMUX_IMUX[37] invert by !MAIN[1][29][1]	CELL[1].IMUX_IMUX[38] invert by !MAIN[1][27][17]	CELL[2].IMUX_IMUX[5] invert by !MAIN[1][29][17]	CELL[2].IMUX_IMUX[10] invert by !MAIN[1][27][33]	CELL[2].IMUX_IMUX[21] invert by !MAIN[1][29][33]	CELL[2].IMUX_IMUX[26] invert by !MAIN[1][27][49]	CELL[2].IMUX_IMUX[37] invert by !MAIN[1][29][49]
IGNORE0	in	CELL[0].IMUX_IMUX[9] invert by !MAIN[0][26][2]	CELL[0].IMUX_IMUX[17] invert by !MAIN[0][28][2]	CELL[0].IMUX_IMUX[43] invert by !MAIN[0][26][18]	CELL[0].IMUX_IMUX[4] invert by !MAIN[0][28][18]	CELL[0].IMUX_IMUX[7] invert by !MAIN[0][26][34]	CELL[0].IMUX_IMUX[15] invert by !MAIN[0][28][34]	CELL[1].IMUX_IMUX[41] invert by !MAIN[0][26][50]	CELL[1].IMUX_IMUX[2] invert by !MAIN[0][28][50]	CELL[1].IMUX_IMUX[28] invert by !MAIN[1][26][2]	CELL[1].IMUX_IMUX[36] invert by !MAIN[1][28][2]	CELL[1].IMUX_IMUX[39] invert by !MAIN[1][26][18]	CELL[2].IMUX_IMUX[0] invert by !MAIN[1][28][18]	CELL[2].IMUX_IMUX[15] invert by !MAIN[1][26][34]	CELL[2].IMUX_IMUX[16] invert by !MAIN[1][28][34]	CELL[2].IMUX_IMUX[31] invert by !MAIN[1][26][50]	CELL[2].IMUX_IMUX[32] invert by !MAIN[1][28][50]
IGNORE1	in	CELL[0].IMUX_IMUX[1] invert by !MAIN[0][26][1]	CELL[0].IMUX_IMUX[25] invert by !MAIN[0][28][1]	CELL[0].IMUX_IMUX[35] invert by !MAIN[0][26][17]	CELL[0].IMUX_IMUX[12] invert by !MAIN[0][28][17]	CELL[0].IMUX_IMUX[38] invert by !MAIN[0][26][33]	CELL[0].IMUX_IMUX[23] invert by !MAIN[0][28][33]	CELL[1].IMUX_IMUX[33] invert by !MAIN[0][26][49]	CELL[1].IMUX_IMUX[10] invert by !MAIN[0][28][49]	CELL[1].IMUX_IMUX[20] invert by !MAIN[1][26][1]	CELL[1].IMUX_IMUX[5] invert by !MAIN[1][28][1]	CELL[1].IMUX_IMUX[31] invert by !MAIN[1][26][17]	CELL[2].IMUX_IMUX[1] invert by !MAIN[1][28][17]	CELL[2].IMUX_IMUX[14] invert by !MAIN[1][26][33]	CELL[2].IMUX_IMUX[17] invert by !MAIN[1][28][33]	CELL[2].IMUX_IMUX[30] invert by !MAIN[1][26][49]	CELL[2].IMUX_IMUX[33] invert by !MAIN[1][28][49]
O	out	CELL[0].OUT_BUFG[0]	CELL[0].OUT_BUFG[1]	CELL[0].OUT_BUFG[2]	CELL[0].OUT_BUFG[3]	CELL[0].OUT_BUFG[4]	CELL[0].OUT_BUFG[5]	CELL[0].OUT_BUFG[6]	CELL[0].OUT_BUFG[7]	CELL[0].OUT_BUFG[8]	CELL[0].OUT_BUFG[9]	CELL[0].OUT_BUFG[10]	CELL[0].OUT_BUFG[11]	CELL[0].OUT_BUFG[12]	CELL[0].OUT_BUFG[13]	CELL[0].OUT_BUFG[14]	CELL[0].OUT_BUFG[15]

virtex6 CLK_BUFG_N bel BUFGCTRL attribute bits
Attribute	BUFGCTRL[16]	BUFGCTRL[17]	BUFGCTRL[18]	BUFGCTRL[19]	BUFGCTRL[20]	BUFGCTRL[21]	BUFGCTRL[22]	BUFGCTRL[23]	BUFGCTRL[24]	BUFGCTRL[25]	BUFGCTRL[26]	BUFGCTRL[27]	BUFGCTRL[28]	BUFGCTRL[29]	BUFGCTRL[30]	BUFGCTRL[31]
CREATE_EDGE	MAIN[0][27][4]	MAIN[0][29][4]	MAIN[0][27][20]	MAIN[0][29][20]	MAIN[0][27][36]	MAIN[0][29][36]	MAIN[0][27][52]	MAIN[0][29][52]	MAIN[1][27][4]	MAIN[1][29][4]	MAIN[1][27][20]	MAIN[1][29][20]	MAIN[1][27][36]	MAIN[1][29][36]	MAIN[1][27][52]	MAIN[1][29][52]
INIT_OUT bit 0	MAIN[0][27][0]	MAIN[0][29][0]	MAIN[0][27][16]	MAIN[0][29][16]	MAIN[0][27][32]	MAIN[0][29][32]	MAIN[0][27][48]	MAIN[0][29][48]	MAIN[1][27][0]	MAIN[1][29][0]	MAIN[1][27][16]	MAIN[1][29][16]	MAIN[1][27][32]	MAIN[1][29][32]	MAIN[1][27][48]	MAIN[1][29][48]
PRESELECT_I0	!MAIN[0][27][11]	!MAIN[0][29][11]	!MAIN[0][27][27]	!MAIN[0][29][27]	!MAIN[0][27][43]	!MAIN[0][29][43]	!MAIN[0][27][59]	!MAIN[0][29][59]	!MAIN[1][27][11]	!MAIN[1][29][11]	!MAIN[1][27][27]	!MAIN[1][29][27]	!MAIN[1][27][43]	!MAIN[1][29][43]	!MAIN[1][27][59]	!MAIN[1][29][59]
PRESELECT_I1	MAIN[0][26][11]	MAIN[0][28][11]	MAIN[0][26][27]	MAIN[0][28][27]	MAIN[0][26][43]	MAIN[0][28][43]	MAIN[0][26][59]	MAIN[0][28][59]	MAIN[1][26][11]	MAIN[1][28][11]	MAIN[1][26][27]	MAIN[1][28][27]	MAIN[1][26][43]	MAIN[1][28][43]	MAIN[1][26][59]	MAIN[1][28][59]

Bel wires

virtex6 CLK_BUFG_N bel wires
Wire	Pins
CELL[0].IMUX_IMUX[1]	BUFGCTRL[16].IGNORE1
CELL[0].IMUX_IMUX[2]	BUFGCTRL[17].CE0
CELL[0].IMUX_IMUX[3]	BUFGCTRL[18].CE1
CELL[0].IMUX_IMUX[4]	BUFGCTRL[19].IGNORE0
CELL[0].IMUX_IMUX[5]	BUFGCTRL[19].CE1
CELL[0].IMUX_IMUX[6]	BUFGCTRL[20].CE1
CELL[0].IMUX_IMUX[7]	BUFGCTRL[20].IGNORE0
CELL[0].IMUX_IMUX[9]	BUFGCTRL[16].IGNORE0
CELL[0].IMUX_IMUX[10]	BUFGCTRL[17].CE1
CELL[0].IMUX_IMUX[11]	BUFGCTRL[18].CE0
CELL[0].IMUX_IMUX[12]	BUFGCTRL[19].IGNORE1
CELL[0].IMUX_IMUX[14]	BUFGCTRL[20].CE0
CELL[0].IMUX_IMUX[15]	BUFGCTRL[21].IGNORE0
CELL[0].IMUX_IMUX[16]	BUFGCTRL[16].CE1
CELL[0].IMUX_IMUX[17]	BUFGCTRL[17].IGNORE0
CELL[0].IMUX_IMUX[19]	BUFGCTRL[18].S1
CELL[0].IMUX_IMUX[20]	BUFGCTRL[19].S0
CELL[0].IMUX_IMUX[22]	BUFGCTRL[20].S1
CELL[0].IMUX_IMUX[23]	BUFGCTRL[21].IGNORE1
CELL[0].IMUX_IMUX[24]	BUFGCTRL[16].CE0
CELL[0].IMUX_IMUX[25]	BUFGCTRL[17].IGNORE1
CELL[0].IMUX_IMUX[27]	BUFGCTRL[18].S0
CELL[0].IMUX_IMUX[28]	BUFGCTRL[19].S1
CELL[0].IMUX_IMUX[30]	BUFGCTRL[20].S0
CELL[0].IMUX_IMUX[31]	BUFGCTRL[21].S0
CELL[0].IMUX_IMUX[32]	BUFGCTRL[16].S1
CELL[0].IMUX_IMUX[33]	BUFGCTRL[17].S0
CELL[0].IMUX_IMUX[35]	BUFGCTRL[18].IGNORE1
CELL[0].IMUX_IMUX[36]	BUFGCTRL[19].CE0
CELL[0].IMUX_IMUX[38]	BUFGCTRL[20].IGNORE1
CELL[0].IMUX_IMUX[39]	BUFGCTRL[21].S1
CELL[0].IMUX_IMUX[40]	BUFGCTRL[16].S0
CELL[0].IMUX_IMUX[41]	BUFGCTRL[17].S1
CELL[0].IMUX_IMUX[43]	BUFGCTRL[18].IGNORE0
CELL[0].OUT_BUFG[0]	BUFGCTRL[16].O
CELL[0].OUT_BUFG[1]	BUFGCTRL[17].O
CELL[0].OUT_BUFG[2]	BUFGCTRL[18].O
CELL[0].OUT_BUFG[3]	BUFGCTRL[19].O
CELL[0].OUT_BUFG[4]	BUFGCTRL[20].O
CELL[0].OUT_BUFG[5]	BUFGCTRL[21].O
CELL[0].OUT_BUFG[6]	BUFGCTRL[22].O
CELL[0].OUT_BUFG[7]	BUFGCTRL[23].O
CELL[0].OUT_BUFG[8]	BUFGCTRL[24].O
CELL[0].OUT_BUFG[9]	BUFGCTRL[25].O
CELL[0].OUT_BUFG[10]	BUFGCTRL[26].O
CELL[0].OUT_BUFG[11]	BUFGCTRL[27].O
CELL[0].OUT_BUFG[12]	BUFGCTRL[28].O
CELL[0].OUT_BUFG[13]	BUFGCTRL[29].O
CELL[0].OUT_BUFG[14]	BUFGCTRL[30].O
CELL[0].OUT_BUFG[15]	BUFGCTRL[31].O
CELL[0].IMUX_BUFG_O[0]	BUFGCTRL[16].I0
CELL[0].IMUX_BUFG_O[1]	BUFGCTRL[16].I1
CELL[0].IMUX_BUFG_O[2]	BUFGCTRL[17].I0
CELL[0].IMUX_BUFG_O[3]	BUFGCTRL[17].I1
CELL[0].IMUX_BUFG_O[4]	BUFGCTRL[18].I0
CELL[0].IMUX_BUFG_O[5]	BUFGCTRL[18].I1
CELL[0].IMUX_BUFG_O[6]	BUFGCTRL[19].I0
CELL[0].IMUX_BUFG_O[7]	BUFGCTRL[19].I1
CELL[0].IMUX_BUFG_O[8]	BUFGCTRL[20].I0
CELL[0].IMUX_BUFG_O[9]	BUFGCTRL[20].I1
CELL[0].IMUX_BUFG_O[10]	BUFGCTRL[21].I0
CELL[0].IMUX_BUFG_O[11]	BUFGCTRL[21].I1
CELL[0].IMUX_BUFG_O[12]	BUFGCTRL[22].I0
CELL[0].IMUX_BUFG_O[13]	BUFGCTRL[22].I1
CELL[0].IMUX_BUFG_O[14]	BUFGCTRL[23].I0
CELL[0].IMUX_BUFG_O[15]	BUFGCTRL[23].I1
CELL[0].IMUX_BUFG_O[16]	BUFGCTRL[24].I0
CELL[0].IMUX_BUFG_O[17]	BUFGCTRL[24].I1
CELL[0].IMUX_BUFG_O[18]	BUFGCTRL[25].I0
CELL[0].IMUX_BUFG_O[19]	BUFGCTRL[25].I1
CELL[0].IMUX_BUFG_O[20]	BUFGCTRL[26].I0
CELL[0].IMUX_BUFG_O[21]	BUFGCTRL[26].I1
CELL[0].IMUX_BUFG_O[22]	BUFGCTRL[27].I0
CELL[0].IMUX_BUFG_O[23]	BUFGCTRL[27].I1
CELL[0].IMUX_BUFG_O[24]	BUFGCTRL[28].I0
CELL[0].IMUX_BUFG_O[25]	BUFGCTRL[28].I1
CELL[0].IMUX_BUFG_O[26]	BUFGCTRL[29].I0
CELL[0].IMUX_BUFG_O[27]	BUFGCTRL[29].I1
CELL[0].IMUX_BUFG_O[28]	BUFGCTRL[30].I0
CELL[0].IMUX_BUFG_O[29]	BUFGCTRL[30].I1
CELL[0].IMUX_BUFG_O[30]	BUFGCTRL[31].I0
CELL[0].IMUX_BUFG_O[31]	BUFGCTRL[31].I1
CELL[1].IMUX_IMUX[0]	BUFGCTRL[21].CE0
CELL[1].IMUX_IMUX[1]	BUFGCTRL[22].CE1
CELL[1].IMUX_IMUX[2]	BUFGCTRL[23].IGNORE0
CELL[1].IMUX_IMUX[4]	BUFGCTRL[24].S1
CELL[1].IMUX_IMUX[5]	BUFGCTRL[25].IGNORE1
CELL[1].IMUX_IMUX[7]	BUFGCTRL[26].CE0
CELL[1].IMUX_IMUX[8]	BUFGCTRL[21].CE1
CELL[1].IMUX_IMUX[9]	BUFGCTRL[22].CE0
CELL[1].IMUX_IMUX[10]	BUFGCTRL[23].IGNORE1
CELL[1].IMUX_IMUX[12]	BUFGCTRL[24].S0
CELL[1].IMUX_IMUX[13]	BUFGCTRL[25].S0
CELL[1].IMUX_IMUX[15]	BUFGCTRL[26].S1
CELL[1].IMUX_IMUX[17]	BUFGCTRL[22].S1
CELL[1].IMUX_IMUX[18]	BUFGCTRL[23].S0
CELL[1].IMUX_IMUX[20]	BUFGCTRL[24].IGNORE1
CELL[1].IMUX_IMUX[21]	BUFGCTRL[25].S1
CELL[1].IMUX_IMUX[23]	BUFGCTRL[26].S0
CELL[1].IMUX_IMUX[25]	BUFGCTRL[22].S0
CELL[1].IMUX_IMUX[26]	BUFGCTRL[23].S1
CELL[1].IMUX_IMUX[28]	BUFGCTRL[24].IGNORE0
CELL[1].IMUX_IMUX[29]	BUFGCTRL[25].CE0
CELL[1].IMUX_IMUX[31]	BUFGCTRL[26].IGNORE1
CELL[1].IMUX_IMUX[33]	BUFGCTRL[22].IGNORE1
CELL[1].IMUX_IMUX[34]	BUFGCTRL[23].CE0
CELL[1].IMUX_IMUX[35]	BUFGCTRL[24].CE1
CELL[1].IMUX_IMUX[36]	BUFGCTRL[25].IGNORE0
CELL[1].IMUX_IMUX[37]	BUFGCTRL[25].CE1
CELL[1].IMUX_IMUX[38]	BUFGCTRL[26].CE1
CELL[1].IMUX_IMUX[39]	BUFGCTRL[26].IGNORE0
CELL[1].IMUX_IMUX[41]	BUFGCTRL[22].IGNORE0
CELL[1].IMUX_IMUX[42]	BUFGCTRL[23].CE1
CELL[1].IMUX_IMUX[43]	BUFGCTRL[24].CE0
CELL[2].IMUX_IMUX[0]	BUFGCTRL[27].IGNORE0
CELL[2].IMUX_IMUX[1]	BUFGCTRL[27].IGNORE1
CELL[2].IMUX_IMUX[2]	BUFGCTRL[27].S0
CELL[2].IMUX_IMUX[3]	BUFGCTRL[27].S1
CELL[2].IMUX_IMUX[4]	BUFGCTRL[27].CE0
CELL[2].IMUX_IMUX[5]	BUFGCTRL[27].CE1
CELL[2].IMUX_IMUX[10]	BUFGCTRL[28].CE1
CELL[2].IMUX_IMUX[11]	BUFGCTRL[28].CE0
CELL[2].IMUX_IMUX[12]	BUFGCTRL[28].S1
CELL[2].IMUX_IMUX[13]	BUFGCTRL[28].S0
CELL[2].IMUX_IMUX[14]	BUFGCTRL[28].IGNORE1
CELL[2].IMUX_IMUX[15]	BUFGCTRL[28].IGNORE0
CELL[2].IMUX_IMUX[16]	BUFGCTRL[29].IGNORE0
CELL[2].IMUX_IMUX[17]	BUFGCTRL[29].IGNORE1
CELL[2].IMUX_IMUX[18]	BUFGCTRL[29].S0
CELL[2].IMUX_IMUX[19]	BUFGCTRL[29].S1
CELL[2].IMUX_IMUX[20]	BUFGCTRL[29].CE0
CELL[2].IMUX_IMUX[21]	BUFGCTRL[29].CE1
CELL[2].IMUX_IMUX[26]	BUFGCTRL[30].CE1
CELL[2].IMUX_IMUX[27]	BUFGCTRL[30].CE0
CELL[2].IMUX_IMUX[28]	BUFGCTRL[30].S1
CELL[2].IMUX_IMUX[29]	BUFGCTRL[30].S0
CELL[2].IMUX_IMUX[30]	BUFGCTRL[30].IGNORE1
CELL[2].IMUX_IMUX[31]	BUFGCTRL[30].IGNORE0
CELL[2].IMUX_IMUX[32]	BUFGCTRL[31].IGNORE0
CELL[2].IMUX_IMUX[33]	BUFGCTRL[31].IGNORE1
CELL[2].IMUX_IMUX[34]	BUFGCTRL[31].S0
CELL[2].IMUX_IMUX[35]	BUFGCTRL[31].S1
CELL[2].IMUX_IMUX[36]	BUFGCTRL[31].CE0
CELL[2].IMUX_IMUX[37]	BUFGCTRL[31].CE1

Bitstream

virtex6 CLK_BUFG_N rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 4	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 5	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 6	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 7	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: PRESELECT_I1	BUFGCTRL[22]: ! PRESELECT_I0	BUFGCTRL[23]: PRESELECT_I1	BUFGCTRL[23]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 0	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 2	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 1	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[0].OUT_BEL[15] ← CELL[0].IMUX_BUFG_O[13]	SPEC_INT: buffer CELL[0].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[12]	SPEC_INT: buffer CELL[0].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[15]	SPEC_INT: buffer CELL[0].OUT_BEL[11] ← CELL[0].IMUX_BUFG_O[14]	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[12] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[13] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[14] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[15] bit 3	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: CREATE_EDGE	-	BUFGCTRL[23]: CREATE_EDGE	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[6] ← CELL[0].OUT_BUFG[6]	BUFGCTRL[23]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[7] ← CELL[0].OUT_BUFG[7]	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: !invert IGNORE0	BUFGCTRL[22]: !invert S1	BUFGCTRL[23]: !invert IGNORE0	BUFGCTRL[23]: !invert S1	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: !invert IGNORE1	BUFGCTRL[22]: !invert CE1	BUFGCTRL[23]: !invert IGNORE1	BUFGCTRL[23]: !invert CE1	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[22]: !invert CE0	BUFGCTRL[22]: INIT_OUT bit 0	BUFGCTRL[23]: !invert CE0	BUFGCTRL[23]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 4	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 5	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 6	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 7	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: PRESELECT_I1	BUFGCTRL[20]: ! PRESELECT_I0	BUFGCTRL[21]: PRESELECT_I1	BUFGCTRL[21]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 2	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 1	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[0].OUT_BEL[10] ← CELL[0].IMUX_BUFG_O[9]	SPEC_INT: buffer CELL[0].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[8]	SPEC_INT: buffer CELL[0].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[11]	SPEC_INT: buffer CELL[0].OUT_BEL[14] ← CELL[0].IMUX_BUFG_O[10]	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[8] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[9] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[10] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[11] bit 3	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: CREATE_EDGE	-	BUFGCTRL[21]: CREATE_EDGE	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[4] ← CELL[0].OUT_BUFG[4]	BUFGCTRL[21]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[5] ← CELL[0].OUT_BUFG[5]	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: !invert IGNORE0	BUFGCTRL[20]: !invert S1	BUFGCTRL[21]: !invert IGNORE0	BUFGCTRL[21]: !invert S1	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: !invert IGNORE1	BUFGCTRL[20]: !invert CE1	BUFGCTRL[21]: !invert IGNORE1	BUFGCTRL[21]: !invert CE1	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[20]: !invert CE0	BUFGCTRL[20]: INIT_OUT bit 0	BUFGCTRL[21]: !invert CE0	BUFGCTRL[21]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 1	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 2	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 3	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 3	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: PRESELECT_I1	BUFGCTRL[18]: ! PRESELECT_I0	BUFGCTRL[19]: PRESELECT_I1	BUFGCTRL[19]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 6	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 5	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 7	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[0].OUT_BEL[13] ← CELL[0].IMUX_BUFG_O[5]	SPEC_INT: buffer CELL[0].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[4]	SPEC_INT: buffer CELL[0].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[7]	SPEC_INT: buffer CELL[0].OUT_BEL[9] ← CELL[0].IMUX_BUFG_O[6]	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[4] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[5] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[6] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[7] bit 4	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: CREATE_EDGE	-	BUFGCTRL[19]: CREATE_EDGE	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[2] ← CELL[0].OUT_BUFG[2]	BUFGCTRL[19]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[3] ← CELL[0].OUT_BUFG[3]	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: !invert IGNORE0	BUFGCTRL[18]: !invert S1	BUFGCTRL[19]: !invert IGNORE0	BUFGCTRL[19]: !invert S1	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: !invert IGNORE1	BUFGCTRL[18]: !invert CE1	BUFGCTRL[19]: !invert IGNORE1	BUFGCTRL[19]: !invert CE1	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[18]: !invert CE0	BUFGCTRL[18]: INIT_OUT bit 0	BUFGCTRL[19]: !invert CE0	BUFGCTRL[19]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 1	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 2	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 3	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 3	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: PRESELECT_I1	BUFGCTRL[16]: ! PRESELECT_I0	BUFGCTRL[17]: PRESELECT_I1	BUFGCTRL[17]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 6	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 5	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 7	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[0].OUT_BEL[8] ← CELL[0].IMUX_BUFG_O[1]	SPEC_INT: buffer CELL[0].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[0]	SPEC_INT: buffer CELL[0].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[3]	SPEC_INT: buffer CELL[0].OUT_BEL[12] ← CELL[0].IMUX_BUFG_O[2]	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[0] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[1] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[2] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[3] bit 4	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: CREATE_EDGE	-	BUFGCTRL[17]: CREATE_EDGE	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[0] ← CELL[0].OUT_BUFG[0]	BUFGCTRL[17]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[1] ← CELL[0].OUT_BUFG[1]	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: !invert IGNORE0	BUFGCTRL[16]: !invert S1	BUFGCTRL[17]: !invert IGNORE0	BUFGCTRL[17]: !invert S1	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: !invert IGNORE1	BUFGCTRL[16]: !invert CE1	BUFGCTRL[17]: !invert IGNORE1	BUFGCTRL[17]: !invert CE1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[16]: !invert CE0	BUFGCTRL[16]: INIT_OUT bit 0	BUFGCTRL[17]: !invert CE0	BUFGCTRL[17]: INIT_OUT bit 0	-	-	-	-	-	-	-	-

virtex6 CLK_BUFG_N rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 4	-	-	-	-	-	-	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 5	-	-	-	-	-	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 6	-	-	-	-	-	-	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 7	-	-	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: PRESELECT_I1	BUFGCTRL[30]: ! PRESELECT_I0	BUFGCTRL[31]: PRESELECT_I1	BUFGCTRL[31]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 0	-	-	-	-	-	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 2	-	-	-	-	-	-	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 1	-	-	-	-	-	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[15] ← CELL[0].IMUX_BUFG_O[29]	SPEC_INT: buffer CELL[1].OUT_BEL[3] ← CELL[0].IMUX_BUFG_O[28]	SPEC_INT: buffer CELL[1].OUT_BEL[7] ← CELL[0].IMUX_BUFG_O[31]	SPEC_INT: buffer CELL[1].OUT_BEL[11] ← CELL[0].IMUX_BUFG_O[30]	-	-	-	-	-	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[28] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[29] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[30] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[31] bit 3	-	-	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: CREATE_EDGE	-	BUFGCTRL[31]: CREATE_EDGE	-	-	-	-	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[14] ← CELL[0].OUT_BUFG[14]	BUFGCTRL[31]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[15] ← CELL[0].OUT_BUFG[15]	-	-	-	-	-	-	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: !invert IGNORE0	BUFGCTRL[30]: !invert S1	BUFGCTRL[31]: !invert IGNORE0	BUFGCTRL[31]: !invert S1	-	-	-	-	-	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: !invert IGNORE1	BUFGCTRL[30]: !invert CE1	BUFGCTRL[31]: !invert IGNORE1	BUFGCTRL[31]: !invert CE1	-	-	-	-	-	-	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[30]: !invert CE0	BUFGCTRL[30]: INIT_OUT bit 0	BUFGCTRL[31]: !invert CE0	BUFGCTRL[31]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 4	-	-	-	-	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 5	-	-	-	-	-	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 6	-	-	-	-	-	-	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 7	-	-	-	-	-	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: PRESELECT_I1	BUFGCTRL[28]: ! PRESELECT_I0	BUFGCTRL[29]: PRESELECT_I1	BUFGCTRL[29]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 0	-	-	-	-	-	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 2	-	-	-	-	-	-	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 1	-	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[10] ← CELL[0].IMUX_BUFG_O[25]	SPEC_INT: buffer CELL[1].OUT_BEL[6] ← CELL[0].IMUX_BUFG_O[24]	SPEC_INT: buffer CELL[1].OUT_BEL[2] ← CELL[0].IMUX_BUFG_O[27]	SPEC_INT: buffer CELL[1].OUT_BEL[14] ← CELL[0].IMUX_BUFG_O[26]	-	-	-	-	-	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[24] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[25] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[26] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[27] bit 3	-	-	-	-	-	-	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: CREATE_EDGE	-	BUFGCTRL[29]: CREATE_EDGE	-	-	-	-	-	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[12] ← CELL[0].OUT_BUFG[12]	BUFGCTRL[29]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[13] ← CELL[0].OUT_BUFG[13]	-	-	-	-	-	-	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: !invert IGNORE0	BUFGCTRL[28]: !invert S1	BUFGCTRL[29]: !invert IGNORE0	BUFGCTRL[29]: !invert S1	-	-	-	-	-	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: !invert IGNORE1	BUFGCTRL[28]: !invert CE1	BUFGCTRL[29]: !invert IGNORE1	BUFGCTRL[29]: !invert CE1	-	-	-	-	-	-	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[28]: !invert CE0	BUFGCTRL[28]: INIT_OUT bit 0	BUFGCTRL[29]: !invert CE0	BUFGCTRL[29]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 4	-	-	-	-	-	-	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 5	-	-	-	-	-	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 6	-	-	-	-	-	-	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 7	-	-	-	-	-	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: PRESELECT_I1	BUFGCTRL[26]: ! PRESELECT_I0	BUFGCTRL[27]: PRESELECT_I1	BUFGCTRL[27]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 0	-	-	-	-	-	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 2	-	-	-	-	-	-	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 1	-	-	-	-	-	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[13] ← CELL[0].IMUX_BUFG_O[21]	SPEC_INT: buffer CELL[1].OUT_BEL[1] ← CELL[0].IMUX_BUFG_O[20]	SPEC_INT: buffer CELL[1].OUT_BEL[5] ← CELL[0].IMUX_BUFG_O[23]	SPEC_INT: buffer CELL[1].OUT_BEL[9] ← CELL[0].IMUX_BUFG_O[22]	-	-	-	-	-	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[20] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[21] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[22] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[23] bit 3	-	-	-	-	-	-	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: CREATE_EDGE	-	BUFGCTRL[27]: CREATE_EDGE	-	-	-	-	-	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[10] ← CELL[0].OUT_BUFG[10]	BUFGCTRL[27]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[11] ← CELL[0].OUT_BUFG[11]	-	-	-	-	-	-	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: !invert IGNORE0	BUFGCTRL[26]: !invert S1	BUFGCTRL[27]: !invert IGNORE0	BUFGCTRL[27]: !invert S1	-	-	-	-	-	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: !invert IGNORE1	BUFGCTRL[26]: !invert CE1	BUFGCTRL[27]: !invert IGNORE1	BUFGCTRL[27]: !invert CE1	-	-	-	-	-	-	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[26]: !invert CE0	BUFGCTRL[26]: INIT_OUT bit 0	BUFGCTRL[27]: !invert CE0	BUFGCTRL[27]: INIT_OUT bit 0	-	-	-	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 4	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 4	-	-	-	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 5	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 5	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 6	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 6	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 7	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 7	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: PRESELECT_I1	BUFGCTRL[24]: ! PRESELECT_I0	BUFGCTRL[25]: PRESELECT_I1	BUFGCTRL[25]: ! PRESELECT_I0	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 0	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 0	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 2	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 2	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 1	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 1	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: buffer CELL[1].OUT_BEL[8] ← CELL[0].IMUX_BUFG_O[17]	SPEC_INT: buffer CELL[1].OUT_BEL[4] ← CELL[0].IMUX_BUFG_O[16]	SPEC_INT: buffer CELL[1].OUT_BEL[0] ← CELL[0].IMUX_BUFG_O[19]	SPEC_INT: buffer CELL[1].OUT_BEL[12] ← CELL[0].IMUX_BUFG_O[18]	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_BUFG_O[16] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[17] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[18] bit 3	SPEC_INT: mux CELL[0].IMUX_BUFG_O[19] bit 3	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: CREATE_EDGE	-	BUFGCTRL[25]: CREATE_EDGE	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[8] ← CELL[0].OUT_BUFG[8]	BUFGCTRL[25]: !invert S0	SPEC_INT: buffer CELL[0].OUT_BUFG_GFB[9] ← CELL[0].OUT_BUFG[9]	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: !invert IGNORE0	BUFGCTRL[24]: !invert S1	BUFGCTRL[25]: !invert IGNORE0	BUFGCTRL[25]: !invert S1	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: !invert IGNORE1	BUFGCTRL[24]: !invert CE1	BUFGCTRL[25]: !invert IGNORE1	BUFGCTRL[25]: !invert CE1	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	BUFGCTRL[24]: !invert CE0	BUFGCTRL[24]: INIT_OUT bit 0	BUFGCTRL[25]: !invert CE0	BUFGCTRL[25]: INIT_OUT bit 0	-	-	-	-	-	-	-	-

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