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Clock column buffers

Tile HCLK

Cells: 2

Bel HCLK

virtex6 HCLK bel HCLK
PinDirectionWires
LCLK0_DoutputCELL0.LCLK0
LCLK0_UoutputCELL1.LCLK0
LCLK1_DoutputCELL0.LCLK1
LCLK1_UoutputCELL1.LCLK1
LCLK2_DoutputCELL0.LCLK2
LCLK2_UoutputCELL1.LCLK2
LCLK3_DoutputCELL0.LCLK3
LCLK3_UoutputCELL1.LCLK3
LCLK4_DoutputCELL0.LCLK4
LCLK4_UoutputCELL1.LCLK4
LCLK5_DoutputCELL0.LCLK5
LCLK5_UoutputCELL1.LCLK5
LCLK6_DoutputCELL0.LCLK6
LCLK6_UoutputCELL1.LCLK6
LCLK7_DoutputCELL0.LCLK7
LCLK7_UoutputCELL1.LCLK7

Bel GLOBALSIG

virtex6 HCLK bel GLOBALSIG
PinDirectionWires

Bel wires

virtex6 HCLK bel wires
WirePins
CELL0.LCLK0HCLK.LCLK0_D
CELL0.LCLK1HCLK.LCLK1_D
CELL0.LCLK2HCLK.LCLK2_D
CELL0.LCLK3HCLK.LCLK3_D
CELL0.LCLK4HCLK.LCLK4_D
CELL0.LCLK5HCLK.LCLK5_D
CELL0.LCLK6HCLK.LCLK6_D
CELL0.LCLK7HCLK.LCLK7_D
CELL1.LCLK0HCLK.LCLK0_U
CELL1.LCLK1HCLK.LCLK1_U
CELL1.LCLK2HCLK.LCLK2_U
CELL1.LCLK3HCLK.LCLK3_U
CELL1.LCLK4HCLK.LCLK4_U
CELL1.LCLK5HCLK.LCLK5_U
CELL1.LCLK6HCLK.LCLK6_U
CELL1.LCLK7HCLK.LCLK7_U

Bitstream

virtex6 HCLK rect R0
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25
B31 HCLK:MUX.LCLK0_U[6] HCLK:MUX.LCLK0_U[7] HCLK:MUX.LCLK1_U[7] HCLK:MUX.LCLK1_U[6] HCLK:MUX.LCLK4_U[6] HCLK:MUX.LCLK4_U[7] HCLK:MUX.LCLK5_U[7] HCLK:MUX.LCLK5_U[6] HCLK:ENABLE.HCLK11 - - - - - - - - - - - - - - - - -
B30 HCLK:MUX.LCLK0_U[5] HCLK:MUX.LCLK0_U[8] HCLK:MUX.LCLK1_U[8] HCLK:MUX.LCLK1_U[5] HCLK:MUX.LCLK4_U[5] HCLK:MUX.LCLK4_U[8] HCLK:MUX.LCLK5_U[8] HCLK:MUX.LCLK5_U[5] HCLK:ENABLE.HCLK10 - - - - - - - - - - - - - - - - -
B29 HCLK:MUX.LCLK0_U[3] HCLK:MUX.LCLK0_U[4] HCLK:MUX.LCLK1_U[4] HCLK:MUX.LCLK1_U[3] HCLK:MUX.LCLK4_U[3] HCLK:MUX.LCLK4_U[4] HCLK:MUX.LCLK5_U[4] HCLK:MUX.LCLK5_U[3] HCLK:ENABLE.HCLK9 - - - - - - - - - - - - - - - - -
B28 HCLK:MUX.LCLK0_U[1] HCLK:MUX.LCLK0_U[2] HCLK:MUX.LCLK1_U[2] HCLK:MUX.LCLK1_U[1] HCLK:MUX.LCLK4_U[1] HCLK:MUX.LCLK4_U[2] HCLK:MUX.LCLK5_U[2] HCLK:MUX.LCLK5_U[1] HCLK:ENABLE.HCLK8 - - - - - - - - - - - - - - - - -
B27 HCLK:MUX.LCLK2_U[7] HCLK:MUX.LCLK0_U[0] HCLK:MUX.LCLK1_U[0] HCLK:MUX.LCLK3_U[7] HCLK:MUX.LCLK6_U[7] HCLK:MUX.LCLK4_U[0] HCLK:MUX.LCLK5_U[0] HCLK:MUX.LCLK7_U[7] HCLK:ENABLE.HCLK7 - - - - - - - - - - - - - - - - -
B26 HCLK:MUX.LCLK2_U[8] HCLK:MUX.LCLK2_U[6] HCLK:MUX.LCLK3_U[6] HCLK:MUX.LCLK3_U[8] HCLK:MUX.LCLK6_U[8] HCLK:MUX.LCLK6_U[6] HCLK:MUX.LCLK7_U[6] HCLK:MUX.LCLK7_U[8] HCLK:ENABLE.HCLK6 - - - - - - - - - - - - - - - - -
B25 HCLK:MUX.LCLK2_U[4] HCLK:MUX.LCLK2_U[5] HCLK:MUX.LCLK3_U[5] HCLK:MUX.LCLK3_U[4] HCLK:MUX.LCLK6_U[4] HCLK:MUX.LCLK6_U[5] HCLK:MUX.LCLK7_U[5] HCLK:MUX.LCLK7_U[4] HCLK:ENABLE.HCLK5 - - - - - - - - - - - - - - - - -
B24 HCLK:MUX.LCLK2_U[2] HCLK:MUX.LCLK2_U[3] HCLK:MUX.LCLK3_U[3] HCLK:MUX.LCLK3_U[2] HCLK:MUX.LCLK6_U[2] HCLK:MUX.LCLK6_U[3] HCLK:MUX.LCLK7_U[3] HCLK:MUX.LCLK7_U[2] HCLK:ENABLE.HCLK4 - - - - - - - - - - - - - - - - -
B23 HCLK:MUX.LCLK2_U[0] HCLK:MUX.LCLK2_U[1] HCLK:MUX.LCLK3_U[1] HCLK:MUX.LCLK3_U[0] HCLK:MUX.LCLK6_U[0] HCLK:MUX.LCLK6_U[1] HCLK:MUX.LCLK7_U[1] HCLK:MUX.LCLK7_U[0] HCLK:ENABLE.HCLK3 - - - - - - - - - - - - - - - - -
B22 HCLK:MUX.LCLK0_D[6] HCLK:MUX.LCLK0_D[7] HCLK:MUX.LCLK1_D[7] HCLK:MUX.LCLK1_D[6] HCLK:MUX.LCLK4_D[6] HCLK:MUX.LCLK4_D[7] HCLK:MUX.LCLK5_D[7] HCLK:MUX.LCLK5_D[6] HCLK:ENABLE.HCLK2 - - - - - - - - - - - - - - - - -
B21 HCLK:MUX.LCLK0_D[5] HCLK:MUX.LCLK0_D[8] HCLK:MUX.LCLK1_D[8] HCLK:MUX.LCLK1_D[5] HCLK:MUX.LCLK4_D[5] HCLK:MUX.LCLK4_D[8] HCLK:MUX.LCLK5_D[8] HCLK:MUX.LCLK5_D[5] HCLK:ENABLE.HCLK1 - - - - - - - - - - - - - - - - -
B20 HCLK:MUX.LCLK0_D[3] HCLK:MUX.LCLK0_D[4] HCLK:MUX.LCLK1_D[4] HCLK:MUX.LCLK1_D[3] HCLK:MUX.LCLK4_D[3] HCLK:MUX.LCLK4_D[4] HCLK:MUX.LCLK5_D[4] HCLK:MUX.LCLK5_D[3] HCLK:ENABLE.HCLK0 - - - - - - - - - - - - - - - - -
B19 HCLK:MUX.LCLK0_D[1] HCLK:MUX.LCLK0_D[2] HCLK:MUX.LCLK1_D[2] HCLK:MUX.LCLK1_D[1] HCLK:MUX.LCLK4_D[1] HCLK:MUX.LCLK4_D[2] HCLK:MUX.LCLK5_D[2] HCLK:MUX.LCLK5_D[1] HCLK:ENABLE.RCLK5 - - - - - - - - - - - - - - - - -
B18 HCLK:MUX.LCLK2_D[7] HCLK:MUX.LCLK0_D[0] HCLK:MUX.LCLK1_D[0] HCLK:MUX.LCLK3_D[7] HCLK:MUX.LCLK6_D[7] HCLK:MUX.LCLK4_D[0] HCLK:MUX.LCLK5_D[0] HCLK:MUX.LCLK7_D[7] HCLK:ENABLE.RCLK4 - - - - - - - - - - - - - - - - -
B17 HCLK:MUX.LCLK2_D[8] HCLK:MUX.LCLK2_D[6] HCLK:MUX.LCLK3_D[6] HCLK:MUX.LCLK3_D[8] HCLK:MUX.LCLK6_D[8] HCLK:MUX.LCLK6_D[6] HCLK:MUX.LCLK7_D[6] HCLK:MUX.LCLK7_D[8] HCLK:ENABLE.RCLK3 - - - - - - - - - - - - - - - - -
B16 HCLK:MUX.LCLK2_D[4] HCLK:MUX.LCLK2_D[5] HCLK:MUX.LCLK3_D[5] HCLK:MUX.LCLK3_D[4] HCLK:MUX.LCLK6_D[4] HCLK:MUX.LCLK6_D[5] HCLK:MUX.LCLK7_D[5] HCLK:MUX.LCLK7_D[4] HCLK:ENABLE.RCLK2 - - - - - - - - - - - - - - - - -
B15 HCLK:MUX.LCLK2_D[2] HCLK:MUX.LCLK2_D[3] HCLK:MUX.LCLK3_D[3] HCLK:MUX.LCLK3_D[2] HCLK:MUX.LCLK6_D[2] HCLK:MUX.LCLK6_D[3] HCLK:MUX.LCLK7_D[3] HCLK:MUX.LCLK7_D[2] HCLK:ENABLE.RCLK1 - - - - - - - - - - - - - - - - -
B14 HCLK:MUX.LCLK2_D[0] HCLK:MUX.LCLK2_D[1] HCLK:MUX.LCLK3_D[1] HCLK:MUX.LCLK3_D[0] HCLK:MUX.LCLK6_D[0] HCLK:MUX.LCLK6_D[1] HCLK:MUX.LCLK7_D[1] HCLK:MUX.LCLK7_D[0] HCLK:ENABLE.RCLK0 - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - HCLK:DRP_MASK_SYSMON HCLK:DRP_MASK_BELOW HCLK:DRP_MASK_ABOVE
B12 - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - -
HCLK:DRP_MASK_ABOVE 0.F25.B13
HCLK:DRP_MASK_BELOW 0.F24.B13
HCLK:DRP_MASK_SYSMON 0.F23.B13
HCLK:ENABLE.HCLK0 0.F8.B20
HCLK:ENABLE.HCLK1 0.F8.B21
HCLK:ENABLE.HCLK10 0.F8.B30
HCLK:ENABLE.HCLK11 0.F8.B31
HCLK:ENABLE.HCLK2 0.F8.B22
HCLK:ENABLE.HCLK3 0.F8.B23
HCLK:ENABLE.HCLK4 0.F8.B24
HCLK:ENABLE.HCLK5 0.F8.B25
HCLK:ENABLE.HCLK6 0.F8.B26
HCLK:ENABLE.HCLK7 0.F8.B27
HCLK:ENABLE.HCLK8 0.F8.B28
HCLK:ENABLE.HCLK9 0.F8.B29
HCLK:ENABLE.RCLK0 0.F8.B14
HCLK:ENABLE.RCLK1 0.F8.B15
HCLK:ENABLE.RCLK2 0.F8.B16
HCLK:ENABLE.RCLK3 0.F8.B17
HCLK:ENABLE.RCLK4 0.F8.B18
HCLK:ENABLE.RCLK5 0.F8.B19
non-inverted [0]
HCLK:MUX.LCLK0_D 0.F1.B21 0.F1.B22 0.F0.B22 0.F0.B21 0.F1.B20 0.F0.B20 0.F1.B19 0.F0.B19 0.F1.B18
HCLK:MUX.LCLK0_U 0.F1.B30 0.F1.B31 0.F0.B31 0.F0.B30 0.F1.B29 0.F0.B29 0.F1.B28 0.F0.B28 0.F1.B27
HCLK:MUX.LCLK1_D 0.F2.B21 0.F2.B22 0.F3.B22 0.F3.B21 0.F2.B20 0.F3.B20 0.F2.B19 0.F3.B19 0.F2.B18
HCLK:MUX.LCLK1_U 0.F2.B30 0.F2.B31 0.F3.B31 0.F3.B30 0.F2.B29 0.F3.B29 0.F2.B28 0.F3.B28 0.F2.B27
HCLK:MUX.LCLK2_D 0.F0.B17 0.F0.B18 0.F1.B17 0.F1.B16 0.F0.B16 0.F1.B15 0.F0.B15 0.F1.B14 0.F0.B14
HCLK:MUX.LCLK2_U 0.F0.B26 0.F0.B27 0.F1.B26 0.F1.B25 0.F0.B25 0.F1.B24 0.F0.B24 0.F1.B23 0.F0.B23
HCLK:MUX.LCLK3_D 0.F3.B17 0.F3.B18 0.F2.B17 0.F2.B16 0.F3.B16 0.F2.B15 0.F3.B15 0.F2.B14 0.F3.B14
HCLK:MUX.LCLK3_U 0.F3.B26 0.F3.B27 0.F2.B26 0.F2.B25 0.F3.B25 0.F2.B24 0.F3.B24 0.F2.B23 0.F3.B23
HCLK:MUX.LCLK4_D 0.F5.B21 0.F5.B22 0.F4.B22 0.F4.B21 0.F5.B20 0.F4.B20 0.F5.B19 0.F4.B19 0.F5.B18
HCLK:MUX.LCLK4_U 0.F5.B30 0.F5.B31 0.F4.B31 0.F4.B30 0.F5.B29 0.F4.B29 0.F5.B28 0.F4.B28 0.F5.B27
HCLK:MUX.LCLK5_D 0.F6.B21 0.F6.B22 0.F7.B22 0.F7.B21 0.F6.B20 0.F7.B20 0.F6.B19 0.F7.B19 0.F6.B18
HCLK:MUX.LCLK5_U 0.F6.B30 0.F6.B31 0.F7.B31 0.F7.B30 0.F6.B29 0.F7.B29 0.F6.B28 0.F7.B28 0.F6.B27
HCLK:MUX.LCLK6_D 0.F4.B17 0.F4.B18 0.F5.B17 0.F5.B16 0.F4.B16 0.F5.B15 0.F4.B15 0.F5.B14 0.F4.B14
HCLK:MUX.LCLK6_U 0.F4.B26 0.F4.B27 0.F5.B26 0.F5.B25 0.F4.B25 0.F5.B24 0.F4.B24 0.F5.B23 0.F4.B23
HCLK:MUX.LCLK7_D 0.F7.B17 0.F7.B18 0.F6.B17 0.F6.B16 0.F7.B16 0.F6.B15 0.F7.B15 0.F6.B14 0.F7.B14
HCLK:MUX.LCLK7_U 0.F7.B26 0.F7.B27 0.F6.B26 0.F6.B25 0.F7.B25 0.F6.B24 0.F7.B24 0.F6.B23 0.F7.B23
NONE 0 0 0 0 0 0 0 0 0
HCLK0 0 0 1 0 0 0 0 0 1
HCLK1 0 0 1 0 0 0 0 1 0
HCLK2 0 0 1 0 0 0 1 0 0
HCLK3 0 0 1 0 0 1 0 0 0
HCLK4 0 0 1 0 1 0 0 0 0
HCLK5 0 0 1 1 0 0 0 0 0
HCLK6 0 1 0 0 0 0 0 0 1
HCLK7 0 1 0 0 0 0 0 1 0
HCLK8 0 1 0 0 0 0 1 0 0
HCLK9 0 1 0 0 0 1 0 0 0
HCLK10 0 1 0 0 1 0 0 0 0
HCLK11 0 1 0 1 0 0 0 0 0
RCLK0 1 0 0 0 0 0 0 0 1
RCLK1 1 0 0 0 0 0 0 1 0
RCLK2 1 0 0 0 0 0 1 0 0
RCLK3 1 0 0 0 0 1 0 0 0
RCLK4 1 0 0 0 1 0 0 0 0
RCLK5 1 0 0 1 0 0 0 0 0

Tile HCLK_QBUF

Cells: 0

Bel HCLK_QBUF

virtex6 HCLK_QBUF bel HCLK_QBUF
PinDirectionWires

Tile MGT_BUF

Cells: 0

Bel MGT_BUF

virtex6 MGT_BUF bel MGT_BUF
PinDirectionWires