Clock column buffers

Tile HCLK

Cells: 2

Switchbox HCLK

virtex6 HCLK switchbox HCLK programmable buffers
Destination	Source	Bit
N.HCLK_BUF[0]	N.HCLK_ROW[0]	MAIN[8][20]
N.HCLK_BUF[1]	N.HCLK_ROW[1]	MAIN[8][21]
N.HCLK_BUF[2]	N.HCLK_ROW[2]	MAIN[8][22]
N.HCLK_BUF[3]	N.HCLK_ROW[3]	MAIN[8][23]
N.HCLK_BUF[4]	N.HCLK_ROW[4]	MAIN[8][24]
N.HCLK_BUF[5]	N.HCLK_ROW[5]	MAIN[8][25]
N.HCLK_BUF[6]	N.HCLK_ROW[6]	MAIN[8][26]
N.HCLK_BUF[7]	N.HCLK_ROW[7]	MAIN[8][27]
N.HCLK_BUF[8]	N.HCLK_ROW[8]	MAIN[8][28]
N.HCLK_BUF[9]	N.HCLK_ROW[9]	MAIN[8][29]
N.HCLK_BUF[10]	N.HCLK_ROW[10]	MAIN[8][30]
N.HCLK_BUF[11]	N.HCLK_ROW[11]	MAIN[8][31]
N.RCLK_BUF[0]	N.RCLK_ROW[0]	MAIN[8][14]
N.RCLK_BUF[1]	N.RCLK_ROW[1]	MAIN[8][15]
N.RCLK_BUF[2]	N.RCLK_ROW[2]	MAIN[8][16]
N.RCLK_BUF[3]	N.RCLK_ROW[3]	MAIN[8][17]
N.RCLK_BUF[4]	N.RCLK_ROW[4]	MAIN[8][18]
N.RCLK_BUF[5]	N.RCLK_ROW[5]	MAIN[8][19]

virtex6 HCLK switchbox HCLK muxes LCLK[0]
Bits									Destination
MAIN[1][21]	MAIN[1][22]	MAIN[0][22]	MAIN[0][21]	MAIN[1][20]	MAIN[0][20]	MAIN[1][19]	MAIN[0][19]	MAIN[1][18]	S.LCLK[0]
MAIN[1][30]	MAIN[1][31]	MAIN[0][31]	MAIN[0][30]	MAIN[1][29]	MAIN[0][29]	MAIN[1][28]	MAIN[0][28]	MAIN[1][27]	N.LCLK[0]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[1]
Bits									Destination
MAIN[2][21]	MAIN[2][22]	MAIN[3][22]	MAIN[3][21]	MAIN[2][20]	MAIN[3][20]	MAIN[2][19]	MAIN[3][19]	MAIN[2][18]	S.LCLK[1]
MAIN[2][30]	MAIN[2][31]	MAIN[3][31]	MAIN[3][30]	MAIN[2][29]	MAIN[3][29]	MAIN[2][28]	MAIN[3][28]	MAIN[2][27]	N.LCLK[1]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[2]
Bits									Destination
MAIN[0][17]	MAIN[0][18]	MAIN[1][17]	MAIN[1][16]	MAIN[0][16]	MAIN[1][15]	MAIN[0][15]	MAIN[1][14]	MAIN[0][14]	S.LCLK[2]
MAIN[0][26]	MAIN[0][27]	MAIN[1][26]	MAIN[1][25]	MAIN[0][25]	MAIN[1][24]	MAIN[0][24]	MAIN[1][23]	MAIN[0][23]	N.LCLK[2]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[3]
Bits									Destination
MAIN[3][17]	MAIN[3][18]	MAIN[2][17]	MAIN[2][16]	MAIN[3][16]	MAIN[2][15]	MAIN[3][15]	MAIN[2][14]	MAIN[3][14]	S.LCLK[3]
MAIN[3][26]	MAIN[3][27]	MAIN[2][26]	MAIN[2][25]	MAIN[3][25]	MAIN[2][24]	MAIN[3][24]	MAIN[2][23]	MAIN[3][23]	N.LCLK[3]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[4]
Bits									Destination
MAIN[5][21]	MAIN[5][22]	MAIN[4][22]	MAIN[4][21]	MAIN[5][20]	MAIN[4][20]	MAIN[5][19]	MAIN[4][19]	MAIN[5][18]	S.LCLK[4]
MAIN[5][30]	MAIN[5][31]	MAIN[4][31]	MAIN[4][30]	MAIN[5][29]	MAIN[4][29]	MAIN[5][28]	MAIN[4][28]	MAIN[5][27]	N.LCLK[4]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[5]
Bits									Destination
MAIN[6][21]	MAIN[6][22]	MAIN[7][22]	MAIN[7][21]	MAIN[6][20]	MAIN[7][20]	MAIN[6][19]	MAIN[7][19]	MAIN[6][18]	S.LCLK[5]
MAIN[6][30]	MAIN[6][31]	MAIN[7][31]	MAIN[7][30]	MAIN[6][29]	MAIN[7][29]	MAIN[6][28]	MAIN[7][28]	MAIN[6][27]	N.LCLK[5]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[6]
Bits									Destination
MAIN[4][17]	MAIN[4][18]	MAIN[5][17]	MAIN[5][16]	MAIN[4][16]	MAIN[5][15]	MAIN[4][15]	MAIN[5][14]	MAIN[4][14]	S.LCLK[6]
MAIN[4][26]	MAIN[4][27]	MAIN[5][26]	MAIN[5][25]	MAIN[4][25]	MAIN[5][24]	MAIN[4][24]	MAIN[5][23]	MAIN[4][23]	N.LCLK[6]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

virtex6 HCLK switchbox HCLK muxes LCLK[7]
Bits									Destination
MAIN[7][17]	MAIN[7][18]	MAIN[6][17]	MAIN[6][16]	MAIN[7][16]	MAIN[6][15]	MAIN[7][15]	MAIN[6][14]	MAIN[7][14]	S.LCLK[7]
MAIN[7][26]	MAIN[7][27]	MAIN[6][26]	MAIN[6][25]	MAIN[7][25]	MAIN[6][24]	MAIN[7][24]	MAIN[6][23]	MAIN[7][23]	N.LCLK[7]
									Source
0	0	0	0	0	0	0	0	0	off
0	0	1	0	0	0	0	0	1	N.HCLK_BUF[0]
0	0	1	0	0	0	0	1	0	N.HCLK_BUF[1]
0	0	1	0	0	0	1	0	0	N.HCLK_BUF[2]
0	0	1	0	0	1	0	0	0	N.HCLK_BUF[3]
0	0	1	0	1	0	0	0	0	N.HCLK_BUF[4]
0	0	1	1	0	0	0	0	0	N.HCLK_BUF[5]
0	1	0	0	0	0	0	0	1	N.HCLK_BUF[6]
0	1	0	0	0	0	0	1	0	N.HCLK_BUF[7]
0	1	0	0	0	0	1	0	0	N.HCLK_BUF[8]
0	1	0	0	0	1	0	0	0	N.HCLK_BUF[9]
0	1	0	0	1	0	0	0	0	N.HCLK_BUF[10]
0	1	0	1	0	0	0	0	0	N.HCLK_BUF[11]
1	0	0	0	0	0	0	0	1	N.RCLK_BUF[0]
1	0	0	0	0	0	0	1	0	N.RCLK_BUF[1]
1	0	0	0	0	0	1	0	0	N.RCLK_BUF[2]
1	0	0	0	0	1	0	0	0	N.RCLK_BUF[3]
1	0	0	0	1	0	0	0	0	N.RCLK_BUF[4]
1	0	0	1	0	0	0	0	0	N.RCLK_BUF[5]

Bels GLOBALSIG

virtex6 HCLK bel GLOBALSIG pins
Pin	Direction	GLOBALSIG

Bels HCLK_DRP

virtex6 HCLK bel HCLK_DRP pins
Pin	Direction	HCLK_DRP[0]

virtex6 HCLK bel HCLK_DRP attribute bits
Attribute	HCLK_DRP[0]
DRP_MASK_S	MAIN[24][13]
DRP_MASK_N	MAIN[25][13]
DRP_MASK_SYSMON	MAIN[23][13]

Bitstream

virtex6 HCLK rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27
B31	HCLK: mux N.LCLK[0] bit 6	HCLK: mux N.LCLK[0] bit 7	HCLK: mux N.LCLK[1] bit 7	HCLK: mux N.LCLK[1] bit 6	HCLK: mux N.LCLK[4] bit 6	HCLK: mux N.LCLK[4] bit 7	HCLK: mux N.LCLK[5] bit 7	HCLK: mux N.LCLK[5] bit 6	HCLK: buffer N.HCLK_BUF[11] ← N.HCLK_ROW[11]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B30	HCLK: mux N.LCLK[0] bit 5	HCLK: mux N.LCLK[0] bit 8	HCLK: mux N.LCLK[1] bit 8	HCLK: mux N.LCLK[1] bit 5	HCLK: mux N.LCLK[4] bit 5	HCLK: mux N.LCLK[4] bit 8	HCLK: mux N.LCLK[5] bit 8	HCLK: mux N.LCLK[5] bit 5	HCLK: buffer N.HCLK_BUF[10] ← N.HCLK_ROW[10]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B29	HCLK: mux N.LCLK[0] bit 3	HCLK: mux N.LCLK[0] bit 4	HCLK: mux N.LCLK[1] bit 4	HCLK: mux N.LCLK[1] bit 3	HCLK: mux N.LCLK[4] bit 3	HCLK: mux N.LCLK[4] bit 4	HCLK: mux N.LCLK[5] bit 4	HCLK: mux N.LCLK[5] bit 3	HCLK: buffer N.HCLK_BUF[9] ← N.HCLK_ROW[9]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B28	HCLK: mux N.LCLK[0] bit 1	HCLK: mux N.LCLK[0] bit 2	HCLK: mux N.LCLK[1] bit 2	HCLK: mux N.LCLK[1] bit 1	HCLK: mux N.LCLK[4] bit 1	HCLK: mux N.LCLK[4] bit 2	HCLK: mux N.LCLK[5] bit 2	HCLK: mux N.LCLK[5] bit 1	HCLK: buffer N.HCLK_BUF[8] ← N.HCLK_ROW[8]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B27	HCLK: mux N.LCLK[2] bit 7	HCLK: mux N.LCLK[0] bit 0	HCLK: mux N.LCLK[1] bit 0	HCLK: mux N.LCLK[3] bit 7	HCLK: mux N.LCLK[6] bit 7	HCLK: mux N.LCLK[4] bit 0	HCLK: mux N.LCLK[5] bit 0	HCLK: mux N.LCLK[7] bit 7	HCLK: buffer N.HCLK_BUF[7] ← N.HCLK_ROW[7]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B26	HCLK: mux N.LCLK[2] bit 8	HCLK: mux N.LCLK[2] bit 6	HCLK: mux N.LCLK[3] bit 6	HCLK: mux N.LCLK[3] bit 8	HCLK: mux N.LCLK[6] bit 8	HCLK: mux N.LCLK[6] bit 6	HCLK: mux N.LCLK[7] bit 6	HCLK: mux N.LCLK[7] bit 8	HCLK: buffer N.HCLK_BUF[6] ← N.HCLK_ROW[6]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B25	HCLK: mux N.LCLK[2] bit 4	HCLK: mux N.LCLK[2] bit 5	HCLK: mux N.LCLK[3] bit 5	HCLK: mux N.LCLK[3] bit 4	HCLK: mux N.LCLK[6] bit 4	HCLK: mux N.LCLK[6] bit 5	HCLK: mux N.LCLK[7] bit 5	HCLK: mux N.LCLK[7] bit 4	HCLK: buffer N.HCLK_BUF[5] ← N.HCLK_ROW[5]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B24	HCLK: mux N.LCLK[2] bit 2	HCLK: mux N.LCLK[2] bit 3	HCLK: mux N.LCLK[3] bit 3	HCLK: mux N.LCLK[3] bit 2	HCLK: mux N.LCLK[6] bit 2	HCLK: mux N.LCLK[6] bit 3	HCLK: mux N.LCLK[7] bit 3	HCLK: mux N.LCLK[7] bit 2	HCLK: buffer N.HCLK_BUF[4] ← N.HCLK_ROW[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B23	HCLK: mux N.LCLK[2] bit 0	HCLK: mux N.LCLK[2] bit 1	HCLK: mux N.LCLK[3] bit 1	HCLK: mux N.LCLK[3] bit 0	HCLK: mux N.LCLK[6] bit 0	HCLK: mux N.LCLK[6] bit 1	HCLK: mux N.LCLK[7] bit 1	HCLK: mux N.LCLK[7] bit 0	HCLK: buffer N.HCLK_BUF[3] ← N.HCLK_ROW[3]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B22	HCLK: mux S.LCLK[0] bit 6	HCLK: mux S.LCLK[0] bit 7	HCLK: mux S.LCLK[1] bit 7	HCLK: mux S.LCLK[1] bit 6	HCLK: mux S.LCLK[4] bit 6	HCLK: mux S.LCLK[4] bit 7	HCLK: mux S.LCLK[5] bit 7	HCLK: mux S.LCLK[5] bit 6	HCLK: buffer N.HCLK_BUF[2] ← N.HCLK_ROW[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B21	HCLK: mux S.LCLK[0] bit 5	HCLK: mux S.LCLK[0] bit 8	HCLK: mux S.LCLK[1] bit 8	HCLK: mux S.LCLK[1] bit 5	HCLK: mux S.LCLK[4] bit 5	HCLK: mux S.LCLK[4] bit 8	HCLK: mux S.LCLK[5] bit 8	HCLK: mux S.LCLK[5] bit 5	HCLK: buffer N.HCLK_BUF[1] ← N.HCLK_ROW[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B20	HCLK: mux S.LCLK[0] bit 3	HCLK: mux S.LCLK[0] bit 4	HCLK: mux S.LCLK[1] bit 4	HCLK: mux S.LCLK[1] bit 3	HCLK: mux S.LCLK[4] bit 3	HCLK: mux S.LCLK[4] bit 4	HCLK: mux S.LCLK[5] bit 4	HCLK: mux S.LCLK[5] bit 3	HCLK: buffer N.HCLK_BUF[0] ← N.HCLK_ROW[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B19	HCLK: mux S.LCLK[0] bit 1	HCLK: mux S.LCLK[0] bit 2	HCLK: mux S.LCLK[1] bit 2	HCLK: mux S.LCLK[1] bit 1	HCLK: mux S.LCLK[4] bit 1	HCLK: mux S.LCLK[4] bit 2	HCLK: mux S.LCLK[5] bit 2	HCLK: mux S.LCLK[5] bit 1	HCLK: buffer N.RCLK_BUF[5] ← N.RCLK_ROW[5]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B18	HCLK: mux S.LCLK[2] bit 7	HCLK: mux S.LCLK[0] bit 0	HCLK: mux S.LCLK[1] bit 0	HCLK: mux S.LCLK[3] bit 7	HCLK: mux S.LCLK[6] bit 7	HCLK: mux S.LCLK[4] bit 0	HCLK: mux S.LCLK[5] bit 0	HCLK: mux S.LCLK[7] bit 7	HCLK: buffer N.RCLK_BUF[4] ← N.RCLK_ROW[4]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B17	HCLK: mux S.LCLK[2] bit 8	HCLK: mux S.LCLK[2] bit 6	HCLK: mux S.LCLK[3] bit 6	HCLK: mux S.LCLK[3] bit 8	HCLK: mux S.LCLK[6] bit 8	HCLK: mux S.LCLK[6] bit 6	HCLK: mux S.LCLK[7] bit 6	HCLK: mux S.LCLK[7] bit 8	HCLK: buffer N.RCLK_BUF[3] ← N.RCLK_ROW[3]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B16	HCLK: mux S.LCLK[2] bit 4	HCLK: mux S.LCLK[2] bit 5	HCLK: mux S.LCLK[3] bit 5	HCLK: mux S.LCLK[3] bit 4	HCLK: mux S.LCLK[6] bit 4	HCLK: mux S.LCLK[6] bit 5	HCLK: mux S.LCLK[7] bit 5	HCLK: mux S.LCLK[7] bit 4	HCLK: buffer N.RCLK_BUF[2] ← N.RCLK_ROW[2]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B15	HCLK: mux S.LCLK[2] bit 2	HCLK: mux S.LCLK[2] bit 3	HCLK: mux S.LCLK[3] bit 3	HCLK: mux S.LCLK[3] bit 2	HCLK: mux S.LCLK[6] bit 2	HCLK: mux S.LCLK[6] bit 3	HCLK: mux S.LCLK[7] bit 3	HCLK: mux S.LCLK[7] bit 2	HCLK: buffer N.RCLK_BUF[1] ← N.RCLK_ROW[1]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B14	HCLK: mux S.LCLK[2] bit 0	HCLK: mux S.LCLK[2] bit 1	HCLK: mux S.LCLK[3] bit 1	HCLK: mux S.LCLK[3] bit 0	HCLK: mux S.LCLK[6] bit 0	HCLK: mux S.LCLK[6] bit 1	HCLK: mux S.LCLK[7] bit 1	HCLK: mux S.LCLK[7] bit 0	HCLK: buffer N.RCLK_BUF[0] ← N.RCLK_ROW[0]	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_DRP[0]: DRP_MASK_SYSMON	HCLK_DRP[0]: DRP_MASK_S	HCLK_DRP[0]: DRP_MASK_N	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

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Clock column buffers

Tile HCLK

Switchbox HCLK

Bels GLOBALSIG

Bels HCLK_DRP

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