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Clock management tile

TODO: describe this madness

Tile CMT

Cells: 56

Switchbox SPEC_INT

virtex6 CMT switchbox SPEC_INT programmable buffers
DestinationSourceBit
CELL[20].GCLK_CMT[0]CELL[20].GCLK[0]HCLK[26][29]
CELL[20].GCLK_CMT[1]CELL[20].GCLK[1]HCLK[32][22]
CELL[20].GCLK_CMT[2]CELL[20].GCLK[2]HCLK[26][28]
CELL[20].GCLK_CMT[3]CELL[20].GCLK[3]HCLK[32][23]
CELL[20].GCLK_CMT[4]CELL[20].GCLK[4]HCLK[26][27]
CELL[20].GCLK_CMT[5]CELL[20].GCLK[5]HCLK[32][24]
CELL[20].GCLK_CMT[6]CELL[20].GCLK[6]HCLK[26][26]
CELL[20].GCLK_CMT[7]CELL[20].GCLK[7]HCLK[32][25]
CELL[20].GCLK_CMT[8]CELL[20].GCLK[8]HCLK[26][25]
CELL[20].GCLK_CMT[9]CELL[20].GCLK[9]HCLK[32][26]
CELL[20].GCLK_CMT[10]CELL[20].GCLK[10]HCLK[26][24]
CELL[20].GCLK_CMT[11]CELL[20].GCLK[11]HCLK[32][27]
CELL[20].GCLK_CMT[12]CELL[20].GCLK[12]HCLK[26][23]
CELL[20].GCLK_CMT[13]CELL[20].GCLK[13]HCLK[32][28]
CELL[20].GCLK_CMT[14]CELL[20].GCLK[14]HCLK[26][22]
CELL[20].GCLK_CMT[15]CELL[20].GCLK[15]HCLK[32][29]
CELL[20].GCLK_CMT[16]CELL[20].GCLK[16]HCLK[26][14]
CELL[20].GCLK_CMT[17]CELL[20].GCLK[17]HCLK[32][21]
CELL[20].GCLK_CMT[18]CELL[20].GCLK[18]HCLK[26][15]
CELL[20].GCLK_CMT[19]CELL[20].GCLK[19]HCLK[32][20]
CELL[20].GCLK_CMT[20]CELL[20].GCLK[20]HCLK[26][16]
CELL[20].GCLK_CMT[21]CELL[20].GCLK[21]HCLK[32][19]
CELL[20].GCLK_CMT[22]CELL[20].GCLK[22]HCLK[26][17]
CELL[20].GCLK_CMT[23]CELL[20].GCLK[23]HCLK[32][18]
CELL[20].GCLK_CMT[24]CELL[20].GCLK[24]HCLK[26][18]
CELL[20].GCLK_CMT[25]CELL[20].GCLK[25]HCLK[32][17]
CELL[20].GCLK_CMT[26]CELL[20].GCLK[26]HCLK[26][19]
CELL[20].GCLK_CMT[27]CELL[20].GCLK[27]HCLK[32][16]
CELL[20].GCLK_CMT[28]CELL[20].GCLK[28]HCLK[26][20]
CELL[20].GCLK_CMT[29]CELL[20].GCLK[29]HCLK[32][15]
CELL[20].GCLK_CMT[30]CELL[20].GCLK[30]HCLK[26][21]
CELL[20].GCLK_CMT[31]CELL[20].GCLK[31]HCLK[32][14]
CELL[20].BUFH_INT_W[0]CELL[19].IMUX_CLK[0]HCLK[26][30]
CELL[20].BUFH_INT_W[1]CELL[19].IMUX_CLK[1]HCLK[26][31]
CELL[20].BUFH_INT_E[0]CELL[20].IMUX_CLK[0]HCLK[32][30]
CELL[20].BUFH_INT_E[1]CELL[20].IMUX_CLK[1]HCLK[32][31]
CELL[20].GCLK_TEST_IN[0]CELL[20].GCLK_CMT[0]MAIN[19][27][14]
CELL[20].GCLK_TEST_IN[1]CELL[20].GCLK_CMT[1]MAIN[19][28][14]
CELL[20].GCLK_TEST_IN[2]CELL[20].GCLK_CMT[2]MAIN[19][32][14]
CELL[20].GCLK_TEST_IN[3]CELL[20].GCLK_CMT[3]MAIN[19][31][14]
CELL[20].GCLK_TEST_IN[4]CELL[20].GCLK_CMT[4]MAIN[19][27][30]
CELL[20].GCLK_TEST_IN[5]CELL[20].GCLK_CMT[5]MAIN[19][28][30]
CELL[20].GCLK_TEST_IN[6]CELL[20].GCLK_CMT[6]MAIN[19][32][30]
CELL[20].GCLK_TEST_IN[7]CELL[20].GCLK_CMT[7]MAIN[19][31][30]
CELL[20].GCLK_TEST_IN[8]CELL[20].GCLK_CMT[8]MAIN[19][27][46]
CELL[20].GCLK_TEST_IN[9]CELL[20].GCLK_CMT[9]MAIN[19][28][46]
CELL[20].GCLK_TEST_IN[10]CELL[20].GCLK_CMT[10]MAIN[19][32][46]
CELL[20].GCLK_TEST_IN[11]CELL[20].GCLK_CMT[11]MAIN[19][31][46]
CELL[20].GCLK_TEST_IN[12]CELL[20].GCLK_CMT[12]MAIN[19][27][62]
CELL[20].GCLK_TEST_IN[13]CELL[20].GCLK_CMT[13]MAIN[19][28][62]
CELL[20].GCLK_TEST_IN[14]CELL[20].GCLK_CMT[14]MAIN[19][32][62]
CELL[20].GCLK_TEST_IN[15]CELL[20].GCLK_CMT[15]MAIN[19][31][62]
CELL[20].GCLK_TEST_IN[16]CELL[20].GCLK_CMT[16]MAIN[20][27][14]
CELL[20].GCLK_TEST_IN[17]CELL[20].GCLK_CMT[17]MAIN[20][28][14]
CELL[20].GCLK_TEST_IN[18]CELL[20].GCLK_CMT[18]MAIN[20][32][14]
CELL[20].GCLK_TEST_IN[19]CELL[20].GCLK_CMT[19]MAIN[20][31][14]
CELL[20].GCLK_TEST_IN[20]CELL[20].GCLK_CMT[20]MAIN[20][27][30]
CELL[20].GCLK_TEST_IN[21]CELL[20].GCLK_CMT[21]MAIN[20][28][30]
CELL[20].GCLK_TEST_IN[22]CELL[20].GCLK_CMT[22]MAIN[20][32][30]
CELL[20].GCLK_TEST_IN[23]CELL[20].GCLK_CMT[23]MAIN[20][31][30]
CELL[20].GCLK_TEST_IN[24]CELL[20].GCLK_CMT[24]MAIN[20][27][46]
CELL[20].GCLK_TEST_IN[25]CELL[20].GCLK_CMT[25]MAIN[20][28][46]
CELL[20].GCLK_TEST_IN[26]CELL[20].GCLK_CMT[26]MAIN[20][32][46]
CELL[20].GCLK_TEST_IN[27]CELL[20].GCLK_CMT[27]MAIN[20][31][46]
CELL[20].GCLK_TEST_IN[28]CELL[20].GCLK_CMT[28]MAIN[20][27][62]
CELL[20].GCLK_TEST_IN[29]CELL[20].GCLK_CMT[29]MAIN[20][28][62]
CELL[20].GCLK_TEST_IN[30]CELL[20].GCLK_CMT[30]MAIN[20][32][62]
CELL[20].GCLK_TEST_IN[31]CELL[20].GCLK_CMT[31]MAIN[20][31][62]
CELL[20].CCIO_CMT_W[0]IO_W[1].OUT_CLKPADHCLK[28][24]
CELL[20].CCIO_CMT_W[1]IO_W[3].OUT_CLKPADHCLK[28][25]
CELL[20].CCIO_CMT_W[2]IO_W[5].OUT_CLKPADHCLK[28][26]
CELL[20].CCIO_CMT_W[3]IO_W[7].OUT_CLKPADHCLK[28][27]
CELL[20].CCIO_CMT_E[0]IO_E[1].OUT_CLKPADHCLK[30][24]
CELL[20].CCIO_CMT_E[1]IO_E[3].OUT_CLKPADHCLK[30][25]
CELL[20].CCIO_CMT_E[2]IO_E[5].OUT_CLKPADHCLK[30][26]
CELL[20].CCIO_CMT_E[3]IO_E[7].OUT_CLKPADHCLK[30][27]
CELL[20].MGT_CMT_W[0]IO_W[4].MGT_ROW[0]HCLK[28][14]
CELL[20].MGT_CMT_W[1]IO_W[4].MGT_ROW[1]HCLK[28][15]
CELL[20].MGT_CMT_W[2]IO_W[4].MGT_ROW[2]HCLK[28][16]
CELL[20].MGT_CMT_W[3]IO_W[4].MGT_ROW[3]HCLK[28][17]
CELL[20].MGT_CMT_W[4]IO_W[4].MGT_ROW[4]HCLK[28][22]
CELL[20].MGT_CMT_W[5]IO_W[4].MGT_ROW[5]HCLK[28][23]
CELL[20].MGT_CMT_W[6]IO_W[4].MGT_ROW[6]HCLK[28][28]
CELL[20].MGT_CMT_W[7]IO_W[4].MGT_ROW[7]HCLK[28][29]
CELL[20].MGT_CMT_W[8]IO_W[4].MGT_ROW[8]HCLK[28][30]
CELL[20].MGT_CMT_W[9]IO_W[4].MGT_ROW[9]HCLK[28][31]
CELL[20].MGT_CMT_E[0]IO_E[4].MGT_ROW[0]HCLK[30][14]
CELL[20].MGT_CMT_E[1]IO_E[4].MGT_ROW[1]HCLK[30][15]
CELL[20].MGT_CMT_E[2]IO_E[4].MGT_ROW[2]HCLK[30][16]
CELL[20].MGT_CMT_E[3]IO_E[4].MGT_ROW[3]HCLK[30][17]
CELL[20].MGT_CMT_E[4]IO_E[4].MGT_ROW[4]HCLK[30][22]
CELL[20].MGT_CMT_E[5]IO_E[4].MGT_ROW[5]HCLK[30][23]
CELL[20].MGT_CMT_E[6]IO_E[4].MGT_ROW[6]HCLK[30][28]
CELL[20].MGT_CMT_E[7]IO_E[4].MGT_ROW[7]HCLK[30][29]
CELL[20].MGT_CMT_E[8]IO_E[4].MGT_ROW[8]HCLK[30][30]
CELL[20].MGT_CMT_E[9]IO_E[4].MGT_ROW[9]HCLK[30][31]
CELL[20].HCLK_CMT_W[0]IO_W[4].HCLK_ROW[0]HCLK[29][20]
CELL[20].HCLK_CMT_W[1]IO_W[4].HCLK_ROW[1]HCLK[29][21]
CELL[20].HCLK_CMT_W[2]IO_W[4].HCLK_ROW[2]HCLK[29][22]
CELL[20].HCLK_CMT_W[3]IO_W[4].HCLK_ROW[3]HCLK[29][23]
CELL[20].HCLK_CMT_W[4]IO_W[4].HCLK_ROW[4]HCLK[29][24]
CELL[20].HCLK_CMT_W[5]IO_W[4].HCLK_ROW[5]HCLK[29][25]
CELL[20].HCLK_CMT_W[6]IO_W[4].HCLK_ROW[6]HCLK[29][26]
CELL[20].HCLK_CMT_W[7]IO_W[4].HCLK_ROW[7]HCLK[29][27]
CELL[20].HCLK_CMT_W[8]IO_W[4].HCLK_ROW[8]HCLK[29][28]
CELL[20].HCLK_CMT_W[9]IO_W[4].HCLK_ROW[9]HCLK[29][29]
CELL[20].HCLK_CMT_W[10]IO_W[4].HCLK_ROW[10]HCLK[29][30]
CELL[20].HCLK_CMT_W[11]IO_W[4].HCLK_ROW[11]HCLK[29][31]
CELL[20].HCLK_CMT_E[0]IO_E[4].HCLK_ROW[0]HCLK[31][20]
CELL[20].HCLK_CMT_E[1]IO_E[4].HCLK_ROW[1]HCLK[31][21]
CELL[20].HCLK_CMT_E[2]IO_E[4].HCLK_ROW[2]HCLK[31][22]
CELL[20].HCLK_CMT_E[3]IO_E[4].HCLK_ROW[3]HCLK[31][23]
CELL[20].HCLK_CMT_E[4]IO_E[4].HCLK_ROW[4]HCLK[31][24]
CELL[20].HCLK_CMT_E[5]IO_E[4].HCLK_ROW[5]HCLK[31][25]
CELL[20].HCLK_CMT_E[6]IO_E[4].HCLK_ROW[6]HCLK[31][26]
CELL[20].HCLK_CMT_E[7]IO_E[4].HCLK_ROW[7]HCLK[31][27]
CELL[20].HCLK_CMT_E[8]IO_E[4].HCLK_ROW[8]HCLK[31][28]
CELL[20].HCLK_CMT_E[9]IO_E[4].HCLK_ROW[9]HCLK[31][29]
CELL[20].HCLK_CMT_E[10]IO_E[4].HCLK_ROW[10]HCLK[31][30]
CELL[20].HCLK_CMT_E[11]IO_E[4].HCLK_ROW[11]HCLK[31][31]
CELL[20].RCLK_CMT_W[0]IO_W[4].RCLK_ROW[0]HCLK[29][14]
CELL[20].RCLK_CMT_W[1]IO_W[4].RCLK_ROW[1]HCLK[29][15]
CELL[20].RCLK_CMT_W[2]IO_W[4].RCLK_ROW[2]HCLK[29][16]
CELL[20].RCLK_CMT_W[3]IO_W[4].RCLK_ROW[3]HCLK[29][17]
CELL[20].RCLK_CMT_W[4]IO_W[4].RCLK_ROW[4]HCLK[29][18]
CELL[20].RCLK_CMT_W[5]IO_W[4].RCLK_ROW[5]HCLK[29][19]
CELL[20].RCLK_CMT_E[0]IO_E[4].RCLK_ROW[0]HCLK[31][14]
CELL[20].RCLK_CMT_E[1]IO_E[4].RCLK_ROW[1]HCLK[31][15]
CELL[20].RCLK_CMT_E[2]IO_E[4].RCLK_ROW[2]HCLK[31][16]
CELL[20].RCLK_CMT_E[3]IO_E[4].RCLK_ROW[3]HCLK[31][17]
CELL[20].RCLK_CMT_E[4]IO_E[4].RCLK_ROW[4]HCLK[31][18]
CELL[20].RCLK_CMT_E[5]IO_E[4].RCLK_ROW[5]HCLK[31][19]
CELL[20].GIOB_CMT[0]CELL[20].GIOB[0]HCLK[28][18]
CELL[20].GIOB_CMT[1]CELL[20].GIOB[1]HCLK[30][18]
CELL[20].GIOB_CMT[2]CELL[20].GIOB[2]HCLK[28][19]
CELL[20].GIOB_CMT[3]CELL[20].GIOB[3]HCLK[30][19]
CELL[20].GIOB_CMT[4]CELL[20].GIOB[4]HCLK[28][20]
CELL[20].GIOB_CMT[5]CELL[20].GIOB[5]HCLK[30][20]
CELL[20].GIOB_CMT[6]CELL[20].GIOB[6]HCLK[28][21]
CELL[20].GIOB_CMT[7]CELL[20].GIOB[7]HCLK[30][21]
IO_W[4].PERF_ROW[0]CELL[20].OMUX_PLL_PERF_S[0]MAIN[17][26][54]
IO_W[4].PERF_ROW[0]CELL[20].OMUX_PLL_PERF_N[0]MAIN[22][26][9]
IO_W[4].PERF_ROW[1]CELL[20].OMUX_PLL_PERF_S[1]MAIN[17][26][52]
IO_W[4].PERF_ROW[1]CELL[20].OMUX_PLL_PERF_N[1]MAIN[22][26][11]
IO_W[4].PERF_ROW[2]CELL[20].OMUX_PLL_PERF_S[2]MAIN[17][26][50]
IO_W[4].PERF_ROW[2]CELL[20].OMUX_PLL_PERF_N[2]MAIN[22][26][13]
IO_W[4].PERF_ROW[3]CELL[20].OMUX_PLL_PERF_S[3]MAIN[17][26][48]
IO_W[4].PERF_ROW[3]CELL[20].OMUX_PLL_PERF_N[3]MAIN[22][26][15]
IO_W[4].PERF_ROW_OUTER[0]CELL[20].OMUX_PLL_PERF_S[1]MAIN[17][27][52]
IO_W[4].PERF_ROW_OUTER[0]CELL[20].OMUX_PLL_PERF_N[1]MAIN[22][27][11]
IO_W[4].PERF_ROW_OUTER[1]CELL[20].OMUX_PLL_PERF_S[0]MAIN[17][27][54]
IO_W[4].PERF_ROW_OUTER[1]CELL[20].OMUX_PLL_PERF_N[0]MAIN[22][27][9]
IO_W[4].PERF_ROW_OUTER[2]CELL[20].OMUX_PLL_PERF_S[3]MAIN[17][27][48]
IO_W[4].PERF_ROW_OUTER[2]CELL[20].OMUX_PLL_PERF_N[3]MAIN[22][27][15]
IO_W[4].PERF_ROW_OUTER[3]CELL[20].OMUX_PLL_PERF_S[2]MAIN[17][27][50]
IO_W[4].PERF_ROW_OUTER[3]CELL[20].OMUX_PLL_PERF_N[2]MAIN[22][27][13]
IO_E[4].PERF_ROW[0]CELL[20].OMUX_PLL_PERF_S[0]MAIN[17][27][55]
IO_E[4].PERF_ROW[0]CELL[20].OMUX_PLL_PERF_N[0]MAIN[22][27][8]
IO_E[4].PERF_ROW[1]CELL[20].OMUX_PLL_PERF_S[1]MAIN[17][27][53]
IO_E[4].PERF_ROW[1]CELL[20].OMUX_PLL_PERF_N[1]MAIN[22][27][10]
IO_E[4].PERF_ROW[2]CELL[20].OMUX_PLL_PERF_S[2]MAIN[17][27][51]
IO_E[4].PERF_ROW[2]CELL[20].OMUX_PLL_PERF_N[2]MAIN[22][27][12]
IO_E[4].PERF_ROW[3]CELL[20].OMUX_PLL_PERF_S[3]MAIN[17][27][49]
IO_E[4].PERF_ROW[3]CELL[20].OMUX_PLL_PERF_N[3]MAIN[22][27][14]
IO_E[4].PERF_ROW_OUTER[0]CELL[20].OMUX_PLL_PERF_S[1]MAIN[17][26][53]
IO_E[4].PERF_ROW_OUTER[0]CELL[20].OMUX_PLL_PERF_N[1]MAIN[22][26][10]
IO_E[4].PERF_ROW_OUTER[1]CELL[20].OMUX_PLL_PERF_S[0]MAIN[17][26][55]
IO_E[4].PERF_ROW_OUTER[1]CELL[20].OMUX_PLL_PERF_N[0]MAIN[22][26][8]
IO_E[4].PERF_ROW_OUTER[2]CELL[20].OMUX_PLL_PERF_S[3]MAIN[17][26][49]
IO_E[4].PERF_ROW_OUTER[2]CELL[20].OMUX_PLL_PERF_N[3]MAIN[22][26][14]
IO_E[4].PERF_ROW_OUTER[3]CELL[20].OMUX_PLL_PERF_S[2]MAIN[17][26][51]
IO_E[4].PERF_ROW_OUTER[3]CELL[20].OMUX_PLL_PERF_N[2]MAIN[22][26][12]
virtex6 CMT switchbox SPEC_INT programmable inverters
DestinationSourceBit
CELL[20].GCLK_TEST[0]CELL[20].GCLK_TEST_IN[0]MAIN[19][27][0]
CELL[20].GCLK_TEST[1]CELL[20].GCLK_TEST_IN[1]MAIN[19][28][0]
CELL[20].GCLK_TEST[2]CELL[20].GCLK_TEST_IN[2]MAIN[19][32][0]
CELL[20].GCLK_TEST[3]CELL[20].GCLK_TEST_IN[3]MAIN[19][31][0]
CELL[20].GCLK_TEST[4]CELL[20].GCLK_TEST_IN[4]MAIN[19][27][16]
CELL[20].GCLK_TEST[5]CELL[20].GCLK_TEST_IN[5]MAIN[19][28][16]
CELL[20].GCLK_TEST[6]CELL[20].GCLK_TEST_IN[6]MAIN[19][32][16]
CELL[20].GCLK_TEST[7]CELL[20].GCLK_TEST_IN[7]MAIN[19][31][16]
CELL[20].GCLK_TEST[8]CELL[20].GCLK_TEST_IN[8]MAIN[19][27][32]
CELL[20].GCLK_TEST[9]CELL[20].GCLK_TEST_IN[9]MAIN[19][28][32]
CELL[20].GCLK_TEST[10]CELL[20].GCLK_TEST_IN[10]MAIN[19][32][32]
CELL[20].GCLK_TEST[11]CELL[20].GCLK_TEST_IN[11]MAIN[19][31][32]
CELL[20].GCLK_TEST[12]CELL[20].GCLK_TEST_IN[12]MAIN[19][27][48]
CELL[20].GCLK_TEST[13]CELL[20].GCLK_TEST_IN[13]MAIN[19][28][48]
CELL[20].GCLK_TEST[14]CELL[20].GCLK_TEST_IN[14]MAIN[19][32][48]
CELL[20].GCLK_TEST[15]CELL[20].GCLK_TEST_IN[15]MAIN[19][31][48]
CELL[20].GCLK_TEST[16]CELL[20].GCLK_TEST_IN[16]MAIN[20][27][0]
CELL[20].GCLK_TEST[17]CELL[20].GCLK_TEST_IN[17]MAIN[20][28][0]
CELL[20].GCLK_TEST[18]CELL[20].GCLK_TEST_IN[18]MAIN[20][32][0]
CELL[20].GCLK_TEST[19]CELL[20].GCLK_TEST_IN[19]MAIN[20][31][0]
CELL[20].GCLK_TEST[20]CELL[20].GCLK_TEST_IN[20]MAIN[20][27][16]
CELL[20].GCLK_TEST[21]CELL[20].GCLK_TEST_IN[21]MAIN[20][28][16]
CELL[20].GCLK_TEST[22]CELL[20].GCLK_TEST_IN[22]MAIN[20][32][16]
CELL[20].GCLK_TEST[23]CELL[20].GCLK_TEST_IN[23]MAIN[20][31][16]
CELL[20].GCLK_TEST[24]CELL[20].GCLK_TEST_IN[24]MAIN[20][27][32]
CELL[20].GCLK_TEST[25]CELL[20].GCLK_TEST_IN[25]MAIN[20][28][32]
CELL[20].GCLK_TEST[26]CELL[20].GCLK_TEST_IN[26]MAIN[20][32][32]
CELL[20].GCLK_TEST[27]CELL[20].GCLK_TEST_IN[27]MAIN[20][31][32]
CELL[20].GCLK_TEST[28]CELL[20].GCLK_TEST_IN[28]MAIN[20][27][48]
CELL[20].GCLK_TEST[29]CELL[20].GCLK_TEST_IN[29]MAIN[20][28][48]
CELL[20].GCLK_TEST[30]CELL[20].GCLK_TEST_IN[30]MAIN[20][32][48]
CELL[20].GCLK_TEST[31]CELL[20].GCLK_TEST_IN[31]MAIN[20][31][48]
CELL[20].BUFH_TEST_WCELL[20].BUFH_TEST_W_INMAIN[19][30][48]
CELL[20].BUFH_TEST_ECELL[20].BUFH_TEST_E_INMAIN[20][30][0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[0]
BitsDestination
MAIN[19][26][7]MAIN[19][26][5]MAIN[19][26][3]MAIN[19][26][4]MAIN[19][27][4]MAIN[19][27][5]MAIN[19][27][7]MAIN[19][27][6]MAIN[19][26][6]MAIN[19][27][8]MAIN[19][26][8]MAIN[19][26][10]MAIN[19][27][11]MAIN[19][26][12]MAIN[19][27][13]MAIN[19][26][14]MAIN[19][27][15]MAIN[19][26][2]CELL[20].IMUX_BUFG_O[0]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[0]
000000001000000010CELL[20].GCLK_TEST[0]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[1]
BitsDestination
MAIN[19][29][7]MAIN[19][29][5]MAIN[19][29][3]MAIN[19][29][4]MAIN[19][28][4]MAIN[19][28][5]MAIN[19][28][7]MAIN[19][28][6]MAIN[19][29][6]MAIN[19][28][8]MAIN[19][29][8]MAIN[19][29][10]MAIN[19][28][11]MAIN[19][29][12]MAIN[19][28][13]MAIN[19][28][15]MAIN[19][29][14]MAIN[19][27][3]CELL[20].IMUX_BUFG_O[1]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[1]
000000001000000010CELL[20].GCLK_TEST[1]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[2]
BitsDestination
MAIN[19][33][7]MAIN[19][33][5]MAIN[19][33][3]MAIN[19][33][4]MAIN[19][32][4]MAIN[19][32][5]MAIN[19][32][7]MAIN[19][32][6]MAIN[19][33][6]MAIN[19][32][8]MAIN[19][33][8]MAIN[19][33][10]MAIN[19][32][11]MAIN[19][33][12]MAIN[19][32][13]MAIN[19][32][15]MAIN[19][33][14]MAIN[19][31][3]CELL[20].IMUX_BUFG_O[2]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[2]
000000001000000010CELL[20].GCLK_TEST[2]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[3]
BitsDestination
MAIN[19][30][7]MAIN[19][30][5]MAIN[19][30][3]MAIN[19][30][4]MAIN[19][31][4]MAIN[19][31][5]MAIN[19][31][7]MAIN[19][31][6]MAIN[19][30][6]MAIN[19][31][8]MAIN[19][30][8]MAIN[19][30][10]MAIN[19][31][11]MAIN[19][30][12]MAIN[19][31][13]MAIN[19][30][14]MAIN[19][31][15]MAIN[19][30][2]CELL[20].IMUX_BUFG_O[3]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[3]
000000001000000010CELL[20].GCLK_TEST[3]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[4]
BitsDestination
MAIN[19][26][23]MAIN[19][26][21]MAIN[19][26][19]MAIN[19][26][20]MAIN[19][27][20]MAIN[19][27][21]MAIN[19][27][23]MAIN[19][27][22]MAIN[19][26][22]MAIN[19][27][24]MAIN[19][26][24]MAIN[19][26][26]MAIN[19][27][27]MAIN[19][26][28]MAIN[19][27][29]MAIN[19][26][30]MAIN[19][27][31]MAIN[19][26][18]CELL[20].IMUX_BUFG_O[4]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[4]
000000001000000010CELL[20].GCLK_TEST[4]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[5]
BitsDestination
MAIN[19][29][23]MAIN[19][29][21]MAIN[19][29][19]MAIN[19][29][20]MAIN[19][28][20]MAIN[19][28][21]MAIN[19][28][23]MAIN[19][28][22]MAIN[19][29][22]MAIN[19][28][24]MAIN[19][29][24]MAIN[19][29][26]MAIN[19][28][27]MAIN[19][29][28]MAIN[19][28][29]MAIN[19][28][31]MAIN[19][29][30]MAIN[19][27][19]CELL[20].IMUX_BUFG_O[5]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[5]
000000001000000010CELL[20].GCLK_TEST[5]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[6]
BitsDestination
MAIN[19][33][23]MAIN[19][33][21]MAIN[19][33][19]MAIN[19][33][20]MAIN[19][32][20]MAIN[19][32][21]MAIN[19][32][23]MAIN[19][32][22]MAIN[19][33][22]MAIN[19][32][24]MAIN[19][33][24]MAIN[19][33][26]MAIN[19][32][27]MAIN[19][33][28]MAIN[19][32][29]MAIN[19][32][31]MAIN[19][33][30]MAIN[19][31][19]CELL[20].IMUX_BUFG_O[6]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[6]
000000001000000010CELL[20].GCLK_TEST[6]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[7]
BitsDestination
MAIN[19][30][23]MAIN[19][30][21]MAIN[19][30][19]MAIN[19][30][20]MAIN[19][31][20]MAIN[19][31][21]MAIN[19][31][23]MAIN[19][31][22]MAIN[19][30][22]MAIN[19][31][24]MAIN[19][30][24]MAIN[19][30][26]MAIN[19][31][27]MAIN[19][30][28]MAIN[19][31][29]MAIN[19][30][30]MAIN[19][31][31]MAIN[19][30][18]CELL[20].IMUX_BUFG_O[7]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[7]
000000001000000010CELL[20].GCLK_TEST[7]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[8]
BitsDestination
MAIN[19][26][39]MAIN[19][26][37]MAIN[19][26][35]MAIN[19][26][36]MAIN[19][27][36]MAIN[19][27][37]MAIN[19][27][39]MAIN[19][27][38]MAIN[19][26][38]MAIN[19][27][40]MAIN[19][26][40]MAIN[19][26][42]MAIN[19][27][43]MAIN[19][26][44]MAIN[19][27][45]MAIN[19][26][46]MAIN[19][27][47]MAIN[19][26][34]CELL[20].IMUX_BUFG_O[8]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[8]
000000001000000010CELL[20].GCLK_TEST[8]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[9]
BitsDestination
MAIN[19][29][39]MAIN[19][29][37]MAIN[19][29][35]MAIN[19][29][36]MAIN[19][28][36]MAIN[19][28][37]MAIN[19][28][39]MAIN[19][28][38]MAIN[19][29][38]MAIN[19][28][40]MAIN[19][29][40]MAIN[19][29][42]MAIN[19][28][43]MAIN[19][29][44]MAIN[19][28][45]MAIN[19][28][47]MAIN[19][29][46]MAIN[19][27][35]CELL[20].IMUX_BUFG_O[9]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[9]
000000001000000010CELL[20].GCLK_TEST[9]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[10]
BitsDestination
MAIN[19][33][39]MAIN[19][33][37]MAIN[19][33][35]MAIN[19][33][36]MAIN[19][32][36]MAIN[19][32][37]MAIN[19][32][39]MAIN[19][32][38]MAIN[19][33][38]MAIN[19][32][40]MAIN[19][33][40]MAIN[19][33][42]MAIN[19][32][43]MAIN[19][33][44]MAIN[19][32][45]MAIN[19][32][47]MAIN[19][33][46]MAIN[19][31][35]CELL[20].IMUX_BUFG_O[10]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[10]
000000001000000010CELL[20].GCLK_TEST[10]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[11]
BitsDestination
MAIN[19][30][39]MAIN[19][30][37]MAIN[19][30][35]MAIN[19][30][36]MAIN[19][31][36]MAIN[19][31][37]MAIN[19][31][39]MAIN[19][31][38]MAIN[19][30][38]MAIN[19][31][40]MAIN[19][30][40]MAIN[19][30][42]MAIN[19][31][43]MAIN[19][30][44]MAIN[19][31][45]MAIN[19][30][46]MAIN[19][31][47]MAIN[19][30][34]CELL[20].IMUX_BUFG_O[11]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[11]
000000001000000010CELL[20].GCLK_TEST[11]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[12]
BitsDestination
MAIN[19][26][55]MAIN[19][26][53]MAIN[19][26][51]MAIN[19][26][52]MAIN[19][27][52]MAIN[19][27][53]MAIN[19][27][55]MAIN[19][27][54]MAIN[19][26][54]MAIN[19][27][56]MAIN[19][26][56]MAIN[19][26][58]MAIN[19][27][59]MAIN[19][26][60]MAIN[19][27][61]MAIN[19][26][62]MAIN[19][27][63]MAIN[19][26][50]CELL[20].IMUX_BUFG_O[12]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[12]
000000001000000010CELL[20].GCLK_TEST[12]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[13]
BitsDestination
MAIN[19][29][55]MAIN[19][29][53]MAIN[19][29][51]MAIN[19][29][52]MAIN[19][28][52]MAIN[19][28][53]MAIN[19][28][55]MAIN[19][28][54]MAIN[19][29][54]MAIN[19][28][56]MAIN[19][29][56]MAIN[19][29][58]MAIN[19][28][59]MAIN[19][29][60]MAIN[19][28][61]MAIN[19][28][63]MAIN[19][29][62]MAIN[19][27][51]CELL[20].IMUX_BUFG_O[13]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[13]
000000001000000010CELL[20].GCLK_TEST[13]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[14]
BitsDestination
MAIN[19][33][55]MAIN[19][33][53]MAIN[19][33][51]MAIN[19][33][52]MAIN[19][32][52]MAIN[19][32][53]MAIN[19][32][55]MAIN[19][32][54]MAIN[19][33][54]MAIN[19][32][56]MAIN[19][33][56]MAIN[19][33][58]MAIN[19][32][59]MAIN[19][33][60]MAIN[19][32][61]MAIN[19][32][63]MAIN[19][33][62]MAIN[19][31][51]CELL[20].IMUX_BUFG_O[14]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[14]
000000001000000010CELL[20].GCLK_TEST[14]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[15]
BitsDestination
MAIN[19][30][55]MAIN[19][30][53]MAIN[19][30][51]MAIN[19][30][52]MAIN[19][31][52]MAIN[19][31][53]MAIN[19][31][55]MAIN[19][31][54]MAIN[19][30][54]MAIN[19][31][56]MAIN[19][30][56]MAIN[19][30][58]MAIN[19][31][59]MAIN[19][30][60]MAIN[19][31][61]MAIN[19][30][62]MAIN[19][31][63]MAIN[19][30][50]CELL[20].IMUX_BUFG_O[15]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[15]
000000001000000010CELL[20].GCLK_TEST[15]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[16]
BitsDestination
MAIN[20][26][7]MAIN[20][26][5]MAIN[20][26][3]MAIN[20][26][4]MAIN[20][27][4]MAIN[20][27][5]MAIN[20][27][7]MAIN[20][27][6]MAIN[20][26][6]MAIN[20][27][8]MAIN[20][26][8]MAIN[20][26][10]MAIN[20][27][11]MAIN[20][26][12]MAIN[20][27][13]MAIN[20][26][14]MAIN[20][27][15]MAIN[20][26][2]CELL[20].IMUX_BUFG_O[16]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[16]
000000001000000010CELL[20].GCLK_TEST[16]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[17]
BitsDestination
MAIN[20][29][7]MAIN[20][29][5]MAIN[20][29][3]MAIN[20][29][4]MAIN[20][28][4]MAIN[20][28][5]MAIN[20][28][7]MAIN[20][28][6]MAIN[20][29][6]MAIN[20][28][8]MAIN[20][29][8]MAIN[20][29][10]MAIN[20][28][11]MAIN[20][29][12]MAIN[20][28][13]MAIN[20][28][15]MAIN[20][29][14]MAIN[20][27][3]CELL[20].IMUX_BUFG_O[17]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[17]
000000001000000010CELL[20].GCLK_TEST[17]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[18]
BitsDestination
MAIN[20][33][7]MAIN[20][33][5]MAIN[20][33][3]MAIN[20][33][4]MAIN[20][32][4]MAIN[20][32][5]MAIN[20][32][7]MAIN[20][32][6]MAIN[20][33][6]MAIN[20][32][8]MAIN[20][33][8]MAIN[20][33][10]MAIN[20][32][11]MAIN[20][33][12]MAIN[20][32][13]MAIN[20][32][15]MAIN[20][33][14]MAIN[20][31][3]CELL[20].IMUX_BUFG_O[18]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[18]
000000001000000010CELL[20].GCLK_TEST[18]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[19]
BitsDestination
MAIN[20][30][7]MAIN[20][30][5]MAIN[20][30][3]MAIN[20][30][4]MAIN[20][31][4]MAIN[20][31][5]MAIN[20][31][7]MAIN[20][31][6]MAIN[20][30][6]MAIN[20][31][8]MAIN[20][30][8]MAIN[20][30][10]MAIN[20][31][11]MAIN[20][30][12]MAIN[20][31][13]MAIN[20][30][14]MAIN[20][31][15]MAIN[20][30][2]CELL[20].IMUX_BUFG_O[19]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[19]
000000001000000010CELL[20].GCLK_TEST[19]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[20]
BitsDestination
MAIN[20][26][23]MAIN[20][26][21]MAIN[20][26][19]MAIN[20][26][20]MAIN[20][27][20]MAIN[20][27][21]MAIN[20][27][23]MAIN[20][27][22]MAIN[20][26][22]MAIN[20][27][24]MAIN[20][26][24]MAIN[20][26][26]MAIN[20][27][27]MAIN[20][26][28]MAIN[20][27][29]MAIN[20][26][30]MAIN[20][27][31]MAIN[20][26][18]CELL[20].IMUX_BUFG_O[20]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[20]
000000001000000010CELL[20].GCLK_TEST[20]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[21]
BitsDestination
MAIN[20][29][23]MAIN[20][29][21]MAIN[20][29][19]MAIN[20][29][20]MAIN[20][28][20]MAIN[20][28][21]MAIN[20][28][23]MAIN[20][28][22]MAIN[20][29][22]MAIN[20][28][24]MAIN[20][29][24]MAIN[20][29][26]MAIN[20][28][27]MAIN[20][29][28]MAIN[20][28][29]MAIN[20][28][31]MAIN[20][29][30]MAIN[20][27][19]CELL[20].IMUX_BUFG_O[21]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[21]
000000001000000010CELL[20].GCLK_TEST[21]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[22]
BitsDestination
MAIN[20][33][23]MAIN[20][33][21]MAIN[20][33][19]MAIN[20][33][20]MAIN[20][32][20]MAIN[20][32][21]MAIN[20][32][23]MAIN[20][32][22]MAIN[20][33][22]MAIN[20][32][24]MAIN[20][33][24]MAIN[20][33][26]MAIN[20][32][27]MAIN[20][33][28]MAIN[20][32][29]MAIN[20][32][31]MAIN[20][33][30]MAIN[20][31][19]CELL[20].IMUX_BUFG_O[22]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[22]
000000001000000010CELL[20].GCLK_TEST[22]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[23]
BitsDestination
MAIN[20][30][23]MAIN[20][30][21]MAIN[20][30][19]MAIN[20][30][20]MAIN[20][31][20]MAIN[20][31][21]MAIN[20][31][23]MAIN[20][31][22]MAIN[20][30][22]MAIN[20][31][24]MAIN[20][30][24]MAIN[20][30][26]MAIN[20][31][27]MAIN[20][30][28]MAIN[20][31][29]MAIN[20][30][30]MAIN[20][31][31]MAIN[20][30][18]CELL[20].IMUX_BUFG_O[23]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[23]
000000001000000010CELL[20].GCLK_TEST[23]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[24]
BitsDestination
MAIN[20][26][39]MAIN[20][26][37]MAIN[20][26][35]MAIN[20][26][36]MAIN[20][27][36]MAIN[20][27][37]MAIN[20][27][39]MAIN[20][27][38]MAIN[20][26][38]MAIN[20][27][40]MAIN[20][26][40]MAIN[20][26][42]MAIN[20][27][43]MAIN[20][26][44]MAIN[20][27][45]MAIN[20][26][46]MAIN[20][27][47]MAIN[20][26][34]CELL[20].IMUX_BUFG_O[24]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[24]
000000001000000010CELL[20].GCLK_TEST[24]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[25]
BitsDestination
MAIN[20][29][39]MAIN[20][29][37]MAIN[20][29][35]MAIN[20][29][36]MAIN[20][28][36]MAIN[20][28][37]MAIN[20][28][39]MAIN[20][28][38]MAIN[20][29][38]MAIN[20][28][40]MAIN[20][29][40]MAIN[20][29][42]MAIN[20][28][43]MAIN[20][29][44]MAIN[20][28][45]MAIN[20][28][47]MAIN[20][29][46]MAIN[20][27][35]CELL[20].IMUX_BUFG_O[25]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[25]
000000001000000010CELL[20].GCLK_TEST[25]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[26]
BitsDestination
MAIN[20][33][39]MAIN[20][33][37]MAIN[20][33][35]MAIN[20][33][36]MAIN[20][32][36]MAIN[20][32][37]MAIN[20][32][39]MAIN[20][32][38]MAIN[20][33][38]MAIN[20][32][40]MAIN[20][33][40]MAIN[20][33][42]MAIN[20][32][43]MAIN[20][33][44]MAIN[20][32][45]MAIN[20][32][47]MAIN[20][33][46]MAIN[20][31][35]CELL[20].IMUX_BUFG_O[26]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[26]
000000001000000010CELL[20].GCLK_TEST[26]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[27]
BitsDestination
MAIN[20][30][39]MAIN[20][30][37]MAIN[20][30][35]MAIN[20][30][36]MAIN[20][31][36]MAIN[20][31][37]MAIN[20][31][39]MAIN[20][31][38]MAIN[20][30][38]MAIN[20][31][40]MAIN[20][30][40]MAIN[20][30][42]MAIN[20][31][43]MAIN[20][30][44]MAIN[20][31][45]MAIN[20][30][46]MAIN[20][31][47]MAIN[20][30][34]CELL[20].IMUX_BUFG_O[27]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[27]
000000001000000010CELL[20].GCLK_TEST[27]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[28]
BitsDestination
MAIN[20][26][55]MAIN[20][26][53]MAIN[20][26][51]MAIN[20][26][52]MAIN[20][27][52]MAIN[20][27][53]MAIN[20][27][55]MAIN[20][27][54]MAIN[20][26][54]MAIN[20][27][56]MAIN[20][26][56]MAIN[20][26][58]MAIN[20][27][59]MAIN[20][26][60]MAIN[20][27][61]MAIN[20][26][62]MAIN[20][27][63]MAIN[20][26][50]CELL[20].IMUX_BUFG_O[28]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[28]
000000001000000010CELL[20].GCLK_TEST[28]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[29]
BitsDestination
MAIN[20][29][55]MAIN[20][29][53]MAIN[20][29][51]MAIN[20][29][52]MAIN[20][28][52]MAIN[20][28][53]MAIN[20][28][55]MAIN[20][28][54]MAIN[20][29][54]MAIN[20][28][56]MAIN[20][29][56]MAIN[20][29][58]MAIN[20][28][59]MAIN[20][29][60]MAIN[20][28][61]MAIN[20][28][63]MAIN[20][29][62]MAIN[20][27][51]CELL[20].IMUX_BUFG_O[29]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[29]
000000001000000010CELL[20].GCLK_TEST[29]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[30]
BitsDestination
MAIN[20][33][55]MAIN[20][33][53]MAIN[20][33][51]MAIN[20][33][52]MAIN[20][32][52]MAIN[20][32][53]MAIN[20][32][55]MAIN[20][32][54]MAIN[20][33][54]MAIN[20][32][56]MAIN[20][33][56]MAIN[20][33][58]MAIN[20][32][59]MAIN[20][33][60]MAIN[20][32][61]MAIN[20][32][63]MAIN[20][33][62]MAIN[20][31][51]CELL[20].IMUX_BUFG_O[30]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[30]
000000001000000010CELL[20].GCLK_TEST[30]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_E
000000010000000100CELL[20].BUFH_TEST_W
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[1]
000000100000000100CELL[20].CCIO_CMT_W[0]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[1]
000001000000000100CELL[20].MGT_CMT_W[0]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[9]
000010000000000100CELL[20].MGT_CMT_W[8]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[1]
000100000000000100CELL[20].MGT_CMT_E[0]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[9]
001000000000000100CELL[20].MGT_CMT_E[8]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[1]
010000000000000100CELL[20].OUT_PLL_S[0]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[1]
100000000000000100CELL[20].OUT_PLL_N[0]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFG_O[31]
BitsDestination
MAIN[20][30][55]MAIN[20][30][53]MAIN[20][30][51]MAIN[20][30][52]MAIN[20][31][52]MAIN[20][31][53]MAIN[20][31][55]MAIN[20][31][54]MAIN[20][30][54]MAIN[20][31][56]MAIN[20][30][56]MAIN[20][30][58]MAIN[20][31][59]MAIN[20][30][60]MAIN[20][31][61]MAIN[20][30][62]MAIN[20][31][63]MAIN[20][30][50]CELL[20].IMUX_BUFG_O[31]
Source
000000000000000000off
000000000000000001CELL[20].IMUX_BUFG_I[31]
000000001000000010CELL[20].GCLK_TEST[31]
000000001000001000CELL[20].OUT_PLL_N[8]
000000001000010000CELL[20].OUT_PLL_N[9]
000000001000100000CELL[20].OUT_PLL_N[10]
000000001001000000CELL[20].OUT_PLL_N[11]
000000001010000000CELL[20].OUT_PLL_N[12]
000000001100000000CELL[20].OUT_PLL_N[13]
000000010000000010CELL[20].BUFH_TEST_W
000000010000000100CELL[20].BUFH_TEST_E
000000010000001000CELL[20].OUT_PLL_S[8]
000000010000010000CELL[20].OUT_PLL_S[9]
000000010000100000CELL[20].OUT_PLL_S[10]
000000010001000000CELL[20].OUT_PLL_S[11]
000000010010000000CELL[20].OUT_PLL_S[12]
000000010100000000CELL[20].OUT_PLL_S[13]
000000100000000010CELL[20].CCIO_CMT_W[0]
000000100000000100CELL[20].CCIO_CMT_W[1]
000000100000001000CELL[20].CCIO_CMT_W[2]
000000100000010000CELL[20].CCIO_CMT_W[3]
000000100000100000CELL[20].CCIO_CMT_E[0]
000000100001000000CELL[20].CCIO_CMT_E[1]
000000100010000000CELL[20].CCIO_CMT_E[2]
000000100100000000CELL[20].CCIO_CMT_E[3]
000001000000000010CELL[20].MGT_CMT_W[0]
000001000000000100CELL[20].MGT_CMT_W[1]
000001000000001000CELL[20].MGT_CMT_W[2]
000001000000010000CELL[20].MGT_CMT_W[3]
000001000000100000CELL[20].MGT_CMT_W[4]
000001000001000000CELL[20].MGT_CMT_W[5]
000001000010000000CELL[20].MGT_CMT_W[6]
000001000100000000CELL[20].MGT_CMT_W[7]
000010000000000010CELL[20].MGT_CMT_W[8]
000010000000000100CELL[20].MGT_CMT_W[9]
000010000000001000CELL[20].RCLK_CMT_W[0]
000010000000010000CELL[20].RCLK_CMT_W[1]
000010000000100000CELL[20].RCLK_CMT_W[2]
000010000001000000CELL[20].RCLK_CMT_W[3]
000010000010000000CELL[20].RCLK_CMT_W[4]
000010000100000000CELL[20].RCLK_CMT_W[5]
000100000000000010CELL[20].MGT_CMT_E[0]
000100000000000100CELL[20].MGT_CMT_E[1]
000100000000001000CELL[20].MGT_CMT_E[2]
000100000000010000CELL[20].MGT_CMT_E[3]
000100000000100000CELL[20].MGT_CMT_E[4]
000100000001000000CELL[20].MGT_CMT_E[5]
000100000010000000CELL[20].MGT_CMT_E[6]
000100000100000000CELL[20].MGT_CMT_E[7]
001000000000000010CELL[20].MGT_CMT_E[8]
001000000000000100CELL[20].MGT_CMT_E[9]
001000000000001000CELL[20].RCLK_CMT_E[0]
001000000000010000CELL[20].RCLK_CMT_E[1]
001000000000100000CELL[20].RCLK_CMT_E[2]
001000000001000000CELL[20].RCLK_CMT_E[3]
001000000010000000CELL[20].RCLK_CMT_E[4]
001000000100000000CELL[20].RCLK_CMT_E[5]
010000000000000010CELL[20].OUT_PLL_S[0]
010000000000000100CELL[20].OUT_PLL_S[1]
010000000000001000CELL[20].OUT_PLL_S[2]
010000000000010000CELL[20].OUT_PLL_S[3]
010000000000100000CELL[20].OUT_PLL_S[4]
010000000001000000CELL[20].OUT_PLL_S[5]
010000000010000000CELL[20].OUT_PLL_S[6]
010000000100000000CELL[20].OUT_PLL_S[7]
100000000000000010CELL[20].OUT_PLL_N[0]
100000000000000100CELL[20].OUT_PLL_N[1]
100000000000001000CELL[20].OUT_PLL_N[2]
100000000000010000CELL[20].OUT_PLL_N[3]
100000000000100000CELL[20].OUT_PLL_N[4]
100000000001000000CELL[20].OUT_PLL_N[5]
100000000010000000CELL[20].OUT_PLL_N[6]
100000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes BUFH_TEST_W_IN
BitsDestination
MAIN[19][28][49]MAIN[19][28][50]MAIN[19][29][49]MAIN[19][28][57]MAIN[19][29][57]MAIN[19][28][58]MAIN[19][29][59]MAIN[19][28][60]MAIN[19][29][61]CELL[20].BUFH_TEST_W_IN
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes BUFH_TEST_E_IN
BitsDestination
MAIN[20][28][1]MAIN[20][28][2]MAIN[20][29][1]MAIN[20][28][9]MAIN[20][29][9]MAIN[20][28][10]MAIN[20][29][11]MAIN[20][28][12]MAIN[20][29][13]CELL[20].BUFH_TEST_E_IN
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[0]
BitsDestination
MAIN[18][27][24]MAIN[18][26][24]MAIN[18][26][26]MAIN[18][27][27]MAIN[18][26][28]MAIN[18][27][29]MAIN[18][26][30]MAIN[18][27][31]MAIN[18][26][23]MAIN[18][26][21]MAIN[18][27][23]MAIN[18][27][22]MAIN[18][26][22]MAIN[18][26][19]MAIN[18][26][20]MAIN[18][27][20]MAIN[18][27][21]CELL[20].IMUX_BUFHCE_W[0]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[1]
BitsDestination
MAIN[18][28][24]MAIN[18][29][24]MAIN[18][29][26]MAIN[18][28][27]MAIN[18][29][28]MAIN[18][28][29]MAIN[18][29][30]MAIN[18][28][31]MAIN[18][29][23]MAIN[18][29][21]MAIN[18][28][23]MAIN[18][28][22]MAIN[18][29][22]MAIN[18][29][19]MAIN[18][29][20]MAIN[18][28][20]MAIN[18][28][21]CELL[20].IMUX_BUFHCE_W[1]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[2]
BitsDestination
MAIN[18][27][40]MAIN[18][26][40]MAIN[18][26][42]MAIN[18][27][43]MAIN[18][26][44]MAIN[18][27][45]MAIN[18][26][46]MAIN[18][27][47]MAIN[18][26][39]MAIN[18][26][37]MAIN[18][27][39]MAIN[18][27][38]MAIN[18][26][38]MAIN[18][26][35]MAIN[18][26][36]MAIN[18][27][36]MAIN[18][27][37]CELL[20].IMUX_BUFHCE_W[2]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[3]
BitsDestination
MAIN[18][28][40]MAIN[18][29][40]MAIN[18][29][42]MAIN[18][28][43]MAIN[18][29][44]MAIN[18][28][45]MAIN[18][29][46]MAIN[18][28][47]MAIN[18][29][39]MAIN[18][29][37]MAIN[18][28][39]MAIN[18][28][38]MAIN[18][29][38]MAIN[18][29][35]MAIN[18][29][36]MAIN[18][28][36]MAIN[18][28][37]CELL[20].IMUX_BUFHCE_W[3]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[4]
BitsDestination
MAIN[18][27][56]MAIN[18][26][56]MAIN[18][26][58]MAIN[18][27][59]MAIN[18][26][60]MAIN[18][27][61]MAIN[18][26][62]MAIN[18][27][63]MAIN[18][26][55]MAIN[18][26][53]MAIN[18][27][55]MAIN[18][27][54]MAIN[18][26][54]MAIN[18][26][51]MAIN[18][26][52]MAIN[18][27][52]MAIN[18][27][53]CELL[20].IMUX_BUFHCE_W[4]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[5]
BitsDestination
MAIN[18][28][56]MAIN[18][29][56]MAIN[18][29][58]MAIN[18][28][59]MAIN[18][29][60]MAIN[18][28][61]MAIN[18][29][62]MAIN[18][28][63]MAIN[18][29][55]MAIN[18][29][53]MAIN[18][28][55]MAIN[18][28][54]MAIN[18][29][54]MAIN[18][29][51]MAIN[18][29][52]MAIN[18][28][52]MAIN[18][28][53]CELL[20].IMUX_BUFHCE_W[5]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[6]
BitsDestination
MAIN[21][27][8]MAIN[21][26][8]MAIN[21][26][10]MAIN[21][27][11]MAIN[21][26][12]MAIN[21][27][13]MAIN[21][26][14]MAIN[21][27][15]MAIN[21][26][7]MAIN[21][26][5]MAIN[21][27][7]MAIN[21][27][6]MAIN[21][26][6]MAIN[21][26][3]MAIN[21][26][4]MAIN[21][27][4]MAIN[21][27][5]CELL[20].IMUX_BUFHCE_W[6]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[7]
BitsDestination
MAIN[21][28][8]MAIN[21][29][8]MAIN[21][29][10]MAIN[21][28][11]MAIN[21][29][12]MAIN[21][28][13]MAIN[21][29][14]MAIN[21][28][15]MAIN[21][29][7]MAIN[21][29][5]MAIN[21][28][7]MAIN[21][28][6]MAIN[21][29][6]MAIN[21][29][3]MAIN[21][29][4]MAIN[21][28][4]MAIN[21][28][5]CELL[20].IMUX_BUFHCE_W[7]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[8]
BitsDestination
MAIN[21][27][24]MAIN[21][26][24]MAIN[21][26][26]MAIN[21][27][27]MAIN[21][26][28]MAIN[21][27][29]MAIN[21][26][30]MAIN[21][27][31]MAIN[21][26][23]MAIN[21][26][21]MAIN[21][27][23]MAIN[21][27][22]MAIN[21][26][22]MAIN[21][26][19]MAIN[21][26][20]MAIN[21][27][20]MAIN[21][27][21]CELL[20].IMUX_BUFHCE_W[8]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[9]
BitsDestination
MAIN[21][28][24]MAIN[21][29][24]MAIN[21][29][26]MAIN[21][28][27]MAIN[21][29][28]MAIN[21][28][29]MAIN[21][29][30]MAIN[21][28][31]MAIN[21][29][23]MAIN[21][29][21]MAIN[21][28][23]MAIN[21][28][22]MAIN[21][29][22]MAIN[21][29][19]MAIN[21][29][20]MAIN[21][28][20]MAIN[21][28][21]CELL[20].IMUX_BUFHCE_W[9]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[10]
BitsDestination
MAIN[21][27][40]MAIN[21][26][40]MAIN[21][26][42]MAIN[21][27][43]MAIN[21][26][44]MAIN[21][27][45]MAIN[21][26][46]MAIN[21][27][47]MAIN[21][26][39]MAIN[21][26][37]MAIN[21][27][39]MAIN[21][27][38]MAIN[21][26][38]MAIN[21][26][35]MAIN[21][26][36]MAIN[21][27][36]MAIN[21][27][37]CELL[20].IMUX_BUFHCE_W[10]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_W[11]
BitsDestination
MAIN[21][28][40]MAIN[21][29][40]MAIN[21][29][42]MAIN[21][28][43]MAIN[21][29][44]MAIN[21][28][45]MAIN[21][29][46]MAIN[21][28][47]MAIN[21][29][39]MAIN[21][29][37]MAIN[21][28][39]MAIN[21][28][38]MAIN[21][29][38]MAIN[21][29][35]MAIN[21][29][36]MAIN[21][28][36]MAIN[21][28][37]CELL[20].IMUX_BUFHCE_W[11]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_W[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_W[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[0]
BitsDestination
MAIN[18][31][24]MAIN[18][30][24]MAIN[18][30][26]MAIN[18][31][27]MAIN[18][30][28]MAIN[18][31][29]MAIN[18][30][30]MAIN[18][31][31]MAIN[18][30][23]MAIN[18][30][21]MAIN[18][31][23]MAIN[18][31][22]MAIN[18][30][22]MAIN[18][30][19]MAIN[18][30][20]MAIN[18][31][20]MAIN[18][31][21]CELL[20].IMUX_BUFHCE_E[0]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[1]
BitsDestination
MAIN[18][32][24]MAIN[18][33][24]MAIN[18][33][26]MAIN[18][32][27]MAIN[18][33][28]MAIN[18][32][29]MAIN[18][33][30]MAIN[18][32][31]MAIN[18][33][23]MAIN[18][33][21]MAIN[18][32][23]MAIN[18][32][22]MAIN[18][33][22]MAIN[18][33][19]MAIN[18][33][20]MAIN[18][32][20]MAIN[18][32][21]CELL[20].IMUX_BUFHCE_E[1]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[2]
BitsDestination
MAIN[18][31][40]MAIN[18][30][40]MAIN[18][30][42]MAIN[18][31][43]MAIN[18][30][44]MAIN[18][31][45]MAIN[18][30][46]MAIN[18][31][47]MAIN[18][30][39]MAIN[18][30][37]MAIN[18][31][39]MAIN[18][31][38]MAIN[18][30][38]MAIN[18][30][35]MAIN[18][30][36]MAIN[18][31][36]MAIN[18][31][37]CELL[20].IMUX_BUFHCE_E[2]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[3]
BitsDestination
MAIN[18][32][40]MAIN[18][33][40]MAIN[18][33][42]MAIN[18][32][43]MAIN[18][33][44]MAIN[18][32][45]MAIN[18][33][46]MAIN[18][32][47]MAIN[18][33][39]MAIN[18][33][37]MAIN[18][32][39]MAIN[18][32][38]MAIN[18][33][38]MAIN[18][33][35]MAIN[18][33][36]MAIN[18][32][36]MAIN[18][32][37]CELL[20].IMUX_BUFHCE_E[3]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[4]
BitsDestination
MAIN[18][31][56]MAIN[18][30][56]MAIN[18][30][58]MAIN[18][31][59]MAIN[18][30][60]MAIN[18][31][61]MAIN[18][30][62]MAIN[18][31][63]MAIN[18][30][55]MAIN[18][30][53]MAIN[18][31][55]MAIN[18][31][54]MAIN[18][30][54]MAIN[18][30][51]MAIN[18][30][52]MAIN[18][31][52]MAIN[18][31][53]CELL[20].IMUX_BUFHCE_E[4]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[5]
BitsDestination
MAIN[18][32][56]MAIN[18][33][56]MAIN[18][33][58]MAIN[18][32][59]MAIN[18][33][60]MAIN[18][32][61]MAIN[18][33][62]MAIN[18][32][63]MAIN[18][33][55]MAIN[18][33][53]MAIN[18][32][55]MAIN[18][32][54]MAIN[18][33][54]MAIN[18][33][51]MAIN[18][33][52]MAIN[18][32][52]MAIN[18][32][53]CELL[20].IMUX_BUFHCE_E[5]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[6]
BitsDestination
MAIN[21][31][8]MAIN[21][30][8]MAIN[21][30][10]MAIN[21][31][11]MAIN[21][30][12]MAIN[21][31][13]MAIN[21][30][14]MAIN[21][31][15]MAIN[21][30][7]MAIN[21][30][5]MAIN[21][31][7]MAIN[21][31][6]MAIN[21][30][6]MAIN[21][30][3]MAIN[21][30][4]MAIN[21][31][4]MAIN[21][31][5]CELL[20].IMUX_BUFHCE_E[6]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[7]
BitsDestination
MAIN[21][32][8]MAIN[21][33][8]MAIN[21][33][10]MAIN[21][32][11]MAIN[21][33][12]MAIN[21][32][13]MAIN[21][33][14]MAIN[21][32][15]MAIN[21][33][7]MAIN[21][33][5]MAIN[21][32][7]MAIN[21][32][6]MAIN[21][33][6]MAIN[21][33][3]MAIN[21][33][4]MAIN[21][32][4]MAIN[21][32][5]CELL[20].IMUX_BUFHCE_E[7]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[8]
BitsDestination
MAIN[21][31][24]MAIN[21][30][24]MAIN[21][30][26]MAIN[21][31][27]MAIN[21][30][28]MAIN[21][31][29]MAIN[21][30][30]MAIN[21][31][31]MAIN[21][30][23]MAIN[21][30][21]MAIN[21][31][23]MAIN[21][31][22]MAIN[21][30][22]MAIN[21][30][19]MAIN[21][30][20]MAIN[21][31][20]MAIN[21][31][21]CELL[20].IMUX_BUFHCE_E[8]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[9]
BitsDestination
MAIN[21][32][24]MAIN[21][33][24]MAIN[21][33][26]MAIN[21][32][27]MAIN[21][33][28]MAIN[21][32][29]MAIN[21][33][30]MAIN[21][32][31]MAIN[21][33][23]MAIN[21][33][21]MAIN[21][32][23]MAIN[21][32][22]MAIN[21][33][22]MAIN[21][33][19]MAIN[21][33][20]MAIN[21][32][20]MAIN[21][32][21]CELL[20].IMUX_BUFHCE_E[9]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[10]
BitsDestination
MAIN[21][31][40]MAIN[21][30][40]MAIN[21][30][42]MAIN[21][31][43]MAIN[21][30][44]MAIN[21][31][45]MAIN[21][30][46]MAIN[21][31][47]MAIN[21][30][39]MAIN[21][30][37]MAIN[21][31][39]MAIN[21][31][38]MAIN[21][30][38]MAIN[21][30][35]MAIN[21][30][36]MAIN[21][31][36]MAIN[21][31][37]CELL[20].IMUX_BUFHCE_E[10]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_BUFHCE_E[11]
BitsDestination
MAIN[21][32][40]MAIN[21][33][40]MAIN[21][33][42]MAIN[21][32][43]MAIN[21][33][44]MAIN[21][32][45]MAIN[21][33][46]MAIN[21][32][47]MAIN[21][33][39]MAIN[21][33][37]MAIN[21][32][39]MAIN[21][32][38]MAIN[21][33][38]MAIN[21][33][35]MAIN[21][33][36]MAIN[21][32][36]MAIN[21][32][37]CELL[20].IMUX_BUFHCE_E[11]
Source
00000000000000000off
00000001000000001CELL[20].GCLK_CMT[0]
00000001000000010CELL[20].GCLK_CMT[8]
00000001000000100CELL[20].GCLK_CMT[16]
00000001000001000CELL[20].GCLK_CMT[24]
00000001000010000CELL[20].BUFH_INT_E[0]
00000001000100000CELL[20].BUFH_TEST_E
00000001001000000CELL[20].CCIO_CMT_W[0]
00000001010000000CELL[20].OUT_PLL_S[0]
00000001100000000CELL[20].OUT_PLL_N[0]
00000010000000001CELL[20].GCLK_CMT[1]
00000010000000010CELL[20].GCLK_CMT[9]
00000010000000100CELL[20].GCLK_CMT[17]
00000010000001000CELL[20].GCLK_CMT[25]
00000010000010000CELL[20].BUFH_INT_E[1]
00000010000100000CELL[20].BUFH_TEST_W
00000010001000000CELL[20].CCIO_CMT_W[1]
00000010010000000CELL[20].OUT_PLL_S[1]
00000010100000000CELL[20].OUT_PLL_N[1]
00000100000000001CELL[20].GCLK_CMT[2]
00000100000000010CELL[20].GCLK_CMT[10]
00000100000000100CELL[20].GCLK_CMT[18]
00000100000001000CELL[20].GCLK_CMT[26]
00000100000010000CELL[20].OUT_PLL_N[8]
00000100000100000CELL[20].OUT_PLL_S[8]
00000100001000000CELL[20].CCIO_CMT_W[2]
00000100010000000CELL[20].OUT_PLL_S[2]
00000100100000000CELL[20].OUT_PLL_N[2]
00001000000000001CELL[20].GCLK_CMT[3]
00001000000000010CELL[20].GCLK_CMT[11]
00001000000000100CELL[20].GCLK_CMT[19]
00001000000001000CELL[20].GCLK_CMT[27]
00001000000010000CELL[20].OUT_PLL_N[9]
00001000000100000CELL[20].OUT_PLL_S[9]
00001000001000000CELL[20].CCIO_CMT_W[3]
00001000010000000CELL[20].OUT_PLL_S[3]
00001000100000000CELL[20].OUT_PLL_N[3]
00010000000000001CELL[20].GCLK_CMT[4]
00010000000000010CELL[20].GCLK_CMT[12]
00010000000000100CELL[20].GCLK_CMT[20]
00010000000001000CELL[20].GCLK_CMT[28]
00010000000010000CELL[20].OUT_PLL_N[10]
00010000000100000CELL[20].OUT_PLL_S[10]
00010000001000000CELL[20].CCIO_CMT_E[0]
00010000010000000CELL[20].OUT_PLL_S[4]
00010000100000000CELL[20].OUT_PLL_N[4]
00100000000000001CELL[20].GCLK_CMT[5]
00100000000000010CELL[20].GCLK_CMT[13]
00100000000000100CELL[20].GCLK_CMT[21]
00100000000001000CELL[20].GCLK_CMT[29]
00100000000010000CELL[20].OUT_PLL_N[11]
00100000000100000CELL[20].OUT_PLL_S[11]
00100000001000000CELL[20].CCIO_CMT_E[1]
00100000010000000CELL[20].OUT_PLL_S[5]
00100000100000000CELL[20].OUT_PLL_N[5]
01000000000000001CELL[20].GCLK_CMT[6]
01000000000000010CELL[20].GCLK_CMT[14]
01000000000000100CELL[20].GCLK_CMT[22]
01000000000001000CELL[20].GCLK_CMT[30]
01000000000010000CELL[20].OUT_PLL_N[12]
01000000000100000CELL[20].OUT_PLL_S[12]
01000000001000000CELL[20].CCIO_CMT_E[2]
01000000010000000CELL[20].OUT_PLL_S[6]
01000000100000000CELL[20].OUT_PLL_N[6]
10000000000000001CELL[20].GCLK_CMT[7]
10000000000000010CELL[20].GCLK_CMT[15]
10000000000000100CELL[20].GCLK_CMT[23]
10000000000001000CELL[20].GCLK_CMT[31]
10000000000010000CELL[20].OUT_PLL_N[13]
10000000000100000CELL[20].OUT_PLL_S[13]
10000000001000000CELL[20].CCIO_CMT_E[3]
10000000010000000CELL[20].OUT_PLL_S[7]
10000000100000000CELL[20].OUT_PLL_N[7]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK_W[0]
BitsDestination
MAIN[19][28][1]MAIN[19][28][2]MAIN[19][29][1]MAIN[19][28][9]MAIN[19][29][9]MAIN[19][28][10]MAIN[19][29][11]MAIN[19][28][12]MAIN[19][29][13]CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK_W[1]
BitsDestination
MAIN[19][31][1]MAIN[19][31][2]MAIN[19][30][1]MAIN[19][31][9]MAIN[19][30][9]MAIN[19][31][10]MAIN[19][30][11]MAIN[19][31][12]MAIN[19][30][13]CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK_W[0]
BitsDestination
MAIN[19][28][17]MAIN[19][28][18]MAIN[19][29][17]MAIN[19][28][25]MAIN[19][29][25]MAIN[19][28][26]MAIN[19][29][27]MAIN[19][28][28]MAIN[19][29][29]CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK_W[1]
BitsDestination
MAIN[19][31][17]MAIN[19][31][18]MAIN[19][30][17]MAIN[19][31][25]MAIN[19][30][25]MAIN[19][31][26]MAIN[19][30][27]MAIN[19][31][28]MAIN[19][30][29]CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK_W[0]
BitsDestination
MAIN[19][28][33]MAIN[19][28][34]MAIN[19][29][33]MAIN[19][28][41]MAIN[19][29][41]MAIN[19][28][42]MAIN[19][29][43]MAIN[19][28][44]MAIN[19][29][45]CELL[20].IMUX_PLL_CLKFB_HCLK_W[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK_W[1]
BitsDestination
MAIN[19][31][33]MAIN[19][31][34]MAIN[19][30][33]MAIN[19][31][41]MAIN[19][30][41]MAIN[19][31][42]MAIN[19][30][43]MAIN[19][31][44]MAIN[19][30][45]CELL[20].IMUX_PLL_CLKFB_HCLK_W[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_W[0]
001000010CELL[20].HCLK_CMT_W[1]
001000100CELL[20].HCLK_CMT_W[2]
001001000CELL[20].HCLK_CMT_W[3]
001010000CELL[20].HCLK_CMT_W[4]
001100000CELL[20].HCLK_CMT_W[5]
010000001CELL[20].HCLK_CMT_W[6]
010000010CELL[20].HCLK_CMT_W[7]
010000100CELL[20].HCLK_CMT_W[8]
010001000CELL[20].HCLK_CMT_W[9]
010010000CELL[20].HCLK_CMT_W[10]
010100000CELL[20].HCLK_CMT_W[11]
100000001CELL[20].RCLK_CMT_W[0]
100000010CELL[20].RCLK_CMT_W[1]
100000100CELL[20].RCLK_CMT_W[2]
100001000CELL[20].RCLK_CMT_W[3]
100010000CELL[20].RCLK_CMT_W[4]
100100000CELL[20].RCLK_CMT_W[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK_E[0]
BitsDestination
MAIN[20][31][49]MAIN[20][31][50]MAIN[20][30][49]MAIN[20][31][57]MAIN[20][30][57]MAIN[20][31][58]MAIN[20][30][59]MAIN[20][31][60]MAIN[20][30][61]CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK_E[1]
BitsDestination
MAIN[20][28][49]MAIN[20][28][50]MAIN[20][29][49]MAIN[20][28][57]MAIN[20][29][57]MAIN[20][28][58]MAIN[20][29][59]MAIN[20][28][60]MAIN[20][29][61]CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK_E[0]
BitsDestination
MAIN[20][31][33]MAIN[20][31][34]MAIN[20][30][33]MAIN[20][31][41]MAIN[20][30][41]MAIN[20][31][42]MAIN[20][30][43]MAIN[20][31][44]MAIN[20][30][45]CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK_E[1]
BitsDestination
MAIN[20][28][33]MAIN[20][28][34]MAIN[20][29][33]MAIN[20][28][41]MAIN[20][29][41]MAIN[20][28][42]MAIN[20][29][43]MAIN[20][28][44]MAIN[20][29][45]CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK_E[0]
BitsDestination
MAIN[20][31][17]MAIN[20][31][18]MAIN[20][30][17]MAIN[20][31][25]MAIN[20][30][25]MAIN[20][31][26]MAIN[20][30][27]MAIN[20][31][28]MAIN[20][30][29]CELL[20].IMUX_PLL_CLKFB_HCLK_E[0]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK_E[1]
BitsDestination
MAIN[20][28][17]MAIN[20][28][18]MAIN[20][29][17]MAIN[20][28][25]MAIN[20][29][25]MAIN[20][28][26]MAIN[20][29][27]MAIN[20][28][28]MAIN[20][29][29]CELL[20].IMUX_PLL_CLKFB_HCLK_E[1]
Source
000000000off
001000001CELL[20].HCLK_CMT_E[0]
001000010CELL[20].HCLK_CMT_E[1]
001000100CELL[20].HCLK_CMT_E[2]
001001000CELL[20].HCLK_CMT_E[3]
001010000CELL[20].HCLK_CMT_E[4]
001100000CELL[20].HCLK_CMT_E[5]
010000001CELL[20].HCLK_CMT_E[6]
010000010CELL[20].HCLK_CMT_E[7]
010000100CELL[20].HCLK_CMT_E[8]
010001000CELL[20].HCLK_CMT_E[9]
010010000CELL[20].HCLK_CMT_E[10]
010100000CELL[20].HCLK_CMT_E[11]
100000001CELL[20].RCLK_CMT_E[0]
100000010CELL[20].RCLK_CMT_E[1]
100000100CELL[20].RCLK_CMT_E[2]
100001000CELL[20].RCLK_CMT_E[3]
100010000CELL[20].RCLK_CMT_E[4]
100100000CELL[20].RCLK_CMT_E[5]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK[0]
BitsDestination
MAIN[19][30][0]CELL[20].IMUX_PLL_CLKIN1_HCLK[0]
Source
0CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0]
1CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_HCLK[1]
BitsDestination
MAIN[20][30][48]CELL[20].IMUX_PLL_CLKIN1_HCLK[1]
Source
0CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1]
1CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK[0]
BitsDestination
MAIN[19][30][16]CELL[20].IMUX_PLL_CLKIN2_HCLK[0]
Source
0CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0]
1CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_HCLK[1]
BitsDestination
MAIN[20][30][32]CELL[20].IMUX_PLL_CLKIN2_HCLK[1]
Source
0CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1]
1CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK[0]
BitsDestination
MAIN[19][30][32]CELL[20].IMUX_PLL_CLKFB_HCLK[0]
Source
0CELL[20].IMUX_PLL_CLKFB_HCLK_W[0]
1CELL[20].IMUX_PLL_CLKFB_HCLK_E[0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_HCLK[1]
BitsDestination
MAIN[20][30][16]CELL[20].IMUX_PLL_CLKFB_HCLK[1]
Source
0CELL[20].IMUX_PLL_CLKFB_HCLK_E[1]
1CELL[20].IMUX_PLL_CLKFB_HCLK_W[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_IO[0]
BitsDestination
MAIN[18][28][33]MAIN[18][28][34]MAIN[18][29][33]MAIN[18][28][44]MAIN[18][29][45]MAIN[18][28][41]MAIN[18][29][41]MAIN[18][28][42]MAIN[18][29][43]CELL[20].IMUX_PLL_CLKIN1_IO[0]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_IO[1]
BitsDestination
MAIN[21][28][17]MAIN[21][28][18]MAIN[21][29][17]MAIN[21][28][28]MAIN[21][29][29]MAIN[21][28][25]MAIN[21][29][25]MAIN[21][28][26]MAIN[21][29][27]CELL[20].IMUX_PLL_CLKIN1_IO[1]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_IO[0]
BitsDestination
MAIN[18][31][33]MAIN[18][31][34]MAIN[18][30][33]MAIN[18][31][44]MAIN[18][30][45]MAIN[18][31][41]MAIN[18][30][41]MAIN[18][31][42]MAIN[18][30][43]CELL[20].IMUX_PLL_CLKIN2_IO[0]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_IO[1]
BitsDestination
MAIN[21][31][17]MAIN[21][31][18]MAIN[21][30][17]MAIN[21][31][28]MAIN[21][30][29]MAIN[21][31][25]MAIN[21][30][25]MAIN[21][31][26]MAIN[21][30][27]CELL[20].IMUX_PLL_CLKIN2_IO[1]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_IO[0]
BitsDestination
MAIN[18][28][17]MAIN[18][28][18]MAIN[18][29][17]MAIN[18][28][28]MAIN[18][29][29]MAIN[18][28][25]MAIN[18][29][25]MAIN[18][28][26]MAIN[18][29][27]CELL[20].IMUX_PLL_CLKFB_IO[0]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB_IO[1]
BitsDestination
MAIN[21][28][33]MAIN[21][28][34]MAIN[21][29][33]MAIN[21][28][44]MAIN[21][29][45]MAIN[21][28][41]MAIN[21][29][41]MAIN[21][28][42]MAIN[21][29][43]CELL[20].IMUX_PLL_CLKFB_IO[1]
Source
000000000off
001000001CELL[20].CCIO_CMT_W[0]
001000010CELL[20].CCIO_CMT_W[1]
001000100CELL[20].CCIO_CMT_W[2]
001001000CELL[20].CCIO_CMT_W[3]
001010000CELL[20].GIOB_CMT[4]
001100000CELL[20].GIOB_CMT[6]
010000001CELL[20].CCIO_CMT_E[2]
010000010CELL[20].CCIO_CMT_E[3]
010010000CELL[20].CCIO_CMT_E[0]
010100000CELL[20].CCIO_CMT_E[1]
100000001CELL[20].GIOB_CMT[5]
100000010CELL[20].GIOB_CMT[7]
100000100CELL[20].GIOB_CMT[0]
100001000CELL[20].GIOB_CMT[2]
100010000CELL[20].GIOB_CMT[1]
100100000CELL[20].GIOB_CMT[3]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_MGT[0]
BitsDestination
MAIN[18][28][49]MAIN[18][28][50]MAIN[18][29][49]MAIN[18][29][48]MAIN[18][28][58]MAIN[18][29][59]MAIN[18][28][60]MAIN[18][29][61]MAIN[18][28][57]MAIN[18][29][57]CELL[20].IMUX_PLL_CLKIN1_MGT[0]
Source
0000000000off
0010000001CELL[20].MGT_CMT_W[0]
0010000010CELL[20].MGT_CMT_W[1]
0010000100CELL[20].MGT_CMT_E[6]
0010001000CELL[20].MGT_CMT_E[7]
0010010000CELL[20].MGT_CMT_E[8]
0010100000CELL[20].MGT_CMT_E[9]
0011000000CELL[20].MGT_CMT_W[9]
0100000001CELL[20].MGT_CMT_W[6]
0100000010CELL[20].MGT_CMT_W[7]
0100000100CELL[20].MGT_CMT_W[2]
0100001000CELL[20].MGT_CMT_W[3]
0100010000CELL[20].MGT_CMT_W[4]
0100100000CELL[20].MGT_CMT_W[5]
1000000001CELL[20].MGT_CMT_E[4]
1000000010CELL[20].MGT_CMT_E[5]
1000000100CELL[20].MGT_CMT_E[0]
1000001000CELL[20].MGT_CMT_E[1]
1000010000CELL[20].MGT_CMT_E[2]
1000100000CELL[20].MGT_CMT_E[3]
1001000000CELL[20].MGT_CMT_W[8]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1_MGT[1]
BitsDestination
MAIN[21][28][1]MAIN[21][28][2]MAIN[21][29][1]MAIN[21][29][0]MAIN[21][28][10]MAIN[21][29][11]MAIN[21][28][12]MAIN[21][29][13]MAIN[21][28][9]MAIN[21][29][9]CELL[20].IMUX_PLL_CLKIN1_MGT[1]
Source
0000000000off
0010000001CELL[20].MGT_CMT_W[0]
0010000010CELL[20].MGT_CMT_W[1]
0010000100CELL[20].MGT_CMT_E[6]
0010001000CELL[20].MGT_CMT_E[7]
0010010000CELL[20].MGT_CMT_E[8]
0010100000CELL[20].MGT_CMT_E[9]
0011000000CELL[20].MGT_CMT_W[9]
0100000001CELL[20].MGT_CMT_W[6]
0100000010CELL[20].MGT_CMT_W[7]
0100000100CELL[20].MGT_CMT_W[2]
0100001000CELL[20].MGT_CMT_W[3]
0100010000CELL[20].MGT_CMT_W[4]
0100100000CELL[20].MGT_CMT_W[5]
1000000001CELL[20].MGT_CMT_E[4]
1000000010CELL[20].MGT_CMT_E[5]
1000000100CELL[20].MGT_CMT_E[0]
1000001000CELL[20].MGT_CMT_E[1]
1000010000CELL[20].MGT_CMT_E[2]
1000100000CELL[20].MGT_CMT_E[3]
1001000000CELL[20].MGT_CMT_W[8]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_MGT[0]
BitsDestination
MAIN[18][31][49]MAIN[18][31][50]MAIN[18][30][49]MAIN[18][30][48]MAIN[18][31][58]MAIN[18][30][59]MAIN[18][31][60]MAIN[18][30][61]MAIN[18][31][57]MAIN[18][30][57]CELL[20].IMUX_PLL_CLKIN2_MGT[0]
Source
0000000000off
0010000001CELL[20].MGT_CMT_W[0]
0010000010CELL[20].MGT_CMT_W[1]
0010000100CELL[20].MGT_CMT_E[6]
0010001000CELL[20].MGT_CMT_E[7]
0010010000CELL[20].MGT_CMT_E[8]
0010100000CELL[20].MGT_CMT_E[9]
0011000000CELL[20].MGT_CMT_W[9]
0100000001CELL[20].MGT_CMT_W[6]
0100000010CELL[20].MGT_CMT_W[7]
0100000100CELL[20].MGT_CMT_W[2]
0100001000CELL[20].MGT_CMT_W[3]
0100010000CELL[20].MGT_CMT_W[4]
0100100000CELL[20].MGT_CMT_W[5]
1000000001CELL[20].MGT_CMT_E[4]
1000000010CELL[20].MGT_CMT_E[5]
1000000100CELL[20].MGT_CMT_E[0]
1000001000CELL[20].MGT_CMT_E[1]
1000010000CELL[20].MGT_CMT_E[2]
1000100000CELL[20].MGT_CMT_E[3]
1001000000CELL[20].MGT_CMT_W[8]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2_MGT[1]
BitsDestination
MAIN[21][31][1]MAIN[21][31][2]MAIN[21][30][1]MAIN[21][30][0]MAIN[21][31][10]MAIN[21][30][11]MAIN[21][31][12]MAIN[21][30][13]MAIN[21][31][9]MAIN[21][30][9]CELL[20].IMUX_PLL_CLKIN2_MGT[1]
Source
0000000000off
0010000001CELL[20].MGT_CMT_W[0]
0010000010CELL[20].MGT_CMT_W[1]
0010000100CELL[20].MGT_CMT_E[6]
0010001000CELL[20].MGT_CMT_E[7]
0010010000CELL[20].MGT_CMT_E[8]
0010100000CELL[20].MGT_CMT_E[9]
0011000000CELL[20].MGT_CMT_W[9]
0100000001CELL[20].MGT_CMT_W[6]
0100000010CELL[20].MGT_CMT_W[7]
0100000100CELL[20].MGT_CMT_W[2]
0100001000CELL[20].MGT_CMT_W[3]
0100010000CELL[20].MGT_CMT_W[4]
0100100000CELL[20].MGT_CMT_W[5]
1000000001CELL[20].MGT_CMT_E[4]
1000000010CELL[20].MGT_CMT_E[5]
1000000100CELL[20].MGT_CMT_E[0]
1000001000CELL[20].MGT_CMT_E[1]
1000010000CELL[20].MGT_CMT_E[2]
1000100000CELL[20].MGT_CMT_E[3]
1001000000CELL[20].MGT_CMT_W[8]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1[0]
BitsDestination
MAIN[17][27][62]MAIN[17][26][62]CELL[20].IMUX_PLL_CLKIN1[0]
Source
00CELL[20].IMUX_PLL_CLKIN1_IO[0]
01CELL[20].IMUX_PLL_CLKIN1_HCLK[0]
10CELL[20].IMUX_PLL_CLKIN1_MGT[0]
11CELL[17].IMUX_CLK[0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN1[1]
BitsDestination
MAIN[22][27][1]MAIN[22][26][1]CELL[20].IMUX_PLL_CLKIN1[1]
Source
00CELL[20].IMUX_PLL_CLKIN1_IO[1]
01CELL[20].IMUX_PLL_CLKIN1_HCLK[1]
10CELL[20].IMUX_PLL_CLKIN1_MGT[1]
11CELL[22].IMUX_CLK[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2[0]
BitsDestination
MAIN[17][27][61]MAIN[17][26][61]CELL[20].IMUX_PLL_CLKIN2[0]
Source
00CELL[20].IMUX_PLL_CLKIN2_IO[0]
01CELL[20].IMUX_PLL_CLKIN2_HCLK[0]
10CELL[20].IMUX_PLL_CLKIN2_MGT[0]
11CELL[17].IMUX_CLK[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKIN2[1]
BitsDestination
MAIN[22][27][2]MAIN[22][26][2]CELL[20].IMUX_PLL_CLKIN2[1]
Source
00CELL[20].IMUX_PLL_CLKIN2_IO[1]
01CELL[20].IMUX_PLL_CLKIN2_HCLK[1]
10CELL[20].IMUX_PLL_CLKIN2_MGT[1]
11CELL[22].IMUX_CLK[0]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB[0]
BitsDestination
MAIN[17][27][63]MAIN[17][26][63]CELL[20].IMUX_PLL_CLKFB[0]
Source
00CELL[20].IMUX_PLL_CLKFB_IO[0]
01CELL[20].IMUX_PLL_CLKFB_HCLK[0]
11CELL[18].IMUX_CLK[1]
virtex6 CMT switchbox SPEC_INT muxes IMUX_PLL_CLKFB[1]
BitsDestination
MAIN[22][27][0]MAIN[22][26][0]CELL[20].IMUX_PLL_CLKFB[1]
Source
00CELL[20].IMUX_PLL_CLKFB_IO[1]
01CELL[20].IMUX_PLL_CLKFB_HCLK[1]
11CELL[21].IMUX_CLK[0]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_CASC[0]
BitsDestination
MAIN[17][26][22]MAIN[17][27][23]MAIN[17][26][23]CELL[20].OMUX_PLL_CASC[0]
Source
000CELL[20].OUT_PLL_S[0]
001CELL[20].OUT_PLL_S[2]
010CELL[20].OUT_PLL_S[4]
011CELL[20].OUT_PLL_S[6]
100CELL[20].OUT_PLL_S[8]
101CELL[20].OUT_PLL_S[9]
110CELL[20].OUT_PLL_S[10]
111CELL[20].OUT_PLL_S[11]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_CASC[1]
BitsDestination
MAIN[22][26][41]MAIN[22][27][40]MAIN[22][26][40]CELL[20].OMUX_PLL_CASC[1]
Source
000CELL[20].OUT_PLL_N[0]
001CELL[20].OUT_PLL_N[2]
010CELL[20].OUT_PLL_N[4]
011CELL[20].OUT_PLL_N[6]
100CELL[20].OUT_PLL_N[8]
101CELL[20].OUT_PLL_N[9]
110CELL[20].OUT_PLL_N[10]
111CELL[20].OUT_PLL_N[11]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_S[0]
BitsDestination
MAIN[17][27][31]MAIN[17][26][31]MAIN[17][26][33]CELL[20].OMUX_PLL_PERF_S[0]
Source
000off
001CELL[20].OUT_PLL_S[0]
011CELL[20].OUT_PLL_S[2]
101CELL[20].OUT_PLL_S[4]
111CELL[20].OUT_PLL_S[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_S[1]
BitsDestination
MAIN[17][27][30]MAIN[17][26][30]MAIN[17][27][33]CELL[20].OMUX_PLL_PERF_S[1]
Source
000off
001CELL[20].OUT_PLL_S[0]
011CELL[20].OUT_PLL_S[2]
101CELL[20].OUT_PLL_S[4]
111CELL[20].OUT_PLL_S[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_S[2]
BitsDestination
MAIN[17][27][29]MAIN[17][26][29]MAIN[17][26][32]CELL[20].OMUX_PLL_PERF_S[2]
Source
000off
001CELL[20].OUT_PLL_S[0]
011CELL[20].OUT_PLL_S[2]
101CELL[20].OUT_PLL_S[4]
111CELL[20].OUT_PLL_S[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_S[3]
BitsDestination
MAIN[17][27][28]MAIN[17][26][28]MAIN[17][27][32]CELL[20].OMUX_PLL_PERF_S[3]
Source
000off
001CELL[20].OUT_PLL_S[0]
011CELL[20].OUT_PLL_S[2]
101CELL[20].OUT_PLL_S[4]
111CELL[20].OUT_PLL_S[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_N[0]
BitsDestination
MAIN[22][27][32]MAIN[22][26][32]MAIN[22][26][30]CELL[20].OMUX_PLL_PERF_N[0]
Source
000off
001CELL[20].OUT_PLL_N[0]
011CELL[20].OUT_PLL_N[2]
101CELL[20].OUT_PLL_N[4]
111CELL[20].OUT_PLL_N[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_N[1]
BitsDestination
MAIN[22][27][33]MAIN[22][26][33]MAIN[22][27][30]CELL[20].OMUX_PLL_PERF_N[1]
Source
000off
001CELL[20].OUT_PLL_N[0]
011CELL[20].OUT_PLL_N[2]
101CELL[20].OUT_PLL_N[4]
111CELL[20].OUT_PLL_N[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_N[2]
BitsDestination
MAIN[22][27][34]MAIN[22][26][34]MAIN[22][26][31]CELL[20].OMUX_PLL_PERF_N[2]
Source
000off
001CELL[20].OUT_PLL_N[0]
011CELL[20].OUT_PLL_N[2]
101CELL[20].OUT_PLL_N[4]
111CELL[20].OUT_PLL_N[6]
virtex6 CMT switchbox SPEC_INT muxes OMUX_PLL_PERF_N[3]
BitsDestination
MAIN[22][27][35]MAIN[22][26][35]MAIN[22][27][31]CELL[20].OMUX_PLL_PERF_N[3]
Source
000off
001CELL[20].OUT_PLL_N[0]
011CELL[20].OUT_PLL_N[2]
101CELL[20].OUT_PLL_N[4]
111CELL[20].OUT_PLL_N[6]

Bels PLL_V6

virtex6 CMT bel PLL_V6 pins
PinDirectionPLL[0]PLL[1]
CLKIN1inCELL[20].IMUX_PLL_CLKIN1[0]CELL[20].IMUX_PLL_CLKIN1[1]
CLKIN2inCELL[20].IMUX_PLL_CLKIN2[0]CELL[20].IMUX_PLL_CLKIN2[1]
CLKINSELinCELL[3].IMUX_IMUX[11] invert by MAIN[3][26][45]CELL[36].IMUX_IMUX[36] invert by MAIN[36][26][18]
CLKFBINinCELL[20].IMUX_PLL_CLKFB[0]CELL[20].IMUX_PLL_CLKFB[1]
CLKIN_CASCinCELL[20].OMUX_PLL_CASC[1]CELL[20].OMUX_PLL_CASC[0]
CLKFB_CASCinCELL[20].OMUX_PLL_CASC[0]CELL[20].OMUX_PLL_CASC[1]
RSTinCELL[3].IMUX_IMUX[8] invert by MAIN[3][26][47]CELL[36].IMUX_IMUX[39] invert by MAIN[36][26][16]
PWRDWNinCELL[3].IMUX_IMUX[34] invert by MAIN[3][27][47]CELL[36].IMUX_IMUX[13] invert by MAIN[36][27][16]
DCLKinCELL[2].IMUX_CLK[0]CELL[37].IMUX_CLK[1]
DENinCELL[3].IMUX_IMUX[9]CELL[36].IMUX_IMUX[38]
DWEinCELL[3].IMUX_IMUX[10]CELL[36].IMUX_IMUX[37]
DADDR[0]inCELL[5].IMUX_IMUX[7]CELL[34].IMUX_IMUX[40]
DADDR[1]inCELL[5].IMUX_IMUX[6]CELL[34].IMUX_IMUX[41]
DADDR[2]inCELL[5].IMUX_IMUX[5]CELL[34].IMUX_IMUX[42]
DADDR[3]inCELL[5].IMUX_IMUX[43]CELL[34].IMUX_IMUX[4]
DADDR[4]inCELL[5].IMUX_IMUX[42]CELL[34].IMUX_IMUX[5]
DADDR[5]inCELL[5].IMUX_IMUX[41]CELL[34].IMUX_IMUX[6]
DADDR[6]inCELL[5].IMUX_IMUX[40]CELL[34].IMUX_IMUX[7]
DI[0]inCELL[4].IMUX_IMUX[15]CELL[35].IMUX_IMUX[32]
DI[1]inCELL[4].IMUX_IMUX[14]CELL[35].IMUX_IMUX[33]
DI[2]inCELL[4].IMUX_IMUX[13]CELL[35].IMUX_IMUX[34]
DI[3]inCELL[4].IMUX_IMUX[12]CELL[35].IMUX_IMUX[35]
DI[4]inCELL[4].IMUX_IMUX[11]CELL[35].IMUX_IMUX[36]
DI[5]inCELL[4].IMUX_IMUX[10]CELL[35].IMUX_IMUX[37]
DI[6]inCELL[4].IMUX_IMUX[17]CELL[35].IMUX_IMUX[30]
DI[7]inCELL[4].IMUX_IMUX[16]CELL[35].IMUX_IMUX[31]
DI[8]inCELL[3].IMUX_IMUX[39]CELL[36].IMUX_IMUX[8]
DI[9]inCELL[3].IMUX_IMUX[7]CELL[36].IMUX_IMUX[40]
DI[10]inCELL[3].IMUX_IMUX[22]CELL[36].IMUX_IMUX[25]
DI[11]inCELL[3].IMUX_IMUX[37]CELL[36].IMUX_IMUX[10]
DI[12]inCELL[3].IMUX_IMUX[13]CELL[36].IMUX_IMUX[34]
DI[13]inCELL[3].IMUX_IMUX[36]CELL[36].IMUX_IMUX[11]
DI[14]inCELL[3].IMUX_IMUX[12]CELL[36].IMUX_IMUX[35]
DI[15]inCELL[3].IMUX_IMUX[35]CELL[36].IMUX_IMUX[12]
PSCLKinCELL[2].IMUX_CLK[1]CELL[37].IMUX_CLK[0]
PSENinCELL[3].IMUX_IMUX[33] invert by MAIN[3][27][46]CELL[36].IMUX_IMUX[14] invert by MAIN[36][27][17]
PSINCDECinCELL[3].IMUX_IMUX[32] invert by MAIN[3][26][46]CELL[36].IMUX_IMUX[15] invert by MAIN[36][26][17]
TESTIN[0]inCELL[17].IMUX_IMUX[14]CELL[22].IMUX_IMUX[33]
TESTIN[1]inCELL[8].IMUX_IMUX[27]CELL[31].IMUX_IMUX[20]
TESTIN[2]inCELL[8].IMUX_IMUX[11]CELL[31].IMUX_IMUX[36]
TESTIN[3]inCELL[8].IMUX_IMUX[26]CELL[31].IMUX_IMUX[21]
TESTIN[4]inCELL[8].IMUX_IMUX[10]CELL[31].IMUX_IMUX[37]
TESTIN[5]inCELL[8].IMUX_IMUX[25]CELL[31].IMUX_IMUX[22]
TESTIN[6]inCELL[8].IMUX_IMUX[9]CELL[31].IMUX_IMUX[38]
TESTIN[7]inCELL[8].IMUX_IMUX[24]CELL[31].IMUX_IMUX[23]
TESTIN[8]inCELL[8].IMUX_IMUX[8]CELL[31].IMUX_IMUX[39]
TESTIN[9]inCELL[7].IMUX_IMUX[39]CELL[32].IMUX_IMUX[8]
TESTIN[10]inCELL[7].IMUX_IMUX[23]CELL[32].IMUX_IMUX[24]
TESTIN[11]inCELL[7].IMUX_IMUX[7]CELL[32].IMUX_IMUX[40]
TESTIN[12]inCELL[7].IMUX_IMUX[38]CELL[32].IMUX_IMUX[9]
TESTIN[13]inCELL[7].IMUX_IMUX[22]CELL[32].IMUX_IMUX[25]
TESTIN[14]inCELL[7].IMUX_IMUX[6]CELL[32].IMUX_IMUX[41]
TESTIN[15]inCELL[7].IMUX_IMUX[37]CELL[32].IMUX_IMUX[10]
TESTIN[16]inCELL[7].IMUX_IMUX[21]CELL[32].IMUX_IMUX[26]
TESTIN[17]inCELL[7].IMUX_IMUX[5]CELL[32].IMUX_IMUX[42]
TESTIN[18]inCELL[7].IMUX_IMUX[28]CELL[32].IMUX_IMUX[19]
TESTIN[19]inCELL[7].IMUX_IMUX[12]CELL[32].IMUX_IMUX[35]
TESTIN[20]inCELL[7].IMUX_IMUX[43]CELL[32].IMUX_IMUX[4]
TESTIN[21]inCELL[7].IMUX_IMUX[27]CELL[32].IMUX_IMUX[20]
TESTIN[22]inCELL[7].IMUX_IMUX[11]CELL[32].IMUX_IMUX[36]
TESTIN[23]inCELL[7].IMUX_IMUX[42]CELL[32].IMUX_IMUX[5]
TESTIN[24]inCELL[7].IMUX_IMUX[26]CELL[32].IMUX_IMUX[21]
TESTIN[25]inCELL[7].IMUX_IMUX[10]CELL[32].IMUX_IMUX[37]
TESTIN[26]inCELL[7].IMUX_IMUX[41]CELL[32].IMUX_IMUX[6]
TESTIN[27]inCELL[7].IMUX_IMUX[25]CELL[32].IMUX_IMUX[22]
TESTIN[28]inCELL[7].IMUX_IMUX[9]CELL[32].IMUX_IMUX[38]
TESTIN[29]inCELL[7].IMUX_IMUX[40]CELL[32].IMUX_IMUX[7]
TESTIN[30]inCELL[7].IMUX_IMUX[24]CELL[32].IMUX_IMUX[23]
TESTIN[31]inCELL[7].IMUX_IMUX[8]CELL[32].IMUX_IMUX[39]
CLKOUT0outCELL[20].OUT_PLL_S[0]CELL[20].OUT_PLL_N[0]
CLKOUT0BoutCELL[20].OUT_PLL_S[1]CELL[20].OUT_PLL_N[1]
CLKOUT1outCELL[20].OUT_PLL_S[2]CELL[20].OUT_PLL_N[2]
CLKOUT1BoutCELL[20].OUT_PLL_S[3]CELL[20].OUT_PLL_N[3]
CLKOUT2outCELL[20].OUT_PLL_S[4]CELL[20].OUT_PLL_N[4]
CLKOUT2BoutCELL[20].OUT_PLL_S[5]CELL[20].OUT_PLL_N[5]
CLKOUT3outCELL[20].OUT_PLL_S[6]CELL[20].OUT_PLL_N[6]
CLKOUT3BoutCELL[20].OUT_PLL_S[7]CELL[20].OUT_PLL_N[7]
CLKOUT4outCELL[20].OUT_PLL_S[8]CELL[20].OUT_PLL_N[8]
CLKOUT5outCELL[20].OUT_PLL_S[9]CELL[20].OUT_PLL_N[9]
CLKOUT6outCELL[20].OUT_PLL_S[10]CELL[20].OUT_PLL_N[10]
CLKFBOUToutCELL[20].OUT_PLL_S[11]CELL[20].OUT_PLL_N[11]
CLKFBOUTBoutCELL[20].OUT_PLL_S[12]CELL[20].OUT_PLL_N[12]
TMUXOUToutCELL[20].OUT_PLL_S[13]CELL[20].OUT_PLL_N[13]
LOCKEDoutCELL[2].OUT_BEL[8]CELL[37].OUT_BEL[17]
DRDYoutCELL[2].OUT_BEL[18]CELL[37].OUT_BEL[11]
DO[0]outCELL[3].OUT_BEL[7]CELL[36].OUT_BEL[4]
DO[1]outCELL[3].OUT_BEL[3]CELL[36].OUT_BEL[0]
DO[2]outCELL[3].OUT_BEL[2]CELL[36].OUT_BEL[1]
DO[3]outCELL[3].OUT_BEL[6]CELL[36].OUT_BEL[5]
DO[4]outCELL[3].OUT_BEL[5]CELL[36].OUT_BEL[6]
DO[5]outCELL[3].OUT_BEL[1]CELL[36].OUT_BEL[2]
DO[6]outCELL[3].OUT_BEL[0]CELL[36].OUT_BEL[3]
DO[7]outCELL[3].OUT_BEL[4]CELL[36].OUT_BEL[7]
DO[8]outCELL[2].OUT_BEL[17]CELL[37].OUT_BEL[8]
DO[9]outCELL[2].OUT_BEL[11]CELL[37].OUT_BEL[18]
DO[10]outCELL[2].OUT_BEL[15]CELL[37].OUT_BEL[22]
DO[11]outCELL[2].OUT_BEL[2]CELL[37].OUT_BEL[1]
DO[12]outCELL[2].OUT_BEL[16]CELL[37].OUT_BEL[9]
DO[13]outCELL[2].OUT_BEL[19]CELL[37].OUT_BEL[10]
DO[14]outCELL[2].OUT_BEL[9]CELL[37].OUT_BEL[16]
DO[15]outCELL[2].OUT_BEL[1]CELL[37].OUT_BEL[2]
PSDONEoutCELL[2].OUT_BEL[0]CELL[37].OUT_BEL[3]
CLKINSTOPPEDoutCELL[4].OUT_BEL[4]CELL[35].OUT_BEL[7]
CLKFBSTOPPEDoutCELL[4].OUT_BEL[0]CELL[35].OUT_BEL[3]
TESTOUT[0]outCELL[8].OUT_BEL[0]CELL[31].OUT_BEL[3]
TESTOUT[1]outCELL[8].OUT_BEL[4]CELL[31].OUT_BEL[7]
TESTOUT[2]outCELL[7].OUT_BEL[7]CELL[32].OUT_BEL[4]
TESTOUT[3]outCELL[7].OUT_BEL[3]CELL[32].OUT_BEL[0]
TESTOUT[4]outCELL[7].OUT_BEL[2]CELL[32].OUT_BEL[1]
TESTOUT[5]outCELL[7].OUT_BEL[6]CELL[32].OUT_BEL[5]
TESTOUT[6]outCELL[7].OUT_BEL[5]CELL[32].OUT_BEL[6]
TESTOUT[7]outCELL[7].OUT_BEL[1]CELL[32].OUT_BEL[2]
TESTOUT[8]outCELL[7].OUT_BEL[0]CELL[32].OUT_BEL[3]
TESTOUT[9]outCELL[7].OUT_BEL[4]CELL[32].OUT_BEL[7]
TESTOUT[10]outCELL[6].OUT_BEL[7]CELL[33].OUT_BEL[4]
TESTOUT[11]outCELL[6].OUT_BEL[3]CELL[33].OUT_BEL[0]
TESTOUT[12]outCELL[6].OUT_BEL[2]CELL[33].OUT_BEL[1]
TESTOUT[13]outCELL[6].OUT_BEL[6]CELL[33].OUT_BEL[5]
TESTOUT[14]outCELL[6].OUT_BEL[5]CELL[33].OUT_BEL[6]
TESTOUT[15]outCELL[6].OUT_BEL[1]CELL[33].OUT_BEL[2]
TESTOUT[16]outCELL[6].OUT_BEL[0]CELL[33].OUT_BEL[3]
TESTOUT[17]outCELL[6].OUT_BEL[4]CELL[33].OUT_BEL[7]
TESTOUT[18]outCELL[5].OUT_BEL[7]CELL[34].OUT_BEL[4]
TESTOUT[19]outCELL[5].OUT_BEL[3]CELL[34].OUT_BEL[0]
TESTOUT[20]outCELL[5].OUT_BEL[2]CELL[34].OUT_BEL[1]
TESTOUT[21]outCELL[5].OUT_BEL[6]CELL[34].OUT_BEL[5]
TESTOUT[22]outCELL[5].OUT_BEL[5]CELL[34].OUT_BEL[6]
TESTOUT[23]outCELL[5].OUT_BEL[1]CELL[34].OUT_BEL[2]
TESTOUT[24]outCELL[5].OUT_BEL[0]CELL[34].OUT_BEL[3]
TESTOUT[25]outCELL[5].OUT_BEL[4]CELL[34].OUT_BEL[7]
TESTOUT[26]outCELL[4].OUT_BEL[7]CELL[35].OUT_BEL[4]
TESTOUT[27]outCELL[4].OUT_BEL[3]CELL[35].OUT_BEL[0]
TESTOUT[28]outCELL[4].OUT_BEL[2]CELL[35].OUT_BEL[1]
TESTOUT[29]outCELL[4].OUT_BEL[6]CELL[35].OUT_BEL[5]
TESTOUT[30]outCELL[4].OUT_BEL[5]CELL[35].OUT_BEL[6]
TESTOUT[31]outCELL[4].OUT_BEL[1]CELL[35].OUT_BEL[2]
TESTOUT[32]outCELL[17].IMUX_SPEC[3]CELL[27].OUT_BEL[3]
TESTOUT[33]outCELL[17].IMUX_SPEC[3]CELL[27].OUT_BEL[7]
TESTOUT[34]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[35]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[36]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[37]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[38]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[39]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[40]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[41]outCELL[17].IMUX_SPEC[3]CELL[37].IMUX_SPEC[3]
TESTOUT[42]outCELL[10].OUT_BEL[7]CELL[29].OUT_BEL[4]
TESTOUT[43]outCELL[10].OUT_BEL[3]CELL[29].OUT_BEL[0]
TESTOUT[44]outCELL[10].OUT_BEL[2]CELL[29].OUT_BEL[1]
TESTOUT[45]outCELL[10].OUT_BEL[6]CELL[29].OUT_BEL[5]
TESTOUT[46]outCELL[10].OUT_BEL[5]CELL[29].OUT_BEL[6]
TESTOUT[47]outCELL[10].OUT_BEL[1]CELL[29].OUT_BEL[2]
TESTOUT[48]outCELL[10].OUT_BEL[0]CELL[29].OUT_BEL[3]
TESTOUT[49]outCELL[10].OUT_BEL[4]CELL[29].OUT_BEL[7]
TESTOUT[50]outCELL[9].OUT_BEL[7]CELL[30].OUT_BEL[4]
TESTOUT[51]outCELL[9].OUT_BEL[3]CELL[30].OUT_BEL[0]
TESTOUT[52]outCELL[9].OUT_BEL[2]CELL[30].OUT_BEL[1]
TESTOUT[53]outCELL[9].OUT_BEL[6]CELL[30].OUT_BEL[5]
TESTOUT[54]outCELL[9].OUT_BEL[5]CELL[30].OUT_BEL[6]
TESTOUT[55]outCELL[9].OUT_BEL[1]CELL[30].OUT_BEL[2]
TESTOUT[56]outCELL[9].OUT_BEL[0]CELL[30].OUT_BEL[3]
TESTOUT[57]outCELL[9].OUT_BEL[4]CELL[30].OUT_BEL[7]
TESTOUT[58]outCELL[8].OUT_BEL[7]CELL[31].OUT_BEL[4]
TESTOUT[59]outCELL[8].OUT_BEL[3]CELL[31].OUT_BEL[0]
TESTOUT[60]outCELL[8].OUT_BEL[2]CELL[31].OUT_BEL[1]
TESTOUT[61]outCELL[8].OUT_BEL[6]CELL[31].OUT_BEL[5]
TESTOUT[62]outCELL[8].OUT_BEL[5]CELL[31].OUT_BEL[6]
TESTOUT[63]outCELL[8].OUT_BEL[1]CELL[31].OUT_BEL[2]
virtex6 CMT bel PLL_V6 attribute bits
AttributePLL[0]PLL[1]
MMCM_DRP[0] bit 0MAIN[17][26][63]MAIN[22][26][0]
MMCM_DRP[0] bit 1MAIN[17][27][63]MAIN[22][27][0]
MMCM_DRP[0] bit 2MAIN[17][26][62]MAIN[22][26][1]
MMCM_DRP[0] bit 3MAIN[17][27][62]MAIN[22][27][1]
MMCM_DRP[0] bit 4MAIN[17][26][61]MAIN[22][26][2]
MMCM_DRP[0] bit 5MAIN[17][27][61]MAIN[22][27][2]
MMCM_DRP[0] bit 6MAIN[17][26][60]MAIN[22][26][3]
MMCM_DRP[0] bit 7MAIN[17][27][60]MAIN[22][27][3]
MMCM_DRP[0] bit 8MAIN[17][26][59]MAIN[22][26][4]
MMCM_DRP[0] bit 9MAIN[17][27][59]MAIN[22][27][4]
MMCM_DRP[0] bit 10MAIN[17][26][58]MAIN[22][26][5]
MMCM_DRP[0] bit 11MAIN[17][27][58]MAIN[22][27][5]
MMCM_DRP[0] bit 12MAIN[17][26][57]MAIN[22][26][6]
MMCM_DRP[0] bit 13MAIN[17][27][57]MAIN[22][27][6]
MMCM_DRP[0] bit 14MAIN[17][26][56]MAIN[22][26][7]
MMCM_DRP[0] bit 15MAIN[17][27][56]MAIN[22][27][7]
MMCM_DRP[1] bit 0MAIN[17][26][55]MAIN[22][26][8]
MMCM_DRP[1] bit 1MAIN[17][27][55]MAIN[22][27][8]
MMCM_DRP[1] bit 2MAIN[17][26][54]MAIN[22][26][9]
MMCM_DRP[1] bit 3MAIN[17][27][54]MAIN[22][27][9]
MMCM_DRP[1] bit 4MAIN[17][26][53]MAIN[22][26][10]
MMCM_DRP[1] bit 5MAIN[17][27][53]MAIN[22][27][10]
MMCM_DRP[1] bit 6MAIN[17][26][52]MAIN[22][26][11]
MMCM_DRP[1] bit 7MAIN[17][27][52]MAIN[22][27][11]
MMCM_DRP[1] bit 8MAIN[17][26][51]MAIN[22][26][12]
MMCM_DRP[1] bit 9MAIN[17][27][51]MAIN[22][27][12]
MMCM_DRP[1] bit 10MAIN[17][26][50]MAIN[22][26][13]
MMCM_DRP[1] bit 11MAIN[17][27][50]MAIN[22][27][13]
MMCM_DRP[1] bit 12MAIN[17][26][49]MAIN[22][26][14]
MMCM_DRP[1] bit 13MAIN[17][27][49]MAIN[22][27][14]
MMCM_DRP[1] bit 14MAIN[17][26][48]MAIN[22][26][15]
MMCM_DRP[1] bit 15MAIN[17][27][48]MAIN[22][27][15]
MMCM_DRP[2] bit 0MAIN[17][26][47]MAIN[22][26][16]
MMCM_DRP[2] bit 1MAIN[17][27][47]MAIN[22][27][16]
MMCM_DRP[2] bit 2MAIN[17][26][46]MAIN[22][26][17]
MMCM_DRP[2] bit 3MAIN[17][27][46]MAIN[22][27][17]
MMCM_DRP[2] bit 4MAIN[17][26][45]MAIN[22][26][18]
MMCM_DRP[2] bit 5MAIN[17][27][45]MAIN[22][27][18]
MMCM_DRP[2] bit 6MAIN[17][26][44]MAIN[22][26][19]
MMCM_DRP[2] bit 7MAIN[17][27][44]MAIN[22][27][19]
MMCM_DRP[2] bit 8MAIN[17][26][43]MAIN[22][26][20]
MMCM_DRP[2] bit 9MAIN[17][27][43]MAIN[22][27][20]
MMCM_DRP[2] bit 10MAIN[17][26][42]MAIN[22][26][21]
MMCM_DRP[2] bit 11MAIN[17][27][42]MAIN[22][27][21]
MMCM_DRP[2] bit 12MAIN[17][26][41]MAIN[22][26][22]
MMCM_DRP[2] bit 13MAIN[17][27][41]MAIN[22][27][22]
MMCM_DRP[2] bit 14MAIN[17][26][40]MAIN[22][26][23]
MMCM_DRP[2] bit 15MAIN[17][27][40]MAIN[22][27][23]
MMCM_DRP[3] bit 0MAIN[17][26][39]MAIN[22][26][24]
MMCM_DRP[3] bit 1MAIN[17][27][39]MAIN[22][27][24]
MMCM_DRP[3] bit 2MAIN[17][26][38]MAIN[22][26][25]
MMCM_DRP[3] bit 3MAIN[17][27][38]MAIN[22][27][25]
MMCM_DRP[3] bit 4MAIN[17][26][37]MAIN[22][26][26]
MMCM_DRP[3] bit 5MAIN[17][27][37]MAIN[22][27][26]
MMCM_DRP[3] bit 6MAIN[17][26][36]MAIN[22][26][27]
MMCM_DRP[3] bit 7MAIN[17][27][36]MAIN[22][27][27]
MMCM_DRP[3] bit 8MAIN[17][26][35]MAIN[22][26][28]
MMCM_DRP[3] bit 9MAIN[17][27][35]MAIN[22][27][28]
MMCM_DRP[3] bit 10MAIN[17][26][34]MAIN[22][26][29]
MMCM_DRP[3] bit 11MAIN[17][27][34]MAIN[22][27][29]
MMCM_DRP[3] bit 12MAIN[17][26][33]MAIN[22][26][30]
MMCM_DRP[3] bit 13MAIN[17][27][33]MAIN[22][27][30]
MMCM_DRP[3] bit 14MAIN[17][26][32]MAIN[22][26][31]
MMCM_DRP[3] bit 15MAIN[17][27][32]MAIN[22][27][31]
MMCM_DRP[4] bit 0MAIN[17][26][31]MAIN[22][26][32]
MMCM_DRP[4] bit 1MAIN[17][27][31]MAIN[22][27][32]
MMCM_DRP[4] bit 2MAIN[17][26][30]MAIN[22][26][33]
MMCM_DRP[4] bit 3MAIN[17][27][30]MAIN[22][27][33]
MMCM_DRP[4] bit 4MAIN[17][26][29]MAIN[22][26][34]
MMCM_DRP[4] bit 5MAIN[17][27][29]MAIN[22][27][34]
MMCM_DRP[4] bit 6MAIN[17][26][28]MAIN[22][26][35]
MMCM_DRP[4] bit 7MAIN[17][27][28]MAIN[22][27][35]
MMCM_DRP[4] bit 8MAIN[17][26][27]MAIN[22][26][36]
MMCM_DRP[4] bit 9MAIN[17][27][27]MAIN[22][27][36]
MMCM_DRP[4] bit 10MAIN[17][26][26]MAIN[22][26][37]
MMCM_DRP[4] bit 11MAIN[17][27][26]MAIN[22][27][37]
MMCM_DRP[4] bit 12MAIN[17][26][25]MAIN[22][26][38]
MMCM_DRP[4] bit 13MAIN[17][27][25]MAIN[22][27][38]
MMCM_DRP[4] bit 14MAIN[17][26][24]MAIN[22][26][39]
MMCM_DRP[4] bit 15MAIN[17][27][24]MAIN[22][27][39]
MMCM_DRP[5] bit 0MAIN[17][26][23]MAIN[22][26][40]
MMCM_DRP[5] bit 1MAIN[17][27][23]MAIN[22][27][40]
MMCM_DRP[5] bit 2MAIN[17][26][22]MAIN[22][26][41]
MMCM_DRP[5] bit 3MAIN[17][27][22]MAIN[22][27][41]
MMCM_DRP[5] bit 4MAIN[17][26][21]MAIN[22][26][42]
MMCM_DRP[5] bit 5MAIN[17][27][21]MAIN[22][27][42]
MMCM_DRP[5] bit 6MAIN[17][26][20]MAIN[22][26][43]
MMCM_DRP[5] bit 7MAIN[17][27][20]MAIN[22][27][43]
MMCM_DRP[5] bit 8MAIN[17][26][19]MAIN[22][26][44]
MMCM_DRP[5] bit 9MAIN[17][27][19]MAIN[22][27][44]
MMCM_DRP[5] bit 10MAIN[17][26][18]MAIN[22][26][45]
MMCM_DRP[5] bit 11MAIN[17][27][18]MAIN[22][27][45]
MMCM_DRP[5] bit 12MAIN[17][26][17]MAIN[22][26][46]
MMCM_DRP[5] bit 13MAIN[17][27][17]MAIN[22][27][46]
MMCM_DRP[5] bit 14MAIN[17][26][16]MAIN[22][26][47]
MMCM_DRP[5] bit 15MAIN[17][27][16]MAIN[22][27][47]
MMCM_DRP[6] bit 0MAIN[17][26][15]MAIN[22][26][48]
MMCM_DRP[6] bit 1MAIN[17][27][15]MAIN[22][27][48]
MMCM_DRP[6] bit 2MAIN[17][26][14]MAIN[22][26][49]
MMCM_DRP[6] bit 3MAIN[17][27][14]MAIN[22][27][49]
MMCM_DRP[6] bit 4MAIN[17][26][13]MAIN[22][26][50]
MMCM_DRP[6] bit 5MAIN[17][27][13]MAIN[22][27][50]
MMCM_DRP[6] bit 6MAIN[17][26][12]MAIN[22][26][51]
MMCM_DRP[6] bit 7MAIN[17][27][12]MAIN[22][27][51]
MMCM_DRP[6] bit 8MAIN[17][26][11]MAIN[22][26][52]
MMCM_DRP[6] bit 9MAIN[17][27][11]MAIN[22][27][52]
MMCM_DRP[6] bit 10MAIN[17][26][10]MAIN[22][26][53]
MMCM_DRP[6] bit 11MAIN[17][27][10]MAIN[22][27][53]
MMCM_DRP[6] bit 12MAIN[17][26][9]MAIN[22][26][54]
MMCM_DRP[6] bit 13MAIN[17][27][9]MAIN[22][27][54]
MMCM_DRP[6] bit 14MAIN[17][26][8]MAIN[22][26][55]
MMCM_DRP[6] bit 15MAIN[17][27][8]MAIN[22][27][55]
MMCM_DRP[7] bit 0MAIN[17][26][7]MAIN[22][26][56]
MMCM_DRP[7] bit 1MAIN[17][27][7]MAIN[22][27][56]
MMCM_DRP[7] bit 2MAIN[17][26][6]MAIN[22][26][57]
MMCM_DRP[7] bit 3MAIN[17][27][6]MAIN[22][27][57]
MMCM_DRP[7] bit 4MAIN[17][26][5]MAIN[22][26][58]
MMCM_DRP[7] bit 5MAIN[17][27][5]MAIN[22][27][58]
MMCM_DRP[7] bit 6MAIN[17][26][4]MAIN[22][26][59]
MMCM_DRP[7] bit 7MAIN[17][27][4]MAIN[22][27][59]
MMCM_DRP[7] bit 8MAIN[17][26][3]MAIN[22][26][60]
MMCM_DRP[7] bit 9MAIN[17][27][3]MAIN[22][27][60]
MMCM_DRP[7] bit 10MAIN[17][26][2]MAIN[22][26][61]
MMCM_DRP[7] bit 11MAIN[17][27][2]MAIN[22][27][61]
MMCM_DRP[7] bit 12MAIN[17][26][1]MAIN[22][26][62]
MMCM_DRP[7] bit 13MAIN[17][27][1]MAIN[22][27][62]
MMCM_DRP[7] bit 14MAIN[17][26][0]MAIN[22][26][63]
MMCM_DRP[7] bit 15MAIN[17][27][0]MAIN[22][27][63]
MMCM_DRP[8] bit 0MAIN[16][26][63]MAIN[23][26][0]
MMCM_DRP[8] bit 1MAIN[16][27][63]MAIN[23][27][0]
MMCM_DRP[8] bit 2MAIN[16][26][62]MAIN[23][26][1]
MMCM_DRP[8] bit 3MAIN[16][27][62]MAIN[23][27][1]
MMCM_DRP[8] bit 4MAIN[16][26][61]MAIN[23][26][2]
MMCM_DRP[8] bit 5MAIN[16][27][61]MAIN[23][27][2]
MMCM_DRP[8] bit 6MAIN[16][26][60]MAIN[23][26][3]
MMCM_DRP[8] bit 7MAIN[16][27][60]MAIN[23][27][3]
MMCM_DRP[8] bit 8MAIN[16][26][59]MAIN[23][26][4]
MMCM_DRP[8] bit 9MAIN[16][27][59]MAIN[23][27][4]
MMCM_DRP[8] bit 10MAIN[16][26][58]MAIN[23][26][5]
MMCM_DRP[8] bit 11MAIN[16][27][58]MAIN[23][27][5]
MMCM_DRP[8] bit 12MAIN[16][26][57]MAIN[23][26][6]
MMCM_DRP[8] bit 13MAIN[16][27][57]MAIN[23][27][6]
MMCM_DRP[8] bit 14MAIN[16][26][56]MAIN[23][26][7]
MMCM_DRP[8] bit 15MAIN[16][27][56]MAIN[23][27][7]
MMCM_DRP[9] bit 0MAIN[16][26][55]MAIN[23][26][8]
MMCM_DRP[9] bit 1MAIN[16][27][55]MAIN[23][27][8]
MMCM_DRP[9] bit 2MAIN[16][26][54]MAIN[23][26][9]
MMCM_DRP[9] bit 3MAIN[16][27][54]MAIN[23][27][9]
MMCM_DRP[9] bit 4MAIN[16][26][53]MAIN[23][26][10]
MMCM_DRP[9] bit 5MAIN[16][27][53]MAIN[23][27][10]
MMCM_DRP[9] bit 6MAIN[16][26][52]MAIN[23][26][11]
MMCM_DRP[9] bit 7MAIN[16][27][52]MAIN[23][27][11]
MMCM_DRP[9] bit 8MAIN[16][26][51]MAIN[23][26][12]
MMCM_DRP[9] bit 9MAIN[16][27][51]MAIN[23][27][12]
MMCM_DRP[9] bit 10MAIN[16][26][50]MAIN[23][26][13]
MMCM_DRP[9] bit 11MAIN[16][27][50]MAIN[23][27][13]
MMCM_DRP[9] bit 12MAIN[16][26][49]MAIN[23][26][14]
MMCM_DRP[9] bit 13MAIN[16][27][49]MAIN[23][27][14]
MMCM_DRP[9] bit 14MAIN[16][26][48]MAIN[23][26][15]
MMCM_DRP[9] bit 15MAIN[16][27][48]MAIN[23][27][15]
MMCM_DRP[10] bit 0MAIN[16][26][47]MAIN[23][26][16]
MMCM_DRP[10] bit 1MAIN[16][27][47]MAIN[23][27][16]
MMCM_DRP[10] bit 2MAIN[16][26][46]MAIN[23][26][17]
MMCM_DRP[10] bit 3MAIN[16][27][46]MAIN[23][27][17]
MMCM_DRP[10] bit 4MAIN[16][26][45]MAIN[23][26][18]
MMCM_DRP[10] bit 5MAIN[16][27][45]MAIN[23][27][18]
MMCM_DRP[10] bit 6MAIN[16][26][44]MAIN[23][26][19]
MMCM_DRP[10] bit 7MAIN[16][27][44]MAIN[23][27][19]
MMCM_DRP[10] bit 8MAIN[16][26][43]MAIN[23][26][20]
MMCM_DRP[10] bit 9MAIN[16][27][43]MAIN[23][27][20]
MMCM_DRP[10] bit 10MAIN[16][26][42]MAIN[23][26][21]
MMCM_DRP[10] bit 11MAIN[16][27][42]MAIN[23][27][21]
MMCM_DRP[10] bit 12MAIN[16][26][41]MAIN[23][26][22]
MMCM_DRP[10] bit 13MAIN[16][27][41]MAIN[23][27][22]
MMCM_DRP[10] bit 14MAIN[16][26][40]MAIN[23][26][23]
MMCM_DRP[10] bit 15MAIN[16][27][40]MAIN[23][27][23]
MMCM_DRP[11] bit 0MAIN[16][26][39]MAIN[23][26][24]
MMCM_DRP[11] bit 1MAIN[16][27][39]MAIN[23][27][24]
MMCM_DRP[11] bit 2MAIN[16][26][38]MAIN[23][26][25]
MMCM_DRP[11] bit 3MAIN[16][27][38]MAIN[23][27][25]
MMCM_DRP[11] bit 4MAIN[16][26][37]MAIN[23][26][26]
MMCM_DRP[11] bit 5MAIN[16][27][37]MAIN[23][27][26]
MMCM_DRP[11] bit 6MAIN[16][26][36]MAIN[23][26][27]
MMCM_DRP[11] bit 7MAIN[16][27][36]MAIN[23][27][27]
MMCM_DRP[11] bit 8MAIN[16][26][35]MAIN[23][26][28]
MMCM_DRP[11] bit 9MAIN[16][27][35]MAIN[23][27][28]
MMCM_DRP[11] bit 10MAIN[16][26][34]MAIN[23][26][29]
MMCM_DRP[11] bit 11MAIN[16][27][34]MAIN[23][27][29]
MMCM_DRP[11] bit 12MAIN[16][26][33]MAIN[23][26][30]
MMCM_DRP[11] bit 13MAIN[16][27][33]MAIN[23][27][30]
MMCM_DRP[11] bit 14MAIN[16][26][32]MAIN[23][26][31]
MMCM_DRP[11] bit 15MAIN[16][27][32]MAIN[23][27][31]
MMCM_DRP[12] bit 0MAIN[16][26][31]MAIN[23][26][32]
MMCM_DRP[12] bit 1MAIN[16][27][31]MAIN[23][27][32]
MMCM_DRP[12] bit 2MAIN[16][26][30]MAIN[23][26][33]
MMCM_DRP[12] bit 3MAIN[16][27][30]MAIN[23][27][33]
MMCM_DRP[12] bit 4MAIN[16][26][29]MAIN[23][26][34]
MMCM_DRP[12] bit 5MAIN[16][27][29]MAIN[23][27][34]
MMCM_DRP[12] bit 6MAIN[16][26][28]MAIN[23][26][35]
MMCM_DRP[12] bit 7MAIN[16][27][28]MAIN[23][27][35]
MMCM_DRP[12] bit 8MAIN[16][26][27]MAIN[23][26][36]
MMCM_DRP[12] bit 9MAIN[16][27][27]MAIN[23][27][36]
MMCM_DRP[12] bit 10MAIN[16][26][26]MAIN[23][26][37]
MMCM_DRP[12] bit 11MAIN[16][27][26]MAIN[23][27][37]
MMCM_DRP[12] bit 12MAIN[16][26][25]MAIN[23][26][38]
MMCM_DRP[12] bit 13MAIN[16][27][25]MAIN[23][27][38]
MMCM_DRP[12] bit 14MAIN[16][26][24]MAIN[23][26][39]
MMCM_DRP[12] bit 15MAIN[16][27][24]MAIN[23][27][39]
MMCM_DRP[13] bit 0MAIN[16][26][23]MAIN[23][26][40]
MMCM_DRP[13] bit 1MAIN[16][27][23]MAIN[23][27][40]
MMCM_DRP[13] bit 2MAIN[16][26][22]MAIN[23][26][41]
MMCM_DRP[13] bit 3MAIN[16][27][22]MAIN[23][27][41]
MMCM_DRP[13] bit 4MAIN[16][26][21]MAIN[23][26][42]
MMCM_DRP[13] bit 5MAIN[16][27][21]MAIN[23][27][42]
MMCM_DRP[13] bit 6MAIN[16][26][20]MAIN[23][26][43]
MMCM_DRP[13] bit 7MAIN[16][27][20]MAIN[23][27][43]
MMCM_DRP[13] bit 8MAIN[16][26][19]MAIN[23][26][44]
MMCM_DRP[13] bit 9MAIN[16][27][19]MAIN[23][27][44]
MMCM_DRP[13] bit 10MAIN[16][26][18]MAIN[23][26][45]
MMCM_DRP[13] bit 11MAIN[16][27][18]MAIN[23][27][45]
MMCM_DRP[13] bit 12MAIN[16][26][17]MAIN[23][26][46]
MMCM_DRP[13] bit 13MAIN[16][27][17]MAIN[23][27][46]
MMCM_DRP[13] bit 14MAIN[16][26][16]MAIN[23][26][47]
MMCM_DRP[13] bit 15MAIN[16][27][16]MAIN[23][27][47]
MMCM_DRP[14] bit 0MAIN[16][26][15]MAIN[23][26][48]
MMCM_DRP[14] bit 1MAIN[16][27][15]MAIN[23][27][48]
MMCM_DRP[14] bit 2MAIN[16][26][14]MAIN[23][26][49]
MMCM_DRP[14] bit 3MAIN[16][27][14]MAIN[23][27][49]
MMCM_DRP[14] bit 4MAIN[16][26][13]MAIN[23][26][50]
MMCM_DRP[14] bit 5MAIN[16][27][13]MAIN[23][27][50]
MMCM_DRP[14] bit 6MAIN[16][26][12]MAIN[23][26][51]
MMCM_DRP[14] bit 7MAIN[16][27][12]MAIN[23][27][51]
MMCM_DRP[14] bit 8MAIN[16][26][11]MAIN[23][26][52]
MMCM_DRP[14] bit 9MAIN[16][27][11]MAIN[23][27][52]
MMCM_DRP[14] bit 10MAIN[16][26][10]MAIN[23][26][53]
MMCM_DRP[14] bit 11MAIN[16][27][10]MAIN[23][27][53]
MMCM_DRP[14] bit 12MAIN[16][26][9]MAIN[23][26][54]
MMCM_DRP[14] bit 13MAIN[16][27][9]MAIN[23][27][54]
MMCM_DRP[14] bit 14MAIN[16][26][8]MAIN[23][26][55]
MMCM_DRP[14] bit 15MAIN[16][27][8]MAIN[23][27][55]
MMCM_DRP[15] bit 0MAIN[16][26][7]MAIN[23][26][56]
MMCM_DRP[15] bit 1MAIN[16][27][7]MAIN[23][27][56]
MMCM_DRP[15] bit 2MAIN[16][26][6]MAIN[23][26][57]
MMCM_DRP[15] bit 3MAIN[16][27][6]MAIN[23][27][57]
MMCM_DRP[15] bit 4MAIN[16][26][5]MAIN[23][26][58]
MMCM_DRP[15] bit 5MAIN[16][27][5]MAIN[23][27][58]
MMCM_DRP[15] bit 6MAIN[16][26][4]MAIN[23][26][59]
MMCM_DRP[15] bit 7MAIN[16][27][4]MAIN[23][27][59]
MMCM_DRP[15] bit 8MAIN[16][26][3]MAIN[23][26][60]
MMCM_DRP[15] bit 9MAIN[16][27][3]MAIN[23][27][60]
MMCM_DRP[15] bit 10MAIN[16][26][2]MAIN[23][26][61]
MMCM_DRP[15] bit 11MAIN[16][27][2]MAIN[23][27][61]
MMCM_DRP[15] bit 12MAIN[16][26][1]MAIN[23][26][62]
MMCM_DRP[15] bit 13MAIN[16][27][1]MAIN[23][27][62]
MMCM_DRP[15] bit 14MAIN[16][26][0]MAIN[23][26][63]
MMCM_DRP[15] bit 15MAIN[16][27][0]MAIN[23][27][63]
MMCM_DRP[16] bit 0MAIN[15][26][63]MAIN[24][26][0]
MMCM_DRP[16] bit 1MAIN[15][27][63]MAIN[24][27][0]
MMCM_DRP[16] bit 2MAIN[15][26][62]MAIN[24][26][1]
MMCM_DRP[16] bit 3MAIN[15][27][62]MAIN[24][27][1]
MMCM_DRP[16] bit 4MAIN[15][26][61]MAIN[24][26][2]
MMCM_DRP[16] bit 5MAIN[15][27][61]MAIN[24][27][2]
MMCM_DRP[16] bit 6MAIN[15][26][60]MAIN[24][26][3]
MMCM_DRP[16] bit 7MAIN[15][27][60]MAIN[24][27][3]
MMCM_DRP[16] bit 8MAIN[15][26][59]MAIN[24][26][4]
MMCM_DRP[16] bit 9MAIN[15][27][59]MAIN[24][27][4]
MMCM_DRP[16] bit 10MAIN[15][26][58]MAIN[24][26][5]
MMCM_DRP[16] bit 11MAIN[15][27][58]MAIN[24][27][5]
MMCM_DRP[16] bit 12MAIN[15][26][57]MAIN[24][26][6]
MMCM_DRP[16] bit 13MAIN[15][27][57]MAIN[24][27][6]
MMCM_DRP[16] bit 14MAIN[15][26][56]MAIN[24][26][7]
MMCM_DRP[16] bit 15MAIN[15][27][56]MAIN[24][27][7]
MMCM_DRP[17] bit 0MAIN[15][26][55]MAIN[24][26][8]
MMCM_DRP[17] bit 1MAIN[15][27][55]MAIN[24][27][8]
MMCM_DRP[17] bit 2MAIN[15][26][54]MAIN[24][26][9]
MMCM_DRP[17] bit 3MAIN[15][27][54]MAIN[24][27][9]
MMCM_DRP[17] bit 4MAIN[15][26][53]MAIN[24][26][10]
MMCM_DRP[17] bit 5MAIN[15][27][53]MAIN[24][27][10]
MMCM_DRP[17] bit 6MAIN[15][26][52]MAIN[24][26][11]
MMCM_DRP[17] bit 7MAIN[15][27][52]MAIN[24][27][11]
MMCM_DRP[17] bit 8MAIN[15][26][51]MAIN[24][26][12]
MMCM_DRP[17] bit 9MAIN[15][27][51]MAIN[24][27][12]
MMCM_DRP[17] bit 10MAIN[15][26][50]MAIN[24][26][13]
MMCM_DRP[17] bit 11MAIN[15][27][50]MAIN[24][27][13]
MMCM_DRP[17] bit 12MAIN[15][26][49]MAIN[24][26][14]
MMCM_DRP[17] bit 13MAIN[15][27][49]MAIN[24][27][14]
MMCM_DRP[17] bit 14MAIN[15][26][48]MAIN[24][26][15]
MMCM_DRP[17] bit 15MAIN[15][27][48]MAIN[24][27][15]
MMCM_DRP[18] bit 0MAIN[15][26][47]MAIN[24][26][16]
MMCM_DRP[18] bit 1MAIN[15][27][47]MAIN[24][27][16]
MMCM_DRP[18] bit 2MAIN[15][26][46]MAIN[24][26][17]
MMCM_DRP[18] bit 3MAIN[15][27][46]MAIN[24][27][17]
MMCM_DRP[18] bit 4MAIN[15][26][45]MAIN[24][26][18]
MMCM_DRP[18] bit 5MAIN[15][27][45]MAIN[24][27][18]
MMCM_DRP[18] bit 6MAIN[15][26][44]MAIN[24][26][19]
MMCM_DRP[18] bit 7MAIN[15][27][44]MAIN[24][27][19]
MMCM_DRP[18] bit 8MAIN[15][26][43]MAIN[24][26][20]
MMCM_DRP[18] bit 9MAIN[15][27][43]MAIN[24][27][20]
MMCM_DRP[18] bit 10MAIN[15][26][42]MAIN[24][26][21]
MMCM_DRP[18] bit 11MAIN[15][27][42]MAIN[24][27][21]
MMCM_DRP[18] bit 12MAIN[15][26][41]MAIN[24][26][22]
MMCM_DRP[18] bit 13MAIN[15][27][41]MAIN[24][27][22]
MMCM_DRP[18] bit 14MAIN[15][26][40]MAIN[24][26][23]
MMCM_DRP[18] bit 15MAIN[15][27][40]MAIN[24][27][23]
MMCM_DRP[19] bit 0MAIN[15][26][39]MAIN[24][26][24]
MMCM_DRP[19] bit 1MAIN[15][27][39]MAIN[24][27][24]
MMCM_DRP[19] bit 2MAIN[15][26][38]MAIN[24][26][25]
MMCM_DRP[19] bit 3MAIN[15][27][38]MAIN[24][27][25]
MMCM_DRP[19] bit 4MAIN[15][26][37]MAIN[24][26][26]
MMCM_DRP[19] bit 5MAIN[15][27][37]MAIN[24][27][26]
MMCM_DRP[19] bit 6MAIN[15][26][36]MAIN[24][26][27]
MMCM_DRP[19] bit 7MAIN[15][27][36]MAIN[24][27][27]
MMCM_DRP[19] bit 8MAIN[15][26][35]MAIN[24][26][28]
MMCM_DRP[19] bit 9MAIN[15][27][35]MAIN[24][27][28]
MMCM_DRP[19] bit 10MAIN[15][26][34]MAIN[24][26][29]
MMCM_DRP[19] bit 11MAIN[15][27][34]MAIN[24][27][29]
MMCM_DRP[19] bit 12MAIN[15][26][33]MAIN[24][26][30]
MMCM_DRP[19] bit 13MAIN[15][27][33]MAIN[24][27][30]
MMCM_DRP[19] bit 14MAIN[15][26][32]MAIN[24][26][31]
MMCM_DRP[19] bit 15MAIN[15][27][32]MAIN[24][27][31]
MMCM_DRP[20] bit 0MAIN[15][26][31]MAIN[24][26][32]
MMCM_DRP[20] bit 1MAIN[15][27][31]MAIN[24][27][32]
MMCM_DRP[20] bit 2MAIN[15][26][30]MAIN[24][26][33]
MMCM_DRP[20] bit 3MAIN[15][27][30]MAIN[24][27][33]
MMCM_DRP[20] bit 4MAIN[15][26][29]MAIN[24][26][34]
MMCM_DRP[20] bit 5MAIN[15][27][29]MAIN[24][27][34]
MMCM_DRP[20] bit 6MAIN[15][26][28]MAIN[24][26][35]
MMCM_DRP[20] bit 7MAIN[15][27][28]MAIN[24][27][35]
MMCM_DRP[20] bit 8MAIN[15][26][27]MAIN[24][26][36]
MMCM_DRP[20] bit 9MAIN[15][27][27]MAIN[24][27][36]
MMCM_DRP[20] bit 10MAIN[15][26][26]MAIN[24][26][37]
MMCM_DRP[20] bit 11MAIN[15][27][26]MAIN[24][27][37]
MMCM_DRP[20] bit 12MAIN[15][26][25]MAIN[24][26][38]
MMCM_DRP[20] bit 13MAIN[15][27][25]MAIN[24][27][38]
MMCM_DRP[20] bit 14MAIN[15][26][24]MAIN[24][26][39]
MMCM_DRP[20] bit 15MAIN[15][27][24]MAIN[24][27][39]
MMCM_DRP[21] bit 0MAIN[15][26][23]MAIN[24][26][40]
MMCM_DRP[21] bit 1MAIN[15][27][23]MAIN[24][27][40]
MMCM_DRP[21] bit 2MAIN[15][26][22]MAIN[24][26][41]
MMCM_DRP[21] bit 3MAIN[15][27][22]MAIN[24][27][41]
MMCM_DRP[21] bit 4MAIN[15][26][21]MAIN[24][26][42]
MMCM_DRP[21] bit 5MAIN[15][27][21]MAIN[24][27][42]
MMCM_DRP[21] bit 6MAIN[15][26][20]MAIN[24][26][43]
MMCM_DRP[21] bit 7MAIN[15][27][20]MAIN[24][27][43]
MMCM_DRP[21] bit 8MAIN[15][26][19]MAIN[24][26][44]
MMCM_DRP[21] bit 9MAIN[15][27][19]MAIN[24][27][44]
MMCM_DRP[21] bit 10MAIN[15][26][18]MAIN[24][26][45]
MMCM_DRP[21] bit 11MAIN[15][27][18]MAIN[24][27][45]
MMCM_DRP[21] bit 12MAIN[15][26][17]MAIN[24][26][46]
MMCM_DRP[21] bit 13MAIN[15][27][17]MAIN[24][27][46]
MMCM_DRP[21] bit 14MAIN[15][26][16]MAIN[24][26][47]
MMCM_DRP[21] bit 15MAIN[15][27][16]MAIN[24][27][47]
MMCM_DRP[22] bit 0MAIN[15][26][15]MAIN[24][26][48]
MMCM_DRP[22] bit 1MAIN[15][27][15]MAIN[24][27][48]
MMCM_DRP[22] bit 2MAIN[15][26][14]MAIN[24][26][49]
MMCM_DRP[22] bit 3MAIN[15][27][14]MAIN[24][27][49]
MMCM_DRP[22] bit 4MAIN[15][26][13]MAIN[24][26][50]
MMCM_DRP[22] bit 5MAIN[15][27][13]MAIN[24][27][50]
MMCM_DRP[22] bit 6MAIN[15][26][12]MAIN[24][26][51]
MMCM_DRP[22] bit 7MAIN[15][27][12]MAIN[24][27][51]
MMCM_DRP[22] bit 8MAIN[15][26][11]MAIN[24][26][52]
MMCM_DRP[22] bit 9MAIN[15][27][11]MAIN[24][27][52]
MMCM_DRP[22] bit 10MAIN[15][26][10]MAIN[24][26][53]
MMCM_DRP[22] bit 11MAIN[15][27][10]MAIN[24][27][53]
MMCM_DRP[22] bit 12MAIN[15][26][9]MAIN[24][26][54]
MMCM_DRP[22] bit 13MAIN[15][27][9]MAIN[24][27][54]
MMCM_DRP[22] bit 14MAIN[15][26][8]MAIN[24][26][55]
MMCM_DRP[22] bit 15MAIN[15][27][8]MAIN[24][27][55]
MMCM_DRP[23] bit 0MAIN[15][26][7]MAIN[24][26][56]
MMCM_DRP[23] bit 1MAIN[15][27][7]MAIN[24][27][56]
MMCM_DRP[23] bit 2MAIN[15][26][6]MAIN[24][26][57]
MMCM_DRP[23] bit 3MAIN[15][27][6]MAIN[24][27][57]
MMCM_DRP[23] bit 4MAIN[15][26][5]MAIN[24][26][58]
MMCM_DRP[23] bit 5MAIN[15][27][5]MAIN[24][27][58]
MMCM_DRP[23] bit 6MAIN[15][26][4]MAIN[24][26][59]
MMCM_DRP[23] bit 7MAIN[15][27][4]MAIN[24][27][59]
MMCM_DRP[23] bit 8MAIN[15][26][3]MAIN[24][26][60]
MMCM_DRP[23] bit 9MAIN[15][27][3]MAIN[24][27][60]
MMCM_DRP[23] bit 10MAIN[15][26][2]MAIN[24][26][61]
MMCM_DRP[23] bit 11MAIN[15][27][2]MAIN[24][27][61]
MMCM_DRP[23] bit 12MAIN[15][26][1]MAIN[24][26][62]
MMCM_DRP[23] bit 13MAIN[15][27][1]MAIN[24][27][62]
MMCM_DRP[23] bit 14MAIN[15][26][0]MAIN[24][26][63]
MMCM_DRP[23] bit 15MAIN[15][27][0]MAIN[24][27][63]
MMCM_DRP[24] bit 0MAIN[14][26][63]MAIN[25][26][0]
MMCM_DRP[24] bit 1MAIN[14][27][63]MAIN[25][27][0]
MMCM_DRP[24] bit 2MAIN[14][26][62]MAIN[25][26][1]
MMCM_DRP[24] bit 3MAIN[14][27][62]MAIN[25][27][1]
MMCM_DRP[24] bit 4MAIN[14][26][61]MAIN[25][26][2]
MMCM_DRP[24] bit 5MAIN[14][27][61]MAIN[25][27][2]
MMCM_DRP[24] bit 6MAIN[14][26][60]MAIN[25][26][3]
MMCM_DRP[24] bit 7MAIN[14][27][60]MAIN[25][27][3]
MMCM_DRP[24] bit 8MAIN[14][26][59]MAIN[25][26][4]
MMCM_DRP[24] bit 9MAIN[14][27][59]MAIN[25][27][4]
MMCM_DRP[24] bit 10MAIN[14][26][58]MAIN[25][26][5]
MMCM_DRP[24] bit 11MAIN[14][27][58]MAIN[25][27][5]
MMCM_DRP[24] bit 12MAIN[14][26][57]MAIN[25][26][6]
MMCM_DRP[24] bit 13MAIN[14][27][57]MAIN[25][27][6]
MMCM_DRP[24] bit 14MAIN[14][26][56]MAIN[25][26][7]
MMCM_DRP[24] bit 15MAIN[14][27][56]MAIN[25][27][7]
MMCM_DRP[25] bit 0MAIN[14][26][55]MAIN[25][26][8]
MMCM_DRP[25] bit 1MAIN[14][27][55]MAIN[25][27][8]
MMCM_DRP[25] bit 2MAIN[14][26][54]MAIN[25][26][9]
MMCM_DRP[25] bit 3MAIN[14][27][54]MAIN[25][27][9]
MMCM_DRP[25] bit 4MAIN[14][26][53]MAIN[25][26][10]
MMCM_DRP[25] bit 5MAIN[14][27][53]MAIN[25][27][10]
MMCM_DRP[25] bit 6MAIN[14][26][52]MAIN[25][26][11]
MMCM_DRP[25] bit 7MAIN[14][27][52]MAIN[25][27][11]
MMCM_DRP[25] bit 8MAIN[14][26][51]MAIN[25][26][12]
MMCM_DRP[25] bit 9MAIN[14][27][51]MAIN[25][27][12]
MMCM_DRP[25] bit 10MAIN[14][26][50]MAIN[25][26][13]
MMCM_DRP[25] bit 11MAIN[14][27][50]MAIN[25][27][13]
MMCM_DRP[25] bit 12MAIN[14][26][49]MAIN[25][26][14]
MMCM_DRP[25] bit 13MAIN[14][27][49]MAIN[25][27][14]
MMCM_DRP[25] bit 14MAIN[14][26][48]MAIN[25][26][15]
MMCM_DRP[25] bit 15MAIN[14][27][48]MAIN[25][27][15]
MMCM_DRP[26] bit 0MAIN[14][26][47]MAIN[25][26][16]
MMCM_DRP[26] bit 1MAIN[14][27][47]MAIN[25][27][16]
MMCM_DRP[26] bit 2MAIN[14][26][46]MAIN[25][26][17]
MMCM_DRP[26] bit 3MAIN[14][27][46]MAIN[25][27][17]
MMCM_DRP[26] bit 4MAIN[14][26][45]MAIN[25][26][18]
MMCM_DRP[26] bit 5MAIN[14][27][45]MAIN[25][27][18]
MMCM_DRP[26] bit 6MAIN[14][26][44]MAIN[25][26][19]
MMCM_DRP[26] bit 7MAIN[14][27][44]MAIN[25][27][19]
MMCM_DRP[26] bit 8MAIN[14][26][43]MAIN[25][26][20]
MMCM_DRP[26] bit 9MAIN[14][27][43]MAIN[25][27][20]
MMCM_DRP[26] bit 10MAIN[14][26][42]MAIN[25][26][21]
MMCM_DRP[26] bit 11MAIN[14][27][42]MAIN[25][27][21]
MMCM_DRP[26] bit 12MAIN[14][26][41]MAIN[25][26][22]
MMCM_DRP[26] bit 13MAIN[14][27][41]MAIN[25][27][22]
MMCM_DRP[26] bit 14MAIN[14][26][40]MAIN[25][26][23]
MMCM_DRP[26] bit 15MAIN[14][27][40]MAIN[25][27][23]
MMCM_DRP[27] bit 0MAIN[14][26][39]MAIN[25][26][24]
MMCM_DRP[27] bit 1MAIN[14][27][39]MAIN[25][27][24]
MMCM_DRP[27] bit 2MAIN[14][26][38]MAIN[25][26][25]
MMCM_DRP[27] bit 3MAIN[14][27][38]MAIN[25][27][25]
MMCM_DRP[27] bit 4MAIN[14][26][37]MAIN[25][26][26]
MMCM_DRP[27] bit 5MAIN[14][27][37]MAIN[25][27][26]
MMCM_DRP[27] bit 6MAIN[14][26][36]MAIN[25][26][27]
MMCM_DRP[27] bit 7MAIN[14][27][36]MAIN[25][27][27]
MMCM_DRP[27] bit 8MAIN[14][26][35]MAIN[25][26][28]
MMCM_DRP[27] bit 9MAIN[14][27][35]MAIN[25][27][28]
MMCM_DRP[27] bit 10MAIN[14][26][34]MAIN[25][26][29]
MMCM_DRP[27] bit 11MAIN[14][27][34]MAIN[25][27][29]
MMCM_DRP[27] bit 12MAIN[14][26][33]MAIN[25][26][30]
MMCM_DRP[27] bit 13MAIN[14][27][33]MAIN[25][27][30]
MMCM_DRP[27] bit 14MAIN[14][26][32]MAIN[25][26][31]
MMCM_DRP[27] bit 15MAIN[14][27][32]MAIN[25][27][31]
MMCM_DRP[28] bit 0MAIN[14][26][31]MAIN[25][26][32]
MMCM_DRP[28] bit 1MAIN[14][27][31]MAIN[25][27][32]
MMCM_DRP[28] bit 2MAIN[14][26][30]MAIN[25][26][33]
MMCM_DRP[28] bit 3MAIN[14][27][30]MAIN[25][27][33]
MMCM_DRP[28] bit 4MAIN[14][26][29]MAIN[25][26][34]
MMCM_DRP[28] bit 5MAIN[14][27][29]MAIN[25][27][34]
MMCM_DRP[28] bit 6MAIN[14][26][28]MAIN[25][26][35]
MMCM_DRP[28] bit 7MAIN[14][27][28]MAIN[25][27][35]
MMCM_DRP[28] bit 8MAIN[14][26][27]MAIN[25][26][36]
MMCM_DRP[28] bit 9MAIN[14][27][27]MAIN[25][27][36]
MMCM_DRP[28] bit 10MAIN[14][26][26]MAIN[25][26][37]
MMCM_DRP[28] bit 11MAIN[14][27][26]MAIN[25][27][37]
MMCM_DRP[28] bit 12MAIN[14][26][25]MAIN[25][26][38]
MMCM_DRP[28] bit 13MAIN[14][27][25]MAIN[25][27][38]
MMCM_DRP[28] bit 14MAIN[14][26][24]MAIN[25][26][39]
MMCM_DRP[28] bit 15MAIN[14][27][24]MAIN[25][27][39]
MMCM_DRP[29] bit 0MAIN[14][26][23]MAIN[25][26][40]
MMCM_DRP[29] bit 1MAIN[14][27][23]MAIN[25][27][40]
MMCM_DRP[29] bit 2MAIN[14][26][22]MAIN[25][26][41]
MMCM_DRP[29] bit 3MAIN[14][27][22]MAIN[25][27][41]
MMCM_DRP[29] bit 4MAIN[14][26][21]MAIN[25][26][42]
MMCM_DRP[29] bit 5MAIN[14][27][21]MAIN[25][27][42]
MMCM_DRP[29] bit 6MAIN[14][26][20]MAIN[25][26][43]
MMCM_DRP[29] bit 7MAIN[14][27][20]MAIN[25][27][43]
MMCM_DRP[29] bit 8MAIN[14][26][19]MAIN[25][26][44]
MMCM_DRP[29] bit 9MAIN[14][27][19]MAIN[25][27][44]
MMCM_DRP[29] bit 10MAIN[14][26][18]MAIN[25][26][45]
MMCM_DRP[29] bit 11MAIN[14][27][18]MAIN[25][27][45]
MMCM_DRP[29] bit 12MAIN[14][26][17]MAIN[25][26][46]
MMCM_DRP[29] bit 13MAIN[14][27][17]MAIN[25][27][46]
MMCM_DRP[29] bit 14MAIN[14][26][16]MAIN[25][26][47]
MMCM_DRP[29] bit 15MAIN[14][27][16]MAIN[25][27][47]
MMCM_DRP[30] bit 0MAIN[14][26][15]MAIN[25][26][48]
MMCM_DRP[30] bit 1MAIN[14][27][15]MAIN[25][27][48]
MMCM_DRP[30] bit 2MAIN[14][26][14]MAIN[25][26][49]
MMCM_DRP[30] bit 3MAIN[14][27][14]MAIN[25][27][49]
MMCM_DRP[30] bit 4MAIN[14][26][13]MAIN[25][26][50]
MMCM_DRP[30] bit 5MAIN[14][27][13]MAIN[25][27][50]
MMCM_DRP[30] bit 6MAIN[14][26][12]MAIN[25][26][51]
MMCM_DRP[30] bit 7MAIN[14][27][12]MAIN[25][27][51]
MMCM_DRP[30] bit 8MAIN[14][26][11]MAIN[25][26][52]
MMCM_DRP[30] bit 9MAIN[14][27][11]MAIN[25][27][52]
MMCM_DRP[30] bit 10MAIN[14][26][10]MAIN[25][26][53]
MMCM_DRP[30] bit 11MAIN[14][27][10]MAIN[25][27][53]
MMCM_DRP[30] bit 12MAIN[14][26][9]MAIN[25][26][54]
MMCM_DRP[30] bit 13MAIN[14][27][9]MAIN[25][27][54]
MMCM_DRP[30] bit 14MAIN[14][26][8]MAIN[25][26][55]
MMCM_DRP[30] bit 15MAIN[14][27][8]MAIN[25][27][55]
MMCM_DRP[31] bit 0MAIN[14][26][7]MAIN[25][26][56]
MMCM_DRP[31] bit 1MAIN[14][27][7]MAIN[25][27][56]
MMCM_DRP[31] bit 2MAIN[14][26][6]MAIN[25][26][57]
MMCM_DRP[31] bit 3MAIN[14][27][6]MAIN[25][27][57]
MMCM_DRP[31] bit 4MAIN[14][26][5]MAIN[25][26][58]
MMCM_DRP[31] bit 5MAIN[14][27][5]MAIN[25][27][58]
MMCM_DRP[31] bit 6MAIN[14][26][4]MAIN[25][26][59]
MMCM_DRP[31] bit 7MAIN[14][27][4]MAIN[25][27][59]
MMCM_DRP[31] bit 8MAIN[14][26][3]MAIN[25][26][60]
MMCM_DRP[31] bit 9MAIN[14][27][3]MAIN[25][27][60]
MMCM_DRP[31] bit 10MAIN[14][26][2]MAIN[25][26][61]
MMCM_DRP[31] bit 11MAIN[14][27][2]MAIN[25][27][61]
MMCM_DRP[31] bit 12MAIN[14][26][1]MAIN[25][26][62]
MMCM_DRP[31] bit 13MAIN[14][27][1]MAIN[25][27][62]
MMCM_DRP[31] bit 14MAIN[14][26][0]MAIN[25][26][63]
MMCM_DRP[31] bit 15MAIN[14][27][0]MAIN[25][27][63]
MMCM_DRP[32] bit 0MAIN[13][26][63]MAIN[26][26][0]
MMCM_DRP[32] bit 1MAIN[13][27][63]MAIN[26][27][0]
MMCM_DRP[32] bit 2MAIN[13][26][62]MAIN[26][26][1]
MMCM_DRP[32] bit 3MAIN[13][27][62]MAIN[26][27][1]
MMCM_DRP[32] bit 4MAIN[13][26][61]MAIN[26][26][2]
MMCM_DRP[32] bit 5MAIN[13][27][61]MAIN[26][27][2]
MMCM_DRP[32] bit 6MAIN[13][26][60]MAIN[26][26][3]
MMCM_DRP[32] bit 7MAIN[13][27][60]MAIN[26][27][3]
MMCM_DRP[32] bit 8MAIN[13][26][59]MAIN[26][26][4]
MMCM_DRP[32] bit 9MAIN[13][27][59]MAIN[26][27][4]
MMCM_DRP[32] bit 10MAIN[13][26][58]MAIN[26][26][5]
MMCM_DRP[32] bit 11MAIN[13][27][58]MAIN[26][27][5]
MMCM_DRP[32] bit 12MAIN[13][26][57]MAIN[26][26][6]
MMCM_DRP[32] bit 13MAIN[13][27][57]MAIN[26][27][6]
MMCM_DRP[32] bit 14MAIN[13][26][56]MAIN[26][26][7]
MMCM_DRP[32] bit 15MAIN[13][27][56]MAIN[26][27][7]
MMCM_DRP[33] bit 0MAIN[13][26][55]MAIN[26][26][8]
MMCM_DRP[33] bit 1MAIN[13][27][55]MAIN[26][27][8]
MMCM_DRP[33] bit 2MAIN[13][26][54]MAIN[26][26][9]
MMCM_DRP[33] bit 3MAIN[13][27][54]MAIN[26][27][9]
MMCM_DRP[33] bit 4MAIN[13][26][53]MAIN[26][26][10]
MMCM_DRP[33] bit 5MAIN[13][27][53]MAIN[26][27][10]
MMCM_DRP[33] bit 6MAIN[13][26][52]MAIN[26][26][11]
MMCM_DRP[33] bit 7MAIN[13][27][52]MAIN[26][27][11]
MMCM_DRP[33] bit 8MAIN[13][26][51]MAIN[26][26][12]
MMCM_DRP[33] bit 9MAIN[13][27][51]MAIN[26][27][12]
MMCM_DRP[33] bit 10MAIN[13][26][50]MAIN[26][26][13]
MMCM_DRP[33] bit 11MAIN[13][27][50]MAIN[26][27][13]
MMCM_DRP[33] bit 12MAIN[13][26][49]MAIN[26][26][14]
MMCM_DRP[33] bit 13MAIN[13][27][49]MAIN[26][27][14]
MMCM_DRP[33] bit 14MAIN[13][26][48]MAIN[26][26][15]
MMCM_DRP[33] bit 15MAIN[13][27][48]MAIN[26][27][15]
MMCM_DRP[34] bit 0MAIN[13][26][47]MAIN[26][26][16]
MMCM_DRP[34] bit 1MAIN[13][27][47]MAIN[26][27][16]
MMCM_DRP[34] bit 2MAIN[13][26][46]MAIN[26][26][17]
MMCM_DRP[34] bit 3MAIN[13][27][46]MAIN[26][27][17]
MMCM_DRP[34] bit 4MAIN[13][26][45]MAIN[26][26][18]
MMCM_DRP[34] bit 5MAIN[13][27][45]MAIN[26][27][18]
MMCM_DRP[34] bit 6MAIN[13][26][44]MAIN[26][26][19]
MMCM_DRP[34] bit 7MAIN[13][27][44]MAIN[26][27][19]
MMCM_DRP[34] bit 8MAIN[13][26][43]MAIN[26][26][20]
MMCM_DRP[34] bit 9MAIN[13][27][43]MAIN[26][27][20]
MMCM_DRP[34] bit 10MAIN[13][26][42]MAIN[26][26][21]
MMCM_DRP[34] bit 11MAIN[13][27][42]MAIN[26][27][21]
MMCM_DRP[34] bit 12MAIN[13][26][41]MAIN[26][26][22]
MMCM_DRP[34] bit 13MAIN[13][27][41]MAIN[26][27][22]
MMCM_DRP[34] bit 14MAIN[13][26][40]MAIN[26][26][23]
MMCM_DRP[34] bit 15MAIN[13][27][40]MAIN[26][27][23]
MMCM_DRP[35] bit 0MAIN[13][26][39]MAIN[26][26][24]
MMCM_DRP[35] bit 1MAIN[13][27][39]MAIN[26][27][24]
MMCM_DRP[35] bit 2MAIN[13][26][38]MAIN[26][26][25]
MMCM_DRP[35] bit 3MAIN[13][27][38]MAIN[26][27][25]
MMCM_DRP[35] bit 4MAIN[13][26][37]MAIN[26][26][26]
MMCM_DRP[35] bit 5MAIN[13][27][37]MAIN[26][27][26]
MMCM_DRP[35] bit 6MAIN[13][26][36]MAIN[26][26][27]
MMCM_DRP[35] bit 7MAIN[13][27][36]MAIN[26][27][27]
MMCM_DRP[35] bit 8MAIN[13][26][35]MAIN[26][26][28]
MMCM_DRP[35] bit 9MAIN[13][27][35]MAIN[26][27][28]
MMCM_DRP[35] bit 10MAIN[13][26][34]MAIN[26][26][29]
MMCM_DRP[35] bit 11MAIN[13][27][34]MAIN[26][27][29]
MMCM_DRP[35] bit 12MAIN[13][26][33]MAIN[26][26][30]
MMCM_DRP[35] bit 13MAIN[13][27][33]MAIN[26][27][30]
MMCM_DRP[35] bit 14MAIN[13][26][32]MAIN[26][26][31]
MMCM_DRP[35] bit 15MAIN[13][27][32]MAIN[26][27][31]
MMCM_DRP[36] bit 0MAIN[13][26][31]MAIN[26][26][32]
MMCM_DRP[36] bit 1MAIN[13][27][31]MAIN[26][27][32]
MMCM_DRP[36] bit 2MAIN[13][26][30]MAIN[26][26][33]
MMCM_DRP[36] bit 3MAIN[13][27][30]MAIN[26][27][33]
MMCM_DRP[36] bit 4MAIN[13][26][29]MAIN[26][26][34]
MMCM_DRP[36] bit 5MAIN[13][27][29]MAIN[26][27][34]
MMCM_DRP[36] bit 6MAIN[13][26][28]MAIN[26][26][35]
MMCM_DRP[36] bit 7MAIN[13][27][28]MAIN[26][27][35]
MMCM_DRP[36] bit 8MAIN[13][26][27]MAIN[26][26][36]
MMCM_DRP[36] bit 9MAIN[13][27][27]MAIN[26][27][36]
MMCM_DRP[36] bit 10MAIN[13][26][26]MAIN[26][26][37]
MMCM_DRP[36] bit 11MAIN[13][27][26]MAIN[26][27][37]
MMCM_DRP[36] bit 12MAIN[13][26][25]MAIN[26][26][38]
MMCM_DRP[36] bit 13MAIN[13][27][25]MAIN[26][27][38]
MMCM_DRP[36] bit 14MAIN[13][26][24]MAIN[26][26][39]
MMCM_DRP[36] bit 15MAIN[13][27][24]MAIN[26][27][39]
MMCM_DRP[37] bit 0MAIN[13][26][23]MAIN[26][26][40]
MMCM_DRP[37] bit 1MAIN[13][27][23]MAIN[26][27][40]
MMCM_DRP[37] bit 2MAIN[13][26][22]MAIN[26][26][41]
MMCM_DRP[37] bit 3MAIN[13][27][22]MAIN[26][27][41]
MMCM_DRP[37] bit 4MAIN[13][26][21]MAIN[26][26][42]
MMCM_DRP[37] bit 5MAIN[13][27][21]MAIN[26][27][42]
MMCM_DRP[37] bit 6MAIN[13][26][20]MAIN[26][26][43]
MMCM_DRP[37] bit 7MAIN[13][27][20]MAIN[26][27][43]
MMCM_DRP[37] bit 8MAIN[13][26][19]MAIN[26][26][44]
MMCM_DRP[37] bit 9MAIN[13][27][19]MAIN[26][27][44]
MMCM_DRP[37] bit 10MAIN[13][26][18]MAIN[26][26][45]
MMCM_DRP[37] bit 11MAIN[13][27][18]MAIN[26][27][45]
MMCM_DRP[37] bit 12MAIN[13][26][17]MAIN[26][26][46]
MMCM_DRP[37] bit 13MAIN[13][27][17]MAIN[26][27][46]
MMCM_DRP[37] bit 14MAIN[13][26][16]MAIN[26][26][47]
MMCM_DRP[37] bit 15MAIN[13][27][16]MAIN[26][27][47]
MMCM_DRP[38] bit 0MAIN[13][26][15]MAIN[26][26][48]
MMCM_DRP[38] bit 1MAIN[13][27][15]MAIN[26][27][48]
MMCM_DRP[38] bit 2MAIN[13][26][14]MAIN[26][26][49]
MMCM_DRP[38] bit 3MAIN[13][27][14]MAIN[26][27][49]
MMCM_DRP[38] bit 4MAIN[13][26][13]MAIN[26][26][50]
MMCM_DRP[38] bit 5MAIN[13][27][13]MAIN[26][27][50]
MMCM_DRP[38] bit 6MAIN[13][26][12]MAIN[26][26][51]
MMCM_DRP[38] bit 7MAIN[13][27][12]MAIN[26][27][51]
MMCM_DRP[38] bit 8MAIN[13][26][11]MAIN[26][26][52]
MMCM_DRP[38] bit 9MAIN[13][27][11]MAIN[26][27][52]
MMCM_DRP[38] bit 10MAIN[13][26][10]MAIN[26][26][53]
MMCM_DRP[38] bit 11MAIN[13][27][10]MAIN[26][27][53]
MMCM_DRP[38] bit 12MAIN[13][26][9]MAIN[26][26][54]
MMCM_DRP[38] bit 13MAIN[13][27][9]MAIN[26][27][54]
MMCM_DRP[38] bit 14MAIN[13][26][8]MAIN[26][26][55]
MMCM_DRP[38] bit 15MAIN[13][27][8]MAIN[26][27][55]
MMCM_DRP[39] bit 0MAIN[13][26][7]MAIN[26][26][56]
MMCM_DRP[39] bit 1MAIN[13][27][7]MAIN[26][27][56]
MMCM_DRP[39] bit 2MAIN[13][26][6]MAIN[26][26][57]
MMCM_DRP[39] bit 3MAIN[13][27][6]MAIN[26][27][57]
MMCM_DRP[39] bit 4MAIN[13][26][5]MAIN[26][26][58]
MMCM_DRP[39] bit 5MAIN[13][27][5]MAIN[26][27][58]
MMCM_DRP[39] bit 6MAIN[13][26][4]MAIN[26][26][59]
MMCM_DRP[39] bit 7MAIN[13][27][4]MAIN[26][27][59]
MMCM_DRP[39] bit 8MAIN[13][26][3]MAIN[26][26][60]
MMCM_DRP[39] bit 9MAIN[13][27][3]MAIN[26][27][60]
MMCM_DRP[39] bit 10MAIN[13][26][2]MAIN[26][26][61]
MMCM_DRP[39] bit 11MAIN[13][27][2]MAIN[26][27][61]
MMCM_DRP[39] bit 12MAIN[13][26][1]MAIN[26][26][62]
MMCM_DRP[39] bit 13MAIN[13][27][1]MAIN[26][27][62]
MMCM_DRP[39] bit 14MAIN[13][26][0]MAIN[26][26][63]
MMCM_DRP[39] bit 15MAIN[13][27][0]MAIN[26][27][63]
MMCM_DRP[40] bit 0MAIN[12][26][63]MAIN[27][26][0]
MMCM_DRP[40] bit 1MAIN[12][27][63]MAIN[27][27][0]
MMCM_DRP[40] bit 2MAIN[12][26][62]MAIN[27][26][1]
MMCM_DRP[40] bit 3MAIN[12][27][62]MAIN[27][27][1]
MMCM_DRP[40] bit 4MAIN[12][26][61]MAIN[27][26][2]
MMCM_DRP[40] bit 5MAIN[12][27][61]MAIN[27][27][2]
MMCM_DRP[40] bit 6MAIN[12][26][60]MAIN[27][26][3]
MMCM_DRP[40] bit 7MAIN[12][27][60]MAIN[27][27][3]
MMCM_DRP[40] bit 8MAIN[12][26][59]MAIN[27][26][4]
MMCM_DRP[40] bit 9MAIN[12][27][59]MAIN[27][27][4]
MMCM_DRP[40] bit 10MAIN[12][26][58]MAIN[27][26][5]
MMCM_DRP[40] bit 11MAIN[12][27][58]MAIN[27][27][5]
MMCM_DRP[40] bit 12MAIN[12][26][57]MAIN[27][26][6]
MMCM_DRP[40] bit 13MAIN[12][27][57]MAIN[27][27][6]
MMCM_DRP[40] bit 14MAIN[12][26][56]MAIN[27][26][7]
MMCM_DRP[40] bit 15MAIN[12][27][56]MAIN[27][27][7]
MMCM_DRP[41] bit 0MAIN[12][26][55]MAIN[27][26][8]
MMCM_DRP[41] bit 1MAIN[12][27][55]MAIN[27][27][8]
MMCM_DRP[41] bit 2MAIN[12][26][54]MAIN[27][26][9]
MMCM_DRP[41] bit 3MAIN[12][27][54]MAIN[27][27][9]
MMCM_DRP[41] bit 4MAIN[12][26][53]MAIN[27][26][10]
MMCM_DRP[41] bit 5MAIN[12][27][53]MAIN[27][27][10]
MMCM_DRP[41] bit 6MAIN[12][26][52]MAIN[27][26][11]
MMCM_DRP[41] bit 7MAIN[12][27][52]MAIN[27][27][11]
MMCM_DRP[41] bit 8MAIN[12][26][51]MAIN[27][26][12]
MMCM_DRP[41] bit 9MAIN[12][27][51]MAIN[27][27][12]
MMCM_DRP[41] bit 10MAIN[12][26][50]MAIN[27][26][13]
MMCM_DRP[41] bit 11MAIN[12][27][50]MAIN[27][27][13]
MMCM_DRP[41] bit 12MAIN[12][26][49]MAIN[27][26][14]
MMCM_DRP[41] bit 13MAIN[12][27][49]MAIN[27][27][14]
MMCM_DRP[41] bit 14MAIN[12][26][48]MAIN[27][26][15]
MMCM_DRP[41] bit 15MAIN[12][27][48]MAIN[27][27][15]
MMCM_DRP[42] bit 0MAIN[12][26][47]MAIN[27][26][16]
MMCM_DRP[42] bit 1MAIN[12][27][47]MAIN[27][27][16]
MMCM_DRP[42] bit 2MAIN[12][26][46]MAIN[27][26][17]
MMCM_DRP[42] bit 3MAIN[12][27][46]MAIN[27][27][17]
MMCM_DRP[42] bit 4MAIN[12][26][45]MAIN[27][26][18]
MMCM_DRP[42] bit 5MAIN[12][27][45]MAIN[27][27][18]
MMCM_DRP[42] bit 6MAIN[12][26][44]MAIN[27][26][19]
MMCM_DRP[42] bit 7MAIN[12][27][44]MAIN[27][27][19]
MMCM_DRP[42] bit 8MAIN[12][26][43]MAIN[27][26][20]
MMCM_DRP[42] bit 9MAIN[12][27][43]MAIN[27][27][20]
MMCM_DRP[42] bit 10MAIN[12][26][42]MAIN[27][26][21]
MMCM_DRP[42] bit 11MAIN[12][27][42]MAIN[27][27][21]
MMCM_DRP[42] bit 12MAIN[12][26][41]MAIN[27][26][22]
MMCM_DRP[42] bit 13MAIN[12][27][41]MAIN[27][27][22]
MMCM_DRP[42] bit 14MAIN[12][26][40]MAIN[27][26][23]
MMCM_DRP[42] bit 15MAIN[12][27][40]MAIN[27][27][23]
MMCM_DRP[43] bit 0MAIN[12][26][39]MAIN[27][26][24]
MMCM_DRP[43] bit 1MAIN[12][27][39]MAIN[27][27][24]
MMCM_DRP[43] bit 2MAIN[12][26][38]MAIN[27][26][25]
MMCM_DRP[43] bit 3MAIN[12][27][38]MAIN[27][27][25]
MMCM_DRP[43] bit 4MAIN[12][26][37]MAIN[27][26][26]
MMCM_DRP[43] bit 5MAIN[12][27][37]MAIN[27][27][26]
MMCM_DRP[43] bit 6MAIN[12][26][36]MAIN[27][26][27]
MMCM_DRP[43] bit 7MAIN[12][27][36]MAIN[27][27][27]
MMCM_DRP[43] bit 8MAIN[12][26][35]MAIN[27][26][28]
MMCM_DRP[43] bit 9MAIN[12][27][35]MAIN[27][27][28]
MMCM_DRP[43] bit 10MAIN[12][26][34]MAIN[27][26][29]
MMCM_DRP[43] bit 11MAIN[12][27][34]MAIN[27][27][29]
MMCM_DRP[43] bit 12MAIN[12][26][33]MAIN[27][26][30]
MMCM_DRP[43] bit 13MAIN[12][27][33]MAIN[27][27][30]
MMCM_DRP[43] bit 14MAIN[12][26][32]MAIN[27][26][31]
MMCM_DRP[43] bit 15MAIN[12][27][32]MAIN[27][27][31]
MMCM_DRP[44] bit 0MAIN[12][26][31]MAIN[27][26][32]
MMCM_DRP[44] bit 1MAIN[12][27][31]MAIN[27][27][32]
MMCM_DRP[44] bit 2MAIN[12][26][30]MAIN[27][26][33]
MMCM_DRP[44] bit 3MAIN[12][27][30]MAIN[27][27][33]
MMCM_DRP[44] bit 4MAIN[12][26][29]MAIN[27][26][34]
MMCM_DRP[44] bit 5MAIN[12][27][29]MAIN[27][27][34]
MMCM_DRP[44] bit 6MAIN[12][26][28]MAIN[27][26][35]
MMCM_DRP[44] bit 7MAIN[12][27][28]MAIN[27][27][35]
MMCM_DRP[44] bit 8MAIN[12][26][27]MAIN[27][26][36]
MMCM_DRP[44] bit 9MAIN[12][27][27]MAIN[27][27][36]
MMCM_DRP[44] bit 10MAIN[12][26][26]MAIN[27][26][37]
MMCM_DRP[44] bit 11MAIN[12][27][26]MAIN[27][27][37]
MMCM_DRP[44] bit 12MAIN[12][26][25]MAIN[27][26][38]
MMCM_DRP[44] bit 13MAIN[12][27][25]MAIN[27][27][38]
MMCM_DRP[44] bit 14MAIN[12][26][24]MAIN[27][26][39]
MMCM_DRP[44] bit 15MAIN[12][27][24]MAIN[27][27][39]
MMCM_DRP[45] bit 0MAIN[12][26][23]MAIN[27][26][40]
MMCM_DRP[45] bit 1MAIN[12][27][23]MAIN[27][27][40]
MMCM_DRP[45] bit 2MAIN[12][26][22]MAIN[27][26][41]
MMCM_DRP[45] bit 3MAIN[12][27][22]MAIN[27][27][41]
MMCM_DRP[45] bit 4MAIN[12][26][21]MAIN[27][26][42]
MMCM_DRP[45] bit 5MAIN[12][27][21]MAIN[27][27][42]
MMCM_DRP[45] bit 6MAIN[12][26][20]MAIN[27][26][43]
MMCM_DRP[45] bit 7MAIN[12][27][20]MAIN[27][27][43]
MMCM_DRP[45] bit 8MAIN[12][26][19]MAIN[27][26][44]
MMCM_DRP[45] bit 9MAIN[12][27][19]MAIN[27][27][44]
MMCM_DRP[45] bit 10MAIN[12][26][18]MAIN[27][26][45]
MMCM_DRP[45] bit 11MAIN[12][27][18]MAIN[27][27][45]
MMCM_DRP[45] bit 12MAIN[12][26][17]MAIN[27][26][46]
MMCM_DRP[45] bit 13MAIN[12][27][17]MAIN[27][27][46]
MMCM_DRP[45] bit 14MAIN[12][26][16]MAIN[27][26][47]
MMCM_DRP[45] bit 15MAIN[12][27][16]MAIN[27][27][47]
MMCM_DRP[46] bit 0MAIN[12][26][15]MAIN[27][26][48]
MMCM_DRP[46] bit 1MAIN[12][27][15]MAIN[27][27][48]
MMCM_DRP[46] bit 2MAIN[12][26][14]MAIN[27][26][49]
MMCM_DRP[46] bit 3MAIN[12][27][14]MAIN[27][27][49]
MMCM_DRP[46] bit 4MAIN[12][26][13]MAIN[27][26][50]
MMCM_DRP[46] bit 5MAIN[12][27][13]MAIN[27][27][50]
MMCM_DRP[46] bit 6MAIN[12][26][12]MAIN[27][26][51]
MMCM_DRP[46] bit 7MAIN[12][27][12]MAIN[27][27][51]
MMCM_DRP[46] bit 8MAIN[12][26][11]MAIN[27][26][52]
MMCM_DRP[46] bit 9MAIN[12][27][11]MAIN[27][27][52]
MMCM_DRP[46] bit 10MAIN[12][26][10]MAIN[27][26][53]
MMCM_DRP[46] bit 11MAIN[12][27][10]MAIN[27][27][53]
MMCM_DRP[46] bit 12MAIN[12][26][9]MAIN[27][26][54]
MMCM_DRP[46] bit 13MAIN[12][27][9]MAIN[27][27][54]
MMCM_DRP[46] bit 14MAIN[12][26][8]MAIN[27][26][55]
MMCM_DRP[46] bit 15MAIN[12][27][8]MAIN[27][27][55]
MMCM_DRP[47] bit 0MAIN[12][26][7]MAIN[27][26][56]
MMCM_DRP[47] bit 1MAIN[12][27][7]MAIN[27][27][56]
MMCM_DRP[47] bit 2MAIN[12][26][6]MAIN[27][26][57]
MMCM_DRP[47] bit 3MAIN[12][27][6]MAIN[27][27][57]
MMCM_DRP[47] bit 4MAIN[12][26][5]MAIN[27][26][58]
MMCM_DRP[47] bit 5MAIN[12][27][5]MAIN[27][27][58]
MMCM_DRP[47] bit 6MAIN[12][26][4]MAIN[27][26][59]
MMCM_DRP[47] bit 7MAIN[12][27][4]MAIN[27][27][59]
MMCM_DRP[47] bit 8MAIN[12][26][3]MAIN[27][26][60]
MMCM_DRP[47] bit 9MAIN[12][27][3]MAIN[27][27][60]
MMCM_DRP[47] bit 10MAIN[12][26][2]MAIN[27][26][61]
MMCM_DRP[47] bit 11MAIN[12][27][2]MAIN[27][27][61]
MMCM_DRP[47] bit 12MAIN[12][26][1]MAIN[27][26][62]
MMCM_DRP[47] bit 13MAIN[12][27][1]MAIN[27][27][62]
MMCM_DRP[47] bit 14MAIN[12][26][0]MAIN[27][26][63]
MMCM_DRP[47] bit 15MAIN[12][27][0]MAIN[27][27][63]
MMCM_DRP[48] bit 0MAIN[11][26][63]MAIN[28][26][0]
MMCM_DRP[48] bit 1MAIN[11][27][63]MAIN[28][27][0]
MMCM_DRP[48] bit 2MAIN[11][26][62]MAIN[28][26][1]
MMCM_DRP[48] bit 3MAIN[11][27][62]MAIN[28][27][1]
MMCM_DRP[48] bit 4MAIN[11][26][61]MAIN[28][26][2]
MMCM_DRP[48] bit 5MAIN[11][27][61]MAIN[28][27][2]
MMCM_DRP[48] bit 6MAIN[11][26][60]MAIN[28][26][3]
MMCM_DRP[48] bit 7MAIN[11][27][60]MAIN[28][27][3]
MMCM_DRP[48] bit 8MAIN[11][26][59]MAIN[28][26][4]
MMCM_DRP[48] bit 9MAIN[11][27][59]MAIN[28][27][4]
MMCM_DRP[48] bit 10MAIN[11][26][58]MAIN[28][26][5]
MMCM_DRP[48] bit 11MAIN[11][27][58]MAIN[28][27][5]
MMCM_DRP[48] bit 12MAIN[11][26][57]MAIN[28][26][6]
MMCM_DRP[48] bit 13MAIN[11][27][57]MAIN[28][27][6]
MMCM_DRP[48] bit 14MAIN[11][26][56]MAIN[28][26][7]
MMCM_DRP[48] bit 15MAIN[11][27][56]MAIN[28][27][7]
MMCM_DRP[49] bit 0MAIN[11][26][55]MAIN[28][26][8]
MMCM_DRP[49] bit 1MAIN[11][27][55]MAIN[28][27][8]
MMCM_DRP[49] bit 2MAIN[11][26][54]MAIN[28][26][9]
MMCM_DRP[49] bit 3MAIN[11][27][54]MAIN[28][27][9]
MMCM_DRP[49] bit 4MAIN[11][26][53]MAIN[28][26][10]
MMCM_DRP[49] bit 5MAIN[11][27][53]MAIN[28][27][10]
MMCM_DRP[49] bit 6MAIN[11][26][52]MAIN[28][26][11]
MMCM_DRP[49] bit 7MAIN[11][27][52]MAIN[28][27][11]
MMCM_DRP[49] bit 8MAIN[11][26][51]MAIN[28][26][12]
MMCM_DRP[49] bit 9MAIN[11][27][51]MAIN[28][27][12]
MMCM_DRP[49] bit 10MAIN[11][26][50]MAIN[28][26][13]
MMCM_DRP[49] bit 11MAIN[11][27][50]MAIN[28][27][13]
MMCM_DRP[49] bit 12MAIN[11][26][49]MAIN[28][26][14]
MMCM_DRP[49] bit 13MAIN[11][27][49]MAIN[28][27][14]
MMCM_DRP[49] bit 14MAIN[11][26][48]MAIN[28][26][15]
MMCM_DRP[49] bit 15MAIN[11][27][48]MAIN[28][27][15]
MMCM_DRP[50] bit 0MAIN[11][26][47]MAIN[28][26][16]
MMCM_DRP[50] bit 1MAIN[11][27][47]MAIN[28][27][16]
MMCM_DRP[50] bit 2MAIN[11][26][46]MAIN[28][26][17]
MMCM_DRP[50] bit 3MAIN[11][27][46]MAIN[28][27][17]
MMCM_DRP[50] bit 4MAIN[11][26][45]MAIN[28][26][18]
MMCM_DRP[50] bit 5MAIN[11][27][45]MAIN[28][27][18]
MMCM_DRP[50] bit 6MAIN[11][26][44]MAIN[28][26][19]
MMCM_DRP[50] bit 7MAIN[11][27][44]MAIN[28][27][19]
MMCM_DRP[50] bit 8MAIN[11][26][43]MAIN[28][26][20]
MMCM_DRP[50] bit 9MAIN[11][27][43]MAIN[28][27][20]
MMCM_DRP[50] bit 10MAIN[11][26][42]MAIN[28][26][21]
MMCM_DRP[50] bit 11MAIN[11][27][42]MAIN[28][27][21]
MMCM_DRP[50] bit 12MAIN[11][26][41]MAIN[28][26][22]
MMCM_DRP[50] bit 13MAIN[11][27][41]MAIN[28][27][22]
MMCM_DRP[50] bit 14MAIN[11][26][40]MAIN[28][26][23]
MMCM_DRP[50] bit 15MAIN[11][27][40]MAIN[28][27][23]
MMCM_DRP[51] bit 0MAIN[11][26][39]MAIN[28][26][24]
MMCM_DRP[51] bit 1MAIN[11][27][39]MAIN[28][27][24]
MMCM_DRP[51] bit 2MAIN[11][26][38]MAIN[28][26][25]
MMCM_DRP[51] bit 3MAIN[11][27][38]MAIN[28][27][25]
MMCM_DRP[51] bit 4MAIN[11][26][37]MAIN[28][26][26]
MMCM_DRP[51] bit 5MAIN[11][27][37]MAIN[28][27][26]
MMCM_DRP[51] bit 6MAIN[11][26][36]MAIN[28][26][27]
MMCM_DRP[51] bit 7MAIN[11][27][36]MAIN[28][27][27]
MMCM_DRP[51] bit 8MAIN[11][26][35]MAIN[28][26][28]
MMCM_DRP[51] bit 9MAIN[11][27][35]MAIN[28][27][28]
MMCM_DRP[51] bit 10MAIN[11][26][34]MAIN[28][26][29]
MMCM_DRP[51] bit 11MAIN[11][27][34]MAIN[28][27][29]
MMCM_DRP[51] bit 12MAIN[11][26][33]MAIN[28][26][30]
MMCM_DRP[51] bit 13MAIN[11][27][33]MAIN[28][27][30]
MMCM_DRP[51] bit 14MAIN[11][26][32]MAIN[28][26][31]
MMCM_DRP[51] bit 15MAIN[11][27][32]MAIN[28][27][31]
MMCM_DRP[52] bit 0MAIN[11][26][31]MAIN[28][26][32]
MMCM_DRP[52] bit 1MAIN[11][27][31]MAIN[28][27][32]
MMCM_DRP[52] bit 2MAIN[11][26][30]MAIN[28][26][33]
MMCM_DRP[52] bit 3MAIN[11][27][30]MAIN[28][27][33]
MMCM_DRP[52] bit 4MAIN[11][26][29]MAIN[28][26][34]
MMCM_DRP[52] bit 5MAIN[11][27][29]MAIN[28][27][34]
MMCM_DRP[52] bit 6MAIN[11][26][28]MAIN[28][26][35]
MMCM_DRP[52] bit 7MAIN[11][27][28]MAIN[28][27][35]
MMCM_DRP[52] bit 8MAIN[11][26][27]MAIN[28][26][36]
MMCM_DRP[52] bit 9MAIN[11][27][27]MAIN[28][27][36]
MMCM_DRP[52] bit 10MAIN[11][26][26]MAIN[28][26][37]
MMCM_DRP[52] bit 11MAIN[11][27][26]MAIN[28][27][37]
MMCM_DRP[52] bit 12MAIN[11][26][25]MAIN[28][26][38]
MMCM_DRP[52] bit 13MAIN[11][27][25]MAIN[28][27][38]
MMCM_DRP[52] bit 14MAIN[11][26][24]MAIN[28][26][39]
MMCM_DRP[52] bit 15MAIN[11][27][24]MAIN[28][27][39]
MMCM_DRP[53] bit 0MAIN[11][26][23]MAIN[28][26][40]
MMCM_DRP[53] bit 1MAIN[11][27][23]MAIN[28][27][40]
MMCM_DRP[53] bit 2MAIN[11][26][22]MAIN[28][26][41]
MMCM_DRP[53] bit 3MAIN[11][27][22]MAIN[28][27][41]
MMCM_DRP[53] bit 4MAIN[11][26][21]MAIN[28][26][42]
MMCM_DRP[53] bit 5MAIN[11][27][21]MAIN[28][27][42]
MMCM_DRP[53] bit 6MAIN[11][26][20]MAIN[28][26][43]
MMCM_DRP[53] bit 7MAIN[11][27][20]MAIN[28][27][43]
MMCM_DRP[53] bit 8MAIN[11][26][19]MAIN[28][26][44]
MMCM_DRP[53] bit 9MAIN[11][27][19]MAIN[28][27][44]
MMCM_DRP[53] bit 10MAIN[11][26][18]MAIN[28][26][45]
MMCM_DRP[53] bit 11MAIN[11][27][18]MAIN[28][27][45]
MMCM_DRP[53] bit 12MAIN[11][26][17]MAIN[28][26][46]
MMCM_DRP[53] bit 13MAIN[11][27][17]MAIN[28][27][46]
MMCM_DRP[53] bit 14MAIN[11][26][16]MAIN[28][26][47]
MMCM_DRP[53] bit 15MAIN[11][27][16]MAIN[28][27][47]
MMCM_DRP[54] bit 0MAIN[11][26][15]MAIN[28][26][48]
MMCM_DRP[54] bit 1MAIN[11][27][15]MAIN[28][27][48]
MMCM_DRP[54] bit 2MAIN[11][26][14]MAIN[28][26][49]
MMCM_DRP[54] bit 3MAIN[11][27][14]MAIN[28][27][49]
MMCM_DRP[54] bit 4MAIN[11][26][13]MAIN[28][26][50]
MMCM_DRP[54] bit 5MAIN[11][27][13]MAIN[28][27][50]
MMCM_DRP[54] bit 6MAIN[11][26][12]MAIN[28][26][51]
MMCM_DRP[54] bit 7MAIN[11][27][12]MAIN[28][27][51]
MMCM_DRP[54] bit 8MAIN[11][26][11]MAIN[28][26][52]
MMCM_DRP[54] bit 9MAIN[11][27][11]MAIN[28][27][52]
MMCM_DRP[54] bit 10MAIN[11][26][10]MAIN[28][26][53]
MMCM_DRP[54] bit 11MAIN[11][27][10]MAIN[28][27][53]
MMCM_DRP[54] bit 12MAIN[11][26][9]MAIN[28][26][54]
MMCM_DRP[54] bit 13MAIN[11][27][9]MAIN[28][27][54]
MMCM_DRP[54] bit 14MAIN[11][26][8]MAIN[28][26][55]
MMCM_DRP[54] bit 15MAIN[11][27][8]MAIN[28][27][55]
MMCM_DRP[55] bit 0MAIN[11][26][7]MAIN[28][26][56]
MMCM_DRP[55] bit 1MAIN[11][27][7]MAIN[28][27][56]
MMCM_DRP[55] bit 2MAIN[11][26][6]MAIN[28][26][57]
MMCM_DRP[55] bit 3MAIN[11][27][6]MAIN[28][27][57]
MMCM_DRP[55] bit 4MAIN[11][26][5]MAIN[28][26][58]
MMCM_DRP[55] bit 5MAIN[11][27][5]MAIN[28][27][58]
MMCM_DRP[55] bit 6MAIN[11][26][4]MAIN[28][26][59]
MMCM_DRP[55] bit 7MAIN[11][27][4]MAIN[28][27][59]
MMCM_DRP[55] bit 8MAIN[11][26][3]MAIN[28][26][60]
MMCM_DRP[55] bit 9MAIN[11][27][3]MAIN[28][27][60]
MMCM_DRP[55] bit 10MAIN[11][26][2]MAIN[28][26][61]
MMCM_DRP[55] bit 11MAIN[11][27][2]MAIN[28][27][61]
MMCM_DRP[55] bit 12MAIN[11][26][1]MAIN[28][26][62]
MMCM_DRP[55] bit 13MAIN[11][27][1]MAIN[28][27][62]
MMCM_DRP[55] bit 14MAIN[11][26][0]MAIN[28][26][63]
MMCM_DRP[55] bit 15MAIN[11][27][0]MAIN[28][27][63]
MMCM_DRP[56] bit 0MAIN[10][26][63]MAIN[29][26][0]
MMCM_DRP[56] bit 1MAIN[10][27][63]MAIN[29][27][0]
MMCM_DRP[56] bit 2MAIN[10][26][62]MAIN[29][26][1]
MMCM_DRP[56] bit 3MAIN[10][27][62]MAIN[29][27][1]
MMCM_DRP[56] bit 4MAIN[10][26][61]MAIN[29][26][2]
MMCM_DRP[56] bit 5MAIN[10][27][61]MAIN[29][27][2]
MMCM_DRP[56] bit 6MAIN[10][26][60]MAIN[29][26][3]
MMCM_DRP[56] bit 7MAIN[10][27][60]MAIN[29][27][3]
MMCM_DRP[56] bit 8MAIN[10][26][59]MAIN[29][26][4]
MMCM_DRP[56] bit 9MAIN[10][27][59]MAIN[29][27][4]
MMCM_DRP[56] bit 10MAIN[10][26][58]MAIN[29][26][5]
MMCM_DRP[56] bit 11MAIN[10][27][58]MAIN[29][27][5]
MMCM_DRP[56] bit 12MAIN[10][26][57]MAIN[29][26][6]
MMCM_DRP[56] bit 13MAIN[10][27][57]MAIN[29][27][6]
MMCM_DRP[56] bit 14MAIN[10][26][56]MAIN[29][26][7]
MMCM_DRP[56] bit 15MAIN[10][27][56]MAIN[29][27][7]
MMCM_DRP[57] bit 0MAIN[10][26][55]MAIN[29][26][8]
MMCM_DRP[57] bit 1MAIN[10][27][55]MAIN[29][27][8]
MMCM_DRP[57] bit 2MAIN[10][26][54]MAIN[29][26][9]
MMCM_DRP[57] bit 3MAIN[10][27][54]MAIN[29][27][9]
MMCM_DRP[57] bit 4MAIN[10][26][53]MAIN[29][26][10]
MMCM_DRP[57] bit 5MAIN[10][27][53]MAIN[29][27][10]
MMCM_DRP[57] bit 6MAIN[10][26][52]MAIN[29][26][11]
MMCM_DRP[57] bit 7MAIN[10][27][52]MAIN[29][27][11]
MMCM_DRP[57] bit 8MAIN[10][26][51]MAIN[29][26][12]
MMCM_DRP[57] bit 9MAIN[10][27][51]MAIN[29][27][12]
MMCM_DRP[57] bit 10MAIN[10][26][50]MAIN[29][26][13]
MMCM_DRP[57] bit 11MAIN[10][27][50]MAIN[29][27][13]
MMCM_DRP[57] bit 12MAIN[10][26][49]MAIN[29][26][14]
MMCM_DRP[57] bit 13MAIN[10][27][49]MAIN[29][27][14]
MMCM_DRP[57] bit 14MAIN[10][26][48]MAIN[29][26][15]
MMCM_DRP[57] bit 15MAIN[10][27][48]MAIN[29][27][15]
MMCM_DRP[58] bit 0MAIN[10][26][47]MAIN[29][26][16]
MMCM_DRP[58] bit 1MAIN[10][27][47]MAIN[29][27][16]
MMCM_DRP[58] bit 2MAIN[10][26][46]MAIN[29][26][17]
MMCM_DRP[58] bit 3MAIN[10][27][46]MAIN[29][27][17]
MMCM_DRP[58] bit 4MAIN[10][26][45]MAIN[29][26][18]
MMCM_DRP[58] bit 5MAIN[10][27][45]MAIN[29][27][18]
MMCM_DRP[58] bit 6MAIN[10][26][44]MAIN[29][26][19]
MMCM_DRP[58] bit 7MAIN[10][27][44]MAIN[29][27][19]
MMCM_DRP[58] bit 8MAIN[10][26][43]MAIN[29][26][20]
MMCM_DRP[58] bit 9MAIN[10][27][43]MAIN[29][27][20]
MMCM_DRP[58] bit 10MAIN[10][26][42]MAIN[29][26][21]
MMCM_DRP[58] bit 11MAIN[10][27][42]MAIN[29][27][21]
MMCM_DRP[58] bit 12MAIN[10][26][41]MAIN[29][26][22]
MMCM_DRP[58] bit 13MAIN[10][27][41]MAIN[29][27][22]
MMCM_DRP[58] bit 14MAIN[10][26][40]MAIN[29][26][23]
MMCM_DRP[58] bit 15MAIN[10][27][40]MAIN[29][27][23]
MMCM_DRP[59] bit 0MAIN[10][26][39]MAIN[29][26][24]
MMCM_DRP[59] bit 1MAIN[10][27][39]MAIN[29][27][24]
MMCM_DRP[59] bit 2MAIN[10][26][38]MAIN[29][26][25]
MMCM_DRP[59] bit 3MAIN[10][27][38]MAIN[29][27][25]
MMCM_DRP[59] bit 4MAIN[10][26][37]MAIN[29][26][26]
MMCM_DRP[59] bit 5MAIN[10][27][37]MAIN[29][27][26]
MMCM_DRP[59] bit 6MAIN[10][26][36]MAIN[29][26][27]
MMCM_DRP[59] bit 7MAIN[10][27][36]MAIN[29][27][27]
MMCM_DRP[59] bit 8MAIN[10][26][35]MAIN[29][26][28]
MMCM_DRP[59] bit 9MAIN[10][27][35]MAIN[29][27][28]
MMCM_DRP[59] bit 10MAIN[10][26][34]MAIN[29][26][29]
MMCM_DRP[59] bit 11MAIN[10][27][34]MAIN[29][27][29]
MMCM_DRP[59] bit 12MAIN[10][26][33]MAIN[29][26][30]
MMCM_DRP[59] bit 13MAIN[10][27][33]MAIN[29][27][30]
MMCM_DRP[59] bit 14MAIN[10][26][32]MAIN[29][26][31]
MMCM_DRP[59] bit 15MAIN[10][27][32]MAIN[29][27][31]
MMCM_DRP[60] bit 0MAIN[10][26][31]MAIN[29][26][32]
MMCM_DRP[60] bit 1MAIN[10][27][31]MAIN[29][27][32]
MMCM_DRP[60] bit 2MAIN[10][26][30]MAIN[29][26][33]
MMCM_DRP[60] bit 3MAIN[10][27][30]MAIN[29][27][33]
MMCM_DRP[60] bit 4MAIN[10][26][29]MAIN[29][26][34]
MMCM_DRP[60] bit 5MAIN[10][27][29]MAIN[29][27][34]
MMCM_DRP[60] bit 6MAIN[10][26][28]MAIN[29][26][35]
MMCM_DRP[60] bit 7MAIN[10][27][28]MAIN[29][27][35]
MMCM_DRP[60] bit 8MAIN[10][26][27]MAIN[29][26][36]
MMCM_DRP[60] bit 9MAIN[10][27][27]MAIN[29][27][36]
MMCM_DRP[60] bit 10MAIN[10][26][26]MAIN[29][26][37]
MMCM_DRP[60] bit 11MAIN[10][27][26]MAIN[29][27][37]
MMCM_DRP[60] bit 12MAIN[10][26][25]MAIN[29][26][38]
MMCM_DRP[60] bit 13MAIN[10][27][25]MAIN[29][27][38]
MMCM_DRP[60] bit 14MAIN[10][26][24]MAIN[29][26][39]
MMCM_DRP[60] bit 15MAIN[10][27][24]MAIN[29][27][39]
MMCM_DRP[61] bit 0MAIN[10][26][23]MAIN[29][26][40]
MMCM_DRP[61] bit 1MAIN[10][27][23]MAIN[29][27][40]
MMCM_DRP[61] bit 2MAIN[10][26][22]MAIN[29][26][41]
MMCM_DRP[61] bit 3MAIN[10][27][22]MAIN[29][27][41]
MMCM_DRP[61] bit 4MAIN[10][26][21]MAIN[29][26][42]
MMCM_DRP[61] bit 5MAIN[10][27][21]MAIN[29][27][42]
MMCM_DRP[61] bit 6MAIN[10][26][20]MAIN[29][26][43]
MMCM_DRP[61] bit 7MAIN[10][27][20]MAIN[29][27][43]
MMCM_DRP[61] bit 8MAIN[10][26][19]MAIN[29][26][44]
MMCM_DRP[61] bit 9MAIN[10][27][19]MAIN[29][27][44]
MMCM_DRP[61] bit 10MAIN[10][26][18]MAIN[29][26][45]
MMCM_DRP[61] bit 11MAIN[10][27][18]MAIN[29][27][45]
MMCM_DRP[61] bit 12MAIN[10][26][17]MAIN[29][26][46]
MMCM_DRP[61] bit 13MAIN[10][27][17]MAIN[29][27][46]
MMCM_DRP[61] bit 14MAIN[10][26][16]MAIN[29][26][47]
MMCM_DRP[61] bit 15MAIN[10][27][16]MAIN[29][27][47]
MMCM_DRP[62] bit 0MAIN[10][26][15]MAIN[29][26][48]
MMCM_DRP[62] bit 1MAIN[10][27][15]MAIN[29][27][48]
MMCM_DRP[62] bit 2MAIN[10][26][14]MAIN[29][26][49]
MMCM_DRP[62] bit 3MAIN[10][27][14]MAIN[29][27][49]
MMCM_DRP[62] bit 4MAIN[10][26][13]MAIN[29][26][50]
MMCM_DRP[62] bit 5MAIN[10][27][13]MAIN[29][27][50]
MMCM_DRP[62] bit 6MAIN[10][26][12]MAIN[29][26][51]
MMCM_DRP[62] bit 7MAIN[10][27][12]MAIN[29][27][51]
MMCM_DRP[62] bit 8MAIN[10][26][11]MAIN[29][26][52]
MMCM_DRP[62] bit 9MAIN[10][27][11]MAIN[29][27][52]
MMCM_DRP[62] bit 10MAIN[10][26][10]MAIN[29][26][53]
MMCM_DRP[62] bit 11MAIN[10][27][10]MAIN[29][27][53]
MMCM_DRP[62] bit 12MAIN[10][26][9]MAIN[29][26][54]
MMCM_DRP[62] bit 13MAIN[10][27][9]MAIN[29][27][54]
MMCM_DRP[62] bit 14MAIN[10][26][8]MAIN[29][26][55]
MMCM_DRP[62] bit 15MAIN[10][27][8]MAIN[29][27][55]
MMCM_DRP[63] bit 0MAIN[10][26][7]MAIN[29][26][56]
MMCM_DRP[63] bit 1MAIN[10][27][7]MAIN[29][27][56]
MMCM_DRP[63] bit 2MAIN[10][26][6]MAIN[29][26][57]
MMCM_DRP[63] bit 3MAIN[10][27][6]MAIN[29][27][57]
MMCM_DRP[63] bit 4MAIN[10][26][5]MAIN[29][26][58]
MMCM_DRP[63] bit 5MAIN[10][27][5]MAIN[29][27][58]
MMCM_DRP[63] bit 6MAIN[10][26][4]MAIN[29][26][59]
MMCM_DRP[63] bit 7MAIN[10][27][4]MAIN[29][27][59]
MMCM_DRP[63] bit 8MAIN[10][26][3]MAIN[29][26][60]
MMCM_DRP[63] bit 9MAIN[10][27][3]MAIN[29][27][60]
MMCM_DRP[63] bit 10MAIN[10][26][2]MAIN[29][26][61]
MMCM_DRP[63] bit 11MAIN[10][27][2]MAIN[29][27][61]
MMCM_DRP[63] bit 12MAIN[10][26][1]MAIN[29][26][62]
MMCM_DRP[63] bit 13MAIN[10][27][1]MAIN[29][27][62]
MMCM_DRP[63] bit 14MAIN[10][26][0]MAIN[29][26][63]
MMCM_DRP[63] bit 15MAIN[10][27][0]MAIN[29][27][63]
MMCM_DRP[64] bit 0MAIN[9][26][63]MAIN[30][26][0]
MMCM_DRP[64] bit 1MAIN[9][27][63]MAIN[30][27][0]
MMCM_DRP[64] bit 2MAIN[9][26][62]MAIN[30][26][1]
MMCM_DRP[64] bit 3MAIN[9][27][62]MAIN[30][27][1]
MMCM_DRP[64] bit 4MAIN[9][26][61]MAIN[30][26][2]
MMCM_DRP[64] bit 5MAIN[9][27][61]MAIN[30][27][2]
MMCM_DRP[64] bit 6MAIN[9][26][60]MAIN[30][26][3]
MMCM_DRP[64] bit 7MAIN[9][27][60]MAIN[30][27][3]
MMCM_DRP[64] bit 8MAIN[9][26][59]MAIN[30][26][4]
MMCM_DRP[64] bit 9MAIN[9][27][59]MAIN[30][27][4]
MMCM_DRP[64] bit 10MAIN[9][26][58]MAIN[30][26][5]
MMCM_DRP[64] bit 11MAIN[9][27][58]MAIN[30][27][5]
MMCM_DRP[64] bit 12MAIN[9][26][57]MAIN[30][26][6]
MMCM_DRP[64] bit 13MAIN[9][27][57]MAIN[30][27][6]
MMCM_DRP[64] bit 14MAIN[9][26][56]MAIN[30][26][7]
MMCM_DRP[64] bit 15MAIN[9][27][56]MAIN[30][27][7]
MMCM_DRP[65] bit 0MAIN[9][26][55]MAIN[30][26][8]
MMCM_DRP[65] bit 1MAIN[9][27][55]MAIN[30][27][8]
MMCM_DRP[65] bit 2MAIN[9][26][54]MAIN[30][26][9]
MMCM_DRP[65] bit 3MAIN[9][27][54]MAIN[30][27][9]
MMCM_DRP[65] bit 4MAIN[9][26][53]MAIN[30][26][10]
MMCM_DRP[65] bit 5MAIN[9][27][53]MAIN[30][27][10]
MMCM_DRP[65] bit 6MAIN[9][26][52]MAIN[30][26][11]
MMCM_DRP[65] bit 7MAIN[9][27][52]MAIN[30][27][11]
MMCM_DRP[65] bit 8MAIN[9][26][51]MAIN[30][26][12]
MMCM_DRP[65] bit 9MAIN[9][27][51]MAIN[30][27][12]
MMCM_DRP[65] bit 10MAIN[9][26][50]MAIN[30][26][13]
MMCM_DRP[65] bit 11MAIN[9][27][50]MAIN[30][27][13]
MMCM_DRP[65] bit 12MAIN[9][26][49]MAIN[30][26][14]
MMCM_DRP[65] bit 13MAIN[9][27][49]MAIN[30][27][14]
MMCM_DRP[65] bit 14MAIN[9][26][48]MAIN[30][26][15]
MMCM_DRP[65] bit 15MAIN[9][27][48]MAIN[30][27][15]
MMCM_DRP[66] bit 0MAIN[9][26][47]MAIN[30][26][16]
MMCM_DRP[66] bit 1MAIN[9][27][47]MAIN[30][27][16]
MMCM_DRP[66] bit 2MAIN[9][26][46]MAIN[30][26][17]
MMCM_DRP[66] bit 3MAIN[9][27][46]MAIN[30][27][17]
MMCM_DRP[66] bit 4MAIN[9][26][45]MAIN[30][26][18]
MMCM_DRP[66] bit 5MAIN[9][27][45]MAIN[30][27][18]
MMCM_DRP[66] bit 6MAIN[9][26][44]MAIN[30][26][19]
MMCM_DRP[66] bit 7MAIN[9][27][44]MAIN[30][27][19]
MMCM_DRP[66] bit 8MAIN[9][26][43]MAIN[30][26][20]
MMCM_DRP[66] bit 9MAIN[9][27][43]MAIN[30][27][20]
MMCM_DRP[66] bit 10MAIN[9][26][42]MAIN[30][26][21]
MMCM_DRP[66] bit 11MAIN[9][27][42]MAIN[30][27][21]
MMCM_DRP[66] bit 12MAIN[9][26][41]MAIN[30][26][22]
MMCM_DRP[66] bit 13MAIN[9][27][41]MAIN[30][27][22]
MMCM_DRP[66] bit 14MAIN[9][26][40]MAIN[30][26][23]
MMCM_DRP[66] bit 15MAIN[9][27][40]MAIN[30][27][23]
MMCM_DRP[67] bit 0MAIN[9][26][39]MAIN[30][26][24]
MMCM_DRP[67] bit 1MAIN[9][27][39]MAIN[30][27][24]
MMCM_DRP[67] bit 2MAIN[9][26][38]MAIN[30][26][25]
MMCM_DRP[67] bit 3MAIN[9][27][38]MAIN[30][27][25]
MMCM_DRP[67] bit 4MAIN[9][26][37]MAIN[30][26][26]
MMCM_DRP[67] bit 5MAIN[9][27][37]MAIN[30][27][26]
MMCM_DRP[67] bit 6MAIN[9][26][36]MAIN[30][26][27]
MMCM_DRP[67] bit 7MAIN[9][27][36]MAIN[30][27][27]
MMCM_DRP[67] bit 8MAIN[9][26][35]MAIN[30][26][28]
MMCM_DRP[67] bit 9MAIN[9][27][35]MAIN[30][27][28]
MMCM_DRP[67] bit 10MAIN[9][26][34]MAIN[30][26][29]
MMCM_DRP[67] bit 11MAIN[9][27][34]MAIN[30][27][29]
MMCM_DRP[67] bit 12MAIN[9][26][33]MAIN[30][26][30]
MMCM_DRP[67] bit 13MAIN[9][27][33]MAIN[30][27][30]
MMCM_DRP[67] bit 14MAIN[9][26][32]MAIN[30][26][31]
MMCM_DRP[67] bit 15MAIN[9][27][32]MAIN[30][27][31]
MMCM_DRP[68] bit 0MAIN[9][26][31]MAIN[30][26][32]
MMCM_DRP[68] bit 1MAIN[9][27][31]MAIN[30][27][32]
MMCM_DRP[68] bit 2MAIN[9][26][30]MAIN[30][26][33]
MMCM_DRP[68] bit 3MAIN[9][27][30]MAIN[30][27][33]
MMCM_DRP[68] bit 4MAIN[9][26][29]MAIN[30][26][34]
MMCM_DRP[68] bit 5MAIN[9][27][29]MAIN[30][27][34]
MMCM_DRP[68] bit 6MAIN[9][26][28]MAIN[30][26][35]
MMCM_DRP[68] bit 7MAIN[9][27][28]MAIN[30][27][35]
MMCM_DRP[68] bit 8MAIN[9][26][27]MAIN[30][26][36]
MMCM_DRP[68] bit 9MAIN[9][27][27]MAIN[30][27][36]
MMCM_DRP[68] bit 10MAIN[9][26][26]MAIN[30][26][37]
MMCM_DRP[68] bit 11MAIN[9][27][26]MAIN[30][27][37]
MMCM_DRP[68] bit 12MAIN[9][26][25]MAIN[30][26][38]
MMCM_DRP[68] bit 13MAIN[9][27][25]MAIN[30][27][38]
MMCM_DRP[68] bit 14MAIN[9][26][24]MAIN[30][26][39]
MMCM_DRP[68] bit 15MAIN[9][27][24]MAIN[30][27][39]
MMCM_DRP[69] bit 0MAIN[9][26][23]MAIN[30][26][40]
MMCM_DRP[69] bit 1MAIN[9][27][23]MAIN[30][27][40]
MMCM_DRP[69] bit 2MAIN[9][26][22]MAIN[30][26][41]
MMCM_DRP[69] bit 3MAIN[9][27][22]MAIN[30][27][41]
MMCM_DRP[69] bit 4MAIN[9][26][21]MAIN[30][26][42]
MMCM_DRP[69] bit 5MAIN[9][27][21]MAIN[30][27][42]
MMCM_DRP[69] bit 6MAIN[9][26][20]MAIN[30][26][43]
MMCM_DRP[69] bit 7MAIN[9][27][20]MAIN[30][27][43]
MMCM_DRP[69] bit 8MAIN[9][26][19]MAIN[30][26][44]
MMCM_DRP[69] bit 9MAIN[9][27][19]MAIN[30][27][44]
MMCM_DRP[69] bit 10MAIN[9][26][18]MAIN[30][26][45]
MMCM_DRP[69] bit 11MAIN[9][27][18]MAIN[30][27][45]
MMCM_DRP[69] bit 12MAIN[9][26][17]MAIN[30][26][46]
MMCM_DRP[69] bit 13MAIN[9][27][17]MAIN[30][27][46]
MMCM_DRP[69] bit 14MAIN[9][26][16]MAIN[30][26][47]
MMCM_DRP[69] bit 15MAIN[9][27][16]MAIN[30][27][47]
MMCM_DRP[70] bit 0MAIN[9][26][15]MAIN[30][26][48]
MMCM_DRP[70] bit 1MAIN[9][27][15]MAIN[30][27][48]
MMCM_DRP[70] bit 2MAIN[9][26][14]MAIN[30][26][49]
MMCM_DRP[70] bit 3MAIN[9][27][14]MAIN[30][27][49]
MMCM_DRP[70] bit 4MAIN[9][26][13]MAIN[30][26][50]
MMCM_DRP[70] bit 5MAIN[9][27][13]MAIN[30][27][50]
MMCM_DRP[70] bit 6MAIN[9][26][12]MAIN[30][26][51]
MMCM_DRP[70] bit 7MAIN[9][27][12]MAIN[30][27][51]
MMCM_DRP[70] bit 8MAIN[9][26][11]MAIN[30][26][52]
MMCM_DRP[70] bit 9MAIN[9][27][11]MAIN[30][27][52]
MMCM_DRP[70] bit 10MAIN[9][26][10]MAIN[30][26][53]
MMCM_DRP[70] bit 11MAIN[9][27][10]MAIN[30][27][53]
MMCM_DRP[70] bit 12MAIN[9][26][9]MAIN[30][26][54]
MMCM_DRP[70] bit 13MAIN[9][27][9]MAIN[30][27][54]
MMCM_DRP[70] bit 14MAIN[9][26][8]MAIN[30][26][55]
MMCM_DRP[70] bit 15MAIN[9][27][8]MAIN[30][27][55]
MMCM_DRP[71] bit 0MAIN[9][26][7]MAIN[30][26][56]
MMCM_DRP[71] bit 1MAIN[9][27][7]MAIN[30][27][56]
MMCM_DRP[71] bit 2MAIN[9][26][6]MAIN[30][26][57]
MMCM_DRP[71] bit 3MAIN[9][27][6]MAIN[30][27][57]
MMCM_DRP[71] bit 4MAIN[9][26][5]MAIN[30][26][58]
MMCM_DRP[71] bit 5MAIN[9][27][5]MAIN[30][27][58]
MMCM_DRP[71] bit 6MAIN[9][26][4]MAIN[30][26][59]
MMCM_DRP[71] bit 7MAIN[9][27][4]MAIN[30][27][59]
MMCM_DRP[71] bit 8MAIN[9][26][3]MAIN[30][26][60]
MMCM_DRP[71] bit 9MAIN[9][27][3]MAIN[30][27][60]
MMCM_DRP[71] bit 10MAIN[9][26][2]MAIN[30][26][61]
MMCM_DRP[71] bit 11MAIN[9][27][2]MAIN[30][27][61]
MMCM_DRP[71] bit 12MAIN[9][26][1]MAIN[30][26][62]
MMCM_DRP[71] bit 13MAIN[9][27][1]MAIN[30][27][62]
MMCM_DRP[71] bit 14MAIN[9][26][0]MAIN[30][26][63]
MMCM_DRP[71] bit 15MAIN[9][27][0]MAIN[30][27][63]
MMCM_DRP[72] bit 0MAIN[8][26][63]MAIN[31][26][0]
MMCM_DRP[72] bit 1MAIN[8][27][63]MAIN[31][27][0]
MMCM_DRP[72] bit 2MAIN[8][26][62]MAIN[31][26][1]
MMCM_DRP[72] bit 3MAIN[8][27][62]MAIN[31][27][1]
MMCM_DRP[72] bit 4MAIN[8][26][61]MAIN[31][26][2]
MMCM_DRP[72] bit 5MAIN[8][27][61]MAIN[31][27][2]
MMCM_DRP[72] bit 6MAIN[8][26][60]MAIN[31][26][3]
MMCM_DRP[72] bit 7MAIN[8][27][60]MAIN[31][27][3]
MMCM_DRP[72] bit 8MAIN[8][26][59]MAIN[31][26][4]
MMCM_DRP[72] bit 9MAIN[8][27][59]MAIN[31][27][4]
MMCM_DRP[72] bit 10MAIN[8][26][58]MAIN[31][26][5]
MMCM_DRP[72] bit 11MAIN[8][27][58]MAIN[31][27][5]
MMCM_DRP[72] bit 12MAIN[8][26][57]MAIN[31][26][6]
MMCM_DRP[72] bit 13MAIN[8][27][57]MAIN[31][27][6]
MMCM_DRP[72] bit 14MAIN[8][26][56]MAIN[31][26][7]
MMCM_DRP[72] bit 15MAIN[8][27][56]MAIN[31][27][7]
MMCM_DRP[73] bit 0MAIN[8][26][55]MAIN[31][26][8]
MMCM_DRP[73] bit 1MAIN[8][27][55]MAIN[31][27][8]
MMCM_DRP[73] bit 2MAIN[8][26][54]MAIN[31][26][9]
MMCM_DRP[73] bit 3MAIN[8][27][54]MAIN[31][27][9]
MMCM_DRP[73] bit 4MAIN[8][26][53]MAIN[31][26][10]
MMCM_DRP[73] bit 5MAIN[8][27][53]MAIN[31][27][10]
MMCM_DRP[73] bit 6MAIN[8][26][52]MAIN[31][26][11]
MMCM_DRP[73] bit 7MAIN[8][27][52]MAIN[31][27][11]
MMCM_DRP[73] bit 8MAIN[8][26][51]MAIN[31][26][12]
MMCM_DRP[73] bit 9MAIN[8][27][51]MAIN[31][27][12]
MMCM_DRP[73] bit 10MAIN[8][26][50]MAIN[31][26][13]
MMCM_DRP[73] bit 11MAIN[8][27][50]MAIN[31][27][13]
MMCM_DRP[73] bit 12MAIN[8][26][49]MAIN[31][26][14]
MMCM_DRP[73] bit 13MAIN[8][27][49]MAIN[31][27][14]
MMCM_DRP[73] bit 14MAIN[8][26][48]MAIN[31][26][15]
MMCM_DRP[73] bit 15MAIN[8][27][48]MAIN[31][27][15]
MMCM_DRP[74] bit 0MAIN[8][26][47]MAIN[31][26][16]
MMCM_DRP[74] bit 1MAIN[8][27][47]MAIN[31][27][16]
MMCM_DRP[74] bit 2MAIN[8][26][46]MAIN[31][26][17]
MMCM_DRP[74] bit 3MAIN[8][27][46]MAIN[31][27][17]
MMCM_DRP[74] bit 4MAIN[8][26][45]MAIN[31][26][18]
MMCM_DRP[74] bit 5MAIN[8][27][45]MAIN[31][27][18]
MMCM_DRP[74] bit 6MAIN[8][26][44]MAIN[31][26][19]
MMCM_DRP[74] bit 7MAIN[8][27][44]MAIN[31][27][19]
MMCM_DRP[74] bit 8MAIN[8][26][43]MAIN[31][26][20]
MMCM_DRP[74] bit 9MAIN[8][27][43]MAIN[31][27][20]
MMCM_DRP[74] bit 10MAIN[8][26][42]MAIN[31][26][21]
MMCM_DRP[74] bit 11MAIN[8][27][42]MAIN[31][27][21]
MMCM_DRP[74] bit 12MAIN[8][26][41]MAIN[31][26][22]
MMCM_DRP[74] bit 13MAIN[8][27][41]MAIN[31][27][22]
MMCM_DRP[74] bit 14MAIN[8][26][40]MAIN[31][26][23]
MMCM_DRP[74] bit 15MAIN[8][27][40]MAIN[31][27][23]
MMCM_DRP[75] bit 0MAIN[8][26][39]MAIN[31][26][24]
MMCM_DRP[75] bit 1MAIN[8][27][39]MAIN[31][27][24]
MMCM_DRP[75] bit 2MAIN[8][26][38]MAIN[31][26][25]
MMCM_DRP[75] bit 3MAIN[8][27][38]MAIN[31][27][25]
MMCM_DRP[75] bit 4MAIN[8][26][37]MAIN[31][26][26]
MMCM_DRP[75] bit 5MAIN[8][27][37]MAIN[31][27][26]
MMCM_DRP[75] bit 6MAIN[8][26][36]MAIN[31][26][27]
MMCM_DRP[75] bit 7MAIN[8][27][36]MAIN[31][27][27]
MMCM_DRP[75] bit 8MAIN[8][26][35]MAIN[31][26][28]
MMCM_DRP[75] bit 9MAIN[8][27][35]MAIN[31][27][28]
MMCM_DRP[75] bit 10MAIN[8][26][34]MAIN[31][26][29]
MMCM_DRP[75] bit 11MAIN[8][27][34]MAIN[31][27][29]
MMCM_DRP[75] bit 12MAIN[8][26][33]MAIN[31][26][30]
MMCM_DRP[75] bit 13MAIN[8][27][33]MAIN[31][27][30]
MMCM_DRP[75] bit 14MAIN[8][26][32]MAIN[31][26][31]
MMCM_DRP[75] bit 15MAIN[8][27][32]MAIN[31][27][31]
MMCM_DRP[76] bit 0MAIN[8][26][31]MAIN[31][26][32]
MMCM_DRP[76] bit 1MAIN[8][27][31]MAIN[31][27][32]
MMCM_DRP[76] bit 2MAIN[8][26][30]MAIN[31][26][33]
MMCM_DRP[76] bit 3MAIN[8][27][30]MAIN[31][27][33]
MMCM_DRP[76] bit 4MAIN[8][26][29]MAIN[31][26][34]
MMCM_DRP[76] bit 5MAIN[8][27][29]MAIN[31][27][34]
MMCM_DRP[76] bit 6MAIN[8][26][28]MAIN[31][26][35]
MMCM_DRP[76] bit 7MAIN[8][27][28]MAIN[31][27][35]
MMCM_DRP[76] bit 8MAIN[8][26][27]MAIN[31][26][36]
MMCM_DRP[76] bit 9MAIN[8][27][27]MAIN[31][27][36]
MMCM_DRP[76] bit 10MAIN[8][26][26]MAIN[31][26][37]
MMCM_DRP[76] bit 11MAIN[8][27][26]MAIN[31][27][37]
MMCM_DRP[76] bit 12MAIN[8][26][25]MAIN[31][26][38]
MMCM_DRP[76] bit 13MAIN[8][27][25]MAIN[31][27][38]
MMCM_DRP[76] bit 14MAIN[8][26][24]MAIN[31][26][39]
MMCM_DRP[76] bit 15MAIN[8][27][24]MAIN[31][27][39]
MMCM_DRP[77] bit 0MAIN[8][26][23]MAIN[31][26][40]
MMCM_DRP[77] bit 1MAIN[8][27][23]MAIN[31][27][40]
MMCM_DRP[77] bit 2MAIN[8][26][22]MAIN[31][26][41]
MMCM_DRP[77] bit 3MAIN[8][27][22]MAIN[31][27][41]
MMCM_DRP[77] bit 4MAIN[8][26][21]MAIN[31][26][42]
MMCM_DRP[77] bit 5MAIN[8][27][21]MAIN[31][27][42]
MMCM_DRP[77] bit 6MAIN[8][26][20]MAIN[31][26][43]
MMCM_DRP[77] bit 7MAIN[8][27][20]MAIN[31][27][43]
MMCM_DRP[77] bit 8MAIN[8][26][19]MAIN[31][26][44]
MMCM_DRP[77] bit 9MAIN[8][27][19]MAIN[31][27][44]
MMCM_DRP[77] bit 10MAIN[8][26][18]MAIN[31][26][45]
MMCM_DRP[77] bit 11MAIN[8][27][18]MAIN[31][27][45]
MMCM_DRP[77] bit 12MAIN[8][26][17]MAIN[31][26][46]
MMCM_DRP[77] bit 13MAIN[8][27][17]MAIN[31][27][46]
MMCM_DRP[77] bit 14MAIN[8][26][16]MAIN[31][26][47]
MMCM_DRP[77] bit 15MAIN[8][27][16]MAIN[31][27][47]
MMCM_DRP[78] bit 0MAIN[8][26][15]MAIN[31][26][48]
MMCM_DRP[78] bit 1MAIN[8][27][15]MAIN[31][27][48]
MMCM_DRP[78] bit 2MAIN[8][26][14]MAIN[31][26][49]
MMCM_DRP[78] bit 3MAIN[8][27][14]MAIN[31][27][49]
MMCM_DRP[78] bit 4MAIN[8][26][13]MAIN[31][26][50]
MMCM_DRP[78] bit 5MAIN[8][27][13]MAIN[31][27][50]
MMCM_DRP[78] bit 6MAIN[8][26][12]MAIN[31][26][51]
MMCM_DRP[78] bit 7MAIN[8][27][12]MAIN[31][27][51]
MMCM_DRP[78] bit 8MAIN[8][26][11]MAIN[31][26][52]
MMCM_DRP[78] bit 9MAIN[8][27][11]MAIN[31][27][52]
MMCM_DRP[78] bit 10MAIN[8][26][10]MAIN[31][26][53]
MMCM_DRP[78] bit 11MAIN[8][27][10]MAIN[31][27][53]
MMCM_DRP[78] bit 12MAIN[8][26][9]MAIN[31][26][54]
MMCM_DRP[78] bit 13MAIN[8][27][9]MAIN[31][27][54]
MMCM_DRP[78] bit 14MAIN[8][26][8]MAIN[31][26][55]
MMCM_DRP[78] bit 15MAIN[8][27][8]MAIN[31][27][55]
MMCM_DRP[79] bit 0MAIN[8][26][7]MAIN[31][26][56]
MMCM_DRP[79] bit 1MAIN[8][27][7]MAIN[31][27][56]
MMCM_DRP[79] bit 2MAIN[8][26][6]MAIN[31][26][57]
MMCM_DRP[79] bit 3MAIN[8][27][6]MAIN[31][27][57]
MMCM_DRP[79] bit 4MAIN[8][26][5]MAIN[31][26][58]
MMCM_DRP[79] bit 5MAIN[8][27][5]MAIN[31][27][58]
MMCM_DRP[79] bit 6MAIN[8][26][4]MAIN[31][26][59]
MMCM_DRP[79] bit 7MAIN[8][27][4]MAIN[31][27][59]
MMCM_DRP[79] bit 8MAIN[8][26][3]MAIN[31][26][60]
MMCM_DRP[79] bit 9MAIN[8][27][3]MAIN[31][27][60]
MMCM_DRP[79] bit 10MAIN[8][26][2]MAIN[31][26][61]
MMCM_DRP[79] bit 11MAIN[8][27][2]MAIN[31][27][61]
MMCM_DRP[79] bit 12MAIN[8][26][1]MAIN[31][26][62]
MMCM_DRP[79] bit 13MAIN[8][27][1]MAIN[31][27][62]
MMCM_DRP[79] bit 14MAIN[8][26][0]MAIN[31][26][63]
MMCM_DRP[79] bit 15MAIN[8][27][0]MAIN[31][27][63]
MMCM_DRP[80] bit 0MAIN[7][26][63]MAIN[32][26][0]
MMCM_DRP[80] bit 1MAIN[7][27][63]MAIN[32][27][0]
MMCM_DRP[80] bit 2MAIN[7][26][62]MAIN[32][26][1]
MMCM_DRP[80] bit 3MAIN[7][27][62]MAIN[32][27][1]
MMCM_DRP[80] bit 4MAIN[7][26][61]MAIN[32][26][2]
MMCM_DRP[80] bit 5MAIN[7][27][61]MAIN[32][27][2]
MMCM_DRP[80] bit 6MAIN[7][26][60]MAIN[32][26][3]
MMCM_DRP[80] bit 7MAIN[7][27][60]MAIN[32][27][3]
MMCM_DRP[80] bit 8MAIN[7][26][59]MAIN[32][26][4]
MMCM_DRP[80] bit 9MAIN[7][27][59]MAIN[32][27][4]
MMCM_DRP[80] bit 10MAIN[7][26][58]MAIN[32][26][5]
MMCM_DRP[80] bit 11MAIN[7][27][58]MAIN[32][27][5]
MMCM_DRP[80] bit 12MAIN[7][26][57]MAIN[32][26][6]
MMCM_DRP[80] bit 13MAIN[7][27][57]MAIN[32][27][6]
MMCM_DRP[80] bit 14MAIN[7][26][56]MAIN[32][26][7]
MMCM_DRP[80] bit 15MAIN[7][27][56]MAIN[32][27][7]
MMCM_DRP[81] bit 0MAIN[7][26][55]MAIN[32][26][8]
MMCM_DRP[81] bit 1MAIN[7][27][55]MAIN[32][27][8]
MMCM_DRP[81] bit 2MAIN[7][26][54]MAIN[32][26][9]
MMCM_DRP[81] bit 3MAIN[7][27][54]MAIN[32][27][9]
MMCM_DRP[81] bit 4MAIN[7][26][53]MAIN[32][26][10]
MMCM_DRP[81] bit 5MAIN[7][27][53]MAIN[32][27][10]
MMCM_DRP[81] bit 6MAIN[7][26][52]MAIN[32][26][11]
MMCM_DRP[81] bit 7MAIN[7][27][52]MAIN[32][27][11]
MMCM_DRP[81] bit 8MAIN[7][26][51]MAIN[32][26][12]
MMCM_DRP[81] bit 9MAIN[7][27][51]MAIN[32][27][12]
MMCM_DRP[81] bit 10MAIN[7][26][50]MAIN[32][26][13]
MMCM_DRP[81] bit 11MAIN[7][27][50]MAIN[32][27][13]
MMCM_DRP[81] bit 12MAIN[7][26][49]MAIN[32][26][14]
MMCM_DRP[81] bit 13MAIN[7][27][49]MAIN[32][27][14]
MMCM_DRP[81] bit 14MAIN[7][26][48]MAIN[32][26][15]
MMCM_DRP[81] bit 15MAIN[7][27][48]MAIN[32][27][15]
MMCM_DRP[82] bit 0MAIN[7][26][47]MAIN[32][26][16]
MMCM_DRP[82] bit 1MAIN[7][27][47]MAIN[32][27][16]
MMCM_DRP[82] bit 2MAIN[7][26][46]MAIN[32][26][17]
MMCM_DRP[82] bit 3MAIN[7][27][46]MAIN[32][27][17]
MMCM_DRP[82] bit 4MAIN[7][26][45]MAIN[32][26][18]
MMCM_DRP[82] bit 5MAIN[7][27][45]MAIN[32][27][18]
MMCM_DRP[82] bit 6MAIN[7][26][44]MAIN[32][26][19]
MMCM_DRP[82] bit 7MAIN[7][27][44]MAIN[32][27][19]
MMCM_DRP[82] bit 8MAIN[7][26][43]MAIN[32][26][20]
MMCM_DRP[82] bit 9MAIN[7][27][43]MAIN[32][27][20]
MMCM_DRP[82] bit 10MAIN[7][26][42]MAIN[32][26][21]
MMCM_DRP[82] bit 11MAIN[7][27][42]MAIN[32][27][21]
MMCM_DRP[82] bit 12MAIN[7][26][41]MAIN[32][26][22]
MMCM_DRP[82] bit 13MAIN[7][27][41]MAIN[32][27][22]
MMCM_DRP[82] bit 14MAIN[7][26][40]MAIN[32][26][23]
MMCM_DRP[82] bit 15MAIN[7][27][40]MAIN[32][27][23]
MMCM_DRP[83] bit 0MAIN[7][26][39]MAIN[32][26][24]
MMCM_DRP[83] bit 1MAIN[7][27][39]MAIN[32][27][24]
MMCM_DRP[83] bit 2MAIN[7][26][38]MAIN[32][26][25]
MMCM_DRP[83] bit 3MAIN[7][27][38]MAIN[32][27][25]
MMCM_DRP[83] bit 4MAIN[7][26][37]MAIN[32][26][26]
MMCM_DRP[83] bit 5MAIN[7][27][37]MAIN[32][27][26]
MMCM_DRP[83] bit 6MAIN[7][26][36]MAIN[32][26][27]
MMCM_DRP[83] bit 7MAIN[7][27][36]MAIN[32][27][27]
MMCM_DRP[83] bit 8MAIN[7][26][35]MAIN[32][26][28]
MMCM_DRP[83] bit 9MAIN[7][27][35]MAIN[32][27][28]
MMCM_DRP[83] bit 10MAIN[7][26][34]MAIN[32][26][29]
MMCM_DRP[83] bit 11MAIN[7][27][34]MAIN[32][27][29]
MMCM_DRP[83] bit 12MAIN[7][26][33]MAIN[32][26][30]
MMCM_DRP[83] bit 13MAIN[7][27][33]MAIN[32][27][30]
MMCM_DRP[83] bit 14MAIN[7][26][32]MAIN[32][26][31]
MMCM_DRP[83] bit 15MAIN[7][27][32]MAIN[32][27][31]
MMCM_DRP[84] bit 0MAIN[7][26][31]MAIN[32][26][32]
MMCM_DRP[84] bit 1MAIN[7][27][31]MAIN[32][27][32]
MMCM_DRP[84] bit 2MAIN[7][26][30]MAIN[32][26][33]
MMCM_DRP[84] bit 3MAIN[7][27][30]MAIN[32][27][33]
MMCM_DRP[84] bit 4MAIN[7][26][29]MAIN[32][26][34]
MMCM_DRP[84] bit 5MAIN[7][27][29]MAIN[32][27][34]
MMCM_DRP[84] bit 6MAIN[7][26][28]MAIN[32][26][35]
MMCM_DRP[84] bit 7MAIN[7][27][28]MAIN[32][27][35]
MMCM_DRP[84] bit 8MAIN[7][26][27]MAIN[32][26][36]
MMCM_DRP[84] bit 9MAIN[7][27][27]MAIN[32][27][36]
MMCM_DRP[84] bit 10MAIN[7][26][26]MAIN[32][26][37]
MMCM_DRP[84] bit 11MAIN[7][27][26]MAIN[32][27][37]
MMCM_DRP[84] bit 12MAIN[7][26][25]MAIN[32][26][38]
MMCM_DRP[84] bit 13MAIN[7][27][25]MAIN[32][27][38]
MMCM_DRP[84] bit 14MAIN[7][26][24]MAIN[32][26][39]
MMCM_DRP[84] bit 15MAIN[7][27][24]MAIN[32][27][39]
MMCM_DRP[85] bit 0MAIN[7][26][23]MAIN[32][26][40]
MMCM_DRP[85] bit 1MAIN[7][27][23]MAIN[32][27][40]
MMCM_DRP[85] bit 2MAIN[7][26][22]MAIN[32][26][41]
MMCM_DRP[85] bit 3MAIN[7][27][22]MAIN[32][27][41]
MMCM_DRP[85] bit 4MAIN[7][26][21]MAIN[32][26][42]
MMCM_DRP[85] bit 5MAIN[7][27][21]MAIN[32][27][42]
MMCM_DRP[85] bit 6MAIN[7][26][20]MAIN[32][26][43]
MMCM_DRP[85] bit 7MAIN[7][27][20]MAIN[32][27][43]
MMCM_DRP[85] bit 8MAIN[7][26][19]MAIN[32][26][44]
MMCM_DRP[85] bit 9MAIN[7][27][19]MAIN[32][27][44]
MMCM_DRP[85] bit 10MAIN[7][26][18]MAIN[32][26][45]
MMCM_DRP[85] bit 11MAIN[7][27][18]MAIN[32][27][45]
MMCM_DRP[85] bit 12MAIN[7][26][17]MAIN[32][26][46]
MMCM_DRP[85] bit 13MAIN[7][27][17]MAIN[32][27][46]
MMCM_DRP[85] bit 14MAIN[7][26][16]MAIN[32][26][47]
MMCM_DRP[85] bit 15MAIN[7][27][16]MAIN[32][27][47]
MMCM_DRP[86] bit 0MAIN[7][26][15]MAIN[32][26][48]
MMCM_DRP[86] bit 1MAIN[7][27][15]MAIN[32][27][48]
MMCM_DRP[86] bit 2MAIN[7][26][14]MAIN[32][26][49]
MMCM_DRP[86] bit 3MAIN[7][27][14]MAIN[32][27][49]
MMCM_DRP[86] bit 4MAIN[7][26][13]MAIN[32][26][50]
MMCM_DRP[86] bit 5MAIN[7][27][13]MAIN[32][27][50]
MMCM_DRP[86] bit 6MAIN[7][26][12]MAIN[32][26][51]
MMCM_DRP[86] bit 7MAIN[7][27][12]MAIN[32][27][51]
MMCM_DRP[86] bit 8MAIN[7][26][11]MAIN[32][26][52]
MMCM_DRP[86] bit 9MAIN[7][27][11]MAIN[32][27][52]
MMCM_DRP[86] bit 10MAIN[7][26][10]MAIN[32][26][53]
MMCM_DRP[86] bit 11MAIN[7][27][10]MAIN[32][27][53]
MMCM_DRP[86] bit 12MAIN[7][26][9]MAIN[32][26][54]
MMCM_DRP[86] bit 13MAIN[7][27][9]MAIN[32][27][54]
MMCM_DRP[86] bit 14MAIN[7][26][8]MAIN[32][26][55]
MMCM_DRP[86] bit 15MAIN[7][27][8]MAIN[32][27][55]
MMCM_DRP[87] bit 0MAIN[7][26][7]MAIN[32][26][56]
MMCM_DRP[87] bit 1MAIN[7][27][7]MAIN[32][27][56]
MMCM_DRP[87] bit 2MAIN[7][26][6]MAIN[32][26][57]
MMCM_DRP[87] bit 3MAIN[7][27][6]MAIN[32][27][57]
MMCM_DRP[87] bit 4MAIN[7][26][5]MAIN[32][26][58]
MMCM_DRP[87] bit 5MAIN[7][27][5]MAIN[32][27][58]
MMCM_DRP[87] bit 6MAIN[7][26][4]MAIN[32][26][59]
MMCM_DRP[87] bit 7MAIN[7][27][4]MAIN[32][27][59]
MMCM_DRP[87] bit 8MAIN[7][26][3]MAIN[32][26][60]
MMCM_DRP[87] bit 9MAIN[7][27][3]MAIN[32][27][60]
MMCM_DRP[87] bit 10MAIN[7][26][2]MAIN[32][26][61]
MMCM_DRP[87] bit 11MAIN[7][27][2]MAIN[32][27][61]
MMCM_DRP[87] bit 12MAIN[7][26][1]MAIN[32][26][62]
MMCM_DRP[87] bit 13MAIN[7][27][1]MAIN[32][27][62]
MMCM_DRP[87] bit 14MAIN[7][26][0]MAIN[32][26][63]
MMCM_DRP[87] bit 15MAIN[7][27][0]MAIN[32][27][63]
MMCM_DRP[88] bit 0MAIN[6][26][63]MAIN[33][26][0]
MMCM_DRP[88] bit 1MAIN[6][27][63]MAIN[33][27][0]
MMCM_DRP[88] bit 2MAIN[6][26][62]MAIN[33][26][1]
MMCM_DRP[88] bit 3MAIN[6][27][62]MAIN[33][27][1]
MMCM_DRP[88] bit 4MAIN[6][26][61]MAIN[33][26][2]
MMCM_DRP[88] bit 5MAIN[6][27][61]MAIN[33][27][2]
MMCM_DRP[88] bit 6MAIN[6][26][60]MAIN[33][26][3]
MMCM_DRP[88] bit 7MAIN[6][27][60]MAIN[33][27][3]
MMCM_DRP[88] bit 8MAIN[6][26][59]MAIN[33][26][4]
MMCM_DRP[88] bit 9MAIN[6][27][59]MAIN[33][27][4]
MMCM_DRP[88] bit 10MAIN[6][26][58]MAIN[33][26][5]
MMCM_DRP[88] bit 11MAIN[6][27][58]MAIN[33][27][5]
MMCM_DRP[88] bit 12MAIN[6][26][57]MAIN[33][26][6]
MMCM_DRP[88] bit 13MAIN[6][27][57]MAIN[33][27][6]
MMCM_DRP[88] bit 14MAIN[6][26][56]MAIN[33][26][7]
MMCM_DRP[88] bit 15MAIN[6][27][56]MAIN[33][27][7]
MMCM_DRP[89] bit 0MAIN[6][26][55]MAIN[33][26][8]
MMCM_DRP[89] bit 1MAIN[6][27][55]MAIN[33][27][8]
MMCM_DRP[89] bit 2MAIN[6][26][54]MAIN[33][26][9]
MMCM_DRP[89] bit 3MAIN[6][27][54]MAIN[33][27][9]
MMCM_DRP[89] bit 4MAIN[6][26][53]MAIN[33][26][10]
MMCM_DRP[89] bit 5MAIN[6][27][53]MAIN[33][27][10]
MMCM_DRP[89] bit 6MAIN[6][26][52]MAIN[33][26][11]
MMCM_DRP[89] bit 7MAIN[6][27][52]MAIN[33][27][11]
MMCM_DRP[89] bit 8MAIN[6][26][51]MAIN[33][26][12]
MMCM_DRP[89] bit 9MAIN[6][27][51]MAIN[33][27][12]
MMCM_DRP[89] bit 10MAIN[6][26][50]MAIN[33][26][13]
MMCM_DRP[89] bit 11MAIN[6][27][50]MAIN[33][27][13]
MMCM_DRP[89] bit 12MAIN[6][26][49]MAIN[33][26][14]
MMCM_DRP[89] bit 13MAIN[6][27][49]MAIN[33][27][14]
MMCM_DRP[89] bit 14MAIN[6][26][48]MAIN[33][26][15]
MMCM_DRP[89] bit 15MAIN[6][27][48]MAIN[33][27][15]
MMCM_DRP[90] bit 0MAIN[6][26][47]MAIN[33][26][16]
MMCM_DRP[90] bit 1MAIN[6][27][47]MAIN[33][27][16]
MMCM_DRP[90] bit 2MAIN[6][26][46]MAIN[33][26][17]
MMCM_DRP[90] bit 3MAIN[6][27][46]MAIN[33][27][17]
MMCM_DRP[90] bit 4MAIN[6][26][45]MAIN[33][26][18]
MMCM_DRP[90] bit 5MAIN[6][27][45]MAIN[33][27][18]
MMCM_DRP[90] bit 6MAIN[6][26][44]MAIN[33][26][19]
MMCM_DRP[90] bit 7MAIN[6][27][44]MAIN[33][27][19]
MMCM_DRP[90] bit 8MAIN[6][26][43]MAIN[33][26][20]
MMCM_DRP[90] bit 9MAIN[6][27][43]MAIN[33][27][20]
MMCM_DRP[90] bit 10MAIN[6][26][42]MAIN[33][26][21]
MMCM_DRP[90] bit 11MAIN[6][27][42]MAIN[33][27][21]
MMCM_DRP[90] bit 12MAIN[6][26][41]MAIN[33][26][22]
MMCM_DRP[90] bit 13MAIN[6][27][41]MAIN[33][27][22]
MMCM_DRP[90] bit 14MAIN[6][26][40]MAIN[33][26][23]
MMCM_DRP[90] bit 15MAIN[6][27][40]MAIN[33][27][23]
MMCM_DRP[91] bit 0MAIN[6][26][39]MAIN[33][26][24]
MMCM_DRP[91] bit 1MAIN[6][27][39]MAIN[33][27][24]
MMCM_DRP[91] bit 2MAIN[6][26][38]MAIN[33][26][25]
MMCM_DRP[91] bit 3MAIN[6][27][38]MAIN[33][27][25]
MMCM_DRP[91] bit 4MAIN[6][26][37]MAIN[33][26][26]
MMCM_DRP[91] bit 5MAIN[6][27][37]MAIN[33][27][26]
MMCM_DRP[91] bit 6MAIN[6][26][36]MAIN[33][26][27]
MMCM_DRP[91] bit 7MAIN[6][27][36]MAIN[33][27][27]
MMCM_DRP[91] bit 8MAIN[6][26][35]MAIN[33][26][28]
MMCM_DRP[91] bit 9MAIN[6][27][35]MAIN[33][27][28]
MMCM_DRP[91] bit 10MAIN[6][26][34]MAIN[33][26][29]
MMCM_DRP[91] bit 11MAIN[6][27][34]MAIN[33][27][29]
MMCM_DRP[91] bit 12MAIN[6][26][33]MAIN[33][26][30]
MMCM_DRP[91] bit 13MAIN[6][27][33]MAIN[33][27][30]
MMCM_DRP[91] bit 14MAIN[6][26][32]MAIN[33][26][31]
MMCM_DRP[91] bit 15MAIN[6][27][32]MAIN[33][27][31]
MMCM_DRP[92] bit 0MAIN[6][26][31]MAIN[33][26][32]
MMCM_DRP[92] bit 1MAIN[6][27][31]MAIN[33][27][32]
MMCM_DRP[92] bit 2MAIN[6][26][30]MAIN[33][26][33]
MMCM_DRP[92] bit 3MAIN[6][27][30]MAIN[33][27][33]
MMCM_DRP[92] bit 4MAIN[6][26][29]MAIN[33][26][34]
MMCM_DRP[92] bit 5MAIN[6][27][29]MAIN[33][27][34]
MMCM_DRP[92] bit 6MAIN[6][26][28]MAIN[33][26][35]
MMCM_DRP[92] bit 7MAIN[6][27][28]MAIN[33][27][35]
MMCM_DRP[92] bit 8MAIN[6][26][27]MAIN[33][26][36]
MMCM_DRP[92] bit 9MAIN[6][27][27]MAIN[33][27][36]
MMCM_DRP[92] bit 10MAIN[6][26][26]MAIN[33][26][37]
MMCM_DRP[92] bit 11MAIN[6][27][26]MAIN[33][27][37]
MMCM_DRP[92] bit 12MAIN[6][26][25]MAIN[33][26][38]
MMCM_DRP[92] bit 13MAIN[6][27][25]MAIN[33][27][38]
MMCM_DRP[92] bit 14MAIN[6][26][24]MAIN[33][26][39]
MMCM_DRP[92] bit 15MAIN[6][27][24]MAIN[33][27][39]
MMCM_DRP[93] bit 0MAIN[6][26][23]MAIN[33][26][40]
MMCM_DRP[93] bit 1MAIN[6][27][23]MAIN[33][27][40]
MMCM_DRP[93] bit 2MAIN[6][26][22]MAIN[33][26][41]
MMCM_DRP[93] bit 3MAIN[6][27][22]MAIN[33][27][41]
MMCM_DRP[93] bit 4MAIN[6][26][21]MAIN[33][26][42]
MMCM_DRP[93] bit 5MAIN[6][27][21]MAIN[33][27][42]
MMCM_DRP[93] bit 6MAIN[6][26][20]MAIN[33][26][43]
MMCM_DRP[93] bit 7MAIN[6][27][20]MAIN[33][27][43]
MMCM_DRP[93] bit 8MAIN[6][26][19]MAIN[33][26][44]
MMCM_DRP[93] bit 9MAIN[6][27][19]MAIN[33][27][44]
MMCM_DRP[93] bit 10MAIN[6][26][18]MAIN[33][26][45]
MMCM_DRP[93] bit 11MAIN[6][27][18]MAIN[33][27][45]
MMCM_DRP[93] bit 12MAIN[6][26][17]MAIN[33][26][46]
MMCM_DRP[93] bit 13MAIN[6][27][17]MAIN[33][27][46]
MMCM_DRP[93] bit 14MAIN[6][26][16]MAIN[33][26][47]
MMCM_DRP[93] bit 15MAIN[6][27][16]MAIN[33][27][47]
MMCM_DRP[94] bit 0MAIN[6][26][15]MAIN[33][26][48]
MMCM_DRP[94] bit 1MAIN[6][27][15]MAIN[33][27][48]
MMCM_DRP[94] bit 2MAIN[6][26][14]MAIN[33][26][49]
MMCM_DRP[94] bit 3MAIN[6][27][14]MAIN[33][27][49]
MMCM_DRP[94] bit 4MAIN[6][26][13]MAIN[33][26][50]
MMCM_DRP[94] bit 5MAIN[6][27][13]MAIN[33][27][50]
MMCM_DRP[94] bit 6MAIN[6][26][12]MAIN[33][26][51]
MMCM_DRP[94] bit 7MAIN[6][27][12]MAIN[33][27][51]
MMCM_DRP[94] bit 8MAIN[6][26][11]MAIN[33][26][52]
MMCM_DRP[94] bit 9MAIN[6][27][11]MAIN[33][27][52]
MMCM_DRP[94] bit 10MAIN[6][26][10]MAIN[33][26][53]
MMCM_DRP[94] bit 11MAIN[6][27][10]MAIN[33][27][53]
MMCM_DRP[94] bit 12MAIN[6][26][9]MAIN[33][26][54]
MMCM_DRP[94] bit 13MAIN[6][27][9]MAIN[33][27][54]
MMCM_DRP[94] bit 14MAIN[6][26][8]MAIN[33][26][55]
MMCM_DRP[94] bit 15MAIN[6][27][8]MAIN[33][27][55]
MMCM_DRP[95] bit 0MAIN[6][26][7]MAIN[33][26][56]
MMCM_DRP[95] bit 1MAIN[6][27][7]MAIN[33][27][56]
MMCM_DRP[95] bit 2MAIN[6][26][6]MAIN[33][26][57]
MMCM_DRP[95] bit 3MAIN[6][27][6]MAIN[33][27][57]
MMCM_DRP[95] bit 4MAIN[6][26][5]MAIN[33][26][58]
MMCM_DRP[95] bit 5MAIN[6][27][5]MAIN[33][27][58]
MMCM_DRP[95] bit 6MAIN[6][26][4]MAIN[33][26][59]
MMCM_DRP[95] bit 7MAIN[6][27][4]MAIN[33][27][59]
MMCM_DRP[95] bit 8MAIN[6][26][3]MAIN[33][26][60]
MMCM_DRP[95] bit 9MAIN[6][27][3]MAIN[33][27][60]
MMCM_DRP[95] bit 10MAIN[6][26][2]MAIN[33][26][61]
MMCM_DRP[95] bit 11MAIN[6][27][2]MAIN[33][27][61]
MMCM_DRP[95] bit 12MAIN[6][26][1]MAIN[33][26][62]
MMCM_DRP[95] bit 13MAIN[6][27][1]MAIN[33][27][62]
MMCM_DRP[95] bit 14MAIN[6][26][0]MAIN[33][26][63]
MMCM_DRP[95] bit 15MAIN[6][27][0]MAIN[33][27][63]
MMCM_DRP[96] bit 0MAIN[5][26][63]MAIN[34][26][0]
MMCM_DRP[96] bit 1MAIN[5][27][63]MAIN[34][27][0]
MMCM_DRP[96] bit 2MAIN[5][26][62]MAIN[34][26][1]
MMCM_DRP[96] bit 3MAIN[5][27][62]MAIN[34][27][1]
MMCM_DRP[96] bit 4MAIN[5][26][61]MAIN[34][26][2]
MMCM_DRP[96] bit 5MAIN[5][27][61]MAIN[34][27][2]
MMCM_DRP[96] bit 6MAIN[5][26][60]MAIN[34][26][3]
MMCM_DRP[96] bit 7MAIN[5][27][60]MAIN[34][27][3]
MMCM_DRP[96] bit 8MAIN[5][26][59]MAIN[34][26][4]
MMCM_DRP[96] bit 9MAIN[5][27][59]MAIN[34][27][4]
MMCM_DRP[96] bit 10MAIN[5][26][58]MAIN[34][26][5]
MMCM_DRP[96] bit 11MAIN[5][27][58]MAIN[34][27][5]
MMCM_DRP[96] bit 12MAIN[5][26][57]MAIN[34][26][6]
MMCM_DRP[96] bit 13MAIN[5][27][57]MAIN[34][27][6]
MMCM_DRP[96] bit 14MAIN[5][26][56]MAIN[34][26][7]
MMCM_DRP[96] bit 15MAIN[5][27][56]MAIN[34][27][7]
MMCM_DRP[97] bit 0MAIN[5][26][55]MAIN[34][26][8]
MMCM_DRP[97] bit 1MAIN[5][27][55]MAIN[34][27][8]
MMCM_DRP[97] bit 2MAIN[5][26][54]MAIN[34][26][9]
MMCM_DRP[97] bit 3MAIN[5][27][54]MAIN[34][27][9]
MMCM_DRP[97] bit 4MAIN[5][26][53]MAIN[34][26][10]
MMCM_DRP[97] bit 5MAIN[5][27][53]MAIN[34][27][10]
MMCM_DRP[97] bit 6MAIN[5][26][52]MAIN[34][26][11]
MMCM_DRP[97] bit 7MAIN[5][27][52]MAIN[34][27][11]
MMCM_DRP[97] bit 8MAIN[5][26][51]MAIN[34][26][12]
MMCM_DRP[97] bit 9MAIN[5][27][51]MAIN[34][27][12]
MMCM_DRP[97] bit 10MAIN[5][26][50]MAIN[34][26][13]
MMCM_DRP[97] bit 11MAIN[5][27][50]MAIN[34][27][13]
MMCM_DRP[97] bit 12MAIN[5][26][49]MAIN[34][26][14]
MMCM_DRP[97] bit 13MAIN[5][27][49]MAIN[34][27][14]
MMCM_DRP[97] bit 14MAIN[5][26][48]MAIN[34][26][15]
MMCM_DRP[97] bit 15MAIN[5][27][48]MAIN[34][27][15]
MMCM_DRP[98] bit 0MAIN[5][26][47]MAIN[34][26][16]
MMCM_DRP[98] bit 1MAIN[5][27][47]MAIN[34][27][16]
MMCM_DRP[98] bit 2MAIN[5][26][46]MAIN[34][26][17]
MMCM_DRP[98] bit 3MAIN[5][27][46]MAIN[34][27][17]
MMCM_DRP[98] bit 4MAIN[5][26][45]MAIN[34][26][18]
MMCM_DRP[98] bit 5MAIN[5][27][45]MAIN[34][27][18]
MMCM_DRP[98] bit 6MAIN[5][26][44]MAIN[34][26][19]
MMCM_DRP[98] bit 7MAIN[5][27][44]MAIN[34][27][19]
MMCM_DRP[98] bit 8MAIN[5][26][43]MAIN[34][26][20]
MMCM_DRP[98] bit 9MAIN[5][27][43]MAIN[34][27][20]
MMCM_DRP[98] bit 10MAIN[5][26][42]MAIN[34][26][21]
MMCM_DRP[98] bit 11MAIN[5][27][42]MAIN[34][27][21]
MMCM_DRP[98] bit 12MAIN[5][26][41]MAIN[34][26][22]
MMCM_DRP[98] bit 13MAIN[5][27][41]MAIN[34][27][22]
MMCM_DRP[98] bit 14MAIN[5][26][40]MAIN[34][26][23]
MMCM_DRP[98] bit 15MAIN[5][27][40]MAIN[34][27][23]
MMCM_DRP[99] bit 0MAIN[5][26][39]MAIN[34][26][24]
MMCM_DRP[99] bit 1MAIN[5][27][39]MAIN[34][27][24]
MMCM_DRP[99] bit 2MAIN[5][26][38]MAIN[34][26][25]
MMCM_DRP[99] bit 3MAIN[5][27][38]MAIN[34][27][25]
MMCM_DRP[99] bit 4MAIN[5][26][37]MAIN[34][26][26]
MMCM_DRP[99] bit 5MAIN[5][27][37]MAIN[34][27][26]
MMCM_DRP[99] bit 6MAIN[5][26][36]MAIN[34][26][27]
MMCM_DRP[99] bit 7MAIN[5][27][36]MAIN[34][27][27]
MMCM_DRP[99] bit 8MAIN[5][26][35]MAIN[34][26][28]
MMCM_DRP[99] bit 9MAIN[5][27][35]MAIN[34][27][28]
MMCM_DRP[99] bit 10MAIN[5][26][34]MAIN[34][26][29]
MMCM_DRP[99] bit 11MAIN[5][27][34]MAIN[34][27][29]
MMCM_DRP[99] bit 12MAIN[5][26][33]MAIN[34][26][30]
MMCM_DRP[99] bit 13MAIN[5][27][33]MAIN[34][27][30]
MMCM_DRP[99] bit 14MAIN[5][26][32]MAIN[34][26][31]
MMCM_DRP[99] bit 15MAIN[5][27][32]MAIN[34][27][31]
MMCM_DRP[100] bit 0MAIN[5][26][31]MAIN[34][26][32]
MMCM_DRP[100] bit 1MAIN[5][27][31]MAIN[34][27][32]
MMCM_DRP[100] bit 2MAIN[5][26][30]MAIN[34][26][33]
MMCM_DRP[100] bit 3MAIN[5][27][30]MAIN[34][27][33]
MMCM_DRP[100] bit 4MAIN[5][26][29]MAIN[34][26][34]
MMCM_DRP[100] bit 5MAIN[5][27][29]MAIN[34][27][34]
MMCM_DRP[100] bit 6MAIN[5][26][28]MAIN[34][26][35]
MMCM_DRP[100] bit 7MAIN[5][27][28]MAIN[34][27][35]
MMCM_DRP[100] bit 8MAIN[5][26][27]MAIN[34][26][36]
MMCM_DRP[100] bit 9MAIN[5][27][27]MAIN[34][27][36]
MMCM_DRP[100] bit 10MAIN[5][26][26]MAIN[34][26][37]
MMCM_DRP[100] bit 11MAIN[5][27][26]MAIN[34][27][37]
MMCM_DRP[100] bit 12MAIN[5][26][25]MAIN[34][26][38]
MMCM_DRP[100] bit 13MAIN[5][27][25]MAIN[34][27][38]
MMCM_DRP[100] bit 14MAIN[5][26][24]MAIN[34][26][39]
MMCM_DRP[100] bit 15MAIN[5][27][24]MAIN[34][27][39]
MMCM_DRP[101] bit 0MAIN[5][26][23]MAIN[34][26][40]
MMCM_DRP[101] bit 1MAIN[5][27][23]MAIN[34][27][40]
MMCM_DRP[101] bit 2MAIN[5][26][22]MAIN[34][26][41]
MMCM_DRP[101] bit 3MAIN[5][27][22]MAIN[34][27][41]
MMCM_DRP[101] bit 4MAIN[5][26][21]MAIN[34][26][42]
MMCM_DRP[101] bit 5MAIN[5][27][21]MAIN[34][27][42]
MMCM_DRP[101] bit 6MAIN[5][26][20]MAIN[34][26][43]
MMCM_DRP[101] bit 7MAIN[5][27][20]MAIN[34][27][43]
MMCM_DRP[101] bit 8MAIN[5][26][19]MAIN[34][26][44]
MMCM_DRP[101] bit 9MAIN[5][27][19]MAIN[34][27][44]
MMCM_DRP[101] bit 10MAIN[5][26][18]MAIN[34][26][45]
MMCM_DRP[101] bit 11MAIN[5][27][18]MAIN[34][27][45]
MMCM_DRP[101] bit 12MAIN[5][26][17]MAIN[34][26][46]
MMCM_DRP[101] bit 13MAIN[5][27][17]MAIN[34][27][46]
MMCM_DRP[101] bit 14MAIN[5][26][16]MAIN[34][26][47]
MMCM_DRP[101] bit 15MAIN[5][27][16]MAIN[34][27][47]
MMCM_DRP[102] bit 0MAIN[5][26][15]MAIN[34][26][48]
MMCM_DRP[102] bit 1MAIN[5][27][15]MAIN[34][27][48]
MMCM_DRP[102] bit 2MAIN[5][26][14]MAIN[34][26][49]
MMCM_DRP[102] bit 3MAIN[5][27][14]MAIN[34][27][49]
MMCM_DRP[102] bit 4MAIN[5][26][13]MAIN[34][26][50]
MMCM_DRP[102] bit 5MAIN[5][27][13]MAIN[34][27][50]
MMCM_DRP[102] bit 6MAIN[5][26][12]MAIN[34][26][51]
MMCM_DRP[102] bit 7MAIN[5][27][12]MAIN[34][27][51]
MMCM_DRP[102] bit 8MAIN[5][26][11]MAIN[34][26][52]
MMCM_DRP[102] bit 9MAIN[5][27][11]MAIN[34][27][52]
MMCM_DRP[102] bit 10MAIN[5][26][10]MAIN[34][26][53]
MMCM_DRP[102] bit 11MAIN[5][27][10]MAIN[34][27][53]
MMCM_DRP[102] bit 12MAIN[5][26][9]MAIN[34][26][54]
MMCM_DRP[102] bit 13MAIN[5][27][9]MAIN[34][27][54]
MMCM_DRP[102] bit 14MAIN[5][26][8]MAIN[34][26][55]
MMCM_DRP[102] bit 15MAIN[5][27][8]MAIN[34][27][55]
MMCM_DRP[103] bit 0MAIN[5][26][7]MAIN[34][26][56]
MMCM_DRP[103] bit 1MAIN[5][27][7]MAIN[34][27][56]
MMCM_DRP[103] bit 2MAIN[5][26][6]MAIN[34][26][57]
MMCM_DRP[103] bit 3MAIN[5][27][6]MAIN[34][27][57]
MMCM_DRP[103] bit 4MAIN[5][26][5]MAIN[34][26][58]
MMCM_DRP[103] bit 5MAIN[5][27][5]MAIN[34][27][58]
MMCM_DRP[103] bit 6MAIN[5][26][4]MAIN[34][26][59]
MMCM_DRP[103] bit 7MAIN[5][27][4]MAIN[34][27][59]
MMCM_DRP[103] bit 8MAIN[5][26][3]MAIN[34][26][60]
MMCM_DRP[103] bit 9MAIN[5][27][3]MAIN[34][27][60]
MMCM_DRP[103] bit 10MAIN[5][26][2]MAIN[34][26][61]
MMCM_DRP[103] bit 11MAIN[5][27][2]MAIN[34][27][61]
MMCM_DRP[103] bit 12MAIN[5][26][1]MAIN[34][26][62]
MMCM_DRP[103] bit 13MAIN[5][27][1]MAIN[34][27][62]
MMCM_DRP[103] bit 14MAIN[5][26][0]MAIN[34][26][63]
MMCM_DRP[103] bit 15MAIN[5][27][0]MAIN[34][27][63]
MMCM_DRP[104] bit 0MAIN[4][26][63]MAIN[35][26][0]
MMCM_DRP[104] bit 1MAIN[4][27][63]MAIN[35][27][0]
MMCM_DRP[104] bit 2MAIN[4][26][62]MAIN[35][26][1]
MMCM_DRP[104] bit 3MAIN[4][27][62]MAIN[35][27][1]
MMCM_DRP[104] bit 4MAIN[4][26][61]MAIN[35][26][2]
MMCM_DRP[104] bit 5MAIN[4][27][61]MAIN[35][27][2]
MMCM_DRP[104] bit 6MAIN[4][26][60]MAIN[35][26][3]
MMCM_DRP[104] bit 7MAIN[4][27][60]MAIN[35][27][3]
MMCM_DRP[104] bit 8MAIN[4][26][59]MAIN[35][26][4]
MMCM_DRP[104] bit 9MAIN[4][27][59]MAIN[35][27][4]
MMCM_DRP[104] bit 10MAIN[4][26][58]MAIN[35][26][5]
MMCM_DRP[104] bit 11MAIN[4][27][58]MAIN[35][27][5]
MMCM_DRP[104] bit 12MAIN[4][26][57]MAIN[35][26][6]
MMCM_DRP[104] bit 13MAIN[4][27][57]MAIN[35][27][6]
MMCM_DRP[104] bit 14MAIN[4][26][56]MAIN[35][26][7]
MMCM_DRP[104] bit 15MAIN[4][27][56]MAIN[35][27][7]
MMCM_DRP[105] bit 0MAIN[4][26][55]MAIN[35][26][8]
MMCM_DRP[105] bit 1MAIN[4][27][55]MAIN[35][27][8]
MMCM_DRP[105] bit 2MAIN[4][26][54]MAIN[35][26][9]
MMCM_DRP[105] bit 3MAIN[4][27][54]MAIN[35][27][9]
MMCM_DRP[105] bit 4MAIN[4][26][53]MAIN[35][26][10]
MMCM_DRP[105] bit 5MAIN[4][27][53]MAIN[35][27][10]
MMCM_DRP[105] bit 6MAIN[4][26][52]MAIN[35][26][11]
MMCM_DRP[105] bit 7MAIN[4][27][52]MAIN[35][27][11]
MMCM_DRP[105] bit 8MAIN[4][26][51]MAIN[35][26][12]
MMCM_DRP[105] bit 9MAIN[4][27][51]MAIN[35][27][12]
MMCM_DRP[105] bit 10MAIN[4][26][50]MAIN[35][26][13]
MMCM_DRP[105] bit 11MAIN[4][27][50]MAIN[35][27][13]
MMCM_DRP[105] bit 12MAIN[4][26][49]MAIN[35][26][14]
MMCM_DRP[105] bit 13MAIN[4][27][49]MAIN[35][27][14]
MMCM_DRP[105] bit 14MAIN[4][26][48]MAIN[35][26][15]
MMCM_DRP[105] bit 15MAIN[4][27][48]MAIN[35][27][15]
MMCM_DRP[106] bit 0MAIN[4][26][47]MAIN[35][26][16]
MMCM_DRP[106] bit 1MAIN[4][27][47]MAIN[35][27][16]
MMCM_DRP[106] bit 2MAIN[4][26][46]MAIN[35][26][17]
MMCM_DRP[106] bit 3MAIN[4][27][46]MAIN[35][27][17]
MMCM_DRP[106] bit 4MAIN[4][26][45]MAIN[35][26][18]
MMCM_DRP[106] bit 5MAIN[4][27][45]MAIN[35][27][18]
MMCM_DRP[106] bit 6MAIN[4][26][44]MAIN[35][26][19]
MMCM_DRP[106] bit 7MAIN[4][27][44]MAIN[35][27][19]
MMCM_DRP[106] bit 8MAIN[4][26][43]MAIN[35][26][20]
MMCM_DRP[106] bit 9MAIN[4][27][43]MAIN[35][27][20]
MMCM_DRP[106] bit 10MAIN[4][26][42]MAIN[35][26][21]
MMCM_DRP[106] bit 11MAIN[4][27][42]MAIN[35][27][21]
MMCM_DRP[106] bit 12MAIN[4][26][41]MAIN[35][26][22]
MMCM_DRP[106] bit 13MAIN[4][27][41]MAIN[35][27][22]
MMCM_DRP[106] bit 14MAIN[4][26][40]MAIN[35][26][23]
MMCM_DRP[106] bit 15MAIN[4][27][40]MAIN[35][27][23]
MMCM_DRP[107] bit 0MAIN[4][26][39]MAIN[35][26][24]
MMCM_DRP[107] bit 1MAIN[4][27][39]MAIN[35][27][24]
MMCM_DRP[107] bit 2MAIN[4][26][38]MAIN[35][26][25]
MMCM_DRP[107] bit 3MAIN[4][27][38]MAIN[35][27][25]
MMCM_DRP[107] bit 4MAIN[4][26][37]MAIN[35][26][26]
MMCM_DRP[107] bit 5MAIN[4][27][37]MAIN[35][27][26]
MMCM_DRP[107] bit 6MAIN[4][26][36]MAIN[35][26][27]
MMCM_DRP[107] bit 7MAIN[4][27][36]MAIN[35][27][27]
MMCM_DRP[107] bit 8MAIN[4][26][35]MAIN[35][26][28]
MMCM_DRP[107] bit 9MAIN[4][27][35]MAIN[35][27][28]
MMCM_DRP[107] bit 10MAIN[4][26][34]MAIN[35][26][29]
MMCM_DRP[107] bit 11MAIN[4][27][34]MAIN[35][27][29]
MMCM_DRP[107] bit 12MAIN[4][26][33]MAIN[35][26][30]
MMCM_DRP[107] bit 13MAIN[4][27][33]MAIN[35][27][30]
MMCM_DRP[107] bit 14MAIN[4][26][32]MAIN[35][26][31]
MMCM_DRP[107] bit 15MAIN[4][27][32]MAIN[35][27][31]
MMCM_DRP[108] bit 0MAIN[4][26][31]MAIN[35][26][32]
MMCM_DRP[108] bit 1MAIN[4][27][31]MAIN[35][27][32]
MMCM_DRP[108] bit 2MAIN[4][26][30]MAIN[35][26][33]
MMCM_DRP[108] bit 3MAIN[4][27][30]MAIN[35][27][33]
MMCM_DRP[108] bit 4MAIN[4][26][29]MAIN[35][26][34]
MMCM_DRP[108] bit 5MAIN[4][27][29]MAIN[35][27][34]
MMCM_DRP[108] bit 6MAIN[4][26][28]MAIN[35][26][35]
MMCM_DRP[108] bit 7MAIN[4][27][28]MAIN[35][27][35]
MMCM_DRP[108] bit 8MAIN[4][26][27]MAIN[35][26][36]
MMCM_DRP[108] bit 9MAIN[4][27][27]MAIN[35][27][36]
MMCM_DRP[108] bit 10MAIN[4][26][26]MAIN[35][26][37]
MMCM_DRP[108] bit 11MAIN[4][27][26]MAIN[35][27][37]
MMCM_DRP[108] bit 12MAIN[4][26][25]MAIN[35][26][38]
MMCM_DRP[108] bit 13MAIN[4][27][25]MAIN[35][27][38]
MMCM_DRP[108] bit 14MAIN[4][26][24]MAIN[35][26][39]
MMCM_DRP[108] bit 15MAIN[4][27][24]MAIN[35][27][39]
MMCM_DRP[109] bit 0MAIN[4][26][23]MAIN[35][26][40]
MMCM_DRP[109] bit 1MAIN[4][27][23]MAIN[35][27][40]
MMCM_DRP[109] bit 2MAIN[4][26][22]MAIN[35][26][41]
MMCM_DRP[109] bit 3MAIN[4][27][22]MAIN[35][27][41]
MMCM_DRP[109] bit 4MAIN[4][26][21]MAIN[35][26][42]
MMCM_DRP[109] bit 5MAIN[4][27][21]MAIN[35][27][42]
MMCM_DRP[109] bit 6MAIN[4][26][20]MAIN[35][26][43]
MMCM_DRP[109] bit 7MAIN[4][27][20]MAIN[35][27][43]
MMCM_DRP[109] bit 8MAIN[4][26][19]MAIN[35][26][44]
MMCM_DRP[109] bit 9MAIN[4][27][19]MAIN[35][27][44]
MMCM_DRP[109] bit 10MAIN[4][26][18]MAIN[35][26][45]
MMCM_DRP[109] bit 11MAIN[4][27][18]MAIN[35][27][45]
MMCM_DRP[109] bit 12MAIN[4][26][17]MAIN[35][26][46]
MMCM_DRP[109] bit 13MAIN[4][27][17]MAIN[35][27][46]
MMCM_DRP[109] bit 14MAIN[4][26][16]MAIN[35][26][47]
MMCM_DRP[109] bit 15MAIN[4][27][16]MAIN[35][27][47]
MMCM_DRP[110] bit 0MAIN[4][26][15]MAIN[35][26][48]
MMCM_DRP[110] bit 1MAIN[4][27][15]MAIN[35][27][48]
MMCM_DRP[110] bit 2MAIN[4][26][14]MAIN[35][26][49]
MMCM_DRP[110] bit 3MAIN[4][27][14]MAIN[35][27][49]
MMCM_DRP[110] bit 4MAIN[4][26][13]MAIN[35][26][50]
MMCM_DRP[110] bit 5MAIN[4][27][13]MAIN[35][27][50]
MMCM_DRP[110] bit 6MAIN[4][26][12]MAIN[35][26][51]
MMCM_DRP[110] bit 7MAIN[4][27][12]MAIN[35][27][51]
MMCM_DRP[110] bit 8MAIN[4][26][11]MAIN[35][26][52]
MMCM_DRP[110] bit 9MAIN[4][27][11]MAIN[35][27][52]
MMCM_DRP[110] bit 10MAIN[4][26][10]MAIN[35][26][53]
MMCM_DRP[110] bit 11MAIN[4][27][10]MAIN[35][27][53]
MMCM_DRP[110] bit 12MAIN[4][26][9]MAIN[35][26][54]
MMCM_DRP[110] bit 13MAIN[4][27][9]MAIN[35][27][54]
MMCM_DRP[110] bit 14MAIN[4][26][8]MAIN[35][26][55]
MMCM_DRP[110] bit 15MAIN[4][27][8]MAIN[35][27][55]
MMCM_DRP[111] bit 0MAIN[4][26][7]MAIN[35][26][56]
MMCM_DRP[111] bit 1MAIN[4][27][7]MAIN[35][27][56]
MMCM_DRP[111] bit 2MAIN[4][26][6]MAIN[35][26][57]
MMCM_DRP[111] bit 3MAIN[4][27][6]MAIN[35][27][57]
MMCM_DRP[111] bit 4MAIN[4][26][5]MAIN[35][26][58]
MMCM_DRP[111] bit 5MAIN[4][27][5]MAIN[35][27][58]
MMCM_DRP[111] bit 6MAIN[4][26][4]MAIN[35][26][59]
MMCM_DRP[111] bit 7MAIN[4][27][4]MAIN[35][27][59]
MMCM_DRP[111] bit 8MAIN[4][26][3]MAIN[35][26][60]
MMCM_DRP[111] bit 9MAIN[4][27][3]MAIN[35][27][60]
MMCM_DRP[111] bit 10MAIN[4][26][2]MAIN[35][26][61]
MMCM_DRP[111] bit 11MAIN[4][27][2]MAIN[35][27][61]
MMCM_DRP[111] bit 12MAIN[4][26][1]MAIN[35][26][62]
MMCM_DRP[111] bit 13MAIN[4][27][1]MAIN[35][27][62]
MMCM_DRP[111] bit 14MAIN[4][26][0]MAIN[35][26][63]
MMCM_DRP[111] bit 15MAIN[4][27][0]MAIN[35][27][63]
MMCM_DRP[112] bit 0MAIN[3][26][63]MAIN[36][26][0]
MMCM_DRP[112] bit 1MAIN[3][27][63]MAIN[36][27][0]
MMCM_DRP[112] bit 2MAIN[3][26][62]MAIN[36][26][1]
MMCM_DRP[112] bit 3MAIN[3][27][62]MAIN[36][27][1]
MMCM_DRP[112] bit 4MAIN[3][26][61]MAIN[36][26][2]
MMCM_DRP[112] bit 5MAIN[3][27][61]MAIN[36][27][2]
MMCM_DRP[112] bit 6MAIN[3][26][60]MAIN[36][26][3]
MMCM_DRP[112] bit 7MAIN[3][27][60]MAIN[36][27][3]
MMCM_DRP[112] bit 8MAIN[3][26][59]MAIN[36][26][4]
MMCM_DRP[112] bit 9MAIN[3][27][59]MAIN[36][27][4]
MMCM_DRP[112] bit 10MAIN[3][26][58]MAIN[36][26][5]
MMCM_DRP[112] bit 11MAIN[3][27][58]MAIN[36][27][5]
MMCM_DRP[112] bit 12MAIN[3][26][57]MAIN[36][26][6]
MMCM_DRP[112] bit 13MAIN[3][27][57]MAIN[36][27][6]
MMCM_DRP[112] bit 14MAIN[3][26][56]MAIN[36][26][7]
MMCM_DRP[112] bit 15MAIN[3][27][56]MAIN[36][27][7]
MMCM_DRP[113] bit 0MAIN[3][26][55]MAIN[36][26][8]
MMCM_DRP[113] bit 1MAIN[3][27][55]MAIN[36][27][8]
MMCM_DRP[113] bit 2MAIN[3][26][54]MAIN[36][26][9]
MMCM_DRP[113] bit 3MAIN[3][27][54]MAIN[36][27][9]
MMCM_DRP[113] bit 4MAIN[3][26][53]MAIN[36][26][10]
MMCM_DRP[113] bit 5MAIN[3][27][53]MAIN[36][27][10]
MMCM_DRP[113] bit 6MAIN[3][26][52]MAIN[36][26][11]
MMCM_DRP[113] bit 7MAIN[3][27][52]MAIN[36][27][11]
MMCM_DRP[113] bit 8MAIN[3][26][51]MAIN[36][26][12]
MMCM_DRP[113] bit 9MAIN[3][27][51]MAIN[36][27][12]
MMCM_DRP[113] bit 10MAIN[3][26][50]MAIN[36][26][13]
MMCM_DRP[113] bit 11MAIN[3][27][50]MAIN[36][27][13]
MMCM_DRP[113] bit 12MAIN[3][26][49]MAIN[36][26][14]
MMCM_DRP[113] bit 13MAIN[3][27][49]MAIN[36][27][14]
MMCM_DRP[113] bit 14MAIN[3][26][48]MAIN[36][26][15]
MMCM_DRP[113] bit 15MAIN[3][27][48]MAIN[36][27][15]
MMCM_DRP[114] bit 0MAIN[3][26][47]MAIN[36][26][16]
MMCM_DRP[114] bit 1MAIN[3][27][47]MAIN[36][27][16]
MMCM_DRP[114] bit 2MAIN[3][26][46]MAIN[36][26][17]
MMCM_DRP[114] bit 3MAIN[3][27][46]MAIN[36][27][17]
MMCM_DRP[114] bit 4MAIN[3][26][45]MAIN[36][26][18]
MMCM_DRP[114] bit 5MAIN[3][27][45]MAIN[36][27][18]
MMCM_DRP[114] bit 6MAIN[3][26][44]MAIN[36][26][19]
MMCM_DRP[114] bit 7MAIN[3][27][44]MAIN[36][27][19]
MMCM_DRP[114] bit 8MAIN[3][26][43]MAIN[36][26][20]
MMCM_DRP[114] bit 9MAIN[3][27][43]MAIN[36][27][20]
MMCM_DRP[114] bit 10MAIN[3][26][42]MAIN[36][26][21]
MMCM_DRP[114] bit 11MAIN[3][27][42]MAIN[36][27][21]
MMCM_DRP[114] bit 12MAIN[3][26][41]MAIN[36][26][22]
MMCM_DRP[114] bit 13MAIN[3][27][41]MAIN[36][27][22]
MMCM_DRP[114] bit 14MAIN[3][26][40]MAIN[36][26][23]
MMCM_DRP[114] bit 15MAIN[3][27][40]MAIN[36][27][23]
MMCM_DRP[115] bit 0MAIN[3][26][39]MAIN[36][26][24]
MMCM_DRP[115] bit 1MAIN[3][27][39]MAIN[36][27][24]
MMCM_DRP[115] bit 2MAIN[3][26][38]MAIN[36][26][25]
MMCM_DRP[115] bit 3MAIN[3][27][38]MAIN[36][27][25]
MMCM_DRP[115] bit 4MAIN[3][26][37]MAIN[36][26][26]
MMCM_DRP[115] bit 5MAIN[3][27][37]MAIN[36][27][26]
MMCM_DRP[115] bit 6MAIN[3][26][36]MAIN[36][26][27]
MMCM_DRP[115] bit 7MAIN[3][27][36]MAIN[36][27][27]
MMCM_DRP[115] bit 8MAIN[3][26][35]MAIN[36][26][28]
MMCM_DRP[115] bit 9MAIN[3][27][35]MAIN[36][27][28]
MMCM_DRP[115] bit 10MAIN[3][26][34]MAIN[36][26][29]
MMCM_DRP[115] bit 11MAIN[3][27][34]MAIN[36][27][29]
MMCM_DRP[115] bit 12MAIN[3][26][33]MAIN[36][26][30]
MMCM_DRP[115] bit 13MAIN[3][27][33]MAIN[36][27][30]
MMCM_DRP[115] bit 14MAIN[3][26][32]MAIN[36][26][31]
MMCM_DRP[115] bit 15MAIN[3][27][32]MAIN[36][27][31]
MMCM_DRP[116] bit 0MAIN[3][26][31]MAIN[36][26][32]
MMCM_DRP[116] bit 1MAIN[3][27][31]MAIN[36][27][32]
MMCM_DRP[116] bit 2MAIN[3][26][30]MAIN[36][26][33]
MMCM_DRP[116] bit 3MAIN[3][27][30]MAIN[36][27][33]
MMCM_DRP[116] bit 4MAIN[3][26][29]MAIN[36][26][34]
MMCM_DRP[116] bit 5MAIN[3][27][29]MAIN[36][27][34]
MMCM_DRP[116] bit 6MAIN[3][26][28]MAIN[36][26][35]
MMCM_DRP[116] bit 7MAIN[3][27][28]MAIN[36][27][35]
MMCM_DRP[116] bit 8MAIN[3][26][27]MAIN[36][26][36]
MMCM_DRP[116] bit 9MAIN[3][27][27]MAIN[36][27][36]
MMCM_DRP[116] bit 10MAIN[3][26][26]MAIN[36][26][37]
MMCM_DRP[116] bit 11MAIN[3][27][26]MAIN[36][27][37]
MMCM_DRP[116] bit 12MAIN[3][26][25]MAIN[36][26][38]
MMCM_DRP[116] bit 13MAIN[3][27][25]MAIN[36][27][38]
MMCM_DRP[116] bit 14MAIN[3][26][24]MAIN[36][26][39]
MMCM_DRP[116] bit 15MAIN[3][27][24]MAIN[36][27][39]
MMCM_DRP[117] bit 0MAIN[3][26][23]MAIN[36][26][40]
MMCM_DRP[117] bit 1MAIN[3][27][23]MAIN[36][27][40]
MMCM_DRP[117] bit 2MAIN[3][26][22]MAIN[36][26][41]
MMCM_DRP[117] bit 3MAIN[3][27][22]MAIN[36][27][41]
MMCM_DRP[117] bit 4MAIN[3][26][21]MAIN[36][26][42]
MMCM_DRP[117] bit 5MAIN[3][27][21]MAIN[36][27][42]
MMCM_DRP[117] bit 6MAIN[3][26][20]MAIN[36][26][43]
MMCM_DRP[117] bit 7MAIN[3][27][20]MAIN[36][27][43]
MMCM_DRP[117] bit 8MAIN[3][26][19]MAIN[36][26][44]
MMCM_DRP[117] bit 9MAIN[3][27][19]MAIN[36][27][44]
MMCM_DRP[117] bit 10MAIN[3][26][18]MAIN[36][26][45]
MMCM_DRP[117] bit 11MAIN[3][27][18]MAIN[36][27][45]
MMCM_DRP[117] bit 12MAIN[3][26][17]MAIN[36][26][46]
MMCM_DRP[117] bit 13MAIN[3][27][17]MAIN[36][27][46]
MMCM_DRP[117] bit 14MAIN[3][26][16]MAIN[36][26][47]
MMCM_DRP[117] bit 15MAIN[3][27][16]MAIN[36][27][47]
MMCM_DRP[118] bit 0MAIN[3][26][15]MAIN[36][26][48]
MMCM_DRP[118] bit 1MAIN[3][27][15]MAIN[36][27][48]
MMCM_DRP[118] bit 2MAIN[3][26][14]MAIN[36][26][49]
MMCM_DRP[118] bit 3MAIN[3][27][14]MAIN[36][27][49]
MMCM_DRP[118] bit 4MAIN[3][26][13]MAIN[36][26][50]
MMCM_DRP[118] bit 5MAIN[3][27][13]MAIN[36][27][50]
MMCM_DRP[118] bit 6MAIN[3][26][12]MAIN[36][26][51]
MMCM_DRP[118] bit 7MAIN[3][27][12]MAIN[36][27][51]
MMCM_DRP[118] bit 8MAIN[3][26][11]MAIN[36][26][52]
MMCM_DRP[118] bit 9MAIN[3][27][11]MAIN[36][27][52]
MMCM_DRP[118] bit 10MAIN[3][26][10]MAIN[36][26][53]
MMCM_DRP[118] bit 11MAIN[3][27][10]MAIN[36][27][53]
MMCM_DRP[118] bit 12MAIN[3][26][9]MAIN[36][26][54]
MMCM_DRP[118] bit 13MAIN[3][27][9]MAIN[36][27][54]
MMCM_DRP[118] bit 14MAIN[3][26][8]MAIN[36][26][55]
MMCM_DRP[118] bit 15MAIN[3][27][8]MAIN[36][27][55]
MMCM_DRP[119] bit 0MAIN[3][26][7]MAIN[36][26][56]
MMCM_DRP[119] bit 1MAIN[3][27][7]MAIN[36][27][56]
MMCM_DRP[119] bit 2MAIN[3][26][6]MAIN[36][26][57]
MMCM_DRP[119] bit 3MAIN[3][27][6]MAIN[36][27][57]
MMCM_DRP[119] bit 4MAIN[3][26][5]MAIN[36][26][58]
MMCM_DRP[119] bit 5MAIN[3][27][5]MAIN[36][27][58]
MMCM_DRP[119] bit 6MAIN[3][26][4]MAIN[36][26][59]
MMCM_DRP[119] bit 7MAIN[3][27][4]MAIN[36][27][59]
MMCM_DRP[119] bit 8MAIN[3][26][3]MAIN[36][26][60]
MMCM_DRP[119] bit 9MAIN[3][27][3]MAIN[36][27][60]
MMCM_DRP[119] bit 10MAIN[3][26][2]MAIN[36][26][61]
MMCM_DRP[119] bit 11MAIN[3][27][2]MAIN[36][27][61]
MMCM_DRP[119] bit 12MAIN[3][26][1]MAIN[36][26][62]
MMCM_DRP[119] bit 13MAIN[3][27][1]MAIN[36][27][62]
MMCM_DRP[119] bit 14MAIN[3][26][0]MAIN[36][26][63]
MMCM_DRP[119] bit 15MAIN[3][27][0]MAIN[36][27][63]
MMCM_DRP[120] bit 0MAIN[2][26][63]MAIN[37][26][0]
MMCM_DRP[120] bit 1MAIN[2][27][63]MAIN[37][27][0]
MMCM_DRP[120] bit 2MAIN[2][26][62]MAIN[37][26][1]
MMCM_DRP[120] bit 3MAIN[2][27][62]MAIN[37][27][1]
MMCM_DRP[120] bit 4MAIN[2][26][61]MAIN[37][26][2]
MMCM_DRP[120] bit 5MAIN[2][27][61]MAIN[37][27][2]
MMCM_DRP[120] bit 6MAIN[2][26][60]MAIN[37][26][3]
MMCM_DRP[120] bit 7MAIN[2][27][60]MAIN[37][27][3]
MMCM_DRP[120] bit 8MAIN[2][26][59]MAIN[37][26][4]
MMCM_DRP[120] bit 9MAIN[2][27][59]MAIN[37][27][4]
MMCM_DRP[120] bit 10MAIN[2][26][58]MAIN[37][26][5]
MMCM_DRP[120] bit 11MAIN[2][27][58]MAIN[37][27][5]
MMCM_DRP[120] bit 12MAIN[2][26][57]MAIN[37][26][6]
MMCM_DRP[120] bit 13MAIN[2][27][57]MAIN[37][27][6]
MMCM_DRP[120] bit 14MAIN[2][26][56]MAIN[37][26][7]
MMCM_DRP[120] bit 15MAIN[2][27][56]MAIN[37][27][7]
MMCM_DRP[121] bit 0MAIN[2][26][55]MAIN[37][26][8]
MMCM_DRP[121] bit 1MAIN[2][27][55]MAIN[37][27][8]
MMCM_DRP[121] bit 2MAIN[2][26][54]MAIN[37][26][9]
MMCM_DRP[121] bit 3MAIN[2][27][54]MAIN[37][27][9]
MMCM_DRP[121] bit 4MAIN[2][26][53]MAIN[37][26][10]
MMCM_DRP[121] bit 5MAIN[2][27][53]MAIN[37][27][10]
MMCM_DRP[121] bit 6MAIN[2][26][52]MAIN[37][26][11]
MMCM_DRP[121] bit 7MAIN[2][27][52]MAIN[37][27][11]
MMCM_DRP[121] bit 8MAIN[2][26][51]MAIN[37][26][12]
MMCM_DRP[121] bit 9MAIN[2][27][51]MAIN[37][27][12]
MMCM_DRP[121] bit 10MAIN[2][26][50]MAIN[37][26][13]
MMCM_DRP[121] bit 11MAIN[2][27][50]MAIN[37][27][13]
MMCM_DRP[121] bit 12MAIN[2][26][49]MAIN[37][26][14]
MMCM_DRP[121] bit 13MAIN[2][27][49]MAIN[37][27][14]
MMCM_DRP[121] bit 14MAIN[2][26][48]MAIN[37][26][15]
MMCM_DRP[121] bit 15MAIN[2][27][48]MAIN[37][27][15]
MMCM_DRP[122] bit 0MAIN[2][26][47]MAIN[37][26][16]
MMCM_DRP[122] bit 1MAIN[2][27][47]MAIN[37][27][16]
MMCM_DRP[122] bit 2MAIN[2][26][46]MAIN[37][26][17]
MMCM_DRP[122] bit 3MAIN[2][27][46]MAIN[37][27][17]
MMCM_DRP[122] bit 4MAIN[2][26][45]MAIN[37][26][18]
MMCM_DRP[122] bit 5MAIN[2][27][45]MAIN[37][27][18]
MMCM_DRP[122] bit 6MAIN[2][26][44]MAIN[37][26][19]
MMCM_DRP[122] bit 7MAIN[2][27][44]MAIN[37][27][19]
MMCM_DRP[122] bit 8MAIN[2][26][43]MAIN[37][26][20]
MMCM_DRP[122] bit 9MAIN[2][27][43]MAIN[37][27][20]
MMCM_DRP[122] bit 10MAIN[2][26][42]MAIN[37][26][21]
MMCM_DRP[122] bit 11MAIN[2][27][42]MAIN[37][27][21]
MMCM_DRP[122] bit 12MAIN[2][26][41]MAIN[37][26][22]
MMCM_DRP[122] bit 13MAIN[2][27][41]MAIN[37][27][22]
MMCM_DRP[122] bit 14MAIN[2][26][40]MAIN[37][26][23]
MMCM_DRP[122] bit 15MAIN[2][27][40]MAIN[37][27][23]
MMCM_DRP[123] bit 0MAIN[2][26][39]MAIN[37][26][24]
MMCM_DRP[123] bit 1MAIN[2][27][39]MAIN[37][27][24]
MMCM_DRP[123] bit 2MAIN[2][26][38]MAIN[37][26][25]
MMCM_DRP[123] bit 3MAIN[2][27][38]MAIN[37][27][25]
MMCM_DRP[123] bit 4MAIN[2][26][37]MAIN[37][26][26]
MMCM_DRP[123] bit 5MAIN[2][27][37]MAIN[37][27][26]
MMCM_DRP[123] bit 6MAIN[2][26][36]MAIN[37][26][27]
MMCM_DRP[123] bit 7MAIN[2][27][36]MAIN[37][27][27]
MMCM_DRP[123] bit 8MAIN[2][26][35]MAIN[37][26][28]
MMCM_DRP[123] bit 9MAIN[2][27][35]MAIN[37][27][28]
MMCM_DRP[123] bit 10MAIN[2][26][34]MAIN[37][26][29]
MMCM_DRP[123] bit 11MAIN[2][27][34]MAIN[37][27][29]
MMCM_DRP[123] bit 12MAIN[2][26][33]MAIN[37][26][30]
MMCM_DRP[123] bit 13MAIN[2][27][33]MAIN[37][27][30]
MMCM_DRP[123] bit 14MAIN[2][26][32]MAIN[37][26][31]
MMCM_DRP[123] bit 15MAIN[2][27][32]MAIN[37][27][31]
MMCM_DRP[124] bit 0MAIN[2][26][31]MAIN[37][26][32]
MMCM_DRP[124] bit 1MAIN[2][27][31]MAIN[37][27][32]
MMCM_DRP[124] bit 2MAIN[2][26][30]MAIN[37][26][33]
MMCM_DRP[124] bit 3MAIN[2][27][30]MAIN[37][27][33]
MMCM_DRP[124] bit 4MAIN[2][26][29]MAIN[37][26][34]
MMCM_DRP[124] bit 5MAIN[2][27][29]MAIN[37][27][34]
MMCM_DRP[124] bit 6MAIN[2][26][28]MAIN[37][26][35]
MMCM_DRP[124] bit 7MAIN[2][27][28]MAIN[37][27][35]
MMCM_DRP[124] bit 8MAIN[2][26][27]MAIN[37][26][36]
MMCM_DRP[124] bit 9MAIN[2][27][27]MAIN[37][27][36]
MMCM_DRP[124] bit 10MAIN[2][26][26]MAIN[37][26][37]
MMCM_DRP[124] bit 11MAIN[2][27][26]MAIN[37][27][37]
MMCM_DRP[124] bit 12MAIN[2][26][25]MAIN[37][26][38]
MMCM_DRP[124] bit 13MAIN[2][27][25]MAIN[37][27][38]
MMCM_DRP[124] bit 14MAIN[2][26][24]MAIN[37][26][39]
MMCM_DRP[124] bit 15MAIN[2][27][24]MAIN[37][27][39]
MMCM_DRP[125] bit 0MAIN[2][26][23]MAIN[37][26][40]
MMCM_DRP[125] bit 1MAIN[2][27][23]MAIN[37][27][40]
MMCM_DRP[125] bit 2MAIN[2][26][22]MAIN[37][26][41]
MMCM_DRP[125] bit 3MAIN[2][27][22]MAIN[37][27][41]
MMCM_DRP[125] bit 4MAIN[2][26][21]MAIN[37][26][42]
MMCM_DRP[125] bit 5MAIN[2][27][21]MAIN[37][27][42]
MMCM_DRP[125] bit 6MAIN[2][26][20]MAIN[37][26][43]
MMCM_DRP[125] bit 7MAIN[2][27][20]MAIN[37][27][43]
MMCM_DRP[125] bit 8MAIN[2][26][19]MAIN[37][26][44]
MMCM_DRP[125] bit 9MAIN[2][27][19]MAIN[37][27][44]
MMCM_DRP[125] bit 10MAIN[2][26][18]MAIN[37][26][45]
MMCM_DRP[125] bit 11MAIN[2][27][18]MAIN[37][27][45]
MMCM_DRP[125] bit 12MAIN[2][26][17]MAIN[37][26][46]
MMCM_DRP[125] bit 13MAIN[2][27][17]MAIN[37][27][46]
MMCM_DRP[125] bit 14MAIN[2][26][16]MAIN[37][26][47]
MMCM_DRP[125] bit 15MAIN[2][27][16]MAIN[37][27][47]
MMCM_DRP[126] bit 0MAIN[2][26][15]MAIN[37][26][48]
MMCM_DRP[126] bit 1MAIN[2][27][15]MAIN[37][27][48]
MMCM_DRP[126] bit 2MAIN[2][26][14]MAIN[37][26][49]
MMCM_DRP[126] bit 3MAIN[2][27][14]MAIN[37][27][49]
MMCM_DRP[126] bit 4MAIN[2][26][13]MAIN[37][26][50]
MMCM_DRP[126] bit 5MAIN[2][27][13]MAIN[37][27][50]
MMCM_DRP[126] bit 6MAIN[2][26][12]MAIN[37][26][51]
MMCM_DRP[126] bit 7MAIN[2][27][12]MAIN[37][27][51]
MMCM_DRP[126] bit 8MAIN[2][26][11]MAIN[37][26][52]
MMCM_DRP[126] bit 9MAIN[2][27][11]MAIN[37][27][52]
MMCM_DRP[126] bit 10MAIN[2][26][10]MAIN[37][26][53]
MMCM_DRP[126] bit 11MAIN[2][27][10]MAIN[37][27][53]
MMCM_DRP[126] bit 12MAIN[2][26][9]MAIN[37][26][54]
MMCM_DRP[126] bit 13MAIN[2][27][9]MAIN[37][27][54]
MMCM_DRP[126] bit 14MAIN[2][26][8]MAIN[37][26][55]
MMCM_DRP[126] bit 15MAIN[2][27][8]MAIN[37][27][55]
MMCM_DRP[127] bit 0MAIN[2][26][7]MAIN[37][26][56]
MMCM_DRP[127] bit 1MAIN[2][27][7]MAIN[37][27][56]
MMCM_DRP[127] bit 2MAIN[2][26][6]MAIN[37][26][57]
MMCM_DRP[127] bit 3MAIN[2][27][6]MAIN[37][27][57]
MMCM_DRP[127] bit 4MAIN[2][26][5]MAIN[37][26][58]
MMCM_DRP[127] bit 5MAIN[2][27][5]MAIN[37][27][58]
MMCM_DRP[127] bit 6MAIN[2][26][4]MAIN[37][26][59]
MMCM_DRP[127] bit 7MAIN[2][27][4]MAIN[37][27][59]
MMCM_DRP[127] bit 8MAIN[2][26][3]MAIN[37][26][60]
MMCM_DRP[127] bit 9MAIN[2][27][3]MAIN[37][27][60]
MMCM_DRP[127] bit 10MAIN[2][26][2]MAIN[37][26][61]
MMCM_DRP[127] bit 11MAIN[2][27][2]MAIN[37][27][61]
MMCM_DRP[127] bit 12MAIN[2][26][1]MAIN[37][26][62]
MMCM_DRP[127] bit 13MAIN[2][27][1]MAIN[37][27][62]
MMCM_DRP[127] bit 14MAIN[2][26][0]MAIN[37][26][63]
MMCM_DRP[127] bit 15MAIN[2][27][0]MAIN[37][27][63]
ENABLEMAIN[3][26][31]MAIN[36][26][32]
STARTUP_WAITMAIN[3][26][30]MAIN[36][26][33]
DIRECT_PATH_CNTRLMAIN[17][27][22]MAIN[22][27][41]
GTS_WAITMAIN[3][27][30]MAIN[36][27][33]
EN_VCO_DIV1MAIN[13][27][47]MAIN[26][27][16]
EN_VCO_DIV6MAIN[13][26][47]MAIN[26][26][16]
HVLF_CNT_TEST_ENMAIN[14][27][36]MAIN[25][27][27]
IN_DLY_ENMAIN[17][27][16]MAIN[22][27][47]
VLF_HIGH_DIS_BMAIN[9][27][44]MAIN[30][27][19]
VLF_HIGH_PWDN_BMAIN[9][26][15]MAIN[30][26][48]
TMUX_MUX_SEL bit 0MAIN[17][26][24]MAIN[22][26][39]
TMUX_MUX_SEL bit 1MAIN[17][27][24]MAIN[22][27][39]
CONTROL_0 bit 0MAIN[3][26][15]MAIN[36][26][48]
CONTROL_0 bit 1MAIN[3][27][15]MAIN[36][27][48]
CONTROL_0 bit 2MAIN[3][26][14]MAIN[36][26][49]
CONTROL_0 bit 3MAIN[3][27][14]MAIN[36][27][49]
CONTROL_0 bit 4MAIN[3][26][13]MAIN[36][26][50]
CONTROL_0 bit 5MAIN[3][27][13]MAIN[36][27][50]
CONTROL_0 bit 6MAIN[3][26][12]MAIN[36][26][51]
CONTROL_0 bit 7MAIN[3][27][12]MAIN[36][27][51]
CONTROL_0 bit 8MAIN[3][26][11]MAIN[36][26][52]
CONTROL_0 bit 9MAIN[3][27][11]MAIN[36][27][52]
CONTROL_0 bit 10MAIN[3][26][10]MAIN[36][26][53]
CONTROL_0 bit 11MAIN[3][27][10]MAIN[36][27][53]
CONTROL_0 bit 12MAIN[3][26][9]MAIN[36][26][54]
CONTROL_0 bit 13MAIN[3][27][9]MAIN[36][27][54]
CONTROL_0 bit 14MAIN[3][26][8]MAIN[36][26][55]
CONTROL_0 bit 15MAIN[3][27][8]MAIN[36][27][55]
CONTROL_1 bit 0MAIN[3][26][7]MAIN[36][26][56]
CONTROL_1 bit 1MAIN[3][27][7]MAIN[36][27][56]
CONTROL_1 bit 2MAIN[3][26][6]MAIN[36][26][57]
CONTROL_1 bit 3MAIN[3][27][6]MAIN[36][27][57]
CONTROL_1 bit 4MAIN[3][26][5]MAIN[36][26][58]
CONTROL_1 bit 5MAIN[3][27][5]MAIN[36][27][58]
CONTROL_1 bit 6MAIN[3][26][4]MAIN[36][26][59]
CONTROL_1 bit 7MAIN[3][27][4]MAIN[36][27][59]
CONTROL_1 bit 8MAIN[3][26][3]MAIN[36][26][60]
CONTROL_1 bit 9MAIN[3][27][3]MAIN[36][27][60]
CONTROL_1 bit 10MAIN[3][26][2]MAIN[36][26][61]
CONTROL_1 bit 11MAIN[3][27][2]MAIN[36][27][61]
CONTROL_1 bit 12MAIN[3][26][1]MAIN[36][26][62]
CONTROL_1 bit 13MAIN[3][27][1]MAIN[36][27][62]
CONTROL_1 bit 14MAIN[3][26][0]MAIN[36][26][63]
CONTROL_1 bit 15MAIN[3][27][0]MAIN[36][27][63]
CONTROL_2 bit 0MAIN[2][26][63]MAIN[37][26][0]
CONTROL_2 bit 1MAIN[2][27][63]MAIN[37][27][0]
CONTROL_2 bit 2MAIN[2][26][62]MAIN[37][26][1]
CONTROL_2 bit 3MAIN[2][27][62]MAIN[37][27][1]
CONTROL_2 bit 4MAIN[2][26][61]MAIN[37][26][2]
CONTROL_2 bit 5MAIN[2][27][61]MAIN[37][27][2]
CONTROL_2 bit 6MAIN[2][26][60]MAIN[37][26][3]
CONTROL_2 bit 7MAIN[2][27][60]MAIN[37][27][3]
CONTROL_2 bit 8MAIN[2][26][59]MAIN[37][26][4]
CONTROL_2 bit 9MAIN[2][27][59]MAIN[37][27][4]
CONTROL_2 bit 10MAIN[2][26][58]MAIN[37][26][5]
CONTROL_2 bit 11MAIN[2][27][58]MAIN[37][27][5]
CONTROL_2 bit 12MAIN[2][26][57]MAIN[37][26][6]
CONTROL_2 bit 13MAIN[2][27][57]MAIN[37][27][6]
CONTROL_2 bit 14MAIN[2][26][56]MAIN[37][26][7]
CONTROL_2 bit 15MAIN[2][27][56]MAIN[37][27][7]
CONTROL_3 bit 0MAIN[2][26][55]MAIN[37][26][8]
CONTROL_3 bit 1MAIN[2][27][55]MAIN[37][27][8]
CONTROL_3 bit 2MAIN[2][26][54]MAIN[37][26][9]
CONTROL_3 bit 3MAIN[2][27][54]MAIN[37][27][9]
CONTROL_3 bit 4MAIN[2][26][53]MAIN[37][26][10]
CONTROL_3 bit 5MAIN[2][27][53]MAIN[37][27][10]
CONTROL_3 bit 6MAIN[2][26][52]MAIN[37][26][11]
CONTROL_3 bit 7MAIN[2][27][52]MAIN[37][27][11]
CONTROL_3 bit 8MAIN[2][26][51]MAIN[37][26][12]
CONTROL_3 bit 9MAIN[2][27][51]MAIN[37][27][12]
CONTROL_3 bit 10MAIN[2][26][50]MAIN[37][26][13]
CONTROL_3 bit 11MAIN[2][27][50]MAIN[37][27][13]
CONTROL_3 bit 12MAIN[2][26][49]MAIN[37][26][14]
CONTROL_3 bit 13MAIN[2][27][49]MAIN[37][27][14]
CONTROL_3 bit 14MAIN[2][26][48]MAIN[37][26][15]
CONTROL_3 bit 15MAIN[2][27][48]MAIN[37][27][15]
CONTROL_4 bit 0MAIN[2][26][47]MAIN[37][26][16]
CONTROL_4 bit 1MAIN[2][27][47]MAIN[37][27][16]
CONTROL_4 bit 2MAIN[2][26][46]MAIN[37][26][17]
CONTROL_4 bit 3MAIN[2][27][46]MAIN[37][27][17]
CONTROL_4 bit 4MAIN[2][26][45]MAIN[37][26][18]
CONTROL_4 bit 5MAIN[2][27][45]MAIN[37][27][18]
CONTROL_4 bit 6MAIN[2][26][44]MAIN[37][26][19]
CONTROL_4 bit 7MAIN[2][27][44]MAIN[37][27][19]
CONTROL_4 bit 8MAIN[2][26][43]MAIN[37][26][20]
CONTROL_4 bit 9MAIN[2][27][43]MAIN[37][27][20]
CONTROL_4 bit 10MAIN[2][26][42]MAIN[37][26][21]
CONTROL_4 bit 11MAIN[2][27][42]MAIN[37][27][21]
CONTROL_4 bit 12MAIN[2][26][41]MAIN[37][26][22]
CONTROL_4 bit 13MAIN[2][27][41]MAIN[37][27][22]
CONTROL_4 bit 14MAIN[2][26][40]MAIN[37][26][23]
CONTROL_4 bit 15MAIN[2][27][40]MAIN[37][27][23]
CONTROL_5 bit 0MAIN[2][26][39]MAIN[37][26][24]
CONTROL_5 bit 1MAIN[2][27][39]MAIN[37][27][24]
CONTROL_5 bit 2MAIN[2][26][38]MAIN[37][26][25]
CONTROL_5 bit 3MAIN[2][27][38]MAIN[37][27][25]
CONTROL_5 bit 4MAIN[2][26][37]MAIN[37][26][26]
CONTROL_5 bit 5MAIN[2][27][37]MAIN[37][27][26]
CONTROL_5 bit 6MAIN[2][26][36]MAIN[37][26][27]
CONTROL_5 bit 7MAIN[2][27][36]MAIN[37][27][27]
CONTROL_5 bit 8MAIN[2][26][35]MAIN[37][26][28]
CONTROL_5 bit 9MAIN[2][27][35]MAIN[37][27][28]
CONTROL_5 bit 10MAIN[2][26][34]MAIN[37][26][29]
CONTROL_5 bit 11MAIN[2][27][34]MAIN[37][27][29]
CONTROL_5 bit 12MAIN[2][26][33]MAIN[37][26][30]
CONTROL_5 bit 13MAIN[2][27][33]MAIN[37][27][30]
CONTROL_5 bit 14MAIN[2][26][32]MAIN[37][26][31]
CONTROL_5 bit 15MAIN[2][27][32]MAIN[37][27][31]
ANALOG_MISC bit 0MAIN[13][27][14]MAIN[26][27][49]
ANALOG_MISC bit 1MAIN[13][26][13]MAIN[26][26][50]
ANALOG_MISC bit 2MAIN[13][27][12]MAIN[26][27][51]
ANALOG_MISC bit 3MAIN[13][26][11]MAIN[26][26][52]
CP_BIAS_TRIP_SET bit 0MAIN[8][27][12]MAIN[31][27][51]
CP_RES bit 0MAIN[8][27][14]MAIN[31][27][49]
CP_RES bit 1MAIN[8][26][13]MAIN[31][26][50]
V6_AVDD_COMP_SET bit 0MAIN[8][27][44]MAIN[31][27][19]
V6_AVDD_COMP_SET bit 1MAIN[8][26][43]MAIN[31][26][20]
AVDD_VBG_PD bit 0MAIN[8][26][45]MAIN[31][26][18]
AVDD_VBG_PD bit 1MAIN[8][27][45]MAIN[31][27][18]
AVDD_VBG_PD bit 2MAIN[8][26][44]MAIN[31][26][19]
AVDD_VBG_SEL bit 0MAIN[8][26][47]MAIN[31][26][16]
AVDD_VBG_SEL bit 1MAIN[8][27][47]MAIN[31][27][16]
AVDD_VBG_SEL bit 2MAIN[8][26][46]MAIN[31][26][17]
AVDD_VBG_SEL bit 3MAIN[8][27][46]MAIN[31][27][17]
V6_DVDD_COMP_SET bit 0MAIN[14][27][4]MAIN[25][27][59]
V6_DVDD_COMP_SET bit 1MAIN[14][26][3]MAIN[25][26][60]
DVDD_VBG_PD bit 0MAIN[14][26][5]MAIN[25][26][58]
DVDD_VBG_PD bit 1MAIN[14][27][5]MAIN[25][27][58]
DVDD_VBG_PD bit 2MAIN[14][26][4]MAIN[25][26][59]
DVDD_VBG_SEL bit 0MAIN[14][26][7]MAIN[25][26][56]
DVDD_VBG_SEL bit 1MAIN[14][27][7]MAIN[25][27][56]
DVDD_VBG_SEL bit 2MAIN[14][26][6]MAIN[25][26][57]
DVDD_VBG_SEL bit 3MAIN[14][27][6]MAIN[25][27][57]
IN_DLY_MX_CVDD bit 0MAIN[17][26][60]MAIN[22][26][3]
IN_DLY_MX_CVDD bit 1MAIN[17][27][60]MAIN[22][27][3]
IN_DLY_MX_CVDD bit 2MAIN[17][26][59]MAIN[22][26][4]
IN_DLY_MX_CVDD bit 3MAIN[17][27][59]MAIN[22][27][4]
IN_DLY_MX_CVDD bit 4MAIN[17][26][58]MAIN[22][26][5]
IN_DLY_MX_CVDD bit 5MAIN[17][27][58]MAIN[22][27][5]
IN_DLY_MX_DVDD bit 0MAIN[17][26][21]MAIN[22][26][42]
IN_DLY_MX_DVDD bit 1MAIN[17][27][21]MAIN[22][27][42]
IN_DLY_MX_DVDD bit 2MAIN[17][26][20]MAIN[22][26][43]
IN_DLY_MX_DVDD bit 3MAIN[17][27][20]MAIN[22][27][43]
IN_DLY_MX_DVDD bit 4MAIN[17][26][19]MAIN[22][26][44]
IN_DLY_MX_DVDD bit 5MAIN[17][27][19]MAIN[22][27][44]
LF_NEN bit 0MAIN[9][26][41]MAIN[30][26][22]
LF_NEN bit 1MAIN[9][27][40]MAIN[30][27][23]
LF_PEN bit 0MAIN[9][26][43]MAIN[30][26][20]
LF_PEN bit 1MAIN[9][27][42]MAIN[30][27][21]
MAN_LF bit 0MAIN[9][26][47]MAIN[30][26][16]
MAN_LF bit 1MAIN[9][27][46]MAIN[30][27][17]
MAN_LF bit 2MAIN[9][26][45]MAIN[30][26][18]
PFD bit 0MAIN[14][26][21]MAIN[25][26][42]
PFD bit 1MAIN[14][27][21]MAIN[25][27][42]
PFD bit 2MAIN[14][26][20]MAIN[25][26][43]
PFD bit 3MAIN[14][27][20]MAIN[25][27][43]
PFD bit 4MAIN[14][26][19]MAIN[25][26][44]
PFD bit 5MAIN[14][27][19]MAIN[25][27][44]
PFD bit 6MAIN[14][26][18]MAIN[25][26][45]
CP bit 0MAIN[8][26][11]MAIN[31][26][52]
CP bit 1MAIN[8][27][10]MAIN[31][27][53]
CP bit 2MAIN[8][26][9]MAIN[31][26][54]
CP bit 3MAIN[8][27][8]MAIN[31][27][55]
HROW_DLY_SET bit 0MAIN[17][26][57]MAIN[22][26][6]
HROW_DLY_SET bit 1MAIN[17][27][57]MAIN[22][27][6]
HROW_DLY_SET bit 2MAIN[17][26][56]MAIN[22][26][7]
HVLF_CNT_TEST bit 0MAIN[14][26][39]MAIN[25][26][24]
HVLF_CNT_TEST bit 1MAIN[14][27][39]MAIN[25][27][24]
HVLF_CNT_TEST bit 2MAIN[14][26][38]MAIN[25][26][25]
HVLF_CNT_TEST bit 3MAIN[14][27][38]MAIN[25][27][25]
HVLF_CNT_TEST bit 4MAIN[14][26][37]MAIN[25][26][26]
HVLF_CNT_TEST bit 5MAIN[14][27][37]MAIN[25][27][26]
LFHF bit 0MAIN[8][26][5]MAIN[31][26][58]
LFHF bit 1MAIN[8][27][4]MAIN[31][27][59]
LOCK_CNT bit 0MAIN[14][26][63]MAIN[25][26][0]
LOCK_CNT bit 1MAIN[14][27][63]MAIN[25][27][0]
LOCK_CNT bit 2MAIN[14][26][62]MAIN[25][26][1]
LOCK_CNT bit 3MAIN[14][27][62]MAIN[25][27][1]
LOCK_CNT bit 4MAIN[14][26][61]MAIN[25][26][2]
LOCK_CNT bit 5MAIN[14][27][61]MAIN[25][27][2]
LOCK_CNT bit 6MAIN[14][26][60]MAIN[25][26][3]
LOCK_CNT bit 7MAIN[14][27][60]MAIN[25][27][3]
LOCK_CNT bit 8MAIN[14][26][59]MAIN[25][26][4]
LOCK_CNT bit 9MAIN[14][27][59]MAIN[25][27][4]
LOCK_FB_DLY bit 0MAIN[14][26][50]MAIN[25][26][13]
LOCK_FB_DLY bit 1MAIN[14][27][50]MAIN[25][27][13]
LOCK_FB_DLY bit 2MAIN[14][26][49]MAIN[25][26][14]
LOCK_FB_DLY bit 3MAIN[14][27][49]MAIN[25][27][14]
LOCK_FB_DLY bit 4MAIN[14][26][48]MAIN[25][26][15]
LOCK_REF_DLY bit 0MAIN[14][26][42]MAIN[25][26][21]
LOCK_REF_DLY bit 1MAIN[14][27][42]MAIN[25][27][21]
LOCK_REF_DLY bit 2MAIN[14][26][41]MAIN[25][26][22]
LOCK_REF_DLY bit 3MAIN[14][27][41]MAIN[25][27][22]
LOCK_REF_DLY bit 4MAIN[14][26][40]MAIN[25][26][23]
LOCK_SAT_HIGH bit 0MAIN[14][26][47]MAIN[25][26][16]
LOCK_SAT_HIGH bit 1MAIN[14][27][47]MAIN[25][27][16]
LOCK_SAT_HIGH bit 2MAIN[14][26][46]MAIN[25][26][17]
LOCK_SAT_HIGH bit 3MAIN[14][27][46]MAIN[25][27][17]
LOCK_SAT_HIGH bit 4MAIN[14][26][45]MAIN[25][26][18]
LOCK_SAT_HIGH bit 5MAIN[14][27][45]MAIN[25][27][18]
LOCK_SAT_HIGH bit 6MAIN[14][26][44]MAIN[25][26][19]
LOCK_SAT_HIGH bit 7MAIN[14][27][44]MAIN[25][27][19]
LOCK_SAT_HIGH bit 8MAIN[14][26][43]MAIN[25][26][20]
LOCK_SAT_HIGH bit 9MAIN[14][27][43]MAIN[25][27][20]
RES bit 0MAIN[8][26][3]MAIN[31][26][60]
RES bit 1MAIN[8][27][2]MAIN[31][27][61]
RES bit 2MAIN[8][26][1]MAIN[31][26][62]
RES bit 3MAIN[8][27][0]MAIN[31][27][63]
UNLOCK_CNT bit 0MAIN[14][26][55]MAIN[25][26][8]
UNLOCK_CNT bit 1MAIN[14][27][55]MAIN[25][27][8]
UNLOCK_CNT bit 2MAIN[14][26][54]MAIN[25][26][9]
UNLOCK_CNT bit 3MAIN[14][27][54]MAIN[25][27][9]
UNLOCK_CNT bit 4MAIN[14][26][53]MAIN[25][26][10]
UNLOCK_CNT bit 5MAIN[14][27][53]MAIN[25][27][10]
UNLOCK_CNT bit 6MAIN[14][26][52]MAIN[25][26][11]
UNLOCK_CNT bit 7MAIN[14][27][52]MAIN[25][27][11]
UNLOCK_CNT bit 8MAIN[14][26][51]MAIN[25][26][12]
UNLOCK_CNT bit 9MAIN[14][27][51]MAIN[25][27][12]
V6_IN_DLY_SET bit 0MAIN[17][26][18]MAIN[22][26][45]
V6_IN_DLY_SET bit 1MAIN[17][27][18]MAIN[22][27][45]
V6_IN_DLY_SET bit 2MAIN[17][26][17]MAIN[22][26][46]
V6_IN_DLY_SET bit 3MAIN[17][27][17]MAIN[22][27][46]
V6_IN_DLY_SET bit 4MAIN[17][26][16]MAIN[22][26][47]
SYNTH_CLK_DIV bit 0MAIN[17][26][47]MAIN[22][26][16]
SYNTH_CLK_DIV bit 1MAIN[17][27][47]MAIN[22][27][16]
CLOCK_HOLDMAIN[3][27][31]MAIN[36][27][32]
CASC_LOCK_ENMAIN[3][26][29]MAIN[36][26][34]
HVLF_STEPMAIN[14][26][36]MAIN[25][26][27]
INTERP_EN bit 0MAIN[12][26][63]MAIN[27][26][0]
INTERP_EN bit 1MAIN[12][27][62]MAIN[27][27][1]
INTERP_EN bit 2MAIN[12][26][61]MAIN[27][26][2]
INTERP_EN bit 3MAIN[12][27][60]MAIN[27][27][3]
INTERP_EN bit 4MAIN[12][26][59]MAIN[27][26][4]
INTERP_EN bit 5MAIN[12][27][58]MAIN[27][27][5]
INTERP_EN bit 6MAIN[12][26][57]MAIN[27][26][6]
INTERP_EN bit 7MAIN[12][27][56]MAIN[27][27][7]
CLKBURST_ENABLEMAIN[17][26][25]MAIN[22][26][38]
CLKBURST_REPEATMAIN[17][27][25]MAIN[22][27][38]
CLKBURST_CNT bit 0MAIN[17][26][27]MAIN[22][26][36]
CLKBURST_CNT bit 1MAIN[17][27][27]MAIN[22][27][36]
CLKBURST_CNT bit 2MAIN[17][26][26]MAIN[22][26][37]
CLKBURST_CNT bit 3MAIN[17][27][26]MAIN[22][27][37]
CLKOUT0_ENMAIN[16][26][57]MAIN[23][26][6]
CLKOUT0_NOCOUNTMAIN[16][26][52]MAIN[23][26][11]
CLKOUT0_EDGEMAIN[16][27][52]MAIN[23][27][11]
CLKOUT0_DT bit 0MAIN[16][26][55]MAIN[23][26][8]
CLKOUT0_DT bit 1MAIN[16][27][55]MAIN[23][27][8]
CLKOUT0_DT bit 2MAIN[16][26][54]MAIN[23][26][9]
CLKOUT0_DT bit 3MAIN[16][27][54]MAIN[23][27][9]
CLKOUT0_DT bit 4MAIN[16][26][53]MAIN[23][26][10]
CLKOUT0_DT bit 5MAIN[16][27][53]MAIN[23][27][10]
CLKOUT0_HT bit 0MAIN[16][26][60]MAIN[23][26][3]
CLKOUT0_HT bit 1MAIN[16][27][60]MAIN[23][27][3]
CLKOUT0_HT bit 2MAIN[16][26][59]MAIN[23][26][4]
CLKOUT0_HT bit 3MAIN[16][27][59]MAIN[23][27][4]
CLKOUT0_HT bit 4MAIN[16][26][58]MAIN[23][26][5]
CLKOUT0_HT bit 5MAIN[16][27][58]MAIN[23][27][5]
CLKOUT0_LT bit 0MAIN[16][26][63]MAIN[23][26][0]
CLKOUT0_LT bit 1MAIN[16][27][63]MAIN[23][27][0]
CLKOUT0_LT bit 2MAIN[16][26][62]MAIN[23][26][1]
CLKOUT0_LT bit 3MAIN[16][27][62]MAIN[23][27][1]
CLKOUT0_LT bit 4MAIN[16][26][61]MAIN[23][26][2]
CLKOUT0_LT bit 5MAIN[16][27][61]MAIN[23][27][2]
CLKOUT0_MX bit 0MAIN[16][26][51]MAIN[23][26][12]
CLKOUT0_MX bit 1MAIN[16][27][51]MAIN[23][27][12]
CLKOUT0_PM bit 0MAIN[16][27][57]MAIN[23][27][6]
CLKOUT0_PM bit 1MAIN[16][26][56]MAIN[23][26][7]
CLKOUT0_PM bit 2MAIN[16][27][56]MAIN[23][27][7]
CLKOUT0_USE_FINE_PSMAIN[16][26][51]MAIN[23][26][12]
CLKOUT1_ENMAIN[16][26][41]MAIN[23][26][22]
CLKOUT1_NOCOUNTMAIN[16][26][36]MAIN[23][26][27]
CLKOUT1_EDGEMAIN[16][27][36]MAIN[23][27][27]
CLKOUT1_DT bit 0MAIN[16][26][39]MAIN[23][26][24]
CLKOUT1_DT bit 1MAIN[16][27][39]MAIN[23][27][24]
CLKOUT1_DT bit 2MAIN[16][26][38]MAIN[23][26][25]
CLKOUT1_DT bit 3MAIN[16][27][38]MAIN[23][27][25]
CLKOUT1_DT bit 4MAIN[16][26][37]MAIN[23][26][26]
CLKOUT1_DT bit 5MAIN[16][27][37]MAIN[23][27][26]
CLKOUT1_HT bit 0MAIN[16][26][44]MAIN[23][26][19]
CLKOUT1_HT bit 1MAIN[16][27][44]MAIN[23][27][19]
CLKOUT1_HT bit 2MAIN[16][26][43]MAIN[23][26][20]
CLKOUT1_HT bit 3MAIN[16][27][43]MAIN[23][27][20]
CLKOUT1_HT bit 4MAIN[16][26][42]MAIN[23][26][21]
CLKOUT1_HT bit 5MAIN[16][27][42]MAIN[23][27][21]
CLKOUT1_LT bit 0MAIN[16][26][47]MAIN[23][26][16]
CLKOUT1_LT bit 1MAIN[16][27][47]MAIN[23][27][16]
CLKOUT1_LT bit 2MAIN[16][26][46]MAIN[23][26][17]
CLKOUT1_LT bit 3MAIN[16][27][46]MAIN[23][27][17]
CLKOUT1_LT bit 4MAIN[16][26][45]MAIN[23][26][18]
CLKOUT1_LT bit 5MAIN[16][27][45]MAIN[23][27][18]
CLKOUT1_MX bit 0MAIN[16][26][35]MAIN[23][26][28]
CLKOUT1_MX bit 1MAIN[16][27][35]MAIN[23][27][28]
CLKOUT1_PM bit 0MAIN[16][27][41]MAIN[23][27][22]
CLKOUT1_PM bit 1MAIN[16][26][40]MAIN[23][26][23]
CLKOUT1_PM bit 2MAIN[16][27][40]MAIN[23][27][23]
CLKOUT1_USE_FINE_PSMAIN[16][26][35]MAIN[23][26][28]
CLKOUT2_ENMAIN[16][26][25]MAIN[23][26][38]
CLKOUT2_NOCOUNTMAIN[16][26][20]MAIN[23][26][43]
CLKOUT2_EDGEMAIN[16][27][20]MAIN[23][27][43]
CLKOUT2_DT bit 0MAIN[16][26][23]MAIN[23][26][40]
CLKOUT2_DT bit 1MAIN[16][27][23]MAIN[23][27][40]
CLKOUT2_DT bit 2MAIN[16][26][22]MAIN[23][26][41]
CLKOUT2_DT bit 3MAIN[16][27][22]MAIN[23][27][41]
CLKOUT2_DT bit 4MAIN[16][26][21]MAIN[23][26][42]
CLKOUT2_DT bit 5MAIN[16][27][21]MAIN[23][27][42]
CLKOUT2_HT bit 0MAIN[16][26][28]MAIN[23][26][35]
CLKOUT2_HT bit 1MAIN[16][27][28]MAIN[23][27][35]
CLKOUT2_HT bit 2MAIN[16][26][27]MAIN[23][26][36]
CLKOUT2_HT bit 3MAIN[16][27][27]MAIN[23][27][36]
CLKOUT2_HT bit 4MAIN[16][26][26]MAIN[23][26][37]
CLKOUT2_HT bit 5MAIN[16][27][26]MAIN[23][27][37]
CLKOUT2_LT bit 0MAIN[16][26][31]MAIN[23][26][32]
CLKOUT2_LT bit 1MAIN[16][27][31]MAIN[23][27][32]
CLKOUT2_LT bit 2MAIN[16][26][30]MAIN[23][26][33]
CLKOUT2_LT bit 3MAIN[16][27][30]MAIN[23][27][33]
CLKOUT2_LT bit 4MAIN[16][26][29]MAIN[23][26][34]
CLKOUT2_LT bit 5MAIN[16][27][29]MAIN[23][27][34]
CLKOUT2_MX bit 0MAIN[16][26][19]MAIN[23][26][44]
CLKOUT2_MX bit 1MAIN[16][27][19]MAIN[23][27][44]
CLKOUT2_PM bit 0MAIN[16][27][25]MAIN[23][27][38]
CLKOUT2_PM bit 1MAIN[16][26][24]MAIN[23][26][39]
CLKOUT2_PM bit 2MAIN[16][27][24]MAIN[23][27][39]
CLKOUT2_USE_FINE_PSMAIN[16][26][19]MAIN[23][26][44]
CLKOUT3_ENMAIN[16][26][9]MAIN[23][26][54]
CLKOUT3_NOCOUNTMAIN[16][26][4]MAIN[23][26][59]
CLKOUT3_EDGEMAIN[16][27][4]MAIN[23][27][59]
CLKOUT3_DT bit 0MAIN[16][26][7]MAIN[23][26][56]
CLKOUT3_DT bit 1MAIN[16][27][7]MAIN[23][27][56]
CLKOUT3_DT bit 2MAIN[16][26][6]MAIN[23][26][57]
CLKOUT3_DT bit 3MAIN[16][27][6]MAIN[23][27][57]
CLKOUT3_DT bit 4MAIN[16][26][5]MAIN[23][26][58]
CLKOUT3_DT bit 5MAIN[16][27][5]MAIN[23][27][58]
CLKOUT3_HT bit 0MAIN[16][26][12]MAIN[23][26][51]
CLKOUT3_HT bit 1MAIN[16][27][12]MAIN[23][27][51]
CLKOUT3_HT bit 2MAIN[16][26][11]MAIN[23][26][52]
CLKOUT3_HT bit 3MAIN[16][27][11]MAIN[23][27][52]
CLKOUT3_HT bit 4MAIN[16][26][10]MAIN[23][26][53]
CLKOUT3_HT bit 5MAIN[16][27][10]MAIN[23][27][53]
CLKOUT3_LT bit 0MAIN[16][26][15]MAIN[23][26][48]
CLKOUT3_LT bit 1MAIN[16][27][15]MAIN[23][27][48]
CLKOUT3_LT bit 2MAIN[16][26][14]MAIN[23][26][49]
CLKOUT3_LT bit 3MAIN[16][27][14]MAIN[23][27][49]
CLKOUT3_LT bit 4MAIN[16][26][13]MAIN[23][26][50]
CLKOUT3_LT bit 5MAIN[16][27][13]MAIN[23][27][50]
CLKOUT3_MX bit 0MAIN[16][26][3]MAIN[23][26][60]
CLKOUT3_MX bit 1MAIN[16][27][3]MAIN[23][27][60]
CLKOUT3_PM bit 0MAIN[16][27][9]MAIN[23][27][54]
CLKOUT3_PM bit 1MAIN[16][26][8]MAIN[23][26][55]
CLKOUT3_PM bit 2MAIN[16][27][8]MAIN[23][27][55]
CLKOUT3_USE_FINE_PSMAIN[16][26][3]MAIN[23][26][60]
CLKOUT4_ENMAIN[15][26][57]MAIN[24][26][6]
CLKOUT4_NOCOUNTMAIN[15][26][52]MAIN[24][26][11]
CLKOUT4_EDGEMAIN[15][27][52]MAIN[24][27][11]
CLKOUT4_DT bit 0MAIN[15][26][55]MAIN[24][26][8]
CLKOUT4_DT bit 1MAIN[15][27][55]MAIN[24][27][8]
CLKOUT4_DT bit 2MAIN[15][26][54]MAIN[24][26][9]
CLKOUT4_DT bit 3MAIN[15][27][54]MAIN[24][27][9]
CLKOUT4_DT bit 4MAIN[15][26][53]MAIN[24][26][10]
CLKOUT4_DT bit 5MAIN[15][27][53]MAIN[24][27][10]
CLKOUT4_HT bit 0MAIN[15][26][60]MAIN[24][26][3]
CLKOUT4_HT bit 1MAIN[15][27][60]MAIN[24][27][3]
CLKOUT4_HT bit 2MAIN[15][26][59]MAIN[24][26][4]
CLKOUT4_HT bit 3MAIN[15][27][59]MAIN[24][27][4]
CLKOUT4_HT bit 4MAIN[15][26][58]MAIN[24][26][5]
CLKOUT4_HT bit 5MAIN[15][27][58]MAIN[24][27][5]
CLKOUT4_LT bit 0MAIN[15][26][63]MAIN[24][26][0]
CLKOUT4_LT bit 1MAIN[15][27][63]MAIN[24][27][0]
CLKOUT4_LT bit 2MAIN[15][26][62]MAIN[24][26][1]
CLKOUT4_LT bit 3MAIN[15][27][62]MAIN[24][27][1]
CLKOUT4_LT bit 4MAIN[15][26][61]MAIN[24][26][2]
CLKOUT4_LT bit 5MAIN[15][27][61]MAIN[24][27][2]
CLKOUT4_MX bit 0MAIN[15][26][51]MAIN[24][26][12]
CLKOUT4_MX bit 1MAIN[15][27][51]MAIN[24][27][12]
CLKOUT4_PM bit 0MAIN[15][27][57]MAIN[24][27][6]
CLKOUT4_PM bit 1MAIN[15][26][56]MAIN[24][26][7]
CLKOUT4_PM bit 2MAIN[15][27][56]MAIN[24][27][7]
CLKOUT4_USE_FINE_PSMAIN[15][26][51]MAIN[24][26][12]
CLKOUT5_ENMAIN[17][26][9]MAIN[22][26][54]
CLKOUT5_NOCOUNTMAIN[17][26][4]MAIN[22][26][59]
CLKOUT5_EDGEMAIN[17][27][4]MAIN[22][27][59]
CLKOUT5_DT bit 0MAIN[17][26][7]MAIN[22][26][56]
CLKOUT5_DT bit 1MAIN[17][27][7]MAIN[22][27][56]
CLKOUT5_DT bit 2MAIN[17][26][6]MAIN[22][26][57]
CLKOUT5_DT bit 3MAIN[17][27][6]MAIN[22][27][57]
CLKOUT5_DT bit 4MAIN[17][26][5]MAIN[22][26][58]
CLKOUT5_DT bit 5MAIN[17][27][5]MAIN[22][27][58]
CLKOUT5_HT bit 0MAIN[17][26][12]MAIN[22][26][51]
CLKOUT5_HT bit 1MAIN[17][27][12]MAIN[22][27][51]
CLKOUT5_HT bit 2MAIN[17][26][11]MAIN[22][26][52]
CLKOUT5_HT bit 3MAIN[17][27][11]MAIN[22][27][52]
CLKOUT5_HT bit 4MAIN[17][26][10]MAIN[22][26][53]
CLKOUT5_HT bit 5MAIN[17][27][10]MAIN[22][27][53]
CLKOUT5_LT bit 0MAIN[17][26][15]MAIN[22][26][48]
CLKOUT5_LT bit 1MAIN[17][27][15]MAIN[22][27][48]
CLKOUT5_LT bit 2MAIN[17][26][14]MAIN[22][26][49]
CLKOUT5_LT bit 3MAIN[17][27][14]MAIN[22][27][49]
CLKOUT5_LT bit 4MAIN[17][26][13]MAIN[22][26][50]
CLKOUT5_LT bit 5MAIN[17][27][13]MAIN[22][27][50]
CLKOUT5_MX bit 0MAIN[17][26][3]MAIN[22][26][60]
CLKOUT5_MX bit 1MAIN[17][27][3]MAIN[22][27][60]
CLKOUT5_PM bit 0MAIN[17][27][9]MAIN[22][27][54]
CLKOUT5_PM bit 1MAIN[17][26][8]MAIN[22][26][55]
CLKOUT5_PM bit 2MAIN[17][27][8]MAIN[22][27][55]
CLKOUT5_USE_FINE_PSMAIN[17][26][3]MAIN[22][26][60]
CLKOUT6_ENMAIN[15][26][41]MAIN[24][26][22]
CLKOUT6_NOCOUNTMAIN[15][26][36]MAIN[24][26][27]
CLKOUT6_EDGEMAIN[15][27][36]MAIN[24][27][27]
CLKOUT6_DT bit 0MAIN[15][26][39]MAIN[24][26][24]
CLKOUT6_DT bit 1MAIN[15][27][39]MAIN[24][27][24]
CLKOUT6_DT bit 2MAIN[15][26][38]MAIN[24][26][25]
CLKOUT6_DT bit 3MAIN[15][27][38]MAIN[24][27][25]
CLKOUT6_DT bit 4MAIN[15][26][37]MAIN[24][26][26]
CLKOUT6_DT bit 5MAIN[15][27][37]MAIN[24][27][26]
CLKOUT6_HT bit 0MAIN[15][26][44]MAIN[24][26][19]
CLKOUT6_HT bit 1MAIN[15][27][44]MAIN[24][27][19]
CLKOUT6_HT bit 2MAIN[15][26][43]MAIN[24][26][20]
CLKOUT6_HT bit 3MAIN[15][27][43]MAIN[24][27][20]
CLKOUT6_HT bit 4MAIN[15][26][42]MAIN[24][26][21]
CLKOUT6_HT bit 5MAIN[15][27][42]MAIN[24][27][21]
CLKOUT6_LT bit 0MAIN[15][26][47]MAIN[24][26][16]
CLKOUT6_LT bit 1MAIN[15][27][47]MAIN[24][27][16]
CLKOUT6_LT bit 2MAIN[15][26][46]MAIN[24][26][17]
CLKOUT6_LT bit 3MAIN[15][27][46]MAIN[24][27][17]
CLKOUT6_LT bit 4MAIN[15][26][45]MAIN[24][26][18]
CLKOUT6_LT bit 5MAIN[15][27][45]MAIN[24][27][18]
CLKOUT6_MX bit 0MAIN[15][26][35]MAIN[24][26][28]
CLKOUT6_MX bit 1MAIN[15][27][35]MAIN[24][27][28]
CLKOUT6_PM bit 0MAIN[15][27][41]MAIN[24][27][22]
CLKOUT6_PM bit 1MAIN[15][26][40]MAIN[24][26][23]
CLKOUT6_PM bit 2MAIN[15][27][40]MAIN[24][27][23]
CLKOUT6_USE_FINE_PSMAIN[15][26][35]MAIN[24][26][28]
CLKFBOUT_ENMAIN[15][26][25]MAIN[24][26][38]
CLKFBOUT_NOCOUNTMAIN[15][26][20]MAIN[24][26][43]
CLKFBOUT_EDGEMAIN[15][27][20]MAIN[24][27][43]
CLKFBOUT_DT bit 0MAIN[15][26][23]MAIN[24][26][40]
CLKFBOUT_DT bit 1MAIN[15][27][23]MAIN[24][27][40]
CLKFBOUT_DT bit 2MAIN[15][26][22]MAIN[24][26][41]
CLKFBOUT_DT bit 3MAIN[15][27][22]MAIN[24][27][41]
CLKFBOUT_DT bit 4MAIN[15][26][21]MAIN[24][26][42]
CLKFBOUT_DT bit 5MAIN[15][27][21]MAIN[24][27][42]
CLKFBOUT_HT bit 0MAIN[15][26][28]MAIN[24][26][35]
CLKFBOUT_HT bit 1MAIN[15][27][28]MAIN[24][27][35]
CLKFBOUT_HT bit 2MAIN[15][26][27]MAIN[24][26][36]
CLKFBOUT_HT bit 3MAIN[15][27][27]MAIN[24][27][36]
CLKFBOUT_HT bit 4MAIN[15][26][26]MAIN[24][26][37]
CLKFBOUT_HT bit 5MAIN[15][27][26]MAIN[24][27][37]
CLKFBOUT_LT bit 0MAIN[15][26][31]MAIN[24][26][32]
CLKFBOUT_LT bit 1MAIN[15][27][31]MAIN[24][27][32]
CLKFBOUT_LT bit 2MAIN[15][26][30]MAIN[24][26][33]
CLKFBOUT_LT bit 3MAIN[15][27][30]MAIN[24][27][33]
CLKFBOUT_LT bit 4MAIN[15][26][29]MAIN[24][26][34]
CLKFBOUT_LT bit 5MAIN[15][27][29]MAIN[24][27][34]
CLKFBOUT_MX bit 0MAIN[15][26][19]MAIN[24][26][44]
CLKFBOUT_MX bit 1MAIN[15][27][19]MAIN[24][27][44]
CLKFBOUT_PM bit 0MAIN[15][27][25]MAIN[24][27][38]
CLKFBOUT_PM bit 1MAIN[15][26][24]MAIN[24][26][39]
CLKFBOUT_PM bit 2MAIN[15][27][24]MAIN[24][27][39]
CLKFBOUT_USE_FINE_PSMAIN[15][26][19]MAIN[24][26][44]
CLKOUT0_FRAC_ENMAIN[16][27][50]MAIN[23][27][13]
CLKOUT0_FRAC bit 0MAIN[16][26][49]MAIN[23][26][14]
CLKOUT0_FRAC bit 1MAIN[16][27][49]MAIN[23][27][14]
CLKOUT0_FRAC bit 2MAIN[16][26][48]MAIN[23][26][15]
CLKFBOUT_FRAC_ENMAIN[15][27][18]MAIN[24][27][45]
CLKFBOUT_FRAC bit 0MAIN[15][26][17]MAIN[24][26][46]
CLKFBOUT_FRAC bit 1MAIN[15][27][17]MAIN[24][27][46]
CLKFBOUT_FRAC bit 2MAIN[15][26][16]MAIN[24][26][47]
CLKOUT4_CASCADEMAIN[15][27][51]MAIN[24][27][12]
FINE_PS_FRAC bit 0MAIN[3][27][29]MAIN[36][27][34]
FINE_PS_FRAC bit 1MAIN[3][26][28]MAIN[36][26][35]
FINE_PS_FRAC bit 2MAIN[3][27][28]MAIN[36][27][35]
FINE_PS_FRAC bit 3MAIN[3][26][27]MAIN[36][26][36]
FINE_PS_FRAC bit 4MAIN[3][27][27]MAIN[36][27][36]
FINE_PS_FRAC bit 5MAIN[3][26][26]MAIN[36][26][37]
CLKOUT0_FRAC_WFMAIN[16][26][50]MAIN[23][26][13]
CLKOUT5_FRAC_WFMAIN[17][26][2]MAIN[22][26][61]
CLKOUT6_FRAC_WFMAIN[15][26][34]MAIN[24][26][29]
CLKFBOUT_FRAC_WFMAIN[15][26][18]MAIN[24][26][45]
DIVCLK_NOCOUNTMAIN[15][26][9]MAIN[24][26][54]
DIVCLK_EDGEMAIN[15][27][9]MAIN[24][27][54]
DIVCLK_HT bit 0MAIN[15][26][12]MAIN[24][26][51]
DIVCLK_HT bit 1MAIN[15][27][12]MAIN[24][27][51]
DIVCLK_HT bit 2MAIN[15][26][11]MAIN[24][26][52]
DIVCLK_HT bit 3MAIN[15][27][11]MAIN[24][27][52]
DIVCLK_HT bit 4MAIN[15][26][10]MAIN[24][26][53]
DIVCLK_HT bit 5MAIN[15][27][10]MAIN[24][27][53]
DIVCLK_LT bit 0MAIN[15][26][15]MAIN[24][26][48]
DIVCLK_LT bit 1MAIN[15][27][15]MAIN[24][27][48]
DIVCLK_LT bit 2MAIN[15][26][14]MAIN[24][26][49]
DIVCLK_LT bit 3MAIN[15][27][14]MAIN[24][27][49]
DIVCLK_LT bit 4MAIN[15][26][13]MAIN[24][26][50]
DIVCLK_LT bit 5MAIN[15][27][13]MAIN[24][27][50]
CLKFBIN_NOCOUNTMAIN[15][26][1]MAIN[24][26][62]
CLKFBIN_EDGEMAIN[15][27][1]MAIN[24][27][62]
CLKFBIN_HT bit 0MAIN[15][26][4]MAIN[24][26][59]
CLKFBIN_HT bit 1MAIN[15][27][4]MAIN[24][27][59]
CLKFBIN_HT bit 2MAIN[15][26][3]MAIN[24][26][60]
CLKFBIN_HT bit 3MAIN[15][27][3]MAIN[24][27][60]
CLKFBIN_HT bit 4MAIN[15][26][2]MAIN[24][26][61]
CLKFBIN_HT bit 5MAIN[15][27][2]MAIN[24][27][61]
CLKFBIN_LT bit 0MAIN[15][26][7]MAIN[24][26][56]
CLKFBIN_LT bit 1MAIN[15][27][7]MAIN[24][27][56]
CLKFBIN_LT bit 2MAIN[15][26][6]MAIN[24][26][57]
CLKFBIN_LT bit 3MAIN[15][27][6]MAIN[24][27][57]
CLKFBIN_LT bit 4MAIN[15][26][5]MAIN[24][26][58]
CLKFBIN_LT bit 5MAIN[15][27][5]MAIN[24][27][58]

Bels PPR_FRAME

virtex6 CMT bel PPR_FRAME pins
PinDirectionPPR_FRAME
CLKinCELL[39].IMUX_CLK[1]
CTLBinCELL[35].IMUX_IMUX[43]
ENBinCELL[35].IMUX_IMUX[42]
SHIFTBinCELL[35].IMUX_IMUX[40]
UPDATEBinCELL[35].IMUX_IMUX[41]
DA[0]inCELL[20].IMUX_IMUX[44]
DA[1]inCELL[20].IMUX_IMUX[45]
DA[2]inCELL[20].IMUX_IMUX[46]
DA[3]inCELL[20].IMUX_IMUX[47]
DA[4]inCELL[21].IMUX_IMUX[44]
DA[5]inCELL[21].IMUX_IMUX[45]
DA[6]inCELL[21].IMUX_IMUX[46]
DA[7]inCELL[21].IMUX_IMUX[47]
DA[8]inCELL[22].IMUX_IMUX[44]
DA[9]inCELL[22].IMUX_IMUX[45]
DA[10]inCELL[22].IMUX_IMUX[46]
DA[11]inCELL[22].IMUX_IMUX[47]
DA[12]inCELL[23].IMUX_IMUX[44]
DA[13]inCELL[23].IMUX_IMUX[45]
DA[14]inCELL[23].IMUX_IMUX[46]
DA[15]inCELL[23].IMUX_IMUX[47]
DA[16]inCELL[24].IMUX_IMUX[44]
DA[17]inCELL[24].IMUX_IMUX[45]
DA[18]inCELL[24].IMUX_IMUX[46]
DA[19]inCELL[24].IMUX_IMUX[47]
DA[20]inCELL[25].IMUX_IMUX[44]
DA[21]inCELL[25].IMUX_IMUX[45]
DA[22]inCELL[25].IMUX_IMUX[46]
DA[23]inCELL[25].IMUX_IMUX[47]
DA[24]inCELL[26].IMUX_IMUX[44]
DA[25]inCELL[26].IMUX_IMUX[45]
DA[26]inCELL[26].IMUX_IMUX[46]
DA[27]inCELL[26].IMUX_IMUX[47]
DA[28]inCELL[27].IMUX_IMUX[44]
DA[29]inCELL[27].IMUX_IMUX[45]
DA[30]inCELL[27].IMUX_IMUX[46]
DA[31]inCELL[27].IMUX_IMUX[47]
DA[32]inCELL[28].IMUX_IMUX[44]
DA[33]inCELL[28].IMUX_IMUX[45]
DA[34]inCELL[28].IMUX_IMUX[46]
DA[35]inCELL[28].IMUX_IMUX[47]
DA[36]inCELL[29].IMUX_IMUX[44]
DA[37]inCELL[29].IMUX_IMUX[45]
DA[38]inCELL[29].IMUX_IMUX[46]
DA[39]inCELL[29].IMUX_IMUX[47]
DA[40]inCELL[30].IMUX_IMUX[44]
DA[41]inCELL[30].IMUX_IMUX[45]
DA[42]inCELL[30].IMUX_IMUX[46]
DA[43]inCELL[30].IMUX_IMUX[47]
DA[44]inCELL[31].IMUX_IMUX[44]
DA[45]inCELL[31].IMUX_IMUX[45]
DA[46]inCELL[31].IMUX_IMUX[46]
DA[47]inCELL[31].IMUX_IMUX[47]
DA[48]inCELL[32].IMUX_IMUX[44]
DA[49]inCELL[32].IMUX_IMUX[45]
DA[50]inCELL[32].IMUX_IMUX[46]
DA[51]inCELL[32].IMUX_IMUX[47]
DA[52]inCELL[33].IMUX_IMUX[44]
DA[53]inCELL[33].IMUX_IMUX[45]
DA[54]inCELL[33].IMUX_IMUX[46]
DA[55]inCELL[33].IMUX_IMUX[47]
DA[56]inCELL[34].IMUX_IMUX[44]
DA[57]inCELL[34].IMUX_IMUX[45]
DA[58]inCELL[34].IMUX_IMUX[46]
DA[59]inCELL[34].IMUX_IMUX[47]
DA[60]inCELL[35].IMUX_IMUX[44]
DA[61]inCELL[35].IMUX_IMUX[45]
DA[62]inCELL[35].IMUX_IMUX[46]
DA[63]inCELL[35].IMUX_IMUX[47]
DA[64]inCELL[36].IMUX_IMUX[44]
DA[65]inCELL[36].IMUX_IMUX[45]
DA[66]inCELL[36].IMUX_IMUX[46]
DA[67]inCELL[36].IMUX_IMUX[47]
DA[68]inCELL[37].IMUX_IMUX[44]
DA[69]inCELL[37].IMUX_IMUX[45]
DA[70]inCELL[37].IMUX_IMUX[46]
DA[71]inCELL[37].IMUX_IMUX[47]
DA[72]inCELL[38].IMUX_IMUX[44]
DA[73]inCELL[38].IMUX_IMUX[45]
DA[74]inCELL[38].IMUX_IMUX[46]
DA[75]inCELL[38].IMUX_IMUX[47]
DA[76]inCELL[39].IMUX_IMUX[44]
DA[77]inCELL[39].IMUX_IMUX[45]
DA[78]inCELL[39].IMUX_IMUX[46]
DA[79]inCELL[39].IMUX_IMUX[47]
DB[0]inCELL[0].IMUX_IMUX[44]
DB[1]inCELL[0].IMUX_IMUX[45]
DB[2]inCELL[0].IMUX_IMUX[46]
DB[3]inCELL[0].IMUX_IMUX[47]
DB[4]inCELL[1].IMUX_IMUX[44]
DB[5]inCELL[1].IMUX_IMUX[45]
DB[6]inCELL[1].IMUX_IMUX[46]
DB[7]inCELL[1].IMUX_IMUX[47]
DB[8]inCELL[2].IMUX_IMUX[44]
DB[9]inCELL[2].IMUX_IMUX[45]
DB[10]inCELL[2].IMUX_IMUX[46]
DB[11]inCELL[2].IMUX_IMUX[47]
DB[12]inCELL[3].IMUX_IMUX[44]
DB[13]inCELL[3].IMUX_IMUX[45]
DB[14]inCELL[3].IMUX_IMUX[46]
DB[15]inCELL[3].IMUX_IMUX[47]
DB[16]inCELL[4].IMUX_IMUX[44]
DB[17]inCELL[4].IMUX_IMUX[45]
DB[18]inCELL[4].IMUX_IMUX[46]
DB[19]inCELL[4].IMUX_IMUX[47]
DB[20]inCELL[5].IMUX_IMUX[44]
DB[21]inCELL[5].IMUX_IMUX[45]
DB[22]inCELL[5].IMUX_IMUX[46]
DB[23]inCELL[5].IMUX_IMUX[47]
DB[24]inCELL[6].IMUX_IMUX[44]
DB[25]inCELL[6].IMUX_IMUX[45]
DB[26]inCELL[6].IMUX_IMUX[46]
DB[27]inCELL[6].IMUX_IMUX[47]
DB[28]inCELL[7].IMUX_IMUX[44]
DB[29]inCELL[7].IMUX_IMUX[45]
DB[30]inCELL[7].IMUX_IMUX[46]
DB[31]inCELL[7].IMUX_IMUX[47]
DB[32]inCELL[8].IMUX_IMUX[44]
DB[33]inCELL[8].IMUX_IMUX[45]
DB[34]inCELL[8].IMUX_IMUX[46]
DB[35]inCELL[8].IMUX_IMUX[47]
DB[36]inCELL[9].IMUX_IMUX[44]
DB[37]inCELL[9].IMUX_IMUX[45]
DB[38]inCELL[9].IMUX_IMUX[46]
DB[39]inCELL[9].IMUX_IMUX[47]
DB[40]inCELL[10].IMUX_IMUX[44]
DB[41]inCELL[10].IMUX_IMUX[45]
DB[42]inCELL[10].IMUX_IMUX[46]
DB[43]inCELL[10].IMUX_IMUX[47]
DB[44]inCELL[11].IMUX_IMUX[44]
DB[45]inCELL[11].IMUX_IMUX[45]
DB[46]inCELL[11].IMUX_IMUX[46]
DB[47]inCELL[11].IMUX_IMUX[47]
DB[48]inCELL[12].IMUX_IMUX[44]
DB[49]inCELL[12].IMUX_IMUX[45]
DB[50]inCELL[12].IMUX_IMUX[46]
DB[51]inCELL[12].IMUX_IMUX[47]
DB[52]inCELL[13].IMUX_IMUX[44]
DB[53]inCELL[13].IMUX_IMUX[45]
DB[54]inCELL[13].IMUX_IMUX[46]
DB[55]inCELL[13].IMUX_IMUX[47]
DB[56]inCELL[14].IMUX_IMUX[44]
DB[57]inCELL[14].IMUX_IMUX[45]
DB[58]inCELL[14].IMUX_IMUX[46]
DB[59]inCELL[14].IMUX_IMUX[47]
DB[60]inCELL[15].IMUX_IMUX[44]
DB[61]inCELL[15].IMUX_IMUX[45]
DB[62]inCELL[15].IMUX_IMUX[46]
DB[63]inCELL[15].IMUX_IMUX[47]
DB[64]inCELL[16].IMUX_IMUX[44]
DB[65]inCELL[16].IMUX_IMUX[45]
DB[66]inCELL[16].IMUX_IMUX[46]
DB[67]inCELL[16].IMUX_IMUX[47]
DB[68]inCELL[17].IMUX_IMUX[44]
DB[69]inCELL[17].IMUX_IMUX[45]
DB[70]inCELL[17].IMUX_IMUX[46]
DB[71]inCELL[17].IMUX_IMUX[47]
DB[72]inCELL[18].IMUX_IMUX[44]
DB[73]inCELL[18].IMUX_IMUX[45]
DB[74]inCELL[18].IMUX_IMUX[46]
DB[75]inCELL[18].IMUX_IMUX[47]
DB[76]inCELL[19].IMUX_IMUX[44]
DB[77]inCELL[19].IMUX_IMUX[45]
DB[78]inCELL[19].IMUX_IMUX[46]
DB[79]inCELL[19].IMUX_IMUX[47]
DH[0]inCELL[19].IMUX_IMUX[42]
DH[1]inCELL[19].IMUX_IMUX[43]

Bels BUFHCE

virtex6 CMT bel BUFHCE pins
PinDirectionBUFHCE_W[0]BUFHCE_W[1]BUFHCE_W[2]BUFHCE_W[3]BUFHCE_W[4]BUFHCE_W[5]BUFHCE_W[6]BUFHCE_W[7]BUFHCE_W[8]BUFHCE_W[9]BUFHCE_W[10]BUFHCE_W[11]BUFHCE_E[0]BUFHCE_E[1]BUFHCE_E[2]BUFHCE_E[3]BUFHCE_E[4]BUFHCE_E[5]BUFHCE_E[6]BUFHCE_E[7]BUFHCE_E[8]BUFHCE_E[9]BUFHCE_E[10]BUFHCE_E[11]
IinCELL[20].IMUX_BUFHCE_W[0]CELL[20].IMUX_BUFHCE_W[1]CELL[20].IMUX_BUFHCE_W[2]CELL[20].IMUX_BUFHCE_W[3]CELL[20].IMUX_BUFHCE_W[4]CELL[20].IMUX_BUFHCE_W[5]CELL[20].IMUX_BUFHCE_W[6]CELL[20].IMUX_BUFHCE_W[7]CELL[20].IMUX_BUFHCE_W[8]CELL[20].IMUX_BUFHCE_W[9]CELL[20].IMUX_BUFHCE_W[10]CELL[20].IMUX_BUFHCE_W[11]CELL[20].IMUX_BUFHCE_E[0]CELL[20].IMUX_BUFHCE_E[1]CELL[20].IMUX_BUFHCE_E[2]CELL[20].IMUX_BUFHCE_E[3]CELL[20].IMUX_BUFHCE_E[4]CELL[20].IMUX_BUFHCE_E[5]CELL[20].IMUX_BUFHCE_E[6]CELL[20].IMUX_BUFHCE_E[7]CELL[20].IMUX_BUFHCE_E[8]CELL[20].IMUX_BUFHCE_E[9]CELL[20].IMUX_BUFHCE_E[10]CELL[20].IMUX_BUFHCE_E[11]
CEinCELL[19].IMUX_IMUX[0] invert by !MAIN[18][27][19]CELL[19].IMUX_IMUX[1] invert by !MAIN[18][28][19]CELL[19].IMUX_IMUX[2] invert by !MAIN[18][27][35]CELL[19].IMUX_IMUX[3] invert by !MAIN[18][28][35]CELL[19].IMUX_IMUX[4] invert by !MAIN[18][27][51]CELL[19].IMUX_IMUX[5] invert by !MAIN[18][28][51]CELL[20].IMUX_IMUX[0] invert by !MAIN[21][27][3]CELL[20].IMUX_IMUX[1] invert by !MAIN[21][28][3]CELL[20].IMUX_IMUX[2] invert by !MAIN[21][27][19]CELL[20].IMUX_IMUX[3] invert by !MAIN[21][28][19]CELL[20].IMUX_IMUX[4] invert by !MAIN[21][27][35]CELL[20].IMUX_IMUX[5] invert by !MAIN[21][28][35]CELL[19].IMUX_IMUX[6] invert by !MAIN[18][31][19]CELL[19].IMUX_IMUX[7] invert by !MAIN[18][32][19]CELL[19].IMUX_IMUX[8] invert by !MAIN[18][31][35]CELL[19].IMUX_IMUX[9] invert by !MAIN[18][32][35]CELL[19].IMUX_IMUX[10] invert by !MAIN[18][31][51]CELL[19].IMUX_IMUX[11] invert by !MAIN[18][32][51]CELL[20].IMUX_IMUX[6] invert by !MAIN[21][31][3]CELL[20].IMUX_IMUX[7] invert by !MAIN[21][32][3]CELL[20].IMUX_IMUX[8] invert by !MAIN[21][31][19]CELL[20].IMUX_IMUX[9] invert by !MAIN[21][32][19]CELL[20].IMUX_IMUX[10] invert by !MAIN[21][31][35]CELL[20].IMUX_IMUX[11] invert by !MAIN[21][32][35]
OoutCELL[20].HCLK_CMT_W[0]CELL[20].HCLK_CMT_W[1]CELL[20].HCLK_CMT_W[2]CELL[20].HCLK_CMT_W[3]CELL[20].HCLK_CMT_W[4]CELL[20].HCLK_CMT_W[5]CELL[20].HCLK_CMT_W[6]CELL[20].HCLK_CMT_W[7]CELL[20].HCLK_CMT_W[8]CELL[20].HCLK_CMT_W[9]CELL[20].HCLK_CMT_W[10]CELL[20].HCLK_CMT_W[11]CELL[20].HCLK_CMT_E[0]CELL[20].HCLK_CMT_E[1]CELL[20].HCLK_CMT_E[2]CELL[20].HCLK_CMT_E[3]CELL[20].HCLK_CMT_E[4]CELL[20].HCLK_CMT_E[5]CELL[20].HCLK_CMT_E[6]CELL[20].HCLK_CMT_E[7]CELL[20].HCLK_CMT_E[8]CELL[20].HCLK_CMT_E[9]CELL[20].HCLK_CMT_E[10]CELL[20].HCLK_CMT_E[11]
virtex6 CMT bel BUFHCE attribute bits
AttributeBUFHCE_W[0]BUFHCE_W[1]BUFHCE_W[2]BUFHCE_W[3]BUFHCE_W[4]BUFHCE_W[5]BUFHCE_W[6]BUFHCE_W[7]BUFHCE_W[8]BUFHCE_W[9]BUFHCE_W[10]BUFHCE_W[11]BUFHCE_E[0]BUFHCE_E[1]BUFHCE_E[2]BUFHCE_E[3]BUFHCE_E[4]BUFHCE_E[5]BUFHCE_E[6]BUFHCE_E[7]BUFHCE_E[8]BUFHCE_E[9]BUFHCE_E[10]BUFHCE_E[11]
ENABLEMAIN[18][27][30]MAIN[18][28][30]MAIN[18][27][46]MAIN[18][28][46]MAIN[18][27][62]MAIN[18][28][62]MAIN[21][27][14]MAIN[21][28][14]MAIN[21][27][30]MAIN[21][28][30]MAIN[21][27][46]MAIN[21][28][46]MAIN[18][31][30]MAIN[18][32][30]MAIN[18][31][46]MAIN[18][32][46]MAIN[18][31][62]MAIN[18][32][62]MAIN[21][31][14]MAIN[21][32][14]MAIN[21][31][30]MAIN[21][32][30]MAIN[21][31][46]MAIN[21][32][46]
INIT_OUT bit 0MAIN[18][26][18]MAIN[18][29][18]MAIN[18][26][34]MAIN[18][29][34]MAIN[18][26][50]MAIN[18][29][50]MAIN[21][26][2]MAIN[21][29][2]MAIN[21][26][18]MAIN[21][29][18]MAIN[21][26][34]MAIN[21][29][34]MAIN[18][30][18]MAIN[18][33][18]MAIN[18][30][34]MAIN[18][33][34]MAIN[18][30][50]MAIN[18][33][50]MAIN[21][30][2]MAIN[21][33][2]MAIN[21][30][18]MAIN[21][33][18]MAIN[21][30][34]MAIN[21][33][34]

Bel wires

virtex6 CMT bel wires
WirePins
CELL[0].IMUX_IMUX[44]PPR_FRAME.DB[0]
CELL[0].IMUX_IMUX[45]PPR_FRAME.DB[1]
CELL[0].IMUX_IMUX[46]PPR_FRAME.DB[2]
CELL[0].IMUX_IMUX[47]PPR_FRAME.DB[3]
CELL[1].IMUX_IMUX[44]PPR_FRAME.DB[4]
CELL[1].IMUX_IMUX[45]PPR_FRAME.DB[5]
CELL[1].IMUX_IMUX[46]PPR_FRAME.DB[6]
CELL[1].IMUX_IMUX[47]PPR_FRAME.DB[7]
CELL[2].IMUX_CLK[0]PLL[0].DCLK
CELL[2].IMUX_CLK[1]PLL[0].PSCLK
CELL[2].IMUX_IMUX[44]PPR_FRAME.DB[8]
CELL[2].IMUX_IMUX[45]PPR_FRAME.DB[9]
CELL[2].IMUX_IMUX[46]PPR_FRAME.DB[10]
CELL[2].IMUX_IMUX[47]PPR_FRAME.DB[11]
CELL[2].OUT_BEL[0]PLL[0].PSDONE
CELL[2].OUT_BEL[1]PLL[0].DO[15]
CELL[2].OUT_BEL[2]PLL[0].DO[11]
CELL[2].OUT_BEL[8]PLL[0].LOCKED
CELL[2].OUT_BEL[9]PLL[0].DO[14]
CELL[2].OUT_BEL[11]PLL[0].DO[9]
CELL[2].OUT_BEL[15]PLL[0].DO[10]
CELL[2].OUT_BEL[16]PLL[0].DO[12]
CELL[2].OUT_BEL[17]PLL[0].DO[8]
CELL[2].OUT_BEL[18]PLL[0].DRDY
CELL[2].OUT_BEL[19]PLL[0].DO[13]
CELL[3].IMUX_IMUX[7]PLL[0].DI[9]
CELL[3].IMUX_IMUX[8]PLL[0].RST
CELL[3].IMUX_IMUX[9]PLL[0].DEN
CELL[3].IMUX_IMUX[10]PLL[0].DWE
CELL[3].IMUX_IMUX[11]PLL[0].CLKINSEL
CELL[3].IMUX_IMUX[12]PLL[0].DI[14]
CELL[3].IMUX_IMUX[13]PLL[0].DI[12]
CELL[3].IMUX_IMUX[22]PLL[0].DI[10]
CELL[3].IMUX_IMUX[32]PLL[0].PSINCDEC
CELL[3].IMUX_IMUX[33]PLL[0].PSEN
CELL[3].IMUX_IMUX[34]PLL[0].PWRDWN
CELL[3].IMUX_IMUX[35]PLL[0].DI[15]
CELL[3].IMUX_IMUX[36]PLL[0].DI[13]
CELL[3].IMUX_IMUX[37]PLL[0].DI[11]
CELL[3].IMUX_IMUX[39]PLL[0].DI[8]
CELL[3].IMUX_IMUX[44]PPR_FRAME.DB[12]
CELL[3].IMUX_IMUX[45]PPR_FRAME.DB[13]
CELL[3].IMUX_IMUX[46]PPR_FRAME.DB[14]
CELL[3].IMUX_IMUX[47]PPR_FRAME.DB[15]
CELL[3].OUT_BEL[0]PLL[0].DO[6]
CELL[3].OUT_BEL[1]PLL[0].DO[5]
CELL[3].OUT_BEL[2]PLL[0].DO[2]
CELL[3].OUT_BEL[3]PLL[0].DO[1]
CELL[3].OUT_BEL[4]PLL[0].DO[7]
CELL[3].OUT_BEL[5]PLL[0].DO[4]
CELL[3].OUT_BEL[6]PLL[0].DO[3]
CELL[3].OUT_BEL[7]PLL[0].DO[0]
CELL[4].IMUX_IMUX[10]PLL[0].DI[5]
CELL[4].IMUX_IMUX[11]PLL[0].DI[4]
CELL[4].IMUX_IMUX[12]PLL[0].DI[3]
CELL[4].IMUX_IMUX[13]PLL[0].DI[2]
CELL[4].IMUX_IMUX[14]PLL[0].DI[1]
CELL[4].IMUX_IMUX[15]PLL[0].DI[0]
CELL[4].IMUX_IMUX[16]PLL[0].DI[7]
CELL[4].IMUX_IMUX[17]PLL[0].DI[6]
CELL[4].IMUX_IMUX[44]PPR_FRAME.DB[16]
CELL[4].IMUX_IMUX[45]PPR_FRAME.DB[17]
CELL[4].IMUX_IMUX[46]PPR_FRAME.DB[18]
CELL[4].IMUX_IMUX[47]PPR_FRAME.DB[19]
CELL[4].OUT_BEL[0]PLL[0].CLKFBSTOPPED
CELL[4].OUT_BEL[1]PLL[0].TESTOUT[31]
CELL[4].OUT_BEL[2]PLL[0].TESTOUT[28]
CELL[4].OUT_BEL[3]PLL[0].TESTOUT[27]
CELL[4].OUT_BEL[4]PLL[0].CLKINSTOPPED
CELL[4].OUT_BEL[5]PLL[0].TESTOUT[30]
CELL[4].OUT_BEL[6]PLL[0].TESTOUT[29]
CELL[4].OUT_BEL[7]PLL[0].TESTOUT[26]
CELL[5].IMUX_IMUX[5]PLL[0].DADDR[2]
CELL[5].IMUX_IMUX[6]PLL[0].DADDR[1]
CELL[5].IMUX_IMUX[7]PLL[0].DADDR[0]
CELL[5].IMUX_IMUX[40]PLL[0].DADDR[6]
CELL[5].IMUX_IMUX[41]PLL[0].DADDR[5]
CELL[5].IMUX_IMUX[42]PLL[0].DADDR[4]
CELL[5].IMUX_IMUX[43]PLL[0].DADDR[3]
CELL[5].IMUX_IMUX[44]PPR_FRAME.DB[20]
CELL[5].IMUX_IMUX[45]PPR_FRAME.DB[21]
CELL[5].IMUX_IMUX[46]PPR_FRAME.DB[22]
CELL[5].IMUX_IMUX[47]PPR_FRAME.DB[23]
CELL[5].OUT_BEL[0]PLL[0].TESTOUT[24]
CELL[5].OUT_BEL[1]PLL[0].TESTOUT[23]
CELL[5].OUT_BEL[2]PLL[0].TESTOUT[20]
CELL[5].OUT_BEL[3]PLL[0].TESTOUT[19]
CELL[5].OUT_BEL[4]PLL[0].TESTOUT[25]
CELL[5].OUT_BEL[5]PLL[0].TESTOUT[22]
CELL[5].OUT_BEL[6]PLL[0].TESTOUT[21]
CELL[5].OUT_BEL[7]PLL[0].TESTOUT[18]
CELL[6].IMUX_IMUX[44]PPR_FRAME.DB[24]
CELL[6].IMUX_IMUX[45]PPR_FRAME.DB[25]
CELL[6].IMUX_IMUX[46]PPR_FRAME.DB[26]
CELL[6].IMUX_IMUX[47]PPR_FRAME.DB[27]
CELL[6].OUT_BEL[0]PLL[0].TESTOUT[16]
CELL[6].OUT_BEL[1]PLL[0].TESTOUT[15]
CELL[6].OUT_BEL[2]PLL[0].TESTOUT[12]
CELL[6].OUT_BEL[3]PLL[0].TESTOUT[11]
CELL[6].OUT_BEL[4]PLL[0].TESTOUT[17]
CELL[6].OUT_BEL[5]PLL[0].TESTOUT[14]
CELL[6].OUT_BEL[6]PLL[0].TESTOUT[13]
CELL[6].OUT_BEL[7]PLL[0].TESTOUT[10]
CELL[7].IMUX_IMUX[5]PLL[0].TESTIN[17]
CELL[7].IMUX_IMUX[6]PLL[0].TESTIN[14]
CELL[7].IMUX_IMUX[7]PLL[0].TESTIN[11]
CELL[7].IMUX_IMUX[8]PLL[0].TESTIN[31]
CELL[7].IMUX_IMUX[9]PLL[0].TESTIN[28]
CELL[7].IMUX_IMUX[10]PLL[0].TESTIN[25]
CELL[7].IMUX_IMUX[11]PLL[0].TESTIN[22]
CELL[7].IMUX_IMUX[12]PLL[0].TESTIN[19]
CELL[7].IMUX_IMUX[21]PLL[0].TESTIN[16]
CELL[7].IMUX_IMUX[22]PLL[0].TESTIN[13]
CELL[7].IMUX_IMUX[23]PLL[0].TESTIN[10]
CELL[7].IMUX_IMUX[24]PLL[0].TESTIN[30]
CELL[7].IMUX_IMUX[25]PLL[0].TESTIN[27]
CELL[7].IMUX_IMUX[26]PLL[0].TESTIN[24]
CELL[7].IMUX_IMUX[27]PLL[0].TESTIN[21]
CELL[7].IMUX_IMUX[28]PLL[0].TESTIN[18]
CELL[7].IMUX_IMUX[37]PLL[0].TESTIN[15]
CELL[7].IMUX_IMUX[38]PLL[0].TESTIN[12]
CELL[7].IMUX_IMUX[39]PLL[0].TESTIN[9]
CELL[7].IMUX_IMUX[40]PLL[0].TESTIN[29]
CELL[7].IMUX_IMUX[41]PLL[0].TESTIN[26]
CELL[7].IMUX_IMUX[42]PLL[0].TESTIN[23]
CELL[7].IMUX_IMUX[43]PLL[0].TESTIN[20]
CELL[7].IMUX_IMUX[44]PPR_FRAME.DB[28]
CELL[7].IMUX_IMUX[45]PPR_FRAME.DB[29]
CELL[7].IMUX_IMUX[46]PPR_FRAME.DB[30]
CELL[7].IMUX_IMUX[47]PPR_FRAME.DB[31]
CELL[7].OUT_BEL[0]PLL[0].TESTOUT[8]
CELL[7].OUT_BEL[1]PLL[0].TESTOUT[7]
CELL[7].OUT_BEL[2]PLL[0].TESTOUT[4]
CELL[7].OUT_BEL[3]PLL[0].TESTOUT[3]
CELL[7].OUT_BEL[4]PLL[0].TESTOUT[9]
CELL[7].OUT_BEL[5]PLL[0].TESTOUT[6]
CELL[7].OUT_BEL[6]PLL[0].TESTOUT[5]
CELL[7].OUT_BEL[7]PLL[0].TESTOUT[2]
CELL[8].IMUX_IMUX[8]PLL[0].TESTIN[8]
CELL[8].IMUX_IMUX[9]PLL[0].TESTIN[6]
CELL[8].IMUX_IMUX[10]PLL[0].TESTIN[4]
CELL[8].IMUX_IMUX[11]PLL[0].TESTIN[2]
CELL[8].IMUX_IMUX[24]PLL[0].TESTIN[7]
CELL[8].IMUX_IMUX[25]PLL[0].TESTIN[5]
CELL[8].IMUX_IMUX[26]PLL[0].TESTIN[3]
CELL[8].IMUX_IMUX[27]PLL[0].TESTIN[1]
CELL[8].IMUX_IMUX[44]PPR_FRAME.DB[32]
CELL[8].IMUX_IMUX[45]PPR_FRAME.DB[33]
CELL[8].IMUX_IMUX[46]PPR_FRAME.DB[34]
CELL[8].IMUX_IMUX[47]PPR_FRAME.DB[35]
CELL[8].OUT_BEL[0]PLL[0].TESTOUT[0]
CELL[8].OUT_BEL[1]PLL[0].TESTOUT[63]
CELL[8].OUT_BEL[2]PLL[0].TESTOUT[60]
CELL[8].OUT_BEL[3]PLL[0].TESTOUT[59]
CELL[8].OUT_BEL[4]PLL[0].TESTOUT[1]
CELL[8].OUT_BEL[5]PLL[0].TESTOUT[62]
CELL[8].OUT_BEL[6]PLL[0].TESTOUT[61]
CELL[8].OUT_BEL[7]PLL[0].TESTOUT[58]
CELL[9].IMUX_IMUX[44]PPR_FRAME.DB[36]
CELL[9].IMUX_IMUX[45]PPR_FRAME.DB[37]
CELL[9].IMUX_IMUX[46]PPR_FRAME.DB[38]
CELL[9].IMUX_IMUX[47]PPR_FRAME.DB[39]
CELL[9].OUT_BEL[0]PLL[0].TESTOUT[56]
CELL[9].OUT_BEL[1]PLL[0].TESTOUT[55]
CELL[9].OUT_BEL[2]PLL[0].TESTOUT[52]
CELL[9].OUT_BEL[3]PLL[0].TESTOUT[51]
CELL[9].OUT_BEL[4]PLL[0].TESTOUT[57]
CELL[9].OUT_BEL[5]PLL[0].TESTOUT[54]
CELL[9].OUT_BEL[6]PLL[0].TESTOUT[53]
CELL[9].OUT_BEL[7]PLL[0].TESTOUT[50]
CELL[10].IMUX_IMUX[44]PPR_FRAME.DB[40]
CELL[10].IMUX_IMUX[45]PPR_FRAME.DB[41]
CELL[10].IMUX_IMUX[46]PPR_FRAME.DB[42]
CELL[10].IMUX_IMUX[47]PPR_FRAME.DB[43]
CELL[10].OUT_BEL[0]PLL[0].TESTOUT[48]
CELL[10].OUT_BEL[1]PLL[0].TESTOUT[47]
CELL[10].OUT_BEL[2]PLL[0].TESTOUT[44]
CELL[10].OUT_BEL[3]PLL[0].TESTOUT[43]
CELL[10].OUT_BEL[4]PLL[0].TESTOUT[49]
CELL[10].OUT_BEL[5]PLL[0].TESTOUT[46]
CELL[10].OUT_BEL[6]PLL[0].TESTOUT[45]
CELL[10].OUT_BEL[7]PLL[0].TESTOUT[42]
CELL[11].IMUX_IMUX[44]PPR_FRAME.DB[44]
CELL[11].IMUX_IMUX[45]PPR_FRAME.DB[45]
CELL[11].IMUX_IMUX[46]PPR_FRAME.DB[46]
CELL[11].IMUX_IMUX[47]PPR_FRAME.DB[47]
CELL[12].IMUX_IMUX[44]PPR_FRAME.DB[48]
CELL[12].IMUX_IMUX[45]PPR_FRAME.DB[49]
CELL[12].IMUX_IMUX[46]PPR_FRAME.DB[50]
CELL[12].IMUX_IMUX[47]PPR_FRAME.DB[51]
CELL[13].IMUX_IMUX[44]PPR_FRAME.DB[52]
CELL[13].IMUX_IMUX[45]PPR_FRAME.DB[53]
CELL[13].IMUX_IMUX[46]PPR_FRAME.DB[54]
CELL[13].IMUX_IMUX[47]PPR_FRAME.DB[55]
CELL[14].IMUX_IMUX[44]PPR_FRAME.DB[56]
CELL[14].IMUX_IMUX[45]PPR_FRAME.DB[57]
CELL[14].IMUX_IMUX[46]PPR_FRAME.DB[58]
CELL[14].IMUX_IMUX[47]PPR_FRAME.DB[59]
CELL[15].IMUX_IMUX[44]PPR_FRAME.DB[60]
CELL[15].IMUX_IMUX[45]PPR_FRAME.DB[61]
CELL[15].IMUX_IMUX[46]PPR_FRAME.DB[62]
CELL[15].IMUX_IMUX[47]PPR_FRAME.DB[63]
CELL[16].IMUX_IMUX[44]PPR_FRAME.DB[64]
CELL[16].IMUX_IMUX[45]PPR_FRAME.DB[65]
CELL[16].IMUX_IMUX[46]PPR_FRAME.DB[66]
CELL[16].IMUX_IMUX[47]PPR_FRAME.DB[67]
CELL[17].IMUX_IMUX[14]PLL[0].TESTIN[0]
CELL[17].IMUX_IMUX[44]PPR_FRAME.DB[68]
CELL[17].IMUX_IMUX[45]PPR_FRAME.DB[69]
CELL[17].IMUX_IMUX[46]PPR_FRAME.DB[70]
CELL[17].IMUX_IMUX[47]PPR_FRAME.DB[71]
CELL[17].IMUX_SPEC[3]PLL[0].TESTOUT[32], PLL[0].TESTOUT[33], PLL[0].TESTOUT[34], PLL[0].TESTOUT[35], PLL[0].TESTOUT[36], PLL[0].TESTOUT[37], PLL[0].TESTOUT[38], PLL[0].TESTOUT[39], PLL[0].TESTOUT[40], PLL[0].TESTOUT[41]
CELL[18].IMUX_IMUX[44]PPR_FRAME.DB[72]
CELL[18].IMUX_IMUX[45]PPR_FRAME.DB[73]
CELL[18].IMUX_IMUX[46]PPR_FRAME.DB[74]
CELL[18].IMUX_IMUX[47]PPR_FRAME.DB[75]
CELL[19].IMUX_IMUX[0]BUFHCE_W[0].CE
CELL[19].IMUX_IMUX[1]BUFHCE_W[1].CE
CELL[19].IMUX_IMUX[2]BUFHCE_W[2].CE
CELL[19].IMUX_IMUX[3]BUFHCE_W[3].CE
CELL[19].IMUX_IMUX[4]BUFHCE_W[4].CE
CELL[19].IMUX_IMUX[5]BUFHCE_W[5].CE
CELL[19].IMUX_IMUX[6]BUFHCE_E[0].CE
CELL[19].IMUX_IMUX[7]BUFHCE_E[1].CE
CELL[19].IMUX_IMUX[8]BUFHCE_E[2].CE
CELL[19].IMUX_IMUX[9]BUFHCE_E[3].CE
CELL[19].IMUX_IMUX[10]BUFHCE_E[4].CE
CELL[19].IMUX_IMUX[11]BUFHCE_E[5].CE
CELL[19].IMUX_IMUX[42]PPR_FRAME.DH[0]
CELL[19].IMUX_IMUX[43]PPR_FRAME.DH[1]
CELL[19].IMUX_IMUX[44]PPR_FRAME.DB[76]
CELL[19].IMUX_IMUX[45]PPR_FRAME.DB[77]
CELL[19].IMUX_IMUX[46]PPR_FRAME.DB[78]
CELL[19].IMUX_IMUX[47]PPR_FRAME.DB[79]
CELL[20].IMUX_IMUX[0]BUFHCE_W[6].CE
CELL[20].IMUX_IMUX[1]BUFHCE_W[7].CE
CELL[20].IMUX_IMUX[2]BUFHCE_W[8].CE
CELL[20].IMUX_IMUX[3]BUFHCE_W[9].CE
CELL[20].IMUX_IMUX[4]BUFHCE_W[10].CE
CELL[20].IMUX_IMUX[5]BUFHCE_W[11].CE
CELL[20].IMUX_IMUX[6]BUFHCE_E[6].CE
CELL[20].IMUX_IMUX[7]BUFHCE_E[7].CE
CELL[20].IMUX_IMUX[8]BUFHCE_E[8].CE
CELL[20].IMUX_IMUX[9]BUFHCE_E[9].CE
CELL[20].IMUX_IMUX[10]BUFHCE_E[10].CE
CELL[20].IMUX_IMUX[11]BUFHCE_E[11].CE
CELL[20].IMUX_IMUX[44]PPR_FRAME.DA[0]
CELL[20].IMUX_IMUX[45]PPR_FRAME.DA[1]
CELL[20].IMUX_IMUX[46]PPR_FRAME.DA[2]
CELL[20].IMUX_IMUX[47]PPR_FRAME.DA[3]
CELL[20].IMUX_BUFHCE_W[0]BUFHCE_W[0].I
CELL[20].IMUX_BUFHCE_W[1]BUFHCE_W[1].I
CELL[20].IMUX_BUFHCE_W[2]BUFHCE_W[2].I
CELL[20].IMUX_BUFHCE_W[3]BUFHCE_W[3].I
CELL[20].IMUX_BUFHCE_W[4]BUFHCE_W[4].I
CELL[20].IMUX_BUFHCE_W[5]BUFHCE_W[5].I
CELL[20].IMUX_BUFHCE_W[6]BUFHCE_W[6].I
CELL[20].IMUX_BUFHCE_W[7]BUFHCE_W[7].I
CELL[20].IMUX_BUFHCE_W[8]BUFHCE_W[8].I
CELL[20].IMUX_BUFHCE_W[9]BUFHCE_W[9].I
CELL[20].IMUX_BUFHCE_W[10]BUFHCE_W[10].I
CELL[20].IMUX_BUFHCE_W[11]BUFHCE_W[11].I
CELL[20].IMUX_BUFHCE_E[0]BUFHCE_E[0].I
CELL[20].IMUX_BUFHCE_E[1]BUFHCE_E[1].I
CELL[20].IMUX_BUFHCE_E[2]BUFHCE_E[2].I
CELL[20].IMUX_BUFHCE_E[3]BUFHCE_E[3].I
CELL[20].IMUX_BUFHCE_E[4]BUFHCE_E[4].I
CELL[20].IMUX_BUFHCE_E[5]BUFHCE_E[5].I
CELL[20].IMUX_BUFHCE_E[6]BUFHCE_E[6].I
CELL[20].IMUX_BUFHCE_E[7]BUFHCE_E[7].I
CELL[20].IMUX_BUFHCE_E[8]BUFHCE_E[8].I
CELL[20].IMUX_BUFHCE_E[9]BUFHCE_E[9].I
CELL[20].IMUX_BUFHCE_E[10]BUFHCE_E[10].I
CELL[20].IMUX_BUFHCE_E[11]BUFHCE_E[11].I
CELL[20].HCLK_CMT_W[0]BUFHCE_W[0].O
CELL[20].HCLK_CMT_W[1]BUFHCE_W[1].O
CELL[20].HCLK_CMT_W[2]BUFHCE_W[2].O
CELL[20].HCLK_CMT_W[3]BUFHCE_W[3].O
CELL[20].HCLK_CMT_W[4]BUFHCE_W[4].O
CELL[20].HCLK_CMT_W[5]BUFHCE_W[5].O
CELL[20].HCLK_CMT_W[6]BUFHCE_W[6].O
CELL[20].HCLK_CMT_W[7]BUFHCE_W[7].O
CELL[20].HCLK_CMT_W[8]BUFHCE_W[8].O
CELL[20].HCLK_CMT_W[9]BUFHCE_W[9].O
CELL[20].HCLK_CMT_W[10]BUFHCE_W[10].O
CELL[20].HCLK_CMT_W[11]BUFHCE_W[11].O
CELL[20].HCLK_CMT_E[0]BUFHCE_E[0].O
CELL[20].HCLK_CMT_E[1]BUFHCE_E[1].O
CELL[20].HCLK_CMT_E[2]BUFHCE_E[2].O
CELL[20].HCLK_CMT_E[3]BUFHCE_E[3].O
CELL[20].HCLK_CMT_E[4]BUFHCE_E[4].O
CELL[20].HCLK_CMT_E[5]BUFHCE_E[5].O
CELL[20].HCLK_CMT_E[6]BUFHCE_E[6].O
CELL[20].HCLK_CMT_E[7]BUFHCE_E[7].O
CELL[20].HCLK_CMT_E[8]BUFHCE_E[8].O
CELL[20].HCLK_CMT_E[9]BUFHCE_E[9].O
CELL[20].HCLK_CMT_E[10]BUFHCE_E[10].O
CELL[20].HCLK_CMT_E[11]BUFHCE_E[11].O
CELL[20].IMUX_PLL_CLKIN1[0]PLL[0].CLKIN1
CELL[20].IMUX_PLL_CLKIN1[1]PLL[1].CLKIN1
CELL[20].IMUX_PLL_CLKIN2[0]PLL[0].CLKIN2
CELL[20].IMUX_PLL_CLKIN2[1]PLL[1].CLKIN2
CELL[20].IMUX_PLL_CLKFB[0]PLL[0].CLKFBIN
CELL[20].IMUX_PLL_CLKFB[1]PLL[1].CLKFBIN
CELL[20].OUT_PLL_S[0]PLL[0].CLKOUT0
CELL[20].OUT_PLL_S[1]PLL[0].CLKOUT0B
CELL[20].OUT_PLL_S[2]PLL[0].CLKOUT1
CELL[20].OUT_PLL_S[3]PLL[0].CLKOUT1B
CELL[20].OUT_PLL_S[4]PLL[0].CLKOUT2
CELL[20].OUT_PLL_S[5]PLL[0].CLKOUT2B
CELL[20].OUT_PLL_S[6]PLL[0].CLKOUT3
CELL[20].OUT_PLL_S[7]PLL[0].CLKOUT3B
CELL[20].OUT_PLL_S[8]PLL[0].CLKOUT4
CELL[20].OUT_PLL_S[9]PLL[0].CLKOUT5
CELL[20].OUT_PLL_S[10]PLL[0].CLKOUT6
CELL[20].OUT_PLL_S[11]PLL[0].CLKFBOUT
CELL[20].OUT_PLL_S[12]PLL[0].CLKFBOUTB
CELL[20].OUT_PLL_S[13]PLL[0].TMUXOUT
CELL[20].OUT_PLL_N[0]PLL[1].CLKOUT0
CELL[20].OUT_PLL_N[1]PLL[1].CLKOUT0B
CELL[20].OUT_PLL_N[2]PLL[1].CLKOUT1
CELL[20].OUT_PLL_N[3]PLL[1].CLKOUT1B
CELL[20].OUT_PLL_N[4]PLL[1].CLKOUT2
CELL[20].OUT_PLL_N[5]PLL[1].CLKOUT2B
CELL[20].OUT_PLL_N[6]PLL[1].CLKOUT3
CELL[20].OUT_PLL_N[7]PLL[1].CLKOUT3B
CELL[20].OUT_PLL_N[8]PLL[1].CLKOUT4
CELL[20].OUT_PLL_N[9]PLL[1].CLKOUT5
CELL[20].OUT_PLL_N[10]PLL[1].CLKOUT6
CELL[20].OUT_PLL_N[11]PLL[1].CLKFBOUT
CELL[20].OUT_PLL_N[12]PLL[1].CLKFBOUTB
CELL[20].OUT_PLL_N[13]PLL[1].TMUXOUT
CELL[20].OMUX_PLL_CASC[0]PLL[1].CLKIN_CASC, PLL[0].CLKFB_CASC
CELL[20].OMUX_PLL_CASC[1]PLL[0].CLKIN_CASC, PLL[1].CLKFB_CASC
CELL[21].IMUX_IMUX[44]PPR_FRAME.DA[4]
CELL[21].IMUX_IMUX[45]PPR_FRAME.DA[5]
CELL[21].IMUX_IMUX[46]PPR_FRAME.DA[6]
CELL[21].IMUX_IMUX[47]PPR_FRAME.DA[7]
CELL[22].IMUX_IMUX[33]PLL[1].TESTIN[0]
CELL[22].IMUX_IMUX[44]PPR_FRAME.DA[8]
CELL[22].IMUX_IMUX[45]PPR_FRAME.DA[9]
CELL[22].IMUX_IMUX[46]PPR_FRAME.DA[10]
CELL[22].IMUX_IMUX[47]PPR_FRAME.DA[11]
CELL[23].IMUX_IMUX[44]PPR_FRAME.DA[12]
CELL[23].IMUX_IMUX[45]PPR_FRAME.DA[13]
CELL[23].IMUX_IMUX[46]PPR_FRAME.DA[14]
CELL[23].IMUX_IMUX[47]PPR_FRAME.DA[15]
CELL[24].IMUX_IMUX[44]PPR_FRAME.DA[16]
CELL[24].IMUX_IMUX[45]PPR_FRAME.DA[17]
CELL[24].IMUX_IMUX[46]PPR_FRAME.DA[18]
CELL[24].IMUX_IMUX[47]PPR_FRAME.DA[19]
CELL[25].IMUX_IMUX[44]PPR_FRAME.DA[20]
CELL[25].IMUX_IMUX[45]PPR_FRAME.DA[21]
CELL[25].IMUX_IMUX[46]PPR_FRAME.DA[22]
CELL[25].IMUX_IMUX[47]PPR_FRAME.DA[23]
CELL[26].IMUX_IMUX[44]PPR_FRAME.DA[24]
CELL[26].IMUX_IMUX[45]PPR_FRAME.DA[25]
CELL[26].IMUX_IMUX[46]PPR_FRAME.DA[26]
CELL[26].IMUX_IMUX[47]PPR_FRAME.DA[27]
CELL[27].IMUX_IMUX[44]PPR_FRAME.DA[28]
CELL[27].IMUX_IMUX[45]PPR_FRAME.DA[29]
CELL[27].IMUX_IMUX[46]PPR_FRAME.DA[30]
CELL[27].IMUX_IMUX[47]PPR_FRAME.DA[31]
CELL[27].OUT_BEL[3]PLL[1].TESTOUT[32]
CELL[27].OUT_BEL[7]PLL[1].TESTOUT[33]
CELL[28].IMUX_IMUX[44]PPR_FRAME.DA[32]
CELL[28].IMUX_IMUX[45]PPR_FRAME.DA[33]
CELL[28].IMUX_IMUX[46]PPR_FRAME.DA[34]
CELL[28].IMUX_IMUX[47]PPR_FRAME.DA[35]
CELL[29].IMUX_IMUX[44]PPR_FRAME.DA[36]
CELL[29].IMUX_IMUX[45]PPR_FRAME.DA[37]
CELL[29].IMUX_IMUX[46]PPR_FRAME.DA[38]
CELL[29].IMUX_IMUX[47]PPR_FRAME.DA[39]
CELL[29].OUT_BEL[0]PLL[1].TESTOUT[43]
CELL[29].OUT_BEL[1]PLL[1].TESTOUT[44]
CELL[29].OUT_BEL[2]PLL[1].TESTOUT[47]
CELL[29].OUT_BEL[3]PLL[1].TESTOUT[48]
CELL[29].OUT_BEL[4]PLL[1].TESTOUT[42]
CELL[29].OUT_BEL[5]PLL[1].TESTOUT[45]
CELL[29].OUT_BEL[6]PLL[1].TESTOUT[46]
CELL[29].OUT_BEL[7]PLL[1].TESTOUT[49]
CELL[30].IMUX_IMUX[44]PPR_FRAME.DA[40]
CELL[30].IMUX_IMUX[45]PPR_FRAME.DA[41]
CELL[30].IMUX_IMUX[46]PPR_FRAME.DA[42]
CELL[30].IMUX_IMUX[47]PPR_FRAME.DA[43]
CELL[30].OUT_BEL[0]PLL[1].TESTOUT[51]
CELL[30].OUT_BEL[1]PLL[1].TESTOUT[52]
CELL[30].OUT_BEL[2]PLL[1].TESTOUT[55]
CELL[30].OUT_BEL[3]PLL[1].TESTOUT[56]
CELL[30].OUT_BEL[4]PLL[1].TESTOUT[50]
CELL[30].OUT_BEL[5]PLL[1].TESTOUT[53]
CELL[30].OUT_BEL[6]PLL[1].TESTOUT[54]
CELL[30].OUT_BEL[7]PLL[1].TESTOUT[57]
CELL[31].IMUX_IMUX[20]PLL[1].TESTIN[1]
CELL[31].IMUX_IMUX[21]PLL[1].TESTIN[3]
CELL[31].IMUX_IMUX[22]PLL[1].TESTIN[5]
CELL[31].IMUX_IMUX[23]PLL[1].TESTIN[7]
CELL[31].IMUX_IMUX[36]PLL[1].TESTIN[2]
CELL[31].IMUX_IMUX[37]PLL[1].TESTIN[4]
CELL[31].IMUX_IMUX[38]PLL[1].TESTIN[6]
CELL[31].IMUX_IMUX[39]PLL[1].TESTIN[8]
CELL[31].IMUX_IMUX[44]PPR_FRAME.DA[44]
CELL[31].IMUX_IMUX[45]PPR_FRAME.DA[45]
CELL[31].IMUX_IMUX[46]PPR_FRAME.DA[46]
CELL[31].IMUX_IMUX[47]PPR_FRAME.DA[47]
CELL[31].OUT_BEL[0]PLL[1].TESTOUT[59]
CELL[31].OUT_BEL[1]PLL[1].TESTOUT[60]
CELL[31].OUT_BEL[2]PLL[1].TESTOUT[63]
CELL[31].OUT_BEL[3]PLL[1].TESTOUT[0]
CELL[31].OUT_BEL[4]PLL[1].TESTOUT[58]
CELL[31].OUT_BEL[5]PLL[1].TESTOUT[61]
CELL[31].OUT_BEL[6]PLL[1].TESTOUT[62]
CELL[31].OUT_BEL[7]PLL[1].TESTOUT[1]
CELL[32].IMUX_IMUX[4]PLL[1].TESTIN[20]
CELL[32].IMUX_IMUX[5]PLL[1].TESTIN[23]
CELL[32].IMUX_IMUX[6]PLL[1].TESTIN[26]
CELL[32].IMUX_IMUX[7]PLL[1].TESTIN[29]
CELL[32].IMUX_IMUX[8]PLL[1].TESTIN[9]
CELL[32].IMUX_IMUX[9]PLL[1].TESTIN[12]
CELL[32].IMUX_IMUX[10]PLL[1].TESTIN[15]
CELL[32].IMUX_IMUX[19]PLL[1].TESTIN[18]
CELL[32].IMUX_IMUX[20]PLL[1].TESTIN[21]
CELL[32].IMUX_IMUX[21]PLL[1].TESTIN[24]
CELL[32].IMUX_IMUX[22]PLL[1].TESTIN[27]
CELL[32].IMUX_IMUX[23]PLL[1].TESTIN[30]
CELL[32].IMUX_IMUX[24]PLL[1].TESTIN[10]
CELL[32].IMUX_IMUX[25]PLL[1].TESTIN[13]
CELL[32].IMUX_IMUX[26]PLL[1].TESTIN[16]
CELL[32].IMUX_IMUX[35]PLL[1].TESTIN[19]
CELL[32].IMUX_IMUX[36]PLL[1].TESTIN[22]
CELL[32].IMUX_IMUX[37]PLL[1].TESTIN[25]
CELL[32].IMUX_IMUX[38]PLL[1].TESTIN[28]
CELL[32].IMUX_IMUX[39]PLL[1].TESTIN[31]
CELL[32].IMUX_IMUX[40]PLL[1].TESTIN[11]
CELL[32].IMUX_IMUX[41]PLL[1].TESTIN[14]
CELL[32].IMUX_IMUX[42]PLL[1].TESTIN[17]
CELL[32].IMUX_IMUX[44]PPR_FRAME.DA[48]
CELL[32].IMUX_IMUX[45]PPR_FRAME.DA[49]
CELL[32].IMUX_IMUX[46]PPR_FRAME.DA[50]
CELL[32].IMUX_IMUX[47]PPR_FRAME.DA[51]
CELL[32].OUT_BEL[0]PLL[1].TESTOUT[3]
CELL[32].OUT_BEL[1]PLL[1].TESTOUT[4]
CELL[32].OUT_BEL[2]PLL[1].TESTOUT[7]
CELL[32].OUT_BEL[3]PLL[1].TESTOUT[8]
CELL[32].OUT_BEL[4]PLL[1].TESTOUT[2]
CELL[32].OUT_BEL[5]PLL[1].TESTOUT[5]
CELL[32].OUT_BEL[6]PLL[1].TESTOUT[6]
CELL[32].OUT_BEL[7]PLL[1].TESTOUT[9]
CELL[33].IMUX_IMUX[44]PPR_FRAME.DA[52]
CELL[33].IMUX_IMUX[45]PPR_FRAME.DA[53]
CELL[33].IMUX_IMUX[46]PPR_FRAME.DA[54]
CELL[33].IMUX_IMUX[47]PPR_FRAME.DA[55]
CELL[33].OUT_BEL[0]PLL[1].TESTOUT[11]
CELL[33].OUT_BEL[1]PLL[1].TESTOUT[12]
CELL[33].OUT_BEL[2]PLL[1].TESTOUT[15]
CELL[33].OUT_BEL[3]PLL[1].TESTOUT[16]
CELL[33].OUT_BEL[4]PLL[1].TESTOUT[10]
CELL[33].OUT_BEL[5]PLL[1].TESTOUT[13]
CELL[33].OUT_BEL[6]PLL[1].TESTOUT[14]
CELL[33].OUT_BEL[7]PLL[1].TESTOUT[17]
CELL[34].IMUX_IMUX[4]PLL[1].DADDR[3]
CELL[34].IMUX_IMUX[5]PLL[1].DADDR[4]
CELL[34].IMUX_IMUX[6]PLL[1].DADDR[5]
CELL[34].IMUX_IMUX[7]PLL[1].DADDR[6]
CELL[34].IMUX_IMUX[40]PLL[1].DADDR[0]
CELL[34].IMUX_IMUX[41]PLL[1].DADDR[1]
CELL[34].IMUX_IMUX[42]PLL[1].DADDR[2]
CELL[34].IMUX_IMUX[44]PPR_FRAME.DA[56]
CELL[34].IMUX_IMUX[45]PPR_FRAME.DA[57]
CELL[34].IMUX_IMUX[46]PPR_FRAME.DA[58]
CELL[34].IMUX_IMUX[47]PPR_FRAME.DA[59]
CELL[34].OUT_BEL[0]PLL[1].TESTOUT[19]
CELL[34].OUT_BEL[1]PLL[1].TESTOUT[20]
CELL[34].OUT_BEL[2]PLL[1].TESTOUT[23]
CELL[34].OUT_BEL[3]PLL[1].TESTOUT[24]
CELL[34].OUT_BEL[4]PLL[1].TESTOUT[18]
CELL[34].OUT_BEL[5]PLL[1].TESTOUT[21]
CELL[34].OUT_BEL[6]PLL[1].TESTOUT[22]
CELL[34].OUT_BEL[7]PLL[1].TESTOUT[25]
CELL[35].IMUX_IMUX[30]PLL[1].DI[6]
CELL[35].IMUX_IMUX[31]PLL[1].DI[7]
CELL[35].IMUX_IMUX[32]PLL[1].DI[0]
CELL[35].IMUX_IMUX[33]PLL[1].DI[1]
CELL[35].IMUX_IMUX[34]PLL[1].DI[2]
CELL[35].IMUX_IMUX[35]PLL[1].DI[3]
CELL[35].IMUX_IMUX[36]PLL[1].DI[4]
CELL[35].IMUX_IMUX[37]PLL[1].DI[5]
CELL[35].IMUX_IMUX[40]PPR_FRAME.SHIFTB
CELL[35].IMUX_IMUX[41]PPR_FRAME.UPDATEB
CELL[35].IMUX_IMUX[42]PPR_FRAME.ENB
CELL[35].IMUX_IMUX[43]PPR_FRAME.CTLB
CELL[35].IMUX_IMUX[44]PPR_FRAME.DA[60]
CELL[35].IMUX_IMUX[45]PPR_FRAME.DA[61]
CELL[35].IMUX_IMUX[46]PPR_FRAME.DA[62]
CELL[35].IMUX_IMUX[47]PPR_FRAME.DA[63]
CELL[35].OUT_BEL[0]PLL[1].TESTOUT[27]
CELL[35].OUT_BEL[1]PLL[1].TESTOUT[28]
CELL[35].OUT_BEL[2]PLL[1].TESTOUT[31]
CELL[35].OUT_BEL[3]PLL[1].CLKFBSTOPPED
CELL[35].OUT_BEL[4]PLL[1].TESTOUT[26]
CELL[35].OUT_BEL[5]PLL[1].TESTOUT[29]
CELL[35].OUT_BEL[6]PLL[1].TESTOUT[30]
CELL[35].OUT_BEL[7]PLL[1].CLKINSTOPPED
CELL[36].IMUX_IMUX[8]PLL[1].DI[8]
CELL[36].IMUX_IMUX[10]PLL[1].DI[11]
CELL[36].IMUX_IMUX[11]PLL[1].DI[13]
CELL[36].IMUX_IMUX[12]PLL[1].DI[15]
CELL[36].IMUX_IMUX[13]PLL[1].PWRDWN
CELL[36].IMUX_IMUX[14]PLL[1].PSEN
CELL[36].IMUX_IMUX[15]PLL[1].PSINCDEC
CELL[36].IMUX_IMUX[25]PLL[1].DI[10]
CELL[36].IMUX_IMUX[34]PLL[1].DI[12]
CELL[36].IMUX_IMUX[35]PLL[1].DI[14]
CELL[36].IMUX_IMUX[36]PLL[1].CLKINSEL
CELL[36].IMUX_IMUX[37]PLL[1].DWE
CELL[36].IMUX_IMUX[38]PLL[1].DEN
CELL[36].IMUX_IMUX[39]PLL[1].RST
CELL[36].IMUX_IMUX[40]PLL[1].DI[9]
CELL[36].IMUX_IMUX[44]PPR_FRAME.DA[64]
CELL[36].IMUX_IMUX[45]PPR_FRAME.DA[65]
CELL[36].IMUX_IMUX[46]PPR_FRAME.DA[66]
CELL[36].IMUX_IMUX[47]PPR_FRAME.DA[67]
CELL[36].OUT_BEL[0]PLL[1].DO[1]
CELL[36].OUT_BEL[1]PLL[1].DO[2]
CELL[36].OUT_BEL[2]PLL[1].DO[5]
CELL[36].OUT_BEL[3]PLL[1].DO[6]
CELL[36].OUT_BEL[4]PLL[1].DO[0]
CELL[36].OUT_BEL[5]PLL[1].DO[3]
CELL[36].OUT_BEL[6]PLL[1].DO[4]
CELL[36].OUT_BEL[7]PLL[1].DO[7]
CELL[37].IMUX_CLK[0]PLL[1].PSCLK
CELL[37].IMUX_CLK[1]PLL[1].DCLK
CELL[37].IMUX_IMUX[44]PPR_FRAME.DA[68]
CELL[37].IMUX_IMUX[45]PPR_FRAME.DA[69]
CELL[37].IMUX_IMUX[46]PPR_FRAME.DA[70]
CELL[37].IMUX_IMUX[47]PPR_FRAME.DA[71]
CELL[37].OUT_BEL[1]PLL[1].DO[11]
CELL[37].OUT_BEL[2]PLL[1].DO[15]
CELL[37].OUT_BEL[3]PLL[1].PSDONE
CELL[37].OUT_BEL[8]PLL[1].DO[8]
CELL[37].OUT_BEL[9]PLL[1].DO[12]
CELL[37].OUT_BEL[10]PLL[1].DO[13]
CELL[37].OUT_BEL[11]PLL[1].DRDY
CELL[37].OUT_BEL[16]PLL[1].DO[14]
CELL[37].OUT_BEL[17]PLL[1].LOCKED
CELL[37].OUT_BEL[18]PLL[1].DO[9]
CELL[37].OUT_BEL[22]PLL[1].DO[10]
CELL[37].IMUX_SPEC[3]PLL[1].TESTOUT[34], PLL[1].TESTOUT[35], PLL[1].TESTOUT[36], PLL[1].TESTOUT[37], PLL[1].TESTOUT[38], PLL[1].TESTOUT[39], PLL[1].TESTOUT[40], PLL[1].TESTOUT[41]
CELL[38].IMUX_IMUX[44]PPR_FRAME.DA[72]
CELL[38].IMUX_IMUX[45]PPR_FRAME.DA[73]
CELL[38].IMUX_IMUX[46]PPR_FRAME.DA[74]
CELL[38].IMUX_IMUX[47]PPR_FRAME.DA[75]
CELL[39].IMUX_CLK[1]PPR_FRAME.CLK
CELL[39].IMUX_IMUX[44]PPR_FRAME.DA[76]
CELL[39].IMUX_IMUX[45]PPR_FRAME.DA[77]
CELL[39].IMUX_IMUX[46]PPR_FRAME.DA[78]
CELL[39].IMUX_IMUX[47]PPR_FRAME.DA[79]

Bitstream

virtex6 CMT rect MAIN[0]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex6 CMT rect MAIN[1]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex6 CMT rect MAIN[2]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 0 PLL[0]: CONTROL_2 bit 0 PLL[0]: MMCM_DRP[120] bit 1 PLL[0]: CONTROL_2 bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 2 PLL[0]: CONTROL_2 bit 2 PLL[0]: MMCM_DRP[120] bit 3 PLL[0]: CONTROL_2 bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 4 PLL[0]: CONTROL_2 bit 4 PLL[0]: MMCM_DRP[120] bit 5 PLL[0]: CONTROL_2 bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 6 PLL[0]: CONTROL_2 bit 6 PLL[0]: MMCM_DRP[120] bit 7 PLL[0]: CONTROL_2 bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 8 PLL[0]: CONTROL_2 bit 8 PLL[0]: MMCM_DRP[120] bit 9 PLL[0]: CONTROL_2 bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 10 PLL[0]: CONTROL_2 bit 10 PLL[0]: MMCM_DRP[120] bit 11 PLL[0]: CONTROL_2 bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 12 PLL[0]: CONTROL_2 bit 12 PLL[0]: MMCM_DRP[120] bit 13 PLL[0]: CONTROL_2 bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[120] bit 14 PLL[0]: CONTROL_2 bit 14 PLL[0]: MMCM_DRP[120] bit 15 PLL[0]: CONTROL_2 bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 0 PLL[0]: CONTROL_3 bit 0 PLL[0]: MMCM_DRP[121] bit 1 PLL[0]: CONTROL_3 bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 2 PLL[0]: CONTROL_3 bit 2 PLL[0]: MMCM_DRP[121] bit 3 PLL[0]: CONTROL_3 bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 4 PLL[0]: CONTROL_3 bit 4 PLL[0]: MMCM_DRP[121] bit 5 PLL[0]: CONTROL_3 bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 6 PLL[0]: CONTROL_3 bit 6 PLL[0]: MMCM_DRP[121] bit 7 PLL[0]: CONTROL_3 bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 8 PLL[0]: CONTROL_3 bit 8 PLL[0]: MMCM_DRP[121] bit 9 PLL[0]: CONTROL_3 bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 10 PLL[0]: CONTROL_3 bit 10 PLL[0]: MMCM_DRP[121] bit 11 PLL[0]: CONTROL_3 bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 12 PLL[0]: CONTROL_3 bit 12 PLL[0]: MMCM_DRP[121] bit 13 PLL[0]: CONTROL_3 bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[121] bit 14 PLL[0]: CONTROL_3 bit 14 PLL[0]: MMCM_DRP[121] bit 15 PLL[0]: CONTROL_3 bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 0 PLL[0]: CONTROL_4 bit 0 PLL[0]: MMCM_DRP[122] bit 1 PLL[0]: CONTROL_4 bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 2 PLL[0]: CONTROL_4 bit 2 PLL[0]: MMCM_DRP[122] bit 3 PLL[0]: CONTROL_4 bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 4 PLL[0]: CONTROL_4 bit 4 PLL[0]: MMCM_DRP[122] bit 5 PLL[0]: CONTROL_4 bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 6 PLL[0]: CONTROL_4 bit 6 PLL[0]: MMCM_DRP[122] bit 7 PLL[0]: CONTROL_4 bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 8 PLL[0]: CONTROL_4 bit 8 PLL[0]: MMCM_DRP[122] bit 9 PLL[0]: CONTROL_4 bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 10 PLL[0]: CONTROL_4 bit 10 PLL[0]: MMCM_DRP[122] bit 11 PLL[0]: CONTROL_4 bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 12 PLL[0]: CONTROL_4 bit 12 PLL[0]: MMCM_DRP[122] bit 13 PLL[0]: CONTROL_4 bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[122] bit 14 PLL[0]: CONTROL_4 bit 14 PLL[0]: MMCM_DRP[122] bit 15 PLL[0]: CONTROL_4 bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 0 PLL[0]: CONTROL_5 bit 0 PLL[0]: MMCM_DRP[123] bit 1 PLL[0]: CONTROL_5 bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 2 PLL[0]: CONTROL_5 bit 2 PLL[0]: MMCM_DRP[123] bit 3 PLL[0]: CONTROL_5 bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 4 PLL[0]: CONTROL_5 bit 4 PLL[0]: MMCM_DRP[123] bit 5 PLL[0]: CONTROL_5 bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 6 PLL[0]: CONTROL_5 bit 6 PLL[0]: MMCM_DRP[123] bit 7 PLL[0]: CONTROL_5 bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 8 PLL[0]: CONTROL_5 bit 8 PLL[0]: MMCM_DRP[123] bit 9 PLL[0]: CONTROL_5 bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 10 PLL[0]: CONTROL_5 bit 10 PLL[0]: MMCM_DRP[123] bit 11 PLL[0]: CONTROL_5 bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 12 PLL[0]: CONTROL_5 bit 12 PLL[0]: MMCM_DRP[123] bit 13 PLL[0]: CONTROL_5 bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[123] bit 14 PLL[0]: CONTROL_5 bit 14 PLL[0]: MMCM_DRP[123] bit 15 PLL[0]: CONTROL_5 bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 0 PLL[0]: MMCM_DRP[124] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 2 PLL[0]: MMCM_DRP[124] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 4 PLL[0]: MMCM_DRP[124] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 6 PLL[0]: MMCM_DRP[124] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 8 PLL[0]: MMCM_DRP[124] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 10 PLL[0]: MMCM_DRP[124] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 12 PLL[0]: MMCM_DRP[124] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[124] bit 14 PLL[0]: MMCM_DRP[124] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 0 PLL[0]: MMCM_DRP[125] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 2 PLL[0]: MMCM_DRP[125] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 4 PLL[0]: MMCM_DRP[125] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 6 PLL[0]: MMCM_DRP[125] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 8 PLL[0]: MMCM_DRP[125] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 10 PLL[0]: MMCM_DRP[125] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 12 PLL[0]: MMCM_DRP[125] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[125] bit 14 PLL[0]: MMCM_DRP[125] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 0 PLL[0]: MMCM_DRP[126] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 2 PLL[0]: MMCM_DRP[126] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 4 PLL[0]: MMCM_DRP[126] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 6 PLL[0]: MMCM_DRP[126] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 8 PLL[0]: MMCM_DRP[126] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 10 PLL[0]: MMCM_DRP[126] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 12 PLL[0]: MMCM_DRP[126] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[126] bit 14 PLL[0]: MMCM_DRP[126] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 0 PLL[0]: MMCM_DRP[127] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 2 PLL[0]: MMCM_DRP[127] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 4 PLL[0]: MMCM_DRP[127] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 6 PLL[0]: MMCM_DRP[127] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 8 PLL[0]: MMCM_DRP[127] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 10 PLL[0]: MMCM_DRP[127] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 12 PLL[0]: MMCM_DRP[127] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[127] bit 14 PLL[0]: MMCM_DRP[127] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[3]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 0 PLL[0]: MMCM_DRP[112] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 2 PLL[0]: MMCM_DRP[112] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 4 PLL[0]: MMCM_DRP[112] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 6 PLL[0]: MMCM_DRP[112] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 8 PLL[0]: MMCM_DRP[112] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 10 PLL[0]: MMCM_DRP[112] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 12 PLL[0]: MMCM_DRP[112] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[112] bit 14 PLL[0]: MMCM_DRP[112] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 0 PLL[0]: MMCM_DRP[113] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 2 PLL[0]: MMCM_DRP[113] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 4 PLL[0]: MMCM_DRP[113] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 6 PLL[0]: MMCM_DRP[113] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 8 PLL[0]: MMCM_DRP[113] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 10 PLL[0]: MMCM_DRP[113] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 12 PLL[0]: MMCM_DRP[113] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[113] bit 14 PLL[0]: MMCM_DRP[113] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: invert RST PLL[0]: MMCM_DRP[114] bit 0 PLL[0]: invert PWRDWN PLL[0]: MMCM_DRP[114] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: invert PSINCDEC PLL[0]: MMCM_DRP[114] bit 2 PLL[0]: invert PSEN PLL[0]: MMCM_DRP[114] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: invert CLKINSEL PLL[0]: MMCM_DRP[114] bit 4 PLL[0]: MMCM_DRP[114] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 6 PLL[0]: MMCM_DRP[114] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 8 PLL[0]: MMCM_DRP[114] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 10 PLL[0]: MMCM_DRP[114] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 12 PLL[0]: MMCM_DRP[114] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[114] bit 14 PLL[0]: MMCM_DRP[114] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 0 PLL[0]: MMCM_DRP[115] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 2 PLL[0]: MMCM_DRP[115] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 4 PLL[0]: MMCM_DRP[115] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 6 PLL[0]: MMCM_DRP[115] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 8 PLL[0]: MMCM_DRP[115] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 10 PLL[0]: MMCM_DRP[115] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 12 PLL[0]: MMCM_DRP[115] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[115] bit 14 PLL[0]: MMCM_DRP[115] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 0 PLL[0]: ENABLE PLL[0]: MMCM_DRP[116] bit 1 PLL[0]: CLOCK_HOLD - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 2 PLL[0]: STARTUP_WAIT PLL[0]: MMCM_DRP[116] bit 3 PLL[0]: GTS_WAIT - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 4 PLL[0]: CASC_LOCK_EN PLL[0]: MMCM_DRP[116] bit 5 PLL[0]: FINE_PS_FRAC bit 0 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 6 PLL[0]: FINE_PS_FRAC bit 1 PLL[0]: MMCM_DRP[116] bit 7 PLL[0]: FINE_PS_FRAC bit 2 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 8 PLL[0]: FINE_PS_FRAC bit 3 PLL[0]: MMCM_DRP[116] bit 9 PLL[0]: FINE_PS_FRAC bit 4 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 10 PLL[0]: FINE_PS_FRAC bit 5 PLL[0]: MMCM_DRP[116] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 12 PLL[0]: MMCM_DRP[116] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[116] bit 14 PLL[0]: MMCM_DRP[116] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 0 PLL[0]: MMCM_DRP[117] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 2 PLL[0]: MMCM_DRP[117] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 4 PLL[0]: MMCM_DRP[117] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 6 PLL[0]: MMCM_DRP[117] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 8 PLL[0]: MMCM_DRP[117] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 10 PLL[0]: MMCM_DRP[117] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 12 PLL[0]: MMCM_DRP[117] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[117] bit 14 PLL[0]: MMCM_DRP[117] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 0 PLL[0]: CONTROL_0 bit 0 PLL[0]: MMCM_DRP[118] bit 1 PLL[0]: CONTROL_0 bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 2 PLL[0]: CONTROL_0 bit 2 PLL[0]: MMCM_DRP[118] bit 3 PLL[0]: CONTROL_0 bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 4 PLL[0]: CONTROL_0 bit 4 PLL[0]: MMCM_DRP[118] bit 5 PLL[0]: CONTROL_0 bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 6 PLL[0]: CONTROL_0 bit 6 PLL[0]: MMCM_DRP[118] bit 7 PLL[0]: CONTROL_0 bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 8 PLL[0]: CONTROL_0 bit 8 PLL[0]: MMCM_DRP[118] bit 9 PLL[0]: CONTROL_0 bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 10 PLL[0]: CONTROL_0 bit 10 PLL[0]: MMCM_DRP[118] bit 11 PLL[0]: CONTROL_0 bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 12 PLL[0]: CONTROL_0 bit 12 PLL[0]: MMCM_DRP[118] bit 13 PLL[0]: CONTROL_0 bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[118] bit 14 PLL[0]: CONTROL_0 bit 14 PLL[0]: MMCM_DRP[118] bit 15 PLL[0]: CONTROL_0 bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 0 PLL[0]: CONTROL_1 bit 0 PLL[0]: MMCM_DRP[119] bit 1 PLL[0]: CONTROL_1 bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 2 PLL[0]: CONTROL_1 bit 2 PLL[0]: MMCM_DRP[119] bit 3 PLL[0]: CONTROL_1 bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 4 PLL[0]: CONTROL_1 bit 4 PLL[0]: MMCM_DRP[119] bit 5 PLL[0]: CONTROL_1 bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 6 PLL[0]: CONTROL_1 bit 6 PLL[0]: MMCM_DRP[119] bit 7 PLL[0]: CONTROL_1 bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 8 PLL[0]: CONTROL_1 bit 8 PLL[0]: MMCM_DRP[119] bit 9 PLL[0]: CONTROL_1 bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 10 PLL[0]: CONTROL_1 bit 10 PLL[0]: MMCM_DRP[119] bit 11 PLL[0]: CONTROL_1 bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 12 PLL[0]: CONTROL_1 bit 12 PLL[0]: MMCM_DRP[119] bit 13 PLL[0]: CONTROL_1 bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[119] bit 14 PLL[0]: CONTROL_1 bit 14 PLL[0]: MMCM_DRP[119] bit 15 PLL[0]: CONTROL_1 bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[4]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 0 PLL[0]: MMCM_DRP[104] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 2 PLL[0]: MMCM_DRP[104] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 4 PLL[0]: MMCM_DRP[104] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 6 PLL[0]: MMCM_DRP[104] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 8 PLL[0]: MMCM_DRP[104] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 10 PLL[0]: MMCM_DRP[104] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 12 PLL[0]: MMCM_DRP[104] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[104] bit 14 PLL[0]: MMCM_DRP[104] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 0 PLL[0]: MMCM_DRP[105] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 2 PLL[0]: MMCM_DRP[105] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 4 PLL[0]: MMCM_DRP[105] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 6 PLL[0]: MMCM_DRP[105] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 8 PLL[0]: MMCM_DRP[105] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 10 PLL[0]: MMCM_DRP[105] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 12 PLL[0]: MMCM_DRP[105] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[105] bit 14 PLL[0]: MMCM_DRP[105] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 0 PLL[0]: MMCM_DRP[106] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 2 PLL[0]: MMCM_DRP[106] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 4 PLL[0]: MMCM_DRP[106] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 6 PLL[0]: MMCM_DRP[106] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 8 PLL[0]: MMCM_DRP[106] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 10 PLL[0]: MMCM_DRP[106] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 12 PLL[0]: MMCM_DRP[106] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[106] bit 14 PLL[0]: MMCM_DRP[106] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 0 PLL[0]: MMCM_DRP[107] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 2 PLL[0]: MMCM_DRP[107] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 4 PLL[0]: MMCM_DRP[107] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 6 PLL[0]: MMCM_DRP[107] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 8 PLL[0]: MMCM_DRP[107] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 10 PLL[0]: MMCM_DRP[107] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 12 PLL[0]: MMCM_DRP[107] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[107] bit 14 PLL[0]: MMCM_DRP[107] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 0 PLL[0]: MMCM_DRP[108] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 2 PLL[0]: MMCM_DRP[108] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 4 PLL[0]: MMCM_DRP[108] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 6 PLL[0]: MMCM_DRP[108] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 8 PLL[0]: MMCM_DRP[108] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 10 PLL[0]: MMCM_DRP[108] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 12 PLL[0]: MMCM_DRP[108] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[108] bit 14 PLL[0]: MMCM_DRP[108] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 0 PLL[0]: MMCM_DRP[109] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 2 PLL[0]: MMCM_DRP[109] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 4 PLL[0]: MMCM_DRP[109] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 6 PLL[0]: MMCM_DRP[109] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 8 PLL[0]: MMCM_DRP[109] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 10 PLL[0]: MMCM_DRP[109] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 12 PLL[0]: MMCM_DRP[109] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[109] bit 14 PLL[0]: MMCM_DRP[109] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 0 PLL[0]: MMCM_DRP[110] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 2 PLL[0]: MMCM_DRP[110] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 4 PLL[0]: MMCM_DRP[110] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 6 PLL[0]: MMCM_DRP[110] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 8 PLL[0]: MMCM_DRP[110] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 10 PLL[0]: MMCM_DRP[110] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 12 PLL[0]: MMCM_DRP[110] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[110] bit 14 PLL[0]: MMCM_DRP[110] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 0 PLL[0]: MMCM_DRP[111] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 2 PLL[0]: MMCM_DRP[111] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 4 PLL[0]: MMCM_DRP[111] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 6 PLL[0]: MMCM_DRP[111] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 8 PLL[0]: MMCM_DRP[111] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 10 PLL[0]: MMCM_DRP[111] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 12 PLL[0]: MMCM_DRP[111] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[111] bit 14 PLL[0]: MMCM_DRP[111] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[5]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 0 PLL[0]: MMCM_DRP[96] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 2 PLL[0]: MMCM_DRP[96] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 4 PLL[0]: MMCM_DRP[96] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 6 PLL[0]: MMCM_DRP[96] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 8 PLL[0]: MMCM_DRP[96] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 10 PLL[0]: MMCM_DRP[96] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 12 PLL[0]: MMCM_DRP[96] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[96] bit 14 PLL[0]: MMCM_DRP[96] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 0 PLL[0]: MMCM_DRP[97] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 2 PLL[0]: MMCM_DRP[97] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 4 PLL[0]: MMCM_DRP[97] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 6 PLL[0]: MMCM_DRP[97] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 8 PLL[0]: MMCM_DRP[97] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 10 PLL[0]: MMCM_DRP[97] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 12 PLL[0]: MMCM_DRP[97] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[97] bit 14 PLL[0]: MMCM_DRP[97] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 0 PLL[0]: MMCM_DRP[98] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 2 PLL[0]: MMCM_DRP[98] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 4 PLL[0]: MMCM_DRP[98] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 6 PLL[0]: MMCM_DRP[98] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 8 PLL[0]: MMCM_DRP[98] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 10 PLL[0]: MMCM_DRP[98] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 12 PLL[0]: MMCM_DRP[98] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[98] bit 14 PLL[0]: MMCM_DRP[98] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 0 PLL[0]: MMCM_DRP[99] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 2 PLL[0]: MMCM_DRP[99] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 4 PLL[0]: MMCM_DRP[99] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 6 PLL[0]: MMCM_DRP[99] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 8 PLL[0]: MMCM_DRP[99] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 10 PLL[0]: MMCM_DRP[99] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 12 PLL[0]: MMCM_DRP[99] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[99] bit 14 PLL[0]: MMCM_DRP[99] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 0 PLL[0]: MMCM_DRP[100] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 2 PLL[0]: MMCM_DRP[100] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 4 PLL[0]: MMCM_DRP[100] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 6 PLL[0]: MMCM_DRP[100] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 8 PLL[0]: MMCM_DRP[100] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 10 PLL[0]: MMCM_DRP[100] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 12 PLL[0]: MMCM_DRP[100] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[100] bit 14 PLL[0]: MMCM_DRP[100] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 0 PLL[0]: MMCM_DRP[101] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 2 PLL[0]: MMCM_DRP[101] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 4 PLL[0]: MMCM_DRP[101] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 6 PLL[0]: MMCM_DRP[101] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 8 PLL[0]: MMCM_DRP[101] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 10 PLL[0]: MMCM_DRP[101] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 12 PLL[0]: MMCM_DRP[101] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[101] bit 14 PLL[0]: MMCM_DRP[101] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 0 PLL[0]: MMCM_DRP[102] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 2 PLL[0]: MMCM_DRP[102] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 4 PLL[0]: MMCM_DRP[102] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 6 PLL[0]: MMCM_DRP[102] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 8 PLL[0]: MMCM_DRP[102] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 10 PLL[0]: MMCM_DRP[102] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 12 PLL[0]: MMCM_DRP[102] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[102] bit 14 PLL[0]: MMCM_DRP[102] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 0 PLL[0]: MMCM_DRP[103] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 2 PLL[0]: MMCM_DRP[103] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 4 PLL[0]: MMCM_DRP[103] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 6 PLL[0]: MMCM_DRP[103] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 8 PLL[0]: MMCM_DRP[103] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 10 PLL[0]: MMCM_DRP[103] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 12 PLL[0]: MMCM_DRP[103] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[103] bit 14 PLL[0]: MMCM_DRP[103] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[6]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 0 PLL[0]: MMCM_DRP[88] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 2 PLL[0]: MMCM_DRP[88] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 4 PLL[0]: MMCM_DRP[88] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 6 PLL[0]: MMCM_DRP[88] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 8 PLL[0]: MMCM_DRP[88] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 10 PLL[0]: MMCM_DRP[88] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 12 PLL[0]: MMCM_DRP[88] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[88] bit 14 PLL[0]: MMCM_DRP[88] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 0 PLL[0]: MMCM_DRP[89] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 2 PLL[0]: MMCM_DRP[89] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 4 PLL[0]: MMCM_DRP[89] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 6 PLL[0]: MMCM_DRP[89] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 8 PLL[0]: MMCM_DRP[89] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 10 PLL[0]: MMCM_DRP[89] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 12 PLL[0]: MMCM_DRP[89] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[89] bit 14 PLL[0]: MMCM_DRP[89] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 0 PLL[0]: MMCM_DRP[90] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 2 PLL[0]: MMCM_DRP[90] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 4 PLL[0]: MMCM_DRP[90] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 6 PLL[0]: MMCM_DRP[90] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 8 PLL[0]: MMCM_DRP[90] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 10 PLL[0]: MMCM_DRP[90] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 12 PLL[0]: MMCM_DRP[90] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[90] bit 14 PLL[0]: MMCM_DRP[90] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 0 PLL[0]: MMCM_DRP[91] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 2 PLL[0]: MMCM_DRP[91] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 4 PLL[0]: MMCM_DRP[91] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 6 PLL[0]: MMCM_DRP[91] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 8 PLL[0]: MMCM_DRP[91] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 10 PLL[0]: MMCM_DRP[91] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 12 PLL[0]: MMCM_DRP[91] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[91] bit 14 PLL[0]: MMCM_DRP[91] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 0 PLL[0]: MMCM_DRP[92] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 2 PLL[0]: MMCM_DRP[92] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 4 PLL[0]: MMCM_DRP[92] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 6 PLL[0]: MMCM_DRP[92] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 8 PLL[0]: MMCM_DRP[92] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 10 PLL[0]: MMCM_DRP[92] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 12 PLL[0]: MMCM_DRP[92] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[92] bit 14 PLL[0]: MMCM_DRP[92] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 0 PLL[0]: MMCM_DRP[93] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 2 PLL[0]: MMCM_DRP[93] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 4 PLL[0]: MMCM_DRP[93] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 6 PLL[0]: MMCM_DRP[93] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 8 PLL[0]: MMCM_DRP[93] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 10 PLL[0]: MMCM_DRP[93] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 12 PLL[0]: MMCM_DRP[93] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[93] bit 14 PLL[0]: MMCM_DRP[93] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 0 PLL[0]: MMCM_DRP[94] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 2 PLL[0]: MMCM_DRP[94] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 4 PLL[0]: MMCM_DRP[94] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 6 PLL[0]: MMCM_DRP[94] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 8 PLL[0]: MMCM_DRP[94] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 10 PLL[0]: MMCM_DRP[94] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 12 PLL[0]: MMCM_DRP[94] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[94] bit 14 PLL[0]: MMCM_DRP[94] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 0 PLL[0]: MMCM_DRP[95] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 2 PLL[0]: MMCM_DRP[95] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 4 PLL[0]: MMCM_DRP[95] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 6 PLL[0]: MMCM_DRP[95] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 8 PLL[0]: MMCM_DRP[95] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 10 PLL[0]: MMCM_DRP[95] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 12 PLL[0]: MMCM_DRP[95] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[95] bit 14 PLL[0]: MMCM_DRP[95] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[7]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 0 PLL[0]: MMCM_DRP[80] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 2 PLL[0]: MMCM_DRP[80] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 4 PLL[0]: MMCM_DRP[80] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 6 PLL[0]: MMCM_DRP[80] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 8 PLL[0]: MMCM_DRP[80] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 10 PLL[0]: MMCM_DRP[80] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 12 PLL[0]: MMCM_DRP[80] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[80] bit 14 PLL[0]: MMCM_DRP[80] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 0 PLL[0]: MMCM_DRP[81] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 2 PLL[0]: MMCM_DRP[81] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 4 PLL[0]: MMCM_DRP[81] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 6 PLL[0]: MMCM_DRP[81] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 8 PLL[0]: MMCM_DRP[81] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 10 PLL[0]: MMCM_DRP[81] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 12 PLL[0]: MMCM_DRP[81] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[81] bit 14 PLL[0]: MMCM_DRP[81] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 0 PLL[0]: MMCM_DRP[82] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 2 PLL[0]: MMCM_DRP[82] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 4 PLL[0]: MMCM_DRP[82] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 6 PLL[0]: MMCM_DRP[82] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 8 PLL[0]: MMCM_DRP[82] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 10 PLL[0]: MMCM_DRP[82] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 12 PLL[0]: MMCM_DRP[82] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[82] bit 14 PLL[0]: MMCM_DRP[82] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 0 PLL[0]: MMCM_DRP[83] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 2 PLL[0]: MMCM_DRP[83] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 4 PLL[0]: MMCM_DRP[83] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 6 PLL[0]: MMCM_DRP[83] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 8 PLL[0]: MMCM_DRP[83] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 10 PLL[0]: MMCM_DRP[83] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 12 PLL[0]: MMCM_DRP[83] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[83] bit 14 PLL[0]: MMCM_DRP[83] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 0 PLL[0]: MMCM_DRP[84] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 2 PLL[0]: MMCM_DRP[84] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 4 PLL[0]: MMCM_DRP[84] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 6 PLL[0]: MMCM_DRP[84] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 8 PLL[0]: MMCM_DRP[84] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 10 PLL[0]: MMCM_DRP[84] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 12 PLL[0]: MMCM_DRP[84] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[84] bit 14 PLL[0]: MMCM_DRP[84] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 0 PLL[0]: MMCM_DRP[85] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 2 PLL[0]: MMCM_DRP[85] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 4 PLL[0]: MMCM_DRP[85] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 6 PLL[0]: MMCM_DRP[85] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 8 PLL[0]: MMCM_DRP[85] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 10 PLL[0]: MMCM_DRP[85] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 12 PLL[0]: MMCM_DRP[85] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[85] bit 14 PLL[0]: MMCM_DRP[85] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 0 PLL[0]: MMCM_DRP[86] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 2 PLL[0]: MMCM_DRP[86] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 4 PLL[0]: MMCM_DRP[86] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 6 PLL[0]: MMCM_DRP[86] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 8 PLL[0]: MMCM_DRP[86] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 10 PLL[0]: MMCM_DRP[86] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 12 PLL[0]: MMCM_DRP[86] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[86] bit 14 PLL[0]: MMCM_DRP[86] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 0 PLL[0]: MMCM_DRP[87] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 2 PLL[0]: MMCM_DRP[87] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 4 PLL[0]: MMCM_DRP[87] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 6 PLL[0]: MMCM_DRP[87] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 8 PLL[0]: MMCM_DRP[87] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 10 PLL[0]: MMCM_DRP[87] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 12 PLL[0]: MMCM_DRP[87] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[87] bit 14 PLL[0]: MMCM_DRP[87] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[8]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 0 PLL[0]: MMCM_DRP[72] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 2 PLL[0]: MMCM_DRP[72] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 4 PLL[0]: MMCM_DRP[72] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 6 PLL[0]: MMCM_DRP[72] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 8 PLL[0]: MMCM_DRP[72] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 10 PLL[0]: MMCM_DRP[72] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 12 PLL[0]: MMCM_DRP[72] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[72] bit 14 PLL[0]: MMCM_DRP[72] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 0 PLL[0]: MMCM_DRP[73] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 2 PLL[0]: MMCM_DRP[73] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 4 PLL[0]: MMCM_DRP[73] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 6 PLL[0]: MMCM_DRP[73] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 8 PLL[0]: MMCM_DRP[73] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 10 PLL[0]: MMCM_DRP[73] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 12 PLL[0]: MMCM_DRP[73] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[73] bit 14 PLL[0]: MMCM_DRP[73] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 0 PLL[0]: AVDD_VBG_SEL bit 0 PLL[0]: MMCM_DRP[74] bit 1 PLL[0]: AVDD_VBG_SEL bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 2 PLL[0]: AVDD_VBG_SEL bit 2 PLL[0]: MMCM_DRP[74] bit 3 PLL[0]: AVDD_VBG_SEL bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 4 PLL[0]: AVDD_VBG_PD bit 0 PLL[0]: MMCM_DRP[74] bit 5 PLL[0]: AVDD_VBG_PD bit 1 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 6 PLL[0]: AVDD_VBG_PD bit 2 PLL[0]: MMCM_DRP[74] bit 7 PLL[0]: V6_AVDD_COMP_SET bit 0 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 8 PLL[0]: V6_AVDD_COMP_SET bit 1 PLL[0]: MMCM_DRP[74] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 10 PLL[0]: MMCM_DRP[74] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 12 PLL[0]: MMCM_DRP[74] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[74] bit 14 PLL[0]: MMCM_DRP[74] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 0 PLL[0]: MMCM_DRP[75] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 2 PLL[0]: MMCM_DRP[75] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 4 PLL[0]: MMCM_DRP[75] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 6 PLL[0]: MMCM_DRP[75] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 8 PLL[0]: MMCM_DRP[75] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 10 PLL[0]: MMCM_DRP[75] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 12 PLL[0]: MMCM_DRP[75] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[75] bit 14 PLL[0]: MMCM_DRP[75] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 0 PLL[0]: MMCM_DRP[76] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 2 PLL[0]: MMCM_DRP[76] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 4 PLL[0]: MMCM_DRP[76] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 6 PLL[0]: MMCM_DRP[76] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 8 PLL[0]: MMCM_DRP[76] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 10 PLL[0]: MMCM_DRP[76] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 12 PLL[0]: MMCM_DRP[76] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[76] bit 14 PLL[0]: MMCM_DRP[76] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 0 PLL[0]: MMCM_DRP[77] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 2 PLL[0]: MMCM_DRP[77] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 4 PLL[0]: MMCM_DRP[77] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 6 PLL[0]: MMCM_DRP[77] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 8 PLL[0]: MMCM_DRP[77] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 10 PLL[0]: MMCM_DRP[77] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 12 PLL[0]: MMCM_DRP[77] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[77] bit 14 PLL[0]: MMCM_DRP[77] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 0 PLL[0]: MMCM_DRP[78] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 2 PLL[0]: MMCM_DRP[78] bit 3 PLL[0]: CP_RES bit 0 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 4 PLL[0]: CP_RES bit 1 PLL[0]: MMCM_DRP[78] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 6 PLL[0]: MMCM_DRP[78] bit 7 PLL[0]: CP_BIAS_TRIP_SET bit 0 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 8 PLL[0]: CP bit 0 PLL[0]: MMCM_DRP[78] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 10 PLL[0]: MMCM_DRP[78] bit 11 PLL[0]: CP bit 1 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 12 PLL[0]: CP bit 2 PLL[0]: MMCM_DRP[78] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[78] bit 14 PLL[0]: MMCM_DRP[78] bit 15 PLL[0]: CP bit 3 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 0 PLL[0]: MMCM_DRP[79] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 2 PLL[0]: MMCM_DRP[79] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 4 PLL[0]: LFHF bit 0 PLL[0]: MMCM_DRP[79] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 6 PLL[0]: MMCM_DRP[79] bit 7 PLL[0]: LFHF bit 1 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 8 PLL[0]: RES bit 0 PLL[0]: MMCM_DRP[79] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 10 PLL[0]: MMCM_DRP[79] bit 11 PLL[0]: RES bit 1 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 12 PLL[0]: RES bit 2 PLL[0]: MMCM_DRP[79] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[79] bit 14 PLL[0]: MMCM_DRP[79] bit 15 PLL[0]: RES bit 3 - - - - - - - - - -
virtex6 CMT rect MAIN[9]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 0 PLL[0]: MMCM_DRP[64] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 2 PLL[0]: MMCM_DRP[64] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 4 PLL[0]: MMCM_DRP[64] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 6 PLL[0]: MMCM_DRP[64] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 8 PLL[0]: MMCM_DRP[64] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 10 PLL[0]: MMCM_DRP[64] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 12 PLL[0]: MMCM_DRP[64] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[64] bit 14 PLL[0]: MMCM_DRP[64] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 0 PLL[0]: MMCM_DRP[65] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 2 PLL[0]: MMCM_DRP[65] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 4 PLL[0]: MMCM_DRP[65] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 6 PLL[0]: MMCM_DRP[65] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 8 PLL[0]: MMCM_DRP[65] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 10 PLL[0]: MMCM_DRP[65] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 12 PLL[0]: MMCM_DRP[65] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[65] bit 14 PLL[0]: MMCM_DRP[65] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 0 PLL[0]: MAN_LF bit 0 PLL[0]: MMCM_DRP[66] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 2 PLL[0]: MMCM_DRP[66] bit 3 PLL[0]: MAN_LF bit 1 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 4 PLL[0]: MAN_LF bit 2 PLL[0]: MMCM_DRP[66] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 6 PLL[0]: MMCM_DRP[66] bit 7 PLL[0]: VLF_HIGH_DIS_B - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 8 PLL[0]: LF_PEN bit 0 PLL[0]: MMCM_DRP[66] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 10 PLL[0]: MMCM_DRP[66] bit 11 PLL[0]: LF_PEN bit 1 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 12 PLL[0]: LF_NEN bit 0 PLL[0]: MMCM_DRP[66] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[66] bit 14 PLL[0]: MMCM_DRP[66] bit 15 PLL[0]: LF_NEN bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 0 PLL[0]: MMCM_DRP[67] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 2 PLL[0]: MMCM_DRP[67] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 4 PLL[0]: MMCM_DRP[67] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 6 PLL[0]: MMCM_DRP[67] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 8 PLL[0]: MMCM_DRP[67] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 10 PLL[0]: MMCM_DRP[67] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 12 PLL[0]: MMCM_DRP[67] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[67] bit 14 PLL[0]: MMCM_DRP[67] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 0 PLL[0]: MMCM_DRP[68] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 2 PLL[0]: MMCM_DRP[68] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 4 PLL[0]: MMCM_DRP[68] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 6 PLL[0]: MMCM_DRP[68] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 8 PLL[0]: MMCM_DRP[68] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 10 PLL[0]: MMCM_DRP[68] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 12 PLL[0]: MMCM_DRP[68] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[68] bit 14 PLL[0]: MMCM_DRP[68] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 0 PLL[0]: MMCM_DRP[69] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 2 PLL[0]: MMCM_DRP[69] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 4 PLL[0]: MMCM_DRP[69] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 6 PLL[0]: MMCM_DRP[69] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 8 PLL[0]: MMCM_DRP[69] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 10 PLL[0]: MMCM_DRP[69] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 12 PLL[0]: MMCM_DRP[69] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[69] bit 14 PLL[0]: MMCM_DRP[69] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 0 PLL[0]: VLF_HIGH_PWDN_B PLL[0]: MMCM_DRP[70] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 2 PLL[0]: MMCM_DRP[70] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 4 PLL[0]: MMCM_DRP[70] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 6 PLL[0]: MMCM_DRP[70] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 8 PLL[0]: MMCM_DRP[70] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 10 PLL[0]: MMCM_DRP[70] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 12 PLL[0]: MMCM_DRP[70] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[70] bit 14 PLL[0]: MMCM_DRP[70] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 0 PLL[0]: MMCM_DRP[71] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 2 PLL[0]: MMCM_DRP[71] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 4 PLL[0]: MMCM_DRP[71] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 6 PLL[0]: MMCM_DRP[71] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 8 PLL[0]: MMCM_DRP[71] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 10 PLL[0]: MMCM_DRP[71] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 12 PLL[0]: MMCM_DRP[71] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[71] bit 14 PLL[0]: MMCM_DRP[71] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[10]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 0 PLL[0]: MMCM_DRP[56] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 2 PLL[0]: MMCM_DRP[56] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 4 PLL[0]: MMCM_DRP[56] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 6 PLL[0]: MMCM_DRP[56] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 8 PLL[0]: MMCM_DRP[56] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 10 PLL[0]: MMCM_DRP[56] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 12 PLL[0]: MMCM_DRP[56] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[56] bit 14 PLL[0]: MMCM_DRP[56] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 0 PLL[0]: MMCM_DRP[57] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 2 PLL[0]: MMCM_DRP[57] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 4 PLL[0]: MMCM_DRP[57] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 6 PLL[0]: MMCM_DRP[57] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 8 PLL[0]: MMCM_DRP[57] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 10 PLL[0]: MMCM_DRP[57] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 12 PLL[0]: MMCM_DRP[57] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[57] bit 14 PLL[0]: MMCM_DRP[57] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 0 PLL[0]: MMCM_DRP[58] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 2 PLL[0]: MMCM_DRP[58] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 4 PLL[0]: MMCM_DRP[58] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 6 PLL[0]: MMCM_DRP[58] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 8 PLL[0]: MMCM_DRP[58] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 10 PLL[0]: MMCM_DRP[58] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 12 PLL[0]: MMCM_DRP[58] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[58] bit 14 PLL[0]: MMCM_DRP[58] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 0 PLL[0]: MMCM_DRP[59] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 2 PLL[0]: MMCM_DRP[59] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 4 PLL[0]: MMCM_DRP[59] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 6 PLL[0]: MMCM_DRP[59] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 8 PLL[0]: MMCM_DRP[59] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 10 PLL[0]: MMCM_DRP[59] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 12 PLL[0]: MMCM_DRP[59] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[59] bit 14 PLL[0]: MMCM_DRP[59] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 0 PLL[0]: MMCM_DRP[60] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 2 PLL[0]: MMCM_DRP[60] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 4 PLL[0]: MMCM_DRP[60] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 6 PLL[0]: MMCM_DRP[60] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 8 PLL[0]: MMCM_DRP[60] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 10 PLL[0]: MMCM_DRP[60] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 12 PLL[0]: MMCM_DRP[60] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[60] bit 14 PLL[0]: MMCM_DRP[60] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 0 PLL[0]: MMCM_DRP[61] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 2 PLL[0]: MMCM_DRP[61] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 4 PLL[0]: MMCM_DRP[61] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 6 PLL[0]: MMCM_DRP[61] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 8 PLL[0]: MMCM_DRP[61] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 10 PLL[0]: MMCM_DRP[61] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 12 PLL[0]: MMCM_DRP[61] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[61] bit 14 PLL[0]: MMCM_DRP[61] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 0 PLL[0]: MMCM_DRP[62] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 2 PLL[0]: MMCM_DRP[62] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 4 PLL[0]: MMCM_DRP[62] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 6 PLL[0]: MMCM_DRP[62] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 8 PLL[0]: MMCM_DRP[62] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 10 PLL[0]: MMCM_DRP[62] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 12 PLL[0]: MMCM_DRP[62] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[62] bit 14 PLL[0]: MMCM_DRP[62] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 0 PLL[0]: MMCM_DRP[63] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 2 PLL[0]: MMCM_DRP[63] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 4 PLL[0]: MMCM_DRP[63] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 6 PLL[0]: MMCM_DRP[63] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 8 PLL[0]: MMCM_DRP[63] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 10 PLL[0]: MMCM_DRP[63] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 12 PLL[0]: MMCM_DRP[63] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[63] bit 14 PLL[0]: MMCM_DRP[63] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[11]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 0 PLL[0]: MMCM_DRP[48] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 2 PLL[0]: MMCM_DRP[48] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 4 PLL[0]: MMCM_DRP[48] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 6 PLL[0]: MMCM_DRP[48] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 8 PLL[0]: MMCM_DRP[48] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 10 PLL[0]: MMCM_DRP[48] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 12 PLL[0]: MMCM_DRP[48] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[48] bit 14 PLL[0]: MMCM_DRP[48] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 0 PLL[0]: MMCM_DRP[49] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 2 PLL[0]: MMCM_DRP[49] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 4 PLL[0]: MMCM_DRP[49] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 6 PLL[0]: MMCM_DRP[49] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 8 PLL[0]: MMCM_DRP[49] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 10 PLL[0]: MMCM_DRP[49] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 12 PLL[0]: MMCM_DRP[49] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[49] bit 14 PLL[0]: MMCM_DRP[49] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 0 PLL[0]: MMCM_DRP[50] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 2 PLL[0]: MMCM_DRP[50] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 4 PLL[0]: MMCM_DRP[50] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 6 PLL[0]: MMCM_DRP[50] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 8 PLL[0]: MMCM_DRP[50] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 10 PLL[0]: MMCM_DRP[50] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 12 PLL[0]: MMCM_DRP[50] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[50] bit 14 PLL[0]: MMCM_DRP[50] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 0 PLL[0]: MMCM_DRP[51] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 2 PLL[0]: MMCM_DRP[51] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 4 PLL[0]: MMCM_DRP[51] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 6 PLL[0]: MMCM_DRP[51] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 8 PLL[0]: MMCM_DRP[51] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 10 PLL[0]: MMCM_DRP[51] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 12 PLL[0]: MMCM_DRP[51] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[51] bit 14 PLL[0]: MMCM_DRP[51] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 0 PLL[0]: MMCM_DRP[52] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 2 PLL[0]: MMCM_DRP[52] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 4 PLL[0]: MMCM_DRP[52] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 6 PLL[0]: MMCM_DRP[52] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 8 PLL[0]: MMCM_DRP[52] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 10 PLL[0]: MMCM_DRP[52] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 12 PLL[0]: MMCM_DRP[52] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[52] bit 14 PLL[0]: MMCM_DRP[52] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 0 PLL[0]: MMCM_DRP[53] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 2 PLL[0]: MMCM_DRP[53] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 4 PLL[0]: MMCM_DRP[53] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 6 PLL[0]: MMCM_DRP[53] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 8 PLL[0]: MMCM_DRP[53] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 10 PLL[0]: MMCM_DRP[53] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 12 PLL[0]: MMCM_DRP[53] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[53] bit 14 PLL[0]: MMCM_DRP[53] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 0 PLL[0]: MMCM_DRP[54] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 2 PLL[0]: MMCM_DRP[54] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 4 PLL[0]: MMCM_DRP[54] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 6 PLL[0]: MMCM_DRP[54] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 8 PLL[0]: MMCM_DRP[54] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 10 PLL[0]: MMCM_DRP[54] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 12 PLL[0]: MMCM_DRP[54] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[54] bit 14 PLL[0]: MMCM_DRP[54] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 0 PLL[0]: MMCM_DRP[55] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 2 PLL[0]: MMCM_DRP[55] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 4 PLL[0]: MMCM_DRP[55] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 6 PLL[0]: MMCM_DRP[55] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 8 PLL[0]: MMCM_DRP[55] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 10 PLL[0]: MMCM_DRP[55] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 12 PLL[0]: MMCM_DRP[55] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[55] bit 14 PLL[0]: MMCM_DRP[55] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[12]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 0 PLL[0]: INTERP_EN bit 0 PLL[0]: MMCM_DRP[40] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 2 PLL[0]: MMCM_DRP[40] bit 3 PLL[0]: INTERP_EN bit 1 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 4 PLL[0]: INTERP_EN bit 2 PLL[0]: MMCM_DRP[40] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 6 PLL[0]: MMCM_DRP[40] bit 7 PLL[0]: INTERP_EN bit 3 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 8 PLL[0]: INTERP_EN bit 4 PLL[0]: MMCM_DRP[40] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 10 PLL[0]: MMCM_DRP[40] bit 11 PLL[0]: INTERP_EN bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 12 PLL[0]: INTERP_EN bit 6 PLL[0]: MMCM_DRP[40] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[40] bit 14 PLL[0]: MMCM_DRP[40] bit 15 PLL[0]: INTERP_EN bit 7 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 0 PLL[0]: MMCM_DRP[41] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 2 PLL[0]: MMCM_DRP[41] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 4 PLL[0]: MMCM_DRP[41] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 6 PLL[0]: MMCM_DRP[41] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 8 PLL[0]: MMCM_DRP[41] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 10 PLL[0]: MMCM_DRP[41] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 12 PLL[0]: MMCM_DRP[41] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[41] bit 14 PLL[0]: MMCM_DRP[41] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 0 PLL[0]: MMCM_DRP[42] bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 2 PLL[0]: MMCM_DRP[42] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 4 PLL[0]: MMCM_DRP[42] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 6 PLL[0]: MMCM_DRP[42] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 8 PLL[0]: MMCM_DRP[42] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 10 PLL[0]: MMCM_DRP[42] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 12 PLL[0]: MMCM_DRP[42] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[42] bit 14 PLL[0]: MMCM_DRP[42] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 0 PLL[0]: MMCM_DRP[43] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 2 PLL[0]: MMCM_DRP[43] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 4 PLL[0]: MMCM_DRP[43] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 6 PLL[0]: MMCM_DRP[43] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 8 PLL[0]: MMCM_DRP[43] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 10 PLL[0]: MMCM_DRP[43] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 12 PLL[0]: MMCM_DRP[43] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[43] bit 14 PLL[0]: MMCM_DRP[43] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 0 PLL[0]: MMCM_DRP[44] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 2 PLL[0]: MMCM_DRP[44] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 4 PLL[0]: MMCM_DRP[44] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 6 PLL[0]: MMCM_DRP[44] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 8 PLL[0]: MMCM_DRP[44] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 10 PLL[0]: MMCM_DRP[44] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 12 PLL[0]: MMCM_DRP[44] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[44] bit 14 PLL[0]: MMCM_DRP[44] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 0 PLL[0]: MMCM_DRP[45] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 2 PLL[0]: MMCM_DRP[45] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 4 PLL[0]: MMCM_DRP[45] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 6 PLL[0]: MMCM_DRP[45] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 8 PLL[0]: MMCM_DRP[45] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 10 PLL[0]: MMCM_DRP[45] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 12 PLL[0]: MMCM_DRP[45] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[45] bit 14 PLL[0]: MMCM_DRP[45] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 0 PLL[0]: MMCM_DRP[46] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 2 PLL[0]: MMCM_DRP[46] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 4 PLL[0]: MMCM_DRP[46] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 6 PLL[0]: MMCM_DRP[46] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 8 PLL[0]: MMCM_DRP[46] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 10 PLL[0]: MMCM_DRP[46] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 12 PLL[0]: MMCM_DRP[46] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[46] bit 14 PLL[0]: MMCM_DRP[46] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 0 PLL[0]: MMCM_DRP[47] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 2 PLL[0]: MMCM_DRP[47] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 4 PLL[0]: MMCM_DRP[47] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 6 PLL[0]: MMCM_DRP[47] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 8 PLL[0]: MMCM_DRP[47] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 10 PLL[0]: MMCM_DRP[47] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 12 PLL[0]: MMCM_DRP[47] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[47] bit 14 PLL[0]: MMCM_DRP[47] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[13]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 0 PLL[0]: MMCM_DRP[32] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 2 PLL[0]: MMCM_DRP[32] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 4 PLL[0]: MMCM_DRP[32] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 6 PLL[0]: MMCM_DRP[32] bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 8 PLL[0]: MMCM_DRP[32] bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 10 PLL[0]: MMCM_DRP[32] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 12 PLL[0]: MMCM_DRP[32] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[32] bit 14 PLL[0]: MMCM_DRP[32] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 0 PLL[0]: MMCM_DRP[33] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 2 PLL[0]: MMCM_DRP[33] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 4 PLL[0]: MMCM_DRP[33] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 6 PLL[0]: MMCM_DRP[33] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 8 PLL[0]: MMCM_DRP[33] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 10 PLL[0]: MMCM_DRP[33] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 12 PLL[0]: MMCM_DRP[33] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[33] bit 14 PLL[0]: MMCM_DRP[33] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 0 PLL[0]: EN_VCO_DIV6 PLL[0]: MMCM_DRP[34] bit 1 PLL[0]: EN_VCO_DIV1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 2 PLL[0]: MMCM_DRP[34] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 4 PLL[0]: MMCM_DRP[34] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 6 PLL[0]: MMCM_DRP[34] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 8 PLL[0]: MMCM_DRP[34] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 10 PLL[0]: MMCM_DRP[34] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 12 PLL[0]: MMCM_DRP[34] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[34] bit 14 PLL[0]: MMCM_DRP[34] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 0 PLL[0]: MMCM_DRP[35] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 2 PLL[0]: MMCM_DRP[35] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 4 PLL[0]: MMCM_DRP[35] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 6 PLL[0]: MMCM_DRP[35] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 8 PLL[0]: MMCM_DRP[35] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 10 PLL[0]: MMCM_DRP[35] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 12 PLL[0]: MMCM_DRP[35] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[35] bit 14 PLL[0]: MMCM_DRP[35] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 0 PLL[0]: MMCM_DRP[36] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 2 PLL[0]: MMCM_DRP[36] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 4 PLL[0]: MMCM_DRP[36] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 6 PLL[0]: MMCM_DRP[36] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 8 PLL[0]: MMCM_DRP[36] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 10 PLL[0]: MMCM_DRP[36] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 12 PLL[0]: MMCM_DRP[36] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[36] bit 14 PLL[0]: MMCM_DRP[36] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 0 PLL[0]: MMCM_DRP[37] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 2 PLL[0]: MMCM_DRP[37] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 4 PLL[0]: MMCM_DRP[37] bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 6 PLL[0]: MMCM_DRP[37] bit 7 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 8 PLL[0]: MMCM_DRP[37] bit 9 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 10 PLL[0]: MMCM_DRP[37] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 12 PLL[0]: MMCM_DRP[37] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[37] bit 14 PLL[0]: MMCM_DRP[37] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 0 PLL[0]: MMCM_DRP[38] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 2 PLL[0]: MMCM_DRP[38] bit 3 PLL[0]: ANALOG_MISC bit 0 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 4 PLL[0]: ANALOG_MISC bit 1 PLL[0]: MMCM_DRP[38] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 6 PLL[0]: MMCM_DRP[38] bit 7 PLL[0]: ANALOG_MISC bit 2 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 8 PLL[0]: ANALOG_MISC bit 3 PLL[0]: MMCM_DRP[38] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 10 PLL[0]: MMCM_DRP[38] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 12 PLL[0]: MMCM_DRP[38] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[38] bit 14 PLL[0]: MMCM_DRP[38] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 0 PLL[0]: MMCM_DRP[39] bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 2 PLL[0]: MMCM_DRP[39] bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 4 PLL[0]: MMCM_DRP[39] bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 6 PLL[0]: MMCM_DRP[39] bit 7 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 8 PLL[0]: MMCM_DRP[39] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 10 PLL[0]: MMCM_DRP[39] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 12 PLL[0]: MMCM_DRP[39] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[39] bit 14 PLL[0]: MMCM_DRP[39] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[14]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 0 PLL[0]: LOCK_CNT bit 0 PLL[0]: MMCM_DRP[24] bit 1 PLL[0]: LOCK_CNT bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 2 PLL[0]: LOCK_CNT bit 2 PLL[0]: MMCM_DRP[24] bit 3 PLL[0]: LOCK_CNT bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 4 PLL[0]: LOCK_CNT bit 4 PLL[0]: MMCM_DRP[24] bit 5 PLL[0]: LOCK_CNT bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 6 PLL[0]: LOCK_CNT bit 6 PLL[0]: MMCM_DRP[24] bit 7 PLL[0]: LOCK_CNT bit 7 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 8 PLL[0]: LOCK_CNT bit 8 PLL[0]: MMCM_DRP[24] bit 9 PLL[0]: LOCK_CNT bit 9 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 10 PLL[0]: MMCM_DRP[24] bit 11 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 12 PLL[0]: MMCM_DRP[24] bit 13 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[24] bit 14 PLL[0]: MMCM_DRP[24] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 0 PLL[0]: UNLOCK_CNT bit 0 PLL[0]: MMCM_DRP[25] bit 1 PLL[0]: UNLOCK_CNT bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 2 PLL[0]: UNLOCK_CNT bit 2 PLL[0]: MMCM_DRP[25] bit 3 PLL[0]: UNLOCK_CNT bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 4 PLL[0]: UNLOCK_CNT bit 4 PLL[0]: MMCM_DRP[25] bit 5 PLL[0]: UNLOCK_CNT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 6 PLL[0]: UNLOCK_CNT bit 6 PLL[0]: MMCM_DRP[25] bit 7 PLL[0]: UNLOCK_CNT bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 8 PLL[0]: UNLOCK_CNT bit 8 PLL[0]: MMCM_DRP[25] bit 9 PLL[0]: UNLOCK_CNT bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 10 PLL[0]: LOCK_FB_DLY bit 0 PLL[0]: MMCM_DRP[25] bit 11 PLL[0]: LOCK_FB_DLY bit 1 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 12 PLL[0]: LOCK_FB_DLY bit 2 PLL[0]: MMCM_DRP[25] bit 13 PLL[0]: LOCK_FB_DLY bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[25] bit 14 PLL[0]: LOCK_FB_DLY bit 4 PLL[0]: MMCM_DRP[25] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 0 PLL[0]: LOCK_SAT_HIGH bit 0 PLL[0]: MMCM_DRP[26] bit 1 PLL[0]: LOCK_SAT_HIGH bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 2 PLL[0]: LOCK_SAT_HIGH bit 2 PLL[0]: MMCM_DRP[26] bit 3 PLL[0]: LOCK_SAT_HIGH bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 4 PLL[0]: LOCK_SAT_HIGH bit 4 PLL[0]: MMCM_DRP[26] bit 5 PLL[0]: LOCK_SAT_HIGH bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 6 PLL[0]: LOCK_SAT_HIGH bit 6 PLL[0]: MMCM_DRP[26] bit 7 PLL[0]: LOCK_SAT_HIGH bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 8 PLL[0]: LOCK_SAT_HIGH bit 8 PLL[0]: MMCM_DRP[26] bit 9 PLL[0]: LOCK_SAT_HIGH bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 10 PLL[0]: LOCK_REF_DLY bit 0 PLL[0]: MMCM_DRP[26] bit 11 PLL[0]: LOCK_REF_DLY bit 1 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 12 PLL[0]: LOCK_REF_DLY bit 2 PLL[0]: MMCM_DRP[26] bit 13 PLL[0]: LOCK_REF_DLY bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[26] bit 14 PLL[0]: LOCK_REF_DLY bit 4 PLL[0]: MMCM_DRP[26] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 0 PLL[0]: HVLF_CNT_TEST bit 0 PLL[0]: MMCM_DRP[27] bit 1 PLL[0]: HVLF_CNT_TEST bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 2 PLL[0]: HVLF_CNT_TEST bit 2 PLL[0]: MMCM_DRP[27] bit 3 PLL[0]: HVLF_CNT_TEST bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 4 PLL[0]: HVLF_CNT_TEST bit 4 PLL[0]: MMCM_DRP[27] bit 5 PLL[0]: HVLF_CNT_TEST bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 6 PLL[0]: HVLF_STEP PLL[0]: MMCM_DRP[27] bit 7 PLL[0]: HVLF_CNT_TEST_EN - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 8 PLL[0]: MMCM_DRP[27] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 10 PLL[0]: MMCM_DRP[27] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 12 PLL[0]: MMCM_DRP[27] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[27] bit 14 PLL[0]: MMCM_DRP[27] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 0 PLL[0]: MMCM_DRP[28] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 2 PLL[0]: MMCM_DRP[28] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 4 PLL[0]: MMCM_DRP[28] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 6 PLL[0]: MMCM_DRP[28] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 8 PLL[0]: MMCM_DRP[28] bit 9 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 10 PLL[0]: MMCM_DRP[28] bit 11 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 12 PLL[0]: MMCM_DRP[28] bit 13 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[28] bit 14 PLL[0]: MMCM_DRP[28] bit 15 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 0 PLL[0]: MMCM_DRP[29] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 2 PLL[0]: MMCM_DRP[29] bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 4 PLL[0]: PFD bit 0 PLL[0]: MMCM_DRP[29] bit 5 PLL[0]: PFD bit 1 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 6 PLL[0]: PFD bit 2 PLL[0]: MMCM_DRP[29] bit 7 PLL[0]: PFD bit 3 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 8 PLL[0]: PFD bit 4 PLL[0]: MMCM_DRP[29] bit 9 PLL[0]: PFD bit 5 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 10 PLL[0]: PFD bit 6 PLL[0]: MMCM_DRP[29] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 12 PLL[0]: MMCM_DRP[29] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[29] bit 14 PLL[0]: MMCM_DRP[29] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 0 PLL[0]: MMCM_DRP[30] bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 2 PLL[0]: MMCM_DRP[30] bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 4 PLL[0]: MMCM_DRP[30] bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 6 PLL[0]: MMCM_DRP[30] bit 7 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 8 PLL[0]: MMCM_DRP[30] bit 9 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 10 PLL[0]: MMCM_DRP[30] bit 11 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 12 PLL[0]: MMCM_DRP[30] bit 13 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[30] bit 14 PLL[0]: MMCM_DRP[30] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 0 PLL[0]: DVDD_VBG_SEL bit 0 PLL[0]: MMCM_DRP[31] bit 1 PLL[0]: DVDD_VBG_SEL bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 2 PLL[0]: DVDD_VBG_SEL bit 2 PLL[0]: MMCM_DRP[31] bit 3 PLL[0]: DVDD_VBG_SEL bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 4 PLL[0]: DVDD_VBG_PD bit 0 PLL[0]: MMCM_DRP[31] bit 5 PLL[0]: DVDD_VBG_PD bit 1 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 6 PLL[0]: DVDD_VBG_PD bit 2 PLL[0]: MMCM_DRP[31] bit 7 PLL[0]: V6_DVDD_COMP_SET bit 0 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 8 PLL[0]: V6_DVDD_COMP_SET bit 1 PLL[0]: MMCM_DRP[31] bit 9 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 10 PLL[0]: MMCM_DRP[31] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 12 PLL[0]: MMCM_DRP[31] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[31] bit 14 PLL[0]: MMCM_DRP[31] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[15]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 0 PLL[0]: CLKOUT4_LT bit 0 PLL[0]: MMCM_DRP[16] bit 1 PLL[0]: CLKOUT4_LT bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 2 PLL[0]: CLKOUT4_LT bit 2 PLL[0]: MMCM_DRP[16] bit 3 PLL[0]: CLKOUT4_LT bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 4 PLL[0]: CLKOUT4_LT bit 4 PLL[0]: MMCM_DRP[16] bit 5 PLL[0]: CLKOUT4_LT bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 6 PLL[0]: CLKOUT4_HT bit 0 PLL[0]: MMCM_DRP[16] bit 7 PLL[0]: CLKOUT4_HT bit 1 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 8 PLL[0]: CLKOUT4_HT bit 2 PLL[0]: MMCM_DRP[16] bit 9 PLL[0]: CLKOUT4_HT bit 3 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 10 PLL[0]: CLKOUT4_HT bit 4 PLL[0]: MMCM_DRP[16] bit 11 PLL[0]: CLKOUT4_HT bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 12 PLL[0]: CLKOUT4_EN PLL[0]: MMCM_DRP[16] bit 13 PLL[0]: CLKOUT4_PM bit 0 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[16] bit 14 PLL[0]: CLKOUT4_PM bit 1 PLL[0]: MMCM_DRP[16] bit 15 PLL[0]: CLKOUT4_PM bit 2 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 0 PLL[0]: CLKOUT4_DT bit 0 PLL[0]: MMCM_DRP[17] bit 1 PLL[0]: CLKOUT4_DT bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 2 PLL[0]: CLKOUT4_DT bit 2 PLL[0]: MMCM_DRP[17] bit 3 PLL[0]: CLKOUT4_DT bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 4 PLL[0]: CLKOUT4_DT bit 4 PLL[0]: MMCM_DRP[17] bit 5 PLL[0]: CLKOUT4_DT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 6 PLL[0]: CLKOUT4_NOCOUNT PLL[0]: MMCM_DRP[17] bit 7 PLL[0]: CLKOUT4_EDGE - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 8 PLL[0]: CLKOUT4_MX bit 0 PLL[0]: CLKOUT4_USE_FINE_PS PLL[0]: MMCM_DRP[17] bit 9 PLL[0]: CLKOUT4_MX bit 1 PLL[0]: CLKOUT4_CASCADE - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 10 PLL[0]: MMCM_DRP[17] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 12 PLL[0]: MMCM_DRP[17] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[17] bit 14 PLL[0]: MMCM_DRP[17] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 0 PLL[0]: CLKOUT6_LT bit 0 PLL[0]: MMCM_DRP[18] bit 1 PLL[0]: CLKOUT6_LT bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 2 PLL[0]: CLKOUT6_LT bit 2 PLL[0]: MMCM_DRP[18] bit 3 PLL[0]: CLKOUT6_LT bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 4 PLL[0]: CLKOUT6_LT bit 4 PLL[0]: MMCM_DRP[18] bit 5 PLL[0]: CLKOUT6_LT bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 6 PLL[0]: CLKOUT6_HT bit 0 PLL[0]: MMCM_DRP[18] bit 7 PLL[0]: CLKOUT6_HT bit 1 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 8 PLL[0]: CLKOUT6_HT bit 2 PLL[0]: MMCM_DRP[18] bit 9 PLL[0]: CLKOUT6_HT bit 3 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 10 PLL[0]: CLKOUT6_HT bit 4 PLL[0]: MMCM_DRP[18] bit 11 PLL[0]: CLKOUT6_HT bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 12 PLL[0]: CLKOUT6_EN PLL[0]: MMCM_DRP[18] bit 13 PLL[0]: CLKOUT6_PM bit 0 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[18] bit 14 PLL[0]: CLKOUT6_PM bit 1 PLL[0]: MMCM_DRP[18] bit 15 PLL[0]: CLKOUT6_PM bit 2 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 0 PLL[0]: CLKOUT6_DT bit 0 PLL[0]: MMCM_DRP[19] bit 1 PLL[0]: CLKOUT6_DT bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 2 PLL[0]: CLKOUT6_DT bit 2 PLL[0]: MMCM_DRP[19] bit 3 PLL[0]: CLKOUT6_DT bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 4 PLL[0]: CLKOUT6_DT bit 4 PLL[0]: MMCM_DRP[19] bit 5 PLL[0]: CLKOUT6_DT bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 6 PLL[0]: CLKOUT6_NOCOUNT PLL[0]: MMCM_DRP[19] bit 7 PLL[0]: CLKOUT6_EDGE - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 8 PLL[0]: CLKOUT6_MX bit 0 PLL[0]: CLKOUT6_USE_FINE_PS PLL[0]: MMCM_DRP[19] bit 9 PLL[0]: CLKOUT6_MX bit 1 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 10 PLL[0]: CLKOUT6_FRAC_WF PLL[0]: MMCM_DRP[19] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 12 PLL[0]: MMCM_DRP[19] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[19] bit 14 PLL[0]: MMCM_DRP[19] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 0 PLL[0]: CLKFBOUT_LT bit 0 PLL[0]: MMCM_DRP[20] bit 1 PLL[0]: CLKFBOUT_LT bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 2 PLL[0]: CLKFBOUT_LT bit 2 PLL[0]: MMCM_DRP[20] bit 3 PLL[0]: CLKFBOUT_LT bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 4 PLL[0]: CLKFBOUT_LT bit 4 PLL[0]: MMCM_DRP[20] bit 5 PLL[0]: CLKFBOUT_LT bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 6 PLL[0]: CLKFBOUT_HT bit 0 PLL[0]: MMCM_DRP[20] bit 7 PLL[0]: CLKFBOUT_HT bit 1 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 8 PLL[0]: CLKFBOUT_HT bit 2 PLL[0]: MMCM_DRP[20] bit 9 PLL[0]: CLKFBOUT_HT bit 3 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 10 PLL[0]: CLKFBOUT_HT bit 4 PLL[0]: MMCM_DRP[20] bit 11 PLL[0]: CLKFBOUT_HT bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 12 PLL[0]: CLKFBOUT_EN PLL[0]: MMCM_DRP[20] bit 13 PLL[0]: CLKFBOUT_PM bit 0 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[20] bit 14 PLL[0]: CLKFBOUT_PM bit 1 PLL[0]: MMCM_DRP[20] bit 15 PLL[0]: CLKFBOUT_PM bit 2 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 0 PLL[0]: CLKFBOUT_DT bit 0 PLL[0]: MMCM_DRP[21] bit 1 PLL[0]: CLKFBOUT_DT bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 2 PLL[0]: CLKFBOUT_DT bit 2 PLL[0]: MMCM_DRP[21] bit 3 PLL[0]: CLKFBOUT_DT bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 4 PLL[0]: CLKFBOUT_DT bit 4 PLL[0]: MMCM_DRP[21] bit 5 PLL[0]: CLKFBOUT_DT bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 6 PLL[0]: CLKFBOUT_NOCOUNT PLL[0]: MMCM_DRP[21] bit 7 PLL[0]: CLKFBOUT_EDGE - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 8 PLL[0]: CLKFBOUT_MX bit 0 PLL[0]: CLKFBOUT_USE_FINE_PS PLL[0]: MMCM_DRP[21] bit 9 PLL[0]: CLKFBOUT_MX bit 1 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 10 PLL[0]: CLKFBOUT_FRAC_WF PLL[0]: MMCM_DRP[21] bit 11 PLL[0]: CLKFBOUT_FRAC_EN - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 12 PLL[0]: CLKFBOUT_FRAC bit 0 PLL[0]: MMCM_DRP[21] bit 13 PLL[0]: CLKFBOUT_FRAC bit 1 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[21] bit 14 PLL[0]: CLKFBOUT_FRAC bit 2 PLL[0]: MMCM_DRP[21] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 0 PLL[0]: DIVCLK_LT bit 0 PLL[0]: MMCM_DRP[22] bit 1 PLL[0]: DIVCLK_LT bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 2 PLL[0]: DIVCLK_LT bit 2 PLL[0]: MMCM_DRP[22] bit 3 PLL[0]: DIVCLK_LT bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 4 PLL[0]: DIVCLK_LT bit 4 PLL[0]: MMCM_DRP[22] bit 5 PLL[0]: DIVCLK_LT bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 6 PLL[0]: DIVCLK_HT bit 0 PLL[0]: MMCM_DRP[22] bit 7 PLL[0]: DIVCLK_HT bit 1 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 8 PLL[0]: DIVCLK_HT bit 2 PLL[0]: MMCM_DRP[22] bit 9 PLL[0]: DIVCLK_HT bit 3 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 10 PLL[0]: DIVCLK_HT bit 4 PLL[0]: MMCM_DRP[22] bit 11 PLL[0]: DIVCLK_HT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 12 PLL[0]: DIVCLK_NOCOUNT PLL[0]: MMCM_DRP[22] bit 13 PLL[0]: DIVCLK_EDGE - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[22] bit 14 PLL[0]: MMCM_DRP[22] bit 15 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 0 PLL[0]: CLKFBIN_LT bit 0 PLL[0]: MMCM_DRP[23] bit 1 PLL[0]: CLKFBIN_LT bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 2 PLL[0]: CLKFBIN_LT bit 2 PLL[0]: MMCM_DRP[23] bit 3 PLL[0]: CLKFBIN_LT bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 4 PLL[0]: CLKFBIN_LT bit 4 PLL[0]: MMCM_DRP[23] bit 5 PLL[0]: CLKFBIN_LT bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 6 PLL[0]: CLKFBIN_HT bit 0 PLL[0]: MMCM_DRP[23] bit 7 PLL[0]: CLKFBIN_HT bit 1 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 8 PLL[0]: CLKFBIN_HT bit 2 PLL[0]: MMCM_DRP[23] bit 9 PLL[0]: CLKFBIN_HT bit 3 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 10 PLL[0]: CLKFBIN_HT bit 4 PLL[0]: MMCM_DRP[23] bit 11 PLL[0]: CLKFBIN_HT bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 12 PLL[0]: CLKFBIN_NOCOUNT PLL[0]: MMCM_DRP[23] bit 13 PLL[0]: CLKFBIN_EDGE - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[23] bit 14 PLL[0]: MMCM_DRP[23] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[16]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 0 PLL[0]: CLKOUT0_LT bit 0 PLL[0]: MMCM_DRP[8] bit 1 PLL[0]: CLKOUT0_LT bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 2 PLL[0]: CLKOUT0_LT bit 2 PLL[0]: MMCM_DRP[8] bit 3 PLL[0]: CLKOUT0_LT bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 4 PLL[0]: CLKOUT0_LT bit 4 PLL[0]: MMCM_DRP[8] bit 5 PLL[0]: CLKOUT0_LT bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 6 PLL[0]: CLKOUT0_HT bit 0 PLL[0]: MMCM_DRP[8] bit 7 PLL[0]: CLKOUT0_HT bit 1 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 8 PLL[0]: CLKOUT0_HT bit 2 PLL[0]: MMCM_DRP[8] bit 9 PLL[0]: CLKOUT0_HT bit 3 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 10 PLL[0]: CLKOUT0_HT bit 4 PLL[0]: MMCM_DRP[8] bit 11 PLL[0]: CLKOUT0_HT bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 12 PLL[0]: CLKOUT0_EN PLL[0]: MMCM_DRP[8] bit 13 PLL[0]: CLKOUT0_PM bit 0 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[8] bit 14 PLL[0]: CLKOUT0_PM bit 1 PLL[0]: MMCM_DRP[8] bit 15 PLL[0]: CLKOUT0_PM bit 2 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 0 PLL[0]: CLKOUT0_DT bit 0 PLL[0]: MMCM_DRP[9] bit 1 PLL[0]: CLKOUT0_DT bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 2 PLL[0]: CLKOUT0_DT bit 2 PLL[0]: MMCM_DRP[9] bit 3 PLL[0]: CLKOUT0_DT bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 4 PLL[0]: CLKOUT0_DT bit 4 PLL[0]: MMCM_DRP[9] bit 5 PLL[0]: CLKOUT0_DT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 6 PLL[0]: CLKOUT0_NOCOUNT PLL[0]: MMCM_DRP[9] bit 7 PLL[0]: CLKOUT0_EDGE - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 8 PLL[0]: CLKOUT0_MX bit 0 PLL[0]: CLKOUT0_USE_FINE_PS PLL[0]: MMCM_DRP[9] bit 9 PLL[0]: CLKOUT0_MX bit 1 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 10 PLL[0]: CLKOUT0_FRAC_WF PLL[0]: MMCM_DRP[9] bit 11 PLL[0]: CLKOUT0_FRAC_EN - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 12 PLL[0]: CLKOUT0_FRAC bit 0 PLL[0]: MMCM_DRP[9] bit 13 PLL[0]: CLKOUT0_FRAC bit 1 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[9] bit 14 PLL[0]: CLKOUT0_FRAC bit 2 PLL[0]: MMCM_DRP[9] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 0 PLL[0]: CLKOUT1_LT bit 0 PLL[0]: MMCM_DRP[10] bit 1 PLL[0]: CLKOUT1_LT bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 2 PLL[0]: CLKOUT1_LT bit 2 PLL[0]: MMCM_DRP[10] bit 3 PLL[0]: CLKOUT1_LT bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 4 PLL[0]: CLKOUT1_LT bit 4 PLL[0]: MMCM_DRP[10] bit 5 PLL[0]: CLKOUT1_LT bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 6 PLL[0]: CLKOUT1_HT bit 0 PLL[0]: MMCM_DRP[10] bit 7 PLL[0]: CLKOUT1_HT bit 1 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 8 PLL[0]: CLKOUT1_HT bit 2 PLL[0]: MMCM_DRP[10] bit 9 PLL[0]: CLKOUT1_HT bit 3 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 10 PLL[0]: CLKOUT1_HT bit 4 PLL[0]: MMCM_DRP[10] bit 11 PLL[0]: CLKOUT1_HT bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 12 PLL[0]: CLKOUT1_EN PLL[0]: MMCM_DRP[10] bit 13 PLL[0]: CLKOUT1_PM bit 0 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[10] bit 14 PLL[0]: CLKOUT1_PM bit 1 PLL[0]: MMCM_DRP[10] bit 15 PLL[0]: CLKOUT1_PM bit 2 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 0 PLL[0]: CLKOUT1_DT bit 0 PLL[0]: MMCM_DRP[11] bit 1 PLL[0]: CLKOUT1_DT bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 2 PLL[0]: CLKOUT1_DT bit 2 PLL[0]: MMCM_DRP[11] bit 3 PLL[0]: CLKOUT1_DT bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 4 PLL[0]: CLKOUT1_DT bit 4 PLL[0]: MMCM_DRP[11] bit 5 PLL[0]: CLKOUT1_DT bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 6 PLL[0]: CLKOUT1_NOCOUNT PLL[0]: MMCM_DRP[11] bit 7 PLL[0]: CLKOUT1_EDGE - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 8 PLL[0]: CLKOUT1_MX bit 0 PLL[0]: CLKOUT1_USE_FINE_PS PLL[0]: MMCM_DRP[11] bit 9 PLL[0]: CLKOUT1_MX bit 1 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 10 PLL[0]: MMCM_DRP[11] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 12 PLL[0]: MMCM_DRP[11] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[11] bit 14 PLL[0]: MMCM_DRP[11] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 0 PLL[0]: CLKOUT2_LT bit 0 PLL[0]: MMCM_DRP[12] bit 1 PLL[0]: CLKOUT2_LT bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 2 PLL[0]: CLKOUT2_LT bit 2 PLL[0]: MMCM_DRP[12] bit 3 PLL[0]: CLKOUT2_LT bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 4 PLL[0]: CLKOUT2_LT bit 4 PLL[0]: MMCM_DRP[12] bit 5 PLL[0]: CLKOUT2_LT bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 6 PLL[0]: CLKOUT2_HT bit 0 PLL[0]: MMCM_DRP[12] bit 7 PLL[0]: CLKOUT2_HT bit 1 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 8 PLL[0]: CLKOUT2_HT bit 2 PLL[0]: MMCM_DRP[12] bit 9 PLL[0]: CLKOUT2_HT bit 3 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 10 PLL[0]: CLKOUT2_HT bit 4 PLL[0]: MMCM_DRP[12] bit 11 PLL[0]: CLKOUT2_HT bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 12 PLL[0]: CLKOUT2_EN PLL[0]: MMCM_DRP[12] bit 13 PLL[0]: CLKOUT2_PM bit 0 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[12] bit 14 PLL[0]: CLKOUT2_PM bit 1 PLL[0]: MMCM_DRP[12] bit 15 PLL[0]: CLKOUT2_PM bit 2 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 0 PLL[0]: CLKOUT2_DT bit 0 PLL[0]: MMCM_DRP[13] bit 1 PLL[0]: CLKOUT2_DT bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 2 PLL[0]: CLKOUT2_DT bit 2 PLL[0]: MMCM_DRP[13] bit 3 PLL[0]: CLKOUT2_DT bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 4 PLL[0]: CLKOUT2_DT bit 4 PLL[0]: MMCM_DRP[13] bit 5 PLL[0]: CLKOUT2_DT bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 6 PLL[0]: CLKOUT2_NOCOUNT PLL[0]: MMCM_DRP[13] bit 7 PLL[0]: CLKOUT2_EDGE - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 8 PLL[0]: CLKOUT2_MX bit 0 PLL[0]: CLKOUT2_USE_FINE_PS PLL[0]: MMCM_DRP[13] bit 9 PLL[0]: CLKOUT2_MX bit 1 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 10 PLL[0]: MMCM_DRP[13] bit 11 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 12 PLL[0]: MMCM_DRP[13] bit 13 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[13] bit 14 PLL[0]: MMCM_DRP[13] bit 15 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 0 PLL[0]: CLKOUT3_LT bit 0 PLL[0]: MMCM_DRP[14] bit 1 PLL[0]: CLKOUT3_LT bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 2 PLL[0]: CLKOUT3_LT bit 2 PLL[0]: MMCM_DRP[14] bit 3 PLL[0]: CLKOUT3_LT bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 4 PLL[0]: CLKOUT3_LT bit 4 PLL[0]: MMCM_DRP[14] bit 5 PLL[0]: CLKOUT3_LT bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 6 PLL[0]: CLKOUT3_HT bit 0 PLL[0]: MMCM_DRP[14] bit 7 PLL[0]: CLKOUT3_HT bit 1 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 8 PLL[0]: CLKOUT3_HT bit 2 PLL[0]: MMCM_DRP[14] bit 9 PLL[0]: CLKOUT3_HT bit 3 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 10 PLL[0]: CLKOUT3_HT bit 4 PLL[0]: MMCM_DRP[14] bit 11 PLL[0]: CLKOUT3_HT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 12 PLL[0]: CLKOUT3_EN PLL[0]: MMCM_DRP[14] bit 13 PLL[0]: CLKOUT3_PM bit 0 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[14] bit 14 PLL[0]: CLKOUT3_PM bit 1 PLL[0]: MMCM_DRP[14] bit 15 PLL[0]: CLKOUT3_PM bit 2 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 0 PLL[0]: CLKOUT3_DT bit 0 PLL[0]: MMCM_DRP[15] bit 1 PLL[0]: CLKOUT3_DT bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 2 PLL[0]: CLKOUT3_DT bit 2 PLL[0]: MMCM_DRP[15] bit 3 PLL[0]: CLKOUT3_DT bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 4 PLL[0]: CLKOUT3_DT bit 4 PLL[0]: MMCM_DRP[15] bit 5 PLL[0]: CLKOUT3_DT bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 6 PLL[0]: CLKOUT3_NOCOUNT PLL[0]: MMCM_DRP[15] bit 7 PLL[0]: CLKOUT3_EDGE - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 8 PLL[0]: CLKOUT3_MX bit 0 PLL[0]: CLKOUT3_USE_FINE_PS PLL[0]: MMCM_DRP[15] bit 9 PLL[0]: CLKOUT3_MX bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 10 PLL[0]: MMCM_DRP[15] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 12 PLL[0]: MMCM_DRP[15] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[15] bit 14 PLL[0]: MMCM_DRP[15] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[17]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[0] bit 0 PLL[0]: MMCM_DRP[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[0] bit 1 PLL[0]: MMCM_DRP[0] bit 1 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[0] bit 0 PLL[0]: MMCM_DRP[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[0] bit 1 PLL[0]: MMCM_DRP[0] bit 3 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[0] bit 0 PLL[0]: MMCM_DRP[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[0] bit 1 PLL[0]: MMCM_DRP[0] bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 6 PLL[0]: IN_DLY_MX_CVDD bit 0 PLL[0]: MMCM_DRP[0] bit 7 PLL[0]: IN_DLY_MX_CVDD bit 1 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 8 PLL[0]: IN_DLY_MX_CVDD bit 2 PLL[0]: MMCM_DRP[0] bit 9 PLL[0]: IN_DLY_MX_CVDD bit 3 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 10 PLL[0]: IN_DLY_MX_CVDD bit 4 PLL[0]: MMCM_DRP[0] bit 11 PLL[0]: IN_DLY_MX_CVDD bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 12 PLL[0]: HROW_DLY_SET bit 0 PLL[0]: MMCM_DRP[0] bit 13 PLL[0]: HROW_DLY_SET bit 1 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[0] bit 14 PLL[0]: HROW_DLY_SET bit 2 PLL[0]: MMCM_DRP[0] bit 15 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: MMCM_DRP[1] bit 0 SPEC_INT: buffer IO_E[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: MMCM_DRP[1] bit 1 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: MMCM_DRP[1] bit 2 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_S[0] PLL[0]: MMCM_DRP[1] bit 3 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: MMCM_DRP[1] bit 4 SPEC_INT: buffer IO_E[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: MMCM_DRP[1] bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: MMCM_DRP[1] bit 6 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_S[1] PLL[0]: MMCM_DRP[1] bit 7 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: MMCM_DRP[1] bit 8 SPEC_INT: buffer IO_E[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: MMCM_DRP[1] bit 9 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: MMCM_DRP[1] bit 10 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_S[2] PLL[0]: MMCM_DRP[1] bit 11 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: MMCM_DRP[1] bit 12 SPEC_INT: buffer IO_E[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: MMCM_DRP[1] bit 13 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: MMCM_DRP[1] bit 14 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_S[3] PLL[0]: MMCM_DRP[1] bit 15 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 0 PLL[0]: SYNTH_CLK_DIV bit 0 PLL[0]: MMCM_DRP[2] bit 1 PLL[0]: SYNTH_CLK_DIV bit 1 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 2 PLL[0]: MMCM_DRP[2] bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 4 PLL[0]: MMCM_DRP[2] bit 5 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 6 PLL[0]: MMCM_DRP[2] bit 7 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 8 PLL[0]: MMCM_DRP[2] bit 9 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 10 PLL[0]: MMCM_DRP[2] bit 11 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 12 PLL[0]: MMCM_DRP[2] bit 13 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[2] bit 14 PLL[0]: MMCM_DRP[2] bit 15 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 0 PLL[0]: MMCM_DRP[3] bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 2 PLL[0]: MMCM_DRP[3] bit 3 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 4 PLL[0]: MMCM_DRP[3] bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 6 PLL[0]: MMCM_DRP[3] bit 7 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 8 PLL[0]: MMCM_DRP[3] bit 9 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[3] bit 10 PLL[0]: MMCM_DRP[3] bit 11 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 0 PLL[0]: MMCM_DRP[3] bit 12 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 0 PLL[0]: MMCM_DRP[3] bit 13 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 0 PLL[0]: MMCM_DRP[3] bit 14 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 0 PLL[0]: MMCM_DRP[3] bit 15 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 1 PLL[0]: MMCM_DRP[4] bit 0 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[0] bit 2 PLL[0]: MMCM_DRP[4] bit 1 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 1 PLL[0]: MMCM_DRP[4] bit 2 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[1] bit 2 PLL[0]: MMCM_DRP[4] bit 3 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 1 PLL[0]: MMCM_DRP[4] bit 4 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[2] bit 2 PLL[0]: MMCM_DRP[4] bit 5 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 1 PLL[0]: MMCM_DRP[4] bit 6 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_S[3] bit 2 PLL[0]: MMCM_DRP[4] bit 7 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 8 PLL[0]: CLKBURST_CNT bit 0 PLL[0]: MMCM_DRP[4] bit 9 PLL[0]: CLKBURST_CNT bit 1 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 10 PLL[0]: CLKBURST_CNT bit 2 PLL[0]: MMCM_DRP[4] bit 11 PLL[0]: CLKBURST_CNT bit 3 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 12 PLL[0]: CLKBURST_ENABLE PLL[0]: MMCM_DRP[4] bit 13 PLL[0]: CLKBURST_REPEAT - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[4] bit 14 PLL[0]: TMUX_MUX_SEL bit 0 PLL[0]: MMCM_DRP[4] bit 15 PLL[0]: TMUX_MUX_SEL bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 0 PLL[0]: MMCM_DRP[5] bit 0 SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 1 PLL[0]: MMCM_DRP[5] bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_CASC[0] bit 2 PLL[0]: MMCM_DRP[5] bit 2 PLL[0]: MMCM_DRP[5] bit 3 PLL[0]: DIRECT_PATH_CNTRL - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 4 PLL[0]: IN_DLY_MX_DVDD bit 0 PLL[0]: MMCM_DRP[5] bit 5 PLL[0]: IN_DLY_MX_DVDD bit 1 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 6 PLL[0]: IN_DLY_MX_DVDD bit 2 PLL[0]: MMCM_DRP[5] bit 7 PLL[0]: IN_DLY_MX_DVDD bit 3 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 8 PLL[0]: IN_DLY_MX_DVDD bit 4 PLL[0]: MMCM_DRP[5] bit 9 PLL[0]: IN_DLY_MX_DVDD bit 5 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 10 PLL[0]: V6_IN_DLY_SET bit 0 PLL[0]: MMCM_DRP[5] bit 11 PLL[0]: V6_IN_DLY_SET bit 1 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 12 PLL[0]: V6_IN_DLY_SET bit 2 PLL[0]: MMCM_DRP[5] bit 13 PLL[0]: V6_IN_DLY_SET bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[5] bit 14 PLL[0]: V6_IN_DLY_SET bit 4 PLL[0]: MMCM_DRP[5] bit 15 PLL[0]: IN_DLY_EN - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 0 PLL[0]: CLKOUT5_LT bit 0 PLL[0]: MMCM_DRP[6] bit 1 PLL[0]: CLKOUT5_LT bit 1 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 2 PLL[0]: CLKOUT5_LT bit 2 PLL[0]: MMCM_DRP[6] bit 3 PLL[0]: CLKOUT5_LT bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 4 PLL[0]: CLKOUT5_LT bit 4 PLL[0]: MMCM_DRP[6] bit 5 PLL[0]: CLKOUT5_LT bit 5 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 6 PLL[0]: CLKOUT5_HT bit 0 PLL[0]: MMCM_DRP[6] bit 7 PLL[0]: CLKOUT5_HT bit 1 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 8 PLL[0]: CLKOUT5_HT bit 2 PLL[0]: MMCM_DRP[6] bit 9 PLL[0]: CLKOUT5_HT bit 3 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 10 PLL[0]: CLKOUT5_HT bit 4 PLL[0]: MMCM_DRP[6] bit 11 PLL[0]: CLKOUT5_HT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 12 PLL[0]: CLKOUT5_EN PLL[0]: MMCM_DRP[6] bit 13 PLL[0]: CLKOUT5_PM bit 0 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[6] bit 14 PLL[0]: CLKOUT5_PM bit 1 PLL[0]: MMCM_DRP[6] bit 15 PLL[0]: CLKOUT5_PM bit 2 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 0 PLL[0]: CLKOUT5_DT bit 0 PLL[0]: MMCM_DRP[7] bit 1 PLL[0]: CLKOUT5_DT bit 1 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 2 PLL[0]: CLKOUT5_DT bit 2 PLL[0]: MMCM_DRP[7] bit 3 PLL[0]: CLKOUT5_DT bit 3 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 4 PLL[0]: CLKOUT5_DT bit 4 PLL[0]: MMCM_DRP[7] bit 5 PLL[0]: CLKOUT5_DT bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 6 PLL[0]: CLKOUT5_NOCOUNT PLL[0]: MMCM_DRP[7] bit 7 PLL[0]: CLKOUT5_EDGE - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 8 PLL[0]: CLKOUT5_MX bit 0 PLL[0]: CLKOUT5_USE_FINE_PS PLL[0]: MMCM_DRP[7] bit 9 PLL[0]: CLKOUT5_MX bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 10 PLL[0]: CLKOUT5_FRAC_WF PLL[0]: MMCM_DRP[7] bit 11 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 12 PLL[0]: MMCM_DRP[7] bit 13 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[0]: MMCM_DRP[7] bit 14 PLL[0]: MMCM_DRP[7] bit 15 - - - - - - - - - -
virtex6 CMT rect MAIN[18]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 9 - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 10 BUFHCE_W[4]: ENABLE BUFHCE_W[5]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 10 BUFHCE_E[4]: ENABLE BUFHCE_E[5]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 10 - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 11 - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 12 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 12 - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 13 - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 14 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 5 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 14 - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 1 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 1 - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 15 - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 8 - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 4 - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 7 - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 2 - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[4] bit 3 BUFHCE_W[4]: !invert CE BUFHCE_W[5]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[5] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[4] bit 3 BUFHCE_E[4]: !invert CE BUFHCE_E[5]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[5] bit 3 - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[4]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 8 BUFHCE_W[5]: INIT_OUT bit 0 BUFHCE_E[4]: INIT_OUT bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 8 - BUFHCE_E[5]: INIT_OUT bit 0 - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 9 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 7 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 7 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 9 - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[0] bit 6 - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 9 - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 10 BUFHCE_W[2]: ENABLE BUFHCE_W[3]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 10 BUFHCE_E[2]: ENABLE BUFHCE_E[3]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 10 - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 11 - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 12 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 5 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 12 - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 13 - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 14 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 14 - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 3 - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 15 - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 8 - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 4 - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 7 - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 2 - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[2] bit 3 BUFHCE_W[2]: !invert CE BUFHCE_W[3]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[3] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[2] bit 3 BUFHCE_E[2]: !invert CE BUFHCE_E[3]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[3] bit 3 - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[2]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 7 BUFHCE_W[3]: INIT_OUT bit 0 BUFHCE_E[2]: INIT_OUT bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 7 - BUFHCE_E[3]: INIT_OUT bit 0 - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[0] bit 8 - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 9 - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 10 BUFHCE_W[0]: ENABLE BUFHCE_W[1]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 10 BUFHCE_E[0]: ENABLE BUFHCE_E[1]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 10 - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 4 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 11 - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 12 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 12 - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 13 - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 14 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 14 - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 2 - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 15 - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 8 - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 4 - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 7 - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 2 - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[0] bit 3 BUFHCE_W[0]: !invert CE BUFHCE_W[1]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[1] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[0] bit 3 BUFHCE_E[0]: !invert CE BUFHCE_E[1]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[1] bit 3 - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[0]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 7 BUFHCE_W[1]: INIT_OUT bit 0 BUFHCE_E[0]: INIT_OUT bit 0 - - BUFHCE_E[1]: INIT_OUT bit 0 - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[0] bit 6 - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex6 CMT rect MAIN[19]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 2 - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[12] ← CELL[20].GCLK_CMT[12] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[13] ← CELL[20].GCLK_CMT[13] SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[15] ← CELL[20].GCLK_CMT[15] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[14] ← CELL[20].GCLK_CMT[14] SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 1 - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 3 SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 3 - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 4 - SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 4 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 4 - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 5 SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 2 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 5 - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 6 - SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 6 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 6 - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 5 SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 4 - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 7 - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 17 - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 9 - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 16 - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 14 - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[13] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[14] bit 15 - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[12] bit 0 - SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[15] bit 0 - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 8 SPEC_INT: mux CELL[20].BUFH_TEST_W_IN bit 6 - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[12] ← CELL[20].GCLK_TEST_IN[12] SPEC_INT: invert CELL[20].GCLK_TEST[13] ← CELL[20].GCLK_TEST_IN[13] - SPEC_INT: invert CELL[20].BUFH_TEST_W ← CELL[20].BUFH_TEST_W_IN SPEC_INT: invert CELL[20].GCLK_TEST[15] ← CELL[20].GCLK_TEST_IN[15] SPEC_INT: invert CELL[20].GCLK_TEST[14] ← CELL[20].GCLK_TEST_IN[14] - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 2 - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[8] ← CELL[20].GCLK_CMT[8] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[9] ← CELL[20].GCLK_CMT[9] SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[11] ← CELL[20].GCLK_CMT[11] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[10] ← CELL[20].GCLK_CMT[10] SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 1 - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 3 - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 4 - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 5 - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 6 - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 5 - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 7 - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 17 - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 9 - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 16 - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 14 - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[9] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[10] bit 15 - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[8] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[11] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 7 - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_W[1] bit 8 - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[8] ← CELL[20].GCLK_TEST_IN[8] SPEC_INT: invert CELL[20].GCLK_TEST[9] ← CELL[20].GCLK_TEST_IN[9] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK[0] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[11] ← CELL[20].GCLK_TEST_IN[11] SPEC_INT: invert CELL[20].GCLK_TEST[10] ← CELL[20].GCLK_TEST_IN[10] - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 2 - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[4] ← CELL[20].GCLK_CMT[4] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[5] ← CELL[20].GCLK_CMT[5] SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[7] ← CELL[20].GCLK_CMT[7] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[6] ← CELL[20].GCLK_CMT[6] SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 1 - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 3 - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 4 - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 5 - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 6 - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 5 - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 7 - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 17 - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 9 - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 16 - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 14 - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[5] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[6] bit 15 - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[4] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[7] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 7 - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_W[1] bit 8 - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[4] ← CELL[20].GCLK_TEST_IN[4] SPEC_INT: invert CELL[20].GCLK_TEST[5] ← CELL[20].GCLK_TEST_IN[5] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK[0] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[7] ← CELL[20].GCLK_TEST_IN[7] SPEC_INT: invert CELL[20].GCLK_TEST[6] ← CELL[20].GCLK_TEST_IN[6] - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 2 - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[0] ← CELL[20].GCLK_CMT[0] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[1] ← CELL[20].GCLK_CMT[1] SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[3] ← CELL[20].GCLK_CMT[3] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[2] ← CELL[20].GCLK_CMT[2] SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 1 - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 3 - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 4 - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 5 - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 6 - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 5 - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 7 - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 17 - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 9 - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 16 - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 14 - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[1] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[2] bit 15 - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[0] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[3] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 7 - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_W[1] bit 8 - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[0] ← CELL[20].GCLK_TEST_IN[0] SPEC_INT: invert CELL[20].GCLK_TEST[1] ← CELL[20].GCLK_TEST_IN[1] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK[0] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[3] ← CELL[20].GCLK_TEST_IN[3] SPEC_INT: invert CELL[20].GCLK_TEST[2] ← CELL[20].GCLK_TEST_IN[2] - - - - -
virtex6 CMT rect MAIN[20]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 2 - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[28] ← CELL[20].GCLK_CMT[28] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[29] ← CELL[20].GCLK_CMT[29] SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[31] ← CELL[20].GCLK_CMT[31] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[30] ← CELL[20].GCLK_CMT[30] SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 1 - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 3 - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 4 - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 5 - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 6 - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 5 - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 7 - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 17 - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 9 - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 16 - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 14 - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[29] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[30] bit 15 - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[28] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[31] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 7 - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK_E[0] bit 8 - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[28] ← CELL[20].GCLK_TEST_IN[28] SPEC_INT: invert CELL[20].GCLK_TEST[29] ← CELL[20].GCLK_TEST_IN[29] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_HCLK[1] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[31] ← CELL[20].GCLK_TEST_IN[31] SPEC_INT: invert CELL[20].GCLK_TEST[30] ← CELL[20].GCLK_TEST_IN[30] - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 2 - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[24] ← CELL[20].GCLK_CMT[24] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[25] ← CELL[20].GCLK_CMT[25] SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[27] ← CELL[20].GCLK_CMT[27] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[26] ← CELL[20].GCLK_CMT[26] SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 1 - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 3 - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 4 - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 5 - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 6 - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 5 - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 7 - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 17 - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 9 - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 16 - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 14 - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[25] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[26] bit 15 - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[24] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[27] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 7 - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK_E[0] bit 8 - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[24] ← CELL[20].GCLK_TEST_IN[24] SPEC_INT: invert CELL[20].GCLK_TEST[25] ← CELL[20].GCLK_TEST_IN[25] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_HCLK[1] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[27] ← CELL[20].GCLK_TEST_IN[27] SPEC_INT: invert CELL[20].GCLK_TEST[26] ← CELL[20].GCLK_TEST_IN[26] - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 2 - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[20] ← CELL[20].GCLK_CMT[20] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[21] ← CELL[20].GCLK_CMT[21] SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[23] ← CELL[20].GCLK_CMT[23] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[22] ← CELL[20].GCLK_CMT[22] SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 1 - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 3 - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 4 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 4 - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 5 - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 6 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 6 - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 5 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 5 - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 7 - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 17 - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 9 - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 16 - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 14 - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[21] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[22] bit 15 - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[20] bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[23] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 7 - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK_E[0] bit 8 - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[20] ← CELL[20].GCLK_TEST_IN[20] SPEC_INT: invert CELL[20].GCLK_TEST[21] ← CELL[20].GCLK_TEST_IN[21] - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_HCLK[1] bit 0 SPEC_INT: invert CELL[20].GCLK_TEST[23] ← CELL[20].GCLK_TEST_IN[23] SPEC_INT: invert CELL[20].GCLK_TEST[22] ← CELL[20].GCLK_TEST_IN[22] - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 2 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 2 - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[16] ← CELL[20].GCLK_CMT[16] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[17] ← CELL[20].GCLK_CMT[17] SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 2 SPEC_INT: buffer CELL[20].GCLK_TEST_IN[19] ← CELL[20].GCLK_CMT[19] SPEC_INT: buffer CELL[20].GCLK_TEST_IN[18] ← CELL[20].GCLK_CMT[18] SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 1 - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 3 SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 3 - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 4 - SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 1 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 4 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 4 - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 5 SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 2 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 5 - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 6 - SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 3 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 6 - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 6 - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 5 SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 4 - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 7 - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 17 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 17 - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 9 - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 16 - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 14 - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[17] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[18] bit 15 - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFG_O[16] bit 0 - SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 7 - SPEC_INT: mux CELL[20].IMUX_BUFG_O[19] bit 0 - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 8 SPEC_INT: mux CELL[20].BUFH_TEST_E_IN bit 6 - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: invert CELL[20].GCLK_TEST[16] ← CELL[20].GCLK_TEST_IN[16] SPEC_INT: invert CELL[20].GCLK_TEST[17] ← CELL[20].GCLK_TEST_IN[17] - SPEC_INT: invert CELL[20].BUFH_TEST_E ← CELL[20].BUFH_TEST_E_IN SPEC_INT: invert CELL[20].GCLK_TEST[19] ← CELL[20].GCLK_TEST_IN[19] SPEC_INT: invert CELL[20].GCLK_TEST[18] ← CELL[20].GCLK_TEST_IN[18] - - - - -
virtex6 CMT rect MAIN[21]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 9 - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 10 BUFHCE_W[10]: ENABLE BUFHCE_W[11]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 10 BUFHCE_E[10]: ENABLE BUFHCE_E[11]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 10 - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 4 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 11 - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 12 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 12 - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 0 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 13 - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 14 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 14 - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 2 - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 15 - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 8 - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 4 - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 7 - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 2 - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[10] bit 3 BUFHCE_W[10]: !invert CE BUFHCE_W[11]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[11] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[10] bit 3 BUFHCE_E[10]: !invert CE BUFHCE_E[11]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[11] bit 3 - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[10]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 7 BUFHCE_W[11]: INIT_OUT bit 0 BUFHCE_E[10]: INIT_OUT bit 0 - - BUFHCE_E[11]: INIT_OUT bit 0 - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB_IO[1] bit 6 - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 9 - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 10 BUFHCE_W[8]: ENABLE BUFHCE_W[9]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 10 BUFHCE_E[8]: ENABLE BUFHCE_E[9]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 10 - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 11 - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 12 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 5 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 12 - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 13 - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 14 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 1 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 14 - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 3 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 3 - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 15 - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 8 - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 4 - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 7 - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 2 - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[8] bit 3 BUFHCE_W[8]: !invert CE BUFHCE_W[9]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[9] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[8] bit 3 BUFHCE_E[8]: !invert CE BUFHCE_E[9]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[9] bit 3 - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[8]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 7 BUFHCE_W[9]: INIT_OUT bit 0 BUFHCE_E[8]: INIT_OUT bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 7 - BUFHCE_E[9]: INIT_OUT bit 0 - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 8 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_IO[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_IO[1] bit 8 - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 9 - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 9 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 9 - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 10 BUFHCE_W[6]: ENABLE BUFHCE_W[7]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 10 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 10 BUFHCE_E[6]: ENABLE BUFHCE_E[7]: ENABLE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 10 - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 11 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 11 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 11 - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 12 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 12 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 12 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 3 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 12 - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 13 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 13 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 13 - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 14 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 14 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 14 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 5 - SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 14 - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 1 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 1 - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 15 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 16 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 15 - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 8 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 6 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 8 - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 4 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 5 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 4 - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 7 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 0 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 7 - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 2 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 1 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 2 - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[6] bit 3 BUFHCE_W[6]: !invert CE BUFHCE_W[7]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_W[7] bit 3 SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[6] bit 3 BUFHCE_E[6]: !invert CE BUFHCE_E[7]: !invert CE SPEC_INT: mux CELL[20].IMUX_BUFHCE_E[7] bit 3 - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - BUFHCE_W[6]: INIT_OUT bit 0 - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 8 BUFHCE_W[7]: INIT_OUT bit 0 BUFHCE_E[6]: INIT_OUT bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 8 - BUFHCE_E[7]: INIT_OUT bit 0 - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 9 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 7 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 7 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 9 - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1_MGT[1] bit 6 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2_MGT[1] bit 6 - - - - - - -
virtex6 CMT rect MAIN[22]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 14 PLL[1]: MMCM_DRP[7] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 12 PLL[1]: MMCM_DRP[7] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 10 PLL[1]: CLKOUT5_FRAC_WF PLL[1]: MMCM_DRP[7] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 8 PLL[1]: CLKOUT5_MX bit 0 PLL[1]: CLKOUT5_USE_FINE_PS PLL[1]: MMCM_DRP[7] bit 9 PLL[1]: CLKOUT5_MX bit 1 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 6 PLL[1]: CLKOUT5_NOCOUNT PLL[1]: MMCM_DRP[7] bit 7 PLL[1]: CLKOUT5_EDGE - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 4 PLL[1]: CLKOUT5_DT bit 4 PLL[1]: MMCM_DRP[7] bit 5 PLL[1]: CLKOUT5_DT bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 2 PLL[1]: CLKOUT5_DT bit 2 PLL[1]: MMCM_DRP[7] bit 3 PLL[1]: CLKOUT5_DT bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[7] bit 0 PLL[1]: CLKOUT5_DT bit 0 PLL[1]: MMCM_DRP[7] bit 1 PLL[1]: CLKOUT5_DT bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 14 PLL[1]: CLKOUT5_PM bit 1 PLL[1]: MMCM_DRP[6] bit 15 PLL[1]: CLKOUT5_PM bit 2 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 12 PLL[1]: CLKOUT5_EN PLL[1]: MMCM_DRP[6] bit 13 PLL[1]: CLKOUT5_PM bit 0 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 10 PLL[1]: CLKOUT5_HT bit 4 PLL[1]: MMCM_DRP[6] bit 11 PLL[1]: CLKOUT5_HT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 8 PLL[1]: CLKOUT5_HT bit 2 PLL[1]: MMCM_DRP[6] bit 9 PLL[1]: CLKOUT5_HT bit 3 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 6 PLL[1]: CLKOUT5_HT bit 0 PLL[1]: MMCM_DRP[6] bit 7 PLL[1]: CLKOUT5_HT bit 1 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 4 PLL[1]: CLKOUT5_LT bit 4 PLL[1]: MMCM_DRP[6] bit 5 PLL[1]: CLKOUT5_LT bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 2 PLL[1]: CLKOUT5_LT bit 2 PLL[1]: MMCM_DRP[6] bit 3 PLL[1]: CLKOUT5_LT bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[6] bit 0 PLL[1]: CLKOUT5_LT bit 0 PLL[1]: MMCM_DRP[6] bit 1 PLL[1]: CLKOUT5_LT bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 14 PLL[1]: V6_IN_DLY_SET bit 4 PLL[1]: MMCM_DRP[5] bit 15 PLL[1]: IN_DLY_EN - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 12 PLL[1]: V6_IN_DLY_SET bit 2 PLL[1]: MMCM_DRP[5] bit 13 PLL[1]: V6_IN_DLY_SET bit 3 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 10 PLL[1]: V6_IN_DLY_SET bit 0 PLL[1]: MMCM_DRP[5] bit 11 PLL[1]: V6_IN_DLY_SET bit 1 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 8 PLL[1]: IN_DLY_MX_DVDD bit 4 PLL[1]: MMCM_DRP[5] bit 9 PLL[1]: IN_DLY_MX_DVDD bit 5 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 6 PLL[1]: IN_DLY_MX_DVDD bit 2 PLL[1]: MMCM_DRP[5] bit 7 PLL[1]: IN_DLY_MX_DVDD bit 3 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[5] bit 4 PLL[1]: IN_DLY_MX_DVDD bit 0 PLL[1]: MMCM_DRP[5] bit 5 PLL[1]: IN_DLY_MX_DVDD bit 1 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 2 PLL[1]: MMCM_DRP[5] bit 2 PLL[1]: MMCM_DRP[5] bit 3 PLL[1]: DIRECT_PATH_CNTRL - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 0 PLL[1]: MMCM_DRP[5] bit 0 SPEC_INT: mux CELL[20].OMUX_PLL_CASC[1] bit 1 PLL[1]: MMCM_DRP[5] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[4] bit 14 PLL[1]: TMUX_MUX_SEL bit 0 PLL[1]: MMCM_DRP[4] bit 15 PLL[1]: TMUX_MUX_SEL bit 1 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[4] bit 12 PLL[1]: CLKBURST_ENABLE PLL[1]: MMCM_DRP[4] bit 13 PLL[1]: CLKBURST_REPEAT - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[4] bit 10 PLL[1]: CLKBURST_CNT bit 2 PLL[1]: MMCM_DRP[4] bit 11 PLL[1]: CLKBURST_CNT bit 3 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[4] bit 8 PLL[1]: CLKBURST_CNT bit 0 PLL[1]: MMCM_DRP[4] bit 9 PLL[1]: CLKBURST_CNT bit 1 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 1 PLL[1]: MMCM_DRP[4] bit 6 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 2 PLL[1]: MMCM_DRP[4] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 1 PLL[1]: MMCM_DRP[4] bit 4 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 2 PLL[1]: MMCM_DRP[4] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 1 PLL[1]: MMCM_DRP[4] bit 2 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 2 PLL[1]: MMCM_DRP[4] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 1 PLL[1]: MMCM_DRP[4] bit 0 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 2 PLL[1]: MMCM_DRP[4] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[2] bit 0 PLL[1]: MMCM_DRP[3] bit 14 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[3] bit 0 PLL[1]: MMCM_DRP[3] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[0] bit 0 PLL[1]: MMCM_DRP[3] bit 12 SPEC_INT: mux CELL[20].OMUX_PLL_PERF_N[1] bit 0 PLL[1]: MMCM_DRP[3] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 10 PLL[1]: MMCM_DRP[3] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 8 PLL[1]: MMCM_DRP[3] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 6 PLL[1]: MMCM_DRP[3] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 4 PLL[1]: MMCM_DRP[3] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 2 PLL[1]: MMCM_DRP[3] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[3] bit 0 PLL[1]: MMCM_DRP[3] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 14 PLL[1]: MMCM_DRP[2] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 12 PLL[1]: MMCM_DRP[2] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 10 PLL[1]: MMCM_DRP[2] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 8 PLL[1]: MMCM_DRP[2] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 6 PLL[1]: MMCM_DRP[2] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 4 PLL[1]: MMCM_DRP[2] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 2 PLL[1]: MMCM_DRP[2] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[2] bit 0 PLL[1]: SYNTH_CLK_DIV bit 0 PLL[1]: MMCM_DRP[2] bit 1 PLL[1]: SYNTH_CLK_DIV bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: MMCM_DRP[1] bit 14 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: MMCM_DRP[1] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[2] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: MMCM_DRP[1] bit 12 SPEC_INT: buffer IO_E[4].PERF_ROW[3] ← CELL[20].OMUX_PLL_PERF_N[3] PLL[1]: MMCM_DRP[1] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: MMCM_DRP[1] bit 10 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: MMCM_DRP[1] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[3] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: MMCM_DRP[1] bit 8 SPEC_INT: buffer IO_E[4].PERF_ROW[2] ← CELL[20].OMUX_PLL_PERF_N[2] PLL[1]: MMCM_DRP[1] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: MMCM_DRP[1] bit 6 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: MMCM_DRP[1] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[0] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: MMCM_DRP[1] bit 4 SPEC_INT: buffer IO_E[4].PERF_ROW[1] ← CELL[20].OMUX_PLL_PERF_N[1] PLL[1]: MMCM_DRP[1] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_W[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: MMCM_DRP[1] bit 2 SPEC_INT: buffer IO_W[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: MMCM_DRP[1] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer IO_E[4].PERF_ROW_OUTER[1] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: MMCM_DRP[1] bit 0 SPEC_INT: buffer IO_E[4].PERF_ROW[0] ← CELL[20].OMUX_PLL_PERF_N[0] PLL[1]: MMCM_DRP[1] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[0] bit 14 PLL[1]: HROW_DLY_SET bit 2 PLL[1]: MMCM_DRP[0] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[0] bit 12 PLL[1]: HROW_DLY_SET bit 0 PLL[1]: MMCM_DRP[0] bit 13 PLL[1]: HROW_DLY_SET bit 1 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[0] bit 10 PLL[1]: IN_DLY_MX_CVDD bit 4 PLL[1]: MMCM_DRP[0] bit 11 PLL[1]: IN_DLY_MX_CVDD bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[0] bit 8 PLL[1]: IN_DLY_MX_CVDD bit 2 PLL[1]: MMCM_DRP[0] bit 9 PLL[1]: IN_DLY_MX_CVDD bit 3 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[0] bit 6 PLL[1]: IN_DLY_MX_CVDD bit 0 PLL[1]: MMCM_DRP[0] bit 7 PLL[1]: IN_DLY_MX_CVDD bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[1] bit 0 PLL[1]: MMCM_DRP[0] bit 4 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN2[1] bit 1 PLL[1]: MMCM_DRP[0] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[1] bit 0 PLL[1]: MMCM_DRP[0] bit 2 SPEC_INT: mux CELL[20].IMUX_PLL_CLKIN1[1] bit 1 PLL[1]: MMCM_DRP[0] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[1] bit 0 PLL[1]: MMCM_DRP[0] bit 0 SPEC_INT: mux CELL[20].IMUX_PLL_CLKFB[1] bit 1 PLL[1]: MMCM_DRP[0] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[23]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 14 PLL[1]: MMCM_DRP[15] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 12 PLL[1]: MMCM_DRP[15] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 10 PLL[1]: MMCM_DRP[15] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 8 PLL[1]: CLKOUT3_MX bit 0 PLL[1]: CLKOUT3_USE_FINE_PS PLL[1]: MMCM_DRP[15] bit 9 PLL[1]: CLKOUT3_MX bit 1 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 6 PLL[1]: CLKOUT3_NOCOUNT PLL[1]: MMCM_DRP[15] bit 7 PLL[1]: CLKOUT3_EDGE - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 4 PLL[1]: CLKOUT3_DT bit 4 PLL[1]: MMCM_DRP[15] bit 5 PLL[1]: CLKOUT3_DT bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 2 PLL[1]: CLKOUT3_DT bit 2 PLL[1]: MMCM_DRP[15] bit 3 PLL[1]: CLKOUT3_DT bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[15] bit 0 PLL[1]: CLKOUT3_DT bit 0 PLL[1]: MMCM_DRP[15] bit 1 PLL[1]: CLKOUT3_DT bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 14 PLL[1]: CLKOUT3_PM bit 1 PLL[1]: MMCM_DRP[14] bit 15 PLL[1]: CLKOUT3_PM bit 2 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 12 PLL[1]: CLKOUT3_EN PLL[1]: MMCM_DRP[14] bit 13 PLL[1]: CLKOUT3_PM bit 0 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 10 PLL[1]: CLKOUT3_HT bit 4 PLL[1]: MMCM_DRP[14] bit 11 PLL[1]: CLKOUT3_HT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 8 PLL[1]: CLKOUT3_HT bit 2 PLL[1]: MMCM_DRP[14] bit 9 PLL[1]: CLKOUT3_HT bit 3 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 6 PLL[1]: CLKOUT3_HT bit 0 PLL[1]: MMCM_DRP[14] bit 7 PLL[1]: CLKOUT3_HT bit 1 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 4 PLL[1]: CLKOUT3_LT bit 4 PLL[1]: MMCM_DRP[14] bit 5 PLL[1]: CLKOUT3_LT bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 2 PLL[1]: CLKOUT3_LT bit 2 PLL[1]: MMCM_DRP[14] bit 3 PLL[1]: CLKOUT3_LT bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[14] bit 0 PLL[1]: CLKOUT3_LT bit 0 PLL[1]: MMCM_DRP[14] bit 1 PLL[1]: CLKOUT3_LT bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 14 PLL[1]: MMCM_DRP[13] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 12 PLL[1]: MMCM_DRP[13] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 10 PLL[1]: MMCM_DRP[13] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 8 PLL[1]: CLKOUT2_MX bit 0 PLL[1]: CLKOUT2_USE_FINE_PS PLL[1]: MMCM_DRP[13] bit 9 PLL[1]: CLKOUT2_MX bit 1 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 6 PLL[1]: CLKOUT2_NOCOUNT PLL[1]: MMCM_DRP[13] bit 7 PLL[1]: CLKOUT2_EDGE - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 4 PLL[1]: CLKOUT2_DT bit 4 PLL[1]: MMCM_DRP[13] bit 5 PLL[1]: CLKOUT2_DT bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 2 PLL[1]: CLKOUT2_DT bit 2 PLL[1]: MMCM_DRP[13] bit 3 PLL[1]: CLKOUT2_DT bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[13] bit 0 PLL[1]: CLKOUT2_DT bit 0 PLL[1]: MMCM_DRP[13] bit 1 PLL[1]: CLKOUT2_DT bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 14 PLL[1]: CLKOUT2_PM bit 1 PLL[1]: MMCM_DRP[12] bit 15 PLL[1]: CLKOUT2_PM bit 2 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 12 PLL[1]: CLKOUT2_EN PLL[1]: MMCM_DRP[12] bit 13 PLL[1]: CLKOUT2_PM bit 0 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 10 PLL[1]: CLKOUT2_HT bit 4 PLL[1]: MMCM_DRP[12] bit 11 PLL[1]: CLKOUT2_HT bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 8 PLL[1]: CLKOUT2_HT bit 2 PLL[1]: MMCM_DRP[12] bit 9 PLL[1]: CLKOUT2_HT bit 3 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 6 PLL[1]: CLKOUT2_HT bit 0 PLL[1]: MMCM_DRP[12] bit 7 PLL[1]: CLKOUT2_HT bit 1 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 4 PLL[1]: CLKOUT2_LT bit 4 PLL[1]: MMCM_DRP[12] bit 5 PLL[1]: CLKOUT2_LT bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 2 PLL[1]: CLKOUT2_LT bit 2 PLL[1]: MMCM_DRP[12] bit 3 PLL[1]: CLKOUT2_LT bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[12] bit 0 PLL[1]: CLKOUT2_LT bit 0 PLL[1]: MMCM_DRP[12] bit 1 PLL[1]: CLKOUT2_LT bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 14 PLL[1]: MMCM_DRP[11] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 12 PLL[1]: MMCM_DRP[11] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 10 PLL[1]: MMCM_DRP[11] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 8 PLL[1]: CLKOUT1_MX bit 0 PLL[1]: CLKOUT1_USE_FINE_PS PLL[1]: MMCM_DRP[11] bit 9 PLL[1]: CLKOUT1_MX bit 1 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 6 PLL[1]: CLKOUT1_NOCOUNT PLL[1]: MMCM_DRP[11] bit 7 PLL[1]: CLKOUT1_EDGE - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 4 PLL[1]: CLKOUT1_DT bit 4 PLL[1]: MMCM_DRP[11] bit 5 PLL[1]: CLKOUT1_DT bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 2 PLL[1]: CLKOUT1_DT bit 2 PLL[1]: MMCM_DRP[11] bit 3 PLL[1]: CLKOUT1_DT bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[11] bit 0 PLL[1]: CLKOUT1_DT bit 0 PLL[1]: MMCM_DRP[11] bit 1 PLL[1]: CLKOUT1_DT bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 14 PLL[1]: CLKOUT1_PM bit 1 PLL[1]: MMCM_DRP[10] bit 15 PLL[1]: CLKOUT1_PM bit 2 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 12 PLL[1]: CLKOUT1_EN PLL[1]: MMCM_DRP[10] bit 13 PLL[1]: CLKOUT1_PM bit 0 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 10 PLL[1]: CLKOUT1_HT bit 4 PLL[1]: MMCM_DRP[10] bit 11 PLL[1]: CLKOUT1_HT bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 8 PLL[1]: CLKOUT1_HT bit 2 PLL[1]: MMCM_DRP[10] bit 9 PLL[1]: CLKOUT1_HT bit 3 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 6 PLL[1]: CLKOUT1_HT bit 0 PLL[1]: MMCM_DRP[10] bit 7 PLL[1]: CLKOUT1_HT bit 1 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 4 PLL[1]: CLKOUT1_LT bit 4 PLL[1]: MMCM_DRP[10] bit 5 PLL[1]: CLKOUT1_LT bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 2 PLL[1]: CLKOUT1_LT bit 2 PLL[1]: MMCM_DRP[10] bit 3 PLL[1]: CLKOUT1_LT bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[10] bit 0 PLL[1]: CLKOUT1_LT bit 0 PLL[1]: MMCM_DRP[10] bit 1 PLL[1]: CLKOUT1_LT bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 14 PLL[1]: CLKOUT0_FRAC bit 2 PLL[1]: MMCM_DRP[9] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 12 PLL[1]: CLKOUT0_FRAC bit 0 PLL[1]: MMCM_DRP[9] bit 13 PLL[1]: CLKOUT0_FRAC bit 1 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 10 PLL[1]: CLKOUT0_FRAC_WF PLL[1]: MMCM_DRP[9] bit 11 PLL[1]: CLKOUT0_FRAC_EN - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 8 PLL[1]: CLKOUT0_MX bit 0 PLL[1]: CLKOUT0_USE_FINE_PS PLL[1]: MMCM_DRP[9] bit 9 PLL[1]: CLKOUT0_MX bit 1 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 6 PLL[1]: CLKOUT0_NOCOUNT PLL[1]: MMCM_DRP[9] bit 7 PLL[1]: CLKOUT0_EDGE - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 4 PLL[1]: CLKOUT0_DT bit 4 PLL[1]: MMCM_DRP[9] bit 5 PLL[1]: CLKOUT0_DT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 2 PLL[1]: CLKOUT0_DT bit 2 PLL[1]: MMCM_DRP[9] bit 3 PLL[1]: CLKOUT0_DT bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[9] bit 0 PLL[1]: CLKOUT0_DT bit 0 PLL[1]: MMCM_DRP[9] bit 1 PLL[1]: CLKOUT0_DT bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 14 PLL[1]: CLKOUT0_PM bit 1 PLL[1]: MMCM_DRP[8] bit 15 PLL[1]: CLKOUT0_PM bit 2 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 12 PLL[1]: CLKOUT0_EN PLL[1]: MMCM_DRP[8] bit 13 PLL[1]: CLKOUT0_PM bit 0 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 10 PLL[1]: CLKOUT0_HT bit 4 PLL[1]: MMCM_DRP[8] bit 11 PLL[1]: CLKOUT0_HT bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 8 PLL[1]: CLKOUT0_HT bit 2 PLL[1]: MMCM_DRP[8] bit 9 PLL[1]: CLKOUT0_HT bit 3 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 6 PLL[1]: CLKOUT0_HT bit 0 PLL[1]: MMCM_DRP[8] bit 7 PLL[1]: CLKOUT0_HT bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 4 PLL[1]: CLKOUT0_LT bit 4 PLL[1]: MMCM_DRP[8] bit 5 PLL[1]: CLKOUT0_LT bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 2 PLL[1]: CLKOUT0_LT bit 2 PLL[1]: MMCM_DRP[8] bit 3 PLL[1]: CLKOUT0_LT bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[8] bit 0 PLL[1]: CLKOUT0_LT bit 0 PLL[1]: MMCM_DRP[8] bit 1 PLL[1]: CLKOUT0_LT bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[24]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 14 PLL[1]: MMCM_DRP[23] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 12 PLL[1]: CLKFBIN_NOCOUNT PLL[1]: MMCM_DRP[23] bit 13 PLL[1]: CLKFBIN_EDGE - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 10 PLL[1]: CLKFBIN_HT bit 4 PLL[1]: MMCM_DRP[23] bit 11 PLL[1]: CLKFBIN_HT bit 5 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 8 PLL[1]: CLKFBIN_HT bit 2 PLL[1]: MMCM_DRP[23] bit 9 PLL[1]: CLKFBIN_HT bit 3 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 6 PLL[1]: CLKFBIN_HT bit 0 PLL[1]: MMCM_DRP[23] bit 7 PLL[1]: CLKFBIN_HT bit 1 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 4 PLL[1]: CLKFBIN_LT bit 4 PLL[1]: MMCM_DRP[23] bit 5 PLL[1]: CLKFBIN_LT bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 2 PLL[1]: CLKFBIN_LT bit 2 PLL[1]: MMCM_DRP[23] bit 3 PLL[1]: CLKFBIN_LT bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[23] bit 0 PLL[1]: CLKFBIN_LT bit 0 PLL[1]: MMCM_DRP[23] bit 1 PLL[1]: CLKFBIN_LT bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 14 PLL[1]: MMCM_DRP[22] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 12 PLL[1]: DIVCLK_NOCOUNT PLL[1]: MMCM_DRP[22] bit 13 PLL[1]: DIVCLK_EDGE - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 10 PLL[1]: DIVCLK_HT bit 4 PLL[1]: MMCM_DRP[22] bit 11 PLL[1]: DIVCLK_HT bit 5 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 8 PLL[1]: DIVCLK_HT bit 2 PLL[1]: MMCM_DRP[22] bit 9 PLL[1]: DIVCLK_HT bit 3 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 6 PLL[1]: DIVCLK_HT bit 0 PLL[1]: MMCM_DRP[22] bit 7 PLL[1]: DIVCLK_HT bit 1 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 4 PLL[1]: DIVCLK_LT bit 4 PLL[1]: MMCM_DRP[22] bit 5 PLL[1]: DIVCLK_LT bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 2 PLL[1]: DIVCLK_LT bit 2 PLL[1]: MMCM_DRP[22] bit 3 PLL[1]: DIVCLK_LT bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[22] bit 0 PLL[1]: DIVCLK_LT bit 0 PLL[1]: MMCM_DRP[22] bit 1 PLL[1]: DIVCLK_LT bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 14 PLL[1]: CLKFBOUT_FRAC bit 2 PLL[1]: MMCM_DRP[21] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 12 PLL[1]: CLKFBOUT_FRAC bit 0 PLL[1]: MMCM_DRP[21] bit 13 PLL[1]: CLKFBOUT_FRAC bit 1 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 10 PLL[1]: CLKFBOUT_FRAC_WF PLL[1]: MMCM_DRP[21] bit 11 PLL[1]: CLKFBOUT_FRAC_EN - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 8 PLL[1]: CLKFBOUT_MX bit 0 PLL[1]: CLKFBOUT_USE_FINE_PS PLL[1]: MMCM_DRP[21] bit 9 PLL[1]: CLKFBOUT_MX bit 1 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 6 PLL[1]: CLKFBOUT_NOCOUNT PLL[1]: MMCM_DRP[21] bit 7 PLL[1]: CLKFBOUT_EDGE - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 4 PLL[1]: CLKFBOUT_DT bit 4 PLL[1]: MMCM_DRP[21] bit 5 PLL[1]: CLKFBOUT_DT bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 2 PLL[1]: CLKFBOUT_DT bit 2 PLL[1]: MMCM_DRP[21] bit 3 PLL[1]: CLKFBOUT_DT bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[21] bit 0 PLL[1]: CLKFBOUT_DT bit 0 PLL[1]: MMCM_DRP[21] bit 1 PLL[1]: CLKFBOUT_DT bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 14 PLL[1]: CLKFBOUT_PM bit 1 PLL[1]: MMCM_DRP[20] bit 15 PLL[1]: CLKFBOUT_PM bit 2 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 12 PLL[1]: CLKFBOUT_EN PLL[1]: MMCM_DRP[20] bit 13 PLL[1]: CLKFBOUT_PM bit 0 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 10 PLL[1]: CLKFBOUT_HT bit 4 PLL[1]: MMCM_DRP[20] bit 11 PLL[1]: CLKFBOUT_HT bit 5 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 8 PLL[1]: CLKFBOUT_HT bit 2 PLL[1]: MMCM_DRP[20] bit 9 PLL[1]: CLKFBOUT_HT bit 3 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 6 PLL[1]: CLKFBOUT_HT bit 0 PLL[1]: MMCM_DRP[20] bit 7 PLL[1]: CLKFBOUT_HT bit 1 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 4 PLL[1]: CLKFBOUT_LT bit 4 PLL[1]: MMCM_DRP[20] bit 5 PLL[1]: CLKFBOUT_LT bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 2 PLL[1]: CLKFBOUT_LT bit 2 PLL[1]: MMCM_DRP[20] bit 3 PLL[1]: CLKFBOUT_LT bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[20] bit 0 PLL[1]: CLKFBOUT_LT bit 0 PLL[1]: MMCM_DRP[20] bit 1 PLL[1]: CLKFBOUT_LT bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 14 PLL[1]: MMCM_DRP[19] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 12 PLL[1]: MMCM_DRP[19] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 10 PLL[1]: CLKOUT6_FRAC_WF PLL[1]: MMCM_DRP[19] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 8 PLL[1]: CLKOUT6_MX bit 0 PLL[1]: CLKOUT6_USE_FINE_PS PLL[1]: MMCM_DRP[19] bit 9 PLL[1]: CLKOUT6_MX bit 1 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 6 PLL[1]: CLKOUT6_NOCOUNT PLL[1]: MMCM_DRP[19] bit 7 PLL[1]: CLKOUT6_EDGE - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 4 PLL[1]: CLKOUT6_DT bit 4 PLL[1]: MMCM_DRP[19] bit 5 PLL[1]: CLKOUT6_DT bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 2 PLL[1]: CLKOUT6_DT bit 2 PLL[1]: MMCM_DRP[19] bit 3 PLL[1]: CLKOUT6_DT bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[19] bit 0 PLL[1]: CLKOUT6_DT bit 0 PLL[1]: MMCM_DRP[19] bit 1 PLL[1]: CLKOUT6_DT bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 14 PLL[1]: CLKOUT6_PM bit 1 PLL[1]: MMCM_DRP[18] bit 15 PLL[1]: CLKOUT6_PM bit 2 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 12 PLL[1]: CLKOUT6_EN PLL[1]: MMCM_DRP[18] bit 13 PLL[1]: CLKOUT6_PM bit 0 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 10 PLL[1]: CLKOUT6_HT bit 4 PLL[1]: MMCM_DRP[18] bit 11 PLL[1]: CLKOUT6_HT bit 5 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 8 PLL[1]: CLKOUT6_HT bit 2 PLL[1]: MMCM_DRP[18] bit 9 PLL[1]: CLKOUT6_HT bit 3 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 6 PLL[1]: CLKOUT6_HT bit 0 PLL[1]: MMCM_DRP[18] bit 7 PLL[1]: CLKOUT6_HT bit 1 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 4 PLL[1]: CLKOUT6_LT bit 4 PLL[1]: MMCM_DRP[18] bit 5 PLL[1]: CLKOUT6_LT bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 2 PLL[1]: CLKOUT6_LT bit 2 PLL[1]: MMCM_DRP[18] bit 3 PLL[1]: CLKOUT6_LT bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[18] bit 0 PLL[1]: CLKOUT6_LT bit 0 PLL[1]: MMCM_DRP[18] bit 1 PLL[1]: CLKOUT6_LT bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 14 PLL[1]: MMCM_DRP[17] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 12 PLL[1]: MMCM_DRP[17] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 10 PLL[1]: MMCM_DRP[17] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 8 PLL[1]: CLKOUT4_MX bit 0 PLL[1]: CLKOUT4_USE_FINE_PS PLL[1]: MMCM_DRP[17] bit 9 PLL[1]: CLKOUT4_MX bit 1 PLL[1]: CLKOUT4_CASCADE - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 6 PLL[1]: CLKOUT4_NOCOUNT PLL[1]: MMCM_DRP[17] bit 7 PLL[1]: CLKOUT4_EDGE - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 4 PLL[1]: CLKOUT4_DT bit 4 PLL[1]: MMCM_DRP[17] bit 5 PLL[1]: CLKOUT4_DT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 2 PLL[1]: CLKOUT4_DT bit 2 PLL[1]: MMCM_DRP[17] bit 3 PLL[1]: CLKOUT4_DT bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[17] bit 0 PLL[1]: CLKOUT4_DT bit 0 PLL[1]: MMCM_DRP[17] bit 1 PLL[1]: CLKOUT4_DT bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 14 PLL[1]: CLKOUT4_PM bit 1 PLL[1]: MMCM_DRP[16] bit 15 PLL[1]: CLKOUT4_PM bit 2 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 12 PLL[1]: CLKOUT4_EN PLL[1]: MMCM_DRP[16] bit 13 PLL[1]: CLKOUT4_PM bit 0 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 10 PLL[1]: CLKOUT4_HT bit 4 PLL[1]: MMCM_DRP[16] bit 11 PLL[1]: CLKOUT4_HT bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 8 PLL[1]: CLKOUT4_HT bit 2 PLL[1]: MMCM_DRP[16] bit 9 PLL[1]: CLKOUT4_HT bit 3 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 6 PLL[1]: CLKOUT4_HT bit 0 PLL[1]: MMCM_DRP[16] bit 7 PLL[1]: CLKOUT4_HT bit 1 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 4 PLL[1]: CLKOUT4_LT bit 4 PLL[1]: MMCM_DRP[16] bit 5 PLL[1]: CLKOUT4_LT bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 2 PLL[1]: CLKOUT4_LT bit 2 PLL[1]: MMCM_DRP[16] bit 3 PLL[1]: CLKOUT4_LT bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[16] bit 0 PLL[1]: CLKOUT4_LT bit 0 PLL[1]: MMCM_DRP[16] bit 1 PLL[1]: CLKOUT4_LT bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[25]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 14 PLL[1]: MMCM_DRP[31] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 12 PLL[1]: MMCM_DRP[31] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 10 PLL[1]: MMCM_DRP[31] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 8 PLL[1]: V6_DVDD_COMP_SET bit 1 PLL[1]: MMCM_DRP[31] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 6 PLL[1]: DVDD_VBG_PD bit 2 PLL[1]: MMCM_DRP[31] bit 7 PLL[1]: V6_DVDD_COMP_SET bit 0 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 4 PLL[1]: DVDD_VBG_PD bit 0 PLL[1]: MMCM_DRP[31] bit 5 PLL[1]: DVDD_VBG_PD bit 1 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 2 PLL[1]: DVDD_VBG_SEL bit 2 PLL[1]: MMCM_DRP[31] bit 3 PLL[1]: DVDD_VBG_SEL bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[31] bit 0 PLL[1]: DVDD_VBG_SEL bit 0 PLL[1]: MMCM_DRP[31] bit 1 PLL[1]: DVDD_VBG_SEL bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 14 PLL[1]: MMCM_DRP[30] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 12 PLL[1]: MMCM_DRP[30] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 10 PLL[1]: MMCM_DRP[30] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 8 PLL[1]: MMCM_DRP[30] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 6 PLL[1]: MMCM_DRP[30] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 4 PLL[1]: MMCM_DRP[30] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 2 PLL[1]: MMCM_DRP[30] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[30] bit 0 PLL[1]: MMCM_DRP[30] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 14 PLL[1]: MMCM_DRP[29] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 12 PLL[1]: MMCM_DRP[29] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 10 PLL[1]: PFD bit 6 PLL[1]: MMCM_DRP[29] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 8 PLL[1]: PFD bit 4 PLL[1]: MMCM_DRP[29] bit 9 PLL[1]: PFD bit 5 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 6 PLL[1]: PFD bit 2 PLL[1]: MMCM_DRP[29] bit 7 PLL[1]: PFD bit 3 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 4 PLL[1]: PFD bit 0 PLL[1]: MMCM_DRP[29] bit 5 PLL[1]: PFD bit 1 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 2 PLL[1]: MMCM_DRP[29] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[29] bit 0 PLL[1]: MMCM_DRP[29] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 14 PLL[1]: MMCM_DRP[28] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 12 PLL[1]: MMCM_DRP[28] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 10 PLL[1]: MMCM_DRP[28] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 8 PLL[1]: MMCM_DRP[28] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 6 PLL[1]: MMCM_DRP[28] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 4 PLL[1]: MMCM_DRP[28] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 2 PLL[1]: MMCM_DRP[28] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[28] bit 0 PLL[1]: MMCM_DRP[28] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 14 PLL[1]: MMCM_DRP[27] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 12 PLL[1]: MMCM_DRP[27] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 10 PLL[1]: MMCM_DRP[27] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 8 PLL[1]: MMCM_DRP[27] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 6 PLL[1]: HVLF_STEP PLL[1]: MMCM_DRP[27] bit 7 PLL[1]: HVLF_CNT_TEST_EN - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 4 PLL[1]: HVLF_CNT_TEST bit 4 PLL[1]: MMCM_DRP[27] bit 5 PLL[1]: HVLF_CNT_TEST bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 2 PLL[1]: HVLF_CNT_TEST bit 2 PLL[1]: MMCM_DRP[27] bit 3 PLL[1]: HVLF_CNT_TEST bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[27] bit 0 PLL[1]: HVLF_CNT_TEST bit 0 PLL[1]: MMCM_DRP[27] bit 1 PLL[1]: HVLF_CNT_TEST bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 14 PLL[1]: LOCK_REF_DLY bit 4 PLL[1]: MMCM_DRP[26] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 12 PLL[1]: LOCK_REF_DLY bit 2 PLL[1]: MMCM_DRP[26] bit 13 PLL[1]: LOCK_REF_DLY bit 3 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 10 PLL[1]: LOCK_REF_DLY bit 0 PLL[1]: MMCM_DRP[26] bit 11 PLL[1]: LOCK_REF_DLY bit 1 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 8 PLL[1]: LOCK_SAT_HIGH bit 8 PLL[1]: MMCM_DRP[26] bit 9 PLL[1]: LOCK_SAT_HIGH bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 6 PLL[1]: LOCK_SAT_HIGH bit 6 PLL[1]: MMCM_DRP[26] bit 7 PLL[1]: LOCK_SAT_HIGH bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 4 PLL[1]: LOCK_SAT_HIGH bit 4 PLL[1]: MMCM_DRP[26] bit 5 PLL[1]: LOCK_SAT_HIGH bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 2 PLL[1]: LOCK_SAT_HIGH bit 2 PLL[1]: MMCM_DRP[26] bit 3 PLL[1]: LOCK_SAT_HIGH bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[26] bit 0 PLL[1]: LOCK_SAT_HIGH bit 0 PLL[1]: MMCM_DRP[26] bit 1 PLL[1]: LOCK_SAT_HIGH bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 14 PLL[1]: LOCK_FB_DLY bit 4 PLL[1]: MMCM_DRP[25] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 12 PLL[1]: LOCK_FB_DLY bit 2 PLL[1]: MMCM_DRP[25] bit 13 PLL[1]: LOCK_FB_DLY bit 3 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 10 PLL[1]: LOCK_FB_DLY bit 0 PLL[1]: MMCM_DRP[25] bit 11 PLL[1]: LOCK_FB_DLY bit 1 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 8 PLL[1]: UNLOCK_CNT bit 8 PLL[1]: MMCM_DRP[25] bit 9 PLL[1]: UNLOCK_CNT bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 6 PLL[1]: UNLOCK_CNT bit 6 PLL[1]: MMCM_DRP[25] bit 7 PLL[1]: UNLOCK_CNT bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 4 PLL[1]: UNLOCK_CNT bit 4 PLL[1]: MMCM_DRP[25] bit 5 PLL[1]: UNLOCK_CNT bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 2 PLL[1]: UNLOCK_CNT bit 2 PLL[1]: MMCM_DRP[25] bit 3 PLL[1]: UNLOCK_CNT bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[25] bit 0 PLL[1]: UNLOCK_CNT bit 0 PLL[1]: MMCM_DRP[25] bit 1 PLL[1]: UNLOCK_CNT bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 14 PLL[1]: MMCM_DRP[24] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 12 PLL[1]: MMCM_DRP[24] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 10 PLL[1]: MMCM_DRP[24] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 8 PLL[1]: LOCK_CNT bit 8 PLL[1]: MMCM_DRP[24] bit 9 PLL[1]: LOCK_CNT bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 6 PLL[1]: LOCK_CNT bit 6 PLL[1]: MMCM_DRP[24] bit 7 PLL[1]: LOCK_CNT bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 4 PLL[1]: LOCK_CNT bit 4 PLL[1]: MMCM_DRP[24] bit 5 PLL[1]: LOCK_CNT bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 2 PLL[1]: LOCK_CNT bit 2 PLL[1]: MMCM_DRP[24] bit 3 PLL[1]: LOCK_CNT bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[24] bit 0 PLL[1]: LOCK_CNT bit 0 PLL[1]: MMCM_DRP[24] bit 1 PLL[1]: LOCK_CNT bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[26]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 14 PLL[1]: MMCM_DRP[39] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 12 PLL[1]: MMCM_DRP[39] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 10 PLL[1]: MMCM_DRP[39] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 8 PLL[1]: MMCM_DRP[39] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 6 PLL[1]: MMCM_DRP[39] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 4 PLL[1]: MMCM_DRP[39] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 2 PLL[1]: MMCM_DRP[39] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[39] bit 0 PLL[1]: MMCM_DRP[39] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 14 PLL[1]: MMCM_DRP[38] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 12 PLL[1]: MMCM_DRP[38] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 10 PLL[1]: MMCM_DRP[38] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 8 PLL[1]: ANALOG_MISC bit 3 PLL[1]: MMCM_DRP[38] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 6 PLL[1]: MMCM_DRP[38] bit 7 PLL[1]: ANALOG_MISC bit 2 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 4 PLL[1]: ANALOG_MISC bit 1 PLL[1]: MMCM_DRP[38] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 2 PLL[1]: MMCM_DRP[38] bit 3 PLL[1]: ANALOG_MISC bit 0 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[38] bit 0 PLL[1]: MMCM_DRP[38] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 14 PLL[1]: MMCM_DRP[37] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 12 PLL[1]: MMCM_DRP[37] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 10 PLL[1]: MMCM_DRP[37] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 8 PLL[1]: MMCM_DRP[37] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 6 PLL[1]: MMCM_DRP[37] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 4 PLL[1]: MMCM_DRP[37] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 2 PLL[1]: MMCM_DRP[37] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[37] bit 0 PLL[1]: MMCM_DRP[37] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 14 PLL[1]: MMCM_DRP[36] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 12 PLL[1]: MMCM_DRP[36] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 10 PLL[1]: MMCM_DRP[36] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 8 PLL[1]: MMCM_DRP[36] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 6 PLL[1]: MMCM_DRP[36] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 4 PLL[1]: MMCM_DRP[36] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 2 PLL[1]: MMCM_DRP[36] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[36] bit 0 PLL[1]: MMCM_DRP[36] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 14 PLL[1]: MMCM_DRP[35] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 12 PLL[1]: MMCM_DRP[35] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 10 PLL[1]: MMCM_DRP[35] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 8 PLL[1]: MMCM_DRP[35] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 6 PLL[1]: MMCM_DRP[35] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 4 PLL[1]: MMCM_DRP[35] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 2 PLL[1]: MMCM_DRP[35] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[35] bit 0 PLL[1]: MMCM_DRP[35] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 14 PLL[1]: MMCM_DRP[34] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 12 PLL[1]: MMCM_DRP[34] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 10 PLL[1]: MMCM_DRP[34] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 8 PLL[1]: MMCM_DRP[34] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 6 PLL[1]: MMCM_DRP[34] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 4 PLL[1]: MMCM_DRP[34] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 2 PLL[1]: MMCM_DRP[34] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[34] bit 0 PLL[1]: EN_VCO_DIV6 PLL[1]: MMCM_DRP[34] bit 1 PLL[1]: EN_VCO_DIV1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 14 PLL[1]: MMCM_DRP[33] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 12 PLL[1]: MMCM_DRP[33] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 10 PLL[1]: MMCM_DRP[33] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 8 PLL[1]: MMCM_DRP[33] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 6 PLL[1]: MMCM_DRP[33] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 4 PLL[1]: MMCM_DRP[33] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 2 PLL[1]: MMCM_DRP[33] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[33] bit 0 PLL[1]: MMCM_DRP[33] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 14 PLL[1]: MMCM_DRP[32] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 12 PLL[1]: MMCM_DRP[32] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 10 PLL[1]: MMCM_DRP[32] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 8 PLL[1]: MMCM_DRP[32] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 6 PLL[1]: MMCM_DRP[32] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 4 PLL[1]: MMCM_DRP[32] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 2 PLL[1]: MMCM_DRP[32] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[32] bit 0 PLL[1]: MMCM_DRP[32] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[27]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 14 PLL[1]: MMCM_DRP[47] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 12 PLL[1]: MMCM_DRP[47] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 10 PLL[1]: MMCM_DRP[47] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 8 PLL[1]: MMCM_DRP[47] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 6 PLL[1]: MMCM_DRP[47] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 4 PLL[1]: MMCM_DRP[47] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 2 PLL[1]: MMCM_DRP[47] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[47] bit 0 PLL[1]: MMCM_DRP[47] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 14 PLL[1]: MMCM_DRP[46] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 12 PLL[1]: MMCM_DRP[46] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 10 PLL[1]: MMCM_DRP[46] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 8 PLL[1]: MMCM_DRP[46] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 6 PLL[1]: MMCM_DRP[46] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 4 PLL[1]: MMCM_DRP[46] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 2 PLL[1]: MMCM_DRP[46] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[46] bit 0 PLL[1]: MMCM_DRP[46] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 14 PLL[1]: MMCM_DRP[45] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 12 PLL[1]: MMCM_DRP[45] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 10 PLL[1]: MMCM_DRP[45] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 8 PLL[1]: MMCM_DRP[45] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 6 PLL[1]: MMCM_DRP[45] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 4 PLL[1]: MMCM_DRP[45] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 2 PLL[1]: MMCM_DRP[45] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[45] bit 0 PLL[1]: MMCM_DRP[45] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 14 PLL[1]: MMCM_DRP[44] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 12 PLL[1]: MMCM_DRP[44] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 10 PLL[1]: MMCM_DRP[44] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 8 PLL[1]: MMCM_DRP[44] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 6 PLL[1]: MMCM_DRP[44] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 4 PLL[1]: MMCM_DRP[44] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 2 PLL[1]: MMCM_DRP[44] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[44] bit 0 PLL[1]: MMCM_DRP[44] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 14 PLL[1]: MMCM_DRP[43] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 12 PLL[1]: MMCM_DRP[43] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 10 PLL[1]: MMCM_DRP[43] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 8 PLL[1]: MMCM_DRP[43] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 6 PLL[1]: MMCM_DRP[43] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 4 PLL[1]: MMCM_DRP[43] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 2 PLL[1]: MMCM_DRP[43] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[43] bit 0 PLL[1]: MMCM_DRP[43] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 14 PLL[1]: MMCM_DRP[42] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 12 PLL[1]: MMCM_DRP[42] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 10 PLL[1]: MMCM_DRP[42] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 8 PLL[1]: MMCM_DRP[42] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 6 PLL[1]: MMCM_DRP[42] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 4 PLL[1]: MMCM_DRP[42] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 2 PLL[1]: MMCM_DRP[42] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[42] bit 0 PLL[1]: MMCM_DRP[42] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 14 PLL[1]: MMCM_DRP[41] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 12 PLL[1]: MMCM_DRP[41] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 10 PLL[1]: MMCM_DRP[41] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 8 PLL[1]: MMCM_DRP[41] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 6 PLL[1]: MMCM_DRP[41] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 4 PLL[1]: MMCM_DRP[41] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 2 PLL[1]: MMCM_DRP[41] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[41] bit 0 PLL[1]: MMCM_DRP[41] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 14 PLL[1]: MMCM_DRP[40] bit 15 PLL[1]: INTERP_EN bit 7 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 12 PLL[1]: INTERP_EN bit 6 PLL[1]: MMCM_DRP[40] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 10 PLL[1]: MMCM_DRP[40] bit 11 PLL[1]: INTERP_EN bit 5 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 8 PLL[1]: INTERP_EN bit 4 PLL[1]: MMCM_DRP[40] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 6 PLL[1]: MMCM_DRP[40] bit 7 PLL[1]: INTERP_EN bit 3 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 4 PLL[1]: INTERP_EN bit 2 PLL[1]: MMCM_DRP[40] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 2 PLL[1]: MMCM_DRP[40] bit 3 PLL[1]: INTERP_EN bit 1 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[40] bit 0 PLL[1]: INTERP_EN bit 0 PLL[1]: MMCM_DRP[40] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[28]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 14 PLL[1]: MMCM_DRP[55] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 12 PLL[1]: MMCM_DRP[55] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 10 PLL[1]: MMCM_DRP[55] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 8 PLL[1]: MMCM_DRP[55] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 6 PLL[1]: MMCM_DRP[55] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 4 PLL[1]: MMCM_DRP[55] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 2 PLL[1]: MMCM_DRP[55] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[55] bit 0 PLL[1]: MMCM_DRP[55] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 14 PLL[1]: MMCM_DRP[54] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 12 PLL[1]: MMCM_DRP[54] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 10 PLL[1]: MMCM_DRP[54] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 8 PLL[1]: MMCM_DRP[54] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 6 PLL[1]: MMCM_DRP[54] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 4 PLL[1]: MMCM_DRP[54] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 2 PLL[1]: MMCM_DRP[54] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[54] bit 0 PLL[1]: MMCM_DRP[54] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 14 PLL[1]: MMCM_DRP[53] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 12 PLL[1]: MMCM_DRP[53] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 10 PLL[1]: MMCM_DRP[53] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 8 PLL[1]: MMCM_DRP[53] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 6 PLL[1]: MMCM_DRP[53] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 4 PLL[1]: MMCM_DRP[53] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 2 PLL[1]: MMCM_DRP[53] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[53] bit 0 PLL[1]: MMCM_DRP[53] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 14 PLL[1]: MMCM_DRP[52] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 12 PLL[1]: MMCM_DRP[52] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 10 PLL[1]: MMCM_DRP[52] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 8 PLL[1]: MMCM_DRP[52] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 6 PLL[1]: MMCM_DRP[52] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 4 PLL[1]: MMCM_DRP[52] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 2 PLL[1]: MMCM_DRP[52] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[52] bit 0 PLL[1]: MMCM_DRP[52] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 14 PLL[1]: MMCM_DRP[51] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 12 PLL[1]: MMCM_DRP[51] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 10 PLL[1]: MMCM_DRP[51] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 8 PLL[1]: MMCM_DRP[51] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 6 PLL[1]: MMCM_DRP[51] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 4 PLL[1]: MMCM_DRP[51] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 2 PLL[1]: MMCM_DRP[51] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[51] bit 0 PLL[1]: MMCM_DRP[51] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 14 PLL[1]: MMCM_DRP[50] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 12 PLL[1]: MMCM_DRP[50] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 10 PLL[1]: MMCM_DRP[50] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 8 PLL[1]: MMCM_DRP[50] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 6 PLL[1]: MMCM_DRP[50] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 4 PLL[1]: MMCM_DRP[50] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 2 PLL[1]: MMCM_DRP[50] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[50] bit 0 PLL[1]: MMCM_DRP[50] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 14 PLL[1]: MMCM_DRP[49] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 12 PLL[1]: MMCM_DRP[49] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 10 PLL[1]: MMCM_DRP[49] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 8 PLL[1]: MMCM_DRP[49] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 6 PLL[1]: MMCM_DRP[49] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 4 PLL[1]: MMCM_DRP[49] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 2 PLL[1]: MMCM_DRP[49] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[49] bit 0 PLL[1]: MMCM_DRP[49] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 14 PLL[1]: MMCM_DRP[48] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 12 PLL[1]: MMCM_DRP[48] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 10 PLL[1]: MMCM_DRP[48] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 8 PLL[1]: MMCM_DRP[48] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 6 PLL[1]: MMCM_DRP[48] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 4 PLL[1]: MMCM_DRP[48] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 2 PLL[1]: MMCM_DRP[48] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[48] bit 0 PLL[1]: MMCM_DRP[48] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[29]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 14 PLL[1]: MMCM_DRP[63] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 12 PLL[1]: MMCM_DRP[63] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 10 PLL[1]: MMCM_DRP[63] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 8 PLL[1]: MMCM_DRP[63] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 6 PLL[1]: MMCM_DRP[63] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 4 PLL[1]: MMCM_DRP[63] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 2 PLL[1]: MMCM_DRP[63] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[63] bit 0 PLL[1]: MMCM_DRP[63] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 14 PLL[1]: MMCM_DRP[62] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 12 PLL[1]: MMCM_DRP[62] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 10 PLL[1]: MMCM_DRP[62] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 8 PLL[1]: MMCM_DRP[62] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 6 PLL[1]: MMCM_DRP[62] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 4 PLL[1]: MMCM_DRP[62] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 2 PLL[1]: MMCM_DRP[62] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[62] bit 0 PLL[1]: MMCM_DRP[62] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 14 PLL[1]: MMCM_DRP[61] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 12 PLL[1]: MMCM_DRP[61] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 10 PLL[1]: MMCM_DRP[61] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 8 PLL[1]: MMCM_DRP[61] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 6 PLL[1]: MMCM_DRP[61] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 4 PLL[1]: MMCM_DRP[61] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 2 PLL[1]: MMCM_DRP[61] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[61] bit 0 PLL[1]: MMCM_DRP[61] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 14 PLL[1]: MMCM_DRP[60] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 12 PLL[1]: MMCM_DRP[60] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 10 PLL[1]: MMCM_DRP[60] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 8 PLL[1]: MMCM_DRP[60] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 6 PLL[1]: MMCM_DRP[60] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 4 PLL[1]: MMCM_DRP[60] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 2 PLL[1]: MMCM_DRP[60] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[60] bit 0 PLL[1]: MMCM_DRP[60] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 14 PLL[1]: MMCM_DRP[59] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 12 PLL[1]: MMCM_DRP[59] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 10 PLL[1]: MMCM_DRP[59] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 8 PLL[1]: MMCM_DRP[59] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 6 PLL[1]: MMCM_DRP[59] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 4 PLL[1]: MMCM_DRP[59] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 2 PLL[1]: MMCM_DRP[59] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[59] bit 0 PLL[1]: MMCM_DRP[59] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 14 PLL[1]: MMCM_DRP[58] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 12 PLL[1]: MMCM_DRP[58] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 10 PLL[1]: MMCM_DRP[58] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 8 PLL[1]: MMCM_DRP[58] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 6 PLL[1]: MMCM_DRP[58] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 4 PLL[1]: MMCM_DRP[58] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 2 PLL[1]: MMCM_DRP[58] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[58] bit 0 PLL[1]: MMCM_DRP[58] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 14 PLL[1]: MMCM_DRP[57] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 12 PLL[1]: MMCM_DRP[57] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 10 PLL[1]: MMCM_DRP[57] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 8 PLL[1]: MMCM_DRP[57] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 6 PLL[1]: MMCM_DRP[57] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 4 PLL[1]: MMCM_DRP[57] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 2 PLL[1]: MMCM_DRP[57] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[57] bit 0 PLL[1]: MMCM_DRP[57] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 14 PLL[1]: MMCM_DRP[56] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 12 PLL[1]: MMCM_DRP[56] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 10 PLL[1]: MMCM_DRP[56] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 8 PLL[1]: MMCM_DRP[56] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 6 PLL[1]: MMCM_DRP[56] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 4 PLL[1]: MMCM_DRP[56] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 2 PLL[1]: MMCM_DRP[56] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[56] bit 0 PLL[1]: MMCM_DRP[56] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[30]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 14 PLL[1]: MMCM_DRP[71] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 12 PLL[1]: MMCM_DRP[71] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 10 PLL[1]: MMCM_DRP[71] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 8 PLL[1]: MMCM_DRP[71] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 6 PLL[1]: MMCM_DRP[71] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 4 PLL[1]: MMCM_DRP[71] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 2 PLL[1]: MMCM_DRP[71] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[71] bit 0 PLL[1]: MMCM_DRP[71] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 14 PLL[1]: MMCM_DRP[70] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 12 PLL[1]: MMCM_DRP[70] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 10 PLL[1]: MMCM_DRP[70] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 8 PLL[1]: MMCM_DRP[70] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 6 PLL[1]: MMCM_DRP[70] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 4 PLL[1]: MMCM_DRP[70] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 2 PLL[1]: MMCM_DRP[70] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[70] bit 0 PLL[1]: VLF_HIGH_PWDN_B PLL[1]: MMCM_DRP[70] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 14 PLL[1]: MMCM_DRP[69] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 12 PLL[1]: MMCM_DRP[69] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 10 PLL[1]: MMCM_DRP[69] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 8 PLL[1]: MMCM_DRP[69] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 6 PLL[1]: MMCM_DRP[69] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 4 PLL[1]: MMCM_DRP[69] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 2 PLL[1]: MMCM_DRP[69] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[69] bit 0 PLL[1]: MMCM_DRP[69] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 14 PLL[1]: MMCM_DRP[68] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 12 PLL[1]: MMCM_DRP[68] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 10 PLL[1]: MMCM_DRP[68] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 8 PLL[1]: MMCM_DRP[68] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 6 PLL[1]: MMCM_DRP[68] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 4 PLL[1]: MMCM_DRP[68] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 2 PLL[1]: MMCM_DRP[68] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[68] bit 0 PLL[1]: MMCM_DRP[68] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 14 PLL[1]: MMCM_DRP[67] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 12 PLL[1]: MMCM_DRP[67] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 10 PLL[1]: MMCM_DRP[67] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 8 PLL[1]: MMCM_DRP[67] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 6 PLL[1]: MMCM_DRP[67] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 4 PLL[1]: MMCM_DRP[67] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 2 PLL[1]: MMCM_DRP[67] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[67] bit 0 PLL[1]: MMCM_DRP[67] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 14 PLL[1]: MMCM_DRP[66] bit 15 PLL[1]: LF_NEN bit 1 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 12 PLL[1]: LF_NEN bit 0 PLL[1]: MMCM_DRP[66] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 10 PLL[1]: MMCM_DRP[66] bit 11 PLL[1]: LF_PEN bit 1 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 8 PLL[1]: LF_PEN bit 0 PLL[1]: MMCM_DRP[66] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 6 PLL[1]: MMCM_DRP[66] bit 7 PLL[1]: VLF_HIGH_DIS_B - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 4 PLL[1]: MAN_LF bit 2 PLL[1]: MMCM_DRP[66] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 2 PLL[1]: MMCM_DRP[66] bit 3 PLL[1]: MAN_LF bit 1 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[66] bit 0 PLL[1]: MAN_LF bit 0 PLL[1]: MMCM_DRP[66] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 14 PLL[1]: MMCM_DRP[65] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 12 PLL[1]: MMCM_DRP[65] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 10 PLL[1]: MMCM_DRP[65] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 8 PLL[1]: MMCM_DRP[65] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 6 PLL[1]: MMCM_DRP[65] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 4 PLL[1]: MMCM_DRP[65] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 2 PLL[1]: MMCM_DRP[65] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[65] bit 0 PLL[1]: MMCM_DRP[65] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 14 PLL[1]: MMCM_DRP[64] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 12 PLL[1]: MMCM_DRP[64] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 10 PLL[1]: MMCM_DRP[64] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 8 PLL[1]: MMCM_DRP[64] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 6 PLL[1]: MMCM_DRP[64] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 4 PLL[1]: MMCM_DRP[64] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 2 PLL[1]: MMCM_DRP[64] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[64] bit 0 PLL[1]: MMCM_DRP[64] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[31]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 14 PLL[1]: MMCM_DRP[79] bit 15 PLL[1]: RES bit 3 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 12 PLL[1]: RES bit 2 PLL[1]: MMCM_DRP[79] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 10 PLL[1]: MMCM_DRP[79] bit 11 PLL[1]: RES bit 1 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 8 PLL[1]: RES bit 0 PLL[1]: MMCM_DRP[79] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 6 PLL[1]: MMCM_DRP[79] bit 7 PLL[1]: LFHF bit 1 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 4 PLL[1]: LFHF bit 0 PLL[1]: MMCM_DRP[79] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 2 PLL[1]: MMCM_DRP[79] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[79] bit 0 PLL[1]: MMCM_DRP[79] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 14 PLL[1]: MMCM_DRP[78] bit 15 PLL[1]: CP bit 3 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 12 PLL[1]: CP bit 2 PLL[1]: MMCM_DRP[78] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 10 PLL[1]: MMCM_DRP[78] bit 11 PLL[1]: CP bit 1 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 8 PLL[1]: CP bit 0 PLL[1]: MMCM_DRP[78] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 6 PLL[1]: MMCM_DRP[78] bit 7 PLL[1]: CP_BIAS_TRIP_SET bit 0 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 4 PLL[1]: CP_RES bit 1 PLL[1]: MMCM_DRP[78] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 2 PLL[1]: MMCM_DRP[78] bit 3 PLL[1]: CP_RES bit 0 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[78] bit 0 PLL[1]: MMCM_DRP[78] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 14 PLL[1]: MMCM_DRP[77] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 12 PLL[1]: MMCM_DRP[77] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 10 PLL[1]: MMCM_DRP[77] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 8 PLL[1]: MMCM_DRP[77] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 6 PLL[1]: MMCM_DRP[77] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 4 PLL[1]: MMCM_DRP[77] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 2 PLL[1]: MMCM_DRP[77] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[77] bit 0 PLL[1]: MMCM_DRP[77] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 14 PLL[1]: MMCM_DRP[76] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 12 PLL[1]: MMCM_DRP[76] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 10 PLL[1]: MMCM_DRP[76] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 8 PLL[1]: MMCM_DRP[76] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 6 PLL[1]: MMCM_DRP[76] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 4 PLL[1]: MMCM_DRP[76] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 2 PLL[1]: MMCM_DRP[76] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[76] bit 0 PLL[1]: MMCM_DRP[76] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 14 PLL[1]: MMCM_DRP[75] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 12 PLL[1]: MMCM_DRP[75] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 10 PLL[1]: MMCM_DRP[75] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 8 PLL[1]: MMCM_DRP[75] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 6 PLL[1]: MMCM_DRP[75] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 4 PLL[1]: MMCM_DRP[75] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 2 PLL[1]: MMCM_DRP[75] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[75] bit 0 PLL[1]: MMCM_DRP[75] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 14 PLL[1]: MMCM_DRP[74] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 12 PLL[1]: MMCM_DRP[74] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 10 PLL[1]: MMCM_DRP[74] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 8 PLL[1]: V6_AVDD_COMP_SET bit 1 PLL[1]: MMCM_DRP[74] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 6 PLL[1]: AVDD_VBG_PD bit 2 PLL[1]: MMCM_DRP[74] bit 7 PLL[1]: V6_AVDD_COMP_SET bit 0 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 4 PLL[1]: AVDD_VBG_PD bit 0 PLL[1]: MMCM_DRP[74] bit 5 PLL[1]: AVDD_VBG_PD bit 1 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 2 PLL[1]: AVDD_VBG_SEL bit 2 PLL[1]: MMCM_DRP[74] bit 3 PLL[1]: AVDD_VBG_SEL bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[74] bit 0 PLL[1]: AVDD_VBG_SEL bit 0 PLL[1]: MMCM_DRP[74] bit 1 PLL[1]: AVDD_VBG_SEL bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 14 PLL[1]: MMCM_DRP[73] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 12 PLL[1]: MMCM_DRP[73] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 10 PLL[1]: MMCM_DRP[73] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 8 PLL[1]: MMCM_DRP[73] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 6 PLL[1]: MMCM_DRP[73] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 4 PLL[1]: MMCM_DRP[73] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 2 PLL[1]: MMCM_DRP[73] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[73] bit 0 PLL[1]: MMCM_DRP[73] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 14 PLL[1]: MMCM_DRP[72] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 12 PLL[1]: MMCM_DRP[72] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 10 PLL[1]: MMCM_DRP[72] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 8 PLL[1]: MMCM_DRP[72] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 6 PLL[1]: MMCM_DRP[72] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 4 PLL[1]: MMCM_DRP[72] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 2 PLL[1]: MMCM_DRP[72] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[72] bit 0 PLL[1]: MMCM_DRP[72] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[32]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 14 PLL[1]: MMCM_DRP[87] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 12 PLL[1]: MMCM_DRP[87] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 10 PLL[1]: MMCM_DRP[87] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 8 PLL[1]: MMCM_DRP[87] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 6 PLL[1]: MMCM_DRP[87] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 4 PLL[1]: MMCM_DRP[87] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 2 PLL[1]: MMCM_DRP[87] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[87] bit 0 PLL[1]: MMCM_DRP[87] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 14 PLL[1]: MMCM_DRP[86] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 12 PLL[1]: MMCM_DRP[86] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 10 PLL[1]: MMCM_DRP[86] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 8 PLL[1]: MMCM_DRP[86] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 6 PLL[1]: MMCM_DRP[86] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 4 PLL[1]: MMCM_DRP[86] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 2 PLL[1]: MMCM_DRP[86] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[86] bit 0 PLL[1]: MMCM_DRP[86] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 14 PLL[1]: MMCM_DRP[85] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 12 PLL[1]: MMCM_DRP[85] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 10 PLL[1]: MMCM_DRP[85] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 8 PLL[1]: MMCM_DRP[85] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 6 PLL[1]: MMCM_DRP[85] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 4 PLL[1]: MMCM_DRP[85] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 2 PLL[1]: MMCM_DRP[85] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[85] bit 0 PLL[1]: MMCM_DRP[85] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 14 PLL[1]: MMCM_DRP[84] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 12 PLL[1]: MMCM_DRP[84] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 10 PLL[1]: MMCM_DRP[84] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 8 PLL[1]: MMCM_DRP[84] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 6 PLL[1]: MMCM_DRP[84] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 4 PLL[1]: MMCM_DRP[84] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 2 PLL[1]: MMCM_DRP[84] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[84] bit 0 PLL[1]: MMCM_DRP[84] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 14 PLL[1]: MMCM_DRP[83] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 12 PLL[1]: MMCM_DRP[83] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 10 PLL[1]: MMCM_DRP[83] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 8 PLL[1]: MMCM_DRP[83] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 6 PLL[1]: MMCM_DRP[83] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 4 PLL[1]: MMCM_DRP[83] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 2 PLL[1]: MMCM_DRP[83] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[83] bit 0 PLL[1]: MMCM_DRP[83] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 14 PLL[1]: MMCM_DRP[82] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 12 PLL[1]: MMCM_DRP[82] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 10 PLL[1]: MMCM_DRP[82] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 8 PLL[1]: MMCM_DRP[82] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 6 PLL[1]: MMCM_DRP[82] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 4 PLL[1]: MMCM_DRP[82] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 2 PLL[1]: MMCM_DRP[82] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[82] bit 0 PLL[1]: MMCM_DRP[82] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 14 PLL[1]: MMCM_DRP[81] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 12 PLL[1]: MMCM_DRP[81] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 10 PLL[1]: MMCM_DRP[81] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 8 PLL[1]: MMCM_DRP[81] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 6 PLL[1]: MMCM_DRP[81] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 4 PLL[1]: MMCM_DRP[81] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 2 PLL[1]: MMCM_DRP[81] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[81] bit 0 PLL[1]: MMCM_DRP[81] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 14 PLL[1]: MMCM_DRP[80] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 12 PLL[1]: MMCM_DRP[80] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 10 PLL[1]: MMCM_DRP[80] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 8 PLL[1]: MMCM_DRP[80] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 6 PLL[1]: MMCM_DRP[80] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 4 PLL[1]: MMCM_DRP[80] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 2 PLL[1]: MMCM_DRP[80] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[80] bit 0 PLL[1]: MMCM_DRP[80] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[33]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 14 PLL[1]: MMCM_DRP[95] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 12 PLL[1]: MMCM_DRP[95] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 10 PLL[1]: MMCM_DRP[95] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 8 PLL[1]: MMCM_DRP[95] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 6 PLL[1]: MMCM_DRP[95] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 4 PLL[1]: MMCM_DRP[95] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 2 PLL[1]: MMCM_DRP[95] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[95] bit 0 PLL[1]: MMCM_DRP[95] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 14 PLL[1]: MMCM_DRP[94] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 12 PLL[1]: MMCM_DRP[94] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 10 PLL[1]: MMCM_DRP[94] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 8 PLL[1]: MMCM_DRP[94] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 6 PLL[1]: MMCM_DRP[94] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 4 PLL[1]: MMCM_DRP[94] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 2 PLL[1]: MMCM_DRP[94] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[94] bit 0 PLL[1]: MMCM_DRP[94] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 14 PLL[1]: MMCM_DRP[93] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 12 PLL[1]: MMCM_DRP[93] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 10 PLL[1]: MMCM_DRP[93] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 8 PLL[1]: MMCM_DRP[93] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 6 PLL[1]: MMCM_DRP[93] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 4 PLL[1]: MMCM_DRP[93] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 2 PLL[1]: MMCM_DRP[93] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[93] bit 0 PLL[1]: MMCM_DRP[93] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 14 PLL[1]: MMCM_DRP[92] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 12 PLL[1]: MMCM_DRP[92] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 10 PLL[1]: MMCM_DRP[92] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 8 PLL[1]: MMCM_DRP[92] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 6 PLL[1]: MMCM_DRP[92] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 4 PLL[1]: MMCM_DRP[92] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 2 PLL[1]: MMCM_DRP[92] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[92] bit 0 PLL[1]: MMCM_DRP[92] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 14 PLL[1]: MMCM_DRP[91] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 12 PLL[1]: MMCM_DRP[91] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 10 PLL[1]: MMCM_DRP[91] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 8 PLL[1]: MMCM_DRP[91] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 6 PLL[1]: MMCM_DRP[91] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 4 PLL[1]: MMCM_DRP[91] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 2 PLL[1]: MMCM_DRP[91] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[91] bit 0 PLL[1]: MMCM_DRP[91] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 14 PLL[1]: MMCM_DRP[90] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 12 PLL[1]: MMCM_DRP[90] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 10 PLL[1]: MMCM_DRP[90] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 8 PLL[1]: MMCM_DRP[90] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 6 PLL[1]: MMCM_DRP[90] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 4 PLL[1]: MMCM_DRP[90] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 2 PLL[1]: MMCM_DRP[90] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[90] bit 0 PLL[1]: MMCM_DRP[90] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 14 PLL[1]: MMCM_DRP[89] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 12 PLL[1]: MMCM_DRP[89] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 10 PLL[1]: MMCM_DRP[89] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 8 PLL[1]: MMCM_DRP[89] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 6 PLL[1]: MMCM_DRP[89] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 4 PLL[1]: MMCM_DRP[89] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 2 PLL[1]: MMCM_DRP[89] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[89] bit 0 PLL[1]: MMCM_DRP[89] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 14 PLL[1]: MMCM_DRP[88] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 12 PLL[1]: MMCM_DRP[88] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 10 PLL[1]: MMCM_DRP[88] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 8 PLL[1]: MMCM_DRP[88] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 6 PLL[1]: MMCM_DRP[88] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 4 PLL[1]: MMCM_DRP[88] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 2 PLL[1]: MMCM_DRP[88] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[88] bit 0 PLL[1]: MMCM_DRP[88] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[34]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 14 PLL[1]: MMCM_DRP[103] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 12 PLL[1]: MMCM_DRP[103] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 10 PLL[1]: MMCM_DRP[103] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 8 PLL[1]: MMCM_DRP[103] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 6 PLL[1]: MMCM_DRP[103] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 4 PLL[1]: MMCM_DRP[103] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 2 PLL[1]: MMCM_DRP[103] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[103] bit 0 PLL[1]: MMCM_DRP[103] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 14 PLL[1]: MMCM_DRP[102] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 12 PLL[1]: MMCM_DRP[102] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 10 PLL[1]: MMCM_DRP[102] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 8 PLL[1]: MMCM_DRP[102] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 6 PLL[1]: MMCM_DRP[102] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 4 PLL[1]: MMCM_DRP[102] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 2 PLL[1]: MMCM_DRP[102] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[102] bit 0 PLL[1]: MMCM_DRP[102] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 14 PLL[1]: MMCM_DRP[101] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 12 PLL[1]: MMCM_DRP[101] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 10 PLL[1]: MMCM_DRP[101] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 8 PLL[1]: MMCM_DRP[101] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 6 PLL[1]: MMCM_DRP[101] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 4 PLL[1]: MMCM_DRP[101] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 2 PLL[1]: MMCM_DRP[101] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[101] bit 0 PLL[1]: MMCM_DRP[101] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 14 PLL[1]: MMCM_DRP[100] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 12 PLL[1]: MMCM_DRP[100] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 10 PLL[1]: MMCM_DRP[100] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 8 PLL[1]: MMCM_DRP[100] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 6 PLL[1]: MMCM_DRP[100] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 4 PLL[1]: MMCM_DRP[100] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 2 PLL[1]: MMCM_DRP[100] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[100] bit 0 PLL[1]: MMCM_DRP[100] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 14 PLL[1]: MMCM_DRP[99] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 12 PLL[1]: MMCM_DRP[99] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 10 PLL[1]: MMCM_DRP[99] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 8 PLL[1]: MMCM_DRP[99] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 6 PLL[1]: MMCM_DRP[99] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 4 PLL[1]: MMCM_DRP[99] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 2 PLL[1]: MMCM_DRP[99] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[99] bit 0 PLL[1]: MMCM_DRP[99] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 14 PLL[1]: MMCM_DRP[98] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 12 PLL[1]: MMCM_DRP[98] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 10 PLL[1]: MMCM_DRP[98] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 8 PLL[1]: MMCM_DRP[98] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 6 PLL[1]: MMCM_DRP[98] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 4 PLL[1]: MMCM_DRP[98] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 2 PLL[1]: MMCM_DRP[98] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[98] bit 0 PLL[1]: MMCM_DRP[98] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 14 PLL[1]: MMCM_DRP[97] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 12 PLL[1]: MMCM_DRP[97] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 10 PLL[1]: MMCM_DRP[97] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 8 PLL[1]: MMCM_DRP[97] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 6 PLL[1]: MMCM_DRP[97] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 4 PLL[1]: MMCM_DRP[97] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 2 PLL[1]: MMCM_DRP[97] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[97] bit 0 PLL[1]: MMCM_DRP[97] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 14 PLL[1]: MMCM_DRP[96] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 12 PLL[1]: MMCM_DRP[96] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 10 PLL[1]: MMCM_DRP[96] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 8 PLL[1]: MMCM_DRP[96] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 6 PLL[1]: MMCM_DRP[96] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 4 PLL[1]: MMCM_DRP[96] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 2 PLL[1]: MMCM_DRP[96] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[96] bit 0 PLL[1]: MMCM_DRP[96] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[35]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 14 PLL[1]: MMCM_DRP[111] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 12 PLL[1]: MMCM_DRP[111] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 10 PLL[1]: MMCM_DRP[111] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 8 PLL[1]: MMCM_DRP[111] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 6 PLL[1]: MMCM_DRP[111] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 4 PLL[1]: MMCM_DRP[111] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 2 PLL[1]: MMCM_DRP[111] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[111] bit 0 PLL[1]: MMCM_DRP[111] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 14 PLL[1]: MMCM_DRP[110] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 12 PLL[1]: MMCM_DRP[110] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 10 PLL[1]: MMCM_DRP[110] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 8 PLL[1]: MMCM_DRP[110] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 6 PLL[1]: MMCM_DRP[110] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 4 PLL[1]: MMCM_DRP[110] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 2 PLL[1]: MMCM_DRP[110] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[110] bit 0 PLL[1]: MMCM_DRP[110] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 14 PLL[1]: MMCM_DRP[109] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 12 PLL[1]: MMCM_DRP[109] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 10 PLL[1]: MMCM_DRP[109] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 8 PLL[1]: MMCM_DRP[109] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 6 PLL[1]: MMCM_DRP[109] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 4 PLL[1]: MMCM_DRP[109] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 2 PLL[1]: MMCM_DRP[109] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[109] bit 0 PLL[1]: MMCM_DRP[109] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 14 PLL[1]: MMCM_DRP[108] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 12 PLL[1]: MMCM_DRP[108] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 10 PLL[1]: MMCM_DRP[108] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 8 PLL[1]: MMCM_DRP[108] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 6 PLL[1]: MMCM_DRP[108] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 4 PLL[1]: MMCM_DRP[108] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 2 PLL[1]: MMCM_DRP[108] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[108] bit 0 PLL[1]: MMCM_DRP[108] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 14 PLL[1]: MMCM_DRP[107] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 12 PLL[1]: MMCM_DRP[107] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 10 PLL[1]: MMCM_DRP[107] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 8 PLL[1]: MMCM_DRP[107] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 6 PLL[1]: MMCM_DRP[107] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 4 PLL[1]: MMCM_DRP[107] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 2 PLL[1]: MMCM_DRP[107] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[107] bit 0 PLL[1]: MMCM_DRP[107] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 14 PLL[1]: MMCM_DRP[106] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 12 PLL[1]: MMCM_DRP[106] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 10 PLL[1]: MMCM_DRP[106] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 8 PLL[1]: MMCM_DRP[106] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 6 PLL[1]: MMCM_DRP[106] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 4 PLL[1]: MMCM_DRP[106] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 2 PLL[1]: MMCM_DRP[106] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[106] bit 0 PLL[1]: MMCM_DRP[106] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 14 PLL[1]: MMCM_DRP[105] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 12 PLL[1]: MMCM_DRP[105] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 10 PLL[1]: MMCM_DRP[105] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 8 PLL[1]: MMCM_DRP[105] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 6 PLL[1]: MMCM_DRP[105] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 4 PLL[1]: MMCM_DRP[105] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 2 PLL[1]: MMCM_DRP[105] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[105] bit 0 PLL[1]: MMCM_DRP[105] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 14 PLL[1]: MMCM_DRP[104] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 12 PLL[1]: MMCM_DRP[104] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 10 PLL[1]: MMCM_DRP[104] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 8 PLL[1]: MMCM_DRP[104] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 6 PLL[1]: MMCM_DRP[104] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 4 PLL[1]: MMCM_DRP[104] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 2 PLL[1]: MMCM_DRP[104] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[104] bit 0 PLL[1]: MMCM_DRP[104] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[36]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 14 PLL[1]: CONTROL_1 bit 14 PLL[1]: MMCM_DRP[119] bit 15 PLL[1]: CONTROL_1 bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 12 PLL[1]: CONTROL_1 bit 12 PLL[1]: MMCM_DRP[119] bit 13 PLL[1]: CONTROL_1 bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 10 PLL[1]: CONTROL_1 bit 10 PLL[1]: MMCM_DRP[119] bit 11 PLL[1]: CONTROL_1 bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 8 PLL[1]: CONTROL_1 bit 8 PLL[1]: MMCM_DRP[119] bit 9 PLL[1]: CONTROL_1 bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 6 PLL[1]: CONTROL_1 bit 6 PLL[1]: MMCM_DRP[119] bit 7 PLL[1]: CONTROL_1 bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 4 PLL[1]: CONTROL_1 bit 4 PLL[1]: MMCM_DRP[119] bit 5 PLL[1]: CONTROL_1 bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 2 PLL[1]: CONTROL_1 bit 2 PLL[1]: MMCM_DRP[119] bit 3 PLL[1]: CONTROL_1 bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[119] bit 0 PLL[1]: CONTROL_1 bit 0 PLL[1]: MMCM_DRP[119] bit 1 PLL[1]: CONTROL_1 bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 14 PLL[1]: CONTROL_0 bit 14 PLL[1]: MMCM_DRP[118] bit 15 PLL[1]: CONTROL_0 bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 12 PLL[1]: CONTROL_0 bit 12 PLL[1]: MMCM_DRP[118] bit 13 PLL[1]: CONTROL_0 bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 10 PLL[1]: CONTROL_0 bit 10 PLL[1]: MMCM_DRP[118] bit 11 PLL[1]: CONTROL_0 bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 8 PLL[1]: CONTROL_0 bit 8 PLL[1]: MMCM_DRP[118] bit 9 PLL[1]: CONTROL_0 bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 6 PLL[1]: CONTROL_0 bit 6 PLL[1]: MMCM_DRP[118] bit 7 PLL[1]: CONTROL_0 bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 4 PLL[1]: CONTROL_0 bit 4 PLL[1]: MMCM_DRP[118] bit 5 PLL[1]: CONTROL_0 bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 2 PLL[1]: CONTROL_0 bit 2 PLL[1]: MMCM_DRP[118] bit 3 PLL[1]: CONTROL_0 bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[118] bit 0 PLL[1]: CONTROL_0 bit 0 PLL[1]: MMCM_DRP[118] bit 1 PLL[1]: CONTROL_0 bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 14 PLL[1]: MMCM_DRP[117] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 12 PLL[1]: MMCM_DRP[117] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 10 PLL[1]: MMCM_DRP[117] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 8 PLL[1]: MMCM_DRP[117] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 6 PLL[1]: MMCM_DRP[117] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 4 PLL[1]: MMCM_DRP[117] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 2 PLL[1]: MMCM_DRP[117] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[117] bit 0 PLL[1]: MMCM_DRP[117] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 14 PLL[1]: MMCM_DRP[116] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 12 PLL[1]: MMCM_DRP[116] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 10 PLL[1]: FINE_PS_FRAC bit 5 PLL[1]: MMCM_DRP[116] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 8 PLL[1]: FINE_PS_FRAC bit 3 PLL[1]: MMCM_DRP[116] bit 9 PLL[1]: FINE_PS_FRAC bit 4 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 6 PLL[1]: FINE_PS_FRAC bit 1 PLL[1]: MMCM_DRP[116] bit 7 PLL[1]: FINE_PS_FRAC bit 2 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 4 PLL[1]: CASC_LOCK_EN PLL[1]: MMCM_DRP[116] bit 5 PLL[1]: FINE_PS_FRAC bit 0 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 2 PLL[1]: STARTUP_WAIT PLL[1]: MMCM_DRP[116] bit 3 PLL[1]: GTS_WAIT - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[116] bit 0 PLL[1]: ENABLE PLL[1]: MMCM_DRP[116] bit 1 PLL[1]: CLOCK_HOLD - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 14 PLL[1]: MMCM_DRP[115] bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 12 PLL[1]: MMCM_DRP[115] bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 10 PLL[1]: MMCM_DRP[115] bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 8 PLL[1]: MMCM_DRP[115] bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 6 PLL[1]: MMCM_DRP[115] bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 4 PLL[1]: MMCM_DRP[115] bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 2 PLL[1]: MMCM_DRP[115] bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[115] bit 0 PLL[1]: MMCM_DRP[115] bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[114] bit 14 PLL[1]: MMCM_DRP[114] bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[114] bit 12 PLL[1]: MMCM_DRP[114] bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[114] bit 10 PLL[1]: MMCM_DRP[114] bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[114] bit 8 PLL[1]: MMCM_DRP[114] bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[114] bit 6 PLL[1]: MMCM_DRP[114] bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: invert CLKINSEL PLL[1]: MMCM_DRP[114] bit 4 PLL[1]: MMCM_DRP[114] bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: invert PSINCDEC PLL[1]: MMCM_DRP[114] bit 2 PLL[1]: invert PSEN PLL[1]: MMCM_DRP[114] bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: invert RST PLL[1]: MMCM_DRP[114] bit 0 PLL[1]: invert PWRDWN PLL[1]: MMCM_DRP[114] bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 14 PLL[1]: MMCM_DRP[113] bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 12 PLL[1]: MMCM_DRP[113] bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 10 PLL[1]: MMCM_DRP[113] bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 8 PLL[1]: MMCM_DRP[113] bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 6 PLL[1]: MMCM_DRP[113] bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 4 PLL[1]: MMCM_DRP[113] bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 2 PLL[1]: MMCM_DRP[113] bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[113] bit 0 PLL[1]: MMCM_DRP[113] bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 14 PLL[1]: MMCM_DRP[112] bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 12 PLL[1]: MMCM_DRP[112] bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 10 PLL[1]: MMCM_DRP[112] bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 8 PLL[1]: MMCM_DRP[112] bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 6 PLL[1]: MMCM_DRP[112] bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 4 PLL[1]: MMCM_DRP[112] bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 2 PLL[1]: MMCM_DRP[112] bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[112] bit 0 PLL[1]: MMCM_DRP[112] bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[37]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 14 PLL[1]: MMCM_DRP[127] bit 15 - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 12 PLL[1]: MMCM_DRP[127] bit 13 - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 10 PLL[1]: MMCM_DRP[127] bit 11 - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 8 PLL[1]: MMCM_DRP[127] bit 9 - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 6 PLL[1]: MMCM_DRP[127] bit 7 - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 4 PLL[1]: MMCM_DRP[127] bit 5 - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 2 PLL[1]: MMCM_DRP[127] bit 3 - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[127] bit 0 PLL[1]: MMCM_DRP[127] bit 1 - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 14 PLL[1]: MMCM_DRP[126] bit 15 - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 12 PLL[1]: MMCM_DRP[126] bit 13 - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 10 PLL[1]: MMCM_DRP[126] bit 11 - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 8 PLL[1]: MMCM_DRP[126] bit 9 - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 6 PLL[1]: MMCM_DRP[126] bit 7 - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 4 PLL[1]: MMCM_DRP[126] bit 5 - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 2 PLL[1]: MMCM_DRP[126] bit 3 - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[126] bit 0 PLL[1]: MMCM_DRP[126] bit 1 - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 14 PLL[1]: MMCM_DRP[125] bit 15 - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 12 PLL[1]: MMCM_DRP[125] bit 13 - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 10 PLL[1]: MMCM_DRP[125] bit 11 - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 8 PLL[1]: MMCM_DRP[125] bit 9 - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 6 PLL[1]: MMCM_DRP[125] bit 7 - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 4 PLL[1]: MMCM_DRP[125] bit 5 - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 2 PLL[1]: MMCM_DRP[125] bit 3 - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[125] bit 0 PLL[1]: MMCM_DRP[125] bit 1 - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 14 PLL[1]: MMCM_DRP[124] bit 15 - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 12 PLL[1]: MMCM_DRP[124] bit 13 - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 10 PLL[1]: MMCM_DRP[124] bit 11 - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 8 PLL[1]: MMCM_DRP[124] bit 9 - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 6 PLL[1]: MMCM_DRP[124] bit 7 - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 4 PLL[1]: MMCM_DRP[124] bit 5 - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 2 PLL[1]: MMCM_DRP[124] bit 3 - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[124] bit 0 PLL[1]: MMCM_DRP[124] bit 1 - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 14 PLL[1]: CONTROL_5 bit 14 PLL[1]: MMCM_DRP[123] bit 15 PLL[1]: CONTROL_5 bit 15 - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 12 PLL[1]: CONTROL_5 bit 12 PLL[1]: MMCM_DRP[123] bit 13 PLL[1]: CONTROL_5 bit 13 - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 10 PLL[1]: CONTROL_5 bit 10 PLL[1]: MMCM_DRP[123] bit 11 PLL[1]: CONTROL_5 bit 11 - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 8 PLL[1]: CONTROL_5 bit 8 PLL[1]: MMCM_DRP[123] bit 9 PLL[1]: CONTROL_5 bit 9 - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 6 PLL[1]: CONTROL_5 bit 6 PLL[1]: MMCM_DRP[123] bit 7 PLL[1]: CONTROL_5 bit 7 - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 4 PLL[1]: CONTROL_5 bit 4 PLL[1]: MMCM_DRP[123] bit 5 PLL[1]: CONTROL_5 bit 5 - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 2 PLL[1]: CONTROL_5 bit 2 PLL[1]: MMCM_DRP[123] bit 3 PLL[1]: CONTROL_5 bit 3 - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[123] bit 0 PLL[1]: CONTROL_5 bit 0 PLL[1]: MMCM_DRP[123] bit 1 PLL[1]: CONTROL_5 bit 1 - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 14 PLL[1]: CONTROL_4 bit 14 PLL[1]: MMCM_DRP[122] bit 15 PLL[1]: CONTROL_4 bit 15 - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 12 PLL[1]: CONTROL_4 bit 12 PLL[1]: MMCM_DRP[122] bit 13 PLL[1]: CONTROL_4 bit 13 - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 10 PLL[1]: CONTROL_4 bit 10 PLL[1]: MMCM_DRP[122] bit 11 PLL[1]: CONTROL_4 bit 11 - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 8 PLL[1]: CONTROL_4 bit 8 PLL[1]: MMCM_DRP[122] bit 9 PLL[1]: CONTROL_4 bit 9 - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 6 PLL[1]: CONTROL_4 bit 6 PLL[1]: MMCM_DRP[122] bit 7 PLL[1]: CONTROL_4 bit 7 - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 4 PLL[1]: CONTROL_4 bit 4 PLL[1]: MMCM_DRP[122] bit 5 PLL[1]: CONTROL_4 bit 5 - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 2 PLL[1]: CONTROL_4 bit 2 PLL[1]: MMCM_DRP[122] bit 3 PLL[1]: CONTROL_4 bit 3 - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[122] bit 0 PLL[1]: CONTROL_4 bit 0 PLL[1]: MMCM_DRP[122] bit 1 PLL[1]: CONTROL_4 bit 1 - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 14 PLL[1]: CONTROL_3 bit 14 PLL[1]: MMCM_DRP[121] bit 15 PLL[1]: CONTROL_3 bit 15 - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 12 PLL[1]: CONTROL_3 bit 12 PLL[1]: MMCM_DRP[121] bit 13 PLL[1]: CONTROL_3 bit 13 - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 10 PLL[1]: CONTROL_3 bit 10 PLL[1]: MMCM_DRP[121] bit 11 PLL[1]: CONTROL_3 bit 11 - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 8 PLL[1]: CONTROL_3 bit 8 PLL[1]: MMCM_DRP[121] bit 9 PLL[1]: CONTROL_3 bit 9 - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 6 PLL[1]: CONTROL_3 bit 6 PLL[1]: MMCM_DRP[121] bit 7 PLL[1]: CONTROL_3 bit 7 - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 4 PLL[1]: CONTROL_3 bit 4 PLL[1]: MMCM_DRP[121] bit 5 PLL[1]: CONTROL_3 bit 5 - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 2 PLL[1]: CONTROL_3 bit 2 PLL[1]: MMCM_DRP[121] bit 3 PLL[1]: CONTROL_3 bit 3 - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[121] bit 0 PLL[1]: CONTROL_3 bit 0 PLL[1]: MMCM_DRP[121] bit 1 PLL[1]: CONTROL_3 bit 1 - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 14 PLL[1]: CONTROL_2 bit 14 PLL[1]: MMCM_DRP[120] bit 15 PLL[1]: CONTROL_2 bit 15 - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 12 PLL[1]: CONTROL_2 bit 12 PLL[1]: MMCM_DRP[120] bit 13 PLL[1]: CONTROL_2 bit 13 - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 10 PLL[1]: CONTROL_2 bit 10 PLL[1]: MMCM_DRP[120] bit 11 PLL[1]: CONTROL_2 bit 11 - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 8 PLL[1]: CONTROL_2 bit 8 PLL[1]: MMCM_DRP[120] bit 9 PLL[1]: CONTROL_2 bit 9 - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 6 PLL[1]: CONTROL_2 bit 6 PLL[1]: MMCM_DRP[120] bit 7 PLL[1]: CONTROL_2 bit 7 - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 4 PLL[1]: CONTROL_2 bit 4 PLL[1]: MMCM_DRP[120] bit 5 PLL[1]: CONTROL_2 bit 5 - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 2 PLL[1]: CONTROL_2 bit 2 PLL[1]: MMCM_DRP[120] bit 3 PLL[1]: CONTROL_2 bit 3 - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - PLL[1]: MMCM_DRP[120] bit 0 PLL[1]: CONTROL_2 bit 0 PLL[1]: MMCM_DRP[120] bit 1 PLL[1]: CONTROL_2 bit 1 - - - - - - - - - -
virtex6 CMT rect MAIN[38]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex6 CMT rect MAIN[39]
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B60 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B59 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B58 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B57 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B56 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B55 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B54 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B53 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B50 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B49 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B48 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B47 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B46 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B45 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B43 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B42 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B41 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B39 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B38 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B37 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B36 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B35 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B34 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B33 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
virtex6 CMT rect HCLK
BitFrame
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37
B31 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].BUFH_INT_W[1] ← CELL[19].IMUX_CLK[1] - SPEC_INT: buffer CELL[20].MGT_CMT_W[9] ← IO_W[4].MGT_ROW[9] SPEC_INT: buffer CELL[20].HCLK_CMT_W[11] ← IO_W[4].HCLK_ROW[11] SPEC_INT: buffer CELL[20].MGT_CMT_E[9] ← IO_E[4].MGT_ROW[9] SPEC_INT: buffer CELL[20].HCLK_CMT_E[11] ← IO_E[4].HCLK_ROW[11] SPEC_INT: buffer CELL[20].BUFH_INT_E[1] ← CELL[20].IMUX_CLK[1] - - - - -
B30 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].BUFH_INT_W[0] ← CELL[19].IMUX_CLK[0] - SPEC_INT: buffer CELL[20].MGT_CMT_W[8] ← IO_W[4].MGT_ROW[8] SPEC_INT: buffer CELL[20].HCLK_CMT_W[10] ← IO_W[4].HCLK_ROW[10] SPEC_INT: buffer CELL[20].MGT_CMT_E[8] ← IO_E[4].MGT_ROW[8] SPEC_INT: buffer CELL[20].HCLK_CMT_E[10] ← IO_E[4].HCLK_ROW[10] SPEC_INT: buffer CELL[20].BUFH_INT_E[0] ← CELL[20].IMUX_CLK[0] - - - - -
B29 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[0] ← CELL[20].GCLK[0] - SPEC_INT: buffer CELL[20].MGT_CMT_W[7] ← IO_W[4].MGT_ROW[7] SPEC_INT: buffer CELL[20].HCLK_CMT_W[9] ← IO_W[4].HCLK_ROW[9] SPEC_INT: buffer CELL[20].MGT_CMT_E[7] ← IO_E[4].MGT_ROW[7] SPEC_INT: buffer CELL[20].HCLK_CMT_E[9] ← IO_E[4].HCLK_ROW[9] SPEC_INT: buffer CELL[20].GCLK_CMT[15] ← CELL[20].GCLK[15] - - - - -
B28 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[2] ← CELL[20].GCLK[2] - SPEC_INT: buffer CELL[20].MGT_CMT_W[6] ← IO_W[4].MGT_ROW[6] SPEC_INT: buffer CELL[20].HCLK_CMT_W[8] ← IO_W[4].HCLK_ROW[8] SPEC_INT: buffer CELL[20].MGT_CMT_E[6] ← IO_E[4].MGT_ROW[6] SPEC_INT: buffer CELL[20].HCLK_CMT_E[8] ← IO_E[4].HCLK_ROW[8] SPEC_INT: buffer CELL[20].GCLK_CMT[13] ← CELL[20].GCLK[13] - - - - -
B27 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[4] ← CELL[20].GCLK[4] - SPEC_INT: buffer CELL[20].CCIO_CMT_W[3] ← IO_W[7].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_W[7] ← IO_W[4].HCLK_ROW[7] SPEC_INT: buffer CELL[20].CCIO_CMT_E[3] ← IO_E[7].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_E[7] ← IO_E[4].HCLK_ROW[7] SPEC_INT: buffer CELL[20].GCLK_CMT[11] ← CELL[20].GCLK[11] - - - - -
B26 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[6] ← CELL[20].GCLK[6] - SPEC_INT: buffer CELL[20].CCIO_CMT_W[2] ← IO_W[5].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_W[6] ← IO_W[4].HCLK_ROW[6] SPEC_INT: buffer CELL[20].CCIO_CMT_E[2] ← IO_E[5].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_E[6] ← IO_E[4].HCLK_ROW[6] SPEC_INT: buffer CELL[20].GCLK_CMT[9] ← CELL[20].GCLK[9] - - - - -
B25 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[8] ← CELL[20].GCLK[8] - SPEC_INT: buffer CELL[20].CCIO_CMT_W[1] ← IO_W[3].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_W[5] ← IO_W[4].HCLK_ROW[5] SPEC_INT: buffer CELL[20].CCIO_CMT_E[1] ← IO_E[3].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_E[5] ← IO_E[4].HCLK_ROW[5] SPEC_INT: buffer CELL[20].GCLK_CMT[7] ← CELL[20].GCLK[7] - - - - -
B24 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[10] ← CELL[20].GCLK[10] - SPEC_INT: buffer CELL[20].CCIO_CMT_W[0] ← IO_W[1].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_W[4] ← IO_W[4].HCLK_ROW[4] SPEC_INT: buffer CELL[20].CCIO_CMT_E[0] ← IO_E[1].OUT_CLKPAD SPEC_INT: buffer CELL[20].HCLK_CMT_E[4] ← IO_E[4].HCLK_ROW[4] SPEC_INT: buffer CELL[20].GCLK_CMT[5] ← CELL[20].GCLK[5] - - - - -
B23 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[12] ← CELL[20].GCLK[12] - SPEC_INT: buffer CELL[20].MGT_CMT_W[5] ← IO_W[4].MGT_ROW[5] SPEC_INT: buffer CELL[20].HCLK_CMT_W[3] ← IO_W[4].HCLK_ROW[3] SPEC_INT: buffer CELL[20].MGT_CMT_E[5] ← IO_E[4].MGT_ROW[5] SPEC_INT: buffer CELL[20].HCLK_CMT_E[3] ← IO_E[4].HCLK_ROW[3] SPEC_INT: buffer CELL[20].GCLK_CMT[3] ← CELL[20].GCLK[3] - - - - -
B22 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[14] ← CELL[20].GCLK[14] - SPEC_INT: buffer CELL[20].MGT_CMT_W[4] ← IO_W[4].MGT_ROW[4] SPEC_INT: buffer CELL[20].HCLK_CMT_W[2] ← IO_W[4].HCLK_ROW[2] SPEC_INT: buffer CELL[20].MGT_CMT_E[4] ← IO_E[4].MGT_ROW[4] SPEC_INT: buffer CELL[20].HCLK_CMT_E[2] ← IO_E[4].HCLK_ROW[2] SPEC_INT: buffer CELL[20].GCLK_CMT[1] ← CELL[20].GCLK[1] - - - - -
B21 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[30] ← CELL[20].GCLK[30] - SPEC_INT: buffer CELL[20].GIOB_CMT[6] ← CELL[20].GIOB[6] SPEC_INT: buffer CELL[20].HCLK_CMT_W[1] ← IO_W[4].HCLK_ROW[1] SPEC_INT: buffer CELL[20].GIOB_CMT[7] ← CELL[20].GIOB[7] SPEC_INT: buffer CELL[20].HCLK_CMT_E[1] ← IO_E[4].HCLK_ROW[1] SPEC_INT: buffer CELL[20].GCLK_CMT[17] ← CELL[20].GCLK[17] - - - - -
B20 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[28] ← CELL[20].GCLK[28] - SPEC_INT: buffer CELL[20].GIOB_CMT[4] ← CELL[20].GIOB[4] SPEC_INT: buffer CELL[20].HCLK_CMT_W[0] ← IO_W[4].HCLK_ROW[0] SPEC_INT: buffer CELL[20].GIOB_CMT[5] ← CELL[20].GIOB[5] SPEC_INT: buffer CELL[20].HCLK_CMT_E[0] ← IO_E[4].HCLK_ROW[0] SPEC_INT: buffer CELL[20].GCLK_CMT[19] ← CELL[20].GCLK[19] - - - - -
B19 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[26] ← CELL[20].GCLK[26] - SPEC_INT: buffer CELL[20].GIOB_CMT[2] ← CELL[20].GIOB[2] SPEC_INT: buffer CELL[20].RCLK_CMT_W[5] ← IO_W[4].RCLK_ROW[5] SPEC_INT: buffer CELL[20].GIOB_CMT[3] ← CELL[20].GIOB[3] SPEC_INT: buffer CELL[20].RCLK_CMT_E[5] ← IO_E[4].RCLK_ROW[5] SPEC_INT: buffer CELL[20].GCLK_CMT[21] ← CELL[20].GCLK[21] - - - - -
B18 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[24] ← CELL[20].GCLK[24] - SPEC_INT: buffer CELL[20].GIOB_CMT[0] ← CELL[20].GIOB[0] SPEC_INT: buffer CELL[20].RCLK_CMT_W[4] ← IO_W[4].RCLK_ROW[4] SPEC_INT: buffer CELL[20].GIOB_CMT[1] ← CELL[20].GIOB[1] SPEC_INT: buffer CELL[20].RCLK_CMT_E[4] ← IO_E[4].RCLK_ROW[4] SPEC_INT: buffer CELL[20].GCLK_CMT[23] ← CELL[20].GCLK[23] - - - - -
B17 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[22] ← CELL[20].GCLK[22] - SPEC_INT: buffer CELL[20].MGT_CMT_W[3] ← IO_W[4].MGT_ROW[3] SPEC_INT: buffer CELL[20].RCLK_CMT_W[3] ← IO_W[4].RCLK_ROW[3] SPEC_INT: buffer CELL[20].MGT_CMT_E[3] ← IO_E[4].MGT_ROW[3] SPEC_INT: buffer CELL[20].RCLK_CMT_E[3] ← IO_E[4].RCLK_ROW[3] SPEC_INT: buffer CELL[20].GCLK_CMT[25] ← CELL[20].GCLK[25] - - - - -
B16 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[20] ← CELL[20].GCLK[20] - SPEC_INT: buffer CELL[20].MGT_CMT_W[2] ← IO_W[4].MGT_ROW[2] SPEC_INT: buffer CELL[20].RCLK_CMT_W[2] ← IO_W[4].RCLK_ROW[2] SPEC_INT: buffer CELL[20].MGT_CMT_E[2] ← IO_E[4].MGT_ROW[2] SPEC_INT: buffer CELL[20].RCLK_CMT_E[2] ← IO_E[4].RCLK_ROW[2] SPEC_INT: buffer CELL[20].GCLK_CMT[27] ← CELL[20].GCLK[27] - - - - -
B15 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[18] ← CELL[20].GCLK[18] - SPEC_INT: buffer CELL[20].MGT_CMT_W[1] ← IO_W[4].MGT_ROW[1] SPEC_INT: buffer CELL[20].RCLK_CMT_W[1] ← IO_W[4].RCLK_ROW[1] SPEC_INT: buffer CELL[20].MGT_CMT_E[1] ← IO_E[4].MGT_ROW[1] SPEC_INT: buffer CELL[20].RCLK_CMT_E[1] ← IO_E[4].RCLK_ROW[1] SPEC_INT: buffer CELL[20].GCLK_CMT[29] ← CELL[20].GCLK[29] - - - - -
B14 - - - - - - - - - - - - - - - - - - - - - - - - - - SPEC_INT: buffer CELL[20].GCLK_CMT[16] ← CELL[20].GCLK[16] - SPEC_INT: buffer CELL[20].MGT_CMT_W[0] ← IO_W[4].MGT_ROW[0] SPEC_INT: buffer CELL[20].RCLK_CMT_W[0] ← IO_W[4].RCLK_ROW[0] SPEC_INT: buffer CELL[20].MGT_CMT_E[0] ← IO_E[4].MGT_ROW[0] SPEC_INT: buffer CELL[20].RCLK_CMT_E[0] ← IO_E[4].RCLK_ROW[0] SPEC_INT: buffer CELL[20].GCLK_CMT[31] ← CELL[20].GCLK[31] - - - - -
B13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
B0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Tables

Table PLL_MULT

virtex6 table PLL_MULT
Row PLL_CP_LOW PLL_CP_HIGH PLL_CP_SS PLL_RES_LOW PLL_RES_HIGH PLL_RES_SS PLL_LFHF_LOW PLL_LFHF_HIGH PLL_LFHF_SS LOCK_REF_DLY LOCK_FB_DLY LOCK_CNT LOCK_SAT_HIGH UNLOCK_CNT
MMCM_1 0b0001 0b0101 - 0b0111 0b1111 - 0b11 0b00 - 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
MMCM_2 0b0001 0b1111 - 0b0101 0b1111 - 0b11 0b00 - 0b00110 0b00110 0b1111101000 0b1111101001 0b0000000001
MMCM_3 0b0001 0b1111 - 0b1110 0b1101 - 0b11 0b00 - 0b01000 0b01000 0b1111101000 0b1111101001 0b0000000001
MMCM_4 0b0001 0b1111 - 0b0110 0b1001 - 0b11 0b00 - 0b01011 0b01011 0b1111101000 0b1111101001 0b0000000001
MMCM_5 0b0001 0b1111 - 0b1010 0b1110 - 0b11 0b00 - 0b01110 0b01110 0b1111101000 0b1111101001 0b0000000001
MMCM_6 0b0001 0b1111 - 0b1100 0b0001 - 0b11 0b00 - 0b10001 0b10001 0b1111101000 0b1111101001 0b0000000001
MMCM_7 0b0001 0b1111 - 0b1100 0b0001 - 0b11 0b00 - 0b10011 0b10011 0b1111101000 0b1111101001 0b0000000001
MMCM_8 0b0001 0b1111 - 0b1100 0b0110 - 0b11 0b00 - 0b10110 0b10110 0b1111101000 0b1111101001 0b0000000001
MMCM_9 0b0001 0b1111 - 0b1100 0b1010 - 0b11 0b00 - 0b11001 0b11001 0b1111101000 0b1111101001 0b0000000001
MMCM_10 0b0001 0b1111 - 0b0010 0b1010 - 0b11 0b00 - 0b11100 0b11100 0b1111101000 0b1111101001 0b0000000001
MMCM_11 0b0001 0b1111 - 0b0010 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b1110000100 0b1111101001 0b0000000001
MMCM_12 0b0001 0b1110 - 0b0010 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1100111001 0b1111101001 0b0000000001
MMCM_13 0b0010 0b1111 - 0b1100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1011101110 0b1111101001 0b0000000001
MMCM_14 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1010111100 0b1111101001 0b0000000001
MMCM_15 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1010001010 0b1111101001 0b0000000001
MMCM_16 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1001110001 0b1111101001 0b0000000001
MMCM_17 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1000111111 0b1111101001 0b0000000001
MMCM_18 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1000100110 0b1111101001 0b0000000001
MMCM_19 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b1000001101 0b1111101001 0b0000000001
MMCM_20 0b0001 0b1111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0111110100 0b1111101001 0b0000000001
MMCM_21 0b0001 0b1110 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0111011011 0b1111101001 0b0000000001
MMCM_22 0b0001 0b1110 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0111000010 0b1111101001 0b0000000001
MMCM_23 0b0001 0b1110 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0110101001 0b1111101001 0b0000000001
MMCM_24 0b0001 0b1111 - 0b1000 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
MMCM_25 0b0001 0b1101 - 0b1000 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0110010000 0b1111101001 0b0000000001
MMCM_26 0b0001 0b1100 - 0b1000 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0101110111 0b1111101001 0b0000000001
MMCM_27 0b0001 0b1101 - 0b1000 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
MMCM_28 0b0001 0b1101 - 0b1000 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0101011110 0b1111101001 0b0000000001
MMCM_29 0b0001 0b1111 - 0b1000 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
MMCM_30 0b0001 0b1111 - 0b1000 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b0101000101 0b1111101001 0b0000000001
MMCM_31 0b0001 0b1111 - 0b1000 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_32 0b0001 0b0111 - 0b1000 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_33 0b0001 0b1100 - 0b1000 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0100101100 0b1111101001 0b0000000001
MMCM_34 0b0001 0b1100 - 0b1000 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_35 0b0001 0b1110 - 0b1000 0b1010 - 0b11 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_36 0b0001 0b0110 - 0b1000 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0100010011 0b1111101001 0b0000000001
MMCM_37 0b0001 0b0110 - 0b1000 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_38 0b0010 0b0110 - 0b0100 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_39 0b0010 0b0111 - 0b0100 0b1100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_40 0b0010 0b0110 - 0b0100 0b0010 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_41 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_42 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_43 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_44 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_45 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_46 0b0010 0b0100 - 0b0100 0b0100 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_47 0b0010 0b0011 - 0b0100 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_48 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_49 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_50 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_51 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_52 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_53 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_54 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_55 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_56 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_57 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_58 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_59 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_60 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_61 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_62 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_63 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001
MMCM_64 0b0010 0b0011 - 0b1000 0b1000 - 0b11 0b00 - 0b11111 0b11111 0b0011111010 0b1111101001 0b0000000001

Device data pll-in-dly-set

virtex6 device data pll-in-dly-set
Device PLL_V6_IN_DLY_SET
xc6vlx760 0b11111
xc6vlx760l 0b11111
xc6vlx75t 0b11000
xc6vlx75tl 0b11000
xc6vcx75t 0b11000
xc6vlx130t 0b11000
xq6vlx130t 0b11000
xc6vlx130tl 0b11000
xq6vlx130tl 0b11000
xc6vcx130t 0b11000
xc6vlx195t 0b11000
xc6vlx195tl 0b11000
xc6vcx195t 0b11000
xc6vlx240t 0b11000
xq6vlx240t 0b11000
xc6vlx240tl 0b11000
xq6vlx240tl 0b11000
xc6vcx240t 0b11000
xc6vlx365t 0b11000
xc6vlx365tl 0b11000
xc6vlx550t 0b11000
xq6vlx550t 0b11000
xc6vlx550tl 0b11000
xq6vlx550tl 0b11000
xc6vsx315t 0b11000
xq6vsx315t 0b11000
xc6vsx315tl 0b11000
xq6vsx315tl 0b11000
xc6vsx475t 0b11000
xq6vsx475t 0b11000
xc6vsx475tl 0b11000
xq6vsx475tl 0b11000
xc6vhx250t 0b11000
xc6vhx255t 0b11000
xc6vhx380t 0b11000
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