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Input/Output

I/O banks and special functions

Virtex 6 devices have a very regular I/O bank structure. There are up to four I/O columns in the device:

  • outer left (sometimes present)
  • inner left (always present)
  • inner right (always present)
  • outer right (sometimes present)

These columns consist entirely of IO tiles, with one tile per two interconnect rows. Every tile contains two I/O pads: IOB0 and IOB1. IOB0 is located in the bottom row of the tile, while IOB1 is located in the top row. Every I/O bank consists of exactly one region, or 40 I/O pads. The banks are numbered as follows:

  • the bank in region c + i of outer left column (where c is the region containing the top half of the CFG tile) has number 15 + i
  • the bank in region c + i of inner left column has number 25 + i
  • the bank in region c + i of inner right column has number 35 + i
  • the bank in region c + i of outer right column has number 45 + i

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the "true" pin of the pair, while IOB0 is the "complemented" pin. Differential input and true differential output is supported on all pins of the device.

IOB1 pads in the 8 rows surrounding the HCLK row (that is, rows 17, 19, 21, 23) are considered "clock-capable". They can drive BUFIODQS buffers via dedicated connections. The ones in rows 19 and 21 can drive BUFR buffers in this and two surrounding regions, and are considered "multi-region clock capable", while the ones in rows 17 and 23 are considered "single-region clock capable". While Xilinx documentation also considers corresponding IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

There are 8 IOB1\ s that are considered "global clock-capable" and can drive BUFGCTRL global buffers via dedicated interconnect. They are:

  • bank 24 rows 37, 39
  • bank 25 rows 1, 3
  • bank 34 rows 37, 39
  • bank 35 rows 1, 3

The IOB0 in rows 10 and 30 of every region is capable of being used as a VREF pad.

Each bank has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

  • bank 24: rows 4-5
  • bank 34: rows 0-1
  • banks 15, 25, 35: rows 6-7
  • all other banks: rows 14-15

In parallel or SPI configuration modes, some I/O pads in banks 24 and 34 are borrowed for configuration use:

  • bank 24 row 6: CSO_B
  • bank 24 row 7: RS[0]
  • bank 24 row 8: RS[1]
  • bank 24 row 9: FWE_B
  • bank 24 row 10: FOE_B/MOSI
  • bank 24 row 11: FCS_B
  • bank 24 row 12: D[0]/FS[0]
  • bank 24 row 13: D[1]/FS[1]
  • bank 24 row 14: D[2]/FS[2]
  • bank 24 row 15: D[3]
  • bank 24 row 24: D[4]
  • bank 24 row 25: D[5]
  • bank 24 row 26: D[6]
  • bank 24 row 27: D[7]
  • bank 24 row 28: D[8]
  • bank 24 row 29: D[9]
  • bank 24 row 30: D[10]
  • bank 24 row 31: D[11]
  • bank 24 row 32: D[12]
  • bank 24 row 33: D[13]
  • bank 24 row 34: D[14]
  • bank 24 row 35: D[15]
  • bank 34 row 2: A[16]
  • bank 34 row 3: A[17]
  • bank 34 row 4: A[18]
  • bank 34 row 5: A[19]
  • bank 34 row 6: A[20]
  • bank 34 row 7: A[21]
  • bank 34 row 8: A[22]
  • bank 34 row 9: A[23]
  • bank 34 row 10: A[24]
  • bank 34 row 11: A[25]
  • bank 34 row 12: D[16]/A[0]
  • bank 34 row 13: D[17]/A[1]
  • bank 34 row 14: D[18]/A[2]
  • bank 34 row 15: D[19]/A[3]
  • bank 34 row 24: D[20]/A[4]
  • bank 34 row 25: D[21]/A[5]
  • bank 34 row 26: D[22]/A[6]
  • bank 34 row 27: D[23]/A[7]
  • bank 34 row 28: D[24]/A[8]
  • bank 34 row 29: D[25]/A[9]
  • bank 34 row 30: D[26]/A[10]
  • bank 34 row 31: D[27]/A[11]
  • bank 34 row 32: D[28]/A[12]
  • bank 34 row 33: D[29]/A[13]
  • bank 34 row 34: D[30]/A[14]
  • bank 34 row 35: D[31]/A[15]

The SYSMON present on the device can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. If the device has a outer left IO column, the IOBs are located in banks 15 and 35; otherwise, they are located in banks 25 and 35. The IOBs are in the following tiles:

  • VP0/VN0: bank 35 rows 34-35
  • VP1/VN1: bank 35 rows 32-33
  • VP2/VN2: bank 35 rows 28-29
  • VP3/VN3: bank 35 rows 26-27
  • VP4/VN4: bank 35 rows 24-25
  • VP5/VN5: bank 35 rows 14-15
  • VP6/VN6: bank 35 rows 12-13
  • VP7/VN7: bank 35 rows 8-9
  • VP8/VN8: bank 15/25 rows 34-35
  • VP9/VN9: bank 15/25 rows 32-33
  • VP10/VN10: bank 15/25 rows 28-29
  • VP11/VN11: bank 15/25 rows 26-27
  • VP12/VN12: bank 15/25 rows 24-25
  • VP13/VN13: bank 15/25 rows 14-15
  • VP14/VN14: bank 15/25 rows 12-13
  • VP15/VN15: bank 15/25 rows 8-9

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

  • CCLK
  • CSI_B
  • DIN
  • DONE
  • DOUT_BUSY
  • HSWAPEN
  • INIT_B
  • M0, M1, M2
  • PROGRAM_B
  • RDWR_B
  • TCK, TDI, TDO, TMS

Tile IO

Cells: 2 IRIs: 0

Bel ILOGIC0

virtex6 IO bel ILOGIC0
PinDirectionWires
BITSLIPinputTCELL0:IMUX.IMUX8
CE1inputTCELL0:IMUX.IMUX10
CE2inputTCELL0:IMUX.IMUX11
CKINT0inputTCELL0:IMUX.IMUX14
CKINT1inputTCELL0:IMUX.IMUX15
CLKDIVinputTCELL0:IMUX.CLK0
DYNCLKDIVSELinputTCELL0:IMUX.IMUX12
DYNCLKSELinputTCELL0:IMUX.IMUX33
DYNOCLKSELinputTCELL0:IMUX.IMUX13
OoutputTCELL0:OUT18
Q1outputTCELL0:OUT19
Q2outputTCELL0:OUT23
Q3outputTCELL0:OUT20
Q4outputTCELL0:OUT16
Q5outputTCELL0:OUT17
Q6outputTCELL0:OUT21
SRinputTCELL0:IMUX.CTRL1

Bel ILOGIC1

virtex6 IO bel ILOGIC1
PinDirectionWires
BITSLIPinputTCELL1:IMUX.IMUX8
CE1inputTCELL1:IMUX.IMUX10
CE2inputTCELL1:IMUX.IMUX11
CKINT0inputTCELL1:IMUX.IMUX14
CKINT1inputTCELL1:IMUX.IMUX15
CLKDIVinputTCELL1:IMUX.CLK0
DYNCLKDIVSELinputTCELL1:IMUX.IMUX12
DYNCLKSELinputTCELL1:IMUX.IMUX33
DYNOCLKSELinputTCELL1:IMUX.IMUX13
OoutputTCELL1:OUT18
Q1outputTCELL1:OUT19
Q2outputTCELL1:OUT23
Q3outputTCELL1:OUT20
Q4outputTCELL1:OUT16
Q5outputTCELL1:OUT17
Q6outputTCELL1:OUT21
SRinputTCELL1:IMUX.CTRL1

Bel OLOGIC0

virtex6 IO bel OLOGIC0
PinDirectionWires
CLKDIVoutputTCELL0:TEST0
CLKDIV_CKINTinputTCELL0:IMUX.IMUX20
CLK_CKINTinputTCELL0:IMUX.IMUX21
CLK_MUXoutputTCELL0:TEST2
D1inputTCELL0:IMUX.IMUX42
D2inputTCELL0:IMUX.IMUX43
D3inputTCELL0:IMUX.IMUX44
D4inputTCELL0:IMUX.IMUX45
D5inputTCELL0:IMUX.IMUX46
D6inputTCELL0:IMUX.IMUX47
IOCLKGLITCHoutputTCELL0:OUT15
OCBEXTENDoutputTCELL0:OUT5
OCEinputTCELL0:IMUX.IMUX35
ODVinputTCELL0:IMUX.IMUX16
SRinputTCELL0:IMUX.CTRL0
T1inputTCELL0:IMUX.IMUX38
T2inputTCELL0:IMUX.IMUX39
T3inputTCELL0:IMUX.IMUX40
T4inputTCELL0:IMUX.IMUX41
TCEinputTCELL0:IMUX.IMUX34
TFB_BUFoutputTCELL0:OUT22
WCinputTCELL0:IMUX.IMUX17

Bel OLOGIC1

virtex6 IO bel OLOGIC1
PinDirectionWires
CLKDIVoutputTCELL1:TEST0
CLKDIV_CKINTinputTCELL1:IMUX.IMUX20
CLK_CKINTinputTCELL1:IMUX.IMUX21
CLK_MUXoutputTCELL1:TEST2
D1inputTCELL1:IMUX.IMUX42
D2inputTCELL1:IMUX.IMUX43
D3inputTCELL1:IMUX.IMUX44
D4inputTCELL1:IMUX.IMUX45
D5inputTCELL1:IMUX.IMUX46
D6inputTCELL1:IMUX.IMUX47
IOCLKGLITCHoutputTCELL1:OUT15
OCBEXTENDoutputTCELL1:OUT5
OCEinputTCELL1:IMUX.IMUX35
ODVinputTCELL1:IMUX.IMUX16
SRinputTCELL1:IMUX.CTRL0
T1inputTCELL1:IMUX.IMUX38
T2inputTCELL1:IMUX.IMUX39
T3inputTCELL1:IMUX.IMUX40
T4inputTCELL1:IMUX.IMUX41
TCEinputTCELL1:IMUX.IMUX34
TFB_BUFoutputTCELL1:OUT22
WCinputTCELL1:IMUX.IMUX17

Bel IODELAY0

virtex6 IO bel IODELAY0
PinDirectionWires
CinputTCELL0:IMUX.CLK0
CEinputTCELL0:IMUX.IMUX6
CINVCTRLinputTCELL0:IMUX.IMUX3
CNTVALUEIN0inputTCELL0:IMUX.IMUX1
CNTVALUEIN1inputTCELL0:IMUX.IMUX2
CNTVALUEIN2inputTCELL0:IMUX.IMUX0
CNTVALUEIN3inputTCELL0:IMUX.IMUX31
CNTVALUEIN4inputTCELL0:IMUX.IMUX36
CNTVALUEOUT0outputTCELL0:OUT10
CNTVALUEOUT1outputTCELL0:OUT14
CNTVALUEOUT2outputTCELL0:OUT13
CNTVALUEOUT3outputTCELL0:OUT9
CNTVALUEOUT4outputTCELL0:OUT12
DATAINinputTCELL0:IMUX.IMUX37
INCinputTCELL0:IMUX.IMUX7
RSTinputTCELL0:IMUX.IMUX5

Bel IODELAY1

virtex6 IO bel IODELAY1
PinDirectionWires
CinputTCELL1:IMUX.CLK0
CEinputTCELL1:IMUX.IMUX6
CINVCTRLinputTCELL1:IMUX.IMUX3
CNTVALUEIN0inputTCELL1:IMUX.IMUX1
CNTVALUEIN1inputTCELL1:IMUX.IMUX2
CNTVALUEIN2inputTCELL1:IMUX.IMUX0
CNTVALUEIN3inputTCELL1:IMUX.IMUX31
CNTVALUEIN4inputTCELL1:IMUX.IMUX36
CNTVALUEOUT0outputTCELL1:OUT10
CNTVALUEOUT1outputTCELL1:OUT14
CNTVALUEOUT2outputTCELL1:OUT13
CNTVALUEOUT3outputTCELL1:OUT9
CNTVALUEOUT4outputTCELL1:OUT12
DATAINinputTCELL1:IMUX.IMUX37
INCinputTCELL1:IMUX.IMUX7
RSTinputTCELL1:IMUX.IMUX5

Bel IOB0

virtex6 IO bel IOB0
PinDirectionWires
DIFF_TERM_INT_ENinputTCELL1:IMUX.IMUX30
KEEPER_INT_ENinputTCELL0:IMUX.IMUX30
PD_INT_ENinputTCELL0:IMUX.IMUX18
PU_INT_ENinputTCELL0:IMUX.IMUX19

Bel IOB1

virtex6 IO bel IOB1
PinDirectionWires
KEEPER_INT_ENinputTCELL1:IMUX.IMUX25
PD_INT_ENinputTCELL1:IMUX.IMUX18
PU_INT_ENinputTCELL1:IMUX.IMUX19

Bel IOI

virtex6 IO bel IOI
PinDirectionWires

Bel wires

virtex6 IO bel wires
WirePins
TCELL0:IMUX.CLK0ILOGIC0.CLKDIV, IODELAY0.C
TCELL0:IMUX.CTRL0OLOGIC0.SR
TCELL0:IMUX.CTRL1ILOGIC0.SR
TCELL0:IMUX.IMUX0IODELAY0.CNTVALUEIN2
TCELL0:IMUX.IMUX1IODELAY0.CNTVALUEIN0
TCELL0:IMUX.IMUX2IODELAY0.CNTVALUEIN1
TCELL0:IMUX.IMUX3IODELAY0.CINVCTRL
TCELL0:IMUX.IMUX5IODELAY0.RST
TCELL0:IMUX.IMUX6IODELAY0.CE
TCELL0:IMUX.IMUX7IODELAY0.INC
TCELL0:IMUX.IMUX8ILOGIC0.BITSLIP
TCELL0:IMUX.IMUX10ILOGIC0.CE1
TCELL0:IMUX.IMUX11ILOGIC0.CE2
TCELL0:IMUX.IMUX12ILOGIC0.DYNCLKDIVSEL
TCELL0:IMUX.IMUX13ILOGIC0.DYNOCLKSEL
TCELL0:IMUX.IMUX14ILOGIC0.CKINT0
TCELL0:IMUX.IMUX15ILOGIC0.CKINT1
TCELL0:IMUX.IMUX16OLOGIC0.ODV
TCELL0:IMUX.IMUX17OLOGIC0.WC
TCELL0:IMUX.IMUX18IOB0.PD_INT_EN
TCELL0:IMUX.IMUX19IOB0.PU_INT_EN
TCELL0:IMUX.IMUX20OLOGIC0.CLKDIV_CKINT
TCELL0:IMUX.IMUX21OLOGIC0.CLK_CKINT
TCELL0:IMUX.IMUX30IOB0.KEEPER_INT_EN
TCELL0:IMUX.IMUX31IODELAY0.CNTVALUEIN3
TCELL0:IMUX.IMUX33ILOGIC0.DYNCLKSEL
TCELL0:IMUX.IMUX34OLOGIC0.TCE
TCELL0:IMUX.IMUX35OLOGIC0.OCE
TCELL0:IMUX.IMUX36IODELAY0.CNTVALUEIN4
TCELL0:IMUX.IMUX37IODELAY0.DATAIN
TCELL0:IMUX.IMUX38OLOGIC0.T1
TCELL0:IMUX.IMUX39OLOGIC0.T2
TCELL0:IMUX.IMUX40OLOGIC0.T3
TCELL0:IMUX.IMUX41OLOGIC0.T4
TCELL0:IMUX.IMUX42OLOGIC0.D1
TCELL0:IMUX.IMUX43OLOGIC0.D2
TCELL0:IMUX.IMUX44OLOGIC0.D3
TCELL0:IMUX.IMUX45OLOGIC0.D4
TCELL0:IMUX.IMUX46OLOGIC0.D5
TCELL0:IMUX.IMUX47OLOGIC0.D6
TCELL0:OUT5OLOGIC0.OCBEXTEND
TCELL0:OUT9IODELAY0.CNTVALUEOUT3
TCELL0:OUT10IODELAY0.CNTVALUEOUT0
TCELL0:OUT12IODELAY0.CNTVALUEOUT4
TCELL0:OUT13IODELAY0.CNTVALUEOUT2
TCELL0:OUT14IODELAY0.CNTVALUEOUT1
TCELL0:OUT15OLOGIC0.IOCLKGLITCH
TCELL0:OUT16ILOGIC0.Q4
TCELL0:OUT17ILOGIC0.Q5
TCELL0:OUT18ILOGIC0.O
TCELL0:OUT19ILOGIC0.Q1
TCELL0:OUT20ILOGIC0.Q3
TCELL0:OUT21ILOGIC0.Q6
TCELL0:OUT22OLOGIC0.TFB_BUF
TCELL0:OUT23ILOGIC0.Q2
TCELL0:TEST0OLOGIC0.CLKDIV
TCELL0:TEST2OLOGIC0.CLK_MUX
TCELL1:IMUX.CLK0ILOGIC1.CLKDIV, IODELAY1.C
TCELL1:IMUX.CTRL0OLOGIC1.SR
TCELL1:IMUX.CTRL1ILOGIC1.SR
TCELL1:IMUX.IMUX0IODELAY1.CNTVALUEIN2
TCELL1:IMUX.IMUX1IODELAY1.CNTVALUEIN0
TCELL1:IMUX.IMUX2IODELAY1.CNTVALUEIN1
TCELL1:IMUX.IMUX3IODELAY1.CINVCTRL
TCELL1:IMUX.IMUX5IODELAY1.RST
TCELL1:IMUX.IMUX6IODELAY1.CE
TCELL1:IMUX.IMUX7IODELAY1.INC
TCELL1:IMUX.IMUX8ILOGIC1.BITSLIP
TCELL1:IMUX.IMUX10ILOGIC1.CE1
TCELL1:IMUX.IMUX11ILOGIC1.CE2
TCELL1:IMUX.IMUX12ILOGIC1.DYNCLKDIVSEL
TCELL1:IMUX.IMUX13ILOGIC1.DYNOCLKSEL
TCELL1:IMUX.IMUX14ILOGIC1.CKINT0
TCELL1:IMUX.IMUX15ILOGIC1.CKINT1
TCELL1:IMUX.IMUX16OLOGIC1.ODV
TCELL1:IMUX.IMUX17OLOGIC1.WC
TCELL1:IMUX.IMUX18IOB1.PD_INT_EN
TCELL1:IMUX.IMUX19IOB1.PU_INT_EN
TCELL1:IMUX.IMUX20OLOGIC1.CLKDIV_CKINT
TCELL1:IMUX.IMUX21OLOGIC1.CLK_CKINT
TCELL1:IMUX.IMUX25IOB1.KEEPER_INT_EN
TCELL1:IMUX.IMUX30IOB0.DIFF_TERM_INT_EN
TCELL1:IMUX.IMUX31IODELAY1.CNTVALUEIN3
TCELL1:IMUX.IMUX33ILOGIC1.DYNCLKSEL
TCELL1:IMUX.IMUX34OLOGIC1.TCE
TCELL1:IMUX.IMUX35OLOGIC1.OCE
TCELL1:IMUX.IMUX36IODELAY1.CNTVALUEIN4
TCELL1:IMUX.IMUX37IODELAY1.DATAIN
TCELL1:IMUX.IMUX38OLOGIC1.T1
TCELL1:IMUX.IMUX39OLOGIC1.T2
TCELL1:IMUX.IMUX40OLOGIC1.T3
TCELL1:IMUX.IMUX41OLOGIC1.T4
TCELL1:IMUX.IMUX42OLOGIC1.D1
TCELL1:IMUX.IMUX43OLOGIC1.D2
TCELL1:IMUX.IMUX44OLOGIC1.D3
TCELL1:IMUX.IMUX45OLOGIC1.D4
TCELL1:IMUX.IMUX46OLOGIC1.D5
TCELL1:IMUX.IMUX47OLOGIC1.D6
TCELL1:OUT5OLOGIC1.OCBEXTEND
TCELL1:OUT9IODELAY1.CNTVALUEOUT3
TCELL1:OUT10IODELAY1.CNTVALUEOUT0
TCELL1:OUT12IODELAY1.CNTVALUEOUT4
TCELL1:OUT13IODELAY1.CNTVALUEOUT2
TCELL1:OUT14IODELAY1.CNTVALUEOUT1
TCELL1:OUT15OLOGIC1.IOCLKGLITCH
TCELL1:OUT16ILOGIC1.Q4
TCELL1:OUT17ILOGIC1.Q5
TCELL1:OUT18ILOGIC1.O
TCELL1:OUT19ILOGIC1.Q1
TCELL1:OUT20ILOGIC1.Q3
TCELL1:OUT21ILOGIC1.Q6
TCELL1:OUT22OLOGIC1.TFB_BUF
TCELL1:OUT23ILOGIC1.Q2
TCELL1:TEST0OLOGIC1.CLKDIV
TCELL1:TEST2OLOGIC1.CLK_MUX

Bitstream

virtex6 IO bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
63 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:RANK12_DLY ILOGIC0:IFF_SR_USED - - - - ILOGIC0:D_EMU_OPTION[0] ILOGIC0:D_EMU_OPTION[1] - - OLOGIC0:TMUX[0] OLOGIC0:INIT_DLY_CNT[3] - - - IOB0:IBUF_MODE[2]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:NUM_CE[0] ILOGIC0:RANK23_DLY - - - - ILOGIC0:D_EMU_OPTION[2] - - - OLOGIC0:TMUX[4] - - - IOB0:DCI_T -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:READBACK_I ILOGIC0:IFF_REV_USED - - - - - - OLOGIC0:MUX.CLKDIVB[8] OLOGIC0:MUX.CLKDIVB[4] OLOGIC0:INIT_FIFO_RESET[8] OLOGIC0:TMUX[3] - - - ~IOB0:NDRIVE[0]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_CE[1] - - - - - - - - - OLOGIC0:TMUX[2] IODELAY0:EXTRA_DELAY - - - -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_CE[0] - - - - - - - - OLOGIC0:TMUX[1] OLOGIC0:INIT_DLY_CNT[1] - - - -
58 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[5] - - - - - OLOGIC0:OMUX[0] OLOGIC0:OMUX[3] OLOGIC0:MUX.CLKDIVB[2] OLOGIC0:MUX.CLKDIVB[3] - - - - IOB0:DCI_MISC[0] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[5] - - - - - OLOGIC0:OMUX[4] - - - - ~IODELAY0:IDELAY_VALUE_CUR[4] - - IOB0:DCI_MISC[1]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[5] - - - - - ~OLOGIC0:INV.CLK2 - OLOGIC0:MUX.CLKDIVB[7] OLOGIC0:MUX.CLKDIVB[5] OLOGIC0:INIT_FIFO_RESET[11] OLOGIC0:INIT_ORANK2_PARTIAL[3] - - ~IOB0:PDRIVE[0] -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_SRVAL ~ILOGIC0:IFF_LATCH - - - - OLOGIC0:INV.CLKDIV ~OLOGIC0:INV.CLK1 OLOGIC0:MUX.CLKDIVB[1] - - OLOGIC0:INIT_ORANK2_PARTIAL[2] - - - IOB0:LVDS[8]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_SR_SYNC ILOGIC0:SERDES - - - - OLOGIC0:OFF_SR_USED OLOGIC0:DATA_WIDTH[4] - OLOGIC0:MUX.CLKDIVB[0] - OLOGIC0:INIT_DLY_CNT[6] - - ~IOB0:DCIUPDATEMODE_ASREQUIRED -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DDR_CLK_EDGE[0] ~ILOGIC0:IFF2_SRVAL - - - - OLOGIC0:DATA_WIDTH[7] OLOGIC0:DATA_WIDTH[0] OLOGIC0:MUX.CLKB[6] OLOGIC0:MUX.CLKDIVB[6] OLOGIC0:INIT_ORANK2_PARTIAL[1] IODELAY0:ENABLE - - - -
52 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF1_INIT - - - - - OLOGIC0:DATA_WIDTH[2] OLOGIC0:DATA_WIDTH[6] OLOGIC0:MUX.CLKB[3] - OLOGIC0:INIT_ORANK2_PARTIAL[0] - IODELAY0:DELAY_TYPE[4] - ~IOB0:PDRIVE[1] -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[4] - - - - OLOGIC0:DATA_WIDTH[5] OLOGIC0:DATA_WIDTH[3] - - - - ~IODELAY0:IDELAY_VALUE_CUR[3] - - IOB0:OUTPUT_DELAY
50 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[4] - - - - - ~OLOGIC0:INV.T1 OLOGIC0:DATA_WIDTH[1] OLOGIC0:MUX.CLKB[9] OLOGIC0:MUX.CLKB[10] OLOGIC0:TFF_SR_USED OLOGIC0:INIT_FIFO_RESET[4] IODELAY0:DELAY_SRC[1] - IOB0:LVDS[7] -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[4] - - - - ~OLOGIC0:INV.T3 ~OLOGIC0:INV.T2 - - - OLOGIC0:TRISTATE_WIDTH[0] IODELAY0:DELAY_SRC[0] - - ~IOB0:NDRIVE[1]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[3] - - - - - OLOGIC0:INIT_TRANK1[3] ~OLOGIC0:INV.T4 OLOGIC0:MUX.CLKB[2] OLOGIC0:MUX.CLKB[4] OLOGIC0:TFF_SR_SYNC[1] - - - IOB0:PULL[2] -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF2_INIT - - - - - - - OLOGIC0:MUX.CLKB[0] OLOGIC0:INIT_DLY_CNT[7] - - - - IOB0:PULL[1]
46 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[3] - - - - - OLOGIC0:CLK_RATIO[0] - - - ~OLOGIC0:TFF_SRVAL[0] OLOGIC0:INIT_FIFO_ADDR[4] - - IOB0:PULL[0] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_INIT - - - - - OLOGIC0:CLK_RATIO[1] OLOGIC0:MUX.CLKB[8] - OLOGIC0:INIT_FIFO_RESET[12] IODELAY0:HIGH_PERFORMANCE_MODE - - - ~IOB0:PDRIVE[2]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[3] - - - - - OLOGIC0:CLK_RATIO[2] OLOGIC0:CLK_RATIO[3] - OLOGIC0:MUX.CLKB[7] OLOGIC0:MUX.CLKPERF[0] ~OLOGIC0:TFF_SRVAL[2] IODELAY0:DELAY_SRC[2] - IOB0:NSLEW[0] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[2] - - - - OLOGIC0:OFF_SR_SYNC[0] OLOGIC0:SELFHEAL - OLOGIC0:MUX.CLKB[5] - ~OLOGIC0:TFF_SRVAL[1] ~IODELAY0:IDELAY_VALUE_CUR[2] - - IOB0:NSLEW[4]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[2] - - - - - - OLOGIC0:INIT_TRANK1[2] OLOGIC0:MUX.CLKB[1] - OLOGIC0:INIT_DLY_CNT[9] - IODELAY0:DELAY_SRC[4] - ~IOB0:NDRIVE[2] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF3_SRVAL ~ILOGIC0:IFF4_INIT - - - - - - ILOGIC0:MUX.CLKB[6] - OLOGIC0:INIT_FIFO_ADDR[5] - IODELAY0:DELAY_SRC[3] - - IOB0:PDRIVE[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:IFF4_SRVAL ILOGIC0:DDR_CLK_EDGE[1] - - - - ~OLOGIC0:OFF_SRVAL[1] - - ILOGIC0:MUX.CLKB[3] OLOGIC0:ODELAY_USED - - - - -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[2] - - - - ~OLOGIC0:OFF_INIT - ILOGIC0:MUX.CLKB[9] ILOGIC0:MUX.CLKB[10] ~OLOGIC0:TFF_INIT OLOGIC0:INIT_FIFO_ADDR[6] - - - IOB0:PSLEW[0]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[1] - - - - - ~OLOGIC0:OFF_SRVAL[0] - ILOGIC0:MUX.CLKB[4] - OLOGIC0:OFF_SR_SYNC[3] - - - IOB0:LVDS[6] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[1] - - - - - OLOGIC0:INIT_TRANK1[1] ILOGIC0:MUX.CLKB[1] - - - ~IODELAY0:INV.DATAIN - - IOB0:PULL_DYNAMIC
36 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[1] - - - - - - ~OLOGIC0:OFF_SRVAL[2] - - - - - - IOB0:OMUX[0] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK1_PARTIAL[4] - - - - - - - ILOGIC0:MUX.CLKB[5] - - ~IODELAY0:IDELAY_VALUE_CUR[1] - - IOB0:OUTPUT_MISC[0]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_RATE[0] - - - - - - - ILOGIC0:MUX.CLKB[8] - - OLOGIC0:INIT_PIPE_DATA1[0] - - ~IOB0:NDRIVE[3] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_DELAY_ENABLE - - - - OLOGIC0:INIT_TRANK1[0] - - ILOGIC0:MUX.CLKB[7] - OLOGIC0:INIT_FIFO_RESET[7] - - - IOB0:LVDS[5]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:D_EMU - - - - - OLOGIC0:TFF_SR_SYNC[0] - ILOGIC0:MUX.CLKB[2] - - OLOGIC0:SERDES_MODE[0] - - IOB0:NSLEW[2] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:SERDES_MODE[0] ILOGIC0:BITSLIP_SYNC - - - - - OLOGIC0:SERDES ILOGIC0:MUX.CLKB[0] - - OLOGIC0:INIT_DLY_CNT[2] - - - IOB0:PSLEW[1]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK3[0] - - - - - - - - OLOGIC0:MUX.CLKDIV[4] - - - - IOB0:NSLEW[1] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK2[0] - - - - OLOGIC0:INIT_LOADCNT[3] - - - OLOGIC0:INIT_PIPE_DATA0[0] - - - - IOB0:OUTPUT_ENABLE[1]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INIT_BITSLIP[0] - - - - - OLOGIC0:INIT_PIPE_DATA0[6] - OLOGIC0:MUX.CLKDIV[6] - - OLOGIC0:INIT_FIFO_RESET[10] - - IOB0:OUTPUT_ENABLE[0] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK1_PARTIAL[3] - - - - OLOGIC0:INIT_ORANK1[5] - OLOGIC0:MUX.CLKDIV[2] OLOGIC0:MUX.CLKDIV[3] - - ~IODELAY0:IDELAY_VALUE_CUR[0] - - IOB0:PSLEW[2]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK1_PARTIAL[2] - - - - - - OLOGIC0:OMUX[1] - - OLOGIC0:INIT_PIPE_DATA0[1] OLOGIC0:INIT_PIPE_DATA1[1] IODELAY0:DELAY_TYPE[0] - ~IOB0:PDRIVE[4] -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_BITSLIPCNT[0] - - - - OLOGIC0:OMUX[2] OLOGIC0:INIT_PIPE_DATA1[6] OLOGIC0:MUX.CLKDIV[8] OLOGIC0:MUX.CLKDIV[5] OLOGIC0:INIT_DLY_CNT[0] - ~IODELAY0:INV.IDATAIN - - IOB0:OUTPUT_MISC[2]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INV.CLKDIV ~ILOGIC0:INV.CLK[2] - - - - OLOGIC0:INIT_PIPE_DATA1[7] OLOGIC0:INV.D1 OLOGIC0:MUX.CLKDIV[1] - - - - - IOB0:OUTPUT_MISC[1] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[3] ILOGIC0:DYN_CLK_INV_EN - - - - OLOGIC0:INIT_PIPE_DATA0[7] OLOGIC0:INIT_LOADCNT[2] OLOGIC0:MUX.CLKDIV[7] OLOGIC0:MUX.CLKDIV[0] OLOGIC0:DDR3_BYPASS OLOGIC0:DDR3_DATA - - - IOB0:LVDS[4]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.CLK[1] - - - - OLOGIC0:INIT_ORANK1[4] - OLOGIC0:MUX.CLK[6] - OLOGIC0:INIT_FIFO_RESET[5] ~OLOGIC0:INV.CLKPERF IODELAY0:INV.C - IOB0:LVDS[3] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[2] ILOGIC0:BITSLIP_ENABLE - - - - - - OLOGIC0:MUX.CLK[5] - OLOGIC0:INIT_FIFO_RESET[3] OLOGIC0:WC_DELAY IODELAY0:CINVCTRL_SEL - - IOB0:NDRIVE[4]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_BITSLIPCNT[1] - - - - - OLOGIC0:INV.D2 OLOGIC0:INIT_PIPE_DATA1[8] - - - OLOGIC0:INIT_FIFO_ADDR[0] IODELAY0:IDELAY_VALUE_INIT[0] - IOB0:PSLEW[3] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_BITSLIPCNT[2] - - - - OLOGIC0:INIT_LOADCNT[1] OLOGIC0:OFF_SR_SYNC[2] OLOGIC0:MUX.CLK[9] OLOGIC0:MUX.CLK[10] OLOGIC0:INIT_DLY_CNT[4] OLOGIC0:INIT_PIPE_DATA1[2] IODELAY0:IDELAY_VALUE_INIT[1] - - IOB0:DCI_MODE[2]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[1] - - - - - - OLOGIC0:MUX.CLK[4] - OLOGIC0:INIT_FIFO_ADDR[3] - IODELAY0:IDELAY_VALUE_INIT[2] - IOB0:LVDS[2] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DATA_WIDTH[0] ~ILOGIC0:INV.CLK[0] - - - - - OLOGIC0:INIT_PIPE_DATA0[8] OLOGIC0:MUX.CLK[2] - - OLOGIC0:INIT_PIPE_DATA0[2] IODELAY0:IDELAY_VALUE_INIT[3] - - IOB0:NSLEW[3]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[2] ~ILOGIC0:INV.OCLK1 - - - - - OLOGIC0:INIT_ORANK1[3] - - OLOGIC0:INIT_FIFO_RESET[0] - IODELAY0:IDELAY_VALUE_INIT[4] - - -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[0] - - - - - - OLOGIC0:INIT_PIPE_DATA0[10] - - OLOGIC0:INIT_PIPE_DATA1[4] - IODELAY0:DELAY_TYPE[1] - - -
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_OCLK_INV_EN[1] - - - - OLOGIC0:INV.D3 OLOGIC0:INIT_PIPE_DATA1[10] OLOGIC0:MUX.CLK[1] OLOGIC0:MUX.CLK[3] - OLOGIC0:INIT_FIFO_ADDR[1] IODELAY0:ALT_DELAY_VALUE[0] - IOB0:DCI_MODE[0] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:DYN_OCLK_INV_EN[0] ~ILOGIC0:INV.OCLK2 - - - - OLOGIC0:INIT_LOADCNT[0] OLOGIC0:INIT_PIPE_DATA1[9] OLOGIC0:MUX.CLK[7] OLOGIC0:MUX.CLK[8] - OLOGIC0:INIT_DLY_CNT[5] IODELAY0:ALT_DELAY_VALUE[1] - - IOB0:VR
12 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_BITSLIPCNT[3] - - - - - - - - - OLOGIC0:INIT_FIFO_ADDR[2] OLOGIC0:INIT_PIPE_DATA1[3] IODELAY0:ALT_DELAY_VALUE[2] - IOB0:DCI_MODE[1] -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:INV.D4 OLOGIC0:MUX.CLK[0] - OLOGIC0:INIT_PIPE_DATA0[4] - IODELAY0:ALT_DELAY_VALUE[3] - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:INTERFACE_TYPE[1] - - - - - OLOGIC0:INIT_ORANK1[2] - ILOGIC0:MUX.CLK[6] - OLOGIC0:INIT_FIFO_RESET[6] IODELAY0:ALT_DELAY_VALUE[4] - IOB0:PSLEW[4] -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:TSBYPASS_MUX[0] ILOGIC0:DYN_CLKDIV_INV_EN - - - - - OLOGIC0:INIT_PIPE_DATA1[11] ILOGIC0:MUX.CLK[2] ILOGIC0:MUX.CLK[4] - OLOGIC0:INIT_FIFO_RESET[1] IODELAY0:DELAY_TYPE[3] - - IOB0:OUTPUT_MISC[3]
8 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:I_TSBYPASS_ENABLE OLOGIC0:MISR_CLK_SELECT[1] - - - - OLOGIC0:INV.D5 - ILOGIC0:MUX.CLK[9] ILOGIC0:MUX.CLK[10] OLOGIC0:INIT_FIFO_ADDR[7] OLOGIC0:INIT_PIPE_DATA1[5] IODELAY0:DELAY_TYPE[2] - IOB0:LVDS[1] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_TSBYPASS_ENABLE OLOGIC0:MISR_CLK_SELECT[0] - - - - - - - ILOGIC0:MUX.CLK[5] OLOGIC0:INIT_FIFO_ADDR[9] - - - - IOB0:PDRIVE[5]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK1_PARTIAL[1] - - - - - - OLOGIC0:INIT_ORANK1[1] ILOGIC0:MUX.CLK[1] - OLOGIC0:INTERFACE_TYPE[0] - - - IOB0:NDRIVE[5] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INIT_RANK1_PARTIAL[0] - - - - OLOGIC0:INIT_PIPE_DATA0[9] OLOGIC0:INV.D6 - - OLOGIC0:INIT_FIFO_RESET[9] - - - - IOB0:LVDS[0]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC0:IFF_DELAY_ENABLE OLOGIC0:MISR_ENABLE - - - - - - - - OLOGIC0:INIT_FIFO_RESET[2] - - - IOB0:IBUF_MODE[4] -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:MISR_ENABLE_FDBK - - - - - - ILOGIC0:MUX.CLK[8] - - OLOGIC0:INIT_PIPE_DATA0[3] - - - IOB0:VREF_SYSMON
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:INIT_PIPE_DATA0[11] - - ILOGIC0:MUX.CLK[7] - OLOGIC0:INIT_FIFO_ADDR[8] - - IOB0:IBUF_MODE[3] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC0:INIT_ORANK1[0] ILOGIC0:MUX.CLK[3] - OLOGIC0:INIT_DLY_CNT[8] OLOGIC0:INIT_PIPE_DATA0[5] - - - IOB0:IBUF_MODE[1]
0 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC0:INV.D OLOGIC0:MISR_RESET - - - - - OLOGIC0:OFF_SR_SYNC[1] ILOGIC0:MUX.CLK[0] - OLOGIC0:INIT_FIFO_ADDR[10] - - - IOB0:IBUF_MODE[0] -
virtex6 IO bittile 1
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
63 - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_RESET ~ILOGIC1:INV.D - - - - OLOGIC1:OFF_SR_SYNC[1] - - ILOGIC1:MUX.CLK[0] - OLOGIC1:INIT_FIFO_ADDR[10] - - - IOB1:IBUF_MODE[0]
62 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:INIT_ORANK1[0] - - ILOGIC1:MUX.CLK[3] OLOGIC1:INIT_PIPE_DATA0[5] OLOGIC1:INIT_DLY_CNT[8] - - IOB1:IBUF_MODE[1] -
61 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:INIT_PIPE_DATA0[11] ILOGIC1:MUX.CLK[7] - OLOGIC1:INIT_FIFO_ADDR[8] - - - - IOB1:IBUF_MODE[3]
60 - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_ENABLE_FDBK - - - - - - - - ILOGIC1:MUX.CLK[8] OLOGIC1:INIT_PIPE_DATA0[3] - - - IOB1:VREF_SYSMON -
59 - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_ENABLE ILOGIC1:IFF_DELAY_ENABLE - - - - - - - - - OLOGIC1:INIT_FIFO_RESET[2] - - - IOB1:IBUF_MODE[4]
58 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK1_PARTIAL[0] - - - - - OLOGIC1:INV.D6 OLOGIC1:INIT_PIPE_DATA0[9] - - - OLOGIC1:INIT_FIFO_RESET[9] - - IOB1:LVDS[0] -
57 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK1_PARTIAL[1] - - - - OLOGIC1:INIT_ORANK1[1] - - ILOGIC1:MUX.CLK[1] - OLOGIC1:INTERFACE_TYPE[0] - - - IOB1:NDRIVE[5]
56 - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_CLK_SELECT[0] ILOGIC1:IFF_TSBYPASS_ENABLE - - - - - - ILOGIC1:MUX.CLK[5] - - OLOGIC1:INIT_FIFO_ADDR[9] - - IOB1:PDRIVE[5] -
55 - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:MISR_CLK_SELECT[1] ILOGIC1:I_TSBYPASS_ENABLE - - - - - OLOGIC1:INV.D5 ILOGIC1:MUX.CLK[10] ILOGIC1:MUX.CLK[9] OLOGIC1:INIT_PIPE_DATA1[5] OLOGIC1:INIT_FIFO_ADDR[7] - IODELAY1:DELAY_TYPE[2] - IOB1:LVDS[1]
54 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLKDIV_INV_EN ILOGIC1:TSBYPASS_MUX[0] - - - - OLOGIC1:INIT_PIPE_DATA1[11] - ILOGIC1:MUX.CLK[4] ILOGIC1:MUX.CLK[2] OLOGIC1:INIT_FIFO_RESET[1] - - IODELAY1:DELAY_TYPE[4] IOB1:OUTPUT_MISC[3] -
53 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[1] - - - - - OLOGIC1:INIT_ORANK1[2] - ILOGIC1:MUX.CLK[6] - OLOGIC1:INIT_FIFO_RESET[6] - - IODELAY1:ALT_DELAY_VALUE[4] - IOB1:PSLEW[4]
52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OLOGIC1:INV.D4 - - OLOGIC1:MUX.CLK[0] - OLOGIC1:INIT_PIPE_DATA0[4] - IODELAY1:ALT_DELAY_VALUE[3] - -
51 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_BITSLIPCNT[3] - - - - - - - - OLOGIC1:INIT_PIPE_DATA1[3] OLOGIC1:INIT_FIFO_ADDR[2] - IODELAY1:ALT_DELAY_VALUE[2] - IOB1:DCI_MODE[1]
50 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.OCLK2 ILOGIC1:DYN_OCLK_INV_EN[1] - - - - OLOGIC1:INIT_PIPE_DATA1[9] OLOGIC1:INIT_LOADCNT[0] OLOGIC1:MUX.CLK[8] OLOGIC1:MUX.CLK[7] OLOGIC1:INIT_DLY_CNT[5] - - IODELAY1:ALT_DELAY_VALUE[1] IOB1:VR -
49 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_OCLK_INV_EN[0] - - - - - OLOGIC1:INIT_PIPE_DATA1[10] OLOGIC1:INV.D3 OLOGIC1:MUX.CLK[3] OLOGIC1:MUX.CLK[1] OLOGIC1:INIT_FIFO_ADDR[1] - - IODELAY1:ALT_DELAY_VALUE[0] - IOB1:DCI_MODE[0]
48 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INTERFACE_TYPE[0] - - - - OLOGIC1:INIT_PIPE_DATA0[10] - - - - OLOGIC1:INIT_PIPE_DATA1[4] - IODELAY1:DELAY_TYPE[1] - -
47 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.OCLK1 ILOGIC1:INTERFACE_TYPE[2] - - - - OLOGIC1:INIT_ORANK1[3] - - - - OLOGIC1:INIT_FIFO_RESET[0] - IODELAY1:IDELAY_VALUE_INIT[4] - -
46 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.CLK[2] ILOGIC1:DATA_WIDTH[0] - - - - OLOGIC1:INIT_PIPE_DATA0[8] - - OLOGIC1:MUX.CLK[2] OLOGIC1:INIT_PIPE_DATA0[2] - - IODELAY1:IDELAY_VALUE_INIT[3] IOB1:NSLEW[3] -
45 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_WIDTH[1] - - - - - - - - OLOGIC1:MUX.CLK[4] - OLOGIC1:INIT_FIFO_ADDR[3] - IODELAY1:IDELAY_VALUE_INIT[2] - IOB1:LVDS[2]
44 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_BITSLIPCNT[2] - - - - - OLOGIC1:OFF_SR_SYNC[0] OLOGIC1:INIT_LOADCNT[1] OLOGIC1:MUX.CLK[10] OLOGIC1:MUX.CLK[9] OLOGIC1:INIT_PIPE_DATA1[2] OLOGIC1:INIT_DLY_CNT[4] - IODELAY1:IDELAY_VALUE_INIT[1] IOB1:DCI_MODE[2] -
43 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_BITSLIPCNT[1] - - - - OLOGIC1:INIT_PIPE_DATA1[8] OLOGIC1:INV.D2 - - OLOGIC1:INIT_FIFO_ADDR[0] - - IODELAY1:IDELAY_VALUE_INIT[0] - IOB1:PSLEW[3]
42 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:BITSLIP_ENABLE ILOGIC1:DATA_WIDTH[2] - - - - - - - OLOGIC1:MUX.CLK[5] OLOGIC1:WC_DELAY OLOGIC1:INIT_FIFO_RESET[3] - IODELAY1:CINVCTRL_SEL IOB1:NDRIVE[4] -
41 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.CLK[1] - - - - - - OLOGIC1:INIT_ORANK1[4] - OLOGIC1:MUX.CLK[6] ~OLOGIC1:INV.CLKPERF OLOGIC1:INIT_FIFO_RESET[5] - IODELAY1:INV.C - IOB1:LVDS[3]
40 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DYN_CLK_INV_EN ILOGIC1:DATA_WIDTH[3] - - - - OLOGIC1:INIT_LOADCNT[2] OLOGIC1:INIT_PIPE_DATA0[7] OLOGIC1:MUX.CLKDIV[0] OLOGIC1:MUX.CLKDIV[7] OLOGIC1:DDR3_DATA OLOGIC1:DDR3_BYPASS - - IOB1:LVDS[4] -
39 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INV.CLK[0] ILOGIC1:INV.CLKDIV - - - - OLOGIC1:INV.D1 OLOGIC1:INIT_PIPE_DATA1[7] - OLOGIC1:MUX.CLKDIV[1] - - - - - IOB1:OUTPUT_MISC[1]
38 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_BITSLIPCNT[0] - - - - - OLOGIC1:INIT_PIPE_DATA1[6] OLOGIC1:OMUX[2] OLOGIC1:MUX.CLKDIV[5] OLOGIC1:MUX.CLKDIV[8] - OLOGIC1:INIT_DLY_CNT[0] - ~IODELAY1:INV.IDATAIN IOB1:OUTPUT_MISC[2] -
37 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK1_PARTIAL[2] - - - - OLOGIC1:OMUX[1] - - - OLOGIC1:INIT_PIPE_DATA1[1] OLOGIC1:INIT_PIPE_DATA0[1] - IODELAY1:DELAY_TYPE[0] - ~IOB1:PDRIVE[4]
36 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK1_PARTIAL[3] - - - - - - OLOGIC1:INIT_ORANK1[5] OLOGIC1:MUX.CLKDIV[3] OLOGIC1:MUX.CLKDIV[2] - - - ~IODELAY1:IDELAY_VALUE_CUR[0] IOB1:PSLEW[2] -
35 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[0] - - - - - OLOGIC1:INIT_PIPE_DATA0[6] - OLOGIC1:MUX.CLKDIV[6] OLOGIC1:INIT_FIFO_RESET[10] - - - - IOB1:OUTPUT_ENABLE[1]
34 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[0] - - - - - - OLOGIC1:INIT_LOADCNT[3] - - - OLOGIC1:INIT_PIPE_DATA0[0] - - IOB1:OUTPUT_ENABLE[0] -
33 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[0] - - - - - - OLOGIC1:MUX.CLKDIV[4] - - - - - - IOB1:NSLEW[1]
32 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:BITSLIP_SYNC ILOGIC1:SERDES_MODE[0] - - - - OLOGIC1:SERDES - - ILOGIC1:MUX.CLKB[0] OLOGIC1:INIT_DLY_CNT[2] - - - IOB1:PSLEW[1] -
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:D_EMU - - - - - OLOGIC1:TFF_SR_SYNC[0] - ILOGIC1:MUX.CLKB[2] OLOGIC1:SERDES_MODE[0] - - - - IOB1:NSLEW[2]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:I_DELAY_ENABLE - - - - - - OLOGIC1:INIT_TRANK1[3] ILOGIC1:MUX.CLKB[7] - OLOGIC1:INIT_FIFO_RESET[7] - - - IOB1:LVDS[5] -
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DATA_RATE[0] - - - - - - - ILOGIC1:MUX.CLKB[8] OLOGIC1:INIT_PIPE_DATA1[0] - - - - ~IOB1:NDRIVE[3]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK1_PARTIAL[4] - - - - - - - ILOGIC1:MUX.CLKB[5] - - - - ~IODELAY1:IDELAY_VALUE_CUR[1] IOB1:OUTPUT_MISC[0] -
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[1] - - - - ~OLOGIC1:OFF_SRVAL[0] - - - - - - - - -
26 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[1] - - - - - OLOGIC1:INIT_TRANK1[2] - - ILOGIC1:MUX.CLKB[1] - - - ~IODELAY1:INV.DATAIN IOB1:PULL_DYNAMIC -
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[1] - - - - - ~OLOGIC1:OFF_SRVAL[2] - ILOGIC1:MUX.CLKB[4] - OLOGIC1:OFF_SR_SYNC[3] - - - IOB1:LVDS[6]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[2] - - - - - - ~OLOGIC1:OFF_INIT ILOGIC1:MUX.CLKB[10] ILOGIC1:MUX.CLKB[9] OLOGIC1:INIT_FIFO_ADDR[6] ~OLOGIC1:TFF_INIT - - IOB1:PSLEW[0] -
23 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:DDR_CLK_EDGE[1] ~ILOGIC1:IFF4_SRVAL - - - - - ~OLOGIC1:OFF_SRVAL[1] ILOGIC1:MUX.CLKB[3] - - OLOGIC1:ODELAY_USED - - - -
22 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF4_INIT ~ILOGIC1:IFF3_SRVAL - - - - - - - ILOGIC1:MUX.CLKB[6] - OLOGIC1:INIT_FIFO_ADDR[5] - IODELAY1:DELAY_SRC[3] IOB1:PDRIVE[3] -
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[2] - - - - OLOGIC1:INIT_TRANK1[1] - - OLOGIC1:MUX.CLKB[1] - OLOGIC1:INIT_DLY_CNT[9] - IODELAY1:DELAY_SRC[4] - ~IOB1:NDRIVE[2]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[2] - - - - - OLOGIC1:SELFHEAL OLOGIC1:OFF_SR_SYNC[2] OLOGIC1:MUX.CLKB[5] - ~OLOGIC1:TFF_SRVAL[1] - - ~IODELAY1:IDELAY_VALUE_CUR[2] IOB1:NSLEW[4] -
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[3] - - - - OLOGIC1:CLK_RATIO[3] OLOGIC1:CLK_RATIO[2] OLOGIC1:MUX.CLKB[7] - ~OLOGIC1:TFF_SRVAL[0] OLOGIC1:MUX.CLKPERF[0] - IODELAY1:DELAY_SRC[2] - IOB1:NSLEW[0]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF3_INIT - - - - - OLOGIC1:CLK_RATIO[1] - - OLOGIC1:MUX.CLKB[8] IODELAY1:HIGH_PERFORMANCE_MODE OLOGIC1:INIT_FIFO_RESET[12] - - ~IOB1:PDRIVE[2] -
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[3] - - - - - OLOGIC1:CLK_RATIO[0] - - OLOGIC1:INIT_FIFO_ADDR[4] ~OLOGIC1:TFF_SRVAL[2] - - - IOB1:PULL[0]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF2_INIT - - - - - - - OLOGIC1:MUX.CLKB[0] - - OLOGIC1:INIT_DLY_CNT[7] - - IOB1:PULL[1] -
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[3] - - - - ~OLOGIC1:INV.T4 OLOGIC1:INIT_TRANK1[0] OLOGIC1:MUX.CLKB[4] OLOGIC1:MUX.CLKB[2] - OLOGIC1:TFF_SR_SYNC[1] - - - IOB1:PULL[2]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[4] - - - - - ~OLOGIC1:INV.T2 ~OLOGIC1:INV.T3 - - OLOGIC1:TRISTATE_WIDTH[0] - - IODELAY1:DELAY_SRC[0] ~IOB1:NDRIVE[1] -
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[4] - - - - OLOGIC1:DATA_WIDTH[1] ~OLOGIC1:INV.T1 OLOGIC1:MUX.CLKB[10] OLOGIC1:MUX.CLKB[9] OLOGIC1:INIT_FIFO_RESET[4] OLOGIC1:TFF_SR_USED - IODELAY1:DELAY_SRC[1] - IOB1:LVDS[7]
12 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[4] - - - - - OLOGIC1:DATA_WIDTH[3] OLOGIC1:DATA_WIDTH[5] - - - - - ~IODELAY1:IDELAY_VALUE_CUR[3] IOB1:OUTPUT_DELAY -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF1_INIT - - - - OLOGIC1:DATA_WIDTH[6] OLOGIC1:DATA_WIDTH[2] - OLOGIC1:MUX.CLKB[3] - OLOGIC1:INIT_ORANK2_PARTIAL[0] - IODELAY1:DELAY_TYPE[3] - ~IOB1:PDRIVE[1]
10 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF2_SRVAL ILOGIC1:DDR_CLK_EDGE[0] - - - - OLOGIC1:DATA_WIDTH[0] OLOGIC1:DATA_WIDTH[7] OLOGIC1:MUX.CLKDIVB[6] OLOGIC1:MUX.CLKB[6] IODELAY1:ENABLE OLOGIC1:INIT_ORANK2_PARTIAL[1] - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:SERDES ILOGIC1:IFF_SR_SYNC - - - - OLOGIC1:DATA_WIDTH[4] OLOGIC1:OFF_SR_USED OLOGIC1:MUX.CLKDIVB[0] - OLOGIC1:INIT_DLY_CNT[6] - - - - ~IOB1:DCIUPDATEMODE_ASREQUIRED
8 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:IFF_LATCH ~ILOGIC1:IFF1_SRVAL - - - - ~OLOGIC1:INV.CLK1 OLOGIC1:INV.CLKDIV - OLOGIC1:MUX.CLKDIVB[1] OLOGIC1:INIT_ORANK2_PARTIAL[2] - - - IOB1:LVDS[8] -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK3[5] - - - - - ~OLOGIC1:INV.CLK2 OLOGIC1:MUX.CLKDIVB[5] OLOGIC1:MUX.CLKDIVB[7] OLOGIC1:INIT_ORANK2_PARTIAL[3] OLOGIC1:INIT_FIFO_RESET[11] - - - ~IOB1:PDRIVE[0]
6 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_RANK2[5] - - - - - OLOGIC1:OMUX[4] - - - - - - ~IODELAY1:IDELAY_VALUE_CUR[4] IOB1:DCI_MISC[1] -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:INIT_BITSLIP[5] - - - - OLOGIC1:OMUX[3] OLOGIC1:OMUX[0] OLOGIC1:MUX.CLKDIVB[3] OLOGIC1:MUX.CLKDIVB[2] - - - - - IOB1:DCI_MISC[0]
4 - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_CE[0] - - - - - - - - - OLOGIC1:INIT_DLY_CNT[1] OLOGIC1:TMUX[1] - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - ~ILOGIC1:INIT_CE[1] - - - - - - - - IODELAY1:EXTRA_DELAY OLOGIC1:TMUX[2] - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_REV_USED ILOGIC1:READBACK_I - - - - - - OLOGIC1:MUX.CLKDIVB[4] OLOGIC1:MUX.CLKDIVB[8] OLOGIC1:TMUX[3] OLOGIC1:INIT_FIFO_RESET[8] - - ~IOB1:NDRIVE[0] -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:RANK23_DLY ILOGIC1:NUM_CE[0] - - - - - ILOGIC1:D_EMU_OPTION[2] - - - OLOGIC1:TMUX[4] - - - IOB1:DCI_T
0 - - - - - - - - - - - - - - - - - - - - - - - - - - ILOGIC1:IFF_SR_USED ILOGIC1:RANK12_DLY - - - - ILOGIC1:D_EMU_OPTION[1] ILOGIC1:D_EMU_OPTION[0] - - OLOGIC1:INIT_DLY_CNT[3] OLOGIC1:TMUX[0] - - IOB1:IBUF_MODE[2] -
ILOGIC0:BITSLIP_ENABLE 0.27.21
ILOGIC0:BITSLIP_SYNC 0.27.31
ILOGIC0:DYN_CLKDIV_INV_EN 0.27.9
ILOGIC0:DYN_CLK_INV_EN 0.27.23
ILOGIC0:D_EMU 0.26.32
ILOGIC0:IFF_DELAY_ENABLE 0.26.4
ILOGIC0:IFF_REV_USED 0.27.61
ILOGIC0:IFF_SR_SYNC 0.26.54
ILOGIC0:IFF_SR_USED 0.27.63
ILOGIC0:IFF_TSBYPASS_ENABLE 0.26.7
ILOGIC0:INV.CLKDIV 0.26.24
ILOGIC0:I_DELAY_ENABLE 0.27.33
ILOGIC0:I_TSBYPASS_ENABLE 0.26.8
ILOGIC0:RANK12_DLY 0.26.63
ILOGIC0:RANK23_DLY 0.27.62
ILOGIC0:READBACK_I 0.26.61
ILOGIC0:SERDES 0.27.54
ILOGIC1:BITSLIP_ENABLE 1.26.42
ILOGIC1:BITSLIP_SYNC 1.26.32
ILOGIC1:DYN_CLKDIV_INV_EN 1.26.54
ILOGIC1:DYN_CLK_INV_EN 1.26.40
ILOGIC1:D_EMU 1.27.31
ILOGIC1:IFF_DELAY_ENABLE 1.27.59
ILOGIC1:IFF_REV_USED 1.26.2
ILOGIC1:IFF_SR_SYNC 1.27.9
ILOGIC1:IFF_SR_USED 1.26.0
ILOGIC1:IFF_TSBYPASS_ENABLE 1.27.56
ILOGIC1:INV.CLKDIV 1.27.39
ILOGIC1:I_DELAY_ENABLE 1.26.30
ILOGIC1:I_TSBYPASS_ENABLE 1.27.55
ILOGIC1:RANK12_DLY 1.27.0
ILOGIC1:RANK23_DLY 1.26.1
ILOGIC1:READBACK_I 1.27.2
ILOGIC1:SERDES 1.26.9
IOB0:DCI_T 0.40.62
IOB0:OUTPUT_DELAY 0.41.51
IOB0:PULL_DYNAMIC 0.41.37
IOB0:VR 0.41.13
IOB0:VREF_SYSMON 0.41.3
IOB1:DCI_T 1.41.1
IOB1:OUTPUT_DELAY 1.40.12
IOB1:PULL_DYNAMIC 1.40.26
IOB1:VR 1.40.50
IOB1:VREF_SYSMON 1.40.60
IODELAY0:CINVCTRL_SEL 0.38.21
IODELAY0:ENABLE 0.37.53
IODELAY0:EXTRA_DELAY 0.37.60
IODELAY0:HIGH_PERFORMANCE_MODE 0.37.45
IODELAY0:INV.C 0.38.22
IODELAY1:CINVCTRL_SEL 1.39.42
IODELAY1:ENABLE 1.36.10
IODELAY1:EXTRA_DELAY 1.36.3
IODELAY1:HIGH_PERFORMANCE_MODE 1.36.18
IODELAY1:INV.C 1.39.41
OLOGIC0:DDR3_BYPASS 0.36.23
OLOGIC0:DDR3_DATA 0.37.23
OLOGIC0:INV.CLKDIV 0.32.55
OLOGIC0:INV.D1 0.33.24
OLOGIC0:INV.D2 0.32.20
OLOGIC0:INV.D3 0.32.14
OLOGIC0:INV.D4 0.33.11
OLOGIC0:INV.D5 0.32.8
OLOGIC0:INV.D6 0.33.5
OLOGIC0:MISR_ENABLE 0.27.4
OLOGIC0:MISR_ENABLE_FDBK 0.27.3
OLOGIC0:MISR_RESET 0.27.0
OLOGIC0:ODELAY_USED 0.36.40
OLOGIC0:OFF_SR_USED 0.32.54
OLOGIC0:SELFHEAL 0.33.43
OLOGIC0:SERDES 0.33.31
OLOGIC0:TFF_SR_USED 0.36.50
OLOGIC0:WC_DELAY 0.37.21
OLOGIC1:DDR3_BYPASS 1.37.40
OLOGIC1:DDR3_DATA 1.36.40
OLOGIC1:INV.CLKDIV 1.33.8
OLOGIC1:INV.D1 1.32.39
OLOGIC1:INV.D2 1.33.43
OLOGIC1:INV.D3 1.33.49
OLOGIC1:INV.D4 1.32.52
OLOGIC1:INV.D5 1.33.55
OLOGIC1:INV.D6 1.32.58
OLOGIC1:MISR_ENABLE 1.26.59
OLOGIC1:MISR_ENABLE_FDBK 1.26.60
OLOGIC1:MISR_RESET 1.26.63
OLOGIC1:ODELAY_USED 1.37.23
OLOGIC1:OFF_SR_USED 1.33.9
OLOGIC1:SELFHEAL 1.32.20
OLOGIC1:SERDES 1.32.32
OLOGIC1:TFF_SR_USED 1.37.13
OLOGIC1:WC_DELAY 1.36.42
non-inverted [0]
ILOGIC0:DATA_RATE 0.26.34
ILOGIC1:DATA_RATE 1.27.29
DDR 0
SDR 1
ILOGIC0:DATA_WIDTH 0.26.23 0.26.21 0.27.18 0.26.17
ILOGIC1:DATA_WIDTH 1.27.40 1.27.42 1.26.45 1.27.46
NONE 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
10 1 0 1 0
ILOGIC0:DDR_CLK_EDGE 0.27.40 0.26.53
ILOGIC1:DDR_CLK_EDGE 1.26.23 1.27.10
SAME_EDGE_PIPELINED 0 0
OPPOSITE_EDGE 0 1
SAME_EDGE 1 0
ILOGIC0:DYN_OCLK_INV_EN 0.27.14 0.26.13
ILOGIC1:DYN_OCLK_INV_EN 1.27.50 1.26.49
IOB0:DCI_MISC 0.41.57 0.40.58
IOB0:OUTPUT_ENABLE 0.41.29 0.40.28
IOB1:DCI_MISC 1.40.6 1.41.5
IOB1:OUTPUT_ENABLE 1.41.35 1.40.34
OLOGIC0:TFF_SR_SYNC 0.36.48 0.32.32
OLOGIC1:TFF_SR_SYNC 1.37.15 1.33.31
non-inverted [1] [0]
ILOGIC0:D_EMU_OPTION 0.32.62 0.33.63 0.32.63
ILOGIC1:D_EMU_OPTION 1.33.1 1.32.0 1.33.0
DLY3 0 0 0
DLY0 0 0 1
DLY2 0 1 0
MATCH_DLY0 0 1 1
MATCH_DLY2 1 0 0
DLY1 1 1 0
ILOGIC0:IFF1_INIT 0.26.52
ILOGIC0:IFF1_SRVAL 0.26.55
ILOGIC0:IFF2_INIT 0.27.47
ILOGIC0:IFF2_SRVAL 0.27.53
ILOGIC0:IFF3_INIT 0.27.45
ILOGIC0:IFF3_SRVAL 0.26.41
ILOGIC0:IFF4_INIT 0.27.41
ILOGIC0:IFF4_SRVAL 0.26.40
ILOGIC0:IFF_LATCH 0.27.55
ILOGIC0:INV.D 0.26.0
ILOGIC0:INV.OCLK1 0.27.16
ILOGIC0:INV.OCLK2 0.27.13
ILOGIC1:IFF1_INIT 1.27.11
ILOGIC1:IFF1_SRVAL 1.27.8
ILOGIC1:IFF2_INIT 1.26.16
ILOGIC1:IFF2_SRVAL 1.26.10
ILOGIC1:IFF3_INIT 1.26.18
ILOGIC1:IFF3_SRVAL 1.27.22
ILOGIC1:IFF4_INIT 1.26.22
ILOGIC1:IFF4_SRVAL 1.27.23
ILOGIC1:IFF_LATCH 1.26.8
ILOGIC1:INV.D 1.27.63
ILOGIC1:INV.OCLK1 1.26.47
ILOGIC1:INV.OCLK2 1.26.50
IOB0:DCIUPDATEMODE_ASREQUIRED 0.40.54
IOB1:DCIUPDATEMODE_ASREQUIRED 1.41.9
IODELAY0:INV.DATAIN 0.38.37
IODELAY0:INV.IDATAIN 0.38.25
IODELAY1:INV.DATAIN 1.39.26
IODELAY1:INV.IDATAIN 1.39.38
OLOGIC0:INV.CLK1 0.33.55
OLOGIC0:INV.CLK2 0.32.56
OLOGIC0:INV.CLKPERF 0.37.22
OLOGIC0:INV.T1 0.32.50
OLOGIC0:INV.T2 0.33.49
OLOGIC0:INV.T3 0.32.49
OLOGIC0:INV.T4 0.33.48
OLOGIC0:OFF_INIT 0.32.39
OLOGIC0:TFF_INIT 0.36.39
OLOGIC1:INV.CLK1 1.32.8
OLOGIC1:INV.CLK2 1.33.7
OLOGIC1:INV.CLKPERF 1.36.41
OLOGIC1:INV.T1 1.33.13
OLOGIC1:INV.T2 1.32.14
OLOGIC1:INV.T3 1.33.14
OLOGIC1:INV.T4 1.32.15
OLOGIC1:OFF_INIT 1.33.24
OLOGIC1:TFF_INIT 1.37.24
inverted ~[0]
ILOGIC0:INIT_BITSLIP 0.26.58 0.27.49 0.26.48 0.27.43 0.26.36 0.26.28
ILOGIC1:INIT_BITSLIP 1.27.5 1.26.14 1.27.15 1.26.20 1.27.27 1.27.35
OLOGIC0:INIT_ORANK1 0.32.27 0.32.22 0.33.16 0.33.10 0.33.6 0.33.1
OLOGIC1:INIT_ORANK1 1.33.36 1.33.41 1.32.47 1.32.53 1.32.57 1.32.62
non-inverted [5] [4] [3] [2] [1] [0]
ILOGIC0:INIT_BITSLIPCNT 0.26.12 0.27.19 0.26.20 0.27.25
ILOGIC1:INIT_BITSLIPCNT 1.27.51 1.26.44 1.27.43 1.26.38
inverted ~[3] ~[2] ~[1] ~[0]
ILOGIC0:INIT_CE 0.26.60 0.27.59
ILOGIC1:INIT_CE 1.27.3 1.26.4
inverted ~[1] ~[0]
ILOGIC0:INIT_RANK1_PARTIAL 0.27.35 0.27.27 0.26.26 0.26.6 0.27.5
ILOGIC1:INIT_RANK1_PARTIAL 1.26.28 1.26.36 1.27.37 1.27.57 1.26.58
IODELAY0:IDELAY_VALUE_CUR 0.38.57 0.38.51 0.38.43 0.38.35 0.38.27
IODELAY1:IDELAY_VALUE_CUR 1.39.6 1.39.12 1.39.20 1.39.28 1.39.36
inverted ~[4] ~[3] ~[2] ~[1] ~[0]
ILOGIC0:INIT_RANK2 0.27.57 0.26.50 0.26.44 0.27.39 0.27.37 0.27.29
ILOGIC0:INIT_RANK3 0.26.56 0.27.51 0.26.46 0.26.42 0.26.38 0.26.30
ILOGIC1:INIT_RANK2 1.26.6 1.27.13 1.27.19 1.26.24 1.26.26 1.26.34
ILOGIC1:INIT_RANK3 1.27.7 1.26.12 1.27.17 1.27.21 1.27.25 1.27.33
inverted ~[5] ~[4] ~[3] ~[2] ~[1] ~[0]
ILOGIC0:INTERFACE_TYPE 0.26.16 0.27.10 0.26.15
ILOGIC1:INTERFACE_TYPE 1.27.47 1.26.53 1.27.48
MEMORY 0 0 0
NETWORKING 0 0 1
MEMORY_DDR3 0 1 1
OVERSAMPLE 1 0 1
ILOGIC0:INV.CLK 0.27.24 0.27.22 0.27.17
ILOGIC1:INV.CLK 1.26.46 1.26.41 1.26.39
OLOGIC0:OFF_SRVAL 0.33.36 0.32.40 0.32.38
OLOGIC0:TFF_SRVAL 0.37.44 0.37.43 0.36.46
OLOGIC1:OFF_SRVAL 1.33.25 1.33.23 1.32.27
OLOGIC1:TFF_SRVAL 1.37.17 1.36.20 1.36.19
inverted ~[2] ~[1] ~[0]
ILOGIC0:MUX.CLK 0.35.8 0.34.8 0.34.3 0.35.2 0.35.10 0.35.7 0.35.9 0.34.1 0.34.9 0.34.6 0.34.0
ILOGIC0:MUX.CLKB 0.35.39 0.34.39 0.34.34 0.35.33 0.34.41 0.35.35 0.34.38 0.35.40 0.34.32 0.34.37 0.34.31
ILOGIC1:MUX.CLK 1.34.55 1.35.55 1.35.60 1.34.61 1.34.53 1.34.56 1.34.54 1.35.62 1.35.54 1.35.57 1.35.63
ILOGIC1:MUX.CLKB 1.34.24 1.35.24 1.35.29 1.34.30 1.35.22 1.34.28 1.35.25 1.34.23 1.35.31 1.35.26 1.35.32
OLOGIC0:MUX.CLK 0.35.19 0.34.19 0.35.13 0.34.13 0.34.22 0.34.21 0.34.18 0.35.14 0.34.17 0.34.14 0.34.11
OLOGIC0:MUX.CLKB 0.35.50 0.34.50 0.34.45 0.35.44 0.34.53 0.35.43 0.35.48 0.34.52 0.34.48 0.34.42 0.35.47
OLOGIC1:MUX.CLK 1.34.44 1.35.44 1.34.50 1.35.50 1.35.41 1.35.42 1.35.45 1.34.49 1.35.46 1.35.49 1.35.52
OLOGIC1:MUX.CLKB 1.34.13 1.35.13 1.35.18 1.34.19 1.35.10 1.34.20 1.34.15 1.35.11 1.35.15 1.35.21 1.34.16
NONE 0 0 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 1 0 0 0 0 0 0 1
HCLK1 0 0 0 1 0 0 0 0 0 1 0
HCLK2 0 0 0 1 0 0 0 0 1 0 0
HCLK3 0 0 0 1 0 0 0 1 0 0 0
HCLK4 0 0 0 1 0 0 1 0 0 0 0
HCLK5 0 0 0 1 0 1 0 0 0 0 0
HCLK6 0 0 0 1 1 0 0 0 0 0 0
HCLK7 0 0 1 0 0 0 0 0 0 0 1
HCLK8 0 0 1 0 0 0 0 0 0 1 0
HCLK9 0 0 1 0 0 0 0 0 1 0 0
HCLK10 0 0 1 0 0 0 0 1 0 0 0
HCLK11 0 0 1 0 0 0 1 0 0 0 0
RCLK0 0 0 1 0 0 1 0 0 0 0 0
RCLK1 0 0 1 0 1 0 0 0 0 0 0
RCLK2 0 1 0 0 0 0 0 0 0 0 1
RCLK3 0 1 0 0 0 0 0 0 0 1 0
RCLK4 0 1 0 0 0 0 0 0 1 0 0
RCLK5 0 1 0 0 0 0 0 1 0 0 0
IOCLK0 0 1 0 0 0 0 1 0 0 0 0
IOCLK1 0 1 0 0 0 1 0 0 0 0 0
IOCLK2 0 1 0 0 1 0 0 0 0 0 0
IOCLK3 1 0 0 0 0 0 0 0 0 0 1
IOCLK4 1 0 0 0 0 0 0 0 0 1 0
IOCLK5 1 0 0 0 0 0 0 0 1 0 0
IOCLK6 1 0 0 0 0 0 0 1 0 0 0
IOCLK7 1 0 0 0 0 0 1 0 0 0 0
ILOGIC0:NUM_CE 0.26.62
ILOGIC1:NUM_CE 1.27.1
1 0
2 1
ILOGIC0:SERDES_MODE 0.26.31
ILOGIC1:SERDES_MODE 1.27.32
OLOGIC0:SERDES_MODE 0.37.32
OLOGIC1:SERDES_MODE 1.36.31
MASTER 0
SLAVE 1
ILOGIC0:TSBYPASS_MUX 0.26.9
ILOGIC1:TSBYPASS_MUX 1.27.54
T 0
GND 1
IOB0:DCI_MODE 0.41.19 0.40.12 0.40.14
IOB1:DCI_MODE 1.40.44 1.41.51 1.41.49
NONE 0 0 0
OUTPUT 0 0 1
OUTPUT_HALF 0 1 0
TERM_VCC 0 1 1
TERM_SPLIT 1 0 0
IOB0:IBUF_MODE 0.40.4 0.40.2 0.41.63 0.41.1 0.40.0
IOB1:IBUF_MODE 1.41.59 1.41.61 1.40.0 1.40.62 1.41.63
OFF 0 0 0 0 0
VREF_LP 0 0 0 0 1
DIFF_LP 0 0 0 1 0
CMOS12 0 0 0 1 1
CMOS 0 0 1 1 1
VREF_HP 0 1 0 0 1
DIFF_HP 1 0 0 1 0
IOB0:LVDS 0.41.55 0.40.50 0.40.38 0.41.33 0.41.23 0.40.22 0.40.18 0.40.8 0.41.5
IOB1:LVDS 1.40.8 1.41.13 1.41.25 1.40.30 1.40.40 1.41.41 1.41.45 1.41.55 1.40.58
non-inverted [8] [7] [6] [5] [4] [3] [2] [1] [0]
IOB0:NDRIVE 0.40.6 0.41.21 0.40.34 0.40.42 0.41.49 0.41.61
IOB1:NDRIVE 1.41.57 1.40.42 1.41.29 1.41.21 1.40.14 1.40.2
mixed inversion [5] [4] ~[3] ~[2] ~[1] ~[0]
IOB0:NSLEW 0.41.43 0.41.17 0.40.32 0.40.30 0.40.44
IOB0:PSLEW 0.40.10 0.40.20 0.41.27 0.41.31 0.41.39
IOB1:NSLEW 1.40.20 1.40.46 1.41.31 1.41.33 1.41.19
IOB1:PSLEW 1.41.53 1.41.43 1.40.36 1.40.32 1.40.24
IODELAY0:ALT_DELAY_VALUE 0.38.10 0.38.11 0.38.12 0.38.13 0.38.14
IODELAY0:IDELAY_VALUE_INIT 0.38.16 0.38.17 0.38.18 0.38.19 0.38.20
IODELAY1:ALT_DELAY_VALUE 1.39.53 1.39.52 1.39.51 1.39.50 1.39.49
IODELAY1:IDELAY_VALUE_INIT 1.39.47 1.39.46 1.39.45 1.39.44 1.39.43
non-inverted [4] [3] [2] [1] [0]
IOB0:OMUX 0.40.36
O 0
OTHER_O_INV 1
IOB0:OUTPUT_MISC 0.41.9 0.41.25 0.40.24 0.41.35
IOB1:OUTPUT_MISC 1.40.54 1.40.38 1.41.39 1.40.28
OLOGIC0:INIT_LOADCNT 0.32.29 0.33.23 0.32.19 0.32.13
OLOGIC0:INIT_ORANK2_PARTIAL 0.37.56 0.37.55 0.36.53 0.36.52
OLOGIC0:INIT_TRANK1 0.32.48 0.33.42 0.33.37 0.32.33
OLOGIC0:OFF_SR_SYNC 0.36.38 0.33.19 0.33.0 0.32.43
OLOGIC1:INIT_LOADCNT 1.33.34 1.32.40 1.33.44 1.33.50
OLOGIC1:INIT_ORANK2_PARTIAL 1.36.7 1.36.8 1.37.10 1.37.11
OLOGIC1:INIT_TRANK1 1.33.30 1.32.26 1.32.21 1.33.15
OLOGIC1:OFF_SR_SYNC 1.37.25 1.33.20 1.32.63 1.32.44
non-inverted [3] [2] [1] [0]
IOB0:PDRIVE 0.41.7 0.40.26 0.41.41 0.41.45 0.40.52 0.40.56
IOB1:PDRIVE 1.40.56 1.41.37 1.40.22 1.40.18 1.41.11 1.41.7
mixed inversion [5] ~[4] [3] ~[2] ~[1] ~[0]
IOB0:PULL 0.40.48 0.41.47 0.40.46
IOB1:PULL 1.41.15 1.40.16 1.41.17
PULLDOWN 0 0 0
NONE 0 0 1
PULLUP 0 1 1
KEEPER 1 0 1
IODELAY0:DELAY_SRC 0.38.42 0.38.41 0.38.44 0.38.50 0.38.49
IODELAY1:DELAY_SRC 1.39.21 1.39.22 1.39.19 1.39.13 1.39.14
NONE 0 0 0 0 0
I 0 0 0 0 1
O 0 0 0 1 0
IO 0 0 0 1 1
DATAIN 0 0 1 0 0
CLKIN 0 1 0 0 0
DELAYCHAIN_OSC 1 0 0 0 0
IODELAY0:DELAY_TYPE 0.38.52 0.38.9 0.38.8 0.38.15 0.38.26
IODELAY1:DELAY_TYPE 1.39.54 1.39.11 1.39.55 1.39.48 1.39.37
FIXED 0 0 0 0 0
VARIABLE 0 0 0 0 1
VAR_LOADABLE 0 0 0 1 1
VARIABLE_SWAPPED 0 0 1 0 1
IO_VAR_LOADABLE 1 1 1 1 1
OLOGIC0:CLK_RATIO 0.33.44 0.32.44 0.33.45 0.32.46
OLOGIC1:CLK_RATIO 1.32.19 1.33.19 1.32.18 1.33.17
NONE 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 1
7_8 1 1 0 0
6 1 1 0 1
OLOGIC0:DATA_WIDTH 0.32.53 0.33.52 0.32.51 0.33.54 0.33.51 0.32.52 0.33.50 0.33.53
OLOGIC1:DATA_WIDTH 1.33.10 1.32.11 1.33.12 1.32.9 1.32.12 1.33.11 1.32.13 1.32.10
NONE 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 1
3 0 0 0 0 0 0 1 0
4 0 0 0 0 0 1 0 0
5 0 0 0 0 1 0 0 0
6 0 0 0 1 0 0 0 0
7 0 0 1 0 0 0 0 0
8 0 1 0 0 0 0 0 0
10 1 0 0 0 0 0 0 0
OLOGIC0:INIT_DLY_CNT 0.36.42 0.36.1 0.36.47 0.37.54 0.37.13 0.36.19 0.37.63 0.37.31 0.37.59 0.36.25
OLOGIC1:INIT_DLY_CNT 1.37.21 1.37.62 1.37.16 1.36.9 1.36.50 1.37.44 1.36.0 1.36.32 1.36.4 1.37.38
non-inverted [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OLOGIC0:INIT_FIFO_ADDR 0.36.0 0.36.7 0.37.2 0.36.8 0.37.39 0.36.41 0.37.46 0.36.18 0.36.12 0.37.14 0.37.20
OLOGIC1:INIT_FIFO_ADDR 1.37.63 1.37.56 1.36.61 1.37.55 1.36.24 1.37.22 1.36.17 1.37.45 1.37.51 1.36.49 1.36.43
non-inverted [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OLOGIC0:INIT_FIFO_RESET 0.36.45 0.36.56 0.37.28 0.36.5 0.36.61 0.37.33 0.37.10 0.36.22 0.37.50 0.36.21 0.36.4 0.37.9 0.36.16
OLOGIC1:INIT_FIFO_RESET 1.37.18 1.37.7 1.36.35 1.37.58 1.37.2 1.36.30 1.36.53 1.37.41 1.36.13 1.37.42 1.37.59 1.36.54 1.37.47
non-inverted [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OLOGIC0:INIT_PIPE_DATA0 0.32.2 0.33.15 0.32.5 0.33.17 0.32.23 0.32.28 0.37.1 0.36.11 0.37.3 0.37.17 0.36.26 0.36.29
OLOGIC0:INIT_PIPE_DATA1 0.33.9 0.33.14 0.33.13 0.33.20 0.32.24 0.33.25 0.37.8 0.36.15 0.37.12 0.37.19 0.37.26 0.37.34
OLOGIC1:INIT_PIPE_DATA0 1.33.61 1.32.48 1.33.58 1.32.46 1.33.40 1.33.35 1.36.62 1.37.52 1.36.60 1.36.46 1.37.37 1.37.34
OLOGIC1:INIT_PIPE_DATA1 1.32.54 1.32.49 1.32.50 1.32.43 1.33.39 1.32.38 1.36.55 1.37.48 1.36.51 1.36.44 1.36.37 1.36.29
non-inverted [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OLOGIC0:INTERFACE_TYPE 0.36.6
OLOGIC1:INTERFACE_TYPE 1.37.57
DEFAULT 0
MEMORY_DDR3 1
OLOGIC0:MISR_CLK_SELECT 0.27.8 0.27.7
OLOGIC1:MISR_CLK_SELECT 1.26.55 1.26.56
NONE 0 0
CLK1 0 1
CLK2 1 0
OLOGIC0:MUX.CLKDIV 0.34.25 0.34.23 0.34.28 0.35.25 0.35.30 0.35.27 0.34.27 0.34.24 0.35.23
OLOGIC0:MUX.CLKDIVB 0.34.61 0.34.56 0.35.53 0.35.56 0.35.61 0.35.58 0.34.58 0.34.55 0.35.54
OLOGIC1:MUX.CLKDIV 1.35.38 1.35.40 1.35.35 1.34.38 1.34.33 1.34.36 1.35.36 1.35.39 1.34.40
OLOGIC1:MUX.CLKDIVB 1.35.2 1.35.7 1.34.10 1.34.7 1.34.2 1.34.5 1.35.5 1.35.8 1.34.9
NONE 0 0 0 0 0 0 0 0 0
HCLK0 0 0 0 1 0 0 0 0 1
HCLK4 0 0 0 1 0 0 0 1 0
HCLK8 0 0 0 1 0 0 1 0 0
RCLK0 0 0 0 1 0 1 0 0 0
RCLK4 0 0 0 1 1 0 0 0 0
HCLK1 0 0 1 0 0 0 0 0 1
HCLK5 0 0 1 0 0 0 0 1 0
HCLK9 0 0 1 0 0 0 1 0 0
RCLK1 0 0 1 0 0 1 0 0 0
RCLK5 0 0 1 0 1 0 0 0 0
HCLK2 0 1 0 0 0 0 0 0 1
HCLK6 0 1 0 0 0 0 0 1 0
HCLK10 0 1 0 0 0 0 1 0 0
RCLK2 0 1 0 0 0 1 0 0 0
HCLK3 1 0 0 0 0 0 0 0 1
HCLK7 1 0 0 0 0 0 0 1 0
HCLK11 1 0 0 0 0 0 1 0 0
RCLK3 1 0 0 0 0 1 0 0 0
OLOGIC0:MUX.CLKPERF 0.36.44
OLOGIC1:MUX.CLKPERF 1.37.19
OCLK0 0
OCLK1 1
OLOGIC0:OMUX 0.33.57 0.33.58 0.32.25 0.33.26 0.32.58
OLOGIC1:OMUX 1.32.6 1.32.5 1.33.38 1.32.37 1.33.5
NONE 0 0 0 0 0
D1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
SERDES_DDR 0 0 1 0 0
FF 0 1 0 1 0
DDR 0 1 1 0 0
LATCH 1 0 0 1 0
OLOGIC0:TMUX 0.36.62 0.37.61 0.36.60 0.36.59 0.36.63
OLOGIC1:TMUX 1.37.1 1.36.2 1.37.3 1.37.4 1.37.0
NONE 0 0 0 0 0
T1 0 0 0 0 1
SERDES_SDR 0 0 0 1 0
SERDES_DDR 0 0 1 0 0
FF 0 1 0 1 0
DDR 0 1 1 0 0
LATCH 1 0 0 1 0
OLOGIC0:TRISTATE_WIDTH 0.37.49
OLOGIC1:TRISTATE_WIDTH 1.36.14
1 0
4 1

Tile HCLK_IOI

Cells: 2 IRIs: 0

Bel HCLK_IOI

virtex6 HCLK_IOI bel HCLK_IOI
PinDirectionWires
BUFR_CKINT0inputTCELL1:IMUX.IMUX4
BUFR_CKINT1inputTCELL0:IMUX.IMUX4

Bel BUFR0

virtex6 HCLK_IOI bel BUFR0
PinDirectionWires
CEinputTCELL1:IMUX.IMUX28
CLRinputTCELL1:IMUX.IMUX27

Bel BUFR1

virtex6 HCLK_IOI bel BUFR1
PinDirectionWires
CEinputTCELL0:IMUX.IMUX9
CLRinputTCELL0:IMUX.IMUX29

Bel BUFIO0

virtex6 HCLK_IOI bel BUFIO0
PinDirectionWires
DQSMASKinputTCELL0:IMUX.IMUX24

Bel BUFIO1

virtex6 HCLK_IOI bel BUFIO1
PinDirectionWires
DQSMASKinputTCELL0:IMUX.IMUX23

Bel BUFIO2

virtex6 HCLK_IOI bel BUFIO2
PinDirectionWires
DQSMASKinputTCELL1:IMUX.IMUX24

Bel BUFIO3

virtex6 HCLK_IOI bel BUFIO3
PinDirectionWires
DQSMASKinputTCELL1:IMUX.IMUX23

Bel BUFO0

virtex6 HCLK_IOI bel BUFO0
PinDirectionWires

Bel BUFO1

virtex6 HCLK_IOI bel BUFO1
PinDirectionWires

Bel IDELAYCTRL

virtex6 HCLK_IOI bel IDELAYCTRL
PinDirectionWires
DNPULSEOUToutputTCELL0:OUT8
OUTN1outputTCELL0:OUT7
OUTN65outputTCELL0:OUT6
RDYoutputTCELL1:OUT6
RSTinputTCELL1:IMUX.IMUX32
UPPULSEOUToutputTCELL0:OUT11

Bel DCI

virtex6 HCLK_IOI bel DCI
PinDirectionWires
DCIDONEoutputTCELL1:OUT11
INT_DCI_ENinputTCELL0:IMUX.IMUX26
TSTCLKinputTCELL0:IMUX.IMUX27
TSTHLNinputTCELL0:IMUX.IMUX28
TSTHLPinputTCELL1:IMUX.IMUX29
TSTRSTinputTCELL1:IMUX.IMUX9

Bel wires

virtex6 HCLK_IOI bel wires
WirePins
TCELL0:IMUX.IMUX4HCLK_IOI.BUFR_CKINT1
TCELL0:IMUX.IMUX9BUFR1.CE
TCELL0:IMUX.IMUX23BUFIO1.DQSMASK
TCELL0:IMUX.IMUX24BUFIO0.DQSMASK
TCELL0:IMUX.IMUX26DCI.INT_DCI_EN
TCELL0:IMUX.IMUX27DCI.TSTCLK
TCELL0:IMUX.IMUX28DCI.TSTHLN
TCELL0:IMUX.IMUX29BUFR1.CLR
TCELL0:OUT6IDELAYCTRL.OUTN65
TCELL0:OUT7IDELAYCTRL.OUTN1
TCELL0:OUT8IDELAYCTRL.DNPULSEOUT
TCELL0:OUT11IDELAYCTRL.UPPULSEOUT
TCELL1:IMUX.IMUX4HCLK_IOI.BUFR_CKINT0
TCELL1:IMUX.IMUX9DCI.TSTRST
TCELL1:IMUX.IMUX23BUFIO3.DQSMASK
TCELL1:IMUX.IMUX24BUFIO2.DQSMASK
TCELL1:IMUX.IMUX27BUFR0.CLR
TCELL1:IMUX.IMUX28BUFR0.CE
TCELL1:IMUX.IMUX29DCI.TSTHLP
TCELL1:IMUX.IMUX32IDELAYCTRL.RST
TCELL1:OUT6IDELAYCTRL.RDY
TCELL1:OUT11DCI.DCIDONE

Bitstream

virtex6 HCLK_IOI bittile 0
BitFrame
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
31 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[0] HCLK_IOI:UNUSED.RCLK5 HCLK_IOI:BUF.HCLK11 BUFR1:MUX.I[14] BUFR1:MUX.I[7] HCLK_IOI:MUX.RCLK5[3] BUFR1:BUFR_DIVIDE[0] - - HCLK_IOI:DELAY.IOCLK5 HCLK_IOI:BUF.IOCLK5 IDELAYCTRL:RESET_STYLE[0] BUFO1:MUX.I[1] DCI:TEST_ENABLE[0] DCI:QUIET DCI:ENABLE DCI:PMASK_TERM_VCC[5]
30 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[1] HCLK_IOI:UNUSED.RCLK4 HCLK_IOI:BUF.HCLK10 BUFR1:MUX.I[15] BUFR1:MUX.I[6] HCLK_IOI:MUX.RCLK5[1] BUFR1:BUFR_DIVIDE[3] - - - BUFIO1:ENABLE IDELAYCTRL:MODE[2] BUFO0:MUX.I[1] INTERNAL_VREF:VREF[5] INTERNAL_VREF:VREF[1] LVDS:LVDSBIAS[0] DCI:PMASK_TERM_VCC[4]
29 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[2] HCLK_IOI:UNUSED.RCLK3 HCLK_IOI:BUF.HCLK9 BUFR1:MUX.I[13] BUFR1:MUX.I[5] HCLK_IOI:MUX.RCLK5[2] BUFR1:BUFR_DIVIDE[2] - - HCLK_IOI:DELAY.IOCLK1 BUFIO1:MUX.I[0] IDELAYCTRL:MODE[0] HCLK_IOI:BUF.VOCLK1 INTERNAL_VREF:VREF[4] INTERNAL_VREF:VREF[3] DCI:DYNAMIC_ENABLE DCI:PMASK_TERM_VCC[3]
28 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[3] HCLK_IOI:UNUSED.RCLK2 HCLK_IOI:BUF.HCLK8 BUFR1:MUX.I[12] BUFR1:MUX.I[4] HCLK_IOI:MUX.RCLK4[3] BUFR1:BUFR_DIVIDE[1] - - - BUFIO0:MUX.I[0] IDELAYCTRL:MODE[1] HCLK_IOI:BUF.VOCLK0 DCI:CASCADE_FROM_BELOW LVDS:LVDSBIAS[16] LVDS:LVDSBIAS[1] DCI:PMASK_TERM_VCC[2]
27 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[4] HCLK_IOI:UNUSED.RCLK1 HCLK_IOI:BUF.HCLK7 BUFR1:MUX.I[11] BUFR1:MUX.I[3] HCLK_IOI:MUX.RCLK4[1] BUFR1:ENABLE - - HCLK_IOI:DELAY.IOCLK0 BUFIO1:DQSMASK_ENABLE - BUFO1:MUX.I[3] DCI:CASCADE_FROM_ABOVE - LVDS:LVDSBIAS[2] DCI:PMASK_TERM_VCC[1]
26 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[5] HCLK_IOI:UNUSED.RCLK0 HCLK_IOI:BUF.HCLK6 BUFR1:MUX.I[10] BUFR1:MUX.I[2] HCLK_IOI:MUX.RCLK4[2] - - - - BUFIO0:DQSMASK_ENABLE IDELAYCTRL:MODE[3] BUFO1:MUX.I[0] INTERNAL_VREF:VREF[0] - LVDS:LVDSBIAS[3] DCI:PMASK_TERM_SPLIT[5]
25 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[6] HCLK_IOI:MUX.RCLK5[0] HCLK_IOI:BUF.HCLK5 BUFR1:MUX.I[9] BUFR1:MUX.I[1] HCLK_IOI:MUX.RCLK3[3] - - - HCLK_IOI:DELAY.IOCLK4 BUFIO0:ENABLE - BUFO1:MUX.I[2] DCI:NREF_TERM_SPLIT[2] - LVDS:LVDSBIAS[4] DCI:PMASK_TERM_SPLIT[4]
24 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[7] HCLK_IOI:MUX.RCLK4[0] HCLK_IOI:BUF.HCLK4 BUFR1:MUX.I[8] BUFR1:MUX.I[0] HCLK_IOI:MUX.RCLK3[1] - - - - HCLK_IOI:BUF.IOCLK4 - BUFO0:MUX.I[3] DCI:NREF_TERM_SPLIT[1] INTERNAL_VREF:VREF[2] LVDS:LVDSBIAS[5] DCI:PMASK_TERM_SPLIT[3]
23 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[8] HCLK_IOI:MUX.RCLK3[0] HCLK_IOI:BUF.HCLK3 BUFR0:MUX.I[14] BUFR0:MUX.I[7] HCLK_IOI:MUX.RCLK3[2] - - - HCLK_IOI:BUF.PERF0 HCLK_IOI:BUF.IOCLK7 - BUFO0:MUX.I[2] DCI:NREF_TERM_SPLIT[0] DCI:TEST_ENABLE[1] LVDS:LVDSBIAS[6] DCI:PMASK_TERM_SPLIT[2]
22 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[9] HCLK_IOI:MUX.RCLK2[0] HCLK_IOI:BUF.HCLK2 BUFR0:MUX.I[15] BUFR0:MUX.I[6] HCLK_IOI:MUX.RCLK2[3] BUFR0:ENABLE - - HCLK_IOI:DELAY.IOCLK7 BUFIO3:ENABLE IDELAYCTRL:HIGH_PERFORMANCE_MODE BUFO0:MUX.I[0] - - LVDS:LVDSBIAS[7] DCI:PMASK_TERM_SPLIT[1]
21 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[10] HCLK_IOI:MUX.RCLK1[0] HCLK_IOI:BUF.HCLK1 BUFR0:MUX.I[13] BUFR0:MUX.I[5] HCLK_IOI:MUX.RCLK2[1] BUFR0:BUFR_DIVIDE[0] - - - BUFIO3:MUX.I[0] - - - DCI:PREF_TERM_SPLIT[2] LVDS:LVDSBIAS[8] DCI:PMASK_TERM_SPLIT[0]
20 - - - - - - - - - - - - - - - - - - - - - - - - - - - IDELAYCTRL:MUX.REFCLK[11] HCLK_IOI:MUX.RCLK0[0] HCLK_IOI:BUF.HCLK0 BUFR0:MUX.I[12] BUFR0:MUX.I[4] HCLK_IOI:MUX.RCLK2[2] BUFR0:BUFR_DIVIDE[3] - - HCLK_IOI:DELAY.IOCLK3 BUFIO2:MUX.I[0] - - DCI:NREF_OUTPUT_HALF[2] DCI:PREF_TERM_SPLIT[1] LVDS:LVDSBIAS[9] DCI:NMASK_TERM_SPLIT[5]
19 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK5 BUFR0:MUX.I[11] BUFR0:MUX.I[3] HCLK_IOI:MUX.RCLK1[3] BUFR0:BUFR_DIVIDE[2] - - - BUFIO3:DQSMASK_ENABLE - - DCI:NREF_OUTPUT_HALF[1] DCI:PREF_TERM_SPLIT[0] LVDS:LVDSBIAS[10] DCI:NMASK_TERM_SPLIT[4]
18 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK4 BUFR0:MUX.I[10] BUFR0:MUX.I[2] HCLK_IOI:MUX.RCLK1[1] BUFR0:BUFR_DIVIDE[1] - - HCLK_IOI:DELAY.IOCLK2 BUFIO2:DQSMASK_ENABLE - - DCI:NREF_OUTPUT_HALF[0] DCI:PREF_OUTPUT_HALF[2] LVDS:LVDSBIAS[11] DCI:NMASK_TERM_SPLIT[3]
17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK3 BUFR0:MUX.I[9] BUFR0:MUX.I[1] HCLK_IOI:MUX.RCLK1[2] - - - - BUFIO2:ENABLE - - DCI:NREF_OUTPUT[1] DCI:PREF_OUTPUT_HALF[1] LVDS:LVDSBIAS[12] DCI:NMASK_TERM_SPLIT[2]
16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK2 BUFR0:MUX.I[8] BUFR0:MUX.I[0] HCLK_IOI:MUX.RCLK0[3] - - - HCLK_IOI:DELAY.IOCLK6 HCLK_IOI:BUF.IOCLK6 - - DCI:NREF_OUTPUT[0] DCI:PREF_OUTPUT_HALF[0] LVDS:LVDSBIAS[13] DCI:NMASK_TERM_SPLIT[1]
15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK1 - - HCLK_IOI:MUX.RCLK0[1] - - - - HCLK_IOI:BUF.PERF1 - - DCI:PREF_TERM_VCC[1] DCI:PREF_OUTPUT[1] LVDS:LVDSBIAS[14] DCI:NMASK_TERM_SPLIT[0]
14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HCLK_IOI:BUF.RCLK0 - - HCLK_IOI:MUX.RCLK0[2] - - - HCLK_IOI:BUF.PERF2 HCLK_IOI:BUF.PERF3 - - DCI:PREF_TERM_VCC[0] DCI:PREF_OUTPUT[0] LVDS:LVDSBIAS[15] DCI:PMASK_TERM_VCC[0]
13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BUFIO0:DQSMASK_ENABLE 0.37.26
BUFIO0:ENABLE 0.37.25
BUFIO1:DQSMASK_ENABLE 0.37.27
BUFIO1:ENABLE 0.37.30
BUFIO2:DQSMASK_ENABLE 0.37.18
BUFIO2:ENABLE 0.37.17
BUFIO3:DQSMASK_ENABLE 0.37.19
BUFIO3:ENABLE 0.37.22
BUFR0:ENABLE 0.33.22
BUFR1:ENABLE 0.33.27
DCI:CASCADE_FROM_ABOVE 0.40.27
DCI:CASCADE_FROM_BELOW 0.40.28
DCI:DYNAMIC_ENABLE 0.42.29
DCI:ENABLE 0.42.31
DCI:QUIET 0.41.31
HCLK_IOI:BUF.HCLK0 0.29.20
HCLK_IOI:BUF.HCLK1 0.29.21
HCLK_IOI:BUF.HCLK10 0.29.30
HCLK_IOI:BUF.HCLK11 0.29.31
HCLK_IOI:BUF.HCLK2 0.29.22
HCLK_IOI:BUF.HCLK3 0.29.23
HCLK_IOI:BUF.HCLK4 0.29.24
HCLK_IOI:BUF.HCLK5 0.29.25
HCLK_IOI:BUF.HCLK6 0.29.26
HCLK_IOI:BUF.HCLK7 0.29.27
HCLK_IOI:BUF.HCLK8 0.29.28
HCLK_IOI:BUF.HCLK9 0.29.29
HCLK_IOI:BUF.IOCLK4 0.37.24
HCLK_IOI:BUF.IOCLK5 0.37.31
HCLK_IOI:BUF.IOCLK6 0.37.16
HCLK_IOI:BUF.IOCLK7 0.37.23
HCLK_IOI:BUF.PERF0 0.36.23
HCLK_IOI:BUF.PERF1 0.37.15
HCLK_IOI:BUF.PERF2 0.36.14
HCLK_IOI:BUF.PERF3 0.37.14
HCLK_IOI:BUF.RCLK0 0.29.14
HCLK_IOI:BUF.RCLK1 0.29.15
HCLK_IOI:BUF.RCLK2 0.29.16
HCLK_IOI:BUF.RCLK3 0.29.17
HCLK_IOI:BUF.RCLK4 0.29.18
HCLK_IOI:BUF.RCLK5 0.29.19
HCLK_IOI:BUF.VOCLK0 0.39.28
HCLK_IOI:BUF.VOCLK1 0.39.29
HCLK_IOI:DELAY.IOCLK0 0.36.27
HCLK_IOI:DELAY.IOCLK1 0.36.29
HCLK_IOI:DELAY.IOCLK2 0.36.18
HCLK_IOI:DELAY.IOCLK3 0.36.20
HCLK_IOI:DELAY.IOCLK4 0.36.25
HCLK_IOI:DELAY.IOCLK5 0.36.31
HCLK_IOI:DELAY.IOCLK6 0.36.16
HCLK_IOI:DELAY.IOCLK7 0.36.22
HCLK_IOI:UNUSED.RCLK0 0.28.26
HCLK_IOI:UNUSED.RCLK1 0.28.27
HCLK_IOI:UNUSED.RCLK2 0.28.28
HCLK_IOI:UNUSED.RCLK3 0.28.29
HCLK_IOI:UNUSED.RCLK4 0.28.30
HCLK_IOI:UNUSED.RCLK5 0.28.31
IDELAYCTRL:HIGH_PERFORMANCE_MODE 0.38.22
non-inverted [0]
BUFIO0:MUX.I 0.37.28
CCIO 0
PERF1 1
BUFIO1:MUX.I 0.37.29
CCIO 0
PERF0 1
BUFIO2:MUX.I 0.37.20
CCIO 0
PERF3 1
BUFIO3:MUX.I 0.37.21
CCIO 0
PERF2 1
BUFO0:MUX.I 0.39.24 0.39.23 0.39.30 0.39.22
VOCLK0 0 0 0 0
VOCLK0_S 0 0 1 1
VOCLK0_N 1 1 0 0
BUFO1:MUX.I 0.39.27 0.39.25 0.39.31 0.39.26
VOCLK1 0 0 0 0
VOCLK1_S 0 0 1 1
VOCLK1_N 1 1 0 0
BUFR0:BUFR_DIVIDE 0.33.20 0.33.19 0.33.18 0.33.21
BUFR1:BUFR_DIVIDE 0.33.30 0.33.29 0.33.28 0.33.31
BYPASS 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 0 1
4 0 1 1 1
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 1
BUFR0:MUX.I 0.30.22 0.30.23 0.30.21 0.30.20 0.30.19 0.30.18 0.30.17 0.30.16 0.31.23 0.31.22 0.31.21 0.31.20 0.31.19 0.31.18 0.31.17 0.31.16
BUFR1:MUX.I 0.30.30 0.30.31 0.30.29 0.30.28 0.30.27 0.30.26 0.30.25 0.30.24 0.31.31 0.31.30 0.31.29 0.31.28 0.31.27 0.31.26 0.31.25 0.31.24
NONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BUFIO0_I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
BUFIO1_I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
BUFIO2_I 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
BUFIO3_I 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
MGT0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
MGT1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
MGT2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
MGT3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
MGT4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
MGT5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
MGT6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
MGT7 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
MGT8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
MGT9 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
CKINT0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CKINT1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DCI:NMASK_TERM_SPLIT 0.43.20 0.43.19 0.43.18 0.43.17 0.43.16 0.43.15
DCI:PMASK_TERM_SPLIT 0.43.26 0.43.25 0.43.24 0.43.23 0.43.22 0.43.21
DCI:PMASK_TERM_VCC 0.43.31 0.43.30 0.43.29 0.43.28 0.43.27 0.43.14
non-inverted [5] [4] [3] [2] [1] [0]
DCI:NREF_OUTPUT 0.40.17 0.40.16
DCI:PREF_OUTPUT 0.41.15 0.41.14
DCI:PREF_TERM_VCC 0.40.15 0.40.14
DCI:TEST_ENABLE 0.41.23 0.40.31
non-inverted [1] [0]
DCI:NREF_OUTPUT_HALF 0.40.20 0.40.19 0.40.18
DCI:NREF_TERM_SPLIT 0.40.25 0.40.24 0.40.23
DCI:PREF_OUTPUT_HALF 0.41.18 0.41.17 0.41.16
DCI:PREF_TERM_SPLIT 0.41.21 0.41.20 0.41.19
non-inverted [2] [1] [0]
HCLK_IOI:MUX.RCLK0 0.32.16 0.32.14 0.32.15 0.28.20
HCLK_IOI:MUX.RCLK1 0.32.19 0.32.17 0.32.18 0.28.21
HCLK_IOI:MUX.RCLK2 0.32.22 0.32.20 0.32.21 0.28.22
HCLK_IOI:MUX.RCLK3 0.32.25 0.32.23 0.32.24 0.28.23
HCLK_IOI:MUX.RCLK4 0.32.28 0.32.26 0.32.27 0.28.24
HCLK_IOI:MUX.RCLK5 0.32.31 0.32.29 0.32.30 0.28.25
NONE 0 0 0 0
VRCLK0_N 0 0 0 1
VRCLK0 0 0 1 1
VRCLK1_N 0 1 0 1
VRCLK1 0 1 1 1
VRCLK0_S 1 0 0 1
VRCLK1_S 1 1 0 1
IDELAYCTRL:MODE 0.38.26 0.38.30 0.38.28 0.38.29
NONE 0 0 0 0
DEFAULT 0 0 1 1
FULL_0 0 1 0 1
FULL_1 1 1 0 1
IDELAYCTRL:MUX.REFCLK 0.27.20 0.27.21 0.27.22 0.27.23 0.27.24 0.27.25 0.27.26 0.27.27 0.27.28 0.27.29 0.27.30 0.27.31
HCLK0 0 0 0 0 0 0 0 0 0 0 0 1
HCLK1 0 0 0 0 0 0 0 0 0 0 1 0
HCLK2 0 0 0 0 0 0 0 0 0 1 0 0
HCLK3 0 0 0 0 0 0 0 0 1 0 0 0
HCLK4 0 0 0 0 0 0 0 1 0 0 0 0
HCLK5 0 0 0 0 0 0 1 0 0 0 0 0
HCLK6 0 0 0 0 0 1 0 0 0 0 0 0
HCLK7 0 0 0 0 1 0 0 0 0 0 0 0
HCLK8 0 0 0 1 0 0 0 0 0 0 0 0
HCLK9 0 0 1 0 0 0 0 0 0 0 0 0
HCLK10 0 1 0 0 0 0 0 0 0 0 0 0
HCLK11 1 0 0 0 0 0 0 0 0 0 0 0
IDELAYCTRL:RESET_STYLE 0.38.31
V5 0
V4 1
INTERNAL_VREF:VREF 0.40.30 0.40.29 0.41.29 0.41.24 0.41.30 0.40.26
OFF 0 0 0 0 0 0
600 0 0 0 0 1 1
750 0 0 0 1 0 1
900 0 0 1 0 0 1
1100 0 1 0 0 0 1
1250 1 0 0 0 0 1
LVDS:LVDSBIAS 0.41.28 0.42.14 0.42.15 0.42.16 0.42.17 0.42.18 0.42.19 0.42.20 0.42.21 0.42.22 0.42.23 0.42.24 0.42.25 0.42.26 0.42.27 0.42.28 0.42.30
non-inverted [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]

Tables

Device IODELAY:DEFAULT_IDELAY_VALUE
[4] [3] [2] [1] [0]
xc6vlx760 1 1 0 1 1
xc6vlx760l 1 1 0 1 1
xc6vlx75t 1 0 0 1 1
xc6vlx75tl 1 0 0 1 1
xc6vcx75t 1 0 0 1 1
xc6vlx130t 1 0 1 1 0
xq6vlx130t 1 0 1 1 0
xc6vlx130tl 1 0 1 1 0
xq6vlx130tl 1 0 1 1 0
xc6vcx130t 1 0 1 1 0
xc6vlx195t 1 1 0 1 1
xc6vlx195tl 1 1 0 1 1
xc6vcx195t 1 1 0 1 1
xc6vlx240t 1 1 0 1 1
xq6vlx240t 1 1 0 1 1
xc6vlx240tl 1 1 0 1 1
xq6vlx240tl 1 1 0 1 1
xc6vcx240t 1 1 0 1 1
xc6vlx365t 0 1 1 0 0
xc6vlx365tl 0 1 1 0 0
xc6vlx550t 1 0 1 1 0
xq6vlx550t 1 0 1 1 0
xc6vlx550tl 1 0 1 1 0
xq6vlx550tl 1 0 1 1 0
xc6vsx315t 1 0 0 1 0
xq6vsx315t 1 0 0 1 0
xc6vsx315tl 1 0 0 1 0
xq6vsx315tl 1 0 0 1 0
xc6vsx475t 1 1 0 0 0
xq6vsx475t 1 1 0 0 0
xc6vsx475tl 1 1 0 0 0
xq6vsx475tl 1 1 0 0 0
xc6vhx250t 1 0 0 1 0
xc6vhx255t 0 1 1 0 0
xc6vhx380t 1 0 0 1 0
xc6vhx565t 1 1 0 0 0
Name IOSTD:PDRIVE IOSTD:NDRIVE
[5] [4] [3] [2] [1] [0] [5] [4] [3] [2] [1] [0]
BLVDS_25 1 0 1 1 0 0 1 0 1 1 0 0
HSTL_I 0 1 1 1 1 0 0 0 1 0 0 1
HSTL_II 1 1 1 0 1 0 0 1 0 0 0 1
HSTL_III 0 1 1 1 1 0 0 1 1 0 1 0
HSTL_III_18 0 1 0 1 1 0 0 1 1 0 1 0
HSTL_III_DCI 0 1 1 1 1 0 0 1 1 0 1 0
HSTL_III_DCI_18 0 1 0 1 1 0 0 1 1 0 1 0
HSTL_II_18 1 0 1 0 1 1 0 1 0 0 0 1
HSTL_II_DCI 1 1 1 0 1 0 0 1 0 0 0 1
HSTL_II_DCI_18 1 0 1 0 1 1 0 1 0 0 0 1
HSTL_II_T_DCI 0 1 1 1 1 0 0 0 1 0 0 1
HSTL_II_T_DCI_18 0 1 0 1 1 0 0 0 1 0 0 1
HSTL_I_12 1 1 1 0 0 1 0 0 1 1 0 0
HSTL_I_18 0 1 0 1 1 0 0 0 1 0 0 1
HSTL_I_DCI 0 1 1 1 1 0 0 0 1 0 0 1
HSTL_I_DCI_18 0 1 0 1 1 0 0 0 1 0 0 1
LVCMOS12.2 0 0 1 1 1 1 0 0 0 0 1 1
LVCMOS12.4 0 1 1 1 0 1 0 0 0 1 1 0
LVCMOS12.6 1 0 1 0 1 0 0 0 1 0 0 1
LVCMOS12.8 1 1 1 0 0 1 0 0 1 1 0 0
LVCMOS15.12 1 0 1 1 1 1 0 0 1 1 1 0
LVCMOS15.16 1 1 1 1 1 1 0 1 0 0 1 1
LVCMOS15.2 0 0 1 0 0 0 0 0 0 0 1 1
LVCMOS15.4 0 1 0 0 0 0 0 0 0 1 0 1
LVCMOS15.6 0 1 1 0 0 0 0 0 0 1 1 1
LVCMOS15.8 1 0 0 0 0 0 0 0 1 0 1 0
LVCMOS18.12 0 1 1 1 1 1 0 0 1 1 0 0
LVCMOS18.16 1 0 0 1 1 1 0 1 0 0 0 0
LVCMOS18.2 0 0 0 1 0 1 0 0 0 0 1 0
LVCMOS18.4 0 0 1 0 1 0 0 0 0 1 0 0
LVCMOS18.6 0 0 1 1 1 1 0 0 0 1 1 0
LVCMOS18.8 0 1 0 1 0 1 0 0 1 0 0 0
LVCMOS25.12 0 1 0 1 1 1 0 0 1 1 1 1
LVCMOS25.16 0 1 1 1 1 1 0 1 0 0 0 1
LVCMOS25.2 0 0 0 1 0 0 0 0 0 0 1 0
LVCMOS25.24 1 0 1 1 1 1 0 1 1 0 1 0
LVCMOS25.4 0 0 1 0 0 0 0 0 0 1 0 0
LVCMOS25.6 0 0 1 1 0 0 0 0 0 1 1 0
LVCMOS25.8 0 1 0 0 0 0 0 0 1 0 0 1
LVPECL_25 1 1 0 0 0 0 1 1 1 1 0 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0
SSTL15 1 0 0 1 0 0 0 0 1 0 1 0
SSTL15_DCI 1 0 0 1 0 0 0 0 1 0 1 0
SSTL15_T_DCI 1 0 0 1 0 0 0 0 1 0 1 0
SSTL18_I 0 1 0 0 1 1 0 0 1 0 0 0
SSTL18_II 1 1 1 0 0 0 0 1 0 1 1 0
SSTL18_II_DCI 0 1 1 0 1 0 0 0 1 0 1 1
SSTL18_II_T_DCI 0 0 1 1 1 1 0 0 0 1 1 0
SSTL18_I_DCI 0 0 1 1 1 1 0 0 0 1 1 0
SSTL2_I 0 0 1 1 0 1 0 0 0 1 1 1
SSTL2_II 1 0 0 0 1 1 0 1 0 1 0 0
SSTL2_II_DCI 0 1 0 0 0 1 0 0 1 0 0 1
SSTL2_II_T_DCI 0 0 1 0 0 1 0 0 0 1 0 1
SSTL2_I_DCI 0 0 1 0 0 1 0 0 0 1 0 1
VR 0 0 0 0 0 0 0 0 0 0 0 0
Name IOSTD:PSLEW IOSTD:NSLEW
[4] [3] [2] [1] [0] [4] [3] [2] [1] [0]
BLVDS_25 0 0 1 0 1 1 1 1 1 1
HSLVDCI_15 0 1 1 1 1 0 0 1 1 1
HSLVDCI_18 0 0 0 0 0 1 1 1 1 1
HSLVDCI_25 0 0 0 0 0 1 1 1 1 1
HSTL_I 0 1 0 0 1 1 0 1 1 1
HSTL_II 0 0 0 1 1 1 1 1 0 0
HSTL_III 0 0 0 0 0 1 0 1 1 1
HSTL_III_18 0 0 0 0 0 1 1 1 1 1
HSTL_III_DCI 0 0 0 0 0 1 1 1 1 0
HSTL_III_DCI_18 0 0 0 0 1 1 1 1 1 1
HSTL_II_18 0 0 0 1 0 0 1 0 0 1
HSTL_II_DCI 0 1 1 1 1 1 1 1 1 1
HSTL_II_DCI_18 0 1 1 1 0 0 1 1 1 1
HSTL_II_T_DCI 1 0 1 0 0 1 1 1 1 0
HSTL_II_T_DCI_18 0 0 1 1 1 0 0 1 1 1
HSTL_I_12 0 0 1 1 1 1 0 0 0 0
HSTL_I_18 0 0 1 1 1 1 0 1 1 1
HSTL_I_DCI 1 0 1 0 0 1 1 1 1 0
HSTL_I_DCI_18 0 0 1 1 1 0 0 1 1 1
LVCMOS12.2.FAST 1 1 1 1 1 1 1 0 0 0
LVCMOS12.2.SLOW 0 0 0 0 1 0 0 0 0 1
LVCMOS12.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS12.4.SLOW 0 0 0 0 1 0 0 0 0 1
LVCMOS12.6.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS12.6.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS12.8.FAST 1 1 0 0 1 1 1 1 1 1
LVCMOS12.8.SLOW 0 0 0 0 1 0 0 0 1 1
LVCMOS15.12.FAST 0 1 0 0 0 1 1 1 1 1
LVCMOS15.12.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS15.16.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS15.16.SLOW 0 0 0 0 1 0 0 1 1 1
LVCMOS15.2.FAST 1 1 1 1 1 0 0 0 0 1
LVCMOS15.2.SLOW 1 0 0 1 0 0 0 0 0 1
LVCMOS15.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS15.4.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS15.6.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS15.6.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS15.8.FAST 0 1 0 0 1 1 1 1 1 1
LVCMOS15.8.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS18.12.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS18.12.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS18.16.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS18.16.SLOW 0 0 0 0 1 0 0 1 1 1
LVCMOS18.2.FAST 1 0 0 0 1 1 1 1 1 1
LVCMOS18.2.SLOW 0 0 0 0 1 0 0 1 1 1
LVCMOS18.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS18.4.SLOW 0 0 0 0 1 0 0 1 0 0
LVCMOS18.6.FAST 0 0 1 1 1 1 1 1 1 1
LVCMOS18.6.SLOW 0 0 0 0 1 0 0 1 0 1
LVCMOS18.8.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS18.8.SLOW 0 0 0 0 1 0 0 1 0 1
LVCMOS25.12.FAST 0 0 1 1 0 1 1 1 1 1
LVCMOS25.12.SLOW 0 0 0 0 1 0 1 0 1 0
LVCMOS25.16.FAST 0 0 0 0 1 1 1 1 1 1
LVCMOS25.16.SLOW 0 0 0 0 0 0 0 1 0 1
LVCMOS25.2.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS25.2.SLOW 0 0 0 0 0 1 1 1 1 1
LVCMOS25.24.FAST 0 0 0 1 0 1 1 1 1 1
LVCMOS25.24.SLOW 0 0 0 0 1 1 0 1 0 0
LVCMOS25.4.FAST 1 1 1 1 1 1 1 1 1 1
LVCMOS25.4.SLOW 0 0 0 0 0 1 1 1 1 1
LVCMOS25.6.FAST 0 0 0 1 0 1 1 1 1 1
LVCMOS25.6.SLOW 0 0 0 0 1 0 1 0 1 0
LVCMOS25.8.FAST 0 0 0 0 1 1 1 1 1 1
LVCMOS25.8.SLOW 0 0 0 0 1 0 1 0 1 0
LVDCI_15 0 1 1 1 1 0 0 1 1 1
LVDCI_18 0 0 0 0 0 1 1 1 1 1
LVDCI_25 0 0 0 0 0 1 1 1 1 1
LVDCI_DV2_15 1 1 1 1 1 0 0 0 0 1
LVDCI_DV2_18 0 0 0 0 0 0 1 1 0 1
LVDCI_DV2_25 0 0 0 0 0 1 1 1 1 1
LVPECL_25 0 0 1 1 0 1 1 1 1 1
OFF 0 0 0 0 0 0 0 0 0 0
SSTL15 0 1 1 0 0 1 1 1 1 0
SSTL15_DCI 1 0 1 0 1 1 0 1 1 1
SSTL15_T_DCI 1 0 1 0 1 1 0 1 1 1
SSTL18_I 0 1 1 1 0 1 1 1 1 1
SSTL18_II 0 0 1 1 0 1 1 1 1 1
SSTL18_II_DCI 1 0 0 0 0 1 1 1 1 1
SSTL18_II_T_DCI 1 0 0 0 0 0 0 0 1 1
SSTL18_I_DCI 1 0 0 0 0 0 0 0 1 1
SSTL2_I 0 0 0 1 1 1 1 1 1 1
SSTL2_II 0 0 0 1 1 1 1 1 1 1
SSTL2_II_DCI 0 0 1 0 1 0 1 0 1 0
SSTL2_II_T_DCI 0 0 0 1 1 1 1 1 1 1
SSTL2_I_DCI 0 0 0 1 1 1 1 1 1 1
VR 1 1 1 1 1 1 1 1 1 1
Name IOSTD:OUTPUT_MISC
[3] [2] [1] [0]
BLVDS_25 0 0 0 0
HSLVDCI_15 0 0 0 0
HSLVDCI_18 0 0 0 0
HSLVDCI_25 0 0 0 0
HSTL_I 0 0 0 0
HSTL_II 0 0 0 0
HSTL_III 0 0 0 0
HSTL_III_18 0 0 0 0
HSTL_III_DCI 0 0 0 0
HSTL_III_DCI_18 0 0 0 0
HSTL_II_18 0 0 0 0
HSTL_II_DCI 0 0 0 0
HSTL_II_DCI_18 0 0 0 0
HSTL_II_T_DCI 0 0 0 0
HSTL_II_T_DCI_18 0 0 0 0
HSTL_I_12 1 0 0 0
HSTL_I_18 0 0 0 0
HSTL_I_DCI 0 0 0 0
HSTL_I_DCI_18 0 0 0 0
LVCMOS12 1 0 0 0
LVCMOS15 1 0 0 0
LVCMOS18 0 0 0 0
LVCMOS25 0 0 0 0
LVDCI_15 0 0 0 0
LVDCI_18 0 0 0 0
LVDCI_25 0 0 0 0
LVDCI_DV2_15 0 0 0 0
LVDCI_DV2_18 0 0 0 0
LVDCI_DV2_25 0 0 0 0
LVPECL_25 0 0 0 0
OFF 0 0 0 0
SSTL15 0 0 0 0
SSTL15_DCI 0 0 0 0
SSTL15_T_DCI 0 0 0 0
SSTL18_I 0 0 0 0
SSTL18_II 0 0 0 0
SSTL18_II_DCI 0 0 0 0
SSTL18_II_T_DCI 0 0 0 0
SSTL18_I_DCI 0 0 0 0
SSTL2_I 0 0 0 0
SSTL2_II 0 0 0 0
SSTL2_II_DCI 0 0 0 0
SSTL2_II_T_DCI 0 0 0 0
SSTL2_I_DCI 0 0 0 0
Name IOSTD:LVDS_T IOSTD:LVDS_C
[8] [7] [6] [5] [4] [3] [2] [1] [0] [8] [7] [6] [5] [4] [3] [2] [1] [0]
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT_HT_25 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0
OUTPUT_LVDSEXT_25 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0
OUTPUT_LVDS_25 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0
OUTPUT_RSDS_25 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0
TERM_DYNAMIC_HT_25 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0
TERM_DYNAMIC_LVDSEXT_25 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0
TERM_DYNAMIC_LVDS_25 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0
TERM_DYNAMIC_RSDS_25 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0
TERM_HT_25 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0
TERM_LVDSEXT_25 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0
TERM_LVDS_25 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0
TERM_RSDS_25 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0
Name IOSTD:LVDSBIAS
[16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
HT_25 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0
LVDSEXT_25 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0
LVDS_25 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSDS_25 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0
Name IOSTD:DCI:PREF_OUTPUT IOSTD:DCI:NREF_OUTPUT
[1] [0] [1] [0]
HSLVDCI_15 0 0 0 0
HSLVDCI_18 0 0 0 0
HSLVDCI_25 0 0 0 0
LVDCI_15 0 0 0 0
LVDCI_18 0 0 0 0
LVDCI_25 0 0 0 0
OFF 0 0 0 0
Name IOSTD:DCI:PREF_OUTPUT_HALF IOSTD:DCI:NREF_OUTPUT_HALF
[2] [1] [0] [2] [1] [0]
LVDCI_DV2_15 0 1 1 0 1 1
LVDCI_DV2_18 0 1 1 0 1 1
LVDCI_DV2_25 0 1 1 0 1 1
OFF 0 0 0 0 0 0
Name IOSTD:DCI:PREF_TERM_VCC IOSTD:DCI:PMASK_TERM_VCC
[1] [0] [5] [4] [3] [2] [1] [0]
HSTL_III_DCI 1 0 0 0 0 0 0 0
HSTL_III_DCI_18 1 0 0 0 0 0 0 0
OFF 0 0 0 0 0 0 0 0
Name IOSTD:DCI:PREF_TERM_SPLIT IOSTD:DCI:NREF_TERM_SPLIT IOSTD:DCI:PMASK_TERM_SPLIT IOSTD:DCI:NMASK_TERM_SPLIT
[2] [1] [0] [2] [1] [0] [5] [4] [3] [2] [1] [0] [5] [4] [3] [2] [1] [0]
HSTL_II_DCI 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0
HSTL_II_DCI_18 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0
HSTL_II_T_DCI 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0
HSTL_II_T_DCI_18 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0
HSTL_I_DCI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HSTL_I_DCI_18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSTL15_DCI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSTL15_T_DCI 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0
SSTL18_II_DCI 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0
SSTL18_II_T_DCI 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0
SSTL18_I_DCI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSTL2_II_DCI 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0
SSTL2_II_T_DCI 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0
SSTL2_I_DCI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0